Design and Characterization of Integrated Varactors for RF Applications I´n˜igo Gutie´rrez TECNUN, University of Navarra, Spain
Juan Mele´ndez CEIT and TECNUN, University of Navarra, Spain
Erik Herna´ndez CEIT and TECNUN, University of Navarra, Spain
Design and Characterization of Integrated Varactors for RF Applications
Design and Characterization of Integrated Varactors for RF Applications I´n˜igo Gutie´rrez TECNUN, University of Navarra, Spain
Juan Mele´ndez CEIT and TECNUN, University of Navarra, Spain
Erik Herna´ndez CEIT and TECNUN, University of Navarra, Spain
Copyright ß 2006
John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England Telephone (þ44) 1243 779777
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2006029954
British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library ISBN13 9780470025871 (HB) ISBN10 0470025875 (HB) Typeset in 10.5/13 pt Times by Thomson digital Printed and bound in Great Britain by TJ International, Padstow, Cornwall This book is printed on acidfree paper responsibly manufactured from sustainable forestry in which at least two trees are planted for each one used for paper production.
Contents List of Figures
xi
List of Tables
xv
Preface
xvii
Acknowledgements
xix
1 Introduction 1.1 Passive Elements 1.2 Figures of Merit of Varactors 1.2.1 Quality Factor 1.2.2 Tuning Range 1.2.3 Selfresonant Frequency (fR) 1.2.4 Effective Silicon Area 1.2.5 Absolute Capacity Value 1.3 Principal Types of Varactor Manufacture 1.3.1 Discrete Varactors 1.3.2 MEMS Varactors 1.3.3 BST Varactors 1.3.4 Integrated Varactors using Standard Technologies References
2 PNjunction Varactors 2.1 The Operating Principle of a PNjunction Varactor 2.1.1 Electrical Phenomena in a PNjunction Varactor 2.2 Different Architectures of PNjunction Varactors 2.2.1 Different Configurations of PNjunction Varactors 2.3 Influence of Bias Voltage on the Behaviour of a PNjunction Varactor 2.4 Influence of Geometric Parameters on the Behaviour of a PNjunction Varactor 2.4.1 Influence in the Variation of the Number of Islands 2.4.2 Influence of the Size of the Islands
1 1 3 3 4 4 5 5 5 5 6 7 8 8
11 11 13 15 17 19 20 20 21
vi
CONTENTS
2.4.3 Influence of the Distance Between Islands 2.4.4 Variation of the Size of the N Well 2.5 Influence of the Working Frequency on the Results 2.5.1 Influence of the Frequency on the Quality of a Varactor 2.5.2 Influence of the Frequency on the Capacitance of a Varactor 2.6 Comparison Between the Different Types of PNjunction Varactors 2.6.1 Comparison According to the Effective Silicon Area 2.6.2 Comparison According to the Quality Factor References
23 24 25 25 26 28 28 29 30
3 MOS Varactors 3.1 Operating Principles of an NMOS Varactor 3.1.1 Operating Ranges of the NMOS Varactor 3.1.2 Electrical Phenomena of an NMOS Varactor in Accumulation Mode 3.1.3 Electrical Phenomena of an NMOS Varactor in Depletion Mode 3.2 NMOS Varactors 3.2.1 Operating Ranges of the NMOS Varactor 3.3 Influence of the Operating Mode on an NMOS Varactor 3.4 Influence of Bias Voltage on the Behaviour of an NMOS Accumulation Varactor 3.5 Influence of Geometric Parameters on the Behaviour of an NMOS Varactor 3.5.1 Influence of the Variation of the Varactor Size 3.5.2 Influence of the Varactor Gate Length on its Performance 3.5.3 Influence of the Varactor Gate Width on its Performance 3.6 Influence of the Working Frequency on the Results References
31 31 32
4 Measurement Techniques for Integrated Varactors 4.1 Test System 4.2 Equipment Required for the OnWafer Testing of Integrated Varactors 4.2.1 Test Probes 4.2.2 Connectivity 4.3 Calibrating the Test System 4.4 Test Structures 4.4.1 Choosing the Test Structure Configuration
53 53
35 36 38 38 41 44 45 45 46 49 50 51
54 54 54 55 56 56
CONTENTS
4.4.2 Design of the Test Structures 4.4.3 Effects Introduced by the Test Structures 4.5 Test Structure DEembedding Techniques 4.5.1 Single–Short Structure 4.5.2 Single–Open Structure 4.5.3 Thru Structure 4.6 Characterization of Integrated Varactors 4.7 Test System Verification 4.7.1 Error Introduced by Positioning the Test Probes on the Pads 4.7.2 Error Introduced by the Calibration Reference Tolerances 4.7.3 Error Introduced by the Test Probes Heating up 4.7.4 Error Introduced by the Degradation of the Components 4.7.5 Analysis of the Results References
vii
57 59 61 62 63 64 66 67 67
68 69 70 72 72
5 Modeling Varactors 5.1 Introduction to the Modeling of Varactors 5.2 Modeling PNjunction Varactors 5.2.1 Value of Parameter L1 5.2.2 Value of Parameter C1 5.2.3 Value of Parameter R1 5.2.4 Value of Parameter L2 5.2.5 Value of Parameter C2 5.2.6 Value of Parameter R2 5.3 Modeling NMOS Varactors 5.3.1 Value of Parameter LG 5.3.2 Value of Parameter Cox 5.3.3 Value of Parameter CSi 5.3.4 Value of Parameter CGD 5.3.5 Value of Parameter R1 5.3.6 Value of Parameter RN2 5.3.7 Value of Parameter CNS 5.3.8 Value of Parameter LD=S
73 73 74 76 76 77 77 77 78 78 80 80 81 81 82 82 82 83
6 Design Rules for Integrated Varactors 6.1 Design Rules for PNjunction Integrated Varactors 6.2 Design Rules for NMOS Integrated Varactors 6.3 Comparison between Accumulation NMOS Varactors and PNjunction Varactors References
85 85 86 86 88
viii
CONTENTS
7 Design of a Demonstrator: Integrated VCO 7.1 Circuits Including Varactors 7.1.1 Influence of the Figures of Merit of the Varactor 7.1.2 Choosing the Demonstrator 7.2 General Considerations 7.2.1 Introduction 7.2.2 VCO Specifications 7.2.3 Active Circuit 7.2.4 Analysis of the CMOS Oscillator 7.3 Voltagecontrolled Oscillator 7.3.1 Design of the Tank Circuit 7.3.2 Design of the Oscillator 7.3.3 VCO Measurements 7.3.4 PLL Measurements References
89 89 90 96 96 96 97 100 103 106 106 113 115 119 122
Appendix 1: Geometric Characteristics of Varactors A1.1 Chip with the Varactors used in this Book A1.2 Geometrical Characteristics of the PNjuntion Varactors A1.2.1 Interdigit Varactors A1.2.2 Island Varactors A1.2.3 Matrix Varactors A1.3 Geometrical Characteristics of MOS Varactors
123 123 123 123 123 125 126
Appendix 2: Validation of the Predictions Provided by Equations of Chapter 5 A2.1 PNjunction Varactor A2.1.1 Inductance L1 A2.1.2 Capacitance C1 A2.1.3 Resistance R1 A2.1.4 Inductance L2 A2.1.5 Capacitance C2 A2.1.6 Resistance R2 A2.2 NMOS Varactors A2.2.1 Inductance LG A2.2.2 Capacitance Cox A2.2.3 Capacitance CSi A2.2.4 Capacitance CGD A2.2.5 Resistance R1 A2.2.6 Resistance RN2 A2.2.7 Capacitance CNS A2.2.8 Inductance LD=S
129 129 130 130 132 133 134 134 135 135 136 137 139 140 141 141 141
CONTENTS
Appendix 3: Measurement of Oscillator’s Performance A3.1 Design of the Layout A3.2 Measurement Setup A3.3 Oscillator and PLL Measurement A3.3.1 Analysis and Calculation of the Loop Filter A3.3.2 Printed Circuit Board Design A3.3.3 Measurement Setup
ix
143 143 148 150 150 150 152
Glossary
155
Index
157
List of Figures 1.1 1.2 1.3 1.4 2.1 2.2 2.3 2.4 2.5
2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 3.1
Simplified equivalent circuit of a varactor at high frequencies Nonintegrated varactors MEMS varactor (Etxeberria et al., 2005) BST varactor Cross section of a PNjunction varactor Inverse bias voltage: spreading of the depletion zone Carrier diffusion: spreading of the depletion zone with the increase in VR Electric fields in a PNjunction varactor Cross sections of the four types of PNjunction varactors: (a) PþN well; (b) Nþsubstrate P; (c) NþP well; (d) N wellsubstrate P Cross section of an island varactor Depletion zone in an island varactor Cross section of a matrix varactor Depletion zone on a matrix varactor Layout of an interdigit varactor Variation of the quality factor with the bias voltage Variation of the capacitance when varying the number of islands on a PNjunction varactor Variation in capacitance with the variation of the length of the islands Influence of the variation of the width of islands on an interdigit varactor Variation in Q in accordance with the size of the varactor Influence of the distance between islands Effect of the buried layer on a PNjunction varactor Variation of capacitance when the size of the N well is increased Variation of the quality factor with the frequency Resonant frequency in a PNjunction varactor Variation in fr in accordance with the size of the varactor Cross section of an NMOS varactor
5 6 7 8 12 12 13 13
15 17 17 18 18 19 19 20 21 22 23 23 24 25 26 26 28 32
xii
3.2
3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13
LIST OF FIGURES
Total capacitance between the gate and the substrate in accordance with the voltage between terminals (VGS ) NMOS varactor working in accumulation mode NMOS varactor working in depletion mode Electrical and magnetic phenomena in an NMOS varactor in accumulation mode Illustration of the effects appearing in an NMOS varactor in depletion mode Diagram of an NMOS varactor Typical curve of an NMOS varactor with gate (G), drain (D) and bulk (B) connected together Route of the carriers in an NMOS varactor Typical capacitance of the NMOS varactor (BDS) in accordance with voltage VBG Different operating modes of an NMOS varactor Influence of the operating mode Capacitances in an accumulation NMOS Capacitances in an inversion NMOS Variation of the quality factor with the bias voltage in an NMOS varactor Scalability of NMOS accumulation varactors Influence of the gate length with the bias voltage Variation in gate length Simplified model of the capacitances of an NMOS accumulation varactor Variation of the gate width with the bias voltage Variation of the capacitance with the bias voltage for a different number of metal layers Influence of metalization on resonant frequency ACP 40 test probes Test system Test with the device in series Structure of a pad implemented in a threemetal CMOS technology Pads and guard ring of a test structure Test structure Test structure impedance model Simplified impedance model of a test structure Transfer of the reference plane Deembedding structures Singleshort structure Singleshort structure impedance model Single–open structure
33 33 34 35 36 38 39 39 40 42 42 42 43 44 45 46 47 48 49 50 51 54 55 56 57 58 59 59 61 61 62 62 63 63
LIST OF FIGURES
4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 5.1 5.2 5.3 5.4 6.1 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 A1.1 A1.2 A1.3
Single–open structure impedance model Thru structure Thru structure impedance model Complete deembedding process Modification of the S parameter values using deembedding techniques Error introduced by the positioning of the test probes Error introduced by the calibration reference Errors introduced by the test probes heating up Error from component degradation Valid tests on a component Electric model of a PNjunction varactor Simplified electric model of a PNjunction varactor Electric model of an accumulation NMOS varactor Simplified electric model of an accumulation NMOS varactor Comparison of Var M2 and Var 2 Circuit diagrams of two passive BPFs Variation of the insertion loss and bandwidth Simplified schematic of a selective gain amplifier Simplified schematic of a VCO Frequency spectrum of the ideal and real output of an oscillator Block diagram of the ASCC Possible applications of the ASCC TV tuner Different biasing modes in a CMOS oscillator Equivalent highfrequency circuit of the CMOS oscillator Microphotograph of the inductor Modified model for the inductor Microphotograph of the varactor Estimated and measured capacitance variation Transformation of the equivalent conductance of the tank Tank circuit simulation schematic Simulation of the tank circuit conductance Microphotograph of the oscillator Oscillation frequency versus varactor control voltage Oscillator output power vs frequency Measured oscillator phase noise Photographs of the PCB with its components PLL output spectrum PLL phase noise test results PLL output power vs frequency Microphotograph of the varactors used in this book Microphotograph of the interdigit PNjunction varactors Microphotgraph of the island PNjunction varactors
xiii
64 64 65 65
66 68 69 70 71 71 74 75 78 80 87 90 91 92 94 95 97 98 103 103 107 108 110 111 112 113 113 116 117 117 118 119 120 120 121 124 125 125
xiv
A1.4 A1.5 A2.1 A2.2 A2.3 A2.4 A2.5 A2.6 A2.7 A2.8 A2.9 A2.10 A2.11 A2.12 A2.13 A2.14 A2.15 A2.16 A2.17 A2.18 A2.19 A2.20 A2.21 A3.1 A3.2 A3.3 A3.4 A3.5 A3.6 A3.7 A3.8 A3.9 A3.10
LIST OF FIGURES
Microphotograph of the matrix PNjunction varactors Microphotograph of the MOS varactors Var 1 model parameters L1 _measured versus L1 _analytic C1 parameter variation with the biasing voltage of Var 5 C1 _measured versus C1 _analytic R1 parameter variation with the biasing voltage of Var 5 R1 _measured versus R1 _analytic L2 _measured versus L2 _analytic C2 _measured versus C2 _analytic R2 _measured versus R2 _analytic Var M1 parameters model LG _measured versus LG _analytic Cox _measured versus Cox _analytic CSi parameter variation with the bias voltage of Var M2 CSi parameter variation with the bias voltage of Var M2 CSi _measured versus CSi _analytic CGD _measured versus CGD _analytic R1 parameter variation with the bias voltage of Var M2 R1 _measured versus R1 _analytic RN2 _measured versus RN2 _analytic CNS _measured versus CNS _analytic LD=S _measured versus LD=S _analytic Layout of the tank circuit Resistances included due to parasitic effects Layout of the VCO Lateral view of the output pads Layout of the VCO transistors Block diagram of the measurement setup Software for loop filter calculation Top layer of the PCB Bottom layer of the PCB PCB measurement setup
126 127 130 131 131 132 132 133 133 134 135 136 137 137 138 138 139 139 140 140 141 142 142 144 145 146 147 147 148 151 151 152 152
List of Tables 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3.1 3.2 3.3 3.4 4.1 6.1 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 A1.1 A1.2 A1.3
Specifications of the four types of PN junctions Variation of the tuning range and quality with the number of islands Variation of the tuning range and quality with the length of the islands Variation of the quality and tuning range with the distance between islands Variation of the tuning range and quality with the size of the N well Table comparing varactors occupying the same area Table comparing varactors for the same maximum capacitance value Influence of the operating mode on the quality factor and tuning range Variation of the quality factor and tuning range with the number of transistors Influence of gate length on the tuning range and on quality Influence of metallization on the quality factor and the tuning range Typical test deviations Tuning range and quality factor of Var M2 and Var 2 Figures of merit of the ASCC Figures of merit of the VCO Geometrical data of the balanced coil design Measured data of the balanced inductor Geometrical figures of the varactor VCO simulation results Oscillator measurement results PLL measurement results Geometrical characteristics of the interdigit PNjunction varactors Geometrical characteristics of the island PNjunction varactors Geometrical characteristics of the matrix PNjunction varactors
16 21 22 24 25 29 29 44 46 49 51 72 87 98 99 107 108 110 115 118 121 124 125 125
xvi
A1.4 A2.1 A2.2 A3.1 A3.2
LIST OF TABLES
Geometrical characteristics of the MOS varactors Model parameters obtained through measurement for different PNjunction varactors Measurement values for NMOS varactor model Measurement setup components Measurement setup components
126 130 136 149 153
Preface This book introduces the reader to varactor design for RF applications in lowcost technologies (CMOS, BiCMOS and SiGe) at different levels. It initially describes the physical phenomena that take place in the different types of variable capacitor structures currently available in standard integrated circuit fabrication processes. For a better understanding, schematic cross sections of a typical wafer illustrating the electric and magnetic field distributions have been included. Different architectures have also been described and multiple experimental results are given to characterize the different options. One key section of this book is dedicated to the description of the most important design rules to consider when dealing with the optimization of the performance of an integrated varactor. Design rules for the PN and MOStype varactors are extensively described and compared. The experience of different RF IC designers has been summarized in this book to provide the reader with practical knowledge to employ when dealing with challenging VCO designs, etc. In this book some wide band electrical models (up to 5 GHz) are derived which enable the prediction of their performance in an accurate way. Moreover these models are based on physical dimensions and on the properties of the fabrication processes which provides additional information that is really valuable at the design stage. This issue, which has not been addressed by any other author so far, is particularly relevant when the application requires large bandwidths such as the latest communication wireless networks are demanding. After this the authors focus the following chapter on characterization methodology. One specific methodology for integrated varactors is proposed for accurate measurements. It covers the design of onwafer measurement structures, the calibration process and the detailed description of the equipment required. One really interesting feature of this book is that not only are deembedding techniques explained in detail but also the confidence level
xviii
PREFACE
and the uncertainty associated with the test setup is analysed. Once again highly technical issues are solved in a practical way and described in detail so that any RF IC designer can acquire this specific knowledge. Finally, a voltage controlled oscillator (VCO) is presented as a practical example where the knowledge on optimized integrated varactors contained in this book has been employed. This last chapter includes every aspect relating to the varactor in the VCO, such as a description of its influence on the phase noise, the LC tank design and key topics regarding the layout and measurement techniques.
Acknowledgements The authors would like to acknowledge the Consejerı´a de Educacio´n, Universidades e Investigacio´n, the Consejerı´a de Industria, Comercio y Turimo del Gobierno Vasco and the Diputacio´n de Guipu´zcoa for having supported the research group of TECNUN (University of Navarra) and CEITIK4 who acquired the experience and knowledge contained in this book. The authors would like to express their gratitude to their colleagues in the IUMA research centre for their enthusiasm and support in the research of integrated passive elements for RF applications. Last but not least special thanks also go to all the staff of CEITIK4 and TECNUN (University of Navarra), especially to the colleagues in Miramo´n (Andre´s, Joaquı´n, Guillermo, Roc, Jaime, Manu, Nekane, etc. . .) for their support in all the stages involved in the preparation of this book.
1 Introduction This book is focused on the design and characterization of integrated varactors. A varactor is a voltagevariable capacitor; in other words, the value of its capacitance changes in accordance with the voltage applied to it. Chapter 1 looks at the general concepts of an integrated varactor. Chapter 2 analyses the operating principle of integrated PNjunction varactors and the tools used for their design. Chapter 3 continues along the same lines and looks at MOS varactors. After the different types of varactors have been analysed, Chapter 4 offers a method for their characterization, Chapter 5 looks at the models of varactor and Chapter 6 gives details of the design rules resulting from the work of the previous chapters. Finally, Chapter 7 presents the design of different circuits that use varactors for correct operation, including the design of a voltagecontrolled oscillator with a varactor in its LC tank.
1.1 PASSIVE ELEMENTS As a varactor is a voltagevariable capacitor, varactors are passive elements. A passive element is one that can only store or dissipate energy. An active element is one that provides energy to the signals travelling through it. Passive elements can be separated into two large groups: linear elements and nonlinear elements. Linear passive elements mainly include resistors, inductors, capacitors and transformers, which either dissipate or store energy. Nonlinear elements mainly include diodes and varactors. Diodes are characterized by their I–V curve and varactors by their C–V curve and varactors are the subject matter of this book.
Design and Characterization of Integrated Varactors for RF Applications and E. Herna´ndez # 2006 John Wiley & Sons, Ltd
´I. Gutie´rrez, J. Mele´ndez
2
INTRODUCTION
Desoer (1969) gives a defining inequation of passive components. A oneport element with a voltage v(t) and a current i(t) is said to be passive when it fulfils the following equation: Z
t
vðtÞ iðtÞ dt þ eðt0 Þ 0
ð1:1Þ
t0
where eðt0 Þ is the energy stored by the element at the instant t0 . To analyse the passivity of an element at high frequencies, it is more appropriate to analyse the Sparameter matrix when energy is applied to one of its ports (Carlin, 1964). The power dissipated on one of the ports of the element is given by: Pk ¼ Pik Prk
ð1:2Þ
where the subscript i indicates incident power and r indicates reflected power. In terms of reflected waves (b) and incident waves (a), we have the following: bk Pk ¼ ak ak bk
ð1:3Þ
bk represent the conjugate of the incident and reflected waves where ak and on port k, respectively. The sum of the powers of all the ports gives the following: P¼
n X
T
Pk ¼ aT a b b:
ð1:4Þ
k¼1
By the definition of Sparameters, the vector b is equal to Sa, where S represents the Sparameter matrix. Then: T
T
S a ¼ aT ðI S SÞ a ¼ aT Q a P ¼ aT a aT S
ð1:5Þ
where Q is the dissipation matrix. Mention must be made of the fact that: T ¼ IT ðS T SÞT ¼ I S T S ¼ Q Q
ð1:6Þ
Therefore, it can be said that the matrix Q is a Hermitian matrix. By the deﬁnition of passivity: P ¼ aT Q a 0:
ð1:7Þ
FIGURES OF MERIT OF VARACTORS
3
Therefore, if the matrix Q is positive defined or positive semidefined, the Smatrix corresponds to a passive network. This last condition can be deduced intuitively (Niknejaud, 2001). The elements of the Smatrix diagonal represent the reﬂection coefﬁcients when the remaining ports are matched. The other components of the matrix represent the transmission coefﬁcients under matching conditions. On a passive network, the conservation of energy implies that the reflected and transmitted power on one of the ports must be less than or equal to the incident power. In other words, all the elements of the matrix must have a value that is equal to or less than the unit.
1.2 FIGURES OF MERIT OF VARACTORS The two most important figures of merit in the case of varactors are the quality factor (Q) and the tuning range (TR). Other parameters of importance include the selfresonant frequency, maximum capacitance and the effective silicon area. 1.2.1 Quality Factor The quality factor measures element behaviour taking into account both stored and lost energy. The most common definition of the quality factor is the ratio between the absolute value of the negative imaginary part and the real part of the reflection parameter y11 (Ashby et al., 1996; Molnar et al., 2002). Q¼
jImagðy11 Þj Reðy11 Þ
ð1:8Þ
The value of y11 is obtained from the Sparameters of the passive element, in this case, a varactor. The imaginary part of the reflection parameter represents the energy stored in the passive element, whereas the real part is the dissipated energy. Therefore, the quality factor can be defined as per Equation (1.9): Q ¼ 2p
jstored inductive E stored capacitive Ej : E lost per cycle
ð1:9Þ
In accordance with Equation (1.9), the best results are obtained by minimizing the losses and making the energy stored by the device as great as
4
INTRODUCTION
possible. In this case, these energies are defined by maximas. If the varactor operates on a frequency that is remote from the resonance frequency, the stored inductive energy is insignificant: Q ¼ 2p
stored capacitive E ECmax ¼ 2p : E lost per cycle Edis
ð1:10Þ
The maximum energy stored in a varactor is defined as: 1 ECmax ¼ Cp Vp2 2
ð1:11Þ
where VP is the maximum voltage and Cp is the capacity of the varactor. The energy lost per cycle Edis will take different expressions depending on the simplified model of the varactor used, as shown below. 1.2.2 Tuning Range The tuning range can be considered the most important parameter regarding the varactor functionality. The variation range of the capacitance of a specific varactor is defined as the ratio between Cmax and Cmin , where Cmax and Cmin are the maximum and minimum capacitances, respectively. The aim is to achieve a wide capacitance variation range when working with a wide range of voltages. The tuning range is calculated as Cmax =Cmin or using the equation (Hernandez, 2002): TR ¼
1 Cmax Cmin Cmax Cmin ¼
2 Cmax þ Cmin Cmax þ Cmin 2
ð1:12Þ
1.2.3 Selfresonant Frequency ( fR) In principle, the behaviour of a varactor could be represented by the circuit shown in Figure 1.1; however, at high frequencies this circuit is not appropriate. The circuit in Figure 1.1 includes an inductor in series which takes into account the parasite inductance of the interconnection lines used in the varactor. In integrated varactors, the inductance value (Ls) is very low; however, at high frequencies, the said inductance can enter into resonance with the resistance in parallel and the variable capacitance and cancel its value. Obviously, the fR must be as high as possible to avoid the incorrect functioning of the varactor. As the capacitance is variable, the resonant frequency (fR) is a function of the supply voltage. To obtain a constant reference value, the fR
PRINCIPAL TYPES OF VARACTOR MANUFACTURE
5
Ls
Rs
Rp
C
Figure 1.1 Simplified equivalent circuit of a varactor at high frequencies.
corresponding to the minimum voltage value is usually taken (where it reaches Cmax ) (Pedersen, 2001). 1.2.4 Effective Silicon Area This parameter is measured in terms of capacitance by unit of area, where the typical unit is fF/mm2. The objective is to obtain a high effective silicon area as it may represent a considerable reduction in cost by reducing the size of the device (Aparicio and Hajimiri, 2002). 1.2.5 Absolute Capacity Value In the case of discrete designs, varactors are classified in accordance with their absolute capacitance value; each class is labelled with its corresponding useful frequency range. However, with integrated varactors, the capacitive properties are measured in terms of the Cmax =Cmin ratio. Therefore, only one of the two values (Cmax or Cmin ) needs to be specified. 1.3 PRINCIPAL TYPES OF VARACTOR MANUFACTURE 1.3.1 Discrete Varactors Owing to the lack of integrated varactors of acceptable quality, designers are forced to use discrete varactors. Figure 1.2 shows an example of a set
6
INTRODUCTION
Figure 1.2
Nonintegrated varactors.
of nonintegrated varactors with external connections. The use of discrete varactors requires the use of connections that are external to the circuit. This increases the size of the system and involves uncertainty as to the parasite effects of the said connections. However, the quality factors are very high.
1.3.2 MEMS Varactors Another alternative for the manufacture of varactors is a microelectromechanical system (MEMS). A MEMS is a miniaturized intelligent microsystem that integrates the sensor functions of process and/or action. The MEMS for RF, which includes varactors, uses air as dielectric material due to its lower losses in the RF frequency range, leading to very high quality factors Q. A surface micromachining process is commonly used to fabricate MEMS tunable capacitors. The present manufacture of MEMS varactors involves many lines of construction: MEMS varactors based on the micromachining of volume and a subsequent sticking process (Xiao et al., 2003); MEMS varactors using copper as sacrificial layers (Zou et al., 2001);
PRINCIPAL TYPES OF VARACTOR MANUFACTURE
Figure 1.3
7
MEMS varactor (Etxeberria et al., 2005).
MEMS varactors using nickel and gold as structural materials for the suspended plates and titanium as a sacrificial layer material (Gallant and Wood, 2004); MEMS varactors that use silicon wafer and pyrex wafer and developed by an anodic bonding process. Figure 1.3 shows a microphotograph of a varactor that is based on the reactive ion etching of silicon wafer and anodic bonding of silicon and pyrex wafers (Etxeberria et al., 2005). Although MEMS varactors have very high quality factors, they have two significant disadvantages: as they are not manufactured using a standard technology, the manufacturing cost is high and they also require connections external to the circuit. 1.3.3 BST Varactors These varactors are developed using the nonlinear dielectric tuneability of barium strontium titanate (BST) thin films. The goal of integrating passive thin films components with a BST varactor is to allow the development of extremely lowcost microwave components. The BST material was grown on cplane sapphire substrate using RF magnetron substrate. The films were sputtered from multiple ceramic targets consisting of varying ratios of barium and strontium (Chase et al., 2005).
8
INTRODUCTION Top plane BST Ground plane
Si
Figure 1.4 BST varactor.
The principal applications of these varactors are: tuneable bandpass filters; impedance matching networks; voltage control oscillators (VCOs). Figure 1.4 shows the schematic section of a BST varactor. 1.3.4 Integrated Varactors Using Standard Technologies There is much interest in the optimization of integrated varactors using standard CMOS, BiCMOS and SiGe manufacturing technologies with acceptable levels of quality, since this would enable RF designers to improve the performance levels of their RF circuits. Integrated varactors are passive components with a wide range of applications in the field of radiofrequency communications (RF). Depending on the type of application, the geometry of the varactors differs, giving rise to various classes of integrated varactors. This type of varactor is examined as follows. References Aparicio, R. and Hajimiri, A. (2002) Capacity limits and matching properties of integrated capacitors. IEEE Journal of Solid State Circuits, 37(3), 384–393. Ashby, K. B. et al. (1996) High Q inductors for wireless application in a complementary silicon bipolar process. IEEE Journal of SolidState Circuits, 31, 4–9. Carlin, H. J. (1964) An Introduction to Reciprocal and Nonreciprocal Circuits, PrenticeHall, Englewood Cliffs, USA. Chase, D. R. et al. (2005) Modeling the capacitivity nonlinearity in thin film BST varactors. IEEE Transactions on Microwave Theory and Techniques, 53(10), 3215–3220.
PRINCIPAL TYPES OF VARACTOR MANUFACTURE
9
Desoer, C. A. (1969) Basic Circuit Theory, McGraw Hill, New York, USA. Etxeberria, J.A. et al. (2005) Ultrathin metallic membranes to be used in tuneable RFMEMS volume capacitors. Proc. IEEE Sensor, 1, 448–451. Gallant, J. and Wood, D. (2004) The role of fabrication techniques on the performance of widely tuneable micromachined capacitors. Sensor and Actuators, A110, 423–431. Herna´ ndez, E. (2002) Integration of a TV frequency converter for SiGe 0.8 mm technology. Ph.D. Thesis, Tecnun, University of Navarra, Spain. Molnar, K. et al. (2002) MOS varactor modeling with a subcircuit utilizing the BSIM v3 model. IEEE Trans. Electron Devices, 49, 1206–1211. Niknejaud, A. M. (2000) Analysis, simulation and applications of passive devices on conductive substrates. Ph.D. Thesis, Berkeley, California, USA. Pedersen, E. (2001) RF CMOS varactors for wireless applications. Ph.D. Thesis, Aalborg, Denmark. Xiao, Z. et al. (2003) Micromachined variable capacitors with wide tuning range. Sensors and Actuators, A104, 299–305. Zou, J. et al. (2001) Development of a widetuningrange twoparallelplate tunable capacitor for integrated wireless communication systems. International Journal of RF and Microwave Computer Aided Engineering, 11(5), 322–329.
2 PNjunction Varactors 2.1 THE OPERATING PRINCIPLE OF A PNJUNCTION VARACTOR These varactors are based on the capacitance of a PN junction when it is inversely biased. This capacitance varies with the inverse voltage variation applied between the zones, one with a Ptype doping and the other with an Ntype doping. The real part of the impedance of the device corresponds to the resistance between the contacts, whereas the imaginary part is the capacitance of the PN zone (Maget, 2002). To minimize the resistive part of the impedance, Pþ and Nþ diffusions are introduced because their conductivity is greater and they are connected by a metal track. Figure 2.1 shows a cross section of a PNjunction varactor including the discrete elements that describe the electrical phenomena that take place when an AC voltage difference and a bias voltage (VR) are applied. It has three terminals: the anode, the cathode and the substrate. The latter is normally connected to ground. The behaviour of the varactor is related to the capacitance of the depletion zone (Cj), which is located between the Pþ diffusion and the N well. The losses are represented by the resistance in series, Rsj, and the resistance in parallel, Rpj. The resistance that represents the highest contribution is the resistance in series. Therefore, Rsj is the resistance that governs the quality factor Q. The behaviour of the capacitance that appears between the N and P zones can be compared with that of a virtual flatplate condenser. The nonconductive part is equivalent to the depletion zone and the conductive plates are equivalent to the limits of the said zone. These plates are charged with the
Design and Characterization of Integrated Varactors for RF Applications and E. Herna´ndez # 2006 John Wiley & Sons, Ltd
´I. Gutie´rrez, J. Mele´ndez
12
PNJUNCTION VARACTORS A
Cj
P+
Rpj
C
–
VR Rsj
N+
B
P+
N well
Depletion region
Bulk P–
Figure 2.1 Cross section of a PNjunction varactor.
electrons and defect electrons that are attracted when the inverse voltage is applied so that one plate is positively charged and the other is negatively charged, as shown in Figure 2.2. The depletion zone depends on the inverse voltage applied (VR). The greater the voltage, the wider the depletion zone, as shown in Figure 2.3. If the depletion zone is greater, it means that the virtual capacitance plates are further apart (d). Therefore the total capacitance will be lower: C¼e
A d
ð2:1Þ
An increase in the plate area (A) would lead to an increase in capacitance. Later we shall see that to obtain maximum capacitance, the largest depletion zone must be found, increasing the perimeter of the PN junction (Hernandez, 2002). As we have seen, varying the inverse voltage varies the depletion zone and, therefore, the capacitance, which is the purpose of all varactors.
P zone
Holes
Negative ion
N zone
Electrons
Positive ion
–
+
–
+
–
+
–
+
–
+
DIFFUSION
E
Figure 2.2
Inverse bias voltage: spreading of the depletion zone.
13
THE OPERATING PRINCIPLE OF A PNJUNCTION VARACTOR Internal E
+
––––
+++
–
+
––––
+++
–
+
––––
+++
–
+
––––
+++
+
––––
+++
– V–
–
V+
Holes
External E
Figure 2.3
Electrons
Carrier diffusion: spreading of the depletion zone with the increase in VR.
2.1.1 Electrical Phenomena in a PNjunction Varactor As shown in Figure 2.4, when an AC voltage is applied between the two terminals of the varactor, 11 electric fields and two magnetic fields appear as follows. B1(t) and B2(t) magnetic fields: these are generated by the variable current (AC signal) flowing along the metal tracks and the tracks that make up the contacts. They cause: inductive effects. E1(t) and E9(t) electric fields on the metal layers that make up the contacts of the two zones Nþ and Pþ: they are caused by the distribution of voltages on the metal layers. They cause: ohmic loss on the metal layer due to its resistivity. Metal layers
E9
E1 B1
B2
E8
E2
V fa
V fa
E7
E3 E6
N+ diffusion
P+ diffusion E5
E4
N well E10
E11
P substrate
Figure 2.4 Electric fields in a PNjunction varactor.
14
PNJUNCTION VARACTORS
E2(t) and E8(t) electric fields on the tracks: these are generated by the difference in voltage between the contact zone of the track with the diffusion zone and the metal layer. They cause: ohmic loss on the tracks due to their resistivity.
E3(t) and E7(t) electric fields in the diffusion Nþ and Pþ zones: these are generated by the distribution of voltages in these zones. They cause: ohmic loss in the Nþ and Pþ zones due to their resistivity. E4(t) electric field in the N well: this is generated by the difference of voltages between the diffusions and the substrate connected to ground. It produces: a coupling capacitance in the N well; ohmic loss due to the electric field that penetrates the N well. E5(t) electric field between the Pþ and Nþ zones: this is due to the difference in voltage between the two zones. It causes: ohmic loss in the N well due to the electric field that crosses it from the Nþ zone to Pþ. E6(t) electric field in the depletion zone: this produces a distribution of charges in this zone due to the bias voltage. It produces: junction capacitance; ohmic loss due to the depletion zone. E10(t) electric field between the N well and the substrate: this is due to the difference in voltage between the two zones. A depletion zone appears which causes: capacitance between the two zones; ohmic loss due to the depletion zone. E11(t) electric field in the substrate: this is due to the voltage gradient on all the substrate. It causes: capacitance on the substrate; ohmic loss due to the electric field that penetrates the resistive substrate.
15
DIFFERENT ARCHITECTURES OF PNJUNCTION VARACTORS
2.2 DIFFERENT ARCHITECTURES OF PNJUNCTION VARACTORS
With silicon technologies, there are four options for making a varactor of this type. Figure 2.5 shows cross sections of each option. For the four types, the device begins to work when an inverse voltage (VR) is applied between the anode (A) and the cathode (C). If an inverse voltage is applied on a Pþ=Nþ junction, a diode avalanche breakdown occurs. Therefore, an Ntype slab is maintained around Pþ and/or a Ptype slab type is maintained around Nþ. The following sections show that this slab must be minimal but greater than the size of the depletion zone to avoid diode avalanche breakdown. The Pþ=N well junction varactor (Figure 2.5 (a)) is based on the variation of the capacitance associated with the depletion zone between the diffusion A
+
VR
C
–
B
N+
P+
A
– VR
+
N+
P+
P+
C
Depletion region
Depletion region N well
P substrate
P substrate
(a) A
– VR P+
(b) +
C
N+
–
A
VR
+ C N+
P+
N well Depletion region P well Depletion region P substrate
(c)
P substrate
(d)
Figure 2.5 Cross sections of the four types of PNjunction varactors; (a) PþN well; (b) Nþsubstrate P; (c) NþP well; (d) N wellsubstrate P.
16
PNJUNCTION VARACTORS
Pþ and the N well. The main contribution to the loss is the signal travelling through the N well, where the main carriers are electrons, which are more mobile than the defect electrons. Consequently, this type has a relatively high quality factor. The second option is the Nþ/substrate P junction (Figure 2.5 (b)), which is based on the variation of the capacitance associated with the depletion zone that appears between the diffusion Nþ and the substrate P. In this case, the main contribution to the loss is the signal travelling through the substrate P, where the main carriers are defect electrons. Therefore, this structure is expected to have a lower quality factor than the previous case. In addition, in this junction (Nþ in the substrate P), one of the contacts is connected to ground (substrate P, anode) and control over this node is lost. As a result, the AC signal and the bias voltage have to be applied to the same terminal (cathode). One option would be to uncouple the AC and DC connection, but this would introduce extra capacitance and resistance, which would degrade the behaviour of the varactor even further. The Nþ/P well varactor (Figure 2.5 (c)) is almost identical to the previous junction (Nþsubstrate P), except that the substrate is replaced by a P well. It is logical for this type to have a factor that is very similar to the previous type, i.e. low. The fourth and last type is the N well/substrate P junction (Figure 2.5 (d)). This uses the depletion zone that appears between the N well and the substrate P. The signals through the N well and the substrate P show the most significant losses. The main carriers will be defect electrons (on substrate P) and electrons (in N well). Therefore, the quality factor will be the worst of the four options. In addition, the bias voltage and the AC signal must be applied to the terminal itself. Table 2.1 shows the specifications of the four types of PN junction. The PþN well junction varactor is, a priori, the best choice. It has the highest quality factor and no control is lost over its electrodes or terminals (Pedersen, 1999).
Table 2.1
Specifications of the four types of PN junctions.
PNjunction types
Main carriers
Pþ/N well Nþ/substrate P Nþ/P well N well/substrate P
Electrons Defect electrons Defect electrons Electrons/defect electrons
Terminal constraints None Anode to ground None Anode to ground
17
DIFFERENT ARCHITECTURES OF PNJUNCTION VARACTORS N P N+
P+
P+
N+
N+
P+
N well P substrate
Figure 2.6
Cross section of an island varactor.
2.2.1 Different Configurations of PNjunction Varactors According to the structure of the PNjunction varactors, there are at least three configurations: island varactors, matrix varactors and interdigit varactors.
2.2.1.1 Island Varactors These varactors are made up of diffusions in the form of squareshaped Pþ and Nþ type islands in an N well. The purpose of this configuration is to reduce the resistance in series of the varactor and, therefore, increase the quality factor (Gutie´ rrez 2004). Figure 2.6 shows a cross section of this type of varactor. With this type of varactor (Figure 2.7), a depletion zone is formed between the Pþ type islands and the N well around them. The Nþ islands are necessary to reduce the resistance of the external connections of the varactor (Gutie´ rrez, 2004).
P+
N+
P+
N+
P+
N+
P+
N+
P+
Depletion region
N well P substrate
Figure 2.7 Depletion zone in an island varactor.
18
PNJUNCTION VARACTORS N P P+
P+
N+
P+
P+
P+
N well
P substrate Figure 2.8 Cross section of a matrix varactor.
2.2.1.2 Matrix Varactors With this type of PNjunction varactor, the Nþ diffusions of the island varactors are replaced by a doping Nþ mesh (Figure 2.8). The diffusions Pþ are completely surrounded by the Nþ zones. The depletion zone is created evenly around the entire diffusion, unlike the case of the previous varactor, where in the zones with two nearby Pþ islands, the voltage difference did not generate a depletion zone. Therefore, as shown in Figure 2.9, a greater capacitance would be integrated in the same area (Pedersen, 2001). To avoid a diode avalanche breakdown, there must be a distance between the diffusions Pþ and Nþ that is greater than that of the depletion zone that is formed. This distance is created by an N well that increases the total resistance of the varactor. 2.2.1.3 Interdigit Varactors This configuration maximizes the contact perimeter between the different doping zones and maintains the diffusion area constant (Figure 2.10). With
Depletion region
P+
P+
P+
P+
P+
P+ N+
P+
P+
P+
N well P substrate
Figure 2.9 Depletion zone on a matrix varactor.
19
INFLUENCE OF BIAS VOLTAGE ON THE BEHAVIOUR
N+ P+
N well P substrate
Figure 2.10 Layout of an interdigit varactor.
this type of varactor, the total capacitance is increased but the size is maintained (Hernandez, 2002).
2.3 INFLUENCE OF BIAS VOLTAGE ON THE BEHAVIOUR OF A PNJUNCTION VARACTOR The quality factor increases with the bias voltage due mainly to the fact that the capacitance is reduced when the voltage is increased. Figure 2.11 shows how quality varies with the bias voltage for an integrated varactor. This variation shows an opposite tendency to that of the capacitance.
100 95 90
2.9
2.5
85 80 75
2.3 2.1
70 65
1.9 1.7 1.5 0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
60 55 50 4.0
Bias voltage (V)
Figure 2.11 Variation of the quality factor with the bias voltage.
Quality factor (Q)
Capacitance (pF)
2.7
20
PNJUNCTION VARACTORS
2.4 INFLUENCE OF GEOMETRIC PARAMETERS ON THE BEHAVIOUR OF A PNJUNCTION VARACTOR This section analyses the influence of geometric parameters on the behaviour of a PNjunction varactor. The geometric parameters that affect this behaviour are:
the the the the
number of islands; size of islands; distance between islands; size of the N well.
2.4.1 Influence in the Variation of the Number of Islands Figure 2.12 shows the influence on three varactors in which the number of islands has been doubled: Var 1 with 13 islands; Var 2 with 25; and Var 3 with 49. This figure demonstrates that with this type of varactor, the capacitance varies linearly in accordance with the number of islands. The reason behind this effect is that when the number of Pþ/N well junctions increases, the depletion zone increases, together with the capacitance. Table 2.2 shows the tuning range (TR) and the quality factor of these three varactors. As can be seen, the tuning range and quality are kept constant for the varactors under study. The increase in capacitance in the varactors is compensated by a reduction in resistance. As the designs are scalable (because they are small varactors, see Section 2.4.2), when the number of islands is doubled, the capacitance is doubled but the resistance is reduced by half. Consequently, quality is kept almost constant.
Capacitance (pF)
3.0
Var 1 (pF)
2.5
Var 2 (pF) Var 3 (pF)
2.0 I.5 I.0 0.5 0 0
0.5
1.0
1.5 2.0 2.5 Bias voltage(V)
3.0
3.5
4.0
Figure 2.12 Variation of the capacitance when varying the number of islands on a PNjunction varactor.
21
INFLUENCE OF GEOMETRIC PARAMETERS ON THE BEHAVIOUR Table 2.2 Variation of the tuning range and quality with the number of islands.
Var 1 Var 2 Var 3
TR (%)
Q
29 27 28
57 61 56
2.4.2 Influence of the Size of the Islands If, instead of increasing the number of islands, their length is increased but their width maintained, the depletion zone also increases. This has the same effect as increasing the number of islands. To check this, four varactors were made with a constant width (2 mm), a constant distance between islands (1.8 mm) and the same number of islands (25). Figure 2.13 shows the variation in capacitance with the bias voltage of these varactors. Another way of increasing the size of the islands is by increasing their width. Accordingly, three varactors were designed and made in which the width of the islands has been varied: Var 5 (2 mm); Var 13 (2.6 mm); and Var 14 (3.4 mm). Figure 2.14 shows the variation in capacitance with the bias voltage of these three varactors. Based on the results of Figures 2.13 and 2.14, the conclusion drawn is that when the length of the islands is increased, the capacitance increases linearly. A consequence of these results would indicate that with regard to
Capacitance (pF)
Var 2 (pF)
7
Var 4 (pF)
6
Var 5 (pF)
5
Var 6 (pF)
4 3 2 1 0 0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Bias voltage(V)
Figure 2.13 Variation in capacitance with the variation of the length of the islands.
Capacitance (pF)
22
PNJUNCTION VARACTORS 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5
Var 5 (pF) Var 13 (pF) Var 14 (pF)
0
0.5
1.0
1.5 2.0 2.5 Bias voltage (V)
3.0
3.5
4.0
Figure 2.14 Influence of the variation of the width of islands on an interdigit varactor.
capacitance, there is no difference between increasing the number of islands and increasing their length or width. Having analysed the capacitance, we shall now look at the tuning range and the quality factor. The tuning range has similar values for these varactors. However, as shown in Table 2.3, the quality factor is slightly less in the case of Var 6. To study the loss in quality when increasing the size of the varactor, three largesize varactors were made: Var 7, Var 8 and Var 9. Figure 2.15 shows the quality factors of nine varactors whose size has been increased. When the size of the varactor increases, the quality is reduced drastically. The reason for this reduction is an increase in the size of the varactor that does not result in a proportional reduction of resistance owing to spurious effects and connections. Therefore, the quality is affected only by the increase in capacitance, with a consequent reduction in the quality factor.
Table 2.3 Variation of the tuning range and quality with the length of the islands.
Var Var Var Var Var Var
2 4 5 6 13 14
TR (%)
Q
27 28 28 28 25 25
61 59 62 53 56 58
23
INFLUENCE OF GEOMETRIC PARAMETERS ON THE BEHAVIOUR 70 60 Quality factor (Q)
Var 5
Var 2 Var 4 Var 1
50
Var 6
Var 3
40 Var 7 30
Var 8 Var 9
20 10 0
10 000
20 000
30 000
40 000
50 000
Varactor size (µm2)
Figure 2.15 Variation in Q in accordance with the size of the varactor.
2.4.3 Influence of the Distance Between Islands Four varactors were fabricated to study the influence of the distance between islands: Var 5 (1.8 mm); Var 10 (2.3 mm); Var 11 (2.8 mm) and Var 12 (3.6 mm). Figure 2.16 shows the variation in capacitance with the bias voltage. Owing to the reduction of the coupling between tracks, there is a slight reduction of capacitance with the distance between islands, but the value is so insignificant that it cannot be separated from the uncertainty corresponding to the measurement equipment. Therefore it could be said that the capacitance does not vary with the distance between islands, since the depletion
Var 5 (pF) Var 10 (pF) Capacitance (pF)
5.2
Var 11 (pF) Var 12 (pF)
4.7 4.2 3.7 3.2 2.7 0
0.5
1.0
1.5 2.0 2.5 Bias voltage (V)
3.0
3.5
Figure 2.16 Influence of the distance between islands.
4.0
24
PNJUNCTION VARACTORS N P N+
P+
N+
N well N+ P substrate
Figure 2.17 Effect of the buried layer on a PNjunction varactor.
zone does not increase. Therefore the tuning range is also kept constant. The quality factor is reduced when the distance is increased owing to an increase in the resistance of the varactor, but this resistance does not increase linearly with the said distance. The resistance of the varactor might be expected to increase in proportion to the distance between the islands, but this is not so due to the fact that most integrated technologies include an Nþ type lowresistivity buried layer under the N well. Most of the RF currents between the Pþ and Nþ islands flow along this Nþ layer, minimizing the resistive effect of the N well. Figure 2.17 shows the effect of the buried layer on the RF currents. The quality factor and tuning range of these varactors is shown in Table 2.4. As the capacitance is kept almost constant for each varactor, the presence of the buried layer avoids a high reduction in the quality. 2.4.4 Variation of the Size of the N Well Two varactors were designed to analyse the influence of the size of the N well: Var 26 and Var 27. In the former, the N well has a width of 1 mm and the latter of 2 mm. Figure 2.18 shows the variation of the capacitance when this width is varied. Table 2.4 Variation of the quality and tuning range with the distance between islands.
Var Var Var Var
5 10 11 12
TR (%)
Q
28 28 28 27
62 49 43 35
25
Capacitance (pF)
INFLUENCE OF THE WORKING FREQUENCY ON THE RESULTS 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0
Var 26(pF) Var 27(pF)
0.0
0.5
1.0
1.5 2.0 2.5 Bias voltage (v)
3.0
3.5
4.0
Figure 2.18 Variation of capacitance when the size of the N well is increased.
The depletion zone hardly varies when the size and the number of islands are kept constant. Therefore, the capacitance has similar values. Table 2.5 shows the data corresponding to the tuning range and the quality factor. The tuning range hardly varies. The quality is reduced due to the fact that for the same capacitance value, the resistance of the device grows when the size of the N well is increased. 2.5 INFLUENCE OF THE WORKING FREQUENCY ON THE RESULTS 2.5.1 Influence of the Frequency on the Quality of a Varactor The quality factor of a varactor depends on its working frequency. Figure 2.19 shows the variation of the quality factor of a varactor when the working frequency is increased. As can be seen, the quality factor decreases when the working frequency is increased. The reasons for this decrease can be found in the increase of the capacitance with the frequency, which will be analysed below, whereas when the frequency is increased, the resistance of the varactor hardly varies.
Table 2.5 Variation of the tuning range and quality with the size of the N well. TR (%) Var 26 Var 27
23 21
Q 61 47
26
5.2 (WLAN2)
3.5 (WLAN1)
2.4 (Bluetooth)
2.1 (UMTS)
1.575 (GPS)
120 100 80 60 40 20 0 0.9 (GSM)
Quality factor (Q)
PNJUNCTION VARACTORS
Frequency (GHz)
Figure 2.19 Variation of the quality factor with the frequency.
2.5.2 Influence of the Frequency on the Capacitance of a Varactor The capacitance of a varactor increases with the working frequency. This increase in capacitance occurs up to the resonant frequency of the device, as shown in Figure 2.20. From the resonant frequency (fr), in this case from 6 GHz, the capacitive values are negative and the varactor stops taking capacitive values and
2.5
C_11.M C_22.M [E9]
2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 0.0
2.0
4.0
6.0
8.0
10.0
Frequency [E+9]
Figure 2.20 Resonant frequency in a PNjunction varactor.
INFLUENCE OF THE WORKING FREQUENCY ON THE RESULTS
27
begins to work as an inductor. In fact, what is being measured when calculating C11 and C22 represents the imaginary part of the measurement. In the case of varactors, this imaginary part is dominated by their capacitive part. However, owing mainly to the external connections of the device, there is also an inductive part (L), although this inductive part has a low value in comparison with the capacitive part (C). The imaginary part of a varactor can be expressed by the equation: Zimag ¼ Loj þ
1 : Coj
ð2:2Þ
For low frequencies, the inductive part is negligible with regard to the low value of L and that of the angular frequency (o), but if the frequency increases, this can become the dominant parameter. The limit between the zone where the electric field is stored and where the magnetic field is stored is given by the resonant frequency. This frequency is expressed by the equation: fr ¼
1 pﬃﬃﬃﬃﬃﬃ : 2p LC
ð2:3Þ
This resonant frequency should be as high as possible in order to use a varactor with the highest frequency range. Although the varactor maintains its capacitive characteristic, the frequency range near this frequency should not be used to avoid unwanted changes in capacitance and a reduction in quality if the working frequency varies slightly. The bigger the varactor, the higher its capacitance value. Therefore, the resonant frequency decreases. This effect can be seen in Figure 2.21, with three differentsized varactors: Var 4, Var 5 and Var 7. As shown in the graph, the resonant frequency of Var 7 (2.8 GHz) is lower than that of Var 5 (6.3 GHz), which is lower than that of Var 4 (7.5 GHz). In other words, the resonant frequency increases as the size of the varactor decreases. If a designer wants to increase the resonant frequency value for the given capacitance, only the inductance value can be changed. In other words, these values should be minimized in order to increase the working frequency range. As the inductance depends mainly on the external metal connections, to reduce the inductance of these connections, either the length of the connections should be reduced or more connections in parallel should be made. On trying to reduce the inductance, there is an increase in the
28
PNJUNCTION VARACTORS
Capacitance (F)
Var 4
Var 5
Var 7
8E10 6E10 4E10 2E10 0 –2E10 –4E10 –6E10 –8E10 0,E+00
2,E+09
4,E+09
6,E+09
8,E+09
1,E+10
Frequency (Hz)
Figure 2.21 Variation in fr in accordance with the size of the varactor.
parasitic capacitance of the device when the number of capacitances among the highest number of connections is increased, but the capacitance hardly varies due to the fact that the total capacitance of the varactor is much higher than the parasitic capacitances, which hides the increase.
2.6 COMPARISON BETWEEN THE DIFFERENT TYPES OF PNJUNCTION VARACTORS This section compares the different types of PNjunction varactors. Accordingly, the different configurations of the main parameters of the varactor are compared, i.e. the effective silicon area, the quality factor and the tuning range.
2.6.1 Comparison According to the Effective Silicon Area The definition of effective silicon area was given in the introduction to this book. It defines the capacitance by the area of silicon (pF/mm2) used by the varactor. This parameter should be as high as possible so that the varactors take up less space. This reduction in the size of the varactors also affects the resonant frequency, since the smaller the varactor, the fewer its external connections and, therefore, the higher its resonant frequency.
29
COMPARISON BETWEEN DIFFERENT TYPES OF PNJUNCTION Table 2.6 Table comparing varactors occupying the same area. Area (mm2) Interdigit Var Island Var Matrix Var
Cmax(pF)
21 000 21 500 23 000
C/A (pF/mm2)
TR (%)
Q
28 21 22
53 63 52
4
3:17 10 1:21 10 4 8:69 10 5
6.67 2.61 2.01
This comparison focuses on a set of PNjunction varactors of each type. The common characteristic of these varactors is that they occupy an area of a similar value. Table 2.6 shows the values of the aforementioned varactors with regard to the total area, maximum capacitance, the effective silicon area, the quality factor and the tuning range. The interdigit varactors have an effective silicon area that is higher than the rest, i.e. this type of varactor optimizes the capacitance per area of the PNjunction varactors. With regard to the tuning range, again the interdigit varactors have the highest value for this parameter. For many circuit applications, the tuning range should be maximized. Therefore, the aforementioned configurations have the best behaviour. Finally, the highest quality corresponds to the island varactors. For varactors with a high effective silicon area (interdigit), an increase in size has a more significant effect on the reduction of quality. 2.6.2 Comparison According to the Quality Factor This section includes a comparison of the island, interdigit and matrix varactors with regard to the quality factor. Three varactors with similar capacitance values were chosen for the comparison. Table 2.7 gives the figures for these varactors. This table shows once again that the tuning range is better for interdigit varactors than for island varactors. Furthermore, as the former are smaller, Table 2.7
Table comparing varactors for the same maximum capacitance value. Area (mm2)
Interdigit Var Island Var Matrix Var
8 500 21 500 24 500
Cmax(pF) 2.69 2.61 2.57
C/A (pF/mm2) 4
3:16 10 1:21 10 4 1:05 10 4
TR (%)
Q
fr(GHz)
28 21 20
59 63 60
7.48 6.55 6.13
30
PNJUNCTION VARACTORS
they have higher effective silicon area values. As for the quality factor, the island varactor shows better results, but the improvement is not significant. On top of this, the resonant frequency is almost 1 GHz higher in interdigit varactors than in island varactors. The reason for this is that the size of the island varactor is more than double and, consequently, the external connections have to be larger. These external connections increase the parasitic inductance of the varactor and reduce its resonance frequency. As a result of the above, the conclusion can be drawn that interdigit varactors have better characteristics than the rest except for the quality factor. However, the difference in the quality factor is small enough to be considered insignificant.
References Gutie´ rrez, I. (2004) Design and characterization of integrated varactors for RF applications. Ph.D. Thesis, Tecnun, University of Navarra, Spain. Herna´ ndez, E. (2002) Integration of a TV frequency converter for SiGe 0.8 mm technology. Ph.D. Thesis, Tecnun, University of Navarra, Spain. Maget, J. (2002) Varactors and inductors for integrated RF circuits in standard MOS technologies. Ph.D. Thesis, Munich, Germany. Pedersen, E. (2001) RF CMOS varactors for wireless applications. Ph.D. Thesis, Aalborg, Denmark. Pedersen, E. (1999) Performance evaluation of CMOS varactors for wireless RF applications. Proceedings of the 17th NorChip 99 Conference, Oslo, Norway.
3 MOS Varactors This type of varactor is based on MOS transistor structures (metaloxidesemiconductor) and is used in RF applications (Banerjee et al., 2003). With PNjunction varactors, MOS varactors present a large capacitance per area and tuning range. However, the tuning curve has a more abrupt shape, which can be a drawback for certain applications, such as VCOs (Porret, Melly and Enz, 2000). The two most important types of MOS varactors are the NMOS and PMOS varactors.
3.1 OPERATING PRINCIPLES OF AN NMOS VARACTOR The NMOS varactor is the most commonly used varactor in CMOS technology. By varying the voltage between the two terminals (G and D/S), the capacitance of the device changes in accordance with the operating voltage by which it is biased. This device makes use of the gate oxide as dielectric so that the device capacitance is dependent on the capacitance of the charge zone (CSi) and the capacitance of the oxide (Cox). The total capacitance of the device is given by: C ¼ C0 W L
ð3:1Þ
where C0 is the capacitance per unit of area, which is equal to (Svelto, 1999): C0 ¼
1 1 þ Cox CSi
1 ð3:2Þ
:
The NMOS varactor is characterized by its asymmetric nature since the values of its parameters (capacitance and tuning range) vary if they are Design and Characterization of Integrated Varactors for RF Applications and E. Herna´ndez # 2006 John Wiley & Sons, Ltd
´I. Gutie´rrez, J. Mele´ndez
32
MOS VARACTORS G Oxide
D/S
N+
N+
P+
N well
Psubstrate
Figure 3.1
Cross section of an NMOS varactor.
examined from the gate or from the diffusion terminals. In addition, they are very effective from the area point of view (Cmax per unit of area is almost three times higher than that of a PNjunction varactor (Pedersen, 2001)). The values obtained for the quality factor are slightly lower than those corresponding to the PNjunction (Pedersen, 2001) but may be improved with the progress of technology. The Cmax/Cmin ratio improves in comparison with that obtained with PNjunction varactors. To obtain any improvement in the performance of this type of varactor, there must be a compromise between capacitance and the quality factor. When Q reaches its maximum point, the capacitance is at its minimum level and vice versa. NMOS varactors have two operations modes, the accumulation mode and the inversion mode. The most used is the NMOS varactor in accumulation mode. As shown in Figure 3.1 the structure of the NMOS varactor in accumulation mode is similar to that of an Nchannel MOSFET transistor except for the fact that it is made in an N well instead of directly on the P substrate. This strategy removes the PNjunction parasitic capacitances that appeared between the drain, the source and the substrate P, which would have limited the tuning range. The two control electrodes are the gate and the drain/source (shortcircuited by metal connections). The bulk is connected to ground. The operating mode is controlled by the gate–drain DC voltage (VGS). 3.1.1 Operating Ranges of the NMOS Varactor The operating ranges in which an NMOS can be working are shown in Figure 3.2 (Maget, 2001): The solid line represents to the behaviour of the varactor at low frequencies and the broken line to that of high frequencies. There are two
33
OPERATING PRINCIPLES OF AN NMOS VARACTOR
Depletion zone Accumulation zone Inversion zone
Figure 3.2 Total capacitance between the gate and the substrate in accordance with the voltage between terminals (VGS).
significant voltages: the threshold voltage (VTH) and the flatband voltage (VFB). The latter represents the moment when there is no charge below the gate oxide (Tsividis, 1996). In accordance with the voltage applied between the terminals (VGS), there are three different zones (Sedra and Smith, 2000): The accumulation zone. This zone is used when VGS > VFB . The electrons accumulate on the silicon surface under the oxide from the zones Nþ, while the holes are repelled (Figure 3.3). The total capacitance is the result of placing the Cox and CSi in series. On the limit, the Ctotal obtains its maximum value, similar to the value of Cox.
+
D/S –
G Oxide
Polysilicon
N+
N+
P+
N well Accumulation zone
Psubstrate
Electrons
Figure 3.3 NMOS varactor working in accumulation mode.
34
MOS VARACTORS D/S +
–
G Oxide
Polysilicon
N+
N+
P+
N well Deplection zone
Psubstrate
Holes
Figure 3.4
NMOS varactor working in depletion mode.
The depletion zone. The varactor operates in this zone when VTH < VGS < VFB . Holes are attracted from the substrate and depletion zones are created around the Nþ diffusions (Cd) and just below the gate oxide (CSi) (Figure 3.4). The total capacitance will be the combination of Cox, CSi and Cd. Depending on the voltage applied, the depletion zone will be wider or narrower, increasing or reducing CSi and Cd. Therefore, the minimum total capacitance value is reached when VGS ¼ VTH . The advantage of this operating mode for the varactor in comparison with the accumulation mode is that it is possible to control the device capacitance value by means of the voltage between its terminals. The inversion zone. If the voltage continues to fall (VGS < VTH ), an inversion zone is formed under the gate. At low frequencies, working in the inversion zone represents an increase in the device capacitance up to a value close to the maximum (Coxmax). At high frequencies the NMOS varactor behaviour will be explained in Section 3.3. The maximum capacitance value per unit of area, C0max, corresponds to a high accumulation value under the gate oxide and is equal to Coxmax ¼ e=tox . The minimum value C0min is reached when the voltage difference between the device electrodes is equal to the threshold voltage (VTH). The ratio between Cox and C0min defines the tuning range. The behaviour of an NMOS varactor in accordance with the voltage applied between its terminals is different. Consequently, the NMOS varactor is studied separately in accumulation mode and in depletion mode with regard to aspects such as electrical phenomena and equivalent electrical circuits.
35
OPERATING PRINCIPLES OF AN NMOS VARACTOR
3.1.2 Electrical Phenomena of an NMOS Varactor in Accumulation Mode
When working in accumulation mode, there are seven electric fields and one magnetic field. Figure 3.5 gives a diagram of all the above effects. B1(t) magnetic field: this is generated by the variable current (AC signal) flowing along the metal track that forms the gate contact. It causes: parasitic inductance on the connection lines. E1(t) electric field in the gate: this generates: ohmic losses in the gate metal. E2(t) electric field between the gate contact and the accumulation zone: this is generated as the result of the voltage difference between the two. It produces: capacitance in the gate oxide. E3(t) electric field in the N well: this appears as the result of the distribution of voltages in the N well. It causes: parasitic capacitance in the N well; ohmic losses in the N well due to its resistivity. Electrons Drain
N+
Source
N+
P+
N well
Psubstrate
Figure 3.5 Electrical and magnetic phenomena in an NMOS varactor in accumulation mode.
36
MOS VARACTORS
E4(t) electric field between the accumulation zone and the source/drain: it causes: ohmic losses in the source and the drain. E5(t) electric field in the source and drain contacts: this appears as a result of the distribution of voltages in the source and drain contacts. It causes: ohmic loss due to the resistivity of Nþ diffusions and metal contacts.
E6(t) electric field between the N well and the P substrate: there is a voltage difference between the two, then the consequent depletion zone appears. It produces: a parasitic capacitance coupling between the varactor and the substrate; ohmic losses due to the resistivity of the depletion zone. E7(t) electric field in the substrate: this appears as a result of the voltage gradient in the substrate. It generates: parasitic capacitance due to the semiconductive character of the substrate; ohmic losses due to its resistivity. 3.1.3 Electrical Phenomena of an NMOS Varactor in Depletion Mode When an NMOS varactor is working in depletion mode, there are eight electric fields and one magnetic field (Figure 3.6). Holes Drain
Source
N+
N+
P+
N well Psubstrate
Figure 3.6 Illustration of the effects appearing in an NMOS varactor in depletion mode.
OPERATING PRINCIPLES OF AN NMOS VARACTOR
37
B1(t) magnetic field: this is generated by the variable current (AC signal) flowing along the metal track that forms the gate contact. It causes: parasitic inductance. E1(t) electric field in the gate: this causes: ohmic losses in the gate contact.
E2(t) electric field between the gate contact and the accumulation zone: this is generated as a result of the voltage difference between the two. It produces: capacitance coupling through the gate oxide. E3(t) electric field in the depletion zone: this appears as a result of the voltage difference between the gate oxide and the N well. It causes: capacitance in the charge depletion zone under the gate. E4(t) electric field between the depletion zone and the source/drain terminal: this causes: parasitic capacitance between the depletion zone and the Nþdiffusions. E5(t) electric field in the source and drain contacts: this appears as a result of the distribution of voltages in the source and drain contacts. It produces: ohmic losses in the source and the drain terminals. E6(t) electric field in the N well: this appears as a result of the distribution of voltages in the N well. It causes: parasitic capacitance in the N well; ohmic losses in the N well due to its resistivity. E7 (t) electric field between the N well and the P substrate: there is a voltage difference between the two and the consequent depletion zone appears. It produces: a capacitance coupling between the varactor and the substrate; ohmic losses due to the resistivity of the depletion zone.
38
MOS VARACTORS
E8(t) electric field in the substrate: this appears as a result of the voltage gradient in the substrate. It generates: parasitic capacitance due to the semiconductive nature of the substrate; ohmic losses due to its resistivity.
3.2 NMOS VARACTORS In general, these varactors in SiGe and CMOS technologies are not very commonly used as a result of their low quality factor (Andreani and Mattison, 2000). Their main carriers are holes whose mobility is 2.8 times lower than that of electrons. Consequently, their corresponding NMOS varactors obtain better results with lower losses and higher quality factors. Figure 3.7 shows a cross section of an NMOS varactor. The structure is similar to that of an NMOS transistor. The source, drain and bulk diffusions are connected together and inserted in an N well. The result is a variable capacitance with the voltage between bulk and gate (VBG). The gate and the source/drain/bulk contacts are the two control electrodes on the device. Figure 3.8 shows the typical capacitance variation of the NMOS varactor in comparison with the voltage applied (VBG) (Andreani, 1999). 3.2.1 Operating Ranges of the NMOS Varactor Figure 3.8 shows two of the device’s typical voltages: the threshold voltage (VTH) and the flatband voltage (VFB), which differentiate the three operating ranges of the varactor: Inversion range. The varactor works in this range when the voltage applied between its control electrodes VBG is greater than the threshold
B
D/S
G Oxide P+
P+
N+
N well Psubstrate
Figure 3.7 Diagram of an NMOS varactor.
39
NMOS VARACTORS
Accumulation
Depletion
Strong inversion Moderate inversion
Weak inversion
Figure 3.8 Typical curve of an NMOS varactor with gate (G), drain (D) and bulk (B) connected together.
voltage (jIVTH j). When this happens, the defect electrons are attracted under the gate oxide from the zones Pþ, with similar behaviour to that of an NMOS transistor in accumulation mode. Figure 3.9 shows the route of the defect electrons with solid lines. As VBG approaches VTH three zones appear in the inversion range: – strong inversion (VBG > jVTH j): the carrier current (holes) under the gate oxide is high; – moderate inversion (VBG > jVTH j): the mobility of the carriers gradually decreases. – weak inversion (VBG jVTH j): the mobility of the carriers is negligible.
B
D/S
G Oxide P+
P+
N+
N well Psubstrate
Figure 3.9 Route of the carriers in an NMOS varactor.
40
MOS VARACTORS
Depletion range. The varactor works in this range when the value of the voltage applied between its control electrodes is between the threshold voltage and the flatband voltage (VFB < VBG < jVTH j). The mobility of the carriers (default electrons if VG < VB , and electrons if VG > VB ) is low. Accumulation range. The device will work in this range when the voltage VBG VB ) and sufficiently high so as to enable the free movement of electrons as indicated by the broken lines in Figure 3.9.
As mentioned previously, one of the objectives when designing a varactor is to obtain a good capacitance ratio. Figure 3.10 shows the typical variation for an NMOS varactor with B D S (Andreani and Mattison, 2000). The varactor is usually characterized by a variable capacitance and a resistance that represents the possible losses generated (Svelto, 1999). The total capacitance of the NMOS varactor is given by: CPMOS ¼ C W l
ð3:3Þ
where W is the width of the PMOS channel, l is the length of the PMOS channel and C represents the capacitance per unit of area. The maximum possible capacitance value per unit of area of the varactor (Cmax ) is reached in the strong inversion and accumulation zones where the flow of carriers is greater than in the other zones. Its value corresponds to Cmax ¼ Cox max ¼ e=tox , where tox is the thickness of the gate oxide. However, as we approach the threshold voltage, the flow is reduced and the device capacitance falls to the minimum value when VBG ¼ VTH .
Figure 3.10 Typical capacitance of the NMOS varactor (B D S) in accordance with voltage VBG.
INFLUENCE OF THE OPERATING MODE ON AN NMOS VARACTOR
41
With regard to the resistance of the varactor, a good approach for a PMOS working in the strong inversion zone is given by (Andreani and Mattison, 2000): RPMOS ¼
l 12kp WðVBG jVTH jÞ
ð3:4Þ
where W is the width of the channel, l is the length of the channel and kp is the gain factor. In accordance with Equation (3.4), RPMOS increases when VBG approaches jVTH j, and it hypothetically becomes infinite when VBG ¼ jVTH j. In the strong inversion zone, the resistance values are low (VBG > jVTH j) but as we approach the threshold voltage, RPMOS is increased. Higher values are reached throughout the moderate inversion zone because the concentration of defect electrons in the gate oxide decreases and, therefore, the carrier current is low. If the voltage continues to fall, the varactor reaches the depletion zone. There the parasitic resistance is related to the resistive losses of the electron movement. As the mobility of the electrons is 2.8 times that of the defect electrons, the parasitic resistance in the depletion zone reaches very low values, even lower than those obtained in the strong inversion zone. Consequently, the most commonly used varactors are of the NMOS type.
3.3 INFLUENCE OF THE OPERATING MODE ON AN NMOS VARACTOR In Section 3.1 it was mentioned that NMOS varactors have two operating modes: accumulation mode and inversion mode. The only difference between the two configurations lies in the existence of an N well in the channel between the drain and the source in accumulation varactors. Figure 3.11(a) shows a cross section of an NMOS varactor in accumulation mode and Figure 3.11(b) shows the varactor in inversion mode. This difference makes the behaviour with the voltage of both configurations vary. Figure 3.12 shows the variation of the capacitance of the varactors Var M3 and Var M8 with the bias voltage. When a positive voltage (VG) is applied to the gate of an accumulation mode NMOS varactor, the total capacitance is mainly given by the oxide capacitance (Cox). When this voltage is decreased to negative values, the free electrons are repelled out the channel, generating an empty zone to which a capacitance CSi is associated (Figure 3.13).
42
MOS VARACTORS
D/S
D/S
G
N+
G
N+
N+
N+
N well Psubstrate
Psubstrate (a) Accumulation mode
(b) Inversion mode
Figure 3.11 Different operating modes of an NMOS varactor.
Var M3(pF)
Var M8(pF)
4.5
Capacitance (pF)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 –5
–3
–1
1
3
Bias voltage (V)
Figure 3.12 Influence of the operating mode.
Empty zone D/S
N+
N+
N well Psubstrate Electrons
Figure 3.13 Capacitances in an accumulation NMOS.
5
INFLUENCE OF THE OPERATING MODE ON AN NMOS VARACTOR Inversion channel
43
D/S
N+
N+
Psubstrate Electrons
Figure 3.14 Capacitances in an inversion NMOS.
In other words, when positive bias voltages are applied to the gate, the only capacitance of the varactor is Cox. However, when this bias is reduced, it becomes (CoxCSi)/(Cox þ CSi) and the total capacitance decreases. This causes the variation in capacitance with the voltage shown in Figure 3.12. With Var M8 (inversion mode), instead of free electrons (N well), the channel contains free defect electrons (P substrate). Therefore, when negative voltages are applied to the gate, the channel does not change, i.e. the main capacitance is Cox. In this case, the channel assumes a capacitance (Cd) which decreases when the voltage VG varies from negative to positive values. Figure 3.14 shows this effect. Unlike the NMOS varactor in accumulation mode, with an NMOS working in inversion mode for negative voltages in the gate, the only capacitance is that of the oxide, whereas when the voltage is increased, the total capacitance decreases due to the appearance of the capacitance Cd between the inversion channel and the substrate. The variation of the capacitance is (CoxCd)/(Cox þ Cd). This explains the different behaviour of an NMOS in accumulation and inversion modes. An analysis of the results given in Figure 3.12 leads to the conclusion that the capacitance values for negative bias voltage values of Var M8 (inversion) coincide with the capacitance values of Var M3 (accumulation) with a positive voltage. The reason for this coincidence lies in the fact that both measurements give the value of the oxide capacitance, which coincides in both varactors as they are geometrically the same. The quality factor and tuning range of both varactors for a work frequency of 1,575 GHz (GPS standard) is given in Table 3.1. As shown, there is no clear difference for these parameters between both configurations.
44
MOS VARACTORS Table 3.1 Influence of the operating mode on the quality factor and tuning range. TR (%)
Q
36 35
44 45
Var M3 Var M8
Although the tuning range is similar, with Var M3 (accumulation) the variation in capacitance occurs approximately within a voltage range of between 1 V and 1 V, whereas with Var M8 (inversion), this variation occurs between 1 V and 0 V. This means that RF designers need more precision in the design of inversion varactors than accumulation varactors, since any dispersion in the manufacture and design of the varactor can make it work in a range where the capacitance variation is minimal. Together with the advantage of isolation offered by the accumulation NMOS, these factors make this type of varactor the most popular at present.
3.4 INFLUENCE OF BIAS VOLTAGE ON THE BEHAVIOUR OF AN NMOS ACCUMULATION VARACTOR Figure 3.15 shows the variation in the quality factor of a varactor with the bias voltage. The capacitance increases with the bias while the resistance
Capacitance (pF)
Capacitance(pF) 5
60
4
50 40
3
30 2
20
1
10
0
0 –5
–3
–1
1
3
5
Bias voltage (V)
Figure 3.15 Variation of the quality factor with the bias voltage in an NMOS varactor.
45
INFLUENCE OF GEOMETRIC PARAMETERS
does not increase in the same proportion, which leads to a reduction in the quality factor.
3.5 INFLUENCE OF GEOMETRIC PARAMETERS ON THE BEHAVIOUR OF AN NMOS VARACTOR This section analyses the influence of geometric parameters on the behaviour of an NMOS varactor. The geometric parameters that affect this behaviour are: varactor size; gate length; gate width. 3.5.1 Influence of the Variation of the Varactor Size An NMOS varactor was manufactured with an NMOS transistor with a shortcircuited drain/source as a reference. To increase its size, the number of transistors connected in parallel is also increased. To analyse the influence of the size of an NMOS accumulation varactor, three varactors were designed and manufactured with the same size of NMOS transistors, but with a different number of basic devices. Figure 3.16 shows the variation of the capacitance with the bias voltage of Var M1 (36 transistors), Var M2 (90 transistors) and Var M3 (192 transistors). The capacitance increases linearly with the number of transistors used in the varactor, which demonstrates its scalability. As with the PNjunction
Var M1(pF)
Var M2(pF)
Var M3(pF)
Capacitance (pF)
5 4 3 2 1 0 –5
–3
–1
1
3
5
Bias voltage (V)
Figure 3.16 Scalability of NMOS accumulation varactors.
46
MOS VARACTORS Table 3.2 Variation of the quality factor and tuning range with the number of transistors.
Var M1 Var M2 Var M3
TR (%)
Q
36 38 36
45 42 44
varactors, the quality factor and tuning range are the most important parameters to be considered. Table 3.2 shows the values of these two parameters in the varactors under study. The quality factor and tuning range are maintained almost constant with regard to the number of transistors. This constant value in quality is produced since each NMOS transistor type structure that makes up the varactor is connected in parallel to the rest. Accordingly, the capacitance increases but the resistance decreases. Therefore, the quality factor remains constant. The quality factor data are given for a bias voltage of 0 V. 3.5.2 Influence of the Varactor Gate Length on its Performance Together with its width, the length of the gate is one of the most important geometric parameters in an NMOS varactor. The influence of the gate length is studied through the analysis of three NMOS varactors with different gate lengths: Var M3 (0.8 mm), Var M5 (1.6 mm) and Var M6 (2.4 mm). Figure 3.17
Capacitance(pF)
Var M3(pF)
16 14 12 10 8 6 4 2 0 –5
–3
Var M5(pF)
–1
1
Var M6(pF)
3
5
Bias voltage (V)
Figure 3.17 Influence of the gate length with the bias voltage.
47
INFLUENCE OF GEOMETRIC PARAMETERS
shows the variation in capacitance with the bias voltage of these three varactors. An analysis of the data shown in Figure 3.17 shows that an increase in gate length is not equal when positive or negative voltages are applied. In the positive voltage range, an increase in length produces a linear increase in the total capacitance, whereas this is not true for negative voltages. This effect is related to the parasitic capacitances of the varactor, especially the capacitance between tracks. Figure 3.18 shows an approximation of the variation in capacitances when the gate length is increased. When the track width is increased, there is an increase in the oxide capacitance (Cox), since the size of the oxide increases. There is also an increase in the capacitance in the N well (CSi), since this N well also increases. The parasitic capacitances Cp are the result of two effects: the capacitance between metal tracks and the capacitance between the gate oxide and the part of the Nþ zone which, due to the manufacturing process, has been diffused under the oxide. Therefore, as a result of the distancing of
G Oxide
D/S
N+
N+ N well
Psubstrate
G Oxide
D/S
N+
N+
N well Psubstrate
Figure 3.18 Variation in gate length.
48
MOS VARACTORS G
D/S
Figure 3.19 Simplified model of the capacitances of an NMOS accumulation varactor.
the metal connection tracks, there is a reduction in the parasitic capacitances (Cp). Figure 3.19 gives an approximate model of the capacitances in an NMOS varactor. When the varactor works in the accumulation zone, CSi is negligible in comparison with the capacitance of the oxide. Therefore the total capacitance will be: C ¼ Cox þ Cp :
ð3:5Þ
When the gate size is increased, Cp is reduced and Cox is increased. Therefore, the parasitic capacitance is neglegible. In addition, it can be said that for small gate lengths, where Cox decreases and Cp increases, as the increase in capacitance is linear in this working zone, the parasitic capacitances also have little influence. However, in the inversion zone the total capacitance can be estimated using: C¼
Cox CSi þ Cp : Cox þ CSi
ð3:6Þ
In this working zone, the capacitance does not increase linearly with the gate length due to the influence of the parasitic capacitances. When the gate length is increased, Cp decreases but Cox and Csi increase. Although both effects have comparable magnitudes, the total capacitance increases as a result of the greater influence of Cox and CSi. However, as mentioned previously, this increase is not linear, which indicates the clear influence of the parasitic capacitances. This effect has a clear influence on the tuning range, since this difference in behaviour in each zone increases the variation in capacitance. Table 3.3 shows this increase together with the quality factor.
49
INFLUENCE OF GEOMETRIC PARAMETERS Table 3.3 Influence of gate length on the tuning range and on quality.
Var M3 Var M5 Var M6
TR (%)
Q
36 53 56
44 33 25
Together with the increase in the tuning range, there is a decrease in the quality factor. This effect is due to the increase of the channel resistance which, together with the increase in the capacitance, reduces the quality factor. As this type of varactor has a buried layer, the increase in resistance is lessened. An increase in the gate length has two opposite effects: an increase in the tuning range and a decrease in the quality factor. In other words, depending on the application for which the varactor is to be used, a compromise must be reached between both effects. Table 3.3 shows that the tuning range values are high, which implies that the decrease in the quality factor is more limiting. Therefore, a priori, it is better to keep the gate size as low as possible in order to increase Q. 3.5.3 Influence of the Varactor Gate Width on its Performance Two varactors were manufactured in which the NMOS varactor gate width was increased: Var M3 (10 mm) and Var M4 (20 mm). Figure 3.20 Var M3(pF)
Var M4(pF)
9
Capacitance (pF)
8 7 6 5 4 3 2 1 –5
–3
–1
1
3
5
Bias voltage (V)
Figure 3.20 Variation of the gate width with the bias voltage.
50
MOS VARACTORS
shows the variation in capacitance with the bias voltage when the gate width is increased. An increase in the gate width increases the oxide capacitance (Cox) and the capacitance in the N well (CSi), which leads to an increase in the capacitance value. This increase varies between 1.8 and 2 pF when the gate width is doubled.
3.6 INFLUENCE OF THE WORKING FREQUENCY ON THE RESULTS The influence of an increase in frequency on the behaviour of varactors was analysed in Chapter 2 for PNjunction varactors. Most of the analysis coincides and, consequently, this section only gives a study of the improvement of the resonant frequency for NMOS varactors. The resonant frequency determines the working frequency limit for varactors and, therefore, should be as high as possible. To increase this frequency, either the capacitance is decreased or the inductance of the external connections of the varactor is decreased. A varactor was designed and manufactured in which, to minimize inductance, the number of metals in the external connections was doubled. In contrast, this increase in the number of metal layers will increase the parasitic capacitances of the varactor. Figure 3.21 shows the variation in capacitance with the bias voltage of both varactors.
Var M3(pF)
Var M7(pF)
5.0 Capacitance (pF)
4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 –5
–3
–1
1
3
5
Bias voltage (V)
Figure 3.21 Variation of the capacitance with the bias voltage for a different number of metal layers.
51
INFLUENCE OF THE WORKING FREQUENCY ON THE RESULTS Table 3.4 Influence of metallization on the quality factor and the tuning range. TR (%) Var M3 Var M7
Q
36 34
Var M3(pF)
44 42
Var M7(pF)
Capacitance (pF)
3,E+03
2,E+03
1,E+03
0,E+00
–1,E+03 0,E+00
2,E+09
4,E+09
6,E+09
8,E+09
1,E+10
1,E+10
Frequency (Hz)
Figure 3.22 Influence of metallization on resonant frequency.
There is a slight increase in the absolute capacitance value. Therefore, the tuning range decreases slightly, as shown in Table 3.4. The quality factor should increase as a result of the reduction of the parasitic resistance of the connections. However, this reduction is so small that the quality factor hardly varies. However, the resonance frequency value is improved, as shown in Figure 3.22.
References ´ s. IEEE Andreani, P. and Mattison, S. (2000) On the use of MOS varactors in RF VCO Journal of SolidState Circuits, 35(6), 905–910. Andreani, P. and Mattison, S. (1999) A 1.8 GHz CMOS VCO tuned by accumulationmode MOS varactor. Department of Applied Electronics, Lund University, Sweden.
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MOS VARACTORS
Banerjee, S.K. et al. (2003) Simulation and benchmarking of MOS varactors for the CMOS090 RF process technology. Motorola S3 2003 Symposium, Itasca, Illinois, USA. Maget, J. (2001) Comparison of CMOS VCOs for UMTS tuned by standard and novel varactors in standard 0.25 mm technology. Infinion Technologies AG. Pedersen, E. (2001) RF CMOS varactors for wireless applications. Ph.D. Thesis, Aalborg, Denmark. Porret, A. S., Melly, T. and Enz, C. (2000) Design of high Q varactors for lowpower wireless applications using a standard CMOS process. IEEE Journal of Solid State Circuits, 35(3), 337–345. Sedra, A. and Smith, K. (2000) Microelectronics Circuits, Oxford University Press, Oxford, UK. Svelto, F. (1999) A metal oxide semiconductor varactor. IEEE Electron Device Letters, 20(4), 164–166. Tsividis, Y. (1987) Operation and Modeling of the MOS Transistor, McGraw Hill New York, USA.
4 Measurement Techniques for Integrated Varactors 4.1 TEST SYSTEM The test system is defined as the set of equipment, cables, connectors and test probes used in the characterization of a component, in this case an integrated varactor. This test system has been chosen on the basis of the test technique used. Selecting the test technique is the first decision to be taken when defining the test system. The test technique is based on the parameters: frequency range of interest; device under test (DUT) impedance range; parameters under test. There are also other factors which, although less relevant, need to be taken into consideration in certain cases: electrical conditions of the test; physical specifications of the DUT. Owing to the impedance of varactors, the method based on RF IV or that based on the vector network analyser (VNA) should be used. The latter is more appropriate because, in the frequency range in which we are interested, it has the same level of precision as the RF IV method and the cost of a network analyser is lower than that of a radio frequency IV meter.
Design and Characterization of Integrated Varactors for RF Applications and E. Herna´ndez # 2006 John Wiley & Sons, Ltd
´I. Gutie´rrez, J. Mele´ndez
54
MEASUREMENT TECHNIQUES FOR INTEGRATED VARACTORS
4.2 EQUIPMENT REQUIRED FOR THE ONWAFER TESTING OF INTEGRATED VARACTORS 4.2.1 Test Probes Test probes act as adapters between the test cables and the test structure pads. When selecting them, the factors which should be taken into account are: frequency range; equipment used; maximum current. In this case, the preferred and most commonly used in radio frequency tests have been the air coplanar probes (ACP) by Cascade Microtech, 1999 (see Figure 4.1). 4.2.2 Connectivity To connect the VNA with the test probes, a set of elements such as cables and connectors is required. The connection cables have to be correctly screened for use in the frequency range in which the varactors are to be tested, i.e. their insertion loss must be less than 0.75 dB in the working range.
Figure 4.1 ACP 40 test probes.
55
CALIBRATING THE TEST SYSTEM
The connectors are used to make the connection between the VNA and the test probes with the aforementioned cables. The connectors used in this test system are SMA pieces designed for working up to 18 GHz.
4.3 CALIBRATING THE TEST SYSTEM To ensure the reliability of the tests, the test system reference plane has to be positioned as close as possible to the component that is to be tested, i.e. at the end of the test probes. Positioning the reference plane at the desired point is known as calibrating the system. There are many calibration methods, each with its own set of advantages and disadvantages (Lord, 1999). Again, a decision has to be taken to use one method or another. The most relevant factors to be taken into account are: frequency range; VNA compatibility; compatibility with the test probes. Based on these criteria, for the varactor characterization the shortopenloadthru (SOLT) (Cascade Microtech, 1999) calibration method is recommended. Other calibration methods, such as the LRM and LRRM (Kolding, 2000) could be considered valid, but the SOLT is preferred as it does not depend on technology and is therefore a more general method. The test system is shown in Figure 4.2.
HP8719ES VNA
Power supply DC
RF
RF T
T
Bias tee
DC
DUT DC+RF
DC+RF GSG Probes
Figure 4.2 Test system.
56
MEASUREMENT TECHNIQUES FOR INTEGRATED VARACTORS
4.4 TEST STRUCTURES The tests on varactors should be performed on wafer since they are integrated components. Consequently, the structures (known as test structures) that enable the interconnection between the test probes and integrated varactors need to be designed. The importance of these structures lies in the need for the contact between the test system and the varactors to allow the corresponding characterization and, at the same time, introduce the lowest possible influence from the parasitic effects. In turn, a process enabling the systematic elimination of this influence has to be designed. The following is an explanation of the most important considerations when designing the test structures. 4.4.1 Choosing the Test Structure Configuration The first consideration to take into account is the type of configuration to be used when designing the test structures. In this case, the choice is whether to use a oneport or twoport test. For a correct characterization of a passive element it is best to use a twoport configuration, since this analyses the behaviour of the device in the most general way possible (Aguilera and Berenguer, 2003). In addition, in the particular case of the test of an integrated varactor, the twoport test obtains parameters related to the model of varactor that are not obtained with oneport tests, such as parasitic capacitance between the N well and the substrate. Having chosen a twoport test structure, the configuration of the varactor in series between the two ports is defined. This configuration gives an exact characterization of a twoport device and presents a design that is simpler than the configuration in parallel; consequently, it is considered more appropriate. Figure 4.3 (a) shows the device in series with one port and Figure 4.3 (b) shows it with the two ports of the network analyser.
Port 1
Port 1
(a)
Port 2
(b)
Figure 4.3 Test with the device in series.
57
TEST STRUCTURES
4.4.2 Design of the Test Structures
Once the test structures have been configured, they need to be designed. The most important point when approaching the design is knowing the parasitic effects of the structures so as to minimize their influence. These test structures have to be capable of testing varactors on two ports and each port will be of the ground–signal–ground (GSG) type. The test structures have two clearly differentiated parts: the test pads and the guard ring. The following is an explanation of each part. 4.4.2.1 Test Pads The function of the test pads is to make the physical contact between the test probes and the device under test (DUT). To obtain the capacitance between the pad and the substrate the factors which define it have to be considered. These are: pad dimensions, geometrical shape and metal layers employed. Geometrical dimensions. These are determined by the manufacturing technology and by the movement of the probes if the tests are to be performed on wafer or by the bondwire if the tests are to be performed on PCB. For onwafer tests, a solid contact is ensured when the probe shifts 40 mm over the pad. For the case of the bondwire, the most commonly used wire diameter is 25 mm and under normal bonding conditions, the bonding area is twice the diameter of the wire, i.e. 50 mm. Geometrical shape. The most commonly used geometrical shape for a test pad is the square. This is not very appropriate from the point of view of the parasitic effects, since the relation between the contact area and the area occupied by the pad will be very low. This makes it necessary to design pads with geometrical shapes in which this relation is increased, e.g. hexagons, octagons, etc. Pad structure. In general, with conventional technologies such as CMOS and SiGe, the pad is made up of all the available layers. Figure 4.4 shows the Metal 3 Metal 2 Via
Metal 1 Polysilicon 2 Polysilicon 1
Figure 4.4
Structure of a pad implemented in a threemetal CMOS technology.
58
MEASUREMENT TECHNIQUES FOR INTEGRATED VARACTORS
structure of a pad that employs all the available layers in a three metal–two polysilicon fabrication process. They are designed in this way to make them more resistant to the movement of the test probe or the bonding of the bondwire. In order to minimize the losses from the autocoupling between terminals, the signal pads have to be designed using only the last two or three layers of metal available in the technology to reduce the capacitance to the substrate. In addition, a well with a characteristic different from the substrate should be deposited under the pad because, in this way, the capacitance between the N well and the P substrate is in series with that of the pad, reducing total capacitance. Distance between pads. The coupling ðS12 Þ is a very important parameter to be taken into account, since if the DUT has S12 values similar to those of its test structure in the frequency range of interest, the test of the DUT may be affected by the coupling in the structure. The signal between ports 1 and 2 which passes through the DUT should be at least 20 dB greater than the coupling value between ports at the frequency of interest. Consequently, the distance would be approximately 350 mm (Aguilera and Berenguer, 2003). 4.4.2.2 Guard Ring The guard ring is the structure surrounding the passive element, joining the grounded part of the two pads. Figure 4.5 shows a test structure indicating the pads and the guard ring. The guard rings are designed by creating a structure that joins the ground pads of both ports together by metal layers. These metal layers are connected to the substrate. In addition, all the layers of polysilicon allowed by the
Pads DUT Guard ring
Figure 4.5 Pads and guard ring of a test structure.
59
TEST STRUCTURES
Figure 4.6
Test structure.
technology are also connected to these metal layers. This ensures that all the layers in the guard ring are interconnected and shortcircuited to ground to reduce the parasitic effects. Figure 4.6 shows a microphotograph of the test structures together with a varactor designed for its characterization. 4.4.3 Effects Introduced by the Test Structures Having defined the test structures, this section explains the parasitic effects introduced by the structure in order to prepare an efficient deembedding system. Figure 4.7 shows the equivalent model that includes each of the parasitic effects introduced by the test structures. The above figure shows the test structure impedance model for a triterminal element (one of the ports is connected to ground) recommended for integrated varactors. The following is an explanation of each of the effects.
S2
S1 DUT
G1
G2
Figure 4.7
Test structure impedance model.
60
MEASUREMENT TECHNIQUES FOR INTEGRATED VARACTORS
4.4.3.1 Contact Impedance Zc The contact impedance represents the ohmic loss resulting from the contact between the probes and the test structure, together with the loss produced in the pad. As the test structures have a twoport design, there will be contact impedance on both ports (Zc1 and Zc2 ).
4.4.3.2 Coupling Between the Two Ports (Zf ) The signals between the two ports of the structure may couple and this can be modelled by an impedance (Zf) between the pads of both ports. The test structures have been designed with a distance of 400 mm between the pads. This distance notably reduces the coupling effect between ports to a point where it can be considered negligible (Aguilera and Berenguer, 2003). 4.4.3.3 Autocoupling Yp Owing to the fact that the pads have been designed with polysilicon layers and metal layers, parasitic capacitances appear between the pads and ground, resulting in signal losses. This autocoupling occurs on both ports (Yp1 and Yp2). 4.4.3.4 Connection Track Impedance Zi Metal tracks are used to connect the signal pads to the device under test. These connection tracks introduce ohmic loss on both ports (Zi1 and Zi2). 4.4.3.5 Coupling Due to the Connection Tracks Yd Together with the impedance introduced by the connection tracks, there is coupling between the metal of the tracks on both ports and ground (Yd1 and Yd2). In the case of test structures designed by Aguilera and Berenguer (2003), this coupling is negligible in comparison with the impedance introduced by the contact between pads and probes. 4.4.3.6 Impedance to Ground Zs Finally, between the device under test (varactor) and the contact to ground on the substrate, there is an impedance Zs. The effects of the substrate have an important influence when a varactor is inserted in a circuit. Consequently,
61
TEST STRUCTURE DEEMBEDDING TECHNIQUES
S1
S2
DUT
G1
G2
Figure 4.8 Simplified impedance model of a test structure.
Zs should be considered as part of the device under test (DUT) and not as a parasitic effect to be eliminated using deembedding techniques. Figure 4.8 shows the equivalent model of each of the parasitic effects introduced by the test structures once the simplifications explained above have been made. 4.5 TEST STRUCTURE DEEMBEDDING TECHNIQUES The purpose behind using deembedding techniques on the device under test is to transfer the test reference plane from the structure pads to the device. Figure 4.9 shows such a transfer. To complete the deembedding technique, Deembedding
DUT
Reference plane after deembedding
Reference plane after calibration
Figure 4.9 Transfer of the reference plane.
62
MEASUREMENT TECHNIQUES FOR INTEGRATED VARACTORS
Figure 4.10 Deembedding structures.
the parasitic effects occurring on the test structures have to be determined so that they can be eliminated by mathematical procedure. This elimination takes place through the design of a set of specific test structures. The structures enable the isolation of each parasitic effect and, consequently, their mathematical elimination from the device test. In this chapter, three deembedding structures are presented: single–open structure, single–short structure and thru structure. Figure 4.10 shows each of the three structures. The following section gives an explanation of the use of the structures for the deembedding process. 4.5.1 Single–Short Structure This structure is designed by connecting the signal pad of both ports to the ground pads. This shortcircuits the signal to ground on each of the test ports and the short circuit is shown in Figure 4.11.
Figure 4.11 Singleshort structure.
63
TEST STRUCTURE DEEMBEDDING TECHNIQUES
S1
G
S2
G
Figure 4.12 Single–short structure impedance model.
The objective of this structure is to measure the contact impedance Zc1 and Zc2. As the signal pad is shortcircuited with the ground pads, the only impedance value obtained is that which corresponds to the contact resistance. The single–short structure impedance model is shown in Figure 4.12. Measuring Z11 and Z22 with a VNA it is possible to obtain the values Zc1 from port one and Zc2 from port two directly. 4.5.2 Single–Open Structure The single–open structure is designed by keeping the signal pads isolated from the ground pads on both test ports. Figure 4.13 shows this type of structure. This structure is used to determine the autocoupling value of each port (Yp1 and Yp2). The test impedance model for this structure is shown in Figure 4.14. As shown, besides the contact resistance values of ports one and two, this model also includes the autocoupling values. Owing to the inclusion of the contact impedances (Zc1 and Zc2) in the test, in order to calculate the autocoupling values the impedance has to be
Figure 4.13 Single–open structure.
64
MEASUREMENT TECHNIQUES FOR INTEGRATED VARACTORS
S2
S1
G
G
Figure 4.14 Single–open structure impedance model.
subtracted from the single–short and single–open structures. This gives the values of Yp1 and Yp2. 4.5.3 Thru Structure This structure is designed by connecting the signal pads of both ports using a metal of the same size as the one used to connect the pads to the varactors. Figure 4.15 shows a structure connected in this way. A thru structure is designed to calculate the impedance introduced by the aforementioned connections. The result of this structure test can be modelled as shown in Figure 4.16. As shown in the model, besides the impedance associated with the connection line (Zi), this structure test also includes the contact and autocoupling impedances. Therefore these impedances have to be eliminated from the thru structure model. This process begins by subtracting the single– short structure from the thru structure to eliminate Zc. The same has to be
Figure 4.15 Thru structure.
65
TEST STRUCTURE DEEMBEDDING TECHNIQUES
S1
S2
G1
G2
Figure 4.16 Thru structure impedance model.
done with the single–open structure to eliminate the value of Yp. This leaves the model with only the impedance value of the connection lines Zi. This process calculates the impedance value of the connection line that joins together the signal pads of the twoport test structure. As the size of the connection lines depends on each varactor, its impedance is calculated using the value of Zi affected by a correction factor that depends on the size of the connection. Figure 4.17 shows a summary of the deembedding process used.
S2
S1 SHORT G1
G2
S1
S2
S1
S2
G2
G1
G2
OPEN G1 S1
S2
S1
S2
THRU G1
G2
G1
G2
S1
S2
G1
G2
Figure 4.17 Complete deembedding process.
66
MEASUREMENT TECHNIQUES FOR INTEGRATED VARACTORS
4.6 CHARACTERIZATION OF INTEGRATED VARACTORS
Having defined the test system and the deembedding process used, the next step is to characterize the integrated varactors. To obtain the S parameters of a varactor, the test system explained above is used. With integrated varactors, these parameters have to be obtained for each polarization that is to be studied. Consequently, as many S parameter tests as polarization values to be used have to be performed. To apply a polarization to the varactor, the bias tees of the corresponding VNA are used. A voltage source is used to apply a DC signal that is added to the VNA RF signal. Once the corresponding tests have been completed, the deembedding techniques explained above are used to eliminate the parasitic effects introduced by the test structures. Figure 4.18 shows the S parameter values of a varactor before and after the deembedding process. Once the deembedding process has been completed on the basis of the S parameter results of both ports, a transformation is performed to one port using the following equations:
S21 S12 S1 ¼ S11 1 þ S22 S21 S12 S2 ¼ S22 : 1 þ S11
1.0
ð4:1Þ ð4:2Þ
1.0 2.0
0.5
2.0
0.5 3.0 0.2
0.2
5.0
2.0
1.0
0.5
3.0 0.2
5.0
2.0
1.0
0.5
0.2
0.2
–5.0 0.2 –2.0
–0.3 –1.0
–5.0 –2.0
–0.3 –1.0
Figure 4.18 Modification of the S parameter values using deembedding techniques.
TEST SYSTEM VERIFICATION
67
These equations give the parameters that define the behaviour of the varactors, such as the quality factor (Q) and the capacitance and resistance values.
4.7 TEST SYSTEM VERIFICATION After defining the characterization system, a number of tests have to be performed to ensure the reliability of the test process. A test plan was designed to provide data to find the causes of the uncertainly factors, i.e. all the tests focus, on the one hand, on characterizing the divergences between the manufactured component and the electrical models and, on the other, on defining the situations in which the instabilities are produced. The main points where there may be divergences between the electrical model and the actual behaviour are indicated as: E1  error introduced by positioning the test probes on the component under test; E2  error introduced by the calibration reference tolerances; E3  error introduced by the test probes heating up; E4  error from component degradation. Consideration must also be given to the tolerances in the standard manufacturing processes which, in some cases, is around 15 %. Another point worthy of special mention in these tests is that as the error increases with the frequency, these figures have been taken from tests of around 10 GHz and the least favourable case has been considered. 4.7.1 Error Introduced by Positioning the Test Probes on the Pads The component characterization results depend on the position of the test probes on the component itself. In the procedure used for the test, the positions of the probes on the components are defined. However, owing to the fact that the positioning is manual, there are slight differences in the positioning, which introduces uncertainty in the tests. This test focuses on characterizing the error introduced. To perform the test, after the system has been calibrated, the same calibration reference of 50 have to be tested repeatedly on the calibration substrate in a short period of time. The test probes should be moved approximately 16 mm on the calibration reference. A test should be performed
68
MEASUREMENT TECHNIQUES FOR INTEGRATED VARACTORS Relative error on a 50 Ω calibration reference
Relative error (Ω)
12.20E06 10.00E06 8.00E06 6.00E06 4.00E06 2.00E06 0.00E+00 0
5
10
15
20
25
30
35
40
Test number
Figure 4.19 Error introduced by the positioning of the test probes.
in the frequency range of between 0.5 and 10 GHz, and the test value at the frequency giving the greatest difference with the 50 reference should be taken; 40 tests of this reference were performed. Figure 4.19 shows the typical variation of the impedance value in the 50 calibration reference. This test represents the error introduced by the tolerances in the positioning of the probes. The graph shows how the calibration is lost after test 30. Consequently, the results were obtained from the first 30 tests. The standard deviation (s) was calculated using the following equation: sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ðxi xn Þ2 ; s¼ n
ð4:3Þ
where xi is the value of each test, xn is the average of the values taken and n is the number of tests. Taking the 50 calibration as a reference, the standard deviation value is given by: s ¼ 5:6 108 : 4.7.2 Error Introduced by the Calibration Reference Tolerances Before performing the test, the meters that are to be used have to be calibrated. This calibration consists of varying the test reference from the apparatus to the element under test. To perform the calibration, the calibration
69
TEST SYSTEM VERIFICATION
substrate is used in which fixed values can be obtained, such as a short (short circuit) or a load (load of 50 ). However, these values will undergo dispersion in the manufacturing process and the calibration reference will not be exactly the same for each calibration process. Therefore, an error will be introduced which has to be analysed. To perform this test, 10 calibration references of 50 can be used and the procedure should have the steps: calibrate the test system with the calibration reference; carry out five tests of the S11 for each of the 10 calibration references a priori identical to that used to calibrate the system; calculate the average and standard deviation of the tests. The errors introduced by the tests are shown in Figure 4.20. Taking the 50 of the calibration references used in this test as a reference gives a standard deviation value of: s ¼ 54:8 106 :
4.7.3 Error Introduced by the Test Probes Heating Up
Average error of each reference (Ω)
The test equipment shows different results from different tests on the same component, partially due to the fact that when the probes heat up, their
2,50E06 2,00E06 1,50E06 1,00E06 5,00E05 0,00E+00 0
2
4
6
8
10
Calibration reference
Figure 4.20 Error introduced by the calibration reference.
70
MEASUREMENT TECHNIQUES FOR INTEGRATED VARACTORS Influence of the heatingup of the probes on 53 52 51 50 49 0
5
10
15
20
Test number
Figure 4.21 Errors introduced by the test probes heating up.
properties vary. This test focuses on locating the area introduced by the probes in the different tests as a result of heating up. The test procedure is: calibrate the test system; position the probes on a 50 calibration reference; repeat the test every 10 minutes without removing the probes. The results of the Z11 values for the tests performed are shown in Figure 4.21. As the reference is 50 , the standard deviation value given is: s ¼ 1:34 104 : 4.7.4 Error Introduced by the Degradation of the Components To completely characterize a component, different tests have to be performed on each one. Consequently, the component is degraded until it is eventually rendered useless. The pads have a surface layer of oxide. When the probes are moved on the pads, they remove the oxide layer. In successive tests, they also remove part of the metal layers. Consequently, the first tests are affected by the oxide and the final tests may vary if the metal has been removed. Consequently, we need to know how the number of tests affects the final result. The process used for studying component degradation is. repeat the same short structure tests until the component degradation is observed;
71
TEST SYSTEM VERIFICATION 90 80 70 60 50 40 30 20 10 0 –10 0
5
10
15
20
25
30
Test number
Figure 4.22 Error from component degradation.
calculate the average value of Z11 (real) for the frequency range; Eliminate the first tests (oxidation) and the final tests (degradation) and recalculate the average and standard deviation. The average values of Z11 (real) of the tests and their number are shown in Figure 4.22. This test reveals the initial existence of tests where the contact resistance is greater, then it is reduced and becomes stable before it increases greatly as a consequence of the degradation of the pad. Therefore, to find the resistance introduced in the normal tests, the values at each end of the scale should be eliminated. The elimination of the test values affected by the passivation and degradation gives Figure 4.23. 5 4 3 2 1 0 –1 4
9
14 Test number
19
Figure 4.23 Valid tests on a component.
72
MEASUREMENT TECHNIQUES FOR INTEGRATED VARACTORS Table 4.1
Error type E1 E2 E3 E4

Typical test deviations.
Standard deviation ( )
Relative in comparison with total
5:6 108 5:48 107 1:34 104 1:2 103
5–10 pF) is not the one associated with the Pþ N well junction, but the metal contact ones. Thus above a certain size the quality does not remain constant and decreases as the size increases. Design and Characterization of Integrated Varactors for RF Applications and E. Herna´ndez # 2006 John Wiley & Sons, Ltd
´I. Gutie´rrez, J. Mele´ndez
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DESIGN RULES FOR INTEGRATED VARACTORS
The metal connections reduce the resonant frequency. Consequently, if high capacitance values are required, the number rather than the size of islands should be increased in order to use more connections in parallel and avoid them being longer. To increase the capacitance, either the number of diffusions or the base of each diffusion should be increased. The latter solution reduces the resonant frequency as the number of metal connections in parallel is lower.
6.2 DESIGN RULES FOR NMOS INTEGRATED VARACTORS The design rules for NMOS varactors are: Accumulation NMOS varactors have similar tuning range and quality factor specifications to inversion NMOS varactors. The advantage of the first one is that the tuning range is produced in a greater polarization voltage range, which enables the design of the corresponding applications. The variation in capacitance is represented mainly by the parameter CSi, which defines the status of the channel under the gate terminal. Therefore, this channel is the key factor in the design of an NMOS varactor. The maximum capacitance value of the varactor is given by the capacitance of the gate oxide Cox . In other words, the unit Cox and CSi determines the capacitance values of the varactor with the polarization. Both parameters depend on the gate size. To increase the working frequency range, it is best to use the maximum number of metal connections; however, this reduces the tuning range slightly and, consequently, a compromise solution must be found. The increase in the gate length reduces the quality factor due to an increase in the resistance of the varactor. Therefore it is best to work with the minimum gate length allowed by the technology. The increase in the gate width does not vary the conditions of the NMOS varactor regarding the increase in the number of transistors NMOS used. Consequently, this parameter it is not critical in the design of varactors.
6.3 COMPARISON BETWEEN ACCUMULATION NMOS VARACTORS AND PNJUNCTION VARACTORS This section presents a comparison of the characteristics of the values of accumulation NMOS and PNjunction varactors. First, two similar sized
87
COMPARISON BETWEEN ACCUMULATION NMOS VARACTORS
Capacitance (pF)
Var 2 (pF)
Var M2(pF)
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 –2
–1
0
1
2
3
4
Bias voltage (V)
Figure 6.1 Comparison of Var M2 and Var 2.
varactors are presented: Var M2 (4300 mm2) and Var 2 (4050 mm2). Figure 6.1 shows the variation in capacitance with the polarization voltage of both varactors. As shown, the variation in capacitance is greater in the accumulation NMOS varactor (Var M2) than in the PNjunction varactor (Var 2). Consequently, the tuning range of Var M2 is greater, as shown in Table 6.1. With regard to the quality factor, PNjunction varactors have better values due to their lower resistance. This increase in resistance occurs because the varactor is in the empty zone. In this zone, the channel under the gate terminal is emptying its free carriers and its conductivity falls. NMOS varactors have higher absolute capacitance values, which means that their effective silicon area is greater. Thus, in Var M2 the affected area is 4.1 104 pF/mm2 for a polarization voltage of 0 V, whereas in Var 2 it is 3.1 104 pF/mm2. In other words, NMOS varactors have significant advantages if a high tuning range is required. However, PNjunction varactors have a higher quality factor and advantages in the design of circuit applications including varactors, such as VCOs (Andreani and Mattison, 2000; Hern´ andez, 2002; Maget, Tiebout and Kraus, 2002). Table 6.1
Var M2 Var 2
Tuning range and quality factor of Var M2 and Var 2. TR (%)
Q
39 27
42 61
88
DESIGN RULES FOR INTEGRATED VARACTORS
References
Andreani, P. and Mattison, S. (2000) On the use of MOS varactors in RF VCOs. IEEE Journal of SolidState Circuits, 35(6), 905–910. Hern´ andez, E. (2002) Integration of a TV frequency converter for SiGe 0.8 mm technology. Ph.D. Thesis, Tecnun, University of Navarra, Spain. Maget, J., Tiebout, M. and Kraus, R. (2002) Influence of the MOS varactor gate doping on the performance of a 2.7 GHz4 GHz LCVCO in standard digital 0.12 mm CMOS technology, ESSCIRC 2002, 491–494.
7 Design of a Demonstrator: Integrated VCO So far, the previous chapters have developed a detailed theory on integrated varactors, giving optimization and modeling methods that enable an integrated circuit designer to obtain an a priori estimation of how the designed varactor will behave. This represents a significant step forward in IC design, since one of the main voids encountered by designers until now was a notable difference between the simulation results and the onwafer measurement results. To demonstrate the benefits of the optimization and modeling method presented previously, this chapter will present the design of a demonstrator on which a varactor designed with the presented method has been used. Section 7.1 explains the selection of the most appropriate type of demonstrator for verifying the improved specifications of a circuit by optimizing the varactor. Section 7.2 then presents some general considerations about the VCO and Section 7.3 looks at the design of the implemented demonstrator. 7.1 CIRCUITS INCLUDING VARACTORS As passive elements, varactors are always part of more complex circuits. Examples of these circuits include: passive filters; selective gain amplifiers; voltagecontrolled oscillators with LC tank. As the following section shows, the performance levels of the above circuits vary significantly depending on the figures of merit of the varactor Design and Characterization of Integrated Varactors for RF Applications and E. Herna´ndez # 2006 John Wiley & Sons, Ltd
´I. Gutie´rrez, J. Mele´ndez
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DESIGN OF A DEMONSTRATOR: INTEGRATED VCO
used. Therefore it is not only necessary to design goodquality varactors, but also the designer must be reasonably sure that the model used in the simulation is in keeping with the real performance of the varactor. 7.1.1 Influence of the Figures of Merit of the Varactor
This section studies the influence of the quality value (QV ) and the capacitance value (CV ) of the varactor on the circuits in which it can be included. After this analysis, a decision will be taken as to which of the circuits given can be used as the best demonstrator of the optimization of a varactor. 7.1.1.1 Passive Filter Filters are elements that are used to block certain frequencies established by the designer at the same time as they allow others through with the lowest possible return loss. More specifically, passive filters seek to fulfil this objective through the use of lossless passive elements such as inductors, capacitors and varactors. The main advantage of this type of filter is that power consumption is zero in comparison with the usually high consumption of active filters. However, the main disadvantage is that the integration of a highorder filter, which therefore has good selectivity, requires a high number of components and occupies a relatively large area of silicon. In view of the wide variety of filters available, this section focuses on bandpass filters (BPF). Figure 7.1 shows the diagram of two BPF filters. The first is order one and the second is order five. According to (Sainz, 2005),
+ –
+ –
Figure 7.1 Circuit diagrams of two passive BPFs.
CIRCUITS INCLUDING VARACTORS
91
this is the highest order that can be integrated nowadays and obtains results similar to passive filters implemented with external components. The two filters shown in Figure 7.1 would have a fixed frequency spectrum since they are made up of constant value inductors and capacitors, and none of the elements would enable the adjustment of the centre frequency of the filter. Should it be necessary to design a filter that enables the modification of a parameter such as the bandpass frequency, one of the capacitors must be replaced by a varactor. The following analysis is of a firstorder filter, but the results given can be applied to any filter of a higher order and also to lowpass, highpass and bandstop filters. Equation (7.1) calculates the central frequency of the firstorder filter from the previous figure. Replacing the constant value capacitor C1 with a variable capacitance varactor CV, it should be possible to tune the central frequency of the filter in accordance with the designer’s needs. f0 ¼
1 pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ : 2p L1 C1
ð7:1Þ
Figure 7.2 shows how, on the one hand, the variation of the varactor quality QV affects the central frequency and, mainly, the insertion loss and Filter frequency spectrum 0 –5
Insertion loss (dB)
–10 –15 –20 –25 –30 –35 –40 –45 –50 1,00E+09
1,00E+10 Frequency(Hz)
Figure 7.2 Variation of the insertion loss and bandwidth.
92
DESIGN OF A DEMONSTRATOR: INTEGRATED VCO
filter bandwidth. As shown in Equation (7.1) and in Figure 7.2, a poor modeling of the varactor will affect the output frequency, the insertion loss and the bandwidth. On the other hand, the optimization of the varactor specifications will affect mainly the last two factors and, to a lesser extent, the central filter frequency.
7.1.1.2 Selective Gain Amplifier Figure 7.3 shows a simplified diagram of a typical selective gain amplifier. A selective gain amplifier is a circuit that amplifies a signal of a certain frequency but does not amplify the signals that are off that frequency. To achieve this, a tank circuit is used as the amplifier load. This not only filters the frequencies that are adjacent to the desired frequency, but also does so with a high gain and low noise at tank resonant frequency
M3
M3
GND
GND
GND
Figure 7.3 Simplified schematic of a selective gain amplifier.
93
CIRCUITS INCLUDING VARACTORS
(see Equation (7.2)): f0 ¼
1 pﬃﬃﬃﬃﬃﬃﬃﬃﬃ ; 2p LCT
ð7:2Þ
where CT represents the total capacitance, including the capacitance of the varactor and the parasitics appearing due to the circuit configuration. At resonant frequency, supposing that the qualitylimiting element is the varactor, the LC tank behaves like a resistive load that can be calculated with Equation (7.3): RLoad ¼ RV ðQ2T þ 1Þ: 1 ; QT ¼ CV R V
ð7:3Þ
where RLoad ( ) is the equivalent resistance that acts as the amplifier load, RV ( ) is the resistance of the varactor CV (F) is the capacitance of the varactor, and QT is the tank quality. Given that the gain of the amplifier can be calculated as: AV Kgm RLoad
ð7:4Þ
where AV is the gain of the amplifier, gm (mA/V) is the transconductance of the input transistors and K is a proportionality constant. It can be observed that to obtain a high gain, the quality of the varactor must be high and, therefore, its resistance value must be as low as possible. On the other hand, the approximate noise figure of the amplifier can also be seen as a function of: F¼f
gXðQT ; Q2T Þ o0 ; aQT ot
ð7:5Þ
where F is the noise figure, g is a coefficient representing the thermal noise of the channel, X is a function including terms proportional to QL , a is a coefficient that takes into account the length of the MOS channel, o0 (Hz) is the amplifier resonance frequency, and ot (Hz) is the transition frequency. As shown, the noise figure also depends on the quality of the varactor. This again demonstrates that a good optimization of the figures of merit of the varactor will improve the performance of the amplifier that is designed.
94
DESIGN OF A DEMONSTRATOR: INTEGRATED VCO
Similarly, a good modeling of the varactor will enable the designer to obtain results that are in keeping with the simulations. 7.1.1.3 Voltagecontrolled Oscillator with LC Tank A voltagecontrolled oscillator (VCO) should provide a frequency reference that is as pure as possible and which can be adjusted by external voltage. In a VCO, the varactor is of key importance in that it enables the variation of the oscillation frequency as the voltage applied between the corresponding terminals varies. Figure 7.4 shows a simplified diagram of a VCO. The oscillation frequency of this VCO is given by Equation (7.6): fosc ¼
1 pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ; 2p LðCV þ CP Þ
ð7:6Þ
where fosc (GHz) is the oscillation frequency of the VCO output signal, L (nH) is the inductive value of the coil, CV (pF) is the capacitance value of
Out 2
Out 1
CND
Figure 7.4
Simplified schematic of a VCO.
95
CIRCUITS INCLUDING VARACTORS Output power
Ideal output Real output Adjacent bands
Spurious signals
Frequency
Figure 7.5
Frequency spectrum of the ideal and real output of an oscillator.
the varactor, and CP (pF) is the capacitance value of the parasitic capacitances of the circuit. Given that the factor CV will vary with the variation of the voltage applied between the terminals of the varactor, the output frequency will also vary. In addition, as the oscillator is a frequency reference, the aim is for the frequency generated to be as pure as possible, i.e. it should contain the lowest possible energy on the frequencies that are adjacent to the oscillation frequency. Figure 7.5 shows a graphic illustration of the ideal oscillator output and the real oscillator output. The phase noise of an oscillator is defined as the noise power on a band of 1 Hz at a frequency of o of the oscillation frequency, divided by the power of the carrier. One of the most frequently used methods for estimating the phase noise of an oscillator is that of (Craninckx and Steyaert, 1998). Supposing that the oscillator is an LTI system, the estimation for the calculation of the phase noise given in Equation (7.7) is obtained: "
kTReff ð1 þ AÞðo0 =oÞ2 PNfog ¼ 10 log 2 =2 Vmax Reff ¼ RL þ RC þ
1 RP ðo0 CÞ2
# ð7:7Þ
;
where PNfog (dBc/Hz) is the phase noise of the oscillator at a frequency of o Hz, k is the Boltzman constant, T (K) is the absolute temperature, Reff ( ) is the effective resistance of the tank, A is an empirical factor that
96
DESIGN OF A DEMONSTRATOR: INTEGRATED VCO
models the excess noise introduced by the negative resistance amplifier, o0 (Hz) is the oscillation frequency, Vmax (V) is the output wave amplitude, RL ( ) is the resistance of the coil, RC is the resistance of the varactor ( ), RP is the conductance in parallel with the tank circuit ( ), and C (pF) is the capacitance of the tank circuit. As shown, both the resistance and capacitance of the varactor are parameters which directly affect the phase noise value obtained. Therefore the optimization of the quality factor of a varactor will improve the phase noise of the oscillator that has been designed. In addition, the improved modeling of the component will imply greater precision when finding the exact operating frequency of the VCO, together with its tuning range. 7.1.2 Choosing the Demonstrator As shown in the previous sections, the figures of merit of the varactor have a significant influence on the behaviour of the circuits that are designed. However, it has been considered that owing to the use of communication channels on increasingly narrower bands, one of the critical parameters in the design of RF transceivers is oscillator phase noise. Consequently the demonstrator that has been designed to verify the appropriateness of the design and modeling method presented in this book is an integrated voltagecontrolled oscillator with an LC tank. It will be demonstrated that the given design method leads to very good correspondence between simulations and measurement results.
7.2 GENERAL CONSIDERATIONS This section gives an overview of the purpose and usefulness of the oscillators that have been designed, together with the minimum specifications with which they must comply. In addition, certain considerations related to the architecture of the presented VCO will be discussed. 7.2.1 Introduction The oscillator that is to be designed as a demonstrator will, in turn, form part of a transceiver circuit for television signals called an adjustable singlechannel converter (ASCC). The simplified block diagram of this circuit is shown in Figure 7.6.
97
GENERAL CONSIDERATIONS
36.125 MHz 50.5 – 858 MHz 50.5 – 858 MHz
BPF1
SAW
BPF2
VC01
L01
L02
VC02
PLL1
PLL2
PLL3
PLL4
REF1
REF2
REF3
REF4
Figure 7.6
Block diagram of the ASCC.
The circuit shown here must be capable of receiving both analog and digital TV signals on any of the channels of the band from 50.5 to 858 MHz (C2–C69) and processing it (amplification and filtering) so that it can be allocated to any of the channels on the same band at the output. The need for complying with the specifications that enable operation with analog and digital TV signals is due to the fact that both standards will exist together for some years. In comparison with a more common TV tuner, this new proposed model provides the presence of a final frequency upconversion stage, which enables the allocation of any intermediate frequency (IF) channel on the TV band (C2–C69). This increases the applications in comparison with a conventional tuner, since this new feature means that it can be used, for example, with repeaters. Figure 7.7 shows two possible applications of the ASCC TV tuner. The first is a CATV header channel processor. Its mission consists of receiving any channel from the bands allocated to the TV service, processing the signal on an intermediate frequency and placing it on any of the channels on the same band. It also usually includes a microprocessor control and digital status presentation system. The second application is a satellite receiver/ modulator for CATV or MATV and consists of a unit that can tune a channel on the intermediate frequency of a satellite (900–2050 MHz), obtain video and audio signals and modulate an RF signal on any of the channels allocated to the terrestrial TV service. 7.2.2 VCO Specifications The specifications that are to be met by the oscillator have been obtained from those which must be met by the ASCC (shown in Table 7.1). In
98
DESIGN OF A DEMONSTRATOR: INTEGRATED VCO
C2–C69
C2–C69
C2–C69
Power amplifier
TV tuner
Microprocessor
Display
Analog system: TUNER DEMOD FM
Video Digital system: TUNER DEMOD QPSK DECODER
IF = 36 MHz AM modulator
C2–C69
TV tuner
Power amplifier
C2–C69
Audio
Figure 7.7
Possible applications of the ASCC TV tuner.
addition, there are other restrictions, such as the input and output frequencies and the intermediate frequency of the SAW filter, which will help calculate the specifications of the VCO. Taking into account the above, the specifications shown in Table 7.2 are obtained.
Table 7.1 Parameter SNR IMD3 Input power Output power
Figures of merit of the ASCC. Value >60 dB >54 dB
40 20 dBm > 33.5 dBm
Table 7.2
99
GENERAL CONSIDERATIONS Figures of merit of the VCO.
Frequency
PN @ 100 kHz
Output power
1811.125 MHz
> 92.8 dBc/Hz
> 3 dBm
As shown, the oscillator that is to be designed is a fixedfrequency oscillator. In this case, it would seem sufficient to use a tank circuit comprising an inductor and a fixed capacitor to achieve the desired resonant frequency. The problem is that the manufacturing process dispersions of the inductor, the capacitor and the transistors (with the corresponding variation in the parasitic capacitances) create uncertainty with regard to the final oscillation frequency. The way of correcting this uncertainty is to use a varactor, which makes it possible to vary the capacitance value in order to correct the possible dispersions due to the manufacturing process. It can also be deduced that the tuning range of the varactor must not be high. Consequently, when designing the varactor, priority should be given to obtaining good quality over the tuning range. In addition, as analysed in Banerjee (1998), the phase noise of a PLL within the loop bandwidth is filtered and is therefore usually lower than that of the oscillator, whereas outside the bandwidth, the PLL noise is that of the oscillator itself. As, in principle, there is no certainty that we are not within the PLL bandwidth at a frequency distance of 100 kHz from the carrier, the oscillator must comply with the phase noise specifications on its own. Accordingly, in the worstcase scenario, the specifications will be met; otherwise, the phase noise will be better than necessary, which is always an advantage. The output power must be quite high because the oscillator acts as a frequency reference for an integrated mixer that is a Gilbert cell with an ABclass input. Consequently, in order to carry out the switching of the mixer input transistors correctly, a high LO power is required. Finally, the advantages of the architecture of an integrated oscillator with a tank circuit which have led to this being chosen as the most appropriate design option are: It can be fully integrated. This reduces the number of external components to a minimum, as well as the number of external connections and, therefore, the parasitic effects of the bonding wires.
100
DESIGN OF A DEMONSTRATOR: INTEGRATED VCO
Phase noise values of 100 dBc/Hz @ 100 kHz of a 2 GHz carrier have been reported (Craninickx and Steyaert, 1998). This means that it is feasible that it will comply with the phase noise specifications. There are various options for implementing an integrated oscillator with a tank circuit. In general, this type of oscillator comprises one resonant circuit and one active circuit which compensates the losses of the former, together with a feedback network. Depending on which of the different architectures for implementing the active circuit is chosen, the negative conductance added to the tank circuit will be different. 7.2.3 Active Circuit There are various active circuits that are used to compensate for the tank losses and each has its own particular specifications. This section gives the different aspects that have been taken into account when designing the active circuit of the oscillator presented here. 7.2.3.1 Differential or Singleended One of the first differences taken into account when studying oscillator architectures is the use of a differential or a singleended structure. The advantages of the differential design are:
Common mode rejection, i.e. signals such as digital noise and the coupling of noise with the substrate. Due to its configuration, a differential structure eliminates all the signals in common mode. Therefore the influence of the noise from the power source, of the coupling of the noise with the substrate and the unforeseen parasitic effects is eliminated or greatly attenuated. Improved isolation. The evenorder harmonics are greatly attenuated. The effect of packaging is reduced, making the circuit insensitive to unforeseen parasitic effects due to its symmetric structure. There is also a reduction in the dependence of the circuit on external variables such as temperature, etc. The chip ground plane quality and the effect of the external connections are negligible. The noise introduced by the current source of the oscillator is attenuated due to the fact that it is common to both branches of the circuit. The phase noise is reduced (Hajimiri and Lee, 2000).
GENERAL CONSIDERATIONS
The disadvantages are:
101
A balun may be necessary to transform the differential output signal into a singleended one. This adds extra losses. The design requires approximately twice as many components, which means that the occupied area is also almost double. The power consumption of the circuit is also almost double. In the specific case of the oscillator that has been designed, the mixer to which it is connected uses a Gilbert cell configuration, which requires a differential local oscillator input, which makes the use of the extra balun unnecessary. Consequently, despite the fact that the area and power consumed are greater, an oscillator with a differential architecture is implemented. 7.2.3.2 MOS or HBT Transistors The choice between the use of MOS or HBT transistors is determined in this case by the technology that is to be used in the manufacture of the VCO. The main disadvantage with using HBT transistors is that the breakdown voltage of the baseemitter connection of these transistors is 1.5 V. This greatly limits the maximum output power that can be achieved so that the oscillator that has been designed would not obtain an output power greater than approximately 9 dBm, which is nowhere near the required
3 dBm. Therefore, and as a result of the impossibility of changing over to another manufacturing technology, the oscillator has been implemented with a crossedcoupling architecture based on MOS transistors. 7.2.3.3 NMOS, PMOS or CMOS Configuration Once the decision has been taken to integrate an oscillator with MOS transistors, there are three different basic configurations depending on whether NMOS or PMOS transistors or both types (CMOS) are used. The architecture that uses only PMOS transistors has very evident disadvantages in comparison with the other two since very large transistors are required. This affects the maximum working frequency that can be obtained. In addition, they require a very high power consumption. A similar problem is present, but to a lesser extent, in the active circuits that use only NMOS transistors.
102
DESIGN OF A DEMONSTRATOR: INTEGRATED VCO
However, the NMOS architecture has the advantage, among the PMOS, of being able to work with a low power voltage, since it only needs to bias two transistors to saturation point: that of the active circuit and that of the power source. However, the power voltage at which the VCO has to work is fixed at 5 V. This voltage is sufficiently high to use the CMOS stage without any biasing or supply problems. Consequently the biasing is not a decisive parameter when selecting the stage. The NMOS stage enables a greater voltage swing at the output. This would make it possible to work for longer periods in the current limiting region and obtain a lower phase noise. However, as the power supply is 5 V this is not the decisive factor since, even if the CMOS stage were used and supposing a voltage drop of 1 V in each of the three transistors, the output voltage swing could be up to 2 V. Supposing a gain in the output stage of 0.5, this would make it possible to work with power levels of up to 4 dBm within the current limitation region, which is considered as sufficient margin. Furthermore, the main disadvantage with the NMOS configuration, among the CMOS, is that it requires a high biasing current to obtain a high transconductance. This can cause power consumption problems. This problem is solved by using a CMOS configuration in which the current is reused to achieve a double amplification to obtain higher conductances. Therefore, with a CMOS stage, it is possible to increase the amplitude of the oscillator output voltage and therefore the output power with the same power consumption at the same time as the phase noise is reduced as a result of this increase in the output power. As stated in Herna´ ndez et al. (1999), the CMOS architecture has one fundamental advantage over the NMOS architecture: it has a better ratio between phase noise and power consumption. Finally, the fact that there are twice as many transistors in the design has hardly any effect on the total area of the design, since the area is basically determined by the size of the tank circuit. Consequently, the CMOS configuration is chosen as the optimum architecture for the design of the oscillator. Within the configuration of CMOSarchitecture oscillators, there are two different variants as shown in Figure 7.8. Although, according to Herna´ ndez et al. (1999), the phase noise of an oscillator biased by resistors (Figure 7.8(b)) is slightly better, the biasing by a current source (Figure 7.8(a)) offers other advantages such as the reduction of the influence of the process dispersions and greater stability with regard to temperature variations. Consequently, it was decided to implement the integrated oscillator with the crossedcoupling CMOS architecture biased by a current source.
103
GENERAL CONSIDERATIONS
(a)
Figure 7.8
(b)
Different biasing modes in a CMOS oscillator.
7.2.4 Analysis of the CMOS Oscillator Having chosen the architecture with which the oscillator is to be implemented, this section presents the actual design of the component. It begins with an analysis of the active circuit to find the conditions under which the oscillation is produced. Similarly, the frequency at which the oscillation is produced is also calculated. The analysis of the oscillation conditions of the CMOS VCO is based on the schematic shown in Figure 7.8(a). Replacing the transistors with the corresponding highfrequency linear model gives the equivalent linear incremental circuit for the VCO. This is shown in Figure 7.9. Based on this equivalent circuit, it is possible to calculate the admittance generated by the active circuit as the ratio between the current iT and the voltage vT applied.
A
B CGSN
Figure 7.9 Equivalent highfrequency circuit of the CMOS oscillator.
104
DESIGN OF A DEMONSTRATOR: INTEGRATED VCO
The subscript N corresponds to the NMOS transistors and the subscript P to the PMOS transistors. Applying Kirchhoff’s current law to nodes A and B, we can calculate the current iT in accordance with the voltages of the nodes, vA and vB : iT ¼ vA ½ðCGSN þ CGSP þ CGDT Þs þ gdN þ gdP þ vB ½gmN þ gmP CGDT s ¼ vA ½gmN þ gmP CGDT s
ð7:8Þ
vB ½ðCGSN þ CGSP þ CGDT Þs þ gdN þ gdP : In this equation, gm and gd represent the transconductance and admittance of the different transistors. CGS and CGD consider the capacitance between the gate and source and between the gate and drain of the transistors. CGDT represents the sum of all the capacitances between the gate and the drain. We also know that: vT ¼ vA vB :
ð7:9Þ
Based on Equations (7.8) and (7.9), it is possible to calculate the admittance generated by this active circuit. If the parasitic capacitances of the transistors are eliminated and the output conductances are considered negligible, an approximation for low frequencies is obtained as: YT ¼
ðgmN þ gmP Þ : 2
ð7:10Þ
According to Herna´ ndez (2002) and Craninickx and Steyaert (1998), the transconductances of the NMOS transistors have to be equal to those of the PMOS transistors. In this case: YT ¼ gm :
ð7:11Þ
After studying the case of low frequencies, we now analyse the case of high frequencies. Equation (7.12) shows the real part of the admittance generated by the active circuit. The oscillator will work in a stable manner as long as the value of this real part is greater than the tank losses, i.e. as long as Equation (7.13) is true. YT ¼
D2
ABD ; þ 4oEF
ð7:12Þ
105
GENERAL CONSIDERATIONS
where
A ¼ o2 ½ðCGSN þ CGSP Þ2 þ 2CGDT ðCGSN þ CGSP Þ þ ðgmN þ gmP Þ2
ðgdN þ gdP Þ2 ; B ¼ 2ðgdN þ gdP þ gmN þ gmP Þ; D ¼ B2 þ 2oðCGSN þ CGSP Þ; E ¼ CGDT ðgdN þ gdP þ gmN þ gmP Þ þ ðCGSN þ CGSP ÞðgdN þ gdP Þ; and F ¼ ðCGSN þ CGSP Þ jjYT jj R 1 P :
ð7:13Þ
Furthermore, if we replace the voltage generator vT of Figure 7.9 by the tank circuit, the oscillation frequency can be calculated as: fosc ¼
1 pﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ; 2p LðC þ 2CGDT þ CGSN þ CGSP Þ
ð7:14Þ
where L is the inductance of the tank inductor, C is the total capacitance of the two varactors connected in series and CGSN and CGSP are the parasitic capacitances between gate and source of the NMOS and PMOS transistors, respectively. This shows that the frequency is affected by the values of the parasitic capacitances which are, in turn, determined by the size of the transistors. Not only will the value of the oscillation frequency depend on these parasitic capacitances, but so will the tuning range of the VCO. Since the only capacitance whose value can vary is that of the varactor, the lower it is with regard to the total capacitance, the lower the frequency range in which the oscillator will work. Based on the expressions of Equations (7.10) and (7.12), we can deduce that to ensure the oscillation we need to increase the transistor transconductance as much as possible. This must be carried out without the transistor channel resistance affecting the overall admittance too much. In addition, we must remember that, according to Equation (7.15), to increase gm the only option is to increase the width of the transistors or the current consumption. Increasing the size of the transistors involves
106
DESIGN OF A DEMONSTRATOR: INTEGRATED VCO
increasing the parasitic capacitance they introduce, which implies a reduction of the operating frequency and the tuning range of the VCO: sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ 2K 0 IBIAS W gm ¼ ; Leff
ð7:15Þ
where gm (mS) is the transconductance of the transistor, K0 is a constant that depends on the manufacturing process, IBIAS (mA) is the current flowing through the transistor, W (mm) is the transistor channel width, and Leff (mm) is the effective transistor channel length.
7.3 VOLTAGECONTROLLED OSCILLATOR This section presents the design of the oscillator and its simulation results. Having manufactured the oscillator, the measurement results are also shown and compared with the previous ones. Finally, the oscillator was implemented in a printed circuit board (PCB) with a PLL and the results obtained are discussed. 7.3.1 Design of the Tank Circuit Having studied the form of the active circuit that is to be designed, we study the design of the passive components that make up the tank circuit. The integrated inductor will be designed according to the rules given in Aguilera and Berenguer (2003) and the measurements and model obtained will be presented. The integrated varactor has been designed according to the rules obtained in the previous chapters, its measurements and model will also be shown. This section will conclude by calculating the equivalent conductance of the tank circuit that is to be compensated by the active circuit. 7.3.1.1 Design of the Integrated Inductor Given that the oscillator that is to be designed is differential, the best option for implementing the integrated inductor is the use of balanced or centretapped coils. Centretapped coils are very useful for the design of NMOSarchitecture oscillators since they have a central connection to which the
Table 7.3 Geometrical data of the balanced coil design. Radius (mm) 105
107
VOLTAGECONTROLLED OSCILLATOR
Track width (mm)
Turns
Spacing (mm)
16
3.5
1.9
power supply can be connected. In this case, they have the disadvantage of not being completely symmetrical and so the decision has been taken to use a balanced coil, which is symmetrical. The geometrical data of the designed coil are given in Table 7.3 and Figure 7.10 shows a microphotograph of the inductor. Once the inductor has been designed, it is measured to obtain the inductance and quality values at a frequency of 1.8 GHz as shown in Table 7.4. The inductance value obtained near 2 nH is a value which, a priori, is highly appropriate since: It is not too high, which would lead to the need for using a varactor with a low value and short tuning range, which would affect the oscillation tuning range of the VCO.
Figure 7.10 Layout of the inductor.
108
DESIGN OF A DEMONSTRATOR: INTEGRATED VCO Table 7.4
Measured data of the balanced inductor.
L1:8 GHz
Q1:8 GHz
2.15 nH
7.6
It is not too low, which would lead to the need for using a varactor with a high capacitance and, therefore, an increase in the consumption of the oscillator, as well as a higher occupied space. Once the inductor has been measured, it is modelled. The model chosen to characterize this inductor is a modified model. For identification purposes only, as the balanced inductor is a perfectly symmetrical coil, the model must also be symmetrical, dividing the resistance in series of the inductor into two equal parts. The diagram of this model is shown in Figure 7.11. Therefore, this is the inductor that will be used in the design of the voltagecontrolled oscillator. 7.3.1.2 Design of the Integrated Varactor Having measured the coil, it is now necessary to design the varactor that is to be used with it in the tank circuit. A good approximation of the VCO oscillation frequency can be calculated using the formula given in Equation (7.16): fosc ¼
1 sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ ; CV þ CP 2p L 2
ð7:16Þ
where, as it is a differential oscillator, the capacity of each varactor used must be divided by two. As shown in this equation, the oscillation frequency
Figure 7.11 Modified model for the inductor.
VOLTAGECONTROLLED OSCILLATOR
109
will be reduced basically due to the parasitic capacitances of the transistors on the active circuit. The coil substrate capacitances and those of the output stage will also have an influence on the output frequency, as well as those of the circuit metal tracks. A priori, it is not possible to know all the parasitic capacitances of the oscillator to perfection, but several of them can be estimated: those of the active circuit, which have been estimated at 1.2 pF; those of the output stage, which have been estimated at 300 fF; those of the inductor, which have been estimated at 350 fF.
The total estimated parasitic capacitance, without knowing the parasitic capacitances introduced by the layout metal tracks, is 1.85 pF. Given that all the parasitic capacitances are not known, it has been decided that the design will be made to reach an oscillation frequency of 1.9 GHz. With an inductance value of 2.15 nH and in accordance with Equation (7.16), we obtain a capacitance value for each varactor of approximately 2.8 pF. In addition, both the inductance value and all the estimated parasitic capacitances may vary as a result of the dispersions in the manufacturing process. This will make the tank oscillation frequency vary from the simulated frequency. Consequently, the varactor must be designed to have sufficient capacitance variation to be able to correct these dispersions. Therefore, a varactor must be designed which meets the condition of a value of 2.8 pF in the middle of the voltage variation range and, of course, with the highest possible quality factor. As commented previously, the main specifications of the designed oscillator are that it must function at a fixed frequency and with a low phase noise level. Consequently, the use of a varactor with the highest possible quality is required, taking a tuning range that is sufficient to compensate possible variations in the manufacturing process. According to the design rules given in Chapter 6 of this book, the varactors with the highest quality factor are PNjunction varactors and, in particular, island varactors; they have a tuning range which, as we shall see later, is sufficient for the oscillator to work at the correct frequency. Therefore, an island varactor has been designed with these specifications: minimum distance between islands to optimize quality; minimum size of islands, increasing the number of islands to reduce the resistance of the connection lines as far as possible without excessively affecting the occupied area;
110
DESIGN OF A DEMONSTRATOR: INTEGRATED VCO Table 7.5 Geometrical figures of the varactor. Dimensions (mm2) 170 170
Pþ islands
Pþ island width (mm2)
Island distance (mm)
22 22
3.6 3.6
1.8
this also increases the resonant frequency of the varactor, avoiding any influence on the functioning of the oscillator. The geometrical data of the designed varactor are given in Table 7.5 and Figure 7.12 shows a microphotograph of the varactor. Figure 7.13 shows the capacitance variation curves versus the control voltage, obtained through design estimations and measurements. As shown, the reliability of the model obtained is very high, where the greatest deviation between the predicted and measured capacitances is 3 %. As shown in the same graph, the varactor complies with the specifications required for the necessary capacitance value and the tuning range. Besides, its quality factor is around 45, which is good, and it will obtain good phase noise results. Therefore, this varactor will be the one used in the design of the oscillator which is to be designed together with the previously shown coil.
Figure 7.12 Microphotograph of the varactor.
111
VOLTAGECONTROLLED OSCILLATOR Capacitance variation vs control voltage 4.0 3.8
Capacitance (pF)
3.6 3.4 Simulated
3.2
Measured
3.0 2.8 2.6 2.4 2.2 2.0 0
1
2
3
4 5 6 Control voltage
7
8
9
10
Figure 7.13 Estimated and measured capacitance variation.
The capacitance variation range of this varactor can be calculated: g¼
Cmax Cmin 100: Cmax þ Cmin
ð7:17Þ
Accordingly, the capacitance variation range is 26.6 %. Thanks to this figure, it is possible to obtain an estimation of the frequency range in which the designed oscillator will work. The tuning range of the oscillator is estimated at approximately 275 MHz. The dispersions that can be produced in the manufacturing process and which affect the oscillation frequency are due to: Dispersions in the coil inductance – Mele´ ndez (2001) studies the dispersions in the inductance of a coil and quantifies them at 3 %. Dispersions in the design capacitances – they may vary between different technologies but they can be quantified at 10 %. With these figures, it is possible to calculate that in the worstcase scenario there would be a frequency variation of 250 MHz. As shown, this range of possible variation is covered by the varactor tuning range. Consequently, there should be no problem for the designed oscillator to operate correctly.
112
DESIGN OF A DEMONSTRATOR: INTEGRATED VCO
As can be seen, the varactor complies with the required specifications for capacitance value and tuning range and has a very high quality factor. Therefore, the designed varactor is adequate to form part of the tank circuit of the oscillator. 7.3.1.3 Calculation of the Equivalent Conductance of the Tank
Once the two elements that are to form part of the tank circuit have been designed, the equivalent conductance of the tank circuit must be calculated to find the conductance the active circuit has to generate in order to maintain the oscillation stable. An approximation of the tank conductance can be calculated if the simplest model for the varactor and the inductor is used, i.e. the capacitance and inductance in series with a resistance. Figure 7.14 shows the transformation that must take place in order to calculate the equivalent resistance. This calculation is made using the formula shown in Equation (7.18) (Craninickx and Steyaert, 1998). GEQ ¼
1 ðRL þ RC ÞðoCÞ2
:
ð7:18Þ
This gives an approximate value for the equivalent conductance of the tank of 222 or 4.51 mS. To obtain a more exact value, the simulator must be used. The tank circuit has been simulated as shown in the schematic given in Figure 7.15. With this circuit, it is possible to use an S parameters analysis to calculate the conductance of the tank as the real part of the admittance seen by the port. This is shown in Figure 7.16. The simulated conductance value is 4.85 mS.
Figure 7.14 Transformation of the equivalent conductance of the tank.
113
VOLTAGECONTROLLED OSCILLATOR
OUT
IN
P+
N+
N+
P+
VI
Port 1 r : so num = 1
gnd
Figure 7.15 Tank circuit simulation schematic.
7.3.2 Design of the Oscillator Having designed the components that will make up the tank circuit and having obtained its conductance value, the active circuit must be designed to compensate the losses resulting from this conductance in order to maintain a
5.20m
0: Y11 reS
Parameter Response
5.10m
5.00m
4.90m A
4.80m
4.70m
4.60m 1.70G A: (1.8111G 4.84968m)
1.74G
1.78G
1.82G
1.86G
1.90G
Frequency (Hz)
Figure 7.16 Simulation of the tank circuit conductance.
114
DESIGN OF A DEMONSTRATOR: INTEGRATED VCO
stable oscillation. According to the approximation of Equation (7.11), the conductance generated by the active CMOS circuit is equal to, and of the opposite sign to, the transconductance of each transistor. Therefore, each transistor must have a transconductance of 4.85 mS. This will ensure the stable operation of the oscillator. However, this will not ensure that the oscillator will start up. To ensure this, the active circuit must add more conductance than that of the tank. Consequently, a safety factor generally of between two and three is normally used (Craninickx and Steyaert, 1998). The value of this safety factor is chosen as a trade off between the size of the transistors or the current consumption of the oscillator and the risk to be run regarding the start up of the VCO. As the tank components were tested and modelled before the manufacture of the oscillator began, the uncertainty is reduced to the parasitic effects introduced by the connection tracks between the elements in the oscillator. Accordingly, a safety factor of two was considered sufficient. Therefore, the conductance of each transistor must be 9.7 mS or approximately 10 mS. As shown later, the oscillator will be designed in such a way that the current flowing through it can be controlled by means of an external voltage. This will make it possible to vary the transconductance of the transistors and, therefore, the safety factor to ensure that the oscillator starts up. With the formulas given in Equations (7.11) and (7.15), it is only possible to calculate approximations of the conductance generated by the active circuit. To calculate the real conductance, a simulation of the circuit must be performed. Another condition to be taken into consideration is that the design variables cannot be given just any value. The following design rules can be established a priori: The greater the current, the higher the consumption. Furthermore, when designing the layout, the tracks must be wider and will therefore introduce greater parasitic capacitances. The greater the current, the greater the output signal power (Craninickx and Steyaert, 1998) (see Equation (7.19)). Too high output powers cause distortion on the signal in the output stage. This must also be given consideration when choosing the biasing current and the size of the transistors VOut ¼ Idc Reff ; where Reff is as calculated in Equation (7.7).
ð7:19Þ
115
VOLTAGECONTROLLED OSCILLATOR
The greater the width of the transistors, the greater the parasitic capacitances. However, the gate resistance can be reduced by making transistors with a greater number of ‘fingers’ and with a doublegate contact, as we shall see later.
The compromise that is to be reached between high current values and transistor widths of high values focuses on the choice of high current values (as long as they are not excessive) due to the fact that the component in which this oscillator is to be integrated will not be a mobile element, but rather part of a system that is to be connected to the mains. Accordingly, the current consumption is not such a critical part, although it cannot be increased too much since it would lead to problems with power dissipation and chip heating, with the consequent deterioration in operation. After various simulations, the results given in Table 7.6 were obtained. As shown, all the specifications are met.
7.3.3 VCO Measurements Having manufactured the oscillator, its specifications are measured to check that they correspond to the simulations and that it works as required. Figure 7.17 shows a microphotograph of the oscillator. Figure 7.18 shows the graph of the oscillation frequency in comparison with the varactor control voltage generated from the measured data and Figure 7.19 shows the oscillator output power in the whole tuning range. As can be seen, these measurements are in keeping with the simulations. Figure 7.20 shows the phase noise measurement on the 1811.125 kHz carrier. Table 7.7 shows a compilation of the specified, simulated and tested oscillator values. As shown, they meet all the specifications, including that corresponding to the oscillation frequency.
Table 7.6 VCO simulation results. Specification Oscillation frequency Phase noise @ 100 kHz Output power Power consumption
1811.125 MHz < 92.8 dBc/Hz > 3 dBm Minimum
Simulation 1665.2 1959.3 MHz
109 dBc/Hz 3.6 dBm 100 mW
116
DESIGN OF A DEMONSTRATOR: INTEGRATED VCO
Figure 7.17 Microphotograph of the oscillator.
As shown, besides meeting all the specifications, the measurements correspond with the simulation results except for the phase noise value obtained. The difference in the phase noise values is due to: The simulator takes into account only the 1=f 2 zone in which the gradient is 20 dB/dec. It does not simulate the flicker noise effect or the conversion of the thermal noise by the harmonics. The simulator does not take into account other effects that introduce phase noise: the noise introduced through the supply signals and those which control the oscillator and output stage currents.
117
VOLTAGECONTROLLED OSCILLATOR 1.975 1.925
Frequency (GHz)
1.875 1.825 1.775 1.725 1.675 1.625
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Control voltage
Figure 7.18 Oscillation frequency versus control voltage.
6 4 2
Output power (dBm)
0 –2 –4 –6 –8 –10 –12 –14 1.625
1.675
1.725
1.775
1.825
1.875
Frequency (GHz)
Figure 7.19 Oscillator output power vs frequency.
1.925
1.975
118
DESIGN OF A DEMONSTRATOR: INTEGRATED VCO
Figure 7.20 Measured oscillator phase noise.
Part of the phase noise measured is due to the lack of frequency stability of the oscillator as a result of the noise introduced through the varactor control voltage. This effect cannot be eliminated from the measurement and should be counted as phase noise. However, it is logical to think that when the oscillator is locked in a PLL, the phase noise value will improve. As shown, the proposed specifications have been met, but it is very difficult for a freerunning oscillator to work in a system due to its lack of frequency stability (Egan, 1999). Consequently, with a view to obtaining definitive results, it was decided to implement a printed circuit board on which this oscillator would be connected with a commercial PLL. Figure 7.21 shows a prototype of the PCB designed with the oscillator chip, the PLL and the other required components. Table 7.7
Oscillator measurement results. Specified
Oscillation frequency (MHz) PN @ 100 kHz (dBc/Hz) Output power (dBm) Power consumption (mW)
1811.125 < 92.8 > 3 Minimum
Simulated 1665.2 1959.3
109 3.6 100
Measured 1657.9 1949.1
98.3 3.3 105
VOLTAGECONTROLLED OSCILLATOR
119
Figure 7.21 Photographs of the PCB with its components.
7.3.4 PLL Measurements As shown in Figure 7.22, having performed the corresponding measurements, the device is seen to oscillate correctly at the required frequency of 1811.125 MHz. Besides being locked by the PLL, the output frequency is completely stable. The output power is approximately 0 dBm. It has been reduced in comparison with that of the freerunning VCO due to two causes: part of the oscillator power is fed back for control purposes; loss due to the PCB tracks and contacts.
120
DESIGN OF A DEMONSTRATOR: INTEGRATED VCO Agilent 12:12:37 Jul 26, 2002 Ref 0 dBm Samp Log 10 dB/
PAvg 100 W1 S2 S3 FC AA
∆ Mkr1 113 kHz –72.34 dB
Atten 10 dB 1×
Marker Select Marker 1 2 3 4 Normal
Delta
Marker ∆ 113.000 kHz –72.34 dB 1
Start
Band Pair Stop
Span
Span Pair Centre Off
Centre 1.811 GHz Res BH 1 kHz
VBW 1 kHz
Span 1 MHz Sweep 2.5 s (401 pts)
More 1 of 2
Figure 7.22 PLL output spectrum.
The measured phase noise is shown in Figure 7.23. As shown, on a carrier of 1811.125 MHz, at 100 kHz, this phase noise is 103.8 dBc/Hz. The phase noise has improved by approximately 5 dB in comparison with the onwafer measurement and is more similar to that expected as a result of the simulations.
Figure 7.23 PLL phase noise test results.
121
VOLTAGECONTROLLED OSCILLATOR
Figure 7.24 PLL output power vs frequency.
In turn, the oscillation range has been studied and, as shown in Figure 7.24, the PLL is capable of increasing in jumps of 125 kHz at least from 1675 MHz to 1940 MHz, without being unlocked. Finally, Table 7.8 shows the specifications that were required and the results of the measurements. It can be concluded that the design of the oscillator is good since it more than meets all the specifications. However, the consumption has also increased due to the consumption of the PLL itself. It must be pointed out that the power value of 0 dBm given in Table 7.8 does not correspond to that shown in Figure 7.24. This is because the losses have been added from the balun and the output cables. This chapter confirms that the method developed for optimizing varactors makes it possible to obtain good quality varactors and, more importantly, the modeling method makes it possible to obtain models for varactors that ensure little variation between component measurements and simulations. Table 7.8
PLL measurement results.
Oscillation frequency (MHz) PN @ 100 kHz (dBc/Hz) Output power (dBm) Power consumption (mW)
Specified
PLL test
1811.125 < 90 > 3 Minimum
1811.125
103.8 0 250
122
DESIGN OF A DEMONSTRATOR: INTEGRATED VCO
References Aguilera, J. and Berengwer, R. (2003) Design and Test of Integrated Inductors for RF Applications, Kluwer Academic Publishers, Holland. Banerjee, D. (1988) PLL Performance, Simulation and Design, National Semiconductors. Craninickx, J. and Steyaert, M. (1998) Wireless CMOS Frequency Synthesizer Design, Kluwer Academic Publishers, Holland. Egan, W.F. (1999) Frequency Synthesis by Phase Lock, John Wiley & Sons, Inc., New York, USA. Hajimiri, A. and Lee, T.H. (2000) The Design of Low Noise Oscillators, Kluwer Academic Publishers, Holland. Herna´ ndez, E. (2002) Integration of a TV frequency converter for SiGe 0.8 mm technology. Ph.D. Thesis, Tecnun, University of Navarra, Spain. Herna´ ndez, J. et al. (1999) Analysis of architectures for 1.8 GHz CMOS LCtank voltagecontrolled oscillators. Proceedings of DCIS 1999, 139–142. Mele´ ndez, J. (2001) Design of a direct conversion to low IF GPS frontend in CMOS technology. Ph.D. Thesis, Tecnun, University of Navarra, Spain. Sainz, N. (2005) Design of integrated passive filtresat SiGe and BiCMOS technologies for RF applications. Thesis, Tecnun, University of Navarra, Spain.
Appendix 1: Geometric Characteristics of Varactors A1.1 CHIP WITH THE VARACTORS USED IN THIS BOOK A microphotograph of the chip with the varactors used in this book is presented in Figure A1.1. This chip has the dimensions of 4 mm by 4.5 mm and includes PNjunction varactors, MOS varactors and a VCO with a PNjunction varactor.
A1.2 GEOMETRICAL CHARACTERISTICS OF THE PNJUNTION VARACTORS A1.2.1 Interdigit Varactors In this chip 18 interdigit varactors have been fabricated. Their geometrical characteristics are presented in Table A1.1. In Figure A1.2, a microphotograph of the interdigit PNjunction varactors is shown.
A1.2.2 Island Varactors Seven island varactors have been fabricated in this chip. Their geometrical characteristics are presented in Table A1.2. In Figure A1.3, a microphotograph of the island PNjunction varactors is shown.
Design and Characterization of Integrated Varactors for RF Applications and E. Herna´ndez # 2006 John Wiley & Sons, Ltd
´I. Gutie´rrez, J. Mele´ndez
124
APPENDIX 1: GEOMETRIC CHARACTERISTICS OF VARACTORS
Figure A1.1 Table A1.1 Varactor Var Var Var Var Var Var Var Var Var Var Var Var Var Var Var Var Var Var
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 17a
Microphotograph of the varactors used in this book.
Geometrical characteristics of the interdigit PNjunction varactors.
WPþ (mm)
WNþ (mm)
L (mm)
DðNþPþÞ (mm)
Number of islands
2 2 2 2 2 2 2 2 2 2 2 2 2.6 3.4 2.6 3.4 2 2.6
2 2 2 2 2 2 2 2 2 2 2 2 2.6 3.4 2.6 3.4 2 2.6
43.8 43.8 43.8 87.6 175.2 214.2 175.2 175.2 214.2 175.2 175.2 175.2 175.2 175.2 175.2 175.2 175.2 175.2
1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 2.3 2.8 3.6 1.8 1.8 2.8 2.8 1.8 2.8
13 25 49 25 25 25 49 61 61 25 25 25 25 25 25 25 25 25
125
GEOMETRICAL CHARACTERISTICS
Figure A1.2
Microphotograph of the interdigit PNjunction varactors.
Table A1.2 Geometrical characteristics of the island PNjunction varactors. Varactor Var Var Var Var Var Var Var
18 19 20 20a 21 22 23
Number of Islands Pþ Number of Islands Nþ 14 28 14 21 14 14 14 14 14 14 14 14 14 14
Figure A1.3
L (mm)
13 27 13 20 13 13 13 13 13 13 13 13 13 13
DðNþPþÞ (mm)
2 2 3 2 2 2 4
2 2 2 2 2.8 3.6 2
Microphotograph of the island PNjunction varactors.
Table A1.3 Geometrical characteristics of the matrix PNjunction varactors. Varactores Var Var Var Var Var
24 25 26 27 28
Number of Islands Pþ
W Nþ (mm)
L Pþ (mm)
30 24 16 16 22 22 22 22 22 22
2 2 2 2 2
2 2 2 2 3
W N well (mm) 1 1 1 2 1
A1.2.3 Matrix Varactors Five matrix varactors have been fabricated in this chip. Their geometrical characteristics are presented in Table A1.3.
126
APPENDIX 1: GEOMETRIC CHARACTERISTICS OF VARACTORS
Figure A1.4
Microphotograph of the matrix PNjunction varactors.
In Figure A1.4, a microphotograph of the matrix PNjunction varactors is shown. A1.3 GEOMETRICAL CHARACTERISTICS OF MOS VARACTORS Eight MOS varactors have been fabricated in this chip. Their geometrical characteristics are presented in Table A1.4. In Figure A1.5, a microphotograph of the MOS varactors is shown. Table A1.4 Varactor Var Var Var Var Var Var Var Var
M1 M2 M3 M4 M5 M6 M7 M8
LGate (mm) 0.8 0.8 0.8 0.8 1.6 2.4 0.8 0.8
Geometrical characteristics of the MOS varactors. WGate (mm) 10 10 10 20 10 10 10 10
Number of metals 1 1 1 1 1 1 2 1
Mode Accumulation Accumulation Accumulation Accumulation Accumulation Accumulation Accumulation Inversion
Number of transistors 36 90 192 192 192 192 192 192
GEOMETRICAL CHARACTERISTICS OF MOS VARACTORS
Figure A1.5 Microphotograph of the MOS varactros.
127
Appendix 2: Validation of the Predictions Provided by Equations of Chapter 5 In this appendix, the accuracy of the predictions provided by the equations of Chapter 5, taking as reference the adjusted to measurement PNjunction and MOS varactor models, is presented. These models have been described and analysed in Chapter 5. The parameters of each model are compared with the same parameters obtained from measurements. To obtain the model parameters it is necessary to use an automatic adjustment tool. In this case the Agilent ICCAP software was used.
A2.1 PNJUNCTION VARACTOR Each varactor was characterized as explained in Chapter 4. Then, the PNjunction varactor model parameters were obtained employing ICCAP. Figure A2.1 shows the employed model and the parameters that adjust best in the 1 GHz to 5 GHz frequency range, the impedance given by the model and the measurement results when Vpol ¼ 0 V. In order to validate the prediction given by the equations described in Chapter 5 through the comparison with the model parameters, six PNjunction varactors have been measured and their parameters have also been derived. The model parameters of these varactors are shown in Table A2.1. In Sections A2.1.1 to A2.1.6 each model parameter, obtained through measurement and model adjustment at a later stage, is compared with the predictions provided by the equations presented in Chapter 5. Design and Characterization of Integrated Varactors for RF Applications and E. Herna´ndez # 2006 John Wiley & Sons, Ltd
´I. Gutie´rrez, J. Mele´ndez
130
APPENDIX 2: VALIDATION OF THE PREDICTIONS PROVIDED
P port
N port 80.2 pH 0.57 pF
3.21 Ω
56.1 pH
315.2 Ω
267 fF
Figure A2.1 Var 1 model parameters.
A2.1.1 Inductance L1 The values of the parameter L1, obtained from the measurements of six varactors (Var 1, Var 2, Var 3, Var 5, Var 11 and Var 14), have been compared with the values obtained from Equation (5.1) taking into account the different geometry of the aforementioned varactors. Figure A2.2 presents this comparison where L1 _measured stands for the measured values and L1 _analytic represents the values obtained from the equations. From the results obtained in Figure A.2 it is possible to ensure that the total error between the measurement results and the equations is lower than 5 %. A2.1.2 Capacitance C1 The capacitance C1 depends on the biasing voltage so it is necessary to obtain from ICCAP the different values of C1 in the biasing voltage range.
Table A2.1 varactors.
Model parameters obtained through measurement for different PNjunction C1 ðpFÞ
Var Var Var Var Var Var
1 2 3 5 11 14
0.57 1.15 2.34 4.7 4.74 6.76
R1 ð Þ
C2 ðfFÞ
R2 ð Þ
L1 ðpHÞ
L2 ðpHÞ
3.21 1.58 0.82 0.36 0.58 0.41
267 371 533 960 1056 1142
315.2 173.1 85.39 41.3 37.14 32.47
80.2 38.3 20.9 145 146 148
56.1 31 18.7 110 121 112
131
PNJUNCTION VARACTOR
•
160 •
•
Var 11
Var 14
Inductance (pH)
140 120 100 80 60 40 20 0 Var 1
Var 2
Figure A2.2
Var 3
Var 5
L1 _measured versus L1 _analytic.
Capacitance (pF)
Figure A2.3 presents the measured values of C1 in the 0–4 V voltage range. It also presents the total capacitance of the varactors (Var 5). Following the same schedule employed in the previous section, the values of C1 in the biasing voltage range obtained from the measurement are compared to those derived from Equation (5.2) Figure A2.4 shows this comparison for Var 5 in the 0–4 V voltage range. The comparison shown in Figure A2.4 reveals that the total error between the measurement and the values obtained from Equation (5.2) is lower than 5.5 %.
6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0
Var 5 (pF)
0
0.5
1.0
2.0 1.5 2.5 Bias voltage (V)
3.0
3.5
4.0
Figure A2.3 C1 parameter variation with the biasing voltage of Var 5.
132
APPENDIX 2: VALIDATION OF THE PREDICTIONS PROVIDED
Capacitance (pF)
6 5 4 3 2 1 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Bias voltage (V)
Figure A2.4
C1 _measured versus C1 _analytic.
A2.1.3 Resistance R1
Resistance (mΩ)
In this section, the values of the parameter R1 obtained by measurement are compared with those given by Equation (5.3). R1 is a parameter which also depends on the biasing voltage. Consequently, it is necessary to obtain from ICCAP the different values of R1 with the biasing voltage. Figure A2.5 presents the values of the resistance R1 in the biasing voltage range for Var 5. Figure A2.6 presents the comparison between the values of R1 obtained from measurements (R1 _measured) and those derived by Equation (5.3)
700 650 600 550 500 450 400 350 300 250 200 0.0
0.5
1.0
1.5 2.0 2.5 Bias voltage (V)
3.0
3.5
4.0
Figure A2.5 R1 parameter variation with the biasing voltage of Var 5.
133
PNJUNCTION VARACTOR
700 Resistance (mΩ)
600 500 400 300 200 100 0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Bias voltage (V)
Figure A2.6 R1 _measured versus R1 _analytic.
(R1 _analytic) for Var 5 in the 0–4 V biasing voltage range. This comparison reveals that the maximum difference is below 9 %. A2.1.4 Inductance L2 The values of the parameter L2, obtained from the measurements of six varactors (Var 1, Var 2, Var 3, Var 5, Var 11 and Var 14), have been compared with the values obtained from Equation (5.4) taking into account the different geometry of the aforementioned varactors. Figure A2.7 presents
160
Inductance (pH)
140 120 100 80 60 40 20 0 Var 1
Var 2
Figure A2.7
Var 3
Var 5
Var 11
L2 _measured versus L2 analytic.
Var 14
134
APPENDIX 2: VALIDATION OF THE PREDICTIONS PROVIDED
this comparison where L2 _measured stands for the measured values and L2 _analytic represents the values obtained from the equations. From the results obtained in Figure A2.7 it is possible to ensure that the total error between the measurement results and the equations is lower than 5 %.
A2.1.5 Capacitance C2 The values of C2 obtained from the measurement of six varactors (Var 1, Var 2, Var 3, Var 5, Var 11 and Var 14) are compared with the values obtained employing Equation (5.5). Figure A2.8 illustrates the comparisons between measured values (C2 _measured) and those derived from equations (C2 _analytic). Figure A2.8 reveals that the maximum deviation between measured and predicted values for C2 is lower than 5.5 %.
A2.1.6 Resistance R2 The values for R2 obtained from the measurements of six varactors (Var 1, Var 2, Var 3, Var 5, Var 11 and Var 14) have been compared with the ones predicted by Equation (5.6). Figure A2.9 presents the comparison between the values of R2 obtained from the measurements (R2 _measured) and the values of R2 predicted by the equations (R2 _analytic). Figure A2.9 reveals that the maximum deviation between the measured and the predicted values is lower than 5 %.
1200
Capacitance (fF)
1000 800 600 400 200 0 Var 1
Var 2
Figure A2.8
Var 3
Var 5
Var 11
C2 _measured versus C2 _analytic.
Var 14
135
NMOS VARACTORS
350
Resistance (Ω)
300 250 200 150 100 50 0 Var 1
Var 2
Var 3
Var 5
Var 11
Var 14
Figure A2.9 R2 _measured versus R2 _analytic.
A2.2 NMOS VARACTORS This section compares the values of the model parameters obtained for NMOS varactors from the measurements to the ones given by the equations presented in Chapter 5. To obtain the values of the model parameters from measurements the ICCAP automatic adjustment tool has also been employed. For these varactors, the process used is the same as for PNjunction varactors. From ICCAP the model values for Var M1 (Appendix 1) are shown in Figure A2.10. Figure A2.10 shows the employed model and the parameters that best adjust in the 1–5 GHz frequency range, the impedance given by the model and the measurement results when Vpol ¼ 1 V. As PNjunction varactors, the measurements of five NMOS varactors are compared with the equations obtained in the Chapter 5. The model parameters of these varactors are shown in Table A2.2. In the next sections each model parameter will be compared with the results obtained with the equations from Chapter 5. A2.2.1 Inductance LG The values of the parameter LG, obtained from the measurements of five varactors (Var M1, Var M2, Var M3, Var M4 and Var M5), have been compared with the values obtained from Equation (5.7) taking into account the different geometry of the aforementioned varactors.
136
APPENDIX 2: VALIDATION OF THE PREDICTIONS PROVIDED
0.16 pH 63 pH
0.83 pH
0.73 pH
G
6.86 Ω
68 pH D/S
214 Ω
0.17 pF
Figure A2.10
Var M1 parameters model.
Figure A2.11 presents this comparison where LG _measured stands for the measured values and LG _analytic represents the values obtained from the equations. Figure A2.11 reveals that the maximum deviation between the measured and the predicted values is lower than 5 %.
A2.2.2 Capacitance Cox The values of Cox obtained from the measurement of the aforementioned varactors are compared with the values obtained employing Equation (5.8) Figure A2.12 illustrates these comparisons between measured values (Cox _measured) and those derived from equations (Cox _analytic). From the results obtained in Figure A2.12 it is possible to ensure that the total error between the measurement results and the equations is lower than 4.5 %.
Table A2.2 Csi (pF) R1 ð Þ Var Var Var Var Var
M1 M2 M3 M4 M5
0.73 1.76 3.73 7.34 7.51
6.86 2.76 1.32 0.68 2.53
Measurement values for NMOS varactor model. LG (pH)
LD=S (pH)
63 35 24 26 33
68 38 25 27 30
COX (pF) 0.83 1.96 4.31 8.17 8.95
RN2 ( ) CGD (pF) CNS (pF) 214 91 44 29 47
0.16 0.37 0.81 1.55 0.45
0.17 0.36 0.68 0.89 0.74
137
NMOS VARACTORS
70 60 50 40 30 20 10 0 Var M1
Figure A2.11
Var M2
Var M3
Var M4
Var M5
LG _measured versus LG _analytic.
A2.2.3 Capacitance CSi The capacitance CSi depends on the biasing voltage so it is necessary to obtain from ICCAP the different values of CSi in the biasing voltage range. Figure A2.13 presents the measured values of CSi in the 2–2 V voltage range. It also presents the total capacitance of the varactors (Var M2). For positive values of the bias voltage the CSi parameter presents high values. As this capacitance is in series with Cox , for these positive bias voltages the CSi parameter is negligible. Then, the CSi parameter has influence for negative values of the bias voltage, as is shown in Figure A2.14.
10 8 6 4 2 0 Var M1 Var M2 Var M3 Var M4 Var M5
Figure A2.12
Cox _measured versus Cox analytic.
138
APPENDIX 2: VALIDATION OF THE PREDICTIONS PROVIDED Var M2 140 120 100 80 60 40 20 0 –2.0 –1.5 –1.0 –0.5 0.0 0.5 Bias voltage (V)
Figure A2.13
1.0
1.5
2.0
CSi parameter variation with the bias voltage of Var M2.
In Figure A2.14 the influence of the CSi parameter on the total capacitance of Var M2 is represented. Following the same schedule employed for PNjunction varactors, the values of CSi in the biasing voltage range obtained from the measurement are compared with these derived by Equations (5.9) and (5.10). Figure A2.15 shows this comparison for Var M2 in the 2–2 V voltage range. From the results obtained in Figure A2.15 it is possible to ensure that the total error between the measurement results and the equations is lower than 6 %.
Var M2(pF) 12 10 8 6 4 2 0 –2.0
–1.5
–1.0
–0.5
Capacitance Var M2 (pF)
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0
Bias voltage (V)
Figure A2.14
CSi parameter variation with the bias voltage of Var M2.
139
NMOS VARACTORS
140 120 100 80 60 40 20 0 –1.0
–0.5
0.0
0.5
1.0
Bias voltage (V)
Figure A2.15
CSi _measured versus CSi _analytic.
A2.2.4 Capacitance CGD The value of the CGD capacitance parameter obtained from the measurements of the NMOS varactors (Var M1, Var M2, Var M3, Var M4 and Var M5) is compared with the values obtained employing Equation (5.11). Figure A2.16 illustrates these comparisons between measured values (CGD _measured) and those derived from equations (CGD _analytic). From the results obtained in Figure A2.16 it is possible to ensure that the total error between the measurement results and the equations is lower than 6 %.
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 Var M1
Figure A2.16
Var M2
Var M3
Var M4
Var M5
CGD _measured versus CGD _analytic.
140
APPENDIX 2: VALIDATION OF THE PREDICTIONS PROVIDED Var M2 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 –2.0
–1.0
0.0 1.0 Bias voltage (V)
2.0
Figure A2.17 R1 parameter variation with the bias voltage of Var M2.
A2.2.5 Resistance R1 Now, the values of the parameter R1 obtained from measurement are compared to those given by Equation (5.3). R1 is a parameter which also depends on the biasing voltage. Consequently, it is necessary to obtain from ICCAP the different values of R1 with the biasing voltage. Figure A2.17 presents the values of the resistance R1 in the biasing voltage range (2–2 V) for Var M2. Figure A2.18 presents the comparison between the values of R1 obtained from measurements (R1 _measured) and those derived by Equation (5.12) (R1 _analytic) for Var M2 in the 2–2 V biasing voltage range. This comparison reveals that the maximum difference is below 4 %.
2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 –1.0
–0.5
0.0
0.5
1.0
Bias voltage (V)
Figure A2.18
R1 _measured versus R1 _analytic.
141
NMOS VARACTORS
250 200 150 100 50 0 Var M1 Var M2 Var M3 Var M4 Var M5
Figure A2.19
RN2 _measured versus RN2 _analytic.
A2.2.6 Resistance RN2 The values for RN2 obtained from the measurements of the studied varactors have been compared with the ones predicted by Equation (5.13). Figure A2.19 presents the comparison between the values of RN2 obtained from the measurements (RN2 _measured) and the values of RN2 predicted by the equations (RN2 _analytic). From the results obtained in Figure A2.19 it is possible to ensure that the total error between the measurement results and the equations is lower than 6 %. A2.2.7 Capacitance CNS The values of CNS obtained from the measurement of five varactors (Var M1, Var M2, Var M3, Var M4 and Var M5) are compared with the values obtained employing Equation (5.14). Figure A2.20 illustrates these comparisons between measured values (CNS _measured) and those derived from equations (CNS _analytic). Figure A2.20 reveals that the maximum deviation between the measured and the predicted values is lower than 6.5 %.
A2.2.8 Inductance LD=S The last parameter of the NMOS model is the inductance LD=S . The values of the LD=S parameter obtained from the measurements of the studied varactors
142
APPENDIX 2: VALIDATION OF THE PREDICTIONS PROVIDED
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Var M1
Var M2
Var M3
Var M4
Var M5
Figure A2.20 CNS _measured versus CNS _analytic.
have been compared with the values obtained from Equation (5.15) taking into account the different geometry of the aforementioned varactors. Figure A2.21 presents this comparison where LD=S _measured stands for the measured values and LD=S _analytic represents the values obtained from the equations. From the results obtained in Figure A2.21 it is possible to ensure that the total error between the measurement results and the equations is lower than 4 %.
80 70 60 50 40 30 20 10 0 Var M1
Figure A2.21
Var M2
Var M3
Var M4
Var M5
LD=S _measured versus LD=S _analytic.
Appendix 3: Measurement of Oscillator’s Performance In Chapter 7 the design of the oscillator was described and its measurement results were presented. In this appendix the measurement setup used and some other factors related to the measurements are detailed. First of all some considerations about the layout of the oscillator, which could affect the measurement setup and its specifications, are described. Then the measurement setup used to characterize the oscillator will be presented and discussed. Finally the integrated oscillator was soldered in a PCB along with an external PLL. Again the measurement setup used and its most important characteristics are described.
A3.1 DESIGN OF THE LAYOUT The main problem encountered by an RF ASIC designer undertaking the layout of a circuit is the introduction of undesired and uncharacterized parasitic effects. With a good simulator the parasitic capacitances can be estimated and taken into account in the postlayout simulations, in order to estimate how they can affect to the final characteristics of the ASIC. The estimation of the parasitic resistance and, in particular, the parasitic inductance is very difficult and designers should take care to reduce those values in the design of the layout. In the case of the oscillator, the parasitic inductive effects can be neglected but the parasitic resistance can seriously affect the behaviour of the oscillator. Basically the resistance introduced in the interconnections of the tank circuit will be added to its equivalent conductance causing a reduction in the generated negative
Design and Characterization of Integrated Varactors for RF Applications and E. Herna´ndez # 2006 John Wiley & Sons, Ltd
´I. Gutie´rrez, J. Mele´ndez
144
APPENDIX 3: MEASUREMENT OF OSCILLATOR’S PERFORMANCE
conductance, and then running the risk of not assuring the startup of the oscillator. This implies that the metal connections between the tank circuit components should be designed with wide tracks and if possible with all the available metal layers connected in parallel in order to decrease its resistance. Thus, the first step is to design the layout of the tank circuit carefully. Once this has been done a rough estimation of the resistance can be obtained with the process parameters provided by the foundry. After calculating these parasitic resistances they should be included in the electrical scheme for simulation of the oscillator in order to check that they do not degrade the behaviour of the component. Figure A3.1 shows the layout of the tank circuit. All of the metal tracks are 20 mm wide and the two available metal layers are connected in parallel. The length of these tracks has been reduced to the minimum,
Figure A3.1 Layout of the tank circuit.
145
DESIGN OF THE LAYOUT
R55
R70
OUT
IN
var_2V N+ R54
P+ R62
R57
R56
R59
var_2V P+
P+ R79
R58
sp13_s
R51
gnd
Figure A3.2
Resistances included due to parasitic effects.
decreasing the distance between the inductor and the guard ring ground contacts. Figure A3.2 shows the electrical scheme of the tank circuit with the parasitic resistances included. Once the oscillator has been simulated with these new values, if it still fulfils the specifications, the design of the layout can be resumed. Figure A3.3 shows the final layout of the oscillator. There are five pads on the top of the layout that are included for connecting the circuit to the external voltages (DC voltage). The first pad from the lefthand side is the voltage supply. The second pad belongs to the pin of the varactor’s control voltage; it must be taken into account that this voltage cannot have a value which would cause the PN junction of the varactor to be directly biased. The third pad is a ground connection because the DC supply probes used have the PPGPP configuration (P¼power, G¼ground). The fourth and fifth pads are used to connect a voltage which controls the current flowing across the oscillator and the output buffer respectively. The five pads, on the bottom correspond to the outputs of the oscillator. This structure is designed to use differential signal measurement probes with an SGS configuration (S¼signal, G¼ground). The oscillator has a differential output so the output tone can be measured employing the three central pads. Two other ground pads have been added at each end in order to make possible a singleended measurement of each of the outputs with a GSG probe. Figure A3.4 shows a schematic lateral view of the three output pads. As shown, in the central ground pad all the available layers have been connected
146
APPENDIX 3: MEASUREMENT OF OSCILLATOR’S PERFORMANCE
Figure A3.3
Layout of the VCO.
in parallel in order to increase the parasitic capacitance to the substrate providing a better ground connection. On the other hand, the signal pads have been designed employing only the two metal layers, and below the pads, an Nþ diffusion connected to ground has been placed. In this way, a low resistivity path is given to allow the substrate coupling currents flowing to ground. Regarding the layout of the rest of the oscillator, as presented in Figure A3.5 the highest level of symmetry has been maintained. This
147
DESIGN OF THE LAYOUT
Figure A3.4
Lateral view of the output pads.
point is very important in a circuit with a differential configuration to avoid unbalances between the branches which increase common mode coupling. In oscillators, the unbalance of differential signals supposes phase noise increase too. Also symmetry collaborates in the reduction of effects on the circuit performance of the fabrication process dispersions. Common centroid configurations should be used to reduce the associated effects of dispersions as shown in Figure A3.5 for the N and PMOS transistors. Figure A3.5 also shows the presence of a high number of ground contacts to the substrate. The addition of these ground contacts between transistors is
Figure A3.5
Layout of the VCO transistors.
148
APPENDIX 3: MEASUREMENT OF OSCILLATOR’S PERFORMANCE
essential in order to obtain a good ground voltage around the transistors. Then substrate noise will not damage their behaviour and reducing the parasitic capacitances which could appear. All of these ground contacts must be connected to one of the four ground pads included in the layout. Moreover, to ensure a unique ground reference in the circuit and to avoid having different ground planes for each measurement equipment, all the ground pads should be shortcircuited by a structure surrounding the oscillator. Finally, it is worthwhile mentioning the presence of three high value capacitors between the pads of the external voltages and ground. These capacitors filter the possible noise coming through the voltage sources. This noise can affect the phase noise performance of the oscillator significantly. A3.2 MEASUREMENT SETUP To obtain good and reliable measurements for the oscillator an adequate measurement setup should be used. Figure A3.6 shows a block diagram of the measurement setup. In Table A3.1 all of the components employed for the measurement system are described. As a first step, in order to ensure that all is correctly connected, the circuit’s power consumption should be measured. For this reason two highprecision current meters have been included in series with the DC voltage sources. If the measured value corresponds with the simulated one and the active core has been correctly design, the oscillator should startup. Once the VCO has correctly started oscillating, the frequency can be measured accurately with the spectrum analyser. For measuring the output power delivered by the VCO some losses should be considered. These are:
SGS microprobes; Balun; RF wires; SMA adapters. DC source DC source
P P G P P
S G S
B A L U N
Spectrum analyser
Figure A3.6 Block diagram of the measurement setup.
Table A3.1 Measurement setup components. Component
Model
Spectrum analyser
149
MEASUREMENT SETUP
Manufacturer
Main characteristics
E4407B
Agilent
DC microprobe
DCQ05 PPGPP
Signal microprobe
ACP40 SGS
Hybrid coupler
3A055
Cascade Microtech Cascade Microtech Anaren
Voltage sources
E3631A
Hewlett Packard
RF wires
Sucoflex 104A
Suhner
RF wires
4899004
Rosenberger
SMA adapter
Suhner
DC block
23 SMA50051= 199 NE 7006
Weinschel Corp.
50 load
M1406
Weinschel Corp.
For frequencies