CMOS RF Modeling, Characterization and Applications

ected Topics in Electronics and Systei OS RF MODELING, CHARACTERIZATION AND APPLICATIONS CMOS RF MODELING, CHARACTERI...

Author: M. Jamal Deen | Tor A. Fjeldly

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ected Topics in Electronics and Systei

OS RF MODELING, CHARACTERIZATION AND APPLICATIONS

CMOS RF MODELING, CHARACTERIZATION AND APPLICATIONS

SELECTED TOPICS IN ELECTRONICS AND SYSTEMS Editor-in-Chief:

M. S. Shur

Published Vol. 6: Low Power VLSI Design and Technology eds. G. Yeap and F. Najm Vol. 7:

Current Trends in Optical Amplifiers and Their Applications ed. T. P. Lee

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Current Research and Developments in Optical Fiber Communications in China eds. Q.-M. Wang and T. P. Lee

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Signal Compression: Coding of Speech, Audio, Text, Image and Video ed. N. Jayant

Vol. 10: Emerging Optoelectronic Technologies and Applications ed. Y.-H. Lo Vol. 11: High Speed Semiconductor Lasers ed. S. A. Gurevich Vol. 12: Current Research on Optical Materials, Devices and Systems in Taiwan eds. S. Chi and T. P. Lee Vol. 13: High Speed Circuits for Lightwave Communications ed. K.-C. Wang Vol. 14: Quantum-Based Electronics and Devices eds. M. Dutta and M. A. Stroscio Vol. 15: Silicon and Beyond eds. M. S. Shur and T. A. Fjeldly Vol. 16: Advances in Semiconductor Lasers and Applications to Optoelectronics eds. M. Dutta and M. A. Stroscio Vol. 17: Frontiers in Electronics: From Materials to Systems eds. Y. S. Park, S. Luryi, M. S. Shur, J. M. Xu and A. Zaslavsky Vol. 18: Sensitive Skin eds. V. Lumelsky, Michael S. Shur and S. Wagner Vol. 19: Advances in Surface Acoustic Wave Technology, Systems and Applications (Two volumes), volume 1 eds. C. C. W. Ruppel and T. A. Fjeldly Vol. 20: Advances in Surface Acoustic Wave Technology, Systems and Applications (Two volumes), volume 2 eds. C. C. W. Ruppel and T. A. Fjeldly Vol. 21: High Speed Integrated Circuit Technology, Towards 100 GHz Logic ed. M. Rodwell Vol. 22: Topics in High Field Transport in Semiconductors eds. K. F. Brennan and P. P. Ruden Vol. 23: Oxide Reliability: A Summary of Silicon Oxide Wearout, Breakdown, and Reliability ed. D. J. Dumin

Selected Topics in Electronics and Systems - Vol. 24

CMOS RF MODELING, CHARACTERIZATION AND APPLICATIONS

Editors

M. Jamal Deen McMaster University, Canada

Tor A. Fjeldly Norwegian University of Science and Technology, Norway

, © World Scientific !•

New Jersey • London • Singapore • Hong Kong

Published by World Scientific Publishing Co. Pte. Ltd. P O Box 128, Farrer Road, Singapore 912805 USA office: Suite IB, 1060 Main Street, River Edge, NJ 07661 UK office: 57 Shelton Street, Covent Garden, London WC2H 9HE

British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library.

CMOS RF MODELING, CHARACTERIZATION AND APPLICATIONS Copyright © 2002 by World Scientific Publishing Co. Pte. Ltd. All rights reserved. This book or parts thereof, may not be reproduced in anyform or by any means, electronic or mechanical, including photocopying, recording or any information storage and retrieval system now known or to be invented, without written permission from the Publisher.

For photocopying of material in this volume, please pay a copying fee through the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, USA. In this case permission to photocopy is not required from the publisher.

ISBN 981-02-4905-5

Printed in Singapore by Mainland Press

PREFACE CMOS RF MODELING, CHARACTERIZATION AND APPLICATIONS M.JAMALDEEN Department of Electrical and Computer Engineering McMaster University, Hamilton, Ontario, Canada L8S 4K1

TOR A. FJELDLY UniK - Center for Technology at Kjeller, Norwegian University of Science and Technology, N-2027 Kjeller, Norway

The rapid evolution of semiconductor electronics technology is fueled by a never-ending demand for better performance at reduced cost, combined with a fierce global competition. For CMOS technology, this evolution is often measured in generations of three years, the time it takes for manufactured memory capacity to be increased by a factor of four and for logic circuit density to increase by a factor of between two and three. Technologically, this trend is made possible by a downscaling of transistor feature size (i.e., gate length) by a factor of two per two generations. Traditionally, the highfrequency properties of silicon MOSFETs have been considered inferior to other technologies, including silicon bipolar transistors and transistors based on III-V materials such as gallium arsenide. However, the CMOS technology has now reached a state of evolution, in terms of both frequency and noise, where it is becoming a serious contender for radio frequency (RF) applications in the GHz range. Cut-off frequencies of about 50 GHz have been reported for 0.18 urn CMOS technology, and are expected to reach about 100 GHz when the feature size shrinks to 100 nm within a few years. This translates into CMOS circuit operating frequencies well into the GHz range, which covers the frequency range of many of the popular wireless products today, such as cell phones, GPS (Global Positioning System), and Bluetooth. Of course, the great interest in RF CMOS comes the obvious advantages of CMOS technology in terms of production cost, high-level integration, and the ability to combine digital, analog and RF circuits on the same chip. Circuit design is an integral part of electronics technology, as important as the fabrication itself. Advances in the fabrication process always pose new challenges to the circuit designers. In order to be able to take full advantage of the new technology, the designers need to update their CAD (Computer Aided Design) tools with precise

V

vi

Preface

descriptions of the new devices in terms of models that can be implemented into circuit simulators. To be able to scale the devices for different operations, the models must be physics based to account for the complex dependence of the device properties on dimensions and other processing variables. The model parameters are derived from measurements and characterization of the devices. For RF CMOS, both the modeling and the characterization are challenging tasks that will be especially emphasized in this volume. Next follows a survey of the six contributions included in the first issue. Reliable measurements are a prerequisite for any sensible work on device modeling, especially so for high frequencies where the subtleties of the device behavior are plentiful. In the first chapter of this volume, F. Sischka and T. Gneiting discuss a wide range of issues related to RF MOSFET measurements, most of which also apply to RF device characterization in general. A thorough discussion of S-parameters, Smith charts, polar plots, network analyzer measurements, de-embedding techniques, and MOSFET test structures are included, and may serve as a valuable high-level tutorial on the subject of RF measurements. In the second chapter, M. Je, I. Kwon, H. Shin, and K. Lee discuss MOSFET modeling and parameter extraction for RF applications. They review several existing techniques, many of which are based on earlier work on three-terminal III-V devices, and examine the problems and shortcomings encountered in adapting these techniques to RF MOSFETs. The fact that the MOSFET is a four-terminal device and that the silicon substrate is lossy represent major challenges. The authors emphasize the importance of using charge conserving models, especially in conjunction with parameter extraction. They also present a new four-terminal modeling approach for handling RF MOSFETs. Finally, many of the remaining challenges in RF CMOS modeling and parameter extraction are discussed. RF MOSFET modeling is also the topic of the third chapter by Y. Cheng. Equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain physics-based RF models. Procedures for parameter extraction are also discussed. The analysis emphasizes the importance of certain capacitive and resistive components at high frequencies, in particular, the polysilicon gate resistance, the distributed channel resistance, and the components associated with the lossy substrate. An RF MOSFET model based on BSIM3v3 is presented, and good correspondence is obtained with experimental data obtained for different device geometries. Non-quasistatic effects are discussed in conjunction with this model. The modeling of flicker noise and thermal noise, and existing challenges in this area, are also discussed as part of this presentation. The fourth chapter by C.-C. Chen and M. J. Deen is dedicated to RF CMOS noise characterization and modeling. From small-signal models, such as some of those discussed above, it may be difficult to find analytical expressions for the fundamental noise parameters. As an alternative, the authors present techniques for calculating the noise parameters numerically. De-embedding techniques for extraction of RF MOSFET noise parameters and scattering parameters from experiments are also presented in detail, along with procedures for obtaining the frequency and bias dependencies of the extracted

Preface

vii

noise sources. Finally, this chapter includes some considerations for design of low-noise circuits, and a comparison of different noise models reported in the literature. Silicon-on-insulator (SOI) CMOS technology offers exceptional advantages in terms of low-power/low-voltage applications in digital as well as in RF and microwave circuits. In the fifth chapter, D. Flandre, J.-P. Raskin, and D. Vanhoenacker-Janvier present many aspects of the SOI CMOS technology, including SOI materials, devices and circuits, MOSFET properties, passive elements, and last but not least, the RF and microwave modeling and characterization of SOI MOSFETs. A fully developed SOI MOSFET macro model valid from DC to RF is presented, which includes transmission line effects related to both the gate and the channel. Comparisons with experiments show that this model is accurate up to 40 GHz for feature sizes down to 0.16 urn. Some examples of RF SOI CMOS applications are also presented. CMOS operating frequencies in the GHz range have been achieved through the down-scaling of device feature sizes into deep sub-micrometer dimensions. However, this has not come without penalties. Among these are the deleterious effects of hot carrier transport, brought on by a concomitant increase in the MOSFET channel electric field. The high field problem is, of course, rooted in the need for keeping the supply voltages relatively high to maintain high speed and reduce the subthreshold leakage current. Basically, the hot-electron effects lead to device degradation and, hence, represent a serious reliability problem. In the sixth chapter on RF CMOS reliability, S. Naseh and M. J. Deen consider the important issues of hot-carrier effects, and illustrate them by experimental results and simulations.

viii

Preface

M. Jamal Deen is professor of Electrical and Computer Engineering at McMaster University. He also holds the Canada Research Chair in ? •tSU't' Information Technology. He has also been professor of Engineering ; 'N ', Science at Simon Fraser University since 1993. Previously, he was "" ""* & with the CNRS Laboratory of Physics of Semiconductors Devices (LPCS), Grenoble (Visiting Scientist, summer 1998), faculty of Elec* trical Engineering (ECTM Lab), Delft University of Technology (Visiting Professor, summer 1997); Herzberg Institute of Astrophysics, National Research Council, Ottawa (Visiting Scientist, summer 1986); and Lehigh University, Bethlehem, Pennsylvania (Assistant Professor, 1985-86). His industrial experience includes a one-year visiting scientist position (1992-93) with the Device Technology Group, Northern Telecom, Ottawa, and several years of consulting and joint research with Northern Telecom, Bell Northern Research, Conexant, D&V Electronics, IBM, Mitel, National Semiconductor and Rockwell Semiconductor Systems. Dr. Deen holds the Ph.D. and M.S. degrees from Case Western Reserve University, Cleveland, Ohio, U.S.A. in Electrical Engineering and Applied Physics, and the B.Sc. degree from the University of Guyana, Guyana, S. America in Physics/Mathematics. As an undergraduate student, he won the Dr. Irving Adler's Prize for the best graduating mathematics student, and the Chancellor's Medal for the second best graduating student in the University in 1978. He was also a Fulbright Scholar from 1980 to 1982, an American Vacuum Society Scholar from 1983 to 1984, an NSERC Senior Industrial Fellow in 1993. He was given a Reward of Recognition Award, Silicon Technology Division, Northern Telecom in 1993, and won the IEEE 1993 Outstanding Branch Councillor and Advisor Award for Canada. Most recently, he was awarded a Canada Research Chair in Information Technology at McMaster University. Dr. Deen is a member of Eta Kappa Nu (the Electrical Engineering Honor Society, U.S.A) and the Electrochemical Society, a life member of die American Physical Society, and a Senior Member of the IEEE. Dr. Deen is also Editor, IEEE Transactions on Electron Devices; Executive Editor, Fluctuation and Noise Letters; and Member, Editorial Board, Interface — An Electrochemical Society Publication. Dr. Deen is the co-editor of six books or conference proceedings and the co-author of thirteen book chapters and one encyclopedia article. He has authored or co-authored more than 220 peer-reviewed scientific papers, 68 conference abstracts and extended abstracts, and 48 commissioned technical reports. He is also named an inventor in five patents.

Preface

ix

Tor A. Fjeldly received the M. Sc. degree in physics from the Norwegian Institute of Technology, 1967, and the Ph.D. degree from Brown University, Providence, RI, in 1972. From 1972 to 1994, he was with Max-Planck-Institute for Solid State Physics in Stuttgart, Germany. From 1974 to 1983, he worked as a Senior Scientist at the SINTEF research organization in Norway. Since 1983, he has been on the faculty of the Norwegian University of Science and Technology (NTNU), where he is a Professor of Electrical Engineering. He is presently with NTNU's Center for Technology at Kjeller, Norway. He was Head of the Department of Physical Electronics at NTNU, and he also served as an Associate Dean of the Faculty of Electrical Engineering and Telecommunication. From 1990 to 1997, he held the position of Visiting Professor at the Department of Electrical Engineering, University of Virginia, Charlottesville, VA, and from 1997 he has been Visiting Professor at the Electrical, Computer and Systems Engineering Department, Rensselaer Polytechnic Institute, Troy, NY. His research interests have included fundamental studies of semiconductors and other solids, development of solid-state chemical sensors, electron transport in semiconductors, modeling and simulation of semiconductor devices, and circuit simulation. He has written about 150 scientific papers, several book chapters, and is a co-author of the books Semiconductor Device Modeling for VLSI (Englewood Cliffs, NJ: Prentice Hall, 1993) and Introduction to Device Modeling and Circuit Simulation (New York, NY: Wiley & Sons, 1998). He is also a co-developer of the circuit simulator AIM-Spice. Since 1998, he has been a Co-Editor-in-Chief of the International Journal of High Speed Electronics and Systems, Singapore. Dr. Fjeldly is a Fellow of IEEE and a member of the Norwegian Academy of Technical Sciences, the American Physical Society, the European Physical Society and the Norwegian Society of Chartered Engineers.

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CONTENTS

Preface M. J. Deen and T. A. Fjeldly

v

RF MOS Measurements F. Sischka and T. Gneiting

1

MOSFET Modeling and Parameter Extraction for RF IC's M. Je, I. Kwon, H. Shin, and K. Lee

67

MOSFET Modeling for RF IC Design Y. Cheng

121

RF CMOS Noise Characterization and Modeling C.-H. Chen and M. J. Deen

199

SOI CMOS Transistors for RF and Microwave Applications D. Flandre, J.-P. Raskin, and D. Vanhoenacker-Janvier

273

RF CMOS Reliability S. Naseh and M. J. Deen

363

International Journal of High Speed Electronics and Systems, Vol. 11, No. 4 (2001) 887-951 © World Scientific Publishing Company

RF MOS MEASUREMENTS FRANZ SISCHKA Agilent Technologies GmbH, Munich, Germany THOMAS GNEITING admos, Frickenhausen, Germany

The trend to higher integration and higher transmission speed challenges modeling engineers to develop accurate device models up to the Gigahertz range. An absolute prerequisite for achieving this goal are reliable measurements, which have to be checked for data consistency and plausibility. This is especially true for RF data, and also for checking and verifying the applied de-embedding techniques. If this is not the case, RF modeling can become quite time consuming, with a lot of guesswork and ad-hoc judgements, and, basically, frustrating and not correct. If, however, the underlying measurements are flawless and consistent, and provided the applied the models are understood well, RF modeling becomes very effective and provides accurate design kits which will satisfy the chip designer's main goal: right the fist time.

1

Characterizing Devices From D C To High Frequencies

While the characterization of electronic components in the DC domain is relatively simple and only requires a voltmeter and an amperemeter, the frequency performance of the device is affected by magnitude dependence and phase shift of the currents and voltages. Furthermore, nonlinearities will lead to a spectrum of frequencies, although the device is only stimulated with a single, sine frequency. Last not least, inevitable capacitive and inductive parasitics, with values close to those of the very device under test (DUT), will contribute to the measurements and degrade the measured performance of the 'inner' DUT. [1,2]

In this paper, we will go step by step through the individual characterization issues and develop measurement strategies which will provide the base of accurate device modeling.

2

DC Measurements As A Prerequisite For RF Setups

Large signal modeling of a nonlinear component always begins with the characterization of its DC performance. Instead of power supplies, DC parametric analyzers with sourcemonitor-unit plugins (SMU) are applied. This allows to fully characterize the DUT (device under test) from fempto-Ampere up to its maximum current, and in all four i-v quadrants. I.e. forward and reverse currents and voltages, are measured with the same SMU unit. l

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F. Sischka & T.

Gneiting

Usually, in case of a transistor, all 4 terminals (including substrate) are connected to individual SMUs in order to avoid recabling during the forward and reverse measurements.

SMUs apply a Kelvin measurement to avoid parasitic series resistances. This measurement procedure, also known as the four-wire method, consists of a stimulating line (Force) with a second one in parallel (Sense) for every pin of the DUT. Fig. 1 illustrates this. Ohmic losses on the Force line are eliminated by the main operational amplifier (OpAmpl) in voltage follower mode. This means this OpAmpl output will exhibit a somewhat higher voltage than the desired test voltage at the DUT, because the test current generates some ohmic losses along the Force line. The Sense line, connected to the minus input of the OpAmpl, assures that the DUT is biased with exactly the desired test voltage.

SMU

OpAmp2 External Shielding

* L

Ohmic Losses

±

d

OpAmpl

r

•AM/v^-

-r

Dielectric Losses

I desired I voltage

Measurement Instrument

F

Inner Shielding Force

Sense Test Potential

Metering Lines

Fig. 1: The principle of Kelvin measurements (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

While this method compensates the DC errors, it does not cover dynamic measurement problems. For example, to avoid external electro-magnetic influences, both the Force and Sense cables are shielded. Such cable shieldings exhibit parasitic capacitances. Due to charging problems, these capacitances will affect the measurement speed and accuracy of our Kelvin measurement. As a simple example: assume we want to measure the reverse characteristics of a semiconductor diode. This means we need measure very low currents. Before the voltage steps to, e.g. -20 V, the quiescent voltage at the diode is zero. That is, the cable capacitors are not charged. When the negative voltage step occurs, these capacitances have to be charged, and the required current is provided by the OpAmpl. This could lead to either a mis-measurement (DUT current plus charging current) or a delay in the triggering of the actual current measurement (by some intelligent firmware in our measurement). To solve this problem, an extra inner shielding is applied between the hot metering lines and the outer cable shielding, called 'Guard'. This extra shielding is connected to a separate,

2

RF MOS Measurements

889

second 0pAmp2 which follows exactly the value of the desired test voltage. Now it is this auxiliary OpAmp2 which supplies the charging current for the test cables, while the main Op Amp 1 can start current measurements independently of this charging problem. That is, the inner measurement loop does not see the charging problem any more. Of course the point where Force and Sense are tied together must be as close as possible to the DUT. In case they aren't connected, an internal lOkOhm resistor at the . of the SMU acts as the Kelvin point. Another important fact is that the Guard comae i should never be connected to Force or Sense. Otherwise, the inner loop OpAmpl of the SMU would measure the DUT current plus the charging current of the auxiliary, second OpAmp2! In order to maintain the DC measurement accuracy, SMUs perform periodically an autocalibration. This means that the SMU disconnects its outputs from the DUT, measures possible offset voltages and currents and corrects it. This type of calibration does not require any action from the user. See publications [3] and [4] for details.

3

Capacitance Measurements At 1MHz

As discussed in the previous chapter, the DC voltages and currents can be measured directly. The calibration is periodically auto-executed by the instrument. After such a DC characterization, modeling engineers usually perform a so-called CV (capacitance versus voltage) measurement in order to characterize the device capacitances at a standard frequency of 1MHz. This frequency is high enough to allow a resolution down to a few fempto-Ampere (provided shielded probes are applied for e.g. on-wafer measurements), yet still low enough to neglect second order parasitics like resistors in series with the capacitors, or like inductances. For such CV measurements, the DC-bias is swept, a test frequency (1MHz) is applied to the DUT, and the instrument calculates the capacitance between the 2 pins of the DUT from the magnitude and phase of the device voltage and current. For CV meters, an auto-balancing method is typically applied. Fig. 2 depicts the simplified measurement scheme. The DUT is inserted in the feedback loop of an operational amplifier, and the system is stimulated with a 1MHz sine signal plus a DC bias. The feedback resistor R is precisely known, and the complex voltages VI and Vdut are measured. From the formula given in Fig. 2, the capacitance of the DUT can be calculated, assuming an equivalent schematic of either a resistor in series with the capacitor, or, commonly for modeling, a capacitor in parallel with a resistor (which is the bias-dependent diode resistance for example).

3

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Gneiting

CV meter applying the auto-balancing method DUT

V

V

Zx

sine frequency + DC bias

R

Hint: LOW potential is virtual ground !

Fig.2: schematic measurement principle of a CV meter (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

Again, test cables and fixtures contribute and affect the device characterization. Here, the measurement calibration consists of unconnecting the DUT, assuming an ideal OPEN condition and measuring the cables and their OPEN parasitics. The corresponding capacitance is then automatically subtracted from the subsequent DUT measurement. Note: If we are interested in the inner DUT's CV curves, i.e. without its surrounding test pads capacitances, we need to connect to an OPEN dummy structure during CV meter calibration. Such an OPEN dummy consists of all connection pads, lines to the DUT etc, but without the inner DUT itself. See Figures 34 and 46 for examples. When characterizing the capacitances of transistors, the open 3rd transistor terminal can be connected to the shielding potential, eliminating the effect of the unwanted capacitor. See Fig. 3, and also publication [5] for details.

taffies

w ©53®

QOSH

Measurement of CDG With the auto-balancing method, connecting the Source to the cable shielding potential, eliminates the effect of CGS

Fig. 3: measuring transistor capacitances with a CV meter (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

4

RF MOS Measurements

4

891

From Y-, Z-, And H-Parameters To S-Parameters

While the CV measurement is considered as a specific two-pin test condition, the situation changes for frequencies above 100MHz. The modeling device is now operated under its originally intended environment conditions: DC bias is applied to all the pins, and an additional small-signal RF excitation is applied. Now, the sine currents and voltages at all pins of the DUT are to be measured, with magnitude and phase. A natural choice for such characterizations would be Z-, Y- or H-parameters from linear two-port theory. These two-port parameters can be used to completely describe the electrical behavior of our device (or network), including any source and load conditions. For such parameters, we have to measure the voltage or current as a function of frequency and bias at the ports of the device. At high frequencies, however, it is very hard to measure voltage and current at the device ports. One cannot simply connect a voltmeter or current probe and get accurate measurements due to the impedance of the probes themselves and the difficulty to place the probes at the desired positions. Furthermore we have to apply either (AC-wise) OPEN or SHORT circuits as part of the Z-, Y- or H-parameter measurement. Active devices may oscillate or self-destruct with such terminations.

4.1

Introducing S-Parameters

Clearly, some other way of characterizing high-frequency networks is required that doesn't have these drawbacks. That is why scattering or S-parameters were developed. These parameters relate to familiar measurements such as gain, loss, and reflection coefficient. They are relatively simple to measure, and do not require connection of undesirable loads to the DUT. Different to Y and Z, however, they relate to the traveling waves that are scattered or reflected when a network is inserted into a transmission line of a certain characteristic impedance ZO. The measured S-parameters of multiple devices can be cascaded to predict overall system performance. S-parameters are readily used in both linear and nonlinear CAE circuit simulation tools, and Z-, Y- or H-parameters can be derived from S-parameters when necessary. To help with becoming familiar with linear S-parameters, we want to give a short example on characterizing components using power measurements, the lightwave analogy for Transmission and Reflection. Since a circuit described by S-parameters can be thought of like inserted into a uniform characteristic impedance (ZO) environment, we can compare Sparameters to reflection and transmission of an optical lens, surrounded at both sides by air. When light interacts with a lens, as in the photograph of Fig. 4, part of the light incident on the eyeglasses is reflected while the rest is transmitted. The amounts reflected and transmitted are characterized by optical reflection and transmission coefficients. By performing such a measurement, your optician is able to characterize your eyeglasses completely.

5

892

F. Sischka

& T.

Gneiting

Fig. 4: reflection and transmission with eyeglasses (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

Similarly, scattering parameters are measures of reflection and transmission of voltage waves through a two-port electrical network, inserted into a uniform characteristic impedance environment. Definition of S-parameters Referring once again to the spectacles examples from above, i.e. power-wise, the S-parameters are defined as: 2\

Pi I

I

2

i

I ajl 2 ibjl

|2 §2 I

i2

I—22 I

with

f

*

,

J

power wave traveling towards the two-port gate

2

power wave reflected back from the two-port gate

and I SnI2

power reflected from portl

ISi2l2

power transmitted from portl to port2

2

power transmitted from port2 to portl

IS.21I

IS22I2

power reflected from port2

This means that S-parameters relate traveling waves (power) to a two-port's (DUT) reflection and transmission behavior. Since the two-port is imbedded in a characteristic impedance of ZO, these 'waves' can be interpreted in terms of normalized voltage or current amplitudes. This is sketched below.

6

RF MOS Measurements

la,!2

893

-

lb, I2 « Zh

tWt*[

._ , f iiin'niiii

Starting with power

normalized toZo V*V

P=v*i

gives normalized amplitudes for voltage and current V

- VP =

3)

a,

^

•*

1-7

-o = I JZc

In other words, we can convert the power towards the two-port into a normalized voltage amplitude of towards _ twoport

VZo"

(1)

and the power away from the two-port can be interpreted in terms of voltages like L.

away _ from _ twoport

(2) See Fig. 5 for details.

Fig. 5: S-parameter definition (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

7

894

F. Sischka & T.

Gneiting

Looking at the S-parameter coefficients individually, we have: v

_ b1

0

reflected at portl

211 £1

_ b2 _

Q

Vtowards portl

v

o u t of port2

—21 ^1

^towards portl

(3) S l l and S21 are determined by measuring the magnitude and phase of the incident, reflected and transmitted signals when the output is terminated in a perfect ZO load. This condition guarantees that a2 is zero. Sll is equivalent to the input complex reflection coefficient or impedance of the DUT, and S21 is the forward complex transmission coefficient. Likewise, by placing the source at port 2 and terminating port 1 in a perfect load (making al zero), S22 and S12 measurements can be made. S22 is equivalent to the output complex reflection coefficient or output impedance of the DUT, and S12 is the reverse complex transmission coefficient. The accuracy of S-parameter measurements depends greatly on how good a termination we apply to the port not being stimulated. Anything other than a perfect load will result in al or a2 not being zero (which violates the definition for S-parameters). When the DUT is connected to the test ports of a network analyzer and we don't account for imperfect test port match, we have not done a very good job satisfying the condition of a perfect termination. For this reason, two-port calibration, which corrects for source and load match, is very important for accurate S-parameter measurements. In order to become more familiar with S-parameters, we will now discuss some specific Sparameter values.

SllandS22 value -1 0 +1

interpretation all voltage amplitudes towards the twoport are inverted and reflected (Oil) impedance matching, no reflections at all (50 Q) voltage amplitudes are reflected (infinite Q.)

The magnitude of Sll and S22 is always less than 1. Otherwise, it would represent a negative ohmic resistor (!). On the other hand, the magnitude of S21 (transfer characteristics) respectively S12 (reverse) can exceed the value of 1 in the case of active amplification. Also, the starting

RF MOS Measurements

895

points of S21 and S12 can be positive or negative. If they are negative, there is a phase inversion. As an example, S21 of a transistor starts usually at about S21 = -2 ...-10. This means signal amplification within the ZO environment and phase inversion.

S21andS12 magnitude 0 0...+1 +1 >+1

interpretation no signal transmission at all input signal is damped in the Z0 environment unity gain signal transmission in the ZO environment input signal is amplified in the ZO environment

The numbering convention for S-parameters is that the first number following the S is the port at which energy emerges, and the second number is the port at which energy enters. So S21 is a measure of power emerging from Port 2 as a result of applying an RF stimulus to Port 1.

4.2

Smith Chart And Polar Plot

The Smith chart for Sxx What makes Sxx-parameters especially interesting for modeling, is that S11 and S22 can be interpreted as complex input or output resistances of the two-port. That's why they are usually plotted in a Smith chart. NOTE: do not forget that included in Sxx is the termination at the opposite side of the twoport, usually ZO !! The Smith chart is a transformation of the complex impedance plane R into the complex reflection coefficient T (rho) , following the formula:

^R-Z0 ~ R + zo r

(1)

with the system's characteristic impedance ZO = 50 Q. This means that the right half of the complex impedance plane circle in the r-domain. The circle radius is '1' (see Fig. 6).

9

R

is transformed into a

896

F. Sischka & T.

Gneiting

R-50 R

r=

R + 50

j50 Ohm

50 Ohm

Fig. 6: the relationship between Sxx and the complex impedance of a two-port. (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

On the other hand, using a network analyzer with a characteristic system impedance of ZO, the parameter S11 is equal to

S„=2.^-1 v01

(2)

where vl is the complex voltage at port 1 and vOl the stimulating AC source voltage (which is typically normalized to 'I'). Fig. 7 depicts the corresponding circuit schematic. twoport ZO

ZO

V01

Fig. 7: about the definition of SI 1

V1

(S22 is analogous) (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

Under the assumption that R is the complex input resistance at port 1 and ZO is the system impedance, we get using eq.(2) and the resistive divider formula for Fig. 7:

R-ZO S»11 n = 2--=— -1 = = R + ZO R + ZO And this is the reflection coefficient T from(l)!!

10

RF MOS Measurements

897

NOTE: see also the chapter called 'Calculating S-Parameters From Complex Voltages' further down. After all, if the reflection coefficient T resp. Sj j or S22 is known, we get for the complex

i+r 1+s-n R = ZO • —-=• = ZO • — 1-T 1-S1 11

resistor R:

, with usually ZO = 50 Q

This explains how we can get the complex input/output resistance of a two-port directly from S11 or S22, if we plot these S-parameters in a Smith chart. Let's go back to Fig. 6 and consolidate this context a little further: it shows a square with the corners (0/0)Q, (50/0)Q, (50/j50)Q and (0/j50)ii in the complex impedance plane and its equivalent in the Smith chart with ZO=50£2. Please watch the angel-preserving property of this transform (rectangles stay rectangles close to their origins). Also watch how the positive and negative imaginary axis of the R plane is transformed into the Smith chart domain ( T ), and where (50/j50)Q is located in the Smith chart. Also verify that the center of the Smith chart represents ZO, i.e. for ZO = 50Q, the center of the Smith chart is (50/j0)Q. This allows us to make the following statements: > Sxx on the real axis represent ohmic resistors > Sxx above the real axis represent inductive impedances > Sxx below the real axis represent capacitive impedances > Sxx curves in the Smith chart turn clock-wise with increasing frequency. Fig. 8 depicts this graphically.

— K>

CD ED

Fig. 8: Location of ohmic, inductive and capacitive components in the Smith chart (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

11

898

F. Sischka

& T.

Gneiting

As an example for interpreting Smith charts, Fig. 9a shows the S l l plot of a bipolar transistor. In this case, the locus curve stars with S l l = 1 = ° ° * Z Q at low frequencies corresponding to R g g ' + R^j 0( j e + beta*Rr£. For increasing frequencies, the curves then turn into the lower half-plane of the Smith chart, the capacitive region. Here, the C g g shorts R(jiode' anc* beta = 1- F ° r infinite frequency, when the capacitors represent ideal shorts, the end point of S] j lies on the middle axis, i.e. the input impedance is completely ohmic, representing Rgg> + Rr£- Since Rgg> is bias dependent, and decreasing with increasing iB, the end points of the curves represent this bias-dependency. NOTE: For incrementing frequency, the Sxx locus curves turn always clockwise! Fig. 9b shows the S l l curve of a capacitor located between the two ports of the network analyzer (NWA). The capacitor represents an OPEN for DC, thus S11 = 1 = °°*Z0. For highest frequencies, it behaves like a SHORT, and we see the 50 Q of the opposite port2 (!). The transition between the DC point and infinite frequency follows a circle, and the increasing frequency turns the curve again clockwise.

S11

Fig. 9a: Si i of a transistor with increasing Base current iB. (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

12

RF MOS Measurements

899

-F i™ e CI

Fig. 9b: Si ^ of a capacitor between port 1 and port 2

7%e PoZar diagram for Sxy

Fig.10: The polar diagram for S12 and S21 (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

The S21 parameter represents the power transmission from port 1 to port 2, if the two-port is inserted into a matching network with characteristic impedance Z0 of e.g. 50 Q. This means, if no signal is transmitted, then S21=0 (located in the center of the polar plot). If the signal is transmitted, then MAG(S21)>0. The magnitude of the S21 curve will be below T for damping between the port 1 and port 2, and above 1' for amplification. If the phase is inverted, we are basically in the left half-plane of the polar plot (REAL[S21]

\

How to proceed with the de-embedding of lossless delay lines: Provided we know the delay times TDl and TD2, we can use the 'port shift' properties of Sparameter multiplications (shift of reference planes), and obtain:

45

932

F. Sischka & T.

'S11'DUT n,rr S21,DUT

Gneiting

S12-DUT ^ S22,DUT

f

01 -i

0 1

'total

* p j-2Plf 2TD1 e

S21total expj2Plf

(TD1+TD2)

S12total*exp j2Plf 99? * °"total

(TD1+TD2)\

J-2PI-«-2TD2 pvn e x P

f : frequency TD1: delay time at port 1, TD2: delay time at port 2

with:

De-embedding

applying the

ABC-matrix

By definition, ABC matrices are best suited to describe a chain of two-ports. This feature makes them an ideal starting point for parasitics de-embedding related to measurement conditions where we have considerably long connection lines to the device, and a separation into parallel and serial parasitics cannot be achieved. I.e. situations where the parasitic components are more distributed than lumped. ABC matrix de-embedding can be applied for example to packaged or insertable devices like a connector etc.. It can also be applied to special on-wafer components line spiral inductors, which occupy a large area on the chip and whose parasitics are therefore distributed. For a classical ABC matrix de-embedding, let's start with an example of a packaged device. Besides the test fixture for the DUT, which consists basically of a substrate with a strip line for each port of the DUT, we also need a special test structure to characterize these strip lines. This means we need another strip line on the same substrate like the test fixture, and this strip line is exactly as long as the strip lines of the test fixture. See the sketch below.

(L - AL)/2 —location 7 of the DUT AJine

Ajine

AL test fixture to measure the DUT

auxiliary fixture to characterize AJine

With the assumption that the A j m e ABC matrix is identical to the connection strip lines of the test fixture, the total performance of the device-under-test (DUT) including the test fixture can be expressed in A matrices as:

46

RF MOS Measurements A

933

total = A line * A DUT * A line

or solved for the DUT ABC matrix AQJJT; : A _ A - l * A * A _1 • ^ DUT ~ " • line ** total ^ line

How to proceed: The measured S-parameters S. ^ i are converted to A t

taj

. The same applies to the

measured S j m parameters. Then the matrix calculation from above is applied in order to obtain the de-embedded

AQTJX-

As a special case, the ABC matrix can be applied to de-embedding from lossy delay lines. First, we have to define the ABC matrix A j m e of a strip line, with: ZO y ct B or TD

characteristic impedance of the strip line propagation coefficient of the line loss phase shift resp. delay time of the strip line,

r , lossless line Y (freq)- L = |a( fre q) + j • B(f re q) J • L ~

j • B(f) • L = j • 2PI • freq • T D

Note: roughly TD=10ps per mm strip line can be assumed on a ceramic substrate. In case of a lossy line, we calculate first for every frequency point [i] the auxiliary term: aux[i] = (j2 * PI * freqlij * oc + j * 2 * P I * f req[i] * p)* L

and in case of a lossless line (ct=0), we calculate first:

aux[i]=j*2*PI*freq[i]*p*L or aux[i]=j*2*PI*freq[i]*TD which gives for the ABC matrix of the delay line (per frequency point index i): Aline 10 =

cosh(aux[i]) ZO*sinh(aux[i]p —-sinh(aux[i]) cosh(aux)[i]

This matrix is then introduced in the ACB matrix de-embedding formula A

DUT

=

A|j"ne * A t o t a | * AjTne, and we can calculate the de-embed matrix ArjTjj.

47

934

F. Sischka

& T.

Gneiting

Note: in case of a lossless delay line, the formula simplifies to

Mine lossless [i]

( cos(p*l_) = -^sin(p*L)

and

ZO*sin(P*L)^ cos(p*L)

with

p = coVCL

ZO = J —

6.4

De-Embedding The OPEN Dummy Device

The most simple, but very often used de-embedding method is the simple de-embedding from an OPEN device. The underlying prerequisite for this method is, however, that all the circuit components of the OPEN dummy structure can be represented exclusively by lumped circuit components only which are altogether in parallel with the DUT. Only in this case, the well-known Y-matrix subtraction method Y_DUT = Yjxrtal - Y_OPEN can be applied. Fig. 33 depicts this condition. Y DUT

^^•^rDUT^^H infflHHn,t.,.-'M~ ilHIMiiij L"

•••••

- parallel-v. / parasitic;: Y_parallel Fig. 33: For OPEN dummy device de-embedding using Y-matrix subtraction, the OPEN subcircuit has to be completely in parallel with the DUT. (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

In order to successfully applying this Y-matrix subtraction, this prerequisite condition of parallel parasitics has to be verified. Otherwise, the de-embedded curves of the inner DUT may look ok, but they may be wrong. The best way to check this is to model the open. If we are able to achieve a fit with a subcircuit consisting of lumped devices which can be interpreted as being completely in

48

RF MOS Measurements

935

parallel with the DUT, (independent of how complex the inner structure of this sub-circuit is !), we can be sure to perform a correct OPEN de-embedding. Fig. 34 shows an OPEN dummy layout, and its S-parameter performance. Referring to the physical layout given in Fig. 35, we can assume a simple RC TEE structure for low frequencies. For higher frequencies, also crosstalk between the ground-signal-ground GSG contact pads of the dummy and coupling across the pads from port 1 to port 2 comes into play. See Fig. 34 and components CIO, RIO, C12, C20 and R20, where the resirtors again represent the losses of the silicon substrate. This effect happens usually for frequencies above -10 GHz, and can be seen in the S-parameter measurements as a deviation from the low-frequency half-circles. See the typical measured S-parameters in Fig. 34. Of course, this 2nd order high-frequency dependency varies with the layout of the OPEN and also with the wafer process. OPEN DUMMY

R£«»

CE-33

Fig. 34: Modeling the OPEN dummy device (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

49

936

F. Sischka

& T.

Gneiting

Fig. 35: physical representation of the OPEN dummy structure for low frequencies (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

If we did not require e.g. inductors to model the OPEN dummy, or other components which can be assumed to be in series with the inner DUT, we can now perform the de-embedding. The measured S-parameters of the OPEN and the total DUT are transformed to Yparameters and then, the Y-parameters from the OPEN are subtracted from the total DUT's Y-parameters. De-embed from Open: •DUT

=

^Total - Y 0 p w i

Convert to S: SDUT

6.5

~

S(YQUT)

De-embedding The OPEN And The SHORT Dummy Device

A method to also strip off the series parasitic influence from the measured data is to deembed the inner DUT from both the OPEN and SHORT dummy device. The idea behind this method is, that the electrical behavior of the pads around the DUT can be described by a combination of exclusively parallel (OPEN) and exclusively serial (SHORT) circuit elements as described in Fig. 36.

50

RF MOS Measurements

937

SERIAL PARASITICA

; i Di

•

,_

i -'

r

i

;

)

:

. ' •-* t

V*y"' : *

—c

c i..

••- , 7 ^ - ^

isf-M1*)

I'AHALLEL PARAS!TICS • r-i'Hi'u!

Fig. 36: For OPEN and SHORT dummy device de-embedding using Y- and Z-matrix subtraction, the OPEN subcircuit has to be completely in parallel with the DUT, and the SHORT subcircuit completely in series with the DUT. (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

Once the two-port matrices of the serial and parallel parasitic elements are known, they can be subtracted very easily from the total measurement data set. To determine these matrices, the S-parameters of the OPEN and the SHORT dummy test structure are used.

51

938

F. Sischka

& T.

Gneiting

OPEN DUMMY: o

1

o

o-

PARALIEL PAOASITICS Y pu*!let

SHORT

i—ID-

DUMMY: SERIAL PARASITICS ;

._—o-

'^T*•••»"^•i,

--«•?! "••J1."" v i » i l -• rv-1

. o

{seies i;

•O

VYds) = -dI"s BV. gs gds(Vgs,V*)

91

=

2Lt dV,ds

(28) (29)

978 M. Je, I. Kwon, H. Shin & K. Lee

Fig. 9. Model current /* vs. two controlling bias voltages V& and V&. 2 Taking the partial derivative of (28) with respect to Vds, and noting 8 L

dlL

ur dVgs 0,dV, ds we obtain a relationship between the model conductance and model transconductance given in (30). A mathematically equivalent statement (derived using Stokes's Theorem) is given by (31). The indicated contour is any closed loop on the surface defining the model current Jds.

w*wv

5K„,

dV„

< j k Wv. V* )dVgs + gds (Vgs, Vds )dVds ]= 0

(30)

(31)

A key consequence of (30) and (31) is that the model conductance gaJi,Vgs, Vds) and the model transconductance gm(Vg$, Krfs) are not independent functions of bias! Extraction of model gm and gds separately versus bias, which is standard practice in linear analysis, can result in a path-dependent model Ids. That is, the right hand side of (31) may be different from zero. A nonzero result for the right hand side of (31) represents the net (positive or negative) current supplied by the VCCS to the circuit after its controlling voltages are allowed to vary and then return to their original values. This is not a problem in small-signal analysis, where the bias point remains fixed, but it is extremely dangerous in large-signal analysis. Disaster can result in large-signal simulations even if the right hand side of (31) is only slightly different from zero. Under the conditions of large signal periodic input waveforms, the FET model controlling voltages can traverse closed loops in voltage space at the rate of billions of times a second (at microwave frequencies). The error (excess current) generated with each loop traversal accumulates, ultimately becoming large enough to cause the simulation to crash, or else cause a spurious result, such as a runaway voltage on a capacitor plate elsewhere in the circuit. The two properties of path independence and time (frequency) independence of current modeled by VCCS element are hallmarks of a network variable. Exactly the same considerations apply to the network variable charge as applied to the network variable current. The model charge Qgs of the VCQS nonlinear element of Fig. 8 is

92

MOSFET Modeling and Parameter Extraction for RF IC's 979 plotted versus the two controlling bias voltages Vgs and Vj, in Fig. 10. Qgs describes a twodimensional surface. The slope of this surface in the direction parallel to the Vgs axis defines the model capacitance Cgs(Vgs, Vds). The slope of the Qgs surface in the direction parallel to the V& axis defines the model transcapacitance Cm(Vgs, Vds). This is precisely the quantity we met in (27).

Fig. 10. Model charge Q^ vs. two controlling bias voltages VJS and V&. The statement of path independence of the model charge is given in (32). An equivalent statement is given by (33). Mathematically, (32) and (33) show that Cgs(Vgs, Vds) and Cm(Vgs, Vds) are components of a conservative vector field. #

h* (Vs. • V * )dVss + Cm (Vgs, Vds )dVds ] = 0 8Ces

dC„

(32) (33)

dV„ dV„ ds "• gs Again the important point is that the model capacitance and model transcapacitance are not independent functions of bias! Specifying the model capacitances and transcapacitances separately versus bias can result in a path-dependent model Qgs. That is, the right hand side of (32) may be different from zero. Such a situation can result in the same fatal errors as described for the VCCS case. The transient (large-signal) analysis simulations don't fit the ^-parameters versus bias data well. On the other hand, good fits to the measurements can be obtained by using a simple AC (small-signal) model. However, the poor fit to the data in the transient analysis (TA) mode means the TA and AC simulations are inconsistent. Such inconsistencies mean AC simulations over a wide range of bias, no matter how accurate, cannot be used to reliably extrapolate the true large signal model performance. The solution to this problem is to start directly from three-terminal VCQS elements such as Qgs(Vg$, Vds) and QgdiVg,, Vds). Despite the innocent appearance of capacitor symbols in the equivalent circuit of the FET model, the intrinsic capacitors are not two-terminal capacitors. A two-terminal capacitor has a capacitance (and also a charge) that depends only on the single

93

980

M. Je, I. Kwon, H. Shin & K. Lee

voltage difference between the terminals. However, the intrinsic capacitors and charges in

FET's depend on two voltage differences. The consistency between TA and AC modes can now be guaranteed by taking the AC admittance matrix to be given by the linearized TA equations. G

o

G O

9ds -JvW-

9ds SO-

•©•

-OD

9m

(b)

(a)

Fig. 11. Time delay implementation in linear analysis: (a) using a frequency dependent element (b) using a transcapacitance.

The second problem is that large-signal FET models do not simulate time delays of the FET. In linear analysis, time delays are typically introduced via the multiplicative frequency dependent factor gme~J°". In a linear FET model, this factor often appears with the transconductance element at the output. The key point is that in linear analysis only, quantities such as conductances and transconductances can be assigned arbitrary frequency dependences. The objective is to try to represent time delays, at least approximately, using the nonlinear elements. We can start from the standard expression gme'i 10 GHz) cannot be explained.'-'2 On the other hand, without the intrinsic body node, the substrate parasitics cannot be modeled physically. The Rsub connected in series with the drain junction capacitance in Fig. 16 may be just enough to fit the measured K22 or S22 up to about 10 GHz, but its location in the equivalent circuit is not physically correct.81-82 As a result, it is difficult to make the value of Rsub in this model be scalable and predictable from the technology parameters. Above all, all the models examined in this section are three-terminal models, and thus their application is limited to a specific circuit configuration. 3.3. KAIST three-terminal model with simple and accurate parameter extraction technique

Drain

6 Source Fig. 17. Small-signal equivalent circuit of a three-terminal MOSFET model without an intrinsic body node.

We have proposed a simple and accurate parameter extraction method for a small-signal MOSFET model including the substrate-related parameters and a complete set of non-reciprocal capacitors.83 This work focuses on a charge-conserving and physical small signal equivalent

100

MOSFET Modeling and Parameter Extraction for RF IC's

987

circuit of the RF MOSFET and an accurate parameter extraction approach by K-parameter analysis from measured S-parameters. The small signal equivalent circuit of a three-terminal MOSFET model is shown in Fig. 17. Non-reciprocal capacitance and substrate-related parameters are included in the model. In a three-terminal configuration, the source-to-body junction capacitance Cjs and the source-tobody spreading resistance Rsubs can be excluded if the intrinsic body node is assumed to be short-circuited to the source directly. This approximation makes a simple direct extraction of all the elements possible. However, Cjd and Rsubd extracted with this assumption do not provide physically correct values, although they provide excellent fit of Y-n up to 10 GHz, as pointed out in 3.2.80 Four intrinsic capacitances, Cgs, Cgd, Cdg and Csd, are required for the three-terminal model. The overlap capacitances are merged with the correspondent intrinsic capacitances. Cgd and Cdg are the two non-reciprocal capacitance components for the three-terminal model.57*0 The capacitive effect of the drain voltage on the gate charge is represented by Cgd, and the capacitive effect of the gate voltage on the drain charge is represented by Cdg. In general, Cdg is different from Cgd. C„ = Cdg - Cgd is a transcapacitance representing the different effect of the gate and the drain on each other in terms of charging currents, just as gm is a transconductance representing the different effect of these two terminals on each other in terms of transport currents. If Cgd and Cdg are set to be equal, as in most conventional models, large error can be introduced since charge conservation does not hold. In the AC simulation, the transcapacitance has to be included for accurate prediction of the transadmittances v 2 i and Yn. Without the nonreciprocal gate-drain capacitance, it is impossible to model I m ^ i ) and I m ^ u ) accurately at the same time. In the case of a four-terminal model with a separate substrate terminal, a similar approach can be extended by including other non-reciprocal capacitances. The resistance Rg represents the effective gate resistance that consists of the distributed channel resistance and the gate electrode resistance." These effects are approximated by a single effective lumped gate resistance, as shown in the equivalent circuit of the MOSFET shown in Fig. 17. Direct extraction using a linear regression approach is performed by K-parameter analysis on the equivalent circuit of the MOSFET for high frequency operation. In our approach, an optimization process, which may have uncertainties in obtaining physical parameters, is not required. The small-signal equivalent circuit shown in Fig. 17 can be analyzed in terms of Yparameters as follow: ja>(Cgs + Cgd) a>2 (Cgs + Cgd )2 Rg + ja>(Cgs + Cgd) "

\+2Cgd (Cgs + Cgd )Rg - jwCgd

- jwCgd

y 12

Yix

\+a>2{Cgs+Cgd)2Rg2

\+jco{Cgs+Cgd)Rg 1 + MCgs 2

+ Cgd )Rg

8 m -°> Cdg(Cgs

1 + ja(Cgs

+Cgd)Rg l+

+ Cgd )Rg -jccCdg-jcogmRg{Cgs+Cgd)

2

a, (Cgs+Cgd?Rg2

101

988


y22 -_gds

2

*** \+jojCjdRsubd

+

+j(oCsd

**» \ + jcoCjdRsubd

= gdj +

**

, (Cgs+Cgd)Rg

s

"

«

a

u^.,^r

j.r

+Cgd)R2g

2

\ i

(54) For operation frequency up to 10 GHz, by using the assumption that a2 (Cgs + Cgd)2 Rg2 « 1, the K-parameters can be approximated as follows: y,, * w2 (Cgs +Cgd)2Rg+ jo>(Cgs + Cgd)

(55)

2

Yl2 * -w Cgd(Cgs + Cgd)Rg - jcoCgd

(56)

»2i * 8m ~0}2Cdg{Cgs +Cgd)Rg -jwCdg -jojgmRg(Cgs+Cgd)

(57)

2 >-22 * * * +,°)C2*2S:bd 1^ CgdCdgRg \+a> Cjd Rsuhd JWCjd

i ,

l + O) 2C^Jd 2 DRsubd2

+

a>2gmR2gCgd(Cgs +Cgd)

+ jaCsd + jcoCgd + jcogmRgCgd - ja>>CgdCdg(Cgs + Cgd)R2g.

(58) The validity of the assumption that a} (Cgs + Cgd)2 Rg2 « 1 will be checked after each parameter is extracted. All the components of the equivalent circuit are extracted by the Yparameter analysis and analytical equations are derived from real and imaginary parts of the Yparameters. gm is obtained from the ^-intercept of Re(K21) versus of and gds is extracted from the ^-intercept of Re(y22) versus of, at the low frequency range. Rg, Cgd, Cgs and Cdg can be obtained by (61H74).

< 59 >

gm=Re(r2.)Uo /? g =Re(y n )/(Im(K n )) 2

(61)

Cgd=-\miXxl)loj

(62)

Cgs=(lm(Yn)

(63)

+ lm(Yn))/co

Cdg =-lm(Y2l)/o>-gmRg(Cgs+Cgd)

(64)

For the extraction of substrate components Rsuhd and Cjd, Ysub is first defined as follows: ysub = hi ~gds ~-.—

«i

101-

1.S

-.

102-

A,..

subd fl

-»

—I

'

1

1.0

2.5

(a)

—•

—•

B-

r~

(

•—

a

r-

1.5

2.0

(b)

Fig. 22. The drain-bias dependence of small signal parameters for an n-MOSFET having 100 fan width and biased to Vjs= 2 V: (a) capacitances, (b) Rs and /?»«. In Fig. 22, drain-bias dependence of the extracted small-signal parameters for the nMOSFET biased to Vgs= 2V\s shown. The drain-bias dependence of the extracted capacitances are shown in Fig. 22(a). The vertical line at Vds = 0.81 Kis the boundary between the linear and saturation regions. When the transistor is biased in the linear region with low Vds, the intrinsic behavior of the transistor becomes symmetric in terms of drain and source. Thus the intrinsic capacitances Cgsi and Cgdi are almost the same at V^ = 0 V. In Fig. 22(a), the difference between Cgs and Cgd at Vds = 0 Vis due to the parasitic Cgb which is included in the Cgs. Cgb of the gate contact pad component and the poly-to-well capacitance in the field oxide become the major parts of the parasitic capacitance. At V& = 0 V, Cdg is the same as Cgd and Cm = 0. Cm increases with J ^ in the linear region and is almost constant for high Vds in the saturation region. Csd becomes negative in the linear region because the raising the drain voltage will increase the effective reverse bias at the drain end and will cause the magnitude of the inversion layer charges to decrease. In the saturation region for higher Vds, the gate-to-drain capacitance Cgd is almost the same as Cgdo. The extracted capacitance parameters correctly model the bias dependence of intrinsic capacitance. Because the conventional C-V measurements using large C-V test structure are less sensitive to extraction of small capacitance values in short-channel

106

MOSFET

Modeling and Parameter

Extraction for RF IC's

993

RF MOSFET's, measuring S-parameters of the RF MOSFET in the high frequency GHz range is a better alternative. The proposed parameter extraction method can be applied to accurate intrinsic capacitance modeling at GHz operation. The extracted Rg and RsuM with drain bias are shown in Fig. 22(b) and they are almost constant with drain bias.

20 -

W / L * 100/0.35 V*-2V ———_

W/Ls 100/0.35 V. - 2 V • On,

/

(0

•

-

Extraction rwult DC inm urwmnt

Extraction raault DC measurement

E _? 20

/ 8*. \

i . .a

(a) Fig. 23. gm and g& extracted from the S-parameter measurement and those obtained from DC measurement: (a) varying the gate bias for Vis = 2V, (b) varying the drain bias for Vg, = 2 V.

In Fig. 23, gm and gds extracted from the S-parameter measurement and those obtained from DC measurement are compared. Extracted gm and gds as a function of Vgs with gate bias for Vds -2 V are shown in Fig. 23(a), and extracted gm and g* as a function of Vj, with drain bias for Vgs = 2 V are shown in Fig. 23(b). They match very well with each other, verifying the validity of the equivalent circuit and the extraction method. The extraction results correctly modeled the bias dependence of gm and && in the linear and saturation regions. Figure 23 shows that RF conductance data agree well with those from derivatives of measured DC I-V characteristics. This has very important implications, that a large-signal model for I-V characteristics is accurate enough to be used for DC, low-frequency analog, as well as RF circuit simulations. 4. Four-Terminal RF MOSFET Modeling and Parameter Extraction We have examined several trials to model the RF MOSFET as a three-terminal device. As mentioned previously, the three-terminal models are only valid for devices with source-body tied configuration and the complex signal coupling through the intrinsic body node cannot be described. To overcome these important limitations, four-terminal modeling of the RF MOSFET is required as essentially it is a four-terminal device. In this chapter, four-terminal modeling examples will be reviewed.

107

994


4.1. Equivalent-circuit-based

modeling approaches

1

OB

Fig. 24. Complete small-signal model for a four-terminal intrinsic MOSFET proposed by Bagheri and Tsividis.37

In Ref. 37, Bagheri and Tsividis presented a four-terminal physical model of a MOSFET with the equivalent circuit shown in Fig. 24. It includes a "transmission-line effect" which is another name for the non-quasi-static effect, and its parameters are given by functions of terminal voltages, process parameters, and device geometry. The parameters vary continuously in value with bias from strong, through moderate to weak inversion. The equations were derived for the long-channel device using a charge-sheet approximation. Two differential equations the current transport and charge continuity equations -with appropriate boundary conditions were solved using iterative methods for obtaining the small-signal terminal currents. In general, each terminal current has the form of a power series numerator over a common denominator series. From this result, the small-signal /-parameters can be calculated using the definition Y

»P =

L

(69)

v

fr

K=O,y*0

where the subscripts a, fl, and y can stand for drain (d), gate (g), and substrate (b). The Yparameters that were evaluated and truncated to second order in Ref. 37 are shown below. 1 + jcoa{ Y (70) gs = -J®0* D(ja>) 1 + jcoa2 Y (71) gd = -JvCgd D(jco) 1 + j coai (72) hs = -JoCbs D{ja>) 1 + jcoa2 Y 0 (73)

M = -J*" ,bd'

108

MOSFET Modeling and Parameter Extraction for RF IC's

-JoC.«*"

igb

*m

Sti

(74) D(jo>)

\-jcoa4-U

r10

Frequency (GHz)

Fig. 2 The model without the substrate resistances cannot predict the measured Yu characteristics.

Another important component that almost all of the compact models implemented in commercial circuit simulators did not account for is the substrate resistance. Actually, substrate-coupling effects through the drain and source junctions and these substrate resistance components play an important role in the contribution to the output admittance so the inclusion of these substrate components in a RF model is needed. This effective admittance of the substrate network can contribute 50% of the total output admittance.9 As shown in Fig. 2, a MOSFET model without the substrate resistance components cannot predict the frequency dependency of the output admittance of the device so the simulation with such a model will give misleading simulation results of the output admittance when the device operation frequency is in gigaherze range. 1.3. The status of the RF MOSFET modeling Compared with the MOSFET models for both digital and analog application at low frequency, compact models for HF applications are more difficult to develop due to the additional requirements of bias-dependence and geometry scaling of the parasitic components as well as the requirements of accurate prediction of the distortion and noise behavior. A common modeling approach for RF applications is to build sub-circuits based on the intrinsic MOSFET that has been modeled well for analog applications.,0, "' 2 The accuracy of such a model depends on how to establish sub-circuits with the correct understanding of the device physics in HF operation, how to model the HF behavior of intrinsic devices and extrinsic parasitics, and how to extract parameters appropriately for the elements of the sub-circuit. A reliable and physics-based parameter extraction methodology based on the appropriate characterization techniques is another important

124

MOSFET Modeling for RF IC Design 1011 portion of the RF modeling to determine the model parameters and generate scaleable models for circuit optimization. Currently, most RF modeling activities focus on the above subcircuit approach based on different compact MOSFET models developed for digital and low frequency analog applications, such as EKV, 13 MOS9, 6 and BSIM3v3.5 Several MOSFET models for RF applications have been reported.11,12'1415 With added parasitic components at the gate, at the source, at the drain and at the substrate, these models can reasonably well predict theHF AC small signal characteristics of short channel (SB

RSI:UB

B Fig. 7 (e) One resistor substrate network.1

(Gm-j>*Cm)K»

r~

-e— -e— -e-

(QK+j»CsDi)vas/ ^/W

O

v

(Gmb-j»Cmb) s#

RDSB

Fig. 8 An equivalent circuit with both intrinsic and extrinsic components.

132

MOSFET

Modeling for RF IC Design

1019

2.2.4. Implementation ofa subcircuit RF model in circuit simulators The equivalent circuit shown in Fig. 8 can be used to understand and analyze the HF behavior of a MOSFET. In order to implement this equivalent circuit in a Spice simulator, a subcircuit approach has to be used. In the subcircuit, the characteristics of the intrinsic device is described by a MOS transistor compact model implemented in the circuit simulator, and all the extrinsic components have to be located outside the intrinsic device, so that the MOS transistor symbol in the subcircuit only represents the intrinsic part of the device \ For example, (1) the source and drain series resistors have been added outside the MOS intrinsic device to make them visible in AC simulation (in most compact models, since the internal series resistances are only "virtual" resistances embedded in the I-Vmodel to account for the dc voltage drop across the source and drain resistances in calculating the drain current, they do not add any poles and are therefore invisible for AC simulation); (2) The gate resistance should be added to the subcircuit model (usually RG is not part of the MOS compact model, but plays a fundamental role in RF circuits as we discussed in Section 1); (3) The substrate resistors should be added to account for the signal coupling through the substrate; (4) Two external diodes should be added in order to account for the influence of the substrate resistance at HF (the source-to-bulk and drain-to-bulk diodes are part of the compact model but their anodes are connected to the same substrate node, which will short the AC signal at HF12 so the diodes internal to the compact model should be turned off). With the above considerations, a subcircuit that represents a RF MOSFET in a circuit simulator can be given in Fig. 9. Note that the intrinsic substrate node should be connected at some point along the resistor RDSB, but simulations have shown that connecting the intrinsic substrate to the source or the drain side has little influence on the simulated AC parameters. In some RF models,9-" the intrinsic substrate has been connected to the source side of in order to save one node and one component for the subcircuit model. Two external overlap capacitances, CGSP and CGDP as shown in Fig. 9, with bias dependence can be added but this is not always required, depending on the compact model used. For example, BSIM3v3 accounts for bias dependent overlap capacitances that, if extracted correctly, have shown a sufficient accuracy. However, by adding these external capacitances, the inaccuracies of the intrinsic capacitance model appearing for short-channel devices can be corrected. In the next section, we will discuss the modeling of these intrinsic and extrinsic components shown in Fig. 8. 2.3. Modeling of the intrinsic MOSFET Compared with the MOSFET modeling for digital and low frequency analog applications, the HF modeling of MOSFETs is more challenging. All of the requirements for a MOSFET model in low frequency application, such as continuity, accuracy and scaleability of the

It may include the overlap capacitances at the source, at the drain and at the bulk, depending on the intrinsic compact MOSFET model used in the implementation.

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Y. Cheng

DC and capacitance models should be maintained in a RF model." In addition, there are further important requirements to the RF models: (1) The model should accurately predict bias dependence of small signal parameters at HF operation; (2) The model should correctly describe the nonlinear behavior of the devices in order to permit accurate simulation of inter-modulation distortion and high-speed large-signal operation; (3) The model should correctly and accurately predict HF noise which is important for the design of, e.g., low noise amplifiers (LNA); (4) The model should include the NQS effect so it can describe the device behavior at very high frequency range in which NQS effect cannot be ignored for a model to behave correctly and will degrade the device performance significantly; (5) The components in the developed equivalent circuit model should be physics-based and geometrically scaleable so that the model can be used in predictive and statistical modeling for RF applications.

Core/Intrinsic MOSFET • Ro

CGSPJ_ • Rs

J:

-AA/V

_iL.

• .I^J_CGDP

JV CSB

l—AA/V RSB

' Substrate Network /

W\r RDSB

B

AAAr-i RDB

B

fig. 9 A subcircuil that can be implemented in a circuit simulator.

To achieve the above, the model for the intrinsic device should be derived with the inclusions of most (if not all) important physical effects in a modern MOSFET, such as normal and reverse short-channel and narrow width effects, channel length modulation, drain induced barrier lowering (DIBL), velocity saturation, mobility degradation due to vertical electric field, impact ionization, band-to-band tunneling, polysilicon depletion, velocity overshoot, self-heating, channel quantization." Also, the continuities of small signal parameters such as transconductance Gm, channel conductance G&, and the intrinsic trancapacitances must be modeled properly. Many MOSFET models, including MOS9,6 EKV,20 and BSIM3v35 have been developed for digital, analog and mixed signal

134

MOSFET


1021

applications. Recently, they all are extended for use in RF applications. We do not present any new models in this work. Instead, in the following, we give a brief discussion on the concept of deriving a compact model of the intrinsic device for RF applications. A compact model includes many mathematical equations for different physical mechanisms. The most important and essential parts are DC and capacitance models. It has been found that the model accuracy in fittings of HF small signal parameters and large signal distortion of a RF MOSFET is basically determined by the DC and capacitance models.21 2.3.1, DC model In general, a DC MOSFET model is derived based on the following Jn = qiimE + qDn V«

(8)

JP = q^pE-qDpVp

(9)

where J„ and Jp are the current density for electrons and holes respectively; q is the electron charge; n, and /j, are the mobilities for electrons and holes, respectively;« is the electron concentration in the channel; p is the hole concentration in the channel; £ is the electric field; D„ and Dp are the diffusion coefficients for electrons and holes, respectively. D„ and .Dp link tojn and y, with the following equations: Dn = V,Hn

(10)

Dp = viflP

(11)

where v, is the thermal voltage. The first terms in Eqs. (8) and (9) describe the drift current components due to the electric filed E. The second terms describe the diffusion current component due to the carrier concentration gradient. In the strong inversion region, the total current is dominated by the drift current. In the subthreshold region, the diffusion current component dominates. However, in the transition region (moderate inversion region) from subthreshold to strong inversion, both drift and diffusion currents are important, and need to be included in the model. As shown in (8) and (9), the electric field E, carrier density, and mobility are the basic factors determining the current characteristics. The electric field E can be obtained by solving the Poisson equation V>=—£-

135

(12)

1022

Y. Cheng

where 0is the electrostatic potential; p i s the charge density including electron, holes, and other charges in the interesting region of the device. However, to get analytical solutions for I-V models, simplified approaches are needed to consider the influence of the electric field in compact modeling." Besides the proper consideration of the electric field, the channel charge and mobility need to be modeled carefully to describe the current characteristics accurately and physically, based on which, different physical effects can be added in the I-V model. In modeling the channel charge, physical effects such as short channel effect, narrow width effect, non-uniform doping effect, and quantization effect etc. should be accounted for in order to describe the charge characteristics accurately in today's devices. There are two types of charge models, one can be called threshold-voltage (Vlh)based models, another can be called surface-potential (y*)-based models, yf-based charge models are based on the analysis of the surface potential that will appear in the I-V model to describe charge characteristics with the influence of many physical effects.22 F,A-based charge models are derived also by solving the surface potential with the consideration of those physical effects, but finally V,h is used instead of 1/4 in the charge (and hence I-V) model to account for the influence of some process parameters such as oxide thickness and doping and device parameters such as channel length and width.5'6,20 In both models, the continuities of the charge and its derivatives should be modeled carefully for the I-V model to have good continuity and to predict correct distortion behavior of the devices. A F,A-based charge model used in BSIM3v3 is given in Eq. (13) as an example. As shown in Fig. 10, the model fits the measured data of the channel charge and ensures the continuity of the channel charge from strong inversion to the subthreshold regions.23 Fig. 11 shows the continuity of the ^ ^ ( a n d hence the charge model as given in Eq. (13) and its first and second derivatives.19

Qchs o = Cox Vpieff

(13a)

VGS-V,H,

VgsKff =

2nv/ln l+exp(— ) 2nvi 1 + 2nCox l„CoX\^.I—-—exp( ^ qe,iN îNd, 2nvi

(13b) —)

Here Cox is the unit area oxide capacitance; n is the subthreshold swing factor; Nch is the doping concentration in the channel; Voff\s a fitting parameter; " Vas is the gate voltage; V,h is the threshold voltage; vt is the thermal voltage; q is the electron charge; £,, is the dielectric permittivity of the semiconductor; and $ i s the surface potential when Vgs=Vlh, and is given by 0s=2v,ln(-^-)

where Nch is the doping concentration in the channel;«, is the intrinsic carrier density.

136

(13c)

MOSFET Modeling for RF IC Design 1023

l O itt

N =axiaie

10-"•

.2 o o

GJ

io- 1 3 ;

10-

10-'

OS

OO

OS

1.0

1-5

2X1

3 0

2.5

35

V G S (V) Fig. 10. The charge model covers the weak, moderate, and strong inversion regions of MOSFETs.23

The second derivative of VgsUff vs. VGS

The first derivative of Vgsiaff vs. VGS

Vgstsff .

ft********

•1.0

-0.5

0.0

0.5 1.0 yos(V)

*****

1.5

2.0

2.5

Fig. 11. The continuities of the charge model and its derivatives are needed in different operation regimes." Mobility is another key parameter in MOSFET modeling. It will influence the accuracy and distortion behavior of the model significantly.19,24 The relationship between the carrier mobility and the electric field in MOSFETs has been well studied.25,26 Three

137

1024

Y. Cheng

scattering mechanisms have been proposed to describe the dependence of mobility on the electric field.27 Each mechanism may be dominant under specific conditions of doping concentration, temperature and biases as shown in Fig. 12.

Effective Field Eeff

Fig. 12 Mobility behavior influenced by different scattering mechanisms, depending on the bias and temperature conditions.27

In strong inversion, mobility depends on the gate oxide thickness, doping concentration, threshold voltage, gate and substrate biases. In weak inversion, it is usually modeled as a constant. Thus, continuity of the mobility model is also required to ensure the continuity of the /-K model. In BSIM3v3, a mobility expression based on the Vêff given in Eq. (13) is used, fJ, 1+(U.+UCVBSX

(14) ) + Ub{

J ox

) I ox

where ^& Um Ub and Uc are fitting parameters extracted from measured data; V,h is the threshold voltage; Tox is the gate oxide thickness." With Vg5leff\n Eq. (13), the mobility model given in Eq. (14) is continuous from strong inversion to weak inversion. It has been known that the I-Vmodel based on Eq. (14) can predict the distortion behavior of the devices.21 Recently, other detailed analysis of the influence of the mobility model on the distortion behavior of the 7-Kmodel has also been reported.24 In Fig. 13, is shown the comparison of characteristics of Gm and its derivatives versus gate bias between the model and measured data for a device of 5fim

138

MOSFET


1025

channel length, with the consideration of the distortion behavior of the mobility model.24 It has been realized that an accurate and physical description of a mobility model in compact MOSFET RF models for circuit simulation is essential for distortion analysis. It is also suggested that different models for electron and hole mobilities should be developed because of the difference in quantum-mechanical behavior of electrons and holes in the inversion layer in today's MOSFETs.24

*

6*

%. "

l«

•90 r " " • " • ^ «•»»•.-/}----

3.00

--:•

3.30

.if *M

4.50

5.00

5.50

6.00

VcsCV) Fig. 13 Measured (symbols) and modeled (lines) behavior of Gm and its first and second derivatives as a function of VGS for an n-channel MOSFET with a width of lOum and length of 5\im at fis=0V.24

Based on the charge and mobility models, complete I-V equations can be developed with further inclusions of many important physical effects such as short channel and narrow width effects, velocity saturation and overshoot, poly-depletion effect, quantization effect, and so on. In order to meet the requirements for both AC small signal and larger signal applications, the continuity and distortion behavior of the I-V model should be ensured in deriving the equations when including these physical effects. 2.3.2. Capacitance model In real circuit operation, the device operates under time-varying terminal voltages. Depending on the magnitude of the time-varying signals, the dynamic operation can be classified as large signal operation and small signal operation. Both types of dynamic operation are influenced by the capacitive effects of the device. Thus, a capacitance model is another essential part of a compact MOSFET model for circuit simulation.

139

1026

Y. Cheng

Many MOSFET intrinsic capacitance models have been developed. Basically, they can be categorized into two groups. (1) Meyer and Meyer-like capacitance models and (2) charge based capacitance models.28,29 The advantages and shortcomings of the two groups of model have been well discussed and both of them have been implemented in circuit simulators. The Meyer and Meyer-like models are simpler than charge-based models so they are efficient and faster in computations. But they assume that the capacitances in the intrinsic MOSFET are reciprocal, which is not the case in real device,"and earlier models based on this assumption cannot ensure the charge conservation.19'30 Charge-based models ensure the charge conservation and consider the non-reciprocal property of the capacitances in a MOSEFT. These features are required to describe the capacitive effects in a MOSFET, especially for RF applications where the influence of trans-capacitances are critical and should be considered in the model. But usually the charge-based capacitance models require complex equations to describe all of the 16 capacitances in a MOSFET with four terminal, as given in the following, Q=^SL d/,j

i*j,ij=G,D,S,B

(15)

Cj = - ^ L

i=j

(16)

The development of an intrinsic capacitance model of modern MOSFETs is another challenging issue in RF modeling. To meet the needs in RF applications, besides ensuring charge conservation and non-reciprocity, an intrinsic MOSFET capacitance model should at least have the following features such as (1) guaranteeing model continuity and smoothness in all the bias regions, (2) providing model accuracy for devices with different geometry and different bias conditions, and (3) ensuring model symmetry at the bias of VDs=(N. Some comparisons between the MOSFET capacitance models and the measured data have been reported.31 However, a complete verification of the bias and geometry dependencies of those capacitance models has not been seen. It has been found that some engineering approaches have to be used to improve the accuracy of the capacitance model if the intrinsic capacitance model cannot describe the device behavior accurately.32 Recently, the model continuity has been improved greatly. Many discontinuity issues in earlier capacitance models have been fixed.33 However, most capacitance models still cannot ensure the model symmetry when VDs=0. In Fig. 14 and 15, the asymmetries of the capacitance model in BSIM3v3 are shown for CGs=CGD, Q>0 and C^, and for CBD and CBS.i9 It has been known that a MOSFET should be symmetric for some capacitances at VDs=0, i.e. CDD=Css and CBD=CBS. The asymmetric issue in the capacitance model is apparently non-physical and may cause convergence and accuracy problem in the simulation. This issue may become more critical in the model for RF applications because the devices are often biased in the region of KDS=0V in some applications such as switching. Efforts have been made based on the source-referenced approach, the bulkreferenced approach and surface potential oriented approaches to improve the symmetry property of the models.34 The development of advanced capacitance models with good

140

MOSFET


1027

continuity, symmetry, accuracy and scalebility is still a challenge for the model developers.

V D S (V)

Fig. 14 Simulated Css and CDD as a function of VDS- Css *€DD when VDS-0. "

0.2 0.1 -

^

8 O

• \T \

0.0 -

1

y

-0.1 "

£

'a

-0.2-

o B o

-0.3-0.4-0.5-

Oss

....

f

W/L=10/0.5 1

t/SD

1 0.0

VBS=OV

1.0

1.5

2.0

2.5

V D S (V) Fig. 15 Simulated Css and CDD as a function of VDS. CBS ^BD when VDS~0.'9

141

1028

Y. Cheng

2.4. Modeling of the extrinsic

MOSFET

For an AC small signal model at RF, the modeling of parasitics is very important. The models for these parasitic components should be physics-based and linked to process and geometry information to ensure the scalability and prediction capabilities of the model. Also, simple sub-circuits are preferred to reduce the simulation time and to make parameter extraction easier. Besides a development of a physical and accurate intrinsic model discussed above, the following issues should be considered in developing a MOSFET model for deep submicron RF applications: 1) The gate resistance should be modeled and included in the simulation. 2) The extrinsic source and drain resistances should be modeled as real external resistors, instead of only a correction to the drain current with a virtual component. 3) Substrate coupling in a MOSFET, that is, the contribution of substrate resistance, needs to be modeled physically and accurately using approriate substrate network for the model to be used in RF applications. 4) A bias dependent overlap capacitance model, which accurately describes the parasitic capacitive contributions between the gate and drain/source, needs to be included. 2.4.1. Modeling of gate resistance At DC and low frequency, the gate resistance consists mainly of the poly-silicon sheet resistance. The typical sheet resistance for a polysilicon gate ranges between 20-40 £2/square, and can be reduced by a factor of 10 with a silicide process, and even more with a metal stack process. At HF, however, two additional physical effects appear, which will affect the value of the effective gate resistance. One is the distributed transmission line effect on the gate, and another one is the distributed effect or NQS effect in the channel.8,35 The distributed transmission line effect on the gate at HF has been studied.7 It will become more severe as the gate width becomes wider at higher operation frequency. So multi-finger devices are used in the circuit design with narrow gate width for each finger to reduce the influence of this effect. A simple expression of gate resistance, R0, based on that in DC or low frequency has been used to calculate the value of gate resistance with the influence of the distributed gate effect (DGE) at HF. However, a factor of a is introduced, which is 1/3 or 1/12 depending on the layout structures of the gate connection to account for the distributed RC effects at RF, as given in the following,

Rc.^^XZL^+Ot) N/Lf

(17)

a

where RGsh is the gate sheet resistance, ffyis the channel width per finger, Lf is the channel length, and Aîs the number of fingers, Wex, is the extension of the poly-silicon gate over the active region.

142

MOSFET


1029

Complex numerical models for the gate delay have been proposed. However, the simple gate resistance model with the a factor for the distributed effect has been found accurate up to VfTfov a MOSFET without significant NQS effects." The NQS effect or the distributed RC effect in the channel is another effect that should be accounted for in modeling the HF behavior of a MOSFET. For the devices with NQS effects, additional bias and geometry dependences of the gate resistance are needed to account for the NQS effect.8,35 It has been proposed that an additional resistive component in the gate should be added to represent the channel distributed RC effect.8 As discussed above, when a MOSFET operates at high frequencies, the contribution to the effective gate resistance is not only from the physical gate electrode resistance but also from the distributed channel resistance, which can be "seen" by the signal applied to the gate, as shown in Fig. 16. Thus, the effective gate resistance RG consists of two parts: Ra

=Ra.

poly +Ra,

mis

(18)

where Ra.poiy is the distributed gate electrode resistance from the poly-silicon gate material and is given by Eq. (17), RG.^ is the NQS distributed channel resistance seen from the gate and is a function of both biases and geometry.8,35

Fig. 16 Equivalent gate resistance consists of the contributions from the distributed gate poly resistance and distributed channel resistance.S3S

The HF characteristics of the gate resistance have been studied.35 In Fig. 17, it is shown that RG decreases first as Lf increases while showing a weak bias dependence in this region, then starts to increase with £/as Lf continue to increase above 0.4um while showing a strong bias dependence. The Lf dependence of Ra varies for different VGS. At lower VGS, the Lf dependence of Ra is stronger. Also, RG for the devices with longer Lf increases significantly and has stronger VGs dependence. Fig. 18 shows the Wf dependence of RG. It demonstrates that Ra increases as W^-decreases when Wfl

circuit of the substrate

network.17

Ysub

- r CP"

Rsub

—

B

Fig. 32 (c). One resistor EC for the substrate network

161

[37].

parameters-

1047

-i L f 0.36mm W(=12p W f12Mm 1^=10 OOO

Vf

•

r-

_ov R«.»«>»>f/>«">»">»»

100

Cffi rjctyiJrcajijrtmijpr^ranqmmrprar^ 8

9

10

11

Frequency (GHz)

Fig. 34 Extracted values ofCcc Cos, and C0D at a given bias condition.

162

MOSFET


1049

K

dam v~?ov

E O

Q?

V

=O.0V. 0.2V, 0.4V, 0.6V

50

tf§ÂS»S*&& —i—•—i2

4

10

12

Frequency (GHz) Fig. 35. Extracted values of substrate resistance at several different bias conditions.37

2.6. Simulations and comparisons with measurements According to the methodologies discussed above, a subcircuit model based on different core models can be developed. In this section, as an example, we present some results of the RF MOSFET model based on BSIM3v3.10'43 The model has been examined with devices of different geometries at different bias conditions from several technologies. Here we shown the results by using devices fabricated with a 0.25|im RF CMOS technology. Multi-finger devices with lengths Lf from 0.36|lm to 1.36fXm and width per finger (Wj) from 2.5|lm to 12|im are characterized with a HF measurement system consisting of a HP8510 network analyzer and a HP41421-Vtester. S-parameters are measured and are then converted to Y-parameters to facilitate the parameter extraction. The measured raw data are de-embedded with the two-step (open and short) procedure discussed in Section 2.5.1.38 The model parameters for the intrinsic devices as well as for the series source/drain resistances are extracted from the measured DC data. Other parameters for the extrinsic components such Ra, RDB, RSB etc. and some parameters for the capacitance model are extracted from the measured HF and AC data. The simulations with the subcircuit model show satisfactory agreement with experiments. As an example, Figure 34 shows a comparison of the Y-parameter characteristics between measurements and the model for devices with different geometries at VG=VD=W. Y-parameters in liner scale plots instead of Smith-chart plots are presented to clearly show the fitting of the model against measurements. The good match between the model and data proves that the simple subcircuit model can be accurate up to 10GHz. Figure 37 gives a comparison offj-ID characteristics between the model and measurements for several devices. Together with the plots in Fig. 36, it demonstrates that the subcircuit

163

1050

Y. Cheng

model can predict the HF characteristics of the devices with different geometries at different bias conditions.

„^

2

1.5X10- -

O o D

2x12u,mx0.36^01 10x12umx0.56um 10x12|imx0.36^101

C 0)

E v (/J

1.0x10-2.

Solid lines: Model Symbols: Measure data

£

5.0x10-3-

I ... Frequency (GHz)

Fig. 36 (a). Measured and simulated real and imaginary parts ofY,, characteristics for several different devices.4i

„

-5.0x10 4 ' -1.0X10-3 "BS" -1.5X10-3

°8

Solid lines: Model Symbols: Measure data

-2.0x10- 3

-2.5x10-3-

Q:

10x12nmx0.36nm 10x12pnnx0.56nm 2x12nmx0.36ujn

-3.0x10- 3

Frequency (GHz)

Fig. 36 (b). Measured and simulated real and imaginary parts of Yn characteristics for several different devices.4>

164

MOSFET

6x10-2 5x10-2 4x1tr2

T

O O °

~

~

2x12|imx0.36nm 10x12|imx0.36(im 10x12(imx0.56)im

Modeling

~\ • 1 ' Solid lines: Model

for RF IC Design

1051

r

Symbols: Measura data V

DS= V CE= 1 V BS

ov

3x10-2

52-

2x10-21x10-2

If

0

=8.

-1x10-2CD -2x10-2 -3x10-2

F r e q u e n c y (GHz)

Fig. 36 (c) Measured

and simulated

real and imaginary

parts of Yn characteristics for several

different

devices.4

~r

o c E

2x12jjmx0.36prn

°

10x12nmx0.56(j.m

o

10x12)jmx0.36nm

Solid lines: Model Symbols: Measure data v

txfvaf1v

V= • "^B

kf»tfrA$m ... JU_l„JL.i

0.02

0.05

i i ti

i

0.1 02 LgO/m)

i

i

i

93

j

i n

1J)

Fig. 45. Gate length dependence of flicker noise in n-channel MOSFETs with various gate oxide thicknesses."

177

1064

Y. Cheng

decreasing gate oxide thickness for the devices with such short channel lengths, although the gate leakage current becomes larger in the former. A possible mechanis m for the lowering of flicker noise in the devices with thinner oxides is the appearance of band-toband tunneling. However, as also shown in Fig. 45, for devices with channel length longer than 0.2|im, the flicker noise in the device with 1.5nm gate oxide is higher than that in the device with thicker oxide (2.2nm). As a understanding of this result, it has been believed that the higher flicker noise in such devices with longer (than 0.2um) channel length and thinner (1.5nm) gate oxide was caused by the much larger gate leakage current as the devices with longer channel lengths have larger gate area. Further theoretical and experimental investigations on this issue are needed to fully understand the contribution of the band-to-band tunneling and gate leakage to the flicker noise characteristic in today's devices. A compact flicker noise model with the consideration of band-to-band tunneling and gate leakage has not been reported so far. (ii) Modeling and simulation of flicker noise under switched bias conditions It has been reported that devices under switched bias conditions show lower flicker noise than those measured at DC bias conditions.60 Figure 46 shows a typical measurement result. The noise spectrum between 10 Hz and 100 kHz is shown for constant biasing (no switching) together with noise spectra resulting from a 10 kHz switched bias signal with 50% duty cycle. For 50% duty cycle, a low frequency noise power that is

1000 Frequency [Hz]

10000

100000

Fig. 46. Noise reduction as a function of the "off" voltage for an NMOS, V0So„ = 2.5 V, V,h=l = 10 kHz. duty cycle = 50%6'

178

MOSFET


1065

reduced by 6 dB compared to the constant-bias situation is expected. Further noise reduction is observed when the gate-source voltage in the 'off state is decreased, indicating an increasing noise reduction closer to accumulation. Figure 47 shows the results at various switching frequencies. All noise spectra appear to "merge" at low frequencies, with about 7 dB of intrinsic noise reduction (apart from the 6 dB related to 50% duty cycle). Even at MHz frequencies, where the settling of the output voltages becomes incomplete, this noise reduction is found. As switched biasing has been proposed as a technique for reducing the flicker noise in MOSFET's with reduced power consumption to benefit HF circuits,61 it becomes essential for RF MOSFET models to give a reasonable prediction of flicker noise performance of the device under such conditions. In order to do that, the flicker noise model contained in the RF model must be continuous and accurate over a wide bias range from strong inversion to accumulation and from linear to saturation regimes. Further work is needed to validate the flicker noise models with measured noise data in devices under switch biasing conditions and develop more advanced noise models for RF applications.

- * u -I

10

,

1

,

,

100

1000 Frequency [Hz]

10000

100000

Fig. 47. Noise reduction while switching at different frequencies for an NMOSFET, VGSo„ = 2 .5 V, Vcs,0ff = 0V, duty cycle = 50%. Also shown is the noise floor under the same conditions.61

179

1066

Y. Cheng

3.3. Thermal noise modeling 3.3.1. Existing thermal noise models At HF, although all the noise sources contribute to the total noise, the dominant contribution comes from the channel thermal noise. The channel thermal noise characteristics in MOSFETs operating in the strong inversion region have been studied for over two decades. The origin of this thermal noise has been found to be related to the random thermal motion of carriers in the channel of the device. Various models have been developed and some of them have been implemented in circuit simulators. A simple thermal noise model has been implemented in circuit simulators since SPICE2 was developed,62 SidJKsTGm (49) 3 where k is the Boltzman constant and T is the absolute temperature in K; Gm is the transconductance of the device. Other Similar models have also been proposed as given in the following:19,42,62 SIJ=SKSTGOS

(50)

3 „

_ SKaT(Gm + Gos)

„ _ %Kl>T(Gm+GDS+Gmb)

(ri\

(52)

3

where GDS and Gmh are the channel conductance and bulk transconductance. Most compact models developed for circuit simulation have their own thermal noise models. For example, BSIM3v3 includes the following equation to calculate the thermal noise of the device as a user option besides the one given by Eq. (52), Sid=4K*r&LQm

(53) Lqf where j % i s the effective carrier mobility, I c îs the channel length of the device, Qim is the total inversion charge in the channel. It has been reported that Eq. (50) gives a non-physical prediction of thermal noise at F D ÔV. 63 Eqs. (51) and (52) are proposed tofixthis problem even though their accuracy and physical basis need to be verified. Studies to validate the accuracy of the above noise models have been reported recently. 64 Some discussion will be given later. Another thermal noise model that is not implemented in all commercial circuit simulators but widely used for noise analysis by circuit designers is Sb*< =4KsTGiKh = 4KBTyGm

180

C54\

MOSFET


1067

where G„ch is the channel thermal noise conductance and y is a bias dependent factor, which for long-channel devices is equal to unity in the linear region and to 2/3 in saturation." The y factor has been used as a figure of merit to compare the thermal noise performance of different devices. It shows how much noise is generated by the device at the input for a given transconductance. It has been found that the y factor is not a constant for devices with different channel lengths and the y factor for short channel device can be larger than that for long channel device in the saturation regime due to both velocity saturation and hot electrons.65,66 Some models have been proposed to account for the velocity saturation effect 67 and hot carrier effects,68 but they have not been implemented in any compact model yet. Recently a simple thermal noise model is proposed to account for both velocity saturation and hot carriers and can be easily implemented.69 That noise model was originally developed for a transistor biased in saturation and in strong inversion,, but an extended expression has been proposed to cover the regions from weak to strong inversion by rewriting the noise parameter as " y

'

=

y ( 1 +

l2=2) G Leff'

(55)

where vml is the saturation velocity, % is a relaxation time (of the order of ps) used as a fitting parameter and G is the normalized GJID ratio, % is the y factor for the long channel device. This simple model assumes that the carrier velocity is saturated and that the lateral field is equal to the critical field all along the channel from source to drain. Although these assumptions are questionable, the resulting model can fit the measured data over bias and geometry. 6 ' 3.3.2. HF noise parameters" In noise model derivation and circuit simulation, the noise power spectral density is used as a measure for the noise output in the device. Circuit designers also prefer to use the noise power spectral density, the parameters related to the noisy two-port equivalent circuit. However, in measurements, the HF noise is usually characterized by several other parameters: the minimum noise factor (or minimum noise figure), the input referred noise resistance and the optimum source admittance for which the minimum noise figure is obtained. Therefore, it is necessary to discuss these parameters to understand their physical meanings and their relationship in describing the HF noise characteristics of the device. The noise factor is a figure of merit for the performance of a device or a circuit with respect to noise. The standard definition of the noise factor of a two-port network is the ratio of the available output noise power per unit bandwidth to the portion of that

More discussion on this topic can be found in the Chapter by Chen and Deen.

181

1068

Y. Cheng

noise caused by the actual source connected to the input terminals of the device. It can be given by the following equivalent equation, F=*1HL

(56)

Sol No where 5, and S0 are input and output signal; N, and N0 are input and output noise power. The noise factor can be expressed in decibels form, which is termed as the noise figure, that is, Afr = 101ogF

(57)

The noise figure of a two-port network is given by NF = NF miiH

\ys - yop\

(58)

where r„ is the equivalent normalized noise resistance of the two port network, ys=gs+jbs is the normalized source admittance, and y0pi=gopi+jbopt represents the normalized source admittance which results in the minimum (or optimum) noise figure NFmi„. The ys and yop, can be expressed in terms of the reflection coefficients 77 and ropti the ratio of the incident to the reflected wave along a transmission line

y,= . l - C

(59)

i+n

and 1 — I opt y»pt

(60)

i+rv

i, Eq. (58) becomes the following form 4

NF = NF^+

> l p '

r

^

2

(61)

O-lrfHi + rvi

In the HF noise measurements, the source reflection coefficient is varied until a minimum noise figure is reached. The value of NFml„, which occurs when r,= ropl, is read from the noise figure meter, and the source reflection coefficient that produces NFmi„ is determined by a network analyzer. The noise resistance r„ is measured by reading the noise figure when /7=0NFmi„ is a function of the biases (operating current) and frequency. Each NFmi„ is associated with one value of Top,. Figure 48 shows a typical measured characteristic of

182

MOSFET


1069

NFmi„ versus frequency for a RF MOSFET. Figure 49 gives a typical measured plot ofNFmi„ versus bias current. According to the measured noise characteristics, MOSFET can provide a low noise figure that is attractive to the RF applications. Also, a careful selection of the bias conditions is import for the device to achieve a lowest noise performance as shown in Fig. 49. Since RF MOSEFT with a very short channel length includes many different physical effects and contains non-negligible parasitics, it is not very easy to optimize the noise performance of the devices in a circuit with hand calculation by using analytical equations. So it is desirable that an RF model with accurate noise prediction is developed for use in circuit simulation. Whether a RF model can predict accurately the characteristics of noise figure versus bias currents for devices with different sizes is another challenge to device model developers.

4!>.

1

-T—'

'

tOSO-

V

DS=1V

V

BB=0V •

• 2.5-

•

2.0-

•

•

Finger numbers*1G Width per finger s 6^m Length=0.18jim

1.5LO-

•

•

•

-

OS0.03

4

5

Frequency (GHz)

Fig. 48 An example of measured NFmi„ versus frequency for a MOSFET.

4.035-

1

i

|

.

-1

•

1

•

Finger numbers=10 •

Width per finger=€lirn Length~0.18um

.

ID•

S' S

25•

J Z

•

•

Z0VBS=0V

1.5-

Frequency = 3 G H z

1.010

20

mA

los( ) Fig. 49 An example of measured NFmin versus IDS for

a

MOSFET.

As mentioned above, circuit designers prefer to use the parameters re lated to a two-port network to describe the noise performance of a device and a circuit. Universal

183

1070

Y. Cheng

noise models have been developed for any two-port network. A noisy two-port network shown in Fig. 50 (a) can be represented by a noise-free two-port network with two noise current sources, one at the input port (i,) and the other at the output port (i2) as shown in Fig. 50 (b). Figure 50 (b) can also be transformed to a noise-free two-port network in Fig. 50 (c) with a noise current source, Sm=4KBTGin, and a noise voltage source, S™ = 4KBTRW at the input port, where the v„ and i„ are correlated to each other and the correlation relationship is described by a correlation admittance Yc = Gc + JBc The noise source /'„ can be further separated to a noise source /„„ that is uncorrelated to v„ and a noise source /„cthat is fully correlated to v„ in = irm + Inc

(62)

inc = YcVn

(63)

and

The above relationship can be expressed in terms of noise power spectral density as follows: + S,nc

Sinc=\Y(S™

(64)

(65)

According to the two-port network given in Fig. 50, we further have the following relationships, v» =

h

(66)

Y21

in =h + Y\\Vn

(67)

Si 2

&2

S» = - ^ 7 = 4KaTR,

(69)

N2

Sm=4KBTGm

184

(70)

MOSFET


1071

(a)

(b) Ii

+ InQ

Noise-free two port

(c) Fig. 50. Noisy two-port and its ABCD-parameter representation.

Based on the above relationships, the four noise parameters discussed earlier can be calculated, (71)

Xtrt — IYv

k "'

opt

B

(10)

R

_

(ID (12)

_D

opt

cor

and NF„

=

l +

2R

n(Gcor+Gopt)

(13)

Another approach to calculate the noise parameters which is suitable for computeraided analysis is to use the generalized admittance matrix of a noisy two-port network.20'21 According to the noise circuit shown in fig. 1, we can write the admittance nodal equations at port 1 and port 2 as + B h =

P

/21 *22_

.'2

(14)

h

where [B] - [1 0] and [D] = [0 1], and define the noise correlation matrix [C] as M'l* 'lz2

[C] =

l2ll

(15)

l2l2

Using the y-parameters, [B], [C], and [D] matrices defined in (14) and (15), Ru, Gt and Ycor can be calculated from the following expressions21 1 R.. = " 4kTA-/•

-^x[D]*x[Clx[D]T [

2l

203

(16)

1090

C.-H. Chen & M. J. Deen

G

'

f
x).

5.1. Extraction of the channel noise As mentioned in section 2, the noisy two-port may be represented by a noise-free two-port and two noise current sources, one at the input port (ij) and the other at the output port (i2). From (8) and (10), the power spectral density of i2 can be obtained from

^L = 4 * r v | '21 V2

(63)

where k is the Boltzmann's constant, 7" is the absolute temperature, Y2i is m e transadmittance from port 1 to port 2 of the noise-free two-port and Rn is the equivalent noise resistance which is a resistance cascaded at the input port that will produce the same amount of noise power spectral density as i2 does at the output port. At low frequencies, if we convert the noise current sources associated with the parasitic resistances to noise voltage sources and assume that all the capacitors in the equivalent noise circuits of BSIM3 28 - 29 (shown in fig. 18), MOS 9 3 0 ' 3 1 (shown in fig. 19) and EKV 32 ' 33 (shown in fig. 19) models are open-circuited (i.e. all the admittances of the capacitors are approximately zero), the equivalent noise circuit can be simplified to that shown in fig. 21. Here, the thermal noise sources associated with the resistances as well as the channel noise current have been included in the figure. Also, note that at low frequencies, the induced gate noise and its correlation with the channel noise tend to zero and have therefore been omitted from the figure.

222

RF CMOS Noise Characterization

and Modeling

1109

Fig. 18. BSIM3v3 RF noise model and its simplified noise equivalent circuit (parts with thicker lines) at DC or low frequencies.28,29,34"37

G

Rg

G\

CQD

# /€s/i s /k\

,'*>

PU

^ " ^ f V a l 'd W8ds Qdd

!

9-rf=F W

fy

' '

dvy * - * At

iS-

£>'!

-'jun.d

D

W

A fV-jnn^

^fron ^* at T2i versus frequency characteristics for the n-type MOSFET with the channel width W = 10 x 6 um (10 fingers of width 6 um) and length L = 0.18 um biased at VDS = 1.0 V and VGS = 1.2 V.

0.01-1.0x10 • -2.0xl0 : jf

-3.0x10"

1

-4.0xl0":

>> -5.0xl0": -6.0xl0": -7.0xl0":

1

2

3

4

5

6

Frequency (GHz) Fig. 33. Measured (symbols) and simulated (lines) imaginary parts of y^ and y^\ versus frequency characteristics for the n-type MOSFET with the channel width W = 10 x 6 um (10fingersof width 6 um) and length L = 0.18 um biased at VDS = 1.0 V and VGS = 1.2 V.

Figures 34 to 37 show the extracted gm, RDS, CGS and CGD versus gate bias VGS respectively, for devices with different channel lengths. These extracted parameters give similar fitting accuracies as the y-parameters versus frequency characteristics shown in figs. 30 to 33 at all the gate biases shown in figs. 34 to 37.

235

1122


30 r

W=10x6nm

%

L=0.18um • I^0.27nm L=0.42nm

1ou

L=0.64um • L=0.97um

2.0

Fig. 34. Transconductance (gm) versus VGS characteristics extracted from the measured Re(y2i) at the low frequency region for the n-type MOSFETs with channel width W = 10 x 6 (im (10 fingers of width 6 um) and lengths L = 0.97 um, 0.64 urn, 0.42 urn, 0.27 nm and 0.18 urn, respectively, biased at VDS = 1.0 V.

L=0.97um L=0.64u.m L=0.42um L=0.27um L=0.18nm

Fig. 35. Output resistance (#DS) versus VGS characteristics extracted from the measured Re(y2i) at the low frequency region for the n-type MOSFETs with channel width W = 10 x 6 um (10fingersof width 6 um) and lengths L = 0.97 um, 0.64 urn, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V.

236

RF CMOS Noise Characterization and Modeling 1123

400

I V^l.OV

W=10x6nm

• - • - • - -•-•-•-i

• L=0.97um

300

fe

. _ , - • - • - • - • - • — - • — • — • - - • L=0.64um

200

^ ^ - A - A - A - A - A — A — A — A _ A L=0.42nm

100

^ • ^ - » • • • • — • — • — • L=0.27nm • ^ • - • • • — • — • — T — T L=0.18um

T-T

0

0.5

1.0 1.5 V^CVolt)

2.0

Fig. 36. Gate-to-source capacitance (CGS) versus VGS characteristics extracted from the measured lm(yn) at the lowfrequencyregion for the n-type MOSFETs with channel width W = 10 x 6 urn (10 fingers of width 6 um) and lengths L = 0.97 urn, 0.64 um, 0.42 um, 0.27 um and 0.18 urn, respectively, biased at the drain voltage VDS = 1.0 V.

160

L=0.97um

W=10x6um 120

V =1.0V

• L=0.64um

DS

£

80

. L=0.42um

40

< ^ I ^ - - * L=0.27um "^T—•L=0.18uni

m*$$^ 0.5

1.0

1.5

2.0

V ra (Volt) Fig. 37. Gate-to-drain capacitance (CGD) versus VGS characteristics extracted from the measured Im(yn) at the lowfrequencyregion for the n-type MOSFETs with channel width W = 10 x 6 um (10 fingers of width 6 um) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 um, respectively, biased at the drain voltage VDS = 1.0V.

The gate resistance (RG) used in the simulation for different channel lengths is obtained from *G

=

(90) 3 • « •L

237

1124 C.-H. Chen & M. J. Deen where RQSH = 5.17 Q and n is the number of fingers. In fig. 34, the VG$ bias for the peak gm decreases as the channel length is reduced, and this results in the shift of the peak / T shown in fig. 26. Although the peak gm increases when the channel length is reduced, the output resistance (Rps) m fil- 35 decreases at the same time, and this results in the amplification factor (Ay(Hy= gm x RDS) remaining about the same at the V G S where the peak gm occurs. Based on the element values extracted from the measured y-parameters and noise parameters, figs. 38 and 39 show the extracted channel noise and induced gate noise versus frequency characteristics for n-type MOSFETs with different channel lengths biased at V DS = 1.0 V and V GS = 1.2 V. It is shown that the channel noise, in general, is frequency independent and increases when the channel length decreases because of the higher drain current at the same V DS and V GS bias. The solid lines in fig. 38 are the extracted channel noise based on the method described in section 5.1 which provides an alternative way to verify the channel noise extracted by the proposed method. The small increase in the channel noise at low frequencies for deep sub-micron devices might be caused by the inaccuracy of the measurement system at low frequencies. In fig. 39, the induced gate noise is proportional t o / 2 (solid lines in the figures) where/is the operating frequency. In addition, when channel length decreases, the induced gate noise also decreases because of the decrease of gate-to-source capacitance Q J J , as shown in fig. 36. Therefore, the strength of the induced gate noise is mainly determined by the gate-to-source capacitance instead of the voltage or current fluctuation in the channel.

V =1.0V V =1.2V DS

GS

1E-21

-w-* L=0.18um

• • •

* • • • • • • » » • • I^0-27um &.

A

A A

L=o.42um

A A A A A A A A

— • • • • • • • • • • L=0.64um • • • • • • • , • • •

I^0.97um

W=10x6um 1E-22 0

1 2

3

4

5

6

Frequency (GHz) Fig. 38. Extracted channel noise (ij) versusfrequencycharacteristics for the n-type MOSFETs with channel width W = 10 x 6 urn (10 fingers of width 6 |im) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V and VGS = 1.2 V. The solid lines are the extracted channel noise based on the method in section 5.1.

238


1x10

L=0.97um L=0.64um

1x10

> L=0.27um

L=0.42uin L=0.18um

h~« lxl0_24 1x10 Frequency (GHz) Fig. 39. Extracted induced gate noise (i-?) versus frequency characteristics for the n-type MOSFETs with channel width W = 10 x 6 urn (10fingersof width 6 um) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V and VGS = 1.2 V.

Figure 40 shows the extracted noise correlation between the channel noise and induced gate noise versus frequency characteristics for n-type MOSFETs with different channel lengths biased at V D s = 1.0 V and V G S = 1.2 V. It shows that the noise correlation between the channel noise and the induced gate noise is proportional / In addition, when channel length decreases, the noise correlation also decreases because of the decrease in the gateto-source capacitance CGS.

8x10 r L=0.97um

6x10"" •

L=0.64um 4x10"" L=0.42nm 2x10"

L=0.27um L^.18um

2

3

4

5

6

7

Frequency (GHz) Fig. 40. The noise correlation between i* and i\ ( ' „ ' / ) versus frequency characteristics for the n-type MOSFETs with channel width W = 10 x 6 um (10 fingers of width 6 um) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V and VGS = 1.2 V.

239

1126


Another useful parameter that is sometimes used to describe the relationship between the channel noise, induced gate noise and their correlation is the cross-correlation coefficient c, which is defined as,

y/

(91)

W Figure 41 shows the extracted cross-correlation coefficient c versus frequency characteristics for the devices with different channel lengths. In general, c is frequency independent and decreases when the channel length is reduced. This implies that the channel noise and the induced gate noise are less correlated for the shorter channel length devices. These results show an opposite trend to the simulated results presented in Refs. 49 and 50

0.6 r V^l.OV

W=10x6nm

§ 8 u S o o

s

-* b=0.97um 0.4-

• L=0.64um

*-*-r A A

L=0.42um

A A

0.2

L=0.27|xm

•

-*-*0.0

1 2

T •

b=0.18um

T

3

4

5

6

7

Frequency (GHz) Fig. 41. The cross-correlation coefficient c versus frequency characteristics for the n-type MOSFETs with channel width W = 10 x 6 urn (10fingersof width 6 um) and lengths L = 0.97 fim, 0.64 \xm, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDs = 1.0 V and VGS = 1.2 V.

For the V G S bias dependence of the extracted noise sources, figs. 42 and 43 show the extracted i| and fl versus V G S characteristics for the n-type MOSFETs with channel width W = 10 x 6 um and lengths L = 0.97 ^.m, 0.64 \im, 0.42 |am, 0.27 um and 0.18 um respectively, biased at V D s = 1.0 V. The channel noise is caused by the voltage or current fluctuation in the gradual channel region which is from the intrinsic source terminal to the pinch-off point, and from the saturation region which is from the pinch-off point to the intrinsic drain terminal. For long channel devices, the channel noise mainly comes from the gradual channel region. However, for short channel devices, the noise from both regions has to be taken into account. It is shown that the channel noise has a strong V G S dependence and it increases, but then tends to saturate when V G S increases. On the other

240

RF CMOS Noise Characterization

and Modeling

1127

hand, the induced gate noise has a weak VQS dependence because it is mainly determined by the gate-to-source capacitance CGS instead of the voltage or current fluctuation within the channel of the transistor.

1.5xl0'2

T

W=10x6|am V =1.0V DS

1.0x10"'

P-

5.0x10"'

•

•

A'

•

A

L=0.18um

T

I

u

• L=0.27um

A

A L=0.42um

•

• L=0.64um

•

• L=0.97|xm

A.

O.OL

li

0.5

1.0

1.5

2.0

V^CVolt) Fig. 42. Channel noise (i? ) versus V GS characteristics for the n-type MOSFETs with channel width W = 10 x 6 \im (10 fingers of width 6 fim) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 urn, respectively, biased at V D S = 1.0 V.

1x10"

I '•••,

I

I

'••

| L=0.97um L=0.64|im

AA,

••

••

A •

2

!§ lxlO"

TT

TTT

10"

T

A A L=0.42Lim • • L=0.27Mm

A

Ty

•

V^l.OV W=10x6nm 0.5 1.0

1.5

• L=0.18um 2.0

V^CVolt) Fig. 43. Induced gate noise (ij;) versus V G S characteristics for the n-type MOSFETs with channel width W = 10 x 6 um (10 fingers of width 6 um) and lengths L = 0.97 um, 0.64 |im, 0.42 um, 0.27 um and 0.18 um, respectively, biased at V D S = 1.0 V.

Figures 44 and 45 show the extracted correlation noise i Jd* and the cross-correlation coefficient c versus V G S characteristics for the n-type MOSFETs with channel width W = 241

1128


10 x 6 Lim and lengths L = 0.97 Jim, 0.64 Lim, 0.42 iim, 0.27 Lim and 0.18 Lim respectively, biased at V D s = 1.0 V. For the correlation noise, it increases, then tends to saturate when V GS increases. This follows the V G S dependence of the channel noise. However, the correlation noise decreases when the channel length is reduced and this follows the channel length dependence of the induced gate noise. On the other hand, the cross-correlation coefficient tends to decrease when V G S increases. It is because of the faster increase in the channel noise compared to the correlation noise, and it follows the trend predicted in Ref. 17. 3x10 W=10x6um

L=0.97um

v K =i.ov 2x10 F L=0.64um :•

2 lxHT

•

• L=0.27um . • , T .l>0.18nm 2.0 1.5

,••••••• JTTTTTTT

0

0.5

L=0.42um

*

.••:*

C3

T

1.0 V„

c s ^

Fig. 44. The correlation between fl and A ('J/ ) versus VGS characteristics for the n-type MOSFETs with channel width W = 10 x 6 um (10fingersof width 6 um) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V.

0.6 a 'o 0.5

8 u

vDS=i.ov W=10x6um 1

0.4

a o 0.3

1

A

0.2

! u 0.1

***•••••

I CO

a

T

0.0

L=0.97um

0.5

T T

•

•

T,

1.0

1.5

•

L=0.64um ' L=0.42um • L=0.27um L=0.18um 2.0

V Fig. 45. The cross-correlation coefficient c versus VGS characteristics for the n-type MOSFETs with channel width W = 10 x 6 um (10fingersof width 6 um) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V.

242


For the V D S dependence, figures. 46 and 47 show the extracted channel noise versus V GS characteristics at different V D s biases for the devices with 0.97 |im and 0.18 jam channel length, respectively. For the long-channel devices, because the channel noise is mainly contributed from the gradual channel region, it is not sensitive to different V D s biases. However, for the short-channel devices, the saturation region contributes considerable noise power to the overall channel noise. Therefore, the channel noise will increase when the V D s bias is increased because of more noise current contributed from the saturation region than the decrease of the noise current contributed from the gradual channel region. 3.0x10

1.0x10 5.0x10

V GS (Volt) Fig. 46. Channel noise (/^ ) versus VGS characteristics for the n-type MOSFET with channel width W = 10 x 6 um (10fingersof width 6 um) and length L = 0.97 um biased at VDS = 1.0 V, 1.2 V, 1.5 V, 1.8 V and 2.0 V, respectively.

1.8xl0'21 r L=0.18um W=10x6um 1.2xl0"21 h

6.0x10"

0.0 VGS (Volt) Fig. 47. Channel noise (ij) versus VGS characteristics for the n-type MOSFET with channel width W = 10x6 M.m (10fingersof width 6 um) and length L = 0.18 um biased at VDS = 1.0 V, 1.2 V, 1.5 V, 1.8 V and 2.0 V, respectively. 243

1130 C.-H. Chen & M. J. Deen In order to verify the accuracy of the extracted noise sources, and compare the simulation results against the measured data and those based on van der Ziel's model which is suggested for long channel devices, figs. 48 to 51 show the measured (symbol) and simulated (lines) noise parameters versus frequency characteristics. The simulations are performed using the direct calculation technique described in section 3.1 • for the n-type MOSFET with the channel width W = 10 x 6 Jim and length L = 0.97 Lim biased at V D S = 1.0 V and V G S = 1.2 V. In these figures, the solid lines are the simulated results based on the extracted noise sources (solid lines in figs. 38 to 40) and the dashed lines are the simulated results based on van der Ziel's model in which the power spectral density of the noise sources are given by 'J =

(92)

ySatn4kTSdo 2_2

i2

co C0

g

= 5satn4kT-r-

(93)

and

°do

(94)

V 7 = *satn4kTJ

V/////'//////77777? Wafer B

Polishing

SOI Wafer

Fig. 2. Fabrication process for SIMOX (A), BESOI (B) and Smart-Cut (C) SOI wafers.

n+ poly gate

KflaETTraas

N

j

Lb .iu)'ffvn"rri"'

P B: Fully depleted

*—1 Source/ i ^ J drain Depletion

A: Partially depleted

HH Inversion Hill Accumul. C: Accumulation mode D: Volume inversion

^

Neutral

Fig. 3. Types of SOI MOSFET's (for sake of conciseness, only the Si film and active gate material and oxide are represented, not the buried oxide and underlying Si substrate).

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Kink effect

vD

vs -W-

*

v

B

•*•

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Gb

Fig. 4. Typical PD SOI MOSFET structure and ID-VD curves for various gate biases.

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\ Source \

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•

-•.

,

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=•3

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as ©

i

>•?

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-Cl

a

03

Gati

H-gate contact

'normal" lateral contact Fig. 5. Typical body tie layouts.

On the contrary, MOS transistors realized on SOI films thin enough to allow the depletion region to extend across the whole film (Fig. 3.B) feature dramatically reduced FBEs due to the reduction of the source barrier. Furthermore they exhibit superior device characteristics with respect to bulk MOSFET's: sharper subthreshold slope close to an ideal 60 mV/decade value at room temperature, improved drive capability due to smaller body effect and mobility degradation with gate voltage19. These properties result from the front-to-back gate coupling through the Fully-Depleted film capacitance as will be detailed in Section 3. The main drawback of Fully-Depleted or FD devices is-the sensitivity of the threshold voltage to the film thickness and buried oxide parameters, the latter ruling out the use of thin-film FD SOI devices for total-dose radiation-hardness applications. Threshold voltage dependence on the film thickness can however be minimized holding the film total dose constant rather than the doping concentration . Threshold voltage standard deviations similar to bulk devices have indeed been achieved for FD SOI MOSFET's. The use of thin-film SOI substrates, in which, by definition, the lateral isolation field oxide extends down to the buried oxide providing complete dielectric isolation of neighbor devices, considerably eases the fabrication of deep-submicron MOS devices 279

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either FD or PD. When compared to conventional bulk process, threshold voltage roll-off is indeed minimized, reliable ultra-shallow junctions are easily processed, wells and latchup are suppressed and complicated lateral isolation process can be avoided. In addition, although defect densities may be higher in SIMOX films than in bulk substrates, SOI process yield may actually be higher than that of bulk since SOI devices and circuits are much more tolerant to defects1. Unique buried-channel MOS devices, such as p-channel transistors featuring P + source and drain and P" uniformly doped channel regions, can be built on thin-film SOI substrates9 (Fig. 3.C). No current flows as the device is turned off because of the full depletion of holes in the channel region. When the device is turned on, an accumulation current flowing in a surface channel adds to the buried current that flows in the undepleted part of the film. As a result, so-called accumulation-mode or AM devices (Fig. 3c) show low leakage currents, almost ideal subthreshold slopes, as well as excellent drive capability due to the combination of several conduction mechanisms and the use of low doping levels which favors higher mobility. P-type AM devices are of particular interest because -0.7 to -0.4 V threshold voltages are easily achieved using hT-polysilicon gate material, thereby avoiding the problem of boron penetration into the gate oxide when using P+-doped polysilicon. Various processes using p-channel AM transistors have been proposed21, as well as processes with both n- and p-AM devices22. However, originally, AM devices were not candidates for deep-submicron ULSI integration due to shortchannel effects and punchthrough characteristics not as well controlled as in enhancement-mode FD transistors. Nevertheless the feasibility of 0.2 urn AM MOSFET's has been demonstrated23. Double-gate (DG) thin-film MOSFET's may be regarded as the ultimate FD devices24'25 (Fig. 3.D). Also called volume-inversion devices due to the extension of the inversion layer across the whole Si film, these transistors feature very high drive currents, ideal subthreshold characteristics and totally suppressed body effect. The threshold rolloff is moreover much reduced. However, although several fabrication processes for DG devices have been proposed26'27 and some circuits have shown very promising performances, in particular for total-dose radiation-hardness ' ' ' , the fabrication unfortunately remains non-standard which presently jeopardizes the use of DG devices for ULSI applications. Nevertheless the 1999 SLA roadmap and numerous publications clearly point out the need for DG devices to simply and efficiently control the shortchannel effects below 70 nm of channel lengths32'33

2.4. High-speed low-power digital circuits SOI CMOS is already considered as a very attractive technology for the realization of low-voltage low-power (LVLP) digital ULSI circuits and has a number of well-known advantages over conventional bulk Si CMOS34'1. The power and speed performance of simple logic gates are usually characterized by means of the following relationships: Power = Delay ~

fC{vddf

cvdd K{VM-VJ

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where / is the frequency, C the total capacitance of the logic gate, VM the supply voltage, Vth the threshold voltage and K a constant which is inversely proportional to me body factor. These relationships clearly show that simultaneous reduction of power and delay can only be achieved by reducing the capacitance, which is a long-known advantage of SOI. It has been recognized for a long time that the SOI dielectric isolation provides much reduced parasitic capacitances with respect to bulk CMOS. In the latter case, the source/drain loads indeed correspond to junction capacitances, which depend on substrate or well doping and bias voltage (Fig. 6). The technological trend towards reduced dimensions and supply voltages inherently leads to an increase of die source/drain junction capacitances per unit area. In thin-film SOI, die source/drain capacitances are mainly defined by the buried oxide mickness and hence are tremendously reduced when compared to bulk, both regarding the bottom area (Cj„, Cjp) and sidewall components (Cjswn. CjSWp) (Fig. 6). In recent deep submicron CMOS processes, the SOI source/drain junction capacitance reduction even achieves factors on the order of 10 when compared to bulk. The parasitic capacitances of polysilicon and metal interconnection layers are also reduced in SOI due to the presence of die thick buried oxide, but to a lesser extend depending on the technological stack height.

c

jswn - '

-

-

• ""

~jswp

CVitau bulk /SOI -1.3

Fig. 6. Comparison of bulk and SOI junction capacitances for a typical 1 \xm CMOS process (Q and Qsw denote the bottom area and sidewall peripheral junction components at zero bias).

Overall, the typical speed increase and power decrease related to SOI reduced parasitic capacitances amount to about 30 to 40 % versus comparable bulk CMOS circuits. From Eq. (1), another obvious way to preserve the speed performance while reducing the supply voltage is to decrease the threshold voltage. In bulk implementations this can only done at the expense of an increase in the leakage current and hence in static power dissipation. Fully-depleted SOI transistors offer the opportunity to limit that degradation owing to their almost ideal subthreshold slope, as well as to further increase die drive current owing to their smaller body factor. These characteristics all add up to significantly increase the power times delay capability, in particular for reduced supply voltages, as discussed below.

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2.5. Perspectives Years of worldwide research and development in universities and industrial research centers were necessary to demonstrate the benefits and manufacturability of SOI. The industrialization phase towards mainstream production started in August 1998 with the announcement of IBM's plans to ramp-up its SOI technology towards, firstly, the fabrication of commercial high-speed microprocessors6. IBM chose to rely on its ownfabricated SIMOX material and on a PD SOI CMOS process which at this time, proved to be more straightforward and reliable to scale to sub-0.2 um channel lengths, than FD devices requiring very thin SOI films in order to control the short-channel effects . Inherent PD floating-substrate effects are controlled at the design level by proper simulation and timing of critical digital paths36. Nevertheless the FD process has been proved to be the best option for 0.25 um and above SOI CMOS and its controllability is improving at a rapid pace. Scalability towards sub-0.13 um dimensions has been demonstrated on 30 nm-thin SOI films37. The cost issue has long been said to delay the use of SOI for commercial applications. SIMOX or Smart-Cut substrates are still about 3 times more expensive than identical size and comparable quality bulk Si wafers. Nevertheless a past Sematech study demonstrated that if the higher starting cost could be reduced by a factor of 2, the revenues to be made from mass production of 64 Mb SRAM could be substantially higher using a SOI instead of a bulk CMOS process. The reasons are: fewer processing steps, better fabrication yield, smaller chip size and enhanced performance38. More recently, IBM claimed that, even considering the present cost of their SIMOX substrates, the total "SOI wafer + CMOS process" fabrication is only 10 % more expensive than the corresponding bulk Si CMOS process. The SOI material cost decrease could be driven by the development of a high-volume application such as DRAMs. SOI implementation of DRAMs was not considered at first because the SOI film thickness drastically limited the depth of the buried storage capacitor thereby increasing the required cell area. However with the advent of stacked memory capacitors built atop the cell transistors, DRAMs on SOI have been tested and showed considerable improvements over bulk counterparts in cell area and access time39. Nevertheless, there currently remains a critical problem to be overcome regarding SOI use for high-volume applications, namely wafer availability, which in year 2000 does not exceed 2 million pieces per year. The challenges for low-power low-voltage analog and microwave SOI CMOS circuits, however, have not been as widely investigated. Preliminary theoretical results nevertheless showed that analog circuits, in particular operational amplifiers, benefit from the lower body effect and load capacitances in FD SOI CMOS40-41'42'43. On the other hand, preliminary experimental results also showed that submicron FD SOI MOSFET's may achieve transition frequencies in excess of 20 GHz for supply voltages on the order of 3 V . Combined with the ability to realize low-loss matching or interconnection lines on high-resistivity SOI substrates45 and the drastic reduction of substrate crosstalk figures46, these properties may lead to the future development of single-chip mixed digital/analog/microwave solutions. A recent development of SOI applications is related to the field of integrated sensors. High-precision thin membranes can indeed be easily processed on SOI substrates owing to the good control of the film and buried oxide thickness. High-performance pressure sensors as well as accelerometers for use in airbag electronic systems have already been produced.

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3. Properties of Fully-Depleted SOI MOSFET's 3.1. Introduction With SOI emerging as a key technology for the realization of future low-voltage lowpower (LVLP) CMOS circuits, the impact of the improved characteristic* of SOI MOSFET's on speed and power consumption has already received a lot of attention in digital circuitry1. The challenges for analog SOI CMOS circuits, however, have not been as widely investigated. The reduction of parasitic capacitances and the feasibility of diffusion resistors and capacitors free of junction effects have however long been recognized as advantages for the realization of analog circuits on SOI substrates48. Nevertheless, few SOI analog circuits have been reported, presumably because the occurrence of the kink effect in thick-film partially-depleted (PD) SOI MOSFET's severely degrades the output conductance characteristics in saturation1 and thereby the performance of analog circuits. Solutions to the kink effect such as the use of body contacts49 or twin-gate devices50 have been implemented in operational amplifiers but the results showed little improvement of the performances over bulk CMOS counterparts, exception for the ability to withstand elevated temperatures in excess of 300°C51. The kink effect is known to be greatly reduced in thin-film fully-depleted (FD) SOI MOSFET's. Moreover FD devices provide much smaller subthreshold swing and substrate factor than bulk or PD SOI MOS transistors1. This might offer interesting opportunities for LVLP analog circuits. The present section will present the major properties of FD SOI MOSFET's, of interest for the analog circuit design and operational amplifiers (opamps) in particular, i.e. the I-V characteristics of MOS transistors in saturation and principally, the ratio of transconductance over drain current, the output conductance and the intrinsic gate capacitances. Noise, linearity and dynamic range performance will be briefly treated as well. In addition, an engineering model, efficient for opamp design, will be validated.

3.2. I-V characteristics and body effect - impact on digital circuits The main interesting feature of FD SOI MOSFET's is the low value of the body-effect coefficient, which influences both the current drive of the device and its subthreshold swing. The body-effect coefficient, denoted n, is an image of the ideality of the coupling between the gate voltage and the surface potential. It is well known that FD SOI devices offer near-ideal coupling, which yields a value of n close to unity, contrary to bulk Si MOSFET's. This can be intuitively explained by relating the body effect to the capacitive division between channel, gate and substrate potentials (Fig. 7).

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D. Flandre, J.-P. Raskin & D. Vanhoenacker- Janvier Bulk Si MOSFET

mmmsmm;3®is!s& S//////J//JWM'f'(

i

Fully-depleted SOI MOSFET

i C Vs^r T

CH

'B

Fig. 7: Comparison of bulk and SOI MOSFET space charge regions and body effect models.

In a bulk transistor, n is then given by n =l+-

£„•

(2)

where COT is the gate oxide capacitance per unit area, esi is the permittivity of silicon and ^dmax *s m e m a x i m u i n depletion width in strong inversion. In a bulk CMOS process with channel lengths around 1 um (i.e. corresponding to a gate oxide thickness of about 30 nm), n is equal to 1.4-1.6 typically. In a 0.25 um processes, the scaling down of the gate oxide to about 5 nm is partly counterbalanced by the Xdmax reduction due to doping level increase which yields typical n values of 1.2 - 1.3. In a SOI FD MOS transistor, on the other hand, the body effect is given by

« = 1+-

(3)

Cjcsi/(

+Coxb

where Coxb and tsj are the buried oxide capacitance and the silicon film thickness, respectively. Typical n values reduce to 1.05 - 1.1 for a 1 um processes with oxide thickness tm, silicon thickness tsj and buried oxide mickness tmb equal to 30, 80 and 400 nm respectively and even reduce to 1.01 - 1.02 for a 0.25 um processes with tgx, r and roxb equal to 5,40 and 400 nm respectively. The influence of the body-effect coefficient on the current drive of the device can be best understood by using a simple device model. The saturation drain current of a MOSFET is given by the following expression:

tDsa,=^Cox^-(Vg5-Vlhf

(4)

H being the effective mobility, V the gate-to-source bias, Vth the threshold voltage and W and L the width and length of the device respectively. From the above equations, it follows that the saturation drain current may be 30-40% higher in a FD SOI device than in a bulk device with similar parameters, depending on body effect.

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A more accurate model for submicron devices would include velocity saturation and series resistance effects52. These tend to somewhat degrade the superior current drive capability of FD SOI MOSFET's as short channel lengths are considered. It has been shown however that non-optimally designed FD SOI transistors still present a 25% current drive improvement over comparable bulk devices for gate lengths down to 0.2 um which could be restored to even better values with optimization of the device structure . In addition, the subthreshold swing (inverse subthreshold slope) of a MOSFET is also affected by the body effect. Indeed, the subthreshold swing is given by the following expression1: S(mV/dec.)=n—In(l0) 1

(5)

if the influence of the interface traps is neglected. The low value of n in FD SOI devices yields an improvement of the subthreshold slope over bulk devices. Almost ideal subthreshold swings of 60 mV/dec at room temperature corresponding to the predicted n values have been experimentally demonstrated for optimally designed FD SOI MOSFET's with channel lengths down to 0.2 um54. As a result, a lower threshold voltage can be used in SOI devices without jeopardizing the OFF leakage current (Fig. 8a), and ON drive current much higher than in bulk devices can be obtained, in particular for reduced supply voltage (Fig. 8b).

Gate Voltage (V)

Supply voltage (V)

(a)

(b)

Fig. 8. (a) Subthreshold slope of bulk and fully depleted SOI MOSFET's, (b) Ratio of fully depleted SOI to bulk saturation drain currents.

Fig. 9 validates these concepts comparing the Id-Vd curves of short-channel nMOSFET's, from SPICE model results of three available 0.25 um CMOS processes: bulk, PD SOI with body tied to source or not, FD SOI. The impact of the improved FD SOI CMOS characteristics on speed and power consumption has already received a lot of attention in digital circuitry. ASIC's and gate arrays have been realized showing speed improvement factors over bulk counterparts by up to 1.7, with a 3 V power supply ' . Circuits built on a 0.5 um FD SOI CMOS IM gate array showed twice the speed or half the power consumption of similar bulk CMOS circuits when operated at 2 V supply voltage.

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1.40E-03

1.20E-03 1.00E-03 ^

/^^M--~"~

"""

8.00E-04

•

•

•

0.6

cQ 0.4 bt ^H

0.2

y

•

*

•

+

•

•

•

•

x

^

t

^

^^****^

'

0

1.5 2 2.5 3 Supply voltage V D D (V) Fig. 19. Maximum admissible symmetrical threshold voltage of n-/p-channel devices for minimal-dimension CMOS switch with maximum on-resistance of 50 k£2, as a function of VDD-

The drift of MOS transistor current-voltage curves with temperature significantly affects the correct operation of Si MOS integrated circuits. Typical static device characteristics (Fig. 21) clearly show that contrary to SOI, bulk Si MOSFET's present, above 200°C, drastically reduced ON-to-OFF current ratios and threshold voltage values which are not compatible with acceptable noise margins in digital circuits or with bias stability in analog circuits.

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1.5 2 2.5 Supply voltage V D D (V)

3

Fig. 20. Bulk and SOI CMOS switch off-currents resulting from the threshold voltages of Fig. 19 as a function of the supply voltage. Also represented is the limit corresponding to a relative error of 10"4 due to the discharge of a 2 pF-capacitance during a 1 us-holding phase.

-2

-1

0

Gate Voltage (V) Fig. 21. Drain current versus gate voltage curves of SOI (solid line) and bulk (dashed) 20/5 p-MOSFET's with Vo=3V.

Fig. 22. Simplified bulk Si MOSFET cross-section depicting depletion region extension (gray) under channel (dark) and total drain junction area contributing to leakage (large dashed line). Note that other source and wellsubstrate junctions could also contribute to leakage if reverse biased.

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The increase with temperature of MOSFET OFF leakage currents (/;«,*), defined for OFF gate bias condition typically equal to 0 V, is related to the degradation of important MOS electrical parameters: the threshold voltage (V,/,), the subthreshold slope (5) and the reverse-biased junction saturation current (Ijs). These are linked to the increase with temperature of the intrinsic carrier concentration (n/) and of the thermal voltage (U, = kT/q). In a bulk Si MOSFET (Fig. 22): • Vth decreases as the Fermi potential (ty) and the depletion width and charge under channel reduce with temperature. • IjS is proportional to n, and the total bottom and sidewall drain junction area (AjD) below 150°C when generation mechanisms in the junction depletion region dominate, and is proportional to AjD and n,2 above 150° when diffusion mechanisms of excess carriers in the quasi-neutral transition regions become dominant. The temperature behavior of a thick-film PD SOI MOSFET is very similar to bulk. Since the channel depletion region does not extend across the whole active film thickness, it changes with temperature modifying V,h and leaves a quasi-neutral region in the film contributing to junction leakage by diffusion mechanisms. However when the film is thin enough so that the junctions extend down to the buried oxide, A]D reduces to a single sidewall component proportional to the channel width (W) and film thickness (*„•) thereby drastically limiting Ijs. In a thin-film FD SOI MOSFET, the channel depletion extension being equal to the film thickness, it remains constant with temperature and V,h only depends on <j>f. Furthermore, as quasi-neutral regions are suppressed, only generation mechanisms may contribute to Ijs, which is now proportional to «/ and the depletion region volume, i.e. W.L.tsi where L is the channel length. These basic physical behaviors are confirmed by measurements of IJs and V,h as a function of temperature, and performed on bulk and FD SOI MOSFET's (Fig. 23). It may be observed that: • bulk Iis may be up to 1 uA/um of device width at 300°C, and almost three orders of magnitude lower in FD SOI; • bulk Vth may shift by 2 to 5 mV/°C depending on doping, temperature86, etc., whereas FD SOI V,h only shifts by 0.7 to 1.5 mV/°C as long as the device remains fully depleted. Indeed, as the maximum depletion width is reduced when temperature increases, there exists a critical point, typically between 200 and 300°C depending on device optimization, above which FD SOI transistors feature a bulk-like dependence of the threshold voltage and leakage current because the film becomes partially depleted87'88'89. Three more problems of bulk Si CMOS structures1 related to leakage current and threshold voltage variations with temperature should be pointed out: • previous data did not take into account the significant leakage current of the reverse-biased well-to-substrate junctions which are required to isolate e.g. n-MOS devices realized in the P-doped bulk Si substrate from p-MOS devices located in very large-area N-doped wells contacted to the positive supply voltage.

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0

100

200

300

(°C)

Janvier

0

100

200

300

Fig. 23. ljs and V,h evolutions with temperature for bulk (+) and FD SOI (o) MOSFET's (W = 20 Jim).

•

the isolation of individual bulk Si MOSFET's also involves a thick field oxide structure which may give way to lateral parasitic transistors. Their threshold voltages are normally set much above the maximum supply voltage by field implantation, but this is usually not guaranteed for very high-temperature operation due to threshold voltage lowering. • N-P-N-P thyristor-like parasitic structures and related latch-up problems are then unavoidable in bulk Si CMOS circuits. Latch-up may potentially be triggered at lower voltages for temperatures higher than at room temperature, due to the dramatic increase of thermally generated substrate leakage currents. All these three process-related problems are totally suppressed by buried oxide isolation in SOI CMOS structures'. The basic electrical behaviors previously described explain the unavoidable physical limitations of bulk and PD SOI CMOS digital circuits operated at high temperature. Measurements on bulk Si CMOS logic gates show leakage currents per elementary gate on the order of 1 uA at 250°C even though their design was fully optimized for hightemperature operation90'91. On the other hand, FD SOI CMOS logic gates demonstrate leakage currents per inverter lower than 10 nA at 300°C without any design optimization. Similarly the measured standby currents of bulk Si and PD SOI CMOS 64 kb SRAM's 92 increase with temperature following a n,2 dependency. The latter is almost two orders of magnitude lower than the former due to drain junction area reduction (Fig. 24). However extrapolating these values for a 1Mb SRAM of interest for future VLSI applications, we end up with a static power dissipation under 5 V operation larger than 1 W at 300°C even with PD SOI technology! This seems to definitely prevent the use of bulk Si and even questions PD SOI CMOS for VLSI integration at elevated temperature, contrary to FD SOI. Furthermore, the lower temperature dependence of the FD SOI MOSFET characteristics is not only of interest for very high-temperature conditions above 200 °C, but also in the usual range of operation for IC rated up to e.g. 125 °C according to standard burn-in test conditions. Also note that starting at 125-150°C, the leakage current in PD SOI MOS is already reduced by about one order of magnitude when compared to bulk. Fig. 25 compares theoretically a conventional bulk CMOS technology with 0.7 V threshold voltage and 90 mV/dec subthreshold swing to a FD SOI CMOS featuring 0.5 V and 60 mV/dec values respectively, chosen for equal leakage at room temperature. At 300


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125°C, both the bulk and FD SOI threshold voltages are lowered to approximately 0.4 V, but the better SOI subthreshold swing yields a leakage current figure more than one decade below bulk. Also note that low threshold voltage bulk CMOS results almost unpractical under such conditions. 1Mb SRAM

64Kb

10

1

> 10 0

in

® 10" o PL,

10

>-> c

CO

10" 150 200 250 Temperature (°C)

350

Fig. 24. Bulk Si and PD SOI CMOS 64 Kb SRAM standby current dissipation vs. temperature and extrapolation of standby power dissipation for 1 Mb SRAM under 5 V supply operation.

-4 v

T.bult - 0.5 - 0.3 V

= 0.5 - 0.1 V Viibulk-0-7-0-^1

0.5 1.0 Gate Voltage (V)

'

'

•

•

2.0

Fig. 25. Extrapolation of bulk and FD SOI MOS characteristics at 400 K.

This theoretical extrapolation has recently been demonstrated comparing the experimental leakage currents of 0.25 \im bulk and FD SOI MOSFET's which feature Ioff values of about 20 pA/fim93 and 2.2 pA/u.m, respectively94. This may be of tremendous importance regarding the stand-by or static power dissipation of portable systems, as well as die possibility to run IDDQ testing methodologies for rapid production validation. Reciprocally, FD SOI CMOS circuits could be tested under more severe burn-in 301

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conditions, approximately 50 to 75 °C higher than in bulk for similar leakage currents, leading to reduced testing time and costs by a factor of about X according to the classical Arrhenius law.

3.6. Conclusion SOI CMOS can now be regarded as a very attractive and mature technology for the realization of low-voltage low-power (LVLP) digital ULSI circuits owing to a number of well-known advantages over conventional bulk Si CMOS: • dielectric isolation provides reduced parasitic capacitances and leakage currents when compared to junction isolation. • full-depletion (FD) operation of thin-film SOI MOSFET's may yield quasiideal device properties such as sharper subthreshold slope, lower body effect and smaller vertical field mobility degradation. Improved subthreshold slopes in turn allow for the use of lower threshold voltages for identical subthreshold leakage current values. These characteristics all add up to significantly increase the drive capability, in particular for reduced supply voltages. • thinned films and dielectric isolation result in simplified submicron CMOS processes: threshold voltage roll-off is minimized, reliable ultra-shallow junctions are easily obtained, wells and latch-up are suppressed and complicated lateral isolation process can be avoided. • the low temperature dependence of FD SOI MOSFET's drastically minimizes the increase of the leakage currents for typical ratings above 70100 °C, thereby reducing the stand-by power consumption in this range of temperature or enabling rapid IDDQ or burn-in testing above 125 °C. Regarding analog properties, available models for the important small-signal conductance and capacitance characteristics of fully-depleted SOI MOSFET's have been discussed and validated. These have been exploited to investigate the impact of the improved device characteristics of FD SOI MOSFET's, i.e. smaller subthreshold swing, body factor and parasitic capacitances, on the performances of several basic analog cells. We have found that: • CMOS analog switches can still be operated at a supply voltage as low as 1.2 V when optimized in FD SOI CMOS. • FD SOI CMOS has the potential to boost the speed, accuracy, power and area performances of 1- and 2-stage operational amplifiers well over bulk implementations, especially when moderate inversion operation of the active devices is considered, as is common in LVLP circuits. • the linearity properties of FD SOI MOS resistors could be much better than those of bulk counterparts, which is of high interest for LVLP filter implementations. By demonstrating the great potential of FD SOI CMOS for high-performance analog and mixed-mode analog-digital low-voltage low-power applications, this study has opened a whole new field of applications for this technology. In the next sections, the analysis will be extended to microwave performances and finally applied to high-performance circuit design.

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4. Microwave Characterization of Passive Elements on the SOI Substrate This section is devoted to the analysis and modeling of passive elements on SOI substrate, starting with a preliminary analysis of the behavior of the SOI substrate at high frequencies. This model is used afterwards for the transmission lines and integrated inductors.

4.1. High frequency behavior of the SOI substrate The fundamental difference between the Si substrate and the GaAs substrate is the fact that the silicon resistivity is lower then the GaAs one, so that Si cannot be considered as a dielectric for microwave applications. The behavior of the substrate is a function of bias conditions and frequency and will be analyzed for the microstrip structure represented in Fig. 26. The microstrip transmission line is considered as a quasi-TEM transmission line, the transverse lineic (i.e. per unit length) elements are a capacitor and a conductance accounting for the substrate losses. The behavior of the MIS (Metal-InsulatorSemiconductor) capacitor illustrated in Fig. 27, has been reported in the literature for some years. Some models are based on the behavior of the charges in the structure but most of them are limited to a few MHz, assuming that the majority carriers in the semiconductor are responding to voltage variations without delay95,96'97'98' 10°. The relaxation time of the majority carriers is neglected. On the other hand, some authors had a special interest in the distribution of electromagnetic fields in planar lines on semiconductor substrate. Hasegawa101 defines three fundamental modes in such structures: • the dielectric quasi TEM mode • the skin-effect mode • the slow-wave mode.

I Sl(»,

Metal

>*~*—• • •—•"—• • — • — • • • • ' » dielectric mode -6

? o 0|0 -2

o"poop

0 2 dc Bias Condition [V]

Fig. 28. Small-signal characteristics of SOI capacitive structure versus applied dc voltage for various frequencies, d0I = 1 (im, ds, = 500 |im and psi = 4000 Q.cm.

The classical theory explains the low frequency curves: • for positive bias conditions, there is an abundance of electrons below the oxide. For a p-type substrate, this is called an inversion layer. At low frequencies, the minority carriers follow the excitation. This is not the case anymore when the frequency increases (see Fig. 28 in the kHz range). The inversion layer charge cannot keep up with fast variations of the voltage and the required charge changes are provided by covering or uncovering acceptor atoms at the bottom of the depletion region, just as in the case of depletion operation. When the frequency increases above 1 kHz, the inversion layer cannot follow the variations because it is isolated from the outside world. Thermal generation and recombination only can change its electron concentration; those phenomena are very slow. • for negative bias conditions, there is an abundance of holes below the oxide (accumulation), forming the "bottom plate" of the capacitor. As a consequence, the total capacitance is approximately equal to the oxide capacitance. The 2D-Medici simulator gives results in agreement with the above-mentioned theory for low frequencies. It however takes into account the distribution of the potential and the carrier concentration, as well as their evolution with frequency, so that the simulation shows a rapid decrease of the equivalent capacitance for positive and negative bias conditions, at frequencies above 1 MHz. A further decrease happens between 1 MHz and 1 GHz. The section below will briefly explain the behavior of the capacitive structure versus the relaxation time of the carriers.

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4.1.2. Influence of the relaxation time of the minority and majority carriers on the parameters of the MOS capacitor The relaxation time of the minority carriers expresses the inertia of the inversion layer under the oxide layer. For a p-type substrate, the minority carriers are the electrons. Three sources can supply minority carriers to the inversion layer: an electron diffusion current from the bulk silicon, a volume generated current within the depletion region or a surface generated current directly related to the surface states at the insulator-semiconductor interface. Sah et al"°. have demonstrated that the finite generation-recombination within the space charge region is the dominant factor controlling the frequency response of the inversion layer. The generation and recombination of electron/hole pairs carry out the charging and discharging of the inversion layer through traps in the depletion region. These traps may be crystal lattice dislocations, impurity atoms located interstitially or substitionally in the crystal lattice, or surface defects. Hofstein and Warfield96 define for the strong inversion layer regime, a resistance Rgr associated with this generationrecombination: Rgr=^h

(16)

where \j/s, X& n, and x0 are, respectively, the surface potential, the thickness of the depletion region, the density of electrons or holes in an intrinsic semiconductor, and the time carrier density fluctuation to decay to its equilibrium concentration by recombination through traps. This lifetime is typically the order of 10"6 sec. This equivalent resistance allows taking into account the frequency response of the inversion layer. The relaxation time of the minority carriers is given by Tgr = RgrCb,

where Cb is the capacitance

associated to the depletion region under the oxide layer. The simplified equivalent circuit for SOI capacitive structure represented in Fig. 29 is valid in the strong inversion regime. The limits of the equivalent capacity Cgb are

Cgb —> Cox

for

co«x~gr

and

C +C Cgb —» —^ — for co > r~ . In weak or moderate inversion and in depletion regime C

oxCb

C C this model is not valid for co « T~r]. Cgb tends to — o x c

with Cc - C, + Q,.

Cox + Cc

Tsividis104 gives a general expression of Cc valid in all regimes. The depth of the depletion layer depends on the substrate doping, so it is with the capacitor Cb. As a direct consequence, the relaxation time of the minority carriers depends strongly on the substrate resistivity: the minority carriers react up to higher frequencies for higher resistivity silicon substrates. The inertia of the majority carriers is often neglected in the literature. The 2-D Medici simulator however shows that this hypothesis is not valid anymore for frequencies higher than a few MHz. When frequency increases up to GHz, neither minority neither 306


1193

majority carriers follow the variation of the applied potential. The silicon substrate is then considered as a dielectric with losses. The final model for inversion mode, taking into account the minority and the majority carrier inertia, is represented in Fig. 29; Csi and Rsi represent the inertia of majority carriers.

Oxide layer

Minority carriers inertia

Majority

carriers inertia

T Fig. 29. Complete model for capacitive structure valid for inversion mode.

Measurements have been performed up to 500 MHz, to check the validity of the model (Fig. 30). The measured capacitor has been made on a SOI wafer with an oxide thickness of 0.4 u\m and a silicon substrate thickness of 500 urn. The capacitive structure has an area of 900x1200 um2. 100 C„

inversion • O Model Measurements

ilr iimffiiiil ^— 0

Frequency [Hz]

307

(a)

1194



J

with

d = max{Lhto„Lvtol) Ho the permittivity of vacuum N, ws and s as defined above.

(4JI107)

4.4.4. Model of Yue The model of Yue134 gives a full equivalent circuit for an inductance with the output grounded. The parameters of the inductance are represented in Fig. 39. There are no limitations given by the author. The value of the inductance is calculated by using the Greenhouse algorithm135.

Fig. 39. Equivalent lumped circuit of an inductor integrated on SOI.

314


1201

1) Model for the ohmic losses The series resistance Rs of the spiral with underpassing strip takes into account the skin depth of a conductor with finite thickness and the current distribution in a microstrip conductor:

*.=4=' _wA-e-'s')

Wu{\-e-'»'s»)

(20)

with Sm - j2pm/oofi , pm is the metal resistivity at DC, Sm is the metal skin depth, t is the thickness of the metal layer, / is the overall length of spiral, ws is the strip width, tu is the metal thickness of the underpass layer, lu is the length of the underpass between centre of spiral and the output access and W is the width of the underpass. 2) Model for the parasitic capacitance The parasitic crossover capacitance Cs between spiral and the underpass strip is approximated as a parallel-plate capacitance by: C=nw.WuÊs.

(21)

where n is the number of crossovers between spiral and underpass and doxMP is the oxide thickness between spiral and underpass. 3) Model for the substrate effect The expressions of parasitic elements for an inductor realised on SOI substrate are derived from the relations given by Yue. The parasitic capacitors and resistance of the SOI substrate are expressed by: C„=I/w,S£« 2

(22)

d„

Csi=LlWsMjL 2 dsi Rs.=2£i!^L lws

(23) (24)

where / is the overall length of spiral, ws is strip width, do% is the oxide thickness between spiral and substrate, psi is the silicon substrate resistivity. Finally, the equivalent parallel admittance elements Rp and Cp are obtained respectively from the real and imaginary parts of the admittance resulting from the series connection of oxide capacitance Cgx with the complex admittance WR + j40 1.929 30 5.502 31 4.466 3.6 30.5 4.954 20.5 7.4 19

UCL final model UnH) 1.8 3.2 2.56 2.94 4.5

--

Measurements

Fr(GHz) L(nH) 36 1.66 30 2.91 30 2.53 27 2.74 21 4.15 6.82 -

Fr(GHz) 37.2 28.4 26.9 25.9 19.1 11.9

Table 2: Comparison of the various models on a subset of inductors.

The positive and negative coupling is taken into account in the Yue model, which explains its good accuracy in the evaluation of the inductance value. The new model developed by UCL predicts the resonant frequency with a good accuracy, is able to calculate inductances on substrates composed of various layers, lossy or not, and to take into account the geometrical parameters of the spiral. It is not linked to a particular technology.

5. Deep-Submicron DC to RF SOI MOSFET Macro-Model 5.1. Introduction Thin-film short-channel SOI MOS technology appears to be a good candidate for lowpower microwave circuits because of its excellent performance in terms of gain, speed and cutoff frequency137138'139. Therefore, there is a need for an accurate submicron RF SOI MOSFET model with adequate non quasi-static extensions for designing RF circuits. Very little work has been done in RF SOI MOSFET modeling. Furthermore, even in bulk MOSFET modeling, the RF extensions presented so far have a very limited accuracy. The present standard bulk MOSFET models for circuit simulation, such as BSIM3v3, are not accurate enough in high-frequency operation140, because they include neither the extrinsic elements, nor the intrinsic non quasi-static effects (which arise because of the channel propagation delay), and because of their poor fitting and scaling of the intrinsic 317

1204

D. Flandre, J.-P. Raskin & D. Vanhoenacker-

Janvier

device transconductance and output conductance, which critically affect the gain and the S-parameters. As a result, these standard models can be used only for frequencies up to a few GHz140141, and with the restriction of a small range of channel lengths and bias conditions. In a recent work an effort has been done in order to account for the intrinsic non quasi-static effects by introducing a distributed channel resistance seen from the gate ; however, this approximation requires the use of an additional fitting parameter, the final expression of the resistance has to be evaluated numerically and furthermore, it cannot be used in large-signal analysis. The model presented in Ref. 143 accounts for nonquasi-static (NQS) effects by using a voltage controlled current source in parallel with the intrinsic capacitances and admittances; the additional transadmittances are calculated from first-order expansions. However, again, this model is only valid for small-signal analysis only. The model we present in this section can be applied for both small and large-signal analysis. In our circuit model, following Tsividis100, we split the transistor into three shorter transistors in series along the channel length (Fig. 41); this technique automatically takes into account the channel delay propagation effects. An accurate quasistatic intrinsic model is used for those shorter transistors144. This DC model is an extension to the deep-submicron range of our previous unified and charge-based fullydepleted SOI MOSFET model. Then, we combine our intrinsic model with a complete model for the extrinsic part of the device, with scalable equations for its components and which includes an additional lumped capacitance, which is necessary in order to properly account for the effect of the distributed gate resistance on the phase of the S-parameters. A similar technique was used in Ref. 145 for bulk MOSFET's with channel lengths longer than 0.35 um. However, in this reference the device parameters were extracted for the sectioned channel length, by global optimization. In this model, all but two of the parameters, the ones which control DIBL (Drain Induced Barrer Lowering) and the charge sharing, are independent of the number of channel sections and can be extracted using the DC model with just one section. Gate

Fig. 41. SOI MOSFET split into 3 sections along die channel length.

We validated the complete proposed macro-model by comparison with the measured current gains, Maximum Available Gains (MAG's), and the modules and phases of the Sparameters for fully-depleted SOI MOSFET's with effective channel lengths down to 0.16 u.m and for frequencies up to 40 GHz.

318


1205

5.2. Model Description 5.2.1. Extrinsic Part This new model is based on the equivalent circuit shown in Fig. 42. This equivalent circuit is an enhancement of our previous one146, in order to include all the extrinsic capacitances which represent the coupling effects between gate, drain and source metallization levels (Fig. 43a), excluding the line access parameters (e.g. series inductors), which do not depend on the device size (but circuit design). For simplicity, we consider one finger of width equal to W.

c

1

—r-

Intrinsic Bi MOSFET

-wwc

ei

—|—Cfe*

—i— C

VI X> 3 C/3

"1

Si

Fig. 42. Complete equivalent circuit topology for a SOI MOSFET CAD model.

The exact distributed nature of the gate resistance is accounted for by performing a careful small-signal analysis. The small-signal propagation effects along the gate width (Fig. 43b) can be accurately modeled by inserting an effective resistor, R , in series with the gate terminal, and an effective capacitor, C e, in parallel with R e. The values of both elements are proportional to the gate width. Rge and Cge arise from the first and second order terms, respectively, of the Taylor expansion of the admittance expression. The value of 7?^ is found to beRge =^„,,/3 139 (where Rlotis the total gate resistance, Rlot =Wppoly, Ppoiy b e i n g

tri

e polysilicon gate resistivity and W the gate width), and the value of c

is

141

determined as Cge ~Cg/5 (where Cg is the total gate capacitance) . Many models do not consider the lumped capacitor c „ ; however it critically affects the values of the phase of the S-parameters. In this model, for the extrinsic part of the device, we consider the geometry dependence of all elements. The extrinsic source and drain resistances affect the power gain of the device and should be accurately modeled. Assuming that the main contribution comes from the resistance of the diffusion region, the resistance at the source or drain is evaluated as: RXe =Ldiffrdiff IW, where Ldiffis the diffusion length and rdiff is the diffusion sheet resistivity. rpoiy and rd\g are extracted directly from S-parameters measurements as explained in the next section.

319

1206 D. Flandre, J.-P. Raskin & D. Vanhoenacker- Janvier

There are several components of the extrinsic gate-source and gate-drain capacitances (Fig. 43a). Cgse and Cgde are the overlap gate-source and gate-drain capacitances. Q « corresponds to the proximity parasitic capacitance between the drain and source diffusion regions, partly accounting for the effect of the back gate (assumed floating in our RF equivalent circuit) too.

-.. .~ ^ Gate porysilicon

W (b)

Fig. 43. (a) Cross-section of the SOI MOSFET showing'the extrinsic capacitances and (b) top view of one gate finger indicating the distribution of the gate resistance along the transistor width.

These three capacitance elements, Cgse, Cgde and Cdse can be assumed to be proportional of the finger width. Cgsee, Cgdee and Cdsee are the extrinsic capacitances due to parasitic couplings between metallic interconnection lines outside the transistor active zone between gate-source, gate-drain and drain-source, respectively.

5.2.2. Intrinsic Part In order to account for the channel propagation delay effects, the channel of the transistor is split into several smaller sections along the channel length where quasi-static conditions can be fulfilled and a quasi-static model can be applied. This approach is also valid for large signal simulation. Regarding delay effects, the accuracy of the model becomes better

320


1207

by increasing the number of these smaller transistors, but the computation time also increases. Furthermore, the DC equations must remain valid for the smallest subsections, which may be hard to achieve for section lengths below 0.05 Jim. A tradeoff between accuracy and computation time is thus necessary. We have found that the splitting of the channel into three sections is a good choice. In each transistor we use the expressions of the quasi-static drain current and charges given by a new submicron fully-depleted SOI MOSFET model we have developed. This model is an extension of our previous model144'146 to the deep-submicron regime, and it has been validated for channel lengths down to 0.16 |im. The model looks very adequate for the RF equivalent circuit, because it has the advantages of being physics-based, scalable, charge conserving and infinitely continuous through all operation regimes, and accurately predicts the values of the intrinsic DC, small and large signal parameters. The drain current and charge equations are written in terms of continuous expressions of the inversion charge densities at the source and drain ends of the channel; therefore, the same parameters can be used in all the equations. The most important short-channel effects are included using continuous equations: velocity saturation, channel length modulation, charge sharing and DIBL. We also account for relevant effects in deep-submicron technologies, neglected in standard models: quantum effect on the effective gate oxide thickness147, short-channel effects in the charges, impact ionization at high lateral fields and adequate scaling. This is of great importance to allow channel splitting into sections of lengths smaller than 0.1 urn. Only two parameters (the ones that model DIBL and charge sharing) have channel-length dependences and therefore, they have different values for a different number of sections. This model has been implemented in the ELDO circuit simulator and tested by simulating some benchmark circuits. In the quasi-static model, the drain current is written as: W

h=L

eff

an x |

, I \ VT{.

" S ^

3 0 h

>*

N.

^**_

g 3

>

-

E

\V

1n » r

\\\ \ v\ \ >

S ,„i

10 r

\ \

N.

0h

0.3

1

2 3 5 Frequency [GHz]

10

20

40

Fig. 50: Comparison of measured and modeled MAG for a SOI nMOSFET with Ltg = 0.16 |4m.

15

20 25 Frequency [GHl]

15

20 25 Frequency [GHz]

(a) (b) Fig. 51. Comparison of measured (lines) and calculated (symbols), using a distributed small-signal model, (a) magnitude (b) phase of the S parameters. SOI nMOSFET with Us = 0.16 urn.

330


1217

5.5. Conclusion We have developed a Fully-Depleted SOI MOSFET macro model valid from DC to RF. Because of the physical modeling of the intrinsic and the extrinsic parts, including the distributed nature of the gate and channel R-C lines along the length of the transistor channel, our macro-model has proven to be very accurate for frequencies up to 40 GHz and effective channel lengths down to 0.16 (J.m.

6. Microwave Characterization of the SOI CMOS Transistors 6.1. Silicidation for the reduction of the contact resistance Thin-Film SOI MOSFET's are fabricated with a CMOS-compatible process on lowresistivity (20 Qcm) SIMOX wafers. The initial 200 nm silicon film is thinned down to about 100 nm by oxidation and oxide strip. After a semi-recessed LOCOS isolation step, a 30 nm gate oxide is grown and boron is implanted to adjust n- and p-channel threshold voltages. A 340 nm thick polysilicon is then deposited, doped (implantation, As, 100 keV, lxlO16 cm"2) and patterned. Arsenic (80 keV, 4xl0 15 cm 2 ) and boron (20 keV, 5xl0 15 cm"2) are implanted to form the source/drain regions, followed by an RTA (950°C, 40 sec) activation step. Then, a 150 nm thick Si0 2 is deposited and etched by RIE to form spacers. After a short-time 2 % HF dip, layers of titanium, titanium/cobalt stack layer or nickel are deposited with thickness of 30 nm, 7 nm/13 nm and 25 nm, respectively using an e-gun system. The conventional 2-step SALICIDE (self-aligned silicide) process is used for titanium152153 and cobalt154 silicidation (Ti: 675°C, 45 s and 900°C, 15 s; Ti/Co bilayer: 675°C, 45 s and 900°C, 30 s). Nickel monosilicide155156157 is formed with a onestep annealing at 550°C for 40 s. Unreacted metals are selectively removed by a H2SO4+H2O2 (2:1) mixture. A nitride/oxide layer is then deposited and contact holes are opened to access the devices. An aluminum metallization is used to complete the process. The gate sheet resistance of the wafers with TiSi2, CoSi2 and NiSi are 6.2 £2/square, 4.4 fl/square and 2.8 £2/square, respectively. For high frequency applications, it is necessary to reduce the gate, source and drain resistance.

6.2. S-parameter measurement and stability At high frequencies, it becomes difficult to measure voltage and current and the devices are characterized by their scattering matrix (S-parameters).

V 'su

S12

a

_5 I2

5 22 _

a

P2.

\

. 2.

where a* and bj are the incident and reflected waves respectively, defined in units of square roots of watts, at the input and the output of the device. The S-parameters of the transistors are measured on wafer by using a Vector Network Analyzer. The calibration of this instrument, using commercial coaxial standards (for example K connectors) allows to compensate for the losses and phase shift 331

1218 D. Flandre, J.-P. Raskin & D. Vanhoenacker-Janvier

of cables and connectors. The reference planes of measurement are then set to the output plane of the connectors. For on-wafer characterization however, it is necessary to transfer the reference planes on the wafer itself, close to the device to be measured. Commercial impedance standards are available to transfer the reference planes to the probe tips. Due to the different material characteristics of the calibration structure and the substrate, an additional correction is necessary to access the "exact" device characteristics. Another possibility is to develop an on-wafer calibration kit, as the one mentioned in Section 4.3. Different calibration methods are available121, but the variation of the characteristic impedance of the coplanar waveguide with frequency needs its accurate determination.

Fig. 52. Layout view showing a MOSFET embedded in a probing structure. The vertical dashed lines represent thereferenceplanes.

The reference planes of measurement are then brought close to the device to be measured and are represented by dashed lines in Fig. 52. Having measured the Sparameters, it is then possible to fully characterize the device by its figures of merit but also to extract its equivalent circuit. Before using a transistor, it is important to check its stability. Representing a transistor as a two-port, with a source and an output load (Fig. 53), one may calculate the input reflection coefficient of the device, loaded with rL as = 5„ +

i - s22rL

(34)

and the output reflection coefficient of the same device with an input load having a reflection coefficient of fs as Tow - $2:

332

(35)


a

1219

b2

l

1 transistor

1 Fig. 53. Representation of the transistor as a two-port device. The device is unconditionally stable if the input and the output reflection coefficients, rin and rm„ are less than unity for all the possible loads TL and F s . The stability can also be expressed by the Rolled: stability factor:

*=-

1-S,,

2 2 - \S 22 - A 2|S12S21

(36)

where A = S12S21 - 5, ,5 22 The active device is unconditionally stable if k >1 and potentially unstable when k R^ and Rse. After silicidation, the parasitic extrinsic gate resistance is approximately reduced by a factor 10 and fmax is triple. Figure'55 presents the evolution of fT and/ mai versus bias conditions for silicided FD and PD 12x(6.6/0.35) urn2 SOI nMOSFET's. The slight improvement of cut-off frequencies obtained with FD SOI nMOSFET's can be related to the improvement of the gate transconductance and the reduction of the output conductance and channel time delay. The frequency band of the network analyzer being limited up to 40 GHz, the cutoff frequencies above that limit are determined by simple linear extrapolation of the corresponding gains in logarithmic graphs. Due to the measurement and extrapolation inaccuracies, an error of around 15 % can be attributed to these extrapolated cut-off frequencies. That inaccuracy can explain the similar values of /„„„ obtained for FD and PD SOI nMOSFET's at higher bias conditions (V^ = Vgs > 0.7 V).

60

50

a40 2. 130

§• 10

'0~2" 0.3

0.4

0.5 0.6 0.7 0.8 0.9 1.0 Polarisation (Vds= Vg!) [V]

1.1

1.2

Fig.55./r andfimu as a function of supply voltage (Vds = Vgs) for silicided FD (solid lines) and PD (dashed lines) 12x(6.6/0.35) um2 SOI nMOSFET's.

Figure 56 presents the evolution of fT and / „ , versus the channel length of various silicided SOI nMOSFET's having a total gate width (W) of 80 urn and bia; = Vgs = 0.9 V. The cut-off frequencies increase with the reduction of the channel length. The dependence in 1/L2 offT is in accordance with the simplified expression (41). In fact, Gmi 335

1222



being proportional to W/L and (Cgs+Cgd) to WL,fT is a function of 1/L2. fmm has also a dependence in 1/L2 for large channel lengths but this increase rate decreases for L smaller than 0.5 urn because the increase of Rge with the reduction of the channel length (L) becomes dominant in equation (41).

°0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Length [um] Fig. 56. Cut-off frequencies versus channel gate length for 0.35 um FD (solid lines) and PD (dashed lines) SOI nMOSFET's at Vds = Vg! = 0.9 V.

These results are among the best published in the literature on silicided fully depleted SOI nMOSFET's. M. Harada159 has obtained current gain and unilateral gain cut-off frequencies of 19 GHz and 27 GHz respectively, for 12*(5.0/0.25) um2 transistors at 1 V. The performances are directly dependent on the control of the silicidation process for thin silicon films. Furthermore, the microwave performances of these transistors compare very favorably with bulk silicon devices of similar gate length, operated at much larger power consumption. Texas Instrument160 has published the following results for silicided bulk nMOSFET's (L=0.1 um, Wtot = 256 um): fT = 120 GHz, fmax = 28 GHz. Toshiba has obtained silicided bulk nMOSFET's cut-off frequencies of fT = 35 GHz, / = 45 GHz under 2.5 V for CoSi2 silicided transistors (L=0.25 um, Wtot = 200 um)161, and/ mai of 60 GHz and 70 GHz for 0.15 um and 0.1 um respectively162. It can be concluded that fully-depleted SOI nMOSFET's have similar microwave performances as bulk transistors, with a lower power consumption (Vps lower than IV), which is very important for low-power, low-voltage consumer applications163. A comparison between various high frequency devices and the perspectives for Si devices has been presented by J. Gautier et al.'64. As a conclusion, the fully-depleted silicided (TiSi2) 0.25 Um SOI MOSFET transistors are fully suitable for microwave applications, with cut-off frequencies fn^ a n d / r of about 50 GHz for V^s = 0.9 V. This low voltage value, when compared to bulk CMOS, is very attractive for low power telecommunication applications. Their fabrication process is fully compatible with usual CMOS process.

336


1223

6.4. Noise parameters measurement An important parameter for high frequency design is the noise figure, representing the diffusion noise of the device. The noise model used for the nMOS is derived from the Pospieszalski model165, applied to the extrinsic device. Two uncorrelated noise sources are added to the small signal equivalent circuit: an input noise voltage source ein and an output noise current source iOM. These two noise sources can be represented by equivalent noise temperatures Tin and Tou,. Accurate knowledge of transistor noise parameters (NFmin, Rm \rop,l and arg(rop,)) is required in performing realistic and reliable design of Low Noise Amplifiers (LNA), which are the key elements of high sensitive microwave receivers. These parameters can be calculated given the noise sources. More details about the physical interpretations of the measured high frequency noise parameters, but also general interest material and the limitations of SOI MOSFET technology for the realization of ultra-low-noise circuits can be found in Ref. 166. Figure 57 represents the cut-off frequencies (fT and f^) and the minimum noise figure (NFmin) for a 0.25 um FD SOI n-MOSFET with a current density of 100 mA/mm. A current gain cut-off frequency fT and an extrapolated maximum oscillation frequency /„3i*"

'•••'

0.6200

300

Jds (mA/mm)

Fig. 58. Comparison between 12x(6.6/0.25) |im2 FD and PD SOI nMOSFET's: evolution of NF^ and G«„ as a function of the drain current density at 6 GHz and Vd, = 1 V. -•-Fully |

| -•• Partially 1.2-1

•

0

i

~t'

i

10

o . 03 •

1010

10 Frequency (Hz)

Fig. 71. One-stage OTA simulated (-) and measured (o) total transconductance as a function of frequency. 40

:- -.. 30

a 20 O 10

k "

,

"

•

iid.-... x

0

1

-10 10°

10'

v

-

10°

i_; HT

10 10

Frequency (Hz) Fig. 72 Measured voltage gain of the one-stage with G=2pF (- -) and 6pF (-) and the folded-cascode opamps

withCi=6pF(-).

The quite low DC voltage gains Av are due to the device short channel length and the strong inversion operation. Nevertheless for second order sigma-delta converters with low 350

SOI CMOS TYansistors for RF and Microwave Applications

1237

over sampling rate or using reduced gain sensitivity technique e.g., these gain values are sufficient. They may also be sufficient for other high-frequency switched-capacitor filtering applications.

7.1.3. Conclusion Our OTA synthesis methodology has further been exploited to investigate the impact of the improved device characteristics of FD SOI MOSFET's, i.e. smaller subthreshold swing, body factor and parasitic capacitances, on the performances of several basic OTA architectures. We have found that FD SOI CMOS has the potential to boost the speed, accuracy, power and area performances of 1- and 2-stage operational amplifiers well over bulk implementations, especially when moderate inversion operation of the active devices is considered, as is common in LVLP circuits. By demonstrating the great potential of FD SOI CMOS for high-performance analog and mixed-mode analog-digital low-voltage low-power applications, our study has opened a whole new field of applications for this technology. Furthermore, our synthesis procedure has been successfully extended, in other works, to a number of other CMOS OTA architectures (two-stage Miller OTA43, folded-cascode 2-stage OTA, regulated-cascode 3-stage OTA171, multipath hybrid nested Miller 4-stage OTA, etc.), considering a variety of small- and large-signal specifications (gain, transition frequency, phase margin, settling time, noise, slew rate, distortion, PSRR, CMRR, etc.), and operating conditions (high-temperature169; high-frequency80; capacitive and resistive loads ) as well as applications (instrumentation opamp173; MOSFET-C continuous-time filter172; SC L-A modulator174175, RF carrier detector176, current-mode structures177, capacitive pressure transducers178, radiation-hardness179180). The validity of the synthesis procedure has been successfully demonstrated by the experimental realizations of several of those circuits.

7.2 Microwave oscillators Two basic oscillator families are used in the microwave frequency domain: series and feedback oscillators181. They are represented in Fig. 73. Due to high substrate losses and source biasing difficulties, parallel feedback structures were chosen: the first one with active feedback and the second one with passive feedback (inductance). The active feedback structure is represented in Fig. 74. It can be viewed as 2 inverters face to face, with a tank inductor in parallel. The oscillation criteria imposes that the impedance of the inductance ZL should meet the following conditions Re(Z L +Z o „,) 4. These performances can be easily achieved on SOI with a spiral inductor136. The circuit schematic is shown in Fig. 74 and, with more details, in Fig. 75. VI

Z2

I

ir

Y3

Y2 Z3

Fig. 73. Microwave oscillators structures (a) series feedback, (b) parallel feedback.

w

•**0W

T

Si

1

a) Silicon dangling bond

Si

I

—Si

o

Si--Si O

\)

j

J

Si

b) Oxygen dangling bond

O—Si

Si

c) Oxygen vacancy V 0

Fig. 2. Atomic structures of defects in the bulk of silicon dioxide.

At the silicon-silicon dioxide interface, a family of traps generally known as Pj, centers exist which are silicon dangling bonds where silicon is bonded to three other silicon

366

RF CMOS Reliability

atoms, Si3=Si-, and the other three silicon atoms are in the substrate. is shown in Figure 3.

1253

This interface traps

oxide / 1 x.

—Si

substrate

P SiSi

I

Fig. 3. Atomic structures of defects at silicon-silicon dioxide interface.

In the following section, some of the different mechanisms by which hot carriers can damage the device are explained in more detail.

2.1. Channel hot-electrons (CHE) As mentioned before, one of the damages caused by hot carriers is trapped charges in the gate oxide. These charges are carriers in the channel, which on their way from source to drain gain high enough energy so that they can overcome gate oxide potential barrier 4>6 and penetrate into the gate oxide. The event of a carrier gaining energy and entering the gate oxide is a statistical phenomenon. A model called lucky-electron model, has been developed.17 This model takes into account several probability factors in order to calculate the gate current Ig which is representative of hot carriers entering the gate oxide.'7 According to this model, as carriers are accelerated by the lateral electric field in the channel, their move is hindered by scattering caused by the lattice. Some types of scattering called optical phonon and impact ionization scattering cause the carriers to loose their energy and are called inelastic scattering. The probability of a carrier traveling a distance d without experiencing any energy robbing scattering is exp(-dfk) in which X is called the scattering effective mean free path. Some other types of scattering called acoustical phonon scattering, do not cause the carriers to loose their energy significantly. The acoustical phonon scattering, also called elastic scattering, only causes redirection of carriers. Similar to inelastic scattering, a parameter Xr is defined as the redirecting scattering mean free path, and the probability of a carrier redirection over the differential distance dx is dx/ Xr In the redirection process carriers can isotropicly be redirected to all directions and part of them will be directed toward the silicon-silicon dioxide interface. Again, for carriers directed toward the interface, there is a probability involved that some of them reach the interface without any energy robbing scattering. Finally, the probability for carriers which have entered the gate oxide to reach the gate terminal is P(E0X) in which Eox is the electric field inside the oxide. Since the events involved for a carrier to reach the gate terminal are independent from each other, the over-

367

1254 S. Naseh & M. J. Deen

all probability for one carrier reaching the gate terminal is the product of probabilities of each single event. The final result of this analysis can be expressed as:

/ „

=

/

1 * * ( ox>r J/** p E

d]

(3)

dx

b

0

r

in which P^b is the probability of a carrier gaining energy higher than b and retaining its momentum when it reaches the interface and is a function of electric field in the channel, L 11

is the channel length, Id is the drain current and / is the gate current. graphical exhibition of channel hot electron mechanism.

Figure 4 shows a

v„ VH

JTX

^

p substrate

drain

Fig. 4. Channel hot electron generation. The dashed line shows the border between depletion region and neutral bulk.

-9

io r -10 10

10

a

3>

io

10

10

0

J 2

L 4

6 V

8

J 10

c>V

Fig. 5. Measured gate current versus gate voltage (from reference 18).

368

L 12

RF CMOS Reliability 1255 Experimental verification of this model has been reported and shows good agreement with measurement.17 The gate current /„ can be an indicator for the amount of charge trapped inside the gate oxide. A sample measurement of/„ versus gate voltage V„ for constant Vds is shown in Figure 5. The shape of the Ig versus Vds can be qualitatively explained as follows. At low values of V the transistor is in deep saturation which means there is a pinch-off region formed near drain where a high lateral electric field is present. But at low values of Vg, the electric field in the oxide near drain is in a direction which inhibits collection of carriers. As Vg increases, the vertical electric field in the gate oxide near drain becomes favorable for collection of carriers, but at the same time transistor moves toward the linear region from the pinch-off region, and therefore the lateral electric field in the pinch-off region gradually disappears. Since variation of lateral and vertical electric fields are opposite to each other there is a point where Ig has a maximum. The value of Vg at which this maximum happens

is V^Vfr As mentioned in the introduction, however, there have been observations of hot carrier effects even when power supply is low enough so that qVdd is less than both threshold energy for impact ionization and Si-Si0 2 barrier height.7'8 This is not possible according to the simple lucky electron model explained above. Therefore a new model was introduced which assumes that electrons are in quasithermal equilibrium with the electric field and therefore energy distribution of electrons follows the Fermi-Dirac statistics.19 This energy distribution can be approximated by Maxwell-Boltzmann distribution as in the case of hot carriers we are mostly interested in the high energy region of the distribution. According to these energy distributions, there is a certain probability that the electron may gain any energy. Therefore it is possible that electrons have energies above the impact ionization threshold energy or Si-SiC>2 barrier height. The improvement provided by quasithermal equilibrium approach has been incorporated into the lucky electron model.20

2.2. Drain avalanche hot-carriers (DAHC) Another effect that can be caused by energetic carriers in the channel is that carriers on their way toward drain collide with the lattice atoms and generate new electron and hole pairs. These electron and hole pairs can also gain high energy in the electric field and produce new electron-hole pairs, similar to avalanche process in a reversed biased p-n junction. This process is shown in Figure 1 b in the avalanche plasma. During the same process, the energetic carriers can impinge on the atomic bonds at the interface of the substrate and gate oxide or inside the oxide, and break them, thus creating dangling bonds. As a result, new electronic states Nit are created at the interface and these Nit can affect the electrical performance of the device.18

369

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S. Naseh. & M. J. Deen

In a NMOS transistor, the extra electrons which are generated by the avalanche process are absorbed by drain, and the generated holes are absorbed by substrate terminal which form the substrate current component Isub. Typical measurement results of Isub versus Vg at various Vjs a NMOS transistor are shown in Figure 6.

0.30

0.40

0.50

0.60

0.70

v g oo Fig. 6. Measured substrate current versus gate voltage.

As is shown in Figure 6, the variation ofIsub versus V„ for a constant V^s has a maximum. The explanation is as follows. It is known that generation of electron-hole pairs in an avalanche process is proportional to both strength of electric field and the number of primary carriers initially flowing in the channel, that is, carriers which originally flow in the channel and generate new electron-hole pairs by colliding with the lattice atoms. For low values of Vg above threshold, the transistor is in deep saturation and a pinch-off region is formed near the drain which results in a strong lateral electric field in that region. Also, at low values of V the drain current Id is low. As V increases Ij increases but transistor comes out of saturation region gradually. In other words, the variations of the number of primary carriers and the strength of the electric field in the channel with respect to Vg are opposite to each other. This causes that a maximum value for Isub appears at some particular value of Vg It has been observed that this maximum usually happens at about Vg=VJ2. It is reported that the biasing condition which causes maximum Isub is where maximum damage is generated in NMOSFETs.18

370

RF CMOS Reliability

1257

2.3. Substrate hot electrons (SHE) Unlike the cases of CHE and DAHC, which were caused by lateral electric field in channel, SHE are caused by the vertical electric field between gate and substrate. The electrons which are thermally generated in the region below the gate, drift toward the silicon-silicon dioxide interface and gain kinetic energy in the electric field below the gate.

^

^

^_^^ i _ ^ _ _ _ ^ _ ^

p substrate

-* v d

!_?^__

drain

Fig. 7. Substrate hot electron generation.

This is shown in Figure 7. Some of these electrons penetrate into oxide and cause a uniform distribution of trapped charge in the oxide. SHE is not a major problem in short channel devices as most of the electrons are absorbed into source and drain region and a smaller fraction them reaches the device surface, compared to the long channel devices.

2.4. Fowler-Nordheim tunneling (F-N) A mechanism by which electrons can be injected into the gate oxide is tunneling. If a strong electric field is applied between metal plate (gate in a MOSFET), and bulk or substrate of a MOS structure so that direction of electric field is in favor of attracting electrons from bulk toward the gate, electrons may tunnel from the conduction band of the silicon to the conduction band of the silicon dioxide. This mechanism of tunneling is called Fowler-Nordheim tunneling (F-N). The comparison of F-N tunneling and direct tunneling is shown in Figure 8. The current density between gate and substrate is shown both experimentally21 and theoretically to be in the following form: A

-B/E

J = Ks

(4)

in which constants A and B depend on the electron's effective mass and the potential barrier height at silicon-silicon dioxide interface, and Eox is the electric field in the gate oxide.

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This current is shown to cause degradation of the gate oxide and eventually its breakdown.22 Fowler-Nordheim tunneling

Metal

Si02

direct tunneling

Si

Metal

Si02

Fig. 8. Comparison of Fowler-Nordheim tunneling and direct tunneling.

In MOS transistors, as the gate oxide becomes thinner, F-N tunneling can be important. Unlike CHE and DAHC mechanisms which were caused by the lateral electric field in the channel, F-N tunneling is caused by the vertical electric field between the gate and the channel. Therefore, if a large voltage is applied to the gate, this mechanism of current can be important especially near the source which the highest electric field between gate and substrate exists.

2.5. Hot carrier degradation

ofMOSFETs

Different opinions has been suggested about the mechanism of device degradation as result of hot carriers. In some researches, only trapped charges are considered as the source of device degradation.10'11'23'24'25 In some others, interface trap generation is considered as the reason for device degradation. 13 ' 18 ' 26 ' 27 ' 28,29 ' 30 ' 31 ' 32 ' 33 ' 34 There are as well reports where both kinds of damages are considered to be involved in device degradation.35'36'37 Although the idea that only electron injection being responsible for NMOSFET degradation has been reported,27'28 in most of the researches, it has been proposed that hot holes as well as hot electrons are involved in the process of interface states generation at the silicon-silicon dioxide interface.13'29'30'38 It is observed that the maximum interface state generation in NMOSFETs coincides with the maximum Isub condition, and in PMOSFETs the maximum interface traps generation happens at the condition V^Vj which coincides with maximum hot hole injection into the gate oxide.29 This observation confirms that hot holes are important in interface state generation.

372

RF CMOS Reliability

1259

2.6. Lightly doped drain MOSFETs In order to reduce the hot-carrier effect in the MOS transistors, the doping profile of the drain and source are modified in a way that electric field in the pinch off region is reduced. By introducing a narrow, lightly doped n-type region between the channel and the n+ drain and n+ source diffusion regions the so called Lightly Doped Drain (LDD) MOSFET is created. In this structure the high electric field in the drain pinch off region is reduced by spreading it into the n- region, similar to spreading of electric field in a lightly doped p-n junction. Therefore, it is possible to have shorter channel length with the same Vds voltage, or use higher power supply voltages, without having too high electric field in the pinch off region. This structure is shown in Figure 9. t

gate

n+ LDD regions p substrate

Fig. 9. LDD MOSFET structure.

As a result of reduction of electric field, the impact ionization is reduced in LDD MOSFETs compared to the conventional MOS transistor structure. For the same reason, avalanche breakdown also happens at higher Vds voltages. The LDD structure also provides an improvement in the punchthrough voltage of the device, and alleviates the fall off in the threshold voltage due to short channel effects. On the other hand, the introduction of the lightly doped region adds to the ohmic resistance in series with drain and source, but this effect is not seriously affecting the device performance.39

3. Experimental Tools for Hot Carrier Damage Detection For the purpose of studying effects of hot carriers on MOS transistors, experimental tools are required to investigate the damage caused by hot carriers. One of the important experimental technique used in the study of the hot carrier damage in MOS transistors is the charge pumping measurement. Charge pumping is a powerful technique applied to a MOS transistor which is used for determining the interface traps distribution in the energy band gap and also their spatial profile in the channel. Two other types of measurements, C-V measurement and floating-gate measurement, will also be discussed briefly. C-V measurement, a technique for investigation of the sili-

373

1260


con-silicon dioxide interface quality in MOS capacitor, can also be used to study the effect of hot-carriers on the MOSFETs by measuring the device parasitic capacitors Cgd and Cgs. Floating-gate measurement is a technique by which the gate current is measured and it is possible to distinguish whether it is caused by hole injection or electron injection.

3.1. Charge pumping method Charge pumping technique as a mean to study the interface traps at the interface of the silicon substrate and gate oxide of a MOSFET was reported for the first time by the authors of.40 The experimental setup and circuit connection for charge pumping experiment is shown in Figure 10.

pulse generator

JL /\

/\

V

ISL.

^

£J

p substrate

XT ^reverse

DC AMMETER

Fig. 10. Charge pumping measurement setup.

In this experiment, the drain and the source of the MOS transistor are connected together and a reverse voltage is applied between drain/source and substrate terminals. A pulse generator applies voltage pulses between the gate and the substrate in a way that it switches the surface underneath the gate between inversion and accumulation. During inversion, a layer of charge made of substrate minority carriers appear underneath the gate. These charges mainly originate from the source and drain diffusion regions. Some of these carriers fill the fast electronic states at the interface of the substrate and the gate oxide. When the gate voltage changes so that surface underneath the gate returns into the accumulation state, the free minority carriers which form the inversion layer return to the source and drain diffusion regions. The charges trapped in the interface states recombine with the substrate majority charges. Also, a small fraction of the free carriers in the inversion layer may recombine with the majority charges of the substrate too. These two com-

374

RF CMOS Reliability

1261

ponents are called interface trap component and geometric component, respectively, and together, they form a current which flows from substrate to the drain and the source. Therefore, this current, which is called charge pumping current, can be written as: 40 hp=MGWit-aC0X(Vgh-Vth))

(5)

in which: / =charge pumping current, / = frequency of the applied gate pulse, AG = gate area, q = electron charge Nit = fast interface states density, a = fraction of free carriers under gate which recombine with substrate majority carriers, Cox = gate oxide capacitance per unit area, Vgh = gate voltage during the inversion and, Vth - threshold voltage. Usually the waveform of the pulse applied to the gate is chosen in a way that the free carriers have enough time to return to the source and drain, and therefore geometric component of the charge pumping current is small compared to the interface trap component. Therefore, / can be a measure of the density of the fast interface traps under the gate. This forms the basis of the charge pumping technique for studying the interface traps in MOS transistors. In interpreting the result of charge pumping experiment, it is important to consider the kinetics of the charging and discharging of the interface traps.41 Therefore, in the following section, the capture and emission processes are briefly explained. Interface traps can be acceptor type or donor type. Acceptor traps are the traps which are either in neutral state or negatively charged, and donor traps are traps which can be either in neutral state or positively charged. A trap can charge or discharge through both emission and capture processes at the same time. For example, a neutral acceptor trap can capture an electron or emit a hole, i. e., receive an electron from the valence band and it becomes negatively charged. A negatively charged acceptor state can emit an electron or capture a hole, i. e., send an electron to the valence band, and it becomes neutral. The probability per unit time that an interface state can emit (e„ ) or capture (c ) a charge using the Shockley-Read-Hall model is: 42 ' 43 C

n

=

a v

(6>

*n

=

a v

n thnl>

(?)

a V

p ,hPs

(8)

% = apvthPi

(9)

c

p

=

n thns'

and:

375

1262


in which o~n and a p are the capture cross section of electrons and holes, respectively; v^, is the thermal velocity of the carriers; given by: vth = (3kT/m*)W2

(10)

in which m* is the effective mass of carrier, and ns andps are the density of electrons and holes at the surface; and: -{E'-E-)/kT . ( * , - * • > / « •

(11) (

i

2

)

in which nt is the intrinsic density of electrons, E{ is the intrinsic Fermi energy and E, is the energy of the trap in the band gap. ny is the electron concentration in the conduction band and p] is the hole concentration in the valence band that would exist, if the trap energy E, coincided with the Fermi energy EF, and the Boltzmann approximation of the Fermi function is used. If an is much larger than crp, then the trap has a much higher tendency to capture electrons than to capture holes. These sort of traps are considered as electron traps. If o n is much smaller than o p , then the trap is considered as a hole trap, and if 0 n and d p are comparable to each other, then the trap is called generation-recombination center. Using the expressions (6) to (9), it can be shown that if the surface conditions are suddenly changed so that interface states change their charge state, the transition from neutral to negatively charged states occurs exponentially with the time constant:

and the time constant for the transition from the negative state to neutral state will be: t = l/(c„ + e n ).

(14)

in which traps are considered as acceptor type. In the charge pumping experiment, if Ton and T0jr defined as the length of time gate that voltage is kept at V h and Vgi, respectively, are sufficiently long, then the interface traps will reach to an equilibrium with the free carriers in the channel. Also, if rise time Tr and fall time Tf of the pulse applied to the gate are short enough, the interface traps will not have time to emit any charge. In this case, the charging and discharging of traps are done by capture of electrons in inversion and capture of holes in accumulation, respectively. However, if the rise time of the gate voltage is not short, then the interface traps may emit holes during the rise time. The traps which charge this way will not be able to capture electrons as the inversion layer forms in the channel, and therefore they do not contribute to the charge pumping current. In order to simplify the analysis, it may be assumed that free carriers in the channel are in equilibrium with the gate voltage, that is, free electrons

376

RF CMOS Reliability 1263 and holes in the channel are only a function of gate voltage and independent of time. But the interface states are not in equilibrium with the free carriers in the channel and their charge exchange process has the time constants explained before. As the gate voltage varies, when it is slightly above the flat band voltage, it can be assumed that the hole emission process is dominating, and as gate voltages increasingly becomes closer to the threshold voltage, then electron capture becomes dominant. It can be assumed that the interface traps below a certain level Eemh which have a short time constant are negatively charged by emitting holes, and therefore, they do not contribute in the charge pumping. Therefore Eemh sets a lower limit for the energy levels which can be covered in the charge pumping process. During the fall time, as the gate voltage becomes less than the threshold voltage the inversion channel gradually disappears. The interface traps which emit electron before the channel has disappeared will not contribute to the charge pumping current as these charges are collected by the drain and the source terminals. But the interface traps which emit their electrons after the channel has disappeared will contribute to the charge pumping because the emitted electrons recombine with the majority carriers (holes) in the substrate. Similar to the rise time, an energy level can be assumed above which the electron emission time constant is so short that they emit electrons before the inversion layer disappears, and therefore, they do not contribute in the charge pumping current. This sets an upper limit for the energy level which contribute to the charge pumping current. A similar analysis can be performed for the case of donor traps at interface. The charge emission and capture by interface traps which was explained need to be considered in order to be able to consistently explain the observations in charge pumping measurements. The basic experimental setup which now is used for charge pumping measurement has stayed the same. But different schemes for applying the gate voltage have been suggested by different groups in order to improve the measurement. 4 In one class of charge pumping experiments known as variable amplitude mode, the base level voltage applied to the gate, Vgi, is kept constant and the high value of the voltage pulse, Vgh, is increased gradually. In the case of NMOSFET, Vgj value is chosen below flat-band voltage Vpg so that channel is in accumulation. By gradually increasing the amplitude of the pulse, so that Vgh becomes greater than the flat-band voltage, the transistor moves into depletion and as Vgh increases to values above threshold voltage, the channel goes into inversion. A typical charge pumping current versus Vgh is shown in Figure 11. The regions 1, 2 and 3 specified on the plot correspond to values of VghVth, the value of the capacitance again becomes the same as oxide capacitance Cox. In the above explanation, it was assumed that no interface traps were present. If they are present, then they will charge and discharge as the surface potential changes due to the change in Vg. Therefore, they act as a capacitor Cit parallel to the depletion layer capacitor So far, the variation of gate voltage V„ was considered to be slow enough so that the charge in the inversion layer was able to follow its variation. The charges in the inversion layer are supplied by the diffusion of the minority carriers, electrons, in the substrate and the thermal generation of electron and hole pairs in the substrate.12 These two process have a limited rate, and if the variation of Vg is fast, then the inversion layer may not be able to follow V„. In this condition, the depletion layer charge changes in response to the variation of the gate voltage. If the variation of the Vg is fast enough, then the interface traps will not respond to Vg either, and the total capacitance will be the series of the oxide capacitance and depletion layer capacitance. Therefore, by measuring the low frequency capacitance C^-and high frequency capacitance Qy, it is possible to obtain the capacitance due to interface traps Cit:52

(i/clf-i/coxrl-(i/chf-\/cox)-1

cit =

(16)

Cit is a function of surface potential \|/s, and therefore gate voltage. The relation between Cit and the interface trap density Nit is: ctM

(1?)

= ^««P,)

in which \|/s=f]

(36)

i= l

The coefficient C], c2 and c} can be written as:

c

=J.ay

ia

V*HaV

e

* '-L4a>yip-T?>y5p-%aSp--

(38) (39)

When K^ is small enough, the coefficients c;, c2 and c^ will be equal to the first terms in the above relations. In many applications, because of the symmetry in the circuits, the even harmonics are cancelled out and only odd harmonics are left. At this point, the criteria for linearity can be defined as the extrapolated value of Vp at which amplitude of the first and third harmonics would be equal.80 This value is obtained by equating the first terms of series expansions of c} and c3 shown above. Solving this equation, the value of Vp which is called input referred third order intercept voltage and denoted by Vip3 will be: 24g„ A/ Sm3 According to this definition, the higher the Vip3 value, the higher is the linearity of the device. Having defined a figure of merit for device linearity, this value is measured for one device before and after hot-carrier stress and is shown in Figure 29. The parameter which has major effect on the linearity of the device is its carrier mobility m, in NMOSFETs, and effect of hot-carrier stress on linearity is believed to be mostly because of its effect on u^.

395

1282


10 3

L=0.3nmW=120nm stress at: Vd=3.7 V, Vg=0.65 V

10 =

2000 s stress i

10 1

10c

: J

/ "

/

I

I

fi\

s^''

s?

V I .2 V

jr^

10 0.20

1

0.40

0.60

0.80

1.00

V g s (V) Fig. 29. Comparison of third intercept point before and after hot-carrier stress for the stress condition shown.

5. Hot Carrier Effects on the Performance of NMOSFET LNA In the previous sections, the effects of hot carrier stress on the characteristics of a single NMOSFET were explained. Obviously, when these effects appear in the devices used in a circuit, it is expected that the performance of the circuit will be affected as well. As the MOSFET channel length is decreased further, they become more suitable for RF circuits like low noise amplifiers (LNA), oscillators and mixers. Therefore, it is important to know

0.7 V

1.5 V

0.7 V

1.5 V

Ld=7nH L g =8.3 nH Ls=2nH Rb=10KQ C c =40pF L=0.3 um, W=120 urn Fig. 30. Schematic of LNA used for investigating the effect of hot carrier stress o LNA performance.

396

RF CMOS Reliability 1283

how the performance of the RF circuits made of NMOSFET will be affected by hot carrier stress. For this purpose, a test circuit will be considered and the variation of its parameters as a result of hot carriers are studied. In the following, hot carrier effects on a typical LNA are investigated.

5.1. Effect of hot carriers on LNA performance In Figure 30, the schematic of a two stage LNA made of NMOSFETs and its biasing voltages are shown. Each of the two stages in the circuit are in a common source configuration with inductors Lj as the load. In the first stage, the inductor L s is inserted in the source of the transistor M] in order to provide matching at the input of the amplifier. Matching at the input is the condition that signal source impedance is conjugate of the input impedance of the amplifier. At this condition, the maximum power transfer from the signal source to the amplifier occur. The use of an inductor in the source of a MOS transistor for matching purposes is called inductive source degeneration. To qualitatively understand how this technique can be used in matching of the amplifier's input, the simplified small signal model for MOSFET shown in Figure 31 is used to calculate the input impedance of the amplifier. G

•-

4

-•D £m

Fig. 31. Simplified small signal model of a MOSFET.

Using this model and assuming that the resistor Rb in Figure 30 is large enough that does not affect the input impedance, then the following can be written:81'82

* ' > 7T + cLL'

sL + L +

S

^gs

(41)

^gs

It is seen that by choosing the value of Ls properly, the real component of the input impedance can be adjusted to the desirable value. Also, the imaginary component of the input impedance disappears at the frequency at which the reactances of s(Lg+LJ and 1/ sCgs cancel each other. The inductor Lg at the gate of Ml provides a degree of freedom in determining the frequency at which input impedance becomes purely real, and by adjust-

397

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5. Naseh & M. J. Deen

ing its value, this frequency can be adjusted. Capacitors Cc are coupling capacitors and their values are large enough that at the frequency of interest, they will have a small impedance. It should be emphasized that in real circuits and devices, the presence of gateto-drain capacitor Cgcj and drain-source resistor Rds means that the load at the drain of the transistor Mj also affects the input impedance of the amplifier. However, simulation of the input impedance, using the small signal model of Figure 25, shows that essence of the inductive source degeneration technique for amplifier's input matching is still valid and by choosing a proper value for Ls, it is possible to satisfy the matching conditions. The feasibility and performance of the circuit in Figure 30 for RF signal amplification has already been confirmed and reported by measurement on a similar circuit. In order to analyze the performance of the circuit, the operating point of each transistor and their small signal model at those operating point should be known. The biasing current of each transistor for the biasing voltages shown in Figure 30 before hot carrier stress is obtained from the previously measured DC characteristics of the transistors and is 3 mA.

D 0.005 0.003 0.001 -0.001 -0.003

2

4

6

1

8

10

8

10

-

-0.005 I

:

8

0.05 0.04 0.03 0.02 0.01 0.00

0.002 0.000 0

2

4

6

8

0

10

Frequncy (GHz)

2 4 6 8 Frequency (GHz)

10

Fig. 32. Comparison of the Y-parameters of the small signal model (dashed line) and measurement (square symbols). The squares almost completely overlap the dashed lines, and this indicates good agreement between model and measurements.

398

RF CMOS Reliability

1285

The parameters of the small signal model of the transistors at this biasing point are extracted from their S-parameter measurement using the procedures similar to that of. In order to make sure that the extracted small signal model is valid, a comparison of the Yparameters calculated from the small signal model and the Y-parameters derived from measured S-parameters of the transistors before hot-carrier stress are shown in Figure 32. In these plots model parameters are shown by dashed line and measurements by squares. There is a good agreement between the model and measurement and therefore the graphs almost completely overlap and cannot be distinguished from each other. To investigate the effect of hot-carrier on the performance of this amplifier, it can be assumed that both transistors Mj and M2 follow the same degradation pattern, as both of them are biased at the same operating point. By setting both the input source impedance Zs and load impedance RL equal to 50 Q, as happens in many practical cases,83 the voltage variation at the drain of the transistors M[, assuming a 1 mV p-p signal at the amplifier's input, can be shown by simulation to be about 30 mV p-p. Almost the same amount of variation appears at the gate and drain voltage of M2. This level of variation compared to the gate and drain biasing voltages of the transistors are very small and negligible. Therefore, the DC bias voltages across the transistors can be used to determine what mode of hot carrier stress (e. g., CHE, DAHC, etc.) exists in the transistors. For the biasing voltages shown in Figure 30, the DAHC mechanism is dominant. Therefore, the accelerated aging condition specified in Figure 16 is used to do the analysis. It can further be assumed that all the other elements and biasing voltages in the circuit are not affected by the hot carrier stress. Therefore, for the purpose of this investigation, it is enough to replace each of the MOS transistors in the circuit with their small signal model before and after stress. The inductors in the circuit are considered on chip inductors and in the simulation, the inductors are replaced with their 7t-model equivalent circuit obtained from S-parameter measurement of the real spiral inductors which had been fabricated with the same technology. It is assumed that Rb and C c can be modeled by a single resistor and capacitor, respectively. It should be mentioned that since after hot carrier stress, the I-V characteristics of the device changes, then the biasing current of the transistors change to 2 mA for the biasing voltages shown in Figure 30. The small signal model used for the transistors in the simulation are extracted at the new operating point. One important issue in the LNA is the matching at the input of the circuit. The reflection coefficient at the input of the amplifier defined as: Z

-Z

r .in = - ^ — i

(42)

z. +z in

s

and it can be a considered as the criteria for measurement of mismatch at amplifier's input. Zs is the signal source impedance. In Figure 33, the magnitude of r / n versus frequency is

399

1286


0.3 before stress after stress

^ °

2

I 0.1

0.0 2.00

J

I

I

I

L

2.05

2.10

2.15

2.20

2.25

2.30

Frequency (GHz) Fig. 33. Reflection coefficient of the input of the LNA before and after hot carrier stress. Stress condition: Vg = 0.65 V and Vd = 3.7 V.

plotted. It is assumed that both the signal source and the load impedances are 50 Q . It is clearly seen that after the hot carrier stress the matching at the LNA's input is disturbed. There are two points which need to be explained. First, it was observed that the value of the load connected to the output of the amplifier affects the value of the input impedance of the amplifier. This means that the NMOSFETs used in the circuit are not unilateral devices. By considering the small-signal model of the transistors, it can be stated that the gate-to-drain capacitor Cg(j, which has an impedance less than 2 kQ at 2 GHz, provides a path between output and input of each transistor. Also, the output resistance of the MOSFETs Rfc provides another connection between output and input of the device. This is to be expected as device channel length becomes shorter, which causes a more pronounced channel length modulation effect. This is especially important in the design of the first stage of the LNA where the presence of the inductor at the transistor's source provides feedback from the output to the input. This importance can be further confirmed by the trend of variation of input impedance versus frequency, before and after stress. As mentioned before, the gate-to-source capacitor Cgs increases with stress, which then may raise the expectation that the frequency at which input impedance of LNA, Zin, becomes a pure real resistance would shift to lower frequencies after hot-carrier stress. The result of simulations show the opposite trend. In fact, it can be shown by simulation that both the decrease in gm and the decrease in Rjs shift the minimum r i n to higher frequencies. Therefore, the effects of degradation of gm and Rds on the input impedance is more prominent than that of the degradation of C„s due to hot carrier stress.

400

RF CMOS Reliability

1287

The second point is that care should be taken in the use of r,-„ as a measure of mismatch. If the signal source impedance Zs has an imaginary part other than zero, a reflection coefficient r,„= 0 does not correspond to the conjugate matching of the signal source and LNA, which is the desirable condition at LNA's input. Another important parameter of the LNA is its power gain. The transducer power gain GT is defined as the ratio of the power dissipated in the load to the power available from the source, before and after stress, and it is shown in Figure 34. Clearly, this parameter has also decreased after stress and it shows a shift in frequency similar to that of the input reflection coefficient. The drop in the power gain is due to both the increase in input mismatch and the decrease in the overall voltage gain of each transistor. 25 CO •o

(9

I

20

-

15

-

after stress

/

10

/'"\\

/

1

/ i

i

3

4

1

1

2

2

3

\

4

Frequency (GHz) Fig. 34. Transducer power gain before and after stress. Stress condition: Vg = 0.65 V and ^ = 3 . 7 V .

Another important parameter of the amplifier is its stability. The parameter u has been shown to be an appropriate measure of two-port networks stability:84 1-IS,

(43)

Is^-iSj^l + |s12s21| in which: A

^ l 1^22 ~ ^ 1 2 ^ 2 1 '

(44)

If the value of \i is more than 1, then the two-port network is unconditionally stable, and also a higher value of [i indicates a more stable two-port. From Figure 35, it is seen that before stress the LNA has conditional stability but after stress it becomes uncondi-

401

1288


tionally stable. This probably can be attributed to the decrease in the gain of the LNA, as generally, higher gain is associated with lower stability. 1.80 1.60

§

1.40

2

1.20

S 1.00

0.80 1

2

3

4

Frequency (GHz) Fig. 35. Stability factor \i versus frequency before and after stress. Stress condition Vg = 0.65 V and Vd = 3.7 V.

6. Summary In this chapter, the effects of hot carrier stress on the NMOSFETs parameters and its electrical performance were presented. First, the operating mechanisms of a MOSFET was described. Using these mechanisms, it was shown that because of presence of strong electric fields, e. g., as in pinch-off region when device is operating in saturation mode, hot carriers are generated. Different mechanism of hot-carrier generation like channel hot electron (CHE), drain avalanche hot carriers (DAHC), substrate hot electrons (SHE) and Fowler-Nordheim tunneling were explained. Important experimental tools, such as charge pumping and C-V measurement which are used for studying the silicon-silicon dioxide interface in MOSFETs and MOS capacitors, and floating gate measurement which is used to measure the gate leakage current in MOSFETs were explained. The results of measurements of hot-carrier effects on the RF and DC electrical parameters and characteristics of NMOSFETS were presented using the accelerated aging process. Degradation of parameters like transconductance gm, threshold voltage Vth, output conductance gds and transit frequency fT of an NMOS transistor were demonstrated. It was shown that drop in transit frequency is caused by the decrease of gm and the increase of

402


And finally, using the results of measurements of hot-carrier effects on NMOSFETs, the effects of hot carriers on the performance of a LNA made of NMOS transistor were simulated. It was shown that matching at the input of the LNA is disturbed by hot carriers. The gain of the amplifier drops and also the frequency of the maximum gain is shifted due to hot carriers. And as a result of drop in amplifier's gain, its stability increases.

Acknowledgements We thank Dr. D. Landheer, National Research Council, Ottawa and Dr. N.R. Das, McMaster University, Hamilton, for their careful review of parts of this manuscript. We are also grateful to several of our current and previous colleagues for their interest and support, and for their comments and useful suggestions on our work over the past several years. Finally, we are grateful to the Natural Sciences and Engineering Research Council (NSERC) of Canada and Micronet, a federal network center of excellence in microelectronics for partial financial support of this work.

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Selected Topics in Electronics and Systems - Vol. 24

CMOS RF MODELING, CHARACTERIZATION AND APPLICATIONS CMOS technology has now reached a state of evolution, in terms of both frequency and noise, where it is becoming a serious contender for radio frequency (RF) applications in the GHz range. Cutoff frequencies of about 50 GHz have been reported for 0.18 urn CMOS technology, and are expected to reach about 100 GHz when the feature size shrinks to 100 nm within a few years. This translates into CMOS circuit operating frequencies well into the GHz range, which covers the frequency range of many of today's popular wireless products, such as cell phones, GPS (Global Positioning System) and Bluetooth. Of course, the great interest in RF CMOS comes from the obvious advantages of CMOS technology in terms of production cost, high-level integration, and the ability to combine digital, analog and RF circuits on the same chip. This book discusses many of the challenges facing the CMOS RF circuit designer in terms of device modeling and characterization, which are crucial issues in circuit simulation and design.

www.worldscientific.com 4921 he

CMOS RF Modeling, Characterization and Applications

Modeling and characterization of RF and microwave power FETs

Device Modeling for Analog and RF CMOS Circuit Design

Device Modeling for Analog and RF CMOS Circuit Design

Ferroelectrics - Characterization and Modeling

Device Modeling for Analog and RF CMOS Circuit Design

Modeling and Characterization of RF and Microwave Power FETs (The Cambridge RF and Microwave Engineering Series)

Integrated Inductors and Transformers: Characterization, Design and Modeling for RF and MM-Wave Applications

HighLinearity CMOS RF FrontEnd Circuits

Design and Characterization of Integrated Varactors for RF Applications

RF CMOS power amplifiers.Theory,design and implementation

Low-Voltage CMOS RF Frequency Synthesizers

Parasitic-Aware Optimization of CMOS RF Circuits

RF MEMS and Their Applications

Cournot Oligopoly: Characterization and Applications

Cournot Oligopoly: Characterization and Applications

CMOS Circuit Design for RF Sensors

High-Linearity CMOS RF Front-End Circuits

Parasitic-Aware Optimization of CMOS RF Circuits

Integrated 60GHz RF Beamforming in CMOS

Starches: Characterization, Properties, and Applications

Starches: Characterization, Properties, and Applications

RF Mems and Their Applications

Palladacycles: Synthesis, Characterization and Applications

Starches: Characterization, Properties, and Applications

Grafting-Characterization Techniques-Kinetic Modeling

High-Linearity CMOS RF Front-End Circuits

Modeling and Simulation for RF System Design

Smart CMOS image sensors and applications

Microwave and RF Product Applications (Principles and Applications in Engineering)

Microwave and RF Product Applications (Principles and Applications in Engineering)

CMOS RF Modeling, Characterization and Applications

Modeling and characterization of RF and microwave power FETs

Device Modeling for Analog and RF CMOS Circuit Design

Device Modeling for Analog and RF CMOS Circuit Design

Ferroelectrics - Characterization and Modeling

Device Modeling for Analog and RF CMOS Circuit Design

Modeling and Characterization of RF and Microwave Power FETs (The Cambridge RF and Microwave Engineering Series)

Integrated Inductors and Transformers: Characterization, Design and Modeling for RF and MM-Wave Applications

HighLinearity CMOS RF FrontEnd Circuits

Design and Characterization of Integrated Varactors for RF Applications

RF CMOS power amplifiers.Theory,design and implementation

Low-Voltage CMOS RF Frequency Synthesizers

Parasitic-Aware Optimization of CMOS RF Circuits

RF MEMS and Their Applications

Cournot Oligopoly: Characterization and Applications

Cournot Oligopoly: Characterization and Applications

CMOS Circuit Design for RF Sensors

High-Linearity CMOS RF Front-End Circuits

Parasitic-Aware Optimization of CMOS RF Circuits

Integrated 60GHz RF Beamforming in CMOS

Starches: Characterization, Properties, and Applications

Starches: Characterization, Properties, and Applications

RF Mems and Their Applications

Palladacycles: Synthesis, Characterization and Applications

Starches: Characterization, Properties, and Applications

Grafting-Characterization Techniques-Kinetic Modeling

High-Linearity CMOS RF Front-End Circuits

Modeling and Simulation for RF System Design

Smart CMOS image sensors and applications

Microwave and RF Product Applications (Principles and Applications in Engineering)

Microwave and RF Product Applications (Principles and Applications in Engineering)

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