BROADBAND OPTO-ELECTRICAL RECEIVERS IN STANDARD CMOS
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BROADBAND OPTO-ELECTRICAL RECEIVERS IN STANDARD CMOS

ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES Consulting Editor: Mohammed Ismail. Ohio State University Titles in Series: BROADBAND OPTO-ELECTRICAL RECEIVERS IN STANDARD CMOS Hermans, Carolien, Steyaert, Michiel ISBN 978-1-4020-6221-6 ANALOG CIRCUIT DESIGN TECHNIQUES AT 0.5V Chatterjee, S., Kinget, P., Tsividis, Y., Pun, K.P. ISBN-10: 0-387-69953-8 IQ CALIBRATION TECHNIQUES FOR CMOS RADIO TRANCEIVERS Chen, Sao-Jie, Hsieh, Yong-Hsiang ISBN-10: 1-4020-5082-8 LOW-FREQUENCY NOISE IN ADVANCED MOS DEVICES Haartman, Martin v., Östling, Mikael ISBN-10: 1-4020-5909-4 THE GM/ID DESIGN METHODOLOGY FOR CMOS ANALOG LOW POWER INTEGRATED CIRCUITS Jespers, Paul G.A. ISBN-10: 0-387-47100-6 PRECISION TEMPERATURE SENSORS IN CMOS TECHNOLOGY Pertijs, Michiel A.P., Huijsing, Johan H. ISBN-10: 1-4020-5257-X CMOS CURRENT-MODE CIRCUITS FOR DATA COMMUNICATIONS Yuan, Fei ISBN: 0-387-29758-8 RF POWER AMPLIFIERS FOR MOBILE COMMUNICATIONS Reynaert, Patrick, Steyaert, Michiel ISBN: 1-4020-5116-6 IQ CALIBRATION TECHNIQUES FOR CMOS RADIO TRANCEIVERS Chen, Sao-Jie, Hsieh, Yong-Hsiang ISBN: 1-4020-5082-8 ADVANCED DESIGN TECHNIQUES FOR RF POWER AMPLIFIERS Rudiakova, A.N., Krizhanovski, V. ISBN 1-4020-4638-3 CMOS CASCADE SIGMA-DELTA MODULATORS FOR SENSORS AND TELECOM del Río, R., Medeiro, F., Pérez-Verdú, B., de la Rosa, J.M., Rodríguez-Vázquez, A. ISBN 1-4020-4775-4 SIGMA DELTA A/D CONVERSION FOR SIGNAL CONDITIONING Philips, K., van Roermund, A.H.M. Vol. 874, ISBN 1-4020-4679-0 CALIBRATION TECHNIQUES IN NYQUIST A/D CONVERTERS van der Ploeg, H., Nauta, B. Vol. 873, ISBN 1-4020-4634-0 ADAPTIVE TECHNIQUES FOR MIXED SIGNAL SYSTEM ON CHIP Fayed, A., Ismail, M. Vol. 872, ISBN 0-387-32154-3 WIDE-BANDWIDTH HIGH-DYNAMIC RANGE D/A CONVERTERS Doris, Konstantinos, van Roermund, Arthur, Leenaerts, Domine Vol. 871 ISBN: 0-387-30415-0 METHODOLOGY FOR THE DIGITAL CALIBRATION OF ANALOG CIRCUITS AND SYSTEMS: WITH CASE STUDIES Pastre, Marc, Kayal, Maher Vol. 870, ISBN: 1-4020-4252-3 HIGH-SPEED PHOTODIODES IN STANDARD CMOS TECHNOLOGY Radovanovic, Sasa, Annema, Anne-Johan, Nauta, Bram Vol. 869, ISBN: 0-387-28591-1 LOW-POWER LOW-VOLTAGE SIGMA-DELTA MODULATORS IN NANOMETER CMOS Yao, Libin, Steyaert, Michiel, Sansen, Willy Vol. 868, ISBN: 1-4020-4139-X DESIGN OF VERY HIGH-FREQUENCY MULTIRATE SWITCHED-CAPACITOR CIRCUITS U, Seng Pan, Martins, Rui Paulo, Epifânio da Franca, José Vol. 867, ISBN: 0-387-26121-4 DYNAMIC CHARACTERISATION OF ANALOGUE-TO-DIGITAL CONVERTERS Dallet, Dominique; Machado da Silva, José (Eds.) Vol. 860, ISBN: 0-387-25902-3

Broadband Opto-Electrical Receivers in Standard CMOS By

CAROLIEN HERMANS KU Leuven, Belgium

and

MICHIEL STEYAERT KU Leuven, Belgium

A C.I.P. Catalogue record for this book is available from the Library of Congress.

ISBN 978-1-4020-6221-6 (HB) ISBN 978-1-4020-6222-3 (e-book) Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands. www.springer.com

Printed on acid-free paper

All Rights Reserved c 2007 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work.

Preface

The gradual recovery of the optical industry since 2004 has enabled new developments in the communication, consumer and entertainment markets. Lots of new applications are emerging where high volumes and low cost aspects are crucial. To meet these demands, silicon microphotonics aims for the manufacturing of opto-electrical components in the same platform that has enabled Moore’s Law: single-crystal silicon. The presented work ﬁts in this quest for integrated opto-electrical solutions, and focuses on the receiver front-end. To further reduce the cost, the cheapest technology is selected: standard CMOS, without any optical tricks or ﬂavors. Despite the inherent lower optical performance of a mainstream CMOS process, it is shown in theory and practice that light detection is feasible with CMOS diodes. Furthermore, speed enhancement techniques are presented to extend the speed performance above 1 Gbit/s. The three receiver blocks examined in this work are the photodiode (PD), the transimpedance ampliﬁer (TIA) and the limiting ampliﬁer (LA). First, to thoroughly understand the light detection mechanisms in silicon, the basic semiconductor one-dimensional equations are studied. Next, a twodimensional model is developed to compare the performance of diﬀerent types of photodiodes implemented in successive technology generations and for three input wavelengths. Analytical design equations are derived to guide the design of the amplifying circuits. For the TIA, the focus lies on the sensitivity-speed trade-oﬀ. For the LA, a high gain-bandwidth is pursued. Theory is put into practice through several CMOS implementations. A ﬁrst 0.18 µm chip compares diﬀerent photodiode topologies. The diﬀerential diode with TIA has the best high-speed performance and achieves a BER of 3 · 10−10 when a 500 Mbit/s optical signal of −8 dBm is applied. Next, different photodiode topologies manufactured in a 90 nm CMOS technology are compared. The best results are obtained with the p+ n-well diode with guard. This diode with TIA can handle data with bitrates up to 500 Mbit/s and an optical power of −8 dBm, showing a BER of 10−9 . A third chip contains a LA implemented in 0.18 µm CMOS and based on a cascade of Cherryv

vi

Preface

Hooper stages. Eye diagrams at 3.5 Gbit/s illustrate the applied broadband techniques. Finally, all knowledge is gathered in the design of a monolithic optical receiver front-end in 0.18 µm CMOS. This chip contains a diﬀerential CMOS photodiode, a diﬀerential two-stage TIA with cross-coupled feed-back and a high-gain broadband LA. The speed performance of the photodiode is further enhanced by an analog equalizer. The TIA achieves a transimpedancebandwidth product of 19 THzΩ. The LA features a gain-bandwidth product of 397 GHz. At 6 Gbit/s, the LA with output buﬀer has a BER of 10−12 when 8 mVpp is applied at the input. The complete receiver is characterized by a BER smaller than 10−12 for a −6 dBm optical input signal with a bitrate of 1.7 Gbit/s. This receiver competes with present state-of-the-art and is, to the author’s knowledge, the ﬁrst CMOS Gbit/s opto-electrical receiver integrating PD, TIA and LA on the same die.

Heverlee, March 2007

Carolien Hermans Michiel Steyaert

List of Abbreviations and Symbols

Abbreviations ac AGC BER BiCMOS CD CDR CG CMOS CMU CSD DC DG DMUX DSL DVI DVD DWDM ECL FTTH GaAs GaN GB Ge HD-DVD IC In0.53 Ga0.47 As InP ISI ISSCC

Alternating Current Automatic Gain Control Bit Error Rate Bipolar Complementary Metal Oxide Semiconductor Compact Disc Clock and Data Recovery Common Gate Complementary Metal Oxide Semiconductor Clock Multiplication Unit Capacitive Source Degeneration Direct Current Diﬀraction Grating Demultiplexer Digital Subscriber Loop Digital Video Interface Digital Versatile Disc Dense Wavelength-Division Multiplexing Emitter Coupled Logic Fiber-To-The-Home Gallium Arsenide Gallium Nitride Gigabyte Germanium High Density Digital Versatile Disc Integrated Circuit Indium Gallium Arsenide Indium Phosphide Intersymbol Interference International Solid-State Circuits Conference vii

viii

List of Abbreviations and Symbols

LA LAN LD LED MAN MOS MOST MUX nMOS NA NIC NRZ pMOS prbs PA ParBERT PBS PCS P.M. PMMA P.O. POF PON OEIC POF QWP RGC RZ SAN SDH Si SiO2 SML-detector SNR SOI SONET TAS TIA TIS UI VA VCSEL VUC WAN WDM

Limiting Ampliﬁer Local Area Network Laser Diode Light Emitting Diode Metro(politan) Area Network Metal Oxide Semiconductor Media Oriented System Transport Multiplexer n-channel MOS transistor Numerical Aperture Negative Impedance Converter Non-Return-to-Zero p-channel MOS transistor Pseudorandom Bit Sequence Post-Ampliﬁer Parallel Bit Error Ratio Tester Polarization Beam Splitter Polymer-Clad Silica Phase Margin Polymethyl Methacrylate Percent Overshoot Plastic Optical Fiber Passive Optical Networks Opto-electronic Integrated Circuit Plastic Optical Fiber Quarter-Wave Plate Regulated Cascode Return-to-Zero Storage Area Network Synchronous Digital Hierarchy Silicon Silicon dioxide Spatially Modulated Light detector Signal to Noise Ratio Silicon on Insulator Synchronous Optical Network Transadmittance Stage Transimpedance Ampliﬁer Transimpedance Stage Unite Interval Voltage Ampliﬁer Vertical-Cavity Surface-Emitting laser Voltage-Up-Converter Wide Area Networks Wavelength-Division Multiplexing

List of Abbreviations and Symbols

Symbols A A0 A1st ACH ACSD Adif f Aos AP A AP A,0 BWn BWP A BWT IA BWV A c Cdio Cds Cgs Cin CinT Cnext Cout CoutT Cox di2dio di2Mα di2n,T IA di2Rα 2 dvn,T IA Dn Dp Eg Ep f0dB,GH f3dB f3dB,1st f3dB,P A fd,GH fLF

voltage gain DC voltage gain diﬀerential gain of a single stage of a post-ampliﬁer diﬀerential gain of a Cherry-Hooper stage diﬀerential gain of a voltage ampliﬁer with capacitive source degeneration diﬀerential gain gain of an oﬀset compensation ampliﬁer gain of a post-ampliﬁer mid-band gain of a post-ampliﬁer noise bandwidth 3-dB bandwidth of a post-ampliﬁer 3-dB bandwidth of a TIA 3-dB bandwidth of a voltage ampliﬁer speed of light in vacuum diode junction capacitance drain-source capacitance gate-source capacitance input capacitance total input capacitance input capacitance of the next stage output capacitance total output capacitance oxide capacitance diode shot noise thermal channel noise of transistor Mα power spectral density of the TIA input-referred noise current thermal current noise of transistor Rα power spectral density of the TIA output noise voltage electron diﬀusion constant hole diﬀusion constant bandgap energy photon energy unity-gain frequency of the loop gain 3-dB bandwidth 3-dB bandwidth of a single stage of a post-ampliﬁer 3-dB bandwidth of a post-ampliﬁer dominant pole of the loop gain low-frequency cut-oﬀ

ix

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List of Abbreviations and Symbols

fnd,GH fnd,T IA fT FBW gds gm G Geq Gm,CSD GT IA GBW GHT IA h iin in,rms in,OR in,T IA isens pp Idio Ids Jdrif t Jdif f n Jdif f p Kn Kp L LMCH Lb Lnw Lscr Lsd Mi n n(t) n0 NA ND Nf Ns p p0

non-dominant pole of the loop gain non-dominant pole of TIA unity current gain frequency factor deﬁned by the ratio of BWV A and BWT IA transistor output conductance transistor transconductance light generation term transfer function of the equalizer eﬀective transconductance of an ampliﬁer stage with capacitive source degeneration TIA open-loop gain gain-bandwidth product TIA loop gain Planck’s constant small-signal input current equivalent input-referred rms noise total integrated input-referred optical receiver current noise total integrated input-referred TIA current noise electrical receiver sensitivity diode current drain-source current drift current density electron diﬀusion current density hole diﬀusion current density transconductance parameter for an nMOS transistor transconductance parameter for a pMOS transistor transistor length loop gain of the feedback loop in the modiﬁed Cherry-Hooper stage depth in the substrate where n = n0 depth of the n-well, upper edge of space charge region lower edge of the space charge region depth of the source/drain region, upper edge of the space charge region Miller factor electron concentration noise voltage initial electron concentration acceptor concentration in p-substrate donor concentration in n-well number of ﬁngers in a photodiode topology number of squares in a photodiode topology hole concentration initial hole concentration

List of Abbreviations and Symbols sens Pav Pdiss Pn Popt Px q Q(x) R Rb Rdark Rf Rlight Rout Sout t Tb vn,LA

vn,rms vout vpp Vbi Vds Vgs VDSAT VR VT VT H V0 V1 W x x(t) XN ZBW Zin,0 ZN IC ZT IA ZT IA,0 α αgd γ Si ζ η

optical receiver sensitivity power dissipation probability density function for noise (average) optical power probability density function for the wanted signal elementary charge Q function responsivity of a photodiode bitrate responsivity of the dark junctions feedback resistance responsivity of the illuminated junctions output resistance power spectral density of the output signal time bit period total integrated input-referred limiting ampliﬁer voltage noise rms noise voltage small-signal output voltage peak-to-peak value of the received signal built-in voltage drain-source voltage gate-source voltage saturation voltage of a MOS transistor reverse voltage threshold voltage of a transistor threshold voltage of the decision circuit logic zero level logic one level transistor width depth received signal voltage ratio of Cgs to Cdio transimpedance-bandwidth product DC input impedance impedance of a negative impedance converter TIA transimpedance gain TIA DC transimpedance gain absorption coeﬃcient of light (in Silicon) ratio between Cgd and Cgs excess noise factor Silicon permittivity damping ratio of a second-order system quantum eﬃciency of a photodiode

xi

xii

θ(f ) λ λc μ ν τ τn τp Φ Φ0 ωn ω3dB

List of Abbreviations and Symbols

frequency-dependent phase shift wavelength of light maximum absorbed wavelength mobility frequency of light time constant electron minority carrier lifetime hole minority carrier lifetime light ﬂux initial light ﬂux natural pulsation of a second-order system 3-dB bandwidth of a second-order system

Contents

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

List of Abbreviations and Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 A History of Optical Communication . . . . . . . . . . . . . . . . . . . . . . 1.2 Emerging Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Silicon Opto-Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Outline of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1 4 7 9

2

Optical Receiver Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 The Optical Receiver Front-End . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 A Transceiver for Optical Communication Systems . . . . 2.2.2 A Pickup Unit for Optical Storage Systems . . . . . . . . . . . 2.3 Binary Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Bit Error Rate and Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 Bit Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Intersymbol Interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 Low-Pass Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 High-Pass Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13 13 13 13 15 17 20 20 22 23 23 24 25 26

3

Standard CMOS Photodiodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Principles of Light Detection . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 The Use of Standard CMOS . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Overview of Published Integrated Photodiodes . . . . . . . . . . . . . .

27 27 27 28 31 32

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Contents

3.3.1 BiCMOS Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 SOI Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 CMOS Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 One-Dimensional Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 N-Well P-Substrate Junction . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 P+ N-Well Junction with Guard . . . . . . . . . . . . . . . . . . . . 3.5 Two-Dimensional Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Classical N-Well Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 P+ N-Well Diode with Guard . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 Diﬀerential N-Well Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.4 Inﬂuence of Wavelength . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.5 Inﬂuence of Technology Scaling . . . . . . . . . . . . . . . . . . . . . 3.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

32 34 35 36 37 37 43 46 46 49 51 52 56 58

4

Transimpedance Ampliﬁer Design . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.2 Performance Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3 Design of the Shunt-Shunt Feedback TIA . . . . . . . . . . . . . . . . . . . 63 4.3.1 Transimpedance Gain and Bandwidth . . . . . . . . . . . . . . . . 64 4.3.2 Open-Loop Gain and Loop Gain . . . . . . . . . . . . . . . . . . . . 68 4.3.3 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.4 Literature Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.4.1 Common Source TIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.4.2 Regulated Cascode TIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.4.3 The Latest Trends at ISSCC . . . . . . . . . . . . . . . . . . . . . . . . 80 4.5 Case Studies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.5.1 An Inverter-Based TIA for Test Photodiodes in 0.18 µm CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.5.2 An Inverter-Based TIA for Test Photodiodes in 90 nm CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.5.3 A Diﬀerential Bandwidth-Optimized TIA in 0.18 µm CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5

Post-Ampliﬁer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.2 Performance Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.3 Literature Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.4 Design of a Fully Diﬀerential Broadband LA . . . . . . . . . . . . . . . . 113 5.4.1 Cascaded Gain Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.4.2 Broadband Cherry-Hooper Stage . . . . . . . . . . . . . . . . . . . . 116 5.4.3 Broadband Stage with Capacitive Source Degeneration . 120 5.4.4 Oﬀset Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.5 Case Studies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Contents

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5.5.1 A Four-Stage LA in 0.18 µm CMOS . . . . . . . . . . . . . . . . . 124 5.5.2 A Five-Stage LA with Oﬀset Compensation in 0.18 µm CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6

CMOS Realizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 6.2 Test Photodiodes with TIA in 0.18 µm CMOS . . . . . . . . . . . . . 135 6.2.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 6.2.2 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.3 Test Photodiodes with TIA in 90 nm CMOS . . . . . . . . . . . . . . . . 142 6.3.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.3.2 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 6.4 A 3.5 Gbit/s LA in 0.18 µm CMOS . . . . . . . . . . . . . . . . . . . . . . . 146 6.4.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.4.2 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 6.5 A Gbit/s Monolithic Optical Receiver Front-End in 0.18 µm CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 6.5.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 6.5.2 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

7

Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

1 Introduction

1.1 A History of Optical Communication Light as means of communication is not only used in our sophisticated, technology-driven modern era. Since earlier times, man has depended on light to send messages, mostly in the form of ﬁre. The Greek tragedian Aeschylus portrays in the ‘Oresteia’ trilogy (458 BC) how the news about the fall of Troy was sent by ﬁre signals via an unbroken line of beacon-ﬁres from Asia Minor to Mycenae. A few centuries later, the Greek historian Polybius writes ‘The Histories’ or ‘The Rise of the Roman Empire’, covering the period of 220 BC to 146 BC. In this work, he describes an arrangement by which the whole Greek alphabet could be transmitted by ﬁre signals using a two-digit, ﬁve level code. This communication link allowed the transmission of messages not previously agreed upon. The ﬁrst development of a useful optical telegraph dates from the time of the French Revolution. As France was threatened by inner and outer opponents, a new communication system was necessary. The civilian Claude Chappe, a former priest, invented a mechanical-optical telegraph. It consisted of a column with a movable crosswise beam. This beam also had two movable arms. Each arm had seven positions, and the crosswise beam had four more, permitting a 196-combination code. The arms were from 1 m to 10 m long, black, and counterweighted, moved by only two handles. Lamps mounted on the arms proved unsatisfactory for night use. The equipment stood on rooftops or towers, placed from 12 km to 25 km apart. Each tower had a telescope pointing both up and down the relay line. The ﬁrst telegraph line of this sort was put into operation in 1794. The telegraph line consisted of 22 stations and linked Lille with the capital Paris, a distance of over 240 kilometers. It only took 2 to 6 minutes to transfer a message, riding couriers would have needed 30 hours. Other lines were built, including a line from Paris to Toulon. The system was widely copied by other European states, and was used by Napoleon to coordinate his empire and army. In the middle of the 19th century, the optical telegraph was replaced by the electrical telegraph, patented 1

2

1 Introduction

by Samual Morse in 1837. Major advantage of the latter system was a faster signal transmission. In 1880, Alexander Graham Bell invented the photophone. Bell considered this a greater discovery than his previous invention, the telephone. Bell’s photophone worked by projecting voice through an instrument towards a mirror. Vibrations in the voice caused similar vibrations in the mirror. Bell directed sunlight into the mirror, which captured and projected the mirror’s vibrations. The receiver’s mirror received the light and caused a selenium crystal to vibrate, and the sound would come out on the other end. Although the photophone was successful in allowing conversation over open space at a distance up to 200 m, it had a few drawbacks: it did not work well at night, in the rain, or if someone walked between the signal and the receiver. Eventually, Bell gave up on this idea. These anecdotes illustrate that people always have tried to use light, even in its most primitive form, to deliver some type of information between remote locations. The most important drawback is the dependence on atmospheric conditions, that makes direct optical communication through the air unreliable. The advent of the laser in the early 60’s was an important revolution and boosted the development of optical communication systems. The solution to the atmospheric disturbances was found to be the use of optical waveguides that forces the laser beam to follow a certain path. One of the pioneers in the ﬁeld of ﬁber optics is the Dutch scientist Abraham van Heel. In the beginning of the 50’s, he tried to solve the problem of light loss in ﬁbers by using a cladding material. All earlier ﬁbers developed were bare and lacked any form of cladding, with total internal reﬂection occurring at a glass-air interface. The transparent cladding, with a lower refractive index than the glass or plastic ﬁber, protected the total reﬂection surface from contamination and greatly reduced the crosstalk between ﬁbers. By 1960, glass-clad ﬁbers had an attenuation of about 1000 dB/km, ﬁne for medical imaging, but much too high for communication applications. An important milestone in the history of ﬁber-optic communications is the paper [Kao66], published in 1966 by Charles Kao and George Hockam. They showed that optical ﬁber communication would be feasible if the transmission loss could be reduced to less than 20 dB/km. Moreover, they proved that there was no fundamental mechanism that would prevent this loss from being achieved. Only 4 years later, in 1970, Robert Maurer, Donald Keck and Peter Schultz of Corning Glass Corporation achieved this goal and manufactured the ﬁrst optical ﬁber with an attenuation less than 20 dB/km. By 1980, the attenuation loss was reduced even further, and ﬁrms were experimenting with putting cables under the sea. The ﬁrst international undersea ﬁber-optic link, which linked England with Belgium, was installed in 1986. By the end of 1988, the ﬁrst transatlantic ﬁber-optic cable, connecting the United States with Europe, was a fact. The evolution of long-haul communication systems in summarized in Table 1.1. Every generation is characterized by a considerable increase in bitrate-distance product, the ﬁgure of merit com-

Table 1.1. The ﬁve generations of long-haul ﬁber optical communication systems [Agr97, Gra02]. gen. date ﬁrst

bitrate

distance

bitrate-distance product

λ

150 Mbit/s − km 0.8 µm larger repeater space than electrical communication graded-index ﬁber

1980 45 Mbit/s

10 km

second 1987 1.7 Gbit/s

50 km

85 Gbit/s − km

third 1990 2.5 Gbit/s

70 km

175 Gbit/s − km 1.55 µm

1.3 µm

fourth 1996 5 Gbit/s 11300 km 56.5 Tbit/s − km 1.55 µm 2000 100 Gbit/s 9000 km 900 Tbit/s − km ﬁfth

properties

2002 1.28 Tbit/s 4000 km 5120 Tbit/s − km 1.55 µm

single-mode ﬁber minimum dispersion ﬁber loss < 1 dB/km minimal loss (< 0.2 dB/km) dispersion-shifted ﬁber erbium-doped optical ampliﬁers wavelength-division multiplexing (WDM) solitons distributed Raman ampliﬁcation forward error correction dense wavelength-division multiplexing (DWDM)

4

1 Introduction

monly used for optical communication systems. In the early generations, this capacity increase was mainly due to an improvement of the ﬁber properties (lower dispersion, minimal loss), combined with the development of lasers and detectors operating at longer wavelengths. During the fourth generation, the electrical repeater distance was drastically raised by using erbium-doped ampliﬁers, spaced 60 km to 100 km apart, that regenerate the signal optically. The bitrate on the other hand was increased by using the technique of wavelength-division multiplexing (WDM). The era of terabit communication systems has truly arrived with the ﬁfth generation. Todays’ commercial equipments are capable of sending 2.56 Tbit/s (64x40 Gbit/s channels) data over a distance of up to 1000 km, or 1.28 Tbit/s (128x10 Gbit/s channels) data over a distance of up to 4000 km, without any electrical regeneration. The key technologies to realize this high capacity are solitons, distributed Raman ampliﬁcation, forward error correction and dense WDM [Gra02].

1.2 Emerging Applications As revealed in the previous section, the historical popularity of optical ﬁber communication is mainly due to the need of larger bitrate-distance products in the ﬁeld of long-haul communication systems. This section takes a look at some other opto-electrical domains where interesting movements are going on. Short-Distance Communication Networks Optical ﬁber networks have many advantages over copper networks. Besides the high bitrate-distance product, exploited by long-haul communication networks, optical ﬁbers are insensitive to spurious noise signals and avoid electrical ground loops. However, the ultimate reason to replace copper wires with optical ﬁbers remains a purely economical one: a lower cost. Nowadays, bandwidth demands for short-distance communications are increasing exponentially. As a consequence, the critical point will be reached soon where improving the technology supporting these high-bandwidth applications over copper wires will cost more than accomplishing the same speed over ﬁber. To make short-distance ﬁber communication aﬀordable, the industry has developed low-cost solutions like high-bandwidth multimode ﬁbers and 850 nm transceivers. Eventually, ﬁber optics will ﬁnd its way in local area networks (LANs) and new systems like ﬁber-to-the-home (FTTH) will become viable. Note however that there is a large discrepancy between the US and Asia on the one hand, and Europe on the other hand. While the US and Asia invest heavily in deep-ﬁber deployments and FTTH is already available, almost whole Europe lags behind (a few areas, like the former DDR, are an exception). The crowded and fully-wired European countries prefer to extend the possibilities of copper wires by supporting standards like DSL.

1.2 Emerging Applications

5

In-Car Fiber-Optic Networks Opto-electronic systems also become more and more attractive for communication inside cars [Fre04]. To connect the ever-increasing number of in-car electrical devices, plastic optical ﬁber (POF) is used. The beneﬁts of POFnetworks are: a high operation bandwidth, increased transmission security, low weight, immunity to electromagnetic interference, and ease of handling and installation. Diﬀerent protocols are employed or even still in development. In 1998, an international consortium of car manufacturers and suppliers set up an open standard for infotainment networks, the Media Oriented System Transport (MOST). This bus protocol allows 24.8 Mbit/s communication between for instance the radio, the CD/DVD player, the navigation system, a Bluetooth interface, telephones, games consoles and a voice-recognition system inside a car. But not only navigation and entertainment functions can exploit POF. In 1996, BMW gathered some partners and started the development of ByteFlight. This is a protocol that supports 10 Mbit/s communication between the rapidly growing number of sensors, actuators and electronic control units within cars. Unlike MOST, which employs real-time data transfer, ByteFlight is a deterministic system with fault-tolerant behavior and an information latency of 250 µs. BMW’s Series 7 models implement ByteFlight for control of the car’s air-bag systems, while MOST is employed for the vehicle’s information and entertainment systems. Besides MOST and ByteFlight, new protocols are under development. FlexRay is the standard that will be used in the next-generation drive-bywire systems, where mechanical and hydraulic controls are replaced by ﬁber or electrical controls. It is obvious that total reliability is imperative. IDB-1394 is the automotive version of IEEE-1394 (also known as FireWire). It will enable high-speed transfer of digital information at data rates up to 400 Mbit/s. It is a multimedia system like MOST, whereas ByteFlight and FlexRay are more security-focused. All currently in-car optical data bus systems use basically the same components: poly-methyl methacrylate (PMMA) optical ﬁbers, red (650 nm) emitting LEDs and large area silicon photoreceivers. However, this PMMA POF has one key limitation: it can only be used at temperatures below 85◦ C, while many car manufacturers want ﬁber that is speciﬁed at temperatures of 125◦C. A ﬁber that is capable of working at these high temperatures is polymerclad silica ﬁber (PCS). Another attractive feature of PCS is that it supports wavelengths at 850 nm, so that low-cost vertical-cavity surface-emitting lasers (VCSELs) can be used as transmitters. The major advantage of a laser over a LED is an increase of the power budget in the whole system. PCS ﬁbers not only have a low attenuation at 850 nm, but also at 650 nm and thus remain compatible with the standard POF transceivers.

6

1 Introduction

High-Speed Optical Interconnects If Moore’s Law [Moo65] holds true and the processing speed continues to double every 18 months, it is almost certain that a PC built in 2015 will require some form of internal optical data-bus to wire up its diﬀerent chip-sets. Over the next decade, the bandwidth of interconnects inside a computer is expected to increase by an order of magnitude, from 1 GHz to 10 GHz. Ultimately, the chip will be able to work at much higher data rates than todays’ interconnections can handle. An obvious solution would be to use optical interconnections to alleviate the electrical limitations. The major advantage of this approach is that an optical link supports much higher data rates than its electrical counterpart, and continues to do so for far greater distances. History will repeat itself, as the switch has been made in long-haul communication systems (Section 1.1) more than 20 years ago for the same reason. Experts believe that optics could be playing a role in board-to-board links in as little as 2 years. It will take at least 7 years before optical interconnects will be employed for chip-to-chip communication [Sav02, Gra04]. Whether optical interconnects will ever connect the subsystems within a single chip, is under heavy discussion. Blue Laser-Diode and Next-Generation DVD The demand for blue laser diodes, made from gallium nitride (GaN) and invented by Shuji Nakamura in 1995, is being driven by next-generation optical storage systems. The use of blue rather than infrared or red lasers provides a dramatic increase in storage capacity. Together with increases in the numerical aperture of the focusing optics, blue-wavelength storage systems operating at 405 nm can provide 3 to 5 times more storage capacity per layer than the current DVD systems that operate at 650 nm. Two diﬀerent standards have been developed independently: the highdeﬁnition DVD (HD-DVD) standard proposed by Toshiba, and Sony’s BluRay Disc. Blu-Ray Discs have a capacity of 25 GB per layer. Despite a lower capacity of 15 GB per disc layer, one of the advantages of the HD-DVD format is its compatibility with existing DVD production methods. In 2006, the ﬁrst DVD movies were released, both in HD-DVD and in Blu-Ray Disc. Big Hollywood studios like Warner Brothers and Paramount Pictures are supporting both formats, which is a clear sign that both standards will co-exist for a while. Another important consumer-market is the computer gaming market. R 3 in NovemSony Computer Entertainment Inc. launched the Playstation ber 2006, incorporating the Blu-Ray technology. During the same period the Xbox 360 external HD-DVD drive was introduced by Microsoft, that other entertainment giant.

1.3 Silicon Opto-Electronics

7

1.3 Silicon Opto-Electronics According to the Communications Technology Roadmap, silicon microphotonics seeks to build optical devices on the platform that has enabled Moore’s Law: single-crystal silicon [MIT05]. Beyond this, deﬁnitions diverge. At one extreme, hybrid integration on silicon involves the incorporation of non-siliconbased devices manufactured oﬀ-chip with CMOS devices. At the other extreme, CMOS monolithically integrated silicon photonics achieves a complete set of microphotonic devices using processes available in existing CMOS foundries. Between these extremes, intermediate solutions span the spectrum. As also mentioned in [MIT05], silicon microphotonics will likely need to achieve a high degree of monolithic integration with only a small degree of hybrid integration (like laser sources) in order to oﬀer low cost and increased functionality. But why would the existing electrical interconnects be replaced by optical interconnects, and moreover, why would this be done in silicon? The Communications Technology Roadmap [MIT05] identiﬁes the high-level drivers for silicon photonics integration. A ﬁrst important driver is the intrinsic bandwidth-distance product limitation of electrical interconnects. Electronic communication links are impeded by fundamental physical loss mechanisms, like dielectric losses and skin eﬀect losses. As industries are moving to ever higher bandwidths, they are also approaching the theoretical limit predicted by Shannon’s Law. When Shannon’s limit is reached in any given marketplace, there are two options. The ﬁrst option is to hold on to the electrical interconnects, and increase bandwidth by utilizing parallel channels, changing to lower loss interconnect materials or using repeaters. However, every solution raises the cost considerably. Therefore, the second option might be considered: a complete change to an alternative technology platform that does not suﬀer from the same physical limitations. In Section 1.1, the successstory of long-haul optical communication systems has been presented, where the changeover has been made more than 25 years ago. Fig 1.1 shows that also other industries have switched to photonics when the critical bandwidthdistance product (marked in grey) has been reached. Metro area networks (MAN) changed to optical communication over 10 years ago, storage area networks (SAN) switched over 5 years ago. Future candidates are serial computer busses, backplane interconnects and digital visual interface (DVI) for computer displays. The roadmap [MIT05] recognizes that another important driver is needed to justify the nontrivial reapplication of the silicon manufacturing infrastructure for optical interconnects: a volume driver. After all, modern silicon fabs are expensive. Table 1.2 shows that attractive silicon wafer volumes may come from bandwidth increases at the edge of the network. Volumes are far less attractive away from the edge, where the network is already primarily optical today. Higher bandwidth demands at the edge of the network (serial computer busses, backplane interconnects, etc.) will increase pressure for optical

8

1 Introduction Photonic Domain

1 THz

100 GHz Storage Area Net− works

10 GHz Serial Comp. Bus

1 GHz

100 MHz

Metro Area Free Net− Space works Com.

Long Haul Net− works

DVI

Back− plane

10 MHz

1 MHz

Electrical Domain 0.1 m

1m

10 m

100 m

1 km

10 km 100 km

Fig. 1.1. Bandwidth-distance market map [MIT05]. Table 1.2. Network bandwidth requirements and market volume [MIT05]. WAN MAN

LAN

Current BW 1 THz 100 GHz 10 GHz Future BW 1 THz 100 GHz 100 GHz 106 107 Interconnects 105 Wafers/week 2 20 200

Processor 1 GHz 1 THz 109 20000

solutions. That pressure is supported with volume potentials capable of sustaining an industry of silicon fab facilities. Furthermore, Fig. 1.1 shows that these interconnects need bandwidths in the order of 10 GHz. So if silicon opto-electronic solutions want to support these data rates, only todays’ latest silicon technologies will be suitable to enable fully integrated products. The presented research work ﬁts in this quest for integrated optoelectronics, and follows the extreme side of deep-submicron CMOS silicon photonics. After all, the key market driver for silicon microphotonics adoption is a signiﬁcant reduction of cost. Only a lower cost will drive the transition from electronic to photonic interconnects. As was the case for VLSI, monolithic integration will be essential to reduce the cost. Furthermore, for this integration, the technology with the lowest cost must be chosen, which is a standard CMOS technology, widespread used in digital applications. And yes, it will be diﬃcult to reach the same optical performance in CMOS as in dedicated compound -and expensive!- semiconductor technologies.

1.4 Outline of the Work

9

However, silicon solutions are on their way, for detectors and receivers (as presented in this work), modulators and switches. Furthermore, despite the fact that silicon has an indirect bandgap and an over-long spontaneous recombination lifetime, researchers are ﬁnding innovative techniques to ‘light up’ silicon lasers [CP06, Pan05, Cof05]. Moreover, applications will emerge where medium performance can be tolerated, but where low cost and high volumes are of prime importance. These are exactly the strong points of standard CMOS.

1.4 Outline of the Work The presented work aims for the integration of photodiodes together with broadband ampliﬁers in a mainstream CMOS process. It is a contribution in the research for a truly integrated single-chip opto-electrical receiver. Chapter 2 starts with the optical receiver fundamentals. Two receivers will be discussed at the system level: a transceiver for optical communication systems and a pickup unit for optical storage systems. The properties of continuous mode non-return-to-zero pseudorandom binary data will be summarized and the eye diagram will be introduced. Three phenomena will be distinguished that degrade the data quality and introduce errors: noise, bandwidth limitations and jitter. The next three chapters will be dedicated to the three ﬁrst building blocks of an opto-electrical receiver: the photodiode, the transimpedance ampliﬁer, and the post-ampliﬁer. Chapter 3 will treat the implementation of a photodiode in standard CMOS. First, some basic concepts like absorption coeﬃcient, responsivity and intrinsic speed performance of the diode will be deﬁned. Also an explicit motivation for the use of CMOS will be given. To illustrate the feasibility of integrated silicon photodetectors, some publications found in open literature will be discussed. To gain in-depth understanding of the photodetection mechanisms, a one-dimensional model based on semiconductor physics will be worked out. However, this model has its shortcomings that will be redressed by the two-dimensional model. This model will be used to compare the responsivity and speed performance of diﬀerent photodiode topologies, like the classical n-well diode, the p+ n-well diode with guard and the differential diode. Furthermore, the consequences of applying light with shorter wavelengths will be investigated. Finally, the eﬀect of shrinking linewidths in emerging CMOS technologies on the photodiode performance will be studied. The theoretical analysis of the transimpedance ampliﬁer (TIA) will be presented in Chapter 4. After the deﬁnition of the performance requirements, the TIA with shunt-shunt feedback will be studied. High level design equations will be derived for gain, bandwidth, stability and noise performance. The transimpedance-bandwidth product will be proposed as a ﬁgure of merit. In a literature overview, two types of implementations will be recognized: the

10

1 Introduction

TIA with common-source input stage and the TIA with regulated cascode input stage. Finally, the design of three CMOS TIAs will be discussed in detail at the transistor level. The two ﬁrst designs will be based on a single-stage inverter ampliﬁer. The main purpose of these TIAs will be the comparison of diﬀerent photodiode topologies in a 0.18 µm technology as well as in a 90 nm technology. The third TIA will be optimized for the diﬀerential photodiode at its input. It will include a two-stage diﬀerential voltage ampliﬁer and cross-coupled feedback. A bandwidth of 4.3 GHz and a transimpedance gain of 73 dBΩ will result in a simulated transimpedance-bandwidth product of 19 THzΩ. Chapter 5 will cover the design of the post-ampliﬁer, or more precisely the limiting ampliﬁer (LA). Just like for the TIA, the LA performance requirements will be deﬁned and a literature summary will be given. In a ﬁrst design phase, the optimal number of gain stages to achieve maximal gain-bandwidth product will be calculated. Next, two broadband gain stages will be presented and analyzed: the Cherry-Hooper gain stage and the capacitive source degenerated gain stage. Furthermore, a basic oﬀset compensation scheme will be described. The chapter will conclude with transistor-level simulations of two 0.18 µm CMOS LAs. The ﬁrst LA will comprise four identical Cherry-Hooper stages. The second LA will be an improved design, including oﬀset compensation. A gain of 38 dB and a bandwidth of 5 GHz will result in a simulated gain-bandwidth product of almost 400 GHz. Finally, theory will be put into practice in Chapter 6, where the measurement results of four opto-electrical circuits will be discussed. Much attention will be paid to the practical measurement set-up. The ﬁrst chip will contain diﬀerent 0.18 µm photodiode topologies, from which the diﬀerential photodiode will turn out to be the most promising one and will reach bitrates up to 500 Mbit/s with low BER. The second chip will compare the performance of three 90 nm photodiodes. The most successful topology on this chip will be the p+ n-well diode with guard that also will achieve a bitrate of 500 Mbit/s. Compared to the 0.18 µm diﬀerential diode, the same input power will lead to a higher BER. Next, the measurements of the 0.18 µm broadband LA will be discussed. Eye diagrams up to 3.5 Gbit/s will demonstrate the implemented broadband techniques. The ﬁnal chip will synthesize all previous work together with high-speed improvements, to constitute a monolithic 0.18 µm CMOS optical receiver. Photodiode, transimpedance ampliﬁer and limiting ampliﬁer will be integrated on the same die, together with additional circuits like an analog equalizer and a high-speed output buﬀer. Electrical measurements of the LA up to 6 Gbit/s will be shown, while the complete receiver will be proven to be fully functional at bitrates higher than 1 Gbit/s. These results are quite comparable with present state-of-the-art in 0.18 µm CMOS. However, the main bottleneck remains the integration of the photodiode with TIA, while achieving a high sensitivity and a high overall bandwidth. The integration of photodetector and circuit undoubtedly has several advantages, but also poses severe challenges to the analog designer. The main speed obstacle

1.4 Outline of the Work

11

is the photodiode, which will be shown to have an intrinsic bandwidth of 10 MHz. This intrinsic bandwidth will be enhanced by using the diﬀerential photodiode topology combined with an analog equalizer, but then another limit will be reached: jitter. This jitter is due to the nature of the photodiode signals, and can only be eliminated by the design of an improved TIA with an enhanced common-mode suppression. Chapter 7 will conclude with the main contributions and achievements of the presented work, and some suggestions for future research.

2 Optical Receiver Fundamentals

2.1 Introduction This chapter describes the background necessary for the analysis and design of opto-electronic interface circuits. In Section 2.2, the optical receiver is discussed at the system level, presenting two case-studies: a transceiver for optical communication systems and a pickup unit for optical storage systems. Section 2.3 reviews the properties of random binary data and considers methods of generating pseudo-random data. Also the eye diagram, a way to visualize the quality of random data eﬃciently, is introduced. In Section 2.4, it is analyzed how noise in the receiver causes bit errors. This leads to an expression for the bit error rate and the deﬁnition of receiver sensitivity. The eﬀect of bandwidth limitation on random data is discussed in Section 2.5, and the term intersymbol interference is introduced. Finally, diﬀerent types of jitter are explained in Section 2.6.

2.2 The Optical Receiver Front-End This section describes two systems where optical signals must be converted into electrical signals: a transceiver used in optical communication systems and a pickup unit needed in optical storage systems. Both systems have three building blocks in common: a photodiode, a transimpedance ampliﬁer and a post-ampliﬁer. These three blocks are commonly referred to as the receiver front-end. Design of the photodiode, transimpedance ampliﬁer and post-ampliﬁer in a CMOS technology are the main topics of this work and will be discussed in greater detail in Chapter 3, Chapter 4 and Chapter 5 respectively. 2.2.1 A Transceiver for Optical Communication Systems Fig. 2.1 shows the block diagram of a typical optical receiver and transmitter [S¨ ac05]. The optical signal from the ﬁber is received by a photodiode, 13

14

2 Optical Receiver Fundamentals TIA CDR

PD

Driver

DMUX data

n

clock

clock/n

MUX n

LD

Digital Logic

PA

select clock

clock/n

Transceiver CMU

Fig. 2.1. Block diagram of an optical receiver (top) and transmitter (bottom).

which produces a small output current proportional to the optical signal. This current is converted to a voltage by a transimpedance ampliﬁer (TIA). The voltage signal is further ampliﬁed by a post-ampliﬁer (PA), which can either be a limiting ampliﬁer (LA) or an automatic gain control ampliﬁer (AGC ampliﬁer). The resulting signal, which is now several 100 mV strong, is fed into a clock and data recovery circuit (CDR). This unit extracts the clock signal and generates high quality data from the original signal. In high-speed receivers, a demultiplexer (DMUX) converts the fast serial data stream into n parallel, lower-speed data streams that can be processed conveniently by the digital logic block. Sometimes the DMUX task is part of the CDR design, and an explicit DMUX is not needed. The digital logic block descrambles or decodes the bits, performs error checks, extracts the payload data from the framing information, etc. On the transmitter side, the same process happens in reverse order. The parallel data from the digital logic block are merged into a single high-speed data stream using a multiplexer (MUX). To control the select lines of the MUX, a bitrate clock must be synthesized from the parallel data clock. This task is performed by a clock multiplication unit (CMU). Finally, a laser driver or modulator driver drives the corresponding opto-electronic device. The laser driver modulates the current of a laser diode (LD). The modulator driver modulates the voltage across a modulator, which in turn modulates the light intensity from a continuous wave laser. Some laser/modulator drivers also perform data retiming and thus require a clock signal from the CMU.

2.2 The Optical Receiver Front-End

15

Fig. 2.2. A Gbit/s small form-factor pluggable transceiver mounted on an evaluation board.

A module containing a photodiode, TIA, PA, laser driver and laser diode (all the blocks shown inside the dashed box of Fig. 2.1) is called a transceiver. Sometimes also quantization circuits are included in the receiver part. In Fig. 2.2, a so-called small form-factor transceiver is shown, plugged into its evaluation board. The transmitter part is used as high-speed optical source for the measurements discussed in Chapter 6. 2.2.2 A Pickup Unit for Optical Storage Systems Data on an optical disc is physically contained in pits which are precisely arranged on a spiral track. A pickup unit is used to recover this data. It moves across the surface of the rotating disc and must focus, track and read that data track. A three-beam optical pickup is shown in Fig. 2.3 [Poh00]. The light beam, generated by the laser diode (LD), passes through a diﬀraction grating (DG). This is a screen with slits spaced only a few laser wavelengths apart. As the beam passes through the grating, it diﬀracts at diﬀerent angles. When the resulting collection is again focused, it appears as a bright center beam with successively less intense beams on either side. In a three-beam pickup design, the center beam is used for reading data and focusing, and two secondary beams, the ﬁrst order beams, are used for tracking. The polarization beam splitter (PBS) directs the laser light to the disc surface, and bends the reﬂecting light to the photodiode. For the light approaching the PBS, it acts as a transparent window, but for the reﬂected light with rotated plane of polarization, it acts as a prism redirecting the beam. The PBS is followed by a collimator lens, which takes the divergent

16

2 Optical Receiver Fundamentals disc

Objective lens

QWP Collimator lens

Mirror LD

DG

PBS Cylindrical lens

PD E

A

B

C

D

F

Fig. 2.3. General three-beam optical pickup organization.

light rays and makes them parallel. The light then passes through a quarterwave plate (QWP), which rotates the plane of polarization of the incident and reﬂected laser light. As a result, the reﬂected light is polarized in a plane at a right angle relative to that of the incoming light, allowing the PBS to properly deﬂect the reﬂected light. Finally, the light passes through the objective lens, with a numerical aperture (NA) dependent on the minimal pit size. The smaller this size, the higher the NA, and the smaller the wavelength of the laser beam. This trend complicates the realization of the optical system, but there is one big advantage: a smaller pit size also results in a higher disc storage capacity. Table 2.1 compares these ﬁgures for three generations of optical disc storage: CD (infra-red light), DVD (red light) and HD-DVD and Blu-Ray Disc (both blue light). The objective lens is attached to a two-axis actuator and servo system for up/down focusing of motion and lateral tracking motion. When a light spot strikes a land interval between two pits, the light is almost totally reﬂected. When it strikes a pit, destructive interference occurs and a lower light intensity is returned. A change in intensity is interpreted

2.3 Binary Data Formats

17

Table 2.1. Optical Disc Storage Systems. CD λ NA track pitch min. pit size Storage capacity per layer

780 nm 0.45 1.6 µm 0.83 µm 650 MB

DVD HD-DVD Blu-Ray Disc 650 nm 405 nm 0.65 0.65 0.74 µm 0.4 µm 0.4 µm 0.204 µm 4.7 GB 15 GB

405 nm 0.85 0.32 µm 0.14 µm 25 GB

as a one, while an unchanged intensity is interpreted as a zero. The varying intensity light returns through the objective lens, the QWP, the collimator lens, and strikes the surface of the PBS. The light is deﬂected and passes through a cylindrical lens that focuses the light on the photodiode. As can be seen in Fig. 2.3, the photodiode consists of several segments: four central segments A to D and two satellite segments E and F. The central segments detect the main light beam, so are used for focus control and for data readout. The satellite segments detect the side beams and supply signals for tracking control. The current signal from each diode segment is ampliﬁed separately by a transimpedance ampliﬁer and post-ampliﬁer channel. The channels from the signal diodes usually have a higher bandwidth than the more sensitive satellite channels. Finally, the information from the six channels is combined to retrieve the necessary information (e.g. (A+B+C+D) is the wanted data signal, (A+C)-(B+D) is the focus signal and (F-E) is the tracking signal).

2.3 Binary Data Formats This section describes the binary data used in optical communication systems. It is important to understand the terms described further down, because they deﬁne the physical data which is applied at the input of the implemented circuits in Chapter 6. The most commonly used modulation format in optical communication is the non-return-to-zero (NRZ) format, shown in Fig. 2.4. This format is a form of on-oﬀ keying: the signal is on to transmit a one bit and is oﬀ to transmit a zero bit. When the signal is on, it stays on for the entire bit period Tb . The inverse of the bit period is the bitrate Rb . For example, when transmitting the periodic bit pattern ‘010101...’ at a bitrate of 2 Gbit/s in NRZ format, a 1 GHz square wave with 50 % duty cycle is produced. The bit period of each one or zero equal 0.5 ns. In high-speed, long-haul transmission systems, the return-to-zero (RZ) format, also shown in Fig. 2.4, is generally preferred. In this format, the pulses, which represent the one bits, occupy only a fraction (e.g. 50 %) of the bit

18

2 Optical Receiver Fundamentals 0

0

1

0

1

0

1

1

0

1

0

1

NRZ

RZ time Tb

Fig. 2.4. NRZ versus RZ data.

period. Compared with the NRZ signal, the RZ signal requires less signal to noise ratio for reliable detection. On the other hand, the bandwidth needed is larger because of its shorter pulses. The remainder of this text will only deal with NRZ data. To provide data at the input of the receiver with some desirable properties, line coding is applied in the digital domain. First, a DC balanced bit stream, which contains the same number of zeros and ones on average, is wanted. A DC balanced data stream is the same as an average mark density (number of one bits divided by all bits) of 50 %. Such a data stream has the property that its average value (the DC component) is always centered halfway between the zero and one levels. This property often permits the use of ac coupling between circuit blocks. Second, it is desirable to keep the number of successive zeros and ones, or the run length, to a small value. This reduces the low-frequent content of the transmitted signal, and limits the associated baseline wander (explained in Section 2.5.2) when ac coupling is used. In practice, line coding is implemented as either scrambling (SONET, SDH), block coding (Gigabit Ethernet) or a combination of the two (10Gigabit Ethernet): • Scrambling. A pseudorandom bit sequence (prbs) is generated with a feedback shift register, and xor’ed with the data bit stream (see Fig. 2.5). The shift register length is determined by the pattern title, so a 2n − 1 prbs pattern would be generated using a shift register n bits long. This pattern contains every possible combination of n bits, except one. Scrambling provides DC balance without adding overhead bits to the bit stream, thus preserving the bitrate. The average mark density is closer to 50 % as the pattern length increases. On the other hand, the maximum run length is also determined by the length of the shift register: a 231 − 1 prbs pattern contains 31 consecutive ones or zeros. • Block coding. A group of bits is replaced by another, slightly larger group of bits, such that the average mark density becomes 50 % and DC balance is established. For example, in the 8B10B code, 8-bit groups are replaced with 10-bit patterns using a look-up table. The 8B10B code increases the

2.3 Binary Data Formats

1

2

3

n−1

Clock

19

Data out

n

Data in

Fig. 2.5. An n-bit shift register for the generation of a 2n − 1 prbs pattern.

1 0 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 0 1 0 1 continuous mode time 1 0 0 1

1 0 1 1 burst mode time

Fig. 2.6. Continuous mode versus burst mode data.

bitrate by 25 %. However, the maximum run length is strictly limited to ﬁve zeros or ones in a row. With the development of passive optical networks (PON) like ﬁber-to-thehome (FTTH), a new type of transmission mode is introduced: burst mode. In traditional, continuous mode transmission, an uninterrupted stream of bits is transmitted, as shown in Fig. 2.6. The transmitted signal usually is DC balanced, using one of the line codes described above. As a result, ac coupled circuits normally can be used. In burst mode transmission, data bits are transmitted in short bursts, while the transmitter remains silent (laser oﬀ) in between bursts (see Fig. 2.6). Also, the amplitude of the received signal bursts may vary as they originate from diﬀerent sources. The DC component of a burst mode data varies with time, depending on the burst activity. If the activity is high, it may be close to the average of the zero and one levels. If the activity is low, the DC value drifts arbitrarily close to the zero level. So burst mode signals are not DC balanced, which means that ac coupling cannot be used as it would lead to excessive baseline wander (see Section 2.5.2). The receiver front-ends described in this work are designed for continuous mode transmission. To study the eﬀects of circuit and/or system non-idealities on random data, the eye diagram is often used. Such a diagram folds all of the bits into a short interval, for example two bits wide. The total waveform is ﬁrst cut into two-bit segments. Next, all these segments are superimposed, displaying

20

2 Optical Receiver Fundamentals 0

0

0/1

1

1

1/0

0

1

0/1

1

0

1/0

Fig. 2.7. Schematic representation of the construction of an eye diagram.

an accumulation of distorted edges and levels, as can be seen in Fig. 2.7. An important advantage of the eye diagram over the total linear waveform is that all possible bit transitions can be displayed in a compact representation. In Chapter 6, eye diagrams will be used frequently to intuitively judge the quality of the measured signal.

2.4 Bit Error Rate and Sensitivity A ﬁrst phenomenon which degrades the opening of the eye diagram is noise. The noise of the receiver is caused by the detector noise and the ampliﬁer noise. Mostly, the noise of the TIA, is dominant. The conditions for minimum TIA input noise will be discussed in Section 4.3.3. This section describes how the inﬂuence of noise can be measured by introducing the bit error rate and sensitivity of the receiver. 2.4.1 Bit Error Rate The voltage at the output of the TIA or PA can be considered as a superposition of the wanted signal voltage x(t) and the unwanted noise voltage n(t). Occasionally, the instantaneous noise voltage n(t) may become so large that it corrupts the received signal x(t), leading to a decision error or bit error. The bit error rate (BER) is deﬁned as the probability that a zero is misinterpreted as a one or that a one is misinterpreted as a zero. An expression for the BER can be derived [Cou97, Raz03, S¨ac05], based on following assumptions: • The receiver consisting of photodiode, TIA and PA is linear. Even if the PA is implemented as a limiting ampliﬁer, which becomes non-linear for large signals, this model is appropriate, because the noise levels and the signal levels at the sensitivity limit are so small. • The wanted signal is a NRZ data pattern where the logical one is represented by V1 and the logical zero by V0 . The peak-to-peak value vpp thus

2.4 Bit Error Rate and Sensitivity

21

equals V1 − V0 . The probability Px (x = V1 ) of receiving a one equals the probability of receiving a zero Px (x = V0 ), so: Px (x = V1 ) = Px (x = V0 ) = 1/2.

(2.1)

• The probability density function for the noise Pn is stationary and has a Gaussian distribution with zero mean: 2

−n 1 Pn = √ e 2σn2 . 2πσn

(2.2)

The standard deviation σn is equal to the rms value of the noise voltage vn,rms . • The threshold voltage VT H of the decision circuit is located at the midpoint between the zero and one levels, so: VT H =

V1 + V0 . 2

(2.3)

The decision circuit determines whether a bit is a zero or a one by comparing the signal at the output of the PA (or TIA) with this threshold voltage. As demonstrated in [Cou97], a decision level in the middle of the zero and one levels minimizes the BER. For the measurements described in Chapter 6, the decision circuit is included in the measurement equipment. The relationship between signal, noise and BER is graphically represented in Fig. 2.8. The noisy signal is sampled by the decision circuit at the center of each bit period (vertical dashed lines), producing the statistical distributions shown on the right-hand side. Both distributions are Gaussian, and have a standard deviation equal to σn . The BER corresponds to the shaded areas under the Gaussian tails and is given by: v pp BER = Q . (2.4) 2σn Q(x) is called the ‘Q function’ and deﬁned as: ∞ 1 −u2 √ e 2 du. Q(x) = 2π x

(2.5)

The Q function is not available in closed form, but for x > 3, it can be approximated with high accuracy by: −x2 1 Q(x) ≈ √ e 2 . x 2π

(2.6)

Note that the argument of the Q function in (2.4) is given by one half of the peak value of the signal divided by the rms value of the noise. This ratio can be considered as a signal to noise ratio (SNR). Some commonly used values are: Q(6) ≈ 10−9 , Q(7) ≈ 10−12 .

22

2 Optical Receiver Fundamentals 0

1

0

0

1

1

0

σn 00 11 11 00 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11

vpp

VTH

Fig. 2.8. Relationship between signal, noise and BER.

2.4.2 Sensitivity The sensitivity of a receiver is the minimum signal needed at the input to achieve a certain BER. It reﬂects to what level the transmitted signal can become attenuated and still be detected reliable by the receiver. Sensitivity can be deﬁned in the electrical as well as in the optical domain. The electrical sensitivity, isens pp , is deﬁned as the minimum peak-to-peak signal current at the input of the receiver, necessary to achieve a speciﬁed BER. Common BER values to deﬁne sensitivity are 10−9 and 10−12 . The argument of the Q function (2.4) can be referred to the input using the midband values of the small-signal transfer functions of the TIA (ZT IA,0 ) and the PA (AP A,0 ). These transfer functions will be calculated for some circuit implementations in Chapter 4 and Chapter 5, respectively. The equivalent input-referred rms noise in,rms is deﬁned as: σn = vn,rms = ZT IA,0 · AP A,0 · in,rms .

(2.7)

Notice that this noise current is not a signal which is physically present at the input, but only a mathematical deﬁnition to deﬁne the sensitivity of the receiver. For mid-band frequencies, the current swing isens at the input of the pp TIA causes the output voltage vpp at the PA: vpp = ZT IA,0 · AP A,0 · isens pp .

(2.8)

Combining (2.4), (2.7) and (2.8) results in the expression for BER in function of the electrical sensitivity: BER = Q

isens pp . 2in,rms

(2.9)

sens The optical receiver sensitivity, Pav , is deﬁned as the minimum optical power, averaged over time, necessary to achieve a speciﬁed BER. For a DC balanced signal, it holds that:

2.5 Intersymbol Interference

23

R V in

V out C

1 0 1 0 1 0 1 (a) 1 0 0 1 1 0 1 (b)

vpp

V TH time

time t1

t2

Fig. 2.9. Eﬀect of low-pass ﬁltering on binary data: (a) periodic data, (b) random data. sens Pav =

isens pp , 2R

(2.10)

where R is the responsivity of the photodiode (3.4) and expressed in A/W. This leads to a third expression for the BER: P sens · R . (2.11) BER = Q av in,rms In the measurements of Chapter 6, the optical sensitivity for a certain BER will be used, rather than the electrical sensitivity. After all, optical signals are applied at the input and can be measured directly.

2.5 Intersymbol Interference Not only noise reduces the quality of the eye diagram, also bandwidth limitations have impact on the eye opening. This type of degradation is known as intersymbol interference (ISI). The eﬀect of both low-pass ﬁltering and high-pass ﬁltering are discussed. 2.5.1 Low-Pass Filtering In order to study the eﬀect of the ﬁnite bandwidth of circuits, the signal quality at the output of a ﬁrst order low-pass ﬁlter is examined. As shown in Fig. 2.9, the ﬁlter simply consists of resistor R and capacitor C. The 3-dB bandwidth f3dB of this ﬁlter is given by: f3dB =

1 . 2πRC

(2.12)

When a periodic square wave is applied at the input, the output signal consists of rising and falling exponential waves, with time constant τ = RC (see

24

2 Optical Receiver Fundamentals C

V in

V out R

1 0 1 1 1 1

0 1

time

time

Fig. 2.10. Eﬀect of high-pass ﬁltering on random binary data.

Fig. 2.9(a)). This means that for time t = τ , the output has risen or fallen to 63 % of its ﬁnal value. If the bit period Tb is large enough compared to τ , the exponential tail has vanished and the peak-to-peak value of the binary data is large enough to be detected without any errors. Considering random data in Fig. 2.9(b), the output does not attain the upper or lower levels which deﬁne vpp at the end of every bit period. For two consecutive ones or zeros, it does, but for a single one followed by a single zero (or vice versa), it doesn’t. This is undesirable because the output voltage levels corresponding to ones and zeros vary with time, making it diﬃcult to deﬁne a decision threshold VT H . For example, the levels at t = t1 and t = t2 are more susceptible to noise and can be misinterpreted by the detector. This phenomenon is called intersymbol interference (ISI), because the exponential response during one bit period corrupts the signal levels produced for subsequent bits. The narrower the bandwidth, the longer the exponential tails and the greater the ISI. 2.5.2 High-Pass Filtering To understand the eﬀect of high-pass ﬁltering, suppose a random binary sequence is applied to the ﬁrst-order high-pass ﬁlter with capacitor C and resistor R (see Fig. 2.10). The low-frequency cut-oﬀ, or the frequency where the gain is 3 dB lower than its high-frequent value, is given by: fLF =

1 . 2πRC

(2.13)

Such a low-frequency cut-oﬀ appears in the receiver response for instance when ac coupling is used between TIA and PA, or when oﬀset compensation is used in the PA (Chapter 5). Fig. 2.10 shows that each transition at the input immediately appears at the output, but when receiving a long string of ones or zeros, the output voltage drifts. As a result, the bits after each long run suﬀer from a large (temporary) DC shift, making it diﬃcult to set a decision threshold VT H . This phenomenon can also be viewed as ISI, because each bit level depends on the preceding pattern.

2.6 Jitter

25

V

TH

jitter

Fig. 2.11. Jitter deﬁnition.

The above eﬀect is called baseline wander or DC wander, because the ‘instantaneous’ DC value of the output waveform changes randomly. To minimize baseline wander, τ = RC must be suﬃciently larger than the longest possible data run of ones or zeros.

2.6 Jitter So far we have discussed how noise and ISI aﬀect the signal levels at the decision circuit. However, the decision process not only involves the signal voltage, but also the signal timing. The deviations of the threshold voltage VT H crossings from their ideal position in time is called jitter (Fig. 2.11). Jitter may inﬂuence the optimal sampling instant of the decision circuit. Just like noise and ISI, too much jitter closes the eye opening and introduces bit errors. The total jitter may be composed of deterministic jitter and random jitter. Examples of deterministic jitter are data-dependent jitter and duty-cycle distortion jitter. Data-dependent jitter is produced when the signal edge moves slightly in time, depending on the values of the surrounding bits. It can be caused for example by an insuﬃcient bandwidth or by baseline wander due to an insuﬃcient low-frequency cut-oﬀ. Duty-cycle distortion jitter occurs if the rising and falling edges do not cross each other at the decision threshold voltage. Random jitter is, in contrast to deterministic jitter, not related to any data pattern or any deterministic cause. It is produced, for example, by noise on edges with a ﬁnite slew rate. It can also be caused by carrier mobility variations due to instantaneous temperature ﬂuctuations. Besides the data jitter described above, also clock jitter exists. This jitter is important in the clock and data recovery circuit where the decision process takes place. For instance, if the sampling instant of the decision circuit varies with time, an increase in BER might occur. In the frequency domain, the jitter counterpart is called phase noise. It is extremely important for the design of oscillators and clock and data recovery circuits, but falls beyond the scope of this text.

26

2 Optical Receiver Fundamentals

2.7 Conclusions Some basic concepts and deﬁnitions, needed in the remainder of this text, have been introduced in this chapter. First, two systems have been studied which both contain an optical receiver front-end: a transceiver for optical communication systems and a pickup unit for optical storage systems. Next, the data which will be applied at the input of the receiver circuits has been presented: continuous mode non-return-to-zero pseudorandom binary data. An eﬃcient representation of this data is the eye diagram, and it will be used frequently to study the data quality at the output of the receiver. Finally, three phenomena have been studied which reduce the eye opening and introduce bit errors: the receiver noise, the limited receiver bandwidth and jitter.

3 Standard CMOS Photodiodes

3.1 Introduction This chapter discusses the ﬁrst component of the optical receiver, the photodetector. It deviates from subsequent chapters, as no integrated circuits are discussed and no transistors are shown in the ﬁgures. However, the optical and electrical properties of the photodiode impose important requirements on the design of the next blocks of the receiver chain. Therefore, this chapter is completely dedicated to the light detection mechanisms involved using reversely biased silicon pn-junctions. Section 3.2 starts with the basic deﬁnition of a photon, to end with the most relevant characteristics of the photodiode: responsivity and speed. Motivation is provided for the integration of photodetectors in a non-optimized, mainstream CMOS technology. By means of illustration, an overview of some interesting monolithic opto-electrical receivers is given in Section 3.3. Not only CMOS implementations are considered, but also BiCMOS and SOI implementations. To gain in-depth understanding of the photodetection mechanisms, a onedimensional model, based on semiconductor physics equations, is worked out in Section 3.4. Because this model has its limitations, a two-dimensional model is developed with MEDICI. This model is discussed in Section 3.5. The speed and responsivity performance of several diode topologies are compared, and the inﬂuence of technology scaling and illumination with diﬀerent light wavelengths are studied. The results and trends predicted by these simulations correspond well with other photodiode modeling papers which can be found in open literature: [Pal01, Gen01, Rad03, Rad05].

3.2 Basic Concepts In an optical communication system, the light generated by a laser diode is converted to an electrical signal at the receive end by means of a photodiode. 27

28

3 Standard CMOS Photodiodes

Various properties of photodiodes aﬀect the sensitivity and speed of the receiver front end. This section discusses some basic deﬁnitions to characterize the performance of a photodiode. Also the pro’s and con’s of using a mainstream CMOS technology are discussed. 3.2.1 Principles of Light Detection As shown by Albert Einstein in 1905, light behaves not always as a continuous wave. Under certain circumstances, light acts as a stream of discontinuous, individual particles. These particles, or “light quanta,” (later named photons) each carry a “quantum,” or ﬁxed amount of energy, given by: Ep = hν =

hc . λ

(3.1)

h = 6.63 · 10−34 J · s is Planck’s constant, ν is the frequency of the electromagnetic wave, c = 3 · 108 m/s is the speed of light in vacuum and λ is the corresponding wavelength. The higher the frequency or the smaller the wavelength, the more energy per photon or the less photons for a given total energy. Light detection can be performed by a reversely biased junction, as shown in Fig. 3.1. When the junction is illuminated with light, incident photons with an energy larger than or equal to the bandgap energy Eg of the semiconductor material generate electron-hole pairs. Fundamental absorption of photons with an energy smaller than Eg is not possible. Consequently, the semiconductor is transparent for light with wavelengths longer than: λc =

hc . Eg

(3.2)

For silicon, Eg = 1.12 eV, which means that only light with wavelengths shorter than 1.1 µm can be detected with silicon photodiodes. The electrons and holes generated in the depletion region (or space charge region SCR) are separated by a large electric ﬁeld and drift in opposite directions. The transport mechanism of the carriers generated outside the depletion region is diﬀusion, which is a slow transport mechanism compared to drift. These carriers may recombine before they are detected, or they diﬀuse inward and are collected across the junction, adding a slow tail to the photodiode’s time response. To prevent the recombination loss of generated carriers and to have a fast diode response, eﬃcient photodiode operation demands a large depletion region. The absorption coeﬃcient α determines how deep light of a particular wavelength penetrates into a speciﬁc material. The intensity of light penetrating into a medium decreases exponentially with depth, as given by LambertBeer’s Law: (3.3) Φ(x) = Φ0 · e−αx .

3.2 Basic Concepts

29

VR

I dio

Popt

P

Depletion region

N

Electric field hν hν Conduction band Bandgap Energy E g

hν

electron diffusion

Valence band hole diffusion

drift

Fig. 3.1. Principle of operation of a semiconductor photodiode.

Absorption coefficient α (μm−1)

1000 100 10 In0.53Ga0.47As 1

Si InP

Ge

0.1 0.01 GaAs 0.001

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Wavelength λ (μ m) Fig. 3.2. Absorption coeﬃcient versus wavelength for various semiconductor materials [Zim04].

30

3 Standard CMOS Photodiodes

Φ(x) is the light ﬂux ( photons/(cm2 · s)) at depth x in the material while Φ0 is the initial ﬂux. The absorption coeﬃcient versus wavelength is depicted in Fig. 3.2 for the most important semiconductor materials [Zim04]. In0.53 Ga0.47 As and Ge cover the widest range of wavelengths, including 1.3 µm and 1.54 µm, which are used for long distance optical ﬁber communication. The absorption coeﬃcients of GaAs and InP are high in the visible spectrum (≈ 400 nm–700 nm). Silicon detectors are appropriate for the visible and infrared spectral range. The absorption coeﬃcient of silicon is however one or two orders of magnitude smaller than that of the direct semiconductors InP and GaAs. The inverse of the absorption coeﬃcient, 1/α, is called the penetration depth, and will be used frequently in this text. The diode current Idio , consisting of photo-generated carriers, is linearly proportional to the optical power Popt : Idio = R · Popt .

(3.4)

R is called the responsivity of the diode. Typical values for commercially available infrared photodiodes are 0.5 A/W to 0.8 A/W. In an ideal photodiode, every photon entering the device generates an electron-hole pair. In reality, however, some photons are reﬂected from the surface or absorbed by the material to produce heat. The quantum eﬃciency of the photodiode is the ratio of the number of electrons generated, and the number of photons applied: Idio /q Popt /(hc/λ) hc =R qλ 1.24 = R. λ

η=

(3.5) (3.6) (3.7)

Besides responsivity, speed is an important parameter of the photodiode. As already mentioned before, the slowly diﬀusing carriers add a tail to the diode’s time response. For example, the diﬀusion time of a hole through 10 µm of silicon is 40 ns [Mil79]. So for high-speed operation, the depletion region has to be suﬃcient wide, preferably wider than the penetration depth 1/α. Due to the high electrical ﬁeld over the junction, the carriers attain their saturation velocity, which is approximately 107 cm/s in silicon [Mil79]. Consequently, the transit time can be very short, for instance 0.1 ns for a 10 µm wide junction. Having a depletion region that encloses the absorption region is also the requirement for high quantum eﬃciency, as diﬀusing carriers might recombine before detection. In Sections 3.4 and 3.5, the intrinsic speed performance of CMOS photodiodes will be characterized by the 90 % rise time of the step response, the (intrinsic) frequency characteristic and the (intrinsic) bandwidth. Finally, another important characteristic of the photodiode is its parasitic junction capacitance. As will be explained in Section 4.3.1, its value combined

3.2 Basic Concepts

31

with the input impedance of the receiver, determines an RC constant which limits the bandwidth in most circuits. This bandwidth is often called the extrinsic bandwidth, to distinguish from the intrinsic bandwidth. The junction capacitance is thus of uttermost importance for the transmission speed that is achievable with a photodiode-receiver combination. Its value is dependent on doping concentrations, reverse voltage, and diode area. Note that the latter is mostly one of the only degrees of freedom available in the design of a standard CMOS photodiode, as doping levels and the maximum supply voltage are ﬁxed by the technology. 3.2.2 The Use of Standard CMOS As mentioned in Chapter 1, there exists a wide range of emerging applications where optical receivers are needed. Especially, for these applications, cost aspects are crucial. This is the main motivation for choosing a CMOS technology: in the end, CMOS is cheap. Of course, today’s 65 nm CMOS technologies are expensive. But in a few years, when all digital standard cells are implemented in nm-scale technologies, the high manufacturing cost will be justiﬁed by the large production volumes. Using standard CMOS for light detection has the main disadvantage that the technology is not optimized for optical devices. First, the width of the junctions doesn’t match the penetration depth of light. Second, the reverse voltage available to bias the junctions cannot be higher than the supply voltage. Finally, no postprocessing is allowed, so no anti-reﬂective coatings are used. These limitations result in photodiodes with minor responsivity and speed performance compared to commercially available diodes. To circumvent these diﬃculties and to implement cheap but high-performing optical receivers are the main objectives of this work. Besides the low cost aspect, the integration of photodiodes in standard CMOS has even more beneﬁts. The integration of the photodiode on the same die as the receiver causes a reduction of the external components count, resulting in a low-cost system with enhanced yield. Furthermore, an integrated photodiode reduces the total input capacitance by eliminating the parasitics due to the diode’s package, the PCB wiring, the IC-package and some bondpads. As will become clear in Section 4.3.1, this gives the opportunity to increase the transimpedance-bandwidth product for free. A side eﬀect is that the diode capacitance increases as technology scales down, but this will be treated in more detail in Section 3.5.5. Finally, a major advantage of an integrated photodiode is the reduction of noise coupling into the input node thanks to the removal of bondwires, the package pins and the PCB paths connected to this node, which otherwise pick up spurious signals from the environment. Fig. 3.3 shows the junctions which are available in a standard CMOS technology. The ﬁrst one is an n+ p-substrate junction, the second one is an n-well p-substrate junction and the last one is a p+ n-well junction. They all

32

3 Standard CMOS Photodiodes

(a) p−substrate

(b) p +region

(c) n−well

n +region

Fig. 3.3. Junctions capable of light detection in standard CMOS: (a) n+ p-substrate junction, (b) n-well p-substrate junction, (c) p+ n-well junction.

can be used to detect visible or infrared light, but they all have a diﬀerent performance. The most important diﬀerence between the ﬁrst two junctions is the width of the depletion region. Due to the much lower doping levels of the nwell compared to the n+ region, the width of the n-well p-substrate depletion region is larger, resulting in a more eﬃcient photodetection. Consequently, the analysis of the next sections will mainly focus on the n-well p-substrate diode. The last structure, the p+ n-well junction, is also less eﬃcient with respect to capturing light, but has some special features in combination with the n-well p-substrate junction. This will also be discussed in more detail in the following sections.

3.3 Overview of Published Integrated Photodiodes Before starting with a detailed analysis of CMOS photodiodes and their performance, this section discusses integrated silicon photodetectors which can be found in open literature. It is not the intention to give an exhaustive overview, but to highlight some breakthroughs of the recent past. The emphasis lies on the use of mainstream silicon technologies. Not only CMOS is considered, also photodetectors implemented in BiCMOS and SOI technologies are discussed. 3.3.1 BiCMOS Implementations BiCMOS processes combine both bipolar transistors and nMOS as well as pMOS transistors. It is possible to exploit the advantages of both type of transistors. CMOS transistors allow low-power, high-density digital integrated circuits. Bipolar digital circuits implemented with ECL (Emitter Coupled Logic) gates have a larger driver capability and can operate with small logic swings and high noise immunity. Comparing the analog capabilities, better device matching, lower oﬀset voltage and enhanced bandwidth can be obtained with bipolar subcircuits. On the other hand, the zero input bias current of CMOS transistors can also be used advantageously in analog BiCMOS implementations. These beneﬁts are attained at the expense of a more diﬃcult technology

3.3 Overview of Published Integrated Photodiodes

33

development and at the expense of more complex chip-manufacturing tasks, leading to longer chip-fabrication time and higher costs [Zim04]. The bipolar npn transistor is formed by an n+ -emitter, a p-type base, and an n-type collector. To minimize collector series resistance, the collector not only consists of an epitaxial n− -layer, but also has a buried n+ -subcollector and n+ -collector plugs. Without any process modiﬁcations, the buried n+ subcollector can serve as the cathode, the n-collector epitaxial layer can serve as the intrinsic region of a PIN diode, and the p-base implant can serve as the anode. The main advantage of a PIN diode is its lowly doped intrinsic region where a high electric ﬁeld is present if it is depleted. In this region, carrier transport is drift, which results in fast and eﬃcient photodetectors. This is especially true if the intrinsic region corresponds to the light penetration depth. For 800 nm wavelengths, a thickness of at least 10 µm is necessary due to the low optical absorption coeﬃcient (Fig. 3.2). Such a large intrinsic layer thickness requires a severe reduction of the epitaxial layer concentration to obtain a spreading of the electric ﬁeld over the entire intrinsic zone. However, this would destroy the bipolar transistor performance. Therefore, process modiﬁcations are needed to optimize the performance of both the integrated photodiode (which needs a thick, lowly doped intrinsic layer) and the bipolar transistor (which needs a thin, higher doped n-collector). In [Stu05], a dedicated 0.5 µm BiCMOS technology that combines highspeed transistors with an integrated PIN photodiode is described. The available devices are a single-poly npn bipolar transistor with ft =20 GHz, a vertical pnp bipolar transistor with ft =1 GHz, standard 0.5 µm CMOS, and passive devices like capacitors, resistors and laser fuses. The integrated PIN photodiode is optimized concerning speed and sensitivity for all three light wavelengths used for optical data storage, like CD (780 nm), DVD (660 nm) and Blu-ray (405 nm). The measured photodiode sensitivity is 0.35 A/W, 0.4 A/W, and 0.25 A/W for 780 nm, 660 nm and 405 nm wavelengths respectively. The 3-dB small signal intrinsic bandwidth of the photodiode is above 1 GHz. This technology has been used to implement an optical receiver IC for CD, DVD, and Blue-Laser optical data storage applications [Stu04], [Stu05]. It includes a new architecture of high-speed and low-noise variable gain transimpedance ampliﬁers with current preampliﬁer input. The ampliﬁer transimpedance gain is programmable over a range of 130 Ω to 270 kΩ by a serial interface. The ampliﬁer small-signal bandwidth is 260 MHz for the highest gain, which gives a transimpedance-bandwidth product of 70 THzΩ. A redesign of this chip with some new developments is presented in [Sei05]. The obtained improvements are a reduction of the power consumption, the die area, the oﬀset voltage, an increase of the sensitivity, 1.5 V output swing and a drive capability of a 10 pF/10 kΩ output load. An overall transimpedance of 465 kΩ leads, with the responsivity of the photodiode, to a sensitivity of 186 mV/µW for 660 nm light with a 3-dB bandwidth of 145 MHz. Compared

34

3 Standard CMOS Photodiodes

with the previous IC, sensitivity is improved by a factor of 1.8, while bandwidth is decreased by the same factor. The same technology has been used to implement OEIC’s for high-speed optical interconnects between or within electronic systems. The wavelength region of interest now is 600 nm to 850 nm. In [Swo03] an optical receiver with a maximum possible data rate of 1.8 Gbit/s is presented. This is achieved by using a bias voltage of 17 V (instead of the supply voltage of 5 V) at the cathode of the photodiode, to increase the electric ﬁeld strength in the intrinsic region and enhance the diode speed performance. Using 670 nm light, a sensitivity of −21.9 dBm for a BER of 10−9 is measured. The next step is to integrate a voltage-up-converter (VUC) with the OEIC, which generates onchip the higher cathode voltage from the 5 V supply voltage. This is presented in [Swo04], where the VUC produces a voltage of 11 V and improves the bandwidth of the OEIC from 1.5 GHz to 2.4 GHz. For a data rate of 3 Gbit/s and a BER of 10−9 , a sensitivity of −24.3 dBm at a wavelength of 660 nm is obtained. In [Swo05], measurement results at 4 Gbit/s and 5 Gbit/s are added. Finally, [Swo06] presents a 11 Gbit/s integrated receiver for 850 nm wavelength. A reverse photodiode voltage of 17 V extends the diode 3dBfrequency to 2.2 GHz. To enable high-speed data reception above 4 Gbit/s, the frequency response of the diode must be corrected with the help of an analog equalizer, ﬁrst introduced by [Rad04]. At 11 Gbit/s a minimum optical power of −8.9 dBm is needed for a BER of 10−9 . 3.3.2 SOI Implementations Silicon on Insulator (SOI), developed by IBM, is a chip-making technology that builds transistors on a very thin layer of silicon, improving chip performance and reducing power consumption. A thin, insulating layer, such as silicon oxide or glass, is placed between the thin layer of silicon and the silicon substrate. This process helps to reduce the amount of electrical charge that a transistor has to move during a switching operation, thus making it faster and allowing it to switch using less energy. SOI chips can be as much as 15 percent faster and use 20 percent less power than today’s bulk CMOS-based chips. SOI chips tend to cost more than their standard silicon counterparts, so SOI has been primarily used for high-end applications [Fre]. Photodetectors implemented in a thin SOI layer might be attractive, because light with a long wavelength (and long penetration depth) generates carriers in the silicon substrate wafer, which is isolated from the device SOI layer by the buried oxide. Therefore, SOI avoids the slow diﬀusion current known from photodiodes in bulk silicon. In [Csu02], the optical receiver is manufactured on 2 µm thick SOI substrates with a high resistivity. The thickness of the SOI is chosen to achieve a compromise between quantum eﬃciency and bandwidth for the photodiodes. The receiver is implemented in a 130 nm CMOS process ﬂow. The n- and p-type regions of the lateral interdigitated

3.3 Overview of Published Integrated Photodiodes

35

PIN diode is formed by standard nMOS and pMOS drain and source implantations. A sensitivity of −10.9 dBm is obtained for a bitrate of 5 Gbit/s at a BER of 10−9 . In [Yan03], the same photodiode is wire-bonded to a 10 Gbit/s SiGe TIA that was fabricated in a 0.18 µm BiCMOS technology. By applying a higher reverse voltage, the photodiode operates in avalanche gain mode. Owing to impact ionization, photocurrent gain is observed. For a bias voltage > 20 V, the 3-dB optical bandwidth is greater than 8 GHz. The complete receiver achieves a sensitivity of −6.9 dBm (BER < 10−9 ) at 10 Gbit/s. 3.3.3 CMOS Implementations As will become clear in the next sections, the main limitations of standard submicron CMOS photodiodes are caused by the diﬀusing substrate carriers. Many attempts exist in literature to overcome this problem. In [Ing04], the relative part of the drift current to the total current is optimized by using the side-wall capacitance of the n-well p-substrate junction. Although the corresponding depletion region is thin too, its depth perpendicular to the surface is larger compared to the depth of the bottom-plate capacitance. The major disadvantage of this approach is the limited photodiode’s responsivity due to the overhead required to connect the diode. Measurements on the side-wall photodiode have been done with a 650 nm LED as light source. With the network analyzer, a ﬂat response is obtained up to approximately 40 MHz. This pole would be caused by the LED rather than by the integrated photodiode. A ﬁrst breakthrough in the integration of high-speed submicron CMOS photoreceivers was presented by [Woo98]. The 0.35 µm receiver integrates a photodiode, preampliﬁer, digital logic, and oﬀ-chip driver. The n-well region in which the detector was made measures 16.54 µm x 16.54 µm, and is surrounded by a grounded p+ guard ring. Inside the n-well an interdigitated network of p-diﬀusion ﬁngers forms the active terminal of the detector. The photodetector responsivity, using 850 nm light, ranges from 0.01 A/W to 0.04 A/W near junction breakdown (10 V). Under these bias conditions and at a bitrate of 1 Gbit/s, a BER of 10−9 is obtained with an average optical input power of −6.3 dBm. Another way to circumvent the problem of diﬀusing substrate carriers is proposed by [Roo00]. The spatially modulated light (SML) detector consists of a row of rectangular p− -n junctions (ﬁngers) alternatingly covered and noncovered with a light blocking metal. The masked ﬁngers connected together form the deferred detector. The other ﬁngers connected together form the immediate detector. When a light pulse is incident on the detector, carriers are generated below the immediate zone and not below the masked deferred zone. The photo-generated carriers are spatially modulated. The immediate detector “immediately” detects the shallow-generated carriers. The bulk-generated carriers diﬀuse in all directions and most of them will ﬁnally reach a detector

36

3 Standard CMOS Photodiodes

junction (as well in the deferred as in the immediate zone). If the response of the deferred detector is subtracted from the response of the immediate detector, a fast response is achieved as the inﬂuence of the slow diﬀusing carriers is cancelled. This SML-detector is integrated with a low-oﬀset receiver in a 0.6 µm standard CMOS technology [Roo00]. The sensitivity at a BER of 10−9 is −18 dBm (λ = 860 nm) for 250 Mbit/s. A later realization in a 0.25 µm CMOS technology [Roo01] achieves, at 700 Mbit/s, a BER of 10−12 for the same input power. The receiver with SML-detector proposed by [Jut05] is integrated in an unmodiﬁed 0.18 µm CMOS technology. At 2 Gbit/s and using 850 nm light, the sensitivity equals −8 dBm at a BER of 10−9 . A totally diﬀerent approach to enhance the speed of integrated CMOS detectors is introduced by [Rad04, Rad05]. Not the n-well photodiode topology is changed, but a clever circuit solution is proposed. Following device simulations, the overall intrinsic photodiode frequency response shows a slow decay starting in the low MHz range. The roll-oﬀ in the overall photocurrent response is only about 5 dB/decade for frequencies between roughly 10 MHz and the lower GHz range. So the signals from the photodiode are low bandwidth (MHz range) but still relatively strong at very high frequencies (GHz range). Therefore an analog equalizer is introduced that compensates (in gain and phase) for the diode photocurrent roll-oﬀ in the range from 1 MHz to 1 GHz. Because no photogenerated carriers are drained away or subtracted from each other, the author claims there is no sensitivity or responsivity penalty. This results in a measured 3 Gbit/s data rate with a low BER (< 10−9 ) at −19 dBm 850 nm optical input power. 3.3.4 Conclusions The main focus in this literature overview lies on the performance of the photodiodes and the overall speed/sensitivity performance of the optical receivers that they are part of. One important conclusion is that, to the present day, there exists no uniform way to measure and report the characteristics of the opto-electrical receiver. For instance, [Stu05] and [Sei05] express the sensitivity in mV/µW (which is simply the product of responsivity and transimpedance gain). On the other hand, the sensitivity in for example [Swo04] is the minimum average optical input power needed to achieve a BER of 10−9 . Also the use of diﬀerent wavelengths makes a fair comparison more diﬃcult (the BiCMOS implementations mostly use 660 nm light, while the CMOS implementations almost all apply 850 nm light). Finally the speed of the receiver is expressed in diﬀerent ways: some authors (like [Stu05], [Sei05]) emphasize the bandwidth of the amplifying circuit, while others focus on the bitrate of the received data (like [Roo00], [Rad05]). However, the general trends which can be concluded from this overview are: • The photodiodes implemented in BiCMOS achieve the best performance. The main reason is that the technology used in for example [Stu05, Swo06]

3.4 One-Dimensional Model

37

is enhanced to ameliorate both responsivity and intrinsic speed of the photodiode. A higher performance is achieved at the expense of a more expensive technology. • SOI does not oﬀer large advantages over CMOS: comparing [Csu02] with [Rad05], the ﬁrst achieves higher bitrates (5 Gbit/s versus 3 Gbit/s), but the latter has a better sensitivity (−19 dBm versus −10.9 dBm, both for a BER of 10−9 ). • The main challenge in standard CMOS remains the realization of a photodiode with a high intrinsic speed, combined with a large responsivity. This trade-oﬀ will be worked out in more detail in the following sections. Several approaches, like [Roo00] and [Rad05] have increased the intrinsic speed so that the speed performance becomes comparable to the performance of the BiCMOS detectors. However, the sensitivity of the latter ones remains unbeatable.

3.4 One-Dimensional Model In this section, a one-dimensional model is developed to analyze the light detection performance of standard CMOS junctions. It is based on the basic equations of semiconductor physics [Ove98]. The model helps to gain insight in the basic working principles, but should also be treated with care, as it is only a one-dimensional model. To interpret the analytical results, the parameters of a 90 nm CMOS technology are used. The principles and major conclusions of this model have been published in [Her03]. 3.4.1 N-Well P-Substrate Junction The current of this photodetector is composed of a drift current originating from the carriers generated inside the depletion region (or space charge region SCR), an electron diﬀusion current from electrons generated in the psubstrate, and a hole diﬀusion current from holes generated in the n-well. To characterize the magnitude and speed of the total current step response, the concentration of the minority carriers in n-well and p-substrate has to be calculated ﬁrst. Fig. 3.4 shows a schematic representation of the one-dimensional model. Diﬀusion of Holes in the N-Well The continuity equation of the holes in the n-well, which is a non-homogeneous partial diﬀerential equation, is given by: ∂ 2 p(x, t) p(x, t) − p0 ∂p(x, t) = Dp − + αΦe−αx . ∂t ∂x2 τp

(3.8)

38

3 Standard CMOS Photodiodes

0

11111111111111111111111111111111 00000000000000000000000000000000 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111

p−substrate

n−well

000 111 000 111

SCR

L nw L scr

Lb x

Fig. 3.4. One-dimensional model of the n-well p-substrate junction.

Following list gives an explanation of all variables: x depth t time p hole concentration p0 initial hole concentration Dp hole diﬀusion constant τp hole minority carrier lifetime α absorption coeﬃcient of light in Si Φ photon ﬂux According to (3.8), the carrier concentration within an elementary volume can only change as a function of time if there is a diﬀerence between the incoming and outgoing carrier ﬂuxes (due to diﬀusion currents, ﬁrst term), or a net recombination (second term) or generation (third term). The boundary and initial conditions are: p(x = 0, t) = p0 ,

(3.9)

p(x = Lnw , t) = 0, p(x, t = 0) = p0 .

(3.10) (3.11)

The boundary equation (3.9) states that at the surface (x = 0), the concentration equals the initial concentration p0 . This assumption has been made for simplicity, as in reality impurities at the oxide-silicon interface create interface states and a netto recombination. At the edge of the space charge region (x = Lnw ) carriers are swept away, so the minority carrier concentration equals zero (3.10). When no light penetrates the junction, condition (3.11) deﬁnes that the hole concentration equals the initial concentration p0 .

3.4 One-Dimensional Model

39

To solve the mathematical problem of (3.8), the non-homogeneous partial diﬀerential equation is split up in a homogeneous partial diﬀerential equation and a non-homogeneous ordinary diﬀerential equation, which are mathematically easier to handle. The solution p(x, t) is separated in a time-independent part v(x) and a time-dependent part w(x, t): p(x, t) = v(x) + w(x, t).

(3.12)

The solution of (3.8), which describes the variation of the holes in the n-well with respect to depth and time, is thus given by: αΦ e−αx Dp α2 − 1/τp x −x + Ap exp + Bp exp Dp τp Dp τp

∞ kπx k 2 π 2 Dp 1 + Cp (k) sin + exp − t . Lnw L2nw τp

p(x, t) = p0 −

(3.13)

k=1

Ap , Bp and Cp (k) are constants which can be determined by solving the boundary and initial conditions (3.9)–(3.11). The hole diﬀusion current as a function of time is proportional to the gradient of the minority carrier concentration at the edge of the space charge region: ∂p , (3.14) Jdif f p = −qDp ∂x x=Lnw

where q is the elementary charge and Dp the hole diﬀusion constant. Diﬀusion of Electrons in the P-Substrate The continuity equation of the electrons in the p-substrate is similar to (3.8) and given by: ∂n(x, t) ∂ 2 n(x, t) n(x, t) − n0 = Dn − + αΦe−αx . ∂t ∂x2 τn Following list gives an explanation of all variables: x depth t time n electron concentration n0 initial electron concentration Dn electron diﬀusion constant τn electron minority carrier lifetime

(3.15)

40

3 Standard CMOS Photodiodes

α absorption coeﬃcient of light in Si Φ photon ﬂux The boundary and initial conditions now are: n(x = Lscr , t) = 0, n(x = Lb , t) = n0 , n(x, t = 0) = n0 .

(3.16) (3.17) (3.18)

The ﬁrst boundary condition (3.16) declares that the concentration equals zero at the edge of the space charge region (x = Lscr ). At distance x = Lb , the photo-generated minority carriers which are diﬀusing have negligible eﬀect on the equilibrium minority carrier concentration n0 , which results in condition (3.17). Lb depends both on lifetime of the diﬀusion carriers and the penetration depth of light in the material. At the initial state, there is no light input, so the concentration equals the initial concentration n0 (3.18). The solution of this non-homogeneous partial diﬀerential equation (3.15) is found in an analogue way as for the holes, and the solution is given by: αΦ e−αx Dn − 1/τn

x −x + Bn exp √ + An exp √ Dn τn Dn τn

∞ kπ(x − Lscr ) k 2 π 2 Dn 1 + Cn (k) sin + t . exp − (Lb − Lscr ) (Lb − Lscr )2 τn

n(x, t) = n0 −

α2

k=1

(3.19) An , Bn and Cn (k) are constants which again can be determined by solving the boundary and initial conditions (3.16)–(3.18). Like (3.14), the electron diﬀusion current as a function of time is proportional to the gradient of the minority carrier concentration at the edge of the space charge region: ∂n , (3.20) Jdif f n = qDn ∂x x=Lscr

where q is the elementary charge and Dn the electron diﬀusion constant. Drift in the Space Charge Region The drift current in the space charge region is given by: x=Lscr G(x)dx, Jdrif t = q

x=Lnw x=Lscr

=q x=Lnw

αΦe−αx dx.

(3.21)

3.4 One-Dimensional Model

41

G(x) is the generation term due to penetrating light with ﬂux Φ and absorption coeﬃcient α, which also appears in continuity equations (3.8) and (3.15). Lscr − Lnw is the width of the space charge region and determined by: 2Si NA + ND (Vbi − VR ). (3.22) Lscr − Lnw = q NA ND NA is the concentration of acceptors in the p-substrate, ND is the concentration of donors in the n-well, Si is the permittivity of Si, q is the elementary charge, Vbi is the technology-dependent built-in voltage and VR is the reverse voltage of the junction. The space charge region becomes wider when doping concentrations are lowered or when the reverse voltage VR is increased. Graphical Representation of the Results After derivation of the mathematical equations, it is time to visualize and interpret the results. The diode, with the cross section of Fig. 3.4, has an area of 100 µm x 100 µm and is illuminated with a step input of 1 µW. The minority carrier lifetimes in the n-well and in the p-substrate are assumed to be 1 µs. To investigate the inﬂuence of wavelength, two diﬀerent wavelengths are applied: 600 nm and 800 nm. This directly inﬂuences the absorption coeﬃcient α as well as the initial light ﬂux Φ0 . For red 600 nm light, α equals 5000 cm−1 and Φ0 corresponds to 3 · 1016 photons/(cm2 · s). When infrared 800 nm light is applied, α drops to 1000 cm−1 while Φ0 becomes 4 · 1016 photons/(cm2 · s). The reverse voltage over the junction is only 0.5 V, which is half the available power supply in a 90 nm CMOS technology. Fig. 3.5 shows the concentration of minority carriers in the n-well and p-substrate versus time and depth into the substrate. The inﬂuence of wavelength is clear: a longer wavelength results in a larger penetration depth 1/α, and more carriers which are generated in the substrate. In Fig. 3.5(a), the maximum of the electron concentration is 2.1 · 1011 cm−3 at 7 µm, while in Fig. 3.5(b) the maximum equals 1.7 · 1012 cm−3 at 17 µm. The maximum of the hole concentration lies in both cases at one half of the n-well depth (Lnw /2) and equals 1.6 · 1011 cm−3 respectively 5.7 · 1010 cm−3 . The large discrepancy between electron and hole maxima explains why the hole concentration is hardly visible in Fig. 3.5(b). The slowly varying gradient of the electron concentration in the substrate determines the gradually rising diﬀusing current Jdif f n . As depicted in Fig. 3.6, this current is the major part of the total current, but as expected the eﬀect is more pronounced when longer wavelengths are used. According to this model, the responsivity of the diode is 0.32 A/W and the rise time is 19 ns when red light is applied. For infrared light, the responsivity equals 0.44 A/W while the rise time is as high as 260 ns. The relative contribution of drift current Jdrif t and hole diﬀusion current Jdif f p is much smaller in the latter case. So the larger the wavelength, the larger the absorption depth in

42

3 Standard CMOS Photodiodes

11

x 10 −3

concentration [cm ]

2.5 2 1.5 1 0.5 0 200 4 100 time [ns]

2 0 0

−3

x 10

x [cm]

(a)

12

x 10 −3

concentration [cm ]

2 1.5 1 0.5

0 1000 6

500

4

time [ns]

0 0

−3

x 10

2 x [cm]

(b) Fig. 3.5. Minority carrier concentration in n-well p-substrate junction: (a) λ=600 nm, (b) λ=800 nm.

silicon, the more carriers are generated in the substrate and the slower the time response. But the smaller the wavelength, the higher the energy per photon (3.1). For the same input power, less photons penetrate the substrate and the responsivity is lower. Gigabit operation is not yet possible with this kind of rise times, but the more accurate two-dimensional model will show that things are not as bad as they seem at this stage.

3.4 One-Dimensional Model

43

3.5

2

current density [mA/cm ]

3 2.5

maximal current density =3.2mA/cm2

2 1.5 J

diffn

1

Jdiffp

0.5

Jdrift t

0 0

0.9

Jtot

=19 ns

50

100 time [ns]

150

200

(a) 4.5

2

current density [mA/cm ]

4

2

maximal current density =4.4mA/cm

3.5 3 2.5 2 1.5

Jdiffn

1

Jdiffp t

0.9

0.5 0 0

200

Jdrift

=260 ns

Jtot 400 600 time [ns]

800

1000

(b) Fig. 3.6. Current densities in n-well p-substrate junction: (a) λ=600 nm, (b) λ=800 nm.

3.4.2 P+ N-Well Junction with Guard The previous simulations have shown that the diﬀusing substrate carriers are a problem for high-speed operation, certainly when infrared light is used. One way to overcome this problem is to consider the p+ n-well junction together with the n-well p-substrate junction. If the former is used to detect the signal, the substrate contacts can act as guard to draw away the slowly diﬀusing

44

3 Standard CMOS Photodiodes 1111111111111111111111111111111 0000000000000000000000000000000 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111

1111111111111111111111111111111 0000000000000000000000000000000 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111

p−substrate

p +region

111 SCR 000 n−well000 111

Fig. 3.7. One-dimensional model of the p

+

0 L sd L scr1 L nw L scr2

x

n-well junction with guard.

signals carriers in the substrate. The resulting diode response will be smaller, but also a lot faster. This idea has also been implemented successfully in [Woo98]. The performance of this diode has been analyzed using the same physical equations ((3.8) to (3.22)), but now there are three diﬀusion currents and two drift currents. All parameters are the same as in the previous model, and the minority carrier lifetime in the p+ region is assumed to be 0.1 ns due to the very high doping concentration in this region. A cross section of this structure is depicted in Fig. 3.7. Electrons are diﬀusing in the p+ region and in the psubstrate, and they give rise to the currents Jdif f n1 and Jdif f n2 . The diﬀusing holes in the n-well generate the current Jdif f p . Carriers generated in the very shallow space charge region between the p+ region and the n-well will form the small drift current Jdrif t1 . Jdrif t2 , which is somewhat larger, stems from the light generated carriers in the wider space charge region between n-well and p-substrate. The light wavelength is 600 nm, and the reverse voltage over both junctions is 0.5 V. An important question for this model is: which currents will be picked up by which contacts? In a practical implementation, three electrode contacts are present: one for the p+ region, one for the n-well, and one for the p-substrate. The current at the n-well electrode equals the sum of the currents at the electrodes of the p-type regions. The current at the substrate contact consists of the substrate diﬀusion current Jdif f n2 , drift current Jdrif t2 and one part of the n-well diﬀusion current Jdif f p . Equivalently, the current at the p+ region contact is made up of the p+ region diﬀusion current Jdif f n1 , drift current Jdrif t1 and the other part of the n-well diﬀusion current Jdif f p . In this one dimensional model, we assume an equal probability for the light-generated holes in the n-well to be trapped by either of the space charge regions. So one half of Jdif f p is collected by the substrate contacts, and the other half by the p+ region contacts. This simpliﬁcation is true if the carriers inside the n-well

3.4 One-Dimensional Model

45

11

x 10 −3

concentration [cm ]

2.5 2 1.5 1 0.5 0 200 4 100

2 0 0

time [ns]

−3

x 10

x [cm]

(a) 4

2

current density [mA/cm ]

2

3.5 t =13 ns 0.9

max current density =3.5mA/cm

3 Jdiffn1

2.5 2

max current density

Jdiffp

with guard =0.9mA/cm2

Jdiffn2

1.5 t =1.5 ns 0.9

Jdrift1 Jdrift2

1

Jtot1

0.5

J

tot2

0 0

10

20

30 time [ns]

40

50

60

(b) Fig. 3.8. (a) Minority carrier concentration and (b) current densities in p+ n-well junction with guard, λ=600 nm.

are uniformly distributed. However, in reality, the light ﬂux is determined by Lambert-Beer’s Law (3.3) and the light-generated carriers inside the n-well have a decreasing exponential distribution. The results are depicted in Fig. 3.8. Fig. 3.8(a) shows that the concentration of minority carriers in the substrate is very similar to the simple n-well diode: the maximum lies at 7 µm and equals 2.1 · 1011 cm−3 . The maximum minority concentration in the n-well is 1.1 · 1011 cm−3 , while the maximum

46

3 Standard CMOS Photodiodes

concentration in the p+ region is only 5.6 · 108 cm−3 . This last region is not visible in the plot, as the minority concentration is low and the region is very shallow compared to the other regions. All current densities in this structure are depicted in Fig. 3.8(b). The duration of the step input is 200 ns, but to focus on the most interesting data, only the ﬁrst 60 ns are shown. If the two junctions were placed parallel, the resulting performance is comparable to the performance of the simple n-well p-substrate junction. The responsivity is 0.35 A/W and the rise time equals 13 ns. But if the substrate carriers are eﬀectively removed by the substrate contacts, the rise time is only 1.5 ns. The price to pay is a drop in responsivity, which is now only 0.09 A/W. By applying a one dimensional analysis, this example shows that using the appropriate diode structure can alleviate the problem of the diﬀusing minority carriers in the substrate. Also the trade-oﬀ between sensitivity and speed, which will reappear several times in this work, is demonstrated for the ﬁrst time. However, as junctions are located closer to the surface and the side-wall capacitances become more and more important, a more accurate two-dimensional model is needed. This will be discussed in the next section.

3.5 Two-Dimensional Model A two-dimensional analysis of diﬀerent photodiode topologies is performed with the device simulation program Medici [Syn]. It is a powerful tool that can be used to simulate the behavior of MOS and bipolar transistors, and other semiconductor devices (such as diodes). It models the two-dimensional distributions of potentials and carrier concentrations in a device. A number of physical models are incorporated into the program for accurate simulations, including models for recombination, photogeneration, mobility and lifetime. The optical Device Advanced Application Module is used to model propagation of light inside and outside a device. This section discusses three photodiode structures implemented in a 0.18 µm standard CMOS technology: the classical n-well diode, the p+ n-well diode with guard and the diﬀerential diode. Also the inﬂuence of changing the light wavelength is studied. Finally, the eﬀect of technology downscaling on the photodiode performance is investigated. Most of these results have been presented in [Her03, Her04b, Her06a]. 3.5.1 Classical N-Well Diode Fig. 3.9 shows a schematic representation of the simulated n-well diode. As a multimode ﬁber has a core diameter of 50 µm or 65 µm, the dimensions of the diode are 80x80 µm2 . This could be implemented as one large n-well region, or several smaller parallel n-well regions separated by substrate contacts to minimize substrate resistance. The amount of squares per diode side is given

3.5 Two-Dimensional Model

80 μm, Ns squares

80 μm, Ns squares

anode

cathode

47

anode

p−substrate

n−well

p +region

n +region

Fig. 3.9. Schematic representation of the simulated classical n-well diode, left: topview, right: cross-section.

by Ns , and the inﬂuence on both responsivity and speed is investigated. On top of the structure are ohmic contacts (at anode and at cathode), and the contacts are separated by a 1 µm thick oxide layer. For simplicity, the rest of the dielectric stack is omitted. At the silicon-oxide interface, a surface recombination rate of 0 cm/s is supposed, corresponding to the ideal values of an insulator interface. All doping proﬁles used for simulations are constant proﬁles, except for the n-well. For this region, a retrograde well doping proﬁle is taken into account. This is a proﬁle where the highest dopant concentration is located at a certain distance from the surface, while the concentration towards the Si/SiO2 interface becomes lower. It is needed in modern submicron technologies to improve short channel characteristics and increase surface mobility. Although essential for the performance of short channel transistors, the retrograde well proﬁle also inﬂuences the optical performance of the n-well p-substrate junction. By changing the doping proﬁle in the channel region, an electric ﬁeld is created near the surface, which counteracts the electrical ﬁeld of the space charge region. As a result, the photogenerated carriers are less accelerated, resulting in a slower response. As the retrograde well proﬁle is located near the surface, this eﬀect is more pronounced when light with a short wavelength and small penetration depth is used. So the negative eﬀect of the retrograde proﬁle compared to a constant proﬁle is more dominant for blue light than for infrared light. The simulation results for a 0.18 µm CMOS technology are summarized in Fig. 3.10 and Table 3.1.The maximum supply voltage is 1.8 V, and the reverse voltage over the diode is 1 V. The wavelength of light equals 850 nm. These parameters, as well as the photodiode area, will be the same for the next two simulated diode topologies. As Medici is a two-dimensional tool, not only bottom-plate, but also sidewall junctions are taken into account. This is the main reason why the simulation results of the one-dimensional model and the two-dimensional model

48

3 Standard CMOS Photodiodes

responsivity (A/W)

0.35

Ns=4

0.3

Ns=6

0.25

Ns=8

0.2

Ns=12

0.15

Ns=14

N =10 s

0.1 0.05 0 0

0.5

1 time (μs)

1.5

2

norm. gain (dB)

(a) 0 −20

Ns =4 Ns =6

−40 6

phase (degrees)

10

7

8

10 10 frequency (Hz)

9

10

10

10

Ns =8 Ns =10

180

Ns =12 Ns =14

135 90 6

10

7

8

10 10 frequency (Hz)

9

10

10

10

(b) Fig. 3.10. Classical n-well diode simulation results: (a) responsivity, (b) normalized intrinsic frequency characteristic. Ns corresponds to the number of squares per diode side.

diﬀer slightly in responsivity, but greatly in speed performance. Owing to the extra electric ﬁeld regions of the side-wall junctions, the intrinsic photodiode speed becomes better in the two-dimensional model. The responsivity R varies between 0.33 A/W-0.29 A/W and turns out to be slightly dependent on the amount of squares. The higher Ns , the more useful area is taken by the substrate contacts, the smaller R. The speed performance of the photodiode is characterized by its intrinsic 3-dB bandwidth f3dB . It is mainly determined by the diﬀusing carriers in the substrate and independent of layout topology. The simulated value equals 10 MHz. Leaving technology diﬀerences aside, this value should be compared with the value found in the analytical model: a 90 percent rise time of 260 ns for infrared light corresponds in

3.5 Two-Dimensional Model

80 μm, Ns squares

80 μm, Ns squares

49

cathode cathode guard anode guard

p−substrate

n−well

p +region

n +region

Fig. 3.11. Schematic representation of the simulated p+ n-well diode with guard, left: top-view, right: cross-section.

a classical one-pole system to an intrinsic 3-dB bandwidth of 1.3 MHz. The value of 10 MHz is considered to be more accurate, as the contribution of the side-wall junctions is included. These orders of magnitude correspond to the values reported by other authors (a 3-dB bandwidth of 4 MHz for a 0.25 µm technology [Gen01] and a ‘cut-oﬀ frequency’1 of 1 MHz for a 0.18 µm technology [Rad05]). The low-frequency roll-oﬀ (< 50 Mz) is independent of Ns and equals roughly 5 dB/decade. Note that this value is quite diﬀerent from the slopes found in classical electronic systems, where one or multiple RCconstants determine a slope of 20 dB/decade, 40 dB/decade, etc. The system under study is not determined by some discrete R’s or C’s, but by the distributed eﬀect of carriers in n-well, depletion region and p-substrate. 3.5.2 P+ N-Well Diode with Guard As already discussed in Section 3.4.2, eliminating the substrate carriers from the total signal would make the diode response a lot faster. This idea is implemented in the p+ n-well diode with guard, shown schematically in Fig. 3.11 [Woo98]. The basic diode structure is the same as the one of the classical n-well diode, only now a p+ region is embedded in the n-well region. The amount of n-well regions is again given by Ns . The active junction detecting the signal is now the p+ n-well junction. The substrate contacts act as a guard to remove the substrate carriers. This photodiode is capable of high-speed operation, at the expense of a smaller responsivity. The simulation results regarding responsivity are shown in Fig 3.12(a). On top, for Ns = 4 to Ns = 14, the responsivity is shown if the p+ region and p-substrate were placed parallel. These results are slightly smaller (due to the extra interconnect overhead) compared to the classical n-well diode. The responsivity if the substrate contacts act as a guard, is approximately 1

The cut-oﬀ frequency is deﬁned in [Rad05] as the frequency at which the DC and ac asymptotes of the total photodiode response cross.

50

3 Standard CMOS Photodiodes 0.3

Ns=4 Ns=6

responsivity (A/W)

0.25

Ns=8 0.2

N =10 s

Ns=12

0.15

Ns=14

0.1 0.05 0 0

0.5

1 time (μs)

1.5

2

norm. gain (dB)

(a) 0 −20

Ns =4 Ns =6

−40 6

phase (degrees)

10

7

8

10 10 frequency (Hz)

9

10

10

10

Ns =8 Ns =10

0

Ns =12 Ns =14

−45 −90 6

10

7

8

10 10 frequency (Hz)

9

10

10

10

(b) Fig. 3.12. p+ n-well diode simulation results: (a) responsivity (upper curves: p+ n-well junction and p-substrate n-well junction in parallel, lower curves: p+ n-well junction with p-substrate guard), (b) normalized intrinsic frequency characteristic of the p+ n-well diode with guard. Ns corresponds to the number of squares per diode side.

ten times smaller (0.023 A/W for Ns = 4 ), as shown in the same ﬁgure and summarized in Table 3.1. On the other hand, as depicted in Fig. 3.12(b), the intrinsic 3-dB bandwidth is 100 times larger (1 GHz) and again independent of Ns . The frequency roll-oﬀ is also independent of Ns up to a few GHz. The slope is slightly larger compared to the frequency slope of the classical n-well diode: approximately 8 dB/decade instead of 5 dB/decade. These results diﬀer slightly from the one-dimensional analytical model, where red light instead of infrared light was applied. Probably the assumption that one half of the diﬀusing holes in the n-well is collected by the substrate

3.5 Two-Dimensional Model

51

contacts, and the other half by the p+ region contacts, is not correct when the two-dimensional problem is considered. The side-wall space charge region of the n-well plays a non-negligible roll, because the n-well extents much deeper into the substrate than the p+ region. As a result, the major part of the n-well diﬀusion current is picked up by the side-wall space charge region between n-well and p-substrate. Compared to the one-dimensional model, the responsivity in this model drops (from 0.09 A/W to ≤0.023 A/W). The speed improvement found in the one-dimensional model is only a factor of 10 (Fig. 3.6(a) and Fig. 3.8(b): the rise time drops from 19 ns to 1.5 ns). The two-dimensional model is more realistic, as the fast response of the side-wall junctions is included, although the speed improvement by a factor of 100 might be rather optimistic. 3.5.3 Diﬀerential N-Well Diode Another way to increase the diode bandwidth is to use a diﬀerential nwell diode. It is based on the same physical principles as the SML-detector in [Roo00]. As depicted in Fig. 3.13, the diﬀerential n-well diode consists of an alternating pattern of illuminated and dark junctions. The latter ones are covered with metal to block the light. This diode also features substrate contacts alternating the junctions, again to minimize substrate resistance. When light falls on this diode, carriers are generated below the illuminated junctions and not below the dark junctions. The substrate carriers generated close to an illuminated junction will have a higher probability to reach this junction than to reach one of the neighboring dark junctions. Those generated deep in the substrate will require a long time to reach a junction and have more or less equal probability to reach an illuminated or dark junction. If the response of the dark junctions is subtracted from the response of the illuminated junctions, a fast response is achieved as the inﬂuence of the slowly diﬀusing carriers is cancelled. Medici simulations have been performed using the amount of ﬁngers, Nf , as parameter. Rlight , theresponsivity of the illuminated junctions, is less than one half of the responsivity of the classical n-well diode (see upper curves in Fig. 3.14(a) and Table 3.1). This is because the same total area (80x80 µm2 ) is now taken by two diodes, the illuminated one and the dark one. The DC responsivity of the diﬀerential signal (Rlight − Rdark ) varies between 0.10 A/W and 0.076 A/W. This is approximately one half of the responsivity of the illuminated junctions (see lower curves in Fig. 3.14(a) and Table 3.1), but still more than 2 times larger than the responsivity of the p+ n-well diode with guard. More ﬁngers correspond to more interconnection overhead, and a slightly lower responsivity. The frequency characteristic of the diﬀerential diode is depicted in Fig 3.14(b). Its intrinsic 3-dB bandwidth ranges from 1 GHz to more than 4 GHz, and does depend on the amount of ﬁngers. More ﬁngers per diode means less distance for the diﬀusing carriers to bridge before they get detected, resulting in a faster response. These results are consistent

52

3 Standard CMOS Photodiodes Dark junction

Illuminated junction

111111111111111111111 000000000000000000000 111111111111111111111 000000000000000000000

p+ region

p−substrate

111111111111 000000000000 111111111111 000000000000

n−well

111 blocking metal 000 n+ region000 111

80 μ m

80 μ m, Nf fingers

1111 0000 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111

00000 11111 11111 00000 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111

00000 11111 11111 00000 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111

1111 0000 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111

Fig. 3.13. Schematic representation of the simulated diﬀerential n-well diode, bottom: top-view, top: cross-section.

with the results found in [Gen01]. For the simulated frequencies of interest, there is no region of constant roll-oﬀ . The slope at each f3dB equals 3 dB/decade, and rapidly rises to 10 dB/decade for frequencies above 10 GHz. These results show a trade-oﬀ between bandwidth and responsivity, and depending on the design goals, a proper choice of Nf has to be made. 3.5.4 Inﬂuence of Wavelength Up till now, all photodiode simulations have been carried out for a wavelength of 850 nm. This wavelength corresponds to the wavelength used for short-distance low-cost communication networks with multimode ﬁber. For the measurements described in Chapter 6 this wavelength will also be used. However, as described in Chapter 1, there are other low-cost applications where monolithic CMOS implementations should be considered. First there is the optical data storage, where three wavelengths are standardized: 780 nm (CD), 660 nm (DVD) and 405 nm (Blu-Ray Disc and HD-DVD). Second, not only multimode ﬁbers are used for short-distance communication, but also other kinds of ﬁbers, working at a diﬀerent optimal wavelength, might be of interest. For example, more and more cars are exploiting 650 nm plastic optical ﬁber (POF) for their in-vehicle networks. As there is such a wide variety of applications and standards, the inﬂuence of changing the wavelength is investigated.

3.5 Two-Dimensional Model 0.12

Nf=18 Nf=22

0.1 responsivity (A/W)

53

Nf=26 0.08

N =30 f

Nf=34

0.06 0.04 0.02 0 0

0.5

1 time (μs)

1.5

2

norm. gain (dB)

(a) 0 −10

Nf =18 Nf =22

−20

6

phase (degrees)

10

7

8

10 10 frequency (Hz)

9

10

10

10

Nf =26 Nf =30

180

Nf =34

135 90 6

10

7

8

10 10 frequency (Hz)

9

10

10

10

(b) Fig. 3.14. Diﬀerential n-well diode simulation results: (a) responsivity (upper curves: Rlight , lower curves Rlight − Rdark ), (b) normalized intrinsic frequency characteristic of the diﬀerential diode. Nf corresponds to the number of ﬁngers.

Fig. 3.15 shows the simulation results for the classical n-well diode. Three diﬀerent cases are considered: A. infrared light (850 nm), B. red light (650 nm) and C. blue light (400 nm). The responsivity, depicted in Fig. 3.15(a), shows the wavelength dependence of the energy per photon (3.1). The smaller the wavelength, the higher the energy per photon, the smaller the amount of photons which can generate carriers and consequently the smaller the responsivity. Notice that also the penetration depth in combination with the carrier minority lifetime determine responsivity. If the penetration depth is large (which is true for large wavelengths), a lot of carriers will be generated deep into the substrate, and will recombine before being detected. So although more photons are present for the same amount of energy, less useful electrons will

54

3 Standard CMOS Photodiodes Table 3.1. Simulated photodiode performance. p+ n-well diode with guard

classical n-well diode Ns R (A/W) 4 6 8 10 12 14

0.33 0.325 0.32 0.31 0.30 0.29

f3dB

10 MHz

Ns R (A/W) 4 6 8 10 12 14

0.023 0.021 0.019 0.017 0.015 0.013

f3dB

1 GHz

diﬀerential n-well diode Nf Rlight (A/W) Rlight − Rdark (A/W) f3dB 18 0.10 0.052 1 GHz 22 0.094 0.046 1.5 GHz 26 0.088 0.042 2.2 GHz 30 0.083 0.038 3.1 GHz 34 0.076 0.034 4.4 GHz

be collected due to recombination. This explains why the responsivities of infrared (850 nm) and red (650 nm) light are located close to each other, and can even interchange when small simulation parameters are modiﬁed. The normalized frequency response for the three wavelengths is shown in Fig 3.15(b). The smaller the wavelength, the smaller the penetration depth, the higher the relative contribution of the drift current, and thus the higher the 3-dB bandwidth. This results in a f3dB of 10 MHz for 850 nm light, 50 MHz for 650 nm light, and 75 MHz for 400 nm light. At lower frequencies, the slope is also wavelength dependent. For 850 nm light, the roll-oﬀ equals 5 dB/decade, while the rolloﬀ using smaller wavelengths is lower: 1.5 (dB/decade) for 650 nm light and 1 dB/decade for 400 nm light. At higher frequencies (> 100 MHz) the curves have equal slopes, but are shifted due to the higher bandwidth when shorter wavelengths are used. Around 100 MHz, the slope is steep, showing a roll-oﬀ of 15 dB/decade. Above 1 GHz, the steepness slows down and all curves have a slope of 5 dB/decade. At this frequency, the attenuation is larger than 15 dB for all wavelengths. The simulation results for the wavelength inﬂuence on the diﬀerential diode are depicted in Fig. 3.16. For this diode topology, the responsivity (Rlight − Rdark ) is the largest for 650 nm light, smaller for 400 nm light and the smallest for 850 nm light. Rlight has the same dependence on wavelength as the classical n-well diode described above. On the other hand, the smaller the wavelength, the smaller the penetration depth, the less diﬀusing carriers are generated,

3.5 Two-Dimensional Model

55

0.35 A B C

responsivity (A/W)

0.3 0.25 0.2 0.15 0.1 0.05 0 0

0.5

1 time (μs)

1.5

2

norm. gain (dB)

(a) 0 −20 −40

A B C 6

phase (degrees)

10

7

8

7

8

10 10 frequency (Hz)

9

10

10

10

180 135 90

A B C 6

10

10 10 frequency (Hz)

9

10

10

10

(b) Fig. 3.15. Classical n-well diode and inﬂuence of wavelength (A. infrared light (850 nm), B. red light (650 nm), C. blue light (400 nm)): (a) responsivity, (b) normalized intrinsic frequency characteristic.

so the smaller Rdark . For infrared 850 nm light, Rdark is approximately 50 % of Rlight . For red (650 nm) and blue (400 nm) light, Rdark is only 9 % resp. 2 % of Rlight . This eﬀect is also visible in the frequency characteristic: the speed performance of the 400 nm diﬀerential diode (f3dB = 240 MHz and a slope of 10 dB/decade) is worse than the speed performance of the 650 nm and 850 nm diﬀerential diodes (f3dB = 1 GHz and a slope of 3 dB/decade in both cases). So when no or only a few diﬀusing carriers are present in the substrate, a diﬀerential n-well diode topology is not the solution to enhance the diode speed performance with several orders of magnitude. Using blue light (400 nm), the substrate diﬀusing carriers are not the problem, but speed is limited by the diﬀusing carriers in the n-well itself. Although blue light

56

3 Standard CMOS Photodiodes 0.15

responsivity (A/W)

A B C 0.1

0.05

0 0

0.5

1 time (μs)

1.5

2

norm. gain (dB)

(a) 0 −10 −20

A B C 6

phase (degrees)

10

7

8

7

8

10 10 frequency (Hz)

9

10

10

10

180 135 90

A B C 6

10

10 10 frequency (Hz)

9

10

10

10

(b) Fig. 3.16. Diﬀerential n-well diode and inﬂuence of wavelength (A. infrared light (850 nm), B. red light (650 nm), C. blue light (400 nm)): (a) responsivity, (b) normalized intrinsic frequency characteristic.

with a short penetration depth into silicon is very attractive, further research is needed to optimize the speed performance inside the n-well. The simulations for these two diode topologies show that, when both responsivity and bandwidth are considered, the most optimal wavelength is 650 nm. For the classical n-well diode, the responsivity is comparable when using infrared 850 nm light, while the 3-dB frequency is larger. For the diﬀerential diode, responsivity as well as bandwidth are the best using red light. 3.5.5 Inﬂuence of Technology Scaling As dictated by Moore’s Law (the doubling of the number of transistors on integrated circuits every 18 months [Moo65]), the minimum size of a transistor

3.5 Two-Dimensional Model

57

continually reduces. During the research period of this work, the most widely used CMOS technology for analog design was the 0.18 µm CMOS technology. However, also 0.13 µm and 90 nm technologies were available. As 65 nm digital CMOS technologies are emerging, the inﬂuence of technology scaling on the diode performance should be considered. When technology size decreases, doping concentration levels increase to counteract the eﬀect of scaling on transistor characteristics (VT , leakage currents, etc.). Also, the available power supply drops to keep the electrical ﬁeld within limits. As a result, the width of space charge regions (eg. for the n-well p-substrate junction given by (3.22)) decreases. This will result in a smaller contribution of the drift current (3.21) to the total current. Fig. 3.17 shows the inﬂuence of downscaling on the optical performance of the classical n-well diode and the diﬀerential n-well diode. A 0.18 µm CMOS technology is compared with a 0.13 µm CMOS technology. Both responsivity and 3-dB bandwidth of the diodes become slightly worse when technology scales down. The low-frequency roll-oﬀ of the classical diode is 5 dB/decade for both technologies. The diﬀerential n-well diode does show some technology dependence: the slope is slightly steeper around f3dB for the smaller technology: 5 dB/decade compared to 3 dB/decade. Notice that the simulations for the diﬀerential diode were carried out for a ﬁxed amount of ﬁngers Nf . When minimal sizes are reducing, smaller nwell ﬁngers can be taken, resulting in a faster detector response. The eﬀect of having smaller ﬁngers is actually presented in Fig. 3.14(b), but only for the 0.18 µm technology. Moreover, as technology dimensions shrink, the area overhead needed for n-well and substrate contacts will become less. This will result in less area covered with light-blocking metal, and more eﬃcient area taken by photo-sensitive junctions. So despite all the drawbacks, technology scaling might have some advantages for integrated diﬀerential photodiodes. Finally, Table 3.2 draws attention to another important parameter which modiﬁes as a result of technology changes, namely the junction capacitance. As will become clear in Section 4.3.1, its value is inversely proportional to the bandwidth of the transimpedance ampliﬁer, and thus greatly inﬂuences the speed of the overall receiver. Due to doping concentration modiﬁcations (resulting in smaller depletion widths), the zero bias junction capacitance becomes higher. Especially the increase of the side-wall capacitance is remarkable: more than a factor of ten per unit meter. Table 3.2 also compares the total capacitance of the classical n-well diode and the diﬀerential n-well diode implemented in two diﬀerent technologies and reversely biased at one half of the respectively available power supply (1.8 V versus 1.2 V). For the diﬀerential diode, the capacitance of the illuminated junctions (equal to the capacitance of the dark junctions) should be considered, as the currents of these junctions are ampliﬁed separately. This value is approximately one half of the capacitance of the classical n-well diode, which is consistent with the occupied diode area. A technology change from 0.18 µm CMOS to 0.13 µm CMOS means roughly a 4 times increase of the n-well p-substrate junction

58

3 Standard CMOS Photodiodes 0.35 A B C D

responsivity (A/W)

0.3 0.25 0.2 0.15 0.1 0.05 0 0

0.5

1 time (μs)

1.5

2

norm. gain (dB)

(a) 0 −10 −20

A B C D 6

phase (degrees)

10

7

8

7

8

10 10 frequency (Hz)

9

10

10

10

180 135 90

A B C D 6

10

10 10 frequency (Hz)

9

10

10

10

(b) Fig. 3.17. Inﬂuence of technology scaling (A. classical n-well diode 0.18 µm, B. classical n-well diode 0.13 µm, C. diﬀerential n-well diode 0.18 µm, D. diﬀerential n-well diode 0.13 µm): (a) responsivity, (b) normalized intrinsic frequency characteristic.

capacitance. These values have to be taken into account during the transimpedance ampliﬁer design.

3.6 Conclusions This chapter was completely devoted to one single device: the photodiode. It has an important function in the optical receiver, as it is the interface between the optical and the electrical domain. Its speed and responsivity are of uttermost importance for the performance of the complete receiver chain. To understand the opto-electrical mechanisms, some deﬁnitions have been introduced ﬁrst. Next, to illustrate the feasibility of integrated silicon photo-

3.6 Conclusions

59

Table 3.2. Junction capacitance and technology scaling. 0.18 µm CMOS 0.13 µm CMOS Zero bias area junction capacitance 1.07 · 10−4 F/m2 2.17 · 10−4 F/m2 Zero bias side-wall junction capacitance 2.4 · 10−11 F/m 2.7 · 10−10 F/m total capacitance classical n-well diode (Ns = 10) total capacitance illuminated junctions diﬀerential n-well diode (Nf = 26)

428 f F

1.5 pF

210 f F

875 f F

detectors, some published BiCMOS, SOI and CMOS implementations have been discussed. The advantage of CMOS over the other technologies is a lower cost, making it the chosen technology for low-cost, high-volume mass applications. The light detection principles and carrier transport mechanisms involved in a pn-junction have been described both qualitatively and quantitatively using semiconductor physics. This one-dimensional model shows that the nwell p-substrate junction can be used to detect light, but the rise time for red light is only 19 ns. The speed can be enhanced using the p+ n-well junction, which is shielded from the diﬀusing substrate carriers by the n-well p-substrate junction. The improved rise time of 1.5 ns comes at the expense of a lower responsivity: 0.09 A/W compared to 0.32 A/W. A two-dimensional model has been developed to include the non-negligible eﬀect of side-wall junction capacitances. Also the retrograde well doping proﬁle has been taken into account. Depending on the amount of substrate contacts, the classical n-well diode has a responsivity ranging from 0.29 A/W to 0.33 A/W. The speed is mainly limited by the diﬀusing carriers in the substrate, and independent of the n-well layout topology. The photodiode 3dBbandwidth equals 10 MHz, while the low-frequency roll-oﬀ is 5 dB/decade. Two diode topologies to enhance the speed performance have been investigated using this two-dimensional model: the p+ n-well diode with guard and the diﬀerential n-well diode. For the ﬁrst topology, speed is again not much inﬂuenced by the amount of n-well squares, and the diode 3-dB bandwidth equals 1 GHz. For the latter diode, the amount of n-well ﬁngers does aﬀect bandwidth, which varies from 1 GHz (18 ﬁngers) to 4.4 GHz (34 ﬁngers). The diﬀerential diode is not only capable of higher bitrates, also the responsivity is better: for a simulated bandwidth of 1 GHz, the responsivity is 0.052 A/W for the diﬀerential diode versus maximum 0.023 A/W for the p+ n-well diode with guard. The two-dimensional results discussed above all reﬂect the photodiode performance for 850 nm light, used in short-distance communication networks. Because there exists a lot of low-cost applications using shorter wavelengths, the performance of the classical and diﬀerential diode has been studied using red (650 nm) and blue light (400 nm) . The light wavelength does inﬂuence

60

3 Standard CMOS Photodiodes

the optical performance, and red light turns out to be the most “optimal” wavelength concerning speed and responsivity. When blue light is used, the diﬀerential diode topology becomes pointless, as there are no diﬀusing carriers in the substrate which have to be compensated for. As Moore’s Law is still valid in the silicon nano-scaled technology, the consequences of the transition from a 0.18 µm to a 0.13 µm technology have been discussed. Due to higher doping levels and smaller supply voltages, the width of the space charge region becomes smaller, resulting in photodiodes with a slightly smaller responsivity, a lower 3-dB bandwidth and a higher capacitance value. The latter result will directly have impact on the transimpedance ampliﬁer design. Finally, an important conclusion concerning all the device simulations in this chapter is that there exists a trade-oﬀ between responsivity and speed. Depending on the system requirements and consequently the diode speciﬁcations, a proper design choice has to be made.

4 Transimpedance Ampliﬁer Design

4.1 Introduction The transimpedance ampliﬁer (TIA) is without a doubt the most critical building block of the optical receiver. It converts the current generated by the photodiode into an output voltage. The design of this block involves many trade-oﬀs between noise, bandwidth, gain and stability. This chapter tries to reveal all subtleties and challenges encountered during the design of low-noise high-bandwidth TIAs. A summary of the TIA speciﬁcations regarding transimpedance gain, bandwidth, noise and overload currents is given in Section 4.2. Section 4.3 tackles the design of a TIA with shunt-shunt feedback. Design equations are derived for the transimpedance gain, bandwidth, open-loop gain, loop gain and the noise performance. Implementations published in open literature are discussed in Section 4.4. Two main topologies are distinguished: the TIA with common-source input stage and the TIA with regulated cascode input stage. Also some interesting work presented at ISSCC is described. Finally, the designs of three diﬀerent TIAs, of which two are implemented in a 0.18 µm CMOS and one in a 90 nm CMOS technology, are explained more thoroughly in Section 4.5. These case studies clearly demonstrate the compromises to be made during the design of low-noise high-speed TIAs.

4.2 Performance Requirements This section presents the main performance requirements for a TIA: high transimpedance gain, high bandwidth, low noise and high overload current. Transimpedance Gain The transimpedance gain of the TIA, ZT IA , is deﬁned as the ratio of the small-signal output voltage to the small-signal input current: 61

62

4 Transimpedance Ampliﬁer Design

ZT IA =

vout = |ZT IA (f )|ejθ(f ) . iin

(4.1)

The higher this value, the more output signal is produced for a given input signal. The transimpedance gain is speciﬁed either in units of Ω or dBΩ. The value dBΩ is calculated as 20 · log10 (ZT IA /Ω). The transimpedance gain is a complex quantity, with frequency-dependent magnitude |ZT IA (f )| and frequency-dependent phase shift θ(f ). The transimpedance gain at low frequencies is usually ﬂat, and represented by ZT IA,0 . The ﬁrst reason for having a TIA with high gain is to create a signal with an amplitude large enough to drive the post-ampliﬁer (PA). But there is an additional reason which might be even more important: noise. As the TIA is the ﬁrst stage in the optical receiver (Fig. 2.1), the noise of the next stages like the PA will be suppressed by the TIA gain. So a lower transimpedance gain (for example to obtain a higher bandwidth (4.11)) cannot simply be exchanged for a larger post-ampliﬁcation. The total gain remains constant, but the total input-referred noise of the receiver will increase. Bandwidth The upper frequency at which |ZT IA (f )| (4.1) has dropped 3 dB below its DC value, is deﬁned as the TIA bandwidth, BWT IA . As discussed in Section 2.5, a limited bandwidth causes ISI and degrades the opening of the eye diagram. To receive data with a certain bitrate Rb , the bandwidth must be as high as possible to minimize the ISI. But on the other hand, Section 4.3.3 will demonstrate that a large bandwidth increases the noise picked up by the TIA. As a compromise between noise and ISI, a TIA bandwidth equal to 0.7Rb is commonly used [Raz03, S¨ac05]. Noise The input-referred current noise is one of the most critical TIA parameters. Often the noise of the TIA dominates all other noise sources and therefore determines the sensitivity of the receiver. The equivalent input-referred noise current is the current source that, together with the ideal noiseless TIA, reproduces the output noise of the actual noisy TIA. As stated before in Section 2.4.2, it is a ﬁctitious quantity that cannot be observed in the actual circuit. To determine the input-referred noise current, the noise power spectral density at the output for each noise source is calculated ﬁrst. Typical noise sources are transistors, resistors and diodes. Assuming these sources are not correlated, they add up to form the total output noise power spectral density. The power spectral density of the input-referred noise current, di2n,T IA , can then be found by taking the frequency-dependent transimpedance gain into account:

4.3 Design of the Shunt-Shunt Feedback TIA

di2n,T IA =

63

2 dvn,T IA

. (4.2) |ZT IA (f )|2 The input-referred rms noise current, in,rms (2.7), also called the total integrated input-referred noise current of the TIA, in,T IA , is determined by dividing the rms output noise voltage by the DC value of the transimpedance gain. The rms output noise voltage is obtained by integrating the output-referred noise spectrum and taking the square root. ∞ 1 2 dvn,T (4.3) in,T IA = IA df . ZT IA,0 0 Note that this deﬁnition is diﬀerent from integrating the input-referred noise current to a certain bandwidth. For analytical calculations, the integration has to be carried out to inﬁnity. For simulations and measurements, a few times the bandwidth BWT IA , or simply the bandwidth (for higher order TIAs with a steep roll-oﬀ) is taken as upper limit. For completeness, the deﬁnition of noise bandwidth BWn is repeated here. It is the bandwidth, multiplied by the DC value of the power spectral noise density, which gives the same result as the integration of the power spectral noise density to inﬁnity. For a ﬁrst order circuit, BWn equals π2 times the 3-dB bandwidth [San06]. For a third order circuit with a steeper slope, the noise bandwidth and the 3-dB bandwidth nearly coincide. Overload Current A TIA may receive large signal currents, for example when the distance between transmitter and receiver is very short and the photodetector has a high responsivity. As the input level increases, the TIA will introduce nonlinearities in the signal. Due to the binary nature of transmitted data, some nonlinearity can be tolerated. However, too much nonlinearities may corrupt the signal levels and/or distort the zero crossings, increasing the BER. Naturally, this has to be avoided. Following the simulations of Chapter 3, the responsivity of integrated CMOS diodes is rather low, because the standard silicon technology is not optimal for optical applications. So even for large optical signals, the currents at the input will remain below the overload current.

4.3 Design of the Shunt-Shunt Feedback TIA The TIA topology used in this work is the so-called shunt-shunt feedback TIA. A negative feedback network senses the voltage at the output and returns a proportional current to the input. This type of feedback has the advantage that it lowers both the input and output impedance. As a result, the closedloop bandwidth is increased by the loop gain. In this section, the main design equations for the shunt-shunt feedback TIA are derived.

64

4 Transimpedance Ampliﬁer Design TIA

Rf

Rout

nin

Idio

nout

A0

C dio

Cout

Cin

Cnext

PD

(a) Rf vin i dio

Rout

nin

C dio

−A0 vin

Cin

C inT

nout

vout

C out

Cnext

C outT

(b)

Fig. 4.1. The shunt-shunt feedback TIA: (a) general schematic, (b) small-signal equivalent circuit.

4.3.1 Transimpedance Gain and Bandwidth Fig. 4.1(a) shows a general schematic of the shunt-shunt feedback TIA. The photodiode is represented by the current source Idio in parallel with the junction capacitance Cdio . The TIA consists of a voltage ampliﬁer with DC gain A0 and feedback resistance Rf . The input capacitance Cin and output capacitance Cout are determined by the sizes of the transistors that constitute the voltage ampliﬁer. Cnext is the input capacitance of the next stage. Rout is the TIA output resistance and is usually much smaller than Rf . The analysis of the small-signal equivalent circuit, depicted in Fig. 4.1(b), results in following transimpedance gain: ZT IA =

vout Z T IA,0 = R C C (R R out inT outT f f +Rout )CinT idio s2 +s + A0 +1 A0 +1

Rout CoutT A0 +1

, +1 (4.4)

with: ZT IA,0 =

Rout Rf A0 − ≈ Rf , A0 + 1 A0 + 1

(4.5)

4.3 Design of the Shunt-Shunt Feedback TIA

65

CinT = Cdio + Cin ,

(4.6)

CoutT = Cout + Cnext .

(4.7)

According to (4.5), the transimpedance gain at low frequencies equals Rf for large values of A0 and small values of Rout . To ﬁnd the bandwidth of (4.4), two separate cases are considered. First, suppose the second pole of the TIA has a much higher magnitude than the ﬁrst pole. Taking into account following approximations: A0 + 1 ≈ A0 , Rout Rf ,

(4.8) (4.9)

Rout CoutT Rf CinT ,

(4.10)

the well-known expression for the TIA bandwidth BWT IA can be found: BWT IA =

A0 . 2πRf CinT

(4.11)

The dominant pole, which determines the bandwidth in this case, is located at the input node nin. Due to the feedback loop, the resistance at this node is divided by the loop gain, which results in a factor A0 increase of bandwidth. Therefore, A0 has to be maximized during the design process. Other factors that inﬂuence bandwidth are the feedback resistor Rf and the total input capacitance CinT . Rf usually cannot be made too small for gain (4.5) and noise considerations (4.36). CinT consists of two parts: Cdio , determined by the photodiode topology, and Cin , which increases for larger transistor dimensions. This expression for the bandwidth reveals two important conclusions: • As the photodiode junction capacitance directly appears in the denominator of (4.11), a photodiode-TIA co-design is mandatory. • A design aiming for high bandwidth implies an optimization of the voltage gain A0 . The non-dominant pole is located at the output node nout. It coincides with the bandwidth BWV A of the voltage ampliﬁer, which has only one pole in the simpliﬁed model of Fig. 4.1. fnd,T IA = BWV A =

1 . 2πRout Cout

(4.12)

However, the two poles of a second-order system can seldom be treated as two real poles. Mostly, they will be part of a complex conjugated pair. In basic control theory, the denominator of a second-order system is written as [Dor98]: s 2 s + 2ζ + 1, (4.13) ωn ωn where ζ is the dimensionless damping ratio and ωn is the natural pulsation of the system. When ζ = 1, the system is critically damped. Complex conjugated

66

4 Transimpedance Ampliﬁer Design

poles occur when ζ < 1. The relation between 3-dB bandwidth ω3dB , natural pulsation ωn and damping ratio ζ can be calculated by setting the magnitude √ of (4.13) equal to 2/ 2: √ ω3dB = (1 − 2ζ 2 ) + 2 2ζ 4 − 2ζ 2 + 1. ωn

(4.14)

A smaller ζ will result in a larger 3-dB bandwidth, but also a higher overshoot in the time domain and a larger resonance peaking in the frequency domain. This causes degradation of the high and low levels and jitter in the eye diagram, despite the large bandwidth. In [Dor98] the percent overshoot P.O. is deﬁned by: √ 2 (4.15) P.O. = 100e−ζπ/ 1−ζ . √ Setting ζ equal to 2/2 is an attractive solution. The percent overshoot is only 4 %, while the 3-dB bandwidth equals ωn . It also generates a system with a maximally ﬂat frequency response, which corresponds to a Butterworth ﬁlter. This way, a compromise is found between bandwidth and overshoot, leading to a high-quality eye diagram. Equating (4.13) with the denominator of (4.4) gives following results for the natural pulsation and damping ratio of the second-order TIA depicted in Fig. 4.1: A0 + 1 , (4.16) ωn = Rf Rout CinT CoutT R C

f inT +1 1 . ζ = Rout CoutT R 2 (A + 1) f CinT

0

(4.17)

Rout CoutT

For suﬃciently large gain A0 , the last equation can be rewritten as: 1 A0 = 4ζ 2 . Rout CoutT Rf CinT

(4.18)

This is the condition at the input node nin and output node nout of Fig. 4.1 which has to be fulﬁlled to design a TIA with a certain damping ratio ζ. Combining (4.18) and (4.16), the corresponding natural pulsation can be found. More interesting is the 3dB-bandwidth, which can be calculated using (4.14). The results for some typical values of ζ are summarized in Table 4.1. Comparing the fourth column of Table 4.1 with the earlier derived expression for the TIA bandwidth, (4.11), an increase in bandwidth is noticed. The system under study is unchanged, only the basic assumptions for the hand calculations are diﬀerent. In the case of (4.11), the TIA has two well-separated real poles while in the other case, the poles are complex conjugates. Due to these complex poles, the resulting 3dB-bandwidth is larger, but some overshoot will occur in the eye diagram. However, this is tolerable as long as the

4.3 Design of the Shunt-Shunt Feedback TIA

67

Table 4.1. Design equations for the second-order TIA of Fig. 4.1. ζ

Condition (4.18) ωn (4.16) ω3dB (4.14) P.O. (4.15) P.M. (4.27)

1 1 2 Rout CoutT √ 1 2 2 Rout CoutT √ 1 3 2 Rout CoutT

=

A0 Rf CinT

=

2A0 Rf CinT

=

3A0 Rf CinT

A0 Rf CinT √ 2A0 Rf CinT √ 3A0 Rf CinT

1.6A0 Rf CinT √ 2A0 Rf CinT 1.07A0 Rf CinT

16 %

45◦

4%

63◦

0.4 %

72◦

damping ratio is high enough and no ringing occurs. The smaller ζ, the higher the bandwidth, but the more overshoot and ringing. Also the phase margin decreases with ζ. An expression for the phase margin (P.M.) will be derived in the next subsection. Most important is that the main conclusions of (4.11) are still valid: the TIA bandwidth BWT IA is inversely proportional to the input capacitance CinT (which contains the photodiode capacitance Cdio ), inversely proportional to the feedback resistor Rf , and directly proportional to the DC √ gain A0 of the voltage ampliﬁer. Note also that for ζ = 3/2, the expression for the bandwidth almost equals (4.11). The ﬁrst two designs discussed in Section 4.5 will use a rather safe phase margin of at least 72◦ . The last design will allow more √ overshoot in exchange for a higher bandwidth, so ζ will be more around 2/2. This overshoot can be tolerated, as the TIA is followed by a limiting ampliﬁer, which will be discussed in Chapter 5. To compare the performance of diﬀerent TIAs, a parameter which takes into account several of its characteristics is needed. In analogy with the gainbandwidth product GBW of voltage ampliﬁers [San06], the transimpedancebandwidth product ZBW is used to evaluate the TIA performance. It is deﬁned by the product of its transimpedance gain ZT IA,0 and its 3-dB bandwidth BWT IA : A0 ZBW = ZT IA,0 · BWT IA ≈ . (4.19) 2πCinT The transimpedance-bandwidth is independent of the feedback resistor Rf . To some extent, transimpedance gain can simply be exchanged for bandwidth and vice versa, by changing the value of Rf . The only limitation is that the damping ratio has to be high enough, or equivalently, that there needs to be suﬃcient phase margin. (Table 4.1). The transimpedance-bandwidth ZBW (4.19) again emphasizes the importance of the voltage gain A0 . As the total input capacitance is largely determined by the photodiode capacitance, whose parameters are dictated by technology rules and ﬁber size, the only way to optimize ZBW is by maximizing A0 .

68

4 Transimpedance Ampliﬁer Design vin

Rout

nin

idio

C inT

Rf

vout Rf

−A0 vin

nout

Rf

vout

vin Rf

CoutT

(a) idio

−Rf 1+sR f C inT

vin

1

−A0 1+

GTIA

Rf R out

vout

+s R out C outT

1 Rf (b)

Fig. 4.2. TIA representations to determine open-loop gain and loop gain: (a) Coates transformation of Fig. 4.1(b), (b) block diagram.

4.3.2 Open-Loop Gain and Loop Gain Another way of looking at the TIA with shunt-shunt feedback, is depicted in Fig. 4.2(a). The feedback resistor Rf between nodes nin and nout is replaced by its Coates transformation: resistor Rf and voltage-controlled current source vout /Rf between node nin and ground; and resistor Rf and voltagecontrolled current source vin /Rf between node nout and ground. Starting from this equivalent circuit, the block diagram of Fig. 4.2(b) can be derived. It represents the feedback system by its open-loop gain GT IA and loop gain GHT IA . In the block diagram of Fig. 4.2(b), the feedforward voltage controlled current source vin /Rf has been neglected. This is allowed if ARf Rout , which is almost always true. The expression for the open-loop gain GT IA is then given by: GT IA =

A0 Rf . (1 + sRf CinT )(1 + RRout + sRout CoutT ) f

(4.20)

If it also can be assumed that Rf Rout , the open-loop gain further reduces to: A0 Rf GT IA = . (4.21) (1 + sRf CinT )(1 + sRout CoutT ) The loop gain GHT IA equals the open-loop gain GT IA times the feedback factor 1/Rf , or:

4.3 Design of the Shunt-Shunt Feedback TIA

GHT IA =

A0 . (1 + sRf CinT )(1 + sRout CoutT )

69

(4.22)

The phase margin is often used in basic control theory to study the stability of feedback systems [Dor98]. It is the amount of extra phase shift of the loop gain (GHT IA ) at unity magnitude (or 0 dB) that will result in a phase angle of 180◦ . To derive an expression for the phase margin, it is assumed that the poles of (4.22) are real and diﬀer a lot in magnitude. So the dominant pole fd,GH and non-dominant pole fnd,GH of the loop gain GHT IA can readily be found: 1 , 2πRf CinT 1 = . 2πRout CoutT

fd,GH = fnd,GH

(4.23) (4.24)

Note that the latter is also the pole which determines the bandwidth of the voltage ampliﬁer, BWV A (4.12). The unity-gain frequency of the loop gain f0dB,GH is given by: A0 f0dB,GH = , (4.25) 2πRf CinT assuming fd,GH f0dB,GH fnd,GH . Under the same condition, the phase angle at this frequency equals: θ(f0dB,GH ) = −(

f π 0dB,GH . + arctan 2 fnd,GH

(4.26)

This results in the expression for the phase margin P.M.: P.M. =

f f π 0dB,GH nd,GH = arctan . − arctan 2 fnd,GH f0dB,GH

(4.27)

For instance, if fnd,GH = 3 · f0dB,GH , the phase margin equals 72◦ . Other examples for smaller ratios are given in Table 4.1. Note however that these are hand calculations and that the expression for the P.M. approaches reality only if fd,GH f0dB,GH fnd,GH . For the other equations in Table 4.1, the requirements regarding pole location are less stringent. The expressions derived so far are valid for the voltage ampliﬁer model depicted in Fig. 4.1, which has only one dominant pole at the output. If the voltage ampliﬁer consists for example of three identical amplifying stages, three more or less identical poles fnd,GH are present. The loop gain can now be approximated by: GHT IA = and the phase margin:

A0 (1 + sRf CinT )(1 +

, s 3 fnd,GH )

(4.28)

70

4 Transimpedance Ampliﬁer Design

P.M. =

f π 0dB,GH , − 3 · arctan 2 fnd,GH

(4.29)

with f0dB,GH given by (4.25). To achieve the same phase-margin, the ratio of f0dB,GH to fnd,GH has to be approximately three times smaller than the ratio in (4.27). So assuming the same f0dB,GH , the non-dominant pole of the loop-gain, which coincides with the bandwidth of the voltage ampliﬁer, has to be three times higher in frequency for a three-stage ampliﬁer compared to a single-stage ampliﬁer. A good reason for choosing a multiple-stage approach would be to increase the voltage ampliﬁer’s gain A0 . This way, the bandwidth BWT IA is enlarged, or for the same bandwidth, the feedback resistance Rf can be larger (4.11). As will become clear in Section 4.3.3, a larger Rf leads to a better TIA noise performance and thus a better receiver sensitivity. However, due to stability requirement (4.29), the voltage gain of a three-stage ampliﬁer is limited by the ratio of the bandwidth of the TIA (BWT IA ) and the fT of a certain technology. In [Ing04] it is demonstrated that, when BWT IA ≈ 0.1fT or larger, the maximal achievable gain of a single stage voltage ampliﬁer is larger than the maximal achievable gain of a three-stage voltage ampliﬁer. Applications demanding a high bandwidth compared to the technology’s fT have to implement a single-stage ampliﬁer rather than a three-stage ampliﬁer, as there is simply no room for placing the extra poles which are introduced in a multiple-stage approach. However, for frequencies 20 to 30 times below fT , a multiple-stage ampliﬁer is the best design choice. 4.3.3 Noise The noise sources of the shunt-shunt feedback TIA are added to the general schematic in Fig. 4.3. Two TIA noise sources can be distinguished: the noise from the feedback resistor and the noise from the voltage ampliﬁer. The third noise source stems from the noise generated by the photodiode. Noise Densities of the Three Noise Sources The thermal noise of the resistor is modeled by a current noise source di2Rf in parallel: 4kT di2Rf = df. (4.30) Rf The noise current power is proportional to the absolute temperature in Kelvin, and inversely proportional to the value of the feedback resistor Rf . It is white noise, as it does not change with frequency. The noise of the voltage ampliﬁer is represented by the noise of an equivalent input transistor Mx with equivalent transconductance gmx . In most designs, where the input stage features large gain, the equivalent transistor Mx simply corresponds to the input transistor of the voltage ampliﬁer. For a MOS

4.3 Design of the Shunt-Shunt Feedback TIA

71

2

diR

f

Rf

A0

2

diM

x

nin 2 didio

Idio

C dio

Cin

Mx

Rout

nout

Cout

Cnext

Fig. 4.3. The shunt-shunt feedback TIA with the most important noise sources.

transistor, the classical thermal channel noise di2Mx is still the most important noise source. It is given by: di2Mx = 4kT γgmxdf,

(4.31)

where γ is the excess noise factor. This noise current power is also white and proportional to the absolute temperature and to the transconductance gmx . For long-channel devices, γ = 2/3. In short-channel devices the eﬀective temperature of the carriers is signiﬁcantly larger due to the high electric ﬁeld in the channel and γ can be as high as 2 or 3. The pMOS transistor usually exhibits lower γ values than its nMOS counterpart. Finally, the last noise source is the noise from the photodiode di2dio . Mostly, it consists only of shot noise, which is given by: di2dio = 2qIdio df.

(4.32)

The shot noise current power is also white, and proportional to the current ﬂowing through the junction. This noise power is data-dependent: when a photodiode receives a zero, no light power is received, and the current Idio is (almost) zero. When a one is received, the generated noise depends on the received light power and the photodiode responsivity. As the noise current varies with time, it is called non-stationary. However, in most cases, the photodiode shot noise can be neglected. Output Noise Spectral Density and Input-Referred Noise Spectral Density The power spectral density of the output noise voltage is given by the noise current power of each noise source, multiplied by the square of its transfer function to the output.

72

4 Transimpedance Ampliﬁer Design

di2dio ZT2 IA,0 2 dvn,T = 2 IA 2 Rf Rout CinT CoutT (Rf +Rout )CinT Rout CoutT + 1 + s + s A0 +1 A0 +1 A0 +1 2 2 R A di2Rf Af0 +10 1 + s RoutAC0 inT + 2 2 Rf Rout CinT CoutT (Rf +Rout )CinT Rout CoutT + 1 + s + s A0 +1 A0 +1 A0 +1 2 2 di2Mx RAout 1 + sRf CinT 0 + 2 . 2 Rf Rout CinT CoutT (Rf +Rout )CinT Rout CoutT + 1 + s + s A0 +1 A0 +1 A0 +1 (4.33) This expression can be simpliﬁed using following assumptions: • The shot noise of the photodiode is negligible small compared to the other noise sources. • A0 + 1 ≈ A0 . A0 • The zero 2πRout CinT is located at a frequency beyond the frequency range of interest. This corresponds to neglecting the feedforward current of Rf , injected by its noise source in node nout. • Following the one-transistor equivalent of the voltage ampliﬁer, gmx Rout = A0 . The resulting expression for the output noise spectral density is: 4kT Rf df 2 dvn,T IA = 2 Rf Rout CinT CoutT (Rf +Rout )CinT +s + s A0 +1 A0 +1 2 4kT γdf gmx 1 + sRf CinT + 2 Rf Rout CinT CoutT (Rf +Rout )CinT + s + s A0 +1 A0 +1

Rout CoutT A0 +1

Rout CoutT A0 +1

2 + 1

2 . + 1 (4.34)

This expression is plotted versus log(f ) in Fig. 4.4(a). At low frequencies, the noise is dominated by the feedback resistor’s thermal noise. At higher frequencies and for a suﬃcient high gain A0 , the ampliﬁer noise may become dominant. Note that the integration of the power spectral density in this case will lead to an integrated output noise voltage which is dominated by the noise of the ampliﬁer. The representation in Fig. 4.4(a) may suggest something else, but it is misleading due to the logarithmic frequency axis which overemphasizes the integrated low-frequency noise. In a design aiming primarily for large bandwidth, the dominant noise source might be the feedback resistor and not the ampliﬁer. This is the case when the zero and poles of (4.34) are located close to each other, which is usually true for high BWT IA /fT ratios. As the bandwidth is comparable to

4.3 Design of the Shunt-Shunt Feedback TIA dv2n,TIA (dB/Hz) 4kTγ A2 g mx 0

di 2n,TIA (dB/Hz)

Rf amplifier total

73

Rf amplifier total

4kTRf 4kT Rf

4kTγ g mx

4kTγ g mxR2f 1 2π Rf CinT

BWTIA

fnd,TIA f (Hz)

(a)

1 2π Rf CinT

f (Hz)

(b)

Fig. 4.4. Power spectral densities of: (a) TIA output noise, (b) TIA input-referred noise.

fT , there is not much headroom left to place the other poles. An additional advantage is that complex conjugated poles increase the bandwidth, as discussed in Section 4.3.1. Moreover, the noise generated by the feedback resistor is quite large, as the TIA bandwidth is inversely proportional to its resistance value. This value is a few orders of magnitude smaller than in traditional designs, where a bandwidth of a few megahertz is suﬃcient. Finally, also the voltage gain A0 cannot be very large as too much loop gain can cause stability problems. As a result, the maximum value for the ampliﬁer output noise power spectral density depicted in Fig. 4.4(a) and given by: 4kT γ 2 A , gmx 0

(4.35)

will not be reached and the actual maximum will stay below 4kT Rf . Examples of diﬀerent output noise spectral densities will be discussed in Section 4.5. To compare the output voltage noise with the input photodiode current, the output noise is referred to the input. According to (4.2), the power spectral density of the input-referred current noise is given by the division of (4.34) by the square of (4.4). 2 4kT 4kT γdf + sR di2n,T IA = df + C (4.36) 1 . f inT Rf gmx Rf2 This expression is plotted versus frequency in Fig. 4.4(b). The ﬁrst term is caused by the feedback resistor Rf . It is frequency independent and equal to the thermal noise of Rf (4.30). Neglecting the feedforward noise current, only the feedback current at the input remains which directly adds up with the photodiode current. The larger Rf , the smaller this noise, but also the smaller the TIA bandwidth BWT IA (4.11). The second term is the noise contribution

74

4 Transimpedance Ampliﬁer Design

of the voltage ampliﬁer. It features a zero at 1/2πRf CinT , which is a factor A0 below the bandwidth BWT IA (4.11). Due to this zero, the ampliﬁer’s noise may become dominant at higher frequencies. The noise contribution of both the feedback resistor and the ampliﬁer result in an input-referred noise spectrum which is ﬂat at low frequencies, and rises with f 2 at higher frequencies. Noise Optimization As the noise of the TIA directly determines the receiver’s sensitivity, the TIA design plan must include a minimization of noise. Since the TIA is a broadband ampliﬁer, not only the power spectral density of the noise is important, but the integrated noise is even more important. Diﬀerent noise analyses can be found in literature which are based on slightly diﬀerent assumptions. However they have two approximations in common: ﬁrst, the noise of the light detector is neglected and second, the noise of the post-ampliﬁer is neglected. In Section 4.5 some design examples will show that the ﬁrst assumption is not always valid. The latter assumption it true when the transimpedance gain is always suﬃciently high, but in reality this is not always the case. However, since an increased transimpedance gain goes hand in hand with a reduced TIA noise, neglecting the noise of the post-ampliﬁer rarely aﬀects the design optimum. An overview of the most important results is given here. A thorough noise analysis of wide-band ampliﬁers in bipolar and CMOS technologies is given in [Cha91]. An expression is derived for the equivalent input noise density of a wide-band ampliﬁer with capacitive source, which belongs to the same ampliﬁer category as the transimpedance ampliﬁer. The noise reaches a minimum value when the input capacitance of the voltage ampliﬁer equals all other capacitances at the input node. Assuming that the thermal noise of the input transistor is dominant, the optimal input transistor width is calculated. A more speciﬁc noise analysis of a shunt-shunt feedback transimpedance ampliﬁer is presented in [Ing04]. The output noise power density is calculated, but in contrast to (4.34), two separate poles, a dominant pole (4.11) and non-dominant pole (4.12) are assumed in the denominator. The equivalent input-referred noise current (4.36) is minimized, taken into account following assumptions: • gm Rf > 1 • Cin of the ampliﬁer is mainly determined by the gate-source capacitance Cgs of the input transistor. Cgd and the Miller eﬀect on this capacitance, are neglected. • The excess noise factor γ equals 2/3. The optimal gate-source capacitance Cgs , corresponding to the minimal inputreferred current noise, is found to be equal to the diode capacitance: Cgs = Cdio . This is the same result as derived by [Cha91].

4.3 Design of the Shunt-Shunt Feedback TIA

75

However, this result is not unconditional, but based on the assumption that the feedback resistor Rf is independent of the input capacitors. In high-speed receivers, the maximal feedback resistor is limited and its noise contribution becomes relatively more important compared to that of the ampliﬁer. As the receiver’s bandwidth is limited by both Cgs and Rf , there is inevitably some trade-oﬀ between them, also for the noise performance. The optimal ratio XN between Cgs and Cdio is derived in [Ing04] based on a maximization of the signal to noise ratio at the output. The noise power at the output is obtained by integration of the output noise power spectrum (4.34), represented in Fig. 4.4(a). The signal power at the output depends on the spectrum of the data signal and its data coding scheme. In [Ing04], a ﬂat signal spectrum is assumed. The optimal ratio corresponding with the best signal to noise ratio is than given by: XN,opt =

Cgs,opt ≈ Cdio 1+

1 μ(Vgs −VT ) 9 4 A0 L2 FBW BWT IA

,

(4.37)

with factor FBW deﬁned as: FBW =

π BWV A − 1. 2 BWT IA

(4.38)

For typical values of the various parameters this ratio lies between 0.5 and 1. The optimal Cgs is thus always smaller than Cdio . In [Ing04], the signal to noise ratio of a TIA with a single stage voltage ampliﬁer in a 0.7 µm CMOS technology is plotted versus XN . The SNR-curve is relatively ﬂat, which means that a deviation from the optimal XN only results in a slightly lower signal to noise ratio. In [Ler04] the bandwidth of the TIA is considered as a ﬁxed design constraint for a given application. As in [Ing04], the noise optimum is found by integrating both signal and noise at the output of the TIA and maximizing the SNR. The aim of the optimization is to ﬁnd the optimal Cgs of the input transistor for a given maximum voltage gain A0 and unity gain frequency fT . The power spectral density of the NRZ signal Sout is now more accurately described by: 2 2 sin(πf Tb ) Rf 2 Sout = idio Tb (4.39) , R C (1 + s f inT )(1 + sRout Cout ) πf Tb A0 where idio is the amplitude of the diode input current and Tb is the bit period. So again two separated poles are assumed for the transimpedance gain, and its DC value is approximated by Rf . The dominant pole of (4.39), BWT IA (4.11), is set by the bitrate of the application. It is also (approximately) equal to the unity-gain frequency of the loop gain. It can further also be assumed that the non-dominant pole, given by (4.12), is ﬁxed to a minimum value enforced by the stability requirement. Under these assumptions, the output signal power

76

4 Transimpedance Ampliﬁer Design

is solely depending on the DC transimpedance gain Rf . To maximize the SNR it suﬃces to minimize the input-referred integrated noise power i2n,T IA : ∞ i2n,T IA

=

0

2 dvn,T IA df

Rf2

.

(4.40)

So the same integration of the output noise power spectral density is performed as in [Ing04]. The major diﬀerence is that now Cgd and the Miller eﬀect are taken into account: (4.41) Cin = Cgs (1 + Mi αgd ), with: αgd =

Cgd . Cgs

(4.42)

and Mi = A0 + 1. The transconductance gm is rewritten as: gm = 2πfT Cgs =

2πfT Cin . 1 + Mi αgd

(4.43)

The expressions found in [Ler04] demonstrate that the input referred noise increases with the second power of the bandwidth for the Rf contribution and even to the third power for the ampliﬁer contribution. This clearly shows that designing sensitive optical receivers becomes increasingly diﬃcult for larger bitrates. The optimal ratio XN,opt is now given by: XN,opt ≈

1 fT (1 + Mi αgd )2 + (1 + Mi αgd ) 3π 4 BWT IA

1 γA0 FBW

.

(4.44)

By including the Miller eﬀect, the optimal Cgs is even smaller than the optimum (4.37) found in [Ing04]. A numerical example in [Ler04] illustrates that Cgs can be as small as ≈ 0.23 · Cdio (for αgd = 0.25, fT /BWT IA = 20, γ = 1, Mi = 11, FBW = 4). Note also that according to (4.44), the ratio XN,opt will decrease for newer technologies with increasing fT and the same bandwidth BWT IA .

4.4 Literature Examples The main question after studying the high-level design of a TIA is how to realize the voltage ampliﬁer depicted in Fig. 4.1. In literature, two important approaches can be found: the TIA with common source input stage and the TIA with regulated cascode input stage. Both are discussed next, with some paper references as example. Also a survey is given of the latest novelties regarding TIA design presented at the International Solid-State Circuits Conferences (ISSCC).

4.4 Literature Examples

M2 Rf

Rf

77

Vout

Vout

M1

M1

(a)

(b)

Rf M3

M6

M9 Vout

M1

M2

M4

M5

M7

M8

(c) Fig. 4.5. Schematic of (a) a CS TIA with source follower [Kie03, Swo05], (b) a CS TIA [Tsa04, Rad05, Tsa06], (c) a three-stage TIA with gm /gm amplifying stage [Ing94].

4.4.1 Common Source TIA The most widely used topology, implemented in many variants and technologies, is the TIA with common source input stage, depicted in Fig. 4.5(a). Transistor M1 is the common source transistor which realizes ampliﬁcation. The source follower (M2 ) isolates the drain of M1 from the loading eﬀect of both Rf and the input capacitance of the subsequent stage. In addition, the output resistance of the source follower is only 1/gm,M2 , which is much less than Rf . The voltage gain A0 equals gm,M1 /gds,M1 , assuming the output conductance of the current source can be neglected. This circuit has been used for instance in [Kie03] and [Swo05]. The source follower increases the total loop gain, but consumes a large voltage headroom. One may consider to eliminate this stage, arriving at the circuit depicted in Fig. 4.5(b). In a typical design, the output resistance determined by the parallel combination of the output conductance gds,M1 and the current

78

4 Transimpedance Ampliﬁer Design

source (which might be a simple resistor) is not small anymore compared to the feedback resistance Rf . This topology has been used in [Tsa04, Rad05, Tsa06]. A natural way to implement a common-source ampliﬁer stage in CMOS is adding a pMOS load and connecting the gates, which results in an inverter stage. This way, the transconductance of the input stage is doubled, which leads to a higher voltage gain A0 . As demonstrated in [Ing94], the stability requirement for having suﬃcient phase margin (4.27) in the traditional com2 mon source approach is related to gds,M1 , which is strongly process-dependent. Therefore, the inverter stage presented in [Ing94] features a diode-connected nMOS load transistor, so that the output resistance is now determined by 1/gm,M2 . The voltage gain A0 is given by the ratio of transconductances: A0 =

gm,M1 + gm,M3 . gm,M2

(4.45)

The analysis in [Ing94] shows that this ratio is only process dependent through the square root of the ratio of mobilities. The TIA presented in [Ing94] and shown in Fig. 4.5(c) has three identical stages to create a larger voltage gain A0 . Each of these stages consumes 2 mA from a 5 V supply. A transimpedance gain of 150 kΩ is realized, combined with a bitrate of 240 Mbit/s. This results in a transimpedance-bandwidth of 18 THzΩ. When moving to higher BWT IA /fT ratios, the intrinsic technology speed limits the placement of the non-dominant poles at higher frequencies, which is needed to maintain stability (Section 4.3.2). Therefore, the TIA presented in [Ing99] is based on a single-stage gm /gm voltage ampliﬁer, featuring a high speed combined with an accurate gain. The TIA consumes approximately 5 mA from a single 5 V power supply, and features a transimpedance gain of 1 kΩ. It is realized together with a postampliﬁer based on a biased inverter chain and achieves bitrates up to 1 Gbit/s. The optical receiver is characterized electrically by replacing the photodiode by its Thevenin equivalent. A large resistor is inserted after the 50 Ω signal source and the photodiode capacitance is modeled by a 500 fF capacitor. 4.4.2 Regulated Cascode TIA The regulated cascode (RGC) TIA is actually an extension of the common gate (CG) TIA. The latter topology is depicted in Fig. 4.6(a), where the photodiode is connected to the source of the common gate input transistor M1 [Par97]. This way, the photodiode capacitance sees only a small input resistance determined by 1/gm,M1 . The feedback resistor Rf is inserted between the output (neglecting the source follower M4 ) and the drain of M1 . The dominant pole of this feedback ampliﬁer depends on the input capacitance of M2 , the gate and drain capacitance of M1 and the feedback resistor Rf . In contrast to the common source TIA, the bandwidth is isolated from the photodiode capacitance at the input, which is the major advantage of this topology.

4.4 Literature Examples

R1

R2 Rf M2

Vb

R1

RB

M3

M1

R3 M2

Rf M4 Vout

79

M4 M3

M1

M5 Vout

MB Rs

Rs

(a)

(b)

Fig. 4.6. Schematic of (a) a CG TIA [Par97], (b) a RGC TIA [Par00, Par04].

The RGC TIA is shown in Fig. 4.6(b) and presented in [Par00, Par04] . The small-signal input resistance at the source of M1 is given by: Zin,0 =

1 , gm,M1 (1 + gm,MB RB )

(4.46)

where (1 + gm,MB RB ) is the voltage gain of the local feedback stage. One could say that the RGC input stage behaves qualitatively as a CG input stage with a large transconductance Gm of gm,M1 (1 + gm,MB RB ). It enables (1 + gm,MB RB ) times better isolation of the input parasitic capacitance from the bandwidth determination. A source-follower buﬀer stage M2 is introduced between the RGC input stage and the voltage gain stage M3 −R3 . This follower reduces the total capacitance looking from the high impedance node at the drain of M1 and thus provides a potential for wider bandwidth. However, it may reduce the total open-loop gain and degrades the circuit linearity. The measurement results in [Par00] demonstrate a 3-dB bandwidth of 300 MHz and a transimpedance gain of almost 58 dBΩ with a 6 V power supply. The resulting trans-impedance-bandwidth product equals 238 GHzΩ. However, these values are calculated from S-parameter measurements with a network analyzer, where a test power level of −40 dBm emulates a 50 µA current. As a photodiode is a current source with a high output impedance in contrast with the used voltage source with low output impedance (50 Ω), these values should be treated with care. To facilitate the measurements, the photodiode is modeled as an equivalent electrical circuit in [Par04] and mounted on a test board together with the TIA chip. The frequency response is measured with a network analyzer, achieving a transimpedance gain of 58 dBΩ and 3-dB bandwidth of 950 MHz for a 0.5 pF photodiode capacitance. As a consequence, the transimpedancebandwidth product equals 755 GHzΩ. Also eye diagrams are presented at 622 Mbit/s, 1.0625 Gbit/s, 1.25 Gbit/s and 1.866 Gbit/s for a 231 − 1 prbs

80

4 Transimpedance Ampliﬁer Design

data with 125 µA equivalent input current. The chip core dissipates 85 mW from a 5 V supply. No optical measurements are performed, only electrical measurements with a low-impedance voltage source and the electrical equivalent model of the photodiode. For 1.25 Gbit/s operation, the electrical sensitivity is measured to be 5 µApp for a BER of 10−12 . Although the RGC and CG input stage both have the great advantage that the TIA bandwidth is nearly independent of the photodiode capacitance, there is also a price to pay. The extra transistors and resistors necessary to obtain a low input impedance also present extra noise sources. For instance the resistance current noises of RS on one hand and the parallel combination of R1 and Rf on the other hand directly add up with the input signal. In the common source approach, the only thermal resistance noise which appears directly at the input is the noise of Rf . A detailed noise analysis of the RGC TIA can be found in [Par04]. In [San06], a simpliﬁed comparison of the noise performance between the TIA with voltage ampliﬁer (common source topology) and the TIA with current ampliﬁer (cascode topology) is made. Both comparisons based on noise densities and based on the integrated noise arrive at the same conclusion: the noise of the TIA with voltage ampliﬁer is always smaller, as long as Rf is large enough. As this is usually the case, the regulated cascode topology is not adopted in this work. 4.4.3 The Latest Trends at ISSCC To conclude this literature section, an overview of some design trends of the past years at ISSCC is given. In [Sei04a, Sei04b], the problem is addressed when the TIA bandwidth is limited by the parasitic capacitance of a large polysilicon resistor. A conventional 200 kΩ polysilicon feedback resistor has for instance a 3-dB cut-oﬀ frequency of 67 MHz and therefore this frequency can be the dominant pole of the circuit. To solve this problem, a capacitivecoupled voltage divider is proposed as feedback network instead of a simple feedback resistor. It consists of a low- and high-frequency path of voltage dividers, connected by a coupling capacitor. A pin photodiode is integrated with the TIA in a BiCMOS technology and has a responsivity of 0.43 A/W for 660 nm light. The bandwidth is measured with a network analyzer modulating a laser and equals 378 MHz. Together with a transimpedance gain of 178 kΩ, this results in a transimpedance-bandwidth product of 67 THzΩ. The power consumption equals 70.5 mW from a 5 V power supply, of which the output driver dissipates 38 mW. One year later, [Tsa05b] introduces a self-compensated diﬀerential SiGe TIA which is tolerant of large capacitances at the input. The eﬀective input capacitance caused by the photodiode is signiﬁcantly reduced by adding a unity-gain buﬀer. The voltage at the cathode of the photodiode ideally tracks the RF voltage at the anode of the photodiode. Hence the transient voltage signal across the photodiode is reduced during operation to suppress the effect of its capacitance on the receiver bandwidth. This idea has already been

4.5 Case Studies

81

presented for a single-ended topology in [Tsa04, Tsa05a]. However, a unique feature of the proposed self-compensated diﬀerential topology is that it not only signiﬁcantly suppresses the impact of the photodiode capacitance on the receiver performance, but it also reduces the impact of other capacitances connected from the inputs to ground. When the photodiode is applied externally, these capacitances are due to the bondpads as well as the ESD protection circuits. Optical measurements are performed with the TIA IC integrated with a commercial 1310 nm InGaAs pin photodiode in a chip-on-board assembly. Its parasitic capacitance is around 0.7 pF. A measured 2.5 Gbit/s eye diagram with an optical power of −20 dBm at the input of the TIA IC with ESD protection circuits is shown. The bandwidth of the TIA with ESD equals 1.16 GHz, while the transimpedance gain is adjustable from 1 kΩ to 15 kΩ. No information is provided for which gain setting a 1.16 GHz bandwidth has been measured, so the transimpedance-bandwidth product is situated between 1 THzΩ and 17 THzΩ. The TIA core consumes 4.5 mW from a 3 V supply. Note that this technique is well suited for compensating oﬀ-chip capacitances, but diﬃcult to implement with an integrated CMOS photodiode. For a classical or diﬀerential n-well photodiode (Chapter 3) the anode corresponds to the p-substrate which inevitably has to be biased at the ground potential. Connecting the anode (p-substrate) to the input of the ampliﬁer and the cathode (n-well) to the output of the unity-gain follower is not possible in this case. Finally, a compensation technique at the output of the TIA is presented in [Tsa06]. The basic concept is to cancel the loading eﬀects caused by both the output impedance of the ampliﬁer and the feedback resistor, by introducing a compensation element with a negative impedance. Hence the loop gain can be signiﬁcantly boosted. As a result, the input impedance is reduced and the operating bandwidth is extended. The TIA IC is implemented in a standard 0.35 µm CMOS technology. The diﬀerential transimpedance gain is adjustable from 500 Ω to 13 kΩ. The TIA core dissipates 15 mW from a 3 V supply. Optical measurements demonstrate a bandwidth enhancement factor of 3 achieved by the active compensation technique. Eye diagrams are shown at 1.25 Gbit/s and an optical input power of −27 dBm (high-gain mode) and 0 dBm (low-gain mode). No measured values of the bandwidth are reported (except for the enhancement factor of 3), but assuming a bandwidth of at least 625 MHz, the transimpedance-bandwidth product is larger than 8 THzΩ. To conclude, the transimpedance-bandwidth product of the latest stateof-the-art TIAs equals several THzΩ’s. Furthermore, a trend can be observed that it is easier to achieve high transimpedance-bandwidth products by ampliﬁers with a high gain, but a lower bandwidth, than by high-speed ampliﬁers.

4.5 Case Studies This section discusses in depth three diﬀerent implementations for the voltage ampliﬁer depicted in Fig. 4.1. They all share the common source input stage

82

4 Transimpedance Ampliﬁer Design

topology. As the ultimate goal is to design a high-speed front-end, a singlestage approach is applied in the ﬁrst two implementations. The last design is fully diﬀerential, which enables a two-stage implementation with cross-coupled feedback resistors. The measurement results of these circuits, embedded in a receiver front-end, will be discussed in Chapter 6. 4.5.1 An Inverter-Based TIA for Test Photodiodes in 0.18 µm CMOS Design Goals and Implementation As this TIA is part of a test-chip with several photodiode structures, it must be able to generate a stable output voltage, despite the diﬀerent diode capacitance values at the input. Also, because it is the intention to compare the performance of the diode structures, the TIA should not be the speed limiting factor. Due to the non-optimized responsivity of CMOS photodiodes (see Chapter 3), the equivalent input-referred noise current should be as small as possible. The test photodiodes are: a classical n-well diode, a quasi-fractal nwell diode, a diﬀerential n-well diode, a p+ n-well diode with guard and an n+ p-substrate diode. The layout of these structures will be discussed in detail in Section 6.2. Their junction capacitances are respectively 660 fF, 585 fF, 292 fF, 4.6 pF and 6.8 pF. The schematic of the TIA, with diﬀerent diode conﬁgurations is depicted in Fig. 4.7(a) and Fig. 4.7(b). The n-region of the classical n-well diode, quasifractal n-well diode, diﬀerential n-well diode and n+ p-substrate diode respectively is connected to the input, while the p-substrate is connected to ground (Fig. 4.7(a)). The p+ n-well diode with guard topology consists of 2 diodes: the p+ n-well diode (PD) to detect the signal, and the n-well p-substrate diode (guard) to remove the diﬀusing substrate carriers (Fig. 4.7(b)). The p+ region is connected to the input of the TIA, while the n-well region is biased at a higher voltage Vb3 . In a 0.18 µm CMOS technology, this voltage should be limited to 1.8 V. A higher biasing voltage would generate a larger depletion region and a smaller junction capacitance, but is not applied for reliability reasons. The p-substrate is connected to ground. The TIA consists of a voltage ampliﬁer with inverter topology (nMOS transistor M1 and pMOS transistor M2 ) and a variable feedback resistance (resistor Rf b and pMOS transistor MRf b ). The diode-connected load used for instance in [Ing94, Ing99, Roo00] is omitted. The advantage is that the gain A0 is much higher, the disadvantage is that Rout is now completely determined by the output conductances of transistors M1 and M2 . These are susceptible to process variations, which can lead to stability problems. To avoid unstabilities during measurements, transistor M3 is added as load. It is biased in its linear region and can be switched on or oﬀ by changing the bias voltage Vb2 . Dummy stage M1d -M2d is added to create the same biasing conditions for transistor

4.5 Case Studies Vdd

Vb1

M2 nin

M2d

Vout M1

MRfb

Rfb nout

Vin

Vdd

Vb1

MRfb

83

M3 Vb2

M2

n1

nin

M2d

nout

Vin M1d

Rfb M3

Vout

Vb2

M1

C ac

n1

M1d

C ac

PD Vb3

PD

guard

(a)

(b)

Fig. 4.7. Schematic of the inverter-based 0.18 µm CMOS TIA: (a) conﬁguration for the classical n-well diode, quasi-fractal n-well diode, one half of the diﬀerential n-well diode and n+ p-substrate diode, (b) conﬁguration for the p+ n-well diode with guard.

Table 4.2. Design parameters of the inverter ampliﬁer and dummy stage.

type L W VDSAT IDS gm gds Cgs Cgd

M1

M2

M1d

M2d

nMOS 0.18 µm 40 µm 0.24 V 3.3 mA 15.7 mS 0.8 mS 47 fF 15 fF

pMOS 0.18 µm 60 µm −0.46 V −3.3 mA 10.3 mS 0.7 mS 75 fF 21 fF

nMOS 0.18 µm 4 µm 0.24 V 0.33 mA 1.57 mS 0.08 mS 4.7 fF 1.5 fF

pMOS 0.18 µm 6 µm −0.46 V −0.33 mA 1.03 mS 0.07 mS 7.5 fF 2.1 fF

M3 as for transistor Mrf b : equal drain and source voltages. It is a replica of inverter M1 -M2 , only the widths of the transistors are 10 times smaller to limit the power dissipation. Capacitor Cac is added to remove ac signals from node n1. The design parameters of the inverter ampliﬁer and dummy stage are summarized in Table 4.2. The hand calculations and simulation results for diﬀerent biasing conditions and diﬀerent photodiode topologies can be found in Table 4.3 and Table 4.4.

84

4 Transimpedance Ampliﬁer Design

DC Operating Point As no DC current ﬂows through Rf , MRf b or M3 , following equation should be fulﬁlled: (4.47) IDS,M1 = |IDS,M2 |. Using the current expressions for strong inversion [San06], this equation becomes: 2 Kn W L M1 (VGS − VT )M1 (1 + λn VDS )M1 = Kp W (|VGS | − |VT |)2M2 (1 + λp |VDS |)M2 . (4.48) L M2

W is the transistor width, L is the transistor length, VT is the threshold voltage, VGS the gate-source voltage, Kn and Kp are the transconductance parameters for an nMOS and pMOS transistor respectively, λn and λp are the channel length modulation parameters for an nMOS and pMOS transistor respectively. As a high bandwidth is required, the length of the transistors is chosen minimal (0.18 µm). Rearranging the terms in (4.48) shows that the DC input voltage VIN , which is the same as the DC output voltage VOUT , is completely determined by the ratio of the width of the transistors: Kp (VDD − VIN − |VT p |)2 (1 + λp (VDD − VIN )) WM1 . = WM2 Kn (VIN − VT n )2 (1 + λn VIN )

(4.49)

As VIN also determines the reverse bias voltage of the photodiode, it should be large to widen the depletion region and to reduce the photodiode junction capacitance. However, the width only changes with the square root of the voltage (3.22). When no ac coupling is used, the output voltage VOUT equals the input voltage of the next stage. Moreover, this voltage determines the dynamic range for the TIA. A signal current from the photodiode ﬂows through Rf and increases the output voltage. Very large signals would steer transistor M2 into its linear region, resulting in a corrupted eye diagram. As the currents generated by the integrated diodes are very small, large output voltages almost never occur. In the presented design, the ratio WM1 /WM2 equals 2/3 (Table 4.2), resulting in a simulated VIN = VOUT = 0.8 V. Transimpedance Gain and Bandwidth To increase the ﬂexibility of the TIA, a variable transimpedance gain is implemented. This is realized with a ﬁxed resistor Rf b , in parallel with a pMOS transistor MRf b biased in its linear region. The advantage of using a ﬁxed resistor is that high-ohmic polysilicon can be used, with a value of approximately 1000 Ω/square. As a result, only 2 squares are needed to realize a 2 kΩ resistor, resulting in a compact layout with small parasitic capacitance values. The 4 µm x 8 µm resistor has a 3-dB bandwidth of 28 GHz. Transistor MRf b

4.5 Case Studies Vb1

Vb1

M Rfb

nin

85

M Rfb

nout

A0

nin

PD

nout

A0 PD

(a)

(b)

Fig. 4.8. Implementation of the feedback resistor: (a) nMOS-type, (b) pMOS-type.

is turned on when the signal is strong enough to lower the gain, resulting in a higher bandwidth. The overall feedback value Rf is given by: Rf = Rf b //RMRf b ,

(4.50)

with:

RMRf b = μCox

W L

MRf b

1 (|VGS | − |VT | − |VDS |)MRf b

.

(4.51)

A ﬁrst design choice regarding the feedback transistor is the type of MOS transistor. Fig. 4.8 shows two possible implementations: nMOS-type and pMOS-type. For the nMOS, the source is connected to the input, the drain to the output, the gate to a bias voltage Vb1 (for instance Vdd ) and the bulk to ground. When the photodiode generates an input current, the output voltage rises. As a result, Vgs remains nearly constant, while Vds increases. For large signals, the transistor may go into saturation, which is undesirable. The pMOS on the other hand has its drain connected to the input and its source connected to the output. The bias voltage at the gate Vb1 is now for instance ground. When a signal is applied, the source voltage of the transistor increases. So any change in Vds is reﬂected in an equal change in Vgs and the transistor will stay in the linear region, even for large signals. Therefore, a pMOS-type implementation is chosen. Second, the bulk connection of the pMOS has to be set. As a pMOS transistor is realized in an n-well, the bulk can be connected either to the source or to Vdd . In [Ing04], the principles of dynamic signal compression when the bulk is connected to Vdd are explained using a diode-coupled ac model. However, due to the bulk-eﬀect, VT increases, resulting in a larger RMRf b for the same W/L ratio. In this design, the goal is to lower the resistance value of Rf b by switching on transistor MRf b in parallel. To cover a wide range of possible values (by changing Vb1 ), a low starting value when Vb1 = 0 V is

86

4 Transimpedance Ampliﬁer Design

preferred. When the bulk is connected to Vdd , a much larger transistor width W is needed to create the same resistance value, leading to higher capacitive parasitics and a lower TIA bandwidth. Moreover, the advantages of using dynamic signal compression are not so large as the input signal is usually very small and thus no compression is needed. Therefore, in this design, the bulk is simply connected to the source. The length is chosen minimal to minimize parasitic capacitances. The width equals 10 µm, which results in a simulated Rf that ranges from 589 Ω (Vb1 = 0 V) to 2000 Ω (Vb1 > 0.6 V). The output resistance of the voltage ampliﬁer is determined by the output conductances of transistors M1 and M2 , and the resistance value of M3 . Just like MRf b , this pMOS transistor is biased in its linear region, and the resistance value RM3 is given by a similar expression as (4.51). So the output resistance equals: 1 1 Rout = // //RM3 . (4.52) gds,M1 gds,M2 The voltage gain A0 is determined by: A0 = (gm,M1 + gm,M2 )Rout .

(4.53)

When transistor M3 is switched oﬀ, the output resistance is high, leading to a high gain, which is a nice goal in TIA design (Section 4.3.1). However, generally low output resistances are pursued to avoid output loading. In this design we will have to take the value of Rout into account, as it has the same order of magnitude as Rf . Also, because the output conductance of a transistor is susceptible to process variations, the actual value of Rout and A0 might diﬀer. Because the resistance value of a transistor in the linear region shows less deviations after processing, transistor M3 can be added. However, owing to the lower gain A0 , the TIA performance will be worse. For the transistor dimensions in Table 4.2 and WM3 = 20 µm, LM3 = 0.18 µm, the output resistance varies between 644 Ω (Vb2 > 0.6 V) and 253 Ω (Vb2 = 0 V) Table 4.3 summarizes the results of the main equations derived in Section 4.3 under four extreme biasing conditions. The input photodiode is a classical n-well diode. The transimpedance gain is slightly smaller than Rf due to Rout . The maximum value equals 65 dBΩ, while the minimum value equals 54 dBΩ. For the bandwidth, (4.11) gives a too optimistic result. Summing up Rout with Rf to calculate the dominant pole, which is justiﬁed by (4.4), gives a result which corresponds better with the simulation results. Dependent on the biasing conditions, the bandwidth ranges from 440 MHz up to 1.9 GHz. As expected, a smaller Rf results in a smaller transimpedance gain but a higher bandwidth. Lowering Rout leads to a smaller voltage gain and consequently also a smaller transimpedance bandwidth. The transimpedance-bandwidth product is the largest when Vb1 = Vb2 = 1.8 V and equals 1.1 THzΩ. Table 4.4 compares the results for diﬀerent diode topologies under a ﬁxed biasing condition (MRf b and M3 both oﬀ). The diﬀerent photodiode junction capacitances cause the bandwidth to vary from 166 MHz up to 910 MHz. The

4.5 Case Studies

87

transimpedance-bandwidth product is the largest (1.6 THzΩ) for the topology with the smallest photodiode capacitance, which is the diﬀerential diode. Open-Loop and Loop Gain As the assumption Rout Rf is not valid for the inverter topology, the equations regarding open-loop and loop gain are not very accurate. However, as can be seen in Table 4.3 and Table 4.4, the simulated unity-gain frequency of the loop gain f0dB,GH equals more or less the TIA bandwidth BWT IA . The DC loop gain is always smaller than A0 and is more accurately modeled by: GHT IA,0 =

A0 . 1 + RRout f

(4.54)

Table 4.3 shows that the phase margin is the smallest (99◦ ) when both MRf b and M3 are oﬀ. Switching on MRf b lowers Rf and results in a higher f0dB,GH , but also a higher dominant pole fd,GH (4.23). Because the ratio Rout /Rf becomes larger, the loop gain GHT IA,0 drops. The result is a slight increase in phase margin. M3 is added to compensate for uncertainties in the output conductances of the transistors, which might create an unstable TIA. The simulation results in Table 4.3 show that switching on this transistor increases the phase margin, so stability is ensured. Because Rout becomes smaller, f0dB,GH drops while the dominant pole of the loop gain fd,GH remains nearly constant and the non-dominant pole fnd,GH increases in frequency. The result is that the ratio fnd,GH /f0dB,GH becomes larger, thus creating a better phase margin (4.27). The simulation results in Table 4.4 show that the input photodiodes with the largest parasitic capacitance cause the smallest phase margin. The p+ n-well diode with guard has a P.M. of 71◦ . Switching on MRf b or M3 will increase this value. Noise Fig. 4.9 shows the photodiode model which is used for the noise simulations. It consists of the junction capacitance Cdio in parallel with a very large resistor Rp (≈ 1 TΩ) which models the dark current of the photodiode. When the diode is biased forward, 1/Rp equals the ac conductance. As stated in the Eldo Device Equations Manual [Men], resistor Rs is added in series ‘to include nonidealities’. The value is determined by the parasitic resistance of the anode (for instance the p-substrate), cathode (for instance the n-well), and contacts. It is inversely proportional to the area of the diode: the larger the photodiode area, the smaller the series resistance. While resistor Rp is noiseless, resistor Rs generates thermal noise, given by: di2Rs =

4kT df. Rs

(4.55)

88

4 Transimpedance Ampliﬁer Design anode

2

diR

Rs

s

2 didio

dv2n,TIA (dB/Hz) 4kTR2f Rs

C dio

cathode

shot noise Rs total

2qIdioR2f

Rp

4kT Rs R2f R2p

1 2π RpCdio

(a)

1 BWTIA 2πRsCdio

f (Hz)

(b)

Fig. 4.9. Noise of the photodiode: (a) Eldo diode model [Men], (b) power spectral density of the diode noise at the TIA output.

The noise of the junctions itself is represented by the shot noise current source di2dio (4.32). The spectral density of the noise at the output of the TIA due to the photodiode is given by: ZT2 IA,0 2 2 dvn,T 2 IA = didio 2 Rf Rout CinT CoutT (Rf +Rout )CinT CoutT + 1 +s + Rout s A0 +1 A0 +1 A0 +1 2 Rs Rf 2 Rp 1 + sRp Cdio 2 + diRs (4.56) 2 . Rs (Rout +Rf )Cin Cdio 2 (RC)noise s + s + 1 A0 +1 A0 +1 with: (RC)noise = (Rf + Rout + Rs (A0 + 1))Cdio + (Rf + Rout )Cin .

(4.57)

This equation is valid under following conditions: • The parallel resistance Rp is very large compared to all other resistance values. • The voltage gain A0 is large. • The output capacitance CoutT has been omitted for the transfer function of the Rs noise, to keep the equations as simple as possible. • Rs has been assumed suﬃciently low to neglect its eﬀect on the transimpedance gain (4.4) and consequently also on the transfer function of the diode shot noise. Notice that only the noise at the output of the TIA, originating from the photodiode is modeled here. The inﬂuence of the other noise sources is described in Section 4.3.3 and given by (4.34).

4.5 Case Studies

89

The output power spectral density of the noise due to shot noise and Rs noise of the photodiode is depicted in Fig 4.9(b). The DC values of these noise sources are normally much smaller than the DC value of (4.34) and thus not important at low frequencies. At high frequencies (around the TIA bandwidth), the noise of resistor Rs may become very large, and comparable to the noise of the feedback resistor Rf and the equivalent input transistor Mx . When Rs (A0 + 1) Rf + Rout (due to a high A0 and/or a large Rs ), the peak value of this noise power is given by: 4kT 2 R , Rs f

(4.58)

which is depicted in Fig 4.9(b). The maximum value of the noise power is thus proportional to Rf2 , and inversely proportional to Rs : the smaller Rs , the higher the noise contribution. However, for very small Rs , the assumption Rs (A0 + 1) Rf + Rout does not hold anymore, and the peak value is given by: R A 2 f 0 , (4.59) 4kT Rs Rf + Rout which is directly proportional to Rs . The simulated output power spectral densities for several cases are depicted in Fig. 4.10. The bias voltages are always Vb1 = 1.8 V and Vb2 = 1.8 V, except in Fig. 4.10(b), where Vb1 = 0 V and Vb2 = 0 V. When both MRf b and M3 are turned oﬀ, the noise of Rf b is dominant at DC (−165 dB/Hz). The DC value due to the photodiode shot noise cannot be seen in the graphs of Fig. 4.10 as the zero of (4.56) is as low as 30 kHz. This DC value is −240 dB/Hz, except in Fig. 4.10(b) where it equals −252 dB/Hz due to the smaller Rf . The noise density of M1 is always slightly larger than the noise density of M2 . The equivalent gmx,M1 for the noise contribution of M1 in (4.34) is given by: 1 gm,M1 = , gmx,M1 (gm,M1 + gm,M2 )2

(4.60)

and an analog expression holds for gm,M2 . Because gm,M1 > gm,M2 , the same is true for their noise contributions to the output. Comparing Fig. 4.10(a) and Fig. 4.10(b) shows the eﬀect on the noise performance when transistors MRf b and M3 are turned on. The noise of M3 can still be neglected, so is not depicted in the graphs. Due to the smaller feedback resistance value of MRf b , its noise becomes dominant over the noise of Rf b . Fig. 4.10(a), Fig. 4.10(c) and Fig. 4.10(d) compare the noise performance for the three n-well photodiodes: the classical, the quasi-fractal and (one half of) the diﬀerential photodiode respectively. The larger the diode area, the smaller Rs and the higher the maximum (4.58) of its noise curve. In Fig. 4.10(a), the noise of Rs becomes even larger than the noise of Rf b , while in Fig. 4.10(d), the noise curve of Rs stays well below the noise curve of Rf . Finally, Fig. 4.10(e) and Fig. 4.10(f) show the output noise spectral densities

90

4 Transimpedance Ampliﬁer Design −160 spectral noise density [dB/Hz]

spectral noise density [dB/Hz]

−160

−180

−200

total output noise noise Rf noise M1

−220

noise M

2

noise PD −240 6 10

7

10

8

9

10 10 frequency [Hz]

−180

f

noise M1 noise M2

−220

noise M

Rfb

noise PD −240 6 10

10

10

total output noise noise R

−200

7

10

(a)

spectral noise density [dB/Hz]

spectral noise density [dB/Hz]

−200

total output noise noise R f

noise M1

−220

noise M2 noise PD 7

10

8

9

10 10 frequency [Hz]

−180

−200

f

noise M1

−220

noise M2 noise PD

−240 6 10

10

10

total output noise noise R

7

10

(c)

8

9

10 10 frequency [Hz]

10

10

(d) −160 spectral noise density [dB/Hz]

−160 spectral noise density [dB/Hz]

10

10

−160

−180

−180

−200

total output noise noise R f

noise M1

−220

noise M2 noise PD

−240 6 10

9

(b)

−160

−240 6 10

8

10 10 frequency [Hz]

7

10

8

9

10 10 frequency [Hz]

(e)

10

10

−180

−200

total output noise noise R f

noise M1

−220

noise M2 noise PD

−240 6 10

7

10

8

9

10 10 frequency [Hz]

(f)

Fig. 4.10. Simulated output noise power spectral densities of: (a) TIA with classical n-well diode (Rf = 2000 Ω, Rs = 1200 Ω), (b) TIA with classical n-well diode (Rf = 589 Ω, Rs = 1200 Ω), (c) TIA with fractal n-well diode (Rf = 2000 Ω, Rs = 1600 Ω), (d) TIA with diﬀerential n-well diode (Rf = 2000 Ω, Rs = 3000 Ω), (e) TIA with p+ n-well diode with guard (Rf = 2000 Ω, Rs = 6 Ω) , (f) TIA with n+ p-substrate diode(Rf = 2000 Ω, Rs = 5 Ω) .

10

10

4.5 Case Studies

91

Table 4.3. Hand calculations (upper part) and simulation results (lower part) of the TIA with classical n-well diode under diﬀerent biasing conditions. Vb1

1.8 V

0V

1.8 V

0V

Vb2

1.8 V

1.8 V

0V

0V

Rout

644 Ω

644 Ω

253 Ω

253 Ω

A0

16.8

16.8

6.6

6.6

Cdio

660 fF

660 fF

660 fF

660 fF

Cin

760 fF

760 fF

395 fF

395 fF

CinT

1.42 pF

1.42 pF

1 pF

1 pF

Rf

2000 Ω

589 Ω

2000 Ω

589 Ω

A0 2πRf CinT A0 2π(Rf +Rout )CinT A0 Rf A0 +1 − AR0out +1

940 MHz

3.2 GHz

500 MHz

1.7 GHz

711 MHz

1.5 GHz

440 MHz

1.2 GHz

65 dBΩ

54 dBΩ

65 dBΩ

54 dBΩ

BWT IA

640 MHz

1.9 GHz

440 MHz

1.4 GHz

ZT IA,0

65 dBΩ

54 dBΩ

65 dBΩ

54 dBΩ

ZBW

1.1 THzΩ 952 GHzΩ 782 GHzΩ 702 GHzΩ

GT IA,0

88 dBΩ

73 dBΩ

84 dBΩ

70 dBΩ

GHT IA,0

22 dB

18 dB

18 dB

15 dB

f0dB,GH

692 MHz

2 GHz

510 MHz

1.6 GHz

P.M.

99◦

103◦

111◦

113◦

vn,T IA

222 µVrms 155 µVrms 169 µVrms 128 µVrms

in,tia

0.12 µArms 0.3 µArms 0.1 µArms 0.27 µArms

dominant noise source

PD

MRf b

Rf

MRf b

for the TIAs with the smallest bandwidth and largest photodiode capacitances at their input: the p+ n-well diode with guard, and the n+ p-substrate diode. These diodes also have a much smaller Rs value, so the maximum of its noise curve is given by (4.59) and never becomes dominant. Because the zero of the ampliﬁer noise (4.34) is well separated from the TIA bandwidth, the noise curves of transistors M1 and M2 can increase and even rise above the noise curve of resistor Rf at high frequencies. Table 4.3 and Table 4.4 summarize the results for the integrated output noise and the integrated input-referred noise current. Two times the TIA bandwidth is taken as the upper integration limit. Also the noise source with the largest contribution to the total integrated noise is mentioned. Table 4.3 shows that MRf b is the dominant noise source when turned on. Otherwise, the dominant noise source is Rf b (Vb2 = 0 V) or the photodiode (Vb2 = 1.8 V)

92

4 Transimpedance Ampliﬁer Design

Table 4.4. Hand calculations (upper part) and simulation results (lower part) of the TIA with diﬀerent photodiodes (Vb1 = 1.8 V, Vb2 = 1.8 V). quasi-fractal diﬀerential p+ n-well dio-

n+ p-sub-

n-well diode

diode

de with guard strate diode

Rout

644 Ω

644 Ω

644 Ω

644 Ω

A0

16.8

16.8

16.8

16.8

Cdio

585 fF

292 fF

4.6 pF

6.8 pF

Cin

760 fF

760 fF

760 fF

760 fF

CinT

1.34 pF

1.05 pF

5.3 pF

7.6 pF

Rf

2000 Ω

2000 Ω

2000 Ω

2000 Ω

A0 2πRf CinT A0 2π(Rf +Rout )CinT 0 − AR0out Rf AA +1 0 +1

993 MHz

1.3 GHz

248 MHz

175 MHz

751 MHz

960 MHz

188 MHz

132 MHz

65 dBΩ

65 dBΩ

65 dBΩ

65 dBΩ

BWT IA

741 MHz

910 MHz

230 MHz

166 MHz

ZT IA,0

65 dBΩ

65 dBΩ

65 dBΩ

54 dBΩ

ZBW

1.3 THzΩ

1.6 THzΩ

409 GHzΩ

295 GHzΩ

GT IA,0

88 dBΩ

88 dBΩ

88 dBΩ

88 dBΩ

GHT IA,0

22 dB

22 dB

22 dB

22 dB

f0dB,GH

759 MHz

851 MHz

155 MHz

117 MHz

P.M.

97◦

91◦

71◦

75◦

vn,T IA

224 µVrms

222 µVrms

140 µVrms

140 µVrms

in,T IA

0.12 µArms

0.12 µArms

0.08 µArms

0.08 µArms

dominant

Rf

Rf

Rf

M1

noise source

owing to the higher integration bandwidth. The table also shows that the input-referred noise is the smallest for the largest value of Rf . Comparing the noise for diﬀerent diodes at the input, Table 4.4 shows that the input noise of the TIA with p+ n-well diode with guard and TIA with n+ p-substrate diode is slightly smaller. This is because the integration bandwidth in these cases is considerably lower than for the TIAs with n-well diodes. The dominant noise source in case the n-well diodes are at the input is Rf . For the TIA with p+ n-well diode with guard, the noise contribution of M1 almost equals the noise contribution of Rf , but the latter is still dominant. When the n+ p-substrate diode is at the input, the noise of of M1 dominates all other noise sources. Finally note that no attempt has been made to minimize the integrated noise for a certain photodiode input capacitance as described in Section 4.3.3. The large variation in the photodiode capacitance values results in a ratio XN that

4.5 Case Studies

93

varies between 0.2 for the diﬀerential diode and 0.02 for the n+ p-substrate diode. However, the prime goal was to compare the speed performance of the diode topologies, by amplifying the signals with identical TIA conﬁgurations that have a larger bandwidth than the intrinsic bandwidth of the respective photodiodes. 4.5.2 An Inverter-Based TIA for Test Photodiodes in 90 nm CMOS Design Goals and Implementation The design of this TIA has a lot in common with the one described in the previous section (Section 4.5.1). Again the aim is to amplify the signal from diﬀerent types of photodiodes, comparing their speed performance. The major diﬀerence is that the design is done in a 90 nm CMOS process, with minimum eﬀective gate-length of 80 nm. This is reﬂected in a higher level of Eldo transistor model, namely level 54 or BSIM4. This model is an extension of the BSIM3 model (or Eldo level 53) and addresses the MOSFET physical eﬀects into the sub-100 nm regime. BSIM4 has as much as twenty improved and/or new models compared to BSIM3 [UC 04], of which only a few are: • an accurate new model of the intrinsic input resistance for both RF, highfrequency analog and high-speed digital applications; • a new accurate channel thermal noise model and a noise partition model for the induced gate noise; • an accurate gate direct tunneling model for multiple layer gate dielectrics; • a comprehensive and versatile geometry-dependent parasitics model for various source/drain connections and multi-ﬁnger devices; • improved model for steep vertical retrograde doping proﬁles. These highly accurate models need of course several new parameters to describe the physical phenomena due to downscaling. It is clear that the ‘intuitive’ square law for the saturation current given by: Ids = K

W (Vgs − VT )2 (1 + λVds ), L

(4.61)

becomes more and more out of date [San06]. However, it is still useful to perform raw hand-calculations. The schematic of the TIA, again with diﬀerent diode conﬁgurations, is depicted in Fig. 4.11(a) and Fig. 4.11(b). The test photodiode structures now are a classical n-well diode and a quasi-fractal n-well diode (Fig. 4.11(a)), and a p+ n-well diode with guard (Fig. 4.11(b)). In the latter case, besides the detecting diode PD, also a guard diode is present. The bias voltage of the nwell (Vb3 ) should stay below 1.1 V. Because no detailed junction capacitance models are available for this technology, approximate calculations are performed to determine the total junction capacitance, including bottom-plate

94

4 Transimpedance Ampliﬁer Design Vdd

Vdd

Vb1

Vb1

MRfb

M2

Rfb

nin

M2

nout

Vin M1

MRfb

Vb2

Vout

PD

nin

nout

Vin M3

M1 C ac

Rfb

Vb2

PD Vb3

Vout

M3 C ac

guard

(a)

(b)

Fig. 4.11. Schematic of the inverter-based 90 nm CMOS TIA: (a) conﬁguration for the classical n-well diode and quasi-fractal n-well diode (b) conﬁguration for the p+ n-well diode with guard.

as well as sidewall capacitance. For the classical n-well diode, Cdio ≈ 1.4 pF, for the quasi-fractal n-well diode, Cdio ≈ 1.6 pF, and for the p+ n-well diode with guard, Cdio ≈ 6 pF. The TIA consists again of a single-stage inverter ampliﬁer (nMOS transistor M1 and pMOS transistor M2 ) and a variable feedback resistance (resistor Rf b and pMOS transistor MRf b ). The main diﬀerence with the previous design is that the dummy stage is left out. Transistor M3 operates in the linear region, and can be turned on or oﬀ by changing the bias voltage Vb2 . To have drain and source of transistor M3 biased at the same DC voltage, capacitance Cac is added, which prevents DC current from ﬂowing through M3 . The function of transistor M3 remains the same: taking care of stability problems due to process variations on output conductances gds,M1 and gds,M2 . The same TIA structure with input inductor is presented in [Ler04]. Due to the series inductor between the diode and the TIA, the bandwidth BWT IA is decoupled from the unity-gain frequency f0dB,GH of the loop gain. This way a TIA can be realized with the same gain and bandwidth compared to the regular TIA in Fig. 4.11(a), but with a smaller input-referred noise current. The detailed analysis falls beyond the scope of this text, but the interested reader is referred to [Ler04]. The design parameters of the inverter ampliﬁer are summarized in Table 4.5. The main simulation results for an ‘average’ 1.5 pF photodiode are given in Table 4.6. Because of the high resemblance with the previous TIA,

4.5 Case Studies

95

Table 4.5. Design parameters of the inverter ampliﬁer.

type L W VDSAT IDS gm gds Cgs Cgd

M1

M2

nMOS 80 nm 100 µm 0.09 V 3.8 mA 44 mS 3.5 mS 34 fF 10 fF

pMOS 80 nm 300 µm −0.12 V −3.8 mA 46 mS 3.9 mS 103 fF 36 fF

no exhaustive overview is given anymore, but only the main design issues are discussed brieﬂy. DC Operating Point As M1 and M2 are the only transistors delivering DC current, both currents should be equal: IDS,M1 = |IDS,M2 |. (4.62) Assuming the square law is still valid for the 80 nm-channel transistors in strong inversion, (4.49) gives the relationship between the widths of the transistors and the DC input voltage. Note that VDD is now only 1.1 V. In the presented design, the ratio WM1 /WM2 equals 1/3 (Table 4.5), leading to a simulated VIN = VOUT = 0.49 V. Transimpedance Gain and Bandwidth The transimpedance gain is made variable in the same way and for the same reason as in Section 4.5.1: to increase ﬂexibility when diﬀerent types of photodiodes detect light at the input. For the implementation of the ﬁxed 2700 Ω resistance, salicided p+ polysilicon is used. Due to a compact layout of 1 µm x 9 µm, the RC-constant of the resistor results in a bandwidth as high as 80 GHz. The variable resistance is realized as a pMOS transistor, with bulk connected to source. Its resistance value is given by (4.51). MRf b has minimal length and a width of 70 µm, so the resulting Rf , which is the parallel combination of Rf b and MRf b , ranges from 120 Ω to 2700 Ω. The nominal design value, resulting in a bandwidth of 500 MHz, is 680 Ω (Table 4.6). This corresponds to a transimpedance-bandwidth product of 340 GHzΩ. This value is considerably smaller than the transimpedance-bandwidth product of the inverter-based design in 0.18 µm CMOS (Section 4.5.1). As ZBW is inversely

96

4 Transimpedance Ampliﬁer Design

proportional to the input capacitance (4.19), this decrease is mainly due to the larger junction photodiode capacitance associated with deep-submicron CMOS technologies. Due to the ac-coupling capacitor Cac , the output resistor at DC is ﬁxed and determined by the output conductances of the transistors: Rout =

1 . gds,M1 + gds,M2

(4.63)

Only at higher frequencies, determined by RM3 and Cac , the resistance value of RM3 (4.51) is seen at the output, in parallel with gds,M1 and gds,M2 : Rout,ac =

1 1 // //RM3 . gds,M1 gds,M2

(4.64)

The advantage of this approach is that the DC voltage gain is now also independent of RM3 . It is given by: A0 = (gm,M1 + gm,M2 )Rout ,

(4.65)

A0,ac = (gm,M1 + gm,M2 )Rout,ac

(4.66)

while: is the gain when Cac acts as a short circuit. The possible pitfall is that Cac must be high enough to enable the reduction of the output resistance by RM3 for the frequencies of interest. The implementation of this large capacitance value in a CMOS technology requires a capacitor with a high density per unit area to limit the (expensive) area. As no MIM-capacitors are available, a metal wall capacitance structure is used [Yao04]. It uses the lateral capacitance instead of the vertical capacitance normally used. In deep-submicron technologies, the lateral spaces between metal lines in the same layer are smaller than the vertical spaces between layers, leading to a higher capacitance density. Also the lateral spacing is better controlled. The calculated capacitance per unit area is around 1.7 fF/µm2 , enabling a Cac ≈ 13 pF within the restricted area. Table 4.6 summarizes the maximum, minimum, and nominal values of Rout,ac and the corresponding A0,ac . Open-Loop and Loop Gain The behavior of open-loop gain and loop gain is the same as the behavior of A0 . At DC, they do not change when M3 is turned on or oﬀ. At higher frequencies (dependent on the value of Cac ), the inﬂuence of M3 will become more important. When instabilities occur it allows to decrease Rout and reduce the loop gain at these frequencies, in order to adjust the phase margin and maintain stability. This might be necessary because the output conductances of the transistors, which determine Rout , are subject to process variations. Table 4.6 shows that the simulated unity-gain frequency f0dB,GH equals the TIA bandwidth BWT IA . The phase margin for a photodiode capacitance of 1.5 pF equals 75◦ .

4.5 Case Studies

97

Table 4.6. Simulation results of the TIA with n-well photodiode for which Cdio = 1.5 pF. Rf b

2700 Ω

min-max 120 Ω-2700 Ω nominally 680 Ω

Rf

Rout Rout,ac

min-max 60 Ω-130 Ω nominally 90 Ω A0

A0,ac

130 Ω

11.22

min-max 15 dB-21 dB nominally 18 dB

BWT IA ZT IA,0 ZBW

500 MHz 57 dBΩ 340 GHzΩ

f0dB,GH P.M.

500 MHz 75◦

in,T IA

0.21 µArms

Noise As no detailed model is available for the junction capacitances, an estimated value of 10 Ω is taken for Rs (Fig. 4.9(a)). The noise of this resistor will never become larger than the noise of the feedback resistor Rf or input transistors M1 and M2 . Table 4.6 reveals that the input-referred integrated noise current in,T IA equals 0.21 μArms . Assuming the noise models of Section 4.3.3 are valid, Rf is the dominant noise source. 4.5.3 A Diﬀerential Bandwidth-Optimized TIA in 0.18 µm CMOS Design Goals and Implementation This TIA diﬀers in two major ways from the previous designs discussed in Section 4.5.1 and Section 4.5.2. First, it is optimized for one particular photodiode: the diﬀerential photodiode for which the dark and illuminated junctions both have a junction capacitance of 159 fF respectively. Second, the topology is totally diﬀerent: a diﬀerential common-source structure is implemented, and the voltage ampliﬁer consists of two stages. A diﬀerential ampliﬁer is actually a very natural choice in combination with the diﬀerential photodiode topology: the illuminated junctions are connected to one input while the dark junctions are connected to the other input. Note however that the input

98

4 Transimpedance Ampliﬁer Design Rf

PD PD Rf Vdd M 2a

M 2b

nout a nin a

M 1a

Vout

nout b

M 1b

nin b

ICS

Fig. 4.12. Schematic of the diﬀerential 0.18 µm TIA.

current is not truly diﬀerential: the current from the illuminated junctions consists of a drift and diﬀusion component, while the current from the dark junctions only consists of the diﬀusion component. After this diﬀerential TIA stage, the diﬀerence signal consisting only of the drift component still has to be constructed. The presented TIA is part of an optical receiver which has the ultimate goal to receive and amplify signals with bitrates as high as a few Gbit/s. The other building blocks of this receiver, together with the measurements, will be discussed in Section 6.4. Fig. 4.12 shows the circuit schematic of the diﬀerential TIA. A beneﬁt of a diﬀerential topology is that the number of stages in an ampliﬁer is not limited to an odd number. As a compromise between high bandwidth (one single-ended stage for stability reasons) and high voltage gain (three singleended stages to increase ampliﬁcation), this TIA consists of two diﬀerential amplifying stages with cross-coupled feedback. Each stage consists of the input nMOS transistors M1a -MM1b and the pMOS load transistors M2a -M2b . These transistors are biased in the linear region by connecting their gates to ground. The feedback resistor has as ﬁxed value. As a compromise between

4.5 Case Studies

99

Table 4.7. Design parameters of the two diﬀerential stages. ﬁrst stage

type L W VDSAT IDS gm gds Cgs Cgd

second stage

M1

M2

M1

M2

nMOS 0.18 µm 34 µm 0.22 V 1.95 mA 11.9 mS 0.64 mS 41 fF 12 fF

pMOS 0.18 µm 12 µm −0.94 V −1.95 mA 1.25 mS 2.2 mS 14 fF 8 fF

nMOS 0.18 µm 13 µm 0.25 V 1.1 mA 5.2 mS 0.26 mS 16 fF 5 fF

pMOS 0.18 µm 8 µm −0.95 V −1.1 mA 0.68 mS 1.7 mS 9 fF 6 fF

gain and noise on one hand and bandwidth and phase margin on the other hand, the resistance equals 5000 Ω. The resistor is implemented in high-ohmic polysilicon, and with dimensions of 2 µm x 10 µm, its 3-dB bandwidth equals almost 20 GHz. Table 4.7 shows the transistor design parameters. It is apparent that the two stages are not identical. A more optimal solution is to have a large ﬁrst stage and a smaller second stage. The hand calculations and simulations results are summarized in Table 4.8. DC Operating Point The DC current through the transistors is set by the common-mode current source ICS . Each branch carries one half of its DC current. Owing to the feedback resistor Rf , which does not carry any DC current, the input DC voltage VIN of the TIA is the same as the output DC voltage VOUT . It is determined by: ICS2 RM2 , (4.67) VOUT = VDD − 2 where ICS2 is the DC current in the second stage of the ampliﬁer and RM2 is the resistance value of M2 in the second stage, and given by (4.51). The higher WM2 , the lower RM2 and the higher VOUT . The input voltage is given by: (4.68) VIN = VGS,M1 + VDS,CS1 , where VDS,CS1 is the drain-source voltage of the transistor constituting the current source in the ﬁrst stage. Any change in WM1 will be reﬂected in a change of VGS,M1 when the current is kept constant. However, the current source will adjust its drain-source voltage VDS,CS1 such that VIN still equals VOUT given by (4.67).

100

4 Transimpedance Ampliﬁer Design

In the presented design, the simulated VIN = VOUT = 1.3 V. This is somewhat higher than the DC voltage in the designs of Section 4.5.1 and Section 4.5.2, where one half of the power supply is taken as guideline. As the signal current from the photodiode is so small, large-signal problems with the output swing will never occur. A higher DC voltage has the advantage that the input photodiode capacitance is lowered. The intermediate voltage in between the two stages equals 1.2 V. Transimpedance Gain and Bandwidth The transimpedance gain of this TIA is ﬁxed and determined by the value of Rf , which is 5000 Ω. Due to the loading of Rout , the gain is somewhat lower and equals 4566 Ω or 73 dBΩ (Table 4.8). The voltage gain is maximized by implementing two stages. The total gain A0,tot is than given by: A0,tot = A0,1 · A0,2 , (4.69) with A0,1 and A0,2 the voltage gain of respectively the ﬁrst and the second stage. Their values are determined by: A0 = gm,M1 Rout , while: Rout =

1 //RM2 . gds,M1

(4.70)

(4.71)

As explained several times in this chapter, a large voltage gain is important to achieve a maximization of the TIA bandwidth, in ﬁrst order given by (4.11). The optimization process shows that the two stages shouldn’t be identical. The ﬁrst stage can be made larger: as long as the input capacitance is small enough compared to the photodiode capacitance, the voltage gain increases with gm,M1 and so does the bandwidth. The optimum is reached when increasing WM1 results in a lower bandwidth due to the larger input capacitance and decreasing WM1 results in a lower bandwidth due to a lower voltage gain A0 . The second stage still gives some additional voltage gain, but cannot be made too large as it determines the dominant pole of the voltage ampliﬁer, and thus also the stability of the TIA. Table 4.8 shows a large discrepancy between expression (4.11) and the simulated 3-dB bandwidth. This is because the poles of the TIA are complex conjugated and cause some gain peaking. So the actual bandwidth equals 4.3 GHz, which is larger than the value predicted by (4.11). Together with a gain of 73 dBΩ, this results in a transimpedance-bandwidth product of 19 THzΩ. This is more than one order of magnitude larger than the transimpedance-bandwidth product of the designs discussed in Section 4.5.1 and Section 4.5.2.

4.5 Case Studies

101

Open-Loop and Loop Gain The frequency at which the gain margin in measured, f0dB,GH , equals 2.3 GHz, signiﬁcantly smaller than the simulated BWT IA . The phase margin is 69◦ . Any change in values which increases the TIA bandwidth will result in a smaller phase margin. For example, a larger WM1 in the second stage will increase A0 and consequently also BWT IA . But also the loop gain GHT IA,0 increases, which results in a lower phase margin. Decreasing Rf to extend the bandwidth not only results in a worse noise performance, but also increases f0dB,GH and lowers the phase margin. So allowing suﬃcient phase margin for stable operation, this TIA is truly optimized with respect to bandwidth. Noise The simulated output noise power spectral density for the several noise sources is depicted in Fig. 4.13. At low frequencies, the feedback resistor Rf is clearly the dominant noise source. At higher frequencies, the noise of the series resistance Rs of the photodiode comes into play. Both contributions to the integrated output noise are equivalent: 0.57 mVrms comes from the photodiode and 0.56 mVrms comes from Rf . The transistor noise of the second stage can be neglected, as it is suppressed by the gain of the ﬁrst stage. The noise of the transistors of the ﬁrst stage never becomes dominant for the frequencies of interest. The DC value of the transistor noise contribution is given by: 2 4kT A0,2 Rout,1 4kT γdf 4kT df + . (4.72) 4kT γgm,M1 + df ≈ 2 RM2 1 + A0,tot gm,M1 RM2 gm,M1 The noise of the linearly biased transistor M2 is determined by the thermal noise of its equivalent resistance value. As this term is considerably smaller than the ﬁrst term in (4.72) and provided that the gain A0,tot is large enough, the equivalent gmx as deﬁned in (4.34) of this two-stage diﬀerential TIA is simply given by the transconductance of the input transistor, gm,M1 . Note also that the optimum (4.44) for the input transistor is reached more or less: for αgd = 0.3, Mi = 5 (only the gain of the ﬁrst stage is important for the Miller eﬀect), fT /BWT IA = 10.7, γ = 1, A0 = 11.75 and FBW = 2, the optimum ratio between Cgs of the input transistor and he photodiode capacitance Cpd equals 0.33. In the presented design, this ratio equals 0.26, which is somewhat lower. However, this deviation is justiﬁed for following reasons: • In [Ing04] it is shown that the optimum is a very ﬂat optimum, so any deviation only leads to a small increase in noise. • A smaller input transistor lowers the current consumption for the same Vgs − VT . • Formula (4.44) is only an approximation, as it is derived for a single stage, single-ended TIA with common-source topology.

102

4 Transimpedance Ampliﬁer Design

spectral noise density [dB/Hz]

−150

−170

−190

total output noise noise R f

noise M1

−210

noise M

2

noise PD −230 6 10

7

10

8

9

10 10 frequency [Hz]

10

10

Fig. 4.13. Simulated output noise power spectral density of the diﬀerential TIA with photodiode. Table 4.8. Hand calculations (upper part) and simulation results (lower part) of the diﬀerential TIA with photodiode. Rout

ﬁrst stage

352 Ω

second stage

531 Ω

ﬁrst stage A0 second stage total

4.2 2.8 11.75

Cdio

159 fF

Cin

91 fF

CinT

250 fF

Rf

5000 Ω

A0 2πRf CinT

1.5 GHz

0 Rf AA 0 +1

−

Rout A0 +1

73 dBΩ

BWT IA

4.3 GHz

ZT IA,0

73 dBΩ

ZBW

19 THzΩ

GT IA,0

94 dBΩ

GHT IA,0

20 dBΩ

f0dB,GH

2.3 GHz

P.M.

69◦

vn,T IA

1.36 mVrms

in,T IA

0.29 µArms

4.6 Conclusions

103

Finally, the power spectral density of the total output noise is also plotted in Fig. 4.13. Note that for instance at low frequencies, the noise is 3 dB higher than the noise of the dominant noise source, Rf . This is due to the diﬀerential nature of the circuit, where every noise source appears twice and consequently also has to be counted twice.

4.6 Conclusions This chapter has covered an in-depth design analysis of the ﬁrst electrical circuit of the optical receiver: the transimpedance ampliﬁer. As a starting point, its main performance requirements have been deﬁned. The photodiode current must be converted into an output voltage with high transimpedance gain. The bandwidth of the TIA should be 0.7 times the required bitrate. The equivalent input-referred noise current must be as small as possible, while the overload current must be as large as possible to design a TIA with a large dynamic range. In this work, the focus lies on low-noise TIAs as the current produced by CMOS photodiodes is very small. The TIA with shunt-shunt feedback has been proposed as basic structure and its performance has been studied in detail. Small-signal analysis of the bandwidth reveals that allowing complex conjugated poles with a minimum amount of overshoot leads to an increase in bandwidth. This bandwidth is inversely proportional to the input capacitance (including the photodiode junction capacitance), inversely proportional to the feedback resistance, and directly proportional to the DC gain of the voltage ampliﬁer. The transimpedance gain is mainly determined by the feedback resistance. Consequently, to maximize the transimpedance-bandwidth product, the input capacitance must be small, while the voltage gain should be maximized. Design equations for the loop gain reveal that the ratio between the dominant pole of the voltage ampliﬁer and the unity-gain frequency of the loop gain must be high enough to have suﬃcient phase margin (for instance a ratio of 3 to have 72◦ phase margin). For a multiple-stage voltage ampliﬁer, this ratio even has to be larger. As a result, applications requiring a high bandwidth compared to the technology’s fT will have a single-stage topology rather than a threestage topology. The noise analysis shows that for designs aiming for a high bandwidth, the dominant noise contributor might be the feedback resistor Rf rather than the input transistor of the voltage ampliﬁer. The input-referred current noise spectrum is ﬂat at low frequencies and mainly determined by the noise current of Rf . At high frequencies, the noise spectrum rises with 20 dB/decade due to the ampliﬁer noise. Diﬀerent noise optimization techniques have been discussed which derive an optimal Cgs for the input stage of the voltage ampliﬁer. After the high-level analysis, several TIAs have been discussed at the transistor level. Two main topologies have been illustrated with some examples found in literature: the TIA with common source input stage and the TIA

104

4 Transimpedance Ampliﬁer Design

with regulated cascode input stage. Also three interesting TIA designs of the latest years at ISSCC have been considered. Finally, three TIAs implemented in standard CMOS technologies have been presented in this chapter. The ﬁrst TIA is based on a single-stage inverter ampliﬁer and used to compare the performance of diﬀerent types of 0.18 µm CMOS photodiodes. Precautions have been taken to guarantee stability under all circumstances. Depending on the photodiode capacitance, the bandwidth ranges from 166 MHz to 910 MHz with a gain of 65 dBΩ. The TIA with classical n-well diode has a transimpedance-bandwidth product of 1.1 THzΩ, while the TIA with diﬀerential diode has a transimpedance-bandwidth product of 1.6 THzΩ. Using the ISSCC designs of Section 4.4.3 as a bench-mark, these transimpedance-bandwidth product values are coming close to present stateof-the art. This design also reveals that at higher frequencies the noise of the photodiode series resistance might become important. The second design is also based on a single-stage inverter ampliﬁer, but now photodiodes implemented in a 90 nm technology are compared. With an n-well photodiode capacitance of 1.5 pF at the input, the TIA bandwidth equals 500 MHz. Having a gain of 57 dBΩ, this corresponds to a transimpedance-bandwidth product of 340 GHzΩ. The smaller transimpedance-bandwidth product is mainly due to the larger photodiode junction capacitances in nm-scale technologies. Also the voltage gain A0 does not change favorably with downscaling: in both designs, the TIA is based on an inverter ampliﬁer, where A0 is determined by the ratio of gm and gds . This comes down to a voltage gain that is directly proportional to the product of Early voltage and channel length, and inversely proportional to VGS − VT . As demonstrated by this example, deep submicron CMOS technologies only provide very limited gain. Just this high voltage gain is needed in a TIA to achieve a large bandwidth and a high transimpedance-bandwidth product. Moving to newer technologies with higher fT ’s, a diﬀerent approach should be adopted. In a design for a certain bitrate and consequently a constant bandwidth, the fT /BWT IA ratio increases with downscaling. As explained in Section 4.3.2, a multi-stage approach can now be used to increase the voltage gain, because there is enough room now to place the extra poles. The optimal ratio for minimum noise XN,opt (Cgs,opt /Cdio ), derived in Section 4.3.3, will decrease for increasing fT /BWT IA . However, this will not result in a lower current consumption, as the rise of Cdio will be much higher, requesting higher transistor widths for minimal noise and maximal bandwidth performance. The last TIA is part of a complete optical front-end receiver implemented in 0.18 µm CMOS. A diﬀerential photodiode is used to detect the light signals, which are further ampliﬁed by a diﬀerential TIA. It comprises a two-stage voltage ampliﬁer with cross-coupled feedback. A bandwidth of 4.3 GHz and a transimpedance gain of 73 dBΩ result in a transimpedance-bandwidth product of 19 THzΩ. Implementing a two-stage voltage ampliﬁer and allowing some gain peaking with complex conjugated poles, results in a TIA with large bandwidth, but with suﬃcient phase margin and low noise performance. The power

4.6 Conclusions

105

dissipation of the core circuit, without biasing, equals 11.3 mW. These results are really competitive with present state-of-the-art (Section 4.4.3), combining a transimpedance-bandwidth product of several tens of THzΩ with a bandwidth of a few GHz. Furthermore, the TIA is designed in a fully standard CMOS technology with a minimal gate-length of only 0.18 µm and a fully integrated photodiode at its input. The measurement results of all described TIAs will be revealed in Chapter 6.

5 Post-Ampliﬁer Design

5.1 Introduction The purpose of the post-ampliﬁer (PA) is to amplify the relatively small signal from the transimpedance ampliﬁer (TIA) to a level suﬃcient for reliable operation of the clock and data recovery circuit (see also Fig. 2.1). The required swing at the output of the PA is typically several 100 mV peak-to-peak. Two types of PAs can be distinguished: the limiting ampliﬁer (LA) and the automatic gain control (AGC) ampliﬁer. An LA is an ampliﬁer with no special measures to prevent the output signal from clipping or limiting. For very small input signals, the ampliﬁer operates in the linear regime, and the output voltage is proportional to the input voltage. For larger signals, clipping occurs and the output voltage remains constant. An AGC ampliﬁer consists of a variable gain ampliﬁer and an automatic gain control mechanism that keeps the output swing constant over a wide range of input swings. Whereas the LA starts to distort for large input signals, the AGC ampliﬁer reduces its gain and thus manages to stay in the linear regime. Which PA should be used, depends on whether the application allows nonlinear distortion or not. The LA is generally easier to design and its performance is often superior to an AGC ampliﬁer realized in the same technology. On the other hand, the linear transfer function of the AGC ampliﬁer preserves the signal waveform and permits analog signal processing of the output signal. The LA severely distorts the input signal when operating in the limiting regime, causing much of the information in the input to be lost. This chapter deals with the design of the LA. For further information regarding AGC ampliﬁers for optical communication circuits, the reader is referred to [Rei89, M¨ol94, Wu04, S¨ ac05, Lia06]. Section 5.2 discusses the main LA speciﬁcations, of which the most important are a high gain and a high bandwidth. Next, some recently published LAs are summarized in Section 5.3, together with a short history of the Cherry-Hooper topology. The design of a fully diﬀerential LA is addressed in Section 5.4. The optimal number of gain stages for maximal gain-bandwidth is calculated. Design equations for the CMOS Cherry-Hooper stage and the 107

108

5 Post-Ampliﬁer Design vout,p

vin,p vin

vout

vin,n

vout,n

Fig. 5.1. Input and output signals of a fully diﬀerential post-ampliﬁer (PA).

capacitive source degenerated stage are derived. Also a basic oﬀset compensation scheme is proposed. Finally, Section 5.5 presents two diﬀerent case studies which analyze the design of respectively a four-stage LA and ﬁve-stage LA with oﬀset compensation in 0.18 µm CMOS.

5.2 Performance Requirements While the TIA speciﬁcations determine the primary performance of the optical receiver, such as the sensitivity and the overload limit, the PA speciﬁcations have less impact. However, insuﬃcient PA speciﬁcations may degrade the overall receiver performance. This section deﬁnes the main PA requirements regarding gain, bandwidth, noise, input dynamic range, input oﬀset voltage, input capacitance and jitter. Gain Figure 5.1 shows a fully diﬀerential PA together with its input and output voltages. The diﬀerential input voltage vin is the diﬀerence between the two single-ended input voltages vin,p and vin,n . Similarly, the diﬀerential output voltage vout is the diﬀerence between the two single-ended output voltages vout,p and vout,n . The voltage gain of the PA, AP A , is deﬁned as the ratio of the small-signal diﬀerential output voltage to the small-signal diﬀerential input voltage: AP A =

vout = |AP A (f )|ejθ(f ) . vin

(5.1)

The higher this value, the more output signal is produced for a given input signal. The gain is speciﬁed either on a linear scale or in dB. The gain is a complex quantity, with frequency-dependent magnitude |A(f )| and frequencydependent phase-shift θ(f ). The mid-band gain is usually ﬂat, and represented by AP A,0 . For ampliﬁers with diﬀerential outputs, the gain can be measured single-endedly (vout,p or vout,n ) or diﬀerentially (vout = vout,p − vout,n ). It is important to specify in which way the gain is measured, as the diﬀerential gain is 6 dB higher than the single-ended gain.

5.2 Performance Requirements

109

Bandwidth The upper frequency at which the small-signal gain has dropped 3 dB below its mid-band value, is deﬁned as the PA bandwidth, BWP A . The deﬁnition for bandwidth is based on the assumption that the ampliﬁer operates in its linear regime: when a sine wave is applied at the input, the ampliﬁer produces a sine wave at the output. For a LA, this is not always the case, certainly not in the last stages of the amplifying chain where clipping of the signal occurs. Then the concept of bandwidth no longer applies and must be replaced by a large-signal concept such as the switching speed. However, it is always possible to reduce the input signal amplitude to the point where the LA enter the linear regime. The small-signal bandwidth also tends to be a conservative estimate for the large-signal speed of the ampliﬁer. Remember from Section 4.2 that the bandwidth of a TIA is set to approximately 0.7 times the bitrate Rb to limit the noise. Limiting ampliﬁers on the other hand have a much larger bandwidth, usually equal to the bitrate Rb [Raz03, S¨ ac05]. Noise The noise generated by the LA adds to the total optical receiver noise and thus degrades the receiver sensitivity. The overall integrated equivalent inputreferred noise current of the optical receiver i2n,OR can be expressed as: i2n,OR = i2n,T IA +

2 vn,LA . ZT2 IA,0

(5.2)

i2n,T IA is the integrated input-referred noise current of the TIA (4.3). The 2 is the integrated equivalent noise voltage at the input of same way, vn,LA the LA. Referred to the input of the optical receiver, it is divided by the transimpedance gain. For a receiver sensitivity predominantly determined by the noise of the TIA, the second term in (5.2) must be as small as possible. This becomes more critical for the following reasons: • The large bandwidth required for the post-ampliﬁer yields a greater total integrated noise. • The design of TIAs with a high transimpedance gain becomes increasingly more diﬃcult at high speeds, making the noise of the post-ampliﬁer more signiﬁcant. Input Dynamic Range The input dynamic range of the LA describes the minimum and maximum input signal for which the LA performs a useful function, in other words for which the BER is suﬃciently low. The minimum input signal is determined

110

5 Post-Ampliﬁer Design

by the sensitivity of the LA. Similar to the receiver sensitivity deﬁned in Section 2.4.2, it is the minimum peak-to-peak signal voltage at the input of the LA necessary to achieve a speciﬁed BER. The maximum input signal swing is reached when the LA produces so much pulse-width distortion and jitter that the speciﬁed BER cannot be maintained. Input Oﬀset Voltage The input oﬀset voltage, Vos , is the diﬀerential input voltage for which the diﬀerential output voltage of the PA becomes zero. Even a small input oﬀset voltage may drive the last stages of the LA in saturation. For this reason, limiting ampliﬁer usually incorporate oﬀset compensation. Input Capacitance The LA must exhibit a suﬃciently low input capacitance so that it does not reduce the TIA bandwidth signiﬁcantly. Therefore, the input transistors should be small, but this will lead to a smaller gain for the ﬁrst stage. Jitter LAs may introduce jitter in the signal. It is desirable to maintain this jitter below a few percent of the bit period.

5.3 Literature Examples A cascade of simple resistively-loaded diﬀerential pairs often proves inadequate as broadband ampliﬁer, especially if the input amplitude is small and the ﬁrst stages operate linearly. This is mainly due to the limited fT of today’s mainstream CMOS technologies. Dedicated technologies such as GaAs or SiGe have a much higher fT , making it possible to design high-speed ampliﬁers with basic diﬀerential amplifying stages [Max05]. This section gives a survey of the gain-bandwidth extension techniques used in the design of broadband LAs. Because interest in broadband ampliﬁers has always been high, some of the circuits discussed already date from the 60’s. A common way to increase bandwidth is to use inductive peaking. An integrated passive inductor is placed in series with the load resistor at the dominant node. The capacitance which limits the bandwidth at this node will resonate with the inductor. This results in a transfer function with a resonance peak around the former 3-dB frequency and an extension of the bandwidth. The resonance must occur with minimal peaking and overshoot to provide a well-behaved response to random data with small BER. Major disadvantage of this approach is the large chip area required by the integrated inductors.

5.3 Literature Examples

111

Furthermore, accurate modeling of the electro-magnetic ﬁeld is needed to characterize the inductors with their parasitics and to predict the overall circuit performance. This approach has lead to a successful LA implementation in [Gal03]. The proposed LA consists of a broadband input-matching network, ﬁve identical gain stages comprising the LA core, an oﬀset cancellation feedback loop and an output buﬀer. Besides inductive peaking, other techniques which are used to improve the gain-bandwidth of the gain stages are active feedback and a negative Miller capacitance. This way, a 3-dB bandwidth of 9.4 GHz has been realized with an overall diﬀerential gain of 50 dB. The sensitivity is 4.6 mVpp at 10 Gbit/s for a BER of 10−12 . The power dissipation of the core ampliﬁer is 100 mW, while the buﬀer consumes 30 mW. Total power consumption of the complete chip equals 150 mW from a 1.8 V power supply. One year later, the same authors propose a 40 Gbit/s LA [Gal04]. A tripleresonance structure is introduced which adds an extra inductor between two inductively peaked gain stages. Five diﬀerential triple-resonance stages provide an overall diﬀerential gain of 15 dB. Measurements of the single-ended output eyes are shown for input levels of 20 mVpp , 50 mVpp and 100 mVpp . Comparing these eyes with the simulations, results in an estimated smallsignal bandwidth of 22 GHz. The circuit consumes 190 mW from a 2.2 V power supply. To circumvent the area problem of passive integrated inductors, active inductors can be used to create gain peaking, as in [S¨ac00]. The proposed LA consists of four inversely scaled gain stages and an output buﬀer. The ﬁrst stage is a common-gate diﬀerential pair, providing a low impedance input (50 Ω). The three following stages are common-source diﬀerential pairs, and the last stage is implemented as a source follower. All gain stages have active inductor loads consisting of an nMOS transistor operating in saturation and a gate resistor. The ampliﬁer is implemented in a standard 2.5 V 0.25 µm CMOS technology and consumes 53 mW. The diﬀerential gain equals 32 dB. With a bandwidth of 3 GHz, eye diagrams at 2.5 Gbit/s showing little ISI are measured. One reason for not using active inductors is that they need a bias voltage larger than Vdd to eliminate headroom diﬃculties. Furthermore, they are unfavorable for noise performance. The LAs presented in this work are based on the circuits ﬁrst introduced by Cherry and Hooper in the early 60’s. In [Che63], they describe a design technique for the design of broadband transistor video ampliﬁers. As the ampliﬁers in that era were realized with discrete components, emphasis lies on the fact that gain and bandwidth should be insensitive to transistor parameter variations. The technique is based on the use of impedance mismatch which occurs between stages having alternate series and shunt feedback. The seriesseries feedback stage in Fig. 5.2(a) has a high input and output impedance, whereas the shunt-shunt feedback stage in Fig. 5.2(b) has a low input and output impedance. In order to stabilize the transconductance of the seriesseries feedback ampliﬁer, RE should be large enough. The transconductance is than approximated by 1/RE . In order to stabilize the transresistance of

112

5 Post-Ampliﬁer Design

RL CF

Iout

RL Vout

Vin

RF

RE

(a)

CE

Iin

(b)

Fig. 5.2. Single-stage feedback ampliﬁers after Cherry and Hooper [Che63]: (a) series-series feedback stage, (b) shunt-shunt feedback stage.

a shunt-shunt feedback ampliﬁer, it is necessary to make RF /RL suﬃciently small, so that the transresistance is determined in ﬁrst order by RF . Due to the impedance mismatch between these stages, there is almost no interaction when they are cascaded. The overall gain may be calculated fairly accurately by simply multiplying the individual gain stages. When a series-series stage is followed by a shunt-shunt stage, the approximate voltage gain is thus RF /RE . By adding the high-frequency peaking components CE and CF , the authors show that the circuits are capable of reaching a gain-bandwidth product per stage equal to fT , which is the theoretical gain-bandwidth limit for an ideal transistor. In the 80’s and early 90’s, the techniques introduced by Cherry and Hooper have been adopted in the design of wideband ampliﬁers for optical communication networks [Fau83, Rei87, P¨ oh94]. The circuits are integrated in bipolar silicon technologies. The gain stage consists of a diﬀerential transadmittance stage (TAS) with series-series feedback, followed by a diﬀerential transimpedance stage (TIS) with shunt-shunt feedback, and usually two emitter followers. Sometimes the series feedback resistance RS is omitted. This is possible if the gain peaking introduced by RS and CS is not needed to achieve the required bandwidth. The major advantage is that the gain of the TASstage, which is determined by the gm of the input transistor, can be made larger now. This results in less stages for the overall LA. The 3-stage LA presented by [Fau83] is implemented in a 5 µm bipolar technology. The gain is 60 dB while the bandwidth equals 470 MHz. Four years later [Rei87] presents a 2 µm bipolar LA characterized by a gain of 54 dB and an operating speed of 4 Gbit/s. The LA consists of three equal gain stages, an output buﬀer, an emitter-follower input stage and oﬀset control. Finally, the authors of [P¨ oh94] use a 0.4 µm bipolar technology to implement a 10 Gbit/s LA with 45 dB gain. Also this ampliﬁer consists of three gain stages, an output buﬀer, an emitter-follower input stage and oﬀset control. The major high-level diﬀerence

5.4 Design of a Fully Diﬀerential Broadband LA

113

with [Rei87] is that the last gain stage is a distribution ampliﬁer, where each output of a series-series feedback stage drives two parallel feedback stages. This way, the signal is distributed to two diﬀerential outputs. However, the authors also report that the higher loading of the stage cause an increase in the jitter. To keep this jitter within acceptable limits, the gain of this last gain stage is reduced. So a doubling of the output pads comes at the expense of a lower gain, while no motivation is given in the paper for the need of two diﬀerential output signals. Almost ten years after the > 10 Gbit/s bipolar PAs [P¨ oh94, M¨ ol94], the ﬁrst Cherry-Hooper ampliﬁer implemented in a CMOS technology is presented by [Hol03]. A test circuit, implemented in a 0.35 µm CMOS technology has 9.4 dB gain and 880 MHz bandwidth. In addition, a six-stage 0.18 µm CMOS post-ampliﬁer using modiﬁed Cherry-Hooper stages is presented. It has 43 dB diﬀerential gain and 2.1 GHz bandwidth. Whereas the authors of [Hol03] have demonstrated the usefulness of Cherry-Hooper stages in CMOS, the goal of this work is to extend the achievable bitrates further in the Gbit/s range. Furthermore will the described LA be integrated with TIA and PD to present a single-chip solution for optical front-end receivers.

5.4 Design of a Fully Diﬀerential Broadband LA Most of today’s high-performance post-ampliﬁers employ a diﬀerential topology. The main advantage of diﬀerential operation over single-ended signaling is a higher immunity to environmental noise. Ground and power supply disturbances, originating for instance from the clock and data recovery circuit, will corrupt the signal lines, but the diﬀerential (output) signal will remain intact. So diﬀerential circuits are characterized by a high common-mode rejection ratio (the diﬀerential gain divided by the common-mode rejection, where common-mode rejection is deﬁned as the diﬀerential output voltage for a common-mode input voltage, when the diﬀerential input voltage is zero) and a high power supply rejection ratio (the gain from the input to the output divided by the gain from the power supply to the output). Diﬀerential lines are not only beneﬁcial for sensitive signals, but also for noisy signals. These are for instance present in the last stages of the LA, where the signals have an amplitude of a few 100 mV and change rapidly. Due to the diﬀerential nature of the ampliﬁer, the total current drawn from the power supply remains more or less constant, and alternates between the two branches of the diﬀerential stage. This way, the stage presents a constant load to the power supply, resulting in less noise generated in the power supply. On the other hand, due to a doubling of the devices in a diﬀerential circuit, the input noise √ voltage is always 2 larger than in a single-ended ampliﬁer. However, for the post-ampliﬁer, this drawback does not counterweigh the many advantages of a diﬀerential topology.

114

5 Post-Ampliﬁer Design

This section discusses the main topics related to the design of broadband limiting ampliﬁers. First, the eﬀect of cascading several amplifying stages is examined. Next, some broadband amplifying stages are studied, where the focus lies on combining both high bandwidth and high gain using analog circuit design techniques. Finally, a basic technique for oﬀset compensation is presented. 5.4.1 Cascaded Gain Stages As the broadband LA requires both high gain and high bandwidth, cascading several amplifying stages is required to achieve a high gain-bandwidth product. Assume N second-order stages are cascaded, the overall transfer function is given by: N A1st,0 AP A = , (5.3) ( ωsn )2 + 2ζ( ωsn ) + 1 where A1st,0 is the DC voltage gain for one single stage. So the more stages are cascaded, the higher the overall small-signal DC gain AP A,0 , as it equals: AP A,0 = AN 1st,0 .

(5.4) √ As already mentioned in Section 4.3.1, a second-order system with ζ = 2/2 has a maximally ﬂat response and corresponds to a second-order Butterworth ﬁlter. Also, it can be proven that for this type of ﬁlter ωn = ω3dB . Under these conditions, the overall bandwidth of a PA consisting of N cascaded second-order Butterworth stages is given by:

√ 4 N 2 − 1. (5.5) f3dB,P A = f3dB,1st So the higher N, the smaller the overall bandwidth f3dB,P A , or the higher the required bandwidth per stage f3dB,1st to attain a predetermined overall bandwidth. The gain-bandwidth extension of N cascaded stages compared to a single stage is:

√ GBWP A 1−1/N 4 N = AP A,0 2 − 1. (5.6) GBW1st This function increases for increasing N due to the rising gain when stages are added. However, owing to the smaller bandwidth with increase of N , the function saturates and reaches a maximum. The number of stages corresponding to this maximal GBWP A can be found using following approximation: 0.9 , f3dB,P A ≈ f3dB,1st √ 4 N

(5.7)

which is valid for large enough values of N . Using this approximation, (5.6) reduces to:

5.4 Design of a Fully Diﬀerential Broadband LA 30

PA

GBW /GBW

1st

25 20

115

APA,0=20 A

=40

A

=60

PA,0 PA,0

15 10 5 0 0

5

10 15 Number of stages N

20

Fig. 5.3. Gain-bandwidth extension as a function of the number of stages N in a post-ampliﬁer.

GBWP A AP A,0 0.9 √ . (5.8) ≈ N GBW1st AP A,0 4 N √ To minimize the denominator D = 4 N N AP A,0 , the natural logarithm is taken and diﬀerentiated with respect to N : 1 dD 1 1 = − 2 ln AP A,0 . D dN 4N N

(5.9)

This equation becomes zero for N = 4 ln AP A,0 . The gain-bandwidth extension given by (5.6) is plotted versus the number of stages N for three diﬀerent values of the overall gain AP A,0 in Fig. 5.3. The optimal N corresponding to a maximal GBW is quite high: for AP A,0 = 20, N = 12; for AP A,0 = 40, N = 14; for AP A,0 = 60, N = 16. However, the plot also reveals only an incremental change in GBWP A /GBW1st for values around the optimal N . For instance, when AP A,0 = 20 and as N goes from 5 to 12, the ratio GBWP A /GBW1st only increases by 11 %. Furthermore, when N is high, the gain per stage is small, making the noise contributed by all of the stages signiﬁcant. Finally, a lot of stages also corresponds to a high power dissipation and a large chip area. For these reasons, typical high-gain LAs employ no more than ﬁve stages. For example, assume a 3 GHz 30 dB PA has to be designed. Using second-order Butterworth stages, the optimal N is 14 and the corresponding gain-bandwidth extension GBWP A /GBW1st is 11.7. However, for the reasons mentioned above, some stages may be left out. For N = 4, the gain-bandwidth extension is still 8.8. Each stage needs a GBW1st of 11 GHz, which is realized with a gain of 7.5 dB and a bandwidth of 4.6 GHz.

116

5 Post-Ampliﬁer Design

5.4.2 Broadband Cherry-Hooper Stage Classical Cherry-Hooper Ampliﬁer As discussed in Section 5.3, a technique used for many years to enhance the bandwidth of a diﬀerential ampliﬁer is the Cherry-Hooper topology. A CMOS implementation is depicted in Fig. 5.4(a). Transistors M1 and M2 form the input pair, and resistor Rf provides feedback between the drain and gate of transistor M3 respectively M4 . Rd is the load resistor. Using the original terminology of Cherry, Hooper [Che63] and their followers, transistors M1 and M2 form a diﬀerential TAS-stage with transadmittance gain gm,M1 . M3 , M4 and Rf constitute a diﬀerential TIS-stage with shunt feedback and with transimpedance gain Rf . The small-signal half circuit is shown in Fig. 5.4(b). The output resistances of the transistors are usually larger than Rf and Rd , so they are omitted. The diﬀerential small-signal gain ACH of this stage is given by: C

ACH = ACH,0

gd,M 3 1 − s gm,M 3

R

f s2 gm,M C 2 + s(RC)CH + 1 3

,

(5.10)

with: ACH,0 = gm,M1 Rf , C 2 = C1 Cgd,M3 + C1 CL + Cgd,M3 CL , Rf + Rd CL (RC)CH = Rf Cgd,M3 + C1 + . Rd gm,M3 gm,M3

(5.11) (5.12) (5.13)

C1 is the total parasitic capacitance at node n1, Cgd,M3 is the gate-drain capacitance of transistor M3 and CL is the total capacitance at the output node n3. These equations are valid as long as gm,M3 Rf >> 1 and gm,M3 Rd >> 1. As expected, the small-signal gain of the Cherry-Hooper ampliﬁer at low frequencies (5.11) is given by the product of its transadmittance gain and its transimpedance gain. This product is comparable to the gain of a diﬀerential pair because the load resistor of a diﬀerential stage is of the same order of magnitude as the feedback resistor Rf . However, the bandwidth of this stage can be seriously extended. Assuming that the denominator of (5.10) shows two separated poles, the dominant pole is in ﬁrst order given by 1/(RC)CH . Mostly, Cgd,M3 is much smaller than C1 and CL , so the ﬁrst term in (5.13) can be neglected. If it further can be assumed that Rd >> Rf , the pole at node n1 equals gm3 /C1 , and the pole at node n3 is given by gm3 /CL . Which of these nodes determines the dominant pole depends on the relative values of C1 and CL . In any case, the resistance seen by the dominant pole is only 1/gm,M3 . In a simple diﬀerential stage, the dominant pole is determined by the load capacitance CL and the output resistance. The latter one is usually much larger than 1/gm3, resulting in a smaller bandwidth.

5.4 Design of a Fully Diﬀerential Broadband LA

117

Vdd Rd Rf

Rd

n3

Rf

n4

Vout1 Vout2 I2 n1

M3

M4

n2

I1

M c3 Vin1

M c4

M1

M2

Vin2

M c1

M c2

(a)

Rf

vout

n1

gm,M1 vin 2

2

n3

gm,M3 vgs,M3 C1 Cgd,M3

Rd

CL

(b) Fig. 5.4. CMOS Cherry-Hooper ampliﬁer stage: (a) schematic, (b) small-signal half circuit.

If the design goal of this stage is to optimize bandwidth, the poles will not be separated, but complex conjugated. However, the above reasoning is very valuable for gaining insight in the major advantages of the Cherry-Hooper topology. Gain-bandwidth of the stage is enlarged by moving the poles towards higher frequencies, without the penalty of loosing signiﬁcant gain. Modiﬁed Cherry-Hooper Ampliﬁer One can even go a step further in improving the performance by raising the gain, without a corresponding decrease in bandwidth. This is realized by the

118

5 Post-Ampliﬁer Design Vdd R1 M5 n5

R1

n3b

n4b

R2

R2

n3

Rf

n6

I2

n4

Vout1 Vout2 M3

n1

M6

Rf

M4

n2

I1

M c3 Vin1

M c4

M1

M2

Vin2

M c1

M c2

(a)

Cgd,M3 n1

v gm,M1 in 2

Rf C1

n5

n3

gm,M5 vgs,M5

gm,M3 vgs,M3

vout 2 R2 CL

n3b

R1

(b) Fig. 5.5. Modiﬁed CMOS Cherry-Hooper ampliﬁer stage: (a) schematic, (b) smallsignal half circuit.

modiﬁed Cherry-Hooper ampliﬁer, depicted in Fig. 5.5(a). This stage was ﬁrst introduced in CMOS by [Hol03]. Compared to a traditional Cherry-Hooper stage, resistor Rd is split up in two resistors R1 and R2 , and transistors M5 -M6 provide source follower feedback. The small-signal half circuit is shown in Fig. 5.5(b), where again the output resistances of the transistors are left out. The diﬀerential small-signal gain AMCH is now given by: C

AMCH = AMCH,0

gd,M 3 1 − s gm,M 3

s2 (RC)2MCH + s(RC)MCH + 1

,

(5.14)

5.4 Design of a Fully Diﬀerential Broadband LA

119

with: AMCH,0 = gm,M1 Rf fMCH , R2 , fMCH = 1 + R1 AMCH,0 C 2, (RC)2MCH = gm,M1 gm,M3

(5.15)

C 2 = C1 Cgd,M3 + C1 CL + Cgd,M3 CL , Rf fMCH (RC)MCH = Rf Cgd,M3 fMCH + C1 + CL . R1 gm,M3 gm,M3

(5.18)

(5.16) (5.17)

(5.19)

Again, C1 is the total parasitic capacitance at node n1, Cgd,M3 is the gatedrain capacitance of transistor M3 and CL is the total capacitance at the output node n3. This time, the equations are valid as long as gm,M5 Rf >> 1 and gm,M3 R1 >> 1. By comparing (5.11) and (5.15), one can see that the gain at low frequencies is raised in the modiﬁed topology with the factor fMCH . This factor is mainly determined by the ratio of R2 and R1 . To increase gain, this ratio must be large. Because this factor is determined by a ratio of resistors, it is less sensitive to process modiﬁcations. The topology of Fig. 5.5 has some limitations. The major one is the small voltage headroom available in recent CMOS technologies. This problem will only get worse as linewidth scales down and consequently the available power supply drops. First, when cascading several stages, the ratio R2 /R1 can not be made extremely large, as the DC voltage at nodes n3 and n4 must be suﬃciently high to drive the next stage. Second, a critical path exists between power supply and ground, where attention must be paid to keep all transistors in saturation. The path is formed by the voltage drop over R1 , the gatesource voltage of transistor M5 (Vgs,M5 ), the voltage drop over Rf , the gatesource voltage of transistor M3 (Vgs,M3 ) and ﬁnally the drain-source voltage of biasing transistor Mc3 (Vds,Mc3 ). In a 0.18 µm CMOS technology, the VT of an nMOS transistor is typically 0.5 V. For a traditional overdrive voltage Vgs −VT of 0.2 V, Vgs,M3 and Vgs,M5 must be equal to 0.7 V. Vds,Mc3 should be larger than the saturation voltage, which approximately equals the overdrive voltage Vgs − VT of 0.2 V. As a result, the voltage drop consumed by the transistors is as large as 1.6 V. With a power supply of 1.8 V, only 0.2 V is left for the resistors. Therefore, the current through these resistors is usually low and the resistance values are designed as small as possible within the constraint of high gain. Design values will be given in Section 5.5. The result is that the approximation gm,M5 Rf >> 1 is not longer valid, and the small-signal DC gain is more accurately modeled by: AMCH,0 =

gm,M1 (R1 + R2 )(1/gm,M5 + Rf ) . R1 + 1/gm,M3

(5.20)

120

5 Post-Ampliﬁer Design

Another important issue is the inﬂuence of the ratio R2 /R1 on the bandwidth, as fMCH also appears in (RC)2MCH and (RC)MCH . Simulations of (5.14) show that a large ratio, which is needed for large gain, also results in two real separated poles, which is less beneﬁcial for bandwidth. This should be avoided, and the design must focus on optimizing both gain and bandwidth by introducing complex conjugated poles. Finally, as the circuit of Fig. 5.5(a) has a feedback loop consisting of M5 , Rf , M3 , R1 and R2 , care should be taken to ensure stability. By cutting the loop for example at node n3b, following loop gain LMCH can be found: C

LMCH = −LMCH,0

gd,M 3 1 − s gm,M 3

s2 (RC)2LCH + s(RC)LCH + 1

,

(5.21)

with: LMCH,0 = gm,M3 R1 , (RC)2LCH = Rf (R1 + R2 )C 2 ,

(5.22) (5.23)

(RC)LCH = Rf gm,M3 (R1 + R2 )Cgd,M3 + Rf C1 + (R1 + R2 )CL . (5.24) C 2 is given by (5.18), and it is supposed that gm,M5 Rf >> 1 and gm,M3 R1 >> 1. Just like the small signal gain (5.14), the loop gain has a positive zero. This is dangerous for the phase margin, as it introduces a phase rotation of −90◦ . So the stability of this loop has to be monitored very closely during the optimization of the gain-bandwidth. 5.4.3 Broadband Stage with Capacitive Source Degeneration When the disadvantages of the Cherry-Hooper stage cannot be tolerated, a broadband stage must be realized in a diﬀerent way. Fig. 5.6 shows the circuit diagram of a diﬀerential voltage ampliﬁer stage with capacitive and resistive source degeneration. In order to create a broadband response, the input transistors M1a and M1b are degenerated such that their eﬀective transconductance increases at high frequencies. This requires that resistor Rs and capacitance Cs are placed between the sources of the transistors. The eﬀective transconductance Gm,CSD of the half-circuit equivalent is given by: Gm,CSD =

gm,M1 1 + gm,M1

=

Rs 1 2 // 2sCc

,

gm,M1 (sRs Cs + 1) . sRs Cs + 1 + gm,M1 R2s

(5.25)

The zero introduced by Rs and Cs causes the eﬀective transconductance to increase at higher frequencies. The same zero appears in the transfer function ACSD of the simpliﬁed small-signal half circuit depicted in Fig. 5.6(b):

5.4 Design of a Fully Diﬀerential Broadband LA

121

Vdd R 1a

R 1b n1a

n1b

I1

Vout1 Vout2 Vin1

M 1a

M 1b

Vin2

Rs n2a

n2b

Cs

M s1

M s2

M s3

(a)

n1

vout 2

gm,M1( vin vs) 2 n2 vs

Rs 2

R1

CL

2Cs

(b) Fig. 5.6. Voltage ampliﬁer with source degeneration: (a) schematic, (b) small-signal half circuit.

1 + sRs Cs , ACSD = −ACSD,0 1 + sCL R1 1 + s 1+gRs Cs Rs

(5.26)

m,M 1 2

with: ACSD,0 =

gm,M1 R1 2R1 ≈ . Rs 1 + gm,M1 R2s

(5.27)

The approximation in (5.27) holds for gm,M1 Rs 1. The voltage gain of the source degenerated ampliﬁer features two poles. The ﬁrst one is determined by the load at the output node n1, formed by CL and R1 . The other pole is a result of the source degeneration, and a factor (1 + gm,M1 Rs /2) higher than the corresponding zero. Bandwidth extension is obtained if the zero cancels the pole at node n1, so if:

122

5 Post-Ampliﬁer Design

Rs Cs = R1 CL .

(5.28)

The 3dB-bandwidth of this stage is than given by: BWCSD =

1 + gm,M1 R2s , 2πR1 CL

(5.29)

which is a factor (1 + gm,M1 Rs /2) higher than the bandwidth of a traditional diﬀerential stage with input transistor M1 and load R1 . However, this bandwidth extension comes at the price of a lower gain, which is reduced by the same factor (5.27). Compared to a Cherry-Hooper stage where both gain and bandwidth are extended, the voltage ampliﬁer with source degeneration has a lower gain-bandwidth product, but is less complex to design, has a lower power consumption, shows less problems with a low voltage headroom and is capable of a high output swing. 5.4.4 Oﬀset Compensation According to [S¨ac05], the input oﬀset voltage of an LA should be limited to about 0.1 mV, while a high-speed MOSFET ampliﬁer has a 3σ random oﬀset voltage of around 10 mV. An oﬀset compensation circuit is needed to reduce the oﬀset voltage to the required value. Fig. 5.7 shows a classical implementation of an oﬀset feedback compensation scheme, which will also be used in the LA studied in Section 5.5.2. The DC value at the output of the two signal paths is measured through the low-pass ﬁlter Ros -Cos . The output oﬀset value (the DC component of the diﬀerential output signal) is measured and ampliﬁed with a simple resistively loaded stage with voltage gain Aos . The resulting signal is fed back to the input to take corrective actions until the output oﬀset voltage becomes zero. The oﬀset compensation circuit not only suppresses the unwanted oﬀset voltage, but also some important low-frequency components of the input signal. In other words, the oﬀset compensation introduces a low-frequency cut-oﬀ in the overall LA frequency response. As discussed in Section 2.5.2 and Section 2.6, a low-frequency cut-oﬀ causes baseline wander and data-dependent jitter if the cut-oﬀ frequency is too high. For the conﬁguration of Fig. 5.7, the cut-oﬀ frequency is given by: fLF =

AP A Aos + 1 . 2πRos Cos

(5.30)

Note that AP A Aos is the loop gain of the oﬀset compensation loop. As a high gain AP A is one of the primary speciﬁcations of the PA, the values of Ros and Cos must be quite large to obtain a small cut-oﬀ frequency. In CMOS technologies, these high values can be realized by using some analog extensions which have become widespread: MiM-capacitors with a high capacitance per unit square and high-ohmic poly-resistors.

5.4 Design of a Fully Diﬀerential Broadband LA

123

APA

Vin

A1st

A1st

A1st

Vout

Ros Cos

Aos

Ros

Cos

Fig. 5.7. Block diagram of an LA with oﬀset compensation.

While a low cut-oﬀ frequency is needed to minimize ISI and jitter, the main disadvantage is the long compensation settling time. For most point-topoint communication links, long compensation times are acceptable, but they pose a severe obstacle for upcoming many-to-one links like passive optical networks. Each input channel may have diﬀerent power levels and therefore demand diﬀerent oﬀset settings of the ampliﬁer. The speed of the oﬀset compensation loop will therefore determine how quickly one can change between channels. Therefore [Cra05] proposes a peak detector structure and a variabletap feedback system to improve the trade-oﬀ between settling time and datadependent jitter. The oﬀset of the diﬀerential ampliﬁer is not estimated from the diﬀerence in DC values of its two outputs, but from the diﬀerence in peak values of its outputs. So a peak detector measures the output oﬀset voltage of the LA, and an integrator ﬁlters the instantaneous peak detector output and forces the steady-state output oﬀset voltage to be zero. Since peak information is lost when the gain stages of the LA become saturated, peak detectors are placed at the output of each LA stage and the last unsaturated output is used to sense the oﬀset. To demonstrate the technique, a 7-stage LA is fabricated in a 0.18 µm CMOS process. The prototype is tested up to 3.125 Gbit/s with input amplitudes ranging from 2.5 mVpp to 50 mVpp . The total diﬀerential gain is 42 dB. Oﬀset settling times less than 1 µs are measured while still maintaining SONET OC48 jitter levels. Finally note that often a 50 Ω matching network at the input of the LA is included with the oﬀset compensation circuit, as for example in [P¨oh94, Gal03, S¨ ac05]. This is especially necessary for stand-alone ampliﬁers which are expected by the (measurement) equipment to have a 50 Ω input impedance and to drive a 50 Ω load. As the ultimate goal of this work is to integrate a complete opto-electrical analog front-end with PD, TIA and LA, the issue of input matching is not addressed.

124

5 Post-Ampliﬁer Design

5.5 Case Studies The design simulations of two LAs are considered in this section. The focus lies on the primary speciﬁcations of the PA, namely gain and bandwidth. First a LA with four cascaded Cherry-Hooper stages is discussed, second a ﬁve-stage LA with oﬀset compensation is described. The measurement results of these LAs, realized together with high-speed output buﬀers in a 0.18 µm CMOS technology, will be treated in Section 6.4 and in Section 6.5. 5.5.1 A Four-Stage LA in 0.18 µm CMOS This LA consists of a plain cascade of the modiﬁed Cherry-Hooper stages depicted in Fig. 5.5. Whereas in [Fau83, Rei87, P¨ oh94, Hol03] emitter or source followers are placed between the cascaded stages, they are omitted in the described implementation, as they only degrade the gain performance. Current branches I1 with diode-connected transistor Mc2 and I2 with diode-connected transistor Mc4 are common to all stages. As derived in Section 5.4.2, the major advantage of the modiﬁed Cherry Hooper stage over a simple resistively-loaded diﬀerential stage, is an increase in both gain and bandwidth. The most important design parameters are summarized in Table 5.1. All transistors, except for the common-mode current source transistors, have minimal gate length. Due to the limited voltage headroom of 1.8 V, the saturation voltage VDSAT (≈ VGS − VT ) of the high-frequency transistors is slightly below 0.2 V. The gate length L of the current mirror transistors is not chosen minimal, but equals 0.8 µm, for the following reasons: • In [San06] it is shown that the current diﬀerence in the mirror is proportional to the diﬀerence in drain-source voltage, and inversely proportional to the product of Early voltage and channel length L. The larger L, the ﬂatter the Ids -Vds curve and the smaller the current diﬀerence between two transistors with unequal drain-source voltages. • The CMOS current and VT mismatch parameters are inversely proportional to the square root of the area W L of the transistor. Note also that Rf is as small as 40 Ω to limit the voltage drop over this resistor. Drawback is a smaller DC gain (5.15). In Fig. 5.8 the simulated frequency response for one stage and for the complete LA is depicted. The gain per stage equals 6.8 dB, which results in an overall gain of 27.4 dB. The ﬁrst stage is slightly diﬀerent from the following stages, as an LC input network is included in the simulations to take bondwires, bond pads and ESD-protection into account. This stage is of third order and has a bandwidth of 5.2 GHz. The next stages are all second order stages and have a 3-dB frequency equal to 6.7 GHz. Their gain-bandwidth product equals 14.6 GHz. The LA has an overall simulated bandwidth of 4 GHz, which corresponds quite well with the bandwidth predicted by (5.5). The gainbandwidth of the complete LA is 94 GHz, so the gain-bandwidth extension as

5.5 Case Studies 30

125

10

gain [dB]

gain [dB]

20 10 0 −10 −20 6 10

0

1st stage 2nd stage 3th stage output 7

10

5

first CH stage other CH stages 8

9

10 10 frequency [Hz]

10

10

−5 6 10

7

10

8

9

10 10 frequency [Hz]

(a)

10

10

(b)

Fig. 5.8. Simulated gain of the four-stage LA: (a) gain after each stage and at the output, (b) gain of the individual building blocks.

Table 5.1. Design parameters of the Cherry-Hooper stage in the four-stage LA. M1 /M2 M3 /M4 M5 /M6 type L W VDSAT IDS gm gds Cgs Cgd I1 I2 R1 R2 Rf

nMOS 0.18 µm 34 µm 0.17 V 0.78 mA 7.5 mS 0.46 mS 44 fF 12 fF

nMOS 0.18 µm 44 µm 0.17 V 1.1 mA 11 mS 0.39 mS 56 fF 16 fF

nMOS 0.18 µm 36 µm 0.16 V 0.78 mA 8.1 mS 0.32 mS 47 fF 13 fF

1.6 mA 2.5 mA 200 Ω 400 Ω 40 Ω

deﬁned in (5.6) equals 6.4. The circuit with biasing consumes 19 mA from a 1.8 V power supply. Compared to recently published papers in 0.18 µm CMOS ([Hol03, Gal03, Gal04, Cra05], see Table 6.8), the gain-bandwidth product of this circuit is not that high, but the power dissipation is very low: compared to [Gal04], the power dissipation is almost six time smaller.

126

5 Post-Ampliﬁer Design

5.5.2 A Five-Stage LA with Oﬀset Compensation in 0.18 µm CMOS The block diagram of the second LA is depicted in Fig. 5.9. It consists of an input buﬀer, ﬁve fully diﬀerential amplifying stages and oﬀset compensation feedback. The ﬁrst two stages are non-inverting Cherry-Hooper stages with negative impedance converters (CH with NIC), the last three stages are inverting voltage ampliﬁers with capacitive source degeneration (VA with CSD). The circuit schematic of the input buﬀer and the oﬀset compensation circuit are shown in more detail. A positive oﬀset voltage at the output of the LA will lead to nosp > nosn at the input of the oﬀset compensation feedback ampliﬁer. As a result, the current through Mos1a and consequently also through R1a will increase. Analogously, the current through Mos1b and R1b will decrease. Therefore, the DC input voltage of ninp decreases while the DC input voltage of ninn increases, both compensating for the positive output oﬀset voltage. The values of Ros and Cos , which make up the low-pass ﬁlter, must be chosen carefully. Too small values create a relatively high low-frequency cut-oﬀ. As a result, lower frequency components in the prbs data are considered as DC voltage variations and compensated for. On the other hand, large values of Ros and Cos generate longer settling times. In the described design, the simulated low-frequency cut-oﬀ (5.30) is 700 kHz. The input stage acts as a buﬀer between the previous building block (which is an analog equalizer as discussed in Section 6.5) on one hand and the ﬁrst amplifying stage and the oﬀset compensation ampliﬁer on the other hand. To minimize the load on the equalizer, the input transistors are very small (WM1 = 6 µm, LM1 = 0.18 µm). Capacitive source degeneration is added to increase bandwidth. A detailed circuit schematic of the modiﬁed Cherry-Hooper stage is depicted in Fig. 5.10. To increase the bandwidth of this broadband stage even further, a negative impedance converter (NIC) [Gal03] is added between output nodes n3 and n4. If the gate-drain capacitance of M7 and M8 is neglected, the impedance ZN IC between the drains is expressed by: ZN IC = −

gm,M 7 sCc

+

Cgs,M 7 Cc

+2

gm,M7 − sCgs,M7

,

(5.31)

where Cc is the compensation capacitance and Cgs,M7 is the gate-source capacitance of transistors M7 and M8 . Or, for frequencies well below the fT of the transistors: 1 1 Cgs,M7 + +2 . (5.32) ZN IC ≈ − sCc gm,M7 Cc The impedance ZN IC consists of a capacitive part (−Cc ) in series with a resistive part. This negative capacitance partly compensates for the capacitance at nodes n3 and n4. However, a good design choice has to be made, as a too large value of Cc can cause gain peaking and ringing.

5.5 Case Studies

127

Vdd R 1a

LA core

R 1b nin n

noutp

CH

Vin with Vin1

M 1a

M 1b

NIC

Vin2

Rs

CH with NIC

VA with CSD

VA with CSD

nin p

VA with CSD

Vout

noutn

Cs

I1

I1

Ros nosp

M os1a

M os1b

Ros nosn

Cos

Cos

Ios

Fig. 5.9. Block diagram of the ﬁve-stage LA with detail of the input buﬀer and oﬀset compensation circuit.

The design parameters of the CH stage with NIC are summarized in Table 5.2. To relax the biasing of the transistors in the critical path R1 -M5 -Rf -M3 -Mc3 , and optimizing gain-bandwidth, zero-VT transistors are used for the source follower feedback transistors M5 -M6 . These transistors are standard available in the 0.18 µm CMOS technology used, but have a minimal gate length of 0.3 µm. Comparing the saturation voltages VDSAT with the ones from the design discussed in Section 5.5.1, reveals that the saturation voltages are higher and come closer to the traditional value of 0.2 V. The current mirror transistors have even higher values in order to generate a better deﬁned current. Furthermore, the ratio R2 /R1 and the feedback resistor Rf have larger values in this design. Both measures result in a higher gain (5.15). Finally, note that the compensation capacitor Cc is realized as a series connection of two MiM-capacitors, with the common node connected to ground. This way, the parasitic capacitance to ground is eﬀectively taken into account during simulations. Since a large output swing is not possible with this bandwidth optimized Cherry-Hooper stage, a voltage ampliﬁer with capacitive source degeneration (VA with CSD) is used in the last stages of the amplifying chain. The design equations of this stage have been discussed in Section 5.4.3 and the circuit schematic is shown in Fig. 5.6. The design parameters are given in Table 5.2.

128

5 Post-Ampliﬁer Design Vdd

M5 n5

R1

R1

n3b

n4b

R2

R2

n3 Vout1

n1

Vin1

M3

Rf

M7

M8

I3

Cc

M1

n6

Vout2 n4

NIC

Rf

M6

M4

n2

I3

M2

I2

Vin2

I1

Fig. 5.10. Modiﬁed CMOS Cherry-Hooper with negative impedance converter (NIC).

The source degeneration capacitor Cs is also realized as a series connection of two MiM-capacitors. Finally, the simulated gain of the LA is depicted in Fig. 5.11(a) together with the gain after each stage. The transfer function of the separate gain stages is shown in Fig. 5.11(b). The CH stage with NIC has a simulated bandwidth of 7.6 GHz and a gain of 10 dB. The gain-bandwidth of this stage is 24 GHz, which is a gain-bandwidth improvement of almost 10 GHz compared to the CH stage discussed in Section 5.5.1. The source-degenerated ampliﬁer has a simulated bandwidth of 9 GHz, which results with a gain of 6 dB in a gainbandwidth of 18 GHz. The complete LA has a simulated small-signal gain of 38 dB, an overall 3-dB bandwidth of 5 GHz and a gain-bandwidth as high as 397 GHz. This should be suﬃcient to amplify 5 Gbit/s data with a low BER. The gain-bandwidth extension (5.6) over the Cherry-Hooper stage is 16.5 while the gain-bandwidth extension over the source-degenerated ampliﬁer is 22. Due to the oﬀset compensation circuit, the transfer function has a low-frequency cut-oﬀ of 700 kHz. This is still more than ten times smaller than the smallest frequency component in 231 -1 500 Mbit/s prbs data. Amplifying data with a smaller bitrate or more consecutive ones and zeros might result in baseline wander. The on-chip simulated output swing is 1.2 Vpp . The LA consumes 40 mA from a 1.8 V power supply. Comparing these values with present state-of-the-art (Table 6.8), this ampliﬁer competes with other

5.6 Conclusions

129

Table 5.2. Design parameters of the Cherry-Hooper stage with NIC and the voltage ampliﬁer with CSD in the ﬁve-stage LA. CH with NIC M1 /M2 M3 /M4 type L W VDSAT IDS gm gds Cgs Cgd

nMOS 0.18 µm 17 µm 0.23 V 1.2 mA 6.4 mS 0.3 mS 20 fF 6 fF

I1 I2 I3 R1 R2 Rf Cc Rs Cs

M5 /M6

nMOS zero-VT nMOS 0.18 µm 0.3 µm 44 µm 20 µm 0.19 V 0.25 V 1.7 mA 1.2 mA 13 mS 5.7 mS 0.7 mS 0.66 mS 53 fF 51 fF 16 fF 11 fF 2.6 mA 3.5 mA 0.5 mA 70 Ω 280 Ω 70 Ω 2 x 75 fF -

VA with CSD M7 /M8

M1a /M1b

nMOS 0.18 µm 8 µm 0.2 V 0.5 mA 2.8 mS 0.14 mS 10 fF 3 fF

nMOS 0.18 µm 20 µm 0.25 V 1.8 mA 8 mS 0.43 mS 24 fF 7 fF 1.9 mA 400 Ω 100 Ω 2 x 702 fF

recently published 0.18 µm limiting ampliﬁers, featuring a high gain and a high bandwidth, combined with a relatively low power dissipation.

5.6 Conclusions This chapter has covered diﬀerent design techniques needed for the realization of high-gain broadband limiting ampliﬁers. First, the main requirements for this ampliﬁer needed in order to generate high quality data signals for the clock and data recovery circuit have been discussed. The primary speciﬁcations are a high gain and a bandwidth equal to the bitrate aimed for. Other considerations are noise, input dynamic range, input oﬀset voltage, jitter, and loading of the transimpedance ampliﬁer by the input capacitance. Next, a discussion of some recently published high-performance CMOS LAs has been given. They are mainly based on inductive peaking, either by using passive or active inductors. To circumvent the drawbacks of this technique, another technique is applied in this work which goes back for many years: cascading transadmittance and transimpedance gain stages. This topology has

130

5 Post-Ampliﬁer Design

40

10

30 gain [dB]

gain [dB]

20 10 0

1st stage 2nd stage 3th stage 4th stage output

−10 −20 −30 4

10

6

0 CH with NIC VA with CSD 8

10 10 frequency [Hz]

(a)

5

10

10

−5 6 10

7

10

8

9

10 10 frequency [Hz]

10

10

(b)

Fig. 5.11. Simulated gain of the ﬁve-stage LA with oﬀset-compensation: (a) gain after each stage and at the output, (b) gain of the individual building blocks.

ﬁrst been proposed by Cherry and Hooper in the early 60’s by using a cascade of series-series feedback and shunt-shunt feedback ampliﬁers. Later, the technique is taken over by BiCMOS and CMOS designers for the realization of broadband ampliﬁers for optical communication networks. The most important issues concerning the design of a broadband diﬀerential LA have been treated in the following section. The optimal number of stages as a compromise between gain-bandwidth, area, power dissipation and noise has been found to be equal to ﬁve. An in-depth small-signal analysis of a Cherry-Hooper stage and a slightly modiﬁed Cherry-Hooper stage has been given. The main improvement of this stage compared to a diﬀerential stage with resistive loads, is an increase in both gain and bandwidth. The main limitations are that a suﬃciently high power supply is needed for DC biasing and that the design complexity is rather high. As an alternative, a broadband voltage ampliﬁer with capacitive and resistive source degeneration has been implemented. This stage increases the bandwidth, but at the cost of a corresponding decrease in gain. The implications of the traditional oﬀset compensation feedback loop have been studied and an alternative solution from literature based on peak detection and lower settling times has been discussed. Finally, two diﬀerent case studies have been presented to illustrate the trade-oﬀs encountered during the design of a LA. The ﬁrst LA consists of a simple cascade of four modiﬁed CMOS Cherry-Hooper stages. Each stage has a bandwidth of 6.7 GHz and a gain of 6.8 dB. The total gain of the four cascaded stages equals 27.4 dB, which results with an overall 4 GHz bandwidth in a gain-bandwidth product of 94 GHz. In the second LA design, this gain-bandwidth factor is more than four times improved and equals 397 GHz. This is achieved by using two Cherry-Hooper stages with negative impedance converters and three source-degenerated voltage ampliﬁers. Moreover, this LA

5.6 Conclusions

131

features oﬀset cancellation. The gain equals 38 dB and with a bandwidth of 5 GHz a bitrate of 5 Gbit/s should be feasible with low BER. This circuit, characterized by a high gain-bandwidth product combined with a relatively low power dissipation of 72 mW, outperforms most of the recently published 0.18 µm CMOS limiting ampliﬁers. The measurement results of these two LAs, including high-speed eye diagrams, will be shown in Chapter 6.

6 CMOS Realizations

6.1 Introduction After the theoretical design of the CMOS PD, the TIA and the LA, this chapter deals with four practical CMOS realizations. The TIAs and LAs have been analyzed in previous chapters, only some additional building blocks like the output buﬀers need to be covered here. The main focus lies on the measurements and the interpretation of the results. Each section is dedicated to a diﬀerent implementation. In Section 6.2, test photodiodes with a TIA in a 0.18 µm CMOS technology are discussed, followed in Section 6.3 by test photodiodes with a TIA in a 90 nm CMOS technology. The chip presented in Section 6.4 contains a 0.18 µm LA and high-speed output buﬀer. Finally, the diﬀerent building blocks are brought together in Section 6.5, where a completely integrated 0.18 µm CMOS optical receiver, working at Gbit/s bitrates, is described. One important challenge in opto-electronics is to focus the light from the transmitter on the photodiode. For the labo experiments, a ﬁber approach is chosen. A commercial multi-mode ﬁber is stripped and a clean cleavage is provided by a diamond knife. Another possibility is to use a pigtail style focuser. This is a ﬁber with at one side a regular LC-type connector, but at the other side a lens to focus the light beam. The spot diameter is 100 µm, a few tens of µm larger than the diameter of the implemented diodes. Despite the resulting optical losses, the measurements with the focuser also have advantages. First, the bare ﬁber must be located very close to the chip surface, leading to unwanted collisions with the top oxide. The working distance of the focuser is always a few mm, so oxide damage is avoided. Second, the stripping and cutting of the bare ﬁber is a very time-consuming and precise activity, while the focuser is always immediately on hand. The cost of the focuser is high, but it can be reused during many measurements over many years. The bare ﬁber can be worthless after one day due to a bad ﬁber cut, an unwanted collision or some small dust particles.

133

134

6 CMOS Realizations

Fig. 6.1. Opto-electrical measurement set-up. The inset shows a detail of the Gbit/s optical receiver IC implemented in a 0.18 µm CMOS technology, and the bare ﬁber that is used to focus the 850 nm light beam on the photodiode.

Fig. 6.1 shows a typical labo measurement set-up of an opto-electrical IC. The chip is ﬁrst wire-bonded on a ceramic substrate and mounted in a CopperBeryllium box, serving as a reference ground. A hole is made in the top of the box so that light signals can reach the photodiode. The box with substrate and chip is placed vertically on a precision multi-axis positioning table. Five screws are available to position the chip and/or rotate the ﬁber end. A vertical microscope assists the ﬁber positioning. At the inset of Fig. 6.1, a detail of the 0.18 µm optical receiver IC is shown, and the bare ﬁber tip can be clearly distinguished.

6.2 Test Photodiodes with TIA in 0.18 µm CMOS

135

6.2 Test Photodiodes with TIA in 0.18 µm CMOS As already mentioned in Section 4.5.1, the main purpose of this ﬁrst chip is to compare the performance of diﬀerent kind of photodiode topologies. The TIA is the same for every photodiode. First the layout of the photodiodes and the design of the receiver circuit are discussed. This is followed by an interpretation of the measurement results, of which the most successful ones are published in [Her04b, Her04c, Her06a]. 6.2.1 Circuit Description Photodiodes The ﬁve test photodiodes are: a classical n-well diode, a quasi-fractal nwell diode, a diﬀerential n-well diode, a p+ n-well diode with guard and an n+ p-substrate diode. Their junction capacitances are respectively 660 fF, 585 fF, 292 fF, 4.6 pF and 6.8 pF. All diodes have an area of 100x100 µm2 . The layout of the classical n-well diode, the n+ p-substrate diode and the p+ n-well diode with guard is straightforward. They all have 10 square junctions per diode side (Ns in Sections 3.5.1 and 3.5.2), or 100 junctions in total. Between the junctions are substrate contacts to minimize the substrate resistance. The layout of the classical n-well diode is represented schematically in Fig. 3.9. The layout of the n+ p-substrate diode is quasi the same, only the n-well regions are replaced by n+ regions. The layout of the p+ n-well diode with guard is represented schematically in Fig. 3.11. Every n-well square has two p+ regions surrounded by n-type contacts. The layout of the two other diodes is slightly more complicated. The layout of the quasi-fractal n-well diode is based on a maximization of side-wall capacitance, as this junction extends from the silicon surface down to the bottom of the n-well. A fractal is a well-known concept in mathematics and is deﬁned as an object or quantity that displays self-similarity on all scales. The object repeated in the layout of the quasi-fractal topology (Fig. 6.2(a)) is the n-well cross. As can be seen in the detail, the cross at the lowest level has eight extra branches on each side and the iterated pattern stops. Every n-well junction is surrounded by substrate contacts to minimize its parasitic resistance. The diﬀerential diode, depicted in Fig. 6.2(b), consists of an alternating pattern of illuminated and dark junctions. Subtraction of these two signals cancels the slowly diﬀusing substrate carriers. The total number of junction ﬁngers (Nf in Section 3.5.3) equals 32. Measures have been taken to minimize substrate and contact resistance: every junction is surrounded by substrate contacts, every ﬁnger is divided into halves to provide extra substrate contacts and the junctions have additional connection stripes in horizontal direction. The covering metal used to block the light is metal 3, as metal 1 and metal 2 were needed for routing.

136

6 CMOS Realizations

(a)

(b) Fig. 6.2. Detailed layout of: (a) the quasi-fractal n-well diode, (b) the diﬀerential n-well photodiode, both implemented in a 0.18 µm CMOS technology.

TIA and CSDA Fig. 6.3 shows a schematic of the receiver. It consists of two identical transimpedance ampliﬁers (TIA1 and TIA2 ), a complementary self-biased diﬀerential ampliﬁer (CSDA) [Baz91, Pie04] and an output buﬀer to drive the 50Ω load. For the diﬀerential photodiode, diode PD1 corresponds to the illuminated junctions, while diode PD2 corresponds to the dark junctions. The slow

6.2 Test Photodiodes with TIA in 0.18 µm CMOS

137

Vdd R f1

M2

M2c

M2a to output buffer

M1a

M1

R f2

nbias

M1b

M3 TIA2

TIA1 PD1

M4

M2b

PD2

M1c CSDA

Fig. 6.3. Simpliﬁed schematic of the 0.18 µm CMOS receiver circuit, needed to amplify the currents generated by the test photodiodes.

diﬀusion carriers detected by the two diodes appear as a common-mode signal at the two inputs of the CSDA and are suppressed. Only the fast current component, which is mainly the drift current, is then ampliﬁed. For the other topologies, diode PD1 is the one that captures the signal, while diode PD2 is a dummy diode placed for biasing and matching. The design of the TIA has been discussed thoroughly in Section 4.5.1. As the measurements always have been performed with Vb2 =1.8 V, transistors M3 , M1d and M2d shown in Fig. 4.7(a) are left out in the simpliﬁed schematic depicted in Fig. 6.3. The CSDA consists of two complementary diﬀerential stages, from which the loads have been removed. Transistors M1a , M1b and M1c make up the n-type half, while transistors M2a , M2b and M2c make up the p-type half. The gates of two complementary input transistors are connected so that the input stage is now an inverter. The transconductance is approximately doubled compared to the transconductance of a conventional diﬀerential stage. In order to create a stable current through biasing transistors M1c and M2c , no external voltage is applied, but their gates are connected to the internal ampliﬁer node nbias. This self-biasing of the ampliﬁer creates a negative feedback loop that stabilizes the bias voltages and makes it less sensitive to process or temperature variations. Because the voltage at nbias equals about one half of the power supply, transistors M1c and M2c operate in the linear region. Consequently, the voltages at their drains may be set very close to the supply voltages. So the output swing of this ampliﬁer approaches the power supply. Table 6.1 summarizes the design parameters of the CSDA.

138

6 CMOS Realizations

Table 6.1. Design parameters of the complementary self-biased diﬀerential ampliﬁer (CSDA). M1a /M1b M2a /M2c

M1c

M2c

type nMOS pMOS nMOS pMOS L 0.18 µm 0.18 µm 0.18 µm 0.18 µm W 40 µm 80 µm 40 µm 80 µm 0.25 V 0.26 V 0.26 V VDSAT 0.17 V 1.2 mA 1.2 mA 2.4 mA 2.4 mA IDS 11 mS 9.1 mS 7.7 mS 7.2 mS gm 0.5 mS 0.4 mS 12 mS 5.1 mS gds 47 fF 99 fF 44 fF 99 fF Cgs 15 fF 28 fF 26 fF 37 fF Cgd

The single-ended output of the CSDA is connected to the output buﬀer. It is realized as a single-stage inverter with an nMOS diode load to control the DC threshold voltage. This last stage consumes 1.4 mA from the 1.8 V supply voltage. Finally, a major advantage of this receiver topology is that TIA, CSDA as well as the output buﬀer all have a CMOS inverter topology, which makes it very suitable to implement in standard digital CMOS technologies. 6.2.2 Measurements All test photodiodes are integrated with the ampliﬁer stages in a standard 0.18 µm 1.8 V CMOS technology. No additional masks are used to enhance the performance of the photodiodes. On top of the diodes, there is only the standard dielectric stack, no anti-reﬂective coating. The chip photograph is depicted in Fig. 6.4. The total chip area taken by the ﬁve receivers, including bond pads and decoupling capacitors, equals 1x3.6 mm2 . Every photodiode is followed by an identical amplifying circuit that consumes only 17 mW. The optical source used during measurements is a commercially available 850 nm Inﬁneon transmitter. The average optical power is −6 dBm, and for sensitivity measurements this signal is attenuated by an EXFO attenuator. The electrical 27 -1 prbs data stream is generated by the HP data generator. The eye diagrams are constructed by triggering the Tektronix oscilloscope and by applying a display setting of inﬁnite persistence. BER and jitter measurements are obtained from the SyntheSys BitAlyzer. Fig. 6.5 compares the eye diagrams of the test diodes at 300 Mbit/s. A 27 -1 prbs data stream with an average input optical power (Popt ) of −7 dBm is applied. The slowly rising tail originating from the diﬀusing substrate carriers can be clearly distinguished in the eye diagram of the classical n-well diode (Fig. 6.5(a)). The eye quality of the quasi-fractal n-well diode (Fig. 6.5(b)) is slightly better, as relatively more carriers are generated now in the side-wall

6.2 Test Photodiodes with TIA in 0.18 µm CMOS

139

Fig. 6.4. Chip photograph of the ﬁve testdiodes with amplifying circuit in 0.18 µm standard CMOS.

(a)

(b)

(c)

(d)

Fig. 6.5. Eye diagrams of the 0.18 µm test diodes with amplifying circuit. The input signal has a bitrate of 300 Mbit/s and Popt =−7 dBm. The diﬀerent diodes are: (a) classical n-well diode, (b) quasi-fractal n-well diode, (c) p+ n-well diode with guard, (d) diﬀerential n-well diode.

140

6 CMOS Realizations

Fig. 6.6. Eye diagram of the 0.18 µm n+ p-substrate diode with amplifying circuit. The input signal has a bitrate of 100 Mbit/s and Popt =−7 dBm.

space charge regions. However, the improvement is not that large, because the n-well regions are surrounded by p-well regions with a higher doping proﬁle as the p-substrate, and so the side-wall regions have a limited width. The eye diagram of the third structure, the p+ n-well diode with guard (Fig. 6.5(c)), shows a larger improvement in speed: the edges are steeper and the jitter is less. However, the voltage scale reveals that the signals have a smaller amplitude. This is due to the lower responsivity of this diode topology. The eye diagram of the diﬀerential diode shows the best data quality: the eyeopening is much wider, the rising and falling edges are steeper and the jitter is only 80 ps compared to 310 ps. This progress is achieved without a large reduction of the output swing. The results of one teststructure are not yet shown: the n+ p-substrate photodiode. As expected, this photodiode has the worst performance. The maximum bitrate that can be achieved with an average input optical power of −7 dBm is 100 Mbit/s. The eye diagram is depicted in Fig. 6.6. The eye diagrams in Fig. 6.7 illustrate the high-speed capabilities of the diﬀerential PD with TIA and CSDA. The optical input signal has a bitrate of 500 Mbit/s (Fig. 6.7(a)) respectively 622 Mbit/s (Fig. 6.7(b)), and Popt =−7 dBm. Even at these bitrates, the jitter is small and the eye opening is wide compared to the eye opening of the classical n-well diode at 300 Mbit/s (Fig. 6.5(a)). These eye diagram measurements demonstrate that a diﬀerential photodiode topology is th´e solution for high-speed monolithic optical receivers. The BER versus average input optical power when a 27 -1 prbs data is applied is plotted in Fig. 6.8 for the diﬀerential n-well diode and the classical n-well diode. At 300 Mbit/s and when Popt =−8 dBm, the BER of the diﬀerential structure is better than 10−13 , while the BER of the n-well structure is only 2 · 10−10 . If smaller input signals are applied, the BER of the diﬀerential structure reduces due to the limited responsivity and the reduced data eye

6.2 Test Photodiodes with TIA in 0.18 µm CMOS

(a)

141

(b)

Fig. 6.7. High-speed eye diagrams of the 0.18 µm diﬀerential n-well diode with amplifying circuit. Popt =−7 dBm and the bitrate equals: (a) 500 Mbit/s, (b) 622 Mbit/s.

−3

10

−6

bit error rate

10

−9

10

−12

10

−15

classical n−well diode, 300Mbit/s differential n−well diode, 300Mbit/s differential n−well diode, 500Mbit/s

10

−18

10

−12

−11 −10 −9 −8 −7 Average input power [dBm]

Fig. 6.8. Bit error rate versus average input power of the 0.18 µm classical and diﬀerential n-well photodiode with amplifying circuit.

width. At 500 Mbit/s, the diﬀerential n-well diode achieves a BER of 3 · 10−10 when an input optical signal of −8 dBm is applied. The frequency response of the diﬀerential n-well diode followed by TIA, CSDA and output buﬀer, is depicted in Fig. 6.9. A Rohde&Schwarz network analyzer is used to modulate the laser driver and to evaluate the electrical output signal of the receiver. Measurements are done for the maximum and minimum value of the feedback resistance. When the transimpedance gain is high, the 3-dB bandwidth is 177 MHz. When the transimpedance gain is low, the 3-dB bandwidth is 245 MHz. So bandwidth is inversely proportional to

142

6 CMOS Realizations

Output power [dBm]

−10 −20 −30 −40 −50 Z −60 −70

=65 dBΩ

TIA

ZTIA=54 dBΩ 8

9

10

10 frequency [Hz]

Fig. 6.9. Frequency response of the 0.18 µm diﬀerential n-well photodiode followed by TIA, CSDA and output buﬀer.

Table 6.2. Performance summary of the classical and diﬀerential n-well photodiode with amplifying circuit in 0.18 µm CMOS. Classical Diﬀerential n-well diode n-well diode Technology 0.18 µm CMOS 1.8 V Vdd Optical wavelength 850 nm Die area 1000x685 µm2 1000x565 µm2 Bitrate 300 Mbit/s 500 Mbit/s 2 · 10−10 3 · 10−10 [email protected] =−8 dBm rms [email protected] =−7 dBm 310 ps 80 ps Power dissipation 17 mW

transimpedance gain, as described by (4.11). The 3-dB bandwidth is however smaller than the values predicted by the TIA-simulations in Section 4.5.1. This is due to the lower intrinsic bandwidth of the diﬀerential diode, and proves that the diode is the speed limiting component. The measurement results of both the classical and the diﬀerential n-well diode are summarized in Table 6.2.

6.3 Test Photodiodes with TIA in 90 nm CMOS The objective of this chip is very similar to the objective of the chip discussed in the previous section (Section 6.2): the comparison of the performance of

6.3 Test Photodiodes with TIA in 90 nm CMOS

(a)

(b)

143

(c)

Fig. 6.10. Layout of: (a) the classical n-well diode, (b) the quasi-fractal n-well diode, (c) p+ n-well diode with guard, all implemented in a 90 nm CMOS technology.

diﬀerent diode layout structures. The main diﬀerence is that for this chip a 90 nm CMOS technology has been used. First the design of the photodiodes and the receiver circuit are discussed, followed by an overview of the measurements. The results of this chip are published in [Her04b, Her04a]. 6.3.1 Circuit Description Photodiodes Due to space limitations in this more expensive technology, only three test diodes have been implemented: a classical n-well diode, a quasi-fractal n-well diode and a p+ n-well diode with guard. No accurate models are available for the side-wall n-well junction capacitance, so an estimation of the total junction capacitance has to be made. The values are estimated to be 1.6 pF (classical n-well diode) and 1.4 pF (quasi-fractal n-well diode). For the p+ n-well diode with guard, there exists a model for the side-wall junction and the total calculated capacitance of the p+ n-well junction equals 6 pF. All diodes have an area of 100x100 µm2 . The layout of these diodes is very much the same as the layout of their counterparts in the 0.18 µm technology (Section 6.2.1) and is depicted in Fig. 6.10. TIA and Output Buﬀer The design of the TIA has been discussed in Section 4.5.2. The schematic of the complete receiver circuit, consisting of TIA and output buﬀers, is depicted in Fig. 6.11. The output buﬀers are two scaled inverters with an nMOS load to control the DC threshold voltage. The simulated current consumption of the complete buﬀer equals 4 mA.

144

6 CMOS Realizations Vb1

Vdd

MRfb Rfb

Mb2

M2

Mb5 to 50 Ohm

M1

Vb2

Mb1

M3

Mb3

Mb4

Mb6

C ac Photodiode and TIA

Output Buffer

Fig. 6.11. Schematic of the 90 nm receiver circuit, needed to amplify the currents generated by the test photodiodes.

6.3.2 Measurements Fig. 6.12 shows a photograph of the 90 nm CMOS test chip. The upper part contains two stand-alone test diodes: the classical n-well diode and the quasifractal n-well diode. Both diodes are also implemented with the amplifying circuit (TIA and output buﬀer). In the lower part, the same structures are repeated for the p+ n-well diode with guard. The area of the upper part equals 1000x800 µm2 , the area of the lower part equals 450x1000 µm2 . No additional masks or anti-reﬂective coatings are used to enhance the performance of the photodiodes. As already mentioned in Section 4.5.2, no MiM-capacitors were available. To achieve a high capacitance density both for the on-chip decoupling and for Cac (Fig. 6.11), the metal wall structure is used [Yao04]. It creates a large capacitance value on a small area by using the side-wall capacitance of 8 metals from the 9 metal layer stack. With a supply voltage of 1.1 V, the amplifying circuit consumes 9 mW. The measurement set-up is the same as for the 0.18 µm test diodes. The only diﬀerence is that to determine the BER, the Agilent’s Inﬁnium oscilloscope has been used, that calculates the BER out of Q-factor measurements. The stand-alone testdiodes have been used to measure the DC responsivity. The n-well diode has a responsivity of 0.3 A/W, while the p+ n-well diode with guard has a responsivity of only 0.006 A/W. Fig. 6.13 shows the eye diagrams when a 232 -1 prbs at a bitrate of 100 Mbit/s and with an average input optical power (Popt ) of −7 dBm is applied. The eye diagram of the front-end with the n-well diode (Fig. 6.13(a)) clearly shows the slowly rising tail originating from the diﬀusing carriers in the substrate. There is not much diﬀerence between the eye diagram of the quasi-fractal n-well diode (Fig. 6.13(b)) and the classical n-well diode. The improvement is much less when compared with the 0.18 µm test structures. This is probably due to the higher doping concentration of the p-well. As a

6.3 Test Photodiodes with TIA in 90 nm CMOS

145

Fig. 6.12. Chip photograph of the three testdiodes with amplifying circuit in 90 nm standard CMOS.

result, the width of the depletion region is smaller, and the contribution of the drift current to the total current decreases. This explains why there is not much improvement in speed by optimizing the sidewall capacitance using a quasi-fractal structure. At the other hand, the eye diagram of the front-end with the p+ n-well diode with guard (Fig. 6.13(c)) is much better: the eyeopening is wider and the rising/falling edges are steeper. This demonstrates that the diﬀusing carriers are eﬀectively removed by the substrate contacts. In Fig. 6.14(a) and Fig. 6.14(b), two high-speed eye diagrams at 400 Mbit/s and 500 Mbit/s respectively of the p+ n-well diode with guard and amplifying circuit are shown. To perform sensitivity measurements, the output signals are ampliﬁed with a Mini-Circuits broadband low-noise ampliﬁer (LNA). Its low-frequency cutoﬀ equals 1 kHz and its upper 3-dB bandwidth equals 1 GHz. The LNA is further characterized by a gain of 20 dB and a noise ﬁgure of 3 dB. Sensitivity of the two front-ends is determined by applying a 232 -1 prbs and by measuring the Q-factor of the output data after the LNA. The optical attenuation between the optical source and the device under test has been adjusted to obtain a Q-factor of 6. This value corresponds to a BER of 10−9 . At 100 Mbit/s, the front-end with n-well diode has a sensitivity of −9 dBm, while the front-end

146

6 CMOS Realizations

(a)

(b)

(c) Fig. 6.13. Eye diagrams of the 90 nm test diodes with amplifying circuit. The input signal has a bitrate of 100 Mbit/s and Popt =−7 dBm. The diﬀerent diodes are: (a) classical n-well diode, (b) quasi-fractal n-well diode, (c) p+ n-well diode with guard.

with the quasi-fractal n-well diode has a sensitivity of −8.3 dBm. The frontend with p+ n-well diode with guard even achieves a sensitivity of −10.4 dBm at 400 Mbit/s, and a sensitivity of −8 dBm at 500 Mbit/s. All measurements are summarized in Table 6.3.

6.4 A 3.5 Gbit/s LA in 0.18 µm CMOS After two chips with photodiodes and TIAs, a CMOS implementation of the next receiver building block is presented: the limiting ampliﬁer. Again, an overview of the circuit topology is given before the measurements are discussed. The results are also published in [Her05, Her06a].

6.4 A 3.5 Gbit/s LA in 0.18 µm CMOS

(a)

147

(b)

Fig. 6.14. High-speed eye diagrams of the p+ n-well diode with guard and amplifying circuit. Popt =−7 dBm and the bitrate equals: (a) 400 Mbit/s, (b) 500 Mbit/s. Table 6.3. Performance summary of the test photodiodes with amplifying circuit in 90 nm CMOS. TIA with TIA with quasi- TIA with p+ n-well n-well diode fractal n-well diode diode with guard Technology Vdd Optical wavelength Die area 450x800 µm2 Diode responsivity 0.3 A/W Bitrate 100 Mbit/s Sensitivity @BER=10−9 Power dissipation

−9 dBm

90 nm standard CMOS 1.1 V 850 nm 450x800 µm2 450x1000 µm2 0.006 A/W 100 Mbit/s 400 Mbit/s 500 Mbit/s −8.3 dBm −10.4 dBm −8 dBm 9 mW

6.4.1 Circuit Description Four-Stage Limiting Ampliﬁer The design of this LA has been discussed previously in Section 5.5.1. The LA consists of four cascaded Cherry-Hooper stages, as depicted in Fig. 5.5. Output Buﬀer The output buﬀer, necessary to drive the 50 Ω of the measurement equipment, consists of two stages. To achieve a broad bandwidth, each stage comprises

148

6 CMOS Realizations Vdd 2* gm* v/4 * Rl

Rl

2* gm* v/4 * Rl

Vout1 Vin1 v/2

M1

M2 gm* v/4 nA

M c1

Rl I1

Vout2

M3 0

M4 gm* v/4

Vb

Vin2 v/2

nB

M c2

M c3

Fig. 6.15. Schematic of the fT -doubler.

an fT -doubler [Raz02], shown in Fig. 6.15. Transistors M1 to M4 all have the same sizing (W = 40 µm in the ﬁrst stage and W = 80 µm in the second stage) and operating point (Ids = 2 mA in the ﬁrst stage and Ids = 7 mA in the second stage, all lengths are chosen minimal). Resistor Rl is the load of transistors M1 and M3 at one side, and transistors M2 and M4 at the other side. Compared to a traditional diﬀerential pair with resistive load, this circuit reduces the input capacitance while maintaining the same gain. Consider a diﬀerential voltage v applied at the input transistors M1 and M4 . The small signal behavior of the circuit is also shown in Fig. 6.15. The input Vin1 goes up with an amplitude of v/2, while the input Vin2 goes down with the same amplitude. Vb is zero, as it is a bias voltage equal to the commonmode level of Vin1 and Vin2 . As a consequence, a current equal to gm v/4 ﬂows from drain to source in transistors M1 and M3 , and from source to drain in transistors M2 and M4 . These currents add up at the output nodes which results in a negative small-signal voltage 2 · gm v/4Rl at Vout1 and a positive small-signal voltage 2 · gm v/4Rl at Vout2 . So the diﬀerential gain equals gm Rl , which is the same as that of a diﬀerential pair with input transistor transconductance gm and load resistor Rl . By using the conﬁguration of Fig. 6.15, the input ports of the transistors are placed in series while the output ports are connected in parallel. This results in a lower input capacitance. If the parasitic capacitance at the two common-mode nodes nA and nB is negligible, the input capacitance is roughly equal to Cgs /2, where Cgs is the gate-source capacitance of transistors M1 to M4 Hence the name fT -doubler: the circuit halves the input capacitance while maintaining the same overall transconductance. The circuit also suﬀers from several drawbacks compared to a simple differential pair. First, the power dissipation is doubled. Next, the total current ﬂowing through the load resistors is doubled, making it more diﬃcult to keep the transistors in saturation. Further, the total output capacitance is doubled.

6.4 A 3.5 Gbit/s LA in 0.18 µm CMOS

149

Fig. 6.16. Chip photograph of the 3.5 Gbit/s LA in 0.18 µm standard CMOS.

Finally, if the parasitic capacitance at nodes nA and nB is not negligible, the input capacitance is higher than Cgs /2. 6.4.2 Measurements A die photograph of the limiting ampliﬁer with output buﬀer is depicted in Fig. 6.16. A standard 0.18 µm 1.8 V CMOS technology is used for the implementation. Total chip area including bond pads and decoupling capacitors is 1.3x1.5 mm2 . Special attention has been paid to make the layout symmetrical, both for the diﬀerential stages in the LA and for the diﬀerential stages in the buﬀer. The power dissipation equals 70 mA, from which only 19 mA is consumed by the LA. Bit error rate (BER), eye diagram and jitter measurements are obtained from the Agilent ParBERT (Parallel Bit Error Ratio Tester). A diﬀerential 231 -1 prbs is applied at the input. Fig. 6.17 and Fig. 6.18 show eye diagrams at 1 Gbit/s and at 3.5 Gbit/s respectively, and for diﬀerent input amplitudes. The eye opening measurement obtained from the ParBERT generates a threedimensional bit error rate diagram as a function of the sample delay (x-axis) and the sample threshold (y-axis). The contour of the eye is derived from the bit error rates that have been measured. Diﬀerent grey-levels are used for the regions between the lines of equal bit error rate: black corresponds to a BER lower than 10−12 . The eye opening is the best for large input signals and low bit-rates. But even for an input signal with a bitrate of 3.5 Gbit/s and an input voltage of 10 mVpp , the eye is still considerably open.

150

6 CMOS Realizations

(a)

(b) Fig. 6.17. Eye diagrams at 1 Gbit/s of the four-stage LA with output buﬀer: (a) Vin = 100 mVpp , (b) Vin = 10 mVpp .

(a)

(b) Fig. 6.18. Eye diagrams at 3.5 Gbit/s of the four-stage LA with output buﬀer: (a) Vin = 100 mVpp , (b) Vin = 10 mVpp .

6.4 A 3.5 Gbit/s LA in 0.18 µm CMOS

151

−11

bit error rate

10

−12

10

−13

10

−14

10

1

2 3 bitrate [Gbit/s]

4

Fig. 6.19. Bit error rate versus bitrate of the four-stage LA with output buﬀer. The input prbs signal has an amplitude of 10 mVpp . Table 6.4. Performance summary of the 3.5 Gbit/s 0.18 µm LA. Technology 0.18 µm CMOS 1.8 V Vdd Diﬀerential gain 27 dB Bitrate 3.5 Gbit/s 5 · 10−12 [email protected] mVpp rms jitter 12 ps Power dissipation 70 mA (LA: 19 mA)

The results of the bit error rate tests are shown in Fig. 6.19. A diﬀerential 231 -1 prbs input signal with an amplitude of 10 mVpp is applied, while for each test the bitrate of the input is changed. As expected, the higher the bitrate, the higher the bit error rate. At 1 Gbit/s the BER is as low as 7 · 10−14 , while at 3.5 Gbit/s the BER is still only 5 · 10−12 . The rms jitter is slightly dependent on level and speed of the input signal. For an input level of 10 mVpp and a bitrate of 3.5 Gbit/s, the measured rms jitter is 16 ps. Taking the rms jitter added by the ParBERT into account, the post-ampliﬁer and buﬀer establish an rms jitter of only 12 ps. Finally, the small-signal voltage gain is measured with a network analyzer. This results in a measured singleended voltage gain of 21 dB, which corresponds to a diﬀerential voltage gain of 27 dB. The measurement results are summarized in Table 6.4. In Table 6.8 at the end of this chapter, the performance of this LA [Her05] is compared with the papers discussed in Section 5.3. First it is noticed that the BiCMOS implementations achieve gain-bandwidth products larger than one 1 THz with 20-year-old technologies. Comparing [Her05] with the 0.18 µm

152

6 CMOS Realizations Rf

Vbias R block

A

CH with NIC

C block

50 Ohm Equalizer

PA

buffer

Vout

C block R block

Rf

50 Ohm

Vbias

Fig. 6.20. Block diagram of the described integrated receiver front-end.

CMOS implementations, only [Gal03] and [Gal04] achieve higher bitrates. The gain-bandwidth product of this chip is not that high, but the power dissipation is low. To conclude, the described ampliﬁer is comparable with today’s stateof-the-art, oﬀering wide-open eye diagrams at high bit-rates, low bit error rates and very low power consumption.

6.5 A Gbit/s Monolithic Optical Receiver Front-End in 0.18 µm CMOS The last implementation is a fully integrated optical receiver front-end in 0.18 µm CMOS. The ultimate goal of this ﬁnal chip is to receive light signals at Gbit/s bitrate and to convert them into voltage signals with a high output swing. Two measures have been taken to improve the speed performance of a classical n-well CMOS photodiode: a diﬀerential diode topology and an analog equalizer to compensate for its high-frequency roll-oﬀ. The signals are brought oﬀ-chip with a 50 Ω output buﬀer. In a complete one-chip optical receiver as depicted in Fig. 2.1, this output buﬀer would not be needed, and the output signals of the post-ampliﬁer are used to steer the clock and data recovery circuit (CDR). Fig. 6.20 shows the block diagram of the described receiver front-end. First the implementation of every building block is discussed in detail. Afterwards the measurement results are presented. The most important results are published in [Her06c, Her06b]. 6.5.1 Circuit Description Diﬀerential Photodiode The ﬁrst functional block in the architecture of Fig. 6.20 is the photodiode (PD). As the measurement results of the diﬀerent photodiodes in Section 6.2

6.5 A Gbit/s Monolithic Optical Receiver Front-End in 0.18 µm CMOS

153

Fig. 6.21. Photo of the 0.18 µm CMOS diﬀerential photodiode.

demonstrate the superiority of the diﬀerential photodiode concerning elimination of substrate carriers, also a diﬀerential PD is chosen for the presented receiver. Fig 6.21 depicts a photo of the implemented CMOS PD. As the core and cladding of the ﬁber are circular, an octagonal form is taken with a diagonal of 80 µm. The PD consists of 18 ﬁngers, of which 9 are covered with metal. To minimize optical non-idealities, this covering metal should be located as close to the silicon surface as possible. As metal 1 is used for routing, metal 2 is used for this purpose. Between the junction ﬁngers, substrate contacts are foreseen to minimize substrate resistance. For the same reason, every ﬁnger is cut in two in the middle to place extra substrate contacts. The diode is also surrounded by a broad guard ring of substrate contracts. The junction capacitance of the illuminated PD as well as the dark PD, with a reverse voltage of 1.3 V, equals 159 fF. Diﬀerential Transimpedance Ampliﬁer Before subtraction of the PD signals, the currents from the illuminated PD and dark PD are ﬁrst converted into a voltage by a diﬀerential TIA. The design of this circuit has been elaborated in detail in Section 4.5.3. The schematic of this diﬀerential TIA is depicted in Fig. 4.12. A high-pass ﬁlter, consisting of Cblock and Rblock , is needed to set the DC-level at the input of the subsequent diﬀerential stages. The major reason is that the signals from the illuminated and dark junctions have a diﬀerent peak-to-peak value, and thus generate diﬀerent DC-levels at the output of the TIA. This is not optimal for correct diﬀerential operation. Therefore, the bias voltage Vbias is applied externally and data-independent. The values of Cblock and Rblock must be chosen carefully, as too small values create a relatively high 3-dB frequency. As a result, lower frequency components in the prbs data stream are considered as DC-voltage variations and ﬁltered out. This

154

6 CMOS Realizations

baseline wander must be avoided. In the current design, Cblock =2 pF and Rblock =20 kΩ, which gives a 3-dB frequency of 4 MHz. Subtraction Block Now the currents of the PDs have been converted into voltages, their diﬀerence can be made by a diﬀerential voltage ampliﬁer. The signal originating from the diﬀusing substrate carriers will appear as a common-mode signal at the input of this ampliﬁer and will be suppressed. This function is implemented by a modiﬁed Cherry-Hooper topology with negative impedance converter to enhance bandwidth. The design of this stage has been explained in Section 5.5.2, where is was used as one of the amplifying stages in the limiting ampliﬁer. The speciﬁcations of this block are however slightly diﬀerent. In the subtraction block, it can be important to make a diﬀerential signal introducing as little non-idealities as possible, so bandwidth is maximized. Also the common-mode suppression should be high for a wide frequency band. Simulations show a bandwidth of 5 GHz when this stage is loaded with the almost 200 fF input capacitance of the equalizer. The small-signal diﬀerential gain equals 6 dB. Equalizer The function of the equalizer is to compensate for the frequency roll-of of the diﬀerential diode. Therefore, equalization is performed after subtraction of the signals. The advantage of equalizing a diﬀerential PD compared to a classical n-well diode [Rad04, Rad05] is the intrinsic potential of a better speed performance. The price to pay is a lower sensitivity. The design of this block has been the subject of a master’s thesis [Tav05, Tav06]. The circuit diagram of the equalizer is presented in Fig. 6.22(a) and the design parameters are summarized in Table 6.5. It is a pseudo-diﬀerential stage, with second-order capacitive source degeneration to create zeros at the desired frequencies. Its transfer function is given by: Geq = −

gm,M1 Rx R1 Z2 Z3 1 + gm,M1 R1 Z2 +R 1 Z3 +Z2 Z3

.

(6.1)

Using the expressions for Z2 and Z3 : 1 , sC2 1 Z3 = R3 + , sC3 Z2 = R2 +

(6.2) (6.3)

and assuming that gm,M1 R1 is suﬃciently large, the transfer function reduces to:

6.5 A Gbit/s Monolithic Optical Receiver Front-End in 0.18 µm CMOS

155

Vdd Rx Vin1

Vout2

Vout1

nxa

Rx nxb

M 1b

M 1a

Vin2

n1b

n1a

R3

R2

C3

C2

R1

R1

R2 C2

R3 C3

(a) 10

gain [dB]

5

0

−5

−10 6 10

Equalizer PD Compensated PD 7

10

8

10 frequency [Hz]

9

10

(b) Fig. 6.22. The analog equalizer: (a) schematic, (b) uncompensated and compensated characteristics of the diﬀerential photodiode (PD).

Geq = −

Rx s2 R2 C2 C3 + s((R1 + R2 )C2 + (R1 + R3 )C3 ) + 1 , R1 s2 R2 R3 C2 C3 + s(R2 C2 + R3 C3 ) + 1

with:

R2 = R1 R2 + R2 R3 + R1 R3 .

(6.4)

(6.5)

To gain intuitive insight, it is assumed that the diﬀerent poles are well separated (which is not necessarily true in a practical implementation), and (6.4) than further becomes: Geq = −

Rx (1 + s(R1 + R2 )C2 )(1 + s(R1 + R3 )C3 ) . R1 (1 + sR2 C2 )(1 + sR3 C3 )

(6.6)

The gain is determined by the ratio Rx /R1 . Adding a branch with resistor R and capacitor C creates a zero at frequency 1/2π(R1 + R)C and a pole at frequency 1/2πRC.

156

6 CMOS Realizations Table 6.5. Design parameters of the analog equalizer. M1 type L W VDSAT IDS gm gds Cgs Cgd

nMOS 0.18 µm 107 µm 0.21 V 6.1 mA 38 mS 1.7 mS 128 fF 39 fF

Rx R1 R2 R3 C1 C1

87 Ω 48 Ω 89 Ω 0Ω 3.7 pF 2 pF

Fig. 6.22(b) illustrates the working principle of the equalizer. As derived in Section 3.5.3, the transfer characteristic of a diﬀerential PD with 18 ﬁngers has a 3-dB frequency of 1 GHz and a roll-oﬀ increasing from 3 dB/decade up to 10 dB/decade above 1 GHz. The Eldo-simulations of the equalizer show a corresponding roll-up. The result is a compensated diode characteristic that is almost ﬂat up to 5 GHz. Five-Stage Limiting Ampliﬁer The block diagram of the LA is depicted in Fig. 5.9. Its design has been studied thoroughly in Section 5.5.2. Output Buﬀer The output buﬀer is needed to drive the oﬀ-chip 50 Ω load. It consists of four scaled stages: three fT -doublers (discussed in Section 6.4.1 and depicted in Fig. 6.15) and one diﬀerential pair with resistive load. For the last stage, a simple diﬀerential pair is preferred over the fT -doubler, as the latter one increases the output capacitance, and the output load is already assumed to be 1 pF. Each stage has a larger input transistor (from 24 µm up to 232 µm), consequently a higher input capacitance, also a higher current consumption and a lower load resistance (from 250 Ω down to 40 Ω parallel with 50 Ω). Note also that for this output buﬀer the small-signal 3-dB bandwidth is not

6.5 A Gbit/s Monolithic Optical Receiver Front-End in 0.18 µm CMOS

157

Fig. 6.23. Chip photograph of the Gbit/s monolithic optical receiver in 0.18 µm standard CMOS.

a good measure for its speed performance, as signals with a high amplitude are generated by the LA. Usually, the small-signal bandwidth is a lower limit, but transient signals simulations have to be performed too. Large and high-speed output signals result in a high power consumption: this block consumes 170 mA from the 1.8 V power supply. The on-chip voltage swing of 1.2 Vpp at the output of the LA is converted into a simulated 50 Ω oﬀ-chip swing of 500 mVpp , at bitrates up to 6 Gbit/s. 6.5.2 Measurements A chip photograph of the receiver with photodiode, integrated in a 0.18 µm 1.8 V CMOS technology, is depicted in Fig. 6.23. Die area, including bond pads and on-chip decoupling, is 1.5x3 mm2 . No additional masks or anti-reﬂective coatings have been used to enhance the optical performance of the diode. The measured photodiode DC responsivity for the diﬀerential signal is 0.03 A/W. The current consumption of the complete front-end is 250 mA. Both the TIA and LA consume 40 mA each, 170 mA is dissipated in the output buﬀer to generate high-speed 500 mVpp signals oﬀ-chip. The measurement results are summarized in Table 6.6. In the following, ﬁrst the measurements for the LA with output buﬀer are shown. Next the performance of the complete front-end is discussed. Limiting Ampliﬁer with Output Buﬀer Bit error rate (BER), eye diagram and jitter measurements are obtained from the Agilent ParBERT (Parallel Bit Error Ratio Tester). Applying a 27 -1

158

6 CMOS Realizations

prbs, error free operation from 800 Mbit/s up to 6 Gbit/s has been measured. The rms jitter equals 8 ps. The BER measurements versus input voltage at 4 Gbit/s, 5 Gbit/s and 6 Gbit/s are summarized in Fig. 6.24(a). At 6 Gbit/s, an input voltage of 8 mVpp is needed to achieve a BER of 10−12 . The corresponding eye diagram is depicted in Fig. 6.25(a). The smaller the input amplitude, the higher the bit error rate: a 6 mVpp input voltage at 6 Gbit/s results in a BER of 10−9 . At 5 Gbit/s and 4 Gbit/s , the sensitivity for a BER of 10−12 is 5 mVpp respectively 3 mVpp . Due to clipping of the ﬁrst Cherry-Hooper stage, the limiting ampliﬁer is also capable of handling very large signals. The input swing is only limited by the maximum tolerable voltage at the input, that has to be smaller than the supply voltage for reliability reasons. When the input voltage is 600 mVpp , the BER is better than 10−13 , independent of the bitrate. For a bitrate of 6 Gbit/s, the eye diagram is shown in Fig. 6.25(b). This results in a dynamic range with BER< 10−12 of 37.5 dB at 6 Gbit/s , 41.5 dB at 5 Gbit/s and 46 dB at 4 Gbit/s. Table 6.8 compares the performance of this LA [Her06c] with present stateof-the art. The ampliﬁer achieves a higher gain-bandwidth product than most other 0.18 µm CMOS LAs. Only [Gal03], which uses integrated passive inductors to increase the bandwidth, has an extremely high gain-bandwidth product. Furthermore, the power dissipation of the latter is higher than in [Her06c]. The high gain-bandwidth product of this LA results in maximal achievable bitrates with a low BER as high as 6 Gbit/s, combined with a high gain, a high input dynamic range and a high output swing. Optical Receiver The optical measurements of the complete receiver are performed with a commercially available 850 nm Agilent transmitter, electrically driven with a 27 -1 prbs generated by the ParBERT. The average output power of the transmitter is −6 dBm, and for sensitivity measurements this signal is attenuated by an EXFO attenuator. The BER measurements for bitrates ranging from 1 Gbit/s to 1.9 Gbit/s are summarized in Fig. 6.24(b). The BER becomes worse for higher bitrates and lower input powers. At 1.7 Gbit/s, −6 dBm is needed to achieve a BER smaller than 10−12 . The eye diagram of this output signal is shown in Fig. 6.26(b). For comparison, a 1 Gbit/s eye diagram is shown in Fig. 6.26(a) that achieves a BER< 10−14 . The jitter, characterized by an rms value of 35 ps, is clearly visible in these eyes and is the bottleneck for achieving higher bitrates. Much eﬀort has been put in ﬁnding out where the jitter originates from. After all, purely electrical measurements demonstrate that the circuit, from TIA to output buﬀer, performs according to expectations. Fig. 6.27 shows eye diagrams when the TIA is driven by an electrical 27 -1 prbs signal from the ParBERT with an amplitude of 4 mVpp , corresponding to an equivalent input current of 8 µApp . Taking a responsivity of 0.03 A/W into account, this would correspond to an average input optical power of 133 µW, or −8.75 dBm. The

6.5 A Gbit/s Monolithic Optical Receiver Front-End in 0.18 µm CMOS

6 Gbit/s 5 Gbit/s 4 Gbit/s

−9

10 bit error rate

159

−10

10

−11

10

−12

10

−13

10

2

4 6 8 peak−to−peak input voltage (mVpp)

(a) −6

10

−8

bit error rate

10

−10

10

−12

10

−14

10

1.9 Gbit/s 1.8 Gbit/s 1.7 Gbit/s 1.5 Gbit/s 1 Gbit/s

−12 −11 −10 −9 −8 −7 −6 average input power (dBm)

−5

(b) Fig. 6.24. Bit error rate measurements: (a) BER of the ﬁve-stage LA with output buﬀer versus input voltage for diﬀerent bitrates, (b) BER of the Gbit/s optical receiver versus average input optical power for diﬀerent bitrates.

comparison of Fig. 6.26(a) and Fig. 6.27(a) shows that the jitter is much less when a pure electrical input signal is applied. The 5 Gbit/s eye depicted in Fig. 6.27(b) shows that the data quality now degrades due to bandwidth limitations (as expected at this speed) and not due to jitter limitations. BER tests of the 5 Gbit/s eye result in a BER smaller than 10−14 . The important diﬀerence with the optical measurements is that the eyes in Fig. 6.27 are measured with a purely diﬀerential signal at the input. The nature of the signals generated by the diﬀerential photodiode is totally diﬀerent: the signals from the illuminated and dark photodiode have the same polarity, but diﬀerent amplitudes, and thus a common-mode component. Following experiments have been performed with electrical signals of the same polarity at the input:

160

6 CMOS Realizations

(a)

(b) Fig. 6.25. Eye diagrams at 6 Gbit/s of the ﬁve-stage LA with output buﬀer: (a) Vin = 8 mVpp , (b) Vin = 600 mVpp .

• Two 4 Gbit/s prbs signals with the same polarity, but an amplitude difference of 16 dB, are applied at the input. A serious degradation of the jitter, compared to the eyes in Fig. 6.27 can be observed. Lowering the amplitude diﬀerence to 6 dB deteriorates the amount of jitter even more. • Decreasing the bitrate of the prbs data from 4 Gbit/s to 1 Gbit/s decreases the amount of observed jitter. • Instead of prbs signals, a simple pattern of one-zero-one-zero-etc. is applied at the input. The bitrate is changed from 1 Gbit/s to 4 Gbit/s. The observed jitter is low, much lower as when prbs signals are applied. Also, the amount of jitter does not increase with the bitrate. What does change is the location of the cross-over points on the time axis. The explanation for these observations is that the common-mode suppression of the receiver, and more precisely of the diﬀerential TIA, is not high enough. Ideally, the common-mode rejection ratio for a diﬀerential circuit is inﬁnity. However, due to non-idealities, such as mismatch between the VT of the input transistors (which are nMOS transistors and thus also suﬀer from bulk-eﬀect and mismatch on the bulk-eﬀect parameter), the common-mode rejection becomes worse, especially at higher frequencies. A non-inﬁnite common-mode

6.5 A Gbit/s Monolithic Optical Receiver Front-End in 0.18 µm CMOS

161

(a)

(b) Fig. 6.26. Optical eye diagrams of the complete front-end. The input signal has an average optical power of Popt = −6 dBm and the bitrate equals: (a) 1 Gbit/s, (b) 1.7 Gbit/s.

suppression means that a pure common-mode signal at the input (two signals with the same polarity and the same amplitude, so the diﬀerential input signal equals zero), will result in a non-zero diﬀerential signal at the output. This problem can also be considered as an oﬀset problem. The way that oﬀset problems result in jitter generation is depicted in Fig. 6.28: a diﬀerent oﬀset voltage (suggested by the black and grey transfer curves) will result in diﬀerent cross-over points on the time axis. If the oﬀset voltage remains constant, there is no problem. However, due to the nature of the prbs signals, diﬀerent frequency components are present. As the common-mode suppression varies for diﬀerent frequencies, the oﬀset voltage also changes with time. This results in a large amount of jitter on the time axis. While Table 6.6 summarizes the most important measurements of the fully integrated optical receiver, Table 6.7 compares its performance with other CMOS integrated opto-electrical front-ends. Note that the receiver described in this work [Her06c] features the highest level of integration, incorporating a photodiode, transimpedance ampliﬁer and limiting amliﬁer. [Sch02] and [Che05] do not implement an integrated photodiode, but

162

6 CMOS Realizations

(a)

(b) Fig. 6.27. Electrical eye diagrams of the complete front-end. The input signal has an equivalent current amplitude of Ieq = 8 µApp and the bitrate equals: (a) 1 Gbit/s, (b) 5 Gbit/s.

perform measurements with commercial photodiodes with a responsivity of 0.75 A/W-0.85 A/W. The diﬀerential PD of [Her06c] has a responsivity of only 0.03 A/W, hence the lower receiver sensitivity. The work presented in [Roo00] and [Roo01] uses SML-detectors, essentially the same topology as the diﬀerential diode. Their responsivity is larger because older technologies with wider space charge regions are used. [Rad05] includes an integrated photodiode and outperforms [Her06c] both in speed and in responsivity. The latter results from the use of a classical n-well diode with a higher intrinsic responsivity than the diﬀerential photodiode. To increase the n-well diode speed performance, equalizing techniques have been used. Furthermore, jitter problems are much less an issue in this approach due to the nature of the signals stemming from the single n-well diode. Combining a diﬀerential photodiode with equalizing techniques as presented in [Her06c] should result in a better speed performance. It is strongly believed that, by improving the common-mode suppression of the TIA and thus the jitter performance, achieving bitrates of 5 Gbit/s is feasible using an equalized diﬀerential photodiode in a 0.18 µm CMOS technology.

6.5 A Gbit/s Monolithic Optical Receiver Front-End in 0.18 µm CMOS diff. output

diff. output

jitter!

t

diff. input

diff. input

t

Fig. 6.28. Generation of jitter due to oﬀset problems. Table 6.6. Performance summary of the Gbit/s 0.18 µm optical receiver. Technology Vdd Optical wavelength photodiode DC responsivity

0.18 µm CMOS 1.8 V 850 nm 0.03 A/W

Optical receiver Bitrate [email protected] =−6 dBm rms jitter Power dissipation

1.7 Gbit/s 10−12 35 ps 250 mA

Limiting ampliﬁer with output buﬀer Bitrate 6 Gbit/s 10−12 [email protected] mVpp rms jitter 8 ps Dynamic range 37.5 dB Power dissipation 210 mA (LA: 40 mA)

163

164

6 CMOS Realizations

Table 6.7. Comparison of the described optical receiver front-end with other CMOS opto-electrical receivers. Ref.

Integration level PD TIA PA

Technology

Bitrate

Sensitivity

[Roo00] [Roo01] [Sch02] [Che05] [Rad05]

0.6 µm 0.25 µm 0.35 µm 0.18 µm 0.18 µm

250 Mbit/s 700 Mbit/s 1.25 Gbit/s 10 Gbit/s 3 Gbit/s

−18 dBm −18 dBm −22.5 dBm −12 dBm −19 dBm

x x x

x x x x x

x x -

[Her06b]

0.18 µm

1.7 Gbit/s

−6 dBm

x

x

x

6.6 Conclusions This chapter has covered the implementation of four standard CMOS chips that each contain one or more building blocks of the optical receiver. This way, the theory developed in the previous chapters has been put into practice. Much attention has been paid to the measurement set-up and the interpretation of the measurement results. A systematic approach has been chosen, where the ﬁrst two chip implement test diodes with TIAs, the third chip contains a LA, and the ﬁnal chip presents a fully integrated optical receiver. The objective of the ﬁrst two chips is a demonstration of light detection by standard CMOS photodiodes. No additional layers or coatings have been used to enhance the diode speed or responsivity. Furthermore, the performance of diﬀerent diode types can be compared, as the circuit has been designed not to be the speed limiting factor. Five test diodes with amplifying circuits have been designed in 0.18 µm CMOS, from which the diﬀerential n-well diode has proven to have the best performance. Bitrates up to 500 Mbit/s have been demonstrated with a BER in the order of 10−10 , where the receiver with classical n-well diode can achieve a bitrate of 300 Mbit/s for the same BER. A speed factor improvement of almost two has thus been established by applying a clever layout topology for the photodiode. Due to space limitations, only three test diodes with ampliﬁers have been implemented in the more expensive 90 nm technology. The diﬀerential diode was left out, and the p+ n-well diode with guard turned out to have the best performance. Bitrates of 500 Mbit/s are achieved with a BER of 10−9 . Finally, when the two designs in diﬀerent CMOS generations are compared, one can conclude that achieving higher bitrates at the receiver front-end becomes more diﬃcult in newer CMOS generations with smaller linewidths. There are two main reasons. First, the intrinsic speed as discussed in Chapter 3 becomes lower due to the smaller space charge regions. Second, achieving a high extrinsic speed in combination with the TIA as discussed in Chapter 4 will become more diﬃcult due to the

Table 6.8. Comparison of the described LAs with other LAs implemented in Bipolar or CMOS technologies. Ref.

Technology

[Fau83] 5 µm Bipolar [Rei87] 2 µm Bipolar [P¨ oh94] 0.4 µm Bipolar [S¨ ac00] 0.25 µm CMOS [Hol03] [Gal03] [Gal04] [Cra05]

0.18 0.18 0.18 0.18

µm µm µm µm

CMOS CMOS CMOS CMOS

Vdd 6V 5V −4 V 2.5 V & 3.4 V 1.8 V 1.8 V 2.2 V 1.8 V

[Her05] 0.18 µm CMOS 1.8 V [Her06c] 0.18 µm CMOS 1.8 V

Adif f

GBW

Bitrate

Pdiss

Sensitivity

Max. signal

60 dB 470 GHz 650 Mbit/s 250 mW 300 µVpp 300 mVpp 54 dB 1103 GHz 4 Gbit/s 350 mW 2 mVpp 400 mVpp 45 dB 1600 GHz 10 Gbit/s 400 mW 2.25 mVpp 32 dB 119 GHz 43 dB 50 dB 15 dB 42 dB

2.5 Gbit/s 190 mW

2 mVpp

297 GHz 2 Gbit/s 79 mW 2973 GHz 10 Gbit/s 100 mW 4.6 mVpp 124 GHz 40 Gbit/s 190 mW 393 GHz 3.125 Gbit/s 113 mW 2.5 mVpp

27 dB 94 GHz 38 dB 397 GHz

3.5 Gbit/s 6 Gbit/s

34 mW 72 mW

10 mVpp 8 mVpp

Oﬀset comp. no yes yes

2 Vpp

yes

50 mVpp

no yes no yes

600 mVpp

no yes

166

6 CMOS Realizations

higher photodiode junction capacitance at the dominant input node and due to the limited voltage gain in submicron CMOS technologies. The next building block implemented in a 0.18 µm CMOS technology has been a limiting ampliﬁer. A Cherry-Hooper topology has been used to broaden the bandwidth instead of space-consuming passive inductors or noisy active inductors. The output buﬀer necessary to drive the 50 Ω oﬀ-chip load comprises two fT -doublers. To demonstrate the implemented broadband techniques, eye diagrams with low BER up to 3.5 Gbit/s have been measured. The performance of this chip competes with present state-of-the-art (Table 6.8). Finally, all knowledge has been gathered in the design of the fully integrated 0.18 µm CMOS optical receiver. It contains a diﬀerential photodiode, a diﬀerential TIA, an equalizer to enhance the intrinsic speed of the diﬀerential PD, a high-speed LA with oﬀset-compensation and an output buﬀer including 3 fT -doublers. Applying purely electrical diﬀerential signals at the input, the receiver behaves according to the simulations: bitrates up to 5 Gbit/s have been measured with low BER. The stand-alone LA with output buﬀer can handle bitrates even up to 6 Gbit/s, and outperforms several recently published 0.18 µm CMOS LAs (Table 6.8). Further work needs to be done to improve the opto-electrical measurements, and the attention should be focused on the reduction of the jitter due to an insuﬃcient common-mode suppression. However, this work already demonstrates that receiving 850 nm prbs light signals with bitrates higher than 1 Gbit/s is feasible in a mainstream CMOS technology.

7 Conclusions

After the free fall of the telecommunication industry in the beginning of this century, a gradual recovery started in 2004. At the end of 2006, this positive evolution continues and people start to dream again. Numerous new optoelectronic applications are emerging, while low cost remains a prime concern. The simple law of economics dictates that the existing III-V compound semiconductor opto-electronics industry will be aﬀected by optical devices made of silicon. Nowadays, silicon devices can achieve almost all of the necessary functions for integrated optical devices, like detectors, modulators and switches. Only an electrically powered silicon light source, preferably a laser, is lacking, although successful research is going on also in this ﬁeld, for instance by Intel [CP06, Pan05] and by STMicroelectronics [Cof05]. If a commercial silicon laser ﬁnally would be available, the sky is the limit and silicon photonics will become reality. It will allow manufacturers to build optical components using the same semiconductor equipment and methods they use now for ordinary integrated circuits, thereby dramatically lowering the cost of photonics. The presented work ﬁts in this research on silicon opto-electronics. To further lower the cost, the cheapest technology has been selected: standard CMOS, without any optical tricks or ﬂavors. Of course this mainstream CMOS technology has an inherent lower performance than dedicated (Bi)CMOS or compound semiconductor technologies. The goal of this work is to demonstrate the feasibility of light detection in the same CMOS technology that is used to manufacture standard digital circuits. Furthermore, it is shown in theory and practice that the inherent low speed performance of CMOS diodes can be enhanced both on the detector level and on the circuit level. Besides the design of the photodiode, the focus lies on the design of the transimpedance ampliﬁer and the post-ampliﬁer. The main contributions and achievements are: • The fundamental laws of semiconductor physics have been reviewed to gain in-depth understanding of the opto-electrical mechanisms in silicon detectors. These insights have lead to the development of a one-dimensional

167

168

7 Conclusions

analytical model of the photodiode junction. A complementary numerical two-dimensional model has been developed taking into account more side eﬀects like retrograde doping proﬁles and side-wall junctions. These eﬀects are important for more complicated diode topologies and will also become more and more pronounced for the emerging nm-scale technologies. Based on this two-dimensional model, the theoretical performances of diﬀerent kinds of diode topologies have been compared. As the market today is characterized by two important phenomena: Moore’s law on the electrical side and the development of new light sources on the optical side, these trends have been evaluated using the two-dimensional model. • An in-depth high-level analysis of the shunt-shunt feedback transimpedance ampliﬁer has been presented. Analytical equations have been derived for the transimpedance gain, bandwidth, transimpedance-bandwidth product, loop gain, gain margin and noise. The core ampliﬁer has been modeled as a black box characterized by DC voltage gain A0 , input capacitance Cin and output impedances Cout and Rout . The applied assumptions and approximations have been pointed out explicitly, as a good designer should be aware that design equations are only valid in a limited design space. However, the trends predicted by these equations form a solid base for a sound design. In a next phase, the ampliﬁer’s black box has been opened, and a literature overview of possible implementations has been given. Finally, a detailed study at the transistor level of three diﬀerent common-source TIAs has been presented. Confronting simulation results with design equations has revealed that the basic design assumptions are not always valid when pushing the performance to its limits. Also a more accurate noise model for the photodiode has been elaborated, that takes into account the parasitic series resistance. • The design of a broadband limiting ampliﬁer, consisting of several cascaded gain stages, has been presented. After a (historical) literature study, a Cherry-Hooper topology has been preferred over inductive peaking stages. Analytical design equations have been derived for this broadband stage which again form a solid base for a good design. Also for this building block the assumptions and approximations made to arrive at the equations have been highlighted, so the designer can use them consciously. In addition to the Cherry-Hooper stage, a capacitive source degenerated stage has been analyzed. Finally the technique of oﬀset compensation, indispensable in high-performance LAs, has been disclosed. The theory has been completed with two case studies that clearly illustrate all design choices encountered during the design of an analog high-performance circuit. • An important achievement reached in this work is the systematic analysis, design and implementation of diﬀerent CMOS photodiode topologies. The photodiodes have been realized together with TIAs and output buﬀers in mainstream CMOS technologies and these opto-electronic circuits have been tested in a real-life measurement set-up. Optical signals from a commercial 850 nm transmitter were applied at the input. The

7 Conclusions

169

conclusion is that a diﬀerential photodiode is the best topology choice when high bitrates are pursued, at the expense of a lower responsivity. A comparison of the 0.18 µm PDs with the 90 nm PDs, reveals that technology downscaling is not beneﬁcial for the overall photodiode performance. Also for the TIA, newer technologies with higher fT ’s are not necessarily better, as it becomes more diﬃcult to achieve a high voltage gain in sub-micron technologies. This high voltage gain is needed to maximize the transimpedance-bandwidth product. This should however not impede the CMOS integration of opto-electrical front-ends in future technologies: analog design engineers will always be inventive enough to ﬁnd new solutions for new problems. • To demonstrate the broadband amplifying prospects of CMOS CherryHooper ampliﬁers, a ﬁrst LA is designed, manufactured in 0.18 µm CMOS and measured. The experience gained in this design cycle has lead to the design and measurements of a second LA incorporating oﬀset compensation. The performance achieved by this circuit outperforms present stateof-the-art. Table 6.8 compares the described LAs with the LAs studied in Section 5.3. Looking at the CMOS implementations, only [Gal03] (which integrates passive inductors) has a higher gain-bandwidth than [Her06c]. The broadband techniques applied in [Gal03] are undoubtedly very eﬀective to achieve circuits with high gain-bandwidth. However, power dissipation of the core ampliﬁer (excluding output buﬀers) is higher than in [Her06c]. • The ﬁnal achievement has also been the largest challenge for the presented research: the realization of a monolithic optical receiver front-end, consisting of a PD, TIA and LA. To realize this goal, a very systematic approach has been chosen, where ﬁrst the three building blocks have been studied separately, but at the same time their mutual impact never has been neglected. To enhance the speed performance of the diﬀerential photodiode even further, an analog equalizer compensates for its frequency roll-oﬀ. Table 6.7 compares the presented work with other state-of-the-art integrated opto-electrical receivers and shows that it features the highest level of integration, while its performance is comparable to other designs. The input signals for the photodiode are provided by a commercial available 850 nm optical transmitter. Finally note that, to the author’s knowledge, the chip presented in [Her06c] is the ﬁrst monolithic CMOS opto-electrical receiver integrating photodiode, transimpedance ampliﬁer and limiting ampliﬁer, that achieves bitrates higher than 1 Gbit/s.

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Index

absorption coeﬃcient, 28 automatic gain control ampliﬁer, 14, 107 average mark density, 18

depletion region, 28, 30 diﬀerential n-well diode, 52, 54, 57, 82, 97, 135, 139, 141, 152 diﬀusion, 28, 37, 39 drift, 28, 40 DVD, 16, 52

bandwidth-distance product, 7 baseline wander, 25 BiCMOS, 32 bit error rate, 20, 141, 149, 157 bit period, 17 bitrate, 17 bitrate-distance product, 2 block coding, 18 Blu-Ray Disc, 6, 16, 52 burst mode, 19

electric ﬁeld, 28 electrical sensitivity, 22 equalizer, 36, 154 extrinsic bandwidth, 31 eye diagram, 20, 138, 144, 149, 157

CD, 16, 52 Cherry-Hooper ampliﬁer, 113, 116 classical n-well diode, 47, 53, 57, 82, 93, 135, 139, 143, 146 clock and data recovery circuit, 14 CMOS, 31, 32, 35 common gate TIA, 78 common source TIA, 77, 81 Communications Technology Roadmap, 7 complementary self-biased diﬀerential ampliﬁer, 136 continuity equation, 37, 39 continuous mode, 19 damping ratio, 65 DC wander, 25 demultiplexer, 14

fT -doubler, 148, 156 ﬁber, 2 ﬁber-to-the-home, 4 frequency roll-oﬀ, 49, 50, 52, 54, 57 gain-bandwidth product, 114 HD-DVD, 6, 16, 52 inductive peaking, 110 input dynamic range, 109 input oﬀset voltage, 110 input-referred noise, 62, 73 intersymbol interference, 23 intrinsic 3-dB bandwidth, 48, 50, 51, 54, 57 intrinsic bandwidth, 31 intrinsic frequency characteristic, 48, 50, 53, 55, 56, 58 ISSCC, 80

177

178

Index

jitter, 25, 110, 149, 157, 163 junction capacitance, 57 Lambert-Beer’s Law, 28 laser, 2, 14 laser diode, 14 laser driver, 14 light ﬂux, 30 limiting ampliﬁer, 14, 107, 124, 126, 146 line coding, 18 local area networks, 4 long-haul communication systems, 2 measurement set-up, 134 Medici, 46 modiﬁed Cherry-Hooper ampliﬁer, 117 modulator driver, 14 Moore’s Law, 6, 56 multiplexer, 14 n+ p-substrate diode, 82, 135, 140 n-well p-substrate junction, 38 natural pulsation, 65 noise bandwidth, 63 non-return-to-zero, 17 oﬀset, 163 oﬀset compensation, 122 one-dimensional model, 37 optical sensitivity, 23 optical telegraph, 1 output buﬀer, 143, 147, 156 output noise, 62, 71, 73, 89 overload current, 63 p+ n-well diode with guard, 49, 82, 93, 135, 139, 143, 146, 147 p+ n-well junction with guard, 44 PA bandwidth, 109 penetration depth, 30 phase margin, 69

photodiode, 13, 17, 29, 87, 88 photons, 28 photophone, 2 PIN diode, 33 plastic optical ﬁber, 5 POF, 52 post-ampliﬁer, 14, 17, 107 pseudorandom bit sequence, 18 Q function, 21 Q-factor, 145 quantum eﬃciency, 30 quasi-fractal n-well diode, 82, 93, 135, 139, 143, 146 regulated cascode TIA, 78 responsivity, 30, 48–51, 53–58 retrograde well doping proﬁle, 47 run length, 18 scrambling, 18 sensitivity, 22 series-series feedback, 111, 112 shot noise, 71 shunt-shunt feedback, 63, 111, 112 SML-detector, 36, 51 SOI, 34 space charge region, 28 technology scaling, 57 thermal noise, 70, 71 TIA bandwidth, 62, 65, 66 transceiver, 15 transimpedance ampliﬁer, 14, 17, 61, 82, 93, 97 transimpedance gain, 61, 64 transimpedance-bandwidth product, 67 two-dimensional model, 46 wavelength, 52

ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES Consulting Editor: Mohammed Ismail. Ohio State University Titles in Series: BROADBAND OPTO-ELECTRICAL RECEIVERS IN STANDARD CMOS Hermans, Carolien, Steyaert, Michiel ISBN 978-1-4020-6221-6 ANALOG CIRCUIT DESIGN TECHNIQUES AT 0.5V Chatterjee, S., Kinget, P., Tsividis, Y., Pun, K.P. ISBN-10: 0-387-69953-8 IQ CALIBRATION TECHNIQUES FOR CMOS RADIO TRANCEIVERS Chen, Sao-Jie, Hsieh, Yong-Hsiang ISBN-10: 1-4020-5082-8 LOW-FREQUENCY NOISE IN ADVANCED MOS DEVICES Haartman, Martin v., Östling, Mikael ISBN-10: 1-4020-5909-4 THE GM/ID DESIGN METHODOLOGY FOR CMOS ANALOG LOW POWER INTEGRATED CIRCUITS Jespers, Paul G.A. ISBN-10: 0-387-47100-6 PRECISION TEMPERATURE SENSORS IN CMOS TECHNOLOGY Pertijs, Michiel A.P., Huijsing, Johan H. ISBN-10: 1-4020-5257-X CMOS CURRENT-MODE CIRCUITS FOR DATA COMMUNICATIONS Yuan, Fei ISBN: 0-387-29758-8 RF POWER AMPLIFIERS FOR MOBILE COMMUNICATIONS Reynaert, Patrick, Steyaert, Michiel ISBN: 1-4020-5116-6 IQ CALIBRATION TECHNIQUES FOR CMOS RADIO TRANCEIVERS Chen, Sao-Jie, Hsieh, Yong-Hsiang ISBN: 1-4020-5082-8 ADVANCED DESIGN TECHNIQUES FOR RF POWER AMPLIFIERS Rudiakova, A.N., Krizhanovski, V. ISBN 1-4020-4638-3 CMOS CASCADE SIGMA-DELTA MODULATORS FOR SENSORS AND TELECOM del Río, R., Medeiro, F., Pérez-Verdú, B., de la Rosa, J.M., Rodríguez-Vázquez, A. ISBN 1-4020-4775-4 SIGMA DELTA A/D CONVERSION FOR SIGNAL CONDITIONING Philips, K., van Roermund, A.H.M. Vol. 874, ISBN 1-4020-4679-0 CALIBRATION TECHNIQUES IN NYQUIST A/D CONVERTERS van der Ploeg, H., Nauta, B. Vol. 873, ISBN 1-4020-4634-0 ADAPTIVE TECHNIQUES FOR MIXED SIGNAL SYSTEM ON CHIP Fayed, A., Ismail, M. Vol. 872, ISBN 0-387-32154-3 WIDE-BANDWIDTH HIGH-DYNAMIC RANGE D/A CONVERTERS Doris, Konstantinos, van Roermund, Arthur, Leenaerts, Domine Vol. 871 ISBN: 0-387-30415-0 METHODOLOGY FOR THE DIGITAL CALIBRATION OF ANALOG CIRCUITS AND SYSTEMS: WITH CASE STUDIES Pastre, Marc, Kayal, Maher Vol. 870, ISBN: 1-4020-4252-3 HIGH-SPEED PHOTODIODES IN STANDARD CMOS TECHNOLOGY Radovanovic, Sasa, Annema, Anne-Johan, Nauta, Bram Vol. 869, ISBN: 0-387-28591-1 LOW-POWER LOW-VOLTAGE SIGMA-DELTA MODULATORS IN NANOMETER CMOS Yao, Libin, Steyaert, Michiel, Sansen, Willy Vol. 868, ISBN: 1-4020-4139-X DESIGN OF VERY HIGH-FREQUENCY MULTIRATE SWITCHED-CAPACITOR CIRCUITS U, Seng Pan, Martins, Rui Paulo, Epifânio da Franca, José Vol. 867, ISBN: 0-387-26121-4 DYNAMIC CHARACTERISATION OF ANALOGUE-TO-DIGITAL CONVERTERS Dallet, Dominique; Machado da Silva, José (Eds.) Vol. 860, ISBN: 0-387-25902-3

Broadband Opto-Electrical Receivers in Standard CMOS By

CAROLIEN HERMANS KU Leuven, Belgium

and

MICHIEL STEYAERT KU Leuven, Belgium

A C.I.P. Catalogue record for this book is available from the Library of Congress.

ISBN 978-1-4020-6221-6 (HB) ISBN 978-1-4020-6222-3 (e-book) Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands. www.springer.com

Printed on acid-free paper

All Rights Reserved c 2007 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work.

Preface

The gradual recovery of the optical industry since 2004 has enabled new developments in the communication, consumer and entertainment markets. Lots of new applications are emerging where high volumes and low cost aspects are crucial. To meet these demands, silicon microphotonics aims for the manufacturing of opto-electrical components in the same platform that has enabled Moore’s Law: single-crystal silicon. The presented work ﬁts in this quest for integrated opto-electrical solutions, and focuses on the receiver front-end. To further reduce the cost, the cheapest technology is selected: standard CMOS, without any optical tricks or ﬂavors. Despite the inherent lower optical performance of a mainstream CMOS process, it is shown in theory and practice that light detection is feasible with CMOS diodes. Furthermore, speed enhancement techniques are presented to extend the speed performance above 1 Gbit/s. The three receiver blocks examined in this work are the photodiode (PD), the transimpedance ampliﬁer (TIA) and the limiting ampliﬁer (LA). First, to thoroughly understand the light detection mechanisms in silicon, the basic semiconductor one-dimensional equations are studied. Next, a twodimensional model is developed to compare the performance of diﬀerent types of photodiodes implemented in successive technology generations and for three input wavelengths. Analytical design equations are derived to guide the design of the amplifying circuits. For the TIA, the focus lies on the sensitivity-speed trade-oﬀ. For the LA, a high gain-bandwidth is pursued. Theory is put into practice through several CMOS implementations. A ﬁrst 0.18 µm chip compares diﬀerent photodiode topologies. The diﬀerential diode with TIA has the best high-speed performance and achieves a BER of 3 · 10−10 when a 500 Mbit/s optical signal of −8 dBm is applied. Next, different photodiode topologies manufactured in a 90 nm CMOS technology are compared. The best results are obtained with the p+ n-well diode with guard. This diode with TIA can handle data with bitrates up to 500 Mbit/s and an optical power of −8 dBm, showing a BER of 10−9 . A third chip contains a LA implemented in 0.18 µm CMOS and based on a cascade of Cherryv

vi

Preface

Hooper stages. Eye diagrams at 3.5 Gbit/s illustrate the applied broadband techniques. Finally, all knowledge is gathered in the design of a monolithic optical receiver front-end in 0.18 µm CMOS. This chip contains a diﬀerential CMOS photodiode, a diﬀerential two-stage TIA with cross-coupled feed-back and a high-gain broadband LA. The speed performance of the photodiode is further enhanced by an analog equalizer. The TIA achieves a transimpedancebandwidth product of 19 THzΩ. The LA features a gain-bandwidth product of 397 GHz. At 6 Gbit/s, the LA with output buﬀer has a BER of 10−12 when 8 mVpp is applied at the input. The complete receiver is characterized by a BER smaller than 10−12 for a −6 dBm optical input signal with a bitrate of 1.7 Gbit/s. This receiver competes with present state-of-the-art and is, to the author’s knowledge, the ﬁrst CMOS Gbit/s opto-electrical receiver integrating PD, TIA and LA on the same die.

Heverlee, March 2007

Carolien Hermans Michiel Steyaert

List of Abbreviations and Symbols

Abbreviations ac AGC BER BiCMOS CD CDR CG CMOS CMU CSD DC DG DMUX DSL DVI DVD DWDM ECL FTTH GaAs GaN GB Ge HD-DVD IC In0.53 Ga0.47 As InP ISI ISSCC

Alternating Current Automatic Gain Control Bit Error Rate Bipolar Complementary Metal Oxide Semiconductor Compact Disc Clock and Data Recovery Common Gate Complementary Metal Oxide Semiconductor Clock Multiplication Unit Capacitive Source Degeneration Direct Current Diﬀraction Grating Demultiplexer Digital Subscriber Loop Digital Video Interface Digital Versatile Disc Dense Wavelength-Division Multiplexing Emitter Coupled Logic Fiber-To-The-Home Gallium Arsenide Gallium Nitride Gigabyte Germanium High Density Digital Versatile Disc Integrated Circuit Indium Gallium Arsenide Indium Phosphide Intersymbol Interference International Solid-State Circuits Conference vii

viii

List of Abbreviations and Symbols

LA LAN LD LED MAN MOS MOST MUX nMOS NA NIC NRZ pMOS prbs PA ParBERT PBS PCS P.M. PMMA P.O. POF PON OEIC POF QWP RGC RZ SAN SDH Si SiO2 SML-detector SNR SOI SONET TAS TIA TIS UI VA VCSEL VUC WAN WDM

Limiting Ampliﬁer Local Area Network Laser Diode Light Emitting Diode Metro(politan) Area Network Metal Oxide Semiconductor Media Oriented System Transport Multiplexer n-channel MOS transistor Numerical Aperture Negative Impedance Converter Non-Return-to-Zero p-channel MOS transistor Pseudorandom Bit Sequence Post-Ampliﬁer Parallel Bit Error Ratio Tester Polarization Beam Splitter Polymer-Clad Silica Phase Margin Polymethyl Methacrylate Percent Overshoot Plastic Optical Fiber Passive Optical Networks Opto-electronic Integrated Circuit Plastic Optical Fiber Quarter-Wave Plate Regulated Cascode Return-to-Zero Storage Area Network Synchronous Digital Hierarchy Silicon Silicon dioxide Spatially Modulated Light detector Signal to Noise Ratio Silicon on Insulator Synchronous Optical Network Transadmittance Stage Transimpedance Ampliﬁer Transimpedance Stage Unite Interval Voltage Ampliﬁer Vertical-Cavity Surface-Emitting laser Voltage-Up-Converter Wide Area Networks Wavelength-Division Multiplexing

List of Abbreviations and Symbols

Symbols A A0 A1st ACH ACSD Adif f Aos AP A AP A,0 BWn BWP A BWT IA BWV A c Cdio Cds Cgs Cin CinT Cnext Cout CoutT Cox di2dio di2Mα di2n,T IA di2Rα 2 dvn,T IA Dn Dp Eg Ep f0dB,GH f3dB f3dB,1st f3dB,P A fd,GH fLF

voltage gain DC voltage gain diﬀerential gain of a single stage of a post-ampliﬁer diﬀerential gain of a Cherry-Hooper stage diﬀerential gain of a voltage ampliﬁer with capacitive source degeneration diﬀerential gain gain of an oﬀset compensation ampliﬁer gain of a post-ampliﬁer mid-band gain of a post-ampliﬁer noise bandwidth 3-dB bandwidth of a post-ampliﬁer 3-dB bandwidth of a TIA 3-dB bandwidth of a voltage ampliﬁer speed of light in vacuum diode junction capacitance drain-source capacitance gate-source capacitance input capacitance total input capacitance input capacitance of the next stage output capacitance total output capacitance oxide capacitance diode shot noise thermal channel noise of transistor Mα power spectral density of the TIA input-referred noise current thermal current noise of transistor Rα power spectral density of the TIA output noise voltage electron diﬀusion constant hole diﬀusion constant bandgap energy photon energy unity-gain frequency of the loop gain 3-dB bandwidth 3-dB bandwidth of a single stage of a post-ampliﬁer 3-dB bandwidth of a post-ampliﬁer dominant pole of the loop gain low-frequency cut-oﬀ

ix

x

List of Abbreviations and Symbols

fnd,GH fnd,T IA fT FBW gds gm G Geq Gm,CSD GT IA GBW GHT IA h iin in,rms in,OR in,T IA isens pp Idio Ids Jdrif t Jdif f n Jdif f p Kn Kp L LMCH Lb Lnw Lscr Lsd Mi n n(t) n0 NA ND Nf Ns p p0

non-dominant pole of the loop gain non-dominant pole of TIA unity current gain frequency factor deﬁned by the ratio of BWV A and BWT IA transistor output conductance transistor transconductance light generation term transfer function of the equalizer eﬀective transconductance of an ampliﬁer stage with capacitive source degeneration TIA open-loop gain gain-bandwidth product TIA loop gain Planck’s constant small-signal input current equivalent input-referred rms noise total integrated input-referred optical receiver current noise total integrated input-referred TIA current noise electrical receiver sensitivity diode current drain-source current drift current density electron diﬀusion current density hole diﬀusion current density transconductance parameter for an nMOS transistor transconductance parameter for a pMOS transistor transistor length loop gain of the feedback loop in the modiﬁed Cherry-Hooper stage depth in the substrate where n = n0 depth of the n-well, upper edge of space charge region lower edge of the space charge region depth of the source/drain region, upper edge of the space charge region Miller factor electron concentration noise voltage initial electron concentration acceptor concentration in p-substrate donor concentration in n-well number of ﬁngers in a photodiode topology number of squares in a photodiode topology hole concentration initial hole concentration

List of Abbreviations and Symbols sens Pav Pdiss Pn Popt Px q Q(x) R Rb Rdark Rf Rlight Rout Sout t Tb vn,LA

vn,rms vout vpp Vbi Vds Vgs VDSAT VR VT VT H V0 V1 W x x(t) XN ZBW Zin,0 ZN IC ZT IA ZT IA,0 α αgd γ Si ζ η

optical receiver sensitivity power dissipation probability density function for noise (average) optical power probability density function for the wanted signal elementary charge Q function responsivity of a photodiode bitrate responsivity of the dark junctions feedback resistance responsivity of the illuminated junctions output resistance power spectral density of the output signal time bit period total integrated input-referred limiting ampliﬁer voltage noise rms noise voltage small-signal output voltage peak-to-peak value of the received signal built-in voltage drain-source voltage gate-source voltage saturation voltage of a MOS transistor reverse voltage threshold voltage of a transistor threshold voltage of the decision circuit logic zero level logic one level transistor width depth received signal voltage ratio of Cgs to Cdio transimpedance-bandwidth product DC input impedance impedance of a negative impedance converter TIA transimpedance gain TIA DC transimpedance gain absorption coeﬃcient of light (in Silicon) ratio between Cgd and Cgs excess noise factor Silicon permittivity damping ratio of a second-order system quantum eﬃciency of a photodiode

xi

xii

θ(f ) λ λc μ ν τ τn τp Φ Φ0 ωn ω3dB

List of Abbreviations and Symbols

frequency-dependent phase shift wavelength of light maximum absorbed wavelength mobility frequency of light time constant electron minority carrier lifetime hole minority carrier lifetime light ﬂux initial light ﬂux natural pulsation of a second-order system 3-dB bandwidth of a second-order system

Contents

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

List of Abbreviations and Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 A History of Optical Communication . . . . . . . . . . . . . . . . . . . . . . 1.2 Emerging Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Silicon Opto-Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Outline of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1 4 7 9

2

Optical Receiver Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 The Optical Receiver Front-End . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 A Transceiver for Optical Communication Systems . . . . 2.2.2 A Pickup Unit for Optical Storage Systems . . . . . . . . . . . 2.3 Binary Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Bit Error Rate and Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 Bit Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Intersymbol Interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 Low-Pass Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 High-Pass Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13 13 13 13 15 17 20 20 22 23 23 24 25 26

3

Standard CMOS Photodiodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Principles of Light Detection . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 The Use of Standard CMOS . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Overview of Published Integrated Photodiodes . . . . . . . . . . . . . .

27 27 27 28 31 32

xiii

xiv

Contents

3.3.1 BiCMOS Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 SOI Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 CMOS Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 One-Dimensional Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 N-Well P-Substrate Junction . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 P+ N-Well Junction with Guard . . . . . . . . . . . . . . . . . . . . 3.5 Two-Dimensional Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Classical N-Well Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 P+ N-Well Diode with Guard . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 Diﬀerential N-Well Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.4 Inﬂuence of Wavelength . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.5 Inﬂuence of Technology Scaling . . . . . . . . . . . . . . . . . . . . . 3.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

32 34 35 36 37 37 43 46 46 49 51 52 56 58

4

Transimpedance Ampliﬁer Design . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.2 Performance Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3 Design of the Shunt-Shunt Feedback TIA . . . . . . . . . . . . . . . . . . . 63 4.3.1 Transimpedance Gain and Bandwidth . . . . . . . . . . . . . . . . 64 4.3.2 Open-Loop Gain and Loop Gain . . . . . . . . . . . . . . . . . . . . 68 4.3.3 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.4 Literature Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.4.1 Common Source TIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.4.2 Regulated Cascode TIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.4.3 The Latest Trends at ISSCC . . . . . . . . . . . . . . . . . . . . . . . . 80 4.5 Case Studies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.5.1 An Inverter-Based TIA for Test Photodiodes in 0.18 µm CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.5.2 An Inverter-Based TIA for Test Photodiodes in 90 nm CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.5.3 A Diﬀerential Bandwidth-Optimized TIA in 0.18 µm CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5

Post-Ampliﬁer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.2 Performance Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.3 Literature Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.4 Design of a Fully Diﬀerential Broadband LA . . . . . . . . . . . . . . . . 113 5.4.1 Cascaded Gain Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.4.2 Broadband Cherry-Hooper Stage . . . . . . . . . . . . . . . . . . . . 116 5.4.3 Broadband Stage with Capacitive Source Degeneration . 120 5.4.4 Oﬀset Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.5 Case Studies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Contents

xv

5.5.1 A Four-Stage LA in 0.18 µm CMOS . . . . . . . . . . . . . . . . . 124 5.5.2 A Five-Stage LA with Oﬀset Compensation in 0.18 µm CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6

CMOS Realizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 6.2 Test Photodiodes with TIA in 0.18 µm CMOS . . . . . . . . . . . . . 135 6.2.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 6.2.2 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.3 Test Photodiodes with TIA in 90 nm CMOS . . . . . . . . . . . . . . . . 142 6.3.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.3.2 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 6.4 A 3.5 Gbit/s LA in 0.18 µm CMOS . . . . . . . . . . . . . . . . . . . . . . . 146 6.4.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.4.2 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 6.5 A Gbit/s Monolithic Optical Receiver Front-End in 0.18 µm CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 6.5.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 6.5.2 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

7

Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

1 Introduction

1.1 A History of Optical Communication Light as means of communication is not only used in our sophisticated, technology-driven modern era. Since earlier times, man has depended on light to send messages, mostly in the form of ﬁre. The Greek tragedian Aeschylus portrays in the ‘Oresteia’ trilogy (458 BC) how the news about the fall of Troy was sent by ﬁre signals via an unbroken line of beacon-ﬁres from Asia Minor to Mycenae. A few centuries later, the Greek historian Polybius writes ‘The Histories’ or ‘The Rise of the Roman Empire’, covering the period of 220 BC to 146 BC. In this work, he describes an arrangement by which the whole Greek alphabet could be transmitted by ﬁre signals using a two-digit, ﬁve level code. This communication link allowed the transmission of messages not previously agreed upon. The ﬁrst development of a useful optical telegraph dates from the time of the French Revolution. As France was threatened by inner and outer opponents, a new communication system was necessary. The civilian Claude Chappe, a former priest, invented a mechanical-optical telegraph. It consisted of a column with a movable crosswise beam. This beam also had two movable arms. Each arm had seven positions, and the crosswise beam had four more, permitting a 196-combination code. The arms were from 1 m to 10 m long, black, and counterweighted, moved by only two handles. Lamps mounted on the arms proved unsatisfactory for night use. The equipment stood on rooftops or towers, placed from 12 km to 25 km apart. Each tower had a telescope pointing both up and down the relay line. The ﬁrst telegraph line of this sort was put into operation in 1794. The telegraph line consisted of 22 stations and linked Lille with the capital Paris, a distance of over 240 kilometers. It only took 2 to 6 minutes to transfer a message, riding couriers would have needed 30 hours. Other lines were built, including a line from Paris to Toulon. The system was widely copied by other European states, and was used by Napoleon to coordinate his empire and army. In the middle of the 19th century, the optical telegraph was replaced by the electrical telegraph, patented 1

2

1 Introduction

by Samual Morse in 1837. Major advantage of the latter system was a faster signal transmission. In 1880, Alexander Graham Bell invented the photophone. Bell considered this a greater discovery than his previous invention, the telephone. Bell’s photophone worked by projecting voice through an instrument towards a mirror. Vibrations in the voice caused similar vibrations in the mirror. Bell directed sunlight into the mirror, which captured and projected the mirror’s vibrations. The receiver’s mirror received the light and caused a selenium crystal to vibrate, and the sound would come out on the other end. Although the photophone was successful in allowing conversation over open space at a distance up to 200 m, it had a few drawbacks: it did not work well at night, in the rain, or if someone walked between the signal and the receiver. Eventually, Bell gave up on this idea. These anecdotes illustrate that people always have tried to use light, even in its most primitive form, to deliver some type of information between remote locations. The most important drawback is the dependence on atmospheric conditions, that makes direct optical communication through the air unreliable. The advent of the laser in the early 60’s was an important revolution and boosted the development of optical communication systems. The solution to the atmospheric disturbances was found to be the use of optical waveguides that forces the laser beam to follow a certain path. One of the pioneers in the ﬁeld of ﬁber optics is the Dutch scientist Abraham van Heel. In the beginning of the 50’s, he tried to solve the problem of light loss in ﬁbers by using a cladding material. All earlier ﬁbers developed were bare and lacked any form of cladding, with total internal reﬂection occurring at a glass-air interface. The transparent cladding, with a lower refractive index than the glass or plastic ﬁber, protected the total reﬂection surface from contamination and greatly reduced the crosstalk between ﬁbers. By 1960, glass-clad ﬁbers had an attenuation of about 1000 dB/km, ﬁne for medical imaging, but much too high for communication applications. An important milestone in the history of ﬁber-optic communications is the paper [Kao66], published in 1966 by Charles Kao and George Hockam. They showed that optical ﬁber communication would be feasible if the transmission loss could be reduced to less than 20 dB/km. Moreover, they proved that there was no fundamental mechanism that would prevent this loss from being achieved. Only 4 years later, in 1970, Robert Maurer, Donald Keck and Peter Schultz of Corning Glass Corporation achieved this goal and manufactured the ﬁrst optical ﬁber with an attenuation less than 20 dB/km. By 1980, the attenuation loss was reduced even further, and ﬁrms were experimenting with putting cables under the sea. The ﬁrst international undersea ﬁber-optic link, which linked England with Belgium, was installed in 1986. By the end of 1988, the ﬁrst transatlantic ﬁber-optic cable, connecting the United States with Europe, was a fact. The evolution of long-haul communication systems in summarized in Table 1.1. Every generation is characterized by a considerable increase in bitrate-distance product, the ﬁgure of merit com-

Table 1.1. The ﬁve generations of long-haul ﬁber optical communication systems [Agr97, Gra02]. gen. date ﬁrst

bitrate

distance

bitrate-distance product

λ

150 Mbit/s − km 0.8 µm larger repeater space than electrical communication graded-index ﬁber

1980 45 Mbit/s

10 km

second 1987 1.7 Gbit/s

50 km

85 Gbit/s − km

third 1990 2.5 Gbit/s

70 km

175 Gbit/s − km 1.55 µm

1.3 µm

fourth 1996 5 Gbit/s 11300 km 56.5 Tbit/s − km 1.55 µm 2000 100 Gbit/s 9000 km 900 Tbit/s − km ﬁfth

properties

2002 1.28 Tbit/s 4000 km 5120 Tbit/s − km 1.55 µm

single-mode ﬁber minimum dispersion ﬁber loss < 1 dB/km minimal loss (< 0.2 dB/km) dispersion-shifted ﬁber erbium-doped optical ampliﬁers wavelength-division multiplexing (WDM) solitons distributed Raman ampliﬁcation forward error correction dense wavelength-division multiplexing (DWDM)

4

1 Introduction

monly used for optical communication systems. In the early generations, this capacity increase was mainly due to an improvement of the ﬁber properties (lower dispersion, minimal loss), combined with the development of lasers and detectors operating at longer wavelengths. During the fourth generation, the electrical repeater distance was drastically raised by using erbium-doped ampliﬁers, spaced 60 km to 100 km apart, that regenerate the signal optically. The bitrate on the other hand was increased by using the technique of wavelength-division multiplexing (WDM). The era of terabit communication systems has truly arrived with the ﬁfth generation. Todays’ commercial equipments are capable of sending 2.56 Tbit/s (64x40 Gbit/s channels) data over a distance of up to 1000 km, or 1.28 Tbit/s (128x10 Gbit/s channels) data over a distance of up to 4000 km, without any electrical regeneration. The key technologies to realize this high capacity are solitons, distributed Raman ampliﬁcation, forward error correction and dense WDM [Gra02].

1.2 Emerging Applications As revealed in the previous section, the historical popularity of optical ﬁber communication is mainly due to the need of larger bitrate-distance products in the ﬁeld of long-haul communication systems. This section takes a look at some other opto-electrical domains where interesting movements are going on. Short-Distance Communication Networks Optical ﬁber networks have many advantages over copper networks. Besides the high bitrate-distance product, exploited by long-haul communication networks, optical ﬁbers are insensitive to spurious noise signals and avoid electrical ground loops. However, the ultimate reason to replace copper wires with optical ﬁbers remains a purely economical one: a lower cost. Nowadays, bandwidth demands for short-distance communications are increasing exponentially. As a consequence, the critical point will be reached soon where improving the technology supporting these high-bandwidth applications over copper wires will cost more than accomplishing the same speed over ﬁber. To make short-distance ﬁber communication aﬀordable, the industry has developed low-cost solutions like high-bandwidth multimode ﬁbers and 850 nm transceivers. Eventually, ﬁber optics will ﬁnd its way in local area networks (LANs) and new systems like ﬁber-to-the-home (FTTH) will become viable. Note however that there is a large discrepancy between the US and Asia on the one hand, and Europe on the other hand. While the US and Asia invest heavily in deep-ﬁber deployments and FTTH is already available, almost whole Europe lags behind (a few areas, like the former DDR, are an exception). The crowded and fully-wired European countries prefer to extend the possibilities of copper wires by supporting standards like DSL.

1.2 Emerging Applications

5

In-Car Fiber-Optic Networks Opto-electronic systems also become more and more attractive for communication inside cars [Fre04]. To connect the ever-increasing number of in-car electrical devices, plastic optical ﬁber (POF) is used. The beneﬁts of POFnetworks are: a high operation bandwidth, increased transmission security, low weight, immunity to electromagnetic interference, and ease of handling and installation. Diﬀerent protocols are employed or even still in development. In 1998, an international consortium of car manufacturers and suppliers set up an open standard for infotainment networks, the Media Oriented System Transport (MOST). This bus protocol allows 24.8 Mbit/s communication between for instance the radio, the CD/DVD player, the navigation system, a Bluetooth interface, telephones, games consoles and a voice-recognition system inside a car. But not only navigation and entertainment functions can exploit POF. In 1996, BMW gathered some partners and started the development of ByteFlight. This is a protocol that supports 10 Mbit/s communication between the rapidly growing number of sensors, actuators and electronic control units within cars. Unlike MOST, which employs real-time data transfer, ByteFlight is a deterministic system with fault-tolerant behavior and an information latency of 250 µs. BMW’s Series 7 models implement ByteFlight for control of the car’s air-bag systems, while MOST is employed for the vehicle’s information and entertainment systems. Besides MOST and ByteFlight, new protocols are under development. FlexRay is the standard that will be used in the next-generation drive-bywire systems, where mechanical and hydraulic controls are replaced by ﬁber or electrical controls. It is obvious that total reliability is imperative. IDB-1394 is the automotive version of IEEE-1394 (also known as FireWire). It will enable high-speed transfer of digital information at data rates up to 400 Mbit/s. It is a multimedia system like MOST, whereas ByteFlight and FlexRay are more security-focused. All currently in-car optical data bus systems use basically the same components: poly-methyl methacrylate (PMMA) optical ﬁbers, red (650 nm) emitting LEDs and large area silicon photoreceivers. However, this PMMA POF has one key limitation: it can only be used at temperatures below 85◦ C, while many car manufacturers want ﬁber that is speciﬁed at temperatures of 125◦C. A ﬁber that is capable of working at these high temperatures is polymerclad silica ﬁber (PCS). Another attractive feature of PCS is that it supports wavelengths at 850 nm, so that low-cost vertical-cavity surface-emitting lasers (VCSELs) can be used as transmitters. The major advantage of a laser over a LED is an increase of the power budget in the whole system. PCS ﬁbers not only have a low attenuation at 850 nm, but also at 650 nm and thus remain compatible with the standard POF transceivers.

6

1 Introduction

High-Speed Optical Interconnects If Moore’s Law [Moo65] holds true and the processing speed continues to double every 18 months, it is almost certain that a PC built in 2015 will require some form of internal optical data-bus to wire up its diﬀerent chip-sets. Over the next decade, the bandwidth of interconnects inside a computer is expected to increase by an order of magnitude, from 1 GHz to 10 GHz. Ultimately, the chip will be able to work at much higher data rates than todays’ interconnections can handle. An obvious solution would be to use optical interconnections to alleviate the electrical limitations. The major advantage of this approach is that an optical link supports much higher data rates than its electrical counterpart, and continues to do so for far greater distances. History will repeat itself, as the switch has been made in long-haul communication systems (Section 1.1) more than 20 years ago for the same reason. Experts believe that optics could be playing a role in board-to-board links in as little as 2 years. It will take at least 7 years before optical interconnects will be employed for chip-to-chip communication [Sav02, Gra04]. Whether optical interconnects will ever connect the subsystems within a single chip, is under heavy discussion. Blue Laser-Diode and Next-Generation DVD The demand for blue laser diodes, made from gallium nitride (GaN) and invented by Shuji Nakamura in 1995, is being driven by next-generation optical storage systems. The use of blue rather than infrared or red lasers provides a dramatic increase in storage capacity. Together with increases in the numerical aperture of the focusing optics, blue-wavelength storage systems operating at 405 nm can provide 3 to 5 times more storage capacity per layer than the current DVD systems that operate at 650 nm. Two diﬀerent standards have been developed independently: the highdeﬁnition DVD (HD-DVD) standard proposed by Toshiba, and Sony’s BluRay Disc. Blu-Ray Discs have a capacity of 25 GB per layer. Despite a lower capacity of 15 GB per disc layer, one of the advantages of the HD-DVD format is its compatibility with existing DVD production methods. In 2006, the ﬁrst DVD movies were released, both in HD-DVD and in Blu-Ray Disc. Big Hollywood studios like Warner Brothers and Paramount Pictures are supporting both formats, which is a clear sign that both standards will co-exist for a while. Another important consumer-market is the computer gaming market. R 3 in NovemSony Computer Entertainment Inc. launched the Playstation ber 2006, incorporating the Blu-Ray technology. During the same period the Xbox 360 external HD-DVD drive was introduced by Microsoft, that other entertainment giant.

1.3 Silicon Opto-Electronics

7

1.3 Silicon Opto-Electronics According to the Communications Technology Roadmap, silicon microphotonics seeks to build optical devices on the platform that has enabled Moore’s Law: single-crystal silicon [MIT05]. Beyond this, deﬁnitions diverge. At one extreme, hybrid integration on silicon involves the incorporation of non-siliconbased devices manufactured oﬀ-chip with CMOS devices. At the other extreme, CMOS monolithically integrated silicon photonics achieves a complete set of microphotonic devices using processes available in existing CMOS foundries. Between these extremes, intermediate solutions span the spectrum. As also mentioned in [MIT05], silicon microphotonics will likely need to achieve a high degree of monolithic integration with only a small degree of hybrid integration (like laser sources) in order to oﬀer low cost and increased functionality. But why would the existing electrical interconnects be replaced by optical interconnects, and moreover, why would this be done in silicon? The Communications Technology Roadmap [MIT05] identiﬁes the high-level drivers for silicon photonics integration. A ﬁrst important driver is the intrinsic bandwidth-distance product limitation of electrical interconnects. Electronic communication links are impeded by fundamental physical loss mechanisms, like dielectric losses and skin eﬀect losses. As industries are moving to ever higher bandwidths, they are also approaching the theoretical limit predicted by Shannon’s Law. When Shannon’s limit is reached in any given marketplace, there are two options. The ﬁrst option is to hold on to the electrical interconnects, and increase bandwidth by utilizing parallel channels, changing to lower loss interconnect materials or using repeaters. However, every solution raises the cost considerably. Therefore, the second option might be considered: a complete change to an alternative technology platform that does not suﬀer from the same physical limitations. In Section 1.1, the successstory of long-haul optical communication systems has been presented, where the changeover has been made more than 25 years ago. Fig 1.1 shows that also other industries have switched to photonics when the critical bandwidthdistance product (marked in grey) has been reached. Metro area networks (MAN) changed to optical communication over 10 years ago, storage area networks (SAN) switched over 5 years ago. Future candidates are serial computer busses, backplane interconnects and digital visual interface (DVI) for computer displays. The roadmap [MIT05] recognizes that another important driver is needed to justify the nontrivial reapplication of the silicon manufacturing infrastructure for optical interconnects: a volume driver. After all, modern silicon fabs are expensive. Table 1.2 shows that attractive silicon wafer volumes may come from bandwidth increases at the edge of the network. Volumes are far less attractive away from the edge, where the network is already primarily optical today. Higher bandwidth demands at the edge of the network (serial computer busses, backplane interconnects, etc.) will increase pressure for optical

8

1 Introduction Photonic Domain

1 THz

100 GHz Storage Area Net− works

10 GHz Serial Comp. Bus

1 GHz

100 MHz

Metro Area Free Net− Space works Com.

Long Haul Net− works

DVI

Back− plane

10 MHz

1 MHz

Electrical Domain 0.1 m

1m

10 m

100 m

1 km

10 km 100 km

Fig. 1.1. Bandwidth-distance market map [MIT05]. Table 1.2. Network bandwidth requirements and market volume [MIT05]. WAN MAN

LAN

Current BW 1 THz 100 GHz 10 GHz Future BW 1 THz 100 GHz 100 GHz 106 107 Interconnects 105 Wafers/week 2 20 200

Processor 1 GHz 1 THz 109 20000

solutions. That pressure is supported with volume potentials capable of sustaining an industry of silicon fab facilities. Furthermore, Fig. 1.1 shows that these interconnects need bandwidths in the order of 10 GHz. So if silicon opto-electronic solutions want to support these data rates, only todays’ latest silicon technologies will be suitable to enable fully integrated products. The presented research work ﬁts in this quest for integrated optoelectronics, and follows the extreme side of deep-submicron CMOS silicon photonics. After all, the key market driver for silicon microphotonics adoption is a signiﬁcant reduction of cost. Only a lower cost will drive the transition from electronic to photonic interconnects. As was the case for VLSI, monolithic integration will be essential to reduce the cost. Furthermore, for this integration, the technology with the lowest cost must be chosen, which is a standard CMOS technology, widespread used in digital applications. And yes, it will be diﬃcult to reach the same optical performance in CMOS as in dedicated compound -and expensive!- semiconductor technologies.

1.4 Outline of the Work

9

However, silicon solutions are on their way, for detectors and receivers (as presented in this work), modulators and switches. Furthermore, despite the fact that silicon has an indirect bandgap and an over-long spontaneous recombination lifetime, researchers are ﬁnding innovative techniques to ‘light up’ silicon lasers [CP06, Pan05, Cof05]. Moreover, applications will emerge where medium performance can be tolerated, but where low cost and high volumes are of prime importance. These are exactly the strong points of standard CMOS.

1.4 Outline of the Work The presented work aims for the integration of photodiodes together with broadband ampliﬁers in a mainstream CMOS process. It is a contribution in the research for a truly integrated single-chip opto-electrical receiver. Chapter 2 starts with the optical receiver fundamentals. Two receivers will be discussed at the system level: a transceiver for optical communication systems and a pickup unit for optical storage systems. The properties of continuous mode non-return-to-zero pseudorandom binary data will be summarized and the eye diagram will be introduced. Three phenomena will be distinguished that degrade the data quality and introduce errors: noise, bandwidth limitations and jitter. The next three chapters will be dedicated to the three ﬁrst building blocks of an opto-electrical receiver: the photodiode, the transimpedance ampliﬁer, and the post-ampliﬁer. Chapter 3 will treat the implementation of a photodiode in standard CMOS. First, some basic concepts like absorption coeﬃcient, responsivity and intrinsic speed performance of the diode will be deﬁned. Also an explicit motivation for the use of CMOS will be given. To illustrate the feasibility of integrated silicon photodetectors, some publications found in open literature will be discussed. To gain in-depth understanding of the photodetection mechanisms, a one-dimensional model based on semiconductor physics will be worked out. However, this model has its shortcomings that will be redressed by the two-dimensional model. This model will be used to compare the responsivity and speed performance of diﬀerent photodiode topologies, like the classical n-well diode, the p+ n-well diode with guard and the differential diode. Furthermore, the consequences of applying light with shorter wavelengths will be investigated. Finally, the eﬀect of shrinking linewidths in emerging CMOS technologies on the photodiode performance will be studied. The theoretical analysis of the transimpedance ampliﬁer (TIA) will be presented in Chapter 4. After the deﬁnition of the performance requirements, the TIA with shunt-shunt feedback will be studied. High level design equations will be derived for gain, bandwidth, stability and noise performance. The transimpedance-bandwidth product will be proposed as a ﬁgure of merit. In a literature overview, two types of implementations will be recognized: the

10

1 Introduction

TIA with common-source input stage and the TIA with regulated cascode input stage. Finally, the design of three CMOS TIAs will be discussed in detail at the transistor level. The two ﬁrst designs will be based on a single-stage inverter ampliﬁer. The main purpose of these TIAs will be the comparison of diﬀerent photodiode topologies in a 0.18 µm technology as well as in a 90 nm technology. The third TIA will be optimized for the diﬀerential photodiode at its input. It will include a two-stage diﬀerential voltage ampliﬁer and cross-coupled feedback. A bandwidth of 4.3 GHz and a transimpedance gain of 73 dBΩ will result in a simulated transimpedance-bandwidth product of 19 THzΩ. Chapter 5 will cover the design of the post-ampliﬁer, or more precisely the limiting ampliﬁer (LA). Just like for the TIA, the LA performance requirements will be deﬁned and a literature summary will be given. In a ﬁrst design phase, the optimal number of gain stages to achieve maximal gain-bandwidth product will be calculated. Next, two broadband gain stages will be presented and analyzed: the Cherry-Hooper gain stage and the capacitive source degenerated gain stage. Furthermore, a basic oﬀset compensation scheme will be described. The chapter will conclude with transistor-level simulations of two 0.18 µm CMOS LAs. The ﬁrst LA will comprise four identical Cherry-Hooper stages. The second LA will be an improved design, including oﬀset compensation. A gain of 38 dB and a bandwidth of 5 GHz will result in a simulated gain-bandwidth product of almost 400 GHz. Finally, theory will be put into practice in Chapter 6, where the measurement results of four opto-electrical circuits will be discussed. Much attention will be paid to the practical measurement set-up. The ﬁrst chip will contain diﬀerent 0.18 µm photodiode topologies, from which the diﬀerential photodiode will turn out to be the most promising one and will reach bitrates up to 500 Mbit/s with low BER. The second chip will compare the performance of three 90 nm photodiodes. The most successful topology on this chip will be the p+ n-well diode with guard that also will achieve a bitrate of 500 Mbit/s. Compared to the 0.18 µm diﬀerential diode, the same input power will lead to a higher BER. Next, the measurements of the 0.18 µm broadband LA will be discussed. Eye diagrams up to 3.5 Gbit/s will demonstrate the implemented broadband techniques. The ﬁnal chip will synthesize all previous work together with high-speed improvements, to constitute a monolithic 0.18 µm CMOS optical receiver. Photodiode, transimpedance ampliﬁer and limiting ampliﬁer will be integrated on the same die, together with additional circuits like an analog equalizer and a high-speed output buﬀer. Electrical measurements of the LA up to 6 Gbit/s will be shown, while the complete receiver will be proven to be fully functional at bitrates higher than 1 Gbit/s. These results are quite comparable with present state-of-the-art in 0.18 µm CMOS. However, the main bottleneck remains the integration of the photodiode with TIA, while achieving a high sensitivity and a high overall bandwidth. The integration of photodetector and circuit undoubtedly has several advantages, but also poses severe challenges to the analog designer. The main speed obstacle

1.4 Outline of the Work

11

is the photodiode, which will be shown to have an intrinsic bandwidth of 10 MHz. This intrinsic bandwidth will be enhanced by using the diﬀerential photodiode topology combined with an analog equalizer, but then another limit will be reached: jitter. This jitter is due to the nature of the photodiode signals, and can only be eliminated by the design of an improved TIA with an enhanced common-mode suppression. Chapter 7 will conclude with the main contributions and achievements of the presented work, and some suggestions for future research.

2 Optical Receiver Fundamentals

2.1 Introduction This chapter describes the background necessary for the analysis and design of opto-electronic interface circuits. In Section 2.2, the optical receiver is discussed at the system level, presenting two case-studies: a transceiver for optical communication systems and a pickup unit for optical storage systems. Section 2.3 reviews the properties of random binary data and considers methods of generating pseudo-random data. Also the eye diagram, a way to visualize the quality of random data eﬃciently, is introduced. In Section 2.4, it is analyzed how noise in the receiver causes bit errors. This leads to an expression for the bit error rate and the deﬁnition of receiver sensitivity. The eﬀect of bandwidth limitation on random data is discussed in Section 2.5, and the term intersymbol interference is introduced. Finally, diﬀerent types of jitter are explained in Section 2.6.

2.2 The Optical Receiver Front-End This section describes two systems where optical signals must be converted into electrical signals: a transceiver used in optical communication systems and a pickup unit needed in optical storage systems. Both systems have three building blocks in common: a photodiode, a transimpedance ampliﬁer and a post-ampliﬁer. These three blocks are commonly referred to as the receiver front-end. Design of the photodiode, transimpedance ampliﬁer and post-ampliﬁer in a CMOS technology are the main topics of this work and will be discussed in greater detail in Chapter 3, Chapter 4 and Chapter 5 respectively. 2.2.1 A Transceiver for Optical Communication Systems Fig. 2.1 shows the block diagram of a typical optical receiver and transmitter [S¨ ac05]. The optical signal from the ﬁber is received by a photodiode, 13

14

2 Optical Receiver Fundamentals TIA CDR

PD

Driver

DMUX data

n

clock

clock/n

MUX n

LD

Digital Logic

PA

select clock

clock/n

Transceiver CMU

Fig. 2.1. Block diagram of an optical receiver (top) and transmitter (bottom).

which produces a small output current proportional to the optical signal. This current is converted to a voltage by a transimpedance ampliﬁer (TIA). The voltage signal is further ampliﬁed by a post-ampliﬁer (PA), which can either be a limiting ampliﬁer (LA) or an automatic gain control ampliﬁer (AGC ampliﬁer). The resulting signal, which is now several 100 mV strong, is fed into a clock and data recovery circuit (CDR). This unit extracts the clock signal and generates high quality data from the original signal. In high-speed receivers, a demultiplexer (DMUX) converts the fast serial data stream into n parallel, lower-speed data streams that can be processed conveniently by the digital logic block. Sometimes the DMUX task is part of the CDR design, and an explicit DMUX is not needed. The digital logic block descrambles or decodes the bits, performs error checks, extracts the payload data from the framing information, etc. On the transmitter side, the same process happens in reverse order. The parallel data from the digital logic block are merged into a single high-speed data stream using a multiplexer (MUX). To control the select lines of the MUX, a bitrate clock must be synthesized from the parallel data clock. This task is performed by a clock multiplication unit (CMU). Finally, a laser driver or modulator driver drives the corresponding opto-electronic device. The laser driver modulates the current of a laser diode (LD). The modulator driver modulates the voltage across a modulator, which in turn modulates the light intensity from a continuous wave laser. Some laser/modulator drivers also perform data retiming and thus require a clock signal from the CMU.

2.2 The Optical Receiver Front-End

15

Fig. 2.2. A Gbit/s small form-factor pluggable transceiver mounted on an evaluation board.

A module containing a photodiode, TIA, PA, laser driver and laser diode (all the blocks shown inside the dashed box of Fig. 2.1) is called a transceiver. Sometimes also quantization circuits are included in the receiver part. In Fig. 2.2, a so-called small form-factor transceiver is shown, plugged into its evaluation board. The transmitter part is used as high-speed optical source for the measurements discussed in Chapter 6. 2.2.2 A Pickup Unit for Optical Storage Systems Data on an optical disc is physically contained in pits which are precisely arranged on a spiral track. A pickup unit is used to recover this data. It moves across the surface of the rotating disc and must focus, track and read that data track. A three-beam optical pickup is shown in Fig. 2.3 [Poh00]. The light beam, generated by the laser diode (LD), passes through a diﬀraction grating (DG). This is a screen with slits spaced only a few laser wavelengths apart. As the beam passes through the grating, it diﬀracts at diﬀerent angles. When the resulting collection is again focused, it appears as a bright center beam with successively less intense beams on either side. In a three-beam pickup design, the center beam is used for reading data and focusing, and two secondary beams, the ﬁrst order beams, are used for tracking. The polarization beam splitter (PBS) directs the laser light to the disc surface, and bends the reﬂecting light to the photodiode. For the light approaching the PBS, it acts as a transparent window, but for the reﬂected light with rotated plane of polarization, it acts as a prism redirecting the beam. The PBS is followed by a collimator lens, which takes the divergent

16

2 Optical Receiver Fundamentals disc

Objective lens

QWP Collimator lens

Mirror LD

DG

PBS Cylindrical lens

PD E

A

B

C

D

F

Fig. 2.3. General three-beam optical pickup organization.

light rays and makes them parallel. The light then passes through a quarterwave plate (QWP), which rotates the plane of polarization of the incident and reﬂected laser light. As a result, the reﬂected light is polarized in a plane at a right angle relative to that of the incoming light, allowing the PBS to properly deﬂect the reﬂected light. Finally, the light passes through the objective lens, with a numerical aperture (NA) dependent on the minimal pit size. The smaller this size, the higher the NA, and the smaller the wavelength of the laser beam. This trend complicates the realization of the optical system, but there is one big advantage: a smaller pit size also results in a higher disc storage capacity. Table 2.1 compares these ﬁgures for three generations of optical disc storage: CD (infra-red light), DVD (red light) and HD-DVD and Blu-Ray Disc (both blue light). The objective lens is attached to a two-axis actuator and servo system for up/down focusing of motion and lateral tracking motion. When a light spot strikes a land interval between two pits, the light is almost totally reﬂected. When it strikes a pit, destructive interference occurs and a lower light intensity is returned. A change in intensity is interpreted

2.3 Binary Data Formats

17

Table 2.1. Optical Disc Storage Systems. CD λ NA track pitch min. pit size Storage capacity per layer

780 nm 0.45 1.6 µm 0.83 µm 650 MB

DVD HD-DVD Blu-Ray Disc 650 nm 405 nm 0.65 0.65 0.74 µm 0.4 µm 0.4 µm 0.204 µm 4.7 GB 15 GB

405 nm 0.85 0.32 µm 0.14 µm 25 GB

as a one, while an unchanged intensity is interpreted as a zero. The varying intensity light returns through the objective lens, the QWP, the collimator lens, and strikes the surface of the PBS. The light is deﬂected and passes through a cylindrical lens that focuses the light on the photodiode. As can be seen in Fig. 2.3, the photodiode consists of several segments: four central segments A to D and two satellite segments E and F. The central segments detect the main light beam, so are used for focus control and for data readout. The satellite segments detect the side beams and supply signals for tracking control. The current signal from each diode segment is ampliﬁed separately by a transimpedance ampliﬁer and post-ampliﬁer channel. The channels from the signal diodes usually have a higher bandwidth than the more sensitive satellite channels. Finally, the information from the six channels is combined to retrieve the necessary information (e.g. (A+B+C+D) is the wanted data signal, (A+C)-(B+D) is the focus signal and (F-E) is the tracking signal).

2.3 Binary Data Formats This section describes the binary data used in optical communication systems. It is important to understand the terms described further down, because they deﬁne the physical data which is applied at the input of the implemented circuits in Chapter 6. The most commonly used modulation format in optical communication is the non-return-to-zero (NRZ) format, shown in Fig. 2.4. This format is a form of on-oﬀ keying: the signal is on to transmit a one bit and is oﬀ to transmit a zero bit. When the signal is on, it stays on for the entire bit period Tb . The inverse of the bit period is the bitrate Rb . For example, when transmitting the periodic bit pattern ‘010101...’ at a bitrate of 2 Gbit/s in NRZ format, a 1 GHz square wave with 50 % duty cycle is produced. The bit period of each one or zero equal 0.5 ns. In high-speed, long-haul transmission systems, the return-to-zero (RZ) format, also shown in Fig. 2.4, is generally preferred. In this format, the pulses, which represent the one bits, occupy only a fraction (e.g. 50 %) of the bit

18

2 Optical Receiver Fundamentals 0

0

1

0

1

0

1

1

0

1

0

1

NRZ

RZ time Tb

Fig. 2.4. NRZ versus RZ data.

period. Compared with the NRZ signal, the RZ signal requires less signal to noise ratio for reliable detection. On the other hand, the bandwidth needed is larger because of its shorter pulses. The remainder of this text will only deal with NRZ data. To provide data at the input of the receiver with some desirable properties, line coding is applied in the digital domain. First, a DC balanced bit stream, which contains the same number of zeros and ones on average, is wanted. A DC balanced data stream is the same as an average mark density (number of one bits divided by all bits) of 50 %. Such a data stream has the property that its average value (the DC component) is always centered halfway between the zero and one levels. This property often permits the use of ac coupling between circuit blocks. Second, it is desirable to keep the number of successive zeros and ones, or the run length, to a small value. This reduces the low-frequent content of the transmitted signal, and limits the associated baseline wander (explained in Section 2.5.2) when ac coupling is used. In practice, line coding is implemented as either scrambling (SONET, SDH), block coding (Gigabit Ethernet) or a combination of the two (10Gigabit Ethernet): • Scrambling. A pseudorandom bit sequence (prbs) is generated with a feedback shift register, and xor’ed with the data bit stream (see Fig. 2.5). The shift register length is determined by the pattern title, so a 2n − 1 prbs pattern would be generated using a shift register n bits long. This pattern contains every possible combination of n bits, except one. Scrambling provides DC balance without adding overhead bits to the bit stream, thus preserving the bitrate. The average mark density is closer to 50 % as the pattern length increases. On the other hand, the maximum run length is also determined by the length of the shift register: a 231 − 1 prbs pattern contains 31 consecutive ones or zeros. • Block coding. A group of bits is replaced by another, slightly larger group of bits, such that the average mark density becomes 50 % and DC balance is established. For example, in the 8B10B code, 8-bit groups are replaced with 10-bit patterns using a look-up table. The 8B10B code increases the

2.3 Binary Data Formats

1

2

3

n−1

Clock

19

Data out

n

Data in

Fig. 2.5. An n-bit shift register for the generation of a 2n − 1 prbs pattern.

1 0 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 0 1 0 1 continuous mode time 1 0 0 1

1 0 1 1 burst mode time

Fig. 2.6. Continuous mode versus burst mode data.

bitrate by 25 %. However, the maximum run length is strictly limited to ﬁve zeros or ones in a row. With the development of passive optical networks (PON) like ﬁber-to-thehome (FTTH), a new type of transmission mode is introduced: burst mode. In traditional, continuous mode transmission, an uninterrupted stream of bits is transmitted, as shown in Fig. 2.6. The transmitted signal usually is DC balanced, using one of the line codes described above. As a result, ac coupled circuits normally can be used. In burst mode transmission, data bits are transmitted in short bursts, while the transmitter remains silent (laser oﬀ) in between bursts (see Fig. 2.6). Also, the amplitude of the received signal bursts may vary as they originate from diﬀerent sources. The DC component of a burst mode data varies with time, depending on the burst activity. If the activity is high, it may be close to the average of the zero and one levels. If the activity is low, the DC value drifts arbitrarily close to the zero level. So burst mode signals are not DC balanced, which means that ac coupling cannot be used as it would lead to excessive baseline wander (see Section 2.5.2). The receiver front-ends described in this work are designed for continuous mode transmission. To study the eﬀects of circuit and/or system non-idealities on random data, the eye diagram is often used. Such a diagram folds all of the bits into a short interval, for example two bits wide. The total waveform is ﬁrst cut into two-bit segments. Next, all these segments are superimposed, displaying

20

2 Optical Receiver Fundamentals 0

0

0/1

1

1

1/0

0

1

0/1

1

0

1/0

Fig. 2.7. Schematic representation of the construction of an eye diagram.

an accumulation of distorted edges and levels, as can be seen in Fig. 2.7. An important advantage of the eye diagram over the total linear waveform is that all possible bit transitions can be displayed in a compact representation. In Chapter 6, eye diagrams will be used frequently to intuitively judge the quality of the measured signal.

2.4 Bit Error Rate and Sensitivity A ﬁrst phenomenon which degrades the opening of the eye diagram is noise. The noise of the receiver is caused by the detector noise and the ampliﬁer noise. Mostly, the noise of the TIA, is dominant. The conditions for minimum TIA input noise will be discussed in Section 4.3.3. This section describes how the inﬂuence of noise can be measured by introducing the bit error rate and sensitivity of the receiver. 2.4.1 Bit Error Rate The voltage at the output of the TIA or PA can be considered as a superposition of the wanted signal voltage x(t) and the unwanted noise voltage n(t). Occasionally, the instantaneous noise voltage n(t) may become so large that it corrupts the received signal x(t), leading to a decision error or bit error. The bit error rate (BER) is deﬁned as the probability that a zero is misinterpreted as a one or that a one is misinterpreted as a zero. An expression for the BER can be derived [Cou97, Raz03, S¨ac05], based on following assumptions: • The receiver consisting of photodiode, TIA and PA is linear. Even if the PA is implemented as a limiting ampliﬁer, which becomes non-linear for large signals, this model is appropriate, because the noise levels and the signal levels at the sensitivity limit are so small. • The wanted signal is a NRZ data pattern where the logical one is represented by V1 and the logical zero by V0 . The peak-to-peak value vpp thus

2.4 Bit Error Rate and Sensitivity

21

equals V1 − V0 . The probability Px (x = V1 ) of receiving a one equals the probability of receiving a zero Px (x = V0 ), so: Px (x = V1 ) = Px (x = V0 ) = 1/2.

(2.1)

• The probability density function for the noise Pn is stationary and has a Gaussian distribution with zero mean: 2

−n 1 Pn = √ e 2σn2 . 2πσn

(2.2)

The standard deviation σn is equal to the rms value of the noise voltage vn,rms . • The threshold voltage VT H of the decision circuit is located at the midpoint between the zero and one levels, so: VT H =

V1 + V0 . 2

(2.3)

The decision circuit determines whether a bit is a zero or a one by comparing the signal at the output of the PA (or TIA) with this threshold voltage. As demonstrated in [Cou97], a decision level in the middle of the zero and one levels minimizes the BER. For the measurements described in Chapter 6, the decision circuit is included in the measurement equipment. The relationship between signal, noise and BER is graphically represented in Fig. 2.8. The noisy signal is sampled by the decision circuit at the center of each bit period (vertical dashed lines), producing the statistical distributions shown on the right-hand side. Both distributions are Gaussian, and have a standard deviation equal to σn . The BER corresponds to the shaded areas under the Gaussian tails and is given by: v pp BER = Q . (2.4) 2σn Q(x) is called the ‘Q function’ and deﬁned as: ∞ 1 −u2 √ e 2 du. Q(x) = 2π x

(2.5)

The Q function is not available in closed form, but for x > 3, it can be approximated with high accuracy by: −x2 1 Q(x) ≈ √ e 2 . x 2π

(2.6)

Note that the argument of the Q function in (2.4) is given by one half of the peak value of the signal divided by the rms value of the noise. This ratio can be considered as a signal to noise ratio (SNR). Some commonly used values are: Q(6) ≈ 10−9 , Q(7) ≈ 10−12 .

22

2 Optical Receiver Fundamentals 0

1

0

0

1

1

0

σn 00 11 11 00 00 11 00 11 00 11 00 11 00 11 00 11 00 11 00 11

vpp

VTH

Fig. 2.8. Relationship between signal, noise and BER.

2.4.2 Sensitivity The sensitivity of a receiver is the minimum signal needed at the input to achieve a certain BER. It reﬂects to what level the transmitted signal can become attenuated and still be detected reliable by the receiver. Sensitivity can be deﬁned in the electrical as well as in the optical domain. The electrical sensitivity, isens pp , is deﬁned as the minimum peak-to-peak signal current at the input of the receiver, necessary to achieve a speciﬁed BER. Common BER values to deﬁne sensitivity are 10−9 and 10−12 . The argument of the Q function (2.4) can be referred to the input using the midband values of the small-signal transfer functions of the TIA (ZT IA,0 ) and the PA (AP A,0 ). These transfer functions will be calculated for some circuit implementations in Chapter 4 and Chapter 5, respectively. The equivalent input-referred rms noise in,rms is deﬁned as: σn = vn,rms = ZT IA,0 · AP A,0 · in,rms .

(2.7)

Notice that this noise current is not a signal which is physically present at the input, but only a mathematical deﬁnition to deﬁne the sensitivity of the receiver. For mid-band frequencies, the current swing isens at the input of the pp TIA causes the output voltage vpp at the PA: vpp = ZT IA,0 · AP A,0 · isens pp .

(2.8)

Combining (2.4), (2.7) and (2.8) results in the expression for BER in function of the electrical sensitivity: BER = Q

isens pp . 2in,rms

(2.9)

sens The optical receiver sensitivity, Pav , is deﬁned as the minimum optical power, averaged over time, necessary to achieve a speciﬁed BER. For a DC balanced signal, it holds that:

2.5 Intersymbol Interference

23

R V in

V out C

1 0 1 0 1 0 1 (a) 1 0 0 1 1 0 1 (b)

vpp

V TH time

time t1

t2

Fig. 2.9. Eﬀect of low-pass ﬁltering on binary data: (a) periodic data, (b) random data. sens Pav =

isens pp , 2R

(2.10)

where R is the responsivity of the photodiode (3.4) and expressed in A/W. This leads to a third expression for the BER: P sens · R . (2.11) BER = Q av in,rms In the measurements of Chapter 6, the optical sensitivity for a certain BER will be used, rather than the electrical sensitivity. After all, optical signals are applied at the input and can be measured directly.

2.5 Intersymbol Interference Not only noise reduces the quality of the eye diagram, also bandwidth limitations have impact on the eye opening. This type of degradation is known as intersymbol interference (ISI). The eﬀect of both low-pass ﬁltering and high-pass ﬁltering are discussed. 2.5.1 Low-Pass Filtering In order to study the eﬀect of the ﬁnite bandwidth of circuits, the signal quality at the output of a ﬁrst order low-pass ﬁlter is examined. As shown in Fig. 2.9, the ﬁlter simply consists of resistor R and capacitor C. The 3-dB bandwidth f3dB of this ﬁlter is given by: f3dB =

1 . 2πRC

(2.12)

When a periodic square wave is applied at the input, the output signal consists of rising and falling exponential waves, with time constant τ = RC (see

24

2 Optical Receiver Fundamentals C

V in

V out R

1 0 1 1 1 1

0 1

time

time

Fig. 2.10. Eﬀect of high-pass ﬁltering on random binary data.

Fig. 2.9(a)). This means that for time t = τ , the output has risen or fallen to 63 % of its ﬁnal value. If the bit period Tb is large enough compared to τ , the exponential tail has vanished and the peak-to-peak value of the binary data is large enough to be detected without any errors. Considering random data in Fig. 2.9(b), the output does not attain the upper or lower levels which deﬁne vpp at the end of every bit period. For two consecutive ones or zeros, it does, but for a single one followed by a single zero (or vice versa), it doesn’t. This is undesirable because the output voltage levels corresponding to ones and zeros vary with time, making it diﬃcult to deﬁne a decision threshold VT H . For example, the levels at t = t1 and t = t2 are more susceptible to noise and can be misinterpreted by the detector. This phenomenon is called intersymbol interference (ISI), because the exponential response during one bit period corrupts the signal levels produced for subsequent bits. The narrower the bandwidth, the longer the exponential tails and the greater the ISI. 2.5.2 High-Pass Filtering To understand the eﬀect of high-pass ﬁltering, suppose a random binary sequence is applied to the ﬁrst-order high-pass ﬁlter with capacitor C and resistor R (see Fig. 2.10). The low-frequency cut-oﬀ, or the frequency where the gain is 3 dB lower than its high-frequent value, is given by: fLF =

1 . 2πRC

(2.13)

Such a low-frequency cut-oﬀ appears in the receiver response for instance when ac coupling is used between TIA and PA, or when oﬀset compensation is used in the PA (Chapter 5). Fig. 2.10 shows that each transition at the input immediately appears at the output, but when receiving a long string of ones or zeros, the output voltage drifts. As a result, the bits after each long run suﬀer from a large (temporary) DC shift, making it diﬃcult to set a decision threshold VT H . This phenomenon can also be viewed as ISI, because each bit level depends on the preceding pattern.

2.6 Jitter

25

V

TH

jitter

Fig. 2.11. Jitter deﬁnition.

The above eﬀect is called baseline wander or DC wander, because the ‘instantaneous’ DC value of the output waveform changes randomly. To minimize baseline wander, τ = RC must be suﬃciently larger than the longest possible data run of ones or zeros.

2.6 Jitter So far we have discussed how noise and ISI aﬀect the signal levels at the decision circuit. However, the decision process not only involves the signal voltage, but also the signal timing. The deviations of the threshold voltage VT H crossings from their ideal position in time is called jitter (Fig. 2.11). Jitter may inﬂuence the optimal sampling instant of the decision circuit. Just like noise and ISI, too much jitter closes the eye opening and introduces bit errors. The total jitter may be composed of deterministic jitter and random jitter. Examples of deterministic jitter are data-dependent jitter and duty-cycle distortion jitter. Data-dependent jitter is produced when the signal edge moves slightly in time, depending on the values of the surrounding bits. It can be caused for example by an insuﬃcient bandwidth or by baseline wander due to an insuﬃcient low-frequency cut-oﬀ. Duty-cycle distortion jitter occurs if the rising and falling edges do not cross each other at the decision threshold voltage. Random jitter is, in contrast to deterministic jitter, not related to any data pattern or any deterministic cause. It is produced, for example, by noise on edges with a ﬁnite slew rate. It can also be caused by carrier mobility variations due to instantaneous temperature ﬂuctuations. Besides the data jitter described above, also clock jitter exists. This jitter is important in the clock and data recovery circuit where the decision process takes place. For instance, if the sampling instant of the decision circuit varies with time, an increase in BER might occur. In the frequency domain, the jitter counterpart is called phase noise. It is extremely important for the design of oscillators and clock and data recovery circuits, but falls beyond the scope of this text.

26

2 Optical Receiver Fundamentals

2.7 Conclusions Some basic concepts and deﬁnitions, needed in the remainder of this text, have been introduced in this chapter. First, two systems have been studied which both contain an optical receiver front-end: a transceiver for optical communication systems and a pickup unit for optical storage systems. Next, the data which will be applied at the input of the receiver circuits has been presented: continuous mode non-return-to-zero pseudorandom binary data. An eﬃcient representation of this data is the eye diagram, and it will be used frequently to study the data quality at the output of the receiver. Finally, three phenomena have been studied which reduce the eye opening and introduce bit errors: the receiver noise, the limited receiver bandwidth and jitter.

3 Standard CMOS Photodiodes

3.1 Introduction This chapter discusses the ﬁrst component of the optical receiver, the photodetector. It deviates from subsequent chapters, as no integrated circuits are discussed and no transistors are shown in the ﬁgures. However, the optical and electrical properties of the photodiode impose important requirements on the design of the next blocks of the receiver chain. Therefore, this chapter is completely dedicated to the light detection mechanisms involved using reversely biased silicon pn-junctions. Section 3.2 starts with the basic deﬁnition of a photon, to end with the most relevant characteristics of the photodiode: responsivity and speed. Motivation is provided for the integration of photodetectors in a non-optimized, mainstream CMOS technology. By means of illustration, an overview of some interesting monolithic opto-electrical receivers is given in Section 3.3. Not only CMOS implementations are considered, but also BiCMOS and SOI implementations. To gain in-depth understanding of the photodetection mechanisms, a onedimensional model, based on semiconductor physics equations, is worked out in Section 3.4. Because this model has its limitations, a two-dimensional model is developed with MEDICI. This model is discussed in Section 3.5. The speed and responsivity performance of several diode topologies are compared, and the inﬂuence of technology scaling and illumination with diﬀerent light wavelengths are studied. The results and trends predicted by these simulations correspond well with other photodiode modeling papers which can be found in open literature: [Pal01, Gen01, Rad03, Rad05].

3.2 Basic Concepts In an optical communication system, the light generated by a laser diode is converted to an electrical signal at the receive end by means of a photodiode. 27

28

3 Standard CMOS Photodiodes

Various properties of photodiodes aﬀect the sensitivity and speed of the receiver front end. This section discusses some basic deﬁnitions to characterize the performance of a photodiode. Also the pro’s and con’s of using a mainstream CMOS technology are discussed. 3.2.1 Principles of Light Detection As shown by Albert Einstein in 1905, light behaves not always as a continuous wave. Under certain circumstances, light acts as a stream of discontinuous, individual particles. These particles, or “light quanta,” (later named photons) each carry a “quantum,” or ﬁxed amount of energy, given by: Ep = hν =

hc . λ

(3.1)

h = 6.63 · 10−34 J · s is Planck’s constant, ν is the frequency of the electromagnetic wave, c = 3 · 108 m/s is the speed of light in vacuum and λ is the corresponding wavelength. The higher the frequency or the smaller the wavelength, the more energy per photon or the less photons for a given total energy. Light detection can be performed by a reversely biased junction, as shown in Fig. 3.1. When the junction is illuminated with light, incident photons with an energy larger than or equal to the bandgap energy Eg of the semiconductor material generate electron-hole pairs. Fundamental absorption of photons with an energy smaller than Eg is not possible. Consequently, the semiconductor is transparent for light with wavelengths longer than: λc =

hc . Eg

(3.2)

For silicon, Eg = 1.12 eV, which means that only light with wavelengths shorter than 1.1 µm can be detected with silicon photodiodes. The electrons and holes generated in the depletion region (or space charge region SCR) are separated by a large electric ﬁeld and drift in opposite directions. The transport mechanism of the carriers generated outside the depletion region is diﬀusion, which is a slow transport mechanism compared to drift. These carriers may recombine before they are detected, or they diﬀuse inward and are collected across the junction, adding a slow tail to the photodiode’s time response. To prevent the recombination loss of generated carriers and to have a fast diode response, eﬃcient photodiode operation demands a large depletion region. The absorption coeﬃcient α determines how deep light of a particular wavelength penetrates into a speciﬁc material. The intensity of light penetrating into a medium decreases exponentially with depth, as given by LambertBeer’s Law: (3.3) Φ(x) = Φ0 · e−αx .

3.2 Basic Concepts

29

VR

I dio

Popt

P

Depletion region

N

Electric field hν hν Conduction band Bandgap Energy E g

hν

electron diffusion

Valence band hole diffusion

drift

Fig. 3.1. Principle of operation of a semiconductor photodiode.

Absorption coefficient α (μm−1)

1000 100 10 In0.53Ga0.47As 1

Si InP

Ge

0.1 0.01 GaAs 0.001

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Wavelength λ (μ m) Fig. 3.2. Absorption coeﬃcient versus wavelength for various semiconductor materials [Zim04].

30

3 Standard CMOS Photodiodes

Φ(x) is the light ﬂux ( photons/(cm2 · s)) at depth x in the material while Φ0 is the initial ﬂux. The absorption coeﬃcient versus wavelength is depicted in Fig. 3.2 for the most important semiconductor materials [Zim04]. In0.53 Ga0.47 As and Ge cover the widest range of wavelengths, including 1.3 µm and 1.54 µm, which are used for long distance optical ﬁber communication. The absorption coeﬃcients of GaAs and InP are high in the visible spectrum (≈ 400 nm–700 nm). Silicon detectors are appropriate for the visible and infrared spectral range. The absorption coeﬃcient of silicon is however one or two orders of magnitude smaller than that of the direct semiconductors InP and GaAs. The inverse of the absorption coeﬃcient, 1/α, is called the penetration depth, and will be used frequently in this text. The diode current Idio , consisting of photo-generated carriers, is linearly proportional to the optical power Popt : Idio = R · Popt .

(3.4)

R is called the responsivity of the diode. Typical values for commercially available infrared photodiodes are 0.5 A/W to 0.8 A/W. In an ideal photodiode, every photon entering the device generates an electron-hole pair. In reality, however, some photons are reﬂected from the surface or absorbed by the material to produce heat. The quantum eﬃciency of the photodiode is the ratio of the number of electrons generated, and the number of photons applied: Idio /q Popt /(hc/λ) hc =R qλ 1.24 = R. λ

η=

(3.5) (3.6) (3.7)

Besides responsivity, speed is an important parameter of the photodiode. As already mentioned before, the slowly diﬀusing carriers add a tail to the diode’s time response. For example, the diﬀusion time of a hole through 10 µm of silicon is 40 ns [Mil79]. So for high-speed operation, the depletion region has to be suﬃcient wide, preferably wider than the penetration depth 1/α. Due to the high electrical ﬁeld over the junction, the carriers attain their saturation velocity, which is approximately 107 cm/s in silicon [Mil79]. Consequently, the transit time can be very short, for instance 0.1 ns for a 10 µm wide junction. Having a depletion region that encloses the absorption region is also the requirement for high quantum eﬃciency, as diﬀusing carriers might recombine before detection. In Sections 3.4 and 3.5, the intrinsic speed performance of CMOS photodiodes will be characterized by the 90 % rise time of the step response, the (intrinsic) frequency characteristic and the (intrinsic) bandwidth. Finally, another important characteristic of the photodiode is its parasitic junction capacitance. As will be explained in Section 4.3.1, its value combined

3.2 Basic Concepts

31

with the input impedance of the receiver, determines an RC constant which limits the bandwidth in most circuits. This bandwidth is often called the extrinsic bandwidth, to distinguish from the intrinsic bandwidth. The junction capacitance is thus of uttermost importance for the transmission speed that is achievable with a photodiode-receiver combination. Its value is dependent on doping concentrations, reverse voltage, and diode area. Note that the latter is mostly one of the only degrees of freedom available in the design of a standard CMOS photodiode, as doping levels and the maximum supply voltage are ﬁxed by the technology. 3.2.2 The Use of Standard CMOS As mentioned in Chapter 1, there exists a wide range of emerging applications where optical receivers are needed. Especially, for these applications, cost aspects are crucial. This is the main motivation for choosing a CMOS technology: in the end, CMOS is cheap. Of course, today’s 65 nm CMOS technologies are expensive. But in a few years, when all digital standard cells are implemented in nm-scale technologies, the high manufacturing cost will be justiﬁed by the large production volumes. Using standard CMOS for light detection has the main disadvantage that the technology is not optimized for optical devices. First, the width of the junctions doesn’t match the penetration depth of light. Second, the reverse voltage available to bias the junctions cannot be higher than the supply voltage. Finally, no postprocessing is allowed, so no anti-reﬂective coatings are used. These limitations result in photodiodes with minor responsivity and speed performance compared to commercially available diodes. To circumvent these diﬃculties and to implement cheap but high-performing optical receivers are the main objectives of this work. Besides the low cost aspect, the integration of photodiodes in standard CMOS has even more beneﬁts. The integration of the photodiode on the same die as the receiver causes a reduction of the external components count, resulting in a low-cost system with enhanced yield. Furthermore, an integrated photodiode reduces the total input capacitance by eliminating the parasitics due to the diode’s package, the PCB wiring, the IC-package and some bondpads. As will become clear in Section 4.3.1, this gives the opportunity to increase the transimpedance-bandwidth product for free. A side eﬀect is that the diode capacitance increases as technology scales down, but this will be treated in more detail in Section 3.5.5. Finally, a major advantage of an integrated photodiode is the reduction of noise coupling into the input node thanks to the removal of bondwires, the package pins and the PCB paths connected to this node, which otherwise pick up spurious signals from the environment. Fig. 3.3 shows the junctions which are available in a standard CMOS technology. The ﬁrst one is an n+ p-substrate junction, the second one is an n-well p-substrate junction and the last one is a p+ n-well junction. They all

32

3 Standard CMOS Photodiodes

(a) p−substrate

(b) p +region

(c) n−well

n +region

Fig. 3.3. Junctions capable of light detection in standard CMOS: (a) n+ p-substrate junction, (b) n-well p-substrate junction, (c) p+ n-well junction.

can be used to detect visible or infrared light, but they all have a diﬀerent performance. The most important diﬀerence between the ﬁrst two junctions is the width of the depletion region. Due to the much lower doping levels of the nwell compared to the n+ region, the width of the n-well p-substrate depletion region is larger, resulting in a more eﬃcient photodetection. Consequently, the analysis of the next sections will mainly focus on the n-well p-substrate diode. The last structure, the p+ n-well junction, is also less eﬃcient with respect to capturing light, but has some special features in combination with the n-well p-substrate junction. This will also be discussed in more detail in the following sections.

3.3 Overview of Published Integrated Photodiodes Before starting with a detailed analysis of CMOS photodiodes and their performance, this section discusses integrated silicon photodetectors which can be found in open literature. It is not the intention to give an exhaustive overview, but to highlight some breakthroughs of the recent past. The emphasis lies on the use of mainstream silicon technologies. Not only CMOS is considered, also photodetectors implemented in BiCMOS and SOI technologies are discussed. 3.3.1 BiCMOS Implementations BiCMOS processes combine both bipolar transistors and nMOS as well as pMOS transistors. It is possible to exploit the advantages of both type of transistors. CMOS transistors allow low-power, high-density digital integrated circuits. Bipolar digital circuits implemented with ECL (Emitter Coupled Logic) gates have a larger driver capability and can operate with small logic swings and high noise immunity. Comparing the analog capabilities, better device matching, lower oﬀset voltage and enhanced bandwidth can be obtained with bipolar subcircuits. On the other hand, the zero input bias current of CMOS transistors can also be used advantageously in analog BiCMOS implementations. These beneﬁts are attained at the expense of a more diﬃcult technology

3.3 Overview of Published Integrated Photodiodes

33

development and at the expense of more complex chip-manufacturing tasks, leading to longer chip-fabrication time and higher costs [Zim04]. The bipolar npn transistor is formed by an n+ -emitter, a p-type base, and an n-type collector. To minimize collector series resistance, the collector not only consists of an epitaxial n− -layer, but also has a buried n+ -subcollector and n+ -collector plugs. Without any process modiﬁcations, the buried n+ subcollector can serve as the cathode, the n-collector epitaxial layer can serve as the intrinsic region of a PIN diode, and the p-base implant can serve as the anode. The main advantage of a PIN diode is its lowly doped intrinsic region where a high electric ﬁeld is present if it is depleted. In this region, carrier transport is drift, which results in fast and eﬃcient photodetectors. This is especially true if the intrinsic region corresponds to the light penetration depth. For 800 nm wavelengths, a thickness of at least 10 µm is necessary due to the low optical absorption coeﬃcient (Fig. 3.2). Such a large intrinsic layer thickness requires a severe reduction of the epitaxial layer concentration to obtain a spreading of the electric ﬁeld over the entire intrinsic zone. However, this would destroy the bipolar transistor performance. Therefore, process modiﬁcations are needed to optimize the performance of both the integrated photodiode (which needs a thick, lowly doped intrinsic layer) and the bipolar transistor (which needs a thin, higher doped n-collector). In [Stu05], a dedicated 0.5 µm BiCMOS technology that combines highspeed transistors with an integrated PIN photodiode is described. The available devices are a single-poly npn bipolar transistor with ft =20 GHz, a vertical pnp bipolar transistor with ft =1 GHz, standard 0.5 µm CMOS, and passive devices like capacitors, resistors and laser fuses. The integrated PIN photodiode is optimized concerning speed and sensitivity for all three light wavelengths used for optical data storage, like CD (780 nm), DVD (660 nm) and Blu-ray (405 nm). The measured photodiode sensitivity is 0.35 A/W, 0.4 A/W, and 0.25 A/W for 780 nm, 660 nm and 405 nm wavelengths respectively. The 3-dB small signal intrinsic bandwidth of the photodiode is above 1 GHz. This technology has been used to implement an optical receiver IC for CD, DVD, and Blue-Laser optical data storage applications [Stu04], [Stu05]. It includes a new architecture of high-speed and low-noise variable gain transimpedance ampliﬁers with current preampliﬁer input. The ampliﬁer transimpedance gain is programmable over a range of 130 Ω to 270 kΩ by a serial interface. The ampliﬁer small-signal bandwidth is 260 MHz for the highest gain, which gives a transimpedance-bandwidth product of 70 THzΩ. A redesign of this chip with some new developments is presented in [Sei05]. The obtained improvements are a reduction of the power consumption, the die area, the oﬀset voltage, an increase of the sensitivity, 1.5 V output swing and a drive capability of a 10 pF/10 kΩ output load. An overall transimpedance of 465 kΩ leads, with the responsivity of the photodiode, to a sensitivity of 186 mV/µW for 660 nm light with a 3-dB bandwidth of 145 MHz. Compared

34

3 Standard CMOS Photodiodes

with the previous IC, sensitivity is improved by a factor of 1.8, while bandwidth is decreased by the same factor. The same technology has been used to implement OEIC’s for high-speed optical interconnects between or within electronic systems. The wavelength region of interest now is 600 nm to 850 nm. In [Swo03] an optical receiver with a maximum possible data rate of 1.8 Gbit/s is presented. This is achieved by using a bias voltage of 17 V (instead of the supply voltage of 5 V) at the cathode of the photodiode, to increase the electric ﬁeld strength in the intrinsic region and enhance the diode speed performance. Using 670 nm light, a sensitivity of −21.9 dBm for a BER of 10−9 is measured. The next step is to integrate a voltage-up-converter (VUC) with the OEIC, which generates onchip the higher cathode voltage from the 5 V supply voltage. This is presented in [Swo04], where the VUC produces a voltage of 11 V and improves the bandwidth of the OEIC from 1.5 GHz to 2.4 GHz. For a data rate of 3 Gbit/s and a BER of 10−9 , a sensitivity of −24.3 dBm at a wavelength of 660 nm is obtained. In [Swo05], measurement results at 4 Gbit/s and 5 Gbit/s are added. Finally, [Swo06] presents a 11 Gbit/s integrated receiver for 850 nm wavelength. A reverse photodiode voltage of 17 V extends the diode 3dBfrequency to 2.2 GHz. To enable high-speed data reception above 4 Gbit/s, the frequency response of the diode must be corrected with the help of an analog equalizer, ﬁrst introduced by [Rad04]. At 11 Gbit/s a minimum optical power of −8.9 dBm is needed for a BER of 10−9 . 3.3.2 SOI Implementations Silicon on Insulator (SOI), developed by IBM, is a chip-making technology that builds transistors on a very thin layer of silicon, improving chip performance and reducing power consumption. A thin, insulating layer, such as silicon oxide or glass, is placed between the thin layer of silicon and the silicon substrate. This process helps to reduce the amount of electrical charge that a transistor has to move during a switching operation, thus making it faster and allowing it to switch using less energy. SOI chips can be as much as 15 percent faster and use 20 percent less power than today’s bulk CMOS-based chips. SOI chips tend to cost more than their standard silicon counterparts, so SOI has been primarily used for high-end applications [Fre]. Photodetectors implemented in a thin SOI layer might be attractive, because light with a long wavelength (and long penetration depth) generates carriers in the silicon substrate wafer, which is isolated from the device SOI layer by the buried oxide. Therefore, SOI avoids the slow diﬀusion current known from photodiodes in bulk silicon. In [Csu02], the optical receiver is manufactured on 2 µm thick SOI substrates with a high resistivity. The thickness of the SOI is chosen to achieve a compromise between quantum eﬃciency and bandwidth for the photodiodes. The receiver is implemented in a 130 nm CMOS process ﬂow. The n- and p-type regions of the lateral interdigitated

3.3 Overview of Published Integrated Photodiodes

35

PIN diode is formed by standard nMOS and pMOS drain and source implantations. A sensitivity of −10.9 dBm is obtained for a bitrate of 5 Gbit/s at a BER of 10−9 . In [Yan03], the same photodiode is wire-bonded to a 10 Gbit/s SiGe TIA that was fabricated in a 0.18 µm BiCMOS technology. By applying a higher reverse voltage, the photodiode operates in avalanche gain mode. Owing to impact ionization, photocurrent gain is observed. For a bias voltage > 20 V, the 3-dB optical bandwidth is greater than 8 GHz. The complete receiver achieves a sensitivity of −6.9 dBm (BER < 10−9 ) at 10 Gbit/s. 3.3.3 CMOS Implementations As will become clear in the next sections, the main limitations of standard submicron CMOS photodiodes are caused by the diﬀusing substrate carriers. Many attempts exist in literature to overcome this problem. In [Ing04], the relative part of the drift current to the total current is optimized by using the side-wall capacitance of the n-well p-substrate junction. Although the corresponding depletion region is thin too, its depth perpendicular to the surface is larger compared to the depth of the bottom-plate capacitance. The major disadvantage of this approach is the limited photodiode’s responsivity due to the overhead required to connect the diode. Measurements on the side-wall photodiode have been done with a 650 nm LED as light source. With the network analyzer, a ﬂat response is obtained up to approximately 40 MHz. This pole would be caused by the LED rather than by the integrated photodiode. A ﬁrst breakthrough in the integration of high-speed submicron CMOS photoreceivers was presented by [Woo98]. The 0.35 µm receiver integrates a photodiode, preampliﬁer, digital logic, and oﬀ-chip driver. The n-well region in which the detector was made measures 16.54 µm x 16.54 µm, and is surrounded by a grounded p+ guard ring. Inside the n-well an interdigitated network of p-diﬀusion ﬁngers forms the active terminal of the detector. The photodetector responsivity, using 850 nm light, ranges from 0.01 A/W to 0.04 A/W near junction breakdown (10 V). Under these bias conditions and at a bitrate of 1 Gbit/s, a BER of 10−9 is obtained with an average optical input power of −6.3 dBm. Another way to circumvent the problem of diﬀusing substrate carriers is proposed by [Roo00]. The spatially modulated light (SML) detector consists of a row of rectangular p− -n junctions (ﬁngers) alternatingly covered and noncovered with a light blocking metal. The masked ﬁngers connected together form the deferred detector. The other ﬁngers connected together form the immediate detector. When a light pulse is incident on the detector, carriers are generated below the immediate zone and not below the masked deferred zone. The photo-generated carriers are spatially modulated. The immediate detector “immediately” detects the shallow-generated carriers. The bulk-generated carriers diﬀuse in all directions and most of them will ﬁnally reach a detector

36

3 Standard CMOS Photodiodes

junction (as well in the deferred as in the immediate zone). If the response of the deferred detector is subtracted from the response of the immediate detector, a fast response is achieved as the inﬂuence of the slow diﬀusing carriers is cancelled. This SML-detector is integrated with a low-oﬀset receiver in a 0.6 µm standard CMOS technology [Roo00]. The sensitivity at a BER of 10−9 is −18 dBm (λ = 860 nm) for 250 Mbit/s. A later realization in a 0.25 µm CMOS technology [Roo01] achieves, at 700 Mbit/s, a BER of 10−12 for the same input power. The receiver with SML-detector proposed by [Jut05] is integrated in an unmodiﬁed 0.18 µm CMOS technology. At 2 Gbit/s and using 850 nm light, the sensitivity equals −8 dBm at a BER of 10−9 . A totally diﬀerent approach to enhance the speed of integrated CMOS detectors is introduced by [Rad04, Rad05]. Not the n-well photodiode topology is changed, but a clever circuit solution is proposed. Following device simulations, the overall intrinsic photodiode frequency response shows a slow decay starting in the low MHz range. The roll-oﬀ in the overall photocurrent response is only about 5 dB/decade for frequencies between roughly 10 MHz and the lower GHz range. So the signals from the photodiode are low bandwidth (MHz range) but still relatively strong at very high frequencies (GHz range). Therefore an analog equalizer is introduced that compensates (in gain and phase) for the diode photocurrent roll-oﬀ in the range from 1 MHz to 1 GHz. Because no photogenerated carriers are drained away or subtracted from each other, the author claims there is no sensitivity or responsivity penalty. This results in a measured 3 Gbit/s data rate with a low BER (< 10−9 ) at −19 dBm 850 nm optical input power. 3.3.4 Conclusions The main focus in this literature overview lies on the performance of the photodiodes and the overall speed/sensitivity performance of the optical receivers that they are part of. One important conclusion is that, to the present day, there exists no uniform way to measure and report the characteristics of the opto-electrical receiver. For instance, [Stu05] and [Sei05] express the sensitivity in mV/µW (which is simply the product of responsivity and transimpedance gain). On the other hand, the sensitivity in for example [Swo04] is the minimum average optical input power needed to achieve a BER of 10−9 . Also the use of diﬀerent wavelengths makes a fair comparison more diﬃcult (the BiCMOS implementations mostly use 660 nm light, while the CMOS implementations almost all apply 850 nm light). Finally the speed of the receiver is expressed in diﬀerent ways: some authors (like [Stu05], [Sei05]) emphasize the bandwidth of the amplifying circuit, while others focus on the bitrate of the received data (like [Roo00], [Rad05]). However, the general trends which can be concluded from this overview are: • The photodiodes implemented in BiCMOS achieve the best performance. The main reason is that the technology used in for example [Stu05, Swo06]

3.4 One-Dimensional Model

37

is enhanced to ameliorate both responsivity and intrinsic speed of the photodiode. A higher performance is achieved at the expense of a more expensive technology. • SOI does not oﬀer large advantages over CMOS: comparing [Csu02] with [Rad05], the ﬁrst achieves higher bitrates (5 Gbit/s versus 3 Gbit/s), but the latter has a better sensitivity (−19 dBm versus −10.9 dBm, both for a BER of 10−9 ). • The main challenge in standard CMOS remains the realization of a photodiode with a high intrinsic speed, combined with a large responsivity. This trade-oﬀ will be worked out in more detail in the following sections. Several approaches, like [Roo00] and [Rad05] have increased the intrinsic speed so that the speed performance becomes comparable to the performance of the BiCMOS detectors. However, the sensitivity of the latter ones remains unbeatable.

3.4 One-Dimensional Model In this section, a one-dimensional model is developed to analyze the light detection performance of standard CMOS junctions. It is based on the basic equations of semiconductor physics [Ove98]. The model helps to gain insight in the basic working principles, but should also be treated with care, as it is only a one-dimensional model. To interpret the analytical results, the parameters of a 90 nm CMOS technology are used. The principles and major conclusions of this model have been published in [Her03]. 3.4.1 N-Well P-Substrate Junction The current of this photodetector is composed of a drift current originating from the carriers generated inside the depletion region (or space charge region SCR), an electron diﬀusion current from electrons generated in the psubstrate, and a hole diﬀusion current from holes generated in the n-well. To characterize the magnitude and speed of the total current step response, the concentration of the minority carriers in n-well and p-substrate has to be calculated ﬁrst. Fig. 3.4 shows a schematic representation of the one-dimensional model. Diﬀusion of Holes in the N-Well The continuity equation of the holes in the n-well, which is a non-homogeneous partial diﬀerential equation, is given by: ∂ 2 p(x, t) p(x, t) − p0 ∂p(x, t) = Dp − + αΦe−αx . ∂t ∂x2 τp

(3.8)

38

3 Standard CMOS Photodiodes

0

11111111111111111111111111111111 00000000000000000000000000000000 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111 00000000000000000000000000000000 11111111111111111111111111111111

p−substrate

n−well

000 111 000 111

SCR

L nw L scr

Lb x

Fig. 3.4. One-dimensional model of the n-well p-substrate junction.

Following list gives an explanation of all variables: x depth t time p hole concentration p0 initial hole concentration Dp hole diﬀusion constant τp hole minority carrier lifetime α absorption coeﬃcient of light in Si Φ photon ﬂux According to (3.8), the carrier concentration within an elementary volume can only change as a function of time if there is a diﬀerence between the incoming and outgoing carrier ﬂuxes (due to diﬀusion currents, ﬁrst term), or a net recombination (second term) or generation (third term). The boundary and initial conditions are: p(x = 0, t) = p0 ,

(3.9)

p(x = Lnw , t) = 0, p(x, t = 0) = p0 .

(3.10) (3.11)

The boundary equation (3.9) states that at the surface (x = 0), the concentration equals the initial concentration p0 . This assumption has been made for simplicity, as in reality impurities at the oxide-silicon interface create interface states and a netto recombination. At the edge of the space charge region (x = Lnw ) carriers are swept away, so the minority carrier concentration equals zero (3.10). When no light penetrates the junction, condition (3.11) deﬁnes that the hole concentration equals the initial concentration p0 .

3.4 One-Dimensional Model

39

To solve the mathematical problem of (3.8), the non-homogeneous partial diﬀerential equation is split up in a homogeneous partial diﬀerential equation and a non-homogeneous ordinary diﬀerential equation, which are mathematically easier to handle. The solution p(x, t) is separated in a time-independent part v(x) and a time-dependent part w(x, t): p(x, t) = v(x) + w(x, t).

(3.12)

The solution of (3.8), which describes the variation of the holes in the n-well with respect to depth and time, is thus given by: αΦ e−αx Dp α2 − 1/τp x −x + Ap exp + Bp exp Dp τp Dp τp

∞ kπx k 2 π 2 Dp 1 + Cp (k) sin + exp − t . Lnw L2nw τp

p(x, t) = p0 −

(3.13)

k=1

Ap , Bp and Cp (k) are constants which can be determined by solving the boundary and initial conditions (3.9)–(3.11). The hole diﬀusion current as a function of time is proportional to the gradient of the minority carrier concentration at the edge of the space charge region: ∂p , (3.14) Jdif f p = −qDp ∂x x=Lnw

where q is the elementary charge and Dp the hole diﬀusion constant. Diﬀusion of Electrons in the P-Substrate The continuity equation of the electrons in the p-substrate is similar to (3.8) and given by: ∂n(x, t) ∂ 2 n(x, t) n(x, t) − n0 = Dn − + αΦe−αx . ∂t ∂x2 τn Following list gives an explanation of all variables: x depth t time n electron concentration n0 initial electron concentration Dn electron diﬀusion constant τn electron minority carrier lifetime

(3.15)

40

3 Standard CMOS Photodiodes

α absorption coeﬃcient of light in Si Φ photon ﬂux The boundary and initial conditions now are: n(x = Lscr , t) = 0, n(x = Lb , t) = n0 , n(x, t = 0) = n0 .

(3.16) (3.17) (3.18)

The ﬁrst boundary condition (3.16) declares that the concentration equals zero at the edge of the space charge region (x = Lscr ). At distance x = Lb , the photo-generated minority carriers which are diﬀusing have negligible eﬀect on the equilibrium minority carrier concentration n0 , which results in condition (3.17). Lb depends both on lifetime of the diﬀusion carriers and the penetration depth of light in the material. At the initial state, there is no light input, so the concentration equals the initial concentration n0 (3.18). The solution of this non-homogeneous partial diﬀerential equation (3.15) is found in an analogue way as for the holes, and the solution is given by: αΦ e−αx Dn − 1/τn

x −x + Bn exp √ + An exp √ Dn τn Dn τn

∞ kπ(x − Lscr ) k 2 π 2 Dn 1 + Cn (k) sin + t . exp − (Lb − Lscr ) (Lb − Lscr )2 τn

n(x, t) = n0 −

α2

k=1

(3.19) An , Bn and Cn (k) are constants which again can be determined by solving the boundary and initial conditions (3.16)–(3.18). Like (3.14), the electron diﬀusion current as a function of time is proportional to the gradient of the minority carrier concentration at the edge of the space charge region: ∂n , (3.20) Jdif f n = qDn ∂x x=Lscr

where q is the elementary charge and Dn the electron diﬀusion constant. Drift in the Space Charge Region The drift current in the space charge region is given by: x=Lscr G(x)dx, Jdrif t = q

x=Lnw x=Lscr

=q x=Lnw

αΦe−αx dx.

(3.21)

3.4 One-Dimensional Model

41

G(x) is the generation term due to penetrating light with ﬂux Φ and absorption coeﬃcient α, which also appears in continuity equations (3.8) and (3.15). Lscr − Lnw is the width of the space charge region and determined by: 2Si NA + ND (Vbi − VR ). (3.22) Lscr − Lnw = q NA ND NA is the concentration of acceptors in the p-substrate, ND is the concentration of donors in the n-well, Si is the permittivity of Si, q is the elementary charge, Vbi is the technology-dependent built-in voltage and VR is the reverse voltage of the junction. The space charge region becomes wider when doping concentrations are lowered or when the reverse voltage VR is increased. Graphical Representation of the Results After derivation of the mathematical equations, it is time to visualize and interpret the results. The diode, with the cross section of Fig. 3.4, has an area of 100 µm x 100 µm and is illuminated with a step input of 1 µW. The minority carrier lifetimes in the n-well and in the p-substrate are assumed to be 1 µs. To investigate the inﬂuence of wavelength, two diﬀerent wavelengths are applied: 600 nm and 800 nm. This directly inﬂuences the absorption coeﬃcient α as well as the initial light ﬂux Φ0 . For red 600 nm light, α equals 5000 cm−1 and Φ0 corresponds to 3 · 1016 photons/(cm2 · s). When infrared 800 nm light is applied, α drops to 1000 cm−1 while Φ0 becomes 4 · 1016 photons/(cm2 · s). The reverse voltage over the junction is only 0.5 V, which is half the available power supply in a 90 nm CMOS technology. Fig. 3.5 shows the concentration of minority carriers in the n-well and p-substrate versus time and depth into the substrate. The inﬂuence of wavelength is clear: a longer wavelength results in a larger penetration depth 1/α, and more carriers which are generated in the substrate. In Fig. 3.5(a), the maximum of the electron concentration is 2.1 · 1011 cm−3 at 7 µm, while in Fig. 3.5(b) the maximum equals 1.7 · 1012 cm−3 at 17 µm. The maximum of the hole concentration lies in both cases at one half of the n-well depth (Lnw /2) and equals 1.6 · 1011 cm−3 respectively 5.7 · 1010 cm−3 . The large discrepancy between electron and hole maxima explains why the hole concentration is hardly visible in Fig. 3.5(b). The slowly varying gradient of the electron concentration in the substrate determines the gradually rising diﬀusing current Jdif f n . As depicted in Fig. 3.6, this current is the major part of the total current, but as expected the eﬀect is more pronounced when longer wavelengths are used. According to this model, the responsivity of the diode is 0.32 A/W and the rise time is 19 ns when red light is applied. For infrared light, the responsivity equals 0.44 A/W while the rise time is as high as 260 ns. The relative contribution of drift current Jdrif t and hole diﬀusion current Jdif f p is much smaller in the latter case. So the larger the wavelength, the larger the absorption depth in

42

3 Standard CMOS Photodiodes

11

x 10 −3

concentration [cm ]

2.5 2 1.5 1 0.5 0 200 4 100 time [ns]

2 0 0

−3

x 10

x [cm]

(a)

12

x 10 −3

concentration [cm ]

2 1.5 1 0.5

0 1000 6

500

4

time [ns]

0 0

−3

x 10

2 x [cm]

(b) Fig. 3.5. Minority carrier concentration in n-well p-substrate junction: (a) λ=600 nm, (b) λ=800 nm.

silicon, the more carriers are generated in the substrate and the slower the time response. But the smaller the wavelength, the higher the energy per photon (3.1). For the same input power, less photons penetrate the substrate and the responsivity is lower. Gigabit operation is not yet possible with this kind of rise times, but the more accurate two-dimensional model will show that things are not as bad as they seem at this stage.

3.4 One-Dimensional Model

43

3.5

2

current density [mA/cm ]

3 2.5

maximal current density =3.2mA/cm2

2 1.5 J

diffn

1

Jdiffp

0.5

Jdrift t

0 0

0.9

Jtot

=19 ns

50

100 time [ns]

150

200

(a) 4.5

2

current density [mA/cm ]

4

2

maximal current density =4.4mA/cm

3.5 3 2.5 2 1.5

Jdiffn

1

Jdiffp t

0.9

0.5 0 0

200

Jdrift

=260 ns

Jtot 400 600 time [ns]

800

1000

(b) Fig. 3.6. Current densities in n-well p-substrate junction: (a) λ=600 nm, (b) λ=800 nm.

3.4.2 P+ N-Well Junction with Guard The previous simulations have shown that the diﬀusing substrate carriers are a problem for high-speed operation, certainly when infrared light is used. One way to overcome this problem is to consider the p+ n-well junction together with the n-well p-substrate junction. If the former is used to detect the signal, the substrate contacts can act as guard to draw away the slowly diﬀusing

44

3 Standard CMOS Photodiodes 1111111111111111111111111111111 0000000000000000000000000000000 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111

1111111111111111111111111111111 0000000000000000000000000000000 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111 0000000000000000000000000000000 1111111111111111111111111111111

p−substrate

p +region

111 SCR 000 n−well000 111

Fig. 3.7. One-dimensional model of the p

+

0 L sd L scr1 L nw L scr2

x

n-well junction with guard.

signals carriers in the substrate. The resulting diode response will be smaller, but also a lot faster. This idea has also been implemented successfully in [Woo98]. The performance of this diode has been analyzed using the same physical equations ((3.8) to (3.22)), but now there are three diﬀusion currents and two drift currents. All parameters are the same as in the previous model, and the minority carrier lifetime in the p+ region is assumed to be 0.1 ns due to the very high doping concentration in this region. A cross section of this structure is depicted in Fig. 3.7. Electrons are diﬀusing in the p+ region and in the psubstrate, and they give rise to the currents Jdif f n1 and Jdif f n2 . The diﬀusing holes in the n-well generate the current Jdif f p . Carriers generated in the very shallow space charge region between the p+ region and the n-well will form the small drift current Jdrif t1 . Jdrif t2 , which is somewhat larger, stems from the light generated carriers in the wider space charge region between n-well and p-substrate. The light wavelength is 600 nm, and the reverse voltage over both junctions is 0.5 V. An important question for this model is: which currents will be picked up by which contacts? In a practical implementation, three electrode contacts are present: one for the p+ region, one for the n-well, and one for the p-substrate. The current at the n-well electrode equals the sum of the currents at the electrodes of the p-type regions. The current at the substrate contact consists of the substrate diﬀusion current Jdif f n2 , drift current Jdrif t2 and one part of the n-well diﬀusion current Jdif f p . Equivalently, the current at the p+ region contact is made up of the p+ region diﬀusion current Jdif f n1 , drift current Jdrif t1 and the other part of the n-well diﬀusion current Jdif f p . In this one dimensional model, we assume an equal probability for the light-generated holes in the n-well to be trapped by either of the space charge regions. So one half of Jdif f p is collected by the substrate contacts, and the other half by the p+ region contacts. This simpliﬁcation is true if the carriers inside the n-well

3.4 One-Dimensional Model

45

11

x 10 −3

concentration [cm ]

2.5 2 1.5 1 0.5 0 200 4 100

2 0 0

time [ns]

−3

x 10

x [cm]

(a) 4

2

current density [mA/cm ]

2

3.5 t =13 ns 0.9

max current density =3.5mA/cm

3 Jdiffn1

2.5 2

max current density

Jdiffp

with guard =0.9mA/cm2

Jdiffn2

1.5 t =1.5 ns 0.9

Jdrift1 Jdrift2

1

Jtot1

0.5

J

tot2

0 0

10

20

30 time [ns]

40

50

60

(b) Fig. 3.8. (a) Minority carrier concentration and (b) current densities in p+ n-well junction with guard, λ=600 nm.

are uniformly distributed. However, in reality, the light ﬂux is determined by Lambert-Beer’s Law (3.3) and the light-generated carriers inside the n-well have a decreasing exponential distribution. The results are depicted in Fig. 3.8. Fig. 3.8(a) shows that the concentration of minority carriers in the substrate is very similar to the simple n-well diode: the maximum lies at 7 µm and equals 2.1 · 1011 cm−3 . The maximum minority concentration in the n-well is 1.1 · 1011 cm−3 , while the maximum

46

3 Standard CMOS Photodiodes

concentration in the p+ region is only 5.6 · 108 cm−3 . This last region is not visible in the plot, as the minority concentration is low and the region is very shallow compared to the other regions. All current densities in this structure are depicted in Fig. 3.8(b). The duration of the step input is 200 ns, but to focus on the most interesting data, only the ﬁrst 60 ns are shown. If the two junctions were placed parallel, the resulting performance is comparable to the performance of the simple n-well p-substrate junction. The responsivity is 0.35 A/W and the rise time equals 13 ns. But if the substrate carriers are eﬀectively removed by the substrate contacts, the rise time is only 1.5 ns. The price to pay is a drop in responsivity, which is now only 0.09 A/W. By applying a one dimensional analysis, this example shows that using the appropriate diode structure can alleviate the problem of the diﬀusing minority carriers in the substrate. Also the trade-oﬀ between sensitivity and speed, which will reappear several times in this work, is demonstrated for the ﬁrst time. However, as junctions are located closer to the surface and the side-wall capacitances become more and more important, a more accurate two-dimensional model is needed. This will be discussed in the next section.

3.5 Two-Dimensional Model A two-dimensional analysis of diﬀerent photodiode topologies is performed with the device simulation program Medici [Syn]. It is a powerful tool that can be used to simulate the behavior of MOS and bipolar transistors, and other semiconductor devices (such as diodes). It models the two-dimensional distributions of potentials and carrier concentrations in a device. A number of physical models are incorporated into the program for accurate simulations, including models for recombination, photogeneration, mobility and lifetime. The optical Device Advanced Application Module is used to model propagation of light inside and outside a device. This section discusses three photodiode structures implemented in a 0.18 µm standard CMOS technology: the classical n-well diode, the p+ n-well diode with guard and the diﬀerential diode. Also the inﬂuence of changing the light wavelength is studied. Finally, the eﬀect of technology downscaling on the photodiode performance is investigated. Most of these results have been presented in [Her03, Her04b, Her06a]. 3.5.1 Classical N-Well Diode Fig. 3.9 shows a schematic representation of the simulated n-well diode. As a multimode ﬁber has a core diameter of 50 µm or 65 µm, the dimensions of the diode are 80x80 µm2 . This could be implemented as one large n-well region, or several smaller parallel n-well regions separated by substrate contacts to minimize substrate resistance. The amount of squares per diode side is given

3.5 Two-Dimensional Model

80 μm, Ns squares

80 μm, Ns squares

anode

cathode

47

anode

p−substrate

n−well

p +region

n +region

Fig. 3.9. Schematic representation of the simulated classical n-well diode, left: topview, right: cross-section.

by Ns , and the inﬂuence on both responsivity and speed is investigated. On top of the structure are ohmic contacts (at anode and at cathode), and the contacts are separated by a 1 µm thick oxide layer. For simplicity, the rest of the dielectric stack is omitted. At the silicon-oxide interface, a surface recombination rate of 0 cm/s is supposed, corresponding to the ideal values of an insulator interface. All doping proﬁles used for simulations are constant proﬁles, except for the n-well. For this region, a retrograde well doping proﬁle is taken into account. This is a proﬁle where the highest dopant concentration is located at a certain distance from the surface, while the concentration towards the Si/SiO2 interface becomes lower. It is needed in modern submicron technologies to improve short channel characteristics and increase surface mobility. Although essential for the performance of short channel transistors, the retrograde well proﬁle also inﬂuences the optical performance of the n-well p-substrate junction. By changing the doping proﬁle in the channel region, an electric ﬁeld is created near the surface, which counteracts the electrical ﬁeld of the space charge region. As a result, the photogenerated carriers are less accelerated, resulting in a slower response. As the retrograde well proﬁle is located near the surface, this eﬀect is more pronounced when light with a short wavelength and small penetration depth is used. So the negative eﬀect of the retrograde proﬁle compared to a constant proﬁle is more dominant for blue light than for infrared light. The simulation results for a 0.18 µm CMOS technology are summarized in Fig. 3.10 and Table 3.1.The maximum supply voltage is 1.8 V, and the reverse voltage over the diode is 1 V. The wavelength of light equals 850 nm. These parameters, as well as the photodiode area, will be the same for the next two simulated diode topologies. As Medici is a two-dimensional tool, not only bottom-plate, but also sidewall junctions are taken into account. This is the main reason why the simulation results of the one-dimensional model and the two-dimensional model

48

3 Standard CMOS Photodiodes

responsivity (A/W)

0.35

Ns=4

0.3

Ns=6

0.25

Ns=8

0.2

Ns=12

0.15

Ns=14

N =10 s

0.1 0.05 0 0

0.5

1 time (μs)

1.5

2

norm. gain (dB)

(a) 0 −20

Ns =4 Ns =6

−40 6

phase (degrees)

10

7

8

10 10 frequency (Hz)

9

10

10

10

Ns =8 Ns =10

180

Ns =12 Ns =14

135 90 6

10

7

8

10 10 frequency (Hz)

9

10

10

10

(b) Fig. 3.10. Classical n-well diode simulation results: (a) responsivity, (b) normalized intrinsic frequency characteristic. Ns corresponds to the number of squares per diode side.

diﬀer slightly in responsivity, but greatly in speed performance. Owing to the extra electric ﬁeld regions of the side-wall junctions, the intrinsic photodiode speed becomes better in the two-dimensional model. The responsivity R varies between 0.33 A/W-0.29 A/W and turns out to be slightly dependent on the amount of squares. The higher Ns , the more useful area is taken by the substrate contacts, the smaller R. The speed performance of the photodiode is characterized by its intrinsic 3-dB bandwidth f3dB . It is mainly determined by the diﬀusing carriers in the substrate and independent of layout topology. The simulated value equals 10 MHz. Leaving technology diﬀerences aside, this value should be compared with the value found in the analytical model: a 90 percent rise time of 260 ns for infrared light corresponds in

3.5 Two-Dimensional Model

80 μm, Ns squares

80 μm, Ns squares

49

cathode cathode guard anode guard

p−substrate

n−well

p +region

n +region

Fig. 3.11. Schematic representation of the simulated p+ n-well diode with guard, left: top-view, right: cross-section.

a classical one-pole system to an intrinsic 3-dB bandwidth of 1.3 MHz. The value of 10 MHz is considered to be more accurate, as the contribution of the side-wall junctions is included. These orders of magnitude correspond to the values reported by other authors (a 3-dB bandwidth of 4 MHz for a 0.25 µm technology [Gen01] and a ‘cut-oﬀ frequency’1 of 1 MHz for a 0.18 µm technology [Rad05]). The low-frequency roll-oﬀ (< 50 Mz) is independent of Ns and equals roughly 5 dB/decade. Note that this value is quite diﬀerent from the slopes found in classical electronic systems, where one or multiple RCconstants determine a slope of 20 dB/decade, 40 dB/decade, etc. The system under study is not determined by some discrete R’s or C’s, but by the distributed eﬀect of carriers in n-well, depletion region and p-substrate. 3.5.2 P+ N-Well Diode with Guard As already discussed in Section 3.4.2, eliminating the substrate carriers from the total signal would make the diode response a lot faster. This idea is implemented in the p+ n-well diode with guard, shown schematically in Fig. 3.11 [Woo98]. The basic diode structure is the same as the one of the classical n-well diode, only now a p+ region is embedded in the n-well region. The amount of n-well regions is again given by Ns . The active junction detecting the signal is now the p+ n-well junction. The substrate contacts act as a guard to remove the substrate carriers. This photodiode is capable of high-speed operation, at the expense of a smaller responsivity. The simulation results regarding responsivity are shown in Fig 3.12(a). On top, for Ns = 4 to Ns = 14, the responsivity is shown if the p+ region and p-substrate were placed parallel. These results are slightly smaller (due to the extra interconnect overhead) compared to the classical n-well diode. The responsivity if the substrate contacts act as a guard, is approximately 1

The cut-oﬀ frequency is deﬁned in [Rad05] as the frequency at which the DC and ac asymptotes of the total photodiode response cross.

50

3 Standard CMOS Photodiodes 0.3

Ns=4 Ns=6

responsivity (A/W)

0.25

Ns=8 0.2

N =10 s

Ns=12

0.15

Ns=14

0.1 0.05 0 0

0.5

1 time (μs)

1.5

2

norm. gain (dB)

(a) 0 −20

Ns =4 Ns =6

−40 6

phase (degrees)

10

7

8

10 10 frequency (Hz)

9

10

10

10

Ns =8 Ns =10

0

Ns =12 Ns =14

−45 −90 6

10

7

8

10 10 frequency (Hz)

9

10

10

10

(b) Fig. 3.12. p+ n-well diode simulation results: (a) responsivity (upper curves: p+ n-well junction and p-substrate n-well junction in parallel, lower curves: p+ n-well junction with p-substrate guard), (b) normalized intrinsic frequency characteristic of the p+ n-well diode with guard. Ns corresponds to the number of squares per diode side.

ten times smaller (0.023 A/W for Ns = 4 ), as shown in the same ﬁgure and summarized in Table 3.1. On the other hand, as depicted in Fig. 3.12(b), the intrinsic 3-dB bandwidth is 100 times larger (1 GHz) and again independent of Ns . The frequency roll-oﬀ is also independent of Ns up to a few GHz. The slope is slightly larger compared to the frequency slope of the classical n-well diode: approximately 8 dB/decade instead of 5 dB/decade. These results diﬀer slightly from the one-dimensional analytical model, where red light instead of infrared light was applied. Probably the assumption that one half of the diﬀusing holes in the n-well is collected by the substrate

3.5 Two-Dimensional Model

51

contacts, and the other half by the p+ region contacts, is not correct when the two-dimensional problem is considered. The side-wall space charge region of the n-well plays a non-negligible roll, because the n-well extents much deeper into the substrate than the p+ region. As a result, the major part of the n-well diﬀusion current is picked up by the side-wall space charge region between n-well and p-substrate. Compared to the one-dimensional model, the responsivity in this model drops (from 0.09 A/W to ≤0.023 A/W). The speed improvement found in the one-dimensional model is only a factor of 10 (Fig. 3.6(a) and Fig. 3.8(b): the rise time drops from 19 ns to 1.5 ns). The two-dimensional model is more realistic, as the fast response of the side-wall junctions is included, although the speed improvement by a factor of 100 might be rather optimistic. 3.5.3 Diﬀerential N-Well Diode Another way to increase the diode bandwidth is to use a diﬀerential nwell diode. It is based on the same physical principles as the SML-detector in [Roo00]. As depicted in Fig. 3.13, the diﬀerential n-well diode consists of an alternating pattern of illuminated and dark junctions. The latter ones are covered with metal to block the light. This diode also features substrate contacts alternating the junctions, again to minimize substrate resistance. When light falls on this diode, carriers are generated below the illuminated junctions and not below the dark junctions. The substrate carriers generated close to an illuminated junction will have a higher probability to reach this junction than to reach one of the neighboring dark junctions. Those generated deep in the substrate will require a long time to reach a junction and have more or less equal probability to reach an illuminated or dark junction. If the response of the dark junctions is subtracted from the response of the illuminated junctions, a fast response is achieved as the inﬂuence of the slowly diﬀusing carriers is cancelled. Medici simulations have been performed using the amount of ﬁngers, Nf , as parameter. Rlight , theresponsivity of the illuminated junctions, is less than one half of the responsivity of the classical n-well diode (see upper curves in Fig. 3.14(a) and Table 3.1). This is because the same total area (80x80 µm2 ) is now taken by two diodes, the illuminated one and the dark one. The DC responsivity of the diﬀerential signal (Rlight − Rdark ) varies between 0.10 A/W and 0.076 A/W. This is approximately one half of the responsivity of the illuminated junctions (see lower curves in Fig. 3.14(a) and Table 3.1), but still more than 2 times larger than the responsivity of the p+ n-well diode with guard. More ﬁngers correspond to more interconnection overhead, and a slightly lower responsivity. The frequency characteristic of the diﬀerential diode is depicted in Fig 3.14(b). Its intrinsic 3-dB bandwidth ranges from 1 GHz to more than 4 GHz, and does depend on the amount of ﬁngers. More ﬁngers per diode means less distance for the diﬀusing carriers to bridge before they get detected, resulting in a faster response. These results are consistent

52

3 Standard CMOS Photodiodes Dark junction

Illuminated junction

111111111111111111111 000000000000000000000 111111111111111111111 000000000000000000000

p+ region

p−substrate

111111111111 000000000000 111111111111 000000000000

n−well

111 blocking metal 000 n+ region000 111

80 μ m

80 μ m, Nf fingers

1111 0000 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111

00000 11111 11111 00000 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111

00000 11111 11111 00000 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111

1111 0000 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111

Fig. 3.13. Schematic representation of the simulated diﬀerential n-well diode, bottom: top-view, top: cross-section.

with the results found in [Gen01]. For the simulated frequencies of interest, there is no region of constant roll-oﬀ . The slope at each f3dB equals 3 dB/decade, and rapidly rises to 10 dB/decade for frequencies above 10 GHz. These results show a trade-oﬀ between bandwidth and responsivity, and depending on the design goals, a proper choice of Nf has to be made. 3.5.4 Inﬂuence of Wavelength Up till now, all photodiode simulations have been carried out for a wavelength of 850 nm. This wavelength corresponds to the wavelength used for short-distance low-cost communication networks with multimode ﬁber. For the measurements described in Chapter 6 this wavelength will also be used. However, as described in Chapter 1, there are other low-cost applications where monolithic CMOS implementations should be considered. First there is the optical data storage, where three wavelengths are standardized: 780 nm (CD), 660 nm (DVD) and 405 nm (Blu-Ray Disc and HD-DVD). Second, not only multimode ﬁbers are used for short-distance communication, but also other kinds of ﬁbers, working at a diﬀerent optimal wavelength, might be of interest. For example, more and more cars are exploiting 650 nm plastic optical ﬁber (POF) for their in-vehicle networks. As there is such a wide variety of applications and standards, the inﬂuence of changing the wavelength is investigated.

3.5 Two-Dimensional Model 0.12

Nf=18 Nf=22

0.1 responsivity (A/W)

53

Nf=26 0.08

N =30 f

Nf=34

0.06 0.04 0.02 0 0

0.5

1 time (μs)

1.5

2

norm. gain (dB)

(a) 0 −10

Nf =18 Nf =22

−20

6

phase (degrees)

10

7

8

10 10 frequency (Hz)

9

10

10

10

Nf =26 Nf =30

180

Nf =34

135 90 6

10

7

8

10 10 frequency (Hz)

9

10

10

10

(b) Fig. 3.14. Diﬀerential n-well diode simulation results: (a) responsivity (upper curves: Rlight , lower curves Rlight − Rdark ), (b) normalized intrinsic frequency characteristic of the diﬀerential diode. Nf corresponds to the number of ﬁngers.

Fig. 3.15 shows the simulation results for the classical n-well diode. Three diﬀerent cases are considered: A. infrared light (850 nm), B. red light (650 nm) and C. blue light (400 nm). The responsivity, depicted in Fig. 3.15(a), shows the wavelength dependence of the energy per photon (3.1). The smaller the wavelength, the higher the energy per photon, the smaller the amount of photons which can generate carriers and consequently the smaller the responsivity. Notice that also the penetration depth in combination with the carrier minority lifetime determine responsivity. If the penetration depth is large (which is true for large wavelengths), a lot of carriers will be generated deep into the substrate, and will recombine before being detected. So although more photons are present for the same amount of energy, less useful electrons will

54

3 Standard CMOS Photodiodes Table 3.1. Simulated photodiode performance. p+ n-well diode with guard

classical n-well diode Ns R (A/W) 4 6 8 10 12 14

0.33 0.325 0.32 0.31 0.30 0.29

f3dB

10 MHz

Ns R (A/W) 4 6 8 10 12 14

0.023 0.021 0.019 0.017 0.015 0.013

f3dB

1 GHz

diﬀerential n-well diode Nf Rlight (A/W) Rlight − Rdark (A/W) f3dB 18 0.10 0.052 1 GHz 22 0.094 0.046 1.5 GHz 26 0.088 0.042 2.2 GHz 30 0.083 0.038 3.1 GHz 34 0.076 0.034 4.4 GHz

be collected due to recombination. This explains why the responsivities of infrared (850 nm) and red (650 nm) light are located close to each other, and can even interchange when small simulation parameters are modiﬁed. The normalized frequency response for the three wavelengths is shown in Fig 3.15(b). The smaller the wavelength, the smaller the penetration depth, the higher the relative contribution of the drift current, and thus the higher the 3-dB bandwidth. This results in a f3dB of 10 MHz for 850 nm light, 50 MHz for 650 nm light, and 75 MHz for 400 nm light. At lower frequencies, the slope is also wavelength dependent. For 850 nm light, the roll-oﬀ equals 5 dB/decade, while the rolloﬀ using smaller wavelengths is lower: 1.5 (dB/decade) for 650 nm light and 1 dB/decade for 400 nm light. At higher frequencies (> 100 MHz) the curves have equal slopes, but are shifted due to the higher bandwidth when shorter wavelengths are used. Around 100 MHz, the slope is steep, showing a roll-oﬀ of 15 dB/decade. Above 1 GHz, the steepness slows down and all curves have a slope of 5 dB/decade. At this frequency, the attenuation is larger than 15 dB for all wavelengths. The simulation results for the wavelength inﬂuence on the diﬀerential diode are depicted in Fig. 3.16. For this diode topology, the responsivity (Rlight − Rdark ) is the largest for 650 nm light, smaller for 400 nm light and the smallest for 850 nm light. Rlight has the same dependence on wavelength as the classical n-well diode described above. On the other hand, the smaller the wavelength, the smaller the penetration depth, the less diﬀusing carriers are generated,

3.5 Two-Dimensional Model

55

0.35 A B C

responsivity (A/W)

0.3 0.25 0.2 0.15 0.1 0.05 0 0

0.5

1 time (μs)

1.5

2

norm. gain (dB)

(a) 0 −20 −40

A B C 6

phase (degrees)

10

7

8

7

8

10 10 frequency (Hz)

9

10

10

10

180 135 90

A B C 6

10

10 10 frequency (Hz)

9

10

10

10

(b) Fig. 3.15. Classical n-well diode and inﬂuence of wavelength (A. infrared light (850 nm), B. red light (650 nm), C. blue light (400 nm)): (a) responsivity, (b) normalized intrinsic frequency characteristic.

so the smaller Rdark . For infrared 850 nm light, Rdark is approximately 50 % of Rlight . For red (650 nm) and blue (400 nm) light, Rdark is only 9 % resp. 2 % of Rlight . This eﬀect is also visible in the frequency characteristic: the speed performance of the 400 nm diﬀerential diode (f3dB = 240 MHz and a slope of 10 dB/decade) is worse than the speed performance of the 650 nm and 850 nm diﬀerential diodes (f3dB = 1 GHz and a slope of 3 dB/decade in both cases). So when no or only a few diﬀusing carriers are present in the substrate, a diﬀerential n-well diode topology is not the solution to enhance the diode speed performance with several orders of magnitude. Using blue light (400 nm), the substrate diﬀusing carriers are not the problem, but speed is limited by the diﬀusing carriers in the n-well itself. Although blue light

56

3 Standard CMOS Photodiodes 0.15

responsivity (A/W)

A B C 0.1

0.05

0 0

0.5

1 time (μs)

1.5

2

norm. gain (dB)

(a) 0 −10 −20

A B C 6

phase (degrees)

10

7

8

7

8

10 10 frequency (Hz)

9

10

10

10

180 135 90

A B C 6

10

10 10 frequency (Hz)

9

10

10

10

(b) Fig. 3.16. Diﬀerential n-well diode and inﬂuence of wavelength (A. infrared light (850 nm), B. red light (650 nm), C. blue light (400 nm)): (a) responsivity, (b) normalized intrinsic frequency characteristic.

with a short penetration depth into silicon is very attractive, further research is needed to optimize the speed performance inside the n-well. The simulations for these two diode topologies show that, when both responsivity and bandwidth are considered, the most optimal wavelength is 650 nm. For the classical n-well diode, the responsivity is comparable when using infrared 850 nm light, while the 3-dB frequency is larger. For the diﬀerential diode, responsivity as well as bandwidth are the best using red light. 3.5.5 Inﬂuence of Technology Scaling As dictated by Moore’s Law (the doubling of the number of transistors on integrated circuits every 18 months [Moo65]), the minimum size of a transistor

3.5 Two-Dimensional Model

57

continually reduces. During the research period of this work, the most widely used CMOS technology for analog design was the 0.18 µm CMOS technology. However, also 0.13 µm and 90 nm technologies were available. As 65 nm digital CMOS technologies are emerging, the inﬂuence of technology scaling on the diode performance should be considered. When technology size decreases, doping concentration levels increase to counteract the eﬀect of scaling on transistor characteristics (VT , leakage currents, etc.). Also, the available power supply drops to keep the electrical ﬁeld within limits. As a result, the width of space charge regions (eg. for the n-well p-substrate junction given by (3.22)) decreases. This will result in a smaller contribution of the drift current (3.21) to the total current. Fig. 3.17 shows the inﬂuence of downscaling on the optical performance of the classical n-well diode and the diﬀerential n-well diode. A 0.18 µm CMOS technology is compared with a 0.13 µm CMOS technology. Both responsivity and 3-dB bandwidth of the diodes become slightly worse when technology scales down. The low-frequency roll-oﬀ of the classical diode is 5 dB/decade for both technologies. The diﬀerential n-well diode does show some technology dependence: the slope is slightly steeper around f3dB for the smaller technology: 5 dB/decade compared to 3 dB/decade. Notice that the simulations for the diﬀerential diode were carried out for a ﬁxed amount of ﬁngers Nf . When minimal sizes are reducing, smaller nwell ﬁngers can be taken, resulting in a faster detector response. The eﬀect of having smaller ﬁngers is actually presented in Fig. 3.14(b), but only for the 0.18 µm technology. Moreover, as technology dimensions shrink, the area overhead needed for n-well and substrate contacts will become less. This will result in less area covered with light-blocking metal, and more eﬃcient area taken by photo-sensitive junctions. So despite all the drawbacks, technology scaling might have some advantages for integrated diﬀerential photodiodes. Finally, Table 3.2 draws attention to another important parameter which modiﬁes as a result of technology changes, namely the junction capacitance. As will become clear in Section 4.3.1, its value is inversely proportional to the bandwidth of the transimpedance ampliﬁer, and thus greatly inﬂuences the speed of the overall receiver. Due to doping concentration modiﬁcations (resulting in smaller depletion widths), the zero bias junction capacitance becomes higher. Especially the increase of the side-wall capacitance is remarkable: more than a factor of ten per unit meter. Table 3.2 also compares the total capacitance of the classical n-well diode and the diﬀerential n-well diode implemented in two diﬀerent technologies and reversely biased at one half of the respectively available power supply (1.8 V versus 1.2 V). For the diﬀerential diode, the capacitance of the illuminated junctions (equal to the capacitance of the dark junctions) should be considered, as the currents of these junctions are ampliﬁed separately. This value is approximately one half of the capacitance of the classical n-well diode, which is consistent with the occupied diode area. A technology change from 0.18 µm CMOS to 0.13 µm CMOS means roughly a 4 times increase of the n-well p-substrate junction

58

3 Standard CMOS Photodiodes 0.35 A B C D

responsivity (A/W)

0.3 0.25 0.2 0.15 0.1 0.05 0 0

0.5

1 time (μs)

1.5

2

norm. gain (dB)

(a) 0 −10 −20

A B C D 6

phase (degrees)

10

7

8

7

8

10 10 frequency (Hz)

9

10

10

10

180 135 90

A B C D 6

10

10 10 frequency (Hz)

9

10

10

10

(b) Fig. 3.17. Inﬂuence of technology scaling (A. classical n-well diode 0.18 µm, B. classical n-well diode 0.13 µm, C. diﬀerential n-well diode 0.18 µm, D. diﬀerential n-well diode 0.13 µm): (a) responsivity, (b) normalized intrinsic frequency characteristic.

capacitance. These values have to be taken into account during the transimpedance ampliﬁer design.

3.6 Conclusions This chapter was completely devoted to one single device: the photodiode. It has an important function in the optical receiver, as it is the interface between the optical and the electrical domain. Its speed and responsivity are of uttermost importance for the performance of the complete receiver chain. To understand the opto-electrical mechanisms, some deﬁnitions have been introduced ﬁrst. Next, to illustrate the feasibility of integrated silicon photo-

3.6 Conclusions

59

Table 3.2. Junction capacitance and technology scaling. 0.18 µm CMOS 0.13 µm CMOS Zero bias area junction capacitance 1.07 · 10−4 F/m2 2.17 · 10−4 F/m2 Zero bias side-wall junction capacitance 2.4 · 10−11 F/m 2.7 · 10−10 F/m total capacitance classical n-well diode (Ns = 10) total capacitance illuminated junctions diﬀerential n-well diode (Nf = 26)

428 f F

1.5 pF

210 f F

875 f F

detectors, some published BiCMOS, SOI and CMOS implementations have been discussed. The advantage of CMOS over the other technologies is a lower cost, making it the chosen technology for low-cost, high-volume mass applications. The light detection principles and carrier transport mechanisms involved in a pn-junction have been described both qualitatively and quantitatively using semiconductor physics. This one-dimensional model shows that the nwell p-substrate junction can be used to detect light, but the rise time for red light is only 19 ns. The speed can be enhanced using the p+ n-well junction, which is shielded from the diﬀusing substrate carriers by the n-well p-substrate junction. The improved rise time of 1.5 ns comes at the expense of a lower responsivity: 0.09 A/W compared to 0.32 A/W. A two-dimensional model has been developed to include the non-negligible eﬀect of side-wall junction capacitances. Also the retrograde well doping proﬁle has been taken into account. Depending on the amount of substrate contacts, the classical n-well diode has a responsivity ranging from 0.29 A/W to 0.33 A/W. The speed is mainly limited by the diﬀusing carriers in the substrate, and independent of the n-well layout topology. The photodiode 3dBbandwidth equals 10 MHz, while the low-frequency roll-oﬀ is 5 dB/decade. Two diode topologies to enhance the speed performance have been investigated using this two-dimensional model: the p+ n-well diode with guard and the diﬀerential n-well diode. For the ﬁrst topology, speed is again not much inﬂuenced by the amount of n-well squares, and the diode 3-dB bandwidth equals 1 GHz. For the latter diode, the amount of n-well ﬁngers does aﬀect bandwidth, which varies from 1 GHz (18 ﬁngers) to 4.4 GHz (34 ﬁngers). The diﬀerential diode is not only capable of higher bitrates, also the responsivity is better: for a simulated bandwidth of 1 GHz, the responsivity is 0.052 A/W for the diﬀerential diode versus maximum 0.023 A/W for the p+ n-well diode with guard. The two-dimensional results discussed above all reﬂect the photodiode performance for 850 nm light, used in short-distance communication networks. Because there exists a lot of low-cost applications using shorter wavelengths, the performance of the classical and diﬀerential diode has been studied using red (650 nm) and blue light (400 nm) . The light wavelength does inﬂuence

60

3 Standard CMOS Photodiodes

the optical performance, and red light turns out to be the most “optimal” wavelength concerning speed and responsivity. When blue light is used, the diﬀerential diode topology becomes pointless, as there are no diﬀusing carriers in the substrate which have to be compensated for. As Moore’s Law is still valid in the silicon nano-scaled technology, the consequences of the transition from a 0.18 µm to a 0.13 µm technology have been discussed. Due to higher doping levels and smaller supply voltages, the width of the space charge region becomes smaller, resulting in photodiodes with a slightly smaller responsivity, a lower 3-dB bandwidth and a higher capacitance value. The latter result will directly have impact on the transimpedance ampliﬁer design. Finally, an important conclusion concerning all the device simulations in this chapter is that there exists a trade-oﬀ between responsivity and speed. Depending on the system requirements and consequently the diode speciﬁcations, a proper design choice has to be made.

4 Transimpedance Ampliﬁer Design

4.1 Introduction The transimpedance ampliﬁer (TIA) is without a doubt the most critical building block of the optical receiver. It converts the current generated by the photodiode into an output voltage. The design of this block involves many trade-oﬀs between noise, bandwidth, gain and stability. This chapter tries to reveal all subtleties and challenges encountered during the design of low-noise high-bandwidth TIAs. A summary of the TIA speciﬁcations regarding transimpedance gain, bandwidth, noise and overload currents is given in Section 4.2. Section 4.3 tackles the design of a TIA with shunt-shunt feedback. Design equations are derived for the transimpedance gain, bandwidth, open-loop gain, loop gain and the noise performance. Implementations published in open literature are discussed in Section 4.4. Two main topologies are distinguished: the TIA with common-source input stage and the TIA with regulated cascode input stage. Also some interesting work presented at ISSCC is described. Finally, the designs of three diﬀerent TIAs, of which two are implemented in a 0.18 µm CMOS and one in a 90 nm CMOS technology, are explained more thoroughly in Section 4.5. These case studies clearly demonstrate the compromises to be made during the design of low-noise high-speed TIAs.

4.2 Performance Requirements This section presents the main performance requirements for a TIA: high transimpedance gain, high bandwidth, low noise and high overload current. Transimpedance Gain The transimpedance gain of the TIA, ZT IA , is deﬁned as the ratio of the small-signal output voltage to the small-signal input current: 61

62

4 Transimpedance Ampliﬁer Design

ZT IA =

vout = |ZT IA (f )|ejθ(f ) . iin

(4.1)

The higher this value, the more output signal is produced for a given input signal. The transimpedance gain is speciﬁed either in units of Ω or dBΩ. The value dBΩ is calculated as 20 · log10 (ZT IA /Ω). The transimpedance gain is a complex quantity, with frequency-dependent magnitude |ZT IA (f )| and frequency-dependent phase shift θ(f ). The transimpedance gain at low frequencies is usually ﬂat, and represented by ZT IA,0 . The ﬁrst reason for having a TIA with high gain is to create a signal with an amplitude large enough to drive the post-ampliﬁer (PA). But there is an additional reason which might be even more important: noise. As the TIA is the ﬁrst stage in the optical receiver (Fig. 2.1), the noise of the next stages like the PA will be suppressed by the TIA gain. So a lower transimpedance gain (for example to obtain a higher bandwidth (4.11)) cannot simply be exchanged for a larger post-ampliﬁcation. The total gain remains constant, but the total input-referred noise of the receiver will increase. Bandwidth The upper frequency at which |ZT IA (f )| (4.1) has dropped 3 dB below its DC value, is deﬁned as the TIA bandwidth, BWT IA . As discussed in Section 2.5, a limited bandwidth causes ISI and degrades the opening of the eye diagram. To receive data with a certain bitrate Rb , the bandwidth must be as high as possible to minimize the ISI. But on the other hand, Section 4.3.3 will demonstrate that a large bandwidth increases the noise picked up by the TIA. As a compromise between noise and ISI, a TIA bandwidth equal to 0.7Rb is commonly used [Raz03, S¨ac05]. Noise The input-referred current noise is one of the most critical TIA parameters. Often the noise of the TIA dominates all other noise sources and therefore determines the sensitivity of the receiver. The equivalent input-referred noise current is the current source that, together with the ideal noiseless TIA, reproduces the output noise of the actual noisy TIA. As stated before in Section 2.4.2, it is a ﬁctitious quantity that cannot be observed in the actual circuit. To determine the input-referred noise current, the noise power spectral density at the output for each noise source is calculated ﬁrst. Typical noise sources are transistors, resistors and diodes. Assuming these sources are not correlated, they add up to form the total output noise power spectral density. The power spectral density of the input-referred noise current, di2n,T IA , can then be found by taking the frequency-dependent transimpedance gain into account:

4.3 Design of the Shunt-Shunt Feedback TIA

di2n,T IA =

63

2 dvn,T IA

. (4.2) |ZT IA (f )|2 The input-referred rms noise current, in,rms (2.7), also called the total integrated input-referred noise current of the TIA, in,T IA , is determined by dividing the rms output noise voltage by the DC value of the transimpedance gain. The rms output noise voltage is obtained by integrating the output-referred noise spectrum and taking the square root. ∞ 1 2 dvn,T (4.3) in,T IA = IA df . ZT IA,0 0 Note that this deﬁnition is diﬀerent from integrating the input-referred noise current to a certain bandwidth. For analytical calculations, the integration has to be carried out to inﬁnity. For simulations and measurements, a few times the bandwidth BWT IA , or simply the bandwidth (for higher order TIAs with a steep roll-oﬀ) is taken as upper limit. For completeness, the deﬁnition of noise bandwidth BWn is repeated here. It is the bandwidth, multiplied by the DC value of the power spectral noise density, which gives the same result as the integration of the power spectral noise density to inﬁnity. For a ﬁrst order circuit, BWn equals π2 times the 3-dB bandwidth [San06]. For a third order circuit with a steeper slope, the noise bandwidth and the 3-dB bandwidth nearly coincide. Overload Current A TIA may receive large signal currents, for example when the distance between transmitter and receiver is very short and the photodetector has a high responsivity. As the input level increases, the TIA will introduce nonlinearities in the signal. Due to the binary nature of transmitted data, some nonlinearity can be tolerated. However, too much nonlinearities may corrupt the signal levels and/or distort the zero crossings, increasing the BER. Naturally, this has to be avoided. Following the simulations of Chapter 3, the responsivity of integrated CMOS diodes is rather low, because the standard silicon technology is not optimal for optical applications. So even for large optical signals, the currents at the input will remain below the overload current.

4.3 Design of the Shunt-Shunt Feedback TIA The TIA topology used in this work is the so-called shunt-shunt feedback TIA. A negative feedback network senses the voltage at the output and returns a proportional current to the input. This type of feedback has the advantage that it lowers both the input and output impedance. As a result, the closedloop bandwidth is increased by the loop gain. In this section, the main design equations for the shunt-shunt feedback TIA are derived.

64

4 Transimpedance Ampliﬁer Design TIA

Rf

Rout

nin

Idio

nout

A0

C dio

Cout

Cin

Cnext

PD

(a) Rf vin i dio

Rout

nin

C dio

−A0 vin

Cin

C inT

nout

vout

C out

Cnext

C outT

(b)

Fig. 4.1. The shunt-shunt feedback TIA: (a) general schematic, (b) small-signal equivalent circuit.

4.3.1 Transimpedance Gain and Bandwidth Fig. 4.1(a) shows a general schematic of the shunt-shunt feedback TIA. The photodiode is represented by the current source Idio in parallel with the junction capacitance Cdio . The TIA consists of a voltage ampliﬁer with DC gain A0 and feedback resistance Rf . The input capacitance Cin and output capacitance Cout are determined by the sizes of the transistors that constitute the voltage ampliﬁer. Cnext is the input capacitance of the next stage. Rout is the TIA output resistance and is usually much smaller than Rf . The analysis of the small-signal equivalent circuit, depicted in Fig. 4.1(b), results in following transimpedance gain: ZT IA =

vout Z T IA,0 = R C C (R R out inT outT f f +Rout )CinT idio s2 +s + A0 +1 A0 +1

Rout CoutT A0 +1

, +1 (4.4)

with: ZT IA,0 =

Rout Rf A0 − ≈ Rf , A0 + 1 A0 + 1

(4.5)

4.3 Design of the Shunt-Shunt Feedback TIA

65

CinT = Cdio + Cin ,

(4.6)

CoutT = Cout + Cnext .

(4.7)

According to (4.5), the transimpedance gain at low frequencies equals Rf for large values of A0 and small values of Rout . To ﬁnd the bandwidth of (4.4), two separate cases are considered. First, suppose the second pole of the TIA has a much higher magnitude than the ﬁrst pole. Taking into account following approximations: A0 + 1 ≈ A0 , Rout Rf ,

(4.8) (4.9)

Rout CoutT Rf CinT ,

(4.10)

the well-known expression for the TIA bandwidth BWT IA can be found: BWT IA =

A0 . 2πRf CinT

(4.11)

The dominant pole, which determines the bandwidth in this case, is located at the input node nin. Due to the feedback loop, the resistance at this node is divided by the loop gain, which results in a factor A0 increase of bandwidth. Therefore, A0 has to be maximized during the design process. Other factors that inﬂuence bandwidth are the feedback resistor Rf and the total input capacitance CinT . Rf usually cannot be made too small for gain (4.5) and noise considerations (4.36). CinT consists of two parts: Cdio , determined by the photodiode topology, and Cin , which increases for larger transistor dimensions. This expression for the bandwidth reveals two important conclusions: • As the photodiode junction capacitance directly appears in the denominator of (4.11), a photodiode-TIA co-design is mandatory. • A design aiming for high bandwidth implies an optimization of the voltage gain A0 . The non-dominant pole is located at the output node nout. It coincides with the bandwidth BWV A of the voltage ampliﬁer, which has only one pole in the simpliﬁed model of Fig. 4.1. fnd,T IA = BWV A =

1 . 2πRout Cout

(4.12)

However, the two poles of a second-order system can seldom be treated as two real poles. Mostly, they will be part of a complex conjugated pair. In basic control theory, the denominator of a second-order system is written as [Dor98]: s 2 s + 2ζ + 1, (4.13) ωn ωn where ζ is the dimensionless damping ratio and ωn is the natural pulsation of the system. When ζ = 1, the system is critically damped. Complex conjugated

66

4 Transimpedance Ampliﬁer Design

poles occur when ζ < 1. The relation between 3-dB bandwidth ω3dB , natural pulsation ωn and damping ratio ζ can be calculated by setting the magnitude √ of (4.13) equal to 2/ 2: √ ω3dB = (1 − 2ζ 2 ) + 2 2ζ 4 − 2ζ 2 + 1. ωn

(4.14)

A smaller ζ will result in a larger 3-dB bandwidth, but also a higher overshoot in the time domain and a larger resonance peaking in the frequency domain. This causes degradation of the high and low levels and jitter in the eye diagram, despite the large bandwidth. In [Dor98] the percent overshoot P.O. is deﬁned by: √ 2 (4.15) P.O. = 100e−ζπ/ 1−ζ . √ Setting ζ equal to 2/2 is an attractive solution. The percent overshoot is only 4 %, while the 3-dB bandwidth equals ωn . It also generates a system with a maximally ﬂat frequency response, which corresponds to a Butterworth ﬁlter. This way, a compromise is found between bandwidth and overshoot, leading to a high-quality eye diagram. Equating (4.13) with the denominator of (4.4) gives following results for the natural pulsation and damping ratio of the second-order TIA depicted in Fig. 4.1: A0 + 1 , (4.16) ωn = Rf Rout CinT CoutT R C

f inT +1 1 . ζ = Rout CoutT R 2 (A + 1) f CinT

0

(4.17)

Rout CoutT

For suﬃciently large gain A0 , the last equation can be rewritten as: 1 A0 = 4ζ 2 . Rout CoutT Rf CinT

(4.18)

This is the condition at the input node nin and output node nout of Fig. 4.1 which has to be fulﬁlled to design a TIA with a certain damping ratio ζ. Combining (4.18) and (4.16), the corresponding natural pulsation can be found. More interesting is the 3dB-bandwidth, which can be calculated using (4.14). The results for some typical values of ζ are summarized in Table 4.1. Comparing the fourth column of Table 4.1 with the earlier derived expression for the TIA bandwidth, (4.11), an increase in bandwidth is noticed. The system under study is unchanged, only the basic assumptions for the hand calculations are diﬀerent. In the case of (4.11), the TIA has two well-separated real poles while in the other case, the poles are complex conjugates. Due to these complex poles, the resulting 3dB-bandwidth is larger, but some overshoot will occur in the eye diagram. However, this is tolerable as long as the

4.3 Design of the Shunt-Shunt Feedback TIA

67

Table 4.1. Design equations for the second-order TIA of Fig. 4.1. ζ

Condition (4.18) ωn (4.16) ω3dB (4.14) P.O. (4.15) P.M. (4.27)

1 1 2 Rout CoutT √ 1 2 2 Rout CoutT √ 1 3 2 Rout CoutT

=

A0 Rf CinT

=

2A0 Rf CinT

=

3A0 Rf CinT

A0 Rf CinT √ 2A0 Rf CinT √ 3A0 Rf CinT

1.6A0 Rf CinT √ 2A0 Rf CinT 1.07A0 Rf CinT

16 %

45◦

4%

63◦

0.4 %

72◦

damping ratio is high enough and no ringing occurs. The smaller ζ, the higher the bandwidth, but the more overshoot and ringing. Also the phase margin decreases with ζ. An expression for the phase margin (P.M.) will be derived in the next subsection. Most important is that the main conclusions of (4.11) are still valid: the TIA bandwidth BWT IA is inversely proportional to the input capacitance CinT (which contains the photodiode capacitance Cdio ), inversely proportional to the feedback resistor Rf , and directly proportional to the DC √ gain A0 of the voltage ampliﬁer. Note also that for ζ = 3/2, the expression for the bandwidth almost equals (4.11). The ﬁrst two designs discussed in Section 4.5 will use a rather safe phase margin of at least 72◦ . The last design will allow more √ overshoot in exchange for a higher bandwidth, so ζ will be more around 2/2. This overshoot can be tolerated, as the TIA is followed by a limiting ampliﬁer, which will be discussed in Chapter 5. To compare the performance of diﬀerent TIAs, a parameter which takes into account several of its characteristics is needed. In analogy with the gainbandwidth product GBW of voltage ampliﬁers [San06], the transimpedancebandwidth product ZBW is used to evaluate the TIA performance. It is deﬁned by the product of its transimpedance gain ZT IA,0 and its 3-dB bandwidth BWT IA : A0 ZBW = ZT IA,0 · BWT IA ≈ . (4.19) 2πCinT The transimpedance-bandwidth is independent of the feedback resistor Rf . To some extent, transimpedance gain can simply be exchanged for bandwidth and vice versa, by changing the value of Rf . The only limitation is that the damping ratio has to be high enough, or equivalently, that there needs to be suﬃcient phase margin. (Table 4.1). The transimpedance-bandwidth ZBW (4.19) again emphasizes the importance of the voltage gain A0 . As the total input capacitance is largely determined by the photodiode capacitance, whose parameters are dictated by technology rules and ﬁber size, the only way to optimize ZBW is by maximizing A0 .

68

4 Transimpedance Ampliﬁer Design vin

Rout

nin

idio

C inT

Rf

vout Rf

−A0 vin

nout

Rf

vout

vin Rf

CoutT

(a) idio

−Rf 1+sR f C inT

vin

1

−A0 1+

GTIA

Rf R out

vout

+s R out C outT

1 Rf (b)

Fig. 4.2. TIA representations to determine open-loop gain and loop gain: (a) Coates transformation of Fig. 4.1(b), (b) block diagram.

4.3.2 Open-Loop Gain and Loop Gain Another way of looking at the TIA with shunt-shunt feedback, is depicted in Fig. 4.2(a). The feedback resistor Rf between nodes nin and nout is replaced by its Coates transformation: resistor Rf and voltage-controlled current source vout /Rf between node nin and ground; and resistor Rf and voltagecontrolled current source vin /Rf between node nout and ground. Starting from this equivalent circuit, the block diagram of Fig. 4.2(b) can be derived. It represents the feedback system by its open-loop gain GT IA and loop gain GHT IA . In the block diagram of Fig. 4.2(b), the feedforward voltage controlled current source vin /Rf has been neglected. This is allowed if ARf Rout , which is almost always true. The expression for the open-loop gain GT IA is then given by: GT IA =

A0 Rf . (1 + sRf CinT )(1 + RRout + sRout CoutT ) f

(4.20)

If it also can be assumed that Rf Rout , the open-loop gain further reduces to: A0 Rf GT IA = . (4.21) (1 + sRf CinT )(1 + sRout CoutT ) The loop gain GHT IA equals the open-loop gain GT IA times the feedback factor 1/Rf , or:

4.3 Design of the Shunt-Shunt Feedback TIA

GHT IA =

A0 . (1 + sRf CinT )(1 + sRout CoutT )

69

(4.22)

The phase margin is often used in basic control theory to study the stability of feedback systems [Dor98]. It is the amount of extra phase shift of the loop gain (GHT IA ) at unity magnitude (or 0 dB) that will result in a phase angle of 180◦ . To derive an expression for the phase margin, it is assumed that the poles of (4.22) are real and diﬀer a lot in magnitude. So the dominant pole fd,GH and non-dominant pole fnd,GH of the loop gain GHT IA can readily be found: 1 , 2πRf CinT 1 = . 2πRout CoutT

fd,GH = fnd,GH

(4.23) (4.24)

Note that the latter is also the pole which determines the bandwidth of the voltage ampliﬁer, BWV A (4.12). The unity-gain frequency of the loop gain f0dB,GH is given by: A0 f0dB,GH = , (4.25) 2πRf CinT assuming fd,GH f0dB,GH fnd,GH . Under the same condition, the phase angle at this frequency equals: θ(f0dB,GH ) = −(

f π 0dB,GH . + arctan 2 fnd,GH

(4.26)

This results in the expression for the phase margin P.M.: P.M. =

f f π 0dB,GH nd,GH = arctan . − arctan 2 fnd,GH f0dB,GH

(4.27)

For instance, if fnd,GH = 3 · f0dB,GH , the phase margin equals 72◦ . Other examples for smaller ratios are given in Table 4.1. Note however that these are hand calculations and that the expression for the P.M. approaches reality only if fd,GH f0dB,GH fnd,GH . For the other equations in Table 4.1, the requirements regarding pole location are less stringent. The expressions derived so far are valid for the voltage ampliﬁer model depicted in Fig. 4.1, which has only one dominant pole at the output. If the voltage ampliﬁer consists for example of three identical amplifying stages, three more or less identical poles fnd,GH are present. The loop gain can now be approximated by: GHT IA = and the phase margin:

A0 (1 + sRf CinT )(1 +

, s 3 fnd,GH )

(4.28)

70

4 Transimpedance Ampliﬁer Design

P.M. =

f π 0dB,GH , − 3 · arctan 2 fnd,GH

(4.29)

with f0dB,GH given by (4.25). To achieve the same phase-margin, the ratio of f0dB,GH to fnd,GH has to be approximately three times smaller than the ratio in (4.27). So assuming the same f0dB,GH , the non-dominant pole of the loop-gain, which coincides with the bandwidth of the voltage ampliﬁer, has to be three times higher in frequency for a three-stage ampliﬁer compared to a single-stage ampliﬁer. A good reason for choosing a multiple-stage approach would be to increase the voltage ampliﬁer’s gain A0 . This way, the bandwidth BWT IA is enlarged, or for the same bandwidth, the feedback resistance Rf can be larger (4.11). As will become clear in Section 4.3.3, a larger Rf leads to a better TIA noise performance and thus a better receiver sensitivity. However, due to stability requirement (4.29), the voltage gain of a three-stage ampliﬁer is limited by the ratio of the bandwidth of the TIA (BWT IA ) and the fT of a certain technology. In [Ing04] it is demonstrated that, when BWT IA ≈ 0.1fT or larger, the maximal achievable gain of a single stage voltage ampliﬁer is larger than the maximal achievable gain of a three-stage voltage ampliﬁer. Applications demanding a high bandwidth compared to the technology’s fT have to implement a single-stage ampliﬁer rather than a three-stage ampliﬁer, as there is simply no room for placing the extra poles which are introduced in a multiple-stage approach. However, for frequencies 20 to 30 times below fT , a multiple-stage ampliﬁer is the best design choice. 4.3.3 Noise The noise sources of the shunt-shunt feedback TIA are added to the general schematic in Fig. 4.3. Two TIA noise sources can be distinguished: the noise from the feedback resistor and the noise from the voltage ampliﬁer. The third noise source stems from the noise generated by the photodiode. Noise Densities of the Three Noise Sources The thermal noise of the resistor is modeled by a current noise source di2Rf in parallel: 4kT di2Rf = df. (4.30) Rf The noise current power is proportional to the absolute temperature in Kelvin, and inversely proportional to the value of the feedback resistor Rf . It is white noise, as it does not change with frequency. The noise of the voltage ampliﬁer is represented by the noise of an equivalent input transistor Mx with equivalent transconductance gmx . In most designs, where the input stage features large gain, the equivalent transistor Mx simply corresponds to the input transistor of the voltage ampliﬁer. For a MOS

4.3 Design of the Shunt-Shunt Feedback TIA

71

2

diR

f

Rf

A0

2

diM

x

nin 2 didio

Idio

C dio

Cin

Mx

Rout

nout

Cout

Cnext

Fig. 4.3. The shunt-shunt feedback TIA with the most important noise sources.

transistor, the classical thermal channel noise di2Mx is still the most important noise source. It is given by: di2Mx = 4kT γgmxdf,

(4.31)

where γ is the excess noise factor. This noise current power is also white and proportional to the absolute temperature and to the transconductance gmx . For long-channel devices, γ = 2/3. In short-channel devices the eﬀective temperature of the carriers is signiﬁcantly larger due to the high electric ﬁeld in the channel and γ can be as high as 2 or 3. The pMOS transistor usually exhibits lower γ values than its nMOS counterpart. Finally, the last noise source is the noise from the photodiode di2dio . Mostly, it consists only of shot noise, which is given by: di2dio = 2qIdio df.

(4.32)

The shot noise current power is also white, and proportional to the current ﬂowing through the junction. This noise power is data-dependent: when a photodiode receives a zero, no light power is received, and the current Idio is (almost) zero. When a one is received, the generated noise depends on the received light power and the photodiode responsivity. As the noise current varies with time, it is called non-stationary. However, in most cases, the photodiode shot noise can be neglected. Output Noise Spectral Density and Input-Referred Noise Spectral Density The power spectral density of the output noise voltage is given by the noise current power of each noise source, multiplied by the square of its transfer function to the output.

72

4 Transimpedance Ampliﬁer Design

di2dio ZT2 IA,0 2 dvn,T = 2 IA 2 Rf Rout CinT CoutT (Rf +Rout )CinT Rout CoutT + 1 + s + s A0 +1 A0 +1 A0 +1 2 2 R A di2Rf Af0 +10 1 + s RoutAC0 inT + 2 2 Rf Rout CinT CoutT (Rf +Rout )CinT Rout CoutT + 1 + s + s A0 +1 A0 +1 A0 +1 2 2 di2Mx RAout 1 + sRf CinT 0 + 2 . 2 Rf Rout CinT CoutT (Rf +Rout )CinT Rout CoutT + 1 + s + s A0 +1 A0 +1 A0 +1 (4.33) This expression can be simpliﬁed using following assumptions: • The shot noise of the photodiode is negligible small compared to the other noise sources. • A0 + 1 ≈ A0 . A0 • The zero 2πRout CinT is located at a frequency beyond the frequency range of interest. This corresponds to neglecting the feedforward current of Rf , injected by its noise source in node nout. • Following the one-transistor equivalent of the voltage ampliﬁer, gmx Rout = A0 . The resulting expression for the output noise spectral density is: 4kT Rf df 2 dvn,T IA = 2 Rf Rout CinT CoutT (Rf +Rout )CinT +s + s A0 +1 A0 +1 2 4kT γdf gmx 1 + sRf CinT + 2 Rf Rout CinT CoutT (Rf +Rout )CinT + s + s A0 +1 A0 +1

Rout CoutT A0 +1

Rout CoutT A0 +1

2 + 1

2 . + 1 (4.34)

This expression is plotted versus log(f ) in Fig. 4.4(a). At low frequencies, the noise is dominated by the feedback resistor’s thermal noise. At higher frequencies and for a suﬃcient high gain A0 , the ampliﬁer noise may become dominant. Note that the integration of the power spectral density in this case will lead to an integrated output noise voltage which is dominated by the noise of the ampliﬁer. The representation in Fig. 4.4(a) may suggest something else, but it is misleading due to the logarithmic frequency axis which overemphasizes the integrated low-frequency noise. In a design aiming primarily for large bandwidth, the dominant noise source might be the feedback resistor and not the ampliﬁer. This is the case when the zero and poles of (4.34) are located close to each other, which is usually true for high BWT IA /fT ratios. As the bandwidth is comparable to

4.3 Design of the Shunt-Shunt Feedback TIA dv2n,TIA (dB/Hz) 4kTγ A2 g mx 0

di 2n,TIA (dB/Hz)

Rf amplifier total

73

Rf amplifier total

4kTRf 4kT Rf

4kTγ g mx

4kTγ g mxR2f 1 2π Rf CinT

BWTIA

fnd,TIA f (Hz)

(a)

1 2π Rf CinT

f (Hz)

(b)

Fig. 4.4. Power spectral densities of: (a) TIA output noise, (b) TIA input-referred noise.

fT , there is not much headroom left to place the other poles. An additional advantage is that complex conjugated poles increase the bandwidth, as discussed in Section 4.3.1. Moreover, the noise generated by the feedback resistor is quite large, as the TIA bandwidth is inversely proportional to its resistance value. This value is a few orders of magnitude smaller than in traditional designs, where a bandwidth of a few megahertz is suﬃcient. Finally, also the voltage gain A0 cannot be very large as too much loop gain can cause stability problems. As a result, the maximum value for the ampliﬁer output noise power spectral density depicted in Fig. 4.4(a) and given by: 4kT γ 2 A , gmx 0

(4.35)

will not be reached and the actual maximum will stay below 4kT Rf . Examples of diﬀerent output noise spectral densities will be discussed in Section 4.5. To compare the output voltage noise with the input photodiode current, the output noise is referred to the input. According to (4.2), the power spectral density of the input-referred current noise is given by the division of (4.34) by the square of (4.4). 2 4kT 4kT γdf + sR di2n,T IA = df + C (4.36) 1 . f inT Rf gmx Rf2 This expression is plotted versus frequency in Fig. 4.4(b). The ﬁrst term is caused by the feedback resistor Rf . It is frequency independent and equal to the thermal noise of Rf (4.30). Neglecting the feedforward noise current, only the feedback current at the input remains which directly adds up with the photodiode current. The larger Rf , the smaller this noise, but also the smaller the TIA bandwidth BWT IA (4.11). The second term is the noise contribution

74

4 Transimpedance Ampliﬁer Design

of the voltage ampliﬁer. It features a zero at 1/2πRf CinT , which is a factor A0 below the bandwidth BWT IA (4.11). Due to this zero, the ampliﬁer’s noise may become dominant at higher frequencies. The noise contribution of both the feedback resistor and the ampliﬁer result in an input-referred noise spectrum which is ﬂat at low frequencies, and rises with f 2 at higher frequencies. Noise Optimization As the noise of the TIA directly determines the receiver’s sensitivity, the TIA design plan must include a minimization of noise. Since the TIA is a broadband ampliﬁer, not only the power spectral density of the noise is important, but the integrated noise is even more important. Diﬀerent noise analyses can be found in literature which are based on slightly diﬀerent assumptions. However they have two approximations in common: ﬁrst, the noise of the light detector is neglected and second, the noise of the post-ampliﬁer is neglected. In Section 4.5 some design examples will show that the ﬁrst assumption is not always valid. The latter assumption it true when the transimpedance gain is always suﬃciently high, but in reality this is not always the case. However, since an increased transimpedance gain goes hand in hand with a reduced TIA noise, neglecting the noise of the post-ampliﬁer rarely aﬀects the design optimum. An overview of the most important results is given here. A thorough noise analysis of wide-band ampliﬁers in bipolar and CMOS technologies is given in [Cha91]. An expression is derived for the equivalent input noise density of a wide-band ampliﬁer with capacitive source, which belongs to the same ampliﬁer category as the transimpedance ampliﬁer. The noise reaches a minimum value when the input capacitance of the voltage ampliﬁer equals all other capacitances at the input node. Assuming that the thermal noise of the input transistor is dominant, the optimal input transistor width is calculated. A more speciﬁc noise analysis of a shunt-shunt feedback transimpedance ampliﬁer is presented in [Ing04]. The output noise power density is calculated, but in contrast to (4.34), two separate poles, a dominant pole (4.11) and non-dominant pole (4.12) are assumed in the denominator. The equivalent input-referred noise current (4.36) is minimized, taken into account following assumptions: • gm Rf > 1 • Cin of the ampliﬁer is mainly determined by the gate-source capacitance Cgs of the input transistor. Cgd and the Miller eﬀect on this capacitance, are neglected. • The excess noise factor γ equals 2/3. The optimal gate-source capacitance Cgs , corresponding to the minimal inputreferred current noise, is found to be equal to the diode capacitance: Cgs = Cdio . This is the same result as derived by [Cha91].

4.3 Design of the Shunt-Shunt Feedback TIA

75

However, this result is not unconditional, but based on the assumption that the feedback resistor Rf is independent of the input capacitors. In high-speed receivers, the maximal feedback resistor is limited and its noise contribution becomes relatively more important compared to that of the ampliﬁer. As the receiver’s bandwidth is limited by both Cgs and Rf , there is inevitably some trade-oﬀ between them, also for the noise performance. The optimal ratio XN between Cgs and Cdio is derived in [Ing04] based on a maximization of the signal to noise ratio at the output. The noise power at the output is obtained by integration of the output noise power spectrum (4.34), represented in Fig. 4.4(a). The signal power at the output depends on the spectrum of the data signal and its data coding scheme. In [Ing04], a ﬂat signal spectrum is assumed. The optimal ratio corresponding with the best signal to noise ratio is than given by: XN,opt =

Cgs,opt ≈ Cdio 1+

1 μ(Vgs −VT ) 9 4 A0 L2 FBW BWT IA

,

(4.37)

with factor FBW deﬁned as: FBW =

π BWV A − 1. 2 BWT IA

(4.38)

For typical values of the various parameters this ratio lies between 0.5 and 1. The optimal Cgs is thus always smaller than Cdio . In [Ing04], the signal to noise ratio of a TIA with a single stage voltage ampliﬁer in a 0.7 µm CMOS technology is plotted versus XN . The SNR-curve is relatively ﬂat, which means that a deviation from the optimal XN only results in a slightly lower signal to noise ratio. In [Ler04] the bandwidth of the TIA is considered as a ﬁxed design constraint for a given application. As in [Ing04], the noise optimum is found by integrating both signal and noise at the output of the TIA and maximizing the SNR. The aim of the optimization is to ﬁnd the optimal Cgs of the input transistor for a given maximum voltage gain A0 and unity gain frequency fT . The power spectral density of the NRZ signal Sout is now more accurately described by: 2 2 sin(πf Tb ) Rf 2 Sout = idio Tb (4.39) , R C (1 + s f inT )(1 + sRout Cout ) πf Tb A0 where idio is the amplitude of the diode input current and Tb is the bit period. So again two separated poles are assumed for the transimpedance gain, and its DC value is approximated by Rf . The dominant pole of (4.39), BWT IA (4.11), is set by the bitrate of the application. It is also (approximately) equal to the unity-gain frequency of the loop gain. It can further also be assumed that the non-dominant pole, given by (4.12), is ﬁxed to a minimum value enforced by the stability requirement. Under these assumptions, the output signal power

76

4 Transimpedance Ampliﬁer Design

is solely depending on the DC transimpedance gain Rf . To maximize the SNR it suﬃces to minimize the input-referred integrated noise power i2n,T IA : ∞ i2n,T IA

=

0

2 dvn,T IA df

Rf2

.

(4.40)

So the same integration of the output noise power spectral density is performed as in [Ing04]. The major diﬀerence is that now Cgd and the Miller eﬀect are taken into account: (4.41) Cin = Cgs (1 + Mi αgd ), with: αgd =

Cgd . Cgs

(4.42)

and Mi = A0 + 1. The transconductance gm is rewritten as: gm = 2πfT Cgs =

2πfT Cin . 1 + Mi αgd

(4.43)

The expressions found in [Ler04] demonstrate that the input referred noise increases with the second power of the bandwidth for the Rf contribution and even to the third power for the ampliﬁer contribution. This clearly shows that designing sensitive optical receivers becomes increasingly diﬃcult for larger bitrates. The optimal ratio XN,opt is now given by: XN,opt ≈

1 fT (1 + Mi αgd )2 + (1 + Mi αgd ) 3π 4 BWT IA

1 γA0 FBW

.

(4.44)

By including the Miller eﬀect, the optimal Cgs is even smaller than the optimum (4.37) found in [Ing04]. A numerical example in [Ler04] illustrates that Cgs can be as small as ≈ 0.23 · Cdio (for αgd = 0.25, fT /BWT IA = 20, γ = 1, Mi = 11, FBW = 4). Note also that according to (4.44), the ratio XN,opt will decrease for newer technologies with increasing fT and the same bandwidth BWT IA .

4.4 Literature Examples The main question after studying the high-level design of a TIA is how to realize the voltage ampliﬁer depicted in Fig. 4.1. In literature, two important approaches can be found: the TIA with common source input stage and the TIA with regulated cascode input stage. Both are discussed next, with some paper references as example. Also a survey is given of the latest novelties regarding TIA design presented at the International Solid-State Circuits Conferences (ISSCC).

4.4 Literature Examples

M2 Rf

Rf

77

Vout

Vout

M1

M1

(a)

(b)

Rf M3

M6

M9 Vout

M1

M2

M4

M5

M7

M8

(c) Fig. 4.5. Schematic of (a) a CS TIA with source follower [Kie03, Swo05], (b) a CS TIA [Tsa04, Rad05, Tsa06], (c) a three-stage TIA with gm /gm amplifying stage [Ing94].

4.4.1 Common Source TIA The most widely used topology, implemented in many variants and technologies, is the TIA with common source input stage, depicted in Fig. 4.5(a). Transistor M1 is the common source transistor which realizes ampliﬁcation. The source follower (M2 ) isolates the drain of M1 from the loading eﬀect of both Rf and the input capacitance of the subsequent stage. In addition, the output resistance of the source follower is only 1/gm,M2 , which is much less than Rf . The voltage gain A0 equals gm,M1 /gds,M1 , assuming the output conductance of the current source can be neglected. This circuit has been used for instance in [Kie03] and [Swo05]. The source follower increases the total loop gain, but consumes a large voltage headroom. One may consider to eliminate this stage, arriving at the circuit depicted in Fig. 4.5(b). In a typical design, the output resistance determined by the parallel combination of the output conductance gds,M1 and the current

78

4 Transimpedance Ampliﬁer Design

source (which might be a simple resistor) is not small anymore compared to the feedback resistance Rf . This topology has been used in [Tsa04, Rad05, Tsa06]. A natural way to implement a common-source ampliﬁer stage in CMOS is adding a pMOS load and connecting the gates, which results in an inverter stage. This way, the transconductance of the input stage is doubled, which leads to a higher voltage gain A0 . As demonstrated in [Ing94], the stability requirement for having suﬃcient phase margin (4.27) in the traditional com2 mon source approach is related to gds,M1 , which is strongly process-dependent. Therefore, the inverter stage presented in [Ing94] features a diode-connected nMOS load transistor, so that the output resistance is now determined by 1/gm,M2 . The voltage gain A0 is given by the ratio of transconductances: A0 =

gm,M1 + gm,M3 . gm,M2

(4.45)

The analysis in [Ing94] shows that this ratio is only process dependent through the square root of the ratio of mobilities. The TIA presented in [Ing94] and shown in Fig. 4.5(c) has three identical stages to create a larger voltage gain A0 . Each of these stages consumes 2 mA from a 5 V supply. A transimpedance gain of 150 kΩ is realized, combined with a bitrate of 240 Mbit/s. This results in a transimpedance-bandwidth of 18 THzΩ. When moving to higher BWT IA /fT ratios, the intrinsic technology speed limits the placement of the non-dominant poles at higher frequencies, which is needed to maintain stability (Section 4.3.2). Therefore, the TIA presented in [Ing99] is based on a single-stage gm /gm voltage ampliﬁer, featuring a high speed combined with an accurate gain. The TIA consumes approximately 5 mA from a single 5 V power supply, and features a transimpedance gain of 1 kΩ. It is realized together with a postampliﬁer based on a biased inverter chain and achieves bitrates up to 1 Gbit/s. The optical receiver is characterized electrically by replacing the photodiode by its Thevenin equivalent. A large resistor is inserted after the 50 Ω signal source and the photodiode capacitance is modeled by a 500 fF capacitor. 4.4.2 Regulated Cascode TIA The regulated cascode (RGC) TIA is actually an extension of the common gate (CG) TIA. The latter topology is depicted in Fig. 4.6(a), where the photodiode is connected to the source of the common gate input transistor M1 [Par97]. This way, the photodiode capacitance sees only a small input resistance determined by 1/gm,M1 . The feedback resistor Rf is inserted between the output (neglecting the source follower M4 ) and the drain of M1 . The dominant pole of this feedback ampliﬁer depends on the input capacitance of M2 , the gate and drain capacitance of M1 and the feedback resistor Rf . In contrast to the common source TIA, the bandwidth is isolated from the photodiode capacitance at the input, which is the major advantage of this topology.

4.4 Literature Examples

R1

R2 Rf M2

Vb

R1

RB

M3

M1

R3 M2

Rf M4 Vout

79

M4 M3

M1

M5 Vout

MB Rs

Rs

(a)

(b)

Fig. 4.6. Schematic of (a) a CG TIA [Par97], (b) a RGC TIA [Par00, Par04].

The RGC TIA is shown in Fig. 4.6(b) and presented in [Par00, Par04] . The small-signal input resistance at the source of M1 is given by: Zin,0 =

1 , gm,M1 (1 + gm,MB RB )

(4.46)

where (1 + gm,MB RB ) is the voltage gain of the local feedback stage. One could say that the RGC input stage behaves qualitatively as a CG input stage with a large transconductance Gm of gm,M1 (1 + gm,MB RB ). It enables (1 + gm,MB RB ) times better isolation of the input parasitic capacitance from the bandwidth determination. A source-follower buﬀer stage M2 is introduced between the RGC input stage and the voltage gain stage M3 −R3 . This follower reduces the total capacitance looking from the high impedance node at the drain of M1 and thus provides a potential for wider bandwidth. However, it may reduce the total open-loop gain and degrades the circuit linearity. The measurement results in [Par00] demonstrate a 3-dB bandwidth of 300 MHz and a transimpedance gain of almost 58 dBΩ with a 6 V power supply. The resulting trans-impedance-bandwidth product equals 238 GHzΩ. However, these values are calculated from S-parameter measurements with a network analyzer, where a test power level of −40 dBm emulates a 50 µA current. As a photodiode is a current source with a high output impedance in contrast with the used voltage source with low output impedance (50 Ω), these values should be treated with care. To facilitate the measurements, the photodiode is modeled as an equivalent electrical circuit in [Par04] and mounted on a test board together with the TIA chip. The frequency response is measured with a network analyzer, achieving a transimpedance gain of 58 dBΩ and 3-dB bandwidth of 950 MHz for a 0.5 pF photodiode capacitance. As a consequence, the transimpedancebandwidth product equals 755 GHzΩ. Also eye diagrams are presented at 622 Mbit/s, 1.0625 Gbit/s, 1.25 Gbit/s and 1.866 Gbit/s for a 231 − 1 prbs

80

4 Transimpedance Ampliﬁer Design

data with 125 µA equivalent input current. The chip core dissipates 85 mW from a 5 V supply. No optical measurements are performed, only electrical measurements with a low-impedance voltage source and the electrical equivalent model of the photodiode. For 1.25 Gbit/s operation, the electrical sensitivity is measured to be 5 µApp for a BER of 10−12 . Although the RGC and CG input stage both have the great advantage that the TIA bandwidth is nearly independent of the photodiode capacitance, there is also a price to pay. The extra transistors and resistors necessary to obtain a low input impedance also present extra noise sources. For instance the resistance current noises of RS on one hand and the parallel combination of R1 and Rf on the other hand directly add up with the input signal. In the common source approach, the only thermal resistance noise which appears directly at the input is the noise of Rf . A detailed noise analysis of the RGC TIA can be found in [Par04]. In [San06], a simpliﬁed comparison of the noise performance between the TIA with voltage ampliﬁer (common source topology) and the TIA with current ampliﬁer (cascode topology) is made. Both comparisons based on noise densities and based on the integrated noise arrive at the same conclusion: the noise of the TIA with voltage ampliﬁer is always smaller, as long as Rf is large enough. As this is usually the case, the regulated cascode topology is not adopted in this work. 4.4.3 The Latest Trends at ISSCC To conclude this literature section, an overview of some design trends of the past years at ISSCC is given. In [Sei04a, Sei04b], the problem is addressed when the TIA bandwidth is limited by the parasitic capacitance of a large polysilicon resistor. A conventional 200 kΩ polysilicon feedback resistor has for instance a 3-dB cut-oﬀ frequency of 67 MHz and therefore this frequency can be the dominant pole of the circuit. To solve this problem, a capacitivecoupled voltage divider is proposed as feedback network instead of a simple feedback resistor. It consists of a low- and high-frequency path of voltage dividers, connected by a coupling capacitor. A pin photodiode is integrated with the TIA in a BiCMOS technology and has a responsivity of 0.43 A/W for 660 nm light. The bandwidth is measured with a network analyzer modulating a laser and equals 378 MHz. Together with a transimpedance gain of 178 kΩ, this results in a transimpedance-bandwidth product of 67 THzΩ. The power consumption equals 70.5 mW from a 5 V power supply, of which the output driver dissipates 38 mW. One year later, [Tsa05b] introduces a self-compensated diﬀerential SiGe TIA which is tolerant of large capacitances at the input. The eﬀective input capacitance caused by the photodiode is signiﬁcantly reduced by adding a unity-gain buﬀer. The voltage at the cathode of the photodiode ideally tracks the RF voltage at the anode of the photodiode. Hence the transient voltage signal across the photodiode is reduced during operation to suppress the effect of its capacitance on the receiver bandwidth. This idea has already been

4.5 Case Studies

81

presented for a single-ended topology in [Tsa04, Tsa05a]. However, a unique feature of the proposed self-compensated diﬀerential topology is that it not only signiﬁcantly suppresses the impact of the photodiode capacitance on the receiver performance, but it also reduces the impact of other capacitances connected from the inputs to ground. When the photodiode is applied externally, these capacitances are due to the bondpads as well as the ESD protection circuits. Optical measurements are performed with the TIA IC integrated with a commercial 1310 nm InGaAs pin photodiode in a chip-on-board assembly. Its parasitic capacitance is around 0.7 pF. A measured 2.5 Gbit/s eye diagram with an optical power of −20 dBm at the input of the TIA IC with ESD protection circuits is shown. The bandwidth of the TIA with ESD equals 1.16 GHz, while the transimpedance gain is adjustable from 1 kΩ to 15 kΩ. No information is provided for which gain setting a 1.16 GHz bandwidth has been measured, so the transimpedance-bandwidth product is situated between 1 THzΩ and 17 THzΩ. The TIA core consumes 4.5 mW from a 3 V supply. Note that this technique is well suited for compensating oﬀ-chip capacitances, but diﬃcult to implement with an integrated CMOS photodiode. For a classical or diﬀerential n-well photodiode (Chapter 3) the anode corresponds to the p-substrate which inevitably has to be biased at the ground potential. Connecting the anode (p-substrate) to the input of the ampliﬁer and the cathode (n-well) to the output of the unity-gain follower is not possible in this case. Finally, a compensation technique at the output of the TIA is presented in [Tsa06]. The basic concept is to cancel the loading eﬀects caused by both the output impedance of the ampliﬁer and the feedback resistor, by introducing a compensation element with a negative impedance. Hence the loop gain can be signiﬁcantly boosted. As a result, the input impedance is reduced and the operating bandwidth is extended. The TIA IC is implemented in a standard 0.35 µm CMOS technology. The diﬀerential transimpedance gain is adjustable from 500 Ω to 13 kΩ. The TIA core dissipates 15 mW from a 3 V supply. Optical measurements demonstrate a bandwidth enhancement factor of 3 achieved by the active compensation technique. Eye diagrams are shown at 1.25 Gbit/s and an optical input power of −27 dBm (high-gain mode) and 0 dBm (low-gain mode). No measured values of the bandwidth are reported (except for the enhancement factor of 3), but assuming a bandwidth of at least 625 MHz, the transimpedance-bandwidth product is larger than 8 THzΩ. To conclude, the transimpedance-bandwidth product of the latest stateof-the-art TIAs equals several THzΩ’s. Furthermore, a trend can be observed that it is easier to achieve high transimpedance-bandwidth products by ampliﬁers with a high gain, but a lower bandwidth, than by high-speed ampliﬁers.

4.5 Case Studies This section discusses in depth three diﬀerent implementations for the voltage ampliﬁer depicted in Fig. 4.1. They all share the common source input stage

82

4 Transimpedance Ampliﬁer Design

topology. As the ultimate goal is to design a high-speed front-end, a singlestage approach is applied in the ﬁrst two implementations. The last design is fully diﬀerential, which enables a two-stage implementation with cross-coupled feedback resistors. The measurement results of these circuits, embedded in a receiver front-end, will be discussed in Chapter 6. 4.5.1 An Inverter-Based TIA for Test Photodiodes in 0.18 µm CMOS Design Goals and Implementation As this TIA is part of a test-chip with several photodiode structures, it must be able to generate a stable output voltage, despite the diﬀerent diode capacitance values at the input. Also, because it is the intention to compare the performance of the diode structures, the TIA should not be the speed limiting factor. Due to the non-optimized responsivity of CMOS photodiodes (see Chapter 3), the equivalent input-referred noise current should be as small as possible. The test photodiodes are: a classical n-well diode, a quasi-fractal nwell diode, a diﬀerential n-well diode, a p+ n-well diode with guard and an n+ p-substrate diode. The layout of these structures will be discussed in detail in Section 6.2. Their junction capacitances are respectively 660 fF, 585 fF, 292 fF, 4.6 pF and 6.8 pF. The schematic of the TIA, with diﬀerent diode conﬁgurations is depicted in Fig. 4.7(a) and Fig. 4.7(b). The n-region of the classical n-well diode, quasifractal n-well diode, diﬀerential n-well diode and n+ p-substrate diode respectively is connected to the input, while the p-substrate is connected to ground (Fig. 4.7(a)). The p+ n-well diode with guard topology consists of 2 diodes: the p+ n-well diode (PD) to detect the signal, and the n-well p-substrate diode (guard) to remove the diﬀusing substrate carriers (Fig. 4.7(b)). The p+ region is connected to the input of the TIA, while the n-well region is biased at a higher voltage Vb3 . In a 0.18 µm CMOS technology, this voltage should be limited to 1.8 V. A higher biasing voltage would generate a larger depletion region and a smaller junction capacitance, but is not applied for reliability reasons. The p-substrate is connected to ground. The TIA consists of a voltage ampliﬁer with inverter topology (nMOS transistor M1 and pMOS transistor M2 ) and a variable feedback resistance (resistor Rf b and pMOS transistor MRf b ). The diode-connected load used for instance in [Ing94, Ing99, Roo00] is omitted. The advantage is that the gain A0 is much higher, the disadvantage is that Rout is now completely determined by the output conductances of transistors M1 and M2 . These are susceptible to process variations, which can lead to stability problems. To avoid unstabilities during measurements, transistor M3 is added as load. It is biased in its linear region and can be switched on or oﬀ by changing the bias voltage Vb2 . Dummy stage M1d -M2d is added to create the same biasing conditions for transistor

4.5 Case Studies Vdd

Vb1

M2 nin

M2d

Vout M1

MRfb

Rfb nout

Vin

Vdd

Vb1

MRfb

83

M3 Vb2

M2

n1

nin

M2d

nout

Vin M1d

Rfb M3

Vout

Vb2

M1

C ac

n1

M1d

C ac

PD Vb3

PD

guard

(a)

(b)

Fig. 4.7. Schematic of the inverter-based 0.18 µm CMOS TIA: (a) conﬁguration for the classical n-well diode, quasi-fractal n-well diode, one half of the diﬀerential n-well diode and n+ p-substrate diode, (b) conﬁguration for the p+ n-well diode with guard.

Table 4.2. Design parameters of the inverter ampliﬁer and dummy stage.

type L W VDSAT IDS gm gds Cgs Cgd

M1

M2

M1d

M2d

nMOS 0.18 µm 40 µm 0.24 V 3.3 mA 15.7 mS 0.8 mS 47 fF 15 fF

pMOS 0.18 µm 60 µm −0.46 V −3.3 mA 10.3 mS 0.7 mS 75 fF 21 fF

nMOS 0.18 µm 4 µm 0.24 V 0.33 mA 1.57 mS 0.08 mS 4.7 fF 1.5 fF

pMOS 0.18 µm 6 µm −0.46 V −0.33 mA 1.03 mS 0.07 mS 7.5 fF 2.1 fF

M3 as for transistor Mrf b : equal drain and source voltages. It is a replica of inverter M1 -M2 , only the widths of the transistors are 10 times smaller to limit the power dissipation. Capacitor Cac is added to remove ac signals from node n1. The design parameters of the inverter ampliﬁer and dummy stage are summarized in Table 4.2. The hand calculations and simulation results for diﬀerent biasing conditions and diﬀerent photodiode topologies can be found in Table 4.3 and Table 4.4.

84

4 Transimpedance Ampliﬁer Design

DC Operating Point As no DC current ﬂows through Rf , MRf b or M3 , following equation should be fulﬁlled: (4.47) IDS,M1 = |IDS,M2 |. Using the current expressions for strong inversion [San06], this equation becomes: 2 Kn W L M1 (VGS − VT )M1 (1 + λn VDS )M1 = Kp W (|VGS | − |VT |)2M2 (1 + λp |VDS |)M2 . (4.48) L M2

W is the transistor width, L is the transistor length, VT is the threshold voltage, VGS the gate-source voltage, Kn and Kp are the transconductance parameters for an nMOS and pMOS transistor respectively, λn and λp are the channel length modulation parameters for an nMOS and pMOS transistor respectively. As a high bandwidth is required, the length of the transistors is chosen minimal (0.18 µm). Rearranging the terms in (4.48) shows that the DC input voltage VIN , which is the same as the DC output voltage VOUT , is completely determined by the ratio of the width of the transistors: Kp (VDD − VIN − |VT p |)2 (1 + λp (VDD − VIN )) WM1 . = WM2 Kn (VIN − VT n )2 (1 + λn VIN )

(4.49)

As VIN also determines the reverse bias voltage of the photodiode, it should be large to widen the depletion region and to reduce the photodiode junction capacitance. However, the width only changes with the square root of the voltage (3.22). When no ac coupling is used, the output voltage VOUT equals the input voltage of the next stage. Moreover, this voltage determines the dynamic range for the TIA. A signal current from the photodiode ﬂows through Rf and increases the output voltage. Very large signals would steer transistor M2 into its linear region, resulting in a corrupted eye diagram. As the currents generated by the integrated diodes are very small, large output voltages almost never occur. In the presented design, the ratio WM1 /WM2 equals 2/3 (Table 4.2), resulting in a simulated VIN = VOUT = 0.8 V. Transimpedance Gain and Bandwidth To increase the ﬂexibility of the TIA, a variable transimpedance gain is implemented. This is realized with a ﬁxed resistor Rf b , in parallel with a pMOS transistor MRf b biased in its linear region. The advantage of using a ﬁxed resistor is that high-ohmic polysilicon can be used, with a value of approximately 1000 Ω/square. As a result, only 2 squares are needed to realize a 2 kΩ resistor, resulting in a compact layout with small parasitic capacitance values. The 4 µm x 8 µm resistor has a 3-dB bandwidth of 28 GHz. Transistor MRf b

4.5 Case Studies Vb1

Vb1

M Rfb

nin

85

M Rfb

nout

A0

nin

PD

nout

A0 PD

(a)

(b)

Fig. 4.8. Implementation of the feedback resistor: (a) nMOS-type, (b) pMOS-type.

is turned on when the signal is strong enough to lower the gain, resulting in a higher bandwidth. The overall feedback value Rf is given by: Rf = Rf b //RMRf b ,

(4.50)

with:

RMRf b = μCox

W L

MRf b

1 (|VGS | − |VT | − |VDS |)MRf b

.

(4.51)

A ﬁrst design choice regarding the feedback transistor is the type of MOS transistor. Fig. 4.8 shows two possible implementations: nMOS-type and pMOS-type. For the nMOS, the source is connected to the input, the drain to the output, the gate to a bias voltage Vb1 (for instance Vdd ) and the bulk to ground. When the photodiode generates an input current, the output voltage rises. As a result, Vgs remains nearly constant, while Vds increases. For large signals, the transistor may go into saturation, which is undesirable. The pMOS on the other hand has its drain connected to the input and its source connected to the output. The bias voltage at the gate Vb1 is now for instance ground. When a signal is applied, the source voltage of the transistor increases. So any change in Vds is reﬂected in an equal change in Vgs and the transistor will stay in the linear region, even for large signals. Therefore, a pMOS-type implementation is chosen. Second, the bulk connection of the pMOS has to be set. As a pMOS transistor is realized in an n-well, the bulk can be connected either to the source or to Vdd . In [Ing04], the principles of dynamic signal compression when the bulk is connected to Vdd are explained using a diode-coupled ac model. However, due to the bulk-eﬀect, VT increases, resulting in a larger RMRf b for the same W/L ratio. In this design, the goal is to lower the resistance value of Rf b by switching on transistor MRf b in parallel. To cover a wide range of possible values (by changing Vb1 ), a low starting value when Vb1 = 0 V is

86

4 Transimpedance Ampliﬁer Design

preferred. When the bulk is connected to Vdd , a much larger transistor width W is needed to create the same resistance value, leading to higher capacitive parasitics and a lower TIA bandwidth. Moreover, the advantages of using dynamic signal compression are not so large as the input signal is usually very small and thus no compression is needed. Therefore, in this design, the bulk is simply connected to the source. The length is chosen minimal to minimize parasitic capacitances. The width equals 10 µm, which results in a simulated Rf that ranges from 589 Ω (Vb1 = 0 V) to 2000 Ω (Vb1 > 0.6 V). The output resistance of the voltage ampliﬁer is determined by the output conductances of transistors M1 and M2 , and the resistance value of M3 . Just like MRf b , this pMOS transistor is biased in its linear region, and the resistance value RM3 is given by a similar expression as (4.51). So the output resistance equals: 1 1 Rout = // //RM3 . (4.52) gds,M1 gds,M2 The voltage gain A0 is determined by: A0 = (gm,M1 + gm,M2 )Rout .

(4.53)

When transistor M3 is switched oﬀ, the output resistance is high, leading to a high gain, which is a nice goal in TIA design (Section 4.3.1). However, generally low output resistances are pursued to avoid output loading. In this design we will have to take the value of Rout into account, as it has the same order of magnitude as Rf . Also, because the output conductance of a transistor is susceptible to process variations, the actual value of Rout and A0 might diﬀer. Because the resistance value of a transistor in the linear region shows less deviations after processing, transistor M3 can be added. However, owing to the lower gain A0 , the TIA performance will be worse. For the transistor dimensions in Table 4.2 and WM3 = 20 µm, LM3 = 0.18 µm, the output resistance varies between 644 Ω (Vb2 > 0.6 V) and 253 Ω (Vb2 = 0 V) Table 4.3 summarizes the results of the main equations derived in Section 4.3 under four extreme biasing conditions. The input photodiode is a classical n-well diode. The transimpedance gain is slightly smaller than Rf due to Rout . The maximum value equals 65 dBΩ, while the minimum value equals 54 dBΩ. For the bandwidth, (4.11) gives a too optimistic result. Summing up Rout with Rf to calculate the dominant pole, which is justiﬁed by (4.4), gives a result which corresponds better with the simulation results. Dependent on the biasing conditions, the bandwidth ranges from 440 MHz up to 1.9 GHz. As expected, a smaller Rf results in a smaller transimpedance gain but a higher bandwidth. Lowering Rout leads to a smaller voltage gain and consequently also a smaller transimpedance bandwidth. The transimpedance-bandwidth product is the largest when Vb1 = Vb2 = 1.8 V and equals 1.1 THzΩ. Table 4.4 compares the results for diﬀerent diode topologies under a ﬁxed biasing condition (MRf b and M3 both oﬀ). The diﬀerent photodiode junction capacitances cause the bandwidth to vary from 166 MHz up to 910 MHz. The

4.5 Case Studies

87

transimpedance-bandwidth product is the largest (1.6 THzΩ) for the topology with the smallest photodiode capacitance, which is the diﬀerential diode. Open-Loop and Loop Gain As the assumption Rout Rf is not valid for the inverter topology, the equations regarding open-loop and loop gain are not very accurate. However, as can be seen in Table 4.3 and Table 4.4, the simulated unity-gain frequency of the loop gain f0dB,GH equals more or less the TIA bandwidth BWT IA . The DC loop gain is always smaller than A0 and is more accurately modeled by: GHT IA,0 =

A0 . 1 + RRout f

(4.54)

Table 4.3 shows that the phase margin is the smallest (99◦ ) when both MRf b and M3 are oﬀ. Switching on MRf b lowers Rf and results in a higher f0dB,GH , but also a higher dominant pole fd,GH (4.23). Because the ratio Rout /Rf becomes larger, the loop gain GHT IA,0 drops. The result is a slight increase in phase margin. M3 is added to compensate for uncertainties in the output conductances of the transistors, which might create an unstable TIA. The simulation results in Table 4.3 show that switching on this transistor increases the phase margin, so stability is ensured. Because Rout becomes smaller, f0dB,GH drops while the dominant pole of the loop gain fd,GH remains nearly constant and the non-dominant pole fnd,GH increases in frequency. The result is that the ratio fnd,GH /f0dB,GH becomes larger, thus creating a better phase margin (4.27). The simulation results in Table 4.4 show that the input photodiodes with the largest parasitic capacitance cause the smallest phase margin. The p+ n-well diode with guard has a P.M. of 71◦ . Switching on MRf b or M3 will increase this value. Noise Fig. 4.9 shows the photodiode model which is used for the noise simulations. It consists of the junction capacitance Cdio in parallel with a very large resistor Rp (≈ 1 TΩ) which models the dark current of the photodiode. When the diode is biased forward, 1/Rp equals the ac conductance. As stated in the Eldo Device Equations Manual [Men], resistor Rs is added in series ‘to include nonidealities’. The value is determined by the parasitic resistance of the anode (for instance the p-substrate), cathode (for instance the n-well), and contacts. It is inversely proportional to the area of the diode: the larger the photodiode area, the smaller the series resistance. While resistor Rp is noiseless, resistor Rs generates thermal noise, given by: di2Rs =

4kT df. Rs

(4.55)

88

4 Transimpedance Ampliﬁer Design anode

2

diR

Rs

s

2 didio

dv2n,TIA (dB/Hz) 4kTR2f Rs

C dio

cathode

shot noise Rs total

2qIdioR2f

Rp

4kT Rs R2f R2p

1 2π RpCdio

(a)

1 BWTIA 2πRsCdio

f (Hz)

(b)

Fig. 4.9. Noise of the photodiode: (a) Eldo diode model [Men], (b) power spectral density of the diode noise at the TIA output.

The noise of the junctions itself is represented by the shot noise current source di2dio (4.32). The spectral density of the noise at the output of the TIA due to the photodiode is given by: ZT2 IA,0 2 2 dvn,T 2 IA = didio 2 Rf Rout CinT CoutT (Rf +Rout )CinT CoutT + 1 +s + Rout s A0 +1 A0 +1 A0 +1 2 Rs Rf 2 Rp 1 + sRp Cdio 2 + diRs (4.56) 2 . Rs (Rout +Rf )Cin Cdio 2 (RC)noise s + s + 1 A0 +1 A0 +1 with: (RC)noise = (Rf + Rout + Rs (A0 + 1))Cdio + (Rf + Rout )Cin .

(4.57)

This equation is valid under following conditions: • The parallel resistance Rp is very large compared to all other resistance values. • The voltage gain A0 is large. • The output capacitance CoutT has been omitted for the transfer function of the Rs noise, to keep the equations as simple as possible. • Rs has been assumed suﬃciently low to neglect its eﬀect on the transimpedance gain (4.4) and consequently also on the transfer function of the diode shot noise. Notice that only the noise at the output of the TIA, originating from the photodiode is modeled here. The inﬂuence of the other noise sources is described in Section 4.3.3 and given by (4.34).

4.5 Case Studies

89

The output power spectral density of the noise due to shot noise and Rs noise of the photodiode is depicted in Fig 4.9(b). The DC values of these noise sources are normally much smaller than the DC value of (4.34) and thus not important at low frequencies. At high frequencies (around the TIA bandwidth), the noise of resistor Rs may become very large, and comparable to the noise of the feedback resistor Rf and the equivalent input transistor Mx . When Rs (A0 + 1) Rf + Rout (due to a high A0 and/or a large Rs ), the peak value of this noise power is given by: 4kT 2 R , Rs f

(4.58)

which is depicted in Fig 4.9(b). The maximum value of the noise power is thus proportional to Rf2 , and inversely proportional to Rs : the smaller Rs , the higher the noise contribution. However, for very small Rs , the assumption Rs (A0 + 1) Rf + Rout does not hold anymore, and the peak value is given by: R A 2 f 0 , (4.59) 4kT Rs Rf + Rout which is directly proportional to Rs . The simulated output power spectral densities for several cases are depicted in Fig. 4.10. The bias voltages are always Vb1 = 1.8 V and Vb2 = 1.8 V, except in Fig. 4.10(b), where Vb1 = 0 V and Vb2 = 0 V. When both MRf b and M3 are turned oﬀ, the noise of Rf b is dominant at DC (−165 dB/Hz). The DC value due to the photodiode shot noise cannot be seen in the graphs of Fig. 4.10 as the zero of (4.56) is as low as 30 kHz. This DC value is −240 dB/Hz, except in Fig. 4.10(b) where it equals −252 dB/Hz due to the smaller Rf . The noise density of M1 is always slightly larger than the noise density of M2 . The equivalent gmx,M1 for the noise contribution of M1 in (4.34) is given by: 1 gm,M1 = , gmx,M1 (gm,M1 + gm,M2 )2

(4.60)

and an analog expression holds for gm,M2 . Because gm,M1 > gm,M2 , the same is true for their noise contributions to the output. Comparing Fig. 4.10(a) and Fig. 4.10(b) shows the eﬀect on the noise performance when transistors MRf b and M3 are turned on. The noise of M3 can still be neglected, so is not depicted in the graphs. Due to the smaller feedback resistance value of MRf b , its noise becomes dominant over the noise of Rf b . Fig. 4.10(a), Fig. 4.10(c) and Fig. 4.10(d) compare the noise performance for the three n-well photodiodes: the classical, the quasi-fractal and (one half of) the diﬀerential photodiode respectively. The larger the diode area, the smaller Rs and the higher the maximum (4.58) of its noise curve. In Fig. 4.10(a), the noise of Rs becomes even larger than the noise of Rf b , while in Fig. 4.10(d), the noise curve of Rs stays well below the noise curve of Rf . Finally, Fig. 4.10(e) and Fig. 4.10(f) show the output noise spectral densities

90

4 Transimpedance Ampliﬁer Design −160 spectral noise density [dB/Hz]

spectral noise density [dB/Hz]

−160

−180

−200

total output noise noise Rf noise M1

−220

noise M

2

noise PD −240 6 10

7

10

8

9

10 10 frequency [Hz]

−180

f

noise M1 noise M2

−220

noise M

Rfb

noise PD −240 6 10

10

10

total output noise noise R

−200

7

10

(a)

spectral noise density [dB/Hz]

spectral noise density [dB/Hz]

−200

total output noise noise R f

noise M1

−220

noise M2 noise PD 7

10

8

9

10 10 frequency [Hz]

−180

−200

f

noise M1

−220

noise M2 noise PD

−240 6 10

10

10

total output noise noise R

7

10

(c)

8

9

10 10 frequency [Hz]

10

10

(d) −160 spectral noise density [dB/Hz]

−160 spectral noise density [dB/Hz]

10

10

−160

−180

−180

−200

total output noise noise R f

noise M1

−220

noise M2 noise PD

−240 6 10

9

(b)

−160

−240 6 10

8

10 10 frequency [Hz]

7

10

8

9

10 10 frequency [Hz]

(e)

10

10

−180

−200

total output noise noise R f

noise M1

−220

noise M2 noise PD

−240 6 10

7

10

8

9

10 10 frequency [Hz]

(f)

Fig. 4.10. Simulated output noise power spectral densities of: (a) TIA with classical n-well diode (Rf = 2000 Ω, Rs = 1200 Ω), (b) TIA with classical n-well diode (Rf = 589 Ω, Rs = 1200 Ω), (c) TIA with fractal n-well diode (Rf = 2000 Ω, Rs = 1600 Ω), (d) TIA with diﬀerential n-well diode (Rf = 2000 Ω, Rs = 3000 Ω), (e) TIA with p+ n-well diode with guard (Rf = 2000 Ω, Rs = 6 Ω) , (f) TIA with n+ p-substrate diode(Rf = 2000 Ω, Rs = 5 Ω) .

10

10

4.5 Case Studies

91

Table 4.3. Hand calculations (upper part) and simulation results (lower part) of the TIA with classical n-well diode under diﬀerent biasing conditions. Vb1

1.8 V

0V

1.8 V

0V

Vb2

1.8 V

1.8 V

0V

0V

Rout

644 Ω

644 Ω

253 Ω

253 Ω

A0

16.8

16.8

6.6

6.6

Cdio

660 fF

660 fF

660 fF

660 fF

Cin

760 fF

760 fF

395 fF

395 fF

CinT

1.42 pF

1.42 pF

1 pF

1 pF

Rf

2000 Ω

589 Ω

2000 Ω

589 Ω

A0 2πRf CinT A0 2π(Rf +Rout )CinT A0 Rf A0 +1 − AR0out +1

940 MHz

3.2 GHz

500 MHz

1.7 GHz

711 MHz

1.5 GHz

440 MHz

1.2 GHz

65 dBΩ

54 dBΩ

65 dBΩ

54 dBΩ

BWT IA

640 MHz

1.9 GHz

440 MHz

1.4 GHz

ZT IA,0

65 dBΩ

54 dBΩ

65 dBΩ

54 dBΩ

ZBW

1.1 THzΩ 952 GHzΩ 782 GHzΩ 702 GHzΩ

GT IA,0

88 dBΩ

73 dBΩ

84 dBΩ

70 dBΩ

GHT IA,0

22 dB

18 dB

18 dB

15 dB

f0dB,GH

692 MHz

2 GHz

510 MHz

1.6 GHz

P.M.

99◦

103◦

111◦

113◦

vn,T IA

222 µVrms 155 µVrms 169 µVrms 128 µVrms

in,tia

0.12 µArms 0.3 µArms 0.1 µArms 0.27 µArms

dominant noise source

PD

MRf b

Rf

MRf b

for the TIAs with the smallest bandwidth and largest photodiode capacitances at their input: the p+ n-well diode with guard, and the n+ p-substrate diode. These diodes also have a much smaller Rs value, so the maximum of its noise curve is given by (4.59) and never becomes dominant. Because the zero of the ampliﬁer noise (4.34) is well separated from the TIA bandwidth, the noise curves of transistors M1 and M2 can increase and even rise above the noise curve of resistor Rf at high frequencies. Table 4.3 and Table 4.4 summarize the results for the integrated output noise and the integrated input-referred noise current. Two times the TIA bandwidth is taken as the upper integration limit. Also the noise source with the largest contribution to the total integrated noise is mentioned. Table 4.3 shows that MRf b is the dominant noise source when turned on. Otherwise, the dominant noise source is Rf b (Vb2 = 0 V) or the photodiode (Vb2 = 1.8 V)

92

4 Transimpedance Ampliﬁer Design

Table 4.4. Hand calculations (upper part) and simulation results (lower part) of the TIA with diﬀerent photodiodes (Vb1 = 1.8 V, Vb2 = 1.8 V). quasi-fractal diﬀerential p+ n-well dio-

n+ p-sub-

n-well diode

diode

de with guard strate diode

Rout

644 Ω

644 Ω

644 Ω

644 Ω

A0

16.8

16.8

16.8

16.8

Cdio

585 fF

292 fF

4.6 pF

6.8 pF

Cin

760 fF

760 fF

760 fF

760 fF

CinT

1.34 pF

1.05 pF

5.3 pF

7.6 pF

Rf

2000 Ω

2000 Ω

2000 Ω

2000 Ω

A0 2πRf CinT A0 2π(Rf +Rout )CinT 0 − AR0out Rf AA +1 0 +1

993 MHz

1.3 GHz

248 MHz

175 MHz

751 MHz

960 MHz

188 MHz

132 MHz

65 dBΩ

65 dBΩ

65 dBΩ

65 dBΩ

BWT IA

741 MHz

910 MHz

230 MHz

166 MHz

ZT IA,0

65 dBΩ

65 dBΩ

65 dBΩ

54 dBΩ

ZBW

1.3 THzΩ

1.6 THzΩ

409 GHzΩ

295 GHzΩ

GT IA,0

88 dBΩ

88 dBΩ

88 dBΩ

88 dBΩ

GHT IA,0

22 dB

22 dB

22 dB

22 dB

f0dB,GH

759 MHz

851 MHz

155 MHz

117 MHz

P.M.

97◦

91◦

71◦

75◦

vn,T IA

224 µVrms

222 µVrms

140 µVrms

140 µVrms

in,T IA

0.12 µArms

0.12 µArms

0.08 µArms

0.08 µArms

dominant

Rf

Rf

Rf

M1

noise source

owing to the higher integration bandwidth. The table also shows that the input-referred noise is the smallest for the largest value of Rf . Comparing the noise for diﬀerent diodes at the input, Table 4.4 shows that the input noise of the TIA with p+ n-well diode with guard and TIA with n+ p-substrate diode is slightly smaller. This is because the integration bandwidth in these cases is considerably lower than for the TIAs with n-well diodes. The dominant noise source in case the n-well diodes are at the input is Rf . For the TIA with p+ n-well diode with guard, the noise contribution of M1 almost equals the noise contribution of Rf , but the latter is still dominant. When the n+ p-substrate diode is at the input, the noise of of M1 dominates all other noise sources. Finally note that no attempt has been made to minimize the integrated noise for a certain photodiode input capacitance as described in Section 4.3.3. The large variation in the photodiode capacitance values results in a ratio XN that

4.5 Case Studies

93

varies between 0.2 for the diﬀerential diode and 0.02 for the n+ p-substrate diode. However, the prime goal was to compare the speed performance of the diode topologies, by amplifying the signals with identical TIA conﬁgurations that have a larger bandwidth than the intrinsic bandwidth of the respective photodiodes. 4.5.2 An Inverter-Based TIA for Test Photodiodes in 90 nm CMOS Design Goals and Implementation The design of this TIA has a lot in common with the one described in the previous section (Section 4.5.1). Again the aim is to amplify the signal from diﬀerent types of photodiodes, comparing their speed performance. The major diﬀerence is that the design is done in a 90 nm CMOS process, with minimum eﬀective gate-length of 80 nm. This is reﬂected in a higher level of Eldo transistor model, namely level 54 or BSIM4. This model is an extension of the BSIM3 model (or Eldo level 53) and addresses the MOSFET physical eﬀects into the sub-100 nm regime. BSIM4 has as much as twenty improved and/or new models compared to BSIM3 [UC 04], of which only a few are: • an accurate new model of the intrinsic input resistance for both RF, highfrequency analog and high-speed digital applications; • a new accurate channel thermal noise model and a noise partition model for the induced gate noise; • an accurate gate direct tunneling model for multiple layer gate dielectrics; • a comprehensive and versatile geometry-dependent parasitics model for various source/drain connections and multi-ﬁnger devices; • improved model for steep vertical retrograde doping proﬁles. These highly accurate models need of course several new parameters to describe the physical phenomena due to downscaling. It is clear that the ‘intuitive’ square law for the saturation current given by: Ids = K

W (Vgs − VT )2 (1 + λVds ), L

(4.61)

becomes more and more out of date [San06]. However, it is still useful to perform raw hand-calculations. The schematic of the TIA, again with diﬀerent diode conﬁgurations, is depicted in Fig. 4.11(a) and Fig. 4.11(b). The test photodiode structures now are a classical n-well diode and a quasi-fractal n-well diode (Fig. 4.11(a)), and a p+ n-well diode with guard (Fig. 4.11(b)). In the latter case, besides the detecting diode PD, also a guard diode is present. The bias voltage of the nwell (Vb3 ) should stay below 1.1 V. Because no detailed junction capacitance models are available for this technology, approximate calculations are performed to determine the total junction capacitance, including bottom-plate

94

4 Transimpedance Ampliﬁer Design Vdd

Vdd

Vb1

Vb1

MRfb

M2

Rfb

nin

M2

nout

Vin M1

MRfb

Vb2

Vout

PD

nin

nout

Vin M3

M1 C ac

Rfb

Vb2

PD Vb3

Vout

M3 C ac

guard

(a)

(b)

Fig. 4.11. Schematic of the inverter-based 90 nm CMOS TIA: (a) conﬁguration for the classical n-well diode and quasi-fractal n-well diode (b) conﬁguration for the p+ n-well diode with guard.

as well as sidewall capacitance. For the classical n-well diode, Cdio ≈ 1.4 pF, for the quasi-fractal n-well diode, Cdio ≈ 1.6 pF, and for the p+ n-well diode with guard, Cdio ≈ 6 pF. The TIA consists again of a single-stage inverter ampliﬁer (nMOS transistor M1 and pMOS transistor M2 ) and a variable feedback resistance (resistor Rf b and pMOS transistor MRf b ). The main diﬀerence with the previous design is that the dummy stage is left out. Transistor M3 operates in the linear region, and can be turned on or oﬀ by changing the bias voltage Vb2 . To have drain and source of transistor M3 biased at the same DC voltage, capacitance Cac is added, which prevents DC current from ﬂowing through M3 . The function of transistor M3 remains the same: taking care of stability problems due to process variations on output conductances gds,M1 and gds,M2 . The same TIA structure with input inductor is presented in [Ler04]. Due to the series inductor between the diode and the TIA, the bandwidth BWT IA is decoupled from the unity-gain frequency f0dB,GH of the loop gain. This way a TIA can be realized with the same gain and bandwidth compared to the regular TIA in Fig. 4.11(a), but with a smaller input-referred noise current. The detailed analysis falls beyond the scope of this text, but the interested reader is referred to [Ler04]. The design parameters of the inverter ampliﬁer are summarized in Table 4.5. The main simulation results for an ‘average’ 1.5 pF photodiode are given in Table 4.6. Because of the high resemblance with the previous TIA,

4.5 Case Studies

95

Table 4.5. Design parameters of the inverter ampliﬁer.

type L W VDSAT IDS gm gds Cgs Cgd

M1

M2

nMOS 80 nm 100 µm 0.09 V 3.8 mA 44 mS 3.5 mS 34 fF 10 fF

pMOS 80 nm 300 µm −0.12 V −3.8 mA 46 mS 3.9 mS 103 fF 36 fF

no exhaustive overview is given anymore, but only the main design issues are discussed brieﬂy. DC Operating Point As M1 and M2 are the only transistors delivering DC current, both currents should be equal: IDS,M1 = |IDS,M2 |. (4.62) Assuming the square law is still valid for the 80 nm-channel transistors in strong inversion, (4.49) gives the relationship between the widths of the transistors and the DC input voltage. Note that VDD is now only 1.1 V. In the presented design, the ratio WM1 /WM2 equals 1/3 (Table 4.5), leading to a simulated VIN = VOUT = 0.49 V. Transimpedance Gain and Bandwidth The transimpedance gain is made variable in the same way and for the same reason as in Section 4.5.1: to increase ﬂexibility when diﬀerent types of photodiodes detect light at the input. For the implementation of the ﬁxed 2700 Ω resistance, salicided p+ polysilicon is used. Due to a compact layout of 1 µm x 9 µm, the RC-constant of the resistor results in a bandwidth as high as 80 GHz. The variable resistance is realized as a pMOS transistor, with bulk connected to source. Its resistance value is given by (4.51). MRf b has minimal length and a width of 70 µm, so the resulting Rf , which is the parallel combination of Rf b and MRf b , ranges from 120 Ω to 2700 Ω. The nominal design value, resulting in a bandwidth of 500 MHz, is 680 Ω (Table 4.6). This corresponds to a transimpedance-bandwidth product of 340 GHzΩ. This value is considerably smaller than the transimpedance-bandwidth product of the inverter-based design in 0.18 µm CMOS (Section 4.5.1). As ZBW is inversely

96

4 Transimpedance Ampliﬁer Design

proportional to the input capacitance (4.19), this decrease is mainly due to the larger junction photodiode capacitance associated with deep-submicron CMOS technologies. Due to the ac-coupling capacitor Cac , the output resistor at DC is ﬁxed and determined by the output conductances of the transistors: Rout =

1 . gds,M1 + gds,M2

(4.63)

Only at higher frequencies, determined by RM3 and Cac , the resistance value of RM3 (4.51) is seen at the output, in parallel with gds,M1 and gds,M2 : Rout,ac =

1 1 // //RM3 . gds,M1 gds,M2

(4.64)

The advantage of this approach is that the DC voltage gain is now also independent of RM3 . It is given by: A0 = (gm,M1 + gm,M2 )Rout ,

(4.65)

A0,ac = (gm,M1 + gm,M2 )Rout,ac

(4.66)

while: is the gain when Cac acts as a short circuit. The possible pitfall is that Cac must be high enough to enable the reduction of the output resistance by RM3 for the frequencies of interest. The implementation of this large capacitance value in a CMOS technology requires a capacitor with a high density per unit area to limit the (expensive) area. As no MIM-capacitors are available, a metal wall capacitance structure is used [Yao04]. It uses the lateral capacitance instead of the vertical capacitance normally used. In deep-submicron technologies, the lateral spaces between metal lines in the same layer are smaller than the vertical spaces between layers, leading to a higher capacitance density. Also the lateral spacing is better controlled. The calculated capacitance per unit area is around 1.7 fF/µm2 , enabling a Cac ≈ 13 pF within the restricted area. Table 4.6 summarizes the maximum, minimum, and nominal values of Rout,ac and the corresponding A0,ac . Open-Loop and Loop Gain The behavior of open-loop gain and loop gain is the same as the behavior of A0 . At DC, they do not change when M3 is turned on or oﬀ. At higher frequencies (dependent on the value of Cac ), the inﬂuence of M3 will become more important. When instabilities occur it allows to decrease Rout and reduce the loop gain at these frequencies, in order to adjust the phase margin and maintain stability. This might be necessary because the output conductances of the transistors, which determine Rout , are subject to process variations. Table 4.6 shows that the simulated unity-gain frequency f0dB,GH equals the TIA bandwidth BWT IA . The phase margin for a photodiode capacitance of 1.5 pF equals 75◦ .

4.5 Case Studies

97

Table 4.6. Simulation results of the TIA with n-well photodiode for which Cdio = 1.5 pF. Rf b

2700 Ω

min-max 120 Ω-2700 Ω nominally 680 Ω

Rf

Rout Rout,ac

min-max 60 Ω-130 Ω nominally 90 Ω A0

A0,ac

130 Ω

11.22

min-max 15 dB-21 dB nominally 18 dB

BWT IA ZT IA,0 ZBW

500 MHz 57 dBΩ 340 GHzΩ

f0dB,GH P.M.

500 MHz 75◦

in,T IA

0.21 µArms

Noise As no detailed model is available for the junction capacitances, an estimated value of 10 Ω is taken for Rs (Fig. 4.9(a)). The noise of this resistor will never become larger than the noise of the feedback resistor Rf or input transistors M1 and M2 . Table 4.6 reveals that the input-referred integrated noise current in,T IA equals 0.21 μArms . Assuming the noise models of Section 4.3.3 are valid, Rf is the dominant noise source. 4.5.3 A Diﬀerential Bandwidth-Optimized TIA in 0.18 µm CMOS Design Goals and Implementation This TIA diﬀers in two major ways from the previous designs discussed in Section 4.5.1 and Section 4.5.2. First, it is optimized for one particular photodiode: the diﬀerential photodiode for which the dark and illuminated junctions both have a junction capacitance of 159 fF respectively. Second, the topology is totally diﬀerent: a diﬀerential common-source structure is implemented, and the voltage ampliﬁer consists of two stages. A diﬀerential ampliﬁer is actually a very natural choice in combination with the diﬀerential photodiode topology: the illuminated junctions are connected to one input while the dark junctions are connected to the other input. Note however that the input

98

4 Transimpedance Ampliﬁer Design Rf

PD PD Rf Vdd M 2a

M 2b

nout a nin a

M 1a

Vout

nout b

M 1b

nin b

ICS

Fig. 4.12. Schematic of the diﬀerential 0.18 µm TIA.

current is not truly diﬀerential: the current from the illuminated junctions consists of a drift and diﬀusion component, while the current from the dark junctions only consists of the diﬀusion component. After this diﬀerential TIA stage, the diﬀerence signal consisting only of the drift component still has to be constructed. The presented TIA is part of an optical receiver which has the ultimate goal to receive and amplify signals with bitrates as high as a few Gbit/s. The other building blocks of this receiver, together with the measurements, will be discussed in Section 6.4. Fig. 4.12 shows the circuit schematic of the diﬀerential TIA. A beneﬁt of a diﬀerential topology is that the number of stages in an ampliﬁer is not limited to an odd number. As a compromise between high bandwidth (one single-ended stage for stability reasons) and high voltage gain (three singleended stages to increase ampliﬁcation), this TIA consists of two diﬀerential amplifying stages with cross-coupled feedback. Each stage consists of the input nMOS transistors M1a -MM1b and the pMOS load transistors M2a -M2b . These transistors are biased in the linear region by connecting their gates to ground. The feedback resistor has as ﬁxed value. As a compromise between

4.5 Case Studies

99

Table 4.7. Design parameters of the two diﬀerential stages. ﬁrst stage

type L W VDSAT IDS gm gds Cgs Cgd

second stage

M1

M2

M1

M2

nMOS 0.18 µm 34 µm 0.22 V 1.95 mA 11.9 mS 0.64 mS 41 fF 12 fF

pMOS 0.18 µm 12 µm −0.94 V −1.95 mA 1.25 mS 2.2 mS 14 fF 8 fF

nMOS 0.18 µm 13 µm 0.25 V 1.1 mA 5.2 mS 0.26 mS 16 fF 5 fF

pMOS 0.18 µm 8 µm −0.95 V −1.1 mA 0.68 mS 1.7 mS 9 fF 6 fF

gain and noise on one hand and bandwidth and phase margin on the other hand, the resistance equals 5000 Ω. The resistor is implemented in high-ohmic polysilicon, and with dimensions of 2 µm x 10 µm, its 3-dB bandwidth equals almost 20 GHz. Table 4.7 shows the transistor design parameters. It is apparent that the two stages are not identical. A more optimal solution is to have a large ﬁrst stage and a smaller second stage. The hand calculations and simulations results are summarized in Table 4.8. DC Operating Point The DC current through the transistors is set by the common-mode current source ICS . Each branch carries one half of its DC current. Owing to the feedback resistor Rf , which does not carry any DC current, the input DC voltage VIN of the TIA is the same as the output DC voltage VOUT . It is determined by: ICS2 RM2 , (4.67) VOUT = VDD − 2 where ICS2 is the DC current in the second stage of the ampliﬁer and RM2 is the resistance value of M2 in the second stage, and given by (4.51). The higher WM2 , the lower RM2 and the higher VOUT . The input voltage is given by: (4.68) VIN = VGS,M1 + VDS,CS1 , where VDS,CS1 is the drain-source voltage of the transistor constituting the current source in the ﬁrst stage. Any change in WM1 will be reﬂected in a change of VGS,M1 when the current is kept constant. However, the current source will adjust its drain-source voltage VDS,CS1 such that VIN still equals VOUT given by (4.67).

100

4 Transimpedance Ampliﬁer Design

In the presented design, the simulated VIN = VOUT = 1.3 V. This is somewhat higher than the DC voltage in the designs of Section 4.5.1 and Section 4.5.2, where one half of the power supply is taken as guideline. As the signal current from the photodiode is so small, large-signal problems with the output swing will never occur. A higher DC voltage has the advantage that the input photodiode capacitance is lowered. The intermediate voltage in between the two stages equals 1.2 V. Transimpedance Gain and Bandwidth The transimpedance gain of this TIA is ﬁxed and determined by the value of Rf , which is 5000 Ω. Due to the loading of Rout , the gain is somewhat lower and equals 4566 Ω or 73 dBΩ (Table 4.8). The voltage gain is maximized by implementing two stages. The total gain A0,tot is than given by: A0,tot = A0,1 · A0,2 , (4.69) with A0,1 and A0,2 the voltage gain of respectively the ﬁrst and the second stage. Their values are determined by: A0 = gm,M1 Rout , while: Rout =

1 //RM2 . gds,M1

(4.70)

(4.71)

As explained several times in this chapter, a large voltage gain is important to achieve a maximization of the TIA bandwidth, in ﬁrst order given by (4.11). The optimization process shows that the two stages shouldn’t be identical. The ﬁrst stage can be made larger: as long as the input capacitance is small enough compared to the photodiode capacitance, the voltage gain increases with gm,M1 and so does the bandwidth. The optimum is reached when increasing WM1 results in a lower bandwidth due to the larger input capacitance and decreasing WM1 results in a lower bandwidth due to a lower voltage gain A0 . The second stage still gives some additional voltage gain, but cannot be made too large as it determines the dominant pole of the voltage ampliﬁer, and thus also the stability of the TIA. Table 4.8 shows a large discrepancy between expression (4.11) and the simulated 3-dB bandwidth. This is because the poles of the TIA are complex conjugated and cause some gain peaking. So the actual bandwidth equals 4.3 GHz, which is larger than the value predicted by (4.11). Together with a gain of 73 dBΩ, this results in a transimpedance-bandwidth product of 19 THzΩ. This is more than one order of magnitude larger than the transimpedance-bandwidth product of the designs discussed in Section 4.5.1 and Section 4.5.2.

4.5 Case Studies

101

Open-Loop and Loop Gain The frequency at which the gain margin in measured, f0dB,GH , equals 2.3 GHz, signiﬁcantly smaller than the simulated BWT IA . The phase margin is 69◦ . Any change in values which increases the TIA bandwidth will result in a smaller phase margin. For example, a larger WM1 in the second stage will increase A0 and consequently also BWT IA . But also the loop gain GHT IA,0 increases, which results in a lower phase margin. Decreasing Rf to extend the bandwidth not only results in a worse noise performance, but also increases f0dB,GH and lowers the phase margin. So allowing suﬃcient phase margin for stable operation, this TIA is truly optimized with respect to bandwidth. Noise The simulated output noise power spectral density for the several noise sources is depicted in Fig. 4.13. At low frequencies, the feedback resistor Rf is clearly the dominant noise source. At higher frequencies, the noise of the series resistance Rs of the photodiode comes into play. Both contributions to the integrated output noise are equivalent: 0.57 mVrms comes from the photodiode and 0.56 mVrms comes from Rf . The transistor noise of the second stage can be neglected, as it is suppressed by the gain of the ﬁrst stage. The noise of the transistors of the ﬁrst stage never becomes dominant for the frequencies of interest. The DC value of the transistor noise contribution is given by: 2 4kT A0,2 Rout,1 4kT γdf 4kT df + . (4.72) 4kT γgm,M1 + df ≈ 2 RM2 1 + A0,tot gm,M1 RM2 gm,M1 The noise of the linearly biased transistor M2 is determined by the thermal noise of its equivalent resistance value. As this term is considerably smaller than the ﬁrst term in (4.72) and provided that the gain A0,tot is large enough, the equivalent gmx as deﬁned in (4.34) of this two-stage diﬀerential TIA is simply given by the transconductance of the input transistor, gm,M1 . Note also that the optimum (4.44) for the input transistor is reached more or less: for αgd = 0.3, Mi = 5 (only the gain of the ﬁrst stage is important for the Miller eﬀect), fT /BWT IA = 10.7, γ = 1, A0 = 11.75 and FBW = 2, the optimum ratio between Cgs of the input transistor and he photodiode capacitance Cpd equals 0.33. In the presented design, this ratio equals 0.26, which is somewhat lower. However, this deviation is justiﬁed for following reasons: • In [Ing04] it is shown that the optimum is a very ﬂat optimum, so any deviation only leads to a small increase in noise. • A smaller input transistor lowers the current consumption for the same Vgs − VT . • Formula (4.44) is only an approximation, as it is derived for a single stage, single-ended TIA with common-source topology.

102

4 Transimpedance Ampliﬁer Design

spectral noise density [dB/Hz]

−150

−170

−190

total output noise noise R f

noise M1

−210

noise M

2

noise PD −230 6 10

7

10

8

9

10 10 frequency [Hz]

10

10

Fig. 4.13. Simulated output noise power spectral density of the diﬀerential TIA with photodiode. Table 4.8. Hand calculations (upper part) and simulation results (lower part) of the diﬀerential TIA with photodiode. Rout

ﬁrst stage

352 Ω

second stage

531 Ω

ﬁrst stage A0 second stage total

4.2 2.8 11.75

Cdio

159 fF

Cin

91 fF

CinT

250 fF

Rf

5000 Ω

A0 2πRf CinT

1.5 GHz

0 Rf AA 0 +1

−

Rout A0 +1

73 dBΩ

BWT IA

4.3 GHz

ZT IA,0

73 dBΩ

ZBW

19 THzΩ

GT IA,0

94 dBΩ

GHT IA,0

20 dBΩ

f0dB,GH

2.3 GHz

P.M.

69◦

vn,T IA

1.36 mVrms

in,T IA

0.29 µArms

4.6 Conclusions

103

Finally, the power spectral density of the total output noise is also plotted in Fig. 4.13. Note that for instance at low frequencies, the noise is 3 dB higher than the noise of the dominant noise source, Rf . This is due to the diﬀerential nature of the circuit, where every noise source appears twice and consequently also has to be counted twice.

4.6 Conclusions This chapter has covered an in-depth design analysis of the ﬁrst electrical circuit of the optical receiver: the transimpedance ampliﬁer. As a starting point, its main performance requirements have been deﬁned. The photodiode current must be converted into an output voltage with high transimpedance gain. The bandwidth of the TIA should be 0.7 times the required bitrate. The equivalent input-referred noise current must be as small as possible, while the overload current must be as large as possible to design a TIA with a large dynamic range. In this work, the focus lies on low-noise TIAs as the current produced by CMOS photodiodes is very small. The TIA with shunt-shunt feedback has been proposed as basic structure and its performance has been studied in detail. Small-signal analysis of the bandwidth reveals that allowing complex conjugated poles with a minimum amount of overshoot leads to an increase in bandwidth. This bandwidth is inversely proportional to the input capacitance (including the photodiode junction capacitance), inversely proportional to the feedback resistance, and directly proportional to the DC gain of the voltage ampliﬁer. The transimpedance gain is mainly determined by the feedback resistance. Consequently, to maximize the transimpedance-bandwidth product, the input capacitance must be small, while the voltage gain should be maximized. Design equations for the loop gain reveal that the ratio between the dominant pole of the voltage ampliﬁer and the unity-gain frequency of the loop gain must be high enough to have suﬃcient phase margin (for instance a ratio of 3 to have 72◦ phase margin). For a multiple-stage voltage ampliﬁer, this ratio even has to be larger. As a result, applications requiring a high bandwidth compared to the technology’s fT will have a single-stage topology rather than a threestage topology. The noise analysis shows that for designs aiming for a high bandwidth, the dominant noise contributor might be the feedback resistor Rf rather than the input transistor of the voltage ampliﬁer. The input-referred current noise spectrum is ﬂat at low frequencies and mainly determined by the noise current of Rf . At high frequencies, the noise spectrum rises with 20 dB/decade due to the ampliﬁer noise. Diﬀerent noise optimization techniques have been discussed which derive an optimal Cgs for the input stage of the voltage ampliﬁer. After the high-level analysis, several TIAs have been discussed at the transistor level. Two main topologies have been illustrated with some examples found in literature: the TIA with common source input stage and the TIA

104

4 Transimpedance Ampliﬁer Design

with regulated cascode input stage. Also three interesting TIA designs of the latest years at ISSCC have been considered. Finally, three TIAs implemented in standard CMOS technologies have been presented in this chapter. The ﬁrst TIA is based on a single-stage inverter ampliﬁer and used to compare the performance of diﬀerent types of 0.18 µm CMOS photodiodes. Precautions have been taken to guarantee stability under all circumstances. Depending on the photodiode capacitance, the bandwidth ranges from 166 MHz to 910 MHz with a gain of 65 dBΩ. The TIA with classical n-well diode has a transimpedance-bandwidth product of 1.1 THzΩ, while the TIA with diﬀerential diode has a transimpedance-bandwidth product of 1.6 THzΩ. Using the ISSCC designs of Section 4.4.3 as a bench-mark, these transimpedance-bandwidth product values are coming close to present stateof-the art. This design also reveals that at higher frequencies the noise of the photodiode series resistance might become important. The second design is also based on a single-stage inverter ampliﬁer, but now photodiodes implemented in a 90 nm technology are compared. With an n-well photodiode capacitance of 1.5 pF at the input, the TIA bandwidth equals 500 MHz. Having a gain of 57 dBΩ, this corresponds to a transimpedance-bandwidth product of 340 GHzΩ. The smaller transimpedance-bandwidth product is mainly due to the larger photodiode junction capacitances in nm-scale technologies. Also the voltage gain A0 does not change favorably with downscaling: in both designs, the TIA is based on an inverter ampliﬁer, where A0 is determined by the ratio of gm and gds . This comes down to a voltage gain that is directly proportional to the product of Early voltage and channel length, and inversely proportional to VGS − VT . As demonstrated by this example, deep submicron CMOS technologies only provide very limited gain. Just this high voltage gain is needed in a TIA to achieve a large bandwidth and a high transimpedance-bandwidth product. Moving to newer technologies with higher fT ’s, a diﬀerent approach should be adopted. In a design for a certain bitrate and consequently a constant bandwidth, the fT /BWT IA ratio increases with downscaling. As explained in Section 4.3.2, a multi-stage approach can now be used to increase the voltage gain, because there is enough room now to place the extra poles. The optimal ratio for minimum noise XN,opt (Cgs,opt /Cdio ), derived in Section 4.3.3, will decrease for increasing fT /BWT IA . However, this will not result in a lower current consumption, as the rise of Cdio will be much higher, requesting higher transistor widths for minimal noise and maximal bandwidth performance. The last TIA is part of a complete optical front-end receiver implemented in 0.18 µm CMOS. A diﬀerential photodiode is used to detect the light signals, which are further ampliﬁed by a diﬀerential TIA. It comprises a two-stage voltage ampliﬁer with cross-coupled feedback. A bandwidth of 4.3 GHz and a transimpedance gain of 73 dBΩ result in a transimpedance-bandwidth product of 19 THzΩ. Implementing a two-stage voltage ampliﬁer and allowing some gain peaking with complex conjugated poles, results in a TIA with large bandwidth, but with suﬃcient phase margin and low noise performance. The power

4.6 Conclusions

105

dissipation of the core circuit, without biasing, equals 11.3 mW. These results are really competitive with present state-of-the-art (Section 4.4.3), combining a transimpedance-bandwidth product of several tens of THzΩ with a bandwidth of a few GHz. Furthermore, the TIA is designed in a fully standard CMOS technology with a minimal gate-length of only 0.18 µm and a fully integrated photodiode at its input. The measurement results of all described TIAs will be revealed in Chapter 6.

5 Post-Ampliﬁer Design

5.1 Introduction The purpose of the post-ampliﬁer (PA) is to amplify the relatively small signal from the transimpedance ampliﬁer (TIA) to a level suﬃcient for reliable operation of the clock and data recovery circuit (see also Fig. 2.1). The required swing at the output of the PA is typically several 100 mV peak-to-peak. Two types of PAs can be distinguished: the limiting ampliﬁer (LA) and the automatic gain control (AGC) ampliﬁer. An LA is an ampliﬁer with no special measures to prevent the output signal from clipping or limiting. For very small input signals, the ampliﬁer operates in the linear regime, and the output voltage is proportional to the input voltage. For larger signals, clipping occurs and the output voltage remains constant. An AGC ampliﬁer consists of a variable gain ampliﬁer and an automatic gain control mechanism that keeps the output swing constant over a wide range of input swings. Whereas the LA starts to distort for large input signals, the AGC ampliﬁer reduces its gain and thus manages to stay in the linear regime. Which PA should be used, depends on whether the application allows nonlinear distortion or not. The LA is generally easier to design and its performance is often superior to an AGC ampliﬁer realized in the same technology. On the other hand, the linear transfer function of the AGC ampliﬁer preserves the signal waveform and permits analog signal processing of the output signal. The LA severely distorts the input signal when operating in the limiting regime, causing much of the information in the input to be lost. This chapter deals with the design of the LA. For further information regarding AGC ampliﬁers for optical communication circuits, the reader is referred to [Rei89, M¨ol94, Wu04, S¨ ac05, Lia06]. Section 5.2 discusses the main LA speciﬁcations, of which the most important are a high gain and a high bandwidth. Next, some recently published LAs are summarized in Section 5.3, together with a short history of the Cherry-Hooper topology. The design of a fully diﬀerential LA is addressed in Section 5.4. The optimal number of gain stages for maximal gain-bandwidth is calculated. Design equations for the CMOS Cherry-Hooper stage and the 107

108

5 Post-Ampliﬁer Design vout,p

vin,p vin

vout

vin,n

vout,n

Fig. 5.1. Input and output signals of a fully diﬀerential post-ampliﬁer (PA).

capacitive source degenerated stage are derived. Also a basic oﬀset compensation scheme is proposed. Finally, Section 5.5 presents two diﬀerent case studies which analyze the design of respectively a four-stage LA and ﬁve-stage LA with oﬀset compensation in 0.18 µm CMOS.

5.2 Performance Requirements While the TIA speciﬁcations determine the primary performance of the optical receiver, such as the sensitivity and the overload limit, the PA speciﬁcations have less impact. However, insuﬃcient PA speciﬁcations may degrade the overall receiver performance. This section deﬁnes the main PA requirements regarding gain, bandwidth, noise, input dynamic range, input oﬀset voltage, input capacitance and jitter. Gain Figure 5.1 shows a fully diﬀerential PA together with its input and output voltages. The diﬀerential input voltage vin is the diﬀerence between the two single-ended input voltages vin,p and vin,n . Similarly, the diﬀerential output voltage vout is the diﬀerence between the two single-ended output voltages vout,p and vout,n . The voltage gain of the PA, AP A , is deﬁned as the ratio of the small-signal diﬀerential output voltage to the small-signal diﬀerential input voltage: AP A =

vout = |AP A (f )|ejθ(f ) . vin

(5.1)

The higher this value, the more output signal is produced for a given input signal. The gain is speciﬁed either on a linear scale or in dB. The gain is a complex quantity, with frequency-dependent magnitude |A(f )| and frequencydependent phase-shift θ(f ). The mid-band gain is usually ﬂat, and represented by AP A,0 . For ampliﬁers with diﬀerential outputs, the gain can be measured single-endedly (vout,p or vout,n ) or diﬀerentially (vout = vout,p − vout,n ). It is important to specify in which way the gain is measured, as the diﬀerential gain is 6 dB higher than the single-ended gain.

5.2 Performance Requirements

109

Bandwidth The upper frequency at which the small-signal gain has dropped 3 dB below its mid-band value, is deﬁned as the PA bandwidth, BWP A . The deﬁnition for bandwidth is based on the assumption that the ampliﬁer operates in its linear regime: when a sine wave is applied at the input, the ampliﬁer produces a sine wave at the output. For a LA, this is not always the case, certainly not in the last stages of the amplifying chain where clipping of the signal occurs. Then the concept of bandwidth no longer applies and must be replaced by a large-signal concept such as the switching speed. However, it is always possible to reduce the input signal amplitude to the point where the LA enter the linear regime. The small-signal bandwidth also tends to be a conservative estimate for the large-signal speed of the ampliﬁer. Remember from Section 4.2 that the bandwidth of a TIA is set to approximately 0.7 times the bitrate Rb to limit the noise. Limiting ampliﬁers on the other hand have a much larger bandwidth, usually equal to the bitrate Rb [Raz03, S¨ ac05]. Noise The noise generated by the LA adds to the total optical receiver noise and thus degrades the receiver sensitivity. The overall integrated equivalent inputreferred noise current of the optical receiver i2n,OR can be expressed as: i2n,OR = i2n,T IA +

2 vn,LA . ZT2 IA,0

(5.2)

i2n,T IA is the integrated input-referred noise current of the TIA (4.3). The 2 is the integrated equivalent noise voltage at the input of same way, vn,LA the LA. Referred to the input of the optical receiver, it is divided by the transimpedance gain. For a receiver sensitivity predominantly determined by the noise of the TIA, the second term in (5.2) must be as small as possible. This becomes more critical for the following reasons: • The large bandwidth required for the post-ampliﬁer yields a greater total integrated noise. • The design of TIAs with a high transimpedance gain becomes increasingly more diﬃcult at high speeds, making the noise of the post-ampliﬁer more signiﬁcant. Input Dynamic Range The input dynamic range of the LA describes the minimum and maximum input signal for which the LA performs a useful function, in other words for which the BER is suﬃciently low. The minimum input signal is determined

110

5 Post-Ampliﬁer Design

by the sensitivity of the LA. Similar to the receiver sensitivity deﬁned in Section 2.4.2, it is the minimum peak-to-peak signal voltage at the input of the LA necessary to achieve a speciﬁed BER. The maximum input signal swing is reached when the LA produces so much pulse-width distortion and jitter that the speciﬁed BER cannot be maintained. Input Oﬀset Voltage The input oﬀset voltage, Vos , is the diﬀerential input voltage for which the diﬀerential output voltage of the PA becomes zero. Even a small input oﬀset voltage may drive the last stages of the LA in saturation. For this reason, limiting ampliﬁer usually incorporate oﬀset compensation. Input Capacitance The LA must exhibit a suﬃciently low input capacitance so that it does not reduce the TIA bandwidth signiﬁcantly. Therefore, the input transistors should be small, but this will lead to a smaller gain for the ﬁrst stage. Jitter LAs may introduce jitter in the signal. It is desirable to maintain this jitter below a few percent of the bit period.

5.3 Literature Examples A cascade of simple resistively-loaded diﬀerential pairs often proves inadequate as broadband ampliﬁer, especially if the input amplitude is small and the ﬁrst stages operate linearly. This is mainly due to the limited fT of today’s mainstream CMOS technologies. Dedicated technologies such as GaAs or SiGe have a much higher fT , making it possible to design high-speed ampliﬁers with basic diﬀerential amplifying stages [Max05]. This section gives a survey of the gain-bandwidth extension techniques used in the design of broadband LAs. Because interest in broadband ampliﬁers has always been high, some of the circuits discussed already date from the 60’s. A common way to increase bandwidth is to use inductive peaking. An integrated passive inductor is placed in series with the load resistor at the dominant node. The capacitance which limits the bandwidth at this node will resonate with the inductor. This results in a transfer function with a resonance peak around the former 3-dB frequency and an extension of the bandwidth. The resonance must occur with minimal peaking and overshoot to provide a well-behaved response to random data with small BER. Major disadvantage of this approach is the large chip area required by the integrated inductors.

5.3 Literature Examples

111

Furthermore, accurate modeling of the electro-magnetic ﬁeld is needed to characterize the inductors with their parasitics and to predict the overall circuit performance. This approach has lead to a successful LA implementation in [Gal03]. The proposed LA consists of a broadband input-matching network, ﬁve identical gain stages comprising the LA core, an oﬀset cancellation feedback loop and an output buﬀer. Besides inductive peaking, other techniques which are used to improve the gain-bandwidth of the gain stages are active feedback and a negative Miller capacitance. This way, a 3-dB bandwidth of 9.4 GHz has been realized with an overall diﬀerential gain of 50 dB. The sensitivity is 4.6 mVpp at 10 Gbit/s for a BER of 10−12 . The power dissipation of the core ampliﬁer is 100 mW, while the buﬀer consumes 30 mW. Total power consumption of the complete chip equals 150 mW from a 1.8 V power supply. One year later, the same authors propose a 40 Gbit/s LA [Gal04]. A tripleresonance structure is introduced which adds an extra inductor between two inductively peaked gain stages. Five diﬀerential triple-resonance stages provide an overall diﬀerential gain of 15 dB. Measurements of the single-ended output eyes are shown for input levels of 20 mVpp , 50 mVpp and 100 mVpp . Comparing these eyes with the simulations, results in an estimated smallsignal bandwidth of 22 GHz. The circuit consumes 190 mW from a 2.2 V power supply. To circumvent the area problem of passive integrated inductors, active inductors can be used to create gain peaking, as in [S¨ac00]. The proposed LA consists of four inversely scaled gain stages and an output buﬀer. The ﬁrst stage is a common-gate diﬀerential pair, providing a low impedance input (50 Ω). The three following stages are common-source diﬀerential pairs, and the last stage is implemented as a source follower. All gain stages have active inductor loads consisting of an nMOS transistor operating in saturation and a gate resistor. The ampliﬁer is implemented in a standard 2.5 V 0.25 µm CMOS technology and consumes 53 mW. The diﬀerential gain equals 32 dB. With a bandwidth of 3 GHz, eye diagrams at 2.5 Gbit/s showing little ISI are measured. One reason for not using active inductors is that they need a bias voltage larger than Vdd to eliminate headroom diﬃculties. Furthermore, they are unfavorable for noise performance. The LAs presented in this work are based on the circuits ﬁrst introduced by Cherry and Hooper in the early 60’s. In [Che63], they describe a design technique for the design of broadband transistor video ampliﬁers. As the ampliﬁers in that era were realized with discrete components, emphasis lies on the fact that gain and bandwidth should be insensitive to transistor parameter variations. The technique is based on the use of impedance mismatch which occurs between stages having alternate series and shunt feedback. The seriesseries feedback stage in Fig. 5.2(a) has a high input and output impedance, whereas the shunt-shunt feedback stage in Fig. 5.2(b) has a low input and output impedance. In order to stabilize the transconductance of the seriesseries feedback ampliﬁer, RE should be large enough. The transconductance is than approximated by 1/RE . In order to stabilize the transresistance of

112

5 Post-Ampliﬁer Design

RL CF

Iout

RL Vout

Vin

RF

RE

(a)

CE

Iin

(b)

Fig. 5.2. Single-stage feedback ampliﬁers after Cherry and Hooper [Che63]: (a) series-series feedback stage, (b) shunt-shunt feedback stage.

a shunt-shunt feedback ampliﬁer, it is necessary to make RF /RL suﬃciently small, so that the transresistance is determined in ﬁrst order by RF . Due to the impedance mismatch between these stages, there is almost no interaction when they are cascaded. The overall gain may be calculated fairly accurately by simply multiplying the individual gain stages. When a series-series stage is followed by a shunt-shunt stage, the approximate voltage gain is thus RF /RE . By adding the high-frequency peaking components CE and CF , the authors show that the circuits are capable of reaching a gain-bandwidth product per stage equal to fT , which is the theoretical gain-bandwidth limit for an ideal transistor. In the 80’s and early 90’s, the techniques introduced by Cherry and Hooper have been adopted in the design of wideband ampliﬁers for optical communication networks [Fau83, Rei87, P¨ oh94]. The circuits are integrated in bipolar silicon technologies. The gain stage consists of a diﬀerential transadmittance stage (TAS) with series-series feedback, followed by a diﬀerential transimpedance stage (TIS) with shunt-shunt feedback, and usually two emitter followers. Sometimes the series feedback resistance RS is omitted. This is possible if the gain peaking introduced by RS and CS is not needed to achieve the required bandwidth. The major advantage is that the gain of the TASstage, which is determined by the gm of the input transistor, can be made larger now. This results in less stages for the overall LA. The 3-stage LA presented by [Fau83] is implemented in a 5 µm bipolar technology. The gain is 60 dB while the bandwidth equals 470 MHz. Four years later [Rei87] presents a 2 µm bipolar LA characterized by a gain of 54 dB and an operating speed of 4 Gbit/s. The LA consists of three equal gain stages, an output buﬀer, an emitter-follower input stage and oﬀset control. Finally, the authors of [P¨ oh94] use a 0.4 µm bipolar technology to implement a 10 Gbit/s LA with 45 dB gain. Also this ampliﬁer consists of three gain stages, an output buﬀer, an emitter-follower input stage and oﬀset control. The major high-level diﬀerence

5.4 Design of a Fully Diﬀerential Broadband LA

113

with [Rei87] is that the last gain stage is a distribution ampliﬁer, where each output of a series-series feedback stage drives two parallel feedback stages. This way, the signal is distributed to two diﬀerential outputs. However, the authors also report that the higher loading of the stage cause an increase in the jitter. To keep this jitter within acceptable limits, the gain of this last gain stage is reduced. So a doubling of the output pads comes at the expense of a lower gain, while no motivation is given in the paper for the need of two diﬀerential output signals. Almost ten years after the > 10 Gbit/s bipolar PAs [P¨ oh94, M¨ ol94], the ﬁrst Cherry-Hooper ampliﬁer implemented in a CMOS technology is presented by [Hol03]. A test circuit, implemented in a 0.35 µm CMOS technology has 9.4 dB gain and 880 MHz bandwidth. In addition, a six-stage 0.18 µm CMOS post-ampliﬁer using modiﬁed Cherry-Hooper stages is presented. It has 43 dB diﬀerential gain and 2.1 GHz bandwidth. Whereas the authors of [Hol03] have demonstrated the usefulness of Cherry-Hooper stages in CMOS, the goal of this work is to extend the achievable bitrates further in the Gbit/s range. Furthermore will the described LA be integrated with TIA and PD to present a single-chip solution for optical front-end receivers.

5.4 Design of a Fully Diﬀerential Broadband LA Most of today’s high-performance post-ampliﬁers employ a diﬀerential topology. The main advantage of diﬀerential operation over single-ended signaling is a higher immunity to environmental noise. Ground and power supply disturbances, originating for instance from the clock and data recovery circuit, will corrupt the signal lines, but the diﬀerential (output) signal will remain intact. So diﬀerential circuits are characterized by a high common-mode rejection ratio (the diﬀerential gain divided by the common-mode rejection, where common-mode rejection is deﬁned as the diﬀerential output voltage for a common-mode input voltage, when the diﬀerential input voltage is zero) and a high power supply rejection ratio (the gain from the input to the output divided by the gain from the power supply to the output). Diﬀerential lines are not only beneﬁcial for sensitive signals, but also for noisy signals. These are for instance present in the last stages of the LA, where the signals have an amplitude of a few 100 mV and change rapidly. Due to the diﬀerential nature of the ampliﬁer, the total current drawn from the power supply remains more or less constant, and alternates between the two branches of the diﬀerential stage. This way, the stage presents a constant load to the power supply, resulting in less noise generated in the power supply. On the other hand, due to a doubling of the devices in a diﬀerential circuit, the input noise √ voltage is always 2 larger than in a single-ended ampliﬁer. However, for the post-ampliﬁer, this drawback does not counterweigh the many advantages of a diﬀerential topology.

114

5 Post-Ampliﬁer Design

This section discusses the main topics related to the design of broadband limiting ampliﬁers. First, the eﬀect of cascading several amplifying stages is examined. Next, some broadband amplifying stages are studied, where the focus lies on combining both high bandwidth and high gain using analog circuit design techniques. Finally, a basic technique for oﬀset compensation is presented. 5.4.1 Cascaded Gain Stages As the broadband LA requires both high gain and high bandwidth, cascading several amplifying stages is required to achieve a high gain-bandwidth product. Assume N second-order stages are cascaded, the overall transfer function is given by: N A1st,0 AP A = , (5.3) ( ωsn )2 + 2ζ( ωsn ) + 1 where A1st,0 is the DC voltage gain for one single stage. So the more stages are cascaded, the higher the overall small-signal DC gain AP A,0 , as it equals: AP A,0 = AN 1st,0 .

(5.4) √ As already mentioned in Section 4.3.1, a second-order system with ζ = 2/2 has a maximally ﬂat response and corresponds to a second-order Butterworth ﬁlter. Also, it can be proven that for this type of ﬁlter ωn = ω3dB . Under these conditions, the overall bandwidth of a PA consisting of N cascaded second-order Butterworth stages is given by:

√ 4 N 2 − 1. (5.5) f3dB,P A = f3dB,1st So the higher N, the smaller the overall bandwidth f3dB,P A , or the higher the required bandwidth per stage f3dB,1st to attain a predetermined overall bandwidth. The gain-bandwidth extension of N cascaded stages compared to a single stage is:

√ GBWP A 1−1/N 4 N = AP A,0 2 − 1. (5.6) GBW1st This function increases for increasing N due to the rising gain when stages are added. However, owing to the smaller bandwidth with increase of N , the function saturates and reaches a maximum. The number of stages corresponding to this maximal GBWP A can be found using following approximation: 0.9 , f3dB,P A ≈ f3dB,1st √ 4 N

(5.7)

which is valid for large enough values of N . Using this approximation, (5.6) reduces to:

5.4 Design of a Fully Diﬀerential Broadband LA 30

PA

GBW /GBW

1st

25 20

115

APA,0=20 A

=40

A

=60

PA,0 PA,0

15 10 5 0 0

5

10 15 Number of stages N

20

Fig. 5.3. Gain-bandwidth extension as a function of the number of stages N in a post-ampliﬁer.

GBWP A AP A,0 0.9 √ . (5.8) ≈ N GBW1st AP A,0 4 N √ To minimize the denominator D = 4 N N AP A,0 , the natural logarithm is taken and diﬀerentiated with respect to N : 1 dD 1 1 = − 2 ln AP A,0 . D dN 4N N

(5.9)

This equation becomes zero for N = 4 ln AP A,0 . The gain-bandwidth extension given by (5.6) is plotted versus the number of stages N for three diﬀerent values of the overall gain AP A,0 in Fig. 5.3. The optimal N corresponding to a maximal GBW is quite high: for AP A,0 = 20, N = 12; for AP A,0 = 40, N = 14; for AP A,0 = 60, N = 16. However, the plot also reveals only an incremental change in GBWP A /GBW1st for values around the optimal N . For instance, when AP A,0 = 20 and as N goes from 5 to 12, the ratio GBWP A /GBW1st only increases by 11 %. Furthermore, when N is high, the gain per stage is small, making the noise contributed by all of the stages signiﬁcant. Finally, a lot of stages also corresponds to a high power dissipation and a large chip area. For these reasons, typical high-gain LAs employ no more than ﬁve stages. For example, assume a 3 GHz 30 dB PA has to be designed. Using second-order Butterworth stages, the optimal N is 14 and the corresponding gain-bandwidth extension GBWP A /GBW1st is 11.7. However, for the reasons mentioned above, some stages may be left out. For N = 4, the gain-bandwidth extension is still 8.8. Each stage needs a GBW1st of 11 GHz, which is realized with a gain of 7.5 dB and a bandwidth of 4.6 GHz.

116

5 Post-Ampliﬁer Design

5.4.2 Broadband Cherry-Hooper Stage Classical Cherry-Hooper Ampliﬁer As discussed in Section 5.3, a technique used for many years to enhance the bandwidth of a diﬀerential ampliﬁer is the Cherry-Hooper topology. A CMOS implementation is depicted in Fig. 5.4(a). Transistors M1 and M2 form the input pair, and resistor Rf provides feedback between the drain and gate of transistor M3 respectively M4 . Rd is the load resistor. Using the original terminology of Cherry, Hooper [Che63] and their followers, transistors M1 and M2 form a diﬀerential TAS-stage with transadmittance gain gm,M1 . M3 , M4 and Rf constitute a diﬀerential TIS-stage with shunt feedback and with transimpedance gain Rf . The small-signal half circuit is shown in Fig. 5.4(b). The output resistances of the transistors are usually larger than Rf and Rd , so they are omitted. The diﬀerential small-signal gain ACH of this stage is given by: C

ACH = ACH,0

gd,M 3 1 − s gm,M 3

R

f s2 gm,M C 2 + s(RC)CH + 1 3

,

(5.10)

with: ACH,0 = gm,M1 Rf , C 2 = C1 Cgd,M3 + C1 CL + Cgd,M3 CL , Rf + Rd CL (RC)CH = Rf Cgd,M3 + C1 + . Rd gm,M3 gm,M3

(5.11) (5.12) (5.13)

C1 is the total parasitic capacitance at node n1, Cgd,M3 is the gate-drain capacitance of transistor M3 and CL is the total capacitance at the output node n3. These equations are valid as long as gm,M3 Rf >> 1 and gm,M3 Rd >> 1. As expected, the small-signal gain of the Cherry-Hooper ampliﬁer at low frequencies (5.11) is given by the product of its transadmittance gain and its transimpedance gain. This product is comparable to the gain of a diﬀerential pair because the load resistor of a diﬀerential stage is of the same order of magnitude as the feedback resistor Rf . However, the bandwidth of this stage can be seriously extended. Assuming that the denominator of (5.10) shows two separated poles, the dominant pole is in ﬁrst order given by 1/(RC)CH . Mostly, Cgd,M3 is much smaller than C1 and CL , so the ﬁrst term in (5.13) can be neglected. If it further can be assumed that Rd >> Rf , the pole at node n1 equals gm3 /C1 , and the pole at node n3 is given by gm3 /CL . Which of these nodes determines the dominant pole depends on the relative values of C1 and CL . In any case, the resistance seen by the dominant pole is only 1/gm,M3 . In a simple diﬀerential stage, the dominant pole is determined by the load capacitance CL and the output resistance. The latter one is usually much larger than 1/gm3, resulting in a smaller bandwidth.

5.4 Design of a Fully Diﬀerential Broadband LA

117

Vdd Rd Rf

Rd

n3

Rf

n4

Vout1 Vout2 I2 n1

M3

M4

n2

I1

M c3 Vin1

M c4

M1

M2

Vin2

M c1

M c2

(a)

Rf

vout

n1

gm,M1 vin 2

2

n3

gm,M3 vgs,M3 C1 Cgd,M3

Rd

CL

(b) Fig. 5.4. CMOS Cherry-Hooper ampliﬁer stage: (a) schematic, (b) small-signal half circuit.

If the design goal of this stage is to optimize bandwidth, the poles will not be separated, but complex conjugated. However, the above reasoning is very valuable for gaining insight in the major advantages of the Cherry-Hooper topology. Gain-bandwidth of the stage is enlarged by moving the poles towards higher frequencies, without the penalty of loosing signiﬁcant gain. Modiﬁed Cherry-Hooper Ampliﬁer One can even go a step further in improving the performance by raising the gain, without a corresponding decrease in bandwidth. This is realized by the

118

5 Post-Ampliﬁer Design Vdd R1 M5 n5

R1

n3b

n4b

R2

R2

n3

Rf

n6

I2

n4

Vout1 Vout2 M3

n1

M6

Rf

M4

n2

I1

M c3 Vin1

M c4

M1

M2

Vin2

M c1

M c2

(a)

Cgd,M3 n1

v gm,M1 in 2

Rf C1

n5

n3

gm,M5 vgs,M5

gm,M3 vgs,M3

vout 2 R2 CL

n3b

R1

(b) Fig. 5.5. Modiﬁed CMOS Cherry-Hooper ampliﬁer stage: (a) schematic, (b) smallsignal half circuit.

modiﬁed Cherry-Hooper ampliﬁer, depicted in Fig. 5.5(a). This stage was ﬁrst introduced in CMOS by [Hol03]. Compared to a traditional Cherry-Hooper stage, resistor Rd is split up in two resistors R1 and R2 , and transistors M5 -M6 provide source follower feedback. The small-signal half circuit is shown in Fig. 5.5(b), where again the output resistances of the transistors are left out. The diﬀerential small-signal gain AMCH is now given by: C

AMCH = AMCH,0

gd,M 3 1 − s gm,M 3

s2 (RC)2MCH + s(RC)MCH + 1

,

(5.14)

5.4 Design of a Fully Diﬀerential Broadband LA

119

with: AMCH,0 = gm,M1 Rf fMCH , R2 , fMCH = 1 + R1 AMCH,0 C 2, (RC)2MCH = gm,M1 gm,M3

(5.15)

C 2 = C1 Cgd,M3 + C1 CL + Cgd,M3 CL , Rf fMCH (RC)MCH = Rf Cgd,M3 fMCH + C1 + CL . R1 gm,M3 gm,M3

(5.18)

(5.16) (5.17)

(5.19)

Again, C1 is the total parasitic capacitance at node n1, Cgd,M3 is the gatedrain capacitance of transistor M3 and CL is the total capacitance at the output node n3. This time, the equations are valid as long as gm,M5 Rf >> 1 and gm,M3 R1 >> 1. By comparing (5.11) and (5.15), one can see that the gain at low frequencies is raised in the modiﬁed topology with the factor fMCH . This factor is mainly determined by the ratio of R2 and R1 . To increase gain, this ratio must be large. Because this factor is determined by a ratio of resistors, it is less sensitive to process modiﬁcations. The topology of Fig. 5.5 has some limitations. The major one is the small voltage headroom available in recent CMOS technologies. This problem will only get worse as linewidth scales down and consequently the available power supply drops. First, when cascading several stages, the ratio R2 /R1 can not be made extremely large, as the DC voltage at nodes n3 and n4 must be suﬃciently high to drive the next stage. Second, a critical path exists between power supply and ground, where attention must be paid to keep all transistors in saturation. The path is formed by the voltage drop over R1 , the gatesource voltage of transistor M5 (Vgs,M5 ), the voltage drop over Rf , the gatesource voltage of transistor M3 (Vgs,M3 ) and ﬁnally the drain-source voltage of biasing transistor Mc3 (Vds,Mc3 ). In a 0.18 µm CMOS technology, the VT of an nMOS transistor is typically 0.5 V. For a traditional overdrive voltage Vgs −VT of 0.2 V, Vgs,M3 and Vgs,M5 must be equal to 0.7 V. Vds,Mc3 should be larger than the saturation voltage, which approximately equals the overdrive voltage Vgs − VT of 0.2 V. As a result, the voltage drop consumed by the transistors is as large as 1.6 V. With a power supply of 1.8 V, only 0.2 V is left for the resistors. Therefore, the current through these resistors is usually low and the resistance values are designed as small as possible within the constraint of high gain. Design values will be given in Section 5.5. The result is that the approximation gm,M5 Rf >> 1 is not longer valid, and the small-signal DC gain is more accurately modeled by: AMCH,0 =

gm,M1 (R1 + R2 )(1/gm,M5 + Rf ) . R1 + 1/gm,M3

(5.20)

120

5 Post-Ampliﬁer Design

Another important issue is the inﬂuence of the ratio R2 /R1 on the bandwidth, as fMCH also appears in (RC)2MCH and (RC)MCH . Simulations of (5.14) show that a large ratio, which is needed for large gain, also results in two real separated poles, which is less beneﬁcial for bandwidth. This should be avoided, and the design must focus on optimizing both gain and bandwidth by introducing complex conjugated poles. Finally, as the circuit of Fig. 5.5(a) has a feedback loop consisting of M5 , Rf , M3 , R1 and R2 , care should be taken to ensure stability. By cutting the loop for example at node n3b, following loop gain LMCH can be found: C

LMCH = −LMCH,0

gd,M 3 1 − s gm,M 3

s2 (RC)2LCH + s(RC)LCH + 1

,

(5.21)

with: LMCH,0 = gm,M3 R1 , (RC)2LCH = Rf (R1 + R2 )C 2 ,

(5.22) (5.23)

(RC)LCH = Rf gm,M3 (R1 + R2 )Cgd,M3 + Rf C1 + (R1 + R2 )CL . (5.24) C 2 is given by (5.18), and it is supposed that gm,M5 Rf >> 1 and gm,M3 R1 >> 1. Just like the small signal gain (5.14), the loop gain has a positive zero. This is dangerous for the phase margin, as it introduces a phase rotation of −90◦ . So the stability of this loop has to be monitored very closely during the optimization of the gain-bandwidth. 5.4.3 Broadband Stage with Capacitive Source Degeneration When the disadvantages of the Cherry-Hooper stage cannot be tolerated, a broadband stage must be realized in a diﬀerent way. Fig. 5.6 shows the circuit diagram of a diﬀerential voltage ampliﬁer stage with capacitive and resistive source degeneration. In order to create a broadband response, the input transistors M1a and M1b are degenerated such that their eﬀective transconductance increases at high frequencies. This requires that resistor Rs and capacitance Cs are placed between the sources of the transistors. The eﬀective transconductance Gm,CSD of the half-circuit equivalent is given by: Gm,CSD =

gm,M1 1 + gm,M1

=

Rs 1 2 // 2sCc

,

gm,M1 (sRs Cs + 1) . sRs Cs + 1 + gm,M1 R2s

(5.25)

The zero introduced by Rs and Cs causes the eﬀective transconductance to increase at higher frequencies. The same zero appears in the transfer function ACSD of the simpliﬁed small-signal half circuit depicted in Fig. 5.6(b):

5.4 Design of a Fully Diﬀerential Broadband LA

121

Vdd R 1a

R 1b n1a

n1b

I1

Vout1 Vout2 Vin1

M 1a

M 1b

Vin2

Rs n2a

n2b

Cs

M s1

M s2

M s3

(a)

n1

vout 2

gm,M1( vin vs) 2 n2 vs

Rs 2

R1

CL

2Cs

(b) Fig. 5.6. Voltage ampliﬁer with source degeneration: (a) schematic, (b) small-signal half circuit.

1 + sRs Cs , ACSD = −ACSD,0 1 + sCL R1 1 + s 1+gRs Cs Rs

(5.26)

m,M 1 2

with: ACSD,0 =

gm,M1 R1 2R1 ≈ . Rs 1 + gm,M1 R2s

(5.27)

The approximation in (5.27) holds for gm,M1 Rs 1. The voltage gain of the source degenerated ampliﬁer features two poles. The ﬁrst one is determined by the load at the output node n1, formed by CL and R1 . The other pole is a result of the source degeneration, and a factor (1 + gm,M1 Rs /2) higher than the corresponding zero. Bandwidth extension is obtained if the zero cancels the pole at node n1, so if:

122

5 Post-Ampliﬁer Design

Rs Cs = R1 CL .

(5.28)

The 3dB-bandwidth of this stage is than given by: BWCSD =

1 + gm,M1 R2s , 2πR1 CL

(5.29)

which is a factor (1 + gm,M1 Rs /2) higher than the bandwidth of a traditional diﬀerential stage with input transistor M1 and load R1 . However, this bandwidth extension comes at the price of a lower gain, which is reduced by the same factor (5.27). Compared to a Cherry-Hooper stage where both gain and bandwidth are extended, the voltage ampliﬁer with source degeneration has a lower gain-bandwidth product, but is less complex to design, has a lower power consumption, shows less problems with a low voltage headroom and is capable of a high output swing. 5.4.4 Oﬀset Compensation According to [S¨ac05], the input oﬀset voltage of an LA should be limited to about 0.1 mV, while a high-speed MOSFET ampliﬁer has a 3σ random oﬀset voltage of around 10 mV. An oﬀset compensation circuit is needed to reduce the oﬀset voltage to the required value. Fig. 5.7 shows a classical implementation of an oﬀset feedback compensation scheme, which will also be used in the LA studied in Section 5.5.2. The DC value at the output of the two signal paths is measured through the low-pass ﬁlter Ros -Cos . The output oﬀset value (the DC component of the diﬀerential output signal) is measured and ampliﬁed with a simple resistively loaded stage with voltage gain Aos . The resulting signal is fed back to the input to take corrective actions until the output oﬀset voltage becomes zero. The oﬀset compensation circuit not only suppresses the unwanted oﬀset voltage, but also some important low-frequency components of the input signal. In other words, the oﬀset compensation introduces a low-frequency cut-oﬀ in the overall LA frequency response. As discussed in Section 2.5.2 and Section 2.6, a low-frequency cut-oﬀ causes baseline wander and data-dependent jitter if the cut-oﬀ frequency is too high. For the conﬁguration of Fig. 5.7, the cut-oﬀ frequency is given by: fLF =

AP A Aos + 1 . 2πRos Cos

(5.30)

Note that AP A Aos is the loop gain of the oﬀset compensation loop. As a high gain AP A is one of the primary speciﬁcations of the PA, the values of Ros and Cos must be quite large to obtain a small cut-oﬀ frequency. In CMOS technologies, these high values can be realized by using some analog extensions which have become widespread: MiM-capacitors with a high capacitance per unit square and high-ohmic poly-resistors.

5.4 Design of a Fully Diﬀerential Broadband LA

123

APA

Vin

A1st

A1st

A1st

Vout

Ros Cos

Aos

Ros

Cos

Fig. 5.7. Block diagram of an LA with oﬀset compensation.

While a low cut-oﬀ frequency is needed to minimize ISI and jitter, the main disadvantage is the long compensation settling time. For most point-topoint communication links, long compensation times are acceptable, but they pose a severe obstacle for upcoming many-to-one links like passive optical networks. Each input channel may have diﬀerent power levels and therefore demand diﬀerent oﬀset settings of the ampliﬁer. The speed of the oﬀset compensation loop will therefore determine how quickly one can change between channels. Therefore [Cra05] proposes a peak detector structure and a variabletap feedback system to improve the trade-oﬀ between settling time and datadependent jitter. The oﬀset of the diﬀerential ampliﬁer is not estimated from the diﬀerence in DC values of its two outputs, but from the diﬀerence in peak values of its outputs. So a peak detector measures the output oﬀset voltage of the LA, and an integrator ﬁlters the instantaneous peak detector output and forces the steady-state output oﬀset voltage to be zero. Since peak information is lost when the gain stages of the LA become saturated, peak detectors are placed at the output of each LA stage and the last unsaturated output is used to sense the oﬀset. To demonstrate the technique, a 7-stage LA is fabricated in a 0.18 µm CMOS process. The prototype is tested up to 3.125 Gbit/s with input amplitudes ranging from 2.5 mVpp to 50 mVpp . The total diﬀerential gain is 42 dB. Oﬀset settling times less than 1 µs are measured while still maintaining SONET OC48 jitter levels. Finally note that often a 50 Ω matching network at the input of the LA is included with the oﬀset compensation circuit, as for example in [P¨oh94, Gal03, S¨ ac05]. This is especially necessary for stand-alone ampliﬁers which are expected by the (measurement) equipment to have a 50 Ω input impedance and to drive a 50 Ω load. As the ultimate goal of this work is to integrate a complete opto-electrical analog front-end with PD, TIA and LA, the issue of input matching is not addressed.

124

5 Post-Ampliﬁer Design

5.5 Case Studies The design simulations of two LAs are considered in this section. The focus lies on the primary speciﬁcations of the PA, namely gain and bandwidth. First a LA with four cascaded Cherry-Hooper stages is discussed, second a ﬁve-stage LA with oﬀset compensation is described. The measurement results of these LAs, realized together with high-speed output buﬀers in a 0.18 µm CMOS technology, will be treated in Section 6.4 and in Section 6.5. 5.5.1 A Four-Stage LA in 0.18 µm CMOS This LA consists of a plain cascade of the modiﬁed Cherry-Hooper stages depicted in Fig. 5.5. Whereas in [Fau83, Rei87, P¨ oh94, Hol03] emitter or source followers are placed between the cascaded stages, they are omitted in the described implementation, as they only degrade the gain performance. Current branches I1 with diode-connected transistor Mc2 and I2 with diode-connected transistor Mc4 are common to all stages. As derived in Section 5.4.2, the major advantage of the modiﬁed Cherry Hooper stage over a simple resistively-loaded diﬀerential stage, is an increase in both gain and bandwidth. The most important design parameters are summarized in Table 5.1. All transistors, except for the common-mode current source transistors, have minimal gate length. Due to the limited voltage headroom of 1.8 V, the saturation voltage VDSAT (≈ VGS − VT ) of the high-frequency transistors is slightly below 0.2 V. The gate length L of the current mirror transistors is not chosen minimal, but equals 0.8 µm, for the following reasons: • In [San06] it is shown that the current diﬀerence in the mirror is proportional to the diﬀerence in drain-source voltage, and inversely proportional to the product of Early voltage and channel length L. The larger L, the ﬂatter the Ids -Vds curve and the smaller the current diﬀerence between two transistors with unequal drain-source voltages. • The CMOS current and VT mismatch parameters are inversely proportional to the square root of the area W L of the transistor. Note also that Rf is as small as 40 Ω to limit the voltage drop over this resistor. Drawback is a smaller DC gain (5.15). In Fig. 5.8 the simulated frequency response for one stage and for the complete LA is depicted. The gain per stage equals 6.8 dB, which results in an overall gain of 27.4 dB. The ﬁrst stage is slightly diﬀerent from the following stages, as an LC input network is included in the simulations to take bondwires, bond pads and ESD-protection into account. This stage is of third order and has a bandwidth of 5.2 GHz. The next stages are all second order stages and have a 3-dB frequency equal to 6.7 GHz. Their gain-bandwidth product equals 14.6 GHz. The LA has an overall simulated bandwidth of 4 GHz, which corresponds quite well with the bandwidth predicted by (5.5). The gainbandwidth of the complete LA is 94 GHz, so the gain-bandwidth extension as

5.5 Case Studies 30

125

10

gain [dB]

gain [dB]

20 10 0 −10 −20 6 10

0

1st stage 2nd stage 3th stage output 7

10

5

first CH stage other CH stages 8

9

10 10 frequency [Hz]

10

10

−5 6 10

7

10

8

9

10 10 frequency [Hz]

(a)

10

10

(b)

Fig. 5.8. Simulated gain of the four-stage LA: (a) gain after each stage and at the output, (b) gain of the individual building blocks.

Table 5.1. Design parameters of the Cherry-Hooper stage in the four-stage LA. M1 /M2 M3 /M4 M5 /M6 type L W VDSAT IDS gm gds Cgs Cgd I1 I2 R1 R2 Rf

nMOS 0.18 µm 34 µm 0.17 V 0.78 mA 7.5 mS 0.46 mS 44 fF 12 fF

nMOS 0.18 µm 44 µm 0.17 V 1.1 mA 11 mS 0.39 mS 56 fF 16 fF

nMOS 0.18 µm 36 µm 0.16 V 0.78 mA 8.1 mS 0.32 mS 47 fF 13 fF

1.6 mA 2.5 mA 200 Ω 400 Ω 40 Ω

deﬁned in (5.6) equals 6.4. The circuit with biasing consumes 19 mA from a 1.8 V power supply. Compared to recently published papers in 0.18 µm CMOS ([Hol03, Gal03, Gal04, Cra05], see Table 6.8), the gain-bandwidth product of this circuit is not that high, but the power dissipation is very low: compared to [Gal04], the power dissipation is almost six time smaller.

126

5 Post-Ampliﬁer Design

5.5.2 A Five-Stage LA with Oﬀset Compensation in 0.18 µm CMOS The block diagram of the second LA is depicted in Fig. 5.9. It consists of an input buﬀer, ﬁve fully diﬀerential amplifying stages and oﬀset compensation feedback. The ﬁrst two stages are non-inverting Cherry-Hooper stages with negative impedance converters (CH with NIC), the last three stages are inverting voltage ampliﬁers with capacitive source degeneration (VA with CSD). The circuit schematic of the input buﬀer and the oﬀset compensation circuit are shown in more detail. A positive oﬀset voltage at the output of the LA will lead to nosp > nosn at the input of the oﬀset compensation feedback ampliﬁer. As a result, the current through Mos1a and consequently also through R1a will increase. Analogously, the current through Mos1b and R1b will decrease. Therefore, the DC input voltage of ninp decreases while the DC input voltage of ninn increases, both compensating for the positive output oﬀset voltage. The values of Ros and Cos , which make up the low-pass ﬁlter, must be chosen carefully. Too small values create a relatively high low-frequency cut-oﬀ. As a result, lower frequency components in the prbs data are considered as DC voltage variations and compensated for. On the other hand, large values of Ros and Cos generate longer settling times. In the described design, the simulated low-frequency cut-oﬀ (5.30) is 700 kHz. The input stage acts as a buﬀer between the previous building block (which is an analog equalizer as discussed in Section 6.5) on one hand and the ﬁrst amplifying stage and the oﬀset compensation ampliﬁer on the other hand. To minimize the load on the equalizer, the input transistors are very small (WM1 = 6 µm, LM1 = 0.18 µm). Capacitive source degeneration is added to increase bandwidth. A detailed circuit schematic of the modiﬁed Cherry-Hooper stage is depicted in Fig. 5.10. To increase the bandwidth of this broadband stage even further, a negative impedance converter (NIC) [Gal03] is added between output nodes n3 and n4. If the gate-drain capacitance of M7 and M8 is neglected, the impedance ZN IC between the drains is expressed by: ZN IC = −

gm,M 7 sCc

+

Cgs,M 7 Cc

+2

gm,M7 − sCgs,M7

,

(5.31)

where Cc is the compensation capacitance and Cgs,M7 is the gate-source capacitance of transistors M7 and M8 . Or, for frequencies well below the fT of the transistors: 1 1 Cgs,M7 + +2 . (5.32) ZN IC ≈ − sCc gm,M7 Cc The impedance ZN IC consists of a capacitive part (−Cc ) in series with a resistive part. This negative capacitance partly compensates for the capacitance at nodes n3 and n4. However, a good design choice has to be made, as a too large value of Cc can cause gain peaking and ringing.

5.5 Case Studies

127

Vdd R 1a

LA core

R 1b nin n

noutp

CH

Vin with Vin1

M 1a

M 1b

NIC

Vin2

Rs

CH with NIC

VA with CSD

VA with CSD

nin p

VA with CSD

Vout

noutn

Cs

I1

I1

Ros nosp

M os1a

M os1b

Ros nosn

Cos

Cos

Ios

Fig. 5.9. Block diagram of the ﬁve-stage LA with detail of the input buﬀer and oﬀset compensation circuit.

The design parameters of the CH stage with NIC are summarized in Table 5.2. To relax the biasing of the transistors in the critical path R1 -M5 -Rf -M3 -Mc3 , and optimizing gain-bandwidth, zero-VT transistors are used for the source follower feedback transistors M5 -M6 . These transistors are standard available in the 0.18 µm CMOS technology used, but have a minimal gate length of 0.3 µm. Comparing the saturation voltages VDSAT with the ones from the design discussed in Section 5.5.1, reveals that the saturation voltages are higher and come closer to the traditional value of 0.2 V. The current mirror transistors have even higher values in order to generate a better deﬁned current. Furthermore, the ratio R2 /R1 and the feedback resistor Rf have larger values in this design. Both measures result in a higher gain (5.15). Finally, note that the compensation capacitor Cc is realized as a series connection of two MiM-capacitors, with the common node connected to ground. This way, the parasitic capacitance to ground is eﬀectively taken into account during simulations. Since a large output swing is not possible with this bandwidth optimized Cherry-Hooper stage, a voltage ampliﬁer with capacitive source degeneration (VA with CSD) is used in the last stages of the amplifying chain. The design equations of this stage have been discussed in Section 5.4.3 and the circuit schematic is shown in Fig. 5.6. The design parameters are given in Table 5.2.

128

5 Post-Ampliﬁer Design Vdd

M5 n5

R1

R1

n3b

n4b

R2

R2

n3 Vout1

n1

Vin1

M3

Rf

M7

M8

I3

Cc

M1

n6

Vout2 n4

NIC

Rf

M6

M4

n2

I3

M2

I2

Vin2

I1

Fig. 5.10. Modiﬁed CMOS Cherry-Hooper with negative impedance converter (NIC).

The source degeneration capacitor Cs is also realized as a series connection of two MiM-capacitors. Finally, the simulated gain of the LA is depicted in Fig. 5.11(a) together with the gain after each stage. The transfer function of the separate gain stages is shown in Fig. 5.11(b). The CH stage with NIC has a simulated bandwidth of 7.6 GHz and a gain of 10 dB. The gain-bandwidth of this stage is 24 GHz, which is a gain-bandwidth improvement of almost 10 GHz compared to the CH stage discussed in Section 5.5.1. The source-degenerated ampliﬁer has a simulated bandwidth of 9 GHz, which results with a gain of 6 dB in a gainbandwidth of 18 GHz. The complete LA has a simulated small-signal gain of 38 dB, an overall 3-dB bandwidth of 5 GHz and a gain-bandwidth as high as 397 GHz. This should be suﬃcient to amplify 5 Gbit/s data with a low BER. The gain-bandwidth extension (5.6) over the Cherry-Hooper stage is 16.5 while the gain-bandwidth extension over the source-degenerated ampliﬁer is 22. Due to the oﬀset compensation circuit, the transfer function has a low-frequency cut-oﬀ of 700 kHz. This is still more than ten times smaller than the smallest frequency component in 231 -1 500 Mbit/s prbs data. Amplifying data with a smaller bitrate or more consecutive ones and zeros might result in baseline wander. The on-chip simulated output swing is 1.2 Vpp . The LA consumes 40 mA from a 1.8 V power supply. Comparing these values with present state-of-the-art (Table 6.8), this ampliﬁer competes with other

5.6 Conclusions

129

Table 5.2. Design parameters of the Cherry-Hooper stage with NIC and the voltage ampliﬁer with CSD in the ﬁve-stage LA. CH with NIC M1 /M2 M3 /M4 type L W VDSAT IDS gm gds Cgs Cgd

nMOS 0.18 µm 17 µm 0.23 V 1.2 mA 6.4 mS 0.3 mS 20 fF 6 fF

I1 I2 I3 R1 R2 Rf Cc Rs Cs

M5 /M6

nMOS zero-VT nMOS 0.18 µm 0.3 µm 44 µm 20 µm 0.19 V 0.25 V 1.7 mA 1.2 mA 13 mS 5.7 mS 0.7 mS 0.66 mS 53 fF 51 fF 16 fF 11 fF 2.6 mA 3.5 mA 0.5 mA 70 Ω 280 Ω 70 Ω 2 x 75 fF -

VA with CSD M7 /M8

M1a /M1b

nMOS 0.18 µm 8 µm 0.2 V 0.5 mA 2.8 mS 0.14 mS 10 fF 3 fF

nMOS 0.18 µm 20 µm 0.25 V 1.8 mA 8 mS 0.43 mS 24 fF 7 fF 1.9 mA 400 Ω 100 Ω 2 x 702 fF

recently published 0.18 µm limiting ampliﬁers, featuring a high gain and a high bandwidth, combined with a relatively low power dissipation.

5.6 Conclusions This chapter has covered diﬀerent design techniques needed for the realization of high-gain broadband limiting ampliﬁers. First, the main requirements for this ampliﬁer needed in order to generate high quality data signals for the clock and data recovery circuit have been discussed. The primary speciﬁcations are a high gain and a bandwidth equal to the bitrate aimed for. Other considerations are noise, input dynamic range, input oﬀset voltage, jitter, and loading of the transimpedance ampliﬁer by the input capacitance. Next, a discussion of some recently published high-performance CMOS LAs has been given. They are mainly based on inductive peaking, either by using passive or active inductors. To circumvent the drawbacks of this technique, another technique is applied in this work which goes back for many years: cascading transadmittance and transimpedance gain stages. This topology has

130

5 Post-Ampliﬁer Design

40

10

30 gain [dB]

gain [dB]

20 10 0

1st stage 2nd stage 3th stage 4th stage output

−10 −20 −30 4

10

6

0 CH with NIC VA with CSD 8

10 10 frequency [Hz]

(a)

5

10

10

−5 6 10

7

10

8

9

10 10 frequency [Hz]

10

10

(b)

Fig. 5.11. Simulated gain of the ﬁve-stage LA with oﬀset-compensation: (a) gain after each stage and at the output, (b) gain of the individual building blocks.

ﬁrst been proposed by Cherry and Hooper in the early 60’s by using a cascade of series-series feedback and shunt-shunt feedback ampliﬁers. Later, the technique is taken over by BiCMOS and CMOS designers for the realization of broadband ampliﬁers for optical communication networks. The most important issues concerning the design of a broadband diﬀerential LA have been treated in the following section. The optimal number of stages as a compromise between gain-bandwidth, area, power dissipation and noise has been found to be equal to ﬁve. An in-depth small-signal analysis of a Cherry-Hooper stage and a slightly modiﬁed Cherry-Hooper stage has been given. The main improvement of this stage compared to a diﬀerential stage with resistive loads, is an increase in both gain and bandwidth. The main limitations are that a suﬃciently high power supply is needed for DC biasing and that the design complexity is rather high. As an alternative, a broadband voltage ampliﬁer with capacitive and resistive source degeneration has been implemented. This stage increases the bandwidth, but at the cost of a corresponding decrease in gain. The implications of the traditional oﬀset compensation feedback loop have been studied and an alternative solution from literature based on peak detection and lower settling times has been discussed. Finally, two diﬀerent case studies have been presented to illustrate the trade-oﬀs encountered during the design of a LA. The ﬁrst LA consists of a simple cascade of four modiﬁed CMOS Cherry-Hooper stages. Each stage has a bandwidth of 6.7 GHz and a gain of 6.8 dB. The total gain of the four cascaded stages equals 27.4 dB, which results with an overall 4 GHz bandwidth in a gain-bandwidth product of 94 GHz. In the second LA design, this gain-bandwidth factor is more than four times improved and equals 397 GHz. This is achieved by using two Cherry-Hooper stages with negative impedance converters and three source-degenerated voltage ampliﬁers. Moreover, this LA

5.6 Conclusions

131

features oﬀset cancellation. The gain equals 38 dB and with a bandwidth of 5 GHz a bitrate of 5 Gbit/s should be feasible with low BER. This circuit, characterized by a high gain-bandwidth product combined with a relatively low power dissipation of 72 mW, outperforms most of the recently published 0.18 µm CMOS limiting ampliﬁers. The measurement results of these two LAs, including high-speed eye diagrams, will be shown in Chapter 6.

6 CMOS Realizations

6.1 Introduction After the theoretical design of the CMOS PD, the TIA and the LA, this chapter deals with four practical CMOS realizations. The TIAs and LAs have been analyzed in previous chapters, only some additional building blocks like the output buﬀers need to be covered here. The main focus lies on the measurements and the interpretation of the results. Each section is dedicated to a diﬀerent implementation. In Section 6.2, test photodiodes with a TIA in a 0.18 µm CMOS technology are discussed, followed in Section 6.3 by test photodiodes with a TIA in a 90 nm CMOS technology. The chip presented in Section 6.4 contains a 0.18 µm LA and high-speed output buﬀer. Finally, the diﬀerent building blocks are brought together in Section 6.5, where a completely integrated 0.18 µm CMOS optical receiver, working at Gbit/s bitrates, is described. One important challenge in opto-electronics is to focus the light from the transmitter on the photodiode. For the labo experiments, a ﬁber approach is chosen. A commercial multi-mode ﬁber is stripped and a clean cleavage is provided by a diamond knife. Another possibility is to use a pigtail style focuser. This is a ﬁber with at one side a regular LC-type connector, but at the other side a lens to focus the light beam. The spot diameter is 100 µm, a few tens of µm larger than the diameter of the implemented diodes. Despite the resulting optical losses, the measurements with the focuser also have advantages. First, the bare ﬁber must be located very close to the chip surface, leading to unwanted collisions with the top oxide. The working distance of the focuser is always a few mm, so oxide damage is avoided. Second, the stripping and cutting of the bare ﬁber is a very time-consuming and precise activity, while the focuser is always immediately on hand. The cost of the focuser is high, but it can be reused during many measurements over many years. The bare ﬁber can be worthless after one day due to a bad ﬁber cut, an unwanted collision or some small dust particles.

133

134

6 CMOS Realizations

Fig. 6.1. Opto-electrical measurement set-up. The inset shows a detail of the Gbit/s optical receiver IC implemented in a 0.18 µm CMOS technology, and the bare ﬁber that is used to focus the 850 nm light beam on the photodiode.

Fig. 6.1 shows a typical labo measurement set-up of an opto-electrical IC. The chip is ﬁrst wire-bonded on a ceramic substrate and mounted in a CopperBeryllium box, serving as a reference ground. A hole is made in the top of the box so that light signals can reach the photodiode. The box with substrate and chip is placed vertically on a precision multi-axis positioning table. Five screws are available to position the chip and/or rotate the ﬁber end. A vertical microscope assists the ﬁber positioning. At the inset of Fig. 6.1, a detail of the 0.18 µm optical receiver IC is shown, and the bare ﬁber tip can be clearly distinguished.

6.2 Test Photodiodes with TIA in 0.18 µm CMOS

135

6.2 Test Photodiodes with TIA in 0.18 µm CMOS As already mentioned in Section 4.5.1, the main purpose of this ﬁrst chip is to compare the performance of diﬀerent kind of photodiode topologies. The TIA is the same for every photodiode. First the layout of the photodiodes and the design of the receiver circuit are discussed. This is followed by an interpretation of the measurement results, of which the most successful ones are published in [Her04b, Her04c, Her06a]. 6.2.1 Circuit Description Photodiodes The ﬁve test photodiodes are: a classical n-well diode, a quasi-fractal nwell diode, a diﬀerential n-well diode, a p+ n-well diode with guard and an n+ p-substrate diode. Their junction capacitances are respectively 660 fF, 585 fF, 292 fF, 4.6 pF and 6.8 pF. All diodes have an area of 100x100 µm2 . The layout of the classical n-well diode, the n+ p-substrate diode and the p+ n-well diode with guard is straightforward. They all have 10 square junctions per diode side (Ns in Sections 3.5.1 and 3.5.2), or 100 junctions in total. Between the junctions are substrate contacts to minimize the substrate resistance. The layout of the classical n-well diode is represented schematically in Fig. 3.9. The layout of the n+ p-substrate diode is quasi the same, only the n-well regions are replaced by n+ regions. The layout of the p+ n-well diode with guard is represented schematically in Fig. 3.11. Every n-well square has two p+ regions surrounded by n-type contacts. The layout of the two other diodes is slightly more complicated. The layout of the quasi-fractal n-well diode is based on a maximization of side-wall capacitance, as this junction extends from the silicon surface down to the bottom of the n-well. A fractal is a well-known concept in mathematics and is deﬁned as an object or quantity that displays self-similarity on all scales. The object repeated in the layout of the quasi-fractal topology (Fig. 6.2(a)) is the n-well cross. As can be seen in the detail, the cross at the lowest level has eight extra branches on each side and the iterated pattern stops. Every n-well junction is surrounded by substrate contacts to minimize its parasitic resistance. The diﬀerential diode, depicted in Fig. 6.2(b), consists of an alternating pattern of illuminated and dark junctions. Subtraction of these two signals cancels the slowly diﬀusing substrate carriers. The total number of junction ﬁngers (Nf in Section 3.5.3) equals 32. Measures have been taken to minimize substrate and contact resistance: every junction is surrounded by substrate contacts, every ﬁnger is divided into halves to provide extra substrate contacts and the junctions have additional connection stripes in horizontal direction. The covering metal used to block the light is metal 3, as metal 1 and metal 2 were needed for routing.

136

6 CMOS Realizations

(a)

(b) Fig. 6.2. Detailed layout of: (a) the quasi-fractal n-well diode, (b) the diﬀerential n-well photodiode, both implemented in a 0.18 µm CMOS technology.

TIA and CSDA Fig. 6.3 shows a schematic of the receiver. It consists of two identical transimpedance ampliﬁers (TIA1 and TIA2 ), a complementary self-biased diﬀerential ampliﬁer (CSDA) [Baz91, Pie04] and an output buﬀer to drive the 50Ω load. For the diﬀerential photodiode, diode PD1 corresponds to the illuminated junctions, while diode PD2 corresponds to the dark junctions. The slow

6.2 Test Photodiodes with TIA in 0.18 µm CMOS

137

Vdd R f1

M2

M2c

M2a to output buffer

M1a

M1

R f2

nbias

M1b

M3 TIA2

TIA1 PD1

M4

M2b

PD2

M1c CSDA

Fig. 6.3. Simpliﬁed schematic of the 0.18 µm CMOS receiver circuit, needed to amplify the currents generated by the test photodiodes.

diﬀusion carriers detected by the two diodes appear as a common-mode signal at the two inputs of the CSDA and are suppressed. Only the fast current component, which is mainly the drift current, is then ampliﬁed. For the other topologies, diode PD1 is the one that captures the signal, while diode PD2 is a dummy diode placed for biasing and matching. The design of the TIA has been discussed thoroughly in Section 4.5.1. As the measurements always have been performed with Vb2 =1.8 V, transistors M3 , M1d and M2d shown in Fig. 4.7(a) are left out in the simpliﬁed schematic depicted in Fig. 6.3. The CSDA consists of two complementary diﬀerential stages, from which the loads have been removed. Transistors M1a , M1b and M1c make up the n-type half, while transistors M2a , M2b and M2c make up the p-type half. The gates of two complementary input transistors are connected so that the input stage is now an inverter. The transconductance is approximately doubled compared to the transconductance of a conventional diﬀerential stage. In order to create a stable current through biasing transistors M1c and M2c , no external voltage is applied, but their gates are connected to the internal ampliﬁer node nbias. This self-biasing of the ampliﬁer creates a negative feedback loop that stabilizes the bias voltages and makes it less sensitive to process or temperature variations. Because the voltage at nbias equals about one half of the power supply, transistors M1c and M2c operate in the linear region. Consequently, the voltages at their drains may be set very close to the supply voltages. So the output swing of this ampliﬁer approaches the power supply. Table 6.1 summarizes the design parameters of the CSDA.

138

6 CMOS Realizations

Table 6.1. Design parameters of the complementary self-biased diﬀerential ampliﬁer (CSDA). M1a /M1b M2a /M2c

M1c

M2c

type nMOS pMOS nMOS pMOS L 0.18 µm 0.18 µm 0.18 µm 0.18 µm W 40 µm 80 µm 40 µm 80 µm 0.25 V 0.26 V 0.26 V VDSAT 0.17 V 1.2 mA 1.2 mA 2.4 mA 2.4 mA IDS 11 mS 9.1 mS 7.7 mS 7.2 mS gm 0.5 mS 0.4 mS 12 mS 5.1 mS gds 47 fF 99 fF 44 fF 99 fF Cgs 15 fF 28 fF 26 fF 37 fF Cgd

The single-ended output of the CSDA is connected to the output buﬀer. It is realized as a single-stage inverter with an nMOS diode load to control the DC threshold voltage. This last stage consumes 1.4 mA from the 1.8 V supply voltage. Finally, a major advantage of this receiver topology is that TIA, CSDA as well as the output buﬀer all have a CMOS inverter topology, which makes it very suitable to implement in standard digital CMOS technologies. 6.2.2 Measurements All test photodiodes are integrated with the ampliﬁer stages in a standard 0.18 µm 1.8 V CMOS technology. No additional masks are used to enhance the performance of the photodiodes. On top of the diodes, there is only the standard dielectric stack, no anti-reﬂective coating. The chip photograph is depicted in Fig. 6.4. The total chip area taken by the ﬁve receivers, including bond pads and decoupling capacitors, equals 1x3.6 mm2 . Every photodiode is followed by an identical amplifying circuit that consumes only 17 mW. The optical source used during measurements is a commercially available 850 nm Inﬁneon transmitter. The average optical power is −6 dBm, and for sensitivity measurements this signal is attenuated by an EXFO attenuator. The electrical 27 -1 prbs data stream is generated by the HP data generator. The eye diagrams are constructed by triggering the Tektronix oscilloscope and by applying a display setting of inﬁnite persistence. BER and jitter measurements are obtained from the SyntheSys BitAlyzer. Fig. 6.5 compares the eye diagrams of the test diodes at 300 Mbit/s. A 27 -1 prbs data stream with an average input optical power (Popt ) of −7 dBm is applied. The slowly rising tail originating from the diﬀusing substrate carriers can be clearly distinguished in the eye diagram of the classical n-well diode (Fig. 6.5(a)). The eye quality of the quasi-fractal n-well diode (Fig. 6.5(b)) is slightly better, as relatively more carriers are generated now in the side-wall

6.2 Test Photodiodes with TIA in 0.18 µm CMOS

139

Fig. 6.4. Chip photograph of the ﬁve testdiodes with amplifying circuit in 0.18 µm standard CMOS.

(a)

(b)

(c)

(d)

Fig. 6.5. Eye diagrams of the 0.18 µm test diodes with amplifying circuit. The input signal has a bitrate of 300 Mbit/s and Popt =−7 dBm. The diﬀerent diodes are: (a) classical n-well diode, (b) quasi-fractal n-well diode, (c) p+ n-well diode with guard, (d) diﬀerential n-well diode.

140

6 CMOS Realizations

Fig. 6.6. Eye diagram of the 0.18 µm n+ p-substrate diode with amplifying circuit. The input signal has a bitrate of 100 Mbit/s and Popt =−7 dBm.

space charge regions. However, the improvement is not that large, because the n-well regions are surrounded by p-well regions with a higher doping proﬁle as the p-substrate, and so the side-wall regions have a limited width. The eye diagram of the third structure, the p+ n-well diode with guard (Fig. 6.5(c)), shows a larger improvement in speed: the edges are steeper and the jitter is less. However, the voltage scale reveals that the signals have a smaller amplitude. This is due to the lower responsivity of this diode topology. The eye diagram of the diﬀerential diode shows the best data quality: the eyeopening is much wider, the rising and falling edges are steeper and the jitter is only 80 ps compared to 310 ps. This progress is achieved without a large reduction of the output swing. The results of one teststructure are not yet shown: the n+ p-substrate photodiode. As expected, this photodiode has the worst performance. The maximum bitrate that can be achieved with an average input optical power of −7 dBm is 100 Mbit/s. The eye diagram is depicted in Fig. 6.6. The eye diagrams in Fig. 6.7 illustrate the high-speed capabilities of the diﬀerential PD with TIA and CSDA. The optical input signal has a bitrate of 500 Mbit/s (Fig. 6.7(a)) respectively 622 Mbit/s (Fig. 6.7(b)), and Popt =−7 dBm. Even at these bitrates, the jitter is small and the eye opening is wide compared to the eye opening of the classical n-well diode at 300 Mbit/s (Fig. 6.5(a)). These eye diagram measurements demonstrate that a diﬀerential photodiode topology is th´e solution for high-speed monolithic optical receivers. The BER versus average input optical power when a 27 -1 prbs data is applied is plotted in Fig. 6.8 for the diﬀerential n-well diode and the classical n-well diode. At 300 Mbit/s and when Popt =−8 dBm, the BER of the diﬀerential structure is better than 10−13 , while the BER of the n-well structure is only 2 · 10−10 . If smaller input signals are applied, the BER of the diﬀerential structure reduces due to the limited responsivity and the reduced data eye

6.2 Test Photodiodes with TIA in 0.18 µm CMOS

(a)

141

(b)

Fig. 6.7. High-speed eye diagrams of the 0.18 µm diﬀerential n-well diode with amplifying circuit. Popt =−7 dBm and the bitrate equals: (a) 500 Mbit/s, (b) 622 Mbit/s.

−3

10

−6

bit error rate

10

−9

10

−12

10

−15

classical n−well diode, 300Mbit/s differential n−well diode, 300Mbit/s differential n−well diode, 500Mbit/s

10

−18

10

−12

−11 −10 −9 −8 −7 Average input power [dBm]

Fig. 6.8. Bit error rate versus average input power of the 0.18 µm classical and diﬀerential n-well photodiode with amplifying circuit.

width. At 500 Mbit/s, the diﬀerential n-well diode achieves a BER of 3 · 10−10 when an input optical signal of −8 dBm is applied. The frequency response of the diﬀerential n-well diode followed by TIA, CSDA and output buﬀer, is depicted in Fig. 6.9. A Rohde&Schwarz network analyzer is used to modulate the laser driver and to evaluate the electrical output signal of the receiver. Measurements are done for the maximum and minimum value of the feedback resistance. When the transimpedance gain is high, the 3-dB bandwidth is 177 MHz. When the transimpedance gain is low, the 3-dB bandwidth is 245 MHz. So bandwidth is inversely proportional to

142

6 CMOS Realizations

Output power [dBm]

−10 −20 −30 −40 −50 Z −60 −70

=65 dBΩ

TIA

ZTIA=54 dBΩ 8

9

10

10 frequency [Hz]

Fig. 6.9. Frequency response of the 0.18 µm diﬀerential n-well photodiode followed by TIA, CSDA and output buﬀer.

Table 6.2. Performance summary of the classical and diﬀerential n-well photodiode with amplifying circuit in 0.18 µm CMOS. Classical Diﬀerential n-well diode n-well diode Technology 0.18 µm CMOS 1.8 V Vdd Optical wavelength 850 nm Die area 1000x685 µm2 1000x565 µm2 Bitrate 300 Mbit/s 500 Mbit/s 2 · 10−10 3 · 10−10 [email protected] =−8 dBm rms [email protected] =−7 dBm 310 ps 80 ps Power dissipation 17 mW

transimpedance gain, as described by (4.11). The 3-dB bandwidth is however smaller than the values predicted by the TIA-simulations in Section 4.5.1. This is due to the lower intrinsic bandwidth of the diﬀerential diode, and proves that the diode is the speed limiting component. The measurement results of both the classical and the diﬀerential n-well diode are summarized in Table 6.2.

6.3 Test Photodiodes with TIA in 90 nm CMOS The objective of this chip is very similar to the objective of the chip discussed in the previous section (Section 6.2): the comparison of the performance of

6.3 Test Photodiodes with TIA in 90 nm CMOS

(a)

(b)

143

(c)

Fig. 6.10. Layout of: (a) the classical n-well diode, (b) the quasi-fractal n-well diode, (c) p+ n-well diode with guard, all implemented in a 90 nm CMOS technology.

diﬀerent diode layout structures. The main diﬀerence is that for this chip a 90 nm CMOS technology has been used. First the design of the photodiodes and the receiver circuit are discussed, followed by an overview of the measurements. The results of this chip are published in [Her04b, Her04a]. 6.3.1 Circuit Description Photodiodes Due to space limitations in this more expensive technology, only three test diodes have been implemented: a classical n-well diode, a quasi-fractal n-well diode and a p+ n-well diode with guard. No accurate models are available for the side-wall n-well junction capacitance, so an estimation of the total junction capacitance has to be made. The values are estimated to be 1.6 pF (classical n-well diode) and 1.4 pF (quasi-fractal n-well diode). For the p+ n-well diode with guard, there exists a model for the side-wall junction and the total calculated capacitance of the p+ n-well junction equals 6 pF. All diodes have an area of 100x100 µm2 . The layout of these diodes is very much the same as the layout of their counterparts in the 0.18 µm technology (Section 6.2.1) and is depicted in Fig. 6.10. TIA and Output Buﬀer The design of the TIA has been discussed in Section 4.5.2. The schematic of the complete receiver circuit, consisting of TIA and output buﬀers, is depicted in Fig. 6.11. The output buﬀers are two scaled inverters with an nMOS load to control the DC threshold voltage. The simulated current consumption of the complete buﬀer equals 4 mA.

144

6 CMOS Realizations Vb1

Vdd

MRfb Rfb

Mb2

M2

Mb5 to 50 Ohm

M1

Vb2

Mb1

M3

Mb3

Mb4

Mb6

C ac Photodiode and TIA

Output Buffer

Fig. 6.11. Schematic of the 90 nm receiver circuit, needed to amplify the currents generated by the test photodiodes.

6.3.2 Measurements Fig. 6.12 shows a photograph of the 90 nm CMOS test chip. The upper part contains two stand-alone test diodes: the classical n-well diode and the quasifractal n-well diode. Both diodes are also implemented with the amplifying circuit (TIA and output buﬀer). In the lower part, the same structures are repeated for the p+ n-well diode with guard. The area of the upper part equals 1000x800 µm2 , the area of the lower part equals 450x1000 µm2 . No additional masks or anti-reﬂective coatings are used to enhance the performance of the photodiodes. As already mentioned in Section 4.5.2, no MiM-capacitors were available. To achieve a high capacitance density both for the on-chip decoupling and for Cac (Fig. 6.11), the metal wall structure is used [Yao04]. It creates a large capacitance value on a small area by using the side-wall capacitance of 8 metals from the 9 metal layer stack. With a supply voltage of 1.1 V, the amplifying circuit consumes 9 mW. The measurement set-up is the same as for the 0.18 µm test diodes. The only diﬀerence is that to determine the BER, the Agilent’s Inﬁnium oscilloscope has been used, that calculates the BER out of Q-factor measurements. The stand-alone testdiodes have been used to measure the DC responsivity. The n-well diode has a responsivity of 0.3 A/W, while the p+ n-well diode with guard has a responsivity of only 0.006 A/W. Fig. 6.13 shows the eye diagrams when a 232 -1 prbs at a bitrate of 100 Mbit/s and with an average input optical power (Popt ) of −7 dBm is applied. The eye diagram of the front-end with the n-well diode (Fig. 6.13(a)) clearly shows the slowly rising tail originating from the diﬀusing carriers in the substrate. There is not much diﬀerence between the eye diagram of the quasi-fractal n-well diode (Fig. 6.13(b)) and the classical n-well diode. The improvement is much less when compared with the 0.18 µm test structures. This is probably due to the higher doping concentration of the p-well. As a

6.3 Test Photodiodes with TIA in 90 nm CMOS

145

Fig. 6.12. Chip photograph of the three testdiodes with amplifying circuit in 90 nm standard CMOS.

result, the width of the depletion region is smaller, and the contribution of the drift current to the total current decreases. This explains why there is not much improvement in speed by optimizing the sidewall capacitance using a quasi-fractal structure. At the other hand, the eye diagram of the front-end with the p+ n-well diode with guard (Fig. 6.13(c)) is much better: the eyeopening is wider and the rising/falling edges are steeper. This demonstrates that the diﬀusing carriers are eﬀectively removed by the substrate contacts. In Fig. 6.14(a) and Fig. 6.14(b), two high-speed eye diagrams at 400 Mbit/s and 500 Mbit/s respectively of the p+ n-well diode with guard and amplifying circuit are shown. To perform sensitivity measurements, the output signals are ampliﬁed with a Mini-Circuits broadband low-noise ampliﬁer (LNA). Its low-frequency cutoﬀ equals 1 kHz and its upper 3-dB bandwidth equals 1 GHz. The LNA is further characterized by a gain of 20 dB and a noise ﬁgure of 3 dB. Sensitivity of the two front-ends is determined by applying a 232 -1 prbs and by measuring the Q-factor of the output data after the LNA. The optical attenuation between the optical source and the device under test has been adjusted to obtain a Q-factor of 6. This value corresponds to a BER of 10−9 . At 100 Mbit/s, the front-end with n-well diode has a sensitivity of −9 dBm, while the front-end

146

6 CMOS Realizations

(a)

(b)

(c) Fig. 6.13. Eye diagrams of the 90 nm test diodes with amplifying circuit. The input signal has a bitrate of 100 Mbit/s and Popt =−7 dBm. The diﬀerent diodes are: (a) classical n-well diode, (b) quasi-fractal n-well diode, (c) p+ n-well diode with guard.

with the quasi-fractal n-well diode has a sensitivity of −8.3 dBm. The frontend with p+ n-well diode with guard even achieves a sensitivity of −10.4 dBm at 400 Mbit/s, and a sensitivity of −8 dBm at 500 Mbit/s. All measurements are summarized in Table 6.3.

6.4 A 3.5 Gbit/s LA in 0.18 µm CMOS After two chips with photodiodes and TIAs, a CMOS implementation of the next receiver building block is presented: the limiting ampliﬁer. Again, an overview of the circuit topology is given before the measurements are discussed. The results are also published in [Her05, Her06a].

6.4 A 3.5 Gbit/s LA in 0.18 µm CMOS

(a)

147

(b)

Fig. 6.14. High-speed eye diagrams of the p+ n-well diode with guard and amplifying circuit. Popt =−7 dBm and the bitrate equals: (a) 400 Mbit/s, (b) 500 Mbit/s. Table 6.3. Performance summary of the test photodiodes with amplifying circuit in 90 nm CMOS. TIA with TIA with quasi- TIA with p+ n-well n-well diode fractal n-well diode diode with guard Technology Vdd Optical wavelength Die area 450x800 µm2 Diode responsivity 0.3 A/W Bitrate 100 Mbit/s Sensitivity @BER=10−9 Power dissipation

−9 dBm

90 nm standard CMOS 1.1 V 850 nm 450x800 µm2 450x1000 µm2 0.006 A/W 100 Mbit/s 400 Mbit/s 500 Mbit/s −8.3 dBm −10.4 dBm −8 dBm 9 mW

6.4.1 Circuit Description Four-Stage Limiting Ampliﬁer The design of this LA has been discussed previously in Section 5.5.1. The LA consists of four cascaded Cherry-Hooper stages, as depicted in Fig. 5.5. Output Buﬀer The output buﬀer, necessary to drive the 50 Ω of the measurement equipment, consists of two stages. To achieve a broad bandwidth, each stage comprises

148

6 CMOS Realizations Vdd 2* gm* v/4 * Rl

Rl

2* gm* v/4 * Rl

Vout1 Vin1 v/2

M1

M2 gm* v/4 nA

M c1

Rl I1

Vout2

M3 0

M4 gm* v/4

Vb

Vin2 v/2

nB

M c2

M c3

Fig. 6.15. Schematic of the fT -doubler.

an fT -doubler [Raz02], shown in Fig. 6.15. Transistors M1 to M4 all have the same sizing (W = 40 µm in the ﬁrst stage and W = 80 µm in the second stage) and operating point (Ids = 2 mA in the ﬁrst stage and Ids = 7 mA in the second stage, all lengths are chosen minimal). Resistor Rl is the load of transistors M1 and M3 at one side, and transistors M2 and M4 at the other side. Compared to a traditional diﬀerential pair with resistive load, this circuit reduces the input capacitance while maintaining the same gain. Consider a diﬀerential voltage v applied at the input transistors M1 and M4 . The small signal behavior of the circuit is also shown in Fig. 6.15. The input Vin1 goes up with an amplitude of v/2, while the input Vin2 goes down with the same amplitude. Vb is zero, as it is a bias voltage equal to the commonmode level of Vin1 and Vin2 . As a consequence, a current equal to gm v/4 ﬂows from drain to source in transistors M1 and M3 , and from source to drain in transistors M2 and M4 . These currents add up at the output nodes which results in a negative small-signal voltage 2 · gm v/4Rl at Vout1 and a positive small-signal voltage 2 · gm v/4Rl at Vout2 . So the diﬀerential gain equals gm Rl , which is the same as that of a diﬀerential pair with input transistor transconductance gm and load resistor Rl . By using the conﬁguration of Fig. 6.15, the input ports of the transistors are placed in series while the output ports are connected in parallel. This results in a lower input capacitance. If the parasitic capacitance at the two common-mode nodes nA and nB is negligible, the input capacitance is roughly equal to Cgs /2, where Cgs is the gate-source capacitance of transistors M1 to M4 Hence the name fT -doubler: the circuit halves the input capacitance while maintaining the same overall transconductance. The circuit also suﬀers from several drawbacks compared to a simple differential pair. First, the power dissipation is doubled. Next, the total current ﬂowing through the load resistors is doubled, making it more diﬃcult to keep the transistors in saturation. Further, the total output capacitance is doubled.

6.4 A 3.5 Gbit/s LA in 0.18 µm CMOS

149

Fig. 6.16. Chip photograph of the 3.5 Gbit/s LA in 0.18 µm standard CMOS.

Finally, if the parasitic capacitance at nodes nA and nB is not negligible, the input capacitance is higher than Cgs /2. 6.4.2 Measurements A die photograph of the limiting ampliﬁer with output buﬀer is depicted in Fig. 6.16. A standard 0.18 µm 1.8 V CMOS technology is used for the implementation. Total chip area including bond pads and decoupling capacitors is 1.3x1.5 mm2 . Special attention has been paid to make the layout symmetrical, both for the diﬀerential stages in the LA and for the diﬀerential stages in the buﬀer. The power dissipation equals 70 mA, from which only 19 mA is consumed by the LA. Bit error rate (BER), eye diagram and jitter measurements are obtained from the Agilent ParBERT (Parallel Bit Error Ratio Tester). A diﬀerential 231 -1 prbs is applied at the input. Fig. 6.17 and Fig. 6.18 show eye diagrams at 1 Gbit/s and at 3.5 Gbit/s respectively, and for diﬀerent input amplitudes. The eye opening measurement obtained from the ParBERT generates a threedimensional bit error rate diagram as a function of the sample delay (x-axis) and the sample threshold (y-axis). The contour of the eye is derived from the bit error rates that have been measured. Diﬀerent grey-levels are used for the regions between the lines of equal bit error rate: black corresponds to a BER lower than 10−12 . The eye opening is the best for large input signals and low bit-rates. But even for an input signal with a bitrate of 3.5 Gbit/s and an input voltage of 10 mVpp , the eye is still considerably open.

150

6 CMOS Realizations

(a)

(b) Fig. 6.17. Eye diagrams at 1 Gbit/s of the four-stage LA with output buﬀer: (a) Vin = 100 mVpp , (b) Vin = 10 mVpp .

(a)

(b) Fig. 6.18. Eye diagrams at 3.5 Gbit/s of the four-stage LA with output buﬀer: (a) Vin = 100 mVpp , (b) Vin = 10 mVpp .

6.4 A 3.5 Gbit/s LA in 0.18 µm CMOS

151

−11

bit error rate

10

−12

10

−13

10

−14

10

1

2 3 bitrate [Gbit/s]

4

Fig. 6.19. Bit error rate versus bitrate of the four-stage LA with output buﬀer. The input prbs signal has an amplitude of 10 mVpp . Table 6.4. Performance summary of the 3.5 Gbit/s 0.18 µm LA. Technology 0.18 µm CMOS 1.8 V Vdd Diﬀerential gain 27 dB Bitrate 3.5 Gbit/s 5 · 10−12 [email protected] mVpp rms jitter 12 ps Power dissipation 70 mA (LA: 19 mA)

The results of the bit error rate tests are shown in Fig. 6.19. A diﬀerential 231 -1 prbs input signal with an amplitude of 10 mVpp is applied, while for each test the bitrate of the input is changed. As expected, the higher the bitrate, the higher the bit error rate. At 1 Gbit/s the BER is as low as 7 · 10−14 , while at 3.5 Gbit/s the BER is still only 5 · 10−12 . The rms jitter is slightly dependent on level and speed of the input signal. For an input level of 10 mVpp and a bitrate of 3.5 Gbit/s, the measured rms jitter is 16 ps. Taking the rms jitter added by the ParBERT into account, the post-ampliﬁer and buﬀer establish an rms jitter of only 12 ps. Finally, the small-signal voltage gain is measured with a network analyzer. This results in a measured singleended voltage gain of 21 dB, which corresponds to a diﬀerential voltage gain of 27 dB. The measurement results are summarized in Table 6.4. In Table 6.8 at the end of this chapter, the performance of this LA [Her05] is compared with the papers discussed in Section 5.3. First it is noticed that the BiCMOS implementations achieve gain-bandwidth products larger than one 1 THz with 20-year-old technologies. Comparing [Her05] with the 0.18 µm

152

6 CMOS Realizations Rf

Vbias R block

A

CH with NIC

C block

50 Ohm Equalizer

PA

buffer

Vout

C block R block

Rf

50 Ohm

Vbias

Fig. 6.20. Block diagram of the described integrated receiver front-end.

CMOS implementations, only [Gal03] and [Gal04] achieve higher bitrates. The gain-bandwidth product of this chip is not that high, but the power dissipation is low. To conclude, the described ampliﬁer is comparable with today’s stateof-the-art, oﬀering wide-open eye diagrams at high bit-rates, low bit error rates and very low power consumption.

6.5 A Gbit/s Monolithic Optical Receiver Front-End in 0.18 µm CMOS The last implementation is a fully integrated optical receiver front-end in 0.18 µm CMOS. The ultimate goal of this ﬁnal chip is to receive light signals at Gbit/s bitrate and to convert them into voltage signals with a high output swing. Two measures have been taken to improve the speed performance of a classical n-well CMOS photodiode: a diﬀerential diode topology and an analog equalizer to compensate for its high-frequency roll-oﬀ. The signals are brought oﬀ-chip with a 50 Ω output buﬀer. In a complete one-chip optical receiver as depicted in Fig. 2.1, this output buﬀer would not be needed, and the output signals of the post-ampliﬁer are used to steer the clock and data recovery circuit (CDR). Fig. 6.20 shows the block diagram of the described receiver front-end. First the implementation of every building block is discussed in detail. Afterwards the measurement results are presented. The most important results are published in [Her06c, Her06b]. 6.5.1 Circuit Description Diﬀerential Photodiode The ﬁrst functional block in the architecture of Fig. 6.20 is the photodiode (PD). As the measurement results of the diﬀerent photodiodes in Section 6.2

6.5 A Gbit/s Monolithic Optical Receiver Front-End in 0.18 µm CMOS

153

Fig. 6.21. Photo of the 0.18 µm CMOS diﬀerential photodiode.

demonstrate the superiority of the diﬀerential photodiode concerning elimination of substrate carriers, also a diﬀerential PD is chosen for the presented receiver. Fig 6.21 depicts a photo of the implemented CMOS PD. As the core and cladding of the ﬁber are circular, an octagonal form is taken with a diagonal of 80 µm. The PD consists of 18 ﬁngers, of which 9 are covered with metal. To minimize optical non-idealities, this covering metal should be located as close to the silicon surface as possible. As metal 1 is used for routing, metal 2 is used for this purpose. Between the junction ﬁngers, substrate contacts are foreseen to minimize substrate resistance. For the same reason, every ﬁnger is cut in two in the middle to place extra substrate contacts. The diode is also surrounded by a broad guard ring of substrate contracts. The junction capacitance of the illuminated PD as well as the dark PD, with a reverse voltage of 1.3 V, equals 159 fF. Diﬀerential Transimpedance Ampliﬁer Before subtraction of the PD signals, the currents from the illuminated PD and dark PD are ﬁrst converted into a voltage by a diﬀerential TIA. The design of this circuit has been elaborated in detail in Section 4.5.3. The schematic of this diﬀerential TIA is depicted in Fig. 4.12. A high-pass ﬁlter, consisting of Cblock and Rblock , is needed to set the DC-level at the input of the subsequent diﬀerential stages. The major reason is that the signals from the illuminated and dark junctions have a diﬀerent peak-to-peak value, and thus generate diﬀerent DC-levels at the output of the TIA. This is not optimal for correct diﬀerential operation. Therefore, the bias voltage Vbias is applied externally and data-independent. The values of Cblock and Rblock must be chosen carefully, as too small values create a relatively high 3-dB frequency. As a result, lower frequency components in the prbs data stream are considered as DC-voltage variations and ﬁltered out. This

154

6 CMOS Realizations

baseline wander must be avoided. In the current design, Cblock =2 pF and Rblock =20 kΩ, which gives a 3-dB frequency of 4 MHz. Subtraction Block Now the currents of the PDs have been converted into voltages, their diﬀerence can be made by a diﬀerential voltage ampliﬁer. The signal originating from the diﬀusing substrate carriers will appear as a common-mode signal at the input of this ampliﬁer and will be suppressed. This function is implemented by a modiﬁed Cherry-Hooper topology with negative impedance converter to enhance bandwidth. The design of this stage has been explained in Section 5.5.2, where is was used as one of the amplifying stages in the limiting ampliﬁer. The speciﬁcations of this block are however slightly diﬀerent. In the subtraction block, it can be important to make a diﬀerential signal introducing as little non-idealities as possible, so bandwidth is maximized. Also the common-mode suppression should be high for a wide frequency band. Simulations show a bandwidth of 5 GHz when this stage is loaded with the almost 200 fF input capacitance of the equalizer. The small-signal diﬀerential gain equals 6 dB. Equalizer The function of the equalizer is to compensate for the frequency roll-of of the diﬀerential diode. Therefore, equalization is performed after subtraction of the signals. The advantage of equalizing a diﬀerential PD compared to a classical n-well diode [Rad04, Rad05] is the intrinsic potential of a better speed performance. The price to pay is a lower sensitivity. The design of this block has been the subject of a master’s thesis [Tav05, Tav06]. The circuit diagram of the equalizer is presented in Fig. 6.22(a) and the design parameters are summarized in Table 6.5. It is a pseudo-diﬀerential stage, with second-order capacitive source degeneration to create zeros at the desired frequencies. Its transfer function is given by: Geq = −

gm,M1 Rx R1 Z2 Z3 1 + gm,M1 R1 Z2 +R 1 Z3 +Z2 Z3

.

(6.1)

Using the expressions for Z2 and Z3 : 1 , sC2 1 Z3 = R3 + , sC3 Z2 = R2 +

(6.2) (6.3)

and assuming that gm,M1 R1 is suﬃciently large, the transfer function reduces to:

6.5 A Gbit/s Monolithic Optical Receiver Front-End in 0.18 µm CMOS

155

Vdd Rx Vin1

Vout2

Vout1

nxa

Rx nxb

M 1b

M 1a

Vin2

n1b

n1a

R3

R2

C3

C2

R1

R1

R2 C2

R3 C3

(a) 10

gain [dB]

5

0

−5

−10 6 10

Equalizer PD Compensated PD 7

10

8

10 frequency [Hz]

9

10

(b) Fig. 6.22. The analog equalizer: (a) schematic, (b) uncompensated and compensated characteristics of the diﬀerential photodiode (PD).

Geq = −

Rx s2 R2 C2 C3 + s((R1 + R2 )C2 + (R1 + R3 )C3 ) + 1 , R1 s2 R2 R3 C2 C3 + s(R2 C2 + R3 C3 ) + 1

with:

R2 = R1 R2 + R2 R3 + R1 R3 .

(6.4)

(6.5)

To gain intuitive insight, it is assumed that the diﬀerent poles are well separated (which is not necessarily true in a practical implementation), and (6.4) than further becomes: Geq = −

Rx (1 + s(R1 + R2 )C2 )(1 + s(R1 + R3 )C3 ) . R1 (1 + sR2 C2 )(1 + sR3 C3 )

(6.6)

The gain is determined by the ratio Rx /R1 . Adding a branch with resistor R and capacitor C creates a zero at frequency 1/2π(R1 + R)C and a pole at frequency 1/2πRC.

156

6 CMOS Realizations Table 6.5. Design parameters of the analog equalizer. M1 type L W VDSAT IDS gm gds Cgs Cgd

nMOS 0.18 µm 107 µm 0.21 V 6.1 mA 38 mS 1.7 mS 128 fF 39 fF

Rx R1 R2 R3 C1 C1

87 Ω 48 Ω 89 Ω 0Ω 3.7 pF 2 pF

Fig. 6.22(b) illustrates the working principle of the equalizer. As derived in Section 3.5.3, the transfer characteristic of a diﬀerential PD with 18 ﬁngers has a 3-dB frequency of 1 GHz and a roll-oﬀ increasing from 3 dB/decade up to 10 dB/decade above 1 GHz. The Eldo-simulations of the equalizer show a corresponding roll-up. The result is a compensated diode characteristic that is almost ﬂat up to 5 GHz. Five-Stage Limiting Ampliﬁer The block diagram of the LA is depicted in Fig. 5.9. Its design has been studied thoroughly in Section 5.5.2. Output Buﬀer The output buﬀer is needed to drive the oﬀ-chip 50 Ω load. It consists of four scaled stages: three fT -doublers (discussed in Section 6.4.1 and depicted in Fig. 6.15) and one diﬀerential pair with resistive load. For the last stage, a simple diﬀerential pair is preferred over the fT -doubler, as the latter one increases the output capacitance, and the output load is already assumed to be 1 pF. Each stage has a larger input transistor (from 24 µm up to 232 µm), consequently a higher input capacitance, also a higher current consumption and a lower load resistance (from 250 Ω down to 40 Ω parallel with 50 Ω). Note also that for this output buﬀer the small-signal 3-dB bandwidth is not

6.5 A Gbit/s Monolithic Optical Receiver Front-End in 0.18 µm CMOS

157

Fig. 6.23. Chip photograph of the Gbit/s monolithic optical receiver in 0.18 µm standard CMOS.

a good measure for its speed performance, as signals with a high amplitude are generated by the LA. Usually, the small-signal bandwidth is a lower limit, but transient signals simulations have to be performed too. Large and high-speed output signals result in a high power consumption: this block consumes 170 mA from the 1.8 V power supply. The on-chip voltage swing of 1.2 Vpp at the output of the LA is converted into a simulated 50 Ω oﬀ-chip swing of 500 mVpp , at bitrates up to 6 Gbit/s. 6.5.2 Measurements A chip photograph of the receiver with photodiode, integrated in a 0.18 µm 1.8 V CMOS technology, is depicted in Fig. 6.23. Die area, including bond pads and on-chip decoupling, is 1.5x3 mm2 . No additional masks or anti-reﬂective coatings have been used to enhance the optical performance of the diode. The measured photodiode DC responsivity for the diﬀerential signal is 0.03 A/W. The current consumption of the complete front-end is 250 mA. Both the TIA and LA consume 40 mA each, 170 mA is dissipated in the output buﬀer to generate high-speed 500 mVpp signals oﬀ-chip. The measurement results are summarized in Table 6.6. In the following, ﬁrst the measurements for the LA with output buﬀer are shown. Next the performance of the complete front-end is discussed. Limiting Ampliﬁer with Output Buﬀer Bit error rate (BER), eye diagram and jitter measurements are obtained from the Agilent ParBERT (Parallel Bit Error Ratio Tester). Applying a 27 -1

158

6 CMOS Realizations

prbs, error free operation from 800 Mbit/s up to 6 Gbit/s has been measured. The rms jitter equals 8 ps. The BER measurements versus input voltage at 4 Gbit/s, 5 Gbit/s and 6 Gbit/s are summarized in Fig. 6.24(a). At 6 Gbit/s, an input voltage of 8 mVpp is needed to achieve a BER of 10−12 . The corresponding eye diagram is depicted in Fig. 6.25(a). The smaller the input amplitude, the higher the bit error rate: a 6 mVpp input voltage at 6 Gbit/s results in a BER of 10−9 . At 5 Gbit/s and 4 Gbit/s , the sensitivity for a BER of 10−12 is 5 mVpp respectively 3 mVpp . Due to clipping of the ﬁrst Cherry-Hooper stage, the limiting ampliﬁer is also capable of handling very large signals. The input swing is only limited by the maximum tolerable voltage at the input, that has to be smaller than the supply voltage for reliability reasons. When the input voltage is 600 mVpp , the BER is better than 10−13 , independent of the bitrate. For a bitrate of 6 Gbit/s, the eye diagram is shown in Fig. 6.25(b). This results in a dynamic range with BER< 10−12 of 37.5 dB at 6 Gbit/s , 41.5 dB at 5 Gbit/s and 46 dB at 4 Gbit/s. Table 6.8 compares the performance of this LA [Her06c] with present stateof-the art. The ampliﬁer achieves a higher gain-bandwidth product than most other 0.18 µm CMOS LAs. Only [Gal03], which uses integrated passive inductors to increase the bandwidth, has an extremely high gain-bandwidth product. Furthermore, the power dissipation of the latter is higher than in [Her06c]. The high gain-bandwidth product of this LA results in maximal achievable bitrates with a low BER as high as 6 Gbit/s, combined with a high gain, a high input dynamic range and a high output swing. Optical Receiver The optical measurements of the complete receiver are performed with a commercially available 850 nm Agilent transmitter, electrically driven with a 27 -1 prbs generated by the ParBERT. The average output power of the transmitter is −6 dBm, and for sensitivity measurements this signal is attenuated by an EXFO attenuator. The BER measurements for bitrates ranging from 1 Gbit/s to 1.9 Gbit/s are summarized in Fig. 6.24(b). The BER becomes worse for higher bitrates and lower input powers. At 1.7 Gbit/s, −6 dBm is needed to achieve a BER smaller than 10−12 . The eye diagram of this output signal is shown in Fig. 6.26(b). For comparison, a 1 Gbit/s eye diagram is shown in Fig. 6.26(a) that achieves a BER< 10−14 . The jitter, characterized by an rms value of 35 ps, is clearly visible in these eyes and is the bottleneck for achieving higher bitrates. Much eﬀort has been put in ﬁnding out where the jitter originates from. After all, purely electrical measurements demonstrate that the circuit, from TIA to output buﬀer, performs according to expectations. Fig. 6.27 shows eye diagrams when the TIA is driven by an electrical 27 -1 prbs signal from the ParBERT with an amplitude of 4 mVpp , corresponding to an equivalent input current of 8 µApp . Taking a responsivity of 0.03 A/W into account, this would correspond to an average input optical power of 133 µW, or −8.75 dBm. The

6.5 A Gbit/s Monolithic Optical Receiver Front-End in 0.18 µm CMOS

6 Gbit/s 5 Gbit/s 4 Gbit/s

−9

10 bit error rate

159

−10

10

−11

10

−12

10

−13

10

2

4 6 8 peak−to−peak input voltage (mVpp)

(a) −6

10

−8

bit error rate

10

−10

10

−12

10

−14

10

1.9 Gbit/s 1.8 Gbit/s 1.7 Gbit/s 1.5 Gbit/s 1 Gbit/s

−12 −11 −10 −9 −8 −7 −6 average input power (dBm)

−5

(b) Fig. 6.24. Bit error rate measurements: (a) BER of the ﬁve-stage LA with output buﬀer versus input voltage for diﬀerent bitrates, (b) BER of the Gbit/s optical receiver versus average input optical power for diﬀerent bitrates.

comparison of Fig. 6.26(a) and Fig. 6.27(a) shows that the jitter is much less when a pure electrical input signal is applied. The 5 Gbit/s eye depicted in Fig. 6.27(b) shows that the data quality now degrades due to bandwidth limitations (as expected at this speed) and not due to jitter limitations. BER tests of the 5 Gbit/s eye result in a BER smaller than 10−14 . The important diﬀerence with the optical measurements is that the eyes in Fig. 6.27 are measured with a purely diﬀerential signal at the input. The nature of the signals generated by the diﬀerential photodiode is totally diﬀerent: the signals from the illuminated and dark photodiode have the same polarity, but diﬀerent amplitudes, and thus a common-mode component. Following experiments have been performed with electrical signals of the same polarity at the input:

160

6 CMOS Realizations

(a)

(b) Fig. 6.25. Eye diagrams at 6 Gbit/s of the ﬁve-stage LA with output buﬀer: (a) Vin = 8 mVpp , (b) Vin = 600 mVpp .

• Two 4 Gbit/s prbs signals with the same polarity, but an amplitude difference of 16 dB, are applied at the input. A serious degradation of the jitter, compared to the eyes in Fig. 6.27 can be observed. Lowering the amplitude diﬀerence to 6 dB deteriorates the amount of jitter even more. • Decreasing the bitrate of the prbs data from 4 Gbit/s to 1 Gbit/s decreases the amount of observed jitter. • Instead of prbs signals, a simple pattern of one-zero-one-zero-etc. is applied at the input. The bitrate is changed from 1 Gbit/s to 4 Gbit/s. The observed jitter is low, much lower as when prbs signals are applied. Also, the amount of jitter does not increase with the bitrate. What does change is the location of the cross-over points on the time axis. The explanation for these observations is that the common-mode suppression of the receiver, and more precisely of the diﬀerential TIA, is not high enough. Ideally, the common-mode rejection ratio for a diﬀerential circuit is inﬁnity. However, due to non-idealities, such as mismatch between the VT of the input transistors (which are nMOS transistors and thus also suﬀer from bulk-eﬀect and mismatch on the bulk-eﬀect parameter), the common-mode rejection becomes worse, especially at higher frequencies. A non-inﬁnite common-mode

6.5 A Gbit/s Monolithic Optical Receiver Front-End in 0.18 µm CMOS

161

(a)

(b) Fig. 6.26. Optical eye diagrams of the complete front-end. The input signal has an average optical power of Popt = −6 dBm and the bitrate equals: (a) 1 Gbit/s, (b) 1.7 Gbit/s.

suppression means that a pure common-mode signal at the input (two signals with the same polarity and the same amplitude, so the diﬀerential input signal equals zero), will result in a non-zero diﬀerential signal at the output. This problem can also be considered as an oﬀset problem. The way that oﬀset problems result in jitter generation is depicted in Fig. 6.28: a diﬀerent oﬀset voltage (suggested by the black and grey transfer curves) will result in diﬀerent cross-over points on the time axis. If the oﬀset voltage remains constant, there is no problem. However, due to the nature of the prbs signals, diﬀerent frequency components are present. As the common-mode suppression varies for diﬀerent frequencies, the oﬀset voltage also changes with time. This results in a large amount of jitter on the time axis. While Table 6.6 summarizes the most important measurements of the fully integrated optical receiver, Table 6.7 compares its performance with other CMOS integrated opto-electrical front-ends. Note that the receiver described in this work [Her06c] features the highest level of integration, incorporating a photodiode, transimpedance ampliﬁer and limiting amliﬁer. [Sch02] and [Che05] do not implement an integrated photodiode, but

162

6 CMOS Realizations

(a)

(b) Fig. 6.27. Electrical eye diagrams of the complete front-end. The input signal has an equivalent current amplitude of Ieq = 8 µApp and the bitrate equals: (a) 1 Gbit/s, (b) 5 Gbit/s.

perform measurements with commercial photodiodes with a responsivity of 0.75 A/W-0.85 A/W. The diﬀerential PD of [Her06c] has a responsivity of only 0.03 A/W, hence the lower receiver sensitivity. The work presented in [Roo00] and [Roo01] uses SML-detectors, essentially the same topology as the diﬀerential diode. Their responsivity is larger because older technologies with wider space charge regions are used. [Rad05] includes an integrated photodiode and outperforms [Her06c] both in speed and in responsivity. The latter results from the use of a classical n-well diode with a higher intrinsic responsivity than the diﬀerential photodiode. To increase the n-well diode speed performance, equalizing techniques have been used. Furthermore, jitter problems are much less an issue in this approach due to the nature of the signals stemming from the single n-well diode. Combining a diﬀerential photodiode with equalizing techniques as presented in [Her06c] should result in a better speed performance. It is strongly believed that, by improving the common-mode suppression of the TIA and thus the jitter performance, achieving bitrates of 5 Gbit/s is feasible using an equalized diﬀerential photodiode in a 0.18 µm CMOS technology.

6.5 A Gbit/s Monolithic Optical Receiver Front-End in 0.18 µm CMOS diff. output

diff. output

jitter!

t

diff. input

diff. input

t

Fig. 6.28. Generation of jitter due to oﬀset problems. Table 6.6. Performance summary of the Gbit/s 0.18 µm optical receiver. Technology Vdd Optical wavelength photodiode DC responsivity

0.18 µm CMOS 1.8 V 850 nm 0.03 A/W

Optical receiver Bitrate [email protected] =−6 dBm rms jitter Power dissipation

1.7 Gbit/s 10−12 35 ps 250 mA

Limiting ampliﬁer with output buﬀer Bitrate 6 Gbit/s 10−12 [email protected] mVpp rms jitter 8 ps Dynamic range 37.5 dB Power dissipation 210 mA (LA: 40 mA)

163

164

6 CMOS Realizations

Table 6.7. Comparison of the described optical receiver front-end with other CMOS opto-electrical receivers. Ref.

Integration level PD TIA PA

Technology

Bitrate

Sensitivity

[Roo00] [Roo01] [Sch02] [Che05] [Rad05]

0.6 µm 0.25 µm 0.35 µm 0.18 µm 0.18 µm

250 Mbit/s 700 Mbit/s 1.25 Gbit/s 10 Gbit/s 3 Gbit/s

−18 dBm −18 dBm −22.5 dBm −12 dBm −19 dBm

x x x

x x x x x

x x -

[Her06b]

0.18 µm

1.7 Gbit/s

−6 dBm

x

x

x

6.6 Conclusions This chapter has covered the implementation of four standard CMOS chips that each contain one or more building blocks of the optical receiver. This way, the theory developed in the previous chapters has been put into practice. Much attention has been paid to the measurement set-up and the interpretation of the measurement results. A systematic approach has been chosen, where the ﬁrst two chip implement test diodes with TIAs, the third chip contains a LA, and the ﬁnal chip presents a fully integrated optical receiver. The objective of the ﬁrst two chips is a demonstration of light detection by standard CMOS photodiodes. No additional layers or coatings have been used to enhance the diode speed or responsivity. Furthermore, the performance of diﬀerent diode types can be compared, as the circuit has been designed not to be the speed limiting factor. Five test diodes with amplifying circuits have been designed in 0.18 µm CMOS, from which the diﬀerential n-well diode has proven to have the best performance. Bitrates up to 500 Mbit/s have been demonstrated with a BER in the order of 10−10 , where the receiver with classical n-well diode can achieve a bitrate of 300 Mbit/s for the same BER. A speed factor improvement of almost two has thus been established by applying a clever layout topology for the photodiode. Due to space limitations, only three test diodes with ampliﬁers have been implemented in the more expensive 90 nm technology. The diﬀerential diode was left out, and the p+ n-well diode with guard turned out to have the best performance. Bitrates of 500 Mbit/s are achieved with a BER of 10−9 . Finally, when the two designs in diﬀerent CMOS generations are compared, one can conclude that achieving higher bitrates at the receiver front-end becomes more diﬃcult in newer CMOS generations with smaller linewidths. There are two main reasons. First, the intrinsic speed as discussed in Chapter 3 becomes lower due to the smaller space charge regions. Second, achieving a high extrinsic speed in combination with the TIA as discussed in Chapter 4 will become more diﬃcult due to the

Table 6.8. Comparison of the described LAs with other LAs implemented in Bipolar or CMOS technologies. Ref.

Technology

[Fau83] 5 µm Bipolar [Rei87] 2 µm Bipolar [P¨ oh94] 0.4 µm Bipolar [S¨ ac00] 0.25 µm CMOS [Hol03] [Gal03] [Gal04] [Cra05]

0.18 0.18 0.18 0.18

µm µm µm µm

CMOS CMOS CMOS CMOS

Vdd 6V 5V −4 V 2.5 V & 3.4 V 1.8 V 1.8 V 2.2 V 1.8 V

[Her05] 0.18 µm CMOS 1.8 V [Her06c] 0.18 µm CMOS 1.8 V

Adif f

GBW

Bitrate

Pdiss

Sensitivity

Max. signal

60 dB 470 GHz 650 Mbit/s 250 mW 300 µVpp 300 mVpp 54 dB 1103 GHz 4 Gbit/s 350 mW 2 mVpp 400 mVpp 45 dB 1600 GHz 10 Gbit/s 400 mW 2.25 mVpp 32 dB 119 GHz 43 dB 50 dB 15 dB 42 dB

2.5 Gbit/s 190 mW

2 mVpp

297 GHz 2 Gbit/s 79 mW 2973 GHz 10 Gbit/s 100 mW 4.6 mVpp 124 GHz 40 Gbit/s 190 mW 393 GHz 3.125 Gbit/s 113 mW 2.5 mVpp

27 dB 94 GHz 38 dB 397 GHz

3.5 Gbit/s 6 Gbit/s

34 mW 72 mW

10 mVpp 8 mVpp

Oﬀset comp. no yes yes

2 Vpp

yes

50 mVpp

no yes no yes

600 mVpp

no yes

166

6 CMOS Realizations

higher photodiode junction capacitance at the dominant input node and due to the limited voltage gain in submicron CMOS technologies. The next building block implemented in a 0.18 µm CMOS technology has been a limiting ampliﬁer. A Cherry-Hooper topology has been used to broaden the bandwidth instead of space-consuming passive inductors or noisy active inductors. The output buﬀer necessary to drive the 50 Ω oﬀ-chip load comprises two fT -doublers. To demonstrate the implemented broadband techniques, eye diagrams with low BER up to 3.5 Gbit/s have been measured. The performance of this chip competes with present state-of-the-art (Table 6.8). Finally, all knowledge has been gathered in the design of the fully integrated 0.18 µm CMOS optical receiver. It contains a diﬀerential photodiode, a diﬀerential TIA, an equalizer to enhance the intrinsic speed of the diﬀerential PD, a high-speed LA with oﬀset-compensation and an output buﬀer including 3 fT -doublers. Applying purely electrical diﬀerential signals at the input, the receiver behaves according to the simulations: bitrates up to 5 Gbit/s have been measured with low BER. The stand-alone LA with output buﬀer can handle bitrates even up to 6 Gbit/s, and outperforms several recently published 0.18 µm CMOS LAs (Table 6.8). Further work needs to be done to improve the opto-electrical measurements, and the attention should be focused on the reduction of the jitter due to an insuﬃcient common-mode suppression. However, this work already demonstrates that receiving 850 nm prbs light signals with bitrates higher than 1 Gbit/s is feasible in a mainstream CMOS technology.

7 Conclusions

After the free fall of the telecommunication industry in the beginning of this century, a gradual recovery started in 2004. At the end of 2006, this positive evolution continues and people start to dream again. Numerous new optoelectronic applications are emerging, while low cost remains a prime concern. The simple law of economics dictates that the existing III-V compound semiconductor opto-electronics industry will be aﬀected by optical devices made of silicon. Nowadays, silicon devices can achieve almost all of the necessary functions for integrated optical devices, like detectors, modulators and switches. Only an electrically powered silicon light source, preferably a laser, is lacking, although successful research is going on also in this ﬁeld, for instance by Intel [CP06, Pan05] and by STMicroelectronics [Cof05]. If a commercial silicon laser ﬁnally would be available, the sky is the limit and silicon photonics will become reality. It will allow manufacturers to build optical components using the same semiconductor equipment and methods they use now for ordinary integrated circuits, thereby dramatically lowering the cost of photonics. The presented work ﬁts in this research on silicon opto-electronics. To further lower the cost, the cheapest technology has been selected: standard CMOS, without any optical tricks or ﬂavors. Of course this mainstream CMOS technology has an inherent lower performance than dedicated (Bi)CMOS or compound semiconductor technologies. The goal of this work is to demonstrate the feasibility of light detection in the same CMOS technology that is used to manufacture standard digital circuits. Furthermore, it is shown in theory and practice that the inherent low speed performance of CMOS diodes can be enhanced both on the detector level and on the circuit level. Besides the design of the photodiode, the focus lies on the design of the transimpedance ampliﬁer and the post-ampliﬁer. The main contributions and achievements are: • The fundamental laws of semiconductor physics have been reviewed to gain in-depth understanding of the opto-electrical mechanisms in silicon detectors. These insights have lead to the development of a one-dimensional

167

168

7 Conclusions

analytical model of the photodiode junction. A complementary numerical two-dimensional model has been developed taking into account more side eﬀects like retrograde doping proﬁles and side-wall junctions. These eﬀects are important for more complicated diode topologies and will also become more and more pronounced for the emerging nm-scale technologies. Based on this two-dimensional model, the theoretical performances of diﬀerent kinds of diode topologies have been compared. As the market today is characterized by two important phenomena: Moore’s law on the electrical side and the development of new light sources on the optical side, these trends have been evaluated using the two-dimensional model. • An in-depth high-level analysis of the shunt-shunt feedback transimpedance ampliﬁer has been presented. Analytical equations have been derived for the transimpedance gain, bandwidth, transimpedance-bandwidth product, loop gain, gain margin and noise. The core ampliﬁer has been modeled as a black box characterized by DC voltage gain A0 , input capacitance Cin and output impedances Cout and Rout . The applied assumptions and approximations have been pointed out explicitly, as a good designer should be aware that design equations are only valid in a limited design space. However, the trends predicted by these equations form a solid base for a sound design. In a next phase, the ampliﬁer’s black box has been opened, and a literature overview of possible implementations has been given. Finally, a detailed study at the transistor level of three diﬀerent common-source TIAs has been presented. Confronting simulation results with design equations has revealed that the basic design assumptions are not always valid when pushing the performance to its limits. Also a more accurate noise model for the photodiode has been elaborated, that takes into account the parasitic series resistance. • The design of a broadband limiting ampliﬁer, consisting of several cascaded gain stages, has been presented. After a (historical) literature study, a Cherry-Hooper topology has been preferred over inductive peaking stages. Analytical design equations have been derived for this broadband stage which again form a solid base for a good design. Also for this building block the assumptions and approximations made to arrive at the equations have been highlighted, so the designer can use them consciously. In addition to the Cherry-Hooper stage, a capacitive source degenerated stage has been analyzed. Finally the technique of oﬀset compensation, indispensable in high-performance LAs, has been disclosed. The theory has been completed with two case studies that clearly illustrate all design choices encountered during the design of an analog high-performance circuit. • An important achievement reached in this work is the systematic analysis, design and implementation of diﬀerent CMOS photodiode topologies. The photodiodes have been realized together with TIAs and output buﬀers in mainstream CMOS technologies and these opto-electronic circuits have been tested in a real-life measurement set-up. Optical signals from a commercial 850 nm transmitter were applied at the input. The

7 Conclusions

169

conclusion is that a diﬀerential photodiode is the best topology choice when high bitrates are pursued, at the expense of a lower responsivity. A comparison of the 0.18 µm PDs with the 90 nm PDs, reveals that technology downscaling is not beneﬁcial for the overall photodiode performance. Also for the TIA, newer technologies with higher fT ’s are not necessarily better, as it becomes more diﬃcult to achieve a high voltage gain in sub-micron technologies. This high voltage gain is needed to maximize the transimpedance-bandwidth product. This should however not impede the CMOS integration of opto-electrical front-ends in future technologies: analog design engineers will always be inventive enough to ﬁnd new solutions for new problems. • To demonstrate the broadband amplifying prospects of CMOS CherryHooper ampliﬁers, a ﬁrst LA is designed, manufactured in 0.18 µm CMOS and measured. The experience gained in this design cycle has lead to the design and measurements of a second LA incorporating oﬀset compensation. The performance achieved by this circuit outperforms present stateof-the-art. Table 6.8 compares the described LAs with the LAs studied in Section 5.3. Looking at the CMOS implementations, only [Gal03] (which integrates passive inductors) has a higher gain-bandwidth than [Her06c]. The broadband techniques applied in [Gal03] are undoubtedly very eﬀective to achieve circuits with high gain-bandwidth. However, power dissipation of the core ampliﬁer (excluding output buﬀers) is higher than in [Her06c]. • The ﬁnal achievement has also been the largest challenge for the presented research: the realization of a monolithic optical receiver front-end, consisting of a PD, TIA and LA. To realize this goal, a very systematic approach has been chosen, where ﬁrst the three building blocks have been studied separately, but at the same time their mutual impact never has been neglected. To enhance the speed performance of the diﬀerential photodiode even further, an analog equalizer compensates for its frequency roll-oﬀ. Table 6.7 compares the presented work with other state-of-the-art integrated opto-electrical receivers and shows that it features the highest level of integration, while its performance is comparable to other designs. The input signals for the photodiode are provided by a commercial available 850 nm optical transmitter. Finally note that, to the author’s knowledge, the chip presented in [Her06c] is the ﬁrst monolithic CMOS opto-electrical receiver integrating photodiode, transimpedance ampliﬁer and limiting ampliﬁer, that achieves bitrates higher than 1 Gbit/s.

References

G. P. Agrawal, Fiber-Optic Communication Systems, John Wiley & Sons, second edition, 1997. Baz91. M. Bazes, “Two Novel Fully Complementary Self-Biased CMOS Diﬀerential Ampliﬁers”, IEEE Journal of Solid-State Circuits, vol. 26, no. 2, pp. 165–168, Feb. 1991. Cha91. Z. Y. Chang and W. M. C. Sansen, Low-Noise Wide-band Ampliﬁers in Bipolar and CMOS Technologies, Kluwer Academic Publishers, 1991. Che63. E. M. Cherry and D. E. Hooper, “The Design of Wide-Band Transistor Feedback Ampliﬁers”, Proceedings IEE, vol. 110, no. 2, pp. 375–389, Feb. 1963. Che05. W.-Z. Chen, Y.-L. Cheng, and D.-S. Lin, “A 1.8-V 10-Gb/s Fully Integrated CMOS Optical Receiver Analog Front-end”, IEEE Journal of Solid-State Circuits, vol. 40, no. 6, pp. 1388–1396, June 2005. Cof05. S. Coﬀa, “Light From Silicon”, IEEE Spectrum, pp. 36–41, Oct. 2005. Cou97. L. W. Couch, Digital and Analog Communication Systems, Prentice-Hall, 1997. CP06. Y. Carts-Powell, “Innovative Techniques Light Up Silicon Lasers”, FibreSystems Europe/LIGHTWAVE Europe, pp. 33–34, Sept. 2006. Cra05. E. Crain and M. Perrott, “A 3.125 Gb/s Limit Ampliﬁer with 42 dB Gain and 1 µs Oﬀset Compensation in 0.18-µm CMOS”, in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 232–233, San Francisco, USA, Feb. 2005. Csu02. S. M. Csutak, J. B. Schaub, W. E. Wu, and J. C. Campbell, “High-Speed Monolithically Integrated Silicon Optical Receiver Fabricated in 130-nm CMOS Technology”, IEEE Photonics Technology Letters, vol. 14, no. 4, pp. 516–518, Apr. 2002. Dor98. R. C. Dorf and R. H. Bishop, Modern Control Systems, Addison-Wesley, 1998. Fau83. D. W. Faulkner, “A Wide-Band Limiting Ampliﬁer for Optical Fiber Repeaters”, IEEE Journal of Solid-State Circuits, vol. 18, no. 3, pp. 333–340, 1983. Fre. http://www.freescale.com, Freescale Semiconductor–Technologies– Research and Development–Semiconductor R&D Laboratories–Silicon on Insulator. Agr97.

171

172 Fre04. Gal03.

Gal04.

Gen01.

Gra02. Gra04. Her03.

Her04a.

Her04b.

Her04c.

Her05.

Her06a.

Her06b.

Her06c.

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Index

absorption coeﬃcient, 28 automatic gain control ampliﬁer, 14, 107 average mark density, 18

depletion region, 28, 30 diﬀerential n-well diode, 52, 54, 57, 82, 97, 135, 139, 141, 152 diﬀusion, 28, 37, 39 drift, 28, 40 DVD, 16, 52

bandwidth-distance product, 7 baseline wander, 25 BiCMOS, 32 bit error rate, 20, 141, 149, 157 bit period, 17 bitrate, 17 bitrate-distance product, 2 block coding, 18 Blu-Ray Disc, 6, 16, 52 burst mode, 19

electric ﬁeld, 28 electrical sensitivity, 22 equalizer, 36, 154 extrinsic bandwidth, 31 eye diagram, 20, 138, 144, 149, 157

CD, 16, 52 Cherry-Hooper ampliﬁer, 113, 116 classical n-well diode, 47, 53, 57, 82, 93, 135, 139, 143, 146 clock and data recovery circuit, 14 CMOS, 31, 32, 35 common gate TIA, 78 common source TIA, 77, 81 Communications Technology Roadmap, 7 complementary self-biased diﬀerential ampliﬁer, 136 continuity equation, 37, 39 continuous mode, 19 damping ratio, 65 DC wander, 25 demultiplexer, 14

fT -doubler, 148, 156 ﬁber, 2 ﬁber-to-the-home, 4 frequency roll-oﬀ, 49, 50, 52, 54, 57 gain-bandwidth product, 114 HD-DVD, 6, 16, 52 inductive peaking, 110 input dynamic range, 109 input oﬀset voltage, 110 input-referred noise, 62, 73 intersymbol interference, 23 intrinsic 3-dB bandwidth, 48, 50, 51, 54, 57 intrinsic bandwidth, 31 intrinsic frequency characteristic, 48, 50, 53, 55, 56, 58 ISSCC, 80

177

178

Index

jitter, 25, 110, 149, 157, 163 junction capacitance, 57 Lambert-Beer’s Law, 28 laser, 2, 14 laser diode, 14 laser driver, 14 light ﬂux, 30 limiting ampliﬁer, 14, 107, 124, 126, 146 line coding, 18 local area networks, 4 long-haul communication systems, 2 measurement set-up, 134 Medici, 46 modiﬁed Cherry-Hooper ampliﬁer, 117 modulator driver, 14 Moore’s Law, 6, 56 multiplexer, 14 n+ p-substrate diode, 82, 135, 140 n-well p-substrate junction, 38 natural pulsation, 65 noise bandwidth, 63 non-return-to-zero, 17 oﬀset, 163 oﬀset compensation, 122 one-dimensional model, 37 optical sensitivity, 23 optical telegraph, 1 output buﬀer, 143, 147, 156 output noise, 62, 71, 73, 89 overload current, 63 p+ n-well diode with guard, 49, 82, 93, 135, 139, 143, 146, 147 p+ n-well junction with guard, 44 PA bandwidth, 109 penetration depth, 30 phase margin, 69

photodiode, 13, 17, 29, 87, 88 photons, 28 photophone, 2 PIN diode, 33 plastic optical ﬁber, 5 POF, 52 post-ampliﬁer, 14, 17, 107 pseudorandom bit sequence, 18 Q function, 21 Q-factor, 145 quantum eﬃciency, 30 quasi-fractal n-well diode, 82, 93, 135, 139, 143, 146 regulated cascode TIA, 78 responsivity, 30, 48–51, 53–58 retrograde well doping proﬁle, 47 run length, 18 scrambling, 18 sensitivity, 22 series-series feedback, 111, 112 shot noise, 71 shunt-shunt feedback, 63, 111, 112 SML-detector, 36, 51 SOI, 34 space charge region, 28 technology scaling, 57 thermal noise, 70, 71 TIA bandwidth, 62, 65, 66 transceiver, 15 transimpedance ampliﬁer, 14, 17, 61, 82, 93, 97 transimpedance gain, 61, 64 transimpedance-bandwidth product, 67 two-dimensional model, 46 wavelength, 52

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