Nanometer CMOS RFICs for Mobile TV Applications (Analog Circuits and Signal Processing)

Nanometer CMOS RFICs for Mobile TV Applications ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES Consulting Editor: Moham...

Author: Ahmed A. Youssef | James W. Haslett

68 downloads 964 Views 3MB Size Report

This content was uploaded by our users and we assume good faith they have the permission to share this book. If you own the copyright to this book and it is wrongfully on our website, we offer a simple DMCA procedure to remove your content from our site. Start by pressing the button below!
Report copyright / DMCA form

DOWNLOAD PDF

Nanometer CMOS RFICs for Mobile TV Applications

ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES Consulting Editor: Mohammed Ismail. Ohio State University

For other titles published in this series, go to http://www.springer.com/series/7381

Ahmed A. Youssef James Haslett ●

Nanometer CMOS RFICs for Mobile TV Applications

Ahmed A. Youssef University of Calgary Department of Electrical & Computer Engineering Theoretical & Empirical Software 2500 University Drive Calgary AB T2N 1N4 Canada [email protected]

James Haslett Department of Electrical and Computer Engineering University of Calgary Calgary Canada [email protected]

ISBN 978-90-481-8603-7 e-ISBN 978-90-481-8604-4 DOI 10.1007/978-90-481-8604-4 Springer Dordrecht Heidelberg London New York Library of Congress Control Number: 2010922879 © Springer Science+Business Media B.V. 2010 No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)

TO OUR FAMILIES

Preface

People often ask me why I chose to publish this work. Primarily, this book was motivated by my experience in industry after having been in the academic world for many years. We often hear about the need to bridge the gap between industry and academia, but one can easily intellectually understand something without having experienced it first hand. I lived in the gap between the academic and industrial worlds for some time and saw how people on both sides can target the same application and work toward the same goal, but do so from completely different angles. Radio frequency (RF) IC designers in the industry do not have the luxury of time to dig through the extensive publications that flood their field to understand the latest developments related to their own circuits or systems. Researching the many areas related to RF circuit design such as device models, fabrication technology, signal analysis, and communication theory proves to be an insurmountable task. Therefore, their circuit analysis, and thus optimization, can be easily curtailed because of the time restraints inherent in the semiconductor industry. On the other hand, university students of all levels are often so flooded in their own studies that they lose the practical sense needed to make their research seem applicable to realworld products – the world of RFIC design becomes dry and intangible. The main purpose of this book is thus to help bridge the gap between academia and industry in the area of nanometer CMOS RFIC design for one of the latest, most dynamic wireless applications, the mobile TV. In 2005, South Korea became the first country in the world to offer mobile TV reception. Japan and several European countries soon followed, and the United States and Canada are not far behind. This book explores the design, implementation, and demonstration of highly linear, low power, RFICs that facilitate the integration of TV service into cellular phones using nanometer CMOS technologies. Emphasis is made on how to break the trade-off between power consumption and performance (linearity and noise figure) by optimizing the mobile TV front-end dynamic range in three hierarchical levels: the intrinsic MOSFET level, the circuit level, and the architectural level.

vii

viii

Preface

The objectives of this book are as follows: –– Develop a complete system analysis to extract the target specifications of the mobile TV RFIC signal path. The RF front-end architectures and circuits described in this book are based on this analysis. –– Discuss the challenges associated with designing wide dynamic range, lowpower, broadband CMOS low-noise amplifiers (LNAs). The main CMOS LNA topologies are analyzed in the context of their dynamic range. The modern noise-cancelling CMOS amplifiers are discussed and their limitations in achieving the requirements of the mobile TV receiver are described. The book also presents several new circuit design techniques proposed to improve the dynamic range of current noise-cancelling LNAs. –– Provide methods for implementing the gain variation function in CMOS amplifiers. Both the analog and digital approaches are considered. –– Present the RF passive gain control technique as a low-power solution to help mobile TV receivers achieve their stringent linearity requirements and present the linearization circuits needed for this technique. –– Expose students in academia to the practical steps required to develop successful mobile TV products: the physical realization of three 65 nm CMOS test chips is described and the associated challenges are highlighted, the bias generator circuits that allow the developed circuits to withstand process and temperature variations are discussed, and lastly, the test setup required to characterize the designed test boards in the lab is presented. Although the RFIC specifications developed in this book target the DVB-H mobile TV standard, the solutions described can be scaled to any other digital TV standard or any standard requiring a wide dynamic range receiver. Finally, I am much obliged to mention the various individuals who helped make this book possible. I would first like to thank James Haslett, my co-author, advisor and mentor for his innumerable contributions to my knowledge of this field. I will also always be indebted to Professor Hani Ragai, who introduced me to VLSI circuit design while I was an undergraduate student and inspired me to pursue my study of it. Additionally, I would like to thank my colleagues Edward Youssoufian and Janakan Siva (Newport Media Inc.), Aly Ismail (Ultrawave Labs), and Ahmet Tekin (Aydeekay Inc.). All of them have contributed to the material in this book in so many ways. Very special thanks go to Hassan Elwan for transferring some of his baseband circuit design knowledge to me. The text was reviewed and edited by Carey Williamson (University of Calgary), Igor Filanovsky (University of Alberta), and Mohammed Ismail (Ohio State University). I am indebted to all of them for their kind assistance. I must also thank the staff at Springer, particularly Cindy Zitter for their assistance. Finally, this work would not have been possible without the support of my wife, Marwa. I thank her for her encouragement and patience. November 2009

Ahmed Youssef

Contents

1 Introduction and Overview....................................................................... 1.1 Mobile TV Architectures.................................................................... 1.2 DVB-H Mobile TV System Definitions............................................. 1.3 Scope of This Book.............................................................................

1 3 9 12

2 Wideband CMOS LNA Design Techniques............................................. 2.1 Dynamic Range Limits in MOSFETs................................................. 2.1.1 The Noise Limit...................................................................... 2.1.2 The Distortion Limit............................................................... 2.1.3 Dynamic Range Trade-offs in CMOS..................................... 2.2 Traditional CMOS LNA Topologies................................................... 2.2.1 R-CS Amplifier....................................................................... 2.2.2 CG Amplifier.......................................................................... 2.2.3 SFB Amplifier......................................................................... 2.2.4 L-Degenerate Amplifier.......................................................... 2.3 Recent Trends in Wideband CMOS LNAs......................................... 2.3.1 Current Reuse Amplifiers....................................................... 2.3.2 L-Degenerate Wideband Amplifiers....................................... 2.3.3 Capacitive Cross-Coupled CG Amplifiers.............................. 2.3.4 Noise and Distortion Cancelling Amplifiers........................... 2.4 Techniques to Improve the Wideband LNA Dynamic Range............. 2.4.1 Wideband CMOS LNA State-of-the-Art................................ 2.4.2 New Low-Power Noise-Cancelling Technique....................... 2.5 Chapter Summary...............................................................................

15 16 16 19 25 26 26 28 28 31 33 34 36 37 39 43 43 45 56

3 Nanometer CMOS LNAs for Mobile TV Receivers................................ 3.1 Requirements of the LNA in Mobile TV Receivers........................... 3.1.1 DVB-H RF Front-End Specifications..................................... 3.1.2 DVB-H LNA Performance Requirements.............................. 3.2 A 65 nm CMOS Wideband LNA Prototype....................................... 3.2.1 LNA Core Circuit.................................................................... 3.2.2 DC Bias Generator Circuits.................................................... 3.2.3 Multi-Mode Test Buffer Circuits............................................

59 59 60 61 63 64 71 77 ix

x

Contents

3.3 Experimental Results.......................................................................... 3.3.1 Test Environment Descriptions............................................... 3.3.2 Measurement Results.............................................................. 3.4 Chapter Summary...............................................................................

81 81 84 91

4 RF Attenuator Linearization Circuits..................................................... 4.1 The Necessity of RF Automatic Gain Control.................................... 4.1.1 RF Gain Control in Mobile TV Receivers.............................. 4.1.2 Gain Control Circuit Techniques............................................ 4.2 RF Gain Control System Analysis...................................................... 4.2.1 Case One: DR Is Limited by the Clipping Level.................... 4.2.2 Case Two: DR Is Limited by the IIP3 Level........................... 4.3 Highly-Linear RF Front-End Architectures........................................ 4.3.1 Linear RF Architectures.......................................................... 4.3.2 Gain Step Size......................................................................... 4.4 Design of the Binary-Weighted RF Attenuator.................................. 4.4.1 Topology Evolution................................................................. 4.4.2 Binary-Weighted RF Attenuator Design................................. 4.4.3 Gain Control Logic Circuits.................................................... 4.5 Practical Considerations...................................................................... 4.5.1 RF Attenuator & LNA Integration.......................................... 4.5.2 Package Bond Wire Coupling................................................. 4.6 A 65 nm CMOS RF Passive Attenuator............................................. 4.6.1 The Fabrication....................................................................... 4.6.2 Measurement Results.............................................................. 4.6.3 Comparison with Simulations................................................. 4.7 Chapter Summary...............................................................................

95 95 95 96 98 99 100 103 103 104 106 106 108 112 117 117 120 123 123 124 127 130

5 Wide Dynamic Range Mobile TV Front-End Architecture................... 5.1 Mobile TV Front-End with Automatic Gain Control......................... 5.1.1 Self-Contained RF AGC Control............................................ 5.1.2 DVB-H RF Front-End with AGC Algorithm.......................... 5.1.3 AGC RF Level Indicator Circuit............................................. 5.2 A 65 nm CMOS RF Front-End Prototype.......................................... 5.2.1 The Fabrication....................................................................... 5.2.2 Measurement Results of the AGC Test................................... 5.3 Chapter Summary...............................................................................

131 131 131 132 133 135 135 136 138

6 Summary and Conclusions....................................................................... 6.1 Summary and Conclusions................................................................. 6.1.1 Digitally-Controlled Variable-Gain LNA............................... 6.1.2 Digitally-Programmed RF Passive Attenuator........................ 6.1.3 Wide Dynamic Range Mobile TV Front-End.........................

139 139 139 140 142

Contents

xi

6.2 Further Research Areas....................................................................... 143 6.2.1 System Studies........................................................................ 143 6.2.2 Circuit Studies......................................................................... 144 References......................................................................................................... 145 Index.................................................................................................................. 153 Author Biographies.......................................................................................... 157

List of Symbols and Abbreviations

Acronym

Definition

AC ADC AGC BiCMOS BPF BSIM CG amplifier CMMB CMOS CSP dB dBm DC DCR DMB-T DR DTV DVB-H DVB-T f fs ft FB FE FOM GHz GSM Hz IF IIP3 IP3

Alternating Current Analog-to-Digital Converter Automatic gain control Bipolar and CMOS capable process Band-Pass Filter Berkeley Short-Channel IGFET Model Common-gate amplifier China Multimedia Mobile Broadcasting Complementary Metal Oxide Semiconductor Chip scale package Logarithmic ratio of power Logarithmic ratio of power referenced to 1 mW Direct Current Direct Conversion Receiver Digital Multimedia Broadcast-Terrestrial Dynamic range Digital TV Digital Video Broadcasting-Handheld Digital Video Broadcasting-Terrestrial Frequency Sampling frequency Unity current gain frequency Feedback Front-end circuit Figure of merit Gigahertz Global System Mobile communications Hertz Intermediate frequency Input-referred IP3 Third-order intercept point xiii

xiv

IM3 IR ISDB-T low_th_n low_th_p kHz LC LG LNA LO LPF MER MIM MOSFET NF NMOS OFDM Opamp OTA PMA PMOS Q QAM QFN R-2R R-CS amplifier RF RFLI RL rms S11 S12 S21 S22 SAW SFB amplifier SMA SNR SOC up_th_n up_th_p U/D UHF


Third-order intermodulation distortion Image rejection Integrated Services Digital Broadcasting-Terrestrial Negative lower threshold voltage of the RFLI Positive lower threshold voltage of the RFLI kilohertz Inductor–capacitor circuit Loop gain Low-noise amplifier Local Oscillator Low-pass filter Modulation Error Rate Metal–Insulator–Metal capacitor Metal-Oxide-Semiconductor Field-Effect Transistor Noise figure N-channel MOSFET Orthogonal Frequency Division Multiplexing Operational amplifier Operational transconductance amplifier Post-mixer amplifier P-channel MOSFET Quality factor Quadrature amplitude modulation Quad Flat No-Lead Package Analog-to-digital converter topology Resistive terminated common-source amplifier Radio frequency RF level indicator Load resistor Root-mean-square Input reflection coefficient Reverse transmission coefficient Forward transmission coefficient Output reflection coefficient Surface acoustic wave Shunt feedback amplifier Sub-Miniature version A Signal-to-Noise Ratio System On Chip Negative upper threshold voltage of the RFLI Positive upper threshold voltage of the RFLI Undesired-to-desired-signal Ultra High Frequency


Vgs vgs VGA VHF WLAN

DC gate–source voltage Small signal AC gate-source voltage Variable Gain Amplifier Very High Frequency Wireless Local Area Network

xv

Chapter 1

Introduction and Overview

Digital TV (DTV) has currently been deployed in several countries around the world [1]. Where in use, digital TV has many advantages over traditional analog TV such as better image and sound quality, increased number of channels, and interactive multimedia services. Additionally, digital TV standards would facilitate the implementation of video reception (i.e., TV) in cellular phones and multimedia enabled handheld devices [2]. In broadcast DTV, the two most dominant standards are DVB-T (Digital Video Broadcasting-Terrestrial) in Europe and ISDB-T (Integrated Services Digital Broadcasting-Terrestrial) in Japan and Brazil. Both of them are based on OFDM (Orthogonal Frequency-Division Multiplexing) modulation. Using OFDM, the broadcast tolerates both fading and multipath [3, 4], which until now have generated unacceptable obstacles for mobile reception of conventional analog TV. Since both ISDB-T and DVB-T standards are for full screen TV, the data transmission rates are too large for mobile TV use. Each of these standards was thus modified differently to try to make it applicable for use in mobile TV applications. In the Japanese standard, a mobile TV standard called ISDB-Tss (ISDB-T single segment), which uses a lower bandwidth than that of the broadcast ISDB-T, was developed. It uses 430 KHz bandwidth in a 6 MHz channel divided into 13 segments as shown in Fig. 1.1. The standard is defined mainly for a portion of the UHF band, 440–740 MHz, to allow interoperability with the 900 MHz band for GSM (Global System Mobile). In contrast, the European standard was modified to develop a mobile version called DVB-H (DVB – Handheld), which uses time divided transmission called “time slicing”, where each burst transmission is followed by a longer off period. Time slicing operation is shown in Fig. 1.2. The first DVB-H field trials were held in Europe and used the UHF band (470–862 MHz). Since then, DVB-H has also been targeted for deployment in North America using the L-band spectrum between 1670 and 1675 MHz. There has also been discussion of reallocating European L-band frequencies for DVB-H services. Finally, several other mobile TV standards, both terrestrial and satellite, are emerging world-wide such as MediaFLO [2] and ATSC-mobile in the USA, DMB-T and satellite based CMMB in China and T-DMB [1] in Korea.

A.A. Youssef and J. Haslett, Nanometer CMOS RFICs for Mobile TV Applications, Analog Circuits and Signal Processing, DOI 10.1007/978-90-481-8604-4_1, © Springer Science + Business Media B.V. 2010

1

2

1 Introduction and Overview 1 segment = 430 KHz

6 MHz Channel

12 10

8

6

4

2

0

1

3

5

Guard band

7

9

11

Guard band

Segment 0 is dedicated for mobile use. The other 12 segments are used for high bit rate broadcast

Fig. 1.1 Transmissions of ISDB-Tss broadcast

0.25s 0.75s (OFF)

Burst Transmission

Data Rate 5 Mbps (QPSK 1/2)

Effective Data Rate = 400 kbps Fig. 1.2 Time slicing in DVB-H

A key component of the next generation of mobile TV-enabled cellular phones is the silicon receiver that integrates all the TV tuner functions into a silicon die. Low-cost, low-power and small physical size are required by cellular phones and other multimedia mobile products. These features necessitate moving into a low-cost technology and to a smaller geometry. Nanometer CMOS technology is thus essential to achieve these requirements by facilitating the integration of more high-performance RF (Radio Frequency) functions into a single piece of silicon. In addition to the power, cost, and size requirements, all sensitivity, blocking

1.1 Mobile TV Architectures

3

8 Economic recession period

6 Paper numbers at ISSCC

4

WLAN application Mobile TV application

2 0 2003

2005

2007

Year

Fig. 1.3 Comparison between the numbers of research papers at the ISSCC conference for the last five years for WLAN and mobile TV applications

and intermodulation specifications of different standards should be met without sacrificing the optimality of the solution. For the past few years, the development of mobile TV systems has been under extensive study in both industry and university research communities. The first paper addressing the challenges of implementing mobile TV reception in cell phone front-ends was published in 2004 at the world-class International Solid-State Circuit Conference (ISSCC). Since then, the number of papers on this topic has increased rapidly. Figure 1.3 shows a comparison between the number of published papers in the area of WLAN (Wireless Local Area Network) applications and the number of published papers in the area of mobile TV applications in the last 5 years at ISSCC. As shown in this chart, since 2006 the topic of mobile TV has started to attract research interests and is expected to continue doing so in the future.

1.1 Mobile TV Architectures The broadband nature of the TV band introduces many technical challenges in the design of silicon tuners needed for mobile TV. To support digital TV reception, typical broadcast TV tuners need to address issues such as coverage of several octaves, rejection of interference at integer multiples of the wanted signal, and inband and out-of-band image rejection. These issues have been extensively addressed in the technical literature [5–10]. The traditional TV-can tuner architecture uses a passive LC tracking filter and an IF SAW (surface acoustic wave) filter as shown in Fig. 1.4. The tracking filter prevents image mixing and harmonic mixing which are described in Fig. 1.5 [8]. Image mixing is the process whereby the negative frequency component folds into the baseband in the down-conversion mixing process. Harmonic mixing is the

4

1 Introduction and Overview on-chip

RF input

RF-VGA Tracking Filter

x

SAW IF output

Recently, an elaborate varactor was proposed to facilitate the tracking filter integration [21]. Also, a selectable on-chip bipolar filter was used in [14] to suppress the odd harmonics of LO.

VGA: Variable Gain Amplifier Channel Selection

Fig. 1.4 Conventional TV-can tuner architecture

LO harmonics

Harmonic Conversion

DC

LO

2LO

3LO

Desired signal Image

Blockers

Image Conversion

DC IF

LO-IF

LO

LO+IF

48-862 MHz

Fig. 1.5 Harmonic and image conversion in wideband receiver

process whereby undesired bands fold into the desired signal due to LO (Local Oscillators) harmonics. Harmonic mixing should be addressed by conventional tuners since the conventional TV broadcast uses a wide spectrum range from VHF to UHF. Therefore, the undesired TV bands may fold into the desired TV signal. Although TV-can tuner architecture meets the broadcast TV standard specifications, it needs many discrete components such as coils, varactors and SAW filters that run contrary to the mobile TV application requirements. However, it has a great advantage of reducing the linearity requirement of the RF front-end circuit (i.e., low-noise amplifiers (LNAs) and down-conversion mixers).


5

RF input

On-chip ~ 1GHz

RF-VGA BPF

x

SAW

x

IF output

Recently in [10], this filter was replaced by a digital IR algorithm in the baseband and the SAW filter (1GHz) was also replaced by a digital filter

Channel Selection

Fig. 1.6 Up-down type double-conversion architecture

Furthermore, the high IF frequency of TV-can architecture requires high sampling rate at the following ADC (Analog-to-Digital Converter), which tends to increase the power consumption of the ADC. Thus, this solution is not considered power efficient. In an effort to eliminate the LC tracking filter, up-down double-conversion approaches have been proposed [9–13]. Shown in Fig. 1.6 is the up-down type double conversion architecture, where the first IF frequency is chosen to be 1 GHz or above so that the LO harmonics will be out of the TV band. Since the image is two times the IF frequency away from the desired signal, an LPF (low-pass filter) in front of the tuner is used to attenuate it. The SAW filter, at the first IF path, is used to remove the second mixer image. This architecture is more amenable to integration than the first one. However, increased complexity of circuits and the necessity of using a SAW filter are still obstacles for low-cost and low-power solution tuners. Also, removing the RF tracking filter in this architecture usually complicates the front-end circuit design (it needs to handle the whole TV spectrum as an input). The discussion above illustrates how the choice of a TV architecture along with understanding the limitations of current technologies influences the RF front-end performance requirements (see Fig. 1.7). Integrated TV tuners should meet a set of requirements quite different from those of the existing can-tuners. The task of suppressing harmonic mixing and images on-chip contributes greatly to the complexity of the mobile TV tuner architecture. A more integrated TV tuner architecture uses a selectable on-chip bandpass filter for suppression of the odd harmonics of the LO and a polyphase filter for image rejection [14]. However, this filter requires high power for active filtering, and the in-band image rejection is still limited by the gain and phase imbalance. A recent architecture, published last year, overcomes these challenges by using the polyphase mixer for harmonic rejection and a digital filter for image rejection [15]. In order to clearly and succinctly quantify the impact of the solutions described in this book on the overall performance of mobile TV systems, all recent published mobile TV receivers are simplified in two main architectures. The first one is the direct-conversion architecture (DCR) (also called zero-IF) and the second

6

1 Introduction and Overview Both covered in section 1.1

Tuner Architecture

Technology Limitation

+

covered in section 1.2

+

Mobile TV Standard

RF Front-end Specs

Fig. 1.7 RF front-end specification control factors On-chip

RF input

RF-VGA

x

LPF I

Baseband output

BPF Q

x

LPF

Channel Selection

Fig. 1.8 Direct-conversion architecture

one is the low intermediate frequency (low-IF) double conversion architecture. The direct-conversion architecture, considered one of the most efficient architectures that can be used for mobile TV application, is shown in Fig. 1.8. Since there is no image problem (the IF frequency is zero), simple on-chip RF circuits can be used. However, this architecture suffers from the well-known flicker noise and the DC offsets problems [16]. The information around the center frequency can be lost due to these problems, with the degree of loss depending on the type of modulation scheme. In other words, some modulation schemes inherently can provide a robust solution for the DC offset problem in the DCR architecture. Womac et al. [17] have shown recently that a high pass pole at 300 Hz removes only one OFDM subcarrier from the DVB-H signal, which means that the information


7 on-chip

RF input

RF-VGA

x

0

o

I

+

BPF

LPF

Q

x

o

90

IF output

Image rejection mixer [30]

Channel Selection

Fig. 1.9 Low-IF architecture

can still be recovered using digital signal processing in the demodulator. Accordingly, we can say that although this architecture cannot be considered a good candidate for the traditional analog TV tuner, it may be used in some of the digital TV tuners that are based on the OFDM modulation. A low-IF receiver (shown in Fig. 1.9) with an image rejection mixer [18] is a favorable architecture when the information loss in direct conversion is not tolerable. In this case, usually the image rejection ratio is limited to less than 40 dB due to component mismatch in the image rejection mixer. One of the main advantages of this architecture is that the low IF (~4 MHz) facilitates the digital implementation of the IF channel filtering so that it can be programmed for different channel bandwidth. Additionally, the image can be suppressed in the digital domain. The mobile TV receivers reported in the literature indicate that the DCR architecture is the chosen candidate for DVB-H tuners [17, 19–22]. In the meantime, the low-IF architecture is often used for ISDB-Tss tuners as reported in [23–29]. In this book, the DCR architecture is selected to be the candidate that best facilitates implementing the TV reception function into DVB-H based cell phones. As mentioned earlier, this architecture has the advantages of reduced complexity, fewer external components, and no need for image suppression. A summary of the recent published papers on receivers (RF front-end and baseband) for analog/digital broadcast and mobile TV application is shown in Table 1.1. The main features of each receiver including the harmonics, and image rejection techniques, the dissipated power consumption, and the noise performance are briefly described. The table gives a good overview of the research efforts that have been made to produce low-cost, high-performance tuner chip sets. Knowledge of these systems helps in creating new solutions to implement the RF tuner functions. Unless the system requirements are well defined and well understood, coming up

8

1 Introduction and Overview

Table 1.1 State-of-the-art of analog/digital TV receivers

Mobile TV Standards

Research paper

Technology

Architecture

Image rejection

Harmonic rejection

Noise figure (dB)

Power (mW)

Stevenson 2007 [19]

0.35 µm BiCMOS

DCR

IR mixer a (75 dB)

Up/down

6

330

Gupta 2007 [23]

0.18 µm CMOS

Low-IF

Digitally (61 dB)

Polyphase b mixer

4

540

Fillâtre 2007 [24]

0.25 µm BiCMOS

Low-IF

IR mixer and polyphase filter c (60 dB)

LC tracking filter

5

750

0.5 µm BiCMOS

Low-IF

IR mixer and Polyphase filter

Not mentioned

2.7

87f

0.25 µm BiCMOS

DCR Zero-IF

SAW

2.6

61

0.18 µm CMOS

DCR Zero-IF

Not mentioned

3.5

259

0.35 µm BiCMOS

DCR Zero-IF

SAW

3.6

340

0.18 µm CMOS

Low-IF

IR mixer and polyphase filter (56 dB)

Not mentioned

3

100

Zero-IF

Not mentioned

4.3

185

Digitally (60 dB)

Up/down

6.7

750

Selective LNA

9

150

SAW

~11

160

d

Sakai 2007 [25] g

Peluso 2006 [20] h

Vassiliou 2006 [21] i

Womac 2006 [17] j

Kim 2006 [26] k

Kim 2006 [22] l

Heng 2005 [27] m

Rumpt 2005 [28] o

Azuma 2004 [29]

a

0.18 µm CMOS

DCR

0.25 µm CMOS

Low-IF

BiCMOS

Low-IF

BiCMOS

Low-IF

e

n

(FPHP) filter

p

IR mixer and polyphase filter (37 dB)

Achieved 75 dB IR with using 2 IF-SAWs. On-chip RF tracking filter has been used also for harmonic rejection 72 dB. An auto-calibration technique is implemented to boost the IR. d Dedicated to the ISDB-T Mobile TV standard. e Adaptive control technique has been proposed for power reduction. f IR mixer is based on Hartley architecture [30]. g Dedicated for Media-Flo Mobile TV standard (698−746 MHz). h Dedicated for DVB-T broadcast TV standard. i Dedicated for DVB-H Mobile TV standard. j Dedicated for ISDB-T/T-DMB Mobile TV standard. k Dedicated for DVB-H Mobile TV standard. l Dedicated for NTSC, PAL, and SECAM standards. m Dedicated for PAL, NTSC, SECAM, DVB-H standards. n FPHP: fully integrated programmable high precision filter with a dynamic image suppression system. o Dedicated for ISDB-T Mobile TV receiver. p IR mixer is based on Hartley architecture [30]. b c

1.2 DVB-H Mobile TV System Definitions

9

with innovative ways that enable the multimedia reception to cell phones becomes difficult and risky. The following section presents the system definitions of the DVB-H mobile TV standard and discusses the associated challenges.

1.2 DVB-H Mobile TV System Definitions Among mobile TV standards, DVB-H poses the most stringent sensitivity (the minimum signal that a receiver can detect) and blocking requirements (the robustness of a receiver to interferers). The standard specifies a set of interferer patterns to test the conformity of the tuner [31, 32]. These reception conditions have significant impacts on the tuner specifications as will be described below. The interferer patterns are classified into two categories. One specifies the selectivity test patterns to check the immunity to a single analog or digital TV interferer (shown in Table 1.2). The other category defines the linearity test patterns (shown in Table 1.3), which check the immunity to two analog or digital interferers. In those test patterns, there are some main mechanisms that can create distortion or noise components on the desired channel: 1. The intermodulation among sub-carriers on the interferer channel 2. The clipping that might happen due to a large interferer channel 3. The cross-modulation among sub-carriers on the interferer channel and on the desired channel [33] 4. The decrease in the small-signal gain (gain compression) due to the third order nonlinearity [16] 5. The mixing between interferer components and noise components of the local oscillator output, harmonic mixing [16]. The receiver dynamic range (DR) is generally defined as the ratio of the maximum input level that the receiver can tolerate (DR upper end) to the minimum input level at which the receiver provides the required sensitivity (DR lower end). All of the above described distortion mechanisms can limit the receiver dynamic range in one way or another depending on the system design parameters and its performance. Mechanisms One through Four are discussed in detail throughout this book. Most of the design recommendations that have been presented in this book to optimize the DVB-H receiver DR were based on these four mechanisms. Since mechanism Table 1.2 Selectivity test patterns of the DVB-H standard Pattern Modulation of Interferer Interferer Location U/D a (dB) S1 Analog N+1 38 N + K (K ¹ 0, 1) 40 N+1 29 S2 Digital 40 N + K (K ¹ 0, 1) a U: undesired interferer power (on each channel), D: desired channel power.

U (dBm) −35 −28 −35 −28

10


Table 1.3 Linearity test patterns of the DVB-H standard Pattern Modulation of Interferer Interferer Location U/D a (dB) L1 Digital and analog N+2 45 N+4 L2 Analog N + 2, N+4 45 L3 Digital N+2, N+4 40 Desired channel modulation: 16QAM. a U: undesired interferer power (on each channel), D: desired channel power.

U (dBm) −35 −35 −35

Five is controlled by other receiver blocks (the frequency synthesizer) that are out of the scope of this book, it is highlighted very briefly. The lower end of a tuner DR is the sensitivity level, which depends on the tuner noise figure (NF) (a measure of degradation of the output (signal-to-noise) ratio caused by the tuner circuits). In other words, the sensitivity requirements always set the target noise performance of a receiver. For DVB-H standard, the sensitivity of the tuner for 16QAM modulation (Quadrature amplitude modulation) is −86.6 dBm and hence the tuner NF is required to be below 5 dB. Typically, a receiver NF is controlled by the RF front-end noise performance and specifically by the first stage of the RF front-end, which is the low noise amplifier (LNA). This can be seen using Friis formulas as in [16]. The tuner NF is given by

NFtuner = NFLNA +

NFMixer − 1 GLNA

(1.1)

where NFLNA and GLNA represent the noise figure and available power gain of the LNA respectively. NFMixer is the mixer noise figure. As will be shown, achieving a competitive noise performance (NF < 3 dB) for an LNA that consumes low power and supports the broadband nature of TV bands is one of the biggest challenges. The other limit (upper end) that sets the receiver DR is the linearity figure of merit. For the DVB-H receiver, this figure of merit is set by the linearity pattern (L3) [25] as shown in Table 1.3. A graphical illustration of this pattern is given in Fig. 1.10. Due to the third-order nonlinearity, two digital TV interferers that are 40 dB larger than the desired signal can generate a third-order intermodulation product on top of the desired signal. The corruption of the desired signal due to third order intermodulation of two nearby interferers is quantified by “third order intercept point” (IP3). This parameter is measured by a two-tone test as shown in Fig. 1.11. The required input IP3 (IIP3) according to the interferer level can be calculated by [16]

IIP3 =

1 (3Pundesired − Pdesired + S / N ) 2

(1.2)

where Pundesired is the interferer power level, Pdesired is the desired signal power, S is the signal power and N is the noise power. Using L3 pattern parameters and

1.2 DVB-H Mobile TV System Definitions

Desired Signal

11

Digital Interferer

Digital Interferer

−35 dBm

−35 dBm

N+2 (N+16MHz)

N+4 (N+32MHz)

f1

f2

−75 dBm U/D 40 dB N IM3

2f1-f2

Freq.

f

Fig. 1.10 DVB-H L3 pattern requirements

Vout (dB)

DR is limited by the distortion Low-distortion region (0.1%-0.001%)

DR is limited by the noise 3 dB/dB

IM3 1 dB/dB

DR and IM3 is maximum here

IP3 is the IM3 Intercept point

Noise

IM3=1

IP3

Vin (dB)

Fig. 1.11 Third-order intermodulation distortion

Eq. 1.2 the IIP3 of DVB-H tuners is found to be equal to −8 dBm, where the required S/N is supposed to be 13.7 dB for 16QAM modulation. One of the important characteristics of mobile TV standards is that achieving this level of linearity is not required at the receiver sensitivity level. This can be further clarified by finding the NF of the DVB-H tuner in the L3 pattern reception scenario. The NF can be given by:

NF = Psignal − 10 log(kTB) − (S / N )

(1.3)

where k, T, and B represent Boltzman’s constant, temperature, and channel bandwidth, respectively.

12


Since the desired channel power of L3 pattern is −75 dBm, the required tuner NF can be estimated to be 15 dB. Therefore, achieving the required −8 dBm IIP3 can come at the expense of the tuner noise performance. As will be shown, this has a great impact on the design of the mobile TV RF front-end architectures. Additional challenges include the presence of GSM interference from a cell phone up-link in DVB-H. GSM handsets incorporating DVB-H may suffer from increased noise floor if the transmitter power amplifier noise leaks into the DVB-H signal band. Also, a +33 dBm GSM carrier may block the desired TV signal and desensitize the tuner. Given the requirements for low cost and low power the above specifications call for careful design and innovation techniques.

1.3 Scope of This Book As previously mentioned, the goal of this book is the exploration, design, implementation, and demonstration of wide dynamic range, low-power, RFICs that facilitate integrating TV reception into cellular phones and other hand-held devices. Towards this goal, a mobile TV receiver that can meet the DVB-H mobile TV standard specifications is proposed as a case study to illustrate the step-by-step design progression and implementation of the RFICs described in the following chapters. As shown in Fig. 1.12, an RF front-end, emphasized in the dashed box, is composed of a variable-gain LNA, a programmable RF passive attenuator and an RF power detector. The front-end amplifies the input RF signal (RFin) over frequencies ranging from 470 to 862 MHz and sends them to a quadrature passive mixer. A detector performs automatic gain control (AGC) to meet the necessary level of carrier-to-noise ratio or carrier-to-intermodulation products (C/I) over the desired bandwidth. The baseband chain consists of a post-mixer amplifier (PMA), and a SD analog-to-digital converter (ADC). The baseband circuits’ performance [34, 35] facilitates extracting the RF front-end circuit specifications needed for DVB-H mobile TV receivers. 65 nm CMOS technology was chosen for the implementation as it allows an exploration of the impact of using nanometer CMOS processes on designing wide dynamic range RFICs. Since the book deals specifically with the circuit design techniques needed to improve receiver dynamic range, the dynamic range physical limits have to be defined. Basically, a receiver’s dynamic range can be limited by the third-order intermodulation distortion, the clipping level, or the phase noise performance. The dynamic range optimization techniques discussed in this book will focus only on the first two. Hence, the RF building blocks which might affect the receiver phase noise will be highlighted very briefly (i.e., the mixer and the voltage controlled oscillator (VCO)). This book contains six chapters: Chapter 2 presents the challenges of achieving low noise figure in wideband CMOS LNAs. It begins by reviewing the MOSFET

1.3 Scope of This Book

13

RF Detector

Quadrature Passive Mixer

Post Mixer Amplifier

PMA

Σ∆ADC

ADC I

RFin LNA RF Attenuator

1/4

RF Front-End

Q PMA

ADC

VCO

Gain

6dB

21dB

-

Noise

1.5dB

10nv/Hz 0.5

60nv/Hz 0.5

IIP3

+20dB

-

-

Fig. 1.12 Block diagram of a DVB-H mobile TV receiver

noise mechanisms at RF frequencies and the different sources of transistor distortion with the purpose of defining the MOSFET dynamic range. Then, the main CMOS LNA topologies including the resistor-terminated common-source amplifier (R-CS), shunt feedback (SFB) amplifier, common-gate (CG) amplifier, and wideband inductively degenerated (L-degenerate) amplifier are analyzed and discussed in the context of their dynamic range and their applicability for mobile TV application. The recent noise-cancelling CMOS LNAs are also presented and solutions to design an LNA that can meet the DVB-H standard requirements are given. Chapter 3 presents a silicon prototype of a noise-cancelling LNA that can meet the mobile TV standard requirements. This chapter introduces the reader to the challenges associated with the practical realization of a mobile TV LNA in 65 nm CMOS technology, including the MOSFET low output resistance, the high resistivity of the polysilicon material, the increased substrate coupling, and the use of a digital transistor layout that is not optimized for RF operation. The bias circuit generators as well as the measurement environment are also discussed in this chapter. Chapter 4 continues by describing the use of an RF automatic gain control technique to enhance receiver linearity. This chapter discusses the two possible ways needed to achieve gain control in RF front-ends; namely, by active gain control through a variable-gain LNA or by passive gain control through a programmable passive attenuator. The chapter ends by presenting measurement results of a prototype of

14


an RF passive linearization circuit in 65 nm CMOS technology. Chapter 5 describes a wide dynamic range RF front-end architecture implementation with an AGC algorithm. Chapter 6 concludes by summarizing the RFICs developed in this book and outlining further areas of research required to finalize the mobile TV tuner. Finally, it should be stated that some of the discussions in these chapters rely on knowledge of areas outside the scope of this book. Readers are therefore encouraged to refer to the references recommended throughout the text for further study.

Chapter 2

Wideband CMOS LNA Design Techniques

The low-noise amplifier (LNA) is the backbone of any radio frequency (RF) communication receiver. Its specifications define the overall receiver noise performance and can have deleterious effects on the overall linearity. CMOS LNAs specifically receive intense attention because they help in achieving a one-chip solution by integrating the LNA with the receiver’s baseband digital signal processing blocks that are inherently realized in CMOS technology. The one-chip solution reduces overall package cost and form factor. Moreover, it saves the power required to drive package pins in the multi-chip solution [36, 37]. Wideband LNAs are used in the receiver processing of several signal channels such as TV cable modems, multi-band mobile terminals [38], software defined radio [39, 40], and ultra-wideband applications [41, 42]. The high sensitivity required for these applications demands a noise figure below 3 dB over a wide frequency range. In the meantime these LNAs have to provide a wideband input match to a 50 W source impedance to limit reflections on a cable or to avoid changing the characteristics of the RF filter preceding the LNA. Also, they have to provide sufficient gain and good isolation. Achieving all these requirements with moderate power consumption is a challenge especially without having the benefit of using resonance input circuits and loads as is the case with narrowband LNAs. An additional requirement that was previously ignored or considered as a minor constraint in LNA design is the nonlinearity factor. In some applications like mobile TV, large blocking interferers exist nearby the desired channel requiring a very linear LNA. An LNA with a large dynamic range (DR) is key for such applications. The dynamic range of wideband amplifiers that works well in other applications like high-speed optical transceivers may not be good enough for mobile TV systems. In fact, the LNA design is one of the main challenges. In this chapter, the foundation for the design of a wideband LNA that can meet the DVB-H mobile TV specifications has been defined. To provide some background, Section 2.1 describes the fundamental physical limits of MOSFET dynamic range in CMOS. Based on this, the four traditional topologies of CMOS LNAs are


15

16

2 Wideband CMOS LNA Design Techniques

discussed. Their limitations in achieving the required noise performance over several octaves of frequency with low-power consumption are discussed in Section 2.2. The chapter continues by presenting most of the research efforts that have been made to push the state-of-the-art of wideband CMOS LNA performance. Section 2.3 presents different LNA design techniques proposed recently in the literature to improve the noise and linearity performance and to decrease the power consumption. LNAs based on noise-cancelling approaches are selected as a candidate that can achieve mobile TV requirements. New techniques are described to overcome the limitation in existing noise-cancelling techniques and hence improve the dynamic range of the current wideband LNAs. The associated theory as well as the design methodology is given in Section 2.4.

2.1 Dynamic Range Limits in MOSFETs The LNA must be able to simultaneously handle very small signals close to the noise level and very high signal levels close to the transmitter antenna. Therefore, the noise and the distortion are both important and both define the dynamic range in any device. Its lower bound is limited by the noise and the upper bound is limited by the distortion as explained in Chapter 1. Understanding different mechanisms that can control the MOSFET dynamic range helps in optimizing the CMOS LNA’s performance. In this section, the MOSFET noise mechanisms in RF are discussed with the goal of identifying the potential noise sources and presenting ways to either minimize them or minimize their contribution. The minimum noise figure NFmin that a MOSFET can achieve is briefly discussed and is used in this book as a reference to compare between different LNA topologies. This section then reviews the different sources of nonlinear distortion in a MOSFET and presents the feedback mechanism as a common technique used to reduce the transistor distortion. Throughout the discussion, the implications of using 65 nm CMOS technology are highlighted.

2.1.1 The Noise Limit This section describes different noise sources in a MOSFET including, the thermal noise, flicker noise, and substrate noise. The classical noise optimization theory is also discussed. 2.1.1.1 Noise Mechanisms in MOSFETs There are different sources of noise in a MOSFET that can control its noise performance. Since these devices are basically voltage-controlled resistors, they exhibit a channel thermal noise known as a drain noise current.

2.1 Dynamic Range Limits in MOSFETs

17

This drain noise current can be capacitively coupled through the gate-channel capacitance, and results in what is called induced gate noise. The induced gate noise current is obviously correlated with the drain noise current. However, the induced gate noise current is only relevant at very high frequencies, beyond ft /5 [43], where ft is the frequency at which the small-signal short circuit current gain is unity. For 65 nm CMOS technology where ft equals about 160 GHz, it is not expected for the induced gate noise to have that great of an impact in the overall MOSFET noise performance in commercial applications at much lower frequencies. The noise current due to drain noise and induced gate noise can be modeled as current sources as shown in Fig. 2.1, where Cgs is the gate-source capacitance, Cgd is the gate-drain capacitance, gds is the channel conductance, and gm is the transconductance. The mean-squared noise current spectral densities for these sources are

2 ind = 4 kTggdo Df

(2.1)

2 ing = 4 kTdgg Df

(2.2)

where gdo is the drain-source conductance of the transistor when the drain-source voltage vds = 0, gg = (wCgs)2/5gdo, Df is the noise bandwidth, k is Boltzman’s constant, g and d are the coefficients of the drain noise and the induced gate noise respectively (g = 2/3 and d = 4/3 for long channel devices) and T is the absolute temperature [44, 45]. Despite the fact that g and d values in nanometer CMOS have been under extensive research for the last 20 years [46–49], their exact values have not yet accurately been defined. However, most experimental papers have largely confirmed that their values increase with smaller transistor gate lengths. Some of them indicate that this is due to the channel length modulation and carrier heating because of the high electric field associated with decreasing the channel length [50, 51]. Others proclaim that their increase is due to a diffusion current that flows in the channel on the source side with associated shot noise [52, 53]. It has been reported that they are about 50% larger for 180 nm CMOS and double for 130 nm CMOS technology [49]. In this work, by comparing simulation results with measured values, we were able

Cgd

Gate

2

ing

Drain gmvgs

Cgs

2

ind

gds

Source 2 Fig. 2.1 The small-signal AC model of a MOSFET device with its noise generators. ind repre2 sents the drain noise current and ing represents the induced gate noise current

18


to show that their values increased by about 65% in 65 nm CMOS technology. g = 1.45 and d = 3 are used in this work. Another source of thermal noise in a MOSFET is the poly-gate resistor RG. Even if the gate material is highly doped, it can make a large contribution to the overall noise performance in the MOSFET, depending on the width of the gate fingers and on how far the fingers extend beyond the active area of the channel. The question that then arises is how does one quantify the contribution of each noise source to the overall noise performance of a MOSFET? Furthermore, how does one then minimize each source contribution? Referring these noise sources to the input of a MOS device as a single noise voltage generator helps in quantifying each noise generator’s effect on the overall noise behavior. The input noise voltage is called 2 = 4 kTReff Df ). the equivalent input noise voltage ( vieq This voltage can be minimized by decreasing the MOSFET overdrive voltage (Vgs − Vth) for a fixed current, where Vgs is the DC gate-source voltage and Vth is the device threshold voltage or by increasing W/L ( W is the transistor width and L is the transistor length) and the drain current. This holds true so long as the gate resistance is small. The gate resistance can be decreased by contacting the gate on both sides and using multiple gate fingers [54, 55]. Another noise source that can eventually dominate the MOSFET noise is the substrate back-gate resistance (RB). This noise is always present even if the substrate contact is shorted to the source contacts. The RB noise can be referred to the input by multiplying its contribution by (n − 1)2 where n − 1 is the ratio between the bulkback gate transconductance (gmb) to the MOS transconductance (gm) as shown in Fig. 2.2. Using sufficient substrate contacts around the transistor gate fingers can greatly eliminate the contribution of RB noise [56]. The last contribution to the equivalent input noise voltage is given by the series resistor in the source itself. Normally, this is quite small, but depends on the effective channel length. The realization of low-noise MOSFETs requires the simultaneous minimization of the four contributions. In addition to these types of noise discussed above, MOSFETs generate a 1/f flicker noise. This is due to the surface states. The flicker noise can be modeled as an input-referred noise voltage generator [57]

vieq

Reff

Cgd

RB +

Cgs gmvgs

gmbvbs

gds

vbs −

Reff = γ /gm+RG+RB(n-1)

2

(n-1)=gmb /gm ~ 0.2-0.5

Fig. 2.2 The small-signal AC model of a MOSFET with the equivalent input noise voltage generator. The total equivalent input noise voltage includes the contribution of the substrate resis2 2 tance R , the channel noise current, and the gate noise R . At high frequency ing =(Cgsw)2 vieq B G should be added. It is correlated with the noise voltage

2.1 Dynamic Range Limits in MOSFETs 2 vieqf =

19

KF Df WLCox2 f

(2.3)

where KF is a constant dependent on the device type, W and L are the transistor dimensions, Cox is the gate capacitance per unit area, f is the frequency, and Df is the bandwidth. Although most LNA designers ignore the flicker noise because of the LNA high frequency of operation, this cannot be done in cases where the LNA’s nonlinearity is taken into account. In fact due to the LNA nonlinearity, a large interferer blocker can upconvert the low frequency noise (i.e., 1/f noise) to the RF bands. Therefore, large signal noise analysis is mandatory in some cases of LNA design. In the examples described in this book, such analysis has been conducted to ensure the robustness of achieved noise performance in all wireless environment scenarios. One can note that a MOSFET with thin oxide and a large area minimize the 1/f noise. 2.1.1.2 Minimum Noise Figure In order to identify the minimum noise figure that a MOSFET can achieve, the classical noise optimization technique is reviewed very briefly. The theory shows that there is an optimum signal-source admittance (Yopt=Gopt + jBopt) for a given MOSFET that leads to the lowest noise figure. The optimum source admittance, is given by [58]

g  Yopt =  m × wCgs  K1 − jwCgs (1 − K 2)  gdo 

(2.4)

and the corresponding minimum noise figure NFmin is given by NFmin = 1 + 2g

w K1 wT

(2.5)

where K1 and K2 are technological parameters and wT = gm/Cgs. The expression in (2.4) shows that the optimum susceptance required to achieve NFmin is basically an inductor. Hence, achieving a broadband minimum noise figure is fundamentally difficult. The optimization also shows that the optimum conductance is that which balances the contribution of drain and gate noise generators. As a signal source admittance Ys = Gs + jBs deviates from Yopt, the noise figure degrades according to

NF = NFmin +

ggdo 1 (Gs − Gopt )2 + ( Bs − Bopt )2  . gm2 Gs 

(2.6)

2.1.2 The Distortion Limit In this section, we describe the main sources of distortion in MOSFETs. The linear distortion that is a result of filter action (i.e, nonlinear distortion) is not considered here as it is not a concern in LNA designs. Also, since LNAs usually deal with

20


small signal levels, we limit our discussion to low levels of distortion, on the order of −60 dB down to −100 dB. The high level of distortion that is a result of clipping is not considered. We are therefore only interested in what are called soft nonlinearities, which give a small amount of distortion. The main sources that generate soft distortions in CMOS are the transconductance (gm) nonlinear behavior and the MOSFET output resistance (ro=1/gds) nonlinearity. As will be shown, the latter has a great impact in specifying the level of distortion in nanometer CMOS. The other sources such as bulk and depletion capacitance nonlinearity are also briefly mentioned. 2.1.2.1 The Distortion Mechanisms in MOSFETs As in any nonlinear system, a MOSFET transfer function can be described by a power series: io = ao+ a1vin + a2vin2 + a3vin3 +¼ . The coefficients of this power series (ai) determine the amount of distortion that a MOSFET can generate. Among these coefficients, a3 is particularly important because it controls the third-order intermodulation distortion (IM3) at low signal levels and, thus, determines the IIP3 value. In our discussion, we will intuitively specify the main factors that can control the magnitude of these coefficients and hence can control the MOSFET nonlinearity. However, more detailed analysis and derivations about these coefficients can be found in [59]. Now, let us discuss the distortion in MOSFETs that result from the gm nonlinearity. Figure 2.3 illustrates the relation between the transconductance (gm) and the overdrive voltage (Vod) for a MOSFET with a length of 65 nm and width of 100 µm. It shows that the overdrive voltage range that is available to bias a 65 nm MOSFET in strong inversion (the square-law region) is between 200 and 320 mV. This is quite small compared to the one that is available for a 0.18 µm MOSFET, which is about 250 mV, as reported in [60]. This difference is due to the velocity gm mS 0.4

Vod = 0.32V Weak Inversion

Strong Inversion

Velocity Saturation gmsat

Vod = 0.2V

square-law region becomes smaller in nanometer CMOS

0.2 Vth

0

0.2

0.32

Vgs-Vth

Vsat

Fig. 2.3 Transconductance (gm) versus overdrive voltage (Vod = Vgs − Vth) for a MOSFET with a minimum feature length of 65 nm. Sixty-five nm CMOS models are used in this simulation (the transistor width = 100 µm)


21

saturation voltage Vsat scaling (in Fig. 2.3) as the channel length decreases. Shrinking the strong inversion region makes the simple square-law model invalid and inaccurate to represent the MOSFET operation. Furthermore, the curvature of gm curve causes a lot of distortion. The strong inversion region can be seen as where the gm curvature is inverted. The exponential of the weak inversion region curves upwards whereas flattening in velocity saturation gives a downwards curvature. As a result of this, the second derivative of the gm would go through zero and hence makes IM3 equal to zero. As an example, we measured IIP3 for a MOSFET with L = 65 nm and W = 150 µm for different values of gate-source voltages Vgs. As can be seen in Fig. 2.4, there is a Vgs value (Vgsopt) at which the IM3 would equal zero and IIP3 is maximum. However, this peak in IIP3 is very narrow and requires an accurate biasing within ±10 mV of the optimum voltage. Manually tuned bias circuits are not capable of such precision in the presence of process and temperature variations. A research effort has been made by Aparin and Larson in [60] to improve the robustness in generating Vgsopt. However, their bias circuit that can keep track of process and temperature variation while cancelling IM3 is very sensitive to the device mismatch and requires an expensive thin-oxide technology.

IIP3 (dBm)

15

Optimum gate bias (Vgsopt) required to cancel IM3

5.0

−5.0

0.25

1

Vgs (V) Fig. 2.4 Simulation results of a MOSFET IIP3 in 65 nm CMOS technology. The gate-source voltage (Vgs) has been swept between 0.1 and 1.2 V. The MOSFET has a length of L=65 nm and a width of W=150 µm. The peak IIP3 is located at the transition from the weak inversion to the strong inversion mode of operation point

22


In addition to the gm nonlinearity, a MOSFET has many more distortion components. Voltage variations at the drain or at the bulk also generate distortion. In general, the AC small-signal drain current (ids) can be expanded into the following power series in terms of the small-signal gate-source voltage (vgs) around the bias point [61]: ids = gmvgs+ K2gmvgs2 + K3gmvgs3 + govds + K2govds2 + K3govds3+ gmbvbs + K2gmbvbs2 + K3gmbvbs3 + K2gm&gmbvgsvbs + K3,2gm&gmbvgs2vbs+ K3,gm&2gmbvgsvbs2 +.... K3gm&gmb&govgsvdsvbs

(2.7)

where Kigm are the coefficients of the transconductance nonlinearity, Kigo are the coefficients of the output resistance nonlinearity and, Kigmb are the coefficients of the bulk transconductance (gmb) nonlinearity. A natural question would be how can we control these coefficients? Kigm coefficients depend on the value of the DC overdrive voltage used to bias the device (Vgs − Vth). For low distortion, a large overdrive voltage must be used. As for Kigo coefficients, they depend on the DC drain-source voltage bias Vds. These are really

Strong inversion

IIP3 (dBm)

15

5.0

RLoad = 50 Ohms

−5.0

RLoad = 15 Ohms 0.2

Vds (V)

0.8

Fig. 2.5 Simulation results for a MOSFET IIP3 with the drain-source voltage Vds sweep. The output swing varies by changing the load choke RLoad. The MOSFET has an L = 65 nm and W = 150 µm. The Vds is biased through an RF choke with ideal power supply. The power supply varies from 0.1 to 1.1 V


23

important as the output resistance of a nanometer transistor has become quite small. Figure 2.5 shows the simulated IIP3 of a MOSFET with L = 65 nm and W = 150 µm with varying drain-source voltage Vds. Two curves have been generated by changing the output voltage swing applied on the device by using two different loads. As can be seen, for relatively low output voltage swing (Rload = 15 W), the IIP3 is independent of the Vds variations. This can be explained by the fact that the IIP3 is not dominated by the ro nonlinearity. However, in the case of relatively large output voltage swing (Rload = 50 W), ro nonlinearity is brought into the picture. The fact that IIP3 improves with increasing Vds values in the strong inversion region demonstrates that ro nonlinearity heavily impacts the distortion level in this case. Another implication of dominating ro nonlinearity is that it makes the scaled transistors experience a shift of the IIP3 peak to higher current densities requiring large power consumptions to achieve high linearity. This can be seen in the plot shown in Fig. 2.6. In this plot, the Vds bias is swept and IIP3 is measured for two different transistors with L1 = 65 nm and L2 = 130 nm. Both of these have the same W/L. Also, it is noted that the longer channel provides better IIP3 value as it provides better ro linearity. As a result, moving to the 65 nanometer technology makes the design trade-offs much more difficult and very tight. In summary, as in the case of LNA design, the designer should know if the design is limited by the input nonlinearity (gm) or the output nonlinearity (ro). This will facilitate the process of IIP3 optimization.

L= 130 nm L= 65 nm

IIP3 (dBm)

5.0

L=130 nm

−5.0

L=65 nm

0.2

Vds (V)

0.8

Fig. 2.6 Simulation results for a MOSFET IIP3 with the drain-source voltage Vds sweep for two different transistors. The first has an L = 65 nm and the second has an L = 130 nm. Both transistors have the same current swing and the same W/L ratio. 65 nm CMOS models are used in both cases

24


Other sources of distortions such as the bulk and depletion capacitance distortion will not be discussed in detail as they are expected to have a very limited effect on the mobile TV LNA IIP3 described in this book. The bulk nonlinearity is governed by (gmb) and source depletion capacitances nonlinearity is governed by the squareroot characteristic in this equation [61]: Cj =

Co 1−

vin j

(2.8)

where Cj is the junction capacitance, Co is Cj at zero volts, vin is the reverse bias voltage and, F is the junction built-in voltage (0.6–0.8 V). 2.1.2.2 Distortion Reduction by Feedback The most common technique to reduce the distortion is by application of feedback. As explained in the previous section, one can decrease the distortion in a MOSFET by increasing either Vgs or Vds depending on the type of the nonlinearity that dominates. Also, smaller signals cause less distortion. Thus, one can say that in general the distortion in MOSFETs improves by decreasing the relative signal swing (i.e., vgs/Vod for the input nonlinearity), and as will be discussed that is exactly what the feedback does. Feedback reduces the relative signal swing by the loop gain value. Moreover, the distortion should also be decreased by the feedback loop gain [59]. To study the distortion while taking into account the effect of the feedback on the signal swing, let us take a single MOSFET amplifier with a series resistor Rs in the source. The amplifier is shown in Fig. 2.7. It is biased so that its IIP3 is limited by the input nonlinearity. A plot that shows the effect of changing the amplifier loop gain (gmRs) on the distortion generated by this amplifier is also shown in the same figure. The DC current is kept constant and so is the relative current swing. This means that the input voltage Vin is constant until the value of the loop gain is equal to unity and then increases with the loop gain. As can be seen in this plot for values of the loop gain larger than unity, both IM2 and IM3 decrease with the same slope of −20 dB/ decade. This is expected since the distortion should be reduced by the loop gain. A very interesting conclusion can now be made. Contrary to what we have already mentioned about the distortion in MOSFETs, the overdrive voltage (Vgs − Vth) should decrease for a fixed current to reduce the distortion for a MOSFET that is in a feedback loop. This is because in this case the effect of the increase in gm, and hence in loop gain is more important than the increase of the overdrive voltage. Although this technique can be used to improve the MOSFET IIP3 value, the improvement achieved in IIP3 won’t benefit the MOSFET dynamic range. Adding Rs leads to an increase in the thermal noise of this amplifier and hence just causes a shift in the dynamic range. This technique is used in the LNA described in the next chapter after describing a way to cancel the noise added by Rs so that the amplifier can benefit from the IIP3 boosting.


a

25

b Iout

IM

After this point VRS > Vod / 2

% 10

Vin

VRS

IM2

1.0

+ −

IM3

0.1

Rs

Same slopes

0.01 1 0.01 0.1

10

1.0

100

10

1K 100

Rs

Loop Gain

Fig. 2.7 A common-source amplifier with a series feedback resistor Rs is shown in (a) and its distortion plot is shown in (b). In this plot the second-order intermodulation distortion IM2 and third-order intermodulation distortion IM3 are calculated at different values of Rs. The relative current swing remains constant by increasing Vin at all points where loop gain is >1. The IM2 and IM3 values decrease with the same slope of −20 dB/decade after the loop gain values become larger than unity

2.1.3 Dynamic Range Trade-offs in CMOS In this section, guidelines to optimize the MOSFET dynamic range (DR) are presented. As it has been shown earlier in this chapter, there is a trade-off between the noise performance of a MOSFET and the amount of distortion that it generates. Improving the noise figure by decreasing the overdrive voltage (Vgs − Vth) at fixed current consumption directly hurts the IIP3 value (assuming that the distortion is limited by the MOSFET input nonlinearity). Although this might not be a problem when the LNAs IIP3 is relaxed according to the targeted application, it becomes a real challenge in cases where linear LNAs are required. The only factor that can be used to increase the dynamic range and relax this trade-off is the power dissipation factor. The dynamic range of a MOSFET amplifier can be given by [62]:

DR =

IIP3 µIxZ o NF − 1

(2.9)

where I is the current consumed by the amplifier and Zo is the amplifier input impedance. As shown in (2.9), increasing the MOSFET DR requires consuming more current. This can be noted by exploring the research efforts that have been made to push the state-of-the-art of LNA performance in the last 20 years. Most of the efforts were focused on inventing new circuit design techniques to reduce the power consumption in LNAs. In other words, researchers were trying to improve LNA performance in terms of dynamic range while keeping the power consumption at a

26


modest level. Although there have been many outstanding LNAs proposed, there is still a need for novel LNA designs that can satisfy the stringent requirements of some of the new emerging applications such as mobile TV. In the past couple of years LNA research has shifted to other approaches. Instead of trying to minimize the magnitude of the noise and distortion generators, efforts have focused on trying to keep them as they are but cancel their contributions. Before going into detail about this approach, the main conventional LNA topologies are reviewed in the next section to provide the background foundation needed to discuss the recent trends in CMOS LNA design.

2.2 Traditional CMOS LNA Topologies In the design of low-noise amplifiers (LNAs) in wireless receivers, there are several common goals. These include low noise figure (NF < 3 dB), reasonable gain with sufficient linearity, a stable 50 W input impedance and low-power consumption, which is needed in portable systems. Satisfying all the design goals with the broad bandwidth required by some of the wireless applications like the mobile TV is particularly difficult compared to conventional wireless receivers. To demonstrate this, the main CMOS LNA topologies including the resistor-terminated commonsource amplifier (R-CS), shunt feedback (SFB) amplifier, common-gate (CG) amplifier and, inductively degenerated (L-degenerate) amplifier are analyzed and discussed in the context of the mobile TV application. We show that adding a 50 W input matching requirement sets the power consumption level in some of these amplifiers (i.e., CG & SFB amplifiers) and therefore limits the dynamic range that they can achieve. Moreover, trying to decouple the input matching from the power consumption as in the R-CS amplifier merely slides the dynamic range by raising the noise figure and IIP3 together. The L-degenerate topology can offer the right properties by its capabilities of achieving the NFmin of a MOSFET as prescribed by the classical optimization (Section 2.1.1.2) but unfortunately just in a narrow band around a single frequency. A complete dynamic range study for these amplifiers is presented in the following subsections. This study also shows that adding more design constraints other than the dynamic range (i.e., input matching) complicates the compromise and tightens the trade-offs even more. In the described analysis, the induced gate noise of MOSFETs (Section 2.1.1.1) is ignored because of the relatively low operating frequency of the LNA designed for mobile TV application.

2.2.1 R-CS Amplifier The first topology uses a resistive termination at the input of a common-source amplifier to provide a 50 W input matching [63, 64]. To quantify the effect of adding this resistor, consider a transistor to which a resistor aRs is added, as shown in Fig. 2.8.

2.2 Traditional CMOS LNA Topologies

27

Fig. 2.8 A resistive terminated commonsource amplifier

RFout

Rs

RFin

αRs Zin

The NF of this amplifier can be written as a function of the source resistance Rs and the transconductance gm to be: 1+ a 1+ a  g + .  a  gm Rs a 2

NFR −CS =

(2.10)

Indeed the NF can be examined in two cases, with perfect matching (a = 1) and without (a = •). These are as follows

NFR −CS = 1 +

g ,a = ∞ gm Rs

(2.11)

NFR −CS = 2 +

4g , a = 1 . gm Rs

(2.12)

As can be seen from (2.11) and (2.12), the resistive termination degrades the achieved NF. Two effects are responsible for this degradation. First, the added resistor contributes its own thermal noise to the output, which is equal to the contribution of Rs. This results in a factor of two difference in the first terms of (2.11) and (2.12). Second, the input is attenuated leading to the factor of four difference in the second term of (2.11) and (2.12). The large noise penalty resulting from these effects pushes the R-CS amplifier noise figure further from NFmin of the transistor. Therefore, although this topology offers the possibilities of having very lowpower design (gm is decoupled from Zin) across broad bandwidth, the achieved noise figure (NFR−CS > 3dB) makes it unattractive for mobile TV application. Also, adding this resistor would not benefit the DR at all since the NF and IIP3 both shift in the same direction.

28


Fig. 2.9 A common-gate amplifier

Rs RFout

RFin Zin

2.2.2 CG Amplifier Another topology that can provide a 50 W input matching is the common-gate amplifier (shown in Fig. 2.9) [65]. The input impedance of this LNA is controlled by the transistor transconductance (Zin ~ 1/gm). Hence, gm of this amplifier has to be at least 20 mA/V. In other words, the matching determines the power consumption of this amplifier. Moreover, the matching also has an effect on the achieved NF. The noise figure of this topology at matching can be given as follows:

NFCG = 1 + g .

(2.13)

The achieved NF of this amplifier is usually larger than 3 dB for short channel MOSFET devices (NFCG > 3 dB). The only thing preferable about this amplifier is that the achieved matching has a broadband nature. However, one can note that it suffers from the low-voltage gain associated with this wideband feature. For a given capacitive load (i.e., from a mixer), the load resistance must be lowered to push out the output pole (~200 W), this leads to an LNA with a voltage gain of 12 dB. Moreover, the load resistor noise raises the NF to about 5 dB. In terms of linearity, this amplifier offers higher values of IIP3 compared to the R-CS amplifier because it is current driven. So, as a conclusion, the features that the CG amplifier can offer don’t fit with the target application figure of merits.

2.2.3 SFB Amplifier Another example of an amplifier that can provide broadband matching to a 50 W source resistor Rs is the resistive shunt feedback amplifier that is shown in Fig. 2.10 [66]. Since the added resistor RF is in the feedback path, its value is larger than 50 W due to the advantage of Miller effect and therefore its noise contribution is less than that of Rs. Hence, in terms of noise figure, this topology provides better NF


29

Fig. 2.10 A resistive shunt feedback amplifier RL RF

RFout

Rs Av RFin Zin

than that of the R-CS. Moreover, this amplifier doesn’t suffer from the fundamental trade-off between its NF and input matching like the CG amplifier does. To better visualize this, let us examine the amplifier input impedance ZinSFB, the gain AvSFB, and noise figure NFSFB. The input impedance can be derived to be ZinSFB =

RF + RL 1 + gm RL

(2.14)

where RF is the feedback resistor, gm is the MOSFET transconductance, and RL is the load resistor. The MOSFET channel length modulation and the parasitic capacitances (Cgs and Cgd) are ignored in this expression. The amplifier voltage gain without taking the matching into account is given by AvSFB =

1 / RF − gm 1 / RL + 1 / RF

(2.15)

and the noise figure under the constraint of input match can be derived to be NFSFB ≈ 1 +

1 (1 − gm RF )2

 RF 2    1 1  1 ( gm RF − 1)2   (2.16) + +   ggm +  + Rs  ggm +    . RF RL RL RF   Rs  

In this derivation, in addition to neglecting the transistor channel length modulation, it has been assumed that RL ≫ RF so that the amplifier gain is controlled mainly by the feedback resistor RF. Now looking at (2.14), (2.15), and (2.16), one can note that since the amplifier is not constrained by the input matching, its contribution to the noise figure NFSFB can be arbitrarily small by increasing gm of the transistors at the expense of the power consumption. However, although the matching/noise figure trade-off is broken in this topology, they are still directly coupled as shown in (2.14) and (2.16); both

30


depend on RL and RF. Because of this coupling, it is generally difficult to achieve an arbitrarily low noise figure for an input impedance of 50 W with reasonable power consumption [58, 67]. However, we still haven’t quantified exactly what is the minimum noise figure that this amplifier can achieve. Can this amplifier achieve a NF < 3 dB required by the mobile TV receiver? To give an answer to this question some assumptions have been made to simplify the noise figure expression in (2.16). The drain noise contribution of the main transistor is neglected. To examine the validity of this simplifying assumption, let us find the noise contribution of the main transistor in the SFB amplifier. The output noise current of the transistor can be given by

2 inout =

in2 4 kTg Df ≈ (1 + gm Rs )2 gm Rs 2

(2.17)

2 where inout is the mean-squared noise current output from the transistor that flows through resistors Rs and RF, and in2 is the mean squared channel thermal noise of the transistor. At reasonably high values of gm the transistor doesn’t contribute to the total output noise. Given that value of gm, the load resistor RL noise current can be also neglected. Therefore, the amplifier noise figure is only limited by the feedback resistor RF. Now, looking at (2.16), one can assume that at reasonably high value of RF, the amount of the noise current that leaks from this resistor to the input can be neglected as well and hence the amount that leaks to the output determines the minimum noise figure that can be achieved by this topology. The minimum noise figure NFminSFB can be derived to be

NFmin SFB = 1 +

1 1 + Av

(2.18)

which can be below 2 (i.e., 3 dB), providing adequate gain Av = gmRL is available. Despite its good noise performance, this amplifier suffers from an insufficient amount of gain and thus requires multiple cascaded stages to be used within the feedback loop. This makes its operation prone to instability [68, 69]. As for nonlinearity factor, one can expect that this amplifier would have better IIP3 values than that of the R-CS and CG amplifiers due to the negative FB. However, the loop gain expression implies different results. The loop gain of the SFB amplifier under the matching constraint can be derived assuming ZL ≫ ZF to be

Av . 2 + Av

(2.19)

As can be seen in (2.19), the open loop gain at ZinSFB = 50 W condition is below 1, therefore the closed loop linearity is not much better than that of the transistor itself. In fact it would get worse at higher frequencies due to decreasing the loop gain. In conclusion, the power consumption as well as the gain associated with the SFB amplifier makes it an unlikely candidate for use in mobile TV applications.


31

2.2.4 L-Degenerate Amplifier Inductor degeneration in common-source amplifiers was introduced by Van Der Ziel and Strutt to generate the real part needed to match the input impedance [70]. By decoupling the input impedance from the noise, these topologies allow the optimization of the dynamic range with reasonable power consumption. To better visualize this, consider the circuit shown in Fig. 2.11. The degeneration inductor Ls results in an equivalent input resistance given by: Ri = w T Ls (2.20) where wT is the short circuit unity current gain frequency of the transistor. The resulting equivalent circuit of the degenerated transistor consists of Cgs, Ri, and Ls as also shown in the same figure. The input impedance is purely resistive at the resonance frequency (wo) of Ls and Cgs. In practice, an inductor Lg is added in series to align the series resonance frequency with the desired frequency of operation. The unique property of this amplifier is that it can achieve the minimum noise figure NFmin of a MOSFET proposed by the classical optimization theory (see Section 2.1.1.2). In fact, a simulated NF of about 0.5 dB has been achieved at 1.8 GHz while gmRs = 1, Cgs = 0.5 pF, (Lg + Ls =15 nH), and Lg and Ls are lossless. This is an incredible result compared with any other amplifier noise figure. Assuming ideal inductors, this amplifier produces a noise figure NFL−deg equal to 2

w  NFL − deg = 1 + ggm Rs  o  .  wT 

(2.21)

It is noted that the noise figure improves quadratically with the transistor unity gain frequency (wT) for a given resonance frequency (wo). To obtain the best noise figure, the transistor should be biased at the maximum of wT. One can note also that due to the noiseless inductive degeneration Ls, (2.20) and (2.21) are decoupled.

Iout Iin

Rs

Lg

Ls

Cgs

Zeq

RFin

Ri = ω TLs Zin = Rs (at resonanace )

Zeq

Ls

Degenerated transistor equivalent circuit

Fig. 2.11 Equivalent circuit for the inductively degenerated transistor

32


Therefore, the input-matching noise-figure trade-off limitation that exists in all other amplifiers discussed so far (R-CS, CG, SFB amplifiers) is broken here. However, in some cases, the minimum degeneration inductance is limited because of the packaging considerations. For a wirebond package, the minimum degeneration inductor even in the case of multiple parallel downbonds cannot be lower than 0.5 nH because of the mutual inductance. As can be seen in (2.20), this would limit the maximum allowable wT needed to achieve a 50 W input resistance and would thus affect the noise figure. A passive LC network can be used to relax this coupling. The network shown in Fig. 2.12 can be used to transfer down a real resistance in a narrow band of frequencies. A transformation ratio (a) is used in the matching network to lower the input resistance to 50 W. This ratio is given by a=

Rs ' . Rs

(2.22)

As a result, for a given Ls degeneration, the resulting NF can be given by 2

NFL − deg_ a

w 2  w  = 1 + ggm Rs  o  a 2 = 1 + ggm Rs '  o  Ls. w  w  T

(2.23)

T

Although this topology can achieve superior noise performance, adding the reactive component Ls does not lead to any improvement in the amplifier dynamic range. This can be seen with the aid of the IIP3 expression

IIP3L − deg ≈

IIP3MOSFET  vgs   v  RFin

2

2

2 w  ≈ IIP3MOSFET (gm Rs )  o   wT 

(2.24)

where vgs is the small-signal gate-source voltage and vRFin is the RF input voltage. Equations 2.21 and 2.24 indicate that this topology suffers severely from the common trade-off between the NF and IIP3 limiting any improvement in the achieved

Rs

Rs

Rs C1 RFin

Fig. 2.12 Narrowband impedance transformation using passive elements

L1

Ls

Rs >Rs

2.3 Recent Trends in Wideband CMOS LNAs

33

dynamic range. As can be seen from (2.23), decreasing the device transconductance gm improves the NF but also degrades IIP3. Moreover, scaling the device leads to the improvement in the unity gain frequency of the transistor, which results in improvement in NF, but again degrades IIP3. This can be intuitively described by considering the passive gain of the input matching Lg, Ls, and Cgs network.

1

Passive _ GainL − deg = 2 Rs

Cgs

.

(2.25)

( Lg + Ls )

Increasing the passive gain by decreasing Cgs and therefore decreasing gm improves the NF but unfortunately degrades IIP3 because of the larger signal swing at the transistor input. The NF and IIP3 values become strongly dependent on the passive elements rather than on the transistor itself [71–75]. However, at some point the amplifier performance is going to be limited by the losses of the passive network itself, mainly the Lg losses. Detailed optimization procedures for the L-degenerate amplifier taking into account the losses of the passive network can be found in [76]. Another trade-off arises while trying to achieve the broadband matching from this topology. The NF expression in (2.21) can be rewritten as a function of the quality factor Q of the passive matching network as

NFL − deg = 1 +

g . gm RsQ 2

(2.26)

Basically, the L-degenerate amplifier provides real impedance only in a narrow bandwidth (wo/Q) around the resonance frequency (wo). To achieve a wideband impedance matching, the Q of the matching circuit should be significantly lowered. This will largely degrade the noise figure, which defeats the purpose. As a result, this type of amplifier cannot be used in the mobile TV receiver. However, several attempts have been made to extend the L-degenerate amplifier bandwidth as will be presented and discussed in the next section.

2.3 Recent Trends in Wideband CMOS LNAs This section discusses the progress that has been made to push the performance of wideband LNAs and examines the possibility of using some of these new techniques towards the design of a mobile TV LNA. As described in the introduction of Section 2.2, in order to improve an LNA’s performance, one should either try to minimize the magnitude of the MOSFET noise or distortion generators or try to cancel their contribution at the amplifier output. These two main factors govern the discussion in this section. The section begins by presenting the current reuse techniques developed to boost the device transconductance (gm) in order to minimize the MOSFET noise. Then, the section continues by demonstrating different methodologies proposed to extend

34


the bandwidth of the L-degenerate amplifier. Although these techniques help in improving the noise performance of an LNA, they do not offer a solution to improve the IIP3 as well. Research has thus been redirected to other approaches in order to improve both the noise and linearity and therefore improve the dynamic range. The concept of cancelling the noise of the matching transistor in the CG and SFB amplifiers has been reported in 2002 at ISSCC [92]. Since then, several published results showed the feasibility of designing a CG and SFB amplifier in CMOS technology with NF well below 3 dB, regardless of the input matching constraint. Some of these techniques also allow cancelling the distortion and hence improve the amplifier dynamic range.

2.3.1 Current Reuse Amplifiers The MOSFET device suffers intrinsically from the lower driving efficiency. The value of (gm/Id) depends on how the device is biased, which is usually constrained by the NF and IIP3 optimization. A circuit technique that can be adopted to improve this ratio, and therefore lower the power consumption for a fixed DR, is to reuse the current. By simply stacking two NMOS devices (or one NMOS and one PMOS device) as amplifying devices, one can facilitate the current reuse [77]. This enhances the overall transconductance (Gm) from (gm1) to (gm1 + gm2), where gm1 and gm2 are the transconductances of the first and second devices, respectively. Doing this therefore allows one to halve the current for the same input impedance and DR. This technique is implemented in [78] as three stacked NMOS devices that form three gain blocks (shown in Fig. 2.13a). The effective Gm is almost three times higher for the same current in this topology. Large on-chip decoupling capacitors provide stable intermediate nodes between the stacked gain blocks. The output nodes of each of the gain blocks are combined with capacitors C2 and C3 to form one effective signal node at RFout. Lowering the power in this amplifier is achieved at the expense of the bias circuit complications and the use of expensive on-chip capacitors. The LNA design in [79] avoids using decoupling capacitors by using different bias techniques. As shown in Fig. 2.13b, a resistor R1 is used to bias the stacked NMOS device. The author went even further by implementing an active common-mode feedback technique to permit the amplifier to operate reliably on a 1.5 V supply. Another example of implementing the current reuse in LNAs is shown in Fig. 2.14a [80]. In this amplifier the stacked device is a PMOS transistor. This eliminates on-chip coupling capacitors and greatly simplifies the biasing circuit. The interstage transformer T2 acts as a high impedance for ac signals and low impedance for DC signals, making the reuse of bias current feasible. The only disadvantage is the smaller ft of the PMOS device. The PMOS is also used as a stacked device in (Fig. 2.14b) [81] in a simple design where no transformers or capacitors are used. The PMOS device is stacked on top on the NMOS device directly at the expense of generating a stability problem at the intermediate point. An active feedback amplifier is used to set the DC output voltage. This current reuse technique has been used also in [82] for designing a broadband CG amplifier.


35

a

b Vbias

R1

R2 Current reuse

R3

+

R1

-

R4

RFout Cc3

Cc2

Vbias

R1

M5

RFout C2

M6

M2

M4

M1

M3

C3

Vbias

R1

Rs

Ls1

Cc1

RFin

Ls1 I

RFin

Rs

Fig. 2.13 Amplifiers implementing current reuse using NMOS devices: (a) is a wideband amplifier based on [78] and (b) is a narrowband amplifier based on [79]

a

b +

RFout

−

M5

M6

current reuse devices Vbias

T2

RFout M2

M4 Rx

Rs M1

Cx

M3

RFin I

Vref

T1

RFin

Rs

Fig. 2.14 Amplifiers implementing the current reuse using PMOS devices: (a) is a narrowband amplifier based on [80] and (b) is a narrowband amplifier based on [81]

36


2.3.2 L-Degenerate Wideband Amplifiers The L-degenerate amplifier is usually the optimum amplifier in terms of the achieved NF, as it can come closer to the MOSFET NFmin as was shown in Section 2.2.4. A new type of amplifier is introduced to extend the bandwidth of the conventional narrowband L-degenerate amplifier. As shown in Fig. 2.15, an LC ladder filter has been used to match the input impedance of the L-degenerate amplifier across a wide bandwidth. It can be shown that in such a circuit the transistor Cgs/MCgd determines the maximum ratio of the upper frequency (fU) to the lower frequency (fL) across which the impedance is matched, where MCgd is the Miller multiplied feedback gate-drain capacitance and Cgs is the gate-source capacitance. The fU/fL ratio is limited to about 2 in CMOS technology because of the relatively large feedback capacitance in MOSFETs [83]. This limits the achievable bandwidth. An external capacitance is added (Cext) in parallel with the gate capacitance to overcome this limitation, but this directly compromises gain and noise. Therefore, this topology might not be feasible to cover the VHF/UHF band required for mobile TV applications. The LNA designers kept trying to extend the L-degenerate amplifier because of its superior performance. The design in [84] used the gate-drain capacitance to create another feedback loop around the main transistor in addition to the source inductor Ls feedback loop. This additional feedback loop resonates at a different frequency from the series inductor Ls loop. The overall structure of this amplifier and the input equivalent circuit taking Miller effect into account are shown in Fig. 2.16. If the cascode transistor M2 is designed properly, a wideband input match with minimum noise figure can be achieved.

Ls

RL

M2

Rs

L1

CL

CL RFout

Lg M1

RFin

L2

C2

Cext

Ls

Fig. 2.15 Broadband L-degenerate amplifier with input matching using LC ladder


Ls

37

RL

M2

CL RFout

Cgd

Rs

Lg

Lg

R2

Ls

Cgs

M1

C2 RFin

Ls

L1

Ri = ω TLs C1

R1

Degenerated transistor equivalent circuit with Miller effect

Fig. 2.16 Broadband L-degenerate amplifier with input matching using Miller effect based on [84]. The equivalent circuit for the input matching is also shown

Drain-gate capacitance has also been used to provide the wideband matching in [85, 86]. However, this wideband matching technique strongly depends on process and temperature variation making it an unattractive solution. The same concept has been used to design the wideband amplifier shown in Fig. 2.17 [87]. This topology is implemented by inserting a feedback capacitor CL between the two transistors M1 and M2 of a narrowband inductively degenerated cascode LNA. The design is robust against temperature and process variations. However, it requires two extra pins to provide the DC path to the cascode transistor, which increases the packaging cost.

2.3.3 Capacitive Cross-Coupled CG Amplifiers The CG amplifier discussed in Section 2.2.2 requires a gm = 1/Rs to provide a wideband input match. Given this condition, the CG amplifier has a NF that is larger than 1 + g (>3 dB in nanometer CMOS). This trade-off is somewhat relaxed for the balanced CG amplifier, which uses capacitive input cross-coupling as shown in Fig. 2.18. In 1999, Cho proposed the cross-coupling idea as a technique that can be used for gain enhancement in CG amplifiers [88]. Subsequently, the authors in [89] reported the benefit of using this technique on the NF of the CG amplifiers for the first time. The noise figure of the capacitive cross-coupled CG amplifier NFCG−CC under the input matching constraint can be derived to be equal to

38


Fig. 2.17 Broadband L-degenerate amplifier based on [87]

Ls

RL

Cascode device M2

RFout

CL

RF choke

Rs

CL

Lg M1

RFin

Ls

Fig. 2.18 Capacitive cross-coupled common-gate amplifier

RFout M1

M2

Cross-coupling capacitors

C1

C2

RFin

NFCG −CC = 1 +

g . 2

Rs

(2.27)

The cross-coupling technique does not add much cost or complexity. It doubles the effective Gm, thus, the power consumption can be reduced. Also, in terms of IIP3, the CG amplifier utilizing a capacitive cross-coupling is expected to achieve a higher IIP3 than that of the conventional differential CG amplifier. The only disadvantage is that the capacitors limit the amplifier bandwidth. The same idea has been used in [90] to design a shunt feedback common-gate (SFBCG) amplifier. As shown in Fig. 2.19, this amplifier is no more than a GC with cross-coupled


39

current reuse

C1

C2

M2 Rf1

M4 Rf2

RFout M1

M3

C1

RFin

C2

Rs

Fig. 2.19 Broadband SFBCG amplifier based on [90]

capacitors incorporating the current reuse technique. The current reuse technique further pushes the effective Gm to 4gm where gm is the transconductance of a single transistor M1. In this case, the SFBCG amplifier produces a NFSFBCG equal to

NFSFBCG = 1 +

g . 4

(2.28)

Although these efforts have helped in pushing the noise performance of CG amplifiers with resulting dynamic range improvements in wideband LNAs, these amplifiers still suffer from the input match-noise figure trade-off. New techniques are thus still needed to break this trade-off and hence increase the degree of freedom to allow the dynamic range to be pushed even further while keeping the power consumption to a minimum. The authors in [91] used the cross-coupling idea to boost the gm, but used a transformer instead of capacitors. They reported a 2.5 dB NF amplifier. However, the impedance matching constraint remained unchanged.

2.3.4 Noise and Distortion Cancelling Amplifiers In 2002 at ISSCC, Bruccoleri reported a SFB amplifier with a 2.4 dB NF [92]. He was able to break the SFB amplifier input matching NF trade-off described in Section 2.2.3 by proposing a thermal noise-cancelling technique. A simplified schematic diagram of his amplifier is shown in Fig. 2.20. His idea was based on

40


The noise current output from M1 leading to noise voltages at X and Y that are fully correlated

"A" RF

M3 Y

Rs

RFout

M1

M2

X

RFin

noise curent

Amplifier plus adder to cancel the noise of M1

Fig. 2.20 A resistive shunt feedback amplifier using noise cancelling

exploiting the difference in sign for the noise and the signal gain at the output (see point Y in the same figure) making it possible to cancel the output noise contribution of the main transistor M1 while adding the signal. This was done by creating a new output, where the voltage at node Y is added to a scaled negative replica of the voltage at X, using a second stage amplifier “A”. It can be shown that the output noise cancellation is achieved if

gm 2 RF = 1+ gm 3 Rs

(2.29)

where gm2 and gm3 are the transconductance of M2 and M3, respectively. With this condition, the overall gain of the SFB amplifier with noise cancellation can be found to be

GainSFB _ noise _ cancelled = −2

RF . Rs

(2.30)

At this gain, the noise of M1 is totally cancelled. However, this is not the case with the feedback resistor RF. This can be seen by splitting its noise current in two correlated sources to ground, at the output node Y and the input node X. The former is cancelled but the latter is not. Therefore, the minimum noise figure of the conventional SFB amplifier expressed in (2.18) can be reformulated to include the noise cancellation as shown in (2.31)

NFmin SFB _ noise _ cancelled = 1 +

Rs . RF

(2.31)

This expression assumes that gm2 is high enough that it would not affect the total NFminSFB_noise_cancelled. Therefore, to lower the NF even further, the power consumption


41

R1

R2 RFout

noise current

CG noise

M1

CG noise

Rs M2

RFin

Fig. 2.21 A common-gate amplifier using noise cancelling

of the second stage should be high and RF should be large. In terms of the amplifier DR, the added amplifier “A” would degrade the overall linearity and therefore limit the IIP3 value. If these limitations could be avoided, a better version of a SFB amplifier can be realized. The concept of noise cancelling has been implemented in a CG amplifier as shown in Fig. 2.21 [83]. An interesting property of this circuit is that the fraction of M1 noise current that flows into R1 and Rs induces an in-phase amplified noise current in R2 by driving the gate of M2. Therefore, if the resulting noise voltages at the two output terminals are equal, then M1’s noise is common-mode and can be cancelled by differential sensing. It can be proven that the noise cancellation occurs when

gm1 R1 = gm 2 R2.

(2.32)

At this condition, assuming balanced loads, the new noise figure of the CG amplifier exploiting noise cancelling (NFCG_noise_cancelled) is derived to be

NFCG _ noise _ cancelled = 1 + g.

(2.33)

Comparing with the NF of the conventional CG amplifier expressed in (2.13), the noise-cancellation technique transferred the problem of the high noise level associated with the CG transconductance needed for matching to the commonsource amplifier that is used for noise cancelling. In other words, for this noisecancelling technique to be efficient, unbalanced loads are required to achieve NF < 3 dB with low-power consumption. In the presence of unbalanced loads the NFCG_noise_cancelled is

42


NFCG _ noise _ cancelled = 1 +

 gm 2 R 2 2 4g    Rs  (gm1 R1 + gm 2 R 2 )2 

(2.34)

where gm1 and gm2 are the transconductances of the common-gate (M1) and common-source (M2) amplifiers, respectively. As can been seen in (2.25), the load R2 can be traded with power consumption of the common-source amplifier (gm2). Another advantage of this amplifier is that the gain can be increased by up to 6 dB when the output swings are balanced. Also, the load resistor noise is less significant. The only limitation of this amplifier is that the common-source amplifier M2 used to cancel the noise of M1 limits the overall noise figure of the new CG amplifier. Not only that, but its transconductance value is somehow coupled with the input matching requirement in the case where balanced loads are present. If these limitations can be avoided, a very high dynamic range common-gate wideband LNA can be realized. Other circuits recently proposed in the literature exploiting noise-cancellation mechanisms are shown in Fig. 2.22 [93, 94]. A CG amplifier in a feedback path is used to achieve 50 W wideband input matching and partial noise cancellation at the same time. The noise current of the common-source transistor M1 produces a noise voltage at the output. A scaled version of this noise is fed back to its gate again, where it is amplified and inverted. As a result, at the output (summing node), some of this correlated noise is cancelled and the total output noise is reduced. Some limitations also exist in these amplifiers. The major noise contribution now originates from transistor M3. Because M3 is outside the feedback loop, its noise is not subjected to the cancellation mechanism. Specifically, the noise contribution of M3 is (1 + gmRo)2 times larger than that of the CG transistor M2, assuming the same W/L ratio, where Ro is the equivalent resistance seen by the source of M2. a

b Currect reuse

M oad

R oad

Rload

RFout

RFout

M2

M2 Noise cancellation by active feedback

Ro

Ro

Mcascode

R1

Rs

Rbias

Mcascode

Rs M1

RFin

M1

RFin M3

C M3 Currect reuse

Fig. 2.22 A common-gate amplifier exploiting noise cancelling by active feedback. Amplifier (a) is reported in [93] while amplifier (b) is reported in [94]

2.4 Techniques to Improve the Wideband LNA Dynamic Range

43

Another disadvantage is that these circuits degrade substantially the IIP3 value because of the large signal usually applied at the gate of the CG transistor M2. Another effect that also contributes to the IIP3 degradation is the feedback loop. The feedback can combine the second-order distortion with the fundamentals of the output signal of the circuit, producing third-order distortion at the circuit input, which worsens the IIP3 value. The same mechanism leading to cancellation of the output noise can also be exploited to cancel the distortion. However, since the IIP3 will always be limited by the other added amplifier, specific distortion cancellation circuits have been investigated. In [95], the LNA design uses a circuit that can sense the distortion as an inherently generated signal, amplified through a parallel path, and cancel it at the output. The large overhead of the auxiliary amplifier makes this technique unattractive. Other designers went even further by trying to cancel the third-order nonlinearity of a MOSFET by adding a parallel transistor that is biased in the triode region as in [96] or in the subthreshold region as in [97]. However, this concept did not catch on due to this approach’s sensitivity to process and temperature variations.

2.4 Techniques to Improve the Wideband LNA Dynamic Range In this section, the LNA topology that can best meet the stringent dynamic range (DR) requirements of the mobile TV application has been introduced. Two main factors are considered here: the minimum noise figure that a topology can achieve, and its DR.

2.4.1 Wideband CMOS LNA State-of-the-Art As has been shown earlier, the inductor-based wideband LNAs have superior noise performance as their NF can reach the NFmin of a MOSFET. Moreover, with a good design, they can achieve a very good dynamic range that is limited by the amount of current they consume. However, these topologies have received less interest with respect to their inductorless counterparts. In the modern nanometer CMOS technology, the use of area consuming on-chip inductors must be avoided as the cost per area for such processes is extremely high. Also, high quality factor (Q) inductors do not easily lend themselves to integration in a digital CMOS process, due to their need for special process enhancements such as high substrate resistivity for implementation. The CMOS process with RF enhancements usually lags one to two generations behind the digital one. Moreover, these types of amplifiers do not fit with the trend toward flexible multi-mode and multi-standard radios as they have limited bandwidths. As shown in Table 2.1, inductorless type amplifiers have been

CGf CGh SFB Noise Cancel CG

Inductorless CMOS Wideband LNAs 0.6 µm CMOS Choe 1999 [88] Zhuog 2000 [89] 0.5 µm CMOS Van Zeijli 2002 [99] 0.18 µm CMOS

Bruccolerik 2002 [92] Rogin 2003 [100] 2.4 4

0 +10

N/A +5 N/A

−9 −3

IIP3 (dBm)

13 10

15 12 N/A

15 18

Voltage gain (dB)

35 7

N/A 20 7j

7.5c 50

Power (mW)

Chehrazi 2005 [83] 0.13 µm CMOS Noise Cancel 3 +1 19 12.5 Zhan 2006 [101] 90 nm CMOS SFBl 2 −14 25 42 Bagheri 2006 [40] 90 nm CMOS Noise Cancel 3 +1 19 12.5 Ramzan 2007 [94] 0.13 µm CMOS Noise Cancel 2.7m −4n 17 25 90 nm CMOS Noise Cancel 2.5dB −15 17 10 Borremanso2007 [93] Grey: Narrow band applications. a The amplifier supports an ultra-wideband receiver (3–10 GHz). b The drain-gate capacitance helps in achieving a very low NF. c This amplifier is optimized for the power consumption. d The amplifier supports 0.7–1.4 GHz band. e The amplifier supports a 900 MHz spread-spectrum cordless phone receiver. f Capacitive cross-coupling technique has been used to boost the CG gm. g The amplifier supports a 900 MHz narrowband receiver. h Capacitive cross-coupling techniques have been used to push the NF of the CG amplifier. i The amplifier supports Bluetooth radio. j This power has been achieved for a source resistance of 150 W. k The LNA supports 2–1,600 MHz band. l A source follower feedback amplifier has been proposed to tune the input matching, this topology benefits from high ft of the 90 nm CMOS process. m Measured differentially from 1 to 7 GHz. n High IP3 value achieved due to the differential operation and the feedback technique. o The LNA covers from DC to 6 GHz.

0.25 µm CMOS 0.13 µm CMOS

2.3b 0.5

L-degenerate L-degenerate

Inductor-based CMOS Wideband LNAs 0.18 µm CMOS Leea 2006 [84] Belostotskid 2007 [98] 0.18 µm CMOS 2 3 3.5

NF (dB)

Table 2.1 Current state-of-the-art of wideband CMOS LNAs Research paper Technology Topology

44 2 Wideband CMOS LNA Design Techniques


45

implemented several times in narrowband receivers [88–100] because of the above mentioned reasons. For the mobile TV LNA, low cost, small area, inductorless topologies should only be considered. High performance wideband inductorless topologies such as noise-cancelling amplifiers [40, 63] or feedback type designs [99, 101] suffer from high power, or inadequate NF as shown in Table 2.1. As shown in Section 2.3.4, the noise-cancelling amplifiers incorporate another amplifier to cancel the noise of the main transistor of an SFB or CG amplifier. This added amplifier unfortunately dominates the noise performance and makes achieving low NF ( 1. Let us consider the circuit diagram shown in Fig. 2.27 in order to discuss the feedback loop elements (CG transistor M1 and the feedback resistor RF). To find the noise contribution of M1, the feedback system is modeled as shown in the block diagram of Fig. 2.28. Using this model, the output noise current that leaks from the M1 to the load resistor R2 (ino+CG) can be found as follows2

ino + CG =

(gm 2 Rs ) (1 + gm1 RT ) g  g m1  1 + m2  Rs gm 3  1 + gm1 RT 

inCG .

(2.39)

Similarly, the output noise current that leaks to the load resistor R1 in the common-gate branch (ino−CG) from the M1 is

ino −CG =

1 (1 + gm1 RT ) g  g m1  1 + m2  Rs gm 3  1 + gm1 RT 

inCG .

(2.40)

As can be seen from (2.39) and (2.40), the output noise current of the M1 branch can be totally cancelled with differential sensing (ino+CG and ino−CG are inphase) given that gm2 = 1/Rs. However, this would limit the power consumption of 2

The channel noise current of M1 can be modeled at low frequencies as an input-referred voltage vinCG = inCG/gm1.


51

M1 noise contribution, normalized

100%

60%

R2=80 Ω

R2=40 Ω R2=120 Ω 20%

0

0.02

0.06

0.1

gm2 (S) Fig. 2.29 Dependence of the common-gate noise-cancellation mechanism on gm2 and R2. The active feedback loop is broken to decouple the CS branch from the CG branch. Otherwise, the amplifier input matching cannot be maintained. The R1 is set to 250 W

the CS transistor. Using unbalanced loads can resolve this by cancelling the differential output noise voltage at the output such that (ino+CG R2 = ino−CG R1). Therefore, the noise of M1 can be completely cancelled given that R1 = gm 2 × R2 × Rs.

(2.41)

This condition is satisfied at infinite possibilities of gm2 and R2. The dependence of the cancellation mechanism on these parameters is shown in Fig. 2.29. The choice of gm2 depends on the power-noise tradeoff. The same noise-cancelling mechanism applied on M1 is also applied on the feedback resistor RF. Using Fig. 2.27, the output noise current that leaks to the load resistor R1 in the common-gate branch (io−RF) from the resistor RF is

ino − RF =

(gm1 RF ) (1 + gm1 RT ) g  g m1  1 + m2  Rs gm 3  1 + gm1 RT 

inRF .

(2.42)

Similarly, the output noise current that leaks from the feedback resistor RF to the load resistor R2 (ino+RF) can be found as follows

52


ino + RF =

(gm1 gm 2 RsRF ) (1 + gm1 RT )i g  g m1  1 + m2  Rs gm 3  1 + gm1 RT 

nRF

.

(2.43)

As can been seen from (2.42) and (2.43), the output noise current of RF can be totally cancelled with differential sensing giving the same noise-cancelling condition of the CG transistor M1 (Eq. 2.41). Given the derivations of the noise contribution of M1, M2, and the feedback resistor RF, the noise figure of the new LNA topology (NFCG_noise_cancelled_NEW) can be derived (assuming that the noise of the CG transistor M1 as well as the feedback resistor RF is cancelled) to be     g 1  R2    gm 2    . = 1+ 2  (2.44)  R1   ( g Rs )  Rs   g m1  1 + m2  gm 3  1 + gm1 ( Rs + RF )      2

NFCG _ noise _ cancelled _ NEW

Comparing this expression with the one reported for Chehrazi’s noise-cancelling amplifier [83] shows that the NF of the new amplifier has improved by the square of the loop gain. The simulated NF value mentioned in Section 2.4.2 is very close to the value predicted from (2.44) and is similar to values of counterpart L-degenerate amplifiers. To determine the minimum achievable NF value of this topology, remaining performance parameters for the amplifier have to be defined. These parameters, namely input matching, gain, and linearity are discussed in the following sections. 2.4.2.2 Input Matching and Gain Analysis A common-gate amplifier with a source resistance RF (shown in Fig. 2.30a) has an input resistance approximately equal to

RinCG = RF + 1 / gm1 .

(2.45)

This expression has to be modified in the presence of feedback around the CG amplifier as shown in Fig. 2.30b. In this figure, the transistor M1 acts as a commondrain amplifier for the feedback signal, making M1 look like a shunt-shunt feedback type amplifier. Because of this type of feedback, the input impedance of the CG amplifier (RinCG) is decreased by the amount of the loop gain (“A” in Fig. 2.30). The input resistance of the CG amplifier with an active feedback loop (RinCG_FB) is expressed by

RinCG _ FB =

RF + 1 / gm1 . 1 + gm 2 / gm 3

(2.46)


a

53

b

R1

ro1

R1

M1

ro1

CS amplifier

M1

RinCG

A

ro>>R1

RF

RF

RinCG_FB

A=gm2/gm3

Fig. 2.30 Input resistance calculation of the common-gate amplifier. Amplifier (a) without feedback (b) with feedback. The output intrinsic resistance ro1 of M1 is assumed to be large enough so that the effect of the load resistance R1 on the total input resistance is negligible

Two important observations can be made by comparing (2.45) and (2.46). First, adding the loop gain around the CG amplifier allows the matching to be adjusted through (gm2/gm3). This makes it possible to achieve the input match requirements at lower power consumption. Second, feedback helps in saving some voltage headroom that can then be used to increase the amplifier gain (by decreasing the value of RF required to achieve the matching). The question that remains is what is the ultimate achievable NF for this topology? As discussed in Section 2.4.2.1, the NF can be improved by increasing the feedback loop gain (LG). However, as can be seen in (2.46), this demands an increase in the resistance value of the feedback resistor RF to maintain the matching. Since the upper limit of this value is bound by the available voltage headroom, the minimum NF that can be achieved for this amplifier is now limited by the supply voltage. Therefore, decreasing the NF value of this amplifier requires an increase in the supply voltage.3 The gain in this topology also differs from that of a conventional CG amplifier. This topology includes a single-to-differential conversion which results in an increase in the gain. The gain can be increased up to 6 dB when the output swings are balanced. The differential gain of this topology under the input matching constraint can be expressed by

Differential _ Gain =

gm 2 R2 Rs + R1 . 2 Rs

(2.47)

3 In our previous discussion, the output resistance (ro1) was neglected. However, this value can be very small in nanometer CMOS and hence its effect cannot be ignored. In fact, it tightens the design trade-offs.

54


The gain can be further increased by increasing the load resistors R2 and gm2. However, this degrades the NF since it affects the cancellation mechanism and also increases the power consumption. Therefore, under the constraint of the noise cancellation, the gain can best be increased by increasing the supply voltage. 2.4.2.3 Linearity Analysis A wideband LNA requires high linearity to suppress the cross-modulation and intermodulation distortions that result from the increased co-existence of adjacent blockers or the on-chip transmitter leakage (see Chapter 1). While the noise of nanometer CMOS improves with scaling, the linearity deteriorates with supply voltage, high mobility effects, and the transistor velocity saturation effect. In general, the amplifier linearity can be controlled either by changing the characteristic of the intrinsic MOSFET device itself (see Section 2.1.2.1) or by using linearization circuit techniques (see Section 2.1.2.2). Neither of these techniques should affect the noise performance of the circuit – i.e., shifting of the dynamic range has to be avoided. Even though the nonlinearity of the MOSFET drain current can be generated either from the nonlinear transconductance or from the nonlinear drain conductance, the latter will be ignored assuming that the load resistors R1 and R2 are relatively small. Consider the circuit diagram of the described noise-cancelling LNA topology shown in Fig. 2.31. The input signal at the gate of M1 is large in amplitude relative

R1

To cancel the second order distortion of M2

R2

RFout

−

gm1(v x)

3

+

Vbias ο RBias

M3

g''m1(vx)

M4

M1 +

Vx RFin

Rs

ro1 −

RF

g'm1(v x )

2

M2

C

Fig. 2.31 Noise-cancelling CG LNA topology incorporating a second order distortion free circuit technique in the common-source stage M2. The nonlinearity transconductance of M1 is demonstrated by g¢m and g¢¢m


55

to the other transistors due to the feedback. Therefore, M1 nonlinearity plays a significant role in controlling the overall IIP3 value. As discussed in Section 2.1.2.2, feedback can be utilized to reduce the distortion. Resistor RF is used as a negative feedback for M1 in order to decrease the input signal swing and hence improve the linearity of the feedback path. Cancelling the RF noise in this topology allows for a wide dynamic range to be reached. The common-source transistor M2 also uses negative feedback for noise cancellation as well as to cancel the distortion. Therefore, M2 linearity improves as the loop gain increases. Second-order nonlinearity is usually not of primary concern in the LNA design because it results in distortion that is outside of the frequency of interest. However, due to the feedback configuration of the described amplifier, secondorder nonlinearity may contribute third-order distortion. The common-source transistor M2 generates second order distortion at the circuit output, which propagates linearly to the input through the feedback path. The second-order nonlinearity of M2 combines this second-order distortion with the fundamentals at the amplifier input, producing third-order distortion. Finally, this third-order distortion propagates linearly to the output. Concurrent cancellation of the intrinsic thirdorder distortion from the CS and CG stages then limits IIP3 by the second-order interaction between them. Therefore, in order to achieve very low third-order distortion, it becomes vitally important to linearize both second and third-order nonlinearities. Although the LNA topology serves as a single-to-differential converter, it does not suppress second-order nonlinearity, as would a fully-balanced circuit. However, this can be compensated by using a PMOS transistor (M4) as a common-source amplifier with the NMOS CS transistor as shown in Fig. 2.31 [102]. The output current from the PMOS and NMOS transistor can be expressed as

g' g ''   iout = in + i p =  gmn × vin + mn × v 2 in + mn × v3in  2 6   g 'mp   g '' (2.48) −  gmp × (−vin ) + × (−vin )2 + mn × (−vin )3  2 6   ( g 'mn − g 'mp ) 2 ( g ''mn + g ''mp ) 3 = ( gmn + gmp ) × vin + × v in + × v in 2 6

where gmn and gmp are the NMOS and PMOS transconductances respectively and g¢mn, g¢mp, g¢¢mn, and g¢¢mp are the second and third derivatives of the NMOS and PMOS transconductances. As can be seen in (2.48), the single-ended input current iout is free from second-order distortion if g¢m is well matched. As for dynamic range, the added PMOS transistor M4 doesn’t affect the noise of the amplifier since its noise can be cancelled in a similar way as the M2 noise was cancelled. Moreover, the bias current of NMOS transistor M2 is reused in PMOS transistor M4, thereby all the current reuse technique benefits can be

56


utilized (see Section 2.3.1). Another advantage of M4 is that the current reduction in the load resistor R2 facilitates using high resistance values, allowing for a smaller chip area.

2.5 Chapter Summary This chapter has examined the problem of designing wideband CMOS low-noise amplifiers (LNA) with wide dynamic range (DR) and has presented solutions to improve the state-of-the-art LNA performance. The intrinsic dynamic range (DRMOS) in CMOS is proportional to the amount of current consumed. Thus, the more current MOSFETs consume, the wider DR they can achieve. Additionally, this DR can be shifted up or down using the gate bias voltage (Vgs) for constant current consumption. Since MOSFET-based LNAs have to provide a 50 W input match to their antennas, their dynamic range would shift from DRMOS. Hence, several LNA topologies have emerged based on the technique used to provide the matching, each with its own distinct dynamic range. For fixed current, the R-CS topology shifts up the DRMOS because of the 50 W resistor added at the transistor gate for matching. The current consumption and the gate bias can still be used to control the DR of this amplifier. However, the achieved DR would be limited by the thermal noise of the matching resistor, a problem that can further be avoided by using reactive components for matching. The L-degenerate topology shifts down the DRMOS due to the LC network added at the transistor gate for matching. Adding these matching elements to the MOSFET transistor provides an additional degree of freedom in controlling the DR of these amplifiers. In addition to the current consumption and gate bias, the passive gain of the LC matching network can be used to shift the DR up and down. In fact, this DR can be shifted down until its lower limit hits the NFmin value of a MOSFET. Despite these beautiful features, the expensive on-chip coils make this topology unattractive for low-cost production. Naturally, wideband amplifiers such as CG and SFB amplifiers are good alternatives, especially in nanometer CMOS technologies. The CG topology can provide a wideband input match through the intrinsic properties of the MOSFET, the transconductance (gm). This makes the DR of these amplifiers fixed and dependent on the DC power consumption that is constrained by the input matching requirement. Moreover, this fixed DR (i.e., NF) is inadequate to achieve the sensitivity required by most modern communication systems (−100 dBm). The SFB amplifiers can break this trade-off and therefore allow flexibility in the DR optimization, but their matching mechanism prevents them from achieving the DRMOS at low-power consumption. The feedback resistor must be increased in order to decrease its noise contribution. This unfortunately requires high current consumption to preserve the matching. The amount of power needed to widen the DR makes SFB amplifiers an unattractive solution for portable receivers. In most CMOS amplifiers, the current reuse technique can be used to

2.5 Chapter Summary

57

cause a downward shift of the DR. However, even with the use of this technique, R-CS, SFB, and CG amplifiers cannot fulfill the performance requirements of modern wireless receivers. Several noise and distortion cancelling techniques have been described to overcome the shortcomings discussed above. The cross-coupling capacitive technique has been applied to the CG amplifier to partially cancel the transistor noise contribution at the output. The dynamic range is improved with respect to the conventional CG topology but the input match constraint remains, and DR is still fixed. Recently, Chehrazi proposed a technique to completely cancel the noise of the matching transistor in the CG amplifier and therefore break the matching-noise figure trade-offs. Breaking this trade-off allows the possibility of controlling the amplifier DR by varying the current consumption without any constraints. However, this flexibility comes at the expense of the power consumption of the added amplifier “A” needed to cancel the CG transistor noise. Therefore, the current noise-cancelling CG amplifier can achieve the same DRMOS but at higher power consumption. This chapter presents a noise-cancelling technique to decrease the power consumption of current noise-cancelling CG amplifiers. By using active negative feedback, the noise of the added amplifier “A” can be eliminated. This allows the CG amplifiers to achieve the DRMOS with lower power consumption than the current state-of-the-art. The described amplifier can also be seen as an SFB amplifier with noise-cancelling feedback resistor (shown in Fig. 2.32) and with a more relaxed power requirement on the matching MOSFET (Mmain) compared with the current state-of-the-art SFB amplifiers. The physical fundamental noise limit of the described solution has been examined by exploring the power, linearity, input match, and gain trade-offs. The next chapter presents the IC design of a wideband CMOS LNA using the cancelling techniques introduced in this chapter and looks at the challenges associated with the LNA implementation.

RFB eliminates the noise of A RFB noise is cancelled by the differential sensing

RFin

RFB

A

Mmain noise is eliminated by A

Rs Mmain

Fig. 2.32 The proposed noise-cancelling solution in this work can be seen as an SFB amplifier that implements noise free feedback resistor RFB

Chapter 3

Nanometer CMOS LNAs for Mobile TV Receivers

This chapter presents the design of a wideband low-noise amplifier in 65 nm digital CMOS technology that takes advantage of the noise and distortion cancelling techniques described in Chapter 2. In addition to examining the practicality of these techniques, this chapter also discusses the challenges associated with using a nanoscale technology such as the 65 nm CMOS process, including the MOSFET low output resistance, the high resistivity of the polysilicon material, the increased substrate coupling, and the use of a digital transistor layout that is not optimized for radio frequency (RF) operation. Furthermore, this chapter examines ways to achieve the nonlinearity requirement of the mobile TV application while providing RF gain control in the LNA. Lastly, this chapter looks at biasing techniques that allow the LNA to withstand process and temperature variations, and verifies the design’s performance using lab measurements from tests conducted on a prototype of the designed LNA.

3.1 Requirements of the LNA in Mobile TV Receivers This section presents the LNA specifications that allow a receiver to meet the requirements of the mobile TV standard, DVB-H. Figure 3.1 shows a DVB-H receiver that has been introduced to help extract the DVB-H LNA performance requirements. The receiver baseband circuits are based on the state-of-the-art solutions reported in [34, 35] (see Chapter 1). A post-mixer amplifier (PMA) is used to provide the gain and filtering needed to relax the dynamic range of the ADC (Analog-to-Digital converter). The gain and noise specs of these circuits are shown in Fig. 3.1. A maximum signal level of −6 dBm is required at the input and the output of the PMA circuit in order to allow the baseband chain to achieve the desired linearity of the DVB-H mobile TV standard. While the PMA circuit provides a variable gain


59

60

3 Nanometer CMOS LNAs for Mobile TV Receivers

−6 dBm max

−6 dBm max

Baseband Circuits PMA

ADC

RFin RF Front-end Circuit

Post Mixer Amplifier

PMA

Gain

0 dB-21 dB

Noise

10 nv/Hz0.5

I

Σ∆ ADC

ADC

Q

60 nv/Hz0.5

Fig. 3.1 The mobile TV DVB-H receiver

function to maintain the signal level at −6 dBm at its output, the RF front-end (FE) has to provide the same function (gain control) in order to adjust the signal level at the PMA input. The RF front-end circuit requirements (i.e., Gain, NF, IIP3) are derived taking the baseband circuit specifications into account. These front-end specifications then determine the LNA performance goals.

3.1.1 DVB-H RF Front-End Specifications Chapter 1 defined the NF and IIP3 values required for a receiver to be compatible with the DVB-H standard. A receiver NF of less than 5 dB is needed to achieve the sensitivity requirement (−86.6 dBm for 16QAM modulation). However, the lowest possible NF value is desirable (NF < 3 dB) to ensure satisfactory TV signal reception. This LNA design example targets a NF of 2 dB. The IIP3 value should be set to comply with all interferer patterns included in the standard. To simplify the analysis, only the most stringent interferer’s patterns are considered here (Table 3.1). The DVB-H front-end circuit has to provide a certain amount of gain in order to minimize the baseband noise contribution to the overall cascaded NF. Using Friis equation, 42 dB of gain is required to limit the noise contribution of the baseband circuits (Fig. 3.1) to 0.1 dB. This would then result in a cascaded NF of 2.1 dB (in case if the LNANF = 2 dB). Although a gain of 42 dB helps in achieving the sensitivity requirement, it can cause a lot of distortion if there is a large interferer

3.1 Requirements of the LNA in Mobile TV Receivers Table 3.1 Interferer signal patterns of the DVB-H standard [31] Modulation Undesired/ Pattern of interferer Interferer location desired (dB) S1 Analog 40 N + K (K ¹ 0, 1) L3 Digital N + 2b and N+4c 40 a N: desired channel (8 MHz bandwidth). b N + 2 blocker locates at 16 MHz. c N + 4 blocker locates at 32 MHz.

61

Desireda (dBm) −68 −75

Undesired (dBm) −28 −35

level at the RF input. For example, in an S1 pattern reception scenario, in order to prevent the receiver from clipping (maximum of −6 dBm at the PMA input), the gain of the front-end has to be adjusted to 22 instead of 42 dB. At this gain, the required NF for the DVB-H receiver is equal to 18 dB (carrier-to-noise ratio C/N is set to 19.2 dB for 64QAM signal). The 18 dB NF will limit the dynamic range of the DVB-H receiver since the S1: N + 2 interferer third-order distortion IM3 does not fall within the desired channel bandwidth. The IIP3 value does not affect the dynamic range in this case. On the other hand, in the case of receiving an L3 pattern, the interferers are two digital signals located at N + 2 and N + 4, i.e., 16 and 32 MHz away for the desired signal respectively. In this case, IM3 products fall within the desired channel and can cause third-order intermodulation distortion. If we set the signal level at the PMA input at −6 dBm while receiving a −35 dBm digital interferer (see L3 pattern in Table 3.1), the gain of the front-end should be adjusted to 26 dB. At this gain, an IIP3 value of −8 dBm is required (see Chapter 1). From the above discussion, it can be deduced that to achieve both L3 and S1 requirements, high linearity at high gain setting and low noise figure at lower gain setting are required. The trade-off between the linearity and noise is inevitable, which makes the design of the variable-gain DVB-H front-end circuit challenging. The target performance of the DVB-H front-end (FE) is given in Table 3.2. Additionally, it must be noted that a minimum gain of −6 dB is required so as not to saturate the baseband circuits at a maximum desired input signal level in the range of 0 dBm.

3.1.2 DVB-H LNA Performance Requirements An RF front-end circuit consisting of an RF passive attenuator, wideband LNA, and a passive quadrature mixer is introduced as a candidate for the DVB-H receiver (shown in Fig. 3.2). The high linearity of the passive mixer compared with the active mixer makes the former a better choice for the DVB-H application [40]. A quadrature version of the mixer is used to facilitate the generation of the in-phase (I) and quadrature- phase (Q) signals. The mixer’s specs are shown in Fig. 3.2. Based on these specifications, the LNA has to provide 36 dB of gain across the UHF band and an NF of 2 dB in order to achieve the sensitivity requirement of the DVB-H receiver.

62

3 Nanometer CMOS LNAs for Mobile TV Receivers Table 3.2 RF front-end target specifications for the DVB-H front-end receiver UHF: 47 0-862 MH z

Frequency range

Maximum gain

42 dB

NF @ Maximum gain

2 dB

Minimum gain

- 6 dBa

NF @ FE gain of 22 dB

18 dBb

IIP3 @ FE gain of 26 dB

>-8 dBmc

Supply voltage

2.5 V

Technology

65 nm CMOS

To achieve the sensitivity requirement

To achieve the maximum input level requirement To achieve the selectivity requirement To achieve the linearity requirement

aBaseband

circuit gain =0-21 dB. 64 QAM C R = 2/3, C/N = 19.2 dB, 8 MHz channel bandwidth (noise floor = -105 dBm). cAssuming -35 dBm digital interferers at 6 and 32 MHz. bAssuming

RF FE: RF Front-end

Quadrature Passive Mixer

RFin

I

Baseband Circuit Chain

LNA

Q Gain: 6 dB (Differential) Noise: 1.5 dB RF attenuator

IIP3: +20 dB

Fig. 3.2 The variable gain RF front-end for the DVB-H receiver

In the case of S-pattern reception, the LNA has to drop 20 dB from its maximum gain (36 dB) to avoid any kind of degradation in the overall linearity. However, system analysis show that in order to maximize the receiver dynamic range, a gain drop of only 6 dB should be provided by the LNA while the remainder of the 14 dB gain drop is to be provided by a passive RF attenuator preceding the LNA (see Fig. 3.2). A detailed discussion about the effect of using an RF attenuator to optimize receiver dynamic range is given in Chapter 4. According to this discussion, the minimum gain of the LNA is set to 30 dB. At this gain, the NF looking at the LNA input has to be 4 dB to achieve the dynamic range requirement at S-pattern interferer reception. Using the cascaded IIP3 expression:

1 IIP32 Front − end

≈

1 ( LNA _ Gain)2 + IIP 32 LNA IIP 32 Mixer

(3.1)

3.2 A 65 nm CMOS Wideband LNA Prototype

63

Table 3.3 The target specifications of the DVB-H wideband LNA Frequency range Maximum gain

UHF: 47 0-862 MH z 36 dBa

NF @ Maximum gain

2 dB

Minimum gain

30 dB

NF @ Mini mum gain

4 dBb

IIP3 @ Minimum gain

>-17 dBmc

Supply voltage

2.5 V

Technology

65 nm CMOS

To achieve the frontend NF specs To achieve the selectivity requirement and to maximize the receiver dynamic range To achieve the linearity requirement

a

The mixer has a differential gain of 6 dB. To allow a 18 dB cascaded NF at the S1 interferer pattern reception. Mixer IIP3= +20 dBm, LNA gain is 30 dB, a 10 dB gain reduction is provided by the RF attenuator. b c

the LNA IIP3 has to equal at least −17 dBm to help the DVB-H receiver to achieve the L3 linearity pattern requirement (in this case: the IIP3Front-end = −8 dBm, IIP3Mixer = +20 dBm, and the LNA_Gain = 30 dB). The summary of the DVB-H LNA requirements is given in Table 3.3. It is noted that the IIP3 value requirement of the LNA is relaxed by the amount of the passive attenuator attenuation (IIP3LNA = −7 dBm is required without using the passive attenuator to control the RF gain).

3.2 A 65 nm CMOS Wideband LNA Prototype This section describes the design of a wideband LNA that meets the specifications of the DVB-H mobile TV standard. The noise and distortion cancelling techniques described in Chapter 2 have been used in order to widen the LNA’s dynamic range. A variable-gain control mechanism is implemented in this LNA in order to improve the overall receiver linearity. The success of the fabricated LNA in achieving the target performance depends strongly on the techniques used to optimize the silicon layout. Additionally, the layout parasitics as well as the package parasitics must be taken into account before taping out the design. The practicality of the design demands reliable bias generator circuits that can help the LNA circuit to achieve the performance goals independent of the amount of power supply noise, and process and temperature variations. Furthermore, to facilitate the LNA prototype characterization in the lab, auxiliary circuits are needed to interface the LNA to the 50 W environment of the measurement equipment. Two multi-mode buffers are designed and integrated to allow successful noise figure and linearity measurements for the DVB-H LNA prototype.

64


3.2.1 LNA Core Circuit 3.2.1.1 LNA Circuit Description The schematic circuit diagram of the LNA is shown in Fig. 3.3. The common-gate (CG) transistor M1 is used to provide a wideband input matching (across the UHF band) to a 50 W source impedance. The feedback resistor RF is used to eliminate M1 noise as well as to cancel part of its distortion as described in Section 2.4.2. The inductor Lbias is used to provide a DC path for the M1 device. The use of an inductor instead of the conventional bias method of using a current source helps in avoiding the added noise of the latter. The inductance value is selected so any resonance that might occur at the LNA input is out of its frequency band of operation. 2.5 V

RFin 2.5 V

Cc2

Common-gate branch

M4 20K

+ OTA −

20K

Ο

R1

Vbias_CS_P

Vbias_cas_P

Ο +

RFout

M5 CMOS3

−

2.5 V

Ο

Ο

M6

M3

Cc3

20K

M1 Common-source branch

RF

Cc1

RFin

M2

Lbias

5K

Ο

5K CMOS2 CMOS1

10µA

2.5 V

Vbias_cas_N

Vbias_CS_N

Ο Vbias_CG

Fig. 3.3 The schematic diagram of the DVB-H wideband low noise amplifier

VREF


65

The common-source (CS) transistors M2 and M4 generate another path for the signal that allows cancelling the CG branch noise, M1 & RF noise (Section 2.4.2.1), when the output signal is sensed differentially. The current ratio in both branches (CG and CS branches) is adjusted to facilitate achieving the condition of the noise cancellation mentioned in Chapter 2. The noise of M2 and M4 is eliminated by the negative active feedback loop provided by the CG transistor M1 and the feedback resistor RF. The bias current of M2 is reused to bias M4 to save the current consumption. In addition to the power saving, the second-order distortion that M2 generates cancels some of the second-order distortion of M4. Since M1, M2, and M4 devices have negative feedback loops around them, the LNA IIP3 is expected to be limited by the second-order interaction between the CG and CS transistors (see Section 2.4.2.3). Cascode transistors M3 and M5 offer the capability of boosting the gain in order to overcome the low intrinsic gain of a MOSFET in 65 nm CMOS technology. However, this comes at the expense of increasing the voltage headroom and generating an unstable DC point at the (−RFout) node. To mitigate this, an operational transconductance amplifier (OTA) is introduced to stabilize this node. The OTA compares the voltage of the (−RFout) node to a reference voltage VREF and then uses the output to control the bias of the CS transistor M4. This guarantees that the DC voltage at the (−RFout) node is equal to a value very close to VREF depending on the precision of the transconductance amplifier (OTA gain). Two coupling capacitors (Cc1 and Cc2) are thus required to decouple the bias of M2 from M4 bias so that the OTA does not affect the M2 bias. Another coupling capacitor Cc3 is also used to facilitate the CG transistor M1 biasing. These coupling capacitors provide flexibility in optimizing the LNA design. The noise coupled through the power supplies as well as the noise generated from the bias generator circuits used to bias the CS and CG transistors (M1, M2, and M4) can have a deleterious effect on the LNA noise figure. In fact, their noise contributions can dominate the LNA NF. Hence, all the bias voltages are filtered by using low pass filters. Although the capacitors used in these filters are based on MOS devices (MOS-capacitors) to save silicon area, the amount of filtering is still limited by the area budget constraints. CMOS1 and CMOS2 are based on N-channel devices while CMOS3 is based on a P-channel device. This kind of implementation helps in rejecting any noise that might couple to the LNA through the supplies and ground traces.

3.2.1.2 LNA Design Trade-Offs Most of the amplifier trade-offs have been presented in detail in Chapter 2. Because 65 nm CMOS models were still unavailable at the time when the theory discussed in Chapter 2 was developed, simulation results used to support the theory were based on 0.13 µm CMOS models. Additional design considerations emerged with the use of this newer nanometer CMOS technology (i.e., 65 nm) and it is important that these considerations be highlighted here.

66


Simulation results show that the IIP3 value of the designed LNA in 65 nm CMOS is dominated by the MOSFET output resistance nonlinearity (see Section 2.1.2.1). Although the achieved IIP3 of −13 dBm using 65 nm CMOS models can still meet DVB-H receiver specifications, this value differs from the one mentioned in Chapter 2 (IIP3 = −5 dBm using 0.13 µm CMOS models). Improving the IIP3 value requires either an increase in the supply voltage or a decrease in the output signal swing on the CS transistors M2 & M4. Increasing the supply voltage comes at the expense of increasing the power consumption while decreasing the output signal swing degrades the LNA noise figure. As mentioned in Chapter 2 a higher loop gain in the feedback loop around M2 (proportional to the output signal swing of M2) results in a lower noise figure of the amplifier. Hence, decreasing the loop gain lowers the output signal swing and therefore improves the linearity and degrades the noise figure. The question that remains is what is the effect of the cascode transistor M3 on the CS transistor’s (M2) nonlinearity? It can be stated that lowering the output signal swing by adding the cascode transistor M3 does not improve the M2 nonlinearity. Adding the cascode increases the magnitude of the nonlinear coefficients due to the decrease of the DC drain-source voltage Vds, which mitigates the benefit of decreasing the output signal swing. As a result of this discussion, since IIP3 is limited by the output nonlinearity of the MOSFET, the M1 and M4 CS transistors are biased at the moderate inversion region in order to improve the current efficiency by maximizing the (gm/I) ratio. This allows lowering the power consumption for the same dynamic range for the LNA. The rest of the trade-offs (matching, gain, NF, power) are the same as described in Chapter 2. The loop gain is selected to be 1.6 by setting the ratio of (gm2/gm3) to be equal to 2. This loop gain value is found to be the best compromise between the input matching, noise figure, and the power consumption taking the 2.5 V supply voltage into account. Using this loop gain value, the noise of M1 and RF is completely eliminated and the noise of M2 and M4 is reduced by 50% relative to their noise without applying the feedback. The amount of the current noise reduction achieved in this design is shown in Fig. 3.4.

3.2.1.3 LNA Variable-Gain Control Function As discussed in Section 3.1, the LNA should be able to control the gain of the RF front-end of the DVB-H receiver. Implementing the gain control function in an LNA has been introduced in [22, 29]. In [22], the gain control was provided in the LNA by varying the gate–source bias voltage (Vgs) of the transistors, while the gain control in [29] was provided by varying the load current. A detailed discussion of these gain control techniques is given in the next chapter, where the dynamic range optimization for the DVB-H receiver is presented. In this LNA example, the first approach has been considered to provide the gain control function in the DVB-H LNA design example. However, instead of varying the gate–source voltage, the drain–source bias voltage is changed, so as to


a

100% reduction in RF&M1 noise R1

Ro

0.6in

Noise current

67

b

50% reduction in M1 noise R1

Ro

0.5in

RFout

RFout

3in M1

M1

in RF

M3

0.06in

RF

M3

M2 RFin

M2 RFin

in

Noise current

Fig. 3.4 The amount of noise cancellation achieved in the DVB-H LNA: (a) illustrates the amount of the noise current that leaks from the CG branch to the outputs while (b) shows the amount of noise current that leaks from M2 transistor to the outputs. Ro is the equivalent resistance at the drain of the cascode transistor M3

take advantage of the variations that exist in the nonlinear output resistance for a MOSFET in 65 nm CMOS technology when the drain–source voltage (Vds) is varied. As Vds increases and the pinch-off moves toward the source, the rate at which the depletion region around the source becomes wider decreases, resulting in a higher incremental output resistance. The output resistance for a MOSFET (roMOS) can be approximated by [106]:

roMOS =

2L 1 1 − ( DL / L ) I D

qN B (Vds − Vds ,sat ) 2e si

(3.2)

where Vds,sat is the drain-source voltage at the onset of pinch-off, L is the transistor channel length, ID is the drain current, esi is the dielectric constant of the silicon, q is the electron charge, NB is the doping concentration of the substrate, and DL is the variation in the channel length for a given increment in Vds. As shown in Fig. 3.5, since the OTA fixes the DC bias at the (−RFout) node to a value equal to VREF, the bias of this node can be varied by varying the VREF value. Changing the bias at the (−RFout) node consequently changes the total output resistance at this node (RoutCS-branch), and thus changes the LNA gain. This can be seen by writing the LNA gain expression (only the common-source branch is considered here)1: 1 In this derivation, the effect of ro2 and ro4 on the effective transconductance of this branch is ignored.

68

3 Nanometer CMOS LNAs for Mobile TV Receivers 2.5 V

RFin 2.5 V M4 +

OTA

Ο

Ο

−

Vbias_CS_P

Vbias_cas_P M5

RoutCS-branch

10µA

− RFout 2.5 V

Common-gate branch Vbias_cas_N

Ο

RFin

M3

M2

M1

Ο VREF

20K

Common-source branch

RF

Fig. 3.5 Simplified schematic diagram for the DVB-H LNA indicating the gain control mechanism

Gain _ LNACS

branch

≈ ( gm 2 + gm 4 ) RoutCS

branch

(3.3)

where, RoutCS

branch

= (1 + ( gm 3 + gmb 3 )ro2 )ro3 + ro2  / / (1 + ( gm 5 + gmb 5 )ro4 )ro5 + ro4  (3.4)

where gm2, gm3, gm4, and gm5 are the transconductances of M2, M3, M4, and M5, respectively, gmb3, gmb5 are the back gate transconductances of M3 and M5, respectively, and ro2, ro3, ro4, and ro5 are the output resistances of M2, M3, M4, and M5 respectively. As can be seen from (3.4), if the designed LNA gain is limited by ro2 and ro3, as is the case in this example, and the bias voltage at the (−RFout) node decreases, the first part of expression (3.4) decreases while the second part increases. This results in a decrease in the total output resistance (RoutCS-branch) at the output node and thus the LNA gain decreases. One can note that the gm3, gm5 values also change with Vds (gm ∝ (1 + lVds ) ) where l is the transistor channel length modulation coefficient.


69

The circuit needed to generate the variable bias VREF is given in Section 3.2.2.3, where the design of the OTA bias circuit is presented. VREF variations are limited by the bias condition required to keep M2, M3, M4, and M5 transistors in the saturation region. In this example, the VREF is varied just twice to provide two gain steps for the DVB-H LNA, each one equal to a 3 dB drop from the maximum gain. A decrease in the LNA gain results in a change in performance relative to that achieved at the maximum gain mode of operation. The LNA NF degrades while decreasing the gain since changing the CS branch gain violates the noise-cancelling condition (see Section 2.4.2.1) required to optimize the LNA NF. However, since the decrease in the LNA gain is a result of a large input signal at the LNA input, the noise performance required in this case is somehow relaxed (see Table 3.3). The achieved linearity at the LNA minimum gain settings also differs from that achieved at maximum gain mode. Since the nonlinearity in the designed DVB-H LNA is limited by the MOSFET output resistance nonlinearity (i.e., ro2), decreasing the bias voltage at the (−RFout) node (to decrease the LNA gain) degrades the IIP3 value. This can be explained by noting that decreasing Vds voltage for a MOSFET results in an increase in the magnitude of the nonlinear coefficients of its output resistance rMOS (see Section 2.1.2.1), which results in a degradation of the IIP3 value. The achieved IIP3 value at minimum gain mode is important for the DVB-H receiver to meet the linearity requirements of the L3 interferer pattern. Another factor to consider is the impact of changing the LNA gain on the input matching requirement. Since the transconductance of transistor M3 changes while changing the LNA gain, the loop gain around the matching transistor M1 also changes. As discussed in Section 2.4.2.2, changing this loop gain value results in changing the LNA input impedance. Therefore, if the loop gain around M1 is optimized to set the LNA input impedance to a 50 W value at maximum gain mode of operation, the input matching would degrade at the LNA minimum gain settings. To resolve this issue, the feedback resistor RF can vary to compensate for the input matching deviation caused by changing the loop gain. However, in this design example, the degradation in the input matching at the LNA minimum gain settings was found to be acceptable and hence the DVB-H LNA can still be matched to a 50 W at the minimum gain mode. 3.2.1.4 LNA Physical Implementation In order to achieve the expected LNA performance, especially the low noise figure, very careful attention must be given to the LNA layout. The MOSFET transistor provided through the digital design kit is not optimized for RF operation. First, the transistor layout has to be designed in a way that makes the effect of the MOSFET gate resistance on the LNA noise figure negligible. The transistor is broken into multiple fingers in order to overcome the high resistivity of the polysilicon material in the 65 nm CMOS process (~14 W/square) [103]. For example, a minimum feature length MOSFET in 65 nm CMOS with a 15 µm width results in 1 kW gate resistance. The same transistor results in 2.7 W gate resistance when it is broken

70


into 20 fingers. This resistance can be decreased even further by contacting the gate at both ends (~0.6 W in this case). The only disadvantage of breaking the transistor into multiple fingers is the increase in the substrate resistance and routing parasitics. However, this can be avoided by subdividing the transistor into multiple unit cells [104]. Any ground current that might flow through the substrate is now soaked up by the low resistance path through the substrate contacts. Additionally, using the multiple unit cells configuration for a MOSFET allows the DC current to split such that the maximum current density for each of the metals used in the transistor layout does not violate the maximum amount allowed by the design rules of the 65 nm CMOS technology (i.e., 1.5 mA/µm for metal 1). Another issue that has to be considered with regards to the transistor RF optimization is the substrate coupling. Since the ultimate goal of the designed LNA is to be integrated with the rest of the DVB-H system, avoiding the substrate coupling is critical as it can increase the noise floor of the LNA circuit, and thus, damage the overall receiver sensitivity. To shield the NMOS transistors from any noise that might couple through the substrate, a deep N-well is used to improve the isolation. Doing so also allows connecting the source of the transistor to the substrate, thus one can avoid changing the device characteristics by the bulk-source voltage variations. An example of a digital transistor layout that is optimized for the RF operation is shown in Fig. 3.6. The coupling capacitors (Cc1,Cc2, and Cc3) are implemented using a number of shunt MIM-capacitors in the N-well in order to improve the LNA shielding (see Fig. 3.3). The N-well of Cc1 and Cc3 is connected to the ground bond while the N-well of Cc2 is connected to the power supply bond. The silicon area of these capacitors is reduced by taking the transistor sizes of M1, M2, and M4 into account. Other types of capacitors that are available in the 65 nm CMOS process are the MOS-capacitors. These capacitors are used in this design example to implement the filtering capacitors CMOS1, CMOS2, and CMOS3 because of their high capacitance density (10 fF/mm2 in the 65 nm CMOS process) [105]. Thus, a huge saving in the silicon area can be achieved by using MOS-capacitors instead of MIM-capacitors (2 fF/mm2 in the 65 nm CMOS process). Note that MOS-capacitors have not been used to implement the coupling capacitors because of the distortion they can generate in the signal path. A detailed discussion regarding the implementation

Substrate contacts One transistor unit Gate fingers

Gate is contacted at both ends

Fig. 3.6 Optimizing the layout of the transistor M4 for RF operation


Metal 6

71

Metal 7

M4 transistor

Gate is contacted at both ends

Fig. 3.7 Die photograph of the PMOS transistors M4 used in LNA core circuit. Transistor M4 has a length of 60 nm and a width of 136 µm. Each transistor has been broken into multiple unit cells. Each unit cell has 17 fingers. The polysilicon gate is connected at both ends to further decrease the transistor’s gate resistance. The ultra-thick metal 7 as well as the thick metal 6 are also shown

of MOS-capacitors in the 65 nm CMOS process is given in Chapter 4. The resistors used to provide filtering to the supply noise have been implemented by using P+ poly resistors without silicide material since they have a very high sheet resistance (~700 W/square). A final issue to consider in the layout of the LNA is the routing parasitics. The ultra-thick metal (metal 7, thickness = 3.4 nm) is used as much as the process design rules allow in routing the signal path traces from the LNA input pad to the LNA output pad. In fact, sometimes, a stack of metals (metal 1 through 7) is used to further decrease the parasitic resistance. During the LNA circuit simulations, the extracted parasitics have been taken into consideration. Moreover, the pad capacitance as well as package bond wire parasitics have also been taken into account. The die photograph of the RF transistors (M4) is shown in Fig. 3.7, while the fabricated die photograph of the LNA core circuit is shown in Fig. 3.8.

3.2.2 DC Bias Generator Circuits The design of the bias circuits is critical for ensuring optimal LNA performance. The bias circuits should be designed in a way that makes the LNA performance independent of the power supply voltage variations. Any coupled noise from the supply can easily increase the noise floor of the LNA and thus, degrade its noise performance. Additionally, any noise generated from the bias circuits themselves should be filtered so as not to contribute to the LNA NF.

72

3 Nanometer CMOS LNAs for Mobile TV Receivers 230 µm

180 µm

Cc1

37µm

OTA

M4

30µm

Cc2

Cc3

Fig. 3.8 Die photograph of the LNA core circuit

Another important property of these bias circuits is that they should provide a stable current independent of temperature and process variations. The MOSFET threshold voltage as well as the mobility exhibit temperature dependence [106]. The simple resistive biasing circuit shown in Fig. 3.9, for example, generates unstable drain current since the gate voltage is dependent on the supply, process, and temperature. Therefore, it can negatively affect the NF performance of the designed LNA. Current mirrors are used in this work to mirror a precisely-defined current source that is already available through a bandgap reference operating at a 1.2 V supply [106]. The bandgap reference generates bias that is independent of the supply voltage and robust against temperature and process variations. The bias scheme used for the mobile TV LNA is illustrated in Fig. 3.10. Three different bias generator circuits have been designed to bias the LNA core. Bias circuit (1) takes a 10 µA bandgap current and provides the bias for the cascode transistors M3, M5 and M6. Since transistors M3 and M6 share the same bias, only two different voltages have been generated (Vbias_cas_N, Vbias_cas_P). Bias circuit (2) also takes a 10 µA bandgap current and provides the bias for the CS transistor M4 (Vbias_CS_P). An OTA has been used to stabilize the LNA common-mode voltage. Finally, bias circuit (3) takes a 100 µA bandgap current and provides the bias for the transistors M1 and M2 (Vbias_CG, Vbias_CS_N). To resolve any chance of transistor breakdown in these bias circuits, the transistors are chosen to be 2.5 V devices that are available in the 65 nm CMOS process instead of the 1.2 V devices used in the LNA core. The following sections describe each of these bias generator circuits in detail.


73

Fig. 3.9 Simple resistive bias generator circuit noise

Iout R1 M1 noise

R2

1.2V Bandgap Reference Current

10 µA

Vbias_cas_N Vbias_cas_P

100 µA

Cascode Bias Generator Circuit (M3, M5, M6)

2.5V

CS & CG Bias Generator Circuit (M1, M2)

(1)

Vbias_CS_N Vbias_CG

(3) Common-Mode Stabilization Circuit (OTA-M4) (2)

Vbias_CS_P

Fig. 3.10 Biasing schemes used to generate the required bias for the LNA core

3.2.2.1 Cascode Bias Generator Circuit The circuit used to generate the bias for the cascode transistors in the LNA core is shown in Fig. 3.11. The current mirror employed by MBias_cas1 and MBias_cas2 maps the 10 µA of the bandgap reference current to 20 µA. This 20 µA current is then used to provide the bias voltages, through a variable resistor, to the cascode transistors. A variable resistor is selected to provide flexibility while conducting the lab measurements. In this case, the generated voltage is independent of the power supply noise as well as the process and temperature variations. The current mirrors employ large channel length (L = 2 µm) in order to improve the accuracy of the current mapping

74

3 Nanometer CMOS LNAs for Mobile TV Receivers 2.5 V

CBias_cas3

Bandgap Reference 1.2 V MB as_cas3

MBias_cas4

MBias_cas5

10 µA 4K

Vbias_cas_N

R MBias_cas1

MBias_cas2

4K

R

41.25K

41.25K CBias_cas1

CBias_cas4

20 µA

Vbias_cas_P

20 µA

CBias_cas2

20 µA

Fig. 3.11 Bias generator circuit of cascode transistors M3, M5, and M6

by increasing the transistor output resistance. Additionally, the same length for all of the transistors is used to minimize the errors due to side-diffusion of the source and drain area. MOS-capacitors CBias_cas1 and CBias_cas2 are used to guarantee that the cascode gates are AC grounded, hence improving their characteristics as current buffers. The variable resistor is shown in Fig. 3.12. It is digitally controlled through four switches SW1, SW2, SW3 and SW4. When the switches are closed, the output voltage is ~825 mV, while when they are open, the output voltage is ~1.8 V. The switches can turn ON and OFF in multiple combinations to generate binaryweighted voltages with a minimum increment of 60 mV. The type of the resistor units used to implement the variable resistor have been selected to match the resistor used in the bandgap circuit in order to provide voltage that is independent of the temperature variation [106]. 3.2.2.2 CS and CG Bias Generator Circuit The circuit used to generate the bias for the CS transistor M2 and CG transistor transistor M1 is shown in Fig. 3.13. The current mirror employed by MBias_CS&CG1 and MBias_CS&CG2 maps the 100 µA of the bandgap reference current to 900 µA. The CS transistor is biased through the current mirror transistor MBias_CS&CG5, while the CG transistor is biased through the voltage generated by a 2 kW resistor. These biases are independent of the supply, process, and temperature variation. However, they can be affected by the mismatch between the mirror transistors especially with


75

Fig. 3.12 The binary-weighted digitally-controlled variable resistor used in the cascode bias generator circuit

2.5 V

20 µA

4K

I

SW1

SW2

SW3

SW4

Output

25K

12.5K

6.25K

3.125K

41.25K

using the 65 nm CMOS process. In general, the transistor matching is more of a concern in nanometer CMOS processes than when using other, less advanced technology [107]. In order to improve the matching in this circuit, wide transistors have been used for the mirror transistors. Additionally, dummy devices have been added to the transistor layout to mitigate any mismatch that may occur from the well proximity effect [108]. 3.2.2.3 Common-Mode Stabilization Circuit The operational transconductance amplifier (OTA) shown in Fig. 3.14 has been used to bias the CS transistor M4 of the LNA core. A feedback loop is employed around the OTA to facilitate generating a stable DC value equal to VREF at the common-mode node of the LNA CS branch. The OTA consists of a differential pair (MOTA5 & MOTA6) loaded with an active current mirror (MOTA7 & MOTA8). The tail current is provided by two current mirrors (MOTA1 & MOTA2) and (MOTA3 & MOTA4)

76

3 Nanometer CMOS LNAs for Mobile TV Receivers 2.5 V Bandgap Reference 1.2 V

MBias_CS&CG3

MBias_CS&CG4

100 µA

MBias_CS&CG6 60K 2K

Vbias_CG

60K

MBias_CS&CG1

MBias_CS&CG5 MBias_CS&CG2

900 µA

Vbias_CS

900 µA

Fig. 3.13 Bias generator circuit of the CS (M2) and CG (M1) transistors

that are biased by a 10 µA bandgap reference current. A variable resistor R is employed to provide variable values of VREF in order to facilitate the gain control function in the LNA. The same variable resistor described in Section 3.2.2.1 is reused here. The open loop gain of the OTA is chosen according to the precision required of VREF (i.e., 40 dB of gain gives 1% error in VREF). A 30 dB of gain is chosen in this design example. The sizes of the transistors have been selected to make them operate in the saturation region at different values of VREF. One of the most important issues in this bias circuit is the OTA stability. As shown in Fig. 3.14, the LNA-CS branch acts as a second stage class AB amplifier (M4 & M5) connected at the output of the OTA circuit. M4 and M5 transistors create a high impedance point at the (−RFout) node in the feedback loop, which can cause the negative feedback to be converted to positive feedback at certain frequencies, and thus create a stability problem. Moreover, the added gain of the M4 and M5 transistors increases the chance of oscillation. Therefore, a DC stability analysis has been conducted on this feedback loop. This analysis took into consideration all the non-dominant poles originating from the low-pass filters used for noise filtering along with the coupling capacitors. Additionally, the output load capacitance CL of the buffer needed to interface the LNA to the measurement equipment was also taken into account. Simulation results showing the loop gain as well as the phase margin of the feedback loop are shown in Fig. 3.15. A loop gain of 49 dB and 80° phase margin has been achieved to provide the stability of the feedback loop. The accuracy in achieving a precise value of VREF depends strongly on the physical implementation of the OTA circuit. The physical implementation of the OTA circuit


77

OTA Circuit 2.5 V

2.5 V

20 µA 1.2 V

MOTA3 Bandgap Reference

MOTA4

VREF

VREF >2.5 - VGS4 - VthOTA6

R

LNA-CS branch

10µA

Inp

Inn MOTA5

MOTA6 Vbias_CS_P

MOTA1

For MOTA6 to be in saturation:

MOTA2

MOTA7

2.5V

M4

MOTA8

M5

Ο - RFout

20K Feedback loop

M3

CL

Fig. 3.14 Operational transconductance amplifier used to bias the CS transistor M4. The OTA circuit with the LNA-CS branch circuit acts as a two stage opamp

is shown in Fig. 3.16. As noted before, dummy elements have been used to improve the matching between the mirror transistors. Moreover, each transistor has been broken into multiple unit cells as recommended by the foundry to avoid the oxide stress effect that might occur with using the 65 nm CMOS process [108]. One of the most important issues in the OTA physical implementation is the matching between the differential pair transistors. The interdigitating layout style has been used to implement the differential pair transistors (MOTA5 & MOTA6) in order to make them insensitive to the substrate doping variations, and thus further improve the matching.

3.2.3 Multi-Mode Test Buffer Circuits This section presents the interface circuits needed in order to characterize the mobile TV LNA 65 nm test chip. Two buffers and a transformer is used to allow the RF differential signal at the LNA outputs to drive the input port of a 50 W spectrum analyzer (see Fig. 3.17). The buffers should have a very high input

78

a


60

Loop Gain (dB)

40 20 0 −20 −40 −60 100

1K

10K

100K

1M

10M

100M

Frequency (Hz)

Phase Margin (Degree)

b

200

100

0

−100

−200 100

1K

10K

100K

1M

10M

100M

Frequency (Hz) Fig. 3.15 Stability analysis of the DC stabilization loop used to bias the mobile TV LNA: (a) is the loop gain and (b) shows the phase margin results

impedance and a 100 W output impedance. The balun then transforms the output differential signal from the output of the two buffers to a single output signal. The turns’ ratio is selected to be two for this transformer to allow a 50 W impedance to be achieved at its output.


79 Tail current transistor is broken into multiple unit cells

D

D In(+) In(-)

Interdigitating differential pair

D

D

D Out

D

MOTA7 MOTA2

D

MOTA8

D

MOTA1

D

D: Dummy

Fig. 3.16 The OTA physical implementation

The interface circuits

Cc_buff Buffer

RFout Spectrum Analyzer

RFin

LNA

200Ω Ω

Cc_buff Buffer

50Ω

Cable

Fig. 3.17 Interface circuits needed to characterize the LNA 65 nm CMOS test chip

Most important among the figures of merit for the designed LNA are the NF at its maximum gain (36 dB) and the IIP3 at its minimum gain (30 dB) (see Section 3.1.2). The buffers have to be designed in a way that facilitates a high accuracy for these measurements. In other words, the performance of the buffers should not interfere with the LNA performance during the LNA testing. Accordingly, the buffer performance requirements are discussed first in the following section and then the buffer circuit design realization follows.

80


3.2.3.1 LNA Buffer Performance Requirements As previously mentioned, the buffers should facilitate accurate performance measurements of the LNA test chip while maintaining their 100 W output resistance requirement. The LNA buffers in general should provide some gain to prevent the noise floor of the spectrum analyzer from interfering with the noise floor of the LNA. In this work, a 36 dB of LNA gain results in −137 dBm/Hz noise floor level at the LNA output (to allow an accurate measurement for NF = 1 dB). The noise floor of the spectrum analyzer used for testing (Agilent E4408B) is −168 dBm/Hz, making the LNA noise floor at the input of the spectrum analyzer 31 dB larger than the spectrum analyzer noise floor itself. Accordingly, the buffers’s gain factor in our cases is relaxed. Another factor to consider is the noise figure of these buffers. Using Friis equation (see expression 1.1), one can calculate the required NF of the buffers so that their noise would not interfere with the measured NF of the LNA. The situation is helped by the 36 dB of gain of the LNA that makes the noise requirements on these buffers very relaxed (6 dB NF – relative to the 50 W source resistance). However, this huge gain makes obtaining accurate IIP3 measurements very challenging. A −13 dBm IIP3 is expected to be measured at the LNA input at its minimum gain (30 dB). Therefore, in order for the buffers’ nonlinearity not to contribute to the measured LNA linearity, the buffers IIP3 has to be >+21 dBm, which is again very challenging. 3.2.3.2 LNA Buffer Circuit Realization The circuit schematic diagram for the LNA buffer is shown in Fig. 3.18. The buffer topology is based on the shunt-series amplifier topology. The reason for selecting this topology over more conventional buffers (i.e., source follower) is the stringent linearity requirements. The buffer shown in Fig. 3.18 consists of common-source transistors M1 and M2 and is self biased through RFBbias. A coupling capacitor (Cc_buff) is used in order to facilitate the simple self biasing technique and to help prevent the buffer from clipping at the output and damaging the LNA IIP3 measurements. The value of this capacitor is chosen so that it would not affect the LNA bandwidth. R1 and R2 act as degeneration resistors for the common-source transistors in order to improve the buffer nonlinearity. The degeneration resistor can be varied by switching ON and OFF the transistor switches M3 and M4 through a single bit called “Test mode control bit”. When M3 and M4 are ON, the buffer operates in what is called high-gain mode, while when they are OFF the buffer operates in lowgain mode. In high-gain mode the buffer consumes 13 mA and is used for LNA NF measurements, while in low-gain mode it consumes 3 mA and is used to measure the LNA IIP3. In high-gain mode, the buffer has a negligible effect on the cascaded NF measured by the spectrum analyzer (0.04 dB), therefore guaranteeing accuracy in the LNA NF measurement. In low-gain mode, increasing the value of the degeneration resistor helps the buffer to achieve an IIP3 of +22 dBm. In order to preserve

3.3 Experimental Results

81 2.5 V

R2

M4

R4 M2

Cc_buff RFin

RFout

RFBbias

M1 R3

R1

M3 Test mode control bit

Fig. 3.18 LNA-buffer schematic circuit diagram

the output matching requirement while changing the buffer test mode (i.e., buffer’s gain), the feedback resistor RFBbias must vary. A digitally-controlled resistor has been implemented for that purpose. A detailed design analysis of a shunt-series amplifier can be found in reference [58].

3.3 Experimental Results 3.3.1 Test Environment Descriptions The complete schematic diagram of the LNA test chip is shown in Fig. 3.19. The LNA core, the bias generator circuits as well as the two output buffers have been implemented in one die using 65 nm CMOS technology. The fabricated die is shown in Fig. 3.20. The die occupies (472 × 345 µm) of silicon. The test chip die is wirebonded onto a circuit board as shown in Fig. 3.21. An I2C chip (inter-integrated circuit), was used to program the CMOS test chip (i.e., LNA gain control, buffer test mode). I2C is a multi-master serial computer that can allow a microcontroller to control a test chip with just two general purpose

100 µA

60K

2K

Vbias_cas_N

MB as_cas4

MB as_CS&CG4

2.5 V

41K

R

4K

MB as_CS&CG5

MB as_cas4

MB as_CS&CG2

MB as_CS&CG3

10 µA

MB as_cas3

Vbias_CG

RFin

Vbias_cas_P

Vbias_CS

60K

MB as_CS&CG6

41K

R

4K

MB as_cas5

Lbias

RF

ΟΟ

R1

M1

M6

+

5K

5K

Cc1

Cc3

Ο

-

Ο

Fig. 3.19 The complete schematic diagram of the 65 nm CMOS LNA test chip

MB as_CS&CG1

1.2 V

MB as_cas1

1.2 V

2.5 V

Ο

20K

M2

RFin

Buffer

Buffer

Off-chip

Cc_buff

Cc_buff

20K

CMOS3

20K

2.5 V

Vbias_CS_P

M3

M5

M4

Cc2 1.2 V

10 µA

RFout

MOTA2

MOTA3

Inp

MOTA7

MOTA5

MOTA4

MOTA8

MOTA6

R

Inn

VREF

20 µA

82 3 Nanometer CMOS LNAs for Mobile TV Receivers


83

345µm

Pads

RFout

LNA core

Output buffers Bias generator circuits

VDD

RFout +

472µm

-Gnd2

Gnd1

RFin

Fig. 3.20 The 65 nm DVB-H LNA test chip die photo

SMA of the RFin LNA die I2C ports

Transformer

LNA Board

1.2V

SMA of the RFout 2.5V

Gnd

Fig. 3.21 LNA die bonded to a circuit board for testing

I/O (input/output) pins and software. The Aardvark host adapter was used to interface a Windows OS via USB (Universal Serial Bus) to a downstream embedded system environment and transfer serial messages using the I2C protocol. The 1.2 V supply is used to bias the I2C chip as well as the bandgap reference generator circuit, while the 2.5 V supply is used to bias the LNA test chip (LNA core, bias

84


Windows OS

Aardvark Adapter

Power Supplies

Circuit Board

Spectrum Analyzer

Function Generators

Network Analyzer

Fig. 3.22 Test setup in the laboratory

circuits, and buffers). A balun transformer, B4F type, provided by TOKO Inc. [109], was selected to drive the input port of the measurement equipment since it can achieve a very low insertion loss across the UHF band. The test setup used to characterize the LNA circuit board is shown in Fig. 3.22.

3.3.2 Measurement Results Several measurements were conducted to verify the LNA’s performance in terms of the DVB-H mobile TV standard requirements (Table 3.3). The HP 8753D network analyzer was used for S-parameter measurements. These measurements verify the LNA input matching (S11), the output matching (S22) and the reverse isolation (S12). To ensure the accuracy of these measurements the board traces must be taken into account while calibrating the network analyzer. A special board that does not contain the test chip has been built especially for that purpose. This board with the HP 8753D calibration kit was used to calibrate the network analyzer, thus, guaranteeing that the S11, S22, and S12 measurements accurately represent the LNA’s performance. An S11 < −18 dB was measured at the input of the LNA across the UHF band as shown in Fig. 3.23. In this measurement, the OTA bias was adjusted to make the LNA operate at the maximum gain mode. The same test was then repeated but by


85

40 S11 (dB) 20

0

–20

–40

150MHz

900MHz

Fig. 3.23 Measured S11 of the LNA at maximum gain mode of operation 40 S11 (dB) 20

0

–20

–40

150MHz

900MHz

Fig. 3.24 Measured S11 of the LNA at the first gain step

varying the OTA bias to change the LNA gain. Values of S11 < −12 dB and S11 < −8 dB were measured for the first and second gain steps of the LNA, respectively across the UHF band. These measurements are shown in Figs. 3.24 and 3.25. As expected, there is degradation in the input matching of the LNA while varying the OTA

86

3 Nanometer CMOS LNAs for Mobile TV Receivers 40 S11 (dB) 20

0

–20

–40

150MHz

900MHz

Fig. 3.25 Measured S11 of the LNA at the second gain step

bias due to changing the loop gain around the CG transistor (see Section 3.2.1.3). However, S11 values still satisfy the input impedance required to terminate the transmission line that will deliver the DVB-H signal from the antenna to the LNA. One important property that should be achieved in the DVB-H LNA is the high reverse isolation (see Chapter 4). A value of S12 < −40 dB was measured across the UHF band as shown in Fig. 3.26. The very low measured S12 values show the effectiveness of using the cascode transistors to improve the isolation of the output and input ports. Having a separate downbond for the CS transistor M2 also helped in achieving that value (see Fig. 3.20). To verify the buffer output matching, S22 < −11 dB was measured across the UHF band as shown in Fig. 3.27. The Agilent E4408B spectrum analyzer was used for the gain and noise figure measurements. The loss of the SMA connectors and the coax cable ranging from 0.7 to 1.2 dB was removed from the measurement as these connectors and cables will not be present when the LNA is integrated with the mobile TV antenna. The LNA gain is found by measuring the LNA output spectrum shown in Fig. 3.28. In this figure, the buffer gain as well as the balun transformer insertion loss were de-embedded. The measured maximum LNA gain is 36 dB while two ~3 dB gain steps were measured when varying the OTA bias. Degradation in LNA gain was noted at high frequencies of operation, especially at its maximum gain mode. This is attributed to the underestimation of the parasitic capacitance at the LNA output. Such degradation will not exist when the LNA is integrated with the RF passive mixer as it has very low input parasitic capacitances. As shown in Fig. 3.28, the observed degradation is less at the LNA minimum gain mode due to a minimum value of the LNA output resistance with respect to the output resistance value at maximum gain mode.


87

40 S12 (dB) 20

0

–20

–40

150MHz

900MHz

Fig. 3.26 Measured S12 of the LNA at maximum gain mode of operation 40 S22 (dB) 20

0

–20

–40

150MHz

900MHz

Fig. 3.27 Measured S22 of the LNA test chip

Using the same test setup, the noise floor at the output of the LNA test chip was measured with the noise figure mode available in the Agilent E4408B spectrum analyzer. The buffer was set to operate in high-gain test mode. The measured results of the NF are shown in Fig. 3.29. An average of 1.65 dB NF at LNA maximum gain mode was measured across the UHF band, while an average of 2.4 and 3.7 dB NF were measured at the first and second gain steps, respectively. The NF degradation

88

3 Nanometer CMOS LNAs for Mobile TV Receivers −39.00 Output Signal (dBm)

36 dB of gain

−42.00 Second gain step

3 dB gain step

−45.00

First gain step Max. gain

−48.00 −51.00

250

550

850

Frequency (MHz)

Fig. 3.28 The output LNA spectrum when the input signal is equal to −78 dBm. The frequency is varied from 250 to 850 MHz. Three different gain modes have been considered, the maximum gain, the first gain step, and the second gain step. The LNA gain was varied by changing the DC bias Vref of the OTA bias circuit

6.00

4.00 NF (dB)

NF at max. gain NF at 1st gain step NF at 2nd gain step

2.00

0.00

300

575

850

Frequency (MHz)

Fig. 3.29 Measured LNA NF at maximum gain as well as at the first and second gain steps. The frequency is varied from 300 to 850 MHz

at the first and second gain steps is not surprising since the LNA noise performance is optimized only at maximum gain mode of operation. Therefore, decreasing the LNA gain will automatically deviate the LNA operation from the noise-cancelling condition (see Chapter 2, Eq. 2.31). However, the LNA NF at minimum gain still meets the requirement of the DVB-H standard (see Table 3.3). To verify the linearity performance, a two-tone IIP3 measurement was performed on the LNA and the results are shown in Fig. 3.30. The buffer was set to the


89

Output Voltage (dBm)

−19.3dBm

IM3 =44.8 dB

IM3

Center 515.00 MHz

IM3

Span 50 MHz

Fig. 3.30 Linearity measurement of the LNA at the minimum gain setting

Table 3.4 DVB-H LNA measurements summary Technology 65 nm CMOS Power supply 2.5 V Frequency range UHF: 470 –862 MHz Current consumption

Nanometer CMOS RFICs for Mobile TV Applications (Analog Circuits and Signal Processing)

Substrate Noise Coupling in RFICs (Analog Circuits and Signal Processing)

Full-Chip Nanometer Routing Techniques (Analog Circuits and Signal Processing)

Low-Power High-Speed ADCs for Nanometer CMOS Integration (Analog Circuits and Signal Processing)

CMOS Processors and Memories (Analog Circuits and Signal Processing)

Analog MOS Integrated Circuits for Signal Processing

EMC of Analog Integrated Circuits (Analog Circuits and Signal Processing)

CMOS Capacitive Sensors for Lab-on-Chip Applications: A Multidisciplinary Approach (Analog Circuits and Signal Processing)

CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications (Analog Circuits and Signal Processing)

CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications (Analog Circuits and Signal Processing)

IQ Calibration Techniques for CMOS Radio Tranceivers (Analog Circuits and Signal Processing)

IQ Calibration techniques for CMOS Radio Transceivers (Analog Circuits and Signal Processing)

Smart AD and DA Conversion (Analog Circuits and Signal Processing)

RF Power Amplifiers for Mobile Communications (Analog Circuits and Signal Processing)

Linear CMOS RF Power Amplifiers for Wireless Applications: Efficiency Enhancement and Frequency-Tunable Capability (Analog Circuits and Signal Processing)

Broadband Opto-Electrical Receivers in Standard CMOS (Analog Circuits and Signal Processing)

Design of High Voltage xDSL Line Drivers in Standard CMOS (Analog Circuits and Signal Processing)

Precision Temperature Sensors in CMOS Technology (Analog Circuits and Signal Processing)

Precision Temperature Sensors in CMOS Technology (Analog Circuits and Signal Processing)

Broadband Opto-Electrical Receivers in Standard CMOS (Analog Circuits and Signal Processing)

Precision Temperature Sensors in CMOS Technology (Analog Circuits and Signal Processing)

Broadband Opto-Electrical Receivers in Standard CMOS (Analog Circuits and Signal Processing)

CMOS High Efficiency On-chip Power Management (Analog Circuits and Signal Processing)

Signal Processing for Active Control (Signal Processing and its Applications)

Adaptive RF Front-Ends for Hand-held Applications (Analog Circuits and Signal Processing)

Adaptive Low-Power Circuits for Wireless Communications (Analog Circuits and Signal Processing)

Adaptive Low-Power Circuits for Wireless Communications (Analog Circuits and Signal Processing)

Design of Analog CMOS Integrated Circuits

Analog-Baseband Architectures and Circuits for Multistandard and Low-Voltage Wireless Transceivers (Analog Circuits and Signal Processing)

Design of Analog CMOS Integrated Circuits (Solutions)

Design of Analog CMOS Integrated Circuits

Nanometer CMOS RFICs for Mobile TV Applications (Analog Circuits and Signal Processing)

Substrate Noise Coupling in RFICs (Analog Circuits and Signal Processing)

Full-Chip Nanometer Routing Techniques (Analog Circuits and Signal Processing)

Low-Power High-Speed ADCs for Nanometer CMOS Integration (Analog Circuits and Signal Processing)

CMOS Processors and Memories (Analog Circuits and Signal Processing)

Analog MOS Integrated Circuits for Signal Processing

EMC of Analog Integrated Circuits (Analog Circuits and Signal Processing)

CMOS Capacitive Sensors for Lab-on-Chip Applications: A Multidisciplinary Approach (Analog Circuits and Signal Processing)

CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications (Analog Circuits and Signal Processing)

CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications (Analog Circuits and Signal Processing)

IQ Calibration Techniques for CMOS Radio Tranceivers (Analog Circuits and Signal Processing)

IQ Calibration techniques for CMOS Radio Transceivers (Analog Circuits and Signal Processing)

Smart AD and DA Conversion (Analog Circuits and Signal Processing)

RF Power Amplifiers for Mobile Communications (Analog Circuits and Signal Processing)

Linear CMOS RF Power Amplifiers for Wireless Applications: Efficiency Enhancement and Frequency-Tunable Capability (Analog Circuits and Signal Processing)

Broadband Opto-Electrical Receivers in Standard CMOS (Analog Circuits and Signal Processing)

Design of High Voltage xDSL Line Drivers in Standard CMOS (Analog Circuits and Signal Processing)

Precision Temperature Sensors in CMOS Technology (Analog Circuits and Signal Processing)

Precision Temperature Sensors in CMOS Technology (Analog Circuits and Signal Processing)

Broadband Opto-Electrical Receivers in Standard CMOS (Analog Circuits and Signal Processing)

Precision Temperature Sensors in CMOS Technology (Analog Circuits and Signal Processing)

Broadband Opto-Electrical Receivers in Standard CMOS (Analog Circuits and Signal Processing)

CMOS High Efficiency On-chip Power Management (Analog Circuits and Signal Processing)

Signal Processing for Active Control (Signal Processing and its Applications)

Adaptive RF Front-Ends for Hand-held Applications (Analog Circuits and Signal Processing)

Adaptive Low-Power Circuits for Wireless Communications (Analog Circuits and Signal Processing)

Adaptive Low-Power Circuits for Wireless Communications (Analog Circuits and Signal Processing)

Design of Analog CMOS Integrated Circuits

Analog-Baseband Architectures and Circuits for Multistandard and Low-Voltage Wireless Transceivers (Analog Circuits and Signal Processing)

Design of Analog CMOS Integrated Circuits (Solutions)

Design of Analog CMOS Integrated Circuits

Recommend Documents