a Converters

WIDE-BANDWIDTH HIGH DYNAMIC RANGE D/A CONVERTERS

THE INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE ANALOG CIRCUITS AND SIGNAL PROCESSING Consulting Editor: Mohammed Ismail. Ohio State University Related Titles: METHODOLOGY FOR THE DIGITAL CALIBRATION OF ANALOG CIRCUITS AND SYSTEMS: WITH CASE STUDIES Pastre, Marc, Kayal, Maher Vol. 870, ISBN: 1-4020-4252-3 HIGH-SPEED PHOTODIODES IN STANDARD CMOS TECHNOLOGY Radovanovic, Sasa, Annema, Anne-Johan, Nauta, Bram Vol. 869, ISBN: 0-387-28591-1 LOW-POWER LOW-VOLTAGE SIGMA-DELTA MODULATORS IN NANOMETER CMOS Yao, Libin, Steyaert, Michiel, Sansen, Willy Vol. 868, ISBN: 1-4020-4139-X DESIGN OF VERY HIGH-FREQUENCY MULTIRATE SWITCHED-CAPACITOR CIRCUITS U, Seng Pan, Martins, Rui Paulo, Epifânio da Franca, José Vol. 867, ISBN: 0-387-26121-4 DYNAMIC CHARACTERISATION OF ANALOGUE-TO-DIGITAL CONVERTERS Dallet, Dominique; Machado da Silva, José (Eds.) Vol. 860, ISBN: 0-387-25902-3 ANALOG DESIGN ESSENTIALS Sansen, Willy Vol. 859, ISBN: 0-387-25746-2 DESIGN OF WIRELESS AUTONOMOUS DATALOGGER IC'S Claes and Sansen Vol. 854, ISBN: 1-4020-3208-0 MATCHING PROPERTIES OF DEEP SUB-MICRON MOS TRANSISTORS Croon, Sansen, Maes Vol. 851, ISBN: 0-387-24314-3 LNA-ESD CO-DESIGN FOR FULLY INTEGRATED CMOS WIRELESS RECEIVERS Leroux and Steyaert Vol. 843, ISBN: 1-4020-3190-4 SYSTEMATIC MODELING AND ANALYSIS OF TELECOM FRONTENDS AND THEIR BUILDING BLOCKS Vanassche, Gielen, Sansen Vol. 842, ISBN: 1-4020-3173-4 LOW-POWER DEEP SUB-MICRON CMOS LOGIC SUB-THRESHOLD CURRENT REDUCTION van der Meer, van Staveren, van Roermund Vol. 841, ISBN: 1-4020-2848-2 WIDEBAND LOW NOISE AMPLIFIERS EXPLOITING THERMAL NOISE CANCELLATION Bruccoleri, Klumperink, Nauta Vol. 840, ISBN: 1-4020-3187-4 CMOS PLL SYNTHESIZERS: ANALYSIS AND DESIGN Shu, Keliu, Sánchez-Sinencio, Edgar Vol. 783, ISBN: 0-387-23668-6 SYSTEMATIC DESIGN OF SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTERS Bajdechi and Huijsing Vol. 768, ISBN: 1-4020-7945-1 OPERATIONAL AMPLIFIER SPEED AND ACCURACY IMPROVEMENT Ivanov and Filanovsky Vol. 763, ISBN: 1-4020-7772-6 STATIC AND DYNAMIC PERFORMANCE LIMITATIONS FOR HIGH SPEED D/A CONVERTERS van den Bosch, Steyaert and Sansen Vol. 761, ISBN: 1-4020-7761-0 DESIGN AND ANALYSIS OF HIGH EFFICIENCY LINE DRIVERS FOR Xdsl Piessens and Steyaert Vol. 759, ISBN: 1-4020-7727-0 LOW POWER ANALOG CMOS FOR CARDIAC PACEMAKERS Silveira and Flandre Vol. 758, ISBN: 1-4020-7719-X MIXED-SIGNAL LAYOUT GENERATION CONCEPTS Lin, van Roermund, Leenaerts Vol. 751, ISBN: 1-4020-7598-7

WIDE-BANDWIDTH HIGH DYNAMIC RANGE D/A CONVERTERS by

Konstantinos Doris Philips Research Laboratories, Eindhoven, The Netherlands

Arthur van Roermund Eindhoven University of Technology, Eindhoven, The Netherlands and

Domine Leenaerts Philips Research Laboratories, Eindhoven, The Netherlands

A C.I.P. Catalogue record for this book is available from the Library of Congress.

ISBN-10 ISBN-13 ISBN-10 ISBN-13

0-387-30415-0 (HB) 978-0-387-30415-1 (HB) 0-387-30416-9 (e-book) 978-0-387-30416-8 (e-book)

Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands. www.springer.com

Printed on acid-free paper

All Rights Reserved © 2006 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Printed in the Netherlands.

Contents

Glossary

ix

Abbreviations

xiii

Preface

xv

1 Digital to Analog conversion concepts 1.1 Functional aspects . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 Definition of the D/A function . . . . . . . . . . . . 1.1.2 Functional specifications . . . . . . . . . . . . . . . 1.2 Algorithmic aspects . . . . . . . . . . . . . . . . . . . . . . 1.3 Signal processing aspects . . . . . . . . . . . . . . . . . . . 1.3.1 Waveforms and Line coding . . . . . . . . . . . . . 1.3.2 Signal Modulation concepts . . . . . . . . . . . . . 1.4 Circuit aspects . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.1 Architecture terminology . . . . . . . . . . . . . . . 1.4.2 Resistive voltage division architectures . . . . . . . 1.4.3 Capacitive voltage and charge division architectures 1.4.4 Current division based architectures . . . . . . . . . 1.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . .

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1 1 1 3 8 11 11 13 13 14 15 16 18 18

2 Framework for Analysis and Synthesis of DACs 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . 2.2 Framework description . . . . . . . . . . . . . . . 2.2.1 Analysis . . . . . . . . . . . . . . . . . . 2.2.2 Synthesis . . . . . . . . . . . . . . . . . .

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Contents

vi

3 Current Steering DACs 3.1 Basic circuit . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 Partitioning and segmentation . . . . . . . . . 3.1.2 Current switching network and current sources 3.1.3 Clock-data synchronization circuit . . . . . . . 3.1.4 Auxiliary circuits . . . . . . . . . . . . . . . . 3.2 Implementations and technology impact . . . . . . . .

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4 Dynamic limitations of Current Steering DACs 4.1 State of the art in dynamic linearity . . . . . . . . 4.2 Dynamic limitations of current steering DACs . . 4.2.1 Matching and relative amplitude precision 4.2.2 Matching and relative timing precision . 4.3 Conclusions . . . . . . . . . . . . . . . . . . . .

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35 35 40 41 42 44

5 Current Steering DAC circuit error analysis 5.1 Amplitude domain errors . . . . . . . . . . . . . . . . . . . 5.1.1 Relative amplitude inaccuracies . . . . . . . . . . . 5.1.2 Output resistance modulation . . . . . . . . . . . . 5.2 Time domain errors . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Nonlinear settling and output impedance modulation 5.2.2 Asymmetrical switching . . . . . . . . . . . . . . . 5.2.3 Modulation of switching behavior . . . . . . . . . . 5.2.4 Charge feedthrough and injection . . . . . . . . . . 5.2.5 Relative timing inaccuracies . . . . . . . . . . . . . 5.2.6 Power supply bounce and substrate noise . . . . . . 5.2.7 Clock (timing) jitter . . . . . . . . . . . . . . . . . 5.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . .

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45 45 45 47 48 48 51 53 54 56 59 63 66

6 High-level modeling of Current Steering DACs 6.1 System modeling . . . . . . . . . . . . . . . . . 6.1.1 System layers . . . . . . . . . . . . . . . 6.1.2 System excitations and responses . . . . 6.1.3 System parameters . . . . . . . . . . . . 6.1.4 Subsystem interaction . . . . . . . . . . 6.1.5 System modulation . . . . . . . . . . . . 6.2 Error properties and classification . . . . . . . . 6.2.1 Error properties . . . . . . . . . . . . . . 6.2.2 Error classification . . . . . . . . . . . . 6.3 Functional error generation mechanisms . . . . . 6.3.1 Definitions . . . . . . . . . . . . . . . . 6.3.2 Algorithmic modeling . . . . . . . . . . 6.3.3 Functional modeling . . . . . . . . . . . 6.3.4 Examples . . . . . . . . . . . . . . . . .

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67 67 68 69 69 71 72 72 73 77 79 79 80 82 85

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Contents

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Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

88

7 Functional modeling of timing errors 7.1 Non-uniform timing . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 The Equivalent Timing error of a transition . . . . . . 7.1.2 Non-uniform timing in the process of signal sampling 7.1.3 Non-uniform timing in the process of signal creation . 7.2 Stochastic non-uniform timing analysis . . . . . . . . . . . . 7.2.1 Correlated non-uniform timing . . . . . . . . . . . . . 7.2.2 White non-uniform timing . . . . . . . . . . . . . . . 7.2.3 RZ and NRZ waveforms . . . . . . . . . . . . . . . . 7.3 Deterministic non-uniform timing . . . . . . . . . . . . . . . 7.3.1 Non-linear mapping of time domains . . . . . . . . . 7.3.2 Non-uniform timing in signal creation . . . . . . . . . 7.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . .

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89 89 89 91 92 95 95 97 100 103 103 105 106

8 Functional analysis of local timing errors 8.1 Local timing error analysis . . . . . . . . . 8.1.1 Equivalent timing error calculation . 8.1.2 Signal error calculation . . . . . . . 8.2 High level architectural parameter tradeoffs: 8.3 Conclusions . . . . . . . . . . . . . . . . .

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109 109 109 113 116 118

9 Circuit analysis of local timing errors 9.1 Circuit analysis with linear models . . . . . . . . . . . . . . . . . 9.1.1 Circuit behavioral-level analysis of timing errors in a chain 9.1.2 Transistor level analysis . . . . . . . . . . . . . . . . . . 9.2 Local timing error tradeoffs . . . . . . . . . . . . . . . . . . . . . 9.2.1 Switch timing errors . . . . . . . . . . . . . . . . . . . . 9.2.2 Latch timing errors . . . . . . . . . . . . . . . . . . . . . 9.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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119 119 120 126 135 135 137 137

10 Synthesis concepts for CS DACs 10.1 Information management in the CS DAC . . . . . . . . . . . 10.1.1 The basic current steering DAC hardware . . . . . . 10.1.2 Information sources . . . . . . . . . . . . . . . . . 10.1.3 Optional hardware: detection and control operations 10.1.4 Algorithms . . . . . . . . . . . . . . . . . . . . . . 10.1.5 Space/Time error mapping and processing . . . . . . 10.2 Synthesis Policy . . . . . . . . . . . . . . . . . . . . . . . 10.3 A-posteriori error correction methods . . . . . . . . . . . . 10.3.1 Calibration in amplitude and time domain . . . . . . 10.3.2 Generalized mapping . . . . . . . . . . . . . . . . . 10.3.3 Applications of generalized mapping . . . . . . . .

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Contents

10.3.4 Realization issues of the generalized mapping concept . . . . . . 156 10.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11 Design of a 12 bit 500 Msample/s DAC 11.1 Design approach . . . . . . . . . . . . . . . . 11.2 Architecture . . . . . . . . . . . . . . . . . . . 11.2.1 Signaling and circuit logic . . . . . . . 11.2.2 Power supply and biasing . . . . . . . 11.2.3 Thermometer/binary bits partitioning . 11.3 Switched-Current cell . . . . . . . . . . . . . . 11.3.1 Current source . . . . . . . . . . . . . 11.3.2 Switch . . . . . . . . . . . . . . . . . 11.4 Decoder, data synchronization and conditioning 11.4.1 Binary-to-Thermometer decoder . . . . 11.4.2 Delay equalization . . . . . . . . . . . 11.4.3 Master-slave latches and drivers . . . . 11.4.4 Clock buffer . . . . . . . . . . . . . . 11.5 Layout . . . . . . . . . . . . . . . . . . . . . . 11.6 Experimental results . . . . . . . . . . . . . . 11.6.1 DC linearity measurements . . . . . . . 11.6.2 AC linearity measurements . . . . . . . 11.7 Conclusions . . . . . . . . . . . . . . . . . . . References

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159 159 160 160 161 162 164 164 170 174 174 175 175 177 178 180 180 181 184 185

A Output spectrum for timing errors 199 A.1 Power spectrum of y(t) for random timing errors . . . . . . . . . . . . . 199 A.2 Spectrum of y(t) for deterministic timing errors . . . . . . . . . . . . . . 202 B Literature data

203

Glossary

Symbol

Description

Aβ AD AVth B1 B2 cn−m (tn ,tm ) Ck−l ( fk , fl ) Cq ( f , − f ) |C( f )|2 Cu

current factor mismatch process parameter gain of a driver threshold mismatch process parameter lower frequency limit of a bandpass signal higher frequency limit of a bandpass signal joint probability density function of timing errors characteristic function for timing errors µm characteristic function for correlated stationary timing errors characteristics function for uncorrelated stationary timing errors capacitance difference between switched on and off phases of a switched current source output capacitance of a switched-on current source output capacitance of a switched-off current source total clock node capacitance output capacitance of the clock driver self output load capacitance of the driver MOS gate drain capacitance gate capacitance of the current switches interconnect capacitance between driver and current switches clock interconnect network capacitance MOS overlap capacitance per unit width oxide capacitance per unit area delta pulse unit error of the k-th current source timing error created by a circuit (accompanied by a subscript) thermometer bit i as a function of discrete time index m DAC binary input word at time index m

Con Co f f CC CCD CD Cgd CG Cint CInt Cov Cox δ (t) ∆Ik ∆t di (m) D(m)

Unit

mV µ m Hz Hz

F F F F F F F F F F F m−1 F m−2 A sec

x

Glossary

E{} f f1 f2 fN h(t) |H( f )|2 I Inorm (w) Iu IFS J p (x) K λ L m µi µm N NB NT pr (t) p(t) P PB Pk Pmax PN |Pr ( f )|2 PS rµ (m, q) Ry (t,t + τ ) Rˆ y (τ ) Rz (m, m + q) Rˆ z (m, m + q)
Ry (τ ) E{Rˆ y (τ )} Sy ( f ) Sˆy ( f )
Sy ( f ) E{Sˆy ( f )} Rz (0) RL σ s(t)

expectation with respect to the probability density function (PDF) of the function under consideration frequency lower band frequency limit higher band frequency limit Nyquist frequency arbitrary interpolation pulse energy spectral density of an arbitrary pulse h(t) reference (LSB) current of the DAC normalized current amplitude as a function of w current generated by a switched current cell full scale current of the DAC Bessel function of the first kind number of bands frequency normalized over fs MOS transistor length discrete time index local timing error of each circuit element i timing errors as a function of the time index m number of bits bits remaining in binary code bits decoded in thermometer code rectangular pulse sinc interpolation pulse total signal power including signal and noise power of a signal in a band power of the k-th harmonic of a signal power of the largest spurious component in the band of interest noise power energy spectral density of a rectangular pulse pr (t) signal power correlation function of the timing error series {µm } probabilistic autocorrelation of the CT process y(t) empirical autocorrelation of the CT process y(t) probabilistic autocorrelation of the DT process z(m) empirical autocorrelation of the DT process z(m) averaged probabilistic autocorrelation mean of the empirical autocorrelation probabilistic power spectrum of the CT process y(t) empirical power spectrum of the CT process y(t) averaged probabilistic power spectrum of the CT process y(t) mean of the empirical power spectrum of the CT process y(t) power of z(m) output DAC resistive load spread of timing errors output signal of the DAC

Hz Hz Hz Hz Hz−2 A A A A

m sec sec

W W W W W Hz−2 W sec2 V 2 or A2 V 2 or A2 V 2 or A2 V 2 or A2 V 2 or A2 V 2 or A2 W Hz−1 W Hz−1 W Hz−1 W Hz−1 W Ω sec V or A

Glossary

S0 SzDT (λ ) Sz ( f ) Sz (t) τ τ (w) τu t tox T0 TE (w1 , w2 ) tm Tr(m − 1, m) Ts u(t, ˆ w) u(t) |U( f )|2 v(t, ˆ w) Vdd VD VL Vre f Vss Vswi Vth w(m) W |Y ( f )| z(m) Zu ( f )

xi

amplitude of the power spectral density W power spectral density of z(m) W normalized Hz power spectral density of z(t) W sec first derivative of z(t)(instantaneous slope) V sec−1 time constant (accompanied with subscripts) sec DAC output node time constant as a function of w sec DAC output node time constant increment per each step of w sec time variable sec oxide thickness m width of a return to zero pulse sec equivalent timing error for the transistion w1 → w2 sec non-uniform timing moments sec normalized transition from sample to sample V or A Sampling period sec normalized pulse for local timing errors µi unit step energy spectral density of a step pulse u(t) Hz−2 general description of the normalized pulse V or A positive power supply V voltage swing of a driver V voltage swing of a latch V reference voltage V negative power supply V voltage swing Threshold voltage V integer value of D(m) MOS transistor width m magnitude spectrum of y(t) V or A generic discrete time signal V or A output impedance of a switched current cell vs. frequency Ω

Abbreviations

AC ADC AM BER BJT CAD CML CMOS CS CT DAC DC DEM DNL DT DT/CT ECL ESD FM HD2,HD3 HW INL LSB MSB NRZ PPM PSD PWL PWM PDM RZ

Alternating Current Analog-to-Digital Converter Amplitude Modulation Bit Error Rate Bipolar Junction Transinstor Computer Aided Design Current Mode Logic Complementary Metal Oxide Semiconductor Current Steering Continous Time Digital-to-Analog Converter Direct Current Dynamic Element Matching Differential Non Linearity Discrete Time Discrete Time to Continous Time conversion Emitter Coupled Logic Energy Spectral Density Frequency Modulation Second and third order harmonic distortion Hardware Integral Non Linearity Least Significant Bit Most Singificant Bit Non Return to Zero Pulse Position Modulation Power Spectral Density Piece-wise Linear Pulse Width Modulation Pulse Duration Modulation Return to Zero

xiv

SC SI SDR SFDR SNDR SNR T/H THD WSS

Abbre viations

Switched Capacitor Switched Current Signal to Distortion Ratio Spurious Free Dynamic Range Signal to Noise and Distortio Ratio Signal to Noise Ratio Track and Hold Total Harmonic Distortion Wide Sense Stationary

Preface

H

IGH-SPEED Digital to Analog (D/A) converters are essential components in digital communication systems providing the necessary conversion of signals encoding information in bits to signals encoding information in their amplitude vs. time domain characteristics. In general, they are parts of a larger system, the interface, which consists of several signal conditioning circuits. Dependent on where the converter is located within the chain of circuits in the interface, signal processing operations are partitioned in those realized with digital techniques, and those with analog. The rapid evolution of CMOS technology has established implicit and explicite trends related to the interface, and in particular to the D/A converter. The implicit relationship comes via the growth of digital systems. First, it is a global trend with respect to all interface circuits that increasing operating frequencies of digital systems place a similar demand for the interface circuits. The second trend takes place locally within the interface. Initially, the D/A converter was placed at the beginning of the interface chain, and all signal conditioning was implemented in the analog domain after the D/A conversion. The increasing flexibility and robustness of digital signal processing shifted the D/A converter closer to the end point of the chain where the demands for high quality high frequency operation are very high. Third, there is a gradual change in the signal properties and specifications, which reflect to the rapid widening of application range, to user requirements, and of course to environmental constraints relevant to the application. Explicit trends are established by the direct impact of physical constrains of the technology on converters. One of them concerns how information is distributed in the amplitude and time domains. Modern CMOS technologies allow less and less room to use the amplitude domain due to decreasing power supply levels but not decreasing noise and interference levels. Instead, they offer plenty of room in the time domain. Wideband high dynamic range D/A converters are carriers of these trends and enablers of modern multi-carrier communication applications. These converters are required to process multiple signals over large frequency ranges of hundreds of mega hertz with high

xvi

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linearity and low noise levels. To further simplify the subsequent lowpass filtering and to allow efficient implementation of pre-distortion techniques for high data rate communications sampling rates multiple times higher than the actual transmitted signal bandwidth are required. However, the demands placed by these trends can not be straightforwardly mapped to physical realization despite the potential offerings of modern technologies. As a result the D/A converter becomes one of the bottlenecks in system performance. The Current Steering Digital to Analog Converter (CS DAC) offers the possibility for such wideband high dynamic range signal conversion. However, its potential to achieve high speed is limited by the fact that it exhibits strong nonlinear behavior at high frequencies, which is unwanted. This nonlinear behavior, especially at high frequencies, is dominated by mechanisms that can not be described as amplitude domain transfer functions between input and output signals, like for example the case of the nonlinear behavior of an operational amplifier. This nonlinear behavior is neither easy to understood, nor to cope with. It stems mainly from the way circuit imperfections affect the inherently nonlinear transient behavior of the signals the D/A converter generates. The appearance of such behavior reveals that there is limited knowledge about the CS DAC nonlinear behavior at high frequencies. As a result, there is a corresponding difficulty to bring a relationship between signals, user information, application aspects, internal aspects of the converter, environmental aspects, etc. in a generic form that would allow maximum exploitation of what modern technologies offer. The lack of knowledge brings up an ambiguity element in the CS DAC design phase that impedes performance progress. This book provides a structured and comprehensive description of the nonlinear behavior of the CS DAC and of ways to deal with it. In order to achieve this an analysis and synthesis framework of concepts will be built with a generic scope beyond this particular architecture, and then the proposed concepts will be applied in practice with an IC implementation. The book consists of an introductory part about DACs (Chapters 1-2), a modeling and analysis part for Current Steering Digital to Analog Converters (chapters 3-9) and a synthesis part (Chapters 10 and 11). Chapters 1 and 2 deal with the general aspects of D/A converters, and those of the framework of analysis and synthesis that will be developed. Chapters 3-6 concern CS DACs. In Chapter 3 architectural and circuit aspects of CS DACs are discussed. In Chapter 4, the current state of the art is examined which helps to formulate the characteristics of knowledge that needs to be developed about the behavior of this circuit. In Chapter 5 circuit error mechanisms due to hardware imperfections are analyzed, emphasizing those that limit high frequency performance. This chapter reviews and extends further existing knowledge about these error mechanisms. Chapter 6 deals with high level DAC modeling. The signal errors are mapped to principle causes within the physical hierarchy of the DAC and they are categorized to classes according to their principle characteristics with amplitude, time, spatial domains, and other properties. Chapters 7-9 deal specifically with the class of timing errors which is the most significant one for high frequencies. Chapter 7 addresses functional modeling issues of timing errors, and shows that they can be described with Pulse Position and Pulse Width Modulation in the DAC signal creation process. This unifies all the errors of this class under one

Pref ace

xvii

common modulation mechanism, each error being a specific subcase of this mechanism that is determined by its other error properties. In chapter 8 the developed models are applied to spatially local timing errors (timing skew between individual current transients) which is one of the most important but least understood high frequency error mechanisms. In chapter 9 these errors are analyzed in circuit details, moving from the functional aspects to circuit and transistor level ones. All analysis results are then combined to reveal interesting design tradeoffs. Chapters 10 and 11 deal with DAC synthesis. A generic view of DAC synthesis is presented in chapter 10. The information available about a CS DAC is classified according to its type (e.g. information about signals, errors, application, user, etc.) and properties. Of particular importance is the definition of a-priori information, which is information about the DAC known at the design phase, and a-posteriori information obtained only after chip implementation. It is explained that current DACs use only a-priori information to deal with the dominant high-frequency error mechanisms. The use of a-posteriori information can provide a next step in DAC performance and efficiency. Two methods that can deal with local timing errors are discussed. Chapter 11 presents the design of a concept driven 12 bit 500 Msample/s DAC IC in a CMOS 0.18 µ m process that achieves exceptionally high performance at low power consumption and occupying small area. The DAC is optimized using only a-priori information about error generation mechanisms to investigate the limits of this approach.

1

Digital to Analog conversion concepts

F

UNCTIONAL , algorithmic, signal processing, and circuit aspects of a Digital to Analog (D/A) converter will be briefly reviewed in this chapter. Definitions with respect to these aspects and D/A converters architectures will be given.

1.1 Functional aspects 1.1.1

Definition of the D/A function

The term Digital to Analog (D/A) conversion describes the conversion of a signal that represents data in Digital format to a signal that represents data in Analog format. This description excludes the electrical nature of conversion, and refers basically to how information is represented, i.e. in digital or in analog form. When one speaks of an electronic Digital to Analog converter there are additional conversions that take place. An electronic linear D/A converter is an electronic circuit that accepts at its input a set of electrical signals, that represent a digital numeric code, and yields at its output an analog electrical signal, i.e. in proportion to a reference electrical quantity as the input numeric code is to the full range of possible codes. A full list of the electronic characteristics that the ideal electronic D/A converter must satisfy are described in [1]. It is indeed tempting to reduce the definition of the D/A converter to a statement similar to “the conversion of an input code word to an output electric quantity”, neglecting completely the electrical waveform characteristics of the input signal. Because information in the input electrical signal is defined very accurately with the use of only two digits, the input electrical signals can be abstracted to generic signals described by a sequence of values; it becomes identical to speak of abstract signals with zero’s and one’s or of continuous time 1

2

Chapter 1 Digital to Analog conversion concepts

(CT) electrical signals that use specific voltage levels to represent logic levels. Since the electrical nature of the input signal can be neglected the only relevant “time” issue is the sequence of the input samples. On the basis of this reduction an N bit linear D/A converter is the electronic system that represents an N bit binary word D = D1 D2 ...DN at its input with an electrical quantity at its output (usually voltage or current) that has amplitude or time domain characteristics that are modulated in proportion to the value of the code word and to a reference quantity.

Code conversion

Electrical signal creation

Waveform shaping

amplitude and time references

Ts

C D(m)

binary to integer

w(m)

DT CT

Pulse h(t)

s(t)

Figure 1.1 D/A conversion in the amplitude domain.

A functional diagram of the D/A conversion when the information is placed in the amplitude domain is given in fig. 1.1. The generic input signal is represented by the sequence of code words D(m). In the first stage of the diagram, the words D(m) are converted into the integer values w(m). The second stage represents the creation of the electrical signal that possesses physical dimensions. This is realized using amplitude and time references. A multiplication assigns the amplitude dimensions to the abstract signal. The Discrete-to-Continuous time conversion (DT/CT) assigns the time domain properties to the signal. The last sub-function of the D/A function is the shaping (filtering) of the generated electrical signal to obtain the predetermined shape (e.g. interpolation). The result of the three sub-functions is an electrical signal consisting of pulses that are amplitude modulated by the integer equivalent w(m) of the binary words D(m). Where exactly the time domain conversion takes place does not imply any physical necessity, rather it represents the subjectiveness of the model. Physically, time domain exists in D(m) and can not be separated from it. From a modeling perspective, such a distinction defines at which point time domain issues are important at the realized hardware and can not be neglected any more. For example, if a Track and Hold (T/H) circuit is used at the output to re-sample the signal and clean it from artifacts that appear at the switching transients, the time domain assignment takes place there. It should be mentioned that the term DT is misleading, because it implies that time is involved in the signal D(m); this is not true since the only relevant issue in D(m) is the sequence (the order) of the values. The D/A conversion function with information encapsulated in the time domain of an electrical signal is given in fig. 1.2 and can be explained in a similar manner. In summary, the function of an ideal electronic D/A converter consists of:

1.1 Functional aspects

3


code conversion in the abstract amplitude domain.
conversion from the abstract to the electrical signal domain. It consists of amplitude and time domain signal creation with the use of references (e,g, voltage, current).
Electrical signal shaping (filtering) in which the electrical signal takes a predetermined pulse shape modulated by the integer value w.

Code conversion

D(m)

binary to integer

w(m)

Electrical signal creation time and amplitude references Ts C s(t) PWM

Figure 1.2 D/A conversion in the time domain.

In this description of a D/A converter with figures 1.1 and 1.2 there is no coupling of the types of sub-operations and no transparency on the way of implementing each of them. In practice, all three sub-functions come together every time a specific algorithm is instantiated to realize the D/A function. The D/A converter that performs the 1-1 mapping of an input code to an output electrical signal as defined by the previously mentioned operations will be referred to as a D/A converter core, or simply a DAC core.

1.1.2

Functional specifications

A real D/A converter is subject to many physical imperfections that introduce limitations to its functionality. The DAC is designed such that it complies with a set of functional specifications, which can be embraced under the term “signal quality” within a well defined area of electrical and environmental conditions. Specifications include
Functional specifications that express whether the signal quality offered by the hardware complies to a prespecified range. Resolution, absolute accuracy, conversion rate, dynamic range are typical examples.
Physical specifications that describe the physical resources required (area, power etc) for the hardware to deliver a prespecified signal quality.
Environmental specifications that describe the conditions under which the hardware can operate with a predetermined signal quality. Temperature is a typical example. Hardware quality depends on the factors considered relevant for a given application. Often, figures of merit are defined to capture a combination of functional and physical specifications (e.g. energy per conversion per frequency for a specific accuracy). Functional specifications for DAC’s are described in more detail in the following.

4

Chapter 1 Digital to Analog conversion concepts

Signal quality receives proper meaning by defining how information is embodied in the characteristics of the electrical signal, and how these are affected by physical imperfections. In an ADC (see fig. 1.3) all errors due to physical imperfections are embodied Input

Output ADC

00111

All problems are embodied in the amplitude domain (codewords)

Input

Output DAC

Problems are distributed in the amplitude and time domains

Figure 1.3 Dynamic problems affecting amplitude and time domains of

DAC/ADC output signals. in the amplitude domain of the output signal (the codewords). In a DAC the output signal consists of a series of pulses. Therefore, errors related to limitations in the dynamic response of the DAC are embodied in the characteristics of pulse to pulse transitions (fig. 1.3). These dynamic phenomena decay substantially at the end of the sampling period and the settled (DC) value of the converter can be determined. Therefore, the impact of physical problems in the functional behavior of the DAC is distributed in both amplitude and time domains at the output signal and each problem can be mapped to a specific deformation of the ideally expected waveform (overshoot, delay, settling, etc.); in contrast, in an ADC everything ends to amplitude domain errors. Consequently, the revelant issue for DAC’s is which output waveform characteristics are relevant for a given application. A major distinction is between static and dynamic performance evaluation. This refers to the use of time invariant, or variant input signals (e.g. sinusoids), respectively. The latter result in dynamics of transients that dominate the performance. One way of assessing dynamic performance is based on the time domain response of the DAC for a full scale pulse as input (fig. 1.4). This method relies on evaluation of waveform characteristics such as the time it takes for the output signal to settle within a specified value (e.g. LSB). Other criteria include the rise/fall times, or the glitch magnitude compared to an LSB value. Evaluating time domain electrical characteristics was exercised until the beginning of the 90’s.1 The shift of interest to the spectral properties of signals was essentially a shift from characterizing hardware at a higher layer, following the trends of digital processing systems evolution toward larger signal processing systems. Sinusoidal signals are the most widely adopted type of signals used for performance evaluation. When processing sinusoids, any waveform deformation that generates (non) harmonic distortion is relevant to performance. Before giving the figures of merit that describe linearity it is insightful to give a brief description of the concept of linearity. 1 Static and dynamic performance terminology for ADCs and DACs is given in [2], expressing the methods to characterize functional performance (see also [3] for static and dynamic test methods of these times).

1.1 Functional aspects

5

overshoot and glitches < LSB LSB

LSB

settles to 1 LSB error

LSB Settling time

Figure 1.4 Full scale transition: (a) settling time and (b) amplitude based eval-

uation of dynamic performance.

Nonlinear distortion is the distortion caused by a deviation from a linear relationship between specified input and output parameters of a system or component. For the DAC, nonlinear distortion refers to its input-output functional relationship. Yet, further specification is required to define which particular aspects of this relationship are relevant. The DAC realizes a transfer function between its input and output signal amplitudes. For an ideal DAC this linear function can be described as s = α · w, where α is a gain factor while s and w have their usual meaning. Time domain effects are not included here; it simply defines the output settled, or DC, signal value that corresponds to an input value. In practice, the transfer function is not linear and shows deviations. It can be modeled as a ν -th order polynomial s = α1 w + α2 w2 + α3 w3 + ...αν wν . The degree of deviation from the ideal transfer function determines the accuracy of the converter. Because only static signals are assumed, it can be called static nonlinearity. Neglecting the inherent dynamics of the DAC but using a time-variant signal, a nonlinear error is generated at the output that changes over time. The only dynamic phenomenon here relates to the signal. In reality time-variant signals are processed by a DAC that in addition involves certain dynamic behavior. For a input sample to sample transition, an output signal transient is composed. The nonlinear errors in these case extend to the nonlinear relationship between the output signal transients, which are different for different input sample transitions. Errors generated in this way are also dynamic nonlinear errors, but dynamic applies now both to the signal and the inherent dynamics of the DAC. In practice, the DAC dynamics are dominant as frequencies increase beyond a few MHz.

Number of bits The number of bits N of the DAC represents the relative accuracy with which a full scale electrical signal range can be represented in discrete steps. Observe that in a DAC quantization noise or distortion is not a relevant issue since by nature of the DAC function it does not introduce quantization.

6

Chapter 1 Digital to Analog conversion concepts

Differential and Integral Non-Linearity For static performance characterization, Integral-Non-Linearity (INL) and the DifferentialNon-Linearity (DNL) figures are used. DNL expresses the output difference between two adjacent codes compared to the LSB step ∆. The INL expresses output amplitude deviations from ideal values for a selected input codeword. The ideal output values fall in a line that is corrected for gain and offset errors. The DNL and INL at an input step k are defined in [4] by DNLk =

Ak −Ak−1 a·∆

INLk =

Ak a·∆

(1.1)

where ∆ is the LSB step and a is the input value corrected for offset and gain error. The worst case DNL and INL are given by DNL = maxk∈1...N {|DNLk |}, INL = maxk∈1...N {|INLk |},

(1.2)

Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the power of the fundamental and the total noise power within a certain frequency band excluding harmonic components: SNR = 10 · log10

PS , PN

(1.3)

where PS is the signal power and PN is the noise power in the band of interest. The SNR is not a linearity figure in the strict sense. Whether or not it may be used in a linearity context is a modeling issue. For example, amplitude quantization is a non-linear effect that is expressed as a transfer function [5] and for sinusoidal signals it generates harmonic distortion that can be calculated. However, it is often approximated as noise (see [6] for an overview of the conditions). Other effects can be considered noisy as well. Dynamic range In a system or device dynamic range is the ratio of a specified maximum level of a parameter, such as power, current, voltage, or frequency to the minimum detectable value of that parameter. The dynamic range is usually expressed in dB. In a transmission system, dynamic range is the ratio of the overload level, i.e., the maximum signal power that the system can tolerate without distortion of the signal, to the noise level of the system. Used in the context of digital systems, it defines the ratio of maximum and minimum signal levels required to maintain a specified bit error ratio. Total Harmonic Distortion and Signal to Distortion ratio The total harmonic distortion (THD) is the ratio of the total harmonic distortion power and the power of the fundamental in a certain frequency band, i.e. T HD = 10 · log10

∞

∑k=2 Pk , PS

(1.4)

1.1 Functional aspects

7

Power (dB)

where Pk is the power of the k-th harmonic, and PS is the power of the signal. The inverse of the THD can be defined as the Signal to Distortion ratio (SDR).

SFDR

f

2f

3f

4f

frequency (Hz)

fundamental

Figure 1.5 Spurious Free Dynamic Range (SFDR).

Signal-to-Noise and Distortion Ratio The signal-to-noise-and-distortion ratio (SNDR) is the ratio between the power of the fundamental and the total noise and distortion power in a certain frequency band SNDR = 10 · log10

PS , PN + ∑∞ k=2 Pk

(1.5)

where Pk is the power of the k-th harmonic. Spurious Free Dynamic Range The spurious-free dynamic range (SFDR) is the ratio between the power of the signal and the power of the largest spurious (unwanted) tone within a certain frequency band, as shown in figure 1.5. SFDR is usually expressed in dB as SFDR = 10 · log10

PS , Pmax

(1.6)

where PS is the signal power and Pmax is the power of the largest spurious component in the band of interest. The SFDR is the same when one distortion component is very dominant with respect to the other, and when all components are equal. In the former case the SFDR approximates the SDR, but in the latter SFDR and SDR are widely different. Bandwidth and conversion rate All the previously given measures of linearity need always to be associated with a bandwidth in which they are evaluated, and a conversion rate. The bandwidth of the DAC

8

Chapter 1 Digital to Analog conversion concepts

defines the frequency range in which the figures of merit are evaluated. The maximum conversion rate of DAC defines the maximum rate of conversion of samples at which the functional specifications are within their specified range. In literature, it is most often used to describe the maximum conversion rate at which the DAC still operates, meaning that it still captures properly the digital input data. This definition, however, does only characterise the digital parts of the DAC and the limits of the technology used. Functional specifications for this book The range of functional specifications that are relevant for this thesis are
Resolution and accuracy 10 − 16 bits.
Conversion rates 100 − 1000+ MHz.
SFDR over 60 dB for signals up to the Nyquist frequency.

1.2

Algorithmic aspects

The definition of an algorithm is always given with respect to a particular problem that needs to be solved. An algorithm defines a step-by-step problem solving procedure for solving a problem in a finite number of steps. An algorithm has a ubiquitous scope and applies in every step of the design hierarchy. The function defined by a DAC core can be realized with a wide variety of algorithms. Each D/A conversion algorithm represents a mapping of the D/A function to a specific combination of functional components and operations that can realize the function. The main components of a D/A algorithm are 1. Coding. Coding describes all aspects related to how the assumed binary input symbols will be converted in the end to integer symbols at the output. The weighting can be binary, thermometer or any other code form which can be easily convertible to an integer value. 2. The reference quantity. The (electric) reference of the signals being processed to make the conversion. 3. The electrical generation mechanism. The electrical generation mechanism describes the physical mechanism that creates the signal. It is distinguished in (a) the Amplitude domain, where for example amplitude modulation (eg. PAM) describes the mechanism of signal shaping of the amplitude in proportion to the input code, (b) and in the Time domain, where PWM, PPM, etc. modulation concepts describe the signal shaping of the time domain characteristic (duration, position etc) in proportion to the input code.

1.2 Algorithmic aspects

9

The combination of the algorithmic concepts is described with an algorithmic architecture that binds together the exact functions between signals, signal components, the time steps of execution, the amplitude conversion steps, and the reference division. The mapping, or translation of the D/A algorithm to hardware includes always the following two steps 1. Partitioning: it defines how certain operations will be divided in sub-parts, each part realized with different algorithmic concepts. It also defines the number of steps and the order with which the algorithmic concepts instantiated occur. 2. Time Scheduling: it assigns relative time to the operations, ie. the order in which the operations are performed. Partitioning is a concept that can be applied hierarchically and recursively in a DAC. More details about it will be given in another chapter. Next, a specific form of partitioning used very often in the coding of the DAC will be describe in more details: segmentation. The binary to decimal conversion is written as N

w = ∑ Di 2i

(1.7)

i=1

for an input binary code D = D1 D2 ...DN and an output decimal value w, which describes that for an N bit converter a word consisting of N digits are multiplied with binary weighted units and then summed. Let us consider the following modification of eq. (1.7): NF

NC

i=1

k=1

w = ∑ Di 2i−1 + ∑ Dk+NF 2k−1 2NF

(1.8)

with NC + NF = N. This equation says that the output code is generated by the summation of two terms, each one defined with different weighting factors and different bits of the input code word. The separation of the overall code conversion in two or more parts is a partitioning of the code. The part with the NC Most Significant Bits (MSB’s) is called the coarse part, and the part with the NF Least Significant Bits (LSB’s) fine part. Code conversion in a segment requires a dedicated code conversion digital circuitry. In DAC terminology, segmentation is explicitly meant as partitioning of the binary code in one part that remains binary coded, and another one that is decoded to a thermometer code [7], which is only one of the possibilities available. If all binary words are translated to thermometer code then it is said that the converter is called fully segmented; and when only some bits become thermometer encoded, then the larger the number of the thermometer bits is, the larger the segmentation that the converter uses. For example, for a 10 bit DAC in [8] 80% segmentation means 8 thermometer and 2 binary bits. This terminology will not be used here. Segmentation is a form of partitioning, consequently the larger the segmentation should be interpreted as “the more the binary code is partitioned to more parts, or segments”, and not that number of bits per partition is increased.

10

Chapter 1 Digital to Analog conversion concepts

N

2 −1 C N

2 −2 2 DN

N−2

N−1

2

2 DN−2

DN−1

N−3

2 D1

0

2N−3

C

Cw

1 Cw D

encoder

(a)

(b)

Figure 1.6 Parallel-bit algorithms: (a) combination of weighted units, (b) se-

lection of the correct value among all possible ones.

Examples of algorithms In fig. 1.6(a) binary weighted (coding) summation is portrayed. Unit replicas of the reference electrical quantity are provided by reference replication and scaling mechanisms. Other types of algorithms which are not based on summation and combination of weighted units exist as well. In fig. 1.6(b) another algorithm is shown, named parallelselect algorithm [1]. The algorithm selects the proper output value among all 2N − 1 possible output values. This means that all possible values must be available (task to be accomplished by reference replication and scaling). A selection mechanism picks the right output value with the aid of an encoding mechanism. D= D D... D 1 2

N

i=1,2,..,N C

C

D0

D

(−1)

N+1−i

z−1/2

−1

wi

−1

2

2

z−1/2 (a)

D 0 is the sign−bit for D i

Di

z−1/2

w(m)

z−1/2

z−1 (b)

Figure 1.7 Serial-bit algorithms: (a) conversion starts with LSB DN , (b) con-

version starts with MSB D1.

1.3 Signal processing aspects

11

Because in fig. 1.6(a) the composition of the output word is made in parallel for all weighted units the algorithm is called parallel-bit. The same applies for the algorithm depicted in fig. 1.6(b). Parallel-bit algorithms offer intrinsic advantages for high speed operation because all sub-operations can be performed synchronously to each other. Another main category of algorithms are the serial-bit algorithms [1]. The main characteristic of serial-bit converters is that they require a sequence of steps before they generate the correct output value. In each step a bit is resolved and the equivalent analog value of this bit is added in the output. After all bits are resolved the final value is available for use. The type of coding used determines the number of steps. For binary weighting codes N steps are needed, whereas for a thermometer code the steps vary between zero and 2N − 1. A binary weighted serial-bit algorithm is described by the iterative procedure: w(m, i) = w(m, i − 1) + Di (m)2i

(1.9)

where m is the sample index, and i iterates from bit to bit. A specific version of a serial bit algorithm is the cyclic algorithm, which uses the same hardware iteratively for all steps of the conversion. Two examples of serial-bit algorithms are shown in fig. 1.7. In literature, the term “algorithmic” converter is misleading because it is meant only for a specific type of cyclic converters neglecting the fact that all converters are algorithmic by nature! For both algorithmic-architectures shown in fig. 1.7 the code conversion is based on summation of binary weighted units, hence it is finalized after N steps. Therefore, although both are serial, there are differences on how they are realized. Most of the concepts mentioned can be instantiated recursively. An example can be found in [9], where the partitioning concepts are applied in the amplitude and time domains, in the coding, in a serial-bit formation. In particular, an amplitude domain D/A converter of 15 bits is partitioned in three parts (5 − 5 − 5, i.e. coarse, fine, finest). The three partitions are cascaded in series, which means that the conversion is divided in three sequential steps. Each part is individually realized using thermometer coding and realized again in a serial-bit manner. Several other algorithmic concepts may be added next to the parallel and serial concepts: for example, converters based on counters, on duty cycles, interpolation between previous and next values, etc.

1.3 Signal processing aspects Sampling and interpolation theory is the theoretical framework under which A/D and D/A conversion is placed when it comes to input-output signal relationships. The D/A function represents the reconstruction process of a sampled signal, however, if seen in view of generic discrete time signals it can be defined as a signal generation process. Two signal processing aspects of this process are discussed in this section.

1.3.1

Waveforms and Line coding

In communication terminology Binary Line Coding [10] represents how a series of bit data are formatted physically in an electrical signal which is passed on to a physical

12

Chapter 1 Digital to Analog conversion concepts

s(t)

mTs (m+1)Ts (m+2)Ts

t (sec)

Figure 1.8 DT/CT conversion and RZ interpolation of samples in a DAC.

channel. These formats are called line codes. Line codes are distinguished in two major categories: Return-to-Zero (RZ) and Non-Return-to-Zero (NRZ). Given a bit interval Ts , a RZ waveform returns to zero volts (for a voltage waveform) for a portion of the bit interval, whereas the NRZ stays constant. Line codes may be further classified according to the voltage levels that represent the binary data. Examples include Unipolar signaling, Polar signaling, Bipolar (Pseudoternary) signaling [10], etc. s(t)

mTs (m+1)Ts (m+2)Ts

t (sec)

Figure 1.9 Interpolation of samples in D/A converter using NRZ pulses.

The D/A converter output can show similar shape, and this is why the terms RZ and NRZ are used. In the D/A output, the signal represents CT information, and the pulse shape determines the interpolation of the signal value between the sample moments. DT/CT conversion and RZ Interpolation of D/A input data w(m) is shown in fig. 1.8. If T0 is the duration of each pulse, then the RZ pulses are described by s(t) = u(t) ⊗

∞

∑

m=−∞

w(m) (δ (t − mTs ) − δ (t − T0 − mTs ))

(1.10)

where u(t) is the unit step function. With NRZ pulses the signal is described in a Σ∆ form s(t) = u(t) ⊗

∞

∑

m=−∞

∆w(m)δ (t − mTs )

(1.11)

with zero initial conditions. A graphical representation of this signal is given in fig. 1.9.

1.4 Circuit aspects

13

The above descriptions can now be defined in a more generic way. Let us consider only the signal creation process of a real signal from an arbitrary sequence of samples z(m) assuming an arbitrary interpolating pulse h(t). Then the generated signal is given by s(t) =

∞

∑

m=−∞

z(m)h(t − mTs ) = h(t) ⊗

∞

∑

m=−∞

z(m)δ (t − mTs )

(1.12)

The signal generation process consists of the creation of an amplitude modulated delta pulse train, and the interpolation (or signal shaping, filtering, etc.), which assigns the wanted shape to the signal. The creation of the delta train is called DT/CT conversion, despite that the sequence of samples z(m) does not constitute any time varying signal as the term DT implies. Notice now how both NRZ and RZ waveforms from eq. (1.10) and (1.10), respectively, can be mapped to the general description of eq. (1.12). For the RZ waveform, we let the interpolating pulse be h(t) = u(t) and the samples z(m) to represent the specific samples w(m) of the D/A input. For the NRZ waveform, we assume that the signal w(m) is passed through a differentiator before it is interpolated, such that z(m) = ∆w(m) = w(m) − w(m − 1). Alternatively, one may consider z(m) = w(m) and replace h(t) by p(t), where p(t) is a pulse with a fixed duration of one sample period Ts . Moving back to the digital bitstream, to create such a waveform a series of finite energy pulses h(t − mTs ) is amplitude modulated by the binary data z(m), which are either logic one, or logic zero. For the spectral content of such a pulse train as a function of the pulse type, the encoding of bit values, etc. there is a plethora of results in telecommunication theory textbooks that describe it when assumptions are made for the type and content of signals z(m) (stochastic, deterministic, signals that represent specific digital modulation schemes, etc.) and for the specific line coding [10]. These results are placed in the heart of the D/A area on the basis of the previously mentioned similarities, if one modifies the meaning and properties of z(m) to the D/A input signal, and then links the D/A output signal to the particular physical problems that appear in a physical realization.

1.3.2

Signal Modulation concepts

The D/A conversion algorithms that described so far refer to algorithms that implement the DAC core function. DAC cores can be used as well as parts of larger D/A converters that use signal modulation in the whole stream of data that carries information, instead of using the one to one mapping between an input and an output value. These D/A converters seize specific modulation concepts that convert information from a given combination of amplitude and time domains to another combination, thereby operating in both domains of a real signal simultaneously. Σ∆ modulation is maybe the most popular modulation concepts that belongs in this category.

1.4 Circuit aspects The architecture of the circuit hardware is the result of a one-to-many translation of an algorithm to hardware. In this section we review some basic architectures that realize

14

Chapter 1 Digital to Analog conversion concepts

DACs. First architecture terminology is given, and then resistive voltage, capacitive voltage and charge, and current division architectures are briefly described.

1.4.1

Architecture terminology

Architectures are distinguished in literature via combinations of circuit and algorithmic concepts, or via distinguishing features, e.g. Σ∆, Flash, cyclic, interpolative converters for DACs in general, or current-steering, R-2R ladder, binary weighted, resistor string, charge re-distribution, segmented, etc. for DAC cores in particular. Here, the focus is at high speed operation, therefore only parallel amplitude-domain DAC’s are considered. An architecture can be further distinguished in three main circuit parts: (1) reference scaling and replication network; (2) code conversion network; (3) output network. Reference network To realize waveforms that have characteristics proportional to the applied input codes, the amplitude range of the converter (amplitude and time references) should be discretized such that all resolution defined values can be recovered either via reference division, or via replications of the reference into scaled units and combinations of them according to a code. For an N bit linear converter with all information in the amplitude domain, the reference scaling and replication circuit should provide 2N − 1 discrete unit levels. Reference scaling in general (division or multiplication) is realized with a few basic circuit networks consisting of resistors, capacitors, voltage and current sources. Most amplitude domain scaling concepts exploit the charge conservation law. Code conversion The code conversion domain is where the binary to integer conversion is realized. The two main implementations are (a) a selection network that selects the correct value that corresponds to the input binary code, among all possible codes that are available for selection, (b) a combinatorial network, which combines weighted quantities according to a code or code combinations and generates the proper output value dependent on the input code. The code conversion domain can be realized in the voltage, current, or charge domain and usually grands the name of the converter. Output network It is the role of the output network to make the necessary conversions and impedance adaptations such that the DAC can drive efficiently external loads. The most common blocks required are voltage to voltage buffers for impedance adaptation, resistors, or integrating amplifiers to convert charge packets or currents into voltage. In practice, these circuits influence significantly the high speed potential of an architecture.

1.4 Circuit aspects

1.4.2

15

Resistive voltage division architectures

A parallel resistive voltage division DAC is shown in fig 1.10 [1]. It consists of three stages: the first is a resistive divider, the second is a network of switches, and the third is an impedance adaptation buffer. The reference voltage Vre f of the voltage divider is divided Vref RM

D1 V M−1

D2

R M−1

R

V M−2 DN

D1

R

−

V0

+ D1 V2

V1 R1 Voltage division

D1

D2

Voltage level selection

Volt

Volt

Impedance adaptation

Figure 1.10 Resistor string DAC core circuit.

in M = 2N steps using a network of identical resistors. Because the number of resistors scales with a power of N, for high resolution this architecture becomes impractical. The main consideration for the ladder is to meet the requirements for INL and DNL, which are limited by process mismatch between resistors. The ladder’s resistors are made of polysilicon or of diffusion layers. The physical reasons causing the values of identically designed resistors to vary are geometrical variations, doping level variations, variations in contact resistances, etc. The layout of the resistor ladderon silicon has a significant impact on the magnitude of these problems. The DC signal error for an input code is determined by the accumulation of the individual resistor errors that contribute to the output value. When the individual errors are random, the law of the large numbers applies. The resistor value seen at each tap is important for the capability of the ladder to discharge large capacitive load at each tap. Because the resistance varies from tap to tap the speed of charging a capacitive load varies as well. The transition time from a signal value to another is modulated by the input codeword value because this determines which tap is selected. This result in significant signal distortion. If the ladders are made of diffused resistors, then the dependence of the resistance value on the thickness of the depletion layer beneath the device which is a function of the voltage is important, because this voltage is a function of the rank of the resistor in the ladder, and varies from the reference voltage to the ground. Also, the depletion layer capacitance across the ladder to

16

Chapter 1 Digital to Analog conversion concepts

the substrate can also impact the charging and discharging time constants of each tap. The network of switches is controlled via a decoder by the input bits. For an input codeword the network selects one of the binary taps and provides resistive path from that tap to the output node. For an N bit DAC N switches appear in series between the tap and the output nodes. Consequently, a very large number of switches is required for high resolution. Moreover, the switch devices introduce additional input signal dependent impedance modulation [11]. Finally, an output buffer is required by this DAC to drive properly an output load. This buffer is a major bottleneck in high speed. In literature several architectural modifications have been considered [4,7,11]. In [12] a modification called switched subdivider has been introduced, which reduces the number of required devices to approximately 2N/2 instead of 2N . This technique is based on partitioning the ladder in a coarse-fine configuration. Drawbacks of the switched subdivider architecture have been alleviated with the double resistor string ladder (intermeshed ladder) architecture [13]. In [11] the combination of an intermeshed ladder [13] in a matrix arrangement [14] proved the feasibility of 10 bits of resolution with 50 MHz conversion rate, which is basically the highest reported for these type of converter. In summary, the main limitations of this circuit architecture are: the accuracy of matching (random and deterministic) between the resistors; the output buffer, which dominates the performance at higher frequencies; the code-dependent output impedance; the switch network. Resistor string DACs proved capable and versatile for medium-high resolution and low to moderate speed applications due to several inherent advantages (monotonicity, versatility, compactness of integration etc), but not equally succesful for high speeds.

1.4.3

Capacitive voltage and charge division architectures

Capacitive voltage and charge division based DAC cores are realized with networks of switched capacitors based on charge re-distribution. This concept has been adopted in [15] to create a voltage-division binary-weighted parallel-bit A/D converter, whereas in [16] it was used to construct a voltage-division cyclic DAC. The binary-weighted DAC from [15] is portrayed in fig. 1.11(a). The SC network consists of weighted capacitors. An additional capacitor C is added such that for an N bit converter a total of 2N C capacitance is present at the common capacitor terminal. The capacitor array is discharged before each conversion via the switch Sd . Then all capacitors except the additional resume the reference voltage at their individual terminals and precharge to Vre f . The additional capacitor C is held grounded. A total charge Q = Vre f C2N is deposited on the top plates. When the conversion starts all capacitors resume ground, or Vre f , dependent on their bits, while the additional capacitor is let free. The charge conservation law makes the stored charge in the top plate to re-distribute forcing a voltage voltage at the top plate which is a fraction of Vre f according to the code. The accuracy of SC DACs is limited by capacitor matching [17,18] and shares similarities with that of resistors: for a fixed relative capacitance spread, the averaging principle determines the impact on INL as a function of the number of elements of the converter. Inherent matching of capacitors is practically limited around the level of 10 bits of accuracy. Additional non-linearity problems rise from the voltage and temperature dependency of

1.4 Circuit aspects

17

SI CI Sd C

20 C

S1

VC 21 C

2N−1 C

S2

− +

SN

Sd

Vout C

20 C

S1

VC

S2

Vout

+

SN

V ref (a)

−

2N−1 C

21 C

V ref (b)

Figure 1.11 (a) SC DAC core circuit, (b)SC DAC using an integrating amplifier.

MOS integrated capacitors [17, 18]. The dynamic performance of SC DACs based on parallel capacitor arrays is highly affected by the large capacitance connected in parallel in the common node, and by the thermal noise considerations that dictate large capacitors. Notice that for all SC DACs a voltage buffer is required as well. For charge division, this buffer is replaced by an integrator to convert the current delivering the charge packets into voltage transients. To drive resistive loads an additional Gm stage may be necessary. The requirements for such blocks limits substantially the maximum speed of operation for SC DACs. SC DACs are realized today with differential circuit topologies. The architecture shown in fig. 1.11(a) has received several modifications [4, 7, 9, 19–23]. In [24, 25] the binary capacitor array was partitioned in coarse-fine segments connected by a capacitive divider (two-stage binary-weighted architecture [19, 26]). In this way, the LSB to MSB capacitor ratio’s was reduced significantly. A combination of circuit and code level partitioning was applied in [27] using a coarse thermometer resistor part and a fine binary capacitor part. The transition from the voltage division to the charge division using the same capacitor array from fig. 1.11(a) has been introduced in [19] (see fig. 1.11(b)). A circuit modification called the Direct-Charge-Transfer (DCT) technique is described in [22]. Sequential bisection of charge has been initially applied in [20] and recently in [28] and [29] with 10 bits in a differential version reaching a sampling rate of 400 Msample/s [29], and good dynamic performance for 300 Msample/s. In summary, SC DAC’s are limited by: matching accuracy of the capacitors; speed and linearity limitations of the voltage buffer; large capacitance present in the node of the top plates of the capacitors; non-linear relation between a capacitor’s value and the voltage; on-linear behavior of the junction capacitance in MOS switches; thermal noise. SC DAC cores have been used successfully as parts of other architectures such as “algorithmic” ADCs [30], pipeline [31], and Σ∆ ADCs and DACs [22, 32]. A wide application range is covered with this technique, from low data rate very high-resolution audio DACs [22, 23, 33] to high-resolution medium-frequencies [32] for communication applications (e.g. ADSL), SC DACs have been proven most suitable for high accuracy applications (12 − 16+ bits) and low to medium frequencies (1 kHz − 1 MHz).

Chapter 1 Digital to Analog conversion concepts

18

1.4.4

Current division based architectures

A parallel DAC based on current division is shown in fig. 1.12 known as the current steering (CS) DAC. It consists of a reference current replication network, a network that combines binary weighted currents to generate the output value and a current to voltage converter. The original version of this architecture was filed as a patent in 1955 [1] and granted in 1963. This architecture has proven well its potential for high speeds because the current steering nature of the circuitry is inherently fast, and because the demanding output buffer can be replaced with a simple resistor. V out I/V buffer

MSB

I N−1

LSB

I1 Current division network

Figure 1.12 Conceptual diagram of the binary CS DAC architecture.

CS DAC’s are used for high speed and high resolution applications such as Direct Digital Synthesis, video applications, upstream cable transmission channels, etc. DACs with conversion rates in the range of hundreds of MHz have been available in non CMOS processes for a long time already [34–38]. Recently they appear in CMOS as well [8, 39, 40] whereas resolution and accuracy of 10 − 16 bits are mainstream features of todays DACs [41–43]. The dynamic range offered by today’s realizations vary roughly between 50 − 90 dB dependent mainly on frequency ranges and conversion rates and not so much on the resolution. This architecture will be the main focus for the remaining of this book.

1.5

Conclusions

The chapter presented an overview of the functional, algorithmic, and circuit aspects of Digital to Analog converters. The D/A conversion function was defined as a signal creation process that realizes a code conversion in the abstract amplitude domain, a conversion from the abstract to the electrical signal domain, and a process of electrical signal shaping. The algorithmic aspects of the DAC were discussed, and the concepts of partitioning and scheduling were introduced. Waveform Line coding in the DAC output pulses was defined based on its similarities with digital pulse methods. Finally, circuit architecture terminology and an overview of the main DAC architectures were given.

2

Framework for Analysis and Synthesis of DACs

T

HE qualitative lines of the proposed framework of analysis and synthesis for DACs will be described in this chapter.

2.1 Overview The main lines of an analysis and synthesis framework are explained with the aid of fig. 2.1. The system, e.g. a DAC, realizes a function between input and output signals. It can be described in various hierarchical layers with subfunctions, circuits, etc. Actual input signals are applied to it via its functional, electrical, and physical environment. The functional inputs are constitutional parts of its functional relationship, whereas all other inputs are parameters of its behavior. The outputs responses of the system and its physical characteristics are described by properties, such as signal quality, silicon area, power consumption, etc. Several signals constitute its hidden excitations and responses that are visible only within its hierarchy. An analysis framework reveals the links between the system responses and properties and the input excitations applied to it, and shows the physical, circuit, and functional mechanisms and principles that govern its operation. Synthesis is the inverse of analysis. It starts with a predetermined aim of a system that is to be built and problems to address, although specific properties are still left open. A synthesis combines analysis with principle design techniques throughout the complete hierarchy of the system, from physics to signals. Therefore, synthesis requires the knowledge of design techniques to exploit the knowledge offered by the analysis in view of a coarsely defined system. A specific design example is the result of the combination of a specific set of required system properties -the specifications-, and the general synthesis procedures. 19

20

actual system responses

all system excitations

SYSTEM physical & signal properties hidden signal/system responses&properties

Design procedure

Instatiation&combinations of techniques

physics

device

principal techniques circuit

algorithm

Available IC design technology

function

DAC analysis

specific design example

specifications signal & physical (e.g. resources, environmental)

Chapter 2 Frame work for Analysis and Synthesis of DACs

Figure 2.1 Framework for analysis and synthesis.

DAC synthesis

2.2 Frame work description

21

2.2 Framework description In this section the main aspects of the framework for analysis and synthesis that will be build will be described. For a DAC, the limit to achieve low signal errors and high quality figures of performance (functional, physical, etc.) is determined by two factors: (a) the potential offered by the used technology that realizes the converter, (b) the level of exploitation of this potential, which is determined by the knowledge available about the way errors are generated, and the use of proper techniques to exploit this potential.

2.2.1

Analysis

The CS DAC represents the system shown in fig. 2.1. Of primary role in the developed concepts is the meaning of errors in the actual DAC response -the output signal-, and the way it can be grasped functionally, given that only in the functional level they can be evaluated. The meaning of errors in the signal can be understood introducing the concept of the normalized pulses at the DAC output. In the top left side of fig. 2.2 an ideal DAC output signal is shown. Below the actual signal we see the normalized pulses that result by dividing each pulse with the corresponding number of discrete steps it includes. In this ideal situation all normalized pulses are identical; they start at the same moment every other Ts and they have the same shape during the transition from the old value to the new value. The problem is that for a wide variety of reasons, the actual DAC signal pulses are corrupted, consequently their normalized counterparts look different from each other. This can be seen at the right side of fig. 2.2. The normalized deformations is an indication of signal errors. If the normalized pulses are different for each sample in Actual signal

normalized transitions

output signal

Ideal signal

mTs

(m+1)Ts

time

Figure 2.2 The concept of normalized pulses.

mTs

(m+1)Ts

time

Chapter 2 Frame work for Analysis and Synthesis of DACs

22

a data-dependent way, then for a sinusoidal signal the errors are harmonically related to it, whereas if the deformations are random, then the results are noise and distortion dependent on the correlation with the input signal. From chapter 1, in eq. (1.12) we see that the signal creation mechanism is based on mapping a sequence of samples to a sequence of pulses according to z(m) → z(m) · h(t) ⊗ δ (t − mTs )


  amplitude shape

(2.1)

timing

which says that 1. the amplitude of the signal is determined by z(m), 2. the time difference between successive sample transitions equals Ts , 3. the shape of the pulse h(t) is identical for every code to code transition. Therefore, when modeling the actual signal with the former equation, the timing of a pulse can be distinguished from its shape, both of which together form the actual signal pulse, or the actual code to code signal transition. In the following the use of the word actual is meant for this distinction. If each transition from an input value to another resulted in identical normalized pulse shape and ideally accurate timing, then the ideal amplitude modulated pulse train given in eq. (2.1) would be obtained. The quality degradation of a DACs actual output signal can be related to the deformations of its normalized pulse shape and timing in random or deterministic ways, correlated or not to the input signal (for example, clock jitter). In other words, the signal’s quality is a function of the the non-linear transfer functions pulse-shape vs. signal, and timing vs. signal.

Horizontal modulation in the signal flow DAC function signal in z(m)

subfunction 1 (decoding)

subfunction 2 (re−timing)

subfunction 3 (V/I conversion)

signal out s(t)

Figure 2.3 Signal flow in the functional description of the DAC.

Another aspect in the framework is the association between output signal errors and the input signal in view of system parameters and properties of lower hierarchy: that is, how do the normalized pulses depend on the signal; what do exactly these dependencies cause; what is their dependence with system properties and parameters.

2.2 Frame work description

23

To understand these aspects the so called error generation mechanism of each error need to be found. These are the mixing of vertical and horizontal modulation mechanisms. The DAC function can be partitioned in main subfunctions realized by functional circuits, which are further realized by circuit components. In each hierarchy layer there are horizontal modulation mechanisms in the input-output signal flow. Horizontal means that the modulations take place at the same physical abstraction layer. For example, the principles of modulation theory apply to describe how the signal is generated from its primitive signal components in the functional layer: this defines the functional signal generation mechanisms of the DAC. A description of this functional mechanism is given in fig. 2.3 for the CS DAC, without loss of generality. Circuit imperfections are usually introduced at specific locations at the bottom layers of the DAC description, however they can be abstracted at the functional level. How they are introduced at these locations is determined by the vertical modulation mechanisms which translate physical imperfections to error signals at the subfunctions. The way errors are generated in each sublayer can be described with the corresponding error mechanisms (e.g. circuit mechanisms). Consequently, the mixture of horizontal and vertical modulation mechanisms results in the creation of signal errors in the output signal (see the schematic in fig. 2.4), and it describes the error generation, or error creation mechanism. Vertical modulation from physics to signal

Horizontal modulation in the signal flow DAC functional description signal in z(m)

subfunction 1

subfunction 2

subfunction 3

signal out s(t)

circuit network

circuit network

circuit network

circuit transistor

circuit transistor

circuit transistor

physical

physical

physical

Environment

Figure 2.4 Vertical and horizontal error generation mechanisms.

The pattern that will be followed is the following 1. Vertical error mechanisms are analyzed (i.e. the imperfections in the realization of each DAC subfunction) in electronic circuit details; 2. The results of the analysis will be translated to abstract errors in the subfunctions such subsignals embody important properties of the lower hierarchical levels. This will be made by grouping errors that share similar properties. Therefore, error properties will be defined, and the errors will be classified.

24

Chapter 2 Frame work for Analysis and Synthesis of DACs

3. The expanded signal flow such as the one given in fig. 2.4 will be reduced to a simple functional description similar to eq. (1.12). This will be studied to reveal the signal errors as a function of generic input signals with lower hierarchical layer properties as parameters. 4. The generic results will then be applied to specific cases of error mechanisms with specific setting of DAC input signals and system parameters.

2.2.2

Synthesis

The exploitation of knowledge over the error generation mechanisms in the DAC consists of two components: first, use of the analysis to rationalize and improve the way DACs are designed with established designed techniques, subsequently improving the state of the art performance envelope, and second, to pave the way for new design techniques that can push the DAC performance envelope even further. How this will be achieved is further described in the following paragraphs. The analysis framework approach described previously, summarizes the error knowledge by classifying errors according to their principle properties. Furthermore, via the identification of the vertical and horizontal error components it shows how errors are influenced by parameters, actual and hidden signals, etc. that span through the complete physical hierarchy of the DAC. Therefore, in fig. 2.1 it can be said that the analysis provides the knowledge on how the output signal functional and physical properties of the DAC are parameterized to its excitations, responses and parameters. Since all errors of a class share common characteristics, the line of thinking can be inverted to see that all errors of the same class can be treated in the same principle ways; each class of errors can be associated with specific principle techniques. Of course, treating an error requires that there is specific information about it (its actual values, its parameters, etc.). Consequently, once the basic properties of an error are known, and information about it or its principle components can be extracted, in principle it can be corrected using principal techniques shown at the bottom of fig. 2.1. The information about the errors, their principle components, the architecture and circuits, the input and output signals, the application, the environment, and many more, all relevant ot the DAC that is to be realized, can be distinguished to a-priori and aposteriori information. A-priori information means that it is known prior the design phase and can be taken into account in it, whereas a-posteriori information can only obtained after manufacturing. Information is then used to process errors instantiating combinations of techniques. As a result, the way design techniques use information can also distinguish them in those based on a-priori, and those based on a-posteriori information. The combination of the analysis for the CS DAC architecture and with design techniques reveals a landscape plenty of unexplored paths. Specification will be made on which paths to explore experimentally, because not all options are physical realizable, or beneficial to do so.

3

Current Steering DACs

I

N this chapter a more detailed look is given in the Current Steering DAC architecture. Initially, some architectural, circuit and electronic aspects of it are described, and then an overview is given of existing technology implementations.

3.1 Basic circuit A fully binary weighted DAC is shown in fig. 3.1. It consists of a current replication network which generates weighted currents (shown as independent current sources), a current switching network controlled by the binary bits, and a resistor that converts the current to voltage. A new N bit word sets the switches in the corresponding on or off state. The switch network combines at the output node the corresponding current and creates the output value. This process repeats for each new word. On the right side of fig. 3.1 a possible implementation with MOS transistors is shown. The LSB current source consists of a MOS current source in a cascode configuration. Both are biased at constant voltages. To build the current sources of the other bits, the LSB transistors are sized up according to the bit weight and are biased by the same bias voltages. The switches are made by differential pairs, and their sizes are scaled up according to the bit values as well. In practice, partitioning is applied to the weighted sources and each weighted current source (or cascodes, or switches) is made of a number of LSB devices connected in parallel (the LSB device becomes the unit device). By partitioning the weighted devices in units so that the MSB consists of 2N −1 unit devices, the unit devices can be positioned according to common-centroids or other related layouting algorithms to reduce the impact of matching error gradients etc. 25

26

Chapter 3 Current Steering DACs

Switched current cell R

MSB

I N−1

V out

differential current switch

LSB

I N−2 I

I

cascoded current source

Figure 3.1 Simple binary weighted CS DAC and transistor implementation.

This very simple and compact implementation is able to reach very high conversion rates, being limited only by the steepness of the data waveforms carrying the bits, by the maximum switching speed of the current switches, and by the process limitations. However, its simplicity and low power is paid with severe drawbacks that limit its performance long before the limits of the technology are reached. There exist two main problems. First, matching requirements for achieving good accuracy are very high because weighting restricts the advantages offered by the law of the large numbers. The MSB current (2N − 1 times larger than the LSB) needs to be matched to the LSB one within one LSB accuracy. This dictates tough matching requirements. The second problem relates to the weighted impact of switching problems: the socalled MSB/LSB glitches. They can be the result of imperfect synchronization of the data waveforms that control the current switches. For example, in a 6 bit binary weighted DAC at the midscale transition 011111 → 100000 the MSB current source turns on and all the remaining bits turn off. If the MSB source turns on a bit earlier than the remaining sources turn off, then for a time interval the code 111111 will appear before the 100000. This instanteneous voltage spike (major carry glitch) in the normal operation of the DAC creates harmonic distortion. Glitches with lower amplitudes appear also at the transitions at 1/4, 1/8... This type of problems has been for years the menace of CS DAC’s. Full binary weighted converters have been primarily reported in literature until the end of the 70’s and in some high conversion rate DACs in the 80’s [35]. Some efforts on this direction are still made today [44, 45], mainly with an eye on the low power corners of the design space. The solution for the MSB/LSB glitches were the famous de-glitching circuits, which appeared already before [46,47]. The term “de-glitching” is not very much in use today, but the concept behind it (re-sampling) is used very often [4, 7, 23, 42] at the penalty of migrating all problems of the switches to a Track and Hold (T/H) circuit that can not operate at very high frequencies with good dynamic performance.

3.1.1

Partitioning and segmentation

Code partitioning was introduced in [48] as a means to reduce the matching requirements between MSB and LSB sources. However, its impact is much broader. Typical options is

3.1 Basic circuit

27

R

V out

R

R V out

I

I

I

Vb2 Vb1

Output: 2^N−1 bits

Binary to thermometer decoder

Bit 1

Bit 2^N−1

Output: 2^N−1 bits in differential form

Binary to thermometer decoder N

1 Binary input N

Binary input

1

Figure 3.2 Thermometer CS DAC and its circuit implementation in CMOS.

to use some binary and some thermometer bits. Other codes can be used as well. In the following a brief overview of the existing views of code partitioning is given. In the far opposite side of the full binary DAC lies the full thermometer DAC (fig. 3.2). Each thermometer word consists of 2N − 1 bits, each one driving a switched current cell. All switched current cells are identical relaxing the matching requirements substantially. Binary weighted switching problems are eliminated and monotonicity is guaranteed because when bits change in the input, sources are either turned on, or turned off, but not both. The matching of timing and switching behavior of the identical switching currents becomes now a major problem. It is nowadays one of the most important issues of CS DACs. As it will be shown later, large numbers governs equally well this problem. The large numbers is the strong and the weak point of this method. The strong point is the averaging principle. However, as the resolution scales up, the number of elements increases dramatically (e.g. 4095 switched current cells for a 12 bits DAC) and requires a tremendously complex decoder, interconnect lines, etc. This approach becomes impractical for more than 8 bits (255 elements), although there are exceptions [49]. And despite differences in the switching currents (e.g. due to mismatch) average better with more thermometer bits, at the same time their synchronization becomes more difficult. A compromise between the two is the segmented (partitioned) [48] converter which uses a coarse thermometer part, and a fine binary part. A conventional segmented architecture (fig. 3.3) consists of 1. a digital decoder responsible for encoding operations for the binary input data. 2. a delay equalizer that matches coarsely the delays of binary and thermometer data. 3. a clock-data synchronization circuit which synchronizes the data waveforms to the

28

Chapter 3 Current Steering DACs

R

IT

IT

IT

2B I

2I

I

Clocked elements (latches, or flip−flops)

B

2 1

Output: 2^T−1 bits

Binary to thermometer decoder

Clock generator

Delay equalizer

Input: T bits

N

B+1

Thermometer bits: from B+1 to N

B

2 1

Binary bits: from 1 to B

Figure 3.3 A thermometer-binary segmented architecture.

clock with finer precision and conditions all data waveforms. It consists of a clock generation circuit, a clock distribution network, and clocked elements. 4. the current switching network that is driven by the clocked elements. 5. the current source network where the currents are generated. Segmentation is considered mainstream option nowadays. Opinions differ as to how many bits should be assigned in each part. Initially, the binary to thermometer decoding circuitry was the dominant issue [38, 50, 51]. The larger the thermometer part, the more complex the logic-depth, the larger number of clocked elements, and the more difficult it becomes to satisfy high data throughput with good data signal integrity, power and substrate bounce constraints, timing, and power consumption demands. These issues are also a strong function of the circuit styles used. Several articles [34, 37–39, 41, 50– 54] demonstrate the attention that has been given to these points. In [8] it is believed that the main dynamic problems are all major carry related glitches, thus the number of thermometer bits should be maximized to the level tolerated by area, power consumption and complexity. Others [55] believe that the larger the thermometer part is, the more difficult it becomes to satisfy the timing accuracy of the switch signals, therefore it should not be maximized. In [42] the old-time-classic trust in re-sampling circuits is observed; they are using segmentation only for DC matching issues.

3.1 Basic circuit

3.1.2

29

Current switching network and current sources

A current switch and a current source form together a switched current cell (SI). The SI cells are to a great extent responsible for the performance of the DAC and occupy a large portion of the area of the DAC. A conventional topology of an SI cell consists of a cascoded current source configuration and a differential current switch (see fig. 3.1 and 3.2). The input of the cell is a low to medium swing differential signal and the output is a differential current. Usually all cells share the same bias voltages. Dependent on the input bit values the current is driven to one or the other side of the cell -thus the term current steering. This makes the switching very fast because the large capacitances associated with the current source terminals stay charged for most of the time. An extended list of problems is associated with these cells, which are described very briefly in this section. When a switch is turned on it connects a fixed impedance to the output node. When it turns off its impedance becomes very large. The total output impedance is the parallel combination of all switched-on cell impedances. Consequently, the output impedance is modulated by the input signal and generates both static (INL [38]) as well as dynamic errors (e.g, harmonic distortion [56]). A classical problem in a MOS switch implementation is that the MOS transistor provides a parasitic capacitive path from the control terminal to the output terminal (gate drain capacitance). When the switch is driven by a rapidly changing signal, a charge is injected at the output node of the DAC. Another basic problem is that due to processing limitations the switches from different cells exhibit different transient characteristics (e.g. timing skew). This leads to significant distortion. Finally, the non linear I/V characteristic of switches causes on/off dynamic behavior asymmetry, leading to spikes and non linear effects. Mismatch increases this problem.

3.1.3

Clock-data synchronization circuit

A clock-data synchronization circuitry makes re-timing and conditioning of the data waveforms carrying the bits. Because the resemblance and the shape of the waveforms reaching the current switches is critical, this circuitry essentially transfers the information from digital pulse waveforms of 0’s and 1’s to information contained in analog pulse signals, in which signals issues such as distortion, gain, noise, pulse shape, timing are considered. There are three main benefits of using this circuitry. First, the maximum conversion rate is determined by the delay measured from the input data nodes of the DAC to the output. Re-timing reduces this delay (pipelining). Second, it eliminates the unwanted variability of the decoded data waveforms (time skew, different rise and fall times, and logic glitches) introduced by different logic depths and wire interconnection lengths. Third, it adjusts the waveform characteristics to the requirements of the current switches. The clock-data synchronization circuit consists of 1. A global clock signal generator that generates a highly stable clock signal, with which all clocked elements are to be synchronized. 2. Clocked data-storage and -conditioning elements that receive data and clock signals and generate synchronized data pulses with the required shape.

30

Chapter 3 Current Steering DACs

3. Means of clock distribution and regeneration that delivers the clock signal to every clocked element of the system in the correct format. The three subparts have to be co-optimized together in the design phase because their requirements affect each other. Many similarities exists with the clocking systems of modern high performance digital microprocessors, hence results of this area may be utilized. The main characteristics of a DAC clocking system are: 1. Significantly smaller clocking network area than digital ICs, therefore smaller interconnection lengths and complexity, but problems like interference, cross-coupling, charge feedthrough phenomena, parasitic capacitances, transmission line effects have drastic impact on the analog output signal. 2. Small number of clocked devices (up to hundreds), but they dictate very small processing parameter and temperature fluctuations. Increased sensitivity to the mismatch in the shape and timing of individual pulses. 3. High operational speeds (up to GHz), however with maximum allowed clock uncertainties in the order of one pico-second.

3.1.4

Auxiliary circuits

In the CS-DAC architecture there exist circuits that are placed in the signal flow and they are vital for the processing of the signal components (latches, switches, decoder etc) and circuits that are not in the signal flow, hence they are not as critical because they make supplementary operations such as corrections, monitoring, etc. Any supplementary circuitry that is placed in the signal flow has to face the penalty of its location. In principle, latches are also auxiliary circuits. However, because their use is obliged if any decent performance is to be obtained, they have been transformed into constitutional circuits of the DAC architecture. Typical circuits that are not placed in the signal flow are monitoring and calibration circuits. They are responsible for monitoring and sensing some hidden signals and calibrating hardware such that the output signal is correct.

3.2

Implementations and technology impact

Technological options for DAC realization consist of primarily GaAs CMOS, Bipolar and BiCMOS. CMOS is today’s mainstream option to integrate the DAC as part of a larger VLSI system. While CMOS was not initially the high speed option, the continuous breeze coming from the rapid developments of integration technology brought CMOS in a dominant position in the CS DAC landscape and conversion rates of 1+ GHz with more than 10 bits of resolution have already been reached [39, 40]. A couple of examples of high conversion rate DACs available in literature include GaAs [35, 36, 57], Si-Bipolar [37, 50, 53], BiCMOS [55, 58–60], CMOS [8, 38–40, 43].

3.2 Implementations and technology impact

31

Non-CMOS implementations The fast switching times offered by GaAs, Si-Bipolar and SiGe technologies offer significant advantages for high conversion rates. BiCMOS allows also partitioning of the DAC in Bipolar and a CMOS parts in the same chip: digital operations and some non-critical analog with CMOS and switching parts with BJT’s. The main circuit characteristics of non-CMOS DACs aimed for high speed are: 1. Full differential current steering topology for every circuit in the signal flow. ECL levels for input and clock, small swing in the rest of the circuits of the DAC [37]. 2. Partitioning in a few thermometric bits (3-5) [34, 36, 37], or no partitioning at all [35, 61, 62]. 3. Decoder, if present, with a few alternatives (multi-level [50], row-column [37]). 4. Master-slave latches before the switches, latch buffers to filter switching noise of the latches and condition the data properly. Low swing differential signals everywhere, and especially at the switches. This offers high crossing points in the complementary switch control signals. Time multiplexing in the decoder or the latches in some cases to increase data throughput [35, 50]. 5. Speed optimized switched current cells. BJT cascoded resistors as current sources of the thermometric part in Si-Bipolar DACs, transistors for GaAs, and R-2R ladders for the binary part. 6. No output buffer, and direct connection of the current switches to the output node. 7. Re-sampling at the output in many occasions. 8. Multiple supply networks (analog, digital) to separate interference of digital switching noise in critical analog circuits. 9. DC accuracy achieved with inherent matching or post fabrication methods (e.g. laser trimming). CMOS implementations CMOS CS DACs dominate (e.g. [38, 39, 41–43, 54, 63–68]) today the DAC landscape due to their compatibility with digital processes. Their main characteristics (see fig. 3.4) are: 1. Single ended CMOS signal format for most circuits in the signal flow except from the current cell. Single ended CMOS clock format. 2. Partitioning between a medium to large thermometer part (5 − 8) and a relatively small binary part. 3. CMOS logic based decoder implemented with the row-column architecture [38] or with alternative configurations [41].

32

Chapter 3 Current Steering DACs

R

R

Vout

Vb2 Vb1

D

D1

T

2 −1

Binary to thermometer decoder

N

φ

BB

Clock generator

B+1

B1 Delay equalizer

B

2 1

Figure 3.4 A conventional Current Steering CMOS DAC implementation.

4. Reduced swing CMOS logic, and single latch configuration implemented with cross-coupled CMOS inverters. Also, reduced swing CMOS logic switch drivers to tune the crossing point of the complementary switch control signals. 5. Differential current switches, and use of cascoding to increase the impedance of the current sources, and transistor based current sources. 6. No output buffer, and direct connection of the current switches to the output node. 7. Re-sampling at the output in a few occasions. 8. Multiple supply networks (analog, digital) to separate interference of digital switching noise in critical analog circuits. 9. Calibration circuitry and switching sequences that deal with DC error correction. At first sight, there are not that many differences in the circuitry between non-CMOS and CMOS DACs. The main differences seem to be the larger number of thermome-

3.2 Implementations and technology impact

33

ter bits, calibration and switching sequences, single ended circuit logic, and single latch configurations for CMOS, compared to small number of thermometer bits, no calibration or switching sequences, full differential signals and circuit topologies, and master-slave latch configurations for non-CMOS DACs. Apart for the DC error correction methods, the remaining differences are mainly implications of technological differences, and as we will explain shortly partially because of different application focus. CMOS DACs appeared in the middle of the 80’s aiming for video applications (e.g HDTV), and started dominating only after the beginning of 90’s. A representative difference in speed between several processes can be seen comparing CMOS and Si-Bipolar DACs from [38] and [50] with 80 and 500 Msample/s, respectively (8 bits both). However, at the same time period CMOS DACs already started increasing significantly in conversion rates (e.g. 400 Msample/s, 4 bit [51]) but for less bits. Applications such as arbitrary waveform generators for testing equipment were the main drive to build Gsample/s DACs in GaAs with 12 bits such as the one found in [35], or later with the 14 bit GaAs DAC [36] that reached rates up to 2 Gsample/s. A Si-Bipolar DAC reaching the same rate at 10 bits was reported in [37]. Todays examples include a GaAs 12 bit 1.6 GSample/s DAC [57] and a 15 bit 1.2 GSample/s [59] and a 6 bit 22 GSample/s [60] implemented with SiGe BiCMOS process. Notice however, the cost in power consumption and area: a total of 6 Watts and roughly 30 mm2 are used for the cause of obtaining exceptionally good dynamic performance in [59]. For CMOS more than 1 Gsample/s was reached in [39] for 10 bits, and in [40] for 14 bits. One of the most important architectural aspects of the DAC was, and still is, the segmentation to thermometer and binary bits, because it has a multi-dimensional impact on several properties (linearity, matching requirements, complexity of design, area, power, additional error mechanisms, etc.). Given this context, the reason of the different numbers of thermometer bits used in CMOS and non-CMOS is easy to explain. The main aspect of using non-CMOS processes was the need for large conversion rates. Neither low DC errors due to mismatch [48], or low harmonic distortion -both become lower as the number of thermometer bits increases- were significant requirements at that time. At the same time, the main limitations for high speed (except the technology) and power was the digital logic of the decoder, Therefore, it is not strange that non-CMOS DACs had few numbers of thermometer bits, or none at all. Today, segmentation is exploited vigorously for the potential it offers for high linearity, consequently high speed DACs do use large number of thermometer bits. Another difference between CMOS and non-CMOS is the use of calibration. Calibration is a main option today for high resolution CMOS DACs making full use of the digital processing advantages offered plentyfully by modern narrow length CMOS processes. Interesting to note is that, while the turnover of the 80’s brought the first on-chip calibration DAC [69] (off chip calibration was lazer trimming) reaching a static linearity of 14 bits, still at the end of the same decade there were high resolution and high speed DACs [35] using on chip switching functions and off-chip trimmable current sources, or later [36] 1 − 2 Gsample/s 14 bit DACs with no more than 10 bits of static accuracy.

4

Dynamic limitations of Current Steering DACs

I

N this chapter, initially the state of the art of widebandwidth DACs will be presented. Then the type of knowledge needed to realize widebandwidth high dynamic range DACs will be described by comparison with existing knowledge on DACs with high sampling rates and good low frequency linearity. This discussion will highlight the main contribution of the remaining chapters of this book.

4.1 State of the art in dynamic linearity In this section, the state of the art in widebandwidth high dynamic range DACs will be presented and where and why CS DACs fail will be discussed. Let us examine the maximum conversion (sampling) rate of reported high speed DAC’s. The plot is given in fig. 4.1 (the data are given in appendix B). Some straightforward remarks can be made; for example, it is clear that some non-CMOS converters have provided much higher sampling rates in their given year context (indicated by the number next to each point). This is most likely due to the speed advantages offered by these processes. Recent CMOS DACs have already exceeded 1 GHz conversion rate. Since this plot says nothing about dynamic linearity at those frequencies the sampling rates indicate, we also evaluate the magnitude of the “glitch” artifacts relatively to the LSB level (see fig. 1.4(b)). This criterion defines that for a converter to comply dynamically to its resolution level, the magnitude of all glitches should be confined within one LSB value. With this criterion of dynamic linearity, significant knowledge has been developed that links specific circuit limitations to the relevant glitches (e.g. the anomalies in the middle of the sample to sample transients are not assumed to be a concern, but the glitches in the beginning and end of the transition are), and also design methods were developed 35

36

Chapter 4 Dynamic limitations of Current Steering DACs

Figure 4.1 State of the art in sampling rate.

to tackle these problems. Data from literature and industry shows a gradual reduction on the glitch level during the years (characterized by the so called glitch energy [7]) from 100 V psec at the beginning of the eighties to sub V psec levels at the end of the nineties. When dynamic linearity was subsequently characterized with harmonic distortion, many glitch related issues became obsolete. For example, for the glitch observed in the middle of the pulse transition in fig. 1.4(b) because it appears at the clock frequency, which is out of the band of interest, causes no problems. However, sample to sample transition anomalies became important because they generate harmonic distortion. To understand how the different meaning of the signal quality defines a completely new learning curve on the problems and methods [35, 36] is cited as representative of the transition phase to characterize the signal quality with frequency domain properties. In [35] a 12 bit DAC (with 14 bit static accuracy) is reported at 1 Gsample/s sampling rate which delivers a mere 52 dB Spurious Free Dynamic Range (SFDR) at just 1/10 of the sampling rate (100 MHz), and 62 dB using an output sampler. In [36] despite the 1 − 2 Gsample/s rates offered by a 14 bit GaAs DAC, only 58 dB are obtained at 62 MHz signal frequencies at a 0.75 Gsample/s rate. These results do not indicate badly designed IC’s, but IC’s that were designed for a specific meaning of dynamic signal quality associated to a specific type of signals (step signals). Next, representatice data of the period when signal quality is evaluated in the frequency domain are presented (essentially after [55] a sound focus in spurious performance is observed). The SFDR is here the relevant criterion. Each of the three plots in fig. 4.2,

4.1 State of the art in dynamic linearity

37

Figure 4.2 State of art SFDR at very low frequencies.

4.3 and 4.4) has on the horizontal axis the sampling rate and the vertical axis the SFDR: each coordinate of a data point represents the SFDR of a reported IC and the sampling rate in which it is reported. In each coordinate the resolution of the DAC is also noted. For each plot the data correspond to a different normalized frequency, that is f / fs . In fig. 4.2 data for very low frequencies f / fs