ADVANCED DC/DC CONVERTERS
Fang Lin Luo Hong Ye
CRC PR E S S Boca Raton London New York Washington, D.C. © 2004 by CRC...
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ADVANCED DC/DC CONVERTERS
Fang Lin Luo Hong Ye
CRC PR E S S Boca Raton London New York Washington, D.C. © 2004 by CRC Press LLC
Power Electronics App Series 8/19/03 10:11 AM Page 1
POWER ELECTRONICS AND A P P L I C AT I O N S S E R I E S Muhammad H. Rashid, Series Editor University of West Florida
PUBLISHED TITLES Complex Behavior of Switching Power Converters Chi Kong Tse DSPBased Electromechanical Motion Control Hamid A. Toliyat and Steven Campbell Advanced DC/DC Converters Fang Lin Luo and Hong Ye FORTHCOMING TITLES Renewable Energy Systems: Design and Analysis with Induction Generators Marcelo Godoy Simoes and Felix Alberto Farret
© 2004 by CRC Press LLC
ADVANCED DC/DC CONVERTERS
Fang Lin Luo Hong Ye
CRC PR E S S Boca Raton London New York Washington, D.C. © 2004 by CRC Press LLC
1956_C00.fm Page iv Thursday, August 21, 2003 4:25 PM
Library of Congress CataloginginPublication Data Luo, Fang Lin. Advanced DC/DC converters / Fang Lin Luo and Hong Ye. p. cm. — (Power electronics and applications series) Includes bibliographical references and index. ISBN 0849319560 (alk. paper) 1. DCtoDC converters. I. Ye, Hong, 1973 II. Title. III. Series. TK7887.6.L86 2003 621.31′32—dc21
2003051622
This book contains information obtained from authentic and highly regarded sources. Reprinted material is quoted with permission, and sources are indicated. A wide variety of references are listed. Reasonable efforts have been made to publish reliable data and information, but the author and the publisher cannot assume responsibility for the validity of all materials or for the consequences of their use. Neither this book nor any part may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, microfilming, and recording, or by any information storage or retrieval system, without prior permission in writing from the publisher. The consent of CRC Press LLC does not extend to copying for general distribution, for promotion, for creating new works, or for resale. Specific permission must be obtained in writing from CRC Press LLC for such copying. Direct all inquiries to CRC Press LLC, 2000 N.W. Corporate Blvd., Boca Raton, Florida 33431. Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identification and explanation, without intent to infringe.
Visit the CRC Press Web site at www.crcpress.com © 2004 by CRC Press LLC No claim to original U.S. Government works International Standard Book Number 0849319560 Library of Congress Card Number 2003051622 Printed in the United States of America 1 2 3 4 5 6 7 8 9 0 Printed on acidfree paper
© 2004 by CRC Press LLC
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Dedicated to Our respected great lady Mme. Liao Jing Ms. Luo Yuan Zhi and her family
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Preface
The purpose of this book is to provide uptodate information on advanced DC/DC converters that is both concise and useful for engineering students and practicing professionals. It is well organized in 748 pages with 320 diagrams to introduce more than 100 topologies of the advanced DC/DC converters originally developed by the authors. EMI/EMC reduction and various DC voltage sources are also illustrated in this book. All prototypes represent novel approaches and great contributions to modern power engineering. Power engineering is the method used to supply electrical energy from a source to its users. It is of vital importance to industry. It is likely that the air we breathe and water we drink are taken for granted until they are not there. Energy conversion technique is the main focus of power engineering. The corresponding equipment can be divided into four groups: • • • •
AC/AC AC/DC DC/DC DC/AC
transformers rectifiers converters inverters
From recent reports, the production of DC/DC converters occupies the largest percentage of the total turnover of all conversion equipment production. DC/DC conversion technology is progressing rapidly. According to incomplete statistics, there are more than 500 topologies of DC/DC converters existing, with new topologies created every year. It is a lofty undertaking to treat the large number of DC/DC converters. The authors have sorted these converters into six generations since 2001. This systematical work is very helpful for DC/ DC converter’s evolution and development. The converters are listed below: 1. 2. 3. 4. 5. 6.
First generation (classical/traditional) converters Second generation (multiplequadrant) converters Third generation (switched component) converters Fourth generation (softswitching) converters Fifth generation (synchronous rectifier) converters Sixth generation (multipleelement resonant power) converters
© 2004 by CRC Press LLC
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A review of the DC/DC conversion technique development reveals that the idea was induced from other equipment. Transformers successfully convert an AC source voltage to other AC output voltage(s) with very high efficiency. Rectifier devices such as diode, transistor, and thysistor effectively rectify an AC source voltage to DC output voltage. Nearly eight decades ago, people sought to invent equipment to convert a DC source voltage to another DC output voltage(s) with high efficiency. Unfortunately, no such simple apparatus such as a transformer and/or rectifier was found for DC/DC conversion purpose. High frequency switchon and off semiconductor devices paved the way for chopper circuits. This invention inspired the idea for DC/DC conversion. Therefore, the fundamental DC/DC converters were derived from the corresponding choppers. At present, the fundamental converters — Buck converter, Boost converter, and BuckBoost converter — are still the basic circuits for DC/DC conversion technique in research and development. The voltagelift technique is a popular method that is widely applied in electronic circuit design. Applying this technique effectively overcomes the effects of parasitic elements and greatly increases the output voltage. Therefore, these DC/DC converters can convert the source voltage into a higher output voltage with high power efficiency, high power density, and simple structure. It is applied in the periodical switching circuit. Usually, a capacitor is charged during switchon by a certain voltage. This charged capacitor voltage can be arranged on topup to output voltage during switchoff. Therefore, the output voltage can be lifted. A typical example is the sawtoothwave generator with voltagelift circuit. The voltagelift technique has been successfully employed in the design of DC/DC converters. However, its output voltage increases in arithmetic progression, stage by stage. The superlift technique is a great achievement in DC/DC conversion technology. It is more powerful than the voltagelift technique; the output voltage transfer gain of superlift converters can be very high, which increases in geometric progression, stage by stage. It effectively enhances the voltage transfer gain in power series. Four series of superlift converters created by the authors are introduced in this book. Some industrial applications verified their versatile and powerful characteristics. Multiplequadrant operation is often required in industrial applications. Most publications in the literature concentrate on the singlequadrant operation. This fact is reasonable since most novel approaches were derived from its simple structure. To compensate for these losses, the authors have spent much time and spirit to develop multiplequadrant converters, positivenegative converters in various generations. This book is organized in 18 chapters. The DC/DC conversion technique is introduced in Chapter 1 and the voltage list converters in Chapter 2. Chapters 3 to 6 introduce the four series superlift converters. Chapter 7 introduces the second generation converters; and Chapter 8, the third generation converters. Chapters 9 and 10 introduce the twoseries multiplelift pushpull switchedcapacitor converters. Chapter 11 introduces the fourth © 2004 by CRC Press LLC
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generation converters and Chapter 12 the fifth generation converters. Chapters 13 to 16 introduce the sixth generation converters. Chapter 17 introduces various DC voltage sources; and Chapter 18 introduces the gatingsignal generator, EMI/EMC, and some applications. The authors are pioneers in DC/DC conversion technology. They have devoted many years to this research area and created a large number of outstanding converters, including worldrenowned series DC/DC converters, namely, LuoConverters, which cover all six generation converters. Superlift converters are our favorite achievement in our 20years’ research fruits. Our biographies and information are provided on the following page. Our acknowledgment goes to the executive editor for this book. Dr. Fang Lin Luo and Dr. Hong Ye Nanyang Technological University Singapore
© 2004 by CRC Press LLC
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Authors
Dr. Fang Lin Luo is currently with the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore. He received his B.Sc. degree, first class with honors in RadioElectronic Physics at the Sichuan University, Chengdu, Sichuan, China and his Ph.D. degree in Electrical Engineering and Computer Science at Cambridge University, England, in 1986. Dr. Luo was with the Chinese Automation Research Institute of Metallurgy, Beijing, China as a Senior Engineer after his graduation from Sichuan University. He was with the Entreprises Saunier Duval, Paris, France as a project engineer from 1981 to 1982. He was with Hocking NDT Ltd, AllenBradley IAP Ltd., and Simplatroll Ltd. in England as a Senior Engineer after he received his Ph.D. degree from Cambridge University. He is a Senior Member of the IEEE. He has published two textbooks and 198 technical papers in IEE Proceedings and IEEE Transactions, and various international conferences. His present research interest is in power electronics and DC and AC motor drives with computerized artificial intelligent control and digital signal processing, and AC/DC and DC/DC converters and DC/AC inverters. Dr. Luo is the Chief Editor of the international journal Power Supply Technologies and Applications. He is currently the Associate Editor of IEEE Transactions on Power Electronics in charge of the technical topic Low Power Converters. Dr. Hong Ye is currently with the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore. She received her B.S. (with honors) in 1995 and the M.S. degree in Engineering from Xi’an Jiaotong University, China in 1999. She completed her Ph.D. degree in 2002 in Information Technology (IT) in the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore. Dr. Ye was with the Research and Development Institute, Xi’an Instrument Group, XIYI © 2004 by CRC Press LLC
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Company, Ltd., Xi’an, China as a Research Engineer from 1995 to 1997. Dr. Ye is an IEEE Member and has authored two textbooks and more than 38 technical papers in IEEE Transactions, IEE Proceedings, and other international journals and various international conferences. Her research interests are in the areas of DC/DC converters, signal processing, operations research, and structural biology.
© 2004 by CRC Press LLC
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Contents
1 1.1 1.2
1.3
1.4
Introduction Historical Review MultipleQuadrant Choppers 1.2.1 MultipleQuadrant Operation 1.2.2 The FirstQuadrant Chopper 1.2.3 The SecondQuadrant Chopper 1.2.4 The ThirdQuadrant Chopper 1.2.5 The FourthQuadrant Chopper 1.2.6 The First and Second Quadrant Chopper 1.2.7 The Third and Fourth Quadrant Chopper 1.2.8 The FourQuadrant Chopper Pump Circuits 1.3.1 Fundamental Pumps 1.3.1.1 Buck Pump 1.3.1.2 Boost Pump 1.3.1.3 BuckBoost Pump 1.3.2 Developed Pumps 1.3.2.1 Positive LuoPump 1.3.2.2 Negative LuoPump 1.3.2.3 CúkPump 1.3.3 TransformerType Pumps 1.3.3.1 Forward Pump 1.3.3.2 FlyBack Pump 1.3.3.3 ZETA Pump 1.3.4 SuperLift Pumps 1.3.4.1 Positive Super LuoPump 1.3.4.2 Negative Super LuoPump 1.3.4.3 Positive PushPull Pump 1.3.4.4 Negative PushPull Pump 1.3.4.5 Double/Enhanced Circuit (DEC) Development of DC/DC Conversion Technique 1.4.1 The First Generation Converters 1.4.1.1 Fundamental Converters 1.4.1.2 TransformerType Converters 1.4.1.3 Developed Converters 1.4.1.4 Voltage Lift Converters 1.4.1.5 Super Lift Converters 1.4.2 The Second Generation Converters
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1.4.3
The Third Generation Converters 1.4.3.1 Switched Capacitor Converters 1.4.3.2 MultipleQuadrant Switched Capacitor LuoConverters 1.4.3.3 MultipleLift PushPull Switched Capacitor Converters 1.4.3.4 MultipleQuadrant Switched Inductor Converters 1.4.4 The Fourth Generation Converters 1.4.4.1 ZeroCurrentSwitching QuasiResonant Converters 1.4.4.2 ZeroVoltageSwitching QuasiResonant Converters 1.4.4.3 ZeroTransition Converters 1.4.5 The Fifth Generation Converters 1.4.6 The Sixth Generation Converters 1.5 Categorize Prototypes and DC/DC Converter Family Tree References 2 2.1 2.2
2.3
VoltageLift Converters Introduction Seven SelfLift Converters 2.2.1 SelfLift Cúk Converter 2.2.1.1 Continuous Conduction Mode 2.2.1.2 Discontinuous Conduction Mode 2.2.2 SelfLift P/O LuoConverter 2.2.2.1 Continuous Conduction Mode 2.2.2.2 Discontinuous Conduction Mode 2.2.3 Reverse SelfLift P/O LuoConverter 2.2.3.1 Continuous Conduction Mode. 2.2.3.2 Discontinuous Conduction Mode 2.2.4 SelfLift N/O LuoConverter 2.2.4.1 Continuous Conduction Mode 2.2.4.2 Discontinuous Conduction Mode 2.2.5 Reverse SelfLift N/O LuoConverter 2.2.5.1 Continuous Conduction Mode 2.2.5.2 Discontinuous Conduction Mode 2.2.6 SelfLift SEPIC 2.2.6.1 Continuous Conduction Mode 2.2.6.2 Discontinuous Conduction Mode 2.2.7 Enhanced SelfLift P/O LuoConverter Positive Output LuoConverters 2.3.1 Elementary Circuit 2.3.1.1 Circuit Description 2.3.1.2 Variations of Currents and Voltages 2.3.1.3 Instantaneous Values of Currents and Voltages 2.3.1.4 Discontinuous Mode 2.3.1.5 Stability Analysis
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2.3.2
2.4
SelfLift 2.3.2.1 2.3.2.2 2.3.2.3 2.3.2.4
Circuit Circuit Description Average Current IC1 and Source Current IS Variations of Currents and Voltages Instantaneous Value of the Currents and Voltages 2.3.2.5 Discontinuous Mode 2.3.2.6 Stability Analysis 2.3.3 ReLift Circuit 2.3.3.1 Circuit Description 2.3.3.2 Other Average Currents 2.3.3.3 Variations of Currents and Voltages 2.3.3.4 Instantaneous Value of the Currents and Voltages 2.3.3.5 Discontinuous Mode 2.3.3.6 Stability Analysis 2.3.4 MultipleLift Circuits 2.3.4.1 TripleLift Circuit 2.3.4.2 QuadrupleLift Circuit 2.3.5 Summary 2.3.6 Discussion 2.3.6.1 DiscontinuousConduction Mode 2.3.6.2 Output Voltage VO versus Conduction Duty k 2.3.6.3 Switch Frequency f Negative Output LuoConverters 2.4.1 Elementary Circuit 2.4.1.1 Circuit Description 2.4.1.2 Average Voltages and Currents 2.4.1.3 Variations of Currents and Voltages 2.4.1.4 Instantaneous Values of Currents and Voltages 2.4.1.5 Discontinuous Mode 2.4.2 SelfLift Circuit 2.4.2.1 Circuit Description 2.4.2.2 Average Voltages and Currents 2.4.2.3 Variations of Currents and Voltages 2.4.2.4 Instantaneous Value of the Currents and Voltages 2.4.2.5 Discontinuous Mode 2.4.3 ReLift Circuit 2.4.3.1 Circuit Description 2.4.3.2 Average Voltages and Currents 2.4.3.3 Variations of Currents and Voltages 2.4.3.4 Instantaneous Value of the Currents and Voltages 2.4.3.5 Discontinuous Mode
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2.4.4
MultipleLift Circuits 2.4.4.1 TripleLift Circuit 2.4.4.2 QuadrupleLift Circuit 2.4.5 Summary 2.5 Modified Positive Output LuoConverters 2.5.1 Elementary Circuit 2.5.2 SelfLift Circuit 2.5.3 ReLift Circuit 2.5.4 MultiLift Circuit 2.5.5 Application 2.6 Double Output LuoConverters 2.6.1 Elementary Circuit 2.6.1.1 Positive Conversion Path 2.6.1.2 Negative Conversion Path 2.6.1.3 Discontinuous Mode 2.6.2 SelfLift Circuit 2.6.2.1 Positive Conversion Path 2.6.2.2 Negative Conversion Path 2.6.2.3 Discontinuous Conduction Mode 2.6.3 ReLift Circuit 2.6.3.1 Positive Conversion Path 2.6.3.2 Negative Conversion Path 2.6.3.3 Discontinuous Conduction Mode 2.6.4 MultipleLift Circuit 2.6.4.1 TripleLift Circuit 2.6.4.2 QuadrupleLift Circuit 2.6.5 Summary 2.6.5.1 Positive Conversion Path 2.6.5.2 Negative Conversion Path 2.6.5.3 Common Parameters Bibliography 3 3.1 3.2
3.3
Positive Output SuperLift LuoConverters Introduction Main Series 3.2.1 Elementary Circuit 3.2.2 ReLift Circuit 3.2.3 TripleLift Circuit 3.2.4 Higher Order Lift Circuit Additional Series 3.3.1 Elementary Additional Circuit 3.3.2 ReLift Additional Circuit 3.3.3 TripleLift Additional Circuit 3.3.4 Higher Order Lift Additional Circuit
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3.4
Enhanced Series 3.4.1 Elementary Enhanced Circuit 3.4.2 ReLift Enhanced Circuit 3.4.3 TripleLift Enhanced Circuit 3.4.4 Higher Order Lift Enhanced Circuit 3.5 ReEnhanced Series 3.5.1 Elementary ReEnhanced Circuit 3.5.2 ReLift ReEnhanced Circuit 3.5.3 TripleLift ReEnhanced Circuit 3.5.4 Higher Order Lift ReEnhanced Circuit 3.6 MultipleEnhanced Series 3.6.1 Elementary MultipleEnhanced Circuit 3.6.2 ReLift MultipleEnhanced Circuit 3.6.3 TripleLift MultipleEnhanced Circuit 3.6.4 Higher Order Lift MultipleEnhanced Circuit 3.7 Summary of Positive Output SuperLift LuoConverters 3.8 Simulation Results 3.8.1 Simulation Results of a TripleLift Circuit 3.8.2 Simulation Results of a TripleLift Additional Circuit 3.9 Experimental Results 3.9.1 Experimental Results of a TripleLift Circuit 3.9.2 Experimental Results of a TripleLift Additional Circuit 3.9.3 Efficiency Comparison of Simulation and Experimental Results Bibliography 4 4.1 4.2
4.3
4.4
Negative Output SuperLift LuoConverters Introduction Main Series 4.2.1 Elementary Circuit 4.2.2 N/O ReLift Circuit 4.2.3 N/O TripleLift Circuit 4.2.4 N/O Higher Order Lift Circuit Additional Series 4.3.1 N/O Elementary Additional Circuit 4.3.2 N/O ReLift Additional Circuit 4.3.3 N/O TripleLift Additional Circuit 4.3.4 N/O Higher Order Lift Additional Circuit Enhanced Series 4.4.1 N/O Elementary Enhanced Circuit 4.4.2 N/O ReLift Enhanced Circuit 4.4.3 N/O TripleLift Enhanced Circuit 4.4.4 N/O Higher Order Lift Enhanced Circuit
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4.5
ReEnhanced Series 4.5.1 N/O Elementary ReEnhanced Circuit 4.5.2 N/O ReLift ReEnhanced Circuit 4.5.3 N/O TripleLift ReEnhanced Circuit 4.5.4 N/O Higher Order Lift ReEnhanced Circuit 4.6 MultipleEnhanced Series 4.6.1 N/O Elementary MultipleEnhanced Circuit 4.6.2 N/O ReLift MultipleEnhanced Circuit 4.6.3 N/O TripleLift MultipleEnhanced Circuit 4.6.4 N/O Higher Order Lift MultipleEnhanced Circuit 4.7 Summary of Negative Output SuperLift LuoConverters 4.8 Simulation Results 4.8.1 Simulation Results of a N/O TripleLift Circuit 4.8.2 Simulation Results of a N/O TripleLift Additional Circuit 4.9 Experimental Results 4.9.1 Experimental Results of a N/O TripleLift Circuit 4.9.2 Experimental Results of a N/O TripleLift Additional Circuit 4.9.3 Efficiency Comparison of Simulation and Experimental Results 4.9.4 Transient Process and Stability Analysis Bibliography 5 5.1 5.2
5.3
5.4
5.5
Positive Output Cascade Boost Converters Introduction Main Series 5.2.1 Elementary Boost Circuit 5.2.2 TwoStage Boost Circuit 5.2.3 ThreeStage Boost Circuit 5.2.4 Higher Stage Boost Circuit Additional Series 5.3.1 Elementary Boost Additional (Double) Circuit 5.3.2 TwoStage Boost Additional Circuit 5.3.3 ThreeStage Boost Additional Circuit 5.3.4 Higher Stage Boost Additional Circuit Double Series 5.4.1 Elementary Double Boost Circuit 5.4.2 TwoStage Double Boost Circuit 5.4.3 ThreeStage Double Boost Circuit 5.4.4 Higher Stage Double Boost Circuit Triple Series 5.5.1 Elementary Triple Boost Circuit 5.5.2 TwoStage Triple Boost Circuit 5.5.3 ThreeStage Triple Boost Circuit 5.5.4 Higher Stage Triple Boost Circuit
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5.6
Multiple Series 5.6.1 Elementary Multiple Boost Circuit 5.6.2 TwoStage Multiple Boost Circuit 5.6.3 ThreeStage Multiple Boost Circuit 5.6.4 Higher Stage Multiple Boost Circuit 5.7 Summary of Positive Output Cascade Boost Converters 5.8 Simulation and Experimental Results 5.8.1 Simulation Results of a ThreeStage Boost Circuit 5.8.2 Experimental Results of a ThreeStage Boost Circuit 5.8.3 Efficiency Comparison of Simulation and Experimental Results 5.8.4 Transient Process Bibliography 6 6.1 6.2
6.3
6.4
6.5
6.6
6.7 6.8
Negative Output Cascade Boost Converters Introduction Main Series 6.2.1 N/O Elementary Boost Circuit 6.2.2 N/O TwoStage Boost Circuit 6.2.3 N/O ThreeStage Boost Circuit 6.2.4 N/O Higher Stage Boost Circuit Additional Series 6.3.1 N/O Elementary Additional Boost Circuit 6.3.2 N/O TwoStage Additional Boost Circuit 6.3.3 N/O ThreeStage Additional Boost Circuit 6.3.4 N/O Higher Stage Additional Boost Circuit Double Series 6.4.1 N/O Elementary Double Boost Circuit 6.4.2 N/O TwoStage Double Boost Circuit 6.4.3 N/O ThreeStage Double Boost Circuit 6.4.4 N/O Higher Stage Double Boost Circuit Triple Series 6.5.1 N/O Elementary Triple Boost Circuit 6.5.2 N/O TwoStage Triple Boost Circuit 6.5.3 N/O ThreeStage Triple Boost Circuit 6.5.4 N/O Higher Stage Triple Boost Circuit Multiple Series 6.6.1 N/O Elementary Multiple Boost Circuit 6.6.2 N/O TwoStage Multiple Boost Circuit 6.6.3 N/O ThreeStage Multiple Boost Circuit 6.6.4 N/O Higher Stage Multiple Boost Circuit Summary of Negative Output Cascade Boost Converters Simulation and Experimental Results 6.8.1 Simulation Results of a ThreeStage Boost Circuit 6.8.2 Experimental Results of a ThreeStage Boost Circuit
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6.8.3
Efficiency Comparison of Simulation and Experimental Results 6.8.4 Transient Process Bibliography 7 7.1 7.2
Multiple Quadrant Operating LuoConverters Introduction Circuit Explanation 7.2.1 Mode A 7.2.2 Mode B 7.2.3 Mode C 7.2.4 Mode D 7.2.5 Summary 7.3 Mode A (Quadrant I Operation) 7.3.1 Circuit Description 7.3.2 Variations of Currents and Voltages 7.3.3 Discontinuous Region 7.4 Mode B (Quadrant II Operation) 7.4.1 Circuit Description 7.4.2 Variations of Currents and Voltages 7.4.3 Discontinuous Region 7.5 Mode C (Quadrant III Operation) 7.5.1 Circuit Description 7.5.2 Variations of Currents and Voltages 7.5.3 Discontinuous Region 7.6 Mode D (Quadrant IV Operation) 7.6.1 Circuit Description 7.6.2 Variations of Currents and Voltages 7.6.3 Discontinuous Region 7.7 Simulation Results 7.8 Experimental Results 7.9 Discussion 7.9.1 DiscontinuousConduction Mode 7.9.2 Comparison with the DoubleOutput LuoConverter 7.9.3 Conduction Duty k 7.9.4 Switching Frequency f Bibliography 8 8.1 8.2
Switched Component Converters Introduction A TwoQuadrant SC DC/DC Converter 8.2.1 Circuit Description 8.2.1.1 Mode A 8.2.1.2 Mode B 8.2.2 Mode A (Quadrant I Operation)
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8.2.3 8.2.4 8.2.5
Mode B (Quadrant II Operation) Experimental Results Discussion 8.2.5.1 Efficiency 8.2.5.2 Conduction Duty k 8.2.5.3 Switching Frequency f 8.3 FourQuadrant Switched Capacitor DC/DC LuoConverter 8.3.1 Mode A (QI: Forward Motoring) 8.3.1.1 Mode A1: Condition V1 > V2 8.3.1.2 Mode A2: Condition V1 < V2 8.3.1.3 Experimental Results 8.3.2 Mode B (QII: Forward Regenerative Braking) 8.3.2.1 Mode B1: Condition V1 > V2 8.3.2.2 Mode B2: Condition V1 < V2 8.3.3 Mode C (QIII: Reverse Motoring) 8.3.4 Mode D (QIV: Reverse Regenerative Braking) 8.4 Switched Inductor FourQuadrant DC/DC LuoConverter 8.4.1 Mode A (QI: Forward Motoring) 8.4.1.1 Continuous Mode 8.4.1.2 Discontinuous Mode 8.4.2 Mode B (QII: Forward Regenerative Braking) 8.4.2.1 Continuous Mode 8.4.2.2 Discontinuous Mode 8.4.3 Mode C (QIII: Reverse Motoring) 8.4.3.1 Continuous Mode 8.4.3.2 Discontinuous Mode 8.4.4 Mode D (QIV: Reverse Regenerative Braking) 8.4.4.1 Continuous Mode 8.4.4.2 Discontinuous Mode 8.4.5 Experimental Results Bibliography 9 9.1 9.2
9.3
Positive Output MultipleLift PushPull SwitchedCapacitor LuoConverters Introduction Main Series 9.2.1 Elementary Circuit 9.2.2 ReLift Circuit 9.2.3 TripleLift Circuit 9.2.4 Higher Order Lift Circuit Additional Series 9.3.1 Elementary Additional Circuit 9.3.2 ReLift Additional Circuit 9.3.3 TripleLift Additional Circuit 9.3.4 Higher Order Lift Additional Circuit
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9.4
Enhanced Series 9.4.1 Elementary Enhanced Circuit 9.4.2 ReLift Enhanced Circuit 9.4.3 TripleLift Enhanced Circuit 9.4.4 Higher Order Enhanced Lift Circuit 9.5 ReEnhanced Series 9.5.1 Elementary ReEnhanced Circuit 9.5.2 ReLift ReEnhanced Circuit 9.5.3 TripleLift ReEnhanced Circuit 9.5.4 Higher Order Lift ReEnhanced Circuit 9.6 MultipleEnhanced Series 9.6.1 Elementary MultipleEnhanced Circuit 9.6.2 ReLift MultipleEnhanced Circuit 9.6.3 TripleLift MultipleEnhanced Circuit 9.6.4 Higher Order Lift MultipleEnhanced Circuit 9.7 Theoretical Analysis 9.8 Summary of This Technique 9.9 Simulation Results 9.9.1 A TripleLift Circuit 9.9.2 A TripleLift Additional Circuit 9.10 Experimental Results 9.10.1 A TripleLift Circuit 9.10.2 A TripleLift Additional Circuit Bibliography 10 10.1 10.2
10.3
10.4
10.5
Negative Output MultipleLift PushPull SwitchedCapacitor LuoConverters Introduction Main Series 10.2.1 N/O Elementary Circuit 10.2.2 N/O ReLift Circuit 10.2.3 N/O TripleLift Circuit 10.2.4 N/O Higher Order Lift Circuit Additional Series 10.3.1 N/O Elementary Additional Circuit 10.3.2 N/O ReLift Additional Circuit 10.3.3 N/O TripleLift Additional Circuit 10.3.4 N/O Higher Order Lift Additional Circuit Enhanced Series 10.4.1 N/O Elementary Enhanced Circuit 10.4.2 N/O ReLift Enhanced Circuit 10.4.3 N/O TripleLift Enhanced Circuit 10.4.4 N/O Higher Order Lift Enhanced Circuit ReEnhanced Series 10.5.1 N/O Elementary ReEnhanced Circuit 10.5.2 N/O ReLift ReEnhanced Circuit
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10.5.3 N/O TripleLift ReEnhanced Circuit 10.5.4 N/O Higher Order Lift ReEnhanced Circuit 10.6 MultipleEnhanced Series 10.6.1 N/O Elementary MultipleEnhanced Circuit 10.6.2 N/O ReLift MultipleEnhanced Circuit 10.6.3 N/O TripleLift MultipleEnhanced Circuit 10.6.4 N/O Higher Order Lift MultipleEnhanced Circuit 10.7 Summary of This Technique 10.8 Simulation and Experimental Results 10.8.1 Simulation Results 10.8.2 Experimental Results Bibliography 11 MultipleQuadrant SoftSwitch Converters 11.1 Introduction 11.2 MultipleQuadrant DC/DC ZCS QuasiResonant LuoConverters 11.2.1 Mode A 11.2.1.1 Interval t = 0 to t1 11.2.1.2 Interval t = t1 to t2 11.2.1.3 Interval t = t2 to t3 11.2.1.4 Interval t = t3 to t4 11.2.2 Mode B 11.2.2.1 Interval t = 0 to t1 11.2.2.2 Interval t = t1 to t2 11.2.2.3 Interval t = t2 to t3 11.2.2.4 Interval t = t3 to t4 11.2.3 Mode C 11.2.3.1 Interval t = 0 to t1 11.2.3.2 Interval t = t1 to t2 11.2.3.3 Interval t = t2 to t3 11.2.3.4 Interval t = t3 to t4 11.2.4 Mode D 11.2.4.1 Interval t = 0 to t1 11.2.4.2 Interval t = t1 to t2 11.2.4.3 Interval t = t2 to t3 11.2.4.4 Interval t = t3 to t4 11.2.5 Experimental Results 11.3 MultipleQuadrant DC/DC ZVS Quasi Resonant LuoConverter 11.3.1 Mode A 11.3.1.1 Interval t = 0 to t1 11.3.1.2 Interval t = t1 to t2 11.3.1.3 Interval t = t2 to t3 11.3.1.4 Interval t = t3 to t4 © 2004 by CRC Press LLC
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11.3.2 Mode B 11.3.2.1 Interval t = 0 to t1 11.3.2.2 Interval t = t1 to t2 11.3.2.3 Interval t = t2 to t3 11.3.2.4 Interval t = t3 to t4 11.3.3 Mode C 11.3.3.1 Interval t = 0 to t1 11.3.3.2 Interval t = t1 to t2 11.3.3.3 Interval t = t2 to t3 11.3.3.4 Interval t = t3 to t4 11.3.4 Mode D 11.3.4.1 Interval t = 0 to t1 11.3.4.2 Interval t = t1 to t2 11.3.4.3 Interval t = t2 to t3 11.3.4.4 Interval t = t3 to t4 11.3.5 Experimental Results 11.4 MultipleQuadrant ZeroTransition DC/DC LuoConverters 11.4.1 Mode A (Quadrant I Operation) 11.4.2 Mode B (Quadrant II Operation) 11.4.3 Mode C (Quadrant III Operation) 11.4.4 Mode D (Quadrant IV Operation) 11.4.5 Simulation Results 11.4.6 Experimental Results 11.4.7 Design Considerations Bibliography 12 Synchronous Rectifier DC/DC Converters 12.1 Introduction 12.2 Flat Transformer Synchronous Rectifier LuoConverter 12.2.1 Transformer Is in Magnetizing Process 12.2.2 SwitchingOn 12.2.3 Transformer Is in Demagnetizing Process 12.2.4 SwitchingOff 12.2.5 Summary 12.3 Active Clamped Synchronous Rectifier LuoConverter 12.3.1 Transformer Is in Magnetizing 12.3.2 SwitchingOn 12.3.3 Transformer Is in Demagnetizing 12.3.4 SwitchingOff 12.3.5 Summary 12.4 Double Current Synchronous Rectifier LuoConverter 12.4.1 Transformer Is in Magnetizing 12.4.2 SwitchingOn 12.4.3 Transformer Is in Demagnetizing © 2004 by CRC Press LLC
1956_C00.fm Page xxv Thursday, August 21, 2003 4:25 PM
12.4.4 SwitchingOff 12.4.5 Summary 12.5 ZeroCurrentSwitching Synchronous Rectifier LuoConverter 12.5.1 Transformer Is in Magnetizing 12.5.2 Resonant Period 12.5.3 Transformer Is in Demagnetizing 12.5.4 SwitchingOff 12.5.5 Summary 12.6 ZeroVoltageSwitching Synchronous Rectifier LuoConverter 12.6.1 Transformer Is in Magnetizing 12.6.2 Resonant Period 12.6.3 Transformer Is in Demagnetizing 12.6.4 SwitchingOff 12.6.5 Summary Bibliography 13
Multiple EnergyStorage Element Resonant Power Converters 13.1 Introduction 13.1.1 TwoElement RPC 13.1.2 ThreeElement RPC 13.1.3 FourElement RPC 13.2 Bipolar Current and Voltage Source 13.2.1 Bipolar Voltage Source 13.2.1.1 Two Voltage Source Circuit 13.2.1.2 One Voltage Source Circuit 13.2.2 Bipolar Current Source 13.2.2.1 Two Voltage Source Circuit 13.2.2.2 One Voltage Source Circuit 13.3 A TwoElement RPC Analysis 13.3.1 Input Impedance 13.3.2 Current Transfer Gain 13.3.3 Operation Analysis 13.3.4 Simulation Results 13.3.5 Experimental Results Bibliography 14 Π CLL Current Source Resonant Inverter 14.1 Introduction 14.1.1 Pump Circuits 14.1.2 Current Source 14.1.3 Resonant Circuit 14.1.4 Load 14.1.5 Summary © 2004 by CRC Press LLC
1956_C00.fm Page xxvi Thursday, August 21, 2003 4:25 PM
14.2 Mathematic Analysis 14.2.1 Input Impedance 14.2.2 Components’ Voltages and Currents 14.2.3 Simplified Impedance and Current Gain 14.2.4 Power Transfer Efficiency 14.3 Simulation Results 14.4 Discussion 14.4.1 Function of the ΠCLL Circuit 14.4.2 Applying Frequency to this ΠCLL CSRI 14.4.3 Explanation of g > 1 14.4.4 DC Current Component Remaining 14.4.5 Efficiency Bibliography 15 Cascade Double Γ CL Current Source Resonant Inverter 15.1 Introduction 15.2 Mathematic Analysis 15.2.1 Input Impedance 15.2.2 Components, Voltages, and Currents 15.2.3 Simplified Impedance and Current Gain 15.2.4 Power Transfer Efficiency 15.3 Simulation Result 15.3.1 β = 1, f = 33.9 kHz, T = 29.5 µs 15.3.2 β = 1.4142, f = 48.0 kHz, T = 20.83 µs 15.3.3 β = 1.59, f = 54 kHz, T = 18.52 µs 15.4 Experimental Result 15.5 Discussion 15.5.1 Function of the Double ΓCL Circuit 15.5.2 Applying Frequency to this Double ΓCL CSRI 15.5.3 Explanation of g > 1 Bibliography 16 Cascade Reverse Double Γ LC Resonant Power Converter 16.1 Introduction 16.2 SteadyState Analysis of Cascade Reverse Double ΓLC RPC 16.2.1 Topology and Circuit Description 16.2.2 Classical Analysis on AC Side 16.2.2.1 Basic Operating Principles 16.2.2.2 Equivalent Load Resistance 16.2.2.3 Equivalent AC Circuit and Transfer Functions 16.2.2.4 Analysis of Voltage Transfer Gain and the Input Impedance 16.2.3 Simulation and Experimental Results 16.2.3.1 Simulation Studies 16.2.3.2 Experimental Results © 2004 by CRC Press LLC
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16.3 Resonance Operation and Modeling 16.3.1 Operating Principle, Operating Modes and Equivalent Circuits 16.3.2 StateSpace Analysis 16.4 SmallSignal Modeling of Cascade Reverse Double ΓLC RPC 16.4.1 SmallSignal Modeling 16.4.1.1 Model Diagram 16.4.1.2 Nonlinear State Equation 16.4.1.3 Harmonic Approximation 16.4.1.4 Extended Describing Function 16.4.1.5 Harmonic Balance 16.4.1.6 Perturbation and Linearization 16.4.1.7 Equivalent Circuit Model 16.4.2 ClosedLoop System Design 16.5 Discussion 16.5.1 Characteristics of VariableParameter Resonant Converter 16.5.2 Discontinuous Conduction Mode (DCM) Bibliography Appendix: Parameters Used in SmallSignal Modeling 17 DC Energy Sources for DC/DC Converters 17.1 Introduction 17.2 SinglePhase HalfWave Diode Rectifier 17.2.1 Resistive Load 17.2.2 Inductive Load 17.2.3 Pure Inductive Load 17.2.4 Back EMF Plus Resistor Load 17.2.5 Back EMF Plus Inductor Load 17.3 SinglePhase Bridge Diode Rectifier 17.3.1 Resistive Load 17.3.2 Back EMF Load 17.3.3 Capacitive Load 17.4 ThreePhase HalfBridge Diode Rectifier 17.4.1 Resistive Load 17.4.2 Back EMF Load (0.5 2Vin < E < 2Vin) 17.4.3 Back EMF Load (E < 0.5 2Vin) 17.5 ThreePhase FullBridge Diode Rectifier with Resistive Load 17.6 Thyristor Rectifiers 17.6.1 SinglePhase HalfWave Rectifier with Resistive Load 17.6.2 SinglePhase HalfWave Thyristor Rectifier with Inductive Load 17.6.3 SinglePhase HalfWave Thyristor Rectifier with Pure Inductive Load © 2004 by CRC Press LLC
1956_C00.fm Page xxviii Thursday, August 21, 2003 4:25 PM
17.6.4
SinglePhase HalfWave Rectifier with Back EMF Plus Resistive Load 17.6.5 SinglePhase HalfWave Rectifier with Back EMF Plus Inductive Load 17.6.6 SinglePhase HalfWave Rectifier with Back EMF Plus Pure Inductor 17.6.7 SinglePhase FullWave Semicontrolled Rectifier with Inductive Load 17.6.8 SinglePhase FullControlled Rectifier with Inductive Load 17.6.9 ThreePhase HalfWave Rectifier with Resistive Load 17.6.10 ThreePhase HalfWave Thyristor Rectifier with Inductive Load 17.6.11 ThreePhase FullWave Thyristor Rectifier with Resistive Load. 17.6.12 ThreePhase FullWave Thyristor Rectifier with Inductive Load Bibliography 18
Control Circuit: EMI and Application Examples of DC/DC Converters 18.1 Introduction 18.2 LuoResonator 18.2.1 Circuit Explanation 18.2.2 Calculation Formulae 18.2.3 A Design Example 18.2.4 Discussion 18.3 EMI, EMS and EMC 18.3.1 EMI/EMC Analysis 18.3.2 Comparison to HardSwitching and SoftSwitching 18.3.3 Measuring Method and Results 18.3.4 Designing Rule to Minimize EMI/EMC 18.4 Some DC/DC Converter Applications 18.4.1 A 5000 V Insulation Test Bench 18.4.2 MIT 42/14 V 3 KW DC/DC Converter 18.4.3 IBM 1.8 V/200 A Power Supply Bibliography
© 2004 by CRC Press LLC
1956_C01.fm Page 1 Monday, August 18, 2003 3:36 PM
1 Introduction
Conversion technique is a major research area in the field of power electronics. The equipment for conversion techniques have applications in industry, research and development, government organizations, and daily life. The equipment can be divided in four technologies: • • • •
AC/AC AC/DC DC/DC DC/AC
transformers rectifiers converters inverters
According to incomplete statistics, there have been more than 500 prototypes of DC/DC converters developed in the past six decades. All existing DC/DC converters were designed to meet the requirements of certain applications. They are usually called by their function, for example, Buck converter, Boost converter and BuckBoost converter, and zero current switching (ZCS) and zero voltage switching (ZVS) converters. The large number of DC/DC converters had not been evolutionarily classified until 2001. The authors have systematically classified the types of converters into six generations according to their characteristics and development sequence. This classification grades all DC/DC converters and categorizes new prototypes. Since 2001, the DC/DC converter family tree has been built and this classification has been recognized worldwide. Following this principle, it is now easy to sort and allocate DC/DC converters and assess their technical features.
1.1
Historical Review
DC/DC conversion technology is a major subject area in the field of power engineering and drives, and has been under development for six decades. DC/DC converters are widely used in industrial applications and computer hardware circuits. DC/DC conversion techniques have developed very
© 2003 by CRC Press LLC
1956_C01.fm Page 2 Monday, August 18, 2003 3:36 PM
quickly. Statistics show that the DC/DC converter worldwide market will grow from U.S. $3336 million in 1995 to U.S. $5128 million in the year 2004 with a compound annual growth rate (CAGR) of 9%.* This compares to the AC/DC power supply market, which will have a CAGR of only about 7.5% during the same period. In addition to its higher growth rate, the DC/DC converter market is undergoing dramatic changes as a result of two major trends in the electronics industry: low voltage and high power density. From this investigation it can be seen that the production of DC/DC converters in the world market is much higher than that of AC/DC converters. The DC/DC conversion technique was established in the 1920s. A simple voltage conversion, the simplest DC/DC converter is a voltage divider (such as rheostat, potential–meter, and so on), but it only transfers output voltage lower than input voltage with poor efficiency. The multiplequadrant chopper is the second step in DC/DC conversion. Much time has been spent trying to find equipment to convert the DC energy source of one voltage to another DC actuator with another voltage, as does a transformer employed in AC/AC conversion. Some preliminary types of DC/DC converters were used in industrial applications before the Second World War. Research was blocked during the war, but applications of DC/DC converters were recognized. After the war, communication technology developed very rapidly and required low voltage DC power supplies. This resulted in the rapid development of DC/DC conversion techniques. Preliminary prototypes can be derived from choppers.
1.2
MultipleQuadrant Choppers
Choppers are the circuits that convert fixed DC voltage to variable DC voltage or pulsewidth–modulated (PWM) AC voltage. In this book, we concentrate on its first function.
1.2.1
MultipleQuadrant Operation
A DC motor can run in forward running or reverse running. During the forward starting process its armature voltage and armature current are both positive. We usually call this forward motoring operation or quadrant I operation. During the forward braking process its armature voltage is still positive and its armature current is negative. This state is called the forward regenerating operation or quadrant II operation. Analogously, during the reverse starting process the DC motor armature voltage and current are both negative. This reverse motoring operation is called the quadrant III operation. * Figures are taken from the Darnell Group News report on DCDC Converters: Global Market Forecasts, Demand Characteristics and Competitive Environment published in February 2000. © 2003 by CRC Press LLC
1956_C01.fm Page 3 Monday, August 18, 2003 3:36 PM
V Quadrant II Forward Regenerating
Quadrant I Forward Motoring
I Quadrant III Reverse Motoring
Quadrant IV Reverse Regenerating
FIGURE 1.1 Fourquadrant operation.
During reverse braking process its armature voltage is still negative and its armature current is positive. This state is called the reverse regenerating operation quadrant IV operation. Referring to the DC motor operation states; we can define the multiplequadrant operation as below: Quadrant I operation: forward motoring, voltage is positive, current is positive Quadrant II operation: forward regenerating, voltage is positive, current is negative Quadrant III operation: reverse motoring, voltage is negative, current is negative Quadrant IV operation: reverse regenerating, voltage is negative, current is positive The operation status is shown in the Figure 1.1. Choppers can convert a fixed DC voltage into various other voltages. The corresponding chopper is usually named according to its quadrant operation chopper, e.g., the firstquadrant chopper or “A”type chopper. In the following description we use the symbols Vin as the fixed voltage, Vp the chopped voltage, and VO the output voltage.
1.2.2
The FirstQuadrant Chopper
The firstquadrant chopper is also called “A”type chopper and its circuit diagram is shown in Figure 1.2a and corresponding waveforms are shown in Figure 1.2b. The switch S can be some semiconductor devices such as BJT, IGBT, and MOSFET. Assuming all parts are ideal components, the output voltage is calculated by the formula, VO = © 2003 by CRC Press LLC
ton V = kVin T in
(1.1)
1956_C01.fm Page 4 Monday, August 18, 2003 3:36 PM
S VIN
+
iO

+ VP
D
L
+ C
Vo
R


(a) Circuit Diagram
VIN
t VP VO tON
T
t
kT
T
t
VO
(b) Voltage Waveforms FIGURE 1.2 The firstquadrant chopper.
where T is the repeating period T = 1/f, f is the chopping frequency, ton is the switchon time, k is the conduction duty cycle k = ton/T. 1.2.3
The SecondQuadrant Chopper
The secondquadrant chopper is the called “B”type chopper and the circuit diagram and corresponding waveforms are shown in Figure 1.3a and b. The The output voltage can be calculated by the formula, VO = © 2003 by CRC Press LLC
toff T
Vin = (1 − k )Vin
(1.2)
1956_C01.fm Page 5 Monday, August 18, 2003 3:36 PM
+
D L
I
VIN S
+ VP
+ C

Vo 
(a) Circuit Diagram
VIN
t VP VO tON
T
t
kT
T
t
VO
(b) Voltage Waveforms FIGURE 1.3 The secondquadrant chopper.
where T is the repeating period T = 1/f, f is the chopping frequency, toff is the switchoff time toff = T – ton, and k is the conduction duty cycle k = ton/T. 1.2.4
The ThirdQuadrant Chopper
The thirdquadrant chopper and corresponding waveforms are shown in Figure 1.4a and b. All voltage polarity is defined in the figure. The output voltage (absolute value) can be calculated by the formula, VO = © 2003 by CRC Press LLC
ton V = kVin T in
(1.3)
1956_C01.fm Page 6 Monday, August 18, 2003 3:36 PM
–
S
iO
VIN +
+ D
VP
–
L C
Vo
R
–
+
(a) Circuit Diagram
VIN
t VP
tON
T
t
kT
T
t
VO
(b) Voltage Waveforms FIGURE 1.4 The thirdquadrant chopper.
where ton is the switchon time, and k is the conduction duty cycle k = ton/T. 1.2.5
The FourthQuadrant Chopper
The fourthquadrant chopper and corresponding waveforms are shown in Figure 1.5a and b. All voltage polarity is defined in the figure. The output voltage (absolute value) can be calculated by the formula, VO =
toff T
Vin = (1 − k )Vin
(1.4)
where toff is the switchoff time toff = T – ton, time, and k is the conduction duty cycle k = ton/T. © 2003 by CRC Press LLC
1956_C01.fm Page 7 Monday, August 18, 2003 3:36 PM
D L
VIN – + S
+ VP
I – C
–
Vo +
(a) Circuit Diagram
VIN
t VP
VO tON
T
t
kT
T
t
VO
(b) Voltage Waveforms FIGURE 1.5 The fourthquadrant chopper.
1.2.6
The First and Second Quadrant Chopper
The first and second quadrant chopper is shown in Figure 1.6. Dual quadrant operation is usually requested in the system with two voltage sources V1 and V2. Assume that the condition V1 > V2, and the inductor L is an ideal component. During quadrant I operation, S1 and D2 work, and S2 and D1 are idle. Vice versa, during quadrant II operation, S2 and D1 work, and S1 and D2 are idle. The relation between the two voltage sources can be calculated by the formula, kV1 V2 = (1 − k )V1 © 2003 by CRC Press LLC
QI _ operation QII _ operation
(1.5)
1956_C01.fm Page 8 Monday, August 18, 2003 3:36 PM
D2
S1
+ VI
L
–
+
+ D1
S2
VP
–
V2
–
FIGURE 1.6 The firstsecond quadrant chopper.
D2
S1 L
VI
+
+ D1
S2
VP
+
V2
FIGURE 1.7 The thirdfourth quadrant chopper.
where k is the conduction duty cycle k = ton/T. 1.2.7
The Third and Fourth Quadrant Chopper
The third and fourth quadrant chopper is shown in Figure 1.7. Dual quadrant operation is usually requested in the system with two voltage sources V1 and V2. Both voltage polarity is defined in the figure, we just concentrate their absolute values in analysis and calculation. Assume that the condition V1 > V2, the inductor L is ideal component. During quadrant I operation, S1 and D2 work, and S2 and D1 are idle. Vice versa, during quadrant II operation, S2 and D1 work, and S1 and D2 are idle. The relation between the two voltage sources can be calculated by the formula, kV1 V2 = (1 − k )V1
QIII _ operation QIV _ operation
where k is the conduction duty cycle k = ton/T. © 2003 by CRC Press LLC
(1.6)
1956_C01.fm Page 9 Monday, August 18, 2003 3:36 PM
D1
S1
+ VI
V2
L
D3
S3
D4
S4
– D2
S2
FIGURE 1.8 The fourquadrant chopper.
TABLE 1.1 The Switches and Diode’s Status for FourQuadrant Operation Switch or Diode
Quadrant I
Quadrant II
Quadrant III
Quadrant IV
S1 D1 S2 D2 S3 D3 S4 D4 Output
Works Idle Idle Works Idle Idle On Idle V2 +, I2 +
Idle Works Works Idle Idle Idle Idle On V2 +, I2 –
Idle Works Works Idle On Idle Idle Idle V2 –, I2 –
Works Idle Idle Works Idle On Idle Idle V2 –, I2 +
1.2.8
The FourQuadrant Chopper
The fourquadrant chopper is shown in Figure 1.8. The input voltage is positive, output voltage can be either positive or negative. The switches and diode status for the operation are shown in Table 1.1. The output voltage can be calculated by the formula, kV1 (1 − k )V 1 V2 = − kV 1 −(1 − k )V1
1.3
QI _ operation QII _ operation QIII _ operation QIV _ operation
(1.7)
Pump Circuits
The electronic pump is a major component of all DC/DC converters. Historically, they can be sorted into four groups: © 2003 by CRC Press LLC
1956_C01.fm Page 10 Monday, August 18, 2003 3:36 PM
• • • •
Fundamental pumps Developed pumps Transformertype pumps Superlift pumps
1.3.1
Fundamental Pumps
Fundamental pumps are developed from fundamental DC/DC converters just like their name: • Buck pump • Boost pump • Buckboost pump All fundamental pumps consist of three components: a switch S, a diode D, and an inductor L. 1.3.1.1 Buck Pump The circuit diagram of the buck pump, and some current waveforms are shown in Figure 1.9. Switch S and diode D are alternately on and off. Usually, the buck pump works in continuous operation mode, inductor current is continuous in this case. 1.3.1.2 Boost Pump The circuit diagram of the boost pump, and some current waveforms are shown in Figure 1.10. Switch S and diode D are alternately on and off. The inductor current is usually continuous. 1.3.1.3 BuckBoost Pump The circuit diagram of the buckboost pump and some current waveforms are shown in Figure 1.11. Switch S and diode D are alternately on and off. Usually, the buckboost pump works in continuous operation mode, inductor current is continuous in this case. 1.3.2
Developed Pumps
Developed pumps are created from the developed DC/DC converters just like their name: • Positive Luopump • Negative Luopump • Cúkpump © 2003 by CRC Press LLC
1956_C01.fm Page 11 Monday, August 18, 2003 3:36 PM
i1
L
S
i2
+
+
V1
D
R
V2
_
_
i1
0
kT
T
t
kT
T
t
L
D
i2
0
FIGURE 1.9 Buck pump.
i1
i2
+
+
V1
R
V2
S
_
_
i1
0
kT
T
t
T
t
i2
0
FIGURE 1.10 Boost pump. © 2003 by CRC Press LLC
kT
1956_C01.fm Page 12 Monday, August 18, 2003 3:36 PM
i1
i2 S
D
+
–
V1
L
R
V2
–
+
i1
0
kT
T
t
T
t
i2
0
kT
FIGURE 1.11 Buckboost pump.
All developed pumps consist of four components: a switch S, a diode D, a capacitor C, and an inductor L. 1.3.2.1 Positive LuoPump The circuit diagram of the positive Luopump and some current and voltage waveforms are shown in Figure 1.12. Switch S and diode D are alternately on and off. Usually, this pump works in continuous operation mode, inductor current is continuous in this case. The output terminal voltage and current is usually positive. 1.3.2.2 Negative LuoPump The circuit diagram of the negative Luopump and some current and voltage waveforms are shown in Figure 1.13. Switch S and diode D are alternately on and off. Usually, this pump works in continuous operation mode, inductor current is continuous in this case. The output terminal voltage and current is usually negative. 1.3.2.3 CúkPump The circuit diagram of the Cúk pump and some current and voltage waveforms are shown in Figure 1.14. Switch S and diode D are alternately on and off. Usually, the Cúk pump works in continuous operation mode, inductor current is continuous in this case. The output terminal voltage and current is usually negative. © 2003 by CRC Press LLC
1956_C01.fm Page 13 Monday, August 18, 2003 3:36 PM
i2 i1
S
C
+
_
L
V1
D
R
V2
_
+
i1
0
kT
T
t
i2
0
kT
t
T
FIGURE 1.12 Positive Luopump.
i1
S D
i2
+
L
V1
C
_
R
V2
_
+
i1
0
kT
T
t
i2
0
FIGURE 1.13 Negative Luopump. © 2003 by CRC Press LLC
kT
T
t
1956_C01.fm Page 14 Monday, August 18, 2003 3:36 PM
i1
i2
L
C +
+
V1
D
R
V2
S
_
_
i1
0
kT
T
t
i2
0
kT
T
t
FIGURE 1.14 Cúkpump.
1.3.3
TransformerType Pumps
Transformertype pumps are developed from transformertype DC/DC converters just like their name: • Forward pump • FlyBack pump • ZETA pump All transformertype pumps consist of a switch S, a transformer with the turn ratio N and other components such as diode D (one or more) and capacitor C. 1.3.3.1 Forward Pump The circuit diagram of the forward pump and some current waveforms are shown in Figure 1.15. Switch S and diode D1 are synchronously on and off, and diode D2 is alternately off and on. Usually, the forward pump works in discontinuous operation mode, input current is discontinuous in this case. 1.3.3.2 FlyBack Pump The circuit diagram of the flyback pump and some current waveforms are in Figure 1.16. Since the primary and secondary windings of the transformer © 2003 by CRC Press LLC
1956_C01.fm Page 15 Monday, August 18, 2003 3:36 PM
+
i1
1:N
i2
D1
+ D2
R
Vo
V in
– Control
S
– i1
0
kT
T
t
i2
0
kT
T
t
FIGURE 1.15 Forward pump.
are purposely arranged in inverse polarities, switch S and diode D are alternately on and off. Usually, the flyback pump works in discontinuous operation mode, input current is discontinuous in this case. 1.3.3.3 ZETA Pump The circuit diagram of the ZETA pump and some current waveforms are shown in Figure 1.17. Switch S and diode D are alternately on and off. Usually, the ZETA pump works in discontinuous operation mode, input current is discontinuous in this case.
1.3.4
SuperLift Pumps
Superlift pumps are developed from superlift DC/DC converters: • • • • •
Positive super Luopump Negative super Luopump Positive pushpull pump Negative pushpull pump Double/Enhanced circuit (DEC)
All superlift pumps consist of switches, diodes, capacitors, and sometimes an inductor. © 2003 by CRC Press LLC
1956_C01.fm Page 16 Monday, August 18, 2003 3:36 PM
i1
i2
1:N
+
+
D N1
N2
C
R
Vo
V in
_ Control
T1
i1
0
kT
T
t
i2
0
kT
T
t
FIGURE 1.16 Flyback pump.
1.3.4.1 Positive Super LuoPump The circuit diagram of the positive superlift pump and some current waveforms are shown in Figure 1.18. Switch S and diode D1 are synchronously on and off, but diode D2 is alternately off and on. Usually, the positive superlift pump works in continuous conduction mode (CCM), inductor current is continuous in this case. 1.3.4.2 Negative Super LuoPump The circuit diagram of the negative superlift pump and some current waveforms are shown in Figure 1.19. Switch S and diode D1 are synchronously on and off, but diode D2 is alternately off and on. Usually, the negative superlift pump works in CCM, but input current is discontinuous in this case. 1.3.4.3 Positive PushPull Pump All pushpull pumps consist of two switches without any inductor. They can be employed in multiplelift switched capacitor converters. The circuit diagram of positive pushpull pump and some current waveforms are shown in Figure 1.20. Since there is no inductor in the pump, it is applied in © 2003 by CRC Press LLC
1956_C01.fm Page 17 Monday, August 18, 2003 3:36 PM
L i1
. .
i2
1:N
+ Vin
C
R D
S
+ Vo _
_
i1
0
kT
T
t
i2
0
kT
T
t
FIGURE 1.17 ZETA pump.
switchedcapacitor converters. The main switch S and diode D1 are synchronously on and off, but the slave switch S1 and diode D2 are alternately off and on. Usually, the positive pushpull pump works in pushpull state continuous operation mode. 1.3.4.4 Negative PushPull Pump The circuit diagram of this pushpull pump and some current waveforms are shown in Figure 1.21. Since there is no inductor in the pump, it is often used in switchedcapacitor converters. The main switch S and diode D are synchronously on and off, but the slave switch S1 is alternately off and on. Usually, the superlift pump works in pushpull state continuous operation mode, inductor current is continuous in this case. 1.3.4.5 Double/Enhanced Circuit (DEC) The circuit diagram of the double/enhanced circuit and some current waveforms are in Figure 1.22. The switch is the only other existing circuit part. This circuit is usually applied in lift, superlift, and pushpull converters. These two diodes are alternately on and off, so that two capacitors are alternately charging and discharging. Usually, this circuit can enhance the voltage doubly or at certain times. © 2003 by CRC Press LLC
1956_C01.fm Page 18 Monday, August 18, 2003 3:36 PM
Iin
D1
D2 IC1
+ L1
C1
+ VC1 –
Vin
+ C2
+
VC2 –
S
R
VO –
–
iin
0
kT
T
t
iC1
0
kT
T
t
FIGURE 1.18 Positive super Luopump.
1.4
Development of DC/DC Conversion Technique
According to incomplete statistics, there are more than 500 existing prototypes of DC/DC converters. The main purpose of this book is to catorgorize all existing prototypes of DC/DC converters. This job is of vital importance for future development of DC/DC conversion techniques. The authors have devoted 20 years to this subject area, their work has been recognized and assessed by experts worldwide. The authors classify all existing prototypes of DC/DC converters into six generations. They are • • • • • •
First generation (classical/traditional) converters Second generation (multiquadrant) converters Third generation (switchedcomponent SI/SC) converters Fourth generation (softswitching: ZCS/ZVS/ZT) converters Fifth generation (synchronous rectifier SR) converters Sixth generation (multiple energystorage elements resonant MER) converters
© 2003 by CRC Press LLC
1956_C01.fm Page 19 Monday, August 18, 2003 3:36 PM
IC1
Iin S
+
L1
+ VC1 –
C1
–
Vin
– D1
D2
R
VC2
C2
VO +
+
–
iin
0
kT
Tt
t
iC1
0
kT
T
t
FIGURE 1.19 Negative super Luopump.
1.4.1
The First Generation Converters
The firstgeneration converters perform in a single quadrant mode and in low power range (up to around 100 W). Since its development lasts a long time, it has, briefly, five categories: • • • • •
Fundamental converters Transformertype converters Developed converters Voltagelift converters Superlift converters
1.4.1.1 Fundamental Converters Three types of fundamental DC/DC classifications were constructed, these are buck converter, boost converter, and buckboost converter. They can be derived from single quadrant operation choppers. For example, the buck converter was derived from an Atype chopper. These converters have two main problems: linkage between input and output and very large output voltage ripple. © 2003 by CRC Press LLC
1956_C01.fm Page 20 Monday, August 18, 2003 3:36 PM
I in
D1
D2 I C1
+
+ S1
C1
V C1 –
V in
+ C2
+
V C2 –
S
R
VO –
–
i in
0
kT
T
t
i C1
0
kT
T
t
FIGURE 1.20 Positive pushpull pump.
1.4.1.1.1 Buck Converter The buck converter is a stepdown DC/DC converter. It works in firstquadrant operation. It can be derived from a quadrant I chopper. Its circuit diagram, and switchon and off equivalent circuit are shown in Figure 1.23. The output voltage is calculated by the formula, VO =
ton V = kVin T in
(1.8)
where T is the repeating period T = 1/f, f is the chopping frequency, ton is the switchon time, and k is the conduction duty cycle k = ton/T. 1.4.1.1.2 Boost Converter The boost converter is a stepup DC/DC converter. It works in secondquadrant operation. It can be derived from quadrant II chopper. Its circuit diagram, and switchon and off equivalent circuit are shown in Figure 1.24. The output voltage is calculated by the formula, VO = © 2003 by CRC Press LLC
1 T Vin = V 1 − k in T − ton
(1.9)
1956_C01.fm Page 21 Monday, August 18, 2003 3:36 PM
I C1
I in S
+
+ C1
S1
V C1 
V in
D1
D2
R
V C2
C2
VO +
+

i in
0
kT
T
t
i C1
0
kT
t
T
FIGURE 1.21 Negative pushpull pump.
D1
D2 I C1
I C2
+ C1
V C1 –
S
+ C2
V C2 –
FIGURE 1.22 Double/enhanced circuit (DEC).
where T is the repeating period T = 1/f, f is the chopping frequency, ton is the switchon time, k is the conduction duty cycle k = ton/T. © 2003 by CRC Press LLC
1956_C01.fm Page 22 Monday, August 18, 2003 3:36 PM
i1
S
+
D 
+
iL

V1
i2
L
+
VC
VD

+
C
R
V2
iC

(a) Circuit diagram
i1
L
i2
+
iL
+
+
VC
V1
R


V2
iC
C

(b) Switchon
L
iL
i2
+
+
VC 
C
R iC
V2 
(c) Switchoff
FIGURE 1.23 Buck converter.
1.4.1.1.3 BuckBoost Converter The buckboost converter is a step down/up DC/DC converter. It works in thirdquadrant operation. Its circuit diagram, switchon and off equivalent circuit, and waveforms are shown in Figure 1.25. The output voltage is calculated by the formula, VO =
ton k Vin = V 1 − k in T − ton
(1.10)
where T is the repeating period T = 1/f, f is the chopping frequency, ton is the switchon time, and k is the conduction duty cycle k = ton/T. By using this converter it is easy to obtain the random output voltage, which can be higher or lower than the input voltage. It provides great convenience for industrial applications. © 2003 by CRC Press LLC
1956_C01.fm Page 23 Monday, August 18, 2003 3:36 PM
i1
L
i2
D VD
+
iL
V1
+
+
VC S
R
–
–
iC
C
V2 –
(a) Circuit diagram
i1
i2
L
+
+
iL
V1
+
VC
R
–
–
iC
C
V2 –
(b) Switch on
i1
+
V1 –
L
i2
+
iL
+
VC –
C
R iC
V2 –
(c) Switch off
FIGURE 1.24 Boost converter.
1.4.1.2 TransformerType Converters Since all fundamental DC/DC converters keep the linkage from input side to output side and the voltage transfer gain is comparably low, transformertype converters were developed in the 1960s to 1980s. There are a large group of converters such as the forward converter, pushpull converter, flyback converter, halfbridge converter, bridge converter, and Zeta (or ZETA) converter. Usually, these converters have high transfer voltage gain and high insulation between both sides. Their gain usually depends on the transformer’s turn ratio N, which can be thousands times. 1.4.1.2.1 Forward Converter A forward converter is a transformertype buck converter with a turn ratio N. It works in first quadrant operation. Its circuit diagram is shown in Figure 1.26. The output voltage is calculated by the formula, VO = kNVin © 2003 by CRC Press LLC
(1.12)
1956_C01.fm Page 24 Monday, August 18, 2003 3:36 PM
i1
i2
D
S
–
VD
+
–
C
VC
V1
L
–
R
+
V2
iC
iL
+
(a) Circuit diagram
i2 i1 –
–
+
VC
V1
L
–
R
+
iL
iC
C
V2 +
(b) Switch on
i2
–
–
VC L
R
+
V2
iC
C
+
(c) Switch off
FIGURE 1.25 Buckboost converter.
1:n
+
D1
L +
D2 Vin
C
Vo
R –
Control
T1
FIGURE 1.26 Forward converter.
where N is the transformer turn ratio, and k is the conduction duty cycle k = ton/T. In order to exploit the magnetic ability of the transformer iron core, a tertiary winding can be employed in the transformer. Its corresponding circuit diagram is shown in Figure 1.27. © 2003 by CRC Press LLC
1956_C01.fm Page 25 Monday, August 18, 2003 3:36 PM
1:1:N
+
L
D1
+ C
D2
Vin
Vo
R –
T1
D3
FIGURE 1.27 Forward converter with tertiary winding.
1:N
D1
+
L +
+ T1
V' –
C
Vo
R –
– T2 D2
FIGURE 1.28 Pushpull converter.
1.4.1.2.2
PushPull Converter
The boost converter works in pushpull state, which effectively avoids the iron core saturation. Its circuit diagram is shown in Figure 1.28. Since there are two switches, which work alternately, the output voltage is doubled. The output voltage is calculated by the formula, VO = 2 kNVin
(1.13)
where N is the transformer turn ratio, and k is the conduction duty cycle k = ton/T. 1.4.1.2.3 FlyBack Converter The flyback converter is a transformer type converter using the demagnetizing effect. Its circuit diagram is shown in Figure 1.29. The output voltage is calculated by the formula, VO =
k NVin 1− k
(1.14)
where N is the transformer turn ratio, and k is the conduction duty cycle k = ton/T. © 2003 by CRC Press LLC
1956_C01.fm Page 26 Monday, August 18, 2003 3:36 PM
D1
1:N
+
+ N1
N2
C
R
Vo –
Control
T1
–
FIGURE 1.29 Flyback converter.
+
1:N C1
D1
L +
T1 C3
R
Vo –
Vin
C2
T2
D2
–
FIGURE 1.30 Halfbridge converter.
1.4.1.2.4 HalfBridge Converter In order to reduce the primary side in one winding, the halfbridge converter was constructed. Its circuit diagram is shown in Figure 1.30. The output voltage is calculated by the formula, VO = kNVin
(1.15)
where N is the transformer turn ratio, and k is the conduction duty cycle k = ton/T. 1.4.1.2.5 Bridge Converter The bridge converter employs more switches and therefore gains double output voltage. Its circuit diagram is shown in Figure 1.31. The output voltage is calculated by the formula, VO = 2 kNVin
(1.16)
where N is the transformer turn ratio, and k is the conduction duty cycle k = ton/T. © 2003 by CRC Press LLC
1956_C01.fm Page 27 Monday, August 18, 2003 3:36 PM
D1
1:N
+ T1
L +
T2 C1
R
Vo –
C
Vin
T3
D2
T4
–
FIGURE 1.31 Bridge converter.
L1
. .
C1
L2
1:N
+
+ D
Vin
C2
R
Vo –
S –
FIGURE 1.32 Zeta converter.
1.4.1.2.6 ZETA Converter The ZETA converter is a transformer type converter with a lowpass filter. Its output voltage ripple is small. Its circuit diagram is shown in Figure 1.32. The output voltage is calculated by the formula, VO =
k NVin 1− k
(1.17)
where N is the transformer turn ratio, and k is the conduction duty cycle k = ton/T. 1.4.1.2.7 Forward Converter with Tertiary Winding and Multiple Outputs Some industrial applications require multiple outputs. This requirement is easily realized by constructing multiple secondary windings and the corresponding conversion circuit. For example, a forward converter with tertiary winding and three outputs is shown in Figure 1.33. The output voltage is calculated by the formula, VO = kN iVin © 2003 by CRC Press LLC
(1.18)
1956_C01.fm Page 28 Monday, August 18, 2003 3:36 PM
1:1:n
+
1
O/P 1 n2
Vin
O/P 2 T1
n3 O/P 3
–
FIGURE 1.33 Forward converter with tertiary winding and three outputs.
where Ni is the transformer turn ratio to the secondary winding, i = 1, 2, and 3 respectively, and k is the conduction duty cycle k = ton/T. In principle, this structure is available for all transformertype DC/DC converters for multiple outputs applications. 1.4.1.3 Developed Converters Developedtype converters overcome the second fault of the fundamental DC/DC converters. They are derived from fundamental converters by the addition of a lowpass filter. The preliminary design was published in a conference in 1977 (Massey and Snyder, 1977). The author designed three types of converters that derived from fundamental DC/DC converters plus a lowpass filter. This conversion technique was very popular between 1970 and 1990. Typical prototype converters are positive output (P/O) Luoconverter, negative output (N/O) Luoconverter, double output (D/O) Luoconverter, Cúkconverter, SEPIC (singleended primary inductance converter) and Watkins–Johnson converters. The output voltage ripple of all developedtype converters is usually small and can be lower than 2%. In order to obtain the random output voltage, which can be higher or lower input voltage. All developed converters provide ease of application for industry. Therefore, the output voltage gain of all developed converters is VO =
k V 1 − k in
(1.19)
1.4.1.3.1 Positive Output (P/O) LuoConverter The positive output Luoconverter is the elementary circuit of the series positive output Luoconverters. It can be derived from the buckboost converter. Its circuit diagram is shown in Figure 1.34. The output voltage is calculated by the Equation (1.19). 1.4.1.3.2 Negative Output (N/O) LuoConverter The negative output Luoconverter is the elementary circuit of the series negative output Luoconverters. It can also be derived from buckboost converters. Its © 2003 by CRC Press LLC
1956_C01.fm Page 29 Monday, August 18, 2003 3:36 PM
i Lo
– VC + S
io LO
C
+
+
iL
VI
CO
D
L
R
–
VO –
FIGURE 1.34 Positive output Luoconverter.
iI + VI –
i LO D
S iL
LO
–
–
vC L +
C
iO
CO
R
vO +
FIGURE 1.35 Negative output Luoconverter.
circuit diagram is shown in Figure 1.35. The output voltage is calculated by the Equation (1.19). 1.4.1.3.3 Double Output (D/O) LuoConverter In order to obtain mirror symmetrical positive plus negative output voltage double output (D/O) Luoconverters were constructed. The double output Luoconverter is the elementary circuit of the series double output Luoconverters. It can also be derived from the buckboost converter. Its circuit diagram is shown in Figure 1.36. The output voltage is calculated by Equation (1.19). 1.4.1.3.4 CúkConverter The Cúkconverter is derived from boost converter. Its circuit diagram is shown in Figure 1.37. The output voltage is calculated by Equation (1.19). 1.4.1.3.5 SingleEnded Primary Inductance Converter The singleended primary inductance converter (SEPIC) is derived from the boost converter. Its circuit diagram is shown in Figure 1.38. The output voltage is calculated by Equation (1.19). © 2003 by CRC Press LLC
1956_C01.fm Page 30 Monday, August 18, 2003 3:36 PM
+
Di
S
LO
C1
+
VI L1
–
V O+
CO
D1
RO
–
– V O– L 11
Di1
C1O
C11
R1O +
L 1O
D11
FIGURE 1.36 Double output Luoconverter.
iL
+
+
vC
i LO
– LO
C
L
iO
– VO
VI
S
D
CO
R
–
+
FIGURE 1.37 Cúkconverter.
iL + VI –
+ L
vC C
S
io
–
i L1 L1
+
D
CO
R
vO –
FIGURE 1.38 SEPIC.
1.4.1.3.6 Tapped Inductor Converter These converters are derived from fundamental converters. The circuit diagrams are shown in Table 1.2. The voltage transfer gains are shown in Table 1.3. Here the tapped inductor ratio is n = n1/(n1 + n2). © 2003 by CRC Press LLC
The Circuit Diagrams of the Tapped Inductor Fundamental Converters Standard Converter
S
Switch Tap
S
L
Rail to Tap
Diode to Tap
S
N2
S
N1
N2 N1
Buck
V IN
C
D
L
Boost
V IN
VO
V IN
D
N1
D C
S
VO
V IN
C
N2
VO
V IN
N1 C
VO
C
VO V IN
D
S
D
N1
N2
D
D
N2
V IN
C
VO
VO
C
VO
C
VO
D
N1
V IN
S
C N2
S
S
BuckBoost
D
S
D
V IN
L
C
VO
C V IN
S
N1
S N2
N2 VO
V IN
N1
N1 D C
VO
V IN
N2
D
© 2003 by CRC Press LLC
1956_C01.fm Page 31 Monday, August 18, 2003 3:36 PM
TABLE 1.2
1956_C01.fm Page 32 Monday, August 18, 2003 3:36 PM
TABLE 1.3 The Voltage Transfer Gains of the Tapped Inductor Fundamental Converters Converter
No tap
Switched to tap
Diode to tap
Rail to tap
Buck
k
k n + k(1 − n)
nk 1 + k(n − 1)
k−n k(1 − n)
Boost
1 1− k
n + k(1 − n) n(1 − k )
1 + k(n − 1) 1− k
n−k n(1 − k )
BuckBoost
k 1− k
k n(1 − k )
nk 1− k
k 1− k
1.4.1.4 Voltage Lift Converters Voltage lift technique is a good method to lift the output voltage, and is widely applied in electronic circuit design. After longterm industrial application and research this method has been successfully used in DC/DC conversion technique. Using this method the output voltage can be easily lifted by tens to hundreds of times. Voltage lift converters can be classed into selflift, relift, triplelift, quadruplelift, and highstage lift converters. The main contributors in this area are Dr. Fang Lin Luo and Dr. Hong Ye. These circuits will be introduced in Chapter 2 in detail. 1.4.1.5 Super Lift Converters Voltage lift (VL) technique is a popular method that is widely used in electronic circuit design. It has been successfully employed in DC/DC converter applications in recent years, and has opened a way to design high voltage gain converters. Three series Luoconverters are examples of voltage lift technique implementations. However, the output voltage increases in stage by stage just along the arithmetic progression. A novel approach — super lift (SL) technique — has been developed, which implements the output voltage increasing stage by stage along in geometric progression. It effectively enhances the voltage transfer gain in powerlaw. The typical circuits are sorted into four series: positive output superlift Luoconverters, negative output superlift Luoconverters, positive output cascade boost converters, and negative output cascade boost converters. These circuits will be introduced in the Chapter 3 to Chapter 6 in detail.
1.4.2
The Second Generation Converters
The second generation converters are called multiple quadrant operation converters. These converters perform in twoquadrant operation and fourquadrant operation with medium output power range (hundreds of Watts or higher). The topologies can be sorted into two main categories: first are © 2003 by CRC Press LLC
1956_C01.fm Page 33 Monday, August 18, 2003 3:36 PM
the converters derived from the multiplequadrant choppers and/or from the first generation converters. Second are constructed with transformers. Usually, one quadrant operation requires at least one switch. Therefore, a twoquadrant operation converter has at least two switches, and a fourquadrant operation converter has at least four switches. Multiplequadrant choppers were employed in industrial applications for a long time. They can be used to implement the DC motor multiplequadrant operation. As the chopper titles indicate, there are classA converters (onequadrant operation), classB converters (twoquadrant operation), classC converters, classD converters, and classE (fourquadrant operation) converters. These converters are derived from multiquadrant choppers, for example, class B converters are derived from Btype choppers and class E converters are derived from Etype choppers. The classA converter works in quadrant I, which corresponds to the forwardmotoring operation of a DC motor drive. The classB converter works in quadrant I and II operation, which corresponds to the forwardrunning motoring and regenerative braking operation of a DC motor drive. The classC converter works in quadrant I and VI operation. The classD converter works in quadrant III and VI operation, which corresponds to the reverserunning motoring and regenerative braking operation of a DC motor drive. The classE converter works in fourquadrant operation, which corresponds to the fourquadrant operation of a DC motor drive. In recent years many papers have investigated the classE converters for industrial applications. Multiquadrant operation converters can be derived from the first generation converters. For example, multiquadrant Luoconverters are derived from positiveoutput Luoconverters and negativeoutput Luoconverters. These circuits will be introduced in Chapter 7 in detail. The transformertype multiquadrant converters easily change the current direction by transformer polarity and diode rectifier. The main types of such converters can be derived from the forward converter, halfbridge converter, and bridge converter.
1.4.3
The Third Generation Converters
The third generation converters are called switched component converters, and are made of either inductors or capacitors, socalled switchedinductor and switchedcapacitors. They can perform in two or fourquadrant operation with high output power range (thousands of Watts). Since they are made of only inductor or capacitors, they are small. Consequently, the power density and efficiency are high. 1.4.3.1 Switched Capacitor Converters Switchedcapacitor DC/DC converters consist of only capacitors. Because there is no inductor in the circuit, their size is small. They have outstanding advantages such as low power losses and low electromagnetic interference © 2003 by CRC Press LLC
1956_C01.fm Page 34 Monday, August 18, 2003 3:36 PM
(EMI). Since its electromagnetic radiation is low, switchedcapacitor DC/DC converters are required in certain equipment. The switchedcapacitor can be integrated into an integratedchip (IC). Hence, its size is largely reduced. Much attention has been drawn to the switchedcapacitor converter since its development. Many papers have been published discussing its characteristics and advantages. However, most of the converters in the literature perform a singlequadrant operation. Some of them work in the pushpull status. In addition, their control circuit and topologies are very complex, especially, for the large difference between input and output voltages. These circuits will be introduced in the Chapter 8 in detail. 1.4.3.2 MultipleQuadrant Switched Capacitor LuoConverters Switchedcapacitor DC/DC converters consist of only capacitors. Since its power density is very high it is widely applied in industrial applications. Some industrial applications require multiple quadrant operation, so that, multiplequadrant switchedcapacitor Luoconverters have been developed. There are twoquadrant operation type and fourquadrant operation type, which will be discussed in detail. 1.4.3.3 MultipleLift PushPull Switched Capacitor Converters Voltage lift (VL) technique is a popular method widely used in electronic circuit design. It has been successfully employed in DC/DC converter applications in recent years, and has opened a way to design high voltage gain converters. Three series Luoconverters are examples of voltage lift technique implementation. However, the output voltage increases stagebystage just along the arithmetic progression. A novel approach — multiplelift pushpull (mlpp) technique — has been developed that implements the output voltage, which increases stage by stage along the arithmetic progression. It effectively enhances the voltage transfer gain. The typical circuits are sorted into two series: positive output multiplelift pushpull switched capacitor Luoconverters and negative output multiplelift pushpull switched capacitor Luoconverters. These circuits will be introduced in the Chapter 9 and Chapter 10 in detail. 1.4.3.4 MultipleQuadrant Switched Inductor Converters The switchedcapacitors have many advantages, but their circuits are not simple. If the difference of input and output voltages is large, many capacitors must be required. The switchedinductor has the outstanding advantage that only one inductor is required for one switched inductor converter no matter how large the difference between input and output voltages is. This characteristic is very important for large power conversion. At the present time, large power conversion equipment is close to using switchedinductor converters. For example, the MIT DC/DC converter designed by Prof. John G. Kassakian for his new system in the 2005 automobiles is a twoquadrant © 2003 by CRC Press LLC
1956_C01.fm Page 35 Monday, August 18, 2003 3:36 PM
switchedinductor DC/DC converter. These circuits will be introduced in Chapter 8.
1.4.4
The Fourth Generation Converters
The fourth generation DC/DC converters are called softswitching converters. There are four types of softswitching methods: 1. 2. 3. 4.
Resonantswitch converters Loadresonant converters Resonantdclink converters Highfrequencylink integralhalfcycle converters
Until now attention has been paid only to the resonantswitch conversion method. This resonance method is available for working independently to load. There are three main categories: zerocurrentswitching (ZCS), zerovoltageswitching (ZVS), and zerotransition (ZT) converters. Most topologies usually perform in single quadrant operation in the literature. Actually, these converters can perform in two and fourquadrant operation with high output power range (thousands of Watts). According to the transferred power becomes large, the power losses increase largely. Main power losses are produced during the switchon and switchoff period. How to reduce the power losses across the switch is the clue to increasing the power transfer efficiency. Softswitching technique successfully solved this problem. Professor Fred Lee is the pioneer of the softswitching technique. He established a research center and manufacturing base to realize the zerocurrentswitching (ZCS) and zerovoltageswitching (ZVS) DC/DC converters. His first paper introduced his research in 1984. ZCS and ZVS converters have three resonant states: over resonance (completed resonance), optimum resonance (critical resonance) and quasi resonance (subresonance). Only the quasiresonance state has two clear crosszero points in a repeating period. Many papers after 1984 have been published that develop the ZCS quasiresonantconverters (QRCs) and ZVSQRCs. 1.4.4.1 ZeroCurrentSwitching QuasiResonant Converters ZCSQRC equips the resonant circuit on the switch side to keep the switchon and switchoff at zerocurrent condition. There are two states: fullwave state and half wave state. Most engineers use the halfwave state. This technique has halfwave current resonance waveform with two zerocross points. 1.4.4.2 ZeroVoltageSwitching QuasiResonant Converters ZVSQRC equips the resonant circuit on the switch side to keep the switchon and switchoff at zerocurrent condition. There are two states: fullwave state © 2003 by CRC Press LLC
1956_C01.fm Page 36 Monday, August 18, 2003 3:36 PM
and half wave state. Most engineers use the halfwave state. This technique has halfwave current resonance waveform with two zerocross points. 1.4.4.3 ZeroTransition Converters Using ZCSQRC and ZVSQRC largely reduces the power losses across the switches. Consequently, the switch device power rates become lower and converter power efficiency is increased. However, ZCSQRC and ZVSQRC have large current and voltage stresses. Therefore the device’s current and voltage peak rates usually are 3 to 5 times higher than the working current and voltage. It is not only costly, but also ineffective. ZeroTransition (ZT) technique overcomes this fault. It implements zerovoltage plus zerocurrentswitching (ZVZCS) technique without significant current and voltage stresses. These circuits will be introduced in Chapter 11 in detail.
1.4.5
The Fifth Generation Converters
The fifth generation converters are called synchronous rectifier (SR) DC/DC converters. This type of converter was required by development of computing technology. Corresponding to the development of the micropower consumption technique and highdensity IC manufacture, the power supplies with low output voltage and strong current are widely used in communications, computer equipment, and other industrial applications. Intel , which developed the Zelogtype computers, governed the world market for a long time. Inter80 computers used the 5 V power supply. In order to increase the memory size and operation speed, largescale integrated chip (LSIC) technique has been quickly developed. As the amount of IC manufacturing increased, the gaps between the layers became narrower. At the same time, the micropowerconsumption technique was completed. Therefore new computers such as those using Pentium I, II, III, and IV, use a 3.3 V power supply. Future computers will have larger memory and will require lower power supply voltages, e.g. 2.5, 1.8, 1.5, even if 1.1 V. Such low power supply voltage cannot be obtained by the traditional diode rectifier bridge because the diode voltage drop is too large. Because of this requirement, new types of MOSFET were developed. They have very low conduction resistance (6 to 8 m Ω¸) and forward voltage drop (0.05 to 0.2 V). Many papers have been published since 1990 and many prototypes have been developed. The fundamental topology is derived from the forward converter. Activeclamped circuit, flattransformers, double current circuit, softswitching methods, and multiple current methods can be used in SR DC/DC converters. These circuits will be introduced in Chapter 12 in detail.
1.4.6
The Sixth Generation Converters
The sixth generation converters are called multiple energystorage elements resonant (MER) converters. Current source resonant inverters are the heart © 2003 by CRC Press LLC
1956_C01.fm Page 37 Monday, August 18, 2003 3:36 PM
of many systems and equipment, e.g., uninterruptible power supply (UPS) and highfrequency annealing (HFA) apparatus. Many topologies shown in the literature are the series resonant converters (SRC) and parallel resonant converters (PRC) that consist of two or three or four energy storage elements. However, they have limitations. These limitations of two, three, and/or fourelement resonant topologies can be overcome by special design. These converters have been catagorized into three main types: • Two energystorage elements resonant DC/AC and DC/AC/DC converters • Three energystorage elements resonant DC/AC and DC/AC/DC converters • Four energystorage elements (2L2C) resonant DC/AC and DC/ AC/DC converters By mathematical calculation there are eight prototypes of twoelement converters, 38 prototypes of threeelement converters, and 98 prototypes of fourelement (2L2C) converters. By careful analysis of these prototypes we find that few circuits can be realized. If we keep the output in lowpass bandwidth, the series components must be inductors and shunt components must be capacitors. Through further analysis, the first component of the resonantfilter network can be an inductor in series, or a capacitor in shunt. In the first case, only alternate (square wave) voltage sources can be applied to the network. In the second case, only alternate (square wave) current sources can be applied to the network. These circuits will be introduced in Chapter 13 to Chapter 16 in detail.
1.5
Categorize Prototypes and DC/DC Converter Family Tree
There are more than 500 topologies of DC/DC converters. It is urgently necessary to categorize all prototypes. From all accumulated knowledge we can build a DC/DC converter family tree, which is shown in Figure 1.39. In each generation we introduce some circuits to readers to promote understanding of the characteristics.
© 2003 by CRC Press LLC
1956_C01.fm Page 38 Monday, August 18, 2003 3:36 PM
Buck Converter Fundamental Circuits
Boost Converter BuckBoost Converter
1G Classical Converters
Developed Forward Converter FlyBack Converter PushPull Converter Transformer
HalfBridge Converter Bridge Converter ZETA Converter
Positive Output LuoConverter Negative Output LuoConverter Double Output LuoConverter CukConverter SEPIC TappedInductor Converters
7 SelfLift Converter Positive Output LuoConverter Negative Output LuoConverter
Voltage Lift
Modified P/O LuoConverter Double Output LuoConverter Positive Output Cascade Boost Converter
SuperLift
Negative Output Cascade Boost Converter Positive Output SuperLift LuoConverter
DC/DC Converters
Negative Output SuperLift LuoConverter 2G MultiQuadrant Converters
Transformertype Converters Developed
MultiQuadrant LuoConverter Two Quadrants Converter
SwitchedCapacitor Converter 3G SwitchedComponent Converters
Four Quadranrts SC LuoConverter
MultiLift
P/O MultiLift PushPull LuoConverter
N/O MultiLift PushPull LuoConverter Transformertype Converters SwitchedInductor Converter Four Quadranrts SI LuoConverter
4G SoftSwitching Converters 5G Synchoronous Rectifier Converters 6G MultiElements Resonant Power Converters
FIGURE 1.39 DC/DC converter family.
© 2003 by CRC Press LLC
ZCSQRC  Four Quadrants ZeroCurrent Switching LuoConverter ZVSQRC  Four Quadrants ZeroVoltage Switching LuoConverter ZTC  Four Quadrants ZeroTransition LuoConverter FlatTransformer Synchronous Rectifier Converter Synchronous Rectifier Converter with Active Clamp Circuit Double Current Synchronous Rectifier Converter ZCS Synchronous Rectifier Converter ZVS Synchronous Rectifier Converter 2Elements ∏ − CLL Current Sources on Resonant Inverter 3Elements Double GammaCL Current Source Resonant Inverter 4Elements Reverse Double GammaCL Resonant Power Converter
1956_C01.fm Page 39 Monday, August 18, 2003 3:36 PM
Bibliography Cúk, S., Basics of switchedmode power conversion: topologies, magnetics, and control, in Cúk, S., Ed., Advances in SwitchedMode Power Conversion, Irvine, CA, Teslaco, 1995, vol. 2. Erickson, R.W. and Maksimovic, D., Fundamentals of Power Electronics, 2nd ed., Kluwer Academic Publishers, Norwell, MA, 1999. Kassakian, J., Schlecht, M., and Vergese, G., Principles of Power Electronics, AddisonWesley, Reading, MA, 1991. Kazimierczuk, M.K. and Bui, X.T., ClassE DCDC converters with an inductive impedance inverter, IEEETransactions on Power Electronics, 4, 124, 1989. Liu, Y. and Sen, P.C., New classE DCDC converter topologies with constant switching frequency, IEEETransactions on Industry Applications, 32, 961, 1996. Luo, F.L., Relift circuit, a new DCDC stepup (boost) converter, IEEElectronics Letters, 33, 5, 1997. Luo, F.L., Positive output Luoconverters, a series of new DCDC stepup (boost) conversion circuits, in Proceedings of the IEEE International Conference PEDS 1997, Singapore, p. 882. Luo, F.L., Relift converter: design, test, simulation and stability analysis, IEE Proceedings on Electric Power Applications, 145, 315, 1998. Luo, F.L., Negative output Luoconverters, implementing the voltage lift technique, in Proceedings of the Second World Energy System International Conference WES 1998, Toronto, Canada, 1998, 253. Luo, F.L. and Ye, H., DC/DC conversion techniques and nine series Luoconverters, in Rashid M.H., Luo F.L., et al., Eds., Power Electronics Handbook, Academic Press, San Diego, 2001, chap. 17. Maksimovic, D. and Cúk, S., Switching converters with wide DC conversion range, IEEE Transactions on Power Electronics, 6, 151, 1991. Massey, R.P. and Snyder, E.C., High voltage singleended DC/DC converter, in Proceedings of IEEE PESC ’77, Record. 1977. p. 156. Middlebrook, R.D. and Cúk, S., Advances in SwitchedMode Power Conversion, TESLAco, Pasadena, CA, 1981, vols. I and II. Mohan, N., Undeland, T.M., and Robbins, W.P., Power Electronics: Converters, Applications and Design, 3rd ed., John Wiley & Sons, New York, 2003. Oxner, E., Power FETs and Their Applications, Prentice Hall, NJ, 1982. Rashid, M.H., Power Electronics: Circuits, Devices and Applications, 2nd ed., PrenticeHall, New York, 1993. Redl, R., Molnar, B., and Sokal, N.O., ClassE resonant DCDC power converters: analysis of operations, and experimental results at 1.5 Mhz, IEEETransactions on Power Electronics, 1, 111, 1986. Severns, R.P. and Bloom, E., Modern DCtoDC Switch Mode Power Converter Circuits, Van Nostrand Reinhold Company, New York, 1985. Smedley, K.M. and Cúk, S., Onecycle control of switching converters, IEEE Transactions on Power Electronics, 10, 625, 1995.
© 2003 by CRC Press LLC
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2 VoltageLift Converters
The voltagelift (VL) technique is a popular method that is widely applied in electronic circuit design. Applying this technique effectively overcomes the effects of parasitic elements and greatly increases the output voltage. Therefore, these DC/DC converters can convert the source voltage into a higher output voltage with high power efficiency, high power density, and a simple structure.
2.1
Introduction
VL technique is applied in the periodical switching circuit. Usually, a capacitor is charged during switchon by certain voltages, e.g., source voltage. This charged capacitor voltage can be arranged on topup to some parameter, e.g., output voltage during switchoff. Therefore, the output voltage can be lifted higher. Consequently, this circuit is called a selflift circuit. A typical example is the sawtoothwave generator with a selflift circuit. Repeating this operation, another capacitor can be charged by a certain voltage, which may possibly be the input voltage or other equivalent voltage. The second capacitor charged voltage is also possibly arranged on topup to some parameter, especially output voltage. Therefore, the output voltage can be higher than that of the selflift circuit. As usual, this circuit is called relift circuit. Analogously, this operation can be repeated many times. Consequently, the series circuits are called triplelift circuits, quadruplelift circuits, and so on. Because of the effect of parasitic elements the output voltage and power transfer efficiency of DCDC converters are limited. Voltage lift technique opens a way to improve circuit characteristics. After longterm research, this technique has been successfully applied to DCDC converters. Three series Luoconverters are the DCDC converters, which were developed from prototypes using VL technique. These converters perform DCDC voltage increasing conversion with high power density, high efficiency, and cheap topology in simple structure. They are different from any other DCDC stepup converters and possess many advantages including a high output voltage
© 2003 by CRC Press LLC
1956_C02.fm Page 42 Monday, August 18, 2003 3:26 PM
with small ripples. Therefore, these converters are widely used in computer peripheral equipment and industrial applications, especially for high output voltage projects. This chapter’s contents are arranged thusly: 1. 2. 3. 4. 5.
2.2
Seven types of selflift converters Positive output Luoconverters Negative output Luoconverters Modified positive output Luoconverters Double output Luoconverters
Seven SelfLift Converters
All selflift converters introduced here are derived from developed converters such as Luoconverters, Cúkconverters, and singleended primary inductance converters (SEPICs) discussed in Section 1.3. Since all circuits are simple, usually only one more capacitor and diode required that the output voltage be higher by an input voltage. The output voltage is calculated by the formula VO = (
k 1 + 1)Vin = V 1− k 1 − k in
(2.1)
There are seven circuits: • • • • • • •
Selflift Cúk converter Selflift P/O Luoconverter Reverse selflift P/O Luoconverter Selflift N/O Luoconverter Reverse selflift Luoconverter Selflift SEPIC Enhanced selflift P/O Luoconverter
These converters perform DCDC voltage increasing conversion in simple structures. In these circuits the switch S is a semiconductor device (MOSFET, BJT, IGBT and so on). It is driven by a pulsewidthmodulated (PWM) switching signal with variable frequency f and conduction duty k. For all circuits, the load is usually resistive, i.e., R = VO / I O © 2003 by CRC Press LLC
1956_C02.fm Page 43 Monday, August 18, 2003 3:26 PM
The normalized load is zN =
R fLeq
(2.2)
where Leq is the equivalent inductance. We concentrate on the absolute values rather than polarity in the following description and calculations. The directions of all voltages and currents are defined and shown in the corresponding figures. We also assume that the semiconductor switch and the passive components are all ideal. All capacitors are assumed to be large enough that the ripple voltage across the capacitors can be negligible in one switching cycle for the average value discussions. For any component X (e.g., C, L and so on): its instantaneous current and voltage are expressed as iX and vX . Its average current and voltage values are expressed as Ix and Vx. The input voltage and current are VO and IO; the output voltage and current are VI and II. T and f are the switching period and frequency. The voltage transfer gain for the continuous conduction mode (CCM) is M=
Vo I I = VI I o
(2.3)
Variation of current iL :
ζ1 =
∆iL / 2 IL
(2.4)
Variation of current iLO :
ζ2 =
∆iLo / 2 I Lo
(2.5)
Variation of current iD :
ξ=
∆iD / 2 ID
(2.6)
Variation of voltage vC :
ρ=
∆vC / 2 VC
(2.7)
Variation of voltage vC1 :
σ1 =
∆vC1 / 2 vC 1
(2.8)
Variation of voltage vC2 : © 2003 by CRC Press LLC
σ2 =
∆vC 2 / 2 vC 2
(2.9)
1956_C02.fm Page 44 Monday, August 18, 2003 3:26 PM
Variation of output voltage vO :
ε=
∆Vo / 2 Vo
(2.10)
Here ID refers to the average current iD which flows through the diode D during the switchoff period, not its average current over the whole period. Detailed analysis of the seven selflift DCDC converters will be given in the following sections. Due to the length limit of this book, only the simulation and experimental results of the selflift Cúk converter are given. However, the results and conclusions of other selflift converters should be quite similar to those of the selflift Cúkconverter.
2.2.1
SelfLift Cúk Converter
Selflift Cúk converters and their equivalent circuits during switchon and switchoff period are shown in Figure 2.1. It is derived from the Cúk converter. During switchon period, S and D1 are on, D is off. During switchoff period, D is on, S and D1 are off. 2.2.1.1 Continuous Conduction Mode In steady state, the average inductor voltages over a period are zero. Thus VC1 = VCO = VO
(2.11)
During switchon period, the voltage across capacitors C and C1 are equal. Since we assume that C and C1 are sufficiently large, so VC = VC1 = VO
(2.12)
The inductor current iL increases during switchon and decreases during switchoff. The corresponding voltages across L are VI and −(VC − VI ) . Therefore, kTVI = (1 − k )T (VC − VI ) Hence, VO = VC = VC1 = VCO = The voltage transfer gain in the CCM is © 2003 by CRC Press LLC
1 V 1− k
(2.13)
1956_C02.fm Page 45 Monday, August 18, 2003 3:26 PM
i
v
I
+ L
+ V
i C
D
C
v I
LO
i
–
S
D
–
L 1
O
O
–
–
VO
C1
C
+
C
1
R
O
+
(a) Circuit diagram
iI + +
i LO
vC
L
iO
– LO
C
–
– v C1
VI
S
–
+
vO CO
C1
R
+
(b) Switch on iI + +
L
vC
iO
– LO
C
–
– v C1
VI
+
–
vO C1
CO
R
+
(c) Switch off FIGURE 2.1 Selflift Cúk converter and equivalent circuits. (a) The selflift Cúk converter. (b) The equivalent circuit during switchon. (c) The equivalent circuit during switchoff.
M=
VO I 1 = I = VI IO 1 − k
(2.14)
The characteristics of M vs. conduction duty cycle k are shown in Figure 2.2. Since all the components are considered ideal, the power loss associated with all the circuit elements are neglected. Therefore the output power PO is considered to be equal to the input power PIN : VO I O = VI I I
© 2003 by CRC Press LLC
1956_C02.fm Page 46 Monday, August 18, 2003 3:26 PM
M 12 10 8 6 4 2
k
0 0
0.2
0.4
0.6
0.8
1
FIGURE 2.2 Voltage transfer gain M vs. k.
Thus, 1 I 1− k O
IL = II = During switchoff, iD = i L
ID =
1 I 1− k O
(2.15)
The capacitor CO acts as a low pass filter so that I LO = I O The current iL increases during switchon. The voltage across it during switchon is VI, therefore its peaktopeak current variation is ∆iL =
kTVI L
The variation ratio of the current iL is ζ1 = © 2003 by CRC Press LLC
∆iL / 2 kTVI k(1 − k )2 R kR = = = 2IL 2 fL 2 M 2 fL IL
(2.16)
1956_C02.fm Page 47 Monday, August 18, 2003 3:26 PM
The variation of current iD is ξ = ζ1 =
kR 2 M 2 fL
(2.17)
The peaktopeak variation of voltage vC is ∆vC =
I L (1 − k )T I O = C fC
(2.18)
The variation ratio of the voltage vC is ρ=
∆vC / 2 IO 1 = = 2 fCVO 2 fRC VC
(2.19)
The peaktopeak variation of the voltage vC1 is ∆vC1 =
I LO (1 − k )T I O (1 − k ) = C1 fC1
(2.20)
The variation ratio of the voltage vC1 is σ1 =
∆vC1 / 2 I O (1 − k ) 1 = = 2 fC1VO 2 MfRC1 VC1
(2.21)
The peaktopeak variation of the current iLO is approximately:
∆iLO
1 ∆vC1 T I (1 − k ) = 2 2 2 = O2 8 f LO C1 LO
(2.22)
The variation ratio of the current iLO is approximately: ζ2 =
∆iLO / 2 I (1 − k ) 1 = O2 = 16 f LO C1 I O 16 Mf 2 LO C1 I LO
(2.24)
The peaktopeak variation of voltage vO and vCO is
∆vO = ∆vCO © 2003 by CRC Press LLC
1 ∆iLO T I O (1 − k ) = 2 2 2 = CO 64 f 3 LO C1CO
(2.25)
1956_C02.fm Page 48 Monday, August 18, 2003 3:26 PM
The variation ratio of the output voltage is ε=
∆vO / 2 I O (1 − k ) 1 = = VO 128 f 3 LO C1COVO 128 Mf 3 LO C1CO R
(2.26)
The voltage transfer gain of the selflift Cúk converter is the same as the original boost converter. However, the output current of the selflift Cúk converter is continuous with small ripple. The output voltage of the selflift Cúk converter is higher than the corresponding Cúk converter by an input voltage. It retains one of the merits of the Cúk converter. They both have continuous input and output current in CCM. As for component stress, it can be seen that the selflift converter has a smaller voltage and current stresses than the original Cúk converter. 2.2.1.2 Discontinuous Conduction Mode Selflift Cúk converters operate in the discontinuous conduction mode (DCM) if the current iD reduces to zero during switchoff. As a special case, when iD decreases to zero at t = T, then the circuit operates at the boundary of CCM and DCM. The variation ratio of the current iD is 1 when the circuit works in the boundary state. ξ=
k R =1 2 M 2 fL
(2.27)
Therefore the boundary between CCM and DCM is MB = k
R = 2 fL
kz N 2
(2.28)
where z N is the normalized load R/(fL). The boundary between CCM and DCM is shown in Figure 2.3a. The curve that describes the relationship between MB and z N has the minimum value MB = 1.5 and k = ⅓ when the normalized load z N is 13.5. When M > MB , the circuit operates in the DCM. In this case the diode current iD decreases to zero at t = t1 = [k + (1 – k) m] T where kT < t1< T and 0 < m < 1. Define m as the current filling factor (FF). After mathematical manipulation: m=
© 2003 by CRC Press LLC
M2 1 = ξ k R 2 fL
(2.29)
1956_C02.fm Page 49 Monday, August 18, 2003 3:26 PM
a) Boundary between CCM and DCM
b) The voltage transfer gain M vs. the normalized load at various k FIGURE 2.3 Boundary between CCM and DCM and DC voltage transfer gain M vs. the normalized load at various k. (a) Boundary between CCM and DCM. (b) The voltage transfer gain M vs. the normalized load at various k.
From the above equation we can see that the discontinuous conduction mode is caused by the following factors: • Switch frequency f is too low • Duty cycle k is too small • Inductance L is too small • Load resistor R is too big
© 2003 by CRC Press LLC
1956_C02.fm Page 50 Monday, August 18, 2003 3:26 PM
In the discontinuous conduction mode, current iL increases during switchon and decreases in the period from kT to (1 – k)mT. The corresponding voltages across L are VI and −(VC − VI ) . Therefore, kTVI = (1 − k )mT (VC − VI ) Hence, VC = [1 +
k ]V (1 − k )m I
(2.30)
Since we assume that C, C1, and CO are large enough, VO = VC = VCO = [1 +
k ]V (1 − k )m I
(2.31)
or VO = [1 + k 2 (1 − k )
R ]V 2 fL I
(2.32)
R 2 fL
(2.33)
The voltage transfer gain in the DCM is MDCM = 1 + k 2 (1 − k )
The relation between DC voltage transfer gain M and the normalized load at various k in the DCM is also shown Figure 2.3b. It can be seen that in DCM, the output voltage increases as the load resistance R is increasing.
2.2.2
SelfLift P/O LuoConverter
Selflift positive output Luoconverters and the equivalent circuits during switchon and switchoff period are shown in Figure 2.4. It is the selflift circuit of the positive output Luoconverter. It is derived from the elementary circuit of positive output Luoconverter. During switchon period, S and D1 are switchon, D is switchoff. During switchoff period, D is on, S and D1 are off. 2.2.2.1 Continuous Conduction Mode In steady state, the average inductor voltages over a period are zero. Thus VC = VCO = VO During switchon period, the voltage across capacitor C1 is equal to the source voltage. Since we assume that C and C1 are sufficiently large, © 2003 by CRC Press LLC
1956_C02.fm Page 51 Monday, August 18, 2003 3:26 PM
iI
–
+
S
vC
i LO
+
iO
LO
C D
+ D1
VI
+ vC1 –
iL –
vO CO
C1
R –
L
a) Self–Lift Positive Output Luo–Converter
iI
–
vC
i LO
+ LO
C
+
iO
+ VI iL L
–
+ vC1 –
vO CO
C1
R –
b) The equivalent circuit during switch–on
iI
–
vC
i LO
+ LO
C
+
iO
+ VI iL –
L
+ vC1 –
v C1
CO
R –
c) The equivalent circuit during switch–off FIGURE 2.4 Selflift positive output Luoconverter and its equivalent circuits. (a) Selflift positive output Luoconverter. (b) The equivalent circuit during switchon. (c) The equivalent circuit during switchoff.
VC1 = VI The inductor current iL increases in the switchon period and decreases in the switchoff period. The corresponding voltages across L are VI and −(VC − VC1 ) . © 2003 by CRC Press LLC
1956_C02.fm Page 52 Monday, August 18, 2003 3:26 PM
Therefore kTVI = (1 − k )T (VC − VC1 ) Hence, VO =
1 V 1− k I
The voltage transfer gain in the CCM is M=
VO 1 = VI 1 − k
(2.34)
Since all the components are considered ideal, the power loss associated with all the circuit elements are neglected. Therefore the output power PO is considered to be equal to the input power PIN , VO I O = VI I I Thus, II =
1 I 1− k O
The capacitor CO acts as a low pass filter so that I LO = I O The charge of capacitor C increases during switchon and decreases during switchoff. Q+ = I C −ON kT = I O kT
Q− = I C −OFF (1 − k )T = I L (1 − k )T
In a switch period, Q + = Q−
IL =
k I 1− k O
during switchoff period, iD = iL + iLO Therefore, I D = I L + I LO = © 2003 by CRC Press LLC
1 I 1− k O
1956_C02.fm Page 53 Monday, August 18, 2003 3:26 PM
For the current and voltage variations and boundary condition, we can get the following equations using a similar method that was used in the analysis of selflift Cúk converter. Current variations: ζ1 =
1 R 2 M 2 fL
ζ2 =
k R 2 M fLO
ξ=
k R 2 M 2 fLeq
where Leq refers to Leq =
LLO L + LO
Voltage variations: ρ=
k 1 2 fCR
σ1 =
M 1 2 fC1R
ε=
k 1 2 8 M f LO CO
2.2.2.2 Discontinuous Conduction Mode Selflift positive output Luoconverters operate in the DCM if the current iD reduces to zero during switchoff. As the critical case, when iD decreases to zero at t = T, then the circuit operates at the boundary of CCM and DCM. The variation ratio of the current iD is 1 when the circuit works in the boundary state. ξ=
k R =1 2 M 2 fLeq
Therefore the boundary between CCM and DCM is MB = k
R = 2 fLeq
kz N 2
(2.35)
where z N is the normalized load R / ( fLeq ) and Leq refers to Leq = LLO L + LO . When M > MB , the circuit operates at the DCM. In this case the circuit operates in the diode current iD decreases to zero at t = t1 = [k + (1 – k) m] T, where KT < t1< T and 0 < m < 1, with m as the current filling factor. We define m as: m=
© 2003 by CRC Press LLC
1 M2 = ξ k R 2 fLeq
(2.36)
1956_C02.fm Page 54 Monday, August 18, 2003 3:26 PM
In the discontinuous conduction mode, current iL increases in the switchon period kT and decreases in the period from kT to (1 – k)mT. The corresponding voltages across L are VI and −(VC − VC1 ) . Therefore, kTVI = (1 − k )mT (VC − VC1 ) and VC = VCO = VO
VC1 = VI
Hence, VO = [1 +
k ]V (1 − k )m I
or VO = [1 + k 2 (1 − k )
R ]V 2 fLeq I
(2.37)
So the real DC voltage transfer gain in the DCM is MDCM = 1 + k 2 (1 − k )
R 2 fL eq
(2.38)
In DCM, the output voltage increases as the load resistance R is increasing.
2.2.3
Reverse SelfLift P/O LuoConverter
Reverse selflift positive output Luoconverters and their equivalent circuits during switchon and switchoff period are shown in Figure 2.5. It is derived from the elementary circuit of positive output Luoconverters. During switchon period, S and D1 are on, D is off. During switchoff period, D is on, S and D1 are off. 2.2.3.1 Continuous Conduction Mode In steady state, the average inductor voltages over a period are zero. Thus VC1 = VCO = VO © 2003 by CRC Press LLC
1956_C02.fm Page 55 Monday, August 18, 2003 3:26 PM
iI
+ S
+
vC1
i LO
–
iO
LO
C1
D1
–
D
VI L
–
vO – vC +
iL
R +
CO C
a) Reverse Self–Lift Positive Output Luo–Converter iI
+
vC1
i LO
– LO
C1
+
iO
– VI
vO – vC +
iL L
–
R +
CO C
b) The equivalent circuit during switch–on iI
+
vC1
i LO
– LO
C1
+
iO
– VI
vO iL
–
L
– vC +
C
CO
R +
c) The equivalent circuit during switch–off FIGURE 2.5 Reverse selflift positive output Luoconverter and its equivalent circuits. (a) Reverse selflift positive output Luoconverter. (b) The equivalent circuit during switchon. (c) The equivalent circuit during switchoff.
During switchon period, the voltage across capacitor C is equal to the source voltage plus the voltage across C1. Since we assume that C and C1 are sufficiently large, VC1 = VI + VC © 2003 by CRC Press LLC
1956_C02.fm Page 56 Monday, August 18, 2003 3:26 PM
Therefore, VC1 = VI +
1 k VI = V 1− k 1− k I
VO = VCO = VC1 =
1 V 1− k I
(2.39)
The voltage transfer gain in the CCM is M=
VO 1 = VI 1 − k
(2.40)
Since all the components are considered ideal, the power losses on all the circuit elements are neglected. Therefore the output power PO is considered to be equal to the input power PIN , VO I O = VI I I Thus, II =
1 I 1− k O
The capacitor CO acts as a low pass filter so that I LO = I O The charge of capacitor C1 increases during switchon and decreases during switchoff Q+ = I C1−ON kT Q− = I LO (1 − k )T = I O (1 − k )T In a switch period, Q + = Q−
I C1−ON =
I C −ON = I LO + I C1−ON = I O + © 2003 by CRC Press LLC
1− k I k O 1− k 1 IO = IO k k
(2.41)
1956_C02.fm Page 57 Monday, August 18, 2003 3:26 PM
The charge of capacitor C increases during switchoff and decreases during switchon. Q+ = I C −OFF (1 − k )T
Q− = I C −ON kT =
1 I kT k O
In a switch period, Q + = Q−
1− k 1 = I I k C −ON 1 − k O
I C −OFF =
(2.42)
Therefore, I L = I LO + I C −OFF = I O +
1 2−k I = I = IO + I I 1− k O 1− k O
During switchoff, iD = iL − iLO Therefore, I D = I L − I LO = I O The following equations are used for current and voltage variations and boundary conditions. Current variations: ζ1 =
k R , (2 − k ) M 2 fL
ζ2 =
k R 2 M fLO
ξ=
1 R 2 M 2 fLeq
where Leq refers to Leq =
LLO L + LO
Voltage variations: ρ=
1 1 2 k fCR
© 2003 by CRC Press LLC
σ1 =
1 1 2 M fC1R
ε=
1 k 16 M f 2 CO LO
1956_C02.fm Page 58 Monday, August 18, 2003 3:26 PM
2.2.3.2 Discontinuous Conduction Mode Reverse selflift positive output Luoconverter operates in the DCM if the current iD reduces to zero during switchoff at t = T, then the circuit operates at the boundary of CCM and DCM. The variation ratio of the current iD is 1 when the circuit works in the boundary state. ξ=
k R =1 2 2 M fLeq
Therefore the boundary between CCM and DCM is MB = k
R = 2 fLeq
kz N 2
(2.43)
where z N is the normalized load R / ( fLeq ) and Leq refers to Leq = LLO L + LO . When M > MB , the circuit operates in the DCM. In this case the diode current iD decreases to zero at t = t1 = [k + (1 – k) m] T, where KT < t1 < T and 0 < m < 1. m is the current filling factor. m=
1 M2 = ξ k R 2 fLeq
(2.44)
In the discontinuous conduction mode, current iL increases during switchon and decreases in the period from kT to (1 – k)mT. The corresponding voltages across L are VI and −VC . Therefore, kTVI = (1 − k )mTVC and VC1 = VCO = VO
VC1 = VI + VC
Hence, VO = [1 +
k ]V (1 − k )m I
or R VO = 1 + k 2 (1 − k ) VI fL 2 eq © 2003 by CRC Press LLC
(2.45)
1956_C02.fm Page 59 Monday, August 18, 2003 3:26 PM
iI
+ VI –
i LO
+ vC1 – S
C1 iL
L
LO
D – vC D1 +
iO – vO CO
C
R
+
a) SelfLift Negative Output LuoConverter iI
+ vC1 –
+
C1
VI –
iL
L
i LO LO
– vC +
iO – vO CO
C
R
+
b) The equivalent circuit during switchon iI
+ vC1 –
+
C1
VI –
iL
L
i LO LO
– vC +
iO
C
– CO
R
+
c) The equivalent circuit during switchoff FIGURE 2.6 Selflift negative output Luoconverter and its equivalent circuits. (a) Selflift negative output Luoconverter. (b) The equivalent circuit during switchon. (c) The equivalent circuit during switchoff.
So the real DC voltage transfer gain in the DCM is MDCM = 1 + k 2 (1 − k )
R 2 fL
(2.46)
In DCM the output voltage increases as the load resistance R increases.
2.2.4
SelfLift N/O LuoConverter
Selflift negative output Luoconverters and their equivalent circuits during switchon and switchoff period are shown in Figure 2.6. It is the selflift circuit of the negative output Luoconverter. The function of capacitor C1 is to lift the voltage VC by a source voltage VI . S and D1 are on, and D is off during switchon period. D is on, and S and D1 are off during switchoff period. © 2003 by CRC Press LLC
1956_C02.fm Page 60 Monday, August 18, 2003 3:26 PM
2.2.4.1 Continuous Conduction Mode In the steady state, the average inductor voltages over a period are zero. Thus VC = VCO = VO During switchon period, the voltage across capacitor C1 is equal to the source voltage. Since we assume that C and C1 are sufficiently large, VC1 = VI . Inductor current iL increases in the switchon period and decreases in the switchoff period. The corresponding voltages across L are VI and −(VC − VC1 ) . Therefore, kTVI = (1 − k )T (VC − VC1 ) Hence, VO = VC = VCO =
1 V 1− k I
(2.47)
The voltage transfer gain in the CCM is M=
VO 1 = VI 1 − k
(2.48)
Since all the components are considered ideal, the power loss associated with all the circuit elements are neglected. Therefore the output power PO is considered to be equal to the input power PIN , VO I O = VI I I . Thus, II =
1 I 1− k O
The capacitor CO acts as a low pass filter so that I LO = I O . For the current and voltage variations and boundary condition, the following equations can be obtained by using a similar method that was used in the analysis of selflift Cúk converter. Current variations: ζ1 = Voltage variations: © 2003 by CRC Press LLC
k R , 2 M 2 fL
ζ2 =
k 1 2 16 f LO C
ξ=
k R 2 M 2 fL
1956_C02.fm Page 61 Monday, August 18, 2003 3:26 PM
ρ=
k 1 2 fCR
σ1 =
M 1 2 fC1R
ε=
k 1 128 f 3 LO CCO R
2.2.4.2 Discontinuous Conduction Mode Selflift negative output Luoconverters operate in the DCM if the current iD reduces to zero at t = T, then the circuit operates at the boundary of CCM and DCM. The variation ratio of the current iD is 1 when the circuit works at the boundary state. ξ=
k R =1 2 M 2 fL
Therefore the boundary between CCM and DCM is MB = k
R = 2 fLeq
kz N 2
(2.49)
where Leq refers to Leq = L and z N is the normalized load R / ( fLeq ) . When M > MB , the circuit operates in the DCM. In this case the diode current iD decreases to zero at t = t1 = [k + (1 – k)m]T, where KT < t1 < T and 0 < m < 1. m is the current filling factor and is defined as: m=
M2 1 = ξ k R 2 fL
(2.50)
In the discontinuous conduction mode, current iL increases during switchon and decreases during period from kT to (1 – k)mT. The voltages across L are VI and −(VC − VC1 ) . kTVI = (1 − k )mT (VC − VC1 ) and VC1 = VI
VC = VCO = VO
Hence, VO = [1 + © 2003 by CRC Press LLC
k ]V (1 − k )m I
or
VO = [1 + k 2 (1 − k )
R ]V 2 fL I
1956_C02.fm Page 62 Monday, August 18, 2003 3:26 PM
iI
+ VI –
–
vC
S iL
i LO
+ D1
C
L
LO
+
vC1 D –
iO + vO R–
CO
C1
a) Reverse SelfLift Negative Output LuoConverter iI
–
v C
+ VI –
i LO
+
iL
LO
+ vC1 –
L
iO + vO R–
CO
C1
b) The equivalent circuit during switchon
iI
+ VI –
– S
vC
i LO
+
C1 vC1
iL
L
LO
+ –
iO
C1
+ CO
vO R–
c) The equivalent circuit during switchoff FIGURE 2.7 Reverse selflift negative output Luoconverter and its equivalent circuits. (a) Reverse selflift negative output Luoconverter. (b) The equivalent circuit during switchon. (c) The equivalent circuit during switchoff.
So the real DC voltage transfer gain in the DCM is MDCM = 1 + k 2 (1 − k )
R 2 fL
(2.51)
We can see that in DCM, the output voltage increases as the load resistance R is increasing.
2.2.5
Reverse SelfLift N/O LuoConverter
Reverse selflift negative output Luoconverters and their equivalent circuits during switchon and switchoff period are shown in Figure 2.7. It is derived from the Zeta converter. During switchon period, S and D1 are on, D is off. During switchoff period, D is on, S and D1 are off. © 2003 by CRC Press LLC
1956_C02.fm Page 63 Monday, August 18, 2003 3:26 PM
2.2.5.1 Continuous Conduction Mode In steady state, the average inductor voltages over a period are zero. Thus VC1 = VCO = VO The inductor current iL increases in the switchon period and decreases in the switchoff period. The corresponding voltages across L are VI and −VC . Therefore kTVI = (1 − k )TVC Hence, VC =
k V 1− k I
(2.52)
voltage across C. Since we assume that C and C1 are sufficiently large, VC1 = VI + VC Therefore, VC1 = VI +
k 1 V = V 1− k I 1− k I
VO = VCO = VC1 =
1 V 1− k I
The voltage transfer gain in the CCM is M=
VO 1 = VI 1 − k
(2.53)
Since all the components are considered ideal, the power loss associated with all the circuit elements is neglected. Therefore the output power PO is considered to be equal to the input power PIN , VO I O = VI I I . Thus, II =
1 I 1− k O
The capacitor CO acts as a low pass filter so that I LO = I O . The charge of capacitor C1 increases during switchon and decreases during switchoff. Q+ = I C1−ON kT © 2003 by CRC Press LLC
Q− = I C1−OFF (1 − k )T = I O (1 − k )T
1956_C02.fm Page 64 Monday, August 18, 2003 3:26 PM
In a switch period, Q + = Q−
I C1−ON =
1− k 1− k = I I k C −OFF k O
The charge of capacitor C increases during switchon and decreases during switchoff. Q+ = I C −ON kT
Q− = I C −OFF (1 − k )T
In a switch period, Q + = Q− I C −ON = I C1−ON + I LO =
I C −OFF =
1− k 1 IO + IO = IO k k
1 k k 1 I C −ON = IO = I 1− k 1− k k 1− k O
Therefore, I L = I C −OFF =
1 I 1− k O
During switchoff period, iD = i L
ID = IL =
1 I 1− k O
For the current and voltage variations and the boundary condition, we can get the following equations using a similar method that was used in the analysis of selflift Cúk converter. Current variations: ζ1 =
k R 2 M 2 fL
ζ2 =
1 R 2 16 M f LO C1
ξ=
k R 2 M 2 fL
Voltage variations: ρ=
1 1 2 k fCR
© 2003 by CRC Press LLC
σ1 =
1 1 2 M fC1R
ε=
1 1 3 128 M f LO C1CO R
1956_C02.fm Page 65 Monday, August 18, 2003 3:26 PM
2.2.5.2 Discontinuous Conduction Mode Reverse selflift negative output Luoconverters operate in the DCM if the current iD reduces to zero during switchoff. As a special case, when iD decreases to zero at t = T, then the circuit operates at the boundary of CCM and DCM. The variation ratio of the current iD is 1 when the circuit works in the boundary state. ξ=
k R =1 2 2 M fLeq
The boundary between CCM and DCM is MB = k
R = 2 fLeq
kz N 2
where z N is the normalized load R / ( fLeq ) and Leq refers to Leq = L . When M > MB , the circuit operates at the DCM. In this case, diode current iD decreases to zero at t = t1 = [k + (1 – k) m] T where KT < t1 < T and 0 < m < 1 with m as the current filling factor. m=
1 M2 = ξ k R 2 fLeq
(2.54)
In the discontinuous conduction mode, current iL increases in the switchon period kT and decreases in the period from kT to (1 – k)mT. The corresponding voltages across L are VI and −VC . Therefore, kTVI = (1 − k )mTVC and VC1 = VCO = VO
VC1 = VI + VC
Hence, VO = [1 + © 2003 by CRC Press LLC
k ]V (1 − k )m I
1956_C02.fm Page 66 Monday, August 18, 2003 3:26 PM
or R VO = 1 + k 2 (1 − k ) V fL I 2
(2.55)
The voltage transfer gain in the DCM is MDCM = 1 + k 2 (1 − k )
R 2 fL
(2.56)
It can be seen that in DCM, the output voltage increases as the load resistance R is increasing.
2.2.6
SelfLift SEPIC
Selflift SEPIC and the equivalent circuits during switchon and switchoff period are shown in Figure 2.8. It is derived from SEPIC (with output filter). S and D1 are on, and D is off during switchon period. D is on, and S and D1 are off during switchoff period. 2.2.6.1 Continuous Conduction Mode In steady state, the average voltage across inductor L over a period is zero. Thus VC = VI . During switchon period, the voltage across capacitor C1 is equal to the voltage across C. Since we assume that C and C1 are sufficiently large, VC1 = VC = VI In steady state, the average voltage across inductor LO over a period is also zero. Thus
VC 2 = VCO = VO
The inductor current iL increases in the switchon period and decreases in the switchoff period. The corresponding voltages across L are VI and −(VC − VC1 + VC 2 − VI ) . Therefore kTVI = (1 − k )T (VC − VC1 + VC 2 − VI ) or
© 2003 by CRC Press LLC
1956_C02.fm Page 67 Monday, August 18, 2003 3:26 PM
iI
+
+ L
vC
–
–
vC1
i LO
+
LO
D
C
iO
+
+
VI
vC2
i L1
D1
L1
S
–
–
vO R –
CO
C2
a) SelfLift Sepic Converter iI
+
+ L
vC
–
–
i LO
vC1 +
iO
LO
C
+
+
VI
vC2
i L1 L1
S
–
–
vO R –
CO
C2
b) The equivalent circuit during switchon iI
+
+ L
vC
–
vC1
i LO
+
iO
LO
C
+
+
VI –
–
vC2
i L1 S
L1
–
C2
CO
vO R –
c) The equivalent circuit during switchoff FIGURE 2.8 Selflift sepic converter and its equivalent circuits. (a) Selflift sepic converter. (b) The equivalent circuit during switchon. (c) The equivalent circuit during switchoff.
kTVI = (1 − k )T (VO − VI ) Hence, VO =
1 V = VCO = VC 2 1− k I
(2.57)
The voltage transfer gain in the CCM is M=
VO 1 = VI 1 − k
(2.58)
Since all the components are considered ideal, the power loss associated with all the circuit elements is neglected. Therefore the output power PO is considered to be equal to the input power PIN , VO I O = VI I I . Thus, © 2003 by CRC Press LLC
1956_C02.fm Page 68 Monday, August 18, 2003 3:26 PM
II =
1 I = IL 1− k O
The capacitor CO acts as a low pass filter so that I LO = I O The charge of capacitor C increases during switchoff and decreases during switchon. Q− = I C −ON kT
Q+ = I C −OFF (1 − k )T = I I (1 − k )T
In a switch period, Q + = Q−
I C −ON =
1− k 1− k = I I k C −OFF k I
The charge of capacitor C2 increases during switchoff and decreases during switchon. Q− = I C 2−ON kT = I O kT
Q+ = I C 2−OFF (1 − k )T
In a switch period, Q + = Q−
IC 2−OFF =
k k = I I 1 − k C −ON 1 − k O
The charge of capacitor C1 increases during switchon and decreases during switchoff. Q+ = I C1−ON kT
Q− = I C1−OFF (1 − k )T
In a switch period, Q + = Q−
I C1−OFF = I C 2−OFF + I LO =
k 1 IO + IO = I 1− k 1− k O
Therefore I C1−ON = During switchoff, © 2003 by CRC Press LLC
1− k 1 I C1−OFF = I O k k
I L1 = I C1−ON − I C −ON = 0
1956_C02.fm Page 69 Monday, August 18, 2003 3:26 PM
iD = i L − i L 1 Therefore, ID = I I =
1 I 1− k O
For the current and voltage variations and the boundary condition, we can get the following equations using a similar method that is used in the analysis of selflift Cúk converter. Current variations: ζ1 =
k R 2 M 2 fL
ζ2 =
k R 16 f 2 LO C2
ξ=
k R 2 M 2 fLeq
where Leq refers to Leq =
LLO L + LO
Voltage variations: ρ=
M 1 2 fCR
σ1 =
M 1 2 fC1R
σ2 =
k 1 2 fC2 R
ε=
k 1 3 128 f LO C2 CO R
2.2.6.2 Discontinuous Conduction Mode Selflift Sepic converters operate in the DCM if the current iD reduces to zero during switchoff. As a special case, when iD decreases to zero at t = T, then the circuit operates at the boundary of CCM and DCM. The variation ratio of the current iD is 1 when the circuit works in the boundary state. ξ=
k R =1 2 2 M fLeq
Therefore the boundary between CCM and DCM is MB = k
© 2003 by CRC Press LLC
R = 2 fLeq
kz N 2
(2.59)
1956_C02.fm Page 70 Monday, August 18, 2003 3:26 PM
LLO where z N is the normalized load R / ( fLeq ) and Leq refers to Leq = . L +diode LO When M > MB , the circuit operates in the DCM. In this case the current iD decreases to zero at t = t1 = [k + (1 – k) m] T where KT < t1 < T and 0 < m < 1. m is defined as: m=
1 M2 = ξ k R 2 fLeq
(2.60)
In the discontinuous conduction mode, current iL increases during switchon and decreases in the period from kT to (1 – k)mT. The corresponding voltages across L are VI and −(VC − VC1 + VC 2 − VI ) . Thus, kTVI = (1 − k )T (VC − VC1 + VC 2 − VI ) and VC = VI
VC1 = VC = VI
VC 2 = VCO = VO
Hence, VO = [1 +
k ]V (1 − k )m I
or R VO = 1 + k 2 (1 − k ) V 2 fL eq I So the real DC voltage transfer gain in the DCM is MDCM = 1 + k 2 (1 − k )
R 2 fLeq
(2.61)
In DCM, the output voltage increases as the load resistance R is increasing.
2.2.7
Enhanced SelfLift P/O LuoConverter
Enhanced selflift positive output Luoconverter circuits and the equivalent circuits during switchon and switchoff periods are shown in Figure 2.9. They are derived from the selflift positive output Luoconverter in Figure 2.4 with swapping the positions of switch S and inductor L. © 2003 by CRC Press LLC
1956_C02.fm Page 71 Monday, August 18, 2003 3:26 PM
iI
+
– vC1 +
i LO
C1
LO
L
iO
D1 VI
+
D + vC
S –
–
CO
vO R –
C
FIGURE 2.9 Enhanced selflift P/O Luoconverter.
During switchon period, S and D1 are on, and D is off. Obtain: VC = VC1 and ∆iL =
VI kT L
During switchoff period, D is on, and S and D1 are off. ∆iL =
VC − VI (1 − k )T L
So that VC =
1 V 1− k I
The output voltage and current and the voltage transfer gain are VO = VI + VC1 = (1 +
IO =
M = 1+ © 2003 by CRC Press LLC
1 )V 1− k I
1− k I 2−k I
1 2−k = 1− k 1− k
(2.62)
(2.64)
(2.65)
1956_C02.fm Page 72 Monday, August 18, 2003 3:26 PM
Average voltages: VC =
1 V 1− k I
(2.66)
VC1 =
1 V 1− k I
(2.67)
Average currents:
IL =
I LO = I O
(2.68)
2−k I = II 1− k O
(2.69)
Therefore, VO 1 2−k = +1= VI 1 − k 1− k
2.3
(2.70)
Positive Output LuoConverters
Positive output Luoconverters perform the voltage conversion from positive to positive voltages using VL technique. They work in the first quadrant with large voltage amplification. Five circuits have been introduced in the literature: • • • • •
Elementary circuit Selflift circuit Relift circuit Triplelift circuit Quadruplelift circuit
The elementary circuit can perform stepdown and stepup DCDC conversion, which was introduced in previous section. Other positive output Luoconverters are derived from this elementary circuit, they are the selflift circuit, relift circuit, and multiplelift circuits (e.g., triplelift and quadruplelift circuits) shown in the corresponding figures. Switch S in these diagrams is a Pchannel power MOSFET device (PMOS), and S1 is an Nchannel power MOSFET device (NMOS). They are driven by a PWM switch signal with © 2003 by CRC Press LLC
1956_C02.fm Page 73 Monday, August 18, 2003 3:26 PM
repeating frequency f and conduction duty k. The switch repeating period is T = 1/f, so that the switchon period is kT and switchoff period is (1 – k)T. For all circuits, the load is usually resistive, R = VO/IO; the combined inductor L = L1L2/(L1 + L2); the normalized load is zN = R/fL. Each converter consists of a positive Luopump and a lowpass filter L2CO, and lift circuit (introduced in the following sections). The pump inductor L1 transfers the energy from source to capacitor C during switchoff, and then the stored energy on capacitor C is delivered to load R during switchon. Therefore, if the voltage VC is higher the output voltage VO should be higher. When the switch S is turned off, the current iD flows through the freewheeling diode D. This current descends in whole switchoff period (1 – k)T. If current iD does not become zero before switch S turned on again, this working state is defined as the continuous conduction mode (CCM). If current iD becomes zero before switch S turned on again, this working state is defined as the discontinuous conduction mode (DCM). Assuming that the output power is equal to the input power, PO = PIN
or
VO I O = VI I I
The voltage transfer gain in continuous mode is M=
VO I = I VI IO
ξ1 =
∆iL1 / 2 I L1
ξ2 =
∆iL 2 / 2 I L2
ζ=
∆iD / 2 I L1 + I L 2
Variation ratio of current iL1:
Variation ratio of current iL2:
Variation ratio of current iD:
Variation ratio of current iL2+j is χj = © 2003 by CRC Press LLC
∆iL 2+ j / 2 I L 2+ j
j = 1, 2, 3, …
1956_C02.fm Page 74 Monday, August 18, 2003 3:26 PM
Variation ratio of voltage vC: ρ=
∆vC / 2 VC
Variation ratio of voltage vCj: σj =
∆vCj / 2 VCj
j = 1, 2, 3, 4, …
Variation ratio of output voltage vCO: ε=
2.3.1
∆vO / 2 VO
Elementary Circuit
Elementary circuit and its switchon and off equivalent circuits are shown in Figure 2.10. Capacitor C acts as the primary means of storing and transferring energy from the input source to the output load via the pump inductor L1. Assuming capacitor C to be sufficiently large, the variation of the voltage across capacitor C from its average value VC can be neglected in steady state, i.e., vC(t) ≈ VC, even though it stores and transfers energy from the input to the output. 2.3.1.1 Circuit Description When switch S is on, the source current iI = iL1 + iL2. Inductor L1 absorbs energy from the source. In the mean time inductor L2 absorbs energy from source and capacitor C, both currents iL1 and iL2 increase. When switch S is off, source current iI = 0. Current iL1 flows through the freewheeling diode D to charge capacitor C. Inductor L1 transfers its stored energy to capacitor C. In the mean time current iL2 flows through the (CO – R) circuit and freewheeling diode D to keep itself continuous. Both currents iL1 and iL2 decrease. In order to analyze the circuit working procession, the equivalent circuits in switchon and off states are shown in Figures 2.10b, c, and d. Actually, the variations of currents iL1 and iL2 are small so that iL1 ≈ IL1 and iL2 ≈ IL2. The charge on capacitor C increases during switch off: Q+ = (1 – k)T IL1. © 2003 by CRC Press LLC
1956_C02.fm Page 75 Monday, August 18, 2003 3:26 PM
iS
– VC +
iC +
VI
Vs – + VL1
N
iL1
C
L1
+ VL2 – L2
iD
+
Io
iL2
iCo
D
VD
+
CoR
Vo
–
–
–
a) Circuit Diagram iS
VO
iC
VL2 +
iL1
+
+ VL1
VIN
L2
– iL2 Vo
VD
–
– b) Switchon VO
iC
VL2 +
L2
iL1 + VL1 –
L1
– iL2 Vo
iD
c) Switchoff VO iL1
+
L1
L2
VD
iL2 Vo
– d) Discontinuos mode
FIGURE 2.10 Elementary circuit of positive output Luoconverter(a) Circuit diagram. (b) Switchon. (c) Switchoff. (d) Discontinuous mode.
It decreases during switchon: Q – = kTIL2 © 2003 by CRC Press LLC
1956_C02.fm Page 76 Monday, August 18, 2003 3:26 PM
In a whole period investigation, Q+ = Q–. Thus, I L2 =
1− k I k L1
(2.71)
Since capacitor CO performs as a lowpass filter, the output current IL2 = IO
(2.72)
These two Equations (2.71) and (2.72) are available for all positive output LuoConverters. The source current is iI = iL1 + iL2 during switchon period, and iI = 0 during switchoff. Thus, the average source current II is I I = k × iI = k(iL1 + iL 2 ) = k(1 +
1− k ) I L1 = I L1 k
(2.73)
Therefore, the output current is IO =
1− k I k I
(2.74)
VO =
k V 1− k I
(2.75)
Hence, output voltage is
The voltage transfer gain in continuous mode is ME =
VO k = VI 1 − k
(2.76)
The curve of ME vs. k is shown in Figure 2.11. Current iL1 increases and is supplied by VI during switchon. It decreases and is inversely biased by –VC during switchoff. Therefore, kTVI = (1 − k )TVC The average voltage across capacitor C is VC = © 2003 by CRC Press LLC
k V = VO 1− k I
(2.77)
1956_C02.fm Page 77 Monday, August 18, 2003 3:26 PM
10
8
ME
6
4
2
0 0
0.2
0.4
k
0..6
0.8
1
FIGURE 2.11 Voltage transfer gain ME vs. k
2.3.1.2 Variations of Currents and Voltages To analyze the variations of currents and voltages, some voltage and current waveforms are shown in Figure 2.12. Current iL1 increases and is supplied by VI during switchon. It decreases and is inversely biased by –VC during switchoff. Therefore, its peaktopeak variation is ∆iL1 =
kTVI L1
Considering Equation (2.73), the variation ratio of the current iL1 is ξ1 =
∆iL1 / 2 kTVI 1− k R = = 2L1 I I 2 ME fL1 I L1
(2.78)
Current iL2 increases and is supplied by the voltage (VI + VC – VO) = VI during switchon. It decreases and is inversely biased by –VO during switchoff. Therefore its peaktopeak variation is ∆iL 2 =
kTVI L2
(2.79)
Considering Equation (2.72), the variation ratio of current iL2 is ξ2 = © 2003 by CRC Press LLC
∆iL 2 / 2 kTVI k R = = 2L2 I O 2 ME fL2 I L2
(2.80)
1956_C02.fm Page 78 Monday, August 18, 2003 3:26 PM
S on
VI
O
L1
S off
II DT VI L2
IO
IL1
− VO L1
VI L1
0 IL2
S on
V 1 − L
IL1 kII
S off
T
t
− VO L2
0 IL2
t1
T
t
− VO L2 L2
VI
IO 0 IS
t
VI L
0
t
IS L
VI
II+IO II
II 0
ID
II+IO
t
− VO L
0 ID
t − V L O
IO IO 0 IC
t IL2
0
t
IC1
IO 0
t
IL1
IL2
0 IL1
t
I1 VL1,VL2 VI
VL1,VL2 VI
VI
0
0
VO
VO
t
VS
t
VO VS
VO+VI
VO+VI
VI
VI
0
t
VD
0
t
VDR
VO+VI
VO+VI VO
VO 0
t
0
a
FIGURE 2.12 Some voltage and current waveforms of elementary circuit. © 2003 by CRC Press LLC
t
b
1956_C02.fm Page 79 Monday, August 18, 2003 3:26 PM
When switch is off, the freewheeling diode current is iD = iL1 + iL2 and ∆iD = ∆iL1 + ∆iL 2 =
kTVI kTVI kTVI (1 − k )TVO + = = L1 L2 L L
(2.81)
Considering Equation (2.71) and Equation (2.72), the average current in switchoff period is ID = IL1 + IL2 =
IO 1− k
The variation ratio of current iD is ζ=
∆iD / 2 (1 − k )2 TVO k(1 − k )R k2 R = = = 2LI O 2 ME fL ID ME 2 2 fL
(2.82)
The peaktopeak variation of vC is ∆vC =
Q + 1− k = TI I C C
Considering Equation (2.77), the variation ratio of vC is ρ=
∆vC / 2 (1 − k )TI I k 1 = = 2CVO 2 fCR VC
(2.83)
If L1 = L2 = 1 mH, C = CO = 20 µF, R = 10 Ω, f = 50 kHz and k = 0.5, we get ξ1 = ξ2 = 0.05, ζ = 0.025 and ρ = 0.025. Therefore, the variations of iL1, iL2, and vC are small. In order to investigate the variation of output voltage vO, we have to calculate the charge variation on the output capacitor CO, because Q = CO VO and ∆Q = CO ∆vO ∆Q is caused by ∆iL2 and corresponds to the area of the triangle with the height of half of ∆iL2 and the width of half of the repeating period T/2, which is shown in Figure 2.12. Considering Equation (2.79), ∆Q = © 2003 by CRC Press LLC
1 ∆iL 2 T T kTVI = 2 2 2 8 L2
1956_C02.fm Page 80 Monday, August 18, 2003 3:26 PM
Thus, the half peaktopeak variation of output voltage vO and vCO is ∆vO ∆Q kT 2VI = = 2 CO 8CO L2 The variation ratio of output voltage vO is ε=
∆vO / 2 kT 2 VI k 1 = = 2 VO 8CO L2 VO 8 ME f CO L2
(2.84)
If L2 = 1 mH, CO = 20 µF, f = 50 kHz and k = 0.5, we obtain that ε = 0.00125. Therefore, the output voltage VO is almost a real DC voltage with very small ripple. Because of the resistive load, the output current iO(t) is almost a real DC waveform with very small ripple as well, and IO = VO/R. 2.3.1.3 Instantaneous Values of Currents and Voltages Referring to Figure 2.12, the instantaneous values of the currents and voltages are listed below: 0 vS = VO + VI
for for
0 < t ≤ kT kT < t ≤ T
V + VO vD = I 0
for for
0 < t ≤ kT
(2.85)
(2.86)
kT < t ≤ T
VI v L1 = −VO
for for
0 < t ≤ kT kT < t ≤ T
(2.87)
VI vL 2 = −VO
for for
0 < t ≤ kT kT < t ≤ T
(2.88)
V i (0) + iL 2 (0) + I t iI = iS = L1 L 0
iL1
V i L 1 ( 0) + I t L1 = VO iL1 ( kT ) − (t − kT ) L1
© 2003 by CRC Press LLC
for for
for for
0 < t ≤ kT kT < t ≤ T
0 < t ≤ kT kT < t ≤ T
(2.89)
(2.90)
1956_C02.fm Page 81 Monday, August 18, 2003 3:26 PM
iL 2
V i L 2 ( 0) + I t L2 = VO iL 2 ( kT ) − (t − kT ) L2
for for
0 VO iD = iL1 ( kT ) + iL 2 ( kT ) − L (t − kT ) V i L 2 ( 0) + I t L2 iC ≈ VO −iL1 ( kT ) + (t − kT ) L1
iCO
0 < t ≤ kT kT < t ≤ T
for for
for for
V i L 2 ( 0) + I t − I O L2 ≈ VO −iL1 ( kT ) + (t − kT ) − I O L1
0 < t ≤ kT kT < t ≤ T
0 < t ≤ kT kT < t ≤ T
for for
0 < t ≤ kT kT < t ≤ T
(2.91)
(2.92)
(2.93)
(2.94)
where i L 1 ( 0) =
kI O (1 − k )VO − 1− k 2 fL1
iL1 ( kT ) =
kI O (1 − k )VO + 1− k 2 fL1
i L 2 ( 0) = I O −
(1 − k )VO 2 fL2
iL 2 ( kT ) = I O +
(1 − k )VO 2 fL2
2.3.1.4 Discontinuous Mode Referring to Figure 2.10d, we can see that the diode current iD becomes zero during switch off before next period switch on. The condition for discontinuous mode is ζ≥1 © 2003 by CRC Press LLC
1956_C02.fm Page 82 Monday, August 18, 2003 3:26 PM
20 continuous mode 10 k=0.9 5 ME
k=0.7 2 1
k=0.5
0.5 k=0.3 0.2
discontinuous mode k=0.1
0.1 1
2
5
10
20
50
100
200
500 1000
R/fL
FIGURE 2.13 The boundary between continuous and discontinuous modes and the output voltage vs. the normalized load zN = R/fL.
k2 R ≥1 ME 2 2 fL
i.e.,
ME ≤ k
or
z R =k N 2 fL 2
(2.95)
The graph of the boundary curve vs. the normalized load zN = R/fL is shown in Figure 2.13. It can be seen that the boundary curve is a monorising function of the parameter k. In this case the current iD exists in the period between kT and t1 = [k + (1 – k)mE]T, where mE is the filling efficiency and it is defined as: 2
mE =
ME 1 = ζ k2 R 2 fL
(2.96)
Considering Equation (2.95), therefore 0 < mE < 1. Since the diode current iD becomes zero at t = kT + (1 – k)mET, for the current iL, then kTVI = (1 – k)mETVC or VC = © 2003 by CRC Press LLC
k R VI = k(1 − k ) V (1 − k )mE 2 fL I
1956_C02.fm Page 83 Monday, August 18, 2003 3:26 PM
with R 1 ≥ 2 fL 1 − k and for the current iLO kT(VI + VC – VO) = (1 – k)mETVO Therefore, output voltage in discontinuous mode is VO =
k R VI = k(1 − k ) V (1 − k )mE 2 fL I
with R 1 ≥ 2 fL 1 − k
(2.97)
i.e., the output voltage will linearly increase during load resistance R increasing. The output voltage vs. the normalized load zN = R/fL is shown in Figure 2.13. It can be seen that larger load resistance R may cause higher output voltage in discontinuous conduction mode. 2.3.1.5 Stability Analysis Stability analysis is of vital importance for any converter circuit. Considering the various methods including the Bode plot, the rootlocus method in splane is used for this analysis. According to the circuit network and control system theory, the transfer function in sdomain for switchon and off are obtained: Gon = {
δVO ( s) sCR } = δVI ( s) on s 3 CCO L2 R + s 2 CL2 + s(C + CO )R + 1
(2.98)
Goff = {
δVO ( s) sCR } = δVI ( s) off s 3 CCO L2 R + s 2 CL2 + s(C + CO )R + 1
(2.99)
where s is the Laplace operator. From Equation (2.98) and Equation (2.99) in Laplace transform it can be seen that the elementary converter is a third order control circuit. The zero is determined by the equations where the numerator is equal to zero, and the poles are determined by the equation where the denominator is equal to zero. There is a zero at original point (0, © 2003 by CRC Press LLC
1956_C02.fm Page 84 Monday, August 18, 2003 3:26 PM
2.5
x 104
2 ×
1.5
R↑
1
× jωn
0.5 ×
0
×
0.5 1
× jωn
1.5
×
2 2.5 30
20
10
0
10
20
30
10
20
30
(a) Switchon x 104 2.5 2 1.5
×
R↑
1
× jωn
0.5 ×
×
0 0.5 1 1.5
× jωn ¥
2 2.5 30
20
10
0
(b) Switchoff
FIGURE 2.14 Stability analysis of elementary circuit. (a) Switchon. (b) Switchoff.
0) and three poles located in the lefthand half plane in Figure 2.14, so that this converter is stable. Since the equations to determine the poles are the equations with all positive real coefficients, according to the Gauss theorem, the three poles are one negative real pole and a pair of conjugate complex poles with negative real part. When the load resistance R increases and tends toward infinity, the three poles move. The real pole goes to the original point and eliminates with the zero. The pair of conjugate complex poles becomes a pair of imaginary poles located on the image axis. Assuming C = CO and L1 = L2 {L = L1 L2/(L1 + L2) or L2 = 2L}, the pair of imaginary poles are © 2003 by CRC Press LLC
1956_C02.fm Page 85 Monday, August 18, 2003 3:26 PM
s = ±j
C + C0 1 = ±j = ± jω n CC0 L2 CL
for switch on
(2.100)
s = ±j
C + C0 1 = ±j = ± jω n CC0 L2 CL
for switch off
(2.101)
where ω n = 1 CL is the converter normal angular frequency. They are locating on the stability boundary. Therefore, the circuit works in the critical state. This fact is verified by experiment and computer simulation. When R = ∞, the output voltage vO intends to be very high value. The output voltage VO cannot be infinity because of the leakage current penetrating the capacitor CO. 2.3.2
SelfLift Circuit
Selflift circuit and its switchon and off equivalent circuits are shown in Figure 2.15, which is derived from the elementary circuit. Comparing to Figure 2.10 and Figure 2.15, it can be seen that the pump circuit and filter are retained and there is only one capacitor C1 and one diode D1 more, as a lift circuit is added into the circuit. Capacitor C1 functions to lift the capacitor voltage VC by a source voltage Vin. Current iC1(t) = δ(t) is an exponential function. It has a large value at the power on moment, but it is small in the steady state because VC1 = Vin. 2.3.2.1 Circuit Description When switch S is on, the instantaneous source current is iI = iL1 + iL2 + iC1. Inductor L1 absorbs energy from the source. In the mean time inductor L2 absorbs energy from source and capacitor C. Both currents iL1 and iL2 increase, and C1 is charged to vC1 = VI. When switch S is off, the instantaneous source current is iI = 0. Current iL1 flows through capacitor C1 and diode D to charge capacitor C. Inductor L1 transfers its stored energy to capacitor C. In the mean time, current iL2 flows through the (CO – R) circuit, capacitor C1 and diode D, to keep itself continuous. Both currents iL1 and iL2 decrease. In order to analyze the circuit working procession, the equivalent circuits in switchon and off states are shown in Figures 2.15b, c and d. Assuming that capacitor C1 is sufficiently large, voltage VC1 is equal to VI in steady state. Current iL1 increases in switchon period kT, and decreases in switchoff period (1 – k)T. The corresponding voltages applied across L1 are VI and –(VC – VI) respectively. Therefore, kTVI = (1 − k )T (VC − VI ) © 2003 by CRC Press LLC
1956_C02.fm Page 86 Monday, August 18, 2003 3:26 PM
86
Advanced DC/DC Converters iC
+ V L2 –
S + iIN
Vs
–
L2
c iD1
V IN
D
iO iCO
iL2
iD
iL1 L1
+ VO –
R
D1 iC1
C1
CO
(a) circuit diagram iIN
iC
VO
L2
C + V L1 L 1 – V IN C1
V IN
–
+
VO
– VD + iC1
(b) switch on iC
– VO +
+
V L2 –
i L2
L2
C – VD +
VO
L1 V IN
(c) switch off – VC +
+
V L2 –
i L2
L2 i L1
– VD + VO
L1 V IN
(d) discontinuous mode FIGURE 2.15 Selflift circuit. (a) Circuit diagram. (b) Switch on. (c) Switch off. (d) Discontinuous mode.
© 2003 by CRC Press LLC
1956_C02.fm Page 87 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
87
10
8
MS
6
4
2
0
0.2
0
0.6
0.4
0.8
1
k
FIGURE 2.16 Voltage transfer gain MS vs. k.
VC =
Hence,
1 V 1− k I
(2.102)
Current iL2 increases in switchon period kT, and decreases in switchoff period (1 – k)T. The corresponding voltages applied across L2 are (VI + VC – VO) and –(VO – VI). Therefore, kT (VC + VI − VO ) = (1 − k )T (VO − VI ) Hence,
1 V 1− k I
(2.103)
I O = (1 − k )I I
(2.104)
VO =
and the output current is
Therefore, the voltage transfer gain in continuous mode is MS =
VO 1 = VI 1 − k
The curve of MS vs. k is shown in Figure 2.16. © 2003 by CRC Press LLC
(2.105)
1956_C02.fm Page 88 Monday, August 18, 2003 3:26 PM
88 2.3.2.2
Advanced DC/DC Converters Average Current IC1 and Source Current IS
During switchoff period (1 – k)T, current iC1 is equal to (iL1 + iL2), and the charge on capacitor C1 decreases. During switchon period kT, the charge increases, so its average current in switchon period is I C1 =
I 1− k 1− k (i L 1 + i L 2 ) = ( I L1 + I L 2 ) = O k k k
(2.106)
During switchoff period (1 – k)T the source current iI is 0, and in the switchon period kT, iI = iL1 + iL 2 + iC1 Hence,
I I = k ( i L 1 + i L 2 + iC 1 ) = k ( I L 1 + I L 2 + I C 1 ) = k( I L1 + I L 2 )(1 +
I I 1− k 1 ) = k L2 = O k 1− k k 1− k
(2.107)
2.3.2.3 Variations of Currents and Voltages To analyze the variations of currents and voltages, some voltage and current waveforms are shown in Figure 2.17. Current iL1 increases and is supplied by VI during switchon period kT. It decreases and is reversely biased by –(VC – VI) during switchoff. Therefore, its peaktopeak variation is ∆iL1 =
kTVI L1
Hence, the variation ratio of current iL1 is ξ1 =
∆iL1 / 2 kVI T 1− k R = = 2 kL1 I I 2 MS fL1 I L1
(2.108)
Current iL2 increases and is supplied by the voltage (VI + VC – VO) = VI in switchon period kT. It decreases and is inversely biased by –(VC – VI) during switchoff. Therefore its peaktopeak variation is ∆iL 2 =
kTVI L2
Thus, the variation ratio of current iL2 is ξ2 = © 2003 by CRC Press LLC
∆iL 2 / 2 kVI T k R = = 2L2 I O 2 MS fL2 I L2
(2.109)
1956_C02.fm Page 89 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
89
S on
VI
L1
O
L
0 I L2
t
I
1
T VO – V I L2
–
V
kT VI L2
IO
I L1
VO – V I L1
II
0 IL2
–
S off
V
VI L1
S on –
I L1 kI I
S off
t1
T
t
– V O – L2 L 2 VI
VI
DQ
IO 0
0 II =I S
t V
II =I S
t
t) VI + d( L
II
t) d(
+
I
L
II
0 ID
–
t
VO – V I L
0 ID
t – V O L
IO
–V
I
IO 0
t
I D1 IO k
d(t) IO k
0 I C1
0 ID
t
t
d(t)
0
t
d(t)
IO k
I C1 0
0 –(II+I O )
IC1 IO
d(t)
t
V O–V I L
V O –V I L
IL2
I C1
0
t
–I L1
t
I L2
0 –I L1
t
–I1 V L1 ,V L2 VI
V L2 VI
VI
0
0
–(VO –VI)
–VO
t
VS
VS
VO
VO
VI
VI
0
t
–(VO –VI)
0
t
V D1
V D1
VO
VO
t
VI
(V O –VI)
0
t
VD
0
t
VD
VO
VO kV O
kV O 0
t
0
(a)
FIGURE 2.17 Some voltage and current waveforms of selflift circuit. © 2003 by CRC Press LLC
t
(b)
1956_C02.fm Page 90 Monday, August 18, 2003 3:26 PM
90
Advanced DC/DC Converters
When switch is off, the freewheeling diode current is iD = iL1 + iL2 and ∆iD = ∆iL1 + ∆iL 2 =
kTVI k(1 − k )VO = T L L
(2.110)
Considering Equation (2.71) and Equation (2.72), ID = IL1 + IL2 =
IO 1− k
The variation ratio of current iD is ζ=
∆iD / 2 k(1 − k )2 TVO k R = = ID 2LI O MS 2 2 fL
(2.111)
The peaktopeak variation of voltage vC is Q + (1 − k )TI L1 1 − k = = kTI I C C C
∆vC = Hence, its variation ratio is ρ=
∆vC / 2 (1 − k )2 kI I T k = = VC 2CVI 2 fCR
(2.112)
The charge on capacitor C1 increases during switchon, and decreases during switchoff period (1 – k)T by the current (IL1 + IL2). Therefore, its peaktopeak variation is ∆vC1 =
(1 − k )T ( I L1 + I L 2 ) I O = C1 fC1
Considering VC1 = VI, the variation ratio of voltage vC1 is σ=
∆vC1 / 2 IO MS = = VC1 2 fC1VI 2 fC1R
(2.113)
If L1 = L2 = 1mH, C = C1 = CO = 20 µF, R = 40 Ω, f = 50 kHz and k = 0.5, we obtained that ξ1 = 0.1, ξ2 = 0.1, ζ = 0.1, ρ = 0.006 and σ = 0.025. Therefore, the variations of iL1, iL2, vC1 and vC are small. Considering Equation (2.84) and Equation (2.105), the variation ratio of output voltage vO is © 2003 by CRC Press LLC
1956_C02.fm Page 91 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
ε=
91 ∆vO / 2 kT 2 VI k 1 = = 2 VO 8CO L2 VO 8 MS f CO L2
(2.114)
If L2 = 1 mH, C0 = 20 µF, f = 50 kHz and k = 0.5, ε = 0.0006. Therefore, the output voltage VO is almost a real DC voltage with very small ripple. Because of the resistive load, the output current iO(t) is almost a real DC waveform with very small ripple as well, and IO = VO/R. 2.3.2.4 Instantaneous Value of the Currents and Voltages Referring to Figure 2.17, the instantaneous values of the currents and voltages are listed below: 0 vS = VO
for for
0 < t ≤ kT kT < t ≤ T
V vD = O 0
for for
0 < t ≤ kT kT < t ≤ T
0 vD1 = VO
for for
0 < t ≤ kT kT < t ≤ T
VI v L1 = v L 2 = −(VO − VI )
for for
(2.115)
(2.116)
(2.117)
0 < t ≤ kT kT < t ≤ T
V i (0) + iL 2 (0) + δ(t) + I t iI = iS = L1 L 0
for for
iL1
V i L 1 ( 0) + I t L1 = VO − VI iL1 ( kT ) − (t − kT ) L1
for for
iL 2
V i L 2 ( 0) + I t L2 = VO − VI iL 2 ( kT ) − (t − kT ) L2
for for
© 2003 by CRC Press LLC
(2.118)
0 < t ≤ kT kT < t ≤ T
0 < t ≤ kT kT < t ≤ T
0 < t ≤ kT kT < t ≤ T
(2.119)
(2.120)
(2.121)
1956_C02.fm Page 92 Monday, August 18, 2003 3:26 PM
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Advanced DC/DC Converters
0 VO − VI iD = (t − kT ) iL1 ( kT ) + iL 2 ( kT ) − L δ(t) iD1 = 0
for for
for for
0 < t ≤ kT kT < t ≤ T
V i L 2 ( 0) + I t L2 iC = VO − VI iL1 ( kT ) − (t − kT ) L1
for for
V iL 2 (0) + I t − IO L2 = VO − VI iL 2 ( kT ) − (t − kT ) − IO L2
(2.122)
(2.123)
0 < t ≤ kT kT < t ≤ T
δ(t) VO − VI iC 1 = (t − kT ) −iL1 ( kT ) − iL 2 ( kT ) + L
iCO
0 < t ≤ kT kT < t ≤ T
for for
for for
(2.124)
0 < t ≤ kT kT < t ≤ T
0 < t ≤ kT kT < t ≤ T
(2.125)
(2.126)
where iL1(0) = k II – k VI/2 f L1 iL1(kT) = k II + k VI/2 f L1 and iL2(0) = IO – k VO/2 f M L2 iL2(kT) = IO + k VO/2 f M L2 2.3.2.5 Discontinuous Mode Referring to Figure 2.15d, we can see that the diode current iD becomes zero during switch off before next period switch on. The condition for discontinuous mode is ζ ≥ 1, i.e.,
© 2003 by CRC Press LLC
k R ≥1 MS 2 2 fL
1956_C02.fm Page 93 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
93
30 continuous mode
20 k=0.9 10
MS
8 k=0.8 5 3 k=0.5
2
k=0.33 1.5 k=0.1 1
discontinuous mode 24.7
13.56
62.5 R/fL
222
842
FIGURE 2.18 The boundary between CCM and DCM and the output voltage vs. the normalized load zN = R/fL.
MS ≤ k
or
z R = k N 2 fL 2
(2.127)
The graph of the boundary curve vs. the normalized load zN = R/fL is shown in Figure 2.18. It can be seen that the boundary curve has a minimum value of 1.5 at k = ⅓. In this case the current iD exists in the period between kT and t1 = [k + (1 – k)mS]T, where mS is the filling efficiency and it is defined as: mS =
MS 2 1 = ζ k R 2 fL
(2.128)
Considering Equation (2.127), therefore 0 < mS < 1. Since the diode current iD becomes zero at t = kT + (1 – k)mST, for the current iL kTVI = (1 – k)mST(VC – VI) or VC = [1 + © 2003 by CRC Press LLC
k R ]V = [1 + k 2 (1 − k ) ]V (1 − k )mS I 2 fL I
1956_C02.fm Page 94 Monday, August 18, 2003 3:26 PM
94
Advanced DC/DC Converters
with k
R 1 ≥ 2 fL 1 − k
and for the current iLO kT(VI + VC –VO) = (1 – k)mST(VO – VI) Therefore, output voltage in discontinuous mode is VO = [1 +
k R ]V = [1 + k 2 (1 − k ) ]V (1 − k )mS I 2 fL I
with
k
R 1 ≥ 2 fL 1 − k
(2.129)
i.e., the output voltage will linearly increase while load resistance R increases. The output voltage VO vs. the normalized load zN = R/fL is shown in Figure 2.18. Larger load resistance R causes higher output voltage in discontinuous conduction mode. 2.3.2.6 Stability Analysis Taking the rootlocus method in splane for stability analysis the transfer functions in sdomain for switchon and off are obtained: Gon = {
Goff = {
δVO ( s) sCR } on = 3 2 δVI ( s) s CCO L2 R + s CL2 + s(C + CO )R + 1
(2.130)
δVO ( s) sCR (2.131) } off = 3 2 δVI ( s) s (C + C1 )CO L2 R + s (C + C1 )L2 + s(C + C1 + CO )R + 1
where s is the Laplace operator. From Equations (2.130) and (2.131) in Laplace transform it can be seen that the selflift converter is a third order control circuit. The zero is determined by the equation when the numerator is equal to zero, and the poles are determined by the equation when the denominator is equal to zero. There is a zero at origin point (0, 0) and three poles located in the lefthand half plane in Figure 2.19, so that the selflift converter is stable. Since the equations to determine the poles are the equations with all positive real coefficients, according to the Gauss theorem, the three poles are one negative real pole and a pair of conjugate complex poles with negative real part. When the load resistance R increases and tends towards infinity, the three poles move. The real pole goes to the origin point and eliminates with the zero. The pair of conjugate complex poles becomes a pair of imaginary poles locating on the image axis. Assuming C = C1 = CO and L1 = L2 {L = L1 L2/(L1 + L2) or L2 = 2L}, the pair of imaginary poles are © 2003 by CRC Press LLC
1956_C02.fm Page 95 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
2.5
95
x 104
2 ×
1.5
R↑
× jω
1 0.5 ×
0
×
0.5 1
× jωn
1.5
×
2 2.5 30
20
10
0
10
20
30
20
30
(a) Switch on x 104 2.5 ×
2 1.5
R↑ →
1
×
j(√3/2)ωn
0.5 ×
0
→
0.5 1
→
× j(√3/2)ω n
1.5 ×
2 2.5 30
20
10
0
10
(b) Switch off FIGURE 2.19 Stability analysis of selflift circuit. (a) Switchon. (b) Switchoff.
C + C0 1 = ±j = ± jω n for switch on CC0 L2 CL
(2.132)
C + C1 + C0 3 3 = ±j = ±j ω for switch off (C + C1 )C0 L2 4CL 2 n
(2.133)
s = ±j
s = ±j
© 2003 by CRC Press LLC
1956_C02.fm Page 96 Monday, August 18, 2003 3:26 PM
96
Advanced DC/DC Converters
where ω n = 1 CL is the selflift converter normal angular frequency. They are locating on the stability boundary. Therefore, the circuit works in the critical state. This fact is verified by experiment and computer simulation. When R = 8, the output voltage vO intends to be a very high value. The output voltage VO cannot be infinity because of the leakage current penetrating the capacitor CO. 2.3.3
ReLift Circuit
Relift circuit, and its switchon and off equivalent circuits are shown in Figure 2.20, which is derived from the selflift circuit. It consists of two static switches S and S1; three diodes D, D1, and D2; three inductors L1, L2 and L3; four capacitors C, C1, C2, and CO. From Figure 2.10, Figure 2.15, and Figure 2.20, it can be seen that the pump circuit and filter are retained and there are one capacitor C2, one inductor L3 and one diode D2 added into the relift circuit. The lift circuit consists of D1C1L3D2S1C2. Capacitors C1 and C2 perform characteristics to lift the capacitor voltage VC by twice the source voltage VI. L3 performs the function as a ladder joint to link the two capacitors C1 and C2 and lift the capacitor voltage VC up. Current iC1(t) = δ1(t) and iC2(t) = δ2(t) are exponential functions. They have large values at the moment of power on, but they are small because vC1 = vC2 = VI in steady state. 2.3.3.1 Circuit Description When switches S and S1 turn on, the source instantaneous current iI = iL1 + iL2 + iC1 + iL3 + iC2. Inductors L1 and L3 absorb energy from the source. In the mean time inductor L2 absorbs energy from source and capacitor C. Three currents iL1, iL3 and iL2 increase. When switches S and S1 turn off, source current iI = 0. Current iL1 flows through capacitor C1, inductor L3, capacitor C2 and diode D to charge capacitor C. Inductor L1 transfers its stored energy to capacitor C. In the mean time, current iL2 flows through the (CO – R) circuit, capacitor C1, inductor L3, capacitor C2 and diode D to keep itself continuous. Both currents iL1 and iL2 decrease. In order to analyze the circuit working procession, the equivalent circuits in switchon and off states are shown in Figure 2.20b, c, and d. Assuming capacitor C1 and C2 are sufficiently large, and the voltages VC1 and VC2 across them are equal to VI in steady state. Voltage vL3 is equal to VI during switchon. The peaktopeak variation of current iL3 is ∆iL 3 =
VI kT L3
(2.134)
This variation is equal to the current reduction when it is switchoff. Suppose its voltage is –VL3–off, so © 2003 by CRC Press LLC
1956_C02.fm Page 97 Monday, August 18, 2003 3:26 PM
VoltageLift Converters –V C +
S i IN
+
97
–
Vs
iC
D1
D2
VI L1
i CO
i L2
iD
i D1
i L1
–
L2
c D
N
V L2
+
i C1
C1
C2
L3
i L2
R
CO
+ VO –
+ V S1 –
S1
(a) circuit diagram – VO + iIN
iL1
V IN
+ V L2 –
C
i L2
L2
VD
VO
+ V L1 –
V L 1 IN C1
V IN i L3
C2
L3
(b) switch on – VO +
+ V L2 –
C
L2
i L1 L1
i L2
VO V IN C1
V L 3 IN
i L3
C2
(c) switch off – VO +
+ V L2 –
C
L2
i L2
VD iL1
VO V L 1 CIN 1
iL3
V IN L3 C 2
(d) discontinuous mode FIGURE 2.20 Relift circuit: (a) circuit diagram; (b) switch on; (c) switch off; (d) discontinuous mode.
∆iL 3 =
VL 3−off (1 − k )T L3
Thus, during switchoff the voltage drop across inductor L3 is © 2003 by CRC Press LLC
1956_C02.fm Page 98 Monday, August 18, 2003 3:26 PM
98
Advanced DC/DC Converters
VL 3−off =
k V 1− k I
(2.135)
Current iL1 increases in switchon period kT, and decreases in switchoff period (1 – k)T. The corresponding voltages applied across L1 are VI and –(VC – 2VI – VL3–off). Therefore, kTVI = (1 − k )T (VC − 2VI − VL 3−off ) VC =
Hence,
2 V 1− k I
(2.136)
Current iL2 increases in switchon period kT, and it decreases in switchoff period (1 – k)T. The corresponding voltages applied across L2 are (VI + VC – VO) and –(VO – 2VI – VL3–off). Therefore, kT (VC + VI − VO ) = (1 − k )T (VO − 2VI − VL 3−off ) Hence,
VO =
2 V 1− k I
(2.137)
IO =
1− k I 2 I
(2.138)
and the output current is
The voltage transfer gain in continuous mode is MR =
VO 2 = VI 1 − k
(2.139)
The curve of MR vs. k is shown in Figure 2.21. 2.3.3.2 Other Average Currents Considering Equation (2.71), I L1 =
and © 2003 by CRC Press LLC
k k IO = I I 1− k 2
I L 3 = I L1 + I L 2 =
1 I 1− k O
(2.140)
(2.141)
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VoltageLift Converters
99
20
16
MR
12
8
4
0
0.2
0
0.6
0.4
0.8
1
k
FIGURE 2.21 Voltage transfer gain MR vs. k.
Currents iC1 and iC2 equal to (iL1+ iL2) during switchoff period (1 – k)T, and the charges on capacitors C1 and C2 decrease, i.e., iC1 = iC2 = (iL1+ iL2) =
1 I 1− k O
The charges increase during switchon period kT, so their average currents are I C1 = I C 2 =
I 1− k 1− k k ( I L1 + I L 2 ) = ( + 1)I O = O k k 1− k k
(2.142)
During switchoff the source current iI is 0, and in the switchon period kT, it is iI = iL1 + iL 2 + iC1 + iL 3 + iC 2 Hence, I I = kiI = k( I L1 + I L 2 + I C1 + I L 3 + I C 2 ) = k[2( I L1 + I L 2 ) + 2 I C1 ] = 2 k( I L1 + I L 2 )(1 +
© 2003 by CRC Press LLC
I 1 2 1− k ) = 2k L2 = I 1− k k 1− k O k
(2.143)
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100
Advanced DC/DC Converters S on IL1 K I1 2 0 IL2
S off
(i)
S on IL1
(ii)
kT
T
(iii)
t
(iv)
K I1 2 0 IL2
S off
(i)
(ii)
T1
T
(iv)
IO 0 II=IS
t
(v)
t
0 II=IS
t (v)
II 0 ID
(vi)
(vii)
t
0 ID
t (viii)
IO IO 0 ID1
t
0 ID
d(t)
t
d(t)
0
0
t a
t b
FIGURE 2.22 Some voltage and current waveforms of relift circuit.
2.3.3.3 Variations of Currents and Voltages To analyze the variations of currents and voltages, some voltage and current waveforms are shown in Figure 2.22. Current iL1 increases and is supplied by VI during switchon period kT. It decreases and is reversely biased by –(VC – 2VI – VL3) during switchoff period (1 – k)T. Therefore, its peaktopeak variation is ∆iL1 =
kTVI L1
Considering Equation (2.140), the variation ratio of current iL1 is ξ1 =
∆iL1 / 2 kVI T 1 − k R = = I L1 kL1 I I 2 M R fL1
(2.144)
Current iL2 increases and is supplied by the voltage (VI + VC – VO) = VI during switchon period kT. It decreases and is reversely biased by –(VO –2VI – VL3) during switchoff. Therefore, its peaktopeak variation is © 2003 by CRC Press LLC
1956_C02.fm Page 101 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
101
d'(t) IC1
IC1
0
d'(t)
0 t
(i)
t (ii)
(ii) IC IL2
IC1
IO 0 I1
0
t
IL2
VL1,VL2 VI
IL2
IL2
t
VL2 VI
VI
0
0
(VO2VI)
VO
t
t
(VO2VI) VS
VS
VOVI VI
VI
0
0
t
VD1
t
VD1 VOVI
VOVI 0 VD
0 VD
t
t
VO
VO
kVO kVO 0
a
0
t
b
t
FIGURE 2.22 (continued)
∆iL 2 =
kTVI L2
Considering Equation (2.72), the variation ratio of current iL2 is ξ2 = © 2003 by CRC Press LLC
∆iL 2 / 2 kTVI k R = = 2L2 I O 2 M R fL2 I L2
(2.145)
1956_C02.fm Page 102 Monday, August 18, 2003 3:26 PM
102
Advanced DC/DC Converters
When switch is off, the freewheeling diode current is iD = iL1 + iL2 and ∆iD = ∆iL1 + ∆iL 2 =
kTVI k(1 − k )VO = T L 2L
(2.146)
Considering Equation (2.71) and Equation (2.72), ID = IL1 + IL2 =
IO 1− k
The variation ratio of current iD is ζ=
∆iD / 2 k(1 − k )2 TVO k(1 − k )R k R = = = 4LI O 2 M R fL ID M R 2 fL
(2.147)
Considering Equation (2.134) and Equation (2.141), the variation ratio of current iL3 is χ1 =
∆iL 3 / 2 kVI T k R = = 2 1 I L3 M R fL3 2 L3 IO 1− k
(2.148)
If L1 = L2 = 1 mH, L3 = 0.5 mH, R = 160 Ω, f = 50 kHz and k = 0.5, we obtained that ξ1 = 0.2, ξ2 = 0.2, ζ= 0.1 and χ1 = 0.2. Therefore, the variations of iL1, iL2 and iL3 are small. The peaktopeak variation of vC is ∆vC =
Q + 1− k k(1 − k ) = TI L1 = TI I C C 2C
Considering Equation (2.136), the variation ratio is ρ=
∆vC / 2 k(1 − k )TI I k = = VC 4CVO 2 fCR
(2.149)
The charges on capacitors C1 and C2 increase during switchon period kT, and decrease during switchoff period (1 – k)T by the current (IL1 + IL2). Therefore their peaktopeak variations are
© 2003 by CRC Press LLC
∆vC1 =
(1 − k )T ( I L1 + I L 2 ) (1 − k )I I = C1 2C1 f
∆vC 2 =
(1 − k )T ( I L1 + I L 2 ) (1 − k )I I = C2 2C2 f
1956_C02.fm Page 103 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
103
Considering VC1 = VC2 = VI, the variation ratios of voltages vC1 and vC2 are σ1 =
∆vC1 / 2 (1 − k )I I MR = = 4 fC1VI 2 fC1R VC1
(2.150)
σ2 =
∆vC 2 / 2 (1 − k )I I MR = = 4VI C2 f 2 fC2 R VC 2
(2.151)
Considering Equation (2.84), the variation ratio of output voltage vO is ε=
∆vO / 2 kT 2 VI k 1 = = 2 VO 8CO L2 VO 8 M R f CO L2
(2.152)
If C = C1 = C2 = CO = 20 µF, L2 = 1 mH, R = 160 Ω, f = 50 kHz and k = 0.5, we obtained that ρ = 0.0016, σ1 = σ2 = 0.0125, and ε = 0.0003. The ripples of vC, vC1, vC2 and vCO are small. Therefore, the output voltage vO is almost a real DC voltage with very small ripple. Because of the resistive load, the output current iO(t) is almost a real DC waveform with very small ripple as well, and IO = VO/R. 2.3.3.4 Instantaneous Value of the Currents and Voltages Referring to Figure 2.22, the instantaneous current and voltage values are listed below: 0 vS = VO
for for
0 < t ≤ kT kT < t ≤ T
(2.153)
V vD = O 0
for for
0 < t ≤ kT kT < t ≤ T
(2.154)
0 vD1 + vD 2 = VO
for for
0 < t ≤ kT kT < t ≤ T
(2.155)
VI k vL 3 = − VI 1 − k
for for
0 < t ≤ kT kT < t ≤ T
(2.156)
VI k v L1 = v L 2 = −[V − (2 − )V ] O 1− k I © 2003 by CRC Press LLC
for
0 < t ≤ kT
for
kT < t ≤ T
(2.157)
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Advanced DC/DC Converters
V V i (0) + iL 2 (0) + iL 3 (0) + δ 1 (t) + δ 2 (t) + I t + I t for 0 < t ≤ kT (2.158) iI = iS = L1 L L3 0 for kT < t ≤ T
iL 3
iL1
V i L 1 ( 0) + I t L1 k = )V VO − (2 − 1 − k I (t − kT ) ( ) − i kT L1 L1
for for
0 < t ≤ kT kT < t ≤ T
(2.159)
iL 2
V i L 2 ( 0) + I t L2 k = )V VO − (2 − 1 − k I (t − kT ) ( ) − i kT L2 L2
for for
0 < t ≤ kT kT < t ≤ T
(2.160)
V i L 3 ( 0) + I t L3 k = V 1 − k I (t − kT ) iL 3 ( kT ) − L 3
for for
0 < t ≤ kT kT < t ≤ T
0 k iD = )V VO − (2 − 1 − k I (t − kT ) iL1( kT ) + iL 2 ( kT ) − L δ (t) + δ 2 (t) iD1 = 1 0 δ (t) iD2 = 2 0
for for for for
© 2003 by CRC Press LLC
for 0 < t ≤ kT for kT < t ≤ T
0 < t ≤ kT
(2.162)
(2.163)
kT < t ≤ T
0 < t ≤ kT kT < t ≤ T
V i L 2 ( 0) + I t L2 iC = VO − VI iL1 ( kT ) − (t − kT ) L1
(2.161)
(2.164)
for for
0 < t ≤ kT kT < t ≤ T
(2.165)
1956_C02.fm Page 105 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
105
δ 1 (t ) k iC1 = VO − (2 + )V − k I (t − kT ) 1 −iL1( kT ) − iL 2 ( kT ) + L
for 0 < t ≤ kT for kT < t ≤ T
iC 2
δ 2 (t ) for 0 < t ≤ kT k = )V VO − (2 + 1 − k I (t − kT ) for kT < t ≤ T −iL1 ( kT ) − iL 2 ( kT ) + L
iCO
V i L 2 ( 0) + I t − I O L2 k = )V VO − (2 + 1 − k I (t − kT ) − I O iL 2 ( kT ) − L2
for for
(2.166)
(2.167)
0 < t ≤ kT (2.168) kT < t ≤ T
where iL1(0) = k II/2 – k VI/2 f L1, iL1(kT) = k II/2 + k VI/2 f L1, and iL2(0) = IO – k VI/2 f L2, iL2(kT) = IO + k VI/2 f L2, and iL3(0) = IO + k II/2 – k VI/2 f L3, iL3(kT) = IO + k II/2 + k VI/2 f L3. 2.3.3.5 Discontinuous Mode Referring to Figure 2.20d, we can see that the diode current iD becomes zero during switch off before next period switch on. The condition for discontinuous mode is ζ≥1 i.e., k R ≥1 M R 2 fL
or
MR ≤ k
R = k zN fL
(2.169)
The graph of the boundary curve vs. the normalized load zN = R/fL is shown in Figure 2.23. It can be seen that the boundary curve has a minimum value of 3.0 at k = ⅓. In this case the current iD exists in the period between kT and t1 = [k + (1 – k)mR]T, where mR is the filling efficiency and it is defined as:
© 2003 by CRC Press LLC
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106
Advanced DC/DC Converters 60 k=0.95
continuous mode
40 k=0.9 20
MR
k=0.8
10 6 4 3
k=0.5 k=0.33 k=0.1
2
27 32
discontinuous mode 50
125 R/fL
444
1684
FIGURE 2.23 The boundary between continuous and discontinuous modes and the output voltage vs. the normalized load zN = R/fL.
mR =
2 1 MR = ζ k R fL
(2.170)
Considering Equation (2.169), therefore 0 < mR < 1. Since the diode current iD becomes zero at t = kT + (1 – k)mRT, for the current iL kTVI = (1 – k)mRT(VC – 2VI – VL3–off) or VC = [2 +
k k k R + ]VI = [2 + + k 2 (1 − k ) ]V 1 − k (1 − k )mR 1− k 4 fL I
with
k
2 R ≥ fL 1 − k
and for the current iLO kT(VI + VC – VO) = (1 – k)mRT(VO – 2VI – VL3–off) Therefore, output voltage in discontinuous mode is VO = [2 + © 2003 by CRC Press LLC
k k k R + ]V = [2 + + k 2 (1 − k ) ]V 1 − k (1 − k )mR I 1− k 4 fL I
1956_C02.fm Page 107 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
with
107
k
2 R ≥ fL 1 − k
(2.171)
i.e., the output voltage will linearly increase during load resistance R increasing. The output voltage vs. the normalized load zN = R/fL is shown in Figure 2.23. Larger load resistance R may cause higher output voltage in discontinuous mode. 2.3.3.6 Stability Analysis Stability analysis is of vital importance for any converter circuit. According to the circuit network and control systems theory, the transfer functions in sdomain for switchon and off states are obtained: Gon = {
Goff = {
=
=
δVO ( s) sCR } = δVI ( s) on s 3 L2 CCO R + s 2 L2 C + s(C + CO )R + 1
(2.172)
δVO ( s) } δVI ( s) off s(C1 + C2 ) + s 3 L3 C1C2 R sC 1 + sCO R s 2 C1C2
s(C1 + C2 ) + s 3 L3 C1C2 R + sL2 + s 2 L2 CO R 2 sC 1 + sCO R s C1C2 2 3 + s(C1 + C2 ) + s L3 C1C2 + R + sL2 + s L2 CO R 1 + sCO R s 2 C1C2 sCR[(C1 + C2 ) + s 2 L3 C1C2 ] sC[(C1 + C2 ) + s 2 L3 C1C2 ][R + sL2 + s 2 L2 CO R] + (1 + sCO R)[(C1 + C2 ) + s 2 L C C ] + sC C [R + sL + s 2 L C R] 3 1 2 1 2 2 2 O
(2.173)
where s is the Laplace operator. From Equation (2.172) and Equation (2.173) in Laplace transform we can see that the relift converter is a third order control circuit for switchon state and a fifth order control circuit for switchoff state. For the switchon state, the zeros are determined by the equation when the numerator of Equation (2.172) is equal to zero, and the poles are determined by the equation when the denominator of Equation (2.172) is equal to zero. There is a zero at the origin point (0, 0). Since the equation to determine the poles is the equation with all positive real coefficients, according to the Gauss theorem, the three poles are: one negative real pole (p3) © 2003 by CRC Press LLC
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108
Advanced DC/DC Converters
3
x 104
×
2
→
1 P3
R↑ →
×
0
P1
× jωn
z
P3 1
→
P2
× jω n
P2 ×
2
3 30
20
10
0
10
20
30
10
20
30
(a) Switchon 2.5
x 104
2 1.5
P1 ×
P3 ×
P1 z1
0.5 P5
R↑
×
0 0.5
P4
×
n
z3
× ° P 4
×
n
P4
z2
1 1.5
× jωn
j√(2ω ) °× j0.88ω
1
× j0.88ωn
°× j√(2ω ) n
jωn
P2
P2
2 2.5 30
20
10
0
(b) Switchoff FIGURE 2.24 Stability analysis of relift circuit. (a) Switchon. (b) Switchoff.
and a pair of conjugate complex poles with negative real part (p1,2). The three poles are located in the left half plane in Figure 2.24, so that the relift converter is stable. When the load resistance R increases and intends towards infinity, the three poles move. The real pole goes to the origin point and eliminates with the zero. The pair of conjugate complex poles becomes a pair of imaginary poles locating on the imaginary axis. Assuming that all capacitors have same capacitance C, and L1 = L2 {L = L1 L2/(L1 + L2) or L2 = 2L} and L3 = L, Equation (2.172) becomes: © 2003 by CRC Press LLC
1956_C02.fm Page 109 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
Gon = {
δVO ( s) } = δVI ( s) on
109 1
1 2 s 2 LC + 2
(2.174)
poles for switch on
(2.175)
C + CO s 2 L2 CO + C
=
and the pair of imaginary poles is p1,2 = ± j
C + C0 1 = ±j = ± jω n L2 CC0 LC
where ωn = (LC)–1/2 is the relift converter normal angular frequency. For the switchoff state, the zeros are determined by the equation when the numerator of Equation (2.173) is equal to zero, and the poles are determined by the equation when the denominator of Equation (2.173) is equal to zero. There are three zeros: one (z3) at the original point (0, 0) and two zeros (z1,2) on the imaginary axis which are C1 + C2 2 = ±j = ± j 2ω n L3 C1C2 LC
z1,2 = ± j
zeros for switch off (2.176)
Since the equation to determine the poles is the equation with all positive real coefficients, according to the Gauss theorem, the five poles are one negative real pole (p5) and two pairs of conjugate complex poles with negative real parts (p1,2 and p3,4). There are five poles located in the lefthand half plane in Figure 2.24, so that the relift converter is stable. When the load resistance R increases and intends towards infinity, the five poles move. The real pole goes to the origin point and eliminates with the zero. The two pairs of conjugate complex poles become two pairs of imaginary poles locating on the imaginary axis. Assuming that all capacitors have same capacitance C, and L1 = L2 {L = L1 L2/(L1 + L2) or L2 = 2L} and L3 = L, Equation (2.173) becomes: Goff = {
=
δVO ( s) C(C1 + C2 ) + s 2 L3 CC1C2 } off = δVI ( s) (CC1 + CC2 + C1C2 + s 2 L3 CC1C2 )(1 + s 2 L2 CO ) + (C C + C C + s 2 L C C C ) 3 O 1 2 O 1 O 2
2C 2 + s 2 LC 3 2 + s 2 LC = 4 2 2 2 2 2 3 (3C + s LC )(1 + 2 s LC) + (2C + s LC ) 2 s L C + 8 s 2 LC + 5 2
2
3
and the two pairs of imaginary poles are
© 2003 by CRC Press LLC
(2.177)
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110
Advanced DC/DC Converters – VC +
S + V – s
iC
+
c
D1
L2
D
D2
VL2 – iL2
D4
VI N
iL1
iL3
L1 iC1
C1
L3 iC2
iL4 C2
R
L4 iC3
C3
+ VO –
CO
D3 + S1 VS1 –
FIGURE 2.25 Triplelift circuit.
s 2 LC =
6 −3.225 −8 ± 64 − 40 = −2 ± = 4 2 −0.775
poles for switch off, so that p1,2 = ± j 1.8 ωn p3,4 = ± j 0.88 ωn
and
(2.178)
For both states when R tends to infinity all poles are locating on the stability boundary. Therefore, the circuit works in the critical state. From Equation (2.171) the output voltage will be infinity. This fact is verified by the experimental results and computer simulation results. When R = ∞, the output voltage vO tends to be a very high value. In this particular circuit since there is some leakage current across the capacitor CO, the output voltage vO can not be infinity.
2.3.4
MultipleLift Circuits
Referring to Figure 2.20a, it is possible to build multiplelift circuits using the parts (L3C2S1D2) multiple times. For example in Figure 2.25 the parts (L4C3D3D4) were added in the triplelift circuit. Because the voltage at the point of the joint (L4C3) is positive value and higher than that at the point of the joint (L3C2), so that we can use a diode D3 to replace the switch (S2). For multiplelift circuits all further switches can be replaced by diodes. According to this principle, triplelift circuits and quadruplelift circuits were built as shown in Figure 2.25 and Figure 2.28. In this book it is not necessary to introduce the particular analysis and calculations one by one to readers. However, their formulas are shown in this section. © 2003 by CRC Press LLC
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VoltageLift Converters
111
30
24
MT
18
12
6
0 0
0.2
0.6
0.4
0.8
1
k
FIGURE 2.26 Voltage transfer gain MT vs. k.
2.3.4.1 TripleLift Circuit A triplelift circuit is shown in Figure 2.25, and it consists of two static switches S and S1; four inductors L1, L2, L3, and L4; and five capacitors C, C1, C2, C3, and CO; and five diodes. Capacitors C1, C2, and C3 perform characteristics to lift the capacitor voltage VC by three times the source voltage VI. L3 and L4 perform the function as ladder joints to link the three capacitors C1, C2, and C3 and lift the capacitor voltage VC up. Current iC1(t), iC2(t), and iC3(t) are exponential functions. They have large values at the moment of power on, but they are small because vC1 = vC2 = vC3 = VI in steady state. The output voltage and current are VO =
3 V 1− k I
(2.179)
IO =
1− k I 3 I
(2.180)
and
The voltage transfer gain in continuous mode is MT =
VO 3 = VI 1 − k
The curve of MT vs. k is shown in Figure 2.26. © 2003 by CRC Press LLC
(2.181)
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112
Advanced DC/DC Converters
Other average voltages: VC = VO
VC1 = VC2 = VC3 = VI
Other average currents: IL2 = IO
I L1 =
k I 1− k O
I L 3 = I L 4 = I L1 + I L 2 =
1 I 1− k O
Current variations: ξ1 =
1− k R 2 MT fL1
ξ2 =
χ1 =
k R 2 MT fL2
k R MT 2 fL3
ζ=
χ2 =
k(1 − k )R k 3R = 2 MT fL MT 2 2 fL
k R MT 2 fL4
Voltage variations: ρ=
k 2 fCR
σ2 =
MT 2 fC2 R
σ1 =
MT 2 fC1R
σ3 =
MT 2 fC3 R
The variation ratio of output voltage vC is ε=
k 1 2 8 MT f CO L2
(2.182)
The output voltage ripple is very small. The boundary between continuous and discontinuous conduction modes is MT ≤ k
3R = 2 fL
3kz N 2
(2.183)
This boundary curve is shown in Figure 2.27. Comparing with Equations (2.95), (2.165) (2.169), and (2.183), it can be seen that the boundary curve has a minimum value of MT that is equal to 4.5, corresponding to k = ⅓. © 2003 by CRC Press LLC
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113
40 continuous mode
MT
30 k=0.9
15
6
k=0.8
k=0.5
4.5 k=0.33 k=0.1 3
discontinuous mode
40 48
75
188
667
R/fL
FIGURE 2.27 The boundary between continuous and discontinuous modes and the output voltage vs. the normalized load zN = R/fL.
In discontinuous mode the current iD exists in the period between kT and [k + (1 – k)mT]T, where mT is the filling efficiency that is mT =
2 1 MT = ζ k 3R 2 fL
(2.184)
Considering Equation (2.183), therefore, 0 < mT < 1. Since the diode current iD becomes zero at t = kT + (1 – k)mTT, for the current iL1 kTVI = (1 – k)mTT(VC – 3VI – VL3–off – VL4–off) or VC = [3 +
with
k
2k k 2k R + ]VI = [3 + + k 2 (1 − k ) ]V 1 − k (1 − k )mT 1− k 6 fL I
3R 3 ≥ 2 fL 1 − k
and for the current iL2 kT(VI + VC – VO) = (1 – k)mTT(VO – 2VI – VL3–off – VL4–off) Therefore, output voltage in discontinuous mode is VO = [3 + © 2003 by CRC Press LLC
2k k 2k R + ]VI = [3 + + k 2 (1 − k ) ]V 1 − k (1 − k )mT 1− k 6 fL I
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114
Advanced DC/DC Converters –V
+
Vs
iC
C +
S
+ VL2
–
L2
iL2
– c D iL1
VI N
VL1
D1 L1 iC1
D2 iL3 C1
D4
L3
iL4
iC2
C2
L4 iC3
D6
iL5 C3
+ R
L5
VO –
iC4
C4 CO
D3
D5 S1
+ VS1 –
FIGURE 2.28 Quadruplelift circuit.
with
k
3R 3 ≥ 2 fL 1 − k
(2.185)
i.e., the output voltage will linearly increase during load resistance R increasing, as shown in Figure 2.27. 2.3.4.2 QuadrupleLift Circuit Quadruplelift circuit shown in Figure 2.28 consists of two static switches S and S1; five inductors L1, L2, L3, L4, and L5; and six capacitors C, C1, C2, C3, C4, and CO; and seven diodes. Capacitors C1, C2, C3, and C4 perform characteristics to lift the capacitor voltage VC by four times the source voltage VI. L3, L4, and L5 perform the function as ladder joints to link the four capacitors C1, C2, C3, and C4 and lift the output capacitor voltage VC up. Current iC1(t), iC2(t), iC3(t), and iC4(t) are exponential functions. They have large values at the moment of power on, but they are small because vC1 = vC2 = vC3 = vC4 = VI in steady state. The output voltage and current are VO =
4 V 1− k I
(2.186)
IO =
1− k I 4 I
(2.187)
and
The voltage transfer gain in continuous mode is © 2003 by CRC Press LLC
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115
40
32
MQ
24
16
8
0
0
0.2
0.6
0.4
0.8
1
k
FIGURE 2.29 Voltage transfer gain MQ vs. k.
MQ =
VO 4 = VI 1 − k
(2.188)
The curve of MQ vs. k is shown in Figure 2.29. Other average voltages: VC = VO;
VC1 = VC2 = VC3 = VC4 = VI
Other average currents: IL2 = IO;
I L1 =
k I 1− k O
I L 3 = I L 4 = LL 5 = I L1 + I L 2 =
1 I 1− k O
Current variations: ξ1 =
1− k R 2 MQ fL1 χ1 =
© 2003 by CRC Press LLC
ξ2 =
k R MQ 2 fL3
k R 2 MQ fL2 χ2 =
ζ=
k R MQ 2 fL4
k(1 − k )R k 2R = 2 MQ fL MQ 2 fL χ3 =
k R MQ 2 fL5
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116
Advanced DC/DC Converters 60 50 40
continuous mode
k=0.9
30 k=0.8
MQ
20
10 8 6
k=0.5 k=0.33 discontinuous mode
k=0.1 2
54 64
100
250 R/fL
889
FIGURE 2.30 The boundary between continuous and discontinuous modes and the output voltage vs. the normalized load zN = R/fL.
Voltage variations: ρ=
σ2 =
MQ 2 fC2 R
k 2 fCR
σ3 =
σ1 =
MQ 2 fC1R
MQ 2 fC3 R
σ4 =
MQ 2 fC4 R
The variation ratio of output voltage VC is ε=
1 k 2 8 MQ f CO L2
(2.189)
The output voltage ripple is very small. The boundary between continuous and discontinuous modes is MQ ≤ k
2R = 2 kz N fL
(2.190)
This boundary curve is shown in Figure 2.30. Comparing with Equations (2.95), (2.127), (2.169), (2.183), and (2.190), it can be seen that this boundary curve has a minimum value of MQ that is equal to 6.0, corresponding to k = ⅓.
© 2003 by CRC Press LLC
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117
In discontinuous mode the current iD exists in the period between kT and [k + (1 – k)mQ]T, where mQ is the filling efficiency that is
mQ =
2 1 MQ = ζ k 2R fL
(2.191)
Considering Equation (2.190), therefore 0 < mQ < 1. Since the current iD becomes zero at t = kT + (1 – k)mQT, for the current iL1 we have kTVI = (1 – k)mQT(VC – 4VI – VL3–off – VL4–off – VL5–off) or VC = [4 +
3k k 3k R + ]VI = [4 + + k 2 (1 − k ) ]V 1 − k (1 − k )mQ 1− k 8 fL I
with
k
2R 4 ≥ fL 1 − k
and for current iL2 we have kT(VI + VC – VO) = (1 – k)mQT(VO – 2VI – VL3–off – VL4–off – VL5–off) Therefore, output voltage in discontinuous mode is VO = [4 +
3k k 3k R + ]V = [4 + + k 2 (1 − k ) ]V 1 − k (1 − k )mQ I 1− k 8 fL I
with
k
2R 4 ≥ fL 1 − k
(2.192)
i.e., the output voltage will linearly increase during load resistance R increasing, as shown in Figure 2.30.
© 2003 by CRC Press LLC
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118 2.3.5
Advanced DC/DC Converters Summary
From the analysis and calculation in previous sections, the common formulas for all circuits can be obtained: VO I = I VI IO
M=
L=
L1L2 L1 + L2
zN =
R fL
R=
VO IO
Current variations: ξ1 =
1− k R 2 M fL1
k R 2 M fL2
χj =
k R 2 M fL j + 2
k 1 2 8 M f CO L2
σj =
M 2 fC j R
ξ2 =
(j = 1, 2, 3, …)
Voltage variations: ρ=
k 2 fCR
ε=
(j = 1, 2, 3, 4, …)
In order to write common formulas for the boundaries between continuous and discontinuous modes and output voltage for all circuits, the circuits can be numbered. The definition is that subscript 0 means the elementary circuit, subscript 1 means the selflift circuit, subscript 2 means the relift circuit, subscript 3 means the triplelift circuit, subscript 4 means the quadruplelift circuit, and so on. The voltage transfer gain is Mj =
k h( j ) [ j + h( j )] 1− k
j = 0, 1, 2, 3, 4, …
(2.193)
The freewheeling diode current iD’s variation is ζj =
k [1+ h( j )] j + h( j ) zN 2 Mj2
(2.194)
The boundaries are determined by the condition: ζj ≥ 1 or k [1+ h( j )] j + h( j ) zN ≥ 1 2 Mj2 © 2003 by CRC Press LLC
j = 0, 1, 2, 3, 4, …
(2.195)
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119
Therefore, the boundaries between continuous and discontinuous modes for all circuits are Mj = k
1+ h ( j ) 2
j + h( j ) zN 2
j = 0, 1, 2, 3, 4,….
(2.196)
The filling efficiency is 2
Mj 1 2 1 mj = = [1+ h( j )] ζj k j + h( j ) z N
(2.197)
The output voltage in discontinuous mode for all circuits is VO− j = [ j +
j + h( j ) − 1 1− k + k [ 2−u( j )] z ]V 1− k 2[ j + h( j )] N I
j = 0, 1, 2, 3, 4,…. (2.198)
where 0 h( j ) = 1
if if
j≥1 j=0
is the Hong Function
(2.199)
Assuming that f = 50 kHz, L1 = L2 = 1 mH, L2 = L3 = L4 = L5 = 0.5 mH, C = C1 = C2 = C3 = C4 = CO = 20 µF and the source voltage VI = 10 V, the value of the output voltage VO with various conduction duty k in continuous mode are shown in Figure 2.31. Typically, some values of the output voltage VO and its ripples in conduction duty k = 0.33, 0.5, 0.75 and 0.9 are listed in Table 2.1. From these data it states the fact that the output voltage of all LuoConverters is almost a real DC voltage with very small ripple. The boundaries between continuous and discontinuous modes of all circuits are shown in Figure 2.32. The curves of all M vs. zN state that the continuous mode area increases from ME via MS, MR, MT to MQ. The boundary of the elementary circuit is a monorising curve, but other curves are not monorising. There are minimum values of the boundaries of other circuits, which of MS, MR, MT and MQ correspond at k = ⅓. 2.3.6
Discussion
Some important points are vital for particular circuit design. They are discussed in the following sections. 2.3.6.1 DiscontinuousConduction Mode Usually, the industrial applications require the DCDC converters to work in continuous mode. However, it is irresistible that DCDC converter works © 2003 by CRC Press LLC
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120
Advanced DC/DC Converters 120
output voltage, vo,v
100 80
(i)
50 (ii) (iii)
30
(iv)
10
(v)
0.2
0
0.6 0.4 conduction duty k
0.8
1
FIGURE 2.31 Output voltages of all positive output Luoconverters (VI = 10 V).
TABLE 2.1 Comparison among Five Positive Output LuoConverters Positive Output LuoConverters
IO
Elementary Circuit
IO =
SelfLift Circuit
I O = (1 − k )I I
ReLift Circuit
IO =
TripleLift Circuit QuadrupleLift Circuit
VO
k = 0.33
VO (VI = 10 V) k = 0.5 k = 0.75
k = 0.9
VO =
k V 1− k I
5V
10 V
30 V
90 V
VO =
1 V 1− k I
15 V
20 V
40 V
100 V
1− k I 2 I
VO =
2 V 1− k I
30 V
40 V
80 V
200 V
IO =
1− k I 3 I
VO =
3 V 1− k I
45 V
60 V
120 V
300 V
IO =
1− k I 4 I
VO =
4 V 1− k I
60 V
80 V
160 V
400 V
1− k I k I
in discontinuous mode sometimes. The analysis in Section 2.3.2 through Section 2.3.5 shows that during switchoff if current iD becomes zero before next period switchon, the state is called discontinuous mode. The following factors affect the diode current iD to become discontinuous: 1. 2. 3. 4.
Switch frequency f is too low Conduction duty cycle k is too small Combined inductor L is too small Load resistance R is too big
Discontinuous mode means iD is discontinuous during switchoff. The output current iO(t) is still continuous if L2 and CO are large enough. © 2003 by CRC Press LLC
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121
voltage transfer gain M
continuous mode
MQ MT
6
4.5
MR
3 Ms
1.5 ME discontinuous mode
0.5 44.5
27 40.5 54 13.5 normalized load zN = R.fL
FIGURE 2.32 Boundaries between continuous and discontinuous modes of all positive output Luoconverters.
2.3.6.2
Output Voltage VO vs. Conduction Duty k
Output voltage VO is a positive value and is usually greater than the source voltage VI when the conduction duty ratio is k > 0.5 for the elementary circuit, and any value in the range of 0 < k < 1 for selflift, relift, and multiplelift circuits. Although small k results that the output voltage VO of selflift and relift circuits is greater than VI and 2VI and so on, when k = 0 it results in VO = 0 because switch S is never turned on. If k is close to the value of 1, the ideal output voltage VO should be a very big value. Unfortunately, because of the effect of parasitic elements, output voltage VO falls down very quickly. Finally, k = 1 results in VO = 0, not infinity for all circuits. In this case the accident of iL1 toward infinity will happen. The recommended value range of the conduction duty k is 0 < k < 0.9 2.3.6.3 Switch Frequency f In this paper the repeating frequency f = 50 kHz was selected. Actually, switch frequency f can be selected in the range between 10 kHz and 500 kHz. Usually, the higher the frequency, the lower the ripples.
2.4
Negative Output LuoConverters
Negative output Luoconverters perform the voltage conversion from positive to negative voltages using VL technique. They work in the third quadrant with large voltage amplification. Five circuits have been introduced. They are © 2003 by CRC Press LLC
1956_C02.fm Page 122 Monday, August 18, 2003 3:26 PM
122 • • • • •
Advanced DC/DC Converters Elementary circuit Selflift circuit Relift circuit Triplelift circuit Quadruplelift circuit
As the positive output Luoconverters, the negative output Luoconverters are another series of DCDC stepup converters, which were developed from prototypes using voltage lift technique. These converters perform positive to negative DCDC voltage increasing conversion with high power density, high efficiency, and cheap topology in simple structure. The elementary circuit can perform stepdown and stepup DCDC conversion. The other negative output Luoconverters are derived from this elementary circuit, they are the selflift circuit, relift circuit, and multiplelift circuits (e.g., triplelift and quadruplelift circuits) shown in the corresponding figures and introduced in the next sections respectively. Switch S in these diagrams is a Pchannel power MOSFET device (PMOS). It is driven by a PWM switch signal with repeating frequency f and conduction duty k. In this book the switch repeating period is T = 1/f, so that the switchon period is kT and switchoff period is (1 – k)T. For all circuits, the load is usually resistive, i. e., R = VO/IO; the normalized load is zN = R/fL. Each converter consists of a negative Luopump and a “Π”type filter CLOCO, and a lift circuit (except elementary circuit). The pump inductor L absorbs the energy from source during switchon and transfers the stored energy to capacitor C during switchoff. The energy on capacitor C is then delivered to load during switchon. Therefore, if the voltage VC is high the output voltage VO is correspondingly high. When the switch S is turned off the current iD flows through the freewheeling diode D. This current descends in whole switchoff period (1 – k)T. If current iD does not become zero before switch S is turned on again, we define this working state to be continuous mode. If current iD becomes zero before switch S is turned on again, we define this working state to be discontinuous mode. The directions of all voltages and currents are indicated in the figures. All descriptions and calculations in the text are concentrated to the absolute values. In this paper for any component X, its instantaneous current and voltage values are expressed as iX and vX, or iX(t) and vX(t), and its average current and voltage values are expressed as IX and VX. For general description, the output voltage and current are VO and IO; the input voltage and current are VI and II. Assuming the output power equals the input power, PO = PIN
or
VO I O = VI I I
The following symbols are used in the text of this paper. © 2003 by CRC Press LLC
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123
The voltage transfer gain is in CCM: M=
VO I = I VI IO
ζ=
∆iL / 2 IL
ξ=
∆iLO / 2 I LO
Variation ratio of current iL:
Variation ratio of current iLO:
Variation ratio of current iD: ζ=
∆iD / 2 IL
during switchoff, iD = iL
Variation ratio of current iLj is χj =
∆iLj / 2 I Lj
j = 1, 2, 3, …
Variation ratio of voltage vC: ρ=
∆vC / 2 VC
Variation ratio of voltage vCj: σj =
∆vCj / 2 VCj
j = 1, 2, 3, 4, …
Variation ratio of output voltage vO = vCO: ε=
© 2003 by CRC Press LLC
∆vO / 2 VO
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124
Advanced DC/DC Converters iS
VIN
iD
+
VD
–VLO +
–
iL
+ Vs – + VL
D– L
iLO
C
VC +
–
LO
iC
Io iCo Co
– R Vo +
(a) circuit diagram
LO
+ L C
VIN
CO
R
–
(b) switch on D LO C
L
CO
R
(c) switch off
LO L
C
CO
R
(d) discontinuous mode FIGURE 2.33 Elementary circuit: (a) circuit diagram; (b) switchon; (c) switchoff; (d) discontinuous mode.
2.4.1
Elementary Circuit
The elementary circuit, and its switchon and off equivalent circuits are shown in Figure 2.33. This circuit can be considered as a combination of an electronic pump SLDC and a “Π”type lowpass filter CLOCO. The electronic © 2003 by CRC Press LLC
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VoltageLift Converters
125
pump injects certain energy to the lowpass filter every cycle. Capacitor C in Figure 2.33 acts as the primary means of storing and transferring energy from the input source to the output load. Assuming capacitor C to be sufficiently large, the variation of the voltage across capacitor C from its average value VC can be neglected in steady state, i.e., vC(t) ≈ VC, even though it stores and transfers energy from the input to the output. 2.4.1.1 Circuit Description When switch S is on, the equivalent circuit is shown in Figure 2.33b. In this case the source current iI = iL. Inductor L absorbs energy from the source, and current iL linearly increases with slope VI/L. In the mean time the diode D is blocked since it is inversely biased. Inductor LO keeps the output current IO continuous and transfers energy from capacitor C to the load R, i.e., iC–on = iLO. When switch S is off, the equivalent circuit is shown in Figure 2.33c. In this case the source current iI = 0. Current iL flows through the freewheeling diode D to charge capacitor C and enhances current iLO. Inductor L transfers its stored energy to capacitor C and load R via inductor LO, i.e., iL = iC–off + iLO. Thus, currents iL decrease. 2.4.1.2 Average Voltages and Currents The output current IO = ILO because the capacitor CO does not consume any energy in the steady state. The average output current is IO = ILO = IC–on
(2.200)
The charge on the capacitor C increases during switchoff: Q+ = (1 – k) T IC–off And it decreases during switchon: Q– = k T IC–on
(2.201)
In a whole repeating period T,
Q+ = Q–,
I C −off =
k k I C −on = I 1− k 1− k O
Therefore, the inductor current IL is I L = I C −off + I O = © 2003 by CRC Press LLC
IO 1− k
(2.202)
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126
Advanced DC/DC Converters
Equation (2.200) and Equation (2.202) are available for all circuit of negative output Luoconverters. The source current is iI = iL during switchon period. Therefore, its average source current II is I I = k × iI = kiL = kI L =
k I 1− k O
or IO =
1− k I k I
(2.203)
VO =
k V 1− k I
(2.204)
and the output voltage is
The voltage transfer gain in continuous mode is ME =
VO I k = I = VI IO 1 − k
(2.205)
The curve of ME vs. k is shown in Figure 2.34. Current iL increases and is supplied by VI during switchon. It decreases and is inversely biased by –VC during switchoff, kTVI = (1 − k )TVC
(2.206)
k V 1− k I
(2.207)
Therefore, VC = VO =
2.4.1.3 Variations of Currents and Voltages To analyze the variations of currents and voltages, some voltage and current waveforms are shown in Figure 2.35. Current iL increases and is supplied by VI during switchon. Thus, its peaktopeak variation is ∆iL =
© 2003 by CRC Press LLC
kTVI L
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127
10
8
ME
6
4
2
0 0
0.2
0.6
0.4
0.8
1
k
FIGURE 2.34 Voltage transfer gain ME vs. k.
Considering Equation (2.202) and Equation (2.205), and R = VO/IO, the variation ratio of the current iL is ζ=
∆iL / 2 k(1 − k )VI T k(1 − k )R k2 R = = = IL 2LI O 2 ME fL ME 2 2 fL
(2.208)
Considering Equation (2.201), the peaktopeak variation of voltage vC is ∆vC =
Q− k = TI O C C
(2.209)
The variation ratio of voltage vC is ρ=
∆vC / 2 kI O T k 1 = = VC 2CVO 2 fCR
(2.210)
Since voltage VO variation is very small, the peaktopeak variation of current iLO is calculated by the area (B) of the triangle with the width of T/ 2 and height ∆vC/2. ∆iLO =
B 1T k k = TI O = 2 I LO 2 2 2CLO 8 f CLO O
Considering Equation (2.200), the variation ratio of current iLO is © 2003 by CRC Press LLC
(2.211)
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128
Advanced DC/DC Converters S on
DT
T
t
− VO LO
VI Lo
IO
A 0 IS
VI
L1
II
0 ILO
IL1
− VO L
VI L
S off
O
kII
S on
V 1 − L
IL
S off
0 IL2
t1
T
t
VI − V O L2 L2
IO t
VI L
0
t
IS L
VI
II+IO II
II 0
ID
II+IO
t
− VO L
0 ID
t − V L O
IO IO 0 ICO
t IL2
0
IC1
IO 0
t
IL1
t
IL2
0 IL1
t
I1 VL1,VL2 VI
VL1,VL2 VI
VI
0
0
VO
VO
t
VS
VS
VO+VI
VO+VI
VI
VI
0
t
VD
t
VO
0
t
VDR
VO+VI
VO+VI VO
VO 0
t
0
a
FIGURE 2.35 Some voltage and current waveforms of elementary circuit. © 2003 by CRC Press LLC
t b
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129
ξ=
∆iLO / 2 k 1 = I LO 16 f 2 CLO
(2.212)
Since the voltage vC is a triangle waveform, the difference between vC and output voltage VO causes the ripple of current iLO, and the difference between iLO and output current IO causes the ripple of output voltage vO. The ripple waveform of current iLO should be a partial parabola in Figure 2.35 because of the triangle waveform of ∆vC. To simplify the calculation we can treat the ripple waveform of current iLO as a triangle waveform in Figure 2.35 because the ripple of the current iLO is very small. Therefore, the peaktopeak variation of voltage vCO is calculated by the area (A) of the triangle with the width of T/2 and height ∆iLO/2: ∆vCO =
A 1T k k = I = I CO 2 2 16 f 2 CCO LO O 64 f 3 CCO LO O
(2.213)
The variation ratio of current vCO is ε=
∆vCO / 2 IO k k 1 = = 3 VCO 128 f CCO LO VO 128 f 3 CCO LO R
(2.214)
Assuming that f = 50 kHz, L = LO = 100 µH, C = CO = 5 µF, R = 10 Ω and k = 0.6, we obtain
ΜΕ = 1.5 ζ = 0.16 ζ = 0.03 ρ = 0.12 and ε = 0.0015 The output voltage VO is almost a real DC voltage with very small ripple. Since the load is resistive, the output current iO(t) is almost a real DC waveform with very small ripple as well, and it is equal to IO = VO/R. 2.4.1.4 Instantaneous Values of Currents and Voltages Referring to Figure 2.35, the instantaneous current and voltage values are listed below: 0 vS = VO
for for
V + VO vD = I 0 VI vL = −VO © 2003 by CRC Press LLC
0 < t ≤ kT kT < t ≤ T for for
for for
0 < t ≤ kT kT < t ≤ T 0 < t ≤ kT kT < t ≤ T
(2.215)
(2.216)
(2.217)
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130
Advanced DC/DC Converters V i (0) + I t iI = iS = L L 0
0 < t ≤ kT kT < t ≤ T
for for
(2.218)
V i L ( 0) + I t L iL = VO iL ( kT ) − (t − kT ) L
for for
0 < t ≤ kT kT < t ≤ T
(2.219)
0 VO iD = iL ( kT ) − L (t − kT )
for for
0 < t ≤ kT kT < t ≤ T
(2.220)
− I C −on iC ≈ I C −off
for for
0 < t ≤ kT kT < t ≤ T
(2.221)
where iL(0) = k II – k VI/2 f L iL(kT) = k II + k VI/2 f L Since the instantaneous current iLO and voltage vCO are partial parabolas with very small ripples, they can be treated as a DC current and voltage. 2.4.1.5 Discontinuous Mode Referring to Figure 2.33d, we can see that the diode current iD becomes zero during switch off before next period switch on. The condition for discontinuous mode is ζ≥1 i.e., k2 R ≥1 ME 2 2 fL or ME ≤ k © 2003 by CRC Press LLC
z R =k N 2 fL 2
(2.222)
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131
20 continuous mode 10 k=0.9 5 ME
k=0.7 2 1
k=0.5
0.5 k=0.3 0.2
discontinuous mode k=0.1
0.1 1
2
5
10
20
50
100
200
500 1000
R/fL
FIGURE 2.36 The boundary between continuous and discontinuous modes and output voltage vs. the normalized load zN = √R/fL (elementary circuit).
The graph of the boundary curve vs. the normalized load zN = R/fL is shown in Figure 2.36. It can be seen that the boundary curve is a monorising function of the parameter k. In this case the current iD exists in the period between kT and t1 = [k + (1 – k)mE]T, where mE is the filling efficiency and it is defined as: 2
mE =
ME 1 = ζ k2 R 2 fL
(2.223)
Considering Equation (2.222), therefore 0 < mE < 1. Since the diode current iD becomes zero at t = kT + (1 – k)mET, for the current iL kTVI = (1 – k)mETVC or VC =
k R VI = k(1 − k ) V (1 − k )mE 2 fL I
with
R 1 ≥ 2 fL 1 − k
and for the current iLO kT(VI + VC – VO) = (1 – k)mETVO © 2003 by CRC Press LLC
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Therefore, output voltage in discontinuous mode is VO =
k R VI = k(1 − k ) V (1 − k )mE 2 fL I
with
R 1 ≥ 2 fL 1 − k
(2.224)
i.e., the output voltage will linearly increase during load resistance R increasing. The output voltage vs. the normalized load zN = R/fL is shown in Figure 2.36. Larger load resistance R may cause higher output voltage in discontinuous mode.
2.4.2
SelfLift Circuit
Selflift circuit, and its switchon and off equivalent circuits are shown in Figure 2.37, which is derived from the elementary circuit. It consists of eight passive components. They are one static switch S; two inductors L, LO; three capacitors C, C1, and CO; and two diodes D, D1. Comparing with Figure 2.33 and Figure 2.37, it can be seen that there are only one more capacitor C1 and one more diode D1 added into the selflift circuit. Circuit C1D1 is the lift circuit. Capacitor C1 functions to lift the capacitor voltage VC by a source voltage VI. Current iC1(t) is an exponential function δ(t). It has a large value at the moment of power on, but it is small in the steady state because VC1 = VI. 2.4.2.1 Circuit Description When switch S is on, the equivalent circuit is shown in Figure 2.37b. In this case the source current iI = iL + iC1. Inductor L absorbs energy from the source, and current iI linearly increases with slope VI/L. In the mean time the diode D1 is conducted and capacitor C1 is charged by the current iC1. Inductor LO keeps the output current IO continuous and transfers energy from capacitor C to the load R, i.e., iC–on = iLO. When switch S is off, the equivalent circuit is shown in Figure 2.37c. In this case the source current iI = 0. Current iL flows through the freewheeling diode D to charge capacitor C and enhances current iLO. Inductor L transfers its stored energy via capacitor C1 to capacitor C and load R (via inductor LO), i.e., iL = iC1–off = iC–off + iLO. Thus, current iL decreases. 2.4.2.2 Average Voltages and Currents The output current IO = ILO because the capacitor CO does not consume any energy in the steady state. The average output current: IO = ILO = IC–on The charge of the capacitor C increases during switchoff: © 2003 by CRC Press LLC
(2.225)
1956_C02.fm Page 133 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
S iIN VI iL
N
133
+ VC1–
+ VD –
iC1
iD D iD1 – VC +
C1
–
L VD1 +
– V + LO iC
LO
iO iLO
C
iCO CO
– R VO +
(a) circuit diagram
LO
+ VIN
L
C1
C
CO
R
–
(b) switch on C1 LO L
C
CO
R
CO
R
(c) switch off C1 LO L
C
(d) discontinuous mode FIGURE 2.37 Selflift circuit: (a) circuit diagram; (b) switch on; (c) switch off; (d) discontinuous mode.
© 2003 by CRC Press LLC
1956_C02.fm Page 134 Monday, August 18, 2003 3:26 PM
134
Advanced DC/DC Converters Q+ = (1 – k) T IC–off
And it decreases during switchon: Q– = k T IC–on
(2.226)
In a whole repeating period T, Q+ = Q–. Thus, I C −off =
k k I C −on = I 1− k 1− k O
Therefore, the inductor current IL is IO 1− k
(2.227)
1 I 1− k O
(2.228)
I L = I C −off + I O = From Figure 2.37, I C1−off = I L = and I C1−on =
1− k 1 I C1−off = I O k k
(2.229)
In steady state we can use VC1 = VI Investigate current iL, it increases during switch–on with slope VI/L and decreases during switchoff with slope –(VO – VC1)/L = –(VO – VI)/L. Therefore, kVI = (1 − k )(VO − VI ) or VO = © 2003 by CRC Press LLC
1 V 1− k I
(2.230)
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135
10
8
MS
6
4
2
0
0
0.2
0.6
0.4
0.8
1
k
FIGURE 2.38 Voltage transfer gain MS vs. k.
and I O = (1 − k )I I
(2.231)
The voltage transfer gain in continuous mode is MS =
VO I 1 = I = VI IO 1 − k
(2.232)
The curve of MS vs. k is shown in Figure 2.38. Circuit (CLOCO) is a “Π” type lowpass filter. Therefore, VC = VO =
k V 1− k I
(2.233)
2.4.2.3 Variations of Currents and Voltages To analyze the variations of currents and voltages, some voltage and current waveforms are shown in Figure 2.39. Current iL increases and is supplied by VI during switchon. Thus, its peaktopeak variation is ∆iL = © 2003 by CRC Press LLC
kTVI L
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Advanced DC/DC Converters S on VI L
IO
VI
L1
II
0 ILO
IL1
− VO – VI L
S off
VI – VO L 1
kII
S on
−
IL
S off
kT VI LO
−
T
t
VO – VI LO
0 IL2
t1
T
t
V VI − O – V L2 L2 I
∆Q
IO 0 II=IS
t
t) VI + d( L
0
t
II=IS
t)
+
I
V
II
d(
L
II
0 ID
−
t
VO – VI
L
0 ID
t −
VO
L
IO
–
VI
IO 0
t
ID1 IO k
d(t) IO k
0 IC1
0 ID
t
t
d(t)
0
t
d(t)
IO k
IC1 0 (II+IO)
IC
d(t)
0 t
VO – VI L
VO – VI L
IL2
IC1
IO 0
t
IL1
t
IL2
0 IL1
t
I1 VL1,VL2 VI
VL2 VI
VI
0
0 VO
t
VS
VS
VO
VO
VI
VI
0
t
0
VD1
VD1
VO
VO
(VOVI)
VI
0
t
VD
t
(VOVI)
t
0
t
VD
VO
VO kVO
kVO 0
t
0
a
FIGURE 2.39 Some voltage and current waveforms of selflift circuit. © 2003 by CRC Press LLC
t
b
1956_C02.fm Page 137 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
137
Considering Equation (2.227) and R = VO/IO, the variation ratio of the current iL is ζ=
∆iL / 2 k(1 − k )VI T k(1 − k )R k R = = = IL 2LI O 2 MS fL MS 2 2 fL
(2.234)
Considering Equation (2.226), the peaktopeak variation of voltage vC is ∆vC =
Q− k = TI O C C
The variation ratio of voltage vC is ρ=
∆vC / 2 kI O T k 1 = = VC 2CVO 2 fCR
(2.235)
The peaktopeak variation of voltage vC1 is ∆vC1 =
1 kT = I I C1 C1−on fC O
The variation ratio of voltage vC1 is σ1 =
∆vC1 / 2 IO M 1 = = S 2 fC1VI 2 fC1R VC1
(2.236)
Considering the Equation (2.211): ∆iLO =
1T k k TI O = 2 I 2 2 2CLO 8 f CLO O
The variation ratio of current iLO is ξ=
∆iLO / 2 k 1 = 2 I LO 16 f CLO
Considering Equation (2.213): ∆vCO =
© 2003 by CRC Press LLC
B 1T k k = IO = I 2 3 CO 2 2 16 f CCO LO 64 f CCO LO O
(2.237)
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Advanced DC/DC Converters
The variation ratio of current vCO is ε=
∆vCO / 2 IO k k 1 = = VCO 128 f 3 CCO LO VO 128 f 3 CCO LO R
(2.238)
Assuming that f = 50 kHz, L = LO = 100 µH, C = CO = 5 µF, R = 10 Ω and k = 0.6, we obtain MS = 2.5 ζ = 0.096 ξ = 0.03 ρ = 0.12 and ε = 0.0015 The output voltage VO is almost a real DC voltage with very small ripple. Since the load is resistive, the output current iO(t) is almost a real DC waveform with very small ripple as well, and it is equal to IO = VO/R. 2.4.2.4 Instantaneous Value of the Currents and Voltages Referring to Figure 2.39, the instantaneous values of the currents and voltages are listed below: 0 vS = VO − VI
0 < t ≤ kT kT < t ≤ T
for for
(2.239)
V vD = O 0
for for
0 < t ≤ kT kT < t ≤ T
(2.240)
0 vD1 = VO
for for
0 < t ≤ kT kT < t ≤ T
(2.241)
VI vL = −(VO − VI )
for for
V i (0) + δ(t) + I t iI = iS = L1 L 0 V i L ( 0) + I t L iL = V − VI iL ( kT ) − O (t − kT ) L
© 2003 by CRC Press LLC
0 < t ≤ kT kT < t ≤ T
for for
for for
(2.242)
0 < t ≤ kT kT < t ≤ T
0 < t ≤ kT kT < t ≤ T
(2.243)
(2.244)
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139
0 VO − VI iD = (t − kT ) iL1 ( kT ) − L δ(t) iD1 = 0
for for
0 < t ≤ kT kT < t ≤ T
for for
δ(t) VO − VI iC 1 = (t − kT ) −iL ( kT ) + L − I C −on iC ≈ I C −off
0 < t ≤ kT kT < t ≤ T
for for
0 < t ≤ kT kT < t ≤ T
(2.245)
(2.246)
for for
0 < t ≤ kT kT < t ≤ T
(2.247)
(2.248)
where iL(0) = k II – k VI/2 f L iL(kT) = k II + k VI/2 f L Since the instantaneous current iLO and voltage vCO are partial parabolas with very small ripples, they can be treated as a DC current and voltage. 2.4.2.5 Discontinuous Mode Referring to Figure 2.37d, we can see that the diode current iD becomes zero during switch off before next period switch on. The condition for discontinuous mode is ζ≥1 i.e., k R ≥1 MS 2 2 fL or MS ≤ k
© 2003 by CRC Press LLC
z R = k N 2 fL 2
(2.249)
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140
Advanced DC/DC Converters
The graph of the boundary curve vs. the normalized load zN = R/fL is shown in Figure 2.40. It can be seen that the boundary curve has a minimum value of 1.5 at k = ⅓. In this case the current iD exists in the period between kT and t1 = [k + (1 – k)mS]T, where mS is the filling efficiency and it is defined as: mS =
MS 2 1 = ζ k R 2 fL
(2.250)
Considering Equation (2.249), therefore 0 < mS < 1. Since the diode current iD becomes 0 at t = kT + (1 – k)mST, for the current iL kTVI = (1 – k)mST(VC – VI) or VC = [1 +
k R ]V = [1 + k 2 (1 − k ) ]V (1 − k )mS I 2 fL I
with
k
R 1 ≥ 2 fL 1 − k
and for the current iLO kT(VI + VC – VO) = (1 – k)mST(VO – VI) Therefore, output voltage in discontinuous mode is VO = [1 +
k R ]VI = [1 + k 2 (1 − k ) ]V (1 − k )mS 2 fL I
with
k
R 1 ≥ 2 fL 1 − k
(2.251)
i.e., the output voltage will linearly increase during load resistance R increasing. The output voltage VO vs. the normalized load zN = R/fL is shown in Figure 2.40. Larger load resistance R causes higher output voltage in discontinuous mode.
2.4.3
ReLift Circuit
Relift circuit, and its switchon and off equivalent circuits are shown in Figure 2.41, which is derived from the selflift circuit. It consists of one static switch S; three inductors L, L1, and LO; four capacitors C, C1, C2, and CO; and diodes. From Figure 2.33, Figure 2.37, and Figure 2.41, it can be seen that there are one capacitor C2, one inductor L1 and two diodes D2, D11 added into the relift circuit. Circuit C1D1D11L1C D2 is the lift circuit. Capacitors C1 and C2 perform characteristics to lift the capacitor voltage VC by twice © 2003 by CRC Press LLC
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141
30 continuous mode
20 k=0.9 10
MS
8 k=0.8 5 3 2
k=0.5 k=0.33
1.5 k=0.1 1
13.56
discontinuous mode 24.7
62.5 R/fL
222
842
FIGURE 2.40 The boundary between continuous and discontinuous modes and output voltage vs. the normalized load zN = R/fL (selflift circuit).
that of source voltage 2VI. Inductor L1 performs the function as a ladder joint to link the two capacitors C1 and C2 and lift the capacitor voltage VC up. Currents iC1(t) and iC2(t) are exponential functions δ1(t) and δ2(t). They have large values at the moment of power on, but they are small because vC1 = vC2 ≅ VI is in steady state. 2.4.3.1 Circuit Description When switch S is on, the equivalent circuit is shown in Figure 2.41b. In this case the source current iI = iL + iC1 + iC2. Inductor L absorbs energy from the source, and current iL linearly increases with slope VI/L. In the mean time the diodes D1, D2 are conducted so that capacitors C1 and C2 are charged by the current iC1 and iC2. Inductor LO keeps the output current IO continuous and transfers energy from capacitors C to the load R, i.e., iC–on = iLO. When switch S is off, the equivalent circuit is shown in Figure 2.41c. In this case the source current iI = 0. Current iL flows through the freewheeling diode D, capacitors C1 and C2, inductor L1 to charge capacitor C and enhances current iLO. Inductor L transfers its stored energy to capacitor C and load R via inductor LO, i.e., iL = iC1–off = iC2–off = iL1–off = iC–off + iLO. Thus, current iL decreases. 2.4.3.2 Average Voltages and Currents The output current IO = ILO because the capacitor CO does not consume any energy in the steady state. The average output current: IO = ILO = IC–on © 2003 by CRC Press LLC
(2.252)
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Advanced DC/DC Converters i D1 1
i C1
iD
– V LO
S i IN
–V + S
i L1
D 11
D
C1
LO
iC
iO
+ i LO
i CO
L1
D 10
– C2
VI
C
R VO
CO
N
iL
+
L D2
D1
(a) circuit diagram
LO
+ VIN
C1
L
L1
C2
C
CO
R
–
(b) switch on C2
C1 L1
LO
L
CO
C
R
(c) switch off C1
C2 LO
L1 L
C
CO
R
(d) discontinuous mode
FIGURE 2.41 Relift circuit: (a) circuit diagram; (b) switch on; (c) switch off; (d) discontinuous mode.
The charge of the capacitor C increases during switchoff: Q+ = (1 – k) T IC–off And it decreases during switchon: © 2003 by CRC Press LLC
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VoltageLift Converters
143 Q– = k T IC–on
In a whole repeating period T, Q+ = Q–. Thus, I C −off =
k k = I I 1 − k C −on 1 − k O
Therefore, the inductor current IL is I L = I C −off + I O =
IO 1− k
(2.253)
We know from Figure 2.48b that I C1−off = I C 2−off = I L1 = I L =
1 I 1− k O
(2.254)
and I C1−on =
1− k 1 I C1−off = I O k k
(2.255)
I C 2−on =
1− k 1 I C 2−off = I O k k
(2.256)
and
In steady state we can use VC1 = VC 2 = VI and VL1−on = VI
VL1−off =
k V 1− k I
Investigate current iL, it increases during switchon with slope VI/L and decreases during switchoff with slope –(V O – V C1 – V C2 – V L1–off )/L = – [VO – 2VI – k VI/(1 – k)]/L. Therefore, kTVI = (1 − k )T (VO − 2VI − © 2003 by CRC Press LLC
k V) 1− k I
1956_C02.fm Page 144 Monday, August 18, 2003 3:26 PM
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Advanced DC/DC Converters 20
16
MR
12
8
4
0
0
0.2
0.6
0.4
0.8
1
k
FIGURE 2.42 Voltage transfer gain MR vs. k.
or VO =
2 V 1− k I
(2.257)
IO =
1− k I 2 I
(2.258)
and
The voltage transfer gain in continuous mode is MR =
VO I 2 = I = VI IO 1 − k
(2.259)
The curve of MS vs. k is shown in Figure 2.42. Circuit (CLOCO) is a “Π” type lowpass filter. Therefore, VC = VO =
2 V 1− k I
(2.260)
2.4.3.3 Variations of Currents and Voltages To analyze the variations of currents and voltages, some voltage and current waveforms are shown in Figure 2.43. © 2003 by CRC Press LLC
1956_C02.fm Page 145 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
IL K I1 2 0 ILO
145 S on
S off
(i)
(ii)
kT
S on IL1
T
(iii)
K I1 2 0 IL2
t
(iv)
S off
(i)
(ii)
T1
T
(iv)
IO 0 II=I S
0
t
(v)
t
t
II=I S (v) II
0 ID
(vi)
0 ID
t
(vii)
t (viii)
IO IO 0 ID1
t
0 ID
t
0
d(t)
t
d(t)
0
t
a
b
d'(t) IC1
IC1
0
d' (t)
0 t
(i)
t (ii)
(ii) IC
IL2
IC1
IO 0
t
IL2
I 1 V L1 ,V L2 VI
IL2
0
I L2
t
V L2 VI
VI
0
0
(V O2V I)
V O
t
t
(V O2V I) VS
VS
V OV I VI
VI
0
t
V D1
0
t
V D1
VO
V O V I V OV I 0 VD
t
0 VD
t
VO
VO
kV O kV O 0
a
t
0
FIGURE 2.43 Some voltage and current waveforms of relift circuit. © 2003 by CRC Press LLC
b
t
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Advanced DC/DC Converters
Current iL increases and is supplied by VI during switchon. Thus, its peaktopeak variation is ∆iL =
kTVI L
Considering Equation (2.253) and R = VO/IO, the variation ratio of the current iL is ζ=
∆iL / 2 k(1 − k )VI T k(1 − k )R k R = = = IL 2LI O 2 M R fL M R 2 fL
(2.261)
The peaktopeak variation of current iL1 is ∆iL1 =
k TVI L1
The variation ratio of current iL1 is χ1 =
∆iL1 / 2 kTVI k(1 − k ) R (1 − k ) = = 2L1 I O 2 M R fL1 I L1
(2.262)
The peaktopeak variation of voltage vC is ∆vC =
Q− k = TI O C C
The variation ratio of voltage vC is ρ=
∆vC / 2 kI O T k 1 = = 2CVO 2 fCR VC
(2.263)
The peaktopeak variation of voltage vC1 is ∆vC1 =
1 kT = I I C1 C1−on fC O
The variation ratio of voltage vC1 is σ1 = © 2003 by CRC Press LLC
∆vC1 / 2 IO M 1 = = R VC1 2 fC1VI 2 fC1R
(2.264)
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147
Take the same operation, variation ratio of voltage vC2 is σ2 =
∆vC 2 / 2 IO M 1 = = R VC 2 2 fC2VI 2 fC2 R
(2.265)
Considering the Equation (2.211): ∆iLO =
1T k k TI = I 2 2 2CLO O 8 f 2 CLO O
The variation ratio of current iLO is ξ=
∆iLO / 2 1 k = 16 f 2 CLO I LO
(2.266)
Considering the Equation (2.213): ∆vCO =
B 1T k k = IO = I 2 3 CO 2 2 16 f CCO LO 64 f CCO LO O
The variation ratio of current vCO is ε=
∆vCO / 2 IO 1 k k = = 3 3 128 f CCO LO VO 128 f CCO LO R VCO
(2.267)
Assuming that f = 50 kHz, L = LO = 100 µH, C = CO = 5 µF, R = 10 Ω and k = 0.6, we obtain MR = 5 ζ = 0.048 ξ = 0.03 ρ = 0.12
and ε = 0.0015
The output voltage VO is almost a real DC voltage with very small ripple. Since the load is resistive, the output current iO(t) is almost a real DC waveform with very small ripple as well, and it is equal to IO = VO/R. 2.4.3.4 Instantaneous Value of the Currents and Voltages Referring to Figure 2.43, the instantaneous current and voltage values are listed below: 0 k vS = VO − (2 − )V 1− k I © 2003 by CRC Press LLC
for for
0 < t ≤ kT kT < t ≤ T
(2.268)
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Advanced DC/DC Converters
V vD = O 0
for for
0 < t ≤ kT kT < t ≤ T
(2.269)
0 vD1 = vD 2 = VO
for for
0 < t ≤ kT kT < t ≤ T
(2.270)
VI k v L1 = − VI 1 − k
for for
0 < t ≤ kT kT < t ≤ T
(2.271)
VI k vL = )V ] −[V − (2 − O 1− k I
for for
0 < t ≤ kT
(2.272)
kT < t ≤ T
V V i (0) + I t + δ 1 (t) + δ 2 (t) + iL1 (0) + I t for 0 < t ≤ kT iI = iS = L L L1 for kT < t ≤ T 0
(2.273)
V i L ( 0) + I t L k iL = )V VO − (2 − 1 − k I (t − kT ) iL ( kT ) − L
(2.274)
iL1
V i L 1 ( 0) + I t L1 k = V 1 − k I (t − kT ) i kT − ( ) L1 L1
0 k iD = )V VO − (2 − 1 − k I (t − kT ) iL ( kT ) − L
for for
for for
0 < t ≤ kT kT < t ≤ T
0 < t ≤ kT kT < t ≤ T
for for
0 < t ≤ kT kT < t ≤ T
(2.275)
(2.276)
δ (t) iD1 = 1 0
for for
0 < t ≤ kT kT < t ≤ T
(2.277)
δ (t) iD2 = 2 0
for for
0 < t ≤ kT kT < t ≤ T
(2.278)
© 2003 by CRC Press LLC
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149
iC 1
δ 1 (t ) k = )V VO − (2 − − 1 k I (t − kT ) −iL1 ( kT ) + L
for for
0 < t ≤ kT kT < t ≤ T
(2.279)
iC 2
δ 2 (t ) k = VO − (2 − )V 1 − k I (t − kT ) −iL1 ( kT ) + L
for for
0 < t ≤ kT kT < t ≤ T
(2.280)
− I C −on iC = I C −off
for for
0 < t ≤ kT kT < t ≤ T
(2.281)
where iL(0) = k II – k VI/2 f L iL(kT) = k II + k VI/2 f L and iL1(0) = k II – k VI/2 f L1 iL1(kT) = k II + k VI/2 f L1 Since the instantaneous currents iLO and iCO are partial parabolas with very small ripples. They are very nearly DC current. 2.4.3.5 Discontinuous Mode Referring to Figure 2.41d, we can see that the diode current iD becomes zero during switch off before next period switch on. The condition for discontinuous mode is ζ≥1 i.e., k R ≥1 M R 2 fL or MR ≤ k © 2003 by CRC Press LLC
R = k zN fL
(2.282)
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150
Advanced DC/DC Converters 60 k=0.95
continuous mode
40 k=0.9
MR
20 k=0.8 10 6 4 3
k=0.5 k=0.33 k=0.1
2
27 32
discontinuous mode 50
125 R/fL
444
1684
FIGURE 2.44 The boundary between continuous and discontinuous modes and output voltage vs. the normalized load zN = R/fL (relift circuit).
The graph of the boundary curve vs. the normalized load zN = R/fL is shown in Figure 2.44. It can be seen that the boundary curve has a minimum value of 3.0 at k = ⅓. In this case the current iD exists in the period between kT and t1 = [k + (1 – k)mR]T, where mR is the filling efficiency and it is defined as: mR =
2 1 MR = ζ k R fL
(2.283)
Considering Equation (2.282), therefore 0 < mR < 1. Because inductor current iL1 = 0 at t = t1, so that VL1−off =
k V (1 − k )mR I
Since the current iD becomes zero at t = t1 = [k + (1 – k)mR]T, for the current iL kTVI = (1 – k)mRT(VC – 2VI – VL1–off) or VC = [2 +
2k R ]V = [2 + k 2 (1 − k ) ]V (1 − k )mR I 2 fL I
© 2003 by CRC Press LLC
with
k
R 2 ≥ fL 1 − k
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VoltageLift Converters
151 iC1
D11
iIN
iD
iC2
S –V + S
D12
D
C2 L2 iL2
D10
iO
– VLO +
C1 iC
LO
iLO i CO
L1 iL1
–
C3
VI
C
CO
N
R VO +
L iL
D2
D3 iD3
iD2
D1 iD1
FIGURE 2.45 Triplelift circuit.
and for the current iLO kT(VI + VC – VO) = (1 – k)mRT(VO – 2VI – VL1–off) Therefore, output voltage in discontinuous mode is VO = [2 +
2k R ]V = [2 + k 2 (1 − k ) ]V (1 − k )mR I 2 fL I
with
k
2 R ≥ fL 1 − k
(2.284)
i.e., the output voltage will linearly increase during load resistance R increasing. The output voltage vs. the normalized load zN = R/fL is shown in Figure 2.44. Larger load resistance R may cause higher output voltage in discontinuous mode.
2.4.4
MultipleLift Circuits
Referring to Figure 2.45, it is possible to build a multiplelift circuit just only using the parts (L1C2D2D11) multiple times. For example, in Figure 2.16 the parts (L2C3D3D12) were added in the triplelift circuit. According to this principle, the triplelift circuit and quadruplelift circuit were built as shown in Figure 2.45 and Figure 2.48. In this book it is not necessary to introduce the particular analysis and calculations one by one to readers. However, their formulas are shown in this section. 2.4.4.1 TripleLift Circuit Triplelift circuit is shown in Figure 2.45. It consists of one static switch S; four inductors L, L1, L2, and LO; and five capacitors C, C1, C2, C3, and CO; and © 2003 by CRC Press LLC
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152
Advanced DC/DC Converters 30
24
MT
18
12
6
0 0
0.2
0.6
0.4
0.8
1
k
FIGURE 2.46 Voltage transfer gain of triplelift circuit.
diodes. Circuit C1D1L1C2D2D11L2C3D3D12 is the lift circuit. Capacitors C1, C2, and C3 perform characteristics to lift the capacitor voltage VC by three times that of the source voltage VI. L1 and L2 perform the function as ladder joints to link the three capacitors C1, C2, and C3 and lift the capacitor voltage VC up. Current iC1(t), iC2(t), and iC3(t) are exponential functions. They have large values at the moment of power on, but they are small because vC1 = vC2 = vC3 ≅ VI in steady state. The output voltage and current are VO =
3 V 1− k I
(2.285)
IO =
1− k I 3 I
(2.286)
and
The voltage transfer gain in continuous mode is MT = VO / VI =
3 1− k
The curve of MT vs. k is shown in Figure 2.46. Other average voltages: VC = VO © 2003 by CRC Press LLC
VC1 = VC2 = VC3 = VI
(2.287)
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153
Other average currents: I L = I L1 = I L 2 =
ILO = IO
1 I 1− k O
Current variation ratios: k 3R MT 2 2 fL
ζ=
χ1 =
k 1 16 f 2 CLO
ξ=
k(1 − k ) R 2 MT fL1
χ2 =
k(1 − k ) R 2 MT fL2
Voltage variation ratios: ρ=
σ2 =
k 1 2 fCR
σ1 =
MT 1 2 fC2 R
MT 1 2 fC1R
σ3 =
MT 1 2 fC3 R
The variation ratio of output voltage VC is ε=
k 1 3 128 f CCO LO R
(2.288)
The output voltage ripple is very small. The boundary between continuous and discontinuous modes is MT ≤ k
3R = 2 fL
3kz N 2
(2.289)
It can be seen that the boundary curve has a minimum value of MT that is equal to 4.5, corresponding to k = ⅓. The boundary curve vs. the normalized load zN = R/fL is shown in Figure 2.47. In discontinuous mode the current iD exists in the period between kT and [k + (1 – k)mT]T, where mT is the filling efficiency that is mT =
© 2003 by CRC Press LLC
2 1 MT = ζ k 3R 2 fL
(2.290)
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40 continuous mode
MT
30 k=0.9
15
6
k=0.8
k=0.5
4.5 k=0.33 k=0.1 3
discontinuous mode
40 48
75
188
667
R/fL
FIGURE 2.47 The boundary between continuous and discontinuous modes and output voltage vs. the normalized load zN = R/fL (triplelift circuit).
Considering Equation (2.289), therefore 0 < mT < 1. Because inductor current iL1 = iL2 = 0 at t = t1, so that VL1−off = VL 2−off =
k V (1 − k )mT I
Since the current iD becomes zero at t = t1 = [k + (1 – k)mT]T, for the current iL we have kTVI = (1 – k)mTT(VC – 3VI – VL1–off – VL2–off) or VC = [3 +
3k R ]V = [3 + k 2 (1 − k ) ]V (1 − k )mT I 2 fL I
k
with
3R 3 ≥ 2 fL 1 − k
and for the current iLO we have kT(VI + VC – VO) = (1 – k)mTT(VO – 2VI – VL1–off – VL2–off) Therefore, output voltage in discontinuous mode is VO = [3 +
3k R ]V = [3 + k 2 (1 − k ) ]V (1 − k )mT I 2 fL I
© 2003 by CRC Press LLC
with
k
3R 3 (2.291) ≥ 2 fL 1 − k
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VoltageLift Converters
155 iD11
iD12 iD13
S iIN
–V + S
D10
iC2
D11 iC3
D12
D13
iC1
C1
iD
D
C3
iC4
L3
L2
iL3
iC
LO
iLO
iCO
L1
iL2
iL1
–
C4
VIN
iO
– VLO +
C2
C
CO
R VO +
D4
L iL
iD4
D3 iD3
D2 iD2
D1 iD1
FIGURE 2.48 Quadruplelift circuit.
i.e., the output voltage will linearly increase during load resistance R increasing. The output voltage vs. the normalized load zN = R/fL is shown in Figure 2.47. We can see that the output voltage will increase when the load resistance R increases. 2.4.4.2 QuadrupleLift Circuit Quadruplelift circuit is shown in Figure 2.48. It consists of one static switch S; five inductors L, L1, L2, L3, and LO; and six capacitors C, C1, C2, C3, C4, and CO. Capacitors C1, C2, C3, and C4 perform characteristics to lift the capacitor voltage VC by four times of source voltage VI. L1, L2, and L3 perform the function as ladder joints to link the four capacitors C1, C2, C3, and C4 and lift the output capacitor voltage VC up. Current iC1(t), iC2(t), iC3(t), and iC4(t) are exponential functions. They have large values at the moment of power on, but they are small because vC1 = vC2 = vC3 = vC4 ≅ VI in steady state. The output voltage and current are VO =
4 V 1− k I
(2.292)
IO =
1− k I 4 I
(2.293)
and
The voltage transfer gain in continuous mode is MQ = VO / VI = © 2003 by CRC Press LLC
4 1− k
(2.294)
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156
Advanced DC/DC Converters 40
32
MQ
24
16
8
0
0
0.2
0.6
0.4
1
0.8
k
FIGURE 2.49 Voltage transfer gain of quadruplelift circuit.
The curve of MQ vs. k is shown in Figure 2.49. Other average voltages: VC = VO
VC1 = VC2 = VC3 = VC4 = VI
Other average currents: ILO = IO
I L = I L1 = I L 2 = I L 3 =
1 I 1− k O
Current variation ratios: ζ=
χ1 =
k(1 − k ) R 2 MQ fL1
k 2R MQ 2 fL χ2 =
ξ=
k 1 16 f 2 CLO
k(1 − k ) R 2 MQ fL2
χ3 =
k(1 − k ) R 2 MQ fL3
Voltage variation ratios: ρ=
σ2 =
MQ
© 2003 by CRC Press LLC
1 2 fC2 R
k 1 2 fCR
σ3 =
σ1 = MQ
MQ
1 2 fC1R
1 2 fC3 R
σ4 =
MQ
1 2 fC4 R
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157
60 50 40
continuous mode
k=0.9
30 k=0.8
MQ
20
10 8 6
k=0.5 k=0.33 discontinuous mode
k=0.1 2
54 64
100
250 R/fL
889
FIGURE 2.50 The boundary between continuous and discontinuous modes and output voltage vs. the normalized load zN = R/fL (quadruplelift circuit).
The variation ratio of output voltage VC is ε=
k 1 3 128 f CCO LO R
(2.295)
The output voltage ripple is very small. The boundary between continuous and discontinuous conduction modes is MQ ≤ k
2R = 2 kz N fL
(2.296)
It can be seen that the boundary curve has a minimum value of MQ that is equal to 6.0, corresponding to k = ⅓. The boundary curve is shown in Figure 2.50. In discontinuous mode the current iD exists in the period between kT and [k + (1 – k)mQ]T, where mQ is the filling efficiency that is mQ =
2 1 MQ = ζ k 2R fL
(2.297)
Considering Equation (2.296), therefore 0 < mQ < 1. Because inductor current iL1 = iL2 = iL3 = 0 at t = t1, so that © 2003 by CRC Press LLC
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Advanced DC/DC Converters
VL1−off = VL 2−off = VL 3−off =
k V (1 − k )mQ I
Since the current iD becomes zero at t = t1 = kT + (1 – k)mQT, for the current iL we have kTVI = (1 – k)mQT(VC – 4VI – VL1–off – VL2–off – VL3–off) or VC = [4 +
4k R ]VI = [4 + k 2 (1 − k ) ]V (1 − k )mQ 2 fL I
with
k
2R 4 ≥ fL 1 − k
and for current iLO we have kT(VI + VC – VO) = (1 – k)mQT(VO – 2VI – VL1–off – VL2–off – VL3–off) Therefore, output voltage in discontinuous mode is VO = [4 +
4k R ]VI = [4 + k 2 (1 − k ) ]V (1 − k )mQ 2 fL I
with
k
2R 4 (2.298) ≥ fL 1 − k
i.e., the output voltage will linearly increase while load resistance R increases. The output voltage vs. the normalized load zN = R/fL is shown in Figure 2.50. We can see that the output voltage will increase during load resistance while the load R increases.
2.4.5
Summary
From the analysis and calculation in previous sections, the common formulae can be obtained for all circuits: M=
VO I = I VI IO
zN =
R fL
R=
VO IO
Current variation ratios:
© 2003 by CRC Press LLC
ζ=
k(1 − k )R 2 MfL
ξ=
χj =
k(1 − k )R 2 MfL j
(j = 1, 2, 3, …)
k 16 f 2 CLO
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159
Voltage variation ratios: ρ=
k 2 fCR
ε=
k 128 f 3 CCO LO R
σj =
M 2 fC j R
(j = 1, 2, 3, 4, …)
In order to write common formulas for the boundaries between continuous and discontinuous modes and output voltage for all circuits, the circuits can be numbered. The definition is that subscript 0 means the elementary circuit, subscript 1 means the selflift circuit, subscript 2 means the relift circuit, subscript 3 means the triplelift circuit, subscript 4 means the quadruplelift circuit, and so on. Therefore, the voltage transfer gain in continuous mode for all circuits is Mj =
k h( j ) [ j + h( j )] 1− k
j = 0, 1, 2, 3, 4, …
(2.299)
The variation of the freewheeling diode current iD is ζj =
k [1+ h( j )] j + h( j ) zN 2 Mj2
(2.300)
The boundaries are determined by the condition: ζj ≥ 1 or k [1+ h( j )] j + h( j ) zN ≥ 1 2 Mj2
j = 0, 1, 2, 3, 4, …
(2.301)
Therefore, the boundaries between continuous and discontinuous modes for all circuits are Mj = k
1+ h ( j ) 2
j + h( j ) zN 2
j = 0, 1, 2, 3, 4, …
(2.302)
The filling efficiency is 2
mj = © 2003 by CRC Press LLC
Mj 1 2 1 = [1+ h( j )] ζj k j + h( j ) z N
(2.303)
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Advanced DC/DC Converters
120
output voltage, vo, v
100 80
(i)
50 (ii) (iii)
30
(iv)
10 0
(v)
0.2
0.6 0.4 conduction duty k
0.8
1
FIGURE 2.51 Output voltages of all negative output Luoconverters (VI = 10 V).
The voltage across the capacitor C in discontinuous mode for all circuits VC − j = [ j + k [ 2− h( j )]
1− k z ]V 2 N I
j = 0, 1, 2, 3, 4, …
(2.304)
The output voltage in discontinuous mode for all circuits VO− j = [ j + k [ 2− h( j )]
1− k z ]V 2 N I
j = 0, 1, 2, 3, 4, …
(2.305)
where 0 h( j ) = 1
if if
j≥1 j=0
is the Hong Function
The voltage transfer gains in continuous mode for all circuits are shown in Figure 2.51. The boundaries between continuous and discontinuous modes of all circuits are shown in Figure 2.52. The curves of all M vs. zN state that the continuous mode area increases from ME via MS, MR, MT to MQ. The boundary of elementary circuit is a monorising curve, but other curves are not monorising. There are minimum values of the boundaries of other curves, which of MS, MR, MT, and MQ correspond at k = ⅓. Assuming that f = 50 kHz, L = LO = L1 = L2 = L3 = L4 = 100 µH, C = C1 = C2 = C3 = C4 = CO = 5 µF and the source voltage VI = 10 V, the value of the output voltage VO in various conduction duty k are shown in Figure 2.22. Typically, some values of the output voltage VO in conduction duty k = 0.33, © 2003 by CRC Press LLC
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161
voltage transfer gain M
continuous mode
MQ MT
6 4.5
MR
3 Ms 1.5 ME discontinuous mode 0.5 44.5
27 40.5 54 13.5 normalized load zN R/fL
FIGURE 2.52 Boundaries between continuous and discontinuous modes of all negative output Luoconverters.
TABLE 2.2 Comparison among Five Negative Output LuoConverters Negative Output LuoConverters
IO
Elementary Circuit
IO =
SelfLift Circuit
I O = (1 − k )I I
ReLift Circuit
IO =
TripleLift Circuit QuadrupleLift Circuit
VO
k = 0.33
VO (VI = 10 V) k = 0.5 k = 0.75
k = 0.9
VO =
k V 1− k I
5V
10 V
30 V
90 V
VO =
1 V 1− k I
15 V
20 V
40 V
100 V
1− k I 2 I
VO =
2 V 1− k I
30 V
40 V
80 V
200 V
IO =
1− k I 3 I
VO =
3 V 1− k I
45 V
60 V
120 V
300 V
IO =
1− k I 4 I
VO =
4 V 1− k I
60 V
80 V
160 V
400 V
1− k I k I
0.5, 0.75, and 0.9 are listed in Table 2.2. The ripple of the output voltage is very small, say smaller than 1%. For example, using the above data and R = 10 Ω, the variation ratio of the output voltage is ε = 0.0025 × k = 0.0008, 0.0012, 0.0019, and 0.0023 respectively. From these data the fact we find is that the output voltage of all negative output Luoconverters is almost a real DC voltage with very small ripple.
© 2003 by CRC Press LLC
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162
2.5
Advanced DC/DC Converters
Modified Positive Output LuoConverters
Negative output Luoconverters perform the voltage conversion from positive to negative voltages using VL technique with only one switch S. This section introduces the technique to modify positive output Luoconverters that can employ only one switch for all circuits. Five circuits have been introduced in the literature. They are • • • • •
Elementary circuit Selflift circuit Relift circuit Triplelift circuit Quadruplelift circuit
There are five circuits introduced in this section, namely the elementary circuit, selflift circuit, relift circuit, and multiplelift circuit (triplelift and quadruplelist circuits). In all circuits the switch S is a PMOS. It is driven by a PWM switch signal with variable frequency f and conduction duty k. For all circuits, the load is usually resistive, R = VO/IO. We concentrate the absolute values rather than polarity in the following descriptions and calculations. The directions of all voltages and currents are defined and shown in the figures. We will assume that all the components are ideal and the capacitors are large enough. We also assume that the circuits operate in continuous conduction mode. The output voltage and current are VO and IO; the input voltage and current are VI and II. 2.5.1
Elementary Circuit
Elementary circuit is shown in Figure 2.10. It is the elementary circuit of positive output Luoconverters. The output voltage and current and the voltage transfer gain are VO =
k V 1− k I
IO =
1− k I k I
ME =
k 1− k
Average voltage: VC = VO © 2003 by CRC Press LLC
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163
iI
i LO
– vC +
+ VI
S
D1 + vC1 D –
C
iL L
–
iO
LO C1
+ R
CO
vO –
(a) Selflift circuit iI
vC
–
+ VI
i LO +
C
iL L
–
LO
– vC1 +
iO + R
C1
CO
vO –
(b) Switchon equivalent circuit i LO
i I=0 + VI –
iL
– – vC1 vC C + L +
iO
LO C1
+ CO
R
vO –
(c) Switchoff equivalent circuit FIGURE 2.53 Modified selflift circuit and its equivalent circuit. (a) Selflift circuit. (b) Switchon equivalent circuit. (c) Switchoff equivalent circuit.
Average currents: ILO = IO
2.5.2
IL =
k I 1− k O
SelfLift Circuit
Selflift circuit is shown in Figure 2.53. It is derived from the elementary circuit. In steady state, the average inductor voltages over a period are zero. Thus VC1 = VCO = VO
© 2003 by CRC Press LLC
(2.306)
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Advanced DC/DC Converters
The inductor current iL increases in the switchon period and decreases in the switchoff period. The corresponding voltages across L are VI and −VC . Therefore kTVI = (1 − k )TVC Hence, VC =
k V 1− k I
(2.307)
During switchon period, the voltage across capacitor C1 are equal to the source voltage plus the voltage across C. Since we assume that C and C1 are sufficiently large, VC1 = VI + VC Therefore, VC1 = VI +
k 1 V = V 1− k I 1− k I
VO = VCO = VC1 =
1 V 1− k I
The voltage transfer gain of continuous conduction mode (CCM) is M=
VO 1 = VI 1 − k
The output voltage and current and the voltage transfer gain are VO =
1 V 1− k I
I O = (1 − k )I I MS = © 2003 by CRC Press LLC
1 1− k
(2.308)
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165
Average voltages: VC = kVO VC1 = VO Average currents: ILO = IO IL =
1 I 1− k O
We also implement the breadboard prototype of the proposed selflift circuit. NMOS IRFP460 is used as the semiconductor switch. The diode is MR824. The other parameters are VI = 0 ~ 30 V, R = 30 ~ 340 Ω, k = 0.1 ~ 0.9 C = CO = 100 µF and L = 470 µH
2.5.3
ReLift Circuit
Relift circuit and its equivalent circuits are shown in Figure 2.54. It is derived from the selflift circuit. The function of capacitors C2 is to lift the voltage vC by source voltage VI, the function of inductor L1 acts like a hinge of the foldable ladder (capacitor C2) to lift the voltage vC during switch off. In steady state, the average inductor voltages over a period are zero. Thus VC1 = VCO = VO Since we assume C2 is large enough and C2 is biased by the source voltage VI during switchon period, thus VC 2 = VI From the switchon equivalent circuit, another capacitor voltage equation can also be derived since we assume all the capacitors to be large enough, VO = VC1 = VC + VI The inductor current iL increases in the switchon period and decreases in the switchoff period. The corresponding voltages across L are VI and −VL−OFF . Therefore kTVI = (1 − k )TVL−OFF © 2003 by CRC Press LLC
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Advanced DC/DC Converters
iI D 11
S
+ + VI
v C2
i L1 –
L1
+
+ v C1 D
L
iO
LO
D1
C2 iL
i LO
+
C
D 10
–
vC
–
CO
C1
–
vO
R
–
D2
(a) Relift circuit iI
vC
–
i LO
+
LO
C +
–
i L1
+ v C2 –
VI iL
iO
L1
+ v C1 –
C2
+ vO
CO
C1
R
–
L
(b) Switchon equivalent circuit vC
–
iI = 0
i LO
+
LO
C
+
+ VI –
v C2
i L1 –
L1
C2 iL
iO
+ + v C1 –
C1
CO
vO R
–
L
(c) Switchoff equivalent circuit FIGURE 2.54 Modified relift circuit. (a) Relift circuit. (b) Switchon equivalent circuit. (c) Switchoff equivalent circuit.
Hence, VL−OFF =
k V 1− k I
The inductor current iL1 increases in the switchon period and decreases in the switchoff period. The corresponding voltages across L1 are VI and −VL1−OFF . Therefore kTVI = (1 − k )TVL1−OFF © 2003 by CRC Press LLC
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167
Hence, VL1−OFF =
k V 1− k I
From the switchoff period equivalent circuit, VC = VC −OFF = VL−OFF + VL1−OFF + VC 2 Therefore, VC =
k 1+ k k VI + VI + VI = V 1− k 1− k 1− k I VO =
(2.309)
1+ k 2 VI + VI = V 1− k 1− k I
Then we get the voltage transfer ratio in CCM, M = MR =
2 1− k
(2.310)
The following is a brief summary of the main equations for the relift circuit. The output voltage and current and gain are VO =
2 V 1− k I
IO =
1− k I 2 I
MR =
2 1− k
Average voltages: VC =
1+ k V 1− k I
VC1 = VCO = VO VC2 = VI © 2003 by CRC Press LLC
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Advanced DC/DC Converters
iI D 11
S
D 10 D 12 +
v C3
C2
iO
LO
D1
i L1
– +
L1
C3
v C1
L2
+ iL
i LO
+
C
v C2 –
+
VI
vC
–
D
C1
CO
+ R vO
L
–
–
D3
–
D2
FIGURE 2.55 Modified triplelift circuit.
Average currents: ILO = IO I L = I L1 =
2.5.4
1 I 1− k O
MultiLift Circuit
Multiplelift circuits are derived from relift circuits by repeating the section of L1C1D1 multiple times. For example, triplelist circuit is shown in Figure 2.55. The function of capacitors C2 and C3 is to lift the voltage vC across capacitor C by twice the source voltage 2VI, the function of inductors L1 and L2 acts like hinges of the foldable ladder (capacitors C2 and C3) to lift the voltage vC during switch off. The output voltage and current and voltage transfer gain are VO =
3 V 1− k I
IO =
1− k I 3 I
and
MT = © 2003 by CRC Press LLC
3 1− k
(2.311)
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169
iI
– D11
S
+ D12 – D13 i L3
D10 –
+
vC4
vC3
C2
+
L1 L2
L3
+
+ vC1
C4 VI –
iO
LO
D1
C
–
C3
+
i LO
+
i L1
vC2
i L2
vC
D
–
vO C1
CO
R –
iL
L
D3
D4
D2
FIGURE 2.56 Modified quadruplelift circuit.
Other average voltages: 2+k V 1− k I
VC = and VC1 = VO
VC2 = VC3 = VI
Other average currents: ILO = IO I L1 = I L 2 = I L =
1 I 1− k O
The quadruplelift circuit is shown in Figure 2.56. The function of capacitors C2, C3, and C4 is to lift the voltage vC across capacitor C by three times the source voltage 3VI. The function of inductors L1, L2, and L3 acts like hinges of the foldable ladder (capacitors C2, C3, and C4) to lift the voltage vC during switch off. The output voltage and current and voltage transfer gain are VO = and © 2003 by CRC Press LLC
4 V 1− k I
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Advanced DC/DC Converters
IO =
1− k I 4 I
MQ =
4 1− k
(2.312)
Average voltages: VC =
3+k V 1− k I
and VC1 = VO VC2 = VC3 = VC4 = VI Average currents: ILO = IO and IL =
k I 1− k O
I L1 = I L 2 = I L 3 + I L + I LO =
2.5.5
1 I 1− k O
Application
A highefficiency, widely adjustable high voltage regulated power supply (HVRPS) is designed to use these Luoconverters in a high voltage test rig. The proposed HVRPS is shown in Figure 2.57. The HVRPS was constructed by using a PWM IC TL494 to implement closedloop control together with the modified positive output Luoconverters. Its output voltage is basically a DC value with small ripple and can be widely adjustable. The source voltage is 24 V DC and the output voltage can vary from 36 V to 1000 V DC. The measured experimental results show that the efficiency can be as high as 95% and the source effect ratio is about 0.001 and load effect ratio is about 0.005. © 2003 by CRC Press LLC
1956_C02.fm Page 171 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
171
iI
vC
–
D11 C2
V I =+24V
S –
vC3
D13
–
+
–
i L1
vC2
L1 + L2
+
vO
vC1 –
C4
D D4
iL
iO
LO
i L2
L3
+
D1
C
+
C3 i L3
D10 vC4
D12
i LO
+
D3
CO
R
–
C1
D2
L R6
R8 V ref
1.5k 6 (Rt) 12 (Vcc )
5 (Ct)
TL494
15
11 16 7
10k 82k
14
8 R4 820
22u
13
10
9
1 (+)
4 2 (–)
10k 0.001u
C5
R2
R1
C6 1k
R3
R7
R5
1.5k
820 R9 510
Rw1 3.9k
FIGURE 2.57 A high voltage testing power supply.
2.6
Double Output LuoConverters
Mirrorsymmetrical double output voltages are specially required in industrial applications and computer periphery circuits. Double output DCDC Luoconverters can convert the positive input source voltage to positive and negative output voltages. It consists of two conversion paths. Double output Luoconverters perform from positive to positive and negative DCDC voltage increasing conversion with high power density, high efficiency, and cheap topology in simple structure. Double output DCDC Luoconverters consist of two conversion paths. Usually, mirrorsymmetrical double output voltages are required in industrial applications and computer periphery circuits such as operational amplifiers, computer periphery power supplies, differential servomotor drives, and some symmetrical voltage medical equipment. In recent years the DCDC conversion technique has been greatly developed. The main objective is © 2003 by CRC Press LLC
1956_C02.fm Page 172 Monday, August 18, 2003 3:26 PM
172
Advanced DC/DC Converters
to reach a high efficiency, high power density and cheap topology in simple structure. The elementary circuit can perform stepdown and stepup DCDC conversion. The other double output Luoconverters are derived from this elementary circuit, they are the selflift circuit, relift circuit, and multiplelift circuits (e.g., triplelift and quadruplelift circuits). Switch S in these circuits is a PMOS. It is driven by a PWM switch signal with repeating frequency f and conduction duty k. In this paper the switch repeating period is T = 1/ f, so that the switchon period is kT and switchoff period is (1 – k)T. For all circuits, the loads are usually resistive, i.e., R = VO+/IO+ and R1 = VO–/IO–; the normalized loads are zN+ = R/fL (where L = L1 and L = L1L2 L1 + L2 for elementary circuits) and zN– = R1/fL11. In order to keep the positive and negative output voltages to be symmetrically equal to each other, usually, we purposely select that L = L11 and zN+ = zN–. Each converter has two conversion paths. The positive path consists of a positive pump circuit SL1D0C1 and a “Π”type filter (C2)L2CO, and a lift circuit (except elementary circuits). The pump inductor L1 absorbs energy from source during switchon and transfers the stored energy to capacitor C1 during switchoff. The energy on capacitor C1 is then delivered to load R during switchon. Therefore, a high voltage VC1 will correspondingly cause a high output voltage VO+. The negative path consists of a negative pump circuit SL11D10(C11) and a “Π”type filter C11L12C10, and a lift circuit (except elementary circuits). The pump inductor L11 absorbs the energy from source during switchon and transfers the stored energy to capacitor C11 during switchoff. The energy on capacitor C11 is then delivered to load R1 during switchon. Hence, a high voltage VC11 will correspondingly cause a high output voltage VO–. When switch S is turned off, the currents flowing though the freewheeling diodes D0 and D10 are existing. If the currents iD0 and iD10 do not fall to zero before switch S is turned on again, we define this working state to be continuous conduction mode. If the currents iD0 and iD10 become zero before switch S is turned on again, we define that working state to be discontinuous conduction mode. The output voltages and currents are VO+, VO– and IO+, IO–; the input voltage and current are VI and II = II+ + II–. Assuming that the power loss can be ignored, PI = PO, or VIII = VO+ IO+ + VO– IO–. For general description, we have the following definitions in continuous mode: The voltage transfer gain in the continuous mode: M+ =
VO+ VI
and
Variation ratio of the diode’s currents:
© 2003 by CRC Press LLC
M− =
VO− VI
1956_C02.fm Page 173 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
173 ∆iD 0 / 2 I D0
ζ+ =
ζ− =
and
∆iD10 / 2 I L11
Variation ratio of pump inductor’s currents: ξ 1+ =
∆iL1 / 2 I L1
ζ− =
and
∆iL11 / 2 I L11
Variation ratio of filter inductor’s currents: ξ2+ =
∆iL 2 / 2 I L2
ξ− =
and
∆iL12 / 2 I L12
Variation ratio of lift inductor’s currents: χ j+ =
∆iL 2+ j / 2
χ j− =
and
I L 2+ j
∆iL12+ j / 2 I L12+ j
j = 1, 2, 3, …
Variation ratio of pump capacitor’s voltages: ρ+ =
∆vC1 / 2 VC1
ρ− =
and
∆vC11 / 2 VC11
Variation ratio of lift capacitor’s voltages: σ j+ =
∆vC1+ j / 2 VC1+ j
and
σ j− =
∆vC11+ j / 2 VC11+ j
j = 1, 2, 3, 4, …
Variation ratio of output voltages: ε+ =
2.6.1
∆vO+ / 2 VO+
and
ε− =
∆vO− / 2 VO−
Elementary Circuit
The elementary circuit is shown in Figure 2.58. Since the positive Luoconverters and negative Luoconverters have been published, this section can be simplified.
© 2003 by CRC Press LLC
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Advanced DC/DC Converters
S
N
iL IN+
+
C1
L2
– VC1 +
i L2
D20
Vs
iIN VI
VS
i L1
D0
L1
Io +
+ Co
R Vo +
– – iIN – iL 11
+ VC11 –
L11
C11
+ R1 Vo –
i L12
D10
D21
C10
– L12 Io –
FIGURE 2.58 Elementary circuit.
2.6.1.1 Positive Conversion Path The equivalent circuit during switchon is shown in Figure 2.59a, and the equivalent circuit during switchoff in Figure 2.59b. The relations of the average currents and voltages are I L2 =
1− k I k L1
and IL2 = IO+
Positive path input current is I I + = k × iI + = k(iL1 + iL 2 ) = k(1 +
1− k ) I L1 = I L1 k
(2.313)
The output current and voltage are I O+ =
1− k I k I+
and
VO+ =
k V 1− k I
The voltage transfer gain in continuous mode is ME + =
VO+ k = 1− k VI
The average voltage across capacitor C1 is VC1 = © 2003 by CRC Press LLC
k V = VO+ 1− k I
(2.314)
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175
S
iIN+ –
iL2
VC1 +
L2
+
+
+ VIN
L1
iL11
CO
VD0
R
–
VO – –
–
(a) switch on i L2
VC1 +
–
L2 L1
iL11
+ CO
i D0
R
VO – –
(b) switch off
–
i L2
VC1 +
L2
+
+ L1
i L11
VD0
CO
–
R
VO – –
(c) discontinuous mode FIGURE 2.59 Equivalent circuits of elementary circuit positive path: (a) switch on; (b) switch off; (c) discontinuous conduction mode.
The variation ratios of the parameters are ξ 1+ =
∆iL1 / 2 kTVI ∆i / 2 kTVI k R 1− k R = = = = and ξ 2+ = L 2 I L1 I L2 2L1 I I + 2 ME fL1 2L2 I O+ 2 ME fL2
The variation ratio of current iD0 is ζ+ =
∆iD 0 / 2 (1 − k )2 TVO+ k(1 − k )R k2 R = = = 2LI O+ 2 ME fL I D0 ME 2 2 fL
The variation ratio of vC1 is © 2003 by CRC Press LLC
(2.315)
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Advanced DC/DC Converters
ρ+ =
∆vC1 / 2 (1 − k )TI I + k 1 = = VC1 2C1VO+ 2 fC1R
The variation ratio of output voltage vO+ is ε+ =
∆vO+ / 2 kT 2 VI k 1 = = 2 VO+ 8CO L2 VO+ 8 ME f CO L2
(2.316)
If L1 = L2 = 1 mH, C1 = C0 = 20 µF, R = 10 Ω, f = 50 kHz and k = 0.5, we get ξ1+ = 0.05, ξ2+ = 0.05, ζ+ = 0.05, ρ+ = 0.025, and ε = 0.00125. Therefore, the variations of iL1, iL2 and vC1 are small. The output voltage VO+ is almost a real DC voltage with very small ripple. Because of the resistive load, the output current iO+(t) is almost a real DC waveform with very small ripple as well, and is equal to IO+ = VO+/R. 2.6.1.2 Negative Conversion Path The equivalent circuit during switchon is shown in Figure 2.60(a) the equivalent circuit during switchoff is shown in Figure 2.60(b). The relations of the average currents and voltages are IO– = IL12
and IO– = IL12 = IC11–on
Since I C11−off =
k k I C11−on = I 1− k 1 − k O−
the inductor current IL11 is I L11 = I C11−off + I O− =
I O− 1− k
So that I I − = k × iI − = kiL11 = kI L11 =
k I 1 − k O−
The output current and voltage are I O− =
© 2003 by CRC Press LLC
1− k I k I−
and
VO− =
k V 1− k I
(2.317)
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VoltageLift Converters
177 i L12 L12
+
–
– VIN
L11
i L11
iC11
VC11
C10
R1
+
–
VO– +
(a) switch on i D10
i L12 L12
+
–
– VL11
i L11 iC11 L11
C10
VC11
R1
+
–
VO– +
(b) switch off i L12 VD10
L 12
+
–
– VL11
L11
C10
VC11
R1
+
–
VO– +
(c) discontinuous mode FIGURE 2.60 Equivalent circuits of elementary circuit negative path: (a) switch on; (b) switch off; (c) discontinuous conduction mode.
The voltage transfer gain in continuous mode is ME − =
VO− k = 1− k VI
(2.318)
and VC11 = VO− =
k V 1− k I
From Equations (2.314) and (2.318), we can define that ME = ME+ = ME– . The curve of ME vs. k is shown in Figure 2.61. The variation ratios of the parameters are ξ− =
∆iL12 / 2 k 1 = I L12 16 f 2 C10 L12
© 2003 by CRC Press LLC
and
ρ− =
∆vC11 / 2 kI O− T k 1 = = VC11 2C11VO− 2 fC11R1
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178
Advanced DC/DC Converters 10
8
ME
6
4
2
0 0
0.6
0.4
0.2
0.8
1
k
FIGURE 2.61 Voltage transfer gain ME vs. k.
The variation ratio of current iL11 and iD10 is ζ− =
∆iL11 / 2 k(1 − k )VI T k(1 − k )R1 k 2 R1 = = = I L11 2L11 I O− 2 ME fL11 ME 2 2 fL11
(2.319)
The variation ratio of current vC1O is ε− =
∆vC10 / 2 I O− k k 1 = = VC10 128 f 3 C11C10 L12 VO− 128 f 3 C11C10 L12 R1
(2.320)
Assuming that f = 50 kHz, L11 = L12 = 0.5 mH, C = CO = 20 µF, R1 = 10 Ω and k = 0.5, obtained ME = 1, ζ = 0.05, ρ = 0.025, ξ = 0.00125 and ε = 0.0000156. The output voltage VO– is almost a real DC voltage with very small ripple. Since the load is resistive, the output current iO–(t) is almost a real DC waveform with very small ripple as well, and it is equal to IO– = VO–/R1. 2.6.1.3 Discontinuous Mode The equivalent circuits of the discontinuous mode’s operation are shown in Figure 2.59c and Figure 2.60c. In order to obtain the mirrorsymmetrical double output voltages, select: L= and R = R1. Thus, we define © 2003 by CRC Press LLC
L1L2 = L11 L1 + L2
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179
20 continuous mode 10 k=0.9 5 ME
k=0.7 2 1
k=0.5
0.5 k=0.3 0.2
discontinuous mode k=0.1
0.1 1
2
5
10
20
50
100
200
500 1000
R/fL
FIGURE 2.62 The boundary between continuous and discontinuous modes and the output voltage vs. the normalized load zN = R/fL (elementary circuit).
VO = VO+ = VO− 
ME = ME + = ME − =
zN = zN+ = zN–
VO k = VI 1 − k
and ζ = ζ+ = ζ–
The freewheeling diode currents iD0 and iD10 become zero during switch off before next period switch on. The boundary between continuous and discontinuous modes is ζ≥1 i.e., k 2 zN ≥1 ME 2 2 or ME ≤ k
zN 2
(2.321)
The boundary curve is shown in Figure 2.62. In this case the freewheeling diode’s diode current exists in the period between kT and [k + (1 – k)mE]T, where mE is the filling efficiency and it is defined as: © 2003 by CRC Press LLC
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180
Advanced DC/DC Converters
mE =
2 1 2 ME = 2 ζ k zN
(2.322)
Considering the Equation (2.321), therefore, 0 < mE < 1. Since the diode current iD0 becomes zero at t = kT + (1 – k)mET, for the current iL1 kTVI = (1 – k)mETVC or VC1 =
z k VI = k(1 − k ) N VI (1 − k )mE 2
with
zN 1 ≥ 2 1− k
(2.323)
and for the current iL2 kT(VI + VC1 – VO+) = (1 – k)mETVO+ Therefore, the positive output voltage in discontinuous mode is VO+ =
z k VI = k(1 − k ) N VI (1 − k )mE 2
with
zN 1 ≥ 2 1− k
(2.324)
zN 1 ≥ 2 1− k
(2.325)
For the current iL11 we have kTVI = (1 – k)mETVC11 or VC11 =
z k VI = k(1 − k ) N VI (1 − k )mE 2
with
and for the current iL12 we have kT(VI + VC11 – VO–) = (1 – k)mETVO– Therefore, the negative output voltage in discontinuous mode is VO− =
z k V = k(1 − k ) N VI (1 − k )mE I 2
with
We then have VO = VO+ = VO− = k(1 − k )
© 2003 by CRC Press LLC
zN V 2 I
zN 1 ≥ 2 1− k
(2.326)
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VoltageLift Converters
S
181
VS
D20
C1 –
iIN VI
iIN+
+
iL1
D1
VC1+
+
iL2 D0
L1
Io +
L2
C2
Co
R Vo +
– N
– iIN– iL11
L11
D21
+ VC11 D11 – D10
C11
C10
+ R1 Vo–
iL2 – L12
C12
Io–
FIGURE 2.63 Selflift circuit.
i.e., the output voltage will linearly increase while load resistance increases. It can be seen that larger load resistance may cause higher output voltage in discontinuous mode as shown in Figure 2.62.
2.6.2
SelfLift Circuit
Selflift circuit shown in Figure 2.63 is derived from the elementary circuit. The positive conversion path consists of a pump circuit SL1D0C1, a filter (C2)L2CO, and a lift circuit D1C2. The negative conversion path consists of a pump circuit SL11D10(C11), a “Π”type filter C11L12C10, and a lift circuit D11C12. 2.6.2.1 Positive Conversion Path The equivalent circuit during switchon is shown in Figure 2.64a, and the equivalent circuit during switchoff in Figure 2.64b. The voltage across inductor L1 is equal to VI during switchon, and –VC1 during switchoff. We have the relations: VC1 =
k V 1− k I
Hence, VO = VCO = VC 2 = VI + VC1 = and © 2003 by CRC Press LLC
1 V 1− k I
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182
Advanced DC/DC Converters iIN+ –
S
iL2
VC1 +
L2
+ VIN
iL1
C2
L1
+ CO
VC2
R
VO+ –
–
(a) switch on –
iL2
VC1 +
L2 iL1
L1
C2
+
+ VC2 CO –
VO+
R
–
(b) switch off –
iL2
VC1
L2 + L1
VD0 C 2
VC2 C O
VO+
R
–
(c) discontinuous conduction mode
FIGURE 2.64 Equivalent circuits of selflift circuit positive path: (a) switch on; (b) switch off; (c) discontinuous conduction mode.
VO+ =
1 V 1− k I
The output current is I O+ = (1 − k )I I + Other relations are II+ = k iI+ and © 2003 by CRC Press LLC
iI+ = IL1 + iC1–on
iC1−off =
k i 1 − k C1−on
1956_C02.fm Page 183 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
183 I L1 = iC1−off = kiI + = I I +
(2.327)
Therefore, the voltage transfer gain in continuous mode is MS + =
VO+ 1 = 1− k VI
(2.328)
The variation ratios of the parameters are ξ 2+ =
∆iL 2 / 2 k 1 = I L2 16 f 2 C2 L2
ρ+ =
∆vC1 / 2 (1 − k )I I + 1 = = k VC1 kfC 2 1R V 2 fC1 1− k I
and σ 1+ =
∆vC 2 / 2 k = VC 2 2 fC2 R
The variation ratio of the currents iD0 and iL1 is ζ + = ξ 1+ =
∆iL1 / 2 kVI T k R = = I L1 2L1 I I + MS 2 2 fL1
(2.329)
The variation ratio of output voltage vO+ is ε+ =
∆vO+ / 2 k 1 = VO+ 128 f 3 C2 CO L2 R
(2.330)
If L1 = L2 = 0.5 mH, C1 = C2 = CO = 20 µF, R = 40 Ω, f = 50 kHz, and k = 0.5, obtained that ξ1+ = ζ = 0.1, ρ+ = 0.00625; and σ1+ = 0.00625, ξ2+ = 0.00125 and ε = 0.000004. Therefore, the variations of iL1, vC1, iL2 and vC2 are small. The output voltage VO+ is almost a real DC voltage with very small ripple. Because of the resistive load, the output current iO+(t) is almost a real DC waveform with very small ripple as well, and IO+ = VO+/R. 2.6.2.2 Negative Conversion Path The equivalent circuit during switchon is shown in Figure 2.65a, and the equivalent circuit during switchoff in Figure 2.65b. The relations of the average currents and voltages are IO− = I L12 = IC11−on © 2003 by CRC Press LLC
IC11−off =
k 1− k
IC11−on =
k I 1 − k O−
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Advanced DC/DC Converters
S
iL12
iIN– iC12
+ VIN
L11 C12
iL11
–
– VC11 C 10
C11
VO –
R1
+
–
+
(a) switch on iL12
+ VC12 –
L12 iL11
L11
–
– VC11 C 10
iC11
VO –
R1
+
+
(b) switch off i L12
+ VC12 – VD0
i L11
L11
L12
–
– VC11 C 10 +
C11
R1
VO – +
(c) discontinuous conduction mode
FIGURE 2.65 Equivalent circuits of selflift circuit negative path: (a) switch on; (b) switch off; (c) discontinuous conduction mode.
and I L11 = IC11−off + IO− =
IO − 1− k
We know that I C12−off = I L11 =
1 I 1 − k O−
and
I C12−on =
1− k 1 I C12−off = I O− k k
So that VO− =
© 2003 by CRC Press LLC
1 V 1− k I
and
I O− = (1 − k )I I
(2.331)
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185
10
8
MS
6
4
2
0
0.2
0
0.4
0.6 k
0.8
1
FIGURE 2.66 Voltage transfer gain MS vs. k.
The voltage transfer gain in continuous mode: MS − =
VO− 1 = 1− k VI
(2.332)
Circuit (C11L12C10) is a “Π” type lowpass filter. Therefore, VC11 = VO− =
k V 1− k I
From Equation (2.328) and Equation (2.332), we define MS = MS+ = MS–. The curve of MS vs. k is shown in Figure 2.66. The variation ratios of the parameters are ξ− =
ρ− =
σ 1− =
∆iL12 / 2 k 1 = I L12 16 f 2 C10 L12
∆vC11 / 2 kI O− T k 1 = = VC11 2C11VO− 2 fC11R1 ∆vC12 / 2 I O− M 1 = = S 2 fC12VI 2 fC12 R1 VC12
The variation ratio of currents iD10 and iL11 is © 2003 by CRC Press LLC
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Advanced DC/DC Converters
ζ− =
R1 ∆iL11 / 2 k(1 − k )VI T k(1 − k )R1 k = = = I L11 2L11 I O− 2 MS fL11 MS 2 2 fL11
(2.333)
the variation ratio of current vC10 is ε− =
∆vC10 / 2 I O− 1 k k = = 128 f 3 C11C10 L12 VO− 128 f 3 C11C10 L12 R1 VC10
(2.334)
Assuming that f = 50 kHz, L11 = L12 = 0.5 µH, C11 = C10 = 20 µF, R1 = 40 Ω and k = 0.5, we obtain MS = 2, ζ– = 0.2, ρ– = 0.006, σ1– = 0.025, ξ– = 0.0006 and ε– = 0.000004. The output voltage VO– is almost a real DC voltage with very small ripple. Since the load is resistive, the output current iO–(t) is almost a real DC waveform with very small ripple as well, and it is equal to IO– = VO–/R1. 2.6.2.3 Discontinuous Conduction Mode The equivalent circuits of the discontinuous conduction mode’s operation are shown in Figure 2.64 and Figure 2.65 Since we select zN = zN+ = zN–, MS = MS+ = MS– and ζ = ζ+ = ζ– The boundary between continuous and discontinuous conduction modes is ζ≥1 or k zN ≥1 MS 2 2 Hence, MS ≤ k
z = 2
kz N 2
(2.335)
This boundary curve is shown in Figure 2.67. Compared with Equation (2.321) and Equation (2.335), this boundary curve has a minimum value of MS that is equal to 1.5 at k = ⅓. The filling efficiency is defined as: mS = For the current iL1 we have © 2003 by CRC Press LLC
2 1 2 MS = kz N ζ
(2.336)
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187
30 continuous mode
20 k=0.9 10
MS
8 k=0.8 5 3 2
k=0.5 k=0.33
1.5 k=0.1 1
discontinuous mode
13.56
24.7
62.5 R/fL
842
222
FIGURE 2.67 The boundary between continuous and discontinuous conduction modes and the output voltage vs. the normalized load zN = R/fL (selflift circuit).
kTVI = (1 – k)mS+TVC1 or VC1 =
z k V = k 2 (1 − k ) N VI (1 − k )mS I 2
with
kz N 1 ≥ 2 1− k
(2.337)
Therefore, the positive output voltage in discontinuous mode is VO+ = VC1 + VI = [1 +
z k ]V = [1 + k 2 (1 − k ) N ]VI (1 − k )mS I 2 kz N 1 ≥ 2 1− k
with For the current iL11 we have
kTVI = (1 – k)mST(VC11 – VI) or VC11 = [1 +
© 2003 by CRC Press LLC
z k ]VI = [1 + k 2 (1 − k ) N ]VI (1 − k )mS 2
(2.338)
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Advanced DC/DC Converters
kz N 1 ≥ 2 1− k
with
(2.339)
and for the current iL12 we have kT(VI + VC11 – VO–) = (1 – k)mS–T(VO– – VI) Therefore, the negative output voltage in discontinuous conduction mode is VO− = [1 +
z k ]VI = [1 + k 2 (1 − k ) N ]VI (1 − k )mS 2 kz N 1 ≥ 2 1− k
with
(2.340)
We then have VO = VO+ = VO− = [1 + k 2 (1 − k )
zN ]V 2 I
i.e., the output voltage will linearly increase during load resistance increasing. Larger load resistance causes higher output voltage in discontinuous conduction mode as shown in Figure 2.67.
2.6.3
ReLift Circuit
Relift circuit shown in Figure 2.68 is derived from selflift circuit. The positive conversion path consists of a pump circuit SL1D0C1 and a filter (C2)L2CO, and a lift circuit D1C2D3L3D2C3. The negative conversion path consists of a pump circuit SL11D10(C11) and a “Π”type filter C11L12C10, and a lift circuit D11C12L13D22C13D12. 2.6.3.1 Positive Conversion Path The equivalent circuit during switchon is shown in Figure 2.69a, and the equivalent circuit during switchoff in Figure 2.69b. The voltage across inductors L1 and L3 is equal to VI during switchon, and –(VC1 – VI) during switchoff. We have the relations: VC1 =
1+ k V 1− k I
© 2003 by CRC Press LLC
and
VO = VCO = VC 2 = VI + VC1 =
2 V 1− k I
1956_C02.fm Page 189 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
S
VS
iIN
D20
iIN+ +
– VC1 +
D2
i L1
–
L1
iIN– iL11 D21 D22
Io+
L2
+
iL2
D0
L3
C2
R
Co
Vo +
D3
–
D11
+
L11 C12
D1
C1
C3
VI N
189
D12 + VC11 –
L 13 C13
C11
R1
C10
Vo –
iL12
D10
–
L12 Io–
FIGURE 2.68 Relift circuit.
Thus, VO+ =
2 V 1− k I
I O+ =
1− k I 2 I+
and
The other relations are II+ = k iI+
iI+ = IL1 + IL3+ iC3–on + iC1–on
iC1−off =
k i 1 − k C1−on
and I L1 = I L 3 = iC1−off = iC 3−off =
k 1 i = I 2 I+ 2 I+
(2.341)
The voltage transfer gain in continuous mode is MR+ =
© 2003 by CRC Press LLC
VO+ 2 = 1− k VI
(2.342)
1956_C02.fm Page 190 Monday, August 18, 2003 3:26 PM
190
Advanced DC/DC Converters iIN+
S
iL2
– VC1 +
L2
+ VIN
i L1
L1
CO
L3 C2
C3
+ VO+
R
–
–
(a) switch on C3
iL2
– VC1 +
L2 i L1
L1
L3
CO
D0 C2
+ R
VO+ –
(b) switch off
C3
i L2
– VC1
L2 i L1
L1
L3
CO
VD0 C2
+ R
VO+ –
(c) discontinuous mode FIGURE 2.69 Equivalent circuits of relift circuit positive path: (a) switch on; (b) switch off; (c) discontinuous mode.
The variation ratios of the parameters are ξ 2+ =
∆iL 2 / 2 k 1 = I L2 16 f 2 C2 L2
ρ+ =
σ 1+ =
χ 1+ =
∆iL 3 / 2 kVI T k R = = 2 1 I L3 M R fL3 2 L3 I I + 2
∆vC1 / 2 (1 − k )TI I 1 = = + k 1 VC1 (1 + k ) fC1R 4C1 V 1− k I
∆vC 2 / 2 k = 2 fC2 R VC 2
© 2003 by CRC Press LLC
and
σ 2+ =
∆vC 3 / 2 1 − k I I + MR = = 4 fC3 VI 2 fC3 R VC 3
1956_C02.fm Page 191 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
191
The variation ratio of currents iD0 and iL1 is ζ + = ξ 1+ =
∆iD 0 / 2 kVI T k R = = I D0 L1 I I + M R 2 fL1
(2.343)
and the variation ratio of output voltage vO+ is ε+ =
∆vO+ / 2 k 1 = VO+ 128 f 3 C2 CO L2 R
(2.344)
If L1 = L2 = L3 = 0.5 mH, C1 = C2 = C3 = C0 = 20 µF, R = 160 Ω, f = 50 kHz, and k = 0.5, we obtained that ξ1 = ζ+ = 0.2, χ1 = 0.2, σ▫ = 0.0125, ρ = 0.004; and σ1 = 0.00156, ξ2 = 0.0125 and ε = 0.000001. Therefore, the variations of iL1, iL2 and iL3 are small, and the ripples of vC1, vC3 and vC2 are small. The output voltage vO+ (and vCO) is almost a real DC voltage with very small ripple. Because of the resistive load, the output current iO+ is almost a real DC waveform with very small ripple as well, and IO+ = VO+/R. 2.6.3.2 Negative Conversion Path The equivalent circuit during switchon is shown in Figure 2.70a, and the equivalent circuit during switchoff is shown in Figure 2.70b. The relations of the average currents and voltages are I C11−off =
IO– = IL12 = IC11–on
k k = I I 1 − k C11−on 1 − k O−
and I L11 = I C11−off + I O− =
I C12−off = I C13−off = I L11 =
1 I 1 − k O−
I C13−on =
I O− 1− k
I C12−on =
(2.345) 1− k 1 I C12−off = I O− k k
1− k 1 I C13−off = I O− k k
In steady state we have: VC12 = VC13 = VI
© 2003 by CRC Press LLC
VL13−on = VI
and
VL13−off =
k V 1− k I
1956_C02.fm Page 192 Monday, August 18, 2003 3:26 PM
192
Advanced DC/DC Converters i L12
iIN –
S +
iC12
VIN
iL11
L11
C12
iL13
iC13
L13C13
C11
L iC11 12
–
C10
R1
VO+
–
(a) switch on
C12
L13
L12
iL13 L11
iL12
C13
–
iC11 C10
C11
iL1
R1
VO+
(b) switch off C12
L13
C13
VD10
iL12 L12
–
– VC11 +
L11
C11 C10
R1
VO– +
(c) discontinuous mode FIGURE 2.70 Equivalent circuits of relift circuit negative path: (a) switch on; (b) switch off; (c) discontinuous mode.
VO− =
2 V 1− k I
and
I O− =
1− k I 2 I−
The voltage transfer gain in continuous mode is MR− =
VO− I 2 = I− = VI I O− 1 − k
Circuit (C11L12C10) is a “Π” type lowpass filter. Therefore, VC11 = VO− = © 2003 by CRC Press LLC
2 V 1− k I
(2.346)
1956_C02.fm Page 193 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
193
20
16
MR
12
8
4
0 0
0.2
0.6
0.4
0.8
1
k
FIGURE 2.71 Voltage transfer gain MR vs. k.
From Equation (2.342) and Equation (2.346) we define MR = MR+ = MR–. The curve of MR vs. k is shown in Figure 2.71. The variation ratios of the parameters are ξ− =
and
χ 1− =
∆iL12 / 2 k 1 = 2 I L12 16 f C10 L12
∆iL13 / 2 kTVI k(1 − k ) R1 (1 − k ) = = 2L13 I O− 2 M R fL13 I L13
ρ− =
∆vC11 / 2 kI O− T k 1 = = VC11 2C11VO− 2 fC11R1
σ 1− =
∆vC12 / 2 I O− M 1 = = R VC12 2 fC12VI 2 fC12 R1
σ 2− =
∆vC13 / 2 I O− M 1 = = R VC13 2 fC13VI 2 fC13 R1
The variation ratio of the current iD10 and iL11 is ζ− =
∆iL11 / 2 k(1 − k )VI T k(1 − k )R1 k R1 = = = I L11 2L11 I O− 2 M R fL11 M R 2 fL11
© 2003 by CRC Press LLC
(2.347)
1956_C02.fm Page 194 Monday, August 18, 2003 3:26 PM
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Advanced DC/DC Converters
The variation ratio of current vC10 is ε− =
∆vC10 / 2 I O− k k 1 = = VC10 128 f 3 C11C10 L12 VO− 128 f 3 C11C10 L12 R1
(2.348)
Assuming that f = 50 kHz, L11 = L12 = 0.5 mH, C = CO = 20 µF, R1 = 160 Ω and k = 0.5, we obtain MR = 4, ζ– = 0.2, ρ– = 0.0016, σ1– = σ2– = 0.0125, ξ– = 0.00125 and ε– = 10–6. The output voltage VO– is almost a real DC voltage with very small ripple. Since the load is resistive, the output current iO–(t) is almost a real DC waveform with very small ripple as well, and it is equal to IO– = VO–/R1. 2.6.3.3 Discontinuous Conduction Mode The equivalent circuits of the discontinuous conduction mode are shown in Figure 2.69 and Figure 2.70. In order to obtain the mirrorsymmetrical double output voltages, we purposely select zN = zN+ = zN– and ζ = ζ+ = ζ–. The freewheeling diode currents iD0 and iD10 become zero during switch off before next period switch on. The boundary between continuous and discontinuous conduction modes is ζ≥1 or k z ≥1 MR 2 N Hence, M R ≤ kz N
(2.349)
This boundary curve is shown in Figure 2.71. Comparing with Equations (2.321), (2.335), and (2.349), it can be seen that the boundary curve has a minimum value of MR that is equal to 3.0, corresponding to k = ⅓. The filling efficiency mR is mR =
2 1 MR = ζ kz N
So VC1 = [1 + © 2003 by CRC Press LLC
z 2k ]V = [1 + k 2 (1 − k ) N ]VI (1 − k )mR I 2
(2.350)
1956_C02.fm Page 195 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
195
with kz N ≥
2 1− k
(2.351)
Therefore, the positive output voltage in discontinuous conduction mode is VO+ = VC1 + VI = [2 +
z 2k ]V = [2 + k 2 (1 − k ) N ]VI (1 − k )mR I 2 kz N ≥
with
2 1− k
(2.352)
For the current iL11 because inductor current iL13 = 0 at t = t1, so that VL13−off =
k V (1 − k )mR I
for the current iL11 we have kTVI = (1 – k)mRT(VC11 – 2VI – VL13–off) or VC11 = [2 +
z 2k ]V = [2 + k 2 (1 − k ) N ]VI (1 − k )mR I 2
with
kz N ≥
2 1− k
(2.353)
and for the current iL12 kT(VI + VC11 – VO–) = (1 – k)mRT(VO– – 2VI – VL13–off) Therefore, the negative output voltage in discontinuous conduction mode is VO− = [2 +
z 2k ]VI = [2 + k 2 (1 − k ) N ]VI (1 − k )mR 2
with
So VO = VO+ = VO− = [2 + k 2 (1 − k )
© 2003 by CRC Press LLC
zN ]V 2 I
kz N ≥
2 1− k
(2.354)
1956_C02.fm Page 196 Monday, August 18, 2003 3:26 PM
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Advanced DC/DC Converters
60 k=0.95
continuous mode
40 k=0.9
MR
20 k=0.8 10 6 4 3
k=0.5 k=0.33 k=0.1
2
27 32
discontinuous mode 50
125 R/fL
444
1684
FIGURE 2.72 The boundary between continuous and discontinuous modes and the output voltage vs. the normalized load zN = R/fL (relift circuit).
i.e., the output voltage will linearly increase during load resistance increasing. Larger load resistance may cause higher output voltage in discontinuous mode as shown in Figure 2.72.
2.6.4
MultipleLift Circuit
Referring to Figure 2.68, it is possible to build a multiplelifts circuit only using the parts (L3D20C3D3) multiple times in the positive conversion path, and using the parts (D22L13C13D12) multiple times in the negative conversion path. For example, in Figure 2.73 the parts (L4D4C4D5) and parts (D23L14C14D13) were added in the triplelift circuit. According to this principle, triplelift circuits and quadruplelift circuits have been built as shown in Figure 2.73 and Figure 2.76. In this book it is not necessary to introduce the particular analysis and calculations one by one to readers. However, their calculation formulas are shown in this section. 2.6.4.1 TripleLift Circuit Triplelift circuit is shown in Figure 2.73. The positive conversion path consists of a pump circuit SL1D0C1 and a filter (C2)L2CO, and a lift circuit D1C2 D2C3D3L3D4C4D5L4. The negative conversion path consists of a pump circuit SL11D10(C11) and a “Π”type filter C11L12C10, and a lift circuit D11C12D22C13L13D12D23L14C14D13.
© 2003 by CRC Press LLC
1956_C02.fm Page 197 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
S
VS
iIN
iIN+ +
D2
D20
C3 i L1
–
– VC1 +
D4
VI N
197
iIN– i L11
L4
L3
D21
D0
C2
+
R
Co
Vo +
D5
–
D11
D12
+
L14
C13
C12
iL2
D3
L13
L11
Io+
L2
C1
C4
L1
D1
D13 + VC11
C11
D23
Vo –
iL12
D10–
D22
R1
C10
–
C14 L12
Io –
FIGURE 2.73 Triplelift circuit.
2.6.4.1.1 Positive Conversion Path The lift circuit is D1C2D2C3D3L3D4C4D5L4. Capacitors C2, C3, and C4 perform characteristics to lift the capacitor voltage VC1 by three times of source voltage VI. L3 and L4 perform the function as ladder joints to link the three capacitors C3 and C4 and lift the capacitor voltage VC1 up. Current iC2(t), iC3(t), and iC4(t) are exponential functions. They have large values at the moment of power on, but they are small because vC3 = vC4 = VI and vC2 = VO+ in steady state. The output voltage and current are VO+ =
3 V 1− k I
and
I O+ =
1− k I 3 I+
The voltage transfer gain in continuous mode is MT + =
VO+ 3 = 1− k VI
Other average voltages: VC1 =
© 2003 by CRC Press LLC
2+k V 1− k I
VC3 = VC4 = VI
VCO = VC2 = VO+
(2.355)
1956_C02.fm Page 198 Monday, August 18, 2003 3:26 PM
198
Advanced DC/DC Converters
Other average currents: IL2 = IO+
1 1 II+ = I 3 1 − k O+
I L1 = I L 3 = I L 4 =
Current variations: ξ 1+ = ζ + =
k(1 − k )R k 3R = 2 MT fL MT 2 2 fL
χ 1+ =
k 3R MT 2 2 fL3
ξ 2+ =
χ 2+ =
k 1 16 f 2 C2 L2
k 3R MT 2 2 fL4
Voltage variations: ρ+ =
3 2(2 + k ) fC1R
σ 2+ =
MT 2 fC3 R
σ 1+ =
σ 3+ =
k 2 fC2 R
MT 2 fC4 R
The variation ratio of output voltage VC0 is ε+ =
k 1 128 f 3 C2 CO L2 R
(2.356)
2.6.4.1.2 Negative Conversion Path Circuit C12D11L13D22C13D12L14D23C14D13 is the lift circuit. Capacitors C12, C13, and C14 perform characteristics to lift the capacitor voltage VC11 by three times the source voltage VI. L13 and L14 perform the function as ladder joints to link the three capacitors C12, C13, and C14 and lift the capacitor voltage VC11 up. Current iC12(t), iC13(t) and iC14(t) are exponential functions. They have large values at the moment of power on, but they are small because vC12 = vC13 = vC14 ≅ VI in steady state. The output voltage and current are VO− =
3 V 1− k I
and
I O− =
1− k I 3 I−
The voltage transfer gain in continuous mode is MT − = VO− / VI = © 2003 by CRC Press LLC
3 1− k
(2.357)
1956_C02.fm Page 199 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
199
30
24
MT
18
12
6
0 0
0.2
0.6
0.4
0.8
1
k
FIGURE 2.74 Voltage transfer gain MT vs. k.
From Equation (2.355) and Equation (2.357) we define MT = MT+ = MT–. The curve of MT vs. k is shown in Figure 2.74. Other average voltages: VC11 = VO–
VC12 = VC13 = VC14 = VI
Other average currents: IL12 = IO–
I L11 = I L13 = I L14 =
1 I 1 − k O−
Current variation ratios: k 3R1 MT 2 2 fL11
ζ− =
χ 1− =
k(1 − k ) R1 2 MT fL13
ξ 2− =
k 1 16 f 2 C10 L12
χ 2− =
k(1 − k ) R1 2 MT fL14
Voltage variation ratios: ρ− =
σ 2− = © 2003 by CRC Press LLC
k 1 2 fC11R1 MT 1 2 fC13 R1
σ 1− =
MT 1 2 fC12 R1
σ 3− =
MT 1 2 fC14 R1
1956_C02.fm Page 200 Monday, August 18, 2003 3:26 PM
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Advanced DC/DC Converters
The variation ratio of output voltage VC10 is ε− =
k 1 128 f 3 C11C10 L12 R1
(2.358)
2.6.4.1.3 Discontinuous Mode To obtain the mirrorsymmetrical double output voltages, we purposely select: L1 = L11 and R = R1. Define: VO = VO+ = VO−
MT = MT + = MT − =
VO 3 = VI 1 − k
zN = zN+ = zN–
ζ = ζ+ = ζ–
and
The freewheeling diode currents iD0 and iD10 become zero during switch off before next period switch on. The boundary between continuous and discontinuous conduction modes is ζ≥1 Then MT ≤
3kz N 2
(2.359)
This boundary curve is shown in Figure 2.75. Comparing Equation (2.321), Equation (2.335), Equation (2.349), and Equation (2.359), it can be seen that the boundary curve has a minimum value of MT that is equal to 4.5, corresponding to k = ⅓. In discontinuous mode the currents iD0 and iD10 exist in the period between kT and [k + (1 – k)mT]T, where mT is the filling efficiency that is mT =
2 1 2 MT = ζ 3kz N
(2.360)
Considering Equation (2.359), therefore 0 < mT < 1. Since the current iD0 becomes zero at t = t1 = [k + (1 – k)mT]T, for the current iL1, iL3 and iL4 3kTVI = (1 – k)mTT(VC1 – 2VI) or VC1 = [2 + © 2003 by CRC Press LLC
z 3k ]VI = [2 + k 2 (1 − k ) N ]VI (1 − k )mT 2
1956_C02.fm Page 201 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
201
40 continuous mode
MT
30 k=0.9
15
6 4.5
k=0.8
k=0.5 discontinuous mode
k=0.33 k=0.1
3
40 48
75
188
667
R/fL
FIGURE 2.75 The boundary between continuous and discontinuous modes and the output voltage vs. the normalized load zN = R/fL (triplelift circuit).
3kz N 3 ≥ 2 1− k
with
(2.361)
Therefore, the positive output voltage in discontinuous mode is VO+ = VC1 + VI = [3 +
z 3k ]VI = [3 + k 2 (1 − k ) N ]VI (1 − k )mT 2 3kz N 3 ≥ 2 1− k
with
Because inductor current iL11 = 0 at t = t1, so that VL13−off = VL14−off =
k V (1 − k )mT I
Since iD10 becomes 0 at t1 = [k + (1 – k)mT]T, for the current iL11, kTVI = (1 – k)mT–T(VC11 – 3VI – VL13–off – VL14–off) VC11 = [3 + © 2003 by CRC Press LLC
z 3k ]VI = [3 + k 2 (1 − k ) N ]VI (1 − k )mT 2
(2.362)
1956_C02.fm Page 202 Monday, August 18, 2003 3:26 PM
202
Advanced DC/DC Converters
3kz N 3 ≥ 2 1− k
with
(2.363)
for the current iL12 kT(VI + VC14 – VO–) = (1 – k)mT–T(VO– – 2VI – VL13–off – VL14–off) Therefore, the negative output voltage in discontinuous mode is VO− = [3 +
z 3k ]VI = [3 + k 2 (1 − k ) N ]VI (1 − k )mT 2 3kz N 3 ≥ 2 1− k
with
(2.364)
So VO = VO+ = VO− = [3 + k 2 (1 − k )
zN ]V 2 I
i.e., the output voltage will linearly increase during load resistance increasing, as shown in Figure 2.75. 2.6.4.2 QuadrupleLift Circuit Quadruplelift circuit is shown in Figure 2.76. The positive conversion path consists of a pump circuit SL1D0C1 and a filter (C2)L2CO, and a lift circuit D1C2L3D2C3D3L4D4C4D5L5D6C5S1. The negative conversion path consists of a pump circuit SL11D10(C11) and a “Π”type filter C11L12C10, and a lift circuit D11C12D22L13C13D12D23L14C14D13D24L15C15D14. 2.6.4.2.1 Positive Conversion Path Capacitors C2, C3, C4, and C5 perform characteristics to lift the capacitor voltage VC1 by four times the source voltage VI. L3, L4, and L5 perform the function as ladder joints to link the four capacitors C2, C3, C4, and C5, and lift the output capacitor voltage VC1 up. Current iC2(t), iC3(t), iC4(t) and iC5(t) are exponential functions. They have large values at the moment of power on, but they are small because vC3 = vC4 = vC5 = VI and vC2 = VO+ in steady state. The output voltage and current are VO+ = © 2003 by CRC Press LLC
4 V 1− k I
and
I O+ =
1− k I 4 I+
1956_C02.fm Page 203 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
S iIN
VS
D20 D2
iIN+ +
D4
C3
VI N
203
iL1
–
L5
D3
D5
D7
D11
D12
D13
L11
D21
L4
D1
Io+
L2
C1
C5
L3
iIN– iL11
D6
C4
L1
– VC1 +
iL2
D0
C2
+
R
Co
– D14 + VC11 –
L13
C12
C11
R1
C10
C14
D23
+ Vo –
C13
D22
Vo +
– C15
D24
iL12
D10
L12
Io –
FIGURE 2.76 Quadruplelift circuit.
The voltage transfer gain in continuous mode is MQ+ =
VO+ 4 = 1− k VI
(2.365)
Other average voltages: VC1 =
3+k V 1− k I
VC3 = VC4 = VC5 = VI
VCO = VC2 = VO
Other average currents: IL2 = IO+
I L1 = I L 3 = I L 4 = I L 5 =
1 1 I = I 4 I + 1 − k O+
Current variations: ξ 1+ = ζ + =
χ 1+ = © 2003 by CRC Press LLC
k(1 − k )R k 2R = 2 MQ fL MQ 2 fL
k 2R MQ 2 fL3
χ 2+ =
k 2R MQ 2 fL4
ξ 2+ =
1 k 16 f 2 C2 L2
χ 3+ =
k 2R MQ 2 fL5
1956_C02.fm Page 204 Monday, August 18, 2003 3:26 PM
204
Advanced DC/DC Converters
Voltage variations: ρ+ =
σ 2+ =
2 (3 + 2 k ) fC1R
MQ 2 fC3 R
σ 3+ =
MQ
σ 1+ = MQ
2 fC4 R
2 fC2 R σ 4+ =
MQ 2 fC5 R
The variation ratio of output voltage VC0 is ε+ =
k 1 3 128 f C2 C0 L2 R
(2.366)
2.6.4.2.2 Negative Conversion Path Capacitors C12, C13, C14, and C15 perform characteristics to lift the capacitor voltage VC11 by four times the source voltage VI. L13, L14, and L15 perform the function as ladder joints to link the four capacitors C12, C13, C14, and C15 and lift the output capacitor voltage VC11 up. Current iC12(t), iC13(t), iC14(t), and iC15(t) are exponential functions. They have large values at the moment of power on, but they are small because vC12 = vC13 = vC14 = vC15 ≅ VI in steady state. The output voltage and current are VO− =
4 V 1− k I
and
I O− =
1− k I 4 I−
The voltage transfer gain in continuous mode is MQ− = VO− / VI =
4 1− k
(2.367)
From Equation (2.365) and Equation (2.367) we define MQ = MQ+ = MQ–. The curve of MQ vs. k is shown in Figure 2.77. Other average voltages: VC10 = VO–
VC12 = VC13 = VC14 = VC15 = VI
Other average currents: IL12 = IO–
© 2003 by CRC Press LLC
I L11 = I L13 = I L14 = I L15 =
1 I 1 − k O−
1956_C02.fm Page 205 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
205
40
32
MQ
24
16
8
0 0
0.2
0.6
0.4
1
0.8
k
FIGURE 2.77 Voltage transfer gain MQ vs. k.
Current variation ratios: ζ− =
χ 1− =
k(1 − k ) R1 2 MQ fL13
k 2 R1 MQ 2 fL11 χ 2− =
k 1 16 f 2 CL12
ξ− =
k(1 − k ) R1 2 MQ fL14
χ 3− =
k(1 − k ) R1 2 MQ fL15
Voltage variation ratios: ρ− =
σ 2− =
MQ
1
2 fC13 R1
k 1 2 fC11R1 σ 3− =
σ 1− = MQ
MQ
1
2 fC12 R1
1
2 fC14 R1
σ 4− =
MQ
1 2 fC15 R1
The variation ratio of output voltage VC10 is ε− =
k 1 3 128 f C11C10 L12 R1
The output voltage ripple is very small.
© 2003 by CRC Press LLC
(2.368)
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206
Advanced DC/DC Converters 60 50 40
continuous mode
k=0.9
30 k=0.8
MQ
20
10 8 6
k=0.5 k=0.33 discontinuous mode
k=0.1 2
54 64
100
250 R/fL
889
FIGURE 2.78 The boundary between continuous and discontinuous modes and the output voltage vs. the normalized load zN = R/fL (quadruplelift circuit).
2.6.4.2.3 Discontinuous Conduction Mode In order to obtain the mirrorsymmetrical double output voltages, we purposely select: L1 = L11 and R = R1. Therefore, we may define VO = VO+ = VO− and
MQ = MQ+ = MQ− =
VO 4 = VI 1 − k
zN = zN+ = zN–
ζ = ζ+ = ζ–
The freewheeling diode currents iD0 and iD10 become zero during switch off before next period switch on. The boundary between continuous and discontinuous conduction modes is ζ≥1 or
MQ ≤ 2 kz N
(2.369)
This boundary curve is shown in Figure 2.78. Comparing Equations (2.321), (2.335), (2.349), (2.359), and (2.369), it can be seen that this boundary curve has a minimum value of MQ that is equal to 6.0, corresponding to k = ⅓.
© 2003 by CRC Press LLC
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VoltageLift Converters
207
In discontinuous mode the currents iD0 and iD10 exist in the period between kT and [k + (1 – k)mQ]T, where mQ is the filling efficiency that is mQ =
2 1 MQ = ζ 2 kz N
(2.370)
Considering Equation (2.369), therefore 0 < mQ < 1. Since the current iD0 becomes zero at t = t1 = kT + (1 – k)mQT, for the current iL1, iL3, iL4 and iL5 4kTVI = (1 – k)mQT(VC1 – 3VI) VC1 = [3 +
z 4k ]V = [3 + k 2 (1 − k ) N ]VI (1 − k )mQ I 2 2 kz N ≥
with
4 1− k
(2.371)
Therefore, the positive output voltage in discontinuous conduction mode is VO+ = VC1 + VI = [4 +
z 4k ]VI = [4 + k 2 (1 − k ) N ]VI (1 − k )mQ 2 2 kz N ≥
with
4 1− k
(2.372)
Because inductor current iL11 = 0 at t = t1, so that VL13−off = VL14−off = VL15−off =
k V (1 − k )mQ I
Since the current iD10 becomes zero at t = t1 = kT + (1 – k)mQT, for the current iL11 we have kTVI = (1 – k)mQ–T(VC11 – 4VI – VL13–off – VL14–off – VL15–off) So VC11 = [4 +
with © 2003 by CRC Press LLC
z 4k ]VI = [4 + k 2 (1 − k ) N ]VI (1 − k )mQ 2 2 kz N ≥
4 1− k
(2.373)
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Advanced DC/DC Converters
TABLE 2.3 Comparison among Five Circuits of Double Output LuoConverters Double Output LuoConverters
IO
Elementary Circuit
IO =
SelfLift Circuit
I O = (1 − k )I S
ReLift Circuit
IO =
TripleLift Circuit QuadrupleLift Circuit
VO
k = 0.33
k = 0.5
VO(VS = 10 V) k = 0.75 k = 0.9
VO =
k V 1− k S
5V
10 V
30 V
90 V
VO =
1 V 1− k S
15 V
20 V
40 V
100 V
1− k I 2 S
VO =
2 V 1− k S
30 V
40 V
80 V
200 V
IO =
1− k I 3 S
VO =
3 V 1− k S
45 V
60 V
120 V
300 V
IO =
1− k I 4 S
VO =
4 V 1− k S
60 V
80 V
160 V
400 V
1− k I k S
For the current iL12 kT(VI + VC15 – VO–) = (1 – k)mQT(VO– – 2VI – VL13–off – VL14–off – VL15–off) Therefore, the negative output voltage in discontinuous conduction mode is VO− = [4 +
z 4k ]V = [4 + k 2 (1 − k ) N ]VI (1 − k )mQ I 2 2 kz N ≥
with
4 1− k
(2.374)
So VO = VO+ = VO− = [4 + k 2 (1 − k )
zN ]V 2 I
i.e., the output voltage will linearly increase during load resistance increasing, as shown in Figure 2.78.
2.6.5
Summary
2.6.5.1 Positive Conversion Path From the analysis and calculation in previous sections, the common formulae can be obtained for all circuits:
© 2003 by CRC Press LLC
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VoltageLift Converters
209
M=
VO+ I = I+ VI I O+ L=
VO+ I O+
R fL
R=
ξ 2+ =
k R 2 ME fL2
zN =
L1L2 L1 + L2
for elementary circuits only; L = L1 for other lift circuit’s current variations: ξ 1+ =
1− k R 2 ME fL1
and
for elementary circuit only; ξ 1+ = ζ + =
k(1 − k )R 2 MfL
ξ 2+ =
and
k 1 16 f 2 C2 L2
for other lift circuits ζ+ =
k(1 − k )R 2 MfL
χ j+ =
k R 2 M fL j + 2
(j = 1, 2, 3, …)
Voltage variations are ρ+ =
k 2 fC1R
ε+ =
k 1 8 ME f 2 C0 L2
for elementary circuit only; ρ+ =
M 1 M − 1 2 fC1R
ε+ =
k 1 3 128 f C2 C0 L2 R
for other lift circuits σ 1+ =
© 2003 by CRC Press LLC
k 2 fC2 R
σ j+ =
M 2 fC j +1R
(j = 2, 3, 4, …)
1956_C02.fm Page 210 Monday, August 18, 2003 3:26 PM
210
Advanced DC/DC Converters
2.6.5.2 Negative Conversion Path From the analysis and calculation in previous sections, the common formulae can be obtained for all circuits: M=
VO− I = I− VI I O−
zN − =
R1 fL11
R1 =
VO− I O−
Current variation ratios: ζ− =
k(1 − k )R1 2 MfL11
ξ− =
k 16 f 2 C11L12
χ j− =
k(1 − k )R1 2 MfL j + 2
(j = 1, 2, 3, …)
Voltage variation ratios: ρ− =
k 2 fC11R1
ε− =
k 128 f 3 C11C10 L12 R1
σ j− =
M 2 fC j +11R1
(j = 1, 2, 3, 4, …)
2.6.5.3 Common Parameters Usually, we select the loads R = R1, L = L11, so that we have got zN = zN+ = zN–. In order to write common formulas for the boundaries between continuous and discontinuous modes and output voltage for all circuits, the circuits can be numbered. The definition is that subscript 0 means the elementary circuit, subscript 1 means the selflift circuit, subscript 2 means the relift circuit, subscript 3 means the triplelift circuit, subscript 4 means the quadruplelift circuit, and so on. The voltage transfer gain is Mj =
k h( j ) [ j + h( j )] 1− k
j = 0, 1, 2, 3, 4, …
The characteristics of output voltage of all circuits are shown in Figure 2.79. The freewheeling diode current’s variation is ζj =
k [1+ h( j )] j + h( j ) zN 2 Mj2
The boundaries are determined by the condition: ζj ≥ 1 or © 2003 by CRC Press LLC
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VoltageLift Converters
211
120
output voltage, vo, v
100 80
(i)
50 (ii) (iii)
30
(iv)
10
(v)
0.2
0
0.6 0.4 conduction duty k
0.8
1
FIGURE 2.79 Output voltages of all double output Luoconverters (Vi = 10 V).
k [1+ h( j )] j + h( j ) zN ≥ 1 2 Mj2
j = 0, 1, 2, 3, 4, …
Therefore, the boundaries between continuous and discontinuous modes for all circuits are Mj = k
1+ h ( j ) 2
j + h( j ) zN 2
j = 0, 1, 2, 3, 4, …
The filling efficiency is 2
Mj 1 2 1 mj = = [1+ h( j )] j + h( j ) z N ζj k
j = 0, 1, 2, 3, 4, …
The output voltage in discontinuous mode for all circuits VO− j = [ j + k [ 2− h( j )]
1− k z ]V 2 N I
where 0 h( j ) = 1
if if
© 2003 by CRC Press LLC
j≥1 j=0
j = 0, 1, 2, 3, 4, …
h(j) is the Hong Function
1956_C02.fm Page 212 Monday, August 18, 2003 3:26 PM
212
Advanced DC/DC Converters
voltage transfer gain M
continuous mode
MQ MT
6 4.5
MR
3 Ms 1.5 ME discontinuous mode 0.5
4.5
27 40.5 54 13.5 normalized load zN R/fL
FIGURE 2.80 Boundaries between continuous and discontinuous modes of all double output LuoConverters.
The boundaries between continuous and discontinuous modes of all circuits are shown in Figure 2.80. The curves of all M vs. zN state that the continuous mode area increases from ME via MS, MR, MT to MQ. The boundary of elementary circuit is a monorising curve, but other curves are not monorising. There are minimum values of the boundaries of other curves, which of MS, MR, MT, and MQ correspond at k = ⅓.
Bibliography Chen, X.F., Luo, F.L., and Ye, H., Modified positive output Luo converters, in Proceedings of the IEEE International Conference PEDS’99, Hong Kong, 1999, p. 450. Farkas, T. and Schecht, M.F., Viability of active EMI filters for utility applications, IEEE Transactions on Power Electronics, 9, 328, 1994. Hart, D., Introduction to Power Electronics, Prentice Hall, New York, 1997. Jozwik, J.J. and Kazimerczuk, M.K., Dual sepic PWM switchingmode DC/DC power converter, IEEE Transactions on Industrial Electronics, 36, 64, 1989. Krein, P., Elements of Power Electronics, Oxford University Press, 1998. LaWhite, I.E. and Schlecht, M.F., Active filters for 1 MHz power circuits with strict input/output ripple requirements, IEEE Transactions on Power Electronics, 2, 282, 1987. Luo, F.L., Positive output Luoconverters: voltage lift technique, IEE Proceedings on Electric Power Applications, 146, 415, 1999. Luo, F.L., Negative output LuoConverters: voltage lift technique, IEE Proceedings on Electric Power Applications, 146, 208, 1999. Luo, F.L., Double output Luoconverters: advanced voltage lift technique, IEEProceedings on Electric Power Applications, 147, 469, 2000.
© 2003 by CRC Press LLC
1956_C02.fm Page 213 Monday, August 18, 2003 3:26 PM
VoltageLift Converters
213
Luo, F.L., Six selflift DC/DC converters: voltagelift technique, IEEE Transactions on Industrial Electronics, 48, 1268, 2001. Luo, F.L., Seven selflift DC/DC converters: voltagelift technique, IEE Proceedings on Electric Power Applications, 148, 329, 2001. Martins, D.C., Application of the Zeta converter in switchmode power supplies, in Proceedings of IEEE APEC’93, U.S., 1993, p. 214. Maksimovic, D. and Cúk, S., A general approach to synthesis and analysis of quasiresonant converters, IEEE Transactions on Power Electronics, 6, 127, 1991. Maksimovic, D. and Cúk, S., Constantfrequency control of quasiresonant converters, IEEE Transactions on Power Electronics, 6, 141, 1991. Massey, R.P. and Snyder, E.C., High voltage singleended DCDC converter, in Proceedings of IEEE PESC’77, Record. 1977, p. 156. Newell, W.E., Power electronicsemerging from limbo, in Proceedings of IEEE Power Electronics Specialists Conference, U.S., 1993, p. 6. Walker, J., Design of practical and effective active EMI filters, in Proceedings of Poweron 11, U.S., 1984, p. 1. Zhu, W., Perreault, D.J., Caliskan, V., Neugebauer, T.C., Guttowski, S., and Kassakian, J.G., Design and evaluaion of an active ripple filter with Rogowskicoil current sensing, in Proceedings of the 30th Annual IEEEPESC’99, U.S., 1999, p. 874.
© 2003 by CRC Press LLC
1956_C03.fm Page 215 Thursday, August 7, 2003 10:10 PM
3 Positive Output SuperLift LuoConverters
Voltage lift (VL) technique has been successfully employed in design of DC/ DC converters, e.g., three series Luoconverters. However, the output voltage increases in arithmetic progression. SuperLift (SL) technique is more powerful than VL technique, its voltage transfer gain can be a very large number. SL technique implements the output voltage increasing in geometric progression. It effectively enhances the voltage transfer gain in power series.
3.1
Introduction
This chapter introduces positive output super lift Luoconverters. In order to differentiate these converters from existing VL converters, these converters are called positive output superlift Luoconverters. There are several subseries: • Main series — Each circuit of the main series has only one switch S, n inductors for nth stage circuit, 2n capacitors, and (3n – 1) diodes. • Additional series — Each circuit of the additional series has one switch S, n inductors for nth stage circuit, 2(n + 1) capacitors, and (3n + 1) diodes. • Enhanced series — Each circuit of the enhanced series has one switch S, n inductors for nth stage circuit, 4n capacitors, and (5n – 1) diodes. • Reenhanced series — Each circuit of the reenhanced series has one switch S, n inductors for nth stage circuit, 6n capacitors, and (7n – 1) diodes. • Multiple (j)enhanced series — Each circuit of the multiple (j times)enhanced series has one switch S, n inductors for nth stage circuit, 2(1 + j)n capacitors and [(3 + 2j)n – 1] diodes. In order to concentrate the voltage enlargement, assume the converters are working in steady state with continuous conduction mode (CCM). The conduction duty ratio is k, switch frequency is f, switch period is T = 1/f,
© 2003 by CRC Press LLC
1956_C03.fm Page 216 Thursday, August 7, 2003 10:10 PM
the load is resistive load R. The input voltage and current are Vin and Iin, out voltage and current are VO and IO. Assume no power losses during the conversion process, Vin × Iin = VO × IO. The voltage transfer gain is G: G=
3.2
VO Vin
Main Series
The first three stages of positive output superlift Luoconverters — main series — are shown in Figure 3.1 through Figure 3.3. For convenience, they are called elementary circuits, relift circuit, and triplelift circuit respectively, and are numbered as n = 1, 2, and 3.
3.2.1
Elementary Circuit
The elementary circuit and its equivalent circuits during switchon and off are shown in Figure 3.1. The voltage across capacitor C1 is charged to Vin. The current iL1 flowing through inductor L1 increases with voltage Vin during switchon period kT and decreases with voltage –(VO – 2Vin) during switchoff period (1 – k)T. Therefore, the ripple of the inductor current iL1 is ∆iL1 =
V − 2Vin Vin (1 − k )T kT = O L1 L1
(3.1)
2−k V 1 − k in
(3.2)
VO 2 − k = Vin 1 − k
(3.3)
VO = The voltage transfer gain is G=
The input current iin is equal to (iL1 + iC1) during switchon, and only equal to iL1 during switchoff. Capacitor current iC1 is equal to iL1 during switchoff. In steady–state, the average charge across capacitor C1 should not change. The following relations are obtained: iin−off = iL1−off = iC1−off © 2003 by CRC Press LLC
iin−on = iL1−on + iC1−on
kTiC1−on = (1 − k )TiC1−off
1956_C03.fm Page 217 Thursday, August 7, 2003 10:10 PM
Iin
D1
D2 IO
+ L1
+ VC1
C1
–
Vin
+ C2
VC2
+ R
–
S
VO –
–
(a) Circuit diagram Iin IO + + Vin
L1
Vin C2
C1
+ VC2
R
–
–
+ VO –
–
(b) Equivalent circuit during switchingon I in
L1
+
VL1
C1 IO – Vin +
Vin
C2
+ VC2
R
–
+ VO –
–
(c) Equivalent circuit during switchingoff FIGURE 3.1 Elementary circuit.
If inductance L1 is large enough, iL1 is nearly equal to its average current IL1. Therefore, iin−off = iC1−off = I L1
iin−on = I L1 +
I 1− k I L1 = L1 k k
iC1−on =
1− k I k L1
and average input current I in = kiin−on + (1 − k )iin−off = I L1 + (1 − k )I L1 = (2 − k )I L1 Considering Vin 1 − k 2 VO 1− k 2 =( =( ) ) R I in 2 − k IO 2−k © 2003 by CRC Press LLC
(3.4)
1956_C03.fm Page 218 Thursday, August 7, 2003 10:10 PM
Iin
D1
D2
D4
V1
D5 IO
+ VC1 –
+ L1
C1
L2
+ VC3 –
C3
+
Vin
R D3
+ VC2 –
C2
–
S
VO –
+ VC4 –
C4
(a) Circuit diagram Iin
V1
IO
+ Vin L1
C1
+ Vin
+ VC2 L2
C2
–
–
+ VC4 R –
+ C4 V1
C3
–
+ VO –
–
(b) Equivalent circuit during switchingon Iin
C1
L1
V1
L2
C3 IO
+
VL1
VL2
– Vin +
Vin
C2
+ V1
– V1 + C4
+ VC4
–
R
–
+ VO –
–
(c) Equivalent circuit during switchingoff FIGURE 3.2 Relift circuit.
the variation ratio of current iL1 through inductor L1 is ξ1 =
∆iL1 / 2 k(2 − k )TVin k(1 − k )2 R = = 2L1 I in 2(2 − k ) fL1 I L1
(3.5)
Usually ξ1 is small (much lower than unity), it means this converter normally works in the continuous mode. The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C2 C2 fC2 R
Therefore, the variation ratio of output voltage vO is ε= © 2003 by CRC Press LLC
∆vO / 2 1− k = 2 RfC2 VO
(3.6)
1956_C03.fm Page 219 Thursday, August 7, 2003 10:10 PM
I in
D1
D2
D4
V1
D5
D7
V2
D8
IO +
L1
+
C1
+
VC1
Vin
C3
L2
+
VC3
_
C5
L3
VC5
_
+
_
R
_
D3
D6
+
C2
VC4
_
+
S
+
C4
VC2
VO
C6
_
_
VC6
_
(a) Circuit diagram
I in
V1 +
+
Vin L1
C1
_
+
Vin C2
L2 V1
_
_
IO
V2 +
+
C3
V1
L3 V2
_
_
C4
C6
+
C5
V2
+
+
VC6
VO
R
_
_
_
(b) Equivalent circuit during switchon
I in +
L1
V L1
C1 _
Vin _
Vin
V1
L2
V L2
+
C2
+
V1
C3 _
V1
V2
V L3
+
C4
_
L3
C5 _
+
V2
V2
IO +
C6
+
+
VC 6 _
R
VO
_ _
(c) Equivalent circuit during switchoff FIGURE 3.3 Triplelift circuit.
Usually R is in kΩ, f in 10 kHz, and C2 in µF, this ripple is smaller than 1%. 3.2.2
ReLift Circuit
The relift circuit is derived from elementary circuit by adding the parts (L2D3D4D5C3C4). Its circuit diagram and equivalent circuits during switchon and off are shown in Figure 3.2. The voltage across capacitor C1 is charged to Vin. As described in previous section the voltage V1 across capacitor C2 is V1 =
2−k V 1 − k in
The voltage across capacitor C3 is charged to V1. The current flowing through inductor L2 increases with voltage V1 during switchon period kT and decreases with voltage –(VO – 2V1) during switchoff period (1 – k)T. Therefore, the ripple of the inductor current iL2 is © 2003 by CRC Press LLC
1956_C03.fm Page 220 Thursday, August 7, 2003 10:10 PM
∆iL 2 =
V − 2V1 V1 (1 − k )T kT = O L2 L2
(3.7)
2−k 2−k 2 ) Vin V =( 1− k 1 1− k
(3.8)
VO 2−k 2 =( ) Vin 1− k
(3.9)
VO = The voltage transfer gain is
G=
Similarly, the following relations are obtained: ∆iL1 =
Vin kT L1
I L1 =
I in 2−k
∆iL2 =
V1 kT L2
I L2 = (
I 2−k − 1)I O = O 1− k 1− k
Therefore, the variation ratio of current iL1 through inductor L1 is ξ1 =
∆iL1 / 2 k(2 − k )TVin k(1 − k ) 4 R = = 2L1 I in 2(2 − k ) 3 fL1 I L1
(3.10)
The variation ratio of current iL2 through inductor L2 is ξ2 =
∆iL 2 / 2 k(1 − k )TV1 k(1 − k )2 TVO k(1 − k )2 R = = = 2L2 I O 2(2 − k )L2 I O 2(2 − k ) fL2 I L2
(3.11)
and the variation ratio of output voltage vO is ε=
3.2.3
∆vO / 2 1− k = 2 RfC4 VO
(3.12)
TripleLift Circuit
Triplelift circuit is derived from relift circuit by double adding the parts (L2D3D4D5C3C4). Its circuit diagram and equivalent circuits during switchon and off are shown in Figure 3.3. The voltage across capacitor C1 is charged to Vin . As described before the voltage V 1 across capacitor C 2 is 2 V1 = (2 − k 1 − k )Vin , and voltage V2 across capacitor C4 is V2 = (2 − k 1 − k ) Vin . © 2003 by CRC Press LLC
1956_C03.fm Page 221 Thursday, August 7, 2003 10:10 PM
The voltage across capacitor C5 is charged to V2. The current flowing through inductor L3 increases with voltage V2 during switchon period kT and decreases with voltage –(VO – 2V2) during switchoff (1 – k)T. Therefore, the ripple of the inductor current iL2 is V − 2V2 V2 kT = O (1 − k )T L3 L3
(3.13)
2−k 2−k 2 2−k 3 ) V1 = ( ) Vin V =( 1− k 2 1− k 1− k
(3.14)
∆iL 3 =
VO =
The voltage transfer gain is G=
VO 2−k 3 =( ) Vin 1− k
∆iL1 =
Vin kT L1
I L1 =
I in 2−k
∆iL2 =
V1 kT L2
I L2 =
2−k I (1 − k )2 O
∆iL3 =
V2 kT L3
I L3 =
IO 1− k
(3.15)
Analogously,
Therefore, the variation ratio of current iL1 through inductor L1 is ξ1 =
∆iL1 / 2 k(2 − k )TVin k(1 − k )6 R = = 2L1 I in 2(2 − k ) 5 fL1 I L1
(3.16)
The variation ratio of current iL2 through inductor L2 is ξ2 =
∆iL 2 / 2 k(1 − k ) 2 TV1 kT (2 − k ) 4 VO k(2 − k ) 4 R = = = 2(2 − k )L2 I O 2(1 − k ) 3 L2 I O 2(1 − k ) 3 fL2 I L2
(3.17)
The variation ratio of current iL3 through inductor L3 is ξ3 =
∆iL 3 / 2 k(1 − k )TV2 k(1 − k )2 TVO k(1 − k )2 R = = = 2 L3 I O 2(2 − k )L2 I O 2(2 − k ) fL3 I L3
© 2003 by CRC Press LLC
(3.18)
1956_C03.fm Page 222 Thursday, August 7, 2003 10:10 PM
and the variation ratio of output voltage vO is ε=
3.2.4
∆vO / 2 1− k = 2 RfC6 VO
(3.19)
Higher Order Lift Circuit
Higher order lift circuit can be designed by just multiple repeating the parts (L2D3D4D5C3C4). For nth order lift circuit, the final output voltage across capacitor C2n is VO = (
2−k n ) Vin 1− k
The voltage transfer gain is G=
VO 2−k n =( ) 1− k Vin
(3.20)
The variation ratio of current iLi through inductor Li (i = 1, 2, 3, …n) is ξi =
∆iLi / 2 k(1 − k )2( n−i +1) R = I Li 2(2 − k )2( n−i )+1 fLi
(3.21)
and the variation ratio of output voltage vO is ε=
3.3
∆vO / 2 1− k = 2 RfC2 n VO
(3.22)
Additional Series
Using two diodes and two capacitors (D11D12C11C12), a circuit called double/ enhance circuit (DEC) can be constructed, which is shown in Figure 3.4, which is same as the Figure 1.22 but with components renumbered. If the input voltage is Vin, the output voltage VO can be 2Vin, or other value that is higher than Vin. The DEC is very versatile to enhance DC/DC converter’s voltage transfer gain. All circuits of positive output superlift Luoconvertersadditional series are derived from the corresponding circuits of the main series by adding a DEC. The first three stages of this series are shown in Figure 3.5 to Figure 3.7. © 2003 by CRC Press LLC
1956_C03.fm Page 223 Thursday, August 7, 2003 10:10 PM
Iin
D11
D12 IO + VC11
+ C11
– Vin
R S
+ VC12 –
C12
–
+ VO –
FIGURE 3.4 Double/enhanced circuit (DEC).
For convenience they are called elementary additional circuit, relift additional circuit, and triplelift additional circuit respectively, and numbered as n = 1, 2, and 3.
3.3.1
Elementary Additional Circuit
This circuit is derived from elementary circuit by adding a DEC. Its circuit and switchon and off equivalent circuits are shown in Figure 3.5. The voltage across capacitor C1 is charged to Vin and voltage across capacitor C2 and C11 is charged to V1. The current iL1 flowing through inductor L1 increases with voltage Vin during switchon period kT and decreases with voltage –(VO – 2Vin) during switchoff (1 – k)T. Therefore, V1 =
2−k V 1 − k in
(3.23)
VL1 =
k V 1 − k in
(3.24)
and
The output voltage is VO = Vin + VL1 + V1 =
3−k V 1 − k in
(3.25)
The voltage transfer gain is G= © 2003 by CRC Press LLC
VO 3 − k = Vin 1 − k
(3.26)
1956_C03.fm Page 224 Thursday, August 7, 2003 10:10 PM
Iin
D1
D2
V1 D11
D12 IO
+ VC1
+ L1
C1
+ VC11
C11
–
–
Vin
+ VO
R S
+ VC2 –
C2
–
–
+ VC12 –
C12
(a) Circuit diagram Iin
V1
IO
+ + C11 V1
+ Vin
L1
C1
Vin
C2
+
–
–
+ VC12 R –
C12
V1 –
+ VO –
– (b) Equivalent circuit during switching–on C11 Iin +
IO
L1 – VL1 +
C1
– V1 + V1
– Vin + C2
Vin –
+ V1
C12
+ VC12 –
R
+ VO –
– (c) Equivalent circuit during switching–off
FIGURE 3.5 Elementary additional (enhanced) circuit.
The following relations are derived: iin−off = I L1 = iC11−off + iC1−off =
2IO 1− k
iin−on = iL1−on + iC1−on = I L1 +
IO k
iC1−on =
I 1− k iC1−off = O k k
iC1−off = iC 2−off =
iC 2−off =
I k k = = O i i 1 − k C 2−on 1 − k C11−on 1 − k
iC11−on =
I 1− k = O i k C11−off k
iC12−off =
kI k iC12−on = O 1− k 1− k
iC11−off = I O + iC12−off = I O + © 2003 by CRC Press LLC
I k iC12−on = O 1− k 1− k
IO 1− k
1956_C03.fm Page 225 Thursday, August 7, 2003 10:10 PM
I In
D1
V1
D2
D5 V2 D11
D4
D12
IO +
L1
+
C1
+
L2
VC1
Vin
C3
+
VC3
_
C11
VC11
_
+
_
R
_
D3
+
C2
S
+
C4
V_C2
VO
+
VC4
C12
_
_
VC12
_
(a) Circuit diagram
I in V1 +
+
C1
Vin
L1
_
+
C2 Vin
L2 V1
_
IO
V2 C3
+
+
C4
V1
_
+
C11 V2
+
+
VC12 _
VO
R
_
_
_
C12
V2
_
(b) Equivalent circuit during switching–on C11
I in
L1 _
+
Vin
L2
V1
C1
V1 +
Vin
C2
_
V2
IO
+
V2
_
+
_
C3 +
+
+
V1
V2
_
_
C12 C4
+
VC12 R
VO
_
(c) Equivalent circuit during switching–off FIGURE 3.6 Relift additional circuit.
If inductance L1 is large enough, iL1 is nearly equal to its average current IL1. Therefore, iin−off = I L1 =
2IO 1− k
iin−on = I L1 +
IO 2 1 1+ k =( + )I = I k 1 − k k O k(1 − k ) O
Verification: I in = kiin−on + (1 − k )iin−off = (
1+ k 3−k + 2) I O = I 1− k 1− k O
Considering Vin 1 − k 2 VO 1− k 2 =( =( ) ) R I in 2 − k IO 2−k © 2003 by CRC Press LLC
1956_C03.fm Page 226 Thursday, August 7, 2003 10:10 PM
Iin
D1
D2 V1 + VC1 –
+ L1
C1
D4
L2
D5
V2
+ VC3 –
C3
D7
L3
D8 + VC5 –
C5
D12
D11
C11
IO
+ VC11 –
+
Vin
VO
R D3 C2
–
D6
+ VC2 –
+ V C4 –
C4
+ VC6 –
C6
S
–
+ VC12 –
C12
(a) Circuit diagram Iin
V2
V1
V3
IO
+ C1 Vin
L1
+
+
C2
VC2 L2
Vin
–
–
+
+ C4 V1
C3
C5
VC4 L3 –
–
+ C11 VC6
+ C6 V2
+ C12 V3
–
–
–
+ VC12 R –
+ VO –
–
(b) Equivalent circuit during switchingon C11 Iin
L1
C1
V1
L2
C3
V2
L3 C5
+ – Vin + Vin
– V1 +
+ V1
C2
C4
–
IO
– V3 + V3 +
+ V2
– V1 +
–
C6
+ C12 V3
VC12 R –
+ VO –
–
–
(c) Equivalent circuit during switchingoff
FIGURE 3.7 Triplelift additional circuit.
The variation of current iL1 is ∆iL1 =
kTVin L1
Therefore, the variation ratio of current iL1 through inductor L1 is ξ1 =
∆iL1 / 2 k(1 − k )TVin k(1 − k )2 R = = 4L1 I O 4(3 − k ) fL1 I L1
The ripple voltage of output voltage vO is ∆vO = © 2003 by CRC Press LLC
∆Q I O (1 − k )T 1 − k VO = = C12 C12 fC12 R
(3.27)
1956_C03.fm Page 227 Thursday, August 7, 2003 10:10 PM
Therefore, the variation ratio of output voltage vO is ∆vO / 2 1− k = 2 RfC12 VO
ε=
3.3.2
(3.28)
ReLift Additional Circuit
This circuit is derived from the relift circuit by adding a DEC. Its circuit diagram and switchon and switchoff equivalent circuits are shown in Figure 3.6. The voltage across capacitor C1 is charged to Vin. As described in previous section the voltage across C2 is V1 =
2−k V 1 − k in
The voltage across capacitor C3 is charged to V1 and voltage across capacitor C4 and C11 is charged to V2. The current flowing through inductor L2 increases with voltage V1 during switchon period kT and decreases with voltage –(VO – 2V1) during switchoff (1 – k)T. Therefore, V2 =
2−k 2−k 2 V1 = ( ) Vin 1− k 1− k
(3.29)
k V 1− k 1
(3.30)
and VL2 = The output voltage is VO = V1 + VL 2 + V2 =
2−k 3−k V 1 − k 1 − k in
(3.31)
The voltage transfer gain is G=
VO 2 − k 3 − k = Vin 1 − k 1 − k
∆iL1 =
Vin kT L1
I L1 =
3−k I (1 − k )2 O
∆iL2 =
V1 kT L2
I L2 =
2IO 1− k
(3.32)
Analogously,
© 2003 by CRC Press LLC
1956_C03.fm Page 228 Thursday, August 7, 2003 10:10 PM
Therefore, the variation ratio of current iL1 through inductor L1 is ξ1 =
∆iL1 / 2 k(1 − k )2 TVin k(1 − k ) 4 R = = 2 2(3 − k )L1 I O 2(2 − k )( 3 − k ) fL1 I L1
(3.33)
and the variation ratio of current iL2 through inductor L2 is ξ2 =
∆iL 2 / 2 k(1 − k )TV1 k(1 − k )2 R = = 4L2 I O 4(3 − k ) fL2 I L2
(3.34)
The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C12 C12 fC12 R
Therefore, the variation ratio of output voltage vO is ε=
3.3.3
∆vO / 2 1− k = 2 RfC12 VO
(3.35)
TripleLift Additional Circuit
This circuit is derived from the triplelift circuit by adding a DEC. Its circuit diagram and equivalent circuits during switchon and off are shown in Figure 3.7. The voltage across capacitor C1 is charged to Vin. As described in previous section the voltage across C2 is V1 =
2−k V 1 − k in
and voltage across C4 is V2 =
2−k 2−k 2 V1 = ( ) Vin 1− k 1− k
The voltage across capacitor C5 is charged to V2 and voltage across capacitor C6 and C11 is charged to V3. The current flowing through inductor L3 increases with voltage V2 during switchon period kT and decreases with voltage –(VO – 2V2) during switchoff (1 – k)T. Therefore, V3 = © 2003 by CRC Press LLC
2−k 2−k 2 2−k 3 V2 = ( ) V1 = ( ) Vin 1− k 1− k 1− k
(3.36)
1956_C03.fm Page 229 Thursday, August 7, 2003 10:10 PM
and VL3 =
k V 1− k 2
(3.37)
The output voltage is VO = V2 + VL 3 + V3 = (
2−k 2 3−k ) V 1 − k 1 − k in
(3.38)
The voltage transfer gain is G=
VO 2−k 2 3−k =( ) 1− k 1− k Vin
(3.39)
Analogously, ∆iL1 =
Vin kT L1
I L1 =
(2 − k )( 3 − k ) IO (1 − k ) 3
∆iL2 =
V1 kT L2
I L2 =
3−k I (1 − k )2 O
∆iL3 =
V2 kT L3
I L3 =
2IO 1− k
Considering Vin 1 − k 2 VO 1− k 2 =( =( ) ) R I in 2 − k IO 2−k the variation ratio of current iL1 through inductor L1 is ξ1 =
k(1 − k )3 TVin ∆iL1 / 2 = 2(2 − k )(3 − k )L1IO I L1
(1 − k )3 k(1 − k )3 T R k(1 − k )6 = VO = 2 2(2 − k )(3 − k )L1IO (2 − k ) ( 3 − k ) 2(2 − k )3 ( 3 − k )2 fL1 and the variation ratio of current iL2 through inductor L2 is © 2003 by CRC Press LLC
(3.40)
1956_C03.fm Page 230 Thursday, August 7, 2003 10:10 PM
ξ2 =
∆iL 2 / 2 k(1 − k )2 TV1 = IL2 2(3 − k )L2 IO
k(1 − k )2 T k(1 − k )4 R (1 − k )2 VO = = 2(3 − k )L2 IO (2 − k )(3 − k ) 2(2 − k )(3 − k )2 fL2
(3.41)
and the variation ratio of current iL3 through inductor L3 is ξ3 =
∆iL 3 / 2 k(1 − k )TV2 k(1 − k )T 1 − k k(1 − k )2 R = = VO = 4 L3 I O 4 L3 I O 3 − k 4(3 − k ) fL3 I L3
(3.42)
The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C12 C12 fC12 R
Therefore, the variation ratio of output voltage vO is ε=
3.3.4
∆vO / 2 1− k = 2 RfC12 VO
(3.43)
Higher Order Lift Additional Circuit
The higher order lift additional circuit is derived from the corresponding circuit of the main series by adding a DEC. For nth order lift additional circuit, the final output voltage is VO = (
2 − k n −1 3 − k ) V 1− k 1 − k in
The voltage transfer gain is G=
VO 2 − k n −1 3 − k =( ) 1− k 1− k Vin
(3.44)
Analogously, the variation ratio of current iLi through inductor Li (i = 1, 2, 3, …n) is ξi =
∆iLi / 2 k(1 − k )2( n−i +1) R = 2 ( n − i ) +1 2 u( n− i −1) h ( n− i ) I Li fLi 2[2(2 − k )] (2 − k ) (3 − k )
© 2003 by CRC Press LLC
(3.45)
1956_C03.fm Page 231 Thursday, August 7, 2003 10:10 PM
where x>0 is the Hong function x≤0
0 h( x) = 1 and 1 u( x) = 0
x≥0 is the unitstep function x0 x≤0
is the Hong function
and 1 u( x) = 0
x≥0 x0 x≤0
is the Hong function
and 1 u( x) = 0
x≥0 x0 x≤0
is the Hong function
(3.108)
1956_C03.fm Page 254 Thursday, August 7, 2003 10:10 PM
and x≥0 x> 0V 9.980ms V(R:2)
9.984ms V(D2:2) V(D5:2)
9.988ms
9.992ms
9.996ms
10.000ms
Time
FIGURE 3.17 The simulation results of triplelift circuit at condition k = 0.5 and f = 100 kHz.
3.8
Simulation Results
To verify the design and calculation results, the PSpice simulation package was applied to these converters. Choosing Vin = 20 V, L1 = L2 = L3 = 10 mH, all C1 to C8 = 2 µF, and R = 30 kΩ, and using k = 0.5 and f = 100 kHz. 3.8.1
Simulation Results of a TripleLift Circuit
The voltage values V1, V2 and VO of a triplelift circuit are 66 V, 194 V, and 659 V respectively and inductor current waveforms are iL1 (its average value IL1 = 618 mA), iL2, and iL3. The simulation results are shown in Figure 3.17. The voltage values are matched to the calculated results.
3.8.2
Simulation Results of a TripleLift Additional Circuit
The voltage values V1, V2, V3, and VO of the triplelift additional circuit are 57 V, 165 V, 538 V, and 910 V respectively and current waveforms are iL1 (its average value IL1 = 1.8 A), iL2, and iL3. The simulation results are shown in Figure 3.18. The voltage values are matched to the calculated results. © 2003 by CRC Press LLC
1956_C03.fm Page 259 Thursday, August 7, 2003 10:10 PM
2.0A (19.988m, 1.8) (19.988m, 623m) 1.0A
(19.988m, 248m)
0A I(L1)
I(L2)
I(L3)
1.0KV (19.988m, 910) (19.988m, 538) 0.5KV
(19.988m, 165) (19.988m, 57)
SEL>> 0V 19.980ms V(D8:2)
19.984ms V(R:2) V(D2:2)
19.988ms V(D5:2)
19.992ms
19.996ms
20.000ms
Time
FIGURE 3.18 Simulation results of triplelift additional circuit at condition k = 0.5 and f = 100 kHz.
3.9
Experimental Results
A test rig was constructed to verify the design and calculation results, and compare with PSpice simulation results. The testing conditions were the same: Vin = 20 V, L1 = L2 = L3 = 10 mH, all C1 to C8 = 2 µF and R = 30 kΩ, and using k = 0.5 and f = 100 kHz. The component of the switch is a MOSFET device IRF950 with the rates 950 V/5 A/2 MHz. The values of the output voltage and first inductor current are measured in the following converters.
3.9.1
Experimental Results of a TripleLift Circuit
After careful measurement, the current value of IL1 = 0.62 A (shown in channel 1 with 1 A/Div) and voltage value of VO = 660 V (shown in channel 2 with 200 V/Div). The experimental results (current and voltage values) are shown in Figure 3.19, that are identically matched to the calculated and simulation results, which are IL1 = 0.618 A and VO = 659 V shown in Figure 3.17.
3.9.2
Experimental Results of a TripleLift Additional Circuit
The experimental results of the current value of IL1 = 1.8 A (shown in channel 1 with 1 A/Div) and voltage value of VO = 910 V (shown in channel 2 with © 2003 by CRC Press LLC
1956_C03.fm Page 260 Thursday, August 7, 2003 10:10 PM
FIGURE 3.19 The experimental results of triplelift circuit at condition k = 0.5 and f = 100 kHz.
TABLE 3.4 Comparison of Simulation and Experimental Results of a TripleLift Circuit Stage No. (n) Simulation results Experimental results
IL1 (A)
Iin (A)
Vin (V)
Pin (W)
VO (V)
PO (W)
η (%)
0.618 0.62
0.927 0.93
20 20
18.54 18.6
659 660
14.47 14.52
78 78
TABLE 3.5 Comparison of Simulation and Experimental Results of a TripleLift Additional Circuit Stage No. (n) Simulation results Experimental results
IL1 (A)
Iin (A)
Vin (V)
Pin (W)
VO (V)
PO (W)
η (%)
1.8 1.8
2.7 2.7
20 20
54 54
910 910
27.6 27.6
51 51
200 V/Div) are shown in Figure 3.20 that are identically matched to the calculated and simulation results, which are IL1 = 1.8 A and VO = 910 V shown in Figure 3.18.
3.9.3 Efficiency Comparison of Simulation and Experimental Results These circuits enhanced the voltage transfer gain successfully, but efficiency, particularly, the efficiencies of the tested circuits is 51 to 78%, which is good for high voltage output equipment. Comparison of the simulation and experimental results, which are listed in the Tables 3.4 and 3.5, demonstrates that all results are well identified each other. © 2003 by CRC Press LLC
1956_C03.fm Page 261 Thursday, August 7, 2003 10:10 PM
FIGURE 3.20 Experimental results of triplelift additional circuit at condition k = 0.5 and f = 100 kHz.
Usually, there is high inrush current during the initial poweron. Therefore, the voltage across capacitors is quickly changed to certain values. The transient process is very quick in only few milliseconds.
Bibliography Kassakian, J.G., Wolf, HC., Miller, J.M., and Hurton, C.J., Automotive electrical systems, circa 2005, IEEE Spectrum, 8, 22, 1996. Lander, C.W., Power Electronics, McGrawHill, London, 1993. Luo, F.L., Luoconverters, a new series of positivetopositive DCDC stepup converters, Power Supply Technologies and Applications, Xi’an, China, 1, 30, 1998. Luo, F.L., Positive output Luoconverters, the advanced voltage lift technique, Electrical Drives, Tianjin, China, 2, 47, 1999. Luo, F.L. and Ye, H., Positive output superlift Luoconverters, in Proceedings of IEEEPESC’2002, Cairns, Australia, 2002, p. 425. Luo, F.L. and Ye, H., Positive output superlift converters, IEEE Transactions on Power Electronics, 18, 105, 2003. Pelley, B.R., Tryristor Phase Controlled Converters and Cycloconverters, John Wiley, New York, 1971. Pressman, A.I., Switching Power Supply Design, 2nd ed., McGrawHill, New York, 1998. Rashid, M.H., Power Electronics, 2nd ed., Prentice Hall of India Pvt. Ltd., New Delhi, 1995. Trzynadlowski, A.M., Introduction to Modern Power Electronics, Wiley Interscience, New York, 1998. Ye, H., Luo, F.L., and Ye, Z.Z., Widely adjustable highefficiency high voltage regulated power supply, Power Supply Technologies and Applications, Xi’an, China, 1, 18, 1998. Ye, H., Luo, F.L., and Ye, Z.Z., DC motor Luoconverterdriver, Power Supply World, Guangzhou, China, 2000, p. 15. © 2003 by CRC Press LLC
1956_C04.fm Page 263 Thursday, August 7, 2003 10:08 PM
4 Negative Output SuperLift LuoConverters
Along with the positive output superlift Luoconverters, negative output (N/O) superlift Luoconverters have also been developed. They perform superlift technique as well.
4.1
Introduction
Negative output superlift Luoconverters are sorted into several subseries: • Main series — Each circuit of the main series has one switch S, n inductors, 2n capacitors and (3n – 1) diodes. • Additional series — Each circuit of the additional series has one switch S, n inductors, 2(n + 1) capacitors and (3n + 1) diodes. • Enhanced series — Each circuit of the enhanced series has one switch S, n inductors, 4n capacitors and (5n + 1) diodes. • Reenhanced series — Each circuit of the reenhanced series has one switch S, n inductors, 6n capacitors and (7n + 1) diodes. • Multipleenhanced series — Each circuit of the multipleenhanced series has one switch S, n inductors, 2(n + j + 1) capacitors and (3n + 2j + 1) diodes. All analyses in this section are based on the condition of steady state operation with continuous conduction mode (CCM). The conduction duty ratio is k, switch period T = 1/f (f is the switch frequency), the load is resistive load R. The input voltage and current are Vin and Iin, output voltage and current are VO and IO. Assume no power losses during the conversion process, Vin × Iin = VO × IO. The voltage transfer gain is G: G=
VO Vin 263
© 2003 by CRC Press LLC
1956_C04.fm Page 264 Thursday, August 7, 2003 10:08 PM
I in IO
S
+
+
C1
L1
V in
V C1
_
_
–
R D1
VO
_
D2
V C2
C2
+
+
(a) Circuit Diagram
I in
IO _
_
+
+
V in
L1
C1
_
V C2
C2
Vin
VO
R
+
_
+
(b) Swichon C1
+
+
V in _
L1
Vin
V L1
IO _
_
C2
V C2
_
R
VO
+ +
(c) Swichoff FIGURE 4.1 N/O elementary circuit.
4.2
Main Series
The first three stages of negative output superlift Luoconverters — main series — are shown in Figure 4.1 to Figure 4.3. For convenience they are called elementary circuits, relift circuits, and triplelift circuits respectively, and numbered as n = 1, 2 and 3.
4.2.1 Elementary Circuit N/O elementary circuit and its equivalent circuits during switchon and switchoff are shown in Figure 4.1. The voltage across capacitor C1 is charged © 2003 by CRC Press LLC
1956_C04.fm Page 265 Thursday, August 7, 2003 10:08 PM
I in S
IO
D3 +
+
C1
L1
+
L2
V C1 _
V in
C3
V C3
V1
_
_
R
_
D1
D2
_
C2
D4
D5
V C2
VO
_ +
C4
V C4 +
+
(a) Circuit Diagram
I in
V in
L2
+
+
L1
C1
Vin
_
C2
_
V1+Vin
V C4
_
V1
_
IO
+
C3
_
C4
_
VO
R
+
V1
+
+
(b) Swichon
L2
C1
C3
V1 + +
Vin
L1
V
Vin
_
C2 L1
_
IO _ V L2
+ V1+Vin
V1 +
C4
_
_ _ V C4 R +
VO +
(c) Swichoff FIGURE 4.2 N/O relift circuit.
to Vin. The current flowing through inductor L1 increases with slop Vin/L1 during switchon period kT and decreases with slop –(VO – Vin)/L1 during switchoff (1 – k)T. Therefore, the variation of current iL1 is ∆iL1 =
VO = © 2003 by CRC Press LLC
V − Vin Vin (1 − k )T kT = O L1 L1
(4.1)
1 2−k Vin = ( − 1)Vin 1− k 1− k
(4.2)
1956_C04.fm Page 266 Thursday, August 7, 2003 10:08 PM
I in D3
S
D6
IO + +
C1
L1
+
V C1 L2
Vin
+
L3
V C3
C3
C5
_
_
V1
V2
R
_
D1
V C5
_
_
D2
D4
_
C2
D5
_
C4
V C2
D7
D8 C6
V C4
+
+
VO
_
+
V C6 +
(a) Circuit Diagram
L2
I in
+
L3
+
C3
C5
V2+Vin
IO
V1+Vin _
L1
_
Vin
C1
_
_
C2
C4
V C6
V2
_
V1
V1
C6
V2
_
_
+
+
V in
_
VO
R
+
+
+
+
(b) Switchon
C1
V1
C3
L2
V2
L3
C5
V L3
_ + V2+Vin
IO + + V in
_ Vin
L1
C2
_
_
V L2
+
_ V1+Vin
V1 +
C4
_ V2 +
C6
_ _ V C6 +
R
VO +
(c) Switchoff FIGURE 4.3 N/O triplelift circuit.
The voltage transfer gain is G1 =
VO 2 − k = −1 Vin 1 − k
(4.3)
In steadystate, the average charge across capacitor C1 in a period should be zero. The relations are available: kTiC1−on = (1 − k )TiC1−off © 2003 by CRC Press LLC
and
iC1−on =
1− k i k C1−off
1956_C04.fm Page 267 Thursday, August 7, 2003 10:08 PM
This relation is available for all capacitor’s current in switchon and switchoff periods. The input current iin is equal to (iL1 + iC1) during switchon, and zero during switchoff. Capacitor current iC1 is equal to iL1 during switchoff. iin−on = iL1−on + iC1−on
iL1−off = iC1−off = I L1
If inductance L1 is large enough, iL1 is nearly equal to its average current IL1. Therefore, iin−on = iL1−on + iC1−on = iL1−on +
1− k 1− k 1 )I L1 = I L1 iC1−off = (1 + k k k
and I in = kiin−on = I L1
(4.4)
Further iC 2−on = I O
iC 2−off =
I L1 = iC 2−off + I O =
k I 1− k O
k 1 i I +I = 1 − k C 2−on O 1 − k O
Variation ratio of inductor current iL1 is ξ1 =
∆iL1 / 2 k(1 − k )TVin k(1 − k ) R = = 2L1 I O I L1 G1 2 fL1
(4.5)
Usually ξ1 is small (much lower than unity), it means this converter works in the continuous conduction mode (CCM). The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C2 C2 fC2 R
Therefore, the variation ratio of output voltage vO is ε=
© 2003 by CRC Press LLC
∆vO / 2 1− k = 2 RfC2 VO
(4.6)
1956_C04.fm Page 268 Thursday, August 7, 2003 10:08 PM
Usually R is in kΩ, f in 10 kHz, and C2 in µF, this ripple is very small. 4.2.2
N/O ReLift Circuit
N/O relift circuit is derived from N/O elementary circuit by adding the parts (L2D3D4D5C3C4). Its circuit diagram and equivalent circuits during switchon and off are shown in Figure 4.2. The voltage across capacitor C1 is charged to Vin. As described in previous section the voltage V1 across capacitor C2 is V1 =
1 V 1 − k in
The voltage across capacitor C3 is charged to (V1 + Vin). The current flowing through inductor L2 increases with slop (V1 + Vin)/L2 during switchon period kT and decreases with slop –(VO – 2V1 – Vin)/L2 during switchoff (1 – k)T. Therefore, the variation of current iL2 is ∆iL 2 =
V − 2V1 − Vin V1 + Vin (1 − k )T kT = O L2 L2
(4.7)
(2 − k )V1 + Vin 2−k 2 = [( ) − 1]Vin 1− k 1− k
(4.8)
VO =
The voltage transfer gain is G2 =
VO 2−k 2 =( ) −1 1− k Vin
(4.9)
The input current iin is equal to (iL1 + iC1 + iL2 + iC3) during switchon, and zero during switchoff. In steadystate, the following relations are available: iin−on = iL1−on + iC1−on + iL 2−on + iC 3−on iC 4−on = I O
iC 3−off = I L 2 = I O + iC 4−off =
iC 2−on = I L 2 + iC 3−on = © 2003 by CRC Press LLC
IO 1− k
IO I IO + O = 1− k k k(1 − k )
iC 4−off =
k I 1− k O
iC 3−on =
IO k
iC 2−off =
IO (1 − k )2
1956_C04.fm Page 269 Thursday, August 7, 2003 10:08 PM
iC1−off = I L1 = I L 2 + iC 2−off =
IO IO 2−k + = I 1 − k (1 − k )2 (1 − k )2 O
iC1−on =
2−k I k(1 − k ) O
Thus iin−on = iL1−on + iC1−on + iL 2−on + iC 3−on =
1 3 − 2k ( I L1 + I L 2 ) = I k k(1 − k )2 O
Therefore I in = kiin−on =
3 − 2k I (1 − k )2 O
Since ∆iL1 =
Vin kT L1
I L1 =
2−k I (1 − k )2 O
∆iL 2 =
V1 + Vin 2 − k kT kT = V 1 − k L2 in L2
I L2 =
1 I 1− k O
Therefore, the variation ratio of current iL1 through inductor L1 is ξ1 =
kTVin ∆iL1 / 2 k(1 − k )2 R = = 2−k (2 − k )G2 2 fL1 I L1 2L I (1 − k )2 1 O
(4.10)
The variation ratio of current iL2 through inductor L2 is ξ2 =
∆iL 2 / 2 k(2 − k )TVin k(2 − k ) R = = 2L2 I O I L2 G2 2 fL2
(4.11)
The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C4 C4 fC4 R
Therefore, the variation ratio of output voltage vO is ε= © 2003 by CRC Press LLC
∆vO / 2 1− k = 2 RfC4 VO
(4.12)
1956_C04.fm Page 270 Thursday, August 7, 2003 10:08 PM
4.2.3
N/O TripleLift Circuit
N/O triplelift circuit is derived from N/O relift circuit by double adding the parts (L2D3D4D5C3C4). Its circuit diagram and equivalent circuits during switchon and off are shown in Figure 4.3. The voltage across capacitor C1 is charged to Vin. As described in previous section the, voltage V1 across capacitor C2 is V1 = ((2 − k ) (1 − k ) − 1)Vin = (1 1 − k )Vin , and voltage V2 across 2 2 capacitor C4 is V2 = [(2 − k 1 − k ) − 1]Vin = 3 − 2 k (1 − k ) Vin . The voltage across capacitor C5 is charged to (V2 + Vin). The current flowing through inductor L3 increases with slop (V2 + Vin)/L3 during switchon period kT and decreases with slop –(VO – 2V2 – Vin)/L3 during switchoff (1 – k)T. Therefore, the variation of current iL3 is
(
∆iL 3 =
)
V − 2V2 − Vin V2 + Vin (1 − k )T kT = O L3 L3
(4.13)
(2 − k )V2 + Vin 2−k 3 = [( ) − 1]Vin 1− k 1− k
(4.14)
VO =
The voltage transfer gain is G3 =
VO 2−k 3 =( ) −1 1− k Vin
(4.15)
The input current iin is equal to (iL1 + iC1 + iL2 + iC3 + iL3 + iC5) during switchon, and zero during switchoff. In steady state, the following relations are available: iin−on = iL1−on + iC1−on + iL 2−on + iC 3−on + iL 3− on + iC 5− on iC 6−on = I O
iC 5−off = I L 3 = I O + iC 6−off =
iC 4−on = I L 3 + iC 5−on =
IO I IO + O = k(1 − k ) 1− k k
iC 3−off = I L 2 = I L 3 + iC 4−off =
© 2003 by CRC Press LLC
IO 1− k
2−k I (1 − k )2 O
iC 6−off =
k I 1− k O
iC 5−on =
IO k
iC 4−off =
IO (1 − k )2
iC 3−on =
2−k I k(1 − k ) O
1956_C04.fm Page 271 Thursday, August 7, 2003 10:08 PM
iC 2−on = I L 2 + iC 3−on =
2−k I k(1 − k )2 O
iC1−off = I L1 = I L 2 + iC 2−off =
(2 − k )2 I (1 − k ) 3 O
iC 2−off =
2−k I (1 − k ) 3 O
iC1−on =
(2 − k )2 I k(1 − k )2 O
Thus iin−on = iL1−on + iC1−on + iL 2−on + iC 3−on + iL 3−on + iC 5−on =
1 7 − 9k + 3k 2 ( I L1 + I L 2 + I L 3 ) = I k k(1 − k )3 O
Therefore I in = kiin−on =
7 − 9k + 3k 2 2−k 3 I O = [( ) − 1]I O 1− k (1 − k ) 3
Analogously, ∆iL1 =
Vin kT L1
I L1 =
(2 − k )2 I (1 − k ) 3 O
∆iL 2 =
V1 + Vin 2−k kT = kTVin L2 (1 − k )L2
I L2 =
2−k I (1 − k )2 O
∆iL 3 =
V2 + Vin 2 − k 2 kT kT = ( ) V 1 − k L3 in L3
I L3 =
IO 1− k
Therefore, the variation ratio of current iL1 through inductor L1 is ξ1 =
∆iL1 / 2 k(1 − k ) 3 TVin k(1 − k ) 3 R = = 2 2(2 − k ) L1 I O (2 − k )2 G3 2 fL1 I L1
(4.16)
The variation ratio of current iL2 through inductor L2 is ξ2 =
© 2003 by CRC Press LLC
∆iL 2 / 2 k(1 − k )TVin k(1 − k ) R = = 2L2 I O I L2 G3 2 fL2
(4.17)
1956_C04.fm Page 272 Thursday, August 7, 2003 10:08 PM
The variation ratio of current iL3 through inductor L3 is ξ3 =
∆iL 3 / 2 k(2 − k )2 TVin k(2 − k )2 R = = 2(1 − k )L3 I O (1 − k )G3 2 fL3 I L3
(4.18)
The ripple voltage of output voltage vO is ∆Q I O (1 − k )T 1 − k VO = = C6 C6 fC6 R
∆vO =
Therefore, the variation ratio of output voltage vO is ε=
4.2.4
∆vO / 2 1− k = 2 RfC6 VO
(4.19)
N/O Higher Order Lift Circuit
N/O higher order lift circuits can be designed by repeating the parts (L2D3D4D5C3C4) multiple times. For nth order lift circuit, the final output voltage across capacitor C2n is VO = [(
2−k n ) − 1]Vin 1− k
(4.20)
The voltage transfer gain is Gn =
VO 2−k n =( ) −1 Vin 1− k
(4.21)
The variation ratio of current iLi through inductor Li (i = 1, 2, 3, …n) is
© 2003 by CRC Press LLC
ξ1 =
∆iL1 / 2 k(1 − k )n R = I L1 (2 − k )( n−1) Gn 2 fLi
(4.22)
ξ2 =
∆iL 2 / 2 k ( 2 − k )( 3 − n ) R = I L2 (1 − k )( n− 3 ) Gn 2 fLi
(4.23)
ξ3 =
∆iL 3 / 2 k ( 2 − k )( n − i + 2 ) R = I L3 (1 − k )( n−i +1) Gn 2 fL3
(4.24)
1956_C04.fm Page 273 Thursday, August 7, 2003 10:08 PM
The variation ratio of output voltage vO is ε=
4.3
∆vO / 2 1− k = 2 RfC2 n VO
(4.25)
Additional Series
All circuits of negative output superlift Luoconverters — additional series — are derived from the corresponding circuits of the main series by adding a double/enhanced circuit (DEC). The first three stages of this series are shown in Figure 4.4 to Figure 4.6. For convenience they are called elementary additional circuits, relift additional circuit, and triplelift additional circuit respectively, and numbered as n = 1, 2 and 3.
4.3.1
N/O Elementary Additional Circuit
This circuit is derived from the N/O elementary circuit by adding a DEC. Its circuit and switchon and switchoff equivalent circuits are shown in Figure 4.4. The voltage across capacitor C1 is charged to Vin. The voltage across capacitor C2 is charged to V1 and C11 is charged to (V1 + Vin). The current iL1 flowing through inductor L1 increases with slope Vin/L1 during switchon period kT and decreases with slope –(V1 – Vin)/L1 during switchoff (1 – k)T. Therefore, ∆iL1 =
V1 =
Vin V − Vin (1 − k )T kT = 1 L1 L1
(4.26)
1 2−k Vin = ( − 1)Vin 1− k 1− k VL1−off =
k V 1 − k in
The output voltage is VO = Vin + VL1 + V1 =
© 2003 by CRC Press LLC
2 3−k Vin = [ − 1]Vin 1− k 1− k
(4.27)
1956_C04.fm Page 274 Thursday, August 7, 2003 10:08 PM
I in IO
S
+
C1
L1
+
+
V C1
C 11
V C11
_
Vin
_
_
R
_
D1
D 11
D2
D 12
_
V C12
C 12
V C2
C2
VO
_
+
+
+
(a) Circuit Diagram
I in
C 11
Vin
L1
_
_
+
C1
Vin
_
_
V1+Vin
+
IO
V1 _
+
V C12
C 12
V1
C2
+
_
R
+
VO +
(b) Switchon
C11 +
C1 +
+
Vin
L1
Vin
V1
_
C2
IO _
_
VL1
_
_
V1+Vin
C12
V1
_
VC12 +
R
+
VO +
(c) Switchoff FIGURE 4.4 N/O elementary additional (enhanced) circuit.
The voltage transfer gain is G1 =
VO 3 − k = −1 Vin 1 − k
(4.28)
Following relations are obtained: iC12−on = I O © 2003 by CRC Press LLC
iC12−off =
kI O 1− k
1956_C04.fm Page 275 Thursday, August 7, 2003 10:08 PM
I in S
IO
D3 +
L1
+
C1
+
L2
V C1
V in
C3
_
+
C11
V C3
V1
V C11
V2
_
_
_
R
_
D1
D2
D4
_
C2
D5
V C2
_ D11
C4
D12
V C4
+
C 12
V C12
+
+
VO
_
+
(a) Circuit Diagram
C11
I in
_
+
C3
+
V1+Vin
Vin
C1
L1
Vin
_
_
IO _
L2
+
+
V2
V2+Vin
V C12
_
V1
_
C2
_
_
V2 C4
+
C12
VO
R
+
+
V1 +
(b) Switchon C11 C1 +
+
Vin
L1
_
L2
V1 _
Vin C2
V L1
_
V L2
+ V1+Vin _
V1
C4
+
_
+
C3
IO
V2+Vin V2
_ _
_
V2 C12
VC12 R
+
+
VO +
(c) Switchoff FIGURE 4.5 N/O relift additional circuit.
iC11−off = I O + iC12−off =
iC 2−off = iC1−off =
IO 1− k
I L1 = iC1−off + iC11−on =
© 2003 by CRC Press LLC
IO 1− k
iC11−on = iC 2−on =
iC1−on = 2IO 1− k
IO k
IO k
1956_C04.fm Page 276 Thursday, August 7, 2003 10:08 PM
I in D3
S
D6
IO + +
C1
L1
+
V C1 L2
Vin
V C3
C3
C5
_
V1
V2
D2
_
C2
D4
D5 C4
V C2
V C11
_
_
V3 R
_
D1
C11
V C5
_
_
+
+
L3
+
_
D7
D8
_
V C4
C6
V C6
D11
D12
_
C12
+
+
VO +
V C12 +
+
(a) Circuit Diagram C11 _
+
L2
I in
+
V3
V3+Vin
L3
+
C3 C5
V1+Vin
IO
V2+Vin _
_ +
+
Vin
Vin
C1
L1
_
_
C2
_
V2
_
V1 C4
V1
C6
V2
_
_
V3
V C12
+
C12
_
+
+
(b) Switchon C11 V1
C1
+
Vin
V L1 L1
+
L2
_
Vin C2
_
V L2
V1
+
V2
L3
_
V1+Vin C4
+
_
C3
_
V L3
C5 _
+
V2+Vin
V2 +
C6
+
_
IO
V3+Vin V3 _
V3 C12 +
_ _
VC12
R
+
(c) Switchoff FIGURE 4.6 N/O triplelift additional circuit.
iin = I L1 + iC1−on + iC11−on = (
2 1 1 2 + + )I = I 1 − k k k O k(1 − k ) O
Therefore, I in = kiin =
2 3−k IO = [ − 1]I O 1− k 1− k
The variation ratio of current iL1 through inductor L1 is © 2003 by CRC Press LLC
R
VO +
+
VO +
1956_C04.fm Page 277 Thursday, August 7, 2003 10:08 PM
ξ1 =
∆iL1 / 2 k(1 − k )TVin k(1 − k ) R = = 4L1 I O 2G1 2 fL1 I L1
(4.29)
The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C12 C12 fC12 R
Therefore, the variation ratio of output voltage vO is ε=
4.3.2
∆vO / 2 1− k = 2 RfC12 VO
(4.30)
N/O ReLift Additional Circuit
The N/O relift additional circuit is derived from the N/O relift circuit by adding a DEC. Its circuit diagram and switchon and switchoff equivalent circuits are shown in Figure 4.5. The voltage across capacitor C1 is charged to vin. As described in a previous section the voltage across C2 is V1 =
1 V 1 − k in
The voltage across capacitor C3 is charged to (V1 + Vin), voltage across capacitor C4 is charged to V2 and voltage across capacitor C11 is charged to (V2 + Vin). The current flowing through inductor L2 increases with voltage (V1 + Vin) during switchon kT and decreases with voltage –(V2 – 2V1 – Vin) during switchoff (1 – k)T. Therefore, ∆iL 2 =
V2 =
V1 + Vin V − 2V1 − Vin (1 − k )T kT = 2 L2 L2
(4.31)
(2 − k )V1 + Vin 3 − 2k 2−k 2 = = [( ) − 1]Vin 2 1− k 1− k (1 − k )
and VL 2−off = V2 − 2V1 − Vin = The output voltage is © 2003 by CRC Press LLC
k( 2 − k ) V (1 − k )2 in
(4.32)
1956_C04.fm Page 278 Thursday, August 7, 2003 10:08 PM
VO = V2 + Vin + VL 2 + V1 =
5 − 3k 3−k 2−k V =[ − 1]Vin (1 − k )2 in 1− k 1− k
(4.33)
The voltage transfer gain is G2 =
VO 2 − k 3 − k = −1 Vin 1 − k 1 − k
(4.34)
Following relations are obtained: iC12−on = I O
iC12−off =
iC11−off = I O + iC12−off =
iC 4−off = iC 3−off =
IO 1− k
iC11−on = iC 4−on =
IO 1− k
I L 2 = iC11−off + iC 3−off =
iC 2−on = I L 2 + iC 3−on =
kI O 1− k
iC 3−on =
IO k
iC 2−off =
1+ k I (1 − k )2 O
iC1−on =
3−k I k(1 − k ) O
2IO 1− k
1+ k I k(1 − k ) O
I L1 = iC1−off = I L 2 + iC 2−off =
3−k I (1 − k )2 O
iin = I L1 + iC1−on + iC 2−on + iC 4−on = [
3−k 3−k 1+ k 1 5 − 3k + + I + ]I O = 2 (1 − k ) k(1 − k ) k(1 − k ) k k(1 − k )2 O
Therefore, I in = kiin =
5 − 3k 3−k 2−k I =[ − 1]I O (1 − k )2 O 1− k 1− k
Analogously, ∆iL1 = © 2003 by CRC Press LLC
IO k
Vin kT L2
I L1 =
3−k I (1 − k )2 O
1956_C04.fm Page 279 Thursday, August 7, 2003 10:08 PM
∆iL 2 =
V1 + Vin 2−k kT = kTVin L2 (1 − k )L2
I L2 =
2IO 1− k
Therefore, the variation ratio of current iL1 through inductor L1 is ξ1 =
∆iL1 / 2 k(1 − k )2 TVin k(1 − k )2 R = = 2(3 − k )L1 I O (3 − k )G2 2 fL1 I L1
(4.35)
The variation ratio of current iL2 through inductor L2 is ξ2 =
∆iL 2 / 2 k(2 − k )TVin k(2 − k ) R = = 4L2 I O 2G2 2 fL2 I L2
(4.36)
The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C12 C12 fC12 R
Therefore, the variation ratio of output voltage vO is ε=
4.3.3
∆vO / 2 1− k = 2 RfC12 VO
(4.37)
N/O TripleLift Additional Circuit
This circuit is derived from the N/O triplelift circuit by adding a DEC. Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 4.6. The voltage across capacitor C1 is charged to Vin. As described in a previous section the voltage across C2 is V1 =
1 V 1 − k in
and voltage across C4 is V2 =
3 − 2k 3 − 2k V1 = V 1− k (1 − k )2 in
The voltage across capacitor C5 is charged to (V2 + Vin), voltage across capacitor C6 is charged to V3 and voltage across capacitor C11 is charged to (V3 + Vin). The current flowing through inductor L3 increases with voltage © 2003 by CRC Press LLC
1956_C04.fm Page 280 Thursday, August 7, 2003 10:08 PM
(V 2 + Vin ) during switchon period kT and decreases with voltage –(V3 – 2V2 – Vin) during switchoff (1 – k)T. Therefore, ∆iL 3 =
V3 =
V − 2V2 − Vin V2 + Vin (1 − k )T kT = 3 L3 L3
(4.38)
(2 − k )V2 + Vin 7 − 9k + 3k 2 2−k 3 = Vin = [( ) − 1]Vin 3 1− k 1− k (1 − k )
and VL 3−off = V3 − 2V2 − Vin =
k( 2 − k ) 2 V (1 − k ) 3 in
(4.39)
The output voltage is VO = V3 + Vin + VL 3 + V2 =
11 − 13k + 4 k 2 3−k 2−k 2 ( ) − 1]Vin Vin = [ (1 − k ) 3 1− k 1− k
(4.40)
The voltage transfer gain is G3 =
VO 2−k 2 3−k =( ) −1 1− k 1− k Vin
(4.41)
Following relations are available: iC12−on = I O
iC12−off =
iC11−off = I O + iC12−off =
iC 6−off = iC 5−off =
IO 1− k
IO 1− k
I L 3 = iC11−off + iC 5−off =
iC 4−on = I L 3 + iC 5−on = © 2003 by CRC Press LLC
kI O 1− k
iC11−on = iC 6−on =
IO k
iC 5−on =
IO k
iC 4−off =
1+ k I (1 − k )2 O
2IO 1− k
1+ k I k(1 − k ) O
1956_C04.fm Page 281 Thursday, August 7, 2003 10:08 PM
I L 2 = iC 3−off = I L 3 + iC 4−off =
iC 2−on = I L 2 + iC 3−on =
3−k I (1 − k )2 O
3−k I k(1 − k )2 O
I L1 = iC1−off = I L 2 + iC 2−off =
(3 − k )(2 − k ) IO (1 − k ) 3
iC 3−on =
3−k I k(1 − k ) O
iC 2−off =
3−k I (1 − k ) 3 O
iC1−on =
(3 − k )(2 − k ) IO k(1 − k )2
iin = I L1 + iC1−on + iC 2−on + iC 4−on + iC 6−on =[ =
3−k 1+ k 1 (3 − k )(2 − k ) (3 − k )(2 − k ) + + + + ]I O 3 2 2 k(1 − k ) k(1 − k ) k(1 − k ) k (1 − k )
11 − 13k + 4 k 2 IO k(1 − k )3
Therefore, I in = kiin =
11 − 13k + 4 k 2 3−k 2−k 2 IO = [ ( ) − 1]I O 3 (1 − k ) 1− k 1− k
Analogously, ∆iL1 =
Vin kT L2
I L1 =
(2 − k )( 3 − k ) IO (1 − k ) 3
∆iL 2 =
V1 + Vin 2−k kT = kTVin L2 (1 − k )L2
I L2 =
3−k I (1 − k )2 O
∆iL 3 =
V2 + Vin (2 − k )2 kT = kTVin (1 − k )2 L3 L3
I L3 =
2IO 1− k
Therefore, the variation ratio of current iL1 through inductor L1 is ξ1 =
k(1 − k ) 3 TVin ∆iL1 / 2 k(1 − k ) 3 R = = 2(2 − k )(3 − k )L1 I O (2 − k )( 3 − k )G3 2 fL1 I L1
(4.42)
and the variation ratio of current iL2 through inductor L2 is ξ2 =
∆iL 2 / 2 k(1 − k )(2 − k )TV1 k(1 − k )(2 − k ) R = = 2(3 − k )L2 I O (3 − k )G3 2 fL2 I L2
© 2003 by CRC Press LLC
(4.43)
1956_C04.fm Page 282 Thursday, August 7, 2003 10:08 PM
and the variation ratio of current iL3 through inductor L3 is ξ3 =
∆iL 3 / 2 k(2 − k )2 TVin k( 2 − k ) 2 R = = 4(1 − k )L3 I O 2(1 − k )G3 2 fL3 I L3
(4.44)
The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C12 C12 fC12 R
Therefore, the variation ratio of output voltage vO is ε=
4.3.4
∆vO / 2 1− k = 2 RfC12 VO
(4.45)
N/O Higher Order Lift Additional Circuit
Higher order N/O lift additional circuits can be derived from the corresponding circuits of the main series by adding a DEC. Each stage voltage Vi (i = 1, 2, … n) is Vi = [(
2−k i ) − 1]Vin 1− k
(4.46)
This means V1 is the voltage across capacitor C2, V2 is the voltage across capacitor C4 and so on. For nth order lift additional circuit, the final output voltage is 3 − k 2 − k n −1 ( ) − 1]Vin 1− k 1− k
(4.47)
VO 3 − k 2 − k n−1 = ( ) −1 Vin 1 − k 1 − k
(4.48)
VO = [ The voltage transfer gain is Gn =
Analogously, the variation ratio of current iLi through inductor Li (i = 1, 2, 3, …n) is ξ1 = © 2003 by CRC Press LLC
∆iL1 / 2 k(1 − k )n R = h(1−n) I L1 2 [(2 − k )( n−2 ) (3 − k )]u( n−2 ) Gn fL1
(4.49)
1956_C04.fm Page 283 Thursday, August 7, 2003 10:08 PM
ξ2 =
∆iL 2 / 2 k(1 − k )( n−2 ) (2 − k ) R = h ( n− 2 ) I L2 2 (3 − k )( n−2 ) Gn 2 fL2
(4.50)
ξ3 =
∆iL 3 / 2 k(2 − k )( n−1) R = h ( n− 3 ) ( n− 2 ) 2 (1 − k ) I L3 Gn 2 fL3
(4.51)
where 0 h( x) = 1
x>0 is the Hong function x≤0
and 1 u( x) = 0
x≥0 is the unitstep function x>
(9.99m, 639)
9.980ms V(C4:2)
9.985ms V(C2:2)
9.990ms
V(R:2)
9.995ms
10.000ms
Time
FIGURE 4.16 Simulation results of a N/O triplelift circuit at condition k = 0.5 and f = 100 kHz.
2.0A (19.99m, 1.79) (19.99m, 610m) 1.0A
(19.99m, 206m)
0A 0V
I(L1)
I(L2)
I(L3) (19.99m, 38) (19.99m, 146)
0.5KV
(19.99m, 517) (19.99m, 889)
SEL>> 1.0KV 19.980ms V(D6:1)
19.985ms V(D2:1)
V(R:2)
19.990ms
19.995ms
20.000ms
V(C6:2)
Time
FIGURE 4.17 Simulation results of a N/O triplelift additional circuit at condition k = 0.5 and f = 100 kHz.
4.9.2
Experimental Results of a N/O TripleLift Additional Circuit
The experimental results (voltage and current values) are identically matched to the calculated and simulation results as shown in Figure 4.19. The current value of IL1 = 1.78 A (shown in channel 1 with 1 A/Div) and voltage value of VO = –890 V (shown in channel 2 with 200 V/Div) are obtained. The experimental results are identically matched to the calculated and simulation results, which are IL1 = 1.79 A and VO = –889 V shown in Figure 4.17. © 2003 by CRC Press LLC
1956_C04.fm Page 308 Thursday, August 7, 2003 10:08 PM
FIGURE 4.18 Experimental results of a N/O triplelift circuit at condition k = 0.5 and f = 100 kHz.
FIGURE 4.19 Experimental results of a N/O triplelift additional circuit at k = 0.5 and f = 100 kHz.
4.9.3
Efficiency Comparison of Simulation and Experimental Results
These circuits enhanced the voltage transfer gain successfully, but efficiency, particularly the efficiencies of the tested circuits are 51 to 78%, which is good for high voltage output equipment. Comparison of the simulation and experimental results, which are listed in the Table 4.4 and Table 4.5, demonstrates that all results are well identified with each other.
4.9.4
Transient Process and Stability Analysis
Usually, there is high inrush current during the first poweron. Therefore, the voltage across capacitors is quickly changed to certain values. The transient process is very quick lasting only a few milliseconds. © 2003 by CRC Press LLC
1956_C04.fm Page 309 Thursday, August 7, 2003 10:08 PM
TABLE 4.4 Comparison of Simulation and Experimental Results of a N/O TripleLift Circuit Stage No. (n) Simulation results Experimental results
IL1 (A)
Iin (A)
Vin (V)
Pin (W)
VO(V)
PO (W)
η (%)
0.603 0.6
0.871 0.867
20 20
17.42 17.33
639 640
13.61 13.65
78.12 78.75
TABLE 4.5 Comparison of Simulation and Experimental Results of a N/O TripleLift Additional Circuit Stage No. (n) Simulation results Experimental results
IL1 (A)
Iin (A)
Vin (V)
Pin (W)
VO(V)
PO (W)
η (%)
1.79 1.78
2.585 2.571
20 20
51.7 51.4
889 890
26.34 26.4
51 51
Bibliography Baliga, B.J., Modern Power Devices, New York, John Wiley & Sons, 1987. Luo, F.L., Advanced voltage lift technique — negative output Luoconverters, Power Supply Technologies and Applications, Xi’an, China, 3, 112, 1998. Luo, F.L. and Ye, H., Negative output superlift converters, IEEE Transactions on Power Electronics, 18, 268, 2003. Luo, F.L. and Ye, H., Negative output superlift Luoconverters, in Proceedings of IEEEPESC’2003, Acapulco, Mexico, 2003, p. 1361. Mitchell, D.M., DCtoDC Switching Regulator Analysis, New York: McGrawHill, 1988. Ye, H., Luo, F.L., and Ye, Z.Z., Practical circuits of Luoconverters, Power Supply Technologies and Applications, Xi’an, China, 2, 19, 1999.
© 2003 by CRC Press LLC
1956_C05.fm Page 311 Friday, August 8, 2003 12:04 AM
5 Positive Output Cascade Boost Converters
Superlift technique increases the voltage transfer gain in geometric progression. However, these circuits are a bit complex. This chapter introduces a novel approach — the positive output cascade boost converter — that implements the output voltage increasing in geometric progression, but with simpler structure. They also effectively enhance the voltage transfer gain in powerlaw.
5.1
Introduction
In order to sort these converters differently from existing voltagelift (VL) and superlift (SL) converters, these converters are entitled positive output cascade boost converters. There are several subseries: • Main series — Each circuit of the main series has one switch S, n inductors, n capacitors, and (2n – 1) diodes. • Additional series — Each circuit of the additional series has one switch S, n inductors, (n + 2) capacitors, and (2n + 1) diodes. • Double series — Each circuit of the double series has one switch S, n inductors, 3n capacitors, and (3n – 1) diodes. • Triple series — Each circuit of the triple series has one switch S, n inductors, 5n capacitors, and (5n – 1) diodes. • Multiple series — Each multiple series circuit has one switch S and a higher number of capacitors and diodes. In order to concentrate the superlift function, these converters work in the steady state with the condition of continuous conduction mode (CCM). The conduction duty ratio is k, switching frequency is f, switching period is T = 1/f, the load is resistive load R. The input voltage and current are Vin and Iin, output voltage and current are VO and IO. Assume no power losses during the conversion process, Vin × Iin = VO × IO. The voltage transfer gain is G:
© 2003 by CRC Press LLC
1956_C05.fm Page 312 Friday, August 8, 2003 12:04 AM
G=
5.2
VO Vin
Main Series
The first three stages of positive output cascade boost converters — main series — are shown in Figure 5.1 to Figure 5.3. For convenience they are called elementary boost converter, twostage circuit, and threestage circuit respectively, and numbered as n = 1, 2, and 3.
5.2.1
Elementary Boost Circuit
The elementary boost converter is the fundamental boost converter introduced in Chapter 1 (see Figure 1.24). Its circuit diagram and its equivalent circuits during switchon and switchoff are shown in Figure 5.1. The voltage across capacitor C1 is charged to VO. The current iL1 flowing through inductor L1 increases with voltage Vin during switchon period kT and decreases with voltage –(VO – Vin) during switchoff period (1 – k)T. Therefore, the ripple of the inductor current iL1 is ∆iL1 =
V − Vin Vin (1 − k )T kT = O L1 L1
(5.1)
1 V 1 − k in
(5.2)
VO 1 = Vin 1 − k
(5.3)
VO R
(5.4)
VO = The voltage transfer gain is G= The inductor average current is
I L1 = (1 − k )
The variation ratio of current iL1 through inductor L1 is ξ1 = © 2003 by CRC Press LLC
kTVin ∆iL1 / 2 k R = = (1 − k )2L1VO / R 2 fL1 I L1
(5.5)
1956_C05.fm Page 313 Friday, August 8, 2003 12:04 AM
iIN
L1
D1
+ VIN –
+ VC1 –
S
C1 R
iO + VO –
(a) Circuit diagram iIN
L1
+ C1
VIN –
+ VC1 R –
iO + VO –
(b) Switchingon iIN +
L1 iO
VL1
VIN –
C1
+ VC1 –
R
+ VO –
(c) Switchingoff FIGURE 5.1 Elementary boost converter.
Usually ξ1 is small (much lower than unity), which means this converter works in the continuous mode. The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C1 C1 fC1 R
Therefore, the variation ratio of output voltage vO is ε=
∆vO / 2 1− k = 2 RfC1 VO
(5.6)
Usually R is in kΩ, f in 10 kHz, and C1 in µF, the ripple is smaller than 1%. 5.2.2
TwoStage Boost Circuit
The twostage boost circuit is derived from elementary boost converter by adding the parts (L2D2D3C2). Its circuit diagram and equivalent circuits © 2003 by CRC Press LLC
1956_C05.fm Page 314 Friday, August 8, 2003 12:04 AM
iIN
L1
L2
D1 V1
+ VIN –
D2 C1
+ VC1 –
D3
C2
S
+ VC2R –
iO + VO –
(a) Circuit diagram iIN
V1
+ VIN –
+ VC1 L2 C2 –
L1 C1
+ VC2 R –
iO + VO –
(b) Equivalent circuit during switchingon iIN + VIN –
L1
L2
VL1
VL2 + VC1 C2 –
C1
+ VC2 R –
iO + VO –
(c) Equivalent circuit during switchingoff FIGURE 5.2 Twostage boost circuit.
during switchon and switchoff are shown in Figure 5.2. The voltage across capacitor C1 is charged to V1. As described in previous section the voltage V1 across capacitor C1 is V1 =
1 V 1 − k in
The voltage across capacitor C2 is charged to VO. The current flowing through inductor L2 increases with voltage V1 during switchingon period kT and decreases with voltage –(VO – V1) during switchoff period (1 – k)T. Therefore, the ripple of the inductor current iL2 is ∆iL 2 =
V − V1 V1 (1 − k )T kT = O L2 L2
(5.7)
1 1 2 V1 = ( ) Vin 1− k 1− k
(5.8)
VO = The voltage transfer gain is © 2003 by CRC Press LLC
1956_C05.fm Page 315 Friday, August 8, 2003 12:04 AM
G=
VO 1 2 =( ) 1− k Vin
(5.9)
Analogously, ∆iL1 =
Vin kT L1
I L1 =
IO (1 − k )2
∆iL2 =
V1 kT L2
I L2 =
IO 1− k
Therefore, the variation ratio of current iL1 through inductor L1 is ξ1 =
∆iL1 / 2 k(1 − k )2 TVin k(1 − k ) 4 R = = 2L1 I O 2 I L1 fL1
(5.10)
the variation ratio of current iL2 through inductor L2 is ξ2 =
∆iL 2 / 2 k(1 − k )TV1 k(1 − k )2 R = = 2L2 I O 2 I L2 fL2
(5.11)
and the variation ratio of output voltage vO is ε=
5.2.3
∆vO / 2 1− k = 2 RfC2 VO
(5.12)
ThreeStage Boost Circuit
The threestage boost circuit is derived from the twostage boost circuit by double adding the parts (L2D2D3C2). Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 5.3. The voltage across capacitor C1 is charged to V1. As described previously, the voltage V1 across capacitor C1 is V1 =
1 V 1 − k in
and voltage V2 across capacitor C2 is V2 = ( © 2003 by CRC Press LLC
1 2 ) Vin 1− k
1956_C05.fm Page 316 Friday, August 8, 2003 12:04 AM
D3 iIN
L1
L2
D1 V1
+ VIN –
D2 C1
L3
V2
D5
D4
+ VC1 –
iO
+ VC2 –
C2
S
C3
+ R VC3 –
+ VO –
(a) Circuit diagram iIN + VIN –
L1C1
V1
V2
+ VC1 L2C2 –
+ VC2 L3C3 –
+ VC3 R –
iO + VO –
(b) Equivalent circuit during switchingon iIN
L1
V1
+ VIN
V2
L2
VL1
VL2
C1
+ VC1 C2 –
–
L3 VL3 + VC2 C3 –
+ VC3 R –
iO + VO –
(c) Equivalent circuit during switchingoff FIGURE 5.3 Threestage boost circuit.
The voltage across capacitor C3 is charged to VO. The current flowing through inductor L3 increases with voltage V2 during switchingon period kT and decreases with voltage –(VO – V2) during switchoff (1 – k)T. Therefore, the ripple of the inductor current iL3 is V − V2 V2 (1 − k )T kT = O L3 L3
(5.13)
1 1 2 1 3 V2 = ( ) V1 = ( ) Vin 1− k 1− k 1− k
(5.14)
∆iL 3 =
VO =
The voltage transfer gain is G= Analogously, © 2003 by CRC Press LLC
VO 1 3 =( ) 1− k Vin
(5.15)
1956_C05.fm Page 317 Friday, August 8, 2003 12:04 AM
∆iL1 =
Vin kT L1
I L1 =
IO (1 − k ) 3
∆iL2 =
V1 kT L2
I L2 =
IO (1 − k )2
∆iL3 =
V2 kT L3
I L3 =
IO 1− k
Therefore, the variation ratio of current iL1 through inductor L1 is ξ1 =
∆iL1 / 2 k(1 − k ) 3 TVin k(1 − k )6 R = = 2L1 I O 2 I L1 fL1
(5.16)
The variation ratio of current iL2 through inductor L2 is ξ2 =
∆iL 2 / 2 k(1 − k ) 2 TV1 k(1 − k ) 4 R = = 2L2 I O 2 I L2 fL2
(5.17)
The variation ratio of current iL3 through inductor L3 is ξ3 =
∆iL 3 / 2 k(1 − k )TV2 k(1 − k )2 R = = 2 L3 I O 2 I L3 fL3
(5.18)
and the variation ratio of output voltage vO is ε=
5.2.4
∆vO / 2 1− k = 2 RfC3 VO
(5.19)
Higher Stage Boost Circuit
Higher stage boost circuit can be designed by just multiple repeating of the parts (L2D2D3C2). For nth stage boost circuit, the final output voltage across capacitor Cn is VO = ( The voltage transfer gain is © 2003 by CRC Press LLC
1 n ) Vin 1− k
1956_C05.fm Page 318 Friday, August 8, 2003 12:04 AM
G=
VO 1 n =( ) 1− k Vin
(5.20)
the variation ratio of current iLi through inductor Li (i = 1, 2, 3, …n) is ξi =
∆iLi / 2 k(1 − k )2( n−i +1) R = I Li fLi 2
(5.21)
and the variation ratio of output voltage vO is ε=
5.3
∆vO / 2 1− k = 2 RfCn VO
(5.22)
Additional Series
All circuits of positive output cascade boost converters — additional series — are derived from the corresponding circuits of the main series by adding a DEC. The first three stages of this series are shown in Figure 5.4 to Figure 5.6. For convenience they are called elementary additional circuits, twostage additional circuits, and threestage additional circuits respectively, and numbered as n = 1, 2, and 3.
5.3.1
Elementary Boost Additional (Double) Circuit
This elementary boost additional circuit is derived from elementary boost converter by adding a DEC. Its circuit and switchon and switchoff equivalent circuits are shown in Figure 5.4. The voltage across capacitor C1 and C11 is charged to V1 and voltage across capacitor C12 is charged to VO = 2 V1. The current iL1 flowing through inductor L1 increases with voltage Vin during switchingon period kT and decreases with voltage –(V1 – Vin) during switchingoff (1 – k)T. Therefore, ∆iL1 =
Vin V − Vin (1 − k )T kT = 1 L1 L1 V1 =
© 2003 by CRC Press LLC
1 V 1 − k in
(5.23)
1956_C05.fm Page 319 Friday, August 8, 2003 12:04 AM
iIN
L1
+
D1
D11
D12
+ VC1 –
+ VC11 C1 –
C11
iO
VIN
C12
S –
+ R VC12 –
+ VO
+ VC12 R –
+ VO –
–
(a) Circuit diagram iIN
L1
V1 iO
+
C1
VIN –
+ C11 VC1 –
+ C12 VC11 –
(b) Equivalent circuit during switchingon
iIN + VIN
C11
L1 VL1 C1
– + + VC11 VC1 C12
–
–
+ VC12 R –
iO + VO –
(c) Equivalent circuit during switchingoff FIGURE 5.4 Elementary boost additional (double) circuit.
The output voltage is VO = 2V1 =
2 V 1 − k in
(5.24)
The voltage transfer gain is G=
VO 2 = Vin 1 − k
(5.25)
and iin = I L1 =
2 I 1− k O
The variation ratio of current iL1 through inductor L1 is
© 2003 by CRC Press LLC
(5.26)
1956_C05.fm Page 320 Friday, August 8, 2003 12:04 AM
ξ1 =
∆iL1 / 2 k(1 − k )TVin k(1 − k )2 R = = 4L1 I O 8 I L1 fL1
(5.27)
The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C12 C12 fC12 R
Therefore, the variation ratio of output voltage vO is ε=
5.3.2
∆vO / 2 1− k = 2 RfC12 VO
(5.28)
TwoStage Boost Additional Circuit
The twostage additional boost circuit is derived from the twostage boost circuit by adding a DEC. Its circuit diagram and switchon and switchoff equivalent circuits are shown in Figure 5.5. The voltage across capacitor C1 is charged to V1. As described in the previous section the voltage V1 across capacitor C1 is V1 =
1 V 1 − k in
The voltage across capacitor C2 and capacitor C11 is charged to V2 and voltage across capacitor C12 is charged to VO. The current flowing through inductor L2 increases with voltage V1 during switchon period kT and decreases with voltage –(V2 – V1) during switchoff period (1 – k)T. Therefore, the ripple of the inductor current iL2 is ∆iL2 =
V1 V − V1 (1 − k )T kT = 2 L2 L2
(5.29)
1 1 2 V1 = ( ) Vin 1− k 1− k
(5.30)
V2 = The output voltage is
VO = 2V2 =
© 2003 by CRC Press LLC
2 1 2 V1 = 2( ) Vin 1− k 1− k
(5.31)
1956_C05.fm Page 321 Friday, August 8, 2003 12:04 AM
iIN
L1
L2
D1
D3
D11
D12
+ VC11 –
+ D2 VIN
+ VC1 –
C1 –
S
+ VC2 –
C2
iO C11 C12
+
R VC12 –
+ VO –
(a) Circuit diagram iIN
V1
+ VIN
+ L2 VC1 –
C1
L1
V2 C2
+ C11 V2 –
+ C12 VC11 –
+ VC12 R –
iO + VO –
–
(b) Equivalent circuit during switchingon iIN
L1 VL1
+ VIN –
L2
V1
VL2 + VC1 C2 –
C1
V2
C11 –V + C11 + V2 C12 –
+ VC12 R –
iO + VO –
(c) Equivalent circuit during switchingoff FIGURE 5.5 Twostage boost additional circuit.
The voltage transfer gain is G=
VO 1 2 = 2( ) Vin 1− k
∆iL1 =
Vin kT L1
I L1 =
2 I (1 − k )2 O
∆iL2 =
V1 kT L2
I L2 =
2IO 1− k
(5.32)
Analogously,
Therefore, the variation ratio of current iL1 through inductor L1 is
© 2003 by CRC Press LLC
1956_C05.fm Page 322 Friday, August 8, 2003 12:04 AM
∆iL1 / 2 k(1 − k )2 TVin k(1 − k ) 4 R = = 4L1 I O 8 I L1 fL1
ξ1 =
(5.33)
and the variation ratio of current iL2 through inductor L2 is ξ2 =
∆iL 2 / 2 k(1 − k )TV1 k(1 − k )2 R = = 4L2 I O 8 I L2 fL2
(5.34)
The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C12 C12 fC12 R
Therefore, the variation ratio of output voltage vO is ε=
5.3.3
∆vO / 2 1− k = 2 RfC12 VO
(5.35)
ThreeStage Boost Additional Circuit
This circuit is derived from the threestage boost circuit by adding a DEC. Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 5.6. The voltage across capacitor C1 is charged to V1. As described previously the voltage V1 across capacitor C1 is V1 = (1 1 − k )Vin , 2 and voltage V2 across capacitor C2 is V2 = (1 1 − k ) Vin . The voltage across capacitor C3 and capacitor C11 is charged to V3. The voltage across capacitor C12 is charged to VO. The current flowing through inductor L3 increases with voltage V2 during switchon period kT and decreases with voltage –(V3 – V2) during switchoff (1 – k)T. Therefore, ∆iL3 =
V − V2 V2 (1 − k )T kT = 3 L3 L3
(5.36)
and V3 =
1 1 2 1 3 V =( ) V1 = ( ) Vin 1− k 2 1− k 1− k
(5.37)
The output voltage is VO = 2V3 = 2( © 2003 by CRC Press LLC
1 3 ) Vin 1− k
(5.38)
1956_C05.fm Page 323 Friday, August 8, 2003 12:04 AM
D3
I in
L1
D1
L2
V1
L3
V2
D5 V3 D11
D12 +
D4
C11
IO
V C11 _
D2
+
R
Vin
+
+
_
C1
C2
V C1
S
VC2
C3
+
C12
V C3
_
_
+
VC12
_
+
VO _
_
(a) Circuit diagram
I in
V1 +
+
Vin
L1
C1
V2 +
L2
C2
VC1
V3 L3
C2
+
IO C12
C11
+
V2
_
V3
_
_
+
+
VC12
_
VO
R
_ V3
_
_
(b) Equivalent circuit during switchon
I in +
L1
V L1
V in
L2
V1 +
L3
V2
V L2
V1
+
C2
_
V2 _
V L3
C3
C11
V3 _ +
V3 _
V3
IO
+
C12
+
V C12 _
_
+
R
VO _
(b) Equivalent circuit during switchoff FIGURE 5.6 Threestage boost additional circuit.
The voltage transfer gain is G=
VO 1 3 = 2( ) Vin 1− k
∆iL1 =
Vin kT L1
I L1 =
2 I (1 − k ) 3 O
∆iL2 =
V1 kT L2
I L2 =
2 I (1 − k )2 O
∆iL3 =
V2 kT L3
I L3 =
2IO 1− k
(5.39)
Analogously:
© 2003 by CRC Press LLC
1956_C05.fm Page 324 Friday, August 8, 2003 12:04 AM
Therefore, the variation ratio of current iL1 through inductor L1 is ∆iL1 / 2 k(1 − k ) 3 TVin k(1 − k )6 R = = 4L1 I O 8 I L1 fL1
ξ1 =
(5.40)
and the variation ratio of current iL2 through inductor L2 is ∆iL 2 / 2 k(1 − k ) 2 TV1 k(1 − k ) 4 R = = 4L2 I O 8 I L2 fL2
ξ2 =
(5.41)
and the variation ratio of current iL3 through inductor L3 is ξ3 =
∆iL 3 / 2 k(1 − k )TV2 k(1 − k )2 R = = 4 L3 I O 8 I L3 fL3
(5.42)
The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C12 C12 fC12 R
Therefore, the variation ratio of output voltage vO is ε=
5.3.4
∆vO / 2 1− k = 2 RfC12 VO
(5.43)
Higher Stage Boost Additional Circuit
Higher stage boost additional circuits can be designed by repeating the parts (L2D2D3C2) multiple times. For nth stage additional circuit, the final output voltage is VO = 2(
1 n ) Vin 1− k
The voltage transfer gain is G=
VO 1 n = 2( ) Vin 1− k
(5.44)
Analogously, the variation ratio of current iLi through inductor Li (i = 1, 2, 3, …n) is
© 2003 by CRC Press LLC
1956_C05.fm Page 325 Friday, August 8, 2003 12:04 AM
ξi =
∆iLi / 2 k(1 − k )2( n−i +1) R = I Li fLi 8
(5.45)
and the variation ratio of output voltage vO is ε=
5.4
∆vO / 2 1− k = 2 RfC12 VO
(5.46)
Double Series
All circuits of the positive output cascade boost converter — double series — are derived from the corresponding circuits of the main series by adding a DEC in each stage circuit. The first three stages of this series are shown in Figures 5.4, 5.7, and 5.8. For convenience to explain, they are called elementary double circuits, twostage double circuits, and threestage double circuits respectively, and numbered as n = 1, 2, and 3.
5.4.1
Elementary Double Boost Circuit
From the construction principle, the elementary double boost circuit is derived from the elementary boost converter by adding a DEC. Its circuit and switchon and switchoff equivalent circuits are shown in Figure 5.4, which is the same as the elementary boost additional circuit.
5.4.2
TwoStage Double Boost Circuit
The twostage double boost circuit is derived from the twostage boost circuit by adding a DEC in each stage circuit. Its circuit diagram and switchon and switchoff equivalent circuits are shown in Figure 5.7. The voltage across capacitor C1 and capacitor C11 is charged to V1. As described in the previous section, the voltage V1 across capacitor C1 and capacitor C11 is V1 = (1 1 − k )Vin . The voltage across capacitor C12 is charged to 2V1. The current flowing through inductor L2 increases with voltage 2V1 during switchon period kT and decreases with voltage –(V2 – 2V1) during switchoff period (1 – k)T. Therefore, the ripple of the inductor current iL2 is ∆iL2 =
© 2003 by CRC Press LLC
V − 2V1 2V1 kT = 2 (1 − k )T L2 L2
(5.47)
1956_C05.fm Page 326 Friday, August 8, 2003 12:04 AM
I in
L1
D1
V1
D11
L2
D12
D21
D3
D22
+
D2
+
V C11
C11
V in
C21
_
+
_
C1
IO
+
V C12
C12
_
+
VC21 R
+
S
+
V C1
_
C2
+
V C2
C22
_
_
_VC22
VO _
(a) Circuit diagram I in
V1
+
Vin
C1
L1
L2 2V 1
+
V1
V2
+
C12
+ _
_
2V 1
V1
C2
+
+
V2 _
_
C 11
IO
_
C22
+
VO
_
V2
C21
+
VC22
R
_
_
(b) Equivalent circuit during switchon
I in +
L1
C11
V1 _
VL1
V1
+
C1
V C1 _
_
L2
2V 1
C12
_
V L2
+
C21
V2
+
+
VC12
V2
_
C2
_
V2
IO +
C22
+
+
R
VC12
VO
_
V in
_
(c) Equivalent circuit during switchoff FIGURE 5.7 Twostage boost double circuit.
V2 =
2 1 2 V = 2( ) Vin 1− k 1 1− k
(5.48)
The output voltage is VO = 2V2 = (
2 2 ) Vin 1− k
(5.49)
The voltage transfer gain is G=
© 2003 by CRC Press LLC
VO 2 2 =( ) Vin 1− k
(5.50)
1956_C05.fm Page 327 Friday, August 8, 2003 12:04 AM
Analogously, ∆iL1 =
Vin kT L1
I L1 = (
∆iL2 =
V1 kT L2
I L2 =
2 2 ) I 1− k O
2IO 1− k
Therefore, the variation ratio of current iL1 through inductor L1 is ∆iL1 / 2 k(1 − k )2 TVin k(1 − k ) 4 R = = 8L1 I O 16 I L1 fL1
ξ1 =
(5.51)
and the variation ratio of current iL2 through inductor L2 is ξ2 =
∆iL 2 / 2 k(1 − k )TV1 k(1 − k )2 R = = 4L2 I O 8 I L2 fL2
(5.52)
The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C22 C22 fC22 R
Therefore, the variation ratio of output voltage vO is ε=
5.4.3
∆vO / 2 1− k = 2 RfC22 VO
(5.53)
ThreeStage Double Boost Circuit
This circuit is derived from the threestage boost circuit by adding a DEC in each stage circuit. Its circuit diagram and equivalent circuits during switchon and off are shown in Figure 5.8. The voltage across capacitor C1 and capacitor C11 is charged to V1. As described earlier the voltage V1 across capacitor C1 and capacitor C11 is V1 = (1 1 − k )Vin , and voltage V2 across capac2 itor C2 and capacitor C12 is V2 = 2(1 1 − k ) Vin . 2 The voltage across capacitor C22 is 2V2 = (2 1 − k ) Vin . The voltage across capacitor C3 and capacitor C31 is charged to V3. The voltage across capacitor C12 is charged to VO. The current flowing through inductor L3 increases with
© 2003 by CRC Press LLC
L1
D1
V1
D11
D12
L2
2V1
D3
V2 D21
Vin
VC11
C11
C1
C21
D4
_
+
_
VC12
C12
_
D22
C31
_
C2
_
R
C22
_
_
S
+
VC2
IO
VC31
VC21
+
+
VC1
D32 +
+
+
D2
+
D5 V3 D31
C3
_VC22
+
C32
VC3
VC32
_
_
(a) Circuit diagram Iin
V1
+
L1
Vin
C1
+
+
V1 _
_
2V1 +
C12
L2 2V1
V1
C11
V2
C2
+
_
+
V2 _
_
2V2 +
C22
L3 2V2
V2
C21
C3
+
+
V3 _
_
_
IO
V3 C32
_
C31
+
+
VC32
V3
VO
R
_
_
(b) Equivalent circuit during switchon Iin +
Vin
L1
C11
V1 _
VL1 +
C1
_
V C1 _
V1
2V1 +
C12
L2
_
VL2 + VC12 _
C21
V2
C2
+ V2 _
V2
2V2 +
C22
L3
_
VL3 + VC22 _
C3
IO
C31
V3
+ V3 _
V3
+
C32
+
VC32 _
R
+
VO _
(c) Equivalent circuit during switchoff FIGURE 5.8 Threestage boost double circuit.
© 2003 by CRC Press LLC
+
+
VO _
1956_C05.fm Page 328 Friday, August 8, 2003 12:04 AM
L3
2V2
Iin
1956_C05.fm Page 329 Friday, August 8, 2003 12:04 AM
voltage V2 during switchon period kT and decreases with voltage –(V3 – 2V2) during switchoff (1 – k)T. Therefore, ∆iL3 =
V − 2V2 2V2 (1 − k )T kT = 3 L3 L3
(5.54)
and V3 =
2V2 4 V = (1 − k ) (1 − k ) 3 in
(5.55)
The output voltage is VO = 2V3 = (
2 3 ) Vin 1− k
(5.56)
The voltage transfer gain is G=
VO 2 3 =( ) Vin 1− k
(5.57)
Analogously, ∆iL1 =
Vin kT L1
I L1 =
8 I (1 − k ) 3 O
∆iL2 =
V1 kT L2
I L2 =
4 I (1 − k )2 O
∆iL3 =
V2 kT L3
I L3 =
2IO 1− k
Therefore, the variation ratio of current iL1 through inductor L1 is ξ1 =
∆iL1 / 2 k(1 − k ) 3 TVin k(1 − k )6 R = = 16L1 I O 128 fL1 I L1
(5.58)
and the variation ratio of current iL2 through inductor L2 is ξ2 = © 2003 by CRC Press LLC
∆iL 2 / 2 k(1 − k ) 2 TV1 k(1 − k ) 4 R = = 8L2 I O 32 I L2 fL2
(5.59)
1956_C05.fm Page 330 Friday, August 8, 2003 12:04 AM
and the variation ratio of current iL3 through inductor L3 is ξ3 =
∆iL 3 / 2 k(1 − k )TV2 k(1 − k )2 R = = 4 L3 I O 8 I L3 fL3
(5.60)
The ripple voltage of output voltage vO is ∆Q I O (1 − k )T 1 − k VO = = C32 C32 fC32 R
∆vO =
Therefore, the variation ratio of output voltage vO is ε=
5.4.4
∆vO / 2 1− k = 2 RfC32 VO
(5.61)
Higher Stage Double Boost Circuit
The higher stage double boost circuits can be derived from the corresponding main series circuits by adding a DEC in each stage circuit. For nth stage additional circuit, the final output voltage is VO = (
2 n ) Vin 1− k
The voltage transfer gain is G=
VO 2 n =( ) Vin 1− k
(5.62)
Analogously, the variation ratio of current iLi through inductor Li (i = 1, 2, 3, …n) is ξi =
∆iLi / 2 k(1 − k )2( n−i +1) R = I Li fLi 2 ∗ 2 2n
(5.63)
The variation ratio of output voltage vO is ε=
© 2003 by CRC Press LLC
∆vO / 2 1− k = 2 RfCn 2 VO
(5.64)
1956_C05.fm Page 331 Friday, August 8, 2003 12:04 AM
iIN
L1
D1 V1 D11 C1
D12 2V1 D13
C11
D14 iO
C13
C12
VIN
R
C14 S
+ VO –
(a) Circuit Diagram iIN
2V1
V1
+ L1
C1
VIN –
+ C11 + C12 VC1 VC11 – –
+ C13 VC12 –
+ C14 VC13 –
+ VC12 R –
iO + VO –
(b) Equivalent circuit during switchingon
iIN + VIN –
V1
C13 C11
L1 VL1 C1
2V1 –V + + C11 VC1 C12 –
C14 + VC12 –
R
iO + VO –
(c) Equivalent circuit during switchingoff FIGURE 5.9 Cascade boost redouble circuit.
5.5
Triple Series
All circuits of P/O cascade boost converters — triple series — are derived from the corresponding circuits of the double series by adding the DEC twice in each stage circuit. The first three stages of this series are shown in Figure 5.9 to Figure 5.11. For convenience they are called elementary triple boost circuit, twostage triple boost circuit, and threestage triple boost circuit respectively, and numbered as n = 1, 2 and 3.
5.5.1
Elementary Triple Boost Circuit
From the construction principle, the elementary triple boost circuit is derived from the elementary double boost circuit by adding another DEC. Its circuit
© 2003 by CRC Press LLC
1956_C05.fm Page 332 Friday, August 8, 2003 12:04 AM
and switchon and off equivalent circuits are shown in Figure 5.9. The output voltage of first stage boost circuit is V1, V1 = Vin/(1 – k). The voltage across capacitors C1 and C11 is charged to V1 and voltage across capacitors C12 and C13 is charged to VC13 = 2V1. The current iL1 flowing through inductor L1 increases with voltage Vin during switchon period kT and decreases with voltage –(V1 – Vin) during switchoff (1 – k)T. Therefore, ∆iL1 =
Vin V − Vin (1 − k )T kT = 1 L1 L1 V1 =
(5.65)
1 V 1 − k in
The output voltage is VO = VC1 + VC13 = 3V1 =
3 V 1 − k in
(5.66)
The voltage transfer gain is G=
5.5.2
VO 3 = Vin 1 − k
(5.67)
TwoStage Triple Boost Circuit
The twostage triple boost circuit is derived from the twostage double boost circuit by adding another DEC in each stage circuit. Its circuit diagram and switchon and off equivalent circuits are shown in Figure 5.10. As described in the previous section the voltage V1 across capacitors C1 and C11 is V1 = (1 1 − k )Vin . The voltage across capacitor C14 is charged to 3V1. The voltage across capacitors C2 and C21 is charged to V2 and voltage across capacitors C22 and C23 is charged to VC23 = 2V2. The current flowing through inductor L2 increases with voltage 3V1 during switchon period kT, and decreases with voltage –(V2 – 3V1) during switchoff period (1 – k)T. Therefore, the ripple of the inductor current iL2 is ∆iL2 =
V − 3V1 3V1 kT = 2 (1 − k )T L2 L2
V2 =
© 2003 by CRC Press LLC
3 1 2 V1 = 3( ) Vin 1− k 1− k
(5.68)
(5.69)
1956_C05.fm Page 333 Friday, August 8, 2003 12:04 AM
iIN
D1 V1 D11
L1
+
D12 2V1 D13
D14 3V1
D3 V2 D21 D22 2V2 D23
L2
C13
C11
D24 iO
C23
C21
+ VO
R
VIN
D2 C1
–
C12
–
S
C14
C2 C22
C24
(a) Circuit diagram iIN +
V1
2V1
3V1
V2
2V2 iO
L1 C1
VIN
+ C11 + C12 VC1 VC11 – –
+ C13 VC12 –
+ C14 VC13 –
+ VC14 L2 –
C2
+ C21 + C22 VC2 VC21 – –
+ C23 VC22 –
+ C24 VC23 –
+ R VC24 –
–
+ VO –
(b) Equivalent circuit during switchingon C23 V2 C13
V1 iIN + VIN
C11
L1 VL1 C1
–
3V1
L2
VC21
–
– VC13 +
–V + + C11 VC1 C12 –
2V1C14 + VC12 –
+ C2 VC14 –
+ VC2 –
– VC23 + +
2V2 C 24
C21
+ VC
C22
–
+ VC24 R –
iO + VO –
22
(c) Equivalent circuit during switchingoff
FIGURE 5.10 Twostage boost redouble circuit.
The output voltage is VO = VC 2 + VC 23 = 3V2 = (
3 2 ) Vin 1− k
(5.70)
The voltage transfer gain is G= Analogously,
© 2003 by CRC Press LLC
VO 3 2 =( ) Vin 1− k
(5.71)
1956_C05.fm Page 334 Friday, August 8, 2003 12:04 AM
∆iL1 =
Vin kT L1
I L1 = (
∆iL2 =
V1 kT L2
I L2 =
2 2 ) I 1− k O
2IO 1− k
Therefore, the variation ratio of current iL1 through inductor L1 is ∆iL1 / 2 k(1 − k )2 TVin k(1 − k ) 4 R = = 8L1 I O 16 I L1 fL1
ξ1 =
(5.72)
and the variation ratio of current iL2 through inductor L2 is ξ2 =
∆iL 2 / 2 k(1 − k )TV1 k(1 − k )2 R = = 4L2 I O 8 I L2 fL2
(5.73)
The ripple voltage of output voltage vO is ∆Q I O (1 − k )T 1 − k VO = = C22 C22 fC22 R
∆vO =
Therefore, the variation ratio of output voltage vO is ε=
5.5.3
∆vO / 2 1− k = 2 RfC22 VO
(5.74)
ThreeStage Triple Boost Circuit
This circuit is derived from the threestage double boost circuit by adding another DEC in each stage circuit. Its circuit diagram and equivalent circuits during switchon and off are shown in Figure 5.11. As described earlier the voltage V2 across capacitors C2 and C11 is V2 = 3V1 = (3 1 − k )Vin , and voltage across capacitor C24 is charged to 3V2. The voltage across capacitors C3 and C31 is charged to V3 and voltage across capacitors C32 and C33 is charged to VC33 = 2V3. The current flowing through inductor L3 increases with voltage 3V2 during switchon period kT and decreases with voltage –(V3 – 3V2) during switchoff (1 – k)T. Therefore, the ripple of the inductor current iL3 is ∆iL3 = © 2003 by CRC Press LLC
V − 3V2 3V2 (1 − k )T kT = 3 L3 L3
(5.75)
L1
D1 V1 D11
D12 2V D 1 13
D3
V2 D21 D22 2V2 D23 D24 3V2 L3
C13
C11
+
L2
D14 3V1
D5 V3 D31
D32 2V3 D33
C31
C33
C23
C21
D34 iO R
VIN
D2
–
D4
C14
C12
C1
+ VO
C22
C2
– C3
S
C24
C32
C34
(a) Circuit diagram iIN
V1
+ VIN
C1
2V1 C11
C12
3V1
V2
C14
C13
2V2
C2
C21
3V2
C22
C23
C3
C24
L2
L1
V3
2V3 C31
C32
C33
C34
L3
R
–
(b) Equivalent circuit during switchingon C33 V3 – V + C33 C23
V2
3V2
C21 C13
V1 iIN + VIN
– VC23 + 3V1
L2
C11
L1 VL1 C1
–
– VC13 + 2V1C 14 – + + VC11 + VC1 C12 VC12 – –
– VC21 + C22
+ C2 VC14 –
+ VC2 –
2V2 + VC22 –
C24
– VC31 + 2V3
L3 C31 + VC24 –
C3
(c) Equivalent circuit during switchingoff FIGURE 5.11 Threestage boost redouble circuit.
© 2003 by CRC Press LLC
R
+ VC3 –
+ VC34
C32
C34 + VC32 –
–
iO + VO –
iO + VO –
1956_C05.fm Page 335 Friday, August 8, 2003 12:04 AM
iIN
1956_C05.fm Page 336 Friday, August 8, 2003 12:04 AM
and V3 =
3 1 3 V = 9( ) Vin 1− k 2 1− k
(5.76)
The output voltage is VO = VC 3 + VC 33 = 3V3 = (
3 3 ) Vin 1− k
(5.77)
The voltage transfer gain is G=
VO 3 3 =( ) Vin 1− k
(5.78)
Analogously, ∆iL1 =
Vin kT L1
I L1 =
32 I (1 − k ) 3 O
∆iL2 =
V1 kT L2
I L2 =
8 I (1 − k )2 O
∆iL3 =
V2 kT L3
I L3 =
2 I 1− k O
Therefore, the variation ratio of current iL1 through inductor L1 is ξ1 =
∆iL1 / 2 k(1 − k ) 3 TVin k(1 − k )6 R = = 64L1 I O 12 3 I L1 fL1
(5.79)
and the variation ratio of current iL2 through inductor L2 is ξ2 =
∆iL 2 / 2 k(1 − k ) 2 TV1 k(1 − k ) 4 R = = 16L2 I O 12 2 I L2 fL2
(5.80)
and the variation ratio of current iL3 through inductor L3 is ξ3 = © 2003 by CRC Press LLC
∆iL 3 / 2 k(1 − k )TV2 k(1 − k )2 R = = 4 L3 I O 12 I L3 fL3
(5.81)
1956_C05.fm Page 337 Friday, August 8, 2003 12:04 AM
The ripple voltage of output voltage vO is ∆Q I O (1 − k )T 1 − k VO = = C32 C32 fC32 R
∆vO =
Therefore, the variation ratio of output voltage vO is ε=
5.5.4
∆vO / 2 1− k = 2 RfC32 VO
(5.82)
Higher Stage Triple Boost Circuit
Higher stage triple boost circuits can be derived from the corresponding circuit of double boost series by adding another DEC in each stage circuit. For nth stage additional circuit, the final output voltage is VO = (
3 n ) Vin 1− k
The voltage transfer gain is G=
VO 3 n =( ) Vin 1− k
(5.83)
Analogously, the variation ratio of current iLi through inductor Li (i = 1, 2, 3, …n) is ξi =
∆iLi / 2 k(1 − k )2( n−i +1) R = I Li fLi 12 ( n−i +1)
(5.84)
and the variation ratio of output voltage vO is ε=
5.6
∆vO / 2 1− k = 2 RfCn 2 VO
(5.85)
Multiple Series
All circuits of P/O cascade boost converters — multiple series — are derived from the corresponding circuits of the main series by adding DEC multiple © 2003 by CRC Press LLC
1956_C05.fm Page 338 Friday, August 8, 2003 12:04 AM
1 iIN
L1
D1 V1 D11
+
C1
2...
D12 2V1
C11
j D1(2j–1) D12j (1+j)V1 iO
C1(2j–1)
C12
VIN
R
C12j S
–
+ VO –
(a) Circuit diagram iIN
V1
+ L1
C1
VIN –
2V1
+ C11 + C12 VC1 VC11 – –
+ C13 VC12 –
jV1 C12(j–1)
(j+1)V1
C1(2j–1)
C12j R
iO + VO –
(b) Equivalent circuit during switchingon C1(2j–1)
(1+j)V1
C13 V1 iIN + VIN
C11
L1 VL1 C1
–
– + + VC11 VC1 C12 –
3V1 C12j
2V1 C14 + VC12 –
iO R
+ VO –
(c) Equivalent circuit during switchingoff FIGURE 5.12 Cascade boost multipledouble circuit.
(j) times in each stage circuit. The first three stages of this series are shown in Figure 5.12 to Figure 5.14. For convenience they are called elementary multiple boost circuits, twostage multiple boost circuits, and threestage multiple boost circuits respectively, and numbered as n = 1, 2, and 3.
5.6.1
Elementary Multiple Boost Circuit
From the construction principle, the elementary multiple boost circuit is derived from the elementary boost converter by adding DEC multiple (j) times in the circuit. Its circuit and switchon and off equivalent circuits are shown in Figure 5.12. The voltage across capacitors C1 and C11 is charged to V1 and voltage across capacitors C12 and C13 is charged to VC13 = 2V1. The voltage across capacitors C1(2j2) and C1(2j1) is charged to VC1(2j1) = jV1. The current iL1 flowing through inductor L1 increases with voltage Vin during switchon period kT and decreases with voltage –(V1 – Vin) during switchoff (1 – k)T. Therefore, © 2003 by CRC Press LLC
1956_C05.fm Page 339 Friday, August 8, 2003 12:04 AM
∆iL1 =
Vin V − Vin (1 − k )T kT = 1 L1 L1 V1 =
1 V 1 − k in
(5.86)
(5.87)
The output voltage is VO = VC1 + VC1( 2 j −1) = (1 + j )V1 =
1+ j V 1 − k in
(5.88)
The voltage transfer gain is G=
5.6.2
VO 1 + j = Vin 1 − k
(5.89)
TwoStage Multiple Boost Circuit
The twostage multiple boost circuit is derived from the twostage boost circuit by adding multiple (j) DECs in each stage circuit. Its circuit diagram and switchon and off equivalent circuits are shown in Figure 5.13. The voltage across capacitor C1 and capacitor C11 is charged to V1 = (1 1 − k )Vin . The voltage across capacitor C1(2j) is charged to (1 + j)V1. The current flowing through inductor L2 increases with voltage (1 + j)V1 during switchon period kT and decreases with voltage –[V2 – (1 + j)V1] during switchoff period (1 – k)T. Therefore, the ripple of the inductor current iL2 is ∆iL2 =
V − (1 + j )V1 1+ j kTV1 = 2 (1 − k )T L2 L2
V2 =
1+ j 1 2 V1 = (1 + j )( ) Vin 1− k 1− k
(5.90)
(5.91)
The output voltage is VO = VC1 + VC1( 2 j −1) = (1 + j )V2 = (
1+ j 2 ) Vin 1− k
(5.92)
The voltage transfer gain is G= © 2003 by CRC Press LLC
VO 1+ j 2 =( ) Vin 1− k
(5.93)
1956_C05.fm Page 340 Friday, August 8, 2003 12:04 AM
1 iIN
D1 V1 D11
L1
+
2...
1
j
jV1 (1+)jV1 L2 D1(2j–1) D12j
D12
V2 D3 D21
C1(2j–1)
C11
2...
j jV2 (1+j)V2 D2(2j–1) D22j
D22
iO
C2(2j–1)
C21
VIN
R D2 C1
–
C12
–
S
C12j
+ VO
C2 C22
C24
(a) Circuit diagram iIN + L1
VIN
V1 C1
jV1
+ C11 VC1 –
(1+)jV1
C1(2j–1) C 12j
C12(j–1)
V2 C2
jV2
C21 C22(j–1)
(1+j)V2
C2(2j–1) C 22j
L2
iO + VO –
+ R VC24 –
–
(b) Equivalent circuit during switchingon (1+j)V2 C2(2j–1) C1(2j–1) (1+)jV 1
V1 iIN + VIN
V2 – VC21 +
L2
C11
L1 VL1 C1
–
C22j
C21
– + + VC11 VC1 C12 –
C1 + VC12 –
C2
+ VC2 –
+ VC22 C22
+ VC22j –
iO R
+ VO –
–
(c) Equivalent circuit during switchingoff FIGURE 5.13 Twostage boost multipledouble circuit.
The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C22 j C22 j fC22 j R
Therefore, the variation ratio of output voltage vO is ε=
© 2003 by CRC Press LLC
∆vO / 2 1− k = 2 RfC22 j VO
(5.94)
1956_C05.fm Page 341 Friday, August 8, 2003 12:04 AM
5.6.3
ThreeStage Multiple Boost Circuit
This circuit is derived from the threestage boost circuit by adding multiple (j) DECs in each stage circuit. Its circuit diagram and equivalent circuits during switchon and off are shown in Figure 5.14. The voltage across capacitor C1 and capacitor C11 is charged to V1 = (1 1 − k )Vin . The voltage across capacitor C1(2j) is charged to (1 + j)V1. The voltage V2 across capacitor C2 and capacitor C2(2j) is charged to (1 + j)V2. The current flowing through inductor L3 increases with voltage (1 + j)V2 during switchon period kT and decreases with voltage –[V3 – (1 + j)V2] during switchoff (1 – k)T. Therefore, ∆iL3 =
V − (1 + j )V2 1+ j kTV2 = 3 (1 − k )T L3 L3
(5.95)
and V3 =
(1 + j )V2 (1 + j )2 V = (1 − k ) (1 − k ) 3 in
(5.96)
The output voltage is VO = VC 3 + VC 3( 2 j −1) = (1 + j )V3 = (
1+ j 3 ) Vin 1− k
(5.97)
The voltage transfer gain is G=
VO 1+ j 3 =( ) 1− k Vin
(5.98)
The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C32 j C32 j fC32 j R
Therefore, the variation ratio of output voltage vO is ε=
© 2003 by CRC Press LLC
∆vO / 2 1− k = 2 RfC32 j VO
(5.99)
L1
D1
+
V1
2...jV 1
D11
D12
j
(1+j)V1
D1(2j1)D12j
2... jV2 j
1 L2
D3
C11
V2
D21
D22
C21
D31
j
(1+j)V3 D3(2j1) D32j
D32
iO
C3(2j1) R
D4
C12j
C12
D5
C31
D2
C1
2...jV3
1 V3
L3
C2(2j1)
C1(2j1) VIN
(1+j)V2
D2(2j1)D22j
C3
S
C22j
C22
C2
C32
C32j
(a) Circuit Diagram iIN
V1
+ VIN
C1
jV1
C11 C12(j1) C1(2j1)
(1+j)V1 C12j
jV2
V2 C2
C21
C22(j1)
C2(2j1)
(1+j)V2
L2
L1
V3
C22j
C3
jV3
C31 C32(j1)
C3(2j1)
(1+j)V3 C32j
L3
R

(b) Equivalent circuit during switchingon C3(2j1)
(1+j)V3
V3 C2(2j1) V2 C1(2j1) V1 iIN + VIN
(1+j)V1
L2
VL1 C1

+ + VC11 VC1 C12 
C22 C12j + VC12 
C2
+ VC2 

© 2003 by CRC Press LLC
+
C31 C22j
C3
+ VC22 
(c) Equivalent circuit during switchingoff FIGURE 5.14 Threestage boost multipledouble circuit.
VC31
L3
 VC21 +
C11
L1
(1+j)V2
C21
+ VO
C32j
+ VC3 
C32
+ VC32 
R
iO + VO 
iO + VO 
1956_C05.fm Page 342 Friday, August 8, 2003 12:04 AM
1 iIN
1956_C05.fm Page 343 Friday, August 8, 2003 12:04 AM
5.6.4
Higher Stage Multiple Boost Circuit
Higher stage multiple boost circuit is derived from the corresponding circuit of the main series by adding multiple (j) DECs in each stage circuit. For nth stage additional circuit, the final output voltage is VO = (
1+ j n ) Vin 1− k
The voltage transfer gain is G=
VO 1+ j n =( ) 1− k Vin
(5.100)
Analogously, the variation ratio of output voltage vO is ε=
5.7
∆vO / 2 1− k = 2 RfCn 2 j VO
(5.101)
Summary of Positive Output Cascade Boost Converters
All circuits of the positive output cascade boost converters as a family are shown in Figure 5.15 as the family tree. From the analysis of the previous two sections we have the common formula to calculate the output voltage:
1 n ( 1 − k ) Vin 1 n ) Vin 2 ∗ ( 1− k 2 n VO = ( ) Vin 1− k ( 3 )n Vin 1− k j+1 n ( 1 − k ) Vin The voltage transfer gain is © 2003 by CRC Press LLC
main _ series additional _ series double _ series triple _ series multiple( j ) _ series
(5.102)
1956_C05.fm Page 344 Friday, August 8, 2003 12:04 AM
Main Series
Additional Series
Double Series
Triple Series
Multi Series
5 Stage Boost Circuit
5 Stage Additional Boost Circuit
5 Stage Double Boost Circuit
5 Stage Triple Boost Circuit
5 Stage Multiple Boost Circuit
4 Stage Boost Circuit
4 Stage Additional Boost Circuit
4 Stage Double Boost Circuit
4 Stage Triple Boost Circuit
4 Stage Multiple Boost Circuit
3 Stage Boost Circuit
3 Stage Additional Boost Circuit
3 Stage Double Boost Circuit
3 Stage Triple Boost Circuit
3 Stage Multiple Boost Circuit
2 Stage Boost Circuit
2 Stage Additional Boost Circuit
2 Stage Double Boost Circuit
2 Stage Triple Boost Circuit
2 Stage Multiple Boost Circuit
Elementary Additional/Double Boost Circuit
Elementary Triple Boost Circuit
Elementary Multiple Boost Circuit
Positive Output Elementary Boost Converter
FIGURE 5.15 The family of positive output cascade boost converters
1 n (1 − k ) 1 n ) 2 ∗ ( 1− k V 2 n G= O = ( ) Vin 1 − k ( 3 )n 1− k j+1 n ( 1 − k )
main _ series additional _ series double _ series
(5.103)
triple _ series multiple( j ) _ series
In order to show the advantages of the positive output cascade boost converters, we compare their voltage transfer gains to that of the buck converter, G= © 2003 by CRC Press LLC
VO =k Vin
1956_C05.fm Page 345 Friday, August 8, 2003 12:04 AM
forward converter, G=
VO = kN Vin
G=
VO k = Vin 1 − k
G=
VO k = N Vin 1 − k
G=
VO 1 = Vin 1 − k
N is the transformer turn ratio
Cúkconverter,
flyback converter, N is the transformer turn ratio
boost converter,
and positive output Luoconverters G=
VO n = Vin 1 − k
(5.104)
If we assume that the conduction duty k is 0.2, the output voltage transfer gains are listed in Table 5.1; if the conduction duty k is 0.5, the output voltage transfer gains are listed in Table 5.2; if the conduction duty k is 0.8, the output voltage transfer gains are listed in Table 5.3.
5.8 5.8.1
Simulation and Experimental Results Simulation Results of a ThreeStage Boost Circuit
To verify the design and calculation results, the PSpice simulation package was applied to a threestage boost converter. Choosing Vin = 20 V, L1 = L2 = L3 = 10 mH, all C1 to C8 = 2 µF, and R = 30 kΩ, k = 0.7 and f = 100 kHz. The © 2003 by CRC Press LLC
1956_C05.fm Page 346 Friday, August 8, 2003 12:04 AM
TABLE 5.1 Voltage Transfer Gains of Converters in the Condition k = 0.2 Stage No. (n) Buck converter Forward converter Cúkconverter Flyback converter Boost converter Positive output Luoconverters Positive output cascade boost converters — main series Positive output cascade boost converters — additional series Positive output cascade boost converters — double series Positive output cascade boost converters — triple series Positive output cascade boost (j = 3) converters — multiple series
1
2
1.25 1.25
3
4
5
n
0.2 0.2N (N is the transformer turn ratio) 0.25 0.25N (N is the transformer turn ratio) 1.25 2.5 3.75 5 6.25 1.25n 1.563 1.953 2.441 3.052 1.25n
2.5
3.125
3.906
4.882
6.104
2∗1.25n
2.5
6.25
15.625
39.063
97.66
(2∗1.25)n
3.75
14.06
52.73
197.75
741.58
(3∗1.25)n
5
25
125
625
3125
(4∗1.25)n
TABLE 5.2 Voltage Transfer Gains of Converters in the Condition k = 0.5 Stage No. (n) Buck converter Forward converter Cúkconverter Flyback converter Boost converter Positive output Luoconverters Positive output cascade boost converters main series Positive output cascade boost converters additional series Positive output cascade boost converters double series Positive output cascade boost converters triple series Positive output cascade boost (j = 3) converters — multiple series
1
2
3
4
5
n
—
0.5 0.5N (N is the transformer turn ratio) 1 N (N is the transformer turn ratio) 2 2 4 6 8 10 2n 2 4 8 16 32 2n
—
4
8
16
32
64
—
4
16
64
256
1024
(2∗2)n
—
6
36
216
1296
7776
(3∗2)n
8
64
512
4096
32,768
(4∗2)n
2∗2n
obtained voltage values V1, V2, and VO of a triplelift circuit are 66 V, 194 V, and 659 V respectively and inductor current waveforms iL1 (its average value IL1 = 618 mA), iL2, and iL3. The simulation results are shown in Figure 5.16. The voltage values match the calculated results.
© 2003 by CRC Press LLC
1956_C05.fm Page 347 Friday, August 8, 2003 12:04 AM
TABLE 5.3 Voltage Transfer Gains of Converters in the Condition k = 0.8 Stage No. (n)
1
Buck converter Forward converter Cúkconverter Flyback converter Boost converter Positive output Luoconverters Positive output cascade boost converters — main series Positive output cascade boost converters — additional series Positive output cascade boost converters — double series Positive output cascade boost converters — triple series Positive output cascade boost (j=3) converters — multiple series
5 5
2
3
4
5
n
0.8 0.8N (N is the transformer turn ratio) 4 4N (N is the transformer turn ratio) 5 10 15 20 25 5n 25 125 625 3125 5n 2∗5n
10
50
250
1250
6250
10
100
1000
10,000
100,000
(2∗5)n
15
225
3375
50,625
759,375
(3∗5)n
20
400
8000
160,000
32∗105
(4∗5)n
1.0A
(9.988m, 618m) 0.5A
(9.988m, 218m) (9.988m, 111m)
0A
I(L1)
I(L2)
I(L3)
1.0KV
(9.988m, 659m) (9.988m, 194m) (9.988m, 66m)
0.5KV SEL>> 0V 9.980ms
V(R:2)
9.984ms
V(D2:2)
9.988ms
V(D5:2)
9.992ms
9.996ms
10.000ms
Time
FIGURE 5.16 The simulation results of a threestage boost circuit at condition k = 0.7 and f = 100 kHz.
5.8.2
Experimental Results of a ThreeStage Boost Circuit
A test rig was constructed to verify the design and calculation results, and compared with PSpice simulation results. The test conditions are still Vin = 20 V, L1 = L2 = L3 = 10 mH, all C1 to C8 = 2 µF and R = 30 kΩ, k = 0.7, and f = 100kHz. The component of the switch is a MOSFET device IRF950 with the rate 950 V/5 A/2 MHz. The measured values of the output voltage and © 2003 by CRC Press LLC
1956_C05.fm Page 348 Friday, August 8, 2003 12:04 AM
FIGURE 5.17 The experimental results of a threestage boost circuit at condition k = 0.7 and f = 100 kHz
TABLE 5.4 Comparison of Simulation and Experimental Results of a TripleLift Circuit Stage No. (n) Simulation results Experimental results
IL1 (A)
Iin (A)
Vin (V)
Pin (W)
VO (V)
PO (W)
η (%)
0.618 0.62
0.927 0.93
20 20
18.54 18.6
659 660
14.47 14.52
78 78
first inductor current in a threestage boost converter. After careful measurement, we obtained the current value of IL1 = 0.62 A (shown in channel 1 with 1 A/Div) and voltage value of VO = 660 V (shown in channel 2 with 200 V/ Div). The experimental results (current and voltage values) in Figure 5.17 match the calculated and simulation results, which are IL1 = 0.618 A and VO = 659 V shown in Figure 5.16.
5.8.3
Efficiency Comparison of Simulation and Experimental Results
These circuits enhanced the voltage transfer gain successfully, and efficiently. Particularly, the efficiency of the tested circuits is 78%, which is good for high voltage output equipment. Comparison of the simulation and experimental results is shown in Table 5.4.
5.8.4
Transient Process
Usually, there is high inrush current during the first poweron. Therefore, the voltage across capacitors is quickly changed to certain values. The transient process is very quick taking only a few milliseconds. © 2003 by CRC Press LLC
1956_C05.fm Page 349 Friday, August 8, 2003 12:04 AM
Bibliography Chokhawala, R.S., Catt, J., and Pelly, B.R., Gate drive considerations for IGBT modules, IEEE Trans. on Industry Applications, 31, 603, 1995. Czarkowski, D. and Kazimierczuk, M.K., Phasecontrolled seriesparallel resonant converter, IEEE Trans. on Power Electronics, 8, 309, 1993. Kassakian, J.G., Schlecht, M.F., and Verghese, G.C., Principles of Power Electronics, AddisonWesley, New York, 1991. Khan, I.A., DCtoDC converters for electric and hybrid vehicles, in Proceedings of Power Electronics in Transportation, 1994, p. 113. Luo, F.L. and Ye, H., Positive output cascade boost converters, in Proceedings of IEEEIPEMC’2003, Xi’an, China, 866, 2002. Luo, F.L. and Ye, H., Fundamentals of positive output cascade boost converters, submitted to IEEE Transactions on Power Electronics, 18, 1526, 2003. Luo, F. L. and Ye, H., Development of positive output cascade boost converters, submitted to IEEE Transactions on Power Electronics, 18, 1536, 2003. Poon, N.K. and Pong, M.H., Computer aided design of a crossing current resonant converter (XCRC), in Proceedings of IECON’94, Bologna, Italy, 1994, p. 135. Steigerwald, R.L., Highfrequency resonant transistor DCDC converters, IEEE Trans. on Industrial Electronics, 31, 181, 1984.
© 2003 by CRC Press LLC
1956_C06.fm Page 351 Monday, August 18, 2003 3:24 PM
6 Negative Output Cascade Boost Converters
6.1
Introduction
This chapter introduces negative output cascade boost converters. Just as with positive output cascade boost converters these converters use the superlift technique. There are several subseries: • Main series — Each circuit of the main series has one switch S, n inductors, n capacitors, and (2n – 1) diodes. • Additional series — Each circuit of the additional series has one switch S, n inductors, (n + 2) capacitors, and (2n + 1) diodes. • Double series — Each circuit of the double series has one switch S, n inductors, 3n capacitors, and (3n – 1) diodes. • Triple series — Each circuit of the triple series has one switch S, n inductors, 5n capacitors, and (5n – 1) diodes. • Multiple series — Multiple series circuits have one switch S and a higher number of capacitors and diodes. The conduction duty ratio is k, switching frequency is f, switching period is T = 1/f, the load is resistive load R. The input voltage and current are Vin and Iin, output voltage and current are VO and IO. Assume no power losses during the conversion process, Vin × Iin = VO × IO. The voltage transfer gain is G: G=
6.2
VO Vin
Main Series
The first three stages of the negative output cascade boost converters — main series — are shown in Figure 6.1 to Figure 6.3. For convenience they are 351 © 2003 by CRC Press LLC
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352
Advanced DC/DC Converters
C1 iIN
D1 iO –
S
+ VIN
L1
R
–
VO +
(a) Circuit diagram iIN
C1
+ VIN
L1
+ VC1 – R
iO – VO +
–
(b) Equivalent circuit during switchingon C1
iIN +
iO –
+V – C1
VIN
L1
–
R
VO +
(c) Equivalent circuit during switchingoff FIGURE 6.1 Elementary boost converter.
called elementary boost converter, twostage boost circuit and threestage boost circuit respectively, and numbered as n = 1, 2 and 3.
6.2.1
N/O Elementary Boost Circuit
The N/O elementary boost converter and its equivalent circuits during switchon and off are shown in Figure 6.1. The voltage across capacitor C1 is charged to VC1. The current iL1 flowing through inductor L1 increases with voltage Vin during switchon period kT and decreases with voltage –(VC1 – Vin) during switchoff period (1 – k)T. Therefore, the ripple of the inductor current iL1 is ∆iL1 =
V − Vin Vin (1 − k )T kT = C1 L1 L1 VC1 =
© 2003 by CRC Press LLC
1 V 1 − k in
(6.1)
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Negative Output Cascade Boost Converters
VO = VC1 − Vin =
353 k V 1 − k in
(6.2)
The voltage transfer gain is G=
VO 1 = −1 Vin 1 − k
(6.3)
The inductor average current is I L1 = (1 − k )
VO R
(6.4)
The variation ratio of current iL1 through inductor L1 is ξ1 =
kTVin ∆iL1 / 2 k R = = (1 − k )2L1VO / R 2 fL1 I L1
(6.5)
Usually ξ1 is small (much lower than unity), it means this converter works in the continuous mode. The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C1 C1 fC1 R
Therefore, the variation ratio of output voltage vO is ε=
∆vO / 2 1− k = 2 RfC1 VO
(6.6)
Usually R is in kΩ, f in 10 kHz, and C1 in µF, this ripple is smaller than 1%. 6.2.2
N/O TwoStage Boost Circuit
The N/O twostage boost circuit is derived from elementary boost converter by adding the parts (L2D2D3C2). Its circuit diagram and equivalent circuits during switchon and switch off are shown in Figure 6.2. The voltage across capacitor C1 is charged to V1. As described in the previous section the voltage V1 across capacitor C1 is V1 = © 2003 by CRC Press LLC
1 V 1 − k in
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Advanced DC/DC Converters
iIN
+ C1 –
D1
+ C2 – L2
S
+ VIN
D3
iO –
R
VO +
D2
L1
–
(a) Circuit diagram iIN
C2 +
C1
VIN
L1
+ VC1 + VC2 – R –
L2
–
iO – VO +
(b) Equivalent circuit during switchingon iIN
C2 C1
+
+ V – C2
+V –
VIN
L2
C1
L1 –
R
iO – VO +
(c) Equivalent circuit during switchingoff FIGURE 6.2 Twostage boost circuit.
The voltage across capacitor C2 is charged to VC2. The current flowing through inductor L2 increases with voltage V1 during switchon period kT and decreases with voltage –(VC2 – V1) during switchoff period (1 – k)T. Therefore, the ripple of the inductor current iL2 is ∆iL 2 =
V − V1 V1 (1 − k )T kT = C 2 L2 L2
VC 2 =
1 1 2 V =( ) Vin 1− k 1 1− k
VO = VC 2 − Vin = [( The voltage transfer gain is © 2003 by CRC Press LLC
(6.7)
1 2 ) − 1]Vin 1− k
(6.8)
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Negative Output Cascade Boost Converters
G=
355
VO 1 2 =( ) −1 1− k Vin
(6.9)
Analogously, ∆iL1 =
Vin kT L1
I L1 =
IO (1 − k )2
∆iL2 =
V1 kT L2
I L2 =
IO 1− k
Therefore, the variation ratio of current iL1 through inductor L1 is ∆iL1 / 2 k(1 − k )2 TVin k(1 − k ) 4 R = = 2L1 I O 2 I L1 fL1
ξ1 =
(6.10)
the variation ratio of current iL2 through inductor L2 is ξ2 =
∆iL 2 / 2 k(1 − k )TV1 k(1 − k )2 R = = 2L2 I O 2 I L2 fL2
(6.11)
and the variation ratio of output voltage vO is ε=
6.2.3
∆vO / 2 1− k = 2 RfC2 VO
(6.12)
N/O ThreeStage Boost Circuit
The N/O threestage boost circuit is derived from the twostage boost circuit by double adding the parts (L2D2D3C2). Its circuit diagram and equivalent circuits during switchon and off are shown in Figure 6.3. The voltage across capacitor C1 is charged to V1. As described previously the voltage VC1 across capacitor C1 is VC1 = (1 1 − k )Vin , and voltage VC2 across capacitor C2 is 2 VC 2 = (1 1 − k ) Vin . The voltage across capacitor C3 is charged to VO. The current flowing through inductor L3 increases with voltage VC2 during switchon period kT and decreases with voltage –(VC3 – VC2) during switchoff (1 – k)T. Therefore, the ripple of the inductor current iL3 is ∆iL 3 = © 2003 by CRC Press LLC
VC 2 V − VC 2 (1 − k )T kT = C 3 L3 L3
(6.13)
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Advanced DC/DC Converters
iIN
+ C1 –
D1
+ C2 –
L2
L3 D5
D3
S
+
+ C3 –
D2
VIN
L1
R
D4
–
iO – VO +
(a) Circuit diagram iIN
C3 +
C1
VIN –
L1
C2 + VC1 L 2 –
+ + VC3 – VC2 L 3 R –
iO – VO +
(b) Equivalent circuit during switchingon iIN
C1
+ VC1 C2 –
+ VC2 C3 –
L2
L3
+ VIN –
L1
R
+ VC3 – iO – VO +
(c) Equivalent circuit during switchingoff FIGURE 6.3 Threestage boost circuit.
VC 3 =
1 1 2 1 3 V =( ) VC1 = ( ) Vin 1 − k C2 1− k 1− k
VO = VC 3 − Vin = [(
1 3 ) − 1]Vin 1− k
(6.14)
The voltage transfer gain is G= Analogously, © 2003 by CRC Press LLC
VO 1 3 =( ) −1 Vin 1− k
(6.15)
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Negative Output Cascade Boost Converters
357
∆iL1 =
Vin kT L1
I L1 =
IO (1 − k ) 3
∆iL2 =
V1 kT L2
I L2 =
IO (1 − k )2
∆iL3 =
V2 kT L3
I L3 =
IO 1− k
Therefore, the variation ratio of current iL1 through inductor L1 is ξ1 =
∆iL1 / 2 k(1 − k ) 3 TVin k(1 − k )6 R = = 2L1 I O 2 I L1 fL1
(6.16)
the variation ratio of current iL2 through inductor L2 is ξ2 =
∆iL 2 / 2 k(1 − k ) 2 TV1 k(1 − k ) 4 R = = 2L2 I O 2 I L2 fL2
(6.17)
the variation ratio of current iL3 through inductor L3 is ξ3 =
∆iL 3 / 2 k(1 − k )TV2 k(1 − k )2 R = = 2 L3 I O 2 I L3 fL3
(6.18)
and the variation ratio of output voltage vO is ε=
6.2.4
∆vO / 2 1− k = 2 RfC3 VO
(6.19)
N/O Higher Stage Boost Circuit
N/O higher stage boost circuit can be designed by multiple repetition of the parts (L2D2D3C2). For nth stage boost circuit, the final output voltage across capacitor Cn is VO = [( The voltage transfer gain is © 2003 by CRC Press LLC
1 n ) − 1]Vin 1− k
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Advanced DC/DC Converters
G=
VO 1 n =( ) −1 1− k Vin
(6.20)
the variation ratio of current iLi through inductor Li (i = 1, 2, 3, …n) is ξi =
∆iLi / 2 k(1 − k )2( n−i +1) R = I Li fLi 2
(6.21)
and the variation ratio of output voltage vO is ε=
6.3
∆vO / 2 1− k = 2 RfCn VO
(6.22)
Additional Series
All circuits of negative output cascade boost converters — additional series — are derived from the corresponding circuits of the main series by adding a DEC. The first three stages of this series are shown in Figure 6.4 to Figure 6.6. For convenience they are called elementary additional boost circuit, twostage additional boost circuit, and threestage additional boost circuit respectively, and numbered as n = 1, 2 and 3.
6.3.1
N/O Elementary Additional Boost Circuit
This N/O elementary boost additional circuit is derived from N/O elementary boost converter by adding a DEC. Its circuit and switchon and switchoff equivalent circuits are shown in Figure 6.4. The voltage across capacitor C1 and C11 is charged to VC1 and voltage across capacitor C12 is charged to VC12 = 2VC1. The current iL1 flowing through inductor L1 increases with voltage Vin during switchon period kT and decreases with voltage –(VC1 – Vin) during switchoff (1 – k)T. Therefore, ∆iL1 =
V − Vin Vin (1 − k )T kT = C1 L1 L1 VC1 =
© 2003 by CRC Press LLC
1 V 1 − k in
(6.23)
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Negative Output Cascade Boost Converters
359
C12
C1 iIN
D11
D1
D12 iO – VO
S
+ VIN
C11
L1
R
+
–
(a) Circuit diagram iIN
C12 + L1
VIN
C1 + C11 VC11 –
+ + VC12 – VC11 R –
iO – VO +
–
(b) Equivalent circuit during switchingon iIN
C12 +V
C1 +
+V – C1
VIN
– C11
C12
+ V – C11
L1
R
iO – VO +
–
(c) Equivalent circuit during switchingoff FIGURE 6.4 Elementary boost additional (double) circuit.
The voltage VC12 is VC12 = 2VC1 =
2 V 1 − k in
(6.24)
2 − 1]Vin 1− k
(6.25)
The output voltage is VO = VC12 − Vin = [ The voltage transfer gain is G=
© 2003 by CRC Press LLC
VO 2 = −1 Vin 1 − k
(6.26)
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Advanced DC/DC Converters
The variation ratio of current iL1 through inductor L1 is ξ1 =
∆iL1 / 2 k(1 − k )TVin k(1 − k )2 R = = 4L1 I O 8 I L1 fL1
(6.27)
The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C12 C12 fC12 R
Therefore, the variation ratio of output voltage vO is ε=
6.3.2
∆vO / 2 1− k = 2 RfC12 VO
(6.28)
N/O TwoStage Additional Boost Circuit
The N/O twostage additional boost circuit is derived from the N/O twostage boost circuit by adding a DEC. Its circuit diagram and switchon and switchoff equivalent circuits are shown in Figure 6.5. The voltage across capacitor C1 is charged to VC1. As described in the previous section the voltage VC1 across capacitor C1 is VC1 =
1 V 1 − k in
The voltage across capacitor C2 and capacitor C11 is charged to VC2 and voltage across capacitor C12 is charged to VC12. The current flowing through inductor L2 increases with voltage VC1 during switchon period kT and decreases with voltage –(VC2 – VC1) during switchoff period (1 – k)T. Therefore, the ripple of the inductor current iL2 is ∆iL 2 =
VC1 V − VC1 (1 − k )T kT = C 2 L2 L2
(6.29)
1 1 2 VC1 = ( ) Vin 1− k 1− k
(6.30)
VC 2 =
VC12 = 2VC 2 =
© 2003 by CRC Press LLC
2 1 2 VC1 = 2( ) Vin 1− k 1− k
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Negative Output Cascade Boost Converters
361
C2
C1 iIN
L2
D1
D3
C12
D11
D12 iO –
S
+
D2
VIN
L1
R
C11
–
VO +
(a) Circuit diagram iIN
C12 +
C1
VIN
+ C2 VC1 –
L2
L1
+ C11 VC2 –
+ + VC12 – VC2 R –
–
iO – VO +
(b) Equivalent circuit during switchingon iIN
+
C1
+ VC1 C2 –
+ VC2 C12 – C11
L2
+ VC11 –
VIN L1
–
R
+ VC12 – iO – VO +
(c) Equivalent circuit during switchingoff FIGURE 6.5 Twostage additional boost circuit.
The output voltage is VO = VC12 − Vin = [2(
1 2 ) − 1]Vin 1− k
(6.31)
The voltage transfer gain is G= Analogously,
© 2003 by CRC Press LLC
VO 1 2 = 2( ) −1 Vin 1− k
(6.32)
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362
Advanced DC/DC Converters
∆iL1 =
Vin kT L1
I L1 =
2 I (1 − k )2 O
∆iL2 =
V1 kT L2
I L2 =
2IO 1− k
Therefore, the variation ratio of current iL1 through inductor L1 is ∆iL1 / 2 k(1 − k )2 TVin k(1 − k ) 4 R = = 4L1 I O 8 I L1 fL1
ξ1 =
(6.33)
and the variation ratio of current iL2 through inductor L2 is ξ2 =
∆iL 2 / 2 k(1 − k )TV1 k(1 − k )2 R = = 4L2 I O 8 I L2 fL2
(6.34)
The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C12 C12 fC12 R
Therefore, the variation ratio of output voltage vO is ε=
6.3.3
∆vO / 2 1− k = 2 RfC12 VO
(6.35)
N/O ThreeStage Additional Boost Circuit
This N/O circuit is derived from threestage boost circuit by adding a DEC. Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 6.6. The voltage across capacitor C1 is charged to VC1. As described previously, the voltage V C 1 across capacitor C 1 is 2 VC1 = (1 1 − k )Vin , and voltage V2 across capacitor C2 is VC 2 = (1 1 − k ) Vin . The voltage across capacitor C3 and capacitor C11 is charged to VC3. The voltage across capacitor C12 is charged to VC12. The current flowing through inductor L3 increases with voltage VC2 during switchon period kT and decreases with voltage –(VC3 – VC2) during switchoff (1 – k)T. Therefore, ∆iL 3 = © 2003 by CRC Press LLC
VC 2 V − VC 2 (1 − k )T kT = C 3 L3 L3
(6.36)
1956_C06.fm Page 363 Monday, August 18, 2003 3:24 PM
Negative Output Cascade Boost Converters
363
C1 iIN
+ VIN
C3
C2
L2
D1
L3
D3
D5
C12
D11
D12
S D2 L1
C11
D4
–
R
iO – VO +
(a) Circuit diagram C12
iIN C1
+ VIN L1
C2 + VC1 L – 2
+ C3 VC2 – L3
+ C11 VC3 –
+ + VC12 – VC11 R –
–
iO – VO +
(b) Equivalent circuit during switchingon iIN
+ VC12 –
+ VC1 –
+
+ C1 VC2 –
+ C2 VC3 –
L2
L3
C12 C3 C11
VIN L1
–
+ VC11 – R
iO – VO +
(c) Equivalent circuit during switchingoff FIGURE 6.6 Threestage additional boost circuit.
and VC 3 =
1 1 2 1 3 V =( ) VC1 = ( ) Vin 1 − k C2 1− k 1− k
(6.37)
The voltage VC12 is VC12 = 2VC 3 = 2(
1 3 ) Vin 1− k
The output voltage is VO = VC12 − Vin = [2( © 2003 by CRC Press LLC
1 3 ) − 1]Vin 1− k
(6.38)
1956_C06.fm Page 364 Monday, August 18, 2003 3:24 PM
364
Advanced DC/DC Converters
The voltage transfer gain is G=
VO 1 3 = 2( ) −1 1− k Vin
(6.39)
Analogously, ∆iL1 =
Vin kT L1
I L1 =
2 I (1 − k ) 3 O
∆iL2 =
V1 kT L2
I L2 =
2 I (1 − k )2 O
∆iL3 =
V2 kT L3
I L3 =
2IO 1− k
Therefore, the variation ratio of current iL1 through inductor L1 is ∆iL1 / 2 k(1 − k ) 3 TVin k(1 − k )6 R = = 4L1 I O 8 I L1 fL1
ξ1 =
(6.40)
and the variation ratio of current iL2 through inductor L2 is ∆iL 2 / 2 k(1 − k ) 2 TV1 k(1 − k ) 4 R = = 4L2 I O 8 I L2 fL2
ξ2 =
(6.41)
and the variation ratio of current iL3 through inductor L3 is ξ3 =
∆iL 3 / 2 k(1 − k )TV2 k(1 − k )2 R = = 4 L3 I O 8 I L3 fL3
(6.42)
The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C12 C12 fC12 R
Therefore, the variation ratio of output voltage vO is ε= © 2003 by CRC Press LLC
∆vO / 2 1− k = 2 RfC12 VO
(6.43)
1956_C06.fm Page 365 Monday, August 18, 2003 3:24 PM
Negative Output Cascade Boost Converters 6.3.4
365
N/O Higher Stage Additional Boost Circuit
The N/O higher stage boost additional circuit is derived from the corresponding circuit of the main series by adding a DEC. For the nth stage additional circuit, the final output voltage is VO = [2(
1 n ) −]Vin 1− k
The voltage transfer gain is G=
VO 1 n = 2( ) −1 1− k Vin
(6.44)
Analogously, the variation ratio of current iLi through inductor Li (i = 1, 2, 3, …n) is ξi =
∆iLi / 2 k(1 − k )2( n−i +1) R = I Li fLi 8
(6.45)
and the variation ratio of output voltage vO is ε=
6.4
∆vO / 2 1− k = 2 RfC12 VO
(6.46)
Double Series
All circuits of N/O cascade boost converters — double series — are derived from the corresponding circuits of the main series by adding a DEC in each stage circuit. The first three stages of this series are shown in Figures 6.4, 6.7, and 6.8. For convenience they are called elementary double boost circuit, twostage double boost circuit, and threestage double boost circuit respectively, and numbered as n = 1, 2 and 3.
6.4.1
N/O Elementary Double Boost Circuit
This N/O elementary double boost circuit is derived from the elementary boost converter by adding a DEC. Its circuit and switchon and switchoff equivalent circuits are shown in Figure 6.4, which is the same as the elementary boost additional circuit. © 2003 by CRC Press LLC
1956_C06.fm Page 366 Monday, August 18, 2003 3:24 PM
366
Advanced DC/DC Converters
C1 iIN S
+ VIN
C12
D11
D1
D12
C2
L2
D3
C22 D22
C21
C11 L1
D21
R
D2
–
iO – VO +
(a) Circuit diagram C22
iIN C1
+ VIN L1 –
C + 11 VC1 –
C + 12 VC11 –
C2 + VC12 – L2
+ C21 VC2 –
+ + VC22 – VC21 R –
iO – VO +
(b) Equivalent circuit during switching–on iIN
+ VC22 – + VC1 –
+
+ C1 VC12 C11 –
+ C12 VC2 –
C22 C2 C21
VIN + VC11 –
L2
L1
–
+ VC21 – R
iO – VO +
(c) Equivalent circuit during switching–off FIGURE 6.7 Twostage double boost circuit.
6.4.2
N/O TwoStage Double Boost Circuit
The N/O twostage double boost circuit is derived from twostage boost circuit by adding a DEC in each stage circuit. Its circuit diagram and switchon and switchoff equivalent circuits are shown in Figure 6.7. The voltage across capacitor C1 and capacitor C11 is charged to V1. As described in the previous section the voltage VC1 across capacitor C1 and capacitor C11 is VC1 = (1 1 − k )Vin . The voltage across capacitor C12 is charged to 2VC1. The current flowing through inductor L2 increases with voltage 2VC1 during switchon period kT and decreases with voltage –(VC2 – 2VC1) during switchoff period (1 – k)T. Therefore, the ripple of the inductor current iL2 is ∆iL 2 = © 2003 by CRC Press LLC
V − 2VC1 2VC1 kT = C 2 (1 − k )T L2 L2
(6.47)
1956_C06.fm Page 367 Monday, August 18, 2003 3:24 PM
Negative Output Cascade Boost Converters
VC 2 =
367
2 1 2 V = 2( ) Vin 1 − k C1 1− k
(6.48)
The voltage VC22 is VC 22 = 2VC 2 = (
2 2 ) Vin 1− k
The output voltage is VO = VC 22 − Vin = [(
2 2 ) − 1]Vin 1− k
(6.49)
The voltage transfer gain is G=
VO 2 2 =( ) −1 Vin 1− k
(6.50)
Analogously, ∆iL1 =
Vin kT L1
I L1 = (
∆iL2 =
V1 kT L2
I L2 =
2 2 ) I 1− k O
2IO 1− k
Therefore, the variation ratio of current iL1 through inductor L1 is ∆iL1 / 2 k(1 − k )2 TVin k(1 − k ) 4 R = = 8L1 I O 16 I L1 fL1
ξ1 =
(6.51)
and the variation ratio of current iL2 through inductor L2 is ξ2 =
∆iL 2 / 2 k(1 − k )TV1 k(1 − k )2 R = = 4L2 I O 8 I L2 fL2
The ripple voltage of output voltage vO is ∆vO = © 2003 by CRC Press LLC
∆Q I O (1 − k )T 1 − k VO = = C22 C22 fC22 R
(6.52)
1956_C06.fm Page 368 Monday, August 18, 2003 3:24 PM
368
Advanced DC/DC Converters
C1 iIN
D1
C12
D11
D12
C2
L2
D4
D21
C22 D22
L3
C3 D5
D31
C32 D32
S
+
iO – VO +
C11
VIN
L1
C21
D2
–
R D3
C31
(a) Circuit diagram C32
iIN +
C1
+ C11 VC1 –
VIN L1
+ C12 VC11 –
C2 + VC12 L – 2
+ C21 + C22 VC21 VC2 – –
C3 + VC22 L – 3
+ C31 VC3 –
+ + VC32 – VC31 R –
iO – VO +
–
(b) Equivalent circuit during switchingon iIN
+
+ VC1 –
+ C1 VC12 C11 –
+ C12 VC2 –
+ VC11 –
L2
+ C2 VC22 – C21
+ C22 VC3 –
C32 C3 C31
VIN
–
+ VC21–
L3
L1
+ VC31 R
iO – VO +
(c) Equivalent circuit during switchingoff FIGURE 6.8 Threestage double boost circuit.
Therefore, the variation ratio of output voltage vO is ε=
6.4.3
∆vO / 2 1− k = 2 RfC22 VO
(6.53)
N/O ThreeStage Double Boost Circuit
This N/O circuit is derived from the threestage boost circuit by adding DEC in each stage circuit. Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 6.8. The voltage across capacitor C1 and capacitor C11 is charged to VC1. As described previously, the voltage VC1 across capacitor C1 and capacitor C11 is VC1 = (1 1 − k )Vin , and voltage VC2 across capac2 itor C2 and capacitor C12 is VC 2 = 2(1 1 − k ) Vin . © 2003 by CRC Press LLC
1956_C06.fm Page 369 Monday, August 18, 2003 3:24 PM
Negative Output Cascade Boost Converters
369
The voltage across capacitor C22 is 2VC 2 = (2 1 − k ) Vin . The voltage across capacitor C3 and capacitor C31 is charged to V3. The voltage across capacitor C12 is charged to VO. The current flowing through inductor L3 increases with voltage V 2 during switchon period kT and decreases with voltage –(VC3 – 2VC2) during switchoff (1 – k)T. Therefore, 2
∆iL 3 =
2VC 2 V − 2VC 2 (1 − k )T kT = C 3 L3 L3
(6.54)
2VC 2 4 V = (1 − k ) (1 − k ) 3 in
(6.55)
and VC 3 = The voltage VC32 is VC 32 = 2VC 3 = (
2 3 ) Vin 1− k
The output voltage is VO = VC 32 − Vin = [(
2 3 ) − 1]Vin 1− k
(6.56)
The voltage transfer gain is G=
VO 2 3 =( ) −1 Vin 1− k
Analogously, ∆iL1 =
Vin kT L1
I L1 =
8 I (1 − k ) 3 O
∆iL2 =
V1 kT L2
I L2 =
4 I (1 − k )2 O
∆iL3 =
V2 kT L3
I L3 =
2IO 1− k
Therefore, the variation ratio of current iL1 through inductor L1 is © 2003 by CRC Press LLC
(6.57)
1956_C06.fm Page 370 Monday, August 18, 2003 3:24 PM
370
Advanced DC/DC Converters ∆iL1 / 2 k(1 − k ) 3 TVin k(1 − k )6 R = = 16L1 I O 128 fL1 I L1
ξ1 =
(6.58)
and the variation ratio of current iL2 through inductor L2 is ∆iL 2 / 2 k(1 − k ) 2 TV1 k(1 − k ) 4 R = = 8L2 I O 32 I L2 fL2
ξ2 =
(6.59)
and the variation ratio of current iL3 through inductor L3 is ξ3 =
∆iL 3 / 2 k(1 − k )TV2 k(1 − k )2 R = = 4 L3 I O 8 I L3 fL3
(6.60)
The ripple voltage of output voltage vO is ∆Q I O (1 − k )T 1 − k VO = = C32 C32 fC32 R
∆vO =
Therefore, the variation ratio of output voltage vO is ε=
6.4.4
∆vO / 2 1− k = 2 RfC32 VO
(6.61)
N/O Higher Stage Double Boost Circuit
The N/O higher stage double boost circuit is derived from the corresponding circuit of the main series by adding DEC in each stage circuit. For nth stage additional circuit, the final output voltage is VO = [(
2 n ) − 1]Vin 1− k
The voltage transfer gain is G=
VO 2 n =( ) −1 1− k Vin
(6.62)
Analogously, the variation ratio of current iLi through inductor Li (i = 1, 2, 3, …n) is ξi = © 2003 by CRC Press LLC
∆iLi / 2 k(1 − k )2( n−i +1) R = I Li fLi 2 ∗ 2 2n
(6.63)
1956_C06.fm Page 371 Monday, August 18, 2003 3:24 PM
Negative Output Cascade Boost Converters
371
and the variation ratio of output voltage vO is ε=
6.5
∆vO / 2 1− k = 2 RfCn 2 VO
(6.64)
Triple Series
All circuits of N/O cascade boost converters — triple series — are derived from the corresponding circuits of the main series by adding DEC twice in each stage circuit. The first three stages of this series are shown in Figure 6.9 to Figure 6.11. For convenience they are called elementary triple boost (or additional) circuit, twostage triple boost circuit, and threestage triple boost circuit respectively, and numbered as n = 1, 2 and 3.
6.5.1
N/O Elementary Triple Boost Circuit
This N/O elementary triple boost circuit is derived from the elementary boost converter by adding DEC twice. Its circuit and switchon and switchoff equivalent circuits are shown in Figure 6.9. The output voltage of the first stage boost circuit is VC1, VC1 = Vin/(1 – k). After the first DEC, the voltage (across capacitor C12) increases to VC12 = 2VC1 =
2 V 1 − k in
(6.65)
After the second DEC, the voltage (across capacitor C14) increases to 3 V 1 − k in
(6.66)
3 − 1]Vin 1− k
(6.67)
VC14 = VC12 + VC1 = The final output voltage VO is equal to VO = VC14 − Vin = [ The voltage transfer gain is G=
© 2003 by CRC Press LLC
VO 3 = −1 Vin 1 − k
(6.68)
1956_C06.fm Page 372 Monday, August 18, 2003 3:24 PM
372
Advanced DC/DC Converters
C12
C1 D11 iIN
D12
C14 D13
D14
D1 +
S
C11
VIN –
R
C13
L1
iO – VO +
(a) Circuit diagram i IN iO + VIN
C 14
–
L1 C1
–
C 11
C 12
C 13
R
VO +
(b) Equivalent circuit during switchingon i IN
+
C 12
C1
C 14
–
VIN –
iO
C 11 C 13
L1
R
VO +
(c) Equivalent circuit during switchingoff FIGURE 6.9 Elementary triple boost circuit.
6.5.2
N/O TwoStage Triple Boost Circuit
The N/O twostage triple boost circuit is derived from twostage boost circuit by adding DEC twice in each stage circuit. Its circuit diagram and switchon and switchoff equivalent circuits are shown in Figure 6.10. As described in the previous section the voltage across capacitor C14 is VC14 = (3 1 − k )Vin . Analogously, the voltage across capacitor C24 is. VC 24 = ( © 2003 by CRC Press LLC
3 2 ) Vin 1− k
(6.69)
1956_C06.fm Page 373 Monday, August 18, 2003 3:24 PM
Negative Output Cascade Boost Converters
C12
C1 D11 iIN +
C2
C14
D12
D1
373
D13
D14
C11
L2
C24
C22
D3
D21
D23
D22
C13
D24
C23
C21
S
R
VIN D2
–
iO – VO +
L1
(a) Circuit diagram iIN iO
+ C24
VIN –
R
L1
C1
C11
C12
C13
C14
L2
C2
C21
C22
C23
– VO +
(b) Switch on iIN
C1
C12
C14
+ VIN – L1
C11
C13
C2
C22
C24 iO
L2
C21
– VO
C23 R
+
(c) Switch off FIGURE 6.10 Twostage triple boost circuit.
The final output voltage VO is equal to VO = VC 24 − Vin = [(
3 2 ) − 1]Vin 1− k
(6.70)
The voltage transfer gain is G=
© 2003 by CRC Press LLC
VO 3 2 =( ) −1 1− k Vin
(6.71)
1956_C06.fm Page 374 Monday, August 18, 2003 3:24 PM
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Advanced DC/DC Converters
Analogously, ∆iL1 =
Vin kT L1
I L1 = (
∆iL2 =
V1 kT L2
I L2 =
2 2 ) I 1− k O
2IO 1− k
Therefore, the variation ratio of current iL1 through inductor L1 is ∆iL1 / 2 k(1 − k )2 TVin k(1 − k ) 4 R = = 8L1 I O 16 I L1 fL1
ξ1 =
(6.72)
and the variation ratio of current iL2 through inductor L2 is ξ2 =
∆iL 2 / 2 k(1 − k )TV1 k(1 − k )2 R = = 4L2 I O 8 I L2 fL2
(6.73)
The ripple voltage of output voltage vO is ∆vO =
∆Q I O (1 − k )T 1 − k VO = = C22 C22 fC22 R
Therefore, the variation ratio of output voltage vO is ε=
6.5.3
∆vO / 2 1− k = 2 RfC22 VO
(6.74)
N/O ThreeStage Triple Boost Circuit
This N/O circuit is derived from the threestage boost circuit by adding DEC twice in each stage circuit. Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 6.11. As described in the previous section the voltage across capacitor C14 is 2 VC14 = (3 1 − k )Vin , and the voltage across capacitor C24 is VC 24 = (3 1 − k ) Vin. Analogously, the voltage across capacitor C34 is VC 34 = (
3 3 ) Vin 1− k
The final output voltage VO is equal to © 2003 by CRC Press LLC
(6.75)
iIN
D1
+
D12 D13
D14
C11
L2
D3
D21
D22
C13
C3
C24
C22 D23
D24
L3
D31
C23
C21
C34
C32
D5
D33
D32
C31
D34 iO – VO +
C33 R
S D2
VIN
L1
–
D4
(a) Circuit diagram
iIN
iO
+ C34
VIN –
R
L1
C1
C11
C12
C13
C14
L2
C2
C21
C22
C23
C14
L3
C3
C31
C32
C33
– VO +
(b) Equivalent circuit during switchon iIN
C1
C12
C14
C2
C22
C24
C3
C32
C34 iO
+ VIN – L1
C11
C13
L2
C21
C23
L3
C31
– VO
C33 R
+
(c) Equivalent circuit during switchoff
© 2003 by CRC Press LLC
375
FIGURE 6.11 Threestage triple boost circuit.
1956_C06.fm Page 375 Monday, August 18, 2003 3:24 PM
D11
C2
C14
Negative Output Cascade Boost Converters
C12
C1
1956_C06.fm Page 376 Monday, August 18, 2003 3:24 PM
376
Advanced DC/DC Converters
VO = VC 34 − Vin = [(
3 3 ) − 1]Vin 1− k
(6.76)
The voltage transfer gain is G=
VO 3 3 =( ) −1 1− k Vin
(6.77)
Analogously, ∆iL1 =
Vin kT L1
I L1 =
32 I (1 − k ) 3 O
∆iL2 =
V1 kT L2
I L2 =
8 I (1 − k )2 O
∆iL3 =
V2 kT L3
I L3 =
2 I 1− k O
Therefore, the variation ratio of current iL1 through inductor L1 is ∆iL1 / 2 k(1 − k ) 3 TVin k(1 − k )6 R = = 64L1 I O 12 3 I L1 fL1
ξ1 =
(6.78)
and the variation ratio of current iL2 through inductor L2 is ∆iL 2 / 2 k(1 − k ) 2 TV1 k(1 − k ) 4 R = = 16L2 I O 12 2 I L2 fL2
ξ2 =
(6.79)
and the variation ratio of current iL3 through inductor L3 is ξ3 =
∆iL 3 / 2 k(1 − k )TV2 k(1 − k )2 R = = 4 L3 I O 12 I L3 fL3
(6.80)
Usually ξ1, ξ2, and ξ3 are small, this means that this converter works in the continuous mode. The ripple voltage of output voltage vO is ∆vO =
© 2003 by CRC Press LLC
∆Q I O (1 − k )T 1 − k VO = = C32 C32 fC32 R
1956_C06.fm Page 377 Monday, August 18, 2003 3:24 PM
Negative Output Cascade Boost Converters
377
Therefore, the variation ratio of output voltage vO is ∆vO / 2 1− k = 2 RfC32 VO
ε=
6.5.4
(6.81)
N/O Higher Stage Triple Boost Circuit
The N/O higher stage triple boost circuit is derived from the corresponding circuit of the main series by adding DEC twice in each stage circuit. For nth stage additional circuit, the voltage across capacitor Cn4 is VCn 4 = (
3 n ) Vin 1− k
The output voltage is VO = VCn 4 − Vin = [(
3 n ) − 1]Vin 1− k
(6.82)
The voltage transfer gain is G=
VO 3 n =( ) −1 1− k Vin
(6.83)
Analogously, the variation ratio of current iLi through inductor Li (i = 1, 2, 3, …n) is ξi =
∆iLi / 2 k(1 − k )2( n−i +1) R = I Li fLi 12 ( n−i +1)
(6.84)
and the variation ratio of output voltage vO is ε=
6.6
∆vO / 2 1− k = 2 RfCn 2 VO
(6.85)
Multiple Series
All circuits of N/O cascade boost converters — multiple series — are derived from the corresponding circuits of the main series by adding DEC multiple © 2003 by CRC Press LLC
1956_C06.fm Page 378 Monday, August 18, 2003 3:24 PM
378
Advanced DC/DC Converters
(j) times in each stage circuit. The first three stages of this series are shown in Figure 6.12 to Figure 6.14. For convenience they are called elementary multiple boost circuit, twostage multiple boost circuit, and threestage multiple boost circuit respectively, and numbered as n = 1, 2 and 3.
6.6.1
N/O Elementary Multiple Boost Circuit
This N/O elementary multiple boost circuit is derived from elementary boost converter by adding a DEC multiple (j) times. Its circuit and switchon and switchoff equivalent circuits are shown in Figure 6.12. The output voltage of the first DEC (across capacitor C12j) increases to VC12 j =
j+1 V 1 − k in
(6.86)
The final output voltage VO is equal to VO = VC12 j − Vin = [
j+1 − 1]Vin 1− k
(6.87)
The voltage transfer gain is G=
6.6.2
VO j+1 = −1 Vin 1 − k
(6.88)
N/O TwoStage Multiple Boost Circuit
The N/O twostage multiple boost circuit is derived from the twostage boost circuit by adding DEC multiple (j) times in each stage circuit. Its circuit diagram and switchon and switchoff equivalent circuits are shown in Figure 6.13. As described in the previous section the voltage across capacitor C12j is VC12 j =
j+1 V 1 − k in
Analogously, the voltage across capacitor C22j is. VC 22 j = (
j+1 2 ) Vin 1− k
The final output voltage VO is equal to © 2003 by CRC Press LLC
(6.89)
1956_C06.fm Page 379 Monday, August 18, 2003 3:24 PM
Negative Output Cascade Boost Converters
379
1
C12j
C 12
C1 D 11 i IN +
j
2....
D 12
D 1(2j–1)
D 12j
D1 S
C 11
VIN –
R C 1(2j–1)
L1
iO – VO +
(a) Circuit diagram iIN iO +
C 12j
VIN L1 C1
–
C11
C 1(2j–i) R
C12
– VO +
(b) Equivalent circuit during switching–on iIN
+
C1
C12
C 12j
–
VIN –
iO
C11 C 1(2j–1)
L1
R
VO +
(c) Equivalent circuit during switching–off FIGURE 6.12 Elementary multiple boost circuit.
VO = VC 22 j − Vin = [(
j+1 2 ) − 1]Vin 1− k
(6.90)
The voltage transfer gain is G=
VO j+1 2 =( ) −1 Vin 1− k
The ripple voltage of output voltage vO is © 2003 by CRC Press LLC
(6.91)
1956_C06.fm Page 380 Monday, August 18, 2003 3:24 PM
380
Advanced DC/DC Converters
1
C1
iIN
+
2...
D1
j
C12
D11
D12
C12j D1(2j–1) D12j
C2 D3
L2
D21
j
2...
1
C22 D22
C22j
D2(2j–1) D22j
S C11
VIN
C1(2j–1)
–
C2(2j–1)
C21
L1
R
iO – VO +
D2
(a) Circuit diagram iIN iO C22j
+ VIN –
R
L1
C1
C11
C12 C1(2j–1)
C12j
L2
C2
C21
C22 C2(2j–1)
– VO +
(b) Switch on iIN
C12
C1
C12j
C2
C22
C22j iO
+ VIN – L1
C1(2j–1)
C11
L2
C21
C2(2j–1) R
– VO +
(c) Switch off FIGURE 6.13 Twostage multiple boost circuit.
∆vO =
∆Q I O (1 − k )T 1 − k VO = = C22 j C22 j fC22 j R
Therefore, the variation ratio of output voltage vO is ε= © 2003 by CRC Press LLC
∆vO / 2 1− k = 2 RfC22 j VO
(6.92)
1956_C06.fm Page 381 Monday, August 18, 2003 3:24 PM
Negative Output Cascade Boost Converters 6.6.3
381
N/O ThreeStage Multiple Boost Circuit
This N/O circuit is derived from the threestage boost circuit by adding DEC multiple (j) times in each stage circuit. Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 6.14. As described in the previous section the voltage across capacitor C12j is VC12 j = ( j + 1 1 − k )Vin , a n d t h e v o l t a g e a c r o s s c a p a c i t o r C 2 2 j i s 2 VC 22 j = ( j + 1 1 − k ) Vin . Analogously, the voltage across capacitor C32j is VC 32 j = (
j+1 3 ) Vin 1− k
(6.93)
The final output voltage VO is equal to
VO = VC 32 j − Vin = [(
j+1 3 ) − 1]Vin 1− k
(6.94)
The voltage transfer gain is
G=
VO j+1 3 =( ) −1 Vin 1− k
(6.95)
The ripple voltage of output voltage vO is
∆vO =
∆Q I O (1 − k )T 1 − k VO = = C32 j C32 j fC32 j R
Therefore, the variation ratio of output voltage vO is
ε=
6.6.4
∆vO / 2 1− k = 2 RfC32 j VO
(6.96)
N/O Higher Stage Multiple Boost Circuit
The N/O higher stage multiple boost circuit is derived from the corresponding circuit of the main series by adding DEC multiple (j) times in each stage circuit. For nth stage multiple boost circuit, the voltage across capacitor Cn2j is © 2003 by CRC Press LLC
© 2003 by CRC Press LLC C 11
C 12 C 1(2j–1)
D2
C 12j
L2
C 12j
L2
D4
C2 D 21
D 22
C 2(2j–1)
C2
C 21
C 22 C 2(2j–1) C 22j
D 2(2j–1) D 22j
C 22
(a) Circuit diagram
C 21
D3
j
L3
L3
C 22j
C3
C 31
C 31
D5
C3
C 32
D 31
1
D 32
+
–
V IN
i IN
L1
C 11
C 12
C 1(2j–1)
C 12j
C 21
C 22
C 2(2j–1)
C 22j
L3
C3
(c) Equivalent circuit during switchoff
L2
C2
(b) Equivalent circuit during switchon
C 31
C 32
C 3(2j–1) R
C 32j
+
– VO
iO
C 3(2j–1)
j
C 3(2j–1)
+
– VO
iO
R
D 3(2j–1) D 32j
C 32
2...
R C1
D 1(2j–1) D 12j
C 1(2j–1)
C 12
2...
C 32j
C1
C 11
D 12
1
– L1
C1 D 11
j
V IN
+
i IN
L1
S
D1
2...
iO
+
VO
–
C 32j
382
FIGURE 6.14 Threestage multiple boost circuit.
–
V IN
+
iIN
1
1956_C06.fm Page 382 Monday, August 18, 2003 3:24 PM
Advanced DC/DC Converters
1956_C06.fm Page 383 Monday, August 18, 2003 3:24 PM
Negative Output Cascade Boost Converters
VCn 2 j = (
383
j+1 n ) Vin 1− k
The output voltage is VO = VCn 2 j − Vin = [(
j+1 n ) − 1]Vin 1− k
(6.97)
The voltage transfer gain is G=
VO j+1 n =( ) −1 1− k Vin
(6.98)
The variation ratio of output voltage vO is ε=
6.7
∆vO / 2 1− k = 2 RfCn 2 j VO
(6.99)
Summary of Negative Output Cascade Boost Converters
All the circuits of the N/O cascade boost converters as a family can be shown in Figure 6.15. From the analysis of the previous two sections we have the common formula to calculate the output voltage: 1 n [( 1 − k ) − 1]Vin 1 n ) − 1]Vin [2 ∗ ( − k 1 2 n VO = [( ) − 1]Vin − k 1 [( 3 )n − 1]Vin 1− k j+1 n [( 1 − k ) − 1]Vin The voltage transfer gain is © 2003 by CRC Press LLC
main _ series additional _ series double _ series triple _ series multiple( j ) _ series
(6.100)
1956_C06.fm Page 384 Monday, August 18, 2003 3:24 PM
384
Advanced DC/DC Converters Main Series
Additional Series
Double Series
Triple Series
Multiple Series
5 Stage N/O Boost Circuit
5 Stage N/O Additional Circuit
5 Stage N/O Double Circuit
5 Stage N/O Triple Circuit
5 Stage N/O Multiple Circuit
4 Stage N/O Boost Circuit
4 Stage N/O Additional Circuit
4 Stage N/O Double Circuit
4 Stage N/O Triple Circuit
4 Stage N/O Multiple Circuit
3 Stage N/O Boost Circuit
3 Stage N/O Additional Circuit
3 Stage N/O Double Circuit
3 Stage N/O Triple Circuit
3 Stage N/O Multiple Circuit
2 Stage N/O Boost Circuit
2 Stage N/O Additional Circuit
2 Stage N/O Double Circuit
2 Stage N/O Triple Circuit
2 Stage N/O Multiple Circuit
Elementary N/O Triple Circuit
Elementary N/O Multiple Circuit
Elementary N/O Additional/Double Circuit
Elementary Negative Output Boost Converter
FIGURE 6.15 The family of negative output cascade boost converters.
1 n (1 − k ) − 1 1 n ) −1 2 ∗ ( − 1 k V 2 n G= O = ( ) −1 Vin 1 − k ( 3 )n − 1 1− k j+1 n ( 1 − k ) − 1
main _ series additional _ series double _ series
(6.101)
triple _ series multiple( j ) _ series
In order to show the advantages of N/O cascade boost converters, we compare their voltage transfer gains to that of the buck converter, G= © 2003 by CRC Press LLC
VO =k Vin
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Negative Output Cascade Boost Converters
385
forward converter, G=
VO = kN Vin
G=
VO k = Vin 1 − k
G=
VO k = N Vin 1 − k
G=
VO 1 = Vin 1 − k
N is the transformer turn ratio
Cúkconverter,
flyback converter, N is the transformer turn ratio
boost converter,
and negative output Luoconverters G=
VO n = Vin 1 − k
(6.102)
If we assume that the conduction duty k is 0.2, the output voltage transfer gains are listed in Table 6.1, if the conduction duty k is 0.5, the output voltage transfer gains are listed in Table 6.2, if the conduction duty k is 0.8, the output voltage transfer gains are listed in Table 6.3.
6.8 6.8.1
Simulation and Experimental Results Simulation Results of a ThreeStage Boost Circuit
To verify the design and calculation results, PSpice simulation package was applied to a threestage boost circuit. Choosing Vin = 20 V, L1 = L2 = L3 = 10 mH, all C1 to C8 = 2 µF and R = 30 kΩ, and using k = 0.7 and f = 100 kHz. The voltage values V1, V2, and VO of a triplelift circuit are 66 V, 194 V, and 659 V respectively, and inductor current waveforms iL1 (its average value IL1 = 618 mA), iL2, and iL3. The simulation results are shown in Figure 6.16. The voltage values are matched to the calculated results. © 2003 by CRC Press LLC
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TABLE 6.1 Voltage Transfer Gains of Converters in the Condition k = 0.2 Stage No. (n) Buck converter Forward converter Cúkconverter Flyback converter Boost converter Negative output Luoconverters Negative output cascade boost converters — main series Negative output cascade boost converters — additional series Negative output cascade boost converters — double series Negative output cascade boost converters — triple series Negative output cascade boost converters — multiple series (j=3)
1
2
3
4
5
n
1.25 0.25
0.2 0.2N (N is the transformer turn ratio) 0.25 0.25N (N is the transformer turn ratio) 1.25 2.5 3.75 5 6.25 1.25n 0.563 0.953 1.441 2.052 1.25n1
1.5
2.125
2.906
3.882
5.104
2∗1.25n1
1.5
5.25
14.625
38.063
96.66
(2∗1.25)n1
2.75
13.06
51.73
196.75
740.58
(3∗1.25)n1
4
24
124
624
3124
(4∗1.25)n1
TABLE 6.2 Voltage Transfer Gains of Converters in the Condition k = 0.5 Stage No. (n)
1
Buck converter Forward converter Cúkconverter Flyback converter Boost converter Negative output Luoconverters Negative output cascade boost converters — main series Negative output cascade boost converters — additional series Negative output cascade boost converters — double series Negative output cascade boost converters — triple series Negative output cascade boost converters — multiple series (j=3)
0.5 0.5N (N is the transformer turn ratio) 1 N (N is the transformer turn ratio) 2 2 4 6 8 10 2n 1 3 7 15 31 2n1
6.8.2
2
3
4
5
n
3
7
15
31
63 2∗2n1
3
15
63
255
1023 (2∗2)n1
5
35
215
1295
7775 (3∗2)n1
7
63
511
4095
32767 (4∗2)n1
Experimental Results of a ThreeStage Boost Circuit
A test rig was constructed to verify the design and calculation results, and compare with PSpice simulation results. The test conditions are still Vin = 20 V, L1 = L2 = L3 = 10 mH, all C1 to C8 = 2 µF and R = 30 kΩ, and using k = 0.7 and f = 100 kHz. The component of the switch is a MOSFET device IRF950 © 2003 by CRC Press LLC
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387
TABLE 6.3 Voltage Transfer Gains of Converters in the Condition k = 0.8 Stage No. (n)
1
Buck converter Forward converter Cúkconverter Flyback converter Boost converter Negative output Luoconverters Negative output cascade boost converters — main series Negative output cascade boost converters — additional series Negative output cascade boost converters — double series Negative output cascade boost converters — triple series Negative output cascade boost converters — multiple series (j=3)
2
5 4
3
4
5
n
0.8 0.8N (N is the transformer turn ratio) 4 4N (N is the transformer turn ratio) 5 10 15 20 25 5n 24 124 624 3124 5n1 2∗5n1
9
49
249
1249
6249
9
99
999
9999
99999
(2∗5)n1
14
224
3374
50624
759374
(3∗5)n1
19
399
7999
15999
32 × 105
(4∗5)n1
1.0A (9.99m, 603m) 0.5A
0A
(9.99m, 205m) (9.99m, 55m) I(L1)
I(L2)
I(L3)
0V 250V
(9.99m, 46) (9.99m, 174)
500V SEL>>
(9.99m, 639)
9.980ms V(C4:2)
9.985ms V(C2:2)
V(R:2)
9.990ms
9.995ms
10.000ms
Time
FIGURE 6.16 The simulation results of a threestage boost circuit at condition k = 0.7 and f = 100 kHz.
with the rates 950 V/5 A/2 MHz. We measured the values of the output voltage and first inductor current in the following converters. After careful measurement, the current value of IL1 = 0.62 A (shown in channel 1 with 1 A/Div) and voltage value of VO = 660 V (shown in Channel 2 with 200 V/Div) are obtained. The experimental results (current and voltage values) in Figure 6.17 match the calculated and simulation results, which are IL1 = 0.618 A and VO = 659 V shown in Figure 6.16. © 2003 by CRC Press LLC
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Advanced DC/DC Converters
FIGURE 6.17 The experimental results of a threestage boost circuit at condition k = 0.7 and f = 100 kHz.
TABLE 6.4 Comparison of Simulation and Experimental Results of a TripleLift Circuit. Stage No. (n) Simulation results Experimental results
6.8.3
IL1 (A)
Iin (A)
0.618 0.62
0.927 0.93
Vin (V)
Pin (W)
VO (V)
PO (W)
η (%)
20 20
18.54 18.6
659 660
14.47 14.52
78 78
Efficiency Comparison of Simulation and Experimental Results
These circuits enhanced the voltage transfer gain successfully, and efficiently. Particularly, the efficiencies of the tested circuits is 78%, which is good for high output voltage equipment. To compare the simulation and experimental results, see Table 6.4. All results are well identified with each other.
6.8.4
Transient Process
Usually, there is high inrush current during the first poweron. Therefore, the voltage across capacitors is quickly changed to certain values. The transient process is very quick taking only a few milliseconds. It is difficult to demonstrate it in this section.
© 2003 by CRC Press LLC
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389
Bibliography Liu, K.H. and Lee, F.C., Resonant switches — a unified approach to improved performances of switching converters, in Proceedings of International Telecommunications Energy Conference, New Orleans, LA, U.S., 1984, p. 344. Luo, F.L. and Ye, H., Fundamentals of negative output cascade boost converters, in Proceedings of IEEEEPEMC’2003, Xi’an, China, 2003, p. 1896. Luo, F.L. and Ye, H., Development of negative output cascade boost converters, in Proceedings of IEEEEPEMC’2003, Xi’an, China, 2003, p. 1888. Martinez, Z.R. and Ray, B., Bidirectional DC/DC power conversion using constantfrequency multiresonant topology, in Proceedings of Applied Power Electronics Conf. APEC’94, Orlando, FL, U.S., 1994, p. 991. Masserant, B.J. and Stuart, T.A., A high frequency DC/DC converter for electric vehicles, in Proceedings of Power Electronics in Transportation, 1994, p. 123. Pong, M.H., Ho, W.C., and Poon, N.K., Soft switching converter with power limiting feature, IEE Proceedings on Electric Power Applications, 146, 95, 1999.
© 2003 by CRC Press LLC
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7 Multiple Quadrant Operating LuoConverters
Classical DCDC converters usually perform in single quadrant operation, such as buck converter, and Luoconverters. Multiplequadrant operation is required in industrial applications, e.g., a DC motor running forward and reverse in motoring and regenerative braking states. This chapter introduces three new converters that can perform two and fourquadrant DC/DC conversion. One particular application is the MIT 42/±14 V DC/DC converter used for new car power supply systems. Because this converter implements dualdirection energy transference, it is a secondgeneration DC/DC converter. Simulation and experimental results have verified its characteristics.
7.1
Introduction
Multiplequadrant operation converters can be derived from the multiplequadrant chopper. Correspondingly, class B converters can be derived from type B choppers (twoquadrant operation), class E converters from type E choppers (fourquadrant operation) and so on. Also, multiplequadrant operating converters can be derived from other first generation converters. This paper introduces two and fourquadrant operation Luoconverters, which are derived from positive, negative and double output Luoconverters. They correspond to a DC motor drive in forward and reverse running with motoring and regenerative braking states. These converters are shown in Figure 7.1. The input source and output load are usually certain voltages as shown V1 and V2. Switches S1 and S2 in this diagram are power MOSFET devices, and driven by a pulsewidthmodulated (PWM) switching signal with repeating frequency f and conduction duty k. In this paper the switch repeating period is T = 1/f, the switchon period is kT and switchoff period is (1 – k)T. The equivalent resistance is R for each inductor. During switchon the voltage drop across the switches and diodes are VS and VD. When the switch is turned off, the freewheeling diode current descends in whole switchoff period (1 – k)T. If the diode current does not become zero before
© 2003 by CRC Press LLC
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Advanced DC/DC Converters
C _ + VC
S1
L2
R I2
D1 I1
+ V2_
S2
L1
+ _ V1
D2 R
(a) Circuit 1
S2
S1
L2
R i L2
D1 I1
L1
+ _ V1
_
D2 C
_
VC +
V2
R
+ I2
(b) Circuit 2 A1/ B2
A
S1
C _ + VC
B B1/ C2
L2
R
D1 I1
+ L1
+ _ V1
S2
D2 C
R
V2
_
I2
C1/ A2
(C) Circuit 3 FIGURE 7.1 Multiplequadrant operating Luoconverters.
the switch is turned on again, we define this working state to be the continuous region. If the current becomes zero before the switch is turned on again, this working state is the discontinuous conduction region. In this chapter, variation ratio of current iL1 is ξ1 =
© 2003 by CRC Press LLC
∆iL1 / 2 I L1
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393
Variation ratio of current iL2 is ξ2 =
∆iL 2 / 2 I L2
Variation ratio of current iD is ζ=
∆iD / 2 ID
ρ=
∆vC / 2 VC
Variation ratio of voltage vC is
7.2
Circuit Explanation
Each converter shown in Figure 7.1 consists of two switches with two passive diodes, two inductors and one capacitor. Circuit 1 performs a twoquadrant (forward) operation, and circuit 2 performs a twoquadrant (reverse) operation. Circuit 1 and circuit 2 can be converted to each other by a threepole (A, B, and C) doublethrough (A1/A2, B1/B2, and C1/C2) auxiliary changeover switch as circuit 3. Circuit 3 performs a fourquadrant operation. Since the changeover process between forward and reverse operations is not very frequent, so that the auxiliary changeover switch can be isolatedgate bipolar transistor (IGBT), power relay and contactor. The source voltage (V1) and load voltage (V2) are usually considered as constant voltages. The load can be a battery or motor back electromotive force (EMF). For example, when the source voltage is 42 V and load voltage is ±14 V there are four modes of operation: 1. Mode A (Quadrant I): electrical energy is transferred from source side V1 to load side V2 2. Mode B (Quadrant II): electrical energy is transferred from load side V2 to source side V1 3. Mode C (Quadrant III): electrical energy is transferred from source side V1 to load side –V2 4. Mode D (Quadrant IV): electrical energy is transferred from load side –V2 to source side V1 Each mode has two states: on and off. Circuit 1 in Figure 7.1a implements Modes A and B, and Circuit 2 in Figure 7.1b implements Modes C and D. © 2003 by CRC Press LLC
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Advanced DC/DC Converters C _
S1
L2
VC+
i L1 + V _ 1
R
i L2
S2 L1
+ V2 _ D2
R
(a) Switch on C _
L2
VC+
L1
R
+ V2
D2
_
i L1
i L2
R
(b) Switch off i
i L1
i L2 0
t
v vC
0
kT
T
t
(c) Waveforms with enlarged variations FIGURE 7.2 Mode A.
7.2.1
Mode A
Mode A implements the characteristics of the buckboost conversion. For mode A, stateon is shown in Figure 7.2a: switch S1 is closed, switch S2 and diodes D1 and D2 are not conducted. In this case inductor currents iL1 and iL2 increase, and i1 = iL1 + iL2. Stateoff is shown in Figure 7.2b: switches S1, S2, and diode D1 are off and diode D2 is conducted. In this case current iL1 © 2003 by CRC Press LLC
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Multiple Quadrant Operating LuoConverters C _ + VC
S1 D1 +
L2
R
+ V2 _
S2
L1
V1
395
_
i L1
i L2
R
(a) Switch on –
+
C
D1
L2
VC
R + V2
L1
_
i L1 R
i L2
(b) Switch off i
i L1 i L2
0
t
v vC A
0
t
(c) Waveforms with enlarged variations FIGURE 7.3 Mode B.
flows via diode D2 to charge capacitor C, in the meantime current iL2 is kept to flow through load battery V2. The freewheeling diode current iD2 = iL1 + iL2. Some currents’ and voltages’ waveforms are shown in Figure 7.2c. 7.2.2
Mode B
Mode B implements the characteristics of the boost conversion. For mode B, stateon is shown in Figure 7.3a: switch S2 is closed, switch S1 and diodes D1 and D2 are not conducted. In this case inductor current iL2 increases by biased © 2003 by CRC Press LLC
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Advanced DC/DC Converters
V2, inductor current iL1 increases by biased VC. Therefore capacitor voltage VC reduces. Stateoff is shown in Figure 7.3b: switches S1, S2 and diode D2 are not on, and only diode D1 is on. In this case source current i1 = iL1 + iL2 which is a negative value to perform the regenerative operation. Inductor current iL2 flows through capacitor C, it is charged by current iL2. After capacitor C, iL2 then flows through the source V1. Inductor current iL1 flows through the source V1 via diode D1. Some currents’ and voltages’ waveforms are shown in Figure 7.3c.
7.2.3
Mode C
Mode C implements the characteristics of the buckboost conversion. For mode C, stateon is shown in Figure 7.4a: switch S1 is closed, switch S2 and diodes D1 and D2 are not conducted. In this case inductor currents iL1 and iL2 increase, and i1 = iL1. Stateoff is shown in Figure 7.4b: switches S1, S2, and diode D1 are off and diode D2 is conducted. In this case current iL1 flows via diode D2 to charge capacitor C and the load battery V2 via inductor L2. The freewheeling diode current iD2 = iL1 = iC + i2. Some waveforms are shown in Figure 7.4c. 7.2.4
Mode D
Mode D implements the characteristics of the boost conversion. For mode D, stateon is shown in Figure 7.5a: switch S2 is closed, switch S1 and diodes D1 and D2 are not conducted. In this case inductor current iL1 increases by biased V2, inductor current iL2 decreases by biased (V2 – VC). Therefore capacitor voltage VC reduces. Current iL1 = iC–on + i2. Stateoff is shown in Figure 7.5b: switches S1, S2, and diode D2 are not on, and only diode D1 is on. In this case source current i1 = iL1 which is a negative value to perform the regenerative operation. Inductor current i2 flows through capacitor C that is charged by current i2, i.e., ic–off = i2. Some currents and voltages waveforms are shown in Figure 7.5c.
7.2.5
Summary
The switch status of all modes is listed in Table 7.1. From the table it can be seen that only one switch works in one mode, so that this converter is very simple and effective.
7.3
Mode A (Quadrant I Operation)
As shown in Figure 7.2a and b the voltage across capacitor C increases during switchon, and decreases during switch off. Capacitor C acts as the primary
© 2003 by CRC Press LLC
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L2
S1
+ _
V1 i L1
397
C
L1
R
_ VC +
_
V2
R
+
i L2
(a) Switch on L2
D2
R
_
_
VC +
C
L1
V2
+
i L1 R
i L2
(b) Switch off i
i L1 i L2
0
t
v vC A
0
t
(c) Waveforms with enlarged variations FIGURE 7.4 Mode C.
means of storing and transferring energy from the input source to the output load via the pump inductor L1. Assuming capacitor C to be sufficiently large, the variation of the voltage across capacitor C from its average value VC can be neglected in steady state, i.e., vC(t) ≈ VC, even though it stores and transfers energy from the input to the output.
7.3.1
Circuit Description
When switch S1 is on, the source current i1 = iL1 + iL2. Inductor L1 absorbs energy from the source. In the mean time inductor L2 absorbs energy from © 2003 by CRC Press LLC
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Advanced DC/DC Converters D1
+
V1
_
L2
S2 _
L1
C
R
i L2
V + C
R _
V2
+
i L1
(a) Switch on L2
D1 i L1 + _ V1
L1
_
C
V + C
R i L2
_
V2
+
R
(b) Switch off i i L1 i L2 0
v
t vC B
0
kT
T t
(c) Waveforms with enlarged variations FIGURE 7.5 Mode D.
TABLE 7.1 Switch Status Switch or Diode Circuit
S1 D1 S2 D2
Mode A (QI) Mode B (QII) Mode C (QIII) Mode D (QIV) Stateon Stateoff Stateon Stateoff Stateon Stateoff Stateon Stateoff Circuit 1 Circuit 2 ON ON ON ON ON ON ON ON
Note: The blank status means OFF.
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399
source and capacitor C, both currents iL1 and iL2 increase. When switch S1 is off, source current iI = 0. Current iL1 flows through the freewheeling diode D2 to charge capacitor C. Inductor L1 transfers its stored energy to capacitor C. In the mean time current iL2 flows through the load V2 and freewheeling diode D2 to keep itself continuous. Both currents iL1 and iL2 decrease. In order to analyze the circuit working procession, these waveforms with enlarged variations are shown in Figure 7.2c. The equivalent circuits in switchon and off states are shown in Figure 2a and b. Actually, the variations of currents iL1 and iL2 are small so that iL1 ≈ IL1 and iL2 ≈ IL2 The charge on capacitor C increases during switch off and on: Q+ = (1 – k)T IL1 Q– = kTIL2 In a whole period investigation, Q+ = Q–. I L2 =
Thus,
1− k I k L1
(7.1)
Since capacitor C performs as a lowpass filter, the output current IL2 = I2 The source current i1 = iL1 + iL2 during switchon, and i1 = 0 during switchoff. Average source current I1 is I 1 = k × i1 = k(iL1 + iL 2 ) = k(1 +
1− k ) I L1 = I L1 k
Hence, the output current is I2 =
1− k I k 1
The input and output powers are PI = V1 I 1 The power losses are © 2003 by CRC Press LLC
and
PO = V2 I 2
(7.2)
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Advanced DC/DC Converters VSI1 — RIL12 — VDI1 — RIL22 —
Switch power loss Power loss across inductor L1 Diode power loss Power loss across inductor L2
The total power losses are Ploss = VS I 1 + VD I 1 + R( I 12 + I 2 2 )
(7.3)
Since PI = PO + Ploss hence V1 I 1 = V2 I 2 + (VS + VD )I 1 + R( I 12 + I 2 2 )
(7.4)
or V1 = V2
1− k 1− k k + (VS + VD ) + RI 2 ( + ) 1− k k k
(7.5)
1− k k 1− k k R( + ) 1− k k
(7.6)
The output current is
I2 =
V1 − VS − VD − V2
The minimum conduction duty k corresponding to I2 = 0 is kmin =
V2 V1 + V2 − VS − VD
(7.7)
The power transfer efficiency is ηA =
PO V2 I 2 = = PI V1 I 1
© 2003 by CRC Press LLC
1 VS + VD k RI 1− k 2 1+ ) ] + 2 [1 + ( 1 − k V2 V2 k
(7.8)
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Multiple Quadrant Operating LuoConverters 7.3.2
401
Variations of Currents and Voltages
Because the voltage across the inductor L1 is (V1 – RI1) during switchon and (VC + RI1) during switchoff, the average voltage across capacitor C is kT (V1 − RI 1 ) = (VC + RI 1 )(1 − k )T Hence VC =
RI 2 1 k k k k = V1 − RI 1 = (V1 − ) (7.9) V1 − RI 2 2 1− k 1− k 1− k 1− k 1− k (1 − k )
The peaktopeak variation of capacitor voltage vC is ∆vC =
Q− kTI 2 kI 2 = = C C fC
The variation ratio of capacitor voltage vC is ρ=
∆vC / 2 (1 − k )I 2 = 1 VC 2 fC(V1 − RI 2 ) 1− k
(7.10)
The peaktopeak variation of inductor current iL1 is ∆iL1 =
V1 − VS − RI 1 kT L1
The variation ratio of inductor current iL1 is ξ1 =
V − VS − RI 1 ∆iL1 / 2 =k 1 2 fL1 I 1 I L1
(7.11)
The peaktopeak variation of inductor current iL2 is ∆iL 2 =
V1 − VS − V2 + VC − RI 2 V − VS − RI 1 kT = 1 kT L2 L2
The variation ratio of inductor current iL2 is ξ2 = © 2003 by CRC Press LLC
V − VS − RI 1 ∆iL 2 / 2 =k 1 2 fL2 I 2 I L2
(7.12)
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Advanced DC/DC Converters
I1
Continuous Region Discontinuous Region 0
1
Kmin
k
FIGURE 7.6 Boundary between continuous and discontinuous regions of Mode A.
The freewheeling diode’s current iD2 during switch off is: iD2 = iL1 + iL2. Its peaktopeak variation is ∆iD 2 = ∆iL1 + ∆iL 2 =
V1 − VS − RI 1 kT L
where L = L1L2 /( L1 + L2). The variation ratio of the diode current iD2 is ζD2 =
7.3.3
V − VS − RI 1 V − VS − RI 1 ∆iD 2 / 2 =k 1 = k2 1 I L1 + I L 2 2 fL( I 1 + I 2 ) 2 fLI 1
(7.13)
Discontinuous Region
If the diode current becomes zero before S1 switch is on again, the converter works in discontinuous region. The condition iD ζD2 = 1, i.e., k2 =
2 fLI 1 V1 − VS − RI 1
(7.14)
From Equations (7.7) and (7.14) the boundary between continuous and discontinuous regions is shown in Figure 7.6. Particularly, since conduction duty k is greater than kmin and the current is high, the converter usually works in the continuous region. © 2003 by CRC Press LLC
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7.4
403
Mode B (Quadrant II Operation)
As shown in Figure 7.3a and b the voltage across capacitor C decreases during switchon, and increases during switch off. Capacitor C acts as the primary means of storing and transferring energy from the load battery to the source via inductor L2. Assuming capacitor C to be sufficiently large, the variation of the voltage across capacitor C from its average value VC can be neglected in steady state, i.e., vC(t) ≈ VC, even though it stores and transfers energy from the load V2 to the source V1. 7.4.1
Circuit Description
When switch S2 is off, source current i1 = 0. Current iL1 flows through the switch S2 and capacitor C, and increases. Current iL1 flows through the switch S2, and increases. When switch S2 is off, the source current i1 = iL1 + iL2. The freewheeling diode D1 is conducted. Both currents iL1 and iL2 decrease. Inductor L1 transfers its stored energy to capacitor C. In the mean time current iL2 flows through the source V1. In order to analyze the circuit working procession, these waveforms with enlarged variations are shown in Figure 7.3c. The equivalent circuits in switchon and off states are shown in Figures 7.3a and b. Actually, the variations of currents iL1 and iL2 are small so that iL1 ≈ IL1
and iL2 ≈ IL2
The charge on capacitor C increases during switch off and on: Q+ = (1 – k)T IL2 Q– = kTIL1 In a whole period investigation, Q+ = Q–. Thus,
I L1 =
1− k I k L2
(7.15)
Since capacitor C performs as a lowpass filter, the output current IL2 = I2 The source current i1 = iL1 + iL2 during switchon, and i1 = 0 during switchoff. Average source current I1 is © 2003 by CRC Press LLC
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Advanced DC/DC Converters
I 1 = (1 − k )i1 = (1 − k )(iL1 + iL 2 ) = (1 − k )(1 +
1 )I = I L1 1 − k L1
Hence, the output current is I1 =
1− k I k 2
(7.16)
The input and output powers are PI = V2 I 2
and
PO = V1 I 1
The power losses are VSI1 — RIL12 — VDI1 — RIL22 —
Switch power loss Power loss across inductor L1 Diode power loss Power loss across inductor L2
The total power losses are Ploss = VS I 1 + VD I 1 + R( I 12 + I 2 2 )
(7.17)
Since PI = PO + Ploss hence V2 I 2 = V1 I 1 + (VS + VD )I 1 + R( I 12 + I 2 2 )
(7.18)
or V2 =
1− k 1− k k (V1 + VS + VD ) + RI 1 ( + ) 1− k k k
(7.19)
The output current is
I1 =
© 2003 by CRC Press LLC
V2 − (V1 + VS + VD )
1− k k
1− k k + R( ) 1− k k
(7.20)
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The minimum conduction duty k corresponding to I1 = 0 is V1 + VS + VD V1 + V2 + VS + VD
kmin =
(7.21)
The power transfer efficiency is
ηB =
7.4.2
PO V1 I 1 = = PI V2 I 2
1 VS + VD RI 1 1− k 2 1+ [1 + ( ) ] + V1 V1 k
(7.22)
Variations of Currents and Voltages
Because the voltage across the inductor L2 is (V2 – RI2) during switchon and (V1 – V2 + VC + RI2) during switchoff, the average voltage across capacitor C is kT (V2 − RI 2 ) = (V1 − V2 + VC + RI 2 )(1 − k )T Hence VC =
V2 V 1 k − V1 − RI = 2 − V1 − RI 1 1− k 1− k 2 1− k (1 − k )2
(7.23)
The peaktopeak variation of capacitor voltage vC is ∆vC =
Q− kTI 1 kI 1 = = C C fC
The variation ratio of capacitor voltage vC is ρ=
∆vC / 2 = VC
kI 1 V2 k 2 fC[ ] − V1 − RI 1 1− k (1 − k )2
The peaktopeak variation of current iL1 is ∆iL1 = © 2003 by CRC Press LLC
VC − VS − RI 1 V − VS − RI 2 kT = 2 kT L1 L1
(7.24)
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The variation ratio of inductor current iL1 is ξ1 =
V − VS − RI 2 ∆iL1 / 2 =k 2 2 fL1 I 1 I L1
(7.25)
The peaktopeak variation of inductor current iL2 is ∆iL 2 =
V2 − VS − RI 2 kT L2
The variation ratio of inductor current iL2 is ξ2 =
V − VS − RI 2 ∆iL 2 / 2 =k 2 2 fL2 I 2 I L2
(7.26)
The freewheeling diode’s current iD1 during switch off is: iD1 = iL1 + iL2. Its peaktopeak variation is
∆iD 2 = ∆iL1 + ∆iL 2 =
V2 − VS − RI 2 kT L
where L = L1L2 /( L1+ L2). The variation ratio of diode current iD1 is ζ D1 =
7.4.3
V − VS − RI 2 V − VS − RI 2 ∆iD 2 / 2 =k 2 = k2 2 I L1 + I L 2 2 fL( I 1 + I 2 ) 2 fLI 2
(7.27)
Discontinuous Region
If the diode current becomes zero before S2 is switched on again, the converter works in discontinuous region. The condition is: ζD1 = 1, i.e., k2 =
2 fLI 2 V2 − VS − RI 2
(7.28)
From Equations (7.21) and (7.28) the boundary between continuous and discontinuous regions is shown in Figure 7.7. Particularly, since conduction duty k is greater than kmin and the current is high, the converter usually works in the continuous region. © 2003 by CRC Press LLC
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I2
Continuous Region
0
Discontinuous Region
Kmin
1
k
FIGURE 7.7 Boundary between continuous and discontinuous regions of Mode B.
7.5
Mode C (Quadrant III Operation)
As shown in Figure 7.4a and b the voltage across capacitor C increases during switchoff, and decreases during switch on. Capacitor C acts as the primary means of storing and transferring energy from the input source to the output load via the pump inductor L1. Assuming capacitor C to be sufficiently large, the variation of the voltage across capacitor C from its average value VC can be neglected in steady state, i.e., vC(t) ≈ VC, even though it stores and transfers energy from the input to the output.
7.5.1
Circuit Description
The equivalent circuits in switchon and off states are shown in Figure 7.4a and b. When switch S1 is on, the source current i1 = iL1. Inductor L1 absorbs energy from the source. In the mean time inductor L2 absorbs energy from capacitor C, current iL1 increases and i2 decreases. When switch S1 is off, source current i1 = 0. Current iL1 flows through the freewheeling diode D2 to charge capacitor C and increase current i2. Inductor L1 transfers its stored energy to capacitor C and the load V2. Current iL1 decreases and i2 increases. In order to analyze the circuit working procession, these waveforms with enlarged variations are shown in Figure 7.4c. Actually, the variations of currents iL1 and iL2 are small so that iL1 ≈ IL1 and iL2 ≈ IL2 = I2. Since the capacitor current iC–on is equal to I2 during switchon, iC–off should be: iC −off = © 2003 by CRC Press LLC
k I 1− k 2
(7.29)
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Inductor current iL1 during switchoff is iL1 = I 2 + iC −off = (1 +
1 k )I = I 1− k 2 1− k 2
(7.30)
The source average current I1 is I 1 = kiL1 =
k I 1− k 2
or
I L1 =
1 I k 1
(7.31)
The input and output powers are PI = V1 I 1 and PO = V2 I 2 The power losses are VSI1 — RIL12 — VDI1 — RIL22 —
Switch power loss Power loss across inductor L1 Diode power loss Power loss across inductor L2
The total power losses are Ploss = VS I 1 + VD I 1 + R[(
I1 2 ) + I22 ] k
(7.32)
Since PI = PO + Ploss hence V1 I 1 = V2 I 2 + (VS + VD )I 1 + R[(
I1 2 ) + I22 ] k
(7.33)
or V1 = V2 © 2003 by CRC Press LLC
1− k 1 1− k + (VS + VD ) + RI 2 [ + ] k k(1 − k ) k
(7.34)
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The output current is
I2 =
1− k k 1 1− k R[ + ] k(1 − k ) k
V1 − VS − VD − V2
(7.35)
The minimum conduction duty k corresponding to I2 = 0 is kmin =
V2 V1 + V2 − VS − VD
(7.36)
The power transfer efficiency is ηC =
7.5.2
PO V2 I 2 = = PI V1 I 1
1 VS + VD k RI 1 2 1+ ) ] + 2 [1 + ( 1 − k V2 1− k V2
(7.37)
Variations of Currents and Voltages
Because the voltage across the inductor L1 is (V1 – RIL1) during switchon and (VC + RIL1) during switchoff, the average voltage across capacitor C is kT (V1 − RI L1 ) = (VC + RI L1 )(1 − k )T Hence VC =
1 1 k k V1 − RI L1 = V1 − RI 2 1− k 1− k 1− k (1 − k )2
(7.38)
The peaktopeak variation of capacitor voltage vC is ∆vC =
kTI 2 kI 2 = C fC
The variation ratio of capacitor voltage vC is ρ=
© 2003 by CRC Press LLC
∆vC / 2 = VC
kI 2 RI 2 k 2 fC[ ] V1 − 1− k (1 − k )2
(7.39)
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The peaktopeak variation of inductor current iL1 is ∆iL1 =
V1 − VS − RI 1 kT L1
The variation ratio of inductor current iL1 is ξ1 =
V − VS − RI 1 ∆iL1 / 2 =k 1 2 fL1 I 1 I L1
(7.40)
Diode’s current iD2 during switchoff is: iD2 = iL1. Its peaktopeak variation is ∆iD 2 = ∆iL1 =
V1 − VS − RI 1 kT L1
and the variation ratio of inductor current iD2 is ζD2 = ξ1 =
V − VS − RI 1 ∆iD 2 / 2 =k 1 I L1 2 fL1 I 1
(7.40a)
Since voltage vC varies very little, the peaktopeak variation of inductor current iLO is calculated by the area A of a triangle with width T/2 and height ∆vC/2: ∆iL2 =
k A 1 T kTI 2 I = = L2 2 2 2CL2 8 f 2 CL2 2
The variation ratio of inductor current iL2 is ξ2 =
7.5.3
∆iL 2 / 2 k = 16 f 2 CL2 I2
(7.41)
Discontinuous Region
If the diode current becomes zero before S1 is switched on again, the converter works in discontinuous region. The condition id ζD2 = 1, i.e., k=
© 2003 by CRC Press LLC
2 fL1 I 1 V1 − VS − RI 1
(7.42)
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I1
Continuous Region Discontinuous Region 0
Kmin
1
k
FIGURE 7.8 Boundary between continuous and discontinuous regions of Mode C.
From Equations (7.36) and (7.42) the boundary between continuous and discontinuous regions is shown in Figure 7.8. Particularly, since conduction duty k is greater than kmin and the current is high, the converter usually works in the continuous region.
7.6
Mode D (Quadrant IV Operation)
As shown in Figure 7.5a and b the voltage across capacitor C decreases during switchon, and increases during switch off. Capacitor C acts as the primary means of storing and transferring energy from the load battery to the source via inductor L1. Assuming capacitor C to be sufficiently large, the variation of the voltage across capacitor C from its average value VC can be neglected in steady state, i.e., vC(t) ≈ VC, even though it stores and transfers energy from the load V2 to the source V1. 7.6.1
Circuit Description
When switch S2 is on, source current i1 = 0. Current iL1 flows through the switch S2, then capacitor C and load battery V2. It increases and iL1 = iC–on + i2, when switch S2 is off. The source current is i1 = iL1. The freewheeling diode D1 is conducted. Current iL1 decreases. Inductor L1 transfers its stored energy to source V1. In order to analyze the circuit working procession, these waveforms with enlarged variations are shown in Figure 7.5c. The equivalent circuits in switchon and off states are shown in Figure 7.5a and b. Actually, the variations of currents iL1 and iL2 are small so that iL1 ≈ IL1 and iL2 ≈ I2. © 2003 by CRC Press LLC
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Since the capacitor current iC–off is equal to I2 during switchoff, iC–on should be: iC −on =
1− k I k 2
(7.43)
Inductor current iL1 during switchon is iL1 = I 2 + iC −on = (1 +
1− k 1 )I 2 = I 2 k k
(7.44)
The source average current I1 is I 1 = (1 − k )iL1 =
1− k I k 2
or I L1 =
1 I 1− k 1
(7.45)
The input and output powers are PI = V2 I 2 and PO = V1 I 1 The power losses are VSI1 RIL12 VDI1 RIL22
— — — —
Switch power loss Power loss across inductor L1 Diode power loss Power loss across inductor L2
The total power losses are Ploss = VS I 1 + VD I 1 + R( I L12 + I 2 2 )
(7.46)
Since PI = PO + Ploss hence V2 I 2 = V1 I 1 + (VS + VD )I 1 + R( I L12 + I 2 2 ) © 2003 by CRC Press LLC
(7.47)
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413
or V2 =
1− k 1 k (V1 + VS + VD ) + RI 1[ + ] k k(1 − k ) 1 − k
(7.48)
The output current is
I1 =
V2 − (V1 + VS + VD )
1− k k
1 k R[ + ] k(1 − k ) 1 − k
(7.49)
The minimum conduction duty k corresponding to I1 = 0 is kmin =
V1 + VS + VD V1 + V2 + VS + VD
(7.50)
The power transfer efficiency is ηD =
7.6.2
PO V1 I 1 = = PI V2 I 2
V + VD RI 1 1+ S + V1 V1
1 2 1 k + 2 1− k (1 − k )
(7.51)
Variations of Currents and Voltages
Because the voltage across the inductor L1 is (VC – RIL1) during switchon and (V1 + RIL1) during switchoff, the average voltage across capacitor C is kT (VC − RI L1 ) = (V1 + RI L1 ) (1 − k ) T Hence VC =
1− k 1 1− k 1 V1 + RI L1 = V1 + RI 1 k k k k(1 − k )
The peaktopeak variation of capacitor voltage vC is ∆vC =
(1 − k )TI 2 kI 1 = C fC
The variation ratio of capacitor voltage vC is © 2003 by CRC Press LLC
(7.52)
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Advanced DC/DC Converters
ρ=
∆vC / 2 = VC
kI 1 RI 1 1− k V1 + 2 fC[ ] k k(1 − k )
(7.53)
The peaktopeak variation of current iL1 is ∆iL1 = kT
VC − VS − RI 1 V − VS − RI 2 = (1 − k ) 2 L1 fL1
The variation ratio of inductor current iL1 is ξ1 =
V − VS − RI 2 ∆iL1 / 2 = (1 − k ) 2 2 fL1 I 1 I L1
(7.54)
Current iD1 during switchoff is iD1 = iL1. Its peaktopeak variation is ΛiD1 = ∆iL1 = (1 − k )
VC − VS − RI 2 fL1
and the variation ratio of inductor current iD1 is ζ D1 = ξ 1 =
V − VS − RI 2 ∆iD1 / 2 =k 2 I L1 2 fL1 I 2
(7.54a)
Since voltage vC varies very little, the peaktopeak variation of inductor current iLO is calculated by the area B of a triangle with width T/2 and height ∆vC/2: ∆iL2 =
k B 1 T kTI 1 = = I L2 2 2 2CL2 8 f 2 CL2 1
The variation ratio of inductor current iL2 is ξ2 =
7.6.3
∆iL 2 / 2 1− k = 16 f 2 CL2 I2
(7.55)
Discontinuous Region
If the diode current becomes zero before S2 is switched on again, the converter works in discontinuous region. The condition id ζD1 = 1, i.e., © 2003 by CRC Press LLC
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415
I2
Continuous Region
0
Discontinuous Region
Kmin
1
k
FIGURE 7.9 Boundary between continuous and discontinuous regions of Mode D.
k=
2 fL1 I 2 V2 − VS − RI 2
(7.56)
From Equations (7.50) and (7.56) the boundary between continuous and discontinuous regions is shown in Figure 7.9. Particularly, since conduction duty k is greater than kmin and the current is high, the converter usually works in the continuous region.
7.7
Simulation Results
In order to verify the above analysis and calculation formulae, and the characteristics of this converter, we applied the PSpice simulation methodology to obtain the results shown in Figure 7.10 to Figure 7.13. The first plot is current iL1, the second plot is current iL2, and the third plot is voltage vC. The repeating frequency f = 50 Hz. The conduction duty cycle k = 0.4 for modes A and C, 0.8 for modes B and D. These results agree with the analysis and calculations in the previous sections.
7.8
Experimental Results
In order to verify the above analysis and calculation formulae, and the characteristics of this converter, we collected the following experimental results. The experimental testing conditions are © 2003 by CRC Press LLC
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Advanced DC/DC Converters 31A
(19.968ms, 30.811) (19.980ms, 30.182)
30A I(L1) 46A
(19.980ms, 43.813)
44A (19.968ms, 44.447) 42A I(L2) 40V
(19.980m, 24.119)
(19.968m, 6.1142) SEL>> 0V 19.96ms
19.97ms
V(C1:2, C1:1)
19.98ms
19.99ms
20.00ms
Time
FIGURE 7.10 Simulation results of Mode A.
7.0A (19.976ms, 6.9185) (19.980ms, 6.5604)
6.5A I(L1) 29.0A
(19.976ms, 28.955) (19.980ms, 28.599)
28.5A I(L2) 20V
(19.980m, 14.167)
SEL>> 0V 19.97ms 19.96ms V(C1:2, C1:1)
(19.976m, 8.7191) 19.98ms
19.99ms
20.00ms
Time
FIGURE 7.11 Simulation results of Mode B.
V1 = 42 V, V2 = 14 V, VS = 0.3 V, VD = 0.5 V, R = 0.05 Ω, L1 = L2 = L = LO = 0.5 mH, C = 20 µF, f = 50 kHz The experimental results corresponding to various conduction duty k are shown in Table 7.2 for the Mode A, Table 7.3 for the Mode B, Table 7.4 for the Mode C and Table 7.5 for the Mode D. © 2003 by CRC Press LLC
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417
44A (44.260m, 42.816) (44.268m, 43.430) 42A 24.40616352A
I(L1)
(44.253m, 25.431) (44.263m, 25.479)
22.69750393V
I(L2) (44.268m, 11.326) (44.260m, 21.727)
SEL>> 18.31446541V 44.244ms
44.250ms
44.260ms
44.270ms
44.280ms
V(C1:1, C1:2)
FIGURE 7.12 Simulation results of Mode C.
20A (19.090m, 18.157) (19.100m, 17.810) 10A 0A
I(L1)
19.626A (19.068m, 14.0041) (19.099m, 17.618)
19.600A I(U2) 15V
(19.096m, 11.172) (19.100m, 13.874) SEL>> 10V 19.070ms
19.090ms
19.100ms
19.110ms
19.115ms
V(C1:1, C1:2)
FIGURE 7.13 Simulation results of Mode D.
When compared with the analysis and calculations, the experimental results are reasonable. From these data we can see that the function of this converter has been verified. © 2003 by CRC Press LLC
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Advanced DC/DC Converters TABLE 7.2 The Experimental Results for Mode A (Quadrant QI) with kmin = 0.2536 k 0.26 0.28 0.30 0.32 0.34
I1 (A)
I2 (A)
VC (V)
PI (W)
PO (W)
ηA (%)
3.0 13.7 26.5 41.5 58.8
8.5 35.1 61.8 88.2 114.2
14.28 15.07 15.77 16.33 18.77
126 575 1113 1743 2470
119 491 865 1235 1599
94.4 85.4 77.7 70.8 64.7
TABLE 7.3 The Experimental Results for Mode B (Quadrant QII) with kmin = 0.7535 k
I2 (A)
I1 (A)
VC (V)
PI (W)
PO (W)
ηB
0.76 0.78 0.80 0.82 0.84
8.81 35.72 62.0 87.7 112.9
2.78 10.08 15.5 19.3 21.5
13.70 12.72 11.67 10.57 9.43
123 500 870 1230 1580
117 423 652 810 903
94.9 84.6 75.0 65.9 57.1
TABLE 7.4 The Experimental Results for Mode C (Quadrant QIII) with kmin = 0.2536 k 0.26 0.28 0.30 0.32 0.34
I1 (A)
I2 (A)
VC (V)
PI (W)
PO (W)
ηC (%)
3.0 13.7 26.5 41.5 58.8
8.5 35.1 61.8 88.2 114.2
14.28 15.07 15.77 16.33 18.77
126 575 1113 1743 2470
119 491 865 1235 1599
94.4 85.4 77.7 70.8 64.7
TABLE 7.5 The Experimental Results for Mode D (Quadrant QIV) with kmin = 0.7535 k
I2 (A)
I1 (A)
VC (V)
PI (W)
PO (W)
ηD
0.76 0.78 0.80 0.82 0.84
8.81 35.72 62.0 87.7 112.9
2.78 10.08 15.5 19.3 21.5
13.70 12.72 11.67 10.57 9.43
123 500 870 1230 1580
117 423 652 810 903
94.9 84.6 75.0 65.9 57.1
© 2003 by CRC Press LLC
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7.9 7.9.1
419
Discussion DiscontinuousConduction Mode
Usually, the industrial applications require that the DCDC converters work in continuous mode. However, it is irresistible that DCDC converter works in discontinuous mode sometimes. The analysis in Sections 3.3, 4.3, 5.3, and 6.3 shows that during switchoff if current iD2 and iD1 becomes zero before next period switch on, the state is called discontinuous mode. The following factors affect the diode current to become discontinuous: 1. Switching frequency f is too low 2. Conduction duty cycle k is too small and close kmin 3. Inductor L is too small
7.9.2
Comparison with the DoubleOutput LuoConverter
The analysis of the double output Luoconverter is based on ideal components. For example, all voltage drops are zero and inductor resistance is zero, i.e., VS = VD = 0 and R = 0. If we use these conditions the corresponding formulae will return back to those forms for double output Luoconverter. From Equation (7.5): k=
V2 V1 + V2
or V2 =
k V 1− k 1
I2 =
1− k I k 1
k=
V1 V1 + V2
and
From Equation (7.19):
© 2003 by CRC Press LLC
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Advanced DC/DC Converters
or V1 =
k V 1− k 2
I1 =
1− k I k 2
k=
V2 V1 + V2
and
From Equation (7.34):
or V2 =
k V 1− k 1
I2 =
1− k I k 1
k=
V1 V1 + V2
V1 =
k V 1− k 2
I1 =
1− k I k 2
and
From Equation (7.48):
or
and
because the power losses are zero, the power transfer efficiency is 100%.
© 2003 by CRC Press LLC
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7.9.3
Conduction Duty k
Since the source and load voltages are fixed, conduction duty k does not affect the voltage transfer gain. We have considered the power losses on the switches, diodes, and inductors. Therefore, the conduction duty k affects the output and input currents and power transfer efficiency. Usually, large k causes large currents and power losses. For each mode there is a minimum conduction duty kmin. When k = kmin the input and output currents are zero. In order to limit the overcurrent, the values of the conduction duty k are usually selected in the range of kmin < k < kmin + 0.12
7.9.4
Switching Frequency f
In this paper the repeating frequency f = 50 kHz was selected. Actually, switching frequency f can be selected in the range between 10 kHz and 500 kHz. Usually, the higher the frequency, the lower the current ripples.
Bibliography Luo, F.L. and Ye, H., Fourquadrant operating Luoconverter, Power Supply Technologies and Applications, Xi’an, China, 3, 82, 2000. Luo, F.L. and Ye, H., Twoquadrant Luoconverter in forward operating, Power Supply World, Guangzhou, China, 2, 62, 2000. Luo, F.L. and Ye, H., Twoquadrant Luoconverter in reverse operating, Power Supply World, Guangzhou, China, 3, 96, 2000. Luo, F.L., Ye, H., and Rashid, M.H., Fourquadrant DC/DC zerocurrentswitching quasiresonant Luoconverter, Power Supply Technologies and Applications, Xi’an, China, 5, 278, 1999. Luo, F.L., Ye, H., and Rashid, M.H., Multiple quadrant operation Luoconverters, IEE Proceedings on Electric Power Applications, 149, 9, 2002. Wang, J., Dunford, W.G., and Mauch, K., Some novel fourquadrant DCDC converters, in Proceedings of IEEEPESC’98, Fukuoka, Japan, 1998, p. 1775.
© 2003 by CRC Press LLC
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8 Switched Component Converters
Classic DC/DC converters consist of inductors and capacitors. They are large because of the mixture of inductors and capacitors. On engineering design experience, a circuit constructed by only inductor or capacitor may be small in size. In order to reduce the converter size and enlarge the power density, a third generation of DC/DC converters have been developed, and they are called switched component converters. Particularly, they are switchedcapacitor (SC) DC/DC converters and switchedinductor (SI) DC/DC converters. The switched capacitor DC/DC converter is a new prototype of DC/DC conversion technology. Since a switched capacitor can be integrated into a power IC chip, these converters are small and have a high power density. However, most of the published papers avoid discussing the efficiency because most switched capacitor converters possess low power transfer efficiency. This section introduces a switched capacitor twoquadrant DC/ DC converter implementing voltage lift and current amplification techniques with high efficiency, high power density, and low electromagnetic interference (EMI). Experimental results verified the advantages of this converter. Fourquadrant operation is required by industrial applications. SC converters can perform fourquadrant operations as well. SC converters always perform in pushpull state, and the control circuitry is complex. A large number of capacitors are required, especially in the case of large differences between input and output voltages. Switched inductor DC/DC converters are a prototype of DC/DC conversion technology from SC converters. Switched inductor DC/DC converters have advantages such as simple structure, simple control circuitry, high efficiency, large power, and high power density. Usually, one inductor is required for a SI DC/DC converter. Since it consists of only an inductor, it is small. This converter has advantages: no matter how many quadrant operations and how large the difference between input and output voltages, only one inductor is usually employed in one DC/DC SI converter.
© 2003 by CRC Press LLC
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8.1
Advanced DC/DC Converters
Introduction
A new type DC/DC converter consisting of capacitors only was developed around the 1980s. Since it can be integrated into a power semiconductor IC chip, it has attracted much attention in recent years. However, most of the converters introduced in the literature perform singlequadrant operations. Some of them work in the flipflop status, and their control circuit and topologies are very complex. A newly designed DC/DC converter, twoquadrant DC/DC converter with switched capacitors was developed from the prototype of the authors’ research work. This converter implements the voltagelift and currentamplification technique, so that it reaches high power density and high power transfer efficiency. In order to successfully reduce electromagnetic interference (EMI), a lower switching frequency f = 5 kHz was applied in this converter. It can perform stepdown and stepup twoquadrant positive to positive DCDC voltage conversion with high power density, low EMI, and cheap topology in simple structure. The conduction duty k is usually selected to be k = 0.5 in most of the papers in the literature. We have carefully analyzed this problem, and verified its reasonableness. Multiplequadrant operation is required by industrial applications. Switchedcapacitor multiple quadrant converters and switched inductor multiple quadrant converters will be introduced in this chapter as well.
8.2
A TwoQuadrant SC DC/DC Converter
A twoquadrant SC converter is shown in Figure 8.1. It consists of nine switches, seven diodes, and three capacitors. The high voltage (HV) source and low voltage (LV) load are usually constant voltages. The load can be a battery or motor back electromotive force (EMF). For example, the source voltage is 48 V and load voltage is 14 V. There are two modes of operation: 1. Mode A (quadrant I): electrical energy is transferred from HV side to LV side; 2. Mode B (quadrant II): electrical energy is transferred from LV side to HV side.
8.2.1
Circuit Description
Each mode has two states: on and off. Usually, each state operates in different conduction duty k. The switching period is T where T = 1/f. The parasitic © 2003 by CRC Press LLC
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Switched Component Converters S1
S2
D1
iH
425
D2
+ +
C1
VH
–
S3
D3
D4
S4
S6
C3
S5
C2
–
iL
+
+ D5
D6
–
S7
+
VL
–
– S8
D8
S9
D9
S10
D10
FIGURE 8.1 Twoquadrant DC/DC switchedcapacitor converter.
resistance of all switches is rS, the equivalent resistance of all capacitors is rC and the equivalent voltage drop of all diodes is VD. Usually select the three capacitors have same capacitance C1= C2= C3 = C. Some reference data are useful: rS = 0.03 Ω, rC = 0.02 Ω, and VD = 0.5 V, f = 5 kHz, and C = 5000 µF. 8.2.1.1 Mode A For mode A, stateon is shown in Figure 8.2a: switches S1 and S10 are closed and diodes D5 and D5 are conducted. Other switches and diodes are open. In this case capacitors C 1 , C 2 , and C 3 are charged via the circuit VH–S1–C1–D5–C2–D6–C3–S10, and the voltage across capacitors C1, C2, and C3 is increasing. The equivalent circuit resistance is RAN = (2rS + 3rC) = 0.12 Ω, and the voltage deduction is 2VD = 1 V. Stateoff is shown in Figure 8.2b: switches S2, S3, and S4 are closed and diodes D8, D9, and D9 are conducted. Other switches and diodes are open. In this case capacitor C1 (C2 and C3) is discharged via the circuit S2(S3 and S4)–VL–D8(D9 and D10)–C1(C2 and C3), and the voltage across capacitor C1 (C2 and C3) is decreasing. The equivalent circuit resistance is RAF = rS + rC = 0.05 Ω, and the voltage deduction is VD = 0.5 V. Capacitors C1, C2, and C3 transfer the energy from the source to the load. The voltage waveform across capacitor C1 is shown in Figure 8.2c. Mode A uses the currentamplification technique. All three capacitors are charged in series during stateon. The input current flows through three capacitors and the charges accumulated on the three capacitors should be the same. These three capacitors are discharged in parallel during stateoff. Therefore, the output current is amplified by three. 8.2.1.2
Mode B
For mode B, stateon is shown in Figure 8.3a: switches S8, S9, and S10 are closed and diodes D2, D3, and D4 are conducted. Other switches and diodes are off. In this case all three capacitors are charged via each circuit VL–D2(and D3, D4)–C1(and C2, C3)–S8(and S9, S10), and the voltage across three capacitors © 2003 by CRC Press LLC
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Advanced DC/DC Converters S1 , S10 ,D 5 , D 6 On S1
C1
+ –
D5
+
+
C2
–
VH
D6
–
C3
i C1
S2 , S 3 , S4 , D 8 ,D 9 , D 10 On
i C1 S3
S2 +
+ –
i C2
i C3
S4
+
VL
VH
–
–
+ C1
+
C2
– D8
+ C3
+
VL
–
–
–
D9
D 10
S10
(a) Switchon
(b) Switchoff
vC1 V C1
kT
T
kT
T
t
i C1
t
(c) Some voltage and current waveforms FIGURE 8.2 Mode A operation.
is increasing. The equivalent circuit resistance is RBN = rS + rC and the voltage deduction is VD. Stateoff is shown in Figure 8.3b: switches S5, S6, and S7 are closed and diode D1 is on. Other switches and diodes are open. In this case all capacitors are discharged via the circuit VL–S7–C3–S6–C2–S5–C1–D1–VH, and the voltage across all capacitors is decreasing. The equivalent circuit resistance is RBF = 3 (rS + rC) and the voltage deduction is VD. The voltage waveform across capacitor C1 is shown in Figure 8.3c. Mode B implements the voltagelift technique. All three capacitors are charged in parallel during stateon. The input voltage is applied to the three © 2003 by CRC Press LLC
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427
S7, S6, S5, D1 On
S8, S9, S10, D2, D3, D4 On D4
D3
+ VL –
+ C3
–
S10
C2 S9
S7
D2 +
+
+
C1
–
–i
C3 S6 C2 i C1
+
VH
VL
–
–
C1
S8
S5 C1 D1 + VH –
(b) Switchoff
(a) Switchon vC1
VC1
kT
T
kT
T
t
i C1
t
(c) Some voltage and current wave forms FIGURE 8.3 Mode B operation.
capacitors symmetrically, so that the voltages across these three capacitors should be the same. They are discharged in series during stateoff. Therefore, the output voltage is lifted by three. Summary. In this circuit we have RAN = 0.12 Ω, RAF = 0.05 Ω, RBN = 0.05 Ω, RBF = 0.15 Ω. The switch status is shown in Table 8.1. 8.2.2
Mode A (Quadrant I Operation)
Refer to Figure 8.2a and b the voltage across capacitor C1 increases during switchon, and decreases during switchoff according to the integration of the current iC1. If the switching period T is small enough (comparing with the circuit time constant) we can use average current to replace its instantaneous value for the integration. Therefore the voltage across capacitor C1 is
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Advanced DC/DC Converters TABLE 8.1 Switch Status Switches and Diodes S1 D1 S2,S3,S4 D2,D3,D4 S5,S6,S7 D5,D6 S8,S9 S10 D8,D9,D10
Mode A Stateon Stateoff
Mode B Stateon Stateoff
ON ON ON ON ON ON ON ON
ON ON
Note: The blank status means off.
t t 1 v C 1 ( 0) + iC1 (t)dt ≈ vC1 (0) + i H C C 0 v C 1 (t ) = t t − kT 1 vC1 ( kT ) + C iC1 (t)dt ≈ vC1 ( kT ) − C iL kT
∫
∫
0 ≤ t < kT (8.1) kT ≤ t < T
The current flowing through the three capacitors is an exponential function. If the switching period T is small enough (comparing with the circuit time constant) we can use their initial values while ignoring their variations. Therefore the current flowing through capacitor C1 is iC 1 ( t ) = V − 3VC1 − 2VD VH − 3vC1 (0) − 2VD = iH (1 − e − t/RAN C ) ≈ H RAN RAN − vC1 ( kT ) − VL − VD − t/RAFC ≈ − VC1 − VL − VD = − e iL RAF RAF
0 ≤ t < kT
(8.2)
kT ≤ t < T
Therefore, iH = 3
1− k i k L
(8.3)
Where i H is the average input current in the switchon period kT that is equal to IH/k, and iL is the average output current in the switchoff period (1 – k)T that is equal to IL/3(1 – k). Therefore, we have 3IH = IL. The variation of the voltage across capacitor C1 is © 2003 by CRC Press LLC
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Switched Component Converters
∆vC1 =
1 C
kT
∫i
C1
(t)dt =
0
429
k(VH − 3VC1 − 2VD ) kT i = C H fCRAN
0 ≤ t < kT
or
∆vC1 =
1 C
T
∫
iC1 (t)dt =
kT
(1 − k )(VC1 − VL − VD ) (1 − k )T iL = C fCRAF
kT ≤ t < (1 – k)T
After calculation, k(VH − 2VD ) + 2.4(1 − k )(VL + VD ) 2.4 + 0.6 k
(8.4)
k(VH − 3VC1 − 2VD ) 2.4 k(1 − k )(VH − 3VL − 5VD ) = fCRAN (2.4 + 0.6 k ) fCRAN
(8.5)
VC1 = Hence ∆vC1 = We have
vC1 (0) = VC1 −
∆vC1 2
vC1 ( kT ) = VC1 +
and
∆vC1 2
The average output current is
IL =
3 T
T
∫i
C1
(t)dt ≈ 3(1 − k )
kT
VC1 − VL − VD RAF
(8.6)
The average input current is
IH = Output power
1 T
kT
∫ 0
iC1 (t)dt ≈ k
VH − 3VC1 − 2VD RAN
(8.7)
VC1 − VL − VD RAF
(8.8)
is PO = VL I L = 3(1 − k )VL
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Advanced DC/DC Converters TABLE 8.2 The Calculation Results for Mode A k
VC1 (V)
∆vC1 (V)
IH (A)
IL (A)
PI (W)
PO (W)
ηA
0.4 0.5 0.6
15.03 15.15 15.26
0.255 0.259 0.243
6.36 6.48 6.08
19.08 19.44 18.24
305.3 311.0 291.8
267.1 272.2 255.4
0.875 0.875 0.875
Input power is PI = VH I H = kVH
VH − 3VC1 − VD RAN
(8.9)
The transfer efficiency is ηA =
PO 1 − k 3VL VC1 − VL − VD RAN 3VL = = PI k VH VH − 3VC1 − VD RAF VH
(8.10)
If f = 5 kHz, VH = 48 V and VL = 14 V, and all C = 5000 µF, for the various k values, the data are shown in Table 8.2. From this analysis, it can be seen that the transfer efficiency only relies on the ratio of the source and load voltages, and it is independent upon R, C, f, and k. The conduction duty k does not affect the power transfer efficiency, it affects the input and output power in a small region. The maximum output power corresponds at k = 0.5.
8.2.3
Mode B (Quadrant II Operation)
Refer to Figure 8.3a and b, the voltage across capacitor C1 increases during switchon, and decreases during switchoff according to the integration of the current iC1. If the switching period T is small enough we can use average current to replace its instantaneous value for the integration. Therefore the voltage across capacitor C1 is t t 1 v C 1 ( 0) + iC1 (t)dt ≈ vC1 (0) + iL C C 0 v C 1 (t ) = t 1 t − kT vC1 ( kT ) + C iC1 (t)dt ≈ vC1 ( kT ) − C i H kT
∫
∫
0 ≤ t < kT (8.11) kT ≤ t < T
The current flowing through the three capacitors is an exponential function. If the switching period T is small enough we can use their initial values and ignore their variations. Therefore the current flowing through capacitor C1 is © 2003 by CRC Press LLC
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431
iC 1 ( t ) = VL − vC1 (0) − VD V − VC1 − VD (1 − e − t/RBN C ) ≈ L = iL RBN RBN − 3vC1 ( kT ) + VL − VH − VD − t/RBFC ≈ − 3VC1 + VL − VH − VD = − e iH RBF RBF
0 ≤ t < kT
(8.12)
kT ≤ t < T
Therefore, iL =
1− k i k H
(8.13)
Where iL is the average input current in the switchon period kT that is equal to IL/k, and i H is the average output current in the switchoff period (1 – k)T that is equal to IH/3(1 – k). Therefore, we have 4IH = IL. The variation of the voltage across capacitor C is
∆vC1 =
1 C
kT
∫i
C1
(t)dt =
0
k(VL − VC1 − VD ) kT i = C L fCRBN
0 ≤ t < kT
or
∆vC1
1 = C
T
∫i
C1
(t)dt =
kT
(1 − k )(3VC + VL − VH − VD ) (1 − k )T iH = C fCRBF
kT ≤ t < (1 – k)T
After calculation, VC1 = k(VL − VD ) +
1− k (VH − VL + VD ) 3
(8.14)
Hence
∆vC1 =
vC1 (0) = VC1 −
© 2003 by CRC Press LLC
k(1 − k )[4(VL − VD ) − VH ] fCRBN
∆vC1 2
and
vC1 ( kT ) = VC1 +
(8.15)
∆vC1 2
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Advanced DC/DC Converters TABLE 8.3 The Calculation Results for Mode B k
VC1 (V)
∆vC1 (V)
IH (A)
IL (A)
PI (W)
PO (W)
ηB
12.3 12.5 12.7
1.152 1.2 1.152
9.6 10 9.6
38.4 40 38.4
537.6 560 537.6
460.8 480 460.8
0.857 0.857 0.857
0.4 0.5 0.6
The average input current is kT
IL =
1 [3 iC1 (t)dt + T
∫ 0
T
∫i
C1
(t)dt ≈ 3k
kT
VL − VC1 − VD RBN
(8.16)
3V + VL − VH − VD + (1 − k ) C1 RBF The average output current is 1 IH = T
T
∫i
C1
(t)dt ≈ (1 − k )
kT
3VC1 + VL − VH − VD RBF
(8.17)
Input power is PI = VL I L = VL [3k
VL − VC − VD 3V + VL − VH − VD + (1 − k ) C ] RBN RBF
(8.18)
Output power is PO = VH I H = VH (1 − k )
3VC + VL − VH − VD RBF
(8.19)
The transfer efficiency is ηB =
PO V = H PI 4VL
(8.20)
If f = 5 kHz, VH = 48 V and VL = 14 V, and all C = 5000 µF, for the various k values the data are shown in Table 8.3. From this analysis, it can be seen that the transfer efficiency only relies on the ratio of the source and load voltages, and it is independent of R, C, f, and k. The conduction duty k does not affect the power transfer efficiency. It affects the input and output power in a small region. The maximum output power corresponds at k = 0.5. © 2003 by CRC Press LLC
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433
TABLE 8.4 Experimental Results Mode
IL(A)
IH(A)
VC1(V)
PI(W)
PO(W)
η(%)
A B Average
18.9 40 29.45
6.4 9.8 8.1
15.15 12.5 13.8
307 560 434
264 470 367
86 84 85
8.2.4
P
(W)
286 515 400
Volume (in3)
PD (W/in3)
24 24 24
11.9 21.5 16.7
Experimental Results
A twoquadrant DC/DC converter operates the conversion between 14 V and 48 VDC. The converter has been developed and is introduced in this paper. This converter is a twoquadrant DC/DC converter with switchedcapacitors for the dualdirection conversion between 14 V and 48 VDC. A testing rig was constructed and consists of a modern car battery 14 VDC as a load and a 48 VDC source power supply. The testing conditions are Switching frequency: f Conduction duty: k High and low voltages: VH All capacitance: C
= = = =
5 kHz 0.5 48 V and VL = 14 V 5000 µF
The experimental results are shown in Table 8.4. The average power transfer efficiency is 85%. The total average power density (PD) is 16.7 W/in3. This figure is much higher than the PD of classical converters, which are usually less than 5 W/in3. Since the switching frequency is low, the electromagnetic interference (EMI) is weak.
8.2.5
Discussion
8.2.5.1 Efficiency From theoretical analysis and experimental results we find that the power transfer efficiency of switched capacitor converters is limited. The reason to spoil the power transfer efficiency is the power consumption on the circuit parasitic resistors and the diodes. In steady state, the increase and decrease of the charge across a capacitor should be equal to each other. Therefore, its average input current II must be equal to the average output current IO. If only one capacitor is applied in a switched capacitor DC/DC converter, its power transfer efficiency is η= © 2003 by CRC Press LLC
PO VO I O VO = = PI VI I I VI
(8.21)
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Advanced DC/DC Converters
S1
S2
D1
D2
D3
S3
+
+
–
S8
D5 S 5
D8
– D 6
S9
S4
C3
C2
C1 V IN
D4
S6
D9
–S
S 10
i2
+ 7
V2
D 10
FIGURE 8.4 Fourquadrant switchedcapacitor DC/DC Luoconverters.
Since the voltagelift and currentamplification technique are applied in the circuit, the power transfer efficiency is around 86.6%, which is much higher than those of the circuits introduced by the literature. 8.2.5.2 Conduction Duty k From the data calculated in previous sections, it can be seen that if k = 0.4, 0.5, or 0.6 the efficiencies ηA and ηB are not changed. The output power is slightly affected by k, and its maximum value corresponds k = 0.5. Therefore, we can take the typical data corresponding to k = 0.5. 8.2.5.3 Switching Frequency f Because the switching frequency f = 5 kHz is very low, its electromagnetic interference (EMI) is much lower than that of the traditional classical converters. The switching frequency applied in the traditional classical converters normally ranges between 50 kHz to 200 kHz.
8.3
FourQuadrant Switched Capacitor DC/DC LuoConverter
Since most SC DC/DC converters published in the literature perform in singlequadrant operation working in the pushpull status their control circuit and topologies are very complex. This section introduces an SC fourquadrant DC/DC Luoconverter. The experimental results verified our analysis and calculation. This converter, shown in Figure 8.4, consists of eight switches and two capacitors. The source voltage V1 and load voltage V2 (e.g., a battery or DC motor back EMF) are usually constant voltages. In this paper they are assumed to be 21 V and 14 V. Capacitors C1 and C2 are the same and C1= C2 = 2000 µF. The circuit equivalent resistance R = 50 mΩ. Therefore, there are four modes of operation for this converter: © 2003 by CRC Press LLC
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435
TABLE 8.5 Switch Status Q No
Condition
ON
OFF
Source
Load
QI, Mode A Forw. Mot.
V1 > V2 V1 < V2
S1,4,6,8 S1,4,6,8
S 2 , 4, 6 , 8 S 2 , 4, 7
V1+ I 1+
V2+ I2+
QII, Mode B Forw. Reg.
V1 > V2 V1 < V2
S2,4,6,8 S2,4,6,8
S 1 , 4, 7 S 1 , 4, 6 , 8
V1+ I 1–
V2+ I2–
QIII, Mode C Rev. Mot
V1 > V2 V1 < V2
S1,4,6,8 S1,4,6,8
S 3 , 5, 6 , 8 S 3 , 5, 7
V1+ I 1+
V2– I2–
QIV Mode D Rev. Reg.
V1 > V2 V1 < V2
S3,5,6,8 S3,5,6,8
S 1 , 4, 7 S 1 , 4, 6 , 8
V1+ I 1–
V2– I2+
Note: Omitted switches are off.
• Mode A (quadrant I, QI): energy is transferred from source to positive voltage load • Mode B (quadrant II, QII): energy is transferred from positive voltage load to source • Mode C (quadrant III, QIII): energy is transferred from source to negative voltage load • Mode D (quadrant IV, QIV): energy is transferred from negative voltage load to source The first quadrant is called the forward motoring (Forw. Mot.) operation. V1 and V2 are positive, and I1 and I2 are positive as well. The second quadrant is called the forward regenerative (Forw. Reg.) braking operation. V1 and V2 are positive, and I1and I2 are negative. The third quadrant is called the reverse motoring (Rev. Mot.) operation. V1 and I1 are positive, and V2 and I2 are negative. The fourth quadrant is called the reverse regenerative (Rev. Reg.) braking operation. V1 and I2 are positive, and I1 and V2 are negative. Each mode has two conditions: V1 > V2 and V1 < V2. Each condition has two states: on and off. Usually, each state operates in a different conduction duty k. The switching period is T where T = 1/f. The switch status is shown in Table 8.5. For mode A1, condition V1 > V2 is shown in Figure 8.5. Since V1 > V2 two capacitors C1 and C2 can be used in parallel. During switchon state, switches S1, S4, S6, and S8 are closed and other switches are open. In this case capacitors C1//C2 are charged via the circuit V1–S1–C1//C2–S4, and the voltage across capacitors C1 and C2 is increasing. During switchoff state, switches S2, S4, S6, and S8 are closed and other switches are open. In this case capacitors C1// C2 are discharged via the circuit S2–V2–S4–C1//C2, and the voltage across capacitors C1 and C2 is decreasing. Capacitors C1 and C2 transfer the energy from the source to the load. The voltage waveform across capacitor C1 is shown in Figure 8.5c. © 2003 by CRC Press LLC
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Advanced DC/DC Converters S1
S1
S2
S2
S6
VIN
+ VC1 –
S6
S7 C1
S8
S5 C2
+ + VIN
V2
+ VC1 –
S7 C1
S8
S5
+ V2 –
–
–
S4
C2
S4
(a) Switchon: S1, S4, S6, S8 on
(b) Switchoff: S2, S4, S6, S8 on
vC1 VC1
kT
T
kT
T
t
i C1
t
(c) Some waveforms FIGURE 8.5 Mode A1 (quadrant I) forward motoring operation with V1 > V2.
For mode A2, condition V1 < V2 is shown in Figure 8.6. Since V1 < V2 two capacitors C1 and C2 are in parallel during switchon and in series during switchoff. This is the voltage lift technique. During switchon state, switches S1, S4, S6, and S8 are closed and other switches are open. In this case capacitors C1//C2 are charged via the circuit V1–S1–C1//C2–S4, and the voltage across capacitors C1 and C2 is increasing. During switchoff state, switches S2, S4, and S7 are closed and other switches are open. In this case capacitors C1 and C2 are discharged via the circuit S2–V2–S4–C1–S7–C2, and the voltage across capacitor C1 and C2 is decreasing. Capacitors C1 and C2 transfer the energy from the source to the load. The voltage waveform across capacitor C1 is shown in Figure 8.6c. For mode B1, condition V1 > V2 is shown in Figure 8.7. Since V1 > V2 two capacitors C1 and C2 are in parallel during switchon and in series during switchoff. The voltage lift technique is applied. During switchon state, switches S2, S4, S6, and S8 are closed. In this case capacitors C1//C2 are charged via the circuit V2–S2–C1//C2–S4, and the voltage across capacitors C1 and C2 is increasing. During switchoff state, switches S1, S4, and S7 are © 2003 by CRC Press LLC
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437
S1
S2
S2
S7
S5 V2
C2
S8
S1
S6
S6 C1
+ VC1 –
+
+
VIN
V2
–
–
S5
S7 C2
S8
C1
+ VC1 –
VIN
S4
S4
(a) Switchon: S2, S4, S6, S8 on
(b) Switchoff: S1, S4, (S5), S7 on
vC1 VC1
kT
T
kT
T
t
i C1
t
(c) Some waveforms FIGURE 8.6 Mode A2 (quadrant I) forward motoring operation with V1 < V2.
closed. In this case capacitors C1 and C2 are discharged via the circuit S1–V1–S4–C2–S7–C1, and the voltage across capacitor C1 and C2 is decreasing. Capacitors C1 and C2 transfer the energy from the load to the source. The voltage waveform across capacitor C1 is shown in Figure 8.7c. For mode B2, condition V1 < V2 is shown in Figure 8.8. Since V1 < V2 two capacitors C1 and C2 can be used in parallel. During switchon state, switches S2, S4, S6, and S8 are closed. In this case capacitors C1//C2 are charged via the circuit V2–S2–C1//C2–S4, and the voltage across capacitors C1 and C2 is increasing. During switchoff state, switches S1, S4, S6, and S8 are closed. In this case capacitors C1//C2 are discharged via the circuit S1–V1–S4–C1//C2, and the voltage across capacitors C1 and C2 are decreasing. Capacitors C1 and C2 transfer the energy from the load to the source. The voltage waveform across capacitor C1 is shown in Figure 8.8c. For mode C1, condition V1 > V2 is shown in Figure 8.9. Since V1 > V2 two capacitors C1 and C2 can be used in parallel. During switchon state, switches S1, S4, S6, and S8 are closed. In this case capacitors C1//C2 are © 2003 by CRC Press LLC
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Advanced DC/DC Converters S2
S1
S7
S5 V2
C2
S8
+ VC1 –
C1
S1
S2
S6 +
+
VIN
V2
–
–
S6 S7
S5
C2
S4
S8
C1
+ VC1 –
VIN
S4
(b) Switchoff: S1, S4, (S5), S7 on
(a) Switchon: S2, S4, S6, S8 on
vC1 VC1
kT
T
kT
T
t
i C1
t
(c) Some waveforms FIGURE 8.7 Mode B1 (quadrant II) forward motoring operation with V1 > V2.
charged via the circuit V1–S1–C1//C2–S4, and the voltage across capacitors C1 and C2 is increasing. During switchoff state, switches S3, S5, S6, and S8 are closed. Capacitors C1 and C2 are discharged via the circuit S3–V2–S5–C1/ /C2, and the voltage across capacitors C1 and C2 is decreasing. Capacitors C1 and C2 transfer the energy from the source to the load. The voltage waveform across capacitor C1 is shown in Figure 8.9c. For mode C2, condition V1 < V2 is shown in Figure 8.10. Since V1 < V2 two capacitors C1 and C2 are in parallel during switchon and in series during switchoff, applying the voltage lift technique. During switchon state, switches S1, S4, S6, and S8 are closed. Capacitors C1 and C2 are charged via the circuit V1–S1–C1//C2–S4, and the voltage across capacitors C1 and C2 is increasing. During switchoff state, switches S3, S5, and S7 are closed. Capacitors C1 and C2 are discharged via the circuit S3–V2–S5–C1–S7–C2, and the voltage across capacitor C1 and C2 is decreasing. Capacitors C1 and C2 transfer the energy from the source to the load. The voltage waveform across capacitor C1 is shown in Figure 8.10c. For mode D1, condition V1 > V2 is shown in Figure 8.11. Since V1 > V2 two capacitors C1 and C2 are in parallel during switchon and in series © 2003 by CRC Press LLC
1956_C08.fm Page 439 Thursday, August 7, 2003 9:58 PM
Switched Component Converters
V2
S8
S1
S6
S7 C2
S2
S1
S2 S6 S5
439
C1
+ + VC1 V – IN
V2
–
–
+
S5
S7 C2
S8
C1
+ VC1 –
VIN
S4
S4
a) Switchon: S2, S4, S6, S8 on
(b) Switchoff: S2, S4, S6, S8 on
vC1 VC1
kT
T
kT
T
t
i C1
t
(c) Some waveforms FIGURE 8.8 Mode B2 (quadrant II) forward motoring operation with V1 < V2.
during switchoff, applying the voltage lift technique. During switchon state, switches S3, S5, S6, and S8 are closed. In this case capacitors C1//C2 are charged via the circuit V2–S3–C1//C2–S5, and the voltage across capacitors C1 and C2 is increasing. During switchoff state, switches S1, S4, and S7 are closed. Capacitors C1 and C2 are discharged via the circuit S1–V1–S4–C2–S7–C1, and the voltage across capacitor C1 and C2 is decreasing. Capacitors C1 and C2 transfer the energy from the load to the source. The voltage waveform across capacitor C1 is shown in Figure 8.11c. For Mode D2, condition V1 < V2 is shown in Figure 8.12. Since V1 < V2 two capacitors C1 and C2 can be used in parallel. During switchon state, switches S3, S5, S6, and S8 are closed. In this case capacitors C1//C2 are charged via the circuit V2–S3–C1//C2 –S5, and the voltage across capacitors C1 and C2 is increasing. During switchoff state, switches S1, S4, S6, and S8 are closed. Capacitors C1 and C2 are discharged via the circuit S1–V1–S4–C1// C2, and the voltage across capacitors C1 and C2 is decreasing. Capacitors C1 and C2 transfer the energy from the load to the source. The voltage waveform across capacitor C1 is shown in Figure 8.12c. © 2003 by CRC Press LLC
1956_C08.fm Page 440 Thursday, August 7, 2003 9:58 PM
440
Advanced DC/DC Converters S1
S1
S2
S2
S6 + VC1 –
VIN
S6
S7 C1
C2
S8
S5 +
+
V2 S4
VIN S3
+ VC1 –
S7 C1
S8
–
–
C2
S5 V2
S4
(a) Switchon: S1, S4, S6, S8 on
(b) Switchoff: S3, S5, S6, S8 on
vC1 VC1
kT
T
kT
T
t
i C1
t
(c) Some waveforms FIGURE 8.9 Mode C1 (quadrant III) forward motoring operation with V1 > V2.
8.3.1 8.3.1.1
Mode A (QI: Forward Motoring) Mode A1: Condition V1 > V2
Mode A1, condition V1 > V2, is shown in Figure 8.5. Because two capacitors are connected in parallel, the total capacitance is C = C1 + C2 = 4000 µF. Suppose that the equivalent circuit resistance is R = 50 mΩ, V1 = 21 V and V2 = 14 V, and the switching frequency is f = 5 kHz. The voltage and current across the capacitors are t t 1 v C ( 0) + i (t)dt ≈ vC (0) + i1 C C C 0 v C (t ) = t 1 t − kT vC ( kT ) + C iC (t)dt ≈ vC ( kT ) − C i2 kT
∫
∫
© 2003 by CRC Press LLC
0 ≤ t < kT (8.22) kT ≤ t < T
1956_C08.fm Page 441 Thursday, August 7, 2003 9:58 PM
Switched Component Converters S1
441 S1
S2
S2
S6
VIN
+ VC1 –
S6
S7 C1
S5 +
C2
S8
V2 S4
+ VIN
S3
+ VC1 –
S7 C1
–
–
S8
C2
S5 V2
S4
(b) Switchoff: S3, S5, S7 on
(a) Switchon: S1, S4, S6, S8 on vC1
VC1
kT
T
kT
T
t
i C1
t
(c) Some waveforms FIGURE 8.10 Mode C2 (quadrant III) forward motoring operation with V1 < V2.
V − VC V1 − vC (0) (1 − e − t/RC ) ≈ 1 = i1 R R iC ( t ) = v ( kT ) − V2 − t/RC V − V2 − C ≈− C = − i2 e R R
0 ≤ t < kT (8.23) kT ≤ t < T
Therefore, i1 =
1− k i k 2
(8.24)
Where i1 is the average input current in the switchon period kT that is equal to I1/k, and i2 is the average output current in the switchoff period (1 – k)T that is equal to I2/(1 – k). Therefore, we have I1 = I2. The variation of the voltage across capacitor C is © 2003 by CRC Press LLC
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442
Advanced DC/DC Converters S2
S6
S6 S7
S5 V2
C2
S1
S2
S1
+ VC1 –
C1
S8
+
+ S5
VIN
V2
–
–
S4
S7 C2
S8
C1
+ VC1 – VIN
S4
(a) Switchon: S3, S5, S6, S8 on
(b) Switchoff: S1, S4, S7 on
vC1 VC1
kT
T
kT
T
t
i C1
t
(c) Some waveforms FIGURE 8.11 Mode D1 (quadrant IV) forward motoring operation with V1 > V2.
1 ∆vC = C
kT
kT
∫ i (t)dt = C i C
0
1
=
k(V1 − VC ) fCR
0 ≤ t < kT
or 1 ∆vC = C
T
∫ i (t)dt = C
kT
(1 − k )(VC − V2 ) (1 − k )T i2 = C fCR
kT ≤ t < T
After calculation, VC = kV1 + (1 − k )V2 Hence © 2003 by CRC Press LLC
(8.25)
1956_C08.fm Page 443 Thursday, August 7, 2003 9:58 PM
Switched Component Converters S2
443 S2
S1
S6
S6 S7
S5 V2
C2
S8
S1
+ VC1 –
C1
S3
+
+
VIN
V2
–
–
S5
S7 C2
S8
C1
+ VC1 – VIN
S4
S4
(a) Switchon: S3, S5, S6, S8 on
(b) Switchoff: S1, S4, S6, S8 on
vC1 VC1
kT
T
kT
T
t
i C1
t
(c) Some waveforms FIGURE 8.12 Mode D2 (quadrant IV) forward motoring operation with V1 < V2.
∆vC =
k(1 − k )(V1 − V2 ) fCR
We then have vC (0) = VC −
∆vC 2
vC ( kT ) = VC +
∆vC 2
and
The average output current © 2003 by CRC Press LLC
is
(8.26)
1956_C08.fm Page 444 Thursday, August 7, 2003 9:58 PM
444
Advanced DC/DC Converters TABLE 8.6 The Calculation Results for Mode A1 (V1 > V2) k 0.4 0.5 0.6
VC
∆vC
I1
I2
ηA1
16.8 V 17.5 V 18.2 V
1.68 V 1.75 V 1.68 V
33.6 A 35 A 33.6A
33.6 A 35 A 33.6A
0.67 0.67 0.67
1 I2 = T
T
∫ i (t)dt ≈ (1 − k) C
kT
1 I1 = T
kT
∫ i (t)dt ≈ k C
0
VC − V2 R
V1 − VC R
(8.27)
(8.28)
Output power is PO = V2 I 2 = (1 − k )V2
VC − V2 R
(8.29)
Input power is PI = V1 I 1 = kV1
V1 − VC R
(8.30)
The transfer efficiency is ηA1 =
PO 1 − k V2 VC − V2 V2 = = PI k V1 V1 − VC V1
(8.31)
From this equation it can be seen that the transfer efficiency only relies on the ratio of the source and load voltages, and it is independent of R, C, f, and k. If f = 5 kHz, V1 = 21 V and V2 = 14 V, and total C = 4000 µF, R = 50 mΩ, for three k values the data are found in Table 8.6. From the analysis and calculation, it can be seen that the conduction duty k does not affect the power transfer efficiency. It affects the input and output power in a small region. The maximum output power corresponds at k = 0.5. 8.3.1.2
Mode A2: Condition V1 < V2
Mode A2, condition V1 < V2, is shown in Figure 8.6. Because two capacitors are connected in parallel during switchon, the total capacitance C = 2 × C1 © 2003 by CRC Press LLC
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Switched Component Converters
445
= 4000 µF. Input current i1 is two times that of capacitor current iC1. Two capacitors are connected in series during switchoff, the total capacitance C′ = C1/2 = 1000 µF. Output current i2 is equal to capacitor current iC1. Suppose that the equivalent circuit resistance R = 50 mΩ, V1 = 14 V and V2 = 21 V, and the switching frequency is f = 5 kHz. The voltage and current across each capacitor are t t 1 v C 1 ( 0) + iC1 (t)dt ≈ vC1 (0) + i C1 2C1 1 0 v C 1 (t ) = t 1 t − kT ( ) + v kT iC1 (t)dt ≈ vC1 ( kT ) − i C1 C C1 2 1 kT
∫
0 ≤ t < kT (8.32)
∫
kT ≤ t < T
V − VC1 V1 − vC1 (0) = i1 / 2 (1 − e − t/RC ) ≈ 1 R R iC 1 ( t ) = 2v ( kT ) − V2 − t/RC 2V − V2 − C 1 ≈ − C1 = − i2 e R R
0 ≤ t < kT (8.33) kT ≤ t < T
Therefore, i1 = 2
1− k i k 2
(8.34)
Where i1 is the average input current in the switchon period kT that is equal to I1/k, and 2 i2 is the average output current in the switchoff period (1 – k)T that is equal to I2/(1 – k). Therefore, we have I1 = 2I2. The variation of the voltage across capacitor C is
∆vC =
1 C
kT
∫
iC (t)dt =
0
k(V1 − VC ) kT i1 = 2C 2 fCR
0 ≤ t < kT
or 1 ∆vC = C
T
∫ i (t)dt = C
kT
(1 − k )(2VC − V2 ) (1 − k )T i2 = C fCR
kT ≤ t < T
To simplify the calculation, set k = 0.5 we have: VC = © 2003 by CRC Press LLC
0.5V1 + V2 = 11.2 V 2.5
(8.35)
1956_C08.fm Page 446 Thursday, August 7, 2003 9:58 PM
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Advanced DC/DC Converters
Hence k(V1 − VC ) = 0.7 V 2 fCR
∆vC =
(8.36)
We then have vC (0) = VC −
∆vC = 10.85 V 2
and vC ( kT ) = VC +
∆vC = 11.55 V 2
The average output current is 1 I2 = T
T
∫ i (t)dt ≈ (1 − k) C
kT
2VC − V2 R
(8.37)
The average input current is 1 I1 = T
kT
∫ i (t)dt ≈ k C
0
V1 − VC R
(8.38)
2VC − V2 R
(8.39)
Output power is PO = V2 I 2 = (1 − k )V2 Input power is PI = V1 I 1 = kV1
V1 − VC R
(8.40)
The transfer efficiency is ηA 2 =
© 2003 by CRC Press LLC
PO 1 − k V2 2VC − V2 V = = 2 PI k V1 V1 − VC 2V1
(8.41)
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Switched Component Converters
447
TABLE 8.7 The Calculation Results for Mode A2 (V1 < V2) k
VC (V)
∆vC (V)
I1 (A)
I2 (A)
P1 (W)
PO (W)
ηA2
0.5
11.2
0.7 V
28
14
392
294
0.75
TABLE 8.8 Experimental Results I1 (A)
I2 (A)
VC (V)
PI (W)
PO (W)
h
P (W)
PD (W/in3)
33
32
17.5
693
448
0.646
571
23.8
From this equation it can be seen that the transfer efficiency only relies on the ratio of the source and load voltages, and it is independent of R, C, f, and k. If f = 5 kHz, V1 = 14 V and V2 = 21 V and total C = 4000 µF, R = 50 mΩ. For k = 0.5 the data are listed in Table 8.7. From the analysis and calculation, it can be seen the power transfer efficiency only depends on the source and load voltages. 8.3.1.3 Experimental Results A testing rig of two batteries 14 VDC and 21 VDC was prepared. The testing conditions were f = 5 kHz, V1 = 21 V and V2 = 14 V, total C = 4000 µF, R = 50 mΩ. The experimental results for mode A are shown in Table 8.8. The equipment volume is 24 in3. The total average power density (PD) is 23.8 W/in3. This figure is much higher than the classical converters whose PD is usually less than 5 W/in3. Since the switching frequency is low, the electromagnetic interference (EMI) is weak.
8.3.2 8.3.2.1
Mode B (QII: Forward Regenerative Braking) Mode B1: Condition V1 > V2
Mode B1, condition V1 > V2 is shown in Figure 8.7. This mode operation is similar to mode A2. Because two capacitors are connected in parallel during switchon, the total capacitance C = 2 × C1 = 4000 µF. Input current i1 is two times the capacitor current iC1. Two capacitors are connected in series during switchoff, the total capacitance C′ = C1/2 = 1000 µF. Output current i2 is equal to capacitor current iC1. Suppose that the equivalent circuit resistance R = 50 mΩ, V1 = 21 V and V2 = 14 V, and the switching frequency f = 5 kHz, in order to save the description we quote the results as follows. The voltage and current across each capacitor are © 2003 by CRC Press LLC
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Advanced DC/DC Converters
t t 1 v C 1 ( 0) + iC1 (t)dt ≈ vC1 (0) + i C1 2C1 2 0 v C 1 (t ) = t 1 t − kT ( ) + v kT iC1 (t)dt ≈ vC1 ( kT ) − i C1 C C1 1 1 kT
∫
0 ≤ t < kT (8.42)
∫
kT ≤ t < T
V − VC1 V2 − vC1 (0) (1 − e − t/RC ) ≈ 2 = i2 / 2 R R iC 1 ( t ) = 2v ( kT ) − V1 − t/RC 2V − V1 − C 1 ≈ − C1 = −i1 e R R
0 ≤ t < kT (8.43) kT ≤ t < T
Therefore, i2 = 2
1− k i k 1
(8.44)
where i2 is the average input current in the switchon period, kT is equal to I2/k, and 2 i1 is the average output current in the switchoff period (1 – k)T that is equal to I1/(1 – k). Therefore, we have I2 = 2I1. The variation of the voltage across capacitor C is
∆vC =
1 C
kT
∫
iC (t)dt =
0
k(V2 − VC ) kT i2 = 2C 2 fCR
0 ≤ t < kT
or 1 ∆vC = C
T
∫ i (t)dt = C
kT
(1 − k )(2VC − V1 ) (1 − k )T i1 = C fCR
kT ≤ t < T
To simplify the calculation, set k = 0.5: VC =
0.5V2 + V1 = 11.2 V 2.5
(8.45)
k(V2 − VC ) = 0.7 V 2 fCR
(8.46)
Hence ∆vC =
© 2003 by CRC Press LLC
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Switched Component Converters
449
vC (0) = VC −
∆vC = 10.85 V 2
and vC ( kT ) = VC +
∆vC = 11.55 V 2
The average output current is 1 I1 = T
T
∫ i (t)dt ≈ (1 − k) C
kT
2VC − V1 R
(8.47)
The average input current is 1 I2 = T
kT
∫ i (t)dt ≈ k C
0
V2 − VC R
(8.48)
2VC − V1 R
(8.49)
Output power is PO = V1 I 1 = (1 − k )V1 Input power is PI = V2 I 2 = kV2
V2 − VC R
(8.50)
The transfer efficiency is ηB 1 =
PO 1 − k V1 2VC − V1 V = = 1 PI k V2 V2 − VC 2V2
(8.51)
From this equation it can be seen that the transfer efficiency only relies on the ratio of the source and load voltages, and it is independent of R, C, f, and k. If f = 5 kHz, V1 = 21 V and V2 = 14 V and total C = 4000 µF, R = 50 mΩ, for k = 0.5 the data are listed in Table 8.9. From the analysis and calculation, it can be seen the power transfer efficiency only depends on the source and load voltages.
© 2003 by CRC Press LLC
1956_C08.fm Page 450 Thursday, August 7, 2003 9:58 PM
450
Advanced DC/DC Converters TABLE 8.9 The Calculation Results for Mode B1 (V1 > V2) k 0.5
8.3.2.2
VC (V)
∆vC (V)
I1 (W)
I2 (W)
P1 (W)
PO (W)
ηB1
11.2
0.7
28
14
392
294
0.75
Mode B2: Condition V1 < V2
Mode B2, condition V1 < V2 is shown in Figure 8.8. This mode is similar to the mode A1. Because two capacitors are connected in parallel, the total capacitance C = C1 + C2 = 4000 µF. Suppose that the equivalent circuit resistance R = 50 mΩ, V2 = 21 V and V1 = 14 V, and the switching frequency f = 5 kHz, the voltage and current across the capacitors are t t 1 v C ( 0) + iC (t)dt ≈ vC (0) + i2 C C 0 v C (t ) = t 1 t − kT vC ( kT ) + C iC (t)dt ≈ vC ( kT ) − C i1 kT
∫
0 ≤ t < kT (8.52)
∫
kT ≤ t < T
V − VC V2 − vC (0) (1 − e − t/RC ) ≈ 2 = i2 R R iC ( t ) = v ( kT ) − V1 − t/RC V − V1 − C ≈− C = −i1 e R R
0 ≤ t < kT (8.53) kT ≤ t < T
Therefore, i2 =
1− k i k 1
(8.54)
Where i2 is the average input current in the switchon period kT that is equal to I2/k, and i1 is the average output current in the switchoff period (1 – k)T that is equal to I1/(1 – k). Therefore, we have I2 = I1. The variation of the voltage across capacitor C is 1 ∆vC = C
kT
kT
∫ i (t)dt = C i C
0
2
=
k(V2 − VC ) fCR
0 ≤ t < kT
or 1 ∆vC = C
T
∫ i (t)dt = C
kT
© 2003 by CRC Press LLC
(1 − k )(VC − V1 ) (1 − k )T i1 = C fCR
kT ≤ t < T
1956_C08.fm Page 451 Thursday, August 7, 2003 9:58 PM
Switched Component Converters
451
After calculation, VC = kV2 + (1 − k )V1
(8.55)
Hence ∆vC =
k(1 − k )(V2 − V1 ) fCR
(8.56)
We then have vC (0) = VC −
∆vC 2
vC ( kT ) = VC +
∆vC 2
and
The average output current is
I1 =
1 T
T
∫ i (t)dt ≈ (1 − k) C
kT
VC − V1 R
(8.57)
The average input current is kT
iC (t)dt ≈ k
V2 − VC R
(8.58)
PO = V1 I 1 = (1 − k )V1
VC − V1 R
(8.59)
I2 =
1 T
∫ 0
Output power is
Input power is PI = V2 I 2 = kV2 The transfer efficiency is © 2003 by CRC Press LLC
V2 − VC R
(8.60)
1956_C08.fm Page 452 Thursday, August 7, 2003 9:58 PM
452
Advanced DC/DC Converters TABLE 8.10 The Calculation Results for Mode B2 (V1 < V2) k 0.4 0.5 0.6
VC
∆vC
I1
I2
ηA1
16.8 V 17.5 V 18.2 V
1.68 V 1.75 V 1.68 V
33.6 A 35 A 33.6A
33.6 A 35 A 33.6A
0.67 0.67 0.67
ηB 2 =
PO 1 − k V1 VC − V1 V1 = = PI k V2 V2 − VC V2
(8.61)
The transfer efficiency only relies on the ratio of the source and load voltages, and it is independent of R, C, f, and k. If f = 5 kHz, V2 = 21 V and V1 = 14 V and total C = 4000 µF, R = 50 mΩ. For three k values we obtain the data in Table 8.10. From the analysis and calculation, it can be seen that the conduction duty k does not affect the power transfer efficiency. It affects the input and output power in a small region. The maximum output power corresponds at k = 0.5.
8.3.3
Mode C (QIII: Reverse Motoring)
This mode is similar to the mode A.
8.3.4
Mode D (QIV: Reverse Regenerative Braking)
This mode is similar to the mode B.
8.4
Switched Inductor FourQuadrant DC/DC LuoConverter
Although switchedcapacitor DC/DC converters can reach high power density, their circuits are always very complex with difficult control. If the difference between input and output voltages is large, multiple switchcapacitor stages must be employed. Switched inductor DC/DC converters successfully overcome this disadvantage. Usually, only one inductor is required for each converter with 1quadrant, 2quadrant or 4quadrant operation no matter how large the difference between the input and output voltages. Therefore, the switched inductor converter is a very simple circuit and consequently has high power density. This section introduces an SI fourquadrant DC/DC Luoconverter working in fourquadrant operation.
© 2003 by CRC Press LLC
1956_C08.fm Page 453 Thursday, August 7, 2003 9:58 PM
Switched Component Converters
453
This converter is shown in Figure 8.13a consisting of three switches, two diodes, and only one inductor L. The source voltage V1 and load voltage V2 (e.g., a battery or DC motor back EMF) are usually constant voltages. R is the equivalent resistance of the circuit, it is usually small. Its equivalent circuits for quadrant I and II, and quadrant III and IV operation are shown in Figure 8.13b and c. Assuming the condition V1 > V2, they are +42 V and ±14 V, respectively. Therefore, there are four quadrants (modes) of operation: • Mode A (quadrant I: QI): the energy is transferred from source to positive voltage load • Mode B (quadrant II: QII): the energy is transferred from positive voltage load to source • Mode C (quadrant III: QIII): the energy is transferred from source to negative voltage load • Mode D (quadrant IV: QIV): the energy is transferred from negative voltage load to source The first quadrant is called the forward motoring (Forw. Mot.) operation. V1 and V2 are positive, and I1 and I2 are positive as well. The second quadrant is called the forward regenerative (Forw. Reg.) braking operation. V1 and V2 are positive, and I1 and I2 are negative. The third quadrant is called the reverse motoring (Rev. Mot.) operation. V1 and I1 are positive, and V2 and I2 are negative. The fourth quadrant is called the reverse regenerative (Rev. Reg.) braking operation. V1 and I2 are positive, and I1 and V2 are negative. Each mode has two states: on and off. Usually, each state is operating in different conduction duty k. The switching period is T where T = 1 / f. The switch status is shown in Table 8.11. Mode A operation is shown in Figure 8.14a (switch on) and b (switch off). During switchon state, switch S1 is closed. In this case the source voltage V1 supplies the load V2 and inductor L, inductor current iL increases. During switchoff state, diode D2 is on. In this case current iL flows through the load V2 via the freewheeling diode D2, and it decreases. Mode B operation is shown in Figure 8.15 a (switch on) and b (switch off). During switchon state, switch S2 is closed. In this case the load voltage V2 supplies the inductor L, inductor current iL increases. During switchoff state, diode D1 is on, current iL flows through the source V1 and load V2 via the diode D1, and it decreases. Mode C operation is shown in Figure 8.16 a (switch on) and b (switch off). During switchon state, switch S1 is closed. The source voltage V1 supplies the inductor L, inductor current iL increases. During switchoff state, diode D2 is on. Current iL flows through the load V2 via the freewheeling diode D2, and it decreases.
© 2003 by CRC Press LLC
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454
Advanced DC/DC Converters D1
D2
S1
L1
S2
R1
Switch S
i IN 3,4
VI
1,2
3,4
N
1,2 i2
V2
(a) Circuit diagram D1
S1
L1
S2
Vhigh
R1
Vlow
D2
I high
I low
(b) Quadrant I and II operation circuit D1
D2
S1
S2 L1
Vhigh I high
Vlow R1
I low
(c) Quadrant III and IV operation circuit FIGURE 8.13 Fourquadrant switchedinductor DC/DC Luoconverters.
Mode D operation is shown in Figure 8.17 a (switch on) and b (switch off). During switchon state, switch S2 is closed. The load voltage V2 supplies the inductor L, inductor current iL increases. During switchoff state, diode D1 is on. Current iL flows through the source V1 via the diode D1, and it decreases.
© 2003 by CRC Press LLC
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Switched Component Converters
455
TABLE 8.11 Switch Status Q No.
State
S1
D1
QI , Mode A Forw. Mot.
on off
ON
QII , Mode B Forw. Reg.
on off
QIII , Mode C Rev. Mot.
on off
QIV , Mode D Rev. Reg.
on off
S2
D2
S3
Source
Load
ON
ON 1/2 ON1/2
V 1+ I 1+
V 2+ I 2+
ON 1/2 ON 1/2
V 1+ I 1–
V 2+ I 2–
ON 3/4 ON 3/4
V 1+ I 1+
V 2– I 2–
ON 3/4 ON 3/4
V 1+ I 1–
V 2– I 2+
ON ON ON ON ON ON
Note: Omitted switches are off.
S1
L1
iIN i1
Vhigh Ihigh
L1
R1
Vlow Ilow
Vhigh
D2
R1
i2
Vlow
Ihigh
Ilow
(a) Switchon
(b) Switchoff
FIGURE 8.14 Mode A (quadrant I) operation.
D1
L1
R1
R1
L1
iO
iIN Vlow
i1
S2
Vhigh Ihigh
Ilow
(a) Switchon FIGURE 8.15 Mode B (quadrant II) operation. © 2003 by CRC Press LLC
Vlow
i2
Vhigh Ihigh
Ilow
(b) Switchoff
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Advanced DC/DC Converters D2
S1 iIN Vhigh
i1
Vlow
Ihigh
L1
iO
R1
R1 Vhigh
Ilow
Vlow
i2 L1
Ihigh
(a) Switchon
Ilow
(b) Switchoff
FIGURE 8.16 Mode C (quadrant III) operation.
D1 S2
iIN
iO R1
R1 i1
Vhigh Ihigh
L1
Vlow
Vhigh
Ilow
i2
Ihigh
(a) Switchon
Vlow L1
Ilow
(b) Switchoff
FIGURE 8.17 Mode D (quadrant IV) operation.
8.4.1
Mode A (QI: Forward Motoring)
8.4.1.1 Continuous Mode Refer to Figure 8.14a and suppose that V1 = +42 V and V2 = +14 V, L = 0.3 mH and the parasitic resistance R = 3 mΩ. V − V2 − RI L v L (t ) = 1 −(V2 + RI L ) V1 − V2 − RI L t i L ( 0) + L i L (t ) = V + RI L iL ( kT ) − 2 (t − kT ) L
0 ≤ t < kT kT ≤ t < T
(8.62)
0 ≤ t < kT kT ≤ t < T
(8.63)
where iL(0) = IL – ∆iL/2 © 2003 by CRC Press LLC
(8.64)
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Switched Component Converters
457
iL(kT) = IL + ∆iL/2
(8.65)
From Equations (8.62) and (8.63) the average inductor current is IL =
kV1 − V2 R
(8.66)
The peaktopeak variation of inductor current iL is ∆iL =
k(1 − k )V1 fL
(8.67)
The variation ratio is ζ=
∆iL / 2 k(1 − k )V1 R = IL kV1 − V2 2 fL
(8.68)
Substituting Equations (8.66) and (8.67) into Equations (8.64) and (8.65), we have i L ( 0) =
kV1 − V2 k(1 − k )V1 − R 2 fL
(8.69)
iL ( kT ) =
kV1 − V2 k(1 − k )V1 + R 2 fL
(8.70)
and
The average input current is 1 II = T
kT
∫ i (t)dt ≈ k L
0
kV1 − V2 R
(8.71)
kV1 − V2 R
(8.72)
The average output current is 1 IO = T
T
∫ i (t)dt ≈ L
0
Input power is PI = V1 I I = kV1 © 2003 by CRC Press LLC
kV1 − V2 R
(8.73)
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Advanced DC/DC Converters
Output power is PO = V2 I O = V2
kV1 − V2 R
(8.74)
The transfer efficiency is ηA =
PO V = 2 PI kV1
(8.75)
The transfer efficiency only relies on conduction duty k, the source and load voltages. It is independent of R, L, and f. If f = 1 kHz, L = 300 µH, R = 3 mΩ, k = 0.35, V1 = 42 V and V2 = 14 V, we find that IL = 233 A, ∆iL = 31.85 A ζ = 6.83% II = I1 = 81.6 A, IO = I2 = 233 A, PO = 32,672W
PI = 3427 W
ηΑ = 95%
8.4.1.2 Discontinuous Mode From Equation (8.68), when ζ ≥ 1 the current iL is discontinuous. The boundary between continuous and discontinuous regions is defined: ζ=
∆iL / 2 k(1 − k )V1 R = ≥1 IL kV1 − V2 2 fL
i.e., k(1 − k )V1 R ≥1 kV1 − V2 2 fL or k≤
V2 R + k(1 − k ) 2 fL V1
(8.76)
From Equation (8.76) the discontinuous conduction region is caused by the following factors: • Switching frequency f is too low • Duty cycle k is too small © 2003 by CRC Press LLC
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Switched Component Converters
459
• Inductance L is too small • Load resistor R is too big The whole conduction period is smaller than T. Assuming the conduction period is in the region between 0 and t1 that is smaller than T. The filling coefficient mA is defined as mA =
t1 − kT (1 − k )T
kT < t1 ≤ T
(8.77)
The voltage and current across inductor L are V1 − V2 − RI L vL (t) = −(V2 + RI L ) 0
0 ≤ t < kT kT ≤ t < t1 t1 ≤ t < T
V1 − V2 − RI L t L V V + RI L 1 kT − 2 t L i L (t ) = L 0
(8.78)
0 ≤ t < kT kT ≤ t < t1
(8.79)
t1 ≤ t < T
because iL(0) = 0 iL ( kT ) =
V1 − V2 − RI L kT L
iL(kT) is the peak value of inductor current iL(t). It is also the peaktopeak variation ∆iL . From Equation (8.79) when t = t1, iL(t1) = 0. Therefore, we have the following relation: iL (t1 ) =
V1 V + RI L kT − 2 t1 = 0 L L
Therefore, t1 = © 2003 by CRC Press LLC
V1 kT V2 + RI L
(8.80)
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Advanced DC/DC Converters
Considering Equation (8.76), kT < t1 < T Since R is usually small, we can get t1 ≈
V1 kT V2
The average inductor current is 1 IL = T
t1
t1
V1
∫ i (t)dt = 2T i (kT ) = V + RI L
L
s
2
0
L
V1 − V2 − RI L 2 k 2 fL
Since R is usually small, it can be rewritten as IL ≈
V1 V1 − V2 2 k V2 2 fL
The average input current is 1 II = T
kT
∫ i (t)dt = L
0
iL ( kT ) V − V2 − RI L 2 kT = 1 k 2T 2 fL
The average output current is 1 IO = T
t1
∫ i (t)dt = L
0
iL ( kT ) V − V2 − RI L V1 t1 = 1 k2 2T 2 fL V2 + RI L
Input power is PI = V1 I I = V1
V1 − V2 − RI L 2 k 2 fL
Output power is PO = V2 I O = V2
© 2003 by CRC Press LLC
V1 − V2 − RI L V1 k2 V2 + RI L 2 fL
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461
The transfer efficiency is ηA− dis =
PO V2 = PI V2 + RI L
(8.81)
with k≤
8.4.2
V2 R + k(1 − k ) 2 fL V1
Mode B (QII: Forward Regenerative Braking)
8.4.2.1 Continuous Mode Refer to Figure 8.15a, and suppose that V1 = +42 V and V2 = +14 V, L = 0.3 mH and the parasitic resistance R = 3 mΩ. V − RI L v L (t ) = 2 −(V1 − V2 + RI L )
0 ≤ t < kT kT ≤ t < T
V2 − RI L t iL (0) + L i L (t ) = V − V2 + RI L iL ( kT ) − 1 (t − kT ) L
(8.82)
0 ≤ t < kT kT ≤ t < T
(8.83)
Where iL (0) = I L − ∆iL / 2
(8.84)
iL ( kT ) = I L + ∆iL / 2
(8.85)
Since the inductor average voltage is zero, we have k(V2 − RI L ) = (1 − k )(V1 − V2 + RI L ) then: IL =
V2 − (1 − k )V1 R
The peaktopeak variation of inductor current iL is © 2003 by CRC Press LLC
(8.86)
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Advanced DC/DC Converters
∆iL =
k(1 − k )V1 fL
(8.87)
The variation ratio is ζ=
∆iL / 2 k(1 − k )V1 R = IL V2 − (1 − k )V1 2 fL
(8.88)
Substituting Equations (8.86) and (8.87) into Equations (8.84) and (8.85), i L ( 0) =
V2 − (1 − k )V1 k(1 − k )V1 − R 2 fL
(8.89)
and iL ( kT ) =
V2 − (1 − k )V1 k(1 − k )V1 + R 2 fL
(8.90)
The average input current is
II =
1 T
T
∫ i (t)dt = L
0
V2 − (1 − k )V1 R
(8.91)
The average output current is
IO =
1 T
T
∫ i (t)dt = (1 − k) L
kT
V2 − (1 − k )V1 R
(8.92)
Input power is PI = V2 I I = V2
V2 − (1 − k )V1 R
(8.93)
Output power is PO = V1 I O = (1 − k )V1 The transfer efficiency is © 2003 by CRC Press LLC
V2 − (1 − k )V1 R
(8.94)
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Switched Component Converters
ηB =
463 PO (1 − k )V1 = PI V2
(8.95)
The transfer efficiency only relies on conduction duty k, the source and load voltages. It is independent of R, L, and f. 8.4.2.2 Discontinuous Mode From Equation (8.88), when ζ ≥ 1 the current iL is discontinuous. The boundary between continuous and discontinuous regions is defined as: ζ=
∆iL / 2 k(1 − k )V1 R = ≥1 IL V2 − (1 − k )V1 2 fL
i.e., k(1 − k )V1 R ≥1 V2 − (1 − k )V1 2 fL or k ≤ (1 −
V2 R ) + k(1 − k ) V1 2 fL
(8.96)
The whole conduction period is smaller than T. Assume that the conduction period is in the region between 0 and t2 that is smaller than T. The filling coefficient mB is defined as mB =
t2 − kT (1 − k )T
kT < t2 ≤ T
(8.97)
The voltage and current across inductor L are V2 − RI L vL (t) = −(V1 − V2 + RI L ) 0
0 ≤ t < kT kT ≤ t < t2 t2 ≤ t < T
V2 − RI L t L V V − V2 + RI L iL (t) = 1 kT − 1 t L L 0 © 2003 by CRC Press LLC
(8.98)
0 ≤ t < kT kT ≤ t < t2 t2 ≤ t < T
(8.99)
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Advanced DC/DC Converters
because iL(0) = 0 iL ( kT ) =
V2 − RI L kT L
iL(kT) is the peak value of inductor current iL(t). It is also the peaktopeak variation ∆iL. From Equation (8.99) when t = t2, iL(t2) = 0. Therefore, we have the following relation: V1 V − V2 + RI L kT − 1 t2 = 0 L L
i L (t 2 ) = Therefore,
t2 =
V1 kT V1 − V2 + RI L
Considering Equation (8.86), kT 0V 1.980ms V(D8:2)
(1.99m,15.8) 1.984ms V(R:2)
1.988ms V(D5:2)
1.992ms
1.996ms
2.000ms
V(D2:2) Time
FIGURE 9.18 The simulation result of a triplelift additional circuit at condition k = 0.5 and f = 100 kHz.
FIGURE 9.19 The experimental result of a triplelift circuit at condition k = 0.5 and f = 100 kHz.
9.6.3
TripleLift MultipleEnhanced Circuit
The triplelift multipleenhanced circuit is derived from triplelift circuit by adding the DEC multiple (j) times in each stage circuit. Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 9.14. The switches S and (S1, S2, S3) operate in pushpull state. The voltage across capacitor C1 is charged to Vin, voltage across capacitor C3 is © 2003 by CRC Press LLC
1956_C09.fm Page 499 Thursday, August 7, 2003 9:56 PM
FIGURE 9.20 The experimental result of a triplelift additional circuit at condition k = 0.5 and f = 100 kHz.
charged to V1, voltage across capacitor C5 is charged to V2 and voltage across capacitor C11 is charged to V3 during switchon. The voltage across capacitor C2 is charged to V1 = 2Vin – ∆V1, voltage across capacitor C4 is charged to V2 = 2V1 – ∆V2 and voltage across capacitor C6 is charged to V3 = 2V2 – ∆V3 during switchoff. Therefore, the output voltage is VO = V3 + V2 − ∆V3 − ∆VO = 12Vin − 6 ∆V1 − 3 ∆V2 − ∆V3 − ∆VO
(9.22)
where ∆V3 is set for the same reason as ∆V1. 9.6.4
Higher Order Lift MultipleEnhanced Circuit
Higher order lift multipleenhanced circuit is derived from the corresponding circuit of the main series by adding the DEC multiple (j) times in each stage circuit. The output voltage of the nthlift multipleenhanced circuit is n −1
VO = 1.5 × (2 n Vin −
∑ 2 ∆V i
n− i
) − ∆Vn − ∆VO
(9.23)
i =1
9.7
Theoretical Analysis
The maximum output current is a key parameter of the DCDC converter. The output voltage of DCDC stepup converter can be shown as © 2003 by CRC Press LLC
1956_C09.fm Page 500 Thursday, August 7, 2003 9:56 PM
VO =
m +1
1+ where kS =
k sVin − k dVd T 1+ R
m +1
∑ i =1
kTn
i − ni [1 − e RiCi ] Ci
(9.24)
m +1
∏n
2 j
j =1
i
∑∏n
j
i =1 j =1 m +1
∏n
m +1
and kd =
∑
ni (ni + 1) m+1
i
i =1
In Equation (9.24), m and n are the stepnumber of the converter and the number of the serialparallel capacitors network respectively. T and k are the switch period and the dutycycle ratio in the state 1, respectively. For the threelift circuit, m = 1, n1 = n2 = 1 and f = 1/T, we can write the Equation (9.24) as follows VO =
1 1+ ( fR
3Vin − 4Vd 1 / C2 1 / C1 + 1 1 1− e
−
2 fR2C2
1− e
−
(9.25) )
2 fR1C1
Since Io = VO/R, we can write the output current of this threelift circuit as follows 3Vin − 4Vd − VO f (9.26) Io = 1 / C2 1 / C1 + 1 1 1− e
−
2 fR2C2
1− e
−
2 fR1C1
where Vin is the source voltage assuming 10 V, VO is the output voltage assuming 21.6 V, Vd is the voltage drop across diode, Ri which corresponds to the wire resistor of capacitor Ci. In order to increase the output current of the converter, we selected Schottky barrier diode (Vd = 0.4 V), then 3Vin – 4Vd – VO = 6.8 V
(9.27)
For getting the maximum output current, C1 = C2 = C have to be chosen. In addition we assumed R1 = R2 = R. Therefore, the description of the output current can be simplified as Io = 0.9 f C [1 – exp(–1/2RfC)]
(9.28)
Figure 9.15 shows the relationship among output current IO, operation frequency f and capacitance C on the basis of the equation. From the result, it is concluded that © 2003 by CRC Press LLC
1956_C09.fm Page 501 Thursday, August 7, 2003 9:56 PM
1. Higher frequency can result in bigger output current, especially the capacitance of C if the serialparallel capacitors is not elevated for integration. 2. For a certain capacitor, there is a maximum frequency restriction, and it reduces when the capacitance is raised. 3. The output current can be up to 1A if the operation frequency f of the converter and the capacitance C of the serialparallel capacitors are suitably chosen. In addition, it can be shown from the equation deducing that the maximum ratio Po/C can be obtained by using the same capacitance of the serialparallel capacitors in the structure. The theoretical analysis for the higher order lift circuits is similar to above description.
9.8
Summary of This Technique
Using this technique, it is easy to design the Higher Order Lift circuit to obtain high output voltage. All these converters can be sorted in several subseries: main series, additional series, enhanced series, reenhanced series and multipleenhanced series. The output voltage of the nthlift circuit is m −1 2 m Vin − 2i ∆Vm−i i =0 m −1 1.5 ∗ (2 m Vin − 2i ∆Vm−i ) − ∆Vm − ∆VO i =1 m −1 2i ∆Vm−i ) − ∆Vm − ∆VO VO = ( 3m Vin − i =1 m −1 ( 4 m Vin − 2i ∆Vm−i ) − ∆Vm − ∆VO i =1 m −1 m [( j + 2) V − 2i ∆Vm−i ] − ∆Vm − ∆VO in i =1
∑
∑
Main _ series Additional _ series
∑
Enhanced _ series
∑
Re Enhanced _ series
∑
(9.29)
Multiple  Enhanced _ series
From above formula, the family tree of positive output multiplelift pushpull switchedcapacitor Luoconverters is shown in Figure 9.16.
9.9
Simulation Results
To verify the design and calculation results, the PSpice simulation package was applied to these circuits. Choosing VI = 10 V, all capacitors Ci = 2 µF, R © 2003 by CRC Press LLC
1956_C09.fm Page 502 Thursday, August 7, 2003 9:56 PM
= 60 k, k = 0.5 and f = 100 kHz, we obtain the current and voltage values in the following converters.
9.9.1
A TripleLift Circuit
Assume that the voltage drops ∆V1, ∆V2, and ∆V3 are about 4.2 V, the current waveforms of ID2, ID5, and ID8, then voltage values of V1, V2, and VO are 15.7 V, 27.2 V, and 50.7 V. The simulation results (current and voltage values) in Figure 9.17 are identically matched to the calculated results.
9.9.2
A TripleLift Additional Circuit
Assume that the voltage drops ∆V1, ∆V2, ∆V3, and ∆VO are about 4.2 V, the current waveforms of ID2, ID5, ID8, and ID12, then voltage values of V1, V2, V3, and VO are 15.8 V, 27.5 V, 50.8 V, and 74.8 V. The simulation results (current and voltage values) shown in Figure 9.18 are identically matched to the calculated results.
9.10
Experimental Results
A test rig was constructed to verify the design and calculation results, and was compared with PSpice simulation results. With VI = 10 V, all capacitors Ci = 2 µF, R = 60 k, k = 0.5 and f = 100 kHz, we measured the output voltage and the first diode current values in following converters.
9.10.1
A TripleLift Circuit
After careful measurement, we obtained the current waveform of ID2 (shown in channel 1 with 5 A/Div in Figure 9.19) and voltage value of VO of 50.8 V (shown in channel 2 with 20 V/Div). The experimental results (current and voltage values) in Figure 9.17 are identically matched to the calculated and simulation results.
9.10.2
A TripleLift Additional Circuit
The experimental results (voltage and current values) are identically matching to the calculated and simulation results, as shown in Figure 9.20. The current waveform of ID2 (shown in channel 1 with 5 A/Div) and voltage value of VO of 75 V (shown in channel 2 with 20 V/Div) have been obtained.
© 2003 by CRC Press LLC
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Bibliography Cheong, S.V., Chung, H., and Ioinovici, A., Inductorless DCDC converter with high power density, IEEE Trans. on Industrial Electronics, 41, 208, 1994. Chung, H.S., Hui, S.Y.R., Tang, S.C., and Wu, A., On the use of current control scheme for switchedcapacitor DC/DC converters, IEEE Trans. Ind. Electron, 47, 238, 2000. Gao, Y. and Luo, F.L., Theoretical analysis on performance of a 5V/12V pushpull switched capacitor DC/DC converter, in Proceedings of IEEIPEC’2001, Singapore, 2001, p. 711. Harris, W.S. and Ngo, K.D.T., Power switchedcapacitor DCDC converter: analysis and design, IEEE Transactions on ANES, 33, 386, 1997. Liu, J. and Chen, Z., A pushpull switched capacitor DCDC setup converter, Technology of Electrical Engineering, 1, 41, 1998. Luo, F.L. and Ye H., Fourquadrant switched capacitor converter, in Proceedings of the 13th Chinese Power Supply Society IAS Annual Meeting, Shenzhen, China, 1999, p. 513. Luo, F.L. and Ye, H., Positive output multiplelift pushpull switchedcapacitor Luoconverters, in Proceedings of IEEEPESC’2002, Cairns Australia, 2002, p. 415. Mak, O.C. and Ioinovici, A., Switchedcapacitor inverter with high power density and enhanced regulation capability, IEEE Trans. on CASI, 45, 336, 1998. Midgley, D. and Sigger, M., Switchedcapacitors in power control, IEE Proc., 121, 703, 1974. Tse, C.K., Wong, S.C., and Chow, M.H. L., On lossless switchedcapacitor power converters, IEEE Trans. on PE, 10, 286, 1995.
© 2003 by CRC Press LLC
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10 Negative Output MultipleLift PushPull SwitchedCapacitor LuoConverters
Positive output multiplelift pushpull switchedcapacitor Luoconverters have been introduced in the previous chapter. Correspondingly, negative output multiplelift pushpull switchedcapacitor Luoconverters will be introduced in this chapter.
10.1 Introduction Negative output multiplelift pushpull switchedcapacitor Luoconverters can be sorted into several subseries: • • • • •
Main series Additional series Enhanced series Reenhanced series Multipleenhanced series
Each circuit has one main switch S and several slave switches as Si (i = 1, 2, 3, …n). The number n is called stage number. The main switch S is on and slaves off during switchingon period kT, and S is off and slaves on during switchoff period (1 – k)T. The load is resistive load R. Input voltage and current are Vin and Iin, output voltage and current are VO and IO. Each circuit in the main series has one main switch S and n slave switches for nth stage circuit, 2n capacitors and (3n – 1) diodes. Each circuit in the additional series has one main switch S and n slave switches for nth stage circuit, 2(n + 1) capacitors and (3n + 1) diodes. Each circuit in the enhanced series has one main switch S and n slave switches for nth stage circuit, 4n capacitors and (5n – 1) diodes. Each circuit in the reenhanced series has one main switch S and n slave switches for nth stage circuit, 6n capacitors, and
© 2003 by CRC Press LLC
1956_C10.fm Page 506 Monday, August 18, 2003 3:22 PM
Iin S
+
C1
S1
IO
+ VC1 –
–
Vin
– D1
D2
R
VO
VC2
C2
+
+
–
(a) Circuit diagram Iin IO + – VC2
+ Vin
C1
Vin C2
– R
+
–
VO +
–
(b) Equivalent circuit during switchingon (S on)
C1 IO + + Vin – Vin
C2
– VC2
– R
+
VO +
–
(c) Equivalent circuit during switchingoff (S1 on) FIGURE 10.1 Elementary circuit of N/O pushpull SC Luoconverter.
(7n – 1) diodes. Each circuit in the multiple (j times)enhanced series has one main switch S and n slave switches for nth stage circuit, 2(1 + j)n capacitors and [(3 + 2j)n – 1) diodes. To simplify the calculation and explanation, all output values are the absolute values. The output voltage polarity is shown in the corresponding figure.
10.2 Main Series The first three stages of the main series are shown in Figure 10.1 to Figure 10.3. For convenience they are called negative output (N/O) elementary © 2003 by CRC Press LLC
1956_C10.fm Page 507 Monday, August 18, 2003 3:22 PM
Iin
+
s S1
IO
+ D3 VC1 S2 – V1
C1
Vin D1
C3
D4 – VC2
D2 C2
–
+ VC3 –
– D5 C4
R
VO
–
+
VC4 +
+
(a) Circuit diagram Iin + C3 + Vin C1
IO
+ V1+Vin
–
–
Vin
C4
– C2
– V1 +
–
–
VC4 R +
VO +
(b) Equivalent circuit during switchingon (S on) C1
V1
C3 IO
+ + Vin – Vin
C2
– V1 +
+ V1+V – in
–
–
C4
VC4
VO
+
R
+
–
(c) Equivalent circuit during switchingoff (S1 and S2 on) FIGURE 10.2 N/O relift pushpull SC circuit.
circuit, N/O relift circuit, and N/O triplelift circuit respectively, and are numbered as n = 1, 2, and 3.
10.2.1
N/O Elementary Circuit
The elementary circuit and its equivalent circuits during switchon and switchoff are shown in Figure 10.1. Two switches S and S1 operate in pushpull state. The voltage across capacitor C1 is charged to Vin during switchon. The voltage across capacitor C2 is charged to VO = 2Vin during switchoff. Therefore, the output voltage is (absolute value): © 2003 by CRC Press LLC
1956_C10.fm Page 508 Monday, August 18, 2003 3:22 PM
Iin s
D3
D6
+
IO S1
+ VC1
C1
S2
–
Vin D1
+ VC3
C3
D4 – VC2 +
D2 C2
–
S3
–
V1
+ VC5
C5
–
V2 D7 – VC4 +
D5 C4
D8 C6
R
– VO
–
+
VC6 +
(a) Circuit diagram Iin +
Vin
C3 + Vin – C2
C1
–
+ V1+Vin
C5
– V1 – V1 +
IO
+ V2+Vin
–
– V2 C4
C6
– V2 +
–
VC6 R +
VO +
(b) Equivalent circuit during switchingon (S on) C1
V1
C5
C3
IO + + Vin – Vin
C2
+ V1+V – in
– V1 +
C4
– VC4 +
+ V2+V – in C6
–
–
VC6 R
VO
+
+
–
(c) Equivalent circuit during switchingoff (S1, S2, and S3 on) FIGURE 10.3 N/O triplelift pushpull SC circuit.
VO = 2Vin − Vin = Vin
(10.1)
Considering the voltage drops across the diodes and switches, we combine all values in a figure of ∆V1. The real output voltage is VO = Vin − ∆V1
© 2003 by CRC Press LLC
(10.2)
1956_C10.fm Page 509 Monday, August 18, 2003 3:22 PM
10.2.2
N/O ReLift Circuit
The N/O relift circuit is derived from N/O elementary circuit by adding one slave switch, two switchedcapacitors, and three diodes (S2C3C4D3D4D5). Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 10.2. The switches S and (S1, S2) operate in pushpull state. The voltage across capacitor C1 is charged to Vin and voltage across capacitor C3 is charged to V1 during switchon. The voltage across capacitor C2 is charged to V1 = 2Vin – ∆V1 and voltage across capacitor C4 is charged to VO = 2V1 – ∆V2 during switchoff. Therefore, the output voltage is VO = 2V1 − ∆V2 − Vin = 3Vin − 2 ∆V1 − ∆V2
(10.3)
where ∆V2 is set for the same reason as ∆V1. 10.2.3
N/O TripleLift Circuit
The N/O triplelift circuit is derived from N/O relift circuit by adding one more slave switch, two switchedcapacitors, and three diodes (S3C5C6D6D7D8). Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 10.3. The switches S and (S1, S2, S3) operate in pushpull state. The voltage across capacitor C1 is charged to Vin, voltage across capacitor C3 is charged to V1 and voltage across capacitor C5 is charged to V2 during switchon. The voltage across capacitor C2 is charged to V1 = 2VI, voltage across capacitor C4 is charged to V2 = 2V1 – ∆V2 and voltage across capacitor C6 is charged to VO = 2V2 – ∆V3 during switchoff. Therefore, the output voltage is VO = 2V2 − ∆V3 − Vin = 4V1 − 2 ∆V2 − ∆V3 − Vin = 7Vin − 4 ∆V1 − 2 ∆V2 − ∆V3
(10.4)
where ∆V3 is set for the same reason as ∆V1. 10.2.4
N/O Higher Order Lift Circuit
The N/O higher order lift circuit is can be designed by multiple repeating of the parts mentioned in previous sections. If the slave switches’ number is n, the output voltage of the nthlift circuit is n −1
VO = (2 n − 1)Vin −
∑ 2 ∆V i
i =0
© 2003 by CRC Press LLC
n− i
(10.5)
1956_C10.fm Page 510 Monday, August 18, 2003 3:22 PM
Iin
+
IO
s S1
C1
+ VC1 –
+ VC11 –
C11
–
Vin D1
D2 C2
–
D11 – VC2
D12 C12
+
R
VO
–
+
VC12 +
(a) Circuit diagram Iin +
Vin
C1
C11 + Vin – C2
–
+ V1+Vin – V1 C12 – V1 +
IO –
–
VC12 R
VO
+
+
(b) Equivalent circuit during switchingon (S on) C11 IO + C1 Vin C2 –
+ Vin – V1 – V1 +
+ V2+V – in C12
–
–
VC12 R
VO
+
+
(c) Equivalent circuit during switchingoff (S1 on) FIGURE 10.4 N/O elementary additional/enhanced circuit.
10.3 Additional Series The first three stages of the additional series are shown in Figure 10.4 to Figure 10.6. For convenience they are called N/O elementary additional circuit, N/O relift additional circuit, and N/O triplelift additional circuit respectively, and are numbered as n = 1, 2, and 3.
© 2003 by CRC Press LLC
1956_C10.fm Page 511 Monday, August 18, 2003 3:22 PM
10.3.1
N/O Elementary Additional Circuit
The N/O elementary additional circuit is derived from the N/O elementary circuit by adding a DEC. Its circuit diagram and its equivalent circuits during switchon and switchoff are shown in Figure 10.4. Two switches S and S1 operate in pushpull state. The voltage across capacitor C1 is charged to Vin during switchon. The voltage across capacitors C2 and C11 is charged to V1 = 2Vin during switchoff. Therefore, the output voltage is VO = V1 + Vin − Vin = 2Vin
(10.6)
Considering the voltage drops across the diodes and switches, we combine all values in a figure of ∆V1 and ∆VO (for additional output parts). The real output voltage is VO = 2Vin − ∆V1 − ∆VO
10.3.2
(10.7)
N/O ReLift Additional Circuit
The N/O relift additional circuit is derived from the N/O relift circuit by adding a DEC. Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 10.5. The switches S and (S1, S2) operate in pushpull state. The voltage across capacitor C1 is charged to Vin, voltage across capacitor C3 is charged to V1 and voltage across capacitor C11 is charged to V2 during switchon. The voltage across capacitor C2 is charged to V1 = 2Vin – ∆V1, voltage across capacitor C4 is charged to V2 = 2V1 – ∆V2 and voltage across capacitor C12 is charged to VO = V2 + V1 – ∆V2 – ∆VO during switchoff. Therefore, the output voltage is VO = V2 + V1 − ∆V2 − ∆VO − Vin = 5Vin − 3 ∆V1 − ∆V2 − ∆VO
(10.8)
where ∆V2 is set for the same reason as ∆V1. 10.3.3
N/O TripleLift Additional Circuit
The N/O triplelift additional circuit is derived from the N/O triplelift circuit by adding a DEC. Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 10.6. The switches S and (S1, S2, S3) operate in pushpull state. The voltage across capacitor C1 is charged to Vin, voltage across capacitor C3 is charged to V1, voltage across capacitor C5 is charged to V2 and voltage across capacitor C11 is charged to V3 during switchon. The voltage across capacitor C2 is charged to V1 = 2Vin – ∆V1, voltage across capacitor C4 is charged to V2 = 2V1 – ∆V2 and voltage across © 2003 by CRC Press LLC
1956_C10.fm Page 512 Monday, August 18, 2003 3:22 PM
Iin s
+
S1
+ D3 VC1 S2 – V1
C1
Vin D1
C3
D4 – VC2
D2 C2
–
IO + VC3 –
C11
D5
D11 – VC4
C4
+
+ VC11 – D12 C12
+
– R
VO
– VC12 +
+
(a) Circuit diagram Iin
C11 V2
+
IO
+ V2+V –
C3
+ Vin
C1
Vin
+ V1+Vin –
in
–
V1
–
C2 –
– V1 +
C12 – V2 +
C4
–
VC12 R
VO
+
+
(b) Equivalent circuit during switchingon (S on) C1
V1
C11 IO
+
+ Vin –
Vin
C2
– V1 +
C3 V2 C4
–
+ + V2+Vin – V1+Vin – C12 – V2 +
– VC12 R +
– VO +
(b) Equivalent circuit during switchingoff (S1 and S2 on) FIGURE 10.5 N/O relift additional circuit.
capacitor C6 is charged to V3 = 2V2 – ∆V3 during switchoff. Therefore, the output voltage is VO = V3 + V2 − ∆V3 − ∆VO − Vin = 11Vin − 6 ∆V1 − 3 ∆V2 − ∆V3 − ∆VO (10.9) where ∆V3 is set for the same reason as ∆V1.
© 2003 by CRC Press LLC
1956_C10.fm Page 513 Monday, August 18, 2003 3:22 PM
Iin s
D3
D6
+
IO S1
+ VC1 S2
C1
+ VC3 S3
C3
– V1
Vin
+ VC5
C5
– V2
–
+ VC11
C11
– VO
–
V3
R D1
D4 – VC2 +
D2 C2
–
D7 – VC4 +
D5 C4
D8
D11 –
D12
C6
VC6 +
C12
+
– VC12 +
(a) Circuit diagram Iin
C11 V3
+ + Vin
C1
+ V1+Vin
C3
C5
– V1 – V1 +
Vin – C2
–
IO
+ V3+V – + in V2+Vin –
–
V2 – V2 +
C4
– V3 +
C6
–
VC12 R
C12
VO
+
+
(b) Equivalent circuit during switchingon (S on) C1
C3
V1
C11 IO
+ + Vin – Vin
C2
– V1 +
V1+Vin+ –
–
C5
VC4
C4
V3
+
C6
–
+ + V3+Vin – V2+Vin – C12 – V3 +
– VC12 R +
– VO +
(c) Equivalent circuit during switchingoff (S1, S2, and S3 on) FIGURE 10.6 N/O triplelift additional circuit.
10.3.4
N/O Higher Order Lift Additional Circuit
The N/O higher order lift additional circuit is derived from the corresponding circuit of the main series by adding a DEC. The output voltage of the nthlift circuit is n −1
VO = 1.5 ∗ (2 Vin − n
∑ 2 ∆V i
i =1
© 2003 by CRC Press LLC
n− i
) − Vin − ∆Vn − ∆VO
(10.10)
1956_C10.fm Page 514 Monday, August 18, 2003 3:22 PM
Iin s
D3
+
IO S1
+ VC1
C1
Vin
C11
+ VC11 S2
– V1
+ VC3
C3
–
C21
+ VC21
–
– VO
– R
D1
D2 C2
–
D11 – VC2 +
D4 – VC12 +
D12 C12
D5
D21 –
D22
C4
VC4 +
C22
+
– VC22 +
(a) Circuit diagram Iin +
Vin
C1
C11 + Vin – C2
–
+ V1+Vin – V1 – V1 +
C3
+ VC3
C21
–
C12
– VC12 C4 +
+ V2+Vin – V2 C22 – V2 +
IO –
–
VC22 R +
VO +
(b) Equivalent circuit during switchingon (S on) C21
C11
IO + C1 Vin C2 –
+ Vin + V2+Vin – – – V1 VC12 C12 – V1 + +
C3
C4
+ VC3 + V3+Vin – – V2 C22 – V2 +
– VC22 R +
– VO +
(c) Equivalent circuit during switchingoff (S1, S2, and S3 on) FIGURE 10.7 N/O relift enhanced circuit.
10.4 Enhanced Series The first three stages of the enhanced series are shown in Figures 10.4, 10.7, and 10.8. For convenience, they are called N/O elementary enhanced circuit, N/O relift enhanced circuit, and N/O triplelift enhanced circuit respectively, and are numbered as n = 1, 2, and 3. © 2003 by CRC Press LLC
1956_C10.fm Page 515 Monday, August 18, 2003 3:22 PM
10.4.1
N/O Elementary Enhanced Circuit
The N/O elementary enhanced circuit is derived from N/O elementary circuit by adding a DEC. Its circuit diagram and its equivalent circuits during switchon and switchoff are shown in Figure 10.4. Therefore, the output voltage is VO = V1 + Vin − Vin = 2Vin
(10.6)
Considering the voltage drops across the diodes and switches, we combine all values in a figure of ∆V1 and ∆VO (for additional output parts). The real output voltage is VO = 2Vin − ∆V1 − ∆VO
10.4.2
(10.7)
N/O ReLift Enhanced Circuit
The N/O relift enhanced circuit is derived from the N/O relift circuit by adding the DEC in each stage circuit. Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 10.7. The switches S and (S1, S2) operate in pushpull state. The voltage across capacitor C1 is charged to Vin, voltage across capacitor C3 is charged to V1 and voltage across capacitor C11 is charged to V2 during switchon. The voltage across capacitor C2 is charged to V1 = 2Vin – ∆V1, voltage across capacitor C4 is charged to V2 = 2V1 – ∆V2 and voltage across capacitor C12 is charged to VO = V2 + V1 – ∆V2 – ∆VO during switchoff. Therefore, the output voltage is VO = V2 + V1 − ∆V2 − ∆VO − Vin = 8Vin − 3 ∆V1 − ∆V2 − ∆VO
(10.11)
where ∆V2 is set for the same reason as ∆V1. 10.4.3
N/O TripleLift Enhanced Circuit
The N/O triplelift enhanced circuit is derived from the N/O triplelift circuit by adding the DEC in each stage circuit. Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 10.8. The switches S and (S1, S2, S3) operate in pushpull state. The voltage across capacitor C1 is charged to Vin, voltage across capacitor C3 is charged to V1, voltage across capacitor C5 is charged to V2 and voltage across capacitor C11 is charged to V3 during switchon. The voltage across capacitor C2 is charged to V1 = 2Vin – ∆V1, voltage across capacitor C4 is charged to V2 = 2V1 – ∆V2 and voltage across capacitor C6 is charged to V3 = 2V2 – ∆V3 during switchoff. Therefore, the output voltage is © 2003 by CRC Press LLC
1956_C10.fm Page 516 Monday, August 18, 2003 3:22 PM
Iin s
D3
+
D6 IO
S1
+ VC1
C1
Vin
+ S2 VC11
C11
– V1
+ VC3 C21
C3
–
+ VC21
–
S3
C5
–
+ VC5
C31
+ VC31
– V1
– R
D1
D2 C2
–
D11 – VC2 +
D4 D5 – VC12 C4 +
D12 C12
D21 D22 – VC4 C22 +
–
D7
D8 C6
VC22 +
D31 – VC6 +
D32
– VO
– + VC32 +
C32
(a) Circuit diagram Iin + C1 Vin
+ C3 V1+Vin
C11 + Vin –
– V1 – V1C12 +
C2 –
+ VC3
+ C5 V2+Vin
C21
– – VC12 +
C4
– V2 – V2 C22 +
+ VC5
C31
– – VC22 +
C6
IO
+ V3+Vin – V3 C32 – V3 +
–
–
VC32R
VO
+
+
(b) Equivalent circuit during switchingon (S on) C21
C11
C31 IO
+
+ + – Vin V2+Vin – V1 C12 – V1 + C2
C1
Vin –
C3 – VC12 + C4
+ + – VC3 V3+Vin – V2 C22 – V2 +
C5 – VC22 + C6
+ + – VC5 V4+Vin – V3 C32 – V3 +
–
– VC32 R +
VO +
(c) Equivalent circuit during switchingoff (S1, S2, and S3 on)
FIGURE 10.8 N/O triplelift enhanced circuit.
VO = V3 + V2 − ∆V3 − ∆VO − Vin = 26Vin − 6 ∆V1 − 3 ∆V2 − ∆V3 − ∆VO
(10.12)
where ∆V3 is set for the same reason as ∆V1. 10.4.4
N/O Higher Order Lift Enhanced Circuit
The N/O higher order lift enhanced circuit is derived from the corresponding circuit of the main series by adding the DEC in each stage circuit. The output voltage of the nthlift circuit is n −1
VO = [(3 n − 1)Vin − © 2003 by CRC Press LLC
∑ 2 ∆V i
i =1
n− i
] − ∆Vn − ∆VO
(10.13)
1956_C10.fm Page 517 Monday, August 18, 2003 3:22 PM
Iin
+
IO
s S1
C1
+ VC1 –
C11
+ VC11 –
C13
+ VC13 –
–
Vin
R D1
D11 – VC2
D2 C2
–
D12 C12
+
D13 – VC12 +
D14
–
C14
VO +
VC14 +
(a) Circuit diagram Iin +
Vin
C11 + Vin –
C1
C2 –
+ V1+Vin C13 – V1 – V1 +
C12
IO
+ V2+V1 – V2 C14 – V2 +
– VC14 R
– VO
+
+
(b) Equivalent circuit during switchingon (S on) C13 IO + C1 Vin C2 –
+ C11 + Vin VC11 + V2+V1 – – – V1 V2 C14 – – V1 V2 + C12 +
–
–
VC14 R
VO
+
+
(c) Equivalent circuit during switchingoff (S1 on) FIGURE 10.9 N/O elementary reenhanced circuit.
10.5 ReEnhanced Series The first three stages of the reenhanced series are shown in Figure 10.9 to Figure 10.11. For convenience, they are called N/O elementary reenhanced circuit, N/O relift reenhanced circuit, and N/O triplelift reenhanced circuit respectively, and are numbered as n = 1, 2, and 3.
10.5.1
N/O Elementary ReEnhanced Circuit
The N/O elementary reenhanced circuit is derived from N/O elementary circuit by adding the DEC twice. Its circuit diagram and its equivalent circuits © 2003 by CRC Press LLC
1956_C10.fm Page 518 Monday, August 18, 2003 3:22 PM
during switchon and switchoff are shown in Figure 10.9. Two switches S and S1 operate in pushpull state. The voltage across capacitor C1 is charged to Vin during switchon. The voltage across capacitors C2 and C11 is charged to V1 = 2Vin during switchoff. The voltage across capacitors C12 and C13 is charged to VC12 = 4Vin during switchoff. Therefore, the output voltage is VO = VC12 − Vin = 3Vin
(10.14)
Considering the voltage drops across the diodes and switches, we combine all values in a figure of ∆V1 and ∆VO (for additional output parts). The real output voltage is VO = 3Vin − ∆V1 − ∆VO
10.5.2
(10.15)
N/O ReLift ReEnhanced Circuit
The N/O relift reenhanced circuit is derived from the N/O relift circuit by adding the DEC twice in each stage circuit. Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 10.10. The switches S and (S1, S2) operate in pushpull state. The voltage across capacitor C1 is charged to Vin, voltage across capacitor C3 is charged to V1 and voltage across capacitor C11 is charged to V2 during switchon. The voltage across capacitor C2 is charged to V1 = 2Vin – ∆V1, voltage across capacitor C4 is charged to V2 = 2V1 – ∆V2 and voltage across capacitor C12 is charged to VO = V2 + V1 – ∆V2 – ∆VO during switchoff. Therefore, the output voltage is VO = V2 + V1 − ∆V2 − ∆VO − Vin = 15Vin − 3 ∆V1 − ∆V2 − ∆VO
(10.16)
where ∆V2 is set for the same reason as ∆V1. 10.5.3
N/O TripleLift ReEnhanced Circuit
The N/O triplelift reenhanced circuit is derived from the N/O triplelift circuit by adding the DEC twice in each stage circuit. Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 10.11. The switches S and (S1, S2, S3) operate in pushpull state. The voltage across capacitor C1 is charged to Vin, voltage across capacitor C3 is charged to V1, voltage across capacitor C5 is charged to V2 and voltage across capacitor C11 is charged to V3 during switchon. The voltage across capacitor C2 is charged to V1 = 2Vin – ∆V1, voltage across capacitor C4 is charged to V2 = 2V1 – ∆V2 and voltage across capacitor C6 is charged to V3 = 2V2 – ∆V3 during switchoff. Therefore, the output voltage is VO = V3 + V2 − ∆V3 − ∆VO − Vin = 63Vin − 6 ∆V1 − 3 ∆V2 − ∆V3 − ∆VO © 2003 by CRC Press LLC
(10.17)
1956_C10.fm Page 519 Monday, August 18, 2003 3:22 PM
Iin s + S1
C1
+ VC1 –
C11
IO
+ D3 VC13 S2 –
+ VC11 C13 –
+ VC3 –
C3
+ VC21 C23 –
C21
+ VC23 –
–
Vin D1
D2 C2
–
D11 – VC2
D12 C12
+
D13 D14 – VC12 C14 +
D4
–
D5 C4
VC14 +
D21 – VC4
D22 C22
+
D23 D24 – VC22 C24 +
R
VO
–
+
VC24 +
(a) Circuit diagram Iin +
Vin
C11 + Vin –
C1
C2 –
+ V1+Vin C13 – V1 – V1
C12
+ C3 V2+V1
+ VC3 –
– V2 – C14 V2
C21
– VC14 +
C4
+ VC3+V3 C23 – V3 – V3
C22
IO
+ V4+V3 – V4 C24 – V4
–
–
VC24R
VO
+
+
(b) Equivalent circuit during switchingon (S on)
C13
C23 IO
+ C1 Vin C2 –
+ C11 + Vin VC11 + V2+V1 – – – V1 V2 C14 – – V1 V2 + C12 +
–
C3
VC14 C4
+
+ C21 + VC3 VC21 + V3+V4 – – – V3 V4 C24 – – V3 V4 + C22 +
–
–
VC24 R
VO
+
+
(c) Equivalent circuit during switchingoff (S1, S2, and S3 on) FIGURE 10.10 N/O relift reenhanced circuit.
where ∆V3 is set for the same reason as ∆V1. 10.5.4
N/O Higher Order Lift ReEnhanced Circuit
The N/O higher order lift reenhanced circuit is derived from the corresponding circuit of the main series by adding the DEC twice in each stage circuit. The output voltage of the nthlift circuit is n −1
VO = [( 4 − 1)Vin − n
∑ 2 ∆V i
i =1
© 2003 by CRC Press LLC
n− i
] − ∆Vn − ∆VO
(10.18)
s IO + VC1
+ S1
C1
+ VC11
C11
–
+ D3 VC13 S2 –
C13
–
+ VC3
C3
+ VC21
C21
–
+ D6 VC23
C23
–
S3
C5
+ VC5
+ VC31
C31
–
–
+ VC33
C33
–
–
–
Vin
R D1
D11 – VC2
D2 C2
–
D13 – VC12
D12 C12
+
D14
–
C14
D4
+
D21 – VC4
D5 C4
VC14 +
D22 C22
+
D23 – VC22
D7
D24
–
C24
VC24
+
D8 C6
D31 – VC6
D33 – VC32
D32 C32
+
+
D34
VO
–
C34
+
VC34
+
+
(a) Circuit diagram
Iin
+
C1
C11 +
C3
+
C13
V1+Vin
V2+V1
–
–
+ VC3 –
+
C21
C5
+
C23
VC3+V3
V4+V3
–
IO + VC5 –
C31
+
+
C33
VC5+V5
–
V5+V6
–
V1
–
V2 –
C2
V1 +
V4 –
+
V2 C12
V3
– VC14
C14 –
V3 C4
+
+
C24 –
V6 C34 –
–
+
V4 C22
V5
– VC24
V5 C6
+
VC34
R
VO
+ +
V6 C32
+
–
–
–
Vin
+
(b) Equivalent circuit during switchingon (S on) C13
C23
C33 IO
+
C1
+ C11 Vin – V1 –
Vin
+ VC11
C2
+ C12
V2+V1
C3
– –
– V2
C14
–
V1 –
+
V2 +
+ C21 VC3 – V3 –
VC14 +
V3 C4
+ C22
+
+
VC21 V3+V4 – V4 – V4 +
C5
–
C24
–
+ C31 VC5 – V5 –
VC24
V6
+ C6
+ C32
(c) Equivalent circuit during switchingoff (S1, S2, and S3 on) FIGURE 10.11 N/O triplelift reenhanced circuit.
© 2003 by CRC Press LLC
+
+
–
VC31 V5+V6 – V6 – V6 +
C34
– VC34 R +
– VO +
1956_C10.fm Page 520 Monday, August 18, 2003 3:22 PM
Iin
1956_C10.fm Page 521 Monday, August 18, 2003 3:22 PM
Iin
+
IO
s S1
C1
+ VC1 –
C11
+ VC11 –
+
C1(2j–1)
VC1(2j–1) –
Vin D1
D11 – VC2
D2 C2
–
D12 C12
+
D1(2j–1) –
D12j C12j
VC12 +
– R
VO
–
+
VC12j +
(a) Circuit diagram Iin +
Vin
C1
C11 + Vin – C2
–
+ V1+Vin – V1 C12 – V1 +
IO
C1(2j–1) + VC1(2j–1) – – VC12 C12j
VC12j
+
+
–
– R
VO +
(b) Equivalent circuit during switchingon (S on)
+
C1
C11 + Vin – C2
V1+Vin – V1 C12 – V1 +
IO
C1(2j–1) + VC1(2j–1) – – VC12 C12j
VC12j
+
+
–
– R
VO +
(c) Equivalent circuit during switchingoff (S1 on) FIGURE 10.12 N/O elementary multipleenhanced circuit.
10.6 MultipleEnhanced Series The first three stages of the multipleenhanced series are shown in Figure 10.12 to Figure 10.14. For convenience they are called N/O elementary multipleenhanced circuit, N/O relift multipleenhanced circuit and N/O triplelift multipleenhanced circuit respectively, and are numbered as n = 1, 2, and 3.
© 2003 by CRC Press LLC
1956_C10.fm Page 522 Monday, August 18, 2003 3:22 PM
Iin D3
s
IO + VC1
+ S1
C1
+ C1(2j–1) + VC11 VC1(2j–1) – –
C11
–
S2
+ VC3
C3
+ C2(2j–1) + VC21 VC2(2j–1) – –
C21
–
Vin D1
D11 – VC2
D2 C2
–
D12 C12
+
D1(2j–1) D12j – C12j VC12 +
–
D4
D21 – VC4
D5 C4
VC12j +
D2(2j–1) D22j – C22j VC22 +
D22 C22
+
R
– VO
–
+
VC22j +
(a) Circuit diagram Iin +
+
C1 Vin
C11 + Vin – C2
–
C1(2j–1) + C3 V1+Vin VC1(2j–1) – – – VC12 V1C12 – C12j + V1 +
+
+ VC3 –
C21
– VC12j +
C4
VC21 – V2 – C22 V2 +
C2(2j–1) + VC2(2j–1) – – VC22 C22j +
IO
–
–
VC22j R V O +
+
(b) Equivalent circuit during switchingon (S on)
C11
C21
C1(2j–1)
C2(2j–1) IO
C1
C2
+ Vin + V2+Vin – – V1 C12 – V1 +
C3
– VC1(2j–1) – VC12
C12j
– VC12j
+
+
C4
+ VC3 + – V2 – V2 +
VC21
–
C22
– VC2(2j–1) – VC22 +
C22j
–
–
VC22jR
VO
+
+
(c) Equivalent circuit during switchingoff (S1 and S2 on)
FIGURE 10.13 N/O relift multipleenhanced circuit.
10.6.1
N/O Elementary MultipleEnhanced Circuit
The N/O elementary multipleenhanced circuit is derived from the N/O elementary circuit by adding the DEC multiple (j) times. Its circuit diagram and its equivalent circuits during switchon and switchoff are shown in Figure 10.12. Two switches S and S1 operate in pushpull state. The voltage across capacitor C1 is charged to Vin during switchon. The voltage across capacitors C2 and C11 is charged to V1 = 2Vin during switchoff. The voltage across capacitors C1(2j–1) is charged to VC1(2j–1) = (1 + j)Vin during switchoff. Therefore, the output voltage is VO = VC1( 2 j −1) − Vin = jVin © 2003 by CRC Press LLC
(10.19)
D3
s
D6 IO
+ VC1
+ C1
S1
+ C1(2j– VC11 1) –
C11
–
+ VC1(2j–1) –
S2
C3
+ VC3
+ C2(2j– VC21 1) –
C21
–
+ VC5
+ VC2(2j–1) –
S3
C5
+ C3(2j– VC31 1) –
C31
–
+ VC3(2j–1) –
–
Vin D1
D11 – VC2
D2 C2
–
D1(2j–1) D12j – C12j VC12
D12 C12
+
+
–
D4
VC12j
D21 – VC4
D5 C4
+
D2(2j–1) D22j – VC22 C22j
D22 C22
+
–
D7
+
D31 – VC6
D8 C6
VC22j
D3(2j–1) D32j – VC32 C32j
D32 C32
+
+
R
VO
–
+
VC32j
+
+
(a) Circuit Diagram
Iin
+ C11 + Vin –
C1
V1+Vin –
C3
+ VC1(2j–1)
+
+ VC3 –
C21
C12j
+
– VC12j +
VC2(2j–1)
– C22 V2 +
+
+ VC5 –
C31
VC31 –
–
VC22
V2 C4
C5
+
C2(2j– 1) –
VC21 –
–
VC12
V1C12 – V1 +
C2
C1(2j– 1) –
C22j
+
– VC22j +
V3 – C32 V3 +
C6
IO
+
C3(2j– 1) –
VC3(2j–1)
VC32
C32j
–
–
VC32j
+
+
– R
VO +
(b) Equivalent circuit switchingon (S on) C11
+
C1
+ Vin – V1 –
Vin
+
V2+Vin
C1(2j– 1) –
C12
V1 –
C2
+V – C1(2j–1) – VC12
C3
– V2 –
VC12j +
+
+ VC3
–
C12j +
C2(2j– 1)
C21
V2 C4
+
+
VC21 C22
–
+
VC2(2j–1) –
C31
VC22 +
C5
– –
VC5 – V3 –
VC22j
C22j +
V3 C6
(c) Equivalent circuit switchingoff (S1 and S2 and S3 on) FIGURE 10.14 N/O triplelift multipleenhanced circuit.
© 2003 by CRC Press LLC
+
+
+
VC31 C32
C3(2j– 1) –
+
VC3(2j–1) –
IO –
VC32 +
– VC32j R
– VO
C32j +
+
1956_C10.fm Page 523 Monday, August 18, 2003 3:22 PM
Iin
1956_C10.fm Page 524 Monday, August 18, 2003 3:22 PM
Considering the voltage drops across the diodes and switches, we combine all values in a figure of ∆V1 and ∆VO (for additional output parts). The real output voltage is VO = jVin − ∆V1 − ∆VO
10.6.2
(10.20)
N/O ReLift MultipleEnhanced Circuit
The N/O relift multipleenhanced circuit is derived from the N/O relift circuit by adding the DEC multiple (j) times in each stage circuit. Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 10.13. The switches S and (S1, S2) operate in pushpull state. The voltage across capacitor C1 is charged to Vin, voltage across capacitor C3 is charged to V1 and voltage across capacitor C11 is charged to V2 during switchon. The voltage across capacitor C2 is charged to V1 = 2Vin – ∆V1, voltage across capacitor C4 is charged to V2 = 2V1 – ∆V2 and voltage across capacitor C12 is charged to VO = V2 + V1 – ∆V2 – ∆VO during switchoff. Therefore, the output voltage is VO = V2 + V1 − ∆V2 − ∆VO − Vin = [(1 + j )2 − 1]Vin − 3 ∆V1 − ∆V2 − ∆VO
(10.21)
where ∆V2 is set for the same reason as ∆V1. 10.6.3
N/O TripleLift MultipleEnhanced Circuit
The N/O triplelift multipleenhanced circuit is derived from the N/O triplelift circuit by adding the DEC multiple (j) times in each stage circuit.. Its circuit diagram and equivalent circuits during switchon and switchoff are shown in Figure 10.14. The switches S and (S1, S2, S3) operate in pushpull state. The voltage across capacitor C1 is charged to Vin, voltage across capacitor C3 is charged to V1, voltage across capacitor C5 is charged to V2 and voltage across capacitor C11 is charged to V3 during switchon. The voltage across capacitor C2 is charged to V1 = 2Vin – ∆V1, voltage across capacitor C4 is charged to V2 = 2V1 – ∆V2 and voltage across capacitor C6 is charged to V3 = 2V2 – ∆V3 during switchoff. Therefore, the output voltage is VO = V3 + V2 − ∆V3 − ∆VO − Vin = [(1 + j ) 3 − 1]Vin − 6 ∆V1 − 3 ∆V2 − ∆V3 − ∆VO where ∆V3 is set for the same reason as ∆V1. © 2003 by CRC Press LLC
(10.22)
1956_C10.fm Page 525 Monday, August 18, 2003 3:22 PM
10.6.4
N/O Higher Order Lift MultipleEnhanced Circuit
The N/O higher order lift multipleenhanced circuit is derived from the corresponding circuit of the main series by adding the DEC multiple (j) times in each stage circuit. The output voltage of the nth order lift circuit is n −1
VO = [(1 + j )n − 1]Vin −
∑ 2 ∆V i
n− i
− ∆Vn − ∆VO
(10.23)
i =1
10.7 Summary of This Technique Using this technique, it is easy to design N/O higher order lift circuits to obtain high output voltage. All these converters can be sorted in several subseries: main series, additional series, enhanced series, reenhanced series, and multipleenhanced series. The output voltage of the nthlift circuit is n −1 2n − 1 Vin − 2i ∆Vn−1 i =0 n −1 1.5 ∗ 2n − 1 Vin − 2i ∆Vn−1 − ∆Vn − ∆VO i =0 n −1 2i ∆Vn−1 − ∆Vn − ∆VO VO = 3n − 1 Vin − i =0 n −1 n 4 − 1 Vin − 2i ∆Vn−1 − ∆Vn − ∆VO i =0 n −1 n (2 + j ) − 1 V − 2i ∆Vn−1 − ∆Vn − ∆VO in i =0
(
(
[
∑
)
∑
)
Main _ series Additional _ series
(
)
∑
Enhanced _ series
(
)
∑
Re Enhanced _ series
] ∑
Multiple  Enhanced _ series
(10.24)
From above formula, the family tree of negative output multiplelift pushpull switchedcapacitor Luoconverters is shown in Figure 10.15.
10.8 Simulation and Experimental Results To verify the design and calculation results, PSpice simulation package was applied for these circuits. Choosing VI = 10 V, all capacitors Ci = 2 µF, R = 60 k, k = 0.5 and f = 100 kHz, the voltage and current values are obtained from a N/O triplelift circuit. The same conditions are applied to a test rig, experimental results are then obtained. 10.8.1
Simulation Results
Assume that the voltage drops ∆V1, ∆V2, and ∆V3 are about 4.2 V, the voltage values of V1, V2, and VO to be –5.2 V, –16 V, and –41 V respectively and © 2003 by CRC Press LLC
1956_C10.fm Page 526 Monday, August 18, 2003 3:22 PM
Main Series
Additional Series
Enhanced Series
N/O QuintupleLift Circuit
N/O QuintupleLift Additional Circuit
N/O QuintupleLift Enhanced Circuit
N/O QuintupleLift Reenhanced Circuit
N/O QuintupleLift MultipleEnhanced Circuit
N/O QuadrupleLift Circuit
N/O QuadrupleLift Additional Circuit
N/O QuadrupleLift Enhanced Circuit
N/O QuadrupleLift Reenhanced Circuit
N/O QuadrupleLift MultipleEnhanced Circuit
N/O TripleLift Enhanced Circuit
N/O TripleLift Reenhanced Circuit
N/O TripleLift MultipleEnhanced Circuit
N/O Relift Enhanced Circuit
N/O Relift Reenhanced Circuit
N/O Relift MultipleEnhanced Circuit
N/O TripleLift Circuit
N/O TripleLift Additional Circuit
N/O Relift Circuit
N/O Relift Additional Circuit
Reenhanced Series
N/O Elementary Additional/Enhanced Circuit
N/O Elementary Reenhanced Circuit
MultipleEnhanced Series
N/O Elementary MultipleEnhanced Circuit
Elementary Negative Output MultipleLift PushPull SC LuoConverter FIGURE 10.15 The family tree of N/O multiplelift pushpull switchedcapacitor Luoconverters.
(1.9851m, 10.3)
10A
(1.9851m, 7.6)
(1.9969m, 93m)
5A
SEL>> 1A I(D2)
I(D5)
I(D8)
0V (1.99m, 5.2) 25V
(1.99m, 16) (1.99m, 41)
50V 1.980ms V(D7:2)
1.985ms V(D4:2)
1.990ms
1.995ms
2.000ms
V(R:2) Time
FIGURE 10.16 The simulation results of a N/O triplelift circuit at condition k = 0.5 and f = 100 kHz. © 2003 by CRC Press LLC
1956_C10.fm Page 527 Monday, August 18, 2003 3:22 PM
FIGURE 10.17 Experimental results of a N/O triplelift circuit at condition k = 0.5 and f = 100 kHz.
current waveforms of ID2, ID5, and ID8 (the leak values are 103 A, 6.7 A, and 0.093 A respectively) are obtained. The simulation results voltage values in Figure 10.16 are identically matched to the calculated results. 10.8.2 Experimental Results Assuming that the voltage drops ∆V1, ∆V2, and ∆V3 are still about 4.2 V, the output voltage VO (–41 V) and current waveform of ID2 (leak value is 10.3 A) are obtained and shown in Figure 10.17, which are identically matched to the calculated and simulation results.
Bibliography Bhat, A.K.S., A fixedfrequency modified seriesresonant converter: analysis design, and experimental results, IEEE Trans. On Power Electronics, 10, 454, 1995. Harada, K., Katsuki, A., Fujiwara, M., Nakajuma, H., and Matsushita, H., Resonant converter controlled by variable capacitance devices, IEEE Trans. On Power Electronics, 8, 404, 1993. Hua, G., Leu, C., and Lee, F.C., Novel zerovoltagetransition PWM converters, in Proceedings of IEEE PESC’92, 1992, p. 557. Wang, K., Lee, F.C., Hua, G., and Borojevic, D., A comparative study of switching losses of IGBTS under hardswitching, zerovoltageswitching and zerocurrentswitching, in Proceedings of IEEE PESC '94, Record, 1994, p. 1196. Jovanovic, M.M., Lee, F.C., and Chen, D.Y., A zerocurrentswitched offline quasiresonant converter with reduced frequency range: analysis, design, and experimental results, IEEE Trans. on PE, 4, 215, 1987. Luo, F. L. and Ye, H., Negative output multiplelift pushpull switchedcapacitor Luoconverters, in Proceedings of IEEEPESC’2003, Acapulco, Mexico, 2003, p. 1571. Petterteig, A., Lode, J., and Undeland, T. M., IGBT turnoff losses for hard switching and with capacitive snubbers, in Proceedings of IEEE Industry Applications Society Annual Meeting, 1991, p. 1501. © 2003 by CRC Press LLC
1956_C11.fm Page 529 Monday, August 18, 2003 3:19 PM
11 MultipleQuadrant SoftSwitch Converters
The third generation converters can transfer large amounts of power with high power density to actuators. However, its power losses are usually high during the transfer of large amounts of power since the power losses across the switch devices are high. The soft switch technique is an effective way to reduce the converter power losses and improve the efficiency. Therefore, it is a very popular method in industrial applications. The fourth generation converters are called softswitch converters. The softswitch technique involves many methods implementing resonance characteristics. A popular method is the resonantswitch. Softswitch converters are mainly implemented by the resonant technique. The resonant converters have drawn much attention in research applications. They are sorted into four categories: • • • •
Loadresonant converters ResonantDClink converters Highfrequencylink integralhalfcycle converters Resonantswitch converters
The converters of the first, second, and third catagories can be applied in those cases depending on the load components and linkingcable. The converters of the fourth catagory are applied in the case depending on the resonant circuit in the switchend, which are independent from load and link components. After about two decades of investigation and application, most industrial applications use resonantswitch converters. Resonantswitch converters can perform in the overresonant state, critical/optimumresonant state, and quasiresonant state. In order to determine two (current/voltage) zerocross points for switchon and switchoff, the quasiresonant state is usually employed. The corresponding converter is called quasiresonant converter (QRC).The quasiresonant state can perform in fullwaveform mode and halfwaveform mode. The clue of soft switch technique focuses on the zerocross point rather than the resonance. Consequently, there is no need in performing fullwaveform mode. Most soft switch converters perform in halfwaveform mode.
© 2003 by CRC Press LLC
1956_C11.fm Page 530 Monday, August 18, 2003 3:19 PM
The zerocurrentswitch (ZCS) quasiresonantconverters (QRC), zerovoltageswitch (ZVS) quasiresonantconverters (QRC) and zerotransition (ZT) converters will be discussed in this chapter,.
11.1 Introduction Zerocurrentswitch quasiresonantconverters implement ZCS operation. Since switches turnon and turnoff at the moment that the current is equal to zero, the power losses during switchon and off become zero. Consequently, these converters have high power density and transfer efficiency. Usually, the repeating frequency is not very high and the converter works in the resonance state, the components of higher order harmonics is very low. Therefore, the electromagnetic interference (EMI) is low, and electromagnetic susceptibility (EMS) and electromagnetic compatibility (EMC) are reasonable. Zerovoltageswitch quasiresonantconverters use the ZVS technique. Since switches turnon and turnoff at the moment that the voltage is equal to zero, the power losses during switchon and off become zero. Consequently, these converters have high power density and transfer efficiency. Usually, the repeating frequency is not very high and the converter works in the resonance state, the components of higher order harmonics is very low, so that the EMI is low, and EMS and EMC are reasonable. ZCSQRC and ZVSQRC have large voltage and current stresses. In addition the conduction duty cycle k and switch frequency f are not individually adjusted. In order to overcome these drawbacks we designed zerovoltagepluszerocurrentswitches (ZV/ZCS) and zerotransition (ZT) converters, which implement the ZVS and ZCS technique. Since switches turnon and off at the moment that the voltage and/or current is equal to zero, the power losses during switchon and off become zero. Consequently, these converters have high power density and transfer efficiency. Usually, the repeating frequency is not very high and the converter works in the resonance state, the components of higher order harmonics is very low, so that the EMI is low, and EMS and EMC are reasonable. The ZCS technique significantly reduces the power losses across the switches during the switchon and switchoff. Unfortunately, most papers discuss the converters only working at single quadrant operation. This paper introduces the multiplequadrant DC/DC ZCS quasiresonant Luoconverter. It performs the soft switch technique with a fourquadrant operation, which effectively reduces the power losses and largely increases the power transfer efficiency. The results obtained from analysis and design were compared and verified by practical test results.
© 2003 by CRC Press LLC
1956_C11.fm Page 531 Monday, August 18, 2003 3:19 PM
i1
S1
iL
Lr 1
Sa
2
+
D1
V1 –
L r2
Cr
1
L + V2 –
S2
D2
(a) Circuit 1 for the operation in Quadrant I and Quadrant II D1 i1
S1
+
4
Sa
D2
3
Lr
S2 L r
1
2
V1 –
Cr
L
– V2 +
(b) Circuit 2 for the operation in Quadrant III and Quadrant IV D1 S1
2/4
Sa
1/3
L r1 iL
ir
D2
L
S2
+ V1 –
L r2
S3
Cr 1/2
3/4
1/2 +– V 2
3/4
(c) Circuit 3 for the Fourquadrant operation FIGURE 11.1 Fourquadrant DC/DC ZCS quasiresonant Luoconverter.
11.2 MultipleQuadrant DC/DC ZCS QuasiResonant LuoConverters A multiplequadrant DC/DC ZCS quasiresonant Luoconverter is shown in Figure 11.1. Circuit 1 implements the operation in quadrants I and II, i.e., two quadrant (I and II) 2CS quasiresonant Luoconverters. Circuit 2 implements the operation in quadrants III and IV, i.e., two quadrant (III and IV) 2CS quasiresonant Luoconverters. Circuit 1 and circuit 2 can be converted to each other by auxiliary changeover switch S3. Auxiliary switch Sa assists the twoquadrant operation in the same circuit. It is controlled by a logic quadrantoperation controller. Each circuit consists of one main inductor L and two switches. Assuming that the main inductance L is sufficient large, © 2003 by CRC Press LLC
1956_C11.fm Page 532 Monday, August 18, 2003 3:19 PM
TABLE 11.1 Switch Status Mode A (QI) Mode B (QII) Mode C (QIII) Mode D (QIV) Circuit //Switch or Diode Stateon Stateoff Stateon Stateoff Stateon Stateoff Stateon Stateoff Circuit Circuit 1 Circuit 2 S1 ON ON D1 ON ON S2 ON ON D2 ON ON Sa Position 1 Position 2 Position 3 Position 4 Note: The blank status means off.
the current iL remains constant. The source and load voltages are usually constant, e.g., V1 = 42 V and V2 = ± 28 V. There are four modes of operation: 1. Mode A (quadrant I) : electrical energy is transferred from V1 side to V2 side. 2. Mode B (quadrant II): electrical energy is transferred from V2 side to V1 side. 3. Mode C (quadrant III) : electrical energy is transferred from V1 side to –V2 side. 4. Mode D (quadrant IV): electrical energy is transferred from –V2 side to V1 side. Each mode has two states: on and off. The switch status of each state is shown in Table 11.1.
11.2.1
Mode A
Mode A is a ZCS buck converter. The equivalent circuit, current, and voltage waveforms are shown in Figure 11.2. There are four time regions for the switchon and off period. The conduction duty cycle is kT = (t1 + t2) when the input current flows through the switch S1 and the main inductor L. The whole period is T = (t1 + t2 + t3 + t4). The resonance circuit is Lr1 – Cr . The natural resonance frequency is ω1 =
1 Lr 1Cr
(11.1)
Lr 1 Cr
(11.2)
and the normalized impedance is Z1 = © 2003 by CRC Press LLC
1956_C11.fm Page 533 Monday, August 18, 2003 3:19 PM
iLr1
IL
S1 L r1 + vc Cr –
+ V1 –
+ V2 –
D2
(a) Equivalent Circuit
iLr1 0
V1 /Z 1
IL t1
t2
t3
t4
t3
t4
vc0 V1 vc
V1 0
t1
t2
(b) Waveforms FIGURE 11.2 Mode A operation.
The resonant current (AC component) is i r (t ) =
V1 sin(ω 1t + α 1 ) Z1
(11.3)
Considering the DC component IL, the peak current is i1− peeak = I L +
11.2.1.1
V1 Z1
(11.4)
Interval t = 0 to t1
Switch S1 turns on at t = 0, the source current increases linearly with the slope V1/Lr1; this is called current linear rising interval. This current is smaller than the constant load current IL. Therefore, no current flows through the resonant capacitor Cr . When t = t1, it is equal to IL. Therefore, the time is t1 = © 2003 by CRC Press LLC
I L Lr 1 V1
(11.5)
1956_C11.fm Page 534 Monday, August 18, 2003 3:19 PM
And corresponding angular position is α 1 = sin −1 (
11.2.1.2
I L Z1 ) V1
(11.6)
Interval t = t1 to t2
In this period the current flows through the resonant capacitor Cr . Circuit Lr1 – Cr . resonates; this is the resonance interval. The current waveform is a sinusoidal function. After its peak value, current descends down to IL, and then 0 if the converter works in subresonance state. Switch S1 turns off at t = t2. At this point we can see that the switch S1 turns off at zero current condition. This period length is t2 =
1 ( π + α 1) ω1
(11.7)
Simultaneously, the voltage across the capacitor Cr . is a sinusoidal function as well. When t = t2, the corresponding value vCO of the capacitor voltage vC is vCO = V1[1 + sin(π / 2 + α 1)] = V1(1 + cos α 1 ) 11.2.1.3
(11.8)
Interval t = t2 to t3
Since the switch S1 does not allow the resonant current to flow reversibly, the charge across the capacitor Cr will be discharged by the load current IL; this is the linear recovering interval. Because load current IL is a constant current the voltage vC decreases linearly from vCO to 0 at t = t3. t3 =
11.2.1.4
vCO Cr IL
(11.9)
Interval t = t3 to t4
Capacitor voltage vC cannot decrease to negative value because of the freewheeling diode D2; this is the normal switchoff interval. The load current commutates from Cr to D2 at t = t3. Since then, the load current freewheels through the main inductor L, load voltage source V2 and freewheeling diode D2. The time length t4 of this period depends on the design requirement. Ignoring the power losses and I2 = IL, we have the input average current I1: I1 = © 2003 by CRC Press LLC
I LV2 t1 + t2 V 2 cos α 1 = (IL + 1 ) V1 T Z1 π / 2 + α 1
(11.10)
1956_C11.fm Page 535 Monday, August 18, 2003 3:19 PM
Therefore, t4 =
V1 (t1 + t2 ) V 2 cos α 1 (IL + 1 ) − (t1 + t2 + t3 ) V2 I L Z1 π / 2 + α 1
(11.11)
We have the conduction duty t1 + t2 t1 + t2 + t3 + t4
(11.12)
T = t1 + t2 + t3 + t4
(11.13)
k= The whole repeating period is
And corresponding frequency is f = 1/ T
11.2.2
(11.14)
Mode B
Mode B is a ZCS boost converter. The equivalent circuit, current and voltage waveforms are shown in Figure 11.3. There are four time regions for the switchon and off period. The conduction duty cycle is kT = (t1 + t2), but the output current only flows through the source V1 in the period t4. The whole period is T = (t1 + t2 + t3 + t4). The resonance circuit is Lr2 – Cr . The resonance frequency is ω2 =
1 Lr 2 Cr
(11.15)
and the normalized impedance is Z2 =
Lr 2 Cr
(11.16)
The resonant current (AC component) is i r (t ) =
© 2003 by CRC Press LLC
V1 sin(ω 2 t + α 2 ) Z2
(11.17)
1956_C11.fm Page 536 Monday, August 18, 2003 3:19 PM
IL
D1 L r2
+ vc Cr –
+ V1 –
iLr2
S2
+ V2 –
(a) Equivalent Circuit
iLr2 0
V1/Z2
IL t1
t2
t3
t4
vc
V1
V1 0
V1 t1
vc0
t2
t3
t4
(b) Waveforms FIGURE 11.3 Mode B operation.
Considering the DC component IL, the peak current is i2− peeak = I L +
11.2.2.1
V1 Z2
(11.18)
Interval t = 0 to t1
Switch S2 turns on at t = 0, the voltage across capacitor Cr is equal to V1. The inductor current iLr2 increases linearly with the slope V1/Lr1. This current is smaller than the constant load current IL. Therefore, no current flows through the resonant capacitor Cr . When t = t1, it is equal to IL. Therefore, the time is t1 =
I L Lr 2 V1
(11.19)
and corresponding angular position is α 2 = sin −1 ( © 2003 by CRC Press LLC
I L Z2 ) V1
(11.20)
1956_C11.fm Page 537 Monday, August 18, 2003 3:19 PM
11.2.2.2
Interval t = t1 to t2
In this period the current flows through the resonant capacitor Cr . Circuit Lr2 – Cr . resonates. The current waveform is a sinusoidal function. After its peak value, current descends down to IL, and then 0 if the converter works in subresonance state. Switch S2 turns off at t = t2. At this point we can see that the switch S2 turns off at zero current condition. This period length is t2 =
1 (π + α 2 ) ω2
(11.21)
Simultaneously, the voltage across the capacitor Cr . is a sinusoidal function as well. When t = t2, the corresponding value vCO of the capacitor voltage vC is vCO = −V1 sin(π / 2 + α 2 ) = −V1 cos α 2 11.2.2.3
(11.22)
Interval t = t2 to t3
Since the switch S2 does not allow the resonant current to flow reversibly, the charge across the capacitor Cr will be discharged by the load current IL. Because load current IL is a constant current the voltage vC increases linearly from vCO to V1 at t = t3. t3 =
11.2.2.4
(V1 − vCO )Cr IL
(11.23)
Interval t = t3 to t4
Capacitor voltage vC cannot be higher than V1 because of the diode D1 conducted. The main inductor current commutates from Cr to D1 at t = t3. Since then, the load current flows through the main inductor L, diode D1 source voltage V1 and load voltage V2. The time length t4 of this period depends on the design requirement. Ignoring the power losses and I2 = IL, we have the output average current I1: I1 =
I LV2 t4 = IL V1 T
(11.24)
or V2 t4 t4 = = V1 T t1 + t2 + t3 + t4 © 2003 by CRC Press LLC
(11.25)
1956_C11.fm Page 538 Monday, August 18, 2003 3:19 PM
Therefore, t1 + t2 + t3 V1 / V2 − 1
(11.26)
t1 + t2 t1 + t2 + t3 + t4
(11.27)
T = t1 + t2 + t3 + t4
(11.28)
t4 = We have the conduction duty k= The whole repeating period is
and corresponding frequency is f = 1/ T
11.2.3
(11.29)
Mode C
Mode C is a ZCS buckboost converter. The equivalent circuit, current and voltage waveforms are shown in Figure 11.4. There are four time regions for the switchon and off period. The conduction duty cycle is kT = (t1 + t2) when the input current flows through the switch S1 and the main inductor L. The output current only flows through V2 in t4. The whole period is T = (t1 + t2 + t3 + t4). The resonance circuit is Lr1 – Cr . The resonance frequency is ω1 =
1 Lr 1Cr
(11.30)
and the normalized impedance is Z1 =
Lr 1 Cr
(11.31)
The resonant current (AC component) is i r (t ) = © 2003 by CRC Press LLC
V1 sin(ω 1t + α 1 ) Z1
(11.32)
1956_C11.fm Page 539 Monday, August 18, 2003 3:19 PM
iLr1
S1 L r1
D2
+ vc Cr –
+ V1 –
– V2 +
IL
(a) Equivalent Circuit
V1/Z1
iL r1 0
IL
t2' t1
t2
vc 0
t3
t4
V1
vc
t3'
V1 V2 0
V2
V1 t2
t1
t3
t4
(b) Waveforms FIGURE 11.4 Mode C operation.
Considering the DC component IL, the peak current is i1− peeak = I L +
11.2.3.1
V1 Z1
(11.33)
Interval t = 0 to t1
Switch S1 turns on at t = 0, the voltage across capacitor Cr is equal to V2. The inductor current iLr1 increases linearly with the slope (V1 + V2)/Lr1. This current is smaller than the constant load current IL. Therefore, no current flows through the resonant capacitor Cr . When t = t1, it is equal to IL. Therefore, the time t1 =
I L Lr 1 V1 + V2
(11.34)
and corresponding angular position is α 1 = sin −1 ( © 2003 by CRC Press LLC
I L Z1 ) V1
(11.35)
1956_C11.fm Page 540 Monday, August 18, 2003 3:19 PM
Before S1 turns on at t = 0, freewheeling diode D2 is conducted. Therefore the capacitor voltage vC across the resonant capacitor Cr is equal to V2 in this interval. 11.2.3.2
Interval t = t1 to t2
In this period the current flows through the resonant capacitor Cr . Circuit Lr1 – Cr . resonates. The current waveform is a sinusoidal function. After its peak value, current descends down to IL, and then 0 if the converter works in subresonance state. Switch S1 turns off at t = t2. At this point we can see that the switch S1 turns off at zero current condition. This period length is t2 =
1 ( π + α 1) ω1
(11.36)
Simultaneously, the voltage across the capacitor Cr . is a sinusoidal function as well. The resonant amplitude is equal to V1. When t = t2, the corresponding value vCO of the capacitor voltage vC is vCO = V1 − V2 + V1 sin(π / 2 + α 1) = V1(1 + cos α 1 ) − V2 11.2.3.3
(11.37)
Interval t = t2 to t3
Since the switch S1 does not allow the resonant current to flow reversibly, the charge across the capacitor Cr will be discharged by the load current IL. Because load current IL is a constant current the voltage vC decreases linearly from vCO to –V2 at t = t3. In this interval, the freewheeling diode D2 does not conduct because it is reversibly biased. t3 =
11.2.3.4
(vCO + V2 )Cr IL
(11.38)
Interval t = t3 to t4
Capacitor voltage vc is equal to V2 at t = t3, the freewheeling diode D2 then conducted. The main inductor current commutates from Cr to V2 at t = t3. Since then, the load current freewheels through the main inductor L, load voltage source V2 and freewheeling diode D2. The time length t4 of this period depends on the design requirement. Ignoring the power losses, we have the input average current I1: I1 = © 2003 by CRC Press LLC
t1 + t2 V 2 cos α 1 (IL + 1 ) T Z1 π / 2 + α 1
(11.39)
1956_C11.fm Page 541 Monday, August 18, 2003 3:19 PM
and t4 I T L
(11.40)
V1 (t1 + t2 ) V 2 cos α 1 (IL + 1 ) V2 I L Z1 π / 2 + α 1
(11.41)
I2 = Therefore, t4 =
We have the conduction duty t1 + t2 t1 + t2 + t3 + t4
(11.42)
T = t1 + t2 + t3 + t4
(11.43)
k= The whole repeating period is
and corresponding frequency is f = 1/ T
11.2.4
(11.44)
Mode D
Mode D is a ZCS buckboost converter. The equivalent circuit, current and voltage waveforms are shown in Figure 11.5. There are four time regions for the switchon and off period. The conduction duty cycle is kT = (t1 + t2), but the output current only flows through the source V1 in the period t4. The whole period is T = (t1 + t2 + t3 + t4). The resonance circuit is Lr2 – Cr . The resonance frequency is ω2 =
1 Lr 2 Cr
(11.45)
and the normalized impedance is Z2 =
© 2003 by CRC Press LLC
Lr 2 Cr
(11.46)
1956_C11.fm Page 542 Monday, August 18, 2003 3:19 PM
S2 L r2
D1 +
iLr2
+ vc Cr –
V1 –
– V2 +
IL
(a) Equivalent Circuit
iLr2 0
t2'
V2/Z2
IL t1
t2 V2
V1
t3
t4
vc t3'
V1
V1–V2
0
V2 t1
vc0
t2
t3
t4
(b) Waveforms FIGURE 11.5 Mode D operation.
The resonant current (AC component) is i r (t ) =
V1 sin(ω 2 t + α 2 ) Z2
(11.47)
Considering the DC component IL, the peak current is i2− peeak = I L +
11.2.4.1
V1 Z2
(11.48)
Interval t = 0 to t1
Switch S2 turns on at t = 0, the voltage across capacitor Cr is equal to V1. The inductor current iLr2 increases linearly with the slope (V1 + V2)/Lr21. This current is smaller than the constant load current IL. Therefore, no current flows through the resonant capacitor Cr . When t = t1, it is equal to IL. Therefore, the time t1 = © 2003 by CRC Press LLC
I L Lr 2 V1 + V2
(11.49)
1956_C11.fm Page 543 Monday, August 18, 2003 3:19 PM
and corresponding angular position is α 2 = sin −1 (
11.2.4.2
I L Z2 ) V2
(11.50)
Interval t = t1 to t2
In this period the current flows through the resonant capacitor Cr . Circuit Lr2 – Cr . resonates. The current waveform is a sinusoidal function. After its peak value, current descends down to IL, and then 0 if the converter works in subresonance state. Switch S2 turns off at t = t2. At this point we can see that the switch S2 turns off at zero current condition. This period length is t2 =
1 ( π +α 2 ) ω2
(11.51)
Simultaneously, the voltage across the capacitor Cr . is a sinusoidal function as well. When t = t2, the corresponding value vCO of the capacitor voltage vC is vCO = (V1 − V2 ) − V2 sin(π / 2 + α 2 ) = V1 − V2 (1 + cos α 2 ) 11.2.4.3
(11.52)
Interval t = t2 to t3
Since the switch S2 does not allow the resonant current to flow reversibly, the charge across the capacitor Cr will be discharged by the load current IL. Because load current IL is a constant current the voltage vC increases linearly from vCO to V1 at t = t3. t3 =
11.2.4.4
(V1 − vCO )Cr V2 Cr = (1 + cos α 2 ) IL IL
(11.53)
Interval t = t3 to t4
Capacitor voltage vC cannot be higher than V1 because of the diode D1 conducted. The main inductor current commutates from Cr to D1 at t = t3. Since then, the output current I1 flows through the main inductor L, diode D1 source voltage V1 and load voltage V2. The time length t4 of this period depends on the design requirement. Ignoring the power losses, we have the output average current I1: I1 = © 2003 by CRC Press LLC
I LV2 t4 = IL V1 T
(11.54)
1956_C11.fm Page 544 Monday, August 18, 2003 3:19 PM
and t1 + t2 V 2 cos α 2 (IL + 2 ) T Z2 π / 2 + α 2
(11.55)
V2 (t1 + t2 ) V 2 cos α 2 (IL + 2 ) V1 I L Z2 π / 2 + α 2
(11.56)
I2 = Therefore, t4 =
We have the conduction duty t1 + t2 t1 + t2 + t3 + t4
(11.57)
T = t1 + t2 + t3 + t4
(11.58)
k= The whole repeating period is
And corresponding frequency is f = 1/ T
11.2.5
(11.59)
Experimental Results
A testing rig with a battery of ±28 VDC as a load and a source of 42 VDC as the power supply was tested. The testing conditions are : V1 = 42 V and V2 = ±28 V, L = 30 µH, Lr1 = Lr2 = 1 µH, C r = 4 µF and the volume is 40 in3. The experimental results are shown in Table 11.2. The average power transfer efficiency is 96.3%, and the total average power density (PD) is 17.1 W/in3. This figure is much higher than the classical converters whose PD is usually less than 5 W/in3. Since the switch frequency is low (f < 41 kHz) and this converter works at the monoresonance frequency, the components of the highorder harmonics are small. Applying FFT analysis, the total harmonic distortion (THD) is very small, thus the EMI is weak, and the EMS and EMC are reasonable.
11.3 MultipleQuadrant DC/DC ZVS Quasi Resonant LuoConverter Many industrial applications require the multiquadrant operation with ZVS technique, since it significantly reduces the power losses. Unfortunately, © 2003 by CRC Press LLC
1956_C11.fm Page 545 Monday, August 18, 2003 3:19 PM
TABLE 11.2 Experimental Results for Different Frequencies µH) Cr (µ µF) II (A) I O(A) IL(A) PI(W) PO(W) η (%) PD(W/in3) Mode f(kHz) Lr1=Lr2 (µ A A A B B B C C C D D D
20.5 21 21.5 16.5 17 17.5 19 19.3 19.5 40 40.3 40.5
1 1 1 1 1 1 1 1 1 1 1 1
4 4 4 4 4 4 4 4 4 4 4 4
16.98 17.4 17.81 25 25 25 16.17 16.42 16.59 24.05 24.23 24.35
25 25 25 16.4 16.2 15.97 23.82 23.64 23.53 15.64 15.49 15.4
25 25 25 25 25 25 35 35 35 35 35 35
713 730.6 748 700 700 700 679.1 689.7 696.8 663.4 678.5 681.8
700 700 700 688.8 680.4 670.1 667 662 658.8 656.8 650.6 646.7
98.2 95.8 93.5 98.4 97.2 95.8 98.2 96 94.5 97.5 95.9 94.8
17.66 17.88 18.1 17.36 17.25 17.13 16.83 16.9 16.95 16.5 16.6 16.61
most of the papers discuss the ZVS converters only working at single quadrant operation. Fourquadrant DC/DC ZCS quasiresonant Luoconverter effectively reduces the power losses and largely increases the power transfer efficiency. This is shown in Figure 11.6. Circuit 1 implements the operation in quadrants I and II, circuit 2 implements the operation in quadrants III and IV. Circuit 1 and circuit 2 can be converted to each other by an auxiliary changeover switch S3, which is illustrated in circuit 3. Each circuit consists of one main inductor L and two switches. Assuming that the main inductance L is sufficient large, the current iL is constant. The source and load voltages are usually constant, e.g., V1 = 42 V and V2 = ± 28 V. There are four modes of operation: 1. Mode A (quadrant I) : electrical energy is transferred from V1 side to V2 side. 2. Mode B (quadrant II): electrical energy is transferred from V2 side to V1 side. 3. Mode C (quadrant III) : electrical energy is transferred from V1 side to –V2 side. 4. Mode D (quadrant IV): electrical energy is transferred from –V2 side to V1 side. Each mode has two states: on and off. The switch/diode status of each state are shown in Table 11.3.
11.3.1
Mode A
Mode A is a ZVS buck converter. The equivalent circuit, current and voltage waveforms are shown in Figure 11.7. There are four time regions for the switchoff and on period. The conduction duty cycle is kT = (t3 + t4) when © 2003 by CRC Press LLC
1956_C11.fm Page 546 Monday, August 18, 2003 3:19 PM
D1 S1 + V1 –
iL
Lr
Cr1
L
ir Cr2
S2
+ V2 –
D2
(a) Circuit 1 for the operation in Quadrant I and Quadrant II
D1 S1 + V1 –
D2 Lr
S2
ir Cr1
L
– V2 +
Cr2
iL
(b) Circuit 2 for the operation in Quadrant III and Quadrant IV
D1 S1 Cr1
Lr
Cr2
+ V1 –
iL
ir S2
D2
L
S3 ab cd ab cd +– V 2
(c) Circuit 3 for four Quadrant operation
FIGURE 11.6 Fourquadrant DC/DC ZVS quasiresonant Luoconverter.
TABLE 11.3 Switch Status Mode A (QI) Mode B (QII) Mode C (QIII) Mode D (QIV) Circuit //Switch or Diode Stateon Stateoff Stateon Stateoff Stateon Stateoff Stateon Stateoff Circuit Circuit 1 Circuit 2 S1 ON ON D1 ON ON ON ON S2 D2 ON ON Note: The blank status means off.
© 2003 by CRC Press LLC
1956_C11.fm Page 547 Monday, August 18, 2003 3:19 PM
D1 S1 Cr1 + V1 –
IL
Lr ir
+ vc 1 –
+ V2 –
D2
(a) Equivalent Circuit
vC 1 V1 0
Z1IL
t1
t2
t3
ir
IL
t3'
0
IL t1
t4 IL
ir0 1
t2
t3
t4
(b) Waveforms FIGURE 11.7 Mode A operation.
the input current flows through the switch S1 and the main inductor L. The whole period is T = (t1 + t2 + t3 + t4). The resonance circuit is Lr – Cr1. The resonance frequency is ω1 =
1 Lr Cr 1
(11.60)
Lr Cr 1
(11.61)
and the normalized impedance is Z1 =
The resonant voltage (AC component) is vc1 (t) = Z1 I L sin(ω 1t + α 1 )
(11.62)
Considering the DC component V1, the peak voltage is vc1− peak = V1 + Z1I L © 2003 by CRC Press LLC
(11.63)
1956_C11.fm Page 548 Monday, August 18, 2003 3:19 PM
11.3.1.1
Interval t = 0 to t1
Switch S1 turns off at t = 0, the capacitor voltage vC1 increases linearly with the slope IL/Cr1; this is the voltage linear rising interval. This voltage is smaller than the source voltage V1. Therefore, no current flows through the diode D2. When t = t1, it is equal to V1. Therefore, the time is t1 =
V1Cr 1 IL
(11.64)
and corresponding angular position is α 1 = sin −1 (
11.3.1.2
V1 ) Z1 I L
(11.65)
Interval t = t1 to t2
In this period, since the voltage vC1 is higher than source voltage V1, the current flows through the diode D2. Circuit Lr – Cr1. resonates; this is the resonance interval. The voltage waveform is a sinusoidal function. After its peak value vC1peak, it descends down to zero (t = t2). If the converter works in subresonance state, switch S1 turns on at t = t2. At this point we can see that the switch S1 turns off and on at zero voltage condition. This period length is t2 =
1 ( π +α 1 ) ω1
(11.66)
Simultaneously, the current ir flows through the inductor Lr , it is a sinusoidal function as well. When t = t2, the corresponding value irO1 of the inductor current ir is irO1 = − I L sin(π / 2 + α 1) = − I L cos α 1 11.3.1.3
(11.67)
Interval t = t2 to t3
Since the diode D1 does not allow the resonant voltage vC1 to become a negative value, then vC1 = 0. The freewheeling diode D2 conducts and the current ir increases linearly with the slope V1/Lr ; this is the linear recovering interval. Because load current IL is a constant current the current ir increases linearly from irO1 to 0 at t = t′3 , and irO1 = IL at t = t3. t' 3 = − © 2003 by CRC Press LLC
ir 01Lr V1
(11.68)
1956_C11.fm Page 549 Monday, August 18, 2003 3:19 PM
and t3 =
( I L − irO1 )Lr I L (1 + cos α 1 )Lr = V1 V1
(11.69)
Interval t = t3 to t4
11.3.1.4
In this period the load current is supplied by the source. Diode D2 is blocked until t = t4; this is the normal switchon interval. The output current is equal to the main inductor current IL, so the average input current I1 is I V 1 I1 = L 2 = V1 T
t4
t4
1
∫ i dt ≈ T (I t ) = T I r
L 4
L
(11.70)
t3
Therefore, t1 + t2 + t3 V1 / V2 − 1
(11.71)
t3 + t 4 t1 + t2 + t3 + t4
(11.72)
T = t1 + t2 + t3 + t4
(11.73)
t4 = We have the conduction duty
k=
The whole repeating period is
and corresponding frequency is f = 1/ T
11.3.2
(11.74)
Mode B
Mode B is a ZVS boost converter. The equivalent circuit, current and voltage waveforms are shown in Figure 11.8. There are four time regions for the switchoff and on period. The conduction duty cycle is kT = (t3 + t4), but the output current only flows through the source V1 in the period t4. The whole period is T = (t1 + t2 + t3 + t4). The resonance circuit is Lr – Cr2. © 2003 by CRC Press LLC
1956_C11.fm Page 550 Monday, August 18, 2003 3:19 PM
D1
IL
Lr ir
+ V1
+ vc2Cr2 –
–
+ V2 –
S2 D 2
(a) Equivalent Circuit
vC2 V1 0
Z2 I L
t1
t2
t3
t4
t3
t4
ir02 IL ir
IL 0
t1
t 3' t2
(b) Waveforms FIGURE 11.8 Mode B operation.
The resonance frequency is ω2 =
1 Lr Cr 2
(11.75)
Lr Cr 2
(11.76)
and the normalized impedance is Z2 =
The resonant voltage (AC component) is vC 2 (t) = Z2 I L sin(ω 2 t + α 2 )
(11.77)
Considering the DC component V1, the peak current is vC 2− peak = V1 + Z2 I L © 2003 by CRC Press LLC
(11.78)
1956_C11.fm Page 551 Monday, August 18, 2003 3:19 PM
11.3.2.1
Interval t = 0 to t1
Switch S2 turns off at t = 0, the capacitor voltage vC2 increases linearly with the slope IL/Cr2. This voltage is equal to V1 when t = t1. t1 =
V1Cr 2 IL
(11.79)
and corresponding angular position is α 2 = sin −1 (
11.3.2.2
V1 ) Z2 I L
(11.80)
Interval t = t1 to t2
In this period the voltage vC2 is higher than the source voltage V1. Circuit Lr – Cr2 resonates. The voltage waveform is a sinusoidal function. After its peak value, it descends down to 0 when t = t2. If the converter works in subresonance state, switch S2 turns on at t = t2. Until this point we can see that the switch S2 turnsoff and on at zero voltage condition. This period length is t2 =
1 (π + α 2 ) ω2
(11.81)
Simultaneously, the inductor current ir flows through inductor Lr , it is a sinusoidal function as well. When t = t2, the corresponding value irO2 of the inductor current ir is irO 2 = I L [1 + sin(π / 2 + α 2 )] = I L (1 + cos α 2 ) 11.3.2.3
(11.82)
Interval t = t2 to t3
Since the diode D2 does not allow the resonant voltage to become a negative value, the voltage across the capacitor Cr2 will be 0. The inductor current ir decreases linearly with the slope –V1/Lr . Because load current IL is a constant current, the current ir decreases linearly from irO2 to IL at t = t3′ , and ir = 0 at t = t3. t3′ =
(irO 2 − I L )Lr V1
(11.83)
irO 2 Lr V1
(11.84)
t3 = © 2003 by CRC Press LLC
1956_C11.fm Page 552 Monday, August 18, 2003 3:19 PM
11.3.2.4
Interval t = t3 to t4
In this period the switch S2 is on. Load current IL does not flow through the source. Ignoring the power losses, and I2 = IL we have the output average current I1: I V 1 I1 = L 2 = V1 T
t3
∫
ir dt ≈
t1
t +t 1 [ I L (t2 + t3 )] = 2 3 I L T T
(11.85)
or t2 + t3 V2 1 = (t + t ) = V1 T 2 3 t1 + t2 + t3 + t4
(11.86)
Therefore, t4 = (
V1 − 1)(t2 + t3 ) − t1 V2
(11.87)
We have the conduction duty t3 + t 4 t1 + t2 + t3 + t4
(11.88)
T = t1 + t2 + t3 + t4
(11.89)
k= The whole repeating period is
and corresponding frequency is f = 1/ T
11.3.3
(11.90)
Mode C
Mode C is a ZVS buckboost converter. The equivalent circuit, current and voltage waveforms are shown in Figure 11.9. There are four time regions for the switchoff and on period. The conduction duty cycle is kT = (t3 + t4) when the input current I1 flows through the switch S1 and the main inductor L. The whole period is T = (t1 + t2 + t3 + t4). The resonance circuit is Lr – Cr1. © 2003 by CRC Press LLC
1956_C11.fm Page 553 Monday, August 18, 2003 3:19 PM
D1 S1 Cr1
Lr
D2
ir
+ +V – c1 V1 –
– V2 +
IL
(a) Equivalent Circuit
vC1 V1+V2 0
Z1IL
t1
t2
t3
ir
IL
t 3'
0
IL t1
t4 IL
ir01
t2
t3
t4
(b) Waveforms FIGURE 11.9 Mode C operation.
The resonance frequency is ω1 =
1 Lr Cr 1
(11.91)
Lr Cr 1
(11.92)
and the normalized impedance is Z1 =
The resonant voltage (AC component) is vc1 (t) = Z1 I L sin(ω 1t + α 1 )
(11.93)
Considering the DC component V1, the peak voltage is vc1− peak = V1 + V2 + Z1I L © 2003 by CRC Press LLC
(11.94)
1956_C11.fm Page 554 Monday, August 18, 2003 3:19 PM
11.3.3.1
Interval t = 0 to t1
Switch S1 turns off at t = 0, the capacitor voltage vC1 increases linearly with the slope IL/Cr1. This voltage vC1 is smaller than (V1 + V2). Therefore, no current flows through the diode D2. When t = t1, it is equal to (V1 + V2). Therefore, t1 =
(V1 + V2 )Cr 1 IL
(11.95)
and corresponding angular position is α 1 = sin −1 (
11.3.3.2
V1 + V2 ) Z1 I L
(11.96)
Interval t = t1 to t2
In this period, since the voltage vC1 is higher than source voltage V1, the current flows through the diode D2. Circuit Lr – Cr1. resonates. The voltage waveform is a sinusoidal function. After its peak value vC1–peak, it descends down to zero (t = t2). If the converter works in subresonance state, switch S1 turns on at t = t2. This period length is t2 =
1 ( π + α 1) ω1
(11.97)
Simultaneously, the current ir flows through the inductor Lr , it is a sinusoidal function as well. When t = t2, the corresponding value irO1 of the inductor current ir is irO1 = − I L sin(π / 2 + α 1) = − I L cos α 1 11.3.3.3
(11.98)
Interval t = t2 to t3
Since the diode D1 does not allow the resonant voltage vC1 to become a negative value, then vC1 = 0. The freewheeling diode D2 conducts and the current ir increases linearly with the slope (V1 + V2)/Lr . Because load current IL is a constant current the current ir increases linearly from irO1 to 0 at t = t′3, and irO1 = IL at t = t3. t3′ = − and © 2003 by CRC Press LLC
ir 01Lr V1 + V2
(11.99)
1956_C11.fm Page 555 Monday, August 18, 2003 3:19 PM
t3 =
( I L − irO1 )Lr I L (1 + cos α 1 )Lr = V1 + V2 V1 + V2
(11.100)
Interval t = t3 to t4
11.3.3.4
In this period the load current is supplied by the source. Diode D2 is blocked until t = t4. The output current is equal to the main inductor current IL, so the average input current I1 is I V 1 I1 = L 2 = V1 T
t4
∫ t3
ir dt ≈
t 1 ( I L t4 ) = 4 I L T T
(11.101)
t2 + t3 IL T
(11.102)
and 1 I2 = T
t3
∫ (I
L
− ir )dt ≈
t2
Therefore, V2 (t2 + t3 ) V1
(11.103)
t3 + t 4 t1 + t2 + t3 + t4
(11.104)
T = t1 + t2 + t3 + t4
(11.105)
t4 = We have the conduction duty k= The whole repeating period is
and corresponding frequency is f = 1/ T
11.3.4
(11.106)
Mode D
Mode D is a cross ZVS buckboost converter. The equivalent circuit, current and voltage waveforms are shown in Figure 11.10. There are four time © 2003 by CRC Press LLC
1956_C11.fm Page 556 Monday, August 18, 2003 3:19 PM
D2 Lr
D1
S2 Cr2
ir
+
IL
V1 –
+ Vc 2 – – V2 +
(a) Equivalent Circuit
vC2 V1+V2 0
Z2IL
t1
t2
t3
t4
t3
t4
ir02 IL ir
IL 0
t1
t3' t2
(b) Waveforms FIGURE 11.10 Mode D operation.
regions for the switchoff and on period. The conduction duty cycle is kT = (t3 + t4), but the output current only flows through the source V1 in the period t4. The whole period is T = (t1 + t2 + t3 + t4). The resonance circuit is Lr – Cr2. The resonance frequency is ω2 =
1 Lr Cr 2
(11.107)
Lr Cr 2
(11.108)
and the normalized impedance is Z2 =
The resonant voltage (AC component) is vC 2 (t) = Z2 I L sin(ω 2 t + α 2 ) Considering the DC component V1, the peak current is © 2003 by CRC Press LLC
(11.109)
1956_C11.fm Page 557 Monday, August 18, 2003 3:19 PM
vC 2− peak = V1 + Z2 I L 11.3.4.1
(11.110)
Interval t = 0 to t1
Switch S2 turns off at t = 0, the capacitor voltage vC2 increases linearly with the slope IL/Cr2. It is equal to (V1 + V2) when t = t1. t1 =
(V1 + V2 )Cr 2 IL
(11.111)
and corresponding angular position is α 2 = sin −1 (
11.3.4.2
V1 + V2 ) Z2 I L
(11.112)
Interval t = t1 to t2
In this period the voltage vC2 is higher than the sumvoltage (V1 + V2). Circuit Lr – Cr2 resonates. The voltage waveform is a sinusoidal function. After its peak value, it descends down to 0 when t = t2. If the converter works in subresonance state, switch S2 turns on at t = t2. This period length is t2 =
1 (π + α 2 ) ω2
(11.113)
Simultaneously, the inductor current ir flows through inductor Lr , it is a sinusoidal function as well. When t = t2, the corresponding value irO2 of the inductor current ir is irO 2 = I L [1 + sin(π / 2 + α 2 )] = I L (1 + cos α 2 ) 11.3.4.3
(11.114)
Interval t = t2 to t3
Since the diode D2 does not allow the resonant voltage to become a negative value, the voltage across the capacitor Cr2 will be 0. The inductor current ir decreases linearly with the slope –(V1 + V2)/Lr . Because the main inductor current IL is a constant current, the current ir decreases linearly from irO2 to IL at t = t3′ , and ir = 0 at t = t3. t3′ =
© 2003 by CRC Press LLC
(irO 2 − I L )Lr V1 + V2
(11.115)
1956_C11.fm Page 558 Monday, August 18, 2003 3:19 PM
t3 =
11.3.4.4
irO 2 Lr V1 + V2
(11.116)
Interval t = t3 to t4
In this period since the switch S2 is on, the main inductor current IL does not flow through the source. Ignoring the power losses, we have the output average current I1:
1 I1 = T
t3
∫
ir dt ≈
t1
t +t 1 [ I L (t2 + t3 )] = 2 3 I L T T
(11.117)
and
1 I2 = T
t4
t4
1
∫ i dt ≈ T (I t ) = T I r
L 4
L
(11.118)
t3
Therefore, V1 (t + t ) V2 2 3
(11.119)
t3 + t 4 t1 + t2 + t3 + t4
(11.120)
T = t1 + t2 + t3 + t4
(11.121)
t4 =
We have the conduction duty
k=
The whole repeating period is
and corresponding frequency is f = 1/ T
© 2003 by CRC Press LLC
(11.122)
1956_C11.fm Page 559 Monday, August 18, 2003 3:19 PM
TABLE 11.4 Experimental Results for Different Frequencies µH) Cr1 = Cr2 (µ µF) II (A) IO(A) IL(A) PI(W) PO(W) η (%) PD(W/in3) Mode f(kHz) Lr1 (µ A A A B B B C C C D D D
11.3.5
23 23.5 24 54 54.5 55 44 44.5 45 29.5 30 30.5
4 4 4 4 4 4 4 4 4 4 4 4
1 1 1 1 1 1 1 1 1 1 1 1
17.16 16.99 16.82 25 25 25 17.64 17.32 17.01 26.65 26.34 26.28
25 25 25 16.13 16.28 16.43 24.27 24.55 24.83 16.27 16.55 16.83
25 25 25 25 25 25 45 45 45 45 45 45
720.8 713.7 706.6 700 700 700 740.9 727.6 714.5 746.3 737.6 735.9
700 700 700 677.6 683.8 690.1 679.6 687.5 695.2 683.5 695.1 706.7
97.1 98.1 99 96.8 97.7 98.6 91.7 94.5 97.3 91.6 94.2 96
17.76 17.67 17.58 17.22 17.3 17.38 17.76 17.69 17.62 17.87 17.91 18.03
Experimental Results
A testing rig with a battery of ±28 VDC as a load and a source of 42 VDC as the power supply was tested. The testing conditions are: V1 = 42 V and V2 = ±28 V, L = 30 µH, Lr = 4 µH, Cr1 = Cr2 = 1 µF; the volume is 40 in3. The experimental results are shown in Table 11.4. The average power transfer efficiency is higher than 96%, and total average PD is 17.6 W/in3. This figure is much higher than that of the classical converters whose PD is usually less than 5 W/in3. Since the switch frequency is low (f < 56 kHz) and this converter works at the monoresonance frequency, the components of the highorder harmonics are small. Applying FFT analysis, the THD is very small, so that the EMI is weak, and the EMS and EMC are reasonable.
11.4 MultipleQuadrant ZeroTransition DC/DC LuoConverters Zerotransition (ZT) technique significantly reduces the power losses across the switches during switchon and off. Unfortunately, the literature discusses the converters only working at single quadrant operation. The fourquadrant ZT DC/DC Luoconverters perform soft switch fourquadrant operation without significant voltage and current stresses. They effectively reduce the power losses and greatly increase the power transfer efficiency. These converters are shown in Figure 11.11a and b. Circuit 1 implements the operation in quadrants I and II, circuit 2 implements the operation in quadrants III and IV. Circuit 1 and circuit 2 can be converted each other via an auxiliary switch. Each circuit consists of one main inductor L and two main © 2003 by CRC Press LLC
1956_C11.fm Page 560 Monday, August 18, 2003 3:19 PM
D1
iLr
IL
Lr
L
S1
+ V1 –
Da Sa
+
+ V2 –
Cr S2
D2 Sb
Db
(a) Circuit 1 for Modes A & B Operation
D1 S1
+ V1 –
Da Sa
D2 iLr
Lr
+
Cr
S2 Db Sb
IL
L
– V2 +
(b) Circuit 2 for Modes C & D Operation FIGURE 11.11 Fourquadrant zerotransition DC/DC Luoconverters.
switches. The source and load voltages are usually constant, e.g., V1 = 42 V and V2 = ± 28 V. There are four modes of operation: 1. Mode A (quadrant I): electrical energy is transferred from V1 side to V2 side. 2. Mode B (quadrant II): electrical energy is transferred from V2 side to V1 side. 3. Mode C (quadrant III): electrical energy is transferred from V1 side to –V2 side. 4. Mode D (quadrant IV): electrical energy is transferred from –V2 side to V1 side. Each mode has two states: on and off. The switch and diode status of each state for modes A and B are shown in Table 11.5; the status of each state for modes C and D are shown in Table 11.6. The equivalent circuits for modes A, B, C, and D are shown in Figures 11.12, 11.14, 11.16, and 11.18. The corresponding waveforms for each mode are shown in Figures 11.13, 11.15, 11.17, and 11.19 respectively. © 2003 by CRC Press LLC
1956_C11.fm Page 561 Monday, August 18, 2003 3:19 PM
TABLE 11.5 Switch/Diode Status S&D S1 D1 Sa Da S2 D2 Sb Db
∆t1
∆t2
∆t3
Mode A (QI) ∆t4 ∆t5 ∆t6
∆t7
∆t8
∆t1
∆t2
Mode B (QII) ∆t3 ∆t4 ∆t5 ∆t6
∆t7 ∆t8
ON ON ON ON
ON
ON ON ON ON ON ON ON ON ON
ON ON ON ON ON ON
Note: The blank status means off referring to circuit 1 of Figure 11.11a.
TABLE 11.6 Switch/Diode Status S&D S1 D1 Sa Da S2 D2 Sb Db
∆t1
∆t2
Mode C (QIII) ∆t3 ∆t4 ∆t5 ∆t6
∆t7
∆t8
∆t1
∆t2
Mode D (QIV) ∆t3 ∆t4 ∆t5 ∆t6
∆t7 ∆t8
ON ON ON ON
ON
ON ON ON ON ON ON ON ON ON
ON ON ON ON ON ON
Note: The blank status means off referring to circuit 2 of Figure 11.11b.
D1
iLr
S1
IL
Lr
L
Da + V1 –
FIGURE 11.12 Mode A (QI) operation.
© 2003 by CRC Press LLC
Sa
+ Cr
S2
D2 Sb
Db
+ V2 –
1956_C11.fm Page 562 Monday, August 18, 2003 3:19 PM
Sa S1 ISa ID2 IS1 Vds Vcr
ILr t0 t1t2
t3t4 t5
t6t7
FIGURE 11.13 Waveforms of mode A (QI).
11.4.1
Mode A (Quadrant I Operation)
Mode A performs quadrant I operation. The equivalent circuit for Mode A, is shown in Figure 11.12. The corresponding waveforms are shown in Figure 11.13. Stage 1 (t0 – t1): prior to t0, S1 and Sa are all off. The circuit current is freewheeling through the antiparallel diode Db and D2. Cr voltage is zero, IL = ILr + IDb. At t0, the auxiliary switch Sa is turned on with zero current. Capacitor Cr is charged in reverse, so that diode Db is reversebiased in soft commutation. The current of Lr decreases linearly while the current of Sa increases gradually. At t = t1, the current of Lr falls to zero; D2 is turned off with soft commutation. Meanwhile, current of Sa reaches to IL. The current of resonant inductor Lr is iLr =
V1 t Lr
The time interval of the first stage ∆t1 is given by equation ∆t1 =
I L Lr V1
(11.123)
Stage 2 (t1 – t3): the main switch S1 junction capacitor Cj (not shown in Figure 11.12) discharges through Lr , Sa. Capacitor Cr also discharges through Lr . Vcr , and Vds fall to zero rapidly at t2. Thereafter, the antiparallel diode of S1 starts to conduct and a small reverse current flows through Lr . The resonant time interval of stage 2, ∆t2, is given by © 2003 by CRC Press LLC
1956_C11.fm Page 563 Monday, August 18, 2003 3:19 PM
∆t2 =
π Lr C j 2
(11.124)
Stage 3 (t2 – t3): at t3, S1 is turned on with zero current and zero voltage. At the same moment, turn off Sa. It should be noted that the turn on/off point is not critical. S1 and Sa could be turn on and off prior to t2. If so, t2 does not exist in the stage. Therefore, ∆t3 = tSa−on − ∆t1 − ∆t2
(11.125)
Stage 4 (t3 – t4): when Sa is turned off, IL charges Cr and Lr through the conducted S1. The voltage of Cr increases gradually, enabling Sa to be turned off with zero voltage. After iLr reaches IL, capacitor Cr starts to discharge through Lr . At t = t4, Vcr reaches zero again. ∆t4 =
V1Cr IL
(11.126)
Stage 5 (t4 – t5): During this period, the circuit current flows through main switch S1, and inductor Lr , L, like the conventional PWM converter. The length is determined by the control of the PWM signal. ∆t5 =
π Lr Cr 2
(11.127)
Stage 6 (t5 – t6): at t5, main switch S1 is turned off. Inductor and capacitor Cr are in resonance. The voltage of Cr increases gradually at first, so that the voltage across the main switch S1 rises gradually. S1 is therefore turned off with zero voltage. At t6, the voltage of Cr becomes zero; D2 and Db start to conduct. The time interval is given by ∆t6 = kT − ∆t4 − ∆t5
(11.128)
Stage 7 (t6 – t7): During this period, the circuit current is freewheeling through D2 and Db, like the conventional PWM converter. ∆t7 = π Lr Cr
(11.129)
Stage 8 (t7 – t0): at t0, Sa is turned on once more, to start the next switch cycle. The length of this period is determined by the control of the PWM. ∆t8 = (1 − k )T − tSa−on − ∆t7 © 2003 by CRC Press LLC
(11.130)
1956_C11.fm Page 564 Monday, August 18, 2003 3:19 PM
D1
iLr
S1
IL
Lr
L
Da Sa
+ V1 –
+
+ V2 –
Cr S2
D2 Sb
Db
FIGURE 11.14 Mode B (QII) operation.
Sb S2 ISb ID1 IS2 Vds Vcr
ILr t0 t1 t2
t3 t4 t5
t6 t7
FIGURE 11.15 Waveforms of mode B (QII).
11.4.2
Mode B (Quadrant II Operation)
Mode B performs quadrant II operations. The equivalent circuit for mode B, is shown in Figure 11.14. The operational process is analogous to mode A operation. The corresponding waveforms are shown in Figure 11.15. The calculation formulae for mode B are listed below: ∆t1 =
I L Lr V1
∆t3 = tSb−on − ∆t1 − ∆t2 © 2003 by CRC Press LLC
∆t2 =
π Lr C j 2
∆t4 =
V1Cr IL
1956_C11.fm Page 565 Monday, August 18, 2003 3:19 PM
D2
D1 S1 Da
iLr
Lr
+
Cr
Sa
+ V1 –
S2 Db Sb
IL
+ V2 –
L
FIGURE 11.16 Mode C (QIII) operation.
Sa S1 ISa ID2 IS1
Vds Vcr
ILr t0t1t2 t3t4t5
t6t7
FIGURE 11.17 Waveforms of mode C (QIII).
∆t5 =
π Lr Cr 2
∆t7 = π Lr Cr
11.4.3
∆t6 = kT − ∆t4 − ∆t5 ∆t8 = (1 − k )T − tSb−on − ∆t7
Mode C (Quadrant III Operation)
Mode C performs quadrant III operation. The equivalent circuit for mode C, is shown in Figure 11.16. The operational process is analogous to mode A operation. The corresponding waveforms are shown in Figure 11.17. The calculation formulae of mode C are listed below: © 2003 by CRC Press LLC
1956_C11.fm Page 566 Monday, August 18, 2003 3:19 PM
D2
D1 S1 Da + V1 –
iLr
Lr
+
Cr
Sa
S2 Db Sb
IL
+ V2 –
L
FIGURE 11.18 Mode D (QIV) operation.
∆t1 =
I L Lr V1 + V2
∆t3 = tSa−on − ∆t1 − ∆t2
∆t5 =
π Lr Cr 2
∆t7 = π Lr Cr
11.4.4
∆t2 =
π Lr C j 2
∆t4 =
V1 + V2 Cr IL
∆t6 = kT − ∆t4 − ∆t5 ∆t8 = (1 − k )T − tSa−on − ∆t7
Mode D (Quadrant IV Operation)
Mode D performs in quadrant IV operation. The equivalent circuit for mode D, is shown in Figure 11.18. The operational process is analogous to mode B operation. The corresponding waveforms are shown in Figure 11.19. The calculation formulae of mode D are listed below: ∆t1 =
I L Lr V1 + V2
∆t3 = tSb−on − ∆t1 − ∆t2
∆t5 =
π Lr Cr 2
∆t7 = π Lr Cr © 2003 by CRC Press LLC
∆t2 =
π Lr C j 2
∆t4 =
V1 + V2 Cr IL
∆t6 = kT − ∆t4 − ∆t5 ∆t8 = (1 − k )T − tSb−on − ∆t7
1956_C11.fm Page 567 Monday, August 18, 2003 3:19 PM
Sb S2 ISb ID1 IS2 Vds Vcr
ILr t0t1t2 t3t4t5
t6t7
FIGURE 11.19 Waveforms of mode D (QIV).
11.4.5
Simulation Results
PSpice is a popular simulation method to test and verify electronic circuit design. In order to implement this ZVZCS twoquadrant DC/DC converter with 3 kW delivery, the rig of a modern car battery ±28 VDC as a load and a 42 VDC as a source power supply was tested. The testing conditions are V1 = 42 V and V2 = 28 V, Lr = 2 µH , Cr = 0.8 nF, and L = 550 µH , f = 100 kHz. The simulation result for QI is shown in Figure 11.20, the simulation result for QII is shown in Figure 11.21. From these waveform and data, we can see that the main switches in the converter are switched on at ZC and ZVS condition; switched off at ZVS condition. Moreover, all the auxiliary switches and diode are operated under soft commutation. The testing conditions are V1 = 42 V and V2 = –28 V, Lr = 2 µH , Cr = 0.8 nF, and L = 550 µH , f = 100 kHz. The simulation results for QIII are shown in Figure 11.22, the simulation results for QIV are shown in Figure 11.23. From these waveforms we can see that the main switches in the converter are switched on at ZC and ZVS condition; switched off at ZVS condition. Moreover, all the auxiliary switches and diodes are operated under soft commutation.
11.4.6
Experimental Results
A testing rig battery of ±28 VDC as a load and a source of 42 VDC as the power supply was tested. The testing conditions are: V1 = 42 V and V2 = ±28 V, L = 30 µH, Lr1 = Lr2 = 1 µH, Cr = 4 µF, IL = 25 A (for QI and QII)/35 A (for QIII and QIV) and the volume is 40 in3. The experimental results are shown in Table 11.7. The average power transfer efficiency is higher than 89.7% and the total average PD is 17.5 W/in3. This figure is much higher than the classical converters whose PD is usually less than 5 W/in3. Since the switch © 2003 by CRC Press LLC
1956_C11.fm Page 568 Monday, August 18, 2003 3:19 PM
FIGURE 11.20 Simulation result for ZVZCS mode A operation (f = 100 kHz; k = 30%).
FIGURE 11.21 Simulation result for ZVZCS mode B operation (f = 100 kHz; k = 60%).
© 2003 by CRC Press LLC
1956_C11.fm Page 569 Monday, August 18, 2003 3:19 PM
FIGURE 11.22 Simulation result for ZVZCS mode C operation (f = 100 kHz; k = 30%).
FIGURE 11.23 Simulation result for ZVZCS mode D operation (f = 100 kHz; k = 70%).
© 2003 by CRC Press LLC
1956_C11.fm Page 570 Monday, August 18, 2003 3:19 PM
TABLE 11.7 Experimental Results for Different Frequencies µH) Cr (µ µF) II (A) IO(A) Mode f(kHz) Lr1=Lr2 (µ A A A B B B C C C D D D
20.5 21 21.5 16.5 17 17.5 18.3 18.5 18.7 37.2 37.5 37.8
1 1 1 1 1 1 1 1 1 1 1 1
4 4 4 4 4 4 4 4 4 4 4 4
16.98 17.4 17.81 25 25 25 16.24 16.42 16.59 24.42 24.62 24.81
25 25 25 16.4 16.2 15.97 24.03 23.91 23.79 16.02 15.87 15.71
IL(A) PI(W) PO(W) η (%) PD(W/in3) 25 25 25 25 25 25 35 35 35 35 35 35
713 730.6 748 700 700 700 682.1 689.6 696.8 683.8 689.4 694.7
700 700 700 688.8 680.4 670.1 672.8 669.4 666.1 672.7 666.4 660
98.2 95.8 93.5 98.4 97.2 95.8 98.6 97.1 95.6 98.4 96.7 95
17.66 17.88 18.1 17.36 17.25 17.13 16.94 17 17.04 16.95 16.94 16.93
frequency and conduction duty k can be adjusted individually, we chose f = 100 kHz and a suitable conduction duty cycle k to obtain the proper operation state.
11.4.7
Design Considerations
In a practical design, for ease of implementation, the control of the two switches can adopt the constant timedelay method: 1. Turnon of the main switch should delay turnon of the auxiliary switch at least by ∆TONmin. The auxiliary switch could be turned off simultaneously with the turnon of the main switch. But it is better to turn off Sa shortly after turnon of the main switch to secure soft turnoff of the auxiliary switch. 2. For prompt soft turnoff of main switch (S1 or S2) and energy recovery, turnoff of the auxiliary switch should precede turnoff of the main switch by a minimum time of ∆TOFFmin. This means that for prompt soft switch, the above constraint should be met under the minimum duty cycle kmin. The simple timing constraints are calculated as follows: TD ≥ TON min = ∆t1 + ∆t2 =
TP ≥ ∆TOFF min =
iP = I L 2 + © 2003 by CRC Press LLC
V12 ρ
I L Lr π + Lr C j 2 V1
Cr V1 Lr + i iP V1 P ρ=
Lr Cj
(11.131)
(11.132)
(11.133)
1956_C11.fm Page 571 Monday, August 18, 2003 3:19 PM
Where Cj is the junction capacitor across the main switch’s drain and source, TD is the time that turnon of main switch delays turnon of auxiliary switch. TP is the time that turnoff of auxiliary switch precedes turnoff of main switch. iP is Lr peak current. For engineering implementation, as no capacitor is directly paralleled with the main switch, the time interval ∆t2 is very small; moreover, the turnon loss caused by the junction capacitor is minimum if the main switch is turnedon before Vds falls to zero. So, ∆t2 in Equation (11.131) can be ignored for simple design: TD ≥ TON min = ∆t1 =
I L Lr V1
(11.134)
To secure the soft switch under minimum duty cycle kmin , Equation (11.132) can be expressed as: kminTs ≥ ∆TOFF min =
CrV1 Lr + iP iP V1
(11.135)
To achieve the similar conversion ratios of its hard switch PWM counterpart, the commutation transition i.e., ∆TONmin is normally set as 10 to 15% cycle in practical design: TON min =
I L max Lr ≤ (10% − 15%)Ts V1
(11.136)
From Equation (11.136) Lr can be obtained, for practical implementation, turnon of the main switch delays turnon of the auxiliary switch a constant time TD: TD =
I L max Lr V1
(11.137)
To reduce the auxiliary switch’s conduction loss, the auxiliary switch is turned off right after turnon of the main switch. From Equation (11.133), it is obvious that the peak current of Lr does not relate to Cr . So, Cr can be set large enough to reduce the turnoff loss of the main switch most effectively. But Cr should meet the constraint of Equation (11.135) as well. Compared with other softswitch circuits, besides the soft switch of the auxiliary switch, the proposed circuit possesses the simplicity in topology. Another merit is that Cr is not directly paralleled with the main switch. It not only provides soft turnoff for all the switches, but also does not discharge to Lr . A lower peak current in the auxiliary switch could, therefore, © 2003 by CRC Press LLC
1956_C11.fm Page 572 Monday, August 18, 2003 3:19 PM
be expected, particularly in cases where a small snubber inductor is used in highfrequency operation. Moreover, as the charge of Cr does not increase Lr current, the design tradeoff between Cr and current stress on the auxiliary switch does not exist, and the design of Lr and Cr become easy, as the above design analysis indicates. Also, with the help of inductor Lr , the reverserecovery current of the main diode is effectively minimized. It should be also noted here that the turnon point of the main switch is not critical. The main switch could be turned on prior to t2, because the turnon loss caused by the junction capacitor is very small. The control principle adopted here is simple, as it does not need the crosszero voltage detection of the main switch. So it is easy to implement, but it has its limitations in lightload or noload operation. Since the duty cycle of the main switch may be smaller than the duty cycle of the auxiliary switch at no load or light load, the constant duty cycle of the auxiliary switch will charge up the output capacitor without control. In such a case, certain current or voltage crosszero detection is required to adjust the duty cycle of the auxiliary switch. On the other hand, the conduction loss is increased, as the auxiliary switch is not optimized with the minimum conduction at light load by using this control method.
Bibliography Chen, K. and Stuart, T.A., A study of IGBT turnoff behavior and switching losses for zerovoltage and zerocurrent switching, in Proceedings of APEC '92, 1992, p. 411. Chen, K., Masserant, B., and Stuart, T., A new family of ZVS/ZCS DCDC converters for electric vehicles, in Proceedings of the IEEE Workshop on Power Electronics in Transportation, Record, 1992, p. 155. Cho, J.G., Jeong, C.Y., and Lee, F.C.Y., Zerovoltage and zerocurrentswitching fullbridge PWM converter using secondary active clamp, IEEE Trans. on Power Electronics, 13, 601, 1998. Cho, J.G., Sabate, J.A., Hua, G., and Lee, F.C., Zerovoltage and zerocurrentswitching full bridge PWM converter for high power applications, IEEEPE Transactions, 11, 622, 1996. Fuentes, R.C. and Hey, H.L., An improved ZCSPWM commutation cell from IGBT’s application, IEEE Trans. on Power Electronics, 14, 939, 1999. Garabandic, D., Dunford, W.G., and Edmunds, M., Zerovoltagezerocurrent switching in highoutputvoltage fullbridge PWM converters using the interwinding capacitance, IEEE Trans. On Power Electronics. 14, 343, 1999. Gu, W.J. and Harada, K., A novel selfexcited forward DCDC converter with zerovoltageswitched resonant transitions using a saturable core, IEEEPE Transactions, 10, 131, 1995. Hua, G., Leu, C., and Lee, F. C., Novel zerovoltagetransition PWM converters, in Proceedings of IEEE PESC’92, 1992, p. 55. Hua, G., Yang, X., Jiang, Y., and Lee, F.C., Novel zerocurrent transition PWM converters, in Proceedings of IEEE PESC’93, 1993, p. 544. © 2003 by CRC Press LLC
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Hua, G., Yang, X., Jiang, Y., and Lee, F.C., Novel zerocurrent transition PWM converters, in Proceedings of IEEE Power Electronics Specialists Conf. Rec., 1993, p. 538. Ivensky, G., Zeltser, I., Kats, A., and Yaakov, S.B., Reducing IGBT losses in ZCS series resonant converters, IEEE Trans. on Industrial Electronics. 46, 67, 1999. Jovanovic, M.M., Lee, F.C., and Chen, D.Y., A zerocurrentswitched offline quasiresonant converter with reduced frequency range: Analysis, design, and experimental results, IEEE Trans. on Power Electronics, 4, 215, 1987. Jovanovic, M.M., Tabisz, W.A., and Lee, F.C.Y., Highfrequency offline power conversion using zerovoltageswitching quasiresonant and multiresonant techniques, IEEE Trans. on Power Electronics, 4, 459, 1989. Liu, K.H. and Lee, F.C., Zerovoltage switching techniques in DC/DC converter circuits, in Proceedings of Power Electronics Specialist's Conf. PESC’86 Vancouver, Canada, 1986, p. 58. Liu, K.H., Oruganti, R., and Lee, F.C., Quasiresonant converterstopologies and characteristics, IEEE Trans. on Power Electronics, 2, 62, 1987. Luo, F.L. and Jin, L., 42/14V TwoQuadrant DC/DC softswitching converter, in Proceedings of IEEE International Conference IEEEPESC’00, Galway Ireland, 2000 p. 173. Luo, F.L. and Ye, H., Twoquadrant zerocurrentswitching quasiresonant DC/DC Luoconverter in reverse operation, Power Supply Technologies and Applications (Xi’an, China), 3, 113, 2000. Luo, F.L. and Ye, H., Multiquadrant DC/DC zerocurrentswitching quasiresonant Luoconverter, in Proceedings of IEEE International Conference PESC’2001, Vancouver, Canada, 2001, p. 878. Luo, F.L. and Ye, H., Zerovoltageswitching fourquadrant DC/DC quasiresonant Luoconverter, in Proceedings of IEEE International Conference PESC’2001, Vancouver, Canada, 2001, p. 1063. Luo, F.L. and Ye, H., Twoquadrant zerocurrentswitching quasiresonant DC/DC Luoconverter in forward operation, Power Supply World, (Guangzhou, China) 2, 63, 2001. Luo, F.L. and Ye, H., Twoquadrant zerovoltageswitching quasiresonant DC/DC Luoconverter in forward operation, Power Supply Technologies and Applications (Xi’an, China), 4, 26, 2001. Luo, F.L. and Ye, H., Twoquadrant zerovoltageswitching quasiresonant DC/DC Luoconverter in reverse operation, Power Supply Technologies and Applications (Xi’an, China), 4, 185, 2001. Luo, F.L., Ye, H., and Rashid, M. H., Fourquadrant zerovoltageswitching quasiresonant DC/DC Luoconverter, Power Supply Technologies and Applications (Xi’an, China), 3, 185, 2000. Pong, M.H., Ho, W.C., and Poon, N.K., Soft switching converter with power limiting feature, IEEEPA Proceedings, 146, 95, 1999. Zhu, J.Y. and Ding, D., Zerovoltage and zerocurrentswitched PWM DCDC converters using active snubber, IEEE Trans. on Industry Applications, 35, 1406, 1999. Zhu, J.Y. and Ding, D., Zerovoltage and zerocurrentswitched PWM DCDC converters using active snubber, IEEEIA Transactions, 35, 1406, 1999.
© 2003 by CRC Press LLC
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12 Synchronous Rectifier DC/DC Converters
The global merchant dollar market for DC/DC converters is projected to increase from about $3.6 billion in 2001 to about $6.0 billion in 2006, a compound annual growth rate of 10.6%. North American sales of DC/DC converters in networking and telecom equipment are expected to grow from $2.3 billion in 1999 to $4.6 billion in 2004, a yearly compounded growth rate of 15.3%. The first quarter of 1995 was the first time that shipments of 3.3 V microprocessor and memory integrated chips (ICs) exceeded the shipments of 5 V parts. Once this transition occurred in memories and microprocessors, the demand for lowvoltage power conversion began to grow at an increasing rate. The primary application of DC/DC converters is in computer power supplies and communication equipment. The computer power supply shift from 5 V to 3.3 V digital IC has taken over 5 years to occur, from the first indication that voltages below 5 V would be needed until the realization of volume sales. Now that the 5 V barrier has been broken, the trend toward lower and lower voltages is accelerating. Within 2 years, 2.5 V parts are expected to become common with the introduction of the nextgeneration microprocessors. In fact, current plans for nextgeneration microprocessors call for a dual voltage of 1.5/2.5 V with 1.5 V used for the memory bus and 2.5 V used for logic functions. Within another few years, voltages are expected to move as low as 0.9 V, with mainstream, highvolume parts operating at 1.5 V. A lowvoltage plus highcurrent DC power supply is urgently required in the nextgeneration computer and communications equipment. The first idea is to use a forward converter, refer to Figure 1.26, which can perform lowvoltage plus highcurrent output voltage. A modified circuit with dynamic clamp circuit is shown in Figure 12.1. The two diodes D1 and D2 can be normal rectifier diode, rectifier Schottky diode, or MOSFET. Figure 12.2 shows the efficiency gain of the following three types of forward converters needed to construct a lowvoltage highcurrent power supply: • Forward converter using traditional diodes • Forward converter using Schottky diode • Synchronous rectifier using low forwardresistance MOSFET
© 2003 by CRC Press LLC
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R1
C1 L m
V1
Lf
D1
T
v3
D2
RL
Cf
R
v2
1 : N PWM
Q0
Q0
FIGURE 12.1 Forward converter with dynamic clamp circuit.
1.00 Efficiency
0.80 Synchronous Rectifier Schottky Diode
0.60 0.40
Normal Diode 0.20 0.00 0.2
0.3
0.4
0.5
0.6
0.7
0.8
Duty Cycle
FIGURE 12.2 Efficiencies of different types of forward converter.
As the operating voltages ratchet downward, the design of rectifiers requires more attention because the devices forwardvoltage drop constitutes an increasing fraction of the output voltage. The forwardvoltage drop across a switchmode rectifier is in series with the output voltage, so losses in this rectifier will almost entirely determine its efficiency. The synchronous rectifier circuit has been designed primarily to reduce this loss.
12.1 Introduction A synchronous rectifier is an electronic switch that improves powerconversion efficiency by placing a lowresistance conduction path across the diode rectifier in a switchmode regulator. At 3.3 V, the traditional dioderectifier loss is significant with very low efficiency (say less than 70%). For stepdown regulators with a 3.3 V output and 12 V battery input voltage, a 0.4 V forward voltage of a Schottky diode represents a typical efficiency penalty of about 12%, aside from other loss mechanisms. The losses are not as bad at lower © 2003 by CRC Press LLC
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L
T S2
v3
D2
C
R v2
S1
V1
1:N PWM
D1
S
FIGURE 12.3 Synchronous rectifier converter with lowresistance MOSFET.
input voltages because the rectifier has a lower duty cycle and, thus, a shorter conduction time. However, the Schottky rectifier’s forward drop is usually the dominant loss mechanism. For an input voltage of 7.2 V and output of 3.3 V, a synchronous rectifier improves on the Schottky diode rectifier ’s efficiency by around 4%. Figure 12.1 also shows that, as output voltage decreases, the synchronous rectifier provides even larger gains in efficiency. A practical circuit arrangement of a synchronous rectifier (SR) DC/DC converter with purely resistive load is shown in Figure 12.3. It has one MOSFET switch S on the primary side of the transformer. Two MOSFETs S1 and S2 on the secondary side of the transformer are functioning as the synchronous rectifier. T is the isolating transformer with a turn ratio of 1:N. an LC circuit is the lowpass filter and R is the load. V1 is the input voltage and V2 is the output voltage. The main switch S is driven by a PWM pulsetrain signal. Repeating frequency f and turnon duty cycle K of the PWM signal can be adjusted. When the PWM signal is in the positive state, the main switch S conducts. The primary voltage of the transformer is V1, and subsequently the secondary voltage of the transformer is v3 = NV1. In the mean time the MOSFET S1 is forward biased, so it turns ON and inversely conducts. When the PWM signal is in the negative state, the main switch S is switched off. The voltage of the transformer, v3, at this moment in time is approximately –NvC1. At the mean time the MOSFET S2 is forward biased, so it turns ON and inversely conducts. It functions as freewheeling diode and lets the load current remain continuous through the filter L–C and load R. A lot of papers in literature with practical hardware circuit achievements on synchronous rectifier have been presented about the recent IEEE Transactions and IEE Proceedings. The paper “Evaluation of SynchronousRectification Efficiency Improvement Limits in Forward Converters” supported by Virginia Power Electronics Center is one of the few outstanding research publications on synchronous rectifiers (Jovanovic et al., 1995). This chapter provides a practical design of a 3.3V/20A FSR (forward synchronous rectifier) with an efficiency of 85.5%. Similarly, another paper in 1993 also showed the principle of a RCD clamp forward converter with an efficiency of 87.3% © 2003 by CRC Press LLC
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at low output current (Cobos et al., 1993). Two Japanese researchers from Kumamoto Institute of Technology designed an FSR with an additional winding and switching element that is able to hold the gate charge for the freewheeling MOSFET (Sakai and Harada, 1995). Their experimental results for a 5 V/10 A SR gives a maximum efficiency of approximately 91% at a load of 7 A and an efficiency of 89% at 10 A. Another comparable FSR project was made by James Blanc from Siliconix Incorporated (Blanc, 1991). In his paper, he has included a lot of practical and useful simulation and experimental waveform data from his 3.3 V/10 A FSR. As the output voltage decreased, the operating efficiency decreased. Until now, no recent paper has been published on any practical hardware FSR that is able to provide 1.8 V/20 A output current at high efficiency. Analysis and design of DC/DC converters has been the subject of many papers in the past. From the moment averaging techniques were used to model these converters, interest has been focused on finding the best approach to analyze and predict the behavior of the averaged small signal or large signal models. The main difficulty encountered is that the converter models are multipleinput multipleoutput nonlinear systems and thus, using the wellknown transfer function control design approach is not straightforward. The most common approach has been that of considering the linearized small signal model of these converters as a multiloop system, with an outer voltage loop and an inner current loop. Since the current loop has a much faster response than that of the outer loop, the analysis is greatly simplified and the transfer functions obtained allow the designer to predict the closed loop behavior of the system. Another approach in analysis and design has been that of statespace techniques where the linearized statespace equations are used together with design technique such as pole placement or optimal control. Synchronous rectifier DC/DC converters are called the fifth generation converters. The developments in microelectronics and computer science require power supplies with low output voltage and strong current. Traditional diode bridge rectifiers are not available for this requirement. Softswitching technique can be applied in synchronous rectifier DC/DC converters. We have created converters with very low voltage (5 V, 3.3 V, and 1.8 ~ 1.5 V) and strong current (30 A, 60 A, 200 A) and high power transfer efficiency (86%, 90%, 93%). In this section new circuits different from the ordinary synchronous rectifier DC/DC converters are introduced: • Flat transformer synchronous rectifier Luoconverter • Active clamped flat transformer synchronous rectifier Luoconverter • Double current synchronous rectifier Luoconverter with active clamp circuit • Zerocurrentswitching synchronous rectifier Luoconverter • Zerovoltageswitching synchronous rectifier Luoconverter © 2003 by CRC Press LLC
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T
L
RL
D3
CO
S3 Lm
v3
R
v2
S2
V1
1:N PWM
D2
Cj S1
FIGURE 12.4 Flat transformer synchronous rectifier Luoconverter.
12.2 Flat Transformer Synchronous Rectifier LuoConverter The flat transformer is a new design for AC/AC energy conversion. Since its structure is very compatible and wellshielded, its size is very small and likely a flan cardboard. Applying frequency can be 100 KHz to 5 MHz, its power density can be as high as 300 W/inch3. Therefore, it is a good component to use to construct the synchronous rectifier DC/DC converter. The flat transformer SR DC/DC Luoconverter is shown in Figure 12.4. The switches S1, S2, and S3 are the lowresistance MOSFET devices with resistance RS (6 to 8 mΩ). Since we use a flat transformer, its leakage inductance Lm, Lm = 1 nH, and resistance are small. Other parameters are Cj = 50 ~ 100 nF, RL = 2 mΩ, L = 5 µH, CO = 10 µF. The input voltage is V1 = 30 VDC and output voltage is V2, the output current is IO. The transformer turn ratio is N that is usually much smaller than unity in SR DC/DC converters, e.g., N = 1:12 or 1/12. The repeating period is T = 1/f and conduction duty is k. There are four working modes: • • • •
Transformer Is in magnetizing Forward on Transformer Is in demagnetizing Switched off
12.2.1
Transformer Is in Magnetizing Process
The natural resonant frequency is ω=
© 2003 by CRC Press LLC
1 LmC j
(12.1)
1956_C12.fm Page 580 Monday, August 18, 2003 3:17 PM
where the Lm is the leakage inductance of the primary winding, the Cj is the drainsource junction capacitance of the main switch MOSFET S. If Cj is very small in nF, its charging process is very quickly completed. The primary current increases with slope V1/Lm, then the time interval of this period can be estimated t1 =
Lm NI O V1
(12.2)
This is the process used to establish the primary current from 0 to rated value NIO. 12.2.2
SwitchingOn
Switchingon period is controlled by the PWM signal, therefore, t2 ≈ kT
12.2.3
(12.3)
Transformer Is in Demagnetizing Process
The transformer demagnetizing process is estimated in π t3 = LmC j [ + 2
V1 ] Lm 2 2 V1 + ( NI O ) Cj
(12.4)
When the main switch is switchingoff there is a voltage stress, which can be very high. The voltage stress is dependent on the energy stored in the inductor and the capacitor: Vpeak =
Lm NI O Cj
(12.5)
The voltage stress peak value can be tens to hundreds of volts since Cj is small.
12.2.4
SwitchingOff
The switchoff period is controlled by the PWM signal, therefore, t4 ≈ (1 − k )T © 2003 by CRC Press LLC
(12.6)
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L
T S4
Lm
C
v3
D4
S2
V1 D2
RL
CO
R
v2
S3 1:N S1
D3
PWM
FIGURE 12.5 Active clamped flat transformer synchronous rectifier Luoconverter.
12.2.5
Summary
Average output voltage V2 and input current I1 are V2 = kNV1 − ( RL + RS +
Lm 2 N )I O T
(12.7)
and I 1 = kNI O
(12.8)
L RL + RS + m N 2 V2 I O T η= = 1− IO V1 I 1 kNV1
(12.9)
The power transfer efficiency:
When we set the frequency f = 150 to 200 kHz, we obtained the V2 = 1.8 V, N = 1/12, IO = 0 to 30 A, Volume = 2.5 (in.3). The average power transfer efficiency is 92.3% and the maximum PD is 21.6 W/in.3.
12.3 Active Clamped Synchronous Rectifier LuoConverter Active clamped flat transformer SR Luoconverter is shown in Figure 12.5. The clamped circuit effectively suppresses the voltage stress during the main switch turnoff. Comparing the circuit in Figure 12.5 with the circuit in Figure 12.4, one more switch S2 is set in the primary side. It is switchedon and off exclusively to the main switch S1. When S1 is turningoff, S2 is switchingon. A large clamp capacitor C is connected in the primary winding to absorb the energy © 2003 by CRC Press LLC
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stored in the leakage inductor Lm. Since the clamp capacitor C is much larger than the drainsource capacitor Cj by usually hundreds of times, the stress voltage peak value remains at only a few volts. There are four working modes: • • • •
Transformer Is in magnetizing Forward on Transformer Is in demagnetizing Switched off
12.3.1
Transformer Is in Magnetizing
The natural resonant frequency is ω=
1 LmC j
(12.10)
where the Lm is the leakage inductance of the primary winding, the Cj is the drainsource junction capacitance of the main switch MOSFET S. If Cj is very small in nF, its charging process is very quickly completed. The primary current increases with slope V1/Lm, then the time interval of this period can be estimated t1 =
Lm NI O V1
(12.11)
This is the process to establish the primary current from 0 to rated value NIO. 12.3.2
SwitchingOn
Switchingon period is controlled by the PWM signal, therefore, t2 ≈ kT
12.3.3
(12.12)
Transformer Is in Demagnetizing
The transformer demagnetizing process is estimated by π t3 = LmC [ + 2 © 2003 by CRC Press LLC
V1 ] L V12 + m ( NI O )2 C
(12.13)
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where C is the active clamp capacitor in µF. The voltage stress depends on the energy stored in the inductor and the capacitor: Vpeak =
Lm NI O C
(12.14)
The voltage stress peak value is very small since capacitor C is large, measured in µF. 12.3.4
SwitchingOff
Switchingoff period is controlled by the PWM signal, therefore, t4 ≈ (1 − k )T
12.3.5
(12.15)
Summary
Average output voltage is V2 and input current is I1: V2 = kNV1 − ( RL + RS +
Lm 2 N )I O T
(12.16)
and I 1 = kNI O
(12.17)
L RL + RS + m N 2 V2 I O T η= = 1− IO V1 I 1 kNV1
(12.18)
The power transfer efficiency:
When we set the frequency f = 150 to 200 kHz, we obtained the V2 = 1.8 V, N = 1/12, IO = 0 to 30 A, volume = 2.5 (in.3). The average power transfer efficiency is 92.3% and the maximum power density (PD) is 21.6 W/in.3.
12.4 Double Current Synchronous Rectifier LuoConverter The converter in Figure 12.5 likes a half wave rectifier. The double current synchronous rectifier Luoconverter with active clamp circuit is shown in © 2003 by CRC Press LLC
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L2
FT Lm
C D2
1:N
+ –
V1 S2 PWM
S4
D4
CO
S3
D3
_ R + V2 L1
S1
D1
FIGURE 12.6 Doublecurrent synchronous rectifier Luoconverter.
Figure 12.6. The switches S1 to S4 are the lowresistance MOSFET devices with very low resistance RS (6 to 8 mΩ). Since S3 and S4 plus L1 and L2 form a double current circuit and S2 plus C is the active clamp circuit, this converter likes a full wave rectifier and obtains strong output current. Other parameters are C = 1 µF, Lm = 1 nH, RL = 2 mΩ, L = 5 µH, CO = 10 µF. The input voltage is V1 = 30 VDC and output voltage is V2, the output current is IO. The transformer turn ratio is N = 1:12. The repeating period is T = 1/ f and conduction duty is k. There are four working modes: • • • •
Transformer Is in magnetizing Forward on Transformer Is in demagnetizing Switched off
12.4.1
Transformer Is in Magnetizing
The natural resonant frequency is ω=
1 LmC j
(12.19)
where the Lm is the leakage inductance of the primary winding, the Cj is the drainsource junction capacitance of the main switch MOSFET S. If Cj is very small in nF, its charging process is very quickly completed. The primary current increases with slope V1/Lm, and the time interval of this period can be estimated t1 = © 2003 by CRC Press LLC
Lm NI O V1
(12.20)
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This is the process used to establish the primary current from 0 to rated value NIO. 12.4.2
SwitchingOn
Switchingon period is controlled by the PWM signal, therefore, t2 ≈ kT
12.4.3
(12.21)
Transformer Is in Demagnetizing
The transformer demagnetizing process is estimated in π t3 = LmC [ + 2
V1 ] L V12 + m ( NI O )2 C
(12.22)
When the main switch is switchingoff there is a very low voltage stress since the active clamp circuit is applied.
12.4.4
SwitchingOff
Switchingoff period is controlled by the PWM signal, therefore, t4 ≈ (1 − k )T
12.4.5
(12.23)
Summary
Average output voltage V2 and input current I1 are V2 = kNV1 − ( RL + RS +
Lm 2 N )I O T
(12.24)
and I 1 = kNI O
(12.25)
L RL + RS + m N 2 V2 I O T η= = 1− IO V1 I 1 kNV1
(12.26)
The power transfer efficiency is
© 2003 by CRC Press LLC
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L2
FT S4 1:N Lm
+ –
V1
Cr
S3
CO
D1
I2
R
+ _V2
D3 L1
C L4
S6
D4
S5
D5
D2 1:N
L3 S2
Lr PWM S1
D1
FIGURE 12.7 ZCS synchronous rectifier Luoconverter.
When we set the frequency f = 200 to 250 kHz, we obtained the V2 = 1.8 V, N = 12, IO = 0 to 35 A, volume = 2.5 (in.3). The average power transfer efficiency is 94% and the maximum PD is 25 W/in.3.
12.5 ZeroCurrentSwitching Synchronous Rectifier LuoConverter The zerocurrentswitching (ZCS) synchronous rectifier Luoconverter is shown in Figure 12.7. Since the power loss across the main switch S1 is high in the double current SR Luoconverter, we designed the ZCS, DC SR LuoConverter shown in Figure 12.7. This converter is based on the DC SR Luoconverter plus ZCS technique. It employs a double core flat transformer. There are four working modes: • • • •
Transformer Is in magnetizing Resonant period Transformer Is in demagnetizing Switched off
© 2003 by CRC Press LLC
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12.5.1
Transformer Is in Magnetizing
The ZCS resonant frequency is ωr =
1 Lr Cr
(12.27)
Lr Cr
(12.28)
I 1Zr ) V1
(12.29)
The normalized impedance is Zr = The shiftangular distance is α = sin −1 (
where the Lr is the resonant inductor and the Cr is the resonant capacitor. The primary current increases with slope V1/Lr , then the time interval of this period can be estimated I 1Lr V1
(12.30)
1 (π + α) ωr
(12.31)
t1 =
12.5.2
Resonant Period
The resonant period is, t2 =
12.5.3
Transformer Is in Demagnetizing
The transformer demagnetizing process is estimated in t3 =
V1 (1 + cos α )Cr I1
(12.32)
When the main switch is switchingoff there is a very low voltage stress since active clamp circuit is applied. © 2003 by CRC Press LLC
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12.5.4
SwitchingOff
Switchingoff period is controlled by the PWM signal, therefore, t4 =
12.5.5
V1 (t1 + t2 ) V cos α (IL + 1 ) − (t1 + t2 + t3 ) V2 I 1 Zr π / 2 + α
(12.33)
Summary
Average output voltage V2 and input current I1 are V2 = kNV1 − ( RL + RS +
Lr + Lm 2 N )I O T
(12.34)
and I 1 = kNI O
(12.35)
The power transfer efficiency is L + Lm 2 RL + RS + r N V2 I O T η= = 1− IO V1 I 1 kNV1
(12.36)
Since Lr is larger than Lm, therefore Lm can be ignored in the above formulae. When we set the V1 = 60 V and frequency f = 200 to 250 kHz, we obtained the V2 = 1.8 V, N = 1/12, IO = 0 to 60 A, volume = 4 (in.3). The average power transfer efficiency is 94.5% and the maximum PD is 27 W/in.3.
12.6 ZeroVoltageSwitching Synchronous Rectifier LuoConverter The zerovoltageswitching synchronous rectifier Luoconverter is shown in Figure 12.8, which is derived from the DC SR Luoconverter plus ZVS technique. It employs a double core flat transformer. There are four working modes: • • • •
Transformer Is in magnetizing Resonant period Transformer Is in demagnetizing Switched off
© 2003 by CRC Press LLC
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L2
FT
1:N
S4
D4
S3
D3
Lm Lr + –
I2
R
+ _V2
L1
C1
V1 D2 1:N
L4
S6
D6
S5
D5
S2
PWM
CO
L3 D1
S1
Cr
FIGURE 12.8 ZVS synchronous rectifier Luoconverter.
12.6.1
Transformer Is in Magnetizing
The ZVS resonant frequency is ωr =
1 Lr Cr
(12.37)
Lr Cr
(12.38)
V1 ) Zr I 1
(12.39)
The normalized impedance is Zr = The shiftangular distance is α = sin −1 (
where the Lr is the resonant inductor and the Cr is the resonant capacitor. The switch voltage increases with slope I1/Cr , then the time interval of this period can be estimated © 2003 by CRC Press LLC
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V1Cr I1
(12.40)
1 (π + α) ωr
(12.41)
t1 =
12.6.2
Resonant Period
The resonant period is, t2 =
12.6.3
Transformer Is in Demagnetizing
The transformer demagnetizing process is estimated in t3 =
I 1 (1 + cos α )Lr V1
(12.42)
While the main switch is switchingoff there is a very low voltage stress since active clamp circuit is applied.
12.6.4
SwitchingOff
Switchingoff period is controlled by the PWM signal, therefore, t4 =
12.6.5
t1 + t2 + t3 V1 −1 V2
(12.43)
Summary
Average output voltage V2 and input current I1 are V2 = kNV1 − ( RL + RS +
Lr //Lm 2 N )I O T
(12.44)
and I 1 = kNI O The power transfer efficiency is © 2003 by CRC Press LLC
(12.45)
1956_C12.fm Page 591 Monday, August 18, 2003 3:17 PM
L //Lm 2 RL + RS + r N V2 I O T η= = 1− IO V1 I 1 kNV1
(12.46)
Since Lr is larger than Lm, therefore Lr can be ignored in the above formulae. When we set the V1 = 60 V and frequency f = 200 to 250 kHz, we obtained the V2 = 1.8 V, N = 12, IO = 0 to 60 A, volume = 4 (in.3). The average power transfer efficiency is 94.5% and the maximum PD is 27 W/in.3.
Bibliography Blanc, J., Practical Application of MOSFET Synchronous Rectifiers, in Proceedings of the TelecomEng. Conference INTELEC’1991, Japan, 1991, p. 495. Chakrabarty, K., Poddar, G., and Banerjee, S., Bifurcation behavior of the buck converter, IEEE Trans. Power Electronics, 11, 439, 1996. Cobos, J.A., O. Grcia, J., and Sebastian, J.U., RCD clamp PWM forward converter with self driven synchronous rectification, in Proceedings of IEEE International Telecommunication Conference INTELEC’93, 1993, p. 1336. Cobos, J.A., Sebastian, J., Uceda, J., Cruz, E. de la, and Gras, J.M., Study of the applicability of selfdriven synchronous rectification to resonant topologies, in Proceedings of IEEE Power Electronics Specialists Conference, 1992, p. 933. Garofalo, F., Marino, P., Scala, S., and Vasca, F., Control of DCDC converters with linear optimal feedback and nonlinear feedforward, IEEE Trans. Power Electronics, 9, 607, 1994. Jovanovic, M.M., Zhang, M.T., and Lee, F.C., Evaluation of synchronousrectification efficiency improvement limits in forward converters, IEEE Transactions on Industrial Electronics, 42, 387, 1995. Leu, C.S., Hua, G., and Lee, F.C., Analysis and design of RCD clamp forward converter, in Proceedings of the VPEC’92, 1992, p. 198. Luo, F.L. and Chua, L.M., Fuzzy logic control for synchronous rectifier DC/DC converter, in Proceedings of the IASTED International ConferenceASC’00, Canada, 2000, p. 24. Mattavelli, P., Rossetto, L., and Spiazzi, G., Generalpurpose slidingmode controller for DC/DC converter applications, IEEE Trans. Power Electronics, 8, 609, 1993. Ogata, K., Designing Linear Control Systems with MATLAB, PrenticeHall, Upper Saddle River, NJ, 1994. Phillips, C.P. and Harbor, R., Feedback Control System, PrenticeHall, 1991. Rim, C.T., Joung, G.B., and Cho, G.H., Practical switch based statespace modeling of DCDC converters with all parasitics, IEEE Trans. Power Electronics, 6, 611, 1991. Sakai, E. and Harada, K., Synchronous Rectifier for Low Voltage Switching Converter, in Proceedings of the TelecomEng. Conference INTELEC’1995, Japan, 1995, p. 471. Yamashita, N., Murakami, N., and Yachi, Toshiaki., Conduction power loss in MOSFET synchronous rectifier with parallelconnected Schottky barrier diode, IEEE Transaction on Power Electronics, 13, 667, 1998.
© 2003 by CRC Press LLC
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13 Multiple EnergyStorage Element Resonant Power Converters
13.1 Introduction Multiple energystorage element resonant power converters (xelement RPC) are the sixth generation converters. As the transfer power becomes higher and higher, traditional methods are unable to deliver large amounts of power from the source to the final actuators with high efficiency. In order to reduce the power losses during the conversion process the sixth generation converters — multiple energystorage elements resonant power converters (xelement RPC), were created. They can be classified into two main groups • DC/DC resonant converters • DC/AC resonant inverters Both groups consist of multiple energystorage elements: two, three, or four elements. These energystorage elements are passive parts: inductors and capacitors. They can be connected in series or parallel in various methods. The circuits of the multiple energystorage elements converters are • Eight topologies of twoelement RPC shown in Figure 13.1. • Thirtyeight topologies of threeelement RPC shown in Figure 13.2. • Ninetyeight topologies of fourelement (2L2C) RPC shown in Figure 13.3. If no restriction such as 2L2C for fourelement RPC, the number of the topologies of fourelement RPC can be very large. How to investigate the large quantity of converters is a task of vital importance. This problem was outstanding in the last decade of last century. Unfortunately, it was not paid very much attention. This generation of converters were not well discussed, only a limited number of papers were published in the literature.
© 2003 by CRC Press LLC
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(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
FIGURE 13.1 The eight topologies of twoelement RPC.
13.1.1
TwoElement RPC
There are eight topologies of twoelement RPCs shown in Figure 13.1. These topologies have simple circuit structure and minimal components. Consequently, they can transfer the power from source to endusers with higher power efficiency and lower power losses. A particular circuitry analysis will be carried out in the next section. Usually, the twoelement RPC has a very narrow response frequency band, which is defined as the frequency width between the two halfpower points. The working point must be selected in the vicinity of the natural resonant frequency ω0 = © 2003 by CRC Press LLC
1 LC
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(1)
(2)
(5)
(6)
(7)
(8)
(9)
( 10 )
( 11 )
( 12 )
( 15 )
( 16 )
( 13 )
( 14 )
( 17 )
(3)
(4)
( 18 )
FIGURE 13.2 The thirtyeight topologies of threeelement RPC.
Another drawback is that the transferred waveform is usually not sinusoidal, i.e., the output waveform total harmonic distortion (THD) is not zero. Since total power losses are mainly contributed by the power losses across the main switches using resonant conversion technique, the twoelement RPC has a high power transferring efficiency.
13.1.2
ThreeElement RPC
There are 38 topologies of threeelement RPC that are shown in Figure 13.2. These topologies have one more component in comparison to the twoelement © 2003 by CRC Press LLC
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( 20 )
( 21 )
( 23 )
( 24 )
( 25 )
( 26 )
( 27 )
( 28 )
( 29 )
( 30 )
(31)
( 32 )
(33)
(34)
(35)
( 36 )
(37)
( 38 )
( 19 )
( 22 )
FIGURE 13.2 (continued)
RPC topologies. Consequently, they can transfer the power from source to endusers with higher power and high power transfer efficiency. A particular circuitry analysis will be carried out in the next chapter. Usually, the threeelement RPC has a much wider response frequency band, which is defined as the frequency width between the two halfpower points. If the circuit is a lowpass filter, the frequency bands can cover the frequency range from 0 to the natural resonant frequency ω 0 = 1 LC . The working point can be selected in the much wider frequency width which is lower than the natural resonant frequency ω 0 = 1 LC . Another advantage over the twoelement RPC topologies is that the transferred waveform can usually be sinusoidal, i.e., the output waveform THD is nearly zero. A wellknown monofrequency waveform transferring operation has very low EMI. © 2003 by CRC Press LLC
1956_C13.fm Page 597 Monday, August 18, 2003 3:18 PM
(1)
(2)
(3)
(4)
c
(5)
(6)
(7)
(8)
(9)
(10)
(11)
( 12 )
( 13 )
( 14 )
( 15 )
( 16 )
( 18 )
( 19 )
( 17 )
( 20 )
FIGURE 13.3 The ninetyeight topologies of fourelement (2L2C).
13.1.3
FourElement RPC
There are 98 topologies of fourelement RPC (2L2C) that are shown in Figure 13.3. Although these topologies have comparable complex circuit structures, they can still transfer the power from source to endusers with higher power efficiency and lower power losses. Particular circuitry analysis will be carried out in the next chapter. © 2003 by CRC Press LLC
1956_C13.fm Page 598 Monday, August 18, 2003 3:18 PM
( 21 )
( 22 )
( 23 )
( 24 )
( 25 )
( 26 )
( 27 )
( 29 )
( 30 )
( 31 )
( 32 )
( 35 )
( 36 )
( 39 )
( 40 )
( 33 )
( 37 )
( 34 )
( 38 )
( 28 )
FIGURE 13.3 (continued)
Usually, the fourelement RPC has a wide response frequency band, which is defined as the frequency width between the two halfpower points. If the circuit is a lowpass filter, the frequency bands can cover the frequency range from 0 to the high halfpower point, which is definitely higher than the natural resonant frequency ω 0 = 1 LC . The working point can be selected in a wide area across (lower and higher than) the natural resonant frequency © 2003 by CRC Press LLC
1956_C13.fm Page 599 Monday, August 18, 2003 3:18 PM
( 41 )
( 45 )
( 49 )
( 53 )
( 57 )
( 42 )
( 46 )
( 50 )
( 54 )
( 58 )
( 43 )
( 47 )
( 51 )
( 55 )
( 59 )
( 44 )
( 48 )
( 52 )
( 56 )
( 60 )
FIGURE 13.3 (continued)
ω 0 = 1 LC . Another advantage is that the transferred waveform is sinusoidal, i.e., the output waveform THD is very close to zero. As is wellknown, the monofrequencywaveform transferring operation has a very low electromagnetic interference (EMI) and a reasonable electromagnetic susceptibility (EMS) and electromagnetic compatibility (EMC).
13.2 Bipolar Current and Voltage Source Depending on the application, a resonant network can be lowpass filter, highpass filter, or bandpass filter. For a large power transferring process, © 2003 by CRC Press LLC
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( 61 )
( 65 )
( 69 )
( 62 )
( 66 )
( 70 )
( 73 )
( 74 )
( 77 )
( 78 )
( 63 )
( 67 )
( 71 )
( 75 )
( 79 )
( 64 )
( 68 )
( 72 )
( 76 )
( 80 )
FIGURE 13.3 (continued)
a lowpass filter is usually employed. In this case, inductors are arranged in series arms and capacitors are arranged in shut arms. If the first component is an inductor, only voltage source can be applied since inductor current is continuous. Vice versa, if the first component is a capacitor, only current source can be applied since capacitor voltage is continuous. Unipolar current and voltage source are easier to obtain using various pumps, such as buck pump, boost pump, and buckboost pump, which are introduced in Chapter 1. Bipolar current and voltage sources are more difficult to obtain using these pumps. There are some fundamental bipolar current and voltage sources listed in the following sections.
13.2.1
Bipolar Voltage Source
There are various methods to obtain bipolar voltage sources using pumps. © 2003 by CRC Press LLC
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( 81 )
( 82 )
( 83 )
( 85 )
( 86 )
( 87 )
( 89 )
( 93 )
( 97 )
( 90 )
( 94 )
( 91 )
( 95 )
( 84 )
( 88 )
( 92 )
( 96 )
( 98 )
FIGURE 13.3 (continued)
13.2.1.1 Two Voltage Source Circuit A bipolar voltage source using two voltage sources is shown in Figure 13.4. These two voltage sources have the same voltage amplitude and reverse polarity. There are two switches applied alternately switchingon or off to supply positive and negative voltage to the network. In the figure, the load is a resistance R. The circuit of this voltage source is likely a twoquadrant operational chopper. The conduction duty cycle for each switch is 50%. For safety reasons the particular circuitry design has to consider some small gap between the turn over (commutation) operations to avoid a shortcircuit. © 2003 by CRC Press LLC
1956_C13.fm Page 602 Monday, August 18, 2003 3:18 PM
S1
+V
S2 R
VO
–V
FIGURE 13.4 A bipolar voltage source using two voltage sources.
S3
S1 +V
R
VO S2
S4
FIGURE 13.5 A bipolar voltage source using single voltage source.
The repeating frequency is theoretically not restricted. For industrial applications, the operating frequency is usually arranged in the range between 10 kHz to 5 MHz depending on the application conditions. 13.2.1.2 One Voltage Source Circuit A bipolar voltage source using single voltage source is shown in Figure 13.5. Since only one voltage source is applied, there are four switches applied alternately switchingon or switchingoff to supply positive and negative voltage to the network. In the figure, the load is a resistance R. The circuit of this voltage source is likely to be a fourquadrant operational chopper. The conduction duty cycle for each switch is 50%. For safety reasons the particular circuitry design has to consider some small gap between the turn over (commutation) operations to avoid a shortcircuit. The repeating frequency is theoretically not restricted. For industrial applications, the operating frequency is usually arranged in the range between 10 kHz to 5 MHz depending on the application conditions. © 2003 by CRC Press LLC
1956_C13.fm Page 603 Monday, August 18, 2003 3:18 PM
L1
+V
S1
R
VO
S2
–V L2
FIGURE 13.6 A bipolar current voltage source using two voltage sources.
13.2.2
Bipolar Current Source
There are various methods used to obtain bipolar current sources using the pumps. 13.2.2.1 Two Voltage Source Circuit A bipolar current voltage source using two voltage sources is shown in Figure 13.6. These two voltage sources have the same voltage amplitude and reverse polarity. To obtain stable current each voltage source in series is connected by a large inductor. There are two switches applied alternately switchingon or switchingoff to supply positive and negative current to the network. In Figure 13.6, the load is a resistance R. The circuit of this current source is a twoquadrant operational chopper. The conduction duty cycle for each switch is 50%. For safety reasons the particular circuitry design has to consider some small gap between the turn over (commutation) operations to avoid a shortcircuit. The repeating frequency is theoretically not restricted. For industrial applications, the operating frequency is usually arranged in the range between 10 kHz to 5 MHz depending on the application conditions. 13.2.2.2 One Voltage Source Circuit A bipolar current voltage source using single voltage sources is shown in Figure 13.7. To obtain stable current the voltage source in series is connected by a large inductor. There are two switches applied alternately switchingon or off to supply positive and negative current to the network. In the figure, the load is a resistance R. The circuit of this current source is likely a twoquadrant operational chopper. The conduction duty cycle for each switch is 50%. For safety reasons
© 2003 by CRC Press LLC
1956_C13.fm Page 604 Monday, August 18, 2003 3:18 PM
L1
S1 +V R
VO
S2 L2
FIGURE 13.7 A bipolar current source using single voltage source.
I1= I
a
I2 = I
L2
L1
b
D1 S1
D2
S2
L
C
R
vo
Vin
FIGURE 13.8 A twoelement RPC.
the particular circuitry design has to consider some small gap between the turn over (commutation) operations to avoid a shortcircuit. The repeating frequency is theoretically not restricted. For industrial applications, the operating frequency is usually arranged in the range between 10 kHz to 5 MHz depending on the application conditions.
13.3 A TwoElement RPC Analysis This twoelement RPC is the circuit number six in Figure 13.1. The network is a lowpass capacitorinductor (CL) filter, and the first component is a capacitor. By previous analysis, the source should be a bipolar current source. Therefore, the circuit diagram of this twoelement RPC is shown in Figure 13.8. To simplify the analysis, the load can be considered resistive R. The energy source Vin is chopped by two main switches S1 and S2, it is a bipolar current source applied to the twoelement filter and load. The whole RPC equivalent circuit diagram is shown in Figure 13.9. © 2003 by CRC Press LLC
1956_C13.fm Page 605 Monday, August 18, 2003 3:18 PM
a iL
L
iO
+I Ii
0
vC
C
R
vO
I
b
FIGURE 13.9 The equivalent circuit diagram of the twoelement RPC.
13.3.1
Input Impedance
The whole network impendance including the load R is calculated by Z=
R + jωL R + jωL = 1 + jωC( R + jωL) 1 − ω 2 CL + jωRC
(13.1)
The natural resonance angular frequency is ω0 =
1 CL
(13.2)
Using the relevant frequency β ω ω = ω0 CL
(13.3)
ω 0L 1 = R ω 0 RC
(13.4)
β= and the quality factor Q Q= we rewrite the input impendance
1 + jβQ Z Z = = ∠φ 2 R 1 − β + jβ / Q R
(13.5)
where Z 1 + (βQ)2  = R (1 − β2 )2 + (β / Q)2 © 2003 by CRC Press LLC
φ = tan −1 βQ − tan −1
β/Q 1 − β2
1956_C13.fm Page 606 Monday, August 18, 2003 3:18 PM
13.3.2
Current Transfer Gain
The current transfer gain is calculated by G(ω ) =
iO 1 1 = = 2 iin 1 + jωC( R + jωL) 1 − ω CL + jωRC
(13.6)
Defining an auxiliary parameter B B(ω ) = 1 + jωC( R + jωL)
(13.7)
Hence, G(ω ) =
1 = G∠θ B(ω )
(13.8)
Using the relevant frequency and quality factor, G(β) =
iO 1 = iin 1 − β 2 + j β Q
B(β) = 1 − β 2 + j
(13.9)
β Q
(13.10)
and G=
13.3.3
1 (1 − β ) + (β / Q)2 2 2
θ = − tan −1
β/Q 1 − β2
Operation Analysis
Based on the equivalent circuit in Figure 13.9, the state equation is established as: R − i˙L = L 1 v˙ C − C
1 0 i L L + I 0 vC C
(13.11)
By Laplace transform, the state equation in time domain could be transferred into sdomain, given by: © 2003 by CRC Press LLC
1956_C13.fm Page 607 Monday, August 18, 2003 3:18 PM
sLI L ( s) − LI L (0) = VC ( s) − I L ( s)R sCVC ( s) − CVC (0) = I / s − I L ( s)
(13.12)
yielding: I L ( s) =
sLCI L (0) + I / s + CVC (0) s[ I L (0) − I ] + [VC (0) − IR]/ L I = + 1 R 2 R2 s 2 LC + sRC + 1 s (s + ) + − 2 2L LC 4L
(13.13)
The inductor current in time domain is then derived by taking the inverse Laplace transform, giving: iL (t) = a1e − αt cos βt +
b1 − a1α − αt e sin βt + I β
(13.14)
where a1 = I L (0) − I
b1 = [VC (0) − IR]/ L
α is the damping ratio, α = R 2L . β is the resonant angular frequency, β=
(1 LC) − (R2
)
4L2 .
Similarly, the resonant capacitor voltage in sdomain is attained as:
VC ( s) =
sLCVC (0) +
IR + [L( I L (0) − I ) + RCVC (0)] s s 2 LC + sRC + 1
(13.15)
sLC[VC (0) − IR] + {L[ I − I L (0)] + RCVC (0) − IR C} IR + s 2 LC + sRC + 1 s 2
=
The corresponding expression in time domain is written by: vC (t) = a2 e − αt cos βt +
b2 − a2 α − αt e sin βt + IR β
(13.16)
where a2 = VC (0) − IR
b2 = {L[ I − I L (0)] + RCVC (0) − IR 2 C} / LC
To make the analytic Equation (13.14) and Equation (13.16) available, the initial conditions must be known at first. Here the periodic nature is applied © 2003 by CRC Press LLC
1956_C13.fm Page 608 Monday, August 18, 2003 3:18 PM
under steady state operation. Namely, during one switching cycle, the resonant voltage and current at the initial instant should be the same absolute values with negative sign as those at the half cycle, that is i L ( 0) = I L ( 0) = − i L (
Ts ) 2
vC (0) = VC (0) = − vC (
Ts ) 2
(13.17)
Substituting Equation (13.17) into Equation (13.14) and Equation (13.16), respectively, yields: αT − s βTs βT b1 − a1α − α2Ts 2 cos( − I ( 0 ) = a e ) + sin( s ) + I e L 1 2 2 β αT − s βT βTs b2 − a2 α − α2Ts 2 cos( 0 − ( ) = ) + sin( s ) + IR V a e e C 2 2 2 β
(13.18)
Rearranging, m11VC (0) + m12 I L (0) = n1 m21VC (0) + m22 I L (0) = n2 Where m11 =
m12 = e
n1 = Ie
−
−
m21 = e
αTs 2
αTs 2
−
1 − e L
[β cos(
[β cos(
αTs 2
n2 = Ie © 2003 by CRC Press LLC
−
αTs 2
[Rβ cos(
sin(
βTs ) 2
βTs βT ) − α sin( s )] + β 2 2
βTs βT ) + α sin( s )] − βI 2 2
[β cos(
m22 = −
αTs 2
βTs βT ) + α sin( s )] + β 2 2
1 − e C
αTs 2
sin(
βTs ) 2
βTs βT 1 − αRC )− sin( s )] − βIR C 2 2
(13.19)
1956_C13.fm Page 609 Monday, August 18, 2003 3:18 PM
FIGURE 13.10 General waveforms of the resonant voltage vC and current iL.
Since all the parameters shown in the coefficients of Equation (13.19) are constant for a given circuit, the initial values of the resonant voltage and current can be calculated. Thus, the complete expressions of the resonant voltage and current are obtained by substituting VC(0) and IL(0) into Equation (13.14) and Equation (13.16). Figure 13.10 shows the general waveforms of resonant voltage vC(t) and current iL(t). As seen, both of them are oscillatory and trackfollowing. Actually, further investigation of Equation (13.14) states that inductor current can be rewritten as: iL (t) = a1e − αt cos βt +
b1 − a1α − αt e sin βt + I = Ae − αt sin(βt + ϕ) + I β
(13.20)
where A = a12 + (
b1 − a1α 2 ) β
ϕ = tan −1 (
a1β ) b1 − a1α
It is apparent that the inductor current is composed of two different components. One is the oscillatory component, consisting of the sinusoidal function. The other is the compulsory component, given as the input current I. The oscillatory component is timeattenuation. With the time increasing, it will be attenuated to zero and the inductor current is then convergent to the compulsory component. The attenuating rate is determined by the damping ratio α. Larger ratios cause faster attenuation. Similar conclusions can also be made about the capacitor voltage vC(t). © 2003 by CRC Press LLC
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When the value of damping factor e −αTs 2 is approaching 1, the resonant voltage and current will contain an undamped oscillatory component. Hence, the coefficients in Equation (13.19) can be simplified accordingly, giving: ' m11 =
βT 1 sin( s ) 2 L
' m12 = β cos(
n1' = β[cos(
βTs βT ) − 1]I + α sin( s )I 2 2
' m21 = β cos(
' m22 =−
βTs βT ) − α sin( s ) + β 2 2
βTs βT ) + α sin( s ) + β 2 2
βT 1 sin( s ) C 2
n2' = I[Rβ cos(
13.3.4
βTs βT 1 − αRC )− sin( s )] − βIR C 2 2
Simulation Results
For the purpose of verifying the mathematical derivations, a prototype bipolar current source resonant inverter is proposed for simulation and experiments. The simulation is carried out by Pspice and the results are presented in Figure 13.11a, where the upper channel is the input squarewave current Ii and the lower channel is the output current io, respectively. The corresponding FFT spectrums are shown in Figure 13.11b. From the results, it can be found that the output current is very sleekly sinusoidal with the amplitude larger than the input fundamental current. The THD value is only 1.2%. It is obvious that the resonant network has the capability of attenuating the higher order harmonics in the input squarewave current and transferring their energy into the output current. Due to the advantages of high current transfer gain and negligible output harmonics, this inverter could be widely used in many highfrequency hugecurrent applications.
13.3.5
Experimental Results
The corresponding resonant waveforms under this condition are shown in Figure 13.12, where both the capacitor voltage and the inductor current, i.e., output current are undamped oscillatory. © 2003 by CRC Press LLC
1956_C13.fm Page 611 Monday, August 18, 2003 3:18 PM
1.0A 0A 1.0A I(I1)
4.0A
0A SEL>> 4.0A 11.94ms I(R1)
11.95ms
11.96ms
11.97ms
11.98ms
11.99ms
12.00ms
Time (a) The input and output current waveforms
1.0A (35.588K,921.202m) (107.167K,369.528m) 0.5A
(178.583K,245.929m)
SEL>> 0A 2.0A
I(I1) (35.588K,1.8294)
1.0A
0A 0Hz I(R1)
0.2MHz
0.4MHz
0.6MHz
0.8MHz
1.0MHz
Frequency (b) The corresponding FFT spectrums
FIGURE 13.11 The simulation waveforms of the input and output currents.
© 2003 by CRC Press LLC
1.2MHz
1.4MHz
1956_C13.fm Page 612 Monday, August 18, 2003 3:18 PM
FIGURE 13.12 Tested waveforms of the resonant voltage and current under undamped condition.
Bibliography Ang, S.S., Power Switching Converters, New York: Marcel Dekker, 1995. Batarseh, I., Resonant converter topologies with three and four energy storage elements, IEEE Transactions on Power Electronics, 9, 64, 1994. Belaguli, V. and Bhat, A.K. S., Seriesparallel resonant converter operating in discontinuous current modeanalysis, design, simulation, and experimental results, IEEE Transactions on Circuits and System, 47, 433, 2000. Bhat, A.K.S., Analysis and design of a seriesparallel resonant converter with capacitive output filter, IEEE Transactions on Industry Applications, 27, 523, 1991. Bhat, A.K.S. and Dewan, S.B., Analysis and design of a high frequency resonant converter using LCC type Commutation, in Proceedings of IEEE Industry Applications Society Annual Meeting, 1986, p. 657. Cosby, Jr., M.C. and Nelms, R.M., A resonant inverter for electronic ballast applications, IEEE Transactions on Industry Electronics, 41, 418, 1994. Johnson, S.D. and Erickson, R.W., Steadystate analysis and design of the parallel resonant converter, IEEE Transactions on Power Electronics, 3, 93, 1988. Jones, C.B. and Vergez, J.P., Application of PWM techniques to realize a 2 MHz offline switching regulator, with hybrid implementations, in Proceedings of IEEE APEC’87, 1986, p. 221. Kang, Y.G. and Upadhyay, A.K., Analysis and design of a halfbridge parallel resonant converter operating above resonance, IEEE Transactions on Industry Applications, 27, 386, 1991. King, R.J. and Stuart, T.A., Modeling the fullbridge seriesresonant power converter, IEEE Transaction on Aerospace and Electronic System, 18, 449, 1982. © 2003 by CRC Press LLC
1956_C13.fm Page 613 Monday, August 18, 2003 3:18 PM
Kisch, J.J. and Perusse, E.T., Megahertz power converters for specific power systems, in Proceedings of IEEE APEC’87, 1987, p. 115. Kislovski, A.S., Redl, R., and Sokal, N.O., Dynamic Analysis of SwitchingMode DC/DC Converters, New York, Van Nostrand Reinhold, 1991. Mitchell, D.M., DCDC Switching Regulator Analysis, New York, McGrawHill, 1988. Nathan, B.S. and Ramanarayanan, V., Analysis, simulation and design of series resonant converter for high voltage applications, in Proceedings of IEEE International Conference on Industrial Technology’00, 2000, p. 688. Severns, R.P., Topologies for threeelement resonant converters, IEEE Transactions on Power Electronics, 7, 89, 1992. Steigerwald, R.L., A comparison of halfbridge resonant converter topologies, IEEE Transactions on Power Electronics, 3, 174, 1988. Tanaka, J., Yuzurihara I., and Watanabe, T., Analysis of a fullbridge parallel resonant converter, in Proceedings of 13th International Telecommunications Energy Conference, 1991, p. 302. Witulski, A. and Erickson, R.W., Steadystate analysis of the series resonant converter, IEEE Transactions on Aerospace Electronics, 21, 791, 1985.
© 2003 by CRC Press LLC
1956_C14.fm Page 615 Thursday, August 7, 2003 9:47 PM
14 ΠCLL Current Source Resonant Inverter
14.1 Introduction This chapter introduces a threeelement current source resonant inverter (CSRI): ΠCLL CSRI consists of three energystorage elements CLL, the ΠCLL. A bipolar current source is employed in this circuit as described in the previous chapter and shown in Figure 13.7. Since there is no transformer and the circuit is not working in pushpull operation, the control circuit is very simple and power losses are low. This ΠCLL CSRI is shown in Figure 14.1. The energy source is a DC voltage Vin, which is chopped by two mains switches S1 and S2. The three energystoring elements are C, L1 and L2. Two inductors can be different, i.e., L2 = p L1 with p as a random value. The load can be a coil, transformer or HF annealing equipment. A resistance Req is assumed. Its equivalent circuit diagram is shown in Figure 14.2. 14.1.1
Pump Circuits
In this application two boost pumps are used working at the conduction duty k = 0.5. Each pump consists of the common DC voltage source Vin, a switch S, and a large inductor L. The pumpout energy is usually measured by output current injection.
14.1.2
Current Source
An ideal current source has infinite impedance and constant output current. If the inductance of the pump circuits is large enough, the current flowing through it may keep a nearly constant value. The internal equivalent impedance of the pump is very high. The ripple of the inductor current depends on the input voltage, inductor’s inductance, switching frequency, and conduction duty.
© 2003 by CRC Press LLC
1956_C14.fm Page 616 Thursday, August 7, 2003 9:47 PM
L10
VL1
+
_
L1 S1
+ V in _
+
C
+
VC
L2
_
V_ L2 +
Req S2
L20
VO _
R
FIGURE 14.1 The ΠCLL current source resonant inverter. L1 +
+ Ii  Ii
ii
C
L2
Req
VO _
FIGURE 14.2 The equivalent circuit.
14.1.3
Resonant Circuit
Like other resonant inverters, this ΠCLL CSRI consists of a resonant circuit sandwiched between the current source (input switching circuit) and the output load. The resonant circuit can be considered as a ΠCLL lowpass filter. By network theory, these three components construct a circuit that is no longer a real lowpass filter. Therefore, the ΠCLL circuit has two peak resonant points. It gives more convenience to designers to match in the industrial applications.
14.1.4
Load
Load is usually resistive load or inductive plus resistive load. To simplify the problem we use Req to represent either an actual or an equivalent resistance, to consume the output power. This assumption is reasonable, because the load inductance can be considered the parallel part to the inductor L2. 14.1.5
Summary
The switching circuit consists of two pumps (two boost pumps employed): the Req is as mentioned, either an actual or an equivalent AC load resistance. © 2003 by CRC Press LLC
1956_C14.fm Page 617 Thursday, August 7, 2003 9:47 PM
The source current ii is a constant current yielded by input voltage Vi via large inductors L10 and L20. To operate this circuit, S1 is turned on and off in 180° (S2 is idle) at the frequency ω = 2πf. After the switching circuit, input current can be considered a bipolar squarewave current alternating in value between +Ii and –Ii that is then input to the resonant circuit section. The equivalent circuit is shown in Figure 14.2.
14.2 Mathematic Analysis In order to concentrate the function analysis of this ΠCLL, we assume: 1. The inverter’s source is a constant current source determined by the pump circuits. 2. Two MOSFETs in the switching circuit are turnedon and turnedoff 180° out of phase with each other at same switching frequency and with a duty cycle of 50%. 3. Two switches are ideal components without onresistance, and negligible parasitic capacitance and zero switching time. 4. Two diodes are components having a zero forward voltage drop and forward resistance. 5. Four energystorage elements are passive, linear, timeinvariant, and do not have parasitic reactive components. Using these assumptions, the following analyses are based on using Figure 14.2.
14.2.1
Input Impedance
This CSRI is a thirdorder system. The mathematic analysis of operation and stability is more complex than three energystorage element current source resonant inverters. The input impedance is given by
Z(ω ) =
−ω 2 L1L2 + jωReq (L1 + L2 ) Req [1 − ω 2 (L1 + L2 )C] + jωL2 (1 − ω 2 L1C)
(14.1)
The corresponding phase angle is φ(ω ) = tan −1 { © 2003 by CRC Press LLC
ωReq (L1 + L2 ) −ω L1L2 2
} − tan −1 {
ωL2 (1 − ω 2 L1C) } Req [1 − ω 2 (L1 + L2 )C]
(14.2)
1956_C14.fm Page 618 Thursday, August 7, 2003 9:47 PM
Define B(ω ) = Req [1 − ω 2 (L1 + L2 )C] + jωL2 (1 − ω 2 L1C)
(14.3)
So that
Z(ω ) =
14.2.2
−ω 2 L1L2 + jωReq (L1 + L2 ) B(ω )
(14.4)
Components’ Voltages and Currents
This ΠCLL CSRI has three resonant components C, L1, and L2, and the output equivalent resistance Req. In order to compare with the parameters easily, all components’ voltages and currents are responded to the input fundamental current Ii. All transfer functions are in frequency domain (ωdomain). Voltage and current on capacitor C: −ω 2 L1L2 + jωReq (L1 + L2 ) VC (ω ) = Z(ω ) = I in (ω ) B(ω )
(14.5)
2 3 I C (ω ) −ω Req C(L1 + L2 ) − jω CL1L2 = I i (ω ) B(ω )
(14.6)
Voltage and current on inductor L1: 2 VL1 (ω ) −ω L1L2 + jωReq L1 = I in (ω ) B(ω )
(14.7)
I L1 (ω ) Req + jωL2 = I in (ω ) B(ω )
(14.8)
Voltage and current on inductor L2:
© 2003 by CRC Press LLC
VL 2 (ω ) jωReq L2 = I in (ω ) B(ω )
(14.9)
Req I L 2 (ω ) = I in (ω ) B(ω )
(14.10)
1956_C14.fm Page 619 Thursday, August 7, 2003 9:47 PM
ΠCLL Current Source Resonant Inverter
619
The output voltage and current on the resistor Req: VO (ω ) VL 2 (ω ) jωReq L2 = = I in (ω ) I in (ω ) B(ω )
(14.11)
The current transfer gain is given by g (ω ) =
IO (ω ) jωL2 jωL2 = = 2 Iin (ω ) B(ω ) Req [1 − ω (L1 + L2 )C] + jωL2 (1 − ω 2 L1C)
= (1 − ω 2 L1C) − j
(14.12)
1 = g∠θ Req [1 − ω 2 (L1 + L2 )C] ωL2
Thus, 1
 g(ω )= (1 − ω 2 L1C)2 +
θ(ω ) = tan −1
14.2.3
(14.13)
Req 2 [1 − ω 2 (L1 + L2 )C]2 (ωL2 )2
Req [1 − ω 2 (L1 + L2 )C]
(14.14)
ωL2 (1 − ω 2 L1C)
Simplified Impedance and Current Gain
Usually, we are interested in the input impedance and output current gain rather than all transfer functions listed in previous section. To simplify the operation, we can select: ω0 =
1 L1C
β=
ω ω0
Q=
ω 0L 1 = Req ω 0 CReq
and
p=
L2 L1
Hence Z(ω ) =
=
= © 2003 by CRC Press LLC
−β2ω 0 2 L1L2 + jβω 0 Req (L1 + L2 ) Req [1 − β2ω 0 2 (L1 + L2 )C] + jβω 0 L2 (1 − β2ω 0 2 L1C) −β2ω 0 2 pL12 + jβω 0 Req L1(1 + p) Req [1 − β2ω 0 2 L1(1 + p)C] + jβω 0 pL1(1 − β2ω 0 2 L1C) − p(βQReq )2 + j(1 + p)βQReq 2 Req {[1 − (1 + p)β2 ] + jpβQ(1 − β2 )}
= Z∠φ
(14.15)
1956_C14.fm Page 620 Thursday, August 7, 2003 9:47 PM
620
Advanced DC/DC Converters
Then obtain, B(β) = Req [1 − (1 + p)β 2 + jpβQ(1 − β 2 )]
(14.16)
and φ(ω ) = tan −1 { = tan −1
βω 0 Req L1 (1 + p) − pβ 2 ω 0 2 L12
} − tan −1 {
pβω 0 L1 (1 − β 2 ω 0 2 L1C) } Req [1 − β 2 ω 0 2 L1 (1 + p)C]
1+ p pβQ(1 − β 2 ) − tan −1 − pβQ 1 − β 2 (1 + p)
= π − tan −1
(14.17)
1+ p pβQ(1 − β 2 ) − tan −1 pβQ 1 − β 2 (1 + p)
Therefore, Z=
− pβ2Q 2 + jβQ(1 + p) R = Z θ 1 − (1 + p)β2 + jpβQ(1 − β2 ) eq
(14.18)
where Z =
p 2β 4Q 4 + β2Q 2 (1 + p)2 [1 − (1 + p)β2 ]2 + [pβQ(1 − β2 )]2
Req
( pβ 2Q 2 )2 + [βQ(1 + p)]2 Z = Req [1 − (1 + p)β 2 ]2 + [pβQ(1 − β 2 )]2
(14.19)
and φ = π − tan −1
1+ p pβQ(1 − β 2 ) − tan −1 pβQ 1 − (1 + p)β 2
The characteristics of input impedance Z/Req vs. relevant frequency β referring to p = 0.5 and various Q, is shown in Figure 14.3 and Table 14.1. The characteristics of phase angle φ vs. relevant frequency β referring to p = 0.5 and various Q, is shown in Figure 14.4 and Table 14.2. The current transfer gain becomes g=
© 2003 by CRC Press LLC
1 = g θ 1 − (1 + p)β2 2 + 1− β jpQ
(14.20)
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ΠCLL Current Source Resonant Inverter
621
FIGURE 14.3 The curves of Z/Req vs. β referring to Q.
TABLE 14.1 Z/Req vs. β Referring to p = 0.5 and Various Q Q = 0.2 0.5 1 2 5
β = 0.5
0.678
0.755
0.83
1.0
1.5
2.0
3.0
5.0
0.2397 0.5954 1.1652 2.1693 4.3323
0.6513 1.5809 2.8924 4.6483 7.9346
1.5266 3.4353 5.3662 7.1323 11.0396
5.9126 8.6490 9.6875 10.9302 16.4384
0.6013 1.5207 3.1623 7.2111 29.1548
0.1898 0.4790 0.9852 2.1031 5.7645
0.1202 0.3029 0.6183 1.2804 3.3015
0.0721 0.1814 0.3673 0.7437 1.8719
0.0412 0.1033 0.2076 0.4162 1.0415
where g =
1 1 − (1 + p)β2 2 [ ] + (1 − β2 )2 pQ
and θ = − tan −1 © 2003 by CRC Press LLC
1 − (1 + p)β 2 p(1 − β 2 )Q
(14.21)
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Advanced DC/DC Converters
FIGURE 14.4 The curves of φ vs. β referring to Q.
TABLE 14.2 φ vs. β Referring to p = 0.5 and Various Q β = 0.5 Q = 0.2 0.5 1 2 5
1.5442 1.5050 1.4445 1.3521 1.2827
0.678
0.755
0.83
1.0
1.5
2.0
3.0
5.0
1.4985 1.3965 1.2601 1.1276 1.1732
1.4008 1.1856 0.9755 0.8863 1.0760
2.2849 2.8022 3.1587 3.5185 4.0348
1.6374 1.7359 1.8925 2.1588 2.6012
1.5917 1.6209 1.6585 1.6879 1.6593
1.5839 1.6011 1.6184 1.6220 1.6011
1.5785 1.5869 1.5912 1.5873 1.5788
1.5749 1.5776 1.5769 1.5746 1.5724
The characteristics of current transfer gain g vs. relevant frequency β referring to p = 0.5, 1 and 2, and various Q, is shown in Figure 14.5 to Figure 14.7 and Table 14.3 to Table 14.5. The characteristics of the phase angle θ vs. relevant frequency β referring to p = 0.5 and various Q, is shown in Figure 14.8 and Table 14.6. For various β and Q we have different current transfer gain. For example, when β2 = 1 with any p, we have g = –jQ = Q ∠ 90°. It means that the output current can be larger than the fundamental harmonic of the input current! The larger the value of Q is, the higher the gain g. Actually, set β2 = t, we can find the maximum g from d g= 0 dt © 2003 by CRC Press LLC
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ΠCLL Current Source Resonant Inverter
FIGURE 14.5 The curves of g vs. β referring to Q.
FIGURE 14.6 The curves of g vs. β referring to Q. © 2003 by CRC Press LLC
623
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Advanced DC/DC Converters
FIGURE 14.7 The curves of g vs. β referring to Q.
TABLE 14.3 g vs. β Referring to p = 0.5 and Various Q β = 0.5 Q = 0.2 0.5 1 2 5
0.0799 0.1978 0.3831 0.6860 1.1094
0.678
0.755
0.83
1.0
1.5
2.0
3.0
5.0
0.2169 0.5236 0.9404 1.4119 1.7528
0.5082 1.1361 1.7346 2.1236 2.2895
1.9679 2.8558 3.1122 3.1879 3.2101
0.2000 0.5000 1.0000 2.0000 5.0000
0.0630 0.1549 0.2937 0.4957 0.7136
0.0397 0.0958 0.1715 0.2561 0.3162
0.0236 0.0541 0.0866 0.1109 0.1224
0.0130 0.0265 0.0356 0.0399 0.0414
TABLE 14.4 g vs. β Referring to p = 1 and Various Q β = 0.5 Q = 0.2 0.5 1 2 5
0.1978 0.4682 0.8000 1.1094 1.2883
or © 2003 by CRC Press LLC
0.678
0.755
0.83
1.0
1.5
2.0
3.0
5.0
1.2446 1,6939 1.8075 1.8397 1.8490
0.9782 1.7609 2.1355 2.2734 2.3171
0.4353 1.0394 1.8138 2.5943 3.0850
0.2000 0.5000 1.0000 2.0000 5.0000
0.0852 0.2070 0.3778 0.5848 0.7495
0.0563 0.1313 0.2169 0.2879 0.3246
0.0340 0.0721 0.1020 0.1178 0.1238
0.0183 0.0323 0.0386 0.0408 0.0415
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ΠCLL Current Source Resonant Inverter
625
TABLE 14.5 g vs. β Referring to p = 2 and Various Q β = 0.5 Q = 0.2 0.5 1 2 5
0.6860 1.1094 1.2649 1.3152 1.3304
0.678
0.755
0.83
1.0
1.5
2.0
3.0
5.0
0.6673 1.2862 1.6438 1.7918 1.8409
0.4184 0.9670 1.5694 2.0406 2.2720
0.3098 0,7563 1.4007 2.2360 2.9709
0.2000 0.5000 1.0000 2.0000 5.0000
0.1035 0.2480 0.4370 0.6349 0.7648
0.0711 0.1596 0.2457 0.3030 0.3279
0.0433 0.0848 0.1099 0.1207 0.1243
0.0227 0.0355 0.0398 0.0412 0.0416
FIGURE 14.8 The curves of θ vs. β referring to Q.
TABLE 14.6 θ vs. β Referring to p = 0.5 and Various Q Q = 0.2 0.5 1 2 5
β = 0.5
0.678
0.755
0.83
1.0
1.5
2.0
3.0
5.0
1.5109 1.4219 1.2793 1.0304 0.5880
1.4533 1.2840 1.0378 0.7030 0.3268
1.3505 1.0604 0.7290 0.4200 0.1768
0.9120 0.4769 0.2528 0.1284 0.0516
1.5708 1.5708 1.5708 1.5708 1.5708
1.4920 1.3759 1.1948 0.9025 0.4690
1.4514 1.2793 1.0304 0.6947 0.3218
1.3811 1.1233 0.8058 0.4802 0.2054
1.2532 0.8828 0.5465 0.2953 0.1211
© 2003 by CRC Press LLC
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626
Advanced DC/DC Converters 1 − (i + p)t (1 + p) + (1 − t) = 0 pQ
(14.22)
We obtain t=
1 + p + pQ = 1 + 2 p + p 2 + pQ
1 p + p2 1+ 1 + p + pQ
If taking Q = 1, t = β2 = 0.6, or β = 0.7746, g = 2.236. If this inverter is working at the conditions: β = 1 and Q >> 1, Z=
φ=
jQ 1 −1 + j Q
Req =⋅ − jQReq
(14.23)
1 ⋅ π π π − tan −1 = −π=− −Q 2 2 2
correspondingly g=
1 =⋅ jQ − jp / pQ
(14.24)
θ = −π / 2 The ΠCLL circuit is not only the resonant circuit, but the bandpass filter as well. All higher order harmonic components in the input current are effectively filtered by the ΠCLL circuit. The output current is nearly a pure sinusoidal waveform with the fundamental frequency ω = 2πf. 14.2.4
Power Transfer Efficiency
The power transfer efficiency is a very important parameter and is calculated here. From Figure 14.5 we know the input current is ii(ωt), i.e., + I ii (ωt) = i − I i
2nπ ≤ ωt ≤ (2n + 1)π (2n + 1)π ≤ ωt ≤ 2(n + 1)π
with n = 0, 1, 2, 3, … ∞
where Ii = V1 Z + jωL10 that varies with different frequency. © 2003 by CRC Press LLC
(14.25)
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ΠCLL Current Source Resonant Inverter
627
This is a square waveform pulsetrain. Using fast fourier transform (FFT), we have the spectrum form as
ii (ωt) =
2Ii π
∞
∑ n =1
sin(2n + 1)ωt 2n + 1
(14.26)
The fundamental frequency component is i fund (ωt) =
2Ii sin ωt π
(14.27)
i 2 ( ωt ) = g
2Ii sin ωt π
(14.28)
Output current is
Because of the assumptions no power losses were considered. The power transfer efficiency from DC source to AC output is calculated in following equations. The total input power is Pin = I i 2 ∗ real(Z)
(14.29)
The AC output power is gathered in the fundamental component that is Pfund = ( g
2Ii 2 ) Req π 2
(14.30)
The power transfer efficiency is
η=
Pfund Pin
2( I i  g)2 Req 2 g2 π2 cos φ = = π2 I i 2 ∗ real(Z)
(14.31)
14.3 Simulation Results To verify the design and calculation results, PSpice simulation package was applied for these circuits. Choosing VI = 30 V, all pump inductors Li = 10mH, the resonant capacitor C = 0.2 µF, and inductors L1 = L2 = 70 µH, load R = 10 Ω, k = 0.5 and f = 35 kHz. The input and output current waveforms are © 2003 by CRC Press LLC
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Advanced DC/DC Converters
1.0A 0A 1.0A I(I1)
4.0A
0A SEL>> 4.0A 11.94ms I(R1)
11.95ms
11.96ms
11.97ms 11.98ms Time (a) Input and output circuit waveforms of piCLL CSRI
11.99ms
12.00ms
1.0A (35.000K, 934.769m) (104.917K, 379.501m)
0.5A SEL>> 0A 2.0A
(174.833K, 250.929m) (244.750K, 180.877m)
I(I1) (35.000K, 1.8101)
1.0A
0A 0Hz
0.2MHz
I(R1)
0.4MHz
0.6MHz
0.8MHz
1.0MHz
1.2MHz
1.4MHz
Frequency
(b) Corresponding FFT
FIGURE 14.9 Input and output current waveforms of ΠCLL circuit at f = 35KHz.
shown in Figure 14.9a. Their corresponding FFT spectrums are shown in Figure 14.9b. It is obviously illustrated that the output waveform is nearly a sinusoidal function, and its corresponding THD is nearly unity.
14.4 Discussion 14.4.1
Function of the ΠCLL Circuit
As a ΠCLC filter, it is a typical lowpass filter. All harmonics with frequency ω > ω0 will be blocked. ΠCLL filter circuit has thoroughly different characteristics from that of lowpass filters. It allows the signal with higher frequency ω > ω0 (it means β > 1 in Section 14.2) passing it and enlarging the energy.
© 2003 by CRC Press LLC
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ΠCLL Current Source Resonant Inverter 14.4.2
629
Applying Frequency to this ΠCLL CSRI.
From our analysis and verifications we found the fact that the effective applying frequency to this ΠCLL current source resonant inverter is (0.8 to 2.0) f0. Outside this region both current transfer gain and efficiency are falling fast.
14.4.3
Explanation of g > 1
We recognized the fact that current transfer gain is greater than unity from mathematical analysis, and simulation and experimental results. The reason to enlarge the fundamental current is that the resonant circuit transfers the energy of other higher order harmonics to the fundamental component. Therefore the gain of the fundamental current can be greater than unity.
14.4.4
DC Current Component Remaining
Since the ΠCLL resonant circuit could not block the DC component, the output current still remains the same DC current component. This is not useful for most ordinary inverter applications.
14.4.5
Efficiency
From mathematical calculation and analysis, and simulation and experimental results, we can obtain very high efficiency. Its maximum value can be nearly unity! It means this ΠCLL resonant circuit can transfer the energy from not only higher order harmonics, but also a DC component into the fundamental component.
Bibliography Batarseh, I., Resonant converter topologies with three and four energy storage elements, IEEE Transactions on PE, 9, 64, 1994. Batarseh, I., Liu, R., and Lee, C.Q., Stateplan analysis and design of parallel resonant converter with LCCtype commutation, in Proceedings of IEEESICE’88, Tokyo, 1988, p. 831. Chen, J. and Bonert, R., Load independent AC/DC power supply for higher frequencies with sinewave output, IEEE Transactions on IA, 19, 223, 1983. Kazimierczuk, M.K. and Cravens, R.C., Currentsource parallelresonant DC/AC inverter with transformer, IEEE Transactions on PE,, 11, 275, 1996. Kazimierczuk, M.K. and Czarkowski, D., Resonant Power Converters, John Wiley, New York, 1995.
© 2003 by CRC Press LLC
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Advanced DC/DC Converters
Liu, R., Batarseh, I., and Lee, C.Q., Comparison of performance characteristics between LLCtype and conversional parallel resonant converters, IEE Electronics Letters, 24, 1510, 1988. Luo, F.L. and Ye, H., Investigation of πCLL current source resonant inverter, in Proceedings of IEEEIPEMC’03, Xi’an China, 2003, p. 658. Matsuo, M., Suetsugu, T., Mori, S., and Sasase, I., Class DE currentsource parallel resonant inverter, IEEE Transactions on IE, 46, 242, 1999. Severns, R.P., Topologies for threeelement converters, IEEE Transactions on PE, 7, 89, 1992. Van Wyk, J.D. and Snyman, D.B., High frequency link systems for specialized power control applications, in Proceedings of IEEEIAS’82 Annual Meeting, 1982, p. 793.
© 2003 by CRC Press LLC
1956_C15.fm Page 631 Thursday, August 7, 2003 9:46 PM
15 Cascade Double ΓCL Current Source Resonant Inverter
15.1 Introduction This chapter introduces a fourelement current source resonant inverter (CSRI): a cascade double Γtype CL circuit CSRI. Its circuit diagram is shown in Figure 15.1. It consists of four energystorage elements, the double ΓCL: C1L1 and C2L2. The energy source is a DC voltage Vin chopped by two main switches S1 and S2 to construct a bipolar current source, ii = ± I i . The pump inductors L10 and L20 are equal to each other, and are large enough to keep the source current nearly constant during operation. The real load absorbs the delivered energy, its equivalent load should be proposed resistive, Req. The equivalent circuit diagram is shown in Figure 15.2.
15.2 Mathematic Analysis In order to concentrate the function analysis of this double cascade ΓCL CSRI, assume: 1. The inverter’s source is a constant current source determined by the pump circuits. 2. Two MOSFETs in the switching circuit are turnedon and turnedoff 180° out of phase with each other at same switching frequency and with a duty cycle of 50%. 3. Two switches are ideal components without onresistance, and negligible parasitic capacitance and zero switching time. 4. Two diodes are components having a zero forward voltage drop and forward resistance. 5. Four energystorage elements are passive, linear, timeinvariant, and do not have parasitic reactive components. 631 © 2003 by CRC Press LLC
1956_C15.fm Page 632 Thursday, August 7, 2003 9:46 PM
L10
V + in _
S1
+ VL1 _
+ VL2 _
L1
L2 +
+ C1
VC1 _
C2
VC2 _
+ Req
S2
VO _
L20
FIGURE 15.1 Cascade double ΓCL CSRI.
L1
L2 +
+Ii
ii
C1
C2
 Ii
Req
VO _
FIGURE 15.2 Equivalent circuit.
Based on these assumptions and the equivalent circuit the following analysis is derived.
15.2.1
Input Impedance
This CSRI is a fourthorder system. The mathematic analysis of operation and stability is more complex than three energystorage element current source resonant inverters. The input impedance is given by
Z(ω ) =
Req (1 − ω 2 L1C2 ) + jω(L1 + L2 − ω 2 L1L2 C2 ) 1 − ω 2 (L1C1 + L2 C1 + L2 C2 ) + ω 4 L1L2 C1C2 + jωR (C + C − ω 2 L C C ) 1 2 1 1 2 eq
(15.1)
or
Z(ω ) = where © 2003 by CRC Press LLC
Req (1 − ω 2 L1C2 ) + jω(L1 + L2 − ω 2 L1L2 C2 ) B(ω )
(15.2)
1956_C15.fm Page 633 Thursday, August 7, 2003 9:46 PM
B(ω ) = 1 − ω 2 (L1C1 + L2 C1 + L2 C2 ) + ω 4 L1L2 C1C2 + jωReq (C1 + C2 − ω 2 L1C1C2 )
15.2.2
(15.3)
Components, Voltages, and Currents
This CSRI has four resonant components C1, C2, L1 and L2, plus the output equivalent resistance Req. In order to compare with the parameters easily, all components voltages and currents are responded to the input fundamental current Ii. Voltage and current on capacitor C1 is 2 2 VC1 (ω ) Req (1 − ω L1C2 ) + jω(L1 + L2 − ω L1L2 C2 ) = I i (ω ) B(ω )
(15.4)
2 2 I C1 (ω ) Req (1 − ω L1C2 ) + jω(L1 + L2 − ω L1L2 C2 ) = I i (ω ) B(ω ) / jωC1
(15.5)
Voltage and current on inductor L1 is 2 2 VL1 (ω ) − Req ω L1C2 + jωL1 (1 − ω L2 C2 ) = I i (ω ) B(ω )
(15.6)
2 I L1 (ω ) (1 − ω L2 C2 ) + jReq ωC2 = I i (ω ) B(ω )
(15.7)
Voltage and current on capacitor C2 is VC 2 (ω ) Req + jωL2 = I i (ω ) B(ω )
(15.8)
2 I C 2 (ω ) −ω L2 C2 + jReq ωC2 = I i (ω ) B(ω )
(15.9)
Voltage and current on inductor L2 is VL 2 (ω ) jωL2 = I i (ω ) B(ω ) © 2003 by CRC Press LLC
(15.10)
1956_C15.fm Page 634 Thursday, August 7, 2003 9:46 PM
I L 2 (ω ) 1 = I i (ω ) B(ω )
(15.11)
The output voltage and current on the resistor Req: Req Vo (ω ) = I i (ω ) B(ω )
(15.12)
The current transfer gain is given by g (ω ) =
15.2.3
I o (ω ) 1 = I i (ω ) B(ω )
(15.13)
Simplified Impedance and Current Gain
Usually, the input impedance and output current gain are paid more attention rather than other transfer functions listed in the previous section. To simplify the operation, select: L1 = L2 = L;
Q=
C1 = C2 = C
ω 0L 1 = Req ω 0 CReq
ω0 =
β=
1 LC
ω ω0
Obtain B(β) = 1 − 3β 2 + β 4 + j
2 − β2 β Q
(15.14)
Therefore, Z=
(1 − β2 ) + jQ(2 − β2 ) Req = Z φ 2 − β2 1 − 3β2 + β 4 + j β Q
where Z=
(1 − β 2 )2 + Q 2 (2 − β 2 )2 2 − β2 2 (1 − 3β + β ) + β ( ) Q 2
© 2003 by CRC Press LLC
4 2
2
Req
(15.15)
1956_C15.fm Page 635 Thursday, August 7, 2003 9:46 PM
30 25
Q=5
Z/R
20 15 10 Q=2 5 Q=1 0
0
0.5
1
1.4141.5
2
Normalized switching frequency FIGURE 15.3 The curves of Z/Req vs. β referring to Q.
TABLE 15.1 Z/Req vs. β Referring to Various Q Q=1 2 5
and
β = 0.59
1
1.2
1.414
1.59
1.1994 4.1662 23.464
0.7071 1.7889 4.9029
0.5672 1.0955 2.7031
1.0000 1.0000 1.0000
2.0237 4.9137 17.463
φ = tan −1
2 − β2 (2 − β 2 )β Q − tan −1 2 1− β (1 − 3β 2 + β 4 )Q
The characteristics of input impedance Z/Req vs. relevant frequency β referring to various Q, is shown in Figure 15.3 and Table 15.1. The characteristics of phase angle φ vs. relevant frequency β referring to various Q, is shown in Figure 15.4 and Table 15.2. The current transfer gain becomes 1
g=
1 − 3β2 + β 4 + j
2 − β2 β Q
= g θ
(15.20)
where g =
1 2 − β2 2 (1 − 3β + β ) + β ( ) Q 2
© 2003 by CRC Press LLC
4 2
2
(15.21)
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636
Advanced DC/DC Converters 100
Phase angle of Z
Q=5 50
Q=2 Q=1
0
50
100
0
0.5
1
1.5
2
Normalized switching frequency
FIGURE 15.4 The curves of φ vs. β referring to Q.
TABLE 15.2 φ vs. β Referring to Various Q Q=1 2 5
β = 0.59
1
1.2
1.414
1.59
–29.3 –9.5 13.9
–45.0 –63.4 –78.7
–28.5 –56.8 –76.4
0.0 0.0 0.0
–48.3 –17.6 29.0
and θ = − tan −1
(2 − β 2 )β (1 − 3β 2 + β 4 )Q
The characteristics of current transfer gain g vs. relevant frequency β referring to various Q, is shown in Figure 15.5 and Table 15.3. The characteristics of the phase angle θ vs. relevant frequency β referring to various Q, is shown in Figure 15.6 and Table 15.4. For various β and Q, different current transfer gain is obtained. Actually, the maximum g can be found from d g= 0 dβ2 or 4β 6 + (
© 2003 by CRC Press LLC
3 8 4 − 18)β 4 + (22 − 2 )β 2 + ( 2 − 6) = 0 2 Q Q Q
(15.22)
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Cascade Double ΓCL Current Source Resonant Inverter
637
Current transfer gain g
6 Q=5
5 4 3
Q=2
2 Q=1 1 0
0
0.5 0.618
1
1.414 1.5 1.618
2
Normalized switching frequency
FIGURE 15.5 The curves of g vs. β referring to Q.
TABLE 15.3 g vs. β Referring to Various Q β = 0.59
1
1.2
1.414
1.59
1.0229 2.0270 4.7725
0.7071 0.8944 0.9806
0.7062 0.7747 0.7977
0.9994 0.9994 0.9994
1.1607 2.1641 3.9087
Q=1 2 5
Phase angle of g (deg.)
200 150 100 50 Q=5 0
Q=2
50 Q=1
100 150 200
0
0.5 0.618
1 1.414
1.51.618
2
Normalized switching frequency
FIGURE 15.6 The curves of θ vs. β referring to Q.
when Q=2
© 2003 by CRC Press LLC
4β 6 − 17.25β 4 + 20β 2 − 5 = 0
(15.23)
1956_C15.fm Page 638 Thursday, August 7, 2003 9:46 PM
TABLE 15.4 θ vs. β Referring to Various Q Q = 0.5 1 2
yields
β = 0.59
1
1.2
1.414
1.59
–87.7 –85.5 –81.0
–116.6 –135.0 –153.4
–132.8 –151.7 –164.9
–180.0 –180.0 –180.0
96.6 102.9 114.7
β1 = 0.59 β2 = 1.20
β3 = 1.59
Take β3 = 1.59 (the local maximum transfer gain is achieved at β1 = 0.59), and the corresponding g(β) is equal to 2.165. In practice, Equation (15.23) is dependent on the qualify factor Q. For various load conditions, the maximum transfer gain will be achieved at different operating frequencies. When Q >>1, we then have 2β 6 − 9β 4 + 11β 2 − 3 = 0
(15.24)
or (2β 2 − 3)(1 − 3β 2 + β 4 ) = 0 yields three positive real roots as β4 = 0.618 β5 = 1.618
β6 = 1.225
It should be noted that two peaks exist in the transfer gain curves with corresponding frequencies at β4 = 0.618 and β5 = 1.618, respectively. The current transfer gain drops from the peak to the vale at β6 = 1.225. Taking further investigation, it is found that at the frequencies corresponding to peak gain, the following equation can be obtained, 1 − 3β 2 + β 4 = 0
(15.25)
Thus, the current transfer gain at β4 and β5 is
g(β) =
© 2003 by CRC Press LLC
1
=Q
2
2 − β2 2 (1 − 3β 2 + β 4 )2 + β Q
β 4 ,β 5
(15.26)
1956_C15.fm Page 639 Thursday, August 7, 2003 9:46 PM
The relevant phase angle θ is θ 4 = –90° θ5 = 90° The results indicate that the current transfer gain is proportional to the quality factor Q. The larger the value of Q is, the higher the gain g(β). For instance, when Q = 1, 2 and 5 with β4 = 0.618 or β5 = 1.618, g(β) will have the same value. Note that although β4 and β5 are derived from the assumption of Q >>1, the Equation (15.26) is still valid for all the values of quality factors. Furthermore, when Q 1 we then have Z=
jQ R ≈ − jQReq −1 + j / Q eq
1 π π π ≈ −π≈− ϕ = − tan −1 −Q 2 2 2 and correspondingly © 2003 by CRC Press LLC
(15.29)
1956_C15.fm Page 640 Thursday, August 7, 2003 9:46 PM
g(β) =
1 = −1 −1 + j / Q
(15.30)
θ = −π The double ΓCL circuit is not only the resonant circuit, but the bandpass filter as well. All higher order harmonic components in the input current are effectively filtered by the double ΓCL circuit. The output current is nearly a pure sinusoidal waveform with the fundamental frequency ω = 2f. 15.2.4
Power Transfer Efficiency
The power transfer efficiency is a very important parameter and it is calculated here. From Figure 15.2, the input current is a bipolar value ii(ωt): I ii (ωt) = i − I i
2nπ ≤ ωt ≤ (2n + 1)π (2n + 1)π ≤ ωt ≤ 2(n + 1)π
with n = 0, 1, 2, 3, … ∞
(15.31)
where Ii = V1 (Z + jωL10 ) (L10 = L20) that varies with operating frequency. This is a square waveform pulsetrain. Applying fast Fourier transform (FFT), the spectrum form is
ii (ωt) =
4Ii π
∞
∑ n= 0
sin(2n + 1)ωt 2n + 1
(15.32)
The fundamental frequency component is i fund (ωt) =
4Ii sin ωt π
(15.33)
i0 (ωt) = g
4Ii sin ωt π
(15.34)
Output current is
The power transfer efficiency from input current source to AC output load is analyzed and calculated. Since the input current is a square waveform the total input power is Pin = I i 2 Z © 2003 by CRC Press LLC
(15.35)
1956_C15.fm Page 641 Thursday, August 7, 2003 9:46 PM
The output current is nearly a pure sinusoidal waveform, its rootmeansquare value is its peak value times 1/√2. Therefore the output power is PO = ( g
4Ii 2 I ) Req = 8( g i ) 2 Req π π 2
(15.36)
We can get the power transfer efficiency as
η=
PO = Pin
8
( I i  g)2 R eq 8 g2 R eq π2 = π 2 Z I i 2 Z
(15.37)
Considering Equation (15.15) and Equation (15.21), we obtain: η=
If If If If
β2 β2 β2 β2
= = = =
8 π2
1 (1 − β ) + Q β (2 − β ) 2 2
2
2
2 2
2 − β2 2 (1 − 3β + β ) + β ( ) Q 2
4 2
(15.38)
2
2 (β = 1.414) with any Q, η = 0.8106. 1 (β = 1) and Q = 1, η = 0.5732. 2.5 (β = 1.581) and Q = 1, η = 0.5771. 2.618 (β = 1.618) and Q = 1, η = 0.4263.
Therefore, the characteristics of efficiency η vs. relevant frequency β referring to various Q is obtained, and shown in Figure 15.7 and Table 15.5.
15.3 Simulation Result In order to verify analysis and calculation, using PSpice software simulation method to obtain a set of simulation waveforms as shown in Figure 15.8 to Figure 15.9 corresponding to Q = 2 and β = 1, 1.414, and 1.59. The parameter values are set below: I = 1 A, V1 = 30 V, L10 = L20 = 20 mH, Req = 10 Ω, C1 = C2 = C = 0.22 µF, and L1 = L2 = L = 100 µH. Therefore, ω0 = 213 krad/s, f0 = 33.93 kHz, and Q = 2. The particular frequencies for the figures are f = 33.9 kHz, 48.0 kHz and 54.0 kHz. In order to pick the input current a small resistance R0 = 0.001 Ω is employed. The load in the simulation circuit is R rather than Req. © 2003 by CRC Press LLC
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0.9 0.8 0.7 0.6 Q=1
0.5
η
Q=0.5 0.4 Q=2
0.3 0.2
Q=0.2 Q=5
0.1 0 0.5
1
1.5
2 log β
2.5
3
3.5
FIGURE 15.7 Curves of η vs. β referring to Q.
TABLE 15.5 η vs. β Referring to Various Q Q = 0.2 0.5 1 2 5
β = 0.618
0.8
1
1.414
1.581
1.618
2
3
4
5
0.2496 0.5098 0.6895 0.7745 0.8045
0.3527 0.5559 0.5885 0.4927 0.2680
0.7948 0.7250 0.5732 0.3625 0.1590
0.8106 0.8106 0.8106 0.8106 0.8106
0.1359 0.3268 0.5771 0.7955 0.6473
0.0995 0.2394 0.4263 0.6304 0.7715
0.0127 0.0238 0.0253 0.0176 0.0079
0.0008 0.0009 0.0006 0.0003 0.0001
0.0001 0.0001 0.0001 0.0000 0.0000
0.0000 0.0000 0.0000 0.0000 0.0000
All figures have two parts a and b. Figure a shows the input and output current waveforms, and b shows the corresponding FFT spectrum. The first channel of Figure 15.11a to Figure 15.13a is the input current flowing through resistance R0, which corresponds to the input current ii(ωt). It is a square waveform pulse train with the pulsewidth ωt = π. The second channel of Figure 15.11a to Figure 15.13a is the output current flowing through resistance R. From Figure 15.11b to Figure 13b, the first channel of each figure is the corresponding input current FFT spectrum. The second channel of each figure is the corresponding output current FFT spectrum. From the spectrums, it can be clearly seen that there is only monofrequency existing in output currents. All output current waveforms are very pure sinusoidal function. © 2003 by CRC Press LLC
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1.0A
0A SEL>> 1.0A I(Ii) 2.0A 0A 2.0A 1.94ms I(R)
1.96ms
1.98ms
2.00ms
Time (a) Input and output current waveforms 2.0A
(34K,1.272) (170K,0.247)
1.0A
(102K,0.420)
(306K,0.128)
(238K,0.171)
0A I(Ii) 2.0A (34K,1.145) 1.0A SEL>> 0A 0Hz
100KHz
200KHz
300KHz
I(R) Frequency (b) The corresponding FFT spectrum of input and output current waveforms
FIGURE 15.8 Input and output current waveforms at f = 33.9 kHz.
15.3.1
β = 1, f = 33.9 kHz, T = 29.5 µs
The waveforms and corresponding FFT spectrums are shown in Figure 15.8. The THD = 0 and current transfer gain is g=
15.3.2
I ( R) 1.145 = = 0.9002  I ( R0)1 f = 33.9 kHz 1.272
β = 1.4142, f = 48.0 kHz, T = 20.83 µs
The waveforms and corresponding FFT spectrums are shown in Figure 15.9. The THD = 0 and current transfer gain is © 2003 by CRC Press LLC
1956_C15.fm Page 644 Thursday, August 7, 2003 9:46 PM
1.0A
0A
1.0A I(Ii) 2.0A 0A SEL>> 2.0A 1.96ms I(R)
1.97ms
1.98ms
1.99ms
2.00ms
Time
(a) Input and output current waveforms 2.0A (48K,1.271) (240K,0.245) 1.0A
(144K,0.419)
(336K,0.168)
0A I(Ii) 2.0A (48K,1.271) 1.0A SEL>> 0A 0Hz
100KHz
200KHz
300KHz
I(R) Frequency
(b) The corresponding FFT spectrum of input and output current waveforms FIGURE 15.9 Input and output current waveforms at f = 48 kHz.
g=
15.3.3
1.271 I ( R) f = 48 kHz = = 1.00 1.271 I ( R 0 )1
β = 1.59, f = 54 kHz, T = 18.52 µs
The waveforms and corresponding FFT spectrums are shown in Figure 15.10. The THD = 0 and current transfer gain is g= © 2003 by CRC Press LLC
I ( R) 2.752 = 2.162 f = 54 kHz = I ( R 0 )1 1.273
1956_C15.fm Page 645 Thursday, August 7, 2003 9:46 PM
1.0A
0A SEL>> 1.0A I(Ii) 4.0A 0A 4.0A 1.96ms
1.97ms
I(R)
1.98ms
1.99ms
2.00ms
Time
(a) Input and output current waveforms 2.0A (54K,1.273) 1.0A
(162K,0.424)
(270K,0.254)
0A I(Ii) 4.0A (54K,2.752) 2.0A SEL>> 0A 0Hz
100KHz
200KHz
300KHz
I(R) Frequency
(b) The corresponding FFT spectrum of input and output current waveforms FIGURE 15.10 Input and output current waveforms at f = 54 kHz.
15.4 Experimental Result In order to verify our analysis and calculation, a test rig with the same components was constructed: I = 1 A, V1 = 30 V, L10 = L20 = 20 mH, Req = 10 Ω, C1 = C2 = C = 0.22 µF, and L1 = L2 = L = 100 µH. Therefore, ω0 = 213 krad/s, f0 = 33.93 kHz, and Q = 2. The MOSFET device is IRF640 (Rds = 0.15 ohm, Cds = 140 pF). Since the junction capacitance of Cds © 2003 by CRC Press LLC
1956_C15.fm Page 646 Thursday, August 7, 2003 9:46 PM
FIGURE 15.11 Testing waveform of the output voltage at β = 1.
FIGURE 15.12 Testing waveform of the output voltage at β = 1.414.
FIGURE 15.13 Testing waveform of the output voltage at β = 1.59. © 2003 by CRC Press LLC
1956_C15.fm Page 647 Thursday, August 7, 2003 9:46 PM
is much smaller than the resonance capacitance C = 0.22 µF (C/Cds = 1429), it does not affect the experimental results. The output current waveform is a perfect sine function. A set of tested output voltage waveforms that correspond to the output current with β = 1, 1.4142, and 1.59 is shown in Figure 15.11 to Figure 15.13. The particular applied frequencies for the figures are f = 33.9 kHz, 48.0 kHz, and 54.0 kHz, and peaktopeak voltage Vpp = 28.1 V, 40.3 V, 71.9 V, and 65.5 V, which are very close to the values in Figure 15.8 to Figure 15.10.
15.5 Discussion 15.5.1
Function of the Double ΓCL Circuit
Single ΓCL filter is a wellknown circuit. As a ΠCLC filter, it is a typical lowpass filter. All harmonics with frequency ω > ω0 will be blocked. Cascade double ΓCL filter circuit has thoroughly different characteristics from that of lowpass filters. It allows the signal with higher frequency ω > ω0 (it means β > 1 in Section 15.2) passing it and enlarging the energy. 15.5.2
Applying Frequency to this Double ΓCL CSRI
From analysis and verifications it can be found the fact that the effective applying frequency to this double ΓCL current source resonant inverter is (0.6 to 2.0) f0. Outside this region both current transfer gain and efficiency is falling fast.
15.5.3
Explanation of g > 1
We recognized the fact that current transfer gain is greater than unity from mathematical analysis, and simulation and experimental results. The reason to enlarge the fundamental current is that the resonant circuit transfers the energy of other higher order harmonics to the fundamental component. Therefore the gain of the fundamental current can be greater than unity.
Bibliography Bhat, A.K.S., Analysis and design of a seriesparallel resonant converter, IEEE Transactions on Power Electronics, 8, 1, 1993. Bhat, A.K.S. and Swamy, M.M., Analysis and design of a highfrequency parallel resonant converter operating above resonance, in Proceedings of IEEE Applied Power Electronics Conference, 1988, p. 182. © 2003 by CRC Press LLC
1956_C15.fm Page 648 Thursday, August 7, 2003 9:46 PM
Forsyth, A.J. and Ho, Y.K. E., Dynamic characteristics and closedloop performance of the seriesparallel resonant converter, IEE ProceedingsElectric Power Applications, 143, 345, 1996. Ho, W.C. and Pong, M.H., Design and analysis of discontinuous mode series resonant converter, in Proceedings of the IEEE International Conference on Industrial Technology, 1994, p. 486. Hua, G., Yang, E.X., Jiang, Y., and Lee, F.C.Y., Novel zerovoltagetransition PWM converters, IEEE Transaction on Power Electronics, 9, 213, 1994. Keown, J., OrCAD PSpice and Circuit Analysis, 4th ed., New Jersey, Prentice Hall, 2001. Liu, K.H., Oruganti, R., and Lee, F.C., Resonant switchestopologies and characteristics, in Proceedings of IEEE Power Electronics Specialists Conference, 1985, p. 106. Luo F.L. and Wan, J.Z., Bipolar current source applying to cascade double gammaCL CSRI, in Proceedings of UROP Congress’2003, Singapore, 2003, p. 328. Luo, F.L. and Ye, H., Analysis of a double ΓCL current source resonant inverter, in Proceedings of IEEE IAS Annual Meeting IAS2001, Chicago, U.S., 2001, p. 289. Luo, F.L. and Ye, H., Investigation and verification of a double ΓCL current source resonant inverter, Proceedings of IEE on Electric Power Applications, 149, 369, 2002. Luo, F.L. and Zhu, J.H., Verification of a double ΓCL current source resonant inverter, in Proceedings of IEEIPEC’2003, Singapore, 2003, p. 386. Oruganti, R. and Lee, F.C., Stateplane analysis of parallel resonant converter, in Proceedings of IEEE Power Electronics Specialists Conference, 1985, p. 56. Vorpérian, V., Analysis of Resonant Converter, Ph.D dissertation, California Institute of Technology, Pasadena, May 1984.
© 2003 by CRC Press LLC
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16 Cascade Reverse Double ΓLC Resonant Power Converter
A fourelement power resonant converter — cascade reverse double ΓLC resonant power converter (RPC) — will be discussed in this chapter. Since the first element is an inductor, the power supply should be a bipolar voltage source. Do remember that the first element of CSRIs in previous chapters is a capacitor, therefore, a bipolar current source was employed. The major work is concentrated on the analysis of steadystate operation, dynamic behavior, and control specialties of the novel resonant converter. The simulation and experimental results show that this resonant converter has many distinct advantages over the existing two or three element resonant converters and overcomes their drawbacks.
16.1 Introduction Generally, a switchedmode power converter is often required to meet all or most of the following specifications: • • • • • •
High switching frequency High power density for reduction of size and weight High conversion efficiency Low total harmonic distortion (THD) Controlled power factor if the source is an AC voltage Low electromagnetic interference (EMI)
A review of the commonly used pulsewidthmodulating (PWM) converter and new generated resonant converter is presented in order to fully understand the two major branches of the high frequency switching converter. Although PWM technique is widely used in power electronic applications, it encounters serious problems when the switching converter operates at
© 2003 by CRC Press LLC
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+V
S1
D 1 S1 L1
L2
Lf D3
–V
S2
D2 S 2
C1
D4
C2
Cf D5
R
vo
D6
FIGURE 16.1 Circuit diagram of cascade reverse double ΓLC RPC.
high frequencies. Due to the hardswitching transitions caused by PWM technique, switching losses possess large proportion in total power dissipations. In other words, when the switch is turned on, the current through it rises very fast, while the voltage across it cannot descend immediately due to the parasitic output capacitance. Similarly, when the switch is turned off, the voltage across it rises rapidly while the current through it cannot drop at once because of the recombination of carriers. In general, a resonant power converter is defined as a converter in which one or more switching waveforms are resonant waveforms. It is reasonable to say that a resonant power converter usually contains a resonant circuit. In fact, there are many topologies of the resonant power converter, which are many more than ZCS and ZVS QRCs in Chapter 11.
16.2 SteadyState Analysis of Cascade Reverse Double Γ LC RPC In this chapter, a cascade reverse double ΓLC RPC is introduced. Under some assumptions and simplifications, the steadystate AC analysis is undertaken to study the two most interesting topics: voltage transfer gain and the input impedance.
16.2.1
Topology and Circuit Description
The circuit diagram of a halfbridge cascade reverse double ΓLC resonant power converter is shown in Figure 16.1. Like other resonant converters, this topology consists of a bipolar voltage source, resonant network — the cascade reverse double ΓLC, the rectifierplusfilter, and load (such as a resistive load R). The power MOSFETs S1 and S2 and their antiparalleled diodes © 2003 by CRC Press LLC
1956_C16.fm Page 651 Friday, August 8, 2003 12:33 AM
D1 and D2 act together as a bipolar voltage source. To operate this circuit, S1 is turned on and off 180° out of phase with respect to the turnoff and on of S2 at same frequency ω = 2πf. After the switching circuit, the input voltage can be considered as a bipolar squarewave voltage alternating in value between +V and –V, which is then input to the resonant circuit section. L1, L2 and C1, C2 represent the resonant inductors and capacitors, respectively. The output DC voltage is obtained by rectifying the voltage across the second resonant capacitor C2. Lf and Cf comprise a lowpass filter to smooth out the output voltage and current, and R denotes either an actual or an equivalent load resistance. The following assumptions should be made: 1. All the switches and diodes used in the converter are ideal components 2. All the inductors and capacitors are passive, linear and timeinvariant 3. The output inductor is large enough to assume that the load current does not vary significantly during switching period 4. The converter operates above resonance
16.2.2
Classical Analysis on AC Side
This analysis is available on the AC side before the rectifier bridge. 16.2.2.1 Basic Operating Principles For the cascade reverse double ΓLC RPC considered here, the halfbridge converter applies a square wave of voltage to a resonant network. Since the resonant network has the effect of filtering the higherorder harmonic voltages, a sine wave of current will appear at the input to the resonant circuit (this is true over most of the load range of interest). This fact allows classical AC analysis techniques to be used. The analysis proceeds as follows. The fundamental component of the square wave input voltage is applied to the resonant network, and the resulting sine waves of current and voltage in the resonant circuit are computed using classical AC analysis. For a rectifier with an inductor output filter, the sine wave voltage at the input to the rectifier is rectified, and the average value is taken to arrive at the resulting DC output voltage. For a capacitive output filter, a square wave of voltage appears at the input to the rectifier while a sine wave of current is injected into the rectifier. For this case the fundamental component of the square wave voltage is used in the AC analysis. 16.2.2.2 Equivalent Load Resistance It is necessary that the rectifier with its filter should be expressed as an equivalent load resistance before the analysis is carried out, which illustrates © 2003 by CRC Press LLC
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652
Advanced DC/DC Converters ILf
vp
ILf
Lf
iac(rms) vac(rms)
Cf
R
VO
FIGURE 16.2 Equivalent load resistance Req.
the derivation of the equivalent resistance to use in loading the resonant circuit. The resonant converter uses an inductor output filter and drives the rectifier with an equivalent voltage source, i.e., a lowimpedance source provided by the resonant capacitor. A square wave of current is drawn by the rectifier, and its fundamental component must be used in arriving at an equivalent AC resistance. For this case, the rootmeansquare value of the voltage and current before the rectifier are given as: v ac (rms) =
iac (rms) =
Req =
π 2 2
Vo
2 2 I π Lf
v ac (rms) π 2 Vo π 2 = = R 8 I Lf 8 iac (rms)
The equivalent resistance Req is shown in Figure 16.2. 16.2.2.3 Equivalent AC Circuit and Transfer Functions The equivalent AC circuit diagram of the cascade reverse double ΓLC RPC is shown in Figure 16.3. Note that all the parameters and variables are transferred to the sdomain. Using Laplace operator s = jω s , it is a simple matter to write down the voltage transfer gain of the cascade reverse double ΓLC RPC: V ( s) g( s) = o = Req Vi ( s) or © 2003 by CRC Press LLC
[s 4 L1L2 Req C1C2 + s 3 L1L2 C1 + s 2 (L1Req C1 + L1Req C2 + L2 Req C2 ) + s(L1 + L2 ) + Req ]
1956_C16.fm Page 653 Friday, August 8, 2003 12:33 AM
Cascade Reverse Double ΓLC Resonant Power Converter L1
653
L2
+V Req 0
Vi
C1
C2
vC2
–V
FIGURE 16.3 Equivalent circuit of the cascade reverse double ΓLC RPC.
g( s) = Req / B( s)
(16.1)
where B( s) = s 4 L1L2 Req C1C2 + s 3 L1L2 C1 + s 2 (L1Req C1 + L1Req C2 + L2 Req C2 ) + s(L1 + L2 ) + Req
(16.2)
The voltage and current stresses on different reactive resonant components are obtained with respect to the input fundamental voltage Vi. Voltage and current on inductor L1: 3 2 VL1 ( s) sL1[s L2 Req C1C2 + s L2 C1 + sReq (C1 + C2 ) + 1] = Vi ( s) B( s)
(16.3)
3 2 I L1 ( s) s L2 Req C1C2 + s L2 C1 + sReq (C1 + C2 ) + 1 = Vi ( s) B( s)
(16.4)
Voltage and current on capacitor C1: 2 VC1 ( s) s L2 Req C2 + sL2 + Req = Vi ( s) B( s)
(16.5)
2 I C1 ( s) sC1 ( s L2 Req C2 + sL2 + Req ) = Vi ( s) B( s)
(16.6)
Voltage and current on inductor L2: VL 2 ( s) sL2 ( sReq C2 + 1) = Vi ( s) B( s) © 2003 by CRC Press LLC
(16.7)
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654
Advanced DC/DC Converters I L 2 ( s) sReq C2 + 1 = Vi ( s) B( s)
(16.8)
Voltage and current on capacitor C2: Req VC 2 ( s) = Vi ( s) sC2 ⋅ B( s)
(16.9)
Req I C 2 ( s) = Vi ( s) B( s)C2
(16.10)
The input impedance is given by Zin =
B( s) s L2 Req C1C2 + s L2 C1 + sReq (C1 + C2 ) + 1 3
2
(16.11)
16.2.2.4 Analysis of Voltage Transfer Gain and the Input Impedance In general, the voltage gain and the input impedance have more attractions to the designer rather than other transfer functions listed above. To simplify the mathematical analysis, the resonant components are chosen as follows: L1 = L2 = L
C1 = C2 = C
ω0 =
1 LC
The quality factor Q is defined as Q=
ω 0L Z 1 = = 0 Req ω 0 CReq Req
(16.12)
where the characteristic impedance Z0 is Z0 =
L C
(16.13)
The relative switching frequency is defined as β=
ω ω0
(16.14)
where ω is the switching frequency and ω0 is the natural resonance frequency: © 2003 by CRC Press LLC
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Cascade Reverse Double ΓLC Resonant Power Converter
ω0 =
1 LC
655
(16.15)
Under the abovesimplified conditions, the voltage gain g(s) given in previous section can be rewritten as B(β) = Req [1 − 3β 2 + β 4 + j(2 − β 2 )βQ] g(β) =
1 = g(β) ∠ θ (1 − 3β + β ) + j(2 − β2 )βQ 2
4
(16.17)
The determinant and phase of g(β) are given by: g(β) =
1 (1 − 3β + β ) + (2 − β 2 )2 β 2Q 2 2
4 2
and θ = − tan −1
(2 − β 2 )βQ 1 − 3β 2 + β 4
(16.18)
Analogiously, the input impedance Zin(s) can also be simplified as: Zin (β) =
Req [1 − 3β2 + β 4 + j(2 − β2 )βQ] 1 − β2 + j(2 − β2 )β / Q
= Zin (β) ∠ φ
(16.19)
where
Zin (β) =
Req (1 − 3β 2 + β 4 )2 + (2 − β 2 )2 β 2Q 2 (1 − β 2 )2 + (2 − β 2 )2 β 2 / Q 2
and φ = tan −1
(2 − β 2 )βQ (2 − β 2 )β − tan −1 2 4 1 − 3β + β (1 − β 2 )Q
(16.20)
The characteristics of the voltage gain g(β) and phase angle θ vs. relative frequency β referring to various Q is shown in Figure 16.4 and Figure 16.5, respectively. Note that for lower Q value, the voltage gain g(β) is higher than unity at some certain switching frequencies. It means the output voltage © 2003 by CRC Press LLC
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656
Advanced DC/DC Converters 2.5
Voltage gain Vo/Vin
2.0
1.5 Q = 0.5 1.0
Q=1
Q=2
0.5
Q=4 Q = 10 0.0 0.0
0.5
1.0
1.5
2.0
2.5
Normalized switching frequency
FIGURE 16.4 Voltage gain g(β) vs. β referring to Q.
Phase angle of voltage gain (deg)
200 150 100
Q = 10 4
50 0 –50 –100 2
–150 –200 0.0
Q=1 0.5
1.0
1.5
2.0
2.5
Normalized switching frequency
FIGURE 16.5 Phase angle θ vs. β referring to Q.
can be larger than the fundamental harmonic of the input voltage. The result could be explained thusly: the resonant network consisting of inductors and capacitors has the function of filtering the higher order harmonic components in the input quasisquare voltage. The energy of higher order harmonics is then transferred to the fundamental component thus enlarging the output voltage. This explanation is reasonable when fast Fourier transform (FFT) is applied to the comparison to waveforms of the input voltage and the second capacitor voltage respectively. The resonant circuit in cascade reverse double ΓLC © 2003 by CRC Press LLC
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Cascade Reverse Double ΓLC Resonant Power Converter
657
RPC allows the signal with higher frequency (β > 1) passing it and enlarging the energy. In other words, the bandwidth of this novel converter is wider, as it provides more options for the designer to choose the appropriate operating frequency in different applications. The maximum voltage gain g(β) can be obtained from d g(β) = 0 dβ 2 or
4β 6 + (3Q 2 − 18)β 4 + (22 − 8Q 2 )β 2 + 4Q 2 − 6 = 0
when
Q=1
4β 6 − 15β 4 + 14β 2 − 2 = 0
(16.21) (16.22)
β1 = 0.42 β2 = 1.11 β3 = 1.53
yields
It means the local maximum or minimum values on the gain curve are achieved at these roots, respectively. Generally, the voltage gain decreases with the increase of the Q value. For instance, when Q = 1, 2, and 4 with β2 = 2, the gain g(β) = 1, 0.5, and 0.25, respectively. At certain switching frequencies, the smaller the value of Q is, the higher the gain. Specifically, when Q 1, Equation (16.21) can be rearranged, © 2003 by CRC Press LLC
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658
Advanced DC/DC Converters 120
Normalized input impedence
Q = 10 100
80
60
40
Q=6
20
Q=4 Q=2
0 0.0
0.5
1.0 Q = 1
1.5
2.0
2.5
Normalized switching frequency
FIGURE 16.6 Input impedance Zin(β) vs. β referring to Q.
3β 4 − 8β 2 + 4 = 0
(16.25)
It gives other two positive real roots as β3 = 0.816
β4 = 1.414
The former represents the switching frequency at which the local minimum gain is achieved, while at the latter the maximum voltage gain can be obtained. From Equation (16.24), it should be noted that when β = 1.414 (β2 = 2), the voltage gain g(β) constantly keeps unity with any value of Q, as shown in Figure 16.4. The absolute value of the input impedance Zin(β) and phase angle φ vs. β referring to various Q is shown in Figure 16.6 and Figure 16.7, respectively. The input impedance has its maximum value when the switching frequency is equal to natural resonant frequency (i.e., β = 1), and its minimum value when the β = 1.414. The phase angle φ keeps zero when β = 1.414, with any Q value, which means the resonant converter can be regarded as a pure resistive load.
16.2.3
Simulation and Experimental Results
Some simulation and experimental results shown in this section are helpful to understand the design and analysis. The chosen technical data are good examples to implement a particular RPC for reader’s reference. © 2003 by CRC Press LLC
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Cascade Reverse Double ΓLC Resonant Power Converter
659
Phase angle of input impedence (deg)
100 80 60 40
Q=1
20 0
Q=2
–20 Q=4 –40 Q=6 –60
Q = 10
–80 0.0
0.5
1.0
1.5
2.0
2.5
Normalized switching frequency
FIGURE 16.7 Phase angle φ vs. β referring to Q.
40 Vi VC2
30 Voltage(V)
20 10 0 –10 –20 –30 –40 9.93
9.94
9.95 Time(s)
9.96
9.97
9.98 10–3
FIGURE 16.8 Simulation results at frequency f = 50 KHz.
16.2.3.1 Simulation Studies In order to verify the mathematical analyses, a fourelement cascade reverse double ΓLC RPC is simulated using PSpice. The parameters used are Vi = ±15 V , L1 = L2 = 100 µH, C1 = C2 = 0.22 µF, and R = 22 Ω. The natural resonant frequency is f0 = 1 2 π LC = 34 kHz. The applying frequency is f = 50 KHz, corresponding to the β = 1.42. The simulation results are shown in Figure 16.8. The input signal Vi is a square waveform and the voltage across C2 is a very smooth sinusoidal waveform.
(
© 2003 by CRC Press LLC
)
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FIGURE 16.9 Experimental waveforms (f = 50.38 KHz).
16.2.3.2 Experimental Results To verify the simulation results of the proposed cascade double ΓLC RPC, a test rig was constructed with the same conditions: Vi = ±15 V , L1 = L2 = 100 µH, C1 = C2 = 0.22 µF and R = 22 Ω. The natural resonant frequency is f0 = 34 kHz. For high frequency operation, the main power switch selected is IRF640 with its inner parasitic diode used as the antiparalleled diode. A highspeed integrated chip IR2104 is utilized to drive the halfbridge circuit. The switching frequency is chosen to be 50.38 KHz, corresponding to the β = 1.42. The experimental results are shown in Figure 16.9. The input signal Vi is a square waveform and the voltage across C2 is a very smooth sinusoidal waveform. Select the switching frequency to be 42.19 KHz, corresponding to the β = 1.24. The experimental results are shown in Figure 16.10. The input signal Vi is a square waveform and the voltage across C2 is also a smooth sinusoidal waveform.
16.3 Resonance Operation and Modeling From the circuit diagram in Figure 16.1, the steadystate operation of the circuit is characterized by four operating modes within one switching period, when the resonant converter operates under continuous conduction mode (CCM). The equivalent circuits corresponding to each operating mode are depicted in Figure 16.11. Note that for a large output filter inductor, the bridge rectifier and the load can be represented as an alternating current © 2003 by CRC Press LLC
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661
FIGURE 16.10 Experimental waveforms (f = 42.19 KHz).
L1
L1
L2
L2
Io Vi= +V
C1
C2
vC2
Io C1
Vi= +V
L1
L2
L2
Io Vi= –V
C1
C2
(c) Mode 3
vC2
(b) Mode 2
(a) Mode 1 L1
C2
vC2
Io Vi= –V
C1
C2
vC2
(d) Mode 4
FIGURE 16.11 Different operating resonance modes.
sink with constant amplitude I0, synchronous with the polarity of the second resonant capacitor voltage vC2. 16.3.1
Operating Principle, Operating Modes and Equivalent Circuits
The operating modes of cascade reverse double ΓLC RPC are very difficult to distinguish by analytic calculations, even under CCM conditions. However, the state of the converter should not exceed four modes when it operates above resonant frequency. The sequence among different modes is dependent on the phase angle to the voltage gain VC2(s)/Vi(s). In other words, when this angle is between 0° and +180°, the voltage across the second © 2003 by CRC Press LLC
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vC2
2 +V
t1
t0
0
t2
t3
t4
t
Vi –V Mode 1
Mode 2
Mode 4
Mode 3
FIGURE 16.12 Voltage waveforms when vC2 leads Vi.
Mag. TS 2
vC2
+V
t0
0
t1
t2
t3
t4
t
Vi –V Mode 1
Mode 2
Mode 4
Mode 3
FIGURE 16.13 Voltage waveforms when vC2 lags behind Vi.
capacitor vC2 leads the input quasiwave voltage Vi in Figure 16.12, thus the sequence from mode 1 to mode 4 should be: • Mode 1 (t0 < • Mode 2 (t1 < • Mode 3 (t2 < • Mode 4 (t3
<
< < >
0 0 0 0
(Figure 16.11a) (Figure 16.11b) (Figure 16.11c) (Figure 16.11d)
Similarly, when the angle is between –180° and 0°, vC2 will lag behind the input voltage Vi in Figure 16.13, causing the sequence to be changed to: • Mode 2 (t0 < • Mode 1 (t1 < • Mode 4 (t2 < • Mode 3 (t3 < © 2003 by CRC Press LLC
t t t t
< < <
> <
>
0 and vc2 > 0, it can be obtained 0 0 1 C1 A1 = 0 0 0 © 2003 by CRC Press LLC
0 0 − 1 C2 1 C2 0 0
−1 L1 1 L2 0 0 0 0
0 − 1 L2 0 0 1 Lf 0
0 0 0 − 1 C2 0 1 Cf
0 0 0 0 − 1 Lf − 1 RC f
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and
0
0
0
0]
T
0
x = (iL1 , iL 2 , vC1 , vC 2 , iLf , vCf )T
where
For mode 2, Vi > 0, vC2 < 0, the structure of the topology is changed due to the alteration of the polarity of the second capacitor voltage, giving: 0 0 1 C1 A2 = 0 0 0
0 0 − 1 C2 1 C2 0 0
−1 L1 1 L2 0 0 0 0
0 − 1 L2
0 0 0 1 C2
0 0 −1 L f
0 1 Cf
0
0 0 0 0 − 1 Lf − 1 ( RC f )
B2 = B1
and
For mode 3, Vi < 0, vC2 < 0, because only the input source is changed, the topology of the system remains invariant, thus the state coefficient matrix A3 is identical with A2, that is, A3 = A2
and
B3 = [−V L1
0
0
0
0
0]
T
Similarly, when operating the above resonance, for mode 4, Vi < 0, vC2 > 0, yielding: A4 = A1
and
B4 = B3
By employing the above coefficient matrices and vectors with the initial conditions, the values of all state variables in different operating modes can be obtained following Equation (16.39). Thus, the dynamic operating behavior of the resonant converter can be described by these state variables as well.
16.4 SmallSignal Modeling of Cascade Reverse Double Γ LC RPC In the previous section, statespace averaging technique has been applied to investigate the dynamic behavior and successfully simulated the waveforms © 2003 by CRC Press LLC
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Power Stage SmallSignal Model
vˆ
667
vˆ O
R
fˆsN
FIGURE 16.14 Smallsignal perturbations in input voltage and switching frequency.
ˆi1L
ˆiL2
L1
ˆiLf
L2
ˆi O
Lf
a +V + vˆ  vab
C1
+ vˆ 1C
C2
–
–V + vˆ 
+ vˆ 2C –
rc + Cf
Vˆ cf –
+ vˆ O – R
b
FIGURE 16.15 Equivalent circuit of cascade reverse double ΓLC RPC.
at different time intervals, however, the numerical results cannot reveal the relations of various control specialties, e.g., frequency response, closedloop control system stability, etc. In order to study these characteristics more deeply, a number of mathematical methods were presented among them the smallsignal modeling is implemented.
16.4.1
SmallSignal Modeling Analysis
16.4.1.1 Model Diagram The block diagram of the smallsignal model is depicted in Figure 16.14, where vˆ and fˆsN represent smallsignal perturbation of the line voltage and the frequency control signal. The output variable is the perturbed output voltage, vˆ o . With the model, it is easy to obtain the commonly used smallsignal transfer functions, such as controltooutput transfer function, linetooutput transfer function, input impedance, and output impedance. 16.4.1.2 Nonlinear State Equation The equivalent circuit of the resonant converter is shown in Figure 16.15. As seen, the halfbridge circuit employing two diodes, applies a squarewave voltage, vab, to the resonant network. Suppose the converter operates above resonance, the state equations of the resonant converter can be obtained, where the nonlinear terms are in bold face: © 2003 by CRC Press LLC
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L1
diL1 + vC1 = vab dt
C1
dvC1 + iL 2 = iL1 dt
L2
diL 2 + vC 2 = vC1 dt
dv C2 C 2 + sgn(vC 2 )iLf = iL 2 dt Lf Cf
diLf dt dvCf dt
(16.41)
+ (iLf − io )rc + vCf = vC 2 = iLf − io
The output variable is the output voltage, vo, which gives: vo = (iLf − io )rc + vCf
(16.42)
In this circuit, the output voltage is regulated either by the input line voltage, v, or by the applying switching frequency, ω. Thus, the operating point P can be expressed as the function of these variables P = {v, R, ω}. 16.4.1.3 Harmonic Approximation Under the assumption that both the voltage and current inside the resonant network are quasisinusoidal, the socalled fundamental approximation method is applied to the derivation of the smallsignal models. In other words, the variables in the resonant network are assumed as: iL1 = i1s (t) sin ωt + i1c (t) cos ωt iL 2 = i2 s (t) sin ωt + i2 c (t) cos ωt
(16.43)
vC1 = v1s (t) sin ωt + v1c (t) cos ωt vC 2 = v2 s (t) sin ωt + v2 c (t) cos ωt Note that the envelope terms {i1s, i1c, i2s, i2c, v1s, v1c, v2s, v2c} are slowly time varying, thus the dynamic behavior of these terms can be investigated. The derivatives of iL1, iL2, vC1 and vC2 are found to be: © 2003 by CRC Press LLC
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669
di di diL1 = [ 1s − ωi1c ]sin ωt + [ 1c + ωi1s ]cos ωt dt dt dt di di diL 2 = [ 2 s − ωi2 c ]sin ωt + [ 2 c + ωi2 s ]cos ωt dt dt dt dvC1 dv dv = [ 1s − ωv1c ]sin ωt + [ 1c + ωv1s ]cos ωt dt dt dt
(16.44)
dvC 2 dv dv = [ 2 s − ωv2 c ]sin ωt + [ 2 c + ωv2 s ]cos ωt dt dt dt 16.4.1.4 Extended Describing Function By employing the extended describing function modeling technique stated in the literature, the nonlinear terms in Equation (16.41) can be approximated either by the fundamental harmonic terms or by the DC terms, to yield: vab (t ) ≈ f1(v)sin ω st sgn(v2 )iLf ≈ f2 (v2 s , v2 c , iLf )sin ω st + f3 (v2 s , v2 c , iLf )cos ω st
(16.45)
vC 2 ≈ f4 (v2 s , v2 c ) These functions are called extended describing functions (EDFs). They are dependent on the operating conditions and the harmonic coefficients of the state variables. The EDF terms can be calculated by making Fourier expansions of the nonlinear terms, to give: f1 (v) =
4 v π
f2 (v2 s , v2 c , iLf ) =
4 v2 s i π Ap Lf
4 v2 c f3 (v2 s , v2 c , iLf ) = i π Ap Lf f4 (v2 s , v2 c ) =
2 A π p
where Ap = v22s + v22c
© 2003 by CRC Press LLC
(16.46)
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is the peak voltage of the second capacitor voltage vC2. 16.4.1.5 Harmonic Balance Substituting Equation (16.43) to Equation (16.46) into Equation (16.41), the nonlinear largesignal model of cascade reverse double ΓLC RPC is obtained as follows: di1s
L1 (
dt di1c
L1 (
C1 (
− ω s v1c ) = i1s − i2 s
dt dv1c
+ ω s v1s ) = i1c − i2 c
dt
− ω s i2 c ) = v1s − v2 s
dt di2 c
L2 (
+ ω s i2 s ) = v1c − v2 c
dt
C2 ( C2 (
Cf
dv1s
di2 s
L2 (
dv2 s dt dv2 c dt
diLf
− ω s v2 c ) +
4 v2 s i = i2 s π Ap Lf
+ ω s v2 s ) +
4 v2 c i = i2 c π Ap Lf
+ (iLf − io )rc =
dt dvCf dt
4 v π
+ ω s i1s ) + v1c = 0
dt
C1 (
Lf
− ω s i1c ) + v1s =
(16.47)
2 A − vCf π p
= iLf − io
The corresponding output equation is vo = (iLf − io )rc + vCf
(16.48)
It should be noted that the smallsignal modulation frequency is lower than the switching frequency, thus the nonlinear model can be linearized by perturbing the system around the operating point P. The perturbed variables are the inputs, the state variables, and the outputs. Each one has the form of x(t) = X + xˆ (t) © 2003 by CRC Press LLC
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671
where X is the steady state at the operating point, and xˆ (t) is a small amplitude perturbation. Similarly, in this circuit, the input variables are found to be v = V + vˆ
ω s = Ω s + ωˆ s
16.4.1.6 Perturbation and Linearization Under the small amplitude perturbation assumptions, the complete linearized smallsignal models can be established by applying the perturbation to Equation (16.47) and only considering the first partial derivatives, to give:
L1
diˆ1s = ZL1iˆ1c + E1s fˆsN − vˆ 1s + k v vˆ dt
L1
diˆ1c = − ZL1iˆ1s − E1c fˆsN − vˆ 1c dt
C1
dvˆ 1s ˆ = i1s − iˆ2 s + Gs vˆ 1c + J 1s fˆsN dt
C1
dvˆ 1c ˆ = i1c − iˆ2 c − Gs vˆ 1s − J 1c fˆsN dt
L2
diˆ2 s = vˆ 1s − vˆ 2 s + ZL 2 iˆ2 c + E2 s fˆsN dt
diˆ L2 2 c = vˆ 1c − vˆ 2 c − ZL 2 iˆ2 s − E2 c fˆsN dt
C2
dvˆ 2 s ˆ = i2 s − g ss vˆ 2 s + g sc vˆ 2 c − 2 k s iˆLf + J 2 s fˆsN dt
C2
dvˆ 2 c ˆ = i2 c − g cc vˆ 2 c + g cs vˆ 2 s − 2 kc iˆLf + J 2 c fˆsN dt
Lf Cf © 2003 by CRC Press LLC
diˆLf dt dvˆ Cf dt
= (iˆo − iˆLf )rc − vˆ Cf + k s vˆ 2 s + kc vˆ 2 c = iˆLf − iˆo
(16.49)
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ˆi 1S L1 kvvˆ
iˆ2S
eˆ1S – +
L2
+ vˆ 1S
+ –
eˆ 2S – +
C1
ˆj 1S
jˆ2S
L1
+ vˆ 1C – eˆ 1C
C1
ˆj 2C
ˆj 1C ˆi 2C
– +
kCvˆ 2C
C2
+ vˆ 2C –
– +
L2
+
ˆiO
Lf
rC
–
+ –
gCC
eˆ 2C
iˆLf kSvˆ 2S
+ vˆ 2S –
gSS
–
iˆ1C
C2
+ vˆ Cf
R Cf
+ vˆ O –
–
FIGURE 16.16 Equivalent smallsignal circuit of cascade reverse double ΓLC RPC.
where the input variables are vˆ and fˆsN , standing for the perturbed line voltage and normalized switching frequency, respectively. The output part of the smallsignal model is given by: vˆ o = (iˆLf − iˆo )rc + vˆ Cf
(16.50)
All the parameters used in the above models are given in the Appendix. 16.4.1.7 Equivalent Circuit Model This linearized smallsignal model makes it possible to describe the operating characteristics of the resonant converter using equivalent circuit model, as shown in Figure 16.16. In this model, the circuit is divided into two parts: the resonant network and the output part. To simplify the drawing, some dependent sources are defined as: eˆ1s = ZL1iˆ1c + E1s fˆsN
eˆ1c = ZL1iˆ1s + E1c fˆsN
eˆ2 s = ZL 2 iˆ2 c + E2 s fˆsN
eˆ2 c = ZL 2 iˆ2 s + E2 c fˆsN
ˆj = G vˆ + J fˆ 1s 1s sN s 1c
ˆj = G vˆ + J fˆ 1c 1c sN s 1s
ˆj = g vˆ − 2 k iˆ + J fˆ 2s sc 2 c s Lf 2 s sN
ˆj = g vˆ − 2 k iˆ + J fˆ 2c cs 2 s c Lf 2 c sN
© 2003 by CRC Press LLC
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+V –V
Driver
Cascade Reverse Double ΓLC Resonant Power Converter
Halfbridge circuit
vab
Double LC resonant network
vC2
673
Rectifier & lowpass R filter
vO
vS
Sampling network Z2 Voltage controlled oscillator
ve
Z1 Vref Compensation network
FIGURE 16.17 Closedloop system of cascade reverse double ΓLC RPC.
By employing the Kirchoff’s current law and voltage law, the equivalent circuit can be drawn following the stateequation Equation (16.49). Note that in the output part, the voltage across the second capacitor vˆ C2 is replaced by two voltagecontrolled sources {k s vˆ 2 s , kc vˆ 2 c }. This circuit model can be implemented in generalpurpose simulation software, such as PSpice or MATLAB, to obtain the frequency response of the system.
16.4.2
ClosedLoop System Design
The closedloop control system diagram of the halfbridge cascade reverse double ΓLC RPC is illustrated in Figure 16.17, where the feedback loop is composed of the sampling network, the compensator, and the voltagecontrolled oscillator (VCO). The sampling network, R1 and R2, contributes attenuation according to its sampling ratio of R1/(R1 + R2). Since the two resistors are chosen to be equal, the gain attenuation of the network is 20 log (vs/vo) = –6dB. The sampled voltage, vs, is then sent to the inverting input side of the error amplifier, where it is compared with a fixed reference voltage vref and generates an error voltage, ve. This voltage determines the frequency output of a voltagecontrolled oscillator (VCO), whose gain can be obtained either in datasheet or by experiment. The Bode plot, considering all the voltage gains of the main circuit, the sampling network and VCO, is shown in Figure 16.18. It should be noted that the slope of the magnitude response at the unitygain crossover frequency is –40dB/decade. Both the gain margin and the phase margin of the smallsignal model are not able to meet the requirements of the stability. Thus, the alleged feedback compensation is often used to shape the frequency response such that it remains stable under all operating conditions, especially in the presence of noise or disturbance injected at any point in the loop. In order to yield a –20dB/decade slope at the unitygain crossover frequency, the magnitude response of the compensation network must have a slope of +20dB/decade slope at the unitygain crossover frequency. Hence, a three poles and double zeros compensation network is © 2003 by CRC Press LLC
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Magnitude (dB)
50
40 dB/decade 0 50
Phase (deg)
100 0 Phase margin = 5 deg. 175 180
360 101
540
102
103
104
Frequency (Hz)
FIGURE 16.18 Bode diagram of the smallsignal equivalent circuit.
C2 C3
R3
C1
R2
+V
R vs ∞
ve
Vref –V
FIGURE 16.19 Compensation network.
employed, whose circuit implementation and Bode diagram are shown in Figure 16.19 and Figure 16.20 respectively. The transfer function for this compensation network is H ( jω ) =
1 + jω( R1 + R3 )C3 1 + jωR2 C1 −ω R2 C1C2 + jω(C1 + C2 ) R1 + jωR1R3 C3 2
(16.51)
As seen from Equation (16.51), it has two highfrequency poles, one at fp1 = 1/2R3C3 and the other at fp2 = (C1 + C2)/2R2C1C2. The zeros are at fz1 = 1/ 2R2C1 and fz2 = 1/2(R1 + R3)C3, respectively. The two gains of the compensation network are K1 = R2/R1 and K2 = R2 (R1 + R3)/R1R3, respectively. To simplify the design process, the two high frequency poles are usually chosen to be equal to each other (i.e., fp1 = fp2 = fp) such that © 2003 by CRC Press LLC
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Magnitude (dB)
Cascade Reverse Double ΓLC Resonant Power Converter
K +20dB/dec. 20dB/dec.
20dB/dec. K1
f(log scale)
fz
0
Phase (degree)
675
fp
0
90
fz
f1
fp
f(log scale)
FIGURE 16.20 Bode schematic diagram of the compensation network.
C1 + C2 1 = 2 πR3 C3 2 πR2 C1C2
(16.52)
The phase lag due to the double poles, θp, is θ p = 2 tan −1 (
fp f1
)
(16.53)
where f1 is the unitygain crossover frequency. Similarly, the two zeros are also chosen to be equal, such that 1 1 = 2 πR2 C1 2 π( R1 + R3 )C3
(16.54)
The phase boost at the double zeros, θz, is f θ z = 2 tan −1 ( 1 ) fz
(16.55)
Hence the total phase lag introduced by the compensation network and the error amplifier at the unitygain crossover frequency is fp f θc = 270° − 2 tan −1( 1 ) + 2 tan −1( ) fz f1 © 2003 by CRC Press LLC
(16.56)
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Magnitude (dB)
50
20 dB/decade 0
Gain margin = 9.7 dB
50
Phase (deg)
100 0 134
Phase gain = 46 deg.
180
360 101
102
930 103
104
Frequency (Hz)
FIGURE 16.21 Bode diagram of the open loop system.
where the 270° phase lag is due to the phase inversion introduced by the inverting amplifier and the pole at the origin of the compensation network. Consider the real system described in Figure 16.21, the unitygain crossover frequency is chosen to be 900 Hz, where the attenuation is –16 dB. Hence, the gain of the error amplifier at the unitygain crossover frequency is chosen to be +16 dB in order to yield 0 dB at the unitygain crossover frequency. The locations of the double poles and double zeros of the compensation network are chosen to yield the desired phase margin of 45°. The total phase shift at the unitygain crossover frequency is 360° – 45° or 315°. Taking into account the effect of equivalent series resistor (ESR) in the output capacitor, the phase lag of the output filter with an output capacitor ESR is θLC = 180° − tan −1(
f1 fESR
)
(16.57)
where fESR is the ESR break frequency fESR =
1 2πrc C f
(16.58)
Then the phase lag contribution from the compensation network and the error amplifier is θ ea = 315° − θLC © 2003 by CRC Press LLC
(16.59)
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677
Hence, from Equation (16.58), the phase lag contribution from the compensation network is fp 3 2 tan −1( ) − 2 tan −1( ) = 270° − θ ea fz 3
(16.60)
Solving this equation yields a value of 4.64 to achieve a phase lag of 65.67°. Hence, the highfrequency pole should be located at 4.64 times the unitygain crossover frequency, or 4.2 KHz, while the lowfrequency zero should be located at onefourth of the unitygain crossover frequency, or 190 Hz. There are six components to be selected for the compensation network. As described previously, the gain at the double zero, K1, is 0 dB, or 1. Assuming an R1 value of 1 KΩ, R2 is 1 KΩ too. The gain at the double poles, K2, is selected to be 20 dB, or 10. Thus, R3 is given by
R3 =
R1R2 K 2 R1 − R2
(16.61)
1 2 πfp R3
(16.62)
The capacitance value for C3 is C3 =
Hence, the capacitance values of C1 and C2 can be calculated respectively from Equation (16.52) and Equation (16.54). The Bode diagram of the open loop system is given in Figure 16.21. Notice that the gain at the unitygain crossover frequency in the overall magnitude response of the feedbackcompensated resonant converter is 0 dB with a slope of –20 dB/decade. The unitygain crossover frequency is enhanced from 540 KHz to 930 KHz, at which point the phase lag is reduced from –175° to –134°. The values of gain margin and phase margin are 9.7 dB and 46°, respectively. Both of them have fit the specified requirements of the stability. In most cases, the stability plays an important role in various performance indexes of a closedloop system. For this resonant converter, the stability can be studied by analyzing the characteristics of the poles and zeros of the closedloop system. Since the smallsignal model has been found in previous section, the statespace equations can be established from Equation (16.49), to give: dxˆ = Axˆ + Buˆ dt © 2003 by CRC Press LLC
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and yˆ = Cxˆ + Duˆ where
(
xˆ = iˆ1s , iˆ1c , vˆ 1s , vˆ 1c , iˆ2 s , iˆ2 c , vˆ 2 s , vˆ 2 c , iˆLf , vˆ Cf
(
uˆ = vˆ , fˆsN , iˆo
)
T
)
T
yˆ = vˆ o
Based on the relationship between the statespace equation and transfer function, these equations of the open loop system can be transformed to the transfer function G1(s), to give: G1 ( s) =
Yˆ ( s) = C[sI − A]−1 B + D Uˆ ( s)
(16.63)
By considering both the expression in Equation (16.51) and G1(s), the closedloop control system transfer function can be obtained. Hence, the poles of the closedloop control system are found to be: p1,2 = –0.3138 ±19.3296i
p3,4 = –0.8750 ±12.9716i
p5,6 = –0.8809 ± 5.2819i
p7,8 = –0.3914 ± 0.9492i
p9,10 = –0.0071 ± 0.0377i
p11,12 = –0.7777 ± 0.0000i
p13 = 0 Notice that all the real parts of the poles are nonnegative, thus, the whole system is found stable. The root loci of the closedloop system are given in Figure 16.22.
16.5 Discussion In all the previous sections, the analyses are undertaken on the basis of the assumption that two resonant inductors are identical, as well as two resonant capacitors. The following discussion will be focused on the condition that the resonant components have different values, that is, variableparameters. © 2003 by CRC Press LLC
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679
Root Locus 20 15
Image Axis
10 5 0 5 10 15 20 Real Axis
FIGURE 16.22 Root loci of the closedloop system.
In addition, the discontinuous operation, always occurring when switching frequency is lower than the natural resonant frequency, will also be taken into consideration.
16.5.1
Characteristics of VariableParameter Resonant Converter
In fact, most of the derivation results and general conclusions in Section 16.3 and Section 16.4 are still valid for the variableparameter condition, except that the curves of the voltage transfer gain are a little bit different. For instance, if the ratios of two inductors and two capacitors are defined as: p = L1 / L2
and
q = C1 / C2
then the expression in Equation (16.1) can be rewritten as : g (ω ) =
Req ω pβL C Req − ω 2 ( pq + p + 1)LCReq + R + j[ωL( p + 1) − ω 3 L2 Cpq] eq 4
2
2
(16.64)
Following the same definitions of the natural resonant frequency ω0, Q value, and relative frequency β, the voltage transfer gain g(β) is given by: g(β) = © 2003 by CRC Press LLC
1 1 − β 2 ( pq + p + 1) + β 4 pq + j[( p + 1) − pqβ 2 ]βQ
(16.65)
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Advanced DC/DC Converters
and its determinant is 1
g(β) =
[1 − β ( pq + p + 1) + β pq]2 + [( p + 1) − pqβ 2 ]2 β 2Q 2 2
4
(16.66)
The local maximum and minimum values of the voltage gain g(β) can be gained by solving the resulting equation after setting the derivatives of the determinant to zero. d g(β) = 0 dβ 2
(16.67)
4 p 2 q 2β 6 + [3 p 2 q 2Q 2 − 6 pq( pq + p + 1)]β 4 + [4 pq + 2( pq + p + 1)2 − 4 pq( p + 1)Q 2 ]β 2
(16.68)
+ Q 2 ( p + 1)2 − 2( pq + p + 1) = 0 When p = q = 1, this equation is simplified to be
(
)
(
)
4β6 + 3Q 2 − 18 β 4 + 22 − 8Q 2 β2 + 4Q 2 − 6 = 0 which is the same as Equation (16.21). Figure 16.23a to d depict the voltage gain g(β) with different parameter ratios referring to various Q values. One can find that all the curves have the similar shape in Figure 16.4, which begins with unity at low switching frequency and displays two peaks with lower Q values. However, the different parameter ratio results in a different bandwidth. Thus, the designer will have more choice to find the most appropriate bandwidth to meet the requirements of various applications. Besides this, with certain parameter ratios (for example, p = 2, q = 1), all the curves intersect at one point, which is independent of the Q values. The corresponding switching frequency can be calculated by setting the imaginary part of the denominator in the expression in Equation (16.65) to zero, gives: p + 1 = pqβ˜ 2 or p+1 β˜ 2 = pq
© 2003 by CRC Press LLC
(16.69)
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Cascade Reverse Double ΓLC Resonant Power Converter
1.8
6
Voltage gain (Vc2/Vi)
Voltage gain (Vc2/Vi)
L1 = 0.5*L2 C1 = C2
L1 = 2*L2 C1 = C2
Q = 0.5
1.6 1.4 1.2 Q=1 1 0.8 0.6
Q=2 0.4
0.0 0.0
5
4
3 Q = 0.5
2
Q=1 1
Q=4 0.2
681
Q=2 Q=4
Q = 10 0.5
1.5
1.0
0 0.0
2.5
2.0
Normalized switching frequency
0.5
(b) 3.5 L1 = L2 C1 = 2*C2
Q = 0.5
1.4
L1 = L2 C1 = 0.5*C2
3
Voltage gain (Vc2/Vi)
Voltage gain (Vc2/Vi)
3
2
Q=1
1 Q=2 0.5
Q=4
2.5 2 1.5 Q = 0.5 1 Q=1 0.5
Q=2 Q=4
Q = 10 0.0 0.0
2.5
2.0
Normalized switching frequency
(a)
1.5
Q = 10 1.5
1.0
0.5
1.5
1.0
2.0
2.5
0 0.0
Normalized switching frequency
0.5
1.5
1.0
2.5
2.0
Normalized switching frequency
(c)
Q = 10
(d)
FIGURE 16.23 Voltage gain g(β) with different parameter ratios referring to various Q.
Substituting Equation (16.69) into Equation (16.65), the voltage gain at this frequency is obtained as: g(β˜ ) =
1 p
(16.70)
Hence, the voltage transfer gain is only dependent on the inductors ratio α and it determines the rough shape of the gain curve over a wide frequency range [0 ~ β˜ ] , which is useful for the designer to estimate the needed operating point. Figure 16.24 gives the maximum voltage transfer gain vs. different parameter ratios of p and q, corresponding to the peak value in Figure 16.23a to d. Notice that the maximum gain is obtained with small p and large q. This is true because when L1 is much smaller than L2 while C1 is larger than C2, the cascade reverse double ΓLC RPC will be degraded to the conventional parallel resonant converter, which voltage gain is prominent near the natural resonant frequency. Figure 16.24 shows the threedimensional relations. © 2003 by CRC Press LLC
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Advanced DC/DC Converters
30 25 1.5
10
os
15
0.2
0.4
0.6
0.8
or
pa
0
cit
0.5
0
rat i
1
5
(C 1/C 2)
2
20
1
1.2
1.4
1.6
1.8
0
Ca
Maximum voltage gain
682
2
Inductor ratios (L1/L2) FIGURE 16.24 Maximum voltage gain vs. different parameter ratios of p and q.
The dynamic analysis of the variableparameter resonant converter is similar to that in the previous section, except that some relevant matrices need to be amended. The waveforms of the input and the resonant voltage are shown in Figure 16.25a, where some distortions can be found in the second capacitor voltage vc2. Figure 16.25b is the probe output of the commonly used circuit simulation software PSpice. From this one can find a good accordance between the two figures. The comparison of the resonant output voltage and total harmonic distortion (THD) of the variableparameter resonant converter is given in Table 16.1. Compared to other conditions, the second capacitor voltage obtains the highest amplitude when L1 = L2, C1 = C2, while it keeps the lowest total harmonic distortion value. Thus, it is reasonable to implement the practical cascade reverse double ΓLC RPC with dual symmetric resonant network.
16.5.2
Discontinuous Conduction Mode (DCM)
When the switching frequency is lower than half of the natural resonant frequency, the current through the inductors and the voltage across the capacitors will become discontinuous. For the cascade reverse double ΓLC PRC, in DCM operation, the energy in the resonant capacitor is consumed before the new half of a switching cycle. There are six stages of operation in one switching cycle, as shown in Figure 16.26. Suppose before the beginning of a switching cycle, the second inductor current iL2 is zero. When stage 1 begins at time t0, since iL2 is lower than the constantcurrentsink Io, all the © 2003 by CRC Press LLC
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Cascade Reverse Double ΓLC Resonant Power Converter
683
40 Vi Vc2
Voltage (V)
30 20 10 0 10 20 30 40 8.31
8.32
8.33
8.34
Time (s)
8.35
8.36 x 103
(a) 40V 20V
V(i) 0V
V(C2) 20V
40V 4.94ms
4.95ms 4.96ms 4.97ms
4.98ms 4.99ms 5.00ms
Time
(b) FIGURE 16.25 Simulation waveforms using Matlab (a) and PSpice (b) when L1 = 10 L2.
rectifier diodes become forward biased and conduct. The second capacitor C2 is clamped to zero volts by the freewheeling action, which is shown in Figure 16.27a. Thus, the second inductor L2 is charged and the current though it is increased. Stage 2 commences when the current iL2 reaches the magnitude of the currentsink I0, at time t1. The topology at this moment is the same as that in CCM operation. Stage 3 starts when the input voltage source Vi changes its polarity at time t2, as depicted in Figure 16.27c. This completes the first halfcycle of operation. The next halfcycle operation repeats the same way as the first halfcycle, except that the direction of the inductor current iL2 and the polarity of the capacitor voltage vC2 are reversed. The state coefficient matrix and input source vector corresponding to two additional operating modes are given by:
© 2003 by CRC Press LLC
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Advanced DC/DC Converters TABLE 16.1 Comparison of Output Resonant Voltage and THD Values under Different Parameter Ratios α (L1/L2)
β (C1/C2)
1 2 0.5 1 1 2 0.5 0.5 2
1 1 1 2 0.5 2 0.5 2 0.5
Switching frequency fs = 50 KHz Vc2 Amplitude (V) THD (%) 23.5 11.0 17.0 6.0 8.0 3.5 10.0 19.0 6.0
2.41 7.90 6.84 5.82 5.93 2.72 7.14 8.55 3.91
Note: With L2 = 100 µH, C2 = 0.22 µF, R = 22 Ω, Lf = 2.4 mH, Cf = 220 µF
TABLE 16.2 Comparison of Output Voltage and THD among Different Resonant Converters Vo(V) Converter
THD(%)
SRC RPC SRPC CRD ΓLC Vi
3.355 4.254 4.341 2.407 —
7.88 6.09 15.9 12.0 —
Harmonic Statistics 1st 3rd 5th 16.50 12.18 59.87 23.29 18.83
3.042 0.419 2.485 0.517 6.366
Harmonic proportion (%) 1st 3rd 5th
3.663 0.261 0.625 0.179 3.820
100 100 100 100 100
18.4 3.44 4.15 2.22 33.8
vC2 i L2
Vi
I0
t4 t1
t0
mode1
t2
mode2
t3
t5
t6 t
mode3
FIGURE 16.26 Switching waveforms for the discontinuousmode cascade reverse double ΓLC RPC. © 2003 by CRC Press LLC
22.2 2.14 1.04 0.77 18.5
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Cascade Reverse Double ΓLC Resonant Power Converter L1
V
685
L2
C1
C2
Io
(a) L1
V
L2
C1
C2
vC2 Io
C2
vC2 Io
(b) L1
V
L2
C1
(c) FIGURE 16.27 Discontinuousmode equivalent circuits in half cycle.
0 0 1 C1 A5 = 0 0 0
0 0 − 1 C2 0 0 0
B5 = [V L1
−1 L1 1 L2 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 1 Cf
0
0
0
0
0 0 0 0 − 1 Lf − 1 RC f 0]
T
and A6 = A5
B6 = [−V L1
0
0
0
0
0]
T
The augmented statespace equation in Section 16.4 is still valid besides that the state transition matrices describing two additional operating modes should be considered as well. The waveforms of simulation and experimental results under DCM operation are shown in Figure 16.28. Note that the © 2003 by CRC Press LLC
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Advanced DC/DC Converters
40 V (10V/div.) Vc2 (20V/div.)
Voltage (V)
30 20 10 0 10 20 30 40 9
9.1
9.2
9.3
9.4
9.5
Time (s)
9.6
9.7
9.8
9.9
10
x 104
(a)
(b) FIGURE 16.28 Simulation (a) and experimental (b) switching waveforms for DCM operation.
second capacitor voltage is discontinuous at some intervals, which verifies the description of the theoretical analysis. In practice, the discontinuous conduction mode is often dependent on the switching frequency and the equivalent load current I0. Namely, under a certain load current, when the switching frequency is increased, the operating state of the resonant converter will transfer from DCM to CCM. Conversely, if the switching frequency is invariant, the increase of the load current will lead to the occurrence of DCM. Thus, it is very significant to © 2003 by CRC Press LLC
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Cascade Reverse Double ΓLC Resonant Power Converter
687
Load resistor (Ohms)
60 50 40 30 20 10 0 20
25
30
35
40
45
50
55
60
65
70
Switching frequency (KHz) FIGURE 16.29 Critical load resistor vs. the switching frequency.
find the relationship between the load current and the switching frequency, in other words, to find the critical load current Jcr under a certain frequency. In many open literatures, the critical load current is always obtained by solving the differential equations and identifying the respective duration of various subintervals. For instance, the normalized critical load current of RPC is given: J cr = sin 2 ( γ / 2) + sin 2 ( γ ) / 4 − sin( γ ) / 2
(16.71)
This conclusion is very simple and straightforward to describe the relationship between fs and I0. However, it is acquired at the cost of very complicated calculations and derivations. For SRPC, there is no similar analytical expression given in the literature. In fact, with the increase of the quantity of the resonant components, the order of the differential equations becomes very large so that it seems impossible to solve them by pen and paper. Once again, the numerical calculation offers a very useful solution to overcome such a problem. The numerical analysis method starts at solving the higher order state equations using recursion algorithm. Once the steady state is achieved, it is up to the algorithm that judges whether the critical load current is found correctly. The drawbacks of this method are in two aspects: one is the discrete result; the other is timeconsuming. However, the obtained results are proved to be precise and useful so long as the step of the loop is small enough. The critical load resistor and critical load current vs. the switching frequency are shown in Figure 16.29 and Figure 16.30 respectively. © 2003 by CRC Press LLC
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Advanced DC/DC Converters 1.8
Load resistor (Ohms)
1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 20
25
30
35
40
45
50
55
60
65
70
Switching frequency (KHz) FIGURE 16.30 Critical load current vs. the switching frequency.
Bibliography Agarwal, V. and Bhat, A.K.S., Smallsignal analysis of the LCCtype parallel resonant converter using discrete time domain modeling, in Proceedings of IEEE Power Electronics Specialists Conference, 1994, p. 805. Bhat, K.S., Analysis and design of a seriesparallel resonant converter with capacitive output filter, IEEE Transactions on Industry Applications, 27, 523, 1991. Bhat, K.S. and Swamy, M.M., Analysis and design of a parallel resonant converter including the effect of highfrequency transformer, in Proceedings of IEEE Power Electronics Specialists Conference, 1989, p. 768. Deb, S., Joshi, A., and Doradla, S.R., A novel frequency domain model for a parallel resonant converter, IEEE Transactions on Power Electronics, 3, 208, 1988. Forsyth, A. J., Ho, Y.K. E., and Ong, H.M., Comparison of smallsignal modeling techniques for the seriesparallel resonant converter, in Proceedings of IEE Conference on Power Electronics and Variable Speed Drives, 1994, p. 268. Johnson, S.D., Steadystate analysis and design of the parallel resonant converter, IEEE Transactions on Power Electronics, 3, 93, 1988. Kang, Y.G. and Upadhyay, A.K., Analysis and design of a halfbridge parallel resonant converter, IEEE Transactions on Power Electronics, 3, 254, 1988. Kit, S.K., Recent Developments in Resonant Power Conversion, CA, Intertec Communications, 1988. Liu, K.H. and Lee, F.C., Zerovoltage switching technique in DC/DC converters, in Proceedings of IEEE Power Electronics Specialists Conference, 1986, 58. Middlebrook, R.D. and Cúk, S., A general unified approach to modeling switching converter power stages, in Proceedings of IEEE Power Electronics Specialists Conference, 1976, p. 18. Nathan, B.S. and Ramanarayanan, V., Analysis, simulation and design of series resonant converter for high voltage applications, in Proceedings of IEEE International Conference on Industrial Technology 2000, 2000, p. 688. © 2003 by CRC Press LLC
1956_C16.fm Page 689 Friday, August 8, 2003 12:33 AM
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689
Ranganathan, V.T., Ziogas, P.D., and Stefenovic, V.R., A regulated DCDC voltage source converter using highfrequency link, in Proceedings of IEEE Industry Application Society Conference, 1981, p. 917. Sanders, S., Noworolski, J., Liu, X., and Verghese, G., Generalized averaging method for power conversion circuits, in Proceedings of IEEE Power Electronics Specialists Conference, 1989, p. 273. Swamy, M.M. and Bhat, A.K.S., A comparison of parallel resonant converters operating in lagging power factor mode, IEEE Transactions on Power Electronics, 9, 181, 1994. Verghese, G., Elbuluk, M., and Kassakian, J., Sampleddata modeling for power electronics circuits, in Proceedings of IEEE Power Electronics Specialists Conference, 1984, p. 316. Vorperian, V. and Cúk, S., A complete DC analysis of the series resonant converter, in Proceedings of IEEE Power Electronics Specialist Conference, 1982, p. 85. Vorpérian, V. and Cúk, S., Smallsignal analysis of resonant converters, in Proceedings of IEEE Power Electronics Specialists Conference, 1983, p. 269. Yang, E.X., Choi, B.C., Lee, F.C., and Cho, B.H., Dynamic analysis and control design of LCC resonant converter, in Proceedings of IEEE Power Electronics Specialists Conference, 1992, p. 941. Zhu, J.H. and Luo, F.L., Cascade reverse double ΓLC resonant power converter, in Proceedings of IEEEPEDS’03, Singapore, 2003, p. 326.
© 2003 by CRC Press LLC
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Advanced DC/DC Converters
APPENDIX Parameters Used in SmallSignal Modeling kv =
4 π
g ss =
geα 2 α 2 + β2
ks =
2 V2 s π Ap
g cc =
g eβ 2 α 2 + β2
kc =
2 V2 c π Ap
g sc = Ω sC2 +
ZL1 = Ω s L1
g cs = −Ω sC2 +
ZL 2 = Ω s L2 Gs = Ω sC1 E1s = ω 0 L1 I 1c E1c = ω 0 L1 I 1s E2 s = ω 0 L2 I 2 c E2 c = ω 0 L2 I 2 s J 1s = ω 0 C1V1c J 1c = ω 0 C1V1s J 2 s = ω 0 C2V2 c J 2 c = −ω 0 C2V2 s
© 2003 by CRC Press LLC
αβ α 2 + β2
Ve =
4 V π g
ge =
8 π2R
Ap =
1 α + β2 2
αβ α + β2 2
Ve
α = g e Ω s L(Ω 2s LC − 2) β = Ω s4 L2 C 2 − 3Ω 2s LC + 1
1956_C17.fm Page 691 Thursday, August 7, 2003 9:42 PM
17 DC Energy Sources for DC/DC Converters
The DC/DC converter is used to convert a DC source voltage to another DC voltage actuator (user). In a DC/DC converter system the main parts are the DC voltage source, switches, diodes, inductors/capacitors, and load. This chapter introduces the various DC energy sources that are usually employed in DC/DC converters.
17.1 Introduction In a DC/DC converter system the initial energy source is a DC voltage source with certain voltage and very low internal impedance, which can be usually omitted. This means the used DC voltage source is ideal. The DC voltage source can be a battery, a DC bus (usually equipped in factories and laboratories), a DC generator, and an AC/DC rectifier. As is wellknown, the battery, DC bus, and DC generator can be considered an ideal voltage source. They will be not discussed in this book. AC/DC rectifiers are widely applied in industrial applications and research centers since it is easily constructed and less costly. In this chapter the AC/DC rectifiers will be discussed in detail. AC/DC rectifiers can be grouped as follows: • • • • • • •
Singlephase halfwave diode rectifier Singlephase fullwave bridge diode rectifier Threephase bridge diode rectifier Singlephase halfwave thyrister rectifier Singlephase fullwave bridge thyrister rectifier Threephase bridge thyrister rectifier Other devices rectifiers
© 2003 by CRC Press LLC
1956_C17.fm Page 692 Thursday, August 7, 2003 9:42 PM
D
iO
iin +
vin =
vD
–
2 Vinsinωt
+
Z
vO –
FIGURE 17.1 Halfwave diode rectifier.
17.2 SinglePhase HalfWave Diode Rectifier The singlephase halfwave diode rectifier is shown in Figure 17.1, it is the simplest rectifier circuit. The load Z in the figure can be any type such as resistor, inductor, capacitor, back electromotive force (EMF), and/or a combination of these. This rectifier can rectify the AC input voltage into DC output voltage. The analysis of the circuit is based on the assumption that a diode as an ideal component is used for the rectification. A diode forward biased will conduct without forward voltagedrop and resistance. A diode reverse biased will be blocked, and likely an open circuit. Since the used diode is not continuously conducted, the output current is always discontinuous in some part of negative halfcycle.
17.2.1
Resistive Load
A singlephase half wave rectifier with a purely resistive load (R) is shown in Figure 17.2a, and its input/output voltage vin and vO, and input/output current iin and iO waveforms are shown in Figure 17.2b and c. The AC supply voltage vin is sinusoidal, the output voltage and current obey Ohm’s law. Therefore the output voltage and current are sinusoidal halfwaveforms vin (t) = 2Vin sin ωt 2Vin sin ωt vO ( t ) = 0 2Vin iin (t) = iO (t) = R sin ωt 0 © 2003 by CRC Press LLC
(17.1)
0 ≤ ωt ≤ π π < ωt < 2 π
0 ≤ ωt ≤ π π < ωt < 2 π
(17.2)
(17.3)
1956_C17.fm Page 693 Thursday, August 7, 2003 9:42 PM
D
iO
iin +
vin =
vD
–
2 Vinsinωt
+
Z
vO –
(a) Circuit diagram
vin 2 Vin
iin
π
0
2π
ωt
2π
ωt
(b) Input voltage and current
vO 2 Vin
iO
π
0
(c) Output voltage and current FIGURE 17.2 A singlephase half wave rectifier with a purely resistive load (R).
Where Vin is the rootmeansquare (RMS) value of the input voltage. The input wave is a sinusoidal waveform, the corresponding output is halfwave of a sinusoidal waveform for both voltage and current without angle shift between voltage and current. The output DC average voltage and current are VO− av =
2 V = 0.45Vin π in
I O− av = 0.45
17.2.2
Vin R
(17.4)
(17.5)
Inductive Load
A singlephase half wave rectifier with an inductive load (a resistor R plus an inductor L) is shown in Figure 17.3a. The input voltage and current vin and iin waveforms are shown in Figure 17.3b, output voltage vO in c and © 2003 by CRC Press LLC
1956_C17.fm Page 694 Thursday, August 7, 2003 9:42 PM
D
iin
vD
+
vin =
vO
L +
–
2 Vinsinωt
vD –
(a) Circuit diagram
e10 i
∆I
∆i
A ωL∆i

e20
i R
B
Voltage across Voltage across R
L Voltage across diode
ωt
ωt
ωt
ωt
0
1
2
3
e20 D ωt
C
1 cycle
(b),(c), and (d) FIGURE 17.3 A singlephase half wave rectifier with an inductive load (R + L). © 2003 by CRC Press LLC
R
1956_C17.fm Page 695 Thursday, August 7, 2003 9:42 PM
output current iO in d. The AC supply voltage is sinusoidal, the output voltage and current obey Ohm’s law. The impedance of load is Z = R + jωL = R 2 + (ωL)2 ∠ φ where Z = R 2 + (ωL)2
and
φ = tan −1
ωL R
Input voltage is vin (t) = 2Vin sin ωt
(17.1)
Output voltage is 2Vin sin ωt vO (t) = 0
0 ≤ ωt ≤ ( π + φ) ( π + φ) < ωt < 2 π
(17.6)
Where Vin is the RMS value of the input voltage. The input wave is sinusoidal waveform, the corresponding output is a partial sinusoidal waveform more than halfcycle. Since it is negative value in the negative halfcycle, the output DC average voltage is VO− av =
2 (1 − cos φ)Vin = 0.45(1 − cos φ)Vin π
(17.7)
The input and output current waveform is no longer a sinusoidal waveform. 2Vin − t/τ iin (t) = iO (t) = Z [sin(ωt − φ) + sin φ ⋅ e 0
0 ≤ ωt ≤ ( π + φ) (17.8) ( π + φ) < ωt < 2 π
where τ is the load time constant τ = L/R. The input and output current average value is I O− av = 0.45
© 2003 by CRC Press LLC
Vin (1 − cos φ) R
(17.9)
1956_C17.fm Page 696 Thursday, August 7, 2003 9:42 PM
D
iin +
vin =
vD
iO +
–
2 Vinsinωt
vO
L
–
(a) Circuit diagram
vin = vO 2 Vin
0
π
2π
ωt
2π
ωt
(b) Input and output voltages
2
iin = iO
2 Vin
wL
Io
0
π
(c) Input and output currents FIGURE 17.4 A singlephase half wave rectifier with a pure inductive load (L).
17.2.3
Pure Inductive Load
A singlephase half wave rectifier with a pure inductive load (an inductor L only) is shown in Figure 17.4a, and its input/output voltage vin and vO and input/output current iin and iO waveforms are shown in Figure 17.4b and c. The circuit will be analyzed for the relationship of the output to input. The AC supply voltage is sinusoidal, the output voltage can follow it in time. The impedance of load is Z = jωL = ωL ∠ π / 2 Input and output voltage is © 2003 by CRC Press LLC
1956_C17.fm Page 697 Thursday, August 7, 2003 9:42 PM
vin (t) = vO (t) = 2Vin sin ωt
(17.1a)
Where Vin is the RMS value of the input voltage. The input wave is sinusoidal waveform, the corresponding output can be a full sinusoidal waveform too. Since it is negative value in full negative halfcycle, the output DC average voltage is 0. The input and output current waveform is a sinusoidal waveform. iin (t) = iO (t) =
17.2.4
2Vin (1 − cos ωt) ωL
(17.10)
Back EMF Plus Resistor Load
A singlephase half wave rectifier with a resistor plus an EMF load (a resistor R plus an EMF) is shown in Figure 17.5a, and its input/output voltage vin and vO and input/output current iin and iO waveforms are shown in Figure 17.5b and c. The EMF value is E which is smaller than the input peak voltage √2Vin. Suppose an auxiliary parameter m is m = E/√2Vin < 1 and α = sin −1 m = sin −1
E 2Vin
The circuit will be analyzed for the relationship of the output to input. The AC supply voltage is sinusoidal, the output voltage and current obey Ohm’s law. The impedance of load is vin (t) = 2Vin sin ωt
Input voltage is
Input voltage is
2Vin sin ωt vO (t) = E
α ≤ ωt ≤ ( π − α ) ( π − α ) < ωt < (2 π + α )
(17.1)
(17.11)
Where Vin is the RMS value of the input voltage. The input wave is a sinusoidal waveform, the corresponding output is a partial sinusoidal waveform less than halfcycle. The output DC average voltage is VO− av = © 2003 by CRC Press LLC
2Vin 1 α cos α + E( + ) > E π 2 π
(17.12)
1956_C17.fm Page 698 Thursday, August 7, 2003 9:42 PM
D
iO
iin +
vD
–
vO
2 Vinsinωt
vin =
+
R
E
–
– +
(a) Circuit diagram
vin 2 Vin
iin
π
0
2π
ωt
2π
ωt
(b) Input voltage and current
vO 2 Vin
iO
E
π
0
(b) Output voltage and current FIGURE 17.5 Singlephase half wave rectifier with an EMF plus resistor (R + EMF).
The input and output current waveform is no longer a sinusoidal waveform. 1 ( 2Vin sin ωt − E) iin (t) = iO (t) = R 0
α ≤ ωt ≤ ( π − α ) ( π − α ) < ωt < (2 π + α )
(17.13)
The input and output current average value is I O− av =
© 2003 by CRC Press LLC
0.45Vin [2 cos α − m( π − 2α )] 2R
(17.14)
1956_C17.fm Page 699 Thursday, August 7, 2003 9:42 PM
17.2.5
Back EMF Plus Inductor Load
A singlephase half wave rectifier with an EMF and inductive load (an EMF plus an inductor L) is shown in Figure 17.6a, and its input/output voltage vin and vO and input/output current iin and iO waveforms are shown in Figure 17.6b and c. The circuit will be analyzed for the relationship of the output to input. The AC supply voltage is sinusoidal waveform: vin (t) = 2Vin sin ωt
Output voltage is
Where
∫
π −α
α
2Vin sin ωt vO (t) = E
( 2Vin sin ωt − E)d(ωt) =
∫
α ≤ ωt ≤ ( π + γ ) ( π + γ ) < ωt < (2 π + α )
π −α + γ
π −α
(17.1)
(17.15)
(E − 2Vin sin ωt)d(ωt)
Where vin is the RMS value of the input voltage. The input wave is sinusoidal waveform, the corresponding output is a partial sinusoidal waveform. The output DC average voltage is E. The input and output current waveform is no longer a sinusoidal waveform. iin (t) = iO (t) 2Vin α ≤ ωt ≤ ( π + α + γ ) = ωL [(cos α − cos ωt) − m(ωt − α )] 0 ( π + α + γ ) < ωt < (2 π + α )
(17.16)
The input and output current average value is I O− av =
0.45Vin m [γ cos γ − sin(α + γ ) + sin α − α 2 ] 2ωL 2
17.3 SinglePhase Bridge Diode Rectifier Singlephase fullwave diode rectifier has two forms: • Bridge (Graetz) • Centertap (midpoint)
© 2003 by CRC Press LLC
(17.17)
1956_C17.fm Page 700 Thursday, August 7, 2003 9:42 PM
D
iin +
vin =
L
io –
vD
+
2 Vinsinωt
E
vO
+ –
–
(a) Circuit diagram e10 i E
∆I
∆i
A ωL∆i

e20
i R
B
Voltage across L Voltage across R
ωt
ωt
ωt
ωt
0
1
2
3
Voltage across diode
e20 E
D
ωt
C
1 cycle
(b), (c) and (d) FIGURE 17.6 Singlephase half wave rectifier with EMF plus inductor (EMF + L).
These are shown in Figure 17.7a and b. The input and output waveforms are same in both circuits. Use Graetz type for the description in the following sections. © 2003 by CRC Press LLC
1956_C17.fm Page 701 Thursday, August 7, 2003 9:42 PM
IO +
+
Vin
D1
D3
+ R
VS
VO –
D4
D2
–
–
(a) Bridge (Graetz)
VD1 +
+
D1
VS
R
iL

Vin
+ –
VS –
–
V
O
+
D2 VD2
(b) Centertap (Midpoint) FIGURE 17.7 Singlephase fullwave diode rectifier.
17.3.1
Resistive Load
A singlephase fullwave diode rectifier with a purely resistive load is shown in Figure 17.8a, and its input/output voltage vin and vO and input/output current iin and iO waveforms are shown in Figure 17.8b and c. The circuit will be analyzed for the relationship of the output to input. The AC supply voltage is sinusoidal, the output voltage and current obey Ohm’s law. Therefore the output voltage and current are sinusoidal halfwaveforms. vin (t) = 2Vin sin ωt 2Vin sin ωt vO ( t ) = 2Vin sin(ωt − π)
0 ≤ ωt ≤ π π < ωt < 2 π
2Vin sin ωt R iin (t) = iO (t) = 2Vin sin(ωt − π) R © 2003 by CRC Press LLC
(17.18) (17.19)
0 ≤ ωt ≤ π (17.20) π < ωt < 2 π
1956_C17.fm Page 702 Thursday, August 7, 2003 9:42 PM
iO iin
+ D4
D1
R
Vin D3
D2
VO
–
(a) Circuit diagram
2 Vin
vin iin
π
0
2π
ωt
(b) Input voltage and current
2 Vin
vO iO
0
π
2π
ωt
(c) Output voltage and current FIGURE 17.8 Singlephase fullwave diode rectifier with a purely resistive load.
Where Vin is the RMS value of the input voltage. The input wave is sinusoidal waveform, the corresponding output is repeating halfwave sinusoidal waveform for both voltage and current without angle shift between voltage and current. The output is a DC voltage with ripple in the repeating frequency 2ω. After FFT analysis of the rectified waveform, harmonics components are shown in the frequency spectrum. From the spectrum, there are only nth (n = 2k) harmonics exsisting. The parameter ripple factor RF is defined ∞
V RF = ac = Vdc © 2003 by CRC Press LLC
∑V
n
n =1
Vdc
(17.21)
1956_C17.fm Page 703 Thursday, August 7, 2003 9:42 PM
where Vdc is the DC component of the output voltage, which is the average value, Vn is the nth order harmonic component of the output voltage. The output DC average voltage and current are VO− av =
2 2 V = 0.9 Vin π in
I O− av = 0.9
17.3.2
Vin R
(17.22)
(17.23)
Back EMF Load
A singlephase fullwave diode rectifier with an EMF plus resistor load (a resistor R plus an EMF) is shown in Figure 17.9a, and its input/output voltage vin and vO and input/output current iin and iO waveforms are shown in Figure 17.9b and c. The EMF value is E which is smaller than the input peak voltage √2Vin. Suppose an auxiliary parameter m: m = E/√2Vin < 1 and α = sin −1 m = sin −1
E 2Vin
The circuit will be analyzed for the relationship of the output to input. The AC supply voltage is sinusoidal, the output voltage and current obey Ohm’s law. The impedance of load is Input voltage is
Output voltage is
vin (t) = 2Vin sin ωt 2Vin sin ωt vO (t) = E
α ≤ ωt ≤ ( π − α ) ( π − α ) < ωt < ( π + α )
(17.1)
(17.24)
Where Vin is the RMS value of the input voltage. The input wave is sinusoidal waveform, the corresponding output is a partial sinusoidal waveform less than halfcycle with repeating frequency of 2ω. The output DC average voltage is VO− av = © 2003 by CRC Press LLC
2 2Vin 2α E>E cos α + π π
(17.25)
1956_C17.fm Page 704 Thursday, August 7, 2003 9:42 PM
iO iin
+ D4
D1
D3
D2
R VO
Vin E
–
(a) Circuit diagram
vin
2 Vin
iin E
π
0
2π
ωt
2π
ωt
(b) Input voltage and current vO 2 Vin
iO E
π
0
(c) Output voltage and current FIGURE 17.9 Singlephase fullwave Drectifier with EMF plus resistor (R + EMF).
The input and output current waveform is no longer a sinusoidal waveform. 1 ( 2Vin sin ωt − E) iin (t) = iO (t) = R 0
α ≤ ωt ≤ ( π − α ) ( π − α ) < ωt < ( π + α )
(17.26)
The input and output current average value is I O− av =
© 2003 by CRC Press LLC
0.45Vin [cos α − m( π − 2α )] R
(17.27)
1956_C17.fm Page 705 Thursday, August 7, 2003 9:42 PM
iO
iin
+ D4
D1
D3
D2
C
Vin
R
VO
–
(a) Circuit diagram iin vin
2 Vin
π
0
2π
ωt
(b) Input voltage and current
iO 2 Vin
0
vO
π
2π
ωt
(c) Output voltage and current FIGURE 17.10 Singlephase full wave Drectifier with an capacitive load (R + C).
17.3.3
Capacitive Load
A singlephase full wave diode rectifier with a capacitive load (a resistor R plus a capacitor C) is shown in Figure 17.10a, and its input/output voltage vin and vO and input/output current iin and iO waveforms are shown in Figure 17.10b and c. The circuit will be analyzed for the relationship of the output to input. The AC supply voltage is sinusoidal. The load time constant τ = RC. © 2003 by CRC Press LLC
1956_C17.fm Page 706 Thursday, August 7, 2003 9:42 PM
vin (t) = 2Vin sin ωt
Input voltage is
(17.1)
From previous section analysis, the peak value of output voltage is Vmax = √2Vin. The minimum output DC voltage is Vmin. The capacitor charges from Vmin to Vmax during t1, discharges from Vmax to Vmin during t2 = T/2 – t1 ≅ 1/2f since usually t1 E cos α + ( π π 2
(17.41)
The input and output current waveform is no longer a sinusoidal waveform. 1 ( 2Vin sin ωt − E) iin (t) = iO (t) = R 0 © 2003 by CRC Press LLC
α ≤ ωt ≤ ( π − α ) ( π − α ) < ωt < ( π + α )
(17.42)
1956_C17.fm Page 710 Thursday, August 7, 2003 9:42 PM
17.4.3
Back EMF Load (E < 0.5 √2Vin)
A threephase halfwave diode rectifier with an EMF plus resistor load (a resistor R plus an EMF) is shown in Figure 17.12. The EMF value E is in the condition E < 0.5 √2Vin. Suppose an auxiliary parameter m: m = E/√2Vin < 0.5 vin (t) = 2Vin sin ωt vO (t) = 2Vin sin ωt
(
2nπ π 2nπ 5π + ) ≤ ωt ≤ ( + ) 3 6 3 6
(17.34)
(17.35)
where n = 1, 2, 3, … 1 ( 2Vin sin ωt − E) iin (t) = iO (t) = R 0
(
2nπ π 2nπ 5π + ) ≤ ωt ≤ ( + ) 3 6 3 6 other
(17.43)
Where Vin is the RMS value of the input voltage. The input wave is sinusoidal waveform, the corresponding output is repeating partial sinusoidal waveform for both voltage and current without angle shift between voltage and current. The output is a DC voltage with ripple in the repeating frequency 3ω. After FFT analysis of the rectified waveform, harmonic components are shown in the frequency spectrum. From the spectrum, there are only nth (n = 3k) harmonics existing. Where Vdc is the DC component of the output voltage, which is the average value, Vn is the nth order harmonic component of the output voltage. The output DC average voltage and current are VO− av =
3 6 V = 1.17Vin 2 π in
(17.44)
17.5 ThreePhase FullBridge Diode Rectifier with Resistive Load A threephase fullbridge diode rectifier with a purely resistive load is shown in Figure 17.13a, and its input/output voltage vin and vO and input/output current iin and iO waveforms are shown in Figure 17.13b. The three phase AC suppliers have same RMS value Vin with amplitude √2Vin and frequency ω, and phase angle shift of 120° each other. The circuit will be analyzed f