ULSI Science and Technology 1991

PROCEEDING SYPSU OFk THlE'.1 HIR INTERNATIONALLY UTALRESLEIFGAT6 SCEC AN TECANOLAGY AN ECNLG/19 ULSI~~ SCECSN ...

Author: John M. Andrews and George K. Celler (Editors)

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PROCEEDINGS OF THE THIRD INTERNATIONAL SYMPOSIUM ON ULTRA LARGE SCALE INTEGRATION SCIENCE AND TECHNOLOGY

ULSI SCIENCE AND TECHNOLOGY/ 1991 Edited by George K. Celler AT&T Bell Laboratories Murray Hill, New Jersey

John M. Andrews Naval Research Laboratory Washington, D.C.

C

COULD INC. Assistant Editors Wayne Bailey

Paul Nicollian

Sam Broydo

Carl Osburn

Jonathan Chapple-Sokol

Dan Peters

Linda Ephrath

Mark Pinto

Steve Fonash

Gary Ray

Wayne Greene

Arnold Reisman

Bob Kostelak

Dennis Schmidt

Hisham Massoud

Geraldine Schwartz

Ed Middlesworth

Jimmie Wortman

Ken Monnig

I.-W. Wu

Shyam Murarka

ELECTRONICS AND DIELECTRIC SCIENCE AND TECHNOLOGY DIVISIONS Proceedings Volume 91-11 THE ELECTROCHEMICAL SOCIETY, INC., 10 South Main St., Pennington, NJ 08534-2896

Copyright 1991 by The Electrochemical Society, Incorporated

Papers contained herein may not be reprinted and may not be digested by publications other than those of The Electrochemical Society in excess of 1/6 of the material presented.

Library of Congress Catalog Number: 91-75851 Printed in the United States of America

PREFACE This ECS Softbound Symposium Volume contains the papers presented at the Third International Symposium on Ultra Large Scale Integration (ULSI) Science and Technology, held May 5-10, 1991, in Washington, DC. The symposium was cosponsored by the Electronics and the Dielectrics Science and Technology Divisions of the Electrochemical Society, Inc. The total number of papers submitted was much larger than could be accommodated in a five day symposium. The final program consisted of 20 invited reviews and 73 contributed papers. The symposium continues to be international in character, with 27 papers from outside the United States, namely 16 from Japan, 10 from Europe, and one from India. One half of the accepted papers represents work done in industry, with the other half submitted by universities and non-profit research facilities in the US and abroad. The Symposiuim was intended to provide a forum for reviewing the recent important developments in the rapidly changing field of ULSI technology. In the two years since the last ULSI Symposium, the density and complexity of integrated circuits have roughly doubled. Full scale production of 16 Mbit DRAMs is about to begin, and 64 and 256 Mbit memory chips are being designed. Scaling of non-memory circuits is proceeding at a similar pace. Processing structures with deep submicron dimensions is becoming critically important. These issues are reflected in the contents of the present volume. One of the highlights of this year's ULSI Symposium was the award address by Dr. V. J. Kapoor, titled "Review of Thin Oxynitride Dielectrics for Memory Device Technology" Dr. Kapoor received the 1991 Thomas D. Callinan Award, sponsored by the Dielectrics Science and Technology Division. I This proceedings volume is divided into thirteen sections: Device Structure and Technology, Submicron Device and Process Modeling, Submicron Feature Patterning: Lithography, Submicron Feature Patterning: Etching, Shallow Junctions and Ohmic Contacts, Thin Gates, Process-Induced Damage and Contamination, Rapid Thermal Processing, Planarization Techniques, Interconnect and Packaging, Wafer Cleaning and Oxidation, Thin Film Deposition, and Miscellaneous Processing Issues. Each of the first ten sections is introduced by invited reviews. Their authors, who set the tone for the meeting, deserve special thanks. They are: K.-Y. Chiu D. J. Dumin R. C. Frye R. M. Geffken R. W. Hill L. D. Hutcheson D.-L. Kwong M. E. Law T. P. Ma K. Maex M. Miyake S. C. McNevin K. A. Monnig

Hewlett Packard Clemson University AT&T Bell Laboratories IBM IBM Raynet The Univ. of Texas Univ. of Florida Yale Univ. IMEC NTT AT&T Bell Laboratories SEMATECH

iii

M. M. Moslehi 0. Nalamasu M. R. Pinto K. Shimohigashi C. H. Ting J. J. Wortman

Texas Instruments AT&T Bell Laboratories AT&T Bell Laboratories Hitachi Intel North Carolina State Univ.

The symposium would not be possible without the hard work and assistance of many people. We would like to thank Howard Huff, Chairman of the Electronics Division, and Geraldine Schwartz, who chairs the Dielectrics Science and Technology Division, for their support and encouragement. We also greatly appreciate the assistance of the Electrochemical Society Office staff, in particular: V. H. Branneky and Roque J. Calvo, Executive Secretary and Assistant Executive Secretary of the Society, Sarah A. Kilfoyle, Director of Publications, and Brian Rounsavill, Meetings and Programs Manager. Members of the ULSI Subcommittee of the Electronics Division provided extensive assistance in the planning of the symposium. We want to especially acknowledge all of the Session Chairmen and Vice-chairmen, since they did most of the work on paper selection and manuscript reviewing for publication in this volume. They are: Wayne Bailey Sam Broydo Jonathan Chapple-Sokol Linda Ephrath Steve Fonash Wayne Greene Bob Kostelak Hisham Massoud Ed Middlesworth Ken Monnig Shyam Murarka Paul Nicollian Carl Osburn Dan Peters Mark Pinto Gary Ray Arnold Reisman Dennis Schmidt Geraldine Schwartz Jimmie Wortman I.-W. Wu

Texas Instruments OPS, Inc. IBM IBM Pennsylvania State Univ. Hewlett Packard AT&T Bell Laboratories Duke University Hewlett Packard SEMATECH Rensselaer Polytechnic Inst. Texas Instruments MCNC Hewlett Packard AT&T Bell Laboratories Hewlett Packard MCNC consultant IBM North Carolina State Univ. Xerox PARC

We would also like to thank all of the authors for making this symposium possible by sharing their latest results and putting considerable effort into the preparation of the camera-ready manuscripts. John Andrews George Celler May 1991

iv

TABLE OF CONTENTS Preface

iii DEVICE STRUCTURE AND TECHNOLOGY

*Device Design and Process Optimization of Sub-Half Micron CMOS Technology, K.-Y. Chiu, D. Peters, and M. Kakumu

1

*Advanced Deep-Submicron BICMOS Technology, K. Shimohigashi

5

A P+ Poly-Si Gate with Nitrogen-Doped Poly-Si Layer for Deep Submicron PMOSFETS, S. Nakayama

9

Super SILO/RTN: Quasi-Recessed Field Oxide and 80 nm Bird's Beak Using a SILO/RTN Process, P. Molle and S. Deleonibus

17

Advanced Processes to Increase the Effective Storage Area of Stacked DRAM Cells, P. C. Fazan, H. C. Chan, Y. C. Liu, A. Ditali, C. H. Dennison, H. E. Rhodes, V. Mathews, and T. A. Lowrey

26

SUB-MICRON DEVICE AND PROCESS MODELING *Point Defect Based Modeling of Dopant Diffusion in Silicon, M. E. Law

34

*Simulation of ULSI Device Effects, M. R. Pinto

43

Non-Equilibrium Diffusion Process Modeling Based on Three-Dimensional Regulated Point-Defect Injection and in-situ TEM Observation, T. K. Okada, S. Onga, H. Kawaguchi, S. Kambayashi, I. Mizushima, J. Matsunaga, and K. Yamabe

52

*Invited

V

Simulation of Metal "Cone" Formation in a Tri-Layer Liftoff Process, M. D. Kellam, W. B. Rogers, R. W. Sayer, and R. C. Chapman

61

Use of Simulation for Rapid Design Prototyping, G. Chin and M. E. Law

78

SUBMICRON FEATURE PATTERNING: LITHOGRAPHY *X-Ray Lithography at IBM, R. W. Hill and J. R. Maldonado

88

*An Adaptive Neural Network for Computation of ProximityEffect Corrections, R. C. Frye, E. A. Rietman, and K. D. Cummings

101

*The Chemistry and Process Characteristics of Chemically Amplified Positive Resist Materials, 0. Nalamasu and A. E. Novembre

110

A 0.4 pum CMOS Test Circuit Completely Processed with 8-Level X-Ray Lithography, D. Friedrich, W. Windbracke, H. Bernt, G. Zwicker, P. Staudt-Fischbach, H. J. Schliwinski, P. Hemicker, P. Lange, and M. Pelka

120

A 0.5 Micrometer CMOS Process Based on a 248 nm Excimer Laser Stepper, M. D. Kellam, S. Goodwin-Johansson, S. Jones, B. Dudley, and C. Peters

131

Deep UV Lithography of Monolayer Films with Selective Electroless Metallization, J. M. Calvert, M.-S. Chen, C. S. Dulcey, J. H. Georger, M. C. Peckerar, J. M. Schnur, and P. E. Schoen

145

Silylated Acid Hardened Resist Processing for Submicron Deep UV Lithography, E. K. Pavelchek, J. F. Bohland, P. W. Freeman, S. K. Jones, and B. W. Dudley

155

Pitch and Line Width Measurements in Scanning Probe Metrology, J. E. Griffith, M. J. Vasile, G. L. Miller, E. R. Wagner, E. A. Fitzgerald, D. A. Grigg, and P. E. Russell

164

*Invited

vi

Extending a 0.35 NA h-Line Stepper to 0.8 Micrometer (1.6 Micrometer Pitch) CMOS Technology Using Trilayer Templates and Halo LDD Devices, K. W. Markus, S. Goodwin-Johannson, W. B. Rogers, and W. C. Donaldson

174

A Charge-Reducing Process Using a Charge Transfer Complex in Electron Beam Lithography, K. Yano, T. Maruyama, and K. Kobayashi

183

Characterization of a New Submicron I-Line Photoresist, L. N. Nguyen, J. R. Johnson, G. J. Stagaman, and W. Y. Hata

190

A Comprehensive Performance Evaluation of I-Line Resists for Submicron CMOS Technology, G. J. Stagaman, N. S. Thane, J. R. Johnson, L. N. Nguyen, and W. Y. Hata

199

SUBMICRON FEATURE PATTERNING: ETCHING *Time Modulated Plasma Etching, S. C. McNevin

206

Super-ECR Plasma Etching Technology for 64Mbit DRAM, S. Samukawa

216

Highly Controllable SiO2 Etching Technology by Vapor HF/H2 0 System, S. Onishi, K. Matsuda, and K. Sakiyama

226

Anisotropic Etching Process of n+-Polysilicon with Chlorine and Nitrogen Mixed ECR Plasma, T. Matsuura, H. Uetake, T. Ohmi, J. Murota, and S. Ono

236

Low Temperature Etching of Organic Photoresist with an Electron Cyclotron Resonance System, W. Varhue, J. Burroughs, and W. Mylnko

244

SHALLOW JUNCTIONS AND OHMIC CONTACTS *Silicided Shallow Junctions for ULSI, K. Maex, L. P. Hobbs, and W. Eichhammer

254

*Invited

vii

*Formation of Shallow Boron-Doped Layers Using Preamorphization and its Application to MOSFET Fabrication,M. Miyake

266

Ohmic Contact Formation to Shallow Junctions by Selective Titanium Silicide Chemical Vapor Deposition, K. Saito, T. Amazawa, and Y. Arita

276

Defect Annealing in Ultra-Shallow Junctions for Scaled Sub-Micron CMOS Technology, S. Chevacharoenkul, C. M. Osburn, and G. E. McGuire

285

Ultra-Shallow Junction Formation by Diffusion from Polycrystalline SixGel-x Alloys, D. T. Rider, M. C. Oztuirk, and 1. J. Wortman

296

Enhanced Silicide Formation Using Selective Epi Growth on Source/Drain for Deep Submicron CMOS, L. K. Wang, D. Moy, J. A. Ott, and T. S. Kuan

305

Optimization and Characterization of LPCVD TiB2 for ULSI Applications, C. S. Choi, G. A. Ruggles, C. M. Osburn, and G. C. Xing

310

Ideal Metal/Silicon Contact Formation by Clean-Nitrogen-Seal Processing,H. Kuwabara, M. Otsuki, and T. Ohmi

321

Junction Formation for Scaled Sub-Micron CMOS Technology, C. M. Osburn, S. Chevacharoenkul, and G. E. McGuire

330

Stability of TiB2 as a Diffusion Barrier on Silicon, C. S. Choi, C. C. Xing, G. A. Ruggles, C. M. Osburn, A. S. Shah, and J. D. Hunn

343

THIN GATES *Polarity Effects Associated with Wearout and Breakdown in Thin Silicon Oxide Films, D. J. Dumin, J. R. Cooper, K. J. Dickerson, N. B. Heilemann, and P. A. McAllister *Invited

viii

353

*UltrathinMOS

Gate Dielectrics Fabricated by RTP and RTP-CVD, D. L. Kwong, G. Q. Lo, and W. Ting

363

Integrity of Lightly Nitrided Oxide as the Gate Dielectric for 0.5 pm CMOS Devices, D.-G. Lin, J. A. Yasaitis, and C. H. Chiacchia

374

Reliability of Thermally Grown Thin SiO 2 for ULSI Applications, Y. L. Chiou, G. Li, C. H. Sow, J. P. Gambino, and P. J. Tsang

382

Breakdown Characteristics of 0 2 -Diluted and RTO Thin Si0 2 Films, L. Fonseca and F. Campabadal

391

Effects of Si Wafer Surface Micro-Roughness on Electrical Properties of Very Thin Gate Oxide Films, M. Morita, A. Teramoto, K. Makihara, T. Ohmi, Y. Nakazato, A. Uchiyama, and T. Abe

400

Dielectric Breakdown Strength Analysis of SiO 2 Using a Stepped-Field Testing Method, E. A. Sprangle, J. M. Andrews, and M. C. Peckerar

409

Top-Oxidation Effects on the Reliability of Oxide-Nitride-Oxide (ONO) Stacked Film, K. Yoneda, T. Ishida, Y. Todokoro, and M. Inoue

421

Thin Gate Oxide Integrity in Fluorinated MOS Structures, W. M. Greene, T. E. Kopley, and 0. S. Nakagawa

431

Electrical and Structural Properties of Ultrathin Si0 2 Gate Dielectrics Prepared Under Various Conditions, P. Lange, L. Schmidt, M. Pelka, P. Hemicker, H. Bernt, and W. Windbracke

445

Correlation of Metal Impurity Content of ULSI Chemicals and Defect-Related Breakdown of Gate Oxides, M. Meuris, M. Heyns, W. Kuiper, S. Verhaverbeke, and A. Philipossian

454

*Invited

ix

PROCESS-INDUCED DAMAGE AND CONTAMINATION

*Process-Induced Ionizing Radiation Effects in MOS Devices, T. P. Ma

464

Charge Sharing "Antenna" Effects for Gate Oxide Damage During Plasma Processing, S. Fang, A. M. McCarthy, and J. P. McVittie

473

Effects of Process-Induced Damage on 115 A Thin Gate Oxides and Their Removal by Low Temperature Passivation, S. Kar, A. Pandey, A. Raychaudhuri, and S. Ashok

483

Radiation-Induced Neutral Electron Trap Generation in Electrically Biased IGFET Gate Insulators, M. Walters and A. Reisman

493

RAPID THERMAL PROCESSING *Advanced Equipment and Sensor Technologies for Rapid Thermal Processing, M. M. Moslehi, H. Najm, L. Velo, R. Yeakley, J. Kuehne, B. Dostalik, D. Yin, and C. J. Davis

503

*Review of Process and Equipment Issues in RTP, J. J. Wortman, J. R. Hauser, M. C. Oztiirk, and F. Y. Sorrell

528

Principles of Wafer Temperature Measurement Using in situ Ellipsometry, H. Z. Massoud, R. K. Sampson, K. A. Conrad, Y.-Z. Hu, and E. A. Irene

541

Factors Affecting the Economic Performance of Cluster-Based Fabs, S. C. Wood and K. C. Saraswat

551

Single-Wafer Rapid Thermal CVD Technology for Fabrication of MOS and Bipolar Devices, A. Kermani, F. Wong, and K. E. Johnsgard

566

Simultaneous Measurement of Wafer Temperature and Native Oxide Thickness Using in situ Ellipsometry, R. K. Sampson and H. Z. Massoud

574

*Invited

x

A Cylindrical Tube Based Rapid Thermal Processor, D. T.

Chapman, J. M. Melzak, M. J. Fordham, J. J. Wortman, M. C. Oztiirk, and F. Y. Sorrell

582

PLANARIZATION TECHNIQUES

*Dielectric PlanarizationProcess for ULSI, C. H. Ting

592

*Overview of Planarization by Mechanical Polishing of Interlevel Dielectrics, S. Sivaram, R. Leggett, A. Maury, K. Monnig, and R. Tolles

606

Advanced Dielectric Techniques for the Fabrication of 16 Megabit DRAM Generation Devices, B. Ahlburn, R. Nowak, M. Galiano, and J. Olsen

617

Excimer Laser Assisted Planarizationfor ULSI Metallization, G. S. Sandhu, C. Yu, and T. T. Doan

627

Effect of Barrier Material on Excimer Laser Planarization of AICu, H. Chu, E. Ong, S.-Q. Wang, and 1. Raaijmakers

635

Application of a Spin-On-Glass Planarization Process to Submicron Triple Metal Technology, S. Morimoto, S. Queller, R. Gasser, and J. Kronschnabel

642

Oxide-Filled Trench Isolation Planarized Using Chemical/Mechanical Polishing, J. M. Pierce, P. Renteln, W. R. Burger, and S. T. Ahn

650

THOMAS D. CALLINAN AWARD ADDRESS Review of Thin Oxynitride Dielectrics for Memory Device Technology, V. J. Kapoor

657

*Invited

Xi

INTERCONNECT AND PACKAGING

*An Overview of Polyimide Use in Integrated Circuits and Packaging,R. M. Geffken

667

*Materialsand Packaging for Optical Interconnects: Status and Challenges, L. D. Hutcheson

678

Properties of PECVD 0 2/TEOS Silicon Dioxide, W. J. Patrick, G. C. Schwartz, J. D. Chapple-Sokol, K. Olson, and R. Carruthers

692

Electrochemical Effects of HF on Polyphenylquinoxaline Polymer Used in the Fabrication of PPQICu on Si Multilayer Interconnection Modules, F. Templier, J. Torr6s, A. Halimaoui, J. Palleau, and J. C. Oberlin

712

Gap-Fill with PECVD Silicon Dioxide Using Deposition/Sputter-Etch Cycles, G. C. Schwartz and P. Johns

720

Magnetron-Enhanced Etching of Double-Level Tungsten Interconnect, R. Hsu, C. Y. Fu, and B. Law

730

Selective Electroless Metal Deposition for Via Hole Filling and Conductor Pattern Formation in VLSI Multilevel Interconnection Structures, V. M. Dubin

739

WAFER CLEANING AND OXIDATION Novel Method for Prevention of Particle Deposition in Wet LSI Processes, A. Saito, K. Ohta, Y. Takahara, and H. Oka Low-Temperature in-situ Native Oxide Removal Using Anhydrous Hydrogen Fluoride, P. P. Apte, K. C. Saraswat, M. M. Moslehi, and R. Yeakley Low Temperature Oxidation of Silicon in an Electron Cyclotron Resonance Plasma, D. A. Carl and D. W. Hess *Invited

xii

749

755 765

Characterization of Stress Distribution in Submicron Isolation Structures by Micro-Raman Spectroscopy and Correlation with Transmission Electron Microscopy, I. De Wolf, J. Vanhellemont, A. Romano-Rodriguez, H. Norstr6m, and H. E. Maes

775

THIN FILM DEPOSITION A Manufacturable in-situ Doped Polysilicon Process for 16-64M Bit DRAM Technology, D. E. Bailey

785

Diffusion Behaviour of Dopants in Polycrystalline Silicon Electrode for Ultra High Speed Bipolar Devices, H. Yamaguchi and N. Owada

793

A New Polysilicon Texturization Technique Using Excimer Laser Processing, V. K. Mathews and C. Yu

800

As-Deposited Rugged Polysilicon for 16 and 64 Mbit DRAM Cells, V. K. Mathews, P. C. Fazan, and A. Ditali

810

Experimental Verification of a Fundamental Model for Multiwafer LPCVD of Polysilicon, T. A. Badgwell, T. F. Edgar, I. Trachttenberg, and J. K. Elliott

820

Low-Temperature Silicon Epitaxy without Substrate Heating by Ultraclean ECR-Plasma-Enhanced CVD, K. Fukuda, J. Murota, S. Ono, T. Matsuura, H. Uetake, and T. Ohmi

834

LPCVD of Silicon Dioxide Below 500 °C by Pyrolysis of Diethylsilane in Oxygen: A Safe Alternative to Silane, J. D. Patterson and M. M. Oztuirk

841

Optimization of Process Conditions for Selective Deposition of Polycrystalline SiGel-x Alloys in a Rapid Thermal Processor,M. Sanganeria, M. C. Ozturk, G. Harris, D. M. Maher, D. Batchelor, J. J. Wortman, B. Zhang, and Y. L. Zhong

851

xiii

MISCELLANEOUS PROCESSING ISSUES UV Annealing Passivation Effect on Sodium (Na+) Contamination, M. Itsumi, H. Yoshino, S. Nakayama, H. Akiya, and S. Muramoto

861

Variation of Surface and Interfacial SiO 2 Layers During Thermal Process, L. Ling and F. Shimura

870

Enhanced Degradation in Germanium Implanted PMOSFETs, L. P. Hobbs, A. von Schwerin, and K. Maex

880

xiv

FACTS ABOUT THE ELECTROCHEMICAL SOCIETY, INC. The Electrochemical Society, Inc., is a nonprofit, scientific, educational, international, individual membership organization founded for the advancement of the theory and practice of electrochemistry, electrothermics, electronics, and allied subjects. The Society was founded in Philadelphia in 1902 and incorporated in 1930. There are currently over 5000 scientists and engineers from more than 40 countries who hold individual membership; the Society is also supported by more than 100 corporations through Benefactor, Patron, and Sustaining Memberships. The technical activities of the Society are carried on by Divisions and Groups. Local Sections of the Society have been organized in a number of cities and regions. Major international meetings of the Society are held in the Spring and Fall

of each year. At these meetings, the Divisions and Groups hold general sessions and sponsor symposia on specialized subjects. The Society has an active publications program which includes the following. JOURNAL OF THE ELECTROCHEMICAL SOCIETY The JOURNAL is a monthly publication containing technical papers covering basic research and technology of interest in the areas of concern to the Society. Papers submitted for publication are subjected to careful evaluation and review by authorities in the field before acceptance, and high standards are maintained for the technical content of the JOURNAL. EXTENDED ABSTRACTS - Extended abstracts of the technical papers presented at the Spring and Fall Meetings of the Society are published in serialized softbound volumes. PROCEEDINGS

VOLUMES

-

Papers

presented

in

symposia at Society and Topical Meetings are published from time to time as serialized softbound Proceedings Volumes. These provide up-to-date views of specialized topics and frequently offer comprehensive treatment of rapidly developing areas. MONOGRAPH VOLUMES - The Society has, for a number of years, sponsored the publication of hardbound Monograph Volumes, which provide authoritative accounts of specific topics in electrochemistry, solid state science and related disciplines.

Xv

DEVICE DESIGN AND PROCESS OPTIMIZATION OF SUB-HALF MICRON CMOS TECHNOLOGY Kuang-Yi Chiu, Dan Peters and Masakazu Kakumu Silicon Process Lab Circuit Technology R&D Hewlett Packard Company 3500 Deer Creek Road, Palo Alto, CA 94304

The device structure and process design optimization for realizing high performance and reliable sub-half micrometer CMOS devices will be discussed. As MOS device dimensions are scaling down to below 0.5 micrometer, optimization between performance and reliability becomes a must in choosing the right device structure, device design, and power-supply voltage. This paper addresses the trade-off between performance and reliability at both room temperature and low temperature operation, and solutions appropriate for fabricating ULSI circuits with sub-half micrometer CMOS devices. INTRODUCTION The two major technological driving forces that continue to propel the IC industry are the ability to scale feature sizes to enhance circuit packing density and the ability to further improve device performance by maintaining a constant powersupply voltage from the 64K DRAM to 4M DRAM technology generations. With the increase in scale of integration and the decrease of device dimensions to below 0.5 micron, the constant voltage scaling scenario, which the VLSI industry has employed in the past decade, is now encountering many physical limitations, especially the difficulties in maintaining the reliability of gate insulators and the hot carrier degradation of devices. The other limitation imposed on sub-half micron ULSI circuits is the significant increase in current density needed, which will cause electromigration problems in submicrometer interconnect line and contact holes. To overcome these fundamental limits encountered by the scaling into the sub-half micron regime, a comprehensive study in device design, process technology, and its operation environments are needed in order to make the best use of further scaled CMOS devices. In this paper, the relationship between device, structure, power-

I

supply voltage, device operation temperature, and fabrication process is examined especially for sub-half micron CMOS technology generations. DEVICE DESIGN OPTIMIZATION For many VLSI technology generations, power-supply voltage has been maintained at 5 volts for actual CMOS VLSIs in order to achieve higher circuit performance and maintain TML compatibility. This constant voltage scaling has been achieved with many device structure modifications, such as double diffused drain (DDD) and lightly doped drain (LDD) etc.. However, as MOS device geometries are scaling down to 0.5 um or below, reliability problems caused by hot carrier injection, oxide breakdown, gate-induced leakage and overall power dissipation concerns have made the reduction of power-supply voltage a necessity. However, the drive to continue increasing circuit performance places other demands on device design. The most important issue in the sub-half micron CMOS device design is an appropriate choice of a power-supply voltage to address the fundamental trade-off between performance and reliability of CMOS circuits. It has been observed that a higher power-supply voltage cannot always provide high-speed operation for circuits with below 0.5 um geometries, because higher electric field and impurity concentration could cause mobility degradation, increase in parasitic capacitance, and many other degradation effects. Optimization of device design with appropriate choice of power-supply voltage is critical for developing sub-half micron CMOS technology. Fig. 1 summarizes results obtained for an optimized power-supply voltage and process/device parameters selected by simulation for 0.2 um, 0.3 um and 0.5 um CMOS devices at both room temperature [11 and low temperature [2]. Physical Dimension of Poly Length Power-Supply Voltage M Gate Oxide Thickness inm) Threshold Voltage of nMOSFET M Threshold Voltage of pMOSFET M 3 Surface Impurity Concentration (cm- ) 3

Bulk Impurity Concentration (cm- ) Transconductance (mS/mm) of nMOSFET Transconductance (mS/mrn of pMOSFET Delay time with F1O II (ps/stage) Delay time with F/O = 3 (pa/stage)

0.2 lam

0.5 grm

1.4 (2.4) 6.5 (8.0) 0.18 10.53) 0.20 0.55) 5.3E16/5.3E16

2-0 (3.2) 10.5 (11.5) 0.21 (0.56) 0.22 (0.58) 2.3E16/2.3E16

2.8E17 InMOS13.3E17 (pMOS) 542 (298) 303 (169) 21.8 (37.4) 56.3 (79.3)

1.3E1719.gE16 286 (202) 155 (104) 30.5 (49.7) 75.0 (106.4)

5.8E1614.9E16 197(145) 106(72.2) 38.2 (70.9) 93.2 (156.8)

Delay time with F/O = 3. At 2mm (ps/stags) Power Density (s.u)

SNote:

0.3 pm

1.0 (1.7) 4.5 (5.0) 0.15 4D.39) 0.16 43.42) 2.0E17 CnMOSI2.1E17 (pMOS)

Off current criterion for RT -0.2gm

82.7 (120.7)

114.4 (173.4)

0.92 (1.23)

0.99 (1.15)

158.5 (276.2) 1(1)

Is lOpA/ pm

Fig. 1. A simulated optimum power-supply voltage and process/device parameters for sub-half micron CMOS at room [1] and 77 K [2] temperatures. Room temperature dates In parentheses.

2

It should be noticed that for a chosen optimum power-supply voltage at each technology generation, other process parameters such as gate oxide thickness, impurity concentrations and source/drain junction structure are changed to achieve the highest circuit performance and maintain its circuit reliability. PROCESS DESIGN OPTIMIZATION With the progress that has been achieved in lithography techniques, optical lithography will provide the manufacturing capability for continual down scaling. However, as we crossed into the sub-half micron era, conventional device structure and fabrication techniques reached their physical limitations. Therefore, it is necessary to develop new structures or use new materials to overcome key performance and reliability limitations, such as the parasitic resistance and capacitance, the sub-half micron contact etch and fill and interconnect RC delays, etc.. Fig. 2 shows the CMOS/VLSI process evolution that has happened from 1.8 to 0.5 micron generation and predicts what will be needed in the sub-half micron generations. Technology

Generation 1.8 urn

Isolation

Gate rnter.l

Material Well

Technology

dielectrics

Junction Structure

N or P well

LOCOS

N-polyloxide

N+/P+

Contact and [interconnect Via structure metal Wetetched tapered contact

Al-Si

Power Supply Voltage

5.0 V

N-polyloxide polycde

5.0 a Dry etched LOCOS DDD Al-Si 1.2 urn N or P well slopedcontact n-LDD Dry etched 5.0 v 0.8 urn Twinwell/ EPI ModifiedLOCOS N-polyloxide SALUCIDE sloped contact AI-SI Cu/TiW Vertical contact n& pLDD I EPf Twin well Modified LOCOS N-polyfoxede 0.5 urn TiN/Al-Cu/TiN 3.3 / 5.0 v SALICIDE with W plug Retrode grade Shallowtrench N and PFrameless cent GOLD/N+/P0.35 urn well I EPI Poly/oxide SALICIDE Via with W plug TiN/AI-Cu/TiN 2.5 13.3 v Shallowand ITUNAI-Cu/TiN Retrode grade 0.25 um N &P poly/ON(GOLDNI/P- Stackedcontacl wellI EPI Deep trench ?7?????? SALICIDE??fl withW plug or Cu/TiN??? Retrode grade Shallowand Cu/TiN???? or 0.15 urn Ref.retaT??/ welVEPIor SO0 Deep trench Hi-Tc sup.???? Fig. 2.

CMOS VLSIIULSI process technology trend

Some of the emerging technologies such as isolation, LDD with shallow junction structure, self-aligned silicide, local interconnect and self-aligned contact structures for sub-half micron ULSI will need significant improvement to comply with the device down scaling. Multilevel interconnect technology will perhaps undergo the 3

most significant changes in the sub-half micron era. All sections of interconnect technology require major improvement in the future that includes: Metal material structure, dielectric deposition and global planarization, non-enclosed contacts as well as the etch and fill of sub-half micron contacts. CONCLUSION As technology drives toward sub-half micron generation and beyond, many device structural changes are required in order to continue improving circuit performance and density, and to maintain reliability goals. Trade-off between performance and reliability needs to be understood for selecting an optimum powersupply voltage and the associated device structure and its process technology to fabricate a high performance and reliable ULSI circuit. REFERENCES 1. M. Kakumu, M. Kinugawa and K. Hashimoto, IEEE Trans. on Electron Devices, vol. Ed- 37, p. 1334, 1990. 2. M. Kakumu, D. Peters, H.Y. Liu and K.Y. Chiu, in IEDM Tech. Dig., paper no. 9.1, December, 1990.

ADVANCED DEEP-SUBMICRON BICMOS TECHNOLOGY Katsuhiro Shimohigashi, Central Research Laboratory, Hitachi Ltd. 1-280 Higashi-Koigakubo, Kokubunji Tokyo 185, Japan This paper will overview the deep-submicron BiCMOS tehchnology in the 1990's from the process, device, and circuit point of views. Critical design issues, such as the MOS-bipolar performance optimization, the isolation technology, the metal layer design, and the process modulalrity, are described and the future device development direction will be shown. In addition, our experimental half-a-micron BiCMOS technology will be presented, as an example. INTRODUCTION Since the introduction of BiCMOS technology to Large-Scale Integrated circuits, it has been used for a variety of products throughout the 1980', with the device feature size of 3.0-1.0 Jim. Although BiCMOS technology has the advantage compared to CMOS and bipolar technologies as shown in Fig. 1[11, scaling down to the deep-submicron range is said to be rather difficult, because both bipolar and MOS devices should be scaled simultaneously. The purpose of this paper is to describe the deep-submicron BiCMOS technology in the 1990's, showing our experimental half-a-micron BiCMOS technology as an example. INTEGRATION TREND Figure 2 shows the trend of the integration density versus the device feature size [2]. The density has been increasing four times in every three years, which is just as same as the MOS memory density trend. In the middle of the 1990's, one hundred million devices will be integrated on a single chip with the device feature size of 0.3tim. Its impact is so large that the middle to large computers could be integrated on a chip. DEEP-SUBMICRON BICMOS DEVICE DIRECTION Although, there are two types of device structures, costoriented CMOS based one and performance-oriented bipolar based one, the discussion hereafter will mostly deal with the performance 5

oriented BiCMOS technology. There are a number of issues for realizing the deep-submicron BiCMOS. These include, 1) the optimum design between bipolar and MOS device parameters, 2) high performance bipolar and MOS structures, 3) the isolation technology, 4) the number of metal layers and materials, 5) low voltage device and circuit designs, 6) the device and metal reliability, and 7) the modular process design.

108 Z

0

1o

7

'2

Slo6 aO5

m

i I I

3

I

I

2 1.3

I

I

I

0.8

0.5

0.3

Device Feature Size (gim) Fig. 1 Performance Comparison.

Fig. 2

Device Integration Density vs. Device Feature Size.

The optimum design between the bipolar and MOS performance is the key to the device design, as shown in Fig. 3. The fT of the bipolar device should be increased linearly to the scaling factor K to achieve the best performance of the BiCMOS gate circuit [3].In the deep submicron regime, the fT of larger than 20GHz will be necessary, leading to the necessity of the self-aligned bipolar structure. As the supply voltage will be reduced lower than 5V, MOS devices should also be designed carefully. Although the current capability enhancement by the drain engineering and the channel doping profile control is most important, the reduction of the source/drain resistance and capacitance should be considered at the same time. The silicidation technology will become important. For applying to the very high-speed ECL circuits, the reduction of the collector-substrate capacitance Ccs of the bipolar device is critical. The trench isolation technique should be used. 6

Although the required number of metal layers will depend on a particular application, at least three layers will be necessary for realizing complex digital functions in the 1990's. As will be apparent from the above discussion, the application of BiCMOS technology is expected to be quite wide, the costperformance or the process complexity versus the performance should better be traded-off in each application. The process modular design will become the most important leverage to realize the versatility of BiCMOS technology. Figure 4 shows a design device structure[3]. S50

-P---BMOS

(3 ..•20 0~

St10 K1

-

U2

I

0 0.3

I 0.5

0.8

I

I

1.3

2

Device Feature Size (grm) Fig. 3

ample of the half-a-micron BiCMOS

-

POLARE-

l

3

Fig. 4

fT versus Device Feature Size.

Cross-sectional View of 0.5 jPm BiCMOS Structure.

LOW VOLTAGE DEVICE AND CIRCUIT The low voltage BiCMOS gate development has been paid much attention in these days[4] and it will greatly affect the device structure. The conventional BiCMOS gate(Fig. 5(a)) can not be used with the supply voltage of less than 3.5-4.OV because of the combined voltage drop, Vth +VBE, as shown in Fig. 6. For the low voltage operation, the BiNMOS gate(Fig. 5(b)) and the complementary BiCMOS gate (Fig. 5.(c)) are likely to be the candidates. The CBiCMOS gate has an advantage of the lower voltage operation down to 2-2.5V. However, an additional PNP bipolar device is required, resulting in the increase in the process complexity. Therefore the coupling between the process and circuit design will become much more important in the future BiCMOS technology development.

7

(a)BiCMOS

(b)BiNMOS

(c)CMeMOS

R

{3 02

V

0

•

U

"1 ADDITIONAL 0 NO ISOLATION

NO PROCESS

.

.

S

.

2 V 3

.

4V

.

V)5

Supply Voltage Vs (V)

FOR BIPOLAR

Fig. 6

Fig. 5 BiCMOS Gate Circuits.

Gate Delay Time vs. Supply Voltage.

CONCLUSIONS We have reviewed the design issues for the advanced deepsubmicron BiCMOS technology and showed a future device development direction, showing our experimental half-a-micron BiCMOS technology as an example.

REFERENCES [1] [2] [3] [41

M. Kubo, "Perspective to Bi-CMOS VLSIs", Symp. on VLSI Circuits, pp89-90, May, 1987. K. Miyata, "BiCMOS technology overview", in '87 IEDM Short Course "BiCMOS Technology", A. Watanabe et al, "Future BiCMOS technology for scaled H. J. Shin, "Full-swing logic circuits in a complementary BiCMOS technology", Symp. on VLSI Circuits, pp89-90, June

1990.

8

A P+ POLY-Si GATE WITH NITROGEN-DOPED POLY-Si LAYER FOR DEEP SUBMICRON PMOSFETS Satoshi Nakayama 3-1,

NTT LSI Laboratories, Morinosato Wakamiya, Atugi-si, Kanagawa, 243-01, Japan

thin A new P+ polysilicon gate with a very layer at the polypolysilicon nitrogen-doped silicon gate/SiO2 interface is proposed for deep submicron PMOSFETs. This nitrogen-doped silicon boron penetration layer effectively suppresses through the ultra-thin oxide into the silicon A thin nitrogen-doped silicon layer substrate. of about (5 nm) with a nitrogen concentration 1x10 2 1 cm- 3 gives a process margin of about 50'C during heat-treatment after the formation of the gate electrode. This suppression of boron decrease in boron penetration is due to a diffusivity in the nitrogen-doped silicon layer. INTRODUCTION have been Over recent years, P+ polysilicon gates in suggested to fabricate surface-channel PMOS devices surfacedeep submicron regions[l,2]. This is because buried channel PMOS devices are superior to conventional in respect to both short channel channel PMOS devices characteristics and turn off characteristics. However, P+ polysilicon gates are disadvantaged by unstable threshold voltages. This is due to penetration of boron from the into the channel region through the gate oxide boron-doped polysilicon gate. This penetration of boron wet 02 ambient conditions is accelerated by annealing in or H2 ambient conditions, or by fluorine incorpolating into implantation[3,4,5]. the gate electrode, a result of BF 2 The issue of boron penetration becomes more serious as gate a new oxide thickness is reduced. This paper proposes supresses boron polysilicon gate that effectivily penetration through the ultra-thin gate oxide. SAMPLE PREPARATION and The new polysilicon gate consists of a boron-doped a nitrogen-doped double layer. The nitrogen-doped silicon

9

layer was deposited onto the gate oxide at about 510 O by LPCVD (low chemical

2 z

"

pressure vapor

deposition) with

a

Si 2 H 6 -NH 3 gas system. Then, without any breakin processing, the boron-doped silicon

layer was deposited onto the nitrogendoped silicon layer at the same of temperature 510*C with a

Si

2 H6

-

o

z

9

8 z w

•

R m 1io7

010-

I0-

z

P,4 , (atm) Fig.I

Dependence of depositon rate and

B2 H6 gas system[6]. nitrogen concentration in nitrogen-doped silicon on NH3 partial pressure. the Figure 1 shows dependence of deposition rate and nitrogen concentration on the partial pressure of NH3 . Here, nitrogen concentration(CN) was determined by secondory ion mass spectroscopy (SIMS). Deposition rate decreases slightly with NH3 partial pressure increases. Also, nitrogen concentration is in almost direct proportion to increases in NH3 partial pressure. The characteristics of MOS diodes fabricated on P-type substrates (5 Pcm) with the new polysilicon gate were evaluated. The total thickness of the polysilicon gate was 300 nm and boron concentration of the boron-doped polysilicon layer was 2x10 2 0 cm- 3 . The thickness of the nitrogen-doped silicon layer in the polysilicon gate was about 5 nm estimated by deposition rate and deposition time. The thickness of the gate oxide determined by ellipsometory was 3.4-3.8 nm. MOS diodes were annealed to electrically activate boron atoms after definition of the polysilicon gate. During this heat-treatment, boron atoms diffuse into the nitrogen-doped silicon layer and the gate oxide. RESULTS AND DISCUSSION Effects of the nitrogen-doped silicon layer The flatband voltage (VFB) of the MOS diode with the new polysilicon gate was determined by its high-freqency C-V characteristics. Figure 2 shows typical highfrequency C-V curves of MOS capacitors whose structure is shown in the inset. For samples annealed in dry N2 ambient 10

conditions, the VFB of capacitors with nitrogendoped silicon layers of CN=O is

the This

almost

value.

boron

that

indicates

wet 02 increases

L-.. "a boronC"

50

•

-um

T0x-3.7nm ea ixl- 4cm 12

dry N2 . (AVFB)

,

(cm-3)

10 x14. ,

0 -1

compared These

0

j

0

GATE VOLTAGE (V)

annealed

with capacitors shifts

Anneal: 850eC,30rin Niog,,-do4 wet 02 Ply-Sl layer

- -----. dry N2

the same as

theoretical

penetration can be ignored if annealing at 850'C in dry N2 even when CN=O. dry Annealing at 8506C in N2 is, therefore, assumed not to cause any boron penetration regardless of CN of nitrogen-doped silicon layers. On the other hand, the VFB of capacitors annealed in in

100

VFB

Fig.2

Typical high-frequency C-V curves of the p+ polysilicon gate MOS capacitors. MOS capacitor structure is shown in inset.

are ascribed

to boron penetration into the substrate, The AVFB resulting from boron 0,5 penetration by annealing in wet 02 is shown in Fig. 3 0.4as a function of CN. Here, AVFB is the 0.3difference in VFB

Anneal: 850°C, 30min wet 02

>

between capacitor dry N 2 in annealed with and capacitor

the same CN annealed in wet 02. The AVFB decreases with

increasing CN UP to 3 21 cm-

of

beyond which

it

about lxl0 CN,

levels result that

off. This demonstrates the

nitrogen-

• >
1 J/cm 2 doses. They are very sensitive to deep-UV radiation with the addition of an onium salt or nitrobenzyl ester (covalent) PAG molecule. Process optimization efforts were concentrated on metal-ion-free and non-ionic PAG resist formulations. These resists exhibit 0.3 Jim resolution in 1 jim resist film at a sensitivity of 20-30 mJ/cm 2 with good process latitude. 115

REFERENCES [1]

J. V. Crivello, in "Polymers in Electronics", ACS symposium Series 242, Davidson, T. Ed., ACS, Washington, D.C., 1984, pp. 3-10.

[21

H. Ito and C. G. Willson, ibid, pp. 11-23.

[3]

E. Riechmanis, F. M. Houlihan, 0. Nalamasu, T. X. Neenan, Chemistry of Materials,accepted for publication.

[41

0. Nalamasu, M. Cheng, J. M. Kometani, S. Vaidya, E. Reichmanis and L. F. Thompson, Proc. SPIE, 1262, 32 (1990).

[5]

0. Nalamasu, E. Reichmanis, M. Cheng, V. Pol, J. M. Kometani, F. M. Houlihan, T. X. Neenan, M. P. Bohrer, D. A. Nixon, L. F. Thompson, C. Takemoto, Proc. SPIE, 1466, in print.

[6]

A. E. Novembre, W. W. Tai, 0. Nalamasu, J. M. Kometani, F. M. Houlihan, T. X. Neenan and E. Reichmanis, ACS Polymer Prints, 31 (2), 379 (1990).

[7]

A. E. Novembre, W. W. Tai, J. M. Kometani, J. Hansen, 0. Nalamasu, G. N. Taylor, E. Reichmanis, L. F. Thompson, Proc.SPIE, 1466, in print.

[8]

R. G. Tarascon, E. Reichmanis, F. M. Houlihan, A. Shugard, L. F. Thompson, Polym. Eng. Sci. 29, 850, 1989.

[91 T. X. Neenan, F. M. Houlihan, E. Reichmanis, J. M. Kometani, B. J. Bachman, L. F. Thompson, Proc. SPIE, 1086, 1, 1989. [10]

J. M. Kometani, 0. Nalamasu, E. Reichmanis, R. S. Kanga, L. F. Thompson, S. Heffner, J. Vac. Sci. and Technol. B, 8 (6), 1428, 1990.

[11]

M. J. Bowden, E. A. Chandross, J. Electrochem. Soc., 122, 1370, 1975.

[12]

T. X. Neenan, F. M. Houlihan, E. Reichmanis, J. Kometani, B. J. Bachman, L. F. Thompson, Macromolecules,23, 145, 1990.

116

TABLE I. Process Flow for Chemically Amplified Resists. Spin Coat Prebake Exposure Post-Exposure Bake Development Rinse TABLE IL Effect of Copolymer Molecular Properties on Lithographic Performance. Molecular Molecular Composition Weight Molecular (TBS:SO 2 ) Weight Dispersity T9 g/mole

Sensitivity (D,) x-ray

e-beam

deep-UV

(mr/cm 2 ) (jtC/cm2 ) (mJ/cm 2 ) 1.75:1 2.1:1 2.8:1 3.75:1 1:0

3.53 4.74 2.14 2.50 1.07

2.70 1.88 1.89 1.98 1.60

168 165 159 151

10 20 30 40 > 120 b

nd 60 80 100 >300c

nd -1000a nd nd >1500

aPEB conditions were 140'C/2.5 mins. b showed 3% thickness loss during exposure and lost no further thickness during PEB. CWas insoluble even with 300 pC/cm 2 dose. nd = not determined TABLE Ill. Process Capabilities of Deep-UV Resist. Thickness Uniformity Resolution Sensitivity Linewidth Control Exposure Latitude Focus Latitude Thermal Stability

3a < 20X 0.30 gtm line/spaces (in 1 gim film) 0.40 ptm contact holes 20-30 mJ/cm 2 < 0.05 gim (for 0.5 gim feature) ±13% for 10% CD (0.5 jim feature) ±0.75 jim for 10% CD (0.5 pim feature) _>140 0 C 117

-(CH-CH

2

)_--(SO

2

-

-- (CH-CH2),-(SO2-CH-CH ),2

CH-CH2 ),j-

H

# c=O I

t-BOC

C=O I

I

o

OH

OH

POLY (HYDROXYSTYRENE-SULFONE)

0I

PHSS

H3 C-C-CH3

H 3 C-C-CH3

/

I

CH3

Ph3 S +ASF- ONIUMSALT PHOTOACID GENERATOR

CH3

N_2

._

NITROBENZYL

(POLY(t.BUTOXYCARBONYLOXYSTYRENE-SULFONE) PTBSS

Scheme I.

x

CH2 -O-SIt 0

y

ESTER PHOTOACID GENERATORS

Schematic representation of a chemical amplification scheme based on poly(t-butoxycarbonyloxystyrene-sulfone) with onium salt and nitrobenzyl ester photoacid generators.

H

H O

H

I 1 I1 _CC--S_ 0

H 0

1

0

H

1 1 -C--C*

H

H

II .S_

I I C=C

l

0

0 6-

+ so2

7, X-ra0y 0o

. (H*)

I

Scheme II.

o

I 0

0

I (OH2)2 C

CI (at 2 )3

I (OH C 2 )2

I

E-beam and x-ray induced chain scission and acid generation in PTBSS copolymers.

118

Figure 1.

SEM picture of 0.30 jim line/space pairs in I jim thick resist exposed (dose-- 30 mJ/cm) at 248 nm using a GCA laserstep prototype deep-UV stepper with a NA = 0.35 lens and 5X reduction optics.

0.3 /im

Figure 2.

SEM picture of coded 0.4 gim line/space pairs in I pm thick resist exposed using an X-ray dose of (X = 14A) 25 mJ/cm 2.

COOED 0.4 Am LINE/SPACE

Figure 3.

CODED 0.25 um LINE/SPACE

119

SEM picture of coded 0.25 jim linelspace pairs in 1 gim thick resist exposed using an edose of beam 90 tC/cm 2 @ 30 kV.

A 0.4 gim CMOS TEST CIRCUIT COMPLETELY PROCESSED WITH 8-LEVEL X-RAY LITHOGRAPHY D. Friedrich, W.Windbracke, H. Bernt, G. Zwicker, P. Staudt-Fischbach, H.J. Schliwinski, P. Hemicker, P. Lange, M.Pelka Fraunhofer-Institut fOr Mikrostrukturtechnik (IMT) Dillenburger Str. 53, 1000 Berlin 33 Federal Republic of Germany Sub-0.5 lim CMOS devices have been successfully fabricated by means of X-ray lithography at all levels. This paper reports about the X-ray lithography characterization, the CMOS technology including electrical device performance and the influence of radiation induced damages on the transistor behaviour. The overlay of subsequent lithography levels was determined • 180 nm, 3 a with respect to X-ray mask copies with a mask distortion of 150 nm maximum. A linewidths variation in the poly-Si gate level of ± 50 nm could be achieved. The electrical devices have been characterized by static and dynamic measurements. NMOS and PMOS transistors exhibit no severe short channel effects for gate lengths down to 0.35 Ilm with a supply voltage of VD = 5 V.A stage delay time of 120 ps was measured at a 33 stage 0.45 ýim CMOS ring oscillator. Radiation damages have been evaluated by comparison of X-ray and optically processed transistors and reveal no drastical differences. INTRODUCTION The quarter micron CMOS generation probably will require X-ray lithography as a tool for pattern transfer in industrial mass production. For this goal four components have to be available: X-ray source, stepper, masks and resist. In general, the advantages of X-ray lithography compared to the optical lithography are, in addition to the resolution capability, the high depth of focus and the large exposure field size (10 cm 2). Contrary to this, the most critical point of this method is the mask in terms of pattern placement accuracy and defect density. Due to the technique of 1:1 shadow printing, the mask overlay requirement for a 0.25 g±m process is less than 100 rim, 3 a which has to be adjusted by an advanced stress engineering technique in the mask technology and a high precision stepper alignment. At the IMT in Germany, a state of the art X-ray lithography process has been established for test device fabrication on a laboratory scale with low integration density. Based on former developments of 4 level PMOS and NMOS processes /1,2/ a partially scaled 0.4 Vm CMOS process with 8 X-ray lithography levels was developed. 120

The primarily intention of our work is the evaluation of all X-ray lithography components in a complete CMOS process with regard to overlay and linewidths control. Furthermore, the influence of radiation induced damages on the device behaviour under the specific process conditions have been investigated. The process technology exhibits all features to fulfill the device requirements for a basic 0.4 gm CMOS process. No special emphasis was laid on advanced drain engineering for reduction of hot carrier effects. X-RAY LITHOGRAPHY All exposures have been carried out with synchrotron radiation in the spectral range of 0.8 ... 1.5 nm at the Bessy storage ring in Berlin. The mask wafer alignment was performed with a first generation stepper MAX 1 from Suss with an alignment accuracy of 150 nm, 3 a /3/. The X-ray masks used are X-ray copies of e-beam written master masks. Within the exposure field they consist of a 2 g±m highly B-Ge doped stress compensated Si membrane with electroplated 0.8 jam Au absorbers /4/. A positive tone, 3 component resist Ray/PF with chemical amplification from Hoechst company was used at all lithography levels /5/. The Ray/PF resist exhibits a high sensitivity of < 50 mJ/cm 2 , a resolution capability down to 0.2 lam and sufficient etch stability /6/. At all levels, the exposure time was approximately 30 sec per stepfield. Special emphasis was laid on the overlay and CD control. The overlay values measured on box in box patterns of subsequent lithography levels are listed in Table 1. They include all contributing error types, mainly mask distortions, alignment errors and linewidths variations and reveal _ 180 nm, 3 a at all levels. The pattern placement accuracy of the X-ray copies, which is the most contributing part of the overlay budged, has been determined to 150 nm maximum. With reduced influence on the overlay, a total linewidths variation of ± 50 nm could be achieved. A typical overlay diagram of the contact to Poly-Si gate level is shown in Fig. 1 with a deviation of 180 nm, 3 a within a 3 cm x 3 cm stepfield. Table 1:

Overlay values of subsequent lithography levels

Overlay

Lithography Level

mean (nm)

max m (nm)

LOCOS/P-Well

90

170

Poly-SI / LOCOS

85

160

Contact / Poly-Si

12C

180

Metal / Contact

10!

156

First results with the new Suss stepper XRS 200, which reproducible perform an alignment accuracy of 80 nm, 3 a, reveal an improved overlay of 160 nm, 3 a. A further improvement is expected by using master masks in121

stead of work copies. With a maximal master mask distortion below 120 nm and the XRS 200 alignment accuracy an overlay of about 140 nm, 3 cr could be realized.

Fig. 1:

Overlay diagram of the contact / Poly - Si level. The stepfield size is 3 cm x 3 cm DEVICE TECHNOLOGY

The process technology of the partially scaled 0.4 pgm CMOS process was developed at the IMT for evaluation of the X-ray lithography under realistic process conditions. An overview of the essential process steps is given in Table 2. Special interest has to focus on some process features, which distinctly influence the device performance. In order to improve the short channel behaviour of NMOS and PMOS transistors n+ and p+ poly gate technique was used, resulting in surface channel transistors for both types of devices. An appropriate channel doping concentration was realized by a dual channel implant for the p-well and nwell definition, leading to a retrograde doping profile. With a thermal budged reduction the junction depth of the p-well could kept below 1 gim. This technique allows to minimize the n+ - p+ spacing between LOCOS isolated different wells on 4 lim, under the condition of sufficient latch up hardness. The requirement of punch through reduction for channel lengths in the sub-0.5 tim range implies surface channel concentrations of approximately 2 x 1017 cm- 3 . This condition has been led to a gate oxide thickness of dox = 10 nm for a threshold voltage adjustment of VT = 0.7 V. The junction depth of the source/drain regions is in the order of 0.15 jim and 0.2 jim for NMOS and PMOS transistors, respectively. CoSi2 was used for the reduction of parasitic resistances down to 4 L/VE in the active areas and on p+ - n+ poly Si lines. A cross-section SEM picture, as shown in Fig. 2, demonstrates clearly the dimensions of a subhalf-pm transistor. 1Z2

Table 2: Essential CMOS technology steps

Lithography level

Critical dimension (Vm)

Process parameters

1. P-Well

>1

2. LOCOS

0.6

3. N-Well

>1

4. Poly-Si

0.4

5. P+

>1

6. N+

>1

As implant for source/drain and n+ poly-Si Tempering: 9000C, 30 min CoSi2 process

7. Contact

0.5

8. Metal

0.8

TEOS SiO 2 for isolation: 600 nm TiN thickness: 100 nm Al thickness: 800 nm Post metallization anneal: 4500C, 20 min

Dual boron implant for retrograde pwell Phosphorous field implant 0.5 Aim field-oxide thickness: Dual phosphorous implant for retrograde n-well Gateoxide thickness: 10 nm Poly-Si thickness: 250 nm TEOS spacer: 60 nm BF2 implant for source/drain and p+ poly-Si

Fig. 2: Cross-section of a 0.4 g~m NMOS transistor. The junction depth is about 0.15 jim.

123

DEVICE CHARACTERIZATION For the device characterization, both dynamic and static measurements have been performed. The 0.4 g±m NMOS and PMOS transistors behave according to the technology used in terms of static device characteristics, as depicted in Fig. 3. Transfer and drain curves exhibit sufficient short channel performance with punch through stability up to VD = 5 V and minor influence of DIBL (drain induced barrier lowering) effects in the sub-0.5 gIm channel lengths range. The use of Co salicidation technique introduces no additional drain leakage current in the n+ and p+ junctions.

PMOS

NMOS a

10-1

C

10-1 10-1

L.. U

0 ._o C

10-1

Gate Voltage VG (V) E

b

C. C

.5 L._ o

Drain Voltage Vo (V) Fig. 3:

Transfer (a) and drain characteristics (b) for NMOS and PMOS transistors with leff = 0.35 gIm

A threshold voltage decrease caused by DIBL was not observable for effective channel lengths down to 0.3 Wi under the measurement condition of VD = 50 mV. The slight increase of the n-channel threshold voltage, as demonstrated in Fig. 4, indicates a rise of the channel concentration near the source/drain regions, due to boron redistribution during the reoxidation process M/. The basic device parameters are summarized in Table 3. 124

Table 3: Electrical device parameters for NMOS and PMOS transistors

Process parameter

NMOS

PMOS

Effective channel length left (pm) / W = 10ln

0.35

0.35

Threshold voltage VT (V) measured with VD = 50 mV

0.79

-0.73

Subthreshold slope (mV/Dec)

92

93

Transconductance Triode: gm max (mS/mm)

15

3.5

Transconductance Saturation: gm sat (mS/mm)

160

78

Junction depth (gim)

0.15

0.2

4

5

Sheet resistance CoSi2 Rs (9n)/I

0.8

-0,8

0.6

-0.6

U)

0.2

-0.4 V[s r 50mV

0.2 ¢I-

Vas = -50mV

NMOS I

I

0.4

I

PMOS

-0.2 I

0.8

I

I

12

If

I

16

If

I

I

I

2.0

I

04

Effective Channel Length

I

G8

I

12

I

16

I

I

2.0

egf (pm)

Fig. 4: Threshold voltage characteristic for NMOS and PMOS transistors 125

The dynamic device behaviour was examined with a 33 stage ring oscillator. A non velocity optimized inverter delay time of 120 ps/stage was achieved for a ring oscillator with left = 0.45 gim and a supply voltage of VD = 5 V. As clearly demonstrated in Fig. 5, a performance improvement with decreasing channel lengths has been obtained, which is scaled reciprocal proportional by the channel lengths. A fully processed ring oscillator is shown in Fig. 6, which also exhibits the overlay capability of the last lithography level.

o

Supply Voltage V., (V) a

b

Fig. 5:

Ring oscillator frequency (a) and stage delay time (b) for two different effective channel lengths

Fig. 6:

Microscope picture of a fully processed CMOS ring oscillator with left = 0.4 lim. The contact hole sizes are 0.5 gIm with 1 jim distance to the gate edge. 126

RADIATION DAMAGE The influence of X-ray induced radiation damages on the device characteristic was investigated by comparison of X-ray and optically processed sub-0.5 lgm NMOS and PMOS transistors. Both types of devices have been processed identically within the same lot and were only been splitted to perform the X-ray and optical lithography, respectively. For the realization of sub0.5 g±m channel lengths with optical lithography, the resist stuctures in the gate level have been shrunk by isotropic 02 plasma etch. In order to ensure the similarity of the transistors compared, the effective channel lengths, the surface concentrations of channel dopants and the gate oxide thicknesses have been determined electrically by transconductance and C-V measurements [8]. Within the gateoxide of dox = 10 nm the absorbed X-ray dose is about 2.5 Mrad, calculated by the simulation program XMAS. The mechanism of the X-ray damage is caused by the absorption of X-ray photons with energies higher than the SiO 2 bandgap of 8.8 eV, which are able to create electron hole pairs. Charge separation with subsequent hole trapping can occur, due to the internal field across the gate oxide, caused by the work function differences for n+ and p+ poly - Si, respectively. The internal electrical field strength for NMOS and PMOS transistors amount about ± 0.9 MV/cm, resulting in a different hole trapping characteristic. For NMOS transistors the holes move to the SiO 2 - Si interface according the direction of the field vector, where deep hole traps are mainly located. In contrast, for PMOS transistors an opposite field direction across the gate oxide governs a hole motion to the Si0 2 - poly Si interface, with reduced hole trapping efficiency. These effects can be observed by VT comparison between X-ray and optical NMOS and PMOS devices, as demonstrated in Fig. 7. N.V0*

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,

Both, NMOS and PMOS transistors exhibit a negative VT shift of AVTp = 9 mV and AVTN = 51 mV, due to the different hole trapping efficiency, mentioned above. No significant difference in the interface trap density Dit could be observed in both cases, which can be explained by ADit annealing during the post metallization tempering at 4500C, 20 min. The influence of X-ray radiation on the long term stability was examined by hot carrier experiments. For this purpose, X-ray and optical transistors with sub-0.5 gim channel lengths have been stressed according to the following conditions:

Stress Condition

NMOS

PMOS

1000

1000

Stress drain voltage VD (V)

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128

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Dependence of hot carrier induced VT shift (AVT = AVT (0) - VT stress) on effective channel lengths for NMOS and PMOS transistors CONCLUSION

In this paper we have demonstrated the capability of X-ray lithography for CMOS device making in the sub-0.5 pm range with low integration density. For this purpose all X-ray components like masks, stepper and resist could be successfully applied in an entire 0.4 gm CMOS process. The current overlay results with 180 nm maximum are suitable for processes with 0.5 gm design rules. Further reduction of the overlay error down to 140 nm maximum can be realized by the application of master masks and the XRS 200 (Suss) stepper alignment, which will meet the overlay demands for the 64 Mbit DRAM generation. The CMOS technology used could ensure an adequate device performance in terms of static and dynamic transistor behaviour. Radiation induced damages, evaluated on NMOS and PMOS transistors reveal a VT shift of AVTN = 51 mV and AVTp = 9 mV, respectively. Long term stability, examined by hot carrier experiments exhibit no severe differences between both types of devices. These results are no limitation in terms of X-ray induced device degradation and are related to an absorbed X-ray dose of about 2.5 Mrad within a gate oxide of dox < 10 nm. ACKNOWLEDGEMENTS We would like to thank our colleagues from the X-ray lithography group for mask-making, K. Tomkowiak for the X-ray exposures and A. Kloor for performing the electrical measurements. This research was financially supported by the Bundesministerium fur Forschung und Technologie (Federal Ministry of Research and Technology) of the Federal Republic of Germany.

129

REFERENCES [1]

G. Zwicker, W. Windbracke, H. Bernt and D. Friedrich, Fabrication of 0.5 pm n- and p- type metal-oxide-semiconductor test devices using X-ray lithography, J. Vac. Sci. Technol. B7, 1642 (1989)

[2]

D. Friedrich, H. Bernt, H.L. Huber, W. Windbracke and G. Zwicker, Fabrication of 0.5 g±m MOS test devices by application of X-ray lithography at all levels, Proc. SPIE Vol. 1089, 202 (1989)

[3]

H.L. Huber, U. Scheunemann, W. Rohrmoser and E. Cullmann, Application of X-ray steppers using optical alignment for synchrotron based X-ray lithography, Proc. Microelectron. Eng. 151 (1988)

[4]

W. Windbracke, H. Betz, H.L. Huber, W. Pilz and S. Pongratz, Critical dimension control in X-ray masks with electroplated gold absorbers, Proc. Microelectron. Eng., 73 (1986)

[5]

R.U. Ballhorn, R. Dammel and H.H. David, Performance optimization of the chemically ampified radiation resist RAY/PF, Proc. Microelectron. Eng. (1990)

[6]

W. Windbracke, H.L. Huber, P. Staudt and G. Zwicker, Fabrication of sub 0.5 gm pattern for MOS devices by means of X-ray lithography and plasma etching, Proc. Microelectron. Eng. 109 (1988)

[7]

M. Orlewski, C. Mazur6 and F. Lau, Submicron short channel effects due to gate reoxidation induced lateral interstitial diffusion, IEDM Tech. Dig., 632 (1987)

[8]

D. Friedrich, H. Bernt, L. Schmidt and W. Windbracke, Degradation behavior of 0.5 gm p-channel metal-oxide-semiconductor transistors fabricated by means of X-ray and optical lithography J. Vac. Sci. Technol. B8 (6), 1638 (1990)

130

A 0.5 MICROMETER CMOS PROCESS BASED ON A 248 NM EXCIMER LASER STEPPER Mark D. Kellam, Scott Goodwin-Johansson, Susan Jones, Bruce Dudley, and Charles Peters MCNC, Center for Microelectronics P.O. Box 12889, Research Triangle Park, NC 27706-2889

A 0.5 micrometer CMOS process with cobalt salicide and three levels of metal interconnect has been developed for implementation on the GCA ALS 200 Excimer Laser Stepper, which operates at a 248 nm wavelength. The process is designed to meet aggressive performance, density, and manufacturability requirements by using minimum mask level dimensions of 0.5 micrometers at the polysilicon gate, contact, first metal and first via levels. Device and process design strategies are presented. INTRODUCTION A 0.5 micrometer CMOS process with cobalt salicide and three levels of metal interconnect has been developed for implementation on the GCA ALS 2000 Excimer Laser Stepper, which operates at a 248 nm wavelength. The process is designed to meet aggressive performance, density, and manufacturability requirements by using minimum mask level dimensions of 0.5 micrometers at the polysilicon gate, contact, first metal and first via levels. The process requires 11 masks and 13 lithography operations including a third level of metal and passivation. The layout groundrules for the process reflect a 3 sigma inter-level overlay specification of 0.15 micrometers. The process is designed for reliable operation at a power supply voltage of 3.3 volts. The gate oxide thickness used in the process is 11 nm and nominal effective channel lengths of the devices are 0.32 micrometers. LITHOGRAPHY Current non-achromatic fused silica lens place tight constraints on the light sources of deep UV excimer laser steppers, such that tight bandwidth control is important. In the deep UV stepper used at our fabrication facility, a GCA ALS 200 Excimer Laser Stepper with a

131

numerical aperture of .35 and a 248 nm light source, a wavelength control system can lock the source wavelength to a user specified position. The key parameters affected by wavelength setting were 1) distortion, an image placement error, 2) ultimate resolution, 3) proximity effect, as defined by the difference in measured linewidths between isolated features and gratings of a nominal feature size, and 4) astigmatism, in which horizontal and vertical foci do not coincide, reducing depth of focus. These parameters were evaluated to determine the best absolute wavelength setting for achievement of optimum imaging performance, and compared to the laser wavelength determined during installation to yield almost the minimum distortion. Metrology methods used for the evaluation include electrical resistance (Prometrix Lithomap® EM1), scanning electron microscopy (Hitachi S6000 Metrology SEM), and an intrafield metrology system built into the stepper (GCA SMARTSETO). It was documented that proximity effect decreases, resolution improves, and absolute lens distortion increases with negative shifts in laser wavelength setting, with a slight differential in the setting required to minimize horizontal versus vertical proximity effect and astigmatism [1]. A negative wavelength offset of 2.3 A from the nominal stepper setup wavelength was determined to be the best operating wavelength for our applications. The effect of laser wavelength adjustment on 0.50 .Im nominal features in terms of proximity effect, astigmatism and total lens distortion is given in the graph of Figure 1. It should be noted that the lens distortion plotted in the figure represents an absolute value of maximum displacement across the field. Lens distortion was the only intrafield parameter measured by Smartset that could not be corrected by adjustments to the reticle platen of the stepper. As shown in the figure, a minimum in lens distortion and an acceptable level of astigmatism is achieved at a wavelength offset of 0.5 A. However, at this offset the proximity effect is nearly 0.2 im for the features of interest. This means that an isolated feature printed 0.2 micrometers smaller than a line that is part of a dense array. A wavelength offset of -2.3 A provided a more acceptable compromise for our design rules, although total lens distortion measured 0.2 ptm. For wafers exposed operating the stepper with the detuned laser, top down low voltage SEM measurements of photoresist lines yielded a proximity effect of 0.04 gm for vertically oriented 0.50 gm nominal lines. Astigmatism measured 0.02 pm for 0.50 pgm nominal lines. Electrical linewidth testing documented a linewidth uniformity of 0.05 ptm (3a) for cz-L.

For small a, we have

>2

where the area A = WL. The error term in this case is a few percent of the total value. In addition, if the plates are not properly aligned with the axis of the tube, they will register an erroneous lateral motion with the tip moves vertically. Its presence is, however, easily detected because ghost images of tall objects will appear in plots of the capacitor output. The most effective way to deal with the error is to remove it 167

numerically. As described by Carr [3], the end of ,the tube tilts during lateral motion, causing the tip to swing relative to the reference plates. The size of the error is directly proportional to the distance between the tip and the end of the piezo tube, so it can be reduced by keeping that distance short. iThe 6 mm tip length in our microscope produces a swing of approximately 10 nm/V. If the capacitors are calibrated relative to a stage micrometer, the correction for the tip swing will be automatically included if the tip length is not changed afterward. The preformance of the system was checked by calibrating it with a twodimensional holographic grating. Over a 7 4im scan the capacitor output was linear to better than ±20 nm. The main error in the calibration actually arose from variations in the shape of the bumps in the grating. A convenient primary standard for widescan probe microscopes does not exist. LINE WIDTH MEASUREMENT: PROBE TIPS SHARPENED WITH A FOCUSSED ION BEAM The challenge in line width measurement occurs at the side walls of tall features because the width of a lithographically patterned object can not be known without measuring the shape of the sides, which are the least accessible part of the pattern. To make the problem even worse, side walls are often undercut. As in optical and electron microscopy, the ultimate limit to a probe microscope's ability to image a side wall is encountered in the interaction between the probe and the sample. In our case, no fundamental physical principles are involved; it is simply a question of tip size and shape. In most cases, the characteristic dimensions of the probe tip must be smaller than that of the features being scanned. Fortunately, the same processes used to fabricate the sample can often be used to sculpt the tip. The atomic resolution for which probe microscopes are famous can be misleading when considering the capabilities of such a microscope over a surface with steep topography. Atomic resolution arises from the configuration of a few atoms at the apex of a tip that may otherwise be quite blunt. A tip that can resolve atoms may be utterly incapable of discerning the shape of a quarter micron wide trench. When attempting to scan an object 1 .im deep, for instance, the tip shape must be known, and controlled, at least 1 pm from the apex. The finite width of the probe tip will induce errors, which can sometimes be numerically corrected. A scan requiring correction is shown in Figure 3 where a blunt probe tip encounters a moderately steep side wall. The point of closest approach, or proximal point, is indicated by the black dot. When the probe is scanning a flat region, the proximal point will coincide with the apex, but on a slope it wanders away from the apex. We describe the displacement of the proximal point from the apex with a shift vector, which must be determined if an accurate representation of the surface is to be extracted. This extraction is often called "deconvolution", which is unfortunate

168

terminology since convolution implies a linear process. The interaction of a probe tip " with any surface, flat or otherwise, is not linear [12].

Figure 3. Behavior of the proximal point when a blunt probe tip encounters an incline. The arrow indicates the shift vector. The problem of extracting the true surface from a scan has been discussed in several papers [13-15]. The extraction is not always possible. If, for instance, a blunt tip does not reach the bottom of a narrow trench, then only a lower bound for the depth is available. In Figure 3 the extraction is possible. Neither the tip nor the sample has a cusp at the proximal point, so the tangent planes of the two surfaces are parallel. The slope of the scan thus tells us the slope of the tip at the proximal point. For some tip shapes, the slope uniquely determines the shift vector. For instance, a parabaloidal tip allows such a determination, while a conical tip does not. Clearly, the shape of the probe tip must be accurately known. The probe shape can be measured with an electron microscope, but a better method is to use the probe microscope itself in conjunction with a known measurement structure. In Figure 4 we show how a trench or hole with vertical side walls can be used to determine the shape of the tip. As the tip drops into the hole, the proximal point stops at the lip and begins to generate a scan of the probe tip itself. With the tip shape in hand the most general way to perform the surface extraction would be to generate a look-up table associating a shift vector with each element in a small array of slopes. Alternatively one might fit the tip with a simple geometrical shape and then perform the extraction analytically. It is important that the tip characterization be performed after the data are collected. Under some circumstances the tip can be altered by the scanning; a tip that is sharp before a scan may not be so while the data are being taken.

169

Figure 4. A method for measuring the shape of the probe tip using the probe microscope and a known structure, in this case a hole. Because of the steep side walls, the image over the hole reveals the shape of the tip. Ideally one wants to have a tip so sharp that the correction to the scan is insignificant. Several papers on tip shaping techniques have been published most of them describing electrochemical etching procedures [16-20]. In some cases electrochemical etching produces tip radii as low as 10 nm, but such shapes are not easily reproduced. We have found that machining the probe with a Ga÷ focussed ion beam yields superior results [21]. The technique is shown in Figure 5. A 1.5 nA beam with 0.4 gtm with FWHM impinges on the probe along its axis. Several cuts with an annular raster produce a tip with radius of curvature as small as 4 nm. The probe typically widens to 0.2 pgm at a distance of 1 p.m from the apex. The dose required for the machining is roughly 10t 9 /cm 2 . Several tips can be prepared in an hour. Two SEM images of one of our Ir tips is shown in Figure 6. Focussed ion beam sharpening works with any stable material. When held vertical to the sample, the tip in Figure 6 can not directly scan a vertical side wall or a side wall that is undercut. At best is can establish an outer bound for the wall. That does not mean, however, that vertical side walls are inaccessible to probe microscopes. They have, in fact, been scanned by tips held at a small angle relative to the vertical. The disadvantage to this trick is that the side walls are not simultaneously accessible in all orientations. A better method is shown in Figure 7 where a probe with a flared bottom is used. Such a probe has not yet been successfully employed because a new feedback algorithm for this situation must be 170

I

41

1

0ks

Ga

I0

SI N. oJ I

0

1.0

2.0

LG (PaM) Fig. 12 Dependence of threshold voltage on gate length. Open symbols are for channelpreamorphized MOSFETs, and solid symbols are for MOSFETs without channel preamorphization.

Fig. 13 Drain current as a function of drain voltage for a 0.2-.um gate-length MOSFET with channel preamorphization. Gate width is 20 /um. Gate voltages ranged from 0 to -2 V in 0.2-V increments.

the MOSFET without channel preamorphization. It can be seen that transconductance for the channel-preamorphized MOSFET is almost the same as that for the MOSFET without channel preamorphization. This result indicates that carrier mobility is not degraded by channel preamorphization. Figure 12 shows the dependence of threshold voltage on gate length for two different drain voltages, -0.1 and -2 V. Open symbols represent the channelpreamorphized MOSFETs, and solid symbols those without channel preamorphization. It is clear that short-channel effects are suppressed in the channel-preamorphized MOSFETs due to the shallower counter-doped boron profile compared with MOSFETs without channel preamorphization. Figure 13 shows the drain current as a function of drain voltage for a 0.2-Mum gatelength MOSFET with channel preamorphization. Figure 14 shows IDS-VGS characteristics for the 0.2-Mtm MOSFET at two different drain voltages, -0.1 and -2 V. As shown in these figures, 0.2-gum gate-length pMOSFETs with good subthreshold characteristics have been successfully fabricated by using channel preamorphization. Leakage characteristics of p+n junction diodes fabricated in the same channel-preamorphized substrates are shown in Fig. 15 along with those of a nonpreamorphized diode. The diode area is 100 gm x 100 Aim. Solid curves represent channel-preamorphized diodes, and the dashed curve represents a nonpreamorphized diode. Channel-preamorphized diodes with leakage characteristics as good as those without channel preamorphization were obtained as indicated by curve A. Not all channel-preamorphized diodes exhibited such good characteristics, however. Some diodes showed poor leakage characteristics as shown by curve B. This large leakage current probably

273

-

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---

CHANNEL- PREAMORPHIZED NONPREAMORPHIZED

8 10-9 I-

z

are

A

LU 10-11 1

Io-2

0

-1 -2 APPLIED VOLTAGE (V)

-

.6

VGS (V)

Fig. 15 Leakage characteristics of p~n junction diodes fabricated in channel-preamorphized (solid curves) and nonpreamorphized (dashed curve) substrates. Diode area is 100 pm x 100 pm.

Fig. 14 IDS-VGS characteristics for a 0.2-pm gate-length MOSFET with channel preamorphization.

derives from insufficient preamorphization depth and/or metal contamination during ion implantation for channel preamorphization. It is important, therefore, to make the preamorphization depth sufficiently deep and to eliminate metal contamination during ion implantation to suppress leakage current.

SUMMARY The channel preamorphization technique, a technique for forming shallow boron-doped layers for channel doping using preamorphization, was reviewed. Preamorphization does not affect MOS capacitor characteristics so long as the original a/c interface is sufficiently deep. Buried-channel pMOSFETs with a shallow boron counter-doped layer using channel preamorphization were successfully fabricated. It was shown that channel preamorphization does not degrade carrier mobility and improves MOSFET characteristics in the subquarter-micrometer gate-length region suppressing short-channel effects.

ACKNOWLEDGMENTS The author wishes to thank T. Sakai and T. Kobayashi for their advice and encouragement.

274

REFERENCES [1] T. M. Liu and W. G. Oldham, IEEE Electron Device Lett., EDL-4, 59(1983) (2] A. E. Michel, R. H. Kastl, S. R. Mader, B. J. Masters, and J. A. Gardner, Apple. Phys. Lett., 44, 404(1984) [3] T. S. Seidel, R. Knoell, F. A. Stevie, G. Poli, and B. Sehwartz, in "VL9I Science and Technology/1984," (PV 84-7) K. E. Bean and G. A. Rozgonyi, Editors, p. 201, The Electrochemical Society Softbound Proceedings Series, Pennington, NJ( 1984) [4] B. Y. Tsaur and C. H. Anderson, Jr., J. Apple. Phys., 54, 6336(1983) [5] M. E. Lunnon, J. T. Chen, and J. E. Baker, J. Electrochem. Soc., 132, 2473(1985) [6] T. E. Seidel, R. Knoell, G. Poli, and B. Schwartz, J. Apple. Phys., §8, 683(1985) [7] S. D. Brotherton, J. P. Gowers, N. D. Young, J. B. Clegg, and J. R. Ayres, J. Apple. Phys., 60, 3567(1986) (8] M. Miyake, S. Aoyama, S. Hirota, and T. Kobayashi, J. Electrochem. Soc., 135. 2872(1988) [9] M. Miyake, T. Kobayashi, and Y. Okazaki, IEEE Trans. Electron Devices, 36, 392(1989) [10] K. M. Chain and S. Chang, IEEE Trans. Electron Devices, ED-31, 964(1984) [11] M. Miyake, J. Electrochem. Soc., 137, 2860(1990) [12] M. Miyake, T. Kobayashi, and Y. Okazaki, IEEE Trans. Electron Devices, 37, 2007(1990) [13] M. Miyake and H. Harada, J. Electrochem. Soc., 129, 1097(1982) [14] M. Miyake and S. Aoyama, J. Apple. Phys., 63, 1754(1988) [15] J. Narayan, 0. W. Holland, R. E. Eby, J. J. Wortman, V. Ozguz, and G. A. Rozgonyi, Appl. Phys. Lett., 43, 957(1983) [16] R. B. Fair, J. J. Wortman, and J. Liu, J. Electrochem. Soc., 131, 2387(1984) (17] S. J. Pennycook, J. Narayan, and 0. W. Holland, J. Electrochem. Soc., 132, 1962(1985) [18] R. Angelucci, P. Negrini, and S. Solmi, Appl. Phys. Lett., 49, 1468(1986) [19] A. E. Michel, W. Rausch, P. A. Ronsheim, and R. H. Kastl, Appl. Phys. Lett.,

[20] T. J. [21] S. in [22] S. 51, [23] M.

50,

416(1987)

0. Sedgwick, A. E. Michel, V. R. Deline, and S. A. Cohen, Appl. Phys., g3, 1452(1988) D. Brotherton, J. R. Ayres, J. B. Clegg, and B. J. Goldsmith, Mat. Res. Soc. Symp. Proc., 104, 161(1987) Solmi, R. Angelucci, F. Cambali, and M. Servidori, Appl. Phys. 331(1987) Kuhn, Solid-State Electron., 13, 873(1970)

275

Lett.,

OHMIC CONTACT FORMATION TO THE SHALLOW JUNCTIONS BY SELECTIVE TITANIUM SILICIDE CHEMICAL VAPOR DEPOSITION Kunio Saito, Takao Amazawa, and Yoshinobu Arita NTT LSI Laboratories Morinosato Wakamiya 3-1, Atsugi-shi, Kanagawa, 243-01 Japan

Selective titanium silicide chemical vapor deposition with an in-situ silane gas cleaning treatment and a silicon consumption control method are developed. The dependence of the source-gas flow rate on silicon consumption and film resistivity are clarified. Silicon consumption can be controlled by making a very small TiCI 4 /SiH 4 flow-rate ratio. By applying selective titanium silicide film to test devices with 0.1- /i m-deep shallow junctions, a low contact resistivity around 10-' • cm2 and a low junction leakage 2 current around 1011 A/mm are obtained.

INTRODUCTION Selective silicide chemical vapor deposition (CVD) is expected to be used in future deep submicron devices to reduce the contact resistivity of metal/silicon contacts or sheet resistance of silicon electrodes. Selective titanium silicide CVD has been studied by some researchers. [1, 21 However, difficult problems, such as the nucleation which resulted from the film growth started with islets and a large silicon substrate consumption, were unfortunately revealed. These problems have been studied further. V. Ulderem et al. reported deposition of a thin polysilicon layer prior to silicide deposition promoting the nucleation of titanium silicide. [3] D. Bensahel et al. reported titanium silicide deposition without silicon consumption using a TiCI 4 /SiH 4 system diluted in H2 and a fast-switching lamp system. [4] When a selective titanium silicide CVD process is applied to deep submicron devices with very shallow junctions, severe requirements such as both of small grains and small silicon consumption must be satisfied. We previously reported that the nucleation problem can be solved by using an in-situ SiH 4 gas cleaning treatment prior to titanium silicide deposition. The effect of the SiHl4 gas cleaning treatment on native oxide reduction was studied throughout the experiments; the nuclei density of titanium silicide were greatly increased by the cleaning treatment, and each silicon nuclei in-situ deposited on the silicon substrate after the cleaning 276

treatment grew epitaxially. [5, 6] This paper reports clear evidence of native oxide reduction by the in-situ SiH4 gas cleaning treatment. The paper also reports the silicon consumption depended on the ratio of the source-gas flow rate. Some electrical characteristics obtained from test devices with 0.1- 1rm-deep shallow junctions were also reported. EXPERIMENTS The silicon wafer was dipped in diluted HF and rinsed with pure water. Titanium silicide films were selectively deposited by the following process and conditions using the previously reported CVD apparatus [51 First, the in-situ SiH 4 gas cleaning treatment was performed at a temperature of about 720r- with a SiH4 gas flow rate of 10 SCCM and pressure of 0.5 mTorr. Sequentially, titanium silicide film was selectively deposited at a temperature of 720-7401C with a SiH 4 gas flow rate of 50 SCCM, partial SiH4 gas pressure of 19 mTorr, and TiCl 4 gas flow rate of 0.05-0.3 SCCM. The effect of the in-situ SiH4 gas cleaning treatment was confirmed using in-situ silicon deposition with a large deposition rate and depth profile measurement by secondary ion mass spectroscopy (SIMS) analysis. The quantity of silicon consumption was measured using a cross-sectional view of a scanning electron microscope (SEM). Titanium silicide film deposited under optimum condition was observed by a transmission electron microscope (TEM). (100) oriented p-type and n-type 1-10 0 - cm silicon wafers were used to obtain electrical characteristics. The device areas were isolated by oxide film formed by the LOCOS process. Shallow n/p junctions were formed by a low-energy As implant of 4 X 1015 cm-' dose. Shallow p7/n junctions were formed by a two-step implant including a low-energy silicon implant to preamorphize the silicon substrate and a low-energy BF2 implant of 2 X 10 1 5cm- 2 dose. [7] The wafers were annealed by a rapid thermal-annealing system. Both the n'/p and p÷/n junctions were formed about 0.1 /Am in depth. TiN film for barriers and AI(Cu) film for electrodes were sputtered and patterned. The contact resistances were measured using Kelvin resistors. RESULTS & DISCUSSION Effect of the in-situ Sil. gas cleaning treatment Wafers of p-type (100) silicon were cleaned by a modified RCA washing treatment Two types of wafers were prepared for this experiment. One was made through eliminating native oxide by dipping the wafers in diluted HF and rinsing them in pure water for 2 hours (specimen A). The other was made 277

through oxidization by dipping in diluted H2 0 2 after eliminating native oxide with diluted HF (specimen B). In-situ silicon film deposition was performed after the SiHl4 gas cleaning treatment to maintain the native oxide in the deposited silicon / substrate silicon interface. The in-situ SiH 4 gas cleaning treatment and in-situ silicon deposition were performed under the conditions shown in Table 1 and 2, respectively. Figure l(a) and (b) show the depth profiles of oxygen and carbon concentrations in the deposited silicon / substrate silicon structures; (a) and (b) show the profiles of specimens A and B, respectively, with and without the SiH4 gas cleaning treatment. It is clear from Fig. 1 that the native oxide is reduced by the SiH 4 gas cleaning treatment. The reduction of native oxide in specimen B is more effective than that in specimen A. The carbon is not reduced very much by the cleaning treatment. We think the two peaks of the carbon profile in Fig. l(b) were caused in the SIMS measurement by the surface roughness of the deposited silicon which originated from incomplete epitaxy. Considering the above results and the phenomena of titanium silicide deposition with and without the in-situ SiHl4 gas cleaning treatment, [5, 6] the oxygen on silicon has a strong influence on the titanium suicide growth when a TiCI 4 /SiH 4 gas system is used. conversely, it is clear that the carbon on silicon does not strongly influence the titanium silicide growth.

Table 1. The conditions of the in-situ SiH4 gas cleaning treatment Wafer temperature Sill,, gas flow rate SiH4 gas pressure Treatment time

about 750'C 10 SCCM 0.5 mTorr 1.5 min for specimen A 12.5 min for specimen B

Table 2. The conditions of the silicon deposition Wafer temperature : about 750rC SiH 4 gas flow rate : 20 SCCM Sill4 gas pressure 65 mTorr Deposition time L5 min Film thickness 0.35-0.4 /Lm

278

U 02 Go

0

z 02

z U z 0W

0 15 30 SPUTTERING TIME (min)

0 15 30 SPUTTERING TIME (min)

(a) Rinsed in pure water.

(b) Oxidized in diluted H.0 2 .

Fig. L Depth profiles of oxygen and carbon concentrations in the deposited silicon / substrate silicon structures with and without the in-situ Sil-14 gas cleaning treatment. The substrate silicon surfaces were rinsed in pure water for 2 hr (a) or oxidized in diluted H0a 5 (b). Specimens were sputtered about 0.5 ILm in depth for 30 min.

Si consumption The silicon substrate consumption was successfully controlled by a very small ratio of the TiCl/SiH4 gas flow rate. Figure 2 shows the TiCl 4 gas flow rate dependence of the titanium suicide film resistivity and the consumed silicon depth expressed as a percentage of the titanium silicide film thickness. The titanium silicide films grew with full selectivity under the conditions for the TiCl. gas flow rate over 0.05 SCCM at least. As seen in Fig. 2, the silicon consumption decreases with a decrease in the TiCl 4 gas flow rate, but the film resistivity increases. In contrast, the film resistivity becomes closer to the bulk value for increasing TiCl4 gas flow rate, but the silicon consumption simply increases. Using X-ray diffraction analysis, the C54 type of TiSi. was observed for a TiClI gas flow rate of 0.1-0.3 SCCM, and a mixture of C54 TiSi2 and 279

-~

bc-SiH

S1001a720-740r

4:

"'

50 SCCM

Mo WZý

"-50aU

so-

'-1500

0

0.1

0.2

0.3

0

(SCCM) TiCI 4 GAS FLOW RATE

Fig. 2. The TiC14 gas flow rate dependence of titanium silicide film resistivity and the consumed silicon depth expressed as a percentage of the titanium silicide film thickness.

Ti5 Si 3 for a TiC14 gas flow rate below about 0.1 SCCM. Supposing that only titanium is supplied to the silicon substrate to make C54 type TiSi2 , the consumed silicon depth is calculated to about 90% of the titanium silicide film thickness. A relatively small silicon consumption shown in Fig. 2 indicates that part of the Si in the titanium silicide was supplied from the gas phase. A larger silicon consumption than about 90% means that the substrate silicon was consumed to make titanium suicide, and part of the substrate silicon evaporated with a byproduct form through the titanium silicide film. TEM observation of the titanium suicide film Figure 3 shows a cross-sectional TEM photograph of titanium silicide film deposited under the optimum conditions of which the consumed silicon depth corresponds to about 50% of the titanium sUicide film thickness. The film consists of small-size grains less than about 800 A along the silicon surface and less than about 400 A in the perpendicular direction. The film penetrates the underlying silicon to about 200 A in maximum depth. The titanium silicide grows with a nucleus form, as seen in Fig. 3. Considering the cause of the growth feature, a small quantity of oxygen or carbon remaining after the in-situ SiM4 gas cleaning treatment on the silicon substrate, as shown in Fig. 1, has the possibility to prevent uniform growth of titanium silicide. Another possibility for the nucleation is a high process temperature. 280

i Titanium silicide

I

0 0 0

Silicon substrate

Fig. 3. A cross-sectional TEM photograph of titanium silicide film deposited under the optimum conditions.

Selective titanium silicide film deposition in a deep submicron contact hole Figure 4 shows an SEM photograph of selectively deposited titanium silicide film on the bottom of a 0.2-g m-diameter contact hole which has an

Fig. 4. An SEM photograph of selectively deposited titanium silicide film on the bottom of a 0.2- I m-diameter contact hole (aspect ratio = 2.5). 281

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10

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1

L5

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CONTACT HOLE SIZE (IL m)

Fig. 5. The contact resistance as a function of contact hole size.

I

V

as depo. 400 450 500

ANNEALING TEMPERATURE (C)

Fig. 6. The contact resistance as a function of annealing temperature.

aspect ratio of 2.5. Using the selective CVD method, we can easily form titanium silicide film on the bottom of a deep submicron contact hole. Contact resistivity A selective titanium silicide film was deposited on the 0.1- IL m-deep shallow junctions under the optimum conditions. Figure 5 shows the contact resistance for n' and p÷ silicon as a function of contact hole size. The contact resistivities for n- and p' silicon are about 2 X 10-' and 6 X 10' Q - cm', respectively. Annealing caused little change in the contact resistance at 400-500r,, as shown in Fig. 6. In this experiment, optimization of impurity concentration at the titanium silicide / silicon interface was not performed. Thus, we think a lower contact resistivity might be obtained by the optimization. Junction leakage current for the shallow junctions Figure 7 shows the junction leakage currents for 0.1- IL m-deep shallow junctions as a function of annealing temperature. The device used in this measurement was on the same wafer with Kelvin resistors. The junction areas were 0.03 mm2 for the n÷/p junction and 0.2 mm" for the p÷/n junction. The contact areas were about half of the junction areas. The leakage currents of both the n-/p and p÷/n junctions are in the

282

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IV

Junction depth: 0.1 g m Bias: ±5 V

z

n÷/p

10-10

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p÷/n

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400

450

500

ANNEALING TEMPERATURE ('C) Fig. 7. The junction leakage current for 0.1- g m-deep shallow junctions as a function of annealing temperature.

order of 10' A/mm 2 and were slightly changed by 400-500U annealing. This result shows that the selective titanium silicide CVD method can be used for ohmic contact formation to shallow junctions. CONCLUSION Clear evidence of the native oxide reduction by the in-situ SiH4 gas cleaning treatment was presented using in-situ silicon deposition and a depth profile measurement of SIMS. The silicon substrate consumption was successfully controlled to a relatively small value by a very small TiCI4 /SiH 4 flow-rate ratio that ranged from 0.001 to 0.005 when the SiH 4 gas flow was 50 SCCM at 720-740rC. The selective titanium silicide film deposited under optimum conditions was applied to test devices with 0.1- g m-deep shallow junctions. A low contact resistivity around 10' 0 • cm2 and a low junction leakage current around 10-" A/mm2 were obtained. The values were low enough to apply the selective titanium silicide film to devices with very shallow junctions.

283

ACKNOWLEDGEMENT We would like to thank Dr. T. Sakai for his encouragement throughout this work.

[1] A. 2080. [2) G. [3) V. [4] D.

REFERENCES Bouteville, A. Royer, and J. C. Remy: J. Electrochem. Soc. 134 (1987)

J. Reynolds, C. B. Cooper, and P. J. Gaczi, J. AppL Phys. 65 (1989) 3212. Ilderem and R. Reif: Appl. Phys. Lett. 53 (1988) 687. Bensahel and J. L. Regolini: Appl. Phys. Lett. 55 (1989) 1549. [5] K. Saito, T. Amazawa, and Y. Arita: Extended Abstracts of the 21st Conference on Solid State Devices and Materials, Tokyo (1989) 541. [6] K. Saito, T. Amazawa, and Y. Arita: Jap. J. Apple. Phys. 29 (1990) L185. M7l M. Miyake, S. Aoyama, S. Hirota, and T. Kobayashi: I. Electrochem. Soc. 135 (1988) 2872.

284

DEFECT ANNEALING IN ULTRA-SHALLOW JUNCTIONS FOR SCALED SUB-MICRON CMOS TECHNOLOGY S. Chevacharoenkul1, C.M. Osburnl, 2 , G.E. McGuire 1 1 MCNC, Center for Microelectronics P.O. Box 12889, Research Triangle Park, NC 27709 2 Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC 27695 Defect annealing in preamorphized and non-preamorphized Si substrates that have been implanted with low energy ions (Ge, Si, As, BF2) were examined as a function of 10 second rapid thermal annealing temperature (650-1050 °C) using transmission electron microscopy. The energy and dose of implantation were selected in accordance with a scaling rule based on minimization of the short channel effect. Such energies and doses result in the formation of amorphous layers which extend to the surface. It was found that lower annealing temperatures are required to remove the ion implantation damage when the junction depths are shallower. Factors affecting the damage removal were determined to be both the integrated recoils beyond the amorphous/crystalline (a/c) interface and the proximity of the a/c interface to the free surface. As the junction becomes deeper a higher temperature is needed to provide more vacancies for recombination with the interstitials dissolving from the loops. INTRODUCTION Ion channeling leading to a deeper-than-anticipated junction is a well known phenomenon in junction formation by ion implantation. Preamorphization of the Si surface with electrically non-active species such as Si, Ge and Sn was proposed to eliminate the channeling of the dopant [1-5]. However, the formation of end-of-range defects resulting from point defect agglomeration during the dopant activation can lead to high leakage current [6]. Their size- and spatial distributions were shown to depend on annealing temperature, as well as on the ion-energy and dose of implantation [7]. In general, defect annealing involves dissolution and recombination of interstitials and vacancies whose concentrations and diffusivities increase exponentially with temperature. Defect annealing is, therefore, expected to influence the kinetics of dopant diffusion which in turn determines the junction depth. It was the objective of this study to understand the relationship between the point defect production, annealing temperature, dopant diffusion and defect annealing in the formation of ultra-shallow junctions. EXPERIMENTAL PROCEDURE Details of the experimental procedure can be found in a companion article [8]. Only a summary is given here. Both p- and n-type Si (100) -10 ohm-cm substrates were RCA285

cleaned, and their top halves were masked with 1.5 micron thick photoresist films. Preamorphization of the lower halves with Ge or Si was done in a Varian 350 D Ion Implanter at 7 degree tilt. The photoresist films were later stripped by wet etching and the entire wafers were ion-implanted with As or BF2. Solid-phase epitaxial (SPE) regrowth of the amorphous region was accomplished by annealing at 450WC and 5500 C for 30 min each. Rapid thermal annealing (RTA) to electrically activate the dopants was done for each wafer at 650, 750, 850, 950 or 1050'C for 10 sec. After electrical measurements, wafers were divided for TEM and SIMS analyses. Both planar and cross-sectional views of each sample were studied in a transmission electron microscope operated at 300 kV. SIMS profiling conditions were optimized to ensure the minimum knock-on mixing.The complete SIMS results for the dopant profiles, as-implanted and after RTA, are given in the companion paper mentioned above. Table I. Process Description Technology

I12

Xj (nm):

200

Lkm

1/4 tim

150

70

40/5x10 14 30/5x 1014 20/2x10 15 10/5x1014

25/4x1014 20/4x 1014 15/1.5x10 1 5 8/4x10 14

450/30 550/30 1000/10

450/30 550/30 950/10

2

Ion: energy/ dose ( keV/cm- ) 85/lx10 15 Ge Si 50/5x1015 As 44/lx10 15 BF2 Annealing : temperature/time SPE (°C/min) 550/30 RTA (°C/see)

1050/10

RESULTS AND DISCUSSION Amorphization Depth Room temperature implantations using the conditions listed in Table I produce uniform amorphous layers to the depths shown in Table II. As seen in Fig. 1, the amorphous/crystalline (a/c) interface was abrupt. The amorphization depths obtained in this study were plotted along with those reported in the literature [9-25] in Fig. 2 A-C. The depth of the amorphous layer in nm produced by Si or Ge or As implants into Si substrate can be fitted to the equations : Da/c (Si)

=

6.22 + 2.05E + (1.76x10- 3 )E2 ,

and Do/c (Ge or As)

=

1.3E

286

E a 20

where E is the implant energy in keV. The amorphization depths obtained in our study are slightly less than those reported by others. Possibly the combination of room temperature implantation and the use of medium currents can induce substantial dynamical annealing. It should be noted that although data in the plots were not confined to one dose and that the use of a higher dose results in a larger depth of amorphization [7], the data do not appear to scatter significantly from the line given above. Table II. Amorphous Layer Thickness

ion

Ge Ge Ge Si Si As As As BF2 BF2 BF2

implantation conditions dose current (cm-2 ) 0iA) (keV)

a/c interface depth

energy

25 40 85 20 30 15 40 50 8 10 44.4

14

4x10 5x1014

lxi015 14

4x10 5x1014 1.5x1015 15

4x10 5x1015 14 4x10 5x10

14

lx1015

40 50 55 70 60 40 100 125 16 25 47

(nm) 34 50 98 32 43 26 62 75 11 14 38

Fig. 1. XTEM micrographs of (100) Si substrates implanted with (A) Ge,(B) Si, (C) As and (D) BF2 showing the amorphous layer thickness, uniform amorphization within the layer, and abrupt amorphous/crystalline interface.

287

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0 50 100 150 200 250 Implantation Energy (keV)

400

• 300

S250,

S150

CLI 100. 0

100 200 300 400 500

Fig. 2. Plots of the amorphous layer thickness as a function of energy for A) Ge, B) Si and C) As implants into (100) Si, including data from ref. [9-25].

Ua

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Implantation Energy (keV)

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* this work * Prussin et al * Cerva&Kuster * Horiuchi et al 1 Narayan et al a Kown&Lee

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Damage Removal Damage removal which occurs during 10 second rapid thermal annealing at various temperatures in scaled Ge-preamorphized junctions (25 keV, 4x10 14 Ge) is shown in Fig.

3.During the SPE anneal at 550 TC for 30 minutes, the implantation damage which consists

of interstitials and vacancies interacts through the processes of annihilation and

agglomeration to form a band of many small interstitial loops at the amorphous/crystalline interface. The material above the boundary appears defect-free. However, one study [26] reported that this layer is vacancy-rich. Below the a/c interface the vacancies produced by implantation either recombine with interstitials, diffuse to the surface, recombine with other vacancies or remain as free vacancies. The existence of vacancies both above and below the ion-implanted Si before and after a low temperature annealing was detected using a positron annihilation technique [27]. Rapid thermal annealing up to 750 'C did not result in significant change in the defect structure formed during SPE regrowth. However, significant removal of the damage occurred at 850 0 C. The interstitial loops which survived at this temperature grew in size indicating these were loops with radii larger than a critical radius below which complete dissolution of loops occurred during the 10 second of anneal. A flux of atoms from the dissolved loops recombined with the undissolved loops and

caused them to grow. After 10 seconds 950 'C or 1050 'C, damage removal was almost complete and complete, respectively. Plan-view TEM micrographs of residual damage in the Ge preamorphized junctions after 10 second annealing at 1050 °C, 1000 'C or 950 'C for 85 keV, 40 keV, and 25 keV Ge, respectively, are shown in Fig. 4. Two important findings are seen in Fig. 4. First, as the implant energy increases, both the depth and areal loop density of defects increase. Second, higher annealing temperatures are required to remove all the defects produced by higher implantation energies. This later phenomena is presumeably a result of the greater damage depth from the surface which might act as a vacancy source or interstitial sink and/or greater damage density. This finding is also true for the non- Ge preamorphized Asimplant and BF2-implant junctions shown in Figures 5 and 6, respectively. A computer souce code : TRIM. CAS [28], which is a 3-dimensional Fortran Monte-Carlo program with cascades, was employed to calculate the ion ranges and Frenkel-pair defect production for the 85, 40 and 25 keV Ge implants as well as for a 20 keV Si implant into Si substrate. Ten thousand incident ions were used to compute distributions of interstitials and vacancies assuming a displacement energy of 15 eV. Fig. 7 shows the results. The distributions were normalized to the doses employed here (Table I). While the three implant conditions produce nearly the same Ge peak height of 1.5x1020 cm3, the peak heights of the interstitials are not the same. It should be added that the distributions of the vacancies are almost identical to those of the interstitials and that the concentration of interstitials at the a/c interface is about 1.7x10 22 cm- 3 for room temperature implants. The interstitials (damage) which must be removed during annealing can be estimated by integrating the area under the curve from the amorphization depth to the tail which is given in Table III. The implantation condition for the one micron technology produces 2.44 and 2.98 times more interstitials than those of the one-half and one-quarter micron technology, respectively. However, since damage removal involves diffusion of these interstitials and/or creation of vacancies, it is informative to examine the diffusivity of

289

Fig. 3. XTEM of Ge-preamorphized Si after 550 *C SPE regmwth (A). Plan-view TEM's after RTA at B) 750 OC, C) 850 OC, and D) 950 OC.

Fig. 4. Plan-view TEM's of Ge preamorphized Si after 10 sec RTA. A) 1050 *C (85 keV/lxlO05 cm' 2 ); B) 1000 0 C (40 keV/5xl0 14 cm-2 ); C) 950 OC (25 keV/4xl0 14 cnr 2 ).

290

Fig. 5. Plan-view TEM's of non-Ge preamorphized Arsenic implanted Si after 10 sec 0 2 0 RTA. A) 1050 0C (50 keV/5xl0 5 cm-2 ); B) 1000 C (25 keV2xl015 cm- ); C) 950 C (15 keV/1.5 keV/10 15 cm-2).

Si after 10 sec RTA at Fig. 6. Plan-view TEMs of non-Ge preamorphized BF2 implanted 2 14 2 A) 1050 TC (44.4 keV/1xl015 cm- ), B) 1000 *C (10 keV/5xl0 cmn ), and C) 950 'C (8 keV/4x 1014 cm-2).

291

Si at the three annealing temperatures as a measure of the concentration and mobility of the defects. The Si diffusivities at 950, 1000 and 1050 'C are 4.1x10- 18, 3.2x10- 17 and 1.8x1016 cm 2 /s , respectively [29], i.e., Si diffuses 5.6 and 44 times faster at 1050 "C than at 1000 'C and 950 'C, respectively. The differences in the integrated recoils among the three implants, i.e. only 2.44x and 2.89x, seem insignificant in comparision to the large differences in the diffusivity. From a diffusion view-point, annealing the 85 keV Ge implanted Si at 1050 'C should result in a damage-free junction, but experimental data indicate otherwise.This result leads to the conclusion that the total number of recoiled atoms beyond the a/c interface does not fully explain the damage removal behavior in the scaled junctions. Table IIn. Integrated Interstitials Beyond the a/c Interface for Ge implants Energy/dose (keV/cm-2 )

Interstitials (cm-2 )

85/ 1xl0 15 40/5x101 4 25/4x10 14

3.16x10 1.29x10 1.06x10

16 16 16

Another parameter which can affect damage removal is surface proximity of the a/c interface. The surface proximity effect on the damage removal was studied in two experiments. In the first, the amorphous depths were nearly equal but the integrated recoils were different ( Fig. 7b). In the second experiment , the integrated recoils were the same but the amorphous depths were different. Shown in Fig. 8 are plan-view TEM micrographs of Ge (25 keV/4xl014 cm-2) and Si (20 keV/4x 1014 cm- 2 ) preamorphized junctions which were annealed at 950 'C for 10 seconds. These two junctions had only a 2 nm difference in the amorphizartion depth (32 nm for Si versus 34 nm for Ge). It is seen that the remaining damage is very different for the two implants, i.e., nearly complete for the Gepreamorphization but considerable residual for Si implantation. This experiment indicates that equal proximity to the free surface does not produce equal damage removal. In the second experiment, a Si substrate was implanted with Ge at 85 keV and lx10 15 cm-2 dose and then 38 nm of the amorphized layer was etched away before performing an identical SPE and RTA anneal. The residual damage in the two samples is shown in Fig. 9. The loop size in the two micrographs is about the same but the areal density changes from 2.5x109 cm- 2 to 4.7x109 cm-2 in the etched and unetched samples, respectively. Moving the a/c interface 40 % closer to the surface results in a 47 % reduction in the residual damage. The enhanced damage removal induced by the reduction of a/c interface found here is in agreement with the work of Thornton and Hill [30] but in contradiction with that of Ganin and Marwick [31]. CONCLUSIONS In this study scaled shallow junctions were found to require lower annealing temperatures to remove the damage. This phenomenon is partially explained by the fact that fewer interstitial atoms are produced below the a/c interface when the ion -implantation energy is lower. For different implants possessing the same depth of amorphization, 292

a

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C.)

0

a

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0

40

160 120 80 Depth (nm)

200

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240

20

SO au 40 Depth (nm)

iuu

120

Fig. 7. TRIM concentration-depth profiles: A) interstitials (i) and germanium (g) for 25, 40 and 85 keV Ge implants; B) interstitials (i), 25 keV germanium (g) and 20 keV silicon (s). Hatched areas represent integrated recoils beyond amorphous/crystalline interface.

at 950 0 C. Fig. 8. Plan-view TEM of Ge (A) and Si (B) preamorphized Si after 10 sec RTA depth of identical The implant energies (25 keV Ge and 20 keV Si) were chosen to give amorphization. 293

damage removal depends on the number of interstitial atoms below the a/c interface. However, the numbers of interstitials alone could not completely explain the damage removal behavior. Etch-back experiments show that reducing the a/c interface depth results in an accelerated damage removal which leads to the conclusion that surface proximity also plays an important role in the removal of damage caused by ion implantation.

Fig. 9. Plan view TEM's of damage removal in 85 keV Ge implanted silicon after 10 sec at 1050 'C RTA: A) 38 nm of substrate removed by chemical etching prior to RTA; B) no etching ACKNOWLEDGMENTS The authors wish to express their appreciation to the following persons who have made contributions to this work : R. Chapman, R. Fair, J. J. Lee, M. Ma, M. Ray R.Stokell and T. Tan. They would also like to thank the staff of the MCNC Silicon Processing Facility for the sample preparation. REFERENCES [1] M. Y. Tsai and B. G. Streetman, J. Appl. Phys. 50, 183 (1979). [2] T.E. Seidel, IEEE Electron Device Lett. EDL-4, 353 (1983). [3] D. K. Sadana, W. Mazsara, J. J. Wortman, G. A. Rozgonyi, and W. K. Chu, J. Electrochem. Soc., 131, 934 (1984).

294

[4] M.C. Ozturk, J.J. Wortman, C.M. Osburn, A. Ajmera, G. A. Rozgonyi, E. Frey, W.K. Chu, and C. Lee, IEEE Trans. Electron Devices, 35, 659 (1988). [5] S. D. Brotherton, J. R. Ayres, J.B. Clegg and J. P. Gower, J. Electronic Materials, 18, 173 (1989). [61 M. Miyake, S. Aoyarna, S. Hirota, and T. Kobayachi, J. Electrochem. Soc. 135, 2872 (1988). [7] K. S. Jones, and D. Venables, J. Apple. Phys. 69, 2931 (1991). [8] C. M. Osburn, S. Chevacharoenkul, and G. E. McGuire, in 1991 ULSI Science and Technology, J. M. Andrews and G. Celler, eds. Electrochem. Soc., 1991. [9] S. D. Brotherton, J. R. Ayres, J.B. Clegg and J. P. Gower, J. Electronic Materials, 18, 173 (1989). [10] S. Prussin and K. S. Jones, J. Elctrochem. Soc., 137, 1912 (1990). [11] M.C. Ozturk, J.J. Wortman, C.M. Osburn, A. Ajmera, G. A. Rozgonyi, E. Frey, W.K. Chu, and C. Lee, IEEE Trans. Electron Devices, 35, 659 (1988). [12] C. P. Wu, J. T. Mcginn, and L. R. Hewitt, J. Electronics Materials, 18, 721 (1989). [13] E. Myers, G. A. Rozgonyi, D. K. Sadana, J. J. Wortnan, and J. Narayan, in Rapid Thermal Processing,T. 0. Sedgwick, T. E. Seidel, B. -Y. Tsaur, eds., Mat. Res. Soc.Symp. Proc., 52, 107 (1986). [14] A. C. Ajmnera and G. A. Rozgonyi, Appl. Phys. Lett., 49, 1269 (1986). [15] M. Miyake, S. Aoyamna, S. Hirota, and T. Kobayachi, J. Electrochem. Soc. 135, 2872 (1988). [16] A. Tanaka, T. Yamnachi, A. Uchiyama, T. Iwabuchi, and S. Nishikawa, IEDM, 32, 785 (1989). [17] D. Brotherton, J. P. Gowers, N. D. Young, J. B. Clegg, and J. R. Ayres, J. Appl. Phys., 60, 3567 (1986). [18] D. M. Maher, R.V. Knoll, M.B. Ellington and D.C. Jacobson, in Rapid Thermal Processing,T. 0. Sedgewick, T. E. Seidel, B. -Y. Tsaur, eds., Mat. Res. Soc.Symp. Proc., 52, 94 (1986). [19] C. P. Wu, J. T. Mcginn, and L. R. Hewitt, J. Electronics Materials, 18, 721 (1989) [20] G. A. Ruggles, S. Hong, J. J. Wortman, M. C. Ozturk, E. R. Myers, L J. Hren, and R. F. Fair, in Processingand Characterizationof MaterialsUsing Ion Beams, L. E. Rehn, Greene, F. A. Smidt, eds., Mat. Res. Soc. Syrup. Proc., 128, 611 (1989). [21] S. Prussin, D. I. Margolese, and R. N. Tauber, J. Apple. Phys. 57, 180 (1985). [22] H. Cerva and K. -H. Kusters, J. Appl. Phys., 66, 4723 (1989). [23] M. Horiuchi, M.Tamura, and S. Aoki, J. Appl. Phys.,65, 2238 (1989). [24] J. Narayan and J. Fletcher, in Defects in Semiconductor, J. Narayan and T. Y. Tan, eds., Mat. Res. Soc. Symp. Proc., 2, 191 (1981). [251 S. J. Kown and J. D. Lee, J. Electrochem. Soc., 138, 867 (1991). [26] S. Solomi, R. Angelucci, F. Cembali, and M. Serviori, Appl. Phys. Lett. 51, 331 (1987). [27] P. Hautojarvi, P. Huttunen, J. Makinen, E. Punkka and A. Vehanen, in Defects in ElectronicMaterials,M. Stavola, S.J. Pearton and G. Davies, eds., Mat. Res. Soc. Syrup. Proc., 104, (1987). [28] J. P. Biersack and L. G. Haggrmark, Nucl. Instrum. Methods, 174, 257 (1980). [29] R. B. Fair, in Impurity Doping Processes in Silicon, F. F. F. Wang, ed., NorthHolland, New York, 1991. [30] J. Thornton and C. Hill, Semiconduct. Sci. Technol., 4, 53 (1989). [31] E. Ganin and A. Marwick, in Ion Beam ProcessingOf Advanced ElectronicMaterials, N. W. Cheung, A. D. Marwick, and J. B. Roberto, eds., Mat. Res. Soc. Symp. Proc., 147, 13 (1989).

295

ULTRA-SHALLOW JUNCTION FORMATION BY DIFFUSION FROM POLYCRYSTALLINE SixGel-x ALLOYS D.T. Grider, M.C. Oztiirk, and J.J. Wortman Department of Electrical and Computer Engineering North Carolina State University Raleigh, North Carolina 27695 ABSTRACT Selectively deposited, implanted polycrystalline SixGel-x has been investigated as a potential diffusion source for boron in the formation of ultra-shallow p÷-n junctions in silicon. Polycrystalline SixGel-x can be deposited on Si selectively with no deposition occuring on Si0 2 . In addition, the alloys exhibit a different etch chemistry than silicon so that if desired, SixGel-x may be selectively removed following dopant drive-in, making this technique directly comparable to ion-implantation without introducing substrate damage in Si. The alloys used in this study were deposited selectively on Si in a rapid thermal processor using dichlorosilane and germane as the reactant gases. After deposition, the alloys were doped with boron using ion-implantation and then annealed in a rapid thermal processor to diffuse boron into silicon. Shallow junctions were obtained with high peak surface concentrations and steeply sloped dopant profiles. Forward bias I-V and reverse bias I-V and I-1/T measurements indicated low leakage current densities and good ideality factors. I. INTRODUCTION Scaling trends continue to drive feature sizes of MOS devices smaller and smaller. Considerable effort has been directed to the issue of scaling vertical junction depths to keep pace with decreasing line widths [1 - 4]. Of all the existing techniques to form shallow junctions, low energy ion-implantation continues to be the most commonly used method to form these junctions today. In practice, shallow p+-n junctions are typically much more difficult to obtain than n÷-p junctions because of the channeling of boron during implantation, causing a spreading of the as-implanted profile. Several methods have been used to circumvent this problem, including implantation of BF2 [2], preamorphization with heavy ions such as Si or Ge [5]. During ion-implantation, damage is introduced in the silicon substrate which must be annealed out or, at a minimum, be kept out of the vicinity of the junction depletion region [5]. The removal of this implantation damage becomes more difficult as more stringent demands are placed on thermal budgets to maintain shallow dopant profiles. Using solid diffusion sources appears to be another viable technique to form shallow junctions in silicon. Polycrystalline silicon has been extensively studied for this purpose [6 - 8]. The technique offers rapid dopant diffusion in polycrystalline silicon through the grain boundaries so that the material acts as a constant dose diffusion source and prevents

296

substrate damage during ion-implantation. A disadvantage of the technique is that it is difficult to deposit polycrystalline silicon selectively with no deposition occuring on SiO 2 . In this paper we present results on an alternative diffusion source. We have used selectively deposited polycrystalline Si.Gel-x alloys doped using boron ion-implantation as a diffusion source to form ultra-shallow p+-n junctions in silicon. As with polycrystalline silicon, the SixGel-x alloys have rapid boron diffusion along grain boundaries so that the dopant quickly reaches the silicon surface. The advantages of polycrystalline SixGe1-x over polycrystalline Si are in the processing flexibilities SixGel-x offers in forming the junctions. We have shown previously that selective deposition of these films is much easier than that of silicon due to the formation of highly volatile GeO [9]. In addition, Cams, et.al. have shown that SixGel-x alloys have different etch properties than silicon [10]. This means that following junction formation, the diffusion source may be selectively removed making the process directly comparable to ion-implantation without introducing substrate damage in Si. In this work, we have studied the electrical properties of boron doped p+-n junctions formed by diffusion of boron into Si from selectively deposited and implanted polycrystalline SixGel-x alloys. Secondary ion-mass 'spectroscopy (SIMS) has been utilized to obtain as-implanted and annealed boron profiles in Si and SixGel-x. II. EXPERIMENTAL Ultra-shallow p+-n diodes were fabricated on Czochralski grown 0.2-0.45 Q-cm silicon substrates and used to characterize the properties of the diffused junctions. A 3500 A thermal oxide was grown and patterned using conventional photolithography to define the active areas for the diodes. Selective SixGel-x alloys were deposited on the wafers in the active areas to a thickness of 2000 A using a cold-wall, lamp heated rapid thermal processor. A fixed Ge concentration of 30 % (SiO. 7Geo.3) was used in this study. The deposition conditions were optimized to obtain a smooth two-dimensional growth of Si 0 .7 GeO. 3 on Si. The details of the optimization procedures can be found elsewhere [ 11]. For comparison, monitors were fabricated without selective Sio.7GeO. 3 deposition in the active areas. To eliminate boron channeling in Si, the monitor wafers were preamorphized with Ge ions [5]. Boron implantation into SiO.7GeO. 3 was carried out at 10 keV with varying implant doses. For these samples , the implantation energy and dose were chosen to keep the as-implanted profile confined to the polycrystalline layer. A thin oxide was then deposited on all the samples at 450'C followed by rapid thermal annealing in a HeatpulseTM rapid thermal annealer at temperatures between 1000*C and 1100'C. Aluminum was evaporated and patterned on all the wafers. This was followed by a forming gas anneal at 400'C to complete the fabrication process. Samples were also prepared by depositing SixGel-x alloys on bare silicon wafers to monitor the diffused boron profiles by SIMS. III. RESULTS Dopant Profiles Anneal temperature, anneal time, and implant dose all contribute to determining dopant profiles and junction depths during diffusion. The effects of all of these parameters on boron diffusion into silicon from SiO.TGeO.3 has been investigated. Boron implant doses of

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lxl0 15 cm-2 , 3x10 15 cm-2 , and lxl0 16 cm- 2 ; anneal temperatures of 1000TC, 1050'C, and 1 100'C; and anneal times between 10 s and 60 s were investigated. The progression of the boron profile with RTA temperature is shown in Figure 1. Each sample was implanted with lxl016 cm-2 boron at 10 keV and rapid thermal annealed for 10 seconds in an Argon ambient. As shown, the as-implanted profile is confined to the SiO. 7 GeO. 3 layer. Rapid diffusion of boron in the polycrystalline layer during RTA has resulted in a nearly uniform boron distribution in Si0.7GeO. 3 . At the interface between the polycrystalline SiO.7GeO.3 alloy and the crystalline silicon substrate the slope of the boron profile changes due to the decrease in diffusivity as the boron leaves the polycrystalline layer and enters the crystalline substrate. With this high dose implant, the junction depth can be varied over a wide range by small changes in the RTA temperature with junction depths varying between 600 A and 1600 A at a background concentration of lx10 16 cm-3 as the temperature is increased by only 50 0 C. The temperature dependence of the boron dose reaching the silicon for an implant dose of lxl0 16 cm-2 is shown in Figure 2. It is expected that almost all of the boron in silicon will be electrically active at these RTA temperatures. In addition to controlling the dopant profiles with RTA temperature, implant dose may also be used to control the junction depths as well as the peak surface concentration. This is illustrated in Figure 3 with boron profiles following RTA for three different implant doses. Each of the samples was annealed at I 100°C for 10 seconds in an Argon ambient. By simply varying the implant dose, the junction depth has been varied between 1300 A and 4000 A at a background concentration of lxl0 16 cm- 3 and the peak boron concentration has been controlled between 2x1019 cm- 3 , and 2x10 20 cm-3 for an anneal temperature of 1100'C. The amount of boron in silicon as a function of the implant dose is shown in Figure 4. Through proper choice of anneal conditions and implant dose, a wide degree of control over junction depth and boron concentration can be achieved. Electrical Properties To study the electrical properties of the junctions diffused from polycrystalline SiO.7GeO.3, p÷-n diodes were fabricated as described in Section II. Reverse bias I-V characteristics obtained from a 400 A deep, 400 gim x 400 ltim diffused junction before and after forming gas anneal are shown in Figure 5. The junction was formed by implanting boron into SiO.7Ge 0 .3 at 10 keV/3xl0 15 cm- 2 followed by RTA at 1050'C/10 s. The junction depth was determined by SIMS. Also shown for comparison is the reverse bias 14 IV characteristics of an implanted junction. This sample was first implanted with 3x10 cm- 2 Ge at 50 keV to preamorphize the silicon followed by boron implantation at 3x10 15 cm- 2 and 10 keV. RTA was performed at 1100'C for 10 seconds resulting in a much deeper junction of 0.2 gim. As shown, both IV profiles are quite similar before the forming gas anneal with comparable leakage currents and breakdown voltages. After the forming gas anneal, the leakage current of the diffused junction is greatly reduced while that of the implanted sample is only slightly reduced. The low leakage current of the diffused junction is supported by the forward I-V measurements which indicated an ideality factor of 1.05. The reduction in leakage current in the diffused sample following forming gas anneal can be understood by considering the junction under reverse bias. The diffused junction is expected to have many generation centers at the Si 0 .7Ge 0 .3/Si interface and in the 300

polycrystalline layer along the grain boundaries due to unsatisfied bonds. Carriers generated within a diffusion length of the depletion region will be swept across and add to the reverse bias leakage. During the forming gas anneal, some of these unsatisfied bonds will be compensated by the hydrogen atoms, thus reducing the number of generation centers and hence the leakage current. Another interesting feature in Figure 5 is the gradual increase in reverse leakage for the implanted sample that did not exist before the forming gas anneal. This can be attributed to the penetration of aluminum into silicon during the anneal. It should be noted that even though the implanted junction is much deeper than the diffused junction, a 0.2 gim junction should still be considered shallow and a diffusion barrier for Al must be used to avoid this problem. Aluminum penetration has been avoided in the diffused junctions because the effective junction depth is much greater than the actual junction depth due to the addition of the polycrystalline Sio.7Ge0.3 layer. As shown in Figure 5, both the diffused and implanted junctions exhibit a fairly high breakdown voltage of approximately 23 V.

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interface. Then, the interface and the polycrystalline material should both contribute generation centers in the depletion region causing the increase in reverse bias leakage. An effective means of verifying the above behavior is to plot the reverse bias leakage current as a function of inverse temperature. The leakage current of a pn-junction diode can be expressed in terms of two components : Igen due to generation of carriers within the depletion region and ldiff due to diffusion of carriers generated outside the depletion region. These current components can be expressed as [12]: (1)

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which can be used to determine the dominant leakage current mechanism of pn junction diode. The reverse bias leakage current of a diffused junction formed by implanting boron into SiO.7GeO.3 at 10 keV/lx10 16 cm- 2 is shown as a function of 1/T in Figure 6 for two reverse bias voltages of -5 V and -15 V. These voltages were chosen to bias the diode below and above the kink observed in the INV profile of Figure 5. The -5 V bias produces a curve which clearly illustrates generation dominated current at low temperatures with a slope of 0.59 and diffusion dominated current at high temperatures with a slope of 0.93. At a -15 V bias, however, generation current dominates throughout the entire temperature range with a slope of 0.55 at low temperatures and 0.65 at higher temperatures. The offset of the two curves also shows an increase in the magnitude of the generation component of leakage current. Even though this appears to be a problem, it should be noted that the kink occurs at voltages much higher than supply voltages considered for submicron MOS transistors. Furthermore, even with the kink at -8 V, an ultra-shallow - 400 A deep diffused junction exhibits a lower leakage than a much deeper (- 2000 A) implanted junction throughout the entire voltage range as shown in Figure 5.

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. IV. CONCLUSIONS In this paper, we have demonstrated the feasibility of forming high quality shallow p+n junctions by diffusion from selectively deposited, boron implanted polycrystalline SixGel.x alloys. This was confirmed by forward bias and reverse bias I-V and I-T measurements. We have shown that a wide degree of control can be achieved over the junction profiles by varying the implant dose and the RTA temperature. In the fabrication of submicron MOSFETs, we can utilize implanted polycrystalline SixGel-x as a diffusion source in two different ways to form shallow source/drain junctions: i) we can leave the selectively deposited Si0.7 Ge0.3 on the junctions after dopant drive-in to raise the junctions which was the subject of this study. Here, SixGeIx can serve as a sacrificial layer during silicide formation and eliminate silicon consumption below the gate level, ii) SixGel.x can be removed after dopant drive-in making the process directly comparable to ion-implantation. If desired, selective removal of SixGeIx can be also be followed by in-situ doped selective Si epitaxy to raise the junctions. V. ACKNOWLEDGEMENTS The authors would like to thank Barbara Neptune of MCNC for ion-implantation, Dieter Griffis and Jerry Hunter for SIMS analysis, and Joan O'Sullivan, Richard Kuehn, and Henry Taylor for assistance in sample preparation. This work has been partially supported by NSF Engineering Research Centers Program through the Center for Acvanced Materials Processing (Contract # CDR-8721505) and SRC Microstructures Science Program (Grant 90-SJ-081).

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VL REFERENCES C. M. Osburn, "Formation of silicided, ultra-shallow junctions using low thermal budget.processing", Journal of Electronic Materials, vol. 19, P. 67, 1990. 2. M. C. Ozturk, J. J. Wortman, and R. B. Fair, "Very shallow p+-n junction formation by low-energy BF2 ion-implantation into crystalline and germanium preamorphized silicon", Applied Physics Letters, vol. 52, p. 963, 1988. 3. P. G. Carey, T. W. Sigmon, R. L. Press, and T. S. Fahlen, "Ultra shallow high concentration boron profiles for CMOS processing", IEEE Electron Device Letters, vol. EDL-6, p. 291, 1985. 4. S. N. Hong, G. A. Ruggles, J. J. Wortman, E. R. Myers, and J. J. Hren, "Characterization of the ultra-shallow p+-n junction diodes fabricated by 500-eV boron ion-implantation", IEEE Transactions on Electron Devices, vol. 38, p. 28, 1991. 5. M. C. Oztfirk, J. J. Wortman, C. M. Osburn, A. Ajmera, G. A. Rozgonyi, E. Frey, W. K. Chu, and C. Lee, "Optimization of the germanium preamorphization conditions for shallow-junction formation", IEEE Transactions on Electron Devices, vol. 35, p. 659, 1988. 6. C. Hill and S. K. Jones, "Modelling diffusion in and from polysilicon layers", in MRS Symposia Proceedings, Vol. 182, p. 129, 1990 7. K. Park, S. Batra, S. Banerjee, and G. Lux, "Comparison of amorphous and polycrystalline silicon films as a solid diffusion source for advanced VLSI processes", in MRS Symposia Proceedings, Vol. 182, p. 159, 1990 8. B. Raicu, M. I. Current, W. A. Keenan, D. Mordo, R. Brennan, and R. Holzworth, "Supersaturated p-type polycrystalline films produced by rapid thermal annealing of high dose boron implants for interconnects and shallow junction diffusion sources", in MRS Symposia Proceedings, Vol. 182, p. 153, 1990 9. Y. Zhong, M. C. Oztiirk, D. T. Grider, J. J. Wortman, and M. A. Littlejohn, "Selective low pressure chemical vapor deposition of Si/Ge alloys in a rapid thermal processor using dichlorosilane and germane", Applied Physics Letters, vol. 57, p. 2092, 1990. 10. T. K. Cams, S. S. Rhee, G. K. Chang, and K. L. Wang, "The study and application of a selective etchant in GeSi/Si Heterostructures", in Proceedings of Techcon'90, p. 297, 1990 11. M. Sanganeria, M. C. Oztiirk, G. Harris, D. H. Maher, D. Batchelor, J. J. Wortman, B. Zhang, and Y. L. Zhong, "Optimization of Process Conditions for Selective Deposition of Polycrystalline Si/Ge Alloys in a Rapid Thermal Processor", To be published in proceedings of Third International Symposiun on ULSI, Science and Technology. 12. A. S. Grove, Physics and Technology of Semiconductor Devices. John Wiley & Sons, 1967. 1.

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ENHANCED SILICIDE FORMATION USING SELECTIVE EPI GROWTH ON SOURCE/DRAIN FOR DEEP SUBMICRON CMOS L.K. Wang, D. Moy, J. A. Ott and T. S. Kuan IBM Research Division T. J. Watson Research Center Yorktown Heights, NY 10598 Thin titanium silicide formation on very shallow junctions is often impeded due to retardation of phase transition and dopant effect. A selectively deposited epi can provide an undoped silicon buffer layer to eliminate these two effects. In this experiment, deep submicron CMOS devices are fabricated using selective epi on very shallow source/drain. The electrical characteristics of the fabricated devices will be presented. INTRODUCTION Shallow source/drain junctions are required to fabricate deep sub-micron CMOS devices. However such junctions may be too resistive without a layer of low-resistivity silicide [1]. The formation of low sheet resistance, ultra-thin titanium silicide on ultra-shallow junctions can be very difficult. Both the reduction of the thickness of the silicide film and the decrease in the linewidth of the titanium silicide of the polysilicon gates or diffusions can retard the transformation from the high resistivity C-49 phase to the low resistivity C-54 phase. As shown in Figure 1, the silicide sheet resistance increases very rapidly when the linewidth and thickness are reduced. To reduce the sheet resistance, thicker titanium has to be used which will consume more silicon in the junction region to form the silicide. This will introduce both the junction leakage as well as higher silicide to N + contact resistance due to the consumption of the highly doped region of the junctions [2]. Furthermore a highly doped n-type source-drain diffusion can additionally impede the silicide formation at lower formation temperatures. Figure 2 shows the effect of the n + junction implant dose on the sheet resistance of the silicide formed over the n + junctions. In order to form a low sheet resistance silicide on very shallow junctions without consuming silicon from the junctions, we use a selective silicon epi growth (SEG) process to deposit a layer of undoped silicon epi on the source/drain junctions of CMOS devices for thicker titanium silicide formation.

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Figure 1 The effect of titanium thickness and linewidth on silicide sheet resistance over undoped silicon.

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PROCESS The selective silicon epi is deposited in a Applied Materials AMC-7810 cylindrical epitaxial reactor (Figure 3) at 850°C under reduced pressure [3,4,5]. The pre-deposition cleaning is accomplished by a short HCI-H 2 etch followed by a selective deposition of silicon facilitated by the use of SiC14 in H 2 carrier gas. A silicon epi layer, typically 30nm thick, is deposited to provide a 35nm thick titanium silicide. Thicker epitaxial silicon can be deposited if a thicker titanium silicide layer is desired.

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Figure 3 Selective silicon epi deposition system.

In this experiment silicon epitaxial layer is grown selectively on CMOS devices with 800 nm arsenic N + junctions formed by a 1000°C RTA process. A 30nm thick Si 3 N4 is deposited and followed by RIE to form a sidewall for the selective epi process after the N + junction annealing. The P + junctions are formed after the epi deposition to reduce the drive-in of the boron junctions during the epi growth. A germanium amorphization implant followed by a BF 2 implant is used for the P + junction process. The annealing is attained by a 950°C RTA process with a junction depth of around 100 nm including the thickness of the selective epi. A 25nm thick titanium film is deposited to form a self-aligned titanium silicide layer with a two step RTA annealing process. The final diffusion sheet resistance is around 5 fl/El for both N+ and P+ junctions. The TEM micrographs of the devices with SEG raised source/drain are shown in Figure 4(a) and (b) 0.15pm Figure 4(a) Cross-sectional image of a n-FET with a 30-nm-thick, selective epi on the source and drain.

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(b) SEG source/drain n-FET with a 0.3,um gate width.

The SEG-CMOS device characteristics are compared to the non-siuicide and non-epi control devices. The SEG devices show less junction leakage current and lower diffusion sheet resistance. The I-V characteristics of the SEG devices are essential the same as the control devices (Figures 5(a) and (b)). ID

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However the N + /P + diffusion sheet resistance of the SEG devices has been re-

duced to around 5 Q/O- from the 10-40 Q/O of the non-epi N + diffusion due to the elimination of the dopant effect during the silicidation process. There is no line width dependence on the sheet resistance in our measurement even for the narrowest N + diffusion at 0.5 pm. In summary, we have demonstrated a method to use selective epi growth to form low sheet resistance silicide over ultra shallow and narrow junctions and

polysilicon gate for deep sub-micron CMOS devices. REFERENCES [1] S. P. Muraka, D.B. Fraser, A. K. Sinha,and H. J. Levinstein, IEEE Trans. ED-27, (1980) p.1409. [2] Y. Taur, J. Y-C Sun, D. Moy, L.K. Wang, B. Davari, S.P. Klepner and C. Y. Ting, Trans. ED-34, (1987) p. 57 5 . [3] H.K. Park, J. Vac. Sci. Technol. A2 (1984) p. 26 4 . 14] B. Ginsberg, Ext. Abs. Electro. Chem. Soc. Fall Meeting (1987) p.991. [5] T.O. Sedgwick, Appl. Phys. Lett. 54, (1989) p.2689.

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OPTIMIZATION AND CHARACTERIZATION OF LPCVD TiB2 FOR ULSI APPLICATIONS C.S. Choi*, G.A. Ruggles*, C.M. Osburn*,+, and G.C. Xing** *Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695 Department of Material Science and Engineering, North Carolina State University, Raleigh, NC 27695 +MCNC, Center for Microelectronics, P.O.Box 12889, Research Triangle Park, NC 27709 The chemical vapor deposition of TiB 2 from gaseous mixtures of TiCIL, B2H 6 and H2 onto various substrates was studied. Experimental depositions of films were carried out in a cold wall system over a broad range of temperatures, pressures and input gas flow rates. The as-deposited films are very fine grained polycrystalline or amorphous, and the films RTA-annealed above 900'C are crystalline TiB 2 . Below 550'C, surface reactions are the dominant factor for the kinetics of TiB 2 deposition, while mass transport is a limiting step for deposition above 550'C. At higher temperatures the deposition rate increases linearly with flow rate and total pressure, suggesting the deposition mechanism is reactant limited. The B/Ti ratio determined approaches the stoichiometric value of 2 in higher temperature films, while the presence of excess boron and chlorine was detected for low temperature films. Stoichiometric TiB 2 films were deposited over a wide range of input gas mixture. Depletion effects of input gas were observed at low flow rate and high pressure where the residence time of reactants is longer than 10 sec. INTRODUCTION Because of its interesting properties, titanium diboride has been investigated and commercially used for several applications such as: crucible materials for melting metals, thermocouple protection tubes in melting metal, abrasives, protective coatings, high temperature electrodes in nuclear fusion applications, and cathodes or containers in aluminum reduction cells. Nicolet has already pointed out titanium boride as an interesting potential material for mictoelectronic device fabrication [I]. The high conductivity and chemical inertness at high temperature leads TiB 2 to be considered as a potential candidate for a diffusion barrier or gate/diffusion cladding. The resistivity of bulk polycrystalline TiB2 (=101Q-cm) [2] and single crystal (6pQ-cm) [31 is lower than that of other potential barrier materials like silicides or nitrides and only slightly higher than that of tungsten. Shappirio et al. showed that ZrB2 is stable in contact to aluminum up to 600'C [4]. Feldman et al. used TiB2 as an electrode in polycrystalline silicon thin film solar cells [5]. Several different methods have been employed to produce TiB 2 thin films: i.e. sputtering [4, 6-10], reactive ion plating [11], laser induced vapor-phase synthesis [12], and reaction of Ti-B thin film couples [13]. Due to stringent ULSI requirements for low thermal budget, conformal step coverage, and high purity films, low pressure chemical vapor deposition is a good choice for producing high quality TiB 2 films.

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Chemical vapor deposited polycrystalline TiB 2 films have been initially obtained from a source gas of TiCI4/BC13/H2. Peshev et al. deposited TiB2 films in the temperature range from 1000-1400'C [14]. A pyrolytic deposition of TiB 2 was performed at 1400 1600'C and at 3-5 Torr [15,16]. Models for the deposition process were developed based

on the experimental results of deposition rates and efficiencies, coupled with thermodynamic calculations for CVD TiB2 [17].

Pierson et. al. reported that the

atmospheric CVD at 900-950'C produced boron-rich titanium diboride even at a stoichiometric input gas [18]. A deposition study combined with a thermodynamic study suggested that equilibrium is approached under typical TiB2 CVD conditions, and that the deposited phases are far more sensitive to changes in system chemistry than they are to changes in temperature [19]. A glow discharge deposition was performed at temperatures from 480 to 6500 C, resulting in as-deposited resistivity ranging from about 200-450gi)-cm [20]. A chemical vapor deposition of titanium diboride using the reaction of TiCI4 with B2H6 in a hydrogen atmosphere in the temperature range of 600-900*C temperature was also reported [21]. The deposition rate of the B2 H6 reaction was considerably greater than that of the BC13 reaction, and it proceeded at a lower temperature; however, the deposition rate was negligible below 700'C, and above 1000'C the deposition tended to be powdery, probably the result of vapor phase nucleation. This work consists of experimental results for the mechanism of TiB 2 film deposition at various temperatures, pressures, gas mixtures, and flow rates, as well as analysis of TiB 2 films. EXPERIMENTAL TiB 2 films were prepared by chemical vapor deposition using TiC14 , B2H 6 and H2 source gases. A detailed description of the cold-wall CVD reactor and is given in a separate publication [22]. Titanium boride films were deposited on bare Si, or thermally oxidized silicon wafers. Chemical vapor deposition of TiB 2 for this work was done over a wide range of process temperatures (375'C - 750 0 C), pressures (0.5 Torr - 5 Torr), and total flow rates (69 -550sccm). The B/B+Ti ratio of the input gases was varied from Ti rich (B/B+Ti = 0) to B rich (B/B+Ti = 1). Only one parameter was varied for each set of experiments, while the others were held at a nominal value. The thicknesses and surface roughness of the TiB2 films were measured using a Dektak profilometer after etching through the film with a 30% H 202 solution at room temperature for 1-10 min to provide a step at the measurement point. The thickness of some samples was verified using Rutherford backscattering spectroscopy (RBS) and/or cross-sectional Transmission Electron Microscopy (TEM). The thickness of films deposited below 600*C was measured via angle lapping and cross sectioning SEM. The composition and phases of the films were determined by Auger Electron Spectroscopy (AES), X-ray Photon Spectroscopy (XPS), and X-ray diffraction. The optimized deposition conditions were achieved through a careful characterization of the as-deposited and annealed TiB 2 films. This optimization required measuring the following parameters; phases and crystallinity, stoichiometry, resistivity, impurity incorporation into the films, deposition rate and uniformity.

311

RESULTS AND DISCUSSION Film Chemistry X-ray diffraction was employed to identify the phases present in the as-deposited films. No X-ray diffraction lines of TiB 2 were observed at a deposition temperature up to 750'C, suggesting the presence of a very fine grained polycrystalline or amorphous phase for the as-deposited films. As shown in Fig. 1, the films RTA-annealed above 900'C gave patterns corresponding to the TiB2 structure, and the intensities of the TiB 2 peaks increased as the annealing temperature was increased. The X-ray data indicated that the average grain size in TiB 2 film grows with annealing temperature. Only the as-deposited sample showed a silicon substrate line, which is probably due to a stress build-up during film deposition. The grain-size growth and the resistivity reduction with annealing temperature are discussed in detail elsewhere [23]. In addition, XPS, coupled with depth profiling, was performed to find the phase(s) and chemical composition of the films. A typical result for a stoichiometric TiB 2 film deposited at 650'C and 5 Torr is shown in Fig: 2. No phase and composition change in the bulk film were noticed after rapid thermal anneal at 1150 0 C, 10 sec [24]. The film appears to be pure TiB 2 , with some oxygen present only at the surface, presumably due to surface oxidation. Examination of the B Is peak in detail revealed that only Ti-B bonding was present in the film, with the exception of the surface, where some B-O bonding is also present, revealing the formation of BxOy• The effect of deposition time on deposition rate. The dependence of the film thickness on the deposition time was examined in Fig. 3. The TiB 2 films were deposited on silicon, or thermal oxide substrates under a typical deposition condition: 600'C, 1 Torr, TiC14 = 25 sccm, and 10% B2 H 6 in H 2= 250 sccm (B/B+Ti= 0.67). The film thickness increased linearly with the growth time, and the deposition rate was independent of the substrate (Si vs. SiO 2 ). Some evidence of an incubation time (=20 sec) was observed. Since this time is very small compared to a typical deposition time (6 min), the growth rate was calculated simply by dividing the film thickness by the growth time in this work. The effect of temperature on the deposition. The effect of temperature on deposition rate of TiB 2 was studied as shown in Fig. 4. The depositions of TiB 2 were done at 3 Torr, B/B+Ti= 0.67 in the temperature range of 375 - 750 'C. This graph contains an Arrhenius plot of the logarithm of the deposition rate as a function of reciprocal temperature. As can be seen in this figure, two distinct regimes of deposition kinetics are evident. From standard CVD theory, the presence of the two regimes is defined by the type of controlling reaction rate; if the surface reaction is rate limiting, as is often the case at low temperature, the deposition rate will be a strong function of deposition temperature. If the rate limiting step is either reactant limited or diffusion controlled, the temperature dependence will be slight. As can be seen from the figure, below 550'C surface reactions are apparently the dominant factor for the kinetics of TiB 2 deposition, while mass transport is a limiting step for deposition above 550'C. Activation energies for deposition are 1.36 eV, and 0.31 eV for low and high temperature deposition, respectively. The reported value of the activatic n energies for TiB 2 deposition from BC13, TiCI4 , and H2 source were 1.74 eV and 0.17 eV [25].

312

Figure 5 shows the B/Ti and the Cl/Ti mole ratios as a function of deposition temperature. The B/Ti ratio of films was determined by AES coupled with depth profiling. A 3 KeV Ar beam was used for sputtering the film. The lack of a titanium diboride standard did not allow us to calibrate the B/Ti ratio precisely. Instead, the sensitivity factors of metallic titanium and metallic boron were adopted to quantify the ratio. AES analysis of the these films indicated the presence of excess boron throughout the bulk for films deposited at low temperatures. For example, the B/Ti ratio for a TiBx film deposited at 500'C was found to be 2.6 rather than the 2.0 value obtained for higher deposition temperatures. In addition, during wet etching, the films deposited at temperatures below 600'C, could not be completely removed. The residual layer, which was not completely etched in H 2 0 2 , is believed to result from concentration of a boron phase as the boron-rich titanium boride film is etched, ultimately resulting in a layer which resists further etching. Thus, thickness data were obtained from cross-sectional SEM after an angle lapping. As the deposition temperature increases, the B/Ti ratio approaches the stoichiometric value of 2, within the reasonable uncertainty of the AES sensitivity factors, and stays constant at higher temperatures. Pierson et al. also found boron-rich films deposited at 600'C or below and more stoichiometric films at higher temperature [21]. In addition to the problem of excess boron, a large Cl content was observed in low temperature films as well. At 6000 C and above the Cl was at the detection limit for EDS (2%). The decomposition of the chlorides at lower temperature is presumably not efficient, so that the films containing chlorine and excess boron are deposited. The benefit of higher temperature deposition in producing purer and more stoichiometric films is clear, and qualitatively in agreement with the thermodynamic calculations. The effect of input gas mixture on deposition. The deposition rate of titanium boride films was measured for the films deposited at 600-C, 3 Torr for 6 min. The B/B+Ti ratio of the input gas mixture was varied from 0.0 to 0.8 at a constant total flow rate of 550 sccm. In the temperature range 375 - 750'C, a violet colored film was deposited on the cold wall and the color changed to white when the chamber door was opened. The deposition on the wall was more pronounced in lower total pressure runs, in which the deposition efficiency is lower. It is believed that the observed films were titanium subchloride(s) because both TiCI3 [20, 25, 26] and TiCI 2 [21] are reported as stable substances below 440 and 475°C respectively. One interesting observation is the reaction between a Si substrate and the reactant gas in a CVD system containing only TiC14 (B/B+Ti=0),'since TiSi 2 could form. In this work, no discernible depositions were observed when 75 sccm of TiCI4 and 925 sccm of H 2 were introduced at either 375°C or 600'C, 3 Torr for 20 nin. Reynolds et al. also found no reaction at 627°C when TiCI4 was introduced over a Si wafer; however he did form TiSi 2 , and simultaneously etch Si above 827'C over the pressure range of I750mTorr [27]. Boutevitle et al. used a hydrogen reduction of TiCI4 in the temperature range of 700-1000'C and a total pressure of 0.75 Torr to form titanittm silicide selectively on Si [28]. The deposition rate and B/Ti atomic ratio determined via AES are plotted as a function of the B/B+Ti ratio in the reactant gas mixture in Fig. 6. The B/Ti ratio and the deposition rate were found to be dependent on the input gas ratio. No deposition is observed at an input gas mixture of B/B+Ti=0 (TiCI 4 only). On the other hand, the films deposited at B/B+Ti=0.8 were very nonuniform in composition and color. For this boronrich input gas mixture, the B/Ti ratio in the film increases from 2.4 to 9.9 along the

313

direction in which the input gases travel, indicating a depletion of TiCl 4 . The peak in deposition rate occurs close to an input gas ratio corresponding to stoichiometry (0.67). Such a peak in deposition rate from a fixed total flow system could be expected from a highly-efficient, or reactant-limited process. However, it is difficult to conclude whether there is a true maxima in the B/Ti ratio at B/B+Ti = 0.67 in the input gas, or if the data represent noise in the AES measurements. The films were found to have a constant, nearly-stoichiometric B/Ti ratio over a wide range of input gas mixture ratios ranging from 0.4 to 0.71. This result indicates that the window to deposit a single phase TiB 2 with very limited amount of secondary deposits (e.g. < 0.1 %) was wide. The effect of input gas flow rate on deposition. The deposition rate at 600°C increases linearly with total flow rate, from 70 to 550 sccm, as shown in Fig. 7. However the TiB2 thickness (deposition rate) also varies along the gas flow direction as shown in Fig. 8. For flow rates below 140 sccm, the thickness of the film decreases monotonously along the substrate in the direction of gas travel; at higher flow rates the film thickness maximum moves toward the center of the wafer. For the transport of gaseous species between the bulk gas and the deposition surface, it is usually assumed that a laminar boundary layer lies between the turbulent bulk gas flow and the deposition surface, and that the diffusion of gaseous species through the laminar boundary layer is a possible rate-limiting step. Typically two distinct types of mass transport limitations are associated with reactant flux into the reaction chamber, and the combination of these two establishes the mass transport limiting aspects of a reaction taking place in a given open tube system. The first depends entirely on the rate of introduction of gaseous reactant into the chamber. The second depends on the movement of this introduced mass to all portions of the reaction chamber, particularly the reaction site, and is governed by the system geometry. The average linear gas stream velocity is typically computed in a hot wall system to provide a normalization of the geometry [29]. However, it is practically very difficult to get a meaningful value of the linear gas stream velocity. in a cold wall system due to the complex reactor geometry. In this work, flow rates are used for analysis, instead of linear gas stream velocities. The residence time of the input gas in a reactor is defined as t = 60VP/f, where t = residence time (sec), V = volume of the reactor (1), f = flow rate (SLPM), P = pressure (Atm). At a low flow rate, the residence time of the reactant introduced into the reaction chamber may be long in comparison to chemical reaction or mass transfer rates. Hence the chemical system in the reactor may be expected to approach equilibrium. Once the system approaches equilibrium, the input gas flow rate becomes the mass transport rate. In other words, in this regime the deposition rate is determined entirely by the input gas flow rate, and therefore is proportional to the flow rate. In Fig. 7 the deposition rate is a linear function of the flow rate. On the other hand, as the reactants flow along the length of the reaction chamber, a portion of the reactant gas is consumed. The partial pressure of the reactant gas is thus lower near the outlet end of the reactor, and the deposition rate is reduced there if all other deposition parameters remain constant. The calculated residence time for the system used here is shown in Table I. As clan be seen in the table, the residence time increases as the flow rate decreases. When t ie flow rate or gas stream velocity is low, i.e. the residence time is long, depletion of input gases might be expected to occur. Indeed, as can be seen in

314

Table 1. The residence time at various input gas flow rates 600'C, 1 Torr, B/B+Ti--0.67 flow rate (sccm) residence time (sec)

68.8 21.9

103.1 14.7

137.5 11.0

275 5.5

550 2.8

Fig. 8, for total flow rates below 137.5 sccm the thickness of TiB 2 decreases along the direction of gas travel, indicating depletion of the input gas, while at high flow rates with short residence times, the thickness is maximum at the center of the wafer and decreases radially. The location of the maximum thickness is observed to shift from the wafer edge nearest the gas injector to that of the pumping port as the flow rate (linear gas stream velocity) increases. This is probably because that it takes longer for the input gas to approach the deposition temperature at high flow rate. The effect of pressure on deposition A series of experiments to study the dependence of pressure on deposition of TiB 2 were performed. The total pressure of the chamber was varied from 0.1 to 4 Torr by throttling the exhaust valve. The other deposition variables were fixed at 600'C, 250 sccm total flow rate having B/B+Ti = 0.67 and 6 min deposition time. Figure 9 shows the dependence of the deposition rate of TiB 2 films on the total pressure. No deposition was detected at 0.1 Torr, even using 4 point probe sheet resistance measurement, which should be sensitive to the presence of ultra thin film. A meaningful value of deposition rate could not be obtained at a pressure of 4 Torr due to poor thickness uniformity. As can be seen in the figure, the deposition rate linearly increases with the input partial pressure of TiCl4 and B 2 H6 . The film thickness variation on the wafer along the direction of gas flow is plotted in Fig. 10, where evidence of gas depletion is seen above 1 Torr. The location of the maximum in the film thickness shifts from the leading(input) to the trailing(exhaust) edge as the pressure decreases from 2 Torr to 0.5 Tort. For a horizontal CVD reactor, the boundary layer thickness, 5, can be determined using the equation: 8 = (Dr d / Re)1/ 2 ,where Dr is the diameter of the tube, d is the axial distance along the tube, and Re is the Reynolds number. Evidently Dr and d are independent of the pressure. The Reynolds number is calculated using the formula: Re=Dd x L / DA, where Dd is linear gas stream velocity, L is a characteristic length descriptive of the flow field which, for the case of gas flow in a tube, would be equal to the diameter of the tube, and DA is diffusion constant. Because L is independent of pressure and both the linear gas stream velocity and the diffusion constant are inversely proportional to the system pressure, the Reynolds number and consequently boundary layer thickness are independent of the pressure [30]. However the deposition rate increases linearly with the partial pressure of the reactants, which is proportional to total pressure in this experiment. The residence time of the input gas in the chamber and deposition efficiency are calculated in Table. II. The deposition efficiency is defined as a ratio of the mole amount of Ti deposited on the heated area to the mole amount of Ti in the input gas based on the input gas flow rate. The residence time of reactant and the deposition efficiency both increase with the pressure. The gas depletion effect discussed earlier in the flow rate experiments is observed again in these pressure experiments for long residence times.

315

Table II. The residence time and deposition efficiency at various pressures 600'C, 275sccm total flow, B/B+Ti=0.67 total pressure (orr) residence time (sec) deposition efficiency (%)

.5 2.8 0.75

1.0 5.5 8.1

1.5 8.2 13.5

2.0 11.0 18

At the total pressure of 2 Torr where the residence time is 11 sec, the input gas depletion effect is very pronounced, i.e. the film thickness on the wafer decreases along the direction of gas flow. A more uniform wafer, having the thickest film more symmetrically at the center, is obtained at the pressure of 1 Tort. It is very interesting to note the shift of the thickest film position from the front of the wafer at 2 Torr toward the back at 0.5 Torn, presumably caused by the low pressure gas taking longer (travelling farther) to achieve thermal equilibrium. CONCLUSIONS The as-deposited films are very fine grained polycrystalline or amorphous. However, the films RTA-annealed above 900'C gave patterns corresponding to the TiB 2 structure. Except for an oxidized layer at the surface, the films appear to be pure TiB 2 when analyzed via XPS. The film thickness increased linearly with the growth time, and the deposition rate was independent of the substrate (Si vs. Si0 2). Two distinct regimes of deposition kinetics were evident in different deposition temperature ranges. Below 600'C, surface reactions are found to be the dominant factor for the kinetics of TiB 2 deposition, while mass transport is the limiting step for deposition above 600'C. Activation energies for deposition were determined to be 1.36 eV, and 0.31 eV for low and high temperature deposition, respectively. The presence of excess boron and chlorine was detected throughout the bulk for low temperature films. As the deposition temperature increased, the B/Ti ratio approached the stoichiometric value of 2, and remained constant at higher temperatures; furthermore the Cl content was reduced. Over a wide range of input gas mixture ratios from 0.4 to 0.71, the films were found to have a constant, nearlystoichiometric B/Ti ratio. This result indicates that the window to deposit single phase TiB 2 is quite wide. The peak in deposition rate was found to occur close to an input gas ratio corresponding to stoichiometry (0.67), suggesting that the deposition mechanism was reactant limited. The deposition rate increased linearly with flow rate and pressure, indicating that the mechanism for deposition was equilibrium limited in the range of flow rate 70 - 550 seem. Input gas depletion effects were observed at low flow rates and high pressures where the residence time of reactants was longer than 10 sec. A surface reaction limited mechanism was not observed in these experiments, even at the maximum flow rate of 550sccm. The roughness of the films increased linearly with the thickness. To get stoichiometric and uniform films in the reactor used in this study, the optimized process condition was 600'C, 1 Torr, total flow rate of 550 sccm with an input gas mixture of B/B+Ti = 0.67. ACKNOWLEDGEMENTS This work has been supported by the Semiconductor Research Corporation (Contract #89-MP-132) and MCNC. The authors also gratefully acknowledge helpful discussion with A. Reisman, and J.J. Wortman of the Nanometer Engineering Laboratory

316

of NCSU/MCNC and Stephen Bobbio at MCNC. They would like to thank C.U. Ro, A. S. Shah, Susan K. Hofmeister and J.D. Hunn for technical assistance. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [91 [10] [11] [12] [13] [14] [15] [16] [17] [181 [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30]

M.-A. Nicolet, Thin Solid Films, 52, 415 (1978). G.V. Samsonov, B.A. Kovenskaya, and T.I. Serebryakova, Izv. Vyssh. Ucheb. Zaved. Fiz. 14, 19 (1971). A.D. McLeod, J.S. Haggerty, and D.R. Sadoway, J. American Ceramic Society, 67, No. 11 705 (1984). J.R. Shappirio, J.J. Finnegan, R.A. Lux, J. Vac. Sci. Technol. A3, 2255 (1985). C. Feldman, F.G. Satkiewicz and N.A. Blum, J. Less-Common Met., 82, 183 (1981). G. Ryan, S. Roberts, G.J. Slusser and E.D. Adams, Thin Solid Films, 153, 329 (1982). T, Shikama, Y. Sakai, M. Fukutomi and M. Okada, Thin Solid Films, 156, 287 (1988). T. Shikama, Y. Sakai, M. Fujitsuka, Y. Tamauchi, H. Shinno and M. Okada, Thin, 164, 95 (1988). T. Larsson, H.-O Blom, S. Berg, and M. Ostling, Thin Solid Films, 172, 133 (1989). H.-O Blom, T. Larsson, S. Berg, and M. Jostling, J. Vac. Sci. Technol. A 6 (3), May/Jun, 1693 (1988). T. Sato, M. Kudo, and T. Tachikawa, Denki Kagaku 55 No.7, 542 (1987). J.D. Casey and J.S. Haggerty, J. Materials Science, 22, 737 (1987). C. Feldman, F.G. Satkiewicz and G. Jones, J. Less-Common Met., 79, 221 (1981). P. Peshev and T. Niemyski, J. Less-Common Met., 10, 133 (1965). R.E. Gannon, R.C. Folweiler, and T. Vasilos, J. American Ceramic Society, 46, No.10 496 Sept. (1963). J.J Gebhart and R.F, Cree, J. American Ceramic Society 48, No.5 May , 262 (1965) T.M. Besmann and K.E. Spear, J. Electrochem. Soc., 124, 790 (1977). H.O. Pierson and A.W. Mullendore, Thin Solid Films, 95, 99 (1982). E. Randich and T.M. Gerlach, Thin Solid Films, 75, 271 (1981). L.W. William, Appl. Phys. Lett., 46 (1), 43 (1985). H.O. Pierson and A.W. Mullendore, Thin Solid Films, 72, 511 (1980). C.Choi, G.A. Ruggles, C.M. Osburn, P. Shea, and G.S. Xing, Proceeding of MRS symposium, Advanced metallization in microelectronics, Vol 181, 455 (1990) C.S. Choi, G.C. Xing, G.A. Ruggles, and C.M. Osburn, accepted by J. Appl. Phys. (1990). T.M. Besmann and K.E. Spear, J. Electrochem. Soc., 124, 790 (1977). R.J. H. Clark, The chemistry of Titanium and Vanadium, Elsevier, NY, 40 (1968). N. Nakanishi, S. Mori, and E. Kato, J. Electrochem. Soc., 137, No.], 322, (1990). G.J. Reynolds, C.B. Cooper III and P.J. Gaczi, J. Apple. Phys. 65, No.8, 3213, (1989). A. Bouteville, A. Royer, and J.C. Remy, J. Electrochem. Soc. 134, No. 8, 2080, (1987). A. Reisman and M. Berkenblit, J. Electrochem. Soc. 113, No. 2, 146 (1966). A. Reisman, private communication. 317

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320

IDEAL METAL/SILICON CONTACT FORMATION BY CLEAN-NITROGEN-SEAL PROCESSING H.

Kuwabara,

M. Otsuki and T.

Ohmi

Department of Electronics. Faculty of Engineering, Tohoku University, Sendal 980 Japan Fax:(022)224-2549, Phone:(022)224-2649 ABSTRACT The formation of high quality metal/silicon contacts has been demonstrated by a clean-nitrogen gas seal processing. Al, Cu, and Ti thin films were deposited on either n-type or p-type Si substrates by a low energy bias sputtering process. The J-V characteristics of Schottky contacts and Ohmic contacts were evaluated. The experimental results show that the sum of the Schottky barrier height for n-type Si and p-type Si is equal to the bandgap of Si. The dependence of Schottky barrier heights on substrate orientation is also demonstrated. As a result, it is apparent that Schottky barrier height for ntype (lO0)Si is larger than that for n-type (lll)Si by about 0.02eV, and Schottky barrier height for p-type (lO0)Si is smaller than that for p-type (lll)Si by about 0.02eV. The exponential dependence of contact resistance on Schottky barrier height is made clear and very low contact resistance of 3x10-O Q.cm2 is achieved without any heat treatment. Thus the formation of ideal metal/silicon contacts has been verified. Introduction The formation of Ideal metal/silicon contacts and ideal SiO 2 /Si interfaces are most essential to achieve high performances in semiconductor devices. It is well known that native oxide grows very rapidly on Si surfaces and affects the crystallinity of epitaxially grown Si films or the electrical characteristics of metal/silicon contacts such as Schottky contacts and Ohmic contacts[l], [2]. Therefore, it is necessary to suppress the native oxide growth on Si wafer surfaces for highly reliable semiconductor manufacturing. It was reported that the native oxide growth occurs under the coexistence of oxygen and water[il], which results in the increase in the contact resistance as well as the increase in their nonuniformity and fluctuations. The

321

purpose of this paper is to realize ideal metal/silicon contact by isolating the bare Si wafer surface from the clean room air which contains oxygen and water. For this purpose, we have developed new wet cleaning equipment where ultrapure water and a diluted HF vessel are sealed by cleanAs a result, reduction in Al, Cu, Ti/n--Si N2 -gas[2]. contact resistances down to 3.3-3.8x10-7 Q.cm2 and the J-V -characteristics of Schottky diodes identical to those derived from the thermionic emission theory have been obtained without any post-metallization thermal annealing. Thus the effectiveness of the clean-nitrogen seal process has been demonstrated. Experimental (100) and (111) oriented Si wafers were used for the experiment. Patterning of contact holes was carried out by wet chemical etching to avoid damage generation by RIE. After cleaning in boiling H2 S04/H 2 0 2 solution and rinsing in ultrapure water, Si wafers were transported to clean-N2 -gas sealed wet cleaning station. Then, the wafers were chemically etched in diluted HF acid to remove native oxide, rinsed in ultrapure water having dissolved oxygen concentration of 20ppb, and dried by the N2 -gas blow. The Si wafers were transported to sputtering chambers also in N2 ambient. Then Al, Cu, or Tl film deposition was carried out by low-energy bias sputtering technology with in-situ surface cleaning[3],[4]. The metal/silicon contacts were characterized by measuring the J-V characteristics of the Schottky contacts and Ohmic contacts. Results and Discussion There have been several reports on native oxide in metal semiconductor contacts[2][5][6]. Reduction on native oxide growth has been demonstrated under clean-N2 -gas seal processing by Miyawaki et al.[2]. They have pointed out that suppression of native oxide growth is essential to improve electrical characteristics of metal/silicon contacts such as Schottky contacts and Ohmic contacts. Current transport mechanisms in atomically abrupt metal/semiconductor contacts have been reported by Shenai and Dutton[71. They obtained excellent agreements of experimental results with their new current transport theory in Al/n-GaAs system. This paper reports electrical characteristics of metal/Si contacts fabricated under the new clean-N2 -gas seal processing carried out in a different manner. In order to characterize metal/Si contacts with high reliability and high accuracy, all Schottky diodes described in the following were fabricated by the clean-N 2 -gas seal processing(N-process). Figure 1 shows the J-V 322

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2.

barrier Schottky height of Al/n-Si(lO0) of function a as perimeter length.

characteristics of an Al/n-Si Schottky diode. The contact 2 4 area is 1.6xlO- cm and measurement temperature is 300K. The while the doted line shows measured J-V characteristics, derived from the thermionic ideal J-V characteristics emission theory is superimposed by a solid line. The Al/n-Si and an Schottky diode have nonideal J-V characteristics factor (n-value) of the Schottky diode is 1.05. ideality Figure 2 shows Schottky barrier height of Al/n-Si Schottky diodes calculated from the J-V characteristics as a function the of the perimeter length of the Schottky diodes, where 2 4 contact areas of the diodes are constant of 1.6x10- cm . From the figure, it is seen that the Schottky barrier height strongly depends on the perimeter length and decreases with increase in the perimeter length. Figures 1 and 2 point out that the leakage current flowing through the perimeter is dominant in reverse saturation currents of the Schottky diodes. In order to evaluate the real Schottky barrier the leakage current should be suppressed by a height, channel stopper or a guard ring. Figure 3 shows J-V characteristics of Al/n-Si and Al/pSi Schottky diodes at room temperature by a solid line and a dashed line, respectively. In the case of Al/n-Si contact, and the shows saturation density the reverse current obtained. is current-voltage characteristics rectifying is observed for the However, only Ohmic characteristics Al/p-Si contact (dashed line). This is because the barrier current height is very low and the reverse saturation

323

r 100

At/p-SI

S 10-

Al/p-Si T=77K

I0"' 10"1

'•10-'

.50

I0-

10 U

At/n -Si -0.3

Fig. 3.

-0.2

T=300K -0.1 0 0.1 BIAS VOLTAGE (V)

0.2

0.3

-

.

BIAS VOLTAGE (V)

J-V characteristics of Schottky diodes for Al/n-Si and Al/p-Si were measurements carried out at 300K.

Fig. 4. J-V characteristics of a Schottky diode on Al/p-Si at 77K.

density (J-) becomes very large. Since the barrier height for Al/n-SI is about 0.80eV, that for Al/p-SI would be 0.33eV assuming their sum equals to the bandgap of Si (1.13eV). Reduction in the barrier height by about 0.5eV results in the enhancement In the reverse saturation current density (J-) by nine orders of magnitude. As a result, the voltage drop at the series resistance of the substrate becomes dominant in the J-V characteristics in low voltage region. Figure 4 demonstrates the J-V characteristics of an Al/p-Si contact measured at 77K. It is clearly seen that the Al/p-SI contact has rectifier characteristics, demonstrating the existence of the Schottky barrier. However, carrier freeze-out occurs at this temperature, making accurate barrier height evaluation quite difficult. In order to characterize metal/silicon contacts in more reliable manner, a proper metal must be selected for experiment. Figure 5 shows Schottky barrier heights for Al/n-SI (30 Q-cm) contacts for four different contact areas formed by the clean-N 2 -gas seal process(N-process). Aluminum metallization is carried out by using RF-DC coupled mode bias sputtering technology[4]. The value D.- strongly depends on the contact area due to the leakage current flowing at the perimeter as is discussed in reference to Fig.2. On the other hand, in Cu/n-Si(30 Q.cm) contacts, the Schottky barrier height (D. is independent of the contact area over four orders of magnitude, as shown in Fig.6. Moreover, fluctuation of (bD, is less than 0.005eV. The Schottky barrier heights 4D,.- of the diodes fabricated in Nprocess are slightly smaller than those in C-process because of native oxide at the metal silicon interface.

324

00.84

r 0.82 j0.80

LU 0.78< 0.76 im'

10-5 Fig. 5.

AL/n-Si Schottky Diode I I I 10-1 10-2 18-3 10-4 CONTACT AREA (cm 2 )

Barrier heights of Al/n-Si Schottky diodes for four different contacts area formed by the clean-N.-gas seal process(N-process), where barrier heights are calculated from J-V characteristics at 300K. Cu/n-Si Schottky Diode 0 N-Process M C-Process

• 0.70 "ILU

M 0.69 rt" m0.68-

I

10-5

II

I

10-4

16--

10-2

CONTACT AREA (cm2 ) Fig. 6.

Barrier heights of Cu/n-Si Schottky diodes for four different contact areas and two different processings (N-process and C-process), where barrier heights are calculated from J-V characteristics at 300K.

Figures 7 (a) and (b) show the J-V characteristics of Cu/n-type and p-type Si Schottky diodes at 240K where the by solid lines. The theoretical curves are indicated Cu/n-Si contact. excellent agreement is obtained for the From Fig. 7 (a), the current density greater than 10-2A/cm2 tends to deviate from the in the forward direction of high curve due to the series resistance theoretical resistivity substrate (30 9.cm). Figure 7 (b) indicates the J-V characteristics of the Cu/p-Si Schottky diode where the 325

- 10

o

CU/p-Si T-240K

........

-, I -V zo-

-Theory -- Experiment (b)

0.3

BIAS VOLTAGE (V)

Fig.

7.

0.2

0.1 0 -0.1 BIAS VOLTAGE (V)

-0.2

-0.3

J-V characteristics of Schottky diodes for Cu/n-type S(a) and Cu/p-type Si(b) at 240K. Dots demonstrate measurement points and solid lines are calculated from the thermionic emission theory. T(K)

340 320

300

280

260

240

IV -E

S\O "to" X 3 V). Both samples had comparable initial characteristics, i.e. Vt and subthreshold swing. The enhancement of Id in high Vg region was attributed to the improved geff and reduced field dependence at high normal field [15]. The effects of RTO on the behaviors of geff are demonstrated in Fig.4, where PIeff is plotted as a function of Vg-Vt. RTO degraded the maximum peff by 5% to 15% for the two RTO conditions. However, RTO samples exhibited a dramatic improvement (30%) of geff under high field, probably due to a large reduction of interface states which are distributed above the conduction band after RTN/RTO compared to the control SiO2 [15,16]. The hot-carrier immunity of MOSFETs has been studied using AGm,max under F-N injection (J=-4 mA/cm 2 ). In Fig.5, AGm,max/Gm,maxo is plotted as a function of stress time in MOSFETs for several different gate dielectrics. In our previous study [12], it was found that RTN oxides showed degraded interface endurance properties against hot-carrier stress. For samples with the same RTN conditions, light RTO resulted in a larger AGm,max than the control samples. In contrast, heavy RTO resulted in a significant suppression of AGm,max, even better than the control oxide samples. The advantages of using RTP over furnace processing are also shown in Fig.5, where AGm,max/Gm,maxO of MOSFETs with gate dielectrics prepared by a 900*C/30 min or 850'C/30 min nitridation followed by a 900PC/15 min reoxidation (d). ADit was measured using charge pumping technique and ADit/Dito correlates well with AGm,max/Gm,maxo under the same stress condition, as shown in Fig.6, suggesting AGm,max/Gm,maxo is an indirect probe of the SiO2/Si interface endurance. A qualitative model [121 has been proposed to describe the structural modifications in the dielectric film leading to the observed changes in the electrical characteristics. During RTN of oxide, the nitriding specie preferentially reacts with the interface defects such as Si dangling bonds and/or the Si-O-Si strained bonds to form Si-N related structure. Formation of mismatched Si-N bonds distorts and weakens the nearby Si-O network. As a result, there are more breakable bonds available at the interface, which are responsible for the observed deterioration of the interface endurance to stress. Subsequent RTO not only restores the distorted Si-O bonds but also oxidizes the substrate and pushes the Si-N structure away by interracial reoxidation. This SixNyOz/Si interface has better endurance to

365

the hot carrier injection compared to the original SiO 2 /Si interface due to the presence of shorter Si-N bonds which relieve the compressive stress at the SiO2/Si interface. For future CMOS technology, p+-polysilicon gate was recommenend for surfacechannel p-MOSFETs. The p+-polysilicon is formed by B or BF 2 ion-implantation followed by thermal annealing. However, B tends to penetrate through thin gate SiO 2 into channel region during thermal drive-in, resulting in device instabilities. Furthermore, B penetration is aggravated when H-, OH- [21,22] or F- [23,24] are present. We have investigated the use of RTN/RTO oxides for p+-polysilicon gated p-MOSFETs [25]. B was introduced into S/D and polysilicon gate by BF 2 +-implantation at 50 keV with a dose of 5x1015 cm-2. RTA at 1000*C (for 20, 40, and 60 s) was used to activate and distribute the implanted B. Fig.7 illustrates the subthreshold swing S as a function of RTA drive-in time. Obviously, both control and RTN oxides samples show a significant increase of S values with prolonged RTA drive-in. An enhanced S degradation was observed for RTN oxide samples. However, this instability is drastically reduced in RTN/RTO samples. The n-MOSFETs these gate dielectrics show negligible variation of S values, indicating that the B penetration is primarily responsible for S degradation rather than RTN and RTO induced Dit. FLUORINATED GATE OXIDES Fluorinated gate oxide dielectrics have attracted considerable attention over the past few years [26-37]. The incorporation of small amounts of F (parts per million) into SiO2 was shown to improve the SiO2/Si interface hardness against hot-electron and radiation damages [30-37]. Several techniques have been proposed for the incorporation of F into MOS gate oxides. These include immersing Si wafers in an aqueous HF solution without DI water rinse prior to oxidation [30,31], ion implantation of F into polysilicon followed by a thermal drive-in [32-35], and high-energy F implantation into Si followed by thermal annealing and gate oxidation [36]. Furnace oxidation in 0 2 +NF 3 (diluted in N2 ) [37] was also demonstrated; however, thin gate dielectrics (.10 nm) may not easily be fabricated. We have applied RTP to the fabrication of thin (-10 nm), high quality fluorinated oxides in 0 2 +NF 3 (100 ppm diluted in N2 ) [26-28]. By using this method, F can be incorporated precisely and selectively into the oxides. The control SiO 2 was grown by RTO in dry 02 at 1050°C for 60 s. Two sets of samples were prepared using two different techniques for F incorporation. One set of samples received in-situ RTA in diluted NF3 with durations from 10 to 40 s at 9000 C prior to RTO (1050OC/60 s). For another set of samples, NF 3 was introduced into RTP chamber together with 02 and RTO was carried out at 1050*C for 60 s. The purge time for NF 3 varied from 10 to 60 s. An enhanced oxidation rate was observed due to the presence of F. Since F competes with 0 to form Si-F bonds and Si-dangling bonds via the cleavage of Si-Si bonds, the interracial reactivity was enhanced [38,39]. The sequence of NF 3 purging prior to or during RTO significantly affects the resulting F distributions. For samples which received RTA in NF 3 at 900*C for 20 s prior to oxidation, F piled up at the oxide surface. In contrast, F piled up at both the oxide surface and the Si/SiO2 interface in sample grown by RTO with an NF 3 purge during the first 10 s of oxidation. F distributions have dramatic impacts on the oxide electrical properties, as shown in Fig.8.

366

In Fig. 9, Dit distribution is plotted against E-Emg for oxides with several NF 3 purge times. It is clear that the hot-electron hardness of resulting dielectrics depends strongly on the amount of F incorporated. Excessive fluorination may result in nonbridging oxygen centers [32] , accompanying a local strain relaxation which suppresses the defect migration. For a 10 s NF3 purge at 10501C, the F induced strain relaxation effect exceeded that of induced nonbridging oxygen centers. The charge trapping properties are shown in Fig. 10, where AVfb is plotted as a function of NF 3 purge time during RTO. The fluorinated oxide with 10 s NF3 purge shows a far less negative AVfb than the control oxide. However, prolonged NF3 purges result in a larger AVfb, indicating an increased hole trap density. The increased hole trap density strongly suggests the existence of defects such as oxygen deficiency of stretched Si-Si bonds due to F incorporation. OXYNITRIDES GROWN BY RTP IN N20 Another method to incorporate nitrogen at the SiO 2/Si interface to improve the dielectric performance and reliability is to oxidizing Si substrates in N20. The nitrogen distribution in N20 oxides is measured by SIMS, AES, and XPS, and is found to be similar to that in RTN/RTO oxides [46]. AES oxygen and nitrogen depth profiles taken from a 60 A oxide sample grown in N20 at 1200 OC indicate the nitrogen concentration is low at the oxide surface and in the bulk. It increases gradually toward the substrate and a peak concentration of 5% was reached at the Si/Si02 interface. The peak concentration decreases with decreasing growth temperatures, from 5 % at 1200 °C, 4% at 1100 °C, to slightly less than 2% at 1000 'C. This trend is also confirmed by XPS depth profiling. Samples oxidized in N2 0 at 1050, 1100 and 1150 *C to a thickness of 62±2 A were studied. The peak nitrogen intensities were also found to decrease with decreasing temperatures. The nitrogen ls electron binding energy as revealed by XPS was 398±0.2 eV for for all three samples. This binding energy is consistent with the value measured on a 80 A Si 3 N4 sample deposited by LPCVD. This demonstrates that the nitrogen atoms in N 20 oxides are bound only to Si. The chemical composition of the nitrogen-rich layer at the Si/SiO 2 interface of nitrided oxides is similar to that in reoxidized/nitrided oxides. It will be shown later that the presence of small amounts of nitrogen in N20 oxides has a dramatic influence on their electrical properties. SIMS depth profiling has also been performed and nitrogen distribution similar to AES profiles were obtained with very low concentrations of hydrogen in the oxide bulk or at the Si0 2/Si interface, although a much higher hydrogen concentration was seen at the oxide surface, which resulted from adsorbed moisture and hydrogen on the surface after its being exposed to air. Fig. 11 shows the oxide thickness as a function of oxidation time at various temperatures. The oxidation rate of oxides grown in N 20 is significantly lower than in 02. We attribute the reduced oxidation rate to the formation of a nitrogen-rich layer at the SiOvjSi interface. This property allows the extreme control of growing gate oxides with thicknesses in the deep sub- 100 A region. Fig. 12 illustrates AVg of MOS capacitors under constant current stressing. Although both control oxides and N 20 oxides exhibit initial hole trapping, the subsequent electron trap generation is significantly suppressed in N20 oxides. Unlike the nitridation of oxides in NH3, oxidation of Si in N 20 does not involve any H-containing species, resulting in a very low electron trapping density. The reduced electron trap generation in N2 0 oxides was attributed to the nitrogen passivation of strained Si-O bonds which, upon breaking, would form electron traps during a high-field stressing [40]. AVfb after constant current stressing was also investigated and the results are summarized in Fig. 13. Apparently, hole trapping

367

near the Si/SiO2 interface was significantly suppressed in N20 oxides due to a decrease in the strain-bond density near the Si/SiO2 interface due to nitrogen incorporation [12]. The initial Ditm measured on fresh devices showed that both oxynitrides and control oxides exhibited Ditm in the range of 2.5 to 4xi0 10 eV-lcm- 2 . After stressing, however, a significantly lower ADinm was observed in oxynitride devices, especially under positive gate polarity. It is speculated that nitrogen incorporation at the Si/SiO2 interface reduces strained Si-O bond density by forming Si-N bonds, thus suppressing ADitm [12]. The resistance to B penetration was examined by measuring Vfb of BF 2 implanted polysilicon-gated devices as a function of annealing temperature. As shown in Fig. 10, the control oxide exhibited AVfb of - 5V when the annealing temperature was raised from 850 'C to 950 *C due to B penetration into the thin gate oxides. N2 0 oxides, on the other hand, exhibited much less AVfb ( 10000 C) and short time processing (typically a few tens of seconds), that are impossible to simultaneously achieve in furnace tubes.

391

EXPERIMENTAL Al-gated MOS capacitors were fabricated on 2", < 100 > oriented, 11cm, p-type Czochralsky grown silicon wafers. l6nm dry oxides were grown in a conventional diffusion furnace at 950'C in a Ar+ 10%0 2+2%HC1 atmosphere. On the other hand, an Addax R1000 by AET equipment was used to grow 16 nm RTO oxides at 1050°C, followed by a 30s RTA (rapid thermal annealing) in N2 at the same temperature. AI+ I %Si was deposited on top and bottom of the wafers, and after square gate definition by standard photolithographic procedures, all samples experienced a 20 min PMA at 435-C in hydrogenated ambient. Next, both destructive and non destructive electrical characterization tools were used in order to comparatively assess different aspects of electrical quality of these two kind of dielectric layers. NON DESTRUCTIVE ELECTRICAL CHARACTERIZATION In Fig. 1 thickness maps obtained for both oxides by C-V characterization of the fully processed capacitors are presented. RTO oxides are usually reported as less homogeneous due to problems of uniform heating [2]. In our case standard deviation for RTO samples (16A) was 5 times that of 0O-diluted oxides (3A).

160 40 ZO 40 30

Tý,M, ,,

RTO

J

•,•

MM

02-d diluted

Figure 1. Thickness wafer maps of RTO and 02-diluted oxides, RTO samples exhibiting a characteristic upward concavity and less homogeneity than furnace oxides.

No fixed positive charge in the vicinity of the Si-SiO2 interface could be inferred from the flatband voltages measured for both oxides. Interface states at midgap were also below detection of the two frequencies C-V method (!; 1.5e10 crmeV') in both cases.

392

In order to check if aggressive thermal cycling inherent to RTO technique, with temperature ramp rates as high as 300*C/s, damages the Si substrate, the pulsed Zerbst C-t method [3] was used and retention times were evaluated (figure 2). At this respect,

a damaged substrate is expected to offer more generation sites and thus exhibit worse storage time. However, RTO oxides showed three times higher carrier lifetime (- 140As) and an order lower (-I1cm'as') other parasitic relaxation currents. This fact makes RTO processes a good choice for DRAM applications.

Figure 2. Capacitance transients recorded for both types of samples, from the deep depletion to the equilibrium inversion value, being the area tested 2 2.3e-3em .

Inspection of I-V characteristics showed Fowler-Nordheim conduction over six decades of current prior to breakdown. Reasonable values of 3.0-3.1 eV for the Al-SiO2 barrier were obtained in both cases from the slopes of F-N plots, under the usual assumptions made in these calculations [4], indicating good structural characteristics for both oxides.

BREAKDOWN MEASUREMENTS Both time-zero and time-dependent stresses were performed on both type of oxides in order to characterize the electrical endurance of these films with such figures of merit as the breakdown field (E,) and the charge-to-breakdown (Q.).

393

Trne-Zero Breakdown experiences Using a HP4145B parameter analyzer, both types of samples were taken to destructive breakdown by performing staircase voltage ramp stresses at an approximately ramp rate of 4 V/s with the Si substrates biased in accumulation. It should be noted that all the fields appearing in this study are across the oxide and were calculated from the applied ones by taking into account the theoretical voltage distribution in MOS structures. 30-

30-

Am 3.

Area U (310)

I (RTO)

= 11.6 MV/em 25.

1.d. 1.7 7 MY/cm

MV/cm . -4 s.d. = 0.4 MV/cm

4) 10.

0

(b)

(a)

F'

15.

I

d

&

:•

•

5 7 6

A 4•

4"4

01

I

0-1

I Jl-,.. 21

41

112 34

6 67

Area I (O.-diluted)

km H (o,-dutd)

a

3.- 12.1 Wi/cm &.d. = 0.6 MV/cm

&.d.

I

11.0 MV/cm 3.2

iM/cm

M IW I1

1

1

|Z

h 1.. IJ

$2 131

1

a4?

p. 4? 4? S..

(d)

(c)

E (MV/cm)

E (MV/em)

Figure 3. Breakdown histograms of RTO (ab) and 0 2-diluted samples (c,d) for the two areas tested 2 2 (I:3.24e-4cm , ll:6.4e-5cm ).

In addition and regarding to the poor uniformity of RTO oxides the average thickness was not used in the calculation of breakdown fields. We used instead individual

394

thickness values for each sample considered and discarded those of less than 150A, the minimum thickness also observed for the O2 -diluted samples, in order to get a set of data suitable for comparison. The areas of the capacitors tested were 3.24e-4 cm2 and 6.4e-5 cm2. 50 capacitors of each type and area were used to construct the breakdown statistics. The breakdown histograms obtained for both types of oxides showing a good percentage of high field failures are presented in Fig. 3. From inspection of this figure it can be observed that although more 0O-diluted oxides broke down near the maximum breakdown field recorded (-13 MV/cm), RTO samples always showed tighter distributions. Average breakdown fields are summarized in Table I, RTO samples showing approximately 0.5 MV/cm higher dielectric strength. Analyzing failure data according to extreme value statistics [5], Weibull plots (Fig. 4) can be calculated from the cumulative failure functions (F). 2.0¸ 1.0 -.

0.0 -1.0

-2.0 -

R

-3.0 -4.0 -5.0

"I "I ",

F I""

E (MV/cm)

E (MV/cm)

Figure 4. Weibull plots of both areas RTO (a) and 0 2-di10-1° A were designated as shorted devices. If the capacitor is found to be shorted, the prober moves to the next capacitor and the test for the initial leakage current is repeated. If the capacitor passes the initial leakage test, it is then subjected to high-field stressing at a constant field Estres for a fixed stressing period tstress. After the stress field is applied, the leakage current is again 6 checked at the test field of 1 MV/cm. If the capacitor conducts a leakage current >2x10" A at the test field, it is designated "broken down." The following data are then recorded: the initial leakage current measured at 1 MV/cm prior to stressing, the leakage currents measured at the test field of 1 MV/cm just before and just after breakdown, and the electric field strength required to induce breakdown. A logic diagram of the testing routine is shown in Fig. 2. Dielectric breakdown conditions defined in this way are sufficient to guarantee that irreversible, catastrophic damage to the oxide has taken place [1, 4]. The statistical nature associated with the dielectric breakdown phenomenon requires a large number of capacitors to be broken down in order to provide reproducible data. Generally our experimental procedure was applied to 10x1O arrays of MOS capacitors on each wafer. However, to provide an adequate data base, a 30x30 array of MOS capacitors was chosen which covers most of the area of one wafer. The testing program was designed to reduce this larger 30x30 array into 9 10x10 nested arrays. In this way, 9 independent sets of 100 data points can be generated from each wafer. The prober was programmed to step across the wafer, contacting every third capacitor. Thus the 9 nested arrays are superimposed within the same overall area, and the effects of localized trends, such as varying oxide thickness, are minimized.

411

Fig. 2.

Flowchart of the stepped-field method for determining dielectric breakdown strength.

THE STATISTICAL NATURE OF FIELD-DEPENDENT DIELECTRIC BREAKDOWN Initial efforts were directed to discover the relationship between intrinsic and defectinduced breakdown by breaking down 900 MOS capacitors on one wafer. Extrinsic or defectinduced breakdown is defined as breakdown caused by a defect that formed, or contamination that was incorporated, during oxide growth. Intrinsic breakdown is defined as an inherent property of SiO 2 , which is related to the Si-O bond strength. Intrinsic breakdown occurs at considerable higher values of electric field than extrinsic or defect-induced breakdown. Evidently, the probability of observing defect-induced breakdown in a MOS capacitor is proportional to the area, assuming an oxide with a fixed defect density and with thickness

412

that is independent of position. Therefore capacitors with relatively small area must be utilized so that the defect-induced breakdown distribution does not overwhelm the intrinsic breakdown distribution [5]. It has been shown that the intrinsic breakdown field is proportional to the logarithm of the area of the conducting electrode [61. The stepped-field program was written so that the electric field begins at I MV/cm and steps toward breakdown in increments of 0.1 MV/cm. Baseline data was collected on an oxide that was 630 A thick, and was stressed for a period of 4 seconds at each successively increased field strength.

140

0

1l20 1C0

NUMBER OF DA STRESS TIME: 3 OXIDE THICKNE!

Ir

Defect Induced Distribution

043 23 n 0U

Fig. 3.

J 2

4

0 0 lU 1Z 14 BREAKDOWN FIELD (MV/cm)

10

10

&J

Histogram of breakdown fields illustrating a bimodal nature.

A histogram of the breakdown fields is shown in Fig. 3. From this histogram, it is clear that dielectric breakdown is a non-gaussian phenomenon that exhibits multimodal behavior. It has been shown that the Weibull distribution is appropriate for modelling the statistical nature of dielectric breakdown in oxides [5]. The data were fitted to the Weibull function: F(x)=l-exp[-exp(x)]

(1)

where F(x) is the cumulative distribution function, and x is a dimensionless parameter given by: x = (E-E___ ) S E.

413

(2)

The quantity Em is the modal breakdown field at which point x=0, and 1-e-1 or 63% of the MOS capacitors have broken down. The product SEo is the slope of the Weibull distributions shown in Figs. 4 and 5, and E0 is a characteristic electric field that is related to current injection into the oxide prior to breakdown [7]. The failure rate is given by:

fRx) =!LE = exp[x-exp(x)]

(3)

dx

LN (-LN(I-F)) -7 2D

-6

-5

-4

-3

i

i

i

ij

-2

-1

0

1

-2

3

SAMPLE SIZE 90oo STRESS TIME: 4 SEC

>

15

0

-

OXIDE THICKNESS: 630 Al Em =13.7 CORRELATION: 97.6%/

LL

z

F_. w5.15

10 CORRELATION: 97.4%/

0

0

00 o

.•.. I

< cla

0.5 1 2 5 10 20 50 90 99 CUMULATIVE PROBABILITY OF FAILURE (%) Fig. 4.

Weibull distributions of intrinsic and defect-induced dielectric breakdown illustrating bimodal behavior.

The maximum failure rate occurs when df/dx=0. This yields x=0 and corresponds to the modal value of the breakdown field Em. Two modes were separately fitted to similar Weibull distribution functions by truncating the ranked data, as illustrated in Fig. 4. The upper mode corresponds to the the intrinsic dielectric strength of the SiO 2, whereas the lower mode corresponds to dielectric breakdown associated with extrinsic defects. The correlation coefficient is above 97% for each of the distributions, indicating an excellent fit.

414

THE STATISTICAL NATURE OF TIME-DEPENDENT DIELECTRIC BREAKDOWN

Experimental efforts were next focused on the relationship between the intrinsic breakdown field and the stressing time. Defect-induced breakdowns were omitted from this investigation because of the limited data base and uncontrolled factors comprising their origin. The stepped-field method for breaking down dielectrics provides an accurate control of the stressing time. An analysis of the breakdown field as a function of stressing time was performed on the same wafer for periods of 1, 2,4, 10, 20, and 30 seconds. The data base contains 100 MOS capacitors for each of these stressing times.

co 0

0 a3

15

Fig. 5.

2) 33 40 ED 60 70 8D T 95 99 CUMULATIVE PROBABILITY OF FAILURE (%)

Weibull distributions of dielectric breakdown with varied stressing times.

After the data were collected, the defect-induced breakdowns were removed by truncating the ranked data, and the remaining points were compared with a Weibull distribution. By utilizing a simple independent variable transformation, a straight line could be fitted to the Weibull distribution and the correlation coefficient calculated. Data points were removed from the lower portion of the distribution until the correlation coefficient exceeded 97%. A plot of the breakdown fields fitted to a series of Weibull distribution functions is shown in Fig. 5.

415

The modal breakdown field Em for each Weibull distribution is defined at x=0 for each of the stressing times, and a plot of the characteristic breakdown field as a function of the stressing time is shown in Fig. 6. This plot indicates a logarithmic relationship between characteristic breakdown field and stressing time with a correlation coefficient of 99%.

E

z

2L -J

0 0

Fig. 6.

5

10 15 2 STRESSING TIME (SEC)

25

30

Modal breakdown field as a function of stressing time, fitted to a logarithmic function.

MATHEMATICAL MODEL RELATING PROBABILITY OF BREAKDOWN TO STRESSING FIELD AND STRESSING TIME Cumulative distributions of dielectric failures, plotted as a function of the logarithm of the stressing time, have been observed to undergo a parallel shift that is proportional to the electric stressing field [6, 8]. These observations have led Wolters and Verwey [9] to propose a model that incorporates the combined effect of electric field and stressing time: lni-In(1-F)]

-

ln(t)-In(tm) + E S SE.

(4)

where tm is the modal lifetime, or the stressing time at which the rate of dielectric breakdown events is maximum. With this model, we can predict dielectric breakdown behavior under conditions that may be impractical to measure experimentally, such as for very long stressing

416

times or relatively low stressing fields. vanishes, and we obtain: E

If we set E = Em, then the left hand side of Eq. 4

(5)

= Eo[ln(tm) - In(t)]

The data shown in Figs. 5 and 6 have been compared with this model, yielding empirical values: Eo= 1.42 MV/cm and tm = 1.91 x 104 sec. The fit is excellent for values of t 8MV/cm) for both top-oxidation conditions. (a)

100

SIO2ISl3N film Top-Ox. 900'C Dry Ox. 30mmn so .TIFM.= 01 ....................................

----.......--- ................

• 60 U-

Lj 40

20 2

4

6

8

10

12

14

BREAKDOWN FIELD (MV/cm) 4

SIO2/SI3N4film Top-Ox. 900'C Pyro. Ox. >-80 30mln - rf=•--i ......................

........... Z. -----

60 Lu

SNegative bias

Positive bias

[S

40 F

520

LU

0

2

4

6

8

10

12

14

BREAKDOWN FIELD (MV/cm)

Fig.4 Dielectric breakdown histograms of ONO stacked capacitor for positive and negative bias for (a) dry and (b) pyrogenic steam top-oxidation 425

Low field (14MV/cm) the MITF5o's for the dry/TCA and the pyrogenic top-oxidation are shorter than that for the dry oxidation.

A1

"0 ii_j

TIME TO BREAKDOWN (SEC) Fig.5 weibull-plot of constant voltage TDDB characteristics of ONO stacked capacitor for various top-oxidation conditions 426

111/v

Sii •

st e-t •

(v )

(b)

1/v (V ")

U-

uJ -I-

0)

1010 1411 1z

11

1U

S......... ^ 101 i 141I 13

W

STRESS VOLTAGE (V)

.. 11

.. 1U

. 9

STRESS VOLTAGE (V)

Fig.6 Time to 50% cumulative failures (MTTF5o) of ONO stacked films for various top-oxidation condition under the positive high fields (>14MV/cm) and medium high fields. The electric field acceleration factor P for the dry top-oxidation is 0.46 decade/V and does not depend on oxidation time. On the other hand, from Fig.6 (a) for the dry/TCA and pyrogenic top-oxidation, 13 becomes larger than that for the dry oxidation and are 0.65 and 0.58 decade/V, respectively. From Fig.6 (b), the 13 for the dry, pyrogenic and dry/TCA oxidation are 0.52, 0.93 and 1.14 decade/V, respectively. On the basis of this 0 value, MTTF5o's for the dry/lCA and pyrogenic top-oxidation at the operating voltage (2.5-4V) are estimated to be longer than that for the dry top-oxidation. Figure 7 shows MTTFso of the ONO stacked capacitor as a function of stress voltage for negative bias. The MTTF50 and 13are almost same for the all top-oxidation conditions P range from 0.5 to 0.6 decade/V. These results indicate that the MTTF5o for the positive bias and for the negative bias depends on the top-oxide and on the bottomoxide, respectively. From these results the dry/TCA top-oxidation is most suitable to get a high performance ONO stacked film with low leakage current, high reliability and large 13. The optimum top-oxide thickness is 2 to 3nm. The precise control and film quality control of bottom oxide is also important to form the highly reliable ONO stacked film. 427

Figure 8 shows the MTTF5o of the ONO stacked capacitors for pyrogenic steam topoxidation at 8501C and 900 0 C. The 3 value tends to be higher with increasing oxidation temperature. High temperature top-oxidation gives high 03and high reliability. However, the top-oxidation temperature becomes a trade-off between thermal budget and performance. Figure 9 shows the gate voltage variation (AVg) during current injection vs. injection current density of the ONO stacked film for various top-oxidation conditions. The behavior of AVg of the ONO stacked film is interpreted as follows. At the initial stage of current injection, holes are trapped at the SiO2/Si3N4 interface and increases the electric field across the film. At the next stage, electrons are trapped at the SiO2/Si3N4 interface. For the dry top-oxidation hole trapping is dominant. On the contrary, for the dry/TCA top-oxidation electron trapping is dominant. As shown in Fig.9, charge trapping behavior of the ONO stacked film varies depending on top-oxidation conditions. The 0 difference may be attributed to charge trapping difference mentioned above. The dielectric reliability of ONO stacked films strongly depend on the top-oxidation thickness and process method. Even if the topoxide thickness is equal, the dielectric reliability is dominated by the top-oxidation method. IN (V-') iN (V-') 8

0.9

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Fig.7 Time to 50% cumulative failures of ONO stacked films under the negative field

11

STRESS VOLTAGE (V)

Fig.8 Time to 50% cumulative failures of ONO stacked films for different top-oxidation temperature under the positive fields 428

The dry/TCA and pyrogenic top-oxidation have higher 0 than the dry top-oxidation. This is due to the thickness difference of top-oxide. Moreover, the dry/TCA topoxidation has higher 0 than the pyrogenic top-oxidation. This result may come from the difference of top-SiO2 Si 3 N 4 interface structure caused by adding the C1 during oxidation. 15 1

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INJECTED CURRENT DENSITY (A/crf ) Fig.9 Gate voltage variation vs. injection current density for various top-oxidation conditions SUMMARY Effects of top-oxidation on the reliability of ONO stacked film has been discussed. and the reliability of the ONO The leakage current, electric field acceleration factor J0 stacked film are strongly affected by the top-oxidation conditions. (1)Dry/TCA and pyrogenic top-oxidation are effective to suppress the leakage current of ONO stacked films. This result can be explained by the difference of top-oxide thickness. For dry/TCA and pyrogenic top-oxidation, thick top-oxide can be obtained. (2) From view point of dielectric reliablity,the optimum top-oxide thickness is 2 to 3 nm. Control of the bottom oxide thickness and quality are also important in getting highly reliable ONO stacked films. Top-oxide thickness and oxidation condition (temperature and ambient) should be determined by the combination of leakage current, effective thickness, dielectric reliablity and thermal budget. (3) Leakage current and 03were improved by the dry/TCA and pyrogenic top-oxidation. In particular, using the dry/TCA top-oxidation, P is improved drastically and low leakage current, low defects density and highly reliable ONO stacked films can be obtained. This superior dielectric characteristics may come from the difference of top-SiO 2 /Si 3 N4 interface structure. 429

The dry/TCA top-oxidation of nitride is very useful to get a highly reliable ONO stacked film and a promising technique for realizing a high performance DRAM, EEPROM and FPGA.

ACKNOWLEDGMENT The authors wish to thank to Mr.H.Iwasa and Mr.H.Koide for their continuous support and encouragement. The authors thank to Pilot Production Department for their careful processing and Support Technology Department for their support of measurements and AES analysis. The authors wish to thank to Mr.Royce Richter of Matsushita Semiconductor Corporation of America for his useful discussion and language assistance.

REFERENCES [1]T.Watanabe, N.Goto, N.Yasuhira, T.Yanase, T.Tanaka and S.Shinozaki,1987 Proc. Int. Reliability Phys. Symp.,p50,1987 [2]Y.Ohji, T.Kusaka, I.Yoshida, A.Hiraiwa, K.Yagi and K.Mukai, 1987 Proc. Int. Reliability Phys. Symp.,p55,1987 [3]J.Yugami, T.Mine, S.Iijima and A.Hiraiwa, Extended abstracts of the 20th conference on SSDM, p. 173 , 1988 [4]S.Chiang, R.Wang, J.Chen, K.Hayes, J.McCollum, E.Hamdy and C.Hu, 1990 Proc. Int. Reliability Phys. Symp., p.186, 1990 [5]A.E.Kuiper,M.F.C.Willemsen,M.L.Mulder,J.B.Oude Elferink, F.H.P.M. Habraken and W.F.Van der Weg, J. Vac. Sci. Technol., B7, p.455, 1989

430

THIN GATE OXIDE INTEGRITY IN FLUORINATED MOS STRUCTURES W.M. Greene and T.E. Kopley Circuit Technology Research and Development Hewlett Packard 3500 DeerCreek Road Palo Alto, CA 94303 and O.S. Nakagawa Center for Electronic Materials and Processing The Pennsylvania State University University Park, PA 16802 oxide MOS (and chlorinated) Fluorinated capacitors and MOSFETs were studied by Fowlerdielectric time-depedendent Nordheim injection, hot carrier stress. and channel breakdown, Fluorinated and chlorinated oxides have more hole With interface traps. traps but have less initial stress the amount of interface states generated is oxides. The fluorinated oxides similar for all Hot carrier have thicker effected oxide thickness. stress on MOSFETs showed devices with fluorinated oxides, but no chlorine, had longer lifetimes at high stress voltages than devices with chlorinated voltages to operating Extrapolation oxides. predicted that chlorinated oxide devices will have Devices with both fluorine the better reliability. and chlorine incorporation have worse lifetimes, than both at stress and operating conditions, devices with chlorine incorporation only. INTRODUCTION Producing reliable thin dielectrics for CMOS applications involves gate oxide engineering to minimize degradation Incorporation of during device operation and stress. various amounts of F via implantation into the polysilicon Oxide charge gate has attracted significant interest. time dependent state generation, interface trapping, (TDDB), and channel hot electron breakdown dielectric degradation mechanisms that are desired trapping are all to be minimized. EXPERIMENTAL Test Structures -

431

Capacitors

Injection experiments were perfor~ied on polysilicon gate MOS capacitors of area 1 x 10' cm' and isolation edge of 4 x 10 cm. The polysilicon edge overlaps the field oxide by 1 m. The capacitors were fabricated on a substrate consisting of a epitiial layer of p-type silicon, doping concentration 8 x 10 cm- and thickness approximately 6 m, grown on a p-type silicon substrate. These capacitors were fabricated along with n-channel MOSFETs of drawn gate length down to 0.5 m, and therefore got both a threshold voltage adjust implant and a punchthrough control implant. These imp~jntsyive the substrate an effective doping of -1.5 x 10 cm . The isolation used is SWAMI.[1] The gate oxide is a dry thermal oxide grown at 850 0 C with a post oxidation anneal in N2 for 30 minutes. The oxide thickness is approximately 10 nm to 12 nm thick. Chlorine is incorporated into the oxide by flowing a carrier gas through a TCA bubbler for the final 10 minutes of oxidation. Fluorine is added to the oxide by implantation at 25 keY into the polysilicon gate and subsequent diffusion during later thermal process steps. Table 1 shows the oxide process and the resultant concentration of F or Cl as determined by SIMS. Note that fluorinated oxides all have the 10 minute TCA step. The gate material is 250 nm of LPCVD deposited polysilicon doped with POCL3 at 9000 C. The POCL3 doping occurs after the F implant, and dopes the polysilicon degenerate. Metal Oxide Semiconductor Field Effect Transistors N-channel MOSFETs with LDD source and drain were fabricated along with MOS capacitors. The measured FETs were all L=0.6 m and W=10 m drawn. Effective channel lengths were not measured on these structures, but should be Leff -0.4 m. The MOSFETs were subjected to the same fluorine and chlorine process steps as the MOS capacitors. Additional fluorinated MOSFETs from a different lot with oxide thickness 15 nm and no TCA step during the oxide growth were also measured. Te LDD structure of the MOSFETs consisted of a 4 x 1013 cm dose of phosphorus at 30 keV and 00 implant angle. A 1600 TEOS oxide was used as a spacer Aateri.al. The source and drain were implanted with 3 x 10 cm arsenic and annealed at 9000 C for 30 minutes. The devices had titanium salicidation and 7000 PSG deposited over them. After contact etching, a metal consisting of 1500 TiW diffusion barrier and 5000 aluminum doped with 4% copper was deposited and etched. A TEOS oxide of 5000 was used for passivation. 432

Electron Injection Electron injection experiments were performed on the MOS capacitors. The applied voltage used for injection was a constant 12 V which resulted in electron injection from the Si substrate. The injection current was varied by illuminating the capacitors with white light of varying intensity. This effectively produced injection of constant current as well as voltage. Without light, no FowlerNordheim current flowed at 12 V, which we attribute to the lack of minority carriers in the p-type substrate due to their small generation rate. The light produces electronhole pairs which produces current characteristic of FN tunneling. In thee expqjiments, the injection current was held at 1.5 x 10- A/cmF and the temperature was held at 250 C.

Both the flatband voltage, VFB, and the interface trap density at midgap, N. , were monitored as a function of electron fluence. -ach data point is taken from a different capacitor which was stressed for the desired time and then measured by high frequency CV at

1MHz and GV at

200 kHz. This frequency was chosen because it was the frequency of highest conductance on G vs. freq. curves with the capacitors biased to flatband conditions. Separate capacitors were used because relaxation effects associated with taking the devices off stress to do the measurements skewed the results. The curves shown in this paper are representative of all data obtained. The consistency of the data is due to the uniformity of the oxide across the wafer, measured by CV to be ± 0.2 nm. Time Dependent Dielectric Breakdown (TDDB) TDDB was performed on large area (0.032 cm2 ) capacitors that minimize isolation and diffusion edge components. The tests were performed at 8 MV/cm in accumulation at 1500 C. Hot carrier lifetime The hot carrier lifetime of MOSFETs was measured using a unique test structure that allowed the simultaneous DC stress of up to 20 FETs all at different Vds and Vgs. This allows one to extrapolate to operating conditions from a single stress measurement. The test structure consists of 20 FETs all of the same length and width connected with a common source, gate, and substrate. The common source is the key to the structure. It consists of a single Al interconnect of width 5 m which runs from the source probe pad to the end of the structure. Along its length are 433

attached the source diffusion of each FET. It is designed with enough series resistance between FETs (-2 ) so that each FET sees a different source resistance. The actual series resistance is easily measured using the last FET as a current source and all the other FETs on the source line as voltage probes. The combination of all the stress currents that flow from each transistor then produce a different source voltage drop for each FET. This in turn, produces different stress voltages, Vds and Vgs, on each FET. This structure will produce DC stress voltages constant in time only when the stress currents remain constant in time. One must be careful to monitor stress currents, and FET designs that have an intrinsically large shift in I with hot carrier stress will not work well. with is structure. Since the stress currents produce the source voltage drop that determines the stress voltages, and the stress currents are dependent on the stress voltages, finding the true stress voltages requires a self-consistent calculation using the measured IV curves of the stressed FETs and the measured series resistance noted above. Lifetime is defined as a 10 % change in the linear region Ids (@ Vds=. 1 V and Vgs=4 V) for each stress voltage. The set of lifetime, Vds pairs is fit to a straight line, which is extrapolated to Vd- at operation conditions to give a lifetime at operation conditions. Other parameters monitored include linear region transconductance, gm (@ Vds=.l V and Vgs=4V) and threshold voltage, VT. VT for these LDD devices changes very little and is not a good monitor of hot carrier degradation. RESULTS General observations The fluorinated oxides show trends in oxide thickness, I sat and VT as shown in Figs. 1 and 2. The larger the fluorine concentration, the larger the effective thickness of the oxide. This trend is mimicked in the device Idsat and the TDDB t5 n results. This could be due to variations in dielectric constant; or it may be a structural effect that occurs during subsequent thermal processes involving the fluorine's effect on the mobility and reactivity of the oxidant species. There is also a trend in VFB and V associated with F concentration. The differences in tliese characteristic voltages are too large to be due to differences in oxide thicknesses (or dielectric constants) alone. The positive 434

shift in these parameters could be due to differences in positive oxide charge, N , between the various oxides. More likely it is due to enhanced boron diffusion through the polysilicon gate in the presence of fluorine[2]. CV measurements show that the substrate doping concentration indeed changes for oxides implanted with BF2 . This explains the largest shifts in the oxides implanted with BFV, but not the shifts in oxides with different F implants. Oxides implanted with F only do not have the boron to change the substrate doping, which has been verified by CV measurements. In these devices, F compensation of the P dopant in the polysilicon is possible. The compensation would change the work function difference between the p-type silicon substrate and the ntype polysilicon gate. This effect has been observed in devices with F implanted directly into the substrate of MOS capacitors[3]. The same effect could occur in polysilicon if the polysilicon is only marginally degenerately doped. Injection experiments Fig. 3 shows the flatband voltage shift vs. electron fluence for various F implantation doses. The initial shifts are negative with a reversal of sign near 0.2 C/cm . This implies some sort of hole generation and trapping for low fluence which is then compensated at longer injection times by electron trapping. This is consistent with previous work of Nishioka et al.[4] who studied FN injection of ultra-dry oxides. Their fluence at which sign reversal of voltage shift occurs is near 0.1 C/cm . This may be due to differences in the quantity of hole traps and/or the electron trapping cross-section between our oxides and theirs. Again looking at the low fluence regime, one sees that the higher the F dose, the greater the V B shift. (The same trend was seen in chlorinated oxides. - The effective positive oxide charges (assuming the charge resides at the Si-SiO2 interface) responsible for the observed VJB shifts are noted in the figure. The calculated values are approximately an order of magnitude greater than the measured changes in interface trap density at the same fluence which gives us confidence that the shifts are mostly due to oxide charges. It is possible that the fluorinated oxides have, besides the hole generation mechanism seen in non-fluorinated oxides, another hole generation and trapping mechanism that is influenced by the presence of fluorine and chlorine. Two separate and noninteracting mechanisms with different cross-sections and saturation values could be detected by observing the characteristic charging of these sites. Unfortunately, 435

these characteristics are masked by electron trapping and trap generation. At larger electron fluences, the VFB shifts reverse their earlier trend and eventually changed sign. The plots of VFB vs. fluence show that the shifts do not saturate. (Measurements up to the charge to breakdown, Qbd 1 C/cm, of the oxides were performed and showed no saturation.) This is because electron traps are being generated during the injection. Our oxide electric field is -11 MV/cm, which is far above the threshold field needed for electron trap creation.[5,6] Another oxide parameter of interest is the interface trap density, Nit. The measured interface trap density as a function o• fluence is qualitatively the same for Cl and F impregnated oxides. Figs. 4 and 5 plot midgap Nit vs. fluence for chlorinated and fluorinated oxides. The initial N. for both Cl and F oxides shows a consistent trend: thelVigher the halogen concentration the smaller the initial Ni. The Cl oxides, however, show negligible difference in N. generation with Cl concentration. F oxides show a larger initial difference in N-t, but the amount of Nit generated seems independent of F concentration. All curves show a notable kink near 0.1 C/cm fluence. These curves are qualitatively different from previously reported interface trap generation by FN tunneling.[4,5,7] A correlation of interest would be between the oxides' hole trapping qualities and interface state generation. For instance, if the mechanism of interface trap creation due to trapped hole annihilation occurs in these oxides , one would expect to see more interface trap generation with oxides of larger hole trapping (those with more F and Cl as shown above). Unfortunately, the characteristic energy of these types of interface states lie in the upper portion of the bandgap, and the midgap N.t does not monitor them. Experiments are continuing to proe N. in the upper levels of the bandgap. Compensation of anyltrapped holes occurs above 0.2 C/cm2 as shown in Fig. 3, 2but N.it generation eerto decreases markedly after only 0.1 C/cm . The shape of the N.t curves seem correct though, as one would intuitively tAink that hole annihilation would occur at the start of injection and give a larger Nit generation rate there.

Hot carrier stress Hot carrier lifetime in hours as a function of I/Vds at 436

stress are shown in Figs. 6 and 7. Fig. 6 data comes from MOSFETs processed as described above. Note that devices with the F implant show worse lifetimes than the control devices that have the TCA oxide only. Also the slope of the curves are different, as the TCA oxide has higher slope and will have an even higher lifetime at operation conditions. The lifetime extracted for 10% change in the parameter shows the same difference in slope between the two types oxides although the absolute lifetimes are much closer in value between the two types of oxide devices. Using this lifetime to compare devices still shows nonfluorinated oxides to have the best reliability. g

These results are in contrast to previously reported work on hot carrier stress in fluorinated oxides.[9,10] The work of Kasai et al. (10] showed that non-fluorinated oxides have a smaller slope in lifetime vs. i/Vds than fluorinated oxides. Since our device processing sequence is much different, and our gate oxide recipe includes TCA oxides, a direct comparison is difficult. Another parameter these authors note is the slope of the degradation vs. stress time curves. Our slopes for this curve are much smaller than reported by Kasai et al. and references therein, being -0.17-0.2 for TCA oxide devices and -0.19-0.22 for fluorinated oxides. Then slopes quoted above are for devices stressed up to 10 seconds, but it is well known that degradation does not follow a pure logarithm formal], but that the slope of the degradation vs. stress time decreases with increasing stress time. The initial slopes in our degradation experiments are actually higher than the ones quoted above for long stress time. The initial slopes are -0.33-0.35 for TCA oxide devices and -0.27-0.29 for fluorinated oxide devices for stress times up to 1000 seconds. Other workers have noted, though, that the beneficial effects of fluorine in gate oxides can be masked by the presence of chlorine.[ 12] We have therefore also measured MOSFETs that contain fluorine, but no chlorine. These devices were processed similarly to the devices described above, but had 150 gate oxides and concomitant VT implant differences. Most important, the fluorinated oxide devices had no chlorine in their oxides. Results on measurements on these devices are presented in Fig. 7. Note that the fluorinated oxide devices show a longer lifetime than the devices with the control oxides that have only chlorine. Again, as in Fig. 6, the nonfluorinated oxide devices show a larger slope in the 437

lifetime vs. i/Vds curve. Extrapolated for operating conditions (Vd - 4.0 V) the non-fluorinated oxides will have a longer lifetime. Again, using 10% change in gm as a definition of lifetime gives the same trend. These results are intriguing though, and further study is continuing. The results on the 150 devices may point to a gate oxide thickness dependence, not just an effect of chlorine on hot carrier hardness of fluorinated oxides. Measurements of lifetime vs. substrate current, which were not possible with our test structures used in these studies, will be done on packaged devices allowing better statistics and give substrate current also. CONCLUSIONS MOS capacitors and MOSFETs with various amounts and combinations of fluorine (and chlorine) incorporated into their gate oxides have been studied using Fowler-Nordheim (FN) injection, time-dependent dielectric breakdown (TDDB), and channel hot carrier stress. The FN injection showed chlorinated and fluorinated oxides to have more hole traps than oxides with neither chlorine nor fluorine. In addition, fluorinated oxides had less initial interface traps, but the same amount of interface trap generation as non-fluorinated oxides. The fluorinated oxides had thicker effective oxide thicknesses as measured by TDDB and electrical characteristics. Channel hot carrier stress on MOSFETs showed devices with fluorinated oxides, but no chlorine, had longer lifetimes at high stress voltages than devices with chlorinated oxides. Extrapolation to operating voltages predicts that the chlorinated oxide devices will have the better reliability. Devices with both fluorine and chlorine incorporation have worse lifetimes, both at stress and operating conditions, than devices with chlorine incorporation only. ACKNOWLEDGEMENTS The authors would like to thank the Silicon Process Laboratory at HP, Irene Leal for processing coverage, John Turner for SIMS analysis, Tom Dungan for help in hot carrier data analysis, and T.P. Ma for useful discussions. REFERENCES [1]. K.Y. Chiu, J.L.Moll, and J. Electron Devices ED-28, 1115 (1981).

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Manoliu,

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[2]. J.R.Phiester, L.C. Parrillo, and F.K. Electron Device Letts., EDL-11, 247 (1990). [3]. of

X.W. Wang, A. Balasinski, the

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and T.P. Ma, Interface

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IEEE

Baker,

Specialists

Conference. [4]. Y. Nishioka, Y. Ohji, I. Yoshida, Sugano, J. Apple. Phys. 67, 3903 (1990). [5].

D.J.

2342

(1989).

DiMaria and J.W.

Stasiak,

T. Nishida and S. [6]. IEEE IRPS, 310 (1991).

Thompson,

[7]. Phys.

S. Horiguchi, T. 58, 387 (1985).

Kobayashi,

[8].

S.K.

Lai,

J.

Apple. Phys.

K.

J.

Mukai,

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and K.

54,

2540

[9]. Y. Nishioka, K. Ohyu, Y. Ohji, Electron Device Lett. 10, 540 (1989). (10]. N. Kasai, P.J. Wright, and K.C. Electron Devices 37, 1426 (1990).

Saito,

T.P. Ma,

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(1983). and T.P.

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(11]. K.M. Cham, J. tui, P. van Voorde, and Proceedings of the 25 IEEE IRPS, 191 (1987). [12).

and T.

H.S.

Fu,

Table 1. Summary of F and Cl concentrations as measured by SIMS mCl]

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444

ELECTRICAL AND STRUCTURAL PROPERTIES OF ULTRATHIN Si02 GATE DIELECTRICS PREPARED UNDER VARIOUS CONDITIONS P. Lange, L. Schmidt, M. Pelka*, P. Hemicker, H. Bemt, and W. Windbracke Fraunhofer-Institut for Mikrostrukturtechnik, Dillenburger Str. 53, 1000 Berlin 33, FRG We have fabricated ultrathin SiO 2 layers between 5 and 10 nm. Conventional thermal and rapid thermal oxide forming processes were applied as well as a low temperature chemical vapor deposition (CVD) process. With these dielectrics, single layers have been produced for structural investigations by infrared (IR) absorbance spectroscopy. The IR-spectra of the thermal oxides and the postannealed CVD-oxide revealed nearly the same vibrational properties. MOS devices such as capacitors and field effect transistors (FETs) have been fabricated with these dielectrics. Breakdown measurements revealed a reduced high field breakdown voltage with a broadened distribution for CVD layers as compared to the results obtained for thermal oxides. This effect was reduced with decreasing thickness. From transfer characteristics and charge pumping measurements on FETs, no considerable difference in the number of fixed oxide charge and interface trapped charge density was observed for all oxides. The device properties appear to be more strongly effected by substrate dopant concentrations and the oxide thickness than by the intrinsic properties of the oxide.

INTRODUCTION The upcoming generations of 16 Mbit DRAMs and beyond require gate dielectrical layers with an effective oxide thickness of 10 nm and below . This increases the demands regarding the structural and electrical properties of dielectrical layers. Ion-diffusion blocking properties and hot carrier resistance become more significant as miniaturization increases. Aside from new approaches with oxide-nitride-oxide (ONO) thin multilayer systems [1,2], silicon oxynitride layers [3] or fluorinated gate dielectrics [4,5], silicon dioxide still plays a major role in the application as gate dielectrica [6,7,8]. In addition, in such highly integrated devices, there is a growing need for low-temperature, short-time processes in order to keep doping profiles present address:

Fraunhofer Arbeitsgruppe fOr Integrierte Schaltungen, Artilleriestrale 12, D-8520 Erlangen, FRG 445

shallow. This is why current efforts are focussed on rapid thermal processing [9,10] and low-temperature processing [11,12] of dielectrics. In a previous study we reported on the structural conformalities between postannealed CVD-oxide layers and thermally grown oxides in the 140 nm thickness range [13]. This result was concluded from infrared (IR) absorbance and wet chemical etching experiments. The question remains if this result is also obtainable for ultrathin layers and if there is a relationship to the electrical performance of such layers. Thus, we conducted a study in which Si0 2 was processed by low temperature deposition and subsequent annealing by rapid thermal oxidation and via conventional thermal oxidation. Thin layers in the 5 to10 nm range were then investigated by infrared absorbance measurements. For electrical characterization, breakdown measurements were carried out on MOS capacitors. In addition, n-channel MOSFETs have been fabricated and the transfer characteristics have been measured. The threshold voltages and transconductances were determined and compared to values received from device simulation. The interface trapped charge density was calculated from charge pumping measurements. EXPERIMENTAL WAFER PROCESSING Single films and MOS devices have been fabricated on 4 inch, n-Si (100) wafers, using three different oxidation processes, as described below: (a) Furnace oxidation (OX) in 02 at 9000C (ASM) (b) Rapid thermal oxidation (RTO) at 10500C in a rapid optical annealer (Eaton). This device is initially equipped with N2 , Ar gas lines for short-time, high-temperature activation or annealing, but through the introduction of 02 gas into the system, rapid thermal oxidation is possible. (c) Low temperature oxide (LTO) deposition in a low pressure-CVD reactor (ASM) at 4300C by reaction of SiH 4 and 02. The annealing of the LTO layers was carried out in N2 atmosphere at 9000C and 10000C for 30 min. MOS capacitors with 5 to 10 nm dielectrics and poly-silicon gate material doped from a POC13 source were prepared. N-channel MOSFETs were fabricated using a four mask lithography process, as reported in detail in Ref. [14]. Unlike the procedure described therein, in this study the lithography was performed optically using a g-line full wafer exposure mask aligner. For p-well implantation and the adjustment of the threshold voltage, a double boron implantation was carried out at 200 keV with 3 • 1013 ions cm- 2 and 60 keV with 1 . 1013 ions cm- 2 . After the standard LOCOS process and a subsequent modified RCA clean without an HF-etch step, the oxide was formed with 7 nm thickness. Immediately following, the poly-Si gate material was deposited. Subsequent to patterning the poly-level, sidewall spacer technology was applied. Source/Drain and poly-Si doping was carried out by means of arsenic implantation at 80 keV and 1 . 1016 ions cm- 2 , followed by a reoxidation step 446

which also ensures the diffusion and activation of implantation areas. Contact hole and AI-metallization levels were fabricated in a standard procedure. STRUCTURAL CHARACTERIZATION

The evaluation of structural properties was performed using a Fourier transform infrared (FTIR) spectrometer (Digilab QS-200) equipped with a 300 angle of incidence and unpolarized light. In this configuration, the excitation of the Berreman mode [15], which is a longitudinal optical (LO) resonance, is possible. It provides information regarding the quality of oxides in addition to information received from transverse optical (TO) modes, particularly from the principle absorption band at - 1070 cm- 1 . Any mention of TO and LO modes in the following refers only to these two modes. The absorption spectra of RTO layers with different thickness values are shown in Fig. 1. These spectra reveal peak positions of 1071 and 1064 cm"1 for the TO mode and full widths of half maximum (FWHM) values of 74 and 83 cm- 1 for 10 and 5.5 nm thickness, respectively. The well resolved LO mode at 1251 cm- 1 is also displayed. These features do not show any deviation from spectra obtained from conventional thermal oxides which are not shown here. As the thickness decreases, there is a slight shift to lower wave numbers in the TO mode, as has also been observed by others [16] for conventional thermal oxidation.

C

-_=

.0 0

Wavenumber

Wavenumber

(cm-)

(cm-')

Fig. 2: IR-absorbance spectra of a deposited (a) and annealed (b) LTO layer of 7 nm thickness

Fig. 1: IR-absorbance spectra of RTO layers with 10 and 5.5 nm thickness 447

For the LTO layer, the spectra are shown in Fig. 2 for an as-deposited film (a) and a postannealed (10000C) film (b). The as-deposited film spectrum 1 1 exhibits a TO mode at 1055 cm- with a FWHM of 86 cm- , and an LO mode 1 at -1225 cm- 1 . After annealing, the TO mode shifts to 1071 cm- and shows a 1 1 FWHM of 83 cm- . The position of the LO mode changes to 1251 cm- . This indicates a rearrangement process and thus a reduction of disorder in the oxide. Recently, more details on this subject have been reported in Ref. [13]. Overall, the features of the annealed LTO layer reveal a striking similarity with those observed on thermally grown oxides. However, the IR spectra appear as a good tool for the evaluation of structural qualities of thin films, but the question remains if a similar behavior is obtainable in the electrical performance of such films. ELECTRICAL CHARACTERIZATION Breakdown Measurements Breakdown measurements have been carded out on MOS capacitors 2 by applying a voltage ramp up to a current density of 2 • 10-4 A/cm . This current density has been accepted as the breakdown limit, as reversible measurements are possible up to this point.

0= ==

L,

U>

S=

E

UJ

Breakdown Field [MV/cm]

Fig. 3: Cumulative failures vs. breakdown field for various oxides of 10 nm thickness: a) LTO with 10000C annealing, b) OX, c) RTO and d) LTO with 9000C annealing

Fig. 4: Cumulative failures vs. breakdown field for various oxides of 5 nm thickness: a) LTO with 10000C annealing, b) OX and c) RTO 448

The cumulative breakdown statistics are displayed in Figs. 3 and 4 for 10 and 5 nm layers, respectively. The RTO and OX layers do not show any differences in their characteristics, and a high field breakdown voltage of 8-9 MV/cm for both thickness values. The LTO layer in Fig. 3 (annealed at 10000C) shows a reduced high field breakdown voltage with a broader distribution. However, for the g000 C annealed LTO layer, considerably poorer breakdown statistics have been obtained, as shown in Fig. 3. An annealing temperature above the viscous flow point is obviously required to reduce the number of low field breakdowns. If the thickness is decreased down to 5 nm, as shown in Fig. 4, the LTO layer also shows a higher field strength as compared to the 10 nm case. This effect is most likely due to the increased possibility of reduced structural defects with a decreased layer thickness. These measurements have been carried out on capacitors without measuring pads, fabricated in a separate process flow. On test capacitors which were made simultaneously with the NMOSFET-process flow, we have observed high breakdown fields of 20 MV/cm and 23.5 MV/cm for the 10 and 7 nm thermal oxide layers. The LTO layer of 7 nm thickness again revealed a slightly reduced breakdown field of 22 MV/cm as compared to the aforementioned thermal oxides. The observed differences in the two types of measurements may be explained by the very different process flow. For example, the applied reoxidation is suspended to reduce edge damage effects from plasma etching. Also, the surface dopant concentration for the two devices differs by a factor of 100. Transfer characteristics The transfer characteristics of NMOSFETs with 2 jam gate length and 10 jim width are shown in Fig. 5 for the three oxide layers with a thickness of 7 nm. In order to obtain information on the intrinsic properties of the oxides, we did not focus on gate lengths under 2 g.Lm, although gate lengths down to 0.8 g±m were also fabricated. This was done to exclude any effects which are related to small device geometries. From these data, the threshold voltages Vt and transconductances gm (VDS = 50 mV) have been estimated and are listed in Table I. Table I: Comparison of threshold voltages Vt and transconductances gm obtained from measured transfer characteristics and device simulation for various dielectrics.

OX RTO LTO

Measurement Vt / mV gimrus 470+/- 5 45+/-3 450 +/- 20 46 +/-3 630 +/- 25 41 +/-2 449

Simulation (7.5 nm) Vt / mV gmI/S 440 42 500 37 650 29

W< S: M0

V gate [V]

Fig. 5: Drain current vs. gate voltage for OX (dotted line), RTO (dashed line) and LTO (solid line)

Conc. [El7cm-3]

Fig. 6: Calculated threshold voltage Vt vs. surface dopant concentration for thickness values of the gate dielectric of 5 to 10 nm

The measured values for Vt and gm are in good agreement for the thermal oxide (OX and RTO) gate dielectrica. Deviations from these values have been measured in the case of LTO-dielectrics. The question remains if this effect can be explained by the appearance of various oxide charges, interface trap densities or dopant concentrations. By C-V measurements and subsequent profiling, we obtained the oxide thickness and different dopant concentration profiles. The actual dopant concentration near the surface was extracted from the flatband evaluation [17]. For the thermal oxides, the concentration was determined to be 2 - 1017 cm-3 and 1.7 • 1017 cm-3 for the RTO and OX layers, respectively. For the LTO layer, the concentration was 3 • 1017 cm-3 . This high value may be explained by the additional temperature step at 1 000°C which was applied for LTO densification. Device simulation by MINIMOS was carried out for various dopant concentrations and oxide thickness values. Source/Drain concentrations were simulated with ICECREM. An example is shown in Fig. 6 for the threshold voltages Vt vs. substrate surface concentrations, whereby the set of curves is drawn for various oxide thickness values. A comparison of Vt, extracted for d = 7.5 nm and the above-mentioned concentrations, shows good agreement 450

with the measured values. The values for the simulated transconductance gm are smaller for the LTO layer than for the thermal layers. This tends to agree satisfactorily with the measured values. The difference in the gm values is explained by the different dopant concentrations at the surface. From these results can be concluded that shifts in Vt and gm are not primarily caused by aditional process induced oxide or surface trapped charges. However, an important technological problem appears. As can be seen in Fig. 6, a variation of 1 nm in the thickness of the oxide results in a threshold voltage deviation of -100 mV. If for any reason the absolute value of the oxide thickness differs from a given value, the impact on the threshold value is very great. Also, poor thickness uniformity across the wafer causes a deterioration in the statistical deviations of the threshold voltages. In Tab. I, we also observed larger variances in Vt in the cases of RTO and LTO layers as compared to the variance for an OX layer. This corresponds to the results obtained in ellipsometric thickness measurements with a fixed refractive index. We received variances of a = 0.3 nm for LTO and RTO layers, and a = 0.02 nm for the OX layer. Charge pumping measurements The results of charge pumping measurements on NMOSFETs with 2 gIm gate lengths are displayed in Fig. 7. The bandwidth for the variation of the pumping currents is indicated by the dotted lines for OX layers, dashed lines for RTO layer and solid lines for LTO layer. A threshold voltage shift of -150 mV is also observable therein for the LTO layer. The currents are in the same

uJ 4' (1

0. 0

Fig. 7: Statistical variation in the charge pumping currents Ic vs. offset voltage for OX, RTO and LTO dielectrics, as shown by doffed, dashed •n,4

V offset [V]

a nirt

respectively 451

Iin.

order of magnitude and the number of interface state traps has been estimated as Dit = 3 to 4 x 1010 eV cm- 2 . Within the statistical variations of the pumping currents it can be concluded that there is only a negligible difference in the number of interface states for the three dielectrica. These devices have been stressed to observe any different degradation effects. For this purpose, a voltage of 4.5 V was applied between gate and substrate, and a voltage of 1.8 V between source and drain. Subsequent charge pumping measurements showed an increase by a factor of 2 in the pumping current. But once again, no significant difference for the three oxide layers was observed. CONCLUSION The interface trapped charge densities as well as the number of fixed oxide charges show no significant deviations for the three oxide dielectrics. Therefore, bulk and interface structural properties are very similar at a microscopic level, and all three oxides are suitable for device application. In a macroscopic view, however, LTO seems to be less appropriate because the defect density is enhanced compared to thermally grown oxides. This is shown by the results of the breakdown measurements. Also in this context, thickness uniformities are worse for RTO and LTO than for OX layers, which causes variations in threshold voltages in FETs. For future application, attention has to be focussed mainly on the availability of excellent thickness uniformities and low defect densities. This is of increasing importance for application in 8 inch wafer technology. The essential properties which determine the device characteristics are the dopant concentration profiles in the surface region and the thickness, as well as the uniformity of the dielectric layer. For submicron application, device design and process flow have a much greater effect on the device performance than the intrinsic properties of the oxides. ACKNOWLEDGEMENT The authors would like to express their gratitude to F. Naumann who performed additional C-V and breakdown measurements. REFERENCES [1] S.-W. Lee, T.-Y. Chan, and A.T. Wu IEEE Electron Device Letters, 11, 294 (1990) (2] T. Hori, and H. Iwasaki IEDM Tech. Dig. p. 459 (1989) [3] V.J. Kapoor, R. S. Bailey, and R.A. Turi J. Electrochem. Soc., 137, 3589 (1990) 452

[4] G. Q. Lo, W. Ting, D.- L. Kwong, J. Kuehne, and C. W. Magee IEEE Electron Device Letters, 11, 511(1990) [5] K. P. MacWilliams, L. F. Halle, and T. C. Zietlow IEEE Electron Device Letters, 11,3 (1990) [6] Y. Okazaki, T. Kobayashi, M. Miyake, T. Matsuda, K. Sakuma, Y. Kawai, M. Takahashi, and K. Kanisawa IEEE Electron Device Letters, 11, 134 (1990)

[7] S. P. Tay, A. Kalnitsky, G. Kelly, J. P. Ellul, P. DeLalio, and E. A. Irene J. Electrochem. Soc., 137, 3579 (1990) [8] C. C. - H. Hsu, D. S. Wen, M. R. Wordeman, Y. Taar, and T. H. Ning IEDM Tech. Dig., p. 75 (1989) [9] H. Fukuda, A. Uchiyama, T. Hayashi, T. Iwabuchi, and S. Ohno Jap. J. Apple. Phys., 29, L 137 (1990) [10] S. T. Ang and J. J. Wortman J. Electrochem. Soc., 133, 2361 (1986) [11] L.K.Wang, D. S. Wen, A. A. Bright, T. N. Nguyen, and W. Chang IEDM Tech. Dig., p. 463 (1989) [12] G. Lucovsky, S. S. Kim, and J. T. Fitch J. Vac. Sci. Technol., B8, 822 (1990) [13] P. Lange, U. Schnakenberg, S. Ullerich, and H.-J. Schliwinski J. Appl. Phys., 68, 3532 (1990) [14] D. Fredrich, H. Bemt, H. L. Huber, W. Windbracke and G. Zwicker SPIE Vol. 1089, 202 (1989) [15] D. W. Berreman Phys. Rev., 130, 2193 (1963) [16] J. T. Fitch, C. H. Bjorkman, G. Lucovsky, F. H. Pollak, and X. Yin Apple. Surf. Sci., 39, 103 (1989) [17] B. Ricco, P. Olivo, T. N. Nguyen, T.-S. Kuan, and G. Ferriani IEEE Trans. Electron. Dev., 35, 432 (1988)

453

CORRELATION OF METAL IMPURITY CONTENT OF ULSI CHEMICALS AND DEFECT - RELATED BREAKDOWN OF GATE OXIDES M. Meuris, M. Heyns, W. Kiiper, S. Verhaverbeke IMEC vzw, Kapeldreef 75, B-3001 Heverlee, Belgium and A. Philipossian Digital Equipment Corporation, 77 Reed road, Hudson, MA 01749, USA In this study the performance of ULSI chemicals from different suppliers was investigated in a RCA-type cleaning. After an ammonia/peroxide clean, the metal impurity density on the silicon surface is proportional to the metal impurity content in the peroxide. After a hydrochloric/peroxide clean no such correlation exist and an equal amount of trace metal densities on the silicon surface is found for all different vendors. Breakdown statistics do not completely correlate with the metal impurity content of the chemicals, but it is observed that haze shows a much better correlation with the breakdown statistics.

INTRODUCTION In MOS technology metal contamination seriously degrades the yield by causing defect - related oxide breakdown. In this study an investigation is made between trace metals in chemicals, the metal concentration on silicon wafers treated in these chemicals and the gate oxide properties. ULSI grade chemicals of different suppliers were tested in a RCA-type cleaning sequence. The chemicals used in this study were H2 0 2, HC1, and NH 1 OH. In a previous study M. Heyns et al. [1] correlated roughness parameters to breakdown statistics. This effect is also included in our study.

EXPERIMENTAL The wafers in these tests were silicon wafers n-type doped (resistivity between 1 and 10 Qcm) and 125mm in diameter, used for standard processing of devices. Initially, these wafers were labeled and put into conventional teflon carrier boxes. Just before the RCA-type clean the wafers underwent a 10 minute H 2SO,/H2O2 (5/1) clean at 90°C to remove organic contamination, followed by a DI-water rinse. Then a 20 second dip is performed in 2% aeqeous HF also followed by DI-water rinse. After the sulfuric acid/peroxide cleaning the wafers show a metal

454

contamination below 1011 at.cm- 2 for each metal under investigation. This drops to below 10'0 at.cm- 2 after the HF-dip. After this initial clean, the RCA-type cleaning was performed with ULSI chemicals from 4 different vendors. It has to be noted that because HCI from vendor C

was missing, we used HC1 from vendor B as a substitute. The RCA-type cleaning recipe was optimised in a seperate set of investigations [21. This cleaning was performed in quartz containers and consists of a 10 minute clean in a NH 1OH/H 2 0 2/H 2 O (0.25/1/5) mixture at 75 to 78°C, immediately followed by a'DI-water rinse, followed by a 10 minute clean in a HCII/H2 0 2 /H 2 0 (1/1/5) mixture at 75 to 78°C and again a DI-water rinse. In all cases the peroxide was mixed 2 to 3 minutes before reaching the final temperature of the cleaning solution, to prevent decomposition of the peroxide during the warming-up period. Wafers were dried by putting them vertically on the wet bench under the laminar flow for ten minutes. It was controlled that this drying procedure does not add any substantial contamination regarding particles or metals, compared with a conventional spin-dry procedure. However this drying procedure was more convenient and reproducible. The experiment consisted of 3 seperate runs. In each run the chemicals from the 4 different vendors were tested sequentially. The testing order of the different chemicals was changed in every run. After each NH 4OH/H 20 2 /H 2 0 clean 1 wafer was taken out of the carrier and the metal concentration on this silicon wafer was measured. After each RCA-type clean, 2 wafers were measured on metal contamination and 4 wafers were used to make capacitor structures. So after each run 16 wafers were loaded together in 1 furnace for making a 15 nm gate oxide. This oxide was grown in dry 02 ambient (no addition of chlorine) at a temperature of 900'C in a double walled furnace tube. Phosphorous doped polysilicon was put on top and capacitor structures etched in the polysilicon layer. Aluminum was sputtered and alloyed at the backside of the wafers. On these structures breakdown statistics were measured of capacitors with an area of 1.2 10-2 cm 2 and 3.85 10-1 cm 2 respectively.

Particle densities (for particles of 0.1 /im and 0.5 am in diameter) and haze (average total in ppm, standard definition of the equipment) were measured after the cleaning sequence with a Tencor Surfscan 4500. The particle densities of 0.5 gm in diameter varied for all tests from 0.2 to 1.5 particles/cm2 . This density is believed to have a negligible effect on our experiments. Trace metal content in chemicals The concentration of trace metals in the chemicals was measured with Total reflection X-Ray Fluorescence (TXRF) using a technique as described in ref. [3]. This method allows a relatively fast (approximately 20 minutes) determination of the metal impurity content of the chemical for a large number of metals. A 100 il droplet of each chemical was pipeted and dried on a clean Si substrate. When using

455

Table I: Metal impurity analysis in ppb of H20 2 for different vendors. - means below the detection limit of 0.1 ppb. Element

supplier A

supplier B

supplier C

supplier D

6.6

1.2

S K

1.7 7.4

-

-

-

Ca

4.0

1.4

5.0

22.0

Ti

2.4

-

0.5

-

Cr

3.2

0.6

3.0

0.6

Mn

0.2

-

0.6

0.1

Fe

0.2

3.0

7.3

2.7

Co

0.3

-

0.3

-

Ni Cu Zn

1.3 0.2 1.2

0.3 0.2 2.0

1.7 0.3 3.1

0.5

Ta

-

-

-

3.0

-

2.5

Table I1: Metal impurity analysis in ppb of NH40H for different vendors. - means below the detection limit of 0.3 ppb. Element Ca

supplier A 4.5

supplier B -

supplierC pir

supplierD upir

Fe

-

Cu Zn

1.2 0.5

0.3 0.2 0.5

0.4 0.5 0.4

0.4 0.2 0.4

a Si substrate only elements from Sulfur to Krypton and from Silver to Bismuth can be measured. The detection limit varies from 1 ppb (in weigth) for Sulfur to 0.1 ppb (in weight) for Zinc under the measurement conditions used. The DI water used in our test was contamination free down to the detection limit of 0.1 ppb. The reproducibility of these measurements was better then 10 %, except for Cl, which is a volatile species and can evaporate easily from the solution and for Zn, where the reproducibility was only a factor of 2. The detection limit for NH OH is about 0.3 ppb in our experimental conditions. One vendor delivered an analysis certificate of the supplied chemicals measured with Inductively Coupled Plasma Mass Spectrometry and Atomic Absorption Spectrometry. The difference with our analysis was less than 10 % for the elements which were listed above the detection limit of the vendor (typically 1 ppb). In Table 1, II and III the analysis of respectively H2 0 2 , NH.lOH and HC1 for the different vendors is shown. The metals, which are not present in detectable quantities in any of the 4 different chemicals, are not tabulated.

456

Table III- Metal impurity analysis in ppb of HC1 for different vendors. - means below the detection limit of 0.1 ppb. Element S K Ca Ti Cr Mn Fe Ni Cu Zn

supplier A 0.6 0.4 30.0 0.8 0.3 0.2 6.5 0.1 0.1 8.0

supplier B 2.3 0.2 22.5 1.6 2.0 0.3 19.9 1.6 0.5 2.2

supplier D 1.6 10.0 0.4 0.6 98.0 0.7 0.3 3.5

Metal concentration on silicon wafers The amount of metal concentration on the silicon surface was measured with Vapour Phase Decomposition (VPD)-TXRF [4]. In this technique a HF vapour is used to dissolve the native oxide. Afterwards a 50 1l droplet of a collection solution is used to collect the metals present on the Si surface. The droplet is dried and the TXRF signal measured. The detection limit with this technique is dependent on the wafer size and the collection efficiency. When using a water droplet the collection efficiency for Fe, Co, Ni and Zn is 50 to 60 %. For Cu the collection is only a few percent effective. An improvement of the collection efficiency is observed, when a mixture of 0.5%HF/1%H 2 0 2 /98.5%H 2 0 is used, as reported in [5]. We determined the collection efficiency on 5 different wafers, homogeneously contaminated at the level of 1011 to 1012 at.cm- 2 using a spin technique. In Table IV the collection efficiency of 5 important trace metals is tabulated. From Table IV it can be concluded that the reproducibility of this technique is quite good (around 10%) except for Cu, which is still difficult to collect. However, even in this case a detection limit of about 3 10' at.cm- 2 can be attained, with an accuracy of a factor 2 to 3. The background originating from the 50 pl droplet was 8 I0' for Ca, 2 10' for Fe and Zn and below the detection limit of 1 109 at.cm-2 for the other metals. Breakdown of gate oxides Wafers with polysilicon capacitor structures on 15 nm gate oxides were stressed up to 15 MV.cm-' in steps of 0.5 MV.cm- . From the breakdown statistical data, Weibull plots were generated to distinguish between defect-related and intrinsic breakdown events [6, 7]. The total number of intrinsic breakdowns (typically capacitors surviving a field of 12 MV.cm-1) were counted as "good" capacitors and

457

le-O le-0O le-O Sle-O 4J

C le-0 ý4 ý3 le-O

le-0 le-O le-0

0

3

6

9

12

15

18

Field [MV/cm]

Figure 1: I-V curve (solid line) of a good capacitor. Curve (a) represents the leakage current, curve (b) the tunneling current through the 15 mu gate oxide and curve (c) the spreading resistance of the silicon substrate.

458

Table IV: Collection efficiency of 5 different metals with VPD-TXRF. wafer Fe Co Ni Cu Zn 1 80% 80% 76% 9% 78% 2 77% 76% 72% 28% 74%

3

83%

84%

80%

15%

82%

4 5

84% 84%

83% 82%

80% 77%

111% 16%

81% 75%

this number, divided by the total number of measured capacitors, result in the yield percentage of gate-oxides after cleaning with chemicals from different vendors. Note that to obtain statistical significant results a capacitor area with a yield percentage around 50 % was chosen. In this way a clear difference between the vendors can be detected. Remark that in these measurements, the exact value of the intrinsic breakdown field is not well defined. Due to the high spreading resistance of the substrate the intrinsic breakdown field can be defined arbitrarily between 13 and 18 MV.cm-'. This is illustrated in Fig. 1. In this figure a typical I-V curve of a good capacitor is plotted for a 15 nm gate oxide. At low fields [curve (a)] the leakage current through the oxide is measured. At fields above 7 MV.cm-1 a tunneling current through the 15 nm oxide starts to flow [curve (b)]. This is observed by the large increase of the current. At fields typically larger than 12 MV.cm-' the spreading resistance of our substrate is dominating the I-V curve [curve (c)] and any further increase in the stressing voltage results in a large increase of the voltage drop over the substrate and only a minor increase of the oxide field. Therefore, in this investigations, capacitors surviving the field of 12 MV.cm-' are arbitrarily defined as "intrinsic".

RESULTS AND DISCUSSION As a starting point VPD-TXRF measurements were performed from the silicon wafers, coming out of the storage box, before any cleaning. It was observed that for the metals under investigation only Ca, Fe, Ni, Cu and Zn were present in detectable quantities. Sometimes (but irreproducible) Cr and Mn was measured up to levels of 5 10" at.cm-2. Because of the low concentration of these metals (both before and after cleaning) they will not be discussed further in this paper. The Cu concentration before cleaning was about 4 to 8 10' at.cm- . This Cu concentration did not significantly change during any step of the cleaning treatment. It has to be concluded that none of the cleaning solutions has a strong effect on Cu contamination and no removal of Cu with the conventional RCA cleaning procedure can be obtained. For the chemicals tested in this experiments also no addition was observed. In Table V the detected contamination on 5 different wafers immediately taken out of the storage box is summarized. The overall reproducibility of Ca, Ni

459

I

2UU 200

T >, 4.

S150

-H4

o0 4J

100

a0 4J

50 a• 50 U..

0

5

10 Ca conc.

15

20

25

[ppb]

Fe conc.

[ppb]

500

E5

Ann 4)

-H

U) r 4)

-a 0

V

0

0

4.)

0

z

0

Ni conc.

[ppb]

1

2

Zn conc.

3

[ppb]

Figure 2: Atom density on the silicon surface in 10i at.Cm-2 versus metal content in the H 2 0 2 in ppb for Ca, Fe, Ni and Zn (solid lines to guide the eye). (0) data points after NH 1 OH/H 2 0 2 mixture, (0) data points after HCL/H 2 0 2 mixture.

460

Table V: Atom concentration densities in 10 of the storage box

9

2

at.cm- for Si wafers immediately taken out

wafer

Ca

Fe

1 2 3

225 200 370

12 22 23

4 5

225 310

88 27

Ni

Zn 40 31 44

7 5

55 37

and Zn is typical for all VPD-TXRF measurements (about a factor of 2, especially once beneath the low 10'" at.cm-2 range). A large spread in the Fe contamination was observed (from 12 to 88 10' at.cm-2), due to differences in starting material. With VPD-TXRF also the metal concentration after NH,1OH/H 20 2 /H 2 0 (3 wafers for each vendor) and HC1/H 2 0 2 /H 2 0 (6 wafers for each vendor) cleaning was measured. Above 10" at.cm-2 the reproducibility of the experiment was about 20%. Under this limit the reproducibility degrades and is typically a factor of 2 to 3 at the 10i at.cm-2 level. In Fig. 2 the metal concentration of resp. Ca, Fe, Ni and Zn in the chemical oxide (in 10' at.cm-2 ) is plotted as a function of the metal content in the peroxide. For the ammonia/peroxide mixtures a remarkable correlation between metal content of the peroxide and metal contamination of the chemical oxide is observed. This correlation is almost linear and tends to go through the origin. Such a correlation was not observed for the metal content in NHOH or HCI. Ta was only detected on wafers cleaned with chemicals from vendor D (2 109 cm-2) and can be correlated with the 3 ppb Ta content of the peroxide D. Together with the observation of the cleanliness of the NHRjOH (see Table 11), the conclusion that metal deposition in NH4OH/H 20 2 mixtures is coming from the peroxide, is very plausible. Further it can be observed that the metal deposition problem is the largest for Fe. For 1 ppb metal content in the chemical, the deposition will be 300 10' for Fe, 100 10' for Zn, and 15 10' at.cm-2 for Ca and Ni. For Cr the deposition rate is even lower, because 2 peroxides contain up to 3 ppb of Cr, but no Cr is detected conclusively above the detection limit of 1 10' atc M-2. Therefore Fe and Zn have to be considered as the most critical contaminants in H2 0 2 . All these observations are consistent with the model suggested in [8] of precipitation of metalhydroxides on the chemical oxide. After the HC1/H 20 2/H 2 0 cleaning the result is completely different. In this case no correlation between metal content of the chemical bath and the concentration on the silicon wafer is found. Remembering table III, even a 100 ppb Fe content of the HCl of vendor D, results in only 50 109 at.cm-2 Fe concentration on the Si wafer. The Fe content in HC1/H 20 2 /11 2 0 baths in our experiment is varying from 1 ppb

461

W0 V

Haze

[ppm]

0.09 pjm < No.

of part.

< 0.2 pm

densities cm -2 Figure 3: Yield of capacitor structures as a function of haze and particle (0.1 Am in diameter) for different chemical suppliers. (0) 1.2 10-2 cm 2 capacitor area, (0) 3.85 10-2 cm 2 capacitor area. to 15 ppb and only a change of 20 to 50 10' Fe at.cm- 2 on the silicon surface is observed. The breakdown statistics were measured for the 3 different runs on 4 wafers each. 100 So, in total 12 wafers were measured for each chemical supplier. On each wafer 2 capacitors were measured. On 6 wafers the capacitor area was 1.2 10-2 cm large. 2 On the other 6 wafers it was 3.85 10-2 cm , resulting in breakdown statistics on 600 capacitors for each area. The yield (as defined in the previous section) varied dramatically over the different chemical suppliers (from 74 ± 8 % to 29 ± 24 % for the small capacitors and from 45 ± 4 % to 7 ± 9% for the larger capacitors). Such a large difference (about a factor of 3) cannot be easily correlated with the metal concentration on the silicon wafers. Indeed no large difference on the metal concentration after our cleaning procedure could be observed. In Fig. 3 the density of particles (0.1-0.2 Am in diameter) and the haze is plotted as function of the yield for the different chemical suppliers. The haze and small particles are a parameter for roughness on the wafer J9] and taking into account the relationship between the surface roughness and the breakdown statistics of gate oxides [1) it becomes clear that this observation cannot be a hazardous event. Further it is remarkable that with chemicals of supplier A, not only the best breakdown statistics are obtained, but also the smallest standard deviation for the yield is observed.

CONCLUSIONS In this experiment metal content of chemicals and metal contamination on the 462

silicon surfaces was correlated. A linear correlation between metal content of chemical oxides after ammonia/peroxide mixture cleanings and the metal content of the peroxide could be determined. After hydrochloric/peroxide cleaning no correlation between metal content of the chemical and metal concentration on the silicon surface could be detected. The metal contamination on silicon surfaces after a complete RCA-clean did not vary significantly, even when using chemicals from different suppliers and with different metal content. However, the breakdown statistics changes drastically from vendor to vendor. Measurements on haze and "light-scattering defects" of the silicon surfaces after cleaning indicates that this difference in gate oxide integrity between the chemicals from different vendors is correlated with the difference in surface roughening behaviour of these chemicals.

ACKNOWLEDGMENTS Digital Equipment Corporation is greatly acknowledged for financial support.

REFERENCES [1] M. Heyns, C. Hasenack, R. De Keersmaecker and R. Falster, published in Proceedings 1st Int. Symp. Cleaning Technol. Semicond. Dev. Manuf., ECS meeting, Florida, Oct 1989. [2] M. Meuris, M. Heyns, S. Verhaverbeke, L. Stockman, A. Philipossian, presented at the Mat. Res. Symp., Anaheim, CA, 29 April - 3 May 1991. (3] A. Prange, K. Kramer, and U. Reus, submitted to Spectroch. Acta. [41 P. Eichinger, Proceedings Syrmp. Anal. Techn. Semic. Mat. and Process charact., ECS meeting, Essderc 89 Berlin, Vol 90-11, p. 227. [5] T. Shimono, and M. Tsuji, Proceed. 1st Workshop ULSI Ultra clean Technol., Tokyo 1989, p. 49. [61 D.R. Wolters, in Insulating Films On Semiconductors, Eds. M. Schulz and G. Pensl, (Springer Berlin 1981), p. 180. [7] R. Falster, J. Appl. Phys. 66, 3355 (1989). [8] W. Kiiper, and K. Maex, Proceed. Techn. Conf. on defect control and rel. yield manag., Semicon/Europa 1991, Ziirich, Switserland 1991, p. 1 3 5 . [9] S. Verhaverbeke, M. Meuris, and M. Heyns, Internal Report (IMEC 1990).

463

PROCESS-INDUCED IONIZING RADIATION EFFECTS IN MOS DEVICES T.P.Ma Yale University Center for Microelectronic Materials & Structures, and Department of Electrical Engineering New Haven, CT 06520-2157

Ionizing radiation damage in MOS devices caused by various ULSI wafer processing steps will be reviewed, along with the current understanding of the possible mechanisms. The capabilities and limitations of several annealing techniques will also be discussed.

INTRODUCTION To meet the ever more stringent requirements of dimensional control, increasing use of processing techniques involving highly energetic photons or particles is expected in ULSI wafer fabrication. Some of these processes could cause radiation damage to the devices and circuits being fabricated, resulting in degraded performance and reliability, and/or reduced yield. Depending on the processing sequence and the details of the processing parameters, some of these steps present a more serious problem than the others in terms of the resultant radiation damage. The most commonly observed ionizing radiation effects in a MOS device include: (a) a buildup of positive charge in the oxide; (b) an increase in the interface traps; and (3) an increase in the neutral electron/hole traps in the oxide. These electronic defects are known to cause changes in the MOS transistor parameters, such as a shift in the threshold voltage, a reduction in the transconductance, an increase in the subthreshold swing, and an increase in the source-drain leakage current; they could also cause significant degradation of the device stability and its operating lifetime. Mechanisms of Ionizing Radiation Effects Qualitatively, the ionizing radiation effects arise from the energy transfer of the incident radiation to the Si-O network, causing bond breakage, bond deformation, creation of defects, and generation of electrons and holes. The resulting deformed or broken bonds and the trapping of charge manifest themselves in the change of the electronic properties described above. A detailed description of the ionizing radiation effects can be found in a recently published book [1]. A very brief summary is given below. Figure 1 illustrates the possible 464

processes by which the electronic defects (represented by the three shaded boxes) are generated. Due to the incident radiation, electrons and holes are created in the oxide, or injected into the oxide by internal photoemission from the contacts. These carriers will either recombine or transport through the oxide, and some of them will be trapped, causing oxide charge. Since holes in the oxide have a much lower mobility and a much higher trapping probability than electrons, the radiation-induced oxide charge usually caries a positive sign. Along with the electron-hole generation process, chemical bonds in the oxide may be broken. Some of these bonds may reform when the electrons and holes recombine, while others may remain broken and give rise to bonding defects. These defects may then act as oxide traps or interface traps. Some of the defects generated in the strained region near the SiO 2 /Si interface may migrate toward the interface under the influence of the strain gradient and form interface traps. Chemical impurities, such as H or OH groups, may be released from their original bonding sites and become mobile in the oxide. These impurities may also migrate to the Si0 2 /Si interface, where they undergo reactions to form interface traps.

Fig.1. Mechanisms of ionizing radiation effects in MOS structures. The various processes

and their inter-relationships are shown in the block diagram, and discussed in the text.

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PROCESS-INDUCED IONIZING RADIATION EFFECTS This section briefly describes the ionizing radiation effects caused by a number of wafer processing steps. E-beam and X-ray Lithography E-beam or X-ray lithography offers the advantage of higher resolution than the conventional optical lithography. In both the focused electron beam and the X-ray exposure systems, the silicon wafer will have received an accumulated radiation dose of well over 1 Mrad(Si) after each exposure. The generation of oxide charge, interface traps, and oxide traps in MOS devices by energetic electrons and X-rays is well recognized [2]. While most of the radiation-induced positive charge could be annealed out at 400 0C in forming gas, it has beeh found that the neutral traps are not completely removed even after annealing at 500 OC [3-5]. From the photo I-V measurements, it was suggested that the radiation-induced neutral traps are uniformally distributed spatially [5], as long as the incident radiation is absorbed uniformly through the oxide. The significance of the radiation-induced neutral traps and their impacts on the VLSI technology have been summarized [41, and the design constraints for the operating parameters in order to limit the hot electron injection in VLSI devices have been discussed [6]. Effects of repeated E-beam radiation-thermal annealing cycles on the long-term stability of MOS devices have also been reported [7]. In principle, it is possible to place a blocking layer over the gate oxide during X-ray or E-beam lithography to prevent the penetration of the incident radiation into the oxide. In practice, however, there are difficulties in its implementation [8] due to the secondary X-rays generated by the bombardment of the electron beam, which penetrate deeper than the electrons. The radiation effects resulting from the secondary X-rays generated by the bombarding electron beam were also reported by others [9]. RIE and Other Plasma Processes Plasma processes, including plasma etching, resist removal, RIE (reactive ion etching), and plasma-enhanced chemical vapor deposition (PECVD), are gaining increasing importance in processing high density circuits. Since a typical processing plasma contains various energetic species, it is expected that some radiation effects will occur. In a gaseous discharge, free electrons gain energy from an imposed electric field and lose this energy through collisions with gas molecules and solid objects, leading to the formation of a variety of new active species, including metastables, atoms, free radicals, ions, and photons.

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Since the discharge initiates from the free electrons in the system, and because of their small mass, the electrons have the highest peak kinetic energy among all the energetic species. For a RF plasma the highest electron energy (in eV) would correspond to the applied RF voltage. The high energy end of the photons, i.e., the soft X-rays and VUV, are generated by the electrons impinging upon a solid object (e.g. the electrode plates, the chamber walls, or the sample). UV photons are also emitted by de-excitation of gas molecules in the plasma. Therefore, the peak photon energy should track that of the electron energy. The ions, being charged particles, can gain kinetic energy in the presence of an electric field. Because of their much higher masses compared to electrons, the kinetic energies of the ions are generally much lower than the peak energy of the electrons. The molecules and other neutral species do not gain kinetic energy from the electric field, and therefore have the lowest energies in comparison. In discussing the ionizing radiation effects in Si0 2 , we must examine the penetration depths of the various energetic species in the plasma. Because of their high energies and negligible momenta, the X-ray photons have the highest penetration depth among all the energetic species in the plasma. Based on the absorption coefficients in Al, Si, and Si0 2 as a function of photon energy [101, a penetration depth of approximately 0.5 pm in these materials is expected for a photon energy of 500 eV. The electrons, in contrast, have a much shallower penetration [11], because of the momentum conservation requirement. The ions and neutrals, having even larger masses and smaller kinetic energy, would have the least penetration depths. In a typical processing plasma, the penetration depths for various ions are less than 10 nm. If the oxide is covered with a gate electrode, then only X-rays in a typical processing plasma will be able to penetrate into the oxide and create radiation damage. It is, therefore, not surprising that the resulting radiation effects should be similar to those observed after X-ray lithography discussed in the previous subsection: generation of oxide charge, interface traps, and neutral oxide traps. All of these electronic defects have been observed experimentally [12,13]. The only significant difference is in the spatial distribution of the neutral traps along the thickness direction of the oxide, due to the more limited penetration depth of the soft x-rays generated in the plasma environment [13]. Again, the radiation induced neutral traps are more difficult to anneal out than the oxide charge and the interface traps [12]. While the ions in the processing plasma may not cause significant ionizing radiation effects to the gate oxide due to their limited penetration depths, they may nonetheless cause a potentially more troublesome reliability problem; i.e., the release of mobile ionic charge in Si0 2 . This phenomenon could occur when the surface of the Si0 2 is directly exposed to the processing plasma [14]. A model involving ion-insulator interactions has been proposed to explain the results [15]. The mobile ionic species, once they are introduced into the Si0 2 , are extremely difficult to remove, and therefore precaution must be taken to prevent their occurence. It should be noted that, according to the model proposed in [15], the necessary conditions for this effect to happen are: (1) the oxide sur467

face must be directly exposed to the plasma; (2) the oxide surface must initially contain immobile impurities, such as Na bonded to the SiO 2 network; and (3) the incoming ions must possess sufficient ionization potential so that electronic transitions from the SiO 2 surface can take place to neutralize the ions. Therefore, it should be possible to avoid this effect by designing a plasma process that does not satisfy one or more of the above listed conditions. Although their kinetic energies are relatively low, the ions in a processing plasma are capable of causing displacement damage to the exposed wafer surface [13,16,17]. However, since this paper is intended to focus on issues related to ionizing radiation effects, we will not address other forms of plasma damage here. Another reliability problem associated with plasma processes is the dielectric breakdown phenomenon [18,191, which has been attributed to the excessive charging of the gate. Again, since this is not due to ionizing radiation effects, it will not be covered beyond this paragraph. Sputtering and E-Gun Deposition The radiation damage due to sputter etching and deposition has been studied in detail [14]. In many ways, the sputtering environment is similar to that of RIE and some other plasma processes, with the exception that an inert gas (typically Ar) is used for sputtering. Therefore, its ionizing radiation effects are expected to be qualitatively similar to those from other plasma processes discussed in the previous section. In E-Gun deposition, an electron beam of energy range 10-50 keV is used to bombard the source material, causing heating and evaporation of the material in a vacuum environment. The E-beam bombardment creates X-rays and reflected and secondary electrons, which can cause radiation damage to the substrate on which the materials is being deposited. Again, due to the larger penetration depth of the X-rays compared to the electrons, it is usually the former that produce most of the radiation effects. Generations of oxide charge, interface traps, and oxide traps have all been observed experimentally 120,21]. ANNEALING OF PROCESS-INDUCED RADIATION EFFECTS It is generally accepted [1] that the radiation-induced oxide charge, interface traps, and oxide traps are associated with the microscopic structural and bonding defects in Si02 or at the Si0 2 /Si interface. To remove the radiation damage requires some mechanisms by which bond reformation or some other chemical reactions can take place to make the defect sites electronically inactive. In general, some sort of energy is a necessary input to promote such annealing mechanisms.

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Thermal Annealing The most widely used technique is thermal annealing, in which thermal energy serves to initiate and sustain the various annealing mechanisms. The fact that the radiation-induced positive charge and interface traps in Al-gate MOS devices could be largely annealed out at 400 °C or below was recognized long ago [22]. Since then, a good amount of more detailed work has been done to investigate the annealing process, and data on the time dependence and temperature dependence of the annealing behavior have appeared in numerous publications [23-25]. The important role of hydrogen in the defect annealing process in Si0 2 is now widely recognized [26-31]. During thermal annealing, hydrogen species could undergo chemical reactions to form chemical bonds with certain defects, and make them electrically inactive. Therefore, one would expect the annealing mechanism to be very different with or without the participation of hydrogen. Since the hydrogen species could come from within the Si0 2 itself, or from inward diffusion from external sources, it is very difficult to separate out the two annealing mechanisms. The problem is compounded if the annealing ambient and the hydrogen content in the oxide are not strictly controlled. This is part of the reason why the results reported vary widely from one laboratory to another. Compared to the radiation-induced oxide charge and interface traps, the radiationinduced neutral traps in the oxide are much more difficult to anneal out [3,4,12], and remain a major concern. In recent years, many applications of rapid thermal processes have been demonstrated, but little work has been reported on the annealing of process-induced radiation damage. Because of its relatively low thermal budget, rapid thermal annealing may prove to be a powerful technique for this application. Hydrogen-Assisted Thermal Annealing The role of hydrogen in oxidation, annealing, and defect generation in thermal SiO 2 has been extensively discussed [26,27-29]. It is generally believed that hydrogen enhances the annealing efficiency by passivating the electronically active bonding defects. In the case that hydrogen must be introduced in the annealing ambient, forming gas (a few percent H2 mixed in an inert gas) is most widely used, although pure hydrogen is also occasionally used. To be effective, the active hydrogen species must be diffused into Si0 2 to react with the defects. Therefore, the thermal energy in the hydrogen-assisted annealing process serves three purposes: (1) it promotes the generation of active hydrogen species, most likely atomic hydrogen ; (2) it enhances the diffusion of same; and (3) it drives the defect reaction processes. Depending on the structure of the device being annealed and the annealing parameters, one or the other of the three may be the limiting factor in the overall annealing process. If the oxide is covered with aluminum, as in the Al-gate technology, it has been found that the annealing is equally effective whether or not the ambient contains hydrogen 469

[27,31]. It is believed that, during thermal annealing, the aluminum reacts with minute amounts of H2 0 on the oxide surface to release the active hydrogen species, which then diffuse into SiO 2 and annihilate the bonding defects [27]. In contrast, for polysilicon gate devices, the annealing process goes faster in forming gas than in an inert atmosphere [31], but is generally less effective than that for Al-gate devices even with forming gas [4,33], due to the fact that it is difficult for hydrogen to diffuse through the polysilicon gate at the annealing temperatures (• 500 oC). There has been evidence that, if the polysilicon gate is covered with a layer of aluminum, the defect annihilation rate is enhanced [4], presumably due to the production of active hydrogen species at the AI-polysilicon interface in a way similar to that at the Al-SiO2 interface. These hydrogen species then diffuse into SiO 2 through grain boundaries of the polysilicon. That the lack of active hydrogen species could hinder the defect annealing process in SiO 2 is also evidenced in experiments involving MNOS (Metal/Nitride/Oxide/Si) structures. It was found that, compared to the MOS structure, it is much more difficult to anneal out the oxide charge and interface traps in a MNOS structure [29], presumably due to the blocking of hydrogen by the nitride layer. Strong evidence suggesting that atomic hydrogen may be the active species involved in the defect annealing process has been presented [30]. Detailed studies of the annealing kinetics in Al-gate MOS capacitors [33] also brought out the importance of atomic hydrogen in the annealing of interface traps. Recognizing the importance of hydrogen in the thermal annealing process, attempts have been made to more effectively introduce the active hydrogen species into the oxide. One way is the use of atomic hydrogen generated in a plasma environment [30]. Another method is to perform the thermal annealing in a high pressure environment containing hydrogen [34]. Using a specially designed high-pressure system, the authors found that radiation-induced charged and neutral centers in Si-gate devices could be effectively removed by annealing in 50 atm of forming gas at 400 °C for 30 minutes for radiation doses as high as 5 x 10' rads (Si0 2 ). In contrast, temperatures as high as 600 °C are required to achieve similar results if the thermal annealing was done in 1 atm pressure. In addition to the thermal annealing and its variations, a very different annealing technique, called RF plasr6a annealing, has demonstrated its effectiveness [10,35-38], which is briefly described below. RF Plasma Annealing The RF annealing apparatus and the experimental details can be found in a number of publications [10,35,38]. Basically, the annealing apparatus is similar to a parallel-plate RIE system but with some important differences. The most significant difference is that in the annealing system the sample experiences no dc self-biasing effect. This can be accomplished by having two equal area parallel-plate electrodes with a wide spacing (Ž 8 in) between them, and the sample is positioned in the center between the two electrodes. 470

Other important considerations are that the pressure must be sufficiently low (< 10/pm), the wafer surface must be perpendicular to the RF field, and both sides of the wafer must be exposed to the plasma. Departure from these conditions has been found to result in unsatisfactory results. Complete removal of radiation-induced oxide charge, interface traps, and neutral traps has been demonstrated using this technique at a modest RF power (0.2 to 0.6 W/cm 2 ) [35,38]. It has been shown that, although the wafer temperature does rise during RF plasma annealing, thermal annealing is not the dominating mechanism [10,35,36]. Three essential components for the annealing have been identified [10,35,38], which are (1) plasma interactions with Si0 2 ; (2) RF field; and (3) induced wafer temperature. The primary role of the plasma is to serve as an excitation source for the generation of the electron-hole pairs in the oxide. The RF field controls the motion of these radiationinduced free carriers, and modifies the defect-reaction coordinates such that a more favorable annealing reaction can be achieved. Furthermore, the RF field, along with the plasma-wafer interactions, induces a moderate heating of the wafer, which also contributes to the annealing. The plasma-induced excess carriers could participate in two possible annealing processes. The first process involves the neutralization of the positive oxide charge centers through electron capture. The second process involves the more complicated recombinationenhanced defect reactions (REDR) mechanism [39,40], which could lead to the annihilation of the bonding defects in SiO 2 . Experimentally, it has been demonstrated that the occurence of the REDR mechanism helps to significantly reduce the temperature required for certain defect annealing processes [10]. As pointed out previously, the energetic gas plasma, if it acts alone, is a source of radiation damage. It is only through the proper cooperative interactions of all three essential components that effective annealing is possible. An experimental simulation has been performed in which an X-ray beam was used in place of the RF plasma, and the three essential components for an effective anneal- (1) the X-ray radiation; (2) the RF field; and (3) the induced wafer temperature- could be independently controlled. From a systematic investigation of their individual and combined effects, it was concluded that the cooperative interactions of all three components were necessary to achieve good annealing results. A factor of three reduction in the activation energy accociated with this annealing process was found when compared with the pure thermal annealing process. This is consistent with the recombination-enhanced annealing mechanism. A detailed description of this experiment and its results can be found elsewhere [10,38]. ACKNOWLEDGEMENT The author would like to acknowledge the contributions of his former graduate student, Dr. M.R. Chin, and the support of SRC.

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REFERENCES [1] T.P.Ma and Paul V. Dressendorfer, co-editors, Ionizing Radiation Effects in MOS Devices & Circuits, (John Wiley & Sons), (1989). [2] A. Reisman, et.a] J. Electrochem. Soc. 131, 1404 (1984). [3] J.M. Aitken, D.R. Young, and K. Pan, J. Appl. Phys. 49, 3386 (1978). [4] J.M. Aitken, IEEE J. Solid State Cir. SC-14(2), 294 (1979). [5] W. Schmitz and D.R. Young, J. Appl. Phys. 54(11), 6443 (1983). [6] T.H. Ning, et.al., IEEE Trans. Electron Dev. ED-26(4), 346 (1979). [7] M. Shimaya, et.al, J. Electrochem. Soc. 130, 945 (1983). [8] M. Shimaya, et.al, J. Electrochem. Soc. 131, 1391 (1984). [9] K. Nakamae, et.al, J. Apple. Phys. 52(3), 1306 (1981). [10] T-P. Ma and M.R. Chin, J. Apple. Phys. 51(10), 5458 (1980). [11] T.E. Everhart and P.H. Hoff, J. Appl. Phys. 42, 5837 (1971). [12] D.J. DiMaria, et.al, J. Appl. Phys. 50(6), 4015 (1979). [13] L.M. Ephrath and D.J. DiMaria, Sol. State Technol. p. 182, April 1981. [14] D.V. McCaugham and R.A. Kushner, Proc. of the IEEE 62, 1236 (1974). [15] D.V. McCaugham, et.al, Phys. Rev. Lett. 30, 614 (1973). [16] S.W. Pang, Sol. State Technol. 27, 249 (1984). [17] T.P. Chow, et.al, J. Electrochem. Soc. 131, 156 (1984). [18] T. Watanabe and Y. Yoshida, Sol. St. Technol. p. 263, April (1984). [19] K.H Ryden, et.al, J. Electrochem. Soc., 134, 3113 (1987). [20] T.H. Ning, J. Apple. Phys. 49(7), 4077 (1978). [21] M. Hamasaki, Sol. St. Electron. 26, 299 (1983). [22] K.H. Zaininger and A.G. Holmes-Siedle, RCA Rev. 28, 208 (1967). [23] V. Danchenko, et.al, J. Apple. Phys. 39, 2417 (1968). [24] P.S. Winokur and H.E. Boesch, Jr., IEEE Trans. Nucl. Sci. NS-28, 4088 (1981). [25] D.B. Brown, et.a], IEEE Trans. Nucl. Sci. NS-30, 4059 (1983). [26] A.G. Revesz, J. Electrochem. Soc. 126, 122 (1979). [27] P. Balk, Paper # 111, Electrochem. Soc. Meeting, Oct. 10-14, (1965). [28] P.L. Castro and B.E. Deal, J. Electrochem. Soc. 118, 280 (1971). [29] B.E. Deal, et.al, J. Electrochem. Soc. 116, 997 (1969). [30] N.M. Johnson, et.al, J. Vac. Sci. Technol. 19(3), 390 (1981). [31] M.L. Reed, et.al, Apph Phys. Lett., 47, 400 (1985). [32] T.W. Hickmott, J. Appl. Phys. 48, 723 (1977). [33] M.L. Reed, Ph.D dissertation, Stanford University, (1987). [34] A. Reisman and C.J. Merz, J. Electrochem. Soc. 130, 1384 (1983). [35] T.P. Ma and W.H. Ma, IEEE J. Solid State Circuits SC-13, 445 (1978). [36] T.P. Ma and M.R. Chin, Appl. Phys. Lett. 36, 81 (1980). [37] M.R. Chin and T.P. Ma, Appl. Phys. Lett. 40, 490 (1982). [38] M.R. Chin, Ph.D Dissertation, Yale University, December (1981). [39] L.C. Kimerling, Sol. St. Electron. 21, 1391 (1978). [40] J.D. Weeks, et.al, Phys. Rev. B12(8), 3286 (1975).

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CHARGE SHARING "ANTENNA" EFFECTS FOR GATE OXIDE DAMAGE DURING PLASMA PROCESSING S. Fang, A. M. McCarthy*, and J. P. McVittie Center for Integrated Systems, Stanford University, Stanford, CA 94305 *Lawrence Livermore National Laboratory, L-271, Livermore, CA 94550

In this work, small area capacitors with various sized polysilicon gate antennas and different field-to-gate oxide thickness ratios have been used. The objective is to characterize the role of device structure on thin oxide yield, and the nonuniform charge build-up phenomena during plasma processing. For a given field-to-gate oxide thickness ratio (tf/tg), the yield initially decreases with increasing field-to-gate area ratio (A f/Ag) and then saturates. The yield at saturation increases linearly with decreasing thickness ratio. The low yield region is concentrated at the wafer center and expands with increasing Af/Ag, or tf/tg. A structure dependent field enhancement factor is proposed using a model based on charge sharing between the gate and field capacitors. With surface charge density measurements, this simple model can successfully explain the above results. In addition, the nonuniform charge build-up phenomena is seen in the surface charge density profile and the wafer maps of damaged capacitors. Key words and phrases: charge sharing, antenna, plasma damage, oxide charging, plasma etching, plasma stripping, oxide breakdown

INTRODUCTION Plasma processes use glow discharges to lower process temperature and to obtain directional ion bombardment By their nature, discharges always result in some surface charging and are usually accompanied with some rf current flowing through the wafer. Normally the surface charging is not significant, however under some conditions which are not well understood, charging can be excessive and thin oxide degradation results [1] [2] [3]. Part of the difficulty in understanding this problem is that the observed damage depends on plasma conditions, the device structure, and oxide quality. In this paper, 473

Figure 1: The antenna structure of MOS capacitors: tf ranges from 0.75 pm to 1.7 Pm, t, ranges from 6 nm to 12 nm.

we focus on the role of the device structure [415][6]. In particular, antenna capacitor structures [7] have been used to study thin oxide integrity. These structures consist of small area thin oxide capacitors connected to large area field oxide (or antennas) capacitors as shown in Figure 1. The surface charge that deposits on the polysilicon antennas is measured with an electrically erasable-programmable read-only memory (EEPROM) device [8]. We will show that the experimental breakdown results and the surface charge density are consistent with a capacitor charge sharing model.

EXPERIMENT Antenna Capacitors Polysilicon gate MOS capacitors on 5 ohms-cm n-type Si wafers were used in this study. Figure 1 shows the antenna test structure. The thin gate oxide was grown in dry 0 2 at 85 0 0C. For part of the wafer lot the gate oxide was held at 12 am, and the field oxide thickness (tf) ranged from 0.75 pm to 1.7 pm. For the other wafers the field oxide was held at 1.7 um , and the thin gate oxide thickness (tg) ranged from 6 am to 12 am. Polysilicon was deposited at 650°C and doped with POCI 3 at 900 0C. Polysilicon etching and photoresist stripping were used to achieve the antenna structure. The antenna-to-gate area ratio was varied from 16 to 1000 and 180 to 11,000 for gate oxide areas of 20 x 20 and 6 x 6 pm2 , respectively. To etch the polysilicon, a 474

13.56 MHz parallel plate configuration was used in the plasma mode (wafer on grounded electrode) with a SF6/C2FsCl mixture. The photoresist was subsequently removed in a single wafer 02 plasma stripper in which rf power was capacitively coupled to the plasma at the top of a quartz chamber while the wafer was supported on quartz pins at the bottom. Alternatively, control wafers were fabricated using only a wet chemical process for polysilicon etching and photoresist stripping. To characterize gate oxide damage from plasma processing, ramp voltage breakdown measurements were used. The breakdown voltage was defined as the point at the current exceeding 1I#A. Typically, 200 capacitors were tested for each antenna structure (Af/A•j,tJ/tg) used. Surface Charge Measurements The threshold voltage shift of a special EEPROM device [9] was measured to determine the surface charge density profile on the wafer during the 02 plasma. The EEPROM transistor used in these experiments was an N channel device with two polysilicon gates: a control gate and a floating gate which incorporates a thin dielectric over the source region. The control gate was connected to a large area metal electrode which enhanced the transistor sensitivity to surface charge. To study the plasma-induced wafer charging, initialized EEPROM wafers were exposed to the 02 plasma for three minutes. The resulting threshold voltage shift was measured after the plasma exposure.

RESULTS Role of Device Structure In this section, gate oxide integrity is compared by ramp voltage measurements for antenna capacitors with different structure parameters such as tf, t,, Af , and A,. Note that for plasma processing, both the polysilicon etch and resist strip steps were found to cause damage with the damage mainly arising from stripping. For the results from antenna structures to be reported here, the combined effect of etch and strip was examined. Control wafers prepared without any plasma processing show purely intrinsic breakdown. We use the term intrinsic breakdown for any capacitors with a breakdown field of about 13 MV/cm. The breakdown field below 12 MV/cm is referred to as a defective breakdown. For plasma etching and stripping combined, Fig. 2 shows a typical cumulative failure percentage versus breakdown voltage plot. Both defective and intrinsic breakdown were observed for a gate oxide area 20 x 20 pm 2 with tfl/tg = 142 and Af/A, = 16, 160, 1000. If we define the yield as the percentage of capacitors with intrinsic breakdown from across the entire wafer area , we can plot the yield versus area ratio as shown in Fig. 3 for a gate oxide area of 6 x 6 pm 2 and tf/t9 = 142, 236. For a given 475

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Figure 4: The yield at saturation versus thickness ratio. thickness ratio, the yield initially decreases with increasing area ratios and then saturates at a value which decreases with increasing thickness ratio. This yield dependence on tf/tg is further shown in Fig. 4 where the saturated yield plotted against tf/tg for a gate oxide area 6 x 6 ym 2 increases linearly with decreasing thickness ratio. Tsunokuni et al. [10] also observed the dependence of plasma induced gate oxide damage on area ratio and gate oxide thickness with antenna capacitors. However, our experiments reveal that the damage to thin oxides depends not only on the oxide area ratio and the gate oxide thickness, but also on the field oxide thickness. The dependence of yield on Af/Ag in Fig. 3 differentiates the charge damage from the radiation damage because the polysilicon electrodes of different sizes (Af) serve as antennas to collect charge. The role of field oxide thickness may be explained as follows: The equivalent circuit of the antenna structure has a field and a gate capacitor in parallel. As the field oxide thickness increases, the field capacitance decreases so that more charge flows to the thin oxide gate resulting in higher fields and more damage.

Phenomena of Nonuniform Charge Build-up To study the nonuniform charging in an 02 plasma, wafer maps were made of antenna capacitors wafers using ramp voltage testing and of EEPROM wafers using surface charge density measurements.

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Figure 5: A negative charge build-up profile calculated from Vth shift measured using EEPROM for RF-powered stripper with RF power = 500 Watts. For ramp voltage testing, we define the local yield as the percentage of capacitors with intrinsic breakdown, in a ring bounded by r-0.5 cm and r+0.5 cm. For these plasma processing steps, we see that the low local yield region with a yield < 50 % is concentrated at the wafer center and expands with increasing A1 /A, or tf/bt resembling a bill's eye. Furthermore, there exists a critical radius, r,, which defines the edge of this low local yield region. This same bull's-eye pattern is further observed in surface charge measurements using the EEPROM charge monitors as shown in Fig. 5 where negative surface charge density is shown across a wafer diameter. We calculate the amount of charge density deposited on the surface metal pad as Q,=

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EEPROM results and SPICE simulation, Namura [12] relates the charging nonuniformity 478

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479

to the spatial nonuniformity of plasma potential. However, the origin of nonuniform charging is still not clear. Further research is needed to achieve a better understanding.

MODEL OF CHARGE SHARING The bull's-eye pattern is seen in both the wafer maps of antenna capacitor breakdown measurements and surface charge densities measured by EEPROM. The similarity between the yield and surface charge uniformity measurements implies a correlation. In this section, the yield of antenna capacitors is related to the surface charge density by a simple charge sharing model. The equivalent circuit of an antenna capacitor test structure has a field and a gate capacitor in parallel. For a first order approximation, the current through the gate oxide is negligible. Assuming that the plasma locally deposits a surface charge density, Q., on the wafer, a model based on charge sharing between the gate and field capacitors is as follows. After redistribution of the deposited surface charge, the voltage across the field and the gate capacitor is given by: V = q XX tf = xtg

(2)

where e is the permittivity of Si0 2, and qf, aa are the final charge densities on the field and gate capacitor, respectively. The conservation of charge gives (Af+Ag) xQ.=Af xqf+A, xqg

(3)

Eq. (2) and Eq. (3) yields the electric field in the thin gate oxide during plasma processing as (4) EG = qq X l1+ I' + Aj/Ag ef 1 + tgA//t (Ag where the last term is called the field enhancement factor FA. For a given tf/tg, FA initially increases with increasing Af/A. and then saturates at t11t2. Note that the general feature of this model is also valid if the plasma acts as a current source. We apply this model to explain the phenomena observed. With the Q, described in Fig. 5, the EG below the intrinsic breakdown field (- 1.3 x 107 V/cm) can be calculated for different values of FA as shown in Fig. 6. The critical radius, r, , defines the edge of the low local yield region. The antenna structure parameters (Af/Ag, tfltg) corresponding to the FA of Fig. 6 are shown in Table 1. With this model the r, increases and the yield decreases as FA increases because of an increase in Af/Ag for a given tf/tg= 142, or an increase in tf/tg for Af/Ag _Ž2000. This effect is observed in Fig. 3 and Fig. 4.

480

CONCLUSIONS In summary, we have investigated the role of "antenna" structure parameters on oxide breakdown integrity yield during plasma processing. Our results reveal that the oxide yield depends on both the area ratio (Af/Ag) and the thickness ratio (tf/tg). For a given tfIt, the yield initially decreases with increasing Af/A, and then saturates. The yield at saturation increases linearly with decreasing thickness ratio. In addition, wafer maps are made of defective breakdown capacitors. The location of damaged capacitors is concentrated at the wafer center and expands with increasing Af /A9 , and tj/t . A model based on charge sharing between the gate and field capacitors gives the electric field EG in the thin gate oxide during plasma processing. The EG is proportional to a structure dependent field enhancement factor FA and the surface charge density Q,. With surface charge density measurements, the distribution of oxide field EG during plasma treatment for different FA values can be calculated based on Eq. (4) and this simple model is consistent with our results.

ACKNOWLEDGEMENTS The authors would like to thank Prof. K.C. Saraswat and Dr. L-W. Wu for their helpful discussions, and WJ. Snoeys, S.S. Agarwal for providing the antenna mask. This research was supported by SRC and DARPA.

References [1] T. Watanabe and Y. Yoshida, Solid State Technol., 27, 263(1984). [2] K. H. Ryden, H. Norstrom, C. Nender, and S. Berg, J. Electrochem. Soc., 134, 3113(1987). [3] G. K. Herb et al., Proc. 13th Annual Tegal Seminar, 31(1987). [4] I.-W. Wu, et al., J. Electrochem. Soc., 136, 1638(1989). [5] W. M. Green, J. B. Kruger, and G. KooL, to be published in J. Vac. Sci. Technol. B, April 1991. [6] C. T. Gabriel, to be published in J. Vac. Sci. Technol. B, April 1991. [7] F. Shone, et. al., VLSI Sym. Tech. Dig. , 73(1989). [8] Y. Yoshida, R. Shirota, and K. Azumi, Proc. 9th Symp. Dry Process, 110(1985).

481

[9] A. McCarthy and W. Lukaszek, Proc. IEEE Conf. on microelectronics test structures, Edinburgh, Scotland, March 1989. [10] K. Tsunokuni, et. al., Ext. Abstr. 19th Conf. Sol. Stat. Dev. and Mat'ls, Tokyo, 195(1987). [11] Y. Kawamoto, Proc. 7th Symp. Dry Process, 132(1985). [12] T. Namura and H. Uchida, Proc. l1th Symp. Dry Process, 74(1989).

482

EFFECTS OF PROCESS-INDUCED DAMAGE ON 115 A THIN GATE OXIDES AND THEIR REMOVAL BY LOW TEMPERATURE PASSIVATION S. Kar, A. Pandey, and A. Raychaudhuri Department of Electrical Engineering, Indian Institute of Technology, Kanpur-208016, India and S. Ashok Department of Engineering Science & Mechanics, The Pennsylvania State University, University Park, PA 16802, USA

After thermal oxidation, the oxidized silicon substrates were exposed to Si ion beams. Metallization was then carried out to complete the KOS structures. Comprehensive small signal admittance measurements were made. The admittance data were analyzed by the standard approach used for the silicon/silicon dioxide interface states. The results for ion-beam-exposed samples exhibited many anomalies. In these samples, the trap density obtained from the ac conductance was much smaller than that obtained from the static capacitance. Secondly, very high and very low state capture cross-sections were obtained. Thirdly, G /w versus w profiles exhibited multiple peaks. These and other anomalies are caused by the induction of a high density of defects in the bulk silicon and the oxide and the formation of a high resistivity layer in the silicon subsurface. These results underscore the need for a different circuit model to analyze the admittance data of processdamaged MOS structures. INTRODUCTION Among the important features of ultra large scale integration, are the use of very thin gate oxides, and an ever-increasing exposure of devices to ion and other high-energy particle beams. Ion implantation, ion-beam-assisted etching and deposition are standard processes today. Emerging applications include ion beam lithography and ion beam annealing. In the early years of ion beam processing, it was possible to anneal out almost all the ion beam damage. This task is getting to be difficult in future for a number of reasons, an important one being limitations on annealing and processing temperatures to avoid dilution of profiles, wafer warpage, and cross-diffusions. The present study was undertaken to monitor and understand the characteristics of electronic defects in ion-beam-exposed metal-oxide-semiconductor (MOS) structures with thin gate oxides. The gate oxide is considered to be most prone to radiation damage. The emphasis in this study was laid on understanding completely unpassivated devices, so that all the signatures of the radiation-induced electronic traps could be catalogued, which in turn

483

can facilitate the development of an effective low temperature damage passivation technique. This catalogue should also be useful in process fault diagnosis. EXPERIMENTAL DETAILS The MOS structures were prepared in the following manner. P-type silicon wafers were oxidized in dry oxygen (containing HCI) at 950 0C to reach an oxide thickness of 115 A. Post-oxidation annealing was carried out at 950 0C in N2 for 15 min. Subsequently, the oxidized silicon wafers were exposed to 16 keV Si ions in a Varian 350D ion implanter at 300 K, such that the peak of the total target displacements was located at the silicon-oxide interface. Si ions were chosen 1 to deemphasjze the chemical effects. The ion dosage was varied from 1010/cm to 10 1/cm . Following implantation, Al front (1.0 mm dia dots) and Au back contacts were evaporated in an oil-free ion-pumped Varian VT-112 UHV system using filament sources. Most of the samples were characterized electrically without any sort of damage passivation or annealing. The electrical characterization was carried out using the Hewlett Packard 4061S semiconductor/component test system, equipped with 4192A impedance analyzer, 4140B pA meter/DC voltage source, 7475 graphics plotter, and the 310M controller. Direct current-voltage, quasistatic capacitancevoltage, and sinusoidal small signal capacitance-voltage, conductancevoltage, conductance-frequency measurements were made. The sinusoidal frequency was varied between 80 Hz and 3 MHz. Static capacitancevoltage measurements [1] were made using a Keithley 595 meter. Ellipsometric data were obtained using a Rudolph Research A7905 automatic ellipsometer. RESULTS AND DISCUSSIONS Many interesting new features were observed in the admittance characteristics of the unpassivated ion-beam-exposed M0S structures. One of these related to the experimental data obtained on interface state parameters. These parameters were obtained using the standard MOS admittance techniques [2-4]. In the case of the standard technique, it is assumed that all the traps, that contribute to the observed ac admittance, are located at the silicon/oxide interface. Figure 1 presents the interface state density distributions obtained from the static capacitance-voltage (C-V) characteristics [2], indicated by solid lines, as well as from the conductance-frequency (G-f) characteristics [3], indicated by broken lines, for samples with different ion dosages. For many ion-beam-exposed MOS structures, multiple peaks were observed in the Gp/w versus f (G is the parallel conductance, and w is the small signal angular frequency) profiles. It may be mentioned that for regular MOS structures only one such peak is seen. Figure 2 depicts the Gp /W versus f profiles for sample A12 for different bias values. Two peaks can be seen in each profile, and accordingly, two state density distributions were obtained for this sample from the ac conductance data, as indicated by A and B in Fig. 1. Figure 3 contains the profiles of the hole capture cross-section versus the silicon bandgap energy, for

484

the same samples as in Fig. 1. It may be noted that for sample A12, there are two profiles A and B, for the reason already mentioned.

FIG. 1: Experimental interface state density as a function of the bandgap energy, measured from the valence band edge, for samples, exposed to different ion dosages. The solid lines represent values obtained from the static capacitance data, and the broken lines, data obtained from the ac conductance data.

BANDGAP

ENERGY

leVI

SMALL SIGNAL

FREQUENCY

[Hz]

FIG. 2: Experimental parallel conductance/angular frequency [Gp/W] as a function of the sinusoidal small signal frequency, for sample A12, for two applied bias values.

485

VTn

.1

SAMPlE

AOl

r DOSE: NIL

N

I-

I612

ua

q

: tpetiiueiiai_ nole capture cross-section as a function of the bandgap energy, measured from the valence band edge, for samples, exposed to different ion dosages. For the profile B of sample A12, the right hand scale applies, while for the rest, the left hand scale.

U

e,

16"3

4e

SQ.CM. .;19 U

I

II

I

I

I

0.2 0.4 0.6 BANDGAP ENERGY [eVI

I

e.g

The profiles of Fig. I indicate that, with increasing ion dosage, the value of interface state density, obtained from the ac conductance, becomes progrssively smaller than that obtained from the static capacitance. It may be mentioned that if the defect states are located only at the interface, then in principle the same value of state density should be obtained from both static capacitance as well as ac conductance, as is the case for the control (unexposed) sample AO0, cf. Fig. 1. The profiles of Fig. 3 indicate unusually high and unusually low capture cross-sections for the ion-beam-exposed samples, while typical values are obtained for the control sample AO0. The source of these anomalies lies in the fact that in unpassivated ion-beam-exposed MOS structures, there is significant contribution to the ac admittance from traps located, away from the interface, in the oxide and in the silicon sub-surface layer. In the case of ion-beam exposed MOS structures, the bulk silicon traps may be created mainly by the atomic displacements, while the interface and the oxide traps may be created both by the atomic displacements and ionizations by ions/recoil atoms as well as attendant x-rays [5-7]. For the charging or discharging of oxide traps, the free carriers have to be transported from the silicon surface, most probably by tunneling through the oxide potential barrier [8]. The charging or discharging of the oxide, the interface, and the bulk silicon traps (all assumed to be multi-level) is illustrated in the energy band and the equivalent circuit diagrams of Fig. 4. It is assumed that only states located at or near the Fermi level take part in charging or discharging, i.e. the states whose energy levels intersect the silicon band-bending, as represented by the rectangular boxes in 486

Fig. 4a. In principle, the contribution to the static capacitance will come from all these states, although with varying weightages, since all the states should be able to follow the static signal. Figure 5a represents the reduction of the equivalent circuit in Fig. 4b at static frequencies. It may be noted that, as all states can follow the static signal, there is no loss involved, hence, the circuit of Fig. 5a is purely capacitive.

Ebt,==---EE

FIG. 4: (a) Energy band diagram of the MOS structure, for a given bias, illustrating the charging or discharging of the oxide traps (levels Eotl and Eot 2 ), the interface traps (level Eit), and the bulk traps (Ebtl and Ebt2). (b) Equivalent circuit representation of the MOS structure of Fig. 4a. Cox is the oxide capacitance. C 1 ' C and Cs 3 are capacitances of diterent sections of the surface space charge layer. If there is no contribution from the shallow dopants, these are then dielectric capacitors. Cbtl and Rbtl, and Cbt2 and Rbt2 represent the bulk trap impedances. Cit and Rit represent the interface state impedance. Cot, and Rot,, and Cot2 and Rot 2 represent the oxide trap impedances.

E-t-

I

I

I

SILICON 0

'X1

X,2

I

OXIDE 33 1ý4

I

I

INTERFACE IA 'r I -R it Rbt Rb~at W

C(b)d

CC

Cs2

Cot

COX

Cs 3

CA-Cotl.CWA

CS 1 .Cbt

Cs2

Cs3

Co,1 FIG. 5: (a) Represents the reduction of the equivalent circuit in Fig. 4b under the static condition. (b) Represents the reduction of the equivalent circuit in Fig. 4b at an intermediate frequency, such that the time constant of the bulk trap level Ebt2 at x - x 2 is 11w.

Rbt2 Cbt2 C51. Cb

Cs2

C5 3

Cox

In the case of ac conductance, comes mainly

from states,

whose

the contribution to the conductance

time constant

is

about 1/w.

This means

that, for a given bias, i.e. a given silicon band-bending, and a given signal frequency, the contribution to the conductance will come only 487

from states of one energy level and located in one or a few atomic planes. Figure 5b represents the reduction of the equivalent circuit in Fig. 4b at an intermediate frequency, such that the time constant of the bulk trap level Ebt2 at x - x 2 is 1/t, for the given bias. It may be noted that the traps located at the Fermi level in Fig. 4a to the right of x 2 cannot follow the intermediate signal, hence their equivalent series RC branches in Fig. 4b can be open-circuited, while the traps located at the Fermi level to the left of x 2 can follow the intermediate signal very well, hence the resistances in their equivalent series RC brances can be short-circuited. The very high and very low values obtained for the hole capture cross-sections can be interpreted in the following way. The source for the very low values of the cross-section may be the oxide traps, while for the very high values may be the bulk silicon traps. Since electrons/holes have to tunnel to the oxide traps, the free carrier density at the oxide trap is reduced by the tunneling probability. Since the standard MOS conductance technique has been used for data analysis, the value of the carrier density used for calculating the cross-section is what obtains at the interface, hence, orders of magnitude lower cross-section may have been obtained than the actual. On the other hand, for the bulk silicon traps, the actual free carrier density is orders of magnitude higher than that at the interface, hence, use of the standard procedure may lead to much higher values of the cross-section than the actual. Two factors may be responsible for the discrepancy observed in the state density profiles of Fig. 1. Kramers-Kronig relations holds for the interface states alone [3]. When bulk silicon and oxide states are also present in a significant manner, [G/w]max is no longer related to the total trap capacitance, as obtained from the static capacitance. This happens, because, contribution to the conductance at given bias and frequency always comes from states in one or a few atomic planes, while that to the static capacitance at a given bias will come from states in many atomic planes. Secondly, different equivalent circuits have to be used for the analysis of the static and the conductance data to obtain the actual state densities, as Figs. 5a and 5b indicate. The surface potential at a given bias is experimentally obtained by integrating the static capacitance-voltage characteristic [2]. For a regular MOS structure, the surface potential can also be obtained from the high frequency C-V characteristic, although with lower accuracy. For the ion-beam-exposed samples, it was found that the surface potential difference obtained from the high frequency C-V plot, for a certain bias range, was much larger than that obtained from the static C-V plot. The reason for this anomaly may lie in the fact that the high frequency C-V plot for these samples does not represent the space charge capacitance arising out of the shallow dopants. The atomic displacements in the silicon sub-surface generate bandgap states throughout this region, which trap free carriers donated by the dopants. This deactivation of the dopants leads to the formation of a high resistivity or an intrinsic 488

layer [9,10], and therefore, the high frequency C-V plot in an ion-beamexposed MOS structure may not have any relation to the theoretical space charge capacitance of shallow dopants. Another manifestation of an intrinsic layer in the silicon subsurface was the interesting observation of very low frequency dispersion of the accumulation capacitance. Figure 6 presents the measured static as well as sinusoidal signal capacitance-voltage charyateristics of sample A12, which was exposed to an ion dosage of 10 2/cm . For a standard MOS structure, the MOS capacitance approaches the oxide capacitance, and this capacitance does not exhibit any frequency dispersion at low frequencies. The following interpretation is possible for the frequency dispersion observed in the accumulation region in Fig. 6. The existence of the intrinsic layer results in the formation of a pi junction in series with the accumulation space charge layer, which is very thin. As the gate metal is an array of 1.0 mm dia circular dots, and the back contact area is orders of magnitude larger, the silicon subsurface region has to be represented by a distributed network, as illustrated in Fig. 7. Under the static condition, the lateral resistance elements R. 'a can be short-circuited, and the pi junction capacitance elements ake then in parallel. The sum capacitance SC4 p is much larger than the oxide capacitance, and so is the accumulation layer capacitance Cs, hence under the static condition, the MOS accumulation capacitance, Caccs, approaches the oxide capacitance. Static C-V measurements with different step delay times indicate the time constant R.C. to be in the range of 0.1-10.0 s, depending upon the ion dosage. At frequencies higher than the inverse of this time, the lateral series elements Ri 's can be open-circuited, which results in Cox Cs, and C being in series. As Ci is smaller than Cox, especially for very thit oxides, the MOS accumulation capacitance, C I becomes smaller than the oxide capacitance even at 80 Hz. At stilfcg hher frequencies, Caccss decreases further because of the series resistance R in the i layer. A value for this resistance was obtained from the impednce measurement on the impedance analyzer HP 4192A at 100 kHz under the accumulation condition. This measured total series resistance Rs was found to increase with the ion dosage, cf. Table I. Ellipsometric measurements indicated a change in the intermediate parameters 6 and 0 with the ion dosage, cf. Table I, which provides supporting evidence for the presence of a damaged layer at the silicon surface. Table I shows that the static MOS capacitance in accumulation Caccs increases significantly at high ion dosages beyond the value measured for the control sample. This increase could be partly explained by sputtering of the very thin oxide during the ion beam exposure. However, annealing was found to restore Ca c to the value measured for the cy troll sample. Also, calculations indicate that even at the dosage of 10 /cm , only a few A of the oxide could be etched at the most. The most likely interpretation of the oxide capacitance increase is the increase in the oxide dielectric constant due to space charge effects, caused by atomic displacements in the oxide. At high ion dosages, atomic displacements and replacements can give rise to significant non-

489

stiochiometry in the oxide [11], which in turn leads to silicon-rich oxide islands. These silicon-rich oxide regions, i.e. SiOx regions, where x is \7TMONOCHROMATO R PHTMULTIPLIER Fig. 1. Schematic of ellipsometer/RTP chamber system.

and z

cos1 (

i1j2a

)

(3)

The obtained values of 0 and A are then used to calculate the index of refraction of the silicon substrate using standard ellipsometry software [6]. The temperature dependence of the index of refraction of silicon, nsi = nsi -i,;si, at 6328A was measured by van der Meulen and Hien up to 1100°C and is shown in Fig. 2 [7]. This temperature dependence is then used to determine the temperature. Background radiation is the radiation reaching the photomultiplier which does not result from the light source. It could be radiation from the wafer itself if the wafer is at a temperature higher than 725 0 C, radiation from the heat source transmitted through the wafer, or any radiation reaching the photomultiplier by reflection. This com543

ponent of the light intensity must be taken into account by measuring it with the light source turned off and subtracting it from the total intensity with the light source turned on before calculating a 2 and b2 . This is easily done by inserting a light chopper in the incident branch of the ellipsometer and synchronizing its operation with that of the encoder. 3

4.4

2 02

4.0

1

3.8

T( 0 C) Fig. 2. Temperature dependence of the refractive index of silicon [6]. MEASUREMENT ON A FILM-FREE SURFACE First, we discuss the temperature measurement on a film-free silicon substrate. From the fundamental ellipsometry equation of a bare film-free surface, the real (nsi) and imaginary (Ksi) components of the index of refraction are calculated from [8] tan2

2nsinsi 2

sin 0

and

-

sin 40 sin A (1 + sin 20 cos A) 2

tan2 sin 2

=

0

24 - sin 2 24 sin 2 A 2 (1 + sin 20 cos A)

q-cos 2

544

(4)

(5)

where 0 is the angle of incidence. It should be noted here that two values of T could be obtained from Fig. 2, namely, T, based on the value of ns, and T, based on the value of Ksi. From Eqs. (4) and (5), it can be seen that the calculated values of ns; and KS; depend on the angle of incidence 0, and the measured values of b and A. It is also well known that nsi and Ksi also depend on the wavelength A. of the light source. Many sources contribute to defining the resolution of this temperature measurement technique such as (i) the accuracy with which we know the angle of incidence 0, (ii) the resolution with which we measure the ellipsometric parameters 0 and A, i.e., the resolution of the optical components of the ellipsometer, (iii) the numerical errors introduced in determining nsi and KSi from ellipsometry calculations, (iv) the surface conditions, (v) the influence of background radiation, and (v) the presence, growth or deposition of surface films during the measurement. INFLUENCE OF NUMERCIAL ERRORS Numerical errors are introduced in calculating the index of refraction using the ellipsometry software and in determining the temperature by poynomial fits of the dependence of nsi and rsi on T. The numerical error encountered in determining T is the sum of several non-interacting sources: errors arising from empirical fits of the data, errors resulting from truncation and roundoff during execution, and errors resulting from random events. It was found that the systematic error resulted primarily from the empirical polynomial fits of nsi and Ksi to T and vice versa. The truncation and roundoff errors were primarily random or normally distributed in nature and encountered in the ellipsometry program excecution and the supporting host computer software [9]. Upon correction for the systematic numercial errors, the random numerical errors in determining T were reduced from 5VC to +0.3°C using n8 i and to ±2°C using Ksi. The random numerical error in T, was constant at all temperatures, while that in T,, decreased with T to ±0.8°C in the 800-1000'C range [9]. 545

INFLUENCE OF ANGLE OF INCIDENCE € AND 0 AND A MEASUREMENT In an investigation of the systematic and random errors in the estimation of 0 and A, the role of the polarizer and analyzer imp erfections, the azimuth errors, and the residual birefringrence in the quartz windows were studied for a film-free, lightly doped, isotropic silicon substrate [9]. Errors in determining T caused by errors in the angle of incidence 0, and the angular resolution of the optical components were simulated assuming that these error sources were equivalent to an effective angular resolution 6 in the values of the ellipsometric parameters 0 and A [9]. The simulation proceeded by assuming a value for 6, and then finding the worst combination of b+ 6 and A ± 6 that resulted in the maximum error in T. The results are shown in Figs. 3 and 4, as the maximum possible error in T2, and T ,, respectively. It was found that for an angular resolution of 0.01° in 0 and A, the maximum temperature measurement resolution in this method is better than 3.6°C for temperatures up to 1100'C. It can be easily seen that the maximum measurement error is lower using T,, at low temperatures and using TK at higher temperatures. This is evident in Fig. 2 from the slope of Ksi which is higher than that of ns1 in the high-temperature range. INFLUENCE OF THE WAVELENGTH A. Early experimental results indicate that the wavelength of a He-Ne laser is not the optimal wavelength for determining the temperature of a silicon wafer for temperatures up to 500'C. The pseudodielectric functions of silicon were measured up to 5000C in a spectroscopic ellipsometer and it was found that temperature measurement at 3.0 eV would have a better accuracy. The index of refraction of silicon was calculated from these functions at 3.0 eV or 4133A, and the maximum error in T, and T , were calculated. The results are shown in Figs. 5 and 6. It can be easily seen that the maximum errors in T are smaller at 4133A than at 6328A.

546

E

Wafer Temperature ( C)

Fig. 3. Maximum error in T. as a function of T at 6328A [9].

CA

0

200

400

600

0 Wafer Temperature ( C)

800

1000

Fig. 4. Maximum error in T, as a function of T at 6328A [9]. 547

.JU

A = 4133A 0• = 70d = oA

=.-o

20

6 = 0.075*

a

"0 E

6 = 0.05* 10 6 = 0.025* 6 = 0.01* ,

, , I

.,

*.

.

0

A1

.

.

0 0

10O0

200 300 0 Wafer Temperature ( C)

400

500

Fig. 5. Maximum error in Tr as a function of T at 4133A [9].

a-

0 I-

n Wafer Temperature (°C)

Fig. 6. Maximum error in TK as a function of T at 4133A [9]. 548

INFLUENCE OF SURFACE FILMS The influence of the native oxide of silicon as a source of error in

temperature was also studied, and it was found that the oxide thickness and the temperature of the silicon substrate could be determined simultaneously [10]. The temperature of silicon wafers covered with a native oxide can be determined accurately. It was shown that both T and X., could be calculated from a measured set of 4 and A. In addition, this behavior of 4 and A with respect to T and X.o, is not limited to the native oxide regime. By extending the analysis of 4 and A to accomodate thicker oxides, it was found that the temperature and oxide thickness are uniquely determined by 4 and A up to oxide thicknesses of about 2650A for the same range of temperatures. For the case of film growth or deposition, automated ellipsometry lends itself to the in situ monitoring of fast processes. If the optical constants of the film under study are characterized as a function of T, it would be then possible to predict and control the trajectory of the process in the 4-A plane. The use in situ ellipsometry has been proposed as a method for end-of-process detection and applied to the rapid-thermal oxidation process [11]. CONCLUSIONS In conclusion, we discussed the principles of wafer temperature measurement using in situ ellipsometry. This method is a non-contact technique independent of emissivity which offers many advantages over pyrometers and thermocouples. Being a fast technique, it has wide-ranging possibilities for in situ temperature measurement and process control in many thermal growth and deposition applications.

This work was supported by the NSF/ERC on Advanced Electronic Materials Processing at North Carolina State University. We acknowledge many helpful discussions and the support of Profs. N. Masnari, J. Wortman, and J. Hauser.

549

REFERENCES 1. See for example: J. Nulman, in Rapid Isothermal Processing, R. Singh, Ed., the International Society of Optical Engineering, Bellingham, MA, Vol. 1189, 72 (1990), and references therein. 2. S. A. Cohen, T. 0. Sedgwick, and J. L. Speidel, Mat. Res. Soc. Syrnp. Proc., Vol. 23, 321 (1984). 3. R. E. Sheets, Mat. Res. Soc. Symp. Proc., Vol. 52, 191 (1986). 4. T. Tomita, T. Kinosada, T. Yamashita, M. Shiota, and T. Sakurai, Jap. J. Appl. Phys., Vol. 25, L925 (1986). 5. G. M. W. Kroesen, G. S. Oehrlein, and T. D. Bestwick, J. Appl. Phys., Vol. 69, 3390 (1991). 6. F. L. McCrackin, NBS Tech. Note 479 (1969). 7. Y. J. van der Meulen and N. C. Hien, J. Opt. Soc. Am., Vol. 64, 804 (1974). 8. K. H. Zaininger and A. G. Revesz, RCA Review, Vol. 25, 85 (1964). 9. R. K. Sampson and H. Z. Massoud, to be published. 10. R. K. Sampson and H. Z. Massoud, this symposium. 11. C. T. Yu, K. H. Isaak, and R. E. Sheets, ECS Fall Meeting, Seattle, Wa, October 1990.

550

FACTORS AFFECTING THE ECONOMIC PERFORMANCE OF CLUSTER-BASED FABS Samuel C. Wood and Krishna C. Saraswat Stanford University, Center For Integrated Systems, Stanford, California 94305 Open-architecture cluster tools are playing an increasingly important role in semiconductor manufacturing over the next decade. A subset of perceived advantages of cluster-based fabs are economic performance advantages. Modeling and simulation of a hypothetical fab is used to identify the extent of these advantages and the features of the cluster-based fab that are most important in determining those advantages. Results suggest that clustertools offer significant throughput time (or cycle time) advantages without serious compromises to the fab capital cost or cost per wafer, relative to conventional semiconductor manufacturing. Cluster-based fabs seem particularly suited for low-volume, fast turnaround manufacturing. These advantages are shown to depend on such issues as equipment costs, cluster tool features, and innovative management of fab operations. INTRODUCTION Over the last decade, cluster tools have been playing a role of increasing importance in semiconductor manufacturing. Cluster tools typically consist of the following components: one or more loadlocks where lots of wafers enter the tool; two or more process modules where the processes are performed; and a wafer handler consisting of one or more robots to transport wafers between the different parts of the cluster tool. Cluster tools can be subdivided into two classes: closed architecture and open architecture [1]. Closed architecture tools are typically sold by one vendor as a discrete machine with a proprietary communications and mechanical interface architecture. Open architecture systems are more oriented toward modular designs, where a systems integrator may buy a wafer handler, loadlocks, and process modules from independent vendors and configure the system according to the needs of the final user [2]. Although there is still some controversy surrounding the benefits of cluster tools, the tools will probably become increasingly prevalent over the next decade. Futuristic visions of highly automated, flexible fabs oriented toward rapid product innovation and production often include the idea of cluster tools [e.g., 3]. In addition, major semiconductor manufacturers such as IBM and Texas Instruments have already committed to using substantial levels of cluster-based manufacturing, and other semiconductor manufacturers and Sematech are presently evaluating cluster tools for their facilities [4,5,6]. It is likely that a significant portion of the cluster tools in such future facilities will be open architecture. The fabs just mentioned already use or plan to use open architecture tools to varying degrees. Also, SEMI's Modular Equipment Standards Committee (MESC) is developing a set of mechanical and communications standards for cluster tools to facilitate the design of integratible process modules and wafer handlers [7]. Recently, MESC compatible modules and handlers have already begun to appear on the market [1]. Single wafer processing technology is currently at the point where the majority of the process steps in a typical process flow could theoretically be performed in cluster tools. This suggests the possibility of a hypothetical fab where almost all of the process steps are performed in cluster tools (the major exception being ion implantation). Lithography 551

operations could be performed in atmospheric-pressure cluster tools, while the other cluster tools would be held at vacuum. Much of the enthusiasm for cluster tools stems from the perceived advantages of such cluster-based fabs. These perceived advantages can be grouped into three general categories: technological, strategic, and performance. Technological advantages include die yield improvements due to decreased exposure to contamination, and superior process technologies made possible by transferring wafers between process chambers under vacuum. Possible strategic advantages include addressing markets where short product lead times or a diverse line of low volume process flows are critical competitive factors. Performance advantages can be expressed as improved economic characteristics of the fab such as throughput time (also called cycle time or manufacturing interval) and cost per wafer. The rest of this paper will be restricted to the performance class of advantages. It is true that technological and strategic advantages of cluster-based fabs are probably critical in determining the ultimate role of cluster-tools in semiconductor manufacturing, and work has at least begun in characterizing the advantages. [5, 8] and [3,9] respectively. However, there is an implicit requirement that these cluster-based tools also be at least comparable in economic terms to their conventional counterparts. This paper describes the modeling and simulation of a hypothetical cluster-based fab with the goal of beginning to qualify the general economic performance of cluster-based fabs, and the cost, process, and operations issues critical in determining that performance. THE MODEL Cluster tools, particularly open architecture tools, probably represent a technology that is far from mature. However, descriptions of emerging products as well as industrial and academic literature are already sufficient to make a reasonable description of a cluster-based fab. The model in this paper is a refined version of a model presented in a previous paper [10]. That paper details the model to a greater extent than this paper and also contains a more extended discussion of the model's underlying assumptions. To provide an understanding of the model, this paper must summarize that work before moving on to this paper's focus on the factors determining fab performance. Potential time and cost advantages come from a number of general attributes of the cluster-based technology. Detailed descriptions of these attributes have appeared previously, [10] and include rapid single wafer processing, flexibility in processing, extensive in situ process monitoring, and vacuum transfer of wafers reducing wafer cleaning requirements. One should note that these attributes suggest a cluster-based fab that not only differs from a conventional fab in terms of its physical equipment, but also in terms of other features such as the physical process flow, CIM system requirements, equipment control, and wafer transport. Figures 1 and 2 summarize the models of the model's two varieties of cluster tools. Since cluster tools lend themselves more easily to hermetically sealed wafer carriers, it is assumed that lots are transported between clusters in vacuum carriers. The vacuum cluster can simultaneously accommodate and process a lot of wafers from each loadlock. Each vacuum cluster has two or three process modules. The lithography cluster requires a longer setup time to initialize the stepper and vent the vacuum carrier. Since this setup is required for each new mask, the lithography cluster only accommodates one lot at a time. The average cost in both figures refers to purchase plus installation. While estimates of the

552

"*Average Cost: $1.3 million "*Independent Loadlocks * Can accomodate two lots simultaneously * Loadlock pumping and venting: 5 minutes total

"*Wafer transfer time: 45 seconds "*Operator tend time: 5 minutes, including loading

" Internal handler scheduling: FIFO - Required clean room area: 100 square feet Figure 1:

Schematic of vacuum cluster tool.

"*t•verageCos V.7.; rujnul "*Can accommodate one lot at a time

"*Initial

15 minutes for setup and wafer carrier venting

"*3 minutes for wafer carrier evacuating

"*Wafer transfer time: 15 seconds

"•Operator tend time: - Required clean room area: 150 square feet

Figure 2:

Schematic of lithography cluster tool. 553

future mature cost of such a young technology are inevitably controversial, the costs are roughly consistent with those given for contemporary equipment [11]. As a benchmark for comparison, a conventional fab is also modeled. Table 1 summarizes the equipment in the two fabs. The amount of equipment is chosen to balance the fab as well as possible. The cost of a cluster is calculated by adding the cost of the cluster's frame to the modules in the cluster. The numbers given in this model vary considerably from vendor to vendor, and represent a vision for the next few years rather than past experience, particularly in the case of time available. The conventional equipment costs are generally consistent with those in published studies [121. Table 2 summarizes the process flow in the two fabs. The process flow to be simulated is a 0.6 micron DRAM process developed to produce 16 Mbit DRAMs. The flow is based on an experimental (not a production) flow developed at Texas Instruments. The flow was further altered to protect the proprietary interests of TI, and to better reflect traditional technologies outside TI. The cluster-based flow was then generated by directly transferring small sets of conventional operations to their rapid single-wafer processor counterparts. In a very small number of cases, the flow itself was altered between the fabs. For example, a self-aligned well process which was advantageous only for the conventional fab was translated to an extra mask set (non self-aligned process) in the cluster flow. Also, some implants in the cluster-based flow were done at multiple energy levels which decreased diffusion times at the expense of longer implant times. Process data for the cluster-based flow came from interviews with engineers in relevant companies, as well as a survey of the academic and industrial literature, and experience at Stanford in developing and using its Rapid Thermal Multiprocessor [13]. One striking difference in the resulting flows is between the total number of process steps. This is mainly due to the reduction in the number of steps required for a given clean, the reduction of total required cleans, the replacement of ex situ measurement steps with in situ monitoring, and the integration of multiple conventional steps into single cluster module steps. Another striking difference is between the total process time per wafer. This is a result of the switch from slow batch processes to rapid single wafer processes. Table 3 is a comparison of some key features of the two fabs. This table is intended to illustrate some important qualitative differences between the two fabs. Previously mentioned work describes a similar table in more detail than there is room for here [10]. However, a few features in the table require explanation. An "equipment group" is a set of interchangeable equipment that can perform the same process step. "Pipelining" refers to the splitting of a lot of wafers and processing them through a sequence of equipment one wafer at a time. This is an important feature of cluster tools which results in a reduction in the time to perform a sequence of process steps [4]. The difference in the required class and cost per area of the clean room for the two fabs is due to the fact that wafers are assumed to be transferred in sealed carriers in the cluster-based fab, and traditional cassettes in the conventional fab. Finally, results described later in this paper suggests that smaller lot sizes are more appropriate for cluster-based fabs. The cluster-based lot size of 12 is a result of this conclusion. The capital and annual operating costs are broken down into their components in a previously mentioned paper [101. Although the fabs are smaller (as shown by the "approximate capacity" line in Table 3) than many conventional DRAM "mega-fabs," the costs of the two fabs may still appear to be low for their size. This is probably due to the fact that such sources of expense as fab design and engineering fees, and equipment and 554

Cos

Cost

I"

Number Pece(Sk) Cost (Sk

Faulmient Fam.i steppers spin/develop wet station fumaces single-wafer dry etch cvd chambers medium current ion implanters high current ion implanters sputterers ashers in line, ex situ metrology other in line process equipment other equipment

8 15 16 23 38 9 3 2 3 8 18 24

2500 500 643 437 674 901 1500 2800 2100 240 336 134

20000

7500 10280 10045 25616 8111 4500 5600 6300 1920 6051 3220 15100

Ibi

Avaflahh 97 93 91 96 91 84 86 85 85 98 87 98

CLUS• Averavt Equipment Family

Number

Cost er

otal

Piee (Sk) Cost (ik

T ime

Available

stepper modules spin/develop modules uv/bake modules

10 20 15

2500 500 100

25000 10000 1500

97 93 99

dry clean modules rtp (non-cvd) modules rtcvd modules etchbstrip modules sputter modules ash modules

49 26 27 24 5 11

333 310 377 406 545 260

16320 8055 10180 9755 2725 2860

90 90 90 90 90 90

4 2 4 1

1500 2800 493 45

6000 5600 1972 45 15000

86 85 91 88

49 10

165 280

1650 13720

100 100

medium current ion implanters high current ion implanters in line, ex situ metrology laser scribe other equipment vacuum cluster frames lithography cluster frames

Notes: 'Tune Available" includes time for conditional setups, but does not include scheduled maintenance such as changing chemicals, or equipment down times. A "cluster frame" is a combination of wafer handler and loadlocks. These figures are intended to reflect goals for fabs in the mid-1990s. Table 1: Equipment summary for the two baseline fabs. 555

CONVENTIONAL FAB proes family

oe capacity

1 wafer furnace thermal/cvd < 200 wafers other cvd ý5 6 wafers 1 wafer

scribe

"sputter

*dry etch wet processes ash *implant resist coat/dev/bake "pattern expose metroloy

1 wafer < 48 wafers 48 wafers 1 wafer 1 wafer 1 wafer 1 lot

total

average number proc doe of eps per wafer

50 Seca

1

total proes doe6 per wafer

0.8 mine

91.0 hrs 40 137 mine 7 " 3.8 hrs 5 163 sece 13.6 mine 22 422 Seca 154.8 mine 239 16 mine 63.3 hrs 21 53 mine 18.7 hrs 12 79 seca 15.9 mine 55 130 secs 119.3 mine 16 128 sees 34.1 mine 134 8.2 mine 18.2 lre 200.5 hre 552

total

fraction Of

proc@ sDe total lot per lot proes time

0.3 hrs 91.0 16.1 1.1 61.9 63.3 18.7 6.3 47.7 M3.6 18.2

hrs hre hrs hrs hrs hrs hrs hrs hre lre 338.2 hre

0.09% 26.91% 4.76% 0.33% 18.30% 18.72% 5.53% 1.86% 14,10% 4.02% 5.38% 100.00%

CLUSTER-BASED FAB

""rerals proem family 1 1 1 1 1 1 1 resist coat/dev/bake I I pattern/expose scribe rapid thermal/cvd sputter etch/strip clean ash

"implant

metrology

1

proem capacity wafer wafer wafer wafer wafer wafer wafer wafer wafer lot

total

amble of ase 1 42 4 31 47 16 12 52 17 16 231

proc tane per wafer 50 seam 283 secs 228 seas 209 seas 225 seca 145 sas 87 sees 137 seas 152 seas 16 mine

total proem dU per wafer 0.8 mine 198.2 mine 15.2 mine 108.0 mine 178.1 mine 38.7 mine 17.5 mine 118.3 mine 43.1 mine 260.0 mine 16.2 hre

fraction of total proese tea3 total lot per lot process tdme 0.14% 0.2 hre 39.7 hre 26.92% 2.03% 3.0 hre 14.64% 21.6 hrs 35.2lhrs 23.86% 5.22% 7.7 hlr 3.5 hlr 2.37% 16.07% 23.7 hre 5.83% 8.6 hlr 4.3 hre 2.92% 147.5 hre 100.00%1

* Single asterixed processes involve substantial conditional set up times, which are not necessarily the same from process run to process run.These conditional set up

times are not included in "process time." ** Conventional equipment in the "other cvd" category include batch and singlewafer processors, so "average process time per wafer is not really meaningful.

Other notes: A process step is a visit to a cluster module, wet bath, or conventional machine. Process times include regular equipment setups as well as time for stabilization of temperature, gas flows, etc. These stabilization times represent about a third of the process times for the cluster-based processes. Process times do not include equipment loading and unloading. The lot size is 24 wafers in the conventional fab and 12 wafers in the cluster-based fab. Table 2:

Process summary for the two baseline labs.

556

Capital Cost Process Flow Number of Equipment Groups Number of Equipment Pieces Pipelining? Approximate Capacity Minimum Operator Transfers

$153 million 0.6 pm DRAM 39 198 yes 4700 waf/mo 120 238 16 45 hours 10455 sq ft $16.6 million $700 per sq ft

$157 million 0.6 pim DRAM 63 182 no 6000 waf/mo 551

Total Number of Process Steps 552 Number of Measurement Steps 112 Minimum Cycle Time (1 wafer) 283 hours 12017 sq ft Clean Room Area Fab Operation Cost (per year) $17.7 million $2000 per sq ft Cost of Clean Room Cost of Process Consumables $100 per wafer (purchase and dispose) * 24 lot size *

$100 per wafer 12

Table 3: Comparison of key features between the two fabs. Asterixed bold-faced entries are exogenously determined (independent) parameters.

50004000cost per

wafer (dollars)

conventional

300020001000. 0

l

0

10

l

iI

20

30

40

median throughput time (days)

Figure 3:

Performance comparison of the fabs described in previous Tables. 557

process characterization are not included in the capital cost, and that sources of expense originating outside the fab such as allocated corporate overhead are not included in the operating cost. The operating cost does, however, include depreciation of the capital costs. SIMULATION Descriptions of the equipment, process flows, operators, costs, maintenance schedules, and transportation times were specified in eleven files for each simulation. The simulation software has been described in detail previously [14]. The main source of random variation in the fab is equipment failures. The software runs a monte carlo simulation for a specified number of lots and then produces six output files summarizing throughput times, costs, utilizations, and other performance metrics. Simulation results produced the performance relationships for the two fabs shown in Figure 3. Each point on the two curves represents a separate simulation at a specified fixed inventory level. (Intermediate curves used to generate curves such as this have been illustrated previously 110,15].) The points on the left portions of the curves represent light loadings (i.e., low work in process inventories). In this region, there is little congestion in the fab, and so wafer lots are unlikely to have to wait at machines while other lots are processed. This lack of congestion makes quick throughput times possible. On the other hand, lightly loaded fabs have low throughput rates (i.e., wafer starts) and low equipment utilizations, and so fixed costs such as fab depreciation are amortized over a relatively small number of wafers. This is why the cost per wafer is relatively high in the lightly loaded region. The points on the right portion of the curves represent high work in process inventories or heavy loadings. In this region, increased congestion results in slower throughput times, but also better throughput rates resulting in lower costs per wafer. In general then, the vertical asymptote represents a case where a small number of wafers rush through the fab unhindered. The horizontal asymptote represents a case where large numbers of wafers slowly travel through heavily utilized equipment, and spend most of their time waiting at occupied equipment Figure 3 represents a tradeoff between two key economic parameters that help determine the profit generated by the fab (and thus the fab's value). The cost per wafer is clearly critical since it determines the cost to produce the fab's product. The throughput time is also important, however, because it plays a significant role in determining the value of the wafer. Advantages of rapid throughput times have been described previously [15] and are summarized here: (1) A reduced throughput time can result in faster turnaround for circuit and process experiments and characterizations. This can result in faster innovation and earlier entry into product markets, which in turn can result in higher prices for the product on the wafers, and increased market share [16]. (2) A reduced throughput time on existing products improves responsiveness to customers and market variations, which can improve the demand and price for the product [16,17]. (3) Shorter throughput times reduce the time the wafer exposed to potential yield-reducing contamination, which could increase the number of working chips per wafer [181. As market constraints change, the optimal operating point on the curves in Figure 3 also change. For example, a fab producing ASICs for customers paying a premium for fast order turnaround may operate in the low throughput time regime. A fab ramping up yield and volume for a memory product may start in the low throughput time regime and move to higher throughput times as process understanding and yields improve. For the remainder of this paper, the cost per wafer and throughput time will be considered the two primary economic performance factors in determining the fab's value. This papers next section is aimed at identifying critical factors that determine the shape and position of this curve. 558

PERFORMANCE FACTORS Scale and Equipment Cost Figure 4 shows how the performance curves vary with the cost constraint on the conventional and cluster-based fabs. The smaller fabs have degraded performance for at least two reasons. First, smaller fabs are harder to balance, so more equipment is underutilized even when the fab is configured in an optimum way. Second, since there are less copies of machines in the smaller fabs, performance is more likely to suffer when equipment breakdowns occur. In fact, increasing the copies of equipment available for a specific process generally improves fab performance even in fabs without equipment failures [19]. An important conclusion of Figure 4 is that conventional and cluster-based fabs seem to scale similarly with capital investment. When fabs need to be small, either due to the capital constraints on the firm building the fab, or the size of the market the fab is addressing, the cluster-based fabs may be superior even in the low wafer cost operating regime. For the model assumptions, this cross-over point seems to be for fabs with a cost of around $100 million. The impact of the cluster cost assumptions on fab scaling is addressed in Figures 5 and 6. Figure 5 shows how the maximum throughput rate of the fab changes with the cost of the fab for different vacuum cluster cost assumptions. As stated before, the average cost of a vacuum cluster was roughly $1.3 million for the previous figures. At this cluster cost, cluster-based fabs with capacities less than about 2500 wafers/month are less expensive than their conventional counterparts with the same capacity. In other words, for fabs smaller than this threshold the two curves in Figure 3 would not intercept; the cluster-based fab would be superior at all wafer costs. The other two lines in Figure 5 show the effect of varying the average vacuum cluster cost between two extremes. For an average cluster cost of $0.5 million, the cluster-based fab is generally superior, and for an average cluster cost of $3 million, the cluster-based fab is generally inferior. Readers should note that this figure contains no information about throughput time. The capacity level of the fab simply determines the horizontal asymptote on the wafer cost versus throughput time relationship in Figure 3. This horizontal asymptote for each fab size is plotted in Figure 6. This figure essentially presents the information in Figure 5 in a different form. Rather than expressing the size of the fab in terms of its capacity, the size of the fab is expressed as its minimum achievable cost per wafer. There are a number of factors other than equipment cost which affect the curves in Figures 5 and 6. One of these factors is the process flow. When the total time a wafer requires of an equipment group is reduced, less copies of that equipment are required to achieve the same throughput rate. In other words, for a given fab capacity, reducing such process parameters as set up times or process times (particularly on slow or expensive equipment) would tend to make the curves in Figure 5 steeper, which is desirable. Another factor that determines the shape of the curve is how many different processes one equipment type can perform. This main impact of this type of versatility is on the lower portions of the curve in Figure 5. Increased process versatility is likely to both decrease the minimum achievable fab cost and capacity, and also decrease the fab cost for existing low capacities. This feature has resulted in an interest in developing highly versatile "multiprocessing" equipment for low cost, low volume "micro factories" [13].

559

CONVENTIONAL FAB 50 $68 million

40 cost per 3 wafer (dollars) 20

$70 million

10

$101 million $157 million

0.00

10.00 20.00 30.00 40.00 median throughput time (days)

CLUSTER-BASED FAB

$53 million 4000 cost per 3000-. wafer (dollars) 2000

$55 million

$95 million

1000 0

0.00

million

a$153

10.00

20.00 30.00

40.00

median throughput time (days) Figure 4: Families of performance curves for conventional and cluster-based fabs. Each curve represents a different tab. The curves are labeled with their capital costs. The capital cost of the tab is varied by altering the amount of equipment in the fabs.

560

5000 4000 capacity of fab 3000 (wafers per month) 2000

1000 0 0

50

100

150

200

cost of fab (millions of dollars) Figure 5: Capacity versus cost for different fabs. The thin curve corresponds to the conventional fab described in Tables 1-3. The bold curves correspond to the cluster-based fab described in the same tables, except with varying vacuum cluster costs. The curves are labeled with their corresponding average vacuum cluster costs.

'$3M

•AA

DUUU'

$1.31 minimum

cost per

wafer (dollars)

4000-

$500k

300020001000. conventional

0 0

50

100

150

200

cost of fab (millions of dollars) Figure 6: Minimum cost per wafer versus fab cost for the same fabs in Figure 5 above.

561

Cluster Characteristics Performance characteristics of the cluster tool are factors which may deceivingly appear to be of little consequence in determining the overall performance of the fab. Many of the cluster tool characteristics turn out to be surprisingly important however. Figure 7 shows a performance curve for similar fabs with different wafer transfer times. The wafer transfer time is the time that passes from a wafer being completed in one module until that wafer is ready to start processing in the next module. This time is not only determined by the speed of the robotic arm, but also by the cluster host control system and the pumping and venting of intermediate volumes. The 45 second curve is the same curve that represents the clusterbased fab in Figure 3. Even though the 15 second curve is for a less expensive fab, that fab outperforms the 45 second fab in all regions of the performance curve. (If the fab costs were equal, the difference would be even greater than in Figure 7.) Although the improvement in fab performance may not look that significant in Figure 7, initial estimates suggest that the transfer time improvement could increase the scale cross-over point in Figure 5 by at least several tens of millions of dollars (for the $1.3 millioincurve). Another important characteristic of the cluster tool is its ability to simultaneously process multiple lots residing in multiple loadlocks. This feature results in at least two advantages. One is that one lot can be processed while the other loadlock is pumped or vented. The second advantage is that different lots utilizing different parts of a given cluster tool can be processed at the same time, balancing the utilizations of each module in the cluster tool. Although rather subtle, initial work suggests that the second advantage is the more significant, particularly for smaller fabs and cluster tools with quick loadlock pump/vent times. Exploiting that advantage depends on a reasonably sophisticated scheduling techniques, which are identified further in the next subsection of this paper. Configuration and Operations Management The tasks of configuring and managing cluster-based fabs are likely to be considerably more difficult than the corresponding tasks for conventional fabs. One of these tasks is choosing the appropriate lot size for the fab. In a conventional fab, relatively little effort is devoted to the choice of lot size, since varying the lot size does not seem to dramatically impact the performance of the fab (at least favorably). Figure 8 shows the effect of varying the number of wafers per lot in the cluster-based fab. The 12 wafer curve is the same curve as the cluster-based curve in Figure 3. The other two curves are the results of changing the lot size in the fab which was optimized for a lot size of 12. Re-optimizing the fabs for the respective new lot sizes is expected to reduce the minimum cost per wafer an additional $70 for the lot size of 6 wafers, and $30 for the lot size of 24 wafers. As the plot suggests, the choice of lot size determines the cost per wafer versus throughput time tradeoff of the fab. In the low throughput time regime, smaller lot sizes are optimal, while larger lot sizes are optimal for fabs aimed at operating at minimal cost. This plot also suggests that lot size should be increased as fab production is ramped up. It should also be noted that increasing the lot size improves the appearance of the cluster-based fabs in Figures 5 and 6, since only minimum wafer cost is important in those figures. There are other new issues that the cluster-based fab manager must confront as well. One of these issues is the configuration of an open-architecture fab. The manager must presumably choose the number of each process module, and then how those modules are to be arranged into cluster tools. The traditional approach to balancing a conventional fab is to choose a number of copies of each piece of equipment so that the utilization of the 562

3000 2500 2000-

cost per wafer (dollars) 1500.

1000.

45 seconds

500-

15 seconds

0

_-

0

5

-

_-

-

10

15

20

_-

25

throughput time (days) Figure 7: Performance curves for fabs with different cluster wafer transfer times. The 45 second curve is for the $153 million lab described in the earlier data tables, while the IS second curve is for a similar $133 million lab running the same process flow.

%UUU *

2500.

6 2000. wafers

cost per wafer (dollars) 15 0 0.

1000. 500. 0

I

0

5

10

I I

15

"I

20

25

throughput time (days) Figure 8: Performance of cluster-based fab with different lot sizes. The fab was optimized for a lot size of 12 wafers. 563

equipment is equal across the fab. This approach does not work for cluster-based fabs because process modules may be kept idle while other parts of the cluster are occupied. In other words, a module utilized at 60% in a cluster-based fab could be a bottleneck even if there are other modules utilized at 70%. This often counterintuitive situation made the cluster-based fab configuration much more challenging than the equivalent procedure for the conventional fab. The optimal balance of modules depends on wafer transfer time, lot size, loadlock pump/vent times, and the fab scheduling policy. Once the fab is configured the manager must then choose how to choose which lots go to which of the potential clusters that could process the lot, [10] and how wafers in different lots competing for the wafer handler and process modules should be scheduled within the cluster. Making optimal choices in each of these areas can significantly affect the shape and position of the fab performance curves. CONCLUSION The modeling and simulation of cluster-based and conventional fabs running a modem process was used to investigate the potential performance characteristics of openarchitecture cluster-based fabs. In general, the cluster-based fabs seem to be comparable in their capital cost requirements and cost per wafer performance. However, the cluster-based fabs offer significant advantages in the area of throughput time which could dramatically improve the profit potential of the fab. Specific areas which were identified in determining the economic performance of cluster-based fabs include the size of the fab, the cost of the cluster tools, the process flows in the fab, the characteristics of the cluster tool itself, and fab configuration and management strategies. One area where cluster-based fabs offer particular advantages is for fabs with small cost or small production volume requirements. ACKNOWLEDGEMENTS Portions of this work were supported by the Semiconductor Research Corporation and by Texas Instruments. In particular, the authors are grateful to Graydon Larrabee at TI for his assistance. BIBLIOGRAPHY [1] [2] [3] [4] [5] [6] [7] [8]

N. Korolkoff. "Integrated Processing Part 11 -- Cluster Tool System." Solid State Technology, October, 1990. P. Burggraaf. "Integrated Processing: The 1990s Trend." Semiconductor International,Jueft, 1989. G. B. Larrabee. "The Intelligent Microelectronics Factory of the Future." InternationalSemiconductorManufacturingScience Symposium. San Francisco, California. May 20, 1991. A. S. Bergendahl, D. V. Horak, P. E. Bakeman, and D. J. Miller. "Cluster Tools, Part 2:16 Mbit DRAM Processing." SemiconductorInternational,September, 1990. T. K. McNab. "Cluster Tools, Part 3: Technical Issues." Semiconductor International,October 1990. W. Iversen. "Could This be the Factory of the Future for Low-Volume Chip Production?" Electronics,January, 1989. B. Newboe. "Cluster Tools: A Process Solution?" Electronics,July, 1990. R. S. Freund, ed., SPIE Proceedingson Multichamber and In-Situ Processingof Electronic Materials.October 10-11, Santa Clara, California. 564

[9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]

W. E. Steinmueller. '"he Economics of Alternative Integrated Circuit Manufacturing Technology: A Framework and Appraisal." Center for Economic Policy Research working paper. Stanford University. April, 1991. S. C. Wood and K. C. Saraswat. "Modeling the Performance of Cluster-Based Fabs." InternationalSemiconductorManufacturingScience Symposium. San Francisco, California, May 20, 1991. T.K. McNab. "Cluster Tools, Part I: Emerging Processes." Semiconductor International,August, 1990. "16 Mb DRAM -- 8 in. Line Cost Merits." SemiconductorInternational,February, 1991. K. C. Saraswat, et al. "Rapid Thermal Microprocessing for Micro Factories." SPIE Symposium on MicroelectronicProcessing. Santa Clara, California, October, 1989. S. C. Wood, K. C. Saraswat, and J. M. Harrison. "Cost Performance Modeling of Semiconductor Fabs." SRC Techcon 90. San Jose, California, October 18, 1990. S. C. Wood, K. C. Saraswat, and J. M. Harrison. "The Economic Impact of Single Wafer Multiprocessors." SPIE Conference on Rapid Thermal andRelated ProcessingTechniques. Santa Clara, California, October 2-3, 1990. B. C. Cole. "Getting the the Market on Time." Electronics,April, 1989. G. Stalk, Jr. "Time -- The Next Source of Competitive Advantage." Harvard Business Review, July-August, 1988. L. M. Wein. "On the Relationship Between Yield and Cycle Time in Semiconductor Wafer Fabrication." Submitted to IEEE Transactionson Semiconductor Manufacturing in January, 1991. S. C. Wood, J. M. Harrison, K. C. Saraswat. "Performance Modeling of Multiprocessor Fabs." SRC IFM-IC Workshop, Bryan, Texas, November, 1989.

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SINGLE-WAFER RAPID THERMAL CVD TECHNOLOGY FOR FABRICATION OF MOS AND BIPOLAR DEVICES Ahmad Kermani, Fred Wong and Kris E. Johnsgard RAPRO Technology Inc., Fremont, CA 94539 In fabrication of MOS, bipolar and BiCMOS integrated circuits, single-wafer rapid thermal chemical vapor deposition (RTCVD) can provide the foundation for a wide range of processes. In addition, a number of processing steps can be integrated to a central wafer handler to provide an applicationspecific tool. The applications include MOS gate dielectric, poly-emitter bipolar interface engineering, polysilicon deposition, and single or multi-layers of blanket or selective homo or hetero-epitaxy films. It is increasingly apparent, especially with the advanced generation technology employed for large substrates, that the level of control required can only be achieved when processing sequences are executed in a single-wafer mode under a controlled environment. A combination of low-temperature reduced-pressure wafer cleaning, dielectric, engineering and polysilicon deposition will satisfy the requirements of this emerging concept of integrated, environmentally controlled front-end processing for the MOS gate and poly-emitter bipolar applications. INTRODUCTION For fabrication of small geometry ICs, reduced thermal budget processing is mandatory to restrict dopant movement for maintaining shallow junctions. Furthermore, for stability reasons, strained layer SixGel-x HBT structures can not be subjected to high-temperature processing [1]. For low-thermal budget processing, RTCVD was introduced to provide an alternative to conventional long-time, slow-response batch furnace technology. In this approach, thermal energy is provided by radiative heating in a cold-wall environment. Due to small thermal mass of the system, rapid changes in wafer temperature, both up and down, is made possible. In parallel, various dry low-temperature wafer cleaning techniques have been developed [2,3,4,5]. The key is to effectively clean the wafer at low temperatures (below 6000C) and to maintain surface cleanliness between various processing steps. Dry-phase, anhydrous HF cleaning at room temperature supplemented by UV/ozone treatment has been used to effectively remove the surface native oxide and hydrocarbon residues [6, 7]. This technique has attracted a lot of attention due to its simplicity, ease of integration and low cost. Furthermore, it can be applied to fabrication of both MOS and bipolar devices. 566

INTEGRATED PROCESSING

For both the MOS gate electrode or the bipolar emitter contact applications, the polysilicon deposition immediately follows the most critical step in the process sequence, i.e. the gate oxidation in the MOS devices, and the preparation of the emitter contact in bipolars. Sequential processing of silicon wafers, gate oxidation followed by in-situ deposition of polysilicon electrode without exposing the wafers to atmospheric ambient, has been shown to improve the device yield [8]. The results of comparing the breakdown performance of in-situ and ex-situ deposited polysilicon electrodes for PMOS capacitors are shown in Figure 1. For these samples,

I

I

0

1

2

4

6

8

9

10

11

12

13

Breakdown Voltage, Volts

Figure 1. A comparison of intrinsic integrity of PMOS capacitors for insitu vs. ex-situ deposited poly-Si electrodes on 115 A of gate oxide. the breakdown voltage was measured after the capacitors were ramped to 90 percent of the breakdown level once. For bipolar devices with poly-emitter technology, control of the polysilicon / silicon substrate interface is the key parameter for performance repeatability. Conventionally, a thin oxide layer is chemically grown on the silicon substrate prior to polysilicon deposition. Chemical oxide films are silicon-rich and have a rough surface morphology. Due to the delay between their growth and polysilicon deposition, control of the oxide thickness is poor. Both native and chemical oxide films are thermally 567

and chemically unstable and break down during the polysilicon deposition and emitter drive-in steps [9]. Ronsheim, et. al, [10] have reported on the correlation between the polysilicon / silicon interfacial oxygen content and the bipolar transistor performance. As expected, the transistor gain increases by the increasing amount of interfacial oxide thickness. The increase in the emitter resistance, however, becomes very severe at higher interfacial oxygen content. Tejwani, et. al, [11] have reported on the feasibility of improving the transistor gain without sacrificing the device speed, as evidenced by the value of the emitter resistance. An alternative approach to interfacial oxide growth and polysilicon deposition employs a bipolar poly-emitter integrated processing tool to clean, form and cap the interface [12]. Using the emitter resistance as a figure of merit, the effect of various wafer transfer media on poly-emitter interface characteristics is shown in Figure 2. The comparison is between hot and cold (1000C) conventional furnaces and single-wafer RTCVD. The RTCVD sample received an in-situ hydrogen clean prior to polysilicon deposition. This cleaning step completely removed the interfacial oxide, resulting in the lowest emitter resistance value. Depending on the device application, a controlled ultra-thin interfacial oxide film can be grown prior to the polysilicon deposition. For optimum performance, the thickness of the interfacial oxide must be controlled to balance the benefits of the higher transistor gain and the increase in the emitter resistance.

I

2.0e+15

4.0e+15

6.0e+15

8.00+15

1.0e+16

1.2e+11

Implant Dose, 1/cm2

Figure 2. The effect of wafer transfer media on the emitter resistance, "cold" furnace conditions are 6250 and 1000C, respectively.

"standard"and

568

MOS Gate Dielectric Engineering One application of RTCVD is in engineering of sub 10 nm MOS gate dielectrics. It has been demonstrated that the annealed-nitrided oxides (ANO) films have superior electrical and diffusion barrier properties to pure oxides [13]. The immunity and electrical integrity of optimized ANO films to hot carriers, after injection of 0.5 C/cm 2 of charge, is shown in Figure 3. 80 A thick oxide films were first grown at 1050oC in dry oxygen. Samples were then nitrided in diluted ammonia ambient and sequentially annealed in oxygen and argon. Hole trapping is observed in pure oxide films, while severe electron trapping is evident in the nitrided oxides. Properly engineered ANO films, however, exhibit excellent immunity against injected charge. Electron trapping behavior of the nitrided oxide films can be correlated to the nitridation conditions. Higher partial pressure of ammonia and nitridation temperature results in larger shifts in the flat band voltage. This is primarily due to higher concentration of nitrogen at the oxide/silicon interface and larger concentration of hydrogen related species in the oxide film [13]. The post nitridation anneal in oxygen

0.30 Q injected

0.25

Pure N143 @ 1050 C

0.5 CICm2

@ 10 ma/Cm2

S0.20 •

0.15

V a•

0.10

0.05 0.00

*

DuN@-V

-00o5 0.10

-0.10

RTO

NO Conditions

ONOA

Figure 3. Hot carrier immunity of optimized ANO structures after injection of 0.5 C/cm 2 of charge at 10 mA/cm 2 . and argon is mandatory to remove the nitrogen and hydrogen species from the bulk of the oxide and silicon/oxide interface. The balance between the sequential oxygen and argon anneal is to minimize the oxide growth at the interface and to remove the electron trap sites.

569

Bipolar Poly-emitter Interface Engemeering The interfacial oxide must be thicker than 10 A to be thermally and chemically stable and, thin enough not block dopant atoms, approximately less than 30 A. Furthermore, for best transistor performance, the interracial oxide must have a near-SiO2 stoichiometry. For this range of oxide thickness, the oxidation kinetics must be greatly reduced. This can be achieved by reducing the oxidation temperature, pressure and by lowering the partial pressure of oxygen. Using SIMS, the oxidation kinetics of ultrathin oxide films expressed as total integrated dose of oxygen is shown in Figure 4. For these samples, upon completion of the oxidation step, polysilicon caps were in-situ deposited.

^17 1

-

-SRI

_~DIdute 0205ti

p_

10}15.

I900E

M/ia

AU JLV

0

5

10

15

2)

(Oxidation time)0.5, SecO5

Figure 4. The oxidation kinetics of ultra-thin interfacial oxide films expressed as total integrated dose of oxygen, using SIMS. Polvsilicon deposition - RTCVD of polysilicon films is considered to be a complementary process for both integrated MOS gate and bipolar polyemitter applications. Polysilicon films in production must have good thickness uniformity, smooth surface morphology, uniform grain size distribution and proper grain orientation. The throughput of a single-wafer system must be comparable to that of a conventional LPCVD tube furnace. This can be accomplished by increasing the deposition rate of polysilicon. The deposition kinetics of polysilicon at 5 torr pressure and 2% SiH4/H2 chemistry is shown in Figure 5. At higher pressures, homogeneous gas

570

phase nucleation may result in severe particle problems. While increasing the temperature will increase film growth rate, it will also produce larger polysilicon grains and rough surface morphology. These effects are undesirable and can be prevented by a two step deposition process. An initial deposition at 5800 to 6300C grows a fine grain nucleating layer while subsequent deposition at 6800 to 7800C completes the stack. At the lower temperatures, the deposition rate is 100 to 200 A/min. It rises to 1000 to 2000 A/nain in the higher temperature 'range. Based on TEM plan view results, the average grain size for the two-step deposited films is approximately 1.5 to 2 times larger than the conventional LPCVD polysilicon films.

SIH4

I

= =

1000==

100

10.8.0

=

.

Ea z1.77V

-

8.S

9.0

9.5

10.0

10.5

11.0

11.5

12.0 12.5 13.0

1/T ( *10,000 ), K-1

Figure 5. The growth kinetics of polysilicon at 5 torr pressure for silane/hydrogen and dichlorosilane/hydrogen chemistries. SUMMARY The applications of single-wafer RTCVD for fabrication of MOS and bipolar devices are discussed. For front-end processing, the MOS gate dielectric engineering and bipolar poly-emitter interface engineering are the most immediate applications. The same reactor technology may be used for gate oxidation and poly-emitter interfacial oxide growth. An integrated, environmentally controlled processing system that incorporates cleaning, oxidation, and RTCVD polysilicon modules would satisfy the processing requirements of both MOS and bipolar technologies.

571

ACKNOWLEDGEMENTS The authors would like to thank Steve Tignor, Xiaolan Wu and Steve Baldwin of Unisys Corporation, Memory and Packaging Operation for their sincere cooperation in providing the bipolar poly-emitter results and helpful discussions. REFERENCES [1]

Ted Kamins, et. al., IEEE Electron Device Letters, 10 (11), pp. 503-505, 1989.

[2]

Nobuhiro Mild et. al, IEEE Transactions on Electron Devices, 37 (1), pp. 107-111, 1990.

[3]

G. P. Burns, Appl. Phys. letter 53 (15), pp. 1423-1425, 1988.

[4]

S. S. Iyer, M. Arienzo and E. de Fresart, Appl. Phys. Lett. 57 (9), pp. 893-894,1990.

[5]

Yasuo Takahashi, H. Ishii and K. Fujinaga, Appl. Phys. Lett. 57 (6), pp. 599-600, 1990.

[6]

M. Offenberg, M. Liehr, G. W. Rubloff and K. Holloway, Appl. Phys. Lett. 57 (12), pp. 1254-1256, 1990.

[7]

S.R. Kasi and M. Liehr, Appl. Phys. Lett. 57 (20), pp. 2095-2097, 1990.

[8]

P. Pan and Ahmad Kermani in Rapid Thermal Annealing/Chemical Vapor Deposition and Integrated Processing, edited by D. Hodul, J. Gelpey, M. Green and T. Siedel (Material Research Society Proceedings 146, Pittsburg, PA 1989) pp. 51-53.

[9]

A. Sakai, T. Tatsumi and T. Niino, Semiconductor Silicon 1990, Proceedings of the Sixth International Symposium on Silicon Materials Science and Technology, Edited by H. R. Huff, K. G. Barraclough and J. Chikawa (Electrochemical Society Pennington, NJ 1990) pp 251-260.

[10]

Paul A. Ronsheim, Brian Cunnigham and Mark D. Dupuis, J. Appl. Phys., f9 (1), pp. 495-497 (1990).

[11]

Manu J. Tejwani, Paul A, Ronsheim and Subodh K. Kulkarni, The 178th Electrochemical Society Meeting, News Briefs, Seattle, WA 1990).

572

[12]

Ahmad Kermani and Fred Wong, Solid State Technology, 42, pp. 4143, 1990.

[13]

Peter J. Wright, Ahmad Kermani and Krishna Saraswat, IEEE Transactions on Electron Devices 37 (8), pp. 1837-1839, 1990.

573

SIMULTANEOUS MEASUREMENT OF WAFER TEMPERATURE AND NATIVE OXIDE THICKNESS USING IN SITU ELLIPSOMETRY Ronald K. Sampson and Hisham Z. Massoud Department of Electrical Engineering, Duke University, Durham, N.C. 27706. ABSTRACT The influence of a native oxide layer on the temperature measurement of a silicon wafer using in situ ellipsometry was investigated. This measurement technique is based on determining the index of refraction of silicon (nisi) using ellipsometry, and then inferring the temperature from the known dependence of fisj on T. It was found that for native oxide thicknesses up to 30A and for wafer temperatures up to 11000C, both the oxide thickness and the wafer temperature could be calculated simultaneously either by iterative numerical routines, graphical methods, or polynomial fits. This process can also be applied for oxide thicknesses larger than native oxides. The use of this technique in the monitoring of temperature and growing oxides is discussed. INTRODUCTION It has been shown that the temperature T of a bare silicon wafer can be measured in situ using ellipsometry to within 3.60C for temperatures up to 11000C using an ellipsometer resolving 0.010 in ¢ and A [1]. This is achieved by measuring the ellipsometric parameters 0 and A, calculating the refractive index of silicon, fisi = n - in, and then determining T from the known temperature dependence of n and n. This process also has been shown to offer several advantages over standard techniques such as optical pyrometry and the use of thermocouples, because measurements using ellipsometry are fast, direct, independent of wafer emissivity and non-contact. As a result, 574

ellipsometry is well suited for temperature measurement in a rapid thermal processing (RTP) environment. However, this technique has been limited in application to filmfree wafer surfaces. This restriction is impractical for most thermal processes, since often the objective is to monitor the temperature in situ during film growth or deposition. As a result, the effect of the presence of a native oxide layer on the measured wafer temperature has been investigated and a resulting algorithm developed that enables simultaneous determination of both temperature and oxide thickness from a single ellipsometry measurement. Furthermore, it has been determined that this algorithm applies for thicker oxides, such that this technique can be applied to monitor both temperature and oxide growth in situ during processing. DEVELOPMENT OF THE MEASUREMENT PROCESS A typical RTP chamber equipped with an rotating analyzer ellipsometer (RAE) for temperature and oxide thickness measurement is used in this study. The chamber consists of a radiative heat source, gas inlets, vacuum chamber and optical ports for the RAE. The components of the RAE include a light source, polarizer, sample, rotating analyzer, monochromator and photomultipher. For this investigation, a helium-neon laser (A0 = 6328A) and an angle of incidence q = 700 were used. The silicon wafer sample is assumed to be optically flat, lightly doped and defect free. The refractive index of the native oxide was set as n,. = 1.46474 + 1.22142e-5.T, where T is in °C [2]. Temperature and Oxide Thickness Dependence of 0 and A The temperature and native oxide thickness dependence of the ellipsometric parameters V)and A was obtained using the following sequence of steps. First, both the real and imaginary components of the refractive index of the silicon substrate as a function of temperature were obtained by fitting polynomials to the data of van der Meulen and Hien [2] in the form M

n =

: ai. T' i=0 575

(1)

and N

bj. Tj,

=

(2)

j=0

where the polynomials were generated using a least squares algorithm [3], and the coefficients a, and bj were tabulated for M = 3 and N = 6 [4]. Second, 0 and A were calculated as functions of nsi, the refractive index of the oxide n.., the angle of incidence 0, and the wavelength A0 . The relationship between these parameters and the ellipsometric parameters 0 and A is transcendental [5], such that 0 and A were calculated for temperatures up to 1100'C and oxide thicknesses up to 30A using McCrackin's ellipsometry program [6]. The resulting curves plotted in Fig. 1 illustrate the dependence of 0 with varying temperature and native oxide thickness, where lines of constant oxide thickness are plotted every 5A. From Fig. 1, L is observed to be monotonically increasing with both increasing Xo, and T for the full ranges of temperatures and oxide thicknesses investigated. Similarly, the curves in Fig. 2 illustrate the dependence of A with varying temperature and oxide thickness. However, A is observed to decrease monotonically with both increasing Xo,, and T. It is these opposite trends that result in the unique determination of both X,,, and T from a single measured set of 0 and A. Determination of T and X,, from 0 and A can now be described as follows: For a given measured set (01, A 1), there is a temperature interval T 1 _ 1200'C); it has also been made ultraclean through the use of oil-free pumps. The wafer can be held in any position from horizontal to vertical. Temperature uniformity is a strong function of this orientation. By removing lamps, the temperature profile can be modified. In this manner, it is possible to achieve better uniformity than in simple flat plate reactors. Thermal models have been developed to simulate the RTP system. These models were used to verify experimental results obtained from rapid thermal oxidation and RTCVD of polysilicon. They also indicate that creative lamp holder and reflector design can lead to optimal uniformity control. ACKNOWLEDGEMENTS The authors would like to thank the following individuals for their assistance: Jim Futrell, John Clarke, and Joselito Sarreal - Microelectronics Center of North Carolina; William Kiether and Chris Beasley - NCSU/ECE; Arthur Illingworth, Jim Emerick, Rick Lamy, Tony Mason, Jeffrey Nifong, Doron Strassman, and Marvin Strickland of the NCSU Engineering Research Instrument Shop. This work has been partially supported by the NSF Engineering Research Centers Program through the Center for Advanced Electronic Materials Processing (Grant # CDR8721 505), the North Carolina SEMATECH Center Of Excellence (Contract # 88-MC-809), and SRC Manufacturing Science Program (Grant # 88-MP-132). REFERENCES IR. Singh, J. Apple. Phys. 63, R59 (1988), and references therein. 2S. Wolf, R.N. Tauber, Silicon Processingfor the VLSI Era, Lattice Press, Sunset Beach California, 1986. 3 F. Roozeboom, N. Parekh, "Rapid thermal processing systems: A review with emphasis on temperature control", J. Vac. Sci. Technol. B8 (6), Nov/Dec '90. 4 Creare.x, Inc., Etna Road, P.O. Box 71, Hanover, NH, 03755. 5 C. Hill, S. Jones, and D. Boys, Proc. NATO ASI series B Vol. 207, "Reduced Thermal Processing for ULSI" p. 143, 1988. 6 F. Y. Sorrell, C. P. Eakes, "Temperature uniformity in RTP furnaces", Rapid Isothermal Processing, Rajendra Singh, Editor, Proc. SPIE 1189, pp. 55-63, 1990. 7S. A. Campbell, K. H. Ahn, K. L. Knutson, B. T. H. Liu, and J. D. Leighton, "Steady State Thermal Uniformity and Gas Flow Patterns in a Rapid Thermal Processing Chamber", IEEE Trans. Semicond. Manufact., vol 4, p. 14, 1991. 8 F. S. Johnson, R. M. Miller, M. C. Oztiirk, J. J. Wortman, "Characterization of LPCVD silicon nitride in a rapid thermal processor", MRS Proc., Vol. 146.

591

DIELECTRIC PLANARIZATION PROCESS FOR ULSI Chiu H. Ting Intel Corporation 3065 Bowers Ave. Santa Clara, Calif. 95052-8126

This paper presents an overview of the recent progress and innovation in the area of dielectric planarization for ULSI. Since there is a tremendous amount of information published recently describing a variety of approaches, only the more commonly practiced approaches will be discussed. For example, recent advances in the AP-TEOS/0

3

deposition process have

demonstrated good gap filling capability for high aspect ratio submicron gaps. Progress in thermally reflowable spin-on polymer could provide significant improvement over the standard resist etchback planarization process. Materials and process improvements have made the non-etchback SOG planarization process possible. The chemical mechanical polishing process has demonstrated superb planarity over a wide range of surface topography and provided the feasibility of global planarization.

INTRODUCTION: As device dimensions are scaled into sub-micron region, the performance of ULSI chips are often limited by inter-connection capabilities. Multi-level metallization is required to provide the interconnection between the millions of devices on a chip. However, the topography generated by the accumulation of multiple deposition and etching cycles is detrimental to high resolution lithography and etching processes. Surface topography is also the cause of many reliability problems such as metal step coverage, electromigration and device integrity issues. Therefore, a planarized dielectric layer is a requirement for high performance multilevel interconnections. There is a tremendous amount of information published on this subject describing different approaches to improve the planarity of dielectric surface for subsequent processing [1], [2]. Recent progress of the more important approaches will be discussed below.

592

DIELECTRIC DEPOSITION: In order to planarize the deposited dielectric layer over severe topography, the deposited dielectric layer must be thicker than the required final film thickness since a significant portion will be removed by the planarizing process. Furthermore, the thick deposited dielectric layer must be free from defects. A common problem is the formation of voids or key holes in gaps with high aspect ratio as illustrated in Fig. 1. The CVD technology used to deposit gap filling dielectric layer was originally based on the oxidation of silane. Silane oxide, however, does not give very conformal coating over topography. The non-conformed silane oxide film often results in the formation of cusps and voids in gaps with aspect ratios of 0.5 or larger. The development of CVD TEOS/oxygen process has greatly improved the conformality of the deposited oxide. However, due to the temperature limitation of aluminum, PE-CVD TEOS/oxygen must be used instead of the high temperature thermal CVD TEOS/oxygen process. The oxide deposited by PE-CVD TEOS/Oxygen process still gives improved conformality over the silane oxide [3]. However its conformality is not ideal, typically less than 75% in small spaces. To improve the step coverage, the LPCVD of thermal TEOS/ozone was developed. Thermal TEOS/ozone film gives nearly 100% conformality and is therefore, capable of filling gaps with nearly vertical profile [4]. The dielectric films deposited by the thermal TEOS/ozone process tend to be rather porous and may absorb a significant amount of moisture [4]. Therefore it is common to use it in the dep/etch process so that the bulk thermal TEOS/ozone film is etched away leaving this film only in the gap filling area [5]. The step coverage capability and the dielectric quality of the TEOS/ozone films can be improved by increasing the deposition pressure. The deposited TEOS/ozone films at or near atmospheric pressure using high ozone concentration tend to be thicker at the inside corners of a gap, thus giving a rounded or "reflowed" profile over a step [6], [7]. This is opposite of the cusp formation over a step in standard CVD dielectric films. Furthermore, these AP-TEOS/ozone or SA-TEOS/ozone films tend to be denser and absorbs less moisture than TEOS/ozone films deposited at low pressure [8], [9]. The step coverage capability of the AP-TEOS/ozone dielectric films for a sub-micron gap with an aspect ratio of approximately 2 is illustrated in Fig. 2. However, AP-TEOS/ozone film deposited with high ozone/TEOS ratio tend to be surface sensitive [6] as well as pattern density sensitive. This would make the step coverage vary with different surfaces and pattern densities, as illustrated in Fig. 3. The capability of the AP-CVD TEOS/ozone deposition process to fill submicron high aspect ratio gaps or re-entrant profiles could provide significant simplifications to the planarization processes for future ULSI structures. However, the deposition mechanism as well as the film quality are not yet well understood. It would require careful study before these AP-TEOS/ozone films can be used with consistent reproducibility.

593

Void Formation

Fig. 1:

Void

Void formation in deposited oxide.

Fig. 2:

Deposited AlP TEOS/ozone film filling submicron gap with an aspect ratio of approximately 2. 594

Fig. 3:

Step coverage of AP-TEOS/ozone film over Al lines with different pattern density. 595

ETCHBACK PLANARIZATION PROCESS:

The resist spin-on and etchback process were developed to provide a low temperature planarization process [10]. This process is based on the planarization capability of photoresist which is coated in liquid form over topography surface by spinning the wafer at high speed. The nearly planar surface of the photoresist is transferred to the underlying dielectric film by using a dry etching process, such as plasma or reactive ion etch process, that etches the photoresist and the dielectric layer at nearly equal rates. The etching process is continued until all the photoresist is removed so that the smooth photoresist surface contour is transferred into the dielectric film. This process has been widely used to planarize dielectric layers over A] metallization. However, the degree of planarization depends not only on the resist coating thickness but also on underlying geometries. Good planarity is obtained only for small closely spaced patterns [11],[12]. The planarity degrades rapidly when the pattern width or gap width exceeds several microns. This problem is reduced by using an additional photolithography step to fill in the large gaps with dummy patterns so only small gap geometries remain before coating the second planarizing photoresist layer [13]. This increases the process complexity due to additional photolithography and design complexity since the dummy pattern must be designed to fit a specific pattern and process [14]. The surface planarity of the spin-on layer can be greatly improved if the spin-on polymer layer is thermal flowing rather than thermal setting such as that of novolac resins used in common photoresists. By using a thermal flowing polymer for the spin-on layer, sufficient planarization can be achieved over geometrics as large as several hundred microns as compared to only a few micron when standard positive photoresist layer is used [16]. This is illustrated in Fig. 4. Since the planarization capability of this new thermal flowing polymer exceeds the largest pattern geometry the dummy photoresist pattern and second planarization photoresist coating may no longer be needed, thus greatly simplifying the etchback planarization process. Final planarity of the dielectric surface is also critically dependent on the etchback process. The commonly used 6ne to one etch rate between the polymer film and the dielectric film, as determined by test wafers, does not provide good planarization due to local loading effect. The local loading effect causes the polymer etch rate to change as more dielectric surface is exposed during the etching process [15]. This must be compensated in order to get good surface planarity. The etchback process using the new thermal flowing resin against SiON dielectric was optimized in a hexode RIE system. An etch ratio of 1.2 to 1 was used planarize the surface topography for both small geometries as well as for large geometries [17]. The results are illustrated in Fig. 5.

596

0

s0

100

200

150

250

FEATURE DIMENSION (urn)

Fig. 4:

of PC2-1500 and Planarity photoresist AZ-1370 after 200"C bake for 2 minutes.

Fig. 5:

SEM cross section to show dielectric surface planarity over 200 um Al pattern after PC2-1500 etchback process 597

SPIN-ON GLASS:

The resist spin-on etchback process can be simplified if the spin-on material can be used either as a stand alone dielectric layer or in conjunction with CVD dielectric films. For this reason, a lot of efforts have been made to study the feasibility of using spin-on polymide film (PI) as the dielectric layer [181. Although PI has good dielectric characteristics as well as good thermal stability, its use as a stand alone dielectric layer for VLSI as not yet been accepted. This is because polyimide is an organic polymer and its properties differ significantly from the CVD oxide films. Many process compatibility issues also need to be resolved before PI can be used to replace CVD dielectric films. A more compatible material could be the spin-on glass (SOG) films [191, [20]. There are many different types of SOG materials such as silicates, doped silicates and a variety of polysiloxanes. They can be coated from liquid to give a spin-on film with good surface planarity. SOG films can be cured at relatively low temperature to give a silicon dioxide like film. However, the film properties depend on the starting material and the curing conditions as well 'as subsequent processing conditions [21]. In general the density of SOG layer is lower than the thermal oxide and it cracks easily for thick layers. It is, usually used in conjunction with other CVD dielectric layers. A partial etchback process is generally used to remove SOG from the via opening areas [22], [23] to avoid excessive moisture absorption in the process SOG films. The moisture content of a typical silicate SOG has been determined by Wolters et.al. [24] by using mass spectroscopy to measure the thermally desorbed gas in a UHV system. The primary contaminant is water as illustrated in Fig. 6. This is because the silicate SOG film cured at low temperature is rather porous and can absorb a large amount of moisture. The porosity of the film can be reduced if the SOG is densified at high temperature (ie. 900°C) which is not acceptable for aluminum. Another way to reduce the porosity is by using siloxane material, which have organic groups such as methyl or phenyl groups built on to the end of silicon-oxygen chain to relieve film stress and to reduce moisture absorption. With proper material choice, the moisture absorption of a siloxane film can be reduced to negligible amount. This is illustrated in Fig. 7, where the amount of thermally desorbed gases from a siloxane SOG film were measured in a UHV chamber [25]. The water content from a properly cured siloxane film as shown in Fig. 7 was found to be negligible and the water content of this SOG film was found to be very low even when the film was subject to Ar sputtering and then soaked in water. The water absorbed was found to be comparable to absorbed Ar gas due to the sputtering process. The integrity of organic containing the siloxane films is destroyed by oxygen plasma, such as those commonly used for organic resist strip. The Siloxane film with organic group partially removed by oxygen plasma is very porous, and it cracks easily and absorbs a large amount of water. Therefore, the oxygen plasma

598

-STE'-nz TharlW S4

I.,

U0

W80 000

000

35a

(o c) -1

600 B20

C02

II ii

..

.

10

I I

f 'I LI

20

o

6

60

0

100

U0

-28TIME(M..,)

Fig. 6:

Partial pressure of absorbed gases from a cured silicate SOG film (ref. 24).

OUTGASSING OF CURED SOG Intensity (arb. units)

a) C) Argon (Alter Sputter)

0

|00

200

b), c)

b)

Water (After Sputter)

a)

Water (Alter Cure)

300

400

Temperature (C) Fig. 7:

Water from as cured film.

Partial pressure of desorbed gases from a cured siloxane SOG film.

599

500

Water and Ar from cured SOG film after subject to Ar sputter etching and then soaked in water.

steps must be either eliminated if the siloxane film is to remain on the wafer surface such as that used in the non-etchback SOG planarization process. Otherwise the siloxane film must be protected from the oxygen plasma by a using dense capping layer over the SOG film. If the siloxane film can not be completely protected from the oxygen plasma, the moisture absorbed in the expose region can be removed by a high temperature baking step (ie. 450'C) immediately before subsequent processing. This is illustrated in Fig. 8 with proper care in the processing sequence, the non-etchback SOG process using siloxane film can give good surface planarity as well as via integrity. This has been demonstrated by high via chain yield, shown in Table I from data obtained by C. Ting et.al. [251 and shown in Fig. 9 from data obtained by R. Wolters et. al. [24]. TABLE 1 Comparison of via chain yield of a non-etchback SOG process using dehyration bake and in-situ Ar sputter clean to control wafer without any planarization process

SOG Wafer

Control Wafer Via Resistance (mo hm/via)

95 +/- 10

79 +- 5

Yield of via chain

78%

100%

Number of total vias

19.44K

19.44K

Number of via chains

18

18

Post-via annealing jn 450 °C, N2

30 min.

30 min.

600

I

a)

Fig. 8:

FTIR measurements of water content in cured siloxane SOG film: a) b)

D3

0.9s

c)

0.95 0.9 0.8 0.7

As cured film Film in (a) after oxygen plasma resist strip. Film in (b) immediately after 30 min. anneal at 450°C in dry N2.

0.5 0.1 0.3 0.2 0.1 0.05 0.01 0

2 String

4 resistance

6

B

>10

[Ohms/section)

Fig. 9:

Via string resistance fabricated With non-etchback siloxane SOG planarization process using in-situ pre-heat prior to sputter etching 601

DEP/ETCH PLANARIZATION PROCESS:

A physical etching process, such as sputter etching has an incident angle dependent etch rate. It generally has a lower etch rate for flat surfaces than sloped surfaces. Therefore, physical etching process can be used to remove sharp corners to give a smoother surface [26]. Using repeated etching and deposition cycles, planarized surface can be obtained over small dimensions. To reduce wafer handling for repeated dep/etch cycles, several equipment manufacturers have developed automated systems that combine etching and CVD deposition processes into a single system. By using different combinations of deposition and etching cycles one can obtain various degree of planarization in the final dielectric layer surface. The well known AMP-5000 system uses plasma TEOS for the main dielectric layer. However, plasma TEOS does not have sufficient step coverage for tight geometries. Therefore, it is used in conjunction with thermal TEOS/0 3 to provide the needed step coverage. Unfortunately thermal TEOS/0 3 has rather poor dielectric properties (i.e. high water content as mentioned previously) so an etchback process is used to remove most of the film leaving only pockets of thermal TEOS/0 3 in the gaps to provide a planarized surface. This dep/etch process used to planarized intermetal dielectric layers as reported by Pennington et.al. [5] is illustrated in Fig. 10. The ultimate deposition and etching process is to create a single process where the deposition and etching processes are carried out simultaneously. This is accomplished in the biased-sputtered quartz or BSQ process [27]. Although the BSQ process has been used extensively, it suffers from low throughput because much of the sputtered deposited film is etched away. This short coming can be improved by using more efficient plasma sources such as the electron cyclotron resonance (ECR) process. In the ECR process, the plasma is generated at microwave frequency in resonance with the electron motion so that dense plasma can be generated even at very low pressure. When compared to the BSQ, the ECR process is capable of higher deposition rate and less radiation damage. It is, therefore, more suitable for planarizing surface topography with high aspect ratios. Similar to the BSQ process, the degree of planarization obtained with biased ECR deposition changes with pattern sizes. This is illustrated in Fig. 11 [28]. CHEMICAL/MECHANICAL POLISHING: Truly global planarization can be obtained by using either mechanical lapping or chemical-mechanical polishing. Lapping is a purely mechanical process. It is difficult to control precisely and it may be too harsh for some applications. Chemical-mechanical polishing is a combination of chemical and mechanical processes [29]. The chemical part of the process can used to optimize process control or to obtain large differential polish rates for different materials [30] [31]. The chemical-mechanical polishing process has demonstrated the capability of providing planar surface over very large dimensions, thus giving the possibility of planarizing the entire wafer surface instead of localized smoothing.

602

THCVD Oxide PECVD Oxiae

Metal

a) Wafer Post tst Metal Patterning

d) THCVD Oxide Deposition

PECVD Oxide

THCVD Oxide

b) Initial PECVD Oxide Deposition

e) Oxide Etchback

PECVO Oxide

c) Argon Sputter

f) Final PECVD Oxide Deposition

Fig. 10:

of a dep/etch Schematic planarization process in AMP-5000 (ref. 5).

with ECR depositea dielectric layer with Dias (ref. 28) )fl

Fr'1. a

603

SUMMARY As device dimensions are scaled into submicron region, multiple layers of interconnection are needed to provide the packing density and operating speed. Planarization techniques are essential to eliminate severe surface topography generated by repeated deposition and etching cycles. Although various planarization techniques for metal layers are being developed, they are focused on contact and via hole fillings. Therefore, the dielectric planarization process must provide over-all surface planarization for the deposition and patterning of next metallization layer. This requires a CVD-dielectric deposition process which is able to fill submicron gap with high aspect ratios. The current deposition/etch process as well as the newly developed AP-TEOS/ozone process are being refined to give this capability. The newly developed spin-on polymer that can be thermally flowed to give long range planarization over severe surface topography that should be able to extend the usefulness of the well established spin-on photoresist and etchback process. By optimizing the SOG materials and processing sequence, a non-etchback SOG planarization process based on thick siloxane layer has been demonstrated. This should simplify the commonly used partial etchback SOG process and extend the usefulness of SOG planarization process into deep submicron. Improved instrumentation such as ECR and improved film property such as SA-CVD or AP-CVD TEOS/ozone film should be able to extend the usefulness of the dep/etch process. The renaissance of the old chemical-mechanical polishing technology gives the possibility of achieving true planarized surface across an entire chip or even across an entire wafer.

REFERENCES

1.

V. Comello, Semiconductor International, p. 60, Nov. (1990).

2.

Proceedings of VLSI-Multilevel Interconnection conf.(1986, 1987, 1988, 1989, & 1990).

3.

B.L. Chin, E.P. VandeVen, Solid State Tech., p.119, April, (1988).

4.

S. Nguyen, et.al., J. Electrochem. Soc., _37. p. 22 0 9 (1990).

5.

S. Pennington, et.al., Proceedings of V-MIC conf. p.335, (1989).

6.

Y. Nishimoto, et.al., Proceedings of V-MIC conf. p. 382, (1989).

7.

K. Fujino, et.al., J. Electrochem. Soc., 138, p.550 (1991).

8.

H. Kotani, et.al., Tech Digest IEDM, p. 66 9 (1989). 604

9.

P. Lee, et.al., Proceedings of V-MIC Conf., p. 396, (1990).

10.

A.C. Adams, C.P. Capio, J. Electrochem. Soc, 128, p. 423 (1981).

11.

R.H. Wilson, P.A. Piacente, J. Electrochem. Soc, 1M3. p. 981, (1986).

12.

LE. Stillwagon, et.al., J. Electrochem. Soc, 134, p.2030, (1987).

13.

DJ. Sheldon, et.al., IEEE Trans. Semicond. Manuf., _1.p.140, (1988).

14.

T.H. Daubenspeck, et.al., J. Electrochem. Soc, 138, p. 506, (1991).

15.

B. Vasques, R. Gardner, Proc. V-MIC, p.384, (1987).

16.

C.H. Ting, et.al., Proc. V-MIC, p. 491, (1989).

17.

P.L Pai, C. H. Ting, ECS Ext. Abst., 89-2, p.3 54 (1989).

18.

LB. Rothman, J. Electrochem. Soc, 127 p. 2216 (1980).

19.

F. Dupuis, et. al.,

20.

C.H. Ting, et.al., ECS Ext. Abst., 3.2, p.352, (1986).

21.

P.L Pai, et. al., J. Electrochem. Soc, 134. p.2829, (1987).

22.

J. Multani, et. al., Proc. V-MIC, p.292, (1986).

23.

D. Yen, G. Rao, Proc. V-MIC, p. 85, (1988).

24.

R. Wolters, et. al., Proc. V-MIC, p. 447 (1990).

25.

C.H. Ting, et.al., Proc. of ECS Multilayer Interconnection Symposium (1988).

26.

C.H. Ting, A.R. Neureuther, Solid State Technology p. 115, (Feb. 1982).

27.

C.Y. Ting, et. al., J. Vac. Sci. Tech. _15,p.1105, (1979).

28.

C. Chien, et. al, ECS Ext. Abst., 89-1, p. 260 (1989).

29.

T. Hamaguchi, et. al, Tech. Digest, IEDM, p. 688, (1985).

30.

IBM Technical Disclosure Bulletin, 29, No. 2, p. 577 (July 1986).

Symp. on VLSI Tech., p.52, (1985).

605

OVERVIEW OF PLANARIZATION BY MECHANICAL

POLISHING OF INTERLEVEL DIELECTRICS Srinivasan Sivaram, Robert Leggett, Alvaro Maury, Kenneth Monnig, and Robert Tolles SEMATECH Inc., 2706 Montopolis Dr., Austin, Tx 78745. ABSTRACT The need for extreme planarity in fine featured devices is presented. Lithographic requirements and the ability of various planarization techniques in meeting these requirements are reviewed. We show that chemical mechanical polishing is needed to obtain global planarity. Concepts behind material removal using a hertzian indentor are extended to the polishing process and the chemistry of glass polishing is presented. We also survey the state of the art in the polishing technology and highlight the areas which need improvement so that the process can be used in volume manufacturing. INTRODUCTION Lithography and etching of finely spaced, fine featured interconnect lines requires that the underlying dielectric be extremely planar. The planarity needs to be both local for stringer free etching and global over an entire stepper field for pattern resolution below 0.5 micron feature size. Whereas local planarity can be achieved by gap filling techniques, extreme planarity requirements on the global scale can be met, among the existing planarization techniques, only by processes involving chemical mechanical polish (CMP) (1). In this paper, we describe the need, the technology, and the limitations of chemical-mechanical polishing as a planarization tool. We review the scientific foundations of the art of glass polishing, as applied to thin films, and establish a framework for further experimentation. We provide an overview of the tools used in achieving the planarity and describe the problems one encounters in developing a stable, manufacturable process. NEED FOR GLOBAL PLANARITY The primary driver for extreme planarity, particularly at the interconnect level, is the desire to use optical lithography at less than 0.5 micron resolution. A key to this capability is the minimization of the exposure field depth. In Table I, depths of focus field of prospective exposure tools are listed. Part of these field depths is consumed by the substrate flatness and the device topology. Without planarization, a nominal 0.8um metallization will not be imaged by tools shown in the shaded region in Table I.

606

Many techniques including oxide reflow, resist etch back, spin-on-glass followed by an etch back, deposition-etch-deposition sequences, and electron cyclotron resonance oxide deposition have been used in semiconductor device processing to achieve planarity (2). The last two of the above mentioned techniques are used in filling narrow spaces with oxides and hence provide void free dielectric films. They are not expected to provide planarity at scales much larger than a micron. Reflow techniques, where thermal budgets allow their use, and techniques that use a low viscosity fluid to level the surface produce a rolling topography with a characteristic length of the order of 10 microns (3). However, CMP makes use of a stiff pad which bridges across topography and can planarize over ranges much greater than any of the above techniques. In comparing planarity, two figures of merit need be defined. The planarization range, R, is a relaxation distance at which the difference in height between the lowest and highest feature after planarization becomes equal to the original step height. The original step height is related to the range, R, by the side wall angle o. Figure 1 illustrates the two definitions. Gap fill techniques are characterized by extreme conformality and hence high side wall angles and low range. Local planarization techniques operate around 10 degree side wall angle and about 10 microns range. Global planarization applies to ranges greater than 1 mm (4). The capabilities of the different planarization techniques are summarized in Figure 2. Each of these techniques finds its application in specific situations. For commonly used step-and-repeat imaging systems, an image field is often about 15mm on a side. Hence, the true lithographic requirement on the planarization process is often defined over such a large distance. If one assumes that the depth of focus requirement was about 0.75 microns over the entire stepper field (from Table I), then it is seen that CMP is the only technique that can satisfy the requirements. OVERVIEW OF GLASS POLISHING Where as the art of polishing glass is ancient and is seen in various walks of life, the science of glass polishing is not well known outside of the very confined field of lens manufacture. An excellent review of glass polishing can be found in Reference 5. Mechanistically, removal rate, dr/dt, of a glass surface during polishing follows the Preston equation (6): dr/dt = Kp (ds/dt)

(1).

where p is the applied pressure, and ds/dt is the relative velocity between the glass surface and the pad. K, the proportionality constant, is termed Preston coefficient. The units of K, area/force, relate it to the mechanical properties of the glass. At the fine

607

polishing situations that are normally encountered in planarization, Preston coefficient is related to the Young's modulus and the hardness of the glass. It is only a weak function of the applied pressure and the relative velocity (7). During a brittle grinding situation macroscopic chunks of material are removed from the glass surface, whereas polishing is characterized by near surface interactions and removal of molecular clusters of material. Near surface interactions during polishing are very strongly influenced by the presence of water. Experimenters have shown that removal rate is negligible when the water in the slurry is replaced by organic solvents (8). The process of polishing is thought to occur according to the sequence described in figure 3: a. Formation of hydrogen bonding between the solvated oxide surface and the solvent in the slurry. The solvated oxide surface pertains to both the surface of the wafer and the surface of the slurry particles. b. Formation of hydrogen bonding between the solvated surfaces on the wafer and on the slurry particles. c. Formation of molecular bonding between the surfaces. d. Removal of the bonded wafer surface as the slurry particle moves away. The net reaction can be described as: =Si-O-Si= + H20 2=Si-OH

(2).

Polishing occurs when the depolymerization reaction proceeds faster than the polymerization reaction. The cleavage of the Si-O-Si below the wafer oxide surface is controlled by the diffusion of water through the oxide. The role of the slurry particle is to impart a chemical "tooth" to the polishing process. The strength of the bond between the slurry particle surface and the wafer surface determines the effective kinetic coefficient of friction between the two surfaces during polishing. Thus the chemical nature of the oxide dispersed in the slurry is crucial to the final oxide removal rate (9). Figure 4 shows the polishing rates for silicon dioxide using different slurry chemistries. Plotted on the x-axis is a measure of the single bond strength, normalized to the isoelectric pH (IEP) of the oxide. It is seen that cerium oxide results in the highest removal rate, followed by Zr and Ti oxides. However, for the planarization process, the choice of the slurry chemistry must be made not only based on the removal rate, but also on the planarity obtained, and the ability to distribute the particles effectively in a stable colloidal distribution.

608

TECHNOLOGY OF POLISHING A cross sectional view of a wafer with interconnect structures undergoing polishing is depicted in Figure 5. The wafer is pressed against a polishing pad saturated with an abrasive slurry solution. The polishing pad and the wafer surface are actively rotated against each other. This process preferentially polishes protruding topography. The key to the global planarization capability is that the polishing pad be sufficiently stiff to bridge the die level topography (10). The overall polishing interface, however, needs to conform to the net wafer contour to obtain die to die polishing uniformity. The chemistry of the polishing process was discussed in an earlier section. The most popular slurry used for dielectric polishing consists of colloidal silica in an aqueous KOH solution (11,12). The silica particles are flame produced and extremely uniform in size at a few hundred angstroms. Polishing pads most often used are either polyurethane impregnated Dacron felts or cast, filled polyurethane (13). Typical polishing machinery needs to actively control the down force, pad and wafer rotation rates, slurry feed rate, and polish temperature. In general, the commercially available tools tend to polish one or two wafers simultaneously (14). Typical dielectric polishing tools do not offer the process control needed for large batch processing. Status of the polishing process: Achievement of planarity with the polishing process is relatively simple. However, obtaining simultaneously, stable, high removal rates and uniformity across the wafer is more challenging. Removal rate falls off with age of the pad, causing process control problems. Table II summarizes the effects of various polishing parameters on some of the output parameters including removal rate, slope in removal rate, uniformity within wafer, planarity, and particles left behind on the wafer. It should be noted that these are general trends and the importance of the influence of each parameter is dependent on the specific conditions of the polish. i. Rate drop off: Figure 6 shows a typical polish rate curve as a function of the life of the pad. The removal rate continuously drops off after some initial instability. This drop off with pad life is due to plastic deformation of the pad surface and the resultant glazing. Pad glazing appears to result in two phenomena: a. the net area of contact between the pad and the wafer increases and hence the effective polishing pressure drops, b. the channels available for slurry transport to the interior of the wafer are blocked. Both of these result in rate reduction. However, it is hypothesized that the latter is a stronger phenomenon. Various means have been used in correcting for the drop off during device processing. Increasing polishing pressure has other negatives including loss of planarity

609

and higher drop off slope. "Pad conditioning" is considered the most likely solution to this problem. The conditioning process consists of some method of dressing the pad often through an abrasive process, so that the removal rate is raised back to its original higher level. Most of the work in the pad conditioning area is still in the developmental stage (15).

ii. Pattern sensitivity in removal rate: It has also been observed that an isolated small elevated feature on an otherwise flat topography polishes much faster than a dense array of elevated features. Large high areas polish the slowest. Hence, differing densities of features within a die can result in degraded planarity due to different removal rates (4). Such a pattern sensitivity in polishing degrades within-die uniformity and if uncontrolled might expose underlying layers in one portion of the wafer while leaving large under-polished regions in other parts. Figure 7 shows the amount of oxide removed on top of varying line widths in a test pattern. It is clear that wider the line, the slower the polishing rate over it. Localized polishing pressure variations and the above mentioned slurry distribution problems lead to pattern sensitivity of removal. The general guidelines in using CMP for ILD planarization are: a. isolated elevated features polish very fast and should be avoided, if exposed underlying layers are a concern; b. large spaces of the order of 500 microns do not cause problems for polishing (3), c. isolated lines will show enhanced removal close to the edges, and d. large elevated featureless plateaux will show removal rate inversely varying as their areas. iii. Other manufacturability concerns: a. Within wafer removal rate variations: Within wafer uniformity is thought to be dictated by two major factors during CMP: a. Slurry access as a function of distance from the wafer edge, which often results in bull's eye type patterns, and b. distribution of pressure through the wafer holding mechanism. Since polishing pad aging results in poor slurry distribution, it follows that uniformity degrades with increasing pad life. Slurry access problems are often counteracted by increasing or decreasing the relative velocity between the pad and the wafer, as a function of wafer radius. Proper adjustments of the two speeds can be effective in arriving at an acceptable removal rate uniformity (16). b. Post-polishing cleans: Most of the polyurethane and slurry debris left on the wafer after polishing can

610

be removed by rinsing in water. However, since particle requirements in VLSI processing are stringent, cleaning processes are more elaborate. Particle levels on the wafer tend to stabilize at a lower value as the pad ages, as shown in Figure 8. In this

case, the top surface of the oxide has been etched away using a dilute HF solution, and spray cleaned in deionized water. In order to get very low levels of particles, scrubbing using felt brushes, ultrasonic cleans, and polishing with water (but no slurry) on a different pad have been suggested. The choice would depend on individual requirements and compatibility to the oxide type. c. Measurement of extreme planarity: Since CMP produces side wall angles much smaller than a degree, measurement of planarity is not feasible using the commonly used techniques such as scanning electron microscopy. Many novel methods have been attempted, including interferometry, measurement of phase lag (16), and electrical techniques. Of these techniques, profilometry, and oxide thickness measurements are the two that have become popular due to ease of use and the availability of commercial equipment. CONCLUSIONS In this work, we have reviewed the current status of chemical-mechanical polish for achieving planarity of interlevel dielectrics. The need for the extreme planarity that can be achieved with CMP was illustrated. We presented concepts from the science of glass polishing that can be applied to the technology of CMP for planarization. It is clear from the status of the technology, that there is significant amount of developmental effort still needed before CMP can become a mainstream processing tool. Many manufacturability issues .still need to be addressed, including process stability, and metrology. However, the technology offers unique capabilities not matched by any other planarization method.

ACKNOWLEDGMlENTS The authors would like to express their appreciation for the excellent discussions that they had with Lee Cook of Galileo Optics and Norm Brown of Lawrence Livermore Laboratories. REFERENCES 1. B. Davari, et. al., Technical digest, IEEE-IEDM, 1989. 2. V. Comello, Semiconductor International, 13 (1990), p60. 3. M.E. Thomas, S. Sekigahama, P. Renteln, and J.M. Pierce, Proc. of IEEE-VMIC, 611

1990, p438. 4. T.H. Daubenspeck, J.K. DeBrosse, C.W. Koburger, M. Armacost, and J.R. abernathy, J. electrochem. Soc, 138 (1991), p506. 5. L.M. Cook, J. Non-crystalline Sol., 120 (1990) p152. 6. F. Preston, J. Soc. Glass Tech., 11 (1927), p 2 14 . 7. N. Brown, document MISC4476 (Lawrence Livermore Laboratory, CA, 1987). 8. T. Izumitani in "Treatise on Materials science and technology, Vol 17", Ed. by M. Tomazawa and R.H. Doremus, Academic Press (1979), p115. 9. W. Silvernail, Paper WBI-1, Techn. Digest, Topical meeting on Optical fabrication and technology, Optical Society of America, 1982. 10. P. Renteln, M.E. Thomas, and J.M. Pierce, Proc. of IEEE-VMIC, 1990, p57. 11. Rodel Inc., Rodel Surfacetech Review, Vol 1, Issue 7, 1989: 9495 East San Salvador Dr., Scottsdale, Az 85258. 12. Cabot corporation, Cab-O-Sil Division, PO Box 188, Tuscola, 11. 61953. 13. Rodel Inc., Rodel Surfacetech review, Vol 1, Issue 1, Dec 1986. 14. Westech Systems Inc., 3502 East Atlanta Ave, Phoenix, Ar. 85040. 15. Private communication, Westech systems. 16. J.J. Colacino and T.A. Bartush, Sol. State Technol, Aug 1973, p 30. 17. E. L. Church, and P.Z. Takacs, Optical Engineering, 24 (1985), 296; Wyco Corp, 1955 E. Sixth St., Tucson, Az 85719.

R

Resolution Wavelength .370

.240

S190

.8

1 .5

1 .3

DEPTH of FOCUS 2.2 0.7 .24

2.7 3.4

1.1 1.3

Plaonrizotion Reloyotion Distance. R The distance R traveled over 0 step whereupon the original step height topogrophy, or depth of field,

.38 .47

T, returns

R = T ctnl Set T= .8u, R=.8 ctn, 0 Sidewall Angle

Figure 1: Metrics of planarization

612

POLiIt4ING 8203 RESIST& ES

S....

SOG &/or E8

m -4-

REFLOW

lIi !ii

oDP/ETCH [CR

R

0

0.1

10

10

100

0.1

3'10

45

GAP FILL

I

a low0

LOCAL

10000 .03

GLOBAL

Figure 2: Comparison of planarization processes

H 0

/

2H

Ic1

7

(bJ

H

H

1s8

Wafer surface

Figure 3. Sequence of chemical reactions during polishing

613

Effect of slurry chemistry on polishing

0.3

0.4

0.5 0.6 0.7 0.8 RG-1/[Ioglisngle bond strnth-ab9(7-IEP)]

0.9

Figure 4. Polishing rate vs slurry type

Figure 5: Cross sectional view of a wafer undergoing polishing

614

Tam

11 RESULTS IN

INCREASE IN RATE

SLOPE

WIW

PLNR

I. PRESSURE

D

I

D

NC

2. REL. VEL

D

D

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NC

3. TEMP

0

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ND

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4. PAD AGE

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LEGEND I D NC ND

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a

b

720

a

700

W

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100

150

200

polishing minute-

230

300

350

(5 mnwfr

Figure 6: Removal rate drop off with pad life

615

a £ * 0 V

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0000

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Figure 7: Line-width dependence of removal rate

00

ec P..

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Wafe.r no.02.,

FIgure 8: Post-clean particle levels on a polished wafer Particles shown are larger than 0.5 microns

616

ADVANCED DIELECTRIC TECHNIQUES FOR THE FABRICATION

OF 16 MEGABIT DRAM GENERATION DEVICES B. Ahlburn Texas Instruments - DMOS IV, 13353 Floyd Rd. Dallas, TX 72265 R. Nowak, M. Galiano, and J. Olsen Applied Materials, 3050 Bowers Av. Santa Clara, CA 95054

Submicron gap filling and dielectric planarization schemes are applied to a 16 Megabit DRAM device. PECVD and SACVD TEOS oxide films are used for void free filling of gaps as small as 0.5 um at metal 1 and metal 2 levels. Thin layers of PECVD TEOS oxide are found to be important for reduction of nucleation sensitivity, loading effects, and moisture intake of the 0 3 -TEOS SACVD films. The sacrificial B 2 0 3 planarization scheme is used over metal-1 providing long range surface planarity. Electrical testing of completed 16 Megabit DRAMs indicates that these materials and processes meet or exceed requirements for the 16 Megabit device.

INTRODUCTION The requirements for the inter-metal isolation films used in the 16 Megabit generation devices exceed the capabilities of traditional films and fabrication techniques. The need for void-free gap filling of spaces as small as 0.5 pm at both metal-1 and metal-2 levels and for a high degree of dielectric planarity prior to metal-2 deposition make the multi-step conventional SOG [1] and depositionetchback [2, 3] schemes lengthy and unreliable. The degree of planarity using a single SOG coating and etchback is insufficient for certain topographies as illustrated in Figure 1. Reliability problems related to the use of the SOG are due to cracking, moisture absorption, outgassing, and limited planarity. For example, problems with nucleation of tungsten film in the vias may occur if the SOG film is not removed from the via vicinity in the etchback step. Stringent gap filling requirements have emerged for the passivation layers; metal-2 lines must be isolated by a low dielectric constant material which provides protection from rupture or displacement induced by the LOC packaging process. Consequently, metal-2 void-free gap filling and smoothing of the top chip surface are very desirable. Typical passivation films do not meet these requirements (see Figure 2). 617

In this paper we focus on practical applications of the Sub-Atmospheric (600 Torr) CVD TEOS-0 3 (SA-TEOS) oxide deposition process and the B2 0 3 planarization scheme to 16 Megabit DRAM. The use on device of the SA-TEOS oxide film, which has exceptional gap filling properties [4], is discussed. The B2 0 3 planarization process [5,6] is used to provide very long range planarization of the intermetal dielectric.

Figure 1. Insufficient of

the

planarization dielectric

over

metal-1 iti the guard-band area,

using

single-coat

SOG-etchback process.

Figure 2. "Keyhole" voids in a conventional dual-layer deposited

passivation over

metal-2.

film The

PECVD oxide and nitride films are deposited using the conventional SiH 4 -based chemistries.

618

FILLING OF SUBMICRON GAPS BY OXIDE DEPOSITION The SA-TEOS oxide film deposited at 600 Torr was used for filling of the submicron spaces. Void-free gap filling was obtained for a 0.5/arm wide 1.0/jm deep trench with vertical sidewalls. Similarly, void-free gap filling was demonstrated over 0.8 Yim high tungsten leads (metal-i) for spaces as small as 0.65 'Um. This was achieved despite the relatively large grain of the tungsten which resulted in irregular and sometimes re-entrant metal profiles. Figure 3 shows the result of sequential deposition of the PECVD TEOS (PETEOS) oxide layer followed by the SACVD film over metal-2 leads. Various thicknesses of the initial PECVD film (2000 A - 4000 A) were used to minimize the SACVD film thickness and to test its gap filling ability. The SACVD film had no problem with filling 0.5 jm gaps left after 4000 A PECVD deposition. Figure 3 also illustrates self-smoothing of the underlying topography which occurs in wider gaps resulting in a positive gap profile. This thickness dependent smoothing ability of the SA-TEOS oxide enables one to avoid forbidden gaps formation. Consequently, the profile after deposition of at least 4000 A of the SA-TEOS film is relatively easy to fill by either oxide or nitride PECVD films.

Figure 3. Dual-layer

passivation

(oxide-

nitride) of metal-2. "Keyholes" and "forbidden gaps" have been avoided as a result of the positively tapered profile of the SA-TEOS oxide film. The complete passivation structure consists of PE-TEOS oxide (4000 A) followed by SA-TEOS oxide (4000 A) followed by PE-CVD

nitride (1 um). 619

PROCESS INTEGRATION Loading effects and surface sensitivity It was found that the SA-TEOS oxide film thickness depends on the type of the underlying material and on the density of the underlying interconnect pattern. This is illustrated in Figures 4 (a) and (b), which show the difference in oxide thickness between areas of the wafer having different metal pattern density. The large surface area of the rough tungsten metal aggravates this effect. The surface and pattern sensitivity were found to depend on the 0 3 /TEOS ratio in the SACVD process, with high ratios producing the most surface/pattern sensitivity. A thin in-situ nucleation layer of the PE-TEOS oxide was found to be a solution to the loading effect (Figures 4 (c) and (d)). Identical film thickness is obtained for both pattern densities using this deposition method. The efficiency of the gap filling by the SA-TEOS oxide also increased. The SA-TEOS sidewall coverage in the gaps was found to be higher than 100% and resulted in complete filling of 1.0,pm spaces using films as thin as 0.45,pm. This minimizes the amount of the SA-TEOS needed to fill gaps. Like the atmospheric pressure 0 3 -TEOS process [7,8], the deposition rates of the SA-TEOS oxide vary from one type of substrate material to the next; the 2000 A&min-1 deposition rate observed on bare silicon substrates is reduced to ca. 1650 A min"1 on PE-TEOS oxide coated substrates. Furthurmore, the rate remains constant at 1650 A min-' throughout the entire deposition process, even after the initial nucleation of the SA-TEOS oxide. This phenomenon of substrate dependency is not well understood. However, it was found [9] that the proper treatment of the PECVD oxide surface or the use of the nucleation layer prior to SA-TEOS deposition eliminates the dependence of the deposition rate on the substrate type. Prevention of moisture absorption Like all porous SiO 2 films [10,11], SA-TEOS oxide films absorb water vapor from ambient air. This results in stress instability (Figure 5) as well as other deleterious effects. Water absorption can be mitigated by employing in-situ deposition of thin PE-TEOS oxide layer onto the SACVD oxide film. Figure 6 illustrates the effectiveness of the PE-TEOS oxide layer in protecting the underlying SA-TEOS oxide from moisture absorption during exposure to ambient water vapor. Curve (a) in Figure 6 reveals the quantity of water absorbed by the unprotected SATEOS oxide during extended exposure to air. Curve (b) indicates that the in-situ "cap" of PE-TEOS oxide produces a composite film which is substantially drier, even after the same exposure to ambient air. The SOG film contains an amount of moisture which is intermediate between the two CVD films (a) and (b). Thus, incorporation of moisture into the device can be minimized provided that the SATEOS film is capped. In the event of the exposure of the SA-TEOS film to ambient 620

Figure 4. Deposition rate of SA-TEOS oxide is a function of the underlying material type as well as the

density of the underlying interconnect pattern, giving rise to substantial differences in film thickness from one area of a die to another ((a) and (b)). If the metal pattern is coated with PE-TEOS oxide prior to SA-TEOS oxide deposition, this effect is diminished ((c) and (d)).

SA-TEOS oxide deposited directly onto metal-1 interconnects: a) Area with dense metal pattern

b) Area with less-dense metal pattern

SA-TEOS oxide preceeded by 1500Min-situ deposition of PE-TEOS oxide onto metal-1 interconnects: c) Area with dense metal pattern

d) Area with less-dense metal pattern

621

air, a short bake prior to the subsequent PE-TEOS deposition can drive the moisture out. Using these methods, no degradation of device performance was observed on our 16 Megabit devices. Mn

30I

250-

200

2

4 FILM

6 AGE

a

10

12

(hr.)

Figure 5 (above). Film stress in SA-TEOS oxide films during the first twelve hours of exposure to ambient air after deposition.

WEM Tit (kit) Figure 6 (above right). 0 Water effusion from oxide films during 450 C anneal. All have been exposed to ambient air for several days prior to annealing. Films (a) and (b) are SA-TEOS oxides (4000 A). Film (a) is unprotected. Film (b) is protected by a 1000 A layer of PE-TEOS oxide which was deposited in-situ after the SA-TEOS deposition. Film (c) is a baked and cured SOG 0

311P. The anneal cycle was a 2 minute ramp from room temp to 300 C, a four minute 0

0

hold at 3001C, a two minute ramp to 450 C, and a four minute hold at 450 C. Water effusion was measured using a duPont model 903H Moisture Evolution Analyzer.

DIELECTRIC PLANARIZATION Planarization of the oxide over metal-1 using a single SOG coating and etchback is marginal for the 16 Megabit device, which requires medium-to-long range dielectric planarity beneath metal-2. We have used the B2 0 3 planarization process [5,6] as an alternative to the SOG-etchback scheme. A comparison of results is shown in Figure 7. In the SOG case the degree of planarity is limited by the SOG thickness (3000 A) and selectivity of the etchback step. In the B2 0 3 scheme, planarity is limited by the boron oxide film thickness (1.3 um in this case). Very long range planarization was obtained using a single in-situ B2 0 3 deposition and etchback. In fact, considerable difficulty was encountered when aligning the metal-2 pattern, due to the planarity of the oxide surface. 622

C

en~ 0 4) C

C

.0

C.

4)

-o C)

.0 L~0

bb Uo

4) C C C

I 623

N 4)

C-

"

C

G,

DEVICE PERFORMANCE Table I summarizes electrical performance of completed 16 Megabit DRAMs built using three different intermetal dielectric schemes. The "Baseline" process is similar to most single-spin SOG-etchback planarization schemes: it uses PE-TEOS oxides and a partial SOG etchback such that SOG remains in the gaps between adjacent metal lines and on the tops of large features. Scheme "1' follows the same flow as the "Baseline", except that the first PE-TEOS layer is replaced with in-situ deposition of a thin PE-TEOS nucleation layer, SA-TEOS oxide, and a PE-TEOS cap layer. Just prior to SOG coating, the PE-TEOS protective cap is removed; then the baseline process flow is resumed. Once completed, the SA-TEOS oxide remains in the gaps between adjacent metal lines as well as on all horizontal surfaces, and SOG remains only in the largest gaps and atop large features. Scheme "2" does not use SOG. Gap filling is achieved using a thin PE-TEOS nucleation layer followed by SA-TEOS oxide, followed in turn by a blanket reactive ion etchback which removes most of the SA-TEOS oxide from the horizontal surfaces and leaves most of it in the gaps. Planarization is achieved using in-situ deposition and flow of sacrificial B2 0 3 , which is removed entirely during the following etchback step. The entire sequence of process steps is performed under vacuum. Leakage currents are generally lower through and across the dielectrics produced using schemes "1"and "2", compared with the "Baseline" case. Via integrity was comparable in all three cases. Transistor characteristics - including sensitive metal gate thick field transistors - were unaffected by the alternative schemes. This indicates that so long as proper precautions are taken when integrating these alternative materials and processes into the device flow, device performance is not degraded and may even be improved. The metal-1 integrity results confirm that the 03 used in the SACVD processes does not harm the underlying tungsten metal-1 material. It is noteworthy that in schemes "1" and "2", tungsten metal-2 is deposited into vias in which substantial amounts of SA-TEOS oxide are exposed on the sidewalls. Good via resistances are achieved nonetheless. When SOG materials are exposed on the via sidewalls, however, tungsten deposition fails due to poor local nucleation in these areas. Two Protective Overcoat (Final Passivation) schemes were used on these devices. The baseline scheme is illustrated in Figure 2; the alternative is shown in Figure 3. The alternative scheme is designed to provide a smooth, positively tapered surface profile onto which the PECVD nitride can be deposited, and at the same time to prevent the PECVD nitride from reaching the gaps between closely spaced metal-2 lines. No shifts or degradations were found when comparing electrical test parameters between the two schemes. 624

TABLE I. 16 MBit DRAM Electrical Test Parameters

INTERMETAL DIELECTRIC SCHEME

TEST PARAMETER

Baseline

1

2

BULK LEAKAGE:

mean(sigma)

mean(sigma)

mean(sigma)

-

M1 Block-to-M2 Block (pA)

14.3(3.6)

2.6(0.9)

4.4(5.2)

-

M1 Une-to-M2 Block (pA)

12.6(3.2)

9.2(0.4)

9.0(0.0)

129(114)

63(14)

38(8)

109(119)

33(16)

20(11)

2515(0)

1307(2)

763(0)

- single via (ohm)

0.61(.12)

0.61 (.08)

0.49(.04)

- via string (ohm)

2.87(.11)

2.91(.16)

2.79(.11)

0.20(.01)

0.19(.01)

0.20(.01)

0.26(.04)

0.28(.04)

0.28(.04)

SURFACE LEAKAGE: Between Interdigitated M2 Leads (pA) - Between Interdigitated M2 Leads with Lateral tabs (pA) -

- Between M2 Leads

Lying over a Passive Array (pA) VIA RESISTANCE (0.6 urn vias)

METAL-1 INTEGRITY: - Pad structure -

sheet resistance (ohm/sq) Serpentine structure sheet resistance (ohm/sq)

In the "Baseline" intermetal dielectric scheme, PE-TEOS oxide and SOG are used for gap filing; SOG is the planarizing agent. In the alternative scheme "1", PE-TEOS and SA-TEOS oxides are used for gap filling; SOG is the planarizing agent. In alternative scheme "2", PE-TEOS and SATEOS oxides are used for gap fIlling; boron oxide is used as a sacrificial planarizing agent. "MW"and "M2" refer to metal-1 and metal-2, respectively.

625

CONCLUSIONS Two new films and processes were used to build 16 Megabit DRAM devices, specifically: the PECVD-SACVD TEOS oxide sandwich film and the sacrificial B2 0 3 planarization. The SACVD TEOS film was used as a part of the dielectric insulation for both intermetal dielectric and protective overcoat. The results were compared to the conventional SOG-etchback process. Extensive electrical tests performed on 16 Megabit DRAMs indicated no degradation of any of the measured parameters as compared to the parent lot. Furthermore, some parameters improved. REFERENCES C. Chiang and D.B. Fraser, Proceedings of the VMIC Conference, Santa Clara 1989, p. 39 7 . [2] S. Pennington, S. Luce, and D. Hallock, Proceedings of the VMIC Conference, Santa Clara 1989, p.3 55 . [3] J.M. Perchard, H.E. Smith, R. O'Connor, J.C. Olsen, and K. Law, SPIE Proceedings, 1188, 75 (1989). [4] P. Lee, M. Galiano, P. Keswick, J. Wong, B. Shin, and D. Wang, Proceedings of the VMIC Conference, Santa Clara 1990, p. 18 7 . [5] J. Marks, K. Law, and D. Wang, Proceedings of the VMIC Conference, Santa Clara 1989, p. 89 . [6] J. Marks, K. Law, and D. Wang, SPIE Proceedings, 1188, 69 (1989). [7] K. Fujino, Y. Nishimoto, N. Tokumasu, and K. Maeda, Proceedings of the VMIC Conference, Santa Clara 1990, p.187. [8] K. Fujino, Y. Nishimoto, N. Tokumasu, and K. Maeda, J. Electrochem. Soc., 137, 2883 (1990). [9] P. Lee and R. Robertson, unpublished results. [10] M. Shimbo and T. Matsuo, J. Electrochem. Soc., 130, 135 (1983). [11] N. Nagasima, H. Suzuki, K. Tanaka, and S. Nishida, J. Electrochem.°Soc., 121, 434 (1974). [1]

626

EXCIMER LASER ASSISTED PLANARIZATION FOR ULSI METALLIZATION G.S. Sandhu, C. Yu, and T.T. Doan Micron Technology, Inc., 2805 East Columbia Road, Boise, ID 83706 Laser planarization is a promising technology for ULSI metallization because of its ability to fill high aspect ratio, submicron contact/vias. We have performed a comprehensive study on the effect of metal layer thickness, contact geometry, barrier layers and sputtering conditions on the process window for laser planarization. We used a XeCI excimer laser to planarize AISiCu thin films of thickness ranging from 0.5 gm to 1 Vm on a topography substrate, and to fill both micron and submicron sized contacts of aspect ratios ranging from 1 to 2. Under optimized process conditions, we achieved process windows as large as 20-30% which is significantly larger than the previously reported values (8% or less), and is adequate for this technology to be used in a manufacturing environment. Full electrical evaluations including leakage current, breakdown voltage, metal continuity/shorts, contact resistance, and I-V characteristics of the laser processed devices did not show any deleterious effects of exposure to laser energy.

INTRODUCTION Laser planarization is one of the most promising planar technologies for filling high aspect ratio, submicron contact/vias required for ULSI metallization (1-4). Laser planarization relies on a very short laser pulse to rapidly melt a metal layer. The mass transport of the metal during the molten period results in a planarized metal surface due to the high surface tension and low viscosity of molten metals. Laser planarization has the advantage of being a low thermal budget and effective technique for contact/via filling and surface planarization. Full integration of this technology into manufacturing process flow however, requires the technique to have a sufficiently large process window where, the process window is defined as the difference between minimum laser fluence required to achieve complete filling of the contacts and the maximum fluence before the onset of optical ablation. The flow of metal into a contact/via during laser planarization is governed by the surface tension and viscosity of the metal in its molten state. In addition, the 'resistance' to the flow of metal depends on the interactions at the metal/substrate interface as well as substrate topography. We have performed a comprehensive study on the effect of metal layer thickness, contact geometry, barrier layers and sputtering conditions on the process window for laser planarization. In order to preserve the junction integrity, a barrier metal scheme specific to the laser planarization process has been developed.

627

EXPERIMENTAL A XeCl excimer laser of energy - 500 mJ/pulse was used to planarize AlSiCu thin films of thickness ranging from 0.5 gim to 1 gim on topography substrates, and to fill both micron and submicron contacts of aspect ratios from 1.0 to 2.0. All the test structures were fabricated on 150 mm diameter p-type Si wafers deposited with BPSG and patterned by standard lithography and etch processes. The diffusion barrier and interconnect layer were deposited sequentially in a multi-module DC magnetron sputtering system without breaking the vacuum. For barrier layers, 500 A reactive TiN/500 A Ti were used in this study. The contact/via step coverage before and after laser planarizatio-n was examined by cross-sectional SEM. In addition, various film properties including surface morphology, Ar incorporation, barrier layer and Al alloy inter-diffusion before and after laser processing were investigated by SEM, AES, SIMS, and RBS. Electrical characterizations were carried out on laser planarized DRAM device wafers.

RESULT AND DISCUSSIONS Contact filling/planarization The SEM micrographs of contact vias before and after laser planarization are shown in Figure 1. The laser planarized devices showed completely filled contact/vias. For a given substrate topography, both the minimum laser fluence required to planarize the surface (Fp) and the maximum fluence before the onset of optical ablation (Fa) are lowered with the decrease in metal film thickness[5]. The influence of metal thickness

1 gm = 1 inch (a) (b) Fig. 1 SEM cross-sections of via (a) before and, (b) after laser planarization. 628

l•,q,,/

]0 80

800 nm

E3 600 nm A 500 nm

~60 S40 '-

0

20 as-deposited u

2.5

..

3.0

3.5 Optical

4.0 fluence

4.5

5.0

(J/cm2)

Fig. 2 Contact filling versus laser fluence for AlSiCu films at various thicknesses for contacts 0.9 by 1.4 gmn. on the effectiveness of via filling is shown in figure 2. For a similar contact/via geometry, better contact filling can be achieved at a much lower laser fluence for thinner films. For a given optical fluence, thinner films, because of their lower heat capacity, are heated to higher temperatures giving rise to a longer molten time, which therefore results in better contact filling. However, below certain metal thickness, this advantage is counter balanced by depletion of the metal around contacts during flow giving rise to partially filled contacts. In order to determine the effect of contact/via geometry on the contact filling process, contact filling percentage was determined for both sloped and vertical contacts of various diameters and aspect ratios. Figure 3 shows that for a given contact depth, a smaller diameter contact hole (higher aspect ratio) requires a higher laser fluence for complete filling. For smaller diameters, the surface tension forces act to close off the top of the via. Additional laser energy is therefore required to completely fill the vias[5]. Figure 4 shows contact filling for 1:1.6 aspect ratio contacts with several different as-deposited metal step coverages. In general, the contact filling is significantly greater with improved as-deposited metal step coverage and profile obtained at higher sputtering temperatures and sputtering with bias voltages. For certain sputtering conditions, the as-deposited metal film bridged the top of the contact hole. This resulted in better contact flow and protected the junction integrity since the junction did not get

629

120

Aspect ratio 100-

80C)

600

40-

on

I

3 Optical

4 Fluence

5

(J/cm2)

Fig. 3 Contact filling versus laser fluence for various contact aspect ratios. Contacts with smaller aspect ratios were completely filled at lower fluence. 120

100

80

60 Cu

40 0

U) 20

0

0

1

2 3 4 Optical Fluence (J/cm2)

5

Fig. 4 Effect of initial step coverage on the efficiency of contact filling during laser planarization. Better starting step coverage leads to a larger process window. 630

exposed to the incident laser beam during planarization. defined by the expression; Process Window

=

Clearly, the process window, as

Fa - Ff Fa + Ff

where, Ff is the minimum optical fluence required for complete filling and Fa is the optical fluence at the onset of optical ablation, is significantly widened by improving the initial step coverage. Under optimized process conditions, we have achieved process windows as large as 20-30% for lx1 gim contacts, which is significantly larger than the previously reported values (8% or less)[6]. The nature of the interface between Al and barrier layer has strong consequences on the flow of Al during laser reflow. The wetting properties of the layer being reflowed on the barrier layer can influence the degree of contact filling significantly. We were able to obtain better filling when Ti was in contact with Al at the bottom compared to TiN. In addition, it was observed that exposing TiN to air before Al deposition resulted in ablation at lower optical fluence. Figure 5 shows the optical micrograph of Al films after exposure to a laser pulse. The lasing conditions were selected so as to be close to the onset of optical ablation limit. Clearly, the magnitude of ablation increased significantly when the wafers coated with TiN were exposed to ambient before the deposition of Al film. Large amounts of ablation could result from gas adatoms trapped at the interface of Al and TiN films. These pockets of gas presumably expand rapidly during lasing and cause ablation.

(a)

(b)

Fig. 5 Optical micrograph of the Al films after laser planarization for (a) in-situ deposition (b) after exposing TiN to ambient for 2 hours before depositing Al. 631

and reliability

Electrical measurements

characterization

The laser processed devices were tested for electrical reliability under extreme As shown in figure 6, the laser processed wafers showed 26x environment. improvement in wafer level electromigration lifetime. The enhanced reliability results from better contact filling as well as change in the grain size of the Al films after laser planarization. It is known that a larger grain size of Al films in general leads to better electromigration lifetime.

70

~

e--

6

In 50 m- I I30

'_

""

FS50

T

jI

10

T

- L'S

.1-

/I--

ý

;I

I

,

1/6

,

I

ii1 H I 1

t4

I I Tll

i I 7-1F'

ri

1

E

z• SI.0

rli

LI

1".$1

-2

INeC.

Time (sec)

Fig. 6 Cumulative % failures versus time for a current density of 1.1x10 for a wafer level EM test. The AlSiCu films were 1 gIm in thickness.

7

amps/cm

2

There are several possible mechanisms which can contribute to the deterioration of the device characteristics after laser planarization. These include the breakdown of barrier layer between molten Al and Si which can result in Al spiking into the junction. In addition, the thermal shock received by the devices can lead to stress related problems. Consequently, a comprehensive electrical characterization of laser processed device wafers was undertaken. The I-V characteristics of n+-source diode from test structures on product wafers showed no deleterious effects on junction leakage after laser planarization as shown in Figure 7. The curves for lased and unlased dice on the same wafers showed exact overlap for this set of measurements. Similar behavior was observed for MOSFET transistor characteristics.

632

(mA)

2.000/div

V1

( V)

Fig. 7 IV characteristics of n+-source diode for laser processed and control wafers. Both the curves showed exact overlap for this set of measurements.

80e-

El

Leakage Current

0

Breakdown Voltage

60'E

a)

40-

20-

0-

IotA

IotB

IotC

IotD

Control

Fig. 8 Source to substrate leakage current and gate dielectric breakdown voltage before (Control) and after (lots A to D) laser planarization. 633

Figure 8 compares the source to substrate leakage current and gate breakdown voltage of laser processed wafers with control wafers and shows that junction and gate oxide integrity were preserved after laser planarization. In conclusion, we have achieved production worthy process windows as large as 20-30% for the laser reflow of Al into contact/vias. Full electrical evaluation including leakage current, breakdown voltage, metal continuity/shorts, contact resistance, and I-V characteristics of the laser processed devices have shown excellent results. We have successfully utilized this process for planarizing metal layers deposited on shallow junction contacts on DRAM's and obtained high yields with improved reliability on the finished product device wafers. ACKNOWLEDGEMENTS We would like to thank S. Kim, D. Mccullough for their help with every aspect of this project and R. Cross, A. Ditali for EM measurements. Thanks are due also to M. Tuttle and T. Lowrey for their constant encouragement during the course of this work. The authors would like to thank S. Chen at XMR Inc. for useful discussions. REFERENCES [1] R. Mukai, N.Sasaki, and M. Nakano, IEEE Electron Device Lett., EDL-8(2), 76 (1987). 121 D.B. Tuckerman and R.L. Schmit, in Proc. 1985 VLSI Multilevel Interconnection Conf.(V-MIC), IEEE Cat. 85CH2197-2, pp. 24 (1985). [ 3 ] D.B. Tuckerman and A.H. Weisberg, IEEE Electron Dev. Lett. EDL-7, 1 (1986). [41 B. Woratschek, P. Carey, M. Stolz, and F. Bachmann, International IEEE VLSI Multilevel Interconnection Conference (VMIC), Santa Clara, CA (1989).i [5 ] C. Yu, T.T. Doan, S. Kim and G.S. Sandhu, presented at MRS'90 Fall meeting, Boston, MA. [6 ] R. Liu, K.P. Cheung, and W.Y.-C. Lai, in Proc. 1989 VLSI Multilevel Interconnection Conf.(V-MIC), IEEE Cat. 89TH0259-2, pp. 329 (1989).

634

EFFECT OF BARRIER MATERIAL ON EXCIMER LASER PLANARIZATION OF AICu Harren Chu and Edith Ong XMR Inc., Santa Clara, CA 95054 Shi-Qing Wang' and Ivo Raaijmakers 2 Philips R&D Center, Signetics Company, Sunnyvale, CA 94088

keywords: Laser Planarization, Aluminum, Barrier

ABSTRACT The effect of barrier material (Ti, TiW, TiN) on the XeCI(308nm) excimer laser planarization process of AlCu is investigated. We find that the underlying barrier materials play an important role. A Ti barrier tends to give better filling characteristics than TiW, which in turn, is better than TiN. In addition, the resulting metal surface after laser reflow is much smoother with a Ti underlayer. We believe that the high chemical reactivity between Ti and AlCu contributes to some of these effects. In addition, laser melting redistributes Cu dopants in different AlCu-barrier systems uniformly throughout the AlCu film. INTRODUCTION Metal interconnect technologies pose great challenges to the manufacturing of advanced ICs as device dimensions decrease. Although materials such as W, Cu, and Si have been used, Al and its alloys remain the main interconnect materials for VLSIIULSI circuits. Among the various aluminum metallization schemes under development is the use of an excimer laser to reflow and planarize sputtered aluminum films over contacts and vias. This technique is a solution to the poor step coverage of as- deposited aluminum films and has been demonstrated to completely fill submicron contacts and vias [1-3]. The effectiveness of the laser planarization process, however, is very much dependent on the intrinsic material characteristics of the metallization system. For instance, the dopant distribution within the metal film is important. Woratschek et. al. have shown that large Si nodules in AlSi films are local sites for early ablation [4]. Also the use of anti-reflective coatings has been found to increase the process window [5-7]. Here, we look at the effects of different underlying substrates on the laser planarization process of Al-i %Cu. We will l 2

Present address: Present address:

National Semiconductor, Santa Clara, CA 95052 Novellus Systems, San Jose, CA 95134 635

look at the fluence requirements, the degree of fill, the grain structure, the surface roughness, the sheet resistance, and the degree of intermixing for laser planarized AlCu film on Ti, TiN, TiW, and SiO2 substrates. The integrity of different barrier layers as a diffusion barrier for the laser planarization process has been investigated elsewhere and will not be part of this study [8]. EXPERIMENTAL A lure thick layer of densified (9200C) boro-phospho-silicate glass (BPSG) was deposited on 4" (100) oriented Si wafers. Contact holes with a minimum diameter of 1.0 urn were etched anisotropically in this glass layer until Si was exposed. Prior to barrier layer deposition, wafers were precleaned by a short etch in diluted BF to remove native oxide from exposed Si in the contact holes. Thereafter, different barrier layers were deposited. The TiW barrier was deposited using a TiW target having a nominal Ti content of 10 wt %.The actual Ti content in the deposited layer is slightly lower [9] and, in this case, was measured to be about 9 wt % for the present layers. The residual gas pressure before deposition was about i0e"7 torr and the substrates were not heated intentionally. TiN (Ti-rich and N-rich) and pure Ti barrier layers were deposited in a different system. Wafers were heated to about 200'C before and during deposition. The residual gas pressure was about Ie" torr. TiN layers were sputter deposited from an elemental Ti target in Ar-N2 mixtures. The stoichiometry of the TiN layers was varied by varying the N2/Ar ratio in the working gas. Pure Ar was used for deposition of pure Ti layers. The present procedure resulted in a N content of 45 at. % and 52 at. % for the Ti-rich and N-rich layers, respectively. An Al-lwt%Cu layer of approximate thickness lum was deposited onto the TiN and Ti barrier layers without breaking vacuum. TiW was exposed to atmosphere before AlCu deposition. The substrate temperature during AlCu deposition was about 200°C. In some cases, AICu was also deposited on bare BPSG substrates. The as-deposited metal was lased with the XMR model 7100 aluminum planarization system. This system uses a pulsed 45ns FWHM XeCl(308nm) excimer laser source. Details of the system have been described elsewhere [6]. The specular reflectance at 308nm of the as-deposited samples unpatterned ) was monitored using the Perkin-Elmer Lambda 5 UV/VIS Spectrophotometer. A Si(100) wafer, doped with boron to a resistivity of 14-45 ohm-cm, was used as the reference, The actual composition of the various layers was assessed with 2MeV He+ Rutherford backscattering, using a scattering angle of 170 degrees. Secondary ion mass spectrometry (SIMS) analysis was performed using a Cameca IMS4F. The impact energy of the primary beam was 5.5 KeV per incident Cs+ ion. Positive secondary ions were extracted from the 85umr2 central portion of the 250ur 2 rastered area. The Cu data were quantified using data from the analysis of NBS standard alloy 3004 while the remaining data have been normalized to Al. 636

04 02 0.0

RESULTS AND DISCUSSIONS

-0.2

Planarization

-0.4

The minimum fluence for planarization of the contact structures described above are tabulated in Table 1. Consistent

with our previous results, the fluency required for planarization decreases with increasing substrate temperature [6]. We found, however, that samples with a Ti bartier require the highest fluence for planarization at all substrate temperatures and allow substantially higher fluences before the onset of ablation at 400°C. This results in a larger net planarization process window for the Ti samples at 4000 C. A factor which may explain the higher fluences required for planarization and ablation of samples with a Ti barrier was found to be the significantly higher specular reflectance of AICu on Ti (Table 1). However, the surface roughness of the as-deposited AICu on Ti was similar to that of the other samples (Figure 1). At this point, it is not clear why the specular reflectance should be higher for the Ti samples. Attempts have been made to test for differences in surface concentration of Cu, but we did not detect a significant change in surface

Table 1:

-0.4Q)

0

E

SiO2 TiW TiN, N-rich TiN. Ti-rich

1

0.4 "45 -0.2

00 C' 51 -02 in -0.4 0

100

200

30

100

200

300

0.2 0"0 -02 -04 0

E

0,4ý -0.20'0 0.2 -0.4

"0 10

o 200

30o

Scan Length (um) Figure 1: Stylus profilometer traces for as-deposited AlCu on a) Si02, b) Ti, c) TiW, d) TiN (Ti-rich), and e) TiN (N-rich) substrates.

Fluence requirements for planarization of Al- 1%Cu Min F(J/cm2)*

Substrate Ti

8.

04 0.2 S0.0 -0.2-

Max F(J/cm2) *

Reflectance* 140% 79%

250C 4.5 3.4

400C 3.0 -

250C 7.3 7.3

400C 6.7 -

60%

3.4

2.4

6.1

4.3

41% 35%

3.9 3.4

2.7 3.0

5.2 6.1

3.3 4.3

Reflectance measurementis specularreflectance at 308nm, measuredatnormal incidence and with reference to silicon Min F = Minimum Fluence needed for plananzation Max F = Minimum Fluence for onset of ablation

637

Cu concentraton withn me mints Or " SIMS.

and

It is also not clear why samples with the Ti barrier exhibit more resistance to ablation at 400°C. During laser planarization, however, oxygen and nitrogen can outgas from the TiW and TiN barriers to blow off the AlCu film; whereas, it is less likely for such gases to evolve with Ti samples. Contact Fill For these contact structures, complete contact fill was found only for samples with Ti and TiW barriers. Figure 2 shows that at 4.5 J/cmn and 250C, the degree of fill for the contacts with a Ti barrier is better than that with a TiW barrier or with no barrier at all. TiN barriers (both Ti-rich and N-rich) perform worst with respect to contact fill. Figure 2: Cross-section SEM This is a result which is both surprising micrographs of Al-I%Cu contact fill, and encouraging since we would expect the Ti as-deposited and irradiated with 4.5 J/cm2 sample to have least fill. The absorptivity of at 250C: a) and b) AICu on SiO2; c) and AICu on Ti is lower than that of AICu on other d) AICu on Ti; e) and f) AICu on TiW; g) substrates as is shown before by the higher and h) AICu on TiN (Ti-rich); and i) and fluence required for the onset of planarization j) AlCu on TiN (N-rich). for AICu on Ti films. Also, since filling characteristics can be altered by a change in the metal profile [5], one may suspect different as-deposited metal profiles on the different barrier substrates to cause the observed difference of fill. As shown in Figure 2, the as-deposited profiles for AlCu on different substrates are similar. Lastly, many have postulated that prolonged melt duration helps filling as substrate heating has been found to improve contact fill [1, 10]. Here, we cannot explain the difference of fill based on a difference in melt duration. Apparently, there is another factor causing our observed trend in contact fill. We postulate this factor to be wettability. It is known that different interface energies exist between AlCu and various barrier metals, and that the interfacial energy will decrease as the nature and structure of the contacting phases become increasingly similar. It is also known that metallic liquid moistens solid metallic bodies better if intensive chemical reaction takes place between them [11]. Here, we have a very reactive Ti compound which readily forms a layer of Al-Ti alloy between the top Al and the Ti barrier; we have a thin oxide layer between the top Al and the TiW barrier; and we have an AIN layer between the top Al and the TiN barrier [12]. Based on the above criterions for good wetting and the characteristics 638

F5.5

S. I

S40 S-f

Ti, 400C

T,N, 400C . ? ., Ti 0 T-N

400C

T

r~fh

IC

a

2

.0

2

3

4

5

6

7

Fluence (J/cm2)

Figure 3: Plan view SEM of AlCu surface morphology with a) Ti, b) TiN, c) TiW, and d) SiO2 underlayers after irradiation at 3.9 J/cm2 at 250C.

Figure 4: Change in sheet resistance with Fluence.

of our AICu-barrier systems, we would expect A1Cu to adhere best to Ti, then to TiW, and lastly to TiN. This is consistent with our observed trend in fill. Morphology Consistent with the findings of others, we find that grain size increases with increasing fluence and substrate temperature [13]. We also find that the resultant metal morphology and surface roughness are significantly different for AICu on different substrates after laser planarization. Figure 3 shows that under a given processing condition, the crystallized AlCu grains are largest with underlying SiO2 layer and smallest with an underlying Ti layer. This probably results from the differences in the nucleation and crystallization of molten AlCu on different barrier layers. This result can also be related to differences in chemical reactivity of the substrates. Sheet resistance The sheet resistance was measured before and after laser melting with a four point probe. As shown in Figure 4, the sheet resistance increases with fluence and substrate temperature. Since TiAI3 is readily formed between Al and all substrate barriers (Ti, TiW, and TiN) [12] and since TiA13 is the primary compound which forms above 440C [14,15], we postulate that our increase in sheet resistance is due to this TiA13 formation. Intermixing Our SIMS data (Figure 5) indicate that Ti intermixes readily with the Al layer after laser melting. The degree of intermixing, however, is less severe for AlCu on TiW and TiN (not shown). This is again consistent with the predicted chemical reactivities of our AlCu-barrier systems. Similar data has been reported for TiW barrier [13]. Also in Figure

639

J

.. .. .. ... .•A ,

tj

40

1

S,

E

Approximate Depth tmicrons)

Approximate Depth (microns)

Figure 5: SIMS depth profiles of AI-l%CuJri/SiO2/Si: a) 5 minutes at 250C and b) processed at 3.4 J/cm2 at 250C. 5, we see that the initial Cu pile-up is redistributed uniformly throughout the AICu film after laser melt/crystallization. CONCLUSIONS We have demonstrated that the underlying barrier material plays an important role in the laser planarization of AlCu. Planarization and contact filling properties are best for AlCu on Ti, which is better than that on TiW, which is better than that on TiN. Grain size and surface roughness is largest for lased A1Cu on TiN, which is larger than that on TiW, followed by that on Ti. The resulting sheet resistance and interface mixing are also dependent on the barrier material used. These characteristics can be attributed to the chemical reactivity of the adjacent barrier material with AICu. ACKNOWLEDGEMENTS Special thanks to Dr. S. Chen for his support. REFERENCES [1]

R. Mukai, N. Sasaki and M. Nakano, MRS Symp. Proc. 74,229 (1987). also published in IEEE Electron Decv. Lett. EDL-8, 76 (1987). [2] R. Mukai, K. Kobayashi and M. Nakano, Proc 5th Int. IEEE VLSI Multilevel Interconnection Conf., p. 101, Santa Clara, CA. (1988). [3] D. Pramanik and S. Chen, Proc. IEDM, p. 673 (1989). [4] B. Woratschek, P. Carey, M. Stolz, and F. Bachmann, Proc. 6th Int. IEEE VLSI Multilevel Interconnection Conf., p. 309., Santa Clara, CA. (1989) [5] R. Liu, K.P. Cheung, W.Y.C. Lai and R. Heim, ibid, p. 329. [6] I.J. Raaijmakers, H. Chu, E. Ong, S-Q Wang and K. Ritz, MRS Symp. Proc. 181, 553(1990). [7] C. Yu, G.S. Sandhu, and T.T. Doan, "CVD W, TiW, Ti as Anti-Reflective Coatings for the Laser Planarization of Al-Alloy for ULSI Metallization", presented at the 1990 MRS Tungsten Workshop, to be published at MRS Conf. Proc., VLSI-6. 640

[8] C. Yu, T. Doan, S. Kim, Proc. 7th Int. IEEE VLSI Multilevel Interconnection Conf., p. 444, Santa Clara, CA (1990). [9] I.J.Raaijmakers, T. Setalvad, A.S. Bhanssali, Brad J. Burrow, Laszlo Gutai, and Ki-Rum Kim, J. Electron. Mater. 19, 1221 (1990). [10] R. Baseman and J. Andreshak, MRS Symp Proc. 158,267 (1990). [11] M. Humenik and W.D. Kingery, J. Amer. Cer. Soc. 36, 11, 362 (1955). [12] A.S. Bhansali, I.J. Raaijmakers, R. Sinclair, A.E. Morgan, B.J. Burrow, and M. Arst, MRS Symp Proc. 187, 15(1990) [13] E.K. Broadbent, K.N. Ritz, P. Maillot and E. Ong, Proc. 6th Int. IEEE VLSI Multilevel Interconnection Conf., p. 336, Santa Clara, CA (1989). [14] J. K. Howard, R.F. Lever, P.J. Smith, and P.S. Ho, Journal of Vacuum Science Technology, 13, 68 (1976). [15] R.W. Bower, Applied Physics Letters, 23, 99(1973).

641

APPLICATION OF A SPIN-ON-GLASS PLANARIZATION PROCESS TO SUBMICRON TRIPLE METAL TECHNOLOGY Seiichi Morimoto, Sarah Queller, Robert Gasser and Janice Kronschnabel Portland Technology Development Intel Corporation 5200 N.E. Elam Young Parkway Hillsboro, Oregon 97124

Various spin-on-glass (SOG) planarization processes have been used in the fabrication of semiconductor devices. Their purpose is to planarize topographies both above and below the metal interconnect layers. This paper describes a no etchback SOG process that is capable of planarizing submicron metal spaces without cracking. The use of an organic SOG along with appropriate post spin treatments produces a planarizing film with consistently low via resistances of 100-150 mohms. When exposed to an accelerated steam environment of 158'C and 5 atms., the film was found to be acceptable in terms of delamination, capacitance increases, and leakage currents. Planarity and lithography effects were evaluated for a triple layer metal process. The no etchback SOG process was demonstrated to be a viable planarization approach for a submicron multilevel metal process. A separate SOG process was developed to enhance the planarization of the BPSG surface beyond the partial planarization that is obtained with thermal glass flow cycles. Flat BPSG slopes of almost zero degrees were achieved with this sacrificial SOG planar etchback process. INTRODUCTION Spin-on-glass processes are relatively simple and economical and have been widely used to planarize both submetal and intermetal dielectrics. SOG has an advantage over traditional resist etchback planarization schemes in that its similarity to silicon dioxide allows it to remain as an integral part of the device. Although SOG alone is not a good insulator, it can be readily integrated with CVD films to yield stable insulating properties. SOG also has an advantage over fully planarizing processes in that it is a smoothing film and it produces less via depth differential than that produced by a fully planarizing film. This decrease in via depth differential improves the metal step coverage and reliability. For applications to double metal layer technologies with geometries above 1p.m, SOG planarization has typically been achieved by etching back the SOG so that it remains only in the metal spaces. A relatively thick ILD underlayer is required

642

between the metal and the SOG to prevent loss of planarization once the etch clears the tops of the metal lines. The etched back SOG is then capped with an ILD overlayer which acts as the bulk of the interlayer dielectric. This approach isolates the SOG from the via regions, eliminating via resistance problems associated with outgassing of the SOG film in the via holes. However, the feasibility of this etchback approach is questionable for submicron geometries: The 1lD underlayer required to preserve the planarity during the etchback is thick enough that it pinches off the submicron spaces. The use of SOG to planarize a triple metal process also presents a challenge with regard to achieving adequate planarity. Since SOG planarization is smoothing as opposed to fully planarizing, the metal 3 layer sees the cumulative effect of the planarization of both the premetal and the intermetal dielectrics. Improving the planarization of the glass layer prior to the first metal deposition will improve the planarity seen at the metal 3 layer. This paper describes a SOG planarization scheme that provides adequate planarization for a submicron triple metal process (Figure 1.)

M3 SýOG

-M2

. .

SOG

IpllBPSG

Figure 1: SOG Planarization Scheme

THE DEVELOPMENT OF A NO ETCHBACK SOG PROCESS As described above, a traditional SOG etchback process is not compatible with

643

submicron geometries. The approach taken here to solve this problem is to increase the process window by allowing the SOG to be left on top of the metal and eliminating the etchback step. When SOG is not etched back and is left on top of the metal, however, there are several major issues that must be resolved. 1) SOG outgassing must be eliminated in order to obtain low and stable via resistance when SOG exists in the via region. 2) The reliability aspects of leaving SOG over the entire wafer surface, such as delamination during the high temperature/humidity testing, must be resolved. 3) The integrity of the insulating material as measured by leakage and capacitance between the metal lines as well as between the metal layers must be ensured. 4) SOG cracking and filling problems must be eliminated in the submicron metal spaces. To resolve the issues described above, the following no etchback SOG process sequence was used. 1. Thin ILDI deposition, IOOA plasma oxide 2. SOG spin/bake, 4000A double spin of organic type SOG 3. SOG cure, plasma nitrogen at 400'C for I hour 4. Thick ILD deposition, 5000A plasma oxide 5. Via pattern and etch with chemical resist strip 6. Post via cure, nitrogen at 450'C for 1 hour 7. In-situ sputter etch prior to metal deposition Achieving low and stable via resistance with this process is dependent on eliminating the contamination of the metal film that can occur when SOG outgasses during the metal deposition. In the process described here, consistent via resistances of 100-150 mohm are obtained by curing the SOG at 400'C in a nitrogen plasma, using a chemical resist strip rather than a plasma strip, and including an in-situ sputter clean prior to metal deposition. With this sequence of process steps, the via resistances described above could be achieved with either high organic content SOG material or with inorganic silicate SOG. Via resistance test structures evaluated included a structure with vias placed on a wide metal plate where SOG thickness is maximum. Devices processed using the no etchback SOG planarization were tested in a high temperature and high humidity environment. After 90 hours in steam at 158'C and 5 atmospheres, there were no signs of either delamination or cracking. For devices passivated with oxynitride, the post stress increase in layer to layer capacitance measured 13% and the post stress increase in line to line capacitance measured 2% (Figure 2.) The leakage current measured between metal lines was

[PPQ]nH

Considering results obtained in the reduction of PPQ [I I], We can assume that hydrogen is bonded at nitrogen sites of the PPQ (fig.3).

Figure 3: PolyPhenylQuinoxaline. Some additional experiments were performed using a molar (IM) aqueous solution of HCI instead of concentrated one. In this case, when the potential is held at more reducing values (-4V) we observe hydrogen bubble evolution but no change in the PPQ colour even when this cathodically treated film is dipped in concentrated HCI. This surprising result means that in 1 molar HCI the PPQ is not reduced. At this time, we have no evident explanation of such an effect. However, we can imagine that only a dissolved PPQ is electrochemically reduced. Since the reduction is obtained only in concentrated HCI and in acetonitrile one can conclude that the polymer is slightly soluble in these two media but remain insoluble in diluted (IM) HCI. We did not perform electrochemical measurements using PPQ dissolved in organic solutions [41. The mean reason is that the aim of this work is to investigate the electrochemical behaviour of thin PPQ films over silicon substrate, i.e when the polymer stands in the interconnection modules. CONCLUSION In conclusion, we have demonstrated that when a PPQ film over silicon substrate is dipped in HF solution, both electrochemical and chemical effects occur. The electrochemical reactions which involve current flow occur even in absence of external current supply. These results were found consistent with electrochemical measurements. Different PPQ colours which correspond to different redox and acid/base states of the PPQ have been also evidenced. We believe that in the reduced state the hydrogen is bonded to the nitrogen sites of the PPQ. This reduced state was found unstable in oxygenated ambient (air). From some electrochemical experiments performed in organic solvent we conclude that the PPQ reduction involves protons (H+). Meanwhile, other characterisation techniques such as Infrared and UV transmission must be used in order to determine the exact chemical structure of the different states of the PPQ. Since this polymer is used as a dielectric in our process, electrical measurements must be performed in order to determine if the electrical parameters such as the dielectric constant and the conductivity of the polymer are changed by the different observed effects.

718

REFERENCES [1] F. Templier, J. Torrts, J. Palleau and A. Halimaoui, to be presented at the MRS '91 Spring Meeting, Anaheim. [2] Z. Chi, L. Tongming and L. Fengcai, Kexue Tongbao, 20, 1697 (1988). [3] K. R. Barqawi and M. A. Atfah, ElectrochimicaActa, 4, 597 (1987). [41 R. Even and M. Petit, Technical report, 1990. [5] S. A. Jenekhe, Macromolecules, 24-1, 1 (1991). [6]

S. Mazur, P. S. Lugg and C. Yarnitzky, J. Electrochem. Soc., 134-2, 347 (1987).

[7]

N.S. Sariciftci, H. Kuzmany, H. Neugebauer and A. Neckel, Phys., 92-7, 4530 (1990).

[8]

G. Froyer, Y. Pelous, A. Siove, F. Genoud, M. Nechtschein and B. Villeret, Synt. Metals, 33, 381 (1989).

[9]

D.R. Turner, J. Electrochem. Soc., 105-7, 402 (1958).

[101

M.I.J. Beale, J.D. Benjamin, M.J. Uren, N.G. Chew and A.G. Cullis, Journalof Crystal Growth, 73, 622 (1985).

[11]

J. Chem.

P. Launay and J. Armand, C.R Acad. Sc. Paris,270-23, 1881 (1970).

719

GAP-FILL WITH PECVD SILICON DIOXIDE USING DEPOSITION/SPUTTER ETCH CYCLES Geraldine Cogin Schwartz and Pauline Johns IBM East Fishkill, Hopewell Junction, NY 12533

ABSTRACT The evolution of a process consisting of alternate cycles of PECVD deposition and sputter etching in Ar to fill narrow spaces between adjacent metallic conductors (gaps) with PECVD SiO has been studied. For a fixed process and metal thickness, as Afk (AR = height/width) increases, a low-density region is formed in the gap. At higher AR, physical voids are formed. The ability to fill the gaps with good quality oxide is a function of AR, side-wall angle and the thickness of the metal. Filaments of an unidentified material are detected within the gap. Higher AR spaces can be filled if more of the oxide is sputtered. However, decreasing the thickness of the PECVD film or using 02 instead of Ar has the opposite effect. The low density region in the gap etches at the same rate in a CF 4 plasma; therefore misalignment of vias is not a concern. The dielectric constant of the PECVD SiO 2 is unchanged by sputter etching; the high-field break-down strength of the oxide is reduced. However, after the structure is completed by the deposition of a thick PECVD layer, the effect of the dep/etch cycles on the break-down strength of the composite is not detectable.

INTRODUCTION The difficulty in filling high AR spaces between adjacent conductors by deposition of a film from extended sources is a consequence of shadowing by steps in the underlying structures to be covered by the deposited film. Shadowing results in thinner films on the side walls of a step than on an exposed horizontal surface and minimal coverage at the inside corners of the step [1,2,3,41. Therefore, as the deposition proceeds, the film eventually grows together at the top of a narrow space; this results in an enclosed void within the space. In CVD and PECVD, if TEOS replaces SiH as the Si-source gas in the deposition of SiO 2 the step coverage is improved. This has been attributed to enhanced surface migration of the reactants or of the precursor species along the surfaces [2] or to a decrease in the sticking coefficient of the arriving species [5]. Instead of improving the conformality, attempts have been made to make the TEOS/0 2 process for PECVD highly directional. [6,7,8,9]. However, the improvement in gap-fill has been illustrated only for relatively low AR spaces and thin conductors. 720

In order to fill higher AR spaces, between thicker conductors, processes using sequences of deposition (PECVD and/or CVD) and etch-back steps (RIE and/or sputter etching) in multi-chamber reactors have been developed [10,11,12]. In a somewhat different approach [13], the gap was filled partially with bias-sputtered SiO 2 ; fill was completed by depositing PECVD oxide in another reactor. Relatively high AR between thick conductors can be filled without voids by this process [14] but two separate reactors are used. We studied the PECVD deposition and sputter etch parts of the process described by Bader et al., [12]; we have abbreviated the name to dep/etch. It is a simpler process than the ones decribed in refs. 10 and 11, and less susceptible to contamination than that of ref. 13, which requires tranfer of the wafers between two independent systems. The principle of improved gap-fill by deposition and sputter etching is the same as that invoked in explaining planarization by bias-sputtering [15] i.e., the sputter etch rate depends of the angle of incidence of the impinging ions [16]; an inclined surface etches at a higher rate than a horizontal surface, and a surface parallel to the ions will not be etched. Therefore, the top corner of a step in the deposited film is etched at a higher rate than the film on the horizontal surfaces. The blocking film is thereby etched back so that the acceptance angle presented to the incoming reactants is larger, i.e., the shadowing reduced.

EXPERIMENTAL The dep/etch process we investigated consisted of alternate cycles of PECVD SiO, deposition, using TEOS and 02, and sputter etching in a magnetically-enhanced argon plasma plus a final thick PECVD SiO 2 film adequate to insulate successive wiring planes. The underlying structures were aluminum-alloy conductors formed by reactive ion etching, RIE. The deposition and etch conditions are given in Table I. The standard dep/etch sequence was: deposit 2500A/ etch 500A, although we varied both the thickness of the deposit and the amount sputter etched during the investigation. To examine the effect of taper angle, the underlying metal pattern was formed by lift-off so that the side-walls were 84-85'. In this case, the dep/etch sequence was +6000A/-1200A, but we were not successful in using it for the vertical-walled structures. The completed structure can be partially planarized by chemical-mechanical polishing (CMP) [17] or by resist-etch-back of the final thick PECVD oxide layer, but this step was usually omitted in the work reported here. Deposition and etching were done in separate chambers of a single-wafer multi-chamber reactor with vacuum-transfer between chambers. The chambers were cleaned after each step of the process. The deposition rate was about 7000-8000 A/min; the etch rate only about 300A/min. The experimental technique used to study the evolution of gap-fill as well as the final result was almost exclusively scanning electron microscopy, SEM. 721

Cross sections of the samples were dipped in a buffered-HF solution, BHF, (which also contained glycerine to minimize the attack of the metal lands) to detect regions of different densities within the oxide layer. Other cross-sections of the same samples were etched in an aluminum etch (but not in BHF) to make the photographs more distinct when examining the deposited (unetched) oxide. Thus it was possible to distinguish between low-density regions and physical voids within the gap and to evaluate the etch rates of the oxide in different areas, e g., the side wall vs. the horizontal surface. To investigate the effect of AR, at constant metal thickness, a line/space test-site of varying pitch was used. In order to determine whether the low-density oxide in the gap and the oxide of normal density surrounding it were etched by RIE at different rates, the samples were planarized by CMP, then etched in a CF 4 plasma until the fast-BHF-etching region in the gap was exposed to the etchant. Cross-sections of these samples were then examined with and without decoration in BHF. Cross-sectional transmission electron microscopy, TEM, was used to try to detect differences in density/material in the deposited oxide without the use of preferential etches. We also compared some of the electrical properties of PECVD oxides to those subjected to the dep/etch process, using MOS capacitors with large areas and with low ramp-rates for break-down measurements.

RESULTS and DISCUSSION As in sputter deposition, the higher the AR and the steeper the side-wall angle, the greater the difficulty of void-free filling [18,19, 20]. In the deposition of SiO 2 by PECVD a similar phenomenon is observed. For a given process sequence and metal thickness, as the gap is decreased, at some critical value of AR, a region which etches very rapidly in BHF is seen at the center of the gap. We interpret this as a region of low density or a porous region. At still higher values of AR, physical voids are formed. What had not been reported previously (but is not surprising) is that it is not only the AR itself, but the absolute depth of the gap as well, that determines how well it can be filled. The relationship between the metal thickness and the AR that could be filled without formation of porous regions is shown in fig. I. As in all depositions from an extended source, the side-wall coverage by the PECVD oxide depended on the gap width; the maximum coverage, of an isolated line, was about 60%. The thinner oxide on the side wall has an effect equivalent to a reduction of the AR as seen by the arriving reactants; this facilitates gap-fill. Not unexpectedly, vertical-walled spaces were harder to fill that those with sloping sides in the dep/etch process as well. Figure 2a shows SEMs of fractured cross sections of a series of samples of increasing AR after completion of a 5-step dep/etch process (2 dep/etch cycles + final oxide) and dipped in BHF after fracture. Low-density regions are observed in the higher AR spaces, as mentioned above; in addition, filaments are visible within all the gaps. Our interpretation of the SEM is that the filaments consist of a material that etches more slowly in BHF than the bulk of the oxide. The number of these filaments corresponds to the number of etch steps when the gap is narrow and the walls are vertical. Often a button of 722

material is seen at the corners of the metal stripes. Growth seams are visible within the gap; the interfaces between successive oxide layers are also highlighted. As the AR is increased by decreasing the spacing between conductors of a constant height, the growth seam within the gap widens slightly, enlarges at the base, and finally, successivly larger low-density regions are formed. In gaps of moderate AR, the low-density regions are buried well below the tops of the adjacent conductors. At high AR, they extend to the level of the conductors; we have had almost no samples with metal so thick and spaces so narrow that the low-density region extends beyond the top of the metal. When the cross sections are not decorated in BHF no filaments, buttons, growth seams, or interfaces between layers are visible (fig. 2b). If the AR is high enough, physical voids are formed; these are always smaller than the corresponding low-density region. The progress of the gap-fill process was followed by stopping it after each step and examining fractured cross sections of the resultant structure with and without decoration in BHF. Figure 3a shows the profile of an initial oxide, 2500A thick; after BHF decoration (fig. 3b) it can be seen that the oxide on the side wall was etched at a higher rate than that on the horizontal surface. After sputter etching 500A of oxide from the horizontal surface in Ar, the facet angle of 47' can be seen (fig. 3c). The thickness of the oxide on the side wall appears to be unchanged and none would be expected because of the normal incidence of the ions. We do not detect thickening (re-deposition) on the side-walls. However, when the same structure was decorated in BHF (fig. 3d), two distinct layers are visible along the side wall. In addition, the oxide at the top corner has been etched completely and the thickness of material midway along the wall appears to be greater than in the structure which had not been exposed to BHF. We have no explanation of this apparent contradiction. Figure 3e is the SEM of a sample after a second deposition of 2500A; the gap is filled to about half its depth and the top of the gap is more tapered than in the starting structure. After exposure to BHF (fig. 30, the first oxide layer is, of course, protected from the etch and the film thickness at the top corner is great enough so that it is not etched completely. Along the side-wall, what had appeared as the outer layer in fig. 3d, now seems to be a stubby filament covered by the second oxide. The oxide on the walls near the top of the gap has been thinned. One possible source of the slow-etching filamentary material might be metal sputteied from the underlying conductor, although no attack can be detected. No contaminants were detected by x-ray fluorescence analysis, XFSA, or near the side-wall when examined in cross section by TEM. The filaments were also formed if the the underlying structure was silicon or SiO 2 instead of aluminum-alloy. We then considered the possibility that the the filaments were formed by preferential sputtering of oxygen during etching, leaving silicon or silicon-rich oxide on the walls of the gaps. This would be consistent with a material which etched slowly in BHF. And a faintly denser region was detected near the side-wall in the TEM. However, filaments could not be etched in CF4, or in wet 723

silicon etches. To try to resolve this issue, 02 was substituted for Ar as the sputtering gas. As expected (21], the sputter etch rate decreased to about half its value in argon. As seen in the comparison of the SEMs in fig. 4, on the sample etched in 02, filaments could no longer be detected (decorated sample), but the buttons were still seen. The interfaces between successsive layers were still noticeable, however. The composition of the filaments and buttons has never been identified nor the apparent contradictions resolved. They are not seen in gaps filled by bias sputtered SiO2 or after PECVD of SiO2 which was not followed by sputter etching. The effect of these anomalous structures on the electrical characteristics of the oxide in the gap has still to be determined. For a given thickness of metal and initial oxide deposited, gaps of higher AR could be filled by increasing the amount of oxide sputter .etched, i.e., by increasing the sputter etch time, as illustrated in the graph of fig. 5. The maximum sputter-etch-back time was determined as the time it took to reach, but not attack, the top edges of the conductors forming the sides of the space. Thus, there appears to be a limit of AR to which this process can be extended which will also depend on the thickness of the underlying conductors. Since the sputter etch step was rate-limiting, the thickness of the oxide deposited initially was decreased to minimize the side-wall coverage, and thus, reduce the time required for adequate etch-back. However, this resulted in a much deeper space after etch-back and was self-defeating. The AR that could be filled by a given dcp/etch process was lower when 02 was substituted for Ar. This was attributed to the fact that the facet angle formed by sputter etching in 02 was 67', while, as mentioned previously, the facet angle formed by sputtering in Ar was 47'. Thus the acceptance angle for the arriving reactants was reduced when 02 was used. Because of overlay error in photolithography, the low-density regions between the conductors can be uncovered when the resist pattern for interlevel vias is exposed. Therefore, there is a concern that such vias might be over-etched (luring RIE. We demonstrated that the etch rate in a CF 4 plasma of the low-density material in the gap was the same as that of normal PECVD oxide, as seen in fig. 6. Therefore, mis-aligned vias would not be over-etched if the via im,qge included or abuttdd the region containing porous oxide. The dielectric constant of the interlevel oxide was not affected by the inclusion of sputter etch steps. However, oxides deposited using the dep/etch cycles consistently had lower high-field breakdown strengths, E , than PECVD oxides of approximately the same thickness although the numbers and distributions of low-field breakdowns were comparable. This result is illustrated in fig. 7. One of the causes of the shift to lower break-down strength could be inclusion of particulates, generated by sputter etching or introduced by flaking of poorly adherent deposits sputtered on to the chamber walls. But we found no correlation with chamber cleaning protocol. Another possiblility is is damage due to sputtering; however, this there is no independent evidence for this. The existence of interfaces has been noted, but we do not understand how 724

they would affect the processes responsible for breakdown. None of these, however, seem to be reasonable explanations for the reduction of the high-field breakdown strength while leaving unaffected breakdown events that might be attributed to defects, i.e., the low-field breakdowns. Over-coating the layers formed in the dep-etch cycles with PECVD SiO improves the breakdown characteristics. The structure used as an interlevef insulator included a final thick PECVD SiO 2 layer; it could not be broken down at 1000V. Therefore the degradation of the dielectric breakdown, which appears to be a consequence of sputter etching the PECVD film, is not a practical concern. TABLE I DEPOSITION

SPUTTER ETCH

Wafer-holder temperature = 390'C Input rf power = 350 watts Flow rate TEOS/He = 310 sccm Flow rate of 02 = 325 sccm Pressure = 9.0 Torr Electrode spacing = 185 mils

Input power = 300 watts Pressure = 17 mTorr Ar flow - 50 sccm Magnetic field = 60 Gauss

ACKNOWLEDGEMENTS We appreciate the help of R. Carruthers, B. Cunningham, T. Desormier, K. Olsen and M. A. Zaitz, of IBM East Fishkill and J. Marks and E. Yieh of Applied Materials.

REFERENCES [11CJ.Standley, R.E.Jones, and L.I.Maissel, Thin Solid Films, 5, 355, (1970). 12] R.M.Levin and K.Evans Lutterodt, J.Vac.Sci.Technol., B 1, 54, (1983). 131R.C.Ross and J.L.Vossen, Appl.Phys.Lett., 45,39 (1984). [41 A.C.Adams, Solid State Technology, 26-4, 135 (1983). 151 L.-Y.Cheng, J.P.McVittie, and J.P.Saraswat in ULSI Science and Technolgy 1989, C.M.Osbum and J.M.Andrews, eds., The Electrochemical Society, Pennington, NJ, PV 89-9, 586 (1989). 161J.J.Hsieh, D.E.Ibbotson, J.A.Mucha, and D.L.Flamm, 1989 Proc. IEEE VLSI Multilevel Interconnection Conf., p. 411. 171D.A.Webb, A.P.Lane, and T.E.Tang, in ULSI Science and Technolgy 1989, C.M.Osbum

and J.M.Andrews, eds., The Electrochemical Society, Pennington, NJ, PV 89-9, 571 (1989). 181D.E.Ibbotson, J.A.Mucha, J.J.llsieh, and D.L.Flamm, Flectrochem.Soc.Ext.Abstr. #131, PV 90-1 (1990).

191L.J.Olmer and C.A.Daverse, ibid., #132. [101 O.Spindler and B.Neureither, Thin Solid Films, 74, 67 (1989).

[111J.Marks, K.Law, D.Wang, 1989 Proc. IEEE VLSI Multilevel Interconnection Conf., p.89. 1121 M.E.Bader, R.P.HiaII, and G.Strasser, Solid State Technology, 33-5, 149 (1990),

[13] M.Abe, Y.Mase, T.Katsura, O.tirata, T.Yamamote, and S.Koguschi, 1989 Proc. IEEE VLSI Multilevel Interconnection Conf., p. 404.

1141 G.C.Schwartz, unpublished. 1151 C.Y.Ting, V.J.Vivalda, and H.G.Schaefer, J.Vac.Sci.Technol., 15, 1105 (1978). 725

1161 A.1).Stewart and M.W.Thompson, J.Mat.Sci., 4, 56 (1969). 1171 K.D.Beyer, W.L.Guthrie, S.R.Makarewicz, E.Mendel, W.J.Patrick, K.A.Perry, W.A.Pliskin, J. Riseman, P M.Schaible, and C.L.Standley, IJSPatent # 4,944,836 (1990). 1181 l.A.Blech, D.M.Fraser, and S.E.1aszko, J.Vac.Sci.Technol, 15, 13, (1978). 1191 lI.1'.Bader and M.A.lardon, J.Vac.Sci,Technol., B 4, 1192 (1986). 1201.. S.logan, M1..l1ait, TI.C..lones, G.R.Firth, and 1).B.Thompson, J.Vac.Sci.Technol, A 7, 1392 (1989). 121] R.lF.Jones, 11T.1Winters, and 1,.I.Maissel, .1.Vac.Sci.Technol., 5, 84 (1968). 0.9

FIGURE 1 0.8

ASPECT RATIO of GAPS FILLED with NO POROUS REGION vs. METAL. THICKNESS

S0.7 0•.6 0.5 1.5 13 1.1 09 0.7 0.eo.7 o. k (micr 1.3 m 1e5 Metal Thickness (micrometers)

(7 1,

PIIYS'.A ILVOI)', (NO 1il IOIF( ORA I ION) IN( RIASING AR; MI; IAI - 1.1 MIICRON

FIGURE 2 GAP-FILL INCREASING AR

(a) DECORATED in BHF

(b) NO BHF METAL ETCHED

726

j.I

z

I-

0

0

0

0 0.

727

FIGURE 4 COMPARISON of Ar and 02 as SPUTTER ETCH GAS

(a) Ar

(b) 0 2

FIGURE 5 AR of GAPS FILLED vs. SiO 2 SPUTTER ETCHED

1.1 Porous Reqion

1.0 t,

0.9 -

0.9

0.8

-Z

ý

No Porous Region

0.7 500

750 Amount Sputter Etched (A)

728

1000

FIGURE 6 RIE of POROUS REGION in GAP in CF 4 PLANARIZE, ETCH in CF4

FIGURE 7 BREAK-DOWN CURVES PECVD vs. DEP/ETCH O

K

0 0-4300A

x-398OA

x x x x x x x x x x x x x x x x ×

2X DEP-ETCH DEP ONLY

0 0 0 0 0

e

-

0 0 0 0 0 0 0 0 0 0

2

x x x x x x

0

0

0 0

0

0

0 0

0

I

0

°0 0 0

0 0x

0

I

I

5 FIELD STRENGTH - MV/CM

729

I

I

I

I 10

THE MAGNETRON-ENHANCED ETCHING OF DOUBLE-LEVEL TUNGSTEN INTERCONNECT R. Hsu, C. Y. Fu and B. Law Lawrence Livermore National Lab Livermore, CA 94550

We evaluated dc magnetron-sputtered tungsten (W) and molybdenum (Mo) for double-level interconnect. The combined C12 and NF 3 chemistry was chosen over either gas or SiC14 for magnetron-enhanced etching to achieve better etch selectivity and profile. Tungsten was picked over molybdenum for a more anisotropic etch profile. The etch rate of W depended strongly on sputtering conditions. A reasonably high etch rate at 400 nm/min was obtained with selectivity to resist at about 1.4 to 1. Adhesion layers of 30 nm of TiW or Ta added to either M1 or M2 could be etched by the same recipe with no undercutting. The vertical profile achieved was found to be independent of feature size and had a large operating window in rf power, temperature and overetch time. This process has been successfully applied to define patterns for a double-level interconnect structure.

INTRODUCTION The trend of shrinking features in ULSI design has gradually pushed the aluminum alloy interconnect to its theoretical limitations in terms of electromigration resistance and high temperature compatibility. Refractory metals like tungsten (W) or molybdenum (Mo) become favorable candidates due to their high-temperature stability, corrosion-resistance, and low contact resistance [1]. Although CVD gives better step coverage, the surface is very rough [2-5]. We chose sputtering deposition for the following reasons: (a) the film surface is smooth, (b) no toxic gas used, and (c) adhesion layer or multi-layer can easily be added without breaking vacuum. Adequate step coverage can be achieved for a somewhat planarized topography [1,6-9]. Photoresist patterning of W and Mo with plasma etching using chlorine and/or fluorine etchants usually has problems with profile control, low etch rate, or poor selectivity to resist [2-4]. The higher plasma density associated with magnetron-enhanced reactive ion etching (MIE) as well as better wafer temperature control have been shown to resolve these issues [5]. 730

The purpose of this paper is to study in a sytematic manner the important variables in both the deposition and etch processes that have significant effects on the plasma etch results. A comparison of W and Mo patterning by MIE with different levels of Cl- and F- containing gases follows in order to make the final choice of our double-layer interconnect.

EXPERIMENTAL

Silicon wafers, 4 inches in diameter, were thermally oxidized prior to the deposition of the material to be tested. The first and second level metals (M1 and M2) being evaluated included both W and Mo deposited by dc magnetron sputtering. The original sputtering recipe for W was 1.7 kW power, 63 mTorr pressure, 150 W rf bias power at 175 °C preheat temperature. The W film stress was unpredictable and varied between 600 MPa to 1.5 GPa with resistivity of 50 gohm-cm. The thickness of the films was 200 nm for M1, 500 nm of undoped glass for interlayer dielectric, and 500 nm for M2. The stress of W tends to become highly tensile if annealed above 800 °C [7]. To ensure film integrity during a subsequent 750 °C anneal, a 30 nm adhesion layer of TiW or Ta was also sputtered in-situ for both M1 and M2. One- and two-micron-deep UV photoresists with 30 minutes bake at 120 0C were used in M1 and M2 patterning, respectively. The MIE operating at 13.56 MHz was performed in an MRC ARIES etcher (Fig. 1). Uniform plasma was formed right above the wafer on the cathode by the careful alignment of the counter magnet with the internal magnet. The wafer was held down with three clamps to enhance wafer backside cooling with He at 10 Torr. Both the chamber wall and the cathode had independent temperature control with dual channel heat exchangers. The etch gases studied were SiC14 , C12, NF 3 , and different combinations of NF 3 and C12. Total gas flow and pressure were 40 sccm and 10 mTorr, respectively, in most of the studies. The W thickness was determined by profilometer measurement of step height, subtracting the oxide removed near the dot-mask defined pattern after MIE. The etch rate was then determined after taking into account the fraction of etch time consumed in oxide etch. In order to minimize the inaccuracy of etch rate calculation, the etch time must be estimated properly such that excessive oxide loss can be avoided. The uniformity was calculated based on the maximum and minimum values of five measurement points per wafer.

731

Fig. 1 Schematic of etch chamber for the MIE system. RESULTS AND DISCUSSION The etch rates achieved for W, Mo, SiO 2 and photoresist within the rf power range are summarized for different etchant gases in Table 1.. The following observations were made: Pure Cl etchants in general led to low etch rate and poor selectivity to both SiO 2 and resist. The Cl 2 gas was preferred over SiC14 because of potential SiC14 condensation problems. The NF 3 was chosen as the F source because it contains both F and N, and N might play an important role to passivate the sidewall and provide the end point signal [5]. With pure NF 3 etch, the etch profile is slightly positive for W and positive for Mo. This indicated that N alone did not provide enough sidewall protection until C1 was also added. NF 3 also led to polymer formation and thus resulted in incomplete etch with black residue left on the Mo surface. The combination of C12 and NF 3 at 500 W led to the best results in both selectivity and profile control. We observed a strong dependence of etch rate on the metal sputtering conditions. Most of the W etch rates in Table 1 were based on W prepared from the original sputtering recipe. As the F chemistry was evaluated, the sensitivity of etch rate to the sputter recipe was observed. This explained the range of etch rate listed for W under the 10 sccm and 20 sccm NF 3 columns. The original recipe generally led to a 732

higher etch rate. The optimized recipe was later developed to minimize the film stress. At 27 mTorr, 2.1 kW, 188 W bias and 123 OC, W stress became 500 MPa with resistivity of 18 gohm-cm. The reflectivity stayed at 45%. No pure NF 3 etch rate data for Mo could be obtained because of measurement uncertainties introduced by etch residue. At 20 sccm C12 and 20 sccm NF3 , the variation of W etch rate and its uniformity as a function of substrate preheat temperature (K), sputter pressure (mT), rf power (kW), and bias power (W) are shown in Fig. 2. Different sputtering conditions might lead to different film microstructures and thus cause etch rate variations. The range of temperatures used was low compared with the melting point and thus no difference in phase or grain structure was expected. The increase in etch rate vs temperature might be due to increased outgasing from the substrate holder fixture and possible impurity incorporation into the W film. Similarly, higher pressure might lead to higher degree of Ar incorporation into W. Lower density thus would lead to a higher etch rate. Similarly, increased bias might lead to more energetic bombardment resulting in purer film or higher density and lower etch rate. These arguments were in agreement with the resistivity variations. But further microstructural analysis is necessary before final conclusions can be drawn. The effect of NF 3 addition can be summarized for etch rate in Fig. 3 and for selectivity in Fig. 4. There was a synergistic effect for W etch rate so that mixed Cl and F got higher etch rate than that in either pure gas. But etch rate for oxide or resist with different amounts of added F stayed the same as in pure NF 3. Therefore the W selectivity to resist or oxide reached a maximum of 1.4 at 20 sccm C12 and 20 sccm NF3 . The Mo result were worse in terms of etch rate and selectivity. The optical emission spectra in Fig. 5 show a clear rise in the N signal at 337 nm for blanket W wafer vs oxide, but not as significant an increase for blanket Mo. The corresponding end point curve at 337 nm for patterned W interconnect showed an end point starting at 1 min and completing at 1:15. This rise in the N signal helped support the theory that N was consumed in passivating the newly exposed metal sidewall until oxide is exposed at the end of etch. The etch profile of Mo was found slightly positive while W was vertical. The cross sectional view under SEM showed a vertical W profile from 25 to 100% over etch and changing to slightly positive slope at 150% over etch (Fig. 6). Figure 7 shows the vertical wall and clean etch surface after 100% over etch. Such profile was independent of feature size from 3 to 0.6 micron. The thinner resist on top of the 0.6 micron line was due to developing prior to etch. The profile also remained vertical over a wide window of rf power

733

Table 1

Gas RFWatil W WM S102 Resist

The summary of MIE etch rate of W, Mo, SiO 2 and resist for different gases at the rf values shown.

All SiC14 1 K-2K 500-1K 300-600 500-1 K

1900-3500

3500

All C12 /+10cc NF3 /+20cc NF3 /+30cc PIF3 All NF3 500-1500 500 500 500 500 420-1800 2940-4950 2870-3920 2530 2190-4900 270-1300 1970 2380 2100 1600 170-900 1140 1120 1050 2730 1530-4300 3024 2860 1 1 90 900

44.5

-

4600

3400-

8

4400-

4

7.5

4200 3300

3.5

T

/

4000

-

3

U-ER 310

/

3600-

ETCH RT2

\U-ERI

_/

2

5 4.5

3000

250 300 350 400 450 500 550 600 650

4 n

20

40

60

80 PP•SS

TEMP

8

8 I -•= _1-ER =ErCH RT __

44006

i-

7/

5

4000 3800

4 3600 3 1.5

2

2.5

100 120 140

4800 4600-

7

1

5

ETCHR-

3200

0.5

6.5 \6--I-

3400

,5

3000

7

"

38003200

Z

N /

/

7-

7 6.5

K

-If

5 -50

0

50 100 150 200 250 300 350 1BIAS

Fig. 2 The W etch rate dependence on sputtering (a) temperature (K), (b) pressure (mTorr), (c) power (kW) and (d) bias power (W).

734

6 5.5

3400

3

7.5

0

10

10

NF3 ý.

20

-10

50

40

30

NF3 cc

50

40

30

20

10

0

Fig. 4 The W and Mo etch selectivity to resist and oxide as a function of added NF 3 to C12 at 40 sccm total flow.

Fig. 3 The etch rate of resist, W, Mo and oxide as a function of added NF 3 to C12 at 40 sccm total flow. IMTEMSITI (Q)

Sj02 MOLY TUNGSTEN

0.610

Z90

360

376

366

356

346

336

3Z6

316

386

(um) WAVELENGTH

(Y)

60

68

r

46 26 0 0:

0:20 68

S.

0:40

40 26

.

.

.

]

1:'

I

•

*

I

1:28

I

I r

'

,

I

I

I

:b4

Fig. 5 The emission spectra of (a)oxide, Mo and W, and (b) the associated W end-point curve at 337 nm, for 20 scem C12 and 20 sccm NF3 etch. 735

1 min 15 sec

2 mins

2 mins 30 sec

Fig. 6 Scanning electron micrographs showing that tungsten lines maintain vertical profiles at 25% and 100% over etch and become slightly positive at 150% over etch. I

A A A Al (a) 3 Micron

(b) 1 Micron

AAA (c) 0.8 Micron

(d) 0.6 Micron

Fig. 7 Tungsten lines maintaining vertical profile for features from 0.6 to 3 g.

736

(250-650 W) and cathode temperature (10-65 OC). Better selectivity could be obtained at higher temperature and lower power. Based on the better selectivity, the vertical profile, and the associated negligible CD loss, W was chosen as the Ml and M2 material over Mo. In addition, a lkW initiation step was added to ensure removal of resist residue or native oxide and prevent 'grass' formation. The 20 sccm C12 and 20 sccm NF 3 etch recipe was successfully implemented to define the double-layer pattern as shown in Fig. 8. Different adhesion layers were found to show little effect on etch time or profile.

Fig. 8 The top and cross-sectional views of the double-level W interconnect structures, showing clean etch and good step coverage.

737

CONCLUSIONS A viable MIE process for double-layer W interconnect with vertical profile, reasonable etch rate, and selectivity to oxide and resist has been developed. The combined NF3 and C12 chemistry was simple to run and yet provided adequate end point detectability. The best selectivity to resist was 1.4 using 20 sccm C12 and 20 sccm NF3 . The range of W sputtering conditions we used had a 30% effect on W etch rate. We believe that the selectivity could be nearly doubled if we choose not to minimize W film stress but to maximize the W etch rate instead. With an adhesion layer of 30 nm TiW, acceptable M1 to M2 contact resistance was achieved. Good etch profile was achieved independent of feature size, and with a very big process window in terms of rf power, temperature and over etch time. ACKNOWLEDGEMENT This work was performed under the auspices of the U. S. DOE by LLNL under contract no. W-7405-Eng-48. REFERENCES [1) M.E. Thomas, M.P. Hartnett, J.E. McKay, A.K. Kapoor and J.D. Chinn, in 1988 IEEE V-MIC Conf. Proc., 183 (1988) [21 D.S. Fischl and D.W. Hess, J. Electrochem. Soc., 134, 2265 (1987) [3] W.M. Greene, D.W. Hess and W.G. Oldfam, J. Vac. Sci. Tech., B6, 1570 (1988) [4]

D.W. Hess, Solid State Techno., 4/88, 97 (1988)

[5]

R. Rossen, Microelectronic Manufacturing Techology, 14, 17 (1991)

[6]

F. Hawley, A. Levi, G. Vasche, J.M. Caywood, B. Houck, J. Boyce and L. Tso, in 1988 IEEE V-MIC Conf Proc. 142 (1988)

[7] L. Dori, A. Megdanis, S.B. Brodsky, M. Arienzo and S.A. Cohen, Thin Solid Films, 1931194, 501 (1990) [8] L. Krusin-Elbaum, M.O. Aboelfotoh, T. Lin and K.Y. Aln, Thin Solid Films, 153, 349 (1987) [91 P. Collot, B. Agius, P. Estrache and M.C. Hugon, J. Vac. Sci. Tech., A6, 2319 (1988)

738

SELECTIVE ELECTROLESS METAL DEPOSITION FOR VIA HOLE KILLING AND CONDUCTOR PATTERN FORMATION IN VLSI MULTILEVEL INTERCONNECTION STRUCTURES Valery M. Dubin

Minsk Radioengineering Institute, Minsk, BSSR* The selective electroless Ni-Cu deposition process has been investigated for via hole filling and conductor pattern formation in VLSI multilevel interconnection structures. Cu was added to Al-Si in order to deposit Ni-Cu on AlSi-Cu lines without any activation step and obtain a good selectivity. It was observed that a 0.2 pm Ni-Cu overcoat on a 0.5 pm Al-Si-Cu lines increase corrosion resistance, suppress hillock formation and decrease resistance of interconnections. The Ni-Cu was deposited into via holes on Ni-Cu overcoats of Al-Si-Cu lines without any activation. Via holes in a 1.5 pm polyimide layer were filled by Ni-Cu to the top surface to give completely planarization of interconnections. Good contact resistance has been also obtained without any annealing by measuring the via chain resistance. For comparison selective electroless Ni deposition on Al-Si with Pd activation was also investigated. INTRODUCTION With the continued decrease in device dimensions and increase in scale of integration, modern VLSI (very large scale integration) chips often contain more than one million transistors. As a result, multiple layers of metallization are needed to provide interconnections for these devices. The surface topography created by multiple deposition and etching steps in fabricating the interconnection pattern presents a serious problem for subsequent processing. One of the most challenging issues is the step coverage at via holes because the via holes are not only small in size, but also have nearly vertical sidewalls. Therefore, a via hole filling process is indispensable to achieve a high reliability and a high density of multilevel interconnection structures. W,Pd,Ni,Co,Cu are used to fill the contact holes and via holes in dielectric layers, such as Si02, phosphosilicates glass, borophosphosilicate glass and polyimide [1].

739

The reliability of multilevel metallization also depends on conductor pattern formation process. Because of their favourable properties (low resistivity, good adhesion to SiO, good contact resistance to Si), aluminum and its alloys (Al-Si, Al-Cu, Al-Si-Cu) are widely used as interconnections in manufacturing VLSI circuits. Important problems encountered with aluminum metallization are electromigration, the growth of hillocks during heat treatment and corrosion. Besides, the aluminum surface oxidizes very easily and the contact resistance between the different levels of interconnection becomes very high. In order to improve the properties of aluminum interconnections formed by the conventional processes, the aluminum lines are overcoated with a more reliable material. Refrectory metals or refrectory metal silicides are widely used to improve the current carrying capability, increase corrosion resitance of Al patterns, suppress hillock formation on Al surface and obtain a low contact resistance between different levels of aluminum interconnections [ 2, 3 ]. Relatively few metal deposition processes exist for coating the aluminum films and fill the via holes. One very attractive approach is the selective electroless metal deposition. The electroless metal deposition is potentially a much simpler and less costly process in comparison with other metal deposition processes (vacuum evaporation, sputtering, chemical vapor deposition). The selective electroless metal deposition (with Ni,Co or Pd) has been studied for VLSI multilevel interconnection structures as an alternative to the selective CVD W process [ 1, 4 ]. In these previous studies Ni was selectively electroless deposited on Al after Pd activation. The present paper describes a proces for selective electroless Ni-Cu deposition without any activation step for via hole filling and conductor pattern formation. For comparison, the selective electroless Ni deposition on Al with Pd activation was also studied. EXPERIMENTAL Substrate Preparation. - The substrates used in this study are thermally oxidized 100 mm diam silicon wafers. A 0.5 pm thick Al-Si (1.0 weight % Si) layer and a 0.5 pm thick Al-Si-Cu (1.0 weight % Si and 0.5 weight % Cu) layer were deposited on the wafer surface by a convential sputtering process. The Al layer was patterned with standard photolithography and plasma etching process. The minimum pitch of the metal pattern used in this work is 1.5 um. These samples were then used to study electroless Ni-Cu and Ni deposition on Al, Al-Si and Al-Si-Cu conductor lines. The 740

dielectric layers used in this study were silicon dioxide and polyimide. A dielectric layer with a thickness of 0.80.85 um was deposited on the top of the conductor patterns by a low temperature CVD process. Polyimide (AD 9103) was spun at 6000 rpm onto the conductor patterns on SiO /Si wafers. The samples were subsequently cured by heating to 380 0C for 0.5 hour in a nitrogen-purged oven. A dielectric layer of 1.5-1.6 pm thick polyimide was formed. Via holes of 1.2 pm minimum size were formed in the dielectric layer using standard photolithography and plasma etching. These wafers were then used to investigate via hole filling using selective deposition of electroless Ni or Ni-Cu. For contact resistance measurements, a second Al-Si layer of 0.9-1.0 um thick was deposited on the wafers after via filling. The second Al layer was then patterned using standard processes. The via chain resistance was determined by standard electrical measurements. ComPosition of solution. - Aluminum surfaces are not catalytically active for Ni deposition. Therefore, palladium is often used for surface activation [ 1 3. The composition of a typical Pd activation solution used here is given in Table 1. Many different compositions of solutions for electroless Ni and Ni-Cu deposition have been tested. The compositions of Ni and Ni-Cu solutions giving the best results for conductor pattern formation and via hole filling are presented in Table 2 - Table 4. RESULTS AND DISCUSSION a.Conductor pattern formation. The selective electroless Ni deposition process with Pd activation was used to clad the aluminum lines. It was observed that the grain sizes of the Ni films range from 0.2 pm to 0.5 pm. However, undesired Ni deposition between Al and Al-Si lines was also found. Thus the dielectric surface (SiO ) between the aluminum lines was also activated by Pd deposition. Table 1. Composition of a Pd deposition solution Chemicals

Concentration (ml 11)

PdCl?

0.2 g

HCI

1

Glacial acetic acid

500

HF (50:1)

250

741

Table 2. Composition of a solution for electroless Ni deposition [ 5 ]. Chemicals

Concentration

NiCI, 6HO

0.13

NaHPO, HO

0.1

sodium citrate

0.37

(mol 1"1)

NHCI

0.93

NH40H

Adjust pH to 8.5-9

Table 3. Composition of a solution for electroless Ni-Cu deposition on Al lines ( 6 ]. Chemicals

Concentration (g 1-1)

NiSO4 7HO

50

CuSOL 5HO

0.8

NaHPO, HO

15

citrate

acid

50

NH4CHCOO 3HPO

40

NH40H

Adjust pH to 8.5-9

Table 4.

Composition of a solution for electroless

Ni-Cu deposition for via hole filling [ 7 ] Chemicals

Concentration (g 1"1)

NiCl, 6HO

25

NaHPO, HO

25

NaCHCO0

3HO

5

glycine

30

cystein

0.02

CuS04 5HO

0.25

NH4 OH

Adjust pH to 5.0-5.5

In order to discuss how the dielectric surface becomes activated we will simulate the experimental conditions during this deposition. The potential distribution between

742

the Al lines on a dielectric layer (SiO2 ) can be estimated using Poisson equation

S+ ax 2

_ 2 ay

_

-_I

e'-e

P (X)

(1)

where c0 is the permittivity in vacuum, e is the dielectric constant, p. is the fixed oxide charge density. The solution of equation ( 1 ) in this case is described in detail in Ref. 8. The calculated potential between Al lines is shown in Fig. 1 for various fixed charge values in the dielectric layer and for various values of Al line potentials.

1

0.5

i

CD

0

A V

0

0.5

1

(y 1 0-6 M) Fig. 1. Distribution of the electrical field between Al lines on a dielectric layer. a)-h=10"6 m, 1=10-6, p =10-4 q 6 m"2 V=5V; b)1-h=10" M, 1=10 6 M, p q M-=10" V=-5V; c)6 6 h=10" M, 1=10. M, p'=10"4 q m"2, V=0V'9; d) -h=10"9 m, 1=10-6 m, ps=10"4 q m"2 , V=-IV. The symbols denote: h - thickness of Al lines; 1 - distance between Al lines; p - the fixed charge in dielectric layer; V - potential of Al line. 743

It is commonly accepted that SiO has a positive fixed oxide charge. But it can be seen from Fig. 1, that if the potential of the Al lines is negative the potential between Al lines on the SiO2 can also be negative (Fig. lb and Fig. id). Thus positive Pd ions can be adsorbed on the SiO2 surface having negative potential and be reduced. This may occur in the aqueous solution used for Pd deposition. Because of Al dissolution, the Al lines have negative charge. The Al surface is not catalytically active for Ni deposition. Since a Cu surface is catalytic for Ni deposition with sodium hypophosphite as a reducing agent [5], this process can be simplified by using Al-Si-Cu alloys as catalytic surfaces for Ni deposition without any activation step. Figure 2 shows Ni-Cu deposition on Al-Si-Cu without activation step. Cu was added to the Ni solution in order to increase the corrosion resistance of the deposited film, decrease the grain sizes and obtain a more (also without Pd smooth surface [ 6 ]. In this case activation of Al surface) no Ni-Cu deposition between AlSi-Cu lines on dielectric surface was found. Hillock formation on Al-Si-Cu lines was observed after 510 0C annealing during 30 min in N2 atmosphere. Reduced hillock formation on the Al lines was obtained

Fig. 2.

Al-Si-Cu lines with Ni-Cu overcoats. 744

with a 0.1 pm thick Ni-Cu overcoat. With a 0.2 tim Ni-Cu layer on a 0.5 pm Al-Si-Cu line complete suppression of hillock formation was obtained even after 510 0C heat treatment for 120 min. Measurement of the resistance of Al-Si-Cu/Ni-Cu conductor lines show that after an annealing cycle to 450 OC for 30 min in N atmosphere the resistance of a 0.5 pm AlSi-Cu lines with a 0.2-0.3 pm Ni-Cu overcoat was reduced by a factor of more than 1.2-1.3. The decrease in resistance of the Al-Si-Cu/Ni-Cu system after annealing can be explained as due to recrystallization of Ni-Cu at this temperature [ 5 ]. The investigation of the corrosion resistance of AlSi-Cu/Ni-Cu conductor lines shows that the Ni-Cu overcoat improved the corrosion resistance of Al-Si-Cu conductor line. No corrosion was observed after a treatment of AlSi-Cu/Ni-Cu lines in 60 0C hot water for 200hr. It was found that under these conditions the aluminum was completely consumed in the presence of small amounts of halide contamination. b.Via hole filling. Via holes were patterned in dielectric layers such as CVD Sio2 or thick polyimide layer by standard photolitography and plasma etching processes. The use of the thick polyimide layers (the thickness is more than 1 pm) makes it possible to achieve planar surfaces, to improve the dielectric and mechanical properties of the polyimide layers and to increase the frequency range of VLSI circuits. In order to fill the via holes (the nominal sizes are from 1.5 pm to 5 pm) in thick polyimide layers (the thickness is about 1.5 pm), the selective electroless NiCu and Ni deposition was applied. After Pd activation and selective electroless Ni deposition into via holes it was observed that the deposited Ni is over 0.5 pm thick with the edge somewhat thicker than the middle. If the electroless Ni deposition into via holes is continued for a long time the Ni film grows also on the dielectric surface. If via holes are situated very close to each other accidental connections between the via holes are observed. The activation of the surface in the via holes can be avoided if the Ni-Cu overcoats of Al lines are used. This is because of the Ni-Cu surface being catalytic for electroless Ni deposition. Copper ions and surfactant (cystein) were added in the Ni solution to obtain very smooth Ni-Cu surfaces and to decrease the lateral growth of Ni-Cu pillars. It was observed that the rate of Ni-Cu deposition was 0.25-0.3 pm/min with pH=5-5.5 and tempera745

ture 90-95 0C. Via holes were filled to the top surface to give a completely planar surface (Fig. 3).

Fig.

3. Via holes filled by Ni-Cu.

In comparison with selective Ni deposition on Al surfaces into via holes after Pd activation, the thickness of Ni-Cu on Ni-Cu surfaces in the via holes is larger in the middle than at the edges of the via hole. Ni-Cu pillars were obtained when the electroless Ni-Cu deposition process was continued for a long time. No connections between pillars in via holes was found. c.Via chains. Via chains are formed by two Al layers. The first level of Al-Si-Cu pattern is connected to a second level of Al-Si pattern through a via hole, the second level of Al-Si pattern is connected to another first level of Al-Si-Cu pattern through a second via hole. A via chain pattern of any desired length can be formed by repeating this structure. In this work, the via holes were filled by selective electroless Ni and Ni-Cu deposition before the deposition of second Al layer. For selective electroless Ni deposition into via holes the palladium activation process of Al was applied. For selective electroless Ni-Cu deposition into via holes the overcoat of first level of Al-Si-Cu pattern was applied, the Ni-Cu was deposited into via holes without any activation process. 746

Figure 4 shows a wafer surface after the via holes Al-Si-Cu layer was 0.5 were filled with Ni-Cu. The first gm thick with a 0.2 gm thick Ni-Cu overcoat. The polyimide layer was 1.5 pm thick, the second Al-Si layer was 1 pm thick. As can be seen from Fig. 4, these vias were filled to the top surface to give a planar surface of interconnections.

Fig. 4. Two-level interconnection structure with via holes filled by Ni-Cu (the polyimide layer was removed) The resistance of the chains was measured by electrical probing; the measured resistance for via holes filled by Ni-Cu is very low before annealing. After annealing the resistance is insignificantly increased. This corresponds2 to a specific via resistance of less than 1 10.9 ( cm The before and after annealing (450 OC, 30 min, N,). measured resistance for via holes filled by Ni is very high before annealing, after a 450 °C nitrogen annealing cycle resistance value of less than 150 m R per via has been obtained.This corresponds 2 to a specific via resistivity of less than 1 10.8 R. cm . CONCLUSIONS Selective electroless Ni-Cu deposition process has been studied for via hole filling and conductor pattern formation in VLSI multilevel interconnection structures. Cu 747

was added to Al-Si in order to deposit Ni-Cu on Al-Si-Cu without any activation step and obtain a good selectivity. It was observed that Ni-Cu overcoats of Al-Si-Cu lines increase corrosion resistance, suppress hillock formation and decrease resistance of interconnections. The Ni-Cu was deposited into via holes on Ni-Cu overcoats of Al-Si-Cu lines without any activation step. Ni-Cu filled vias with a planar surfaces were obtained. Good contact resistance was measured also without annealing. ACKNOWLEDGMENTS Many discussions with J.Bottiger,

N.Karpe

and K.K.Larsen

are gratefully acknowledged. Thanks are due to V.Smolskij for assistance with respect to the potential distribution calculation. *Present address: Institute of Physics, Aarhus, DK-8000 Aarhus C, Denmark.

University

of

REFERENCES

[1) C.H.Ting and M.Paunovic, J.Electrochem.

Soc.,

136, 456

(1989).

[2) E.G.Colgan, Materials Science Reports,

5,

1 (1990).

[3] V.Smith, H.Norstrom, U.Wennstrom, A.Johansson, I.Engstrom and Z.Toth-Pal, J.Vac.Sci.Technol., 8, 499 (1990). [4] C.H.Ting, M.Paunovic, P.L.Pai and G.Chiu, J.Electrochem. Soc., 136, 462 (1989). [5] V.V.Sviridov, "Electroless metal deposition in an aqueous solutions", Buelorussia University, Minsk (1987). [6) I.Z.Prebish, in "Hard and wearproof electroless and electroplating coats", MHNTP, Moscow, p.85 (1984). [7]

Author

certificate

No

1110818

(USSR),

in

B.I.,

32

(1984).

[8] A.A.Samarskij, Moscow (1977).

"The theory

748

of circuits",

Science,

NOVEL METHOD FOR PREVENTION OF PARTICLE DEPOSITION IN WET LSI PROCESSES A.Saito, K.Ohta, Y.Takahara and H.Oka Production Engineering Research Lab. Hitachi, Ltd., 292 Yoshida-cho Totsuka-ku, Yokohama, 244 Japan ABSTRACT A novel method to prevent particle deposition by controlling the zeta potential of the particles has been developed. The repulsive force between a particle and a substrate is increased when the zeta potential becomes low. The zeta potential control is realized by adding organic solvent to the solution. 2-amino ethanol is found to be very effective for changing the zeta potential of hydrophobic particles and that of hydrophilic particles using nonionic surfactant together. The prevention of particle deposition is demonstrated for 0.2 - 1.0 pm-size polystyrene particles. INTRODUCTION As semiconductor devices are manufactured more finely, deposition of smaller particles deteriorates production yield and device performances. Simulation of particle deposition[l,2], which is based on a particle-diffusion model, indicates that small particles very easily adhere to Si wafers in wet LSI processes. As even 0.05 pm-size particles would affect the production yield of a 16M bit DRAM, it becomes very important to prevent particle deposition in wet processes. We have clarified that particle deposition depends on a balance between the van der Waals force and repulsive force of electrical double layers between a particle and a substrate[1,2]. The increase in the repulsive force induces the suppression of particle deposition. The repulsive force can be changed by controlling the zeta potential, which is related to the electrical double layer. The zeta potential of particles was changed with the pH of the solution[3] or by adding ionic surfactant to the solution. But when the ionic strength in the solution becomes too high, particles easily adhere to the Si wafer. Therefore we can't use such ionic materials. In this paper we investigated the effect of adding polarized materials such as organic solvent.

749

EXPERIMENTAL 0.2 -1.0 pm-size polystyrene particles (Dow chemical), 1 pm-size Si particles, SiO2 particles and Fe particles (Ko-jundo kagaku) were used as dispersed particles, and ntype Si wafers (Shin-etsu Kagaku) as deposited substrates. Organic solvents (alcohols, aldehydes, organic acids, amino-alcohols and fluoric-alcohols) were used as polarized materials. Each solvent was added to ultra clean water containing dispersed particles. The concentration of solvent was 0.00001 - 10%. Nonionic surfactant (Emulgen 120, Kao Corporation) was used for hydrophilic particles together witl organic solvent. The concentration of surfactant was 10-- mol/l. The zeta potential of the particles was measured by electrophoresis[4] using LASER ZEE TM Model 501 (Pen Kem). The particle deposition experiment was performed as follows. A Si wafer was dipped into ultra clean water including 5 x 10-3 mol/l NaCI with dispersed polystyrene particles. Since 0.2 -1.0 pm-size particles don't adhere to a Si wafer in ultra clean water stationarily, the experiment was made in such ionic strength. After dipping the wafer for 5 minutes, the wafer was dried by spinning. The number of particles deposited on the wafer was measured using an optical microscope. The same treatment was made after adding the organic solvent to the water. RESULTS AND DISCUSSION Si particles pre-cleaned by dilute HF showed zeta potential of -23,7mV, The zeta potential was changed

by

Table 1

Zeta potential change by adding organic solvent Additive

Zeta potential (mV)

adding

various organic solvents to water as shown in Table 1. Alcohols were especially effective. The zeta potential of the Si particles was changed from -23.7 mV to -47.3 mV by adding ethanol with 1% concentration. Si wafer and most of the particles show negative zeta potential, therefore the repulsive force increases

Ethanol

-4

7 .3

Acetaldehyde

-2

6 .7

Acetic acid

- 3 1 .1

Methyl

-3

5.5

acetate None

750

- 23.7

when the zeta potential becomes lower. Table 2 shows the zeta potential change various adding by Ethanol or alcohols. more was 2-propanol to change effective the zeta potential than 1-propanol or Ibutanol. The electron polarization in these molecules was thought the zeta to affect the But potential. is momentum dipole almost the same for as alcohols these The shown in Table 2. distribution of elecwas density tron obtained by ab-initio orbital molecular calculations in order to consider the mechanism of zeta potential The results change. are shown in Figure 1. are Hydrogen atoms omitted to be displayed.

Table 2 Additive

Zeta potential change by adding alcohol Zeta Potential

Dipole momentum

(mN)

Methanol

1.66

-40.5

Ethanol

1.68

-47.3

ProPaaul

1.66

-4 8.8

2-

1 .6 8

-- 4 6 .5

1 .6 8

-2 24. 1

1.63

-2

PrePanel 1Butanol 2-

1.4

Butanol 2 3 .7

None

-0. 74 -0.74

-0 74

"0.00"

49

+0.1

shear plane

-0.32

-0.49 0

-0.5

particle surface zeta potential -47.3mV

-28.8mV ep

n

-24. lmV

-46.5mV

banol2-propanol

Fig.1 Adosorption model of alcohols on particle

751

The value in this figure means elecCH for a neutral tron density. The value 0.8 4 N atom is zero and the value for a high negative. electron-density atom is C Figure I shows the adsorption model of alcohols onto a particle. The ethanol .74 or 2-propanol has a high electronH density atom on the shear plane (slip plane), which is the border between a moving particle and the liquid. This Fig.2 2-amino ethanol result is reasonable since the zeta potential is an electric potential in the shear plane. The calculation was applied to materials which have N or F atoms with high electron negativity. It was clarified that the N atom in 2-amino ethanol had a higher electrondensity (-0.84) than each atom in the ethanol(Figure 2). This means that 2-amino ethanol can be more effective. When the 2-amino ethanol was added, the zeta potential of the Si particles was measured to be -62.lmV, which was the lowest value obtained in this study. Various particles affect the production yield of semior Fe(material of conductor processes, such as Si, SIO producing apparatus). The zeta potentlai of those particles was measured when 2-amino ethanol was added(Table 3). The zeta potential of hydrophobic particles such as polystyrene or HF treated Si was changed by adding 2-amino ethanol. However the zeta potential of hydrophilic particles such as Si(not treated by HF) or Fe was scarcely changed. This Sio adsorbed on the particle is because 2-amino ethanol wasn't surface. Therefore we used nonionic surfactant in order to The experiadsorb 2-amino ethanol on the particle surface. mental results are shown in Table 3. The zeta potential of hydrophilic particles was changed by adding 2-amino ethanol and nonionic surfactant. Table 3

None

Zeta potential change for various particles (mV) Fe S i 02 S i Bare-Si* SPoIYstyrene -- 2 2 ,1 -3 7.8 -4 3.1 -2 3.2 -50.4

2-Amino ethana4 2-Amino ethanol+

-7

1.3 -

-6

2.1 I

Noninnic surfactant

-5

6.0

-7

0.1

-45.1 -7

2.3

I

* S1 treated by HF

752

-3

0,2

-5

7.6

The effect of 2-amino ethanol on particle deposition was evaluated experimentally. Figure 3 shows the relationin the solution and the ship between the ionic strength number of depositing particles in the case of 0.2 pm-size polystyrene particles. Particles adhered to the Si wafer at mol/l. But when 2-amino ethaabove 10 an Ionic strength nol was added(•O] moi/l), particles were able to adhere The relationthe between ship and size particle the number of deposat particles iting the ionic strength is 5 x 10 - mol/ shown in Figure 4. By adding 2-amino 5 mol/l), ethanol(10the number of deposparticles iting became less than one tenth.

M c

0

Ionic Strength (mol/1) Fig.3

Relation between ionic strength and depositing particles 2-Amino Ethanol

o:10-5mol/I

A:O

Ct

3

Ionic Strength 5xO- moW/ U

'A 0.51

0ý5 Particle Size (pm)

0

Fig.4

1

Prevention of particle deposition by zeta potential control 753

CONCLUSION The zeta potential of particles can be changed by adding organic solvent to water. Alcohols were especially effective for changing the zeta potential. The effect of zeta potential control by adding 2-amino ethanol was demonstrated in this experiment. The production yield of LSI would be improved by using "Zeta potential control methods".

REFERENCES l)A.Saito et al.:Extended Abstracts of the 21st Conference on Solid State Devices and Materials, p409-412 (1989) 2)A.Saito et al.: submitted to Japanese Journal of Applied Physics 3)I.Ali et al.:SEMICONDUCTOR INTERNATIONAL APRIL 1990, p92-95 4)A.Delgado et al.: Acta Polymerica,37, p361-364 (1986)

754

LOW-TEMPERATURE IN-SITU NATIVE OXIDE REMOVAL USING ANHYDROUS HYDROGEN FLUORIDE Pushkar P. Apte, Krishna C. Saraswat Center for Integrated Systems, Stanford University, Stanford, CA 94305 and Mehrdad M. Moslehi, Richard Yeakley Semiconductor Process and Design Center, Texas Instruments, Dallas, TX 75265

ABSTRACT A new low-temperature, gas-phase cleaning technique using Anhydrous Hydrogen Fluoride that removes native oxides and carbon in situ prior to film deposition has been demonstrated. The technique is simple and manufacturable, and it is selective in that it removes surface oxides grown by both air and wet chemical cleans, but leaves thermal oxides intact. The efficacy of the technique is shown by both physical analysis and the growth of specular epitaxial silicon. Keywords: Anhydrous Hydrogen Fluoride, in situ dry cleaning, lowtemperature cleaning, native-oxide removal, silicon epitaxy.

INTRODUCTION Advanced semiconductor technologies with sub-micron geometries impose stringent requirements on Ultra Large Scale Integrated (ULSI) device manufacturing. This is manifest in the increasingly exacting demands on the quality of films, on the tolerances for dopant diffusion and on selectivity of deposition/etch processes. The sensitivity of film quality to the atomic-level cleanliness of the surface immediately preceding film deposition underscores the need for effective in situ cleaning. Long process sequences and the need for precisely tailored dopant profiles combine to restrict the thermal budget of individual steps, which requires that both cleaning and deposition be done at low temperatures. The broad objective of ULSI-compatible cleaning research is then the search for an in situ, low-temperature, selective and manufacturable process. This work demonstrates a new dry cleaning technique using Anhydrous Hydrogen Fluoride (AHF) that meets all these challenges effectively, in that it is performed in situ, its operating temperature range is 325-750°C, and it selectively removes native oxide while leaving thermal oxide untouched. Furthermore, the technique is simple to implement and can remove oxides grown by both air and standard wet cleans, which enhances its adaptability to the manufacturing environment. 755

MOTIVATION The main sources of wafer contamination are impurities introduced by the equipment, the ambient, the reactive gases and the wet chemicals. The main contaminants of an exposed wafer surface include a thin layer of non-stoichiometric silicon oxide, metallic ions, organics and particulates. The traditional approach is to remove these ex situ using a series of wet chemical cleans and rinses. However, as processing moves into the ULSI domain, it is becoming increasingly evident that wet cleaning presents significant problems. One is that precise process control is difficult to achieve. Another is the incompatibility with modular equipment such as cluster tools and single wafer processors: incorporation of liquids in this environment is neither easy to implement, nor desirable. A corollary is that in situ wet cleaning is not generally feasible. Another significant problem is that aqueous chemicals may not penetrate sub-micron features due to surface tension. It may therefore be inferred that dry cleaning is of critical importance for ULSI technology. While the goal is to replace the entire wet cleaning sequence with dry processes, native oxide removal represents the most immediate challenge, since even a Si surface which has been stripped of oxide with an HF dip will regrow an ultrathin native oxide layer within a short time. The key factor for oxide growth is the partial pressure of H20 and 02 in the ambient. It has been shown that a critical value for the partial pressure exists for different temperatures [1, 2]; above which an oxide layer will form. This information can be used to maintain an oxide free surface in a vacuum system. The regrowth of a surface oxide layer during storage has also been studied by several workers. The results differ, since the rate and ultimate thickness of the regrown layer are a function of the ambient that the wafers are exposed to. For instance, growth of a monolayer of oxide has been reported to occur within one hour [3, 4]. On the other hand, wafer storage in a single wafer polycarbonate package immediately following an HF dip took a few days for a monolayer to form, with the growth rate increasing after a week [5]. Similar results were obtained in an ambient with moisture restricted to less than 0.1 ppm [6]. While the native oxide can be controlled using special facilities, the complete ex situ elimination of oxide contamination is difficult. Also, it is sometimes desirable .to leave a passivating oxide layer on the wafer to reduce other contamination during wafer transport and storage. Thus the development of an in situ native-oxide removal technique is imperative.

IN SITU DRY CLEANING TECHNIQUES These generally fall into three broad categories, namely use of Ultra High Vacuum (UHV) systems, energetic beam techniques and thermal-chemical techniques. Epitaxial growth of silicon at temperatures of 825°C has been demonstrated in a UHV system [7]. The basic idea in this approach is to hold the H2 0 and 02 in the ambient to levels below the critical levels determined by the previous studies [1, 2]. However, significant system complexity is introduced by the requirement of a base 756

pressure of 10'

Torr. Energetic beam techniques may be sub-divided into physi-

cal and chemical techniques. The former have been demonstrated using an Ar ion plasma [8, 9] at temperatures of 710-7500C. Physical sputtering is constrained by

the limited window within which the clean is effective: too little results in insufficient impurity removal, while too much causes lattice damage. Energetic beams have been also used to enhance the chemical reaction leading to oxide removal. For instance, photochemical cleaning using Ultraviolet(UV) light irradiation in an H2 ambient [10] has been shown to remove surface oxides. From a manufacturing perspective, UHV and energetic beam techniques suffer from the drawback that they increase system cost and complexity, since they typically require special hardware or custom-made chambers. Also, wafer throughput is usually very low, due to the long cycles required for system preparation and actual processing. Thermal-chemical techniques may be divided into high and low temperature techniques. High-temperature techniques use H 2 or HC1 for their cleaning action. Apart from the obvious drawback of a high thermal budget, additional problems such as faceting for HCl and oxide undercutting for H2 bake limit the use of these techniques in the ULSI domain. Low temperature gas-phase cleaning techniques that have been studied include GeH 4 , NF 3 and HF. GeH 4 cleaning has been found to be effective [11, 121 in removing native oxide, although further optimization is needed. The possibility of Ge incorporation into the subsequent film may limit the process domain of this technique. NF 3 seems to require a relatively high temperature (800°C) post-clean bake [13] to be effective. Also NF 3 is non-selective to the type of the oxide and etches quartz, which would degrade reliability in systems with quartz ele-

ments. Significant effort has been targeted at native oxide removal using the vaporphase cleaning action of HF at room temperature. It has been demonstrated that native oxide removal can be achieved without significant addition of metallic impurities [14, 15]. A regime for the selective removal of native oxides has been identified by Miki et al. [16]. However, it was found that this leads to passivation of the surface with fluorine. High temperature annealing (930°C, 1 hour) and bombardment with Ar ions was unsuccessful in removing the fluorine, and Xe lamp irradiation was needed. Vapor-phase HF cleaning will be discussed later, in the context of contrasting

it with this work.

EXPERIMENTAL APPROACH This work describes the use of a mixture of AHF and H2 for the selective removal of surface oxides in a low-temperature regime, with no moisture added. We do not see any corrosive action of the gas-phase reaction even though the chamber walls, quartz elements and plumbing have not undergone any special passivation treatment. Further, we demonstrate in our results that we do not have any fluorine passivation of the silicon surface. The work was done in a single wafer cold wall reactor, with rapid heating provided by tungsten-halogen lamps [11]. The first set of experiments consisted of testing 757

Table 1: Parameters for a typical AHF clean HF H2 50 sccm 150 sccm

Temperature 325°C

Time 200 sec

Pressure 300 mTorr

Table 2: Oxide etching observed for a typical AHF clean Oxide PSG TEOS Chemical Oxides Thermal Oxides

Extent of Etch (A) 80-100 25-40 3-4 NO ETCH

the etching rate of the AHF clean on wafers with blanket oxides. The types of oxides tested included oxides grown by wet chemical cleans, oxides deposited using tetra-ethyl ortho silicate (TEOS), phosphosilicate glass (PSG), and thermal oxides. The thicknesses were measured immediately before and after the pre-clean with a Prometrix Spectramap machine for all oxides except the thin chemical oxides, which were measured with an ellipsometer. In the second set of experiments, the AHF pre-clean was followed by in situ deposition of epitaxial silicon using SiH 2 Cl 2 and H2, at a temperature of 980'C and a pressure of 5 Torr. Parameters for a typical cleaning step are shown in Table 1. Some out-of-the-box wafers were processed, but all the in situ cleaning and deposition results presented are for wafers that had undergone a wet chemical clean (NH 4 OH:H 2 0 2 ), followed by a rinse and dry cycle, prior to being inserted into the chamber. The efficacy of the clean was evaluated by examining the substrate-film interface with Secondary Ion Mass Spectrometry (SIMS). A control sample that had not undergone any in situ cleaning, and had the Si film deposited under identical conditions as the wafers with the pre-clean, was used as a reference. The quality of the deposited layers was examined by optical microscopy, using polarized light.

RESULTS AND DISCUSSION The extent of etch due to a typical AHF clean on wafers with blanket oxides is shown in Table 2. The fact that the pre-clean has no effect on thermal oxides establishes the selectivity of the pre-clean unambiguously. A variety of temperatures, flows and times tested yielded similar results, indicating that the process window for selectivity is quite large. It should be noted that the chemical oxides grown by wet cleaning are typically only 10-12 A thick, and the relatively small (3-4 A) etch observed may be due to regrowth of native oxide between processing and measurement, 758

I

I.

10 C

I

III'

I

I

FILN

UTiEWAM

SUSSIUM1A

U.

Figure 1: SIMS profiles: (a) control wafer, and (b) pre-cleaned wafer since no in situ thickness measurement technique was available. Chemical oxide removal is demonstrated by specular epitaxy and the SIMS results since, as stated earlier, all presented results for in situ cleaning and film deposition are for wafers that had undergone a wet chemical clean prior to insertion in the chamber. The SIMS profiles for a control wafer that did not have the pre-clean and that of a wafer pre-cleaned according to conditions described in Table 1, are shown in Figures 1(a) and 1(b) respectively. The substrate-film interface is indicated by the impurity peaks. The effectiveness of the AHF pre-clean is underscored by three key features that emerge from a comparison of Figures 1(a) and l(b). Firstly, the oxygen peak is sharply reduced, indicating interracial oxide removal. Secondly, the interracial carbon peak also decreases sharply. This is a unique feature, which has not been demonstrated for most other low-temperature chemical native oxide removal techniques. And lastly, the absence of any significant fluorine at the interface implies that the technique does not face the problem of fluorine passivation. Figures 2(a) and 2(b) are optical micrographs of the films deposited on the control and pre-cleaned samples corresponding to Figures 1(a) and 1(b) respectively. The topography of the film on the control sample is extremely rough, while the pre-cleaned sample shows a smooth film surface. This is consistent with the preliminary observation in white 759

1

10 im

Lim

Figure 2: Optical micrographs of films on: (a) control wafer, and (b) pre-cleaned wafer light of a hazy film for the control sample, as opposed to the clear specular film on the pre-cleaned one. This also highlights the sensitive dependence of Si films on the presence of surface oxide and carbon on the starting substrate. Since moisture- activated 'vapor-phase' HF cleaning has been extensively studied, it forms a logical starting point in the search for possible mechanisms of the AHFbased cleaning described in this work. Recent work has described the vapor-phase cleaning action as being similar to that of aqueous HF, with a condensed surface film of HF/H 2 0 effecting the etch [171. The moisture for this condensed film may either be intentionally introduced or may simply be derived from that present in the background and in the carrier gases. As the etching is incumbent on the formation of the condensed film, the cleaning action in this regime is predicted to not work above 40'C and indeed, this is consistent with experimental observations. Also, selectivity in the vapor-phase regime is due to varying moisture contents of different oxides, which in turn leads to different incubation times for the condensed film. Since our work demonstrates cleaning at temperatures above 300'C, where the formation of a condensed film is highly unlikely, it follows that we are operating in a regime that is different from the vapor-phase one. Experiments are currently in progress to try and identify the mechanism of the technique described in this work. One interesting point is the role of temperature, and the SIMS results of some preliminary experiments are shown in Figure 3. The cleaning conditions were the same as those described in Table 1, with the exception 760

I

I

Figure 3: (a) Oxygen and (b) Carbon profiles for wafers cleaned at different temperatures

761

S

0

U

0

1000

500

1500

Temperature (C) Figure 4: Free Energy vs Temperature for standard HF etching reaction of temperature which, as shown in the figure, was varied for two of the samples. While the direction of the change of the interracial oxygen (Figure 3(a)) and carbon (Figure 3(b)) is the same, a clear trend is not observed, since the impurities increase in going from 3250C to 5750C and then decrease on increasing the temperature to 725°C. It should be noted though, that smooth specular epitaxy was observed on all these samples. While more data points are necessary before attempting an explanation, these initial results underscore some of'the directions that future work must take. For instance, the chemical reaction effecting the clean needs to be established precisely, because Figure 3 can be explained by one reaction moving into different regimes or by different reactions. The most commonly accepted reaction for HF etching is: 4HF + SiO 2 -+ 2H 2 0 + SiF 4 The variation of the driving force of this reaction with temperature is of interest. The plot of free energy vs temperature for this reaction is shown in Figure 4. The free energy curve indicates that thermodynamically, this reaction should be less favored as the temperature rises, which is not entirely consistent with what is observed in Figure 3. The discrepancy could be due to kinetics alone or due to the occurrence of a different reaction. In summary, while further work is needed to establish the precise mechanism of this cleaning technique, its effectiveness has been clearly shown in the epitaxial growth results presented. 762

CONCLUSIONS A new gas-phase technique has been removal of native oxide using AHF. It has therefore suitable for possible adaptation ment. Its efficacy has been demonstrated growth of silicon.

demonstrated for low-temperature, in situ been shown to be selective and simple, and to a semiconductor manufacturing environby physical analysis as well as the epitaxial

ACKNOWLEDGEMENTS This work was supported by the T.I./M.M.S.T. program and S.R.C. We would like to thank Cecil Davis of T. I. for his encouragement.

REFERENCES [1] G. Ghidini and F. W. Smith. J. Electrochem. Soc.:Solid-State Science and Technology, 131, 2924, 1984. [2] F. W. Smith and C. Ghidini. J. Electrochem. Soc.:Solid-State Science and Technology, 129, 1300, 1982. [3] G. Mende, J. Finster, D. Flamm, and D. Schulze. Surface Science, 128, 169, 1983. [4] P. A. M. van der Heide, M. J. Baan Hofman, and J. J. Ronde. Technol., A7, 1719, 1989. [5] D. Graf, M. Grundner, R. Schulz, and L. Muhlhoff. 5155, 1990.

J. Vac. Sci.

J. Apple. Phys., 68(10),

[6] M. Morita, T. Ohmi, E. Hasegawa, M. Kawakami, and K. Suma. Appl. Phys. Lett., 55(6), 562, 1989. [7] B. S. Meyerson, E. Ganin, D. A. Smith, and T. N. Nguyen. J. Electrochem. Soc.: Solid-State Science and Technology, 133(6), 1232, 1986. [8] W. R. Burger and R. Reif. J. Apple. Phys., 62(10), 4255, 1987. [9] I. Nagai, T. Takahagi, A. Ishitani, H. Kuroda, and M. Yoshikawa. J. Apple. Phys., 64(10), 5183, 1988. [10] A. Ishitani, Y. Ohshita, K. Tanigaki, K. Takada, and S. Itoh. J. Apple. Phys., 61(6), 2224, 1987. [11] M. M. Moslehi and C. Davis. J. Mat. Res., 5(6), 1159, 1990. 763

[12] Y. Takahasi, H. Ishii, and K. Fujinaga. Apple. Phys. Lett., 57(6), 599, 1990. [13] G. P. Burns. Apple. Phys, Lett., 53(15), 1423, 1988. [14] C. R. Cleavelin and Gary T. Duranko. Semiconductor International, page 95, November 1987. [15] Daniel J. Syverson and Gary T. Duranko. October 1988.

Solid State Technology, page 101,

[16] N. Miki, H. Kikuyama, I. Kawanabe, M. Miyashita, and T. Ohmi. IEEE Trans. Electron Devices, 37, 107, 1990. [17] C. R. Helms, B. E. Deal, and M. A. McNeilly. to be published in Proceedings Institute of Environmental Sciences, 1991.

764

LOW TEMPERATURE OXIDATION OF SILICON IN AN ELECTRON CYCLOTRON RESONANCE PLASMA D. A. Carl* and D. W. Hess Department of Chemical Engineering and M. A. Lieberman Department of Electrical Engineering and Computer Sciences University of California Berkeley, California 94720 Silicon dioxide was grown on single crystal silicon substrates immersed in low pressure electron cyclotron resonance (ECR) oxygencontaining discharges. Physicochemical and electrical properties of the films grown were correlated to plasma parameters, silicon substrate temperature, applied wafer dc bias, and post-processing metallization treatments. Although silicon oxide films could be grown at rates comparable to thermal (> 900 'C) oxides at temperatures below 500 °C under floating, cathodic, and anodic bias conditions, the ECR oxides with the best thickness uniformity and the best physical and electrical characteristics were grown with anodic (substrate holder positive) conditions. Physical and chemical properties of the anodic oxides were equivalent to those of thermal oxides. When polysilicon was used as the gate material, anodic oxides displayed analogous fixed charge and intrinsic breakdown levels to those of thermal oxides, although low field leakage was apparent in the ECR oxides. INTRODUCTION In order to enhance the low thermal oxidation rate of silicon at temperatures below 900 'C, various plasma techniques have been invoked. Silicon has been oxidized in microwave plasmas (- 15 Pa) with and without an applied bias [1-3], in inductively coupled (- 5 Pa) rf plasmas [4, 5], and in downstream afterglows of high pressure (- 130 Pa) microwave discharges [6, 7]. (The above references and approaches are not intended to be exhaustive; for further, more extensive information,

"Currentaddress:

IBM Corporation, General Technology Division, Burlington, VT 05452

765

the reader should consult available review articles [8-10). Although these methods offered improvements in oxidation rate, the rates in downstream configurations, where oxide damage was reduced relative to in-plasma techniques, were still low. Recently, electron cyclotron resonance (ECR) plasmas have been investigated as potential high ion flux, low ion energy discharge atmospheres wherein oxidation rates comparable to those obtained by thermal oxidation at temperatures > 900 'C can be achieved. Under floating (no external dc or rf bias) conditions in a 0.027 Pa oxygen ECR plasma, silicon oxide growth kinetics were studied as a function of temperature and magnetic field configuration [11-13]. Neither linear-parabolic nor power law kinetics accounted for the observed growth rates. 180 marker studies indicated that the reaction took place at the Si-SiO 2 interface, with a small amount of exchange of 0 with the SiO 2 during oxidant transport. Growth rates under these conditions were low (10 nm in 1 hour at 350 °C), and oxide etch rates in HF solutions were 1.1 to 1.5 times that of thermal oxides. Electrical properties were not reported. A distributed ECR (DECR) system has been used to anodize silicon under a variety of plasma contitions [14]. These systems operate at the same pressure and power levels as conventional ECR systems; however, due to the permanent magnets around the microwave cavity, ion energetics are different as a result of near-wafer magnetic field configurations. In this study, substrate temperature was not controlled; substrate temperature was estimated to be 197 °C. Oxidation rate was a function of wafer position with respect to the plasma stream, roughly tracking ion density or the estimated wafer temperature. Electrical properties of the as-grown oxides were not reported. After gate metallization anneal, the MOS structures had2 2 fixed oxide charge levels of 5 x 1011 cm and interface trap densities of 5 x 101 cmeV'. Mobile ionic charge in these oxides was - 7 x 10'° cm-2, and the mean breakdown field (MBDF) was 7.8 MV cmn'. Etch rates in aqueous HF solutions were not reported. In the present study we describe our investigations of the relationship between ECR plasma parameters, oxidation conditions, and resulting chemical and electrical properties of SiO 2 films. In all cases, we compare these properties to those of thermal oxides grown in dry oxygen at 900 °C. EXPERIMENTAL CONSIDERATIONS The ECR system used in this investigation is shown schematically in Fig. 1. In this configuration [15, 16], a 2.45 GHz CW microwave power supply/matching network was connected by a WR284 rectangular waveguide through a quartz window to the 7.8 cm diameter by 22 cm long stainless steel cylindrical vacuum chamber. No special microwave mode conversion was used. Two electromagnets driven in a

766

mirror configuration established the axial magnetic field required for cyclotron resonance. Single crystal (p-type and n-type 10-15 0 -cm, (100)) silicon wafers 75 mm in diameter were clamped onto an aluminum holder via a retention ring, with the holder 14 cm from the source chamber. The substrate holder contained resistive heating elements, a thermocouple for temperature measurement, and could be electrically floated or dc biased. A 3.2 mm thick quartz plate covered the metal portions of the sample holder and had a 50 mm diameter opening to the discharge centered 7 mm above the wafer. This approach assured that all net dc current flowed through the center 50 mm of the 75 mm wafers. The oxygen plasma was characterized by optical emission, actinometry (with the Ar 750.4 nm emission line as a reference), and Langmuir probes. Prior to oxidation, wafer were cleaned in a boiling sulfuric acid/hydrogen peroxide solution, rinsed in DI water, immersed in buffered oxide etch until hydrophobic, then rinsed in 16 M Q0-cm DI water. Oxidation was performed by first evacuating the ECR system to - 1 x 1 0 4 Pa and the silicon wafer was then heated to the desired temperature. When the desired flow rate and pressure of oxygen were established, microwave power was applied. Oxidations were carried out at pressures between 0.033 and 1.3 Pa and at temperatures between 250 and 450 'C. Oxide film thicknesses were measured by ellipsometry. MOS capacitor structures used either thermally evaporated aluminum or deposited n+ polysilicon as the gate electrode. Polysilicon was deposited from silane and phosphine at 50 Pa and 650 'C, and activated at 850 'C in dry nitrogen for 20 min. Capacitance-voltage (CV) at 1 MHz and current-voltage data were obtained prior to and after a 400 'C forming gas sinter for 30 min. Bias-temperature stress measurements were performed at + /-1 V and 200 'C for 5 min. RESULTS AND DISCUSSION Oxidation Results Figure 2 displays silicon oxide thickness versus time for various microwave powers and substrate temperatures under floating (zero applied) bias conditions. Also shown in Fig. 2 are the oxidation rate data for a dry oxygen thermal oxidation performed at 1 atmosphere pressure and 1000 *C. Clearly, when the power level is at least 400 W, ECR oxidation rates are equivalent to thermal oxidation rates performed at temperatures significantly higher. Furthermore, at 700 W, the ECR oxidation rate is independent of substrate temperature (apparent activation energy - 0). Although no difference in rates for n- or p-type Si was observed, (111) orientations showed approximately a 10% increase in rate over that of (100). This difference is above the standard deviation of our oxidation runs -.3%); at present, we can offer no explanation for this observation. The ECR rate data can be fit to both the Deal-Grove (DG) linear-parabolic [17] or the Wolters-Zegers-van 767

Duynhoven (WZD) ion space-charge limited [18] growth models. The resulting constants in these two rate expressions are given in Tables I and II [16]. The apparent activation energies for both the linear and parabolic rate coefficients fall between 0.06 and 0.1 eV. As the ion density increased with increasing power (from 2 x 1011 cm-3 at 300 W to 5 x 10l cm"3 at 700 W), the apparent activation energy decreased to zero. In addition, oxygen ion and oxygen atom emission intensities increased with microwave power. Oxygen ion emission intensity tracked the ion density as measured by Langmuir probe studies [16]. Oxidation rates are obviously controlled by different mechanisms than those ascribed to thermal oxidation processes. Under floating conditions, the oxidation rate was independent of temperature over the range of 250 to 400 'C up to - 80 min. of oxidation (which corresponds to - 30 nm of silicon dioxide). For these oxides, a parabolic rate law described the rate data, although an initial accelerated oxidation rate, which resulted in the virtual instantaneous formation of - 3 nm of oxide) was observed. The ECR oxides had similar chemical and electrical properties to those of thermal oxides until a thickness of 30 nm was reached. Thicker oxides had buffered oxide etch (BOE) rates that ranged from 1.5 to 3.0 times that of thermal oxides grown at 900 *C. When a dc bias is applied to the wafer holder, the wafer surface behaves like a large planar Langmuir probe [8, 19], so that current is drawn through the wafer and the growing oxide film. The current-voltage characteristic depends on plasma conditions through electron density and electron temperature [8, 19]. In our configuration, the ion density 1 cm from the wafer holder is not affected by the dc bias applied between values of -45 and +5 V. In addition, the ion density in the ECR source region is unperturbed by the wafer bias over this potential range. We can thus assume that the wafer holder can be independently biased over this range with no resulting change in electron density, electron temperature, or ion energy in the ECR discharge. Under cathodic biasing conditions (substrate holder negative), positive ions in the growing oxide are attracted to the silicon and electrons are injected from the silicon into the oxide. Oxidation rates were similar to those observed under floating potential; again, a maximum thickness was observed, with no growth observed after this value. The termination thickness depended upon the bias applied (- 40 rnm for -20 V, and - 5 nm for 35 V). The observation of a maximum thickness is analogous to reports of thermal oxidation results under cathodic bias conditions [20]. Thus, positively charged oxygen ions cannot account for the silicon oxidation observed. The cathodic oxidation results might be explained by electron-active oxidation [21, 22]. However, the questionable reproducibility of our cathodic oxidations and the poor quality of the oxides (BOE rates comparable to those grown under floating

768

conditions, refractive index 1.43 or lower and breakdown fields - 3 MV/cm) established that this bias regime would not generate device quality oxide layers. The ECR oxides with the best thickness uniformity and the best physical and electrical characteristics were grown under anodic (substrate holder positive) bias. Anodizations were performed under constant current and constant voltage conditions; both types of anodization yielded identical oxide properties. Thus, only constant current anodization will be discussed here. In constant current anodization, a positive bias relative to the floating potential was applied to the holder and the voltage varied to maintain a specific negative current. Figure 3 shows oxide thickness versus time for a constant anodization current of -20 mA cm"2 at 350 'C, Power (forward) = 500 W, and two pressures [23]. For these constant current conditions, no change in growth rate occurred between 250 and 400 *C. At pressures between 0.13 and 1.3 Pa, three growth regimes were evident: an initial parabolic region (< 10 nm); a linear (ohmic) growth region extending from 10 nm to 100 nm (equivalent to oxidation times of - 8 - 30 min.); and a region (> 100 nm) with growth rates below that of the linear regime where space charge effects appear to dominate. A parabolic rate law was used to analyze the initial regime in Fig. 3. The parabolic rate constants were 0.0008 and 0.0011 u m2 /hr for 0.26 and 1.3 Pa, respectively; these values are slightly higher than those measured for floating bias operation. The larger rate coefficients may be due to a higher near-surface concentration of negatively charged atomic oxygen under positive bias conditions, which is consistent with an increased electron flux from the plasma. As observed under floating conditions, an induction period occurs at the start of the anodization, where the negative current can be maintained without altering the applied potential, although the oxide thickness is changing. Such behavior has been reported in other studies [3]. The thickness of the oxide layer during the induction period was - 4 nm at 0.26 Pa, and - 0.1 nm at 1.3 Pa. In the linear regime, the oxide grew at a constant rate, and the applied voltage had to be increased to maintain constant current. The linear rate coefficients were 0.11 and 0.095,u m/hr at 0.26 and 1.3 Pa, respectively. These values are similar to those reported for an inductively coupled rf plasma oxidation study performed under analogous current densities [4]. For film thicknesses above 100 nm, oxide growth rates were no longer linear with time. Indeed, it has been shown that space-charge in a growing oxide can result in non-linear growth kinetics during constant current anodization [3,9,24]. The applied voltage in this regime scaled with oxide thickness to the 1.3 power [23]. The high growth rates of anodic ECR oxidation relative to those of thermal 769

oxidation at equivalent temperatures are believed to be due to the transport of 0across the growing oxide film by field-aided diffusion. Since it is unlikely that 0generated in the discharge has sufficient energy to overcome the plasma sheath potential and reach the substrate, we propose that atomic oxygen in the plasma adsorbs onto the growing oxide surface where it forms 0- via electron attachment from the large electron flux from the discharge. Physical and chemical properties of as-grown, anodic oxides 60 nm or less in thickness were identical to those of thermal oxides grown at temperatures of 850 TC or higher [23]. For instance, the refractive index of ECR oxides was 1.467. Etch rates in BOE and infrared, Auger, and X-ray photoelectron spectra were indistinguishable from those of thermal oxides. For films above 60 nm, the ECR oxides displayed BOE rates between 1.1 and 1.25 times that of the thermal oxide rate. Such differences may be due to film stress or to overall film degradation from the cumulative effect of passage of electron current with time. Oxide Electrical Properties Aluminum gates were used to evaluate as-grown ECR oxides. All films studied were 20-30 nm thick. All as-grown oxides had significant fixed charge (> 1 x 101 cm-2) and high levels of interface traps (> 1 x 1012 cm-2 eV"1 ) as estimated by Terman's method) compared to the thermal oxide controls. Oxides grown at floating potential exhibited a hysteresis of 400 mV (polarization direction). This "damage" is likely due to UV and electron flux from the plasma. Breakdown fields were - 4.5, - 8.5, and - 11 MV cm"1 for floating, + 5 V (anodic) and thermal oxides, respectively [23]. When polysilicon was used as the gate metal, the effects of plasma-induced radiation damage were reduced substantially. Due to the anneal step following polysilicon deposition, the fixed charge dropped to that of a control (thermal) oxide (4.7 x 1010 era2). Although interface states were still present (- 1 x 1011 cm' eV-1), the density was equivalent to that of our thermal oxide. No mobile charges were detected in bias-temperature stress studies. Intrinsic breakdown fields also improved, and were generally 10-12 MV cm"1 ; however, slight low field leakage was observed in these cases, probably a result of the interface state density and/or residual damage in the oxide.

CONCLUSIONS An ECR oxygen plasma has been used to grow silicon oxides at temperatures below 500 °C with physical, chemical, and electrical properties similar to those of

770

thermal oxides grown at temperatures above 900 'C. ECR oxidation rates, which were equivalent to thermal oxidation rates at temperatures above 900 'C in dry oxygen, were controlled by plasma flux conditions under substrate floating, positive (anodic), or negative (cathodic) bias configurations. Analysis of the growth kinetics during constant current anodization demonstrated that three distinct oxidation regions exist: initial parabolic growth; linear growth; and space-charge limited growth. The highest quality oxides obtained were grown under anodic conditions. ACKNOWLEDGMENTS This work was supported by National Science Foundation Grants No. ECS8517363 and No. ENG-8710988, Department of Energy Grant No. DEFG0387ER13727, and a contract from IBM Corporation, General Technology Division, Burlington, VT. REFERENCES 1.

J. R. Ligenza, J. Apple. Phys., 36, 2703 (1965).

2.

J. Kraitchman, J. Apple. Phys., 8, 4323 (1967).

3.

S. Taylor, W. Eccleston, and K. J. Barlow, J. Appl. Phys., 64, 6515 (1988).

4.

D. L. Pulfrey and J. J. H. Reche, Solid State Electron., 17, 627 (1974).

5.

A. K. Ray and A. Reisman, J. Electrochem. Soc., 126, 2460 (1981).

6.

C. Vinckier, P. Coeckelberghs, G. Stevens, M. Heyns, and S. DeJaegere, J. Apple. Phys., 62, 1450 (1987).

7.

Y. Yasuda, S. Zaima, T. Kaida, and Y. Koide, J. Apple. Phys., 67, 2603 (1990).

8.

J. F. O'Hanlon, in Oxides and Oxide Films, Vol. 5, ed. by A. K. Vijh, Marcel Dekker, Inc., New York, 1977, p. 105.

9.

S. Gourrier and M. Bacal, Plasma Chem. Plasma Proc., 1, 217 (1981).

10.

A. Reisman, in Semiconductor Silicon 198 , ed. by H. R. Huff, T. Abe, and B. Kolbesen, The Electrochem. Soc. Inc. Pennington, 1986, p. 364.

11.

S. Kimura, E. Marakami, K. Miyake, T. Warabisako,, H Skunami, and T. Tokuyama, J. Electrochem. Soc., 132, 1460 (1985).

771

12.

S. Kimura, E. Marakami, M. Miyake, T. Warabisako, E. Mitani, and H. Sunami, J. Apple. Phys., 63, 4655 (1990).

13.

S. Kimura, E. Murakami, K. Miyake, T. Warabisako, and H. Sunami, J. Electrochem. Soc., 135, 2009 (1988).

14.

G. T. Salbert, D. K. Reinhard, and J. Asmussen, J. Vac. Sci. Technol., A8, 2819 (1990).

15.

D. A. Carl, D. W. Hess, and M. A. Lieberman, J. Apple. Phys., 68, 1859 (1990).

16.

D. A. Carl, D. W. Hess, and M. A, Lieberman, J. Vac. Sci. Technol., A8, 2924 (1990).

17.

B. E. Deal and A. S. Grove, J. Apple. Phys., 36, 3770 (1965).

18.

D. R. Wolters and A. T. A. Zegers-van Duynhoven, J. Apple. Phys., 65, 5126 and 5134 (1989).

19.

P. Friedel, S. Gourrier, and P. Dimitriou. J. Electrochem. Soc., 128, 1857 (1981).

20.

P. J. Jorgensen, J. Chem. Phys., 37, 874 (1962).

21.

E. A. Irene and E. A. Lewis, Appl. Phys., Lett., 51, 767 (1987).

22.

E. M. Young, Appl. Phys. A, L7, 259 (1988).

23.

D. A. Carl, Ph.D. Thesis, University of California, Berkeley, 1991.

24.

N. Cabrera and N. F. Mott, Rept. Prog. Phys., 12, 163 (1948).

772

Table I.

Pfo0 ard

Deal-Grove Model Constants for ECR Oxidation at 0.13 Pa and Thermal Oxidation Comparison.

Temperature

700 W

B(u m2/hr)

A(u m)

B/A(ji m/hr)

T (hr)

0.0126

0.060

0.2096

0.03

400 W

623 K

0.00209

0.0179

0.117

0.07

400 W

723 K

0.00454

0.0259

0.175

0.04

Thermal Ox.

1273 K

0.0117

0.165

Thermal Ox.

1373 K

Table II.

0.027

0.090

0.071 0.30

0.037 0.08

Wolters - Zegers-van Duynhoven Constants for ECR Oxidation at 0.13 Pa and Thermal Oxidation Comparison.

Pfoard

Temperature

700 W

a

a

coA/h.-

c(A/h o)

0.714

0.399

865

9215

400 W

623 K

0.664

0.515

381

623

400 W

723 K

0.659

0.505

563

9722

1073 K

0.670

0.490

60

297

Thermal Ox. Thermal Ox. Thermal Ox.

1223 K 1273 K

0.630 0.620

773

0.590 0.600

312 544

5673 15195

Temperature Conol Langmir Probw-

Magnets _ Gas

Fig. 1.

Schematic of at electron cyclotron resonance plasma oxidation system.

2000

1000

1273 K Th-.1l

5

400 W

623 K

0

200

I00

100

s0

0

The. (ie.t.) Fig. 2.

Oxide thickness versus time for various temperatures and microwave poe- levels.

0.26 Pa -20 mA cm -2

1.3 Pa -20 mA cmr-2 /

100

.1

Near,

;E

Space Charge

Parabolic

Linear , Space Charge

.• Parabolic ab

10 0.1

1

10

100

Fig.

3.

1

10

100

lime (min)

Time (min)

Oxide thickness vs. oxidation time for constant current anodization for two system pressures.

774

CHARACTERIZATION OF STRESS DISTRIBUTION IN SUBMICRON ISOLATION STRUCTURES BY MICRO-RAMAN SPECTROSCOPY AND CORRELATION WITH TRANSMISSION ELECTRON MICROSCOPY I. De Wolfl, J. Vanhellemont1, A. Romano-Rodriguez1, 2 , H. Norstrtam 13 and H.E. Maes1 llnteruniversity Micro-Electronics Center (IMEC), Kapeldreef 75, B-3001 Leuven, Belgium; 2 Cdtedra de Electr6nica, University of Barcelona, Diagonal 645, E-08028 Barcelona, Spain; 3 Swedish Institute of Micro-Electronics, P.O. Box 1084, S-16421 Kista, Sweden Local stress in LOCOS and LOPOS structures is studied by Micro Raman spectroscopy and the results are correlated with XTEM analysis. The stress in the silicon substrate under the center of the structures is found to be compressive and to increase with decreasing line width, except for lines widths smaller than 4 gim. Large tensile stresses are concentrated at the bird's beak edge and are found to be correlated with the shape and length of the bird's beak. LOCOS structures show in the center larger stress and at the bird's beak edge smaller stress than LOPOS samples. INTRODUCTION A well known problem in VLSI technology is the concentration of large stresses near the edges of surface films. These stresses may deform the band structure and change the transport properties, resulting in a degradation of the circuit performance. MicroRaman spectroscopy has proved to be a powerful technique to measure such local stresses [1]. Scattering areas with dimensions of the order of the laser wavelength can be probed. This spatial resolution is superior to most conventionally stress measuring techniques, such as X-ray analysis, where the probed areas have dimensions in the millimeter range. Isolation of active components of silicon Integrated Circuits is commonly performed by LOCal Oxidation of Silicon (LOCOS). A drawback of this approach is the lateral encroachment of the field oxide underneath the Si 3N 4 edge, giving rise to the so called bird's beak (BB). As a consequence the available active surface area is reduced and so is the packing density. To reduce the size of the bird's beak, modified LOCOS techniques were explored, e.g. the LOPOS (Local Oxidation of Polysilicon Over Silicon) technique. Micro-Raman spectroscopy was used to study local stress in these structures and the results were compared with XTEM (cross sectional transmission electron microscopy). EXPERIMENTAL PROCEDURES The samples were fabricated on (001) silicon substrates. Experiments were performed on two LOPOS structures (LOP2 and LOP3) and three LOCOS structures (S#7, S#10 and S#1 1). A pad oxide, thickness 10 nm, was grown by thermal oxidation. This was followed by deposition of 50 nm poly-amorphous silicon (LOP2 and LOP3) or SiON (S#10 and S#1 1). Next a Si 3 N4 film was deposited by LPCVD (thickness 150 nm 775

(LOP2, LOP3 and S#7) or 100 nm (S#10 and S#11) and patterned using photolithography, resulting in long Si 3 N4 lines with different widths. Finally a 600 nm thick field oxide was grown by wet oxidation at different temperatures (LOP2 and S#1 1: 1000 "C, LOP3: 1050 "C, S#7 and S#10: 950 "C). Raman spectra were measured in back scattering configuration using the 457.9 nm or 488.0 nm argon laser line with maximal output power of 30 mW. The incoming light was polarized along the length of the lines, the scattered light was not analysed. The diameter of the probed region was smaller than 1 gm. The sample was moved with an XY translation stage in steps of minimum 0.1 jim. In this way the Raman signal of the silicon was obtained at different positions under and near the Si 3 N 4 lines. The Raman lines were fitted with a Lorentzian function, reducing the error on the peak position to values smaller than 0.05 cmt1. Laser plasma lines were used for calibration. MICRO-RAMAN SPECTROSCOPY Mono crystalline silicon (c-Si) has three active optical vibrations. For strain-free c-Si, these vibrations have the same frequency, ,o, at about 520 cm-1. In the case of back scattering from a (001) surface only the LO phonon can be observed. Strain lowers the symmetry of the crystal so that the degeneracy of the optical phonons is partly lifted and they shift to frequencies different from (00 . The phonon frequencies of strained silicon can be calculated using perturbation theory [2,3]. From this theory it follows that the frequencies of the optical phonons in the presence of strain, co, are related to the eigenvalues, k., of the following secular matrix

S

2rexy 2re•

peyy+q(ezz+Exx) 2rezy

2

reyz pezz+q(exx+Eyy)

(1)

by X =

2 -_(362 i=1, 2, 3 from which follows oi = oo + X•j20)o -ijare the components of the strain tensor e, which is related to the stress tensor -Cby Hooke's law: e = S %t where S is the compliance tensor. For c-Si, S has only three 1 12 different components: SiI = 7.68 10- Pa , S12 = -2.14 10-" Pa-1 and S44 = 12.7 10-12 Pa-t. p,q and rare deformation potential constants [1] with for c-Si: p = -1.43 o2 q 1.89 coo2 and r = -0.59w0) 2 . The Raman polarizability tensors will also change under the influence of strain. They can be calculated by a linear combination of the zero-strain polarizability tensors, corresponding to the linear combination between old and new eigenvectors. As a result, it is possible that in the presence of strain or stress more than one of the three c-Si Raman active optical vibrations can be observed.

STRESS MODEL In order to relate the observed shift of the Raman signal with stress in the material one needs a model that describes the stress profile in the silicon substrate underneath the Si 3 N4 lines. Vanhellemont et al. [41 proposed a stress model which they successfully used 776

to describe film edge induced dislocation generation in LOCOS structures. For simplicity the problem was reduced to two dimensions by assuming an idealized film structure consisting of a film edge perpendicular to the image plane and deposited on a semi-infinite substrate. They assumed plane stress in the silicon with a film edge force lying in the image plane (Fig. 1). This force can be decomposed in two components: f=fex

and

k=afez

with x < 0 for bending up of the film, ex and ez are unit vectors along the X axis and Z axis, respectively.

Fig.l: Cross-sectional view of a LOCOS structure with forces acting on the substrate.

Assuming plane stress, only three stress components are present in the silicon substrate under the structure. For a single line they are given by: 2f it

rx(x÷+ az) (x2+

z2)2

2

(x _-w)2-_ _

(2)

(x -w -az)

(3

0'=2f z2( (x +az) 711

2f

X 2+ z2)2

((

)2 + z2)2

x(x + xz)

(x - w)(x - w -

2

z ((x - W)2 +22

(x2 +

.C1

((x-w)2+z2)2}

z)] (4)

where w indicates the distance between the two bird's beak ends. In most samples we studied, the lines are oriented along a [110] direction. This means that the above given equations are in the axes system X = [1101, Y = [1101, Z = [00i]. The secular matrix is given in the crystallographic axes system [1001,[010],[001]. So we had to calculate the strains in the latter system corresponding with the stresses axx, azz and Txz given in the coordinate system shown in Fig. I and solve the secular matrix for eigenvalues and eigenvectors. From the eigenvectors XI, X2 and X.3, the following dependence of the frequency shift AO( 1, Ao02 and A" ( AO)i = i - WOO) of the three Raman peaks on oxx, (Yz and xz was obtained: 777

Aow = -3.65 1010 oY,- 1.93 10-'90 Ao)2 = -2.12 10-9 x, - 1.34 10-9 02z2 + C A" = -2.12 10-9 xx - 1.34 10-9 oC. - C

4(4.02

zz)

10-7 arx + 1.22 10-6

~~~~2080

(5) + 1.64 1011 t3

"2+16

2

0"T

Using the eigenvectors of the secular equation, the polarizability tensors in the presence of these stresses were calculated. The result implies that both the Raman signal corresponding with peak 2 and the one corresponding with peak 3 can be observed, with an intensity depending on the position across the line. Peak 1 is not visible. RESULTS AND DISCUSSION Fig. 2a shows the peak frequency of the Raman signal that was measured during a scan across a 3 jim wide Si 3 N4 line (LOP2), starting from the center of the line (0 gim) =1 C.) -i

.'4.4

0.0

0.5

1.0 1.5 Position (jim)

2.0

b)

Fig. 2: a) Raman frequency of silicon measured at different positions across a 3 Wim LOPOS structure (LOP2). b) XTEM picture of a similar 3 Wi LOPOS sample. 778

across the edge of the nitride mask (at 1.5 urm, indicated by a dashed line) towards the field oxide. The 457.9 nm laser line was used for excitation in order to probe only the uppermost substrate area, where stresses are expected to be higher. The contribution of the poly-Si to the Raman signal was checked by analysing the polarization direction of the scattered light. It was found to be negligible. An XTEM micrograph of the corresponding LOPOS geometry is shown in Fig. 2b. A polysilicon top layer was deposited on the sample to improve the contrast of the picture. In between measurements on LOPOS or LOCOS structures, the peak frequency of stress-free c-Si was measured on a reference sample. From 9 measurements a value of 520.0 cm 1 was obtained. The frequency of the Raman signal at the center of the 3 gxm line shown in Fig. 2a is higher than this reference value: 520.7 cm t . This indicates the presence of compressive stress in the top layer of the silicon substrate at this position. When approaching the BB, the frequency decreases and reaches a minimum value of 519.3 cm 1 , indicating the presence of tensile stress. It is important to notice that this minimum is not located at the edge of the Si 3 N 4 line, but at the BB's end, under the Si 3 N4 film. The Raman frequency increases again towards the edge of the nitride film and reaches the stress-free value underneath the field oxide. To study the influence of the Si 3 N4 line width on the Raman frequency, we repeated the measurement for line widths varying from 2 gin to 15 gm. The results are shown in Fig. 3. For broad lines (5 to 15 grm), the maximum shift is not reached at the center of the lines, but closer to the edge, indicating a relaxation of the compressive stress towards the center of the line, as predicted by the model. An accurate fit of the proposed model to the measurements was difficult because the theory predicts that peak 2 (at2) has a large intensity outside the

779

1.0

15

0,5 0.0 -0.5 10

0.5 0.0 0 -0.5

5

0.5 0.0 -0.5 1.0' 0.5 0.0 -0.5 1.0

3

0.5 0.0 -0.5 0.5 0.0 -0.5

-10

-5

0

5

10

Position (rtm) Fig. 3: Si Raman frequency shift from the value in the center under the field oxide line, at different positions LOPOS (LOP2) lines of varying width.

lines and is not visible in the center, while the reverse is true for peak 3 (o3). They both show a different dependence on stress. According to the model, both peaks should be visible at the edge of the BB. We never observed two different peaks in this area. The appearance of a significant increase of the width of the Raman signal at half maximum (FWHM) in this area could be due to the presence of two Raman peaks which are not resolved by the Raman instrument. However, a more probable explanation is that this effect is caused by the large variation of the stress within the laser beam diameter and within the probed depth. The former corresponds with the large variation of the Raman frequency in this area. To obtain information on the magnitude of these local stresses, we studied the Raman shift in the center of the lines (Acocenter) and the most negative shift (AComin) in the vicinity of the BB's edge. Both were calculated relative to the Raman shift measured in between the lines. Fig. 4 shows the mean values of A~min and Ac.enter obtained for

different line widths. Acocenter increases with decreasing line width, up to 4 Aim, but decreases for smaller lines. A0min is found to be independent of line width within the experimental error. According to the stress model, rxz is zero and azz is negligible compared to ox, at the center of the line for broad lines (> 4 Aim). ca, (Pa) is then linearly related to the Raman frequency shift: Ao = 2-L pS 12 + q(SlI + S12 )] Ox,

-1.93 10-9 o.x

(6)

Using this equation, OYx was calculated from AcOcenter. The values varied from about -0.09 GPa in the center of 15 jim lines to -0.4 GPa in the center of 4 Aim lines. Furthermore, at the center of these broad lines x = w/2 >> z so that oxx is mainly determined by the value of f and relatively independent of (x and z. Using the value of Oxx and Eq. 2, f was found to be about f = 500 N/in. This value corresponds well with f = 800 N/m estimated from computer simulations of the pile up configuration of 60" dislocations in similar structures [5]. For smaller lines -rxz and czz cannot be neglected and Eq.6 is no longer valid. We attribute the decrease of the Raman shift in the center of these lines to a combination of two effects: an increasing influence of the tensile stress at

S0.8

-0.4

S0.6

-0.3

0.4

-0.2 • -0.1

5

10

15

Line width (grm) 780

Fig. 4: Difference between the Raman frequency in the center of LOP2 lines (Amcenter,-) or most negative Raman frequency (ACOmin, -o-) around the BB's edge of the LOP2 lines and the "Raman frequency under the field oxide, as a function of widths of the Si 3 N4 lines. The right Y-axis denotes the stress at the center of the lines. These values are only valid for broad lines (15 to 4 im).

the BB's edge and the presence of a vertical force in the center of the lines due to the bending up of the Si 3 N 4 film, which increases with decreasing line width. For very narrow lines this vertical force becomes so large that it can cause breaking of the pad oxide and/or the nitride film, as was observed by XTEM [6]. According to the theoretical model, Awmin is strongly dependent of f, a and z but almost independent of the line width, w. We indeed found no significant dependence of Acomin on w (Fig. 4). So, while the stress in the silicon substrate underneath the center of the lines is highly influenced by the width w, the stress at the BB's edge does not change. TEM experiments showed that the shape and length of the BB in these LOPOS samples is independent of the width of the lines. This suggests that the stress at the BB's edge is mainly determined by the shape and length of the BB. The separation between the Si 3 N4 lines in all samples was equal to the width of the lines. Fig. 5 shows the difference between the silicon Raman shift measured in the center of the field oxide region in between the Si 3N4 lines of LOP2 and the stress free Si Raman frequency as a function of the spacing of the lines. Reduction of the line spacing results in an larger negative shift up to widths of 4 Am. For smaller lines the shift decreases. This behaviour is a mirror image of the dependence of the compressive stress at the center of the lines on line width, only the scale is much smaller. Assuming also here uniaxial stress for broad lines, the value of a,, is found to vary from about 0.017 GPa in the center between two 15 Am lines (spacing 15 jim) to 0.064 GPa between 4 Jim lines (spacing 4 Am). These tensile stresses are about a factor 10 smaller than the compressive stresses under the Si 3 N4 film. Tensile stress in the substrate underneath the field oxide is expected from the difference in thermal expansion coefficients of c-Si and SiO 2 [7]. A similar result was reported by Brunner et al. [8]. ,-,

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'

freec-Si(520.0Rcm-) as a function of line spacing. The right Yaxis denotes the stress. These values are only valid for broad lines (15 to 4 Am).

The penetration depth of light increases with increasing wavelength. The Raman signal obtained with 457.9 nm arises from an integrated depth of about 0.3 Am. Light with wavelength 488.0 nm will give information about an integrated depth of about 0.6 pm. According to the theoretical model, the stress in the silicon substrate decreases with depth, and the dependence of stress and Raman frequency shift on depth (z) is larger at the BB's edge than in the center of the lines. Fig.6 shows the dependence of the Raman 781

frequency on the position across a 5 gtm LOPOS line (LOP2), measured with 457.9 nm and 488.0 nm excitation light wavelength. At 457.9 nm, Aommin and Aocentr are clearly larger than the shifts measured with 488.0 nm. Also, as predicted by the model, the influence of excitation light wavelength on Raman shift is larger at the BB than in the center of the line.

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40 60 Position

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Fig. 6: Influence of laser light wavelength used for Raman excitation on the Raman shift observed during a scan across a 5 gim LOPOS structure (LOP2). -o-: 488.0 nm; -- : 457.9 nm

520.6 520.4 520.2 520.0 519.8 80

100 120 140 160 Position (pgm/10)

180

Fig. 7: Raman frequency shift measured during a scan across a 5 gtm line of a LOPOS (LOP2) and a LOCOS (S#7) sample. The excitation wavelength is 488.0 nm. -o- : LOCOS; -- : LOPOS Fig. 7 compares the Raman shift observed during a scan across a conventional LOCOS (S#7) structure with a scan across a LOPOS (LOP2) structure. The width of the 782

scanned lines is 5 gtm. The measurements were performed with laser wavelength of 488 rnm. At the field oxide region, the Raman shift observed in both samples is about 520 cm1, corresponding with the Raman frequency of stress free c-Si. The negative deviation from the stress free value at the BB's edge, at about 0.5 gtm from the edge of the layer (indicated by vertical lines) is larger in the LOPOS structure than in the LOCOS structure, indicating smaller stresses near the LOCOS BB's end. This confirms the hypothesis that the large negative deviation of the Raman frequency at the BB's edge from the unstressed value is correlated with BB's length and shape. At the center of the lines, the Raman frequency is higher than 520 RcmI for both LOPOS and LOCOS structures. Assuming uniaxial stress in the silicon substrate at this position, the following stress values are obtained (Eq. 6): cxx,(LOPOS) = 0.29 GPa < rxx(LOCOS) 0.31 GPa. The only difference between both samples is the presence of a poly-Si layer (500 A) in the LOPOS structure. Poly-Si and single c-Si have about the same thermal expansion coefficient. However, poly-Si exhibits an intrinsic compressive stress of about -0.2 GPa [7]. This stress partly compensates for the tensile stress in the Si 3 N4 layer, resulting in a smaller compressive stress in the underlaying silicon substrate compared to the LOCOS sample. Fig. 8 shows the result of Raman measurements performed on LOPOS (LOP2) and modified LOCOS (S#10 and S#11) samples with wavelength 457.9 nm. Again the deviation from the stress free frequency at the BB is smaller in the LOCOS samples than in the LOPOS samples. This difference can be correlated with the length and shape of the BB: XTEM experiments showed that the BB is longer and less steep in the modified LOCOS sample than in the LOPOS sample. In the center of the lines, both structures show approximately the same positive Raman shift from the control value, indicating compressive stresses of equal magnitude in the substrate. This indicates that poly-Si is a better stress buffer than SiON.

44)

Fig. 8: Raman frequency dependence on position across 5 gm lines. The lines are indicated by the shaded area. LOPOS: LOP2; LOCOS [110]: S#10; LOCOS [1001: S#l 1, LOCOS [100] no Si 3N 4 : S# 1I after removal the the Si 3N 4 film. In the same figure, an experiment on a LOCOS structure with lines oriented in the [1001 direction (S#l I) is shown. We did not observe a significant influence of line orientation on Raman shift. Sample S# 1I was also studied after removal of the Si 3 N4 film by etching techniques. This resulted in a decrease of the Raman shift in the center of the 783

lines, indicating a reduction of the compressive stress in the substrate upon removal of the Si 3 N4 layer. The negative shift from the stress free value is not located at the BB, but is shifted outside the borders of the lines. Similar experiments were reported by Kobayashi et al. [9]. They also observed an increase of A(Ocenter with decreasing line width, but, in contrast with the results we obtained when the Si 3 N4 film was present, up to very small active area sizes (1.2 grn). The difference in Raman shift dependence on line width in samples with and without a Si 3 N4 layer can be understood by the presence or absence of the upward vertical force acting on the silicon surface below the center of the nitride line. The present results show that micro-Raman spectroscopy can give detailed quantitative information about local stresses in LOCOS/LOPOS structures. Despite the fact that a complete fit of a simple planar stress model to the Raman data was not possible, important information could be extracted. Further progress can be expected by refinement of the model by e.g. taking into account the presence of an additional upward vertical force or force distribution at the center of the lines or by use of finite element calculations. ACKNOWLEDGMENTS The authors thank Ph. J. Roussel for stimulating discussions on data handling and modelling. The Raman scattering experiments were performed on the equipment of the K.U.Leuven (MTM department). The authors acknowledge the Belgian Fund for Scientific Research (NFWO), the Spanish Ministry of Science and Education and the Swedish Board of Technical Development REFERENCES [1] [2] [3] [4] [5] [6]

[7] [8] [9]

E. Anastassakis, in 1985 PhysicalProblems in Microelectronics,J. Kassabov ed., Proc. of the 4th Int. School ISPPME, Varna, Bulgaria, 128 (1985) E. Anastassakis and E. Burstein. 1. Phys. Chem. Solids 32, 563 (1971) S. Ganesan, A.A. Maradudin, J. Oitmaa, J. Ann. Phys. (N.Y.) 56, 556 (1970) J. Vanhellemont, S. Amelinckx and C. Claeys, J. Appl. Phys. 61, 2170 (1987) J. Vanhellemont, C. Claeys, J. Van Landuyt and S. Amelinckx, In 1985 ProceedingsGADEST, H. Richter ed., 255 (1985) A. Romano-Rodrfguez, J. Vanhellemont, I. De Wolf, H. Norstr6m and H.E. Maes, to be published in 1991 Proceedingsof the "Vllth Oxford Conference on Electron Microscopy of Semiconducting Materials",Oxford (U.K.), March 25-28 (1991) S.M. Hu, in Proc. of the 2th Intern. Symp. on ProcessPhysics and Modeling in SemiconductorTechnology, The Electroch. Soc., 91-4 (1991) K. Brunner, G. Abstreiter, B.O. Kolbesen and H.W. Meul, In 1989 Proceedings INFOS, F. Koch and A. Spitzen ed., 116 (1989) K. Kobayashi, Y. Inoue, T. Nishimura, H. Arima, M. Hirayama and T. Matsukawa, Ext. Abstracts of the 19th Conf. on Solid State Devices and Materials, Tokyo, C-8-5, 323 (1987) 784

A MANUFACTURABLE IN-SITU DOPED POLYSILICON PROCESS FOR 16-64K BIT DRAM TECHNOLOGY Dane E. Bailey MOS Memory Products Texas Instruments Incorporated P.O. Box 655012, M/S 374 Dallas, Texas 75265 An in-situ doped polysilicon process using phosphine (PH3) and silane (SiH4) is described which meets the requirements for ULSI manufacturing technology. Utilizing experimental design, a process optimizing uniformity and load size was developed for a fully automated 150 mm vertical LPCVD reactor. Optimized conditions produce films which have thickness and resistivity variations of < 1.2% and < 2.0%, respectively, for a 75 wafer load size. Additionally, film conformality is > 95% and defect density is < 0.17 /cm 2 for defects > 0.3 microns. INTRODUCTION As DRAM technology moves into the 16-64M bit density regime, processing requirements become more demanding, especially for high aspect ratio trench technology utilizing up to three different polysilicon levels [1]. To achieve the low temperature processing and homogeneous doping requirements for such technology, in-situ doped polysilicon is the preferred technique. However, current in-situ doped polysilicon processes used in the industry require either special designed LPCVD reactors or caged boats [2,3,41 which preclude the use of advanced automation thereby producing unacceptable defect densities or vapor dopant sources [5] which add unwanted impurities such as Carbon. EXPERIMENTAL In-situ doped silicon films were deposited in a fully automated vertical LPCVD reactor, shown schematically in Fig. 1, using silane and phosphine-silane gas mixtures. Wafers were loaded into a single quartz boat with a capacity of eighty 150 mm wafers spaced 7.11 mm apart. Prior to film deposition, 80-100 nm of silicon dioxide was thermally grown on the wafers.

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Polysilicon film thickness measurements were made with a Nanospec using a refractive index of 2.8 after being annealed at 1000 C for 30 seconds in a Heatpulse RTA. Sheet resistance measurements were made with a Prometrix Omni Map. Defect densities were measured on as-deposited films using a WIS8500, which is capable of 0.2 micron minimum resolution on unpatterned films. RESULTS Experimental design was employed to optimize the effects of gas flow, pressure, and PH3/SiH4 ratio with regard to both thickness uniformity and resistivity uniformity across a 75 wafer load. For this investigation, gas flow, pressure and PH3/SiH4 ratio were varied between 100-300 sccm, 300-600 mTorr, and 0.0008-0.002, respectively, while temperature was held constant at 560 C. As shown in Fig. 2, thickness and resistivity variation is inversely proportional to total gas flow, while resistivity variation is proportional to pressure and PH3/SiH4 ratio. The effects of pressure and PH3/SiH4 ratio on thickness variation were negligible as determined by statistical analysis.

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Figure 2. Main effects of experimental design for in-situ doped polysilicon. A) Thickness and resistivity variation vs. B) Resistivity variation vs. phosphine silane flow. concentration. C) Resistivity variation vs. pressure. The resulting optimized process, as predicted by experimental design, has a one sigma variation in both film thickness and resistivity of 1.15% and 1.9%, respectively, A slight with a deposition rate of 22.2 angstroms/min. of +2 C on the top zone and -4 C on the temperature tilt bottom zone aided in the uniformity. The results are shown graphically in Fig. 3. 30 0.0

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Figure 3. Thickness and resistivity results across 75 wafer Deposition load using predictions from experimental design. conditions are Temp = 560 C, Pressure = 300 mTorr, PH3/SiH4 = 0.0008, Top Flow = 300 sccm, Bottom Flow = 235 scciu. 787

In comparison with data reported by Meyerson et al. [6], it is obvious that deposition rate and uniformity are significantly improved as the PH3 content is decreased. Together with a reduction in deposition temperature, it is possible to achieve low resistivity, highly uniform films with acceptable deposition rates. Furthermore, the optimized process combined with the advanced wafer automation capabilities of a vertical LPCVD reactor, is capable of2 producing films with defect levels less than 0.17 defects/cm for defect sizes greater than or equal to 0.3 microns as shown in Fig. 4.

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Figure 4. As-deposited particle levels for 3000 A in-situ doped polysilicon films. In separate experiments, temperature was varied from 550600 C while all other parameters were kept the same as those listed in Fig. 3. An Arrhenius plot of different in-situ doped polysilicon films is shown in Fig. 5. The activation energy, as calculated from Fig. 5 is 1.5 eV compared with 1.5 eV for TBP doped silicon [5] and 2.0 eV for high PH3/SiH4 concentrations as reported by Learn et al. [2] From TEM analysis of as-deposited films, the amorphous-polysilicon transition temperature for this experiment was determined to be 550 C as shown in Fig. 6. Additionally, the grain size for films deposited at 560 C, 570 C, and 600 C are 3000 A, 2000 A, and 300 A, respectively. Finally, as shown in Fig. 7, the resistivity of such films is proportional to the deposition temperature. 788

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E = 2.0 eV.

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Figure 6. SEM micrographs showing as-deposited grain size for B) A) 550 C - amorphous. various deposition temperatures. 560 C

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2000 A.

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300 A.

Data showing trends for poly grain size and film resistivity as a function of deposition temperature are consistent with data reported earlier [2]. 789

1.5

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540

650

560

570

580

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Figure 7. Resistivity vs. deposition temperature. All other deposition conditions are the same as those listed in Fig. 3. Conformal in-situ doped polysilicon films were deposited under the optimized conditions listed in Fig. 3 on wafers patterned and etched with deep trenches. Unlike previous reports using phosphine doped polysilicon for deep trench refill [71, no voids, defects, or seams were formed using the process described herein as confirmed by SEM analysis and by plasma assisted etch back of in-situ doped polysilicon refilled trench wafers. From SEM measurements as shown in Fig. 8, the step coverage is greater than 95% for optimized films. This again is in contrast to earlier findings where conformality was reported to be 60-80% [8].

790

I

-0.

0.5um

SEM micrograph showing > 95% step coverage of Figure 8. Trench size is 0.6 x 1.2 microns. 0.0008 PH3/SiH4 films. SUMMARY High aspect ratio trench technology requires that films not only be uniform and defect free, but also highly conformal This paper describes an in-situ doped polysilicon as well. is capable of attaining thickness and process which resistivity variations of 1.15% and 1.9%, respectively, over Also, due to being developed in a highly 75 wafer loads. automated vertical LPCVD reactor, this process achieves less than 0.17 defects/cm' for defects greater than or equal to 0.3 Furthermore, due to the low deposition temperature microns. and the low dopant concentration used, films are of sufficient conformality and resistivity to meet ULSI requirements.

791

ACKNOWLEDGEMENTS The author would like to thank R. Tyler for help in conducting the experiments and H. L. Tsai of the Material Science Laboratory for TEM analysis. REFERENCES [I] [2] [3] [4] [5] [6] [7] [8]

B. W. Shen, G. Chung, I. C. Chen, D. J. Coleman, P. S. Ying, R. McKee, M. Yashiro, C. W. Teng, IEDM Tech. Dig., 27 (1989). A. J. Learn and D. W. Foster, J. Appl. Phys. 61, 1898 (1987). L. D. Madsen and L. Weaver, J. Electrochem. Soc. 137, 2246 (1990). J. G. M. Mulder, P. Eppenga, M. Hendrix, J. E. Tong, J. Electrochem. Soc. 137, 273 (1990). T. Tang, IEDM Tech. Dig., 39 (1989). B. S. Meyerson and W. Olbricht, J. Electrochem. Soc. 131, 2361 (1984). K. Sawada, Symposium on VSLI Technology, 41 (1989). T. Morie and J. Murota, Jpn. J. Apple. Phys. 23, No. 7, L482 (1984).

792

DIFFUSION BEHAVIOUR OF DOPANTS IN POLYCRYSTALLINE SILICON ELECTRODE FOR ULTRA HIGH SPEED BIPOLAR DEVICES Hizuru Yamaguchi and Nobuo Owada Device Development Center, Hitachi Ltd., 2326 Imai, Ome, Tokyo 198, Japan

Dopant diffusion from poly-Si into Si-substrate can be suppressed under certain process conditions even by increasing heat treatment, because the strain field around grain boundaries stabilizes them in poly-Si to some extent. This suppression is released by increasing doping level more than stably stored level, or by releasing the strain field by poly-Si grain growth. This very unique dopant behaviour makes it possible to form very shallow junctions with poly-Si electrode insensitive to heat treatment. INTRODUCTION Recently, polycrystalline silicon(poly-Si) film is very widely used as a diffusion source and electrode for very shallow junction formation in the scaled MOS devices and in the advanced selfaligned bipolar devices, in which dopants in poly-Si film have been believed to diffuse very fast through the film down into single silicon substrate(Si-substrate) in any case. But, in the development of selfaligned bipolar devices with emitter and base poly-Si electrode, we have found out that the dopants in poly-Si film do not always diffuse into the substrate with the increase in heat treatment, and that the dopant diffusion into the substrate is saturated at the initial stage of drive-in annealing under certain process conditions. This paper reports the detailed study of this very unique diffusion phenomenon of dopants in this poly-Si/Si-substrate structure, observed in very shallow emitter/base junction formation process for an advanced self-aligned bipolar transistor.

EXPERIMENTS Fig. 1 shows the cross-sectional view of an advanced self-aligned bipolar transistor, in which emitter and active base is formed by arsenic and boron diffusion from poly-Si into Si-substrate respectively, and graft base is formed by diffusion of boron implanted

793

in the surface region of Si-substrate both into the substrate and into the poly-Si film deposited on it. This study focuses on diffusion behaviour of dopants in poly-Si/Si-substrate structure, simulating very shallow emitter/base junction formation in this self-aligned bipolar transistor. Poly-Si film is deposited on Si-substrate by thermal decomposition of SiH 4 at 643 0 C. just after removing native oxide with buffered HF. In simulating emitter formation, poly-Si film deposited on Si-substrate is implanted with arsenic at 80keV to the dose of 2X10 16 /cm 2 followed by drive-in annealing around 9000 C. In simulating active base formation, poly-Si film deposited on Sisubstrate is implanted with boron at 30keV to the dose of 2X10 14 /cm 2 followed by two drive-in annealing steps. In simulating graft base formation in Fig. 1, Si-substrate is implanted with boron at 10keV to the dose of 1X10 1 5/cm 2 followed by poly-Si deposition and drive-in annealing at 9500 C. Cross-sectional TEM is used in order to evaluate the crystalline structure of the poly-Si film, and dopant distribution in poly-Si/Si-substrate structure is measured by SIMS using a CAMECA 3f instrument.

base poly-Si

Fig.1

emitter oly-Si

Typical cross-sectional view of a self- aligned high speed bipolar transistor.

794

RESULTS AND DISCUSSIONS

Fig.2 summarizes the diffusion behaviour of arsenic from polySi into SI-substrate, simulating shallow emitter junction formation, under three annealing conditions listed in the figure. After the annealing at 85090 for 20 minutes, arsenic diffusion layer is already formed in Si-substrate, indicating that the arsenic diffuses very fast through the poly-Si film down into the substrate. On the other hand, the diffusion profile of arsenic in poly-Si/Si-substrate changes very little even by increasing the annealing temperature from 8500C to 900'C and the annealing time from 20 minutes to 40 minutes, indicating that the diffusion of arsenic from poly-Si into Si-substrate is saturated at the initial stage of drive-in annealing after dopant profile in poly-Si and in Si-substrate is balanced. Fig. 3 shows boron profiles diffusing from poly-Si into Sisubstrate under three annealing conditions listed in the figure, simulating active base formation. Even in this case, boron profile in poly-Si/Si-substrate structure does not change by increasing drive-in annealing from 90000 for 20 minutes up to 10000C for 40 minutes, indicating that the boron diffusion is also saturated after dopant profile in poly-Si and in Si-substrate is balanced. Fig.4 summarizes diffusion behaviour of boron, implanted in the surface region of Si-substrate, both into the poly-Si film deposited on it and into Si-substrate under three annealing conditions listed in the figure, simulating graft base formation. As is clearly shown in this figure, boron atoms implanted in the surface region of the substrate diffuse very fast up into the poly-Si film after 10 minutes annealing at 9500C. But, the diffusion of boron deep into the substrate does not advance even by increasing the annealing time from 10 minutes up to 60 minutes, indicating that the boron diffusion deep into the substrate is also saturated because of the existence of poly-Si film on it after dopant profile in poly-Si and in Si-substrate is balanced. Extensive studies have been done for the mechanism of the above mentioned dopant diffusion behaviour in poly-Si/Si-substrate structure. And It is deduced from these studies that the strain field in poly-Si film, caused by crystalline imperfection such as grain boundaries, stabilizes some amount of dopants and tends to store them in the poly-Si film, resulting in suppression of their diffusion into the substrate. So, in order to release this saturation of dopant diffusion, doping level should be increased more than the level stably stored in the poly-Si film, or strain field in poly-Si film should be released. Fig.5 and Fig.6 show the effects of increasing doping level, corresponding to Fig.3 and Fig.4 respectively. In Fig.3, the doping

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797

level is increased from 2X10 14 /cm 2 to IX10 16 /cm 2 . and the boron diffusion into the substrate is advanced drastically under the same annealing condition. In Fig.6, the doping level implanted in the surface region of the substrate is increased from IX10 1 5 /cm 2 to lXl0 16 /cm 2 , and the boron diffusion into the substrate is also advanced drastically. The best way to release the strain field is to increase the grain size of poly-Si film, and we have confirmed that the arsenic diffusion from poly-Si into Si-substrate is advanced by raising the annealing temperature from 900FC up to 950 0 C together with the grain growth of poly-Si film. In this way, dopant diffusion in poly-Si/Si-substrate structure shows very unique behaviour that has never been observed in the conventional diffusion mechanism in single crystal silicon. And by making the best use of this saturation phenomenon of dopants, shallow junctions in advanced devices with poly-Si electrode can be made insensitive to heat treatment under very high repeatability. CONCLUSIONS Diffusion mechanism of dopants in poly-Si/Si-substrate structure is completely different from the well established diffusion mechnism in single silicon, and the saturation of dopant diffusion from poly-Si into Si-substrate occurs under certain process conditions. This saturation phenomenon is successfully explained by the mechanism that the strain field in poly-Si film caused by grain boundaries stabilizes some amount of dopants and stores them in the film. This very unique behaviour of dopants in this poly-Si/Sisubstrate structure makes it possible to form very shallow junctions with poly-Si electrode insensitive to heat treatment.

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Depth(p•m) of boron diffusion from poly-Si into Fig.6 Enhancement Si-substrate by increasing doping level corresponding to Fig.4. (Implantation condition; B, 1OkeV, 1 El 6 atoms/crr?) 799

A NEW POLYSILICON TEXTURIZATION TECHNIQUE USING EXCIMER LASER PROCESSING Viju K. Mathews and Chang Yu Micron Technology Inc. Boise, ID 83706

ABSTRACT A new texturization technique utilizing a XeCl excimer laser to modify the surface of polysilicon films has been investigated. A significant change in the surface roughness and optical reflectivity of the polysilicon films has been observed after processing. The change in the surface texture depends on the applied laser fluence and polysilicon deposition temperature. For laser fluences of 0.2 J/cm2 to 0.7 J/cm2, the reflectivity of the polysilicon film after laser processing varied from 10% - 180% (relative to silicon). Optimization of the deposition temperature and laser fluence to maximize the surface roughness of the polysilicon film, used as the capacitor storage node, can result in a significant increase in the effective surface area and cell capacitance.

INTRODUCTION As device dimensions in Dynamic Random Access Memories (DRAM's) continue to shrink, the need to achieve a higher stored charge for a given cell area becomes increasingly important. The utilization of advanced trenched (1] or stacked [2-4] cell structures results in a significant improvement over planar structures, but it also adds to the complexity of the process. "Texturization" or "roughening" of the polysilicon film, that forms the storage plate, has recently received a great deal of attention because of its effectiveness in increasing the cell capacitance for a fixed planar area. Several techniques including reactive ion etching [5], low temperature oxidation [6] and rugged polysilicon deposition [7-11] have been investigated to increase the surface roughness of the polysilicon film. In this paper,

a new texturization

800

technique involving the

surface modification of polysilicon films using an excimer laser is reported. Excimer laser processing relies on a high power, ultra - short laser pulse to achieve an enhanced degree of surface roughness. Compared with the existing texturization procedures, this technique is expected to offer a high throughput, better process control and wider process window at the cost of only introducing an additional process step. Structural and crystallographic modifications of polysilicon films using laser processing have been reported earlier in relation to graphoepitaxy (12-14]. For this application, laser energy was used to induce crystallization in polysilicon films deposited on a SiO2 substrate. The desired orientation, (100), in the recrystallized film was achieved by using gratings on the substrate. These investigations were directed at the development of SOI substrates. The parameters that were reported to be important in these studies included the laser power, beam diameter, scan speed and overlap, substrate temperature, atmosphere during crystallization, silicon film doping and the type of substrate. It was also observed that the process conditions that gave the best crystallographic orientations also resulted in a significant degree of surface roughness [15]. For the present application, the primary requirement is the development of a very rough surface texture on the polysilicon film. The crystallographic orientation is of secondary importance as related to the subsequent doping of the film.

EXPERIMENTAL The substrates used for this study were 150 mm, p-type (100) silicon wafers. An insulating layer of PECVD oxide was used between the substrate and the capacitor structures. The polysilicon films for the capacitor plates were deposited in a LPCVD reactor at a pressure of 80 mTorr. The storage plate was deposited at temperatures ranging from 550-625 C, and the top plate was deposited at 625 C. An 8 nm reoxidized nitride (ON) film was used as the cell dielectric. The texturization of the polysilicon film was carried out using a XeCl (308 nm wavelength) excimer laser with an energy of approximately 500 mJ/pulse and pulse duration of approximately 25 nsec. The laser fluence, defined as the laser energy per unit area (J/cm2), was controlled by varying the laser spot size. In this study, the spot size was typically varied from 6.7 to 8.0 mm. The surface texture of the polysilicon film before and after laser processing was examined by scanning electron microscopy. Reflectance at a wavelength of 480 nm was used to quantify the surface roughness of the films. Capacitance -

801

(a) As-deposited (555 C)

(d)

As-deposited (600 C)

(b)

Fluence = 0.656 J/cm2

(e)


(c)


(f)

Fluence = 0.757

Fig.

J/cm2

1. SEM micrographs of polysilicon films deposited at 555 and 600 C before and after laser processing.

802

voltage measurements on 6.5 e-5 cm2 evaluating the cell capacitance.

structures were used for

RESULTS AND DISCUSSIONS (A)

Undoped films

The surface texture of polysilicon films deposited at 555 and 600 C before and after laser processing is shown in Fig. 1. As seen in the micrographs, laser processing results in the generation of a surface texture consisting of small globules connected in a grain-like structure. It was observed that the size of the globules and the size of the grain-like structure increases with increasing laser fluence. For the highest fluence used in this study, the globules are quite large and the inter - connecting structure is almost absent, indicating a possible breakdown of the film as shown in Fig. ic. The general development of the structure after laser processing was similar for the other films deposited at 560, 565, 570, 575, and 590 C. It was also observed that that the 600 C film did not exhibit the breakdown (Fig. lf) seen in the other films at the highest fluence. An interesting observation for the polysilicon films deposited at different temperatures was the effect of laser processing on the reflectivity of the films. Reflectance measurement at 480 nm was used to quantify the surface roughness of the films. Results from other texturization experiments have indicated that the reflectance of the film is a good indicator of the surface roughness. As shown in Fig. 2, a good correlation is observed between the reflectance of the film and the cell capacitance. The change in the

120 A S.

AA *

110@ 100

., 90

80

1o

Fig.

2.

1.2

1.3

104

1.5

1.6

Effect of film reflectance on cell capacitance. 803

0 CONTROL A 0 o

150

0 A

S

A

0

v

[3

555 C

r]

A

560 C 565 C

N100-

570 C 575 C

0

590 C 600 C 50 A A A 0 0,5

A

A

0.6

0.8

0.7 LASER FLUENCY (J/cm2)

Fig.

3.

Effect of laser processing on film

reflectance.

0 Q

CONTROL

O

0.550

A

0.636 J/cm2

J/cm2

45

TI

S40

V

35 0

30

560

565

570

POLYSILICON DEPOSITION

Fig.

4.

575

Effect of polysilicon deposition

processing on cell capacitance.

804

625

TEMPERATURE (C)

temperature and laser

of the undoped films as a function of the laser reflectance shown in Fig. 3. There was an fluence during processing is increase in reflectance after laser processing for films depothe 555 to 575 C temperature range. In the case of sited in the higher temperature films (590,600 C), there was a decrease in the reflectance values. The silicon deposition temperature used for these tests corresponds to the amorphous to polycrystalline transition region [16,171. Films deposited under these conditions are expected to exhibit the changes in the surface roughness associated with this transition. However, for the initial set of experiments, we did not see a corresponding change in the reflectance of the films (control values in Fig. laser 3). Based on the reflectance results from these tests, fluences of 0.558 J/cm2 and 0.636 J/cm2 were used to further investigate the changes in the surface roughness of polysilicon films in terms of cell capacitance measurements. The polysilicon films for these tests were also deposited at various temperatures ranging from 560 to 625 C. The effect of the polysilicon deposition temperature and laser fluence on the cell capacitance is shown in Fig. 4. The change in the cell capacitance with deposition temperature observed for the as deposited films (control points) is a result of the amorphous transition , mentioned earlier, and the to polycrystalline

(a)

(b) (b)

(a)

1 pm (c) Fig.

5.

Surface texture of polysilicon films 560, (b) 568, and (c) 575 C. 805

deposited at (a)

*

0

1

100 n. 50 nm

10

0 0

0 0

0 0

£ 00 0

00 I. 0

0 0

1. 0C 0

0.3

0 2

0.6

0 5

0.4

0 7

LASER FLUENCE (J/c-2)

Fig.

6.

Effect film.

of

laser

processing

on a 625 C

polysilicon

associated changes in the surface texture. The variation in the surface texture of the as-deposited films from this group is shown in Fig. 5. An increase in cell capacitance with laser processing is only observed for the films deposited at 560 and 625C, the increase being higher for the 625C film. The changes in cell capacitance with laser fluence for polysilicon films deposited at 625 C are shown in Fig. 6. The highest gain in capacitance for a 50 nm film was 8 %. The thickness of the film is also seen to have an effect on the surface texture after laser processing as indicated by the data points for the 100 nm film. (B)

Doped films

The effect of laser processing on doped polysilicon film is shown in Fig. 7. The film was deposited at 625 C and thermally doped with phosphorus at 850C. The capacitance values in all cases were lower than that observed for the control. The thermal doping of polysilicon results in a small degree of texturization because of enhanced oxidation along the grain boundaries during phosophorus diffusion and the subsequent removal of the oxide. The decrease in capacitance with laser processing could be caused by a reduction in this surface 806

0

CONTROL

390

S38

37-

360.5

0.55

0.6

0.65

0.7

0.75

LASER FLUENCE (J/cm2)

Fig. 7.

Effect of laser processing on

doped 625 C polysilicon

film. roughness. Electrical tests to evaluate the capacitor structures, in terms of leakage current and reliability, were not conducted because of the modest gains in capacitance obtained for the process conditions used in this study. However, similar studies on as-deposited rugged polysilicon structures [11,18,19] have indicated that the small increase in leakage current observed for the rough polysilicon capacitors with a reoxidized nitride(ON) dielectric is negligible compared to the typical increases of several orders of magnitude observed when SiO2 is used instead of ON on a rough electrode. Reliability measurements (Time to 50% failure) on rough and smooth capacitors have indicated a lower lifetime for the rugged capacitors at high fields (8-12 MV/cm). However, because of their higher field acceleration coefficient, rugged capacitors are expected to exhibit a much higher lifetime value at the operating field of 3 MV/cm [11,19]. Rugged polysilicon electrodes have been observed to exhibit electron trapping as opposed to hole trapping for the smooth electrodes [18]. Similar observations have been reported in studies related to EEPROM's [20,21] and the results were attributed to the large localized current density at the tip of the asperities. This phenomena, which limits the endurance of EEPROM's [20] can actually be beneficial for DRAM

807

applications where it can relax the localized high fields and reduce excessive leakage currents [22].

electric

CONCLUSIONS A new texturization technique utilizing an excimer laser to enhance the surface roughness of polysilicon films has been investigated. A significant change in the surface roughness and optical reflectivity of the polysilicon film has been observed after laser processing. The polysilicon deposition and doping conditions as well as the laser fluence used during processing were found to be the important parameters for this texturization process.

ACKNOWLEDGEMENT The authors would like to thank M. Tuttle, A. Martin, T. Doan, P. C. Fazan, and H. C. Chan for discussions. The assistance from the process development, manufacturing, and the Y.E. SEM lab groups at Micron is also gratefully acknowleged.

REFERENCES N.C.C. Lu, IEEE Circ. Dev. Mag., Vol. 5, No. 1, 27(1989). T. Ema, S. Kawanago, T. Nishi, S. Yoshida, H. Nishibe, T. Yabu, Y. Kodama, T. Nakano and M. Taguchi, IEDM Tech. Dig., 592(1988). [3] W. Wakamiya, Y. Tanaka, H. Kimura, H. Miyatake and S. Satoh, Symposium VLSI Tech., 69(1989). [4] S. Inoue, A. Nitayama, K. Heida and F. Horiguichi, Ext. Abs. 21st Conf. on SSDM, 141(1989). [5] T. Mine, S. Iijima, J. Yugami, K. Ohga and T. Morimoto, Ext. Abs. 21st Conf. on SSDM, 137(1989). (6] P.C. Fazan, and R.R. Lee, IEEE Electron Dev. Lett., Vol. 11, No. 7, 279(1990). [7] M. Sakao, N. Kasai, T. Ishijima, E. Ikawa, K. Terada and T. Kikkawa, IEDM Tech. Dig., 655 (1990). [8] M. Yoshimaru, J. Miyano, N. Inoue, A. Sakamoto, S. You, H. Tamura and M. Ino, IEDM Tech. Dig., 659(1990). [9] Y. Hayoshide, H. Miyatake, J. Mitsuhashi, M. Hirayama, T. Higaki and H. Abe, Ext. Abs. 22nd Conf. on SSDM, 869 (1990). [10] H. Watanabe, N. Aoto, S. Adachi, T. Ishijima, E. Ikawa, [1] [2]

808

K. Terada, Appl. Phys. Lett., Vol. 58, No. 3, 251 (1991). A. Ditali and [11] V. K. Mathews, P. C. Fazan, G. S. Sandhu, H.R. Rhodes, Ext. Abs. 179th ECS Meeting, Vol. 91-1 , No. 375, 567(1991). [12] M.W. Geis, D.C. Flanders, D.A. Antoniadis and H.I. Smith, Apple. Phys. Lett., Vol. 35, 71(1979). [13] M.W. Geis, D.C. Flanders, D.A. Antoniadis and H.I. Smith, J. Vac. Sci. Tech., Vol. 16, 1640(1979). [14] M.W. Geis, D.C. Flanders, D.A. Antoniadis and H.I. Smith, IEDM Tech. Dig., 210(1980). [15] M.W. Geis, D.A. Antoniadis, D.J. Silversmith, R.W. Mountain and H. I. Smith, Appl. Phys. Lett., Vol. 37, No. 5, 454(1980). [16] P. Joubert, B. Loisel, Y. Chouan and L. Haji, J. Electrochem. Soc., Vol. 134, No. 10, 2541(1987). Proust and K. Zellama, J. Bisaro, J. Magarino, N. [17] R. Appl. Phys., Vol. 59, No. 4, 1167(1986). [18] H. C. Chan, V. K. Mathews and P. C. Fazan, submitted to Elec. Device Letters. H.C. Chan and A. Ditali, to be [19] P.C. Fazan, V.K. Mathews, submitted to Appl. Phys. Letters. [20] N. Mielke, A. Fazio and H.C. tiou, Proc. Int. Rel. Phys. Symp., 85(1987). [21] Y. Fong, A.T.T. Wu and C. Hu, IEEE Trans. Elec. Devices., Vol. 37, 583(1990). [22] T. Watanabe, N. Gato, N. Yasuhisa, T. Yamase, T. Tamnaka and S. Shinozaki, Int. Rel. Phys. Symp., 50(1989).

809

AS-DEPOSITED RUGGED POLYSILICON FOR 16 AND 64 MBIT DRAM CELLS Viju K. Mathews, Pierre C. Micron Technology Inc,

Fazan and Akram Ditali Boise, Idaho 83706

ABSTRACT The effect of processing conditions on the surface texture of polysilicon films has been investigated in this study. We observed an increase in the surface roughness and the corresponding cell capacitance for films deposited at temperatures ranging from 560-570 C when compared to the smooth films obtained at 625C. The as-deposited surface texture is very sensitive to the procedure used for doping the film. The dielectric deposition conditions were also observed to have a small effect on the measured capacitance. The stability of the "rugged" films to subsequent high temperature processing, the electrical properties, and reliabilty of the capacitor structures have also been evaluated.

INTRODUCTION The transition to higher generations of dynamic random access memories (DRAM) is associated with a corresponding decrease in the cell size. This has a direct effect on the surface area available for the storage capacitor. The minimum charge required for the reliable operation of a memory device is determined by several factors such as the soft error rate, sense amplifier sensitivity, 0-1 storage voltage difference and bit line capacitance [1]. This requirement has led to the development of several innovative cell designs utilizing trenched [2] or stacked structures [3-5]. These advanced 3-D structures increase the surface area available for the capacitor without significantly affecting the cell size. However, they usually tend to increase the complexity of the process. Another alternative is the use of materials with high dielectric constants like Tantalum pentoxide [6], Yittrium Oxide [7], and Lead Zirconate Titanate (PZT) [8]. These materials have yet to be used on a large scale because of several unresolved issues related to their processing, leakage current, and reliability. A recent development in the field of cell capacitors has been the application of techniques designed to "roughen" or "textu-

810

rize" the surface of the polysilicon film used as the storage node. This results in a larger surface area for the same planar area occupied by the film. One approach has been the deposition of smooth polysilicon films followed by texturization using reactive ion etching [9], low temperature oxidation [10], or laser processing [11]. The surface texture of polysilicon films can also be changed during deposition by varying the process conditions [12-17]. The main advantages offered by the as-deposited "rugged" polysilicon technique include the simplicity of the process as well as the use of fabrication procedures that are slight variations of well established polysilicon deposition techniques. In addition to this, the electrical characteristics and reliability of capacitor structures using polysilicon films has been widely investigated. In this paper we report on the changes in the surface texture and the corresponding increase in cell capacitance that can be achieved by varying the process conditions during the deposition of polysilicon films. The stability of the "rugged" film during doping, dielectric deposition and subsequent high temperature processing steps has also been investigated. Finally, the leakage characteristics and reliability of the rugged polysilicon capacitor structures are evaluated with respect to the smooth polysilicon capacitors.

EXPERIMENTAL P-Type, (100) wafers with 200 nm of densified TEOS oxide were used as the base for depositing the polysilicon films that formed the storage plate of the capacitor. The polysilicon films were deposited in a vertical LPCVD reactor at temperatures ranging from 550 to 625 C . The base operating pressure was 80 mTorr. The tube pressure was also varied from 80 to 1000 mTorr to study its effect on the film texture. An 8 nm thick re-oxidized nitride (ON) film was used as the cell dielectric. The top plate of the capacitor consisted of a 100 nm thick polysilicon film doped by phosphorus diffusion. The surface texture of the polysilicon films were evaluated using reflectance measurements, scanning electron microscopy, and scanning force microscopy. Their capacitance and leakage current characteristics were determined from capacitance - voltage (C-V) and current-voltage (I-V) measurements using 6.5e-5 cm2 structures. The capacitor lifetime at high electric fields was measured by constant voltage time dependent dielectric breakdown (TDDB) on 2.0e-2 cm2 structures. All measurements involved the application of both positive and negative voltages to the top capacitor electrode to simulate the actual operation of a multi-megabit memory cell. Some of the tests were also conducted at 125 C.

811

(a)

(d)

(b)

(e)

(c) Fig.

I Pm

(f)

1. Surface texture of polysilicon films deposited at (a) 555, (b)560, (c)565, (d)570, (e)575, and (f)625 C.

812

RESULTS AND DISCUSSION

The surface texture of the polysilicon films deposited at the various temperatures used in this study are shown in Fig. 1. The films are amorphous at 550 C and polycrystalline at 625 C. Within this range, the change in surface texture associated with the transition from the amorphous to the polycrystalline phase [13] is responsible for the appearance of the rough layers. For the 100 nm thick films used in this study, we observed a good correlation between the surface roughness of the film and its reflectance (Fig. 2). These measurements were at a wavelength of 480nm, but similar trends were observed at shorther wavelengths of 280 and 370 nm. The change in cell capacitance with the polysilicon deposition temperature is shown in Fig. 3. The maximum increase in capacitance observed in this study was 54%. The changes in capacitance with temperature correlate very well with the surface roughness observed in the SEM micrographs and the reflectance measurements. The surface texture of the polysilicon film was observed to be very sensitive to the doping procedure. As shown in the figure, thermal diffusion of phosphorus to dope the film gives a much lower increase in the capacitance compared to the optimized process. The slightly higher capacitance observed for the 625 C film compared to the 550 and 555 C films, after thermal diffusion, is due to the grain boundary enhanced dif-

1201 PHO0SPHORU0 DIFFUSI00

512

Ii0

•103

i

900

701 0.L 4054 5 0

560 50

580

050 600

620

620

560 500 560 590 600 610 620 630 SOtyTLCON DEPOOSTION 'r~IEMIIAlII( (C)

550

630

pOLYSILICON DEPOSITION TENOEOATURE (C)

Fig.

2.

Change in reflectance with polysilicon deposition temperature.

Fig.

813

3.

Effect of polysilicon deposition temperature on cell capacitance

1.5-

S N N

756 C ( 3:1) 765 C (10:1) 600 C (3:1)

1 *

1.4

~14 11

,

550

6o

POLYSILICON DEPOSITIONT-

Fig.

4.

G

0,

_D

-P-ERAT E (C)

Effect of dielectric deposition conditions on cell capacitance.

_Du "Du 7 8ED "Du 9 -a o

1-u

-•

630

POLYSILICONDEPOSITIONT-pERATURE (C)

Fig.

5.

Stability of the films to subsequent high temperature processing.

fusion in the high temperature film which results in a small amount of texturization. The figure also indicates the high sensitivity of the polysilicon surface roughness to the deposition temperature. This sensitivity can be reduced by otpimizing the

deposition

pressure.

Three different

silicon

nitride

films were used to study the stability of the polysilicon film to the dielectric deposition conditions. The variables included the deposition temperature and the ammonia to dicholorosilane ratios. Based on the results from the rugged polysilicon annealing tests, mentioned below, the temperature at which the nitride film is deposited is not expected to cause any significant change in the polysilicon surface texture. The small differences that were observed could be associated with the conformality of the nitride film as affected by the gas flow ratio and temperature or the variation in thickness of the nitride film. The stability of the films to subsequent processing was evaluated by annealing the final capacitor structures at 900 and 957C in a nitrogen ambient. As shown in Fig. 5, the annealing treatments do not affect the roughness of the polysilicon films. However, it was observed that capacitors formed on smooth polysilicon films (575 and 625 C) exhibited an excessive amount of leakage current after the thermal cycles. I-V curves for samples with different

814

polysilicon storage

I r%-3 IU

-

2500

CDB

CA

10-4

Positive 5D

:0

4 t -11 IV

0

3

6 9 Voltage (V)

12

4

10

Voltage (V)

(a)

(b)

10-3

10"•i

1250C Positive

DB

104-

C

0)

A

125°C

D C

106

Negative

A

0)

10OI

0

10-12U

Fig.

6.

3

6

9

12

15

0

3

6

9

Voltage (V)

Voltage (V)

(c)

(d)

12

15

Current-Voltage characteristics for polysilicon films at (a)25 C, + bias, (b)25 C, - bias, (c)125 C, + bias, and (d)125 C, - bias. The films were deposited at (A)625, (B)570, (C)565, and (D)560 C.

815

improvement of at least 3 orders of magnitude. Hence, the use of a rugged polysilicon electrode for storage capacitors provides a considerable increase in capacitance and also improves their reliability.

CONCLUSIONS The application of as-deposited rugged polysilicon films for the fabrication of cell capacitors in high density DRAM's has been reported in this paper. These films increase the cell capacitance for a given planar surface without increasing the process complexity. The stability of the films to subsequent high temperature processing coupled with the low leakage currents and high lifetime values exhibited by the capacitor structures makes them a highly attractive option for high density dynamic random access memories.

ACKNOWLEDGEMENTS The authors would like to thank Annette Martin and Mark Tuttle for discussions, Bill Black for the TDDB measurements, Brenda Jameson for assistance with the manuscript, and the process development, manufacturing and Y.E. Sem Lab groups at Micron for assistance with the experiments.

REFERENCES [1] [2] [3] (4] [5] [6] [7] [8]

A.L. Tasch and L.H. Parker, Proceedings of the IEEE, Vol. 77, No. 3, 374(1989). N.C.C. Lu, IEEE Circ. Dev. Mag., Vol. 5, No. 1, 27(1989). T. Ema, S. Kawanago, T. Nishi, S. Yoshida, H. Nishibe, T. Yabu, Y. Kodama, T. Nakano and M. Taguchi, IEDM Tech. Dig., 592(1988). W. Wakamiya, Y. Tanaka, H. Kimura, H. Miyatake and S. Satoh, Symposium VLSI Tech., 69(1989). S. Inoue, A. Nitayama, K. Heida and F. Horiguichi, Ext. Abs. 21st Conf. on SSDM, 141(1989). H. Shinriki, Y. Nishioka, Y. Ohji and K. Mukai, IEDM Tech. Dig., 684(1986). L. Manchanda and M. Gurvitch, IEEE Electron Dev. Lett., Vol. 9, No. 4, 180(1988). J. Carrano, C. Sudhama, J. Lee, A. Tasch and W. Miller, IEDM Tech. Dig., 255(1989).

818

[9] [10] [11] [12] [13] (14] [15] [16] [17] [18] [19] [20] [21]

Yugami, K. Ohga and T. Morimoto, T. Mine, S. Iijima, J. Ext. Abs. 21st Conf. on SSDM, 137(1989). P.C. Fazan and R.R. Lee, IEEE Electron Dev. Lett., Vol. 11, No. 7, 279(1990). V.K. Mathews and C. Yu, Ext. Abs. 179th ECS Meeting, Vol. 91-1, No. 374, 565(1991). P. Joubert, B. Loisel, Y. Chouan and L. Haji, J. Electrochem. Soc., Vol. 134, No. 10, 2541(1987). Zellama, J. Magarino, N. Proust and K. R. Bisaro, J. Appl. Phys., Vol 59, No. 4, 1167(1986). Ikawa, K. Terada and M. Sakao, N. Kasai, T. Ishijima, E. T. Kikkawa, IEDM Tech. Dig., 655 (1990). M. Yoshimaru, J. Miyano, N. Inoue, A. Sakamoto, S. You, H. Tamura and M. Ino, IEDM Tech. Dig., 659(1990). Y. Hayoshide, H. Miyatake, J. Mitsuhashi, M. Hirayama, T. Higaki and H. Abe, Ext. Abs. 22nd Conf. on SSDM, 869 (1990). Aoto, S. Adachi, T. Ishijima, E. Ikawa H. Watanabe, N. 251 and K. Terada, Appl. Phys. Lett., Vol. 58, No. 3, (1991). L. Faraone, IEEE Trans. Electron Dev., Vol. 33, No. 11, 1785(1986). Phys., Vol. 38, No. 7, 2951(1967). S. M. Sze, J. Appl. IEDM Tech. Dig., 663(1990). P. C. Fazan and A. Ditali, H. KitaA. Nishimura, S. Murata, S. Kuroda, 0. Enomoto, Phys. Symp., 158 gawa, and S. Hasegawa, Proc. Int. Rel. (1989).

819

EXPERIMENTAL VERIFICATION OF A FUNDAMENTAL MODEL FOR MULTIWAFER LPCVD OF POLYSILICON Thomas A. Badgwell, Thomas F. Edgar, Isaac Trachtenberg Department of Chemical Engineering, The University of Texas at Austin Austin, Texas 78712 J. Kiefer Elliott SEMATECH, Inc. Austin, Texas 78741

A fundamental model for multiwafer LPCVD of polysilicon has been developed and evaluated in terms of its ability to predict experimental data from two widely differing reactors. The model can predict the main features of polysilicon deposition in a small research reactor, even though the model parameters were estimated using data taken from a much larger industrial system. It is demonstrated that the assumption of thermal variations within the reactor can greatly improve model predictions.

INTRODUCTION The horizontal multiwafer Low Pressure Chemical Vapor Deposition (LPCVD) reactor, first introduced in the late seventies [1], is a critical component in the manufacture of integrated circuits. Although this type of reactor is widely used to deposit polysilicon, nitride and low temperature oxide films [2, 3], the transport phenomena and chemical reactions influencing these processes are not well understood. Recent attempts to model the multiwafer LPCVD reactor have shown promising results [4, 5, 6, 7], however an accurate fundamental model which can predict both growth rate and radial nonuniformity for a wide range of chemistries has yet to be developed. This paper presents an experimental evaluation of a fundamental model for 820

multiwafer LPCVD of polysilicon. This analysis demonstrates the capabilities of a relatively simple modeling approach, and suggests promising directions for future

research. UTCVD-P: A MODEL FOR POLYSILICON LPCVD Jensen, Graves and Roenigk have published the most comprehensive modeling work to date for this reactor [4, 5, 6, 7], using concepts from heterogeneous catalysis in their approach. Roenigk's multicomponent model [7] contained two one-dimensional species continuity equations, one for axial transport down the reactor tube and the other for radial transport into the region between each wafer pair. The two equations were coupled at the boundary between the annular and interwafer regions. The Stefan-Maxwell equations were used to relate mole fractions to molar fluxes [8]. An arbitrary number of gas and surface reactions were allowed in this approach. The modeling equations were solved by orthogonal collocation [9]. The derivation of any fundamental model must necessarily involve a trade-off between complexity and utility. The University of Texas Chemical Vapor Deposition of Polysilicon (UTCVD-P) model was developed specifically to investigate thermal variations within the reactor, and to assess the ability of a simplified model to predict experimental results for polysilicon deposition. Other important considerations, such as different chemical processes, a multicomponent gas phase and more complex geometry are not addressed by this model, although these extensions are included in a multicomponent LPCVD model (UTCVD-M) currently under development at The University of Texas. The UTCVD-P model developed here can be regarded as an extension of the Jensen and Graves model [4] to include axial and radial thermal variations, and the more recent kinetic expression published by Roenigk and Jensen [5]. The modeling assumptions include:

"* Multiwafer

hot wall LPCVD reactor, deposition section only

"* Steady-state ideal gas "* Binary gas phase system of silane and hydrogen "* Isobaric plug flow "* A single rate-limiting surface reaction, with the reaction Si) R = kjexp(-l8500/T)pj (mol m-sec + k3 p 1+ k

821

rate given by:

Miuttwater Hot-Wall Reactor Pressure Sonsor

3-Zone Furnace

Quartz Tube

5to205 Load Door

ooue

ae

Waer

Reactant Gases

Boat

UTCVD-P Represenlatlon

F-

K

reacantos vo '0 x0

I

AIl

0

I L

Figure 1: Multiwafer LPCVD Reactor and UTCVD-P Representation

"* Temperature

varies axially within the reactor as follows:

J T

"* Temperature

0.2 _ 0.8 Tp(()

(2)

varies radially across each wafer as follows: T.(ý, () = Te(C) + b(()(4' - 1)

b(C)

-

bo ~0.05 < C• 0.95 b, + b,(( - 0.05)2 C < 0.05

(3)

(4)

bo + bi(C - 0.95)' C > 0.95 Figure 1 shows a typical horizontal multiwafer LPCVD reactor and the corresponding geometry assumed by UTCVD-P. The reactor inlet and outlet sections are ignored by the model. The reactor is divided into two types of regions, the annular space surrounding the wafers, and the interwafer region between each pair of wafers. Isobaric plug flow is assumed for the gas phase, following Roenigk and Jensen [5]. This assumption is supported by direct experimental measurements performed

822

by Hitchman and co-workers [101, and allows the momentum balance to be dropped from consideration. Coltrin et al. [11] postulated that gas phase reactions are not important for this system below 630 degC, and that under these conditions the gas phase can be considered as a binary mixture of silane and hydrogen. We therefore assume a binary gas mixture undergoing a single rate-limiting surface decomposition. The kinetic rate expression used by UTCVD-P is taken from Roenigk and Jensen [5], although slightly different values for the rate constants have been computed in this investigation. The proposed functional forms for axial and radial thermal variations presented here are strictly empirical. They were chosen so as to fit patterns evident in experimental data. The quadratic axial variation function (2) is symmetric about the reactor midpoint, and falls off rapidly at both ends of the wafer load. The radial variation function (4) includes the built-in assumption that the total edge to center thermal drop is smallest at the reactor midpoint and increases toward the ends of the wafer boat. The temperature profile across a given wafer (3) is assumed to follow a quadratic profile and satisfies a symmetry condition at the wafer center. The three constants which define the thermal environment for the model must be estimated from experimental data. The UTCVD-P axial and radial model equations are identical to those derived by Jensen and Graves [4] with the exception of the inlet Danckwerts boundary condition [12]. The corrected form used here was also derived by Joshi [13]. The axial equation and boundary conditions are as follows: d

(VA-) d(

+ Re

- Pe(Dal + DaIz)g(x) = 0

d(C odxP (I +cXo)'Xo

l(6)

=0

(5) (6)

The axial dimension is scaled by the reactor length:

z L

(7)

The axial equation is affected by three dimensionless parameters: Pe = D--L

(8)

2Lr,(1 + a)R0o

(9)

vo(rt' - r,)clo 2Lr',Rl° Da 2 - vo(r2 r)co

10 (10)

823

The Peclet number Pe measures the strength of convection relative to diffusion. The Damkoehler numbers measure the strength of reaction on the tube and boat surfaces (Dal) and the wafers (Da 2) relative to convection. The dimensionless reaction rate is scaled by the rate at inlet conditions: (11)

R(x)

A dimensionless factor accounting for volumetric expansion and thermal effects also appears in the axial equation:

S=(1(1++)'X)'

(T) °.65

f/

12

The radial equation and boundary conditions are:

)_'X) +

i ( (_-_

1 g(X) = 0

=0

X1=Xb

(13) (14)

The radial dimension is scaled by wafer radius: r

(15)

The radial equation is affected by a single dimensionless parameter, the Thiele modulus 4, which measures the strength of reaction relative to radial diffusion: = AcoD

T)0

(16)

The effectiveness factor r measures the average reaction rate across a wafer relative to the rate at the wafer edge, and links the axial and radial equations together:

2 f, R(r)•r•dr RK,

(17)

As the effectiveness factor approaches one, the deposited film becomes more uniform. At a given position, the average film growth rate is computed as follows: G. = vi Rio g(x(C)) 7

824

(18)

The nonuniformity of the deposited film U. (standard deviation divided by mean) is determined by: U=

2 =

2

(o

1)

2

d

(19)

Nonuniformity increases as the effectiveness factor decreases from one. The model equations (5-6) and (13-14) were discretized by orthogonal collocation on finite elements [9], and the resulting nonlinear equations were solved by a HybridPowell method [14]. The steep thermal gradients of the assumed thermal profile required the use of a multiple element solution, rather than the single element approach used by Jensen and Graves [4]. The integrals in equations (17) and (19) were evaluated by Radau quadrature and the interpolated model solution was computed using Lagrange interpolation [15]. POLYSILICON DEPOSITION EXPERIMENTS Experimental data for polysilicon deposition have been collected from two reactors; an industrial scale system at SEMATECH and a research reactor at U.T. The SEMATECH system is a state-of-the-art horizontal BTU/BRUCE furnace, capable of processing up to 150 wafers in six boats of 25 wafers each. Table 1 describes the reactor geometry for the SEMATECH runs. Twenty-eight runs were performed with changes in temperature, inlet composition, total flowrate and pressure, following a Box-Behnken experimental design [16]. Although only the centerpoint runs are discussed here, a more detailed account of these experiments is available elsewhere [17]. The three centerpoint runs were performed at the following conditions; 615 degC, silane mole fraction 0.6 (in hydrogen), total flowrate 230 sccm, and pressure 325 mtorr. For each run, growth rate and film uniformity measurements were taken from monitor wafers at nine locations throughout the load. Monitor positions in the 150 wafer load were: 1, 13, 26, 51, 76, 101, 126, 138, and 150. A Prometrix FT-500 film thickness probe was used to measure the distribution of film thickness at 49 locations on each monitor wafer. Average growth rate was computed as the average of the 49 readings divided by the deposition time of one hour, and radial nonuniformity was computed as the standard deviation of the 49 measurements divided by the mean. The U.T. reactor system is a small research furnace, capable of processing up to 50 wafers in a single open boat. This reactor is about half the size of the SEMATECH system and runs four inch rather than six inch diameter wafers. Three runs were performed at the same process conditions; 615 degC, 322 mtorr, and a silane flowrate of 102 sccm. Table 1 describes the reactor geometry for the U.T. runs. A total of sixteen monitor wafers were measured for each run, providing a higher degree of detail for the axial variations in growth rate and radial nonuniformity. Monitor positions in the 50 wafer load were: 1, 4, 7, 10, 13, 19, 23, 25, 26, 28, 32, 38, 41, 44, 47 and 50. 825

Table 1: SEMATECH and U.T. Reactor Geometry Parameter

SEMATECH Reactor

U.T. Reactor

Reactor Length (m) TC 1 Location (m) TC 2 Location (i) TC 3 Location (i) TC 4 Location (m) TC 5 Location (W) First Wafer (m) Last Wafer (m) Injector 1 Location (m) Injector 2 Location (m)

2.286 0.572 0.793 1.13 1.51 1.61

1.186 0.330 0.483 0.635

0.744 1.47 1.14 1.36

0.466 0.703

Interwafer Spacing (m)

0.00479

0.00483

Tube Inner Radius (m) Wafer Radius (m)

0.160 0.075

0.075 0.050

Boat area/tube area

0.0732

0.0767

A Nanometrics Nanospec/AFT was used to measure the distribution of film thickness at 13 locations on each monitor wafer. Average growth rate was computed as the average of the 13 readings divided by the deposition time of 33 minutes, and radial nonuniformity was computed as the standard deviation of the 13 measurements divided by the mean.

MODEL COMPARISON WITH EXPERIMENTAL DATA Isothermal Case UTCVD-P model parameters were first estimated from the SEMATECH data for the case of an isothermal reactor. Optimal kinetic parameters kj, k2 , and k3 were estimated with a nonlinear parameter estimation package called GREG (General Regression) developed by Caracotsios [18]. The optimal isothermal parameter estimates, shown in Table 2, were found to be of the same magnitude as those reported by Roenigk and Jensen [5]. The intervals reported here are the higher posterior density (HPD) intervals for a 95% probability level. The intervals for our estimates are not symmetric because we estimated the logarithm of the parameters, rather than the parameters themselves. For the SEMATECH centerpoint conditions our estimated reaction rate is 1.6 x 10-moI Si/m 2sec, compared to 1.9 x 0l-mol Si/m 2 sec using the constants from Roenigk and Jensen. This discrepancy can be attributed to a number of factors, including the use of different data sets, models and estimation 826

Table 2: Optimal Isothermal Parameter Estimates Roenigk et al. Parameter {] Our Estimates

ki(molSi/m 2 secatm) k2(atm- 12) k 3 (atm -)

(2.2 < 3.7 < 6.4) x 10' (1.2 < 4.1 < 14) x 101 (0.8 < 1.5 < 2.7) x 10'

(1.2 < 1.6 < 2.0) x 10' (3.0 < 6.0 < 9.0) X 101 (6.0 < 7.0 0, the nucleation still can take place as long as Eg.(4) is valid. The larger the AGv the harder the nucleation and the more stable the layer . For CZ and FZ silicon, Gv(Cz) > Gv(FZ), so AGv(CZ) > AGv(FZ) because of Eqs.(3) and (5). Therefore, the interracial oxide layer in CZ silicon wafer pairs is more stable than that in FZ silicon wafer pairs, which is consistent with the experiment results. In our experiment, the much higher stability of the interfacial oxide layer in CZ silicon pairs, which is caused by higher concentration of interstitial oxygen and a little bit thicker initial oxide layer, makes the layer continuous. The further disintegration and final spheroidization of the oxide layer, which is mainly driven by the interface energy, have been discussed by Ahn et al.[5] in great detail.

Conclusion The SIMS depth profiles for thermal SiO 2 films after heat treatment at 10000C for 5 hours in 02 and N2 showed that a surface SiO 2 film grows with oxygen supplied from the ambient and the contribution of interstitial oxygen in not only FZ silicon but also in CZ silicon is negligible. It has been shown that the interfacial SiO2 layer in bonded FZ silicon wafer pairs disintegrated greatly during a bonding process at 12000C. The higher stability of interfacial SiO 2 layer in CZ silicon was explained by the higher concentration of interstitial oxygen which can increase the system free energy.

ACKNOWLEDGEMENTS The authors thank Shin-etsu Handotai (SEH) for financial support to this study. They are grateful to Dr. T. Abe (SEH) for his supply of bonded wafers and many helpful discussions, and to Dr. D. Griffs (NCSU) for his assistance in SIMS measurements.

878

REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] [10]

[11] [121

G. R. Wolstenholme, N. Jorgensen, F. Ashburn and G. R. Booker, J. Apple. Phys., 61,225(1987). H. Schaber, J. Bieger, T. F. Meister, K. Ehinger, and R. Kakoschke, Proc. IEDM , p170 (1987). M. Delfino, J. G. de Groot, K. N. Ritz, and P. Maillot, J. Electrochrem. Soc., 136,215(1989). K. -Y. Ahn, R. Stengle, T. Y. Tan, U. Goesele, and P. Smith, J. Apple. Phys., 65,561(1989). K. -Y. Ahn, R. Stengle, T. Y. Tan, U. Goesele, and P. Smith, Appl. Phys., A50,85(1990). T. Abe, A. Uchiyama, K. Yoshizawa, Y. Nakazato, M. Miyawaki, and T. Ohmi, Japan. J. Apple. Phys., 29,L2315(1990). ASTM Standards Vol.10.05, Section 10, 1984 (American Society for Testing and Materials). T. Abe, M. Nakano, Submitted to Proc. of 4th Intern. Symp. SO1 Tech. and Devices, Montreal, May 9 (1990). R. B. Black, S. D. Arthur, R. S. Gilmore, N. Lewis, E. L. Hall and R. D. Lillquist, J. Appl. Phys., 63, 2773 (1988). J. W. Christain, " The Theory of Transformations in Metals and Alloys", ed. by G. V. Raynor F. R. S. ( Pergam Press, Oxford) p415 (1965). K. Wang, "Solid State Physics", ed. by The People Education Press, China, p81 (1979). R. A. Craven, " Semiconductor Silicon", ed. by H. R. Huff, R. J. Kriegler and Y. Takeishi (Electrochemical Society, Pennington )p254 (1981).

879

ENHANCED DEGRADATION IN GERMANIUM IMPLANTED PMOSFETS L. P. Hobbs, A. von Schwerin & K. Maex. IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium. ABSTRACT The use of germanium amorphisation and boron implantation is an established technique in forming p+n- junctions for submicron PMOSFET processes. However little information is available on the influence of the germanium on the device degradation. In this work the influence of the germanium on the gate and substrate currents in a PMOSFET is investigated. It will be shown that the PMOSFET devices with germanium have degraded lifetime characteristics. A model is proposed which suggests that this degradation is due to an increased mean free path for the hole which is brought about by the decreased lattice strain in the germanium implanted device. INTRODUCTION Over the past number of years device degradation in MOSFET devices has been the subject of many investigations [1-51 as the topic becomes more important with todays ever shrinking device dimensions. Although most work has been conducted with NMOSFET [1-31 devices more studies are now being carried out to investigate the degradation in PMOSFET devices [4,51. Another topic that has been a major concern is the formation of shallow p+n- junctions [6,71 as such junctions are required in advanced MOS processes. A popular method to create these junctions has been to use germanium implantation to amorphise the silicon surface and by so doing to prevent the boron ion from channeling [7]. However little knowledge is available on the influence of germanium on the PMOSFET degradation. In a recent publication [3] Ng. et al have reported improved degradation results when germanium implantations have been used in NMOSFET devices. The purpose of this work was to investigate what influence the pre-amorphising germanium implants have on device degradation in PMOSFET devices. EXPERIMENTAL DESCRIPTION The starting material was 5 inch silicon wafers which had a resistivity of 15 K2cm. A LOCOS technique was used for device isolation and an anti-punch through implant of 1.4xl0 12 cm- 2 with phosphorus at 180keV was followed by a threshold adjust implant with boron of dose 1.7x1l012 cm- 2 and energy 20keV. A gate oxide of 15nm was grown at 900C and the deposited polysilicon was implanted with

880

phosphorus to yield a n+ gate. After polysilicon gate definition Ge was implanted with a dose and energy of lxlOl 5 cm- and 85keV into some of the wafers. Next all the wafers received a 1F2 implant of dose Ixl0 15 cm-2 and energy 20keV. A zero degree off-axis implant angle was employed. Spacers were subsequently formed using TEOS deposition and an anisotropic oxide etch. A second implant with BF 2 was then performed which had a dose and energy of lxl015 cm- 2 and 45keV. The junctions were then annealed using furnace annealing at 900C for various times. CoSi2 was formed on the junctions by reacting a deposited 20nm layer at 700C in N2.

Depth pgm

(b)

region

El

Ge/n

drain

n substrate

II

region Fig. 1 (a) SRP profile for a BF2 implant of dose and energy 1x101 5cm" 2 and 20keV into preamorphised silicon. The implant had an off-axis implant angle of zero degrees and the junction had been activated using a furnace anneal at 900C for 30 minutes. Also shown is the SIMS profile for

the amorphising germanium implant of dose and energy lxl015cm- 2 and 85keV. (b)Schematic representation of a PMOS device which has received an amorphising germanium implant. 881

After deposition of an inter-layer dielectric the contact holes were defined and the metalisation stage completed. The metalisation layer consisted of a bilayer of 100nm of TiW and lI.tm of Al/l%Si. MATERIAL AND ELECTRICAL CHARACTERISATION Both SIMS and SRP analyses were used to characterise the profiles of the various implants that were performed. This analysis revealed that there was no measurable difference in vertical junction depth between samples which did and did not receive a pre-amorphising implant. The reason for this lack of difference is thought to be due to the fact that the BF2 species acts as an efficient self-amorphising 15 species under these implant conditions [6].The SRP profile for the lxl0 cm-2 20keV BF2 implant, which has been activated using a furnace anneal of 30 minutes at 900C, can be seen in Fig. 1(a). Also shown here is the SIMS profile for the Ge implant. It is obvious that when germanium is used in such a pre-amorphisation scheme large concentrations of this.neutral ion will exist beyond the p+ region. As such the realisation of such a scheme in a MOS device will result in a device structure which is depicted schematically in Fig. l(b). The devices which have germanium in the channel exhibit similar junction leakage currents but higher substrate and gate currents, for the same bias conditions, than those devices in which there is no germanium. This increase in the gate and substrate currents can be observed in Fig. 2 (a) and (b) respectively, which display these characteristics as a function of gate current for a fixed drain voltage of -7.5V. (b)

(a)

IV Gs I(V)

I VGS I(V)

Fig. 2 (a) Gate Current and (b) substrate current versus gate voltage for devices with and without germanium implants. The gate length = l14m, junction depth = 1 10nm for both devices. VDS = 7.5V

882

The substrate current in a PMOS device is created from the impact ionization of channel holes near the drain with the created holes being swept into the drain and the electrons into the substrate where they give rise to the substrate current. In addition the gate current under the bias condition of VGS < VDS is composed of electrons which are injected into the gate from the substrate current [5]. Hence both the gate current and the substrate current in the PMOS device are a measure of the extent of the impact ionization that takes place near the reverse biased drain region. As such it is evident from Fig. 2 that a greater number of electron-hole pairs are generated by impact ionization near the drain of the device which has received the germanium implant. This fact is again illustrated in Fig. 3 where Isub/IDS is now plotted as a

function of the vertical junction depth ( as determined from SRP data) for similar bias conditions on all the devices. Here again it is observed that the devices which have germanium in the channel have an increased substrate current. Junction Activation Time (mins) 30

-5

+

40

50

60

.I.

10

- 010

-7 10

I r

110

1

I

125 120 115 Junction Depth (nm)

130

Fig. 3 Log-linear plot of tsub/tDS versus Junction Depth ( as measured by SRP ) and Junction Anneal Time for devices which (a) did and (b) did not receive a preamorphising Ge implant. Device gate length = tim. VDS = -4V & VGS = -2V.

In addition the behaviour of Isub/IDS with increasing junction depth is different for the two cases. This discrepancy can be explained as follows. The increase in Isub/IDS, for the devices with no germanium, with increasing junction depth is due to the fact that as the junction depth increases the effective channel length of the device will decrease. From [8) the maximum electric field in the channel of a device which has a gate oxide thickness Tox and junction depth of Xj can be expressed as follows

883

Em = VD - IVDsat .......... (1)

where 0 33 . 05 1 =0.22T x Xj. .......... (2)

and VDs1t

IVG-VtlEsatLeff

= IVG_-Vt + EsatLeff .

(3)

where Vt is the device threshold voltage, Esat is the channel field at which the carriers reach saturation velocity and Leff is the effective channel length. From (3) it can be seen that as the effective channel length decreases VDsat will also decrease and hence the maximum electric field increases. From [8] Isub may be expressed as -B IDSAEmI Em Isub= B e .......

(4)

The origins for A and B can be found in the expression for the ionization rate ct [8]. -B Em ax=A e

.......... (5)

Hence it is seen that an increase in junction depth brings about an increase in the maximum electric field which in turn will increase Isub/IDS. This increase in Isub/IDS is not observed in the devices which had received the germanium implant. In fact a slight decrease is observed with increasing junction depth ( Fig 3 ). This decrease is thought to be due to the fact that as the junction spreads more laterally into the channel then the size of the germanium/n region( recall Fig. l(b) ) is steadily reduced and hence the behaviour of the impact ionization approaches that of the standard device. The effect of the germanium on device lifetime is depicted in Fig. 4 where device degradation is plotted as a function of the gate length for devices with and without germanium in the channel ( Alsub/Isub was chosen as the parameter with which device degradation could be best compared as it was found to be most sensitive to changes in the channel ). The difference in the degradation between the two different types of devices can be attributed to the increased carrier injection into the gate oxide regions in the germanium implanted devices.

884

Device degradation in PMOS devices is known to be mainly due to electron injection into the oxide [5,9]. Hence the device with the higher substrate current will inject more electrons into the oxide and so enhance the device degradation. The decrease in the difference between the germanium device and standard device characteristic with decreasing gate length is due to the fact that as the gate length is reduced the increasing electric field begins to dominate and the effect of the germanium is somewhat masked.

0.9

S0.8 "

0.7

0.6

1.5

2.0 2.5 Gate Length (gm)

Fig. 4 Alsub/Isub versus Gate Length for devices which (a) did and (b) did not receive a germanium preamorphisation implant Stress time was 1 hour and stress conditions were VDS = -8V & VGS = 3.5V. Isub was taken as the maximum of the Isub versus VGS curve when VDS = -5V. Junction depth was I10nm. DISCUSSION The reason for the increase in substrate current and subsequent enhancement in device degradation in devices which have received germanium implants is not immediately evident. One possibility is that the mean free path of the carrier has been influenced by the inclusion of the germanium in the channel. In [3] Ng. et al argues that the suppression of the hot carrier degradation in NMOSFETs is due to a decreased mean free path of the hot electrons. If such a hypothesis were to be applied here then it could be concluded that in the PMOSFET device the inclusion of germanium leads to an increase in the mean free path of the hot hole. To investigate this possibility we return to equation (4) which when combined with (1) indicates that a log-lin plot of Isub/IDS(VD - VDsat) versus the inverse of (VD - VDsat ) will return a slope B1. Such curves are illustrated in Fig. 5 for devices with a junction depth of 1l0nm and 120nm. VDsat was determined using (3) assuming a value of 1.2x10 5 V/cm for Esat [10].

885

(a) 10

S10 S10*

10

Sto-~10

10 - 0.2

0.4

0.3

0.5

.0.6

(/V)

VD

VDsat

(b) 10 -3

Device with Ge Standard Device -u-

to 14 '5

t-~10

B = 2.8x10

10 -6; p

6

(V/cm)

10 -7

S10

6

-8

B = 3.2xl0 (Vjcm)

-9

lu

0.2

1

0.3

0.4 1 VD- VDsat

0.5

0.6

(/V)

Fig. 5 Log-linear ploys Of I sub/IDS* (VD - VDsat )) versus 1/ ( VD - Vbsat) for devices with and without germanium. Junctions depths were (a) I l0nm and (b) 120nm.

886

Using (2) B may be determined from the slope of the line is Fig. 5. A value of 3.2xlo 6 V/cm was returned for both cases in which no germanium had been used. This value for B is close to other published values [8,10]. When germanium preamorphisation was employed a somewhat lower value for B of 2.6x.0- V/cm was determined for the device with a junction depth of 110nm ( Fig. 5(a) ). When the junction depth was increased the value of B also increased to 2.8x10 6 V/cm (Fig. 5(b)). In [1] B was expressed as B

!L '.........(6) q2L

where (pi is the energy that a hole requires before it can create an electron-hole pair by impact ionization and X is the mean free path of the hole. Hence if pi is assumed to be the same in devices with and without germanium then the reason for the reduction in B in the germanium implanted devices is due to an increased X. Hence it can be easily calculated, using (6), that in the devices with a junction depth of 110nm ( Fig. 5(a) ) X has been increased by 23% in the germanium implanted device. When the junction depth is increased to 120nm the increase in X is reduced to 14%. The effect of this decreasing X , with increasing junction depth in the germanium implanted devices, was first observed in Fig. 3 and can be attributed to the decreasing influence of the germanium as the boron spreads more laterally into the channel beyond the germanium region. The increase in ?, in the Ge implanted devices could be due to the fact that germanium is expected to compensate the lattice strain that arises after high dose shallow implant/annealing of species such as boron [7]. This argument is supported by a recent work by Iwai et al. [11] in which they showed that increases in stress in the channel ( due to a nitrided gate in their case ) can produce lower hole mobilities in PMOSFETs and higher electron mobilities in NMOSFETs. CONCLUSION Devices which have been fabricated using Ge amorphising implants exhibit increased substrate and gate currents and subsequently degraded device lifetimes. The reason for this degradation is thought to be due to the fact that the germanium implant compensates for the lattice strain produced by the boron implant and so enhances the mean free path of the hole by as much as 23%.

887

ACKNOWLEDGEMENTS The authors would like to thank E. Simoen for useful discussions, B. Deweerdt for processing and W. Vandervorst for SRP and SIMS. K. Maex is a Research Associate of the Belgian Fund for Scientific Research.

REFERENCES [1] C. Hu, S. Tam, F. Hsu, P. Ko, T. Chan & K. Terrill, IEEE Trans. Electron Devices, vol. ED-32, p3 7 5 , February 1985 [2] F. Hsu & H. Grinolds, IEEE Electron Device Letters, vol. EDL-5, p71, March 1984. [3] K. Ng, C. Pai, W. Manisfield & G. Clarke, IEEE Electron Device Letters, vol. 11, p45, January 1990. [4] F. Matsouka, H. Hayashida, K. Hama, Y. Toyoshima, H. Iwai & K. Maeguchi, IEDM 1988, p. 18. [5] T. Ong, P. Ko & C. Hu, IEEE Trans. Electron Devices, vol. 37, p. 1658, July 1990. [6] L. Hobbs & K. Maex, Ext. Abs., Electrochemical Society Meeting, May 1990, ,vol 90-1, p. 6 9 3 . [7] D. K. Sadana, E. Myers, J. Liu, T. Finstead & G. Rozgonyi, Symposia Proceedings of the MaterialsResearch Society, Nov. 1983, vol 23, p. 303. [8] T. Ong, P. Ko and C. Hu, IEEE Electron Device Letters, vol EDL-8, p413, Sept 1987. [9] P. Heremans, R. Bellens, G Groeseneken and H. Maes, IEEE Trans Electron Devices, vol 35, p2194, Dec 1988. [10] C. A. Lee, R. A. Logan, R. L. Bardof, J. J. Kleimack and W. Wiegman, Phys. Rev. vol. 134, p. 761, 1964. [11] H. Iwai, H. Momose, S. Takagi, T. Morimoto, S. Kitagawa, S. Kambayashi, K. Yamabe & S. Onga, 1990 Synposium on VLSI Technology, Tech. Papers, Dig., p. 1 31.

888

AUTHOR INDEX Abe, T. .....................................................................................................

A00

Ahlbum , B.................................................................................................. Ahn, S. T ................................................................................................... Akiya, H ................................................................................................... Amazawa, T .............................................................................................. Andrews, J. M .............................................................................................. Apte, P. P.................................................................................................. Arita, Y...................................................................................................... Ashok, S.................................................................................................... Badgwell, T. A .......................................................................................... Bailey, D. E ................................................ Batchelor, D .............................................................................................. Bernt, H ............................................................................................... Bohland, J. F............................................................................................... Burger, W . R ...............................................................................................

617 650 861 276 409 755 276 483 820 785 851 120,445 155 650

Burroughs, J .................................................................................................

244

145 Calvert, J. M ............................................................................................... 391 Cam pabadal, F.......................................................................................... 765 Carl, D. A .................................................................................................. 692 Carruthers, R ............................................................................................. 26 Chan, H . C ............................................................................................... 582 Chapman, D. T ........................................................................................... 61 Chapman, R. C ........................................................................................ 692 Chapple-Sokol, J. D ................................................................................... 145 Chen, M .-S ................................................................................................. 285,330 Chevacharoenkul, S ............................................................................. 374 Chiacchia, C. H ........................................................................................ 78 Chin, G .................................................................................................... 382 Chiou, Y. L ................................................................................................. I Chiu, K.-Y ................................................................................................ 310,343 Choi, C. S ............................................................................................ ............................................. 635 Chu, H .................... ..... 541 Conrad, K. A.............................................................................................. 353 Cooper, J. R . ................................................................................................ 101 Cum m ings, K. D ........................................................................................... 503 Davis, C. J................................................................................................ 775 De Wolf, I ................................................................................................... 17 Deleonibus, S........................................................................................... 26 Dennison, C. H .........................................................................................

Dickerson, K.J............................................................................................

353

26,810 Ditali, A ............................................................................................... 627 Doan, T. T . .................................................................................................. 174 Donaldson, W . C ......................................................................................... 503 Dostalik, B................................................................................................ 739 Dubin, V. M ................................................................................................ 131,155 Dudley, B. W ....................................................................................... 145 Dulcey, C. S ................................................................................................

889

Dumin, D. J ................................................................................................. 353 Edgar, T. F . ................................................................................................ 820 Eichham mer, W .......................................................................................... 254 Elliott, J. K . ................................................................................................ 820 Fang, S................................................................................................... 473 Fazan, P. C............................................................................................. 26,810 Fitzgerald, E. A .......................................................................................... 164 Fonseca, L ................................................................................................. 391 Fordham , M . J . .......................................................................................... 582 Freeman, P. W ............................................................................................. 155 Friedrich, D ................................................................................................ 120 Frye, R. C .................................................................................................... 101 Fu, C. Y ...................................................................................................... 730 Fukuda,K .................................................................................................. 834 Galiano, M .................................................................................................. 617 Gambino, J. P............................................................................................. 382 Gasser, R .................................................................................................... 642 Geffken, R. M ............................................................................................. 667 Georger, J. H .............................................................................................. 145 Goodwin-Johannson, S.......................................................................... 131,174 Greene, W . M .............................................................................................. 431 Grider, D. T ................................................................................................. 296 Griffith, J. E ................................................................................................ 164 Grigg, D. A .................................................................................................. 164 Halimaoui, A . ............................................................................................ 712 Harris, G . ............................................................................................... 51 Hata, W . Y .......................................................................................... 190,199 Hauser, J. R ................................................................................................ 528 Heilemann, N . B ........................................................................................ 353 Hemicker, P ......................................................................................... 120,445 Hess, D. W ................................................................................................. 765 Heyns, M . .............................................................................................. 454 Hill, R. W ............................................................................................... 88 Hobbs, L. P ........................................................................................... 254,880 Hsu, R ........................................................................................................ 730 Hu, Y.-Z . .................................................................................................... 541 Hunn, J.D ................................................................................................. 343 Hutcheson, L. D ........................................................................................... 678 Inoue, MN................................................................................................ 421 Irene, E. A .................................................................................................. 541 Ishida, T ................................................................................................ 421 Itsum i, M . ................................................................................................... 861 Johns, P ................ ..... ............................................. 720 Johnsgard, K. E ........................................................................................... 566 Johnson, J. R .......................................................................................... 190,199 Jones, S. K............................................................................................ 131,155 Kakum u, M . ................................................................................................... 1 Kambayashi, S ......................................................................................... 52 Kapoor, V. J ................................................................................................ 657 Kar, S........................................................................................................ 483 Kawaguchi, E ........................................................................................... 52 890

Kellam, M . D......................................................................................... Kermani, A ...............................................................................................

61,131 566

Kobayashi, K .............................................................................................

183

Kopley, T. E.......................................................................................... Kronschnabel, J . ..........................................................................................

431 642

305 Kuan, T. S .................................................................................................. 503 Kuehne, J................................................................................................... 454 Kuper, W .................................................................................................. 321 Kuwabara, H .............................................................................................. 363 Kwong, D. L ................................................................................................ 120,445 Lange, P............................................................................................... 730 Law, B....................................................................................................... 34,78 Law, M . E ................................................................................................ 606 Leggett, R................................................................................................... 382 Li, G . .......................................................................................................... 374 Lin, D.-G .................................................................................................... 870 Ling, L . ....................................................................................................... . ........................... 26 Liu, Y................................................................. 363 Lo, G. Q ...................................................................................................... 26 Lowrey, T. A ............................................................................................. 464 M a, T. P . ..................................................................................................... 775 M aes, H. E . ................................................................................................. 254,880 Maex, K ............................................................................................... 851 M aher, D. M . .............................................................................................. 400 M akihara, K. ............................................................................................. 88 M aldonado, J. R ....................................................................................... 174 M arkus, K. W .............................................................................................. 183 M aruyama, T .............................................................................................. 541,574 M assoud, H. Z ..................................................................................... 26,800,810 M athews, V. K ................................................................................ 226 M atsuda, K ............................................................................................... 52 M atsunaga, J........................................................................................... 236,834 M atsuura, T .......................................................................................... 606 M aury, A.................................................................................................... 353 M cAllister, P. A ......................................................................................... 473 M cCarthy, A. M .................................................................................... 285, 330 M cGuire, G. E....................................................................................... 206 M cNevin, S. C............................................................................................. 473 M cVittie, J. M . ...................................................................................... 582 M elzak, J. M .................................................... 454 M euris, M ............................................................................................... 164 M iller, G. L ................................................................................................. 266 M iyake, M .................................................................................................. 52 M izushim a, I........................................................................................... 17 M olle, P ................................................................................................... 606 Monnig, K ................................................................................................... 642 M orim oto, S. ............................................................................................ 400 M orita, M . .................................................................................................. 503, 755 M oslehi, M . M ..................................................................................... 305 M oy, D ....................................................................................................... 861 M uramoto, S ...............................................................................................

891

M urota, J.............................................................................................. M yInko, W ..................................................................................................

236,834

Najm, H ....................................................................................................

503

244

Nakagawa, 0. S . ........................................................................................ 431 Nakayama, S ........................................................................................ 9,861 Nakazato, Y .............................................................................................. 400 Nalamasu, 0 .............................................................................................. 110 Nguyen, L. N........................................................................................ 190,199 Norstr6m , H ................................................................................................ 775 Novembre, A. E ........................................................................................... 110 Nowak, R ................................................................................................... 617 Oberlin, J. C ................................................................................................ 712 Ohmi, T.................................................................................. 236, 321,400,834 Ohta, K ..................................................................................................... 749 Oka, H . ...................................................................................................... 749 Okada, T. K............................................................................................. 52 Olsen, J . ...................................................................................................... 617 Olson, K ..................................................................................................... 692 Ong, E ....................................................................................................... 635 Onga, S ................................................................................................... 52 Onishi, S .................................................................................................... 226 Ono, S .................................................................................................. 236,834 Osburn, C. M .............. ........................................................ 285,310,330,343 Otsuki, M .................................................................................................... 321 Ott, J. A ...................................................................................................... 305 Owada, N .................................................................................................. 793 Oztiirk, M . C .................................................................... 296,528, 582,841,851 Palleau, J................................................................................................... 712 Pandey, A .................................................................................................. 483 Patrick, W . ) . .............................................................................................. 692 Patterson, J. D . ............................................................................................ 841 Pavelchek, E. K .......................................................................................... 155 Peckerar, M . C ...................................................................................... 145,409 Pelka, M .............................................................................................. 120,445 Peters, C ..................................................................................................... 131 Peters, D........................................................................................................ Philipossian, A .......................................................................................... 454 Pierce, J. M .................................................................................................. 650 Pinto, M . R ............................................................................................... 43 Queller, S . .................................................................................................. 642 Raaijm akers, I . ........................................................................................... 635 Raychaudhuri, A ....................................................................................... 483 Reism an, A . ................................................................................................ 493 Renteln, P .................................................................................................. 650 Rhodes, H. E........................................................................................... 26 Rietman, E. A .............................................................................................. 101 Rogers, W . B .......................................................................................... 61,174 Rom ano-Rodriguez, A ............................................................................... 775 Ruggles, G. A ........................................................................................ 310,343 Russell, P. E................................................................................................ 164 Saito, A ..................................................................................................... 749

892

276 Saito, K ...................................................................................................... 226 Sakiyama, K.............................................................................................. 541,574 Sampson, R. K ..................................................................................... 216 Samukawa, S .............................................................................................. 627 Sandhu, G. S . .............................................................................................. 851 Sanganeria, M ............................................................................................ 551,755 Saraswat, K. C .................................................................................... 61 Sayer, R. W ............................................................................................. Schliwinski, H. J ......................................................................................... 120 445 Schmidt, L ................................................................................................. 145 Schnur, J. M ................................................................................................ Schoen, P. E ................................................................................................. 145 692, 720 Schwartz, G. C.................................................................................... Shah, A. S ................................................................................................. 343 5 Shimohigashi, K ..................................................................................... 870 Shimura, F ................................................................................................. 606 Sivaram , S .................................................................................................. 528,582 Sorrell, F. Y . ........................................................................................ 382 Sow, C. H ................................................................................................... 409 Sprangle, E. A ............................................................................................. Stagam an, G. J ...................................................................................... 190,199 120 Staudt-Fischbach, P .................................................................................... 749 Takahara, Y . ............................................................................................. 712 Tem plier, F ............................................................................................... 400 Teramoto, A ............................................................................................... Thane, N . S ................................................................................................. 199 592 Ting, C. H ................................................................................................... ..... ............................................. 363 Ting, W ............................ 421 Todokoro, Y ................................................................................................ Tolles, R . .................................................................................................... 606 712 Torr6s, J.............................................. 820 Trachttenberg, I . ......................................................................................... Tsang, P. J................................................................................................... 382 400 Uchiyama, A ............................................................................................. Uetake, H ............................................................................................ 236,834 775 Vanhellem ont, J .......................................................................................... 244 Varhue, W .................................................................................................. 164 Vasile, M . J................................................................................................. Velo, L ....................................................................................................... 503 454 Verhaverbeke, S ........................................................................................ 880 von Schwerin, A ......................................................................................... 164 Wagner, E. R ............................................................................................... 493 Walters, M . ............................................................................................... 305 W ang, L. K .................................................................................................. 635 Wang, S.-Q .............................................................................................. W indbracke, W ................................................................................... 120,445 566 W ong, F . ..................................................................................................... 551 W ood, S. C................................................................................................ 296, 528, 582, 851 Wortman, J. J ..................................... Xing, G. C ............................................................................................. 310,343 52 Yamabe, K ...............................................................................................

893

Yam aguchi, H ............................................................................................. 793 Yano, K ...................................................................................................... 183 Yasaitis, J. A .............................................................................................. 374 Yeakley, R.......................................................................................... 503,755 Yin, D ........................................................................................................ 503 Yoneda, K .................................................................................................. 421 Yoshino, H ............................................................................................ 861 Yu, C .................................................................................................... 627, 800 Zhang, B .................................................................................................... 851 Zhong, Y. L . ................................................................................................ 851 Zwicker, G .................................................................................................. 120

894

SUBJECT INDEX Ab-Initio Molecular Orbital ........................................................................ Ablation, Optical .......................................................................................

751 631

AC Conductance .........................................................................................

487

427 Acceleration Factor, Electric Field .............................................................. 489 Accumulation Capacitance ......................................................................... 155 Acid-Hardened Resist ................................................................................. 767 Actinometry ................................................................................................ 312 Activation Energy ...................................................................................... 740 Activation Solution ..................................................................................... 105 Adaptive Learning ...................................................................................... 153,203 Adhesion ............................................................................................ 483 Adm ittance Characteristics, Small Signal .............................................. 236 Adsorption .................................................................................................. 121 Advanced Drain Engineering ....................................................................... 423 AES Analysis ......................................................................................... 400 AFM ........................................................................................................... 343,635 Al ........................................................................................................ 739 Al Cladding ............................................................................................... 216 Al-Si-Cu .................................................................................................... 409 AI-Si0 2 M etallurgical Reaction ............................................................. AI-SiO 2 -Si M OS Devices ........................................................................ 402 751 Alcohol ..................................................................................................... 121 Alignment Accuracy, W afer ........................................................................ 851 Alloys, SixGea_x .......................................................................................... 343,635 Aluminum ........................................................................................... 470 Aluminum Gate ....................................................................................... 880 Amorphization .......................................................................................... 285 Amorphization Depth ............................................................................... 308 Amorphization, Ge ..................................................................................... 313, 346 Amorphous .......................................................................................... 312 Amorphous Phase ...................................................................................... 813 Amorphous Silicon ...................................................................................... 755 Anhydrous .................................................................................................. 236,252 Anisotropy ........................................................................................... 528 Annealing ................................................................................................... 285 Annealing of Defects ................................................................................... Annealing Techniques for Process-Induced Radiation .................................... 464 794 Annealing, Drive-In ................................................................................... 470 Annealing, High Pressure Thermal .............................................................. 470 Annealing, RF Plasma ................................................................................. 469 Annealing, Thermal .................................................................................... 769 Anodization ................................................................................................ Antenna Effects, Charge Sharing ............................................................ 473 473 Antennas, Polysilicon Gate ..................................................................... 421 Anti-Fuse .................................................................................................... 133,146 Anti-Reflection Coatings ...................................................................... 592 AP-TEOS ....................................................................................................

895

AP-TEOS/Ozone .........................................................................................

593

715 Aqueous Acidic M edia ................................................................................. Ar .......................................................................................................... 18,835 133 ARC ........................................................................................................... 835 Argon .......................................................................................................... 148 Argon Fluoride ............................................................................................ 720 Aspect Ratio ............................................................................................... 132 Astigmatism ............................................................................................... 592 Atmospheric Pressure TEOS ......................................................................... Atomic Fluorine .......................................................................................... 208 400 Atomic Force M icroscope .............................................................................. 470 Atomic Hydrogen ........................................................................................ 18, 713 Auger Analysis ...................................................................................... 296 B ................................................................................................................ B Diffusivity ........................................................................................... 13 15 B Diffusivity in Single Crystal Si ............................................................ 9 B-Doped Polysilicon .......................................... B-Ge Doped Si Membrane ............................................................................ 121 B2 0 3 . . . . ........................................................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .617 Ballistic Deposition Simulation ................................................................ 61 Band Gap .................................................................................................... 327 Barrier ................................................................................................ 343,635 324 Barrier Height, Schottky ............................................................................ Barrier Layer, TiN ...................................................................................... 628 795 Base Profile ................................................................................................ 46 BEBOP ..................................................................................................... BF 2 . . . ..................................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 296,880 152 Bias Stress .................................................................................................. 602 Bias-Sputtered-Quartz ............................................................................... BiCM OS Device, Low-Voltage .................................................................. 5 BiCMOS Technology, Half-M icron ............................................................ 5 BiNCM OS Technology ............................................................................... 5 153 Biocompatability ....................................................................................... 5,655 Bipolar ................................................................................................ 566 Bipolar Poly-Emitter ............................................................................ 17,139 Bird's Beak ............................................................................................ Bit Line, Buried ...................................................................................... 28 Boltzmann-Based Carrier Transport ......................................................... 43 Bond .......................................................................................................... 237 838 Bond Energy ................................................................................................ 870 Bonded W afer Pairs .................................................................................... 296 Boron .......................................................................................................... 13,347 Boron Diffusion ...................................................................................... Boron Diffusivity in Single Crystal Si ..................................................... 15 880 Boron Difluoride ......................................................................................... Boron Penetration, Suppression of .............................................................. 9 617 Boron Trioxide ........................................................................................... 266 Boron-Doped Layer ..................................................................................... Boron-Doped Polysilicon ............................................................................ 9 17 Borosilic3te Glass Planarization ..............................................................

896

Bottom -Oxide ............................................................................................. 421 313,346 Boundary Diffusion .............................................................................. 315 Boundary Layer ......................................................................................... 642 BPSG .......................................................................................................... 31 Breakdown ............................................................................................... 402 Breakdown Events ...................................................................................... Breakdown M easurem ents of SiO 2 .................................... . . . . . . . . . . . . . . . . . . . . . . . . . .. . 448 17,458 Breakdown of Gate Oxide ...................................................................... 353 Breakdown of Oxides .................................................................................. 454 Breakdown Statistics ............................................................................. 409 Breakdown Strength, Dielectric ............................................................ 396 Breakdown, Charge to ................................................................................. 423, 724 Breakdown, Dielectric ......................................................................... 360 Breakdown, Oxide ..................................................................................... 358 Breakdown, Ram p Voltage .......................................................................... 396 Breakdown, Time Dependent ....................................................................... 394 Breakdown, Time Zero ................................................................................ ... . ........ 394 Breakdown, TZBD ............................. 359 Breakdown-W earout Com parisons .............................................................. 17 BSG Planarization ................................................................................... 602 BSQ .......................................................................................................... 566 Budget, Thermal ...................................................................................... 486 Bulk Silicon Traps .................................................................................. 28 Buried Bit Line ......................................................................................... 137 Buried Channel .......................................................................................... ............... ............................................. 354 C-V Analysis ............................ 11,423 C-V Characteristics, High Frequency .................................................... 392 C-V Characterization ................................................................................. 801,811 C-V M easurement ................................................................................. 592,602 C/M Polishing ..................................................................................... C 2 F 6 . . . . . ..................................................... . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 12,84 Capacitance ........................................................................................... Capacitance, Cell .................................................................................... 30 803 Capacitance, DRAM Cell ............................................................................ 354 Capacitance-Voltage Analysis .................................................................... 392,423 Capacitance-Voltage Characteristics ................................................... 801,811 Capacitance-Voltage M easurem ent ...................................................... 810 Capacitor Cells, 16 and 64 M bit DRAM ........................................................ 421 Capacitor Insulator ..................................................................................... 810 Capacitor Structures, Reliability ................................................................ 26 Capacitor, Stacked .................................................................................. 28 Capacitors ............................................................................................... Capacitors, DRAM , Electrical Characteristics ............................................. 800 391 Capacitors, M OS ......................................................................................... 567 Capacitors, PM OS ....................................................................................... 209 Carbonaceous M aterial ................................................................................ 149 Catalyst ..................................................................................................... 30 Cell Capacitance ..................................................................................... 800, 803 Cell Capacitance, DRAM ..................................................................... 78 Cell Design, DRAM ..................................................................................

897

Cells, 16 and 64 Mbit DRAM Capacitor .......................................................

810

Cells, Leakage Current in DRAM ................................................................. 803 266 Channel Doping .......................................................................................... 137,881 Channel Length ................................................................................... 296,881 Channeling .......................................................................................... 449 Characteristics, Transfer ............................................................................. Characterization ....................................................................................... 310 190 Characterization of I-Line Photoresist ........................................................ 447 Characterization of SiO 2 Gates ................................................................... 473 Charge Build-Up During Plasma Processing ................................................. 661 Charge Centroid ......................................................................................... 431 Charge Injection .......................................................................................... 451 Charge Pumping .......................................................................................... 183 Charge Reduction ........................................................................................ 473 Charge Sharing Antenna Effects .................................................................. 375,396 Charge to Breakdown ........................................................................... 183 Charge Transfer Complex ............................................................................ ................... .. 377,428,803 Charge Trapping ........................................... 183 Charge-Reducing Process ............................................................................. 358,359 Charge-to-Breakdown ......................................................................... 183 Charging of Resist ....................................................................................... 311,344 Chem ical Inertness ............................................................................... 276,503,528,582,692 Chemical Vapor Deposition ............................................. 566 Chemical Vapor Deposition, Rapid Thermal ..................... 592, 602,606,650 Chem ical-M echanical Polishing ............................................. 110,146 Chem ically Amplified Resists ............................................................. 153 Chem isorbed Films .................................................................................... 570 Chem istry, Silane .......................................................................................

CH F3 .. .. ...................................................

... ...... ..... ..... .... ..... ...... ..... ..... . . . .

18

236,440,730 Chlorine ....................................................................................... 236,440 Cl ........................................................................................................ C12 . . . ...................................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209,730 739 Cladding, Al ............................................................................................... 568 Clean, Hydrogen ........................................................................................ 834 Cleaning ..................................................................................................... Cluster Tool M odeling and Economics ........................................................... 551 Cluster-Based Fabs ..................................................................................... 551 1,655 CM OS ..................................................................................................... 374 CM OS Devices, 0.5 gm ................................................................................. 49 CM OS Latchup ......................................................................................... ............... ................................. 131 CM OS Process, 0.5 M icrometer ............... 120 CMOS Ring Oscillator ................................................................................. CMOS Technology, Scaled ....................................................................... 44 120 CM OS, 0.4 pIn Test Circuit ........................................................................... 174 CM OS, 0.8 pm ............................................................................................. 17, 199,305 CM OS, Sub-Micron ......................................................................... 607, 650,651 CM P ............................................................................................. 254 Co-Silicide ................................................................................................. 149 Cobalt ........................................................................................................ 122 Cobalt Disilicide ........................................................................................

898

131 Cobalt Salicide ........................................................................................... 310 Cold Wall System ....................................................................................... 149 Colloidal Pd/Sn Catalyst ........................................................................... 885 Compensate ................................................................................................ Complementary BiCMOS .......................................................................... 5 14 Complementary Error Function ................................................................. 681 Compound Semiconductors ........................................................................... 445 Condensed Matter, Electronic Structure ........................................................ 445 Condensed M atter, Optical Properties ......................................................... 31 Conduction ............................................................................................... 813 Conduction, Poole-Frenkel ........................................................................... 311,344 Conductivity ........................................................................................ 739 Conductor Pattern Formation ....................................................................... 359 Constant-Voltage Stressing ......................................................................... 148 Contact Printing .......................................................................................... 254,328 Contact Resistance......................................... 276 Contact, Ohmic .......................................................................................... 28 Contacts .................................................................................................. 151,861 Contamination ..................................................................................... 541, 574 Control of Temperature ........................................................................ 110 Copolymer Backbone ................................................................................... 112 Copolymer M olecular Properties .................................................................. 149 Copper ........................................................................................................ 667 Copper-Interconnect .................................................................................... 325 Copper-Silicon Contact ............................................................................... 745 Corrosion Resistance .................................................................................... CoSi 2 .. . ....................................................... .. ..... .... ..... .. ... ...... ..... ..... .... ..... ..122 551 Cost Modeling of Semiconductor Fabs .................................. 244 Cryogenic Etching ....................................................................................... 183 Crystal Growth, TCNQ ............................................................................... 795 Crystalline Imperfection ............................................................................. 343 Cu ............................................................................................................... 216 Cu Residue .................................................................................................. .... ....................................... 667 Cu-Interconnect ........................................... 325 Cu-Si Contact .............................................................................................. 712 Cu/PPQ ..................................................................................................... 414 Cumulative Probability of Failure ............................................................... 648 Cure Time of SOG ....................................................................................... 216 Current Density, Ion .................................................................................... Current Distribution, 3D .......................................................................... 49 813 Current, Leakage ......................................................................................... 423,811 Current-Voltage Characteristics .......................................................... 433 C-V ....................................................................................................... 276,503,528,532,534,582,692 CVD ................................................................... 650 CVD Oxide ................................................................................................. 720 CVD SiO 2 , Plasma-Enhanced ..................................................................... 566,851 CVD, Rapid Thermal .......................................................................... Cylindrical Tube Based Rapid Thermal Processor ........................................ 582 401 Czochralski Si W afers ................................................................................ 834 Damage ......................................................................................................

899

285 Dam age Rem oval ........................................................................................ 473 Damage, Gate Oxide ................................................................................... 34,39 Dam age, Implantation ............................................................................ 664 Dangling Bonds ........................................................................................... 78 Data Representations ............................................................................... 43 DD System ................................................................................................ Deactivation of Dopants ........................................................................ 488 5 Deep Subm icron ........................................................................................... 147 Deep UV .................................................................................................... 131 Deep UV Excimer Laser Stepper .................................................................. 110, 145,155 Deep UV Lithography .................................................................. 285 Defect Annealing ........................................................................................ 395 Defect Density ............................................................................................ Defect Distribution ..................................................................................... 495 Defect Generation .................................................................................. 465 384 Defect Related Breakdown .......................................................................... 483 Defect States .............................................................................................. 413 Defect-Induced Dielectric Breakdown ..................................................... 41 Defects, Extended .................................................................................... 34,84 Defects, Point.......................................................................................... 179 Degradation, Hot Carrier ............................................................................ 602 Dep/Etch Cycles ........................................................................................ 720 Dep/Etch Process ........................................................................................ 12 Depletion Layer ....................................................................................... 314 Depletion of Input Gases .............................................................................. 315 Deposition Efficiency .................................................................................. 312 Deposition Kinetics ..................................................................................... 801 Deposition of Polysilicon ............................................................................. 740 Deposition Solution ..................................................................................... 695 Deposition Temperature .............................................................................. 468 Deposition, E-Gun and Sputter ..................................................................... Deposition, In-Situ ..................................................................................... 567 810 Deposition, Polysilicon ............................................................................... 851 Deposition, Selective ................................................................................. 607 Deposition-Etch-Deposition Technique ........................................................ 206 Deposition/Etching, Plasma ....................................................................... Depth of Amorphization ............................................................................. 285 133 Depth of Field ............................................................................................ 120,132, 145,606 Depth of Focus ........................................................................ 871 Depth Profile, SIM S ................................................................................... 1 Design ........................................................................................................... 78 Design, DRAM Cell .................................................................................. 598 Desorbed Gas .............................................................................................. 208 Detection of End-Point ................................................................................ 398 Detrapping, Electron ................................................................................... 191 Developer ................................................................................................... 1 Device Design ................................................................................................ 881 Device Lifetime ............................................................ 624 Device Perform ance ................................................................................... 43 Device Scaling ......................................................................................... 78 Device Simulation ..................................................................................

900

Device Simulation Grid ...........................................................................

81

Device Simulators ................................................................................... 43 Devices, CM OS, 0.5 rm................................................................................ 374 Devices, M OS ...................................................................................... 363,464 124 DIBL .......................................................................................................... Dielectric ................................................................................................... 592 Dielectric Breakdown ...................................................... 374, 385, 401, 423, 724 Dielectric Breakdown Fields, Histogram of ................................................. 413 Dielectric Breakdown Histogram ................................................................ 425 Dielectric Breakdown of Gate Oxide ......................................................... 17 Dielectric Breakdown of Si02 ...................................... . . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . . 697 Dielectric Breakdown Strength .............................................................. 409 Dielectric Breakdown, Ramped-Field M ethod ............................................. 409 Dielectric Breakdown, Stepped-Field Method .................... 409 Dielectric Constant .............................................................................. 692, 724 Dielectric Degradation ............................................................................... 418 Dielectric Deposition .................................................................................. 593 Dielectric Engineering ................................................................................. 569 Dielectric Integrity ..................................................................................... 374 Dielectric Properties of M aterials ............................................................ 445 Dielectric Reliability .......................................................................... 421,803 Dielectric Strength .............................................................................. 395,692 Dielectric, O /N ..................................................................................... 29,801 Dielectric, Reoxidized Nitride .................................................................... 801 Dielectrics, Gate ......................................................................................... 363 Dielectrics, Ultrathin SiO 2 Gate ................................................................. 445 Diethylsilane, Pyrolysis of ........................................................................ 841 Diffusion ................................................................................ 296, 313, 346,347 Diffusion Barrier ........................................................................................ 343 Diffusion Coefficients, Interstitial and Vacancy ...................................... 52 Diffusion M odel, Point-Defect ................................................................. 52 Diffusion of Oxygen ..................................................................................... 871 Diffusion Source for Boron ............................................................................ 296 Diffusion, Dopant .................................................................................... 34 Diffusion, Extrinsic .................................................................................. 41 Diffusion, Oxidation Enhanced ................................................................ 34 Diffusion, Transient Enhanced ................................................................. 34,39 Diffusivity of B in Single Crystal Si .......................................................... 15 Diluted Oxidation Technique ...................................................................... 391 Dipolar Structure ........................................................................................ 500 Disintegration of Oxide Layer ..................................................................... 871 Distortion ................................................................................................... 132 DM SDM A ................................................................................................. 155 Dopant Diffusion ................................................................................... 34,793 Dopant Profiles ........................................................................................... 336 Doped Polysilicon, Phosphorus .................................................................... 803 Doping Effects, Substrate ............................................................................. 357 Doping Profile, Retrograde ......................................................................... 122 Dosage ........................................................................................................ 148 Dose, Oxygen .............................................................................................. 568

901

Double Layer, Electrical ............................................................................. 749 Double Level M etallization ...................................................................... 17 Double-Level Interconnect ........................................................................... 730 Drain Current .............................................................................................. 379 Drain Engineering ....................................................................................... 121 Drain Induced Barrier Lowering ................................................................... 124 DRAM ................................................................................................. 422, 785 DRAM Analysis ....................................................................................... 83 DRAM Capacitors, Electrical Characteristics .............................................. 800 DRAM Cell Capacitance ...................................................................... 800,803 DRAM Cell Design .................................................................................. 78 DRAM Cells, 16 and 64 M bit ........................................................................ 810 DRAM Cells, Leakage Current ............................... 803 DRAM 's .................................................................................................. 26 DRAM , 16 M egabit ...................................................................................... 617 DRAM s, 64 M bit ....................................................................................... 33 Drift Diffusion System ............................................................................ 43 Drive-In Annealing ..................................................................................... 794 Dry Etching ............................................................................................. 18 Dry Etching Si/SiO2 ........................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Dry Oxidation ............................................................................................ 423 Dummy Pattern ........................................................................................... 596 E-Beam Lithography .................................................................................. 466 E-Gun Deposition ........................................................................................ 468 ECL ........................................................................................................... 5 Economic Modeling of Semiconductor Fabs .................................................... 551 Econom ics of Cluster Tools ............................................................................ 551 ECR .......................................................................... 216, 236, 244, 602, 607,834 ECR Plasma ................................................................................................ 765 EEPROM ................................................................................................ 422 Effective Channel Length ............................................................................ 881 Eg Center .................................................................................................... 493 Elastic Recoil Detection Analysis ................................................................ 715 Electric Field .............................................................................................. 881 Electric Field Acceleration Factor ................................................................ 427 Electrical Characteristics of DRAM Capacitors ........................................... 800 Electrical Characterization of Si0 2 Gates .................................................... 448 Electrical Conductivity ........................................................................ 311,344 Electrical Double Layer ............................................................................... 749 Electrical Field Distribution ....................................................................... 741 Electrical Interconnects ................................................................................ 678 Electrical Properties of Gate Oxides ............................................................ 400 Electrical Properties of Interfaces ................................................................ 445 Electrical Properties of Surfaces .................................................................. 445 Electrical Properties of Thin Films .............................................................. 445 Electrochem ical Effects of HF...................................................................... 712 Electroless Deposition ................................................................................. 145 Electroless M etal Deposition ....................................................................... 739 Electroless Plating ...................................................................................... 149 Electromigration Failure ............................................................................ 632

902

101,183,466 Electron Beam Lithography .......................................................... 216,236,244,385,602 Electron Cyclotron Resonance ............................................ 765 Electron Cyclotron Resonance Plasma ........................................................... Electron Density .....................................................................................

Electron Injection ...........................................................................

49, 751

433,880,881

494 Electron Injection, Optically Assisted .......................................................... 500 Electron Spin ............................................................................................ 502 Electron Spin Resonance ............................................................................... Electron Storage Ring .............................................................................. 88 398 Electron Trapping and Detrapping ............................................................... Electron-Gun Deposition ........................................................................ 468 Electron-Hole Recombination .................................................................. 499 Electronic Structure of Condensed M atter...................................................... 445 445 Electronic Structure of Interfaces .................................................................. 445 Electronic Structure of Surfaces .................................................................... 445 Electronic Structure of Thin Films ................................................................ 467 Electrons ................................................................................................. 541,574 Ellipsometry ........................................................................................ Emissivity..................................................................................................528 529 Emissivity of Si .......................................................................................... 795 Em itter Profile ............................................................................................ 568 Emitter Resistance ..................................................................................... Emitter-Coupled Logic .............................................................................. 5 655 Encroachment .............................................................................................. 179 End-of-Life Test .......................................................................................... 208 End-Point Detection .................................................................................... 657 Endurance ................................................................................................... 216 Energy Distribution, Ion .............................................................................. Engineering, Dielectric ............................................................................... 569 570 Engineering, Interface .................................................................................. 880 Enhanced Degradation ................................................................................ 34 Enhanced Diffusion, Oxidation ................................................................ 34,39 Enhanced Diffusion, Transient ................................................................. Enhanced Physical Models ...................................................................... 46 305 Enhanced Silicide Formation ...................................................................... Enhancement of M iscibility ...................................................................... 230 305 Epi Growth, Selective ................................................................................ 306 Epitaxial Silicon ..................................................................................... 755,834 Epitaxy ............................................................................................... Equivalent Circuit Diagrams .................................................................. 486 715 ERDA ......................................................................................................... ESR ........................................................................................................... 502 607 Etch Back of Resist ..................................................................................... 250 Etch Mechanisms ........................................................................................ 248 Etch Profiles ............................................................................................... 648 Etch Rate and Selectivity of SOG:BPSG ...................................................... Etch-Back of Spin-On-Glass .................................................................... 17 596 Etchback Planarization ............................................................................... 236,244 Etching ................................................................................................ Etching Si/SiO2 .............................................. ..... ..... ...... ... ...... ..... ..... .... .... .208

903

Etching, Reactive Ion and Plasma ............................................................ 466 206 Etching/Deposition, Plasma ....................................................................... 752 Ethanol, 2-Amino ........................................................................................ 199 Evaluation of I-Line Photoresist .................................................................. 61 Evaporation M odeling .............................................................................. 800 Excimer Laser Processing .............................................................................. 131 Excimer Laser Stepper, 248 nm ..................................................................... 785 Experimental Design ................................................................................... Experimental Simulation of Radiation Effects ............................................. 471 446 Experimental Wafer Processing ................................................................... 193 Exposure ..................................................................................................... 120 Exposure Field Size ..................................................................................... 90 Exposure System ...................................................................................... 606 Exposure Tools ............................................................................................. 41 Extended Defects ...................................................................................... 44 Extrinsic Device Effects ............................................................................. 41 Extrinsic Diffusion .................................................................................. 440 F ................................................................................................................. 551 Factory Performance Simulation ................................................................. 32 Failure ..................................................................................................... 12 Fermi Level ............................................................................................. 402 Field Enhancement ...................................................................................... Field Oxide, Quasi-Recessed .................................................................. 17 722 Filaments ................................................ 312 Film ........................................................................................................... 801,811 Film Reflectance .................................................................................. ................. .................................. 153 Film s........ ..................... Films, Thin SiO2 .............................................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391 770 Fixed Charge .............................................................................................. 493 Fixed Positive Charge ............................................................................ 11,569 Flatband Voltage ................................................................................... 376 Flatband Voltage Shift ............................................................................... 216 Flight Direction, Ion ................................................................................. 401 Float Zone Si W afers .................................................................................. 870 Float Zone Silicon ....................................................................................... 314 Flow Rate ................................................................................................... 434,440 Fluorine ............................................................................................... 208 Fluorine, Atomic ......................................................................................... 145,193 Focus ................................................................................................... 135 Focus Latitude ............................................................................................. 148 Fourier Transform Mass Spectrometry .......................................................... 393,402,409 Fowler-Nordheim Tunneling ......................................................... 422 FPGA ...................................................................................................... 870 Free Energy of System .................................................................................. 820 Fundamental M odel .................................................................................... 401 FZ Si Wafers ......................................................................................... 870 FZ Silicon ................................................................................................... 678 GaAs .......................................................................................................... 568 Gain, Transistor .......................................................................................... 678 Gallium Arsenide ........................................................................................

904

592,619 Gap Filling .......................................................................................... 720 Gap-Fill ..................................................................................................... 493 Gate Bias .................................................................................................... 881 Gate Current ............................................................................................... 374 Gate Dielectric Integrity ............................................................................. 363 Gate Dielectrics .......................................................................................... 363 Gate Dielectrics, Ultrathin MOS ................................................................ Gate Dielectrics, Ultrathin Si02 ................................... ......... .......... ........... 445 494 Gate Insulator ......................................................................................... 152,432,881 Gate Oxide ................................................................................... 17,458 Gate Oxide Breakdown .................................... Gate Oxide Damage, Plasma Processing ................................................. 473 454,483 Gate Oxides ......................................................................................... 400 Gate Oxides, Electrical Properties of .......................................................... Gate, Aluminum and Polysilicon .............................................................. 470 566 Gate, MOS .................................................................................................. Gates, Electrical Characterization of SiO2 .......................... ..... ..... ..... .... ..... 448 Gates, Structural Characterization of SiO 2 .......................... .... ...... ... .. .... ..... 447 880 Ge ............................................................................................................... 308 Ge Amorphization ...................................................................................... 254 Ge-Preamorphization ................................................................................. 500 Generation Mechanism .............................................................................. Generation of Defects ............................................................................ 465 851,880 Germanium .......................................................................................... 607 Glass Polishing ........................................................................................... 110 Glass Transition Temperature ...................................................................... 606 Global Planarity ......................................................................................... 15,793,798 Grain Boundary ............................................................................... 313,346 Grain Boundary Diffusion ..................................................................... 571 Grain Size ................................................................................................... 134 Grain Structure of Polysilicon ...................................................................... 149 Grass .......................................................................................................... 132 Gratings ...................................................................................................... Grid for Device and Process Simulation ...................................................... 81 45 Grid Points .............................................................................................. 723 Growth Seams ............................................................................................. 851 Growth, Three Dimensional ........................................................................ 838 H2 Addition ............................................................................................... H 20 2 .... ....................................................... .... ..... ..... ..... ..... ...... .... ..... ..... ...400 H 2 SiF 6 ... ...................................................... ..... .... .. ..... ..... ...... ...... ..... ..... .... 226 Half-M icron BiCMOS Technology .............................................................. 5 137 Halo Effect ................................................................................................ 174 Halo LLD Device ........................................................................................ 194 Hardbake ................................................................................................... 48 HBT, Sil.xGe ........................................................................................... 715 HCI ............................................................................................................ 306 HCI-H 2 Etch ............................................................................................... 503 Heating Lamps, M ulti-Zone ........................................................................ 155 Henry's Law ............................................................................................... 48 Hetero-Bipolar Transistor ....................................................................... 905

HF ....................................................................................................... 712,755 HF/H 2 0 Vapor .......................................................................................... 226 High Frequency C-V Characteristics ........................................................... 423 High Pressure Thermal Annealing ............................................................... 470 High Resolution Transmission Electron Microscopy ................. 870 High-Frequency C-V Characteristics ............................................................ 11 High-Performance ...................................................................................... 667 Hillock Formation ...................................................................................... 741 Histogram of Dielectric Breakdown ...................................................... 425,413 HM DS ........................................................................................................ 114 Hole ........................................................................................................... 425 Hole Capture Cross-Section ......................................................................... 484 Hole M ean Free Path ........................................................................... 880,885 Hole Transport ............................................................................................ 494 Hole Trapping ..................................................................................... 428,569 Hole Traps .................................................................................................. 493 Hot Carrier Degradation ..................................................................... 179,431 Hot Carrier Effects ...................................................................................... 121 Hot Electron Degradation ..................................................................... 437,438 Hot Electron Lifetime .................................................................................. 433 HR-TEM ..................................................................................................... 870 Hydration of Silicon Dioxide ...................................................................... 696 Hydrocarbon Fragments ............................................................................... 209 Hydrodynamic Model .............................................................................. 46 Hydrofluoric Acid ....................................................................................... 712 Hydrogen Annealing ................................................................................... 469 Hydrogen Clean ......................................................................................... 568 Hydrogen Fluoride ...................................................................................... 755 Hydrogen, Atomic ....................................................................................... 470 Hydrogenation ............................................................................................ 491 I-Line .................................................................................................. 190,199 I-V Characteristics ..................................................................................... 423 I-V Characteristics of NM OS Devices ......................................................... 378 I-V Measurements ....................................................................................... 811 Idealty Factor ............................................................................................. 323 IGFET ......................................................................................................... 493 Imaging ..................................................................................................... 145 Impact ........................................................................................................ 440 Impact Ionization ................................................................................. 881,885 Imperfection, Crystalline ........................................................................... 795 Implantation .............................................................................................. 794 Implantation Damage ............................................................................. 34,39 Impurities in Silicon Dioxide ....................................................................... 694 Impurity Content ......................................................................................... 454 Im purity Redistribution ............................................................................ 52 In Situ Dry Cleaning .................................................................................... 755 In-Situ Baking ............................................................................................ 600 In-Situ Deposition ...................................................................................... 567 In-Situ Doped Polysilicon ............................................................................ 785 In-Situ Fabrication ...................................................................................... 503

906

In-Situ M ultiprocessing ............................................................................... 582 Incident-Angle-Dependent Etch Rate ........................................................... 602 Incubation Tim e .......................................................................................... 312 Index of Refraction ...................................................................................... 694 Indium Phosphide ....................................................................................... 678 Inertness .............................................................................................. 311,344 Infrared Spectroscopy .................................................................................. 692 Injection ...................................................................................................... 881 Injection of Point-Defects ........................................................................... 52 InP .............................................................................................................. 678 Instability .................................................................................................. 861 Integrated Circuits ............................................................................... 667,671 Integrated Optoelectronic Circuits ............................................................... 679 Integrated Processing ............................................................................... 566 Integration, Tool ....................................................................................... 78 Integrity of Lightly Nitrided Oxide ............................................................ 374 Integrity, Intrinsic .......................................................................................

567

Inter-Polysilicon Insulator ........................................................................... 421 Interconnections, M ultilevel ........................................................................ 739 Interconnects ........................................................................................ 153, 730 Interface Engineering ................................................................................... 570 Interface Flatness ........................................................................................ 400 Interface State Changes, M idgap ................................................................. 376 Interface State Density ................................................................. 484, 662, 770 Interface States ........................................................................................... 436 Interface Structure .................................................................................. 429 Interface Traps ..................................................................................... 355,465 Interface, User ......................................................................................... 80 Interfaces, Electronic Structure ..................................................................... 445 Interracial Oxide ...................................................................................... 568 Interracial Si02 ............................................... ..... ..... ..... ..... ...... ..... .... ..... ...870 Interlevel Dielectrics, Polishing of .............................................................. 606 Intermediate Frequency .............................................................................. 488 Interstitial Diffusion .............................................................................. 52 Interstitial Oxygen ................................................................................ 870 Interstitial Surface Recombination ........................................................... 36 Intrinsic Breakdown .............................................................................. 402 Intrinsic Dielectric Breakdown .................................................................. 413 Intrinsic Integrity ........................................................................................ 567 Intrinsic Layer ............................................................................................ 489 IOC ............................................................................................................ 679 Ion Beam Hydrogenation ........................................................................ 491 Ion Bombardment ........................................................................................ 837 Ion Current Density .............................................................................. 247,216 Ion Energy ................................................................................................... 836 Ion Energy Distribution ................................................................................ 216 Ion Flight Direction .................................................................................... 216 Ion Implantation ......................................................................................... 285 Ion-Beam -Induced Damage ................................................................... 483,491 Ionization Rate ........................................................................................... 881

907

Ionizing Radiation Effects, Processed-Induced ......................................... 464 Ions ......................................................................................................... 467 Isolated Features ........................................................................................ 132 Isolation Technique ................................................................................... 17 Isolation, Trench .................................................................................... 5,650 Isotherm al .................................................................................................. 825 Isotropic Etch .............................................................................................. 207 JFET ............................................................................................................ 682 Junction Depth ..................................................................................... 308,881 Junction Diode ............................................................................................. 266 Junction Field Effect Transistor .................................................................... 682 Junction Formation, Shallow ................................................................. 285,296 Junction Leakage ....................................................................................... 17 Junction Profiling by SIM S ........................................................................... 332 Junction, Shallow ................................................................... 276, 793,305,880 Junctions, Shallow Silicided ........................................................................ 254 Kinetic Parameters .............................................................................. 825,826 Kinetics ...................................................................................................... 312 Krypton Fluoride ........................................................................................ 148 Lamps, M ulti-Zone Heating ........................................................................ 503 Langmuir .................................................................................................... 236 Langmuir Probe ........................................................................................... 768 Langm uir-Blodgett Film s ............................................................................ 147 Laser Planarization ............................................................................. 627,635 Laser Processing, Excimer ............................................................................. 800 Lasers .................................................................................................. 148,681 Latch Up Hardness ..................................................................................... 122 Latchup Simulations ................................................................................. 45 Lateral Diffusion of Oxidant Species ........................................................ 17 Latitude ..................................................................................................... 193 Lattice Strain ...................................................................................... 880,885 LDD ........................................................................................................... 137 LDD Device, Halo ...................................................................................... 174 Leakage .................................................................................................... 31 Leakage Current ...................................................................... 254,421,632,813 Leakage Current in DRAM Cells .................................................................. 803 Leakage Current in Oxides ..................................................................... 409 Lens Distortion ............................................................................................ 132 Leveling Length .......................................................................................... 650 Lifetim e ........................................................................................ 32,152,881 Lifetime, M inority Carrier ......................................................................... 393 Liftoff ..................................................................................................... 61 Liftoff M etal Patterning .............................................................................. 177 Liftoff Process ............................................................................................. 135 Lightly Doped Drain Device, Halo ............................................................. 174 Lightly Nitrided Oxide, Integrity of ........................................................... 374 Lightly-Doped Drain .................................................................................. 137 Linear Rate Coefficient ............................................................................... 769 Linewidth .................................................................................................. 132 Linewidth Control ...................................................................................... 121 Linewidth M easurements ............................................................................ 164 908

Lithographic Performance of PTBSS Resist .................................................. 114 Lithography ....................................................................................... 101,145 110,131 Lithography, Deep UV ....................................................................... Lithography, E-Beam and X-Ray ............................................................

466

Lithography, X-Ray ..................................................................................

110

Loading Effect ......................................................................................... 620 Local Loading Effect .................................................................................... 596 Local Oxidation of Silicon ........................................................................ 17 Local Planarization .................................................................................... 607 Lock-In Detection ............................................... 208 LOCOS .......................................................................................... 17,139,775

LOPOS .......................................................................................................

775

Low Density Region ..................................................................................... 722 Low Energy Electron Beam s.......................................................................... 153 Low Frequency Dispersion ....................................................................... 489 Low Pressure Chemical Vapor Deposition .................................................... 310 Low Pressure CVD Tube ............................................................................... 571 Low Temperature ................................................................................... 83ft Low Temperature Etching ........................................................................... 244 Low Temperature Oxidation of Silicon ......................................................... 765 Low Temperature Oxide .............................................................................. 841 Low Temperature Thermal Annealing .......................................................... 491 Low-Field Breakdown Events .................................................................. 402 Low-Tem perature Cleaning ......................................................................... 755 Low-Voltage BiCM OS Device .................................................................... 5 LPCVD .................................................................................... 10,310,785,820 LPCVD of SiO2 ............................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .841 LPCVD Tube ............................................................................................... 571 LSI ............................................................................................................. 749 M agnetron-Enhanced RIE ............................................................................ 730 M ask Distortion ................................................................................... 121,122 M asks .................................................................................................. 152, 153 M ass Spectrometry ...................................................................................... 148 M aterials for Optical Interconnects .............................................................. 678 M aterials, Dielectric Properties .............................................................. 445 M aximum Electric Field .............................................................................. 881 M BE ........................................................................................................... 682 M ean Free Path .......................................................................................... 880 M ean Free Path of Hole ............................................................................... 885 Measurement of Temperature ................................................................ 541,574 M echanical Polishing, Planarization by ..................................................... 606 M echanical/Chem ical Polishing ............................................................... 650 M echanism of Particle Generation .............................................................. 229 M echanism s of Radiation Effects ............................................................ 464 M embrane Experim ents ............................................................................ 38 M embrane, Polysilicon ............................................................................ 27 M emories ................................................................................................. 26 Mercury Lamp ............................................................................................. 148 M ESFET ...................................................................................................... 682 739 M etal Deposition, Electroless ......................................................................

909

M etal Im purity Analysis ............................................................................. Metal Organic Chemical Vapor Deposition .................................................

456 682

M etal Patterning, Liftoff .............................................................................

177

M etal-Silicon Contact .................................................................................

321

627 M etallization ............................................................................................. M etallization Resistance ............................................................................ 745 M etallization, 0.8 lrm .................................................................................. 606 Metallurgical Reaction of Al with SiO2 .............................. . . . . . . . . . . . . . . . . . . . . . .. . .409 M etallurgical Stability .............................................................................. 343 Methodology, I-Line Process Development ................................................... 192 M etrology ........................................................................................... 132, 164 M icro-Pattern ............................................................................................. 183 M icro-Ram an Spectroscopy ......................................................................... 775 Stress .......................................................................................................... 775 M icro-Roughness of Si W afers ..................................................................... 400 M icrowave Plasma ............................................................................... 207,765 M idgap Interface State Changes .................................................................. 376 M ie Scattering ............................................................................................ 208 M inority Carrier Lifetime ........................................................................... 393 M iscibility Enhancement ............................................................................. 230

MNOS Devices ........................................................................................... Mo .............................................................................................................. M obility .................................................

657 730 885

M OCVD .................................................................................................... 682 Model .................................................................................................. 820,825 Modeling .................................................................................................... 582 Modeling of Cluster Tools ............................................................................ 551 M ODFET .................................................................................................... 681 M odulating Plasma Conditions .................................................................... 206 Modulation Transfer Function ...................................................................... 146 Moisture Absorption .................................................................................... 620 Moisture Content ......................................................................................... 598 M ole Ratio Dependence ............................................................................... 228 M olecular Beam Epitaxy ............................................................................. 682 Molybdenum ............................................................................................... 730 M onolayer Films ......................................................................................... 145 M onte Carlo M odel ................................................................................... 47 M onte Carlo Simulation .............................................................................. 139 M orphology, Surface ......................... ........... ................................. 570,851 M OS Capacitor ....................................................................... 151,266,391,409 M OS Capacitor Yield ............................................................................. 462 M OS Devices ................................................................................ 363,464,861 M OS Devices, AI-Si0 2 -Si ...................................................................... 402 MOS Devices, Radiation Effects in .............................................................. 464 M OS Diode ............................................................................................. 10 M OS Gate ................................................................................................... 566 M OS Gate Dielectrics, Ultrathin ................................................................. 363 M OS Structures ........................................................................................... 483 MOSFET .................................................................................................... 266 M ulti-Layer Resist ..................................................................................... 246

910

M ulti-Point Temperature Sensors ................................................................. M ulti-Zone Heating Lamps ........................................................................

503 503

M ultilevel Interconnections ......................................................................... 739 M ultiprocessing ........................................................................................... 582 820 M ultiwafer LPCVD ..................................................................................... N' Polysilicon .................................................................................... 216,236 N-Doped Silicon ....................................................................................... 9 N 2 . . . . . . ......................................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 N 2 -Gas Seal Processing ............................................................................... 322 N 2 0, RTP of Si in ........................................................................................ 363 Na Ions ....................................................................................................... 861 Native Oxide ...................................................................................... 321,836 Native-Oxide Removal .............................................................................. 755 Near Surface Imaging ........................................... 146 Necking ...................................................................................................... 200 Neural Network Training ............................................................................ 105 Neural Networks ........................................................................................ 101 Neutral Electron Traps .......................................................................... 493 Neutral Traps ............................................................................................. 465 NF3 . . . . . ........................................................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .730 NH 3 ..................................................... . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .10,207 N H 4 Cl ........................................................................................................ 713 N H 4 OH .................................................................................................. 400 Ni-Cu Pillars ............................................................................................ 739 Nickel ........................................................................................................ 149 Nitrous Oxide ............................................................................................. 658 Nitridation ......................................................................................... 374,569 Nitride ................................................................................................... 28 Nitride Dielectric, Reoxidized .................................................................... 801 Nitride Formation, Surface ......................................................................... 207 Nitride Oxidation ...................................................................................... 421 Nitride Sidewall Protection ........................................................................ 208 Nitride, Oxidized ..................................................................................... 27 Nitride/Oxide/Nitride Trilayer ............................................................. 17 Nitrided Oxide ........................................................................................... 374 Nitrogen ..................................................................................................... 236 Nitrogen-Doped Silicon ............................................................................ 9 Nitrogen-Gas Seal Processing ..................................................................... 322 NM OS ................................................................................................. 137,655 NM OS Devices, I-V Characteristics ............................................................ 378 NM OS Transistors ....................................................................................... 120 NM OS-CM OS Spacings ........................................................................... 45 No Etchback SOG .............................................. 642 Non-Etchback ............................................................................................. 598 Non-Etchback SOG .................................................................................... 592 Non-Ionic Surfactant................................................................................... 752 Non-Isothermal .......................................................................................... 826 Notching .................................................................................................... 200 Novolak ..................................................................................................... 146 Nuclear Analysis ..................................................................................... 18

911

Nucleation .................................................................................................. Nucleation Layer ........................................................................................

571 620

O/N Dielectric ........................................................................................ 29 18,209 02 .......................................................................................................... 391 0 2 -Diluted Oxidation Technique ................................................................. 695 0 2 /TEOS Flow Ratio ................................................................................... 276 Ohmic Contact ............................................................................................ 801,811 ON Dielectric ...................................................................................... 421 ON Stacked Film ........................................................................................ 375 ONO .......................................................................................................... 421 ONO Stacked Film ..................................................................................... 631 Optical Ablation ........................................................................................ 730 Optical Emission ......................................................................................... 678 Optical Interconnects ................................................................................... 445 Optical Properties of Condensed M atter ....................................................... Optically Assisted Electron Injection ..................................................... 494 310 Optimization .............................................................................................. 191 Optimization of I-Line Photolithography ................................................... 717 Organic M edia ............................................................................................ 244 Organic Photoresist ................................................................................... 749 Organic Solvent .......................................................................................... 147 Organosilane .............................................................................................. 121 Overlay Control .......................................................................................... 120 Overlay of Lithography Levels ................................................................... Oxidant Species, Lateral Diffusion of ...................................................... 17 28, 765 Oxidation .............................................................................................. 34 Oxidation Enhanced Diffusion .................................................................. 421 Oxidation of Nitride .............................................................................. 423 Oxidation, Dry ...................................................................................... 391 Oxidation, 0 2 -Diluted Technique ................................................................ 421 Oxidation, Pyrogenic Steam ................................................................... 151 Oxide ......................................................................................................... 353, 360,409,473 Oxide Breakdown ................................................................... 435,465 Oxide Charge ..................................................................................... 473 Oxide Charging .................................................................................... Oxide Dielectric Constant ...................................................................... 489 871 Oxide Layer Disintegration ......................................................................... 409 Oxide Leakage Current ................................................................................ 607 Oxide Reflow .............................................................................................. 353,360 Oxide Reliability ................................................................................ 400 Oxide Surface Micro-Roughness ................................................................... 434,495 Oxide Thickness .................................................................................. 574 Oxide Thickness Measurement ..................................................................... 486 Oxide Traps ................................................................................................ 353,355,360 Oxide W earout ............................................................................. 473 Oxide Yield ........................................................................................... 568 Oxide, Interfacial ...................................................................................... 374 Oxide, Lightly Nitrided ............................................................................. 841 Oxide, Low Temperature ............................................................................. 321 Oxide, Native ............................................................................................

912

Oxidized Nitride ..................................................................................... Oxygen Diffusion ........................................................................................ Oxygen Dose .............................................................................................. Oxygen, Interstitial .................................................................................... Oxynitride .................................................................................................. Ozone ......................................................................................................... P + Gate.....................................................................................................

27 871 568 870 657 617 9

P-I Junction ................................................................................................. A89 Packaging ............................................................................................ 153,667 Packaging for Optical Interconnects ............................................................. 678 PADRE ................................................................................................... 46 PAG Resist Formulations ............................................................................. 110 Parabolic Rate Constant .............................................................................. 769 Parallel Plate Plasma Reactor .................................................................... 209 Parallel Processing ...................................................................................... 678 Parameters .......................................................................................... 825,826 Parasitic Resistance Reduction .................................................................... 122 Partial Differential Equation Formulation ............................................... 43 Partial Etchback ......................................................................................... 598 Particle Deposition ..................................................................................... 749 Particle Deposition, Prevention of ............................................................... 753 Passivation ................................................................................... 617,624,861 Pattern Formation, Conductor ...................................................................... 739 Patterning, Liftoff Metal ............................................................................. 177 Pd/Sn Catalyst ........................................................................................... 149 PDE Formulation ...................................................................................... 43 PE-CVD TEOS/Oxygen ............................................................................... 593 PEB ............................................................................................................ 110 PECVD ................................................................................................ 617,692 PECVD Si02 ................................................. .. ..... ..... ..... ...... .... ...... .... ..... .... 720 Penetration Depth ...................................................................................... 467 Performance of I-Line Photoresist ................................................................ 199 Permalloy ................................................................................................... 149 Phase ......................................................................................................... 312 Phase Shift Masks ...................................................................................... 152 Phosphorus-Doped Polysilicon ................................................................... 803 Photochemistry .......................................................................................... 153 Photocleavage ............................................................................................ 148 Photoionization Cross Section ...................................................................... 665 Photolytically Generated Acid ................................................................... 110 Photons ................................................................................................... 467 Photooxidation ........................................................................................... 147 Photoresist ............................................................................. 134,190,199,244 Photospeed ................................................................................................. 152 Piezoceramic Scanner .................................................................................. 164 Pillars, Ni-Cu ............................................................................................. 739 Pinholes ..................................................................................................... 151 PISCES ....................................................................................................... 139 Pitch Measurements .................................................................................... 164 Pits ............................................................................................................. 345

913

Placem ent Error ........................................................................................... 183 642 Planarity .................................................................................................... 606 Planarity, Global ....................................................................................... 592,617,635 Planarization ............................................................................... 606 Planarization by M echanical Polishing ....................................................... 17 Planarization of Borosilicate Glass .......................................................... 642 Planarization Process .................................................................................. 607 Planarization Range ........................................ 650,652 Planarization Rate .............................................................................. 146 Planarizing Layer ....................................................................................... 246, 765,834 Plasm a ......................................................................................... 206 Plasma Conditions, M odulating .................................................................. 473 Plasma Damage .......................................................................................... 466 Plasma Etching ........................................................................................... Plasma Etching Si/SiO 2 ..................................... . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . ... . . . . . 208 473 Plasm a Etching, Charge Build-Up During .................................................... 206 Plasm a Etching/Deposition ......................................................................... 473 Plasma Processing Gate Oxide Dam age ........................................................ 473 Plasma Processing, Charge Build-Up During ................................................ 206 Plasm a Processing, Time M odulated ............................................................. Plasm a Reactor, RF ............................................................................... 208 246 Plasm a Stream Characterization ................................................................ 473 Plasm a Stripping, Charge Build-Up During ........................................... 692 Plasma-Enhanced CVD ............................................................................... Plasma-Enhanced CVD Si02 ............. ............... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 176 PM GI .......................................................................................................... 137 PMOS ......................................................................................................... 567 PM OS Capacitors ........................................................................................ 120 PM OS Transistors ........................................................................................ 9,880 PM OSFETs .............................................................................................. 5 PNP Bipolar ............................................................................................. 49 pnpn Layouts ............................................................................................ POC13 . . . . ...................................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 140 53 Point Defect Type ..................................................................................... 34,84 Point Defects ........................................................................................... Point-Defect Diffusion M odel .................................................................... 52 52 Point-Defects, Injectiqn of ....................................................................... 357 Polarity Independence of Wearout ............................................................... 607 Polishing of Glass ....................................................................................... 606 Polishing of Interlevel Dielectrics ............................................................... 652 Polishing Pad, Polyurethane ....................................................................... 606,650 Polishing, Chem ical-M echanical ........................................................ 606 Polishing, Planarization by M echanical ...................................................... 566 Poly-Em itter, Bipolar ............................................................................... 793 Polycrystalline Silicon ................................................................................ 296 Polycrystalline Silicon-Germ anium Alloys .................................................. 296 Polycrystalline SixGet.x Alloys ................................................................... 667,669 Polyim ide ............................................................................................ 741 Polyim ide Dielectric Layer ......................................................................... 680 Polym er Waveguides ..................................................................................

914

Polyphenylquinoxaline Polymer ..................................................................

712

528,567,570, 785,820 Polysilicon ....................................................................... 801,810 Polysilicon Deposition .........................................................................

Polysilicon Deposition Experiments .............................................................

824

Polysilicon Film .......................................................................................

17

Polysilicon Gate .......................................................................................... Polysilicon Gate Antennas ...........................................................................

470 473

820,821 Polysilicon LPCVD M odel .................................................................... Polysilicon Membrane .............................................................................. 27 803 Polysilicon Reflectance ............................................................................... Polysilicon Surface Roughness ..................................................................... 803 803 Polysilicon Texture ...................................................................................... 810 Polysilicon Texturization ...................................................................... 800 Polysilicon Texturization Technique ........................................................... 236 Polysilicon, n÷............................................................................................. 803 Polysilicon, Phosphorus-Doped ................................................................... 810 Polysilicon, Rugged ..................................................................................... 803 Polysilicon, Undoped .................................................................................. 712 Polysiloxane ............................................................................................... 750 Polystyrene Particle.................................................................................... 652 Polyurethane Polishing Pad ....................................................................... 424,813 Poole-Frenkel Conduction .................................................................... 722 Porous Region .............................................................................................. 712 Porous Silicon Formation ............................................................................. Positive Charge Annihilation ................................................................ 499 110 Positive Resist M aterials ............................................................................ 110 Post-Exposure Baking .................................................................................. 749 Potential, Zeta ........................................................................................... 249 Power Density ............................................................................................. 712 PPQ ........................................................................................................... 713 PPQ/Cr/Si .................................................................................................. 266, 285, 296,330 Preamorphization ................................................................... 254 Preamorphization, Ge and Sb ...................................................................... 139 PREDICT .................................................................................................... 315 Pressure ...................................................................................................... 753 Prevention of Particle Deposition ................................................................ 409 Probability for Breakdown .......................................................................... 176 Probamide 285 ............................................................................................. 164 Probe M icroscope ......................................................................................... 541,574 Process Control ..................................................................................... 432 Process Integration ...................................................................................... 551 Process Integration, Semiconductor .............................................................. 52 Process Modeling ....................................................................................... 5 Process M odularity ......................................................................................... Process Optimization of I-Line Photolithography ........................................ 191 52,78 Process Simulation .................................................................................. 81 Process Simulation Grid ............................................................................. Process Simulator, Three-Dimensional .................................................... 54 627 Process Window .......................................................................................... 464 Process-Induced Ionizing Radiation Effects .............................................. 800 Processing, Excimer Laser .............................................................................

915

Processing, Integrated ................................................................................. Processing, Single W afer ............................................................................. Processing, ULSI W afer ...............................................................................

566 503 464

Processing, Wafer ........................................................................................ 446 Profile ........................................................................................................ 201 Profile, Base and Emitter ............................................................................ 795 Profile, SIM S .............................................................................................. 871 Profiles, Dopant ......................................................................................... 336 Projection Printing ....................................................................................... 148 Projection Stepper ....................................................................................... 149 Proxim ity Effects ................................................................................. 101,132 PSG Films ............................................................................................... 53 PTBSS Resist............................ ..... . . . ............... ... ..................... 110 Pyramid Shaped Pits .................................................................................. 345 Pyrogenic Steam Oxidation .................................................................... 421 Pyrolysis of Diethylsilane .......................................................................... 841 Pyrolytic Decomposition ............................................................................. 841 Pyrometer ................................................................................................... 529 Q d ...................................................................................................... 375,396 Quantum-W ell Lasers ................................................................................. 681 Quasi-Recessed Field Oxide .................................................................... 17 Quasi-Stoichiometric Silicon Nitride ...................................................... 18 Radiation Dam age ................................................................................... 94 Radiation Effects in M OS Devices ........................................................ 464,467 Radiation Effects, Experimental Simulation ................................................ 471 Radiation Effects, Process-induced ............................................................... 464 Radiation, Ionizing ..................................................................................... 464 Radiation-Induced Damage,.......... .... . . ........ .......................... 120 Raman Spectroscopy .................................................................................... 775 Ram p Voltage Breakdown ........................................................................... 358 Ramped-Field Method for Dielectric Breakdown .................. 409 Rapid Therm al Annealing ....................................................... 266, 285, 307,330 Rapid Thermal Chemical Vapor Deposition.......................... .... 566,582 Rapid Thermal CVD ............................................................................ 582,851 Rapid Thermal Nitridation .................................................................... 17 Rapid Thermal Oxidation ............................................................. 391,503,582 Rapid Thermal Oxidation/Nitridation ....................................................... 363 Rapid Thermal Processing ...... ............... .......... 363,503,528,541,574 Rate of Planarization ........................................ :.................................. 650,652 RBS ............................................................................................................ 155 RBS Analysis .............................................................................................. 713 RC Delay .................................................................................................... 139 RCA Clean................ .................................... 454 Reactive Ion Etching ............................................................... 149, 308,466,730 Reactor, Single W afer ............................................................................... 693 Recombination, Electron-Hole ..................................................................... 499 Recom bination, Surface ........................................................................... 36 Recombination-Enhanced Annealing ............................................................ 471 Reflectance, Polysilicon .............................................................................. 803 Reflectance, Thin Film ......................................................................... 801,811

916

607 Reflow Techniques ..................................................................................... 382,493,813 Reliability .................................................................................. 353 Reliability of Thin Oxides .......................................................................... Reliability, Dielectric ......................................................................... 426,803 360 Reliability, Oxide ..................................................................................... Removal of Damage ................................................................................... 285 249 Removal Rate vs. Power Density ................................................................ 569 Reoxidation ............................................................................................... Reoxidized Nitride Dielectric............................... 801,811 375 Reoxidized Nitrided Oxide ......................................................................... Representations of Data .......................................................................... 78 207 Residence Time ........................................................................................... Resist ........................................................................................................ 246 Resist Chem istry ........................................................................................ 113 592,607 Resist Etchback .................................................................................... Resist M aterials, Chem ically Am plified .................................................... 110 183 Resist Process .............................................................................................. Resistance of M etallization ........................................................................ 741 254, 328 Resistance, Contact .............................................................................. 568 Resistance, Em itter .................................................................................... Resistivity, N-Doped Si .......................................................................... 12 Resolution .......................................... 132, 145, 191,200 541 Resolution of Temperature ........................................................................... 657 Retention .................................................................................................... 122 Retrograde Doping Profile ........................................................................... 470 RF Plasma Annealing ....................................... RF Plasma Reactor .................................................................................... 208 308,466,730 RIE .............................................................................................. 120 Ring Oscillator, CM OS ............................................................................... 800 Roughening Technique, for Polysilicon ......................................................... 803 Roughness of Polysilicon Surface ............................................................. 813 Roughness, Surface ..................................................................................... 266,285,307,330,541 RTA ....................................... RTCVD ...................................................................................................... 566 391,503 RTO ..................................................................................................... 363 RTO/RTN .................................................................................................. 363, 503, 528, 532, 574 RTP ................................................................................. 363 RTP-CVD .................................................................................................. Rugged Polysilicon ...................................................................................... 810 155,713 Rutherford Back Scattering .................................................................. Sacrificial Oxide ..................................................................................... 18 SACVD ...................................................................................................... 617 155 SAHR ....................................................................................................... 124 Salicidation .............................................................................................. 713 Saturated Calom el Electrode ....................................................................... Saturation ................................................................................................. 798 Sb-Preamorphization.................................................................................. 254 44 Scaled CM OS Technology ........................................................................ 43 Scaling of Devices ..................................................................................... Scanning Probe M etrology ............................................................................ 164 713 SCE ............................................................................................................

917

Schottky Barrier Height ............................................................................. 324 Schottky Contact ........................................................................................ 321 Sealed Interface Local Oxidation ............................................................. 17 Secondary Ion Mass Spectrometry ........................................................... 14,794 SEG ............................................................................................................ 305 Segregation Coefficient ............................................................................ 13 Selective Deposition ................................................................................. 851 Selective Epi Growth .................................................................................. 305 Selectivity ................................................................................................. 236 Selectivity and Etch Rate of SOG:BPSG ...................................................... 648 Self-Aligned .................................................................................................. 5 SEM Profiles ............................................................................................... 251 Semiconductor Fabs, Economic Modeling ....................................................... 551 Semiconductor Process Integration ................................................................ 551 Sensors, M ulti-Point Temperature ............................................................... 503 SF6 ............................................................................................................. 207 Shallow Boron-Doped Layer ....................................................................... 266 Shallow Junction .............................................................. 276,305,330,793,880 Shallow Junction Formation .................................................................. 285,296 Shallow Junctions, Silicided ........................................................................ 254 Sheet Resistance ........................................................................... 313,333,346 Shift, Threshold Voltage ........................................................................... 380 Short Channel Effects .......................................................................... 120,266 Si ........................................................................................................ 343,834 Si Emissivity .............................................................................................. 529 Si Membrane, Stress Compensated ............................................................... 121 Si Surface M icro-Roughness ........................................................................ 400 Si Template ................................................................................................ 176 Si Wafer Surface Roughness ........................................................................ 400 Si/Si0 2 Interface ....................................................................................... 400 SijxGex HBT ........................................................................................... 48 Si 2 H 6 ... .. .................................................... . .... ..... .. .... ....... .... ..... ...... ..... . . . . 10 Si 3 N 4............................................. .. .... .. ..... .... ....... ..... ...... .... ... 53,307,528,536 SiC14 .............................................. ..... ..... ...... .... ..... ..... .... ..... ..... . 209,306,730 Sidewall .................................................................................................... 239 Sidewall Protection .................................................................................... 208 Signal Processors ......................................................................................... 678 SiH4 ... .. ................................................... ...... ..... ..... ..... .... . .... ..... ..... .. . ... .835 Silane .................................................................................................. 835,841 Silane Chemistry ........................................................................................ 570 Silica Slurry ............................................................................................... 652 Silicate ..................................................................................................... 598 Silicidation .............................................................................................. 5,53 Silicide Formation, Enhanced ...................................................................... 305 Silicide, Ti and Co ...................................................................................... 254 Silicided Shallow Junctions ......................................................................... 254 Silicon ................................................................................................. 454,834 Silicon Dangling Bonds ................................................................................ 664 Silicon Dioxide .................................................................................... 692, 765 Silicon Dioxide Etching ............................................................................... 226

918

Silicon Dioxide Hydration ..........................................................................

696

Silicon Dioxide, Dielectric Breakdown ........................................................

409

Silicon Dioxide, Impurities ......................................................................... Silicon Epitaxy ...........................................................................................

694 755

Silicon Nitride ...........................................................................................

657

Silicon Oxidation ........................................................................................ 765 Silicon Tetrachloride .................................................................................. 730 Silicon, Amorphous ..................................................................................... 813 Silicon, N itrogen-Doped ............................................................................ 9 Silicon-Germanium Alloys .......................................................................... 296 Silicon-Rich Oxide ..................................................................................... 490 SILO ........................................................................................................ 17 SILO /RTN ................................................................................................ 17 Siloxane .................................................................................................... 598 Silylated Acid Hardened Resist .................................................................. 155 Silylation ............................................................................................ 146,155 SIM PL-IPX ............................................................................................... 79 SIM S ..................................................................................... 14, 440, 794,881 SIM S Depth Profile .................................................................................... 871 SIM S Junction Profiling ................................................................................ 332 Sim ulation of Factory Performance .............................................................. 551 Simulation of ULSI Device Effects ............................................................ 43 Sim ulation, Device and Process ................................................................ 78 Single Wafer Reactor .................................................................................. 693 Single W afer Thermal Processing ................................................................ 503 Si02 ............................................. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . 53,528,692,765 Si0 2 Breakdown M easurements .................................................................... 448 SiO 2 Etching ........................................................................................ 209,226 Si0 2 Films, Thin ......................................................................................... 391 SiO 2 Gate Dielectrics .................................................................................. 445 Si0 2 Gates, Electrical Characterization ...................................................... 448 Si0 2 Gates, Structural Characterization ...................................................... 447 Si0 2 , Dielectric Breakdown ........................................................................ 409 Si0 2 , Interfacial ........................................................................................ 870 Si02, LPCVD of .......................................................................................... 841 Si0 2 , PECVD ............................................................................................. 720 Si0 2 , Thermally-Grown .............................................................................. 409 Si0 2 , Trap Density in ............................................................................. 409 Si.Ge 1 _, Alloys .................................................................................... 296,851 Slurry, Silica .............................................................................................. 652 Small Signal Adm ittance Characteristics .............................................. 483 SM IF Box ................................................................................................. 91 Sodium Ions ................................................................................................. 861 Soft X-Rays ................................................................................................ 153 SOG ........................................................................................ 592, 598, 642, 712 SOG Cure Time ............................................................................................ 648 SOG, Etch-Back of ................................................................................... 17 SOG:BPSG Selectivity and Etch Rate .......................................................... 648 Solvent, Organic ......................................................................................... 749

91.9

Source/Drain Junctions, Shallow ..................................................................

305

Spin-On-Glass .......................................................... 592,598,607,617,642,712 Spin-On-Glass, Etch-Back of .................................................................. 17 592 Spin-ON-Polymer ....................................................................................... 730 Sputter ....................................................................................................... Sputter Deposition ................................................................................ 468 721 Sputter Etching ........................................................................................... 628 Sputtering ................................................................................................... 17 SRAM , 16K .............................................................................................. 881 SRP Analysis .............................................................................................. 343 Stability .................................................................................................... 26,421,422 Stacked Capacitor .......................................................................... 146 Standing Waves .......................................................................................... 487 Static Capacitance ...................................................................................... 33 STC ......................................................................................................... 421 Steam Oxidation, Pyrogenic ........................................................................ 152 Step Coverage ............................................................................................. Stepped-Field M ethod for Dielectric Breakdown ......................................... 409 402 STM Profiles ............................................................................................... 345 Stoichiometric ............................................................................................ 312 Stoichiometric Film .................................................................................... 885 Strain ......................................................................................................... 798 Strain Field ................................................................................................ 885 Stress ......................................................................................................... 354 Stress Induced Changes ................................................................................ 409 Stressing Field ............................................................................................ 409 Stressing Time ............................................................................................. 359 Stressing, Constant-Voltage ........................................................................ 447 Structural Characterization of SiO 2 Gates ................................................... I Sub-Half Micron ... ................................................................................... 178,305,305 Sub-M icron CMOS ......................................................................... 199 Submicron CMOS Process ............................................................................. 155 Submicron Deep UV Lithography ................................................................ 190,199 Submicron Photolithography ............................................................... 642 Submicron Triple M etal Technology .................................... Submicron, Deep ........................................................................................ 5 203 Substrate .................................................................................................... 379,881 Substrate Current ................................................................................. 620 Substrate Dependency ................................................................................. 357 Substrate Doping Effects .............................................................................. 606 Substrate Flatness ....................................................................................... 740 Substrate Preparation ................................................................................. SUPERSILO Isolation .............................................................................. 18 17 SuperSILO/RTN ....................................................................................... Suppression of Boron Penetration ................................................................ 9 834 Surface ....................................................................................................... 454,460 Surface Contamination ......................................................................... 146 Surface Imaging .......................................................................................... 114 Surface Inhibition Effects ............................................................................ 400 Surface M icro-Roughness ............................................................................

920

570, 851 Surface M orphology ............................................................................. 207 Surface Nitride Formation .......................................................................... Surface Potential Discrepancy ................................................................ 488 Surface Recombination, Interstitial ......................................................... 36 803 Surface Roughness of Polysilicon .................................................................. 400 Surface Roughness of Si Wafers ................................................................... 813 Surface Texture and Roughness ..................................................................... 445 Surfaces, Electrical Properties ..................................................................... 445 Surfaces, Electronic Structure ....................................................................... 33 SVC ......................................................................................................... 121 Synchrotron Radiation ................................................................................ Synchrotron Storage Ring ........................................................................ 88 870 System Free Energy ..................................................................................... 440 TCA ............................................................................................................ 421 TCA Oxidation ........................................................................................... 183 TCNQ .................................................. 32, 383, 396,414,421,431,811 TDDB .................................................................. 52,308 TEM ....................................................................................................... 870 TEM , High Resolution ................................................................................. 541,574 Temperature Control ............................................................................ 528, 541,574 Temperature M easurement ............................................................. 541 Tem perature Resolution ............................................................................... 503 Temperature Sensors, M ulti-Point ............................................................... 174 Tem plate, Trilayer .................................................................................... 528, 537,617,692,720,841 TEOS ........................................................................ 593 TEOS/Ozone .............................................................................................. 120 Test Circuit, 0.4 mim CM OS ......................................................................... 692 Tetraethoxy Silane ..................................................................................... 841 Tetraethylorthosilicate .............................................................................. 803 Texture, Polysilicon ..................................................................................... 813 Texture, Surface ......................................................................................... Texturization Technique, for Polysilicon ...................................................... 800 810 Texturization, Polysilicon ........................................................................... 110 469 A ermal Annealing ................................................................................. Therm al Annealing, High Pressure .......................................................... 470 491 Thermal Annealing, Low Temperature ........................................................ 152 Thermal Bias Stress .................................................................................. 122,428,566 Thermal Budget ............................................................................ 596 Thermal Flowing Polymer ........................................................................... 582 Thermal M odeling ...................................................................................... 503 Thermal Processing, Single W afer ............................................................... 592 Therm al Reflow .......................................................................................... Thermally-Grown SiO2 .................................... .. ..... .... ...... ..... .... ...... ... . . . 409 801, 811 Thin Film Reflectance .......................................................................... 445 Thin Film s, Electrical Properties ................................................................. Thin Films, Electronic Structure .............................................................. 445 483 Thin Gate Oxides ........................................................................................ Thin Gate Oxides, Electrical Properties of ................................................... 400 353 Thin Oxide Reliability ...............................................................................

921

Thin Oxide Yield ........................................................................................ Thin Oxides ................................................................................................

473 353

Thin SiO 2 Films .......................................................................................... 391 Three Dimensional Growth ......................................................................... 851 Three-Dimensional Process Simulator ....................................................... 54 Threshold Voltage Shift ...................................................................... 380,861 Ti-Silicide .................................................................................................. 254 TiB 2 . .. .................................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310,343 TiC14 . . . . ....................................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Time Dependent Breakdown ........................................................................ 396 Time Dependent Dielectric Breakdown ..................................... 32, 383, 414,421 431,433,434,811 Time Modulated Plasma Processing .............................................................. 206 Time Zero Breakdown ................................................................................. 394 TiN Barrier Layer ....................................................................................... 628 TiSi 2 . . . . ........................................................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 TiSi 2 Formation ........................................................................................... 305 Titanium Silicide ........................................................................................ 276 Titanium Silicide Formation ....................................................................... 305 TiW ............................................................................................................ 730 TM SDEA .................................................................................................... 155 Tool Integration ...................................................................................... 78 Top Surface Imaging .................................................................................... 145 Top-Oxide ............................................................................................. 421 Topography ................................................................................................ 203 Total Dose .................................................................................................. 499 Total Pressure ............................................................................................. 315 Transfer Characteristics .............................................................................. 449 Transfer Function ......................................................................................... 146 Transient Enhanced Diffusion .................................................................. 34,39 Transistor ............................................................................................ 152,432 Transistor Gain ........................................................................................... 568 Transmission Electron M icroscopy ........................................................... 52,308 Trap Density in SiO2 ...................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 Trapped Electron Density ........................................................................... 660 Trapping, Charge ................................................................................. 377,803 Trapping, Electron ....................................................................................... 398 Trapping, Hole .................................................................................... 428,569 Traps .......................................................................................................... 486 Traps, Interface ........................................................................................... 355 Traps, Interface and Neutral ................................................................. 465 Trench Isolation ...................................................................................... 5,650 Tri-Layer Liftoff ......................................................................................... 135 Tri-Layer Resist ....................................................................................... 61 Trilayer Nitride/Oxide/Nitride ............................................................. 17 Trilayer Template ...................................................................................... 174 Triple Metal Technology, Submicron ............................................................ 642 Tungsten ..................................................................................................... 730 Tunneling .................................................................................................... 496 Tunneling, Fowler-Nordheim ...................................................................... 393

922

44 Twin-Tub CM OS Technology ..................................................................... 394 TZBD Breakdown ....................................................................................... 650,667,671 ULSI ............................................................................................. ULSI Device Effects, Simulation of .......................................................... 43

ULSI M OS Gate Dielectrics .........................................................................

363

ULSI Wafer Processing ............................................................................... 464 Ultra High Vacuum .............................................................................. 582 296 Ultra-Shallow Junction Formation ............................................................... Ultra-Thin Film ......................................................................................... 147 236,834 Ultraclean ........................................................................................... Ultrathin M OS Gate Dielectrics ................................................................. 363 445 Ultrathin SiO 2 Gate Dielectrics .................................................................. Undoped Polysilicon ................................................................................... 803 80 User Interface ........................................................................................... UTF ............................................................................................................ 147 150 UTF Metallization Process .......................................................................... UV ............................................................................................................. 147 131 UV Excimer Laser Stepper ........................................................................... 861 UV Light .................................................................................................. 110,145 UV Lithography ................................................................................. 26 V-Cell ..................................................................................................... V-Shaped Structure ................................................................................ 30 52 Vacancy Diffusion .................................................................................... Vapor HF/H 20 ........................................................................................... 226 785 Vertical Furnace ......................................................................................... 841 Very Low Temperature Oxide ..................................................................... 600 Via Chain .................................................................................................. Via Hole Filling ......................................................................................... 739 745 Via Resistivity ........................................................................................... 841 VLTO ........................................................................................................ 593 Void Formation ........................................................................................... 607 Void Free Dielectric Films ......................................................................... 722 Voids ......................................................................................................... 569 Voltage, Flatband ...................................................................................... 715 Voltammetric M easurements ...................................................................... 380 VtShift ...................................................................................................... 730 W ............................................................................................................... 121 Wafer Alignment Accuracy .......................................................................... Wafer Pairs, Bonded ................................................................................. 870 446 Wafer Processing, Experimental .................................................................. Wafer Processing, ULSI .......................................................................... 464 400 Wafer Surface Roughness ........................................................................... 694 Water Pickup ............................................................................................. Waveguide Structures ................................................................................. 681 353 Wearout of Oxides ...................................................................................... 355,360 Wearout, Oxide ................................................................................... .357 Wearout, Polarity Independence ............................................................... 414 Weibull Distribution ............................................................................... 426 W eibull Plot ........................................................................................... W et Process ................................................................................................. 749

923

X-Ray X-Ray X-Ray X-Ray

Irradiation .................................................................................. A93 Lithography ................................................................. 88,110, 120,466 Photoelectron Spectroscopy ............................................................... 237 Resist ............................................................................................. 94

X-Ray Source .......................................................................................... X-Rays ....................................................................................................... XPS ............................................................................................................ XPS Analysis ........................................................................................... Yield of M OS Capacitor .............................................................................. Yield, Thin Oxide ...................................................................................... Zero-Defect Substrates ................................................................................ Zeta Potential ............................................................................................ Zeta Potential Control ................................................................................

924

89 153 237 18 462 473 681 749 754

ULSI Science and Technology 1991

Ulsi Technology

ULSI Semiconductor Technology Atlas

ULSI Devices

ULSI Applications

Compost Science and Technology

Aerosols: Science and Technology

Science and Technology Ethics

Cotton Science and technology

Dairy Science and Technology

Wool: Science and Technology

Photocatalysis: science and technology

Science and technology almanac

Nanocomposite Science and Technology

Corrosion Science and Technology

Food Science and Technology

Nanowires Science and Technology

Dairy Science and Technology

Transport Science and Technology

Zeolites, science and technology

Polymer Science and Technology

Science and Technology

Chocolate Science and Technology

Nanofluids: Science and Technology

Hydrocracking science and technology

Corrosion Science and Technology

Friction Science and Technology

Polymer Science and Technology

Aerosols: Science and Technology

Cotton: Science and Technology

ULSI Science and Technology 1991

Ulsi Technology

ULSI Semiconductor Technology Atlas

ULSI Devices

ULSI Applications

Compost Science and Technology

Aerosols: Science and Technology

Science and Technology Ethics

Cotton Science and technology

Dairy Science and Technology

Wool: Science and Technology

Photocatalysis: science and technology

Science and technology almanac

Nanocomposite Science and Technology

Corrosion Science and Technology

Food Science and Technology

Nanowires Science and Technology

Dairy Science and Technology

Transport Science and Technology

Zeolites, science and technology

Polymer Science and Technology

Science and Technology

Chocolate Science and Technology

Nanofluids: Science and Technology

Hydrocracking science and technology

Corrosion Science and Technology

Friction Science and Technology

Polymer Science and Technology

Aerosols: Science and Technology

Cotton: Science and Technology

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