Turbo-like Codes: Design for High Speed Decoding

Turbo-like Codes

Aliazam Abbasfar

Turbo-like Codes Design for High Speed Decoding

123

A C.I.P. Catalogue record for this book is available from the Library of Congress.

ISBN-10 978–1–4020–6390–3 ISBN-13 978–1–4020–6390–9 Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands. www.springeronline.com

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All Rights Reserved c 2007
No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work.

Dedicated to my wife

Contents

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2

Turbo Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Turbo Codes and Turbo-like Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.1 Turbo Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.2 Repeat–Accumulate Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.3 Product Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Iterative Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Probability Propagation Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Message-passing Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 Graphs with Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.6 Codes on Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6.1 Parity-check Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6.2 Convolutional Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.3 Turbo Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3

High-speed Turbo Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 BCJR Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 Turbo Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Pipelined Turbo Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5 Parallel Turbo Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

vii

viii

Contents

3.6 Speed Gain and Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.6.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.6.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.7 Interleaver Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.7.1 Low Latency Interleaver Structure . . . . . . . . . . . . . . . . . . . . . . . . 31 3.7.2 Interleaver Design Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.7.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.8 Hardware Complexity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4

Very Simple Turbo-like Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.1.1 Bounds on the ML Decoding Performance of Block Codes . . . . 40 4.1.2 Density Evolution Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2 RA Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.2.1 ML Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2.2 DE Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3 RA Codes with Puncturing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3.1 ML Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3.2 Performance of Punctured RA Codes with ML Decoding . . . . . . 53 4.3.3 DE Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.4 ARA Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.4.1 ML Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.4.2 Performance of ARA Codes with ML Decoding . . . . . . . . . . . . . 58 4.4.3 DE Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.5 Other Precoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.5.1 Accumulator wih Puncturing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.6 Hardware Complexity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5

High Speed Turbo-like Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.2 Parallel ARA Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3 Speed Gain and Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.4 Interleaver Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.5 Projected Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.5.1 Parallel Turbo Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.5.2 Other Known Turbo-like Codes . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.5.3 Parallel LDPC Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.5.4 More Accumulate–Repeat–Accumulate Codes . . . . . . . . . . . . . . 74 5.6 General Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

List of Figures

1 2

The block diagram of a PCCC encoder The block diagram of a SCCC encoder

6 6

3 4 5

An example of a HCCC encoder Repeat–Accumulator code block diagram Block diagram of a product code

6 6 6

6 7 8 9

The iterative turbo decoding block diagram Examples of Tanner graphs: (a) tree (b) with cycles Probabilistic graphs Variable x and its connections in the graph

8 8 9 10

10 11

One constraint node and its connections in graph A tree graph

11 12

12 13 14 15 16

Tanner graph for Hamming code, H (7,4) Tanner graph for regular LDPC (3,5) Convolutional code Tanner graph The Tanner graph of Convolutional codes with state variables A trellis section

14 14 15 15 16

17

An example of the graph of a PCCC

16

18 19 20 21

The messages in a convolutional code Block diagram of the SISO Timing diagram of the traditional SISO Message passing between the constituent codes of turbo codes

20 20 21 21

22 23 24 25 26

The iterative decoding structure Pipelined turbo decoder Parallel turbo decoder structure Timing diagram of the parallel SISOs Timing diagram of the parallel SISOs in vector notation

22 23 24 24 25

ix

x

List of Figures

27 28 29

Partitioned graph of a simple PCCC Parallel turbo decoder with shared processors for two constituent codes Performances of parallel decoder

25 26 28

30 31 32

28 29

35

Efficiency and speed gain Efficiency vs. signal to noise ratio (a) Bit sequence in matrix form (b) after row interleaver (c) A conflict-free interleaver (d) Bit sequence in sequential order (e) The conflict-free interleaved sequence Data and extrinsic sequences in two consecutive iterations for turbo decoder with reverse interleaver Sequences in two consecutive iterations for parallel turbo decoder with reverse interleaver Scheduling diagram of the parallel decoder

36 37

The flowchart of the algorithm Performance comparison for B = 1,024

34 36

38 39 40 41

Performance comparison for B = 4,096 (a) alpha recursion (b) beta recursion (c) Extrinsic computation Probability density function of messages in different iterations Constituent code model for density evolution

37 37 42 42

42 43 44

Constituent code model for density evolution SNR improvement in iterative decoding Repeat–Accumulator code block diagram

43 44 44

33 34

30 31 32 32

45 Density evolution for RA codes (q = 3) 46 Accumulator with puncturing and its equivalent for p = 3 47 Block diagram of accumulator with puncturing

46 47 47

48 49 50

Block diagram of check_4 code and its equivalents Normalized distance spectrum of RA codes with puncturing Density evolution for RA codes with puncturing (q = 4, p = 2)

51 54 56

51 52 53 54 55 56 57

The block diagram of the precoder ARA(3,3) BER performance bound ARA(4,4) BER performance bound Normalized distance spectrum of ARA codes with puncturing Density evolution for ARA codes with puncturing (q = 4, p = 2) Performance of ARA codes using iterative decoding The block diagram of the new precoder

57 58 59 60 61 62 63

58 59

Tanner graph for new ARA code Performance of the new ARA code

63 64

List of Figures

xi

60 61 62

The partitioned graph of ARA code Parallel turbo decoder structure Projected graph

68 68 69

63 64 65 66 67 68 69 70

70 71 72 73 74 75 75

71 72 73

Projected graph with conflict-free interleaver A PCCC projected graph with conflict-free interleaver (a) PCCC with 3 component codes (b) SCCC (c) RA(3) (d) IRA(2,3) A parallel LDPC projected graph Simple graphical representation of a LDPC projected graph ARA code without puncturing (a) Rate 1/3 ARA code (b) rate 1/2 ARA code (a) Rate 1/2 ARA code (b) New rate 1/3 ARA code (c) New rate 1/4 ARA code Improved rate 1/2 ARA codes Irregular rate 1/2 ARA codes Irregular ARA code family for rate >1/2

74 75

Parallel decoder hardware architecture Window processor hardware architecture

79 79

76 77 77 78

List of Tables

I Probability Definitions II State Constraint III The Decoder Parameters IV Characteristic Factors for the Parallel Decoder @SNR = 0.7 dB (BER = 10E − 8) V An Example of the Interleaver VI Cut-off Thresholds for RA Codes with Puncturing VII Cut-off Threshold for Rate 1/2 ARA Codes VIII Cutoff Threshold for ARA Codes with Rate