Towards a Design Flow for Reversible Logic
Robert Wille Rolf Drechsler
Towards a Design Flow for Reversible Logic
Robert Wille Institute of Computer Science University of Bremen Bibliothekstr. 1 28359 Bremen Germany
[email protected] Rolf Drechsler Institute of Computer Science University of Bremen Bibliothekstr. 1 28359 Bremen Germany
[email protected] ISBN 978-90-481-9578-7 e-ISBN 978-90-481-9579-4 DOI 10.1007/978-90-481-9579-4 Springer Dordrecht Heidelberg London New York Library of Congress Control Number: 2010932404 © Springer Science+Business Media B.V. 2010 No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Cover design: eStudio Calamar S.L. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
Preface
The development of computing machines found great success in the last decades. But the ongoing miniaturization of integrated circuits will reach its limits in the near future. Shrinking transistor sizes and power dissipation are the major barriers in the development of smaller and more powerful circuits. Reversible logic provides an alternative that may overcome many of these problems in the future. For low-power design, reversible logic offers significant advantages since zero power dissipation will only be possible if computation is reversible. Furthermore, quantum computation profits from enhancements in this area, because every quantum circuit is inherently reversible and thus requires reversible descriptions. However, since reversible logic is subject to certain restrictions (e.g. fanout and feedback are not directly allowed), the design of reversible circuits significantly differs from the design of traditional circuits. Nearly all steps in the design flow (like synthesis, verification, or debugging) must be redeveloped so that they become applicable to reversible circuits as well. But research in reversible logic is still at the beginning. No continuous design flow exists so far. In this book, contributions to a design flow for reversible logic are presented. This includes advanced methods for synthesis, optimization, verification, and debugging. Formal methods like Boolean satisfiability and decision diagrams are thereby exploited. By combining the techniques proposed in the book, it is possible to synthesize reversible circuits representing large functions. Optimization approaches ensure that the resulting circuits are of small cost. Finally, a method for equivalence checking and automatic debugging allows to verify the obtained results and helps to accelerate the search for bugs in case of errors in the design. Combining the respective approaches, a first design flow for reversible circuits of significant size results. This book addresses computer scientists and computer architects and does not require previous knowledge about the physics of reversible logic or quantum computation. The respective concepts as well as the used models are briefly introduced.
v
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Preface
All approaches are described in a self-contained manner. The content of the book does not only conveys a coherent overview about current research results, but also builds the basis for future work on a design flow for reversible logic. Bremen
Robert Wille Rolf Drechsler
Acknowledgements
This book is the result of more than three years of intensive research in the area of reversible logic. During this time, we experienced many support from different people for which we would like to thank them very much. In particular, the Group of Computer Architecture at the University of Bremen earns many thanks for providing a comfortable and inspirational environment. Many thanks go to Stefan Frehse, Daniel Große, Lisa Jungmann, Hoang M. Le, Sebastian Offermann, and Mathias Soeken who actively helped in the development of the approaches described in this book. Sincere thanks also go to Prof. D. Michael Miller from the University of Victoria, Prof. Gerhard W. Dueck from the University of New Brunswick, and Dr. Mehdi Saeedi from the Amirkabir University of Technology in Tehran for very fruitful collaborations. In this context, we would like to thank the German Academic Exchange Service (DAAD) which enabled the close contact with the groups in Canada. Special thanks go to the German Research Foundation (DFG) which funded parts of this work under the contract number DR 287/20-1. Finally, we would like to thank Marc Messing who did a great job of proofreading as well as Christiane and Shawn Mitchell who closely checked the manuscript for English style and grammar.
vii
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Background . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Reversible Functions . . . . . . . . . . . . . . 2.1.2 Reversible Circuits . . . . . . . . . . . . . . . 2.1.3 Quantum Circuits . . . . . . . . . . . . . . . 2.2 Decision Diagrams . . . . . . . . . . . . . . . . . . . 2.2.1 Binary Decision Diagrams . . . . . . . . . . . 2.2.2 Quantum Multiple-valued Decision Diagrams 2.3 Satisfiability Solvers . . . . . . . . . . . . . . . . . . 2.3.1 Boolean Satisfiability . . . . . . . . . . . . . 2.3.2 Extended SAT Solvers . . . . . . . . . . . . .
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Synthesis of Reversible Logic . . . . . . . . . 3.1 Current Synthesis Steps . . . . . . . . . . 3.1.1 Embedding Irreversible Functions . 3.1.2 Transformation-based Synthesis . . 3.2 BDD-based Synthesis . . . . . . . . . . . 3.2.1 General Idea . . . . . . . . . . . . 3.2.2 Exploiting BDD Optimization . . . 3.2.3 Theoretical Consideration . . . . . 3.2.4 Experimental Results . . . . . . . 3.3 SyReC: A Reversible Hardware Language 3.3.1 The SyReC Language . . . . . . . 3.3.2 Synthesis of the Circuits . . . . . . 3.3.3 Experimental Results . . . . . . . 3.4 Summary and Future Work . . . . . . . .
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4
Exact Synthesis of Reversible Logic . . . . . . . . . . . . . . . . . . . 4.1 Main Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 SAT-based Exact Synthesis . . . . . . . . . . . . . . . . . . . . .
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ix
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Contents
4.2.1 Encoding for Toffoli Circuits . . . . . . 4.2.2 Encoding for Quantum Circuits . . . . . 4.2.3 Handling Irreversible Functions . . . . . 4.2.4 Experimental Results . . . . . . . . . . 4.3 Improved Exact Synthesis . . . . . . . . . . . . 4.3.1 Exploiting Higher Levels of Abstractions 4.3.2 Quantified Exact Synthesis . . . . . . . 4.3.3 Experimental Results . . . . . . . . . . 4.4 Summary and Future Work . . . . . . . . . . .
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61 65 68 70 76 77 81 84 91
5
Embedding of Irreversible Functions . 5.1 The Embedding Problem . . . . . 5.2 Don’t Care Assignment . . . . . . 5.2.1 Methods . . . . . . . . . . 5.2.2 Experimental Results . . . 5.3 Synthesis with Output Permutation 5.3.1 General Idea . . . . . . . . 5.3.2 Exact Approach . . . . . . 5.3.3 Heuristic Approach . . . . 5.3.4 Experimental Results . . . 5.4 Summary and Future Work . . . .
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93 94 96 96 99 100 102 104 105 106 111
6
Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Adding Lines to Reduce Circuit Cost . . . . . . . . . . . . . . 6.1.1 General Idea . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . 6.1.3 Experimental Results . . . . . . . . . . . . . . . . . . 6.2 Reducing the Number of Circuit Lines . . . . . . . . . . . . . 6.2.1 General Idea . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 Experimental Results . . . . . . . . . . . . . . . . . . 6.3 Optimizing Circuits for Linear Nearest Neighbor Architectures 6.3.1 NNC-optimal Decomposition . . . . . . . . . . . . . . 6.3.2 Optimizing NNC-optimal Decomposition . . . . . . . . 6.3.3 Experimental Results . . . . . . . . . . . . . . . . . . 6.4 Summary and Future Work . . . . . . . . . . . . . . . . . . .
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113 114 114 116 117 124 125 127 130 131 133 134 138 138
7
Formal Verification and Debugging . . . . . . . 7.1 Equivalence Checking . . . . . . . . . . . . 7.1.1 The Equivalence Checking Problem . 7.1.2 QMDD-based Equivalence Checking 7.1.3 SAT-based Equivalence Checking . . 7.1.4 Experimental Results . . . . . . . . 7.2 Automated Debugging and Fixing . . . . . . 7.2.1 The Debugging Problem . . . . . . . 7.2.2 Determining Error Candidates . . . .
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Contents
7.2.3 Determining Error Locations 7.2.4 Fixing Erroneous Circuits . . 7.2.5 Experimental Results . . . . 7.3 Summary and Future Work . . . . . 8
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161 165 167 173
Summary and Conclusions . . . . . . . . . . . . . . . . . . . . . . . 175
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Acronyms
BDDs CMOS CNF CNOT d HDL LNN NNC MCF MCT P QMDD QF_BV QBF SAT SMT SWOP
Binary Decision Diagrams Complementary Metal Oxide Semiconductor Conjunctive Normal Form Controlled-NOT Number of gates (depth) of a circuit Hardware Description Language Linear Nearest Neighbor Nearest Neighbor Cost Multiple control Fredkin Multiple control Toffoli Peres Quantum Multiple-valued Decision Diagram Quantifier free bit-vector logic Quantified Boolean Formulas Boolean satisfiability SAT Modulo Theories Synthesis with Output Permutation
xiii
Chapter 1
Introduction
In the last decades, great achievements have been made in the development of computing machines. While computers consisting of a few thousands of components filled whole rooms in the early 70’s, nowadays billions of transistors are built on some square millimeters. This is a result of the achievements made in the domain of semiconductors which are still holding on: The number of transistors in a circuit doubles every 18 months (which is also known as Moore’s Law according to the founder of Intel, Gordon E. Moore, who formulated this as a prediction in 1965 [Moo65]).1 Until today, this prediction has not lost any of its validity—each year more complex systems and chips are introduced. However, it is obvious that such an exponential growth must reach its limits in the future—at least when the miniaturization reaches a level, where single transistor sizes are approaching the atomic scale. Besides that, power dissipation more and more becomes a crucial issue for designing high performance digital circuits. In the last decades, the amount of power dissipated in the form of heat to the surrounding environment of a chip increased by orders of magnitudes. Since excessive heat may decrease the reliability of a chip (or even destroys it), power dissipation is one of the major barriers to progress the development of smaller and faster computer chips. Due to these reasons, some researchers expect that from the 2020s on, duplication of transistor density will not be possible any longer. To further satisfy the needs for more computational power, alternatives are needed that go beyond the scope of “traditional” technologies like CMOS.2 Reversible logic marks a promising new direction where all operations are performed in an invertible manner. That is, in contrast to traditional logic, all computations can be reverted (i.e. the inputs can be obtained from the outputs and vice versa). A simple standard operation like the logical AND already illustrates that reversibility is not guaranteed in traditional circuit systems. Indeed, it is possible to obtain the inputs of an AND gate if the output is assigned to 1 (then both inputs must be as1 Originally,
Moore predicted a doubling every 12 months; ten years later he updated to 18 months.
2 CMOS
is the abbreviation for Complementary Metal Oxide Semiconductor, the technology mainly used for today’s integrated circuits. R. Wille, R. Drechsler, Towards a Design Flow for Reversible Logic, DOI 10.1007/978-90-481-9579-4_1, © Springer Science+Business Media B.V. 2010
1
2
1 Introduction
signed to 1 as well). But, it is not possible to determine the input values if the AND outputs 0. In contrast, reversible logic allows bijective operations only, i.e. n-input n-output functions that map each possible input vector to a unique output vector. This reversibility builds the basis for emerging technologies that may replace or at least enhance the traditional computer chip. Two examples of such technologies making use of reversible logic are sketched in the following: • Reversible Logic for Low-Power Design As mentioned above, power dissipation and therewith heat generation is a serious problem for today’s computer chips. A significant part of energy dissipation is due to the non-ideal behaviors of transistors and materials. Here, higher levels of integration and new fabrication processes reduced the heat generation in the last decade. However, a more fundamental reason for power dissipation arises from the observations made by Landauer in 1961 [Lan61]. Landauer proved that using traditional (irreversible) logic, gates always lead to energy dissipation regardless of the underlying technology. More precisely, exactly k · T · log 2 Joule of energy is dissipated for each “lost” bit of information during the irreversible operation (where k is the Boltzmann constant and T is the temperature). While this amount of power currently does not sound significant, it may become crucial additionally considering that (1) today millions of operations are performed in some seconds (i.e. increasing processor frequency multiplies this amount) and (2) more and more operations are performed with smaller and smaller transistor sizes (i.e. in a smaller area). In contrast, Bennett showed that energy dissipation is reduced or even eliminated if computation becomes information-lossless [Ben73]. This holds for reversible logic, since data is bijectively transformed without losing any of the original information. Bennett proved that circuits with zero power dissipation are only possible if they are built from reversible gates. In 2002, first reversible circuits have been built that exploit this observation [DV02]. In fact, these circuits were powered by their input signals only (i.e. without additional power supplies). In the future, such circuits may be an alternative that can cope with the heat generation problem of traditional chips. Furthermore, since reversible circuits already work with low power, applications are also possible in domains where power is a limited resource (e.g. for mobile computation). • Reversible Logic as a Basis for Quantum Computation Quantum circuits [NC00] offer a new kind of computation. Instead of logic signals 0 and 1, quantum circuits make use of qubits. A qubit is a two level quantum system, described by a two dimensional complex Hilbert space. The resulting tools can be obtained under www.revkit.org. This allows to represent not only 0 and 1 but also a superposition of both. As a result, qubits may represent multiple states at the same time enabling enormous speed-ups in computations. For example, it has been shown that using a quantum circuit it is possible to solve the factorization problem in polynomial time, while for traditional circuits only exponential methods exist [Sho94, VSB+01].
1 Introduction
3
But, research in the area of quantum circuits is still at the beginning. Nevertheless, first promising results exist: At the University of Innsbruck one of the first quantum circuits consisting of 8 qubits was built in 2005. This has been further improved so that today circuits with dozens of qubits exists—with upward trend. Even first commercial realizations of quantum circuits (e.g. a random number generator) are available. Reversible logic is important in this area because every quantum operation is inherently reversible. Thus, progress in the domain of reversible logic can be directly applied to quantum logic. Besides that, reversible logic additionally finds application in domains like optical computing [CA87], DNA computing [TS05], as well as nanotechnologies [Mer93]. Also, cryptography or encoding/decoding methods (e.g. for music and videos) can profit from enhancements in this area (see e.g. [ML01]). Furthermore, already today reversible operations are used in instruction sets for microprocessors [SL00]. The basic concepts of reversible logic are thereby not new and have already been introduced in the 60’s by Landauer [Lan61] and were further refined by Bennett [Ben73] and Toffoli [Tof80]. They observed that due to the reversibility, a straightforward usage of fanouts and feedback is not possible in reversible logic. Furthermore, new libraries of (reversible) gates have been introduced to represent invertible operations [Tof80, FT82, Per85, NC00] and it was stated that each reversible circuit must be a cascade of these reversible gates. Even if this still represents the basis for research in the area of reversible logic, the topic was not intensively studied by computer scientists before the year 2000. The main reason for that may lie in the fact that applications of reversible logic (in particular in the domain of quantum computation) have been seen as “dreams of the future”. But, this changed as with factorization a very important problem (factorization builds the basis for most of the today’s encrypting methods) was solved on a physically implemented quantum circuit [Sho94, VSB+01]. Therewith, a proof of concept was available showing that quantum computing, in fact, may be one solution for future computational problems. In particular, this achievement (together with further ones e.g. in reversible CMOS design as mentioned above) significantly moved the topic forward so that nowadays reversible logic is seen as a promising research area. As a consequence, in the last years computer scientists have also started to develop new methods e.g. for synthesis of reversible circuits. However, no real design flow for reversible logic exists until today. This is crucial since, due to the mentioned restrictions (e.g. no fanout and feedback), the design of reversible circuits significantly differs from the design of traditional circuits. Nearly all elaborated methods for synthesis, verification, debugging, and test available for traditional circuit design must be redeveloped so that they become applicable to reversible circuits as well. Now, while applications of reversible logic are starting to become feasible and traditional technologies more and more suffer from the increasing miniaturization, it is even more necessary to work towards such a flow. Moreover, considering the traditional design flow, it can be concluded that until today, computer scientists cannot fully exploit the technical state-of-the-art. That is, the number of transistors that can be physically implemented on a chip grows faster
4
1 Introduction
Fig. 1.1 Proposed design flow
than the ability to design them in a useful manner (also known as the design gap). This becomes even more crucial if, additionally, the ability to verify the correctness of the designed circuits is considered (known as the verification gap). Once reversible logic becomes feasible for large designs in the future, researchers will be faced with similar challenges. Thus, it is worth working towards a design flow for reversible logic already today. First steps in this direction have been made in the domain of synthesis (see e.g. [SPMH03, MDM05]), verification (see e.g. [VMH07, GNP08]), and test (see e.g. [PHM04, PBL05, PFBH05]). However, they are all still far away from covering real design needs. As an example, most synthesis approaches are only applicable for small functions and often produce circuits with relatively high cost. In contrast, design methods to create complex circuits and to efficiently verify their correctness are needed. This book makes contributions to a future design flow for reversible logic by proposing advanced methods for synthesis, optimization, verification, and debugging. Figure 1.1 shows the interaction of the proposed steps in an integrated flow. The left-hand side sketches the restrictions or challenges, respectively, to be solved in comparison to traditional methods. By combining the techniques proposed in the book, it is possible to synthesize reversible circuits representing large functions. Optimization methods ensure that the resulting circuits are of small cost. Finally, methods for equivalence checking and automatic debugging allow to verify the obtained results and help to accelerate the search for bugs in case of errors in the design. In the following, the respective contributions are briefly introduced in the order they appear in this book. A more detailed description of the problems as well as the proposed solutions is given at the beginning of each chapter.
1 Introduction
5
As a starting point, synthesis is considered in Chap. 3. Currently, the synthesis of reversible logic or quantum circuits, respectively, is limited. In the past, only methods have been proposed that are applicable for relatively small functions, i.e. functions with at most 30 variables. In addition, these methods often require an enormous amount of run-time. After reviewing the reasons for these limitations, a new synthesis method based on Binary Decision Diagrams (BDDs) is proposed. This enables synthesis of functions containing over 100 variables and thus is a major step towards design of complex systems in reversible logic. Additionally, a hardware description language is introduced that allows to specify and afterwards synthesize complex circuits in reversible logic. The problem of exact synthesis is considered in Chap. 4. Exact synthesis methods generate minimal circuits for a given function. Naturally, exact synthesis approaches are only applicable for very small functions. But, the resulting circuit realizations can be used later e.g. as building blocks for heuristic approaches. Nevertheless, run-time is the limiting factor here. The chapter describes how techniques of Boolean satisfiability (SAT) can be exploited for efficient exact synthesis of reversible circuits. Further approaches incorporating problem-specific knowledge as well as quantification are then introduced. These methods allow further accelerations of the exact synthesis. With these different synthesis approaches as a basis, the problem of embedding is addressed in Chap. 5. Usually, most of the synthesis approaches require a reversible function as input. But, basic functions like AND or addition are inherently irreversible. Thus, before synthesis, these functions must be embedded into reversible ones. This requires the addition of extra circuit signals and therewith constant inputs, garbage outputs, as well as don’t care conditions at the outputs. Furthermore, the order of outputs may be chosen arbitrarily. All this affects the generated synthesis result. In Chap. 5, methods for finding good embeddings are proposed and evaluated. After synthesis, the resulting circuits often are of high cost. In particular, dedicated technology-specific constraints are not considered by synthesis approaches. To address this, in Chap. 6 three different optimization methods are introduced—each with an own focus on a particular cost metric. The first one considers the reduction of the well-established quantum cost (used in quantum circuits) and the transistor cost (used in CMOS implementations), respectively. The second one addresses the number of lines in a circuit which particularly is important for all quantum realizations. Finally, an approach is introduced that takes a new cost metric based on a dedicated physical realization of quantum circuits into account. This allows that designers can automatically optimize their circuits with respect to the special needs of the addressed technology. To ensure that the respective results (e.g. obtained by optimization) still represent the desired functionality, verification is applied. For this purpose, in Chap. 7 equivalence checkers are introduced that can handle circuits with several thousands of gates in a very short time. Furthermore, an automatic approach for debugging is proposed. Instead of manually searching for the source of an error, this method allows a fast calculation of a reduced set of error candidates to be considered or even to automatically fix the erroneous circuit, respectively.
6
1 Introduction
Fig. 1.2 Structure of the book
Altogether, the contributions of this book to the design flow for reversible logic can be summarized as follows: • Synthesis methods for large functions (i.e. functions with more than 100 variables) • A hardware description language for reversible logic • Exact approaches for synthesizing minimal circuits that can later be used as building blocks • Embedding methods to automatically realize circuits for irreversible functions • Optimization approaches to reduce the cost with respect to the addressed technology • Equivalence checking of large circuits (i.e. circuits with several thousands of gates) • Automatic debugging and fixing of erroneous circuits All proposed methods have been implemented and experimentally evaluated. To this end, a uniform format for specifying reversible functions as well as reversible circuits has been defined which was used in all experiments throughout this book (see also the note on benchmarks on p. 26). Furthermore, all benchmark functions as well as the circuits have been made online available at RevLib under www.revlib.org. The resulting tools can be obtained under www.revkit.org. This allows other researchers to compare their results with the ones obtained in this work. However, the results together with a discussion, related work, and future research directions are, of course, also given in the respective chapters. According to the outline sketched above, the remainder of this book is structured as depicted in Fig. 1.2. The next chapter gives a more detailed introduction into both reversible as well as quantum logic and provides the basic notations and definitions as used in the rest of this book. Afterwards, the chapters about synthesis (Chap. 3), optimization (Chap. 6), as well as verification and debugging (Chap. 7) can be read independently of each other. Only for Chap. 4 about exact synthesis and Chap. 5 about embedding irreversible functions is it recommended to read the previous chapters beforehand. Chapter 8 summarizes all findings and gives directions for future work.
Chapter 2
Preliminaries
This chapter provides the basic definitions and notations to keep the remaining book self-contained. The chapter is divided into three parts. In the first section, Boolean functions, reversible functions, and the respective circuit descriptions are introduced. This builds the basis for all approaches described in this book. Since many of the proposed techniques exploit decision diagrams and satisfiability solvers, respectively, the basic concepts of these core techniques are also introduced in the last two sections. All descriptions are thereby kept brief. For a more in-depth treatment, references to further reading are given in the respective sections.
2.1 Background Reversible logic realizes bijective Boolean functions. Thus, first the basics regarding Boolean functions are revisited and further extended by a description of the properties specifically applied to reversible functions. Then, reversible circuits as well as quantum circuits are introduced which are used as realizations of reversible functions.
2.1.1 Reversible Functions Every logic computation can be defined as a function over Boolean variables B ∈ {0, 1}. More precisely: Definition 2.1 A Boolean function is a mapping f : Bn → B with n ∈ N. A function f is defined over its input variables X = {x1 , x2 , . . . , xn } and hence is also denoted by f (x1 , x2 , . . . , xn ). The concrete mapping is described in terms of Boolean expressions which are formed over the variables from X and the operations ∧ (AND), ∨ (OR), as well as · (NOT). R. Wille, R. Drechsler, Towards a Design Flow for Reversible Logic, DOI 10.1007/978-90-481-9579-4_2, © Springer Science+Business Media B.V. 2010
7
8 Table 2.1 Boolean functions
2 Preliminaries (a) AND
(b) OR
(c) NOT
x1 x2
x1 ∧ x2
x1 x2
x1 ∨ x2
x1
x1
0 0
0
0 0
0
0
1
0 1
0
0 1
1
1
0
1 0
0
1 0
1
1 1
1
1 1
1
Example 2.1 Table 2.1 shows the truth tables of the operations AND, OR, and NOT, respectively. Each truth table has 2n rows, showing the mapping of each input pattern to the respective output pattern. Taking AND, OR, and NOT as a basis, every Boolean function can be derived. For example, the often used functions XOR, implication, and equivalence are derived as follows: • XOR: x1 ⊕ x2 := (x1 ∧ x 2 ) ∨ (x 1 ∧ x2 ) • Implication: x1 ⇒ x2 := x 1 ∨ x2 • Equivalence: x1 ⇔ x2 := x1 ⊕ x2 So far, single-output functions have been introduced. However, in practice also multi-output functions are widely used. Definition 2.2 A multi-output Boolean function is a mapping f : Bn → Bm with n, m ∈ N. More precisely, it is a system of Boolean functions fi (x1 , x2 , . . . , xn ) with 1 ≤ i ≤ m. In the following multi-output functions are also termed as n-input, m-output functions or n × m functions, respectively. Example 2.2 Table 2.2(a) shows the truth table of a 3-input, 2-output function representing the adder function. This book considers reversible functions. Reversible functions are a subset of multi-output functions and are defined as follows: Definition 2.3 A multi-output function f : Bn → Bm is a reversible function iff • its number of inputs is equal to the number of outputs (i.e. n = m) and • it maps each input pattern to a unique output pattern. In other words, each reversible function is a bijection that performs a permutation of the set of input patterns. A function that is not reversible is termed irreversible. Example 2.3 Table 2.2(c) shows a 3-input, 3-output function. This function is reversible, since each input pattern maps to a unique output pattern. In contrast the function depicted in Table 2.2(a) is irreversible, since n = m. Moreover, also the
2.1 Background
9
Table 2.2 Multi-output functions (a) Irrev. (Adder) (b) Irreversible
(c) Reversible
x1
x2
x3
f1
f2
x1 x2 x3
f1 f2 f3
x1 x2 x3
f1 f2 f3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
1
1
0
1
1
0
0
0
1
1
0
0
1
0
0
1
0
0
0
0
1
1
0
1
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
function in Table 2.2(b) is irreversible. Here, the number n of inputs indeed is equal to the number m of outputs, but there is no unique input-output mapping. For example, both inputs 000 and 001 map to the output 000. Quite often, (irreversible) multi-output Boolean functions should be represented by reversible circuits. This necessitates the irreversible function to be embedded into a reversible one which requires the addition of constant inputs and garbage outputs defined as follows: Definition 2.4 A constant input of a reversible function is an input that is set to a fixed value (either 0 or 1). Definition 2.5 A garbage output of a reversible function is an output which is a don’t care for all possible input conditions. The problem of embedding is an integral part of synthesis which is described later in this book. In particular, Sect. 3.1.1 and Chap. 5 cover the respective aspects in detail. Reversible functions can be realized by reversible logic. Due to its special properties, reversible logic found large interest in several domains like low-power design or quantum computation (see Chap. 1). As a result, synthesis of reversible functions has become an intensively studied topic in the last years. Therefore, new kinds of circuits have been proposed that are introduced and compared to traditional circuits in the next section.
2.1.2 Reversible Circuits A circuit realizes a Boolean function. Usually, a circuit is composed of signal lines and a set of basic gates (called gate library). For traditional circuits, often the gate
10
2 Preliminaries
Fig. 2.1 Traditional circuit elements
library depicted in Fig. 2.1 is used. This includes gates for the operations AND, OR, and NOT, based on which any Boolean function can be realized. Furthermore, fanouts are applied to use signal values more than once. In contrast, to realize reversible logic some restrictions must be considered: fanouts and feedback are not directly allowed, since they would destroy the reversibility of the computation [NC00]. Also, the gate library from above as well as the traditional design flow cannot be utilized. As a result, a cascade structure over reversible gates is the established model to realize reversible logic. Definition 2.6 A reversible circuit G over inputs X = {x1 , x2 , . . . , xn } is a cascade of reversible gates gi , i.e. G = g0 g1 · · · gd−1 where d is the number of gates. A reversible gate has the form g(C, T ), where C = {xi1 , . . . , xik } ⊂ X is the set of control lines and T = {xj1 , . . . , xjl } ⊂ X with C ∩ T = ∅ is the set of target lines. C may be empty. The gate operation is applied to the target lines iff all control lines meet the required control conditions. Control lines and unconnected lines always pass through the gate unaltered. In the literature, three types of reversible gates have been established: • A (multiple control) Toffoli gate (MCT) [Tof80] has a single target line xj and maps (x1 , x2 , . . . , xj , . . . , xn ) to (x1 , x2 , . . . , xi1 xi2 · · · xik ⊕ xj , . . . , xn ). That is, a Toffoli gate inverts the target line iff all control lines are assigned to 1. • A (multiple control) Fredkin gate (MCF) [FT82] has two target lines xj1 and xj2 . The gate interchanges the values of the target lines iff the conjunction of all control lines evaluates to 1. • A Peres gate (P) [Per85] has a control line xi , a target line xj1 , and a line xj2 that serves as both, control and target. It maps (x1 , x2 , . . . , xj1 , . . . , xj2 , . . . , xn ) to (x1 , x2 , . . . , xi xj2 ⊕xj1 , . . . , xi ⊕xj2 , . . . , xn ) and thus is a cascade of two MCT gates. Example 2.4 Figure 2.2 shows a Toffoli gate (a), a Fredkin gate (b), and a Peres gate (c) together with a truth table of its functionality. A ● is used to indicate a control line, while an ⊕ (×) is used for denoting the target line of a Toffoli and Peres gate (Fredkin gate). Remark 2.1 These definitions also provide the basis for other gate types. For example, the Toffoli gate builds the basis for the NOT gate (a Toffoli gate with no control lines, i.e. with C = ∅), for the controlled-NOT gate (a Toffoli gate with one control
2.1 Background
11
Fig. 2.2 Reversible gates
Fig. 2.3 Reversible circuits
line),1 as well as for the Toffoli gate as originally proposed in [Tof80]. In contrast, the Fredkin gate builds the basis for a SWAP gate (a Fredkin gate with C = ∅, i.e. an interchanging of two lines). In the following, the notations MCT(C, xj ), MCF(C, xj1 , xj2 ), and P (xi , xj1 , xj2 ) are used to denote a Toffoli, Fredkin, and Peres gate, respectively. The number of control lines, a Toffoli (Fredkin) gates consists of, defines the size of the gate. Using these gate types, universal libraries can be composed. A gate library is called universal, if it enables the realization of any reversible function. For example, it has been proven that every reversible function can be realized using MCT gates only [MD04b]. Also, the gate library consisting of NOT, CNOT, and two-controlled Toffoli gates is universal [SPMH03]. In contrast, a library including only CNOT gates allows the realization of linear reversible functions only [PMH08]. Example 2.5 Figure 2.3 shows reversible circuits realizing the function depicted in Table 2.2(c) with the help of Toffoli and Fredkin gates, respectively. As for their traditional counterparts, the complexity of reversible circuits is measured by means of different cost metrics. More precisely, the cost of the respective circuits is defined as follows: 1 The
controlled-NOT gate is also known as CNOT or Feynman gate.
12
2 Preliminaries
Table 2.3 Quantum cost for Toffoli and Fredkin gates N O . OF CONTROL LINES
Q UANTUM COST OF A
T OFFOLI GATE
OF A
0
1
3
1
1
7
2
5
15
3
13
F REDKIN GATE
28, if at least 2 lines are unconnected 31, otherwise
4
26, if at least 2 lines are unconnected 29, otherwise
40, if at least 3 lines are unconnected 54, if 1 or 2 lines are unconnected 63, otherwise
5
6
38, if at least 3 lines are unconnected
52, if at least 4 lines are unconnected
52, if 1 or 2 lines are unconnected
82, if 1, 2 or 3 lines are unconnected
61, otherwise
127, otherwise
50, if at least 4 lines are unconnected
64, if at least 5 lines are unconnected
80, if 1, 2 or 3 lines are unconnected
102, if 1, 2, 3 or 4 lines are unconnected
125, otherwise
255, otherwise
Definition 2.7 A reversible circuit G = g0 g1 · · · gd−1 has cost of c=
d−1
ci ,
i=0
where ci denotes the cost of gate gi . The concrete cost for a single gate of course depends on the respective type but also on the addressed technology. In this book, the following cost metrics are used: • Gate count denotes the number of gates the circuit consists of (i.e. ci = 1 and c = d). • Quantum cost denotes the effort needed to transform a reversible circuit to a quantum circuit (see also next section). Table 2.3 shows the quantum cost for a selection of Toffoli and Fredkin gate configurations as introduced in [BBC+95] and further optimized in [MD04a] and [MYDM05]. As can be seen, gates of larger size are considerably more expensive than gates of smaller size. The Peres gate
2.1 Background
13
represents a special case, since it has quantum cost of 4, while the realization with two Toffoli gates would imply a cost of 6. • Transistor cost denotes the effort needed, to realize a reversible circuit in CMOS according to [TG08]. The transistor cost of a reversible gate is 8 · s where s is the number of control lines. Example 2.6 Consider the circuits from Example 2.5 depicted in Fig. 2.3. The Toffoli circuit has a gate count of 6, quantum cost of 10, and transistor cost of 56, while the Fredkin circuit has a gate count of 3, quantum cost of 13, and transistor cost of 8, respectively. As can be seen, the costs significantly differ depending on the applied cost model. Even if the number of gates in a cascade is a very simple measure of its complexity, it is the most technology-independent metric. Thus, the gate count is often used to evaluate the quality of a reversible circuit. Besides that, also the quantum cost metric is popular because it represents a measure for the most intensely studied application (namely quantum computation) and considers larger gates to be more costly. The transistor cost model is a relatively new model that arose with the application of reversible circuits to the area of low-power CMOS design. In this book, gate count and quantum cost are primarily considered as it allows a fair comparison of synthesis results with respect to previous work. Transistor costs are additionally addressed where appropriate. Finally, a special property of reversible logic is reviewed: Lemma 2.1 If the cascade of MCT gates G = g0 g1 · · · gd−1 realizes a reversible function f , then the reverse cascade G = gd−1 gd−2 · · · g0 realizes the inverse function f −1 . Proof Each reversible gate realizes a reversible function. That is, for each input pattern a unique output pattern, i.e. a one-to-one mapping, exists. Thus, calculating the inverse of the function f for an output pattern is essentially the same operation as propagating this pattern backwards through the circuit. This lemma is particularly exploited during synthesis of reversible logic as described later in this book. The next section considers quantum circuits and how they are derived from reversible logic.
2.1.3 Quantum Circuits Quantum computation [NC00] is a promising application of reversible logic. Every quantum circuit works on qubits instead of bits. In contrast to Boolean logic, qubits do not only allow to represent Boolean 0’s and Boolean 1’s, but also the superposition of both. More formally:
14
2 Preliminaries
Definition 2.8 A qubit is a two level quantum system, described by a two dimensional complex Hilbert space. The two orthogonal quantum states 1 0 |0 ≡ and |1 ≡ 0 1 are used to represent the Boolean values 0 and 1. Any state of a qubit may be written as |Ψ = α|0 + β|1, where α and β are complex numbers with |α|2 + |β|2 = 1. The quantum state of a single qubit is denoted by the vector α . β The state of a quantum system with n > 1 qubits is given by an element of the tensor product of the respective state spaces and can be represented as a normalized vector of length 2n , called the state vector. The state vector is changed through multiplication of appropriate 2n × 2n unitary matrices. Thus, each quantum computation is inherently reversible but manipulates qubits rather than pure logic values. At the end of the computation, a qubit can be measured. Then, depending on the current state of the qubit a 0 (with probability of |α|2 ) or a 1 (with probability of |β|2 ) returns, respectively. After the measurement, the state of the qubit is destroyed. In other words, using quantum computation and qubits in superposition, functions can be evaluated with different possible input assignments in parallel. But, it is not possible to obtain the current state of a qubit. Instead, if a qubit is measured, either 0 or 1 is returned depending on the respective probability. Nevertheless, researchers exploited quantum computation (in particular superposition) to solve many practically relevant problems faster than by traditional computing machines. For example, it was possible to solve the factorization problem in polynomial time— for traditional machines only exponential algorithms are known. Even if the research in this area is still at the beginning (so far, quantum algorithms with only up to 28 qubits have been implemented), these first promising results motivate further research in this area. The focus of this book is how to design reversible and quantum circuits, respectively. Thus, in the following the model for quantum circuits as used in this book is introduced. For a more detailed treatment of the respective physical background, the reader is referred to [Pit99, NC00, Mer07]. Definition 2.9 A quantum circuit Q is a cascade of quantum gates qi , i.e. Q = q0 · · · qd−1 . In this book, the following quantum gates are considered: • Inverter (NOT): A single qubit is inverted. • Controlled inverter (CNOT): The target qubit is inverted if the control qubit is 1. • Controlled V gate: A V operation is performed on the target qubit if the control qubit is 1. The V operation is also known as the square root of NOT, since two consecutive V operations are equivalent to an inversion.
2.1 Background
15
Fig. 2.4 Quantum gates
Fig. 2.5 State transitions for NOT, CNOT, V, and V+ operations
• Controlled V+ gate: A V+ operation is performed on the target qubit if the control qubit is 1. The V+ gate performs the inverse operation of the V gate, i.e. V + ≡ V −1 . The notation for these gates along with their corresponding 2n × 2n unitary matrices is shown in Fig. 2.4. In the following, the input to a quantum circuit as well as to each control line of a gate is restricted to 0 and 1. This has the effect that the value of each qubit is restricted to one value of the set {0, 1, V0 , V1 }, i.e. a 4-valued logic with 1+i 1 1 + i −i V0 = and V1 = −i 1 2 2 is applied. Figure 2.5 shows the resulting transitions with respect to the possible NOT, CNOT, V, and V+ operations. By restricting the quantum circuit model in this way, physical effects like superposition (and entanglement [NC00]) are excluded from the following consideration so that automated approaches (e.g. for synthesis, optimization, verification, etc.) become applicable. Nevertheless, the restricted model remains realistic for many applications. As an example, many of today’s quantum algorithms (e.g. Deutsch’s algorithm or Grover’s algorithm [NC00]) include quantum realizations of reversible (Boolean) functions. Thus, the mentioned restrictions are common in the design of quantum circuits.
16
2 Preliminaries
Fig. 2.6 Quantum circuit
Fig. 2.7 Pairs of quantum gates with unit cost
Example 2.7 Figure 2.6 shows a quantum circuit realizing the reversible function depicted in Table 2.2(c). All quantum gates are assumed to be the basic blocks of each quantum computation. This is also reflected in the cost metric. Definition 2.10 Each quantum gate has cost of 1. Thus, the cost of a quantum circuit is defined by the number d of its gates. Remark 2.2 In previous work, also an extended cost metric has been applied: When a CNOT and a V (or V+) gate are applied to the same two qubits, the cost of the pair can be considered unit as well [SD96, HSY+06]. The possible pairs (denoted by double gates in the following) are shown in Fig. 2.7. In this book, primarily the cost metric from Definition 2.10 is applied. However, all approaches can also be extended to consider unit cost of double gates. Exemplarily, this is shown for exact synthesis of quantum circuits in Sect. 4.2.2. Since quantum circuits are inherently reversible, every reversible circuit can be transformed to a quantum circuit. To this end, each gate of the reversible circuit is decomposed into a cascade of quantum gates. Example 2.8 Figure 2.8(a) (Fig. 2.8(b)) shows the quantum gate cascade which can be used to transform a Toffoli (Fredkin) gate to a quantum circuit. As can be seen, the number of required quantum gates is equal to the quantum cost of the Toffoli (Fredkin) gate as introduced in Table 2.3. Exploiting these decompositions, synthesis of quantum circuits can be approached from two different angles: (1) Targeting quantum gates directly during the synthesis process or (2) synthesizing reversible circuits first that are later mapped into quantum circuits.
2.2 Decision Diagrams To represent Boolean (including reversible) functions and circuits, decision diagrams can be applied. They provide an efficient data-structure that can represent
2.2 Decision Diagrams
17
Fig. 2.8 Decomposition of reversible gates to quantum circuits
large functions in a more compact way than truth tables. In the past, several types of decision diagrams have been introduced. In this book, Binary Decision Diagrams (BDDs) [Bry86] are considered to represent Boolean functions. Quantum Multiple-valued Decision Diagrams (QMDDs) [MT06, MT08] are used to represent reversible functions that may include quantum operations. Both are briefly introduced in this section.
2.2.1 Binary Decision Diagrams A Boolean function f : Bn → B can be represented by a graph-structure defined as follows: Definition 2.11 A Binary Decision Diagram (BDD) over Boolean variables X with terminals T = {0, 1} is a directed acyclic graph G = (V , E) with the following properties: 1. Each node v ∈ V is either a terminal or a non-terminal. 2. Each terminal node v ∈ V is labeled by a value t ∈ T and has no outgoing edges. 3. Each non-terminal node v ∈ V is labeled by a Boolean variable xi ∈ X and represents a Boolean function f . 4. In each non-terminal node (labeled by xi ), the Shannon decomposition [Sha38] f = x i fxi =0 + xi fxi =1 is carried out, leading to two outgoing edges e ∈ E whose successors are denoted by low(v) (for fxi =0 ) and high(v) (for fxi =1 ), respectively. The size of a BDD is defined by the number of its (non-terminal) nodes. Example 2.9 Figure 2.9 shows a BDD representing the function f = x1 ⊕ x2 · x3 . Edges leading to a node fxi =0 (fxi =1 ) are marked by a 0 (1). This BDD has a size of 5.
18
2 Preliminaries
Fig. 2.9 BDD representing f = x1 ⊕ x2 · x3
A BDD is called free if each variable is encountered at most once on each path from the root to a terminal node. A BDD is called ordered if in addition all variables are encountered in the same order on all such paths. The respective order is defined by π : {1, . . . , n} → {1, . . . , n}. Finally, a BDD is called reduced if it does neither contain isomorphic sub-graphs nor redundant nodes. To achieve reduced BDDs, reduction rules as depicted in Fig. 2.10 are applied. Applying the reduction rules leads to shared nodes, i.e. nodes that have more than one predecessor. Example 2.10 Figure 2.11 shows two reduced ordered BDDs representing the function f = x1 ·x2 +x3 ·x4 +· · ·+xn−1 ·xn . For the order x1 , x2 , . . . , xn−1 , xn , the BDD depicted in Fig. 2.11(a) has a size of O(n), while the BDD depicted in Fig. 2.11(b) with the order x1 , x3 , . . . , xn−1 , x2 , x4 , . . . , xn has size of O(2n ). Remark 2.3 In the following, reduced ordered binary decision diagrams are called BDDs for brevity. BDDs are canonical representations, i.e. for a given Boolean function and a fixed order, the BDD is unique [Bry86]. As shown by Example 2.10, BDDs are very sensitive to the chosen variable order. It has been shown in [BW96] that proving the existence of a BDD with a lower number of nodes (i.e. proving that no other order leads to a smaller BDD size) is NP-complete. As a consequence, several heuristics to find good orders have been proposed. In particular, sifting [Rud93] has been shown to be quite effective. Further reductions of the BDD size can be achieved, if complement edges [BRB90] are applied. They allow to represent a function as well as its complement by one single node only. BDDs can also be used to represent multi-output functions. Then, all BDDs for the respective functions are shared, i.e. isomorphic sub-functions are represented by a single node as well. For a more comprehensive introduction into BDDs, the reader is refereed to [DB98, EFD05]. For the application of BDDs in practice, many well-engineered BDD packages (e.g. CUDD [Som01]) are available.
2.2 Decision Diagrams
19
Fig. 2.10 Reduction rules for BDDs
Fig. 2.11 BDDs with different variable orders
2.2.2 Quantum Multiple-valued Decision Diagrams As described in Sect. 2.1.3, quantum operations are defined by 2n × 2n unitary matrices (consider again Fig. 2.4 on p. 15 for examples). Thus, to represent functions including quantum operations, an adjusted data-structure is needed. Quantum Multiple-valued Decision Diagrams (QMDDs) [MT06, MT08] provide for the representation and manipulation of r n × r n complex-valued matrices with r pure logic states. This includes unitary matrices and thus QMDDs can be applied to represent quantum gates and circuits. Since in this book QMDDs are used as black box only (in contrast to BDDs), a formal definition of QMDDs is omitted and instead they are introduced by exemplarily describing the general idea.
20
2 Preliminaries
Fig. 2.12 QMDD representing the matrix of a single V gate
A QMDD structure is based on partitioning an r n × r n matrix M into r 2 submatrices, each of dimension r n−1 × r n−1 as shown in the following equation: ⎛ ⎞ M0 M1 · · · Mr−1 ⎜ ⎟ ⎜ Mr Mr+1 · · · M2r−2 ⎟ ⎜ ⎟ . M =⎜ . .. .. ⎟ .. ⎜ .. . . . ⎟ ⎝ ⎠ Mr 2 −r Mr 2 −r+1 · · · Mr 2 −1 In the following, the concepts of QMDDs are briefly presented by way of the following example of a single V gate. Example 2.11 Figure 2.12(a) shows a V gate in a 3-line circuit. The unitary matrix describing the behavior of this gate is given in Fig. 2.12(b) where v = 1+i 2 and v = 1−i . The QMDD for this matrix is given in Fig. 2.12(c). The edges from each 2 non-terminal node point to four sub-matrices indexed 0, 1, 2, 3 from left to right. Each edge has a complex-valued weight. For clarity, edges with weight 0 are indicated as stubs. In fact, they point to the terminal node. The key features of QMDD are evident in this example. There is a single terminal node. Furthermore, each edge has a complex-valued weight. Each non-terminal node represents a matrix partitioning. For example, the top node in Fig. 2.12(c) represents the partitioning shown in Fig. 2.12(b). The non-terminal nodes lower in the diagram represent similar partitioning of the resulting sub-matrices. The representation of common sub-matrices is shared. To ensure the uniqueness of the representation, edges with weight 0 must point to the terminal node and normalization is applied to non-terminal nodes so that the lowest indexed edge with non-zero weight has weight 1. As for BDDs, an efficient implementation exists also for QMDDs. However, since QMDD involve multiple edges from nodes and are applicable to both binary
2.3 Satisfiability Solvers
21
and multiple-valued problems, the QMDD package is not built using a standard decision diagram package. Nevertheless, the implementation employs well-known decision diagram techniques like sharing, reordering, and so on. For a more comprehensive introduction into QMDDs, the reader is referred to [MT08].
2.3 Satisfiability Solvers The methods described in this book make use of techniques for solving the Boolean satisfiability problem (SAT problem). The SAT problem is one of the central NP-complete problems. In fact, it was the first known NP-complete problem that was proven by Cook in 1971 [Coo71]. Despite this proven complexity, efficient solving algorithms have been developed that found great success as proof engines for many practically relevant problems. Today there exists algorithms exploiting SAT that solve many practical problem instances, e.g. in the domain of automatic test pattern generation [Lar92, DEF+08], logic synthesis [ZSM+05], debugging [SVAV05], and verification [BCCZ99, CBRZ01, PBG05]. In this section, the SAT problem, the respective solving algorithm, and its application are introduced. Furthermore, extended SAT solvers additionally exploiting bit-vector logic, quantifiers, or problem-specific modules, respectively, are briefly reviewed. These engines are used later as core techniques for selected steps in the proposed flow for reversible logic.
2.3.1 Boolean Satisfiability The Boolean satisfiability problem (SAT problem) is defined as follows: Definition 2.12 Let h : Bn → B be a Boolean function. Then, the SAT problem is to find an assignment to the variables of h such that h evaluates to 1 or to prove that no such assignment exists. In other words, SAT asks if ∃Xh for an h over variables X and determines a satisfying assignment in this case. In this context, the Boolean formula h is often given in Conjunctive Normal Form (CNF). A CNF is a set of clauses, each clause is a set of literals, and each literal is a Boolean variable or its negation. The CNF formula is satisfied if all clauses are satisfied, a clause is satisfied if at least one of its literals is satisfied, and a variable is satisfied when 1 is assigned to the variable (the negation of a variable is satisfied under the assignment 0). Example 2.12 Let h = (x1 + x2 + x 3 )(x 1 + x3 )(x 2 + x3 ). Then, x1 = 1, x2 = 1, and x3 = 1 is a satisfying assignment for h. The values of x1 and x2 ensure that the first clause becomes satisfied, while x3 ensures this for the remaining two clauses.
22
2 Preliminaries
Fig. 2.13 Solving algorithm in modern SAT solvers
To solve SAT problems, in the past several (backtracking) algorithms (or SAT solvers, respectively) have been proposed [DP60, DLL62, MS99, MMZ+01, GN02, ES04]. Most of them apply the steps depicted in Fig. 2.13: While there are free variables left (a), a decision is made (c) to assign a value to one of these variables. Then, implications are determined due to the last assignment (d). This may cause a conflict (e) that is analyzed. If the conflict can be resolved by undoing assignments from previous decisions, backtracking is done (f). Otherwise, the instance is unsatisfiable (g). If no further decision can be made, i.e. a value is assigned to all variables and this assignment did not cause a conflict, the CNF is satisfied (b). Advanced techniques like e.g. efficient Boolean constraint propagation [MMZ+01] or conflict analysis [MS99] as well as efficient decision heuristics [GN02] are common in state-of-the-art SAT solvers today. These techniques as well as the tremendous improvements in the performance of the respective implementations [ES04] enable the consideration of problems with more than hundreds of thousands of variables and clauses. Thus, SAT is widely used in many application domains. Therefore, the real world problem is transformed into CNF and then solved by using a SAT solver as a black box.
2.3.2 Extended SAT Solvers Despite their efficiency, Boolean SAT solvers have a major drawback: they work on the Boolean level. But, many problems are formulated on a higher level of abstraction and would benefit from a more general description, respectively. As a consequence, researchers investigated the use of more expressive formulations than CNF—by still exploiting the established SAT techniques. This leads (1) to the combination of SAT solvers with decision procedures for decidable theories resulting
2.3 Satisfiability Solvers
23
in SAT Modulo Theories (SMT) [BBC+05, DM06b] and (2) to the application of quantifiers resulting in Quantified Boolean Formulas (QBF) [Bie05, Ben05]. Furthermore, problem-specific knowledge is exploited during the solving process by the SAT solver SWORD [WFG+07]. The respective concepts are briefly reviewed in the following.
2.3.2.1 SMT Solvers for Bit-vector Logic An SMT solver integrates a Boolean SAT solver with other solvers for specialized theories (e.g. linear arithmetic or bit-vector logic). The SAT solver thereby works on an abstract representation (still in CNF) of the problem and steers the overall search process, while each (partial) assignment of this representation has to be validated by the theory solver for the theory constraints. Thus, advanced SAT techniques together with specialized theory solvers are exploited. In this book, the theory of quantifier free bit-vector logic (QF_BV) is utilized. This logic is defined as follows: Definition 2.13 A bit-vector is an element b = (bn−1 , . . . , b0 ) ∈ Bn . The index [ ] : Bn × [0, n) → B maps a bit-vector b and an index i to the ith component of the vector, i.e. b[i] = bi . Conversion from (to) a natural number is defined by i nat : Bn → N (bv : N → Bn ) with N = [0, 2n ) ⊂ N and nat(b) := n−1 i=0 bi · 2 −1 (bv := nat ). Problems can be constraint by using bit-vector operations as well as arithmetic operations. Let a, b ∈ Bn be two bit-vectors. Then, the bit-vector operation ◦ ∈ {∧, ∨, . . .} is defined by a ◦ b := (a[n − 1] ◦ b[n − 1], . . . , a[0] ◦ b[0]). An arithmetic operation • ∈ {·, +, . . .} is defined by a • b := nat(a) • nat(b). Example 2.13 Let a, b, and c be three bit-vector variables with bit-width n = 3 and (a ∨ b = c) ∧ (a + b = c) an SMT bit-vector instance over these variables. Then, a = (010), b = (001), and c = (011) is a satisfying solution of this instance, since it satisfies each constraint. To solve SMT instances in QF_BV logic either (1) a combination of a traditional SAT solver and a specialized (bit-vector) theory solver is applied (see e.g. [BBC+05, DM06a]), (2) the instance is pre-processed exploiting the higher level of abstraction before the resulting (simplified) instance is bit-blasted to a traditional SAT solver (see e.g. [GD07, BB09]), or (3) a specialized solver that directly works on the bitlevel of the problem is used (see e.g. [DBW+07]). Having an efficient solver available, similar to Boolean SAT the real world problem is transformed into a QF_BV instance. But instead of a description in terms of clauses, the higher level representation in terms of bit-vectors is used. Then, the resulting instance is passed to the solver which is again used as a black box. The higher abstraction which is now available can be exploited to accelerate the solving process.
24
2 Preliminaries
2.3.2.2 QBF Solvers Another generalization of the SAT problem is given by QBF satisfiability. Here, variables of the Boolean function h additionally can be universally and existentially quantified. More formally: Definition 2.14 Let h : Bn → B be a Boolean function over the variables X (usually given in CNF). Then, Q1 X1 . . . Qt Xt h with disjunct Xi ⊂ X and Qi ∈ {∃, ∀} is a Quantified Boolean Formula (QBF). The QBF problem is to find an assignment to the variables of h such that h evaluates to 1 with respect to the quantifiers or to prove that no such assignment exists. Example 2.14 Let ∃x2 , x3 ∀x1 (x1 + x2 + x 3 )(x 1 + x3 )(x 2 + x3 ). Then x2 = 1 and x3 = 1 is a satisfying assignment for the QBF h. The value of x2 ensures that the first clause becomes satisfied, while x3 ensures this for the remaining two clauses for all possible assignments to x1 . Obviously, solving QBF problems is significantly harder than solving pure SAT instances. In fact, it is PSPACE-complete [Pap93]. Nevertheless, QBF enables the formulation of many problems in a more compact way. In this sense, complexity is moved from the problem formulation to the solving engine, i.e. the task can be formulated in a more compact way resulting in a more complex problem to be solved by the solver. However, since usually solving engines are well-engineered with respect to the dedicated problem, this may lead to a faster solving process. Today, recent solvers (e.g. [Bie05, Ben05]) exploit techniques like symbolic skolemization to solve QBF instances (i.e. converting the instance to a normal form which enables simplifications).
2.3.2.3 SWORD Solver Due to the translation of the problem into CNF (or QF_BV logic, respectively), problem-specific knowledge is lost. More illustrative, decisions, implications, and learning schemes can only exploit the Boolean (bit-vector) description. In contrast, with more problem-specific knowledge available, more options exist how to control the search space traversion. This observation is exploited by the problem-specific SAT solver SWORD [WFG+07].2 SWORD represents the problem in terms of so called modules. Each module defines an operation over bit vectors of module variables. Each module variable is a Boolean variable. By this, structural and semantical knowledge is available which can be exploited by special algorithms for each kind of module. Furthermore, this 2 SWORD
has been co-developed by the authors of this book. Even if SWORD is focused on problem-specific knowledge, it can also be used as an SMT solver and already participated in the respective SMT competitions in 2008 [WSD08] and 2009 [JSWD09], respectively.
2.3 Satisfiability Solvers
25
Fig. 2.14 SWORD algorithm
leads to a more compact problem formulation, since representing complex operations in terms of modules substitutes a significant amount of clauses. Example 2.15 Consider an n × n-multiplier. This multiplier can be represented by n2 AND gates and n − 1 adders [MK04]. Furthermore, a single AND gate can be modeled by three clauses and requires θ (n2 ) auxiliary variables. Thus, just to encode the AND gates a CNF with θ (n2 ) auxiliary variables and clauses is required, respectively. In contrast, using SWORD only 3n module variables (for the two inputs and the output of the multiplication) and a single (multiplier) module are needed to represent the whole multiplication. Given a SAT instance including modules, the overall algorithm depicted in Fig. 2.14 is used to solve the problem. This algorithm is similar to the procedure as applied in standard SAT solvers (see Fig. 2.13 on p. 22): While free variables remain (a), a decision is made (c), implications resulting from this decision are carried out (d), and if a conflict occurs, it is analyzed (f). The important difference is that SWORD has two operation levels: The global algorithm controls the overall search process and calls local procedures of modules for decision and implication. Thus, decision making and the implication engine can be adjusted for each type of module. In more detail, the solver first chooses a particular module based on a global decision heuristic (c.1). Then, this module chooses a value for one of its variables according to a local decision heuristic (c.2). Afterwards, the solver calls the local implication procedures (d.2) of all modules that are potentially affected (d.1) by the previous decision or implication. Here, a variable watching scheme similar to the one presented in [MMZ+01] is used which can efficiently determine these modules. The chosen modules imply further assignments and detect conflicts.
26
2 Preliminaries
Due to the two operation levels, problem-specific strategies e.g. for decision making and propagation can be exploited by the modules. For example, decision making can be prioritized so that modules, which are assumed to be “more important” than others, are selected for a decision with a higher priority than less important modules. Furthermore, different modules can be equipped with different strategies. For a more detailed description of SWORD, the reader is referred to [WFG+07, WFG+09]. Therewith, all preliminaries required for this book have been introduced. Besides an introduction of reversible and quantum logic, also the applied core techniques have been briefly described. With that as a basis, the contributions towards a design flow for reversible logic are proposed in the following chapters. Decision diagrams are thereby applied for synthesis (Sect. 3.2), partially for exact synthesis (Sect. 4.3.2), and for verification (Sect. 7.1.2), while Boolean satisfiability is exploited in exact synthesis (especially in Sect. 4.2 and partially in Sect. 5.3 as well as Sect. 6.3), verification (Sect. 7.1.3), and debugging (Sect. 7.2). The extended SAT solvers (i.e. SMT solvers, QBF solvers, and SWORD) are used to improve exact synthesis (Sect. 4.3). Note on Benchmarks In the following chapters, the respective contributions are introduced and evaluated in detail. Different scopes are thereby considered that are also reflected in the benchmark sets used to experimentally evaluate the respective methods. Synthesis approaches are evaluated using large functions (for the proposed heuristic method), small functions (for exact synthesis), and irreversible functions (to evaluate the different embeddings). In contrast, the methods targeting optimization, verification, and debugging work on a given circuit description. Furthermore, different timeouts are applied in the respective evaluations (e.g. exact synthesis normally requires more run-time than heuristic synthesis). As already stated in the introduction, the benchmarks used in this book are publicly available at www.revlib.org. The resulting tools can be obtained under www.revkit.org.
Chapter 3
Synthesis of Reversible Logic
Synthesis is the most important step while building complex circuits. Considering the traditional design flow, synthesis is carried out in several individual steps such as high-level synthesis, logic synthesis, mapping, and routing (see e.g. [SSL+92]). To synthesize reversible logic, adjustments and extensions are needed. For example, further tasks such as embedding of irreversible functions must be added. Furthermore, throughout the whole flow, the restrictions caused by the reversibility (no fanout and feedback) and a completely new gate library must be considered as well. In the last years, first approaches addressing some of these issues have been introduced (see e.g. [SPMH03, MMD03, MD04b, Ker04, MDM05, GAJ06, HSY+06, MDM07]). The first section of this chapter briefly reviews existing methods for the individual steps. However, the research in this area is still at the beginning. So far, the desired behavior of the circuit to be synthesized is given by function descriptions like truth tables or permutations, respectively. As a result, current synthesis methods are applicable to relatively small functions only and often need a significant amount of run-time. This must be improved in order to design larger functions or complex reversible systems in the future. In this book, the wide area of reversible logic synthesis is covered by the following three chapters—each chapter with an own detailed view on a particular aspect. While Chap. 4 introduces exact (i.e. minimal) circuit synthesis, Chap. 5 discusses aspects of embedding in detail. The present chapter builds the basis for them and additionally proposes new methods that allows a fast synthesis of significantly larger functions and more complex circuits, respectively. Since Toffoli circuits as introduced in Sect. 2.1.2 generally build the basis for both, reversible and quantum circuits, in the following, the focus is on synthesis of Toffoli cascades. Nevertheless, quantum circuit synthesis is additionally considered when it is appropriate. As already mentioned, the first part of this chapter builds the basis for all remaining synthesis sections. Here, it is shown how irreversible functions must be embedded into reversible ones before they can be applied to existing synthesis methods. Then, by using the example of the transformation-based approach introduced in [MMD03], one of the previous synthesis methods is described and discussed. Altogether, this briefly summarizes the basic synthesis steps for reversible logic as they exist today. R. Wille, R. Drechsler, Towards a Design Flow for Reversible Logic, DOI 10.1007/978-90-481-9579-4_3, © Springer Science+Business Media B.V. 2010
27
28
3 Synthesis of Reversible Logic
Motivated by this (in particular by the limitations of the current synthesis methods), the second part of this chapter introduces a new synthesis approach [WD09, WD10] that exploits Binary Decision Diagrams (BDDs) [Bry86]. BDDs allow an efficient representation of large Boolean functions that can be mapped into reversible cascades. As a result, for the first time Toffoli circuits for functions containing over 100 variables can be derived efficiently. Finally, how to specify and synthesize more complex reversible circuits at higher abstractions is considered in the third part of this chapter. For this purpose, a new programming language (called SyReC) and a respective hierarchical synthesis approach is presented and evaluated [WOD10].
3.1 Current Synthesis Steps This section illustrates the current synthesis steps that use well-established methods. First, the problem of embedding irreversible functions is considered. Second, the synthesis itself is introduced. For the latter, a widely known approach, namely the transformation-based approach introduced in [MMD03], is used. Most of the remaining synthesis methods apply similar strategies (e.g. [Ker04, GAJ06, MDM07]) or are developed on top of this method (e.g. [MDM05]).
3.1.1 Embedding Irreversible Functions Table 3.1 shows the truth table of a 1-bit adder which is used as an example in this section. The adder has three inputs (the carry-in cin as well as the two summands x and y) and two outputs (the carry-out cout and the sum). The adder obviously is irreversible, since • the number of inputs differs from the number of outputs and • there is no unique input-output mapping. Even adding an additional output to the function (leading to the same number of inputs and outputs) would not make the function reversible. Then, without loss of generality, the first four lines of the truth table can be embedded with respect to reversibility as shown in the rightmost column of Table 3.1. However, since cout = 0 and sum = 1 already appeared two times (marked bold), no unique embedding for the fifth line is possible any longer. The same also holds for the lines marked italic. This has already been observed in [MD04b]. Here, the authors came to the conclusion that at least log2 (μ) additional (garbage) outputs are required to make an irreversible function reversible, where μ is the maximum number of times an output pattern is repeated in the truth table. Since for the adder at most three output patterns are repeated, log2 (3) = 2 additional outputs are required to make the function reversible.
3.1 Current Synthesis Steps Table 3.1 Truth table of an adder
Table 3.2 Truth table of an embedded adder
29 cin
x
y
cout
sum
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
0
1
?
1
0
1
1
0
1
1
1
0
1
0
?
1
1
1
1
1
1
0
cin
x
y
cout
sum
g1
g2
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
1
0
0
1
1
0
0
0
1
1
1
0
0
1
0
1
0
0
0
1
0
0
0
1
0
1
1
0
1
1
0
1
1
0
1
0
1
0
0
1
1
1
1
1
0
1
1
0
0
0
1
0
0
0
1
0
0
1
1
1
1
1
1
0
1
0
1
1
1
0
1
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
1
1
1
0
0
0
1
0
1
1
1
1
0
1
0
1
Adding new lines causes constant inputs and garbage outputs. The value of the constant inputs can be chosen by the designer. Garbage outputs are by definition don’t cares and thus can be left unspecified leading to an incompletely specified function. However, many synthesis approaches require a completely specified function so that often all don’t cares must be assigned to a concrete value. As a result, the adder is embedded in a reversible function including four variables, one constant input, and two garbage outputs. A possible assignment to the constant as well as the don’t care values is depicted in Table 3.2 (where the original adder function is marked bold). In the following, a synthesis method is introduced assuming a completely specified reversible function as input. However, the concrete embedding of irreversible functions (in particular the concrete assignment to don’t
30
3 Synthesis of Reversible Logic
Table 3.3 MDM procedure line
input
output
1st step
2nd step
3rd step
4th step
5th step
6th step
(i)
abcd
abcd
abcd
abcd
abcd
abcd
abcd
abcd
0
0000
0000
0000
0000
0000
0000
0000
0000
1
0001
0111
0101
0001
0001
0001
0001
0001
2
0010
0110
0110
0110
0010
0010
0010
0010
3
0011
1001
1011
1111
1011
0011
0011
0011
4
0100
0100
0100
0100
0100
0100
0100
0100
5
0101
1011
1001
1101
1101
1101
0101
0101
6
0110
1010
1010
1010
1110
1110
1110
0110
7
0111
1101
1111
1011
1111
0111
1111
0111
8
1000
1000
1000
1000
1000
1000
1000
1000
9
1001
1111
1101
1001
1001
1001
1001
1001
10
1010
1110
1110
1110
1010
1010
1010
1010
11
1011
0001
0011
0111
0011
1011
1011
1011
12
1100
1100
1100
1100
1100
1100
1100
1100
13
1101
0011
0001
0101
0101
0101
1101
1101
14
1110
0010
0010
0010
0110
0110
0110
1110
15
1111
0101
0111
0011
0111
1111
0111
1111
cares) can have a significant impact on the synthesis results (i.e. on the number of gates in the resulting circuit). Thus, this issue is again considered in Chap. 5 which also provides examples showing the effect of different embeddings.
3.1.2 Transformation-based Synthesis In this section, synthesis of reversible logic is exemplarily described using the approach from [MMD03]. The basic idea is to traverse each line of the truth table and to add gates to the circuit until the output values match the input values (i.e. until the identity is achieved). Gates are thereby chosen so that they don’t alter already considered lines. Furthermore, gates are added starting at the output side of the circuit (this is because output values are transformed until the identity is achieved). In the following, the approach is described using the example of the embedded adder from Table 3.2. Table 3.3 shows the respective steps. The first column denotes the truth table line numbers, while the second and third column give the function specification of the adder. For brevity, the inputs 0, cin , x, y and the outputs cout , sum, g1 , g2 are denoted by a, b, c, d, respectively. The remaining columns provide the transformed output values for the respective steps. The approach starts at truth table line 0. Since for this line the input is already equal to the output (both are assigned to 0000), no gate has to be added. In contrast, to match the output with the input in line 1, the values for c and b must be
3.2 BDD-based Synthesis
31
Fig. 3.1 Circuit obtained by transformation-based synthesis
inverted. To this end, two gates MCT({d}, c) (1st step) and MCT({d}, b) (2nd step) are added as depicted in Fig. 3.1. Due to the control line d, this does not affect the previous truth table line. In line 2 and line 3, an MCT({c}, b) as well as an MCT({c, d}, a) is added to match the values of b and a, respectively (step 3 and 4). For the latter gate, two control lines are needed to keep the already traversed truth table lines unaltered. Afterwards, only two more gates MCT({d, b}, a) (5th step) and MCT({c, b}, a) (6th step) are necessary to achieve the input-output identity. The resulting circuit is shown in Fig. 3.1. This circuit consists of six gates and has quantum cost of 18. In [MMD03], further variations of this approach are discussed. In fact, this transformation can also be applied in the inverse direction (i.e. so that the input must match the output) and in both directions simultaneously. Furthermore, in [MDM05] the approach has been extended by the application of templates. These help to reduce the size of the resulting circuits and thus to achieve circuits with lower cost. Having this as a general introduction into synthesis of reversible logic, in the following new synthesis approaches are proposed.
3.2 BDD-based Synthesis The strategy introduced in the last section (namely selecting reversible gates so that the chosen function representation becomes the identity) has been adopted and extended by many other researchers. More precisely, more compact data-structures like decision diagrams [Ker04], positive-polarity Reed-Muller expansion [GAJ06], or Reed-Muller spectra [MDM07] have been applied. But even if complementary approaches are used (e.g. [SPMH03]), so far all approaches are applicable only to relatively small functions, i.e. functions with at most 30 variables [GAJ06]. Moreover, often a significant amount of run-time is needed to achieve these results. Thus, current synthesis methods are limited. These limitations are caused by the underlying techniques. The existing synthesis approaches often rely on truth tables (or similar descriptions like permutations) of the function to be synthesized (e.g. in [SPMH03, MMD03]). But even if alternative data-structures (e.g. the ones mentioned above) are used, the same limitations can be observed. In this section, a synthesis method that can cope with significantly larger functions is introduced. The basic idea is as follows: First, for the function to be synthesized a BDD (see Sect. 2.2.1) is built. This can be efficiently done for large functions using existing well-developed techniques. Then, each node of the BDD is substituted by a cascade of reversible gates. Since BDDs may include shared nodes
32
3 Synthesis of Reversible Logic
causing fanouts (which are not allowed in reversible logic), this may require additional circuit lines. As a result, circuits composed of Toffoli or quantum gates, respectively, are obtained in time and with memory linear to the size of the BDD. Moreover, since the size of the resulting circuit is bounded by the BDD size, theoretical results known from BDDs (see e.g. [Weg00, LL92]), can be transferred to reversible circuits. The experiments show significant improvements (with respect to the resulting circuit cost as well as to the run-time) in comparison to previous approaches. Furthermore, for the first time large functions with more than hundred variables can be synthesized at very low run-time. In the remainder of this section, the BDD-based synthesis approach is introduced as follows: In Sect. 3.2.1, the general idea and the resulting synthesis approach is described in detail. How to exploit BDD optimizations is shown in Sect. 3.2.2, while Sect. 3.2.3 briefly reviews some of the already known theoretical results from reversible logic synthesis and introduces bounds which follow from the new synthesis approach. Finally, in Sect. 3.2.4 experimental results are given.
3.2.1 General Idea In this section, the general idea of the BDD-based synthesis is proposed. The aim of the approach is to determine a circuit realization for a given Boolean function. It is well known that Boolean functions can be efficiently represented by BDDs. Given a BDD G = (V , E), a reversible circuit can be derived by traversing the decision diagram and substituting each node v ∈ V with a cascade of reversible gates. The concrete cascade of gates depends on whether the successors of the node v are terminals or not. For the general case (no terminals), the first row of Table 3.4 shows a substitution with two Toffoli gates or five quantum gates, respectively. The following rows give the substitutions for the remaining cases. These cascades can be applied to derive a complete Toffoli circuit (or quantum circuit, respectively) from a BDD without shared nodes. Example 3.1 Consider the BDD in Fig. 3.2(a). Applying the substitutions given in Table 3.4 to each node of the BDD, the Toffoli circuit depicted in Fig. 3.2(b) results. Remark 3.1 As shown in Table 3.4, an additional (constant) line is necessary if one of the edges low(v) or high(v) leads to a terminal node. This is because of the reversibility which has to be ensured when synthesizing reversible logic. As an example consider a node v with high(v) = 0 (second row of Table 3.4). Without loss of generality, the first three lines of the corresponding truth table can be embedded with respect to reversibility as depicted in Table 3.5(a). However, since f is 0 in the last line, no reversible embedding for the whole function is possible. Thus, an additional line is required to make the respective substitution reversible (see Table 3.5(b)).1 1 For the same reason, it is also not possible to preserve the values for low(v) or high(v), respectively, in the substitution depicted in the first row of Table 3.4.
3.2 BDD-based Synthesis
Table 3.4 Substitution of BDD nodes to reversible/quantum circuits
33
34
3 Synthesis of Reversible Logic
Fig. 3.2 BDD and Toffoli circuit for f = x1 ⊕ x2
Table 3.5 (Partial) Truth tables for node v with high(v) = 0
(b) with additional line
(a) w/o add. line xi
low(f )
f
–
0 xi low(f )
f xi low(f )
0
0
0
0
0 0 0
0 0 0
0
1
1
1
0 0 1
1 0 1
1
0
0
1
0 1 0
0 1 0
1
1
0
?
0 1 1
0 1 1
Based on these substitutions, a method for synthesizing Boolean functions in reversible or quantum logic can be formulated: First, a BDD for function f to be synthesized is created. This can be done efficiently using state-of-the-art BDD packages (e.g. CUDD [Som01]). Next, the resulting BDD G = (V , E) is processed by a depth-first traversal. For each node v ∈ V , cascades as depicted in Table 3.4 are added to the circuit. As a result, circuits are synthesized that realize the given function f .
3.2.2 Exploiting BDD Optimization To build compact BDDs, current state-of-the-art BDD packages exploit several optimization techniques such as shared nodes [Bry86], complement edges [BRB90], or reordering [Bry86, Rud93]. In this section, it is shown how these techniques can be applied to the proposed BDD-based synthesis.
3.2.2.1 Shared Nodes If a node v has more than one predecessor, then v is called a shared node. The application of shared nodes is common for nearly all BDD packages. Shared nodes can be used to represent a sub-formula more than once without the need to rebuild the whole sub-graph. In particular, functions f : Bn → Bm (i.e. functions with more than one output) can be represented more compactly using shared nodes.
3.2 BDD-based Synthesis
35
Fig. 3.3 Substitution for shared nodes without terminals as successors
However, to apply shared nodes in reversible logic synthesis, the output value of a respective node has to be preserved until it is not needed any longer. Considering the substitutions depicted in Table 3.4, this holds for all cases where one of the edges low(v) or high(v) lead to a terminal node. Here, all values of the inputs (in particular of high(v) or low(v) that represent output values of other nodes) are preserved. In contrast, this is not the case for the general case (first row of Table 3.4). Here, only one value (namely the value from the select variable xi ) is preserved. Thus, a modified substitution for shared nodes without terminals as successors is required. Figures 3.3(a) and 3.3(b) show one possible substitution to a reversible cascade and a quantum cascade, respectively. Besides an additional constant circuit line, this requires one (three) additional reversible gates (quantum gates) in comparison to the substitution of Table 3.4. But therefore, shared nodes are supported. Moreover, this substitution also allows to represent the identity of a select variable (last row of Table 3.4) by the respective input line of the circuit (i.e. without any additional gates or lines). Previously, this was not possible, since the value of this circuit line was not necessarily preserved (as an example see Fig. 3.2 where the value of the identity node f gets lost after node f is substituted). Exploiting this, the synthesis algorithm proposed in the last section can be improved as follows: Again a BDD for the function to be synthesized is build which is afterwards traversed in a depth-first manner. Then, for each node v ∈ V , the following checks are performed: 1. Node v represents the identity of a primary input (i.e. the select input) In this case no cascade of gates is added to the circuit, since the identity can be represented by the same circuit line as the input itself. 2. Node v contains at least one edge (low(v) or high(v), respectively) leading to a terminal In this case substitutions as depicted in Table 3.4 are applied, since they often need a smaller number of gates and additionally preserve the values of all input signals. 3. The values of low(v) and high(v) are still needed, since they represent either shared nodes or the identity of an input variable In this case the substitutions depicted in Fig. 3.3 are applied, since they preserve the values of all input signals. 4. Otherwise The substitution as depicted in the first row of Table 3.4 is applied, since no input values must be preserved or a terminal successor occurs, respectively. In
36
3 Synthesis of Reversible Logic
Fig. 3.4 Toffoli circuits for shared BDD
this case, the smaller cascades (with respect to both the number of additional lines and the number of gates) are preferred. Example 3.2 In Fig. 3.4(a) a partial BDD including a shared node f is shown. Since the value of node f is used twice (by nodes f1 and f2 ), an additional line (the second one in Fig. 3.4(b)) and the cascade of gates as depicted in Fig. 3.3 are applied to substitute node f1 . Then, the value of f is still available such that the substitution of node f2 can be applied. The resulting circuit is given in Fig. 3.4(b). Figure 3.4(c) shows the resulting circuit for low(f ) = 0 and high(f ) = 1, i.e. for f representing the identity of xj . In this case no gates for f are added. Instead, the fifth line is used to store the value for both, xj and f . Besides that, the remaining substitutions are equal to the ones described above.
3.2.2.2 Complement Edges Further reductions in BDD sizes can be achieved if complement edges [BRB90] are applied. In particular, this allows to represent a function as well as its negation by a single node only. If there is a complement edge e.g. between v and low(v), then Shannon decomposition with an inverted value of low(v) is applied. To support
3.2 BDD-based Synthesis
37
complement edges in the proposed synthesis approach, adjusted substitutions have to be used that take the inversion of complemented edges into account. Table 3.6 shows the resulting cascades used in the proposed synthesis approach. Note that complements have to be considered only at the low edges of the nodes, since complements at high-edges can be mapped to them and vice versa. In some cases, this leads to larger cascades in comparison to the substitution without complement edges (e.g. compare the second row of Table 3.6 to the first row of Table 3.4). How far this can be compensated by the possible BDD reductions is discussed in the experimental evaluation in Sect. 3.2.4.
3.2.2.3 Reordering of BDDs Finally, different BDD orders may influence the synthesis results. It has been shown that the order of the variables has a high impact to the size of the resulting BDD [Bry86] (see e.g. Fig. 2.11 on p. 19). Since reducing the number of nodes may also reduce the size of the resulting circuits, reordering is considered in this section. In the past, several approaches have been proposed to achieve good orders (e.g. sifting [Rud93]) or to determine exact results (e.g. [DDG00]) with respect to the number of nodes. All these techniques can be directly applied to the BDD-based synthesis approach and need no further adjustments of the already introduced substitutions. Using these optimization techniques (i.e. shared nodes, complement edges, and reordering), in Sect. 3.2.4 it is considered how they influence the resulting Toffoli or quantum circuits, respectively. But before, it is briefly shown how the proposed approach can be used to transfer theoretical results from BDDs to reversible logic.
3.2.3 Theoretical Consideration In the past, first lower and upper bounds for the synthesis of reversible functions containing n variables have been determined. In [MD04b], it has been shown that there exists a reversible function that requires at least (2n / ln 3) + o(2n ) gates (lower bound). Furthermore, the authors proved that every reversible function can be realized with no more than n · 2n gates (upper bound). For a restricted gate library leading to smaller quantum cost and thus only consisting of NOT, CNOT, and two-controlled Toffoli gates (the same as applied for the substitutions proposed here), functions can be synthesized with at most n NOT gates, n2 CNOT gates, and 9 · n · 2n + o(n · 2n ) two-controlled Toffoli gates (according to [SPMH03]). A tighter upper bound of n NOT gates, 2 · n2 + o(n · 2n ) CNOT gates, and 3 · n · 2n + o(n · 2n ) two-controlled Toffoli gates has been proved in [MDM07]. In [PMH08] it has been shown that linear reversible functions are synthesizable with CNOT gates only. Moreover, their algorithm never needs more than Θ(n2 / log n) CNOT gates for any linear function f with n variables.
Table 3.6 Subst. of BDD nodes with complement edge to reversible/quantum circuits
38 3 Synthesis of Reversible Logic
3.2 BDD-based Synthesis
39
Using the synthesis approach proposed in the last sections, reversible circuits for a function f with a size dependent on the number of nodes in the BDD can be constructed. More precisely, let f be a function with n primary inputs which is represented by a BDD containing k nodes.2 Then, the resulting Toffoli circuit consists of at most • k + n circuit lines (since besides the input lines, for each node at most one additional line is added) and • 3 · k gates (since for each node cascades of at most 3 gates are added according to the substitutions of Table 3.4 and Fig. 3.3, respectively). Asymptotically, the resulting reversible circuits are bounded by the BDD size. Since for BDDs many theoretical results exist, using the proposed synthesis approach, these results can be transferred to reversible logic as well. In the following, some results obtained by this observation are sketched. • A BDD representing a single-output function has 2n nodes in the worst case. Thus, each function can be realized in reversible logic with at most 3 · 2n gates (where at most 2 · 2n CNOTs and 2 · 2n Toffoli gates are needed). nodes in the worst case. • A BDD representing a symmetric function has n·(n+1) 2 Thus, each symmetric function can be realized in reversible logic with a quadratic number of gates (more precisely, a quadratic number of CNOTs and a quadratic number of Toffoli gates are needed). • A BDD representing specific functions, like AND, OR, or XOR has a linear size. Thus, there exists a reversible circuit realizing these functions in linear size as well. • A BDD representing an n-bit adder has linear size. Thus, there exists a reversible circuit realizing addition in linear size as well. Further results (e.g. tighter upper bounds for general functions as well as for respective function classes) are also known (see e.g. [Weg00, LL92]). Moreover, in a similar way bounds for quantum circuits can be obtained. However, a detailed analysis of the theoretical results that can be obtained by the BDD-based synthesis is left for future work.
3.2.4 Experimental Results The BDD-based synthesis method together with the suggested improvements has been implemented in C++ on top of the BDD package CUDD [Som01]. In this section, first a case study is given evaluating the effect of the respective BDD optimization techniques on the resulting reversible or quantum circuits. Afterwards, the proposed approach is compared against two previously proposed synthesis methods. 2 For
simplicity, it is assumed that no complement edges are applied.
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3 Synthesis of Reversible Logic
Benchmarks functions provided by RevLib [WGT+08] (including most of the functions which have been previously used to evaluate existing reversible synthesis approaches) as well as from the LGSynth package [Yan91] (a benchmark suite for evaluating traditional synthesis) have been used. All experiments have been carried out on an AMD Athlon 3500+ with 1 GB of memory. The timeout was set to 500 CPU seconds.
3.2.4.1 Effect of BDD Optimization To investigate the effect of the respective BDD optimization techniques the proposed synthesis approach has been applied to the benchmarks with the respective techniques enabled or disabled. In the following, for each optimization technique (i.e. shared nodes, complement edges, and reordering) the respective results are presented and discussed. Shared Nodes Shared nodes can be enabled or disabled by manipulating the unique table. Then, depending on the respective case, the substitutions of Table 3.4 or additionally of Fig. 3.3 are applied. The results are summarized in Table 3.7. The first two columns give the name of the benchmark (F UNCTION) as well as the number of primary inputs and outputs (PI/PO). Then, the number of resulting circuit lines (n), Toffoli gates (dTof ), or quantum gates (dQua ), as well as the run-time of the synthesis approach (in CPU seconds) is given for the naive approach (denoted by W / O S HARED N ODES) and the approach that exploits shared nodes (denoted by WITH S HARED N ODES). One can clearly conclude that the application of shared nodes leads to better realizations for reversible and quantum logic. Both, the number of lines and the number of gates can be significantly reduced. In particular, for the number of lines this might not be obvious, since additional lines are required to support shared nodes (see Sect. 3.2.2). But due to the fact that shared nodes also decrease the number of terminal nodes (which require additional lines as well), this effect is compensated. Complement Edges Complement edges are supported by the CUDD package and can easily be disabled and enabled. For comparison, circuits from both, BDDs with and BDDs without complement edges (denoted by WITH C OMPL . E DGES and W / O C OMPL . E DGES, respectively), are synthesized. In the latter case, the substitutions shown in Table 3.6 are applied whenever a successor is connected by a complement edge. Shared nodes are also applied, since they make complement edges more beneficial. The results are given in Table 3.8.3 The columns are labeled as described above for Table 3.7. Even if the cascades representing nodes with complement edges are larger in some cases (see Sect. 3.2.2), improvements in the circuit sizes can be observed (see 3 Compared to Table 3.7, also benchmarks are considered for which no result could be determined using the W / O S HARED N ODES approach.
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Table 3.7 Effect of shared nodes F UNCTION
PI/PO
W/O
n
S HARED N ODES dTof
dQua
WITH
T IME
n
S HARED N ODES T IME
dTof
dQua
7
7
21
