# 29.4: Procedure

- Page ID
- 37348

## 29.4.1: Common Source Voltage Amplifier

1. Consider the circuit of Figure 29.3.1 using Vdd = 15 volts, Vss = −3 volts, Rin = 33 k\(\Omega\), Rg = 330 k\(\Omega\), Rs = 4.7 k\(\Omega\), Rd = 4.7 k\(\Omega\), Rload = 22 k\(\Omega\), Cin = Cout = 10 \(\mu\)F and Cs = 470 \(\mu\)F. Assuming \(V_{GS}\) = −2 volts and \(g_m\) = 2 mS (4 mS if using the J112), determine the theoretical gain and input impedance of the circuit and record these in Table 29.5.1.

2. Build the circuit of Figure 29.3.1 using Vdd = 15 volts, Vss = −3 volts, Rin = 33 k\(\Omega\), Rg = 330 k\(\Omega\), Rs=4.7 k\(\Omega\), Rd = 4.7 k\(\Omega\), Rload = 22 k\(\Omega\), Cin = Cout = 10 \(\mu\)F and Cs = 470 \(\mu\)F. Set Vin to a 100 mV peak sine at 1 kHz. Measure the voltages at the gate and load, and record these in Table 29.5.1. Capture images of the input and gate voltages, and the gate and load voltages. Note whether or not the load is inverted compared to the gate signal.

3. Based on the measured gate and drain voltages, determine the resulting theoretical \(A_v\) and \(Z_{in}\), and record these in Table 29.5.1. Note that \(Z_{in}\) may be computed using the voltage divider rule or Ohm's law given the gate and input voltages along with the input resistor value. Also determine and record the percent deviations.

4. Repeat steps 1 through 3 for the remaining two JFETs.

## 29.4.2: Common Drain Voltage Follower

5. Consider the circuit of Figure 29.3.2 using Vdd = 15 volts, Vss = −3 volts, Rin = 33 k\(\Omega\), Rg = 330 k\(\Omega\), Rs = 4.7 k\(\Omega\), Rload = 22 k\(\Omega\), Cin = 10 \(\mu\)F and Cout = 470 \(\mu\)F. Assuming \(V_{GS}\) = −2 volts and \(g_m\) = 2 mS (4 mS if using the J112), determine the theoretical gain and input impedance of the circuit and record in Table 29.5.2.

6. Build the circuit of Figure 29.3.2 using Vdd = 15 volts, Vss = −3 volts, Rin = 33 k\(\Omega\), Rg = 330 k\(\Omega\), Rs=4.7 k\(\Omega\), Rload = 22 k\(\Omega\), Cin = 10 \(\mu\)F and Cout = 470 \(\mu\)F. Set Vin to a 100 mV peak sine at 1 kHz. Measure the voltages at the gate and load, and record these in Table 29.5.2. Capture images of the input and gate voltages, and the gate and load voltages. Note whether or not the load is inverted compared to the gate signal.

7. Based on the measured gate and drain voltages, determine the resulting theoretical \(A_v\) and \(Z_{in}\), and record these in Table 29.5.2. Also determine and record the percent deviations.

8. Repeat steps 5 through 7 for the remaining two JFETs.

## 29.4.3: Troubleshooting

9. Consider each of the individual faults listed in Table 29.5.3 and estimate the resulting AC load voltage for circuit 1. Introduce each of the individual faults in turn and measure and record the load voltage in Table 29.5.3.