Synthesis of Computational Structures for Analog Signal Processing

Synthesis of Computational Structures for Analog Signal Processing Cosmin Radu Popa Synthesis of Computational Struc...

Author: Cosmin Radu Popa

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Synthesis of Computational Structures for Analog Signal Processing

Cosmin Radu Popa

Synthesis of Computational Structures for Analog Signal Processing

Cosmin Radu Popa Faculty of Electronics, Telecommunications and Information Technology University Politehnica of Bucharest Bucharest, Romania [email protected]

ISBN 978-1-4614-0402-6 e-ISBN 978-1-4614-0403-3 DOI 10.1007/978-1-4614-0403-3 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2011934510 # Springer Science+Business Media, LLC 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights.

Printed on acid-free paper Springer is part of Springer ScienceþBusiness Media (www.springer.com)

This book is dedicated to my beloved daughter Ilinca Maria.

Preface

Signal processing represents an important domain of electronics, in the last years many efforts being directed for improving the performances of these structures. The approach of the signal processing from an analog perspective presents the advantage of allowing an important reduction of the circuits’ power consumption. The compact implemented structures are compatible with ultimate low-power designs and find a lot of applications such as portable equipments, wireless nanosensors or medical implantable devices. Even the power consumption is continuous for analog circuits comparing with digital structures that consume only in the switching intervals, the possibility of an important reduction of designs’ complexities and of the number of their constitutive active devices strongly decrease the medium power consumption per unity of time for analog designs. Moreover, lowpower analog signal processing circuits are often implemented using subthresholdoperated MOS transistors, having extremely low values of drain currents, this fact producing an additionally lowering of the total power requested by the analog computational structures. The original approach of designing analog signal processing circuits using multifunctional structures also contributes to the decreasing of power consumption per implemented function. Another important advantage of analog signal processing is that the speed of circuits is usually greater than the speed of digital computational circuits, allowing a real time signal processing. Two important classes of analog signal processing circuits can be identified. The first class corresponds to linear structures, such as differential amplifier structures, multiplier circuits or active resistor structures, being necessary to develop particular linearization techniques in order to improve their general performances. The second class of analog signal processing circuits covers the area of nonlinear structures: squaring or square-rooting circuits, exponential structures or vector summation and Euclidean distance circuits. In this case, the most important goal is to minimize the approximation error of the implemented function. In order to improve the circuits’ frequency response, a part of analog signal processing circuits are implemented

vii

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Preface

using exclusively MOS transistors biased in saturation region. In cases in which the low-power operation is crucial, the subthreshold operation of MOS active devices represents the single choice for the designer. In order to obtain an important reduction of design costs and of power consumption for the designed circuits, multifunctional computational structures can be implemented. Their principle of operation is based on the possibility of a multiple use of the same functional cell that is named multifunctional circuit core. As the design effort is mostly focused on the improving of the core performances and because the most important silicon area is consumed by the multifunctional core, the reutilization of this part of the multifunctional structure for all circuit functions will strongly decrease the complexity and power consumption per implemented function. The multifunctional structures present the important advantage of a relatively simple reconfiguration, small changing of the design allowing to obtain all necessary linear or nonlinear circuit functions. The first chapter is dedicated to the presentation of linearization techniques for improving the performances of CMOS differential structures, fundamental circuits in VLSI analog and mixed-signal designs. The mathematical fundamentals are structured in eight different elementary mathematical principles, each of them being illustrated by concrete implementations in CMOS technology of their functional relations. As it exists a relative limited number of mathematical principles that are used for implementing the multiplier circuits, the first part of Chap. 2 is dedicated to the analysis of the mathematical relations that represent the functional core of the designed circuits. In the second part of the chapter, starting from these elementary principles, there are analyzed and designed concrete multiplier circuits, grouped according to their constitutive mathematical principles. Both current and voltage multiplier circuits are presented, their operation being extensively described in Chap. 2. The squaring function can be relatively easily obtained considering the intrinsic squaring characteristic of the MOS transistor biased in saturation region. Referring to the input variable, the squaring circuits can be clustered in two important classes: voltage squarers and current squarers, for both of them, the output variable being, usually, a current. The first part of Chap. 3 is dedicated to the analysis of the mathematical relations that represent the functional core of the designed circuits, while, in the second part of the chapter, starting from these elementary principles, there are analyzed and designed concrete squaring circuits, clustered according to their constitutive mathematical principles. An important class of VLSI computational structures is represented by the square-root circuits. Frequently implemented using a translinear loop, they exploit the squaring characteristic of MOS transistors biased in saturation region. The presented design techniques are based on five different elementary mathematical principles, each of them being illustrated in Chap. 4 by concrete implementations in CMOS technology. Exponential circuits represent important building blocks with many applications in VLSI designs. In CMOS technology, the exponential law is available only for

Preface

ix

the weak inversion operation of MOS transistor, the circuits designed using subthreshold-operated MOS active devices having the disadvantage of a poor frequency response. Thus, circuits realized in CMOS technology that require a good frequency response can be designed using exclusively MOS transistors biased in saturation region. The first part of Chap. 5 is dedicated to the analysis of the mathematical relations that represent the functional core of the designed circuits. In the second part of the chapter, using these elementary principles, there are analyzed and designed concrete exponential circuits, grouped according to the mathematical principles they are based on. Chap. 6 is dedicated to the analysis and design of Euclidean distance circuits, classified (depending on their input variable), in computational structures having current-input or voltage-input vectors. Functionally equivalent with a classical resistor, but presenting many important advantages in comparison with them, active resistor structures are extensively analyzed in Chap. 7. The goal of designing this class of active structures is mainly related to the possibility of an important reduction of the silicon area, especially for large values of the simulated resistances. The techniques presented for designing active resistor structures are based on six different elementary mathematical principles, each of them being illustrated by concrete implementations in CMOS technology. A multitude of fundamental linear or nonlinear analog signal processing blocks can be realized starting from the same core, the optimization techniques implemented for the core being efficient for all derived circuits. The structures that can be realized starting from an improved performance multifunctional core are: differential amplifiers, multiplier circuits, active resistors (having both positive and negative controllable equivalent resistance), squaring, square-rooting or exponential circuits. Additionally, developing proper approximation functions, multifunctional structures are able to generate any continuous mathematical function. The circuits shown in Chap. 8 are based on four different elementary mathematical principles, being also presented concrete implementations in CMOS technology of these complex computational structures. Bucharest, Romania

Cosmin Radu Popa

Contents

1

Differential Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Mathematical Analysis for Synthesis of Differential Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 First Mathematical Principle (PR 1.1) . . . . . . . . . . . . . . . . . . . . . . 1.1.2 Second Mathematical Principle (PR 1.2) . . . . . . . . . . . . . . . . . . . 1.1.3 Third Mathematical Principle (PR 1.3) . . . . . . . . . . . . . . . . . . . . . 1.1.4 Fourth Mathematical Principle (PR 1.4). . . . . . . . . . . . . . . . . . . . 1.1.5 Fifth Mathematical Principle (PR 1.5). . . . . . . . . . . . . . . . . . . . . . 1.1.6 Sixth Mathematical Principle (PR 1.6) . . . . . . . . . . . . . . . . . . . . . 1.1.7 Seventh Mathematical Principle (PR 1.7) . . . . . . . . . . . . . . . . . . 1.1.8 Different Mathematical Principle for Differential Amplifiers (PR 1.D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Analysis and Design of Differential Structures . . . . . . . . . . . . . . . . . . . . 1.2.1 Differential Structures Based on the First Mathematical Principle (PR 1.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 Differential Structures Based on the Second Mathematical Principle (PR 1.2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 Differential Structures Based on the Third Mathematical Principle (PR 1.3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4 Differential Structures Based on the Fourth Mathematical Principle (PR 1.4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.5 Differential Structures Based on the Fifth Mathematical Principle (PR 1.5) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.6 Differential Structures Based on the Sixth Mathematical Principle (PR 1.6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.7 Differential Structures Based on the Seventh Mathematical Principle (PR 1.7) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.8 Differential Structures Based on Different Mathematical Principle (PR 1.D) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1 1 2 2 2 3 3 3 3 4 8 23 34 59 61 62 69 80 85 85 xi

xii

Contents

Voltage and Current Multiplier Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Mathematical Analysis for Synthesis of Multipliers . . . . . . . . . . . . . . 2.1.1 Mathematical Analysis of Voltage Multiplier Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Mathematical Analysis of Current Multiplier Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Analysis and Design of Multiplier Circuits . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Design of Voltage Multiplier Circuits . . . . . . . . . . . . . . . . . . . . . 2.2.2 Design of Current Multiplier Circuits . . . . . . . . . . . . . . . . . . . . . 2.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

92 93 93 164 181 182

3

Squaring Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Mathematical Analysis for Synthesis of Squaring Circuits . . . . . . . 3.1.1 Mathematical Analysis of Voltage Squaring Circuits . . . . . 3.1.2 Mathematical Analysis of Current Squaring Circuits . . . . . 3.2 Analysis and Design of Squaring Circuits. . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Design of Voltage Squaring Circuits . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Design of Current Squaring Circuits . . . . . . . . . . . . . . . . . . . . . . 3.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

185 185 185 186 188 188 224 246 246

4

Square-Root Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Mathematical Analysis for Synthesis of Square-Root Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 First Mathematical Principle (PR 4.1) . . . . . . . . . . . . . . . . . . . . . 4.1.2 Second Mathematical Principle (PR 4.2) . . . . . . . . . . . . . . . . . . 4.1.3 Third Mathematical Principle (PR 4.3) . . . . . . . . . . . . . . . . . . . . 4.1.4 Fourth Mathematical Principle (PR 4.4). . . . . . . . . . . . . . . . . . . 4.1.5 Different Mathematical Principle (PR 4.D) . . . . . . . . . . . . . . . 4.2 Analysis and Design of Square-Root Circuits . . . . . . . . . . . . . . . . . . . . . 4.2.1 Square-Root Circuits Based on the First Mathematical Principle (PR 4.1) . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Square-Root Circuits Based on the Second Mathematical Principle (PR 4.2) . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 Square-Root Circuits Based on the Third Mathematical Principle (PR 4.3) . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 Square-Root Circuits Based on the Fourth Mathematical Principle (PR 4.4) . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.5 Square-Root Circuits Based on Different Mathematical Principles (PR 4.D) . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

249

2

89 89 90

249 249 249 250 250 250 250 250 252 257 260 262 264 264

Contents

5

6

Exponential Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Mathematical Analysis for Synthesis of Exponential Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 First Mathematical Principle (PR 5.1) . . . . . . . . . . . . . . . . . . . . . 5.1.2 Second Mathematical Principle (PR 5.2) . . . . . . . . . . . . . . . . . . 5.1.3 Third Mathematical Principle (PR 5.3) . . . . . . . . . . . . . . . . . . . . 5.1.4 Fourth Mathematical Principle (PR 5.4). . . . . . . . . . . . . . . . . . . 5.1.5 Fifth Mathematical Principle (PR 5.5). . . . . . . . . . . . . . . . . . . . . 5.1.6 Sixth Mathematical Principle (PR 5.6) . . . . . . . . . . . . . . . . . . . . 5.1.7 Seventh Mathematical Principle (PR 5.7) . . . . . . . . . . . . . . . . . 5.1.8 Eighth Mathematical Principle (PR 5.8). . . . . . . . . . . . . . . . . . . 5.1.9 Ninth Mathematical Principle (PR 5.9). . . . . . . . . . . . . . . . . . . . 5.2 Analysis and Design of Exponential Circuits . . . . . . . . . . . . . . . . . . . . . 5.2.1 Exponential Circuits Based on the First Mathematical Principle (PR 5.1) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Exponential Circuits Based on the Second Mathematical Principle (PR 5.2) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Exponential Circuits Based on the Third Mathematical Principle (PR 5.3) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.4 Exponential Circuits Based on the Fourth Mathematical Principle (PR 5.4) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.5 Exponential Circuits Based on the Fifth Mathematical Principle (PR 5.5) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.6 Exponential Circuits Based on the Sixth Mathematical Principle (PR 5.6) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.7 Exponential Circuits Based on the Seventh Mathematical Principle (PR 5.7) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.8 Exponential Circuits Based on the Eighth Mathematical Principle (PR 5.8) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.9 Exponential Circuits Based on the Ninth Mathematical Principle (PR 5.9) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Euclidean Distance Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Mathematical Analysis for Synthesis of Euclidean Distance Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Euclidean Distance of Voltage Input Vectors . . . . . . . . . . . . . 6.1.2 Euclidean Distance of Current Input Vectors . . . . . . . . . . . . . 6.2 Analysis and Design of Euclidean Distance Circuits. . . . . . . . . . . . . . 6.2.1 Euclidean Distance Circuits for Voltage Input Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Euclidean Distance Circuits for Current Input Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xiii

267 267 267 268 269 270 271 273 274 277 278 280 280 295 297 299 300 301 302 303 304 306 306 309 309 309 310 311 311 312 322 322

xiv

7

8

Contents

Active Resistor Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Mathematical Analysis for Synthesis of Active Resistor Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 First Mathematical Principle (PR 7.1) . . . . . . . . . . . . . . . . . . . . . 7.1.2 Second Mathematical Principle (PR 7.2) . . . . . . . . . . . . . . . . . . 7.1.3 Third Mathematical Principle (PR 7.3) . . . . . . . . . . . . . . . . . . . . 7.1.4 Fourth Mathematical Principle (PR 7.4). . . . . . . . . . . . . . . . . . . 7.1.5 Fifth Mathematical Principle (PR 7.5). . . . . . . . . . . . . . . . . . . . . 7.1.6 Different Mathematical Principles (PR 7.D) . . . . . . . . . . . . . . 7.2 Analysis and Design of Active Resistor Circuits. . . . . . . . . . . . . . . . . . 7.2.1 Active Resistor Circuits Based on the First Mathematical Principle (PR 7.1) . . . . . . . . . . . . . . . . . . . . . 7.2.2 Active Resistor Circuits Based on the Second Mathematical Principle (PR 7.2) . . . . . . . . . . . . . . . . . . 7.2.3 Active Resistor Circuits Based on the Third Mathematical Principle (PR 7.3) . . . . . . . . . . . . . . . . . . . . 7.2.4 Active Resistor Circuits Based on the Fourth Mathematical Principle (PR 7.4). . . . . . . . . . . . . . . . . . . 7.2.5 Active Resistor Circuits Based on the Fifth Mathematical Principle (PR 7.5). . . . . . . . . . . . . . . . . . . . . 7.2.6 Active Resistor Circuits Based on Different Mathematical Principles (PR 7.D) . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multifunctional Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Mathematical Analysis for Synthesis of Multifunctional Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1 First Mathematical Principle (PR 8.1) . . . . . . . . . . . . . . . . . . . . . 8.1.2 Second Mathematical Principle (PR 8.2) . . . . . . . . . . . . . . . . . . 8.1.3 Third Mathematical Principle (PR 8.3) . . . . . . . . . . . . . . . . . . . . 8.1.4 Fourth Mathematical Principle (PR 8.4). . . . . . . . . . . . . . . . . . . 8.2 Analysis and Design of Multifunctional Structures . . . . . . . . . . . . . . . 8.2.1 Multifunctional Structures Based on the First Mathematical Principle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2 Multifunctional Structures Based on the Second Mathematical Principle. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.3 Multifunctional Structures Based on the Third Mathematical Principle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.4 Multifunctional Structures Based on the Fourth Mathematical Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

323 323 323 323 324 324 324 324 324 324 341 346 349 352 356 360 360 363 363 363 371 374 374 385 385 409 412 415 427 427

Contents

xv

Appendix 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

431

Appendix 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

437

Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

441

Chapter 1

Differential Structures

1.1

Mathematical Analysis for Synthesis of Differential Amplifiers

Elementary mathematical principles represent the functional basis for designing differential structures [1–55], each theoretical principle corresponding to a class of differential amplifiers. Usually, the proper operation of these circuits uses a biasing in saturation of MOS active devices. The notations of variables are: V1 and V2 represent the input potentials, IOUT signifies the output current, while, usually, VO , VO1 and VO2 constant voltages are introduced for modeling a voltage shifting. In order to obtain a differential structure able to amplify with small distortions an input signal, a linear behavior of the circuit must be implemented.

1.1.1

First Mathematical Principle (PR 1.1)

The first mathematical principle used for implementing differential amplifiers is based on the following relations: IOUT ¼ A

pffiffiffiffi pffiffiffiffi I2 I1

K I1 ¼ ðVGS1 VT Þ2 2 K I2 ¼ ðVGS2 VT Þ2 2 VGS2 VGS1 ¼ V2 V1

) IOUT

rffiffiffiffi K ¼A ðV2 V1 Þ 2

ð1:1Þ

The differential amplifiers based on the previous relation compute a current proportional with the differential input voltage, V2 V1 C.R. Popa, Synthesis of Computational Structures for Analog Signal Processing, DOI 10.1007/978-1-4614-0403-3_1, # Springer Science+Business Media, LLC 2011

1

2

1 Differential Structures

1.1.2

Second Mathematical Principle (PR 1.2)

The mathematical relation that models this principle is: 2 2 2 2 V1 V2 V2 V1 VO2 VO1 VO1 þ VO2 2 2 2 2 V1 V2 V1 þ V2 V1 V2 V1 þ V2 2VO1 þ 2VO2 ¼ 2 2 2 2 ¼ ðVO2 VO1 ÞðV1 V2 Þ ¼ ct: ðV1 V2 Þ

ð1:2Þ

The circuits that use this principle generate a current proportional with the differential input voltage, V1 V2 .

1.1.3

Third Mathematical Principle (PR 1.3)

This principle is illustrated by the following mathematical relation: h

i h i AðV1 V2 Þ2 þ BðV1 V2 Þ þ C AðV1 V2 Þ2 BðV1 V2 Þ þ C ¼ 2BðV1 V2 Þ

ð1:3Þ

The output current will be also proportional with the differential input voltage, V1 V2

1.1.4

Fourth Mathematical Principle (PR 1.4)

The mathematical relation that models this principle is: V1 2 V1 2 V1 2 V C V O VT þ þ VO VT þ VC VO VT 2 2 2 2 V1 VO V T ¼ V1 ð2VC 2VO 2VT Þ 2 þ V1 ð2VO 2VT Þ ¼ 2V1 ðVC 2VT Þ

ð1:4Þ

The output current of the differential amplifier is linearly dependent on the input voltage, V1 .

1.1 Mathematical Analysis for Synthesis of Differential Amplifiers

1.1.5

3

Fifth Mathematical Principle (PR 1.5)

The fifth mathematical principle can be written as follows:

IOUT

1.1.6

V 1 V2 ¼ 2

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi K 2 4K IO þ ðV1 V2 Þ K 2 ðV1 V2 Þ2 4 pffiffiffiffiffiffiffiffi ¼ KIO ðV1 V2 Þ

(1.5)

Sixth Mathematical Principle (PR 1.6)

The method modeled by this mathematical principle, used for linearizing the transfer characteristic of differential structures, uses an anti-parallel connection of two differential amplifiers, the controlled asymmetries between their biasing currents, also between the aspect ratios of their transistors fulfilling this desiderate.

1.1.7

Seventh Mathematical Principle (PR 1.7)

This principle is useful for obtaining a rail-to-rail operation of a differential structure, based on a parallel connection of two complementary differential amplifiers. The mathematical relations of this principle are shown in the following lines: IOUT ¼

pffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi

2K IOp þ IOn ðV1 V2 Þ

(1.6)

pffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffi IOn þ IOp ¼ 2 IO

(1.7)

resulting: IOUT ¼

1.1.8

pffiffiffiffiffiffiffiffiffiffi 8KIO ðV1 V2 Þ

(1.8)

Different Mathematical Principle for Differential Amplifiers (PR 1.D)

There are some circuits based on different mathematical principles that are useful for linearizing the behavior of differential amplifiers.

4


1.2

Analysis and Design of Differential Structures

The classical MOS differential presents a strong nonlinear behavior, as a result of the quadratic characteristic of their constitutive transistors biased in saturation region. In order to improve the linearity of the structure, it is necessary to develop efficient linearization techniques, functional mathematical principles being elaborated for fulfilling this desiderate. Based on the previous presented mathematical analysis, it is possible to design different types of differential structures, included in eight classes, corresponding to the previous presented eight mathematical principles (PR 1.1 – PR 1.7 and PR 1.D). The MOS differential amplifier represents a fundamental block in analog design, having a large area of applications. The analysis of the large signal operation for the classical MOS differential structure (Fig. 1.1) [1, 2] can quantitatively evaluate the circuit’s nonlinearity, being possible to determine the weight of each superiororder distortion introduced by the structure nonlinearity. The VI ¼ V1 V2 differential input voltage can be expressed as follows: VI ¼ VGS1 VGS2 ¼

rffiffiffiffiffiffi! 2I1 VT þ K

rffiffiffiffiffiffi! rffiffiffiffi 2I2 2 pffiffiffiffi pffiffiffiffi VT þ ¼ I1 I2 (1.9) K K

Squaring and replacing the sum I1 þ I2 with IO , it results: 2

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi KV 2 I1 ðIO I1 Þ ¼ IO I 2

(1.10)

The resultant second-order equation will be: I12 IO I1 þ

2 1 KVI2 IO ¼0 2 4

(1.11)

I2

I1 V1

M1

IO

Fig. 1.1 Classical MOS differential structure

M2

RO

V2

1.2 Analysis and Design of Differential Structures

5

having the following solutions: ðI1 Þ1;2

IO IO ¼ 2 2

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi KVI2 K 2 VI4 2 IO 4IO

(1.12)

so: IO IO I1 ¼ þ 2 2

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi KVI2 K 2 VI4 2 ; IO 4IO

IO IO I2 ¼ 2 2

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi KVI2 K 2 VI4 2 IO 4IO

(1.13)

The output differential current will be: sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi KVI2 K 2 VI4 VI I2 I1 ¼ IO 4KIO K 2 VI2 2 ¼ IO 2 4IO

(1.14)

The ðI2 I1 ÞðVI Þ function is strongly nonlinear, the quantitative evaluation of its nonlinearity being possible using a Taylor series expansion. So, it is necessary to compute the superior-order derivates of the following function: f ðVI Þ ¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 4KIO K 2 VI2

(1.15)

and their values for VI ¼ 0 The first-order derivate is: 1=2 f 0 ðVI Þ ¼ K 2 VI 4KIO K 2 VI2

(1.16)

while the second-order one has the following expression: 3=2 f 00 ðVI Þ ¼ 4K 3 IO 4KIO K 2 VI2

(1.17)

f 0 ðVI ÞjVI ¼0 ¼ 0

(1.18)

1 1=2 f 00 ðVI ÞjVI ¼0 ¼ K 3=2 IO 2

(1.19)

resulting:

The Taylor series expansion of the function (1.14) gives: 1=2

ðI2 I1 Þ ðVI Þ ¼ K 1=2 IO VI þ

K 3=2 1=2 8IO

VI3 þ

K 5=2 3=2

128IO

VI5 þ

(1.20)

6


Fig. 1.2 The I1 ðVI Þ and I2 ðVI Þ dependencies for the classical differential amplifier

or: ðI2 I1 Þ ðVI Þ ¼ a1 VI þ a3 VI3 þ a5 VI5 þ

(1.21)

The first term is linearly dependent on the input voltage, while the last two terms model the third-order and fifth-order nonlinearities of the differential structure. The dependencies of the drain currents I1 and I2 on the differential input voltage VI for the differential amplifier from Fig. 1.1 are presented in Fig. 1.2. Considering a load resistance RL ¼ 10 k O, the simulation of the transfer characteristic VO ðVI Þ ¼ RL ðI2 I1 Þ ðVI Þ for the differential amplifier presented in Fig. 1.1 is shown in Fig. 1.3. The simulation of the transfer characteristic VO ðVI Þ for a maximal input range between 0:4 V and 0:4 V and a biasing current IO having the values 0:1 mA, 0:2 mA and 0:3 mA is shown in Fig. 1.4. It could be remarked an increasing of the differential-mode voltage gain for an increasing of the biasing current IO (using pffiffiffi relation (1.20)), the doubling of the biasing current generating an increasing of 2 of the voltage gain. The voltage gain is 10:95 (using relation (1.20)), while the simulated value is 10:43. Fig. 1.5 presents the simulation of the transfer characteristic of the differential amplifier for different values of the common-mode input voltage VC ¼ ðV1 þ V2 Þ=2 (between 1 V and 1:3 V), showing a minimal value of VC of about 1:2 V. The simulation was made considering a passive load attached to the differential amplifier from Fig. 1.1, having R1 ¼ R2 ¼ 10 k O and a supply voltage VDD ¼ 9 V.


7

Fig. 1.3 The VO ðVI Þ dependence for the classical differential amplifier

Fig. 1.4 Parametric VO ðVI Þdependence for the classical differential amplifier

Figure 1.6 represents the simulation of the transfer characteristic of the differential amplifier for different values of the common-mode input voltage VC ¼ ðV1 þ V2 Þ=2 (between 8:9 V and 9:1 V), showing a maximal value for VC of about 9 V. The simulation was made considering a particular implementation of the current source IO from Fig. 1.1 using a classical current mirror.

8


Fig. 1.5 The VO ðVI Þ dependence for multiple common-mode input voltages (1)

Fig. 1.6 The VO ðVI Þ dependence for multiple common-mode input voltages (2)

1.2.1

Differential Structures Based on the First Mathematical Principle (PR 1.1)

The method for obtaining a linear transfer characteristic of the differential amplifier based on the first mathematical principle (PR 1.1) uses the compensation of the squaring characteristic of the MOS transistor biased in saturation using complementary square-root circuits.


9

VDD

Fig. 1.7 Differential structures (1) based on PR 1.1 M1a V1 Ka

V2 M2a Ka

VO M1b Kb

M2b Kb

I1 V1

I2 M2 K

M1 K

V2

IO

-VDD

The first circuit using this method is shown in Fig. 1.7 [3] and it uses two square-root circuits for improving the linearity of the differential amplifier. Using relation that describes the operation of M1a–M1b and M2a–M2b squareroot circuits, the output voltage of the differential amplifier from Fig. 1.7 will be: rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi 1 1 1 1 1 1 2I1 (1.22) þ þ VO ¼ V2 V1 ¼ 2I2 Ka Kb Kb K a Kb Kb Because: pffiffiffiffi pffiffiffiffi I2 I1 ¼

rffiffiffiffi rffiffiffiffi K K ðVGS2 VGS1 Þ ¼ ðV2 V1 Þ 2 2

(1.23)

it results: VO ¼

pffiffiffiffi K

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffi 1 1 1 þ ðV2 V1 Þ Ka K b Kb

(1.24)

equivalent with a linear dependence of the output voltage on the differential input voltage.

10


VDD V1 IOUT1

M7

M5

M6

M8

I3

I3

I4

I4

I1

I2

VC

M1 M3

V2 IOUT2 M2

M4

Fig. 1.8 Differential structures (2) based on PR 1.1

The principle of operation for the differential amplifier shown in Fig. 1.8 [4] is based on the compensation of the squaring characteristic of parallel-coupled differential amplifiers M5–M6 and M7–M8 by two square-rooting circuits, M1–M3 and M2–M4. The principle of operation is similar with the principle of the circuit presented in Fig. 1.7, the advantage being the exclusively biasing in saturation of all MOS transistors. The differential output current of the circuit can be expressed as follows: IOUT1 IOUT2 ¼ ðI3 I1 Þ ðI4 I2 Þ

(1.25)

The constant potential VC is equal with the difference between two gate-source voltages. Supposing a biasing in saturation of all identical MOS transistors, it results: VC ¼ VGS1 VSG3

rffiffiffiffiffiffi rffiffiffiffiffiffi 2I1 2I3 ¼ K K

(1.26)

So: pffiffiffiffi pffiffiffiffi I1 ¼ I3 þ

rffiffiffiffi K VC 2

(1.27)

resulting: I1 ¼ I 3 þ

K 2 pffiffiffiffiffiffiffiffiffiffi V þ 2KI3 VC 2 C

(1.28)

I2 ¼ I 4 þ


(1.29)

and, similarly:


11

VDD M1 4K

I2

I1

M2 4K

M3

M4

I5 IO

M5 4K

M6

M7

M8 4K

I8 IOUT2

IOUT1

IO

Fig. 1.9 Current-mode square-root circuit (1)

From (1.25), (1.28) and (1.29), it results a square-root dependence of the differential output current on the input currents: IOUT1 IOUT2 ¼ The differential expression and V2 , as follows:

pffiffiffiffiffiffi pffiffiffiffi pffiffiffiffi

2K VC I4 I3

(1.30)

pffiffiffiffi pffiffiffiffi I4 I3 is a function of the input potentials V1

rffiffiffiffi rffiffiffiffi K K ðVSG6 VT Þ ðVSG5 VT Þ 2 2 rffiffiffiffi rffiffiffiffi K K ¼ ðVSG6 VSG5 Þ ¼ ðV1 V2 Þ 2 2

pffiffiffiffi pffiffiffiffi I4 I3 ¼

ð1:31Þ

From (1.30) and (1.31), it results a linear dependence of the output current on the differential input voltage: IOUT1 IOUT2 ¼ KVC ðV1 V2 Þ

(1.32)

Alternate implementations of square-root circuits used for linearizing the transfer characteristic of the classical differential amplifier are shown in Figs. 1.9–1.13 [4]. For the square-root circuit shown in Fig. 1.9, the translinear loop realized using M1, M3, M5 and M6 transistors has the following characteristic equation: VSG3 þ VSG6 ¼ VSG1 þ VSG5

(1.33)

pffiffiffiffiffi pffiffiffiffi pffiffiffiffi IO þ I1 ¼ I5

(1.34)

So:

12


VDD I2

I1 M1 VB1

M2 M5

VB2

M3

M4

M6

M7

VB1

M8 I8

I5 IOUT1

IOUT2


VDD M6

M5 VC

VC M2 IOUT1 ID2 I1

M1

M4 I1

I2

I1

I2

M3 ID3 IOUT2 I2


VDD VC

M5

I1

M6

I2

M1

M2 M3

I Fig. 1.12 Current-mode square-root circuit (4)

IOUT1

IO

M4 I’

IOUT2


13

VDD VC M1

M2 M4

M3 I3

IOUT1 I1

I4 I2

I1

IOUT2 I2


Squaring the previous relation, it is possible to write that: pffiffiffiffiffiffiffiffi I5 ¼ IO þ I1 þ 2 IO I1

(1.35)

In a similar way, it results, from the right part of the circuit: pffiffiffiffiffiffiffiffi I8 ¼ IO þ I2 þ 2 IO I2

(1.36)

The differential output current of the squaring structure can be expressed as follows: pffiffiffiffiffipffiffiffiffi pffiffiffiffi IOUT1 IOUT2 ¼ ðI5 þ I2 Þ ðI8 þ I1 Þ ¼ 2 IO I1 I2

(1.37)

In order to obtain a linear differential amplifier, the square-root circuit shown in Fig. 1.9 must have as input currents the drain currents I1 and I2 of a classical differential amplifier M9–M10, resulting the circuit presented in Fig. 1.14. [4] The differential output current of this circuit can be obtained replacing the expressions of I1 and I2 drain currents by their squaring dependencies on the gatesource voltages: IOUT1 IOUT2

pffiffiffiffiffi ¼ 2 IO

rffiffiffiffi pffiffiffiffiffiffiffiffiffiffi K ðVSG9 VSG10 Þ ¼ 2KIO ðV2 V1 Þ 2

(1.38)

For the square-root circuit presented in Fig. 1.10, the translinear loop achieved using M1, M2, M5 and M6 transistors has the following characteristic equation: VB2 VB1 ¼ ðVGS1 þ VSG5 Þ ðVGS2 þ VSG6 Þ

(1.39)

resulting: rffiffiffiffi pffiffiffiffi pffiffiffiffi K ðVB2 VB1 Þ ¼ 2 I5 2 I1 2

(1.40)

14


VDD IO M1 V1 4K

M9

M10

I1

I2

M3

M4 M5

M6

M7

I5 IO

V2 M2 4K

M8 4K

I8 IOUT2

IOUT1

IO


or: pffiffiffiffi pffiffiffiffi VB2 VB1 I5 ¼ I1 þ 2

rffiffiffiffi K 2

(1.41)

Squaring the previous relation, it results: rffiffiffiffiffiffiffi KI1 ðVB2 VB1 Þ2 I5 ¼ I1 þ ðVB2 VB1 Þ þ K 2 8

(1.42)

and, similarly: I8 ¼ I2 þ

rffiffiffiffiffiffiffi KI2 ðVB2 VB1 Þ2 ðVB2 VB1 Þ þ K 2 8

(1.43)

The differential output current can be expressed as follows: IOUT1 IOUT2 ¼ ðI5 þ I2 Þ ðI8 þ I1 Þ

(1.44)

From (1.42)–(1.44), the expression of the differential output current becomes: IOUT1 IOUT2

rffiffiffiffi K pffiffiffiffi pffiffiffiffi ¼ ðVB2 VB1 Þ I1 I 2 2

(1.45)

The implementation of a differential amplifier using this square-root circuit is shown in Fig. 1.15 [4].


15

VDD IO V1

M9 I1

M1 VB1

M2 M5

V2

M10 I2 VB2

M3

M6

M4 M7

VB1

M8 I8

I5

IOUT2

IOUT1 Fig. 1.15 Differential structures (4) based on PR 1.1

The differential output current of the linear differential amplifier from Fig. 1.15 can be obtained replacing I1 and I2 currents by their squaring dependencies on the gate-source voltages: K K IOUT1 IOUT2 ¼ ðVB2 VB1 Þ ðVSG9 VSG10 Þ ¼ ðVB2 VB1 Þ ðV2 V1 Þ 2 2

(1.46)

equivalent with: Gm ¼

K ðVB2 VB1 Þ 2

(1.47)

The square-root circuit presented in Fig. 1.11 is composed from two identical cores (M1–M2 and M3–M4), each of them computing the square-root function of an input current. For M1–M2 pair, VC input voltage can be expressed as follows: VC ¼ VSG2 VSG1

rffiffiffiffi 2 pffiffiffiffiffiffi pffiffiffiffi ID2 I1 ¼ K

(1.48)

So: pffiffiffiffiffiffi ID2 ¼

rffiffiffiffi pffiffiffiffi K VC þ I1 2

(1.49)

16


VDD M6

M5 VC

VC M2

M4

M3

I1

I2

I1

I1

I2

I2

M7

M8

M9

M10

IOUT1 ID1

V1

M1

ID3

IOUT2

V2 -VDD


or: ID2 ¼ I1 þ

K 2 pffiffiffiffiffiffi pffiffiffiffi V þ 2K VC I1 2 C

(1.50)

The expression of the first output current will be: IOUT1 ¼ ID2 I1 ¼


(1.51)

Similarly: IOUT2 ¼


(1.52)

resulting the following expression of the differential output current: IOUT1 IOUT2 ¼

pffiffiffiffiffiffi pffiffiffiffi pffiffiffiffi 2K VC I1 I2

(1.53)

Attaching two parallel-connected classical differential amplifiers to the double square-root circuit presented in Fig. 1.11, it results a differential amplifier with a linear transfer characteristic (Fig. 1.16) [4]. For this circuit, the differential input voltage can be expressed as follows: V1 V2 ¼ VGS7 VGS10

rffiffiffiffi 2 pffiffiffiffi pffiffiffiffi ¼ I1 I2 K

(1.54)


17

From (1.53) and (1.54), it is possible to obtain the expression of the differential output current as a function on the differential input voltage: IOUT1 IOUT2 ¼ KVC ðV1 V2 Þ

(1.55)

so an equivalent transconductance of the circuit expressed by: Gm ¼ KVC

(1.56)

For the square-root circuit shown in Fig. 1.12, the translinear loop realized using M1, M3, M5 and M6 transistors has the following characteristic equation: VSG1 þ VSG3 ¼ VSG5 þ VSG6

(1.57)

Noting VSG5 þ VSG6 with VC , it results: pffiffi I¼

rffiffiffiffi pffiffiffiffi K ðVC 2VT Þ I1 2

(1.58)

So: I ¼ I1 þ

pffiffiffiffiffiffiffiffiffiffi K ðVC 2VT Þ2 2KI1 ðVC 2VT Þ 2

(1.59)

The expression of the first output current will be: IOUT1 ¼ I þ I2 ¼ I1 þ I2 þ


(1.60)

and, similarly: IOUT2 ¼ I1 þ I2 þ


(1.61)

The differential output current can be expressed as follows: IOUT1 IOUT2 ¼

pffiffiffiffiffiffi pffiffiffiffi pffiffiffiffi 2K ðVC 2VT Þ I2 I1

(1.62)

The biasing voltage is equal with: VC ¼ VSG5 þ VSG6

rffiffiffiffiffiffiffi 2IO ¼ 2VT þ 2 K

(1.63)

Replacing (1.63) in (1.62), it can be obtained: pffiffiffiffiffipffiffiffiffi pffiffiffiffi IOUT1 IOUT2 ¼ 4 IO I2 I1

(1.64)

18


VDD


IO V1

M7

V2

M8 M5

I1

I2

M6 M1

M2 M3

IO

I

M4 I’ IOUT2

IOUT1

The implementation of a differential amplifier using this square-root circuit is presented in Fig. 1.17 [4, 5]. The differential output current of the linear differential amplifier from Fig. 1.17 can be obtained replacing the currents I1 and I2 by their squaring dependencies on the gate-source voltages: IOUT1 IOUT2

pffiffiffiffiffi ¼ 4 IO

rffiffiffiffi pffiffiffiffiffiffiffiffiffiffi K ðVSG8 VSG7 Þ ¼ 8KIO ðV1 V2 Þ 2

(1.65)

The equivalent transconductance of the circuit can be expressed as follows: Gm ¼

pffiffiffiffiffiffiffiffiffiffi 8KIO

(1.66)

Another possible implementation of a square-root circuit based on a similar principle is shown in Fig. 1.13. The VC potential can be expressed as follows: VC ¼ VSG3 VGS1

rffiffiffiffi 2 pffiffiffiffi pffiffiffiffi

¼ I3 I1 K

(1.67)

resulting: pffiffiffiffi pffiffiffiffi I3 ¼ I1 þ

rffiffiffiffi K VC 2

(1.68)

Squaring the previous relation, the expression of I3 current will be: I3 ¼ I 1 þ


(1.69)


19

VDD VC M1

M2 M4

M3 IOUT1 I3

V1

I1 M5

I4 I1 M6

I2 M7

I2 M8

IOUT2

V2


and, similarly: I4 ¼ I 2 þ


(1.70)

The output currents have the following expressions: IOUT1 ¼ I3 I1 ¼


(1.71)

IOUT2 ¼ I4 I2 ¼


(1.72)

and:

So, the differential output current will be: IOUT1 IOUT2 ¼

pffiffiffiffiffiffi pffiffiffiffi pffiffiffiffi 2K VC I1 I2

(1.73)

The implementation of a differential amplifier using this square-root circuit is presented in Fig. 1.18 [4]. The I1 and I2 currents are generated by two parallelconnected differential amplifiers, M5–M8 and M6–M7, respectively. The differential output current of the linear differential amplifier from Fig. 1.18 can be obtained replacing the I1 and I2 currents by their squaring dependencies on the gate-source voltages of M5–M8 transistors: IOUT1 IOUT2

pffiffiffiffiffiffi ¼ 2K VC

rffiffiffiffi K ðVGS5 VGS8 Þ ¼ K VC ðV1 V2 Þ 2

(1.74)

20


VDD IOUT1’

V1

IO

SQR

IO

SQR

I1

I2

M1

M2

IOUT2’

V2 IOUT

I1 + I2


resulting: Gm ¼ KVC

(1.75)

The same method for improving the linearity of the classical differential amplifier is used for designing the following differential amplifier. The principle is presented in Fig. 1.19, while the implementation of square-root circuits from Fig. 1.19 [4, 6] is shown in Fig. 1.20a [7].

1.2.1.1

The FGMOS Transistor

The multiple-input floating-gate transistor (M from Fig. 1.20a) is an ordinary MOS device whose gate is floating. The basic structure of a n-channel floating-gate MOS transistor is shown in Fig. 1.20b. The first silicon layer forms the floating-gate over the channel, while the second polysilicon layer forms the multiple input gates, which is located over the floating-gate. This floating-gate is capacitive coupled to the multiple input gates. The symbolical representation of such devices with n inputs is shown in Fig. 1.20c. The drain current of a FGMOS transistor with n-input gates working in the saturation region is given by the following equation: " #2 n K X ID ¼ ki ðVi VS Þ VT 2 i¼1

(1.76)

where K ¼ mn Cox ðW=LÞ is the transconductance parameter of the transistor, mn is the electron mobility, Cox is the gate oxide capacitance, W=L is the transistor aspect


a

VDD

21

b V 1 V2 D

...

...

C1 C2 ...

Vn

... Cn

n+ IOUT1,2’ IO

IO

I1,2

n+

floatinggate

p substrat

I

c

M 4K M1/ M2 K

S

MO K

-VDD

V1 V2

...

D

...

Vn

S B


ratio, ki ; i ¼ 1; :::; n are the capacitive coupling ratios, Vi is the ith input voltage, VS is the source voltage and VT is the threshold voltage of the transistor. The capacitive coupling ratio is defined as: ki ¼ P n

Ci

(1.77)

Ci þ CGS

i¼1

Ci represent the input capacitances between the floating-gate and each of the i-th input and CGS is the gate-source capacitance. Equation (1.76) shows that the FGMOS transistor drain current in saturation is proportional with the square of the weighted sum of the input signals, where the weight of each input signal is determined by the capacitive coupling ratio of the input. The drain current of M transistors from Fig. 1.20a can be expressed as follows: 2 4K VGSO þ VGS1;2 VT I¼ 2 2

(1.78)

while VGSO and VGS1;2 expressions can be obtained from the squaring dependencies of the drain currents of MO and M1/M2 transistors on their gate-source voltages pffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi VGSO ¼ VT þ 2IO =K and VGS1;2 ¼ VT þ 2I1;2 =K . So: I¼

pffiffiffiffiffi pffiffiffiffiffiffiffi 2 pffiffiffiffiffiffiffiffiffiffiffi IO þ I1;2 ¼ IO þ I1;2 þ 2 IO I1;2

(1.79)

resulting: pffiffiffiffiffiffiffiffiffiffiffi IOUT1;2 0 ¼ I IO I1;2 ¼ 2 I1;2 IO

(1.80)

22


VDD M5

M6 M9

M10 I1

I2 V2

I1 M2 M1

I2

V1

I1’

I1 M3

M7

IOUT1

I2

M8

M4

I 2'

IOUT2

VC2

VC1


The circuit shown in Fig. 1.19 will have a linear transfer characteristic: pffiffiffiffiffipffiffiffiffi pffiffiffiffi IOUT ¼ IOUT1 0 IOUT2 0 ¼ 2 IO I1 I2 rffiffiffiffi pffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi K ðVGS1 VGS2 Þ ¼ 2KIO ðV1 V2 Þ ¼ Gm ðV1 V2 Þ ð1:81Þ ¼ 2 IO 2 pffiffiffiffiffiffiffiffiffiffi Gm ¼ 2KIO being the circuit transconductance. So, in a first-order analysis, the dependence of the output current of the differential circuit on its differential input voltage is perfectly linear. A similar method used for linearizing the transfer characteristic of the differential amplifier is presented in Fig. 1.21 [8]. The elementary differential amplifier is composed by M1 and M2 transistors. The linearization of its transfer characteristic is realized using two square-root circuits (M3–M6 and M7–M10), their operation being characterized by the following relations: VC2 ¼ VGS7 VGS8

rffiffiffiffi 2 pffiffiffiffi pffiffiffiffiffi0

¼ I1 I 1 K

(1.82)

resulting: I1 0 ¼ I 1 þ

pffiffiffiffiffiffi pffiffiffiffi K 2 VC2 2K VC2 I1 2

(1.83)

The output current of the first square-root circuit is: IOUT1 ¼ I1 I1 0 ¼

pffiffiffiffiffiffi pffiffiffiffi K 2 VC2 þ 2K VC2 I1 2

(1.84)


23

Similarly, for the second square-root circuit, the output current can be expressed as follows: IOUT2 ¼ I2 I2 0 ¼

pffiffiffiffiffiffi pffiffiffiffi K 2 VC2 þ 2K VC2 I2 2

(1.85)

Because: IOUT ¼ IOUT2 IOUT1

(1.86)

it can be obtained: IOUT ¼

pffiffiffiffiffiffi pffiffiffiffi pffiffiffiffi 2K VC2 I1 I2

(1.87)

As all MOS transistors are biased in saturation region, the differential input voltage of the M1–M2 differential amplifier depends on the difference of the square-roots of the drain currents, I1 and I2 : V1 V2 ¼ VGS1 VGS2

rffiffiffiffi 2 pffiffiffiffi pffiffiffiffi I1 I2 ¼ K

(1.88)

From the previous relations it results: IOUT ¼ KVC2 ðV1 V2 Þ

(1.89)

equivalent with a constant transconductance of the entire differential amplifier presented in Fig. 1.21, Gm ¼ KVC2 . Comparing with the previous similar circuit, the linear differential amplifier from Fig. 1.21 presents the important advantage of implementing also the multiplier function (VC2 and V1 V2 can be considered as input voltages).

1.2.2

Differential Structures Based on the Second Mathematical Principle (PR 1.2)

The symmetrical circuit presented in Fig. 1.22 [9] represents a differential amplifier having the transfer characteristic linearized using the second mathematical principle (PR 1.2). The gate-source voltages of M1a and M4a transistors are equal because they are identical and are biased at the same drain current I1a . As V1 ¼ VGS1a þ VGS4a ,

24


IOUT1

I1a V1

IOUT2

I3a M3a M1a 4K

IO VO

I3b M3b M1b 4K

I1b V2

M5 M4a

M2a 4K

M2b M6 4K

M4b

M7


it results that the gate potential of M2a transistor is V1 =2. Similarly, the gate-source voltages of M2a and M3a are equal, resulting: V1 ¼ 2VGS3a ¼ 2 VT þ VO 2

rffiffiffiffiffiffiffiffi! 2I3a 4K

(1.90)

equivalent with: I3a ¼

2 K V1 VO 2VT 2 2

(1.91)

2 K V1 VT 2 2

(1.92)

and: I1a ¼

The difference between the previous currents can be expressed as follows: I1a I3a ¼

K ðVO 3VT Þ ðV1 VO þ VT Þ 2

(1.93)

Similarly, the I1b I3b differential current will have the following expression: I1b I3b ¼

K ðVO 3VT Þ ðV2 VO þ VT Þ 2

(1.94)

1.2 Analysis and Design of Differential Structures Fig. 1.23 Differential structures (2) based on PR 1.2

25

IOUT2

IOUT1 I1 V1

I4 M1

M4 I2

V2

I5 M2

M5

M3

M6 VC

Thus, the total differential output current of the circuit, IOUT1 IOUT2 , will be: IOUT1 IOUT2 ¼ ðI1a þ I3b Þ ðI1b þ I3a Þ ¼ ðI1a I3a Þ K ðI1b I3b Þ ¼ ðVO 3VT ÞðV1 V2 Þ 2

(1.95)

The VO biasing voltage is implemented as a current-controlled voltage source, this realization having the advantage of removing the dependence of the circuit performances on the variation of the threshold voltage with temperature and technological parameters: VO ¼ 3VGS5

rffiffiffiffiffiffiffi! 2IO ¼ 3 VT þ K

(1.96)

For this particular realization of the voltage source VO , the total differential output current becomes: IOUT1 IOUT2

rffiffiffiffiffiffiffiffi KIO ¼3 ðV1 V2 Þ 2

(1.97)

It was obtained a linear dependence of the output current on the differential input voltage, resulting an equivalent transconductance of the entire structure that can be controlled by the IO biasing current: rffiffiffiffiffiffiffiffi IOUT1 IOUT2 KIO ¼3 Gm ¼ V1 V2 2

(1.98)

An alternate implementation of a linear differential amplifier using the same linearization principle is presented in Fig. 1.23 [9].

26


The differential output current of the circuit can be expressed as follows: IOUT ¼ IOUT1 IOUT2 ¼ ðI1 þ I5 Þ ðI2 þ I4 Þ ¼ ðI1 I2 Þ ðI4 I5 Þ

(1.99)

Because M1 and M3 transistors are identical and they are biased at the same drain current, their gate-source voltages will be equal, so: 2 K V1 VT 2 2

(1.100)

2 K V1 VC V T 2 2

(1.101)

I1 ¼ and: I2 ¼

Similarly, for the right part of the circuit, the expressions of the drain currents are: 2 K V2 VT 2 2

(1.102)

2 K V2 VC V T 2 2

(1.103)

I4 ¼ and: I5 ¼ resulting:

K K K IOUT ¼ VC ðV1 VC 2VT Þ VC ðV2 VC 2VT Þ ¼ VC ðV1 V2 Þ 2 2 2

(1.104)

the equivalent transconductance being expressed by: Gm ¼

K VC 2

(1.105)

The circuit presented in Fig. 1.23 presents the disadvantage of requiring a current from the VC voltage source. In order to avoid a current consumption from the external VC voltage source, the circuit presented in Fig. 1.23 can be modified, as it is shown in Fig. 1.24.


27

IOUT1

IOUT2 I5

I1 V1

M1

M3

IO 4IO

I2

IO M8 M6 VC

M2 M4 VC M9

I2 + I O

I6

M5

V2

M7

I6+ IO

Fig. 1.24 Differential structures (2) based on PR 1.2 with implementation of VC source

The VC potential is obtained as the difference between the gate-source of M9 transistor (biased at 4IO current) and the gate sources of M4 or M8 transistors (working at IO current):

¼

VC ¼ VGS9 VGS4 ¼ VGS9 VGS8 rffiffiffiffiffiffiffi! rffiffiffiffiffiffiffi! rffiffiffiffiffiffiffi 8IO 2IO 2IO VT þ VT þ ¼ K K K

(1.106)

Replacing (1.106) in (1.105), it results: IOUT ¼

rffiffiffiffiffiffiffiffi KIO ðV1 V2 Þ 2

(1.107)

In this case, the equivalent transconductance can be controlled by the reference current IO : rffiffiffiffiffiffiffiffi KIO Gm ¼ 2

(1.108)

A differential difference amplifier (DDA) can be designed using two previous presented differential amplifiers, the block diagram of the DDA being shown in Fig. 1.25. These circuits present a multitude of applications such as amplifying or comparing of differential input voltages and designing complex active filters. The output current of the DDA can be expressed as follows: IOUT ¼ ðIOUT1I þ IOUT2II Þ ðIOUT2I þ IOUT1II Þ ¼ ðIOUT1I IOUT2I Þ ðIOUT1II IOUT2II Þ

ð1:109Þ

28


CM IOUT

IOUT1-I

IOUT2-I

V2 V3

DA I

V1

IOUT2-II

IOUT1-II

DA II

V4

Fig. 1.25 The block diagram of a DDA circuit VDD IOUT

IOUT1-I

V1

IOUT2-I

I2-I

IO

4IO

IO

IO +I2-I

I6-I

IO + I6-I

V2

IOUT2-II

IOUT1-II

V3

I2-II

IO 4IO

IO +I2-II

IO

I6-II

V4

IO + I6-II

Fig. 1.26 DDA circuit

Considering that DA I and DA II differential amplifiers from Fig. 1.25 are identical, the expression of the output current becomes: IOUT ¼ Gm ½ðV1 V2 Þ ðV3 V4 Þ

(1.110)

with Gm expressed by (1.108). The complete implementation of the DDA structure is presented in Fig. 1.26. The differential amplifier shown in Fig. 1.27 [10] presents a linear transfer characteristic, obtained using the same mathematical principle, its equivalent transconductance being controlled by a reference voltage. The expression of I3 current is: I3 ¼

K K ðVGS5 VT Þ2 ¼ ðVSG3 VT Þ2 2 2

(1.111)

Because M1 and M3 are identical and they are biased at the same drain current, their source-gate voltages will be equal, so: I3 ¼

K K ðVSG1 VT Þ2 ¼ ðVDD V2 VT Þ 2 2

(1.112)


29

VDD

M9

M10 V2

M1 M6

V1

M7 M2

I3 M5

I2

I1

M13

M14

IOUT I4 M8

M4

M3 VC

M12

M11

Fig. 1.27 Differential structure (3) based on PR 1.2

Similarly: I4 ¼

K ðVDD V1 VT Þ 2

(1.113)

The I1 current can be expressed as follows: K K ðVGS14 VT Þ2 ¼ ðVSG4 þ VC VT Þ2 2 2 K ¼ ðVDD V1 þ VC VT Þ2 2

I1 ¼

ð1:114Þ

and, similarly: I2 ¼

K ðVDD V2 þ VC VT Þ2 2

(1.115)

The expression of the differential output current is: IOUT ¼ ðI1 þ I3 Þ ðI2 þ I4 Þ

(1.116)

30


VDD M5

M6

VA’

VB’

VA M1

V1

VB M3

Ma M2

V1

Mb M4

V2 IO

IO

ID1 + ID3

ID2 + ID4

Fig. 1.28 Differential structure (4) based on PR 1.2 – circuit’s core

resulting: IOUT ¼

K ðV2 V1 Þð2VDD V1 V2 þ 2VC 2VT Þ 2

K ðV2 V1 Þð2VDD V1 V2 2VT Þ ¼ KVC ðV2 V1 Þ 2

ð1:117Þ

The advantage of this linear differential amplifier is the independence of its equivalent transconductance on the threshold voltage, the result being an important increasing of the circuit accuracy. The linearization technique for the differential amplifier presented in Fig. 1.28 [11, 12] exploits the second mathematical principle (PR 1.2). Its output current is made to be linearly dependent on the drain currents of M1–M4 transistors using a current mirror (not shown in Fig. 1.28), IOUT ¼ ðID1 þ ID3 Þ ðID2 þ ID4 Þ: K K 2 2 ðVA 0 V1 VT Þ þ ðVB 0 V2 VT Þ 2 2 K K 2 2 0 ðVA V2 VT Þ ðVB 0 V1 VT Þ 2 2

IOUT ¼

ð1:118Þ

resulting: IOUT ¼ þ

K ðV2 V1 Þð2VA 0 V1 V2 2VT Þ 2

K ðV1 V2 Þð2VB 0 V1 V2 2VT Þ 2

ð1:119Þ

and: IOUT ¼ K ðVB 0 VA 0 ÞðV1 V2 Þ

(1.120)


31 VDD M13

M12 M11

M5 V1

VA M1

M14

M6 VB’

VA’ VB M3

Ma M2

Mb M4

V1

V2 IO

IOUT

IO

M9

M7

M17

M15

M10

M8

M18

M16

Fig. 1.29 Differential structure (4) based on PR 1.2 – complete implementation

Because: 0

rffiffiffiffiffiffiffi 2IO ¼ VA þ VT þ K

0

rffiffiffiffiffiffiffi 2IO ¼ VB þ VT þ K

VA ¼ VA þ VSGa

(1.121)

and: VB ¼ VB þ VSGb

(1.122)

it results: IOUT ¼ K ðVB VA Þ ðV1 V2 Þ

(1.123)

The equivalent transconductance of the entire structure presented in Fig. 1.28 can be expressed as follows: Gm ¼

IOUT ¼ K ð VB V A Þ V1 V 2

(1.124)

The complete implementation of previous differential amplifier (Fig. 1.29) [11] contains two cascode current mirrors, M7–M10 and M15–M18, in order to increase the circuit accuracy. The efficiency of the second mathematical principle can be illustrated by the differential amplifier presented in Fig. 1.30 [13], having a very simple implementation comparing with the previous circuits. The VC1 and VC2 voltages represent

32


VDD


M8

M7

IOUT

M3

V1

M5

M4 M6 VP2

VP1 V2

IO1 VC1

M1

V1

IO2 VC2

M2

constant external potentials that impose the drain currents of M1 and M2 transistors to be equal with IO1 and IO2 , respectively. The VP2 VP1 voltage is considered to be imposed by an external circuit. The differential amplifier is composed from two parallel-connected differential stages (M3–M5 and M4–M6), having different biasing currents (IO1 and IO2 , respectively). The output current of the entire structure can be expressed as follows: IOUT ¼ ID3 þ ID4 ID5 ID6

(1.125)

equivalent with: K K ðV1 VP1 VT Þ2 þ ðV2 VP2 VT Þ2 2 2 K K 2 ðV2 VP1 VT Þ ðV1 VP2 VT Þ2 2 2

IOUT ¼

ð1:126Þ

or: IOUT ¼ K ðV1 V2 Þ ðVP2 VP1 Þ

(1.127)

As VP1 and VP2 potentials are fixed, the behavior of the circuit shown in Fig. 1.30 is linear, having an equivalent transconductance expressed as: Gm ¼ K ðVP2 VP1 Þ

(1.128)

A method for obtaining a linear differential amplifier is presented in Fig. 1.31.


33

VDD

VDD

I4

I1 M1

V1

M5

M6

M2

I3

I2

V2

M7 M8

M3

M4 VC


Because M5 and M3 transistors are biased at the same drain current, VGS5 ¼ VGS3 ¼ VC , for the left part of the circuit, the differential output current will have the following expression: I1 I 2 ¼

K K K ðV1 VT Þ2 ðV1 VC VT Þ2 ¼ VC ð2V1 VC 2VT Þ (1.129) 2 2 2

Similarly, for the right part of the circuit, it results: I4 I3 ¼

K VC ð2V2 VC 2VT Þ 2

(1.130)

Using a current mirror (not shown in Fig. 1.31), the differential output current of the differential amplifier presented in Fig. 1.31 is designed to be: IOUT ¼ ðI1 I2 Þ ðI4 I3 Þ ¼ KVC ðV1 V2 Þ

(1.131)

The equivalent transconductance of the structure is independent on the threshold voltage, with the result of reducing the circuit errors. Another implementation of a linear differential amplifier based on the same mathematical principle is presented in Fig. 1.32 [14]. The expressions of IOUT1 and IOUT2 currents are: IOUT1 ¼

K K ðVL VT Þ2 þ ðVR VB VT Þ2 2 2

(1.132)

34



IOUT2

IOUT1

V1 VB

VR

VL

VB

V2 IO

and: IOUT2 ¼

K K ðVR VT Þ2 þ ðVL VB VT Þ2 2 2

(1.133)

Implementing an output current IOUT as the difference between IOUT1 and IOUT2 , it results: IOUT ¼ IOUT1 IOUT2 ¼ þ

K ðVL VR ÞðVL þ VR 2VT Þ 2

K ðVR VL ÞðVL þ VR 2VB 2VT Þ 2

(1.134)

So: IOUT ¼ KVB ðVL VR Þ ¼ KVB ðV1 V2 Þ

(1.135)

The equivalent transconductance of the circuit can be controlled by the biasing voltage VB .

1.2.3

Differential Structures Based on the Third Mathematical Principle (PR 1.3)

The circuit shown in Fig. 1.33 [15] represents a differential amplifier having the transfer characteristic linearized using the third mathematical principle (PR 1.3). The advantage of the following circuits is represented by the possibility of implementing also the squaring function, by considering the sum of their output currents.


35

2IO V2

M3

M4

ID3

ID4 VDD

IOUT1 M1

M5

M6

IC

M7

M8

V1

IOUT2 M2

VC 2IO

M9

2IO


The current sources and the circuit’s connections impose the following relation between the currents: ID3 þ ID6 ¼ ID4 þ ID7 ¼ ID3 þ ID4 ¼ 2IO

(1.136)

resulting ID6 ¼ ID4 and ID7 ¼ ID3 . The translinear loops containing M1, M5, M6 and M2, M7, M8 transistors have the following characteristic equations: VGS1 VC ¼ VGS5 VGS6

(1.137)

VGS2 VC ¼ VGS8 VGS7

(1.138)

and:

resulting: rffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffi 2IOUT1 2 pffiffiffiffiffiffi pffiffiffiffiffiffi

VC ¼ ID3 ID4 VT þ K K

(1.139)

and: rffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffi 2IOUT2 2 pffiffiffiffiffiffi pffiffiffiffiffiffi

VC ¼ VT þ ID4 ID3 K K

(1.140)

36


The IOUT1 and IOUT2 output currents can be expressed as follows:

IOUT1

K ¼ 2

"rffiffiffiffi #2 2 pffiffiffiffiffiffi pffiffiffiffiffiffi

ID3 ID4 þ ðVC VT Þ K

IOUT2

K ¼ 2

"rffiffiffiffi #2 2 pffiffiffiffiffiffi pffiffiffiffiffiffi

ID4 ID3 þ ðVC VT Þ K

(1.141)

and:

(1.142)

or: IOUT1 ¼

pffiffiffiffiffiffi pffiffiffiffiffiffi 2 pffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi

K ID3 ID4 þ 2K ID3 ID4 ðVC VT Þ þ ðVC VT Þ2 2 (1.143)

and: IOUT2 ¼

pffiffiffiffiffiffi pffiffiffiffiffiffi 2 pffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi

K ID4 ID3 þ 2K ID4 ID3 ðVC VT Þ þ ðVC VT Þ2 2 (1.144)

The circuit’s differential input voltage is equal with the difference between two source-gate voltages: V1 V2 ¼ VSG3 VSG4

rffiffiffiffi 2 pffiffiffiffiffiffi pffiffiffiffiffiffi

ID3 ID4 ¼ K

(1.145)

From (1.143), (1.144) and (1.145), the expressions of the output currents become: IOUT1 ¼

K K ðV1 V2 Þ2 þ K ðV1 V2 ÞðVC VT Þ þ ðVC VT Þ2 2 2

(1.146)

IOUT2 ¼

K K ðV1 V2 Þ2 K ðV1 V2 ÞðVC VT Þ þ ðVC VT Þ2 2 2

(1.147)

and:

As VC voltage is equal with the gate-source of M9 transistor, that is biased at the IC constant current, the previous relations become: IOUT1 ¼

pffiffiffiffiffiffiffiffiffiffi K ðV1 V2 Þ2 þ 2KIC ðV1 V2 Þ þ IC 2

(1.148)


IO

IOUT1

M5

V1

M6

37

IOUT2

IO 2IO M7

I1 + IO

M8

V2

I2 + IO

IO

IO M1

M2

M3

M4

V 2IO

2IO Fig. 1.34 Differential structure (2) based on PR 1.3

and: IOUT2 ¼

pffiffiffiffiffiffiffiffiffiffi K ðV1 V2 Þ2 2KIC ðV1 V2 Þ þ IC 2

(1.149)

The differential output current will have the following expression: IOUT1 IOUT2 ¼

pffiffiffiffiffiffiffiffiffiffi 8KIC ðV1 V2 Þ

(1.150)

so, the circuit implements a linear dependence of the differential output current on the differential input voltage, the equivalent transconductance being: Gm ¼

pffiffiffiffiffiffiffiffiffiffi 8KIC

(1.151)

A realization of a linear differential amplifier using the computation of the arithmetical mean for input potentials is presented in Fig. 1.34. As M1–M4 transistors implement an arithmetical mean circuit, the expression of V potential will be: V¼

V1 þ V2 2

(1.152)

38


V1

IO

IO

IOUT1

M1

M2

IOUT2

M3

M4

V2


For M5–M6 differential amplifier, the differential input voltage can be expressed as follows: V1 V ¼ VGS5 VGS6

rffiffiffiffi 2 pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi

¼ IOUT1 IO K

(1.153)

Replacing (1.152) in (1.153), it results: IOUT1

rffiffiffiffiffiffiffiffi KIO K ¼ IO þ ðV1 V2 Þ þ ðV1 V2 Þ2 2 8

(1.154)

Similarly, for M7–M8 differential amplifier, it can be obtained: IOUT2

rffiffiffiffiffiffiffiffi KIO K ¼ IO ðV1 V2 Þ þ ðV1 V2 Þ2 2 8

(1.155)

The output current of the differential amplifier circuit shown in Fig. 1.34 will be: IOUT ¼ IOUT1 IOUT2 ¼


(1.156)

A differential amplifier with linear transfer characteristic can be implemented using two classical differential amplifiers (Fig. 1.35) [16]. For M1–M2 differential amplifier, the differential input voltage can be expressed as follows: rffiffiffiffi 2 pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi

V1 V2 ¼ IOUT1 IO K

(1.157)


39

VDD

VC + VIN

IOUT2

IO

IOUT1 M1 VC

M3

M2

VC - VIN

IO

- VDD Fig. 1.36 Differential structure (4) based on PR 1.3

resulting: IOUT1 ¼ IO þ

pffiffiffiffiffiffiffiffiffiffi K 2KIO ðV1 V2 Þ þ ðV1 V2 Þ2 2

(1.158)

Similarly, for M3–M4 differential amplifier, the expression of I2 current will be: IOUT2 ¼ IO

pffiffiffiffiffiffiffiffiffiffi K 2KIO ðV1 V2 Þ þ ðV1 V2 Þ2 2

(1.159)

The output current of the differential amplifier will be linearly dependent on the differential input voltage: IOUT ¼ IOUT1 IOUT2 ¼


(1.160)

The circuit presented in Fig. 1.36 [17] is used for linearizing the transfer characteristic of a classical differential amplifier. The difference between gate-source voltages of M1 and M3 transistors can be expressed as follows: VGS1 VGS3 ¼ ðVC þ VIN Þ VC

(1.161)

For a biasing in saturation of all MOS transistors from Fig. 1.36, it results: VIN ¼

rffiffiffiffi 2 pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi

IOUT1 IO K

(1.162)

40


IOUT1

IOUT2 M1

V1 IOUT1 IO

VO -

M2

IO IO

+

+

IO

VO -

IO

V2 IOUT2 IO

Fig. 1.37 Differential structure (5) based on PR 1.3 – principle of operation

So, the expression of I1 current will be: IOUT1 ¼ IO þ

pffiffiffiffiffiffiffiffiffiffi K 2 VIN þ 2KIO VIN 2

(1.163)

Similarly, computing the difference between the gate-source voltages of M2–M3 transistors, it results: IOUT2 ¼ IO þ

pffiffiffiffiffiffiffiffiffiffi K 2 VIN 2KIO VIN 2

(1.164)

The differential output current for the circuit presented in Fig. 1.36 will be: IOUT ¼ IOUT1 IOUT2 ¼

pffiffiffiffiffiffiffiffiffiffi 8KIO VIN

(1.165)

The following presented principle for linearizing the transfer characteristic of a differential structure is based on the constant sum of gate-source voltages, the circuit’s core being represented by a particular implementation of a differential amplifier (Fig. 1.37) [18] that provides a linear behavior of the circuit. For a biasing in saturation of MOS transistors from Fig. 1.37, the V1 V2 differential input voltage can be expressed as follows: V1 V2 ¼ VGS1 VO

(1.166)

V1 V2 ¼ VO VGS2

(1.167)

and:

resulting the expressions of the sum and difference between gate-source voltages: VGS1 þ VGS2 ¼ 2VO

(1.168)


41

and: VGS1 VGS2 ¼ 2ðV1 V2 Þ

(1.169)

The differential output current IOUT is: IOUT ¼ IOUT1 IOUT2 ¼

K K ðVGS1 VT Þ2 ðVGS2 VT Þ2 2 2

(1.170)

equivalent with: IOUT ¼

K ðVGS1 VGS2 ÞðVGS1 þ VGS2 2VT Þ 2

(1.171)

Replacing (1.168) and (1.169) in (1.171), it results a linear transfer characteristic of the differential amplifier presented in Fig. 1.37: IOUT ¼ 2K ðVO VT ÞðV1 V2 Þ

(1.172)

Usually, the VO voltage sources are implemented as current-controlled voltage sources. The simplest way to realize these sources, having the advantages of simplicity, also of minimizing the errors introduced by the bulk effect is to use the gate-source voltage of a MOS transistor in saturation, biased at a constant current, IO : VO ¼ VGSO

rffiffiffiffiffiffiffi 2IO ¼ VT þ K

(1.173)

Replacing these particular expressions of VO voltage sources in the general expression (1.172) of the output current of the differential amplifier, it can be obtained: IOUT ¼


(1.174)

pffiffiffiffiffiffiffiffiffiffi so, an equivalent transconductance of the differential amplifier Gm ¼ 8KIO that can be very easily controlled by the biasing current, IO . A similar linearization technique is used for the circuit shown in Fig. 1.38 [19]. The VO voltage sources from Fig. 1.37 are implemented in Fig. 1.38 using the gate-source voltages of M3 and M4 transistors, biased at constant current, IO . Considering a biasing in saturation of MOS transistors, the output differential current IOUT can be expressed using (1.172) and (1.174): IOUT ¼ 2K ðV1 V2 ÞðVO VT Þ ¼


(1.175)

42


VDD

IO IOUT1

IOUT2 M1

V1

IO

IOUT

M2

M3

M4

V2

Fig. 1.38 Differential structure (5) based on PR 1.3 – first implementation

The equivalent transconductance of the structure is: Gm ¼

pffiffiffiffiffiffiffiffiffiffi IOUT ¼ 8KIO V1 V2

(1.176)

In Fig. 1.39 [19], the VO voltage sources from Fig. 1.37 are realized as currentcontrolled voltage sources, the gate-source voltages of M3 and M5 transistors being dependent on the IO biasing current. Similarly with the previous circuits, the IOUT output differential current can be expressed as: IOUT ¼ IOUT1 IOUT2 ¼ 2K ðV1 V2 ÞðVO VT Þ ¼


(1.177)

The equivalent transconductance of the structure is: Gm ¼

pffiffiffiffiffiffiffiffiffiffi IOUT ¼ 8KIO V1 V2

(1.178)

A differential amplifier with linear transfer characteristic based on the same mathematical principle can be designed (Fig. 1.40) [20] using two translinear loops implemented using M1, M3, M8, M7 and M5, M6, M4, M2 transistors, respectively. Using the notation VGS ðIÞ for the absolute value of the gate-source voltage of a MOS transistor biased at a drain current equal with I, it is possible to write: rffiffiffiffi 2 pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi

V1 V2 ¼ 2VGS ðIO Þ 2VGS ðIOUT1 Þ ¼ 2 IO IOUT1 K

(1.179)


43

VDD M7 IOUT1 M1

V1

M8 IO

IO

IO

IOUT2 M5

M3

M2

V2

VO

VO I O + I1

IO + I2

M4

M6

-VDD Fig. 1.39 Differential structure (5) based on PR 1.3 – second implementation

VDD IO

IO M3

V1

M1

M8

M6

M5

M7

M4

V2

M2 IOUT2

IOUT1

Fig. 1.40 Differential structure (5) based on PR 1.3 – third implementation

and: rffiffiffiffi 2 pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi

IOUT2 IO K

V1 V2 ¼ 2VGS ðIOUT2 Þ 2VGS ðIO Þ ¼ 2

(1.180)

It results: pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi V1 V2 IOUT1 ¼ IO 2

rffiffiffiffi K 2

(1.181)

44


VDD

IOUT2

IOUT1 M3

M1

V1

M4

M2

V2

I I’ M5

VC

M6

Fig. 1.41 Differential structure (5) based on PR 1.3 – third implementation (improved version)

and: pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi V1 V2 IOUT2 ¼ IO þ 2

rffiffiffiffi K 2

(1.182)

So: pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffi IOUT1 þ IOUT2 ¼ 2 IO

(1.183)

and: pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi IOUT2 IOUT1 ¼ ðV1 V2 Þ

rffiffiffiffi K 2

(1.184)

The differential output current will have the following expression: pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi

IOUT2 IOUT1 IOUT2 þ IOUT1 IOUT2 IOUT1 ¼ pffiffiffiffiffiffiffiffiffiffi ¼ 2KIO ðV1 V2 Þ ¼ Gm ðV1 V2 Þ

ð1:185Þ

The equivalent transconductance of the differential amplifier is: Gm ¼


(1.186)

The principle of operation of the differential amplifier presented in Fig. 1.41 [21] is similar with the general principle described for the previous circuit. The VO voltage


45

VDD

IOUT2

IOUT1 M3’ 4K M3’ 4K

M1

V1

I

M4’ 4K M4’’ 4K

M2

V2

I’ VC M5

M6

Fig. 1.42 Differential structure (5) based on PR 1.3 – fourth implementation

sources from Fig. 1.37 are implemented in Fig. 1.41 using the gate-source voltages of M3 and M4 transistors. Because, from the current equations, I ¼ I 0 ¼ 0, the M3–M6 transistors will be biased at the same drain currents, imposed by the VC potential. Since they are identical, their gate-source voltages will be equal, so VO ¼ VGS3 ¼ VGS4 ¼ VC . Using the general relation (1.172), the differential output current can be expressed as follows: IOUT ¼ IOUT1 IOUT2 ¼ 2K ðVC VT Þ ðV1 V2 Þ

(1.187)

the equivalent transconductance being: Gm ¼ 2K ðVC VT Þ

(1.188)

In order to avoid the dependence of the equivalent transconductance on threshold voltage, the M3 and M4 transistors from Fig. 1.41 have been replaced in Fig. 1.42 [21] with two series-connected MOS transistors, M3’–M3” and M4’–M4”. The voltage sources VO will have the following expression: 0

VO ¼ VGS3 þ VGS3

00

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffi! 2ID5 2 K ¼ 2VT þ ¼ 2 VT þ ðVC VT Þ2 ¼ VC þ VT 4K K 2 (1.189)

Replacing (1.189) in (1.172), it results: IOUT ¼ 2KVC ðV1 V2 Þ

(1.190)

46

1 Differential Structures VDD M5a

M6a K

IOUT1

IOUT1 M1a

V1

M10a

M6b K

IOUT2

IOUT2

M2b

M1b

IO M8a V C

V2 B

I’

2IOUT1

M5b

IO2

IO1

I 2IOUT1

M9a

M3a M3b

M2a

A IOUT1

M7b 2K

M7a 2K

IO M11a

2IOUT2

2IOUT2

M11b M8b

IOUT2 M9b

M10b

Fig. 1.43 Differential structure (5) based on PR 1.3 – fourth implementation (improved version)

So, the equivalent transconductance, Gm ¼ 2KVC will be not dependent on the threshold voltage and VC voltage can control it. Another realization of a differential amplifier with linear behavior based on the third mathematical principle is presented in Fig. 1.43 [22]. The M1 and M2 transistors from Fig. 1.37 have been replaced in Fig. 1.43 by two seriesconnected transistors, M1a–M2a and M1b–M2b, while the voltage sources VO from Fig. 1.37 have been practically implemented in Fig. 1.43 by the gate-source voltages of M3a and M3b transistors. The current equations impose I ¼ I 0 ¼ 0, so IO1 ¼ IO2 ¼ IO . Because M3a, M3b, M11a and M11b transistors are identical and biased at the same current, their gate-source voltages will be identical, so VO ¼ VGS3a ¼ VGS3b ¼ VC . Using (1.172), it can be obtained: IOUT ¼ IOUT1 IOUT2 ¼ 2K ðVC VT Þ ðV1 V2 Þ

(1.191)

The equivalent transconductance is: Gm ¼ 2K ðVC VT Þ

(1.192)

The replacing of M3a and M3b transistors with two series-connected MOS transistors, M3a’–M3a” and M3b’–M3b” (Fig. 1.44) [21, 22], allows to remove the dependence of the circuit equivalent transconductance on the threshold voltage: Gm ¼ 2KVC

(1.193)

The advantage of the circuits presented in Figs. 1.43 and 1.44 with respect to the circuits shown in Figs. 1.41 and 1.42 consists in the availability of the output currents IOUT1 and IOUT2 as external currents, being possible to process them


47 VDD

IOUT1

IOUT1

IOUT2

V1 I

A IOUT1

2IOUT1

2IOUT1

M3a’ 4K

M3b’ 4K

M3a’’ 4K

M3b” 4K

IO

IOUT2

V2 B

I’ IO

2IOUT2 2I OUT2

IOUT2

VC


V DD M9

M10 M5

M3

IOUT V1

M1 IOUT1

M8

M7

M6

M4 IO

IO

M2

V2

IOUT2 M11

M12


in order to implement other classes of circuits (active resistors, multipliers or multifunctional structures). A differential amplifier with linear behavior obtained using the same mathematical principle is presented in Fig. 1.45, the NMOS transistors being replaced by complementary PMOS active devices. The VO voltage sources from Fig. 1.37 are practically implemented in Fig. 1.45 [23] using the source-gate voltages of M4 and M6 transistors, biased at constant current IO . VO ¼ VSG4 ¼ VSG6

rffiffiffiffiffiffiffi 2IO ¼ VT þ K

(1.194)

48

1 Differential Structures VDD M7

M9

V1

VO

M10

M8

M17

M25

M23

VO

M18

M11

V2

M12

IOUT

M13 M14 M20

VC

M21 M33 M34

M16

M15

M22

M24


Fig. 1.47 Differential structure (8) based on PR 1.3 – principle of operation

IO + IOUT1

IO + IOUT2 + IO V1

-

-

VO M13

VO

+ IO V2

M14

IO

IO IOUT2

IOUT1

CM

IOUT

Using the general relation (1.172), the differential output current can be expressed as follows: pffiffiffiffiffiffiffiffiffiffi IOUT2 IOUT1 ¼ 2K ðVO VT ÞðV1 V2 Þ ¼ 2 2KIO ðV1 V2 Þ

(1.195)

resulting an equivalent transconductance of the entire structure, given by: Gm ¼ 2


(1.196)

A similar method based on the constant sum of gate-source voltages is used in Fig. 1.46 [23]. The principle diagram, equivalent with the previous circuit is presented in Fig. 1.47.


49

The core of the differential amplifier is represented by the M13 and M14 transistors, while the VO current-controlled voltage sources are implemented using M11 and M12 transistors, biased at a current imposed by M15 and M16 transistors (having the gate-source voltages determined by the VC control voltage). The current mirror from Fig. 1.47 is implemented in Fig. 1.46 using M34–M22, M33–M24 and M23–M25 pairs, with the goal of realizing the difference of the drain currents of M13 and M14 transistors. For the circuit presented in Fig. 1.47, the differential input voltage can be expressed as follows: V1 V2 ¼ VSG14 VO

(1.197)

V1 V2 ¼ VO VSG13

(1.198)

VSG14 VSG13 ¼ 2ðV1 V2 Þ

(1.199)

VSG14 þ VSG13 ¼ 2VO

(1.200)

and:

resulting:

and:

The differential output current for the circuit presented in Fig. 1.47 will be: IOUT2 IOUT1 ¼ ¼

K K ðVSG14 VT Þ2 ðVSG13 VT Þ2 2 2

K ðVSG14 VSG13 ÞðVSG13 þ VSG14 2VT Þ 2

ð1:201Þ

Replacing (1.199) and (1.200) in (1.201), it results: IOUT2 IOUT1 ¼ 2K ðV1 V2 ÞðVO VT Þ

(1.202)

For the complete circuit presented in Fig. 1.46, the VO voltage sources will have the following relations: VO ¼ VSG11 ¼ VSG12 ¼ VGS15 ¼ VGS16 ¼ VC

(1.203)

Because M11, M12, M15 and M16 transistors are identical and they work at the same drain current, it results: IOUT2 IOUT1 ¼ 2K ðV1 V2 Þ ðVC VT Þ

(1.204)

50


M11’ M11

M12’ M12

M11’’

M12’’

Fig. 1.48 Improving method for the differential structure (8) based on PR 1.3

so, an equivalent transconductance of the circuit expressed by: Gm ¼ 2K ðVC VT Þ

(1.205)

The disadvantage of the circuit is represented by the dependence of its equivalent transconductance on the threshold voltage, concretized in the existance of errors introduced by the bulk effect. In order to avoid this aspect, M11 and M12 transistors from Fig. 1.46 must be replaced (Fig. 1.48) with two series connections of two transistors, M11’–M11’ and M12’–M12”, respectively, each of them having K 0 ¼ K 00 ¼ 4K. For this new configuration, the expression of VO becomes: VO ¼ VSG11 0 þ VSG11 00 ¼ 2VSG11 0 rffiffiffiffiffiffiffiffiffiffiffiffi! rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ID11 0 2 K ðVC VT Þ2 VO ¼ 2 VT þ ¼ 2VT þ 4K K 2

(1.206)

(1.207)

resulting: VO ¼ V C þ VT

(1.208)

In this case, the circuit equivalent transconductance becomes independent on the threshold voltage: Gm ¼ 2KVC

(1.209)

A differential amplifier with linear behavior, having a similar principle of operation is presented in Fig. 1.49 (M5, M6, M12 and M13 transistors have the parameter K fourth time greater than the other circuit’s transistors). The M1 and M2 transistors form the differential input stage, excited by the differential input voltage V1 V2 , while M1 and M2 transistors, together with the current mirrors M17–M18 and M19–M20, mirror the output currents from the differential amplifier (IOUT1 and IOUT2 ) for obtaining the differential output current IOUT . The VO voltage sources


51 VDD M20

M19

IOUT2 IOUT IOUT1 V1

IOUT1

M17

M18 M8

M9

IOUT

M14

IOUT2 M2

M1 M16 M11

M3

VC1

M7

M5

M12

M6

M13

M10

V2

M4

M15

VC2 -VDD


from Fig. 1.37 are implemented in Fig. 1.49 using M5–M6 and M12–M13 pairs, biased at a constant current. This current is imposed using M8–M9–M14 current mirror by M7 transistor, having the gate-source voltage determined by VC1 control potential. The voltage VO can be expressed as follows: rffiffiffiffiffiffiffiffiffi! 2ID5 VO ¼ VGS5 þ VGS6 ¼ 2 VT þ 4K rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 K ¼ 2VT þ ðVC1 VT Þ2 ¼ VC1 þ VT K 2

ð1:210Þ

So, using relation (1.172), it results: Gm ¼ 2KVC1 :

(1.211)

The advantage of the circuit consists in the possibility of controlling Gm transconductance by VC1 potential, as well as the independence of the equivalent transconductance on the bulk effect. A differential amplifier with linear behavior based on a translinear loop is presented in Fig. 1.50 [24]. The translinear loop containing M2, M3, M4 and M7 transistors has the following characteristic equation: rffiffiffiffi 2 pffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi

IO IOUT1 K

V1 V2 ¼ 2VGS ðIO Þ 2VGS ðIOUT1 Þ ¼ 2

(1.212)

52


VDD M7

V1

M1

M2

M8

M3

M6

M4 IO

V2

I1

M5 I2

IO


resulting: IOUT1

K ¼ IO þ ðV1 V2 Þ2 8

rffiffiffiffiffiffiffiffi KIO ðV1 V 2 Þ 2

(1.213)

Similarly, analyzing the translinear loop containing M1, M5, M6 and M8 transistors, it results: IOUT2 ¼ IO þ

K ðV1 V2 Þ2 þ 8

rffiffiffiffiffiffiffiffi KIO ðV1 V 2 Þ 2

(1.214)

The differential output current of the circuit presented in Fig. 1.50 will have the following expression: IOUT2 IOUT1 ¼


(1.215)

A linearization technique [25] using the third mathematical principle (PR 1.3), based on the utilization of translation blocks for realizing DC shifting of input potentials has the block diagram presented in Fig. 1.51 [25]. The “DA” block represents a classical active-load differential amplifier, having the common-sources point biased at a potential V fixed by the circuit “M”. This circuit computes the arithmetical mean of input potentials, providing a very good linearity of the entire structure, with the contribution of “T” blocks (which are used for introducing a translation of input potentials).


53

M

V1 IO

T

V2

V V1T

DA

IO

T V2T

IOUT Fig. 1.51 Differential structure (11) based on PR 1.3 – block diagram

V

Fig. 1.52 Differential structure (11) based on PR 1.3 – DA block implementation

V1T

M1 IOUT1

IOUT2 IOUT

M3

1.2.3.1

V2T

M2

M4

The “DA” (Differential Amplifier) Block

The “DA” block is implemented as a classical active-load differential amplifier, having the concrete realization presented in Fig. 1.52 [25–27]. Considering a biasing in saturation of all MOS devices from Fig. 1.52, the output current of the differential amplifier can be expressed as: IOUT ¼

K ðV1T V2T Þ ð2V V1T V2T 2VT Þ 2

(1.216)

In order to obtain a linear transfer characteristic IOUT ðV1T V2T Þ, it is necessary that the second parenthesis from (1.216) to be constant with respect to the differential input voltage, V1T V2T : 2V V1T V2T 2VT ¼ A ¼ ct:

(1.217)

54


Fig. 1.53 Differential structure (11) based on PR 1.3 – T block implementation

IO

IO V1

M9

M9’

V1T

V2

V2T

resulting the necessity of implementing a V voltage equal with: V¼

1.2.3.2

V1T þ V2T A þ VT þ 2 2

(1.218)

The “T” (Translation) Block

The translation of the V potential with VT þ A=2 (relation (1.218)) can be obtained using the “T” block, having the implementation presented in Fig. 1.53. Because the same IO current is passing through transistors from Fig. 1.53, it is possible to write that: V1 ¼ V1T

rffiffiffiffiffiffiffi 2IO þ VT þ K

(1.219)

and: V2 ¼ V2T


(1.220)

So, both input potentials V1 and V2 are DC shifted with the same amount, pffiffiffiffiffiffiffiffiffiffiffiffiffi VT þ 2IO =K .

1.2.3.3

The “M” (Arithmetic Mean) Block

In order to obtain the arithmetic mean of input potentials expressed by (1.221) relation, the circuit from Fig. 1.54 [25] can be used, having the advantages of using only MOS transistors biased in saturation region and of avoiding any current consumption from the input voltage sources, V1 and V2 .


IO /2 V1

IO /2

M15

M14

55

M15’

IO

M14’

V2

IO V

Fig. 1.54 Differential structure (11) based on PR 1.3 – M block implementation

The M14–M15 and M14’–M15’ differential amplifiers are biased at the same current, IO and, additionally, the sum of drain currents of M15 and M15’ transistors are, also, equal with IO . As a result, gate-source voltages of M14 and M15’ transistors are equal and, similarly, gate-source voltages of M14’ and M15 transistors are equal. In order to obtain the expression of V voltage, it can write that V1 V ¼ VGS14 VGS15 and V V2 ¼ VGS15 0 VGS14 0 . Subtracting these two relations and using the previous observations, V potential will represent the arithmetical mean of V1 and V2 input potentials: V¼

V1 þ V2 2

(1.221)

So: V1T þ V2T þ VT þ V¼ 2

rffiffiffiffiffiffiffi 2IO K

(1.222)

pffiffiffiffiffiffiffiffiffiffiffiffiffi Comparing (1.218) and (1.212) relations, it results that A ¼ 2 2IO =K , so: IOUT ¼

K ðV1T V2T Þ2 2

rffiffiffiffiffiffiffi 2IO pffiffiffiffiffiffiffiffiffiffi ¼ 2KIO ðV1T V2T Þ K

(1.223)

equivalent (using (1.219) and (1.220)) with: IOUT ¼

pffiffiffiffiffiffiffiffiffiffi 2KIO ðV1 V2 Þ ¼ Gm ðV1 V2 Þ

(1.224)

pffiffiffiffiffiffiffiffiffiffi Gm ¼ 2KIO being the equivalent transconductance of the differential amplifier. In conclusion, a linear transfer characteristic of the differential structure having the block diagram presented in Fig. 1.51 is obtained by using a proper voltage biasing of the classical differential amplifier from Fig. 1.52. The full implementation of the linearized differential structure is presented in Fig. 1.55. An equivalent structure, obtained by replacing the “DA” block from Fig. 1.51 with a complementary circuit is presented in Fig. 1.56 [25].

56

1 Differential Structures VDD M11

M12 M13’

M13

M10 IO/2

“T”

M14

M9

V1

M11’

M12’

“M”

M10’ IO/2 M15’

M15

“T”

M14’

M9’

V2

0 2IOUT1

M16

2IOUT2

IO

V

IOUT2

IOUT1

V1T IO

IO

M1 M5

IO M4

M5’

IOUT1 IOUT2 IOUT

M3

M3’

M2’M8’

M8 M2

M6

V2T

M2

IO M4’ M6’

“DA” Fig. 1.55 Differential structure (11) based on PR 1.3 – complete implementation

VDD V2

K V2T

VC

4K

K

IOUT IOUT2

V1

V1T IOUT2 IOUT1

V

4K IOUT1

VC

IOUT2 2IOUT1 4K

4K

V1

V2 V

Fig. 1.56 Differential structure (11) based on PR 1.3 – alternate complete implementation

1.2 Analysis and Design of Differential Structures Fig. 1.57 Differential structure (12) based on PR 1.3 – block diagram

57

IOUT

V1

V2

DA V

T

VC

V’

M A similar behavior can be obtained based on the block diagram presented in Fig. 1.57, using another structure for replacing the block diagram from Fig. 1.51. The full implementation of the differential amplifier using this architecture is shown in Fig. 1.58. A differential amplifier with linear transfer characteristic using FGMOS transistors is presented in Fig. 1.59 [28]. Considering that FGMOS transistors from Fig. 1.59 have different inputs, the expressions of their drain currents will be: IOUT1

IOUT2

2 K V1 þ VPOL1 V VT ¼ 2 2 2 K V2 þ VPOL2 ¼ V VT 2 2

(1.225)

(1.226)

and: 2 K V1 þ V2 þ 2VPOL3 V VT IO ¼ 4 2

(1.227)

Replacing in (1.225) and (1.226) the expression of V potential, expressed from (1.227), it results:

IOUT1

K V1 V2 þ 2VPOL1 2VPOL3 þ ¼ 2 4

rffiffiffiffiffiffiffi!2 2IO K

(1.228)

58

1 Differential Structures VDD IOUT IOUT1IOUT2

IOUT2 V2

V1 IOUT1 IOUT1

2IOUT2

IOUT2

V

V’=(V1 + V2)/2

4K

V2

V1

4K

VC

K


and:

IOUT2

K V2 V1 þ 2VPOL2 2VPOL3 þ ¼ 4 2


(1.229)

The differential output current of the circuit presented in Fig. 1.59 will have the following expression: K V1 V2 VPOL1 VPOL2 þ IOUT1 IOUT2 ¼ 2 2 2 rffiffiffiffiffiffiffi! VPOL1 þ VPOL2 2IO VPOL3 þ 2 2 K

ð1:230Þ

In order to obtain a linear differential amplifier, the structure must be symmetrical, so VPOL1 ¼ VPOL2 , resulting: IOUT1 IOUT2

rffiffiffiffiffiffiffi! K 2IO ¼ ðV1 V2 Þ VPOL1 VPOL3 þ 2 K 4

(1.231)


59

VDD IO IOUT1

IOUT2 VPOL2 V2

VPOL3 1

M2

1

1 1/2 1/2

M3

M1

1 1

V

VPOL1 V1


VDD VC

M3

M4 IOUT2

IOUT1

M6

M5 VB - V1/2

M1

M7

M8

M2

VB + V1/2

V I

Fig. 1.60 Differential structure based on PR 1.4

1.2.4

Differential Structures Based on the Fourth Mathematical Principle (PR 1.4)

A possible illustration of the utilization of fourth mathematical principle (PR 1.4) for linearizing the transfer characteristic of a differential structure is presented in Fig. 1.60 [29]. The symmetrical structure is responsible for an important improvement of the circuit accuracy.

60


Fig. 1.61 Differential structure based on PR 1.4 – symbolic representation

IOUT2

IOUT1

VB - V1/2

DA

VB + V1/2

VC

The expression of IOUT1 output current is: K K ðVGS5 VT Þ2 þ ðVGS8 VT Þ2 2 2

(1.232)

K K ðVC VGS3 VT Þ2 þ ðVGS8 VT Þ2 2 2

(1.233)

IOUT1 ¼ which is equivalent with: IOUT1 ¼

Because M1 and M3 transistors are identical and they are biased at the same drain current, their gate-source voltages will be equal, so: IOUT1 ¼

K K ðVC VGS1 VT Þ2 þ ðVGS8 VT Þ2 2 2

(1.234)

or: IOUT1 ¼

K V1 2 K V1 2 þ VC VB þ V VT þ VB V VT þ 2 2 2 2

(1.235)

Similarly, the second output current, IOUT2 , will have the following expression: IOUT2 ¼

K V1 2 K V1 2 þ VC VB þ V VT VB V VT 2 2 2 2

(1.236)

The differential output current can be expressed as follows: IOUT1 IOUT2 ¼ KV1 ðVC VB þ V VT Þ þ KV1 ðVB V VT Þ ¼ K ðVC 2VT Þ V1 The symbolic representation of the circuit is shown in Fig. 1.61.

ð1:237Þ

1.2 Analysis and Design of Differential Structures Fig. 1.62 Classical MOS differential structure

61

I1

I2

V1

V2

IO’

1.2.5

Differential Structures Based on the Fifth Mathematical Principle (PR 1.5)

The method for obtaining a linear behavior of the differential amplifier using the fifth mathematical principle (PR 1.5) is based on a proper biasing of the structure at a current that is dependent on the differential input voltage. The analysis of the classical differential amplifier (Fig. 1.62) using MOS transistors biased in saturation region illustrates a strongly nonlinear behavior, that can be quantitatively evaluated by the (1.14) dependence of IOUT differential output current on the differential input voltage, VI ¼ V1 V2 .

IOUT

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi KðV1 V2 Þ2 K 2 ðV1 V2 Þ4 ¼ I1 I2 ¼ IO 0 IO 0 4IO 02

(1.238)


V1 V2 2

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 4KIO 0 K 2 ðV1 V2 Þ2

(1.239)

IO 0 being the biasing current of the differential structure. So, superior-order distortions will characterize the behavior of the classical differential structure, imposing the design of a linearization technique for removing the superior-order terms from its transfer characteristic. The method [30] for obtaining a linear transfer characteristic of the differential amplifier, despite the quadratic law of its composing devices (Fig. 1.63) [30], is to obtain the IO 0 biasing current of the entire differential structure as a sum of a main constant term, IO and an additional term, proportional with the square of the differential input voltage, I ¼ KðV1 V2 Þ2 =4: IO 0 ¼ IO þ I ¼ IO þ

K ðV1 V2 Þ2 4

(1.240)

62


Fig. 1.63 Differential structure based on PR 1.5

IOUT1

IOUT2

V1

V2 I O’ i1

I

IO

SQ

resulting, in this case, a perfect linear behavior of the differential amplifier: IOUT ¼

pffiffiffiffiffiffiffiffi KIO ðV1 V2 Þ ¼ Gm ðV1 V2 Þ

(1.241)

pffiffiffiffiffiffiffiffi Gm ¼ KIO being the equivalent transconductance of the structure, that could be very easily controlled by the biasing current, IO . The circuit implementation is relatively simple, allowing to implement, by minor changes of the design, a multitude of circuit functions (multiplying, amplifying and simulating a positive or negative equivalent resistance). In order to implement (1.240) relation, it is necessary to design a CMOS structure able to compute the square of the V1 V2 differential input voltage. A possible implementation of this circuit uses the arithmetical mean of the input potentials (Fig. 1.64) [6]. K K I ¼ I1 þ I2 I3 ¼ ðV1 VT Þ2 þ ðV2 VT Þ2 2 2 2 V1 þ V2 K VT ¼ ðV1 V2 Þ2 K 2 4

1.2.6

ð1:242Þ

Differential Structures Based on the Sixth Mathematical Principle (PR 1.6)

The general linearization technique based on the sixth mathematical principle (PR 1.6) achieves the minimization of superior-order distortions using an antiparallel connection of two or more differential amplifiers having controlled asymmetries and different controlled biasing currents. Using (1.20), the expression


63

VDD

IREF V

V1

V2

VDD I I3

I2

I1 K

2K

K

Fig. 1.64 Squaring circuit for the differential structure based on PR 1.5

of the differential output current for the classical differential amplifier from Fig. 1.62 [31] will be: 1=2

IOUT ðVI Þ ¼ K 1=2 IO VI þ

K 3=2 1=2 8IO

VI3 þ

K 5=2 3=2 128IO

VI5 þ

(1.243)

As a consequence of the circuit symmetry, the even order terms from the previous expansion have been cancel out: IOUT ðVI Þ ¼ a1 VI þ a3 VI3 þ a5 VI5 þ

(1.244)

ak being constant coefficients of the expansion. For simplicity, IO 0 biasing current from Fig. 1.62 has been renamed IO . The total harmonic distortions of the classical differential amplifier are mainly given by the third-order term from the previous expansion: THD ¼

a3 VI3 K 2 ¼ V a1 VI IO I

(1.245)

64


IOUT2

IOUT1

M1

M3

M2

M4

VI

IO1

IO2

- VDD Fig. 1.65 Differential structure (1) based on PR 1.6

The first linear term is proportional with the differential-mode voltage gain of the differential amplifier, while the following two terms model the third-order and the fifth-order nonlinearities of the transfer characteristic. The most important cause of the distortions introduced by the circuit nonlinearity is the third-order term from the previous expansion. The method for improving the circuit linearity uses an anti-parallel connection of two differential amplifiers with controlled asymmetries and different controlled biasing currents (M1–M2 and M3–M4 pairs from Fig. 1.65) [13, 31]. Because M1–M2 differential amplifier is biased at IO1 current and M3–M4 structure is biased at IO2 current, the differential output currents for these circuits are: 3=2

ðID2 ID1 Þ ðVI Þ ¼

1=2 1=2 K1;2 IO1 VI

þ

K1;2

V3 1=2 I 8IO1

5=2

þ

K1;2

3=2

128IO1

VI5 þ

(1.246)

VI5 þ

(1.247)

and: 3=2

1=2 1=2

ðID4 ID3 Þ ðVI Þ ¼ K3;4 IO2 VI þ

5=2

K3;4

K3;4

8IO2

128IO2

V3 þ 1=2 I

3=2


65

The differential output current for the entire anti-parallel structure from Fig. 1.65 will have the following expression: IOUT2 IOUT1 ¼ ðID2 þ ID3 Þ ðID1 þ ID4 Þ ¼ ðID2 ID1 Þ ðID4 ID3 Þ

ð1:248Þ

Replacing (1.257) and (1.258) in (1.259), it results:

þ

1=2 1=2 1=2 1=2 IOUT2 IOUT1 ¼ K3;4 IO2 K1;2 IO1 VI ! ! 3=2 3=2 5=2 5=2 K1;2 K3;4 K1;2 K3;4 3 1=2 VI þ VI5 þ 1=2 3=2 3=2 8IO1 8IO2 128IO1 128IO2

ð1:249Þ

The linearization technique is considered to be efficient if it is able to cancel the third-order distortion, so the condition that must be fulfilled by the design is: 3=2

K1;2

1=2

8IO1

3=2

¼

K3;4

(1.250)

1=2

8IO2

equivalent with: IO1 ¼ IO2

K1;2 K3;4

3 (1.251)

Imposing this condition for obtaining the minimization of the circuit nonlinearity, the main distortions will be caused by the fifth-order term from the circuit transfer characteristic. Using (1.251), relation (1.249) becomes: " IOUT2 IOUT1 ¼ "

5=2

K1;2

5=2

128IO1

1=2 1=2 K1;2 IO1

2=3 # IO2 VI 1 IO1 #

2=3 IO1 VI5 þ 1 IO2

ð1:252Þ

The total harmonic distortions of the improved linearity differential amplifier from Fig. 1.65 are mainly given by the fifth-order term from the previous expansion: VI4 K1;2 2 IO1 2=3 THD ¼ 128 IO1 IO2 0

(1.253)

resulting an important increasing of the circuit linearity (THD0 is much smaller than THD).

66

VI


M1

M2

M3

M4

IO4

IO3

IO2

IO1

M4’

M3’

M2'

M1’

IOUT2

IOUT1


In order to further increase the differential amplifier linearity, the previous technique can be extended for removing both third-order and fifth-order terms from the Taylor series expansion (1.249). This is possible using a parallel connection of four differential amplifiers, having controlled asymmetries and controlled different biasing (Fig. 1.66). Similarly with the circuit presented in Fig. 1.65, the conditions for canceling the third-order and the fifth-order distortions are: K2 ¼ K3 K1 ¼ K2

IO2 IO3 IO1 IO2

1 3

;

K1 ¼ K4

;

K3 ¼ K4

3 5

IO1 IO4 IO3 IO4

1 3

(1.254)

3 5

(1.255)

K1 –K4 being model parameters for M1–M1’, M2–M2’, M3–M3’ and M4–M4’ pairs, respectively. The total harmonic distortions of the circuit presented in Fig. 1.66 are mainly given by the fifth-order term from the Taylor series expansion of the transfer characteristic: 7=2 5=2 7=2 5=2 IO3 IO4 K4 3 1 KK32 1 IO2 K3 IO3 1 K 2 6 THD00 ffi 15 VID

1=2 (1.256) 1=2 1=2 1=2 2 IO2 IO3 IO4 K4 1 1 KK32 IO2 K3 IO3 resulting an important improvement of the circuit linearity by applying this technique. An alternate implementation [32] of the previous linearization technique can be obtained using differential amplifiers based on MOS transistors working in weak inversion region (Fig. 1.67) [32]. This implementation of the differential amplifier circuit allows to obtain an important reduction of the current consumption, the structure being useful for low-power designs. The drive of these transistors is also realized on their gates and bulks. The utilization of the bulk as active terminal


67

VDD

IOUT IOUT1

IOUT2

AaVI AbVI M1a

M1b

M2b

M2a

VI

IO1

IO2

-VDD Fig. 1.67 Differential structure (3) based on PR 1.6

avoids the utilization of large aspect ratios MOS transistors. Aa and Ab represent the voltage gains used for computing the voltage drives of the bulks. The drain currents of MOS transistors composing the M1a–M2a differential amplifier from Fig. 1.67 have the following expressions: ID1;2a ¼

I Oa VGS1a VGS2a n 1 VBS1a VBS2a exp 1 þ exp n nVth Vth IOa ¼ (1.257) VI 1 þ exp Ka Vth

Similarly, for the second differential amplifier, M1b–M2b, the drain currents can be expressed as follows: ID1;2b ¼

I Ob VGS1b VGS2b n 1 VBS1b VBS2b exp 1 þ exp nVth Vth n IOb (1.258) ¼ VI 1 þ exp Kb Vth

68


where Ka ¼ ½1 þ ðn 1ÞAa =n and Kb ¼ ½1 þ ðn 1ÞAb =n. For evaluating the circuit linearity, it is necessary to expand in Taylor series the following mathematical function: f ðxÞ ¼

1 1 x x3 x5 þ ffi þ 1 þ expðxÞ 2 4 48 480

(1.259)

Using this fifth-order limited Taylor series expansion, the drain currents of the M1a–M2a and M1b–M2b differential pairs from Fig. 1.67 will be: ID1;2a

" # 1 Ka VI 1 VI 3 1 VI 5 Ka Ka ¼ IOa 2 4 Vth 48 480 Vth Vth

(1.260)

and: ID1;2b

" # 3 5 1 Kb VI 1 VI 1 VI ¼ IOb Kb Kb Vth Vth 2 4 Vth 48 480

(1.261)

The differential output current of the entire anti-parallel structure is: IOUT ¼ IOUT2 IOUT1 ¼ ðID1a þ ID2b Þ ðID1b þ ID2a Þ Kb IOb Ka IOa VI ¼ ðID1a ID2a Þ ðID1b ID2b Þ ¼ 2Vth K 3 IOa Kb3 IOb 3 Kb5 IOb Ka5 IOa 5 þ a VI þ VI þ 24Vth3 240Vth5

ð1:262Þ

The condition for cancellation of the third-order distortions introduced by the circuit is: Ka ¼ Kb

rffiffiffiffiffiffi 1 þ ðn 1ÞAa 3 IOb ¼ IOa 1 þ ðn 1ÞAb

(1.263)

resulting the following expression of the IOUT output current: IOUT ffi a1 VI þ a5 VI5 þ

(1.264)

where a1 and a5 constants are given by: Ka IOa a1 ¼ 2Vth

"

IOb IOa

#

2=3 1

(1.265)


Ka5 a5 ¼ IOa 240Vth5

" # IOb 2=3 1 IOa

69

(1.266)

The total harmonic distortion coefficient for the linearized circuit will have the following expression: THD ¼

1.2.7

1 Ka VI 4 1 þ ðn 1ÞAb 2 1 þ ðn 1ÞAa 120 nVth

(1.267)

Differential Structures Based on the Seventh Mathematical Principle (PR 1.7)

This principle is useful for obtaining a rail-to-rail operation of a differential structure. The general method for extending the maximal range of the commonmode input voltage is to use a parallel connection of two complementary (NMOS and PMOS) differential amplifiers. The simple parallel connection of these stages has the disadvantage of a variable value of the equivalent transconductance for the resulted structure, while the utilization of a translinear loop or of a “maximum” circuit permits to obtain an approximately constant value of the equivalent transconductance, only slightly dependent on the value of the common-mode input voltage (R1 ¼ R2 ¼ R3 ¼ R4 ). A possible method for obtaining a rail-to-rail operation of a differential structure, using two parallel-connected complementary differential amplifiers is presented in Fig. 1.68. The NMOS differential amplifier is realized using M1–M4 transistors, while the PMOS differential circuit is implemented using M5–M8 active devices. Because these differential amplifiers present complementary common-mode input ranges, their parallel connection will extend the equivalent domain of the commonmode input voltage for the entire structure. The DIFF1 and DIFF2 blocks computes the differential output voltages of the complementary differential amplifiers, while the SUM block realizes the summation of these two output voltages. For medium values of the common-mode input voltages, both NMOS and PMOS differential amplifiers are active, so the equivalent transconductance of the parallel-connected structure will be equal with the sum of the individual transconductances, gTm ¼ gmn þ gmp . The maximal range of the common-mode input voltage for the NMOS differential amplifier, M1–M4 is included between the following limits: NMOS VIC max ¼ VDD

IO R1 IO R1 VDS1sat þ VGS1 ¼ VDD þ VT 2 2

(1.268)

70


DIFF 1 + -

R1

R2

M1 R6

M5

R5 IO

IO M3

VI

VC

M2

VDD

M4

R7

M8 IO

A

SUM + +

M6

M7

R3

R4

DIFF 2 +

VO RL


and: NMOS VIC min

¼ VGS1 þ VDS3sat

pffiffiffi

rIffiffiffiffiffi O ¼ VGS1 þ VGS3 VT ¼ VT þ 2þ1 K

(1.269)

while the maximal range of the common-mode input voltage for the PMOS differential amplifier M5–M8 is included between the following limits: PMOS VIC max ¼ VDD VSG6 VSD8sat ¼ VDD VSG6 VSG8 þ VT pffiffiffi

rIffiffiffiffiffi O ¼ VDD VT 2þ1 K

ð1:270Þ

and: PMOS VIC min ¼

IO R3 IO R3 þ VSD6sat VSG6 ¼ VT 2 2

(1.271)


71

NMOS

VICmax Normal operation NMOS DA

VDD PMOS

VICmax

NMOS

VICmin

0

PMOS

VICmin

Normal operation PMOS DA

Fig. 1.69 Diagram for the range of VIC

The maximal range of the common-mode input voltage for the parallel-connection from Fig. 1.68 is determined by superposing the individual common-mode input ranges for the complementary NMOS and PMOS differential pairs (relations (1.268) – (1.271)) – Fig. 1.69. The maximal range of the common-mode input voltage for the parallel connection from Fig. 1.68 must include the supply voltage range, ½0; VDD . From Fig. 1.69, the conditions for obtaining this goal are: NMOS VIC max > VDD

(1.272)

PMOS NMOS VIC max > VIC min

(1.273)

PMOS VIC min < 0

(1.274)

IO R1 < 2VT

(1.275)

equivalent with:

and: "

ffi pffiffiffi

rffiffiffiffi IO 2þ1 VDD > 2 VT þ K

# (1.276)

The common-mode input ranges for the two parallel-connected differential stages are complementary, existing, however, a range of the common-mode input voltage (corresponding to medium values of this voltages), where the range of NMOS differential structure overlaps the range of the PMOS differential stage. Supposing gmn ¼ gmp ¼ gTm , the dependence of the circuit’s total transconductance, gTm , on the common-mode input voltage is synthesized in Table 1.1. The disadvantage of this parallel connection of two complementary differential amplifiers is a value of the equivalent transconductance gTm that depends on the common-mode input voltage.

72


Table 1.1 Equivalent transconductance for the circuit presented in Fig. 1.68 PMOS NMOS NMOS PMOS PMOS NMOS VIC range VIC VIC VIC min < VIC < VIC min min IO2 , the relations between the currents from the circuit are: ID3 ¼ ID4 ¼ ID5 ¼ IO2

(1.279)

ID1 ¼ ID2 ¼ IO1 ID3 ¼ IO1 IO2

(1.280)

IO ¼ ID1 þ ID5 ¼ ðIO1 IO2 Þ þ IO2 ¼ IO1

(1.281)

ID4 ¼ ID5 ¼ IO2

(1.282)

while for IO1 < IO2 :


77

IO2

IO1

IO

M1

M2

M3

M4

M5

Fig. 1.77 The implementation of the “maximum” circuit

Table 1.2 Equivalent transconductance of the circuit presented in Fig. 1.76 PMOS NMOS NMOS PMOS PMOS NMOS VIC range VIC VIC VIC min < VIC < VIC min min < VIC < VIC max max < VIC < VIC max NMOS DA PMOS DA Parallel modified DA

gm gm gm

0 gm gm

ID3 ¼ IO1 ;

gm 0 gm

ID1 ¼ ID2 ¼ 0

IO ¼ ID1 þ ID5 ¼ IO2

(1.283) (1.284)

NMOS PMOS For medium values of the common-mode input voltages, VIC min < VIC < VIC max , the “maximum” circuit will select the maximal transconductance from gmn and gmp , so the equivalent transconductance of the modified parallel circuit from Fig. 1.76 will be approximately constant and independent on the common-mode input voltage the results are centralized in Table 1.2. The circuit presented in Fig. 1.78 [33] is designed with the main goal of obtaining a rail-to-rail operation using a proper biasing of a parallel connection of two complementary classical differential amplifiers, M1–M2 and M3–M4, biased at IOn and IOp currents, respectively. The utilization of a translinear loop, that forces a proper relation between the biasing currents IOn and IOp , has the advantage of obtaining an approximately constant equivalent transconductance of the entire structure. The output current of the circuit can be expressed as follows:

IOUT ¼ ðIn1 In2 Þ þ ðIP1 IP2 Þ ¼ gmn þ gmp ðV1 V2 Þ

(1.285)

where gmn represents the transconductance of M1–M2 NMOS differential amplifier, while gmp is the transconductance of M3–M4 PMOS differential amplifier.

78

1 Differential Structures 1:1:1

1:1

IOp

IO

1:1

IO

IOn

M6 M7

M5

IO

M8

In1 V1

In1 – In2

IOp M1

M4

M3

Ip2

Ip1

IOn

IO

1:1

IOUT

In2 M2

V2

Ip1 – Ip2 1:1

1:1:1


Supposing a biasing in saturation region of M1–M4 transistors, it is possible to write that: gmn ¼

pffiffiffiffiffiffiffiffiffiffiffiffi Kn IOn

(1.286)

gmp ¼

pffiffiffiffiffiffiffiffiffiffiffiffi Kp IOp

(1.287)

and:

Considering that M1–M4 transistors are identical, it results: IOUT ¼

pffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi

K IOp þ IOn ðV1 V2 Þ

(1.288)

The relation between IOn and IOp currents is imposed by the translinear loop implemented using M5–M8 transistors: VGS5 þ VGS7 ¼ VGS6 þ VGS8

(1.289)

Using the square-root dependence of the drain current on the gate-source voltage for a MOS transistor biased in saturation, it results: pffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffi IOn þ IOp ¼ 2 IO

(1.290)

From (1.288) and (1.290), the expression of the output current will be: IOUT ¼ 2

pffiffiffiffiffiffiffiffi KIO ðV1 V2 Þ

(1.291)

The advantage of this circuit consists in the rail-to-rail operation that can be obtained because of the parallel connection of two complementary differential amplifiers (M1–M2 and M3–M4). The utilization of the M5–M8 translinear loop eliminates the main disadvantage of this method (a variable equivalent transconductance of the parallel connection, depending on the common-mode input voltage).


79

VDD

M6 M7

M5 M8 IOUT1

M9 IOUT2 M2

M3

M1

V1

M4

V2

IO M11

M12

M13

M14

Fig. 1.79 The core of DDA

Using the same principle it is possible to design a double differential amplifier (DDA), having an extended range of the common-mode input voltage and an approximately constant equivalent transconductance. The core of the DDA circuit is represented by a differential stage, having the circuit presented in Fig. 1.79 [34]. The differential output current of this circuit can be expressed as follows: IOUT1 IOUT2 ¼

pffiffiffiffiffiffiffiffiffiffi 8KIO ðV1 V2 Þ ¼ gmn ðV1 V2 Þ

(1.292)

In order to extend the maximal range of the common-mode input voltage, a parallel connection of two complementary differential amplifiers are used, the selection of the active one being done using two “maximum” circuits. The differential amplifier with extended common-mode input range and constant equivalent transconductance is presented in Fig. 1.80 [34]. Relation (1.305) can be rewritten for the two complementary differential amplifiers: In1 In2 ¼

pffiffiffiffiffiffiffiffiffiffiffiffi 8Kn IO ðV1 V2 Þ ¼ gmn ðV1 V2 Þ

(1.293)

Ip1 Ip2 ¼

pffiffiffiffiffiffiffiffiffiffiffiffi 8Kp IO ðV1 V2 Þ ¼ gmp ðV1 V2 Þ

(1.294)

and:

80


VDD In2

In1

IOUT V2

V1 IO

VC

VDD

Ip1

Ip2

Fig. 1.80 Differential amplifier with extended common-mode input range

The output current has the following expression: pffiffiffiffiffiffiffiffiffiffiffiffi IOUT ¼ maxðIn1 ; Ip2 Þ maxðIn2 ; IP1 Þ ¼ 8Kn IO ðV1 V2 Þ pffiffiffiffiffiffiffiffiffiffiffiffi ¼ 8Kp IO ðV1 V2 Þ ¼ gTm ðV1 V2 Þ

(1.295)

where gmn ¼ gmp ¼ gTm . The implementation (Fig. 1.81) of the double differential amplifier is based on the previous presented differential stage (Fig. 1.79). The output current of DDA circuit has the following expression: IOUT ¼ maxðIn2 þ I 0n1 ; Ip1 þ I0p2 Þ maxðIn1 þ I 0n2 ; Ip2 þ I0p1 Þ ¼ gTm Vpp Vpn Vnp Vnn

(1.296)

Because of the utilization of the differential amplifier with extended commonmode input range, the equivalent transconductance of the DDA, gTm , will be approximately constant.

1.2.8

Differential Structures Based on Different Mathematical Principle (PR 1.D)

Another possible realization of a DDA is presented in Fig. 1.81 [35], having a relatively simple implementation comparing with the previous designs of similar circuits.


81 VDD IOUT2

IOUT1 V1

VB

V4

V2

VA

VC

VD

V3

VO

Fig. 1.81 DDA based on PR 1.D

The expressions of IA and IB currents are: IOUT1 ¼

K K K K ðV1 VT Þ2 þ ðV4 VT Þ2 þ ðVC VT Þ2 þ ðVB VT Þ2 (1.297) 2 2 2 2

and: IOUT2 ¼

K K K K ðV2 VT Þ2 þ ðV3 VT Þ2 þ ðVA VT Þ2 þ ðVD VT Þ2 (1.298) 2 2 2 2

The differential output current of the DDA circuit will have the following expressions: IOUT1 IOUT2 ¼

K ðV1 VA ÞðV1 þ VA 2VT Þ 2

K ðV4 VD ÞðV4 þ VD 2VT Þ 2 K K þ ðVB V2 ÞðVB þ V2 2VT Þ þ ðVC V3 ÞðVC þ V3 2VT Þ 2 2 þ

(1.299)

Because: VO ¼ V1 VA ¼ V2 VB ¼ V3 VC ¼ V4 VD

(1.300)

it can be obtained: IOUT1 IOUT2 ¼ KVO ½ðV4 V3 Þ ðV2 V1 Þ

(1.301)

82


VDD IO

IO

IOUT2

IOUT1

V1 M1

V2

M2 M3

V3 V4

M4

VA

VB IO + IOUT1

IO + IOUT2

Fig. 1.82 Differential structure (1) based on PR 1.D

A linear transfer characteristic for a differential amplifier can be obtained using the circuit presented in Fig. 1.82 [36], the simplicity recommending it for a multitude of analog signal processing applications. As M1 and M2 transistors from Fig. 1.82 are biased at IO drain currents, VA and VB potentials can be expressed as follows: rffiffiffiffiffiffiffi 2IO VA ¼ V2 VT K

(1.302)

and: rffiffiffiffiffiffiffi 2IO VB ¼ V1 VT K

(1.303)

The expressions of IOUT1 and IOUT2 currents will be: IOUT1 ¼

K ðV3 VA VT Þ2 2

(1.304)

IOUT2 ¼

K ðV4 VB VT Þ2 2

(1.305)

and:

Replacing (1.302) and (1.303) in (1.304) and (1.305), it results:

IOUT1

K ¼ V3 V2 þ 2


(1.306)

1.2 Analysis and Design of Differential Structures Fig. 1.83 Differential structure (2) based on PR 1.D

83

IOUT2

IOUT1 VC1

VC2

V1

V

V2

IO

and:

IOUT2

K V4 V1 þ ¼ 2


(1.307)

The input potentials are chosen to have both common-mode and differentialmode components: V1 ¼ VC Vi1

(1.308)

V2 ¼ VC þ Vi1

(1.309)

V3 ¼ VC þ Vi2

(1.310)

V4 ¼ VC Vi2

(1.311)

and:

resulting that the differential output current will have the following expression: rffiffiffiffiffiffiffi!2 K 2IO IOUT1 IOUT2 ¼ Vi2 Vi1 þ K 2 ! rffiffiffiffiffiffiffi 2 pffiffiffiffiffiffiffiffiffiffi K 2IO ¼ 8KIO ðVi2 Vi1 Þ Vi1 Vi2 þ K 2

ð1:312Þ

A differential amplifier using FGMOS transistors for cancellation of the errors introduced by the input offset voltage is presented in Fig. 1.83 [37].

84


The VC1 and VC2 voltages represent external applied continuous voltages. Considering a biasing in saturation of all transistors from Fig. 1.83 and FGMOS transistors having identical inputs, the expressions of IOUT1 and IOUT2 currents are: IOUT1

2 K V1 þ VC1 V VT ¼ 2 2

(1.313)

2 K V2 þ VC2 V VT ¼ 2 2

(1.314)

and: IOUT2 resulting: rffiffiffiffi 2 pffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffi V1 V2 VC1 VC2 þ IOUT1 IOUT2 ¼ 2 2 K

(1.315)

Using the notations VID ¼ V1 V2 and DVC ¼ VC1 VC2 and replacing the IOUT1 þ IOUT2 sum with IO , the previous relation becomes: pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffii 8h IO 2 IOUT1 ðIO IOUT1 Þ ¼ ðVID þ DVC Þ2 K

(1.316)

After some computations, it results the following expressions of IOUT1 and IOUT2 currents:

IOUT1

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi IO IO K K2 ¼ þ ðVID þ DVC Þ ðVID þ DVC Þ2 2 2 4IO 64IO2

(1.317)

and:

IOUT2

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi IO IO K K2 ¼ ðVID þ DVC Þ ðVID þ DVC Þ2 4IO 64IO2 2 2

(1.318)

So, the differential output current of the circuit presented in Fig. 1.83 will have the following expression: IOUT1 IOUT2

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi K K2 ¼ IO ðVID þ DVC Þ ðVID þ DVC Þ2 4IO 64IO2

(1.319)

The expression is similar with the result obtained for the differential amplifier based on MOS transistors biased in saturation. The advantage of using FGMOS

References

85

transistors for replacing classical MOS active devices is given by the possibility of compensating the input offset voltage of the differential amplifier by choosing a proper biasing voltage DVC , complementary with the intrinsic offset voltage of the stage.

1.3

Conclusions

Chapter extensively presents a multitude of design techniques for improving the performances of CMOS differential structures. The main goals of these design methods are to improve the linearity of differential structures and to obtain a railto-rail operation, for a more efficient utilization of the available supply voltage. The functional mathematical principles of operation that represent the basis for designing the presented linearization techniques have been used in order to minimize the linearity error of the implemented CMOS differential structures.

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Chapter 2

Voltage and Current Multiplier Circuits

2.1

Mathematical Analysis for Synthesis of Multipliers

The synthesis of multiplier circuits [1–60] is based on the utilization of some elementary principles, each of them representing the starting point for designing a class of multiplier circuit. Referring to the input variables, it can be identified two important classes of multiplier circuits: – Voltage multipliers, having as input variables two single or differential voltages and generating an output current proportional with the product of these input voltages; – Current multipliers, receiving as inputs two currents and producing an output current proportional with the product of the input currents. Because the multiplying function uses the characteristic of MOS transistors biased in saturation region, most of mathematical principles are derived from a linear relation between squaring terms (having voltages or currents as variables). The notations used for revealing these principles are: V1 , V2 , V3 and V4 represent the input potentials, while, usually, a constant voltage, VO , is introduced for modeling a voltage shifting; for current multipliers, I1 , I2 and I3 are the input currents and IO represents a reference current. In both cases, IOUT denotes the output current of the multiplier circuit.

C.R. Popa, Synthesis of Computational Structures for Analog Signal Processing, DOI 10.1007/978-1-4614-0403-3_2, # Springer Science+Business Media, LLC 2011

89

90

2 Voltage and Current Multiplier Circuits

2.1.1

Mathematical Analysis of Voltage Multiplier Circuits

2.1.1.1

First Mathematical Principle (PR 2.1)

The first mathematical principle used for implementing voltage multiplier circuits is based on the following identity: ðV1 þ V2 þ VO Þ2 ðV1 V2 þ VO Þ2 þ ðV1 V2 þ VO Þ2 ðV1 þ V2 þ VO Þ2 ¼ 2V2 ð2V1 þ 2VO Þ 2V2 ð2V1 þ 2VO Þ ¼ 8V1 V2

(2.1)

The voltage multipliers based on the previous relation computes a current proportional with the product of two input voltages, V1 and V2 .

2.1.1.2

Second Mathematical Principle (PR 2.2)

The mathematical relation that models this principle is ðV1 þ V3 þ VO Þ2 ðV2 þ V3 þ VO Þ2 þ ðV2 þ V4 þ VO Þ2 ðV1 þ V4 þ VO Þ2 ¼ ðV1 V2 ÞðV1 þ V2 þ 2V3 þ 2VO Þ ðV1 V2 ÞðV1 þ V2 þ 2V4 þ 2VO Þ ¼ 2ðV1 V2 ÞðV3 V4 Þ

(2.2)

The circuits that use this principle generates a current proportional with the product between two differential input voltages, V1 V2 and V3 V4 .

2.1.1.3

Third Mathematical Principle (PR 2.3)

This principle is illustrated by the following mathematical relation: ðV1 V3 þ VO Þ2 ðV1 V4 þ VO Þ2 þ ðV2 V4 þ VO Þ2 ðV2 V3 þ VO Þ2 ¼ ðV4 V3 Þð2V1 V3 V4 þ 2VO Þ ðV4 V3 Þð2V2 V3 V4 þ 2VO Þ ¼ 2ðV1 V2 ÞðV4 V3 Þ

(2.3)

The multiplier circuits that implement this principle compute, also, an output current proportional with the product between two differential input voltages, V1 V2 and V4 V3 .

2.1 Mathematical Analysis for Synthesis of Multipliers

2.1.1.4

91

Fourth Mathematical Principle (PR 2.4)

The fourth mathematical principle is based on the following mathematical relation: pffiffiffiffiffi IOUT ¼ a IO ðV1 V2 Þ

pffiffiffi ) IOUT ¼ a bðV1 V2 ÞðV3 V4 Þ

IO ¼ bðV3 V4 Þ2

(2.4)

or IOUT ¼ a

pffiffiffiffi pffiffiffiffi I1 I2 ðV1 V2 Þ

pffiffiffiffi pffiffiffiffi2 I1 I2 ¼ bðV3 V4 Þ2

pffiffiffi ) IOUT ¼ a bðV1 V2 ÞðV3 V4 Þ

(2.5)

a and b represent constant coefficients, depending on the particular implementation of the multiplier circuit based on this mathematical principle.

2.1.1.5

Fifth Mathematical Principle (PR 2.5)

The fifth mathematical principle represents the cancellation of a nonlinear dependence of an output current, IOUT , on the input voltage, V1 : IOUT

2.1.1.6

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi IO þ KV12 =4 V12 pffiffiffiffiffiffiffiffi ¼ KIO V1 ¼ KV1 4 K

(2.6)

Sixth Mathematical Principle (PR 2.6)

The mathematical relation that models this principle is

2.1.1.7

V 1 þ V2 VO 2

2

þ

VO2

V1 VO 2

2

V2 VO 2

2 ¼ V1 V2

(2.7)

Seventh Mathematical Principle (PR 2.7)

The identity representing the basis of this mathematical relation is ðV1 þ V2 Þ2 ðV1 V2 Þ2 ¼ 4V1 V2

(2.8)

92

2.1.1.8


Different Mathematical Principles for Voltage Multipliers (PR 2.Da)

A class of multipliers can be designed starting from different mathematical principles, that are useful for linearizing the behavior of the multiplier circuits.

2.1.2

Mathematical Analysis of Current Multiplier Circuits

2.1.2.1

Ninth Mathematical Principle (PR 2.9)

The ninth mathematical principle uses two square-rooting circuits in order to implement the multiplying function: pffiffiffiffiffiffiffiffiffiffiffiffiffi IO1 ¼ a IO IOUT pffiffiffiffiffiffiffiffi I1 I2 IO2 ¼ a I1 I2 ) IOUT ¼ IO IO1 ¼ IO2 ð2:9Þ

2.1.2.2

Tenth Mathematical Principle (PR 2.10)

The identity representing the basis of this mathematical relation is " # " # ðI1 þ I2 Þ2 ðI1 þ I2 Þ2 4I1 I2 IO þ IO ¼ aIO aIO aIO

2.1.2.3

(2.10)

Eleventh Mathematical Principle (PR 2.11)

In order to implement the eleventh mathematical principle, the circuits use only MOS transistors biased in weak inversion region, the translinear loops that contain gate-source voltages generating the product between the input currents.

2.1.2.4

Different Mathematical Principles for Current Multipliers (PR 2.Db)

A class of multipliers can be designed starting from different mathematical principles that are useful for linearizing the behavior of the current multiplier circuits.

2.2 Analysis and Design of Multiplier Circuits

93

VDD IO

IO

IOUT2

M1 -V1

IOUT1

-V2

M5

M7 M2

V

M8 M3

M4 V2

M6

-V1

V1 IO

IO

-VDD Fig. 2.1 Multiplier circuit (1) based on PR 2.1

2.2

Analysis and Design of Multiplier Circuits

2.2.1

Design of Voltage Multiplier Circuits

Based on the previous presented mathematical analysis, the voltage multipliers can be clustered in eight important functional classes: circuits using PR 2.1–PR 2.7 elementary principle and a class containing multipliers based on different functional relations.

2.2.1.1

Multiplier Circuits Based on the First Mathematical Principle (PR 2.1)

The multiplier structures using as functional basis PR 2.1 present the important advantage of using a symmetrical structure that minimizes the intrinsic linearity error of the designed circuits. A circuit that implements the product between two input voltages using the PR 2.1 mathematical principle is presented in Fig. 2.1 [1]. The output current of the voltage multiplier can be expressed as a linear function of the currents, IOUT1 and IOUT2 : IOUT ¼ IOUT1 IOUT2 ¼ ðID2 þ ID4 Þ ðID1 þ ID3 Þ

(2.11)

The drain current of M1 transistor is ID1 ¼

K ðV1 V VT Þ2 2

(2.12)

94


The V potential is imposed by V2 potential and by the gate-source of M5 transistor (that is biased at a constant current, IO ) to be equal with: V ¼ V2 VGS5

rffiffiffiffiffiffiffi 2IO ¼ V2 VT K

(2.13)

Replacing (2.13) in (2.12), it results the following dependence of ID1 current on V1 , and V2 input potentials:

ID1

K ¼ V1 þ V2 þ 2


(2.14)

Similarly, the drain currents of M2–M4 transistors can be expressed as

ID2

K ¼ V1 þ V2 þ 2


ID3

K ¼ V1 V2 þ 2


ID4

K ¼ V1 V2 þ 2


(2.15)

(2.16)

(2.17)

The expression of the output current as a function of input potentials can be obtained using relations (2.11) and (2.14)–(2.17): K IOUT ¼ 2V1 2V2 þ 2 2

rffiffiffiffiffiffiffi! rffiffiffiffiffiffiffi! 2IO K 2IO þ ð2V1 Þ 2V2 þ 2 ¼ 4KV1 V2 (2.18) 2 K K

Another multiplier structure based on the first mathematical principle (PR 2.1) is presented in Fig. 2.2 [2]. Its output current can be expressed as IOUT ¼ ðID1 þ ID3 Þ ðID2 þ ID4 Þ ¼ ðID1 ID2 Þ þ ðID3 ID4 Þ

(2.19)

For M1–M4 transistors, the gate potentials are imposed by the common-mode voltage VC and by the differential components V1 =2 and V2 =2.


95

IOUT2

IOUT1

M2

M1

M3

M4

V1/2

-V1/2

-V1/2

V1/2

V2/2

V2/2

-V2/2

-V2/2

VS

VC

Fig. 2.2 Multiplier circuit (2) based on PR 2.1

Replacing the expressions of the previous drain currents with their quadratic dependence on the gate-source voltages, it results: 2 K V 1 þ V2 þ VC VS VT 2 2 2 2 K V1 þ V2 K V1 V2 þ VC VS VT þ VC VS VT þ 2 2 2 2 2 K V2 V1 þ VC VS VT ð2:20Þ 2 2 IOUT ¼ IOUT1 IOUT2 ¼

So, the output current will be proportional with the product between the differential-mode input voltages: IOUT ¼ þ

K V1 ðV2 þ 2VC 2VS 2VT Þ 2

K ðV1 ÞðV2 þ 2VC 2VS 2VT Þ ¼ KV1 V2 2

ð2:21Þ

An alternate realization of a voltage multiplier circuit based on the first mathematical principle (PR 2.1) is presented in Fig. 2.3. In order to reduce the

96


VDD

IOUT M1 M2

M3 M4

V1 - V1 V2 - V2 Fig. 2.3 Multiplier circuit (3) based on PR 2.1

circuit complexity, a part of classical MOS transistors have been replaced by FGMOS active devices with identical inputs. The output current can be expressed as follows: 2 K V1 þ V2 VT 2 2 2 2 K V1 V2 K V1 þ V2 VT þ VT 2 2 2 2 2 K V2 V1 K K VT ¼ V2 ðV1 2VT Þ V2 ðV1 2VT Þ ¼ KV1 V2 2 2 2 2 IOUT ¼ ðID1 ID2 Þ þ ðID4 ID3 Þ ¼

2.2.1.2

ð2:22Þ

Multiplier Circuits Based on the Second Mathematical Principle (PR 2.2)

The multipliers based on PR 2.2 can be used in a large area of applications that require the implementation of the product between two differential voltages. A voltage multiplier having as functional relation the second mathematical principle (PR 2.2) is presented in Fig. 2.4 [3]. All MOS transistors are biased in saturation region and VO represents a constant voltage that is summed with V3 and V4 voltages. The expression of differential output current is IOUT1 IOUT2 ¼ ðID5 þ ID16 Þ ðID8 þ ID13 Þ

(2.23)


97 VDD

M2

IOUT1

M11

M3 M5

VX V3 + VO

M1 M4

M10

IOUT2

V1

V2

M6 VW

M8

M16

M7

M14 VZ M15

M13 V2

VY V1

M12 M9

V 4 + VO -VDD


where the previous drain currents can be expressed as follows: ID5 ¼

K ðVX þ VDD VT Þ2 2

(2.24)

ID16 ¼

K ðVZ þ VDD VT Þ2 2

(2.25)

ID8 ¼

K ðVW þ VDD VT Þ2 2

(2.26)

ID13 ¼

K ðVY þ VDD VT Þ2 2

(2.27)

As a consequence of the circuit configuration, the gate-source voltages of M2 and M3 transistors are equal, resulting ID2 ¼ ID3 . But ID3 ¼ ID4 and ID1 ¼ ID2 , so ID1 ¼ ID4 . In conclusion, because M1 and M4 transistors are identical, it results VGS1 ¼ VSG4 , equivalent with: V3 þ VO þ VDD ¼ VX V1

(2.28)

Thus, the expression of VX potential will be VX ¼ V1 þ V3 þ VO þ VDD

(2.29)

Replacing (2.29) in (2.24), the drain current of M5 transistor will have the following expression: ID5 ¼

K ½ðV1 þ V3 Þ þ ð2VDD þ VO VT Þ2 2

(2.30)

Similarly, the expression of drain currents of M8, M13 and M16 transistor will be ID8 ¼


(2.31)

98


IOUT2

IOUT1

V3

V1 V2

V4


ID13 ¼


(2.32)

ID16 ¼


(2.33)

Replacing (2.30)–(2.33) in (2.23), it results: IOUT1 IOUT2 ¼

K ðV1 V2 ÞðV1 þ V2 þ 2V3 þ 4VDD þ 2VO 2VT Þ 2

K ðV1 V2 ÞðV1 þ V2 þ 2V4 þ 4VDD þ 2VO 2VT Þ 2

ð2:34Þ

So IOUT1 IOUT2 ¼ K ðV1 V2 Þ ðV3 V4 Þ

(2.35)

A possible implementation of a voltage multiplier based on the second mathematical principle (PR 2.2), using FGMOS transistors is presented in Fig. 2.5 [4]. Considering identical inputs for all FGMOS transistors, the differential output current of the voltage multiplier presented in Fig. 2.5 can be expressed as follows: 2 2 K V1 þ V2 K V3 þ V4 VT þ VT 2 2 2 2 2 2 K V2 þ V3 K V1 þ V4 K VT VT ¼ ðV1 V3 ÞðV2 V4 Þ 2 2 2 2 4 (2.36)

IOUT ¼ IOUT1 IOUT2 ¼


99

IOUT2

IOUT1

V3

V1 V2

V4 VS

IO


An alternate implementation of a voltage multiplier using the second mathematical principle is presented in Fig. 2.6 [4]. The differential output current of the voltage multiplier shown in Fig. 2.6 will have the following expression: 2 K V1 þ V2 IOUT ¼ IOUT1 IOUT2 ¼ VS VT 2 2 2 2 K V3 þ V4 K V 2 þ V3 þ VS VT VS VT 2 2 2 2 2 K V1 þ V4 K ¼ ðV1 V3 Þ ðV2 V4 Þ VS VT 2 2 4

ð2:37Þ

The multiplier circuit presented in Fig. 2.7 [5] is based on the second mathematical principle (PR 2.2). The output current of the voltage multiplier is implemented (using an additional current mirror, not shown in Fig. 2.7) to be the difference between IOUT2 and IOUT1 currents and it can be expressed as follows: IOUT ¼ IOUT2 IOUT1 ¼ ðI1 þ I4 Þ ðI2 þ I3 Þ 2 2 K V1 þ V3 þ VG K V2 þ V4 þ VG VT þ VT ¼ 3 3 2 2 2 2 K V 1 þ V4 þ VG K V2 þ V3 þ VG VT VT 2 2 3 3

ð2:38Þ

100


IOUT1

I1 V1 V3

M1

IOUT2

I2

I3

I4

M2

M3

M4

V2 V4

VG


resulting: K V3 V4 2V1 þ V3 þ V4 þ 2VG 2VT IOUT ¼ 3 3 2 K V3 V4 2V2 þ V3 þ V4 þ 2VG 2VT 2 3 3

ð2:39Þ

So, the output current is proportional with the product between the differential input voltages: IOUT ¼

2.2.1.3

K ðV3 V4 Þ ðV1 V2 Þ 9

(2.40)

Multiplier Circuits Based on the Third Mathematical Principle (PR 2.3)

Alternative implementations of multiplier circuits designed for differential input voltages uses the mathematical relations described by PR 2.3. A combination of two differential amplifiers, M1–M2 and M3–M4, can implement the multiplying function (Fig. 2.8), the functional equations of this circuit being obtained using the third mathematical principle (PR 2.3) [6]. The gate-source voltages of M1 and M5 transistors are equal because they are identical and biased at the same drain current, resulting: VDD V3 ¼ V V1

(2.41)

V ¼ V1 V3 þ VDD

(2.42)

equivalent with:


101 VDD M14 IOUT

M13

V3 M9

V

V4

M2

M1 V1

V4

V2

M10 M11 M6

M5

V3

M4

M3

M11

M12 M12


The drain current of M9 transistor can be expressed as follows: ID9 ¼

K K K ðVGS9 VT Þ2 ¼ ðV VT Þ2 ¼ ½ðV1 V3 Þ þ ðVDD VT Þ2 2 2 2

(2.43)

Similarly, the expressions of drain currents for M10, M11 and M12 transistors are: ID10 ¼

K ½ðV1 V4 Þ þ ðVDD VT Þ2 2

(2.44)

ID11 ¼


(2.45)

ID12 ¼


(2.46)

The output current IOUT of the multiplier will be expressed by IOUT ¼ ID9 þ ID11 ID10 ID12

(2.47)


K ðV4 V3 Þð2V1 V3 V4 þ 2VDD 2VT Þ 2

K ðV3 V4 Þð2V2 V3 V4 þ 2VDD 2VT Þ 2

ð2:48Þ

IOUT ¼ K ðV2 V1 Þ ðV3 V4 Þ

(2.49)

or

102

2 Voltage and Current Multiplier Circuits VDD M14 IOUT

M13

V1

V3

M1

M2 M9 M10

V5 M5

V6

V4

M6

M11 M12

V7 M7

V2

M4

M3

V8 M8

V3


The voltage multiplying function can be implemented using the third mathematical principle (PR 2.3) by the structure presented in Fig. 2.9 [7]. The circuit contains four pairs of transistors (M1–M5, M2–M6, M3–M7 and M4–M8) that implement voltage subtraction functions. Because M1 and M5 transistors are identical and biased at the same drain current, their gate-source voltages will be equal, so that: VDD V1 ¼ V5 V3

(2.50)

resulting that V5 potential is given by the differential input voltage, V3 V1 : V5 ¼ VDD þ ðV3 V1 Þ

(2.51)

The V5 potential is applied on the gate of M9 transistor, its drain current being expressed using the squaring characteristic of the MOS transistor biased in saturation: ID9 ¼

K K ðV5 VT Þ2 ¼ ½ðVDD VT Þ þ ðV3 V1 Þ2 2 2

(2.52)

Similarly, the drain currents of M10, M11 and M12 transistors are ID10 ¼


(2.53)

ID11 ¼


(2.54)

ID12 ¼


(2.55)


103 VDD

M13

M14 IOUT

M1 V3

V1

M5

VM

V4 M3

I1

M10 I2

V2

VN

M8 M4 M6

M2

VO

M11

M7 M9

I3

M12 I4

VO


The output current of the voltage multiplier presented in Fig. 2.9 can be expressed as a linear relation using the previous currents: IOUT ¼ ID9 þ ID10 ID11 ID12

(2.56)


K ðV3 V4 Þð2VDD 2VT þ V3 þ V4 2V1 Þ 2

K ðV4 V3 Þð2VDD 2VT þ V3 þ V4 2V2 Þ 2

ð2:57Þ

So, the circuit implements the voltage multiplying function: IOUT ¼ K ðV3 V4 Þ ðV2 V1 Þ

(2.58)

A multiplier circuit using exclusively MOS transistors biased in saturation region, based on the third mathematical principle (PR 2.3), is presented in Fig. 2.10 [8]. The M1 and M2 transistors form a difference circuit that generates VM potential. Considering identical transistors and because they are biased at the same drain current, it results equal gate-source voltages for these transistors. Thus, VM potential will have the following expression: VM ¼ V1 VGS1 ¼ V1 VGS2 ¼ V1 VO

(2.59)

104


The gate-source voltage of M5 transistor can be obtained using the equality between gate-sources of M5 and M6 transistors: V3 VM ¼ 2VGS5

(2.60)

V3 VM V3 V1 þ VO ¼ 2 2

(2.61)

resulting: VGS5 ¼

Thus, the expression of I1 current will be I1 ¼

2 K K V3 V1 þ VO ðVGS5 VT Þ2 ¼ VT 2 2 2

(2.62)

Similarly, it is possible to determine the expressions of I2 , I3 and I4 currents: I2 ¼

2 K V4 V1 þ VO VT 2 2

(2.63)

I3 ¼

2 K V3 V2 þ VO VT 2 2

(2.64)

I4 ¼

2 K V4 V2 þ VO VT 2 2

(2.65)

The output current can be expressed as a linear function of the previous currents: IOUT ¼ I1 þ I4 I2 I3

(2.66)

resulting: K V2 V1 2V3 V1 V2 þ 2VO 2VT IOUT ¼ 2 2 2 K V2 V1 2V4 V1 V2 þ 2VO 2VT 2 2 2

ð2:67Þ

So IOUT ¼


(2.68)

The multiplier circuit presented in Fig. 2.11 [9] implements the same mathematical principle PR 2.3 and it is composed from two differential amplifiers, M1–M4


105

VDD M4

M8 V2

V V1

M2

M1

V1

M6

M5 V4

V3

M3

V’

M7

IOUT2

IOUT1 IO

IO


and M5–M8. For obtaining a low impedance in the common-source points, each differential amplifier uses a flipped voltage follower (M3–M4 and, M7–M8, respectively). The M4 and M8 transistors absorb current variations of M1–M2 differential pairs and M5–M6. The differential output current of the first differential amplifier, M1–M2 can be expressed using the squaring law of MOS transistors biased in saturation region: ID1 ID2 ¼ ¼

K K ðV V1 VT Þ2 ðV V2 VT Þ2 2 2

K ðV2 V1 Þ ð2V V1 V2 2VT Þ 2

ð2:69Þ

Similarly, the expression of the differential output current for the second differential amplifier, M5–M6 is ID5 ID6 ¼

K ðV1 V2 Þ ð2V 0 V1 V2 2VT Þ 2

(2.70)

The differential output current of the entire multiplier circuit presented in Fig. 2.11 will have the following expression: IOUT1 IOUT2 ¼ ðID1 þ ID5 Þ ðID2 þ ID6 Þ ¼ ðID1 ID2 Þ þ ðID5 ID6 Þ

(2.71)

Replacing (2.69) and (2.70) in (2.71), it results: IOUT1 IOUT2 ¼ K ðV2 V1 Þ ðV V 0 Þ

(2.72)

106


VDD IOUT

V1

I4

I1

M4

M1

I2 M2 V 3’

I3 M3 V3

M5

V4’ V4

V2

M6 IO

IO


Because M3 and M7 transistors are biased at a constant current, IO , imposed by external current generators, the V and V 0 potentials can be expressed as follows: V ¼ V3 þ VSG3

rffiffiffiffiffiffiffi 2IO ¼ V3 þ VT þ K

(2.73)

and 0

V ¼ V4 þ VSG7

rffiffiffiffiffiffiffi 2IO ¼ V4 þ VT þ K

(2.74)

From (2.72), (2.73) and (2.74), it results the multiplying function implemented by the circuit from Fig. 2.11: IOUT1 IOUT2 ¼ K ðV2 V1 Þ ðV3 V4 Þ

(2.75)

A possible realization of a voltage multiplier, based on the third mathematical principle (PR 2.3) is presented in Fig. 2.12 [10]. The core of the circuit is represented by the group of M1–M4 transistors. Using identical devices, their drain currents will have the following expressions: I1 ¼

K ðV1 V3 0 VT Þ2 2

(2.76)

I2 ¼

K ðV2 V3 0 VT Þ2 2

(2.77)


107

I3 ¼

K ðV2 V4 0 VT Þ2 2

(2.78)

I4 ¼

K ðV1 V4 0 VT Þ2 2

(2.79)

As a result of using additional current mirrors, the output current of the differential structure will have a linear variation with respect to I1 I4 currents: IOUT ¼ ðI2 I1 Þ þ ðI4 I3 Þ

(2.80)


K ðV2 V1 Þ ðV1 þ V2 2V3 0 2VT Þ 2

K ðV1 V2 Þ ðV1 þ V2 2V4 0 2VT Þ ¼ K ðV1 V2 Þ ðV3 0 V4 0 Þ 2

ð2:81Þ

Because M5 and M6 transistors are biased at the constant current, IO , they will introduce a voltage shifting between V3 and V3 0 and, respectively, between V4 and V4 0 potentials, as follows: rffiffiffiffiffiffiffi 2IO 0 V3 ¼ V3 þ VSG5 ¼ V3 þ VT þ (2.82) K and 0

V4 ¼ V4 þ VSG6

rffiffiffiffiffiffiffi 2IO ¼ V 4 þ VT þ K

(2.83)

From the previous relations, it results the following expression of the output current: IOUT ¼ KðV1 V2 Þ ðV3 V4 Þ

(2.84)

A voltage multiplier can be designed using 4 v squaring circuits (Fig. 2.13). Considering that the output current of the voltage squaring circuits is equal with KDV 2 =2 DV being its differential input voltage, the differential output current of the multiplier presented in Fig. 2.13 will have the following expression: K K ðV1 V4 Þ2 þ ðV2 V3 Þ2 2 2 K K 2 ðV1 V2 Þ ðV3 V4 Þ2 2 2

IOUT1 IOUT2 ¼

ð2:85Þ

108


V1

SQ I

V3

V2

SQ III

SQ II

V4

SQ IV

IOUT1

IOUT2

Fig. 2.13 Multiplier circuit (6) based on PR 2.3 – block diagram

IOUT1

IOUT2

M2b M1b M3b

M2a M1a

V3 V4

M3a

V1 V2

M2a’

M1a’

M3a’

M2b’ M1b’ M3b’


resulting: IOUT1 IOUT2 ¼ K ðV1 V3 Þ ðV2 V4 Þ

(2.86)

A voltage multiplier that illustrates the third mathematical principle PR 2.3 can be implemented using the symmetrical structure presented in Fig. 2.14 [11]. The circuit is derived from the core shown in Fig. 2.15 [11]. For this circuit core, the ID1 ID2 differential output current can be computed replacing the expressions of drain currents by their squaring dependencies on the gate-source voltages (all MOS transistors are supposed to be biased in saturation region). ID1 ID2 ¼

K K ðVGS1 VT Þ2 ðVGS3 VT Þ2 2 2

(2.87)

2.2 Analysis and Design of Multiplier Circuits Fig. 2.15 The core of the multiplier circuit (7) based on PR 2.3

109

ID1

ID2 M2

V3

M3

V1

M1

The expression of the gate-source voltage of M1 transistor can be obtained using the equality between the gate-source voltages (if M2 and M3 transistors are identical and biased at the same drain current), resulting: VGS1 ¼ V3 VGS2 ¼ V3 VGS3 ¼ V3 V1

(2.88)

Replacing (2.88) in (2.87), the expression of the output differential current for the circuit presented in Fig. 2.14 can be expressed as follows: ID1 ID2 ¼ ¼

K K ðV3 V1 VT Þ2 ðV1 VT Þ2 2 2

K ðV3 2VT ÞðV 3 2V1 Þ 2

ð2:89Þ

In order to implement a voltage multiplier circuit, two identical cores from Fig. 2.15 have to be used (Fig. 2.16 [11]), the input voltages for each of them being V1 and V3 and, respectively, V2 and V3 . For simplifying the analysis of the circuit presented in Fig. 2.16, (2.89) relation can be used, the differential output current of the circuit from Fig. 2.16 being, practically, the difference between two differential output currents of two identical cores, excited using different input voltages: 0 IL IR ¼ ID1 0 þ ID2 ðID2 þ ID1 0 Þ ¼ ðID1 ID2 Þ ðID1 0 ID2 0 Þ

(2.90)

Particularizing (2.89) relation for each circuit core, it results: IL IR ¼

K K ðV3 2VT Þ ðV 3 2V1 Þ ðV3 2VT Þ ðV 3 2V2 Þ 2 2 ¼ K ðV2 V1 Þ ðV3 2VT Þ

ð2:91Þ

110


IR

IL

V3 M2’

M2

M1’

M1 M3

V1

V2

M3’

Fig. 2.16 Half-circuit of the multiplier circuit (7) based on PR 2.3

So, for the voltage multiplier presented in Fig. 2.14, the expression of the differential output current will be IOUT1 IOUT2 ¼ ID1b þ ID2a þ ID1a 0 þ ID2b 0 ID2b ID1a ID2a 0 ID1b 0 ¼ ½ðID1b ID2b Þ ðID1b 0 ID2b 0 Þ ½ðID1a ID2a Þ ðID1b 0 ID2a 0 Þ ¼ ðIL IR Þa ðIL IR Þb ¼ K ðV2 V1 ÞðV4 2VT Þ K ðV2 V1 ÞðV3 2VT Þ ¼ K ðV2 V1 ÞðV4 V3 Þ (2.92) A modified circuit that implements the multiplication of two differential input voltages is presented in Fig. 2.17 [12] (a four-quadrant multiplier that does not require balanced inputs). The difference between the gate-source voltages of M2 and M9 transistors can be expressed as follows: rffiffiffiffi 2 pffiffiffiffi pffiffiffiffiffi I2 IO (2.93) VGS2 VGS9 ¼ V4 V3 ¼ K It results I2 ¼ IO þ

pffiffiffiffiffiffiffiffiffiffi K ðV4 V3 Þ2 þ 2KIO ðV4 V3 Þ 2

(2.94)

Similarly, for M3–M5, M1–M4, M6–M9, M5–M7 and M1–M8 differential pairs, the differences between their gate-source voltages have the following expressions: rffiffiffiffi 2 pffiffiffiffi pffiffiffiffiffi VGS3 VGS5 ¼ V3 V2 ¼ I3 IO (2.95) K


111 VDD

IO IOUT1

IOUT2 M4

V4

M1

I2

M2 M3

V3

I3

I4

V2

V1 M5

M6 M7

I6

I7

V4

M8

I8

M9

V3

- VDD


VGS4 VGS1

rffiffiffiffi 2 pffiffiffiffi pffiffiffiffiffi I4 IO ¼ V1 V4 ¼ K

VGS6 VGS9 ¼ V1 V3 ¼

VGS7 VGS5

rffiffiffiffi 2 pffiffiffiffi pffiffiffiffiffi I6 IO K

rffiffiffiffi 2 pffiffiffiffi pffiffiffiffiffi ¼ V 4 V2 ¼ I7 IO K

(2.96)

(2.97)

(2.98)

and VGS8 VGS1

rffiffiffiffi 2 pffiffiffiffi pffiffiffiffiffi I8 IO ¼ V 3 V4 ¼ K

(2.99)

resulting: I3 ¼ I O þ


(2.100)

I4 ¼ IO þ


(2.101)

I6 ¼ IO þ


(2.102)

I7 ¼ IO þ


(2.103)

112


Fig. 2.18 Multiplier circuit (1) based on PR 2.4 – general block diagram

CM IOUT1 V1

IOUT IOUT2

DA

V2

IO V3

SQ

V4

and I8 ¼ IO þ


(2.104)

The differential output current for the multiplier circuit presented in Fig. 2.17 will have the following expression: IOUT ¼ IOUT1 IOUT2 ¼ I2 þ I3 þ I4 I6 I7 I8 ¼ K ðV1 V2 ÞðV3 V4 Þ

2.2.1.4

ð2:105Þ

Multiplier Circuits Based on the Fourth Mathematical Principle (PR 2.4)

This class of multiplier circuits presents the important advantage of generating, using the same circuit core, multiple circuit functions: amplifying, multiplying, squaring or simulating both positive and negative equivalent resistances. A method for designing a voltage multiplier using the fourth mathematical principle (PR 2.4) is illustrated by the block diagram presented in Fig. 2.18, the biasing current of the first differential amplifier (with V1 V2 differential input voltage) being generated by a voltage squaring circuit having as input another differential voltage V3 V4 . Supposing that the Gm transconductance of the differential core is proportional with the square-root of the biasing current, IO (an usual relation for a large class of differential amplifiers), the output current of the multiplier circuit will be proportional with the product between the input voltages of the differential amplifier and voltage squarer circuit.


113

Fig. 2.19 Multiplier circuit (1) based on PR 2.4 – block diagram with SQ circuit implementation

CM IOUT1

IOUT IOUT2

V1

V2

DA I

IO’ 2IO IOUT1’ V3

IOUT2’

DA II

V4

IO

The implementation of a voltage multiplier circuit can be simplified for a particular realization of the differential amplifier, having the transfer characteristic linearized using the method of constant sum of gate-source voltages. In this case, the squarer circuit from Fig. 2.18 can be implemented using the same differential amplifier, the sum of its output currents being proportional with the square of the differential voltage applied on the input pins. The block diagram presented in Fig. 2.18 can be re-drawn replacing the general voltage squarer with its particular implementation based on a differential amplifier (Fig. 2.19). The IO current from Fig. 2.18 has been replaced with a IO 0 current, linearly dependent on the output current of a squaring circuit from Fig. 2.19, having as input the V3 V4 differential voltage, as follows: IO 0 ¼ IOUT1 0 þ IOUT2 0 2IO

(2.106)

A possible realization of the differential amplifier linearized using the previous principle is shown in Fig. 2.20 [13]. Considering a biasing in saturation of MOS transistors, the IOUT1 and IOUT2 output currents of the differential amplifier from Fig. 2.20 can be expressed as follows: IOUT1 ¼

K ðVGS1 VT Þ2 2

(2.107)

114


IOUT1

IOUT2 M1

V1 IOUT1

M2

IO IO

VO

-

+ IO

IO

+

VO

-

V2 I

IO

OUT2

IO

Fig. 2.20 Multiplier circuit (1) based on PR 2.4 – principle implementation of DA block

IOUT2 ¼

K ðVGS2 VT Þ2 2

(2.108)

The expression of the V1 V2 differential input voltage is V1 V2 ¼ VO VGS2 ¼ VGS1 VO

(2.109)

VGS1 ¼ VO þ ðV1 V2 Þ

(2.110)

VGS2 ¼ VO ðV1 V2 Þ

(2.111)

resulting:

and

Replacing (2.110) and (2.111) in (2.107) and (2.108), it results: IOUT1 ¼

K ½ðVO VT Þ þ ðV1 V2 Þ2 2

(2.112)

IOUT2 ¼

K ½ðVO VT Þ ðV1 V2 Þ2 2

(2.113)

and

So, the differential output current of the circuit presented in Fig. 2.20 will be IOUT ¼ IOUT1 IOUT2 ¼ 2K ðVO VT Þ ðV1 V2 Þ

(2.114)


115

In the particular case of implementing each VO voltage source from Fig. 2.20 using a gate-source voltage of a MOS transistor biased in saturation region, it results: rffiffiffiffiffiffiffi 2IO VO ¼ VT þ K

(2.115)

so IOUT ¼


(2.116)

The sum of the output currents of the differential amplifier will have the following expression: IOUT1 þ IOUT2 ¼ K ðVO VT Þ2 þ K ðV1 V2 Þ2 ¼ 2IO þ K ðV1 V2 Þ2

(2.117)

In conclusion, using in the block diagram of the voltage multiplier from Fig. 2.19 the particular implementation of the differential amplifier shown in Fig. 2.20, it is possible to write: IOUT ¼ IOUT1 IOUT2 ¼

pffiffiffiffiffiffiffiffiffiffiffiffi 8KIO 0 ðV1 V2 Þ

(2.118)

where IO 0 current is linearly dependent on the sum of the output currents of the second differential amplifier: IO 0 ¼ IOUT1 0 þ IOUT2 0 2IO ¼ K ðV3 V4 Þ2

(2.119)

Replacing (2.119) in (2.118), it results: IOUT ¼

pffiffiffi 8K ðV1 V2 Þ ðV3 V4 Þ

(2.120)

The complete implementation of the principle illustrated in the block diagram presented in Fig. 2.19 and the utilization of the method of realization shown in Fig. 2.20 allows many possible configurations. The differential amplifier presented in Fig. 2.21 [14] is realized using M1 and M2 transistors and implements the VO voltage sources from Fig. 2.20 using the gatesource voltages of M3 and M5 transistors, biased at the same constant current, IO . So, the differential output current of the differential structure from Fig. 2.21, IOUT ¼ IOUT1 IOUT2 , will be expressed by (2.116). The realization of the multiplier circuit based on the block diagram from Fig. 2.19, using the differential amplifier presented in Fig. 2.21 [14] is shown in Fig. 2.22, the expression of the output current of the voltage multiplier shown in Fig. 2.22 being given by (2.120).

116


VDD M7

M8 IO

IOUT1

IO

IO

M5 M2

M1 M3

V1

IOUT2 V2

VO

VO

IO + iO2

IO+iO1 M4

M6

-VDD Fig. 2.21 Multiplier circuit (1) based on PR 2.4 – first implementation of DA block

VDD

I O’ IOUT1 V1

IO’

IOUT

IO’ IOUT2

M1

M2

V2

-VDD VDD

2IO

IO

IO

IO

IOUT1’ V3

IOUT2’ M3

M4

V4

-VDD Fig. 2.22 Complete circuit of the multiplier from Fig. 2.19 using the first implementation of DA block


117

VDD

IO

IO

IOUT2

IOUT1 M1 M3

V1 VO

M2 M4

V2 VO

Fig. 2.23 Multiplier circuit (1) based on PR 2.4 – second implementation of DA block

The second possible implementation of the previous presented principle uses as differential amplifier the circuit presented in Fig. 2.23 [14], the VO voltage sources from Fig. 2.20 being realized using the gate-source voltages of M3 and M4 transistors, biased at the same constant current, IO , while the differential amplifier is realized with M1 and M2 transistors. The output current of this differential amplifier is expressed by (2.116). The complete realization of the voltage multiplier is shown in Fig. 2.24, the expression of its output current being given by (2.120). The third implementation of a differential amplifier based on the principle shown in Fig. 2.20 is presented in Fig. 2.25 [13, 15], the VO voltage sources from Fig. 2.20 being realized using the gate-source voltages of M3 and M4 transistors, biased at the same constant current, IO . The output current of this differential amplifier (which is implemented using M1 and M2 transistors) is expressed by (2.116). The disadvantage of this realization of the differential amplifier comparing with the other proposals consists in a biasing of transistors M3 and M4 at variable currents. The complete realization of the voltage multiplier is shown in Fig. 2.26 [15], the expression of its output current being also given by (2.120). The fourth implementation of a differential amplifier based on the principle shown in Fig. 2.20 is presented in Fig. 2.27 [16], the VO voltage sources from Fig. 2.20 being realized using the gate-source voltages of M3a and M3b transistors, biased at the same constant current IO (because I and I 0 currents are zero as a result of the circuit configuration). The output current of this differential amplifier is expressed by (2.116).

118


VDD

IOUT

IO’ IOUT1

IO’

IO’

IOUT2

V2

V1

-VDD VDD

IO

2IO IOUT1’

V3

I O’ IO

IO

IOUT2’

V4

-VDD Fig. 2.24 Complete circuit of the multiplier from Fig. 2.19 using the second implementation of DA block

The fifth implementation of a differential amplifier based on the principle shown in Fig. 2.20 is presented in Fig. 2.28 [17], the VO voltage sources from Fig. 2.20 being realized using the gate-source voltages of M3 and M4 transistors, biased at the same constant current, IO (because I and I0 currents are zero as a result of the circuit configuration). The output current of this differential amplifier (realized with M1 and M2 transistors) is expressed by (2.116).

IOUT2

IOUT1 V1

M1

M2

VO

VO M3

M5

V2

M4

IO

M6

M7

Fig. 2.25 Multiplier circuit (1) based on PR 2.4 – third implementation of DA block

VDD

IOUT2

IOUT1 M2

M1

V1

V2

IOUT2’

IOUT1’

2IO

M4

M3

V3

V4

IO’ M8

M10 M11

M9 M6

M5

M7

IO M14

M13

M12

Fig. 2.26 Complete circuit of the multiplier from Fig. 2.19 using the third implementation of DA block VDD M5a

IOUT1

M2a

M10a

M3a M3b

I 2IOUT1

M9a

M6b

IOUT2

A IOUT1

M7b

IOUT1 M1a

V1

M7a

M6a

IO

VO

IO

2IOUT1 M8a

IO

IO

M2b VO 2IOUT2 M8b

I’

M5b

IOUT2 M1b

V2 B 2IOUT2

IOUT2

M9b

M10b

Fig. 2.27 Multiplier circuit (1) based on PR 2.4 – fourth implementation of DA block

120


VDD

IO

IOUT1 V1

M1

IO M3

IOUT2

M4

M2 VO

VO

V2

I I’ IO

IO

Fig. 2.28 Multiplier circuit (1) based on PR 2.4 – fifth implementation of DA block

ID1

ID1

M1

V1

IOUT1

M2

V2

M3

Fig. 2.29 The core of the multiplier circuit (2) based on PR 2.4

Both fourth and fifth implementations of voltage multipliers (derived from differential amplifiers presented in Fig. 2.27 and Fig. 2.28) are based on the principle illustrated in Fig. 2.19. The core of another voltage multiplier using the fourth mathematical principle is presented in Fig. 2.29 [18] and it is represented by a self-biased differential amplifier. The V1 V2 differential input voltage of the multiplier core can be expressed as a function of the difference between the gate-source voltages of M1 and M2 transistors: V1 V2 ¼ VGS1 VGS2

(2.121)

2.2 Analysis and Design of Multiplier Circuits Fig. 2.30 Replicated core of the multiplier circuit (2) based on PR 2.4

121

ID3

ID3

M3

V1

M4

IOUT2

V2

M5

Replacing the square-root dependence of the gate-source voltage on the drain current for a MOS transistor biased in saturation and considering identical transistors, it results: rffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffi 2ID1 2ID2 V1 V2 ¼ K K

(2.122)

equivalent with: pffiffiffiffiffiffi pffiffiffiffiffiffi ID2 ¼ ID1

rffiffiffiffi K ðV1 V2 Þ 2

(2.123)

Squaring the previous relation, it can be obtained that: ID2 ¼ ID1

pffiffiffiffiffiffiffiffiffiffiffiffi K 2KID1 ðV1 V2 Þ þ ðV1 V2 Þ2 2

(2.124)

Thus, the output current of the differential core presented in Fig. 2.29, IOUT1 , will have the following expression: pffiffiffiffiffiffiffiffiffiffiffiffi K IOUT1 ¼ ID2 ID1 ¼ 2KID1 ðV1 V2 Þ þ ðV1 V2 Þ2 2

(2.125)

In order to implement the multiplying function, the first linear dependent on the differential input voltage term from the previous relation will be used. The same core permits to realize also the squaring function using the second term from the same relation. The simplest way to remove the last quadratic term is to use a similar structure with the circuit from Fig. 2.29 (presented in Fig. 2.30) [18] and having the ID1 current replaced with another current, ID3 . As the quadratic term from (2.125) does not depend on ID1 and ID3 currents, the consideration

122


VDD

Fig. 2.31 Differential amplifier for generating ID3 and ID1 currents

V3

M5 ID3

V4

M6 ID1

of the difference between the output currents of these similar structures will cancel out the undesired term. Similarly with the previous analysis, the output current of the circuit from Fig. 2.30 will have the following expression: pffiffiffiffiffiffiffiffiffiffiffiffi K IOUT2 ¼ ID4 ID3 ¼ 2KID3 ðV1 V2 Þ þ ðV1 V2 Þ2 2

(2.126)

The difference between the output currents IOUT1 and IOUT2 will be IOUT ¼ IOUT1 IOUT2 ¼

pffiffiffiffiffiffipffiffiffiffiffiffi pffiffiffiffiffiffi 2K ID3 ID1 ðV1 V2 Þ

(2.127)

The ID3 and ID1 currents are generated by another differential amplifier M5–M6, having V3 V4 as differential input voltage (Fig. 2.31). For this structure, considering that its composing transistors are biased in saturation, it is possible to write: pffiffiffiffiffiffi pffiffiffiffiffiffi ID3 ID1 ¼

rffiffiffiffi rffiffiffiffi K K ½ðVDD V3 VT Þ ðVDD V4 VT Þ ¼ ðV4 V3 Þ (2.128) 2 2

Replacing (2.128) in (2.127) it results the multiplying function: IOUT ¼ K ðV1 V2 Þ ðV4 V3 Þ

(2.129)

The complete circuit of the multiplier is presented in Fig. 2.32 [18]. The differential amplifier from Fig. 2.31 is replaced with two parallel-connected differential amplifiers M5, M50 –M6, M60 because ID1 and ID3 currents must be duplicated for biasing the differential amplifiers, M1–M2 and M3–M4. Another possible implementation of a voltage multiplier uses the symmetrical structure presented in Fig. 2.33. The multiplier is composed from two self-biased differential amplifiers (M5–M6 and M8–M9, respectively), their active loads being represented by


123 VDD

V4

M6

M6’

M5’

ID1

V3

M5 ID3

ID3

ID1

M7

M8 IOUT1

IOUT2

IOUT IOUT1

M3

V1

M1

M4

M2

V2

Fig. 2.32 The complete implementation of the multiplier circuit (2) based on PR 2.4

VDD M10

M7 V4 V3

M5

M9

M6 IOUT1 V1

M1

V3

M8

IOUT IOUT2

M11 M2

M12 M3

V2 M4 -VDD


M1–M2 and M3–M4 current mirrors. Analyzing the M5–M6 differential amplifier, the V3 V4 differential voltage can be expressed as a difference between two gatesource voltages: V3 V4 ¼ VSG6 VSG5

(2.130)

Replacing the square-root dependence of the gate-source voltage on the drain current for a MOS transistor biased in saturation and considering identical transistors, it results: rffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffi 2ID6 2ID1 V3 V4 ¼ (2.131) K K

124


The ID6 current can be expressed from the previous relation as follows: pffiffiffiffiffiffi pffiffiffiffiffiffi ID6 ¼ ID1 þ

rffiffiffiffi K ðV3 V4 Þ 2

(2.132)

resulting: ID6 ¼ ID1 þ


(2.133)

The differential output current of the M5–M6 differential amplifier will be: IOUT1 ¼ ID6 ID1 ¼


(2.134)

Similarly, the differential output current of the M8–M9 differential amplifier will have the following expression: IOUT2 ¼


(2.135)

The M11–M12 current mirror computes the IOUT output current of the entire multiplier structure from Fig. 2.33: IOUT ¼ IOUT2 IOUT1 ¼

pffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi 2K ðV3 V4 Þ ID4 ID1

(2.136)

Using the squaring dependence of the drain current on the gate-source voltage for a MOS transistor biased in saturation, it is possible to write:

IOUT

pffiffiffiffiffiffi ¼ 2K ðV3 V4 Þ

"rffiffiffiffi # rffiffiffiffi K K ðV2 þ VDD VT Þ ðV1 þ VDD VT Þ 2 2 (2.137) ¼ KðV3 V4 ÞðV2 V1 Þ

A voltage multiplier based on the compensation of the squaring characteristic of the MOS transistor biased in saturation region using two square-root circuits is presented in Fig. 2.34 [19]. The differential input voltage can be expressed as follows: V1 V2 ¼ VGS3 VGS4

rffiffiffiffi 2 pffiffiffiffi pffiffiffiffiffi0 ¼ I 2 I2 K

(2.138)


125

VDD M5

M6 M9

I2

I1

V3

M2 M1

V4

I2 V1

M10

I1 M3

M7

IO

IO

I1

I2

IOUT1

I1’

I2' M4

IOUT2 V2

M8

IO


resulting: I2 0 ¼ I2 þ

pffiffiffiffiffiffi pffiffiffiffi K ðV1 V2 Þ2 2K ðV1 V2 Þ I2 2

(2.139)

The output current of the square-rooting circuit is: IOUT2 ¼ I2 I2 0 ¼

pffiffiffiffiffiffi pffiffiffiffi K ðV1 V2 Þ2 þ 2K ðV1 V2 Þ I2 2

(2.140)

pffiffiffiffiffiffi pffiffiffiffi K ðV1 V2 Þ2 þ 2K ðV1 V2 Þ I1 2

(2.141)

Similarly: IOUT1 ¼ I1 I1 0 ¼ so: IOUT ¼ IOUT2 IOUT1 ¼

pffiffiffiffiffiffi pffiffiffiffi pffiffiffiffi 2K ðV1 V2 Þ I2 I1

(2.142)

The differential input voltage of M1–M2 differential amplifier will have the following expression: V3 V4 ¼ VGS2 VGS1

rffiffiffiffi 2 pffiffiffiffi pffiffiffiffi I2 I1 ¼ K

(2.143)

126


M

V1 IO

T

V2

T

V V1T

DA

IO

V2T

IOUT

V3

SQ

V4


resulting: IOUT ¼ K ðV1 V2 Þ ðV3 V4 Þ

(2.144)

A possible implementation of a voltage multiplier has the block diagram presented in Fig. 2.35. The “DA” block represents a classical active-load differential amplifier, having the common-sources point biased at a V potential fixed by the circuit “M”. This circuit computes the arithmetical mean of input potentials, having the goal of obtaining a very good linearity of the entire structure, with the contribution of “T” blocks (which are used for introducing a translation of input potentials). A squaring circuit, “SQ”, is used for generating the biasing current of the two translation blocks, IO .

The “DA” (Differential Amplifier) block The “DA” block is implemented as a classical active-load differential amplifier, having the concrete realization presented in Fig. 2.36 [20]. Considering a biasing in saturation of the MOS devices from Fig. 2.36, the output current of the differential amplifier can be expressed as follows: IOUT ¼ I2 I1 ¼

K K ðVSG2 VT Þ2 ðVSG1 VT Þ2 2 2

(2.145)


127

V

Fig. 2.36 Multiplier circuit (5) based on PR 2.4 – implementation of DA block

V1T

M1 I1

V2T

M2 I2

M3

IOUT M4


K ðVSG2 VSG1 Þ ðVSG1 þ VSG2 2VT Þ 2

(2.146)

Because: VSG1 ¼ V V1T

(2.147)

VSG2 ¼ V V2T

(2.148)

and:

it results: IOUT ¼

K ðV1T V2T Þ ð2V V1T V2T 2VT Þ 2

(2.149)

In order to obtain a linear transfer characteristic IOUT ðV1T V2T Þ, it is necessary that the second parenthesis from (2.149) to be constant with respect to the differential input voltage, V1T V2T : 2V V1T V2T 2VT ¼ A ¼ ct:

(2.150)

resulting the necessity of implementing a V voltage equal with: V¼

V1T þ V2T A þ VT þ 2 2

(2.151)

128


Fig. 2.37 Multiplier circuit (5) based on PR 2.4 – implementation of T block

IO

IO M9

V1

V1T

M9’

V2

V2T

The “T” (Translation) Block The translation of the V potential by VT þ A=2 (relation (2.151)) can be obtained using “T” block, having the implementation presented in Fig. 2.37 [20]. Because the same IO current is passing through all transistors from Fig. 2.37, it is possible to write that: V1 ¼ V1T


(2.152)

and: V2 ¼ V2T þ VT þ


(2.153)

So, both V1 and V2 input potentials are DC shifted with the same amount, pffiffiffiffiffiffiffiffiffiffiffiffiffi VT þ 2IO =K .

The “M” (Arithmetic Mean) Block In order to obtain the arithmetic mean of input potentials expressed by relation (2.151), the circuit from Fig. 2.38 [20] can be used, having the advantage of using only MOS transistors, biased in saturation region. The expression of the V potential is: V¼

V1 þ V2 2

(2.154)

Replacing (2.152) and (2.153) in (2.156), it can be obtained: V1T þ V2T V¼ þ VT þ 2


(2.155)


V1

M14

129

IO /2

IO /2

M15

M15’

IO

M14’

V2

IO V

Fig. 2.38 Multiplier circuit (1) based on PR 2.4 – implementation of M block

pffiffiffiffiffiffiffiffiffiffiffiffiffi Comparing relations (2.151) and (2.157), it results that A ¼ 2 2IO =K , so: IOUT

K ¼ ðV1T V2T Þ2 2


(2.156)

or: IOUT ¼

pffiffiffiffiffiffiffiffiffiffi 2KIO ðV1T V2T Þ

(2.157)

equivalently (using (2.152) and (2.153)) with: IOUT ¼


(2.158)

IOUT ¼


(2.159)

resulting:

pffiffiffiffiffiffiffiffiffiffi Gm ¼ 2KIO being the equivalent transconductance of the differential amplifier. Because IO biasing currents of the translation blocks “T” from Fig. 2.37 are generated by a voltage squaring circuit having as input a differential voltage, V3 V4 , it results a multiplier circuit with a very good linearity. So, replacing in (2.159) the expression of IO current: IO ¼

K ðV3 V4 Þ2 4

(2.160)

it results: K IOUT ¼ pffiffiffi ðV1 V2 Þ ðV3 V4 Þ 2

(2.161)

130



IOUT1

V1

IOUT2

M3 M4

M5 M6

IO

IO M1

M2

V2

ISS

2.2.1.5

Multiplier Circuits Based on the Fifth Mathematical Principle (PR 2.5)

A method for linearizing the characteristic of a voltage multiplier using the fifth mathematical principle consists in the extension of the linearization technique designed for the CMOS differential amplifier, based on the biasing of the differential structure at a current that is the sum between a constant current and a component proportional with the square of the differential input voltage. The relatively simple implementation of multiplier circuits based on this mathematical principle impose them for a large area of applications in VLSI designs. The expression of the differential output current of the classical CMOS differential amplifier is:

IOUT

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ISS VI2 ¼ KVI K 4

(2.162)

VI representing the differential input voltage and ISS being the biasing current of the differential amplifier. The multiplier with linear characteristic based on the previous presented principle is presented in Fig. 2.39 [21].


131

The output current of the previous voltage multiplier can be expressed as: IOUT ¼ IOUT1 IOUT2 ¼ ðID3 þ ID5 Þ ðID4 þ ID6 Þ ¼ ðID3 ID4 Þ ðID6 ID5 Þ

(2.163)

The differential output currents of the differential amplifiers M3–M4 and M5–M6 can be obtained using the general relation (2.162): ID3 ID4

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ID1 þ IO V12 ¼ KV1 K 4

(2.164)

and: ID6 ID5

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ID2 þ IO V12 ¼ K V1 K 4

(2.165)

The linearization technique is based on the utilization of a current IO proportional with the squaring of the differential input voltage V1 : IO ¼

KV12 4

(2.166)

Replacing (2.164), (2.165) and (2.166) in (2.163), it results the following expression of the output current of the voltage multiplier: IOUT ¼

pffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi K V1 ID1 ID2

(2.167)

Analyzing M1–M2 differential amplifier, the V2 differential input voltage can be expressed as follows: V2 ¼ VGS1 VGS2 ¼

rffiffiffiffiffiffiffiffiffi! 2ID1 VT þ K

rffiffiffiffi 2 pffiffiffiffiffiffi pffiffiffiffiffiffi ID1 ID2 ¼ K

rffiffiffiffiffiffiffiffiffi! 2ID2 VT þ K (2.168)

From (2.168) and (2.167), it results the expression of the IOUT output current as a function on the differential input voltages, V1 and V2 : K IOUT ¼ pffiffiffi V1 V2 2

(2.169)

132


A similar method, useful for low-voltage operation, is presented in Fig. 40 [21]. In order to reduce the minimal value of the supply voltage, the stacked architecture is replaced with a folded structure. The IOUT1 IOUT2 differential output current of the folded voltage multiplier is: IOUT1 IOUT2 ¼ ðID3 þ ID5 Þ ðID4 þ ID6 Þ ¼ ðID3 ID4 Þ ðID6 ID5 Þ

(2.170)

The differential output currents of the differential amplifiers M3–M4 and M5–M6 can be obtained using the general relation (2.162): ID3 ID4

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ISS þ IO ID1 V12 ¼ KV1 K 4

(2.171)

and: ID6 ID5

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ISS þ IO ID2 V12 ¼ KV1 K 4

(2.172)

The linearization technique is based on the utilization of a IO current, proportional with the square of the differential input voltage V1 : IO ¼

KV12 4

(2.173)

Replacing (2.171), (2.172) and (2.173) in (2.170), it results the following expression of the output current of the voltage multiplier: IOUT ¼

pffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ISS ID1 ISS ID2 K V1

(2.174)

The M1–M2 differential amplifier is biased at the constant current, ISS , so ID1 þ ID2 ¼ ISS . The previous relation can be rewritten as: IOUT ¼

pffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi K V1 ID2 ID1

(2.175)

Similarly with the previous voltage multiplier, it results the following expression of the IOUT output current as a function on V1 and V2 differential input voltages: K IOUT ¼ pffiffiffi V1 V2 2

(2.176)


133

VDD ISS

IOUT2

IOUT1

M1 M2

M3 M4

M5 M6

V2 V1

ISS

IO

ISS

IO

Fig. 2.40 Multiplier circuit (1) based on PR 2.5 – circuit core of the folded version

VDD M2

M4

M1

M3

IOUT1

IOUT2

ISS’

V2

MQ5 MQ6

M6

M8

M12

M14

M5

M7 M11

M13

ISQ

MQ1 MQ2

MQ3 MQ4

MS1 MS2

M9

V1A V1

ΔV

V1B MS3 MS4

VC1

ISQ

ISQ

M19

M17

M15

M20

M18

M16

M10

Fig. 2.41 Multiplier circuit (1) based on PR 2.5 – complete implementation of the folded version

The complete implementation of the folded voltage multiplier from Fig. 2.40 is presented in Fig. 2.41 [21]. The M1 and M2 transistors from Fig. 2.40 have been replaced in Fig. 2.41 with MQ5 and MQ6, while the differential amplifiers, M3–M4 and M5–M6 from Fig. 2.40 were renamed MQ1–MQ2 and MQ3–MQ4, respectively. Noting with ISQ the drain

134


currents of transistors M11–M20 and considering that the cascode current mirrors implemented using M11–M20 transistors are not affected by the channel-length modulation, the ISQ current will have the following expression: ISQ ¼ IDMS1 þ IDMS2

(2.177)

For simplifying the computations, the differential input voltage V1 ¼ V1A V1B , can be expressed using a linear relation between the common-mode and the differential-mode input voltages, VC1 and v1 : V1A ¼ VC1

v1 2

(2.178)

V1B ¼ VC1 þ

v1 2

(2.179)

and:

Using this expression of V1 voltage, the ISQ current can be expressed as follows: K K ðV1A VT Þ2 þ ðV1B VT Þ2 2 2 2 K 2 K v1 v1 ¼ VC1 VT þ VC1 þ VT 2 2 2 2 ISQ ¼

(2.180)

resulting: ISQ ¼ K ðVC1 VT Þ2 þ

K 2 v 4 1

(2.181)

Comparing Fig. 2.40 with Fig. 2.41, it results that ISQ current from Fig. 2.41 must be equal with a sum between a constant current, ISS and a IO current, proportional with the squaring of the input voltage: ISS ¼ K ðVC1 VT Þ2

(2.182)

and: IO ¼

K 2 v 4 1

(2.183)

For a proper operation of the folded multiplier, the ISS 0 biasing current of the differential amplifier MQ5–MQ6 must be equal with ISS . This ISS 0 current is


V1A

T14

135

IO /2

IO /2

T15

T15’

IO

T14’

V1B

IO VO

Fig. 2.42 Arithmetical mean circuit

generated by the MS3–MS4 pair, each transistor being biased at the common-mode component of the input voltage V1 : ISS 0 ¼ IDMS3 þ IDMS4

(2.184)

resulting: ISS 0 ¼ 2

K ðVC1 VT Þ2 ¼ K ðVC1 VT Þ2 ¼ ISS 2

(2.185)

The M9 and M10 transistors are used for transferring the differential input voltage, V1 , on the input of cross-connected differential amplifiers MQ1–MQ2 and MQ3–MQ4: DV ¼ ðV1B þ VSG9 Þ ðV1A þ VSG10 Þ

(2.186)

The M9 and M10 transistors being identical and working at the same drain current, it results VSG9 ¼ VSG10 . So: DV ¼ V1B V1A ¼ V1

(2.187)

Concluding that the circuits presented in Fig. 2.40 and Fig. 2.41 are functionally identical, the IOUT output current of the complete implementation of the folded voltage multiplier circuit can be obtained replacing in (2.176) V1 with V1 : K IOUT ¼ IOUT1 IOUT2 ¼ pffiffiffi V1 V2 2

(2.188)

An arithmetical mean circuit (Fig. 2.42) [22] must be used for extracting the common-mode component VC1 of the input voltage V1 . The VO output voltage for this circuit will be: VO ¼

V1A þ V1B ¼ VC1 2

(2.189)

136



IOUT1

IOUT2

V1

V2 IO I12

I34

SQ II V3

SQ I

V4

The voltage multiplier presented in Fig. 2.43 [23], using the fifth mathematical principle (PR 2.5) is derived from a differential amplifier with linear transfer characteristic. The differential output current, IOUT , for the circuit presented in Fig. 2.43 will present a strong nonlinear dependence on the V1 V2 differential input voltage, that can be expressed as: IOUT ¼ IOUT1 IOUT2

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi KðV1 V2 Þ2 K 2 ðV1 V2 Þ4 ¼ IO IO 4IO 2

(2.190)

equivalent with: IOUT

V1 V2 ¼ 2

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 4KIO K 2 ðV1 V2 Þ2

(2.191)

IO being the biasing current of the differential structure. So, superior-order distortions will characterize the behavior of this structure, imposing the design of a linearization technique for removing the superior-order terms from the transfer characteristic. The method for obtaining a linear transfer characteristic is to obtain the IO bias current of the entire differential structure as a sum of two terms: I12 , proportional with the squaring of the V1 V2 differential input voltage and I34 , proportional with the squaring of another differential voltage, V3 V4 : IO ¼ I12 þ I34 ¼

K K ðV1 V2 Þ2 þ ðV3 V4 Þ2 4 4

(2.192)


137

VDD IOUT

M1a

V1

I3 M1b

M2a

V2

I4

I1

M1c M2c

M2b

I2 2VT


resulting, in this case, a perfect proportionality of the output current on the differential input voltages: IOUT ¼

2.2.1.6


(2.193)

Multiplier Circuits Based on the Sixth Mathematical Principles (PR 2.6)

The area of applications of multiplier structures based on PR 2.6 is restricted to the circuits that do not require the multiplication of differential input voltages. The following voltage multiplier circuit is based on the sixth mathematical principle. In order to obtain a linear characteristic of the circuit, a perfect symmetrical structure with respect to the two input potentials is presented in Fig. 2.44 [24, 25]. Considering an operation in saturation for all MOS devices, the output current can be expressed as: IOUT ¼ ðI1 þ I2 Þ ðI3 þ I4 Þ

(2.194)

where: I1 ¼

2 K V1 þ V2 VT 2 2

(2.195)

K 2 V 2 T

(2.196)

I2 ¼

2 K V1 VT I3 ¼ 2 2

(2.197)

138


VDD

IOUT

V2

M1

M2

M3

M4

V1


2 K V2 VT I4 ¼ 2 2

(2.198)

For the previous mathematical relations, it results a perfect linear dependence of the output current on the input voltages: IOUT ¼

K V1 V2 2

(2.199)

Another possible implementation of a voltage multiplier circuit using the sixth mathematical principle (PR 2.6) is presented in Fig. 2.45. The output current of the voltage multiplier can be expressed as follows: IOUT ¼ ðID1 þ ID2 Þ ðID3 þ ID4 Þ

(2.200)

where: ID1 ¼

2 K V1 þ V2 VT 2 2

(2.201)

K 2 V 2 T

(2.202)

ID2 ¼

ID3

ID4

2 K V1 VT ¼ 2 2

(2.203)

2 K V2 ¼ VT 2 2

(2.204)


V1

SQ I

139

V2 V1

IOUT1

SQ II IOUT2

-V2

IOUT

CM Fig. 2.46 Multiplier circuit (1) based on PR 2.7 – block diagram

From the previous mathematical relations it results a perfect linear dependence of the output current on the input voltages: IOUT ¼

2.2.1.7

K V1 V2 2

(2.205)

Multiplier Circuits Based on the Seventh Mathematical Principles (PR 2.7)

Practically derived from the implementation of voltage squaring circuits, the multiplier structures that use as functional basis PR 2.7 find many applications in analog signal processing. A similar approach of a voltage multiplier uses 2 v squaring circuit, connected as it is shown in Fig. 2.46. Considering that the squaring circuits have an output current proportional with KDV 2 =2, DV being the differential input voltage, the output current of the circuit presented in Fig. 2.46 will have the following expression: IOUT ¼ IOUT2 IOUT1 ¼

K K ðV1 þ V2 Þ2 ðV1 V2 Þ2 ¼ 2KV1 V2 2 2

(2.206)

In order to obtain the multiplying function using two squaring circuits, a similar method is proposed in Fig. 2.47. The squaring circuits from Fig. 2.46 have been replaced in Fig. 2.47 with two particular implementations of a differential amplifier (presented in Fig. 2.20). The implementation of the voltage multiplier is shown in Fig. 2.28 [13]. The IOUT output current will have the following expression: h i h i IOUT ¼ 2IO þ K ðV1 þ V2 Þ2 2IO þ K ðV1 V2 Þ2 ¼ 4KV1 V2

(2.207)

140


CM IOUT

V1

-V2 V1

DA I

DA II

V2

IO

IO


Two complete realizations of the previous circuit, using specific implementations of VO sources from Fig. 2.48, are shown in Fig. 2.49 [13] and Fig. 2.50 [13], respectively. A multiplier circuit can be designed starting from a squaring characteristic implemented using a classical differential amplifier (Fig. 2.51) [18]. The differential input voltage for the circuit presented in Fig. 2.51 can be expressed as follows: rffiffiffiffi 2 pffiffi pffiffiffiffiffi I IO V1 V2 ¼ K

(2.208)

resulting: I ¼ IO þ


(2.209)

In order to obtain the multiplying function, four differential amplifiers from Fig. 2.51 can be connected as it is shown in Fig. 2.52. The output current of the multiplier circuit will have the following expression: IOUT ¼ I1 þ I2 I3 I4

(2.210)

resulting: K K ðV1 V2 Þ2 þ ðV1 þ V2 Þ2 2 2 K K 2 ðV1 þ V2 Þ ðV1 V2 Þ2 ¼ 4KV1 V2 2 2 IOUT ¼

(2.211)


141

CM

IOUT1

IOUT2 M1

V1

IOUT1 VO -

+

+

IO

IO

-V2

M2

IO IO

VO -

IOUT2

IO

IO IOUT

I OUT1’

IOUT2’ M3

V1

IOUT1’ V- O + IO

M4

IO IO +

IO

VO -

V2 IOUT2’

IO

IO

Fig. 2.48 Multiplier circuit (2) based on PR 2.7 – principle implementation VDD

IO V1

IOUT IOUT1

IOUT2

-V2

V1

IOUT1’

IOUT2’

V2

-VDD

Fig. 2.49 Multiplier circuit (2) based on PR 2.7 – first implementation

The circuit presented in Fig. 2.53 [12] represents a four-quadrant multiplier with balanced inputs. The difference between the gate-source voltages of M1 and M3 transistors can be expressed as follows: V1 V2 ¼ VGS1 VGS3

(2.212)

142

2 Voltage and Current Multiplier Circuits VDD

IO

IOUT IOUT1’

IOUT2

IOUT1

IOUT2’

-V2 V1

V1

V2

-VDD

Fig. 2.50 Multiplier circuit (2) based on PR 2.7 – second implementation

a

b I

IO

V1

I

V2 I + IO

V1

IO V2

DA

Fig. 2.51 Multiplier circuit (3) based on PR 2.7 – circuit core

CM IOUT I1 - V1

I2

IO

DA I

V2

V1

IO

DA II

I3 -V2 - V1

I4

IO

DA III

- V2

V1

IO

DA IV

V2


For a biasing in saturation of all MOS transistors from Fig. 2.53, it results: rffiffiffiffi 2 pffiffiffiffi pffiffiffiffiffi V1 V2 ¼ I 1 IO K

(2.213)


143 VDD

IOUT2

IOUT1

I2

I1 V1

M1 V2

M3

I5

I4 M4 - V2

M2

M6

M5

V1

- V1

IO

- VDD


So, the expression of I1 current will be: I1 ¼ IO þ


(2.214)

Similarly, computing the difference between the gate-source voltages of M2–M3 transistors, it results: I2 ¼ IO þ


The I1 I2 differential current will have the following expression: pffiffiffiffiffiffiffiffiffiffi I1 I2 ¼ 2V1 2KIO 2KV1 V2

(2.215)

(2.216)

Similarly, for the structure implemented using M4–M6 transistors, the differential output current can be expressed as follows: pffiffiffiffiffiffiffiffiffiffi I4 I5 ¼ 2V1 2KIO 2KV1 V2 (2.217) The differential output current for the entire multiplier structure presented in Fig. 2.53 will be: IOUT ¼ IOUT1 IOUT2 ¼ I2 þ I5 I1 I4 ¼ 4KV1 V2

2.2.1.8

(2.218)

Multiplier Circuits Based on Different Mathematical Principles (PR 2.Da)

Alternate implementations of the previous presented multiplier circuits are based on different mathematical principles. The utilization of the bulk as an active terminal

144


Fig. 2.54 Multiplier circuit (1) based on PR 2.Da – circuit core

IL

V3

IR

V1

V2

gives the possibility of reducing the complexity of a multiplier circuit. The core of the following presented multiplier is presented in Fig. 2.54 [11]. A model of the MOS transistor biased in saturation that includes the dependence of the drain current on the bulk-source voltage is expressed by the following relation: ID ¼

K 2 2 VGS VT AVBS BVBS 2

(2.219)

A and B being constants. The differential output current of the multiplier core from Fig. 2.54, IL IR , will be: IL IR ¼

2 K 2 K V1 VT AV3 BV32 V2 VT AV3 BV32 2 2

(2.220)

K ðV1 V2 Þ V1 þ V2 2VT 2AV3 2BV32 2

(2.221)

resulting: IL IR ¼

In order to obtain the multiplying function, two circuits from Fig. 2.54 can be cross-connected, resulting the multiplier presented in Fig. 2.55 [11]. For this circuit, the differential output current can be expressed as the difference between the differential output currents of each core: IOUT1 IOUT2 ¼ ðIL2 þ IR1 Þ ðIL1 þ IR2 Þ ¼ ðIL2 IR2 Þ ðIL1 IR1 Þ

(2.222)

Replacing (2.221) in (2.222), it results: K ðV1 V2 Þ V1 þ V2 2VT 2AV4 2BV42 2 K ðV1 V2 Þ V1 þ V2 2VT 2AV3 2BV32 2

IOUT1 IOUT2 ¼

(2.223)

equivalent with:

IOUT1 IOUT2 ¼ K ðV1 V2 Þ AðV3 V4 Þ þ B V32 V42 ¼ K ðV1 V2 ÞðV3 V4 Þ½A þ BðV3 þ V4 Þ

(2.224)


145

IOUT2

IOUT1 IL1

V3

IR1

IL2

V4

IR2

V1

V2

Fig. 2.55 Multiplier circuit (1) based on PR 2.Da – complete implementation

If the V1 , V2 , V3 and V4 input voltages contain common-mode terms (V12 and V34 ) and differential-mode terms (v12 and v34 ) as follows: V1 ¼ V12 þ

v12 2

(2.225)

V2 ¼ V12

v12 2

(2.226)

V3 ¼ V34 þ

v34 2

(2.227)

V4 ¼ V34

v34 2

(2.228)

it results: IOUT1 IOUT2 ¼ Kv12 v34 ðA þ 2BV34 Þ

(2.229)

so, the differential output current of the voltage multiplier presented in Fig. 2.55 will be proportional with the product of the differential-mode components of input voltages. An alternate approach of a voltage multiplier, based on bulk-driven MOS devices using another model for the dependence of the threshold voltage VT on the biasing of the bulk (VBS ), is shown in Fig. 2.56 [26]. The differential output current of this multiplier can be expressed as follows: IOUT1 IOUT2 ¼ ðID1 þ ID3 Þ ðID2 þ ID4 Þ ¼ ðID1 ID2 Þ þ ðID3 ID4 Þ (2.230) where it is considered that the drain current of a MOS transistor depends on the gate-source voltage following a quadratic law (2.231) and on the bulk-source voltage as a consequence of the bulk effect using the mathematical relation (2.232): ID ¼

K ðVGS VT Þ2 2

(2.231)

146


IOUT1

IOUT2

V3 M1

V4 M2

V2

M3

M4

V1

V1

Fig. 2.56 Multiplier circuit (2) based on PR 2.Da

VT ¼ VT0 þ g

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffi 2FF VBS 2FF

(2.232)

VT being the threshold voltage of the MOS transistor biased at a bulk-source voltage equal with VBS , g is a model parameter and FF represents the Fermi potential. Replacing (2.232) in (2.231) and using the fact that VT1 ¼ VT2 and VT3 ¼ VT4 (because VBS1 ¼ VBS2 ¼ V3 and VBS3 ¼ VBS4 ¼ V4 ), it results the following expression of the output current: K K IOUT1 IOUT2 ¼ ðV1 V2 Þ ðV1 þ V2 2VT1 Þ þ ðV2 V1 Þ ðV1 þ V2 2VT3 Þ 2 2 (2.233) so: IOUT1 IOUT2 ¼ K ðV1 V2 Þ ðVT3 VT1 Þ

(2.234)

Using the (2.232) relation that models the bulk effect, the previous expression of the output current can be rewritten as follows: pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2FF V4 2FF V3 IOUT1 IOUT2 ¼ K ðV1 V2 Þg r ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffi V4 V3 1 (2.235) ¼ K ðV1 V2 Þg 2FF 1 2FF 2FF theffi Fermi potential, it is For V3 and V4 input signals much smaller than pffiffiffiffiffiffiffiffiffiffi possible to use the first-order Taylor expansion 1 þ x ffi 1 þ x=2, for x

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