SPICE Circuit Handbook

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SPICE Circuit Handbook

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SPICE Circuit Handbook Steven M. Sandler Charles Hymowitz

McGraw-Hill New York

Chicago San Francisco Lisbon London Madrid Mexico City Milan New Delhi San Juan Seoul Singapore Sydney Toronto

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Copyright © 2006 by The McGraw-Hill Companies, Inc. All rights reserved. Manufactured in the United States of America. Except as permitted under the United States Copyright Act of 1976, no part of this publication may be reproduced or ditributed in any form or by any means, or stored in a database or retrieval system, without the prior written permission of the publisher. 0-07-149133-3 The material in this eBook also appears in the print version of this title: 0-07-146857-9. All trademarks are trademarks of their respective owners. Rather than put a trademark symbol after every occurrence of a trademarked name, we use names in an editorial fashion only, and to the benefit of the trademark owner, with no intention of infringement of the trademark. Where such designations appear in this book, they have been printed with initial caps. McGraw-Hill eBooks are available at special quantity discounts to use as premiums and sales promotions, or for use in corporate training programs. For more information, please contact George Hoare, Special Sales, at [email protected] or (212) 904-4069. TERMS OF USE This is a copyrighted work and The McGraw-Hill Companies, Inc. (“McGraw-Hill”) and its licensors reserve all rights in and to the work. Use of this work is subject to these terms. Except as permitted under the Copyright Act of 1976 and the right to store and retrieve one copy of the work, you may not decompile, disassemble, reverse engineer, reproduce, modify, create derivative works based upon, transmit, distribute, disseminate, sell, publish or sublicense the work or any part of it without McGraw-Hill’s prior consent. You may use the work for your own noncommercial and personal use; any other use of the work is strictly prohibited. Your right to use the work may be terminated if you fail to comply with these terms. THE WORK IS PROVIDED “AS IS.” McGRAW-HILL AND ITS LICENSORS MAKE NO GUARANTEES OR WARRANTIES AS TO THE ACCURACY, ADEQUACY OR COMPLETENESS OF OR RESULTS TO BE OBTAINED FROM USING THE WORK, INCLUDING ANY INFORMATION THAT CAN BE ACCESSED THROUGH THE WORK VIA HYPERLINK OR OTHERWISE, AND EXPRESSLY DISCLAIM ANY WARRANTY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. McGraw-Hill and its licensors do not warrant or guarantee that the functions contained in the work will meet your requirements or that its operation will be uninterrupted or error free. Neither McGraw-Hill nor its licensors shall be liable to you or anyone else for any inaccuracy, error or omission, regardless of cause, in the work or for any damages resulting therefrom. McGraw-Hill has no responsibility for the content of any information accessed through the work. Under no circumstances shall McGraw-Hill and/or its licensors be liable for any indirect, incidental, special, punitive, consequential or similar damages that result from the use of or inability to use the work, even if any of them has been advised of the possibility of such damages. This limitation of liability shall apply to any claim or cause whatsoever whether such claim or cause arises in contract, tort or otherwise. DOI: 10.1036/0071468579

This book is dedicated to my wife Susan and my daughters Shanna and Rachel. It is you who encourage me to be the best I can be. Steven M. Sandler

This book is dedicated to my wife Teresa and my three wonderful blessings, Mitchell, Olivia, and Makenna. You make it all worthwhile. Charles Hymowitz

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For more information about this title, click here

Contents

Acknowledgments

xi

Chapter 1. Introduction

1

Chapter 2. Description of the PSpice, IsSpice, SIMetrix, and Micro-Cap Simulators

7

Basic Overview of SPICE SPICE syntax and tutorial DC analysis Transient analysis AC analysis Simulation Types and Data Acquisition Convergence Problems Steps to avoid common mistakes DC convergence solutions Transient convergence solutions AC convergence solutions

Chapter 3. Filter Circuits Fourth-Order Butterworth Low Pass Filter Fourth-Order Butterworth High Pass Filter Fourth-Order Butterworth Band Pass Filter Bessel–Thompson Delay Low Pass Filter Bessel–Thompson Delay Low Pass Filter with Pulse Shaper Inverted Bessel–Thompson Delay High Pass Filter Chebyshev Band Pass Filter Chebyshev Low Pass Filter Chebyshev High Pass Filter Electromagnetic Interference (EMI) Filter

Chapter 4. Power Conversion Circuits LM117 Three-Terminal Linear Regulator LM78S40 Simple Switcher DC-to-DC Converter

10 10 11 12 13 14 14 14 15 16 17

19 19 24 25 27 33 37 39 46 52 52

61 61 68

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Contents

UA723 Hysteretic Buck Regulator 1524A Buck Regulator Low Drop-Out Regulator STR6600 Quasi-Resonant Discontinuous Flyback Discontinuous Flyback Converter

Chapter 5. Electronic Load Circuits Power Section of an Electronic Load Positive DC to Negative DC Comparator Converter Built-in Variable Electronic Load Adjustment Electronic Load Using Power BJT Transistors

Chapter 6. Instrumentation Circuits 555 Timer 555 Missing-Pulse Detector Class AB Amplifier Window Detector Voltage Clamp Resistance to Voltage Polarity Gain

Chapter 7. Logic Circuits Binary Counter Binary Decoder Set-Reset Latch Staircase Generator

Chapter 8. Resonator/Oscillator Circuits 555 Timer Oscillator Fourth-Order Butterworth Low Pass Oscillator Hex Inverter Oscillator Fourth-Order Butterworth No-Offset Low Pass Oscillator Harmonic Neutralized Sine-Wave Oscillator Colpitts Oscillator Schmitt Trigger Oscillator LM111 Oscillator

Chapter 9. Gate Drive Circuits UC1846 50% Duty Cycle Gate Drive Circuit 555 Pulse-Shaped MOSFET Driver Zero-to-100% Duty Cycle Driver

Chapter 10. Voltage Multiplier Circuits AC-to-DC Voltage Doubler Cascade Doubler

73 82 93 106 112

119 119 129 133 137

143 143 148 160 161 176 176 186

195 195 199 205 208

215 215 216 222 228 236 244 250 256

261 262 266 269

277 277 281

Contents

Bridge AC-to-DC Doubler AC-to-DC Quadrupler AC-to-DC Octupler (× 8) High Voltage, High Current DC-to-DC Doubler

Index

305

ix

285 287 292 297


Acknowledgments

We would like to thank AEi Systems personnel, including Mark Kwamusi, Greg Boger, and Danny Chow, for performing all of the simulations for this book in an effort to obtain the best relative run times possible, capturing and running most if not all simulations on the same computer. Thanks to Steve Chapman, the publisher at McGraw-Hill, for continuing to provide us these opportunities to write. Thanks to John Wagner and his guys at Catena Software Ltd. for creating SIMetrix, Andy Thompson and the guys at Spectrum Software for creating Micro-Cap, Larry Meares and Intusoft for creating IsSpice, and OrCAD for creating PSpice. Thanks to Priyanka Negi and the staff at TechBooks for the outstanding effort they put into creating this book. Thanks to Ron Rohrer, Larry Nagel, and all the students at the University of California, Berkeley, who worked hard in 1969 and 1970 to develop the first computer simulation software, Cancer (Computer Analysis of Non-Linear Circuits Excluding Radiation). This effort would result in the release of SPICE into the public domain in 1971. Steven M. Sandler Charles Hymowitz

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Copyright © 2006 by The McGraw-Hill Companies, Inc. Click here for terms of use.


SPICE Circuit Handbook

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Chapter

1 Introduction

Since its introduction in 1971, SPICE (Simulation Program with Integrated Circuit Emphasis) has become the most popular analog simulation tool in use today. In the last 15 years, we have seen explosive growth in the use of SPICE, with the addition of Berkeley SPICE 3 enhancements, and support for C code model and mixed-mode simulation using XSPICE (Cox et al. 1992, Kielkowski 1994).We have also seen many new companies emerge as developers of SPICE-based simulation tools, most of which are currently available for the PC platform. Each vendor of SPICE simulation software has added features such as Monte Carlo analysis, schematic entry, and post simulation waveform processing, as well as extensive model libraries. In most cases, the manufacturers have modified the algorithms for controlling convergence and have added new parameters or syntax for component models. As a result, each electronic design automaton (EDA) tool vendor has the basic Berkeley SPICE 2 features and a unique set of capabilities and performance enhancements. We have also seen component manufacturers providing SPICE model support. Many of these manufacturers provide models of components such as MOSFETs, transistors, and operational amplifiers. Most of these models are available for free via the manufacturer’s web sites, though not all are accurate or well documented. One company filling the void in the modeling area, especially with respect to power electronics, is AEi Systems, LLC (AEi Systems 2005; www.AENG.com). The ability of computers to simulate electronic circuits is increasing every day. The often-quoted “Moore’s law” states that the speed of microprocessors doubles nearly every 18 months. As computers become more powerful and more capable, computer simulation is becoming a significant tool in the design process.

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2

Chapter One

Unfortunately, there is still unwillingness in the electronic design community to embrace the abilities of computers to emulate circuit behavior. Many engineers still don’t take SPICE simulation seriously. Typically, a design engineer, on being shown a SPICE model of the impeding failure of his or her circuit, will reply, “That’s nice, but let’s see what the hardware does.” Even when the hardware fails, the engineer is more likely to investigate the charred and smoking breadboard than the SPICE model that predicted the result. The purpose of this book is to showcase the ability of SPICE, via the simulation tools of several EDA vendors, to accurately predict the behavior of electronic circuitry. The time it takes to run a simulation is orders of magnitude less than the time it takes to build the equivalent circuit on a breadboard. A simulation can be run through any number of environmental conditions with ease–conditions often unavailable or impractical to duplicate in a laboratory environment. Circuit stimulus and tolerances and their effect on the operation of the circuit can be easily evaluated. Still, there are limitations to the capabilities of SPICE and similar circuit simulators. While the sophistication of simulation increases, the hardware breadboard will still remain a necessary step in the design process. This book will aid the engineer in using SPICE simulation as a very powerful tool in the design process. This book is a compilation of all various types of electronic circuits. Such compilations are not unusual; in fact, there are several excellent circuit encyclopedias on bookshelves. However, this book goes several steps further. Instead of simply presenting the circuit to the reader, it also provides a SPICE schematic and details about the equivalent hardware performance. The intricacies involved in developing an accurate SPICE model of the circuit are also included. This format benefits readers in numerous ways. First, it allows them to emulate the correlation techniques introduced in this book in order to make their own SPICE models accurately mimic the behavior of the hardware. Secondly, it allows them to clearly see where SPICE excels in its ability to represent real hardware performance. SPICE simulation gives design engineers a vast array of information that can help ensure a successful and optimal design of their hardware. If designers have circuit designs that they know operate correctly under nominal conditions and also have a SPICE model that can accurately reflect the design’s behavior they are much more likely to be able to produce a design that will operate under all operating conditions. Clearly, SPICE simulation can be a much more integral step in the design process and prove its worthiness to engineers of any circuit discipline.

Introduction

3

The beginning of the book concentrates on the basics of computer simulation of electronic circuits. A brief overview of four popular SPICE programs is provided along with their basic differences. We have selected a broad cross section of analog and mixed-mode designs, which we have simulated, as well as constructed. The circuits are grouped into logical chapters. Generic topics, such as oscillators, amplifiers/receivers, power converters, and filters, all head their own chapter. Each chapter starts with a brief overview of the function of the circuits in the chapter. This is followed by several circuit examples. For instance, in the chapter on reference circuits, the beginning details what reference circuits are and their uses at the system level. This is followed by a detailed discussion on a single type of reference circuit, the band gap reference. The theory of operation of each circuit is discussed, followed by the circuit schematic, the simulation results, and a comparison to laboratory data. Advantages and disadvantages of each circuit are added, along with any tips or hints useful in modeling the circuit accurately. We have attempted to perform each simulation using several versions of SPICE for comparison. Also included are the run times for each circuit simulation. Four simulation programs were used to simulate the circuits in this book: ICAP/4Windows/IsSpice4™ v8.11, OrCAD® /PSpice® v10.5, SIMetrix™ v5.1, and Micro-Cap™ v8.0. The simulations in this book were performed using a PC desktop computer running a 2.8 GHz Intel® microprocessor, 512 MB RAM, and Windows XP Professional® . The run times of the circuits are highly dependant on the CPUs and memory capabilities of the computers running them, as well as the .TRAN and .OPTIONS settings in the simulation. It should be noted that any simulation program can be made to run faster or slower than any other program just by changing various variables, even though comparable output results are obtained. With slight changes in parameters like RELTOL, ABSTOL, VNTOL, TRTOL, or TMAX, simulations have been shown to run 14 times faster (Sandler 1996). Each circuit can be optimized for speed differently, and each EDA vendor’s SPICE program has its own set of enhanced simulation optimization and modeling features. Similarly, the same function or individual component can be modeled in different ways, causing dramatic differences in simulation performance. Tricks that speed up simulations in one circuit may not work in another, or even have the opposite effect on speed. Invariably, SPICE simulations are a tradeoff between simulation speed, accuracy, and convergence (Kielkowski 1994).

4

Chapter One

We have made a reasonable effort to make apples to apples comparisons between the simulation speeds of the software in this book by using commonly available Berkeley SPICE 2 OPTIONS. The reader will notice that it is not predictable which software package will run the fastest on any given circuit. The real purpose of including the run times is to provide the user with an estimate as to how long the circuit will take to simulate on his or her own computer, nothing more. That being said, the simulation times noted after the simulations are reasonably accurate. The reader will also note that in some circumstances, one or more of the simulation software results did not match the hardware results. We have attempted to explain the reasons why this might have occurred. Bear in mind that SPICE is one of those labors in life where you get out of it what you put into it. If you put very little effort into understanding what the models and circuit are doing, chances are your simulation accuracy will be poor. The CD-ROM that comes with this book contains four simulation file folders, one for each of the four simulators. Each folder contains the relevant simulation files for that particular simulator. Schematics in their native format are provided in all cases. The circuit names are provided in the appropriate section for that circuit. For example, Circuit 1, a fourth-order Butterworth low pass filter, lists the file names for that circuit as follows: lp fltr (IsSpice), lpflt (Micro-Cap), lp flt (PSpice). Demonstration versions of each simulation tool set are also included. For SIMetrix both a PC version and a Linux version are included. To make the circuits in this book and your own simulations more useful, we suggest you investigate the Power IC Model Library from AEi Systems, LLC (www.AENG.com/PSpice.asp). This product provides a wide variety of popular switching regulator and PWM IC models, most of which are verified against hardware and not readily available anywhere else. A multitude of application circuit examples are also included in the library. Modeling components using the data sheet information, as is done by most EDA vendors, is not sufficient to model complex parts like power electronics ICs. AEi Systems has taken the time to develop proprietary relationships with IC manufacturers in order to obtain the necessary information. We have put a great deal of effort into the construction of this book. It is our sincere hope that the reader benefits from our hard work. Bibliography AEi Systems. 2005. “EMA Design Automation and AEi Systems Announce New Power IC Model Library for PSpice,” Rochester, NY, June 28. Press release.

Introduction

5

Cox, F. L., III, W. B. Kuhn, J. P. Murray, and S. D. Tynor. 1992. “Code-level Modeling in XSPICE,” in Proceedings of the IEEE International Symposium on Circuits and Systems, 1992 (ISCAS ’92), vol. 2, pp. 871–874, http://users.ece.gatech.edu/ ∼mrichard/Xspice Kielkowski, Ron M. 1994. Inside Spice. New York: McGraw-Hill. Sandler, Steven M. 2006. Switch-Mode Power Supply Simulation with PSpice and SPICE 3. New York: McGraw-Hill. Sandler, Steven M. 1996. SMPS Simulation with SPICE 3. New York: McGraw-Hill.


Chapter

2 Description of the PSpice, IsSpice, SIMetrix, and Micro-Cap Simulators

The development of SPICE was initiated by Ron Rohrer, a junior faculty member at the University of California, Berkeley. Rohrer was teaching a class on circuit simulation, in which he and Larry Nagel developed a simulator using the FORTRAN programming language that was to be named CANCER (Computer Analysis of Nonlinear Circuits Excluding Radiation). It was difficult to test integrated circuits (ICs), but SPICE was thought to be an answer to the quick and reliable design of ICs. Larry Nagel increased the capabilities of CANCER by increasing the 400 component or 100 node limit, adding new and improved components and a macromodeling capability. In 1971, Nagel released this improved version of CANCER as SPICE 1 (Simulation Program with Integrated Circuit Emphasis). In 1975, SPICE 2 was released, which offered equation formulation for voltage-defined elements as well as increased simulation speed. This was achieved through the developments of time step control algorithms. The capabilities of SPICE grew with those of computers. In 1983, SPICE 2G.6 was released and remained the industry standard for many years. Motivated by the increased use of UNIX workstations and superior programming tools, SPICE 2 was converted into the C programming language and released as SPICE 3. Although SPICE 3 is not entirely backward compatible with SPICE 2, the new features far outweigh this drawback. SPICE 3 has a technical advantage of being readily modified because it is written in C. SPICE 3 also offers more and improved device models and analysis functions.

7


8

Chapter Two

A major improvement in terms of usability has been the addition of a graphical waveform post processing and schematic capture tools. Waveform post processors greatly facilitate computation and documentation of simulation results. Schematic capture automates the SPICE netlist generation dramatically reducing the number of syntax errors. Understanding the development of SPICE is useful in making a worthwhile comparison of vendor-offered simulation software. The foundation of many vender-offered simulators is Berkeley SPICE 3F.5 combined with XSPICE from the Georgia Institute of Technology. XSPICE is an add-on to SPICE 3, enhancing it with several key features, including a mixed-mode simulation capability (true digital simulator) and over 40 new primitive functional blocks such as Laplace and state machine elements. Four of these software manufacturers—OrCAD (PSpice), Intusoft (IsSpice), Micro-Cap V (Micro-Cap), and Catena (SIMetrix)—have their products featured in this book. With the exception of PSpice, which uses a greatly enhanced version of SPICE2G.6, these software manufacturers took the Berkley SPICE 3F.5 core and wrapped schematic and waveform display programs around it. The schematic entry tools translate the user-defined design into an ASCII netlist using SPICE syntax. The circuit is processed by SPICE and an answer is generated. The software then takes the result from SPICE and passes it into a graphics postprocessor in order to display the answers in a meaningful form. The tool flow used by EDA vendors to enhance the basic SPICE engine is roughly the same. Four separate modules are utilized (see Table 2.1). The first module is the schematic capture program. Originally, using SPICE meant translating a schematic by hand into the SPICE description language for calculation. The schematic capture program allows the user to pull down parts from a menu, wire together the components

TABLE 2.1

The Four Simulation Tool Modules and Their Functions

Schematic capture Allows users to quickly generate SPICE-compatible netlists graphically. Cross-probing allows users to easily view various simulation results in the post processor by clicking on the object in the schematic.

Text editor Examines output files from SPICE. Examines SPICE netlists generated by the schematic capture program.

SPICE Simulator Performs numerical iteration of the circuit to determine solutions in various domains (time, frequency, DC, etc.).

Graphical post processor Converts the text output of SPICE into more meaningful graphs and waveforms. Has the ability to perform complex numerical calculations on waveforms.

Description of the PSpice, IsSpice, SIMetrix, and Micro-Cap Simulators

9

using a mouse, and click a button to start the simulation. The schematic building feel of the schematic capture programs helps SPICE users to quickly translate their circuit ideas into a schematic compatible with SPICE. A text editor is also included and is an invaluable tool for viewing the generated output text files of SPICE, as well as investigating syntax errors and other subtleties of the SPICE programming language. The text output of SPICE is in an excellent format for exporting to other useful engineering tools such as Excel or MathCAD. The third module is the simulator itself. As stated earlier, each of simulators from the different software vendors uses the core code from Berkeley to iterate solutions of the circuit using mesh equations. The fourth module is the graphics waveform postprocessor. It has the feel of an oscilloscope, translating SPICE’s numerical data output into waveforms. Many different mathematical operations can be performed, such as integration, FFTs, etc. allowing users to get the most out of SPICE. A key difference between the products offered by vendors relates to how the user interfaces with the simulation engine, and the features offered by the various modules. Model libraries are also a key distinguishing characteristic of a vendor’s offering. Users can create their own models, but most of the time they will depend on the model libraries provided by a vendor. The library models that do not use pure Berkeley SPICE 2G.6 syntax are unique to that particular simulator. While the SPICE syntaxes of each product are similar, they are not exactly compatible; both distinct and subtle differences exist. However, in many cases, most models in vendors’ libraries have been provided by the component manufacturers. These models are available for free on the Internet. It is very important to test and qualify models in a library, rather than assuming that they are accurate. The library governs the accuracy of the simulation in which they are used. Just because a model is in a library does not mean that it provides correct results or that it has been verified over even a small portion of the operation range of the real part. Each of the simulators has a schematic editor program, which is used to enter the circuit into the simulator. Accessing the overall quality of a particular schematic editor comes down to preferences. Even though an assessment may be made from the number of keystrokes or clicks of the mouse required to enter a circuit, a user’s effectiveness is a function of familiarity and comfort. Maximizing the performance of a schematic editor is dependant on the user and is difficult to determine. The same can be said when evaluating the performance of the waveform postprocessor. Familiarity governs the ability of a user to manipulate the output data into a desirable viewing form. All of the

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Chapter Two

postprocessors have similar features, and therefore, accessing the performance of a particular postprocessor depends on the preferences of the user.

Basic Overview of SPICE SPICE starts a simulation by making an initial guess at the circuit’s node voltages and then, using the nodal equations of the circuit, calculates the mesh currents. The mesh currents are then used to recalculate the node voltages, and the cycle begins. This iterative process continues until the nodal equations have been solved within specified tolerance limits. These limits can be set by using .OPTION parameters (Reltol, Vntol, and Abstol). As the difference between each iteration approaches zero, the simulation approaches convergence to what it deems is the final answer. SPICE uses the Newton–Raphson algorithm to solve the matrix of nodal equations if the circuit contains a nonlinear device. For a circuit containing only linear devices, SPICE uses Gaussian elimination to solve the matrix.

SPICE syntax and tutorial

The first line of any SPICE netlist is the title line. It is used for documentation purposes only. The next few lines usually tell SPICE which analysis will be performed and what the bounds of that analysis will be. For example, we may be requesting a time domain analysis of a circuit (called a transient analysis). The information as to how long the waveform is and what increments and what section of it are of interest is defined in this section of the code. SPICE netlists generally have one function, command, or element per line (Fig. 2.1). Also defined upfront are global constants, subcircuits (models) used repeatedly in the main circuit, and instructions on which nodes are of interest in the final solution, though this structure is not mandatory. The middle section of the code defines the circuit itself. The structure of each component is roughly similar. The first variable is the reference designator. The next variable is the number of nodes that the component

*EXAMPLE CIRCUIT #1 .TRAN 1U 100U 10U 2U UIC .OPTIONS METHOD=GEAR .PRINT TRAN V(2) .IC V(7)=12 Figure 2.1

Typical lines of the beginning of a SPICE netlist.


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R1 1 0 100K L1 1 2 10U Q1 2 3 4 2N2222A V INPUT 4 0 10 I OUT 3 0 PULSE 0 1 1U 100N 100N 10U 20U Figure 2.2

Typical lines of the middle of a SPICE program.

is connected to. The remaining variables define the parameters of that component. A simple example is a resistor: R1 1 2 100K In this line, resistor R1 is defined as a resistor connected from node 1 to node 2 with a value of 100 k. Several rules apply in defining components. Node 0 is reserved for ground. All circuits must have at least one ground connection. Also, reference designators are limited to alphanumeric characters (Fig. 2.2). Longer statements may be continued on the following line by using a + symbol as the first character to indicate a continuation from the previous line. The final line of any SPICE program must be the .END statement. Several basic analyses are used in this book. An explanation of each is given in the following paragraphs. DC analysis

Before SPICE performs any specified simulation, a DC operating point analysis, .OP, is performed. This establishes the DC bias point of the circuit. There generally must be convergence of this simulation before any other specified simulation can be performed. SPICE calculates the DC operating point by replacing all inductors with shorts, and it treats all capacitors as open circuits. SPICE must determine the DC operating point within a specified number of iterations, otherwise a nonconvergence warning is generated and the simulation is aborted. The default .OPTIONS statement used to determine the DC iteration limit is .OPTIONS

ITL1=100

For nonconvergence, the value of ITL1 should be increased to greater than 500, which increases the maximum allowed number of iterations to determine the solution. Simulators today sport many DC convergence options that are generally invoked automatically when the basic method fails. These include GMIN stepping, source stepping, initial capacitor voltage stepping, and

12

Chapter Two

pseudotransient. Several convergence helpers are discussed below, and they apply to all Berkeley SPICE compatible programs. A .NODESET statement can also be used to reduce the number of iterations required for convergence. The DC voltage of a node can be specified by the user, and it will be used by SPICE in the initial guess of the simulation. This can greatly reduce the number of iterations that are required for convergence. If convergence is not attained by using a nodeset and increasing the ITL1 statement, then an ITL6 statement can be used. By setting ITL6 = 100, or any nonzero value, a source stepping algorithm is used, which decrements the voltage sources down to zero, or until convergence is reached, and then they are stepped back up to their assigned voltage levels. This appears to be the solution to all DC bias point convergence problems. However, there are bugs associated with the ITL6 function, and so it should be used only as a last resort. If the circuit contains semiconductor devices, then it contains regions of zero conductance. This can result in a divide-by-zero error. To eliminate this problem, every PN junction in every SPICE semiconductor device has a GMIN transconductance in parallel with every PN junction. GMIN is assigned globally and has a default value of 100 p. The larger the value of GMIN, the faster the Newton–Raphson algorithm will converge to a solution. Raising GMIN decreases the size of the shunt resistor. The accuracy of the simulation is not affected as long as the current generated in the shunt resistors is lower than the relative error tolerance current resolution (Kielkowski 1995). A suggested value for setting GMIN is given in the following statement: .OPTIONS

GMIN=1n

Transient analysis

A transient time domain analysis begins with a DC operating point analysis unless SPICE is specifically told to skip it. SPICE calculates the DC operating point by replacing all inductors with shorts, and all capacitors with open circuits. SPICE must determine the DC operating point within a specified number of iterations, otherwise a nonconvergence warning is generated and the simulation is aborted. The solution to the DC operating point determines the node voltages at the time T = 0. SPICE then assigns the instantaneous I-V relationship of inductors or capacitors and uses a numeric integration routine to create an equivalent nodal matrix. The nodal matrix changes for every time step in the transient analysis. Each Newton–Raphson iteration that follows starts with an initial guess at the previous set of node voltages. This expedites the iterative process, which continues until the solution is found or the maximum allowed iterations are exceeded. The maximum


13

number of iterations is determined by the setting the .OPTIONS statement ITL4. The default .OPTIONS statement is given below: .OPTIONS

ITL4=10 ; use ITL4=1500 if transient convergence problems occur

When the simulation steps to the next point in time, the transient solver determines the operating point at that moment in time. If the simulation does not reach convergence at this point in time, then the time step is reduced by one-eighth. This is repeated until convergence is achieved or the maximum number of times that the time step can be reduced, which is specified by ITL4, is reached. A large time step, which is also user defined, in a transient simulation can result in convergence difficulties. This is particularly true for switching circuits. The time step must be small enough to provide enough resolution to identify switching voltage levels. Large voltage transitions or device model discontinuities must be taken into account when assigning the transient simulation parameters. An example of a transient simulation statement is given below: .Tran .Tran

Tstep 10u

Tstop 10m

Tstop 0

Tmax 20u

UIC UIC

The time step Tstep = 10u determines each point in time starting from zero that the transient solver will calculate a solution. A safe estimation of the time step is an order of magnitude less than the period of a switching waveform. For example, the time step for a 100 kHz oscillator (period = 10 µs) should be approximately 1 µs. Tmax, the maximum time step, can be left out (at default) or specified to increase (decrease TMAX) or decrease (increase TMAX) simulation accuracy. This allows the simulator to take larger steps when the voltage levels in the circuit experience little change. A transient time domain analysis can prove to be the most difficult to get to converge. AC analysis

An AC analysis begins by determining the DC bias point of the circuit. This can be critical, because it determines the state of the active devices. For instance, the output of a linear regulator or operational amplifier is different if it is operating in the linear region, or if it is operating in the saturated region. After SPICE determines the DC operating point, the large signal transistor and diode models are converted into linear smallsignal models. All nonlinear effects of the circuit will not be accounted for in the AC frequency sweep, which generates a Bode plot or frequency response. Magnitude and phase (real or imaginary) data are produced.

14

Chapter Two

Simulation Types and Data Acquisition All of the simulators have the ability to perform the following analyses: DC Operating Point Analysis

Noise Analysis

DC Small-Signal Transfer Function

Transient Analysis

DC Sweep Analysis

Fourier Analysis

Sensitivity Analysis

Monte Carlo Analysis

AC Analysis

Temperature Analysis

The reference manual that accompanies each simulator provides sufficient information to perform any of the above analyses.

Convergence Problems Convergence problems can be the most perplexing aspect in performing a simulation (Sandler 2006). There is a methodology that comes with experience. This section will provide a structured attack that should cure most convergence problems. The convergence suggestions should be performed in the order that they are listed. They are prioritized so that the first few will be of the most benefit. Begin with the obvious. These adjustments are based on the most commonly available .OPTIONS parameters and features in all of the simulators. Each simulator has several more convergence-related parameters that can be adjusted. Please see the individual syntax manuals for your program for more details on how to handle convergence problems.

Steps to avoid common mistakes

Verify that all circuit connections are valid, the component polarity is proper, and there is a DC path from every node to ground.

Verify that all components have the correct values (i.e., “mega” instead of “milli” for 1E6). Components with no assigned value may be set to a default value determined by the simulator.

Verify that all model parameters are realistic, especially if the model was created or altered by you.

Verify that every node has two connections.

Verify that voltage or current generators have the correct syntax and appropriate values.


15

Use a series equivalent in place of capacitors or current sources that are placed in series.

Verify that the letter “O” was not used in place of the number zero (0).

If behavioral expressions or elements are used in the circuit, verify that division by zero cannot occur.

Verify that dependent source gains are correct.

DC convergence solutions

1. Set ITL1 = 500 in the .OPTIONS statement. This setting increases the number of iterations that SPICE will perform before generating a nonconvergence warning and aborting the simulation. 2. Add .NODESETs. Voltages can be assigned to the nodes of the toplevel schematic. The initial guess made by SPICE to determine the DC bias point incorporates the nodesets. This can greatly reduce the number of iterations required to converge. Improper nodesets can result in inaccurate results or nonconvergence. Care should be taken in setting the .NODESET statements. 3. Use pulse statements to turn on DC power supplies. Example: V1 3 0 5 DC becomes V1 3 0 PULSE 0 5 This allows the user to turn on the power supplies. A rise time may also be used to provide a realistic turn-on. 4. Set GMIN in the .OPTIONS statement. Set GMIN = 1n or 0.1n. Larger values are not recommended. This sets the minimum conductance across all semiconductor devices. 5. Set RSHUNT in the .OPTIONS statement, if available. This option places a resistor, with the value assigned globally by RSHUNT, from every node in the circuit to ground. A solution obtained using this convergence technique could be made at an incorrect operating point. The solution should be carefully examined. 6. Set ILT6 = 100 in the .OPTIONS statement. Source stepping decreases all DC stimuli until a DC bias point is determined, or they are reduced to 0 V. The voltages are then gradually stepped from the DC bias point that converged, which may be at ground, back to the assigned value. The source stepping algorithm uses gradual increases in voltage, to establish a new DC bias point, taking the previous DC bias point as the initial guess. This process continues until a DC bias point has been established for the assigned values of the stimuli of the circuit.

16

Chapter Two

Transient convergence solutions

1. Verify that DC convergence has been achieved. View the error statements in the text editor to verify that the convergence problem pertains exclusively to the transient simulation. 2. Verify that the time step provides an appropriate resolution. The time step must be small enough to provide appropriate resolution of the switching waveforms generated by the simulation. The time step should be assigned to an order of magnitude smaller than the shortest period in the simulation. For example, in a 100 kHz oscillator, the period is 10 µs. The time step should be set to 1 µs. .TRAN 1u 3m Other factors such as the on time or the duty cycle should be considered when determining the time step. Once convergence has been achieved, this value can be maximized to reduce simulation time. 3. For oscillating or switching circuits, set METHOD = GEAR in the .OPTIONS statement. This statement selects the type of integration method that SPICE uses to solve the transient equations. Gear integration should be used for all switching circuitry. The default integration, trapezoidal, has a tendency to produce oscillations. Note: Gear integration is not available in all simulators. 4. Add UIC (Use Initial Conditions) to the .TRAN statement. This statement causes SPICE to bypass the DC operating point analysis. Initial conditions should be placed on capacitors at their expected operating voltage. Just as with the use of incorrect nodesets, incorrect initial condition values can produce incorrect solutions or nonconvergence. Results should be verified for validity. 5. Set ITL4 = 500 in the .OPTIONS statement. This statement increases the number of iterations performed by SPICE, before a nonconvergence warning is issued and the simulation is aborted. 6. Set RELTOL = .01 in the .OPTIONS statement. This statement decreases the accuracy of the simulation by increasing the relative error tolerance required for convergence. This value should not be set lower than .01. The simulation run time is also reduced by increasing RELTOL. Remember as a general rule that every order of decrease in magnitude of the relative tolerance results in doubling the simulation run time. 7. Reduce the rise and fall times of PULSE sources. Drastic changes in voltage can result in nonconvergence problems. Soften the edges of the pulse source by increasing the rise time and fall time of the pulse waveform.


17

8. Set TRTOL = 40 in the .OPTIONS statement. This statement is proportional to the step size used when performing a transient simulation. The accuracy of the simulation can be compromised by changing TRTOL from the default setting of TRTOL = 7. 9. Reduce the accuracy of ABSTOL/VNTOL if current and/or voltage levels permit. The default value of ABSTOL = 1pA, and VNTOL = 1uV, should be set to about eight orders of magnitude below the level of the maximum current and voltage. 10. Set RAMPTIME = 10nSec in the .OPTIONS statement, if available. This statement ramps all independent sources up from zero at the beginning of the transient analysis. The statement is beneficial if the transient analysis will not start. Take care to allow enough time for sources to ramp up, otherwise this statement could do more harm than good. AC convergence solutions

1. Do not use steps 3–5 of the DC convergence solutions. Using these steps may not produce a valid DC operating point, which is essential for SPICE to linearize the circuit. See the AC analysis description. Once DC convergence is achieved, the AC analysis will also converge. Convergence failures are not always a function of SPICE and therefore cannot always be fixed using .OPTIONS statements or other convergence techniques. Convergence failures may result from hardware problems. Bibliography Kielkowski, Ron. 1995. Inside SPICE. New York: McGraw-Hill. Sandler, Steven M. 2006. Switch-Mode Power Supply Simulation with PSpice and SPICE 3. New York: McGraw-Hill.


Chapter

3 Filter Circuits

Filter circuits form the initial building block for many different systems. Communications circuits require only certain signal frequencies to be passed on to transmitter and receiver circuits. Power converters use filters on the input bus to filter out spurious noise and on the output line to smooth the rectified signal. Digital logic circuits use bypass capacitors and RC networks to filter supply voltages that must travel some distance before reaching the IC. Filters can provide the time delays required in some circuits. Filter circuits are very important to these and many other circuits because of the simple function they perform. They allow desirable signals to pass while blocking undesirable signals. For most of the circuits, the transient response of the filter is matched to hardware results. For a select few filters, a network analyzer is utilized to measure the frequency response of the filter. Although filters perform a simple function, the circuits and design parameters used to design filters can be much more complex. Filters can be optimized for a low Q in the pass band (Butterworth type) or a high attenuation in the stop band and steeper roll-off near the cut-off frequency (Chebyshev type). Filters that are used primarily for delays in circuitry might use the Bessel–Thomson type of filter. The expansive set of filter design types is matched by the wide range of filter design applications that use them. Fourth-Order Butterworth Low Pass Filter The first filter in the chapter is one of the most popular. The schematic of the fourth-order Butterworth response low pass filter is shown in Fig. 3.1. The frequency response of the filter to an AC sweep is shown in Fig. 3.2. Note the flat response in the pass band and the stop band frequency of 100 kHz. 19


20

Chapter Three

R1 20K

V_3

R2 20K 4

3

4

V4

4 C2 .01U

6

C1 .005U

5

6

X4 OPAMP

6

VEE

2 2

5

VCC 1 1

R3 20K 55

R4 20K 9

9

9 C4 .01U

11 C3 .005U

20

20

Figure 3.1

X5 OPAMP

11

2 2 VEE

20

VCC 1 1

20

V_20 20

5

5

5

11

20

20

20

Schematic of a fourth-order Butterworth low pass filter.

Unfortunately, the lab used in the creation of the circuits in this book closely resembles the lab of other engineering companies around the world. We use 5% tolerance resistors and 10% tolerance capacitors that are either soldered to a vector board or plugged into a solderless breadboard. This introduces various parasitics and inaccuracies in the results. In order to be more precise in showing the accuracy of SPICE simulation software, we frequently run the simulations with the stated values of the resistors or capacitors used in our lab breadboards. The measured values for each resistor and capacitor used in our breadboard configuration which may be different, are shown in Fig. 3.3. In order to correlate the breadboard to the SPICE circuit, a 5 V pulse replacements was applied with a rise time of 100 ns by using the following command in a V source: PULSE 0 5 750 U 100N This command creates a delay of 750 µs to allow the filter to be at steady state when the pulse is applied. The step response of the breadboard

20.00

Gain in dB (Volts)

−20.00

1

−60.00

−100.00

−140.0

1K

10K

100K

FREQUENCY in Hz

Figure 3.2

AC filter response.

1MEG

Filter Circuits

R2 21.3K

R1 21.3K 3

4

0

21

6

-13.9 C2 .0102U 5

-4.10M C1 .00512U

X4 OPAMP 2

-15.0 VEE

R4 21.3K

R3 21.3K 9

-13.9 VCC

1

-13.9

1

15.0

C4 .0102U

1

X5 OPAMP

-4.20M C3 .005U

20

VEE

-13.9 VCC

V4 PULSE

Figure 3.3

Breadboard configuration of fourth-order Butterworth filter.

circuit is shown in Fig. 3.4a, while that of the IsSpice model is shown in Fig. 3.4b. The top trace is the 5 V pulse, while the bottom trace is the filter response measured at the output of op-amp X5. SPICE automatically precedes the AC and transient analyses with two operating point analysis, one for AC and one for the transient. The operating point values are used to set the biasing for the AC analysis and the initial starting point for the transient analysis. For the AC analysis the operating point analysis is often called the small signal bias solution.

SPICE tip

Figure 3.4a

Breadboard filter response to step input.

22

Chapter Three

10.000

8.000 2

−10.000

6.000

V(20) in Volts

V(3) in Volts

0

1 4.000

−20.00

2.000

−30.00

0

750.0U

1.250M

1.750M

2.250M

2.750M

TIME in Secs

Figure 3.4b IsSpice filter response to step input.

For the transient analysis the operating point is often called the initial transient solution. They are different. In fact, depending on nodeset values, initial conditions, .OPTIONS settings, and so on, one operating point can fail while the other can succeed. The operating point analysis is critical to getting the right information out of the AC and transient analyses, and it must converge if the subsequent analysis is to run.

The circuit was also simulated on Micro-Cap and PSpice. The MicroCap results are shown in Figs. 3.5a and 3.5b, while the PSpice results are shown in Figs. 3.6a and 3.6b.

Figure 3.5a Micro-Cap AC filter response.

Filter Circuits

23

Figure 3.5b Micro-Cap filter response to a step input.

Simulation tip

Note that in the results of the Micro-Cap voltage step response simulation, the magnitude of the output voltage was incorrect. The reason for this is unknown; however, the lesson here is that you must know the limitations of your models. Many times, these libraries can be provided by IC manufacturers or the SPICE software company. It is very important to remember that these models may not be accurate for the operating range or temperature settings you are interested in. People often make different models to represent different aspects of the part’s operation, rather than one all encompassing model. In most cases, the model exhibits only a subset of the actual device performance characteristics, albeit, hopefully the most important ones. For example, some models may

Figure 3.6a

PSpice AC filter response.

24

Chapter Three

Figure 3.6b

PSpice filter response to a step input.

have noise rejection modeled accurately, or AC characteristics, or input current draw, whereas some may not model any of these. If the model does not accurately reflect the characteristic you are interested in, then this does not necessarily mean the model is useless or wrong (although this is a possibility).

Run time summary (s) IsSpice v 8.11 7.25

PSpice v 10.5 5.02

Micro-Cap v8.0 13.734

Advantages: Moderate parts count, flat response in the pass band Disadvantages: Filter Q greater than that of other filter types File names: lp fltr (IsSpice), lp fltr (PSpice), lpflt (Micro-Cap)

Fourth-Order Butterworth High Pass Filter A quick modification to the circuit in Fig. 3.1 produces a high pass filter response. The schematic for the high pass filter is shown in Fig. 3.7, and its AC response is shown in Fig. 3.8. The same pulse as in the low pass filter was applied to the high pass filter. The breadboard results are shown in Fig. 3.9. These may be compared with the IsSpice results shown in Fig. 3.10. The top trace is the 5 V pulse, while the bottom trace is the filter response measured at the output of op-amp X6. This circuit was also simulated using Micro-Cap and PSpice. The results of these simulations are shown below (Figs. 3.11 to 3.14).

V(4) IN

C1 .005U

C2 .01U 4

5

0

-9.99M

6

X4 OPAMP

-11.0M

R1 21.3K

2

R2 21.3K

VEE-15.0

-9.99M

1

15.0

C5 .005U

C6 .01U

VCC

3

10

9

-9.99M

-11.0M

R6 21.3K

X6 OPAMP

R5 21.3K

VEE

VCC

11

-9.99M

V(11) OUT

Figure 3.7

Schematic of fourth-order Butterworth high pass filter.

40.00

1

todB of OUT in dB (Volts)

0

−40.00

−80.00

−120.0

1K

10K

100K

FREQUENCY in Hz

Figure 3.8

AC filter response. Run time summary (s)

IsSpice v 8.11 4.95

PSpice v 10.5 0.84


Advantages: Moderate parts count, flat response in the pass band Disadvantages: Filter Q greater than that of other filter types File names: hp fltr (IsSpice), hp flt (PSpice), hpflt (Micro-Cap)

Fourth-Order Butterworth Band Pass Filter The schematic in Fig. 3.15 shows the configuration for a Butterworth band pass filter. The AC characteristic of the filter is shown in Fig. 3.16. 25

26

Chapter Three

Figure 3.9

Breadboard filter response to a step input.

7.000

5.000

5.000

−5.000

3.000

IN in Volts

OUT in Volts

The breadboard circuit was pulsed with a 5 V step. The response of the band pass filter to the step input is shown in Fig. 3.17. The top trace is the input step, and the bottom trace is the filter response at the output of X5. The IsSpice circuit response to the step input is shown in Fig. 3.18. This circuit was also simulated using PSpice and Micro-Cap. The results of these simulations are shown below (Figs. 3.19 to 3.22).

1.000

2

−15.00

−25.00 1

−1.000

−35.00

500.0U

1.000M

1.500M

2.000M

TIME in Secs

Figure 3.10

IsSpice filter response to a step input.

2.500M

Filter Circuits

Figure 3.11


Figure 3.12


27


PSpice v 10.5 5.75


Advantages: Moderate parts count Disadvantages: Filter Q greater than that of other filter types File names: bp fltr (IsSpice), bp flt (PSpice), bpflt (Micro-Cap)

Bessel–Thompson Delay Low Pass Filter The primary purpose of this filter is to add a delay to a pulse or data sequence. The use of the RC time constant allows this delay to be added to both the rising and the falling edge of the pulse. The ideal response

Figure 3.13 Micro-Cap AC filter response.

Figure 3.14 Micro-Cap filter response to a step input.

C2 .01U

R1 20K 3

4

6

X4 OPAMP

R5 20K

R2 40K

2

C1 .005U

VEE

C4 .01U

R3 20K 9

5

10

X5 OPAMP

VCC 1

R6 20K

C3 .005U

R4 40K

VEE

20

V(3) IN

V4 AC

Figure 3.15 Schematic of a fourth-order Butterworth band pass filter.

28

VCC

V(20) OUT


0

−20.00

−40.00

−60.00 1 −80.00 100

1K

10K

FREQUENCY in Hz

AC filter response.

Figure 3.17


5.000

1.000

−5.000

600.0M

−15.00

OUT in Volts

IN in Volts

Figure 3.16

2

200.0M 1

−25.00

-200.0M

−35.00

-600.0M

750.0U

1.750M

2.750M

3.750M

4.750M

TIME in Secs

Figure 3.18

IsSpice filter response to a step input. 29

30

Chapter Three

Figure 3.19


of the filter is a perfect reproduction of the input delayed by a specified time constant. The time delay of the Bessel–Thompson filter is measured by the time for which the pulse occurs until the time the response is 50% of the input step height. A Bessel–Thompson filter was designed to have a delay close to 500 µs. The design procedure followed gave exact values for all of the capacitors and resistors. These values are rounded to the nearest value of capacitor available. The SPICE packages are used to determine what the implemented delay will be. Measured values of all the components used in the hardware are used. The schematic and the breadboard results are shown as Figs. 3.23 and 3.24, respectively.

Figure 3.20


Filter Circuits

Figure 3.21

31

Micro-Cap AC filter response.

IsSpice had an LM124 model in its library. The simulation response to a step input is shown in Fig. 3.25, and the AC simulation results are shown in Fig. 3.26. PSpice has a model for LM324, but the the UA741 op-amp model was used in its place. The operation amplifier does not play a critical role in this circuit because of its slow response. The limiting parameter of the delay time is the RC time constant and not the slew rate or drive capability of the operational amplifier. The PSpice model response to a step input is shown in Fig. 3.27, and the AC results are shown in Fig. 3.28. Micro-Cap also had an LM124 model. The model response to a step input is shown as Fig. 3.29, and the AC results are shown as Fig. 3.30.

Figure 3.22

Micro-Cap filter response to a step input.

32

Chapter Three

C5 69N 8

8

5

C4 103N

5 4

4

1

1

V3

V_3 R1 2.16K 3

X1 LM124N

R2 2.16K 8

6 2

C1 69N

V1

R3 2.16K

2 VEE

5 5

4

11 7

V_4

VCC

V6 X2 LM124N

R4 2.16K 7

C3 31N

V_25

VEE

1

12 1

VCC

10

V2

V5

5

5 1

Figure 3.23

Bessel–Thompson delay filter.

Figure 3.24


1


PSpice v 10.5 1.25


Advantages: Adds controlled delay to a given signal with moderate parts count Disadvantages: Rounds off signal and places importance on detection device File names: bessel (IsSpice), bes ps (PSpice), besmc5 (Micro-Cap)

Filter Circuits

33

Bessel–Thompson Delay Low Pass Filter with Pulse Shaper

2.000

4.000

1.000

3.000

0

BESSELOUT in Volts

INPUT in Volts

A simple pulse-shaping modification can be added to the Bessel– Thompson delay filter by using an additional operational amplifier. Resistors are used to divide down the supply voltage to half the output voltage of the delay filter, and its response is then compared with the delay filter’s response, which results in a time-delayed square wave. The schematic of this circuit is shown in Fig. 3.31. This simulation also allows us to compare the operational amplifier models that came with each software package. The response of this circuit is driven from rail to rail, providing the saturation voltages of the models. Also, the slew rate of the output should be consistent with the measured and

−1.000

2

2.000

1

x 519.6U < 1.000

>

1.000

x 100.00U < 2.423M > −2.000

0 100.00U

300.0U

500.0U

700.0U

TIME in Secs

Figure 3.25

IsSpice filter response to a step input.

todB of BESSELOUT in dB (Volts)

40.00

0

−40.00

1 −80.00

−120.0

100

1K

10K

100K

WFM.1 BESSELOUT vs. FREQUENCY in Hz

Figure 3.26

IsSpice AC filter response.

900.0U

Figure 3.27


Figure 3.28


Figure 3.29

Micro-Cap filter response to a step input.

34

Filter Circuits

Figure 3.30

35


published data. Keep in mind that these parameters may not be consistent between brands and between lots, but they should be consistent with the average data from the manufacturer. The parameters that will be measured in each of the software packages and the hardware are the minimum and maximum voltages, the rise and fall time of the output, and the effective pulse width. The response of the IsSpice model is shown as Fig. 3.32. Micro-Cap results are shown as Fig. 3.33. PSpice results are displayed in Fig. 3.34, and the hardware measurements are shown as Fig. 3.35.

C5 69N C4 103N

V13 10 14 27

3

R1 2.16K

V3 -10

R2 2.16K 8

6 2

VEE

1 ULSE

C1 69N

V6 -10

X1 LM124N

R3 2.16K

R4 2.16K

12

11

47

VCC

C3 31N

X2 LM124N

15 VEE

VCC

1

10

V2 10 V5 10

Figure 3.31

13

VEE

VCC

5

R11 99.8K R10 11.93K

Bessel–Thompson delay filter with shape reformation.

V14 -10

Pulse shaping response in volts

20.00

10.000

x 1.443M < -3.878U

>

0

x 553.0U < 10.49U

>

−10.000

1

−20.00 200.0U

600.0U

1.000M

1.400M

1.800M

TIME in Secs x = 890.4U y= 0

IsSpice simulation results. Note: Vout(max) = 8.4 V, Vout(min) = –10.7 V, rise time = 53.3 µs, fall time = 53.3 µs, pulse width = 890 µs. Figure 3.32

Micro-Cap simulation results. Note: Vout(max) = 7.4 V, Vout(min) = –10.7 µs, rise time = 49 µs, fall time = 52 µs, pulse width = 833 µs.

Figure 3.33

PSpice simulation results. Note: Vout(max) = 9.08 V, Vout(min) = −10.47 V, rise time = 84 µs, fall time = 71 µs, pulse width = 851 µs.

Figure 3.34

36

Filter Circuits

37

Breadboard data. Note: Vout(max) = 9.1 V, Vout(min) = −10 V, rise time = 49 µs, fall time = 50 µs, pulse width = 780 µs.

Figure 3.35


PSpice v 10.5 0.92


Advantages: Moderate part count, pulse delay and reshaper Disadvantages: May require additional voltage source and op-amp package to reshape voltage to a specification File names: bess shap (IsSpice), bes shap (PSpice), bes lpshap (Micro-Cap)

Inverted Bessel–Thompson Delay High Pass Filter A quick modification to the Bessel–Thompson filter leaves us with a high pass filter. This filter does not have the built-in delay like the low pass version, but it does provide an interesting response. The schematic and the breadboard results are shown in Fig. 3.36 and Fig. 3.37, respectively. The measurements that will be made for comparison purposes are the step response height and the time until the second cross of the zero axis. For each filter, an AC analysis was run for comparison between the different software packages. These results are displayed along with the step response from each of the filters. The results of the IsSpice model are displayed in Figs. 3.38 and 3.39. The PSpice results are shown in Figs. 3.40 and 3.41. The results from the Micro-Cap model are shown in Figs. 3.42 and 3.43.

38

Chapter Three

R2 4.65K R4 3.24K

34 10

C4 10N

V2 -10

C1 10.28N

8

C3 10.25N

VEE

5

R1 5.56K

ULSE

V4 -10

6 2

X1 LM124N

C2 10.5N

12 9 VEE

VCC 5

R3 8.21K

X2 LM124N

7

VCC 11

V1 10 V3 10

Figure 3.36

High pass filter inverse Bessel–Thompson.

Figure 3.37

Breadboard results of step response.


PSpice v 10.5 0.88

Advantages: Moderate parts count Disadvantages: Underdamped response File names: hpbessel (IsSpice), bess hp (PSpice), bes mic5 (Micro-Cap)


Filter Circuits

39

Chebyshev Band Pass Filter The Chebyshev filter response offers higher attenuation and a steeper roll-off near the cutoff frequency than the Butterworth filter response. There is a tradeoff to achieve the higher attenuation. The cost of utilizing a Chebyshev filter is higher values of Q, which leads to difficulties in hardware realization, and nonlinear phase characteristics, which can result in difficulties in predicting circuit performance. The following MathCAD file was used to design a Chebyshev band pass filter with unity gain in the pass band. The filter is comprised of two identical cascaded stages.

2.500

Response in Volts

1.500

500.0M 1

−500.0M

−1.500

100.00U

300.0U

500.0U

700.0U

900.0U

TIME in Secs

Figure 3.38

50.00

IsSpice step response results.

50.00 1

−150.0

−50.00 Gain in dB (Volts)

VP(7) in Deg

−50.00

−150.0

−250.0

−250.0

−350.0

−350.0

2

100

1K

10K

FREQUENCY in Hz

Figure 3.39

IsSpice AC filter response.

100K

Figure 3.40

PSpice step response results.

Figure 3.41


Figure 3.42

Micro-Cap step response results.

40

Filter Circuits

Figure 3.43

41


Design specifications in rad/s, where rad/s = 2π Hz: ω2 := 2950 × 2π ω4 := 3500 × 2π

αmax := 0.5

ω3 := 1500 × 2π

ω1 := 2050 × 2π

αmin := 22

ω0 2 ∼ = ω1 ω 2 √ ω0 := ω1 ω2 ω0 = 1.545 × 104 ω0 ω0freq = 2.459 × 103 ω0freq := 2π BW := ω2 − ω1 BW = 5.655 × 103 ω ∼ 0 qc = BW ω0 qc = 2.732 qc := ω2 − ω1 ω4 − ω3 s = 2.222 s := ω2 − ω1 − ω 2 2 + ω0 2 p := − p = 1 ω2 (ω2 − ω1 )     1 2   × αmin  s  10  cosh n × acosh + 10 − 1    p       ln  2  s     cosh n × acosh   p   αmax := 10 ×

ln(10)

42

Chapter Three

αmax = 0.5

   1 2 2   × α max   s s  × 10 10 + 1 − cosh n × acosh ln   cosh n × acosh p p 

αmin := 10 ×

αmax = 22

ln(10)



 12  αmin  10 10 − 1      acosh  α    max   10 10 − 1 n := s acosh p n = 2.975 Round up to an integer. ceil(n) = 3 n := ceil(n) n 180 n∼ if floor = 2n 2 2 ψ := 180 otherwise n ψ = 60 ψ := ψ ×

π 180

ψ = 1.0 αmax 1 ε := 10 10 − 1 2

ε = 0.349

The pole locations are now determined: qc = 2.732 1 1 a := × asinh a = 0.59138 n ε Real Poles: For ψ = 0; n odd σs := |sinh(a)| σs = 0.626 Complex Poles: For ψ = (ψ, +/ − 2ψ, +/ − 3ψ . . .) σk := | − sinh (a) × cos(ψ)| σk = 0.3 ωk = 1.0 ωk := | cosh (a) × sin(ψ)|

Filter Circuits

The half-power is determined by (3 dB) frequency 1 1 × acosh hp = 1.1 hp := cosh ceil(n) ε = 0.3 := |σk | = 1.0 := |ωk | C := 2 + 2 C = 1.1 2 D := D = 0.229 qc C E := 4 + 2 E = 4.153 qc √ G := E2 − 4D2 G = 4.128 1 1 × (E + G) Q = 8.875 Q := D 2 K :=

Q qc

W := K +

K = 1.01739 √

K2 − 1

W = 1.20469 ω02 = 1.861 × 104

ω02 := Wω0 qc Qo := σs 1 × ω0 ω01 := W

Qo = 4.362 ω01 = 1.283 × 104

Set all values of capacitors to be equal: C := 10−7 Km1 :=

1 2 × QCω01

Km1 = 43.924

Km2 :=

1 2 × Qo Cω0

Km2 = 74.19

Km3 :=

1 2 × QCω02

Km3 = 30.266

Stage 1: R1 := (T1 ) × Km1 R2 :=

1 1−

1 T1

× Km1

R3 := 4 Q2 Km1

R1 = 1.99 R2 = 44. R3 = 1.3

43

44

Chapter Three

Stage 2: R4 := T2 × Km2 R5 :=

1 1−

1 T2

R4 = 2.8

× Km2

R5 = 76 R6 = 5.6

R6 := 4Qo 2 Km2 Stage 3: R7 := (T3 ) × Km3 R8 :=

1 1−

1 T3

R7 = 1.3

× Km3

R8 = 30.948 R9 = 9.536 × 103

R9 := 4Q2 Km3

The schematic in Fig. 3.44 of the Chebyshev band pass filter utilized the predicted values from the MathCAD file, where lab resources allowed. Close approximations were used, to which the circuit performance was extremely sensitive. Any deviations from the values predicted in the MathCAD file resulted in gain in the pass band. Using SPICE to test possible circuit realizations greatly reduces the time to implement hardware. SPICE will predict if a given circuit realization will perform as desired with available parts, before actual hardware measurements are made. This is helpful because Chebyshev circuit realization can be difficult: small changes in the circuit elements can result in undesired performance. The simulated AC results from IsSpice, PSpice, and Micro-Cap are shown in Figs. 3.45, 3.46, and 3.47, respectively. The measured breadboard AC response of the filter is shown

V(5) VCC 5

C8 .1U C10 .1U

6

C12 .1U

16

R10 13.68K

R12 1.99K 14

9

11

19

1 VCC

R11 43.1

C7 .1U

R13 5.644K

V(9) VEE

R15 2.88K

VEE

R14 76.7

17

V(5) VCC 15

C9 .1U

VCC

R16 9.77K R18 1.374K

VEE

R17 29.5

22

V(5) VCC 18

C11 .1U

VCC VEE

V(9) VEE V(9) VEE

Figure 3.44

Chebyshev band pass filter.

0

x 2.445K < 183.6M

>

GNIA ni Vstol

−20.00

−40.00

−60.00

−80.00 200

500

.881 dB Maximum

1K

2K

5K

10K

20K

50K

FREQUENCY in Hz x = 97.55K y = -120.2

Figure 3.45

IsSpice-simulated Chebyshev band pass filter response.

Figure 3.46

PSpice-simulated Chebyshev band pass response.

Figure 3.47

Micro-Cap simulated Chebyshev band pass response. 45

46

Chapter Three

TABLE 3.1

Summary of Results∗

Condition

Hardware

Micro-Cap

IsSpice

PSpice

2.45 0 NA NA

2.42 0.316 BP 2.422

2.4 0.44 Cheby1 3.083

2.44 0.886 BP n2 4.67

Center frequency (kHz) Maximum attenuation (dB) File name Run time AC analysis (s) ∗

For more accuracy, increase the number of points per division.

in Fig. 3.48, and the measured transient response in shown Fig. 3.49. The simulated transient response is shown in Figs. 3.50 and 3.52. All of the simulators correlated well to the hardware. Chebyshev Low Pass Filter The Chebyshev low pass filter shown in Fig. 3.53 was constructed in all three simulators as well as in hardware. The circuit values in Fig. 3.53 were used in all cases. A MathCAD file that was used to design the Chebyshev low pass filter is located in the Chebyshev directory of the CD, which accompanies this book. This file can easily be modified to accommodate designs that use a Sallen–Key circuit for each stage of the filter (see Fig. 3.54). The schematic of the circuit that was used in each simulator is shown in Fig. 3.53. The measured breadboard results are shown in Fig. 3.55, and the simulated results are shown in Figs. 3.56, 3.57, and 3.58.

Figure 3.48

Measured Chebyshev band pass filter response.

Filter Circuits

2500 Hz square-wave input, and sine-wave output.

6.000

12.00

2.000

8.000

−2.000

OUTPUT in Volts

INPUT in Volts

Figure 3.49

−6.000

1 4.000

x 6.325M < 3.234

> x 6.525M < -3.227

−10.000

2

0

>

-4.000

6.138M

6.338M

6.538M

6.738M

6.938M

WFM.2 OUTPUT vs. TIME in Secs x = 200.0U y = -6.461 Figure 3.50

IsSpice 2500 Hz square-wave input, and sine-wave output.

47

Figure 3.51

Micro-Cap 2500 Hz square-wave input, and sine-wave output.

Figure 3.52

PSpice 2500 Hz square-wave input, and sine-wave output.

V(8) VCC

V2 15

C2 .104U

C4 .3U

V3 15

4

R1 1.469K

V(3) VEE V(3) VEE

3 5

VEE

C1 95N

2

R2 1.467K

6

R3 1.478K

7

VEE

VCC 8

C3 21N

11

R4 1.467K

V(3) VEE

R5 1.467K 12

10

VEE

VCC

C5 4.4N

V(8) VCC

1

VCC

V(8) VCC V(8) VCC

Figure 3.53

48

Chebyshev low pass filter.

2Q

1

1

6 4

1

VEE

V21 VIN

Vout

1/2Q 5

VCC 2

Sallen-Key Circuit

Figure 3.54

Sallen–Key circuit.

Figure 3.55

Chebyshev low pass filter, measured data.

Figure 3.56

PSpice Chebyshev low pass filter results. 49

50

Chapter Three

0

x 2.700K < 2.180

>

GAIN in Volts

−20.00

−40.00

−60.00 1

−80.00

2K

3K

4K

5K

6K

7K

8K 9K


Figure 3.57

IsSpice Chebyshev low pass filter results.

Figure 3.58

Micro-Cap Chebyshev low pass filter results.

R7 1.32K

V(6) VCC C1 .1U 4

C3 .1U

10

C4 .1U

VEE

3

V2 AC

R3 2.35K

2

8 7 VEE

VCC

V(6) VCC

R6 46.5K

5

V(5) OUT

V3 15

VCC

6

V4 15

V(6) VCC V(8) VEE

Figure 3.59

Chebyshev high pass filter.

Filter Circuits

Figure 3.60

Chebyshev high pass filter measured results.

Figure 3.61

Chebyshev high pass filter measured results.

TABLE 3.2

SPICE Statistics

51

Simulator

File name

Maximum attenuation

Run time (s)

Hardware PSpice Micro-Cap IsSpice

NA Lp 2 Lp Lp n5

2.03 dB at 2.76 kHz 2.22 dB at 2.75 kHz 2.13 dB at 2.67 kHz 2.18 dB at 2.70 kHz

NA 1 0.329 0.333

Chapter Three

0

0

−20.00

−100.00

−40.00

PHASE in Deg

GAIN in Volts

52

1

−200.0

−60.00

−300.0

−80.00

−400.0

2

20

50

100

200

500

1K

2K

5K

FREQUENCY in Hz

Figure 3.62

IsSpice Chebyshev high pass filter.

Chebyshev High Pass Filter The Chebyshev filter offers higher attenuation and a steeper roll-off near the cutoff frequency than the Butterworth filter. There is a tradeoff to achieve the higher attenuation. The cost of utilizing a Chebyshev filter is higher values of Q, which leads to difficulties in hardware realization, and nonlinear phase characteristics, which can result in difficulties in predicting circuit performance. A Chebyshev high pass filter was constructed with the component values shown in the schematic in Fig. 3.59. The measured results are shown in Figs. 3.60 and 3.61. The results from the three simulators are shown in Figs. 3.62, 3.63, 3.64, and 3.65. All of the simulators accurately predict the phase and gain of the Chebyshev high pass circuit. Electromagnetic Interference (EMI) Filter The last filter that will be looked at in this chapter is the EMI filter. This filter is commonly used on the input of a power circuit to reduce conducted and reflected emissions. For instance, a flyback converter can draw current from the bus that looks like a sawtooth waveform with

TABLE 3.3

Spice Statistics

Simulator

File name

Run time (s)

PSpice Micro-Cap IsSpice

hp 2 hp hp n2

1 0.375 0.233

0

1

GAIN in Volts

−20.00

−40.00

−60.00

−80.00

100

1K

10K

100K

FREQUENCY in Hz

Figure 3.63

IsSpice Chebyshev high pass filter.

Figure 3.64

PSpice Chebyshev high pass filter.

Figure 3.65

Micro-Cap Chebyshev high pass filter. 53

R3 .28 1

3

L1 417U

6

2

C2 69U;60.2

C1 10U;13.4 5

4

R1 3.7

R4 .4

Figure 3.66

R2 10K

EMI filter model (linear).

Output Impedance in dB (Vatts)

20.00

10.00 0

x 1.585K < 11.65

>

0

1

−10.000

−20.00 200

500

1K

2K

5K

10K

20K

50K


Figure 3.67

IsSpice nonlinear core results of output impedance.

Figure 3.68

Measured results of filter output impedance.

54

Filter Circuits

55

a peak amplitude that is dependent on the load. An EMI filter can be designed to smooth these large spikes down to where they are nearly invisible to the bus. The EMI filter presented in this chapter is designed for the flyback topology that converts as low as a 10 V input to a 5 V output. They are several concerns when designing an EMI filter. The parameters of the EMI filter examined in this book reflect these concerns. If the EMI filter is to be used on a converter, the input impedance of the converter must be greater than the output impedance of the filter at all frequencies. It is good practice to allow 6 dB of margin for this parameter. If the output impedance of the filter gets too close to the input impedance of the converter, there can be problems with the stability of the converter. It may be important to note here that this output impedance is sensitive to the effective series resistance (ESR) of the output capacitors. For the hardware data taken for this unit, tantalum capacitors, which have unspecified ESR, were used. The ESR of a similar capacitor was measured for the simulations. Other important characteristics of the converter are the reflected ripple attenuation and the turn-on characteristics. It is expected that the turn-on characteristics will be difficult to simulate because of the nonlinear characteristics of a saturating core. A nonsaturating core is simply described by Faraday’s law, and it can be easily modeled by any of the SPICE simulators. The model used for the EMI filter is shown in Fig. 3.66, and the results of each of the simulators’ output and the measured impedance plots are shown in Figs. 3.67 to 3.70.

Figure 3.69

PSpice filter output impedance results.

56

Chapter Three

Micro-Cap filter output impedance results.

Figure 3.70

The inrush current of an EMI filter is usually examined to ensure that no parts are overstressed during power-up. If the inductor does not saturate, the inrush current is described by Faraday’s law and can easily be modeled by mathematics or a simple SPICE model. It is also not too difficult to determine if a core is saturated during turn-on. A slightly more difficult calculation is to determine what the maximum current will be under a given turn-on condition. The hardware used for measurements used a transformer made of two stacked 55025 cores

R4 10000 5 9

6 1

8

C2 69U;60.2

C1 10U;13.4 3

4 7

R5 .4

Figure 3.71

IsSpice nonlinear core model.

R2 3.7

Filter Circuits

57

30.00

Inrush Current in Amps

x 35.00U < 22.33

>

20.00

10.000

1

0

−10.000 50.00U

150.0U

250.0U

350.0U

450.0U

TIME in Secs x = 465.0U y = −20.98 Figure 3.72

IsSpice results of nonlinear model for inrush current simulation.

Figure 3.73

Measured results of inrush current.

58

Chapter Three

3.000

3.000

2.000

1.000

2.000

Input Current in Amps

Output current in Amps

2

1 1.000

0

0

−1.000

−1.000 4.730M

4.740M

4.750M

4.760M

4.770M

TIME in Secs Figure 3.74

IsSpice attenuation results (nonlinear model).

with 40 turns around them. This was modeled in IsSpice, as shown in Fig. 3.71. Note that a current probe was used to measure the inrush current (Figs. 3.72 and 3.73). It was set on 10 mA/mV, which means that the plot above the y−axis settings are in 5 A/div. It was only measured for Fig. 3.73, and it is 5A/div for the y scale. This filter was designed to have an attenuation of 60 dB. The attenuation is calculated as 20log( Iout / Iin ). Figure 3.74 shows the input versus output current waveforms to demonstrate the lowest reported attenuation.

TABLE 3.4

Parameter

Comparison of Results Conditions

Output impedance (dB) Maximum Turn-on inrush current (A) Attenuation f = 170 kHz (dB) Iout = 2.5 A (max) Duty cycle = 50%

IsSpice IsSpice Micro- Hardware (nonsaturating) (saturating) PSpice Cap data 11.74

11.65

11.71

11.7

11.1

6.17

22.33

6.11

6.16

23.6

56.7

46.7

58.2

58.4

59.3

Filter Circuits

59

Note the saturating core model is available in both PSpice and IsSpice. In PSpice the core is available as part of the AEi Systems Power IC Model Library for PSpice. This figure is shown to give a visual representation of the effects of an EMI filter. Run time summary (s) IsSpice v 8.11 1.65

PSpice v 10.5 4.39


Advantages: Attenuates noise on bus for power converters. Disadvantages: Requires an inductor that is physically a large and expensive part. File names: Filter (IsSpice), non emi (IsSpice), PS emi (PSpice), MC5EMI (Micro-Cap)

Bibliography Parker, Sybil, ed. 1984. Concise Encyclopedia of Science and Technology. New York: McGraw-Hill. Van Valkenburg, M. E. 1982. Analog Filter Design. New York: Harcort Brace Jovanovich College Publishers.


Chapter

4 Power Conversion Circuits

Power converter circuits are often the most overlooked aspect of a system. During the engineering phase, power is not a concern. There are plenty of bench power supplies scattered around the laboratory for use in breadboarding. Even in SPICE, the trusty voltage source element provides infinite voltage and infinite current for new circuit designs. Unfortunately, when the time comes to put the system together, without circuits to condition the power to the system, the system is of little use to anyone. Operational amplifiers frequently need positive and negative DC voltages to operate correctly and amplifiers need both AC and DC voltages, sometimes at high currents, in order to perform their functions. Window comparators and precision sensors need highly accurate AC and DC voltages for the circuit to succeed in its mission. What will power the system when the bench supplies are gone? Luckily, there are circuits that fill all of the power requirements listed above and more. SPICE can be an indispensable tool for designing, troubleshooting, and characterizing power conversion circuits. A simple definition of a power conversion circuit is a circuit that converts a power source of a certain characteristic (e.g., 110 V AC battery voltage, spacecraft bus) into a power source with a more desirable characteristic (e.g., regulated +5V DC for digital logic, constant current sources). A wide variety of these circuits are presented in this chapter.

LM117 Three-Terminal Linear Regulator Three-terminal linear regulator devices have been popular for some time. The combination of simplicity, small package, good regulation, versatility, and reasonable price is attractive to engineers looking to optimize designs. When examining the operation of a three-terminal 61


62

Chapter Four

1

IN

3

OUT

ADJUST

+ VIN 22

LM 117

+ R1 270

2

C4 10 uF

RLOAD 3.3K

1 uF

C_COMP TBD

Figure 4.1

C_Load

R2 3.3K

Typical application for an LM117 three-terminal linear

regulator.

regulator, simulation may not make much sense. An input voltage begets a regulated output voltage. Why simulate this? The answer is explained below. The following circuit (Fig. 4.1) is a typical application configuration for an LM117 circuit. The input voltage is 22 V DC. Resistors R1 and R2 set the regulated output voltage at 16.7 V. One interesting measurement that can be made on this circuit would be the stability. In order to measure the stability in the lab, a special test configuration is used. This test set up is shown in Fig. 4.2. The injection signal must be kept very small (700 µV is suggested), and the measurement probes should be placed at R and A on the diagram in

4

IN

+ V4 22

C4 10 uF

LM 117

OUT

5

ADJUST 7

+ R

R8 270

A

C_Load 1 uF

R_INJ 6.8 6

R9 3.3K 8

C3 TBD

9

Oscillator

Figure 4.2

Stability measurement setup for three-terminal regulator.

R10 3.3K

Power Conversion Circuits

V1 DC = 22 AC = TRAN =

U1 1 1 LM317TI 2 C4 10u R1ESR2 10m

2 LOL

VINJ AC = 1 TRAN = DC =

v out

3

R3 7.1

CLOAD 1U

V

R1 268

10 COL 10

0

Figure 4.3

3

63

R2 3.24K

RESR1 100M

C_COMP 10u

0

I2 5mdc

0

SPICE stability measurement setup for three-terminal regulators.

Fig. 4.2, as shown, with the ground referenced to the output (make sure the power supply in not tied to earth ground). Using the test setup of Fig. 4.2, several configurations were measured in the lab. The cases will be considered one at a time, with comparisons to the SPICE results in each case. The first case is the recommended R operational use by the Linear Databook (Linear Technology 1990, pp. 4–137), which recommends a 1 µF tantalum input bypass capacitor, a 1 µF capacitor at the output, and a 10 µF capacitor at the adjustment pin. The recommended type of capacitor is a solid tantalum. The SPICE configuration for testing stability is shown in Fig. 4.3. The resulting breadboard measurement is shown in Fig. 4.4. The IsSpice result for the same test configuration is shown in Fig. 4.5.

1-28-98 VIN = 22.1V VO = 16.67V Ccomp = 1 µF MM Ccomp = 10 µF MM

Figure 4.4

Breadboard Bode plot (C Comp = 10 µF).

Chapter Four

420.0

40.00

300.0

20.00

180.0

Gain in dB (Volts)

Phase in Deg

64

0

2

60.00

-20.00

-60.00

-40.00

1

1K

10K

100K

FREQUENCY in Hz

Figure 4.5

IsSpice Bode plot (C Comp = 10 µF).

Comparing the results of Figs. 4.4 and 4.5, it was found that the phase margin is 21.4◦ in the breadboard plot and 15.85◦ in the IsSpice plot. The crossover in the breadboard plot was 27.7 kHz, compared with 53.7 kHz in the IsSpice plot. The general shapes of the curves are also very similar. SPICE tip There are three models of LM117 in the Intusoft model library. One model gave the correct DC output voltage and the correct Bode response. One gave an incorrect DC output voltage but the correct Bode response, and one did not converge. Surprisingly, all three models are transistor level. This is just another example of the necessity of testing previously unused models against their data sheet performance in order to ensure model accuracy. Incidentally, the model used in these simulations is the LM317TI model.

The LM117 configuration was also tested without a C COMP capacitor. The breadboard results are shown in Fig. 4.6, and the IsSpice results are shown in Fig. 4.7. The breadboard phase margin and crossover frequency are 7◦ and 7.4 kHz, respectively. The SPICE simulation phase margin and crossover frequency are 1.7◦ and 14.7 kHz, respectively. Good engineering practice suggests a minimum phase margin of 45◦ . The final configuration approaches this value. The C COMP capacitor is changed to 4700 pF. The breadboard measurements are shown in Fig. 4.8, while the IsSpice results are shown in Fig. 4.9.


65

1-28-98 VIN = 22.1V VO = 16.67V Ccomp = 1 µF MM Ccomp = Open

Figure 4.6

Breadboard Bode plot (C Comp = open).

420.0

40.00

300.0

20.00

180.0

Gain in dB (Volts)

Phase in Deg

The breadboard phase margin and crossover frequency are 41.7◦ and 8.3 kHz, respectively. The IsSpice simulation results show a phase margin of 44.6◦ and an 11 kHz crossover. Examining the results of the testing and simulation, we can conclude that there is an optimal value of the C COMP capacitor that maximizes phase margin and

0

2

60.00

−20.00

−60.00

−40.00

1K

10K

FREQUENCY in Hz

Figure 4.7

IsSpice Bode plot (C Comp = open).

100K 1

66

Chapter Four

1-28-98 VIN = 22.1V VO = 16.66V Ccomp = 1 µF MM Ccomp = 4700 pF

OdB

Odeg

Breadboard Bode plot (C Comp = 4700 pF).

Figure 4.8

creates an optimally stable three-terminal regulator. An excellent tool for determining this optimal capacitance is SPICE. The optimizer function of the SPICE simulators is tailor made for this problem. The optimization feature can be performed in MicroCap by using the STEPPING feature in the AC menu, and in PSpice by using the PARAMETRIC sweep in the setup dialog box. In IsSpice, the OPTIMIZER sweep menu is selected by selecting the SIMULATION CONTROL item in the ACTIONS menu of ICAP.

420.0

40.00

300.0

20.00

180.0

gain in dB (Volts)

Phase in Deg

SPICE tip

0

2 60.00

−20.00

−60.00

−40.00 1 1K

10K

FREQUENCY in Hz

Figure 4.9

IsSpice Bode plot (C Comp = 4700 pF).

100K


80.00

x 7.000N < 66.54

67

>

phase_margin in Deg

60.00

40.00

1

20.00

0

10.00N

30.00N

50.00N

70.00N

90.00N

phase vs. CAP

Figure 4.10

Optimizer sweep to determine optimal C COMP capacitance.

The resulting graph from the IsSpice optimizer sweep is shown in Fig. 4.10. Note that the optimal capacitance value is approximately a 6.8 nF, which produces a phase margin of 66.5◦ . Simulations of this circuit were also performed in Micro-Cap. The configuration shown in Fig. 4.3 was simulated with a C COMP value of 4700 pF. The resulting Micro-Cap Bode plot is shown in Fig. 4.11.

Figure 4.11

Micro-Cap results with C COMP = 4700 pF.

68

1

Chapter Four

60

2

480d

400d 40

300d

20 200d

0 100d

-20

0d

-40

-120d >> 100H 1

300H DB(V(vout)) 2

1.0KH P(V(vout))

3.0KH

10KH

30KH

100KH

300KH

1.0MH

Frequency

Fig. 4.11a

PSpice results with C COMP = 4700 pF. Run time summary (s)

IsSpice v 8.11 0.422

PSpice v 10.5


Advantages: Low parts count, inexpensive, good accuracy, good ripple rejection Disadvantages: Excessive power dissipation at higher currents, not as efficient as other topologies (owing to headroom requirements) File names: 117Bod, 117opt (IsSpice); 117bod3 (PSpice); 117bod2 (Micro-Cap)

LM78S40 Simple Switcher DC-to-DC Converter Many semiconductor manufacturers make ICs that encompasses all of the necessary logic and analog circuitry required to construct a switching regulator circuit. An example of this universal approach to deR LM78S40 IC. This IC contains a temperaturesign is the National compensated precision voltage reference, MOSFET driver logic, current limiter, error amplifier, an oscillator, and even a built-in rectifying diode. ICs like this one are excellent for DC-to-DC applications that require more power than a three-terminal linear regulator can provide, but do not require isolation. The block and connection diagrams for this IC are shown in Fig. 4.12. The schematic for our test circuit is shown in Fig. 4.13. The test circuit takes a 20 V DC input and provides a regulated 10 V DC output.


69

Block and connection diagrams for LM78S40 IC R (reprinted with permission from National Semiconductor , Power IC’s Databook, 1993).

Figure 4.12

V(11) SWITCH

L1 239U 15

V(15) VOUT

anode 11

R2 8.2K

RLOAD 25

C2 47U

emitter

C3 1U

6 1 7

R3 1.18K

Figure 4.13

V(13) VREF

8 13

switch C

cathode driver C I sense

amp out

Vin

amp vcc

Ct

amp +

3

gnd 12

amp -

comp -

vref

comp +

Test schematic for 78S40 simple switcher IC.

4

V(3) OSC C1 2.35N

V1 20

70

Chapter Four

V(11) SWITCH

L1 239U 15

11

I(V3) L

V(5) VOUT

R_DCR .5 anode

5

R2 8.2K

RLOAD 25

C2 47U

14

6 1 7

R3 1.18K

Figure 4.14

cathode driver C emitter

C3 1U

V(13) VREF

8 13

switch C

I sense

amp out

Vin

amp vcc

Ct

amp +

4 3

gnd 12

amp -

comp -

vref

comp +

V(3) OSC C1 2.35N

V1 PULS

SPICE equivalent schematic for 78S40 simple switcher IC.

The SPICE equivalent circuit schematic is shown in Fig. 4.14. Note that the DCR (DC Resistance) of the inductor L1 has been added (R DCR) to the circuit. Also added to the circuit is a voltage source between the inductor and the output in order to measure inductor current. The input voltage is pulsed from 0 V to 20 V in order to help get the simulation started. To aid in convergence, the following .OPTIONS statement is also included: .OPTIONS ABSTOL = 1U ITL4 = 1000 ITL6 = 100 METHOD = GEAR Note: PSpice does not support the Gear integration option. It instead relies on a modified trapezoidal-Gear integration algorithm for transient timestep operation. The transient simulation is run from 2.15 to 2.35 ms, with a maximum time step of 100 ns. The transient line also contains the UIC command which will cause SPICE to use the initial conditions specified in the schematic and not attempt to find a DC operating point. The results of the breadboard waveforms and the IsSpice waveforms are compared side by side in Figs. 4.15 and 4.16. Figure 4.15 shows the output ripple voltage at the top, with the inductor voltage at the bottom. Figure 4.16 shows the oscillator frequency at the top, with the


9.950

80.00

9.850

40.00

VOUT in Volts

SWITCH in Volts

1 120.0

9.750

0

9.650

−40.00

9.550

2

2.172M

2.212M

2.252M

2.292M

2.332M

TIME in Secs Figure 4.15a

IsSpice LM78S40 waveforms (top, output ripple; bottom, inductor

voltage).

Figure 4.15b

voltage).

Breadboard LM78S40 waveforms (top, output ripple; bottom, inductor

71

Chapter Four

1.000

120.0

600.0M

80.00

200.0M

SWITCH in Volts

OSC in Volts

72

2

40.00

−200.0M

0

−600.0M

−40.00

1

2.172M

2.212M

2.252M

2.292M

2.332M


IsSpice LM78S40 waveforms (top, oscillator voltage; bottom, inductor

voltage).

Figure 4.16b Breadboard LM78S40 waveforms (top, oscillator voltage; bottom, inductor voltage).


73

inductor voltage at the bottom. The output voltage of the IsSpice model was 9.872 V, while that of the breadboard was 9.78 V. SPICE tip SPICE models for the LM78S40 were not provided in the MicroCap software package. This circuit was simulated using IsSpice and PSpice only.

Run Time Summary (s) IsSpice v 8.11 50

PSpice v 10.5 96.78

Advantages: Medium parts count, good output voltage line and load regulation, versatile, can provide step-up or step-down voltages Disadvantages: No isolation from input to output File names: 7840 1 (IsSpice), 7840 (PSpice)

UA723 Hysteretic Buck Regulator The UA723 can be configured to form a simple, low parts count buck regulator. The UA723 is designed for use in positive or negative power supplies. This type of regulator is popular because it has excellent dynamic response. It can be configured as a series, switching, shunt, or floating regulator. The circuit has variable frequency, because it

V(3) VSWITCH

R8 219K

X2 TIP42

V1 11.64;PU

L1 362U 3

D1 DN5811

C2 10U 16

R5 97.8 X1 UA723 NC

10

V(4) 4 1

R3 2.17K

V(11) CAP

5

CL

FRCO

CS

VCC+

6

IN-

VC

8

IN+

VOUT

VREF

NC

VCC-

R7 982

R9 .1

NC

NC

V(8) BASE

2

R1 9.9 V(10) VOUT

11

C1 .1U

Figure 4.17

R4 5.58K

Schematic for UA723 buck regulator.

R6 20

74

Chapter Four

Figure 4.18

Breadboard collector voltage of UA723 buck regulator.

essentially an uncompensated oscillator. The output ripple is a function of the hysteresis. This comes at the cost of a decrease in the ability to maintain regulation. The schematic is shown in Fig. 4.17. The breadboard data are shown in Figs. 4.18 and 4.19. The IsSpice simulated data are shown in Figs. 4.20 and 4.21. Transient domain simulation of switching power supplies are extremely sensitive to the FET and transistor models, as well as the SPICE control statements used to govern the simulation. The turn-on and turn-off characteristics of the transistor model must be accurate to gain any useful information from a simulation, especially at higher frequencies. Convergence can be a major factor in the simulation of transient domain models. By loosening the restraints on the numeric integration process (RELTOL, VNTOL, and ABSTOL), convergence may be achieved, as well as a faster simulation times, at the expense of accuracy. Once convergence and proper simulation results have been established, simulation accuracy can be increased over a shorter run time to obtain accurate results, as was done in the previous sections. The simulation was performed by substituting the transistor TIP-42 with a QSB1071A. The results of this simulation, shown in Figs. 4.22 and 4.23, correlate better to the measured data. The only difference is the transistor model. To illustrate the importance of the .OPTIONS statement, the original circuit shown in Fig. 4.17 was simulated with the


Figure 4.19

Breadboard UA723 waveforms (top, output ripple; bottom, inductor

voltage).

5.500

1.600

1

5.100

1.200 @L1[I] in Amps

VOUT in Volts

5.300

800.0M

2 4.900

400.0M

4.700

0

2.020M

2.060M

2.100M

2.140M

2.180M


voltage).

IsSpice UA723 waveforms (top, output ripple; bottom, inductor

75

76

Chapter Four

12.00

VSWITCH in Volts

8.000

4.000

0 1

−4.000 2.020M

2.060M

2.100M

2.140M

2.180M

TIME in Secs Frequency=15.49KHz Duty Cycle=51.46%

IsSpice collector voltage of UA723 buck regulator.

Figure 4.21

following .OPTIONS statement: .OPTIONS METHOD = GEAR RELTOL = .01 GMIN = 1N This was changed from the previous .OPTIONS statement: .OPTIONS METHOD = GEAR RELTOL = .001

12.00

1

VSWITCH in Volts

8.000

4.000

0

−4.000

2.020M

2.060M

2.100M

2.140M

2.180M

TIME in Secs Frequency=16.72KHz Duty Cycle=46.7%

Figure 4.22

QSB1071A.

IsSpice collector voltage of UA723 buck regulator with

5.400

1.615

5.200

1.215

5.000

@L1[I] in Amps

VOUT in Volts


77

2 815.0M

4.800

415.0M

4.600

15.00M

1

2.020M

2.060M

2.100M

2.140M

2.180M

TIME in Secs Vout=376mV pk-pk I(L1)=494.7mA pk-pk

IsSpice UA723 waveforms (top, output ripple; bottom, inductor voltage) with QSB1071A.

Figure 4.23

The results of this simulation are shown in Figure 4.24. Notice the shape of the TIP-42 collector waveform. Table 4.1 gives a summary of the results. The results indicate a tradeoff between simulation run time and simulation accuracy.

40.00

5.476 1

20.00

5.076 VOUT in Volts

VSWITCH in Volts

30.00

4.676

10.000

4.276

0

3.876

2

3 4.670M

4.710M

4.750M

4.790M

4.830M

TIME in Secs

IsSpice UA723 waveforms (top, output ripple; bottom, inductor voltage) with TIP-42.

Figure 4.24

78

Chapter Four

TABLE 4.1

Summary of Results

Condition Frequency (kHz) Vout(pk−pk) (V) Vout (V) Inductor current (mA) Run time (s) ∗

Breadboard

TIP-42

TIP-42∗

QSB1071A

27.82 244 5.22 308 NA

15.49 422 5.27 517.6 82.93

14.29 626 5.28 550.8 27.31

16.72 376 5.24 494.7 68.42

.OPTIONS METHOD = GEAR, RELTOL = 0.01, GMIN = 1N.

The simulation results do not correlate well to the hardware. A possible cause is the ESR of a Mallory TDC106K505WSG 10 µF capacitor, C2. The feedback loop is originated at the collector of the PNP transistor to avoid sensitivity to the output capacitor’s ESR. However, investigation into the poor correlation indicates that the circuit is sensitive to the ESR of capacitor C2. The ESR was measured using an HP 3577A network analyzer. The results are shown in Fig. 4.25. The setup to make the measurement of capacitor C2 inverted the signal, which is why the ESR measurement is inverted. The ESR of capacitor C2 is dependent on frequency. The hardware frequency is approximately 27 kHz. The ESR at this frequency is approximately 386 m. Another schematic, which reflects the appropriate ESR of C2 and the DCR of inductor L1, is shown in Fig. 4.26. The schematic includes the circuitry that was used to measure the transient response of the hardware.

Figure 4.25

Measured ESR of C2.


79

13

V(3) VSWITCH

R8 219K

L1 362U

V(9) FEEDBACK

3

V1 11.64

D1 DN5811 R5 97.8 X1 UA723

9

V(4)

NC

CL

FRCO

5

CS

VCC+

6

IN-

VC

8 2

4

IN+

VOUT

1

VREF

NC

R3 2.17K

V(11) CAP

11

C1 .1U

NC

C2 10U

R6 4.9

16

R9 .4

NC

VCC-

R7 982

V(9) VOUT

R13 .3

7

12

V(12) PULSE

R10 14.9 10

V(8) BASE

R12 .6

R1 9.9 V(9) FEEDBACK

R4 5.58K

Figure 4.26

UA723 buck regulator with measured ESR and DCR.

The measured and simulated data are shown in Figs 4.27 to 4.32. A precarious dilemma results when creating a model that can accurately depict a transient response of the converter as well as the output ripple. The ESR of capacitor C2 is a function of frequency. When simulating the output ripple of the converter, the frequency is essentially constant, approximately 25 kHz. However, when the converter

Figure 4.27

Measured UA723 buck regulator transient response.

80

Chapter Four

6.500

40.00

5.500

30.00

4.500

3.500

PULSE in Volts

VOUT in Volts

1

20.00

10.000

x 1.972M < 0 2.500

x 2.069M < 0

>

0

2

1.925M

1.975M

Vmax=6.716V, Vmin=5.087V

Figure 4.28

>

2.025M

2.075M

2.125M

TIME in Secs x = 96.90U y = 0

IsSpice UA723 buck regulator transient response.

encounters a transient, the response is at a much lower frequency, approximately 5 kHz. The ESR for the transient response simulation is different from that for the output ripple simulation. The solution is to either create a capacitor model that has ESR which varies with frequency or change the ESR to the appropriate value for each simulation. The ESR of capacitor C2 is relatively constant from 5 kHz through 20 kHz, but varies immensely outside these frequencies.

Figure 4.29

Micro-Cap V UA723 buck regulator transient response.


Figure 4.30

81

Breadboard UA723 waveforms (top, output ripple; bottom, inductor

voltage).

5.300

900.0M

5.100

700.0M

4.900

@L1[I] in Amps

VOUT in Volts

1

500.0M

4.700

300.0M

4.500

100.00M

2 2.210M

2.230M

2.250M

2.270M

TIME in Secs Vpp=246.4mV; Ipp=395.87mA Figure 4.31

IsSpice UA723 buck regulator output ripple.

2.290M

82

Chapter Four

Figure 4.32

Micro-Cap V UA723 buck regulator output ripple.

In correlating to the transient response, many difficulties arose. The ESR of C2 determines the magnitude of the transient response, as well as the frequency of the output ripple. Varying the ESR of C2 varies the period of the output ripple in which the transient occurred. A larger magnitude of the transient response corresponds to the transient occurring while the transistor is conducting, which indicates that the simulation results are dependent on when the transient occurs. Table 4.2 gives the summary of the results. 1524A Buck Regulator The SG1524A advanced regulating pulse width modulator can be configured to create a voltage mode controlled buck regulator. This type

TABLE 4.2

Summary of Results

Condition Frequency (kHz) Vout(pk−pk) (V) Vout(avg) (V) Inductor current (mA) Peak-to-peak transient response (V) Response duration (µs) Run time of transient response (s)

Breadboard

IsSpice v 8.11

Micro-Cap v8.0

27.82 244 5.22 308 1.6 90 NA

21.3 246 5.21 395.9 1.63 97 147.88

22 292 5.11 396 1.39 88 74.56


83

of regulator will produce an output voltage that is proportional to the duty cycle. The duty cycle is a function of input voltage and loading. The switched voltage is averaged by an L-C filter, which produces a DC output voltage. There are two types of models that can be utilized to analyze switching circuits. The first is an averaged or state space model, which represents the operation of the switching circuit via linearizing techniques. All linear circuits fall into the category of average models. The benefits of using an average model are extremely fast simulation times, reasonable accuracy, and compatibility with AC, as well as, transient domain simulations. Averaged models can be used for predicting phase and gain margins, conducted susceptibility, startup, line and load transients, and input and output impedance. Transient models represent the actual switching action of the circuit in the time domain. This type of model is useful in determining the time domain characteristics of a circuit. These models can be very accurate and display switching spikes, ripple, and propagation delays, and other transient characteristics associated with switching circuits. There are two major disadvantages in using a transient model. Because the simulation accurately models the time domain switching characteristics of the circuit, a simulation run can take a considerable amount of time. Higher frequency circuits require smaller step sizes to accurately predict the time domain characteristics, which increase simulation run times. Transient models cannot be used to determine the AC characteristics of a circuit.

11

V(19) SWITCH

L2 100U

X5 MTP12P10 I(V2) ISWITCH

V2 10

Q3 QN2222

V(13) FEEDBACK

9

R17 21.4K

R18 1.482K

C4 .047U

R13 46.4

R21 9.5K 18 INV

R19 46.1K

R20 21.5K 26

C8 .01U

R10 3.25K

VIN EB

+CL X3 CB UC1524 -CL CA

1 RT 2 CT

C3 2.2N

VREF

3 NINV 17 SYNC

GND

21 8

V(7) DRIVE

7

EA SD COMP

16

V(16) COMP

Figure 4.33

5

X6 MBR2045

I(V3) IND

4

V(13) FEEDBACK

Schematic of SG1524 buck regulator.

R14 4.7

V(13) OUT

13

C6 220U 12

6

R11 9.85K

10

C7 6.8N

C5 .1U

D2 DN4148

R12 .978K

19

R22 .05

R15 100M

R16 2

84

Chapter Four

R8 6.7

R3 21.4K

R6 21.5K

1

4.84 6

C2 6.91N

4.84

R4 1.482K

7

15

4.97

4.97

3

L1 100U

R9 .05

9

10.00

2.43

R2 46.1K

C1 10.3N

V1 10

4

10

13

4.97

4.85 C3 220U

2.29

12

−5

2.43 R5 100M

E/A +2

Comp

2.43

R7 9.3K C4 .047U

Figure 4.34

11

R1 9.85K

RLOAD 2

0

5.00

5V

8

497M

Osc.

Ref.

SG1524 buck regulator average model.

The schematic of the SG1524 buck regulator is shown in Fig. 4.33. The values of the capacitors and resistors are measured values. The phase and gain margins were measured using an average model of the SG1524 buck regulator. The schematic of the average model is shown in Fig. 4.34. There are five parameters that must be passed to the average SG1524 model. T = 6.44µs TO = 300 ns TS = 100 ns EP = 3.7 V EO = 0.85V

Switchingperiod Deadtime Transistorstoragetime Peaksawvoltage Minimumsawvoltage

These values were measured on the breadboard circuit and are shown in Figs. 4.35 and 4.36. The following equations are used to predict the pole and zero locations of the feedback loop. The output filter causes a double pole at L2 : = 100 × 10−6 C6 : = 220 × 10−6 F1 : =

2π ×

1 √

L2 C6

F1 = 1.073 × 103


85

One of these two poles is canceled by R17 and C7: R17 : = 21400 C7 : = 6.8 × 10−9 F2 : =

1 2π R17 C7

F2 = 1.094 × 103 A third pole is created by capacitor C8 and resistor R19: R19 : = 46100 C8 : = 0.01 × 10−6 F3 : =

1 2π R19 C8

F3 = 345.238 A zero is caused by the output filter capacitor, and the ESR of the output filter capacitor: C6 : = 220 × 10−6 R15 : = 100 × 10−3 F4 : =

1 2π R15 C6

F4 = 7.234 × 103 This zero gets cancelled by R18 and C7: C7 : = 6.8 × 10−9 R18 : = 1.428 × 103 F5 : =

1 2π R18 C7

F5 = 1.639 × 104

86

Chapter Four

Figure 4.35

Transistor storage time.

Figure 4.36

Saw waveform resulting from Rt and Ct.


Figure 4.37

87

ESR of output filter capacitor C6.

Because the ESR of the output filter capacitor creates a zero, it is essential to measure this term. The ESR measurement of output filter capacitor C6 is shown in Fig. 4.37. The ESR is approximately equal to 100 m at the bandwidth of the converter. Once the ESR is determined, the open loop phase and gain can be measured as shown in Fig. 4.38 and simulated as shown in Fig. 4.39. The transient domain model shown in Fig. 4.33 was used to measure output ripple voltage, transient response, gate voltage, and inductor current. This model properly predicts the cycle-by-cycle switching effects of the regulator. Figure 4.40 shows the simulated output ripple voltage, while Fig. 4.41 shows the simulated output voltage ripple. The measured transient response is shown in Fig. 4.42, while the simulated transient response is shown in Fig. 4.43. The measured output inductor current and the PWM drive voltage are shown in Fig. 4.44, while the simulated response is shown in Fig. 4.45. The measured output voltage turn-on is shown in Fig. 4.46, while the simulated responses, using the transient domain model and the state space model, are shown in Figs. 4.47 and 4.48 respectively. A comparison between the step load response using the transient domain model and the state space average model is shown in Fig. 4.49, while a similar comparison of the output inductor current during the transient step load is shown in Fig. 4.50.

88

Chapter Four

Measured phase and gain margins.

40.00

450.0

20.00

350.0

0

PHASE in Deg

GAIN in Volts

Figure 4.38

250.0

−20.00

150.0

−40.00

50.00 1K

10K

100K

1MEG

FREQUENCY in Hz 2 1 Phase=99.23 degrees; Gain=33.4 dB; Bandwidth=14.5KH: Figure 4.39

Simulated phase and gain margins.


89

Output Ripple in Volts

4.980

4.940

1

4.900

4.860

4.820

9.125M

9.130M

9.135M

TIME in Secs x = 5.000M y = -1.145M Figure 4.40

Simulated output ripple.

Figure 4.41

Measured output ripple.

9.140M

9.145M

90

Chapter Four

Figure 4.42

Measured transient response.

5.100

x 5.004M < 5.010

>

OUT in Volts

5.000

1

4.900

x 7.314M < 4.910

>

4.800

4.700 5.500M

6.500M

7.500M


Simulated transient response.

8.500M

9.500M


Figure 4.44

91

Measured output inductor current and gate drive voltage.

1.645

35.00

1.445

25.00

1.245

DRIVE in Volts

IND in Amps

1

1.045

15.00

5.000 2

845.0M

−5.000

6.840M

6.845M

6.850M

6.855M

6.860M

TIME in Secs Frequency=141KHz; Duty Cycly=47% Figure 4.45

Output inductor current and gate drive voltage.

92

Chapter Four

Figure 4.46

Measured turn-on of SG1524 buck regulator.

6.000

Tran. Turn On in Volts

1

x 1.887M < 4.920

4.000

>

2.000

0

−2.000 340.0U

940.0U

1.540M

2.140M

2.740M


Simulated turn-on of SG1524 buck regulator using transient model.


x 1.696M < 4.852

6.000

93

> 1

Avg. Turn On in Volts

4.000

2.000

0

−2.000

340.0U

940.0U

1.540M

2.140M

2.740M

TIME in Secs x = 1.696M y = 4.852 Figure 4.48

Simulated turn-on of SG1524 buck regulator using average model.

Low Drop-Out Regulator Multiple output power converters may not provide regulation that is good enough to meet the requirements of every output. The regulation of a single output of the converter may require some type of post regulation to meet the regulation requirements of that output. In many

5.230 1

4.800

4.700

4.600

Transient Output(wfm2) in Volts

State Space Output (wfm 1) in Volts

4.900

4.500

5.130

5.030

4.930

2

4.830

5.500M

6.500M

7.500M

8.500M

9.500M


Average versus transient switching model step load response.

94

Chapter Four

3.000 Tran. Inductor Current (Wfm1) in Amps

Avg. inductor Current (wfm2) in Amps

5.000

4.000

3.000

2.000

1 2.000

1.000 2 0

-1.000

1.000

5.500M

6.500M

7.500M

8.500M

9.500M


Average versus transient model step load response of inductor current.

applications, a simple three-terminal regulator may be used. However, some applications may be sensitive to efficiency. In these applications, the use of a low drop-out linear regulator, which is shown in Fig. 4.54, may be used to meet the specific regulation requirements of a particular output. This circuit utilizes a MOSFET as a source follower. The MOSFET is controlled by a TL431 shunt regulator integrated circuit.

10 9 Probe1-NODE / V

8 7 6 5 4 3 2 1

0 Time/mSecs

0.5

1

1.5

2

2.5 500uSecs/div

Figure 4.51 SIMetrix results: simulated turn-on of SG1524 buck regulator using a transient model.


95

9 8.9 8.8 I1-neg / V

8.7 8.6 8.5 8.4 8.3 8.2 8.1 5.5

6

6.5

7

7.5

8

8.5

Time/mSecs Figure 4.52

9

500uSecs/div

SIMetrix results: transient model step load response.

The MOSFET reduces the minimum input-to-output differential or headroom of 1.5 V to the 2 V of a typical three-terminal regulator, down to the product of the output current and the ON resistance of the MOSFET. The lower the ON resistance of the MOSFET used in the circuit, the lower the headroom of the regulator. This circuit requires a bias voltage for the MOSFET gate, which must be several volts greater than the output voltage. If a large enough voltage is not available in the power converter, then a CMOS charge pump can be used to generate it. The dominant pole is created by the source impedance of the MOSFET, and the output capacitor. A second pole is created by the MOSFET’s Ciss and its driving impedance. Therefore, the MOSFET

Tran. Inductor Current / A

4.4 4.2 4 3.8 3.6 3.4 3.2 5.5 Time/mSecs Figure 4.53

6

6.5

7

7.5

8

8.5

9

9.5 500uSecs/div

SIMetrix results: transient model, step load response, inductor current

96

Chapter Four

TABLE 4.3

SPICE Statistics∗

File name

Simulation

Type of model

AVG TON 1524 TON AVG TRAN SG1524 AVG1524

Transient Transient Transient Transient AC

Average Transient Average Transient Average

∗

SIMetrix run time (s)

IsSpice run time (s)

X 143.172 X 296.656 X

0.933 156.3 1.050 366.5 0.516

The SG1524 model was simulated in IsSpice and SIMetrix, RELTOL = 0.01, TMAX 50n

is the major contributor to the accuracy of the phase and gain margin measurements. A zero is contributed by the compensation of TL431, R2, and C1, which has a corner frequency of approximately 12.8 kHz. In order to measure the control loop stability of the regulator, a simple modification was made to the circuit. L1 and C3 were added to the circuit to effectively open the control loop of the regulator. This allows AC phase and gain measurements to be made. The ESR of capacitor C2

R9 .1 3

0

C2 22U

C5 .1U 6

8

10.00

V2 10

5

R6 10

4

18.0

V1 18

V(8) VOUT

7.76

R5 9.77K

R10 8.2

11.7 9

R1 .978K 2

L1 1

1

11.1

X1 TL431

7.75

C1 4.7N

R2 2.65K

11.1

R3 5.56K 7

11

2.50

R4 2.64K

7.75 C3 1 10

0

V3 AC

Figure 4.54

TL431 low drop-out linear regulator circuit.


Figure 4.55

97

22uF (TDC226K050WSG) ESR.

is shown in Fig. 4.55. The simulated and measured results are shown in Figs. 4.56 to 4.61. The poor correlation of the phase and gain margins can be addressed and corrected. The major player in the phase and gain margins is the MOSFET. The MOSFET used in the hardware is IRF641, which was not available in the IsSpice libraries. To select a MOSFET that is an appropriate match, the data sheet and the correlation to the phase and gain margins of the regulator need to be evaluated. Because the dominant poles are determined by the characteristics of the MOSFET model, selection of a substitute model requires verification of the phase and gain characteristics dictated by the use of a particular model. MOSFETs can be difficult to model, and they are notorious for being inaccurate. Rather than building a MOSFET model of IRF641, an alternate solution was chosen to obtain correlation to the TL431 regulator circuit. To correlate to this model, the correct capacitance of the MOSFET needs to be accounted for. This can be achieved by manipulating the values of the output filter capacitor to values that create the proper phase and gain margins. The modified schematic of this model is shown in Fig. 4.62. The measured results, and the IsSpice and SIMetrix simulated results are shown in Figs. 4.63 to 4.71. File names:

TL431, TL431is, TL431 B (IsSpice); TL431 Ton, TL431 Sim, TL431 AC (SIMetrix)

98

Chapter Four

Figure 4.56

Measured low drop-out regulator phase and gain margins.

100.00

40.00

x 5.603K < 98.01

PHASE in Deg

GAIN in Volts

0

>

60.00

20.00

2

20.00

−20.00

−20.00

−40.00

−60.00

1

1K

10K

100K

1MEG

FREQUENCY in Hz x = 5.503K y = 6.740 Figure 4.57 Simulated low drop-out regulator phase and gain margins. Note the excellent gain and phase margin correlations.


14.00

x 185.0U < 7.720

VOUT in Volts

10.000

> 1

x 1.000M < 7.758

6.000

2.000

−2.000

100.00U

300.0U

500.0U

700.0U

TIME in Secs x = 815.0U y = 37.57M

Figure 4.58

Simulated low drop-out regulator turn-on.

Figure 4.59

Measured low drop-out regulator turn-on.

900.0U

>

99

100

Chapter Four

Figure 4.60

Measured low drop-out regulator transient response.

8.560

VOUT in Volts

8.160

1

7.760

7.360

6.960 600.0U

800.0U

1.000M

1.200M

TIME in Secs

Figure 4.61

Simulated low drop-out regulator transient response.

1.400M


R9 5M 3

C5 .1U

X8 AEI150

6

10.00

V2 10

8

V(8) VOUT

694N

R5 9.77K

R6 10

4

5

18.0

V1 18

694N

C2 10U

R10 8.2

3.08

R1 .978K 2

1

2.00

X1 TL431

C1 4.7N

R2 2.65K

773M 11

R3 5.56K 7

1.14M

773M

R4 2.64K

Figure 4.62

TL431 modified low drop-out linear regulator circuit.

Figure 4.63

Measured modified low drop-out regulator phase and gain

margins.

101

Chapter Four

40.00

80.00

20.00

40.00

0

PHASE in Deg

GAIN in Volts

102

0

2 −20.00

−40.00

−40.00

−80.00 1K

10K

100K

FREQUENCY inHz 96.1 degrees,47.1dB,5.73KHz

Figure 4.64

Modified low drop-out regulator phase and gain margins.

Figure 4.65

Measured modified low drop-out regulator transient response.

1


8.560

VOUT in Volts

8.160

1

7.760

7.360

6.960 600.0U

800.0U

1.000M

1.200M

1.400M

TIME in Secs

Figure 4.66

Simulated modified low drop-out regulator transient response.

Figure 4.67

Measured modified low drop-out regulator turn-on.

103

104

Chapter Four

14.00

VOUT in Volts

10.000 1 6.000

2.000

−2.000

100.00U

300.0U

500.0U

700.0U

900.0U

TIME in Secs

Figure 4.68

Simulated modified low drop-out regulator turn-on.

30 20 10 0 -10 -20 -30 -40 -50 -60

Y1

80 Phase / degrees

dB / db

Y2

60 40 20 0 -20 100 200 400

1k

2k

4k

10k 20k 40k

100k 200k 400k 1M

Frequency / Hertz Figure 4.69

SIMetrix modified low drop-out regulator phase and gain margins.


105

Q2-S / V

7.9 7.8 7.7 7.6 7.5

0.6

0.7

0.8

0.9

1

1.1

1.2


1.3

100uSecs/div

SIMetrix simulated modified low drop-out regulator transient response.

8 7

Vout / V

6 5 4 3 2 1 0

0.2

0.4

0.6

0.8

1

1.2


SIMetrix simulated modified low drop-out regulator turn-on.

1.4 200uSecs/div

106

Chapter Four

STR6600 Quasi-Resonant Discontinuous Flyback Quasi-resonant converters have additional desirable characteristics that standard switching converters do not. Quasi-resonant converters can greatly decrease the power losses dissipated in the semiconductor components while reducing radiated interference (Brown 1994). These converters accomplish this by forcing the voltage or current into a sinusoidal waveform. The quasi-resonant converter switches the MOSFET while the current or voltage is zero, resulting in little or no switching losses. An example of this type of power supply is a zero-current switching (ZCS) quasi-resonant power supply utilizing the STR6600 hybrid IC. STR6600 contains both the power MOSFET and the control circuitry for implementing this type of power supply. In a ZCS-type circuit, the current through the power switch is forced to be sinusoidal and the transistor is switched when this current is at or near zero. The following circuit (Fig. 4.72) shows the implementation of a quasiresonant flyback converter featuring the STR6600. A switching cycle begins with the turn-on of the power MOSFET, which is internal to STR-F6524. The current in the MOSFET rises, starting at approximately 0 A and increasing at a rate determined by the input voltage and the primary inductance of the power transformer. The current generates a proportional voltage across the resistor connected from the source pin to the input return. A control signal is added to the current signal via a resistor connected from the source pin to the OCP pin, allowing a voltage or current injection into the OCP pin. The MOSFET will be turned off when the sum of the source current and the control signal reaches 0.73 V. After the MOSFET turns off, the drain voltage rises and the primary peak current is delivered to the load. The current then falls at a rate determined by the output voltage and the primary inductance. Once the energy in the primary inductance is depleted, the drain voltage falls, in accordance with the resonant characteristics of the primary inductance and the resonant capacitance (plus the primary transformer capacitance and the MOSFET output capacitance). On the basis of actual measurements of the components, several modifications were made to the values listed on the schematic. Resistor R5 is actually 0.14 in the breadboard. The primary inductance of the power transformer measured 324 µH. The output capacitor measured 200 µF with an ESR of 0.13 .


Circuit schematic for quasi-resonant flyback converter.

107

Figure 4.72

108

Chapter Four

X2 XFMR

VIN 200 8

STR-F6524 Vin

15

158

117

Average Model FB/OCP 5

3.17 R53300

17

Vout

200

7

C3 1P

L1 1P

1

730M

0 C1 200U

Source 6

R1 250

V4 AC

4

226M

0

R4 680

R2 .131 R3 .14 3

18.9 X3 XFMR

R6 1K 11

15.0

X6 O66092

9

18.4

V3 15

16

117 10

12

3.76

17.3

R7 100K 14

Q1 QN2222A

13.4 R8 13K

13

12.8

D1 Z04AZ13

R9 1K 2

17.3 C2 .1U

Figure 4.73

State space SPICE model for the quasi-resonant Flyback circuit.

Construction of the SPICE model to measure the AC characteristics of this circuit made some simplifications. The low power outputs have a negligible effect on the AC characteristics of the control loop, and are not included in the SPICE model. The SPICE model schematic is shown in Fig. 4.73. The control loop was effectively opened for the open-loop test by injecting a voltage source directly into the FB/OCP pin. This voltage was adjusted to provide an output voltage of approximately 102 V. For the closed-loop test, this external voltage source was not used. In the SPICE model, when the closed-loop Bode plot was measured, L1 was increased to 1 H and C3 was increased to 1 F. Measurements on the breadboard configuration were made at several output capacitor values. The results are shown in Fig. 4.74. The SPICE model was simulated at Vin = 110 V DC (85 volts AC), with the


109

R Breadboard Bode plots (Data provided courtesy of Allegro ).

Figure 4.74

130.0

40.00

110.0

20.00

90.00

Gain in dB (Volts)

Phase in Deg

200 µF output capacitor. The results of the SPICE simulation are shown in Fig. 4.75. From the results of Figs. 4.74 and 4.75, it is observed that the phase margin is 78◦ in the breadboard plot, against 79.6◦ degrees in the IsSpice plot. The crossover in the breadboard plot is 800 kHz, against

0

70.00

−20.00

50.00

−40.00

2

1

200

500

1K

2K

5K

10K

20K

50K

FREQUENCY in Hz

Figure 4.75

µF).

IsSpice Bode plot results (Vin = 110 V DC [85V AC], Cout = 200

110

Chapter Four

Full load Half load

Half load Full load Vdc

Figure 4.76

Breadboard modulation gain Bode plot.

783 kHz in the IsSpice plot. The general shapes of the curves are also very similar. The modulation gain of the test circuit was also measured. The modulation gain is the gain from the output of the opto-coupler to the output of the STR-F6524 average mode model. The breadboard results are shown in Fig. 4.76, and the IsSpice results are shown in Fig. 4.77. Output impedance was measured on both the breadboard and the IsSpice models. To simulate the output impedance, voltage source V4 was changed to AC 1 and the current source on the output was changed to AC 1. The breadboard measurements are shown in Fig. 4.78, while the IsSpice results are shown in Fig. 4.79. The simulation results from Micro-Cap and PSpice for the control loop characteristics of the quasi-resonant converter are shown in Figure 4.80 and 4.81, respectively.


PSpice v 10.5 0.38

Micro-Cap v8.0 0.32

Advantages: Reduced MOSFET switching losses, reduced EMI Disadvantages: Added circuit complexity, increased cost from additional components File names: STR6500 (IsSpice), str 2 (PSpice), str 3 (Micro-Cap)


111

2 15.00

Open Loop Gain in dB (Volts)

150.0

Phase in Deg

30.00

−90.00

−210.0

5.000

−5.000

−15.00

1

−25.00

−330.0

200

500

1K

2K

5K

Frequency in Hz Figure 4.77

IsSpice modulation gain Bode plot.

VIN = 120 VDC RLOAD = 222X LOOP OVER RIDE VO = 102V

100x

10x

1x

10.0 X

Figure 4.78

Breadboard open-loop output impedance.

10K

20K

50K

112

Chapter Four

Open Loop Output Z in dB (Ohms)

15.00

5.000

−5.000

−15.00 1

−25.00 200

500

1K

2K

5K

10K

20K

50K

Frequency in Hz Figure 4.79

IsSpice open-loop output impedance.

Discontinuous Flyback Converter Recently there has been growing interest in power factor correction circuitry. Power factor, which is defined as the ratio of the apparent required power to the actual true power, ultimately affects the circuit’s efficiency, thus varying the cost of electricity. It seems that almost all AC-powered equipment now require some form of active power factor correction in order to operate efficiently. Active power factor correction utilizes electronics to force the input current to look like a

Figure 4.80

Micro-Cap Bode plot results.


Figure 4.81

113

PSpice Bode plot results.

reflection of the input voltage, thus resulting in high power factor greater than 0.98. PF =

watts volts × amperes

Traditional power factor correction designs utilize a boost topology to accomplish the input power factor correction (PFC) function. The boost topology results in a nonisolated high voltage (approximately 400 V) DC output. This high voltage output powers a DC/DC converter, which provides the required output voltage(s) and input to output isolation. Many new integrated circuits are being developed for the purpose of PFC control. These new controllers include some that incorporate both the PFC controller and a DC-DC controller within a single chip, while others offer critical mode (also called transition mode) control. The critical conduction mode eases the reverse recovery stress that is seen by the boost diode. The boost topology offers several benefits, primarily a very high operating efficiency. Since the boost converter only has to switch the difference between the input voltage and the output voltage, this topology generally results in small magnetic elements and efficiencies above 95%, with the voltage being somewhat proportional to the input voltage. The boost topology also has some negatives, which include the inability to short circuit protect the boost stage and the high stresses in the boost diode, resulting from very high dV/dT at a high applied voltage during the reverse recovery period. The boost topology also exhibits a large inrush current unless an inrush limiter circuit is included, which adds to

114

Chapter Four

Figure 4.82

Actual schematic of the two-phase discontinuous flyback converter.

the complexity of the design. The boost topology also generally requires a DC/DC converter, which in turn requires the power to be switched twice and pushes up the parts count because of the two stages. In many applications it is preferable to perform PFC and isolation within a single converter stage. This is presently common in low-power requirements up to about 40 W using SEPIC and discontinuous conduction mode flyback topologies. The discontinuous mode flyback converter is especially well suited to the task, since it has a wide dynamic operating range also providing input-output isolation while maintaining the simplest topology. In addition the input can be made to look resistive if both the on time and the frequency are fixed. The downside of the flyback converter is that it is best suited to lower power requirements.

X3 XFMR RATI O = .1 5

X4 KBPC80 8

L3 1m

+

8 7

C7 .47u

Y9 V1

3

32

R3 1m

IN

L1 B 10 0u

Tran Gene rators = SIN -

19

2

IV4 V4

IV3 V3 1

vout

C2 25 00u

D2 40 EPS 08 13

C1 250 0u 14

10

V1 0

R10 4.7 5

6

R4 20 m

X1 IRFBC30

V9

Figure 4.83

V6

11

SPICE model of a single phase discontinuous flyback converter.

R5 20m

R2 7.5


R9 1GOhms

1 V1 VOFF = 0V VAMPL = 163V FR EQ = 400Hz

3 1 U3 MP58310

0 0

0

3

U1 2

2

1 2

C10 0.47uF

R8

In+ Out+ In- Out-

C7 0.47uF

3 4

L1 80uH

1mOhms

I

KBPC808

R1 10kOhms

V2 4.7Ohms

0

+

+

-

-

0

I

D4

V I

2 RATIO = 0.25

VH = 0.1V VT = 3V

0

40EPS08

0Vdc V4

0

0

C9 5000uF IC = 28

XFMR TX2

1

R5 3.9Ohms

R4 5mOhms

L2 80uH

IC = 9 C8 15uF

0

SWhy st e S1

R6 V1 = 0V V2 = 5V TD = 0s TR = .1us TF = .1us PW = 3.5us PER = 10us

D5

R2 3kOhms

XFMR TX1

1

0

1N4004RL

115

SWhy st e S2

R7 V1 = 0V V2 = 5V TD = 5us TR = .1us TF = .1us PW = 3.5us PER = 10us

V3 4.7Ohms

+

+

-

-

D3

RATIO = 0.25

VH = 0.1V VT = 3V

0

0

2 40EPS08

0

0 0 XFMR TX3

MUR 120RL D2

R3 100Ohms

RATIO = 0.5

0

0

Figure 4.84

PSpice model of a two phase voltage-mode flyback converter.

The peak input current of the discontinuous flyback converter, with a fixed duty cycle and fixed frequency, is defined by Ipk =

Vin ton Lpri

Measured bench response of the two-phase voltage-mode flyback converter showing the input voltage (upper trace 100V/div) and the input current (lower trace 2A/div).

Figure 4.85

116

Chapter Four

And the average current is related to the peak current as Iavg =

Ipk × Duty 2

By substitution, Iavg =

1 Vin ton × Duty 2 Lpri

If Lpri , ton , and duty are all fixed, then the average input current is proportional to the input voltage, resulting in an ideal power factor of unity. An example of the flyback power factor corrector is shown in Fig. 4.82. The design utilized a National Semiconductor LM5033 100 V pushpull voltage mode PWM controller. This controller was selected for several reasons. It has low initial operating current and up to 100 V input. It also provides high current output drivers and a wide operating temperature range. A final benefit is that it is designed for applications using optically coupled feedback. A single-phase version is shown in Figure 4.83.

1

30.5

15.0

7.22

v(vout)

2

iy9

3

i(r1)

4

iv3

160 3

29.5 s O u t p 1 u t P V 28.5 l o o l t t a g e i n 27.5 v o l t

26.5

5.00 s I n p u t C u -5.00 r r e n t i n a -15.0 m p e r e

7.02 s O u t p u t C 6.82 u r r e n t i n 6.62 a m p e r e

-25.0

6.42

120 s S e c o n d a 80.0 r y C u r r e n 40.0 t i n a m p e 0 r

2

1

4

e

500u

1.50m

2.50m time in seconds

3.50m

4.50m

Figure 4.86 IsSpice flyback converter waveforms (top, output voltage, input current, output current; bottom, secondary current).


TABLE 4.4

117

The Final Converter Performance Numbers Using PQ2620 Transformers Measured two-phase voltagemode flyback results

Calculated two-phase voltagemode flyback results

87.4% 1.03% 0.997

86.9% 1.03 0.997

Efficiency Distortion Power factor

The SPICE implementation for the two-phase version is shown in Fig. 4.84. It utilizes two discontinuous-mode flyback stages, operating 180◦ apart to provide 200 W of active power factor corrected power. This topology offers a significant ripple current reduction in the output capacitor, high efficiency, and reasonable cost. The four-phase solution might be more attractive at higher power levels, and there are threeand four-phase buck controllers available, but such a design would probably be overly complex for the 200 W power level. Table 4.4. shows that the final converter performance numbers using PQ2620 transformers are in excellent agreement with SPICE simulation data produced by PSpice.


PSpice v 10.5 33.31

File names: 2 phase flyback pfc (IsSpice), 2 phase flyback pfc (PSpice)

28.75V 28.13V SEL> 27.00V V(C9:1) 4.0A

0 -4.0A I(V5) 7.250A 7.125A -I(R5) 40A 30A 20A 10A 0 0

0.5ms

1.0ms

1.5ms

2.0ms

2.5ms

3.0ms

3.5ms

4.0ms

4.5ms

5.0ms

I(V4) Time

Figure 4.87 PSpice flyback converter waveforms (top, output voltage, input current, output current; bottom, secondary current).

118

Chapter Four

Bibliography Linear Technology. 1990. Linear Databook. Linear Technology. 1990. Linear Applications Handbook (Vol. I). Mimms, Forrest M. III. 1983. Getting Started in Electronics. National Semiconductor. 1993. Power IC’s Databook. Parker, Sybil, ed. 1984. Concise Encyclopedia of Science and Technology. New York: McGraw-Hill. Sandler, Steven M. 1996. SMPS Simulation with SPICE. New York: McGraw-Hill. Van Valkenburg, M.E. 1982. Analog Filter Design. New York: Harcort Brace Jovanovich College Publishers. Steven M. Sandler, Charles Hymowitz and Harold Eicher. 2006. Optimizing single-stage power factor correction. Power Electronics Technology Magazine, March, pp. 14–22.

Chapter

5 Electronic Load Circuits

Power conversion circuits can be designed to provide large amounts of output power. In order to test these high power output circuits, a load must be created that can safely dissipate the maximum power of the power converter. There are two ways to dissipate this power. Using resistors with high power rating is a typical solution. However, by definition, these resistors are large and bulky. If the designer wishes to test the power converter at different loads, more resistors must be purchased. When the power dissipation required is very large (>200 W), power resistors used to dissipate this load can become unwieldy. The second alternative is an electronic load. This device is a circuit that has a controllable switch (typically a Darlington configured pair of bipolar transistors or a MOSFET) that can be modulated to conduct any level of current the user desires. An example of an electronic load circuit is presented in this chapter. The electronic load will be constructed piece by piece and tested separately. When all the pieces are constructed and simulated, the whole sum of the electronic load can be assembled and tested as a unit.

Power Section of an Electronic Load The power section in this electronic load will be a N-channel power MOSFET. This design uses an IRF250, manufactured by International R . If a substitute part is used, pick a MOSFET that has the Rectifier power, drain-to-source voltage, and current rating required for your range, and try to minimize drain-to-source on resistance (RDSon). The schematic of the power MOSFET and drive circuitry is shown in Fig. 5.1. 119


120

Chapter Five

D20 DN4148

D22 DN4148 32

D21 DN4148 2

12

R8 100K 7

18

9

C1 470P

R7 1K

Q1 IRF250

14

Q4 QN2907A

D19 DN4148

R4 22

4

5

V(5) VCC

+ Load

1

VCC

R9 1K 13

R11 10K

VEE

3

8

0-5 Volt Current Select Voltage

V(8) VEE

X2 OP27A

C2 .001U

R1 .1 16

- Load

17

R12 10K R5 1K 11

V(8) VEE

X7 OP27A 15

VEE VCC

6

R10 10K

V(5) VCC

R13 10K

Figure 5.1

Schematic of electronic load power stage.

Breadboard tip

Although it is rarely necessary to simulate bypass capacitors in SPICE, breadboard circuits certainly need them! Thus, 0.01 µF capacitors from VCC and VEE to ground may be necessary to extract full performance from this circuit. The supply for the operational amplifier should be greater than +10 V (the breadboard in this example used +15 V). Also, if high currents are being supplied by the electronic load, make sure that the MOSFET is heat sunk or air cooled, and also make sure that the 0.1 sense resistor has a power rating appropriate to the current through it.

The connections for the output power supply under test are shown in Fig. 5.1 as + Load and − Load. The load current passes through the 0.1 sense resistor (R1) and is sensed by an operational amplifier (X7) operating as a differential amplifier (R11, R12, R10, R13). The differential amplifier creates a voltage representation of the current, which is sensed by the inverting terminal of another operational amplifier (X2 via R5). This signal is compared to a 0 V to 5 V reference voltage corresponding to 0 A to 5 A of current (sensed by the noninverting terminal of X2). An RC filter is used to filter noise spikes on the reference voltage (R9 and C2). The output of X2 provides gate voltage to the power

Electronic Load Circuits

121

MOSFET (Q1). R4 is a gate resistor used to limit the current in the gate and to avoid any self-oscillations of the MOSFET because of noise. Components R7 and C1 provide compensation for the control loop. One nice bonus feature of this circuit is provided by the 1N4148 diodes (D19–D22) and the 2N2907A PNP transistor (Q4). This circuit serves to limit the inrush current (and subsequent overshoot) of the output power supply under test when the electronic load is first activated. When there is no voltage on the output load, the control op-amp is usually railed high. The diode circuit clamps this output at a voltage just beneath the turn-on of the MOSFET (close to 2.4 V) in order to prevent this occurrence. When the power supply under test is connected (and exceeds the 2.4 V clamp level), the regulation swing of the op-amp’s output is much less than if the op-amp had been railed, allowing for a much faster response and a controlled turn-on. The SPICE transient model for this circuit is shown in Fig. 5.2. Note the additional 10 m resistor (R14) that exists in the SPICE model but

32

2

5

V2 15

7 22

9

V3 15

C1 470P

R7 1K

14

R4 22

4

8

1 VCC

R9 1K 3

13

R11 10K

VEE

R1 .1 16

C2 .001U 17

R12 10K R5 1K 11

15 VEE VCC

6

R10 10K R14 10M

R13 10K

Figure 5.2

1

R8 100K

V(22) VOUT

SPICE schematic of electronic load power stage (transient).

122

Chapter Five

D20 DN4148

D21 DN4148

D22 DN4148 32

2

5 1

R8 100K

V2 15

7 22

D19 DN4148 9

V3 15

C1 470P

R7 1K

8

14

X8 IRF250 VLOAD 6.6

R4 22

4

X2 OP27A

1

VCC

R9 1K 13

V4 .100;PUL

R11 10K

VEE

3

R1 .1 16

C2 .001U 17

R12 10K R5 1K 18

X7 OP27A

LOL 10

15 VEE

11 VCC

COL 10

6

R10 10K R14 10M

19

VOL AC V(11) LOOP

Figure 5.3

R13 10K

SPICE schematic of electronic load power stage (AC).

not our schematic. This is inserted in order to partially represent the characteristics of the cabling. There can be an inductive part to this as well; however, it is important to note that the cabling will have an effect on the slew rate of the current regulation. The SPICE small-signal AC analysis model is shown in Fig. 5.3. Three measurements of the breadboard were taken in order to correlate to the SPICE results. Figure 5.4a is a plot of the current regulator’s turn-on, Fig. 5.5a is a plot of the load current response to a stepped reference voltage, and Fig. 5.6a is a plot of the current regulator loop. The IsSpice results of these measurements are shown in Figs. 5.4b, 5.5b, and 5.6b, respectively. Equivalent models were used from PSpice and Micro-Cap. The results are shown in Figs. 5.7 and 5.8. Note that the IRF150 was used in the PSpice simulations. Examining the results of the SPICE simulations, it is noted all of the simulations show a slight current charging at the beginning of the


123

Breadboard turn-on plot (top, current 100 mA/Div; bottom, drain voltage of FET 10 V/Div).

90.00

400.0M

70.00

200.0M

50.00

Current (V1=1A) In Volts

VOUT In Volts

Figure 5.4a

1 0

30.00

−200.0M

10.000

−400.0M 2

10.000U

30.00U

50.00U

TIME in Secs Figure 5.4b

Turn-on results: output voltage and current.

70.00U

90.00U

124

Chapter Five

Figure 5.5a Breadboard step response (bottom, current 100 mA/Div top, select voltage step).

800.0M

200.0M

1

400.0M

0 Current (1V=1A) in Volts

VIN in Volts

600.0M

200.0M

−200.0M

−400.0M

2 0

−600.0M

1.000M

3.000M

5.000M

TIME in Secs

Figure 5.5b

Current step response.

7.000M

9.000M


125

1-22-98 Loading Iup = 100 µF VOUT = 6.6v

OdB

Odeg

Breadboard current regulator Bode plot.

420.0

40.00

300.0

20.00

180.0

Gain in dB (Volts)

Phase in Deg

Figure 5.6a

0 1 2

60.00

−20.00

−60.00

−40.00

1K

10K

FREQUENCY in Hz

Figure 5.6b

Current loop Bode plot.

100K

126

Chapter Five

Figure 5.7a

Micro-Cap turn-on plot.

turn-on plot. This charging is due to the drain-to-source capacitance of the MOSFET model used in the simulation. Since all the models are slightly different from one another, the results are not unexpected. Also, as a result of the differences in the MOSFET models, the distribution of the Bode plots is also different. A summary of the phase margin and the crossover frequency of each of the simulators and the breadboard is shown in Table 5.1.

Figure 5.7b

Micro-Cap current step response.


Figure 5.7c

Micro-Cap current loop Bode plot.

Figure 5.8a

PSpice turn-on plot.

127

128

Chapter Five

Figure 5.8b

PSpice current step response.

Figure 5.8c

PSpice current loop Bode plot.

TABLE 5.1

Summary of Bode Plot Results

PSpice Micro-Cap IsSpice Breadboard

Phase margin (◦ )

Crossover (kHz)

86.0 84.0 100.4 86.0

49.29 44.73 93.70 139.00


129

The results in Table 5.1 suggest that the loop characteristics are heavily dependent on the MOSFET characteristics, which were not modeled as accurately as they could be by the available FET models. Run time summary (s) IsSpice v 8.11 0.5, 1.483, 0.25

PSpice v 10.5 0.72, 2.45, 0.41

Micro-Cap v8.0 0.515, 3.266, 0.281

Advantages: No current overshoot at turn-on, good loop characteristics Disadvantages: Loop characteristics heavily dependent on MOSFET selection File names: fetload, fetload2, fetload3 (IsSpice); fload, fload2, fload3 (PSpice); mc load, mc load2, mcload3 (Micro-Cap)

Positive DC to Negative DC Comparator Converter One inconvenience associated with using operational amplifiers is the dual positive and negative power supplies that are frequently required. For convenience, and to limit the power source of our electronic load box to one power supply, we will include the following circuit in our electronic load. The circuit takes a 15 V DC signal and converts it to a –11 V DC signal. The schematic for this circuit is shown in Fig. 5.9. Note that the values shown are actual lab values of circuit. Standard resistor values are shown in parentheses. The converter is powered by an external +15 V DC supply. This voltage is divided down by R1 and R2 to form a 7.5 V reference. The 7.5 V on the noninverting pin and the low voltage on the inverting pin cause the output to go to an open collector state (which is tied to the same +15 V source through a 1K pull-up resistor). This charges capacitor C1 through resistor R4. When the voltage on C1 exceeds the 7.5 V reference, the output switches to a low state, adding the hysteresis resistor R5 into the divider. The new reference voltage is now 5 V. Capacitor C1 now discharges through R4 and an oscillator is created. Capacitors C2 and C3, along with diodes D1 and D2, use the square wave generated by the oscillator and rectify it to a DC negative voltage. The breadboard plots of the waveforms at the inverting pin and the output pin of LM111 are shown in Fig. 5.10. The DC output voltage of the breadboard measured –13.68 V. The Micro-Cap waveforms are shown in Fig. 5.11. The Micro-Cap DC output voltage of the circuit measured –12.393 V. The positive DC to negative DC comparator converter was also simulated using PSpice and IsSpice. The inverting pin and output pin waveforms of LM111 are shown in Figs. 5.12 and 5.13. A summary of the DC output voltages of all three simulators compared to the breadboard results is given in Table 5.2.

130

Chapter Five

R6 980 (1K)

V(8) COMP

R5 46.4K (47K) (47K) R1 46.3K 4

V1 15

2

R2 46.2K (47K)

Figure 5.10

8 5

C1 129P (100p)

Figure 5.9

C2 .486U

V(6) OUT

D1 DN4002

VEE

V(5) NEG

VCC

X6 LM111T

1

6

(0.47u) R4 17.5K (18K)

C3 .416U D2 DN4002

Schematic of DC positive to DC negative converter.

Breadboard waveforms (top, pin 7 of LM111; bottom, pin 3 of LM111).

(0.47u)


Figure 5.11

Micro-Cap waveforms (top, pin 7 of LM111; bottom, pin 3 of LM111).

Figure 5.12

PSpice waveforms (top, pin 7 of LM111; bottom, pin 3 of LM111).

131

Chapter Five

40.00

20.00

30.00

10.000

20.00

COMP in Volts

NEG in Volts

132

1

0

−10.000

10.000

2 −20.00

0

991.0U

993.0U

995.0U

997.0U

999.0U

TIME in Secs

IsSpice waveforms (top, pin 7 of LM111; bottom, pin 3 of LM111).

Figure 5.13

SPICE tip

Note that in Table 5.2, the IsSpice simulator gave us the wrong DC output voltage! Examining the model for LM111 in IsSpice reveals that the output comparator is limited internally to 10 V. IsSpice has five models for the LM111 family of devices. None of these models worked correctly with this circuit. Also, none of these models used the typical propagation delay of the LM111 family as a parameter in the model. This circuit is heavily affected by variations in the propagation delay. You can see this effect if you examine the results of Figs. 5.10 and 5.11. The capacitor voltage continues to charge past what should have been the reference voltage. This creates an error term in the final negative output voltage R of the circuit. The Texas Instruments data book (1992) does not specify a minimum propagation delay, so theoretically, the propagation delay of the Intusoft models are not incorrect; however, they are probably not realistic either. The PSpice model for LM111 also does not work properly

TABLE 5.2

DC Output Comparison Summary DC output voltage of circuit (V)

PSpice Micro-Cap IsSpice Breadboard

–11.000 –12.393 –10.000 –13.680


133

and appears to be clamped at 9 V. Only the Micro-Cap model was close to the breadboard results.


PSpice v 10.5 3.59


Advantages: Low parts count, only requires one lab supply to drive op-amps Disadvantages: Negative output highly dependent on propagation delay of LM111, negative drive current capability limited by LM111 File names: pos2neg (IsSpice), pos2negp (PSpice), pos2negm (Micro-Cap)

Built-in Variable Electronic Load Adjustment The final piece in the MOSFET electronic load puzzle is a method of adjusting the current limit. A simplistic yet flexible circuit to accomplish this is shown in Fig. 5.14. This circuit gives the user the option to use a DC current or to use a pulsed current as a load (useful for checking load-switching transients of power supplies). The 15 V input signal is dropped to 10 V by a 5 V zener in series. Switch A selects between the simple potentiometer voltage divider circuit (limited to 5 V maximum by the divider resistors) R10

R12 4.7K 1

100k POT

R6 1K

V(3) COMP

7

R5 47K

Analog Switch (Used MC14066)

Switch A

D3 ZN4733

R1 47K 10

VCC 15

6

4

V(8) OUT

2

R2 47K

VEE

V(5) NEG

3 5

C1 .047U

8

VCC

R4 100K

X6 LM111T

R7 R9 1K 9

100k POT R8 1K

Figure 5.14

Schematic of electronic load reference and pulse load.

134

Chapter Five

R9 4.64K

R6 1K

V(3) COMP

R5 47K 1

X8 PSW1 R1 47K 4

V(8) OUT

2

V1 10

R2 47K

VEE

V(5) NEG

3 5

C1 .047U

8

VCC

X6 LM111T

R4 100K

R7 100K

R8 4.6K

Figure 5.15

Schematic of electronic load reference and pulse load.

and the pulse load. The pulse is generated by a hysteresis oscillator, based on a LM111 comparator. Capacitor C1 and resistor R4 are increased in order to slow the pulse down to 150 Hz. An analog switch is used to switch between the lower voltage level (set by R7–R9) and the upper voltage level (set by R10 and R12). Potentiometers R7 and R10 set the lower and upper voltage levels from 0 to 5 V. The equivalent simulation schematic is shown in Fig. 5.15. The breadboard pulse load waveform (from 300 mA to 5 A) is shown in Fig. 5.16. The IsSpice simulation results are shown in Fig. 5.17. MicroCap and PSpice results are shown in Figs. 5.18 and 5.19. In Figs. 5.15, 5.16, 5.17, and 5.19, the top waveform is the output of the comparator and the bottom waveform is the output of the analog switch (which would then be connected to the electronic load power circuit, such as that shown earlier in this chapter.) SPICE tip

The three simulators have slightly different switch models. The IsSpice model used is the PSW1 switch. This is different from the builtin switch model, which is basically the Berkeley SPICE switch model with hysteresis. The parameters passed are VON = 7 V, RON = 100 , VOFF = 2 V, and ROFF = 100 M. The PSpice simulation used a model called Sbreak. Like the PSW1 and the Micro-Cap switch models, this switch transitions smoothly between the on and off states and has no hysteresis.


Electronic load reference pulse output waveforms.

Figure 5.16

15.00

9.000 2

−5.000

7.000

OUT in Volts

COMP in Volts

5.000

1

5.000

−15.00

3.000

−25.00

1.000

21.00M

23.00M

25.00M

27.00M

29.00M


IsSpice simulation results: reference pulse output waveforms.

135

136

Chapter Five

Figure 5.18

PSpice simulation results: reference pulse output waveforms.

Figure 5.19

Micro-Cap simulation results: reference pulse output waveforms.


137

The Micro-Cap simulation used the analog primitive Switch model. The parameters passed are VON = 7 V, RON = 100 , VOFF = 2 V, and ROFF = 100 M.

VOUT in Volts

800.0M

x 30.00 < 350.3M

400.0M

>

0 1 −400.0M

10.000

20.00

30.00

40.00

V4 in Volts x = 19.90 y = -684.3M

Figure 5.23

IsSpice results of safe operation region circuitry.

50.00

139

140

Chapter Five

1

0.8

0.6

Series1

0.4

0.2

0 5 Figure 5.24

15

25

35

45

55

Breadboard results of safe operation region circuitry.

For this load, a circuit was designed that allows the electronic load to take full advantage of the power transistor’s power rating. This circuit is shown in Fig. 5.21. The collector-emitter voltage is sensed through D3 and R12. The voltage signal is fed into the inverting terminal of op-amp X1 (UA741). This voltage is compared to a reference voltage, generated by a 10 V precision reference IC. At collector-emitter voltages of less than 10 V, the load is limited to 10 A. As the collector-emitter voltage increases, transistors Q1 and Q2 turn on and, utilizing nonlinear

Figure 5.25

Micro-Cap results of safe operation region circuitry.


Figure 5.26

141

PSpice results of safe operation region circuitry.

feedback, allow the limiter circuit to approximate the 110 V load. Above 50 V, a diode-coupled divider substantially increases the slope to limit the transistor within the Is/b portion of the safe operating region. If the collector-emitter voltage exceeds the limit set by this circuit, the electronic load is current limited by pulling the control pin to ground via diode. The data book current limit of the transistor used is shown in Fig. 5.22. The resulting power curve created by the IsSpice model is shown in Fig. 5.23, and the curve created by the breadboard is shown in Fig. 5.24. Micro-Cap and PSpice results are shown in Figs. 5.25 and 5.26, respectively.


PSpice v 10.5 0.89


Advantages: BJT transistors less expensive (typically) than MOSFET transistors Disadvantages: Extra circuitry required to create power limiting of transistors File names: load (IsSpice), ps load (PSpice), load mc (Micro-Cap)

Bibliography Motorola Inc. 1982. Motorola Power Data Book (3rd ed). Parker, Sybil, ed. 1984. Concise Encyclopedia of Science and Technology. New York: McGraw-Hill. Texas Instruments. 1992. Linear Circuits Data Book (Vol. 3). Van Valkenburg, M.E. 1982. Analog Filter Design. New York: Harcort Brace Jovanovich College Publishers.


Chapter

6 Instrumentation Circuits

Instrumentation circuits are unique. The wide definition of “instrumentation” suggests that these are circuits that are not central to the operation of the system, but are critical to the testing and implementation of that system. These circuits act as telemetry signals, allowing remote users to monitor the inner workings of the system without its disassembly. Other applications include internal test points, which provide the same function to the test technician who would like to monitor signals internal to the system without opening up the system or disrupting its operation. The wide variety of applications and circuits that fit under this category also suggest individual and unique obstacles to the proper operation and simulation of these circuits. This chapter will allow the designer to identify those obstacles and avoid them. 555 Timer The versatility of the 555 timer integrated circuit is shown time and again in the number of circuit requirements that can be satisfied with this IC. The original purpose of this IC was to provide a one-shot timer. A schematic for this circuit is shown in Fig. 6.1. When the pulse at V2 transitions low, the timer is started. Capacitor C1 begins to charge through resistor R2. During the charging time, the output of 555 is high. When the voltage at the threshold pin reaches 2/3 of the Vcc voltage (in this example, the Vcc is 15 V, so the trip point of the threshold pin is 10 V), the output transistions low. The V2 source uses a PULSE statement of the following syntax: PULSE 0 15 0 100N 100N 900U 1M 143


144

Chapter Six

R2 76K

3

V1 15 6

TRIG

VCC DISCHG

X2 UA555 V(4) OUT

4

1

THRES

OUT CTRL

5

RESET

V(1) RAMP C1 2140P

C2 .01U V(6) TRIGGER V2 PULSE

Figure 6.1

Schematic of a 555 one-shot timer circuit.

The above PULSE statement translates to a square-wave pulse with an amplitude ranging from 0 to 15 V, 100 ns rise and fall times, and a 1 ms period with a 90% duty cycle. Examining the results of Figs. 6.2 and 6.3, the operation of IC 555 is apparent. When the input (trigger) voltage transistions low, the clock function starts, and it ends 181 µs later (in this example). One other interesting waveform is the threshold pin voltage. This is shown in Fig. 6.4. When the input (trigger) voltage transitions low, the capacitor C1 begins to charge through R2 until its voltage is 2/3 the Vcc voltage. This circuit was also constructed in PSpice and Micro-Cap. The resulting waveforms are shown in Figs. 6.5 and 6.6.


PSpice v 10.5 4.13

Advantage: Low parts count Disadvantage: Limited accuracy File names: 555 1sht (IsSpice), 555 1sh2 (PSpice), 555 1sh3 (Micro-Cap)


Instrumentation Circuits

Breadboard input and output signal waveforms.

40.00

70.00

20.00

50.00

1

0

−20.00

Output in Volts

Trigger Input in Volts

Figure 6.2

30.00

10.000

x 2.082M < 5.001 x 1.900M < 5.000

−40.00

> 2

>

−10.000

2.150M

2.650M

3.150M

Time in Secs x = 181.3U y = 1.458M

Figure 6.3

IsSpice input and output signal waveforms.

3.650M

4.150M

145

Chapter Six

69.87

40.00

49.87

20.00

29.87

9.874

Trigger Input in Volts

Capacitor Voltage in Volts

146

1

0

−20.00 2

−10.13

−40.00

2.150M

2.650M

3.150M

Time in Secs Figure 6.4

Figure 6.5a

IsSpice input and threshold signal waveforms.

Micro-Cap input and output waveforms.

3.650M

4.150M


Figure 6.5b

Micro-Cap input and threshold waveforms.

Figure 6.6a

PSpice input and output waveforms.

147

148

Chapter Six

Figure 6.6b

PSpice input and trigger waveforms.

555 Missing-Pulse Detector With a few components, the 555 timer can be configured to detect missing pulses in a data stream. The schematic for this type of configuration is shown in Fig. 6.7. This circuit is actually a clever use of the timer characteristic of the 555 as long as the pulse spacing is less than the timing interval generated by R2 and C1. Therefore, this circuit not only detects missing pulses, but variations in duty cycle, variations in frequency, and even a terminated pulse stream. Figure 6.8 shows the breadboard in detection

VCC 5

R3 100K

R2 1K

V(1) TRIG 1

TRIG

VCC DISCHG

X2 UA555

INPUT 4

V(5) DISCH

V(1) TRIG

THRES

5

CTRL

3

C1 .1U

OUT

Q1 QN2907A

RESET 2

V(2) VC

C2 .01U

V(4) OUT

Figure 6.7

555 configured as a missing pulse detection circuit.


Figure 6.8

149

Normal operation, no pulses skipped.

mode, with the output pulse high (no missing pulses detected) and the input pulse train on top. Figure 6.9 shows the result when the input pulse (top) terminates. Looking at Fig. 6.10, we note that removing the pulse train (upper trace) triggers the detection pulses (lower trace). The SPICE models were tested slightly differently than the breadboard. The SPICE test schematic is shown in Fig. 6.11. Voltage source V2 uses the command “PULSE 0 5 0 100N 100N 80U 100U,” while voltage source V3 uses the command “PULSE 0 7 500U 100N 100N 200U 1.” The resulting input and output waveforms are shown in Fig. 6.12a. The threshold waveform (V(5)) was also measured; it is shown in Fig. 6.12b. The results of the PSpice and Micro-Cap simulations of this circuit are shown in Figs. 6.13 and 6.14, respectively.


PSpice v 10.5 5.41


Advantages: Low parts count Disadvantages: Not a true missing pulse detection circuit, actually a timer circuit File names: 555 mpd (IsSpice), 555 mpd2 (PSpice), 555 mpd3 (Micro-Cap)

150

Chapter Six

Figure 6.9

Figure 6.10

Pulse stream terminated, detection pulse triggered.

Frequency decreased, detection pulse triggered.


VCC 5

R3 100K

R2 1K

V(1) TRIG

R4 1K 1

8

V2 PULSE

TRIG

VCC DISCHG

X2 UA555

D1 DN4148

4

V(1) TRIG

THRES

5

CTRL RESET

3

C1 .1U

OUT

Q1 QN2907A

7

R5 1K

V(5) DISCH

2

V(1) INPUT

V(2) VC

C2 .01U

V(4) OUT

6

V3 PULSE

SPICE test schematic.

16.00

6.000

12.00

2.000

8.000

1

INPUT in Volts

OUT in Volts

Figure 6.11

−2.000

2 4.000

−6.000

0

−10.000

100.00U

300.0U

500.0U

TIME in Secs

Figure 6.12a

IsSpice input and output waveforms.

700.0U

900.0U

151

Chapter Six

8.000

6.000

6.000

2.000

4.000

1

INPUT in Volts

DISCH in Volts

152

−2.000

2.000

−6.000

0

−10.000

2

100.00U

300.0U

500.0U

TIME in Secs

Figure 6.12b

IsSpice input and threshold waveforms.

Figure 6.13a


700.0U

900.0U


Figure 6.13b

PSpice input and threshold waveforms.

Figure 6.14a


153

154

Chapter Six

Figure 6.14b

Micro-Cap input and threshold waveforms.

Operational Amplifier Adder The original mission of the operational amplifier integrated circuit is to perform operations (just as the name suggests). The op-amp is versatile enough to perform integration, differentiation, summing, subtracting, multiplication, and a multitude of other mathematical operations. Although the functions performed by the circuits may be complex, the circuits themselves are usually relatively easy to build and easy to design. One example of such a circuit is the operational amplifier adder circuit, shown in Fig. 6.15. The signal at input A is summed with the signal at input B. This circuit has a variety of uses in communications circuitry. R2 100K

VCC 15 X1 OPAMP

R1 100K

V(6) SIN_IN

2

V(4) OUT

1 VCC 4

R3 100K 5

6

VEE 3

VEE -15 V(7) PULSE_IN

R4 100K 7

Figure 6.15

Schematic of an op-amp adder circuit.


155

R2 100K

VCC 15

R1 100K

V(6) SIN_IN

2

V(4) OUT

1 VCC 4

R3 100K 6

5

VEE 3

VEE -15

V3 SIN

V(7) PULSE_IN

R4 100K 7

V4 PULSE

Figure 6.16

SPICE equivalent schematic of an op-amp adder circuit.

Our equivalent SPICE model of this circuit is shown in Fig. 6.16, where the inputs have been replaced by voltage sources. The breadboard was constructed and two sets of waveforms were measured. The first two waveforms are the two input signals. The breadboard results are shown in Fig. 6.17, with the top waveform being a ±1 V signal at 1 kHz and the bottom waveform being a 0 V to 1 V pulsed square wave with a 50% duty cycle at 10 kHz. The breadboard result of the addition of these two waveforms is shown in Fig. 6.18. This circuit was also constructed in IsSpice, PSpice, and Micro-Cap. The resulting waveforms are shown in Figs. 6.19 to 6.21. SPICE tip

The IsSpice model used the Intusoft created generic op-amp model. The passed parameters used were VOS=1U, IOS=1N, IBIAS=1N, FT=5MEG, DVDT=5MEG, GAIN=100K. The Micro-Cap and PSpice simulators used the UA741 model for the op-amp. The breadboard used an LM324. As the results show, high performance is not required from the op-amp to get acceptable results from this circuit. Run time summary (s)


PSpice v 10.5 2.22

Advantages: Low parts count Disadvantages: File names: add (IsSpice), add2 (PSpice), add3 (Micro-Cap)


156

Chapter Six

Figure 6.17

Breadboard input signal waveforms.

Figure 6.18

Breadboard output signal result.

7.000

2.000

5.000

0

3.000

SIN_IN in Volts

PULSE_IN in Volts


1

-2.000

1.000

-4.000

-1.000

-6.000

2

1.600M

1.800M

2.000M

2.200M

2.400M

TIME in Secs

Figure 6.19a

IsSpice input waveforms.

2.000

OUT in Volts

1.000

1

0

-1.000

-2.000

1.200M

1.600M

2.000M

TIME in Secs

Figure 6.19b

IsSpice output waveform result.

2.400M

2.800M

157

158

Chapter Six

Figure 6.20a

Micro-Cap input waveforms.

Figure 6.20b

Micro-Cap output results.


Figure 6.21a

PSpice input waveforms.

Figure 6.21b

PSpice output result.

159

160

Chapter Six

V(2) VC

VCC 9

R2 22K

R7 1K

11

2.01M 747M

V(4) IN

9

D1 DN4148 R1 1K 11.1U

0

X2 UA741T

VIN SIN

55.1M R10 2.2

2 5

4

Q5 QN2222A

12

V(2) VC

9.00

VCC

6

17.8M

VEE

V(11) OUT

D2 DN4148

1

R9 2.2

-9.00 V(1) VE

R_LOAD 50

8

VEE -9

-51.0M

V(1) VE 7

-711M

Q7 QN2907A

R8 1K

V(1) VE

Figure 6.22

Schematic of the class AB amplifier circuit.

Class AB Amplifier A class AB amplifier is defined as an amplifier using a power stage that has output current flow for more than half, but less than all, of the input cycle (Gilbilisco 1994). One example of a class AB amplifier circuit is shown in Fig. 6.22. The voltage source VIN provides the input signal. Resistors R1 and R2 set the gain and bandwidth of the amplifier. Output transistors Q5 and Q6 provide sourcing and sinking current for the signal. Diodes D1 and D2 attempt to minimize the distortion created when the input signal passes through the region between where the NPN transistor (Q5) turns off and the PNP transistor (Q7) turns on (and vice versa). Resistors R9 and R10 limit the current drawn from Q5 and Q7. R7 and R8 set the quiescent current of Q5 and Q7. The load is modeled using a resistor (R LOAD). The net result of this circuitry is a power-boosted inverse output representation of the input signal, capable of driving low-impedance loads. Three different measurements were made in order to characterize the performance of this amplifier circuit and show the correlation of the breadboard results to the SPICE models. The three inputs and their resulting measurements are described in detail in Table 6.1. A 1 kHz sine wave was provided at the input, and the output result was measured. The breadboard results are shown in Fig. 6.23. The top trace is the output waveform. The bottom trace is the input waveform.


TABLE 6.1

161

Characteristic Measurements Made on Class AB Amplifier Circuit DC output voltage of circuit (V)

VIN SIN 0 10M 1K

Input is a 1 kHz sine wave with peak-to-peak amplitude of 200 mV

VIN PULSE -100M 100M 0 100N 100N 50U 100U

Square wave of 10 kHz at a 50% duty cycle used to measure transient loop response

VIN AC 1

AC simulation input to determine filter response (frequency analysis)

The IsSpice, PSpice, and Micro-Cap results are shown in Figs. 6.24, 6.25, and 6.26, respectively. The transient response of the amplifier was measured by using a 10 kHz square-wave input with a 50% duty cycle. The breadboard results are shown in Fig. 6.27. The bottom trace is the input square wave, while the top trace is the output result. The Micro-Cap, PSpice, and IsSpice results are shown in Figs. 6.28, 6.29, and 6.30, respectively. In order to measure the frequency response of the class AB amplifier, the input voltage source was changed to a small-signal AC stimulus source (AC 1). The breadboard results are shown in Fig. 6.31. The IsSpice, PSpice, and Micro-Cap results are shown in Figs. 6.32, 6.33, and 6.34, respectively.

Run time summary (s) IsSpice v 8.11

PSpice v 10.5

Micro-Cap v8.0

Advantages: Improved efficiency over class A type amplifiers, excellent drive capability Disadvantages: Output not an exact linear reproduction of the input waveform, continuous current drain, efficiency not as good as that of other amplifier types File names: Clas AB2 (IsSpice), Clas AB2 (PSpice), Clas AB3 (Micro-Cap)

Window Detector Another application of the versatile comparator IC is the window detector. The window detector monitors an important signal (usually DC) and changes state if the level does not stay within the voltage range set by the window comparator. The schematic for the window detector circuit is shown in Fig. 6.35. The input signal is modeled by the independent voltage source V IN. The power supplied to the LM111 components in the circuit is 10 V DC. The emitter outputs of the comparators are tied to VEE, which

162

Chapter Six

Breadboard results of sine-wave input.

3.000

700.0M

1.000

500.0M 2

-1.000

IN in Volts

OUT in Volts

Figure 6.23

-3.000

300.0M

100.0M 1

-5.000

-100.00M

11.00M

13.00M

15.00M

TIME in Secs

Figure 6.24

IsSpice results of sine-wave input.

17.00M

19.00M


Figure 6.25

PSpice result of sine-wave input.

Figure 6.26

Micro-Cap result of sine-wave input.

163

164

Chapter Six

Figure 6.27

Breadboard result of square-wave input .

Figure 6.28

Micro-Cap results of square-wave input.


PSpice results of square-wave input.

2.000

700.0M

0

500.0M

-2.000

IN in Volts

OUT in Volts

Figure 6.29

300.0M

2

-4.000

100.0M

1

-6.000

-100.00M

1.300M

1.400M

1.500M

1.600M

WFM.1 IN vs. TIME in Secs

Figure 6.30

IsSpice results of square-wave input.

1.700M

165

166

Chapter Six

Figure 6.31

Breadboard frequency response results.


32.00

26.00

x 34.97K < 23.84

20.00

> 1

14.00

8.000

100

1K

FREQUENCY in Hz Figure 6.32

IsSpice frequency response results.

10K


Figure 6.33

PSpice frequency response results.

Figure 6.34

Micro-Cap frequency response results.

167

168

Chapter Six

V(3) VC

R1 100 7

3

V1 10

D1 ZN4733

R2 1K V(10) OUT2

34

R6 6.8K

V(2) IN

10

R7 2.2K R5 4.7K X4 LM111T

R8 9.72K

4

6

VCC

Q1 QN2222A

VEE

2

V(3) VC

V_IN PULSE X5 LM111T 1

VCC VEE

R4 9.72K;10 5

R3 149.2K

Figure 6.35

Schematic of the window comparator circuit.

is tied to ground. The 10 V power is dropped to 5.1 V through resistor R1 (which sets the current through the zener at the test current of the device) and zener diode D1 (1N4733). This 5.1 V signal is fed into the noninverting terminal of the upper comparator through a 10K sense resistor (R8). This signal is also scaled down to 4.8 V by a resistor divider consisting of R3 and R4. The 4.8 V signal is fed into the inverting terminal of the lower comparator. Therefore, our upper and lower references are 5.1 V and 4.8 V, respectively. The open collector outputs of the comparators are connected to 5.1 V through the pull-up resistor R2. Table 6.2 shows the possible operating states of this circuit. Transistor Q1 and resistors R5 and R6 simply realize an inverting function to provide the output of the circuit. In many cases, comparators in their normal operating steady state will have a high output in order to

TABLE 6.2

Circuit Behavior of Window Comparator

Input voltage signal

Comparator output

2N2222A signal output

Vin < 4.8 V 4.8 V < Vin < 5.1 V Vin > 5.1 V

Pulled low to ∼100 mV Pulled high to 5.1 V Pulled low to ∼100 mV

Pulled high to 10 V Low signal (∼100 mV) Pulled high to 10 V


TABLE 6.3

169

Characteristic Measurements Made on Window Comparator Circuit

VIN PULSE 2 5 2.25M 1U 1U 2.75M 3M TRAN 1U 16M 6M 2U

Square wave from 2 to 5 V at 333 Hz with a 90% duty cycle

VIN PULSE 5 8 2M 1U 1U 275U 3M TRAN 1U 10M 0 2U

Square wave from 5 to 8 V at 333 Hz with a 10% duty cycle

VIN PULSE 4 8 0 4M 4M 1U 8M TRAN 1U 13M 3M 2U

Triangular waveform from 4 to 8 V at 125 Hz with a 50% duty cycle

minimize power dissipation. This circuit follows that tradition; however, it also provides for a logic high output to drive control circuitry (such as a latch). Three different measurements were made in order to characterize the performance of this window comparator circuit and show the correlation of the breadboard results to the SPICE models. The three inputs and their SPICE statements are described in detail in Table 6.3. The breadboard result of the comparator circuit when a 2 V to 5 V square wave is sensed is shown in Fig. 6.36. The IsSpice result is shown in Fig. 6.37, and the Micro-Cap result is shown in Fig. 6.38. Examining the results of Fig. 6.38, it is noted that there was no state change when the input signal transitioned between 2 V and 5 V. Upon further examination, the culprit was determined to be the Micro-Cap zener diode model 1N4733.

Figure 6.36

Breadboard results of 2 V to 5 V square-wave input.

170

Chapter Six

35.00

8.000

25.00

4.000

15.00

5.000

IN in Volts

OUT2 in Volts

1

0

-4.000 2

-5.000

-8.000

7.000M

9.000M

11.00M

13.00M


IsSpice results of 2 V to 5 V square-wave input.

Figure 6.38

Micro-Cap result of 2 V to 5 V square-wave input.

15.00M


171

R2 100 6

2

V1 0-12.1

Figure

D1 ZN4733

6.39

Breadboard

frequency

response

results.

The Microsemi® data sheet of the 1N4733A shows a nominal zener voltage of 5.1 V at a test current of 49 mA. The IsSpice model shows 5.101 V at 49 mA, while the Micro-Cap model shows 5.819 V at a current of 42 mA. With results such as these, the logical question is, are the models correct? In order to answer this question, the zener voltages versus zener currents were plotted for the Micro-Cap diode, IsSpice diode, and a lab diode. The test circuit is shown in Fig. 6.39. The lab diode used the Fig. 6.39 configuration, and zener current versus zener voltage was plotted. The graph in Fig. 6.40 shows the curves for the Micro-Cap 1N4733, IsSpice 1N4733, and 1N4733A models designed by AEi Systems. Examining the results of Fig. 6.40, it is noted that the measured data of the lab diode shows a knee at approximately 3.9 V. The

1N4733A Zener diode models 8 7 Zener Voltage

6

Vz (bb)

5

Vz(Mc)

4

Vz (Isp)

3

Vz (Aei)

2 1

1. 00 E -0 7 6. 00 E -0 7 1. 77 E -0 5 5. 24 E -0 4 1. 81 E -0 3 3. 71 E -0 3 1. 12 E -0 2 7. 67 E -0 2 1. 21 E -0 1

0

Zener Current Figure 6.40

1N4733 diode plots: zener current vs. zener voltage.

172

Chapter Six

Figure 6.41

Micro-Cap results of 2- to 5-V square-wave input.

zener voltage changes at a different rate above this point than below this point. In order to properly model the zener voltage at both of these regions, a subcircuit is required. The results of Fig. 6.40 clearly illustrate the advantages of using a subcircuit to model a zener diode. In order to allow the Micro-Cap SPICE model of the window comparator to run properly, the AEI zener diode subcircuit was used instead of the 1N4733 model (SPICE .MODEL statement) that ships with MicroCap. The 2 V to 5 V square wave was fed into the modified Micro-Cap model. The results are shown in Fig. 6.41. The breadboard, IsSpice, and Micro-Cap (with AEI diode model) results of a 5 V to 8 V square-wave input are shown in Figs. 6.42, 6.43, and 6.44, respectively. The breadboard, IsSpice, and Micro-Cap results of a triangular waveform of 4 V to 8 V are shown in Figs. 6.45, 6.46, and 6.47, respectively.


PSpice v 10.5 4.06


Advantages: Versatile and easily adjustable Disadvantages: Poor zener diode accuracy (5% initial tolerance) creates errors in trip points; other circuit variants more precise File names: Window (IsSpice), Window2 (PSpice), Window3 (Micro-Cap), 1N4733A.XLS (Excel)


Figure 6.42

Breadboard results of 5 V to 8 V square-wave input.

40.00

10.000

30.00

6.000

20.00

IN in Volts

OUT2 in Volts

1

2.000

10.000

-2.000

0

-6.000

2

1.000M

3.000M

5.000M

7.000M

TIME in Secs

Figure 6.43

IsSpice results of 5 V to 8 V square-wave input.

9.000M

173

174

Chapter Six

Figure 6.44

Micro-Cap results of 5 V to 8 V square-wave input.

Figure 6.45

Breadboard results of 4 V to 8 V triangle-wave input.


40.00

10.000

30.00

6.000

20.00

IN in Volts

OUT2 in Volts

1

2.000

10.000

-2.000

0

-6.000

2

4.000M

6.000M

8.000M

10.00M


IsSpice results of 4 V to 8 V triangle-wave input.

Figure 6.47

Micro-Cap results of 4 V to 8 V triangle-wave input.

12.00M

175

176

Chapter Six

V(5) IN

R2 9.81K

V(17) OUT

5

VIN SIN

V1 15 D6 DN4148

1 17 VCC 3 2

VEE

VREF 5

Figure 6.48

Voltage clamping circuit.

Voltage Clamp A voltage-clamping circuit is one that sets the positive or negative peaks of an AC waveform to a specific DC level. A common method of creating a clamping circuit is the use of a capacitor diode network, or a zener diode. However, the accuracy of a zener diode is dependent on the operating current and temperature. Operating a zener diode at lower than tested currents (“soft” region) creates unpredictability in the temperature coefficient and the zener voltage. The circuit shown in Fig. 6.48 is a precision clamp, which can be constructed with an operational amplifier, resistor, and a reference voltage. A 500 Hz sine waveform and a 500 Hz triangular waveform was used as an input signal in Figs. 6.49 to 6.56. Figures 6.57 to 6.60 show the clamping of a 5 kHz sine waveform. To reduce the switching spike, select an operational amplifier with a larger slew rate. The simulation below (Fig. 6.61 and Table 6.4) compares the output of UA741 to that of LM318. Resistance to Voltage The basic element of an ohm meter is a circuit that can take a resistance and convert it into a voltage. This is most simply realized by using a


TABLE 6.4

Simulation Results

Simulator

File name (5 kHz sine wave)

Measured data Micro-Cap PSpice IsSpice

NA Clmpmc Clmps Clmpis

8.000

3.000

6.000

1.000

Overshoot (V)

Run time (s)

1.8 1.38 1.4 1.06

NA 0.609 1.92 1.583

Measured clamping of 500 Hz triangular waveform.

5.000

OUT in Volts

IN in Volts

Figure 6.49

1 4.000

2 -1.000

2.000

-3.000

0 1.200M

2.200M

3.200M

4.200M

5.200M

TIME in Secs

Figure 6.50

177

IsSpice simulated clamping of 500 Hz triangular waveform.

178

Chapter Six

Figure 6.51

PSpice simulated clamping of 500 Hz triangular waveform.

Figure 6.52

Micro-Cap V simulated clamping of 500 Hz triangular waveform.


Measured clamping of 500 Hz sine waveform.

5.000

8.000

3.000

6.000

1.000

OUT in Volts

IN in Volts

Figure 6.53

1

4.000

2 -1.000

2.000

-3.000

0 1.942M

2.942M

3.942M

4.942M

5.942M

TIME in Secs

Figure 6.54

IsSpice simulated clamping of 500 Hz sine waveform.

179

180

Chapter Six

Figure 6.55

PSpice simulated clamping of 500 Hz sine waveform.

Figure 6.56

Micro-Cap V simulated clamping of 500 Hz sine waveform.


Figure 6.57

Measured clamping of 5 kHz sine waveform.

Figure 6.58

Micro-Cap V simulated clamping of 5 kHz sine waveform.

181

Chapter Six

5.000

8.000

3.000

6.000

1.000

OUT in Volts

IN in Volts

182

1

4.000

x 5.010M < 3.563

-1.000

2.000

-3.000

0 4.800M

4.900M

x 5.076M < 2.501

> 2

>

5.000M

5.100M

5.200M

TIME in Secs x = 66.25U y = -1.062 Figure 6.59

IsSpice simulated clamping of 5 kHz sine waveform.

circuit like the one shown in Fig. 6.62. This circuit provides a linear increase in voltage for increasing resistance from 1 to 1 k. By using two or three known resistors, a conversion table between output voltage and resistance can be developed. A simple modification to this circuit alters the range of resistance to be detected. Changing R3 alters the range of the resistance that can

Figure 6.60

PSpice simulated clamping of 5 kHz sine waveform.


5.000

4.000

4.000

2.000

183

3.000

UA741 in Volts

LM118 in Volts

1

0 2

2.000

-2.000

1.000

-4.000 4.800M

4.900M

5.000M

5.100M

5.200M

TIME in Secs

Clamping of UA741 (top) vs. clamping of LM318 (bottom).

Figure 6.61

be detected by decreasing the rate of rise of the output voltage. This increases the range, but also decreases the accuracy of the ohm meter. The zener diode used for this simulation is used in its “soft” region, which means that it is used below its recommended test current. This region is often not defined in data books, and may not be correctly

V(3) VCC

V3 10

R10 3.9

3

R3 979

4 VCC 2 16

VEE

V2

R1 2.64K 1

D1 ZN4728

R11 2.66K

V(3) VCC

Figure 6.62

Simple resistance-to-voltage circuit.

184

Chapter Six

TABLE 6.5

1N4728 Soft Zener Voltage Comparison Measured data

Conditions Ohms tested

IsSpice

PSpice

Micro-Cap

Measured data

3.9 72.5 179 379 808

3.165 3.166 3.167 3.17 3.174

3.1654 3.1662 3.1675 3.1699 3.1743

3.009 3.01 3.013 3.017 3.026

2.18 2.19 2.19 2.21 2.24

modeled in some libraries. As an illustration of this point, the voltage across the zener diode was taken for all of the test situations. The results of these measurements are given in Table 6.5. PSpice did not have a similar zener diode in its library, so a 1N4728 zener diode model was downloaded from an unnamed Web site. You could also use a voltage source set at 3.3 V in place of the zener. This would assume that the zener is used at its test current, IZT, which biases the PSpice results; however, if asked to build this circuit by using only the models that were contained in PSpice, this would be a natural assumption to make. The output voltage used to determine the resistance will be measured across R1. This positions the curve, so multiplying the output voltage by a scalar results in the resistance being measured. Using the voltage across R1 for our output does not correct the error caused by the incorrect zener voltage in the soft region. The results of the simulation and the measured data are shown in Fig. 6.63.

3

2.5

volts

2

1.5

IsSpice PSpice Micro-Cap

1

Measured Data 0.5

0 0

200

400

600

800

ohms

Figure 6.63

Resistance-to-voltage response using “soft” zener.

1000


V(3) VCC

V3 10

R10 808

3

R3 979

185

4 VCC 2 VEE

16

V2

R1 2.64K 1

D1 ZN4728

R11 70

V(3) VCC

Figure 6.64

Resistance-to-voltage response using “hard” zener.

These results show that all three of the SPICE simulators were not equipped to handle simulations of this particular zener diode in its soft region. However, zener diodes are not well defined or tested in this region of operation, so it may just be that the circuit tested had a worse than average zener diode in it. To further explore this problem, the experiment was modified to put more current than the specified test current in the zener diode. The circuit with these modifications made is shown in Fig. 6.64. The measurements across the zener diode are shown in Table 6.6, and the the resistance-to-voltage response is contained in Fig. 6.65. The 1N4728 has a test current of 78 mA; for the “hard” case, 98 mA was used to drive it. For the soft case, the zener current was only about 3 mA. Using such a wide operating range for a zener diode invites the flaws of the models to show up. If we only looked at the operating point TABLE 6.6

“Hard” Zener Voltage Comparison (Zener Voltage = 3.3 V)

Conditions Ohms tested 3.9 72.5 179 379 308

Measured data IsSpice

PSpice

Micro-Cap

Measured data

3.32 3.32 3.32 3.32 3.321

3.32 3.32 3.32 3.32 3.321

3.939 3.94 3.941 3.944 3.95

3.41 3.41 3.41 3.41 3.41

186

Chapter Six

3.5 3 2.5

volts

2 1.5 1 0.5 IsSpice 0

PSpice 0

200

400

600

800

1000

ohms

Figure 6.65

Micro-Cap Measured Data

Response resistance-to-voltage converter using “hard” zener.

of the zener, nearly all of the zener models are likely to be correct. It is important to note that zener diodes can be modeled, but unless you have compared the response of a zener model to hardware, be careful whether you believe the modeled response.

Run time summary (s) IsSpice v 8.11 Negligible

PSpice v 10.5 0.27

Micro-Cap v8.0 Negligible

Advantages: Low parts count, adjustable range Disadvantages: Small range, enlarging range decreases resolution File names: ohm met (IsSpice), ps ohm (PSpice), mic ohm (Micro-Cap)

Polarity Gain This circuit (Fig. 6.66) can be used to modify the amplitude and shift the phase of a given input waveform. This is accomplished by detecting the input waveform at the noninverting input pin of U1, which is configured as an input buffer. This signal is then fed into operational amplifiers U2 and U3. U2 provides a positive gain, which can be varied by tuning resistor R1. U3 provides a fixed inverted gain of –2. The output of U2 and U3 are then added together by U4. The output resulting from a grounded triangle wave, having a peak of 5 V, can be varied from 5 to –5 V. This includes the output, which is capable of being ground. The phase can also be shifted from 0 to 180◦ .


R2 4.66K

V1 15

R1 9.75K

C1 4.7U V(3) P15

C3 .1U

R8 9.79K

5 3

R6 9.77K

VCC

2.00

8

X2 UA741

15.0 VCC 2.00 X1 UA741

6

VEE

V(3) P15

6.19

V(11) OUTPUT

VEE

4

1 C2

2.00

4.7U -15.0

VIN 2

187

VCC

X4 UA741

V(1) N15 12

C4 .1U

VEE

-319U R3 9.76K

V2 -15

R5 9.86K

R9 4.65K 9

1.14M V(3) P15 R4 4.66K 7

1.15M 10

VCC

X3 UA741

2

VEE

-4.19

R7 4.66K -319U V(1) N15

Figure 6.66

Schematic of a polarity gain circuit.

Figure 6.67

Measured results (top, input; bottom, output).

V(1) N15

11

-2.04

188

Chapter Six

Figure 6.68

Micro-Cap simulated results (top, input; bottom, output).

10.000

6.000

6.000

2.000

2.000

INPUT in Volts

OUTPUT in Volts

1

-2.000

-2.000

-6.000 2

-6.000

-10.000 1.500M

2.500M

3.500M

4.500M

5.500M

TIME in Secs

Figure 6.69



Figure 6.70


Figure 6.71


189

190

Chapter Six

10.000

6.000 1

2.000

2.000 INPUT in Volts

OUTPUT in Volts

6.000

-2.000

-2.000

-6.000 2

-6.000

-10.000 1.700M

2.700M

3.700M

4.700M

TIME in Secs

Figure 6.72

IsSpice simulated results (top, input; bottom, output).

Figure 6.73


5.700M



10.000

6.000

6.000


OUTPUT in Volts

Figure 6.74

2.000

1

-2.000

-2.000

-6.000

-6.000

-10.000

2

2.000M

3.000M

4.000M

5.000M


191

IsSpice simulated results (top, input; bottom, output).

6.000M

192

Chapter Six

The output of the polarity gain adjustment circuitry is determined by the following equations: Vin := 2 V R1 := 9.84 k R2 := 4.66 k R3 := 9.76 k R4 := 4.66 k R6 := 9.77 k R8 := 9.79 k

The output of operational amplifier X2 is determined by R1 + R2 Vout2 := Vin R2 Vout2 := 6.223 V The output of operational amplifier X3 is determined by R3 Vout3 := −Vin R4 Vout3 := −4.189 V The output of the circuit is derived from the sum of the outputs of operational amplifiers X2 and X3. R8 R8 Vout := − Vout2 + Vout3 R6 R6 Vout := −2.038 V The value of resistor R1 can be determined and set to invert the input signal. R8 R8 Vout := − Vout2 + Vout3 R6 R6


TABLE 6.7

193

Simulation Results

Simulator

File name

Run time (s)

Micro-Cap IsSpice PSpice

Pol mc Pol ga Polps

1.125 2.816 1.91

Vout = −Vin

(R1 + R2 )R8 R3 R8 + Vin R2 R6 R4 R6

Vout := −Vin R1 :=

R8 R3 R8 − Vin − Vout + Vin R6 R4 R6 Vin

R2 R6 R8

R1 = 9.75 k The results using sine-wave, square–wave, and triangle-wave inputs are shown in Figs. 6.67 to 6.75. In all cases the gain circuit is symmetrical, resulting in a simple gain of –1. The simulation results (Table 6.7) were recorded for the analysis that had the following input voltage and transient statement. Pulse 0 4 0 1n 1n 1m 12m .TRAN 5u 7m 0 5u Bibliography Gilbilisco, Stan, ed. 1985. Encyclopedia of Electronics. Blue Ridge Summit, PA: TAB Books. Gilbilisco, Stan, ed. 1994. Amateur Radio Encyclopedia. Blue Ridge Summit, PA: TAB Books. Texas Instruments. 1992. Linear Circuits Data Book (Vol. 3). Sandler, Steven, M. 1998. Spice subcircuit accurately models zener characteristics. Personal Engineering Magazine, November, pp. 45–47, available at http://www. aeng.com/articles/zener.pdf


Chapter

7 Logic Circuits

Digital circuits are a key part of virtually every electrical system. The simplicity of 1’s and 0’s can create the reality of computers, calculators, CD-ROMs, fiberoptic transmissions, digital signal processors, and a host of other new technologies too numerous to mention. The building blocks of digital circuits are straightforward. From these simple building blocks, the complex circuits of tomorrow are born. The manufacturers of SPICE have adapted to the digital revolution, and as a result, all four of the simulators featured in this book have mixedmode simulation capabilities. The differences between analog and digital technologies create new and different concerns for engineers attempting to simulate digital circuits. Analog circuits have convergence problems, whereas digital circuits have timing problems. Analog circuits are a time-driven phenomenon, whereas digital circuits are an event-driven phenomenon. In this chapter, we will give the simulation user the tools to use these building blocks in order to perform more complex functions. We will also attempt to aid the engineer in recognizing the potential pitfalls of both breadboard digital circuits and simulated digital circuits.

Binary Counter Using JK flip-flops, we can design a circuit that will count a clock signal and provide a divided output of that clock signal. This circuit is shown in Fig. 7.1. The circuit is powered by an external %-V source (not shown in the schematic). The clock is running at 100 kHz with a 50% duty cycle. The J and K pins of the flip-flop are tied high, and the clear and reset pins are tied low. This causes the Q output to change states when the clock goes from low to high. Because 195


196

Chapter Seven

One

2 4 J 1

D

Clock

PR Q

CLK QN

A

K

10

J

6

PR Q

CLK

7

QN K

CL

9 8

CL

V(10) CLOCK D

D

Zero

V(12) QA Figure 7.1

A

A

12

13

V(13) QB

Schematic of a binary counter circuit.

the circuit only transitions on the low to high clock, two clock cycles go by for one output cycle, thus creating a divide-by-2 output. If this new signal is fed into another JK flip-flop configured the same way, this signal is also divided by 2, which is the original signal divided by 4. Using this method and N more JK flip-flops, any division of 2 N can be realized. The resulting breadboard waveforms are shown in Fig. 7.2. The top waveform is the 100 kHz clock, the middle waveform is the Q output of the first JK flip-flop stage (divide by 2), and the bottom waveform is the Q output of the second JK flip-flop stage (divide by 4). This circuit was simulated using IsSpice, PSpice, and Micro-Cap. The results of each of these simulators are shown in Figs. 7.3, 7.4, and 7.5, respectively. Breadboard tip

Bypass capacitors may be necessary (and are recommended) from the Vdd pin to ground in order to minimize signal jitter and noise effects.

Logic Circuits

Breadboard waveforms of binary counter circuit.

2.500

1.000

1.500

0

500.0M

CLOCK in Volts

QA in Volts

Figure 7.2

1

-1.000 2

-500.0M

-2.000

-1.500

-3.000

3

10.000U

30.00U

50.00U

70.00U


IsSpice waveform results of binary counter circuit.

90.00U

197

198

Chapter Seven

Figure 7.4

PSpice waveform results of binary counter circuit.

Figure 7.5

PSpice waveform results of binary counter circuit.

Logic Circuits

199

For circuits that count to values greater than 4, a counter IC is the more logical choice. Parts such as CD4017 contain any number of these JK counter stages that can be used to count to any number required.


PSpice v 10.5 3.03


Advantages: Accurate, very low propagation delay Disadvantages: Can be realized with fewer parts File names: Count (IsSpice), Count 2 (PSpice), Count3 (Micro-Cap)

Binary Decoder Using the characteristics of the circuit shown in Fig. 7.1, we can add AND gates and create a binary decoder circuit. The binary decoder circuit looks at two input signals and determines whether the signal corresponds to a 0, 1, 2, or 3. The truth table for the binary decoder is shown in Table 7.1. Figure 7.6 shows the schematic of the complete circuit schematic that provides this logic function. The binary counter circuit (Fig. 7.1) provides the input signals, and the AND gates provide the decoder logic. The clock signal is 100 KHz at 50% duty cycle. Breadboard tip

Bypass capacitors may be necessary (and are recommended) from the Vdd pin to ground in order to minimize signal jitter and noise effects.

The breadboard results are shown in Fig. 7.7. Owing to the limitations of the oscilloscope we used, only four traces may be shown on one plot. In Fig. 7.7, the top trace is the QA output, the second trace from the top is the QB output, the third trace is the zero code, and the bottom trace is code 1. The results of Fig. 7.7 illustrate the decoding properties. Figure 7.8 shows the Micro-Cap results. TABLE 7.1

Truth Table for the Binary Decoder Input signal

QA

QB

Output of decoder

Low High Low High

Low Low High High

0 1 2 3

200

Chapter Seven

One

2 3 J

D

Clock

1

PR Q

CLK QN

A

K

10

J

8

PR 7

Q CLK

4

5

QN K

CL

CL

V(10) CLOCK D

D

Zero

A

A

12

V(12) QA

13

V(13) QB

Q1 Q1NOT Q2 Q2NOT

9

17

15

V(15) O2

A

V(14) O1

A

A

A

14

18

D

D

D

D 11

V(11) O0

Figure 7.6

19

16

V(16) O3

Schematic for the binary decoder.

The breadboard results of the code cases 2 and 3 are shown in Fig. 7.9. The top two traces are QA and QB, while the bottom two traces are codes 2 and 3. The Micro-Cap simulation results are shown in Fig. 7.10. The Micro-Cap simulator was exact enough to show the slight overlap of the decoder after code 1 and code 3. This is a result of the

Logic Circuits

Figure 7.7

Breadboard results of the binary decoder circuit (0 and 1).

Figure 7.8

Micro-Cap results of the binary decoder circuit (0 and 1).

201

202

Chapter Seven

Figure 7.9

Breadboard results of the binary decoder circuit (2 and 3).

Figure 7.10

Micro-Cap results of the binary decoder circuit (2 and 3).

Logic Circuits

3.000

203

1.000 1

-1.000

2

-1.000

QA in Volts

QB in Volts

1.000

-3.000 3 -5.000

-3.000

4 -7.000

-5.000

10.000U

30.00U

50.00U

70.00U

90.00U


3.000

IsSpice results of the binary decoder circuit (0 and 1).

1.000 1

-1.000

QA in Volts

QB in Volts

1.000

-3.000

-1.000

2

-3.000

3

-5.000

4 -5.000

-7.000

10.000U

30.00U

50.00U

70.00U


IsSpice results of the binary decoder circuit (2 and 3).

90.00U

204

Chapter Seven

Figure 7.12a

PSpice results of the binary decoder circuit (0 and 1).

race condition that exists in this circuit. Parameters such as rise and fall times must be accurate in order to represent the true behavior of the digital circuitry. The IsSpice and PSpice simulation results are shown in Figs. 7.11 and 7.12. The simulation results from the IsSpice and PSpice are in the same format as the results from the breadboard and the Micro-Cap simulator.

Figure 7.12b

PSpice results of the binary decoder circuit (2 and 3).

Logic Circuits

205


PSpice v 10.5 3.22

Micro-Cap v8.0 0.64

Advantages: Accurate, very low propagation delay Disadvantages: Can be realized with fewer parts File names: Decode (IsSpice), Decode2 (PSpice), Decode3 (Micro-Cap)

Set-Reset Latch A latching circuit waits for an event to occur. Once that event occurs, the latch output changes state and will ignore any further events until reset. This can be described as a memory element. The latch has many applications in the system. For example, if a failure mode occurs in the system, a shutdown signal may be sent to the latch circuit, which will shut down the system and prevent any further possible damage. The system will remain shut down until the power to the system is recycled. The circuitry representation of the set-reset latch is shown in Fig. 7.13. The power to the latch is not shown in the schematic. A +5-V DC input was used to power the digital ICs. The truth table for the set reset latch is shown in Table 5.2. In order to show the performance of the set-reset flip-flop, a series of events were initiated. The reset pin of the flip-flop was first set high, then low. This allows the flip-flop to read and react to a change-ofstate event on the set pin. A pulse was then applied to the set pin. When the set pin transitioned from low to high, the output (Q) of the A1 NOR2_001 Reset

1 4

Q

5

A2 NOR2_002 Qnot Set Figure 7.13

2

Schematic of a set-reset latch.

206

Chapter Seven

TABLE 7.2

Truth Table for Set-Reset Flip-Flop

S

R

Q

Qnot

State

0 0 1 1

0 1 0 1

Q 0 1 0

Qnot 1 0 0

Unchanged Reset Set Not allowed

flip flop changed state from 0 to 1. Subsequent transitions on the set pin were now ignored by the flip-flop. This is shown in the breadboard waveforms of Fig. 7.14. The results of the IsSpice, PSpice, and MicroCap simulations are shown in Figs. 7.15, 7.16, and 7.17, respectively. Examining the results of Figure 7.14, we see the Q output transitioned from low to high when a low to high transition was detected on the set input. After being set high, the flip-flop ignored any further activities of the set pin. In order to return the flip-flop to the read state, the reset pin must be transitioned from low to high, and then back to low again. This action will reset the Q output to 0, and the flip-flop will be ready to respond to the set input.

Figure 7.14

Breadboard output results (top, set input; bottom, Q).

15.00

40.00

5.000

30.00

-5.000

-15.00

OUT in Volts

SET in Volts

Logic Circuits

207

2

20.00

10.000 1

-25.00

0

250.0M

750.0M

1.250


IsSpiceoutput results (top, set input; bottom, Q).

Figure 7.16

PSpice output results (top, Q; bottom, set input).

1.750

2.250

208

Chapter Seven

Figure 7.17

Micro-Cap output results (top, Q; bottom, set input).

In order to model this in the SPICE programs, the set input was pulsed using an independent voltage source and the following command: PULSE 0 5 250M 100U 100U 500M 1 One interesting result of these simulations is the need for the digital circuits to be initialized. Each of the three simulators was run at different time lengths in order to accommodate this requirement of the simulators. If the initialization is not performed, some of the simulators are not able to determine the initial output state.


PSpice v 10.5 0.95


Advantages: Multiple applications Disadvantages: Set and reset high state not allowed File names: latch (IsSpice), latch2 (PSpice), latch3 (Micro-Cap)

Staircase Generator Staircase generator circuits have important applications in video systems. There are several ways to generate staircase waveforms, using

Logic Circuits

209

R2 100K

V1 15

R1 100K

23

V(22) OUT

16 VCC 22

R3 100K 25

VEE 24

R4 100K

V2 -15

R5 100K R6 100K

V(29) QB

V(28) QC

29

A

26

D

D

A

14

D

D

D

A

27

V(26) QD

28

A

V(27) QA

A

V(14) RESET

One

13 5 J

D

Clock

18 6

A

10

Q CLK QN K

Zero

PR

CL

1 7

J

PR Q

CLK QN K

CL

9 8

J

PR Q

CLK QN K

J

2

Q CLK

4

QN K

CL

A

Figure 7.18

CL

11 21

J

PR Q

CLK QN K

12 15

CL

D

V(10) CLOCK

PR

3

Schematic of staircase generator.

either analog or digital design methods. This circuit investigates the digital solution to the staircase generator. The schematic of the staircase generator circuit is shown in Fig. 7.18. Not shown in the schematic is the power to the JK flip-flops and the AND gate. A +5-V DC input was used to power the digital ICs. The staircase waveform starts after the clear signal is received by the JK flip-flops. The clear signal sets all Q outputs to 0 and all Qnot outputs to 1. With the set pin tied low and the J pin tied high, when a low to high clock transition is detected, the Q output will transition from low to high. The Q output is tied to the J pin of the next flip-flop, and so one clock cycle later, the Q output transitions from low to high, and so on. When the final JK flip-flop stage Q output transitions high, the AND gate clears the flip-flops and starts the cycle over again. The four staggered signals from the Q output of the first four flip-flops are summed in an op-amp adder circuit, and the result is the repeating staircase waveform. The clock of the circuit shown in Fig. 7.18 is set at 1 kHz with a 50% duty cycle.

210

Chapter Seven

SPICE tip

The small blocks marked “D A”, at the QA node for example, are artifacts from the mixed-signal simulation process. Most modern SPICE simulators contain separate digital and analog simulators whose time step is linked as the simulation progresses. Pure digital elements are processed by the digital simulator, while the rest of the circuitry is processed by the analog algorithms.

If an event or threshold is reached in one simulator that must be accounted for by the other simulator, the information is passed via one of these A-D or D-A “bridges.” Bridges perform several functions. A-D bridges translate analog signals into digital states depending on a specified threshold. D-A bridges translate a digital state to specified analog voltages. Both bridges can also have several levels of input/output impedance representations.

The schematic capture program hides these bridges, enabling the designer to use digital or analog-modeled parts without regard for the internal simulator that will handle the calculations.

While the bridges are not shown, they are there and will affect the results produced.

The staircase generator circuit was constructed in all three simulators and in the lab by using real components. The breadboard used a

Figure 7.19

Breadboard output results (Q outputs).

Logic Circuits

40.00

211

5.000 1

30.00

-5.000

20.00

QA in Volts

QD in Volts

2 -15.00

10.000

-25.00

3

0

-35.00

4

1.000M

3.000M

5.000M

7.000M

9.000M


IsSpice output results (Q outputs).

UA723 for the op-amp, CD4027 for the JK flip-flops, and a CD4081 for the AND gate. The breadboard staggered Q outputs of the first four JK flip-flops are shown in Fig. 7.19. Figures 7.20, 7.21, and 7.22 show the results of the IsSpice, Micro-Cap, and PSpice simulators, respectively.

Figure 7.21

Micro-Cap output results (Q outputs).

212

Chapter Seven

Figure 7.22

PSpice output results (Q outputs).

Figure 7.23

Staircase waveform: breadboard results.

Logic Circuits

10.000

213

35.00 2

-10.000

-20.00

25.00

OUT in Volts

CLOCK in Volts

0

15.00

5.000 1

-30.00

-5.000

1.000M

3.000M

5.000M

7.000M

9.000M


Staircase waveform: IsSpice results.

Note that the PSpice results are shown in a slightly different configuration because of the PROBE waveform display program. Three of the four Q output waveforms are shown in the lower section of the plot (analog waveform), while the clock (a digital signal) is shown at the top.

Figure 7.25

Micro-Cap results.

214

Chapter Seven

Figure 7.26

PSpice results.

The outputs shown in Figs. 7.19, 7.20, 7.21, and 7.22 were summed by using the operational amplifier adder circuit shown in Fig. 7.18. The results of the breadboard are shown in Fig. 7.23, with the clock at the top and the staircase waveform at the bottom. The IsSpice, Micro-Cap, and PSpice results are shown in Figs. 7.24, 7.25, and 7.26, respectively.


PSpice v 10.5

Micro-Cap v8.0

1.8

1.69

1.031

Advantages: Applicable for multiple frequency input signals Disadvantages: Can be realized with fewer parts File names: stair (IsSpice), stair2 (Micro-Cap), stair2 (PSpice)

Bibliography DeMassa, Thomas A. 1989. Electrical and Electronic Devices: Circuits and Instruments. West Publishing Co. Gibilisco, Stan, ed. 1994. Amateur Radio Encyclopedia. TAB Books. Gibilisco, Stan, ed. 1995. Encyclopedia of Electronics. TAB Books. Harris Semiconductor. 1993. Radiation Hardened Product Databook. Kimbler, Will. 1994. Practical Digital Electronics for Technicians. Oxford: BH Newnes. Markus, John, ed. 1980. Modern Electric Circuit Reference Manual. New York: McGrawHill.

Chapter

8 Resonator/Oscillator Circuits

A resonator is defined as a condition in a circuit that converts energy from a potential form to a kinetic form. One example of a resonator in electronics is that of the LC filter. As the capacitor discharges, the inductor stores the energy, and as the inductor converts the magnetic energy into electrical energy, the capacitor charges up again. This action can be observed by an oscilloscope, with the resulting waveform having a distinct period. This repeating phenomenon is called resonance. An oscillator circuit is defined as “an electronic circuit that converts energy from a direct-current source into a periodically varying electrical output” (Parker 1984). Therefore, an oscillator takes a steady state signal and, using electrical behaviors of circuit elements, converts the signal into a periodic, time-variant signal. This oscillation can be sinusoidal in appearance (sine wave oscillation), square waved, triangular waved, or any variety of repeatable signals. This time-variant signal (usually referred to as an AC signal) is found in a multitude of electronic circuits. Power delivered to homes and businesses is nearly universally transmitted using an AC signal. Communications circuits require exact sine waves in order to transmit information over large distances with low loss of signal integrity. Just as numerous as the amount of potential uses for oscillator circuits is the amount of circuits that can create these oscillators. In this chapter we will examine several oscillator circuits in detail.

555 Timer Oscillator The astable operation of the UA555 as an oscillator has a duty cycle and free running frequency, which are both precisely controlled with two external capacitors and two resistors. The circuit is shown in Fig. 8.1. 215


216

Chapter Eight

R2 37.8K

3

V1 15

R1 38.2K TRIG

VCC DISCHG

X2 UA555

V(4) OUT

4

2

1

THRES

OUT CTRL RESET

5

V(1) RAMP C1 2140P

C2 .01U

Figure 8.1

555 Oscillator schematic.

The circuit was constructed in the laboratory. The values of R1, R2, C1, and C2 are the actual measured values of the components used in the circuit. A Tektronix TDS 340A digital real-time oscilloscope was used to record the output data, as shown in Fig. 8.2. The duty cycle was calculated to be 66.7%, and the output voltages oscillated from 5 V to 10 V. The simulated data, from IsSpice, Micro-Cap V, and PSpice, are shown in Figs. 8.3, 8.4, and 8.5, respectively. Table 8.1 illustrates the variances in the simulated output data. Simulation tips

The IsSpice simulator required a UIC statement even though no initial conditions were used in the transient simulation.

The Micro-Cap V global setting for DIGIOLVL, the default digital IO level, needed to be specified at 2 for the simulation to run correctly.

Fourth-Order Butterworth Low Pass Oscillator Shown in Fig. 8.6 is a fourth-order Butterworth low pass oscillator. Figure 8.7 is the square wave generated at node 10 and the resultant sine wave after filtering at node 3. The lab results are shown in Fig. 8.8. Circuit tip

Note that the Q of the op-amp stage in an oscillator circuit is designed to be large in order to create an oscillation, while the Q of the op-amp stage of a filter is designed to be small in order to suppress the possibility of oscillation.

Resonator/Oscillator Circuits

555 Oscillator measured data.

35.00

15.00

25.00

5.000

15.00

OUT in Volts

RAMP in Volts

Figure 8.2

217

1 -5.000

2 5.000

-15.00

-5.000

-25.00 434.6U

534.6U

634.6U

734.6U

834.6U

TIME in Secs Duty Cycle=66.64% Frequency=5.917KHz Figure 8.3

IsSpice simulated data.

218

Chapter Eight

Figure 8.4

PSpice simulated data.

Figure 8.5

Micro-Cap V simulated data.

TABLE 8.1

Summary of Results

Simulator

SPICE file

Duty cycle (%)

Frequency (kHz)

IsSpice Micro-Cap PSpice

555osc 555mc Ps 555

66.64 66.39 66.35

5.917 5.856 5.93

Run time (s) 2.633 2.533


219

1

15.0 V1 15

R1 20K

V2 15 2

R2 20K

3

-15.0 V(2) VEE

4

40.3M

6

30.0M

C2 .01U 5

19.6M C1 .005U

X4 OPAMP R3 20K VEE

20.6M VCC

R4 20K 91

1

10.3M C4 .01U

-389N C3 .005U

10

X5 OPAMP

VEE

1.00M VCC

VCC VEE

X3 OPAMP

Figure 8.6

Fourth-order Butterworth low pass oscillator schematic.

30.00

10.000

20.00

-10.000

10.000

0

V(3) in Volts

V(10) in Volts

2

-30.00

-50.00 1

-10.000

-70.00

6.700M

7.100M

7.500M

7.900M

8.300M

WFM.2 V(3) vs. TIME in Secs Figure 8.7 IsSpice results of square wave generated at node 10 and the resultant sine wave at node 3.

220

Chapter Eight

Figure 8.8

Hardware results of Butterworth low pass oscillator.

The schematic for Micro-Cap is shown in Fig. 8.9. The resulting waveforms are shown in Fig. 8.10. The PSpice result is shown in Fig. 8.11. Simulation tips

Although all three simulators correctly predicted the frequency and amplitude of the sine wave, only the IsSpice simulation predicted the DC offset in the output waveform. The reason for this is the simulations for each used the LM124 model that came with the simulation

Figure 8.9

Micro-Cap schematic of Butterworth low pass oscillator.

V(6) F

V(8) F Micro-Cap results of Butterworth low pass oscillator.

20.00

30.00

0

20.00

-20.00

V(10) in Volts

V(14) in Volts

Figure 8.10

2 10.000

-40.00

0

-60.00

-10.000

1

9.200M

9.600M

10.00M

10.40M

10.80M

WFM.1 V(10) vs. TIME in Secs Figure 8.11

PSpice results of Butterworth low pass oscillator. 221

222

Chapter Eight

package. These libraries may be provided by manufacturers or the software company. It is very important to remember that these models may not be accurate for all the parameter(s) that you are interested in or over every point in the operating range of the device. Even in IsSpice, there were four different models for the LM124, and only one correctly predicted the DC offset.

If the simulation doesn’t show the model accurately reflecting the component’s behavior, this does not necessarily mean the model is useless or wrong (although this is a possibility). People make models to model different aspects of a part and sometimes only cover a subset of the full operating or temperature range. For example, some models may have only AC characteristics modeled accurately and not the transient performance.

Models are often made for different reasons. If all you are interested in is large signal characteristics, it would not be helpful if noise rejection was also modeled. In addition, if you were interested in only large signal characteristics, you probably would not want a model with noise rejection because it would require more of a transistor-level representation, which would result in much longer simulation run times as well as possible convergence problems. The bottom line with any simulator is that all models are not created equal. You need to understand the trade-offs between speed, accuracy, and the ability to converge (Kielkowski 1994).

The Fourier results were also computed using each of the simulators and compared with the hardware data. The Fourier results of the hardware are shown in Fig. 8.12. The Fourier results of IsSpice, Micro-Cap, and PSpice are shown in Figs. 8.13, 8.14, and 8.15. Note that the simulators returned three different outcomes for the Fourier results of this circuit. Separated hardware waveforms of Fig. 8.8 are shown in Figs. 8.16 and 8.17. with measurements.


PSpice v 10.5 3.34


Advantages: Good long-term frequency stability, moderate distortion, easily adjusted, moderate drive capability Disadvantages: High parts count, DC offset File names: lp osc (IsSpice), pbp osc (PSpice), Lposc (Micro-Cap)

Hex Inverter Oscillator The delay is created by the alternate charging of capacitor C1 (through R1) and the discharge of C1 (through R2). The output is a square wave

Figure 8.12

Fourier analysis results of output of Butterworth low pass oscillator.

Fourier 45 40 35 Magnitude

30 25

dB

20 15 10 5

Frequency Figure 8.13

IsSpice Fourier results.

223

10800

9600

8400

7200

6000

4800

3600

2400

1200

0

224

Chapter Eight

LPOSC.CIR Temperature = 27

HARM(v(8)) F Figure 8.14

Micro-Cap Fourier results.

Fourier 45 40 35

Magnitude

30 25 dB 20 15 10 5

Frequency

Figure 8.15

PSpice Fourier results.

10800

9600

8400

7200

6000

4800

3600

2400

1200

0

Node 10 voltage waveform with high voltage, low voltage, duty cycle, and frequency measurements.

Figure 8.16

Figure 8.17

Output sine wave with frequency, amplitude, and mean measurements.

225

226

Chapter Eight

of fixed frequency. Many different inverter ICs are capable of this operation (SN54LS05, SN74LS04, and CD4049). Make sure the propagation delay is small compared with the period of the oscillator frequency desired. Circuit tip

You are attempting to breadboard this circuit, you may need bypass capacitors (0.1 µF capacitors from Vdd to the local IC ground) in order to minimize jitter and noise effects. These ICs switch at a very fast rate and can easily cause switching noise to appear on the outputs.

Circuit tip

A minimum propagation delay is required for the start-up of this circuit. Make sure the data sheet or SCD of this part has a minimum listed propagation delay.

The circuit schematic is shown in Fig. 8.18. The IsSpice simulation results are shown in Fig. 8.19. These results compare very well with the measured performance (Fig. 8.20). The circuit was also simulated in PSpice and Micro-Cap. The results of those simulations are shown in Figs. 8.21 and 8.22. In Fig. 8.22, interestingly, the Micro-Cap results showed an output frequency roughly twice that of PSpice or IsSpice. The reason for this is the Micro-Cap

V1 5 2

5.00 VCC

1

2.92

VCC

3

2.92

VSS

VSS

R1 46.5K;47 5

R2 98.6K;10 Figure 8.18

Inverter oscillator schematic.

919M C1 1.088N;1

8

919M

V(8) OUT

28.50

15.00

18.50

5.000

8.500

Output in Volts

V(5) in Volts


227

1 -5.000

-1.500

-15.00

-11.50

-25.00

2

50.00U

150.0U

250.0U

350.0U

450.0U


IsSpice simulation results of node 5, and output waveforms.

Figure 8.20

Hardware resulting waveforms of inverter oscillator schematic.

228

Chapter Eight

6.00

OUT in Volts

4.00

2.00

0

1

-2.00

50.0U

150U

250U

350U

450U

WFM.1 OUT vs. TIME in Secs Figure 8.21

PSpice resulting waveforms of inverter oscillator schematic.

model for the 4049 inverter was used. This model had a hysteretic input threshold. In actuality, the part has a linear region and is not hysteretic; however, the Harris data sheet for this part does show that the threshold levels of the model are within the data sheet requirements. This illustrates the dependency of the frequency on the input threshold of the 4049 inverter.


PSpice v 10.5 0.39

Micro-Cap v8.0 2

Advantages: Low parts count, good drive capability Disadvantages: Accuracy over life, temperature probably unpredictable File names: 4049osc (IsSpice), ps 4049 (PSpice), mc 4049 (Micro-Cap)

Fourth-Order Butterworth No-Offset Low Pass Oscillator This oscillator is similar to the circuit in Fig. 8.6, the difference being there is no DC offset in this circuit. The schematic is shown in Fig. 8.23.

MC_4049.CIR Temperature = 27

V(3) Time

V(2) Time Figure 8.22

Micro-Cap resulting waveforms of inverter oscillator schematic.

1

15.0 V1 15

R1 20K

V2 15 2

-15.0 V(2) VEE

13

R2 20K 4

35.4M

6

25.1M C2 .01U

X4 OPAMP

14.8M C1 .005U

5

R3 20K VEE

R4 20K 9

15.8M

11

5.48M

VCC

C4 .01U

X5 OPAMP

-4.84M C3 .005U

10

VEE

-3.84M VCC

1N4735A 6.2V 1N4735A 6.2V

R9 10K

3

18.1M

14 VCC

1.00M

VEE

X3 OPAMP

Figure 8.23

Fourth-order Butterworth no-offset low pass oscillator.

229

230

Chapter Eight

20.00

10.000 V(13) in Volts

1

0

-10.000

-20.00

6.450M

6.950M

7.450M

7.950M

8.450M


Clamped square wave at node 13.

This has the benefit of the harmonics distortion not being sensitive to the Vcc/Vee parameters of the operational amplifier. Two matched zener diodes (1N4735A 6.2 V were used in the lab circuit) across the operational amplifier clamp the output to roughly equal levels. The resistor R9 limits the current through the clamping diodes. Figure 8.24 is the clamped square wave generated at node 13. The resultant sine wave after filtering at node 10 is shown in Fig. 8.26. The lab results are shown in Figs. 8.25 and 8.27. Simulation tip

The amplitude of the SPICE model result has about a 1-V offset missing from the result. This is due to the forward drop of the zener diode, which is not typically modeled in zener diode models. It is not difficult to model this parameter, but since the purpose was to show the zero offset result, it is not important here.

The same circuit was simulated in PSpice and Micro-Cap. The results are shown in Figs. 8.28, 8.29, 8.30, and 8.31. The Fourier results were also calculated. The hardware result is shown in Fig. 8.32, and the results from the simulators are shown in Figs. 8.33, 8.34, and 8.35. Note that in the Fourier results, the second harmonic is now greatly attenuated. The hardware circuit used 5% tolerance resistors, causing the simulation frequency to be slightly off. Another simulation was run


Figure 8.25

231

Lab results of Butterworth no-offset low pass oscillator.

8.000

V(10) in Volts

4.000

1

0

-4.000

-8.000

6.500M

7.000M

7.500M


Sine wave output at node 10.

8.000M

8.500M

232

Chapter Eight

Figure 8.27

Lab results of Butterworth no-offset low pass oscillator.

Figure 8.28

PSpice result of Butterworth no-offset low pass oscillator.


Figure 8.29

PSpice result of Butterworth no-offset low pass oscillator.

Figure 8.30

Micro-Cap result of Butterworth no-offset low pass oscillator.

233

234

Chapter Eight

Figure 8.31

Micro-Cap result of Butterworth no-offset low pass oscillator.

Figure 8.32

Lab data Fourier analysis result of output sine wave.


235

Fourier 40 35

Magnitude

30 25 dB

20 15 10 5 10800

9600

8400

7200

6000

4800

3600

2400

1200

0


IsSpice Fourier analysis results.

Fourier 40 35

Magnitude

30 25 dB

20 15 10 5


PSpice Fourier analysis results.

10800

9600

8400

7200

6000

4800

3600

2400

1200

0

236

Chapter Eight

Figure 8.35

Micro-Cap Fourier analysis results.

with the exact resistor values of the hardware circuit in order to show the accuracy of the model. The schematic is shown in Fig. 8.36, and the resulting waveform is shown in Fig. 8.37.

Run time summary (s) IsSpice v 8.11 2.950, 2.950

PSpice v 10.5 1.02


Advantages: Good long-term frequency stability, moderate distortion, easily adjusted, moderate drive capability Disadvantages: High parts count File names: lp osc2, lp osc2a (IsSpice), ps osc2 (PSpice), lposc2 (Micro-Cap)

Harmonic Neutralized Sine-Wave Oscillator The output of this circuit is generated from a series of square-wave pulses. Square waves are easier to generate than sine waves and can accurately be produced by a digital logic IC. This circuit generates a series of square-wave pulses, skewed in time and summed. This resultant summed waveform resembles a stepped representation of a sinusoidalwave. This waveform is passed through a filter, and the final signal is a clean sine wave. This version of the harmonic neutralized sine-wave oscillator uses a series of flip-flop gates, configured as a shift register (supplied by a 74HC174 IC) and an inverter (supplied by a CD4049) to provide the


237

1

15.0 V1 15

V2 15

R1 21.3K

2

13

-15.0 V(2) VEE

R2 21.3K 4

38.2M

6

27.2M

X4 OPAMP

16.3M C1 .00512U

C2 .0102U 5

R3 21.3K VEE

17.3M VCC

R4 21.3K 9

11

6.26M

C4 .0102U

X5 OPAMP

-4.73M C3 .005U

10

VEE

-3.73M VCC

1N4735A 6.2V 1N4735A 6.2V

R9 9.77K

3

19.4M

14

1.00M

VCC VEE

X3 OPAMP

Figure 8.36

A more exact simulation model.

10.000

12.00 2

-10.000

-20.00

8.000

V(10) in Volts

V(13) in Volts

0

4.000

0 1

-30.00

-4.000

6.700M

7.100M

7.500M

7.900M

WFM.1 V(10) vs. TIME in Secs Figure 8.37

More exact simulation results.

8.300M

238

Chapter Eight

V(24) 500STP

V(28) +5V X26 74174 24

R2 150K

R5 150K

28

VDD

CLR* 14

R3 75K

R1 86.6K

6

8

5

V(28) +5V

Q1

Q6

D1

D6

D2

D5 Q5

Q2 D3

D4

Q3

Q4 CLK

VSS

C2 .1U

21

20

R4 86.6K

3 4

V(28) +5V X27 CD4049UB

VCC VSS

V(4) 6KHZ

Figure 8.38

Schematic of multiphase square-wave generator.

skewed square-wave pulses. The schematic for the harmonic neutralized sine-wave oscillator is shown in Fig. 8.38. A 6-kHz square-wave pulse from a function generator is fed into the clock of the 74HC174. Each of the outputs of the flip-flop gates is summed in such a way so as to eliminate the third, fifth, seventh, and ninth harmonics. This is of great importance when attempting to filter the sine wave. The elimination of the third, fifth, seventh, and ninth harmonics greatly simplifies the design of the output filter. The resulting sum of this signal is shown in Fig. 8.41. The top waveform in Fig. 8.41 is the 6-kHz input square wave. The bottom waveform is the resultant quasi-square output waveform. The skewed outputs of the 74HC174 are shown in Fig. 8.39. The results of the simulation of this circuit are shown in Figs. 8.40, 8.42 and 8.43.


Skewed outputs of the 74HC174.

35.00

15.00

25.00

5.000

15.00

6KHZ in Volts

500STP in Volts

Figure 8.39

2

-5.000

5.000

-15.00

-5.000

-25.00

1

500.0U

1.500M

2.500M


239

IsSpice result of quasi-resonant 500 Hz output.

3.500M

4.500M

240

Chapter Eight

Figure 8.41 6 kHz Input square wave (top) and quasi-resonant 500 Hz output of 74HC174 (bottom).

Figure 8.42

Micro-Cap result of quasi-resonant 500 Hz output.


Figure 8.43

241

SIMetrix result of quasi-resonant 500 Hz output.

The effects of the circuit in the frequency domain were also characterized. The Fourier transform of the quasi-square waveform in Figure 8.41 was taken and the results shown in Fig. 8.44. Note that the third, fifth, seventh, and ninth harmonics are suppressed by about 40db, while the eleventh and thirteenth harmonics are about 20 dB less. The IsSpice simulation of this circuit was generated using the ICL feature of IsSpice. The format of the FOURIER command is shown below in Table 8.2. The resulting circuit characteristics in the frequency domain (Fig. 8.44) compare favorably to the resulting output from the IsSpice file (Table 8.3), which is imported into Excel for graphing (Fig. 8.45). Fourier analysis for v(18) Circuit tip

If you are attempting to breadboard this circuit, you may need bypass capacitors (0.1 µF capacitors from Vdd to the local IC ground) in order to minimize jitter and noise effects. These ICs switch at a very fast rate and can easily cause switching noise to appear on the outputs.

IsSpice and PSpice tip

To import the data resulting from the FOURIER command (as shown in Table 8.3) into a spreadsheet, such as Excel, first, open the output (.out) file. Highlight and copy the data you need in the .out file, and open Excel. After Excel opens, paste the contents into the spreadsheet. The next step should be to pull down the DATA menu and select the TEXT TO COLUMNS command. Follow the steps to convert the pasted data into

242

Chapter Eight

Figure 8.44

Fourier transform of 500 Hz output of 74HC174.

space delimited data. After this is completed, you should have columns for each of the data headings used by IsSpice to write the results of the FOURIER command. You may now use Excel’s graphing features to view your data. This procedure works for normal output data as well. If you ever wish to extract data from an output simulation to Excel, follow these steps. Excel performs a dizzying array of mathematical and statistical operations that can be exploited by engineers.

This circuit is now ready to be connected to a band pass filter, shown in Fig. 8.46.

TABLE 8.2

FOURIER Command Syntax for IsSpice, Pspice, and Micro-Cap

IsSpice: In the Edit Controls box of the schematic, type the following line: .FOUR 1.2K V(10) PSpice: In the Analysis menu, select Setup. Click the Transient button, and check the Enable Fourier box. Then enter the center frequency, number of harmonics, and output variables. Micro-Cap: In the Analysis menu, select Transient Analysis. In the box for the Y expression, enter the following: HARM (V(x)) where x is the node of interest.


TABLE 8.3

243

FOURIER Command Result from IsSpice Simulator

No. Harmonics: 25, THD: 0.48878 %, Gridsize: 200, Interpolation Degree: 1 Harmonic 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Frequency

Magnitude

Phase

Norm. Mag

Norm. Phase

0.000 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 6500 7000 7500 8000 8500 9000 9500 10000 10500 11000 11500 12000

122655 1.24307 0.00319095 0.00166368 0.00128604 0.00109791 0.000827279 0.000628331 0.00061474 0.000631205 0.000489693 0.0036889 0.000405014 0.00192657 0.000349058 0.000234937 0.00030614 0.000372014 0.000271725 0.000184528 0.000247479 0.000309538 0.000223398 0.000872786 0.000205702

0 96.3886 −168.46 −172.57 −172.55 −171.91 −172.44 −169.82 −170.92 −171.98 −169.96 −176.92 −167.58 −0.25543 −166.88 −162.68 −164.37 −165.56 −163.62 −148.74 −160.65 −169.24 −160.26 −173.63 −157.21

0 1 0.00256699 0.00133837 0.00103457 0.000883227 0.000665513 0.000505467 0.000494533 0.000507779 0.000393939 0.00296757 0.000325818 0.00154985 0.000280803 0.000188998 0.000246278 0.00029927 0.000218591 0.000148445 0.000199087 0.000249011 0.000179715 0.000702121 0.000165479

0 0 −264.85 −268.96 −268.94 −268.3 −268.83 −266.21 −267.3 −268.37 −266.35 −273.31 −263.96 −96.644 −263.27 −259.07 −260.76 −261.95 −260.01 −245.13 −257.04 −265.63 −256.65 −270.02 −253.6

db 12000

11000

10000

9000

8000

7000

6000

5000

4000

3000

2000

-10

1000

0

0

-20 -30 db

-40 -50 -60 -70 -80 Figure 8.45

IsSpice results of quasi-resonant 500 Hz output.

244

Chapter Eight

V(10) 500STP

V(28) +5V X26 74174 10

R2 150K

28 14

R3 75K

R1 86.6K

6

R5 150K

C4 .1U

VDD

CLR* Q1

Q6

D1

D6

18

VCC 15

R8 20K

C3 .1U

21

23

V(18) OUT

15 VCC

8

5

V(28) +5V

D2

D5

Q2

Q5

D3

D4

Q3

Q4 CLK

VSS

C2 .1U

20

R4 86.6K

R9 500

VEE 22

VEE -15

3

X33 OPAMP

4

V(28) +5V X27 CD4049UB

VCC VSS

V(4) 6KHZ

Figure 8.46

Schematic of multiphase square-wave generator connected to band pass

filter.

The resulting output of the breadboard is shown in Fig. 8.47. The outputs of the SPICE simulations are shown in Figs. 8.48a and 8.48b. The output of the circuit is a clean, low-distortion 500 Hz sine wave. Our breadboard results examining the frequency components of this output are shown in Fig. 8.49, while the SPICE results are shown in Figs. 8.50a and 8.50b.


PSpice v 10.5 N/A


Advantages: Good long-term frequency stability, excellent distortion Disadvantages: High parts count, added complexity File names: sine (IsSpice), pcm (SIMetrix), sine mc (Micro-Cap)

Colpitts Oscillator This circuit uses the resonance of an LC filter to switch an inverter, creating a square wave at the output of the inverter. The schematic is shown in Fig. 8.51. This arrangement provides better stability than the RC resonating oscillator, and has an amazingly small parts count.


Figure 8.47

245

End result of 500 Hz sine wave.

2.000

1

OUT in Volts

1.000

0

-1.000

-2.000

5.500M

6.500M

7.500M

8.500M

WFM.1 OUT vs. TIME in Secs Figure 8.48a

IsSpice result of 500 Hz sine wave.

9.500M

246

Chapter Eight

2.000

1

OUT in Volts

1.000

0

-1.000

-2.000

5.500M

6.500M

7.500M

8.500M

WFM.1 OUT vs. TIME in Secs Figure 8.48b

Figure 8.49

Micro-Cap result of 500 Hz sine wave.

Fourier results of 500 Hz sine wave after band pass filter.

9.500M


db

12000

9000

7500

6000

4500

10500

-20

3000

-10

1500

0

0

-30 -40 -50

db

-60 -70 -80 -90 -100 Figure 8.50a

IsSpice results of 500 Hz sine wave.

Figure 8.50b

Micro-Cap results of 500 Hz sine wave.

247

248

Chapter Eight

2 VCC

V1 5

1

V(1) IN

GND

L1 1M V(3) OUT

C2 1N

Figure 8.51

Schematic of Colpitts oscillator.

The output is a square-wave oscillation with a fixed frequency set by the LC time constant. The switching signal is driven by a sine-wave resonance between the inductor and the capacitor. An important feature of all SPICE packages is the type of estimation or curve-fitting mathematics available. All four of the packages used in this book default to the trapezoidal method. SIMetrix, Micro-Cap, and IsSpice offer the gear integration method as an option. For this case, transient analysis using the Gear integration option is more accurate. The results of this comparison are shown in Figs. 8.52, 8.53, and 8.54. Simulation note

PSpice does not offer the option of switching to Gear integration, instead a combination of trapezoidal and gear integration is always used. The model of the 74HC04 was taken from IsSpice because the version of PSpice did not offer an analog version of the 74HC04.

The 74HC04 is commonly used as a digital inverter. When building this model it is important to know if the model you are using is capable of providing analog results. The Micro-Cap model had an error in the interpretation of the parts specification. The 74HC04 model switched high at 30% of Vcc and low at 70% of Vcc as if the part had hysterics. This decreased the amplitude of the input sine wave and greatly increased the output frequency. This model of the 74HC04 may work well with digital inputs but is not correct for an analog response. The results of

3.000

16.00

2.000

12.00 OUT in Volts

IN in Volts


1.000

249

1

8.000

0

4.000

-1.000

0

2 5.000U

15.00U

25.00U

35.00U

45.00U

WFM.2 OUT vs. TIME in Secs Figure 8.52

16.00

IsSpice results of Colpitts oscillator (trapezoidal integration).

2.981 1

1.981

8.000

IN in Volts

OUT in Volts

12.00

980.9M

4.000

-19.08M

0

-1.019

2

5.000U

15.00U

25.00U

35.00U

WFM.1 IN vs. TIME in Secs Figure 8.53

IsSpice results of Colpitts oscillator (Gear integration).

45.00U

250

Chapter Eight

Figure 8.54

PSpice results of Colpitts oscillator.

the Micro-Cap simulation and the lab data are shown in Figs. 8.55 and 8.56. Table 8.4 gives a summary of the results. Schmitt Trigger Oscillator Like the Wein-bridge oscillator, the Schmitt trigger only needs a power supply of 5 to 15V to begin its oscillation. This entails that the maximum lead that the clock pulse can drive is in the 1 mA range. The oscillation is controlled by the RC time constant and the hysteretic native to the Schmitt trigger.


PSpice v 10.5 1.22


Advantages: Low part count, moderate frequency stability Disadvantages: Harmonic distortion not controlled File names: hcoms2 (IsSpice), hc04ps (PSpice), michmic (Micro-Cap)

The output of the Schmitt trigger charges the timing capacitor through the resistor creating the ramp signal. The ramp signal bounces back and forth between the positive and negative hysteresis point of the Schmitt trigger.

MICHCMS.CIR Temperature = 27

v(1) T

v(2) T Figure 8.55

Micro-Cap results of Colpitts oscillator.

Figure 8.56

Hardware results of Colpitts oscillator.

251

252

Chapter Eight

TABLE 8.4

Comparison between Simulators Comparison of results

Condition Frequency (kHz) Sine max (V) Sine min (V)

IsSpice

PSpice

Micro-Cap

Measured

80.97 3.06 1.9

82.5 3.04 1.94

494 5.58 –1.815

73.5 3.58 2.06

The most important characteristics of a good model are the positive and negative hysteresis points. Unfortunately, manufactures of the Schmitt trigger give a loose specification as to what these points are. Table 8.5 shows data taken from Radiation Hardened Product Databook (Harris Semiconductor 1993) on the CD4093BMS NAND Schmitt trigger. As you can see, it is unclear at what voltage level the hysteresis will center around or what the separation between the positive and negative switching points will be. A good model should hit the average of the specification, but it is unlikely that a part will perform in a similar manner. Realistically, the person who wrote the existing SPICE model wrote it for a single part. Any model that performs within the specification limits of the device could be considered as correct. This makes for some interesting results from the models included with the different EDA packages. Consider the CD4093B model contained in the IsSpice package. The circuit is shown in Fig. 8.57. The results are displayed in Fig. 8.58. The IsSpice model shows that the ramp voltage peaks at 3.7 V and has a minimum of 1.75 V. The maximum is below the extreme high specification of 4 V, and the minimum is above the extreme minimum specification of 1.4 V. This seems to line up pretty close to the data sheet, but the model’s hysteresis voltage is 1.95 V, and the specified maximum is only 1.6 V. The IsSpice version of the Schmitt trigger would work for some applications where the hysteresis voltage is not so critical, but for this application, the large hysteresis value caused a much lower frequency then expected. The IsSpice model’s frequency is 5.29 kHz.

TABLE 8.5

CD4093BMS NAND Schmitt Trigger Specifications

Parameter

Symbol

Conditions

Temperature

Min

Max

Units

Positive trigger threshold voltage

VP5V

Vdd = 5 V (Note 4)

−55 to +125

2.6

4

V

Negative trigger threshold voltage

VN5V

Vdd = 5 V (Note 4)

−55 to +125

1.4

3.2

V

Hysteresis voltage

VH5V

Vdd = 5 V (Note 4)

−55 to +125

0.3

1.6

V


V1 5

253

X1 CD4093B 3 2

V(2) OUT

4

V(4) RAMP R1 100K

C1 1.1N

Figure 8.57

Schmitt trigger oscillator.

In PSpice both a 7414 and a CD4093 were used. The 7414 is the digital model for the Schmitt trigger inverter. To use the digital device for an analog measurement, E sources (voltage-controlled voltage sources) were used as buffers. The schematic used for the PSpice model is shown in Fig. 8.59. The results are displayed in Fig. 8.60.

6.000

8.000 1

6.000

-2.000

RAMP in Volts

OUT in Volts

2.000

4.000

-6.000

2.000

-10.000

0

2

100.00U

300.0U

500.0U

TIME in Secs

Figure 8.58

Results of IsSpice Schmitt trigger.

700.0U

900.0U

254

Chapter Eight

Figure 8.59

PSpice using digital Schmitt trigger.

The results of the PSpice digital model using the 7414 show that the hysteresis voltage is within the specification limits at 790mV. The minimum positive threshold voltage is 1.65V, and model shows it at 1.69V, meeting this specification also. The only problem is the model does not meet the minimum negative threshold of 1.1V; the model shows it down at 0.9V. With the exception of the negative threshold, PSpice has a valid model of the Schmitt trigger. Unfortunately the negative threshold of the PSpice model causes this particular circuit to not report the proper duty cycle or frequency. The results of the PSpice digital model using the CD4093, shown in Fig. 8.60a, show that the ramp voltage peaks at 2.902V and has a

Figure 8.60

PSpice results of Schmitt trigger oscillator using a 7414.


255

6.0V

4.0V

2.0V

0V 0s V(U1A:J)

0.1ms V(U1A:B)

0.2ms

0.3ms

0.4ms

0.5ms

0.6ms

0.7ms

0.8ms

0.9ms

1.0ms

Time

Figure 8.60a

PSpice results of Schmitt trigger oscillator using a CD4093.

minimum of 1.898V. The hysteresis voltage is 1.0038V, all within the data sheet limits. Micro-Cap has a model of the CD4093A. The results of the simulation of the Micro-Cap model are shown as Fig. 8.61. The Micro-Cap results correlate very well to the data sheet. The hysteresis voltage is right at 1V, well within the 0.3 and 1.6 V limits. The positive threshold voltage is 3V, which is within the 2.6 and 4 V limits. The negative threshold voltage is 2 V, which is between the 1.4 and 3.2 V limits. PSpice’s and Micro-Cap’s models of the Schmitt trigger are clearly valid for the parameters evaluated in this comparison. Comparing the SPICE models with the measured data shown in Fig. 8.62 is difficult. The measured data shows the hysteresis voltage to be 250 mV. This does not meet the minimum specification limit of 300 mV. The minimum and maximum threshold voltages are close to 2.5 V, which does meet the specification limit. These measurements bring out a serious problem with this type of a circuit. The frequency of oscillation can change dramatically due to the wide variance of hysteresis voltage, causing difficulty in modeling the true performance.


PSpice v 10.5 204.11


Advantages: Low part count, good drive capability Disadvantages: Frequency of oscillation and duty cycle unpredictable because of poor tolerance of hysteresis voltage and voltage thresholds File names: hcoms2 (IsSpice), hc04ps (PSpice), michmic (Micro-Cap)

256

Chapter Eight

Figure 8.61

Micro-Cap results of Schmitt trigger oscillator.

LM111 Oscillator The LM111 makes an interesting oscillating circuit. The reference lead of the comparator changes as the comparator changes states. When the output lead of the comparator is low, it acts as a ground putting R16 and R6 in parallel, thus setting the reference of the comparator to its low value. C10 is then allowed to discharge through R17 and the output of the comparator until it reaches the low state of the reference pin. The comparator switches just after these pins match and essentially open circuits the output of the comparator. This causes R43 and R16 to be in parallel with R7, which causes the voltage at the reference pin to reach its high state. C10 is charged up through R43 and R17 until it matches the reference voltage; then the process repeats itself creating the oscillation. The circuit is shown in Fig. 8.63, and the outputs of the actual and simulated circuits are shown in Figs. 8.64, 8.65, 8.66, and 8.67, respectively. The simulation results are shown in Table 8.6.

TABLE 8.6

Simulation Results

Simulator

File name

Frequency (kHz)

Run time (s)

Hardware PSpice Micro-Cap IsSpice

NA LM111ps LM111mc LM111is

90.98 94.5 95.1 95.2

NA 0.55 0.656 0.55

Figure 8.62

Circuit board data from Schmitt trigger oscillator.

VCC 15.02

R43 4.64K 3

15.0

R16 98.4K 4

R7 98.4K

658F X2 COMP

2

V(2) HYST

+

5.00

_ GND

R6 98.1K

V(5) RAMP

V(4) SQUARE

5

C10 330P

Figure 8.63

out

9.36E-028 R17 21.3K

LM111 oscillator circuit.

257

258

Chapter Eight

Figure 8.64

LM111 oscillator measured results.

40.00

4.000

30.00

0

OUT in Volts

RAMP in Volts

1 8.000

20.00 2

-4.000

-8.000

x 30.33U < 5.000

10.000

0

x 19.83U < 5.000 5.000U

Freq=95.2KHz Figure 8.65

>

>

15.00U

25.00U

35.00U

TIME in Secs x = 10.50U y = 0

IsSpice LM111 oscillator simulated results.

45.00U


Figure 8.66

PSpice LM111 oscillator simulated results.

Figure 8.67

Micro-Cap LM111 oscillator simulated results.

259

260

Chapter Eight

Bibliography Kielkowski, Ron M. 1994. Inside Spice. New York: McGraw-Hill.. National Semiconductor. 1994. Linear Applications Handbook. Parker, Sybil, ed. 1984. Concise Encyclopedia of Science and Technology. New York: McGraw-Hill. Harris Semiconductor. 1993. Radiation Hardened Product Databook.

Chapter

9 Gate Drive Circuits

In the late 1970s, MOSFETs (metal oxide semiconductor field effect transistors) began replacing traditional bipolar transistors in many applications. Some of the improvements of the MOSFET over the bipolar transistor include very fast switching, absence of secondary breakdown characteristics, wide safe operating area, and high gain (International Rectifier 1993, application note 936A). Although MOSFETs are much easier to drive than bipolar transistors, attention must be paid to the drive circuitry to maximize the performance of these devices, as well as preventing outright device failure. There are several behavioral characteristics of the MOSFET that require the designer to pay careful attention to the gate drive circuitry. The MOSFET is a voltage-controlled device with theoretically no current draw on the gate. Realistically, there is a large nonlinear gate charge that must be overcome before the MOSFET is able to turn on fully. In order to realize maximum performance from the MOSFET, large instantaneous currents are required to keep switching times and power losses low. Another characteristic that constrains the design of the gate drive is the typical 20 V limit on the gate of the MOSFET. The silicon dioxide layer between the gate and the source regions can be easily penetrated, resulting in device failure, if the voltage between the gate and the source exceeds ± 20 V, even with low current (International Rectifier 1993, application note 937B). The excellent performance characteristics of MOSFETs are conditional on having well-designed gate drive circuitry. This chapter will aid the designer in modeling these circuits and utilizing MOSFETs to their fullest extent.

261


262

Chapter Nine

UC1846 50% Duty Cycle Gate Drive Circuit This circuit was used in Chapter 10 as part of a high-voltage and highcurrent doubler. This circuit can provide a fixed-frequency, fixed 50% duty cycle square wave capable of driving the gate of a power MOSFET. The circuit is shown in Fig. 9.1. It is powered by a 15 V supply connected to Vin and Vc (pins 15 and 13). A bypass capacitor is applied across the power of the IC to help minimize noise effects. The frequency of the output is set by resistor R5 and capacitor C3. The frequency is fixed at 50 kHz, with a 50% duty cycle. The noninverting terminal of the error amplifier is tied to the reference voltage (5.1V) and the inverting terminal is tied to ground, so that the oscillator controls the pulse termination. The output signal appears at AOut (pin 11). Our equivalent SPICE model of this circuit is shown in Fig. 9.2. A 100 M resistor (R4) has been added from the inverting terminal of the current sense pin to ground in order to help convergence and prevent “singular matrix” errors.

X5 1846 10 11 12

18 Ilim

Shdwn

Vref

Vin

C/S-

B Out

C/S+

Vc

E/A+

Gnd

E/A14 13

Comp CT

C3 2200P

Figure 9.1

C4 1U

V3 15

16 17

R1 10 1

A Out Sync

19 15

RT

R5 10K

Schematic of UC1846 fixed duty cycle gate drive circuit.

2

Gate Drive Circuits

263

X3 1846 7 8

R4 100MEG

9 10

11

V(12) CT

12

17 Ilim

Shdwn

Vref

Vin

C/S-

B Out

C/S+

Vc

E/A+

Gnd

E/A-

A Out

Comp CT

C1 2200P

Figure 9.2

Sync

C2 1U

R3 600

V1 15

2

V2 60

16

V(3) GATE

15

X2 IRF150

1

R1 10 3

4

14 13

RT

R2 10K

SPICE equivalent schematic of UC1846 MOSFET drive circuit.

SPICE tip

The “trick” described above is a good way to prevent singular matrix errors. Singular matrix errors usually occur because the node does not have a direct path to ground. When the 100 M resistor is added, this node has a direct path to ground and does not affect the operation of the circuit.

SPICE tip

In order to get this circuit to start, the UIC statement must be included in the .TRAN simulation. Flip-flops inside the model need the UIC directive in order to initialize properly. The SPICE engine has a difficult time determining the steady-state operating point of bistable circuit like the flip-flop without the UIC. Also, the ABSTOL OPTIONS parameter for current absolute current error tolerance has been changed from 1p to 1µ to aid convergence.

A voltage and a resistance (V2 and R3) were added to the drain of the MOSFET so the gate voltage characteristics would be accurate while the MOSFET was biased. The breadboard was constructed and two waveforms were measured. The waveforms are shown in Fig. 9.3: the top trace is the output pulse, and the bottom trace is the voltage on pin CT (pin 8). This circuit was also constructed in IsSpice and PSpice. The resulting waveforms are shown in Figs. 9.4, 9.5, and 9.6. The top waveform in the figure had a frequency of 44.05 kHz, and the bottom waveform had a frequency of 87.86 kHz.

264

Chapter Nine

Breadboard waveforms.

8.000

15.00

6.000

5.000

4.000

2.000

GATE in Volts

CT in Volts

Figure 9.3

1

-5.000

-15.00 2

0

-25.00

910.0U

930.0U

950.0U


IsSpice waveform results.

970.0U

990.0U

Gate Drive Circuits

265

V2 C2 1u U1

R5

1 2

1MEG

4 3 10 R1 9 8

10k C1

7 CT

2200p V

5 6 16

0 R4 1MEG

15

R3

N SOFT V VREF I

C V

600

0

V1

CS+ CS-

R2

SYNC

AOUT

11

10 V

COMP

BOUT

M1

60

Gate

RT CT

IRF150

14

EA+ EASHUTDOWN D N G UC1846 2 1

0

0

0 Figure 9.5

15

13

PSpice equivalent schematic of UC1846 MOSFET drive circuit.

Breadboard tip

You may note that the gate resistor (in this example, 10 ) is present in most of the MOSFET gate drives in circuits today. This resistor damps spurious oscillations that can occur in the gate voltage of power MOSFETs. The value of this resistor is a tradeoff between reducing switching losses and suppressing these spurious oscillations. Another resistor that is usually included is a 10K resistor from the gate of the MOSFET to ground. The gate charge can be large on some power MOSFETs,

15 V

10 V

5V

0V 900 us V( GATE)

91 0u s V( CT)

92 0u s

9 30u s

940u s

950 us

96 0u s

97 0u s

9 80u s

990u s

1000 us

Time

Figure 9.6

circuit.

Waveform results of PSpice equivalent schematic of UC1846 MOSFET drive

266

Chapter Nine

possibly causing the MOSFET to remain on even if the gate drive has been removed. This 10K resistor to ground allows any excess charge to dissipate safely from the gate in the event of this occurrence. In this sample circuit, the low state of UC1846 is low impedance, which allows us to exclude this resistor. SPICE tip

In order to run this schematic in PSpice, several nodes needed to have a fictitious connection added. Unlike the other Berkeley SPICE 3 based simulators used here, PSpice requires two connections at every node. When an input to an IC connects to a behavioral element or controlled source, in this case inside UC1846, PSpice considers that as input node floating. The other simulators do as well, but do not generate error messages. This, coincidently, has to do with the fact that PSpice is based on SPICE 2G.6 and not SPICE 3. The two-connections-at-every-node requirement was fixed in SPICE 3. To bypass the error message, large resistors should be connected from the offending node(s) to ground.


PSpice v 10.5

Advantages: Simple, high frequency capability, high output current, complementary outputs Disadvantages: None File names: 1846 (IsSpice), 1846 (PSpice)

555 Pulse-Shaped MOSFET Driver Proving once again the versatility of 555 timer IC, this circuit uses the ability of 555 to provide varying duty cycle shaped waveforms for MOSFETS. In certain applications of MOSFETs, when the device is turned on, current transfers from a freewheeling diode into the MOSFET. Parasitic inductances and high switching speeds can cause reverse recovery currents in the freewheeling diode that are high enough to destroy the device (International Rectifier 1993, application note AN-937B). For this reason, it is sometimes practical to delay the turn-on edge of the MOSFET in order to limit the reverse recovery current in the freewheeling diode. The pulse-shaping gate drive circuit is shown in Fig. 9.7. The input waveform is generated at voltage source V1. The reset is pulled high through a 4.7K resistor, and the trigger and threshold pins are tied together. This configuration causes the 555 to act as an inverter. The totem pole arrangement of the 2N2222A and 2N2907A transistors provides good current capability to drive the gate of the MOSFET. The gate of the MOSFET is modeled in this circuit by the 1000 pF capacitor. A bypass

Gate Drive Circuits

267

V(1) VCC

V(7) INPUT

V1 PULSE V(8) OUT

VC 12

C3 .1U

7

Q2 QN2222A

1

2

VCC 8

DISCHG

TRIG

D3 DN4148 Q1 QN2907A

C_FET 1000P

THRES 9

3

R1 2.2K

OUT CTRL

6

RESET 5

C1 330P

C2 .01U R2 4.7K V(1) VCC

Figure 9.7

Schematic of pulse-shaping gate drive circuit.

capacitor is applied across the power of the IC to help minimize noise effects (always a good idea when using switching ICs). When the input transitions low, the output of the 555 transitions high. Capacitor C1 begins to charge through resistor R1. This action provides for the delayed pulse. On turn-off, the voltage is discharged through diode D3 to ground, allowing for a fast switching time (which minimizes switching losses). Breadboard tip

If there is no input signal to this circuit, the default output is high. Also note that this circuit operates as an inverter.

SPICE tip

In order to assist convergence in this circuit, the UIC statement was included in the .TRAN simulation. This statement helps in circuits where a steady-state operating point may not exist, multiple stable operating points exist, or it is difficult for SPICE to determine the correct operating point.

The breadboard was constructed, and two waveforms were measured. These waveforms are shown in Fig. 9.8: the top trace is the output gate drive pulse, and the bottom trace is the input voltage to the 555. This circuit was also constructed in IsSpice, PSpice, and MicroCap. The resulting waveforms are shown in Figs. 9.9, 9.10, and 9.11, respectively.

268

Chapter Nine

Figure 9.8


SPICE tip

In order to run this schematic in PSpice, the DISCHG pin of the 555 model needed to be connected to a 0.01 µF capacitor. Leaving this pin floating produced an error. When this capacitor was added, the simulation results matched those of the other two simulators.

Generally, a linear SPICE primitive capacitor is not the best way to model the nonlinear capacitance of a MOSFET. The capacitance of the MOSFET’s gate is dependent on the gate-to-source voltage, and to a lesser extent, the drain-to-source voltage. However, the fixed capacitance used in this simulation is adequate for our purposes.


PSpice v 10.5

Micro-Cap v8.0 4

Advantages: Good drive current capability, reduced turn-on switch transient currents Disadvantages: Higher parts count than other solutions, slower turn-on that creates higher power dissipation in the MOSFET File names: puls sh (IsSpice), pls shp2 (PSpice), pls shp3 (Micro-Cap)

20.00

40.00

10.000


OUT in Volts

Gate Drive Circuits

269

20.00

2

-10.000

10.000

1

-20.00

0

0

30.00U

40.00U

50.00U

60.00U

70.00U


IsSpice waveform results.

Zero-to-100% Duty Cycle Driver Circuits where isolated gate drives operate at nearly full duty cycle or nearly zero duty cycle can be difficult to design. The transformer that provides isolation can easily saturate at full duty cycles. The circuit featured here uses a unique idea in order to circumvent this difficulty.

Figure 9.10

PSpice waveform results.

270

Chapter Nine

Figure 9.11

Micro-Cap waveform results.

This circuit is shown in Fig. 9.12. The input waveform is generated at voltage source VIN. The center-tapped transformer X2 saturates at turn-on, which provides turn-on charge to the output MOSFET through diode D2 and resistor R2. When the input waveform turns off, D2 is reverse biased and turn-off charge is provided to MOSFET X3, allowing for a fast turn-off. Capacitor C1 is the energy bank of the circuit. The transformer is wound on a 41005 toroid using F material. There are three turns for each winding (this example used 26 AWG trifilar twisted). The MOSFET load being driven is approximated as a 2000 pF capacitor.

V(10) OUT V(4) GATE1

10 X3 IRFF110

X2 XFMR-TAP 4 0

VIN PULSE

1

9

V(1) IND

X1 MAGF

D2 DN4148

C1 .01U 2

3

R1 33 V(9) IN

Figure 9.12

V(2) TP1

V(3) TP2

Schematic of zero-to-100% duty cycle gate drive circuit.

R2 4.7 8

C_LOAD 2000P

Gate Drive Circuits

271

Breadboard tip

If this circuit is operated at wide duty cycles, the 33 resistor will dissipate high power. Choose an adequately sized resistor.

SPICE tip

To model the transformer, an ideal center-tapped transformer is combined with a nonlinear core model for the F material. As this circuit counts on the saturation of the core, a SPICE primitive inductor will not work. By adding this nonlinear core model across the input of the center-tapped transformer, the magnetizing inductance and saturation characteristics of the core are realized.

In order to fully test the capabilities of this circuit, the input pulse was varied in duty cycle from 5% to 95%. The voltage source VIN used the following two statements: PULSE 0 15 0 20N 20N .5U 10U; 5% duty cycle PULSE 0 15 0 20N 20N 9.5U 10U; 95% duty cycle Fast switching circuits like this one can cause simulation problems. Discontinuities can create “time step too small” errors. In order to aid in convergence, the following statement was added to each of the simulators. .OPTIONS ITL4 = 500; this increases the number of transient iterations at each time point. You can also set RETOL=0.01. Figure 9.13 shows the waveform results of the breadboard at three different test conditions. The top picture shows the input pulse and the output pulse overlapped so the delay and turn-off ring can be examined. The middle picture shows the input (top) and output (bottom) waveforms when the duty cycle is 5%. The bottom picture shows the input (top) and output (bottom) waveforms when the duty cycle is 95%. This circuit was also constructed in IsSpice, PSpice, and Micro-Cap. The resulting waveforms are shown in Figs. 9.14, 9.15, and 9.16, respectively. Micro-Cap tip

While attempting to run this simulation in Micro-Cap, the following error was generated: “Floating point ‘Pow (0,–1.1376) Domain Error.’ ” This was traced to the use of the SPICE-compatible VALUE statement in an E element. The value statement is used to model equations dependent on other nodes or currents. The statement in question used the form Xˆ - Y. This was acceptable to IsSpice and PSpice, but not to Micro-Cap. This statement was rewritten in the equivalent form 1 / (X ˆ Y), which was accepted without error.

272

Chapter Nine


PSpice v 10.5 6.95


Advantages: Isolated driver, nearly infinite duty cycle range, very low delay, not frequency limited Disadvantages: High power dissipation in the 33 resistor at wide duty cycles, ringing on trailing edge File names: ful duty (IsSpice), duty2 (PSpice), duty 3 (Micro-Cap)

Drive waveforms into 200pF load

Input

Output

Input

Output

Figure 9.13


25.00

25.00

15.00

15.00

5.000

IN in Volts

OUT in Volts

Gate Drive Circuits

5.000 1 2

-5.000

-5.000

-15.00

-15.00

249.9U

250.1U

250.3U

250.5U

250.7U

70.00

20.00

50.00

0

30.00

IN in Volts

OUT in Volts

WFM.1 IN vs. TIME in Secs

1

-20.00

-40.00

10.000

2 -10.000

-60.00

242.0U

246.0U

250.0U

254.0U

258.0U

TIME in Secs

70.00

20.00 1

30.00

0

IN in Volts

OUT in Volts

50.00

10.000

-20.00

-40.00 2

-10.000

-60.00

242.0U

246.0U

250.0U

254.0U

TIME in Secs

Figure 9.14

IsSpice correlation waveform results.

258.0U

273

274

Chapter Nine

Figure 9.15

PSpice waveform results.

Gate Drive Circuits

Figure 9.16

Micro-Cap waveform results.

275

276

Chapter Nine

Bibliography International Rectifier. 1993. Hexfet Power MOSFET Designer’s Manual. Linear Technology. 1990. Linear Databook. Linear Technology. 1990. Linear Applications Handbook (Vol. I). Parker, Sybil, ed. 1984. Concise Encyclopedia of Science and Technology. New York: McGraw-Hill. Van Valkenburg, M. E. 1982. Analog Filter Design. New York: Harcort Brace Jovanovich College Publishers.

Chapter

10 Voltage Multiplier Circuits

As more and more electrical designs utilize the benefits in performance, cost, and size of ICs, demand for DC power in systems has been increasing. Unfortunately, sometimes the only power input available for these circuits is an AC waveform, with a spare winding from a transformer that must power the housekeeping supplies of the system. Adding a DC housekeeping supply adds cost and complexity, often a simpler and less expensive solution is to use a voltage multiplier circuit. Using these circuits requires fewer parts and provides a reasonable design alternative when circumstances permit their use. The information in this chapter will aid the designer in predicting the performance of these circuits and maximizing their capability and usefulness in the system.

AC-to-DC Voltage Doubler The conventional voltage doubler is a very simple, yet effective, method of creating a DC voltage from an AC voltage (Mimms 1983). The schematic for the conventional voltage doubler is shown in Fig. 10.1. The input is an AC waveform. This particular circuit was measured using both a square wave and a sine wave, with the circuit working using both input types. During the positive cycle, the AC waveform is rectified by diode D1 and capacitor C1. During the negative cycle, it is rectified by diode D2 and C2. This creates an effective DC voltage at the output terminals that is roughly 2 times the AC voltage minus the forward drop of the diode. Resistor R3 was added as a slight load. 277


278

Chapter Ten

V(1) OUT 1

+ C1 1uF

D1 DN4002

R3 100K

2

D2 DN4002

VIN PULSE 6

Figure 10.1

+ C2 1uF

Schematic of conventional doubler.

The actual SPICE model of this circuit is shown in Fig. 10.2. Note that there are two resistors in series with each of the capacitors, R1 and R2. These resistors model the approximate equivalent series resistance (ESR) of the tantalum capacitors in the circuit at the switching frequency. V(1) OUT 1

D1 DN4002

C1 1U 5

2

R1 10M

D2 DN4002

VIN PULSE

R3 100K

6

C2 1U 7

R2 10M

Figure 10.2

SPICE equivalent schematic of conventional doubler.

Voltage Multiplier Circuits

279

This circuit was built in the lab using 1N4002 1A 100V rated diodes with 1 µF tantalum capacitors. The input pulse was a square wave from –3 V to +3 V, with a frequency of 5 kHz at a 50% duty cycle. The PULSE statement in the SPICE model is shown below: PULSE −3 3 0.1U 0.1U 100U 200U The input pulse and the output DC voltage were measured using an oscilloscope. The result picture is shown in Fig. 10.3a. Unfortunately, the ripple on the breadboard was small enough to be swamped by the noise in the lab, and we were not able to make an accurate measurement. The IsSpice model result is shown in Fig. 10.3b. The top waveform is the output voltage and the bottom waveform is the input pulse. Breadboard tip

It is not necessary to use the 1N4002 rectifier for this circuit. When choosing a rectifier, remember that the diode reverse characteristics must be rated for 2 times the input voltage.

Figure 10.3a

Breadboard waveforms of input and output.

280

Chapter Ten

12.00

6.000 2

4.000

4.000

OUT in Volts

V(2,6) in Volts

8.000

x 9.501M < 5.034

>

2.000

0

0

-4.000

-2.000

1

9.100M

9.300M

9.500M

9.700M

9.900M


IsSpice waveforms of input and output.

Simulation tip

In order to allow the simulation to find the DC voltage, the simulation was run for 10 ms. Each of the simulations used initial conditions (IC) in order to shorten the simulation time. In this simulation, the capacitors were biased at an initial voltage of 2.75 V. In PSpice, this is accomplished by double clicking the capacitor and changing the attribute for IC; in Micro-Cap, by clicking the TEXT tool button and entering the command .IC v(2)=2.25 v(4)=2.25; and in IsSpice, by double clicking the capacitor and entering 2.5 in the IC field.

SPICE tip

The only real error source for the output voltage are the forward drop characteristics of this diode. Each of the three SPICE simulators has a model for the 1N4002 diode, with all of the simulators within about 100 mV of each other. The question is, which model is correct? The answer is they are probably all correct. The forward drop tolerance of a diode varies from lot to lot, from manufacturer to manufacturer, and from device to device. Table 10.1 shows the results of each of the three simulators along with the breadboard results.

TABLE 10.1

Output Voltage Comparison between SPICE and Breadboard Output voltage results summary (V)


PSpice v 10.5 5.078


Breadboard 5.21


281

The results of the Micro-Cap simulation are shown in Fig. 10.4, while the PSpice results are shown in Fig. 10.5.


PSpice v 10.5 6.46


Advantages: Low parts count Disadvantages: Current capability limited by source, ripple not as controlled as in other topologies, no AC/DC isolation, no regulation File names: con dou (IsSpice), con doub (PSpice), con dub (Micro-Cap)

Cascade Doubler By slightly altering the circuit in Fig. 10.1, we can attain the cascade doubler, which has the output characteristics of the conventional doubler. This circuit is shown in Fig. 10.6a. The SPICE equivalent circuit is shown in Fig. 10.6b. This circuit used the same 1N4002 diodes as the circuit in Fig. 10.1, the same 1µF capacitors, and the same 5 kHz ± 3 V input pulse. A 100K resistor acts as a load for the circuit. The breadboard results are shown in Fig. 10.7a, with the IsSpice results in Fig. 10.7b. The top waveform is the DC output voltage and the bottom waveform is the input pulse.

Figure 10.4


Figure 10.5

PSpice input and output waveforms. V(4) OUT 4

D1 DN4002

V(2) IN

R3 100K

C1 1uF 8

+

2

+ C2 1uF

D2 DN4002

VIN PULSE

Figure 10.6a

Schematic of a cascade doubler. V(4) OUT 4

V(2) IN

R1 10M

D1 DN4002 C1 1U 3

R3 100K 8

C2 1U

2

VIN PULSE

D2 DN4002

7

R2 10M

Figure 10.6b

282

SPICE schematic of a cascade doubler.


Figure 10.7a

Breadboard input and output waveforms.

13.00

8.000

9.000

4.000

5.000

OUT in Volts

IN in Volts

2

x 9.504M < 5.003

>

0

1.000

-4.000

-3.000

-8.000

1

9.100M

9.300M

9.500M



9.700M

9.900M

283

284

Chapter Ten

Figure 10.8


Breadboard tip

Note that in Fig. 10.6a, the capacitors are shown polarized. SPICE does not care one way or the other, but your breadboard tantalum or electrolytic capacitors will! Negative voltages on polarized capacitors will damage them just as easily as exceeding their rated voltage.

The results of the Micro-Cap and PSpice simulators are shown in Figs. 10.8 and 10.9, respectively. The results of the three simulators are tabulated and compared in Table 10.2.

Figure 10.9



TABLE 10.2

285

Output Voltage Comparison Between SPICE and Breadboard Output voltage results summary (V)


PSpice v 10.5 5.081


Breadboard 5.15


PSpice v 10.5 7.45


Advantages: Low parts count Disadvantages: Current capability limited by source, ripple not as controlled as in other topologies, no AC/DC isolation, no regulation File names: cas dou (IsSpice), cas doub (PSpice), cas dub (Micro-Cap)

Bridge AC-to-DC Doubler An improvement to the conventional and cascade doublers shown above is the bridge rectifying doubler. Instead of half wave rectification, a bridge doubler provides full wave rectification. The advantages of full wave rectification include less input impedance and a ripple voltage at twice the input frequency, which improves ripple-filtering capability. The schematic for the bridge doubler is shown in Fig. 10.10. The IsSpice equivalent schematic is shown in Fig. 10.11. This circuit uses the same 1N4002 diodes as the circuit in Fig. 10.1, the same 1 µF capacitors, and the same 5 kHz ± 3 V input pulse. Again, a 100K resistor acts as a load for the circuit. The breadboard results V(1) OUT 1

D1 DN4002

D2 DN4002

+ C1

1 uF

5

D3 DN4002

VIN PULSE

+ C2 1 uF

2

D4 DN4002

Figure 10.10

Schematic of a bridge rectifying doubler.

R3 100K

286

Chapter Ten

V(1) OUT 1

D1 DN4002

C1 1U

D2 DN4002 4

R3 100K

R1 10M

5

D3 DN4002 C2 1U

VIN PULSE

7 6

R2 10M D4 DN4002

Figure 10.11

SPICE schematic of a bridge rectifying doubler (with

ESR shown).

are shown in Fig. 10.12a, with the IsSpice results in Fig. 10.12b. The top waveform is the DC output voltage, and the bottom waveform is the input waveform. The results of the Micro-Cap and PSpice simulators are shown in Figs. 10.13 and 10.14, respectively. The results are tabulated and compared in Table 10.3.

Figure 10.12a



12.00

8.000

8.000

4.000

287

4.000

OUT in Volts

V(5,6) in Volts

1

x 9.501M < 5.004

>

0

0

-4.000

-4.000

-8.000

2

9.100M

9.300M

9.500M

9.700M

9.900M




PSpice v 10.5 5.84


Advantages: Medium parts count, lower impedance than conventional doublers, full wave rectification allowing for less filtering (ripple now at twice the switching frequency) Disadvantages: Current capability limited by source, ripple not as controlled as other topologies, no AC/DC isolation, no regulation File names: bridge1 (IsSpice), bridge2 (PSpice), bridge3 (Micro-Cap)

AC-to-DC Quadrupler By connecting two cascade doublers, we can generate a circuit that provides approximately 4 times the AC input voltage as a DC output voltage. The schematic for this circuit is shown in Fig. 10.15. The SPICE equivalent circuit is shown in Fig. 10.16. Notice in the SPICE circuit (Fig. 10.16), the 50 source impedance of the square-wave generator is modeled as resistor RSOURCE. The output voltage is dependent on the conduction angle through this resistor; therefore, for the measurements we will make on this circuit, it is important to include this resistance. The breadboard was constructed, and the output voltage was measured using five different loads. The results of the breadboard and of each of the three simulators were noted. The results of these measurements are shown in Table 10.4.

288

Chapter Ten

Figure 10.13


Figure 10.14


TABLE 10.3

Output Voltage Comparison between SPICE and Breadboard Output voltage results summary (V)


PSpice v 10.5 5.087


Breadboard 4.95


289

V(1) OUT 1

D2 DN4002 +

C5 1 uF

R3 LOAD

10

+ C1 1 uF

D1 DN4002

2

D4 DN4002

VIN PULSE

+ C2

C4 1uF 9

1 uF

6

+ D3 DN4002

Figure 10.15

Schematic of AC-to-DC quadrupler. V(1) OUT 1

C5 1U

D2 DN4002

C1 1U

5 10

R5 10M

R3 988K

4

D1 DN4002

R1 10M

RSOURCE 50 11 2

VIN PULSE R6 10M

3

9

C2 1U

D4 DN4002 C4 1U

7 6

R2 10M D3 DN4002

Figure 10.16

SPICE schematic of AC-to-DC quadrupler.

TABLE 10.4

Output Voltage Comparison between SPICE and Breadboard for Varying Loading Output voltage results summary (V)

Load ()

Breadboard (V)

IsSpice (V)

PSpice (V)

Micro-Cap (V)

9.88E+05 4.00E+05 2.18E+05 9.80E+04 5.49E+04

10.300 10.140 10.020 9.840 9.660

10.130 10.050 9.963 9.795 9.632

10.289 10.210 10.120 9.939 9.760

10.119 10.044 9.962 9.809 9.661

290

Chapter Ten

Quad AC-DC Circuit Results

Output [volts]

10.400 10.200

Breadboard

10.000

IsSpice

9.800

PSpice

9.600

Micro-Cap

9.400 5.49E+ 04

9.80E+ 04

2.18E+ 05

4.00E+ 05

9.88E+ 05

9.200

Load [ohms] Figure 10.17

DC output voltage results of breadboard and three simulators.

Breadboard tip

Using an oscilloscope to measure this circuit is tricky. The input signal and output voltage do not share a common ground. A characteristic of most oscilloscopes is that the grounds for each of the probes are tied together internally in the oscilloscope. This prevents plotting real-time waveforms on the same screen. If the grounds are tied together, through the oscilloscope probes or otherwise, this circuit will malfunction.

All of the data were collected into Excel and plotted. The resulting plot is shown in Fig. 10.17. Examining Fig. 10.17, it is interesting to note the Micro-Cap and IsSpice results are very similar, the PSpice results are slightly higher, and the breadboard data falls in between the simulations. Suspecting the culprit to be the diode models, these were examined more closely. A simple curve tracer circuit was created in each of the simulators. The IsSpice circuit is shown in Fig. 10.18. The diode on the left is the IsSpice model; the one on the right is the model Kielkowski created

D1 DN4002 2

V1 10

D2 RK4002 1

3

I1 V2 10U 10

4

I2 10U

IsSpice diode forward characteristics test circuit schematic.

Figure 10.18


550.0M

291

550.0M 2 1 4

470.0M

510.0M IsSpice in Volts

RK in Volts

510.0M

5 3

470.0M

430.0M

430.0M

390.0M

390.0M

32.00U

72.00U

112.0U

152.0U

192.0U

current in Amps Figure 10.19

Comparison of 1N4002 diode characteristics.

using measurements in his book on component modeling in SPICE (Kielkowski 1994). This identical test circuit was also constructed in PSpice and Micro-Cap in order to test the characteristics of the 1N4002 diode in the 10 to 200 µA region. In order to run the DC analysis, the current source was stepped from 10 µA to 200 µA in 10 µA increments. Also, a diode from the actual breadboard circuit was measured at the same points as the SPICE models and added to this graph. The plot of all five results is shown in Fig. 10.19. In Fig. 10.19, the traces, from top to bottom, are Ron Kielkowski’s model, the Micro-Cap model, the IsSpice model, the measured data from a 1N4002 from the quadrupler circuit, and the PSpice model. The measured data is the dotted line. All of the diode data is similar. The differences from the breadboard diode, as explained above, are largely due to manufacturing tolerances, different manufacturers, and lot-tolot variations. Ron Kielkowski’s model was taken from the data for an actual 1N4002 diode as well. Figure 10.19 is a good example of how differences in models do not indicate their correctness. It is easy to construct a SPICE-compatible diode model that will exactly trace the curve of the breadboard 1N4002; however it would still be valid only for the exact breadboard modeled with that diode. SPICE tip

Duplicating the results from three simulators and measured data on one grphics post processor plot can be tricky. Each of the three simulators is capable of writing output data directly to a text file. To send PSpice

292

Chapter Ten

data to an output file, use the .PRINT statement in the circuit netlist file. The results will be printed to a *.OUT file, which is directly readable by IntuScope. In Micro-Cap, in the ANALYSIS LIMITS pop-up box, click the button that enables placing the waveform in the numeric output file (*.TNO). This data can be read by any simple text editor and manipulated such that the post processor you are using can read it. By the same fashion, lab data can be entered into a text file and read. Most post processors also accept .CSV (comma separated value) data or CSDF (Common Simulation Data Format) data.


PSpice v 10.5 15.75


Advantages: Low parts count Disadvantages: Current capability limited by source, ripple not as controlled as other topologies, no AC/DC isolation, no regulation File names: quad1 (InSpice), quad2 (PSpice), quad3 (Micro-Cap) Diode File names: 1N4002 (IsSpice), PN4002 (PSpice), MN4002 (Micro-Cap) REAL4002 (measured results), quad res.xls (Excel spreadsheet with results)

AC-to-DC Octupler (× 8) The final circuit in this family is the AC-to-DC circuit shown in Fig. 10.20. This circuit will create a DC output at 8 times the AC value. This circuit is very flexible. By increasing the number of diode capacitor stages, very high DC voltages can be reached using a 50 function generator. Just as in the previous circuits of this chapter, if polarized capacitors are used; the polarity must be in the proper direction. Although the polarity is not shown in Fig. 10.20, the capacitors from left to right are all negative to positive. The pulse, as before, was ± 3 V square wave at 5 kHz with a 50% duty cycle. The resulting input waveform and output waveform from the breadboard are shown in Fig. 10.21. An AC-coupled expanded view of the output (and the ripple) is shown in Fig. 10.22. C1 1U

R1 10M

RSOURCE 50 5

4

C7 1U

R8 10M 8

61

C9 1U

R10 10M 7

16

C11 1U

R12 10M 14

19

7

2

VIN PULSE

D1 DN4002

D5 DN4002

D2 DN4002

D6 DN4002

D7 DN4002

3

1

R7 10M

D9 DN4002

D8 DN4002

D10 DN4002

15

91

C6 1U

R9 10M

1

C8 1U

18

R11 10M

C10 1U

21

R13 10M

C12 1U RLOAD 200K

Figure 10.20

AC-to-DC octupler circuit (× 8).

12

V(12) OUT


Figure 10.21

293


The load at this condition was 200 k. The results of the IsSpice simulations were very similar to the breadboard results, as shown in Fig. 10.23, especially the output ripple in Fig. 10.24. The octupler circuit was simulated in all three simulators at three different load conditions. The results of the ripple of the PSpice, Micro-Cap and SIMetrix simulations (at a load of 200 k) are shown in Figs. 10.25, 10.26, and 10.27, respectively. The results of the DC output voltage of all three simulators and the breadboard at several loading conditions are shown in Table 10.5. The measurements for the output ripple at a load of 200 k for each of the simulators, and the breadboard was also summarized in Table 10.6.


SIMetrix 5.1 134.84

PSpice v 10.5 251.45

Micro-Cap 64.625

Advantages: Low parts count Disadvantages: Current capability limited by source, ripple not as controlled as other topologies, no AC/DC isolation, no regulation File names: oct1 (IsSpice), oct2 (PSpice), oct3 (Micro-Cap), oct4 (SIMetrix)

294

Chapter Ten

Breadboard output waveform (expanded scale).

20.00

14.00

10.000

10.000

0

IN in Volts

OUT in Volts

Figure 10.22

2

6.000

-10.000

2.000

-20.00

-2.000 1 49.10M

49.30M

49.50M

TIME in Secs

Figure 10.23


49.70M

49.90M


19.46

OUT in Volts

19.26

19.06 2

18.86

18.66

49.10M

49.30M

49.50M


IsSpice output waveform (expanded).

Figure 10.25

PSpice output waveform (expanded).

49.70M

49.90M

295

296

Chapter Ten

Figure 10.26

Micro-Cap output waveform (expanded).

22 21.8 21.6 21.4

49

49.1

49.2

49.3

49.4

49.5

49.6

49.7

49.8

Time/mSecs

49.9 100uSecs/div

Figure 10.27

SIMetrix output waveform (expanded).

TABLE 10.5

Output Voltage Results Summary of Octupler AC-to-DC Circuit Output voltage results summary (V)

Load () 9.88E + 05 4.00E + 05 2.18E + 05

Breadboard (V)

SIMetrix (V)

IsSpice (V)

PSpice (V)

Micro-Cap (V)

20.2 19.75 19.31

23.99 22.49 21.82

20.172 19.683 19.071

20.569 20.027 19.406

20.144 19.686 19.110


TABLE 10.6

297

Output Ripple Results Summary of Octupler AC-to-DC Circuit Output voltage results summary (V)

Breadboard 155

IsSpice 159

SIMetrix 190

PSpice 86

Micro-Cap 35

Units mV pk-pk

High Voltage, High Current DC-to-DC Doubler Some of the doubler circuits presented in this chapter have limited current and voltage capabilities. The circuit presented here contains neither of those limitations. The complete breadboard schematic for this circuit is shown in Fig. 10.28. Note that the breadboard circuit utilizes an 1846 gate driver circuit described in detail in Chapter 11. The 1846 circuit generates a 0 to 15 V square-wave pulse at 50 kHz with a 50% duty cycle. This circuit is able to provide enough current to adequately drive the MOSFET. This particular configuration takes a 60 V DC signal and doubles the voltage to 120 V. The 60 V is switched by an IRF150 MOSFET and rectified by diode D1. The 60 V switched signal now appears at capacitor C1 superimposed on the 60 V signal of capacitor C2, thus generating a 120 V DC signal. Resistor R9 is a preload resistor that keeps the doubler from attempting to operate without a load. The equivalent SPICE model circuit of the breadboard is shown in Fig. 10.29. The most drastic difference is the UC1846 circuit has been Vcc C4 1u

V1 15

X3 UC1846 16 17

Shdwn

Ilim Vref

Vin

C/S-

B Out

C/S+

22 14

C3 2200p

E/A+

Gnd A Out

Comp

Sync

CT

RT

7

VAout Aout

R1 10

9

X1 IRF150

C1 6.8U Sec_Wind X2 XFMR-TAP

2

D3 1N5711

11

I_In

13

R6 10k

5

L1 620U

3

R2 .1 8 4

D11 DN5806

Figure 10.28

Vout

ISwitch

20

Vc

E/A-

Vout

D6 DN5806

VDrain

19

DC-to-DC doubler circuit schematic.

V2 60

C2 6.8U

R_PLOAD 192;220K

298

Chapter Ten

R_LDCR 50M V(6) OUT

10

L_LK 4U

V(4) DRAIN

D6 DN5806

X2 XFMR-TAP 9

X1 IRF150

V(1) VGATE

6

12

7

V(7) SEC_WIN

4

C1 6.8U 5

R_PLOAD 192;220K

R1 10 1

2

V1 PULSE

3

V(3) I_IN R2 .1

L1 620U

V2 60

C2 6.8U

8

R4 100MEG D11 DN5806

Figure 10.29

DC-to-DC doubler circuit SPICE equivalent schematic.

replaced with a pulsed voltage source. R4 (100 Meg Resistor) was added to the unconnected lead of the transformer to aid convergence. Leakage inductance and DCR of the main transformer were also added (L Lk and R LDCR). A 75 watt light bulb was used as the load in the breadboard. In order to model this light bulb, resistor R PLOAD was added. SPICE tip

To allow this circuit to converge, the ABSTOL setting in the OPTIONS line was modified from 1p (default) to 1U. This was required on all three simulation programs. The UIC statement was also used on the .TRAN line. Initial conditions were set on the output capacitors (60 V on each).

SPICE note

Although the DSR5700 high-speed rectifying diode was used in the breadboard, there was no SPICE model for it. The 1N5806 was used as a substitute in the SPICE model, even though the voltage rating of the 1N5806 is not optimal.

The voltage at the anode of diode D6 in Fig. 10.29 was compared to the gate voltage waveform, shown below in Fig. 10.30a. The voltage (a representation of the switch current) across the sense resistor R2 was


Figure 10.30a

299

Breadboard results (top, anode of D6; bottom, gate voltage).

also measured and is shown in Fig. 10.31. The results from the IsSpice simulations are shown in Figs. 10.30b and 10.32. The circuit was also simulated using PSpice and Micro-Cap. The PSpice results are shown in Figs. 10.33a and 10.33b, the Micro-Cap results are shown in Figs. 10.34a and 10.34b, and the SIMetrix results are shown in Fig. 10.35. It is interesting to note that in the Micro-Cap simulation the results do not show the avalanche of the MOSFET. SPICE tip

In the Micro-Cap simulation, the model for the IRF140 MOSFET was substituted for the IRF150 MOSFET. The IRF150 MOSFET model showed an unusually long turn-off time, which is believed to be in error. Run time summary (s)

IsSpice v 8.11 13.853

SIMetrix 5.1 4.75

PSpice v 10.5 7.39


Advantages: Medium parts count, good voltage and current range, good way to increase the voltage range of lab power supplies Disadvantages: No isolation from input to output , no automatic line and load regulation File names: Boost1 (IsSpice), Boost2 (PSpice), Boost3 (Micro-Cap), Boost4 (SIMetrix)

300

Chapter Ten

1

1 P l o t

v(12)

2 vaout

120 s v a o 80.0 u t, v ( 40.0 1 2 ) in 0 v o l t -40.0

1 2

4.91m

Figure 10.30b

Figure 10.31

4.93m


4.97m

IsSpice results (top, anode of D6; bottom, gate voltage).

Breadboard results (switch current).

4.99m


1 i_in

3.45

2 iswitch

34.5

s i 3.35 s 33.5 s w i i _ t 1 i c P n h 32.5 l i 3.25 i o n n t v a o m l p t 3.15 e 31.5 r e

3.05

301

2 1

30.5

4.91m

Figure 10.32

4.93m


4.97m

4.99m

IsSpice results (switch current ISwitch and source current I In).

20V

10V

0V

SEL>> -10V V(GATE) 100V

50V

0V

-40V 4.7217ms V(D4:A)

Figure 10.33a

4.7600ms

4.8000ms

4.8400ms

4.8800ms

4.9200ms

Time

PSpice results (top, anode of D6; bottom, gate voltage).

4.9600ms

5.0000ms

302

Chapter Ten

3.672V

3.600V

3.400V

3.200V

3.000V 4.78ms V(R3:2)

Figure 10.33b

4.80ms

4.82ms

4.84ms

4.86ms

4.88ms

4.90ms

4.92ms

4.94ms

4.96ms

4.98ms

5.00ms

Time

PSpice results (switch current) using an IRF150 model that avalanches.

Figure 10.34a Micro-Cap results (top, anode of D6; bottom, gate voltage).


303

Micro-Cap results (switch current). The Micro-Cap model does not avalanche.

Figure 10.34b

Y2

Y1

50

30 20 10

Secondary Winding / V

VGate / V

40

120

0

80 40 0 -40 -80 0.9

0.92

0.94

0.96


0.98

1

20uSecs/div

SIMetrix results (top, anode of D6; bottom, gate voltage).

Bibliography Kielkowski, Ron M. 1994. Inside Spice. New York: McGraw-Hill. Linear Technology. 1990. Linear Databook. Linear Technology. 1990. Linear Applications Handbook (Vol. 1). Mimms, Forrest M. III. 1983. Getting Started in Electronics. Parker, Sybil, ed. 1984. Concise Encyclopedia of Science and Technology. New York: McGraw-Hill. National Semiconductor. 1993. Power IC’s Databook. Sandler, Steven M. 1996. SMPS Simulation with SPICE. New York: McGraw-Hill. Van Valkenburg, M.E. 1982. Analog Filter Design. New York: Harcort Brace Jovanovich College Publishers.


Index

305 Copyright © 2006 by The McGraw-Hill Companies, Inc. Click here for terms of use.


AC analysis and DC bias point of circuit, 13 convergence solutions, 17 AEi Systems, LLC Power IC Model Library, 4 www.AENG.com/PSpice.asp, 1 analog circuits, 195. See also logic circuits

LM111, 134 positive DC to negative DC, 129 window comparator circuit, 168 Computer Analysis of Nonlinear Circuits Excluding Radiation (CANCER), 7. See also Simulation Program of Integrated Circuit Electronics Cox, F. L., 1

Berkeley SPICE 2 OPTIONS, 4 compatible programs, 12 Bessel–Thompson filter, 19 delay filter, 32 low pass with pulse shaper, 27, 33 with shape reformation, 35 modification of, 37 time delay of, 30 binary decoder circuit, 199–205 BJT transistors Darlington configuration, 137 boost topology, 113. See also power factor and benefits, 113 buck regulator circuit 1524A buck regulator, 82 duty cycle, 83 Butterworth filter, fourth-order band pass filter, 25 breadboard configuration of, 21 high pass filter, 24, 25 low pass filter, 4, 19–24 Butterworth low pass oscillator, 216 hardware results of, 220 no-offset low pass oscillator, 228

DC analysis DC operating point, 11–13, 14, 16, 22. See also time domain analysis and convergence solutions, 15 iteration limit, 11 design process, 1. See also Moore’s law analog and mixed-mode, 3 computer simulation as tool, 1 lab breadboard, 2 SPICE simulation as tool, 2 digital circuits building blocks of, 195 digital logic IC, 236 filter circuits, 19 duty cycle driver zero duty, 269

CANCER. See Simulation Program of Integrated Circuit Electronics cascade doubler circuit, 281 Chebyshev circuit, 44 high pass filter, 50, 52 low pass filter, 48 MathCAD file, 39, 44, 46 Chebyshev filter, 39. See also Butterworth filter, fourth order circuit simulation, 2, 3, 7 clamping circuit, 176 class AB amplifier, 160 Colpitts oscillator circuit gear integration, 249 LC filter resonance, 244 trapezoidal integration, 249 comparator converter, 161. See also window detector circuit

effective series resistance (ESR), 55 electromagnetic interference filter converter stability, 55 filter model, 54 for flyback topology, 55 reduce conducted and reflected emissions, 52 electronic circuits time-variant signal/AC signal, 215 electronic design automation (EDA) tool, 1 electronic load circuits, 119–53 and BJT transistors, 137 comparator converter, 129 electronic load, 119 power section of, 119–29 using power BJT transistors, 137–41 electronic load reference and pulse load, 133 load power stage, 120 EMI. See electromagnetic interference filter filter circuits, 19–59 Bessel–Thompson delay low pass filter, 27, 33 Butterworth high/low pass filter, 19, 24

307

308

Index

filter circuits (Cont.) Chebyshev band pass filter, 39 EMI filter, 52 inverted Bessel–Thompson delay high pass filter, 37 IsSpice filter response, 22 Micro-Cap AC filter response, 22 PSpice AC filter response, 23 flyback converter, 112. See also power converter circuits discontinuous mode flyback converter, 114 single phase, 114 two-phase discontinuous, 114, 115 FOURIER command, 241 fourth-order Butterworth filter band pass filter, 25 breadboard configuration of, 21 high pass filter, 24, 25 low pass filter, 19, 20 gate drive circuits, 261–72 and gate drive circuitry, 261 pulse-shaping, 266 UC1846, 50 zero-to-100% duty cycle, 270 hex inverter oscillator, 222 high pass filter Chebyshev high pass filter, 52 fourth-order Butterworth filter, 24, 25 inverse Bessel–Thompson, 38 instrumentation circuits, 143–93 555 missing-pulse detector, 148 555 timer IC, 143 class AB amplifier, 160 operational amplifier adder ICs, 154 polarity gain circuit, 186 voltage clamping circuit, 176 window detector circuit, 161 integrated circuits (ICs), 7, 68, 113. See also Simulation Program of Integrated Circuit Electronics; three-terminal regulator DC-to-DC applications, 68 MOSFET driver logic, 68 inverted Bessel–Thompson delay, high pass filter, 37, 38 IsSpice. See also Simulation Program of Integrated Circuit Electronics attenuation results, 58

Chebyshev high pass filter, 52 description of, 7–17 filter response, 22 model PSW1 switch, 134 response of, 35 nonlinear core model, 56 optimizer, 67 Kielkowski, R., 1, 3, 8, 12, 222, 291 latching circuit, 205–208 linear circuits, 83 LM117 three-terminal linear regulator, 62 logic circuits, 195–214 binary decoder circuit, 199 set-reset latch, 205 staircase generator, 208 low drop-out linear regulator, 94 MathCAD file, 46 metal oxide semiconductor field effect transistors, 1, 261 as a source follower, 94 gate drive circuitry, 261, 263 MOSFET driver 555 pulse-shaped, 266 characteristics of, 261 Micro-Cap description of, 7–17 Mimms, F. M., 277 missing-pulse detector, 148 555 one-shot timer circuit, 144 with 555 IC, 143, 148, 266 Moore’s law, 1 MOSFET. See metal oxide semiconductor field effect transistors multiple output power converters and regulation requirements, 93 Nagel, L., 7 Newton–Raphson algorithm, 10, 12 and iteration, 12 operating point analysis, 22. See also DC analysis operational amplifiers (op-amp), 1, 33, 61. See also simulation adder circuit, 154 and power supplies, 129

Index

.OPTION parameters, 10, 13. See also Simulation Program of Integrated Circuit Electronics oscillating circuits, 215 555 timer oscillator, 215, 216 LM111 oscillator, 256 Parker, S., 215 phase and gain margins, 97. See also Simulation Program of Integrated Circuit Electronics polarity gain circuit, 186 adjustment circuitry output of, 192 power converter, 3, 19 DC-to-DC converter, 68 discontinuous mode flyback converter, 114 ripple attenuation, 55 turn-on characteristics, 55 power converter circuits, 61–117 buck regulator circuit, 1524A, 82 LM117 three-terminal linear regulator, 61 low drop-out regulator, 93–99 SG1524 buck regulator, 84 STR6600 hybrid IC, 106 transistor models, 74 UA723 hysteretic buck regulator, 73 power factor, 112. See also flyback converter correction circuitry, 112 boost topology, 113 PSpice. See also Simulation Program of Integrated Circuit Electronics AC filter response, 23, 30 description of, 7–17 enhanced version of SPICE2G.6, 8 model response, 31 simulation, Sbreak, 134 pulse-shaping modification, 33 quasi-resonant converter and SPICE model, 108 flyback converter, 106 circuit schematic for, 107 Fourier transform of, 241 switching losses, 106 resonance, 215 resonator/oscillator circuits, 215–60

309

Butterworth low pass oscillator, 216 Butterworth no-offset low pass oscillator, 228 Colpitts oscillator circuit, 244 hex inverter oscillator, 222 LC filter, 215 Schmitt trigger oscillator, 250 sine-wave oscillator, 236 Rohrer, R., 7 Sallen–Key circuit, 46, 49. See also Chebyshev filter Sandler, S. M., 3, 14 schematic editor program, 9. See also simulators Schmitt trigger oscillator, 250, 253 semiconductor devices, 12, 68. See also simulation; Simulation Program of Integrated Circuit Electronics set-reset latch. See also binary decoder circuit circuitry representation of, 205 SG1524 buck regulator, 83 simulated turn-on of, 92 SIMetrix description of, 7–17 results, 95 simple switcher IC, 78S40, 68–70. See also power converter circuits simulation approaches, 10 convergence problems, 14 and .OPTIONS parameters adjustments, 14 solutions, 16 for circuit simulation, 3 simulation results, 36 .TRAN and .OPTIONS settings, 3 Simulation Program of Integrated Circuit Electronics (SPICE), 1, 7 basic overview, 10 Gaussian elimination, 10 modules utilized, 8 graphics waveform postprocessor, 9 schematic capture program, 8 simulator, 9 text editor, 9 Newton–Raphson algorithm, 10 nodal equations matrix, 10 power conversion circuits, 61 two operating point analysis, 21

310

Index

simulators, 9 analyses performed by, 14 Berkeley SPICE 2G.6, 9 Berkeley SPICE 3F.5, 8 FORTRAN, 7 types and data acquisition, 14 sine-wave oscillator harmonic neutralized, 236 square wave pulses, 236 software manufacturers, 8 Catena (SIMetrix), 8 Intusoft (IsSpice), 8 Micro-Cap V (Micro-Cap), 8 OrCAD (PSpice), 8 SPICE models and hardware behavior, 2 SPICE netlist, 10 SPICE program, 3, 11 final line, 11 SPICE simulators optimizer function of, 66 SPICE syntax, 9 and tutorial, 10 SPICE versions, 7 SPICE 2, 7 SPICE 2G.6, 7, 9, 266 SPICE 3, 266 SPICE-based simulation software, 1, 3 circuit modeling, 2 Monte Carlo analysis, 1 postsimulation waveform processing, 1 schematic entry, 1 staircase generator circuit, 208, 209 STR6600 hybrid IC, 106 switching circuits, 83 convergence difficulties, 13 transient models, 83 three-terminal regulator, 61 C COMP capacitor, 65

Linear Databook, 63 stability measurement setup, 62 TL431 regulator circuit, 94, 97 time domain analysis (transient analysis), 10, 12, 87 and convergence, 13 transient simulation parameters, 13 transistors, 1 trapezoidal method, 248 and gear integration, 70, 249 UA723 buck regulator output ripple, 74 with ESR and DCR, 79 voltage clamping circuit, 176 voltage multiplier circuits, 277–303 bridge AC-to-DC doubler full wave rectification, 285 bridge rectifying doubler, 286 cascade doubler circuit, 281 voltage doubler, 277 AC-to-DC voltage doubler, 277 waveform postprocessor, 9 window comparator circuit behavior of, 168, 169 window detector circuit, 161 XSPICE mixed-mode simulation capability, 1, 8 ZCS-type circuit, 106 zener diode, 176, 183. See also voltage clamping circuit forward drop of diode, 230 zero-current switching (ZCS), 106. See also quasi-resonant converter STR6600 hybrid IC, 106

ABOUT THE AUTHORS STEVEN M. SANDLER is the founder of AEi Systems, LLC, the world leader in SPICE modeling and worst case circuit analysis since 1995. He has developed and taught courses at Motorola University and has published many books and articles on circuit simulation for McGraw-Hill and Power Electronics, PCIM, and PEIN magazines. CHARLES HYMOWITZ is the Managing Director of AEi Systems, LLC, and has over 25 years of experience in the EDA software and analog simulation industries. From 1988 to 1998 he helped guide Intusoft, a leading EDA corporation, as the Vice President of Product Development. He was the editor of the Intusoft newsletter, and is the co-author/editor of the books Simulating with SPICE, The SPICE Cookbook, and The SPICE Applications Handbook.

311 Copyright © 2006 by The McGraw-Hill Companies, Inc. Click here for terms of use.

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