Solder joint reliability

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Volume 16 Number 2 2004

ISBN 0-86176-966-X

ISSN 0954-0911

Soldering & Surface Mount Technology Solder joint reliability Guest Editor: Professor S.W. Ricky Lee

www.emeraldinsight.com

ISSN 0954-0911

Soldering & Surface Mount Technology Volume 16 Number 2, 2004 Solder joint reliability Guest Editor: Professor S.W. Ricky Lee

Contents

2 Access this journal online

69 Failure analysis of lead-free solder joints for high-density packages

3 Abstracts & keywords

John Lau, Dongkai Shangguan, Todd Castello, Rob Horsley, Joe Smetana, Nick Hoo, Walter Dauksher, Dave Love, Irv Menis and Bob Sullivan

5 French abstracts 7 German abstracts 9 Editorial 10 Contributors

77 Thermal cycling reliability of lead-free chip resistor solder joints Jeffrey C. Suhling, H.S. Gale, R. Wayne Johnson, M. Nokibul Islam, Tushar Shete, Pradeep Lall, Michael J. Bozack, John L. Evans, Ping Seto, Tarun Gupta and James R. Thompson

13 Long term mechanical reliability with lead-free solders W.J. Plumbridge

21 Comparison of solder ball shear strengths for various nickel platings on the bond pads of a PBGA substrate Eric C.C. Yan, S.W. Ricky Lee and X. Huang

88 Internet commentary 91 Book reviews 93 Company profile

27 Strategies for improving the reliability of solder joints on power semiconductor devices Guo-Quan Lu, Xingsheng Liu, Sihua Wen, Jesus Noel Calata and John G. Bai

41 CBGA solder joint thermal fatigue life estimation by a simple method T.E. Wong, C.Y. Lau and H.S. Fenger

46 Reliability testing and data analysis of lead-free solder joints for high-density packages John Lau, Nick Hoo, Rob Horsley, Joe Smetana, Dongkai Shangguan, Walter Dauksher, Dave Love, Irv Menis and Bob Sullivan

93 Association news 97 New products 103 Industry news 109 Exhibitions and conferences 112 Appointments 112 International diary

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Abstracts & keywords

Long term mechanical reliability with lead-free solders

CBGA solder joint thermal fatigue life estimation by a simple method

W.J. Plumbridge

T.E. Wong, C.Y. Lau and H.S. Fenger

Keywords Reliability, Reliability management, Solders, Modelling

Keywords Soldering, Joining processes, Fatigue, Thermal properties of materials

The decision to move to lead-free solders has been made, but processing and performance challenges remain. This paper considers the transition in terms of performance, with particular emphasis on long term, high reliability applications. Comparison of key mechanical properties indicates generally beneficial outcomes of the transition to lead-free alloys, although there is a lack of understanding surroundingânomalous’’ observations, such as the effects of the bismuth. The lower melting point of Sn-Zn-Bi alloys, together with their comparable mechanical properties, provide further impetus to address their shortcomings during processing. Some lead-free alloys, such as Sn-0.5Cu, are susceptible to tin-pest formation following prolonged exposure below 138C, and this possibility remains for the more concentrated Sn-3.8Ag-0.7Cu alloy.

A simple analysis method was developed to determine the fatigue life of a ceramic ball grid array (CBGA) solder joint when exposed to thermal environments. The solder joint consists of a 90Pb/10Sn solder ball with eutectic SnPb solder on both top and bottom of the ball. A closed-form solution, based on the calculation of the equilibrium of the displacements within the electronic package assembly, was first derived in order to calculate the solder joint strains during temperature cycling. In the calculation, an iteration technique was used to obtain a convergent solution for the solder strains, and the elastic material properties were used for all the electronic package assembly components except for the solder materials. A fatigue life prediction model was established.

Comparison of solder ball shear strengths for various nickel platings on the bond pads of a PBGA substrate Eric C.C. Yan, S.W. Ricky Lee and X. Huang

John Lau, Nick Hoo, Rob Horsley, Joe Smetana, Dongkai Shangguan, Walter Dauksher, Dave Love, Irv Menis and Bob Sullivan

Keywords Product reliability, Solders, Shear strength, Semiconductor technology

Keywords Solders, Product reliability, Printed-circuit boards

This paper presents an experimental study to assess the reliability of solder ball attachment to the bond pads of PBGA substrate for various plating schemes. The basic structure of the under bump metallisation is Cu/Ni/Au. Three different kinds of electroless plating solutions are used to deposit the Ni layer, namely, Ni-B, Ni-P (5 per cent), and Ni-P (10 per cent). Also, conventional electrolytic Ni/Au plating is performed to provide a benchmark. After solder ball attachment, mechanical tests are conducted to characterize the ball shear strength for comparison. Furthermore, some specimens are subjected to multiple reflows to investigate the thermal aging effect.

Temperature cycling tests, and statistical analysis of the results, for various high-density packages on printed-circuit boards with Sn-Cu hot-air solder levelling, electroless nickelimmersion gold, and organic solder preservative finishes are investigated in this study. Emphasis is placed on the determination of the life distribution and reliability of the lead-free solder joints of these high-density package assemblies while they are subjected to temperature cycling conditions. A data acquisition system, the relevant failure criterion, and the data extraction method will be presented and examined. The life test data are best fitted to the Weibull distribution. Also, the sample mean, population mean, sample characteristic life, true characteristic life, sample Weibull slope, and true Weibull slope for some of the highdensity packages are provided and discussed. Furthermore, the relationship between the reliability and the confidence limits for a life distribution is established. Finally, the confidence levels for comparing the quality (mean life) of lead-free solder joints of high-density packages are determined.

Strategies for improving the reliability of solder joints on power semiconductor devices Guo-Quan Lu, Xingsheng Liu, Sihua Wen, Jesus Noel Calata and John G. Bai Keywords Soldering, Joining processes, Stress (materials), Semiconductor devices

Soldering & Surface Mount Technology 16/2 [2004] 3–4 Abstracts & keywords # Emerald Group Publishing Limited [ISSN 0954-0911]

Reliability testing and data analysis of lead-free solder joints for high-density packages

In this paper, some strategies taken to improve the reliability of solder joints on power devices in single device and multi-chip packages are presented. A strategy for improving solder joint reliability by adjusting solder joint geometry, underfilling and utilization of flexible substrates is discussed with emphasis on triple-stacked solder joints that resemble the shape of an hourglass. The hourglass shape relocates the highest inelastic strain away from the weaker interface with the chip to the bulk region of the joint, while the underfill provides a load transfer from the joints. Flexible substrates can deform to relieve thermo-mechanical stresses. Thermal cycling data show significant improvements in reliability when these techniques are used. The design, testing and finite-element analyses of an interconnection structure, termed the Dimple-Array Interconnect, for improving the solder joint reliability is also presented.

Failure analysis of lead-free solder joints for high-density packages John Lau, Dongkai Shangguan, Todd Castello, Rob Horsley, Joe Smetana, Nick Hoo, Walter Dauksher, Dave Love, Irv Menis and Bob Sullivan Keywords Solders, Product reliability, Joining processes, Printed-circuit boards Failure analyses of the lead-free and SnPb solder joints of high-density packages such as the plastic ball grid array and the ceramic column grid array soldered on SnCu hot-air solder levelling electroless nickel-immersion gold or NiAu, and organic solderability preservative Entek printed circuit boards are presented. Emphasis is placed on determining the failure locations, failure modes, and intermetallic compound composition for these high-density packages’ solder joints after they have been through 7,500 cycles of temperature cycling. The present results will be compared

[3]

Abstracts & keywords Soldering & Surface Mount Technology 16/2 [2004] 3–4

with those obtained from temperature cycling and finite element analysis.

Thermal cycling reliability of lead-free chip resistor solder joints Jeffrey C. Suhling, H.S. Gale, R. Wayne Johnson, M. Nokibul Islam, Tushar Shete, Pradeep Lall, Michael J. Bozack, John L. Evans, Ping Seto, Tarun Gupta and James R. Thompson Keywords Soldering, Joining processes, Product reliability The solder joint reliability of ceramic chip resistors assembled to laminate substrates has been a long time

[4]

concern for systems exposed to harsh environments. In this work, the thermal cycling reliability of several 2512 chip resistor lead-free solder joint configurations has been investigated. In an initial study, a comparison has been made between the solder joint reliabilities obtained with components fabricated with both tin-lead and pure tin solder terminations. In the main portion of the reliability testing, two temperature ranges ( 40-1258C and 401508C) and five different solder alloys have been examined. The investigated solders include the normal eutectic Sn-Ag-Cu (SAC) alloy recommended by earlier studies (95.5Sn-3.8Ag-0.7Cu), and three variations of the lead-free ternary SAC alloy that include small quaternary additions of bismuth and indium to enhance fatigue resistance.


Fiabilite´ mećanique a` long terme avec les brasures sans plomb W.J. Plumbridge Mots-cle´s Gestion de la fiabilite´, Brasures, Modelage La dećision de passer aux brasures sans plomb a e´te´ prise, mais le traitement et la performance repre´sentent toujours un de´fi. L’article que voici conside`re la transition du point de vue de la performance, en mettant surtout l’accent sur les applications de fiabilite´ e´leveé a` long terme. La comparaison des proprie´te´s mećaniques principales indique d’une manie`re geńe´rale que la transition vers les alliages sans plomb produit des re´sultats avantageux, bien qu’il subsiste un manque de compre´hension concernant les observations ‘‘anormales’’, comme par exemple les effets du bismuth. En raison du point de fusion re´duit des alliages Sn-Zn-Bi et de leurs proprie´te´s mećaniques comparables, les chercheurs sont encourage´s a` examiner plus a` fond leurs imperfections au cours du traitement. Certains alliages sans plomb, comme le Sn-0,5Cu, sont susceptibles de former des maladies de l’e´tain suivant l’exposition prolongeé en-dessous de 138C; cette possibilite´ existe aussi avec l’alliage Sn-3,8Ag-0,7Cu plus concentre´. Il n’est plus viable de se fier uniquement aux essais empiriques et il est extreˆmement urgent de mieux comprendre le comportement des brasures en tant que base pour les me´thodes pheńomeńologiques de pre´diction de la dureé de vie et de la conception.

Comparaison de la re´sistance au cisaillement des billes de soudure pour divers nickelages sur les pastilles de soudure d’un support PBGA Eric C.C. Yan, S.W. Ricky Lee et X. Huang Mots-cle´s Fiabilite´ des produits, Brasures, Re´sistance au cisaillement, Technologie des semi-conducteurs

Soldering & Surface Mount Technology 16/2 [2004] 5–6 French abstracts # Emerald Group Publishing Limited [ISSN 0954-0911]

L’article que voici pre´sente une e´tude empirique qui visait a` e´valuer la fiabilite´ de la fixation des billes de soudure aux pastilles de soudure des supports PBGA, pour divers proce´de´s de placage. La structure de base de la me´tallisation de bosse (under bump metallization) est le Cu/Ni/Au. Trois types diffe´rents de solutions de placage sans courant sont utilise´s pour de´poser la couche de Ni, a` savoir Ni-B, Ni-P (5%), et Ni-P (10%). Le placace e´lectrolytique Ni/Au conventionnel a e´galement lieu afin de fournir un point de repe`re. Apre`s la fixation de la bille de soudure, des essais mećaniques sont reálise´s pour caracte´riser la re´sistance au cisaillement de la bille, afin de pouvoir proce´der a` des comparaisons. De plus, quelques spećimens sont soumis a` des fusions multiples afin d’examiner l’effet du vieillissement thermique. Les re´sultats des essais re´ve`lent que, par rapport au placage Ni-P sans courant, le placage Ni-B sans courant peut entraıˆner une meilleure re´sistance au cisaillement pour la bille de soudure. C’est cependant le placage e´lectrolytique conventionnel qui produit la re´sistance au cisaillement la plus e´leveé pour la bille de soudure. Dans la plupart des cas examine´s, les fusions multiples semblent re´duire le´ge`rement la re´sistance au cisaillement de la bille de soudure. En plus des essais de re´sistance au cisaillement de la bille de soudure, la microscopie e´lectronique par balayage est reáliseé afin d’inspecter la coupe transversale et la surface de rupture des spećimens teste´s. A` partir de l’analyse des de´faillances, certaines caracte´ristiques sont identifieés pour diverses me´thodes de placage au nickel.

Strate´gies permettant d’ame´liorer la fiabilite´ des joints de brasage des dispositifs de puissance a` semi-conducteurs Guo-Quan Lu, Xingsheng Liu, Sihua Wen, Jesus Noel Calata et John G. Bai Mots-cle´s Contrainte Dispositifs

Brasage, Proce´de´s d’assemblage, (Mate´riaux), a` semi-conducteurs

L’article que voici pre´sente certaines strate´gies permettant d’ame´liorer la fiabilite´ des joints de brasage des dipositifs de puissance dans les boıˆtiers a` dispositif simple et multipuce. Il discute une strate´gie permettant d’ame´liorer la fiabilite´ des joints de brasage qui ajuste la geóme´trie des joints de brasage, au moyen de l’underfilling, et qui utilise des supports souples; il met l’accent sur les joints de brasage triple-empile´s qui ont la forme d’un sablier. La forme de sablier e´loigne la contrainte ine´lastique la plus e´leveé de l’interface la plus faible avec la puce, pour la placer dans la re´gion volumique du joint, tandis que l’underfill e´loigne la charge des joints. Les supports souples peuvent se de´former pour re´duire les contraintes thermomećaniques. Les donneés sur la sollicitation aux chocs thermiques indiquent que l’utilisation de ces techniques entraıˆne de fortes ame´liorations de la fiabilite´. L’article traite e´galement du design, des essais et des analyses par e´le´ments finis d’une structure d’interconnexion, appeleé ‘‘Dimple-Array Interconnect’’, qui permet d’ame´liorer la fiabilite´ des joints de brasage.

E´valuation de la re´sistance a` la fatigue thermique des joints de brasage CBGA au moyen d’une simple me´thode T.E. Wong, C.Y. Lau et H.S. Fenger Mots-cle´s Brasage, Proce´de´s d’assemblage, Fatigue, Proprie´te´s thermiques des mate´riaux Une simple me´thode d’analyse fut mise au point; elle permet de de´terminer la re´sistance a` la fatigue des joints de brasage des CBGA (ceramic ball grid array – re´seau en grille a` billes ce´ramiques), lorsqu’ils sont expose´s a` des environnements thermiques. Le joint de brasage se compose d’une bille de brasage 90Pb/10Sn, avec une soudure SnPb eutectique sur la face supe´rieure ainsi que sur la face infe´rieure de la bille. La de´faillance du joint de brasage se produit a` la soudure eutectique. Une solution de forme close, fondeé sur le calcul de l’e´quilibre des de´placements a` l’inte´rieur du boıˆtier e´lectronique, fut tout d’abord de´riveé afin de calculer les contraintes affectant les joints de brasage au cours de la sollicitation aux chocs thermiques. Le calcul utilise une technique ite´rative pour obtenir une solution convergente pour les contraintes affectant les soudures; les proprie´te´s e´lastiques des mate´riaux furent utiliseés pour tous les composants des encapsulages e´lectroniques, sauf pour les mate´riaux de soudure qui utilisaient des proprie´te´s e´lastiques-plastiques. Un mode`le de pre´diction de la re´sistance a` la fatigue fut ensuite e´tabli; celui-ci provenait d’une formule de´riveé de manie`re empirique et fondeé sur une modification de la theórie de la fatigue de Manson-Coffin. Les re´sultats des essais sur les CBGA, fournis par Motorola et combine´s aux contraintes de soudure de´riveés, furent utilise´s pour calibrer le mode`le de pre´diction de la re´sistance propose´. Dans le processus de calibration du mode`le, les re´sultats des essais sur les CBGA a` 255 broches et a` 304 broches, qui furent cycle´s entre 08C et 1008C ou 408C et 1258C, furent mis en assez bonne corre´lation avec les valeurs calculeés des contraintes affectant les joints de brasage. De plus, ce mode`le calibre´ est remarquablement simple par rapport aux mode`les utilisant une e´valuation au moyen de l’analyse par e´le´ments finis. On arrive donc a` la conclusion que ce mode`le peut servir d’outil efficace

[5]


pour de´terminer une e´valuation pre´liminaire de la re´sistance a` la fatigue thermique des joints de brasage des CBGA.

Essais de fiabilite´ et analyse des donneés des joints de brasage sans plomb pour les encapsulages de densite´ e´leveé

nickel-immersion gold) ou NiAu, et OSP (organic solderability preservative). Il cherche surtout a` de´terminer les endroits ou` se produisent ces de´faillances, les modes de de´faillance, et la composition de l’IMC (intermetallic compound) pour les joints de brasage de ces encapsulages a` densite´ e´leveé, suite a` 7.500 cycles de cyclage thermique. Ces re´sultats seront compare´s aux re´sultats obtenus avec le cyclage thermique et l’analyse par e´le´ments finis.

John Lau, Nick Hoo, Rob Horsley, Joe Smetana, Dongkai Shangguan, Walter Dauksher, Dave Love, Irv Menis et Bob Sullivan Mots-cle´s Brasures, Fiabilite´ des produits, Plaquettes a` circuits imprime´s L’e´tude que voici examine les essais de cyclage thermique et l’analyse statistique des re´sultats pour divers encapsulages de densite´ e´leveé, sur des plaquettes a` circuits imprime´s ayant des finitions SnCu HASL, NiAu et OSP. L’accent est mis sur la de´termination de la re´partition de la dureé de vie et la fiabilite´ des joints de brasage sans plomb de ces encapsulages a` densite´ e´leveé, lorsqu’ils sont soumis a` des conditions de cyclage thermique. L’article pre´sente un syste`me d’acquisition des donneés, le crite`re de de´faillance pertinent et la me´thode d’extraction des donneés, puis il les examine. Les donneés des essais de re´sistance conviennent le mieux a` la re´partition de Weibull. L’article pre´sente et discute e´galement la moyenne d’ećhantillon, la moyenne de la population, la dureé de vie caracte´ristique des ećhantillons, la dureé de vie caracte´ristique reélle, la pente de Weibull des ećhantillons et la pente de Weibull reélle, pour certains des encapsulages de densite´ e´leveé. De plus, il e´tablit le rapport qui existe entre la fiabilite´ et les limites de confiance pour une re´partition de la dureé de vie. Finalement, il de´termine la confiance pour comparer la qualite´ (dureé de vie moyenne) des joints de brasage sans plomb des encapsulages de densite´ e´leveé.

Analyse des de´faillances des joints de brasage sans plomb dans les encapsulages de densite´ e´leveé John Lau, Dongkai Shangguan, Todd Castello, Rob Horsley, Joe Smetana, Nick Hoo, Walter Dauksher, Dave Love, Irv Menis et Bob Sullivan Mots-cle´s Brasures, Fiabilite´ des produits, Proce´de´s d’assemblage, Plaquettes a` circuits imprime´s L’article pre´sente les analyses de la de´faillance des joints de brasage sans plomb et SnPb des encapsulages de densite´ e´leveé, comme par exemple les PBGA (plastic ball grid array) et CCGA (ceramic column grid array), soude´s sur des plaquettes a` circuits imprime´s Entek, avec SnCu HASL (hot-air solder levelling) ENIG (electroless

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Fiabilite´ du cyclage thermique des joints de brasage des re´sistances de puce sans plomb Jeffrey C. Suhling, H.S. Gale, R. Wayne Johnson, M. Nokibul Islam, Tushar Shete, Pradeep Lall, Michael J. Bozack, John L. Evans, Ping Seto, Tarun Gupta et James R. Thompson Mots-cle´s Brasage, Proce´de´s d’assemblage, Fiabilite´ des produits La fiabilite´ des joints de brasage des re´sistances de puce ce´ramiques, fixeés a` des substracts stratifie´s, suscite depuis longtemps une certaine inquie´tude, pour ce qui est des syste`mes expose´s a` des environnements rudes. Le travail que voici examine la fiabilite´ lors du cyclage thermique de plusieurs configurations de joints de brasage sans plomb de re´sistances de puce 2512. Une e´tude initiale comparait les fiabilite´s des joints de brasage obtenues avec des composants fabrique´s avec des terminaisons soudeés en e´tain-plomb et celles qui sont obtenues avec des composants ayant des terminaisons soudeés en e´tain pur. La partie principale des essais de fiabilite´ visait a` examiner deux plages de tempe´rature (de 408C a` 1258C et de 408C a` 1508C) et cinq alliages d’apport diffe´rents. Les alliages examine´s e´taient l’alliage SnAgCu (SAC) eutectique normal, recommande´ par les e´tudes ante´rieures, (95,5Sn-3,8Ag-0,7Cu), et trois variations de l’alliage SAC ternaire sans plomb, qui renferment de petites additions quaternaires de bismuth et d’indium, pour rehausser la re´sistance a` la fatigue. Pour chaque configuration, des donneés sur la de´faillance pendant le cyclage thermique ont e´te´ recueillies, puis analyseés au moyen des mode`les a` deux parame`tres de Weibull, afin de ranger les performances relatives des mate´riaux. Les re´sultats obtenus pour l’alliage sans plomb ont e´te´ compare´s aux donneés obtenues pour les joints 63Sn-37Pb normaux. De plus, un second groupe d’ećhantillons soumis au cyclage thermique fut utilise´ dans des e´tudes au microscope, afin d’examiner la propagation des fissures, les changements dans la microstructure des alliages soude´s et la croissance interme´tallique aux interfaces entre l’alliage et la pastille de la plaquette a` circuit imprime´.


Langfristige mechanische Zuverla¨ssigkeit von bleifreien Lo¨tmitteln W.J. Plumbridge Stichworte Zuverla¨ssigkeitsmanagement, Lo¨tmittel, Modellierung Die Entscheidung u¨ber die Umstellung auf bleifreie Lote ist gefallen – was bleibt, sind verschiedene Probleme in Bezug auf die Verarbeitung und Leistung der neuen Lo¨tmitteln. In diesem Artikel wird untersucht, welche Konsequenzen die Umstellung in Bezug auf die Leistung mit sich bringt, insbesondere bei langfristigen Anwendungen, bei denen eine hohe Zuverla¨ssigkeit gefordert ist. Beim Vergleich der wichtigsten mechanischen Eigenschaften schneiden die bleifreien Legierungen allgemein gut ab, wenngleich fu¨r verschiedene beobachtete ‘‘anomale’’ Verhaltensweisen, z.B. bezu¨glich der Auswirkungen des Wismuts, bisher noch keine Erkla¨rungen vorliegen. Der niedrigere Schmelzpunkt von Sn-Zn-Bi-Legierungen sowie deren vergleichbare mechanische Eigenschaften haben einen weiteren Anstoß dazu gegeben, sich mit den weniger gu¨nstigen Verarbeitungsmerkmalen dieser Legierungen auseinander zu setzen. Manche bleifreien Legierungen wie Sn-0.5Cu sind anfa¨llig fu¨r die Bildung von Zinnfraß, wenn sie u¨ber la¨ngere Zeit Temperaturen unter 138C ausgesetzt werden. Eine a¨hnliche Gefahr besteht auch bei den konzentrierteren Sn-3.8Ag-0.7CuLegierungen. Sich ausschließlich auf empirische Tests zu verlassen, ist nicht mehr viabel. Zudem ist dringend ein besseres Versta¨ndnis fu¨r das Verhalten der Lote erforderlich – als Grundlage fu¨r pha¨nomenologische Methoden bei der Vorhersage der Lebensdauer und beim Design.

Vergleich der Scherfestigkeit von Lotkugeln bei verschiedenen Arten von Vernickelung auf den Bondpads eines PBGA-Substrats Eric C.C. Yan, S.W. Ricky Lee und X. Huang Stichworte Produktzuverla¨ssigkeit, Lo¨tmittel, Scherfestigkeit, Halbleitertechnik

Soldering & Surface Mount Technology 16/2 [2004] 7–8 German abstracts # Emerald Group Publishing Limited [ISSN 0954-0911]

Der Artikel pra¨sentiert eine experimentelle Studie, mit der die Zuverla¨ssigkeit der Haftung von Lotkugeln an den Bondpads von PBGA-Substrat bei verschiedenen Vernickelungen untersucht werden sollte. Der Grundaufbau der UBM (Under Bump Metallisation) bestand aus Cu/Ni/Au. Drei verschiedene stromlose Vernickelungslo¨sungen wurden verwendet, um die Nickelschicht aufzubringen: Ni-B, Ni-P (5%) und Ni-P (10%). Zudem wurde zum Vergleich eine herko¨mmliche elektrolytische Ni/Au-Plattierung vorgenommen. Nach dem Anbringen der Lotkugeln wurden mechanische Tests durchgefu¨hrt, um die Scherfestigkeit der Lotkugeln zu vergleichen. Verschiedene Pru¨fstu¨cke wurden außerdem mehreren Reflows unterzogen, um den thermischen Alterungseffekt zu untersuchen. Die Testergebnisse zeigen, dass die stromlose Ni-B-Plattierung vergleichen mit der stromlosen Ni-P-Plattierung eine bessere Lotkugel-Scherfestigkeit ergeben kann. Die ho¨chste Lotkugel-Scherfestigkeit wird jedoch nach wie vor mit der herko¨mmlichen elektrolytischen Vernickelung erzielt. In den meisten untersuchten Fa¨llen schienen mehrere Reflows die Lotkugel-Scherfestigkeit geringfu¨gig zu reduzieren. Neben dem Schertest wurde auch eine Untersuchung unter dem Rasterelektronenmikroskop durchgefu¨hrt, um den Querschnitt und die Bruchfla¨che der Pru¨fstu¨cke zu inspizieren. Anhand der Defektanalyse wurden verschiedene Merkmale der verschiedenen Vernickelungsarten identifiziert.

Strategien zur Verbesserung der Zuverla¨ssigkeit von Lo¨tverbindungen auf Leistungs-Halbleiterbauelementen Guo-Quan Lu, Xingsheng Liu, Sihua Wen, Jesus Noel Calata und John G. Bai Stichworte Lo¨ten, Verbindungsprozesse, Beanspruchung (Materialien), Halbleiterbauelemente In diesem Artikel werden verschiedene Strategien zur Verbesserung der Zuverla¨ssigkeit von Lo¨tverbindungen auf Leistungsbauelementen in Single-Device und MultichipPackages vorgestellt. Insbesondere wird eine Strategie angesprochen, bei der die Zuverla¨ssigkeit der Lo¨tverbindungen durch Anpassung der Lo¨tstellengeometrie, durch Unterfu¨llung und durch die Nutzung flexibler Substrate verbessert werden soll. Eine besondere Rolle spielen dabei dreifach gestapelte Lo¨tna¨hte, die in ihrer Form einer Sanduhr a¨hneln. Durch die Sanduhrform wird die sta¨rkste unelastische Beanspruchung von der weniger robusten Grenzfla¨che mit dem Chip weg und hin in den Hauptbereich der Verbindung verlagert, wa¨hrend die Unterfu¨llungen fu¨r eine Ableitung der Belastung von den Lo¨tstellen weg sorgen. Flexible Substrate ko¨nnen sich verformen, um die thermomechanische Beanspruchung zu verringern. Bei Temperaturwechselbeanspruchungen ist bei Anwendung dieser Techniken eine signifikante Verbesserung der Zuverla¨ssigkeit zu beobachten. Zudem werden Design, Test und Finite-Elemente-Analysen einer Verbindungsstruktur, die Dimple-Array Interconnect-Technik, fu¨r die Verbesserung der Zuverla¨ssigkeit von Lo¨tverbindungen vorgestellt.

Einscha¨tzung der Dauerhaltbarkeit von CBGA-Lo¨tverbindungen bei Wa¨rmebelastung anhand einer einfachen Methode T.E. Wong, C.Y. Lau und H.S. Fenger Stichworte Lo¨ten, Verbindungsprozesse, Ermu¨dung, thermische Materialeigenschaften Es wurde eine einfache Analysemethode entwickelt, um die Dauerhaltbarkeit einer CGBA (Ceramic Ball Grid Array)Lo¨tverbindung unter Wa¨rmebelastung zu untersuchen. Die Lo¨tverbindung bestand aus einer 90Pb/10Sn-Lotkugel, u¨ber und unter der eutektisches SnPb-Lot aufgebracht wurde. Ein Versagen der Lo¨tverbindung trat am eutektischen Lot auf. Zuna¨chst wurde eine geschlossene Lo¨sung, basierend auf einer Berechnung des Verdra¨ngungsgleichgewichts in dem elektronischen Package, hergeleitet, um die Belastung der Lo¨tverbindung wa¨hrend der zyklischen Temperaturwechsel zu berechnen. Bei der Berechnung wurde eine Iterationstechnik verwendet, um eine konvergente Lo¨sung fu¨r die Lotbeanspruchung zu finden. Die elastischen Materialeigenschaften wurden fu¨r alle Komponenten des elektronischen Package mit Ausnahme der Lo¨tmaterialien verwendet, fu¨r die elastoplastische Eigenschaften verwendet wurden. Danach wurde anhand einer empirisch abgeleiteten Formel, die auf einer Modifikation der Coffin-Manson-Ermu¨dungstheorie beruht, ein Vorhersagemodell fu¨r die Dauerhaltbarkeit aufgestellt. Anhand von CBGA-Testergebnissen von Motorola und der hergeleiteten Lotbelastungen wurde das vorgeschlagene Lebensdauer-Vorhersagemodell berechnet. Bei dem Modellkalibrierungsprozess waren die Testergebnisse fu¨r die 255 und 304-Pin-CBGA, die einem zyklischen Temperaturwechsel zwischen 08C und 1008C und zwischen 408C und 1258C ausgesetzt wurden, relativ gut mit der berechneten Lotbeanspruchung korreliert. Das kalibrierte Modell ist zudem bemerkenswert einfach verglichen mit Modellen, die mit Finite-Elemente-Analyse arbeiten. Hieraus la¨sst sich schließen, dass das Modell effektiv fu¨r eine erste Einscha¨tzung der Dauerhaltbarkeit von

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CBGA-Lo¨tverbindungen bei Wa¨rmebelastung genutzt werden kann.

Zuverla¨ssigkeitstestung und Datenanalyse von bleifreien Lo¨tverbindungen in High-Density-Packages John Lau, Nick Hoo, Rob Horsley, Joe Smetana, Dongkai Shangguan, Walter Dauksher, Dave Love, Irv Menis und Bob Sullivan Stichworte Lo¨tmittel, Produktzuverla¨ssigkeit, Leiterplatten Bei der Studie, u¨ber die in diesem Artikel berichtet wird, wurden zyklische Temperaturwechseltests mit verschiedenen High-Density-Packages auf Leiterplatten mit SnCu HASL-, NiAu- und OSP-Oberfla¨che durchgefu¨hrt und die Ergebnisse statistisch analysiert. Das Hauptanliegen dabei war, die Lebensdauerverteilung und Zuverla¨ssigkeit der bleifreien Lo¨tverbindungen dieser High-DensityPackages bei zyklischen Temperaturwechseln zu bestimmen. Ein Datenerfassungssystem, das relevante Ausfallkriterium und die zur Datenextraktion verwendete Methode werden vorgestellt und untersucht. Die Daten des Lebensdauerversuchs waren der Weibullschen Verteilung am besten angepasst. Das Stichprobenmittel, das Populationsmittel, die typische Lebensdauer der Stichproben, die typische wahre Lebensdauer, der WeibullFormparameter der Stichproben und der wahre WeibullFormparameter einiger der High-Density-Packages werden beschrieben und diskutiert. Zudem wird der Zusammenhang zwischen der Zuverla¨ssigkeit und den Vertrauensgrenzen einer Lebensdauerverteilung aufgezeigt. Abschließend wird festgestellt, mit welchem Vertrauen sich die Qualita¨t (die mittlere Lebensdauer) von bleifreien Lo¨tverbindungen von High-Density-Packages bestimmen la¨sst.

Fehleranalyse von bleifreien Lo¨tverbindungen fu¨r High-Density Packages John Lau, Dongkai Shangguan, Todd Castello, Rob Horsley, Joe Smetana, Nick Hoo, Walter Dauksher, Dave Love, Irv Menis und Bob Sullivan Stichworte Lo¨tmittel, Produktzuverla¨ssigkeit, Verbindungsprozesse, Leiterplatten Die Fehleranalysen von bleifreien und SnPbLo¨tverbindungen von High-Density-Packages wie PBGA (Plastic Ball Grid Array) und CCGA (Ceramic Column Grid Array), die auf SnCu HASL (Hot-Air Solder Levelling, Heißluftverzinnen) ENIG (Electroless NickelImmersion Gold) oder NiAu und OSP (Organic

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Solderability Preservative) Entek-Leiterplatten aufgelo¨tet wurden, werden vorgestellt. Der Schwerpunkt der Untersuchung lag darauf, die Defektorte, die Ausfallmodi und die Zusammensetzung von intermetallischen Verbindungen (IMC) der Lo¨tverbindungen der High-Density-Packages zu ermitteln, nachdem diese 7500 Temperaturwechselzyklen ausgesetzt worden waren. Die Ergebnisse werden mit denen der Temperaturwechseltests und der Finite-Elemente-Analyse verglichen.

Zuverla¨ssigkeit von bleifreien Chipwiderstand-Lo¨tverbindungen bei Temperaturwechselbeanspruchung Jeffrey C. Suhling, H. S. Gale, R. Wayne Johnson, M. Nokibul Islam, Tushar Shete, Pradeep Lall, Michael J. Bozack, John L. Evans, Ping Seto, Tarun Gupta und James R. Thompson Stichworte Lo¨ten, Verbindungsprozesse, Produktzuverla¨ssigkeit Bei Systemen, die hohen Umweltbelastungen z.B. in Kraftfahrzeugen oder Flugzeugen ausgesetzt sind, stellt die Zuverla¨ssigkeit der Lo¨tverbindung zwischen KeramikChipwidersta¨nden und Laminatsubstraten seit langem ein Problem dar. In der vorliegenden Studie wurde die Zuverla¨ssigkeit von mehreren bleifreien Lo¨tverbindungen von Widersta¨nden der Baugro¨ße 2512 bei Temperaturwechselbeanspruchung untersucht. Zuna¨chst wurde die Zuverla¨ssigkeit von Lo¨tverbindungen bei Bauteilen mit Zinn-Blei bzw. Reinzinn-Lo¨tanschlu¨ssen miteinander verglichen. Dabei wurden im Wesentlichen zwei Temperaturbereiche ( 40 bis 1258C und 40 bis 1508C) und fu¨nf verschiedene Lotlegierungen untersucht. Die untersuchten Lo¨tmittel schlossen die normale eutektische SnAgCu (SAC)-Legierung, die von fru¨heren Studien empfohlen wurde (95.5Sn-3.8Ag-0.7Cu), und drei Varianten der bleifreien terna¨ren SAC-Legierung ein, die geringfu¨gige quaterna¨re Wismut und Indiumzusa¨tze zur Verbesserung der Dauerfestigkeit enthielten. Fu¨r jede Konfiguration wurden die Versagensdaten nach Temperaturwechselbeanspruchung gesammelt und anhand von zweiparametrigen Weibull-Modellen analysiert, um ein Ranking der relativen Materialleistungen zu erhalten. Die Ergebnisse fu¨r die bleifreien Lo¨tverbindungen wurden mit denen der herko¨mmlichen 63Sn-37Pb-Lo¨tverbindungen verglichen. Zudem wurde ein zweiter Satz von Proben, die ebenfalls einer Temperaturwechselbeanspruchung ausgesetzt worden waren, mikroskopisch auf die Ausbreitung von Rissen, auf Vera¨nderungen in der Mikrostruktur der Lo¨tmittel und auf das Wachstum intermetallischer Verbindungen an der Schnittstelle zwischen Lot und Leiterplatten-Pads untersucht.

Editorial

Surface mount technology (SMT) has become the main technique for the board level assembly of microelectronic devices since 1980s. For surface mounted components (SMCs), the solder joints not only provide for the passage of electrical signal and power, but also the mechanical support to hold the package in position on the printed circuit board (PCB). Since the dimensions of solder joints are relatively small and the electronic devices may experience thermal-mechanical loadings during operation, the solder joint reliability of SMCs is a major concern in the electronics manufacturing industry. This special issue of SSMT is a collection of seven papers on the subject of solder joint reliability. All of the papers were subject to a process of peer review and revision. The first paper gives a comprehensive discussion on the long-term reliability of lead-free solders. This paper considers the transition in terms of performance, with particular emphasis on long-term, high reliability applications. Comparison of key mechanical properties indicated generally beneficial outcomes of the transition to lead-free alloys, although there might be a lack of understanding surrounding anomalous observations. Sole reliance upon empirical testing has become non-viable, and there is an urgent need for a greater understanding of solder behaviour to act as a basis for phenomenological methods of life prediction and design. The second paper presents an experimental study to assess the reliability of solder ball attachment to the bond pads of a plastic ball grid array (PBGA) substrate for various plating schemes. Solder ball shear tests were conducted to characterise the ball attachment strength for comparison. Three different kinds of electroless plating solutions were used to deposit the Ni layer. Also, conventional electrolytic Ni/Au plating was performed to provide a benchmark. In addition to the ball shear tests, scanning electron microscopy (SEM) was performed to inspect the cross-section and the fracture surface of the tested specimens. From the failure analysis, certain characteristics were identified for the various Ni plating schemes. The third paper presents some strategies for improving the reliability of solder joints on power electronics. Schemes for improving solder joint reliability by adjusting solder joint geometry, underfilling and utilisation of flexible substrates are discussed. Thermal cycling data and finite element analysis indicated significant improvements in reliability when the proposed configurations were used. The fourth paper introduces a simple method for the estimation of thermal fatigue life of ceramic ball grid array (CBGA) solder joints. A closed-form solution, based on calculation of the equilibrium of the displacements within the electronic package assembly, was first derived to

calculate the solder joint strains during temperature cycling. In the calculation, an iteration technique was developed to obtain a convergent solution for the solder strains, and the elastic material properties were used for all the electronic package assembly components except for the solder materials, which had elastic-plastic properties. A fatigue life prediction model, evolved from an empirically derived formula based upon a modified Coffin-Manson fatigue model, was established and then validated against previous experimental results. It was concluded that the proposed model could be used as an effective tool to estimate the thermal fatigue life of CBGA solder joints. The fifth paper is an experimental study of solder joint reliability, together with the relevant data analysis. This study investigated temperature cycling tests and statistical analysis of various high-density packages on PCBs with SnCu HASL, NiAu, and OSP finishes. The emphasis was placed on the determination of the life distribution and reliability of the lead-free solder joints under thermal cycling conditions. Much useful first-hand experimental data are presented in this paper. The sixth paper is on the failure analysis of solder joints, which is a sequel to the fifth paper. A series of failure analyses on the solder joints of assemblies of high density packages with various PCB surface finishes was performed. The emphasis was placed on identifying the failure location and failure mechanism of the solder joints after large numbers of temperature cycles. The presented results will be very helpful to researchers who are working on the computational modelling of solder joint reliability. The seventh paper investigates the thermal cycling reliability of chip resistors with lead-free solder joints. In this study, the reliability of 2512 chip resistor lead-free solder joints under thermal cycling was investigated. Two temperature ranges ( 40 to 1258C and 40 to 1508C) and five different solder alloys were examined. In addition to two-parameter Weibull analysis of the experimental data, a second set of thermally cycled samples was used for microscopy studies to examine crack propagation, changes in the microstructure of the solders, and intermetallic growth at the solder to PCB pad interfaces. This special issue covers a wide range of topics on solder joint reliability, which should bring benefits to the readers of SSMT from various points of view. The Guest Editor would like to thank authors of all papers for their contribution and co-operation. Special thanks are due to the Chief Editor of SSMT, David Whalley. Without his strong support, this special issue would not have materialised in time for publication. Furthermore, due to his effective proof-reading, the quality of this special issue has been substantially improved. Ricky Lee Guest Editor

Soldering & Surface Mount Technology 16/2 [2004] 9 # Emerald Group Publishing Limited [ISSN 0954-0911]

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Contributors

John G. Bai received his BS Degree in applied physics from Tianjin University, Tianjin, China, in 1995, the MS Degree in semiconductor physics from Beijing University, Beijing, China, in 1998 and another MS Degree in materials science from Dartmouth College, Hanover, NH, in 2000. He is currently pursuing the PhD degree in the Center for Power Electronics Systems and in the Departments of Materials Science and Engineering and Electrical and Computer Engineering at Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg, VA. His research interests include packaging in microelectronics, power electronics and optoelectronics, processing and applications of electronic, optoelectonic and nanometer materials and their characterization, design and processing of integrated components/devices and their numerical analyses using multiphysics finite element modelling. Jesus Noel Calata obtained his BS and MS degrees in Metallurgical Engineering from the University of the Philippines. He is currently a PhD student in Materials Science and Engineering at Virginia Tech under the supervision of Professor Guo-Quan Lu. His current research interests include packaging of power semiconductor devices; constrained sintering of glass, glass-ceramic, ceramic and metal coatings and thick films on various substrates, nanomaterials processing and fabrication of nanoscale composite structures. He has done work on glass and glass-ceramic-coated electrostatic chucks for semiconductor wafer processing. Other past and present interests are on extractive metallurgy, electroplating, electroless plating, and corrosion. Todd Castello ([email protected]) is a graduate of Herkimer County Community College. He holds an Associates of Science degree in Environmental Science and Forestry Resource Management. He has 21 years of analytical experience in microelectronics and materials research. Recent activities have been on quality assurance and reliability particularly on advanced electronic packaging/surface mount assembly and the insertion of advanced technologies into high volume manufacturing. The current research interests have been focussed on fine pitch BGA, chip scale packaging technologies, mechanical and thermomechanical reliability testing and study of related failure modes and mechanisms. Walter Dauksher ([email protected]) received his PhD in Mechanical Engineering from the University of Washington. He has worked as a structural analyst for both Rockwell International and The Boeing Company and as a reliability engineer for Hewlett-Packard. He is currently with Agilent Technologies where he uses finite element modelling to evaluate packaging and silicon technologies. Walter is a registered Professional Engineer in Colorado and Washington state.

Soldering & Surface Mount Technology 16/2 [2004] 10–12 # Emerald Group Publishing Limited [ISSN 0954-0911]

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H.S. Fenger is an Engineering Fellow at Raytheon Space and Airborne Systems since 1979. He currently leads advanced electronics packaging development projects within the Electronics Centers in El Segundo. He has been actively engaged in applying commercial high density packaging designs into electronics products within the legacy sensors business unit. He has authored numerous papers in materials and process development of advanced interconnects and holds three patents in multichip module interconnect systems. He received his BS in Chemical Engineering from the University of Rhode Island and MS in Chemistry from Brooklyn Polytechnic Institute.

Dr Guo-Quan Lu is Professor in the Departments of Materials Science and Engineering and Electrical and Computer Engineering at Virginia Polytechnic Institute and State University (Virginia Tech). He got his PhD in Applied Physics/Materials Science from the Harvard University in 1990. His research activities and interests are in the general area of materials and processing development for applications in microelectronics, power electronics, optoelectronics, sensors, and nanotechnology. Dr Lu is Thrust Leader for Materials for Integration Technologies in the Center for Power Electronics Systems, an NSF Engineering Research Center based at Virginia Tech. He has been responsible for developing several three-dimensional packaging technologies for integrated power electronics modules. Dr Lu holds three US patents and has published over 100 papers in journals and conference proceedings. He was the 1995 winner of the Virginia Tech Sporn Award for excellence in teaching of engineering subjects and was the recipient of a National Science Foundation CAREER award in 1995. Rob Horsley received his BSc (Hons) degree in Metallurgy and Microstructural Engineering from the Sheffield City Polytechnic, Sheffield, UK and the MSc degree in Advanced Manufacturing from the University of Salford, Manchester, UK, in 1987 and 1996, respectively. In 1996 he joined the Manufacturing Technology Department, Celestica Limited, UK where his main research activities include lead-free soldering implementation. He is now a leading member of the Celestica global lead-free team and in 2003 was awarded a PhD in lead-free solder joint microstructural characterisation at the University of Salford, Manchester, UK. X. Huang received his BSc degree in Materials Science and Engineering (1984), and the MSc degree in Metallic Materials and Heat Treatment (1987), both from the Department of Materials Science and Engineering, Shanghai Jiao Tong University, China. From July 1987 to September 1997, he worked at Sichuan University, Chengdu, China. In January 2003, he obtained his PhD degree in Mechanical Engineering from the Department of Mechanical Engineering, Hong Kong University of Science and Technology. He currently works in the Network System Group (NSG), Foxconn Electronics, Inc., Shenzhen, China, as a failure analysis leader responsible for failure analysis of SMT components and printed circuit board assemblies (PCBAs). He is also responsible for the improvement and development of new manufacturing processes and technologies. Ms C.Y. Lau is Senior Mechanical Engineer at Raytheon Space and Airborne Systems, where she has worked in both physical design and structural analysis during her 6 years of service. Prior to joining Raytheon, she interned with the Advanced Structural Concepts group at Northrop Grumman while completing her BSME at UCLA. In 2000, she earned her MSME from USC as a Raytheon Masters Fellow. Her creative passion compels her to continuously seek opportunities to synergize imagination and technical innovation as she enlarges her sphere of influence. John Lau received his PhD degree in Theoretical and Applied Mechanics from the University of Illinois (1977), an MASc degree in Structural Engineering from the University of British Columbia (1973), a second MS degree in Engineering Physics from the University of Wisconsin (1974), and a third MS degree in Management Science from

Contributors Soldering & Surface Mount Technology 16/2 [2004] 10–12

Fairleigh Dickinson University (1981). He also has a BE degree in Civil Engineering from National Taiwan University (1970). John is an Interconnection Technology Scientist at Agilent Technologies, Inc. His current interests cover a broad range of optoelectronic packaging and lead-free manufacturing technology. Prior to Agilent, he worked for Express Packaging Systems, Hewlett-Packard Company, Sandia National Laboratory, Bechtel Power Corporation, and Exxon Production and Research Company. With more than 30 years of R&D and manufacturing experience in the electronics, photonics, petroleum, nuclear, and defense industries, he has given over 200 workshops and invited presentations, authored and co-authored over 200 technical publications, authored more than 100 book chapters, and is the author and editor of more than 14 books in IC packaging and internations. John served in the editorial boards of the IEEE Transactions on Components, Packaging, and Manufacturing Technology and ASME Transactions, Journal of Electronic Packaging. He also served as general chairman, program chairman, session chairman, and invited speaker of several ASME, IEEE, ASM, MRS, IMAPS, SEMI, and SMI International conferences. He received a few awards from the ASME and IEEE for best Transactions and Proceedings papers and outstanding technical achievements. He is one of the distinguish lecturers of ASME and IEEE/CPMT. He is an ASME Fellow and IEEE Fellow. S.W. Ricky Lee received his PhD degree from Purdue University in 1992. Currently he is Associate Professor of Mechanical Engineering and Director of EPACK Lab at the Hong Kong University of Science and Technology. His research activities cover flip chip technologies, wafer level chip scale packaging, high density interconnects, and solder joint reliability. He has published numerous technical papers in international journals and conference proceedings, and also co-authored three books. Ricky is the Associate Editor of two IEEE Transactions. He also sits on the Editorial Advisory Board of two other international journals. He is an ASME Fellow, a senior member of IEEE, and the VP-conferences of IEEE CPMT. Xingsheng Liu received his PhD in Materials Science and Engineering from Virginia Polytechnic Institute and State University, Blacksburg, VA, USA in 2001. He is currently with the Corning Incorporated Science and Technology Center, Corning, NY, as a Sr Research Scientist. He has published about 40 papers in journals and conference proceedings. His research interests include optoelectronics, microelectronics and power electronics packaging, characterization, process design and development, thermal management as well as reliability evaluation and failure analysis of electronic/optoelectronic devices and packages. Dave Love is currently the Components Technology Manager for the COT group at Sun Microsystems. He holds a Bachelors degree in Chemistry from the University of San Francisco. Dave has 25 years experience in the electronics industry, mostly in the field of semiconductor packaging. He is the author of over a dozen patents and many papers regarding metallurgy or packaging. W.J. Plumbridge carried out research on vacancy decay and precipitation hardening kinetics in aluminium alloys after graduating from the Department of Metallurgy (UMIST). He subsequently became a Research Fellow in the same department, working on fatigue crack growth and fractography of aluminium-based aircraft alloys. In 1970, he joined the Engineering Department at Cambridge

University, to study fatigue-creep interactions in low alloy steels for power generation. In 1973, he took up a lectureship in the Mechanical Engineering Department at Bristol University where he remained for 14 years. During this period he expanded his interests in fatigue, creep and their interactions to include stainless steels, titanium and nickel-based alloys. He was promoted to reader in 1983. He emigrated to Australia in 1987 to take up the chair of Materials Engineering at the University of Wollongong, NSW. In this post, he led the transition from a traditional Metallurgy Department to an integrated Materials Engineering Discipline. He returned to the UK in 1991 to the chair of Materials at the Open University where he initiated the programme on solders and established the Solder Research Group. In total, he has published over 120 papers. Bill is Vice Chair of COST 531 (a European Action on Lead-Free Solders) and Chair of the European Structural Integrity Society, Technical Sub-committee 18 (Structural Integrity in Electronics). He has held many positions in local Materials Societies, and worked as a review chair for the National Quality Assurance Agency in its evaluation of higher education at subject level. In December 2003, his book Structural Integrity and Reliability in Electronics, Enhancing Performance in a Lead-free Environment, co authored with Ray Matela and Angus Westwater, was published. Dongkai Shangguan (dongkai.shangguan@ flextronics.com) obtained a BSc degree in Mechanical Engineering from Tsinghua University, China and a DPhil degree from the University of Oxford, UK, and is currently pursuing an MBA degree from the San Jose State University, CA. He conducted post-doctoral teaching and research at the University of Cambridge, UK and The University of Alabama. He joined Ford Motor Co. in 1991 and worked on electronics packaging and manufacturing technology as a senior technical specialist and supervisor. Currently, he works at Flextronics International as manager for advanced process technology. He has 13 US and international patents, and has published one book (‘‘Cellular Growth of Crystals’’) and over 50 papers in the field of materials processing, electronics packaging and manufacturing technology. Joe Smetana ([email protected]) joined Alcatel (as part of DSC Communications Corporation) in October 1990 in manufacturing engineering to establish a new product engineering and design for manufacturing activity. He is currently serving as a technologist for operations engineering. This includes providing high level strategic and detailed engineering oversight and inputs for manufacturing technology, design for manufacturing, and processes. His work addresses device and system packaging, PWB fabrication, PCB assembly, and system interconnection, covering manufacturing, reliability, and signal integrity. These activities primarily support R&D, new product engineering, and technology development. Joe is a Distinguished Member of the Technical Staff of the Alcatel Technical Academy. Prior to joining Alcatel, Joe served at Texas Instruments as lead engineer for Weapons Systems Division Producibility Engineering from 1985 to 1990. He also served as a nuclear engineering officer in the US Navy from 1980 to 1985, primarily working shipyard overhauls of nuclear powered cruisers. He was qualified as a chief engineering officer for Naval Nuclear Power Plants and as a surface warfare officer during this time. He has a Bachelor of Science degree in Electrical Engineering from Tulane University, as well as graduate studies in Nuclear Engineering with the US Navy. He is a Licensed Professional Engineer in the State of Texas.

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Contributors Soldering & Surface Mount Technology 16/2 [2004] 10–12

Jeffrey C. Suhling received his BS degree in Applied Mathematics, Engineering, and Physics in 1980, and the MS and PhD degrees in Engineering Mechanics in 1981 and 1985, respectively, all from the University of Wisconsin, Madison, WI. He graduated with Distinction in 1980, and has been inducted into the Phi Beta Kappa, Phi Kappa Phi, and Sigma XI honorary societies. During 1980-1983, he received a National Science Foundation Graduate Fellowship. He joined the Department of Mechanical Engineering at Auburn University in 1985, where he currently holds the rank of Quina Distinguished Professor. At Auburn, he serves as the Director of the NSF Center for Advanced Vehicle Electronics, which is an Industry University Cooperative Research Center (IUCRC) with 12 member companies. He was selected as the ‘‘Outstanding Mechanical Engineering Faculty Member’’ by the undergraduate students during 1990, received the College of Engineering Birdsong Superior Teaching Award in 1994, and received the College of Engineering Senior Research Award in 2001. His research interests include the application of analytical, numerical, and experimental methods of solid mechanics to problems in electronic packaging. Dr Suhling has authored over 150 technical publications, and has advised over 50 graduate students. Dr Suhling is a member of the Institute of Electrical and Electronics Engineers (IEEE), the American Society of Mechanical Engineers (ASME), the International Microelectronics and Packaging Society (IMAPS), and the Society for Experimental Mechanics (SEM). He served as Chair of the Electrical and Electronic Packaging Division of ASME during 2002-2003. Bob Sullivan ([email protected]) has been a member of the High Density Packaging User Group (HDPUG) Staff for the last 5 years. The focus of this consortium has been on the second level reliability of hardware technologies applied in Computer and Telecommunication products. Prior to joining HDP User Group he worked for many years in all aspects of Computer hardware technology.

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He received his education in Physics and Mathematics from Le Moyne College in Syracuse, New York, NY. Sihua Wen received his BS degree in Materials Science in 1997 from Tsinghua University, Beijing, PRC. He received his MS degree in 1999, and the PhD degree in 2002, both from Virginia Tech’s Center for Power Electronics Systems. His research interests are in the area of power electronics and microelectronics integration. He is now a post doctoral fellow at the University of Pennsylvania. Dr T.E. Wong is Senior Manager, Engineering in Raytheon Space and Airborne Systems. He has been with Raytheon for 9 years and has previously worked for the Microsoft, Aerospace, and Digital Equipment Corporations. His expertise lies in such fields as solid, continuum, experimental, and fracture mechanics, impact damage evaluation, and mathematical modelling of mechanical systems. He has authored over 40 technical papers and numerous patentable innovations. He has been an invited lecturer in the graduate school class named ‘‘Electronic Packaging Interconnection’’ in UCLA. He has also organized and chaired many technical sessions. He received his MS from the University of New Mexico, Albuquerque in 1980 and PhD from the University of California, Berkeley in 1987. Both degrees are in Mechanical Engineering. Eric C.C. Yan received his MPhil degree in Mechanical Engineering from the Hong Kong University of Science and Technology (HKUST) in 2000. He has substantial experience in R&D of electronic packaging. He specializes in wire bonding, nickel plating, flip chip technology, chip scale packages, decapsulation, and solder joint reliability. Currently, Eric is Senior Technical Staff at the EPACK Lab, HKUST. His duties at EPACK Lab include technical training, equipment maintenance, safety management, material characterization, and failure analysis.

Long term mechanical reliability with lead-free solders

W.J. Plumbridge Department of Materials Engineering, The Open University, UK

Keywords Reliability, Reliability management, Solders, Modelling

Abstract The decision to move to lead-free solders has been made, but processing and performance challenges remain. This paper considers the transition in terms of performance, with particular emphasis on long term, high reliability applications. Comparison of key mechanical properties indicates generally beneficial outcomes of the transition to lead-free alloys, although there is a lack of understanding surrounding “anomalous” observations, such as the effects of the bismuth. The lower melting point of Sn-Zn-Bi alloys, together with their comparable mechanical properties, provide further impetus to address their shortcomings during processing. Some lead-free alloys, such as Sn-0.5Cu, are susceptible to tin-pest formation following prolonged exposure below 138C, and this possibility remains for the more concentrated Sn-3.8Ag-0.7Cu alloy.

Received: 30 November 2003 Revised: 13 February 2004 Accepted: 13 February 2004

Soldering & Surface Mount Technology 16/2 [2004] 13–20 q Emerald Group Publishing Limited [ISSN 0954-0911] [DOI: 10.1108/09540910410537291]

1. Introduction

2. The metallurgical perspective

The die is cast! Lead-free solders are being introduced at different rates across the world. Japan is ahead; for Europe, 1 July 2006 has been set as the deadline for the transition, and the US is making rapid progress towards this goal. The alloys likely to be the initial replacements for Sn-37 Pb are Sn-0.5 Cu, Sn-3.5 Ag and Sn-3.8 Ag-0.7 Cu or slight variations of them. More uncertainty and debate exists around zinc and bismuth-containing systems (Richards et al., 1999). Once that decision was made, two further challenges had to be faced; the implementation of lead-free processing/ manufacturing to achieve an efficient transition in production, and the assurance of the reliability of lead-free solders during performance in service. The present paper addresses the second point, particularly with regard to long term mechanical reliability. It takes the opportunity, presented by the hiatus surrounding the transition to leadfree solders, of reappraising the situation from both a metallurgical and an engineering prespective. At the outset, two questions should be considered. What is meant by “long term” reliability? and Can long term reliability be assumed with traditional Sn-Pb solders, which have been in use in electronics equipment for many decades? The answer to the first of these is very much applicationspecific, and may range from 5 to 50 years accordingly. In this writer’s opinion, the answer to the second question is a resounding “No”! unless the excessive conservatism incorporated in design prior to miniaturisation is permitted. Although the volume of data on the mechanical properties of lead-containing solders is orders of magnitude greater than that available for the new lead-free alloys, much of it has little value in design and life prediction for the commonest cause of service failure – thermomechanical fatigue (TMF). In essence, the argument here is that it is not yet possible to ensure long term reliability, irrespective of the nature of the solder alloy. With that caveat, the key questions to be addressed are: What are the differences between lead-free solders (those alloys cited above) and the established Sn-37 Pb alloy? and How do these differences affect the properties that influence service performance? The present paper considers various aspects that require closer scrutiny, with regard to long term reliability, and draws attention to the significant differences that can arise in the behaviour of broadly similar alloys. While examples from the literature are used to demonstrate the points made, a comprehensive review is not attempted.

Most solders are currently tin-based alloys, and an overview of the physical metallurgy of lead-free alloy development has recently been produced by Subramanian and Lee (2003). Apart from a reduction in density (and hence more solder per unit mass), the removal of lead produces a quite different alloy from Sn-37 Pb. The amount of solute for the popular lead-free systems mentioned above varies between 7 (Sn-3.8Ag-0.6Cu) and 70 (Sn-0.5Cu) times less than in Sn-37Pb. This raises the melting point by some 30-408C, taking processing temperatures perilously close to those that might damage the board or components. In addition, the category of the alloy is changed from a conventional two-phase system (as in Sn-37 Pb) to a particle-strengthened system, and this has significant ramifications on mechanical behaviour, as will be evidenced later. While both types of solder are based upon tin, alloys in the more dilute lead-free group are more likely to exhibit the intrinsic characteristics of that metal. Of particular relevance are its allotropy and anisotropy.

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2.1 The allotropy of tin Pure tin undergoes a transition in crystallographic structure at 138C from body-centred tetragonal, bct, (white tin) to a diamond cubic (grey tin) form at lower temperatures. The 26 per cent volume change accompanying this transformation results in local cracking and eventual disintegration of the sample. The product is known as tin pest. Such an effect has never been observed in Sn-37 Pb alloys, but has been reported for the Sn-0.5 Cu solder alloy (Kariya et al., 2001) which is the most dilute of the lead-free family. Figure 1 shows the severe damage to a massive tensile test piece. In pure tin, the process involves nucleation and growth with a protracted incubation period (Burgers and Green, 1957). Once nucleation has taken place, the growth of grey tin is relatively rapid and the maximum rate of transformation occurs at 2408C (Hedges, 1960). However, the timescales shown in the figure do fall easily within the definition of long term. Formation of tin pest in the less dilute Sn-Ag based solders has yet to be established but long term ageing tests at 2188C indicate that this is a possibility (Plumbridge and Gagg, 2004). Figure 2 shows discoloured surface regions which may be the beginning of tin pest formation. The dark regions on the flat indicate almost total transformation in this location. Their location on the machined area of the cylindrical sample concurs with previous findings that the presence of residual stress or strain promotes the transformation.

2.2 The anisotropy of tin A variation in properties with crystallographic direction is known as anisotropy. At room temperature, the body-centred The current issue and full text archive of this journal is available at www.emeraldinsight.com/0954-0911.htm

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W.J. Plumbridge Long term mechanical reliability with lead-free solders Soldering & Surface Mount Technology 16/2 [2004] 13–20

Figure 1 Extensive tin pest formation on a Sn-0.5 Cu sample aged at 2 188C (Kariya et al., 2001)

Figure 3 Surface damage in a Sn-3.8 Ag-0.7Cu free standing ingot produced by thermally cycling (3,000 cycles between 30 and 1258C) (Liu and Plumbridge, 2004)

3. The engineering perspective

Figure 2 Indications of tin pest on the machined regions of a Sn-3.8 Ag0.7 Cu sample exposed at 2 188C for 46 months (Plumbridge and Gagg, 2004)

tetragonal structure of tin provides ample opportunity for this. For example, the coefficient of thermal expansion (CTE) may change by a factor of two according to the direction in which it is measured, and Young’s modulus may experience a threefold variation. Significant stresses may develop at grain boundaries, according to the orientation of the neighbouring grains (Lee et al., 2002; Subramanian and Lee, 2004). When samples contain large numbers of grains which, by definition, have different crystalline orientations from their neighbours, the net effect is reduced. However, in modern microelectronics actual joints may comprise a few grains, and exposure to temperature change, or repeated thermal cycling, can cause surface roughening or extrusion and cracking as shown in Figure 3 (Liu and Plumbridge, 2003). It must be emphasised that this phenomenon is intrinsic to the material itself. The presence of an interface, as in a solder joint, or the mechanical leverage associated with adjacent joints on a printed circuit board are additional strain-producing effects during service, and originate from mismatch between CTEs of different materials in contact. The consequences of dilute alloy addition, as in lead-free solders, or higher levels of solute, as in Sn-37 Pb, are unknown, and the distinctly two-phase microstructure of the latter further impedes direct comparison. Various situations arising from anisotropy during TMF have been considered in more detail by Lee et al. (2002).

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Modelling TMF behaviour requires knowledge of the following. 1 The solder properties over the temperature range of the cycle. 2 How the rate of temperature change (or strain rate) affects these values. 3 The detailed temperature-time profile. 4 The degree of instability of the microstructure, which is largely determined by its prior thermal history. The mechanical properties that influence performance are the following. . Strength – It is denoted by yield, proof or ultimate stress, and indicates the load-bearing capacity, impact resistance and the low strain fatigue (predominantly elastic cycles such as vibration) calibre of a material. . Ductility – The amount of strain that can be accommodated prior to failure determines the high strain (predominantly plastic cycles) fatigue behaviour. . Fatigue – Mechanical, thermal and thermomechanical sources of cyclic failure involve the initiation and growth of a crack until fracture results. The amplitude of stress, strain or temperature is the principal determinant of fatigue life, although other factors may have a significant role. There is no simple correlation between TMF and isothermal fatigue at the same strain range. . Creep – A time, rather than cycle-dependent process under constant load or stress which may be deformation or crack dominated. The equivalent mechanism when the strain limits are fixed is known as stress relaxation. Both processes may occur in a solder joint subjected to thermal cycles, especially when the temperature-time profile contains dwell periods. According to the component and the operating conditions these properties have a significant effect on performance. The underlying question in the present context is the comparative behaviour of lead-free solders and those containing lead. This point is now addressed.

3.1 Monotonic tensile properties 3.1.1 The effects of temperature and strain rate on strength An increase in temperature reduces the strength of all engineering materials but in a manner that is specific to the material under consideration, and in particular, the homologous temperature range involved. For solders, an increase from 210 to 758C (0:55 , T h , 0:70; where Th is the homologous temperature) produces effects of significantly different magnitude according to the particular


alloy and the strain rate at which strength is determined. For example, the tensile strength of Sn-37 Pb, measured at a strain rate of 1 £ 1021 s21 is approximately halved on increasing the temperature from 210 to 758C, and the effect is enhanced at diminishing strain rates (Plumbridge and Gagg, 1999) (Figure 4). While the trends are generally similar for the lead-free alloys, both Sn-0.5 Cu and Sn-3.5 Ag appear less sensitive to temperature. Proof stress values follow a similar pattern. The salient point is that accurate values of strength pertaining to the alloy, temperature and strain rate are necessary for reliable modelling. Even when temperature is fixed, a change in the rate of deformation may have a significant effect on strength, with the lower strain rates associated with reduced strength

Figure 4 Effect of temperature on the strength of solder alloys. (a) Sn-37Pb, (b) Sn-3.5Ag, and (c) Sn-0.5Cu. Open points: tensile strength, closed points: (0.2 per cent) proof stress (Plumbridge and Gagg, 1999)

(Figure 5). For example, at 2108C, a reduction in strain rate from 102 1 to 102 6 s2 1 produces a greater than threefold fall in tensile strength for Sn-37 Pb, whereas the lead-free alloys are less sensitive, exhibiting strength reductions of around 2-2.5 times (Plumbridge et al., 2003). In long term applications, strain rates may be extremely low, so the use in modelling of strength data determined from higher strain rate tests may be severely non-conservative. However, the lower sensitivity of lead-free alloys is some consolation.

3.1.2 Ductility Ductility is considerably less sensitive to temperature and strain rate than strength. Solders operate at temperatures well above the possibility of any ductile – brittle transition (as occurs in steels) and can be regarded as ductile materials. Ductility measurements, either from strain to fracture or reduction in area, are generally less precise than strength determinations. Figure 6 indicates that Sn-37 Pb and Sn-0.5 Cu are more ductile than the silver-containing alloys, although few points fall below a 20 per cent ductility level. Within the range examined, there are no clear trends regarding the influence of temperature or strain rate.

3.2 Creep Creep can be manifested by excessive deformation and fracture in unconstrained situations or by stress relaxation, internal cracking and failure where geometrical constraint exists. It is a time-dependent, thermally-activated, process and extremely temperature sensitive. For example, the creep rupture lives of Sn-37Pb at 250, 22 and 1258C with a constant stress of 10 MPa are roughly 104, 30 and 0.1 h, respectively (Figure 7) – a variation of 105 times (Plumbridge and Gagg, 2002). Lead-free alloys are similarly sensitive to temperature, although direct comparisons on the basis of applied stress are sometimes difficult due to extended rupture times. With an applied stress of 30 MPa, for example, the rupture times of an as-cast Sn-3.8Ag-0.7Cu solder at 1258C, RT and 2108C are approximately 0.1, 200 and 8 £ 104 (Plumbridge et al., 2001a). These differences can be seen in the different slopes of the stress vs rupture time plots at various temperatures. The creep properties of Sn-0.5Cu are broadly similar to those of Sn-37Pb, but the resistances of the binary and ternary silver-containing alloys are much higher and their sensitivity to temperature is greater (Plumbridge et al., 2001a). From the modelling and reliability perspectives, the need to know creep properties over the range of the service cycle is therefore most important in these alloys. The benefits of greater creep resistance in the silver-containing alloys arise at the expense of ductility. For example, creep strain to fracture in the ternary alloy is usually below 20 per cent at temperatures between 210 and 1258C but rarely falls below 10 per cent. An important consequence of the difference in nature between Sn-37Pb and the lead-free alloys, is that the dispersion strengthened characteristics of the latter result in very high stress exponents in the minimum strain rate – applied stress relationship ð1_m ¼ C s n Þ: While those for tinlead are in the range 3-7, n values for the ternary Sn-3.8Ag0.7Cu alloy generally exceed 10 and increase with diminishing temperature to 18 at 2108C (Plumbridge et al., 2001a). Such high values cause problems for reliable modelling and may lead to convergence difficulties in finite element analysis. Creep behaviour may be used as a vehicle for two other points of debate. The first relates to prior thermal history and Standards for Evaluation of Mechanical Properties. Due to the low melting point of solders, their microstructure in the as-cast condition is inherently unstable at ambient temperature ðT h < 0:6Þ: Consequently, significant variability may be observed in determined properties. Some workers and proposed standards advocate a stabilisation anneal (such as 1 h at 1008C) to produce a microstructure which will remain essentially constant during testing.

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The contrary view is that since joints are small castings and experience no further heat treatment, it is more realistic to assess properties in the as-cast condition. Creep tests on Sn-3.5Ag at 758C indicate a potentially significant effect of a factor of about seven times increase in the minimum creep rate after annealing (Plumbridge et al., 2001b). This was not translated into a proportional effect of the creep life, because the changes in ductility opposed the effects of those in strain rate thereby reducing the overall effect (Figures 8 and 9). This emphasises the importance of selecting the salient parameter in design-strain to failure or lifetime.

Figure 6 The influence of temperature on ductility at different strain rates for: (a) Sn-37Pb, (b) Sn-3.5Ag and (c) Sn-0.5Cu. Open points: Strain to failure. Closed points: Reduction of area (Plumbridge and Gagg, 1999)

‘. . .When the performance of joints is considered, the observed behaviour becomes even more specific, involving additional factors such as joint geometry, thickness and profile of the intermetallic compound (IMC). Failure generally occurs by the initiation and growth of cracks in the highly strained regions in the solder, adjacent to the IMC.. . .’

A second factor which has attracted much debate is the potential of tin-zinc based solder alloys. Although having melting points much closer to that of Sn-37Pb, they are reportedly prone to oxidation and fluxing problems (Richards et al., 1999) and have been investigated sparingly in Europe. In terms of creep, Figure 10 shows that for lives of up to 100 h they can match the silver-containing alloy but at longer lives (lower stresses) they are intermediary between, Sn-3.5Ag and Sn-0.5Cu (Shoji et al., 2004). With further stress reduction (lives above 1,000 h) their creep performance becomes progressively more inferior to the silver-containing alloys. This is a good example of the need to carry out realistically timed creep tests and, perhaps further impetus for tackling the oxidation/fluxing challenge?

3.3 Fatigue Owing to their small yield stress, the vast majority of conditions experienced by solders in service fall into the high-strain category, i.e. there is significant plasticity involved. An exception is high frequency vibration

Figure 5 Influence of strain rate on the strength of solder alloys at 2 108C (Plumbridge et al., 2003)

involving numerous elastically-dominated cycles, with the performance of a material governed by its strength. Since ductility is a principal factor in determining high strain fatigue life (Plumbridge et al., 2003) it is not surprising, from the previous comments regarding that property, that low cycle fatigue endurance is relatively insensitive to temperature, composition and many other parameters. This is shown well in Figure 11 which demonstrates that the continuous cycling fatigue life of bulk Sn-37Pb varies by less than an order of magnitude in the temperature range 240-1508C (Shi et al., 2000). Lead-free solders containing bismuth, however, are very sensitive to composition. At room temperature, the fatigue life of Sn-3.5Ag diminishes progressively with bismuth content, until at 10 per cent bismuth it is 3-4 orders of magnitude lower than the pure binary alloy (Kariya and Otsuka, 1998) (Figure 12). In contrast to bismuth, Kariya and Otsuka (1998) also found that additions of copper, zinc or indium had little effect on fatigue performance of the alloy. These exceptional data

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Figure 7 Effect of stress on the creep life of Sn-37Pb at various temperatures (Plumbridge et al., 2001a, b)

Figure 8 Minimum strain rate as a function of stress for Sn-3.5Ag. Process A – as cast; Process B – as cast, and annealed at 1008C for 1 h (Plumbridge et al., 2001b)

Figure 9 Effect of prior history on creep strain to failure. Process A – as cast; Process B – as cast, and annealed at 1008C for 1 h (Plumbridge et al., 2001b)

indicate the potential pitfalls of thinking across behaviour and properties from one alloy to another. Service cycles which include dwell periods or asymmetric heating/cooling rates may result in life reductions of a factor a 10 or higher, although there appears little consistency in the observed trends to date. When the performance of joints is considered, the observed behaviour becomes even more specific, involving additional factors such as joint geometry, thickness and profile of the intermetallic compound (IMC). When thermal effects are constrained, as after a few thermal cycles, the location and accumulation of damage in mechanical shear fatigue and in thermomechanical cycling are similar (Chen et al., 2002; Howell et al., 2002). Failure generally occurs by the initiation and growth of cracks in the highly strained regions in the solder, adjacent to the IMC. While some

findings suggest that solder type has little effect on the joint strength after thermal cycling (Harrison et al., 2001), other data with different joints and solders seem able to discriminate the effects of small compositional changes (Kariya et al., 1999), for example, compare Figures 13 and 14. Again, addition of bismuth has a significant effect, leading to as much as a halving of residual joint strength. It is evident from such, often conflicting, information that ab initio design and modelling is a long way off. There is much to understand.

4. Summary The purpose of this paper has been to raise the profile of factors that may be safely neglected in routine applications

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Figure 10 Comparative creep performance of Sn-Zn-Bi alloy at 758C (Shoji et al., 2004)

Figure 11 Effect of temperature on the continuously cycled fatigue performance of bulk Sn-37Pb (Shi et al., 2000)

Figure 12 Influence of small additions of bismuth on the fatigue performance of a bulk Sn-3.5Ag alloy (Kariya and Otsuka, 1998)

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Figure 13 Effect of thermal cycling on joint strength (Harrison et al., 2001)

Figure 14 Effect of bismuth additions on the thermal cycling performance of a QFP joint with a Sn-3.5Ag based alloy (Kariya et al., 1999)

several years (Hedges, 1960) and the balance between thermodynamics and kinetics indicates that the transformation in pure tin occurs “most rapidly” at 2408C. At the Open University, both bulk and board samples have experienced low temperature (218 and 2408C) ageing for several years, but the results are far from complete. While it would be imprudent to say at this stage that tin pest will become a serious problem for extended low temperature (sub-zero) applications involving some of the most common lead-free solder alloys, it is appropriate to highlight the possibility. For example, failure of a satellite, after half of its projected 20-year life, due to disintegrating solder joints would be a costly exercise. With regard to service performance and long term reliability, the prognosis for the implementation of lead-free solders appears optimistic. Despite the difference in the intrinsic type of alloy, the influential mechanical properties of the more dilute lead-free systems are similar to, or exceed those of traditional Sn-37Pb. Substantial advantages accrue with the silver-bearing alloys in terms of strength and creep resistance, at the expense of a slight loss of ductility. However, within that generalisation many factors remain unresolved. For example, the profound effect of bismuth on mechanical and TMF is exceptional. There is a pressing need to understand the reasons for this and to identify other additions that may produce similar effects. Further, since the properties of the Sn-Zn-Bi alloys are adequate and there are no material cost penalties, there seems further impetus for solving the processing difficulties associated with them to enable their lower melting points to be exploited. For high reliability, long term applications, the capability of empirical approaches, however, extensive and accelerated, must be in question. They will become uneconomic at best and potentially unreliable. In many cases, available mechanical property data have “runaway” from the understanding of the mechanisms that are responsible for them. The effects of bismuth are a classic example of this. A greater understanding of the physical metallurgy-mechanical property relationship in solders is required to underpin design and lifetime prediction. It is a global challenge with enormous scope for international collaboration. The absence of consistent standards for determining properties is an additional difficulty that should be addressed with urgency.

References

operating in a benign environment. There is an inherent conservatism built into these. However, for long term usage, there is an automatic requirement for higher reliability but it is under these very conditions of prolonged exposure to temperature, cyclic temperature and extended times that the additional factors described above may come into play. The natural reflex of thinking across from one alloy to another, or from one set of operating conditions to another, is common and understandable but it can be dangerous. Each specific combination of solder alloy, joint type and service conditions should be considered on its own merits. The current paucity of understanding of the mechanical behaviour of solder alloys and solder joints demands this. Several of the features considered here cannot be identified and evaluated by accelerated testing. For example, the incubation period for tin pest formation may be

Burgers, W.G. and Green, L.J. (1957), “Mechanism and kinetics of the allotropic transformation of tin”, Faraday Soc. Discussions, Vol. 23, pp. 183-95. Chen, K.C., Telang, A. and Lee, J.G. (2002), “Damage accumulation under repeated reverse stressing of Sn-Ag solder joints”, J. Electron. Mater., Vol. 31 No. 11, pp. 1181-9. Harrison, M., Vincent, J. and Steen, H.A.H. (2001), “Lead-free reflow soldering for electronics assembly”, Soldering and Surface Mount Technology, Vol. 13, pp. 21-38. Hedges, H.E. (1960), Tin and its Alloys, Edward Arnold Ltd, London, p. 51. Howell, J., Telang, A. and Lee, J.G. (2002), “Surface damage accumulation in Sn-Ag solder joints under large reversed strains”, J. Mater. Sci.: Mater. Electron., Vol. 13 No. 6, pp. 335-44. Kariya, Y. and Otsuka, M. (1998), “Mechanical fatigue characteristics of Sn-3.5Ag-X (X ¼ Bi, Cu, Zn and In) solder alloys”, J. Electron. Mater., Vol. 27, pp. 1229-35. Kariya, Y., Gagg, C.R. and Plumbridge, W.J. (2001), “Tin pest in solder alloys”, Soldering and Surface Mount Technology, Vol. 13, pp. 39-40. Kariya, Y., Hirata, Y. and Otsuka, M. (1999), “Effect of thermal cycles on the mechanical strength of quad flat pack leads/Sn3.5Ag-X (X ¼ Bi and Cu) solder joints”, J. Electron. Mater., Vol. 28, pp. 1261-9. Lee, J.G., Telang, A.U., Subramanian, K.N. and Bieler, T.R. (2002), “Modeling thermomechanical fatigue behaviour of Sn-Ag Joints”, J. Electron. Mater., Vol. 31, pp. 1152-9.

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Liu, X.W. and Plumbridge, W.J. (2003), “Damage produced in model (Sn-37Pb) joints during thermomechanical cycling”, J. Electron. Mater., Vol. 32, pp. 278-86. Liu, X.W. and Plumbridge, W.J. (2004), “Autodegradation of SnAg-Cu alloys during thermal cycling” (in press). Plumbridge, W.J. and Gagg, C.R. (1999), “Effects of strain rate and temperature on the stress-strain response of solder alloys”, J. Mater. Sci.: Mater in Electron., Vol. 10, pp. 461-8. Plumbridge, W.J. and Gagg, C.R. (2002), “The influence of temperature on the creep of tin-37 lead solders”, invited paper to Symposium on Pb-free and Pb-bearing Solders, TMS Fall Meeting, Columbus, OH. Plumbridge, W.J. and Gagg, C.R. (2004), unpublished work. Plumbridge, W.J., Gagg, C.R. and Peters, S. (2001a), “Creep of leadfree solders at elevated temperatures”, J. Electron. Mater., Vol. 30, pp. 1178-83. Plumbridge, W.J., Kariya, Y. and Gagg, C.R. (2001b), “The influence of processing history on the creep of tin-3.5 silver alloys”, in, Seventh Symp. on Microjoining and Assembly Technology in Electronics, Yokohama, pp. 451-6.

Plumbridge, W.J., Matela, R.J. and Westwater, A. (2003), Structural Integrity in Electronics-Enhancing Performance in a Lead-free Environment, Chapter 5, Kluwer, Dordrecht Boston, London. Richards, B., Levogner, C.L., Hunt, C.P., Nimmo, K., Peters, S. and Cusack, P. (1999), Lead-free Soldering – An Analysis of the Current Status, DTI. Shi, X.O., Pang, H.L.J., Zhou, W. and Wang, Z.P. (2000), “Low cycle fatigue analysis of temperature and frequency effects in eutectic solder alloy”, Int. J. Fatigue, Vol. 22, pp. 217-28. Shoji, I., Gagg, C.R. and Plumbridge, W.J. (2004), “Creep properties of Sn-8 mass per cent Zn-3 mass per cent Bi lead-free alloy”, J. Electron. Mater.(in press). Subramanian, K.N. and Lee, J.G. (2003), “Physical metallurgy in lead-free electronic solder development”, Journal of Metals, Vol. 55, pp. 26-32. Subramanian, K.N. and Lee, J.G. (2004), J. Mater Sci.: Mater in Electron., Vol. 15, pp. 235-40.

Comparison of solder ball shear strengths for various nickel platings on the bond pads of a PBGA substrate

Eric C.C. Yan Department of Mechanical Engineering, Electronic Packaging Laboratory, Hong Kong University of Science and Technology, Kowloon, Hong Kong S.W. Ricky Lee Department of Mechanical Engineering, Electronic Packaging Laboratory, Hong Kong University of Science and Technology, Kowloon, Hong Kong X. Huang Foxconn Ltd, Shenzhen, People’s Republic of China

Keywords Product reliability, Solders, Shear strength, Semiconductor technology

Abstract This paper presents an experimental study to assess the reliability of solder ball attachment to the bond pads of PBGA substrate for various plating schemes. The basic structure of the under bump metallisation is Cu/Ni/Au. Three different kinds of electroless plating solutions are used to deposit the Ni layer, namely, Ni-B, Ni-P (5 per cent), and Ni-P (10 per cent). Also, conventional electrolytic Ni/Au plating is performed to provide a benchmark. After solder ball attachment, mechanical tests are conducted to characterize the ball shear strength for comparison. Furthermore, some specimens are subjected to multiple reflows to investigate the thermal aging effect.

Received: 20 November 2003 Revised: 13 February 2004


Introduction The plastic ball grid array (PBGA) package has attracted substantial attention since its first appearance in the electronics industry in the late 1980s. Recent technology trends show that PBGAs will dominate the market for packages with pin counts from .208 to 420 in the next decade. Owing to the tremendous mass production volumes expected, the cost and the reliability of PBGAs are the main issues for the electronics manufacturing industry (Lau, 1995). One of the features of PBGA packages is that they are surface mount technology (SMT) compatible. For surface mounted components (SMC), the solder joints are not only the means for passage of electrical signals, power, and ground, but also the mechanical support to hold the module in position on the printed circuit board (PCB). Since the solder volume and the stand-off height are rather small, the solder joint reliability of SMCs is always a concern to the packaging engineers (Lau and Pao, 1997). Currently, the standard package configuration for PBGAs is to attach eutectic Pb/Sn solder balls to the bond pads on the bottom side of a BT substrate. The surface finishing metallisation on the solder bond pads is Ni/Au deposited by electrolytic plating. However, since this process requires routing traces to connect all of the bond pads together, a considerable amount of space is wasted on the BT substrate (which leads to a higher production cost). In order to avoid this deficiency, an electroless Ni/Au plating process is desired for the fabrication of PBGA substrates. However, the conventional electroless Ni plating solutions available in the industry usually contain a relatively high concentration (9-10 per cent) of phosphorus (P) that would reduce the solder joint reliability (Bradley and Banerji, 1996; Martyak and McCaskie, 1996). As a result, the electroless Ni/Au plating process is still not yet adopted by the packaging industry for manufacturing PBGA substrates. In order to reduce or to eliminate the phosphorus, two other types of electroless plating solutions may be considered. One is a Ni-P solution with a low phosphorus-content (5 per cent), and the other is a Nickel-Boron (Ni-B) solution. However, the effects on solder joint reliability due to these alternative electroless Ni plating solutions are not available in the literature. The Emerald Research Register for this journal is available at www.emeraldinsight.com/researchregister

The present study is aimed at the assessment on the reliability of solder ball attachment to the bond pads of PBGA substrate with various plating schemes. The basic structure of the under bump metallisation (UBM) is Cu/Ni/ Au. The electroless Ni plating solutions under evaluation include Ni-B, Ni-P (5 per cent), and Ni-P (10 per cent). All of the plated Ni layers are finished with immersion Au for the prevention of oxidation and the improvement of solder wettability. Conventional electrolytic Ni/Au plating is also performed to provide a benchmark. The reliability of solder ball attachment is characterized by mechanical ball shear tests. Furthermore, some specimens are subjected to multiple reflows to investigate the effect of thermal aging. In addition to the ball shear tests, scanning electron microscopy (SEM) is performed to inspect the cross-section and the fracture surface of the tested specimens for failure analysis. The obtained results may serve as a reference for selecting the optimal plating process for PBGA substrate manufacturing.

Specimen preparation The objective of this study is to investigate the effect of various UBM plating schemes on the reliability of PBGA solder joints. The mechanical ball shear tests were employed as a means to evaluate the reliability. During the course of this study, many PBGA substrates were fabricated. The specimens were BT laminates with one surface fully covered with a layer of Cu. The solder bond pads were defined by the solder mask opening with a diameter of 0.5 mm. On the top of bond pads two more layers of metallisation (Ni/Au) were deposited using various plating schemes as shown in Table I. The detailed processing parameters for Ni plating are given in Table II (Fang et al., 1992; Parker, 1987). After surface finishing, the thicknesses of corresponding metal layers are listed in Table I. The cross-section of a typical Cu/Ni/Au metallisation structure is shown in Figure 1. Once the UBM was prepared, the conventional PBGA ball placement process was performed to attach solder balls to the bond pads on the substrate. The diameter of the solder balls used in the present study was 0.76 mm (30 mil) and the solder material was 63Sn/37Pb. After dispensing a flux paste (Alphametals WS609) onto the bond pads, the solder balls were manually placed onto the pads and reflowed using the The current issue and full text archive of this journal is available at www.emeraldinsight.com/0954-0911.htm

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Eric C.C. Yan, S.W. Ricky Lee and X. Huang Comparison of solder ball shear strengths for various nickel platings on the bond pads of a PBGA substrate Soldering & Surface Mount Technology 16/2 [2004] 21–26

Table I Four types of under bump metallisation plating scheme under investigation Under bump metallisation plating scheme Electrolytic Ni + electrolytic Au Electroless Ni-B + immersion Au Electroless Ni-P (5 per cent) + immersion Au Electroless Ni-P (10 per cent) + immersion Au

Thickness of Ni layer (mm)

Thickness of Au layer (mm)

5.55 ^ 0.72 6.13 ^ 0.22 6.15 ^ 0.17 5.58 ^ 0.34

1.37 ^ 0.014 0.18 ^ 0.006 0.22 ^ 0.018 0.15 ^ 0.005

Table II Comparison of parameters for various Ni plating processes Parameters\UBM Temperature (8c) Plating time (Min) pH Loading factor Agitation Filtration Filtration frequency

Electrolytic Ni

Electroless Ni-B

Electroless Ni-P (5 per cent)

Electroless Ni-P (10 per cent)

50-60 5 3.5-4.5 ASD: 0.5-10 A/dm2 Moderate Continuous (3-5 mm) 3 times/h

60-70 40 6.8-7.5 0.6-1.2 dm2 Mild/part Continuous (3-5 mm) Batch filtration after each work

38-49 30 8.0-9.0 0.25-2.5 dm2 Continuous Continuous (3 mm) 10-15 times/h

85-95 15 4.6-5.2 0.5-2.5 dm2 Continuous Continuous (30 mm) 5 times/h

Figure 1 Cross-section of a typical Cu/Ni/Au structure

temperature profile given in Figure 2. A typical crosssection micrograph of an attached solder ball is shown in Figure 3.

Ball shear tests and experimental results In this study, mechanical shear tests were employed to characterize the strength of solder ball attachment to the bond pads of PBGA substrates. Such ball shear strength measurements are considered to be an index for solder joint reliability. The ball shear tests were performed using a Dage S4000 machine. A schematic diagram of the testing configuration is presented in Figure 4. The ram speed was 100 mm/s and the gap between the ram tip and the base plane was 50 mm. After each run, the value of peak shear force was recorded. In order to investigate the effect of thermal aging, some specimens were subjected to multiple reflows (1-time, 5-time, 10-time reflows) using the same temperature profile shown in Figure 2. From the experimental results shown in Table III and Figure 5, it is found that the electrolytic Ni/Au plating leads to the highest ball shear strength. Among the UBMs with electroless plating, Ni-B gives the best results. Furthermore, the fact that Ni-P (5 per cent) is better than Ni-P (10 per cent) indicates that phosphorus (P) is an undesirable element. On the other hand, for most cases under investigation, the testing results reveal that multiple reflows may slightly

[ 22 ]

reduce the solder ball shear strength. However, the magnitudes of these reductions are not very significant.

Scanning electron microscopy and failure analysis In view of the fact that P usually causes the enbrittlement of metals, the experimental results obtained from mechanical ball shear tests seem to be reasonable. In order to further understand the failure mechanism in the present specimens, a series of cross-sections followed by SEM were performed. The SEM micrographs are presented in Figures 6-8. Figure 6 shows typical cross-section pictures after ball shear tests. It is found that, for all cases under investigation, the fracture surface cuts through the solder ball. However, for UBMs with electrolytic Ni/Au plating and electroless Ni-B plating, there is a relatively large portion of solder remaining on the bond pad. Besides, it can be seen that the fracture surfaces of these two cases always have a kink while the fracture surfaces associated with electroless Ni-P (both 5 and 10 per cent) plated UBMs are rather flat. The top-view pictures presented in Figure 7 show similar features and the close-up micrographs in Figure 8 again confirm the aforementioned phenomenon. It is believed that these observed characteristics in the failure mechanisms contribute to the variations in solder ball shear strength. For the UBMs having a lower ball shear strength, it is suspected that there should be some evidence of metal


Figure 2 Reflow profile for solder ball placement

Figure 3 Cross-section of an attached solder ball

enbrittlement on the surfaces. In order to verify this, energy dispersive X-ray spectroscopy (EDX) was performed on the fracture surfaces shown in Figure 8. The corresponding spectrums are presented in Figure 9. It is identified that, for UBMs with electroless Ni-P (both 5 and 10 per cent), the fracture surfaces contain a small amount of P. In the literature, it is well known that P may cause enbrittlement in metals, e.g. Tai et al. (2002). Therefore, the inspection results by SEM and EDX seem to give a qualitative explanation for the differences in ball shear strength. However, more rigorous failure analyses are required in order to obtain quantitative correlations between all of the experimental data.

Concluding remarks An experimental study is presented in this paper to assess the effect of various UBM plating schemes on the reliability of solder ball attachment to the bond pads of a PBGA substrate. Three different kinds of electroless

Figure 4 Schematic diagram of the ball shear test

Table III Experimental results of ball shear tests No. of reflow

No. of samples

Strength (mean, g)

Standard deviation

Electrolytic Ni/Au

1 5 10

24 21 30

1,905 1,962 1,863

58 77 65

Electroless Ni-B + Imm. Au

1 5 10

30 30 30

1,790 1,727 1,588

74 64 93

Electroless Ni-P (5 per cent) + Imm. Au

1 5 10

30 30 30

1,658 1,540 1,448

52 89 103

Electroless Ni-P (10 per cent) + Imm. Au

1 5 10

30 30 29

1,331 1,222 1,155

47 71 59

Plating scheme

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Figure 5 Comparison of ball shear testing results

Figure 6 Cross-section micrographs after ball shear tests

[ 24 ]


Figure 7 Top view micrographs after ball shear tests

Figure 8 Close-up view micrographs after ball shear tests

[ 25 ]


The Research Grant Council of Hong Kong sponsored this study through the grants of HKUST6078/00E and HKUST6231/01E to the Hong Kong University of Science and Technology (HKUST). The authors wish to acknowledge this sponsorship. In addition, the support from Shipley Ronal Asia Ltd in supplying plating solutions and from the EPACK Lab, HKUST, in providing ball shear testing equipment are appreciated.

[ 26 ]

Figure 9 Typical EDX spectrums for the fracture surfaces after a single reflow

plating solutions, namely, Ni-B, Ni-P (5 per cent), and Ni-P (10 per cent), were used to deposit the Ni layer. The surface was finished with immersion Au to prevent oxidation and to improve the solder wettability. Also, conventional electrolytic Ni/Au plating was performed for use as a benchmark. After solder ball attachment, mechanical tests were conducted to characterize the ball shear strength for comparison. Furthermore, some specimens were subjected to multiple reflows to investigate the thermal aging effect. The testing results indicate that, compared to the electroless Ni-P plating, the electroless Ni-B plating may lead to a better solder ball shear strength. However, the conventional electrolytic Ni/Au plating still gives the highest ball shear strength. For most cases under investigation, multiple reflows seemed to decrease the solder ball shear strength slightly. However, the amount of reduction was not very significant. In addition to the ball shear tests, SEM and EDX were performed to inspect the cross-sections and the fracture surfaces of the tested specimens. From the failure analyses, certain characteristics in failure mechanism were identified.

References Bradley, E. and Banerji, K. (1996), “Effect of PCB finish on the reliability and wettability of ball grid array packages”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, Vol. 19 No. 2, pp. 320-30. Fang, J.L., Ye, X.R. and Fang, J. (1992), “Factors influencing solderability of electroless Ni-P deposits”, Plating and Surface Finishing, pp. 44-7. Lau, J.H. (1995), Ball Grid Array Technology, McGraw-Hill, New York, NY. Lau, J.H. and Pao, Y.H. (1997), Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, McGraw-Hill, New York, NY. Martyak, N.M. and McCaskie, J.E. (1996), “Speciation in electroless nickel solutions”, Plating and Surface Finishing, pp. 62-6. Parker, K. (1987), “The formulation of electroless nickel-phosphorus plating baths”, Plating and Surface Finishing, pp. 60-5. Tai, S.F., Ourdjini, A., Khong, Y.L., Venkatesh, V.C. and Tamin, M.N. (2002), “Effect of phosphorus content and solid state aging on intermetallic formation between lead-free Sn-Ag-Cu solder and electroless nickel/immersion gold under bump metallurgy”, Proc. 4th International Symposium on Electronic Materials and Packaging, Kaohsiung, Taiwan, ROC, pp. 267-70.

Strategies for improving the reliability of solder joints on power semiconductor devices

Keywords Soldering, Joining processes, Stress (materials), Semiconductor devices

Abstract In this paper, some strategies taken to improve the reliability of solder joints on power devices in single device and multi-chip packages are presented. A strategy for improving solder joint reliability by adjusting solder joint geometry, underfilling and utilization of flexible substrates is discussed with emphasis on triplestacked solder joints that resemble the shape of an hourglass. The hourglass shape relocates the highest inelastic strain away from the weaker interface with the chip to the bulk region of the joint, while the underfill provides a load transfer from the joints. Thermal cycling data show significant improvements in reliability when these techniques are used. The design, testing and finite-element analyses of an interconnection structure, termed the DimpleArray Interconnect, for improving the solder joint reliability is also presented.

Received: 12 September 2003 Revised: 13 January 2004


Guo-Quan Lu Departments of Materials Science and Engineering and Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, Virginia, USA Xingsheng Liu Departments of Materials Science and Engineering and Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, Virginia, USA (Currently with Corning Inc., Science and Technology Center, Corning, NY, USA) Sihua Wen Department of Biochemistry and Biophysics, University of Pennsylvania, Philadelphia, Pennsylvania, USA Jesus Noel Calata Department of Materials Science and Engineering, Virginia Polytechnic Institute and State University, Blacksburg, Virginia, USA John G. Bai Department of Materials Science and Engineering, Virginia Polytechnic Institute and State University, Blacksburg, Virginia, USA

Introduction

Stacked solder bump interconnection

Wirebonding remains as the most widely used technology for interconnecting power semiconductor devices because of its known reliability and the maturity of the process and equipment behind it. However, for high-voltage, highcurrent applications, concerns have been raised on issues such as electrical overstressing, large mutual coupling effects, parasitic oscillations, mechanical damage during ultrasonic bonding and limitations on heat dissipation due to its two-dimensional structure (Lall et al., 1997; Wen and Lu, 2000; Xing, 1999). Advances in device technology have reduced the intrinsic silicon resistance, particularly in low power devices, down to levels that are now comparable to or even lower than those conventional packages before a die is placed within them. Chip-level and module-level packaging resistances, therefore, currently account for as much as 90 percent of the overall packaged device resistance (Bindra, 2000). Efforts to further reduce resistance have, therefore, shifted to the device packaging, resulting in the introduction of various innovative interconnect and packaging techniques. Some of these have been implemented in commercial packages. Following the lead of IC manufacturers, power device makers have begun using variations of flip chip packaging where interconnection is attained using solder bumps. Others have gone even further by adopting large-area interconnections. Some of these techniques include the Bottomless Flip Chip from Fairchild Semiconductor (Klein, 2000), CopperStrap (Mannion, 1999) and DirectFET (Morrison, 2002) from International Rectifier, and PowerConnect from Vishay Siliconix (Bindra, 2000) to name a few. Interconnect technologies that were developed at Virginia Tech include a three-dimensional stacked solder joint interconnection (Liu et al., 2001a, b) and dimple array interconnect (DAI) (Wen et al., 2001). These two technologies are the subject of discussion in this paper.

Stacked solder bumping is an extension of the well established solder bump technology. It has some important differences from the conventional bumping technique commonly used in flip chip packages. It provides the ability to control the joint height and shape by appropriate modification of design parameters. It is compatible with surface mount technology and can be adopted for volume production. The major disadvantage is that it involves additional process steps for solder deposition and reflow. The melting temperatures of the solders, bumping process compatibility, manufacturability and reliability are the major factors that influence the choice of solder compositions. Solder composition has a significant influence on solder joint reliability. Eutectic lead-free solder (Sn-3.5Ag) has excellent characteristics with improved reliability over eutectic lead-tin (Harada and Satoh, 1990). Because the melting points of the solder alloys vary over a range of temperatures, a temperature hierarchy must be maintained when selecting the alloy composition for each layer in order to preserve the structural integrity of the joint during each step of the process. For our research, the inner cap was made of lead-free Sn-3.5Ag alloy with a melting temperature of 2218C. The middle bump is of Pb-10Sn alloy with a melting point of 2688C. The outer cap is eutectic leadtin (Sn-37Pb) with a melting temperature of 1838C. The height of the triple stacked joint ranged from 0.5 to 1.25 mm (20-50 mil). The power device was an insulated gate bipolar transistor (IGBT) with 1 mm wide pads. The middle bump is actually a solder ball that is dropped into the structure during processing. The use of a solder ball as the middle bump does not pose a technical hurdle for volume production since solder ball mounting technology is mature and automated (Shimokawa et al., 1997, 1998). The composition of the solder ball is also an important consideration in determining the required reflow temperatures due to potential alloy reactions that can affect the standoff height and shape. Compared with lower-power


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Guo-Quan Lu, Xingsheng Liu, Sihua Wen, Jesus Noel Calata and John G. Bai Strategies for improving the reliability of solder joints on power semiconductor devices Soldering & Surface Mount Technology 16/2 [2004] 27–40

devices such as computer microprocessors, the interconnect structures are large and far smaller in number because the primary aim is to form reliable large-area interconnects with high current-carrying capacity to accommodate the large power requirements for such devices. In principle, only three interconnections (source, drain, gate) are necessary but very wide interconnect areas tend to pose reliability problems, primarily because of the coefficient of thermal expansion (CTE) mismatch between the interconnected structures; hence, a greater number of connections is typically used.

Figure 1 (a) Stacked solder joints on IGBT pads and (b) close-up image of a stacked solder joint

Bumping process The stacked solder bumping technique consists of three basic processes: stencil printing, solder ball placement and reflow. In the stencil-printing process, Sn-3.5Ag solder paste is deposited on the bonding pads by stencil printing. The paste is pre-baked in order to retain its shape for the next process. In the solder ball placement process, a stencil with windows corresponding to the bond pads is placed on top of the chip and high-lead solder balls are dropped through the windows. Finally, the solder paste is reflowed at a peak temperature of 2508C, which is above the melting point of the paste alloy, but below that of the solder ball. The reflow is done in a nitrogen-hydrogen atmosphere to minimize oxidation that may cause defects at the interfaces. A device with solder bumps made by this process is shown in Figure 1. The under bump metallization is Ti/Ni/Ag.

Flip chip assembly process The triple-stacked solder joint fabrication is completed in the flip chip assembly process. A photoimageable solder mask is applied to a pre-patterned substrate by screenprinting. The solder mask is then exposed to UV light to create openings on the substrate corresponding to the bumped pads on the chip and alignment marks for the mounting process. Solder paste (Sn-37Pb) is stencil-printed on the bond pads on the substrate and the bumped die is flipped over and attached to the substrate. The assembly is then heated to melt the outer solder and form a metallurgical bond with the bond pad. The reflow is carried out at a peak temperature of 2108C. The maximum temperature is dictated by the melting point of the solder paste alloy (1838C) and the need to maintain the temperature hierarchy to preserve the structure. After flip chip bonding and cleaning, electrical testing was performed prior to underfilling of the gap with a high-performance epoxy underfill. Devices mounted on the substrate by this flip chip process prior to underfilling are shown in Figure 2. A crosssectional view of the triple-stack solder joint obtained with a scanning electron microscope (SEM) is shown in Figure 3.

Reliability tests The reliability of the solder joints was evaluated using an adhesion test and an accelerated temperature cycling test. A destructive tensile test was performed on both processed and temperature cycled samples to determine the adhesion strength of different solder joint configurations and to study the effect of temperature cycling on the adhesion strength and fracture behavior of the joints. During the accelerated temperature cycling test, in situ electrical resistance measurements and periodic observations by scanning acoustic microscopy and optical microscopy were conducted to monitor the condition of the solder joints. The electrical resistance of the solder joints was measured using a four-point probe method and was used as the failure criterion. A 20 percent increase in electrical resistance was used as the criterion for failure. The three solder joint configurations in the test samples are shown in Figure 4. They are single bump barrel-shaped solder joints, triple-stack barrel-shaped solder joints and triple-stack hourglass-shaped solder joints. The single bump solder joint is made of eutectic lead-tin solder (Sn-37Pb). Temperature cycling was performed on the samples to assess the resistance and robustness of the package structure to extreme temperatures and to determine the effect of

[ 28 ]

alternating exposures to these temperatures. The tests were conducted in an Envirotronics thermal cycling chamber. The test samples were periodically removed from the chamber and tested for integrity using electrical resistance measurements. As shown in Figure 5(a), there are seven solder joints in each device and each chip was attached to a test vehicle as shown in Figure 5(b). For each type of joint, three samples were tested for a total of 21 joints each. The test samples were not underfilled. The temperature cycling was carried out between 240 and 1258C. Heating and cooling rates for both were 6.68C/min and dwell time was 5 min.

Electrical resistance measurements The normalized electrical resistance curves for the three types of joints are shown in Figures 6-8. The curves can be divided into three regions, each corresponding to one of the three fatigue degradation phases, namely crack initiation, crack propagation and catastrophic failure. The crack initiation phase is characterized by a period of very little increase in electrical resistance (,5 percent), while in the crack propagation phase the electrical resistance increases at a higher rate. The electrical resistance dramatically increases in the catastrophic failure stage. Using a 20 percent increase in electrical resistance as the failure criterion, the fatigue life of a single bump barrel-shaped joint is approximately 2,200 cycles, while that of a triplestack barrel-shaped joint is about 3,000 cycles. The average


Figure 2 Flip chip on substrate assembly before underfilling of the gap (Note the high standoff height attainable)

fatigue life of the stacked hourglass-shaped joint is around 3,500 cycles which is longer than any of the barrel-shaped joints. The crack initiation time for the stacked barrelshaped joints, is roughly the same as that of the single bump barrel-shaped joints but the crack propagation time is similar to that of the stacked hourglass-shaped joints. Imperfections arising from the hand assembly of the samples and probe traces are to be expected, resulting in minor discrepancies in the measured resistances of some of the joints as exhibited by curves in Figures 6 and 7 that seem to be contradictory. However, the average of the measurements follows the trend discussed above. The important differences in the three sets of curves are shown in Figure 9. By using stacked hourglass-shaped joints, the crack initiation time is extended by 30-40 percent over that of barrel-shaped joints, which is a significant improvement. By using stacked high-standoff solder joints, the crack propagation time is increased by about 100 percent. Overall, the average fatigue life of the stacked hourglass joint is longer by about 60 percent over that of the single bump barrel joint. The longer fatigue life of the stacked hourglass joint over that of the stacked barrel joint can be traced to the longer crack initiation time. This in turn is the result of a more favorable shape or geometry. Thus, a combination of high standoff height and hourglass geometry can significantly improve the reliability of solder joints. Underfilling of the structures resulted in improved reliability for each type of joint. However, the amount of improvement varied with the type of joint, with the barrel-shaped joint benefiting the most (Liu, 2001). In the case of the highstandoff stacked hourglass joint, it is already reliable enough that the limiting factor is the die-attach layer that tends to fail earlier, thus showing little improvement with underfilling. On the other hand, the barrel-shaped joints can fail earlier than the die-attach layer such that underfilling can provide a significant improvement in the joint reliability.

temperature cycling tests. The dark areas indicate intact bonds while the light areas are cracked or debonded regions. Images were also obtained on the other types of joints for analysis. As the images show, the crack usually

Figure 4 Solder joint configurations used in the test samples: (a) singlebump barrel shape, (b) triple-stack barrel-shape and (c) triplestack hourglass shape

Failure analysis and characterization While the electrical resistance measurements provide the general trends for the effects of joint geometry and height, it does not provide a picture of the location, mode and progression of the joint failure. To monitor the state of the joints during the course of the temperature cycling tests, scanning acoustic microscopy images of the joints were obtained. A 75 MHz transducer was used for imaging. The series of images obtained at the interface of a single bump barrel-shaped joint and die (Figure 10) clearly show the progression of the crack area during the course of the

Figure 3 SEM image of a cross-section of a triple-stack solder joint

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Figure 5 (a) Dimensions (in mm) and solder joint locations on test chips, and (b) temperature cycling vehicle

Figure 6 Electrical resistance vs number of cycles for single-bump barrel-shaped solder joints

initiates at the corners and edges away from the centre of the die, a result that is to be expected when considering the stresses arising from CTE mismatch. A comparison of the crack area propagation of the single bump barrel and stacked hourglass joints is shown in Figure 11. The results clearly show a faster propagation rate for the single bump barrel joint.

[ 30 ]

Figure 12 shows typical cross sections of joints that failed by thermal fatigue. The majority of the joints failed at the solder joint-chip pad interface. Only a small fraction of the joints developed cracks at the corners of the solder jointsubstrate interface. Microcracks occur at points of high localized stress and gradually spread by fracture of the material at the edges of


the crack where there is a stress concentration. The time needed for microcracks to grow could be affected by the local stress, which may help explain why the joint shape is the dominant factor in determining crack initiation time. Generally, fatigue failure occurs first at the interfaces between the solder and die and the solder and substrate due to high thermal stress concentrations, especially at the

Figure 7 Electrical resistance vs number of cycles for stacked barrel-shaped solder joints

corners (Ho et al., 1995; Lau, 1996; Yu et al., 1998). Finite element modeling also showed that an hourglass-shaped joint will have significantly lower stress at the joint corners (Ho et al., 1995; Su et al., 1998; Yu et al., 1998). Analytically, the stress and strain field near the bond contact edges show singular behavior, which can induce considerably larger stress than the nominal stress. It has been shown that the singularity increases and becomes more significant with increasing contact angle (Body, 1952; Williams and Pasadena, 1971). The smaller contact angle of the hourglass joint reduces the order of the singularity and may help explain the longer crack initiation time. The reduced cross section in the middle of the hourglass-shaped joints may also induce a greater portion of the deformation to take place, away from the brittle interfaces with the die and substrate. The experimental results also point to the standoff height as the determining factor in the crack propagation time. This can probably be explained by the laws governing the fatigue crack propagation for stage II growth in a metal. Stage II growth is related to the total strain by a single power law expression extending from the elastic to the plastic regime (Dieter, 1976). The effective strain in the solder joint can be expressed as (Hwang, 1996): 1eff ¼

Figure 8 Electrical resistance vs number of cycles for stacked hourglass-shaped solder joints

bDaDTa h

ð1Þ

where b is the effective factor, Da is the difference in CTE, DT is the temperature change, a is the distance from the neutral expansion point and h is the joint height. Thus, a high joint standoff height will reduce the effective strain and in turn lower the crack propagation rate.

Effect of flexible substrates on reliability The effect of substrate flexibility on joint reliability was investigated by substituting a flex substrate for the rigid printed circuit board (PCB) in the fabrication of flip chip test samples. The solder material for the joint was eutectic leadtin. Two thermal cycling conditions were used for this part of the study: 1 0-1008C, and 2 240-1258C.

Figure 9 Average fatigue life of the different solder joint configurations broken down into crack initiation, crack propagation and catastrophic failure component stages

A comparison of the fatigue life of flip chip on flex (FCOF) and flip chip on PCB board (FCOB) is shown in Figure 13. The results show a significant improvement in the fatigue life if a flexible substrate is used. Thermo mechanical analysis (TMA) of the structure indicate that the flex substrate buckles during temperature cycling to accommodate the displacements brought about by the mismatches in CTEs between the various materials. Thus, by providing a mechanism for accommodating temperatureinduced distortions, the solder joint deformation is reduced resulting in improved reliability. The situation is similar to the effect of underfill encapsulant on the flip chip assembly. The underfill forces the substrate (including rigid ones) to bend and thus, reduce the thermal strain on the joints (Lau, 1994).

FE modeling of solder joints FE modeling of the solder joints was performed in order to show the effect of solder contact angle on the stress distribution in the joint structure. The modeling was conducted using ANSYS. The results shown in Figure 14 were obtained using a two-dimensional model representing the plane passing through the centre of the joints. The joint height was kept constant for all values of contact angle. The von Mises stress and the resultant shear stress show an increasing trend with increasing contact angle, i.e. as the shape of the solder joint contact with the die and substrate transitions from the hourglass structure to that of a barrelshaped joint. The maximum stress occurs at the solder-die interface as shown in the inset. A barrel-shaped joint with a 458 outer angle will experience a stress roughly 50 percent higher than an hourglass-shaped joint with a 458 internal angle.

[ 31 ]


Figure 10 Scanning acoustic microscopy images of the interface between single-bump barrel-shaped joints and die at (a) 1,400 cycles, (b) 1,700 cycles, (c) 2,200 cycles, and (d) 2,400 cycles

Figure 11 Average crack area increase during temperature cycling for single-bump barrel-shaped solder joints and stacked hourglass-shaped solder joints

DAI The conventional controlled collapse bonding (CCB) process produces barrel-shaped solder joints in which stress/ strain concentration is localized at the other edge of the silicon/solder or substrate/solder interface. Under large CTE

[ 32 ]

mismatches such as that between copper and silicon in power modules, the solder joints are prone to early fatigue cracking at the silicon/solder interface. The DAI technique provides the capability of achieving lower switching loss, higher efficiency and better heat dissipation in a threedimensional structure than the wirebonding technique. Additionally, it can provide improved thermal reliability and performance over the conventional CCB power device packaging method. The DAI technique establishes electrical connections on the power devices by solder bumps formed between the device electrodes and arrays of dimples preformed on a metal sheet. The result is a simple, low-profile planar interconnection suitable for multi layer integration with other circuit components. A detailed schematic the structure of a dimple connection is shown in Figure 15. The connecting solder layer takes the shape of an hourglass, which exhibits a better reliability than a barrel structure. With the exception of the fabrication of the dimpled copper, assembly of the DAI structure follows the typical solder joint interconnection processes. A detailed description of the assembly procedure can be found elsewhere ( Wen, 2002). Copper is the preferred material in power electronics because of its excellent electrical, physical and mechanical properties. However, as a first-level interconnect, the large CTE mismatch with silicon presents a reliability issue. A first-order estimate of the shear stress (t) and strain (g) in the solder undergoing a 1008C temperature excursion using typical property values are about 153 MPa and 0.013,


Figure 12 Typical cross sections of thermal fatigue-failed. (a) singlebump barrel shaped solder joints and (b) stacked hourglass shaped solder joints

respectively. For the Sn-Pb eutectic solder, which yields around 43 MPa, tmax is only 21.5 MPa. In CCB joints, the situation is aggravated by the stress concentration at the structural singularity in the solder joint with the silicon. A stress distribution analysis done as early as 1969 by IBM researchers (Goldmann, 1969) shows that when the solder joint is distorted due to CTE mismatch between the substrate and chip, shear stresses are imposed at both ends, together with normal stresses at the corners which must be present for momentum balance to occur. In DAI, the solder is prevented from collapsing by the copper dimple and eliminates the structural singularity at the solder/silicon interface found in CCB joints, thus alleviating the stress concentration and prolonging crack initiation time. Generally, improvements in area array solder joints can be achieved by increasing the flexibility of the interconnect sheet, increasing the solder joint height and underfilling the gap. These methods also apply to DAI. Thermal cycling test samples with either DAI or CCB interconnections were fabricated on a silicon wafer by creating a solderable UBM pattern. Such samples work perfectly well in simulating actual power devices, since the samples are not powered up. Dimpled copper sheets measuring 8 £ 10 mm with 2 £ 3 dimple-arrays were used to connect to the conductive traces forming the DAI structure. The joints formed were roughly 1 mm in diameter. CCB joints were created by using plain copper sheets, with the solder balls forming contacts defined by a solder mask. For power cycling tests, samples were fabricated using functioning power diodes (IXYS DWEP 35-06) measuring 6 £ 6 mm with solderable UBM on both sides. A square pattern with a centre joint (total of five joints) were created on the devices and capped with either dimpled or plain copper sheets. The details of the test structures, apparatus and test procedures can be found elsewhere (Wen, 2002).

Thermal cycling test results

Figure 13 A comparison of the average fatigue life of FCOF and FCOB assemblies during thermal cycling

The normalized resistance of the individual solder joints was used to compare the thermal cycling capability of the CCB and DAI solder joints. The normalized resistance is obtained by dividing the measured resistance, R, by the zero-cycle resistance, R0. Typical normalized resistance curves are shown in Figure 16 for CCB and dimple interconnections. Most of the CCB joints displayed a drastic resistance increase only after 35 cycles from 255 to 1258C whereas the dimple joints show a much slower rate. In addition, more than 20 percent of the CCB joints were found to have high zero-cycle resistance although no open joints were found. The results differ significantly from those of conventional (IC) BGA board-level and flip chip interconnections. Failure in those structures occurs after hundreds of cycles. The main cause is the large CTE mismatch between the silicon device and the copper interconnect (,13 ppm/K) as opposed to the smaller CTE mismatch in the BGA (ceramic substrate to PCB board is about 7 ppm/K) or the flip chip package (silicon to ceramic substrate is ,5 ppm/K). Figure 17 shows a cumulative failure plot, based on a failure criteria of a 20 percent change in resistance, for both types of interconnection. The dimple-array solder joints can be seen to have a significantly longer lifetime than the corresponding CCB joints. If this criterion is taken as the time-to-crack initiation, then the mean time for fatigue crack initiation for dimple-array solder joints is about 110 cycles for this particular test condition, while that for the CCB joints is around 8 cycles. About 30 percent of the CCB joints experienced an open circuit condition after 135 cycles, while roughly 40 percent of the dimple solder joints experienced an open circuit after 345 cycles.

FEM modeling of thermal fatigue In order to correlate FEM modeling with the reliability tests, two cases were studied by FEA modeling: power and temperature cycling conditions. The details of the modeling procedure and materials properties used are described elsewhere (Wen, 2002). Solder materials are complicated to

[ 33 ]


model because of their temperature and time-dependent viscoplastic behavior. The field temperature of solder joints is in the range 0.5-0.8 Tm (melting temperature) such that creep is significant and cannot be ignored. The temperature dependency of the plasticity of solder alloys further complicates the problem. In this study, a constitutive theory developed by Hong and Burrell (Hong, 1998) was used to model the solder material. According to this theory, the total strain in the solder joint is assumed to be the sum of the

Figure 14 Plot of predicted maximum stresses as a function of internal contact angle in a two-dimensional solder interconnection

elastic, plastic, creep and thermal strains. The Prandtl-Reuss equations are used to describe the elastic-plastic behavior of solder. During the course of the study, only the steady-state creep can be modeled using ABAQUS, for which the Garofalo hyperbolic sine law was used. For the modeling of the thermal cycling test, a uniform temperature loading of 255-1258C was used, with the stress-free state selected being the reflow temperature based on the assumption that cooling from the liquidus to room temperature took place within 60 s. For the modeling of the power cycling test, a uniform temperature load of 10-1008C was used, based on the measured temperature at the copper interconnect.

Thermal cycling modeling results

Figure 15 Schematic of the structure of a single dimple interconnect in the DAI

Figure 16 Normalized resistance (R/R0) vs number of thermal cycles

[ 34 ]

A comparison of the von Mises stress distribution for the CCB and dimple samples at 2558C is shown in Figure 18. The copper flex is not shown for clarity and only a quarter of each of the models are shown. Because the temperature cycling samples were not underfilled, the CTE mismatch between the copper and the silicon was mostly loaded on the solder joints, even though the deformation of the copper flex helps reduce the stresses on the joints. The von Mises stress is the major driving force for the inelastic deformation and is responsible for the change in shape and distortion of the material. It is found that the stresses are highest when the temperature is at the cold extreme (2558C), which suggests that more damage occurs at the cold stage of the temperature cycling test. The von Mises stress components at the weakest locations (where failures occur) are plotted in Figure 19. The normal stresses (s11, s22, s33) are fairly high for both interconnects. However, when the normal stresses are close to each other in value, the shear stresses contribute the majority of the yielding of the joints. A comparison of the strain components further proves this point. In Figure 20, the shear strains are found to be substantially higher in the weakest points of the CCB joints than in the dimple joints. The shear stress-strain hysteresis loops are shown in Figure 21 for both CCB and dimple joints. Shear stresses are negative for the cold extreme and positive for the hot extreme of the cycle. The shear strains are ratcheting towards the negative direction of the strain axis with time. Because of the inelastic strain damage (creep and plasticity), the stress/strain cannot fully recover to the starting state of the last cycle. The ratcheting curves of the dimple solder joint are much more stable than those of the CCB solder joints. The smaller shear strain range of the DAI also suggests that temperature cycling causes less damage per cycle to the DAI than to the CCB.


Figure 17 Cumulative failure based on a 20 percent increase in resistance for dimple and CCB Sn-37Pb solder joints

Figure 18 Von Mises stress distribution in: (a) CCB model, and (b) DAI model (The chip center is on the upper left corner of the rectangle)

[ 35 ]


Figure 19 Stress components at the weakest locations in solder joints

Figure 20 Strain components at the weakest locations in the solder joints

Figure 21 Shear stress-strain hysteresis loops for the CCB and dimple solder joints

Power cycling modeling results Figure 22 shows a contour plot of the cumulative equivalent plastic strain. After four cycles, the dimple joint (underfilled sample) has the highest accumulative equivalent plastic strain ð5:07 £ 1023 Þ at the centre of the joint (A), close to the copper/solder interface. This is different from the non-underfilled case where the highest equivalent plastic strain (PEEQ) occurs at the silicon/solder interface (B). The CCB joint is the weakest at the outer corner of the solder joint (silicon/solder interface) with a

[ 36 ]

total equivalent plastic strain of 5:24 £ 1023 : The equivalent plastic strain range (accumulation per cycle) differs dramatically between the two types of joints. The dimple joint experiences higher initial equivalent plastic strain and then stabilizes to a smaller increment per cycle than the CCB. The same behavior applies to the equivalent creep strains. A summary of the equivalent creep and plastic strains is given in Table I. The PEEQ in the weakest location of the CCB joint is much larger than that in the dimple solder joint.


Figure 22 Total cumulative equivalent plastic strain for first four cycles: (a) DAI, and (b) CCB solder joint

Correlation between FE modeling and experiment Thermal cycling correlation

contribute to the discrepancies. These differences are discussed in more detail elsewhere (Wen, 2002).

A modified Coffin-Manson equation based on conventional creep and plastic theory and a constitutive theory of isotropic thermo-viscoplasticity (Hong and Burrell, 1995) was used to estimate the fatigue life of the interconnects and is obtained as: C N 50 ¼ B1 D1in eq

ð2Þ

where N50 is the mean fatigue life, D1in eq is the accumulated equivalent inelastic strain per cycle, B1 and C are materials constants which are 0.146 and 21.94, respectively, for eutectic solder (Mukai et al., 1997). It must be pointed out that the material constants are highly sensitive to the package type, solder pad size and solder volume, and the dominant fatigue mechanism (creep vs plasticity), such that it is not realistic to expect a perfect match between the experimental data and the life prediction based on these constants. The comparison between the experimental results and FEM predictions is summarized in Table II. The dimple array improved the fatigue life by a factor of 14 (for a 20 percent resistance increase) and 8 (for a 50 percent resistance increase) over that of the CCB. The FE modeling predicts an improvement of 4.6 £ for location A and 9.7 £ for location B. Discrepancies between the experimental and predicted numbers are inevitable for a host of reasons. To begin with, the quality of the actual test structures may deviate from the idealized structure used in the model. Assumptions and simplifications in the FEM modeling also

Power cycling correlation Owing to the fact that the power cycling test could not provide a credible estimate of time-to-crack-initiation, it is impossible to correlate FE modeling fatigue life prediction with experiments. For the completeness of this work, the FEM-predicted crack initiation times are shown in Table III. Clearly, the dimple solder joints perform better than the CCB joint under power cycling conditions. While correlation is very difficult to establish, it is nevertheless possible to obtain a correlation of the failure mechanisms as predicted by FE modeling with those observed in the experimental samples. Observed and predicted failure modes and locations for DAI and CCB joints are shown in Figures 23 and 24. The dimple array joint in Figure 23 was cycled 12,700 times from 10 to 1008C. Cracking took place away from the solder/device interface. The FEM-predicted maximum inelastic strain distribution roughly coincides with the cracking on the experimental sample. In the case of the CCB joint in Figure 24, cracking initiated and grew at the solder/device interface. The FE modeling predicted the highest inelastic strain to be in this location and therefore, is the likely site for crack initiation and growth. Fatigue cycles to failure obtained from power cycling tests are usually much larger than those obtained by thermal cycling. The discrepancy arises from the different cycling frequency between the two tests. A thermal cycle takes minutes, and in some case over an hour, to complete, while power cycling can be performed at a much higher frequency. In the case of the test performed here, one cycle

Table I Comparison of the equivalent creep, plastic and total inelastic strain per cycle Saturated strain range Equivalent creep (CEEQ) Equivalent plastic (PEEQ) Total inelastic strain range

Dimple, location A

Dimple, location B

CCB

0.0041 0.00062 0.00472

0.00398 0.0009 0.00488

0.00528 0.0035 0.00878

Table II FEM predictions and experimental results for thermal cycling Saturated strain range Equivalent creep (CEEQ) Equivalent plastic (PEEQ) Equivalent inelastic D1in eq Predicted N50 (cycles) Experimental (20 percent increase of dc resistance) Experimental (50 percent increase of dc resistance)

Dimple, location A

Dimple, location B

0.0617 0.0036 0.0653 29 110

0.0424 0.0020 0.0444 61 110

185

185

CCB 0.1230 0.0207 0.1437 6.3 8 23

[ 37 ]


Table III Predicted crack initiation time using FEM Inelastic strain range D1in eq

Without DBC Modified D1in eq Predicted N50 (cycles)

Dimple, A

Dimple, B

CCB

0.00472 0.00393 6,780

0.00488 0.00407 6,335

0.00878 0.00732 2,029

Figure 23 (a) Optical micrograph of a DAI joint after 12,700 cycles; and (b) the FEM predicted inelastic strain distribution

took at most 1 min. The long duration per thermal cycle allows for the accumulation of significant damage in one cycle, while rapid switching during power cycling produces much less incremental damage per cycle. Nevertheless, both tests should exhibit the same trend as to the relative reliability of each interconnect structure.

Conclusions Based on the experimental and FE modeling work on the stacked solder joint interconnect and DAI, the following conclusions can be made compared with the conventional solder bump interconnection. Temperature cycling tests showed that the hourglass-shaped triple-stacked solder joint has better reliability than a barrel-shaped stacked solder joint, which in turn had improved reliability over that of single bump barrel-shaped solder joint. The increased reliability of the hourglass-shaped stacked solder joint can be traced to increased crack initiation and propagation times over that for the single bump barrel-shaped joint.

[ 38 ]

Using flexible substrates also contributes to the increased reliability of the joint. It provides a mechanism for accommodating the stress generated by the CTE mismatch between the device and substrate by buckling during temperature excursions. The DAI exhibited improved reliability over that of CCB solder joints. Part of the improvement is due to the relocation of highest stress away from the inherently weak solder/device interface. In the FE modeling, the smaller shear strain range of the DAI during temperature cycling suggests a smaller damage per cycle over that of CCB joints, which in turn results in prolonged lifetime. In the modeling of power cycling, the dimple joint experiences higher initial equivalent plastic and creep strains, but stabilizes to smaller increments per cycle than the CCB, thus leading to improved fatigue life. While a perfect correlation between temperature cycling and experiment and FE modeling is not realistic to attain, there is a qualitative agreement between the two in the comparative reliability of DAI and CCB joints. A comparison of the observed failure mechanisms of both joints and FE modeling predictions of the highest inelastic


Figure 24 (a) SEM image of a CCB joint after 8,500 cycles; and (b) the FEM predicted inelastic strain distribution

strains under both temperature and power cycling conditions also showed very good agreement. In the DAI joints, cracking occurred away from the solder/device interface. In the CCB joint, cracking was observed to have taken place at the solder/device interface.

References Bindra, A. (2000), “Innovative packages maximize MOSFETs’ thermal performance”, Electronic Design, Vol. 47 No. 10, p. 52. Body, D.B. (1952), “Two edge-bonded elastic wedges of different materials and wedges angles under surface tractions”, Journal of Applied Mechanics, pp. 526-8. Dieter, G.E. (1976), Mechanical Metallurgy, McGraw-Hill, New York, NY. Goldmann, L.S. (1969), “Geometric optimization of controlled collapse interconnections”, IBM Journal of Research and Development, Vol. 13 No. 3, pp. 251-65. Harada, M. and Satoh, R. (1990), “Mechanical characteristics of 96.5Sn/3.5Ag solder in microbonding”, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 13, pp. 736-42. Ho, T.H., Lee, J.Y., Lee, R.S. and Lin, A.W. (1995), “Linear finite stress simulation of solder joints on 225 I/O plastic BGA packages under thermal cycling”, Proceedings of the 45th IEEE Electronic Components Technology Conference, Las Vegas, NV, pp. 930-6. Hong, B.Z. (1998), “Thermal fatigue analysis of a CBGA package with lead-free solder fillets”, Proceedings of the 6th Inter Society Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, (ITHERM’98), Seattle, WA, pp. 205-11. Hong, B.Z. and Burrell, L.G. (1995), “Nonlinear finite element simulation of thermoviscoplastic deformation of C4 solder

joints in high density packaging under thermal cycling”, IEEE Transactions on Components, Packaging and Manufacturing Technology, Part A, Vol. 18 No. 3, pp. 585-91. Hwang, J.S. (1996), Modern Solder Technology for Competitive Electronics Manufacturing, McGraw-Hill, New York, NY. Klein, J. (2000), “Bottomless SO-8 package boosts MOSFET performance”, PCIM, Vol. 26 No. 5, p. 110. Lall, P., Pecht, M.G. and Hakim, E.B. (1997), Influence of Temperature on Microelectronics and System Reliability, CRC Press, Boca Raton, FL. Lau, J.H. (1994), Chip on Board Technologies for Multichip Modules, Van Nostrand Reinhold, New York, NY. Lau, J.H. (1996), Flip Chip Technologies, McGraw Hill, New York, NY. Liu, X. (2001), “Processing and reliability assessment of solder joint interconnection for power chips”, PhD thesis, Virginia Polytechnic Institute and State University, Blacksburg, Virginia. Liu, X., Haque, S. and Lu, G-Q. (2001a), “Three-dimensional flip chip on flex packaging for power electronics application”, IEEE Transactions on Advanced Packaging, Vol. 24 No. 1, pp. 1-9. Liu, X., Xu, S., Lu, G.Q. and Dillard, D.A. (2001b), “Stacked solder bumping technology for improved solder joint reliability”, Journal of Microelectronics Reliability, Vol. 41 No. 12, pp. 1979-92. Mannion, P. (1999), “MOSFETs break out of the shackles of wirebonding”, Electronic Design, Vol. 47 No. 6, p. 36. Morrison, D.G. (2002), “Dual thermal paths dual power handling for surface-mounted MOSFETs”, Electronic Design, Vol. 50 No. 2, pp. 33-6. Mukai, M., Kawakami, T., Takahashi, K. and Iwase, N. (1997), “Thermal fatigue life prediction of solder joints using stress analysis”, Proceedings of the 1st IEEE IEMT/IMC Symposium, Sonic City, Omiya, Japan, pp. 204-8.

[ 39 ]


We are grateful to Dan Huff for the extensive technical assistance he provided to the research effort.

[ 40 ]

Shimokawa, K., Tatsumi, K., Hashino, E., Ohzeki, Y., Konda, M. and Kawakami, Y. (1997), “Micro-ball bump technology for fine-pitch interconnections”, Proceedings of the 1st IEEE IEMT/IMC Symposium, Sonic City, Omiya, Japan, pp. 105-9. Shimokawa, K., Hashino, E., Ohzeki, Y. and Tatsumi, K. (1998), “Micro-ball bump for flip chip interconnections”, Proceedings of the 48th IEEE Electronic Components Technology Conference, Seattle, WA, pp. 1472-6. Su, B., Hareb, S. and Lee, Y.C. (1998), “Solder joint reliability modeling for a 540-I/O plastic ball-grid-array assembly”, Proceedings of the 7th International Conference on Multichip Modules and High Density Packaging, Denver, CO, pp. 422-8. Wen, S. (2002), “Design and analyses of a dimple array interconnect technique for power electronics packaging”, PhD thesis, Virginia Polytechnic Institute and State University, Blacksburg, Virginia. Wen, S. and Lu, G-Q. (2000), “Finite-element modeling of thermal and thermomechanical behavior for three-dimensional packaging of power electronics modules”, Proceedings of the

7th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, I-Therm, Las Vegas, Nevada, pp. 303-9. Wen, S., Huff, D. and Lu, G-Q. (2001), “Dimple-array interconnect technique for packaging power semiconductor devices and modules”, Proceedings of the 2001 International Symposium on Power Devices and ICs, Osaka, Japan, pp. 69-74. Williams, M.L. and Pasadena, C. (1971), “Stress sigularities resulting from various boundary conditions in angular corners of plates in extension”, Journal of Applied Mechanics, pp. 377-86. Xing, K., (1999), “Modeling, analysis, and design of distributed power electronics system based on building block concept”, PhD dissertation, Virginia Polytechnic Institute and State University, Blacksburg, VA. Yu, Q., Shiratori, M. and Ohshima, Y. (1998), “A study of the effects of BGA solder geometry on fatigue life and reliability assessment”, Proceedings of the 6th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, Seattle, WA, pp. 229-35.

CBGA solder joint thermal fatigue life estimation by a simple method T.E. Wong Raytheon Electronic Systems, El Segundo, California, USA C.Y. Lau Raytheon Electronic Systems, El Segundo, California, USA H.S. Fenger Raytheon Electronic Systems, El Segundo, California, USA

Keywords Soldering, Joining processes, Fatigue, Thermal properties of materials

Abstract A simple analysis method was developed to determine the fatigue life of a ceramic ball grid array (CBGA) solder joint when exposed to thermal environments. The solder joint consists of a 90Pb/10Sn solder ball with eutectic SnPb solder on both top and bottom of the ball. A closedform solution, based on the calculation of the equilibrium of the displacements within the electronic package assembly, was first derived in order to calculate the solder joint strains during temperature cycling. In the calculation, an iteration technique was used to obtain a convergent solution for the solder strains, and the elastic material properties were used for all the electronic package assembly components except for the solder materials. A fatigue life prediction model was established.

Received: 12 September 2003 Revised: 1 February 2004


Introduction Usage of the ball grid array (BGA) has become popular in today’s electronic hardware industry. Owing to the hermetic design requirement in some electronic systems for military applications, the use of the ceramic BGA (CBGA) is imminent. It is well known that the CBGA solder joint thermal fatigue reliability is significantly reduced when the CBGA package is soldered onto an epoxy-based printed wiring board (PWB), e.g. FR-4, and then subjected to temperature cycling. This is due to the absence of compliant leads in the CBGA that would help accommodate the large coefficient of thermal expansion (CTE) mismatch between the package and the PWB. This CTE mismatch is the firstorder driving force for the thermal-fatigue-induced failure of the CBGA solder joints. This failure condition was experimentally demonstrated by many researchers (Cho and Mawer, 1996; Fenger and Wong, 2003; Lau and Pao, 1997). Therefore, the solder joint reliability of the CBGA has become one of the major concerns in the electronics industry. Figure 1, the micro-section of a CBGA solder joint assembly, shows a solder joint consisting of a 0.89 mm diameter 90Pb/10Sn solder ball (dark center) with eutectic SnPb solder (light surrounding) on both top and bottom of the ball. Currently, empirical models evolved from a CoffinManson fatigue life prediction theory in conjunction with complex nonlinear finite element analysis (FEA), are extensively used to estimate the solder joint fatigue life. In these models, the total strain range (Agarwala, 1985; Pao et al., 1997; Uegai et al., 1993; Wong et al., 1997a, b, 1998, 2003) or viscoplastic strain energy density increment (Darveaux, 1993; Engelmaier, 1984; Jung et al., 1997; Lau and Pao, 1997; Sarihan, 1994; Wong and Matsunaga, 2000; Wong et al., 1999a, b) are the most widely used criteria. A high performance computer and finite element modeling/ analysis effort are then desirable or required to estimate the fatigue life. However, this approach is time consuming and expensive. To overcome these inadequacies, a simple analysis method to preliminarily determine the thermal fatigue damage of CBGA solder joints is needed, and its development is the objective of the present study. Steinberg (1991, 2001) showed a simplified method to predict solder joint fatigue life. However, only elastic deformation was used in life prediction. Wong et al. (2003) showed a simplified analysis to predict the solder joint fatigue life of a leadless ceramic chip carrier or a leadless chip capacitor/resistor by incorporating the elastic-plastic deformation of solder during temperature cycling into a closed form solution. However, only one solder material was considered. In the present work, the fatigue damage of the CBGA solder joint, consisting of 90Pb/10Sn and eutectic The Emerald Research Register for this journal is available at www.emeraldinsight.com/researchregister

solders, is evaluated. A simple analysis method using a closed form solution is first developed to calculate the solder joint strains during temperature cycling. In the calculation process, only the solder joints experience elastic-plastic deformation, while the rest of the components within the assembly experience only elastic deformation. Since CBGA solder joint failure has been observed to occur only in the eutectic solder, the calculated strain for this solder material is used in a proposed thermal fatigue life prediction model. Finally, this model is calibrated to test results reported by Cho and Mawer (1996). Note that, for the purpose of the problem simplification, no solder creep is considered in the present study. When the solder creep is included, a detailed FEA is recommended to be used to evaluate CBGA solder joint thermal fatigue damage (Wong et al., 1999b), which will not be addressed in the present study. In addition, no PWB bending during the temperature cycling was considered in this study since the PWB is bonded onto a metal heat sink in most products. Therefore, no/minimum PWB bending is expected. In the model calibration process, 255- and 304-pin CBGAs manufactured by Motorola (Cho and Mawer, 1996), and two different temperature cycling profiles were used. Figure 2 shows a cross-sectional representation of the 255-pin CBGA construction. The geometries of these two CBGAs are summarized in Table I. The CBGAs were soldered onto either a FR-4 or a Thermount (Zussman and Powell, 1996) PWB. All part geometries and material properties used in the following analysis are listed in Table II. The CTE and elastic modulus of each material can be found in ASM (1979) and Touloukian (1977). The two types of accelerated thermal cycling environments (Cho and Mawer, 1996) are summarized in Table III. The CBGA solder joint strain is calculated for each temperature cycling range. During the temperature cycling, no power is provided to the electronic components. The thermal cycling test results (Cho and Mawer, 1996) are summarized in Table IV. In the test, solder joint failure is defined as an electrical discontinuity.

Solder joint analysis A simple analysis method is developed to calculate the solder joint strains during temperature cycling based on the equilibrium of displacements within the electronic package assembly and then updating the solder strains through an iteration process, according to the stress-strain behaviors of the two solders, until a convergent solution is obtained. Figure 3 shows the CTE mismatch between the component and the PWB. The equilibrium equation shown in Steinberg (1991) is presented in equation (1) to describe The current issue and full text archive of this journal is available at www.emeraldinsight.com/0954-0911.htm

[ 41 ]

T.E. Wong, C.Y. Lau and H.S. Fenger CBGA solder joint thermal fatigue life estimation by a simple method Soldering & Surface Mount Technology 16/2 [2004] 41–45

the relationship between the component, PWB, and the solder joint. In other words, the displacement of the component plus the displacement of the solder joint is equal to the displacement of the PWB:

Figure 1 Micro-section of a CBGA solder joint assembly

ac Lc DT þ

where P ¼ force (N); subscripts c, s, h, and p indicate forces on component, eutectic solder, 90Pb/10Sn solder, and PWB, respectively; ap ¼ effective CTE of the PWB (mm/mm-8C); Lp ¼ Lc¼ 1/2 PWB effective length¼ 1/2 component effective length¼ 1/2 distance between centroids of two opposite terminals (mm); ac ¼ effective CTE of component (mm/mm- 8C); DT ¼ temperature excursion from midpoint of cycle (8C); G0 ¼ eutectic solder shear modulus (GPa) ¼ (1611 2 4.325 £ mean cyclic temp.) £ 103; Gh0 ¼ 90Pb/10Sn solder shear modulus (GPa) (Cole et al., 1991); As ¼ Ah ¼ area of all active solder balls on one side of the BGA (mm2); Ap ¼ effective cross-sectional area of PWB ¼ effective PWB thickness £ width of component (mm2); Ep ¼ effective elastic modulus of PWB (GPa); Ac ¼ component’s cross-sectional area (mm2); Ec ¼ elastic modulus of component body (GPa); hs ¼ eutectic solder thickness (mm); hh ¼ 90Pb/10Sn solder thickness (mm).

Figure 2 Cross-sectional representation of the 255-pin CBGA

Table I CBGA geometry Package

Body size (mm)

Array

BGA count

BGA diameter (mm)

Pitch (mm)

21 £ 25 21 £ 21

19 £ 16 16 £ 16

304 255

0.89 0.89

1.27 1.27

MPC106 PowerPC603

P p Lp Pc Lc Ps hs Ph hh þ þ ¼ ap Lp DT 2 ð1Þ Ac Ec As G0 Ah Gh0 Ap Ep

Source: Cho and Mawer (1996)

Equation (1) shows that the solder joint experiences a shear deformation to compensate for the CTE mismatch between the component and the PWB. For a CBGA, the maximum shear deformation of the solder joint occurs across the diagonal dimension of the package, which is defined as the component’s maximum effective length. Based on the measurements of the micro-section in Figure 1, the solder joint height ranges from 0.89 to 0.94 mm. For conservative purposes, a total solder joint height of 0.89 mm was chosen for the current study. The values of hs and hh are then calculated to be 0.26 and 0.63 mm, respectively, based on the proportional volumes of the eutectic and 90Pb/10Sn solders within the BGA solder balls. Since,

Table II Part geometries and material properties

Pc ¼ Ps ¼ Ph ¼ Pp ¼ P

Part

Input parameter

Ceramic module

Width, wc (mm) Thickness, tc (mm) Young’s modulus, Ec (GPa) CTE, ac (mm/mm-8C) No. of solder columns, c No. of solder rows, r Solder pitch, p (mm) Average height, havg (mm) Diameter @ substrate, ds1 (mm) Diameter @ PWB, dp1 (mm) Thickness, tp (mm) Young’s modulus, Ep (GPa) CTE, ap (mm/mm-8C) Thickness, tp (mm) Young’s modulus, Ep (GPa) CTE, ap (mm/mm-8C)

Solder

PWB (FR4)

PWB (Thermount)

MPC 106

PowerPC 603

21 1 303 5.00 £ 102 6 19 16 1.27 0.91 0.89 0.81 1.57 17.2 1.65 £ 102 5 – – –

21 1 303 5.00 £ 102 6 16 16 1.27 0.91 0.89 0.81 1.57 17.2 1.65 £ 102 5 1.57 13.8 1.00 £ 102 5

Table III Temperature cycling profiles Temperature profile

Temperature range (8C)

Dwell (min)

Ramp rate (8C/min)

Period (min/cycle)

0-100 2 40-125

5 15

10 11

30 60

1 2 Source: Cho and Mawer (1996)

[ 42 ]

ð2Þ

the value of P can be calculated from equation (1), into which the part geometries and material properties listed in Table II were substituted. The average solder joint shear stresses (in MPa) within the eutectic and 90Pb/10Sn solders at the centroid of one side of the BGA are

tsc ¼

KP ; As

thc ¼

KP Ah

ð3Þ

where K is the stress concentration factor, which is chosen as 1 in the present study. A correction factor was then used to calculate the maximum solder shear stresses, which are at the most distant solder joints and represented by ts and th corresponding to eutectic and 90Pb/10Sn solders, respectively. A detailed description of this calculation can be found in Steinberg (2001). The shear strains for the eutectic and 90Pb/10Sn solders can be obtained as:

gs ¼

Kða L 2 ac Lc ÞDT ts p p ¼ ; G0 As G0 Lp þ Lc þ hh þ hs Ap Ep Ac Ec Ah Gh0 ð4Þ

gh ¼

Kðap Lp 2 ac Lc ÞDT th ¼ Gh0 Ah Gh0 Lp þ Lc þ hs þ hh Ap Ep Ac Ec As G0


Table IV Test results of CBGA solder joint thermal fatigue life Case

Package

1 2 3 4 5 6

MPC106 MPC106 PowerPC603 PowerPC603 PowerPC603a PowerPC603a

Temperature profile

PWB

1 2 1 2 1 1

FR-4 FR-4 FR-4 FR-4 FR-4 Thermount

Fatigue life (cycles) 0.01 percent failure 50 percent failureb 1,566 700 1,850 590 2,200 4,800

2,440 1,132 2,733 1,056 3,414 6,600

Source: Cho and Mawer (1996) Notes: aImproved package and surface mount process, and bEquivalent to MCTF

Figure 3 CTE mismatch between component and PWB

Figure 4 Equivalent shear modulus of eutectic solder

where gs and gh are the shear strains in the eutectic and 90Pb/10Sn solders, respectively (mm/mm). Kitano et al. (1992) showed the stress-strain behavior of eutectic solder, measured using a cyclic torsion test on hollow specimens, as

gs ¼

1 ts 1 2ts n þ m G0 2 F s f

ð5Þ

where Fs is the plastic coefficient, ðMPaÞ ¼ ð15:38 2 0:064 £ mean cyclic temp:Þ £ 103 ; f is the frequency of temperature cycle (Hz) ¼ 1/3,600 (assumed value); m is the frequency sensitivity exponent ¼ 0.0468 þ 5.85 £ 102 4 £ mean cyclic temperature and n is the strain hardening exponent ¼ 0.168 þ 5.51 £ 102 8 £ mean cyclic temperature. The equivalent shear modulus of the eutectic solder as used in equations (1) and (4) can be obtained as follows. Let

gs; j ¼

ts; j 1 2ts; j þ G0 2 F s f m

Gjþ1 ¼

ts; j ; gs; j

1n ð6Þ

ð7Þ

where Gj+1 is the eutectic solder shear modulus to be iterated to convergence (MPa); gs,j is the eutectic solder strain iterated using the equilibrium of displacements of electronic package assembly (mm/mm); and ts,j is the eutectic solder stress iterated according to stress-strain behavior (MPa) (mm/mm) and j is the iteration number. The tensile stress-strain behavior of 90Pb/10Sn solder at 0, 50 and 1008C can be found in Cole et al. (1991). This available material property information was applied to a FEA of a simple solid cylinder under pure torsion in order to derive the shear stress-strain relationship of the 90Pb/10Sn solder for use in the following iteration process. First, the shear strains of both the eutectic and 90Pb/10Sn solders (gs,0 and gh,0) are obtained using equation (4) by assuming the equivalent shear moduli of the solders to be the real shear moduli (G0 and Gh0). Next, the shear stresses ts,0 and th,0 are calculated according to the stress-strain behaviors of the eutectic solder using equation (6) and of the 90Pb/10Sn solder using FEA results. Figure 4 shows the iteration process used to determine the eutectic solder shear strain value. In this figure, the equivalent shear modulus of the eutectic solder, G1, is obtained using equation (7)

G1 ¼

ts;0 : gs;0

ð8Þ

In the next step, the shear strain, gs,1, and shear stress, ts,1, are calculated using G1, and the equivalent shear modulus G2 in the succeeding step is then derived. This process is iterated j times. During this iteration process, if both Gj and Ghj are determined to have converged then gs,j2 1 and ts,j2 1 are determined to be the current shear strain and shear stress within the eutectic solder. In the present study, the criteria for this convergence is that the values of Gj and Ghj change by no more than 5 percent between iterations. The flow chart of the above iteration process is shown in Figure 5. In the above calculation only the solder joint, consisting of the two solder materials, experiences elastic-plastic deformation, while the rest of the assembly components are elastically deformed. This method is demonstrated in calculating the eutectic solder strain amplitudes of two CBGAs, whose geometries and material properties are listed in Tables I and II, when soldered onto two different types of PWBs and subjected to the two different temperature cycling profiles listed in Table III. The calculated results are summarized in Table V.

Thermal fatigue model Failure of highly ductile solder material arises from repeated deformation. An empirically derived formula based on the modified Manson-Coffin fatigue theory in Solomon (1988) and Solomon et al. (1990) was used in the current study to

[ 43 ]


Figure 5 Flow chart of iteration process

estimate when solder joint failure would occur. Since the CBGA solder joint failure is only observed in the eutectic solder, the proposed fatigue life model will only relate the eutectic solder total shear strain range, Dg, developed during one temperature cycle to the number of cycles needed to induce solder failure, Nf, as described by the following equation: N f ¼ ðAi =AD ÞðDg Þc ;

ð9Þ

where Ai is the solder crack surface area and is equal to 0.62 mm2, AD is the characteristic area in mm2, and parameter c is the exponent value. Two unknown parameters, i.e. c and AD, are determined by correlating the derived solder total shear strain range to the test results of the thermal fatigue lives of two CBGAs, corresponding to all

Table V CBGA solder joint test and analysis results Curve-fitting data Case 1 2 3 4 5 6

MCTF (cycles) 2,440 1,132 2,733 1,056 3,414 6,600

Calculated strain range (percent) 1.708 £ 10 2.836 £ 102 3 1.945 £ 102 3 3.074 £ 102 3 1.945 £ 102 3 7.212 £ 102 4

Note: *Using the derived c and AD

[ 44 ]

23

Back-calculated MCTF* (cycles)

Percent error

2631.49 1399.26 2238.55 1265.63 2238.55 7701.85

27.85 2 23.61 18.09 2 19.85 34.43 2 16.69

six cases in Table IV. In the correlation process, the mean-cycle-to-failure (MCTF), listed in the last column of Table IV or in the second column of Table V, and the total shear strain ranges, calculated from the previous section and summarized in the third column of Table V, are used. Figure 6 is a plot of the solder joint thermal fatigue life versus the calculated solder shear strain range, for which a reasonably good correlation exists. The slope of the correlation line in this figure is equal to the parameter c, which is 21.25, and the characteristic area, AD, is calculated as 0.66 mm2. Applying these two derived values to equation (9), the fatigue lives for all six cases in Table V are calculated with the simple analysis method developed as summarized in the fourth column of Table V. The difference of the fatigue life values obtained from the test data and this simple analysis method is also summarized in the last column of Table V. The maximum difference is less than 35 percent. On the basis of the thermal fatigue prediction model of equation (9) and the developed simple analysis method whose flow chart is shown in Figure 5, an Excel spreadsheet was programmed in Visual Basic to calculate the CBGA solder joint fatigue life and becomes an effective tool to preliminarily estimate the CBGA solder joint thermal fatigue life.

Summary and recommendations A simple analysis method was developed to estimate the CBGA solder shear strains when exposed to thermal environments. The solder joint consists of a 90Pb/10Sn solder


Figure 6 Solder joint thermal fatigue life vs solder shear strain range for eutectic solder

ball with eutectic solder on both top and bottom of the ball. In the analysis, an iteration process that considered the elastic-plastic deformation of the two solders was used to calculate the solder shear strains. Since failure of the solder joints only occurred in the eutectic solder, the thermal fatigue life prediction model of this solder material was established. CBGA test results obtained from Cho and Mawer (1996), combined with the derived solder shear strains, were then used to calibrate the proposed life prediction model. In the model calibration process, the 255- and 304-pin CBGA test results were reasonably well correlated to the calculated solder strain values. In addition, this calibrated model is remarkably simple compared to the model used in an evaluation by FEA. Therefore, this model could be used as an effective tool to preliminarily estimate CBGA solder joint thermal fatigue life. The following future work is also recommended: 1 select more case studies with various solder joint configurations, package sizes, environmental profiles, etc. to further calibrate this life prediction model; 2 use this model to conduct parametric studies to identify critical factors impacting solder joint fatigue life and then seek an optimum design; and 3 develop a similar method to preliminarily estimate the thermal fatigue life of plastic/taped/super BGA solder joints.

References

The authors would like to thank L.A. Kachatorian from Raytheon Electronic Systems for his contribution to this work and Y.C. Cho, A. Mawer and T. Kaschmiedar from Mototrola for their valuable technical discussions.

Agarwala, B.N. (1985), “Thermal fatigue damage in Pb-In solder interconnections”, Proceedings of the 23rd IEEE International Reliability Physics Symposium, Orlando, FL, March 25-29, pp. 198-205. ASM International (1979), Electronic Materials Handbook, Volume 1, Packaging, Materials Park, OH. Cho, Y.C. and Mawer, A. (1996), “Interconnect reliability of a C4/ CBGA at both the chip and board level”, Proceedings of the NEPCON ’96 Conference, San Antonio, TX, pp. 109-18. Cole, M.S., Caulfield, B., Wanton, W. and Gonya (1991), “Constant strain rate tensile properties of various lead based solder alloys at 0, 50, and 1008C”, Proceedings of Materials Developments in Microelectronic Packaging Conference, Montreal, Quebec, Canada, pp. 241-9. Darveaux, R. (1993), “Crack initiation and growth in surface mount solder joints”, Proceedings of the 26th ISHM International Symposium on Microelectronics, Baltimore, MD, pp. 86-97. Engelmaier, W. (1984), “Functional cycles and surface mounting attachment reliability”, ISHM Technical Monograph Series 6984-002, International Society for Hybrid Microelectronics, Silver Springs, MD, pp. 87-114. Fenger, H.S. and Wong, T.E. (2003), “COTS BGA thermal fatigue test for avionics applications”, Proceedings of the ASME InterPack’03 Conference, Maui, HI, InterPACK2003-35017 (on CD-ROM).

Jung, W., Lau, J.H. and Pao, Y.H. (1997), “Nonlinear analysis of full-matrix and perimeter plastic ball grid array solder joints”, Journal of Electronic Packaging, Trans. of the ASME, Vol. 119, pp. 163-70. Lau, J.H. and Pao, Y.H. (1997), Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, McGrawHill, New York, NY. Pao, Y-H., Jih, E., Siddapureddy, V., Song, X., Liu, R., McMillan, R. and Hu, J.M. (1997), “Thermal fatigue of surface mount leadless solder joints”, Advancing Microelectronics, pp. 33-9. Sarihan, V. (1994), “Energy-based methodology for damage and life prediction of solder joints under thermal cycling”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, Vol. 17 No. 4, pp. 626-31. Solomon, H.D. (1998), Low Cycle Fatigue, ASTM STP-942, ASTM, pp. 342-71. Solomon, H.D., Brzozowski, V. and Thompson, D.G. (1990), “Predictions of solder joint fatigue life”, Proceedings of the 40th IEEE Electronic Components Technology Conference, San Diego, CA, pp. 351-9. Steinberg, D.S. (1991), Cooling Techniques for Electronic Equipment, 2nd ed., Wiley, New York, NY. Steinberg, D.S. (2001), Preventing Thermal Cycling and Vibration Failure in Electronic Equipment, Wiley, New York, NY. Touloukian, Y.S. (1977), Thermal Expansion, Nonmetallic Solids, Thermophysical Properties of Matter, Vol. 13, IFI/Plenum, New York, NY. Uegai, Y., Tani, S., Inoue, A., Yoshioka, S. and Tamura, K. (1993), “A method of fatigue life prediction for surface-mount solder joints of electronic devices by mechanical fatigue test”, Proceedings of the 2nd ASME International Electronic Packaging Conference, Vol. 1, Binghamton, NY, pp. 493-8. Wong, T.E. and Matsunaga, A.H. (2000), “Ceramic ball grid array solder joint thermal fatigue life enhancement”, Proceedings of NEPCON West Conference Anaheim, CA, pp. 1066-77. Wong, T.E., Cohen, H.M. and Chu, D.W. (1999a), “PBGA solder joint thermal fatigue life evaluation”, Proceedings of the 1999 ASME Winter Annual Meeting, Nashville, TN, pp. 678-81. Wong, T.E., Kachatorian, L.A. and Cohen, H.M. (1997a), “J-lead solder joint thermal fatigue life model”, Proceedings of the 1997 ASME Winter Annual Meeting, Dallas, TX, pp. 396-400. Wong, T.E., Kachatorian, L.A. and Tierney, B.D. (1997b), “Gullwing solder joint fatigue life sensitivity evaluation”, Journal of Electronic Packaging, Trans. of the ASME, pp. 171-6. Wong, T.E., Lau, C.Y. and Chan, P.C. (2003), “Solder joint thermal fatigue damage evaluation by a simplified method”, Proceedings of the 4th Annual IPC SMEMA APEX Electronic Manufacturing Conference, Anaheim, CA, pp. 746-50. Wong, T.E., Cohen, H.M., Jue, T.Y. and Teshiba, K.T. (1999b), “Ceramic ball grid array solder joint thermal fatigue life prediction model”, Proceedings of InterPack”99, Advances in Electronic Packaging – 1999, EEP-Vol. 26-1, pp. 427-32. Wong, T.E., Suastegui, I., Cohen, H.M. and Matsunaga, A.H. (1998), “Experimentally validated thermal fatigue life prediction model for leadless chip carrier solder joint”, Proceedings of the 1998 ASME Winter Annual Meeting, Anaheim, CA, pp. 15-20. Zussman, M.P. and Powell, D.J. (1996), “Nonwoven aramid – a cost effective surface mount laminate reinforcement”, Technical Paper H-68117, DuPont Company.

[ 45 ]

Reliability testing and data analysis of lead-free solder joints for high-density packages

Keywords Solders, Product reliability, Printed-circuit boards

Abstract Temperature cycling tests, and statistical analysis of the results, for various high-density packages on printed-circuit boards with SnCu hot-air solder levelling, electroless nickel-immersion gold, and organic solder preservative finishes are investigated in this study. Emphasis is placed on the determination of the life distribution and reliability of the lead-free solder joints of these high-density package assemblies while they are subjected to temperature cycling conditions. A data acquisition system, the relevant failure criterion, and the data extraction method will be presented and examined. The life test data are best fitted to the Weibull distribution. Also, the sample mean, population mean, sample characteristic life, true characteristic life, sample Weibull slope, and true Weibull slope for some of the high-density packages are provided and discussed. Furthermore, the relationship between the reliability and the confidence limits for a life distribution is established. Finally, the confidence levels for comparing the quality (mean life) of lead-free solder joints of highdensity packages are determined.



[ 46 ]

John Lau Agilent, Santa Clara, CA, USA Nick Hoo Tin Technology, Middlesex, UK Rob Horsley Celestica, Kidsgrove Staffordshire, UK Joe Smetana Alcatel, Plano, TX, USA Dongkai Shangguan Flextronics, San Jose, CA, USA Walter Dauksher Agilent, Fort Collins, CO, USA Dave Love Sun Microsystems, Menlo Park, CA, USA Irv Menis IBM, Endicott, NY, USA Bob Sullivan HDPUG, Scottsdale, AZ, USA

As mentioned by Smetana et al. (2004), one of the critical issues for lead-free products is solder joint reliability. There are many useful reliability results based on, for example, field data, power/temperature cycling tests, mechanical shearing, bending and twisting tests, shock and vibration tests, electrochemical tests and mathematical modelling, for Sn-Pb solder joints (Lau, 1991; Lau and Rice, 1985; Lee, 2002; Wassink, 1989). However, this is not the case for leadfree solder joints because of their immaturity. Thus, the reliability of lead-free solder joints is currently under scrutiny. A variety of environmental stress factors, e.g. temperature, voltage, humidity, corrosion, current density (electromigration), and mechanical loads, may lead to leadfree solder joint failure. The most common failure modes in practice are overload and fatigue. Overload failure occurs whenever the stress in the solder joint, brought about by the imposed stress factors, is greater than the capacity of the solder material. An example would be excessive bending and twisting of a printed circuit board (PCB) with solder-bumped flip chip (Lau, 1994, 1996, 2000; Lau and Pao, 1997), chip scale packages (CSP) (Lau and Lee, 1999), or ball grid array (BGA) packages (Lau, 1995) soldered to its surface. In this case, the bending and twisting stresses are larger than the strength or fracture toughness of the lead-free solder alloy. Fatigue failure takes place via the initiation and propagation of a crack until it becomes unstable. The stress factors that typically cause failure by fatigue are far below the overload failure levels. Examples of fatigue failure include the temperature cycling and/or vibration of a solderbumped flip chip, CSP, or BGA that is soldered to the surface a PCB. In this study, only temperature fatigue stress factor will be considered. Reliability of the solder joint of a particular package is defined as the probability that the solder joint will perform its intended function for a specified period of time, under a given operating condition, without failure. Numerically,

reliability is the per cent of survivors, i.e. RðtÞ ¼ 1 2 FðtÞ; where R(t) is the reliability (survival) function and F(t) is the cumulative distribution function (CDF). Life distribution is a theoretical population model used to describe the lifetime of a solder joint and is defined as the CDF for the population. Thus, the objective of reliability tests is to obtain failures (the more the better) and to best fit the failure data to (determine the parameters of) the CDF of a chosen probability distribution (e.g. exponential, lognormal, and Weibull). The number of items (sample size) to be tested should be such that the final data are statistically significant. It should be noted that, as soon as the life distribution F(t) of the lead-free solder joint of a particular package is estimated by reliability testing, the reliability R(t) is readily determined. Also, the failure rate, cumulative failure rate, average failure rate, and mean time to failure of the lead-free solder joints can be determined by the equations shown in Lau and Pao (1997). Most reliability tests are accelerated tests (with increased intensity of exposure to aggressive environmental conditions, and realistic sample sizes and test times). Thus, acceleration models (to determine the acceleration factors) are needed to transfer the failure probability, reliability function, failure rate, and mean time to failure from a test condition to a normal operating condition. In establishing the accelerated models of the solder joints, their surrounding materials, (e.g. solder, molding plastic, ceramic, copper, fibre reinforced glass epoxy, and silicon), loadings (e.g. stress, strain, temperature, voltage, humidity, current density, and voltage), and failure mechanisms and modes (e.g. overload, fatigue, corrosion, and electromigration) must be considered. Some common tests for solder-joint reliability are temperature cycling, power cycling, functional cycling, shock and vibration, mechanical shear, pull, push, bend and twist, humidity, corrosion, voltage, current density, etc. In this study, only temperature cycling testing of some high-density packages assembled with a lead-free solder is performed.



Introduction

John Lau, Nick Hoo, Rob Horsley, Joe Smetana, Dongkai Shangguan, Walter Dauksher, Dave Love, Irv Menis and Bob Sullivan Reliability testing and data analysis of lead-free solder joints for high-density packages Soldering & Surface Mount Technology 16/2 [2004] 46–68

In the past four decades reliability has been formulated as the science of estimating and predicting the life distribution of products by the application of theories of probability and statistics (Johnson, 1951, 1964; Weibull, 1951, 1961). Evidence of the intimate relationship between reliability, probability, and statistics is demonstrated in many papers written on statistical methods in reliability (see, for example, the IEEE Transactions on Reliability and ASME Transactions on Reliability). On reviewing some of the paper, one will soon find that reliability has become the playground of mathematicians. Many methods based on sound statistical theories have been proposed for the analysis and solution of reliability problems. However, most of these methods are still either in an ivory tower or not practical enough for regular use. In this study, the reliability of leadfree solder joints is estimated by a temperature cycling test and choosing a probability function, and then is analysed by Johnson’s theory of order statistics (Johnson, 1951, 1964; Lau et al., 1988). In this study, the reliability of lead-free solder joints of high-density packages subjected to temperature cycling is investigated. Emphasis is placed on the determination of the life distribution of these lead-free solder joints. Also, the test data are analysed to provide certain confidence levels.

Components and test board The packages used for this study are shown in Table I. It can be seen that there are many different sizes, pin-counts, leadfinishes and solder ball types for these packages. The more notable ones are: ceramic column grid array (CCGA), plastic ball grid array (PBGA), FLEXBGA, and SMC. The overall dimensions of the 1657CCGA are: 42:5 £ 42:5 £ 6:5 mm3 : The Sn-90(wt per cent)Pb solder columns are arranged in a 41 £ 41 array at 1 mm pitch with six depopulated at each corner. The diameter of the solder columns is 0.5 mm and they are 2.21 mm tall (Lau et al., 2004a). The Sn-90Pb solder columns are joined to the ceramic substrate with Sn-Pb solder and joined to the PCB with either Sn-Ag-Cu or Sn-Pb solder. The pad size on the ceramic substrate is 0.8 mm and on the PCB is 0.673 mm. It should be noted that the CCGA package is not subject to the European lead-free regulations because its solder column content is more than 85 wt per cent of Pb. This is one of the exemptions given by the European Restriction of Hazardous Substances (RoHS) directive. Unlike the CCGA packages, the PBGA packages are made with a bismaleimide triazene (BT) substrate and the

bending stiffness of the PBGA packages is much smaller than that of the ceramic packages. Also, the thermal expansion mismatch between the IC chip and the BT substrate is much larger than that between the IC chip and the ceramic substrate. Thus, there is a dummy chip in most of the PBGA packages tested. For example, the chip sizes in the 256-pin PBGA are 10 £ 10 £ 0:3 mm3 and in the 388-pin PBGA are 8:4 £ 8:4 £ 0:3 mm3 : The overall dimensions of the 256-pin PBGA are 27 £ 27 £ 1:47 mm3 and the 388-pin are 35 £ 35 £ 1:47 mm3 : For both packages, the pad pitch is 1.27 mm and the pads are 0.635 mm in diameter. Unlike PBGA packages, the 144FLEXBGA packages are made from a tape substrate and are in a CSP format (i.e. the package substrate area is less than 1.5 times that of the IC chip area). The bending stiffness of the FLEXBGA packages is smaller than that of the PBGA packages. The overall dimensions of the package are: 14:5 £ 14:25 £ 0:8 mm3 and the solder ball diameter is about 0.3 mm. The solder balls are arranged in a 14 £ 14 array at 0.8 mm pitch with 25 depopulated at the centre. The SMC is a ceramic digital clock, which is designed for use with high-speed timing systems. Differential outputs provide a sine wave that is capable of driving 60 V loads at 800 MHz. The overall dimensions of the SMC are 13:5 £ 9:2 £ 2:05 mm3 : It has eight pads with four on each of the longer edges. The pad dimensions are 1:27 £ 1:93 mm and the pad pitch is 2.54 mm. All pads consist of 30 mm minimum electroless gold on 50 mm minimum electroless nickel over base metal. There is a metallic centre pad ð4:83 £ 2:24 mmÞ; which can be (optionally) grounded on a PCB to provide mechanical support and enhance the solder joint reliability. However, in this study, the centre pad is not soldered to the PCB. The test board which is 193 £ 352 £ 1:6 mm3 is shown in Figure 1. It is made of fibre-reinforced glass and has six copper layers with microvia fabrication. Three different lead-free surface finishes are considered: Sn-Cu hot-air solder levelling (HASL), Entek organic solder preservative (OSP), and electroless nickel-immersion gold (ENIG) or Ni-Au. A total of 20 boards (Table II) are used for the temperature cycling tests.

Test chamber and temperature cycling Thermal cycling was performed in a Thermotron SE600-3-3 environmental chamber. This unit is capable of achieving chamber temperatures as high as 1918C and as low as

Table I High density package type summary Component type BGA BGA BGA BGA BGA BGA BGA BGA CCGA LCSP LQFP PLCC QFP QFP TQFP TSOP TSSOP TSSOP TSSOP SMC (Leadless) Thru-hole receptacle

Pin count

Pitch (mm)

Lead finishes or BGA solder ball/ Column compositions

48 144 64 208 172 196 388 256 1,657 128 176 84 80 208 100 48 56 48 56 8 10

0.75 0.8 0.8 0.8 1 1 1.27 1.27 1 0.5 0.5 1.27 0.5 0.5 0.5 0.5 0.5 0.5 0.5 2.54 2.54

Sn-Pb, Sn-Ag-Cu Sn-Pb, Sn-Ag-Cu Sn-Pb, Sn-Ag-Cu Sn-Pb, Sn-Ag-Cu Sn-Pb, Sn-Ag-Cu Sn-Pb, Sn-Ag-Cu Sn-Pb, Sn-Ag-Cu Sn-Pb, Sn-Ag-Cu 10Sn-90Pb Ni-Au Sn-Pb, Sn-Cu, Sn-Ag, Sn-Pb, Sn-Cu, Sn-Ag, NiPd Sn-Pb, Sn-Cu, Sn-Ag, Sn-Pb, Sn-Cu, Sn-Ag, Sn-Pb, Sn or Sn-Cu NiPd Sn-Pb, Sn or Sn-Cu Sn-Pb, Sn-Cu, Sn Electronless Ni-Au Sn-Pb, Sn

Sn Sn Sn Sn

[ 47 ]


Figure 1 Test board layout

2878C. Heating and cooling are achieved by forced air convection. In order that the chamber operates at peak efficiency, it is important that the airflow in the chamber is disrupted as little as possible. Airflow in the chamber is directed from top to bottom and for this reason, the boards are placed vertically in the chamber. All the boards are placed on a single wire shelf mounted halfway up the chamber. The boards are arranged in two parallel columns of ten panels each. The relative position of each board is shown in Figure 2. To hold them vertically, each row of boards is held in two parallel, notched aluminium holders. Each board

Table II PCB and package sample size details Number of boards 5 5 5 5

[ 48 ]

Board finishes

Solder paste

No. of parts of each type and finish

OSP OSP ENIG Sn-Cu HASL

Sn-Pb Sn-Ag-Cu Sn-Ag-Cu Sn-Ag-Cu

10 10 10 10

is mounted so that the 50-pin connector attachment area (connectors are not populated) and ribbon cable are uppermost. In order to attach to the event detectors, the ribbon cables are passed through a side access port mounted at approximately the same height as the shelf. To prevent disruption to the airflow of the chamber and so as not to prove a hindrance whilst loading other boards, the ribbon cables are threaded straight down through the wire shelf and run across the bottom of the chamber before passing back through the shelf and out of the side entry port. The temperature input to the chamber is shown in Figure 3. It can be seen that the cycle time is 40 min, the temperature is between 0 and 1008C with a 10 min ramp, and a 10 min hold at hot and 10 min hold at cold. The actual results of measurement with thermocouples attached on the PCB surfaces, CCGA1657 ceramic substrate edge, and PBGA388 centres are shown in Figure 4. It can be seen that the: 1

measured temperature profiles have a smaller range than the input temperature profiles,


Figure 2 Schematic of the test board layout within the temperature chamber

Figure 3 Input temperature profile

2 3

maximum temperature range for the CCGA1657 is between ,20 and 928C, and maximum temperature range for the PBGA388 and PCB is between ,15 and 958C.

for the interlinked network. Connection to the test boards is made using ribbon cables comprising of 37 individual wires (32 for monitoring channels and five for common-ground). Eight ribbon cables can be attached via the front panel of each STD-256. The Windatalog package allows the user to determine the frequency at which measurements are taken. This is done by selecting a cycle time and the frequency of resistance measurements (polls) taken per cycle for each channel. Typically, the cycle time of event detection is chosen to match the thermal cycle time. When measurement is triggered, the detectors measure the resistance of each channel in turn. When a potential failure result is generated for a given channel, the software records the time of potential failure in terms of the number of cycles and polls. The default setting for the software is to record the time of each potential failure for a particular channel till a maximum preset number of potential failures are reached (typically 15). After this maximum is reached, the software continues to monitor the channel and record the subsequent percentage of potential failures that occur out of the total number of polls, but does not record the time of each potential failure. Alternatively, the software can be set to record the time of every single potential failure that occurs during testing, but this generates extremely large data files.

Failure criterion and data extraction Data acquisition system During the temperature cycling test, the electrical resistance monitoring in each electrical circuit was performed using four interlinked Anatech STD-256 event detectors. The measured resistance is compared to a reference threshold that, if exceeded, generates a potential failure result. The detector network is controlled using a personal computer (PC) running the Anatech Windatalog (Version 2.0.0) software. Each detector allows 256 individual channels to be monitored, thus giving a maximum total of 1,024 channels

Failure criterion Any channel is deemed to have undergone potential failure when the inherent circuit resistance, as measured by the Anatech Event Detector, exceeds 450 V. Events judged to have been caused by radio frequency (RF) interference, which induces a temporary increase in circuit resistance, are not classed as genuine failure events. During thermal cycling, the Anatech Event Detectors periodically perform a resistance check of each channel being monitored. If the resistance of a circuit is found to be

[ 49 ]


Figure 4 Measured temperature profiles

[ 50 ]

above the threshold resistance value (450 V), the time of the poll and the channel identification number are recorded. However, the actual resistance of a test circuit is never recorded. Thus, this represents a pass/fail criterion. Either the resistance is below 450 V (pass) or the resistance is above 450 V (fail).

Three-cycle moving average The three-cycle moving average (TCMA) is useful for displaying the frequency at which events are being recorded and how the frequency varies with time. Moving averages are often used to assess how values change over a period of time, share prices, batting average, etc. The method works by breaking a long period of time into a large number of smaller periods. For example, over the course of a year it may rain on 22 per cent of the days. This would mean that on an average it rained on 80.3 days. It would not identify when the rainy season occurs. If the year were to be analysed in smaller portions, such as weeks or months, some would have more rainy days than others. By analysing when the highest proportion of rainy days per week or month occurred, the rainy season could be identified. In this exercise a period of three thermal cycles is chosen over which to extract the data. Over the period of three thermal cycles, either 12 or 24 evenly spaced resistance measurements are taken for each test circuit. These measurements are taken using the Anatech event detectors. If the measurement is above 450 V the test is deemed to be a potential failure. The TCMA is calculated by tallying the number of potential failed test results from the first three thermal cycles and dividing by the total number of measurements taken in the three cycles. For each additional measurement, the new measurement is counted and the earliest (of the previous three cycles) discarded. For example, if the first 12 results are tallied, that is the first TCMA value. When the thirteenth result is taken, it is added to the test group with the first measurement left out. When the fourteenth result is recorded the second is discounted and so on. This process is shown in Figure 5. A computer program has been written to identify the time taken for each circuit to reach a genuine circuit resistance of 450 V. The program is designed to distinguish between genuine failures and RF interference events. This is done by analysing the original Anatech data file and identifying the time of each recorded measurement above 450 V. The first

stage of data analysis is to calculate the TCMA for each time when a measurement is taken and represent this frequency data as a percentage. The program then calculates the average (mean) frequency up to that point and the standard deviation (which is a measure of the variation of frequency values). Therefore, for each measurement that has been taken, the current TCMA value, the average TCMA value for all preceding measurements and the standard deviation to that time are calculated. A comparison has to be made to evaluate whether the circuit resistance is actually above 450 V during the thermal cycling. As has been mentioned, the RF behaviour is generally consistent over time and does not tend to change dramatically. When genuine failures occur the frequency of failure reporting increases by a significant margin and remains at this elevated level. For each calculated TCMA value, the program compares it to the mean and standard deviation of all the preceding values. The program is basically looking for dramatic changes of frequency behaviour. When it finds one, it triggers a higher level of investigation. The change necessary to trigger this next stage is if a value is found that is larger than the mean average TCMA þ 2s (standard deviation), for all the preceding TCMA values. If an increase in the frequency is found that is larger than the mean average TCMA þ 2s, the program looks to see if this behaviour is sustained. The program calculates the average values for the next 20 thermal cycles, i.e. 80 TCMA values for four poll/cycle or 160 for eight poll/cycle. If the average TCMA value over the next twenty cycles is below the mean average TCMA þ 2s of all the TCMAs calculated prior to the trigger value then the time is not recognized as the genuine failure point and the program continues its search. If the average TCMA for the next 20 cycles is larger than the mean average TCMA þ 2s, then the point is recognized as the failure point.

Data extraction The event detectors record every instance of a channel circuit exceeding the threshold resistance value (450 V). This considers both genuine and RF-generated events. Neither the detectors nor the Anatech software can distinguish between a genuine event and an RF-generated effect. In an ideal world, no RF-generated events would be detected and therefore, prior to fatigue cracks increasing the resistance of a circuit, no measurement would exceed 450 V. As fatigue crack growth is the only active mechanism by which the resistance of the channel circuits can increase, the time at which the event detector records the first measurement above 450 V can be defined as the “failure” point of the circuit. An example of this type of behaviour is shown in Figure 6. For the failure shown in Figure 6, prior to 7,189 cycles, no measurements above 450 V were recorded. After this point, all measurements were above 450 V. The failure point could therefore be easily identified. On some circuits, RF-generated events are recorded. In order to make a judgment on the “failure” time of a circuit it is necessary to filter these false events from the data. RF interference is random in severity and occurrence. In affected circuits, RF interference creates a “background” level of false events that, if severe enough, can mask the onset of genuine failures. Figure 7 shows the background level of noise generated by RF interference in a circuit whose resistance has not exceeded 450 V. This noise temporarily increases the effective resistance of the test circuit so that the event detector believes the threshold resistance has been exceeded. In fact, the events are false and the circuit has not failed. In order to identify and filter the RF-generated events, it is found that the best way is by a frequency analysis. This shows the proportion of “failure” events as a percentage of the number of measurements taken over a short period of time. If a change in the electrical resistance of the circuit occurs, it would be expected that there would be a corresponding change in the percentage of measurements


that record values over 450 V. The response must be measured over a fairly short period of time as an increase or decrease would be averaged over a long period of time would be difficult to resolve. It is found that the identification of changes in the frequency data is optimum when the percentage of failed events over three thermal cycles, during which either four or eight measurements are made, is plotted versus time for a given channel. Using this method it is found that the RF signal varies randomly, but over time tends to average out at a specific level. The level of RF noise can be determined as it is known that no fatigue

cracks are present in the solder joints very early on in testing and that the circuit resistances are all below 450 V. The level of RF noise can increase and decrease with time, but when it does so, the change usually occurs gradually over a large number of cycles. In some cases, RF spikes are detected where the frequency of false events increases dramatically but then returns to its initial background level after a very short period of time. When genuine failures occur, the frequency of failed events increases. The rise is usually large, sudden and, to a large extent “irreversible”. In many cases, the frequency of

Figure 5 Schematic of the construction of the TCMA values

Figure 6 An ideal fatigue failure

[ 51 ]


Figure 7 A channel experiencing the effects of RF noise. Note the x-axis origin should be at 6,326 cycles and not zero

failed events rises to 100 per cent i.e. every measurement taken by the event detectors yields a value in excess of 450 V. In some cases, the frequency of failed measurements does not reach 100 per cent. In all cases though, an increase in the frequency is observed. This means that the average frequency of resistance measurements above 450 V is higher after the genuine failure point is reached than before. This difference in frequency behaviour can be observed when a graph of the TCMA is plotted as shown in Figure 8, where the significant and prolonged change in behaviour (for more than 20 thermal cycles) achieves the failure criterion. A second prolonged rise in TCMA is also recorded, but failure can only be recorded once. Figures 9 and 10 show variations on the behaviour of different circuits that eventually do fail. The circuit shown in Figure 9 is subject to RF interference. A relatively low-level of failure events is generated during thermal cycling before failure. Once the inherent circuit resistance does rise above 450 V, all measurements exceed the threshold resistance value. Similar failure behaviour is seen in Figure 10. Before failure, channel 552 displayed a far higher frequency of background events. Even so, the failure point is still readily identifiable. Figure 11 shows the TCMA plot for a 1657CCGA that was soldered using Sn-Pb solder paste. It can be seen that based on the present failure criterion and data extraction method, this is not a failure! As a matter of fact, none of the 1657CCGA packages soldered with Sn-Pb paste suffered failure, and only 3 of the 9 registered any recorded resistance failures in the last 1,212 thermal cycles of the experiment.

The sample mean life (m) and the per cent failed at the mean [F(m)] can be determined by, respectively.

m ¼ uGð1 þ 1=bÞ; and FðmÞ ¼ 1 2 e2½G

Simple statistics The Weibull distribution is used to fit the test data to determine the characteristic life (u) and Weibull slope (b).

[ 52 ]

b

ð1þ1=bÞ

;

ð2Þ

where G is the gamma function. The Weibull slope for a given sample size determined by the least squares method is only an estimate of the true population slope. The error (E) of the Weibull slope depends on the number of failures (N) and the confidence level (C) and can be determined by ffi Z Epffiffiffiffi 2N 1 ð1 þ CÞ t2 pffiffiffiffiffiffi : ð3Þ e2 2 dt ¼ 2 2p 21 It is well known that the integral on the left-hand side cannot be integrated in a closed-form. In this study, it is approximated as follows (Abramowitz and Stegun, 1970): ffi Z Epffiffiffiffi 2N 1 t2 pffiffiffiffiffiffi e2 2 dt ¼ 1 2 ZðxÞðb1 t þ b2 t 2 þ b3 t 3 2p 21 þ b4 t 4 þ b5 t 5 Þ þ 1ðxÞ;

ð4Þ

where 1 x2 ZðxÞ ¼ pffiffiffiffiffiffi e2 2 ; 2p t¼

Life distributions of lead-free solder joints

ð1Þ

1 1 þ px

ð5Þ

ð6Þ

and p ¼ 0:2316419; b1 ¼ 0:31938153; b2 ¼ 20:356563782; b3 ¼ 1:781477937; b4 ¼ 21:821255978; b5 ¼ 1:330274429; and j1ðxÞj , 7:5 £ 1028:


Figure 8 An example where there is no RF noise prior to failure but when failure does occur, the TCMA does not increase to 100 per cent

Figure 9 Low-level background of false events prior to a rapid deterioration in circuit integrity

[ 53 ]


Figure 10 A substantial, but consistent level of RF interference is followed by a dramatic rise in TCMA values when genuine failures start to occur

Figure 11 TCMA plot of 1657CCGA with Sn-Pb solder paste on PCB

[ 54 ]


Thus, for a given confidence level and number of failures, the Weibull slope error can be searched for using the above equations. For example, given N ¼ 10 and C ¼ 95 per cent; then E ¼ 44 per cent: One of the difficult tasks in statistical analysis of life-test data is to draw conclusions about a population from a small sample size. It is even more difficult to compare the populations of two products from the knowledge of their test data. If the quality (mean life) of one product lot is found to be superior to another, what level of confidence P, can be had that the same is true of the population? A simple yet useful equation given by Johnson (1951, 1964) is summarized as follows and adopted for this study: P¼

1 1=q 1 þ loglog 1=ð12qÞ

ð7Þ

;

where q¼12h

t¼

1þ

1 tþ4:055 i40=7 ;

ð8Þ

6:12

i pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffih h2 hh1 1 þ T r 1 2 hð12 h2 Þ 2 1 2 ð12h1 Þ

r V2 þ V1

;

ð9Þ

T ¼ ðr1 2 1Þðr2 2 1Þ;

ð10Þ

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Gð1 þ 2=b1 Þ 2 1; V1 ¼ G2 ð1 þ 1=b1 Þ

ð11Þ

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Gð1 þ 2=b2 Þ 2 1; G2 ð1 þ 1=b2 Þ

ð12Þ

V2 ¼

hh1 ð1 2 h2 Þ ; h2 ð1 2 h1 Þ

ð13Þ

h1 ¼

m1 min ; m1

ð14Þ

h2 ¼

m2 min ; m2

ð15Þ

h¼

m2 min : m1 min

ð16Þ

r¼

In the above equations, m1 and m2 are the mean lives, b1 and b2 are the Weibull slopes, r1 and r2 are the number of failures, m1 min and m2 min are the expected minimum values, respectively, of samples 1 and 2, and T is called the total degrees of freedom. In order to determine the life distributions of lead-free solder joints at certain confidence levels (e.g. 95 per cent confidence level), certain rankings (other than the median rank) of the life-test data are necessary and can be determined by the following equation: nðn 2 1Þ 2 z ð1 2 zÞn22 2 · · · 1 2 ð1 2 zÞn 2 nzð1 2 zÞn21 2 2! ð17Þ nðn 2 1Þ. . .ðn 2 j þ 1Þ j21 z ð1 2 zÞn2jþ1 ¼ G: 2 ð j 2 1Þ! In this equation, j is the failure order number, n is the number of samples, G is the required ranking, and z is the per cent rank of the jth value in n. Thus, for a given set of values of G, n, and j, the value of z (0,z , 1) can be searched from the above equation. For example, given the sample size n ¼ 10; and the required ranking G ¼ 95 per cent; then the first value in n is 0.2589. This means that in 95 per cent of the cases the lowest of ten would represent as much as 25.89 per cent of the population. Only in 5 per cent of cases would the lowest

of ten represent even more than 25.89 per cent of the population.

Statistical analysis of 1657CCGA lead-free solder joints Table III shows the test results for the 1657CCGA package with the Sn-Pb and Sn-Ag-Cu solder pastes on the Sn-Cu HASL, Ni-Au, and OSP PCBs. It can be seen that: 1 there are failures on all the three PCBs with the leadfree paste, 2 all the samples with lead-free paste on the OSP PCB are failed, and 3 there were no failures with the Sn-Pb solder paste. A physical explanation for this last observation was given by Lau et al. (2004a). It is because the Young’s modulus of the lead-free solder is higher (stiffer) than that of the Sn-Pb solder. The failure location is in the high-lead column near the “vertex” of the substrate solder fillet and the PCB solder fillet. The test data for the CCGA’s Sn-10Pb columns with lead-free paste on the OSP PCB are plotted in Figure 12(a) with the 70 and 95 per cent confidence limits. It can be seen and expected that, for a given per cent failed, the life (number of cycles to failure) range (interval) is larger for the higher confidence level. It should be pointed out that there is a failure at cycle 2 for the Ni-Au finished board. This is likely to be due to manufacturing defects and eliminated from the statistical analysis. The test data of the CCGA with lead-free paste on the SnCu HASL and Ni-Au PCBs are plotted with 95 per cent confidence level in Figure 12(b) and (c), respectively. It can be seen that, besides the median rank, the test data are plotted on the same paper against 2.5 and 97.5 per cent ranks. The resultant plot yields a 95 per cent confidence interval within which the mean and characteristic values will lie. These values are shown in Table IV. In the case of the CCGA with lead-free paste on a Sn-Cu HASL PCB, from the test sample one would conclude that the mean life (quality) of the solder joints is 6,328 cycles. However, the true mean life, in 95 out of 100 cases (95 per cent confidence level), can be as low as 4,898 cycles and as high as 6,939 cycles. Similarly, the characteristic life can be at least 5,756 cycles, but not more than 7,298 cycles at 95 per cent confidence level. Similar conclusions can be made for other cases. The Weibull slope error for all the cases has been determined and shown in Table IV. It can be seen that (for example, in the case of the CCGA with lead-free paste on the Sn-Cu HASL PCB), in 95 out of 100 cases, the Weibull slope error is 52 per cent and the true Weibull slope can be as low as 2.76 and as high as 8.74. Figure 12(d) shows the median rank plots of the CCGA with lead-free solder paste on the Sn-Cu HASL, Ni-Au, and OSP PCBs. It should be emphasized that this kind of plot is absolutely meaningless, from the statistical points of view, unless the confidence level for each pair of mean-life ratios

Table III 1657CCGA temperature test results (, 22- , 928C, 40 min cycle) Solder paste Sn-Ag-Cu

Sn-Pb

Sn-Cu HASL

PCB ENIG (Ni-Au)

4,537 4,787 5,575 6,018 6,033 6,590 6,990

2 5,844 6,167 6,432 7,041

NA

NA

OSP (Entek) 4,911 5,030 5,233 5,336 5,883 6,284 6,843 6,929 7,109 7,341 No failures

[ 55 ]


Figure 12 Weibull plot of solder joint failures for a 1657CCGA

(Continued )

[ 56 ]


Figure 12

[ 57 ]


Table IV Mean life, characteristic life, and Weibull slope of the 1657CCGA (Sn-90Pb) solder columns with Sn-Ag-Cu solder paste on various PCBs Sn-Ag-Cu paste On

Mean life (m), cycle Sample Per cent failed at mean Population mean at 95 per cent confidence level Characteristic life (u), cycle Sample True u (cycle) at 95 per cent confidence level Weibull Slope (b) Sample Weibull slope error (per cent) at 95 per cent confidence level True Weibull slope at 95 per cent confidence level

Sn-Cu HASL PCB

Ni-Au PCB

OSP PCB

6,328 47.29 4,898 # m # 6,935

7,040 45.56 5,682 # m # 7,326

6,074 46.69 4,962 # m # 6,584

6,838 5,756 # m # 7,298

7,410 6,703 # m # 7,551

6,502 5,595 # m # 6,899

5.75 52

9.71 69

6.89 44

2.76 # b # 8.74

3.01 # b # 16.41

3.86 # b # 9.92

(comparisons) is given. Table V shows the mean-life ratios of the CCGA on these PCBs. It can be seen that: 1 the quality (mean life) of CCGA solder joints on a Ni-Au PCB is superior to those on a Sn-Cu HASL PCB with 83 per cent confidence level, i.e. in 83 out of 100 cases, the solder joints on a Ni-Au PCB are better than those on a Sn-Cu HASL PCB (this could be due to the flatness/printability and consistency of the solder pastes on Ni-Au vs an uneven Sn-Cu HASL finish); 2 at 98 per cent confidence level the solder joints on Ni-Au PCBs are better than those on OSP PCBs (this could be due to better wetting to the Ni-Au finish than OSP finish and thus, the solder columns are more centred); and 3 in only 66 out of 100 cases, the solder-joint mean life on Sn-Cu HASL PCBs is better than that on OSP PCBs (this confidence level could be too low to make sound decisions).

Statistical analysis of SMC8 lead-free solder joints The test data for the SMC leadless components with lead-free and Sn-Pb solder paste on Sn-Cu HASL, Ni-Au, and OSP PCBs are shown in Table VI. It can be seen that: 1 there are failures of the SMC lead-free joints on all of the PCBs, and 2 all of the SMC lead-free solder joints on the Ni-Au PCBs. The possible reasons for the SMC8 failures are: 1 the centre pad of the SMC is not soldered onto the PCB; 2 the thermal expansion mismatch between the leadless ceramic carrier and the PCB; and 3 gold embrittlement.

PCB are shown in Figure 13. Their sample and population mean life, true characteristic life, and true Weibull slope are shown in Table VII. It can be seen that, e.g. for the SMC lead-free solder joints on a Ni-Au PCB that: 1 the percentage failed at the sample mean (5,016) is 48.66 per cent and the population mean at 90 per cent confidence level is as low as 3,884 cycles and as high as 5,746 cycles; 2 the sample characteristic life is 5,512 cycles and the true characteristic life is between 4,511 and 6,293 cycles; and 3 the sample Weibull slope is 4.3 and the true Weibull slope is between 2.71 and 4.46. Similar conclusions can be made about other cases. Figure 14 and Table VIII show a comparison of the mean lives (quality) of the SMC lead-free and Sn-Pb solder joints for all the PCB finishes. It can be seen that there are six comparisons of the mean life of these solder joints, with six corresponding determined confidence levels. For example, the SMC lead-free solder joints on an OSP PCB are better than those on a Ni-Au PCB (with 94.08 per cent confidence level) and is better than the SMC Sn-Pb solder joints on an OSP PCB with 99.97 per cent confidence level. However, the SMC lead-free solder joints on the OSP PCBs was better than that for the Sn-Cu HASL PCBs with only 55.53 per cent confidence level (i.e. 55 out of 100 cases) – essentially it is

Table VI SMC8 solder joint temperature test results (, 18-958C, 40 min cycle) with Sn-Pb and Sn-Ag-Cu solder pastes Solder paste Sn-Ag-Cu

The life distributions (with 90 per cent confidence level) of the SMC lead-free solder joints on the OSP, Sn-Cu HASL, and Ni-Au PCBs and SMC Sn-Pb solder joints on the OSP Table V Mean life ratios of the 1657CCGA (Sn-90Pb) solder columns with Sn-Ag-Cu solder paste on various PCBs Different assembly

Assigned symbol

Mean life, cycle

Mean life ratio (Comparison)

Determined confidence level (per cent)

Sn-Ag-Cu paste on Sn-Cu HASL PCB Sn-Ag-Cu paste on Ni-Au PCB Sn-Ag-Cu paste on OSP PCB

A

6,328

B/A ¼ 1.11

83

B

7,040

B/C ¼ 1.16

98

C

6,074

A/C ¼ 1.04

66

[ 58 ]

Sn-Pb

Sn-Cu HASL 3,573 4,582 4,813 5,619 5,820 6,227 6,433

NA

PCB ENIG (Ni-Au) 3,309 3,540 4,259 4,403 4,523 4,782 6,020 6,238 6,328 6,773 NA

OSP (Entek) 4,047 4,917 5,131 5,653 6,232 6,257 6,401 7,034

2,833 3,075 3,076 3,190 3,300 3,363 3,421 3,747 5,356


Figure 13 Weibull plot of solder joint failures for the SMCB (90 per cent confidence)

(Continued )

[ 59 ]


[ 60 ]

Figure 13


Table VII Mean life, characteristic life, and Weibull slope of the SMC8 solder joints with Sn-Ag-Cu and Sn-Pb solder pastes on various PCBs Sn-Ag-Cu paste on

Mean life (m), cycle Sample Per cent failed at mean Population m at 90 per cent confidence level Characteristic life (u), cycle Sample True u (cycle) at 90 per cent confidence level Weibull slope (b) Sample b error (per cent) at 90 per cent confidence level True b at 90 per cent confidence level

Sn-Cu HASL PCB

Ni-Au PCB

OSP PCB

Sn-Pb paste on OSP PCB

5,958 48.48

5,016 48.66

6,076 47.54

3,657 48.57

4,648 # m # 6,586

3,884 # m # 5,746

4,936 # m # 6,690

2,848 # m # 4,254

6,530 5,474 # m # 7,019

5,512 4,511 # m # 6,293

6,584 5,668 # m # 7,079

4,014 3,318 # m # 4,549

4.48 44

4.3 37

5.46 42

4.38 39

2.51 # b # 6.45

2.71 # b # 4.46

3.17 # b # 7.75

2.67 # b # 6.09

Figure 14 Weibull plot of solder joint failures for the SMC8 on lead-free/Sn-Pb PCBs (median rank)

statistically the same. Similar conclusions can be made about the other cases.

Statistical analysis of 144FLEXBGA lead-free solder joints Table IX shows the life-test data for the 144FLEXBGAs on Sn-Cu HASL, Ni-Au, and OSP PCBs. It can be seen that 1 there are no failures for the Sn-Ag-Cu balled FLEXBGA with both Sn-Pb and Sn-Ag-Cu solder pastes on all the PCBs; 2 there are lots of failures of the Sn-Pb balled FLEXBGA with Sn-Pb paste on the OSP PCBs; and 3 the only failure of the FLEXBGA with Sn-Ag-Cu paste on the OSP PCB was after a very high number of cycles (.7,155).

The statistical analysis of the test data is shown in Figure 15 and Tables X and XI. It can be seen that, e.g. the FLEXBGA with lead-free paste on Sn-Cu HASL PCBs: 1 the quality (mean life) of the solder joints is at least 6,148 cycles, but not more than 10,777 cycles with a 90 per cent confidence level; 2 the true characteristic life of the solder joints is between 8,862 and 11,580 cycles at a 90 per cent confidence level; and 3 the Weibull slope error is 67 per cent and the true Weibull slope (uniformity of the product) is between 0.8 and 4.07 with a 90 per cent confidence level. The quality (mean life) of the Sn-Pb balled FLEXBGA with lead-free solder paste on the Sn-Cu HASL PCBs is better than those on a Ni-Au PCB with 66 per cent confidence level, however, it is better than the Sn-Pb balled

[ 61 ]


Table VIII Mean life ratios of the SMC8 with Sn-Ag-Cu and Sn-Pb solder pastes on various PCBs Different assembly Sn-Ag-Cu paste on Sn-Cu HASL PCB Sn-Ag-Cu paste on Ni-Au PCB Sn-Ag-Cu paste on OSP PCB Sn-Pb paste on OSP PCB

Assigned symbol

Mean life, cycle

A B C D

5,958 5,016 6,076 3,657

Table IX 144BGA temperature test results (, 18-,958C, 40 min cycle) with Sn-Pb and Sn-Ag-Cu solder pastes PCB Solder ball

Solder paste

Sn-Pb

Sn-Ag-Cu

Sn-Pb

Sn-Ag-Cu

Sn-Ag-Cu Sn-Pb

Sn-Cu HASL

ENIG (Ni-Au)

OSP (Entek)

4,398 4,747 7,152

7,155

NA

3,605 5,143 7,006 7,218 7,286 NA

No failures NA

No failures NA

4,694 4,950 6,238 6,239 6,544 6,775 6,930 No failures No failures

FLEXBGA with Sn-Pb paste on an OSP PCB with 94 per cent confidence level. Similar conclusions can be made for the other cases. Since the smaller population mean life of the 144FLEXBGA solder joints is more than 5,000 cycles, they should be reliable for use in most applications.

Statistical analysis of CCGA, SMC, and BGA lead-free solder joints In this section, all of the test data for Sn-Ag-Cu solder paste on all the different (Sn-Cu HASL, Ni-Au, and OSP) PCB types are grouped together for each of the CCGA, SMC, and FLEXBGA assemblies. The solder joint life distributions of the CCGA, SMC, and FLEXBGA (with 95 per cent confidence) are shown in Figures 16, 17 and 18, respectively. The relationship between reliability and confidence can be established from these figures. The three curves (2.5 per cent median and 97.5 per cent ranks) correspond to confidence levels of 2.5, 50, and 97.5 per cent, and the percentage failed (ordinate scale) to percentage reliability (100 – per cent failed). For example, for the CCGA, as shown in Figure 16, at 5,000 cycles, the reliability is 98.05 per cent with a 2.5 and 90.8 per cent confidence level at 50 per cent confidence level, and 76.8 per cent at 97.5 per cent confidence level. Thus, one may expect that in 975 out of 1,000 cases the reliability will be 76.8 per cent, that is, 76.8 per cent of the population will survive 5,000 cycles. Similar conclusions can be made about other cases. Figure 19 shows the comparison between the SMC and CCGA solder joints with Sn-Ag-Cu solder paste at median rank and Table XII shows their mean life, characteristic life, and Weibull slope. Table XIII shows that in 9,855 out of 10,000 cases the mean life (quality) of the CCGA solder joints is better than that of the SMC solder joints. Again, it should be noted that the centre pad of the SMC is not soldered onto the PCBs and all the thermal expansion mismatch between the ceramic and the PCB is applied to the very low standoff (,zero compliance) solder joints. Also, gold embrittlement could be an issue.

[ 62 ]

Mean life ratio (comparison)


C/D ¼ 1.66 C/B ¼ 1.21 C/A ¼ 1.02 A/B ¼ 1.19 A/D ¼ 1.63 B/D ¼ 1.37

99.97 94.08 55.53 89.39 99.89 98.81

Statistical analysis of the 256 and 388-pin PBGA lead-free solder joints Table XIV shows the life test results for the 256PBGA. It can be seen that there were only two failures between all of the 256PBGAs tested, namely, one of the lead-free solder joints on the Sn-Cu HASL PCB failed at 6,750 cycles, and the other failure was at 6,795 cycles for a Sn-Pb solder ball with lead-free solder paste joints. Since they failed at such high numbers of cycles, their solder joints are considered sufficiently reliability for use in most applications, but this conclusion is not statistically significant. Table XV shows the test data for the 388PBGA. As for to the 256PBGA, there were just a few failures, with many of the samples not failing after 7,500 cycles, and the small number of failures were at high cycles, so their solder joints should be reliable for most applications. There was one failure at cycle 2, which is probably due to manufacturing defects. By comparing the test results between the 256PBGA and 388PBGA, it can be seen that the solder joints of the 256PBGA should last longer than those of the 388PBGA, since the dimensions of the 256PBGA is smaller than that of the 388PBGA. Again, this conclusion is not statistically significant.

Summary and recommendation The lead-free thermal-fatigue solder-joint reliability of highdensity packages, such as the 1657CCGA, SMC8, 144BGA, 256PBGA, and 388PBGA, has been determined by temperature cycling tests and statistical analyses. The data acquisition system, failure criterion, and data extraction method have also been presented and discussed. The test data for over 7,000 cycles between 15–208C and 90– 958C, in a 40 min cycle, have been analysed with certain levels of confidence. Some important results are summarized in the following. . For the 1657CCGA, there were no solder joint failures on all the OSP PCBs with the Sn-Pb solder paste. . The quality (mean life) of the lead-free solder pasted 1657CCGA solder joints on Ni-Au PCBs is better than those on Sn-Cu HASL PCBs with an 83 per cent confidence level. . In 98 out of 100 cases, the mean life of 1657CCGA solder joints with lead-free solder paste on a Ni-Au PCB is better than those on an OSP PCB. . For the lead-free solder pasted 1657CCGA, the solder joint mean life on a Sn-Cu HASL PCB is better than that on an OSP PCB, but with only 66 per cent confidence. This confidence level may not be high enough to make sound decisions. . At 5,000 cycles, the reliability of all of the lead-free solder pasted 1657CCGA solder joints on all of the Sn-Cu HASL, Ni-Au, and OSP PCBs is 90.8 per cent, with a 50 and 76.8 per cent at a 97.5 per cent confidence levels. . For all of the lead-free solder pasted 1657CCGA solder joints, on all the PCBs, at a 95 per cent confidence level, the population mean is at least 5,929 cycles, but not more than 6,905 cycles. The true characteristic life is between 6,499 and 7,212


Figure 15 Weibull plot of solder joint failures for the 144BGA Sn-Pb solder balls on

(Continued )

[ 63 ]


Figure 15

.

[ 64 ]

cycles. The true Weibull slope is between 4.8 and 9.12. These are more than adequate for most of the expected applications. The SMC lead-free solder joints on OSP PCBs are better than those on Ni-Au PCBs with a 94.08 per cent confidence level. Also, they are better than the SMC Sn-

.

Pb solder joints on OSP PCBs with 99.97 per cent confidence. The mean life of the SMC lead-free solder joints on OSP PCBs are better than those on Sn-Cu HASL PCBs, but with only 55 per cent confidence level. This means that their quality is about the same.


Table X Mean life, characteristic life, and Weibull slope of the 144BGA (Sn-Pb) solder joints with Sn-Ag-Cu and Sn-Pb solder pastes on various PCBs Sn-Ag-Cu paste On

Mean life (m), cycle Sample Per cent failed at mean Population mean at 90 per cent confidence level Characteristic life (u), cycle Sample True u (cycle) at 90 per cent confidence level Weibull slope (b) Sample Weibull slope error (per cent) at 90 per cent confidence level True Weibull slope at 90 per cent confidence level

Sn-Cu HASL PCB

Ni-Au PCB

Sn-Pb paste On OSP PCB

10,124 52.59

8,711 51.79

6,613 47.27

6,148 # m # 10,777

5,864 # m # 9,615

5,433 # m # 7,163

11,417 8,862 # m # 11,580

9,797 7,531 # m # 10,381

7,141 6,233 # m # 7,555

2.43 67

2.68 53

5.81 44

0.8 # b # 4.07

1.26 # b # 4.11

3.25 # b # 8.37

Table XI Mean life ratios of the 144BGA Sn-Pb solder joints with Sn-Ag-Cu and Sn-Pb solder pastes on various PCBs Different assembly Sn-Ag-Cu paste on Sn-Cu HASL PCB Sn-Ag-Cu paste on Ni-Au PCB Sn-Pb paste on OSP PCB

Assigned symbol

Mean life, cycle



A B C

10,124 8,711 6,613

A/B ¼ 1.16 A/C ¼ 1.53 B/C ¼ 1.32

66 94 99

Figure 16 Weibull plot for 1657CCGA solder columns with Sn-Ag-Cu paste on all PCBs (95 per cent confidence level)

[ 65 ]


Figure 17 Weibull plot for SMC solder joints with Sn-Ag-Cu paste on all PCBs (95 per cent confidence level)

Figure 18 Weibull plot for BGA144 Sn-Pb solder ball with Sn-Ag-Cu paste on all PCBs (95 per cent confidence level)

[ 66 ]


Figure 19 Weibull plot for SMC8 and CCGA1657 solder joints with Sn-Ag-Cu paste on all PCBs (median rank)

Table XII Mean life, characteristic life, and Weibull slope of the SMC and 1657CCGA (Sn-90Pb solder columns) with Sn-Ag-Cu solder pastes on all PCBs

.

.

Mean life (m), Cycle Sample Per cent failed at mean Population m at 95 per cent confidence level Characteristic life (u), cycle Sample True u (cycle) at 95 per cent confidence level Weibull Slope (b) Sample b error (per cent) at 95 per cent confidence level True b at 95 per cent confidence level

SMC8 with Sn-Ag-Cu paste on all PCBs

CCGA1657 with Sn-90Pb columns and Sn-Ag-Cu paste on all PCBs

5,684 48.11

6,543 46.61

4,929 # m # 6,203

5,929 # m # 6,905

6,198 5,529 # m # 6,576

6,996 6,499 # m # 7,212

4.87 30

6.96 31

.

.

3.41 # b # 6.33

4.80 # b # 9.12 .

.

The SMC lead-free solder joints on Sn-Cu HASL PCBs are better than those on the Ni-Au PCBs with 89.39 per cent confidence level. Also, it is better than the SMC Sn-Pb solder joints on an OSP PCB with 99.89 per cent confidence level.

The SMC lead-free solder joints on Ni-Au PCBs are better than the SMC Sn-Pb solder joints on the OSP PCBs with 98.81 per cent confidence level. For all the SMC lead-free solder joints on all of the Sn-Cu HASL, Ni-Au, and OSP PCBs, at 95 per cent confidence level, the true Weibull slope is between 3.41 and 6.33, and the population mean life is at least 4,929 cycles, but not more than 6,203 cycles. The true characteristic life is between 5,529 cycles and 6,576 cycles. These are adequate for most of the expected applications. This is especially true if the centre pad is soldered onto the PCB. The solder-joint quality (mean life) of the 1657CCGA with lead-free solder paste on all of the Sn-Cu HASL, Ni-Au, and OSP PCBs is better (with 98.55 per cent confidence level) than that of the SMC with lead-free solder paste on all the Sn-Cu HASL, Ni-Au, and OSP PCBs. There were no solder joint failures on the lead-free balled 144FLEXBGA with both lead-free and Sn-Pb solder pastes on all the Sn-Cu HASL, Ni-Au, and OSP PCBs. In only 66 out of 100 cases, the quality (mean life) of the solder joints of Sn-Pb balled FLEXBGA with lead-free solder paste on a Sn-Cu HASL PCB is better than that on a Ni-Au PCB. However, it is better than that with Sn-Pb solder paste on an OSP PCB with 99 per cent confidence level.

Table XIII Mean life ratios of the CCGA1657 and SMC8 solder joints with Sn-Ag-Cu solder paste on various PCBs Different assembly CCGA1657 with Sn-90Pb columns and Sn-Ag-Cu paste on all PCBs SMC8 with Sn-Ag-Cu paste on all PCBs

Assigned symbol

Mean life, cycle


Determined confidence level

A

6,543

A/B ¼ 1.15

98.55 per cent

B

5,684

[ 67 ]


Table XIV 256PBGA temperature test results (, 18-,958C, 40 min cycle) with Sn-Pb and Sn-Ag-Cu solder balls and pastes PCB Solder ball Sn-Ag-Cu Sn-Pb

Solder paste

Sn-Cu HASL

ENIG (Ni-Au)

OSP (Entek)

Sn-Ag-Cu Sn-Pb Sn-Ag-Cu Sn-Pb

6,750 NA 6,795 NA

No failures NA No failures NA

No failures No failures No failures No failures

Table XV 388PBGA temperature test results (, 18-,958C, 40 min cycle) with Sn-Pb and Sn-Ag-Cu solder balls and pastes

The authors of this paper would like to acknowledge and thank the many unnamed contributors from the various companies that made this test program possible. These include, but are probably not limited to, contributions from unnamed people at, or formerly employed at, Agilent, Alcatel, Amkor, Celestica, ChipPac, Fairchild Semiconductor, Flextronics, HDPUG, Hewlett Packard Company, IBM, International Tin Research Institute, Lucent, National Semiconductor, Nokia, Nortel Networks, RF Monolithics, ST Microelectronics, Sun Microsystems, Texas Instruments, and Thomas and Betts. Special thanks to Steady Frater, Tom Dyson, and Alan Tan of the Celestica Ashton facility, for their help in making the assembly possible, and to Ruben Bergman of HDPUG, Ted Lancaster and Pete Woodhouse of Agilent for their strong support of this project.

[ 68 ]

PCB Solder ball

Solder paste

Sn-Cu HASL

ENIG (Ni-Au)

OSP (Entek)

Sn-Ag-Cu

Sn-Ag-Cu Sn-Pb

No failures NA

No failures NA

Sn-Pb

Sn-Ag-Cu

5,931

No failures

Sn-Pb

NA

NA

No failures 4,206 5,941 2 7,190 3,281 5,941

.

.

.

.

.

The quality of the Sn-Pb balled FLEXBGA solder joints with lead-free solder paste on Ni-Au PCB is better than that with Sn-Pb solder paste on an OSP PCB with 99 per cent confidence level. At a 90 per cent confidence level, the quality (population mean life) of all the FLEXBGA solder joints is larger than 5,000 cycles. Thus, the solder joints of the FLEXBGA should be reliable for use in most operating conditions. For the 256PBGA and 388PBGA solder joints, there are not enough failures to perform statistical analysis. Since their mean lives, or number of cycles-to-failure, are more than 5,000 cycles, they should be considered reliable for use, but this is not a statistically supported statement. For lead-free solders, in order to transfer the life distribution and reliability function under test conditions to the operating conditions, acceleration models for determining the acceleration factors are desperately needed. The failure modes and analyses on the lead-free solder joints of high-density packages have been reported and examined by Lau et al. (2004b).

References Abramowitz, M. and Stegun, J. (1970), Handbook of Mathematical Functions, Dover Publications, New York, NY. Johnson, I.G. (1951), “The median ranks of sample values in their population with an application to certain fatigue studies”, Industry Mathematics, Vol. 2, pp. 1-9. Johnson, L.G. (1964), The Statistical Treatment of Fatigue Experiments, Elsevier Publishing Company, Amsterdam, The Netherlands. Lau, J.H. (1991), Solder Joint Reliability – Theory and Applications, Van Nostrand Reinhold, New York, NY. Lau, J.H. (1994), Chip on Board Technologies for Multichip Modules, Van Nostrand Reinhold, New York, NY. Lau, J.H. (1995), Ball Grid Array Technology, McGraw-Hill, New York, NY. Lau, J.H. (1996), Flip Chip Technologies, McGraw-Hill, New York, NY. Lau, J.H. (2000), Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, McGraw-Hill, New York, NY. Lau, J.H. and Lee, S.W.R. (1999), Chip Scale Packages, McGraw-Hill, New York, NY. Lau, J.H. and Pao, Y.H. (1997), Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, McGrawHill, New York, NY. Lau, J.H. and Rice, D. (1985), “Solder joint fatigue in surface mount technology: state-of-the-art”, Solid State Technology, Vol. 28, pp. 91-104. Lau, J.H., Harkins, G., Rice, D., Kral, J. and Wells, B. (1988), “Experimental and statistical analyses of surface mount technology PLCC solder joint reliability”, IEEE Transactions on Reliability, Vol. 37 No. 5, pp. 524-30. Lau, J., Dauksher, W., Smetana, J., Horsley, R., Shangguan, D., Castello, T., Menis, I., Love, D. and Sullivan, B. (2004a), “Design for lead-free solder joints reliability of high-density packages”, Soldering and Surface Mount Technology, Vol. 16 No. 1, pp. 12-26. Lau, J., Shangguan, D., Castello, T., Horsley, R., Smetana, J., Dauksher, W., Love, D., Menis, I. and Sullivan, B. (2004b), “Failure analysis of lead-free solder joints for high-density packages”, Soldering and Surface Mount Technology, Vol. 16 No. 2. Lee, N.C. (2002), Reflow Soldering Processed and Troubleshooting for SMT, BGA, CSP, and Flip Chip Technologies, Newnes, Boston, MA. Smetana, J., Horsley, R., Lau, J.H., Snowdon, K., Shangguan, D., Gleason, J., Memis, I., Love, D., Dauksher, W. and Sullivan, B. (2004), “Design, materials and process for lead-free assembly of high density packages”, Soldering and Surface Mount Technology, Vol. 16 No. 1, pp. 53-62. Wassink, R. (1989), Soldering in Electronics, Electrochemical Publications, Ayr, Scotland. Weibull, W. (1951), “A statistical distribution function of wide applicability”, ASME Transactions, Journal of Applied Mechanics, Vol. 18, pp. 293-7. Weibull, W. (1961), Fatigue Testing and Analysis of Results, MacMillan Company, New York, NY.

Failure analysis of lead-free solder joints for high-density packages

Keywords Solders, Product reliability, Joining processes, Printed-circuit boards

John Lau Agilent, Santa Clara, California, USA Dongkai Shangguan Flextronics, San Jose, California, USA Todd Castello Flextronics, Youngsville, North Carolina, USA Rob Horsley Celestica, Kidsgrove, Staffordshire, UK Joe Smetana Alcatel, Plano, Texas, USA Nick Hoo Tin Technology, Middlesex, UK Walter Dauksher Agilent, Fort Collins, Colorado, USA Dave Love Sun Microsystems, Menlo Park, California, USA Irv Menis IBM, Endicott, New York, USA Bob Sullivan HDPUG, Scottsdale, Arizona, USA

Abstract Failure analyses of the lead-free and SnPb solder joints of high-density packages such as the plastic ball grid array and the ceramic column grid array soldered on SnCu hot-air solder levelling electroless nickelimmersion gold or NiAu, and organic solderability preservative Entek printed circuit boards are presented. Emphasis is placed on determining the failure locations, failure modes, and intermetallic compound composition for these high-density packages’ solder joints after they have been through 7,500 cycles of temperature cycling. The present results will be compared with those obtained from temperature cycling and finite element analysis.



Introduction The reliability engineering of lead-free solder joints consists of three major tasks, namely, design for reliability (DFR), reliability testing and data analysis, and failure analysis. The cycle starts off with a design for the solder joints and demonstrates that the design is reliable by the principles of engineering physics (Lau et al., 2004a). Then, the “reliable” design is built and tested (Lau et al., 2004b; Smetana et al., 2003). The test data are then fitted into a life distribution. Failure analysis should then be done on the failed samples. This last task is as important as the first two, and it provides the following: 1 the failure locations, 2 the failure modes, and 3 the failure mechanisms. This information is very useful for the following: 1 verifying the reliability test data, 2 verifying the DFR analysis results, 3 understanding why it failed and how to fix it (or do better) for the next round of DFR and reliability testing, and 4 choosing acceleration models to determine the acceleration factors. In this investigation, the focus is on locating the failures and establishing the failure modes, and the objective is to verify the thermal cycling test data reported in Lau et al. (2004b) and the finite element analysis results reported in Lau et al. (2004a). The failure mechanisms such as: 1 Kirkdendall void formation (Deepak et al., 2002; Jeon et al., 2001; Lau et al., 2004a, b), which is the result of an inter-diffusion process, e.g. between the Ni-P+ layer and the NiSn in the solder joints on the NiAu PCB, 2 the intrinsic stress (Blair et al., 1998; Chan et al., 2001; Sabine et al., 1999), which is built up due to the The Emerald Research Register for this journal is available at www.emeraldinsight.com/researchregister

3

volumetric shrinkage as a result of phase transformation and intermetallic compound IMC formation in the solder joints, and the IMC growth, are out of the scope of the present study and will be published elsewhere.

Sample preparation In this study, failure analyses are reported for some of the components from the temperature cycling tests reported by Smetana et al. (2003). The components are as follows: 1 208PBGA (plastic ball grid array), 2 256PBGA, 3 388PBGA, and 4 1657CCGA (ceramic column grid array). For more information about these packages and their PCB assembly, reliability testing and data analysis, and mathematical modelling, please refer to Lau et al. (2004a, b) and Smetana et al. (2003).

Sample singulation Individual components are couponed from the PCB using a small tabletop laboratory grade diamond band saw. The PCBs are carefully hand-fed into the diamond-impregnated blade as in most cases components are quite close to one another. Water is used as a cutting lubricant. The cut edges are then smoothed using a 320-grit silicon carbide grinding paper. The sample coupons are then cleaned with tap water and blown dry with compressed air.

Flux removal Any residual solder flux on the component is removed using room temperature Dynasolve Deflux with agitation. This process is slow and can take several hours. The samples are checked every half-an-hour using light microscopy. When The current issue and full text archive of this journal is available at www.emeraldinsight.com/0954-0911.htm

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John Lau, Dongkai Shangguan, Todd Castello, Rob Horsley, Joe Smetana, Nick Hoo, Walter Dauksher, Dave Love, Irv Menis and Bob Sullivan Failure analysis of lead-free solder joints for high-density packages Soldering & Surface Mount Technology 16/2 [2004] 69–76

the flux residues have been sufficiently removed, the samples are rinsed in isopropyl alcohol and blown dry with compressed air.

Dye and pry Samples for dye impregnation utilize the following process. 1 Remove flux. 2 Immerse sample in Dykem red steel layout fluid. 3 Subject to vacuum (25 in mercury for 10 min). 4 Remove from vacuum and allow to soak in fluid for at least 30 min. 5 Remove from fluid and bake sample for 30 min at 1008C. 6 Remove samples from oven and allow to cool to room temperature. For pry analysis, a large Exacto knife blade is carefully inserted slightly under the package at one corner. The knife is then rotated increasing the tensile loading on the component until it is popped off from the PCB. Great effort is necessary to insure that the knife blade does not damage any of the solder joints prior to inspection. The separated package and PCB can then be inspected for evidence of dye penetration, which is an indicator of where fractures are present in the solder joints. The crescent shaped damage is generally located near the chip edges and at the outer edges of the PBGA solder joints. For additional studies of the microstructure of the fracture surfaces, the dye can be removed with acetone and the fracture surfaces can be documented with scanning electron microscopy (SEM).

Cross sectioning Prior to sectioning, the samples should have already been couponed and defluxed as described above. The encapsulation and sectioning methods are consistent with standard metallographic sample preparation techniques; the specific steps are given below. All of the samples are inspected and documented as polished. None of the samples are etched prior to inspection.

Encapsulation 1 2 3 4 5 6 7

Place samples into clips to maintain proper orientation. Apply mould release to sample cups, mark sample cups with proper sample ID. Place samples into the centre of sample cups. Mix the epoxy and the hardener in accordance with manufacturer’s recommendations and mix thoroughly. Fill sample cups to two-third full. Place uncured moulds into vacuum chamber and degas epoxy. Place degassed moulds into a tray of water to minimize the temperature rise due to the epoxy exotherm.

Rough polish (Wheel speed at 500 rpm) 1 2 3 4 5

Using a “Texmet” cloth, rough polish with 6 mm diamond paste and diamond extender fluid. Wash sample with abrasive free soap and water. Using a texmet cloth, rough polish with 3 mm diamond paste and diamond extender fluid. Using a texmet cloth, rough polish with 1 mm diamond paste and diamond extender fluid. Note that this step is only needed for the ceramic packages. Wash sample with abrasive free soap and water.

Final polish 1 2 3 4

Using a chemomet cloth, polish with 0.05 mm alumina slurry. Rinse sample on the polishing cloth with water. Using a chemomet cloth, polish with 0.06 mm colloidal silica. Rinse sample on the polishing cloth with water.

Blow sample dry with compressed air, being careful not to create water marks, or other stains on the polished section.

Optical microscopy Inspection and photo-documentation are performed on a stereo-microscope for the dye and pry analysis and on a compound microscope for the cross-sectional analysis.

Scanning electron microscopy Samples are sputter coated with a thin layer of gold to facilitate the SEM inspection. Most of the solder joint images from the SEM are obtained using a backscatter electron detector as this imaging mode gives an mostly atomic number-based contrast mechanism.

Cross-sectioning of untested 256PBGA assemblies Figure 1 shows a cross-section of a Sn-4Ag-0.6Cu solder balled 256PBGA with the Sn-3.8Ag-0.7Cu solder paste on an OSP PCB. This assembly is cross-sectioned after reflow, without being temperature cycled. It can be seen that the solder joint is nicely formed. Figure 2 shows a cross-section of a SnPb balled 256PBGA with the Sn-3.8Ag-0.7Cu solder paste on an OSP PCB. It can be seen that the IMC near the PCB and solder joint interface after reflow is about 5.7 mm thick. Figure 3(a) shows SEMs of a Sn-4Ag-0.6Cu solder balled 256PBGA assembled with the Sn-3.8Ag-0.7Cu solder paste on an OSP PCB. It can be seen that the IMC thickness is about 5.85 mm. Figure 3(b) shows that Sn-Ag3 intermetallic plates and SnCuNi intermetallic needles are present in the lead-free solder joint.

Grinding (Wheel speed at 500 rpm) 1 2 3 4 5 6 7 8

Remove samples from cups serially and transfer sample ID to the cured mould. Bevel top and bottom edges of mould using 240grit SiC grinding paper. Rough grind samples using 240grit SiC until the section plane is within 4 , 6 mil of target solder joints. Continue grinding with 320grit SiC until the section plane is within 1 , 3 mil of the target solder joints. Continue grinding with 400grit SiC until the section plane is roughly 1/3 into the target solder joints. Continue grinding with 600grit SiC until the desired section plane (centre of the solder joint) has been reached. Freshen bevel with 600grit on the sample side of the mould. Wash sample with abrasive free soap and water.

Note that for ceramic samples (CCGA packages), grinding steps (3) through (5) are replaced with 75 and 15 mm metal bonded diamond grinding disks.

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Figure 1 Cross section of an untested lead-free solder joint from a 256PBGA package


Figure 2 Cross section of an untested SnPb solder balled 256PBGA with Sn3.8Ag-0.7Cu paste on an OSP PCB

temperature cycles. This is a SnAgCu solder balled PBGA assembled with SnPb paste on an OSP PCB. It can be seen in the close up pictures that all except one of the solder balls remained attached to the PBGA package. It can also be seen from the dye and pry test that there were no solder joints with fractures, except for one solder joint which shows less than 5 per cent of the solder joint area with dye penetration, near to the interface between the solder and the package substrate. This compares very well with the temperature cycling test reported in (Smetana et al., 2003) where there were no solder joint failures for this type of assembly.

Tin-lead solder balls

Figure 3 Crosssections of an untested 256PBGA lead-free solder joint on a NiAu PCB

Figure 5 shows the dye and pry separations for a PCB and package that had reached 7,500 temperature cycles, respectively. This assembly was made using a SnPb solder balled PBGA with SnPb solder paste on an OSP PCB. It can be seen that most (except a few) of the solder balls have remained attached to the package. Also, the close-up dye and pry pictures show some partially and completely fractured solder joints near the corners of the inner and outer arrays. This is because of the following. 1 The local thermal expansion mismatch between the silicon chip, the BT (bismaleimide triazene) substrate, and the moulding compound. 2 The global thermal expansion mismatch between the whole package and the PCB. This compares very well with the finite element analysis results reported by Lau et al. (2004a). Based on the temperature cycling test results reported in (Lau et al., 2004b), the first solder joint failure for this package was at 5,627 cycles. It should be noted that, in this study, all the samples are temperature cycled up to 7,500 cycles. Also, only the number of temperature cycles to the first solder joint failure in a package is recorded. Thus, if there is more than one failure for a package, there is no way to identify which one occurred first.

Failure analysis of the 208PBGA assemblies Tin-lead solder balls Failure analysis of the SnPb solder balled 208PBGAs assembled with SnPb solder paste on to an OSP PCB, and which first failed at 6,739 cycles is now presented. First of all, the cross sections of the assembly show no significant package warpage and no apparent fractures in the external rows of solder joints. Figure 6 shows a solder joint with a large void. It can be seen that there is a crack on the right-hand side of the void. This crack has initiated from the right-hand corner, propagated at 458 down to the void, and then stopped. Also, there is grain coarsening (but no crack as yet) at the left-hand side of the solder joint along a 458 direction. Figure 7 shows s cross-section of a failed solder joint with a small void. It can be seen from the close up in Figure 7(b), that: 1 there is significant grain coarsening at 458 on both sides of the void, 2 there is crack along the coarsening band, 3 the crack has initiated at both the upper corners of the solder joint, and 4 the cracks have propagated, along the boundary of the Sn and Pb phases, toward the void, and, then linked within the solder joint to form a through crack.

Tin-silver-copper solder balls

Dye and pry analysis of the 208PBGA assemblies Tin-silver-copper solder balls Figure 4 shows the separations after dye and pry for a PCB and a PBGA package that had experienced 7,500

Failure analysis of the SnPb solder balled 208PBGAs assembled with Sn-3.8Ag-0.7Cu solder paste on NiAu PCBs, which first failed at 7,513 cycles, is now presented. First of all, the cross sections show that there are no obvious fractures in the external rows of the solder joints. However, significant warpage of the package (due to the higher leadfree reflow temperature) has caused the formation of elongated solder joints. Though this may not be bad,

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Figure 4 Lead-free solder balled 208PBGA assembled with SnPb paste on an OSP PCB

Figure 5 SnPb solder balled 208PBGA assembled with SnPb paste on an OSP PCB

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Figure 6 An SnPb 208PBGA solder joint with a large void

Figure 7 Cross section of a failed SnPb 208PBGA solder joint with a small void

since the standoff height of the solder joints is now taller and thus the solder-joint thermal-fatigue reliability should be better. Figure 8 shows a cross-section of a solder joint for the package which first failed at 7,513 cycles. It can be seen that there is an interesting coarsening band that runs diagonally across the solder joint. However, there is no crack initiated as yet. Figure 9 shows a cross section of a failed solder joint from the same package. It can be seen that:

Figure 8 Grain coarsening in an unfailed SnPb Solder balled 208PBGA assembled with SnAgCu solder paste on a NiAu PCB

Figure 9 Failed SnPb Solder balled 208PBGA assembled with SnAgCu solder paste on a NiAu PCB

1 2 3

the crack initiated from the upper right-hand corner of the solder joint (Figure 9(b)), the crack propagated diagonally across the solder joint until it fractured, and the crack propagation was along the boundary of the Sn and Pb phases.

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Figure 10 shows a cross-section of a solder joint from the package which first failed at 7,513 cycles. It can be seen that: 1 the crack initiated from the upper left-hand corner of the solder joint, 2 the crack then propagated along the interface between the package substrate and the solder joint, 3 the crack has propagated about half way through the solder joint, 4 there is a tiny crack initiated at the upper right-hand corner of the solder joint, and 5 the joint is not completely fractured yet.

Figure 11 Cross section of an SnPb solder balled 388PBGA assembled with SnAgCu solder paste on an OSP PCB

Failure analysis of 388PBGA assemblies Figure 11 shows the solder joints near the corner and middle of an outer row of a SnPb solder balled 388PBGA assembled with Sn-3.8Ag-0.7Cu solder paste onto an OSP PCB. It can be seen that due to the higher lead-free reflow temperatures, the package is warped severely, leading to the anomalousshape solder joints near the corner and fatter than the normal shape solder joints near the middle. The failure locations of the solder joints of this package are near to the corners of the outer, inner, and the thermal ball arrays. This is due to the global thermal expansion mismatch between the package (silicon chip, moulding compound, and BT substrate) and the PCB, and the local thermal expansion mismatch between the silicon chip, the BT substrate, and the moulding compound.

Figure 10 Cross section of an unfailed SnPb Solder balled 208PBGA assembled with SnAgCu solder paste on a NiAu PCB

For this package, the first solder joint failed at 7,190 cycles. It failed at the corner of the outer row of the package. Figure 12 shows cross sections of this solder joint. It can be seen that; 1 the crack occurred near the interface between the package substrate and the solder joint, 2 the crack may have initiated from both corners of the solder joint, and 3 the cracks are linked at the small void, resulting in a complete fracture of the solder joint.

Failure analysis of 1657CCGA assemblies The failed 1657CCGA assemblies on NiAu PCBs (which first failed at 6,167 cycles), OSP PCBs (first failed at 6,284 cycles), and SnCu HASL PCBs (which first failed at 6,590 cycles) are analysed and the results are shown in Figure 13. All of these were assembled with the Sn-3.8Ag0.6Cu solder paste and were tested up to 7,500 cycles. It can be seen that the Pb from the Sn-90Pb solder columns is dissolved into the Sn-Ag-Cu solder during reflow, even though the maximum reflow temperature is below the melting temperature of the Sn-90Pb alloy (3028C), i.e. this is by dissolution, not by melting. The Pb dendrites can be seen throughout the solder fillet connecting the column to the PCB. A close examination has revealed that all of the damage is at the following. 1 At the Sn-90Pb solder column near the “vertex” of the substrate solder fillet and the PCB solder fillet as shown in Figure 13.

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Figure 12 Failed SnPb solder balled 388PBGA assembled with SnAgCu solder paste on an OSP PCB

1

2

The local bending fatigue of the solder columns whose driving (shear) force is due to the global thermal expansion mismatch between the ceramic substrate and the FR-4 PCB. The corner solder columns being subjected to the largest thermal expansion mismatch between the ceramic substrate and the FR-4 PCB.

These compare very well with the finite element analysis results as reported in (Lau et al., 2004a).

Summary

2 3

Worse at the corners than in the middle of the packages. There are more failures near the vertex of the substrate solder fillets.

These could be due to the following.

Failures in the lead-free and SnPb solder joints of 208PBGA, 256PBGA, 388PBGA, and 1657CCGA packages on PCBs with three different finishes have been analysed by cross sectioning, dye and pry, and SEM methods. Some important results are summarised in the following. . For both the lead-free and SnPb balled 208PBGAs assembled with lead-free or SnPb solder paste, the failure locations are near the corners of the outer and inner arrays. This is due to the global thermal expansion mismatch between the package (silicon chip, moulding compound, and BT substrate) and the PCB, and the local thermal expansion mismatch between the silicon chip, the BT substrate, and the moulding compound. . For both the lead-free and SnPb balled 388PBGAs assembled with lead-free or SnPb solder paste, the failure locations are near the corners of the outer, inner, and the thermal ball arrays. The reason for this is the same as for the 208PBGAs. . For both the lead-free and SnPb PBGA solder joints on the SnCu HASL, NiAu, and OSP finished PCBs, the failure location inside the solder joints was “far away” from the IMC layer near the PCBs. . For both the lead-free and SnPb PBGA solder joints on the SnCu HASL, NiAu, and OSP finished PCBs, most of the failure locations inside the solder joints were near to the interface between the package substrate and the solder joint. The failure mode is crack initiation at the interface and crack propagation inward. Usually, two cracks were initiated, independently, from both (hot and cold) thermal expansion mismatch directions near the upper corner of the solder joint and then they propagate until they met, forming a complete fracture across the solder joint. . Occasionally, however, the failure was formed when cracks initiated from both (hot and cold) thermal expansion mismatch directions, near the upper corner of the solder joint, and then propagated at 458 downwards until they met. . Another interesting failure is where only one crack initiated from the upper corner of the solder joint and then propagated along the diagonal of the solder joint. . Due to the higher reflow temperature for the lead-free solder, the PBGA packages warped severely, which led to anomalous shaped solder joints. . Sn-Ag plates and SnCuNi needles are observed in the lead-free PBGA solder joints on the NiAu PCB. . For all of the 1657CCGA assemblies, the Pb from the Sn-90Pb solder columns dissolved into the Sn-Ag-Cu solder during reflow, even though the reflow temperature was below the melting temperature of the Sn-90Pb alloy. . For all of the 1657CCGA assemblies, failure location was at the corners and the outer rows of the packages. . For all of the 1657CCGA assemblies, all the failure locations are at the Sn-90Pb solder column near the “vertex” of the substrate solder fillet and the PCB solder fillet, with more damage near the substrate side. The failure mode is bending fatigue of the high-lead solder columns for which the driving force is mainly the thermal expansion mismatch between the ceramic carrier and the PCB.

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The authors of this paper would like to acknowledge and thank many unnamed contributors from the various companies who made this test program possible. These include, but are probably not limited to, contributions from unnamed people at, or formerly employed at, Agilent, Alcatel, Amkor, Celestica, ChipPac, Fairchild Semiconductor, Flextronics, HDPUG, Hewlett Packard Co., IBM, International Tin Research Institute, Lucent, National Semiconductor, Nokia, Nortel Networks, RF Monolithics, ST Microelectronics, Sun Microsystems, Texas Instruments, and Thomas and Betts. Special thanks go to Steady Frater, Tom Dyson, and Alan Tan of the Celestica Ashton facility, for their help in making the assembly possible, and to Ruben Bergman of HDPUG, and Ted Lancaster and Pete Woodhouse of Agilent for their strong support to this project.

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Figure 13 Cracks in the high-lead solder columns near the outer rows of the 1657CCGA package

.

The failure locations and failure modes of the solder joints of the PBGA and CCGA packages compare very well with the temperature cycling test and the finite element analysis results.

References Blair, H., Pan, T. and Nicholson, J. (1998), “Intermetallic compound growth on Ni, Au/Ni, and Pd/Ni substrates with SnPb, SnAg, and Sn solders”, Proceedings of the 48th IEEE Electronic Components and Technology Conference, Seattle, pp. 259-67. Chan, Y., Yu, P., Tang, C., Hung, K. and Lai, J. (2001), “Reliability studies of m BGA solder joints – effects of NiSn intermetallic compound”, IEEE Transactions on Advanced Packaging, Vol. 24, pp. 25-31. Deepak, G., Lane, T., Kinzie, P., Panichas, C., Chong, K. and Villalobos, O. (2002), “Failure mechanism of brittle solder joint fracture in the presence of electroless nickel immersion gold (ENIG) interface”, Proceedings of the 52nd IEEE Electronic Components and Technology Conference, San Diego, CA, pp. 732-9. Jeon, Y., Paik, K., Bok, K., Choi, W. and Cho, C. (2001), “Studies on NiAu intermetallic compound and P-rich Ni layer at the electroless Ni UBM – solder interface and their effects on flip chip solder joint reliability”, Proceedings of the 51st IEEE Electronic Components and Technology Conference, Orlando, FL, pp. 69-75.

Lau, J., Dauksher, W., Smetana, J., Horsley, R., Shangguan, D., Castello, T., Menis, I., Love, D. and Sullivan, B. (2004a), “Design for lead-free solder joints reliability of high-density packages”, Soldering and Surface Mount Technology, Vol. 16 No. 1, pp. 12-26. Lau, J., Hoo, N., Horsley, R., Smetana, J., Shangguan, D., Dauksher, W., Love, D., Menis, I. and Sullivan, B. (2004b), “Reliability test and data analysis of high-density packages’ lead-free solder joints”, Soldering and Surface Mount Technology, Vol. 16 No. 2. Sabine, A., Andreas, O., Hermann, O., Rolf, A. and Herbert, R. (1999), “Reliability of electroless nickel for high temperature application”, Proceedings of the International Symposium on Advanced Packaging Materials, Atlanta, GA, pp. 256-61. Smetana, J., Horsley, R., Lau, J., Snowdon, K., Shangguan, D., Gleason, J., Memis, I., Love, D., Dauksher, W. and Sullivan, B. (2003), “Design materials and process for lead-free assembly of high density packages”, Soldering and Surface Mount Technology, Vol. 16 No. 1, pp. 53-62.

Further reading Lau, J.H., Wong, C.P., Lee, N.C. and Lee, S.W.R. (2003), Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials, McGraw-Hill, New York, NY.

Thermal cycling reliability of lead-free chip resistor solder joints

Keywords Soldering, Joining processes, Product reliability

Abstract The solder joint reliability of ceramic chip resistors assembled to laminate substrates has been a long time concern for systems exposed to harsh environments. In this work, the thermal cycling reliability of several 2512 chip resistor lead-free solder joint configurations has been investigated. In an initial study, a comparison has been made between the solder joint reliabilities obtained with components fabricated with both tin-lead and pure tin solder terminations. In the main portion of the reliability testing, two temperature ranges (2 40-1258C and 2 40-1508C) and five different solder alloys have been examined. The investigated solders include the normal eutectic Sn-Ag-Cu (SAC) alloy recommended by earlier studies (95.5Sn-3.8Ag0.7Cu), and three variations of the lead-free ternary SAC alloy that include small quaternary additions of bismuth and indium to enhance fatigue resistance.

Received: 30 January 2004 Revised: 17 February 2004


Jeffrey C. Suhling Center for Advanced Vehicle Electronics (CAVE), Auburn University, Alabania, USA H.S. Gale Center for Advanced Vehicle Electronics (CAVE), Auburn University, Alabania, USA R. Wayne Johnson Center for Advanced Vehicle Electronics (CAVE), Auburn University, Alabania, USA M. Nokibul Islam Center for Advanced Vehicle Electronics (CAVE), Auburn University, Alabania, USA Tushar Shete Center for Advanced Vehicle Electronics (CAVE), Auburn University, Alabania, USA Pradeep Lall Center for Advanced Vehicle Electronics (CAVE), Auburn University, Alabania, USA Michael J. Bozack Center for Advanced Vehicle Electronics (CAVE), Auburn University, Alabania, USA John L. Evans Center for Advanced Vehicle Electronics (CAVE), Auburn University, Alabania, USA Ping Seto DaimlerChrysler-Huntsville Electronics, Huntsville, Alabania, USA Tarun Gupta DaimlerChrysler-Huntsville Electronics, Huntsville, Alabania, USA James R. Thompson DaimlerChrysler-Huntsville Electronics, Huntsville, Alabania, USA

Legislation that mandates the banning of lead in electronics, due to environmental and health concerns, has been actively pursued in several countries during the past 15 years. Although the products covered by and implementation deadlines for such legislation continue to evolve, it is clear that laws requiring conversion to lead-free electronics are becoming a reality. Other factors that are affecting the push towards the elimination of lead in electronics are the market differentiation and advantage being realized by companies producing the so-called “green” products that are lead-free. A large number of research studies have been performed and are currently underway in the lead-free solder area. Detailed reports on multi-year studies have been published by the National Center for Manufacturing Sciences (NCMS) and the National Electronics Manufacturing Initiative (NEMI), as well as other consortia. Although no “drop in”

replacement has been identified for all applications; Sn-Ag, Sn-Ag-Cu (SAC), and other alloys involving elements such as Sn, Ag, Cu, Bi, In, and Zn have been identified as promising replacements for standard 63Sn-37Pb eutectic solder. There have been many reports that solder joint reliability can actually be increased for a given application by using a lead-free replacement alloy such as SAC instead of conventional Sn-Pb. However, this conclusion is not universal, and the degree of reliability improvement/ degradation is package/design and environment dependent. In thermal cycling reliability environments, SAC alloys appear to often outperform Sn-Pb. This has been found for solder joints in more compliant package-board assemblies such as leaded components (e.g. QFPs) and plastic ball grid array (PBGA) applications (Lau et al., 2004), and also for more stiff components (CBGA) subjected to small temperature changes (Farooq et al., 2003). However, for



Introduction

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Jeffrey C. Suhling, H.S. Gale, R. Wayne Johnson, M. Nokibul Islam, Tushar Shete, Pradeep Lall, Michael J. Bozack, John L. Evans, Ping Seto, Tarun Gupta and James R. ThompsonJeffrey C. Suhling, H.S. Gale, R. Wayne Johnson, M. Nokibul Islam, Tushar Shete, Pradeep Lall, Michael J. Bozack, John L. Evans, Ping Seto, Tarun Gupta and James R. Thompson Thermal cycling reliability of lead-free chip resistor solder joints Soldering & Surface Mount Technology 16/2 [2004] 77–87

very stiff components with a high coefficient of thermal expansion (CTE) mismatch with the substrate (e.g. CBGA on FR-4, and non-underfilled flip chip on laminate), the solder joint reliability is typically poorer for lead-free SAC alloys in thermal cycling tests with large swings between the temperature extremes (Schubert et al., 2002, 2003). Another common surface mount technology (SMT) configuration involving stiff components with high CTE mismatch to the substrate is the use of ceramic (alumina) bodied chip resistors on organic substrates (e.g. glass-epoxy laminates). The solder joint reliability of such components has been a long time concern for harsh environments with extreme temperature excursions, such as those found in automotive and aerospace applications. These reliability challenges are further exacerbated for components with larger physical size (distance to neutral point) such as the 2512 resistors used in situations where higher voltages and/or currents lead to power dissipations up to 1 W. Crack growth and the resulting shear strength degradation for both SAC and Sn-Pb-Ag chip resistor solder joints have been examined during thermal cycling (Stam and Davitt, 2001). It was found that the fatigue resistances between lead bearing and SAC solder joints were not significantly different, but were influenced by the component type and board metallisation. In addition, crack length variation has been measured in chip capacitor solder joints as a function of thermal cycling (Grossmann et al., 2002). Cracks were found to grow fast in the Sn-Pb-Ag solder joints relative to several lead-free alternatives. Finally, the changes in microstructure occurring in SAC chip resistor solder joints during thermal cycling have been recently examined (Sayama et al., 2003). A power law relationship was established between the number of cycles to crack initiation and the average b-Sn phase growth parameter. In this work, the thermal cycling reliability of several 2512 chip resistor lead-free solder joint configurations has been investigated. In an initial study, a comparison was made between the solder joint reliabilities obtained with components fabricated with both tin-lead and pure tin solder terminations. In the main portion of the reliability testing, two temperature ranges (240-1258C and 240-1508C) and five different solder alloys have been examined. The investigated solders include the normal eutectic SAC alloy recommended by earlier studies (95.5Sn-3.8Ag-0.7Cu), and three variations of the lead-free ternary SAC alloy that include small quaternary additions of bismuth and indium to enhance fatigue resistance. For each configuration, thermal cycling failure data has been gathered and analysed using two-parameter Weibull models to rank the relative material performances. The obtained lead-free results have been compared to the data for standard 63Sn-37Pb joints. In addition, a second set of thermally cycled samples was used for microscopy studies to examine crack propagation, changes in the microstructure of the solders, and intermetallic growth at the solder to PCB pad interfaces.

Test board A test board was developed for examining the thermal cycling reliability of five sizes of chip resistors (2512, 1206, 0805, 0603, 0402). The industry standard naming convention for these chip resistor sizes describes the length and width of the resistor body in hundredths of an inch. For example, the 2512 resistor has a nominal length of 0.25 in (6.35 mm), and a nominal width of 0.12 in (3.05 mm). Each board contained 15 of each of the five sizes of chip resistors. The 15 resistors in each size were accessible electrically as three daisy-chain sets (five resistors and thus, ten solder joints per chain). The resistor daisy chains were routed to plated through holes at the edge of the board where soldered wire connections could be made for use in resistance monitoring during the thermal cycling tests. Figure 1 is a photograph of an assembled test board. The fabricated test

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boards included four copper conductor layers, FR-406 glass/ epoxy laminate material and had a thickness of 1.57 mm. The external copper traces had either a hot air solder levelled (HASL) Sn-Pb or an electroless nickel immersion gold (ENIG) finish. Figure 2 shows a top view of one of the 2512 resistors and a typical uncycled solder joint cross-section.

Reliability testing Thermal cycling (240-1258C and 240-1508C) of the assembled test boards was performed in a pair of Blue-M environmental chambers, and 6,000 cycles were completed for each temperature range before the testing was terminated. The thermal cycle duration was 90 min, with 20 min at each extreme. Typical thermocouple results from under a component on one of the test boards are shown in Figure 3. Enough boards were assembled so that each of the various legs of the test matrix had 12 test boards (36 resistor chains for each component size). The boards were placed vertically in the chamber, and the wiring passed through access ports to a data acquisition system. Monitoring of the various daisy chain networks was performed throughout the cycling using a high accuracy digital multimeter coupled with a high performance switching system controlled by LabView software. Failure of a daisy-chain network was defined as the point when the resistance change exceeded 5 V.

Reliability data In this paper, only results for the 2512 resistor solder joint reliability will be discussed. Of all the tested chip components, the 2512 resistors have the largest body size and highest rated power dissipation, and consequently, the poorest solder joint reliability. For those components with sufficient failures after 6,000 cycles, the resulting failure data were statistically analysed using two parameter Weibull models. The standard parameters in such an approach are the Weibull slope b, and the characteristic life h, which is the number of cycles required to cause failure of 63.2 percent of the samples from a particular leg of the test matrix. From these values for a particular chip resistor configuration, the cumulative failures (percent) after any number of thermal cycles can be predicted.

Resistor termination study Prior to studying the reliability differences between the various solder types, an initial investigation was performed to examine the effects of using different termination materials for the chip resistors. Historically, chip resistors have been fabricated with 90Sn-10Pb solder terminations to better match the Sn-Pb solder paste used in conventional SMT assembly and to avoid fillet lifting. However, a transition to pure Sn terminations has occurred as a part of the overall lead-free initiative. In the resistor termination study performed here, 2512 resistors from two vendors, with both Sn-Pb and Sn terminations were considered. The boards were fabricated with a Sn-Pb HASL finish, and eutectic 63Sn-37Pb solder paste was utilized. Thus, the only lead-free attributes of these particular experiments were the Sn-terminations in some of the chip resistors. The Weibull failure plot for the Sn and Sn-Pb terminated chip components is shown in Figure 4. From these data, it can be seen that there was little difference in the failure data for the two termination types for a given resistor vendor, although the parts from vendor 2 consistently outperformed those from vendor 1. The nature of these reliability differences for the parts from the two vendors has yet to be explained. In all future discussions in this paper, resistors from vendor 2 with pure Sn termination were utilized.


Figure 1 Chip resistor test board

Figure 2 2512 resistor top view and solder joint

Figure 3 Test board thermal cycle (2 40-1258C)

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Figure 4 Weibull plot for resistor termination study

Lead-free alloy study The compositions of the five alloys (four lead-free and standard 63Sn-37Pb) tested in this investigation are tabulated in Table I. The lead-free solders consisted of the standard SAC eutectic (95.5Sn-3.8Ag-0.7Cu) that is often recommended as a leading candidate for the replacement of Sn-Pb, and a set of three quaternary Sn-Ag-Cu-X alloys, with either Bi or In as the fourth ingredient. The test boards utilized in this part of the investigation were fabricated with an ENIG finish. Typical thermal cycling reliability data for the 2512 resistor solder joints are shown in Figures 5-7. In Figures 5 and 6, the reliabilities of 63Sn-37Pb and Table I Solder alloy compositions Alloy

Composition

Sn-Pb SAC Sn-Ag-Cu-Bi (1) Sn-Ag-Cu-Bi (2) Sn-Ag-Cu-In

63Sn-37Pb 95.5Sn-3.8Ag-0.7Cu 92.35Sn-3.35Ag-1.0Cu-3.3Bi 93.5Sn-3.8Ag-0.7Cu-2.0Bi 88.5Sn-3.0Ag-0.5Cu-8.0In

95.5Sn-3.8Ag-0.7Cu solder joints are compared for the 240-1258C and 240-1508C temperature ranges, respectively. It can be seen from Figure 5 that the reliabilities are very similar to the 240-1258C thermal cycling range. However, Figure 6 indicates that 63Sn-37Pb dramatically outperforms the lead-free SAC alloy for the more extreme 240-1508C testing. This result agrees with the earlier observations for non-underfilled flip chip on laminate assemblies (Schubert et al., 2002, 2003), and further underscores the need to be cautious when proposing lead-free solder substitutions for SMT configurations including stiff components on organic laminate substrates where there are harsh environments with large temperature swings (e.g. automotive under-the-hood applications). In the case of cycling from 240 to 1258C, the reliabilities of the three quaternary Sn-Ag-Cu-X alloys were found to be same or slightly lower than that of eutectic 95.5Sn-3.8Ag0.7Cu. However, as shown in Figure 7, the addition of either Bi or In to SAC can significantly enhance the reliability of the lead-free joints when exposed to the harsher temperature range 240-1508C, where SAC performs poorer than standard Sn-Pb. Further investigation is required to determine the Sn-Ag-Cu-X lead-free alloy formulation that best optimises reliability in harsh environments.

Figure 5 Weibull plot for 2512 chip resistors with Sn-Pb and SAC solders (2 40-1258C)

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Figure 6 Weibull plot for 2512 chip resistors with Sn-Pb and SAC solders (2 40-1508C)

Figure 7 Weibull plot for 2512 chip resistors with lead-free solders (2 40-1508C)

Microscopy and failure analysis Experimental techniques Metallographic samples were prepared from cross-sections of a set of supplemental boards subjected to various levels of thermal cycling. The cross-sections were characterized by scanning electron microscopy (SEM) using a JEOL JSM 840 instrument operated at an accelerating voltage of 20 kV. All samples were imaged as polished. The intermetallic phases observed in these joints were noticeably harder than the matrix. Thus, it was possible to obtain topographic contrast in secondary electron images (SEIs) of the polished samples without resort to etching. Backscattered electron images (BEIs) were also used to produce atomic number contrast (phases with a high average atomic number appear bright). Compositional data were obtained using energy dispersive X-ray spectroscopy (EDS) via an Oxford ultrathin window (UTW) detector and ISIS analyser attached to the JSM 840.

Figure 8 Photograph of an uncycled 95.5Sn-3.8Ag-0.7Cu solder joint with images and locations of crack initiation, corner turning, and completion selected from various cycled samples

Crack propagation Preliminary failure analysis has shown that the solder joint cracking and creep-fatigue damage propagates as expected for chip resistors on FR-4 substrates. As shown in Figures 8 and 9, cracks begin underneath the component and then

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Figure 9 Observed cracks in 95.5Sn-3.8Ag-0.7Cu joints after various number of thermal cycles (2 40-1508C)

typically follow along a path that parallels the resistor termination, turning the corner at the resistor edge, and then proceeding until complete separation has occurred. Unfortunately, insufficient cross-sections were made to fully characterize the crack growth for the various solders. In particular, the Weibull plots in Figures 5-7 indicate that many more cross-sections with environmental exposures between 500 and 3,000 cycles would be necessary to develop a crack propagation criterion for the 2512 resistor solder joints. Another finding was that more study is needed to optimise the assembly process and reflow profile for each lead-free solder type so that voids (Figure 10) are minimized in the solder joints.

Solder fillet microstructures Secondary electron images for solder joints of the four leadfree alloy systems that were cross-sectioned after various levels of thermal cycling from 240 to 1508C are shown in Figures 11-14. In all cases, the magnified images were taken at the interface of the solder and PCB pad with ENIG plating finish, in the bulk of the joint but near the corner of the resistor termination. For all of the lead-free systems, a noticeable feature was that spheroidizing of the eutectic was observed to progress rapidly during cycling. Such spheroidization is driven by the energy of the interfaces between the phases making up the eutectic, since spheroidization reduces the total interfacial area and hence the total interfacial energy. Spheroidization depends on diffusion transport, and would therefore have occurred during the hot part of the thermal cycles. By changing the distribution of hard, brittle intermetallics, spheroidization can often have a significant effect on the mechanical properties of eutectic microstructures. For example, spheroidization can break up Figure 10 Chip resistor lead-free solder joint with void

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networks of brittle phases that would otherwise act as a continuous path for crack propagation. Spheroidization, does not involve a phase transformation, but simply a morphological change. However, this does not preclude the possibility of phase transformations occurring simultaneously with spheroidization. In the present study, it was difficult to determine if such transformations had occurred, due to the small size of some of the particles involved, which were below the spatial resolution of EDS (typically , 1 mm). Also, the apparent compositions of the larger particles, whose composition could be determined using EDS, did not tie up with the limited available phase diagrams. Identification of subtle microstructural changes would require the use of transmission electron microscopy (TEM) for microstructural characterization, which was not practicable given the large number of samples involved. Spheroidization commenced quickly and was clearly apparent in all samples after only 500 cycles. There were variations in the extent of spheroidization within each alloy and an unequivocal difference in spheroidization from alloy to alloy was not apparent. Based on the results discussed above, differences in the gross fillet microstructure alone would not seem to account for the marked differences in thermal fatigue performance of the alloys studied.

Intermetallic layers The formation of distinct intermetallic layers was observed at the interfaces with the solder as seen in Figures 11-14. The typical X-ray elemental mappings contained in Figures 15 and 16 show that the copper and nickel layers largely remained on the surface of the PCB, because the intermetallic layer acts to some extent as a diffusion barrier. Nonetheless, sufficient copper and nickel diffused into the solder to form a variety of fine (a few mm in diameter) second phases throughout the fillets in all of the systems studied, as shown in the backscattered electron images in Figure 17. A distinct difference between the alloys studied was the nature of the intermetallic layers (Figures 11-14) during cycling from 240 to 1508C. The intermetallic layers in the two Sn-Ag-Cu-Bi alloys were fairly fine (typically around 1-3 mm thick) and continuous. The layers formed with the 95.5Sn-3.8Ag-0.7Cu alloy were similar. In contrast, the Sn-Ag-Cu-In alloy produced a highly irregular intermetallic layer consisting of large (10-20 mm) angular precipitates. An unequivocal compositional difference could not be confirmed between the intermetallic layers formed in these different alloys. This analysis was complicated by EDS spotsize issues (see above) and overlaps between the In and Sn


Figure 11 SEM images of 95.5Sn-3.8Ag-0.7Cu joints after various number of thermal cycles (2 40-1508C)

Figure 12 SEM images of 93.5Sn-3.8Ag-0.7Cu-2.0Bi joints after various number of thermal cycles (2 40-1508C)

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Figure 13 SEM images of 92.35Sn-3.35Ag-1.0Cu-3.3Bi joints after various number of thermal cycles (2 40-1508C)

Figure 14 SEM images of 88.5Sn-3.0Ag-0.5Cu-8.0In joints after various number of thermal cycles (2 40-1508C)

X-ray peaks. Since the 88.5Sn-3.0Ag-0.5Cu-8.0 In alloy performed best in the 240-1508C thermal cycling testing, and the 95.5Sn-3.8Ag-0.7Cu the worst, the size and morphology of these intermetallics could be the reason for

the observed differences in performance between these alloys. However, a clear correlation was not observed between the performance of the various alloys investigated and any single microstructural feature.


Figure 15 Elemental maps of a 88.5Sn-3.0Ag-0.5Cu-8.0In joint before cycling

Conclusions In this work, the thermal cycling reliability of several 2512 chip resistor lead-free solder joint configurations has been investigated, with the motivation of qualifying leadfree solders for harsh environment applications in ground and aerospace vehicles. In an initial study, a comparison was made between the solder joint reliabilities obtained with components fabricated with both tin-lead and pure tin solder terminations. For parts from two vendors, little difference was seen in the reliabilities for the two termination types. However, there was a noticeable difference in the reliabilities found for components from the two vendors. In the main portion of the experimentation, reliability testing of 2512 solder joints was performed using two temperature ranges (240-1258C and 240-1508C) and five

different solder alloys. The two parameter Weibull failure plots indicated that the eutectic SAC alloy (95.5Sn3.8Ag-0.7Cu) recommended by earlier studies has similar reliability to standard 63Sn-37Pb for testing from 240 to 1258C. However, 63Sn-37Pb joints dramatically outperformed the lead-free SAC alloy joints for the more extreme 240-1508C testing. This result agrees with earlier observations for CBGA and non-underfilled flip chip on laminate assemblies (configurations with high stiffness components, large CTE mismatches, and large temperature excursions). Such results further underscore the need to be cautious when proposing lead-free solder substitutions for SMT configurations in harsh environments. The measured data also indicated that quaternary variations of the lead-free SAC alloy (Sn-AgCu-X), which include small percentages of bismuth and indium, can be used to the enhance the 240-1508C

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Figure 16 Elemental maps of a 88.5Sn-3.0Ag-0.5Cu-8.0In joint after 4,000 cycles

thermal cycling fatigue resistance relative to the standard 95.5Sn-3.8Ag-0.7Cu. A second set of thermally cycled samples was used for microscopy studies to examine crack propagation, changes in the microstructure of the solders, and intermetallic growth at the solder to PCB pad interfaces. Failure analysis has shown that the solder joint cracking and creep-fatigue damage propagates as expected for chip resistors on FR-4 substrates. Cracks begin underneath the component and then typically follow along a path that parallels the resistor termination until complete separation has occurred. Voiding was also observed in several of the lead-free solder joints, illustrating the need to further optimise the assembly process and reflow profile for each lead-free solder type. This voiding is one possible explanation for the variations from linearity (waviness) and low b values in the Weibull failure data. Another contributing factor could be material

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property variations. Further work is needed to fully understand the fundamental reasons for the relative reliability rankings of the solders and the Weibull slope variations. Spheroidizing of the eutectic was observed to progress rapidly during cycling of all of the lead-free alloys, and was clearly apparent in all samples after only 500 cycles. There were variations in the extent of spheroidization within each alloy and unequivocal differences in spheroidization from alloy to alloy were not apparent. It is believed that differences in the gross fillet microstructure alone do not account for the marked differences in the thermal fatigue performance of the alloys studied. A distinct difference between the alloys studied was the nature of the intermetallic layers. The intermetallic layers in the two Sn-Ag-Cu-Bi alloys and the 95.5Sn-3.8Ag-0.7Cu alloy were fairly fine


This work was funded by the NSF Center for Advanced Vehicle Electronics (CAVE).

Figure 17 Phases and elemental constituents for 88.5Sn-3.0Ag-0.5 Cu-8.0In joints after 500 and 4,000 cycles

(typically around 1-3 mm thick) and continuous. In contrast, the Sn-Ag-Cu-In alloy produced a highly irregular intermetallic layer consisting of large (10-20 mm) angular precipitates. Since this indium variation of the standard SAC metallurgy performed best in the 2401508C thermal cycling testing, the size and morphology of these intermetallics could be the reason for the observed differences in reliability performances of these alloys at high temperatures. However, a clear correlation was not observed between the performance of the various alloys investigated and any single microstructural feature.

References Farooq, M., Goldmann, L., Martin, G., Goldsmith, C. and Bergeron, C. (2003), “Thermo-mechanical fatigue reliability of Pb-free ceramic ball grid arrays: experimental data and lifetime prediction modeling”, Proceedings of the 53rd IEEE Electronic Components and Technology Conference, New Orleans, Louisiana, pp. 827-33. Grossmann, G., Nicoletti, G. and Soler, U. (2002), “Results of comparative reliability tests on lead-free solder alloys”, Proceedings of the 52nd IEEE Electronic Components and Technology Conference, San Diego, California, pp. 1232-7. Lau, J.H., Hoo, N., Horsley, R., Smetana, J., Shangguan, D., Dauksher, W., Love, D., Menis, I. and Sullivan, B. (2004), “Reliability testing and data analysis of lead-free solder joints for high-density packages’”, Soldering and Surface Mount Technology, Vol. 16 No. 2. Sayama, T., Takayanagi, T., Nagai, Y., Mori, T. and Yu, Q. (2003), “Evaluation of microstructural evolution and thermal fatigue crack initiation in Sn-Ag-Cu solder joints”, Proceedings of the ASME InterPACK’03 Conference, Maui, Hawaii, Paper Number IPACK2003-35096, pp. 1-8. Schubert, A., Dudek, R., Walter, H., Jung, E., Gollhardt, A., Michel, B. and Reichl, H. (2002), “Reliability assessment of flip-chip assemblies with lead-free solder joints”, Proceedings of the 52nd IEEE Electronic Components and Technology Conference, San Diego, California, pp. 1246-55. Schubert, A., Dudek, R., Auerswald, E., Gollhardt, A., Michel, B. and Reichl, H. (2003), “Fatigue life models for SnAgCu and SnPb solder joints evaluated by experiments and simulation”, Proceedings of the 53rd IEEE Electronic Components and Technology Conference, New Orleans, Louisiana, pp. 603-10. Stam, F.A. and Davitt, E. (2001), “Effects of thermomechanical cycling on lead and lead-free (SnPb and SnAgCu) surface mount solder joints”, Microelectronics Reliability, Vol. 41, pp. 1815-22.

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Internet commentary I would not enter on my list of friends . . . the man Who needlessly sets foot upon a worm [1] At the time of writing, we are being plagued by yet another worm, MyDoom, aka half-a-dozen other names. At least one person has my name on his address list, is foolish enough to use Outlook or Outlook Express and sufficiently stupid to have opened an unsolicited and unidentified attachment. I know this because I have received hundreds of ‘‘bounces’’ from Web sites with firewalls which have rejected the receipt of the same virus. When will people learn? This time, Microsoft have offered a reward of $250,000 for information leading to the prosecution of the perpetrators of this virus. I don’t think this is a good idea. If it is generalised, it will encourage people in Third World countries to write new viruses, have a friend denounce them and split the proceeds between them and the judicial authorities. However, it could also be interpreted as an admission that Microsoft software is responsible for the propagation of this worm. Bill Gates has recently announced, at the Davos World Economic Forum that his company will have killed spam within a couple of years. His proposal is to introduce a method whereby e-mail messages will be charged a nominal fee. The notion is that, if you and I send a few dozen e-mails per day, and each one is charged one or two cents, then this is not catastrophic. If, as is common today, a spammer were to send two or three million messages, this would cost a small fortune. Will it work? I personally cannot see it being effective, because it would mean that every single ISP in the world would have to co-operate. Even less effective would be the idea to subscribe to a system, run by Microsoft at a cost, of course, whereby the company puts virtual stamps on each non-pre-approved message and the cost of these ‘‘stamps’’ is charged to the originator, assuming he can be traced and he is willing (and able) to pay. Subscribers to the system would probably not even be able to receive e-mails from originators who were not pre-approved. A whitelist filter on the e-mail client would be just as effective and would cost almost nothing! Quite frankly, I think the only way to handle spam is to make sure that it cannot be read. The ISP that I use pre-filters the more blatant spam (and virus-containing messages), eliminating probably about 80 per cent before it even reaches my mail box. I’m not sure that I like this because there is always the risk of a false positive, meaning a message which I can never see. I admit that this risk is very small. The 20 per cent of spam which does get through is effectively filtered by my own system and it takes me only a few seconds per day to check against false positives and eliminate the lot, unread, in one fell swoop.

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While on the subject of Microsoft, the company has just announced that they have provided the means to block yet another ‘‘serious security threat’’ in various versions of Windows. I have some questions which are as follows. . Why has it taken several years for this threat to be discovered, if it is deemed ‘‘serious’’? . The discovery was made by a specialist security company, outside of Microsoft, over 6 months back. If the threat is ‘‘serious’’, why did it take over 6 months to issue a patch, bearing in mind that Microsoft claim to respond to urgent problems within 3 months? I think it may appear that Microsoft’s credibility problem is worsening. This could even be exacerbated by the source codes for some Windows versions being leaked on the Internet. The company’s immediate reaction was to say that it made Windows more vulnerable to attacks. Yet Linux, which has open-source code, which is very widely distributed, does not appear to be overvulnerable to the worst effects of crackers and hackers. Is there a contradiction here? I have often written about e-mail clients and I shall probably write still more articles on the subject, so this one will be no exception. As regular readers will know, I have always been very cautious about using Outlook or Outlook Express, mainly because of the security implications, such as those outlined above. As a result, I have been using Netscape, in various versions, for nearly 10 years. The latest version, 7.02, has been extremely good but does suffer from a few disadvantages. From time to time, I have tried various other e-mail clients, such as Opera, Eudora and so on. I have never been convinced to change to one of them. Having read eulogistic criticisms of Pegasus, I thought I would give that one a try. It was quite an interesting experience and it is certainly the most ‘‘geekish’’ e-mail client that I have tried, up till now. However, it had a number of features which I simply did not like, even after using it continuously for several weeks. I therefore regretfully abandoned this idea. During the time that I was trying Pegasus. I thought I would take a poll of what some of my friends were using. The results are shown in Table I. Now, I don’t pretend that this table is representative of the Internet community, as a whole, because many of my correspondents are possibly above-average in computer savvy. I was quite surprised, nevertheless, to find that fewer than half were using Outlook, in any form. This may also be partially explained by the fact that a few of them (especially in the ‘‘Other clients’’ category) are using MacOS or Linux platforms. I noted that the three clients that I tried while seeking a better choice than Netscape (Eudora, Table I E-mail client Outlook Outlook express Netscape Mozilla Mozilla thunderbird Eudora Pegasus Opera TheBat Other clients Total

No. votes 14 17 2 10 7 3 2 5 1 9 70

Percentage 20.00 24.29 2.86 14.29 10.00 4.29 2.86 7.14 1.43 12.86 100

Pegasus and Opera) all obtained fairly low scores. I was, however, surprised to see how few were using Netscape, which I had always considered as the main alternative to the Microsoft clients (it used to be the Number 1, before Microsoft considered that the Internet was here to stay and tipped up the level playing field). Now, Netscape is an off-shoot of Mozilla, using the same basic open-source code. This inspired me to have a closer look at Mozilla in its various guises. The full Mozilla is actually very similar to Netscape, as can be expected. This means that it is rather top-heavy. However, some time back, the Mozilla developers realised this and started to split it into lighter, simpler, modules, rather than have everything under one roof, while keeping the basic functionality. The main parts are Mozilla Thunderbird as the competition to Outlook and Mozilla Firebird for Microsoft Internet Explorer. Although, at the time of writing, the applications are not yet fully released, they are already extremely stable and reliable. I’ve been using both Thunderbird and Firebird for some months, from now. To give you an idea of how I’m impressed at this lean and mean software, I’ve made them, a month or so ago, my default e-mail client and browser and I’ve stopped using Netscape, except for archival reference. The changeover has been totally painless. The implementation of POPFile, the Bayesian mailbox filter I’ve been using for over a year, was easy. Thunderbird also has a Bayesian filter, but I have not tested this because it is only a simple spam/not-spam implementation and POPFile gives me full satisfaction with many more facilities, including automatic sorting to different mailboxes, and features. Does Netscape offer anything that Thunderbird doesn’t? I think the answer must be negative, although the implementation of the menus is different. Of course, Thunderbird has eliminated all the annoying little Netscape-oriented features, including the force-feeding of AOL and a few other related sites. One feature I particularly like, compared with Netscape 7.x, is that the left hand box of Thunderbird shows the ‘‘folders’’ tree by default, but it changes to the Address Book when in any mode, whereby a message is being prepared for sending (in Netscape, although it was configurable, the two windows were above and below each other, giving insufficient space for either). Thunderbird has become an extremely practical tool and, now that it is stand-alone, should logically give Outlook and Outlook Express a better run for their costless money, even for those who still wish to use Internet Explorer for browsing. Changing to Thunderbird will eliminate many of the security hazards associated with the Microsoft clients and the use of their Address Book by worms. I can highly recommend it. Having consecrated the Netscape e-mail client to the virtual waste paper-basket (or shredder), what about browsing? Well, Firebird is equally lean and mean, yet retaining all the useful features that I’m used to, and more besides. I particularly like having Google as a default part of the main toolbar – in Netscape, I used a plug-in to add it to its own toolbar, but it frequently spontaneously disappeared. Also, the optional sidebar can be controlled by toolbar icons to allow one to switch between bookmarks, downloaded files and history. Gone is the need to use Ctrl-H to find a site you looked at a couple of days back, although the

facility is still there if you want it, but it toggles it into the same place and not into a pop-up window. Talking of pop-ups, the ‘‘Block Pop-up Windows’’ option is still there, with the ability to override it for given Web sites (sometimes particularly necessary for on-line banking) but it has the advantage that it is no longer overridden for Netscape sites. One shouldn’t forget, either, that Mozilla introduced tabs into browsing a few years back; this allows you to switch between any reasonable number of open web pages by a simple click on a tab. It is a wonderfully useful feature that some other browsers have copied, but many have not. The $64,000 question (wow! That dates me, doesn’t it?) is whether it is worthwhile changing from another browser to Firebird? If you are currently using Netscape and are changing your e-mail client to Thunderbird, the answer is an unequivocal yes. If you are using Microsoft Internet Explorer, there are definite security advantages, as many illicit bugs specifically target IE. Also, MSIE does not fully conform to internationally accepted HTML and XML protocols, whereas Firebird does so, rigidly. The answer, then, is, yes, there are definite advantages in changing, even if it will take a day or two to accustom yourself to a slightly different layout and the numerous keyboard shortcuts. From other browsers? Well, I can’t really say – maybe you should try it for yourself. All I can say is that I highly recommend it as a darned good browser. So, are you interested in trying out my cutting-edge recommendations? Go to http:// www.mozilla.org/ to find out more about Thunderbird and Firebird. At the time of writing, it will cost you the time to download, respectively, about 7 and 6 MB and a few minutes to install them by a simple copy (Windows versions). For comparison, the Netscape set-up procedure – which is hairy – involves decompressing 40 MB into a set-up folder while the download is proceeding. Anyway, as the software is open source, it is free-of-charge. Versions are available for all flavours of Windows, MacOS and Linux. I don’t think you will regret it – I haven’t! This is a technical journal, publishing peerreviewed papers, usually of a high standard and theoretically devoid of commercial connotations (the practice may drift away from the theoretical ideal, from time to time, but that is an inevitable part of life). The fact that this journal does not support commercial advertising is very much a plus in its favour, because there cannot be pressure to promote advertisers’ publications in its editorial pages. There are numerous commercially-oriented magazines available and some of these also publish technical articles of varying merit. These do not compete with technical journals but, rather, complement them. My review theme, therefore, is to look at this sector.

menu to the current issue and some regular features. Naturally, I homed in on the current issue and found most of the articles available directly in PDF format. Slightly annoying is that each one was preceded by a page advertising the UP Media’s own e-mail updating service (which some may regard as spam!). The quality of these articles is generally descriptive and varies from good and informative to reasonable but obviously promoting given products manufactured coincidentally by the authors’ employers. I homed in on one article, in particular, because it dealt very specifically with my area of expertise. It was very banal and offered no real information, bar a couple of technical errors, that had not been available for a number of years. This particular one did not offer any references, although some of the other articles did bear some thoughts for further reading. It should be noted that the articles in question are reproduced from the hard copy magazine, with a watermark but without the advertising. Altogether, this is quite a useful source of general information.

http://www.pcdandm.com/ This site is a sister to the previous one, the magazine being Printed Circuit Design and Manufacture, in case the cryptic URL means nothing. Now, dear Reader, I can almost hear you asking what that has to do with the subject of this journal. Well, my answer is, ‘‘A lot’’. I believe in concurrent engineering as a means of costreduction and quality-improvement. If you are concerned with shooting components onto a PCB, please remember that someone designed that board and someone else manufactured it. Were you consulted as to what would make life easier for you, in terms of manufacturability? I’ll hazard a guess: no! Did you go out of the way to tell these guys that you wanted more free space around a given component type or that putting some component types on a HASL surface is problematic? Possibly not. In which case, many of the problems you have are partially of your own making: tough! Just think, if the development engineer, the ECAD/EDA designer, the PCB-fab guy, the purchasing manager, the tester, the reliability expert and you all sat round a table at the start of the design stage and regularly thereafter, until the product was launched, you could tell each other what your requirements are, to the benefit of all. So, reading this magazine would be of benefit to you, wouldn’t it? Not convinced? Well, the keynote article in the current issue, as I write this, is entitled BGA Land Pattern and Assembly Issues. Otherwise, the site is very similar in style and layout to that of Circuits Assembly, albeit with, I believe, a tad more publicity.

http://www.circuitsassembly.com/

http://www.trafalgarpublications.com/

This well-known magazine from the UP Media Group opens to a Home Page whose main feature is a series of links to ‘‘Current News’’, mostly of a commercial nature. Below this are a couple or so of links to articles from the current issue of the hard copy magazine. The page is remarkably free from advertising. The left-hand side of the page shows, mostly, a text menu for general navigation, while the right side consists of a more pictorial

As I write this, the Global SMT and Packaging site is undergoing a facelift, so I cannot comment on it, other than to say that, knowing the hard copy magazine, it is one of the best ‘‘freebies’’, with some very good articles and even papers. Hopefully, when this journal hits your In tray, the site will be up and running and, equally hopefully, well worth your visit. In the meanwhile, you can download the current issue and ask to be

placed on the mailing list as a reader or as an advertiser.

http://www.reed-electronics.com/epp/ Electronic Packaging and Production is, of course, one of the oldest magazines of this type. Even though the publishers, the Reed Electronics Group, are entirely independent from the UP Media Group, the Home Page of EP&P is quite similar in layout to that of the first two sites reviewed in this article. However, there is one difference I do not like and that is that the page is set up for a fixed width of 760 pixels. This means that optimum viewing is at 800 wide resolution or, possibly, 1024 if you use a browser with a sidebar. Anything else and you either lose part of the image from view or part of your screen width is wasted; in both cases, you have to scroll more than would have been necessary had a variable-width layout been used. On the positive side, the articles are faster to access, being HTML and not PDF, as well as not having that annoying introductory page. Again, the articles are on a fixed-width page and the actual articles themselves are only about 480 pixels wide; this gives an average of about 12 words per line, so that it is necessary to scroll through 10 times the screen height for even quite a short article. Again, I homed in on an article relating to my speciality. By coincidence, it happened to come from the same source as the one I mentioned in the Circuits Assembly earlier in this article. This time, though, it was much more blatantly commercial, even to the extent of ‘‘knocking’’ the competition, with a host of halftruths cleverly worded to push their own product. I did not like this style, so I had a look at a few more articles to see whether this one was generic or had just managed to slip through. Sadly, it would appear to be generic and nearly all the articles I read had very commercial overtones, although most did not ‘‘knock’’ the competition but simply ‘‘pushed’’ the authors’ own techniques. This does not mean that the articles are devoid of merit; simply, that the reader needs to use judgement to sift the facts from hype.

http://www.pentair-ep.com/ This is a magazine of an entirely different type, an in-house one destined to inform customers as to what is going on, new products and so on. This particular one, published by a company manufacturing enclosures for different purposes, is a very good example of the genre. Of course, its main function is a platform for publicity, but this is entirely in order.

http://members.ipc.org/IPCLogin/ IPCMembers/IPC/Review/0204/ index.asp Of course, you have to change the 0204 in the URL to the month/year of the issue you wish to see. This is the Web site version but it is also available in a PDF version by changing the URL’s index.asp to 0204pdfofreview.pdf. However, I’m not too sure whether it is accessible to nonmembers, although I believe it is, after logging in. The IPC Review is well known to the IPC members, who receive it in hard copy. In most months, there is at least one technical paper or article and the IPC makes sure that it is essentially non-commercial.

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The ‘‘front cover page’’ of each issue is, unfortunately, also fixed-width, this time at 800 pixels (as are most of the IPC Web sites), but this is slightly less serious than with EP&P, because there are about 640 pixels available for the meat of the page, a third more. I liked the menu column on the left. Hovering over an item revealed a slightly longer explanation. For example, in the February issue, hovering on ‘‘38 Years of Commitment in Europe’’ tells

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you that this link leads to an interview item ‘‘IPC’s newest European representative talks with IPC’s oldest member in Europe, Zincocelere’’. Nice! As this article is slightly longer than usual, I have decided not to show you a screen capture of one of the sites visited. Brian Ellis Cyprus [email protected]

Note 1

I would not enter on my list of friends (Tho’ graced with polished manners and fine sense, Yet wanting sensibility) the man Who needlessly sets foot upon a worm. William Cowper, The Task (1785) bk. 6 The Winter Walk at Noon l. 560.

Book reviews Electronics Assembly Technology – 2nd Edition Wolfgang Scheel Electrochemical Publications Ltd, IOM 939+xvii pp. Figures: 611 (40 colour plates) Tables: 158 References: 1,408 GBP 109.00, USD 218.00 plus p&p Keywords Assembly, Electronics technology, Books Let me start by making it quite clear that this book is a translation from the German, Baugruppentechnologie der Elektronik – Montage, which is in its second edition. It has never been published before in the English language. It is a peculiar book, written by a group of very eminent Germans, each specialising in a fairly narrow field of activity. They have a very great in-depth knowledge of each subject, but it would appear that none of them has a wide knowledge base covering the whole theme of the book, because there are a number of subjects that one might expect in a tome of this size but which are glossed over or simply omitted. This does not mean that the book is worthless – far from it – but it does mean that a beginner would need some other sources of information to gain a whole picture. It seems strange that a book of over 950 pages should have only nine chapters, although the first one is numbered zero! I feel that the authors of the Guinness Book of Records would be interested in chapter 4, which starts on page 130 and ends on page 501. I have known many technical books with fewer pages than this chapter! Although the book has been translated from German, the standard of English is excellent – one has to look hard to find a few sentences that may have a slightly more Teutonic turn of phrase than would be normal. On the other hand, one or two technical terms have been translated literally rather than using the current jargon of our industry. This is not a serious fault because the meaning is obvious. Perhaps, the most easily seen Germanic influence is the citing of many DIN standards. Let me quickly go through each chapter, in order. Chapter 0: Introduction. This is a short chapter, summarising the current state-of-the-art. Chapter 1: Electronic components for throughhole and surface mount technologies. This is a very comprehensive chapter of over 30 pages describing all types of active and passive components. It also has a very interesting section on the trends involving different component types. Chapter 2: Types of electronics assemblies. This is quite a simple, short chapter (24 pages), summarising the many different kinds and methods of assembly. At the end of the chapter, there is a useful list of abbreviations (incorrectly called acronyms) of the types which are currently in use. Chapter 3: Mounting of electronics assemblies. This is where the meat of the book really starts, with a 56 page chapter. Through-hole technology is dismissed in less than a single page. The principles of the various machines used for

assembling surface mount technology devices are described in full, followed by a dissertation on placement accuracy including fiducial recognition. After this, a discussion on the economics and costing of assembly precedes a section on computer and software structures for driving the machinery. Chapter 4: Bonding technologies for electronics assemblies. This is the infamously long chapter which, in my opinion, would have been better divided into several chapters. I say this for two reasons: it would avoid undue to-ing and fro-ing and, more simply, to make it into a more logical and easily referred-to set of documents. In fact, it almost falls naturally into three sub-chapters, if it weren’t that the initial section, entitled Fundamentals of bonding, contains information relative to each of the sub-chapters. Of course, soldering forms an important part of this chapter, with a total of about 190 pages. The following 75 pages cover adhesive bonding. The last subchapter is on wire bonding. Each one of these three sub-chapters is very detailed with many tables and graphs. Chapter 5: Diagnostics of electronics assemblies. This chapter has a misleading title because diagnostics is the art of diagnosis, in turn the process of determining the nature of a disease. In reality, the chapter is all about testing, including that of healthy assemblies. The first 44 pages are devoted to destructive test methods, such as mechanical stressing, metallographic sectioning and accelerated ageing tests. The following 100odd pages cover non-destructive test methods embracing a large amount on optical methods – including outside the visual spectrum of electromagnetic radiation, in-circuit testing and so on. This chapter also has a list of abbreviations, correctly termed this time! Chapter 6: Technical reliability of material connections. The main part of this chapter is devoted to the reliability of the solder joint. It enters into the subject in great mathematical detail, some of which is beyond my comprehension. This is a very important subject, especially with the advent of lead-free solder, and this is probably amongst the best treatises that I have come across outside of specialist metallography books. Chapter 7: Design for production of PCB assemblies. When I first saw the chapter title, I said to myself, ‘‘At last! A book introducing the notion of concurrent engineering!’’. I was disappointed. Half of this chapter is about footprints, albeit very important, and the other half is about warp and twist. There is nothing about board layout, electromagnetic compatibility, routing or of the other many subjects whereby, the design of the board influences the manufacturability. I don’t really understand why this chapter was not put at the beginning of the book; surely the design of an assembly must precede the physical act of assembly itself! Chapter 8: Standards for assemblies. I don’t think that I need to enter into much detail here, other than to say that this chapter is the most internationally oriented within the book. The book is completed by an appendix with several pages of good quality colour plates, a list of symbols used in formulae and equations and an extremely good index. The notion of separating the colour illustrations from the text is annoying, because the text does not always refer you to the appendix and you can look in vain for the figure, until it strikes you that it may be at the end of the

book. I have a suggestion for the publishers if they continue to use this economical method; they should complement the text with a thumbnail captioned monochrome illustration on the same page, with a reference to the full-size colour illustration page number. Each of the chapters, with the exception of chapter 3, has a massive list of references (chapter 3 has but one, while chapter 4 has 937!). This is extremely valuable although it must be said that many of them are in the language of Goethe, for those of us who understand only Serbian, Chinese or English. Physically, the book itself is produced with the high standards that we have come to expect from the publishers. The paper, typography, the binding and the quality of the many line drawings are all impeccable. I don’t believe that this is a book meant for the shop floor operator. The title includes the word ‘‘technology’’ and it is designed for technologists with a good basic grasp of the subject, wishing to deepen their knowledge of the matters covered therein. Brian Ellis Cyprus

The Design of CMOS Radio-frequency Integrated Circuits Thomas H. Lee Cambridge University Press, England ISBN: 0 521 83539 9 797+xviii pp, 20 ch. (hardback, 185 £ 260 £ 42 mm) GBP 45.00, USD 75.00 Keywords CMOS, Integrated circuits, Books It must be said from the start that the subject of this book is marginal to this journal, although there is some overlap. When I first saw the cover illustration – a 0.18 m CMOS transceiver die in the 5-6 GHz bands – (Plate 1) and title, I imagined that it was going to be a rather dry ‘‘how-to’’ work on driving the CAD system for the actual die production. I was totally wrong. It is a full fledged engineering book, going back to first principles, and a good one, at that. Despite being full of equations (many of which were beyond my understanding, having done my RF engineering studies when UHF was still an adventure with such things as Barkhausen oscillators and microwaves were essentially klystrons and pulsed magnetrons for radar), the author’s style is easy to read and even quite humourous. I was very much at home in the opening two chapters, which were in the form of a brief historical survey of RF communications from the spark transmitter through to third-generation mobile handsets. In fact, it was fascinating reading, as it took me back to the spark transmitters and crystal sets I made as a kid! I found it instructive, too. For example, I didn’t know that the first solid state RF amplifiers and oscillators, using a zinc mineral as semiconductor, date back to 1922, a quarter of a century before the transistor saw the light of day. This was the work of a Soviet Engineer, Oleg Losev. Even less did I know that Henry J. Round published a paper describing orange, yellow and even blue LEDs in

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Plate 1

. . .1907, yes, nearly a century back. He used Carborundum (silicon carbide) as his semiconductor. When I was a student, we all learned that Lee de Forest invented the triode, the first thermionic valve (vacuum tube for my American readers) capable of amplification. As such he was almost adulated. What we didn’t know then was that he was an opportunist, plagiarist and even a convicted fraudster. Dr Lee points out that he didn’t even realise the amplification potential of his invention, which was only a means of circumventing an Edison patent for the diode as a detector. The book then discusses the standards for cellular telephony, and the way they work, WiFi, Bluetooth and other modern SHF systems, including those for unlicensed modes such as are used for garage door openers, RC toys and so on. The crunchy part of the book starts with chapter 3, describing RLC networks, most of which is AC theory at 2nd or 3rd year student level, even in my days. This is followed by a chapter on passive devices as may be configured within an IC chip, as lumped components but also laying the groundwork for distributed ones. The fifth chapter goes through the physics of FETs, MOSFETs and similar configurations, ending up at the derivation of Spice models. We then come back to a detailed treatise on distributed systems, so important at giga hertz frequencies. A little dated in this age of computers is the Smith chart, which I had almost forgotten existed, even though it gives a pictorial view of transmission lines. Incidentally, there are a couple of pages here on units. This well-expressed digression is required reading for every engineer, technician or even purchasing manager and a subject close to my own heart; I shudder, every time I see units misused, yes, even in this august journal. This is followed up with techniques for estimating bandwidth and enhancing it within the amplifier design; it was refreshing to see that the shunt-peaked amplifiers present today are almost the same as I used in my dissertation on colour TV in 1951 (except for the nature of the active components, of course!).

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The tenth chapter is based on applying bias voltages to the semiconductors, derived from bandgap voltage references, while the next one is all about the very thorny subject of noise. In this day of digital communications, noise is perhaps of less importance, but the grey area of reliable bits is still a problem. Low noise amplifier design is therefore, a natural follow-on. When Armstrong designed the first superheterodyne receiver in 1917, he could not have realised that this same idea would still be used in 2004 in such a wide range of radio (or, synonymously, wireless) devices. The heart is, of course, the mixer, such a simple but misunderstood contrivance; Dr Lee states, ‘‘. . .electrolytic cells, magnetic ribbons, brain tissue and rusty scissors. . .’’ can be used, as well as traditional thermionic and semiconductor devices. An extensive chapter on feedback systems (negative and positive) follows. Power amplifiers are then treated (a class A power amplifier is ‘‘. . .a standard, text-book, small-signal amplifier on steroids.’’). I admit that I learnt a lot in this chapter, as this is the first time I have encountered constant envelope amplifiers of classes D, E and F (maybe this is an admission of how out-of-touch I am!). However, I was very happy to see that the good old Heising modulation is still used on the classic class C PAs. One of the most important electronics concepts developed mainly since the second World War is the phase-locked loop (PLL), used in FM receivers, TVs and all sorts of other devices based on frequency synthesis. Chapter 16 discusses various types of PLLs in detail, naturally followed by another on oscillators (I see the names of Pierce, Hartley, Colpitts and Clapp in use currently.) and synthesisers. The term ‘‘phase noise’’ is new to me, although the concept is not; we considered it simply as an anomaly causing difficulty in tuning a receiver under some conditions, without actually putting a name on it, other than ‘‘interference’’. There is a lengthy chapter offering counsel on how to minimise it. The chapter entitled Architecture is quite complex, illustrated with such analogies as the computer mouse to illustrate phase quadrature, leading onto the actual chip design. The final chapter goes back to the historic start and illustrates a sampling of milestone RF devices throughout the 20th century, complete with circuit diagrams. As I stated, the book is easy to follow for an esoteric technical work, aided by an eagerness to find the next spark of humour that helpfully illustrates a point, in the tradition of the lectures of Richard Feynman. It is written in the US vernacular and lavishly endowed with page footnotes, some serious references, others more light-hearted. Each chapter has a set of problems at the end for the student to do (and no ‘‘crib’’ to allow him to cheat!). It is well printed and the line illustrations are perfect (even if the component symbols are also in the US vernacular). The line spacing and character font are easy on the eye and the mathematical equations are well-spaced and clear. The index is outstandingly excellent. Other than every latter-day student of RF engineering, who should read this book within the context of the readership of this journal? I firmly believe that it would be useful for anyone designing or assembling RF circuitry, even if he buys – or has made for him – his ICs. The interconnections between the chips still follow exactly the same rules as within them. Even with COB techniques, the wire loop between the die and the PCB, whether it be an MCM or a mother

board, offers more inductance than may be affordable at 3 or 5 GHz and this could make or break the performance of an assembly (not to mention etched lumped or distributed components on a PCB, ideal in the UHF range). Brian Ellis Cyprus

Bob Willis’ Top Ten reference books 2004 Keywords Reference, Books, Printed circuit boards, Soldering, Electronics The list of ‘‘Bob Willis’ Top Ten’’ reference books that has been updated for 2004 considers the recent changes in technology. In the publishing industry there are many charts and awards for the best selling books, but with sales in the tens and hundreds, not thousands, it would be impossible to have a sales chart for technology handbooks. There are only two changes to the top ten this year, there were two others I wanted to add, but Top Ten is not top 12! This list does not indicate the number of sales of any one title, the age or up to date nature of the text, only my opinion on the ‘‘must have’’ engineering titles for your office bookshelf. Remember: generally no new problems in manufacture exist; most have been seen before by someone. Good reading until next year and keep up to date with new titles at the Web site: www.smartgroup.org Area Array Interconnection Handbook . Karl Puttlitz and Paul A Totta . Kluwer Academic Publishers Comprehensive Guide to Design, Manufacture of Printed Board Assemblies . Bill MacLeod Ross . Electrochemical Publications Flexible Circuit . Joe Fjelstad . Electrochemical Publications Quality Assessment of Printed Circuit Boards (Out of Print) . Preben Lund . Bishop Graphics Inc. Reflow Soldering Processes and Troubleshooting . Ning Cheng Lee . Newnes SMT for PC Board Design (2nd Edition) . James Hollomon . Prompt Publications Printed Circuit Handbook (5th Edition) . Clyde Coombs, Jr . McGraw-Hill Electronic Failure Analysis Handbook . Perry L. Martin . McGraw-Hill Microelectronics Packaging Handbook (1st Edition) . Tummala and Rymaszewski . Van Nostrand Reinhold Soldering in Electronics (2nd Edition) . Klein Wassink . Electrochemical Publications Bob Willis

Company profile Fulleon, their switch and the wardrobe Keywords Fulleon, Environmental regulations, Legislation, Electronics industry Industry is being subjected to more stringent environmental legislation. The focus of the End of Life Vehicle Directive, IPP, WEEE and ROHS is to get companies to examine the environmental impact of their company and their products, throughout the total product lifecycle, and take responsibility for it. Many companies equate this with increased expenditure in time and resources, and another slice off the bottom line. Despite British businesses feeling very apprehensive about the effect tighter environmental legislation could have on them, the truth is their fears are as real as the monster in the wardrobe. The government programme, Envirowise, is showing companies how making environmental improvements actually makes good business sense and even better financial sense. Companies grasping the bull by the horns, preparing for tightening legislation by adopting cleaner design principles, are making both monetary savings and improving their competitive advantage in the world market. Cleaner Design is leading the way as a concept, which helps companies identify how to be compliant with environmental legislation and at the same time bring improvements to the bottom line. Integrated Product Policy (IPP) places the responsibility for a product’s environmental impact from cradle to grave, with its producer. Concurrently, the End of Life Vehicle Directive (ELV) and Waste Electrical and Electronic Equipment (WEEE) directive hold the producer responsible for product recovery at the end of a product’s life. Restriction of Hazardous Substance in electrical and electronic equipment (ROHS) also has end of life product recovery at its heart. Cleaner design considers what happens to the product at the end of its life and then designs it so cost-effective recovery, reuse and recycling is practical. This involves identifying how a product gives rise to environmental impacts during its life cycle. It extends to investigating how these impacts can be reduced through design, while still satisfying customer requirements. This approach ‘‘designs out’’ waste at the beginning of the process, improving efficiency and hence reducing production, distribution, use and end-of-life recovery costs. There is currently a gap between businesses understanding the importance of achieving sustainability within their product development and actually accomplishing it. Envirowise, a government programme that provides free, practical advice to industry on how to improve environmental performance through cleaner design and waste minimisation, is stepping into that gap. Through an extensive range of highly relevant products and services, Envirowise is showing companies how to meet legislation and improve their margins. Of particular note is Designtrack, a service, which offers a confidential site visit from a qualified designer who can help a company identify areas that can be improved. Fulleon Ltd, a company in South Wales making break-glass call points, and other elements for fire

alarms, realised the benefits of cleaner design as it sought to improve the competitiveness of its breakglass call point product in a price sensitive market. Prior to taking a holistic view of the design and production process, product development activities were passed from department to department. Now, each department, from design to purchasing is involved in the product development at each stage of the design process. This is known as a team-based concurrent product development approach and is an integral part of cleaner design. Fulleon set about applying the principles of cleaner design and adopted a life-cycle assessment approach that ascertained the environmental impact of each stage of the product’s life cycle. By adopting cleaner design they have reduced manufacturing costs, improved product features and saved an impressive £92,650 a year, maintaining their leading market position in a competitive world economy. These savings came from an average reduction in material costs of 11 per cent, a reduction in labour assembly costs of 34 per cent and a reduction in the overall unit production cost of 21 per cent. The cleaner design process reduced machining times and assembly times through product changes such as introducing snap fit components, using fewer parts and rounding the edges on some moulds. In addition they also examined their packaging and by using plastic bags rather than cardboard boxes, reduced these costs by 24 per cent (Plate 1). The environmental impact of the improved design is significant with reductions in material consumption, energy use, cardboard packaging, transport costs and less waste at the end of the product’s life. Fulleon’s Technical Director, Dean Arnold, is convinced of the benefits of Cleaner Design. ‘‘There are other benefits beyond the savings we have made that improved our commercial position. We were the first company in the world to achieve the BSEN 54-11 European Standard for Fire detection and Fire Alarm Systems as a result of this project. It has also helped to position us as an environmentally responsible, high quality design and manufacturing business,’’ he explained. Fulleon is part of the Cooper Menvier Division of Cooper Industries Inc. and since introducing cleaner design a new Managing Director has been appointed. Peter Maxwell remains committed to the cleaner design principle and has rolled it out across the group. Peter said, ‘‘Cleaner design makes good business sense, good environmental sense and provides us with a tool that delivers a clear long term sustainable competitive advantage. Using cleaner design techniques with a concurrent Plate 1 Fulleon cleaner design system in use

design approach has allowed us to produce a wide range of environmentally friendly market leading products’’. Making similar sorts of savings is within the grasp of any company and preparing for forthcoming directives may be the catalyst for many companies to consider a cleaner design approach. Envirowise is encouraging companies to examine the opportunities more closely and as a starting point they have produced a series of free guides. The first guide (Cleaner product design: an introduction for industry – GG294) is an introduction to cleaner design and takes you step by step through the process of introducing it to your company. There are easy to use checklists to help you. It also highlights ten simple measures that will improve your companies overall financial and environmental performance, without compromising on efficiency and quality. The second guide (Cleaner product design: examples from industry – GG295) provides examples from industry and shows how nine corporate companies have benefited from cleaner design. Whether your business is large or small the approach is the same and there are lessons to be learnt from this publication. The third guide that is worth requesting (Cleaner product design: a practical approach – GG296) looks at cleaner design across businesses of all sizes and has an emphasis on product disassembly and redesign. It includes instructions for carrying out a systematic dismantling exercise using a standard household item such as a kettle or an iron. This quickly highlights the relative complexity of everyday products and where the opportunities for clean design lie to produce a more costeffective and efficient product. Often our perceptions are that cheaper production costs mean quality is compromised and that environmental improvements have a negative affect on profitability. The reality is that with good design you can reduce the costs and environmental impact of a product while increasing its quality. In a commercial world where environmental impact and sustainability is increasingly important the mantra is more with less. Cleaner design can deliver this. Envirowise is here to show you the way with its guides, case studies and designtrack service. To request the three guides mentioned in this paper or for more information about cleaner design, including requesting a designtrack, contact: Tel: 0800 585794; Web site: www.envirowise.gov.uk

Association news SMART Group 6th Annual Lead-Free Seminar and Table-Top Exhibition, 3 February 2004, High Wycombe Keywords SMART Group, Seminars, Lead-free soldering A packed house, a sell-out event. 179 delegates from all over the UK reflected the rising tide of

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concern with a subject that has been well-aired, not least by the SMART Group, but which has yet to find commercial application in the field in this country. The first of the eight excellent speakers was Steve Andrews from the DTI who spoke about The RoHS Directive – Consultation, Compliance & Enforcement. Steve Andrews comes from the DTI Recycling Policy Unit and he highlighted the six key issues to be decided upon, of which more later. He explained the RoHS Directive, and the six hazardous substances, lead, mercury, etc. He looked at the scope of the RoHS Directive, and informed the delegates that there would be UK regulations in place by August 2004. The consultation period is now nearly over, he said, and the draft regulations and non-statutory guidance would be issued in the spring of this year. The six key issues are as follows: Scope – there are ten broad categories in the WEEE directive. Where topics fall is clear in 90 per cent of cases, but there is a significant 10 per cent that fall into the ‘‘grey areas’’. Debate at EU level is difficult, but the DTI is hopeful that they will get the EU to agree upon a list of criteria that member states might use, by end of March. Typically it is the UK which lead the debate! Definition of producer – the definitions are as follows: . one who manufactures and sells own brand . one who resells under own brand . one who imports or exports into the EU BUT there is a problem with inter-EU trade, internet sales and with how it fits into the WEEE directive. The deadline of 1 July 2006 will apply to all member states, including those many Eastern European countries who are yet to be become full EC members.

Put onto the market Article 4.1 of the RoHS applies here. It will apply to the following: . all equipment leaving the manufacturers premises after this date; . all equipment on sale to the final user; . goods leaving the factory gate (or entering the EU); For full details refer to the EC Blue Book which is available on the Internet . Historic equipment will have to comply regardless.

Maximum concentration values Proposed levels are as follows: . 0.1 per cent for lead, hexavalent chromium and mercury; . 0.01 per cent for cadmium; . 0.1 per cent for PBBs and PBDEs. Steve asked, ‘‘what does homogenous material mean?’’ His understanding is that ‘‘by weight in homogenous materials’’ probably is the wording that will be accepted. Steve said to the delegates that if any of them had any thoughts on this subject, he would be pleased to have them, even though the deadline for consultation had now passed.

Compliance There is a UK contract underway with ERA Technology for the TAC study on enforcement. There are several methods that have been proposed. They are as follows:

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. . . .

self-certification by manufacturers; backed up by EU standards on agreed tests; standards on reporting formats; exchange of information.

However, there is no point in UK-only tests, and none of these by itself is the answer, it will be a mix and match. Self-certification is the way forward possibly.

Enforcement . .

.

There will need to be an enforcement body; There will need to be an enforcement approach; There will need to be testing methods. These exist, but which ones are the best and give the best results?

Steve said that he understood that the Secretary of State for Trade and Industry would be responsible for enforcement, the Trading Standards Officers Association (TSOA) having rejected the wearing of this particular mantle. For further information about Envirowise, contact Tel: 0800 585794; Web site: www.dti. gov.uk/sustainability In response to a question ‘‘Is there equivalent legislation in the USA?’’ he said that yes, there was, needless to say it had started in California, but was being looked at in the other United States, and both China and Japan were establishing full legislation on RoHS policy.

Harsh environment applications for leadfree solder systems was the subject of a talk by Steve Brown of Cookson Electronics These environments are in the automotive, aerospace, military medical and industrial fields, and involve temperature cycling, a corrosive environment which may include vacuum, vibration or both. Steve covered the range of temperature experienced in the automotive environment, and the implications for military use. Lead-free must meet performance requirements; no one needs tin whiskers in space! SAC is the alloy of choice in most applications, but there are variations on the theme involving silver, bismuth, indium alloys and gold alloys for high-end applications. Steve took us on a comprehensive sweep through the various aspects of SAC, and its variations, costs, effect on tombstoning, the wider pasty range. There is, he said, no unique ‘‘best solution’’ for every set of circumstances, tin-silver-copper is a good all-rounder, but every company must have room for something else. SAC is a primary choice, but its behaviour leaves a bit to be desired. He listed some proposals for the prevention of interconnect failures. They are as follows: 1 change package design; 2 compliant joints; 3 underfills; 4 total encapsulation; and 5 board design. Why do tin whiskers cause so much concern? Well, they cause short circuits, they can grow in

ambient temperatures, there is no accepted accelerated test, and remember that products may be stored for many years before use. Nowadays automotive electronics are safety critical, tin whiskers are caused by compressive stress on the tin. Compression is caused by high stress coatings, deformation, intermetallic coating and thermal mismatch. Stress can relieved by reflow, the use of a matt tin finish, a Ni/Ag flash or a pre-bake at 1508C. In terms of intermetallic management, he said that the use of a conformal coating can mask a tin whisker, but there is still a problem with harsh environments. On a brighter note, he concluded by saying that the situation is better now than it was even 1 year back. Another 12 months and who knows. The acknowledged expert on product marking Kay Nimmo of Soldertec tackled the vexed question of lead-free and RoHS marking and labelling systems. This is indeed a complex issue, finding out what type of marking systems people would prefer. However the results of the survey were now in and available from the Web site: www.tintechnology.biz /soldertec/soldertec.aspx? page_id=1637&SelectedMenu_ID=73 Kay said that WEEE labelling will be put on all equipment after 13 August 2005. There were several options – CE marking, a crossed out dustbin, and smart chips – are all possibilities. Nothing has been requested officially from RoHS yet, it is still under discussion. Whilst there is no legal requirement for marking for lead-free, how do you demonstrate compliance? It may well be an industry requirement – but this requirement can vary within the supply chain, it depends on the viewpoint of manufacturers, distributor, assembler, recycler, etc. There is no consumer marking. Kay went on to explain about the difficulty in establishing an acceptable international labelling standard. There were various proposed JEDEC labels, and she suggested that a look at their Web site www.lead-free.org would be invaluable. Mike Fenner of Indium Corporation looked at the practical aspects of lead-free soldering. He discussed some of the difficulties, and what you have to do to convert over to lead-free. Lead free is market driven, and you need to accept that this represents a fundamental change in the process of manufacturing your products. Whilst there are some 200 alloys which have low melting points, the choice is pretty well made with SAC which has a melting point of 2178C compared to1838C for Sn/Pb. It takes longer to get to 2178C and it takes more energy to keep it there. There is an increase in DT. Suitable PCB finishes include HASL, OSP, Organic Ag, ENIG, Pd/Ni, and immersion tin. You will need to consider poorer wetting, harder surfaces, longer times, higher temperatures, using the same equipment. Various options include a change of PCB finish, a change of components, and a change in solder paste. His suggestion was to go away and practice quietly in a corner somewhere, and you need to do it NOW! There are many variables to consider, and you may well want to draw up a wish list for a lead-free solder paste, but you have to expect the unexpected. There will be new inspection criteria, as SAC alloys do not wet as well as the old ones, they are more cohesive. Mechanical properties are different, they are stronger but they are less compliant, and failure models are different.

Mary Gregory from A & D Automation encouraged the view towards vapour phase soldering with lead-free. She looked back to the early machines that were crude and difficult to operate. But nowadays VPS as a means to transfer heat is too good to ignore; it provides efficient heat transfer using perflurorcarbon liquid, which is healthy stuff. Nitrogen is no longer needed. An inert vapour atmosphere in vapour phase soldering gives the best possible solder reflow conditions, where the DT is as close to zero as it is possible to get. The IOR pre-heat, variable heating levels, and Soft Temperature Rise allows you to control the temperature rise at 68/s and there is an economical reflow alternative for high volume SMD manufacturers when they are considering their alternatives for lead-free solder reflow. New VPS equipment can produce a board every 20 s. For lead-free no modifications are needed, all you do is change the liquid to one with a boiling point of 2308C. Is the vapour expensive? No, said Mary, it costs about 1.5p per min for the vapour. Helmut Leicht, Managing Director of the manufacturers IBL, covered some of the problems associated with lead-free which included temperatures exceeding 2308C and wetting problems. Whilst traditional convection reflow equipment is already installed, and the process knowledge is well founded, if equipment has to be replaced then the problems associated with overheating and bad wetting will be eliminated by the use of an inert gas. Vapour Phase has some disadvantages, in that no high volumes are available and VPS is not a mature process in the field. However, these can easily be outweighed by the facts that the equipment can be used immediately, there is absolutely no risk of unsoldered joints, no risk of overheating, and there is the best possible wetting in a 100 per cent inert gas atmosphere in a sealed container. VPS joints typically show finer structure and less oxidation, and wetting is also better. Densely populated boards solder superbly with VPS but not with convection ovens. With VPS you get excellent heat transfer through layers with less risk of ‘‘popcorning’’ of different materials with the lower temperature of reflow at vapour phase, and good temperature pressure in the best thermal environment. Inline machines are now available, and Herr Leicht was keen to emphasise that VPS is worthy of serious consideration when considering equipment replenishment with lead-free soldering demands. That another 50 people wished to attend and had to be turned away indicates the fast-growing awareness of the vital importance of the move to lead-free soldering. The concept of lead-free has been around for a very long time, but it has been left to the SMART Group, amongst a few others, to bring the need for ‘‘action this day’’ to be the call, rather than ‘‘we’ll have a look at it next week’’. The facts and figures given in the paper from Martin Allison of Senju accurately indicates the position of the UK. It makes worrying reading. It is not that the industry will not move to lead-free, for it knows that it has to. But it seems to be leaving it all rather late, and other countries who have positioned themselves to meet the demands of to-day will benefit whilst the UK pursues the ‘‘jam tomorrow’’ philosophy. Plate 1 shows the speakers from the seminars.

Plate 1 All eight speakers from the 6th Annual Lead-free seminar

Smart group workshop – PCB specifications and procurement requirement, 18 February 2004 Keywords SMART Group, Printed circuit boards The how, the what and the where of circuit boards. A bright February day saw a select band attend yet another SMART Group Workshop, this time held at the excellent premises of CEMCO at Waterlooville in Hampshire. The welcome came from Bob Willis, SMART Group Technical Director, who brought the thirty or so delegates up to the mark with developments at the Group. These include their new Newsletter, their interactive CD-ROMs, and their planned ‘‘ Leadfree- Hands On Experience’’ which is being run during NEPCON in Brighton on 26 and 27 May. It was the turn of the peerless Pete Starkey to talk to those present about the how. The PCB manufacturing process may well-established technology, but his detailed insight into the complexity of the manufacturing process gave a experienced view of what needs to be considered when sourcing such commodities. Pete talked the meeting through the steps on how boards are made, starting from the basic building block of copper clad laminate. Designs, he said, now come down modem lines, so distance between buyer and supplier is of no consequence. He went through the stages of how a six-layer circuit board was produced, imaging, lay-up, pressing and materials used, core thickness, the dielectric spacing between builds. Good material utilisation, he stressed, is important.

Making multilayer boards is all about keeping layers in registration; changes in temperature and humidity can play havoc with film stability for registration. The path proceeded, pumice brushing cleans copper wonderfully, essential for good photoresist lamination. The DES process was covered, as well as an explanation of post-etch tooling. Then it was on to AOI, X-ray inspection of drilled holes, then cleaning and deburring, and in some detail the complete process through to electrical test and final inspection. This was a presentation that could only be given by someone who has been making circuit boards with longer care than he would like to remember, and longer than most people would care to. Dennis Price of Merlin Circuit Technology is another industry veteran with over 30 years experience, he talked about the capabilities and design for manufacture from the manufacturers viewpoint, and obviously from great experience and knowledge. Happily, he reported, the last 5 months have been really busy at Merlin, so it was good to come to such an event with a cheerful demeanour. Dennis looked at the problems and ambiguities in board specifications. Yield is everything, and material usage is high on the list of priorities. He described how a supplier should provide a detailed checklist where the current capabilities are listed alongside the approved capability. You need to know about shrinkage factors; how drilled hole positional tolerance is ± 0.025 mm for non-PTH, and 0.050 mm PTH was one example. Dennis ran through a comprehensive list of the detail of capability which is on offer, and which might be requested. He explained in depth what it means for a PCB company in terms of capability and the importance of the customer to know what is on offer – and what is not. Quality is in the detail, and the detail is what matters.

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Phil Stoten is the Managing Editor of EMS Now, but in a previous incarnation was a circuit board buyer, and travelled the world sourcing circuit boards for his clients. As an ex-designer and ex-broker he knows the rules of the game, and he expounded on several of them. The relationship with the fabricator was important, obviously, but he urged people not to underestimate the PCB which is critically important; adding good components to a bad board is expensive and failures in the field are costly. Getting the technology right can save money. Where to buy? – The factors of volume; technology; lead times; support (technical and sales) cost of ownership, and the relationship with the supplier are key. Reflect that the saying that ‘‘the world is your plating line’’ is essentially true. It may be the case that there are more graduates in the PCB industry in Taiwan than any other country, but some technologies are best sourced in Europe. He added that both Central and South American countries are coming on stream. How to buy? – there are several routes – direct from manufacturer, or through a local PCB broker; through an Asian PCB broker; through a component supplier, through an EMS company or though a local manufacturer? All are important considerations, the broker brings lots of benefits, especially good service, but charges for it (and rightly so). The Asian broker may be lower in cost but offers a more detached service. As for an EMS company it depends on what they know, but using them could add to the cost of ownership of the board. Remember that local PCB shops have partners in Asia, and some times have a brokering business attached to them viz. Merlin Circuit Technology and Kestrel PCB Services. You do need to consider the solution to the volumes you want, the spend you have and the special features which are definitely needed. Under the heading Who to buy from? Phil said that with whomever you were going to buy from you needed to build a relationship. If the source was Asia, go there and meet the people. Plenty of people have gone to Hong Kong expecting to find a large state-of-the-art PCB shop and have found a grubby office in a high rise in Kowloon instead. Do bear in mind that if you want to buy in Asia the start-up costs might run to some $20,000. You could save that money and work with a UK company. Summing up the need to take care of things such as the business; relationships, contracts; currencies; getting the engineering right; he said you need to make sure you are important to your supplier, it is a dangerous business out there! We then had a second and welcome session with Pete Starkey – who talked about bare board reliability issues in lead-free assembly. The bareboard reliability issues arise during assembly and during fabrication and concern the effects of leadfree soldering on substrates, with interconnections and with temperatures running at 308 higher than with lead-containing solders. Pete discussed the subject of thermal stability of the laminate, the Tg, and with FR4 the predominant material, explained FR4 and its performance characteristics, and he moved seamlessly on to a look at solderable finishes. He stated that electroless-nickel/ immersion gold (ENIG) would tolerate the higher reflow temperatures, and should soon be 24 per cent of the world finish market. Of the others, immersion tin would account for about 5 per cent of the market, with HASL taking

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28 per cent. Legislation may limit the use of immersion tin, whilst the solderability of immersion tin is good the higher reflow temperatures will accelerate the ageing of OCVSP finishes. Prior to lunch, Paul Watson, Sales Director, and Jeremy Bacon, Export Sales Manager took the delegates on a tour of the CEMCO facility. CEMCO are to hot air solder levelling what Judy is to Punch, so they were just the people to confirm to the visitors that their experiences with lead-free had been entirely happy, and that leadfree solders were being used as a matter of course in both their Quicksilver vertical and Lynx horizontal solder levelling systems. Feed the inner man and you have contentment. CEMCO’s hospitality is legendary and the magnificent buffet lunch ensured that a very full but happy assembly sat down afterwards to listen to Bob Willis, who looked at board types and their finishes. Of the finishes currently being applied, gold was 60 per cent ENIG was 30 per cent with tin and HASL taking up the slack. There were no major problems with stencil printing of lead-free solders, even with finer and finer pitches if the board build quality is up to the mark then some of the horror stories about leadfree are groundless. The impact of lead-free on solder finishes was discussed, the thickness of copper plating must be sound. The process must be controlled if fillet lifting and fillet tearing is to be avoided. After tea, it was back to Bob Willis and the subject of initial supplier audit requirements. This was essentially a package of information, starting with general information on the company, and a list of the production equipment and capability for the products being proposed for fabrication. You need to procure a sample batch – assess the quality of samples to relevant standards – and produce a report to compare supplier’s strengths and weaknesses. So often it is a measure of how a supplier reacts when something goes wrong, which sorts out the men from the boys. Plate 2 shows from left to right, Bob Willis, Phil Stoten Dennis Price and Pete Starkey. About three times as many Contract Manufacturers, assemblers, and design companies as had been expected came to Waterlooville for an excellent and varied SMART group Seminar held in the premises of CEMCO. In the field of lead-free the SMART Group have no peer when it comes to information dissemination, but here was a familiar theme placed in a practical environment and with complimentary contributions from three experts. A quality event, attended by the fortunate.

European LEADOUT Project – Bob Willis, SMART Group

Plate 2 Left to right: Bob Willis, Phil Stoten, Dennis Price and Pete Starkey

Solder joint reliability

Essentially an update from Bob Willis, Technical Director of SMART Group; he reminded the delegates of the 6th Framework Programme – covering low cost lead-free soldering technology to improve competitiveness of European SME. This is technical support for benchmarking, for joint reliability, for best practice guides, for assessment of the benefits of nitrogen processing, and for failure analysis. The programme involves several companies, and no less than 12 industry associations. Angus Westwater of Rohm Electronics talked about how you control your components and discussed the impact of lead-free on component. Rohm Electronics are developing a lead-free roadmap, showing the transition to lead-free for components, with a cut-off date. He explained that the route can be easily managed, and how potential leaded component scrap is reduced or eliminated. But, he concluded, a lead-free road map must be implemented by anyone involved with component assembly NOW! Chris Hunt of the NPL warned of the potential pitfalls on the path to lead-free, such as component suitability – there were concerns about softening of polymer mouldings, discoloration of LEDs. NPL had taken a look at the effect of lead-free soldering on LEDs, such effects including discoloration, melting of leg finishes. On polyester capacitors of wound construction could be problematic, temperatures of 2158C led to physical deterioration. With electrolytic capacitors, the extra heat needed for lead-free extra distorts the base, and there is a function loss on polyester capacitors due to high temperatures. With BGAs NPL were worried about out gassing of moisture, and possibly some delamination inside the component. You do need to watch out for components retaining their integrity.

Component finishes Lead-free finishes gave acceptable results for solderability, process yields, moisture ingression, plating ductility – tin whiskers can either be solid, perforated or hollow, they can be straight but can come off in different directions, and he showed some typical examples. Some devices nearing the end of their product life may not be converted to lead-free, cutting short their availability.

SAC is the main alternative alloy to SnPb. But you do need to make comparisons, and global strain around component through thermal coefficient of expansion (TCE) mismatch is one of them; leadfree solder must be able to absorb global strain. Of all the lead-free solders, SAC gives the highest reliability in solder joint strains. For high strain tin/lead is better, for lower strain rate SAC is better. As you will not be able to use tin/lead, use bismuth on the alloy that is better for higher strains. Lead contamination. NPL had looked at leadfree joint failure due to stress through thermal cycling, with SAC this had been in secondary reflow due to the LMP phase, and NPL are looking at this cause of failure.

There is quick test for lead, by the way, using a special pencil containing sodium rhodizonate. Another potential problem with lead-free solder is the formation of Conductive Anodic Filaments Martin Allison of Senju Manufacturing (Europe) looked at the status of lead-free manufacturing in Japan and compared it to leadfree manufacturing in mainland Europe. Japan have various laws in place for the restriction of lead in solder and recycling, and their Road Map is JEITA 2002. They started with components, which will be lead-free by the end of 2004. Equipment will be using lead-free solder from 2003 and they will be totally lead-free in Japan by 2005. Solder alloys being used now are SAC 87 per cent, SnAg 7 per cent, SnAgBi 2 per cent for TV. Wave soldering is using 67 per cent SAC, 22 per cent SnCu, 7 per cent SnAgBi, BGA reflow is all lead-free. In Europe, Matsushita are now lead-free, Fujitsu in Spain will be lead-free by 2004. Pioneer and Sharp aim for complete changeover by 2004 throughout Europe, Sony in Hungary, Spain and the UK are going lead-free by 2004. Hitachi will complete their move to lead-free in Europe by 2004. Sanyo and Canon already have products that are lead-free. A look at non-Japanese companies in Europe and Scandinavia showed that in Norway there were trials under way; in Sweden there were some production and trials in medial and communication and automotive products. In Finland trials were taking place in communications, and automotive and security electronics, Estonia was heavily lead-free. In Hungary, Epson are now lead-free. Germany is being a bit slow off the mark, but Italy has moved to lead-free in communications, and is trialling in other areas. France is at the trial stage for all fields, Portugal is trialling in the automotive and car hi-fi areas. In Spain, subcontractors to Japanese OEMs are already lead-free, and trials are taking place in white goods, automotive, CEMs, components, in Europe, as in Japan, SAC predominates for wave, reflow and BGA soldering. Answering a question on costs, Martin said that lead-free is more expensive. Bob Willis wondered what it would take to get the UK industry moving over to lead-free? A mad panic?! He commented that the supply chain in the UK is a circle that has to be broken somewhere and he was surprised at the attitude of the UK SMT engineers towards lead-free. For further information, visit the Web site: www.smartgroup.org/leadfree2004/name.pdf John Ling Associate Editor

New products New lead-free solder pastes from Agmet Keywords Lead-free soldering, Solder paste Agmet Limited, based in Reading, Berkshire, and part of the ESL Group, have just introduced a new

range of lead-free solder pastes under the EnviroFloe label. This is a Sn/Sa/Cu alloy with a 2178C eutectic. It is compatible with most of the commercially available coatings to be found on both components and PCBs. These include ENIG, OSP, Bare Cu, PD/NI and conventional Sn/PB coatings. For further information, visit the Web site: www.solderpaste.co.uk

superior protection where rugged conditions are the rule. For further information, visit the Web site: www.intertronics.co.uk

New DYMAX electronics encapsulant is ultraflexible

Keywords Reflow, Corrosion, Printed circuit boards

Keywords Encapsulation, Encapsulant materials, Electronics Curing in seconds upon exposure to UV/visible light, DYMAX 9008 encapsulant from INTERTRONICS exhibits excellent adhesion to polyimide, enduring bending and flexing even at extremes of thermal cycling to 208C. The cured coating forms a transparent layer which protects components and leads from moisture, dust and other contaminants. DYMAX 9008 is formulated to dispense consistently through precision dispensing systems. Controlled placement optimises the process and minimises resin consumption. The flow characteristics of DYMAX 9008 are designed to assure coverage of leads of even large surface mount components, without running to areas where protection is not needed (Plate 1). 9008 flexible coating cures in 10-30 s under standard longwave, moderate or high intensity lights (200-1200 mW/cm). The length of exposure depends upon the light used and thickness of the coating. However, thicknesses to 1.5 mm can be cured in UV conveyor belts at speeds of 60-20 cm per minute or under spot lamps in a few seconds. Cure depths to 6.5 mm are possible. Like other DYMAX coatings, 9008 is a tough, durable resin with excellent electrical properties. It has high ionic purity as well as the ability to withstand harsh environmental conditions. Coatings form protective surfaces and exhibit adhesion to a wide variety of surfaces including glass-filled epoxy, metal and ceramic surfaces as well as polyimide and other flex materials. Because 9008 is highly flexible – even at very low temperatures – the encapsulant provides Plate 1 The DYMAX 9008 encapsulant

McDry prevents micro-cracking in ICs

McDry, a new range of drying-cabinets developed by Seika Sangyo GmbH are available exclusively in the UK and Ireland from Contax, the UK’s leading independent supplier of automated production machines. Virtually 100 percent of IC packages containing moisture have a problem with micro-cracking during the Reflow process. This results in the corrosion of printed circuits and can cause wiring breakage and many other problems. This can be prevented by storing and dehumidifying ICs using the new McDry cabinet. Available in a wide range of sizes, McDry offers ultra low humidity storage of sensitive surface mount devices as specified by ‘‘Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices’’, IPC/JEDEC J-STD-033a (July 2002). Storing the ICs in McDry completely eliminates the risk of micro-cracking and can be used as an alternative to baking. The cabinets are nitrogen-free, instead relying on a powerful zeolite desiccant which is automatically recycled and does not need replacement. Using McDry, ICs can be stored safely both before and after mounting, so ensuring complete product integrity.

DEK expands next-generation stencil technology development Keywords DEK, Stencil DEK’s Eform stencil manufacturing process has taken electroform stencils to the next level by incorporating an exclusive, sophisticated aperture height control method to their production of Eform stencils. DEK’s Eform stencils ensure seal contact to the pad(s), pad paste deposit and a greater percentage volume of paste on pad. The reactive force created by DEK Eform stencils provides for an even distribution of paste and allows for a more clean release of paste from the aperture. This technology also delivers ultimate control over stencil thickness and uniformity, ensuring outstanding paste volume consistency for fine pitch applications. As the electronics industry moves even closer to the reality of lead-free manufacturing, DEK Eform stencils will become a necessity, as they improve solder paste release for some of the more challenging lead-free solder paste formulations. But, when DEK’s Eform stencil process is combined with its innovative new technology, termed variable aperture height technology

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(VAHT), it becomes even more powerful. As Richard Tang, DEK global Eform manager, explains, ‘‘Board co-planarity issues are a prevalent problem. The uneven resist layer causes a poor seal between the board and the stencil, which can result in printing problems. DEK has that problem solved. The Variable Aperture Height Technology (VAHT), an inherent characteristic of DEK’s Eform stencils, adjusts for the variances in resist layer heights and provides a uniform seal across the entire board’’. This powerful combination of technologies – Eform stencils with VAHT – results in superior paste printing. For further information, visit the Web site: www.dek.com

Two station system delivers powerful and efficient fume extraction Keyword Fume extractors Metcal, a division of OK International, has introduced a compact and truly portable two-arm fume extraction system that combines strong fan performance with efficient filtration and quiet, flexible operation. Metcal enlisted the fume extraction expertise of Impell, another OK International division, to develop the BVX-200 fume extraction system. The stylish BVX-200 builds on the success of Metcal’s existing BVX-100 single arm system. The new unit features the same motor as the single-armed model, but it has an innovative onestage impeller design that provides more than double the total free-blowing airflow. A proprietary impeller was chosen over an offthe-shelf design to maximise performance while keeping the size and weight to a minimum. The result is a truly portable unit that can be easily transported by one person without the strain induced by larger units. Maximum free-blowing airflow is rated at 250 m3/h, with maximum suction force at 850 Pa. This is the best suction rating in the unit’s class and the highest offered by such a compact and portable system. The 850 Pa rating provides ample capability in reserve to handle any clogging that occurs during normal filter life. The unit is compact enough to be located under, or next to, the workbench. It has been designed specifically to be located off the benchtop to maximise the available working area without obstructing the space underneath. It can be used with either two 2 in. (50 mm) diameter hoses and BVX arms, or one 2.5 in. (67 mm) hose and an Omniflex arm. The single arm offers a 50 percent higher airflow than one of the smaller arms, with airflows per arm rated at 75 and 110 m3/h, respectively. For further information, visit the Web site: www.metcal.co.uk

New vacuum pickup Keywords Intertronics, Vacuum Intertronics has announced the new Fisnar VPP511-110 bench vacuum pickup system – an

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essential tool for handling delicate components in fine placement, rework, dispensing and soldering work. This compact, industrial-strength, high power system is controlled by foot switch to facilitate accurate positioning, not always easy with fingertip control when placing a surface mount component or other miniature device. The VPP511-110 is supplied complete with a full range of vacuum cups and tips. For further information, visit the Web site: www.intertronics.co.uk

New CT-50 System for 2D and 3D X-ray Inspection Keywords X-ray, Inspection The new CT-50 X-ray inspection system from FEINFOCUS combines high-power microfocus 2D X-ray technology with state-of-the-art 3D Computed Tomography techniques and high-end volume rendering software. It performs the detailed inspection and analysis of complex mechanical and electro-mechanical devices in the 3rd dimension (Plate 2). Combining the flexibility, functionality, and ergonomics of a standard microfocus X-ray system with the ability to generate 3D imagery, the CT50 system visualizes the most inner components and precise structural modeling of a device. Cracks, voids, and other crucial anomalies can now be depicted in their actual 3D position, providing valuable insight into the design and manufacturing processes of these devices. This ability makes the new CT-50 system ideally suited for typical NDT and complex electromechanical component inspection applications in automotive, avionics, castings, and other industries. The system comes with a 200 kV directional tube featuring two X-ray modes (microfocus and high-power) with an actual X-ray intensity output up to 100 W. Proprietary FEINFOCUS TXI (True X-ray intensity) Control constantly controls the output level of X-ray intensity during the image acquisition process, guaranteeing stable and permanent image quality time after time. The system manipulator is precise yet rugged for heavy samples up to 30 kg. It features five-axes, Plate 2 The CT-50 System for 2D and 3D X-ray inspection

plus two additional high-precision CT axes. The standard system manipulator is well suited for CT scans of bigger parts and smaller geometric magnification requirements, whereas the additional high-precision unit is ideal for extremely high magnifications and smaller samples. All manipulator movements and inspection processes can be saved and rerun via CNC. The system is ideal for manufacturers with a very different inspection requirements ranging from larger samples, such as castings, to smaller and more complex samples that need to be imaged at higher magnifications. Designed in the interest of rapid prototyping and reverse engineering requirements, it comes with a multi-processor based computer system for fast image reconstruction, the latest FGUI (FEINFOCUS Graphical User Interface) version 2.2 that includes a versatile image processing system, easy configuration of automated processes for serial inspection, and standard network capability. An ergonomic operation console can be positioned adjacent to the large loading door and viewing window and adjusted to the user’s specific requirements. For further information, visit the Web site: www.feinfocus.de

Highly-polished squeegees boost leadfree paste performance Keywords Lead-free soldering, Solder paste Printed circuit board producers are again set to benefit significantly from advanced manufacturing techniques introduced by Dorset based specialist, Tecan, as part of its ongoing initiative to deliver lead-free manufacturing solutions. The company has now developed a range of ‘‘highly-polished’’ squeegee blades that outperform traditional blades. They offer advantages such as true compatibility with leadfree pastes, optimised aperture fill and pasteconditioning characteristics that extend print life. Highly-polished electroformed squeegee blades have been developed to address the rheology problems associated with less dense lead-free and ‘‘no-clean’’ pastes. Effectively, these pastes have a tendency to ‘‘cling’’ to a conventional unpolished blade resulting in ‘‘paste hang-up’’ at the end of the print stroke, thereby reducing the paste bead on subsequent print strokes. The new squeegees deliver a proven solution to all these problems and are particularly beneficial for mixed-component and fine-pitch applications, allowing manufacturers to achieve the most consistent and repeatable performance possible from existing printing machines. The improved ‘‘paste-roll’’ characteristics aided by reduced surface tension also extend the printing life of the paste. Furthermore, successful printing can only be achieved with the selection of the most appropriate stencil, solder paste and paste delivery system, says the company. To achieve the best results, the blades should also possess flexibility to consistently deliver the expected paste volumes. To this end, Tecan has developed ‘‘reactive’’ metal squeegee blades with a mobile ‘‘feathered’’ edge. These durable reactive blades have been tested against a range of single thickness metal blades,

coated metal blades and traditional polyurethane materials. In the tests they were proved to provide significant improvements to printed results, when used with either simple single thickness stencils or multi-level stencils featuring both raised and recessed areas. These mobile-edge squeegees enhance the performance of today’s printers by delivering repeatable results, which match the demands of fine pitch printing. They also provide the solution to the problems of scooping or scavenging that polyurethane squeegees create with larger apertures. The mobile edge allows the blade to flex locally, to overcome uneven surfaces such as proud via holes, thicker tracks and poor silkscreening – recovering quickly to deliver clean consistent printed results. This provides significantly better and more accurately defined deposit formations increased process control and improved product quality. The blades are an effective solution for printers that use trailing edge squeegees. They can either be positioned in front of an existing polyurethane squeegee, where the metal edge becomes the printing edge, or, used as a direct replacement for polyurethane squeegees where the holder permits. For further information, visit the Web site: www.tecan.co.uk

Asymtek introduces the DispenseMatew 550 benchtop dispensing system Keywords Asymtek, Dispensing Asymtek has introduced its newest compact dis pensing system, the DispenseMatew 550 series (Plate 3). The powerful benchtop unit offers advanced capability with a small footprint. Ideal for many batch dispensing operations including potting, gasketing, solder paste and adhesive Plate 3 The DispenseMatew 550 benchtop dispensing system from Asymtek

dispensing, the DispenseMate 550 features a precision motion system with closed-loop brushless DC motors. It also features control for Asymtek’s pumps and valves, digital gages for precise fluid delivery and ease of setup, and an optional vision system. The system utilises Asymtek’s FluidMovew for Windows NT (FmNT) software, the same industry-proven software package used on all Asymtek dispensing systems. FmNT and DispenseMate’s flexible architecture makes it easy for customers to upgrade as needed, and provides the portability to develop programs offline that can be transferred to other sites or moved to in-line systems. CAD Import software and Automatic Pattern Recognition are also available. Two models of the DispenseMate 550 Series are available with different dispensing areas. The 555 model has a dispense area of 525 525 mm, or 20.7 20.7 in. The DispenseMate 553’s dispense area is 325 325, or 12.8 12.8 in. Configured with the DJ-9000 Dispense-Jetw, the DispenseMate offers the latest, most advanced dispensing technology in a cost-effective system. (At press time, the unit jets more than 20,000 dph.) For further information, visit the Web site: www.asymtek.com.

Robot provides economical automation for dispensing or pick and place Keywords Robots, Dispensing, Automation, Intertronics The Fisnar TMB100 from INTERTRONICS is an economical but fully featured solution for robotic dispensing or pick and place operations in conveyor or rotary work cell applications (Plate 4). The system has an actual working area of 400 mm 380 mm, either left or right handed. Programming features high level, easily understood, step-by-step instructions, and the Plate 4 The Fisnar TMB100

software is available for fluid dispensing or pick and place. The TMB100 is controlled by closed looped encoder and includes several input-output functions for communication with other systems. A Windows editing program enables editing and conversion of CAD co-ordinates. The robot is available in three or four axis configuration. For further information, visit the Web site: www.intertronics.co.uk

Universal consolidates line optimisation software onto two modules Keyword Universal Instruments Universal Instruments has simplified implementation of its Dimensions line management tools by announcing a radically new Dimensions configuration, a simplified user interface, and a roadmap of future automatic features to reduce the workload for operators and production managers. By consolidating the line control and line programming functions of the original Dimensions suite, the tool-set is now hosted on two optional boxes consisting of hardware and software that support line control and line programming functions. The Line Control box consolidates the line control features of Dimensions software, and adds new features to minimize changeover time and track consumption information per line. The Line Control box also provides a new user interface that is both easier to use and allows the line to be controlled from the screen of any machine, enhancing utilization. The Line Programming box supports offline programming and optimisation of the line and also hosts the Dimensions product and component library management functions. Data management functions are included in each module to facilitate interpretation and use of machine data, including remote access via a network connection. One or both boxes may be fitted, according to customer requirements. ‘‘This new configuration, combined with current and future feature enhancements, makes Dimensions an even more powerful tool for customers seeking to get more from their machines and lines,’’ said Peter Bologna, Director of GSM Platform Products. ‘‘The new Line Control and Line Programming boxes make Dimensions easier to use and install, and make training faster and easier’’. Further enhancements will include autovalidation and auto-programming capabilities, based on Universal’s intelligent PrecisionPro feeders that are capable of identifying themselves to the machine. Auto validation will enable the machine to automatically detect and identify feeders, using the data gained to validate each component type. Auto programming will automatically list feeders to be added when a new product is setup. In early 2004, the Dimensions suite will add these and several other features to aid in change over, production, programming and data management. Later in the year, Universal will add consumption monitoring as well as feeder and reel management.

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For further information, visit the Web site: www.uic.com

Plate 5 The Fisnar RT-FLEX11-Z rotary dispensing table

New safewash from Electrolube

Keywords Glass, Printed circuit boards

Keywords Printed circuit boards, Cleaning Safewash is a high-powered, water-based PCB, stencil and electronic assembly cleaning range developed by electro-chemical manufacturer Electrolube. Formulated to rapidly remove the most hardened adhesive, paste, flux, dirt and grease deposits, it enables swift, effective and cost-effective cleaning with reduced wastage and long-term reliability. The performance of the multi-purpose cleaner has been comprehensively verified by a number of major international electronics manufacturers. Residue-free, Safewash contains no CFCs and has a low-foam, low VOC formula with a low odour. It is also non-flammable, biodegradable and environmentally friendly, while its chemistry also prevents the build up of inorganic deposits in machinery pipework. Using the Safewash range, cleaning and drying process times can easily be optimised to ensure swift production throughput. The most recent additions to the range are Safewash Mechanical (SWMN) and Safewash Mechanical Plus (SWMP), designed specifically as a replacement for the toxic and highly hazardous solvents found in other degreasers on the market and providing excellent results without compromising on cleaning quality. SWMP is also ideal where a low foaming product is required for in-line, pressure and dishwasher applications. It contains a corrosion inhibitor to allow safe cleaning of sensitive metals and quickly and easily removes all flux types, pastes and greases. Safewash Extra (SWAX) is suitable for use with both solder paste and surface mount adhesives, and can be used on all types of screens, stencils, PCBs, frames and accessories in spray and in-line immersion cleaning machines. SWAX has been approved on most leading brands of solder paste and adhesives in a range of ultrasonic and pressure wash automated cleaning systems, and a complete cleaning cycle, including rinse and dry, can take as little as 13 min. Safewash Super (SWAS), tackles very stubborn flux residues and no-clean fluxes, the latter being very difficult to remove. Designed for use in ultrasonic tanks, SWAS will also tackle heavy greases. This inhibited version will not attack sensitive metals and rinses off easily. Further information on Electrolube and its products can be found at the Web site: www.electrolube.com

New rotary dispensing table Keywords Dispensing, Intertronics The Fisnar RT-FLEX11-Z rotary dispensing table from INTERTRONICS provides accurate, easy-touse dispensing on to circular objects (Plate 5). An adjustable pneumatic z-axis can be inclined to dispense at an angle as the working

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Morgan advanced ceramics offers pressed glass spacers for circuit board applications

part rotates. Objects up to 380 mm can be accommodated on either side of the system. Correct bead size and finish are ensured by the use of simple yet comprehensive controls. The Fisnar DSP501A metering system can be neatly housed within the table for easy access. Dispense and rotation delays are easily programmed, together with automatic cycling and speed control. The system is actuated either by foot pedal or safe two-hand operation. The RT-FLEX11-Z is ideal for circular dispense operations including speaker coils and sealing. For further information, visit the Web site: www.intertronics.co.uk

¨ PEL FEINFOCUS and GO join to launch new combined AOI/AXI system ¨ PEL have combined their FEINFOCUS and GO 30 years of expertise in the field of test and inspection with a recent technology partnership. The new cooperation and development project has resulted in the launch of the OptiCon X-Line inspection system, which was unveiled at Productronica 2003. The new system combines high-performance AOI and X-ray inspection technology for the automated analysis of hidden solder joints. The OptiCon X-Line, based on the popular ¨ PEL, provides automatic OptiCon series from GO recognition of shorts and solder bridges as well as missing solder balls on BGA and BGA devices. FEINFOCUS contributed to the development of the system with innovative X-ray tube technology that was implemented ¨ PEL’s specifications. The according to GO companies will publish joint technical papers and application findings through the use of the combined technologies. For further information, visit the Web site: www.feinfocus.com

Pressed glass spacers used to position and isolate electrically sensitive components such as capacitors and varistors during wave soldering are available from Morgan Advanced Ceramics. Manufactured by the company’s GBC Products Division, the glass spacers are ideal for highreliability printed circuit boards found in a wide variety of electronics, including wireless electronic devices. Unlike plastics, pressed glass spacers can withstand high temperatures providing a low-cost solution for printed circuit board applications. Available in standard sizes including lengths ranging from 0.63 to 6.35 mm, outer diameters from 1.77 to 3.94 mm, and inner diameters from 0.66 to 1.60 mm, the standard tolerance on all dimensions is +0.05 mm. The pressed glass spacers can be tooled to meet specific application requirements and are manufactured in an array of colours, including green, blue, black and white. For further information, visit the Web site: www.morganadvancedceramics.com

Metcal introduces the PS-800 soldering system Keywords Metcal, Soldering With the introduction of the PS-800 Soldering System, the Metcal division of OK International has made the most significant change in hand soldering since the introduction of their patented SmartHeatw technology two decades back. The PS-800 Soldering System revolutionises hand soldering by combining the power and process control advantages of SmartHeatw, with the system quality and innovative design of vintage Metcal irons, at a price that is under e250 (Plate 6). Historically, Metcal has redefined soldering performance and now they have significantly Plate 6 The PS-800 soldering system revolutionises hand soldering by combining the power and process control advantages of SmartHeatw, with the system quality and innovative design of vintage Metcal irons, at the price that is under e250

shifted the price/performance ratio. The PS-800 Soldering System delivers the industry standard thermal performance of Smartheat@, with a compact power supply that fits on or under the bench. However, small size and low cost belie the full capabilities of the PS-800 Soldering System. The system is pure Metcal, featuring variable power/ fixed temperature control in an iron that requires no calibration. Cost of ownership is minimal, as the PS-800 Soldering System uses replaceable heater tips rather than cartridges. The unique Metcal twopiece design separates the heater coil from the tip. The long-life heater coil remains in the handle, while replaceable tips that contain the heater itself, are easily removed and replaced. Most importantly, the cost of the heater tips is comparable to that of conventional tips. Metcal has developed a range of 33 soldering tip geometries for the PS-800, each available in a wide range of temperatures. In addition, enhancements to SmartHeat@ technology have allowed Metcal to employ an increased plating thickness for extended heater tip life, without reducing thermal performance. Designed to be the perfect, compact soldering system for repetitive manual assembly and touchup, the PS-800 Soldering System incorporates an innovative, compact power supply that fits on or under the bench. For further information, visit the Web site: www.metcal.com

New precision 50 ml twin-pack cartridge dispenser Keyword Intertronics Accurate and repeatable dispensing of small shots of two-part materials from 50 ml twin cartridges is often hampered by material drooling after the shot cycle, resulting in waste and clean up. It is also difficult to control shot size using pneumatic or manual cartridge guns. The Fisnar I&J123-D50 from INTERTRONICS eliminates these problems. A stepping motor drive is coupled by a Hydro-Linkw to a double contactram that enters both barrels of the cartridge. A built-in PALMw computer controls the dispense setup, with a graphical display indicating when the cartridge is empty. Shot sizes of 0.002 cc are possible, with the stepping motor mechanically forcing the material through the mixing nozzle in precise steps, achieving an accurate deposit. The system can also be used with any three-axis Fisnar robot for automatic dispensing of beads or single shots from 50 ml cartridges. For further information, visit the Web site: www.intertronics.co.uk

New gantry power dispensing robots

Plate 7 The Fisnar I&J9000 Power series

The Fisnar I&J9000 Power series – ideal for use for conveyorised processes requiring a gantry robot – are also competitively priced for bench applications that require XYZ movement above the work. They feature high repeatability due to the use of ball screw transmissions. The robots are available in three or four axis configurations and are fully interpolated in all axes. Programming is by easy to learn teach pendant. For further information, visit the Web site: www.intertronics.co.uk

New MPM@ Gel-FlexTM Tooling available exclusively from Contax Speedline Technologies’ new Gel-FlexTM Tooling, a revolutionary, new MPM@ conformal board support system, is now available in the UK, Ireland and Benelux exclusively from Contax. The new Gel-Flex tooling approach is far easier to use and costs less than traditional board support options, including manually set pins, clamps, custom work holders, and fixed-grid pin tooling systems. In addition, Gel-Flex significantly reduces both initial set-up and board changeover times, particularly for boards with bottom-side components, and will not damage components or leads. ‘‘The beauty of this new gel tooling concept lies in its simplicity. Since it does not incorporate pins, there is no reason to be concerned about the location of components or leads on the bottom sides ofboards. Gel-Flex uses compressible polyurethane gel support for gentle compliance for components, while providing firm support for the board itself,’’ comments Mike Rapson, Director, PCB Products at Contax Ltd. ‘‘The only decision to be made during product set-up is to ensure that support blocks are spread consistently across the board, reducing board set-up and product changeover times to seconds, not minutes.’’ For further information, contact: E-mail: [email protected]

set-up and changeover times to minutes rather than hours and removes the human element from the process to make high-end repairs as simple as pressing a button. Version 3.21 of its ThermoActive software is intelligent enough to handle changes in both board and device type automatically without the need for teaching modes or expensive operator training (Plate 8). The software is designed to be as easy as possible to use and is rooted in the company’s philosophy of providing inline process quality for the offline rework process. It allows BGAs and other complex devices to be removed and reworked with the user-simplicity associated with hand tools, but the process control and capability of high-end, fully capable rework stations. A key feature of the latest ThermoActive release is its time and temperature modes for configuring soldering profiles. Together with accurate real-time feedback of board and device temperatures from the rework station, these modes allow the process to run fully automatic without the aid of a skilled technician. The package is designed for use with PDR’s X410 BGA and SMT Rework Station; a tool-free, gas-free system based on the company’s patented Focused IR technology. In essence, the software controls the process while the X410 provides efficient lower and upper side heating plus the vital temperature feedback data. The time and temperature modes allow each zone in a temperature profile to be defined as either reaching a specific temperature or running for a set length of time. For example, a typical soldering profile might feature two preheat zones, a temperature soak, reflow spike and cooling. The ThermoActive software reproduces such profiles using temperature mode to set target temperatures for each of the two preheat zones, followed by time mode to hold at the set soak temperature, then temperature mode to reach the solder melting point, and finally time mode again to control the reflow dwell and cooling periods. During each phase, the actual board and device temperatures are monitored by non-contact sensors on the X410 and fed back to the software so that any profile can be closely followed in the most accurate and efficient way. Besides simplifying rework batch runs, this approach also means that changeovers can be handled automatically without the need to change tools or run the system through a teaching mode for the new set-up, both of which require the skills of trained personnel. Plate 8 New rework control software from PDR, has effectively reduced set up and changeover times to zero – making precision rework as simple as pushing a button

Intelligent Software turns rework into child’s play

Keywords Intertronics, Robots New from INTERTRONICs is a range of high power, servo driven, gantry style Cartesian dispensing robots with working areas up to 812 610 mm (Plate 7).

Keywords Ball grid array, Process control, Software Innovative new software from PDR, the infrared rework technology specialist, reduces rework

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When work is required on a different device, the operator simply has to adjust the infrared beam’s spot size to cover the new device and press the start button for the system to take over and react to the new set up. Similarly, different board types are handled automatically, as the system recognises the different heating rates of larger or smaller masses and adjusts accordingly. And it also copes easily with both tin-lead and lead-free solders, where the only change required is to set the upper temperature limit higher to take into account the higher melting point of lead-free solders. Whatever the combination of board, device or material technology used, PDR’s ThermoActive software provides a simple and effective solution for delivering precision rework and high end yields. For further information, visit the Web site: www.pdr-smt.com

Asymtek introduces four-position ‘‘Tilt’’ accessory for conformal coating applications Keywords Asymtek, Conformal coatings Asymtek has released its new four-position Tilt accessory, available exclusively on the award winning SC-300 Swirl Coate applicator. The Tilt option provides coating access in areas not accessible from the standard vertical approach. Ideal for applying conformal coating to component sides or underneath parts on a printed circuit board, the mechanism tilts the SC-300 applicator in four positions: 308 from vertical to the left, right, front or back. Tilt is controlled by Asymtek’s Easy Coatw for Windows NTw software, and can be retrofitted to existing Century conformal coating systems (Plate 9). Plate 9 The new four-position Tilt accessory from Asymtek

Asymtek’s SC-300 Swirl Coat applicator operates in three modes for optimum flexibility and control: bead, monofilament and swirl. Mean Time Between Assist (MTBA) is significantly improved by minimizing material build up at the zero cavity nozzle. If necessary, a periodic clean up routine can be easily added to the coating program. The SC-300 offers high performance and easy maintenance for coating applications that utilize today’s solvent-less (100 percent-solids) formulations, and coatings with greater than 100 cps. It can also be used with low viscosity film coating materials. For further information, visit the Web site: www.asymtek.com.

Universal expands highspeed placement range Keywords Universal Instruments, Placement Universal Instruments has trimmed the footprint and increased the maximum board size for its high speed placement platform. The result is more flexibility in a smaller shop-floor space. And because the new 4797R HSP accepts up to 96 feeders, these advantages are not achieved at the expense of lower throughput or complicated scheduling. Placement speed is maintained at 48,000 cph (Plate 10). The 4797R HSP is capable of handling boards up to 610 mm (24 in.) length 460 mm (18 in.) width. Universal has achieved this within a small footprint machine measuring 3,100 mm (122 in.) long and 2,155 mm (84.8 in.) deep. Besides maximizing throughput and flexibility, the new machine also emphasizes placement accuracy. Three-sigma accuracy is 0.08 mm for MELFs and small chips, and 0.05 mm for leaded components. ‘‘Today’s OEM, EMS, and ODM businesses insist that every inch of the shop floor should deliver maximum productivity,’’ said Heinz Dommel, Systems Manager of Universal Instruments. ‘‘But the flexibility to run high-value products such as backplanes opens up profitable opportunities. The 4797R HSP combines outstanding flexibility and Plate 10 The new 4797R HSP from Universal Instruments has smaller footprints and an increased maximum board size delivering more flexibility in a smaller shop-floor space

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space-efficiency, without compromising on throughput or accuracy’’. This is the most compact 4797-series HSP machine to feature large board handling capability. Accepting up to 72 unique components on standard 8 mm tape feeders, or 96 unique components with dual-track feeders, the 4797R HSP balances small footprint, easy scheduling, and high throughput. As well as 48,000 cph placement performance, the 4797R HSP has a minimum placement tact time of 0.075 s. Feeder axis tact time is 0.09, or 0.08 s with the dual-track feeder. The new 4797R HSP can operate as a standalone machine, or grouped with multiple machines for increased flexibility and volume. It is ideal for assembling high volumes of standard products, as well as larger panels such as backplanes for networking or server applications, or PC motherboards. And its wide component range makes it equally productive in high mix environments. Additional standard equipment includes 12 five-spindle, advanced direct-drive placement heads, and Universal’s UCT53 software for offline programming. Available options include component library data teach, pattern program data teach, Barcode Validation System (BVS), traceability package, BGA/CSP recognition, black light PEC camera, and GEM/SECS II. For further information, visit our Web site: www.uic.com

Lead-free soldering Keyword Lead-free soldering books How will the European Directive banning the use of lead in electronic and electrical equipment impact your business? Have you the knowledge and information you need to meet the regulations? Do you know how to go about it, when you need to be lead-free and when you need to start preparing? Would you like some simple and straightfoward help? ‘‘A guide to lead-free soldering for assemblers and sub-contractors’’, written by Roger Bilham, a metallurgist with many years’ experience developing and making solder products, is a concise source of the information you need. Topics covered in its 48 pages include the following. . Legal position in Europe, USA and Japan. . Lead-free alloy requirements – technical and economic. . Problems posed by lead-free solders. . Melting temperatures. . Oxidation and corrosion. . Fillet lifting and cracking . Tombstoning. . Tin whiskers . Tin pest. . Potential and practical lead-free alloys with their properties. . High temperature, high lead solder – component internal connections, non-melting columns and balls, module assembly. . Patents. . Lead-free circuit board finishes. . Lead-free hot air solder levelling. . Components for lead-free soldering – temperature capabilities and terminations.

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Fluxes Mixed lead-free and lead-containing solders and finishes. Lead-free process challenges – cost, temperature, process window, machine issues, flux residues. Defects, inspection and quality. Repair and rework. Solder variety and standardisation. Use of nitrogen. Lead-free in the reflow process – temperature profile, machine implications. Lead-free in the wave process – composition changes, machine implications. Lead-free vapour phase soldering. Environmental and cost disadvantages of leadfree solders. Logistics of introducing lead-free solders. Sources of further information.

A Guide to Lead-Free Soldering is available, priced £35.00, as a PDF file by E-mail or on a CD from Roger Bilham. E-mail: [email protected]

Industry news Concoat Limited employee receives Electronics Award Keywords Concoat, Awards, Electronics Industry IPC recently honoured an employee of Concoat Limited, at its co-located IPC SMEMA Council’s APEXw/IPC Printed Circuits Expow/IPC Designers Summit exhibition and conference, held on 24-26 February in Anaheim, California (Plate 1).

Graham Naisbitt was awarded the IPC Distinguished Committee Service Award for his leadership and significant contributions in the development of IPC J-STD-004A, Requirements for Soldering Fluxes. This award is given to IPC committee members who have made an exceptional contribution to a specific standard, guideline, round robin test programme or other IPC programme.

Plate 2 To right: Nick Hoo, Manager Materials Technology Division of Tin Research and Keith Bryant, Dage X-ray Sales Manager outside the purpose built Technology Centre at the time of machine delivery

Dage X-ray and Tin Technology Ltd form strong bonds An agreement has been signed which lays the foundation for a close co-operation between Dage X-ray division and Tin Technology Ltd. The agreement includes purchase by Tin Technology of the latest Dage XiDAT X-ray imaging equipment. This will be located at Tin Technology’s new headquarters and laboratories situated at Curo Park near to St Albans (Plate 2). Tom Perrett, Tin Technology Marketing Manager said, ‘‘This is much more than simply buying an X-ray machine. After exhaustive evaluation of the marketplace we chose Dage as our partner. Not only is the XiDAT range of machines at the forefront of digital technology, easy to operate and very robust, but the company is extremely pro-active and an ideal partner for us to work with. Together we will co-operate to educate users and provide industry with a facility to demonstrate and evaluate the equipment’’. Adding ultra high resolution digital X-ray to its laboratory facilities gives Tin Technology a comprehensive range of test, measurement, and troubleshooting capabilities. These will be offered to customers through Tin Technology’s Soldertec network which provides extensive information and support to the electronics sector, particularly in the area of lead-free soldering implementation.

Plate 1 Graham Naisbitt received his award at a luncheon in Anaheim, during the recent APEX Exhibition. Graham Naisbitt is second in, on the left hand side

As part of the contract the companies will hold joint seminars and the new facility at Curo Park will act as a Dage XiDAT machine demonstration centre. Feedback from Tin Technology will be used as part of the Dage product development programme. For further information, visit the Web site: www.dagegroup.com

Asymtek receives Intel Award Keywords Asymtek, Awards Asymtek is a recipient of Intel Corporation’s prestigious 2003 Supplier Continuous Quality Improvement (SCQI) award, Intel’s highest honour for its suppliers, for outstanding commitment to quality and performance by suppliers that provide products and services deemed essential to Intel’s success. The company was given the award for its efforts in supplying Intel with automated fluid dispensing equipment. The SCQI awards are part of the Intel’s Supplier Continuous Quality Improvement process, which encourages Intel’s key suppliers to strive for excellence and continuous improvement. To quality for SCQI status, suppliers must score at least 95 percent on a report card that assesses performance and ability to meet cost, quality, availability, delivery, technology and responsiveness goals. Additional information about the SCQI program is available at the Web site: http://supplier.intel.com/quality/

DEK’s 100 percent Via Fill process wins Apex 2004 Innovative Technology Showcase Award Keywords IPC, DEK, Awards The IPC Association recently commended DEK’s technological advances with its new Via Fill process. Awarded a slot in the Innovative Technology Showcase at the Apex exhibition in Anaheim, California, DEK’s 100 percent fill technology was described by the judges as ‘‘groundbreaking’’.

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DEK representative comments, ‘‘Like most of our products, the Via Fill process was developed in response to customer requirements. We’re delighted that it has been recognised as cuttingedge technology by the IPC Association and believe that our broad-ranging customer base will continue to inspire further technological advances at DEK’’. As part of the Innovative Technology Showcase at Apex, DEK’s Via Fill process that delivers 100 percent fill of substrate vias with no voids and minimal surface residue, will demonstrate what the IPC describes as ‘‘new and emerging technologies’’. This Pro-Flow-based process offers solutions to problems such as insufficient fill, voiding, poor throughput and excessive handling of product associated with conventional methods. For further information, visit the Web site: www.dek.com

Xidat 6600 X-ray Service Announced Tin Technology Ltd has completed the installation of new state-of-the-art XiDAT 6600 X-ray Imaging equipment supplied by Dage Precision Industries. Technical staff have been fully trained and the company is offering the electronics industry hourly, half-day and full day pre-booked inspection time on the new equipment. The equipment will add to the capabilities of Tin Technology’s Soldertec group which provides a full range of technical, marketing, and information services to the global electronics sector. Soldertec is a leading authority on the implementation of lead-free soldering technology. This announcement follows an agreement signed between Dage X-ray division and Tin Technology Ltd which laid the foundations for close co-operation between the two organisations. The Curo Park site will also act as a Dage XiDAT machine demonstration centre, and site for future joint seminars. Feedback from Tin technology will be used as part of the Dage product development program. For further information contact: E-mail: [email protected]

Asymtek voted best in customer service Keywords Asymtek, Awards The technical support team from Asymtek, A Nordson Company, was awarded the Circuits Assembly Service Excellence Award at the IPC/ APEX tradeshow held last month in Anaheim, California. The awards honour key companies in the electronics industry that excel in technical service. Asymtek was selected best supplier in the dispensing equipment category, and received the highest cumulative scores based on customer satisfaction ratings in five areas: technology, dependability, responsiveness, ease-of-use, and value for the dollar (Plate 3). The scores are based on direct customer comments through a third-party survey conducted online. ‘‘Asymtek is honoured to earn the award based on our customers’ high standards

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Plate 3 The technical support team from Asymtek was awarded the Circuits Assembly Service Excellence Award

and we appreciate the effort put into the survey,’’ states Frank Murch, Asymtek’s Director of Technical Support. ‘‘Asymtek’s technical service team is committed to continual customer satisfaction, and welcomes feedback to ensure we are fulfilling their expectations.’’ Asymtek supplies award-winning automated fluid dispensing systems, specializing in semiconductor, surface mount, and electronics packaging applications. With over 20 years of experience, Asymtek is committed to providing innovative dispensing solutions and the best local support to customers worldwide. For more information, visit the Web site: www.asymtek.com

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Evaluation of hot-peel strength of Pbcontaminated LF joints. Applicability of Pb indicator kits for paints for recognition of Pb-containing components.

The work, lead by Martin Wickham, is already underway and results are expected in the next 12 months. Participating partners include: . Aeroflex International Ltd, . AMS Space UK, . BAE SYSTEMS (Operations) Limited, . Celestica Ltd, . Department of Trade and Industry, . Dolby Laboratories, Inc., . Eurotherm Ltd, . Goodrich Engine Control Systems, . Hansatech Group, . National Physical Laboratory, . Robert Bosch GmbH, . Rolls Royce Naval Marine, . TRW Automotive, . Thales Missile Electronics Ltd For more information please contact: Dr Chris Hunt, National Physical Laboratory, Teddington, Middlesex TW11 OLW. Tel: +44(0)20 8943 7027; Fax:+44(0)20 8614 0428; E-mail: chris.hunt@ npl.co.uk

DEK again voted top in customer service at Apex 2004 Keywords DEK, Awards

NPL leads project to investigate solder joint reliability during transition period to lead-free Keywords NPL, Lead-free soldering, Reliability During the run-up to the change over to lead-free (LF) solders by July 2006, a number of end-users have expressed concerns about the reliability of soldered joints formed by mixtures of tin-lead (SnPb) and lead-free materials. These will arise when lead-free components are soldered using SnPb alloys, something already happening in many production lines, and later when SnPb components are soldered with LF alloys. This latter issue may be a significant problem for companies which have had to invest in lifetime purchase of components. Several workers have already published information, which suggests that small levels of Pb contamination in LF joints can significantly reduce joint performance. Many of those concerned end-users approached NPL to assist with clarification of any reliability issues during the transition period. A consortium of 16 contributing companies was formed (list below) and a work programme agreed. The work will cover the following areas: . Reliability assessment of LF joints to SnPb components. . Reliability assessment of SnPb joints to LF components.

Two-times winner of Circuits Assembly Service Excellence Awards thanks customers, praises customer service teams. After receiving the Circuits Assembly Service Excellence Award for the second year in succession at Apex 2004, DEK has thanked its customers for sharing their experiences with the industry by taking part in the Circuits Assembly survey. DEK was the overall winner in the screen printing category, according to customer reviews of vendors’ dependability, ease of use, responsiveness, technology, and value for price. DEK customers who responded to the survey gave very high marks – many of them perfect scores – to the DEK service teams, the equipment’s dependability and to the DEK organization overall. The DEK Process Support Products division (PSP) is a further example, delivering fast turnaround stencil manufacturing supported by overnight delivery, online purchasing for consumables and machine performance upgrades, and continues to invest in new technologies such as electroform stencils, to make optimal solutions readily available to DEK customers. For more information, visit the Web site: www.dek.com

CEMCEX announces event schedule for 2004 Keywords Electronics industry, Conferences Based on the success of last year’s CEMCEX events in Central Europe, organisers of the

Contract Electronics Manufacturers Conference and Exhibition (CEMCEX) have been approached by visitors and exhibitors to conduct further events for 2004. The CEMCEX schedule of events for 2004 began with two, one day events in Poland at the Holiday Inn in Warsaw on 11 May and at the Holiday Inn in Gdansk on the 13 May. To further develop the cooperation established with EMS companies in the Czech Republic and Hungary, a series of two, one day events will be held at the Holiday Inn, Prague, Czech Republic on 12 October and on 14 October at the Hotel ¨ r, Hungary. Running in parallel with Raba in GyO the event will be a series of low-cost workshops that are open to all engineers interested in lead free technology. A limited number of table top positions are available for those companies seeking to explore the growing market in Central Europe. Only 30 exhibition places will be available at each event with simple, low-cost participation at e5,000.00 per company which includes lunch, refreshments and travel for exhibitors from Warsaw to Gdansk ¨ r and and return, similarly from Prague to GyO return. Exhibitors from CEMCEX 2003 included some of the industy’s major suppliers: Siemens Dematic AG, DEK Printing Machines, AIM, DAGE, Balver Zinn KG, Emerson and Cuming – ICI Belgium NV, PRC de Soto, Beck Electrical Insulation GmbH, H-Test, TWI, Vitronics Soltec, Universal Instruments, E-Tronics, Tru-Form and Indium Corporation of America. Aimed at Senior Management throughout the region, CEMCEX will be highly focused, by invitation only and the seminars and exhibition will be free to delegates. Simultaneous translations, coffee breaks, buffet lunch and an informal reception will also be provided. For further information, visit the Web site: www.cemcex.com

Asymtek wins SMT Magazine’s 2003 Vision Award for Conformal Coating Product Keywords Asymtek, Awards, Conformal Coating Asymtek was awarded SMT Magazine’s Vision Award for its Swirl Coate SC-300 conformal coating applicator at IPC/APEX show in Anaheim in February. The SC-300 applicator, judged best in the dispensing equipment category by a panel of industry experts, was selected for its innovation, ability to meet significant industry challenges, creativity and cost-effectiveness (Plate 4). Additionally, the SC-300 was judged on its quality, speed and throughput improvements, ease-of use and environmental responsibility. Award winners were chosen for innovative products in fifteen categories including software, printing, adhesives and components. An independent market research firm handled the balloting process and vote compilations. The SC-300 applicator allows manufacturers to apply conformal coatings to circuit boards by varying the volume, dispensing pressure and shape of the air assist in three modes of operation: bead, monofilament and swirl. An optional Tilt

Plate 4 Asymtek won the SMT Magazine’s Vision Award

accessory tilts the applicator in four positions 308 from vertical to the left, right, front or back, providing coating access in areas not accessible from the standard vertical approach. For more information, visit the Web site: www.asymtek.com

SMT/HYBRID/ PACKAGING 2004 System Integration in Microelectronics International Trade Show and Conference, 15-17 June 2004, Nuremberg Conference Centre Keywords Conferences, Germany, SMT All kinds of solutions, products and services associated with system integration in microelectronics will be on show at the SMT/HYBRID/ PACKAGING 2004, which will take place from 15 to 17 June 2004 in Nuremberg. The exhibition will provide a comprehensive overview of the sector from design and development, PCB production, component parts, placement technologies, through to testing equipment and the latest placement processes – all under one roof. By February 2004, in comparison to SMT/ HYBRID/PACKAGING 2003, the exhibition space is already noticably greater. This clearly shows the development of the event: rise in number of national and international exhibitors, much larger stand spaces booked by some exhibitors and a growing confidence in the sector’s future growth. From newcomers to the market leaders, the sector has passed a vote of confidence in the SMT/HYBRID/PACKAGING, with the date firmly fixed in the exhibition calendar. This year’s VDI/VDE production line will demonstrate ‘‘The PCB as platform for integrating component production’’ with a focus on PCB miniaturisation and associated technologies. A modern production line will manufacture components offering various possibilities for integration – from discrete components and embedded components to SoC and SiP solutions. Some of the future trends for producing electronic components will be presented at several production and demonstration areas next to the main production line. For the first time, Germany’s PCB Association will be taking part at the SMT/HYBRID/ PACKAGING. This will enable the event to address the individual demands of the PCB

industry more specifically. PCB manufacturers have always featured amongst the SMT/HYBRID/ PACKAGING exhibitors – and successfully, too. The 2004 event sees a clear increase in the number of companies from this sector, providing visitors with an even more comprehensive range of PCB products and services. By first July 2006, it is vital that lead-free manufacturing processes will be able to guarantee the production of electronic components, which are reliable. The move towards lead-free electronics production is not only a considerable step for the technology sector; the supply industry will have to overcome huge logistical hurdles to ensure delivery of the components. The still high demand for information can be satisfied at the Joint Stand ‘‘Service Point Lead-Free’’, instigated by the ELEKTRONIKPRAXIS magazine, where various companies present their range of services and products. The parallel SMT/HYBRID/PACKAGING Conference including tutorials is the most important practice oriented platform for presenting and discussing the results of new research, applications and user reports in the microelectronics branch. The focus of the 2004 conference is: ‘‘The PCB – a new system platform by using embedded components’’. The considerable challenge being faced by all developments in the electronic components sector is the increase in performance of the PCB at the least cost possible. Whilst in this context until now the focus has been on wiring boards with very delicate structures with microvia connections, wiring boards with integral passive and active components as well as optical signal paths are becoming increasingly important. The 2004 conference which will involve leading industrial partners will devote 1 day to this very topical theme to look at issues ranging from design through to product examples. The program includes, moreover, 25 user-oriented half-day tutorials on current and future developments in advanced electronic assembly production with regard to the entire net production chain from design through process technologies to quality assurance. However, the main topic throughout the tutorials is lead-free. Seven tutorials focus on the conversion to lead-free addressing the high demand of information within the industry. The complete conference and tutorial program will be published at the event homepage shortly after the event. Further information and the latest exhibitor list can be found on the Web site: www.smtexhibition.com

Henkel Technologies enhances its Multicorew technical support team with M.O.L.E.w Technology Henkel Technologies has selected ECD’s SuperM.O.L.E.w Gold system to help raise the level of technical support it can provide to customers for its Multicorew solder products throughout Europe and to establish a standard platform. After a rigorous test and evaluation procedure, involving five competing products, Henkel Technologies decided that ECD’s market leading temperature-profiling

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tool offered the best combination of features, software, simplicity of use and technical support. Henkel Technologies wanted a profiling tool that its engineers could use to help set-up new soldering processes and troubleshoot any soldering-related problems at the sites of its Multicorew customers. The SuperM.O.L.E.w Gold meets this need as it can be used to optimise process parameters, reduce rework and scrap, lower set-up times, compare temperature profiles and maintain processes in control by using SPC software. ECD’s SuperM.O.L.E.w Gold is a six-channel thermal profiler and is delivered along with all the necessary equipment to enable the user to quickly start his profiling operation. A thermal barrier, capable of protecting the unit in even the harshest lead-free environment, software, manuals and a selection of colour coded thermocouples are included in the kit. Specially developed SuperM.O.L.E.w for Windowse software takes the time and temperature information from the M.O.L.E.w and displays it on the computer screen, allowing all, or some, of the thermocouple data to be viewed simultaneously. The software can show temperatures at any point in the soldering process, as well as the change in degrees per second, how long the object has spent above specific temperatures, average temperatures, standard deviations and more. Additional online support is available via ECD’s Web site (www.ecd.com), which includes software downloads, upgrades and free licensing for customers. The software downloads include paste specifications for Multicorew and other manufacturers products and a comprehensive oven library. For example, the ProfilePlanner tool matches ovens to pastes and generates the most robust profile for the selection. The tool is continually updated and covers over 300 pastes, with specifications for the ramp, soak and spike values, as well as the time above liquidous. The SuperM.O.L.E.w Gold offers six-channel measurement over a temperature range from 129 to +1,3008C ( 200 to +23728F), to an accuracy within 18C (1.88F) and a resolution of 0.58C (18F). The sampling interval can be set from 0.2 s up to 24 h, and up to 5,460 samples can be recorded with six channels active. The compact unit measures 89 152.4 9.41 mm (3.5 6.0 0.38 in.) and it is supplied with a rechargeable Ni-MH power pack. For more information, visit the Web site: www.ecd.com

Universal’s wins Apex 2004 Innovation Technology Showcase Award Keywords Universal Instrument, Awards The Lightning high-speed placement head from Universal Instruments was selected for the Innovative Technology Showcase at APEX 2004. Chosen from the best technologies from all APEX exhibitors, the IPC Association commended Lightning’s solutions to the challenges of modern SMT assembly. Lightning solves the speed challenge through innovative use of Universal’s patented Variable Reluctance Motor (VRM) technology. Now

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developed for rotary application, VRM enables Lightning to index its spindles within 55 ms. Lightning has 30 spindles, yielding substantially high placement rates in a pick and place configuration. It also features dual on-the-head cameras, enabling accurate placement at full speed, from sub-0201 components to CSP, WSP, -BGA, and others up to 30 mm2. The optional embedded process verification using the CyberOptics EPVe6 system, operating concurrently with placement, provides two images at every pick and place event for immediate process analysis and refinement. The Lightning head is compatible with Universal’s AdVantis and dual-head Genesis modular placement platforms. It enables 30,000 cph placement rates in the AdVantis application. Genesis delivers 54,000 cph highspeed placement performance when fitted with twin Lightning heads. For further information, visit the Web site: www.uic.com

Plate 5 Siemens Dematic Electronics Assembly Systems regional headquarters for Southeast Asia

Siplace strengthens global development and production processes Keywords Siemens, Singapore Siemens Dematic Electronics Assembly Systems (SD EA) is globalising its value chain and continuing to expand its presence in Asia. SD EA is expanding its Siplace development and manufacturing activities in Singapore, its regional headquarters for Southeast Asia, to optimise its high production standards for Siplace placement equipment and its global manufacturing and development processes. The company wants to expand Siplace’s market share in Asia to 25 percent over the next 5 years. ‘‘As a globally operating company and market leader in surface mount technology we designed our entire value chain globally in order to continue to be the driving engine in the market worldwide. On top of our high market presence in Europe we have for quite some time been intensifying our sales activities in Asia. Now we are also adding research and development, manufacturing and purchasing. We are certain that this will help to enhance Siplace’s global competitiveness,’’ said Tilo Brandis, President EA. During the startup phase, individual machine components will be produced. As soon as all processes have been securely implemented and high and stable level of manufacturing quality has been established, complete Siplace machines will be produced in Singapore. Singapore will be used as the base for serving the steadily increasing demand of the dynamically growing electronics industry in Asia. To shorten the logistics chain, all major functions will be set up on site – from research, development and assembly to purchasing and logistics. To add more local value, suppliers from the entire region, but mainly from China, will be increasingly involved. With its excellent logistics infrastructure, Singapore offers ideal conditions for SO EA’s activities in Asia (Plate 5). As a visible sign of this expansion, the opening ceremony for the new development centre in Singapore was held on 6 January of this year (Plate 6).

Plate 6 (Right to Left) Heinrich v. Pierer, Siemens Director of the Board, Lee Hsien Loong, Singapore Prime Minister, and Tilo Brandis, CEO Siemens Dematic EA during the Inauguration Ceremony of the Singapore Siemens Centre. SD EA demonstrated live component placement including 01005 components with a SIPLACE placement line

For further information about Siplace, visit the Web site: www.siplace.com

Indium Corporation exhibited Pb-free products at APEX Keyword Lead-free soldering The Indium Corporation exhibited their Pb-free soldering products at APEX this year, they included the following.

NC-SMQ230 Pb-free solder paste for SMT Currently over 5,000,000 mobile phones have been produced with NC-SMQ230. This solder paste is an

air reflow, no-clean material specifically formulated to accommodate the high processing temperatures required by Sn/Ag/Cu and Sn/Ag Pb-free alloy systems. NC-SMQ230 provides outstanding printing performance along with extended stencil life and tack time to handle the rigors of today’s manufacturing environment. Pb-Free solder paste made with NC-SMQ230 has recently received the Frost and Sullivan Product Innovation Award.

PK-001 and PK-002 flip-chip epoxy fluxes These materials are designed especially for use with Sn62 and Sn 63 eutectic solders. PK-002 is specially designed for Pb-Free applications. PK-001 and PK-002 are fast curing, halide-free, no-clean fluxes which can be used for Flip-Chip or CSP soldering processes. PK-001 and PK-002 have a stable thermoset residue, and are compatible with standard underfill materials, conformal coatings, and most finishes and coatings. They are also environment-friendly.

complement to Universal’s industry-leading flexible fine pitch technologies.’’ Continued success of the partnership, and sustained market demand for high speed placement equipment such as the 4797L HSP, have allowed the agreement to be renewed several times in the past. Universal offers the 4797-series HSP alongside its strong modular platform product portfolio, which includes the AdVantis and GSM Genesis placement platforms, as well as costeffective end-of-line and through hole assembly solutions. For more information, visit the Web site: www.uic.com

NPL announces new dates for improved lead-free workshops Keywords NPL, Lead-free soldering

Eutectic AuSn solder AuSn solder finds use in critical applications such as hi-reliability medical, aerospace, and military applications, in die-attach and lid sealing, or as a braze alternative. Its relatively high melting point and exceptional joint strength make the alloy useful for certain applications. For more information, visit the Web site: www.indium.com

Universal and Hitachi extend high speed placement collaboration to 2009 Keyword Hitachi Universal Instruments and Hitachi High Technologies (HHT) have renewed their successful OEM agreement for further 5 years. HHT acquired Sanyo High Technologies, Universal’s original OEM partner, in 2003. The partnership has been lucrative for both companies, enhancing Universal’s best-in-class product portfolio with class-leading, turret-style high speed placement technology while affording HHT an extensive sales and support network. Since being first announced in 1989, this agreement has resulted in more than 1200 HSP platforms sold. The latest high speed placement machine to use HHT’s technology, the 4797L HSP, was recently awarded the 2003 EP&P Excellence Award and 2003 SMT Magazine Vision Award. In addition to customers’ access to the entire line of 4797-series HSP machines, extending the agreement until 2009 will allow further joint efforts to continue. These include recent line software development work, and may extend in the future to additional joint technical projects, technology transfers, and further product sharing. Heinz Dommel, Manager, Systems Division at Universal Instruments, said, ‘‘I am pleased to renew this valuable relationship and continue to make HHT’s best-in-class turret-style high speed placement technology available to a global market by leveraging Universal’s worldwide sales and support infrastructure. The HSP is the perfect

Last year NPL organised workshops that were focused on defined aspects of implementing leadfree processing for small groups with specific job functions. Over 120 key industrial personnel are now better prepared for the transition to lead-free soldering as a result of attending. From participant feedback the solid technical content based on the latest NPL research was found to be very valuable, especially when combined with practical process knowledge. Building on feedback from 2003 sessions, the new 2004 sessions have been updated and focused to better meet real needs and will be full 1-day events held at the NPL facility in Teddington: Specifying: design and procurement for leadfree . 1 June . 21 September . 30 November Manufacturing: engineering and quality for leadfree . 2 June . 22 September . 1 December For delegate numbers of four or more from one company NPL suggest that it is more cost-effective to present the workshop at their site. These interactive workshops will help to identify the main concerns during the transition stages, e.g. compatibility of SnPb components and lead-free alloys. The high demand of these workshops means that it is likely extra dates will be added. For more information, visit the Web site: www.npl.co.uk/ei/training

Universal Instruments and CyberOptics sign partnership agreement Universal Instruments Corporation and CyberOptics Corporation have signed an agreement to integrate the new Embedded Process Verification (EPVe) inspection technology from CyberOptics into Universal’s latest-generation electronic component placement systems.

Universal will offer the CyberOptics EPV sensor system as a feature on its recently released Genesise and AdVantise platform placement machines that incorporate its new Lightninge placement head. Introduction of the EPV sensor is currently planned for the second half of 2004. ‘‘EPV is one of the most exciting innovations in this industry in recent times,’’ stated Ian McEvoy, president of Universal Instruments Corporation. ‘‘To achieve the challenging quality goal of less than ten defects per million for SMT circuit board assembly, you have to verify each component placement. The CyberOptics’ EPV is the first sensing system to enable this within the placement machine.’’ Universal demonstrated an EPV prototype at the Productronica Trade Show in Munich, Germany in November 2003, and both companies demonstrated the product at IPC’s annual APEX Trade Show in Anaheim, CA in February this year.

Lead-Free Solder Reliability Conference Keywords Lead-free soldering, Conferences Over 90 delegates and six exhibitors gathered in NPL’s auditorium for the Winter SSTC (Soldering Science and Technology Club) Lead-Free Solder Reliability Conference. There was a high technical level of presentations, mixed with practical contributions and clear legislative details with ‘‘state of play’’ information, including from DTI representative, Andrew Lunnon. The situation remains fluid as the UK legislation dictating compliance with the already formalised EU directives moves ever closer toward the statute books. Discussion in the intervals was lively giving a clear indication, if any was needed, of the realisation that lead-free compliance means action now for UK companies. The reliability implications of using lead-free solders (for joints and laminates) prompted many questions from the audience. Presentations were as follows: ‘‘Update on implementation of WEEE and RoHS legislation’’ Andrew Lunnon, DTI ‘‘Reliability issues due to Pb contamination during the transition to lead-free soldering’’ Martin Wickham, NPL ‘‘Modelling materials behaviour in the transition to Pb free solder alloys and joint miniaturisation’’ Rachel Thomson, Loughborough University ‘‘Secondary Reflow of Lead Free Joints with Tin/lead Terminations’’ Bob Willis, EPS ‘‘Effect of thermocycling and thermal aging on lead-free solders’’ Milos Dusek, NPL ‘‘Intermetallics and mechanical characteristics of Pb free micro-joints formed from flip-chip assemblies’’ Changqing Liu, Loughborough University ‘‘Contribution of creep and stress relaxation tests to reliability assessment of lead-free solders’’ Milos Dusek, NPL ‘‘Voiding: Occurrence and reliability issues with lead-free’’ Martin Wickham, NPL

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‘‘Can we measure tin whisker propensity?’’ Chris Hunt, NPL ‘‘CAF Susceptibility of PWB Substrates’’ Alan Brewin, NPL For more information contact: Dr Chris Hunt, National Physical Laboratory, Teddington, Middlesex TW11 0LW. Tel: +44(0)20 8943 6065; Fax: +44(0)20 8614 0429; E-mail: chris. [email protected]

Universal and CeTaQ of Germany announce equipment capability assessment service cooperation Universal Instruments Global Services Division and CeTaQ GMBH have reached an agreement in principle to offer machine capability assessment services to surface mount equipment users requiring independent capability measurement and verification. The agreement provides Universal customers worldwide access to an independent and mobile metrology service and corresponding support from Universal’s Global Services team. ‘‘This agreement is based upon a mutual desire to bring a mobile and statistically valid metrology capability to our customers production environs while providing immediate corrective and preventive capability through Universal’s renowned service team,’’ says Bob Lamanna, Director of Global Services at Universal. ‘‘In these early stages of our venture, we are focused on sharing technical data, establishing services products and sorting out the logistics for worldwide availability.’’ Universal has an ongoing and extensive background in customer service and metrology while CeTaQ has established themselves as the premier source for on-site mobile metrology services. This arrangement allows Universal and CeTaQ to ensure continuous exchange of technical data while jointly addressing the emerging inspection needs of the Asian and North American business community. ‘‘Our relationship will allow CeTaQ to further expand its presence in the North American Market and reinforce our commitment to growth in the emerging Asian verification market,’’ says Dr-Ing Mathias Keil, CeTaQ co-founder and Managing Director. For further information, visit the Web site: www.cetaq.com

Soldertec Global announces winners of Lead-Free Solder Awards 2003 Keywords Soldertec, Lead-free soldering, Awards As the July 2006 lead-free compliance deadline draws near this year’s award selections have been designed to reflect the need for clear dissemination of information between the component and

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materials suppliers and the electronics assembly industry. This year there is a Consortium award, a Co-operation award and a service award. The winners are: HDP Users Group (HDPUG), Brian Smith (Celestica), Vivek Gupta (Intel), Thilo Sack (Celestica) and others. Dr Ning-Cheng Lee (Indium Corporation), Dr Edwin Bradley (Motorola) and Dr Vahid Goudarzi (Motorola) Dr Hector Steen (Henkel Technologies – Multicore) The HDP Users Group has been selected to receive a Lead-free Solder Consortium Award in recognition of the group’s key accomplishment in resolving issues leading to supply chain readiness for the launch of lead-free products. In particular, we acknowledge the work of Brian Smith for the General Purpose Lead-free Assembly System concept, Thilo Sack for his minimum peak temperature work, and Vivek Gupta for his work on component labelling. The Lead-free Solder Co-operation Award recognises the spirit of co-operation between materials supplier, Indium Corporation, and end user, Motorola. Dr Ning-Cheng Lee, Dr Edwin Bradley and Dr Vahid Goudarzi have developed a robust lead-free assembly process that has been unveiled to the commercial world. Results from the many parts of the assembly process have been shared through the jointly developed Quickstart program. The Lead-free Solder Service Award has been granted to Dr Hector Steen for his contribution to fundamental research and publications arising from collaborative lead-free projects over a 15 year period. The projects include 1991 UK DTI (Alloy selection), European BRITE program, INNOLOT (High stress/temperature applications) and EPSRC program looking at lead-free flip chip assembly. For further information, visit the Web site: www.lead-free.org

Universal and DaimlerChryslerSIM Tech. announce joint investment and technology partnership Universal Instruments has further underlined its commitment to China’s high technology base by establishing requisites for a long-term partnership with DaimlerChryslerSIM Technology (JV between DaimlerChrysler and Shanghai Institute of Microsystem and Information Technology, DCSIM Tech.) located in Shanghai, China. The objective is to build local expertise in advanced electronic packaging. The two companies will invest in China’s future in these technologies by training engineers, working with local suppliers, increasing local infrastructure and supporting local company projects for first and second level packaging. ‘‘Our vision is to build an industry capable of servicing local Chinese component manufacturers and assemblers as well as export markets throughout Asia and world-wide,’’ said Richard Boulanger of Universal Instruments’ SMT Laboratory. ‘‘Both businesses will invest substantial resources to nurture local technical

expertise and enhance the local infrastructure in Shanghai and Suzhou.’’ For DCSIM Tech., Dr Xiaoming Xie said, ‘‘Both companies are well positioned to develop China’s high-tech electronics industry. As one of the major players on the local market for many years, I am pleased that this agreement has established long term objectives, as a high level of ongoing commitment is the only truly effective way to establish China as a global center of excellence’’. Under the draft terms, Universal Instruments, which has assembly process expertise and laboratories in Binghamton, NY, USA and Suzhou, China, will also help sponsor a student from DCSIM Tech. to join the Electronics Packaging program at Binghamton University. DCSIM Tech. will offer students and other resources such as failure analysis and reliability testing for specific Universal projects. For further information, visit the Web site: www.uic.com

AIM appoints Cabiotec S.R.L. as distributor for Italy AIM has appointed Cabiotec S.R.L. as distributor for AIM’s complete line of solders and related assembly materials for Italy. Cabiotec S.R.L. forms yet another link in the global sales and technical support of the AIM line of assembly and fabrication products. Cabiotec S.R.L. specialises in sales, service and customer support for electronic production materials and equipment. Complementary product lines include screen printers, dispensers, pick and place systems, and reflow ovens. ‘‘AIM’s position in Italy is greatly strengthened by the appointment of the Cabiotec S.R.L.,’’ said Andrew Clarke, European Business Manager at AIM. ‘‘AIM has been manufacturing solder products in Italy for several years, and now we add to this the many years experience in the electronics industry of the Cabiotec staff. I am confident that the Cabiotec S.R.L. will provide customers of AIM soldering products with unparalleled service and support throughout Italy’’. For further information, contact: Cabiotec S.R.L. Tel: 02 6431832; E-mail: c.fiorentino@ cabiotec.it; Web site: www.aimsolder.com

Italy distributor extends Universal infrastructure Keywords Universal Instruments, Italy Universal Instruments has appointed Selettra Srl to distribute its products and augment its support services in Italy. The appointment is part of the corporation’s strategy to strengthen its European infrastructure and move support resources closer to customers. Selettra was founded in 1987 by Massimo Sant’Angelo, Franco Martini and Marco Cavallo – all well respected members of the Italian electronics community. The Milan-based company addresses all the electronics manufacturing markets in Italy with particular focus on the country’s prominent automotive

industry – and the many subcontractors who service this buoyant sector.

Universal appoints distributor in Portugal Keywords Universal Instruments, Portugal Universal Instruments has announced the appointment of Silgal-Sociedade Internacional de Importacoes to handle its sales and support activities in Portugal. This addition further extends the corporation’s infrastructure across Europe; a strategy designed to augment Universal’s own sales force and global services network. Founded in 1985 by Jose Madureira, Silgal is dedicated to the electronics manufacturing industry and supplies assembly solutions from consumables to complete production lines. The company already represents principals in the screen printing, soldering, inspection, handling and materials sectors, employing a dozen people in sales, service and technical support roles. Besides expanding the range of support services currently offered by Universal, the new appointment will serve to locate support staff closer to customers in Portugal. Silgal boasts an enviable list of blue chip customers in many sectors of the Portuguese electronics market, particularly automotive – the primary electronics industry in the country. Silgal is ISO9001 certified. For further information, visit the Web site: www.uic.com

technical knowledge sharing, responsiveness in service and spare parts supply, effectiveness in providing solutions, efficient consignment management and overall supplier performance. ‘‘We expect from our suppliers the same standards of support for our factories in South East Asia as well as in China. Siemens Dematic offered us solutions with the highest levels of service and support from basic Siplace machine services to maintenance contracts and warranty extension agreements designed to support us to increase our productivity and quality,’’ said Dr Chuah Chong Lim, Executive Director for Operations, Electronic Assembly Operations, Seagate Technology International. Siplace Services are based on standardized global modules, such as training, hotline support, on-site support, and fast and efficient spare parts supply. Our customers are provided with the same level of quality support no matter where they are located around the world by our team of highly skilled, professional engineers. The refined and tailored Siplace Global Services strategy for the complete customer life cycle provides value added assistance and helps customers to attain optimum production conditions and efficiency. For further information, visit the Web site: www.siplace.com

Exhibitions and conferences

ElectronicaChina and ProductronicaChina, Siemens Dematic is honoured with the 2003 17-19 March 2004 Gold Equipment Vendor Keywords Conferences, China, Award for Siplace Electronics industry Service and Support Messe M€ unchen held their first ProductronicaKeywords Siemens, Awards Sisemens Dematic Pte Ltd, Electronics Assembly Systems, Singapore received the Gold Equipment Vendor Award from Seagate Technology, a world leader in hard disk drive products, in recognition of its overall service performance to Seagate among all equipment suppliers. Awards were given by Seagate to equipment vendors who participated in the Equipment Reliance Program implemented in Seagate to focus on reducing operation wastages in electronics assembly. The category of equipment vendor was newly consolidated into one from the previous diversified machine categories. ‘‘Siemens Dematic is pleased to be awarded for its overall service and support performance by an industry leader like Seagate,’’ says Mr Siegfried Neubauer, Vice-President of Electronics Assembly Systems, Siemens Dematic Pte Ltd, Singapore. ‘‘This award demonstrates that Siemens Dematic has successfully and continuously been providing value-added services and support to customers’ varying needs.’’ The awards are given to suppliers based on their ability to support Seagate’s supply chain management objectives in the following areas:

China show in conjunction with the alreadyestablished ElectronicaChina in Shanghai at the Shanghai New International Exhibition Centre (SNIEC) in March. The opening on the first day coincided with a tropical storm that may have blown umbrellas inside out but did nothing to extinguish the enthusiasm of those who queued patiently to register. Like many new arrivals, ProductronicaChina was small, by comparison to Munich, but well formed, and it contained a spectrum of international exhibitors that attracted visitors from as far away as Chile to see what was on offer (Plates 1-5). An SMT company setting up in China would have no problem sourcing equipment, Bill Dai and Hongliang Lee of BTU Shanghai were showing their new Pyramax 98 lead-free reflow soldering machine, costing some $70-80,000. Delivery is included in the price and you can have one in a month. BTU have been in Shanghai for the last 5 years, and are doing very well – over 1,000 units sold into China in that time, 60 per cent for reflow, 40 per cent high-temperature furnaces for ceramics and semiconductors. They were having a good show. BTU operates through Kasion, who also represent Casio, Electronix, Nutek, Teknek,

¨ pel amongst many others in CyberOptics and GO SMT line equipment. Another exhibitor smiling broadly was Sven Andersen, President of PAWO, the Swiss high technology company. This was their first show in China, but as a company supplying beautifully engineered and very expensive unique tooling equipment for the placement of seals and connectors onto wiring looms, their future looked more than bright. They are to double their turnover in the next 4 or 5 years as the automotive industry in China ramps up production. In 2002 turnover was SFr 250,000, 2003 that rose to 1.5 million, this year it is set for 2.5 million. Why? They are in China, and China is where, within the next decade, all the cars will be made. In Hall 2 Vishay had a large stand, Norbert Pieper is their VP Business Development and said that 30 per cent of sales go into Asia at present and this is a rising percentage. Vishay is a $2.3 billion company, whose roots go back to 1962 when they were making foil resistors. Now they are one of the world’s largest manufacturers of discrete semiconductors and passive components, and a company to watch in the opto-electronics field. From Finland came Jukka Paajanen of VTI Technologies Oy who are in the business of MEMS sensors. They are only 10 years old, and have been selling into China for just 1 year, and see the big potential. Their MEMS are used in the automotive instrumentation field, as well as in the consumer market. In the next decade, 30 per cent of their sales will be in China, and they were having a good show, too. On the UK sector, David Wilson of Batten & Allen said that 90 per cent of their production of precision metal stamping products was exported, and it was the move of Ericsson from Sweden to China that meant that his company is now in China, too. They took on an agent about a year back, and are now expanding into other top quality niche markets for their quality products manufactured in Cirencester, Gloucestershire. On a slightly larger scale Mecca of Hong Kong is an OEM/ODM company which cover SMT, assembly, PCB fabrication, equipment design, packaging, plastic injection moulding. They started in metal castings back in 1984, but now have a turnover of some £500 million, and are major exporters to China, Europe and the USA. Mecca gets to the major shows, Globaltronics in Singapore and Nepcon in Brighton, UK and is, according to David Chang, their Marketing Manager, extremely busy. Arguably with the biggest stand of the show, and certainly one of the busiest, was Siemens Dematic. Sven Buchholz is the manager of product development in China and lives in Shanghai. In the last 3 years they have sold between 1,000 and 1,300 SMT machines into China, and he mentioned that the market is changing; whereas before the high-end (volume production) and lowend (start-up companies) was about 50/50, now it is moving 70/30 in volume terms and quality is what is needed in the high-volume business. Over from Munich was Matthias Frindt who showed the HF/3 3-gantry system for larger components. This is an end of line machine that combines throughput and accuracy. It uses magnetic linear direct drive, and is the first component placement machine to use this technology. The carbon fibre gantry also minimises weight, and running at 3,700 cph it is

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Plate 1 The Siemens stand was one of the busiest at the show

Plate 2 The Bruderer stand

accurate to 35 m at 4 Sigma. Placement force is between 0.5 and 15 N, and it is designed to take larger components up to 155 30 mm. The company has three service centres, Beijing, Shanghai and Shenzhen, and over 100 service engineers working throughout China. They appear to be well placed to meet the ground they will be gaining in the coming months ahead. A rather committed company, they will be exhibiting again in 4 weeks time, at Nepcon in Shanghai.

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Ivory Lim is the delightful senior customer service ¨ chling, an engineering plastic engineer at RO company who showed how PCB pallet materials are handled in the creation of a carrier for assembled boards that are to be wave soldered. Under the trade mark of Durostonew, this material contains a resin that provides resistance to flux chemistry and prevents solder pick-up, and the low density makes the production process, and the CLF280 version remains dimensionally stable and

flat even after the elevated temperatures of lead¨ chling are to be found in the free soldering. RO UK, France, Singapore, Germany, Italy, USA and of course Shanghai. Another enthusiast was Dr Jim Long who runs a company called eeParts.com which specialise in electronic component inventory re-distribution. Which is another way of saying that if an OEM or an EMS company finds that they have excess stock of a particular item, or items, then Dr Long’s company will make them available to others via online sourcing, on the ‘‘spot market’’ for immediate purchase and delivery. They will also enter into consignment agreements to move the excess. EeParts Inc operate out of Carrollton, Texas, also Suzhou and Shanghai in China. Bruderer and Daniel Troxler, their Product Manager, come from Frasnacht in Switzerland, and they manufacture metal forming and metal stamping presses. It all started back in 1943, and now if you want a metal press in this industry then it is likely to be a Bruderer. They came to the show in Shanghai because this is where their customers are, and they like to follow the trends that become apparent at such events. They export 96 per cent of what they make, which is hardly surprising, the main markets being Germany foremost, then Italy, France, with 10-15 per cent going to Asia. Daniel maintains that within the next 5 years the China market will be saturated, and will then move to India. Heard that before. They have gained considerable market share against stiff Japanese competition, and have a very good overhaul service in China. They were enjoying a good second day at the show. One of their customers is Velt Precision from Shanghai, General Manager Zhang Jianwen explained that they have two product groups, one which produces metal strip and one for punched metal parts or components – metals being aluminium, stainless steel, nickel or copper. Typical of many companies at the show, all of who have their market sectors. Velt only started business in Shanghai 3 months back and are making rapid progress. Mark Johnston hails from the UK but lives in Chicago where as Senior Director, he is reponsible for the global sales and marketing for Knowles Acoustics a $170 million turnover company employing some 2,700 people in the USA, Europe, Japan and in China. Knowles recently introduced the first MEMS microphone for mobile telephones, the SiSonic Surface Mount microphone which can also be used in a number of different applications. They are the first company to be manufacturing MEMS microphones in high-volumes, and joins their other major market share in microphones for hearing aids. If you are looking for MEMS, you need to go to Japan where they are most active in this field, but it would seem that R&D in Chicago is no slouch. TT Electronics had a stand that was never short of busy, and had a lot of information packed into a modest space. TT Electronics is a synergy of companies who each are specialists in their field, thus Welwyn for surface mount components, IRC for wire wound components and thick film technologies, and their market sectors include industrial, automotive, consumer electronics, medical, avionics, defence, and instrumentation. Stuart Tugman has been working for them, on and off, for 30 years, and the inventory of products reflects the ten divisions that produce them.

Plate 3 The German based RECOM exhibited

Plate 4 The stands were colourful and imaginative

Plate 5 The tyco stand was on two storeys

The Shanghai Keepahead Ultrasonic Technology Company Limited might have won the prize for the longest title, if there had been one, but they are certainly keeping ahead of the field when it comes to ultrasonic cleaning equipment. They have a dozen sales offices in China, as well as a further 12 companies representing them around the rest of the world. Cleaning, drying, handling is their forte, as well as electroplating lines. There were few circuit board companies at the show. AT&S had a stand for sure, but within the many German companies who were exhibiting there was Neuschafer Elektronik GmbH who come from Frankenberg. Ravan Graubner, their Sales Manager, explained that this was a company which

had started up some 20 years back, making rigid bards, and 6 years back they moved into flexibles and Polyflex. Polyflex is unique in that unlike conventional PCBs which require soldering of connectors, the thick copper layer (250-400 m) allows Polyflex circuits to be soldered directly. The thick copper tracks can carry high voltage current, and thus is suitable for use in the automotive and aerospace industries. This is their first show in China, and Herr Graubner indicated that once the business in China was established they would manufacture locally. Also from Germany is Recom based in Dietzenbach. They make small DC/DC convertors. Very small ones. They supply a

niche market, and much is made by hand, the tiny convertors being used in process control systems for the automotive industry, aerospace, medical and telecom sectors. Ancestry goes back to 1975, and they have been making them ever since, rather successfully. Jack van Mook lives in Singapore and is the Regional Product Marketing Manager for Assembleón. He has been in the SMT industry for 16 years. He heads up the Assembleón operation in China, where he maintains that their equipment has the edge where volume and technology are concerned. In the next 3 years, he said 70 per cent of all Asia business will be in China. Their market in Europe is reviving rapidly, too, especially in southern Europe, Turkey and Russia are examples. The multinational companies are now established in China, and the local companies come in two forms – existing electronics companies moving into SMT and new start up companies producing everything from ‘‘fridge to phones’’. On their large stand, they were demonstrating two placement machines, the VX3, which places 45,000-90,000 components per hour through a succession of 20 robots which populate boards from two sides, and the VX5, which runs at between 75,000 and 150,000 cph. He states that for this production capacity linear motors work just fine, 9 m accuracy is obtained. By the end of this year it will be six, due to camera alignment. Jack maintains that their parallel placement concept is difficult to compete against. Assembleón have a rich technology heritage, he commented, and whilst his company has training centres throughout Asia, they find that customers try as much as possible to do their own maintenance with their own engineers. In fact the salaries of Chinese graduate engineers are rising at the CAG rate of 20 per cent, which is encouraging. For the graduates, that is! In 4 weeks time he will be at Nepcon in Shanghai, and whilst this is the first Productronica in China, he wanted to have a look at how it tapped into new areas. A scout through the show looking at some of the more interesting products revealed that Rogers Corporation were in the PCIM sector with a busbar range, Hoechst were to be seen through CeramTec, whose ceramics are used in the production of hybrid microelectronic circuits. Laser cut edges are an option, and interest in their aluminium nitride ceramics was strong in the power electronics field in China. Truly semiconductors from Guangdong province had a range of tiny colour monitors and displays that will be familiar with those with the latest mobile telephones. On the Suneast International stand a range of REHM reflow soldering equipment was being displayed, including their popular Dragon 2.6 which uses nitrogen in the reflow for small grid soldering efficiency. Mr Li Quan Xi is the Manager of AN FEI KE YI Scientific Instruments Company, they are the agents in China for the Vision Engineering Kestrel non-contact measuring system used for the optical inspection of surface mounted semiconductors, and close by the Xiamen Hongfa Electroacoustic Co. had a large stand. They are No. 1 in China for relays, and claim to be No. 6 in the world. They can make special relays to order, Chen Yihua says that their biggest competition comes from Japan and the States, but since 1984 they have grown to become a $40 million company employing over 2,600 people. It seems that they only have 10 of their staff to look after sales in 150 countries, which must mean air miles for some.

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Frank He sells for Leister, another Swiss company; they produce laser soldering for metalmetal and laser welding for plastic-plastic, and have been operating in China for the last 3 years. Frank maintains that the market has yet to develop to its full potential for their equipment, but you can see from the samples that the applications are there already. Like all good shows there was the usual colourful plethora of shell scheme stands proffering ESD protection equipment, tools, clean room clothing, clean rooms, lab. scale placement machines, ultrasonic cleaning baths, ferrite armatures, chemicals, and balls for BGAs. On the other end of the spectrum was TYCO, who had a massive stand on two floors. And why not, they are a $10.25 billion company employing 80,000 people in 54 countries, and with electronics being their second biggest market sector, they amply demonstrated the huge range of products that come under their umbrella.

Summary The visitors to the Shanghai New International Expo Centre during Week 12 got good value for money. Halls 1 and 2 hosted ElectronicaChina and ProductronicaChina which were running along with PCIM China, and Halls 7 and 8 were the home of Semicom China. The latter was drawing in over 6,000 visitors a day. Mind you, if you had taken a wrong turning shortly before the SNIEC you could have gone to The third Plum Blossom Exhibition but that was very much an open-air event and would have been a chilly experience. SNEIC on the other hand was warm and welcoming and this show will doubtless be seen as some thing of a landmark occasion. That Messe M€ unchen took the initiative and added the Productronica element to the established Electronica may have much to do with the discussions which are now taking place between them and the CPCA to see how a joint event can be held in the future. Combining that with the news that Nepcon Shanghai would be moving to the autumn and you have the potential for a really comprehensive and world-class event in all eight halls at the SNEIC. We await developments with no little interest.

Appointments Asymtek’s Wesley W. Walters appointed as business development manager Keyword Asymtek Asymtek has promoted Wesley W. Walters as Win 3 business development manager. In his new role, Walters is responsible for building and maintaining relationships with fluid formulators, universities, research institutes and industry consortia, which Asymtek refers to as ‘‘Win 3’’ partners. Walters’s goal is to provide optimal solutions for customer requirements, working together with these industry partners. The end results are win-win-win outcomes. ‘‘We form these relationships to better serve our customers with process development and technical support,’’

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explains Walters. ‘‘When we work closely with the customer and their supplier, we all win.’’ Walters’s new responsibility is a natural extension of his current position as customer application lab manager for Carlsbad, where he is responsible for managing the Applications Engineering Group. The group serves Asymtek’s customers with timely technical data and new, customer-specific applications. As a resource for demonstrations, research and development, the Applications Engineering Group also provides customer training. Walters has over 20 years of experience in the electronics field, including 8 years at Asymtek. Prior to his promotion, Walters held the positions of North American Applications Engineering Manager and Applications Engineer for Asymtek. He also worked for Hughes Aircraft as a Manufacturing Engineer. Walters earned a BS in Business Management from the University of Phoenix and two technical degrees (Electronic Engineering Technology and Laser Electro-Optics Technology) from the University of Idaho. He is currently working toward an MBA. For further information, visit the Web site: www.asymtek.com

NEPCON/ Microelectronics Penang 2004

AIM appoints Cabiotec S.R.L. as distributor for Italy

September Singapore Expo

Keywords AIM, Italy AIM has appointed Cabiotec S.R.L. as distributor for AIM’s complete line of solders and related assembly materials for Italy. Cabiotec S.R.L. forms yet another link in the global sales and technical support of the AIM line of assembly and fabrication products. Cabiotec S.R.L. specialises in Sales, Service and Customer support for electronic production materials and equipment. Complementary product lines include screen printers, dispensers, pick and place systems, and reflow ovens. ‘‘AIM’s position in Italy is greatly strengthened by the appointment of the Cabiotec S.R.L.,’’ said Andrew Clarke, European Business Manager at AIM. ‘‘AIM has been manufacturing solder products in Italy for several years, and now we add to this the many years experience in the electronics industry of the Cabiotec staff. I am confident that the Cabiotec S.R.L. will provide customers of AIM soldering products with an unparalleled service and support throughout Italy.’’ For further information about Cabiotec S.R.L., contact: Tel: 02 6431832; E-mail: c.fiorentino@ cabiotec.it; Web site: [email protected]

International diary SMT/HYBRID/ PACKAGING 15-17 June Exhibition Centre Nuremberg, Germany Web site: www.mesago.de

15-18 June Penang, Malaysia

ELECTRONICS GOES GREEN 6-8 September Fraunhofer IZM Berlin

GlobalTRONICS 2004 7-10 September Suntec City, Mexico

GlobalTRONICS 2004

EPC 2004 European PCB Convention 5-7 October Cologne, Germany

CEMCEX Contract Electronics Manufacturers Conference and Exhibition 12 October Holiday Inn Prague Czech Republic 14 October Hotel Raba, Gyo¨r Hungary Web site: www.cemcex.com

NEPCON UK 2004 October National Exhibition Centre, Birmingham Estrel Conference Centre, Berlin, Germany Web site: www.pb.izm, fhg.de/ee

ELECTRONICA 2004 9-12 November together with the Embedded Systems Conference 2004 8-10 November Munich Trade Fair Centre, Germany Web site: www.global-electronics.de

Solder joint reliability

Solder Joint Reliability Prediction for Multiple Environments

Lead-free Solder Interconnect Reliability

Solder Joint Technology: Materials, Properties, and Reliability (Springer Series in Materials Science)

Solder Paste Jet Printing

Joint Action

Joint Operations

Structural Reliability

Ensuring Software Reliability (Quality and Reliability)

Critical Infrastructure: Reliability and Vulnerability Reliability

Reliability and Risk Models: Setting Reliability Requirements

Engineering reliability

Engineering Reliability

Bayesian Reliability

Time Out of Joint

Time Out of Joint

Time Out of Joint

Time Out of Joint

Joint Cognitive Systems

Under Joint Management

The Joint Rolling Handbook

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Bone and Joint Futures

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Joint Vision 2020

No More Joint Pain

Black Joint Point

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joint vision 2020

Solder joint reliability