Silicon Non-Volatile Memories: Paths of Innovation

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Silicon Non-Volatile Memories


Silicon Non-Volatile Memories Paths of Innovation

Barbara De Salvo Series Editor Mireille Mouis

First published in Great Britain and the United States in 2009 by ISTE Ltd and John Wiley & Sons, Inc. Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address: ISTE Ltd 27-37 St George’s Road London SW19 4EU UK

John Wiley & Sons, Inc. 111 River Street Hoboken, NJ 07030 USA

www.iste.co.uk

www.wiley.com

© ISTE Ltd, 2009 The rights of Barbara De Salvo to be identified as the author of this work have been asserted by her in accordance with the Copyright, Designs and Patents Act 1988. Library of Congress Cataloging-in-Publication Data De Salvo, Barbara. Silicon non-volatile memories : paths of innovation / Barbara De Salvo. p. cm. Revision of author’s thesis (Ph.D.)--Joseph Fourier University of Grenoble, 2007. Includes bibliographical references and index. ISBN 978-1-84821-105-6 1. Semiconductor storage devices. 2. Flash memories (Computers) I. Title. TK7895.M4D495 2009 621.39'732--dc22 2009016200 British Library Cataloguing-in-Publication Data A CIP record for this book is available from the British Library ISBN: 978-1-84821-105-6 Printed and bound in Great Britain by CPI/Antony Rowe, Chippenham and Eastbourne.

Table of Contents

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vii

Chapter 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

Chapter 2. Semiconductor Industry Overview . . . . . . . . . . . . . .

7

2.1. The cyclical semiconductor market . . . . . . . . . . . . . 2.2. The leading IC companies . . . . . . . . . . . . . . . . . . . 2.3. The world IC market distribution . . . . . . . . . . . . . . 2.4. Semiconductor sales by IC devices . . . . . . . . . . . . . 2.5. The semiconductor memory market. . . . . . . . . . . . . 2.6. The impressive price decline of IC circuits . . . . . . . . 2.7. Moore’s Law, the ITRS and their economic impacts . . 2.8. Exponential growth of manufacturing and R&D costs . 2.9. The structural evolution of the semiconductor industry 2.10. Consolidation of the semiconductor memory sector . . 2.11. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12. References . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . .

7 12 17 19 22 26 33 46 56 64 70 73

Chapter 3. Research on Advanced Charge Storage Memories . . .

77

3.1. Key features of Flash technology . . . . . . . . . . . . 3.2. Flash technology scaling . . . . . . . . . . . . . . . . . . 3.3. Innovative paths in silicon NVM technologies . . . . 3.4. Research on advanced charge storage memories . . . 3.4.1. Silicon nanocrystal memories . . . . . . . . . . . . 3.4.2. Silicon nanocrystal memories with high-k IPDs 3.4.3. Hybrid silicon nanocrystal/SiN memories with high-k IPDs . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . .

. . . . . .

. . . . . . . . . . . .

. . . . . .

. . . . . . . . . . . .

. . . . . .

. . . . . . . . . . . .

. . . . . .

. . . . . . . . . . . .

. . . . . .

. . . . . .

78 87 96 97 97 112

.......

117

vi


3.4.4. Silicon nanocrystal double layer memories with high-k IPDs . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5. Metal nano-dots coupled with organic templates . . 3.4.6. High-k IPD-based memories . . . . . . . . . . . . . . . 3.4.7. High-k/metal gate stacks for “TANOS” memories . 3.4.8. FinFlash devices . . . . . . . . . . . . . . . . . . . . . . 3.4.9. Molecular charge-based memories . . . . . . . . . . . 3.4.10. Effects of the few electron phenomena . . . . . . . 3.5. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6. References. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . .

119 121 127 136 139 151 159 163 164

Chapter 4. Future Paths of Innovation . . . . . . . . . . . . . . . . . . .

171

4.1. 3D integration of charge-storage memories . 4.2. Alternative technologies . . . . . . . . . . . . . 4.2.1. Ferro RAMs . . . . . . . . . . . . . . . . . . 4.2.2. Magnetic RAMs . . . . . . . . . . . . . . . 4.2.3. Phase-change RAMs . . . . . . . . . . . . . 4.2.4. Conductive bridging RAMs . . . . . . . . 4.2.5. Oxide resistive RAMs . . . . . . . . . . . . 4.2.6. New crossbar architectures . . . . . . . . . 4.3. Conclusion . . . . . . . . . . . . . . . . . . . . . 4.4. References. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

. . . . . . . . .

. . . . . . . . . .

. . . . . . . . .

. . . . . . . . . .

. . . . . . . . .

. . . . . . . . . .

. . . . . . . . .

. . . . . . . . . .

. . . . . . . . . .

172 185 187 187 188 199 202 206 215 216

Chapter 5. Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

223

5.1. References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

232

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

233

Preface

This book originates from the dissertation I wrote in 2007 to obtain the “Habilitation à diriger des recherches” (a national higher education diploma achievable after a doctorate) from the Joseph Fourier University of Grenoble, Physics Discipline. In many parts of this current publication new text has been added and old text has been updated. This book has been the chance for me to formalize in a single manuscript part of the knowledge I have acquired through several years of experimental and theoretical research conducted in the CEA-LETI (Grenoble, France), in the field of innovative non-volatile memory technologies. The results presented here are the fruit of team-work, where high-technology scientists, IC industrial partners, academics members, PhD and Master students have fruitfully interacted with each other within the frame of several research programs. Research presented here is an example of the strong efforts which are at the origin of the impressive progress of the integrated circuit technologies in the last decade. One of the main scopes of this book is also to provide a general strategy for future innovative research in the memory field. With this goal, a general overview of the different research paths and innovative technological approaches currently studied worldwide to fulfill the novel memory requirements is given. This overview tries to identify the present and future benefits of each approach. We hope that this work will make it easier for scientists and companies involved in this field to make technical and methodological decisions.

viii


Chapter 2 is dedicated to an economic overview of the semiconductor industry, paying particular attention to the memory market trends. The aim of this study, which is quite anomalous for a scientific text, is understanding the main causes which have brought the IC industry to face challenging contradictions in terms of economic pressure, consolidation trend, and strong structural changes (with an unmistakable shift of capital and research and development investments away from Europe and USA to Asia). It is obviously difficult to determine how this sector will evolve in the coming years, as the global restructuring process of the industry is still ongoing. Nevertheless, in retrospect, with the financial crisis and worldwide economic recession exploded in 2009, our 2007 analysis of the semiconductor industry crisis has touched on the roots of the effects of globalization of the world economy and of dangerous short-term financial management of the global industrial sector. As a scientist, I also believe that trying to understand the main factors at the origin of these phenomena is of the highest importance, for they determine the general framework of our research activities and moreover, from a larger perspective, they may impact on the future of our society. I hope that the elements reported here will be useful for the scientific community to improve understanding of the current IC industry economic situation. This book, to a large extent, is the product of interactions with many people whom I would like to acknowledge, including all the authors of many scientific publications who gave me their kind permission to include some material from their works – for the readers, references are always cited to the direct sources. I am indebted toward my close collaborators (students and colleagues from CEA-LETI) for their excellent work, their enthusiasm and their precious advice: G. Molas, L. Perniola, J. Buckley, M. Gely, E. Jalaguier, C. Jahan, S. Deleonibus, J. Gautier, F. Mondon, R. Kies, F. Martin, P. Mur, J.P. Colonna, G. Delapierre, F. Duclairoir, R. Baptist, J.C. Marchon, D. Deleruyelle, S. Jacob, T. Pro, M. Bocquet, G. Gay, E. Nowak, J. Razafindramora, D. Blachier, A. Toffoli, P. Scheiblin, G. Lecarval, D. Mariolle, V. Sousa, J.F. Nodin, A. Persico, V. Jousseaume, S. Maitrejean, L. Poupinet, O Demolliens, M.N. Semeria and certainly many others. Special thanks to G. Ghibaudo and G. Pananakakis from IMEP, T. Baron from LTM, D. Deleruyelle and P. Masson from IM2NP, G. Sarrabeyrouse from LAAS, D. Vuillaume from IEMN, S. Lombardo from IMM-CNR, G. Iannacone from the University of Pisa, L. Selmi from the University of Udine, P. Pavan from the University of Modena, B. Guillaumot, A. Maurelli and J.M. Mirabel from STMicroelectronics, L. Baldi, C. Gerardi and R. Bez from

Preface

ix

Numonyx for having shared with me part of their precious experience and knowledge. Finally, my deep gratitude goes to my husband Andrea and my son Leonard, who, during these years of research, have daily shared with me enthusiasms, joys, difficulties and efforts on a daily basis. Barbara DE SALVO


“At the time when humans ask for spare parts, machines ask for memory” Master Fausto Taiten Guareschi


Chapter 1

Introduction

Semiconductor Flash memory is an indispensable component of modern electronic systems which has gained a strategic position in the last decades due to the progressive shift from computing to consumer (and particularly mobile) products, as revenue drivers for IC (integrated circuits) companies. Today, memories are used in personal computers (PCs), cellular phones, MP3 players, digital cameras, televisions, wireless handsets, smart-media, networks, automotive systems and global positioning systems. At the core of the successful development of memories has been the steady increase of capacity, strictly linked to the shrink ability of the IC technologies. For decades now, semiconductor scientists and engineers have been looking for a universal memory, combining low-cost, speed and capacity, non-volatility, compatibility with current complementary-metal-oxidesemiconductor (CMOS) manufacturing techniques, and scalability. Today, it has been finally recognized that different applications have different requirements, and no one solution could be optimal for a wide range of conflicting demands. Nevertheless, in the past few years, the research and development into new types of memory have dramatically accelerated. There are several reasons for this: first, the “end” of Moore’s Law. Traditional semiconductor technology will not easily scale much further. How far it can be pushed is a matter of conjecture (32 nm node or some smaller nodes), but it is clear that we are close to the end of CMOS scaling. With 45 nm-32 nm semiconductor devices in volume production and 22 nm devices in the design stage, alternative technologies are the subject of a great deal of

2


attention worldwide. This consideration obviously also applies to microprocessors and logic. Second, there is the need for better memories. Conventional memory technology has inherent limitations. DRAM (Dynamic RAM) is cheap but volatile and requires continual refresh. SRAM (Static RAM) is faster but expensive and prone to soft errors – and it is still volatile. Flash is non-volatile but slow. Both magnetic and optical storage are high capacity, but are running up against the limits of current technology. The growing role of mobile computing and communications has led both semiconductor firms, such as Intel, and OEMs (Original Equipment Manufacturers), such as Motorola, to speculate about a future ubiquitous computing paradigm in which most of the customer equipment is untethered. There is a burgeoning demand for low cost, low power consuming nonvolatile memory technologies, with a considerable improvement on today’s Flash in terms of capacity and speed, since the new mobile paradigm for computing and communications will require that these new memories will need to provide rapid write and read capabilities for very large amounts of data (including video data). The third element will be memory for “disposable” electronics products, such as smart cards, RFIDs (radiofrequency identification), electronic tickets, toys, electronic greeting cards, etc., which are beginning to proliferate, as a result of the commercialization of printable and organic electronics. While capacity, speed and most of the other requirements for memory in such applications are not essential requirements, a significant cost reduction would be welcome in this market. In this book, based on the knowledge that we have acquired over several years of experimental and theoretical research in the field of non-volatile memories, we will try to give a general overview of the different technological approaches currently studied worldwide to fulfill the requirements of future memory applications. Although a critical economic analysis of the semiconductor industry is beyond the scope of this dissertation, as scientists working in this field, we cannot ignore the fact that we are currently living in a period of strong changes. All people working today in microelectronics (in companies, research laboratories or universities) live in a climate of challenging contradictions and constant urgency. In Chapter 2, based on historical data, we will show that semiconductor manufacturing is a highly competitive industry, where high technology, device cost and speed are the major economic driving forces. Rapid obsolescence of products (becoming obsolete in less than a year) and dramatic price decline are the main

Introduction

3

characteristics. We will talk about the volatility of the semiconductor markets, the constant price wars among IC companies and the impact of accelerated device scaling on technology costs. Particular attention will be given to the evolution of CMOS memory technologies over the last few decades. Using this analysis, we will try to understand the main economic factors at the basis of the current consolidation of the IC industry. In fact, the semiconductor industry is currently continuing its transformation from a relatively young, high-growth industry to a more mature one, facing many of the same issues that other established industries have already faced, as their markets became more saturated and geographical patterns of supply and demand shifted. Chip-makers are redefining business strategies to compensate for a variety of difficult economic pressures, including the increasing costs of developing new technology and adding new high yield manufacturing capacities. In addition to these fundamental changes, there is an unmistakable shift of capital and research and development (R&D) investments away from Europe (and the USA) to regions which are increasingly important as an end-market for semiconductors, i.e.: South Korea, Taiwan, China, Singapore and Malaysia. In the longer term, the migration of manufacturing and R&D could mean that regions which initiated the industry in terms of innovation and capital investment risk losing their status as centers of the semiconductor sector, along with the current economic leverage that status commands. This is the reality of the new global economy facing high technology-based companies, as well as applied research laboratories, in Europe today. We are crossing a threshold where the pace of disruptive shifts is no longer inter-generational with a meaningful impact over the span of careers and future of our students. In this context, in Chapter 2, we will try to identify and understand the main factors at the origin of these phenomena, looking at the semiconductor industry and market trends from an economic perspective. In Chapter 3, we will shortly introduce the main features and scaling limits of current Flash memory technologies. Then, the main strategy of the innovative research in this field will be presented. Today, two main research paths can be identified. To extend the classical floating gate technology to the 22 nm and possibly lower nodes, different “evolutionary paths”, essentially based on the use of new materials and of new transistor structures, can be investigated. On the other hand, to address smaller IC generations, “disruptive paths”, based on new storage mechanisms and new technologies, are envisaged. In this chapter, we will focus on the

4


“evolutionary approaches”, paying particular attention to the results obtained in our laboratory (LETI, CEA-Grenoble/France) in recent years, in the framework of research funded by internal projects, the French government, European institutions and industrial partnerships. Note that a crucial point in the definition of the research plans has always been maintaining a good equilibrium between short-term (made in collaboration with IC companies) and long-term (developed in collaboration with fundamental research laboratories, universities) solutions. Given the large variety of technologies currently invoked as potential replacements for conventional Flash, one of the hardest tasks for a scientist working in this field, at least concerning near-middle term research (i.e. time to be in production < 10 years), is to identify the right framework of study (for example, embedded or stand-alone environment) for the different technologies, in order to be able to assess the main advantages and disadvantages, and thus to prospect future applications. The “evolutionary approaches” include new modules (i.e. discrete trap memories, and more specifically silicon nanocrystal memories), new materials (high-k materials for the interpoly layer of Flash) and innovative architectures (as FinFlash memories). Moreover, obviously targeting a longer term application, hybrid approaches, which make use of organic molecules – grafted on silicon substrates – as storage sites, have been developed. Finally, the main theoretical limits of charge storage memories (i.e. reliability issues linked to certain few electron phenomena) have been identified, opening up the path to the introduction of disruptive memory technologies based on new storage mechanisms. In Chapter 4, we will try to define the perspective of the accomplished and main paths of research for the next few years. As discussed previously, in order to reduce bit cost and increase bit density, the shrinkage of Flash memories has been aggressively driven by reducing the cell size and introducing multi level technologies. Nevertheless, the linear scaling down of MLC NAND Flash memories is approaching its critical physical, electrical and reliability limits. Conventional cost-reduction approaches, notably smaller design rules, are having less effect, and new approaches should be considered. According to the main IC companies, the short-term way to circumvent these barriers is stacking memory cells on a single Si wafer. In this context, innovative integration paths, suitable for threedimensional integration of IC memory circuits, and new design/system solutions are introduced. On the other hand, “new breakthrough memory technologies”, such as phase-change memories, resistive RAMs, insulator

Introduction

5

and organic polymer cross-bar memories, are also considered as possible candidates for future memory applications. In the last part of this chapter, we will give a general overview of their main advantages and disadvantages in view of future memory applications. In the conclusion, we will summarize the main findings of the previous chapters and make some general considerations on innovation paths in the field of memories and on the future of microelectronics technologies as a whole.


Chapter 2

Semiconductor Industry Overview

In this chapter, we will give a general overview of the semiconductor industry from an economic perspective. Based on historical data, we will show that the integrated circuits (IC) industry is a highly competitive sector, where high technology, device cost and speed are the major economic driving forces. Rapid obsolescence of products (becoming obsolete in less than a year) and dramatic fall in price are the main characteristics. We will talk about the volatility of the semiconductor market, the constant price wars among IC companies, the impact of accelerated device scaling on technology costs. Particular attention will be given to the evolution of semiconductor memory technologies over the last few decades. Using this analysis, we will try to understand the main economic factors at the root of the current transformation and consolidation of the IC industry, from a relatively young, high-growth industry to a more mature and established industry, with an ever smaller number of competitors. 2.1. The cyclical semiconductor market Semiconductor microelectronics is the enabling technology at the heart of all information society technologies (IST) applications, such as personal computers (PCs), workstations, servers and other computer equipment, communication and Internet infrastructures (networking electronic systems and services), and consumer electronics (Internet appliances, mobiles).

8


Billion US Dollars World GDP

~ 60,000

Electronics Industry Semiconductor Industry Semiconductor Equipment Industry

~ 1,300

~ 256 60

40

Material Industry

Figure 2.1. A semiconductor-centric view of the value chain (2007 values)

Other applications of semiconductor integrated circuits (ICs) can be found in the automotive, energy, transportation, medical and pharmaceutical sectors. The semiconductor industry is part of a value chain with mature links (see Figure 2.1). This industry has played a particularly significant role in world economic and productivity growth over the last few decades. According to the Semiconductor Industry Association, in 2007, more than 60 years after the invention of the first transistor at Bell Labs (USA) in 1947, the worldwide IC market revenue totaled nearly $256 billion (~0.5% of world GDP). The semiconductor industry is highly cyclical. IC companies face constant booms and busts in demand for products. In fact, IC demand is an indirect demand, being driven by end-products created with ICs, such as PCs, cell phones and other electronic equipment. Generally rising demand drives up utilization in existing facilities and therefore profits, construction of a large number of new facilities begins, the new facilities come on-line and prices drop rapidly as the market moves into over-supply and companies try to keep their new facilities full.


9

This cycle is driven by the long time required to bring up a new facility and by the high fixed costs of facilities. Changes in the worldwide economy and over-inventory can also trigger downturns. In fact, during times of strong market demand, it is not unusual for companies to double order in trying to get parts, artificially overstating demand. Figure 2.2 shows the global industry sales trend with possible new waves of applications relaunching the market every 5/7 years (medical and robotics applications are foreseen as future market drivers).

Figure 2.2. Semiconductor market applications waves (source: Semico Research Corporation) and the IC industry cycle [ICI 07]

10

Silicon Non-Volatile Memories .

.

.

.

.

.

.

Figure 2.3. Growth of GDP, the electronics industry and sales of semiconductors [ICK 06]

As shown in Figure 2.3, IC industry revenues have grown at an average annual rate of 17% between 1970 and 2002. However, net growth over the last ten years was much less (i.e. 10% to 6%) [ICK 06, UCLA 03, SIA 05]. 1999 and 2000 were two strong revenue growth years, when revenue grew 22% and 34%, respectively. 2001 represented the most severe crisis in the semiconductor industry history (sales declined 32.5% from the previous year, dropping from $204 billion in 2000 to $139 billion in 2001). ICs placed in PCs and other computers accounted for 47% of IC revenues in 2001, down from 55% in 1998. The most significant factor in the slower growth in IC demand in 2001 was found in the maturing of the PC business or saturation of the market. The PC boom in previous years had been powered by the IC. Revenues growth in PCs and servers during 1997-2002 had been essentially zero, down from 16% per annum during the previous five years. Then, some applications, like desktop publishing or the Internet, generally created the need for more complex software and hardware, spurring new purchases in the PC industry. In telecommunication equipment, the 19992000 wave of expansion had fallen sharply in 2001-2002. A recovery in this sector happened in 2003.


11

Concerning 2008, total IC sales were $248.6 billion compared to $255.6 billion in 2007, a decrease of 2.8% [SIA 09]. According to several analysts [JEB 09], the global economic recession severely dampened semiconductor sales in the fourth quarter of 2008 (semiconductor sales in December declined by 16.6% from November 2008), historically a strong quarter for the industry. The worldwide financial turmoil is expected to continue to have an impact on demand for semiconductors in 2009. Never before has the semiconductor industry experienced revenue declines in back-to-back years, but it is forecast that this will occur in 2009, as worldwide semiconductor revenue is predicted to total $219.2 billion, a 16% decline from 2008 revenue. Nevertheless, several analysts suggest that this downturn is different in many ways from the 2001 case, being due to the combination of an overdue industry down-cycle with a global economic crisis of unprecedented magnitude. The 2008 downturn is broad-based, not only limited to technology, has a much different growth profile before the downturn and has far less inventory buildup. The financial meltdown, which began in the summer of 2007, has finally pushed the USA and the whole world into a recession. Consequently, it has spread fear and uncertainty throughout the entire food chain spanning electronics, chips and equipment. Nevertheless, inventory levels this time have been monitored and more tightly controlled throughout the entire food chain, and this will help the market come back more quickly than in 2001. Although there is a wide range of economic predictions, it appears that most economists are predicting that the economy will recover in no less than one year. Several forecasts suggest that the semiconductor industry will recover to grow by 6% in 2010 followed by a growth of 10% in 2011, making it the first year to show double-digit growth. Nevertheless, since 2001 some recommended that the IT industry should get used to “life in the slow lane”, growth being limited by the lack of new applications and new users [RUM 03], no new “killer” applications being foreseen in the short term. Several economists claim that the IC industry has been “maturing” in the last few years. In particular, the semiconductor industry would have been in the maturity phase of the typical “S curve” lifecycle of a technology-based industry (see Figure 2.4). In the early stages of the technology life-cycle (E and G phases), the technology leads the market, while in the latter stages (M and D phases) the technology lags behind the market. Normally, commercial-led life-cycles (as is the case for the IC industry) tend to be shorter and they shrink faster than government-led technology life-cycles. The good management of an R&D portfolio includes

12


the careful timing for the introduction of new products. This aspect is often referred to as the “scheduling” of a breakthrough. Moreover, in technology areas where the speed and acceleration of innovation are significant competitive factors, such barriers to entry can become truly prohibitive for small or even medium size companies, leading to the creation of oligopolistic or even monopolistic market profiles. Nevertheless, it should be said that, even with an annual growth rate which has lowered in the last few years, the high-technology industries still drive the economic growth around the world. According to the Global Insight World Industry Service database, which provides production data for the 70 countries that account for more than 97% of global economic activity, the global market for high-technology goods is growing at a faster rate than for all other manufactured goods [NAT 06].

Figure 2.4. Typical “S curve” life-cycle of a technology-based industry [CAR 99]

2.2. The leading IC companies The semiconductor industry was originally pioneered by US-based companies, and in the very early days of the industry, the North American market share was nearly 100%. Figure 2.5 illustrates the worldwide market share held by each region in the last few decades. Initially, the US-based companies focused on driving technology, but put little emphasis on yield and quality. In the 1980s the Japanese began to dominate commodity product areas like DRAM memory chips with a relentless focus on yield, quality and cost. The Japanese also continued to invest in new facilities


13

during downturns, capturing increased market share in each upturn. In the late 1980s and early 1990s a number of factors combined to bring about the end of Japanese dominance of the semiconductor market. Led by SEMATECH consortium of government and private companies, US-based companies began to improve manufacturing capabilities. The Koreans and later the Taiwanese entered the DRAM market and began to make huge investments in new facilities. In 1995 the DRAM market peaked at nearly $41 billion, while by 2001 the DRAM market had shrunk to just under $11 billion, although it has recovered to $33.8 billion and $31.3 billion in 2006 and 2007, respectively.

Figure 2.5. Semiconductor market share by country in which the company is headquartered [ICK 06]. Rest of the World (ROW) included Europe until 1998, after which Europe was listed separately. Values for 2003, 2004 and 2005 are estimated based on the top 25, 50 and 50 semiconductor companies respectively

The improvement in the manufacturing capabilities of US companies and the market shift to products such as μprocessors, digital signal processing (DSPs) and special memories (such as SRAM and Flash) where US design strengths are relatively more important, drove North America back to the top of the market share ranking. In Figure 2.5, 2004 represents a huge upturn for

14


the rest of the World catching Japan for the first time although in 2005 Japan once again pulled slightly ahead. The top 10 worldwide semiconductor vendors for 2008 are reported in Table 2.1. Intel held the first position for the 17th consecutive year in 2008 (with ~80% of the revenue share for microprocessors). Qualcomm experienced the strongest growth rate among the top 10 vendors, as its revenue increased 15.3% in 2008. All vendors focused on the DRAM and NAND Flash markets experienced strong revenue declines due to oversupply and strong price reductions. Hynix Semiconductor suffered the steepest decline among the top 10 semiconductor vendors in 2008, as revenue dropped 34%. Another vendor that struggled during 2008 was Infineon Technologies as its memory subsidiary Qimonda became marginalized within the DRAM industry. 2008 Rank

2007 Rank

1

1

Intel

33,187

13.3

33,988

-0.5

2

2

Samsung Electronics

17,391

6.8

20,464

-15.0

3

3

Toshiba

10,601

4.2

11,820

-10.3

4

4

Texas Instruments

10,593

4.2

11,768

-10.0

5

6

STMicroelectronics 10,270

4.0

9,966

-3.1

6

5

Infineon Technologies (incl. Qimonda)

8,461

3.3

10,194

-17.0

7

8

Renesas Technology

7,081

2.8

8,001

-11.5

8

11

Qualcomm

6,477

2.5

5,619

15.3

9

7

Hynix Semiconductor

6,010

2.4

9,100

-34.0

10

12

NEC Electronics

5,770

2.3

5,593

3.2

Others

138,545

54.3

143, 029

-3.1

Total

255,013

100.0

269, 542

-5.4

Company

2008 Revenue

2008 Market Share (%)

2007 Revenue

2007-2008 Growth (%)

Table 2.1. Top 10 worldwide semiconductor vendors by revenue estimates (millions of US dollars) [GAR 09]


15

2007 Major IC Foundries 2007 Rank

Company

Foundry Type

Location

2005 Sales ($M)

2006 Sales ($M)

06/05 Sales (%)

2007 Sales ($M)

07/06 Sales (%)

1

TSMC

Pure-Play

Taiwan

8,217

9,748

19%

9,813

1%

2

UMC

Pure-Play

Taiwan

3,259

3,670

13%

3,755

2%

3

SMIC

Pure-Play

China

1,171

1,465

25%

1,550

6%

4

Chartered

Pure-Play

Singapore

1,132

1,527

35%

1,458

-5%

5

TI

IDM

US

540

585

8%

610

4%

6

IBM

IDM

US

665

600

-10%

570

-5%

7

Dongbu

Pure-Play

South Korea

347

456

31%

510

12%

8

Vanguard

Pure-Play

Taiwan

353

398

13%

486

22%

9

X-Fab

Pure-Play

Europe

202

290

44%

410

41%

10

Samsung

IDM

South Korea

-

75

N/A

385

413%

11

SSMC

Pure-Play

Singapore

280

325

16%

350

8%

12

HHNEC

Pure-Play

China

313

315

1%

335

6%

13

He Jian

Pure-Play

China

250

290

16%

330

14%

14

MagnaChip

IDM

South Korea

345

342

-1%

322

-6%

Table 2.2. Top 10 worldwide IC foundries by revenue (millions of US dollars) [ICI 08b]

The top 10 foundries by revenue for 2007 are also reported in Table 2.2. As shown, 11 of the top 14 foundry companies listed are based in the AsiaPacific region. Europe-headquartered X-Fab, which merged with 1st Silicon in 2006, is the only non-Asia-Pacific pure-play foundry company in the top 14 group. The four main players (TSMC, UMC, Chartered, and SMIC) have dominated the foundry market over the past five years. With sales of almost $10 billion, Taiwan Semiconductor Manufacturing Co. (TSMC) was clearly the leading foundry supplier in 2007. UMC maintained its second place ranking with sales of $3.8 billion. SMIC increased its sales and edged slightly ahead of Chartered in 2007 to take the number three position in the ranking. Together, these four players accounted for just over two-thirds (68%) of the $24.5 billion foundry market in 2007. TSMC, UMC, SMIC and Chartered are pure-play foundries – companies that do not offer IC products of their own design, but instead focus on producing ICs for other companies. In 2007, pure-play foundries accounted for 84% of the total foundry market. Integrated device manufacturer (IDM) foundries accounted for 16% of the 2007 foundry market. IDM foundries are defined as those companies

16


that offer foundry services in addition to their own ICs. IDM foundries include IBM, NEC, TI and Samsung. In 2006, Samsung announced it was going to place special emphasis on its foundry business. Aided by a technology alliance with IBM and Chartered and with a new 300 mm wafer fab dedicated exclusively to foundry production, Samsung has quickly emerged as a foundry player. IC foundries have two main customers – fabless IC companies such as Qualcomm, Nvidia, and Xilinx, and IDMs such as Freescale, ST, and others. The success of fabless IC companies as well as the movement to increased outsourcing by existing IDMs has fueled tremendous growth in IC foundry sales since 1998. Large companies and an increasing number of mid-size companies are ditching their fabs in favor of the fabless business model. In order to better understand the current IC industry situation, it is beneficial to have a look to the history of the Taiwanese foundries. In [JUN 06], the author very clearly explains the origins of the fabless/foundry model development in Taiwan, which mainly took advantage of the need for rapid production cycles through the decentralization of the production chain allowing for flexible and rapid responses to changes in demand. The horizontal integration of Taiwan’s industry and the small size of their firms allowed them to fill market space along the lowest levels of the market; this business organization focused their industry around specialized chips and foundry production, shaping the current landscape of their industry. Of the 201 Taiwanese chip companies in 1999, 115 were design houses, 20 were IC producers, 36 were packaging vendors, and 30 were testing companies. This type of horizontal integration allows for a responsive and agile industry that fills in market spaces that large vertically integrated conglomerates cannot occupy. In 2001, Taiwanese design houses captured 25.9% of the global design market, second only to the USA. Unlike American design houses, however, the Taiwanese do not focus on technological break-through for new production possibilities; instead the Taiwanese design houses generally tailor existing large-scale innovations to meet individual customer demands, or provide chip solutions among electronics manufacturers. Horizontal integration, of course, would not be possible without the development of the foundry model. Foundry production is the largest segment of Taiwan’s domestic industry; in 1999, and foundry related business accounted for almost 60% of Taiwan’s total industrial revenue. As with design houses, Taiwanese foundries meet


17

global demand on an individual basis; however, these demands concern the fabrication necessities of semiconductor producers rather than the production necessities of consumer electronic manufacturers. It should be said that Taiwan Semiconductor Manufacturing Company and United Microelectronics capitalized on the inability of American producers to compete with Japanese production efficiency and financial resources in the 1980s. In fact, as American transnationals continued to lose market shares to Japanese competitors, they began to outsource more advanced stages of the production chain to private foreign firms. American firms shifted their focus to their comparative strengths of research and innovation, subsequently leaving spaces in the global industry for firms to fabricate semiconductors. Taiwanese foundries filled this space by meeting the individual demands of each chip producer through direct relationships. By 1998, more than 300 of the world’s 500 fabless chip design houses were located in North America while Taiwanese foundries accrued 75% of global pure-play foundry revenue. No other firm benefited from the creation of this new business model more than TSMC, the world’s largest and most technologically capable chip foundry. In 1995, TSMC provided foundry services to approximately 40 different U.S. firms, 55% of its total production. As of 1999, it became the most profitable technology company in Asia outside of Japan. Net sales grew from $1.2 billion in 1996 to a little under $6 billion in 2003. The substantial demand for foundry production is further evidenced by UMC’s experience. Also begun by a government spin-off in 1980, UMC evolved from producing phone dialer chips to microprocessors to SRAMs. In the last years, the fabless/foundry model is the fastest growing segment of the semiconductor industry. While the entire semiconductor industry experienced slower growth from 1999 to 2004, the foundry segment outperformed the industry with a rise from $7.6 billion in sales in 1999 to $35.4 billion in 2004. In 2000, the entire industry grew at 36.8%, while the leading foundries grew between 60 and 125%. Taiwan’s position at the center of foundry manufacturing is one of the primary reasons for their emergence as a major semiconductor producer. 2.3. The world IC market distribution Concerning the world IC market distribution, of the $250B generated in the IC industry in 2006, Asia (including Japan) accounted for over 60% of all sales (see Figure 2.6). The fastest-growing market is China. China’s semiconductor market growth continues to outrun the rest of the world.

18


Since 2001, the bottom of the last semiconductor business cycle, China’s semiconductor market has grown at a 31.5% compounded annual growth rate (CAGR), while the worldwide market has grown at a 10.6% CAGR. During the past two years, China’s semiconductor consumption market (measured in US dollars) grew by 27% in 2006 and 23% in 2007 (to reach US$88.1 billion, representing 34.4% of the worldwide semiconductor market). This exceeds the markets in Japan, North America, Europe and the rest of the world for the third consecutive year. In contrast, the worldwide market grew by only 9% in 2006 and 3% in 2007. Though China’s semiconductor market continues to grow faster than the global market, its growth rate is gradually decreasing from its 2003 peak. While further slowing is expected, forecasts for China’s growth rate still exceed the worldwide rate by at least 50% for the remainder of this decade. China has a middle class now of about 300 million people, which is basically the equivalent of the entire US population and they still haven’t come up on the per capita GDP scale.

Figure 2.6. Outlook of the worldwide semiconductor market by region, 2003-2007 [PWC 08]


19

Nevertheless, some of China’s poorest regions have a standard of living on par with the poorer parts of Africa. The same considerations are also applicable to India, which has an economic growth of about 8%. India has 17% of the world’s population, but only 2.5% of global GDP (i.e. 390 million people live on less than US$1 a day). For markets of hundreds of million poor consumers, radical, low-cost IC-based products, such as the $100 computer, will be produced (Figure 2.7).

Monthly Salaries

New Applications Europe USA Japan

100

South Korea + Taiwan

80 60

Eastern Europe Brazil Mexico Russia China

40 20 0

500,000

New Customers Indonesia India

1,000,000 1,500,000 2,000,000 2,500,000 Population (in thousands)

Figure 2.7. Different consumer goods are foreseen for different economies

2.4. Semiconductor sales by IC devices As already discussed, among the different applications of semiconductor devices, for many years, computers (PCs, workstations, servers) have been the main market driver (see Figure 2.8). This means that, among the different semiconductor ICs, devices such as dynamics random access memories (DRAMs) serving as temporary storehouses of data and passing information to and from computer devices, memories and microprocessors, i.e. central processing units that contain the

20


basic logic to perform tasks, have driven the largest sales and have the largest volume of IC companies (see Figure 2.9). Nevertheless, today it seems that the application profile of semiconductor devices is changing, with a shift from computing to consumer products as revenue drivers (see Figure 2.10). More exactly, the boundaries between consumer, computers and communication segments are currently blurring and a new segmentation criterion has been introduced. There is a transition from a function-based model to a user-based market model products are designed more on how people use them, rather than on what functions are incorporated. Indeed, it has been mobility applications which have driven the inflection point for high-capacity non-volatile memory devices.

Source: IC Insights Figure 2.8. IC application market growth rate comparison [ICI 08c]


21

Figure 2.9. Semiconductor sales and volume by IC devices [BAR 07]. $250 B sold in 2006: $58 B memories – Flash ($22 B), DRAM ($33 B) & SRAM ($3 B); $54 B MOS micro, including MPU, DSP, MCU; $60 B MOS logic, including chipset, ASIC, FPGA’s and FPLD’s, $37 B analog, $38 B discrete; 520 B units sold in 2006: 67Bu Digital (memory, logic, micro); 70Bu analog; 322 Bu discrete)

22


Figure 2.10. Semiconductor sales by end-product market [WFR 07]

2.5. The semiconductor memory market Concerning the MOS memory sector, the memory market (including DRAM, SRAM and Flash) accounted for $58 B (nearly 28% of the total IC market) in 2006 (see Figure 2.11), making them the second largest category overall just behind logic components. The 2007 market for MOS memory devices was flat in 2006, but memory unit shipments increased very well (32%) during the year. The key driver for memory units has been the increasing number of consumer, communication, and computer products proliferating the market and the increasing amount of memory built in to each system. The DRAM and Flash memory markets remain the two largest memory segments. Together, these two markets accounted for 92% of all memory sales in 2007. DRAM held the largest share of the memory market because of its close ties to the computer industry. However, with the advent of the mobile era, the semiconductor memory with the highest growth has been the Flash memory, especially of the NAND variety which offers ever increasing capacities at lower prices [KIM 06]. The NAND segment overtook the NOR segment in market share in 2005. Flash has been widely implemented in consumer items such as digital cameras and MP3 players, in “computer” applications in the form of USB drives and memory cards, and in communications applications such as cell phones. A wide array of portable products continues to gobble up nearly all the flash memory that vendors can build. In the next years, Flash will likely play a bigger role in the computer segment, as it serves as a replacement for hard disk drives in portable and mobile PCs. Presently, the Flash NVMs (non-volatile memories) market is in the range of $20 billion, but it is forecasted to grow with a higher average annual rate than DRAM and


23

SRAM. In 2007, main players in the NOR market were [LAP 07]: Spansion (~32%), ST/Intel -Numonyx (~36%), Samsung (~13%) and SST (~4%). According to DRAMeXchange [DRA], in 2008, main players in the NAND market were: Samsung (~40.4%), Toshiba (~28.1%), Hynix (15.1%), Micron (7.9%), Intel (5.8%) and Numonyx (2.6%). According to iSupply, in 2008 DRAM top vendors were: Samsung (~30%), Hynix (20%), Elpida (15%), Micron (13%), Qimonda (9.4%), Nanya (4%), Promos (2.1%) and Powerchip (1.7%).

Figure 2.11. Memory sales and volume [BAR 07]. $58 B was sold in 2006: $34 B DRAM, $12 B NAND, $9 B NOR, $4.6 B all other memory. 18.5 B units were shipped in 2006: 8 Bu DRAM, 3.6 Bu NOR, 1.8 Bu NAND, 5 Bu all other memory

24


However a damaging oversupply and dropping demand (which cut revenue even before the current global economic slowdown) has caused a crisis in the memory market which is not predicted to rebound until the end of 2009. The year 2007 has been a very difficult year for DRAM manufacturers. On an annual basis, DRAM revenue in 2007 declined to $31.5 B, down from $34 B in 2006, due to suppliers’ market-share and capital-spending games. In 2007, aside from Hynix and Elpida, every other member of the top-8 rankings, from Samsung downwards, suffered a decline in DRAM revenue in 2007. The year 2008 has been a “disastrous” year for most memory chip manufacturers. Of the top 20 semiconductor suppliers, the memory IC suppliers will suffer some of the largest declines in revenue. Every memory segment has declined in 2008, with DRAM leading the way with a 19% drop in revenue (from $31.3 B in 2007 to $25.7 B in 2008). NOR flash memory has dropped 16% (from $7.7 B in 2007 to $6.6 B in 2008) and SRAM declined by 16%. NAND Flash memory also dropped for the first time in the history of the market, with a 14% decrease (from $14.5 B in 2007 to $12.5 B in 2008). Flash has had the fastest growth market in the history of semiconductors, the axiom implied that the NAND transistor count would double every year in leading-edge devices, thereby driving prices down by some 40% a year as a means of enabling new applications. However, too many vendors followed the same path, creating excess supply and falling average selling prices (ASPs), so that NAND vendors are losing money. Firms which have suffered large declines in revenue include Hynix Semiconductor (with a drop of 29.1%), Micron Technology (with a 9.2% revenue decrease in 2008), Samsung Electronics (also with a 9.1% decline in 2008), Qimonda (with a fall of 40.7%), Nanya Technology (with a 29.1% decrease) and Powerchip Semiconductor (with a 23.4% drop). This negative trend is expected to continue even in 2009 (see Figure 2.12), owing to high bit growth in supply. The impact of financial crisis is still diffusing, and consumer confidence is relatively low with the global recession. The oversupply has encouraged some suppliers to cut capacity and costs, closing fabs and laying off employees, attempting acquisitions to lower overall industry competition and licensing fees, delaying joint ventures, and, in some cases, exploring bankruptcy options (as for Qimonda and Spansion). A strong consolidation of the memory market is also expected. Memory components are predicted to account for $40 billion or 21% of the IC market in 2009, remaining the second largest category overall just behind logic components. Even with the souring environment, the year 2010 will fare significantly better with a return to positive profit growth.

, , , ,

, ,

, ,

, ,

Figure 2.12. Memory percent of Total IC Market [ICI 09]

, ,

, ,

, ,

Semiconductor Industry Overview 25

26


Memory will account for an estimated $50 billion in total revenue and set the trend for continued expansion until 2014 which will result in a compound annual growth rate of 13% over the entire forecasted period. 2.6. The impressive price decline of IC circuits Semiconductor manufacturing is a highly competitive industry in which device cost and speed are the major economic driving forces. High technology and rapid obsolescence (with products becoming obsolete in less than a year) are the main characteristics. There is no other product with quite such brutal requirements. Indeed, swiftly falling prices provided powerful economic incentives for the rapid diffusion of information technology [SIA 05]. Since 1970, the price of a single transistor element of an IC has dropped at an average rate of 27% (in 1954, 5 years before the IC was invented, the average selling price of a transistor was $5.52, 50 years later, in 2004, this had dropped to 191 nanodollars). The rise in revenues of IC companies in the face of constantly deflating prices meant that the unit volume (transistor/year) and market had grown at an average annual rate of over 45% [RUM 03]. Indeed, the only industry where economists have charted sustained decades of improvement in price performance like those of semiconductor devices is the computer industry (with annual declines in cost near 20% through most of the postwar period, and 30% for the personal computers coming onto the scene in the 1980s [FLA 97]), the largest customer for transistors produced by semiconductor companies. Input prices are much higher for “all end-user sectors” industry (such as automobiles) than for computers and communications. It is commonly assumed that the rapid price decline has been directly followed by impressive technological improvements and semiconductor device scaling. Nevertheless, to measure the whole economic impact of the transistor price-decline in a more precise way, we must first chart the overall contours of technological change in semiconductors in a more satisfactory fashion. Figures 2.13 to 2.15 show price decline data (taken from different sources) of semiconductor devices from 1970 to the present day. Figure 2.13 shows that different devices did not have equal price decline. Prices have declined little for analog devices, bipolar devices, and light-


27

emitting diodes. For products making use of leading edge technologies, corresponding to about 25% of processed wafers in 1999 (such as DRAMs – with about 70% leading edge technology; Microprocessors – with 90% leading edge technology; and Flash NAND) an impressive exponential declining cost trend versus time appears, with several swing behaviors [FLA 97, FLA 04, FLA 06, FLA 06b, RUM 03, AIZ 08]. As shown in Figures 2.14 and 2.15, for DRAM and MPU chips after several years with a price decline on average -30 to -40% per year, there has been a “point of inflection” between 1995 and 1999, where price decline accelerated sharply falling at a rate of -60% a year; then, a much slower decline (or even a saturation) over 2001-2004. According to IC Insights, in 2006, the DRAM market grew 32% with DRAM ASP (average selling price) increasing 13%. In contrast, the total IC market grew 9% in 2006 with IC ASP dropping 8%. Moreover, the surge in capital spending in 2006 for DRAM, up 44%, was more than twice the total semiconductor industry increase in capital spending (18%). As a result of this DRAM spending surge, in 2007, DRAM ASP declined 39% in comparison to a 6% decline in industry-wide IC ASP. According to DRAMeXchange, DRAM chip price dropped nearly 75% in 2008 and the industry total loss from Q108 to Q308 was more than $8 billion.. DRAM 667 Mhz 1Gb DDR2 (double data rate, second generation) chip price fell from a high of $2.29 to a low of $0.58, a 75% drop range. The price was not only lower than the cash cost (exclude depreciation) $1 but also close to the back-end testing and packaging price $0.6 to $0.7, and exposed the DRAM vendors to the operating crisis. The worldwide DRAM industry lost $8 billion in the first three seasons of 2008. NAND memory has been on a steeper price decline than DRAM for its entire existence, at an average of nearly 50% per year. While NAND used to be more costly than DRAM, in 2004 it crossed below DRAM. NAND Gb shipments in 2007 were up around 150% over 2006, and prices dropped about 55%, as has occurred every year for the past decade. The average price of a NAND flash member chip plummeted 63% in 2008 and contributed to the global flash memory market declining by nearly 15% last year, according to researcher DRAMeXchange. Overall, revenue of flash suppliers dropped from $13.2 billion in 2007 to $11.4 billion last year, the researcher says. According to DRAMeXchange, the 8 Gb MLC NAND Flash contract price reached $1.63 in October, over a 70% decline from $6.16 of one year ago. Meanwhile, the 16 Gb MLC NAND Flash price also dropped over 80% from

28


$12.8 to $2.22. The revenue decline occurred even though NAND bit shipments increased 117% in 2008. NAND prices declined significantly last year because of intense competition among NAND suppliers for market share combining with excess supply due to overcapacity. As downstream manufacturers continue to launch new products with higher density in 4Q08, upstream suppliers also continue to reduce output. Hynix, Toshiba/SanDisk and Micron have announced to cut output from their 8-inch fab production. Currently, both upstream and downstream of the NAND Flash industry have made efforts to lower inventory level in the market. There is a very wide range of economic literature [FLA 97, FLA 04, FLA 06, FLA 06b, RUM 03, AIZ 08], which tries to explain the reasons for pricedecline and price-swing of semiconductor devices. It is clear that the explanation is very complex and should take into account several factors. Indeed, most of the economists worldwide warn against associating semiconductor price with changes in the pace of the underlying technology, even in the medium long-range. Several other factors, with short-term impacts, undercut the linkage between prices and technology.

Figure 2.13. Price movement of different semiconductor devices [FLA 04]


29

Figure 2.14. MPU and DRAM price index evolution [AIZ 08]. Aggregate price index, [19752004 (annual)], for the period 1992-2004, corresponds to the internal Federal Reserve price index for shipments for NAICS product class 3344131 (integrated circuits); it is extrapolated back to 1977 using an internal Federal Reserve price index for SIC 36741 (integrated circuits); it is then extrapolated back to 1975 using a price index for memory chips constructed by [AIZ 08]. MPU price index [1987:Q1-2004:Q4 (quarterly)], for the period 1992:Q1-2004:Q4, it corresponds to the internal Federal Reserve price index for microprocessors; it is extrapolated back to 1987:Q1 using a matched-model geometric-means index created from quarterly price data for individual Intel MPU chips from Dataquest, Inc. DRAM price index [1975:Q1-2004:Q4 (quarterly)], for the period from 1992:Q1-2004:Q4, it corresponds to the internal Federal Reserve price index for DRAMs; it is extrapolated backward to 1975:Q1 using a series on price per megabit from Dataquest, Inc.

30


Figure 2.15. Price decline of: DRAM ($/one million bits of DRAM), green circles; Intel Microprocessors ($/one million instructions per second), blue squares; $/one million transistors for the industry as a whole, orange triangles; Flash ($/one million bits of Flash) [JON 08]

Several phenomena have been mentioned to explain the behaviors of Figures 2.13 to 2.15. A long-term 30-40% price decline could be related to the technology cost reduction due to the scaling of devices (by following Moore’s law), with a three-year cycle between the technology nodes. Then, the introduction of a two-year cycle between each technology node (i.e. the acceleration of scaling and product cycle introduced by the ITRS road-map since the mid 1990s) could have made the prices fall 40-50%. Nevertheless, the 60% point of inflation at the end of 1990s, and the slow down of price decline in 2001 remain quite anomalous and cannot be related only to technology improvements or manufacturing cost decline [FLA 97, FLA 04, FLA 06, FLA 06b, AIZ 08]. Other reasons have been invoked for these trends, in particular: – Savage competitions between companies in a global context (intensified since mid-1990s) [FLA 97, JUN 06]. Far as μprocessors are concerned,


31

Intel, the world’s biggest chipmaker, and Advance Micro Devices (AMD) have been engaged in an epic battle for market share for many years, this battle is still ongoing today [DAV 06]. In this battle, technology represents only one front of the wars. The other front of μ-processor pricing has been putting pressure on average selling price (ASPs), revenue and ultimately the profits of both companies. With regard to DRAM, major chipmakers (Samsung, Hynix, Sandisk, Micron, Qimonda, etc.) also continue to battle their pricing wars of many years for market share. Compared to the DRAM market, the Flash market is still immature, but it is expected, over time, to undergo a supplier shakeout similar to the DRAM segment [CBR 07]. Today, most chipmakers that produce both DRAM for PCs and NAND Flash for handheld devices (such as Samsung, Hynix, Sandisk, etc.) are periodically shifting their manufacturing capacity to the latter, as a way of offsetting DRAM losses [ICI 07b]. NAND is also under pressure, but seems to have higher margins than DRAM. Nevertheless, this appears to be a shortterm fix, because historically, oversupply swings from one segment to the other. For example, the NAND market lost steam in 2007 due to “massive supply” and maturation of several new factories, which overwhelmed healthy demand. Flash memory chips have become more of a commodity and thus the market is highly volatile. Unit growth has thus far offset price declines in the NAND market, but that will cease to be the case if the supply and demand situation tips unfavorably. – Collusions between DRAM suppliers, in order to slow down the price fall around 2001 and fix DRAM prices, have been demonstrated and convicted (see below [DOJ 07, DOJ 09]). In particular, in June 2002, the USA Department of Justice launched a criminal investigation. Samsung Electronics and its USA subsidiary pleaded guilty and were sentenced to pay a $300 million fine for participating in an international DRAM price-fixing conspiracy (November 2005). The Antitrust Division’s investigation of price fixing in the high-tech DRAM market resulted in total fines in excess of $700 million against DRAM manufacturers Samsung, Hynix, Infineon and Elpida, and 16 DRAM executives were sentenced to a total of 3,185 days in jail for their participation in the conspiracy. Justice Department officials have called the conspiracy “one of the largest cartels ever discovered”. Note that, in September 2007 the Department of Justice Antitrust Division also started investigations into possible anticompetitive practices in the NAND Flash memory market [MAY 07].

32


– Concerning the slow down in the price decline rate of microprocessors after 2001, difficulty in new node introduction at Intel, or resolution of new technical barriers which have at least temporarily slowed down the creation of additional benefits for consumers (and so maturation of the PC market) may explain this trend [FLA 06]. – Price erosion of both DRAM and μprocessors during the last months of 2007 seemed to be related to the excessive hopes that chipmakers had pinned on the release of the Microsoft Vista operating system to drive sales in the first half of the year [CBR 07]. Memory chip makers built too many new production lines in anticipation of strong demand for Microsoft’s Windows Vista, which requires more DRAM per PC. In addition, stronger DRAM prices in general for the past few years were seen by some as a sign that the market had stabilized. Companies have invested so much money in new factories that the increased output has caused a glut, leading to price declines. Contract prices are typically renegotiated between DRAM makers and PC vendors every two weeks. Around four-fifths of all DRAM is sold by contract, while the rest is sold on the spot market, just like commodities such as oil and gold. – After coming back from the 2009 Lunar New Year holidays, the DDR2 1Gb spot chip price went up 25% in one single trading day and closed at its high $1.2. This can be explained by the fact that German DRAM vendor Qimonda declared bankruptcy one hour before the Asian market closed on January 23rd 2009. Two years of consecutive DRAM price drop, even below the vendor’s variable cost (material cost) in 4Q08, caused the German, Korean and Taiwanese governments to provide bail out plans with money funding or aiding by other means the DRAM vendors in order to secure the industry’s future development. For a moment in December 2008, Qimonda saw the light of survival, when the German government, its parent company Infineon, and the Portuguese state bank agreed to fund €325 million. However on January 23rd 2009, information showed that its parent company Infineon had not executed the funding action, and as a result the German government decided to cancel capital support. Qimonda declared bankruptcy. – NAND Flash price started to rebound in December 2008 after Hynix phased out its 8 inch fab in September, thus lower its NAND Flash capacity by 70%, and Toshiba’s 30% capacity cut on its 12 inch fab. 8 Gb and 16 Gb MLC contract prices rose 70% and 50%, respectively, from a low of $1.05


33

and $1.65 which was close to the makers’ material cost of US$1.82 and US$2.46, which was close to the makers’ cash cost. To remain above the current prices, NAND Flash makers have had to keep the scale of capacity cut and even reduce it further as the demand turned down in 1Q09. According to major consumer electronics makers’ 4Q08 earning release, most have suffered from sales shrinking. From the recently announced 4Q08 financial reports and product shipment numbers of the worldwide major consumer electronics vendors, almost everyone was influenced by the global financial crisis. Though NAND Flash makers continue to adjust their supply, further price trends will depend on whether upstream suppliers continue to reduce production in order to meet the market’s declining demand. 2.7. Moore’s Law, the ITRS and their economic impacts The dynamism of the integrated circuit industry is directly linked to the rapid change in information processing technologies. In 1965, Gordon Moore, director of R&D at Fairchild Semiconductor wrote a paper for the journal Electronics entitled “Cramming more components onto integrated circuits” [MOR 65]. In the paper Moore observed that “the complexity for minimum component cost has increased at a rate of roughly a factor two per year”. This observation became known as Moore’s law. Moore’s law was later amended to, the number of components per IC doubles every 18-24 months [JON 08]. Moore’s law has held true for nearly 40 years (see Figure 2.16). The popular perception of Moore’s Law is that the average cost per chip (with increasing computational power or capacity, and inside increasing transistor density) has remained nearly constant over that time period.

34


NAND DRAM

Early Logic

Intel X86

Figure 2.16. Graphic representation of Moore’s law for DRAM, microprocessor and Flash [JON 08]

The ability to cram more components onto each chip at the “minimum cost” was obviously driven by an exponential reduction in the cost of each single transistor. An economist’s corollary to Moore’s Law describes the cost trends for integrated circuits, as follows [FLA 04]: $ processing cost area "yielded" good silicon x silicon area/chip $/component= components/chip

where each of the variables on the right-hand side has a well defined economic or technical meaning.


35

Moore’s Law, strictly speaking, is about the denominator only. Moore, basically, by predicting that the number of transistors packed onto a silicon chip would double every year for the next decade (and therefore increase by a factor of a thousand in a decade), also predicted that the cost per on-chip component would fall by a factor of ten every five years (or a factor of 100 every decade). This latter prediction amounted to a 37% annual decline in transistor cost. It is important to point out that in the first version of Moore’s Law, he considered that ICs could be manufactured using existing feature sizes and manufacturing technology [FLA 04]. This follows from the assumption that costs per chip at that time were dominated by packaging costs and were assumed to remain constant on a per-chip basis. Later (by 1975), however, chip costs were no longer dominated by packaging of the silicon chip; processes carried out to make the chips in increasingly expensive, high-tech, capital-intensive fabrication plants accounted for the vast bulk of the cost, and packaging for relatively little. So, rather than simply increasing the size of the chip to achieve the greater number of devices (components) per chip, manufacturers instead used “finer scale microstructures” to engineer a higher density of components per chip. In the past 40 years, reduction of the bit cost has been addressed through different paths: – First, component feature size (and consequently area) has shrunk dramatically (see Figure 2.17). Shrinking linewidths (and thus smaller transistors) not only enables more components to fit onto an IC (typically 2x per linewidth generation), but also lowers costs, because more transistors are produced per processing step (typically 30% per linewidth generation) [JON 08]. This miniaturization has been the result of ever improved technologies, in particular microlithography.

36


Figure 2.17. Feature size shrink, according to [JON 08] (top) and [CHA 05] (bottom)

Second, the size of the average chip has increased, but substantially less than the factor associated with the increased density due to the introduction of a new technology node (see Figure 2.18). Shrinking linewidths have


37

slowed the growth rate in die size to 1.14x per year versus 1.38 to 1.58x per year for transistor counts. Since the mid-1990s, accelerating linewidth shrinkage has halted and even reversed the growth in die sizes [JON 08]. For example, after roughly a decade in which further generations of DRAMs in essence scaled down the basic DRAM design of the mid-1970s to smaller dimensions, a period of vigorous innovation began in the late 1980s; during which 3D memory cells were developed. In addition to 3D features in memory cells, use of additional interconnecting levels allowed tighter packing of components on a chip, and other types of products moved closer to the leading edge in their use of advanced manufacturing process technology. Thirdly, the size of the silicon wafers has gradually increased, making more chips per process run (see Figure 2.19). The move from 100 mm (4 inch) wafers to 150 mm (6 inch) wafers increased the silicon area by 125% – the same relative gain that will be realized when semiconductor companies make the transition from 200 mm (8 inch) wafers to 300 mm (12 inch). Beyond 300 mm, the same gain requires a jump to 450 mm wafers. Trends indicate that wafer size transitions industry-wide have typically enabled a 4% per year productivity improvement in terms of lower IC cost/cm2 [AND 97]. Going back to 1975, the industry moved fairly rapidly from 100 mm to 125 and 150 mm, with each transition taking about three years. The move from 150 to 200 mm took a little longer (five years) and the move to 300 mm took eight years. Today, all new fabs built are 300 mm fabs. The next big step in chip manufacturing will be the industry’s move from 300 mm wafers to 450 mm wafers [ITR 05, SHA 08]. Chip makers Intel, Samsung Electronics and Taiwan Semiconductor Manufacturing announced in 2008 they will collaborate to move chip manufacturing onto 450 mm silicon wafers, with pilot tests to start in 2012. In fact, as we get down to 22 nm and smaller, the complexities of delivering that particular device are problematic with cost and productivity at 300 mm and it is preferable to move to the next wafer size. Moreover, to improve manufacturing efficiency, today, wafer fabs are completely automated and advanced process control is taking a predominant position. Obviously, this also means that the market “should” increase proportionally.

38


Figure 2.18. Die size trend according to [JON 08]

Figure 2.19. Wafer processing cost (leading edge logic, Greenfield fab, SEMATECH) [FLA 06]


39

Whether or not Moore’s law will breakdown one day is still an open question. Several scenarios are generally invoked [FÖL]. One of the problems will be that the chips become very hot. Another physical limit will be the atomic limit – the indivisibility of atoms. Given the minimum dimensions which have been reached for logic transistors today (i.e. a few nanometers), it is quite clear that we are close to the end of CMOS technology scaling, and that the technology and economic efforts currently in progress worldwide in order to push further the scaling limits are facing very serious difficulties. It is worth noting that, even if Moore’s Law, as its author has repeatedly insisted over the years, it was really an observation, not a law of physics, in the final analysis, from a simple observation (plot), it became an imperative (law). In other words, Moore’s Law was taken as the rule of the game for competition among semiconductor companies, as clearly explained in the works of Prof. Kenneth Flamm from the University of Texas at Austin [FLA 97, FLA 04, FLA 06, FLA 06b]. In 1987, as a reaction to the Japanese VLSI Projects (launched in 1970 by the Japanese government), the USA government decided to have the Defense Department pay half the cost of a joint industry consortium, dubbed SEMATECH (for semiconductor manufacturing technology) and budgeted at $200 million annually. SEMATECH had a clear objective: to regain the reduced US share of the world semiconductor market, and to coordinate the US semiconductor industry through the so-called roadmap process. In 1992, the first “national technology roadmap” was published. Since its inception in 1992, a basic premise of the roadmap has been that continued scaling of microelectronics would further reduce the cost per function (historically, ~25-29% per year) and promote market growth for integrated circuits (historically averaging ~17% per year).

40


Thus, the roadmap has been put together in the spirit of a challenge, essentially: “What technical capabilities need to be developed for the industry to stay on Moore’s Law and the other trends?” [ITR 02]. So the roadmap was a way to have a pre-competitive frame where materials and equipment suppliers jointly work out details of a complex array of likely new technologies required for manufacturing next-generation chips, coordinate the required timing for their introduction, and intensify R&D efforts on the pieces of technologies that were likely to be “showstoppers” and required further work if the overall schedule was to succeed. The International Technology Roadmap for Semiconductors (ITRS) was created in the late 1990s. The invitation to cooperate on the ITRS was extended, by the Semiconductor Industry Association (SIA) [SIA] at the World Semiconductor Council in April 1998, to Europe, Japan, Korea and Taiwan. Since then, full revisions of the ITRS were produced in 1999, 2001, 2003, 2005 and 2007. ITRS updates were produced in the even-numbered years (2000, 2002, 2004, 2006 and 2008). Focusing on this challenge, the emphasis was given on a significant reduction in the elapsed time between introductions of new technologies [FLA 97, FLA 04, FLA 06, FLA 06b, ITRS]: – From the mid-1970s to the mid-1990s, DRAM products set the technology pace by quadrupling the number of bits every three years with the introduction of a new major technology generation. The relation among transistor density (4×) and metal half-pitch (0.7×) and year of introduction (3 year, in agreement with Moore’s law) remained constant. The reduction from generation to generation of the DRAM half-pitch of metal by 30% (0.7× the previous technology generation) was identified as a “technology node”. – In the second half of the 1990s, however, the increase in the number of bits by 4 times from one technology node to the next led to a continuous


41

increase in die size that eventually negatively affected the economics of this silicon cycle. In an attempt to minimize the increase in die size many IC companies accelerated the speed at which new technology nodes were introduced from a 3 year cycle to a 2–2½-year cycle. So, the so-called 250 nanometer technology node was introduced a year earlier than called for in the 1994 Roadmap, and the 1997 National Technology Roadmap called for the next technology node (at 180 nm) to follow after another 2 year interval rather than reverting to the 3 year pattern. It is clear that since 1994 the ITRS has been accelerating the scaling of CMOS devices to lower dimensions continuously, despite the difficulties that appear in device optimization (see Figures 2.20 and 2.21).

Figure 2.20. Continuous acceleration of scaling in the ITRS Roadmap [DEL 06]

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Figure 2.21. ITRS Roadmap Acceleration (2001) [TRY 02]

It is far from clear if this acceleration of technological improvement in the semiconductor industry was solely the result of decisions taken within the membership of the USA SEMATECH consortium and the broader industry, government and academic coalition participating in the USA national technology roadmap process. In fact, Korean producers had become major players on the World semiconductor scene, and Taiwanese manufacturers were rapidly becoming a significant force. Accelerating competitive pressures, and intensifying efforts to more rapidly deploy new technology, was certainly felt, by USA chip producers, to be a logical economic response [FLA 97, FLA 04, FLA 06, FLA 06b]. Moreover, the


43

identification of R&D requirements and explicit coordination of R&D efforts through an industry-wide program was a novel and important development. In fact, other institutional changes coincided with this industry-wide shift toward a 2 year technology node pace. In 1995 a decision was made by SEMATECH to partner with foreign companies in a project aimed at accelerating the development of technology designed for use with 300 mm (12 in.) silicon wafers. In the fiscal year 1996, USA government funding for SEMATECH ended by mutual agreement. In 1998 a separate organization, International SEMATECH, was formed as the umbrella for an increasing number of projects in which non-USA chip producers were involved. SEMATECH was also certainly perceived as a major force in Japan, where the SEMATECH model greatly influenced the formation of a new generation of semiconductor industry R&D consortia in the mid-1990s. The Japanese semiconductor industry’s R&D consortium, known as SELETE, was joined by Korean producer Samsung [FLA 97, FLA 04, FLA 06, FLA 06b]. In 2003, SEMATECH spun off a subset of R&D activities into the International Semiconductor Manufacturing Initiative (ISMI), which walled off access to the “highest tech” activities (e.g., lithography). In September 2004, the “international” designation of SEMATECH was dropped, though the organization still has many full international members. Today, among the main industrial partners of SEMATECH are AMD, Hewlett-Packard, IBM, Infineon, Intel, Samsung, Texas Instruments, TSMC, Panasonic/Matsushita Electric, Spansion, Renesas and NEC. Many economists have underlined the critical economic impact of the move from a 3 year cycle to a 2 year cycle in the introduction of a new technology node [FLA 97, FLA 04, FLA 06, FLA 06b]. Rather than simply accepting a historical norm, it was decided to alter the norm by trying to explicitly coordinate the now-complex array of decentralized pieces of technology that had to be simultaneously improved in order to bring a new generation of manufacturing systems online. Technology node acceleration had a big impact on manufacturing costs, with a shift of manufacturing processes for some products closer to the leading edge in technology, and a shortening of product lives accompanying more frequent introductions of new versions of certain products. Technology node acceleration increased the speed of declines in price and gave rise to intensified competition, ending in some consolidation of this global industry seeing the least successful companies exit the industry. Finally, interestingly Moore’s Law has been interpreted as a case of an informal institutional framework for “analyzing”

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technical change that gradually evolved into a more formally structured process for “organizing” technical change in a major global industry. There was nothing inevitable about Moore’s Law, no underlying technical or physics-based reason for the phenomenon. Nevertheless, it is clear that companies made their technical plans around a Moore’s Law timetable. This was probably not because that schedule would necessarily have maximized their profit, but because they believed that all their competitors would be introducing new products and technology on the Moore’s Law schedule and that, therefore, they too had to stick to the plan in order to stay competitive. This certainly seems to have been the case in DRAMs: the pacing product for new semiconductor manufacturing technology, where a three-year next generation product introduction schedule became an accepted characteristic of the market. It may be impossible to determine the extent to which the coordination process played a role, or the extent to which the simple act of a major group of IC producers announcing new and very specific technology targets created a credible reason for the various suppliers of technology to believe that the technology cycle really was about to accelerate, and therefore caused it to accelerate [FLA 97, FLA 04, FLA 06, FLA 06b]. What is clear is that the industry roadmap – the ultimate descendent of Moore’s Law – has now become an organizing and coordinating framework for private and public R&D in what is the largest, most important, and most globalized manufacturing industry in the world. Today, the ITRS documents remain a truly common reference for the entire semiconductor industry [ITRS]. Aggressive targets, in order to maintain the historical high rate of advancement in integrated circuit technologies, are still given. A good example of that is the adoption of 2012 as the year of introduction of 450 mm wafers in volume production in the 2005 ITRS edition, “a date which is not based on an economics model, but is as a way to induce the working groups to focus on the various technical issues associated with such a transition to 450 mm”. Moreover, it is worth mentioning that, while the ITRS has traditionally focused on Moore’s Law (i.e. geometrical scaling of horizontal and vertical physical feature sizes of the logic and memory devices), starting from the 2005 edition, the new roadmaps complement that with “More than Moore,” also known as functional diversification (see Figure 2.22). In fact, digital circuitry – mostly processors and memory – will continue to scale according to Moore’s Law. Specific issues identified are the increasing process variability and expected physical and reliability


45

limitations of devices and interconnects, as well as the need for new circuit architectures and characterization methods and techniques. There also exist other technologies, related to sensing and interacting (like analog circuitry, i.e. RF for wireless, sensors/actuators, passive components, high voltage devices and even bio chips), where miniaturization isn’t the main driving factor but which account for roughly half of the wafer starts. “More than Moore” focuses on the integration of all these kinds of functions on a single chip, through heterogenous system-on-chip (SoC), but also with system-inpackage (SiP), i.e. integration of different types of chips and devices in a single package, or compact subsystem. Specific identified issues are power consumption, electro-magnetic interference and heat dissipation. It is worth mentioning that for a large number of IC companies, Moore’s Law is no longer the driver. According to the CEO of Infineon Wolfgang Ziebart [FUL 07], competitiveness is no longer necessarily connected to ever-shrinking geometries. “Twenty years ago about 70% of all chips were manufactured using the latest technology generation, today this is true for only about 40%-20% – basically for memory chips and processors. Beyond these two application segments, the latest technology is only a factor in mobile communications. Today, equally important for the competitiveness are system competence and application knowledge”.

Figure 2.22. Moore’s Law and More than Moore, according to ITRS 2005 [ITR 05]

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2.8. Exponential growth of manufacturing and R&D costs What can stop a company following Moore’s law (and open the path to industrial consolidation) is a second empirical law claiming that: “As chip density increases exponentially, the cost to set up manufacturing also increases exponentially”. Let us take the case of photolithography, which is a very critical step for definition of extremely scaled features (Figure 2.23). The minimum feature size (F) in photolithography is given by: F= (k1)(O /NA, where Ois the exposure wavelength, NA is the numerical aperture of the lens system in the photolithography tool (with typical values of 0.5 to 0.8), and k1 is a process related term (with typical values of 0.7 to 0.4). The reduction of F has been achieved by periodically going to smaller and smaller exposure wavelengths. Photolithography is now operating at a deep ultraviolet (UV) wavelength of O = 193 nm. The primary candidate for next generation lithography is believed to be extreme ultraviolet lithography (EUV) that operates at O= 13.2 nm. EUV lithography would make it possible to achieve the integration levels needed for NAND Flash memory of 64-256 Gbit capacities, and μprocessors with 1.6-6.4 billion transistors. This is 4 to 16 times higher than the integration levels of cutting-edge IC today. Note that today, the most aggressive geometry shrinks are taking place in the NAND Flash segment, followed closely by DRAM and then highperformance logic devices (Figure 2.24). Flash devices are characterized by the densest pitches, so the strongest resolution enhancement techniques (RETs) are typically used. In some ways, Flash manufacturers have become the drivers of advanced lithography techniques, since they will be the first to incorporate them.

Figure 2.23. Slashing the lithography wavelength to drive further geometry shrinkage [KIM 07]


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Figure 2.24. The different imaging requirements of leading-edge devices [PET 07] (source: ASML). Because of accelerations in cell-size scaling, NAND flash has surpassed DRAM as the most aggressive CD

This continuous reduction in wavelength has been combined with highly sophisticated designs of lenses, mirrors and advanced and complex masks, innovation in materials, processes, and precision machines. However, with shorter wavelengths, there are long lists of new and substantial technical challenges. At O= 13.2 nm, there are no known


49

transparent materials; therefore all the optical systems and photomasks are based on reflective optics. In addition, obtaining a source with sufficient power at this EUV wavelength is still an open problem. Moreover, it could happen that rather than physical limits, prohibitive costs will make the traditional approach of decreased wavelength impractical. Even today, optical lithography is an extremely expensive unit process [GOD 05]. Historically, the cost of optical exposure tools has increasing exponentially (see Figure 2.25). Even if fundamental challenges are overcome at 13.2 nm, it is believed that the historical exponential increase in tool cost could become even steeper. In addition to tool cost, there exist the recurring and consumable costs associated with process materials, environmental control, complicated photomasks, developing mask sets, etc., which are unique to every product, and usually every fab. Indeed, all these factors make next generation lithography a high-risk proposition. Based on previous considerations, it follows that semiconductor manufacturing cost will continue to climb in the future. High-volume 300 mm production fabs cost $2 to $3 billion, with equipment expenditures accounting for more than 80%. The price tag for building modern chipmaking facilities has been increasing by about 10-15% annually, resulting in a doubling of fab cost every 4 or 5 years (see Figure 2.26). Note that in the second quarter of 2008, 300 mm wafers passed 200 mm wafers as the highest production volume wafer size on a square inch basis [JON 09] and announcements of 200 mm fab closings by memory producers in favor of lower cost 300 mm production are quite usual. IC Knowledge also forecasts 84 operating 300 mm fabs at the end of 2008, 98 operating 300 mm fabs at the end of 2009, and 111 operating 300 mm fabs at the end of 2010. A total 300 mm wafer capacity is forecast to be 30.20 M wafers in 2008, 36.62 M wafers in 2009, and 44.36 M wafers in 2010.


$US Thousands

50

Figure 2.25. The exponential increase in cost of (top) lithography tools [GOD 05], (bottom) masks sets [MCG 07]

Moreover, the cost of developing the process technology continues to rise with each generation (see Figure 2.27). On average, the cost of each process generation increases between 40%-50%, which results in an exponential


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Fab Cost ( $US Billions)

trend. The total cost of developing 90 nm is around $500 million, while the expense of developing upcoming technology nodes is projected to approach $1 billion. State-of-the-art 90 nm and 6 nm fabs reached an average cost of nearly $5 billion. Several analysts estimate that for chipmakers, process development costs for 32 nm could hit $3 billion (twice the level for 65 nm process technologies) while costs for a 32 nm fab are estimated to reach $3.5 billion. Finally, it clearly appears that the only way for a company to recover these costs is to have high throughputs, long tool lives, long photomask lives; and excellent feature fidelity within a chip, between chips and between wafers. Now, the rule of thumb in the industry is that a fab has to generate annual revenues at least equal to its capital cost to generate a reasonable return on investment [RUM 03], so having a business which drives high-volume. With new cutting edge fabs costing $5 billion, few firms in the industry had revenue streams sufficient to justify such an expense. For a 300 mm wafer fab to break even, a throughput of 10,000 wafer starts per week is required. For most IDMs, the demand of a single chip vendor, producing in 65 nm geometries is scarcely enough to utilize such a production line to full capacity. Outsourcing consequently becomes the general trend for many chipmakers (in particular for advanced technologies). Business models of the semiconductor industry have been largely modified in recent years (see section 2.9).

Figure 2.26. Exponentially increasing cost of semiconductor fab capacity [MCG 07]

Figure 2.27. Average development cost trend of semiconductor process nodes [MCG 07]

$US Millions

52 Silicon Non-Volatile Memories


53

Figure 2.28. Chip making R&D versus revenues [HUT 05]. Fab costs escalate faster than revenues

Furthermore, process R&D costs have been increasing rapidly with each new technology node and now outpace the semiconductor revenue growth rate (see Figure 2.28). Various factors contribute to rising R&D expenditures, including steep fab and equipment depreciation and wafer/materials costs (by far the largest contributors); the high cost of introducing new processes (e.g., high-k dielectrics); skyrocketing mask costs; and ever-more-expensive designs. Most technology development takes place in either advanced pilot lines or volume manufacturing wafer fabs. As already mentioned, on the equipment side, the total cost of developing the latest lithography tools is believed to be in the $500 million to $1 billion range. The semiconductor industry in recent years has typically invested 12-15% of its revenues in R&D (the investment by SIA members increased from $2.6 billion in 1990 to $14 billion in 2003) and this percentage is predicted to increase significantly in the next few years [HUT 05].

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According to the IC Insights’ 2007 McClean Report [ICI 07], total worldwide semiconductor industry capital spending surged 18% to $54.75 billion in 2006. This figure represented 22.1% of total semiconductor sales last year. Capex, as a percentage of semiconductor sales, went from an average of 27% in the late 1990s to 21% in the early 2000s. Moreover, IC Insights forecast that capital spending as a percentage of sales will average only 17-18% between 2008 and 2012. In 2006, capital spending for additional Flash memory capacity jumped 35% to $11.5 billion. DRAM capital spending increased a whopping 44% last year to $13.9 billion. Figure 2.29 shows the 2006 capital spending as a percent of sales for the major semiconductor product segments, and examples of “irrational” capital spending of DRAM and Flash memory producers [ICI 07b]. As shown, Flash memory spending as a percent of Flash sales reached 57% in 2006, more than 2.5x the industry average. In 2006, Flash unit shipments grew 32%. However, after the huge capital spending outlays in this segment, it is not surprising that the average selling price for a Flash memory device collapsed significantly in recent years. The DRAM market was one of the shining stars in the semiconductor industry in the last years. In 2006, in the DRAM segment, capital spending as a percent of sales was 41%, almost twice the 2006 industry average. The result (the immutable law of supply and demand) caused a severe decline in DRAM prices, even in the face of good demand. The main explanation for the high capital spending in 2006, was the 2006 DRAM market growth (+32%), which made rational thinking fly “out the window”, and DRAM suppliers overspend for new production facilities [ICI 08]. According to IC Insights, what caused a 32% DRAM market surge in a single year (2006), when the total IC market increased only 9%, was the under-spending in the previous two years. The 2006-2007 DRAM capital expenditures ($34.3 B) were 78% greater than the amount spent in 20042005 ($19.3 B). After looking at the figures, it is easy to see why the 2008 DRAM market was in such a slump. This overspending resulted in the disastrous conditions felt in the DRAM market and forecast to decline over 20% in 2009. In 2009, DRAM manufacturers are severely overreacting to the current downturn in the DRAM market. This overreaction is in the form of slashed capital spending outlays that will leave the DRAM producers unable to meet strong demand in 2010 and 2011. The result will probably be surging


55

average selling prices for DRAM devices beginning in 2010. Historically, the DRAM segment has been the leading example of extreme market volatility in the IC industry. DRAM producers budgeted to spend 12% less on capital expenditures. In 2008-2009 than they spent in 2004-2005.

Source: IC Insights

Capital spending in:

2004

2005

2006

Powerchip

$600 million

$1.3 billion

$2.6 billion (92.3% of sales)

$439 million

$910 million

$2.43 billion

$4.38 billion (55%)

Nanya Hynix

$1.46 billion

Micron

$1.69 billion

SanDisk Toshiba

$ billion

Elpida

36% of sales

Samsung

$7.0 billion

2007E

1.4 billion (100% of sales)

$4.0 billion

Figure 2.29. Top: 2006 capital spending as a percent of 2006 semiconductor segment sales. Bottom: Capital spending of main memory chipmakers [ICI 07b]

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2.9. The structural evolution of the semiconductor industry The maturing of the IC industry has been accompanied by several structural reorganizations [WU 03] (see Figure 2.30). On one side, since its creation, the IC industry has been transitioning from a vertically integrated structure, in which a single company would perform the entire semiconductor production process, to a horizontal structure with many specialized and focused segments, where separate companies focus on the different stages of the industry value chain. On the other side, consolidation by sector has also happened, the main consequence of exploding costs being the trend toward “alliances”, both at the manufacturing stage and in research/development of new technologies. The disaggregation into specialization process occurred in different stages. At the beginning, in the 1970s, traditional monolithic integrated design manufacturers (IDM), such as Intel, Motorola, IBM, Infineon, Toshiba, etc., vertically integrated the entire semiconductor process; offering silicon, libraries and macros, tools and service. In the 1980s-1990s, the organizational separation between semiconductor product design and semiconductor process manufacturing appeared. This phenomenon-has been a structural response to semiconductor firms’ requirement for faster product and process development to be able to meet demand [MAC 01]. The resulting supply chain included IDMs, design fabless houses (such as Qualcomm, NVidia, Xilinx, Broadcom, etc.), functional-IP (Intellect Property) suppliers, pure-play foundries (TSMC, UMC, Chartered, etc.), and contract manufacturers for test.


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Figure 2.30. Diagram of the structural evolution of the semiconductor industry

Currently, chip-makers continuously redefine their business strategies in an effort to survive the economic pressures. IDMs which cannot sustain the economic pressure are now turning to a “fab-lite” strategy. In other words, they are simply no longer investing in in-house manufacturing for chips that are to be made using standard technologies. To survive in a very competitive business, the “foundry” model provides a shared semiconductor manufacturing resource to smaller semiconductor companies. Since 2001, IDMs have increasingly outsourced manufacturing to foundries (for example, AMD/UMC 2002, AMD/Chartered 2006, AMD/TSMC 2007, Freescale/TSMC 2006, Freescale/UMC 2006, PhilipsSTM/TSMC 2000, TI/TSMC, Atmel, etc.) and focus on product diversity (SOC, etc.). IDMs, today, invest only into self-production in cases where a close entanglement of technology development, product design and the manufacturing process is necessary in order to yield a strong competitive position (see Figure 2.31). Processing in-house mainly continues for memory and μprocessors.

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Currently, the disaggregation trend still ongoing, as IC companies are refocusing on core competencies and unloading unprofitable and sometimes debt-ridden businesses. So, several electronics manufacturers spun-off their semiconductor operations (for example, Siemens/Infineon 1999, Motorola/ Freescale 2004, Philips/NXP 2006, etc.). It is worth mentioning that semiconductor companies have been a recent focus of private-equity firms, even if they seem less motivated in this last period due to the financial crisis [MAN 08]. The 2006 purchases of NXP and Freescale, with very high prices paid, resulted in a heavy debt burden loaded onto the companies when the private equity people sold NXP and Freescale on to bond-holders. It has also been argued that the private equity ownership of semiconductor companies stifles innovation, as private equity owners have no incentive to invest in longterm research. The unfortunate situation of NXP in recent years dramatically illustrates this phenomenon. Moreover, several IDMs spin-off their memory businesses (for example, Spansion from AMD/Fujitsu 2003, Qimonda from Infineon 2006, Numonyx from ST Microelectronics and Intel 2008, etc.) because they cannot profit in the memory market. Most of the mother companies continue as logic and system chip companies while pursuing a “fab-lite” strategy and using foundries. Combining memory operation and logic operation in the same company became very difficult due to the different volumes (and consequently capital investments) needed. According to the Intel Annual Report, NOR Flash memory business has lost money for several successive years. In 2005, the Flash business had a $154 million operation loss on revenue of $2.28 billion. Today, several spin-offs are in a very bad situation. Qimonda filed for insolvency under the German law in January 2009. In February 2009, the Japanese subsidiary of flash memory chip maker Spansion Inc. filed for bankruptcy protection with debts of more than US$800 million.


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Figure 2.31. (Top) The IC technology landscape and (bottom) collocation of main chipmaker companies, according to [BRI 07]

Aggregation is going on in several specific sectors. In particular: – Consolidation of manufacturing in Asia-Pacific is occurring (see Figure 2.32), with China as the major beneficiary with 20 new fabs in 2006. In fact, relatively few companies control a very large portion of the IC industry’s supply of wafer fab capacity. According to IC Insights [ICI 09], the top-five capacity leaders accounted for 32% of total wafer capacity as of year-end

60


2007. At the same time, nearly half (48%) of the world’s capacity was represented by the combined capacity of the top-10 leaders. It is interesting to note that two of the largest capacity holders are the pure-play foundries, TSMC and UMC, both located in Taiwan. Taiwan’s chip production increased by 226.2% from 1995 to 2000. Taiwan will have the world’s largest amount of fab capacity by 2009 (in 2008, 300 mm wafers became the highest volume wafer size). Although Taiwan is also the world leader in semiconductor assembly, it is facing increasing pressure to locate facilities on the mainland in order to exploit the Chinese market and to better service mainland exporters by offering quicker turnaround times. Investments of foreign companies are increasing in China. In March 2007, Intel announced a $2.5 billion investment for 300 mm wafer fab in China, which was to become Intel’s first wafer fab in Asia. Note that installed fabs produce technologies with different minimum feature sizes in different regions. According to [ICI 09] more than one-fourth (29%) of all wafer capacity in 2008 has been for devices having geometries or feature sizes smaller than 80 nm. Such devices include high-density DRAM and flash memory devices that are based on 70 nm, 60 nm, 50 nm, and 40 nm technologies and highperformance MPU/MCU/DSP devices and advanced ASIC/ASSP/FPGA devices based on 65 nm and 45 nm technologies. South Korea, Taiwan, and the Americas are more leading-edge focused than other regions or countries. Europe has the highest concentration of “old” technologies with feature sizes greater than 0.4 μm. Given its emphasis on high-density DRAM and flash memory products, South Korea has the largest share of wafer capacity dedicated to leading-edge processes (45%). The Americas are next in line with 37% of their capacity using the most advanced processes, followed by Taiwan with 32%. – Alliances between manufacturers of DRAM and Flash also happened (Toshiba-SanDisk, PowerChip/Renesas, PowerChip/Elpida, Intel and Micron, Spansion/Saifun/UMC, STMicro/Intel, etc.). See section 2.10.

Figure 2.32. Manufacturing capacities by region [WFR 07]


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– Most chipmakers also embraced various cost- and risk-sharing R&D partnerships for leading-edge technologies: - The IBM Fishkill alliance is an example of competitive companies joining forces to ease the R&D spending burden for the development of next-generation semiconductor manufacturing technologies. At the heart of the “Common Platform” technology relationship (see Figure 2.33) is the bulk CMOS process technology that is jointly developed by IBM, Chartered, and Samsung. The group began with joint development of the 90 nm process node and has extended the joint development to lower node processes. In addition to the three manufacturing partners involved with the Common Platform, Infineon and Freescale participate as joint development partners. At the same time, IBM and AMD have been collaborating on the development of next-generation semiconductor manufacturing technologies on SOI (sSilicon-on-insulator) since January 2003. Sony and Toshiba are also participating in the SOI development alliance at IBM’s Semiconductor Research and Development Center (SRDC) in East Fishkill. On July 2007, STMicroelectronics and IBM signed a cooperation agreement to jointly develop the next generations of silicon chip technology. The agreement came shortly before the termination of the Crolles 2 Alliance (in France), at the end of 2007. Note that IBM is strongly supported by the USA government. In fact, to address national security concerns, the USA Department of Defense is contracting with IBM to provide a secure source of advanced chips tailored for defense and intelligence applications. In April 2009, CEA/Leti (the Electronics and Information Technology Laboratory of the CEA, based in Grenoble), and IBM announced that they will collaborate on research in semiconductor and nanoelectronics technology [IBM 09]. This five-year agreement is focused on advanced materials, devices and processes for the development of complementary metal oxide semiconductor (CMOS) process technology for the production of microprocessors and integrated circuits at 22 nm and beyond. With this agreement, CEA/Leti becomes a research associate of IBM and IBM’s semiconductor Joint Development Alliance ecosystem centered in Albany, N.Y. CEA/Leti will reinforce this ecosystem through its specific expertise in low-power CMOS (such as SOI technologies), in e-beam lithography and in nanoscale characterization and modelling. This agreement strengthens the links between the IBM and Crolles-Grenoble ecosystems, following STMicroelectronics’ decision to join the IBM Alliance in 2007, for the development of core CMOS and value-added application-specific derivative technologies and industrialization of these processes.


63

- Top-tier foundries (as TSMC, UMC, etc.) also offer R&D solutions to fabless or fab-lite chip suppliers. In fact, it is reasonable to assume that manufacturing of logic semiconductors at 32 nanometers and below will in future be handled exclusively on the platforms forged by the alliances. It follows that “foundries” will continue to gain importance in this context, and will themselves influence the course of change in the chip industry. - The Advanced SoC Platform Corporation (ASPLA) was formed in 2002 by eleven Japanese IDMs to jointly develop process technology at 90 nm and beyond. The ASPLA includes Fujitsu, Hitachi, Matsushita, Mitsubishi, NEC, Toshiba, Oki, ROHM, Sanyo, Sharp and Sony. Note that Toshiba and Sony are also in IBM’s SOI development alliance.

Figure 2.33. Evolution of the “Common Platform” technology alliance (http://www.commonplatform.com, 2007)

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Another trend is outsourced collaborative R&D alternatives such as Sematech’s Advanced Technology Development Facility, Cypress Semiconductor Silicon Valley Technology Center and LSI Logic’s Orgeon fab University, industry, and government-affiliated R&D efforts, such as Sematech, LETI, IMEC, Selete. 2.10. Consolidation of the semiconductor memory sector The memory sector, which as previously mentioned is one of the most competitive, has also seen very important changes in the last few years. Due to impressive falling prices, owing to very high volumes (with excess supply possibilities), and very high capital investments (and consequently very high risks), manufacturers of DRAM and NAND Flash are in the process of coalescing into just a few groups to share both development and fab costs. According to research released by Strategic Marketing Associates, the sum required to build and equip a state of the art DRAM or Flash fab is becoming too large for a single company to go it alone. They estimated that the Toshiba-SanDisk joint venture, Flash Alliance, will spend as much as $10 billion to fully equip their newest fab. Many manufacturing companies upgraded their production lines and increase their capacity in order to increase market share and decrease costs. The 300 mm Fab 4 of Flash Alliance will have a capacity of 210,000 wafers a month. According to the report, the average capacity of a 300 mm DRAM or NAND Flash fab rose from 40,000 wafers in 2004 to 60,000 by the end of 2006 and should reach 80,000 wafers in 2009. Increasing capacity increases cost which, in turn, pushes manufacturers to seek alliances. Except for Samsung and ProMOS, all major DRAM and NAND flash memory manufacturers have formed joint manufacturing ventures that involve technology licensing as well as development. These alliances include: Inotera Memories, Inc. founded as a joint venture by Qimonda AG and Nanya Technology Corporation on January 23rd, 2003 to manufacture high-density and high-performance commodity DRAM products using state-of-the-art trench technology; PowerChip/Renesas, named Vantel (focus: NAND development), March 2007; PowerChip/Elpida, named Rexchip, DRAM development, December 2006; Toshiba/SanDisk; Intel and Micron, IMFlash alliance formed at the


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end of 2005; Hynix/SanDisk joint venture since 2007 to develop and make flash memories and NAND memory systems based on four-bit-per-cell x4 flash technology; Spansion/Saifun. As a group, these companies will more than double their DRAM and NAND flash capacity by the end of 2010. The total cost of these DRAM and NAND fabs will exceed $100 billion. This growth would not be possible without these alliances. The value of new fabs beginning production in 2007 has been $31 billion, 58% of which will be DRAM and NAND. The DRAM market is often considered to be one of the most relevant examples of consolidation due to high competition. Let us look at the history of the DRAM market. The connection to USA national security made semiconductors a focus for government interest even before their economic importance became apparent [SPI 07]. In the early 1970s, as steady progress in creating denser, cheaper integrated circuits continued, two revolutionary new products critical to this goal were introduced. In 1970 the first dynamic random access memory (DRAM) chips were rolled out by American companies. DRAM made large, cheap arrays of digital storage available to electronic system designers in a standardized, “commodity” format, accessible on a single chip. In 1971, the first microprocessor – the essentials of a very simple computer, squeezed onto a single chip – was introduced by Intel. Together, these two products rapidly grew into large portions of the market, and paced the introduction of new technology for the entire semiconductor industry. Meanwhile, the Asian semiconductor industry began in the 1960s with small pockets of foreign investment, however, quickly grew as countries nurtured their own industries. Japan was the first to establish a significant semiconductor industry in the 1970s. In 1979, Fujitsu surprised the World when it became the first to mass produce 64 kilobit memory chips. By the mid-1980s, Japan had cornered much of the memory chip market and surpassed the USA in semiconductor production. This rapid growth sparked a trade war with USA which was resolved with a 1986 trade agreement. The 1986 Semiconductor Trade Agreement (STA) limited Japanese DRAM exports to the United States and resulted in an opening for Korean manufacturers to establish a presence in the market [JUN 06]. Prior to this trade treaty, Korean firms sustained enormous losses sparking heated internal debates about whether focus should remain in the development of a semiconductor industry. Korean firms sustained these

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losses due to a cyclical recession in the semiconductor industry, but also because little space existed for new entrants in the DRAM market. Long established Japanese firms surpassed American competitors and controlled an overwhelming majority of the market for several years before Korean firms released their first, primitive designs. The primary effect of the STA was to place limits on the ability of Japanese firms to completely dominate the market. Instead, they were forced to focus on developing the next generations of chips, essentially vacating space for Korean manufacturers to offer older designs. Samsung, the leading South Korean firm, entered the market in the mid 1980s with a 64 K DRAM, nearly two generations behind Japanese producers. If Samsung was placed in direct competition with established leaders, this new device would have surely failed to find market space and accrue revenue. However, during the release of Samsung’s 64 K DRAM, Japanese firms focused the sum of their resources to deliver the next generation of 1 M DRAM, conceding market space at lower levels of technology. Eventually, Samsung and Hyundai emerged as the dominant suppliers of the two previous generations of DRAMs, the 64 K and 256 K. This trend continued through the early 1990s. In 1989, as Japanese firms began to release 4 M DRAM chips, they simultaneously phased out 1 M production, leaving another gaping hole for Korean producers to fill. By 1990, Japanese producers accrued a 98% share of the 4 M DRAM market. However, by the end of 1991, Samsung was the world’s largest producer of 1 M DRAM chips. Furthermore, the willingness of Korean manufacturers to undercut DRAM prices also resulted in a larger market share. From the mid 1980s through the early 1990s, dominant Japanese companies attempted to keep the price of memory devices artificially high through controlled output levels. In January of 1990, the top three Japanese producers announced cuts in DRAM production, attempting to stabilize falling prices. These cuts appeared to be so coordinated that many American buyers accused the Japanese industry of acting like a cartel. While these methods worked through the 1980s, they did not expect Samsung and other Korean manufacturers to undercut their prices and vastly increase their market share at the expense of Japanese companies. As Korean production capabilities increased, their added output resulted in a glut of supply in the DRAM market, subsequently dropping their price in the early


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1990s. When Japanese companies attempted to raise the price of DRAMs by cutting supply, they relinquished a large portion of their market share to Korean companies who did not hesitate to continue production at the lower price; if a cartel did indeed exist, the Koreans broke it. This increase in market share was not limited to USA and Europe, but also included Japan’s famously insulated electronics industry. From 1995 to 1997, the export share of Korean chips to Japan rose from 16% to 20% as many independent Japanese electronics makers began to purchase cheaper Korean DRAMs. Essentially, attempts by Japanese firms to control the price of DRAMs resulted in an opportunity for Korean firms to exploit. Because of the ultra-short product life of DRAM chips, continuous investments and reinvestments must be made to remain at the forefront of the market segment. New process technology must be developed for every generation of chip, which comes every two to three years. While the Korean chaebol could bunker down and withstand price drops due to their diversified businesses, a number of smaller American merchant firms could not sustain these fluctuations and went bankrupt. Micron is currently the only American company still alive in the DRAM market. In recent years, the DRAM memory industry has undergone significant consolidation, and continues to consolidate further. Figure 2.34 clearly illustrates a summary of the DRAM vendors history. The 1990s were characterized by a large number of DRAM makers, a quick expansion from 6-inch to 8-inch and fast technology migration (every 3 quarters). 6-inch fabs rapidly exited from DRAM production. Tough competition among DRAM makes it hard to survive, so that companies with non-DRAM business options exited the DRAM race (such as, for example, Intel and Texas Instruments), while pure DRAM companies tried to enter non-DRAM business (Flash, sensor, LCD driver, system-on-chip, digital signal processors and foundry). The 2000s were characterized by a few vendors (5 major players + 3 minor players), a slower transition from 8 inch to 12 inch, technology migration which slows down significantly and longer ramp down of 8-inch DRAM fabs. Similarly, the growing Flash market shares memory manufacturing.

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DRAM Market Consolidation

Figure 2.34. (Top) The history of the DRAM market [SHI 07]. (Bottom) Major DRAM makers by market share 3Q08 [DRA 08])

Today, DRAM supply is heavily concentrated in the hands of few major suppliers. Currently, Samsung alone controls one third of total DRAM supply. Similarly, several alliances took place between DRAM makers in order to expand their positions in the DRAM market while sharing development costs. In 2002, Inotera Memories Inc. was founded as a 50:50 joint venture partnership with Nanya Technology Corporation and Infineon Technologies AG (now Qimonda) and is located in Taoyuan, Taiwan. The


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total investment of the joint venture amounted to around $2.2 billion. In March 2003, Elpida Memory, Inc. (Elpida) and Powerchip Semiconductor Corp. (PSC) announced the official signing of the sales and purchasing contract agreements solidifying their DRAM strategic alliance. In January 2005, Hynix and ProMOS signed a contract for a longterm strategic alliance. It creates approximately one quarter of the world’s secondlargest DRAM output. Looking back in the year 2008, the worldwide DRAM industry was facing severe oversupply and industry structural problems. DRAM chip price has dropped nearly 75% in 2008 and the industry total loss from 1Q08 to 3Q08 was more than $8 billion. In March 2008 Micron & Nanya, with a $550 million investment each, created a new Taiwan DRAM JV MeiYa Technology, a DRAM joint venture to co-develop the products of under 50 nm process, that will leverage both companies’ manufacturing technology. In 2008, Germany’s Qimonda said that it has signed a technology license and foundry agreement for its new 65 nm “buried wordline” technology with Taiwan’s Winbond Electronics Corp. The October of the same year, Micron Technology Inc. announced that it will pay $400 million in cash for Qimonda’s entire 35.6% stake in Inotera. Inotera plans to switch to Micron’s Stack process manufacturing technology from the current Trench process from Qimonda. The Micron-Nanya alliance’s market share is expected to rise to 21.4%, which is extremely close to the Elpida-PSC alliance’s 21.9%, and the Hynix-ProMOS alliance’s 21.6%. The global DRAM market is dominated by the three alliances mentioned above, and industry leader Samsung Electronics Co. After PSC first announced capacity cut in September 2008, Elpida, Promos, Nanya, and Inotera continued to follow. Worlwide DRAM capacity decreased nearly 20%. Recently the Taiwanese vendors have become the most aggressive to cut capacity, cutting about 29% capacity which is the most among all vendors. In January 2009, Qimonda has filed for insolvency under German law (the memory chip maker had a net loss of €1.48 billion between October 2007 and June 2008). Recently, Taiwanese, American and Japanese DRAM vendors united to fight against the Korean vendors. After Samsung announced its 100% annual bit growth target, with its title of worldwide DRAM leader, the Taiwanese vendors bound themselves more tightly to their technology partners Elpida and Micron with closer cooperating relationship in order to survive. Two alliances were formed, with Micron and Elpida as the leaders, to fight against the Koreans. It has also been reported that the Korean company

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Hynix received $550 million support from its creditor banks and that the Taiwanese government prepared a NT$100 billion National Development Fund to bail out the Taiwanese DRAM industry. 2.11. Conclusions In this chapter, we attempted to give a general overview of the semiconductor industry from an economic perspective, trying to identify the main economic factors at the heart of the current IC industry transformation from a relatively young, high-growth industry to a more mature and established one, with an ever smaller number of competitors. The semiconductor industry is highly cyclical, with continuous booms and busts in demand for products. IC revenues reached nearly $256 billion in 2007, growing at an average annual rate of 17% between 1970 and 2002 and most recently falling at nearly 6-10%. Several analysts claim that today this industry has reached a “maturity” phase, partly due to the saturation of the PC market. Nevertheless, a shift from computing revenue drivers to consumer market revenue drivers occurred in recent years. Indeed, it has been mobility applications which have driven the inflection point for highcapacity non-volatile memory devices. In this context, NAND Flash memories are one of the fastest growing sectors of the market, the growth being stimulated by mobile storage and computing. Today, major areas for the IC market are the Asian Pacific regions, which are forecasted to cover approximately half of the world market in 2010 (the fastest-growing market being China). It is commonly assumed that the rapid price decline of semiconductor devices has been directly followed by impressive technological improvements and semiconductor device scaling. Nevertheless, to measure the whole economic impact of the transistor price-decline in a more precise way, we must first chart the overall contours of technological change in semiconductors in a more satisfactory fashion. Since 1970, the price of a single transistor element of an IC has dropped at an average rate of 27%. The rise in revenues of IC companies in the face of constantly deflating prices meant that unit volume (transistor/year) and the market had grown at an average annual rate of over 45%. Explanations of price-swings of semiconductor devices are very complex. Aside from changes in the pace of underlying technology (or advances in semiconductor technology, i.e.


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Moore’s law), several other factors, with short-term impacts, should be considered, in particular: complicated relationships between market demand and IC volume production, and also savage competition between companies in a global context and, eventually, collusions between IC suppliers in bad periods to fix prices. Indeed, the DRAM market is a good example of how the evolution toward fewer suppliers would ultimately lessen the overspending and wild capacity/ASP swings in a product segment. It is clear that semiconductor manufacturing is a highly competitive industry in which device cost and speed are the major economic driving forces. High technology and rapid obsolescence (with products becoming obsolete in less than a year) are the main characteristics. There is no other product with quite such brutal requirements. The dynamism of the integrated circuit (IC) industry was first described by Gordon Moore, in 1965, when he observed that “the complexity for minimum component cost has increased at a rate of roughly a factor two per year”. This observation became known as Moore’s law. Moore’s law has held true for nearly 40 years, essentially thanks to the impressive reduction of component feature size (45 nm-32 nm in production today) and the increasing of silicon wafers (300 mm today). Moore’s Law has been interpreted by economists as an interesting case of an informal institutional framework for “analyzing” technical change that gradually evolved into a more formally structured process for “organizing” technical change in a major global industry. In the last decades, Moore’s Law was taken as the rule of the game for competition among semiconductor companies. Since the mid-1990s, Sematech and the International Technology Roadmap for Semiconductors have been accelerating the scaling of CMOS devices to continuously lower dimensions, despite the difficulties that appear in device optimization, in order to face the competitive pressures of Japanese and then Korean producers and Taiwanese manufacturers, who had become major players in the world semiconductor scene. Many economists have underlined the critical economic impact of this scaling acceleration, which has led, in a final analysis, to an acceleration of the consolidation of the global semiconductor industry. The main result of technology node scaling acceleration was in fact an intensified competition among the main actors, in parallel with an exponentially increasing cost to set up manufacturing and R&D. The total cost of developing the latest lithography tools is in the $500 million to

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$1 billion range. State-of-the-art 90 nm and 65 nm fabs now reach an average cost of $5 billion. A business which drives high-volumes, capable of justifying such an expense, is quite rare among IDMs. Moreover, to face increasing technical difficulties, total worldwide semiconductor industry capital spending surged 18% to $54.75 billion in 2006, which represented 22.1% of total semiconductor sales last year. Clearly, this is unaffordable for most of the existing IDMs. Probably the biggest key to understanding the nature of this problem fully lies in Moore’s Law and the rate at which technology nodes have been developed. If the spending rate must slow, then either the clock rate of Moore’s Law must slow or the industry must become more efficient. All these factors (aggressive competitiveness, declining prices, economic pressures – including the increasing costs of developing new technologies and sustaining the costs of new high yield manufacturing facilities while making them run to full capacity – and finally, saturation of the market growth) have brought the semiconductor industry into a phase of major consolidation. The main consequence of exploding costs is the trend toward “alliances”, both at the manufacturing stage and in the research/development of new technologies. In particular, consolidation of manufacturing capacity is going on through the transformation of many IDMs in “fab-lite” or “fabless” companies, relying on foundries, mainly located in Asia Pacific, for manufacturing of IC products. This means that, relatively few companies control a very large portion of the IC industry’s supply of wafer fab capacity. In 2007, nearly half (48%) of the world’s capacity was represented by the combined capacity of the top-10 leaders. It has also been forecasted that Taiwan will have the world’s largest amount of fab capacity by 2009. Note also that consolidation of manufacturing is only one step forward in the path of global consolidation of the IC activities, as packaging materials and assembly were already mainly located in Asia. In addition, to counter the mounting pressure and challenges of rising R&D costs, most chipmakers (with the exception of Intel) have embraced various cost- and risk-sharing collaborative partnerships for development of leading-edge technologies: among them the IBM Fishkill alliance (initially developed by IBM, Chartered, and Samsung); top-tier foundries (such as TSMC, UMC, etc.) and the Advanced SoC Platform Corporation (ASPLA) in Japan.


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2.12. References [AIZ 08] A. Aizcorbe, S.D. Oliner, D.E. Sichel, “shifting trends in semiconductor prices and the pace of technological progress”, Business Economics, The Journal of the National Association for Business Economics, vol. 43, no. 3, July 2008, http://www.nabe.com/ publib/be/0803/aizcorbe.html. [AND 97] D. Anderson, “Stoking the productivity engine with new materials and larger wafers”, Solid State Technology, vol. 40, no. 3, p.57, March 1997. [BAR 07] R.Barth, “Test challenges beyond 2010”, Proceedings of the Global STC Conference (GSC), Napa, CA, 14-16 May 2007,www.semitest.org/events/gscwebpage/ gsc_presentations/ITRS_test_2007NapaSTCR7b.pdf. [BRI 07] M. Brillouet, “CEA-LETI as a European model of cooperation in nanoelectronics”, FCMN, 2007, www.eeel.nist.gov/812/conference/2007_Talks/Brillouet.pdf. [CAR 99] E.G. Carayannis, R.I. Samanta Poy, J. Alexander, “The speed and acceleration of technological innovation: a co-opetitive dynamics perspective of the small satellites industry”, Proceedings of the IEEE Portland International Conference on Management of Engineering and Technology, vol. 2, pp.149–158, August 1999. [CBR 07] “Severe price erosion clips chip sales”, Computer Business Review, 6 August 2007, http://www.cbronline.com/article_news.asp?guid=5292B773-B6A1-4FC9-809A580F11501724. [CHA 05] R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, M. Radosavljevic, “Benchmarking nanotechnology for high-performance and lowpower logic transistor applications”, Proceedings of the IEEE Transaction on NanoTechnology, vol. 4, no. 2, p. 153, March 2005. [DAV 06] J. Davis, “AMD, Intel margins suffer on price wars”, Electronic News, 24 October 2006, www.edn.com/article/CA6384238.html?partner=enews [DEL 06] S. Deleonibus, B. DeSalvo T. Ernst, O. Faynot, T. Poiroux, P. Scheiblin, M. Vinet, “CMOS devices architectures and technology innovations for the nanoelectronics era”, International Journal of High Speed Electronics and Systems, vol. 16, no. 1, pp.193–219, 2006. [DOJ 07] Department of Justice, “Sixth Samsung executive agrees to plead guilty to participating in DRAM price-fixing cartel”, USA Department of Justice Release, 19 April 2007 http://www.usdoj.gov/atr/public/press_releases/2007/222770.pdf. [DOJ 09] Department of Justice, “The accomplishments of the US Department of Justice 2001-2009”, US Department of Justice, http://www.usdoj.gov/opa/documents/dojaccomplishments.pdf. [DRA 08] “Micron Buys Qimonda's Inotera Stake, Boosting Micon-Nanya Alliance Market Share; Density of NAND Flash Related Products Doubled”, DRAMeXchange, Oct. 14 2008, http://www.dramexchange.com/WeeklyResearch/Post/2/615.html.

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[FLA 97] K. Flamm, “More for less: the economic impact of semiconductors”, Celebration of the 50th Anniversary of the Invention of the Transistor, Semiconductor Industry Association, December 1997, https://www.sia-online.org/downloads/Flamm_Study.pdf. [FLA 04] K. Flamm, “Moore’s Law and the economics of semiconductor price trends”, Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions – Report of a Symposium (2004) Board on Science, Technology, and Economic Policy (STEP), The National Academies Press, 2004, http://books.nap.edu/ openbook.php? record_id=11134&page=151. [FLA 06] K. Flamm, “Economic impacts of international R&D coordination: SEMATECH, the International Technology Roadmap, and innovation in microprocessors”, January 2006, www.nistep.go.jp/IC/ic060110/pdf/2-2.pdf. [FLA 06b] K. Flamm, “Economic impacts of SEMATECH on innovation in semiconductors”, Innovative Flanders: Innovation Policies for the 21st Century: Report of a Symposium, p. 74, The National Academic Press, September 2006, http://www.nap.edu/catalog/ 12092.html. [FUL 07] B. Fuller, “IC industry in midst of fundamental change, says Infineon CEO”, EETimes Supply Network, 01/10/2007, http://www.eetimessupplynetwork.com/ showArticle.jhtml;jsessionid=3F3VXDEAGRQJYQSNDLPSKHSCJUNN2JVN?articleI D=196802729 [GAR 09] “Worldwide Semiconductor Revenue Fell by More Than 5 Percent in 2008, According to Final Results by Gartner”, Press Releases, Gartner Research, April 8, 2009, http://www.gartner.com/it/page.jsp?id=932612. [GOD 05] F. Goodwin, “Trends in the cost of photolithography development and an outlook for the future”, Infineon, Seminar given at the College of Nanoscale Science & Engineering, University of Albany, USA, 7 November 2005, http://cnse.albany.edu /download.cfm/Trends_in_Cost_of_Photolithography_Dev.pdf?AssetID=199. [HUT 05] G.D. Hutcheson “The R&D Crisis”, VLSI Research Inc., 28 Janruary 2005, https://www.vlsiresearch.com/public/600201_r&d_crisis.pdf. [IBM 09] “CEA/Leti and IBM to Collaborate on Future Nanoelectronics Technology”, IBM Press releases, April 2009, http://www-03.ibm.com/press/us/en/pressrelease/27187.wss [ICI 07] “The McClean Report 2007 edition: an in-depth analysis and forecast of the integrated circuit industry”, IC Insights, 2007, http://www.icinsights.com/prodsrvs/ mcclean/mccr2007.pdf. [ICI 07b] “Memory suppliers fail history lesson – again!”, Research Bulletin, IC Insights, 2007, http://www.icinsights.com/news/bulletins/bulletins2007/bulletin20070329 .html. [ICI 08] “DRAM producers to fall behind the curve in capital spending, DRAM average selling prices to surge in 2010!”, Research Bulletin, IC Insights, 2008, http://www.icinsights.com/news/bulletins/bulletins2008/bulletin20081215.html. [ICI 08b] “IC Insights ranks top foundry suppliers”, Research Bulletin, IC Insights, 2008, http://www.icinsights.com/news/bulletins/bulletins2008/bulletin20080505.pdf.


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[ICI 08c] “Electronics systems sales expected to fall 2% in 2009”, Research Bulletin, IC Insights, 2008, www.icinsights.com/news/bulletins/bulletins2008/bulletin20081219.html. [ICI 09] The McClean Report 2009 Edition, IC Insights, 2009, http://www.icinsights.com/ prodsrvs/mcclean/mcclean_section06.html. [ICK 06] “IC market status and trend”, Chapter 2, IC Knowledge LCC, 2006, http://www.icknowledge.com/our_products/Chapter%202.pdf. [ITRS] www.itrs.net [ITR 02] “The International Technology Roadmap for Semiconductors: 2002 Update”, Introduction, http://www.itrs.net/Links/2002Update/2002UpdateIntroduction.pdf [ITR 05a] ITRS, “Advantages and challenges associated with the introduction of 450mm wafers”, Position paper report submitted by the ITRS Starting Materials Sub-TWG, June 2005, http://www.itrs.net/papers.html. [ITR 05b] “International Technology RoadMap for Semiconductors - 2005 Edition”, Executive Summary, http://www.itrs.net/Links/2005itrs/ExecSum2005.pdf [JEB 09] A. Jebens, “2009 economic forecast: facing the perfect storm”, VLSI Research, Semiconductor International, 2009, http://www.semiconductor.net/article/CA6628545.html. [JON 08] S.W. Jones, “Exponential trends in the integrated circuit industry”, IC Knowledge LLC, 12 February 2008, http://www.icknowledge.com/trends/Exponential3.pdf. [JON 09] S.W. Jones, “Status and trends in 300mm manufacturing”, IC Knowledge LLC, January 2009, http://www.solid-state.com/display_article/349311/5/none/none/Feat/ Status-and-trends-in-300mm-manufacturing. [JUN 06] D. Jung, “A new context for technological development, reconsidering South Korea and Taiwan’s semiconductor success through market space and business organization”, Stanford Journal of East Asian Affairs, 25 March 2006, http://www.stanford.edu/ group/sjeaa/journal52/korea1.pdf. [KIM 06] Kinam Kim, “Manufacturing technology for sub-50nm DRAM and NAND Flash memory”, Semiconductor Fabtech – 30th Edition, p.12, Samsung Electronics, Korea, www.fabtech.org. [KIM 07] M. Kimura, “EUV lithography moves toward practical use”, Cover Story, Nikkei Electronics, October 2007, http://techon.nikkeibp.co.jp/article/HONSHI/20070926/ 139712/. [LAP 07] M. Lapedus, “NOR market heats up despite tumultuous times”, EETimes Asia, 2007, http://www.eetasia.com/ART_8800486869_480200_NT_52dd2f00.HTM#. [MAC 01] J.T. Macher, “Vertical disintegration and process innovation in semiconductor manufacturing: foundries vs. integrated producers”, Wharton Technology MiniConference, Philadelphia, PA, March 2001, http://mackcenter.wharton.upenn.edu/ OldTechConfPapers/ macher.pdf. [MCG 07] J. McGregor, “The common platform technology: a new model for semiconductor manufacturing”, In-Stat, 5 January 2007, ttp://www.amkor.com/Common_Platform_ Report0107.pdf.

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[MAY 07] A. Mayhew-Smith, “NAND price fixing probe begins to send subpoenas”, ElectronicWeekley.com, 17 September 2007, http://www.electronicsweekly.com/ Articles/2007/09/17/42191/nand+price+fixing+probe+begins+to+send+subpoenas.htm. [MAN 08] D. Manners, “Private equity losing interest in ICs says John Daane”, ElectronicsWeekly, September 18, 2008, http://www.electronicsweekly.com/blogs/davidmanners-semiconductorblog/2008/09/private-equity-losing-interest.html. [MOR 65] G.E. Moore, “Cramming more components onto integrated circuits”, Electronics, Volume 38, Number 8, April 19, 1965. [NAT 06] National Science Board 2006, “Industry, technology, and the global marketplace, National Science Board”, Chapter 6 in Science and Engineering Indicators 2006 Vol.1, National Science Foundation, Arlington, VA, 2006, http://www.nsf.gov/ statistics/seind06/pdf/c06.pdf [PET 07] L. Peters, “45 to 32 nm: another evolutionary transition”, Semiconductor International, January 1, 2007, http://www.semiconductor.net/article/CA6402509.html. [PWC 08] PricewaterhouseCoopers, “China’s impact on the semiconductor industry: 2008 update”, PricewaterhouseCoopers, 2008, http://www.pwc.com/Extweb/pwcpublications. nsf/docid/E851BD5302E77D82852575020014A85B/$FILE/2008_China_Semicon.pdf. [RUM 03] R.P.Rumelt, “The integrated circuit industry in 2003”, The Anderson school at UCLA, 2003, http://www.anderson.ucla.edu/faculty/dick.rumelt/Docs/Cases/ICInd2003.pdf. [SHA 08] A. Shah, “The next big move in chip manufacturing”, IDG News Service, May 2008, http://www.techworld.com/opsys/features/index.cfm?featureid=4091&pn=2. [SHI 07] B. Shieh, “Changing memory industry dynamics”, PowerChip Semiconductor Corp., US-Taiwan Business Council, Santa Clara California, February 2007, http://www.taiwanchina-outlook.com/presentations/powerchip.pdf. [SIA] Semiconductor Industry Association, www.sia-online.org [SIA 05] Semiconductor Industry Association, Annual Report, 2005. [SIA 09] “Global semiconductor sales fell by 2.8% in 2008”, SIA Press Release, 2009, http://www.sia-online.org/cs/papers_publications/press_release_detail?pressrelease.id=1534. [SPI 07] Mark S. Spillman, “The Asian semiconductor industry and it-s potential impact to US national security”, Electronics Industry Study, Seminar 6, The Industrial College of the Armed Forces, National Defense University, Washington, AY, 2006-2007. [TRY 02] W. Trybula, “Semiconductor industry lithography segment R&D/ROI”, GlobalEconomic Symposium, Scottsdale, AZ, 2002, http://www.sematech.org/meetings/ archives/GES/20021119/symposium/04_Trybula.pdf. [WFR 07] “2007 NVM Workshop”, ICMTD Conference, Web-feet Research, Inc, Giens, France, 2007, http://webfeet.sp360hosting.com/default.aspx. [WU 03] S.-L. Wu, “Industry dynamics within Semiconductor Value Chain IDM, Foundries and Fabless”, Master of Science in Management of Technology, Massachusetts Institute of Technology, May 2003 http://dspace.mit.edu/bitstream/handle/1721.1/29721/54038520 .pdf?sequence=1.

Chapter 3

Research on Advanced Charge Storage Memories

In this chapter, we will start by introducing the main features and scaling limits of current Flash memory technologies. Then, the main strategy of the innovative research in this field will be presented. Today, two main research paths can be identified. To extend the classical floating gate technology to 22 nm and possibly lower nodes, different “evolutionary paths”, essentially based on the use of new materials and of new transistor structures, can be investigated. On the other hand, to address smaller IC generations, “disruptive paths”, based on new storage mechanisms and new technologies, are envisaged. Here we will focus on the “evolutionary approaches”, paying particular attention to the results obtained in our laboratory (LETI, CEAGrenoble/France) in the last few years, funded by internal projects, the French government, European institutions and industrial partnerships. Note that a crucial point in the definition of the research plans has always been maintaining a good equilibrium between short-term (made in collaboration with IC companies) and longterm (developed in collaboration with fundamental research laboratories and universities) solutions. Given the large variety of technologies currently invoked as potential replacements for conventional Flash, one of the hardest tasks for a scientist

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working in this field, at least concerning the near-middle term research (i.e. time to be in production < 10 years), is to identify the right framework of study (for example, embedded or stand-alone environment) for the different technologies, in order to be able to assess the main advantages and disadvantages, and thus to prospect future applications. The “evolutionary approaches” include new modules (i.e. discrete trap memories, and more specifically silicon nanocrystal memories), new materials (high-k materials for the interpoly layer of Flash) and innovative architectures (such as FinFlash memories). Moreover, obviously targeting a longer term application, hybrid approaches, which make use of organic molecules – grafted on silicon substrates – as storage sites, have been developed. Finally, the main theoretical limits of charge storage memories (i.e. reliability issues linked to few electron phenomena) have been identified, opening up the path to the introduction of disruptive memory technologies based on new storage mechanisms. 3.1. Key features of Flash technology There exist two main families of Flash memory devices, NOR and NAND [CAP 99, CAM 05], with different applications (see Figure 3.1). NOR Flash memory provides random memory access and reads fast (useful for pulling data out of memory), but it writes data relatively slowly. NOR is the mainstream technology for the applications requiring the storage of codes and parameters, and more generally for execution-in-place. NOR is the technology currently preferred by cellular handset makers. Today, cell phones constitute up to 60% of the NOR Flash market. NAND, on the other hand, reads data slowly but has fast write speeds (desirable features for storing digital photos, and for MP3 audio, GPS, and other multimedia products). It provides both high programming throughput and high density. It is the dominant technology for data storage and memory cards. NAND memories are one of the fastest growing sectors of the market, the growth being stimulated by mobile storage and computing.


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Finally, it should be stated that today the traditional roles of, and applications for, NOR and NAND devices are becoming blurred, as many new gadgets combine both types of flash devices into a single platform. Some manufacturers have devised “combination” flash architectures that feature the best characteristics of NOR and NAND on a single chip. Examples include Samsung’s OneNANDTM (which makes a single-level-cell NAND core with “logic elements to emulate a NOR interface”, resulting in read times fast enough for NOR-style executable storage, along with write times fast enough for NAND-style data storage) and Spansion’s ORNANDTM devices.

Figure 3.1. NOR and NAND Flash traditional applications [CAM 05, BEZ 07]

As shown in Figure 3.2, in NOR memories, cells are connected in parallel, which enables the device to achieve random access. NOR has long erase and write times, but fast read times. NAND-type cells are created in series. NAND Flash was developed as an alternative optimized for high density data storage, giving up random access capability in a tradeoff to achieve a smaller cell size, which translates to a smaller chip size and lower cost-perbit. NAND has faster erase and write times than NOR, a higher density,

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lower cost per bit than NOR Flash, but it only allows sequential access to data. While NAND cannot inherently perform random access, it is possible at the system level through shadowing [COO 08]. From a practical standpoint, the biggest difference a designer will notice when comparing NAND Flash and NOR Flash is the interface. NOR Flash has a fully memory-mapped random access interface like an EPROM, with dedicated address lines and data lines. Because of this, it is easy to “boot” a system using NOR Flash. On the other hand, NAND Flash has no dedicated address lines. It is controlled using an indirect I/O-like interface and is controlled by sending commands and addresses through a 8 bit bus to an internal command and address register. For example, a typical read sequence consists of the following: writing to the command register the “read” command, writing to the address register 4 bytes of address, waiting for the device to put the requested data in the output data register, and reading a page of data (typically 528 bytes) from the data register. The NAND Flash’s operation is similar to other I/O devices like the disk drive it was originally intended to replace. However, because of its indirect interface, it is generally not possible to “boot” from NAND without using a dedicated state machine or controller. However, the indirect interfaces advantage is that the pin-out does not change with different device densities, since the address register is internal. Because NAND Flash is optimized for solid-state mass storage (low cost, high write speed, high erase speed, high endurance), it is the memory of choice for memory cards [TOS 03]. So, even if NOR and NAND have a common cell architecture, based on the floating gate concept and a one-transistor stacked-gate cell, they have different transistor architecture: high performance logic in NOR (to speed the program/erase algorithm and to obtain the fastest random access time); dedicated logic driven by the cell architecture in NAND (to minimize the mask number and to reduce the process cost). They also have different memory reliability requirements: NOR, after final test, must be a perfect array; NAND is similar to a mass storage media


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(fault tolerant, like Hard-Disk); it makes use of Error Code Correction and is a quasi-perfect array.

Figure 3.2. Main features of NOR and NAND Flash memories [CAM 05, BEZ 07]

A typical example of a Flash memory application is the cellular handset system. It is worth mentioning that cell phones have transformed our lifestyle and have become an integral part of our everyday life. In developed countries, cellular communication has become a necessity. In third-world countries, it is considered an enabler of economic progress. Consequently, it is gaining an increasing share of the entire electronics market, likely overtaking the PC market in the next decade. Worldwide

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mobile phone shipments were 808 million units in 2005, and are expected to grow to about 1.2 billion by 2010 (Figure 3.3) [SPA 06].

Figure 3.3. Worldwide wireless and mobile handset shipments by region (2005-2010) [SPA 06]. Source: iGillotResearch, Inc., 2006

Given that there are just over 6 billion people in the world, this means that over 13% buy a new handset each year. Cellular phones are the largest consumer electronics market in overall volume. In order to capitalize on the expanding worldwide growth opportunity in both emerging and mature markets, handset OEMs must design solutions as diverse as the markets they serve. They must be able to deploy multiple, differentiated product models to a wide range of consumers – from pricesensitive customers in emerging markets to feature-hungry users wanting the most sophisticated gadgets they can buy.


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The wireless industry, including service providers and handset manufacturers, defines handsets by four primary phone categories ranging from smart phones, the most feature-rich and powerful models, and then moving down through high-end phones, feature phones and entry-level, or basic, models (Figure 3.4) [SPA 06]. As a result, manufacturers need a hardware and software platform that will enable them to rapidly and economically scale platforms up and down, stripping or adding features over the production lifetime of the handset. In this way they can serve established markets with handsets at multiple price points, while also satisfying the needs of new users in emerging market.

Figure 3.4. Handset market segmentation [SPA 06]

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Figure 3.5. NEC FOMA 900iL cell phone handset showing shows Intel’s NOR Flash memory working in conjunction with Toshiba’s NAND Flash [PAO 05]

Current Flash memory needs for mid- to high-end cell phones is approximately 1-8G. Figure 3.5 shows a NEC FOMA 900iL cell phone handset, showing Intel’s NOR Flash memory working in conjunction with Toshiba’s NAND Flash [PAO 05].


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Designs for next-generation cell phones have become exceedingly intricate, especially as more advanced features and applications, such as Web browsing, text messaging, interactive games and digital camera functionality, are added to meet demand. Consequently, cell phone designers must carefully balance density, speed, cost and power considerations by using varying combinations of different memory chips to maximize the handset’s overall performance. Generally speaking, a cell phone needs two kinds of memories, volatile and non-volatile. Cell phone architecture determines memory mix (Figure 3.6). Handset designers have traditionally used NOR Flash memory solutions for code storage and execution, and in a dual role for both code execution and data storage requirements. NOR devices feature “execute-inplace” (XIP) capabilities [STM 05, BEZ 07], which allow software tasks to be executed directly in Flash memory. In addition, processors can interface directly with NOR Flash memory (see Figure 3.6). This means that machine instructions can be retrieved and executed out of the Flash memory without having to be buffered into the main memory first, saving time and significant cost associated with buffer RAM solutions. NOR Flash memory also provides very high reliability in order to support code storage and execution. 90% of cell phones have been shipped in 2007 containing only NOR Flash memory, according to Gartner. Low-end phones will continue using NOR Flash and PSRAM with XIP for optimal power consumption, performance and cost. Memory card support will expand to fulfill data storage for memory-hungry multimedia applications. However, NOR I/F (Interface) is no longer a must for new wireless processors. In fact, as data storage requirements have grown beyond the storage capacities of NOR, and handset manufacturers have sought less expensive solutions for pure data storage, NAND solutions have increasingly found their way into handsets to handle the raw growth of data. In a small percentage of very high-end phones, NAND is used instead of NOR for code storage applications.

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Because NAND does not have XIP capabilities, phones that use NAND for code execution must include additional expensive and power-hungry DRAM, increasing cost and power consumption. In these “code shadowing” systems (see Figure 3.6), the code is stored in a lower-cost NAND flash device. At start-up, the code is loaded from the NAND into the high-cost DRAM volatile memory, which then executes it. NAND has significantly lower reliability and slower read speeds than NOR. While this leads to slightly longer boot times, it actually results in faster overall operation into a DRAM where it is executed. In order to support code shadowing, designers must reengineer their hardware and software.

Figure 3.6. (Top) Mobile phone architectures [BEZ 07]. (Bottom) Different memory solutions for different systems [BEZ 07]


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3.2. Flash technology scaling Flash cell size has been reduced by a factor of about 30 in the last 10 years, with a doubling of the memory capacity every year [KIM 06, BEZ 07] (see Figures 3.7 and 3.8). Moreover, mulitlevel technologies (which appeared in 2000 and 2001: NOR flash by Intel and NAND flash by Toshiba and SanDisk respectively) obviously drive further cost reduction (Figure 3.9). NOR has a cell size of about 10F² – F being the minimum feature size – (5F² in Mulitlevel Cell, MLC) due to contacts. NAND has an effective cell size of 5F² (~2.5F² for MLC). NAND has scaled of a factor 10 in 5 years. In terms of the future, the most authoritative industrial forecast, the ITRS, (International Technology Roadmap for Semiconductors) predicts that, to meet the requirements of the multi-gigabit era, the exponential progress of silicon solid-state mass storage will continue at least for the next 10 years [ITR 07] (Figure 3.10). At the VLSI 2007 [KWA 07], Samsung presented a 64 Gb NAND Flash Memory chip based on a 30-nanometer process technology, with a cell size of 0.00593 μm². With the 56 nm 3-bit/cell MLC NAND Flash mass production of Toshiba/SanDisk in 2Q08, the NAND Flash makers started to develop the 3-bit/cell MLC products. In March 2009, Samsung Electronics announced that it has begun using 40 nm process technology to produce an 8 Gb Flex-OneNAND fusion memory chip, which supports both single-level cell (SLC) and mulitlevel cell (MLC) architectures. Applications using Samsung’s 40 nm-made Flex-OneNAND will expand from smartphones to full HDTVs, IPTVs and other high-end applications, according to the company.

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Figure 3.7. Trends in NAND storage density integration and NAND cell size scaling, according to Samsung [KIM 06], http://www.samsung.com/Products/ Semiconductor/NANDFlash


Figure 3.8. (Top) NOR and NAND cell scaling. (Bottom) NOR cell scaling, according to ST-Microelectronics (now Numonyx) [CAM 05, BEZ 07]

Figure 3.9. A non-volatile semiconductor memory history

89

90

Silicon Non-Volatile Memories Year

2006

2008

2011

2016

NOR

NAND

NOR

NAN D

NOR

NAND

NOR

NAND

70

64

57

51

40

36

22

20

Cell size (O²)

9-11

4/2

9-12

4/2

9-12

4/1

10-13

4/1

Cell size (μm²)

0.049

Technology Node (nm)

Generation at prod. SLC MLC

0.034 4G 8G

0.017

8G 16G

Coupling ratio Tunnel oxide EOT (nm)

0.0057

16G 32G

32G 64G

0.6-0.7 8-9

7-8

8-9

6-7

8

6-7

7-8

6-7

Interpoly oxide EOT (nm)

13-15

13-15

1315

10-13

10-12

10-13

8-10

9-10

NOR Lg-stack (physical μm)

0.135

Highest W/E Voltages (V)

7-9

Endurance (# cycles)

0.12 17-19

7-9

15-17

0.08

6-8

1E5

15-17

6-8

1E6

Retention (years) NOR Iread (uA)

0.11

15-17 1E7

10-20 28-36

Max. # bits/cell

26-34

20 27-33

2 Solutions exist

22-28 4

Solutions known

Solutions NOT known

Figure 3.10. Technology roadmap for NOR and NAND Flash memories [ITR 07]


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Today, nearly all Flash devices in production are exclusively using CMOS floating gate technologies. Nevertheless it is widely believed that the scaling of the standard technologies beyond the 22 nm node will be extremely difficult. Among the different key issues are [ITR 07]: 1) The scaling of tunnel and control dielectric thickness is limited by concerns for reliability assurance, in particular the 10 year data-retention, which is of primary importance. Even in present Flash memories, assuring non-volatility for all bits after program/erase cycling is a challenge from the viewpoints of manufacturing and yield. The finite probability of having a cluster of two or three defects in the tunnel oxide, producing a huge local increase of the tunnel current (namely stress induced leakage current, SILC), determines the anomalous failure bits, which are widely recognized as the most important concern in Flash devices. The amplitude of the SILC increases when the tunnel oxide is thinned, limiting the oxide scaling. Indeed, this results in high operating voltages. 2) Drain voltage scaling in NOR memories, also limited by the need for maintaining coupling and program voltage for channel hot electron injection. This phenomenon-gives rise to the drain turn-on phenomenon, which limits the channel length, and consequently the cell area, of NOR devices. 3) The scaling of ultra-dense NAND devices, limited by the parasitic floating gate (FG) interferences (i.e. the states of neighboring cells are coupled via the intra-floating gate capacitance); a lower coupling ratio (interpoly dielectric, IPD, and wordline can no longer fit into the space between gates); and finally less tolerant charge loss, which is particularly critical in mulitlevel cells. The capacitive coupling becomes critical at around 50 nm ground rules and calls for lower k value isolation material or discrete storage nodes [KIM 07]. 4) Finally, the lithography concern will be another stumbling block on the road of NAND flash memory’s evolution. In fact, one of the critical steps can be expected to be the definition of features at extremely high pitch (1030 nm). The primary candidate for next generation lithography is believed to be extreme ultraviolet (EUV) lithography that operates at O= 13.2 nm. EUV lithography makes it possible to achieve the integration levels needed for NAND Flash memory of 64-256 Gbit capacities, and μprocessors with 1.6-

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6.4 billion transistors. This is 4 to 16 times higher than the integration levels of cutting-edge IC today. 5) Reliability issues, due to few electron phenomena, will be the ultimate intrinsic limits of NAND memories (see section 3.4.10). As explained in detail in Chapter 2, it could also happen that prohibitive costs, rather than physical limits, will make the traditional approach of decreased wavelength impractical. The only way to recover these costs is to have high throughputs, long tool lives, long photomask lives and excellent feature fidelity within a chip, between chips and between wafers. In “stand-alone” memories, the available transistor budget is used to build dedicated memory chips with the largest die size compatible with the transistor budget. Nevertheless, as scaling has advanced, silicon technology has become able to integrate very complicated systems on a single silicon chip, video-audio processing rich digital consumer systems, battery operated low power mobile application systems, and so forth. These integrated systems typically consist of some processing unit(s), busses, memories and interfaces. Complex processing of massive data must be handled and executed in a very short period of time, in other words, with a very high system clock frequency. This necessitates higher performance, lower power consumption and larger capacity “embedded” memories. Note that an emerging semiconductor market that is picking up momentum is “embedded” memory (including E-SRAM, E-Flash and EDRAM), which allows for a higher level of system-on-chip (SoC) integration. Until now, system designers have generally used stand-alone or discrete memories. This is changing as the growth of the wireless communications infrastructure creates demand for communications equipment and digital appliances. The system designers of these products are seeking technologies that will permit them to decrease the size and enhance the performance of their products. These designers are facing increased market pressure to rapidly introduce new products, which shortens the time available for research and development. Driving the explosion in demand is the need for more bandwidth. In fact for every tenfold increase in bandwidth demand there is a fivefold increase in memory density. Choosing “embedded” over “stand-alone” memory


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brings clear advantages. It removes the need for connections between chips (the “interconnect wall”). It allows designers the use of ultra-wide data buses as well as flexible array sizes and orientations. In these ways, embedding memory can increase the speed of operation, reduce power consumption and, of course, increase compactness. It is not surprising then, that market researchers expect rapid market growth for embedded memories. Figure 3.11 shows the forecasted dramatically increasing trend of embedded memory area amongst the building components in SoCs (94% in 2014).Embedded memories are becoming more important because they more directly determine the competitiveness of SoCs and will become a key differentiator for the technology offer.

% of Die Area

A major E-Flash application is in microcontrollers (MCU) with embedded NVM: automotive, industrial and household appliances, office automation, smart cards, etc. Just for household appliance, USB controllers, smart cards and automotive segments, shipments of MCU chips with embedded Flash memory are estimated by some market analysts to reach nearly 7 billion units by 2010.

52% 71%

2002

2005 New L ogic

83%

90%

94%

2008

2011

2014

Re us ed L ogic

M em ory

Figure 3.11. Chip area evolution trend of SoC (Source: IC Insights, SIA Roadmap and others) [MAR 05]

Stand-alone non-volatile memories (NVMs) require extremely reduced cell area to reach the maximum storage capability, at the expense of a more complex manufacturing process. In these devices, the manufacturing process

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of the memory cell should be optimized, while the performances of the transistor used for the access and control logic are not critical. Larger cell sizes achieved with a less complex process are acceptable in embedded NVMs for microcontroller SoCs, in which the NVM processing is added to a high performance CMOS process. Figure 3.12 shows selected parameters for NVM built in 90 nm technology [PRI 06]. Embedded memories do not require very high storage capabilities. The critical issues are good performances of the logic transistors and reduced additional cost for the integration of the NVM. The embedded process should support pure CMOS performance, design kit and intellectual property while adding the required on-chip flash features. As shown in Figure 3.13, e-Flash process lags leading logic processes by 4 generations and NOR Flash by 3 generations [WFR 07].

Embedded NVM (NOR)

Standalone NOR

Standalone NAND

Typical Application

Micro-controller

Celullar Phone

MP3 Player, Digital Camera

Typical Density (90 nm technology)

1-32 Mb

256-512 Mb

2 Gb

Typical % of Chip Area

5% - 50%

100%

100%

Bitcell Size (90 nm)

0.18 μm2

0.09 μm2

0.05 μm2

Random Access Read Time

20 ns

50-100 ns

15 μs

Process Complexity

Low

Highest

High

Figure 3.12. Some features of 90 nm NVM technologies [PRI 06]

Figure 3.13. eFlash roadmap compared to NOR Flash and logic devices [WFR 07]

Research on Advanced Charge Storage Memories 95

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3.3. Innovative paths in silicon NVM technologies To meet the requirements of the multi-gigabit era, innovative memory solutions are requested. Main research paths can be roughly divided into two categories (see Figure 3.14). – “Evolutionary solutions” aim at extending the Flash technology lifetime as much as possible, establishing a successful development and scaling strategy until new technologies become a real alternative. They are still based on variations of the well-proven floating-gate architecture (which is currently still the mainstream of the NVM business). These solutions consist essentially of: 1) the integration of new materials (such as Si or metal nanocrystals or nitride traps) for the floating gate, being more robust to defects in the oxide, and high dielectric constant materials – named high-k dielectrics – for the cell active dielectrics (offering improved thickness scalability compared to standard SiO2), eventually coupled to p+ metal control gates (solving the erase saturation problem); 2) the use of new device architecture (such as Finfet transistors) allowing for shorter gate length due to the reduced parasitic short-channel effects. Through these solutions, the floating gate technology could probably be extended to the 32 nm and possibly 22 nm nodes. After the 22 nm node, because of the many limitations encountered in the scaling of memory standard memory cells (such as the limited number of electrons, difficulties in manufacturing, and lithography cost) the only possible forecasted way, based on standard technologies, which will allow the density increase of the NVM memories, will be the vertical stack of the memory arrays (namely, 3D IC technologies). – “Disruptive technologies” will probably be introduced beyond the 22 nm node. Possible solutions are based on the introduction of new storage mechanisms, like phase-change materials (PCM memories), ferroelectric storage (FeRAM) and magnetic storage (MRAM). Other important emerging concepts (with great potential for low cost application to the 22 nm and smaller IC generations) make use of bottom-up approaches (i.e. chemical synthesis, self-assembly and template self-assembly) either as promising precise fabrication techniques of device structures, or even for the entire functional entity. One important option recently proposed is to make a hybrid CMOS/molecular memory, to provide a bridge between Silicon and


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molecular-only technology. However, all these approaches involve the introduction of new, complex materials, and new storage mechanisms, and could present either scalability or material development problems. Moreover, today, all these technologies have a limitation on the cell size (1 cell = 1 transistor + 1 capacitor/resistor) compared to standard Flash (one transistor cell). Moreover, today they cost several times more than DRAM and Flash. So, the question of “if and when” one of the above mentioned technologies will gain the position to take over the standard Flash, is still open. Indeed, reliability and cost will be the key factors for the introduction of these new technologies. Development of Future Non-Volatile 2. Pushing the scaling limits Memories of current FG

•To extend the FG technology to the 3X-2X nodes

2.A New Materials • 1. OUM-PCRAM structures 2. Pushing scaling limits of current FG-NVMs Pushing thethe scaling limits of current NVM technologies 2. Development of Tunnel1.Oxide: Crested Barriers new technologies: • CB-RAM

•

•Resistive FeRAM RAM

•

•MRAM OUM-PCRAM

•

•SeekCB-RAM and Scan

•

•Molecular Resistive RAM memories … • MRAM • •

High-ks,

2.AMetal New Materials 1. NCs

Seek and Scan Organic Molecular memories, etc.

• Beyond the 2X node (perf, reliability, cost) • New applications

•

Tunnel/ Oxide: Crested Barriers IPD: High-k Metal Gate Floating Gate: CVD SiNCs, High-ks, Metal NC s, Metal Nitride NCs …

1. 2.B New transistor Multiple gate FETs structures (FinFlash SOI, Bulk) • Ultra-thin body SOI FinFla sh FET

•

IPD: High-k / Metal Gate

3D Integration

Nanow ire FETs Multiple gate FETs

(FinFlash SOI, Bulk)

3D Integration (wafer bonding, multi-channels, vertical transistors, etc)

• To increase density beyond the 2X node

Figure 3.14. Possible research paths on innovative NVMs

3.4. Research on advanced charge storage memories 3.4.1. Silicon nanocrystal memories The basic idea of discrete trap memories is to replace the standard continuous poly-Si layer of the floating gate with discrete storage nodes, which can be made by natural traps in an appropriate insulator (like the nitride layer in SONOS, MONOS and NROM memories) or composed of semiconductor nanocrystals. Silicon Nanocrystal (Si-NC) memories are one

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of the most promising solutions for pushing the scaling limits of Flash memories at least to the 32-20 nm technology nodes [DES 03, DES 04].

(a)

(b) Figure 3.15. (a) Si-NC memory bitcell (left: cross-section along cell length; right: cross-section along channel width); (b) image of the 32Mb Si-NC array [JAC 08]


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Due to their discrete nature, Si-NCs are robust to defects in the oxide. Thinner tunnel dielectrics and lower operating voltages can be used without compromising data-retention, especially after cycling. Cells with abnormally short retention times (“erratic bits”) are suppressed. Moreover, due to the decreased capacitance coupling ratio, floating gate interferences in ultradense NAND memories are eliminated. Recently, it has been shown that optimized chemical vapor deposition (CVD) process results in partially selforganized nucleation and growth of Si-NCs [LOM 04], mitigating the impact of fluctuations on memory array characteristics. Finally, thanks to the use of a single poly-Si, Si-NC memories require a simple and low cost device fabrication process, which makes them of particular interesting for embedded memory applications [MUR 03]. Recent works have demonstrated the discrete storage node concept on a 32 Mb Si-NC NOR Flash memory product, fabricated in a 130 nm ATMEL technology platform [JAC 08]. To integrate the Si-NCs in a 32 Mb NOR Flash memory array, two main key integration challenges were faced: 1) Si-NC robustness to strong oxidation steps; and 2) Si-NC removal in logic periphery. To solve these issues, the integration strategy was as follows: firstly, the periphery devices (i.e. CMOS logic, High Voltage, and I/Os) were produced using a SASTI (Self Aligned Silicon Trench Isolation) approach. Secondly, the memory bitcells were defined in a conventional flow (non-SASTI). Thirdly, the memory gate stack was removed by dry etch in the periphery of the arrays. The remaining process steps (gate patterning, halo implants, LDDs, Source/Drain implants and back end) closely followed conventional 130 nm process flow. As shown in Figure 3.15, the gate length and width of the Si-NC memory bitcells are 0.23 μm and 0.16 μm, respectively. The memory gate stack consists of 5 nm-thick thermal SiO2 tunnel dielectric covered by the Si-NC storage layer, the 10 nm-thick high temperature topoxide and the n+ poly-silicon control gate. Nanocrystals were deposited following a two-step LPCVD process, described in detail by [DES 03]. Several nanocrystal deposition conditions (yielding similar densities, Ndot, and different dot sizes, )dot) have been explored (see Figure 3.16). Subsequent to deposition, Si-NCs were properly passivated (giving rise to a thin nitrided oxide shell) to avoid any parasitic oxidation.

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Sample 1: ĭdot=4 nm

Sample 2: ĭdot=6.5 nm



(a)

(b)

(c) Figure 3.16. (a) Scanning Electron Microscopy images of Si-NCs with the same dot nucleation step and different dot growing times. (b) Bright field and corresponding EFTEM (energy filtered TEM) images. (c) Dot size distributions calculated from EFTEM images in particular: sample 1 (average ĭdot=4 nm, Ndot|7.5E11cm-2), sample 2 (average ĭdot=6.5 nm, Ndot|5.5E11 cm-2), sample 3 (average ĭdot=8 nm, Ndot|5E11 cm-2), Sample 4 (average ĭdot=12 nm, Ndot|2.7E11 cm-2) [JAC 08]


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Writing: Vg=8V Vd=3.75V Vb=-1.5V Vs=0V t=10μs -5

Drain current (A)

10

-6

10

-7

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Fresh Written Forward Read Written Reverse Read

-8

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-10

10

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1

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Writing: Vd=3.75V Vb=-1.5V Vs=0V Vg=6V Vg=8V 6 Vg=10V 5

Writing: Vg=8V Vb=-1.5V Vs=0V

7

Threshold Voltage (V)


(a)

4 3 2 1

-7

-6

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Vd=3V Vd=3.5V Vd=4V

6 5 4 3 2 1

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(b) Erasing: Vd=Vs=Vb=0V

6

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Vg=-14 V Vg=-16 V Vg=-18 V

Vg=-10 V Vg=-12 V

5 4 3 2

Vg=-16V

VthE-Vthinit (V)


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5 Flash 3 1 0 -1

Fresh

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(model)

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10-6

10-5 10-4 10-3 10-2 Stressing time (s)

10-1

1

(d)

Figure 3.17. SiNC memory bitcell data: (a) Id-Vg of a; (b) writing by channel hot electron; (c) erasing by Fowler-Nordheim [JAC 08]; (d) erase comparison with standard poly-Si Flash

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Regarding the memory cell results, devices are programmed by channel hot electron (CHE) injection and erased by Fowler-Nordheim tunneling (FN). Figure 3.17a shows the Id-Vg curves of a memory bitcell corresponding to the sample with 9 nm Si-NC diameter and 1E12/cm² Si-NC density. Writing and erasing dynamics for different bias conditions are also shown in Figure 3.17b and 3.17c. A very large programming window of 4V is achieved in 10 μs with drain (Vd), gate (Vg) and substrate (Vb) biases equal to 3.75 V, 8 V, -1.5 V, respectively. Moreover, the asymmetry in the written curves (Figure 3.17a), read in the forward (Vds = 1V) and in the reverse mode (Vsd = 1V), clearly states the discontinuity of the Si-NC layer. Looking at Figure 3.17c, we can also observe that fast erase operations can be achieved ('Vth = -3 V with Vg = -16 V, 100 μs) in the FN regime. When compared to standard poly-Si Flash devices, SiNC memory offers erase saturation and 1 to 2 decades faster erase (100 μs) than standard Flash (Figure 3.17d). SiNCs have also been integrated in 4 Mb NOR stand-alone memory array based on a ST-Microelectronics 90 nm Flash technology [GER 08]. Main original technological improvements are a cylindrical symmetry of the 1Transistor bitcell, which significantly increases the coupling ratio (particularly critical in Si-nc memories), and the use of an optimized ONO (oxide/nitride/oxide) control dielectric, which prevents parasitic charge trapping during cycling. Si-ncs were deposited by chemical vapor deposition (CVD) on a thin (4.5 nm) thermally grown tunnel oxide. A typical average radius of 5nm was measured using energy filter TEM planar view. A typical Si-ncs density of ~1012 dots/cm2 was achieved. Si-ncs were passivated by an optimized nitridation process based on annealing in NH3 atmosphere. CVD Si-ncs deposition and passivation was performed by CEA-LETI.

Research on Advanced Charge Storage Memories (a)

103

(b)

Figure 3.18. Top: (a) 90 nm node Si-NC bitcells along the wordline direction; (b) EFTEM cross-section of the bitcell. The cylindrical shape of the memory cell clearly appears. Dimensions of the 4 Mb bitcell are: L=180 nm; W=70 nm. Bottom: Summary of the memory process flow [GER 08]

A control dielectric consisting of an ONO triple layer with EOT = 12 nm was deposited on top of the Si-ncs. The ONO layer has an optimized structure, obtained by reducing the nitride thickness and is thus weakly affected by parasitic charge trapping. A passivation annealing to reduce the nitride trap density was also carried-out in order to further prevent charge trapping. The cell active area has been processed in order to achieve a cylindrical sector shape, with a channel width of 70 nm. Figure 3.18a shows the 90 nm node bitcells along the word-line direction. It can be observed that, by avoiding the ~100 nm thick poly-Si FG, the gate stack thickness is strongly reduced with respect to conventional FG cells, with an improved aspect ratio. The cylindrical symmetry of the memory cell is clearly evident in the figure.

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Figure 3.18b shows the Si-ncs by a magnified Energy Filtering TEM (EFTEM) cross-section. Si-ncs were integrated into a 4 Mb STMicroelectronics NOR memory array, fabricated with a minimum design rule of 90 nm. CMOS peripheral circuitry uses only moderate voltage transistors allowing us to skip 4 masks for circuitry; no FG definition mask was used. Several trials were carried-out with the purpose of optimizing the Si-ncs removal from the circuitry region, until both decoding logics and charge pumps fulfilled the required performance specifications. The memory process flow is summarized in Figure 3.18 and it is derived from a 1T FG memory process flow.

(a)

(b)

Figure 3.19. (a) CHE written Vth, read in the forward and reverse modes, as a function of the reading Vd (erased Vth is 1.5 V). L=180 nm. (b) Data retention of the difference between reverse and forward Vth measured at 150°C [GER 08]


105

Figure 3.20. Program and erase distributions of the 4Mb Si-nc NOR Flash array (program with 9 V between gate and substrate and 4.4V for 10 ms to the drain; erase with 15 V for 10 ms). No correction algorithms were used [GER 08]

Typical dual-bit measurements, consisting of a CHE programming step followed by forward (Vds>0) and reverse (Vds3×1012 cm2) and size (2-3 nm) of the nanocrystals, whereas their crystallinity has been investigated using high-resolution transmission electron microscopy. Capacitance-voltage sweep measurements give excellent memory characteristics with a 7.1 V maximal memory window (see Figure 3.36).

122


Figure 3.35. Images of Pt nanodots obtained by dewetting a thin Pt layer (0.5-1 nm). The dot density Ndot ~ 3E12 dots/cm2 [DUF 08]

FN/FN W/E

Pt

Si Ref

Figure 3.36. Low-thermal budget capacitors with Pt nanodots show large memory windows (up to 7.5 V) [DUF 08]


123

There exists a lot of literature on the materials and fabrication aspects of metal NC devices. The range of metals which have been studied in view of nanodot memory applications include: Ag, Au, Pt, W, Co, Ni, NiSi, Fe, TiN, Al, etc. [LEE 03, LEE 05a, LEE 05b, LIU 00, LIU 01, LIU 02a, LIU 02b, SAM 05a, SAM 05b, SEU 05, WAN 06]. Main fabrication techniques are: sputtering [TAK 03] and dewetting of uniform ultra-thin metal layers through thermal annealings [LIU 02a, LIU 02b, LEE 05d]. However, any memory material/structure that has been reported, to date, does not completely satisfy the reliability criteria required for the gigabit-level NAND memories. In fact, several issues still remain to be solved to achieve a reliable integration process for metal nanodot memories. In particular, due to the fact that metals are fast diffusers, many cares have to be taken when processing the metal nanocrystals in clean-room standard front-end tools in terms of contamination. For example, it has been shown [DUF 07] that Ni nano-dots are prone to react with the silicon oxide tunnel at high temperatures (850°C). This causes a problem of reliability because the presence of Ni atoms in the oxide degrades the insulating properties of the SiO2. Moreover, special attention should be given to the thermal budget of all the processes following the metal deposition (and, in particular, the control dielectric deposition) which could impact on the metal nanodots, stability. Based on these considerations, two main techniques seem to us highly promising today: 1) Metal nanodots obtained through oxidation of metal silicides (as tungsten nanocrystals by oxidation of tungsten silicide-WSix-film [CHE 08]). 2) Metal silicide (MxSiy) nanodots [WEI 07, YEH 05a, YEH 05b, ZHA 05, ZHU 06b, LIU 05, ZHU 07]. In fact, metal silicide materials are already used as interconnections of VLSI circuits due to their larger stability in temperature compared to metals and their relatively low resistivity. Several solutions are also studied in the literature in order to solve the issue of randomness in NC placement and NC number fluctuations, which have been perceived as challenges to device scaling. In particular, the

124


organization of inorganic nanostructures within self-assembled organic or biological templates seems very promising. Researchers at IBM [GUA 03] have used self-assembly of diblock copolymers – a mixture of polystyrene and poly methyl methacrylate (PMMA) molecules – to fabricate a Flash memory device with ordered Si nanocrystals (see Figure 3.37). To make the devices, the diblock copolymer was annealed so that it separated into phases consisting of nanoscale PMMA cylinders in a polystyrene matrix. Removing the PMMA with an organic solvent left a porous polystyrene film, which is used as a template for amorphous Si NC deposition. The nanocrystals had a diameter of 20 nm and a density of 6.5E10 dots/cm2. According to scientists, using a polymer with a lower molecular weight could provide a route for obtaining smaller and denser nanocrystals. More recently, biomolecules (which are capable in general of self-assembling into a wide diversity of structures with nanoscale architecture) have also been used as templates in nanodot memory devices. Some proteins [MAC 02, TAN 05], for example, have been used to form nanoscale ordered 2D arrays of metal and semiconductor quantum dots (see Figure 3.38); by binding preformed nanoparticles onto crystalline protein templates made from genetically engineered hollow double-ring structures called “chaperonins”. Using structural information as a guide, a thermostable recombinant chaperonin subunit was modified to assemble into chaperonins with either 3 nm or 9 nm apical pores surrounded by chemically reactive thiols. These engineered chaperonins were crystallized into two-dimensional templates up to 20 μm in diameter. The periodic solvent-exposed thiols within these crystalline templates were used to size-selectively bind and organize either gold (1.4, 5 or 10 nm) or CdSe–ZnS semiconductor (4.5 nm) quantum dots into arrays. The order within the arrays was defined by the lattice of the underlying protein crystal. These results show that a hybrid bio/inorganic approach to nanophase material organization and nano devices is possible.

100 nm

Figure 3.37. Diagram of a Flash memory with ordered Si nano-dots fabricated by means of polymer template. Polymer templates are formed over 200 mm silicon wafers [GUA 03]

___________

__

100 nm Research on Advanced Charge Storage Memories 125

126


(b) (a)

(c)

(d)

Figure 3.38. (a) Illustration of a chaperonin protein with a genetically engineered hole for inserting quantum dots of metals and semiconductors. (b) TEM image of a 2D crystal of the beta chaperonin variant with apical pores. (c) Graphical representation of 5 nm gold particles binding within the 3 nm pores of engineered chaperonin 2D crystals. (d) STEM imaging of nanogold arrays [MAC 02, TAN 05]


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3.4.6. High-k IPD-based memories One of the nearest major changes of NVMs will concern the engineering of the interpoly dielectric (IPD) stack. In fact, according to the ITRS [ITR 07], from the 5 nm-32 nm node, the IPD should be drastically reduced due to the loss of the vertical sidewalls of the poly-Si floating gate [KIM 05, ALE 06, HOU 05]. It is forecasted that the coupling ratio will be dropped to 0.3 for the 32 nm node instead of the value of 0.6 fixed by the roadmap [HOU 05, PAR 06]. However, standard interpoly oxide-nitride-oxide (ONO) dielectrics reach their lower thickness limit and cannot be scaled in theory beyond 15 nm without dramatically compromising the reliability of the memory. Consequently, high-k dielectric materials (such as HfO2, Al2O3, HfAlO, HfSiO, etc.) are envisaged to replace the standard ONO IPD stack of Flash memories, allowing for a high coupling ratio while maintaining good data-retention. Demonstrations of AlO blocking oxides combined with an SiN trapping layer have already been represented in the literature for mulitlevel NAND applications targeting the 40 nm technology node [PAR 06]. It has also been demonstrated that the integration of HfO2 as interpoly dielectrics (instead of standard ONO stacks) in poly-Si floating gate cells gives rise to a reduction of the programming voltages, due to the better coupling coefficient between the control and the floating gates [VAN 06]. Moreover, some works have recently been presented where the discrete FGs (SiN layer or a high-k material layer) and high-k based IPDs are associated with the metal control gate, to reduce the parasitic electron back tunneling from the control gate during the erase operation [VAN 06, LAI 06, WAN 05, LAI 05, CHI 05, LEE 06, VAN 06b]. Among the different studied materials, a strong interest is given to hafnium aAluminate (HfAlO) compounds, as they have the potential to combine the high dielectric constant of HfO2 and the elevated energy barrier height and good thermal stability of Al2O3. In our recent works [MOL 06, MOL 07b, BOC 07, MOL 08], we investigated in-depth the coupling properties, insulating capabilities, electron conduction modes and parasitic trapping phenomena of HfAlO layers. HfAlO compounds are deposited by ALD, using H2O and HfCl4 as precursors for HfO2 deposition and H2O and Al(CH3)3 for Al2O3 deposition. Three compositions are investigated, designed by the HfCl4:Al(CH3)3 deposition cycle ratio: 9:1 (Hf-rich), 1:4, and 1:9 (Al-rich), corresponding to the following Hf concentrations: 94%, 31% and 27%, respectively. Pure

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HfO2 and Al2O3 based samples are also processed as reference. oxide/HfAlO/oxide (OHO) triple-layer stacks with n+ poly-Si control gate were processed. The HfAlO thickness ranges between 3 nm and 9 nm. Both the bottom and top dielectrics of the triple layer stacks are 4 nm-thick silanebased high thermal oxides (HTO). Figure 3.39 presents the cross-section images of the triple-layer capacitors made by high resolution transmission electron microscopy. It appears that the 9:1 HfAlO layer is crystalline, due to the high Hf concentration in the alloy, while the 1:9 HfAlO layer is amorphous. This agrees with results previously reported in the literature, which stated that the crystallization temperature of the HfAlO alloy increases monotonically as the Al percentage increases, the Al acting as a stabilizer of the amorphous phase [ZHU 02].

N+ poly-Si SiO2 4nm HfAlO 9nm SiO2 4nm Si-p

20 nm

HfAlO 9:1

HfAlO 1:4

HfAlO 1:9

Figure 3.39. High resolution TEM images of the studied HfAlO-based triple-layer dielectrics [MOL 06]


9 7 6 5

6

%Hf increases

5 4

4

3

3

2

%Hf increases

2

H2

HfO2 Hf:Al 9:1 Hf:Al 1:4 Hf:Al 1:6 Hf:Al 1:9 Al2O3

8

H1

129

1

1

0

0 1.5

2 2.5

3 3.5

4 4.5

5 5.5

6 6.5

7 7.5

8

Photon Energy (eV)

Optical Bandgap [eV]

7 6.5

Eg = -0.8276 [Hf] + 6.4461

6 5.5 5 4.5 0

Al2O3

0.2

0.4

0.6

Hf fraction

0.8

1

HfO2

Figure 3.40. Spectroscopic ellipsometry measurements of HfAlO layers. Top: real part H1 and imaginary part H2 of the complex dielectric function H ̓as a function of the photon energy. Bottom: extracted optical bandgap as a function of the targeted Hf fraction of the HfAlO layer [LIC 07]

HfCl4:Al(CH3)3 deposition cycle ratio

HfAlO dielectric constant N

1:0 (HfO2)

20

9:1

17

1:4

15

1:9

11.5

0:1 (Al2O3)

8

Table 3.1. Dielectric constant of the HfAlO stacks [MOL 07b]

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HfAlO composition

EA

HfO2

340 meV

HfAlO 9:1

260 meV

HfAlO 1:4

200 meV

HfAlO 1:9

170 meV

Table 3.2. Activation energies for tri-layer oxide/HfAlO/oxide samples [MOL 07b]

Modifications of HfAlO layers’ optical properties are obtained from spectroscopic ellipsometry (Figure 3.40). A vacuum ultraviolet (VUV) ellipsometer (Jobin Yvon phase modulated ellipsometer, 1.5 eV to 8 eV) has been used to assess the complex dielectric function H=H1-iH2, where H1 and H2 are the real and imaginary part of H [LIC 07]. The thickness and the bandgap of the film are determined from the analysis of the raw data using a Tauc Lorentz model with two oscillators [BOH 04, NGU 05]. The bandgap is extracted by considering a linear variation of D E .E vs the photon energy E, where D is the absorption coefficient. The bandgap (Figure 3.40) is correlated with the hafnium content of the layer and is ranging from 6.4eV for pure Al2O3 to 5.6eV for pure HfO2, confirming the intermixing of HfO2 and Al2O3 during the ALD process. The obtained values are in very good agreement with data reported in the literature [NGU 05, YU 02] also obtained on ALCVD HfAlO films. Concerning the coupling properties, based on C(VG) measurements, and taking into account quantum effects in both the n+ poly-Si gate and the Si substrate, we extracted the equivalent oxide thickness (EOT) of the different stacks and the dielectric constants “N” of the HfAlO compounds (Table 3.1 [MOL 07b]). Note that the dielectric constant of HfAlO progressively increases as the Hf concentration increases, varying between the value of HfO2 and that of Al2O3, which is in agreement with previous results published in the literature [ZHU 02]. It is thus possible to adjust the HfAlO dielectric constant, and consequently the EOT of the IPD by tuning the Hf and Al content of the compound.


10-2 10-3 10-4

10-1 O / HfAlO 9:1 / O

JG @ E=10MV/cm [A/cm2]

Current density [A/cm2]

10-1

SiO2 10nm

10-2

SiO2 10nm

O / HfAlO 1:4 / O

SiO2 10nm

O / HfAlO 1:9 / O 10-3

10-4

10-5

10-6 80

10-5

131

90

100

110

120

EOT [A]

10-6 10-7 10-8

O/HfAlO/O HfAlO 3nm HfAlO 6nm HfAlO 9nm

10-9 -14 -12 -10

-8

-6

-4

-2

2

4

6

8

10

12

14

Electric field MV/cm

Figure 3.41. Leakage currents of O/HfAlO/O stacks with fixed HfAlO composition (9:1) and different HfAlO thickness. Inset: Leakage currents for different HfAlO compositions (at 10 MV/cm) as a function of EOT (results correspond to p-Si substrate [MOL 07b]

Figure 3.41 represents the gate current densities of different OHO samples with various HfAlO compositions [MOL 07b]. We can observe that the insulating capabilities at a fixed electric field increase with the Hf concentration of the HfAlO layer, which may be linked to the reduced EOT of the stack. Indeed, for a given electric field in the SiO2 layer, the electric field in the high-k layer is more important in an Al-rich HfAlO based stack than in an Hf-rich HfAlO based stack, resulting in an increase of the leakage current. In order to investigate the electron conduction mechanisms governing the leakage currents of OHO triple layer stacks, JG(VG) measurements were performed at high temperatures (up to 250°C). The leakage currents of the OHO samples were found to be strongly activated in temperature, as illustrated in Figure 3.42. The Arrhenius plots, extracted at 10 MV/cm, are shown in Figure 3.43 for different OHO samples with various HfAlO compositions. Assuming in the first order that the gate current is proportional to exp(-qEA/kBT) where q is the elementary charge, kB the Boltzmann constant

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and T the temperature (in Kelvin), it is possible to extract a parameter EA which is the activation energy (eV). It clearly appears that this activation energy EA increases as the Hf concentration increases (see Table 3.2). However, we should note that even at 200°C, the Hf-rich alloy still presents the lowest leakage current. In order to clearly identify the conduction modes involved in the triple layer stacks, we plotted in Figure 3.44 the Hill diagrams, starting from previous high temperature measurements. Indeed, a Poole-Frenkel conduction, probably assisted by the traps in the HfAlO layer, is put in evidence. The extracted trap depth (referenced with the conduction band of the high-k) varies typically between 1 eV and 1.5 eV, depending on the HfAlO composition. This consideration agrees well with our previous results obtained on different OHO tri-layer stacks [DEL 04]. The Poole-Frenkel model allows correct matching of our experimental data of OHO samples at strong voltages, for all the tested HfAlO thicknesses, from 3 nm to 9 nm. Traps in HfAlO layers were related to both oxygen vacancies, and oxygen-interstitial-related defect states of the HfO2 [QLI 06], based on XPS low-loss spectra and ab-initio studies. Other works also report two localized electron traps in HfAlO alloys, based on electrical data obtained on capacitors [JOH 02]. In this latter case, the defects are respectively assigned to AlO- bounding groups deriving from a breaking of the network component, and to antibounding Hf atom d states that form the lowest conduction bands of the alloys.

Current density [A/cm2]

10-3

T=200°C

10-4

Poly-Si SiO2

10-5

HfAlO 9:1

10-6

SiO2

10-7

Si sub

T=25°C

10-8 10-9 10-10 -9

-8

-7

-6

-5

-4

-3

-2

-1

0

Gate voltage [V] Figure 3.42. Leakage currents of OHO samples at different temperatures varying between 25°C and 200°C. The 9:1 HfAlO layer is 3 nm-thick [MOL 07b]


133

Current density [A/cm-2]

10-2

10-3

1:9 1:4 9:1

10-4 Poly-Si SiO2

10

-5

HfAlO 3nm SiO2 Si sub

10-6 20

25

30

q/kBT

35

40

[eV-1]

Figure 3.43. Arrhenius plots of OHO samples with various compositions of HfAlO. The HfAlO layer is 3 nm thick. The current density is extracted at 10 MV/cm [MOL 07b]

JG T4exp 1018 1014 1010

- )t kBT HfAlO 9:1

HfAlO 1:9 )t=1.55eV

25°C

)t=1.35eV

25°C

106 102

200°C

200°C

10-2 10-6 10-10 10

*thvDPF2sinh(DPF)

*thvDPF2sinh(DPF) 102 10

102

F(HfAlO)1/2xT-1 [V1/2m-1/2K-1] Figure 3.44. Hill diagrams of OHO samples with two different HfAlO compositions (1:9 and 9:1). The HfAlO layer is 3 nm thick [MOL 07b]

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3

HfAlO 9:1 1:4 1:9 2

'VFB (V)

VG=12V

1

0 -4 10

VG=9V

-3

10

-2

-1

10 10 Stress time (s)

0

10

Figure 3.45. Trapped charges in OHO samples, with various compositions and thicknesses of the HfAlO layer, as extracted from the programming characteristics. The stressing conditions are performed at constant VG/EOT. After [MOL 07b]

To more precisely evaluate the trapping capabilities of the interpoly stacks, we monitored the evolution of the flatband voltages as a function of time when the devices were submitted to different gate stresses (Figure 3.45). A continuous VFB shift is observed, showing the progressive electron trapping in the stack as the stress time increases. It clearly appears that for a given stress condition, the trapping capability increases with the Hf concentration. This result could be correlated with the crystalline structure of the high-k materials: the larger the Hf concentration, the more crystalline the layer, and hence, the higher the trapping capability [LER 04]. In order to validate the suitability of HfAlO as IPDs of future Flash memory cells, we performed simulations of memory programming transients [MOL 06] through a simplified analytical model [DES 01]. Firstly, we considered a “standard” memory cell architecture (corresponding to the 63 nm Flash NAND technological node), with a 6 nm-thick tunnel oxide, a poly-Si floating gate (FG) whose thick sidewalls contribute to the coupling ratio, and an OHO IPD (4 nm HTO/9 nm HfAlO (9:1)/4 nm HTO). Secondly, we investigated the 35 nm Flash NAND architecture, where the physical thickness of the interpoly dielectric will be larger than the space between two adjacent floating gates. In such advanced memories, a “zero overlap FG” structure should be envisaged, leading to a strong reduction of the coupling ratio. We assume a 6 nm-thick tunnel oxide and, in order to compensate the coupling ratio loss, we considered a 12 nm-thick (9:1)


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HfAlO single layer IPD, which indeed allows us to keep DG~0.66. The writing current through the tunnel oxide was calculated using a WKB formalism. The leakage currents through the IPDs were assumed to be equal to the experimental values. Thus, it is possible to determine the charge trapped in the FG, given by the balance of the filling and emptying currents through the tunnel and interpoly dielectrics. The writing characteristics are reported in Figure 3.46, where it appears that a 'Vth of 3 V can be achieved for VGW=16 V TW=1 μs.

(a)

Threshold voltage shift [V]

However it should be highlighted that for the industrial application of these structures, the limited data retention will be one of the most important issues. Leakage currents at low electric fields must be significantly lowered. Indeed, several technological solutions should be explored in the future in order to reduce the trap density of high-k IPD layers. 8

VGw=17V 6

CG

16V 15V

FG

4 Active

2 0 10-8

10-7

10-6

10-5

10-4

10-3

(b)

Threshold voltage shift [V]

Programming time [s] 8

VGw=17V

CG

16V

6

15V

FG

4

Active 2 0 10-8

10-7

10-6

10-5

10-4

10-3

Programming time [s]

Figure 3.46. Simulated writing characteristics of: (a) 63 nm Flash memory, with 6 nm tunnel oxide, OHO IPD (4 nm HTO / 9 nm HfAlO (9:1)/4 nm HTO) and continuous FG with sidewalls (DG~0.63); (b) 35 nm Flash memory, with 6 nm tunnel oxide and 12 nm HfAlO (9:1) IPD (DG~0.66)

136


In a further paper [BOC 07], the effect of NH3 nitridation on high-ț materials in view of application to non-volatile memories (NVMs) has been studied. Our study focused on the trapping properties of thick HfO2 and HfAlO layers (6-14 nm-thick). Through in-depth physical and electrical analyses, we demonstrated that an appropriate nitridation of these layers significantly reduces the charge trapping phenomena. We argued that the lower trapping capability can be related to a smaller ratio of the crystalline phase of the high-ț layers. Finally, we demonstrated by data and physical modeling that the charge trapping is mainly located at the high-ț/bottom oxide interface and that the NH3 annealing strongly affects this interface. 3.4.7. High-k/metal gate stacks for “TANOS” memories One solution which seems very promising today for high-density “standalone” NAND memories is the TANOS (TaN/AlO/Nitride/Oxide/Silicon) charge trap structure [KIM 07], where both high dielectric permittivity AlO, as a blocking layer, and TaN control gate, having stable thermal stability and reasonably high work-function (~4.8 V), have been reported to improve erase time of charge trap cell (which still remain the weak point of this approach). Retention of the TANOS structure has also been found to be dependent on both quality and thickness of blocking and tunnel oxide and charge trap nitride, and has been improved by optimizing their growing processes. Charge trap NAND, like TANOS NAND Flash, will eventually substitute current FG NAND at the 3X-2X nodes due to their superior scaling advantages [KWA 07]. Nevertheless, it should be stated that further searching for improved materials for both blocking oxide and control gate, and further optimizing the quality and thickness of the tunnel, blocking oxide and trapping nitride itself, are still needed in order to solve retention and erase weakness of charge trap NAND.


137

Figure 3.47. Diagram of the nitride-trap devices studied in [BOC 08]

Nevertheless, the identification of the precise role of each layer in nitridetrap memories, and the understanding of the complex physical mechanisms which govern the device performance and reliability, still need further investigation. In [BOC 08], we experimentally studied the influence of the blocking oxide and control gate of SAONOS (silicon/alumina/HTO/nitride/ oxide/silicon) devices on memory performance and reliability (see Figure 3.47). We demonstrated that SAONOS devices present the strong advantage of an improved retention characteristic (with a low temperature activation) compared to SONOS (silicon/HTO/nitride/oxide/silicon) or SANOS (silicon/alumina/nitride/oxide/silicon) memories (see Figure 3.48). SAONOS presents a slight loss of program erase speeds with respect to SANOS devices (see Figure 3.49). Nevertheless, in SAONOS devices the electron back-tunneling effect during erase is mitigated, so that equivalent erase speeds are obtained regardless of the poly-Si control gate doping (N+ or P+), and the erase saturation phenomenon is negligible. Finally, all these effects have been accurately modeled through a semi-analytical model based on the ShockleyRead-Hall theory (see Figure 3.50).

138


Figure 3.48. Data retention of nitride-trap devices with different blocking oxides at (a) 25°C and (b) 125°C. Initial 'VT0=3 V. Data-retention of SAONOS memories at different temperatures (25°C to 200°C), (c) before and (d) after 104 W/E cycles (control gate is N+ poly-Si) [BOC 08]

Figure 3.49. Erase characteristics of nitride-trap memories with different blocking oxides (N+ poly-Si control gate). Symbols: data; lines: simulations [BOC 08]


139

Figure 3.50. Band diagram of the simulated Nitride-trap memories: (a) SANOS during erasing; (b) SAONOS during writing. Mechanisms involved in the device program/erase are illustrated. Basic equations of our model are also reported, as is a table with parameters used to fit data [BOC 08]

3.4.8. FinFlash devices As already discussed, it is widely believed that the scaling of Flash memories down to the 32 nm technological node and beyond will face major issues, due to the high electric fields required for the programming and erasing operations and the stringent leakage requirements for long term charge storage [KIM 05]. In this context, new transistor architectures such as tri-gate FinFlash memory devices [LEE 06b] coupled with the discrete storage node approaches (i.e. nitride storage layer or silicon nanocrystals) offer the possibility of scaled gate dielectrics, implying scaled operating voltages, along with short channel effect immunity and higher sensing current

140


drivability. The idea of the FinFlash memory is to take advantage of the FinFET architecture for memory applications. In particular: 1) The electrostatic control of the channel will be improved, with reduced DIBL and improved short channel effects. Moreover, the use of a narrow fin channel eliminates sub-surface leakage paths, allowing the reduction of the memory gate length. 2) The drive currents will be increased due to the multi-channel conduction, improving the memory access time and programming speed. In such innovative architectures, charge trapping in the floating gate may be affected by the three-dimensional character of the structure, leading in particular to corner effects. Currently, many FinFlash demonstrations are presented in the literature, with SiN trap layer, on bulk substrate [KWA 07] or on SOI (silicon on insulator) substrate [FRI 06], showing results that demonstrate the high interest of these structures. Hereafter, we will present some recent results obtained in our group on FinFlash devices on SOI substrates [RAZ 07, PER 07, LOM 07, JAH 08]. The schema of the structure fabricated is shown in Figure 3.51, where the critical dimensions of the device are also reported. The fabrication of our FinFlash devices is based upon a standard Finfet process flow [JAH 05]. Ebeam lithography and resist trimming are used to pattern both the fin and the gate. Sidewall oxidation is carried out to round fin corners and decrease fin width. After fin patterning and boron channel implantation, gate stack deposition is performed, i.e. the 5-nm thick thermal SiO2, the storage layer made of SiNC (directly deposited by LPCVD or obtained by silicon rich oxide annealing) or 6 nm-thick LPCVD Si3N4, the blocking dielectric (8 nm thick HTO) and, finally, the 100 nm N+ Poly-Si control gate. After the gate etching, nitride spacers were deposited and etched. Raised Source/Drain were epitaxially grown in order to decrease the series resistance. After the completion of source/drain implantation, the flow is terminated by standard back-end-of-line. TEM images of the FinFlash devices are reported in Figure 3.52, demonstrating fin widths WFIN and gate lengths LG down to 10 nm and 30 nm, respectively.


141

Figure 3.53a shows the transfer characteristics (ID-VG) of virgin Si-NC FinFlash cells with WFIN=10 nm and different gate lengths. The enhanced electrostatic control of the gate over the channel at very small fin widths clearly appears. In particular, in the Inset, we can see that the threshold voltage VTH roll-off disappears in narrow fins. Figure 3.53b and c show that in the smallest devices (WFIN/LG=10/30 nm), 220 mV/dec subthreshold slope (SS@VD=1V) and 0.7V/V drain induced barrier lowering (DIBL) are achieved. Control gate

LG

Top oxide

Wfin = 10 … 40 nm Hfin = 35 nm LG= 30 … 130 nm Tunnel oxide: oxide 5 nm - SiO2

Hfin BOX

Wfin

Storage layer Tunnel oxide

Storage: Si-NCs, Si3N4 Top oxide: 8nm-HTO Control gate: Poly-Si N+

Figure 3.51. Diagram of the FinFlash memory cells [RAZ 07]

Wfin= 8nm

Figure 3.52. TEM views of the FinFlash devices with different storage nodes [RAZ 07]


LG [nm] = 30 50 1E-10 70 1E-8

1E-12

2

1E4

@ ID =10-7A

0 -2

WFIN [nm] 10 20 30 40

-4 -6

30

50

-2

0

2

Gate Voltage VG [V]

4

(b)

1E3

1E2

(c)

400

WFIN=10nm 20nm

300

200 LG=30nm 50nm 70nm

70

Gate Length LG [nm] 1E-14

D IB L [m V/V]

Drain Current I D [A ]

1E-6

(a)

WFin = 10nm VDS =1V

1E1

Subthreshold Slope [m V/dec ]

1E-4

Threshold Voltage V th [V]

142

100 10 20 30 40 30 50 70 Fin Width WFIN [nm] Gate Length LG [nm]

Figure 3.53. (a) ID-VG of Si-NCs FinFlash (in the virgin state) with WFIN=10 nm and different LG. Inset: VTH versus LG, for devices with different WFIN. (b) DIBL versus WFIN, for devices with different LG. (c) Subthreshold slope versus LG, for devices with different WFIN [RAZ 07]

Ultra-scaled Si-NC FinFlash devices are first studied in NOR configuration (i.e. channel hot electron writing and Fowler-Nordheim erasing). Figure 3.54 shows that, in scaled devices (WFIN/LG=10/30 nm), CHE yields large programming windows with low VD biases (lower than the Si/SiO2 conduction band difference, i.e. ~3.2 V). In particular, 'VTH ~3 V can be achieved when VD=2.5 V, VG=9 V, and tstress=100 μs. We can also observe that Fowler-Nordheim erasing can be achieved in Silicon Nanocrystal FinFlash devices even with a 5 nm-thick tunnel oxide (nevertheless, a saturation of the erase Vth occurs in the smallest device). Si-NC FinFlash devices can also be programmed in the NROM operating scheme (i.e. channel hot electron writing & hot hole injection erasing). The W/E dynamics are reported in Figure 3.55, with the programmed threshold voltages read either in the forward mode (VDS=1 V) or in the reverse mode (VSD=1 V) [EIT 00]. Indeed, we can clearly observe the asymmetry between the forward/reverse Vths, clearly suggesting that even for such strongly scaled devices the charges injected at the drain do not spread over to the source. Moreover, it can be noticed that erasing by hot holes is effective at a very


143

low drain bias (lower than the Si/SiO2 valence band difference, i.e. ~4.5 V). Data-retention of an Si-NC device with WFIN/LG=10/30 nm is reported in Figure 3.56, showing small charge loss at high temperature (150°C).

1E-5

Read @ V DS=1V

(a)

Erased T E=0.1s, V G=-12V

Fresh

1E-7

Written V D=2.5V V G =7,8,9,10V T W =100μs

Erased

1E-9

1E-11 1E-13

-2

0

2

Threshold Voltage V TH [V]

GateGate Voltage V G [V]VG [V] Voltage 4

4

V G=-12V

(c)

V G=-13V

3

V G=-14V

2

V G=-15V

1 0 -1

1E-7 1E-6 1E-5 1E-4 1E-3

0,01

Erase Time T E [s]

0,1

4

V G =7V V G =8V V G =9V V G =10V

3 2

(b)

VD=2V

1 0

-1


Drain Current ID [A]

1E-3


Good endurance (up to 1E6 cycles) of Si-NC device with WFIN/LG=20/30 nm also appears in Figure 3.57. Nevertheless, it should be stated that a slight degradation of the ID-VG characteristics appeared after 1E5 cycles.

1E-7

4

1E-6

1E-5

1E-4

Write Write Time TWTime [s] T W [s]

(d)

VD=2.5V

3 2 VG=7V

1

VG=8V

0 -1

VG=9V VG=10V 1E-7

1E-6

1E-5

1E-4

Write Time T W [s]

Figure 3.54. CHE/FN characteristics of Si-NC FinFlash with WFIN=10 nm, LG=30 nm. (a) ID-VG in virgin, written (CHE) and erased (FN) states; (b,d) write and erase (c) dynamics [RAZ 07]


Threshold Voltage VTH [V]

144

(a)

4 3

HHI Erase: VG=-4V

2 1

9V 8V

0

-1 -2


-3

3.3V

VG=7V

1E-7

Forward Read

1E-6 1E-5 1E-4 Write/Erase Time [s]

1E1E-3

(b)

3

VD=3V

2

3.1V 3.2V 3.3V

1 9V 8V

0

-1

3.5V

VG=7V

-2

-3

3.5V

CHE Write: VD=2.5V

4

-3

VD=3V 3.1V 3.2V

Reverse Read 1E-7

1E-6 1E-5 1E-4 Write/Erase Time [s]

1E-3


Figure 3.55. CHE/HHI characteristics of Si-NC FinFlash with WFIN=10 nm, LG=30 nm. Programmed threshold voltages are read (a) in the forward mode (VDS=1V) or (b) in the reverse mode (VSD=1V [RAZ 07]

3

T=150°C

Written

2 1 0

10 ys

Erased

1E2

1E4

1E6

1E8

Time [s]

Figure 3.56. Data retention at T=150°C of Si-NC FinFlash with WFIN=20 nm, LG=30 nm (CHE/FN written/erased) [RAZ 07]



4

145

Written (VG=9.5V, VD=2.5V, VS=0V, TW=100μs)

3 2 1 Erased (VG=-9.5V, VD=VS=2.6V, TE=30ms) 1E1

1E4 1E2 1E3 Number of cycles

1E5

1E6

Figure 3.57. Endurance of Si-NC FinFlash with WFIN=20 nm, LG=30 nm [RAZ 07]

Ultra-scaled nitride FinFlash devices are also studied in NROM configuration (i.e. channel hot electron writing & hot hole injection erasing), the Fowler-Nordheim erasing of charged nitride memories being ineffective with 5 nm-thick tunnel oxide. As we previously observed in Si-NC devices, strongly scaled Si3N4 devices can be efficiently written with VD biases lower than 3.2 V and erased by HHI with VD biases lower than 4.5 V (Figure 3.58), while these lowvoltage stresses are not effective for long devices. Moreover, even in nitride devices with ultra reduced cell lengths, a good threshold voltage difference between the reverse and forward states appears. We can remark that the nitride storage layer gives rise to a larger programming window than the Si-NC storage layer, probably due to the higher trap density of amorphous nitride compared to crystalline Si-NCs. Data-retention of Si3N4 devices with WFIN/LG=10/30 nm is reported in Figure 3.59, showing small charge loss at high temperature (150°C) and forward and reverse threshold voltages which remain detached after 10 years.



146

1E-6 Forward Reverse

Fresh

Written TW=100μs VD=2.5V

1E-12

VG=9V

-4

-2

0

HHI Erase: VG=-4V

2

VD=3V

1

3.1V

0

-3

1E-10

Forward Read

3

9V

2

4

6

Gate Voltage VG [V]

3.2V 3.3V

8V VG=7V

-2

1E-8

-6

4

-1


Drain Current ID [A]

TE=100μs V =3.5V 1E-4 D VG=-4V Erased

3.5V

CHE Write: VD=2.5V

1E-7

4 3

1E-6 1E-5 1E-4 1E-3 Write/Erase Time [s]

Reverse Read

2

VD=3V

1 0

3.1V

9V

-1

8V

3.2V

VG=7V

3.3V

-2 -3

3.5V

1E-7

1E-6 1E-5 1E-4 1E-3 Write/Erase Time [s]


Figure 3.58. CHE/HHI characteristics of Nitride FinFlash with (WFIN=10 nm, LG=30 nm). Left: ID-VG characteristics. Right: W/E dynamics, with Vth read in forward and reverse mode [RAZ 07]

Written

4

T=150°C

3 2

Forward Reverse

1

10 ys

0

Erased

-1 0

1E0 10

2

1E2 10

4

1E4 10

6

1E6 10

8

1E8 10

Time [s] Figure 3.59. Data retention of Nitride FinFlash at T=150°C with WFIN=10 nm, LG=30 nm (CHE/HHI written/erased) [RAZ 07]


147

7.5 nm

TiN HfO2 Si3N4 Si fin

HTO SiO2

BOX Figure 3.60. Cross-section TEM of the memory FinFlash cell including HfO2 in the IPD [JAH 08]

In [JAH 08], we presented the technological process and electrical behavior of SONOS FinFlash devices fabricated on silicon-on-insulator (SOI) substrates and including HfO2 in the inter poly dielectric (IPD). Using trimming techniques, ultra-scaled devices were processed with aggressive dimensions down to 10 nm channel width and 30 nm gate length (see Figure 3.60). The use of high k IPD leads to an enhancement of the electrical performance in FN operation. As shown in Figure 3.61, due to the enlarged coupling ratio, FN program/erase dynamics are enhanced (with a 2 V improvement in 'VTH compared to HTO IPD devices). Good retention performances at room and high temperature, before and after cycling, have also been obtained (see Figures 3.62 and 3.63).

Threshold Voltage Shift [V]


VP: +8 to +14V

6

TO: HTO+HfO2

5

TO: HTO

4

2V

W/L= 30/10nm

3 2 1 0 1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

Program Time [s]

Threshold Voltage Shift [V]

148

VE: -8 to -14V

4 3 2 1

TO: HTO + HfO2 0

TO: HTO W/L= 30/10nm

-1 1E-07

1E-06

1E-05

1E-04

1E-03

1E-02

Erase Time [s] Figure 3.61. Fowler-Nordheim program/erase characteristics of FinFlash cells (Wfin=10 nm /Lg=50 nm) with HfO2/ HTO IPD vs HTO IPD [JAH 08]


P :+16V / 1ms

4 3

Initial

2

after 10k cycles

1 E: -16V / 3ms

0

10-yrs

Vth @ 1nA [V]

149

-1 -2 1E+01

1E+03

1E+05 Time [s]

1E+07

1E+09

Figure 3.62. Retention characteristics at 25°C of FinFlash cells with HfO2/HTO stack, before and after cycling [JAH 08]

5 P:+16V / 1ms

3 2 1 0

10-yrs

Vth @ 1nA [V]

4

E:-16V / 3ms

-1 -2 1E+01

1E+03

1E+05 Time [s]

1E+07

1E+09

Figure 3.63. Retention characteristics at 150°C of FinFlash cells with HfO2/HTO stack [JAH 08]

In [LOM 07], we showed that corner effects can explain the P/E efficiency of SONOS FinFlash structures and the robustness to erase saturation.

150


As shown in Figure 3.64, an effective field enhancement in the tunnel oxide and a field suppression in the control oxide are evident. This increases with edge curvature.

Figure 3.64. Electric field enhancement factor, defined as the ratio of the electric fields in the region of maximum curvature and in the flat regions, as a function of the vertical coordinate along the gate stack, for different values of the curvature radius, computed at the interface between the silicon fin and the tunnel oxide [LOM 07]

In [NOW 08], we presented a physical semi-analytical model to correctly describe the memory functionality of nitride charge-trap trigate (CT-3G) NVMs under uniform stress (Fowler-Nordheim (FN) program (P) and erase (E)). The model presented innovations in the tunneling current calculation at corners through the Hankel function formalism. The validation of the model has been operated through extensive comparisons with experimental data obtained on ultra-scaled devices with different aspect ratios and gate stacks. Moreover, scaling opportunities of such 3D devices have been deeply discussed. In particular, the scalability of CT-3G appears more critical along wordline pitch than along bitline pitch. Indeed, along bitline pitch, the excellent electrostatic control of a control gate on active channel provides a functional device with ultrascaled length [LOM 07]. However, along wordline, sufficient space has to be found to accommodate the gate stacks at each side of the fin, and the electrical behavior of ultra-small devices have to be demonstrated.


151

In Figure 3.65 we have represented the programming window as a function of the curvature radius Rc, for hemispherical devices [KWA 07], which benefit from the corner field enhancement on the overall active region. The gate stack thickness is kept constant to keep the data retention properties unaltered, through different memory generation. We see that larger devices (limit of plane cells) have a higher saturation value of ǻVT (i.e. t=100 ms) because the capacitance C of top dielectrics becomes smaller going from hemispherical to planar geometry (i.e. ǻVT= -Q/C). However, smaller devices benefit from faster dynamics. According to our model, CT3G of F=22 nm memory generation can be charged to ~5 V starting from a neutral state. This large ǻVT level leaves room for double-bit functionality.

Figure 3.65. ǻVT dependence with the curvature radius for a hemispherical device at different programming time for VG=16 V. The physical thickness of the stack considered is 15 nm [NOW 08]

3.4.9. Molecular charge-based memories It is now clear that the device scaling in Silicon (Si) technologies, and namely in memory applications, is starting to face important issues. In particular, in the few-nanometer range, device performance/reliability will be governed by few electron phenomena [MOL 06b], being strongly sensitive to the unavoidable fabrication spreads. Moreover, the exponentially growing fabrication costs will be one of the main critical factors. In this context, molecular electronics are of growing interest. This kind of technology uses low-cost “bottom-up” approaches (i.e. chemical synthesis, molecular self-assembly), and the behavior of devices is governed by the properties of specifically designed molecular species. In view of tera-bit

152


memories, several concepts of hybrid semiconductor/molecular “crossbar” systems have been suggested [STR 05, GRE 07]. Recent works have demonstrated an electron transfer between Si and redox-active monolayers in a transistor-like structure [GOW 06]. Such an approach seems to be the most suitable starting point for the experimental understanding of memories based on molecular layers, due to the robust signal readout and fewer new process technology steps. Nevertheless, it should be stated that, today, the work in this field is at a starting point. Great challenges in terms of device fabrication and integration still remain, and an extensive set of proof-of-concept experiments should still be provided. Recent papers [PRO 07, PRO 09], proposed an electrical investigation of hybrid molecular/Si memory capacitor structures, where redox active Ferrocene molecules act as a storage medium. Different characterization techniques (cyclic-voltammetry, impedance spectroscopy) enable us to display the strong impact of the engineering of the redox molecules and their molecular linker on the electron transfer properties. In particular, redoxactive two-state ferrocene (Fc) organic molecules have been anchored as a monolayer on an Si surface (p-type, (100) Si), either directly or with a N3(CH2)11 linker, using combined hydrosilylation-cycloaddition reactions. In both cases, the monolayer formation affords a covalent attachment between the Si surface and the organic molecules. X-ray Photoelectron Spectroscopy (XPS) was performed in order to control the chemical composition of the monolayer (Figures 3.66a,b).As a reference sample, structures with redox inert 1-octadecene molecules grafted on Si have also been prepared. Preliminary Cyclic-Voltammetry (CyV) measurements, using moleculegrafted Si working electrodes, were performed under an Argon atmosphere (Figure 3.67a). Note that the voltage in these experiments is referred to the working electrode. Electrochemical capacitors, with an active area of 150 x 300 μm2, were also fabricated (Figure 3.67b). A 2 nm-thick sacrificial oxide was grown on the Si substrate and removed before molecular attachment. The walls which contain the electrolyte are made of 500 nmthick thermal SiO2 plus 10 μm-thick PECVD SiO2. After molecular grafting, an electrolyte solution (1.0 M tetrabutylammonium hexafluorophosphate in propylene carbonate), acting as a conducting gate, was contacted with the molecular monolayer. Capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics were measured with standard equipment, in a nitrogen atmosphere. The gate voltage in these experiments was applied to the Ag tip. Cyclic-voltammetry (CyV) tests are shown in Figures 3.68 and 3.69.

(b)

Counts(a.u.) 1400

720,0 720,0

704,0 704,0

840

F F ee 22p p 11//22

F Fee 22p p33//22

1120 1120

560 560

O O 1s 1s

C C 1s 1s

280 280

0,0 0,0

Si Si 2s 2s Si Si 2p 2p

(b) (b)

0,0 0,0

Si 2p Si 2p

Si Si 2s 2s

(a) C C 1s 1s

280 280

Binding Binding Energy Energy (eV) (eV)

840 840

7733 66 ,,00 772200,,00 770044,,00 B B iin nd d iin ng g E En n ee rrg g yy ((eeV V ))

1400 1400

560

N 1s

Binding Energy (eV)

1120

Binding Binding energy energy (eV) (eV)

Binding Binding Energy Energy (eV) (eV)

736,0 736,0

Fe Fe 2p1/2 2p1/2

O 1s

Figure 3.66. Chemical structures and XPS spectra of Ferrocene functionalized on Silicon with (a) direct grafting and (b) grafting with linker. Insets: high-resolution XPS spectra of Fe 2p regions [PRO 07]

Counts (a.u.) Counts

(a)

Counts(a.u.)

Countsa.u a.u .) Counts (( .)

Fe Fe 2p3/2 2p3/2


154

Silicon Non-Volatile Memories Working Reference electrode electrode (Si/mol) (Pt)

Counter electrode (Pt)

Ag tip

Electrolyte drop

V ~ Molecule monolayer

Si substrate (p-type, 7-10 ȍ*cm, Boron doped)

(a)

(b)

5·10-5

0.5 V/s 0.2 V/s

1·10-5 0

0.1 V/s 0.4

0.8

Scan rate (V/s)

Reduction

1 V/s

3·10-5

1.2

0.1 V/s 0.2 V/s 0.5 V/s 1 V/s

Oxidation

Peak Current(A)

Current [A]

Figure 3.67. (a) Electrical diagram of the cyclic-voltammetry (CyV) experiment. (b) Electrochemical capacitors used for capacitance-voltage (C-V) and conductance-voltage (G-V) measurements [PRO 07]

Voltage [V]

Figure 3.68. CyV of Fc directly grafted on Si (p-type) at different scan rates. Inset: linear dependence between the intensity of the reduction peak and the scan rate [PRO 07]

1 V/s 1.2·1 0 -5

0.5 V/s

8·1 0 -6

0.1 V/s

4·1 0 -6

0

Reduction

Current [A]

PeakC urrent(A )


0.05 V/s 0 .4

0.8

1.2

S can rate (V/s)

Oxidation

0.05 V/s 0.1 V/s 0.5 V/s 1 V/s

Voltage [V] Figure 3.69. CyV of Fc grafted with linker on Si (p-type) at different scan rates. Inset: linear dependence between the intensity of the reduction peak and the scan rate [PRO 07]

6·10-6

Capacitance (Farads/cm2)

100Hz 5·10-6

4·10-6

Ferrocene 3·10-6

2·10-6

1·10-6

1-octadecene -1

-0.5

0

0.5

1

Voltage (V) Figure 3.70. C-V characteristics of redox-active Fc directly grafted on Si and of redox-inert 1-octadecene molecules [PRO 07]

155

156


In Figure 3.68, the oxidation wave (corresponding to the transfer of electrons from the molecules to the Si) and the reduction wave (corresponding to the electrons tunneling back to the molecules from the Si) of Fc molecules without linker clearly appear. The monolayer exhibits a reduction peak at 0.34 V and an oxidation peak at 0.47 V, with a 0.5 V/sec scan rate. The peak amplitude is proportional to the amount of molecules on the Si surface which undergo the redox reactions. A high molecular density can been extracted equal to 6.38x1013 molecules/cm2. CyV results of Fc grafted with linker are shown in Figure 3.69. In this case, the monolayer exhibits a reduction peak at 0.28 V and an oxidation peak at 0.46 V, with a 0.05 V/sec scan rate. The extracted surface coverage is equal to 7.64x1013 molecules/cm2. Note that the larger redox peak separation in the case of Fc molecules grafted on Si with a linker indicates that the electron transport to/from the molecules is lower than in the case of Fc directly grafted on Si, the linker acting as a tunneling barrier for electrons. Electrical properties of molecule/Si systems have then been studied through C-V and G-V measurements. Figure 3.70 shows the C-V curves of the capacitor cells either with Fc directly grafted on Silicon or with the redox-inert molecule. When the gate voltage sweeps up and down, the C-V curve of the Fc cell shows a peak at 0.45 V. These peaks are due to the charging/discharging transient currents associated with the oxidation/reduction of molecules (note that no peak appears on the redox-inert cell curve). We also studied the Fe/Si electron transfer rate behavior by varying the measurement frequency from 100 Hz to 1 kHz (Figure 3.71). An attenuation of the peak intensity on the C-V curve is observed with increasing frequencies, while the G-V peak intensity increases. Indeed, at low frequencies the charge movement can occur at a rate comparable to the measurement signal and is reflected by the presence of the peak, while at high frequencies the electron transfer process becomes rate limited and no capacitance peaks appear [GOW 06]. C-V and G-V experiments also have been carried out on a Fc with linker (Figure 3.72). A peak on the C-V curves appears at -0.8 V, at a frequency of 20 Hz. The higher peak voltage value and the lower threshold frequency denote a slower


157

electron transfer in Fc grafted on Silicon with a linker rather than directly grafted Fc, in agreement with the results obtained from CyV measurements.


In this study, we have shown electrical tests on hybrid Ferrocene organic molecules/Silicon capacitors clearly demonstrating that the charge transfer properties from/to the redox-active monolayer is tuned by the used linker. 100 H z

5 ·1 0 -6

300 H z

4 ·1 0 -6

500 H z 3 ·1 0 -6

1 kH z

2 ·1 0 -6 1 ·1 0 -6

Conductance (S/cm2)

0 .0 1 2

1 kH z

0 .0 0 8

500 Hz 300 Hz

0 .0 0 4

100 Hz -0 .8

-0 .4

0

0 .4

0 .8

V o lta g e (V ) Figure 3.71. C-V and G-V characteristics of Fc directly grafted on Si, performed at different frequencies [PRO 07]


Conductance (S/cm2)


158

5·10 -6

3·10 -6

20 Hz 1·10 -6

100 H z

1.5·10 -3

1·10 -3

5·10 -4

-1.5

-1

0

1

1.5

Voltage(V) Figure 3.72. C-V and G-V characteristics of Fc grafted on Si with a linker, performed at two different frequencies [PRO 07]

Indeed, this indicates that the engineering of the molecular linker, which acts as a tunneling barrier for electrons, could be the key to controling the retention properties of future molecular memory devices. In the same paper [PRO 07], by means of a simple electrical model, it has also been shown that, at a first approximation, Ferrocene molecules grafted on the Silicon substrate can be considered as interface trap states, the trap characteristic parameters directly depending on the redox molecule properties. Finally, we think that the single-electron functionality provided by properly engineered redox-active molecules has enormous potential for application to future tera-bit memories, allowing us to reduce the feature sizes to molecular dimensions and to achieve high-density circuits.


159

In [PRO 09], the geometry and electronic structure of species resulting from the grafting of Ferrocene on Si (100) small clusters were explored by quantum modelling (see Figure 3.73), in the framework of the density functional theory (DFT). In particular, molecular orbital diagrams of direct and indirect grafted systems were investigated. We observed that the shift of the HOMO level in grafted species follows that of the redox potential exactly. It corroborates the observation that the indirect grafting makes the oxidation more difficult to occur. Moreover, the analysis of the HOMO of ferrocene and LUMO of ferrocenium shows that these orbitals are entirely localized on ferrocene. This means that a higher barrier tunnel exists between Fc and Si, making it harder to extract charge from Fc. This is in agreement with CyV, in which a higher peak separation exists in the case of indirect grafting, compared to direct grafting, explained as a higher tunnel barrier.

(a)

(b)

Figure 3.73. Structures of grafted species with ferrocene on a Si34H40 (1 0 0) cluster: a) direct grafting; b) indirect grafting (with C3 chain length). After [PRO 09]

3.4.10. Effects of the few electron phenomena In the previous sections we have shown that, following the ITRS rules [ITR 07], extensive studies are in progress in applied research laboratories and IC companies in order to further scale the NAND and NOR Flash memory cells and to solve the extrinsic reliability concerns (process related variations, ionic contamination) of future floating gate devices [LAI 04]. In this context, it also becomes urgent to address the intrinsic fundamental

160


limits that FG memories will face once in the deca-nanometer range, even before reaching the ultimate single electron memory [SIL 03]. In particular, as the dimensions of flash memories are scaled down, the number of electrons representing one bit N dramatically reduces, enhancing the effects of the single electron phenomena. To precisely quantify this issue, in [MOL 06b], we have studied the impact of the single electron phenomena on the performance and reliability of floating gate memory devices. We demonstrate that the charging and the discharging of scaled floating gate memories should no longer be considered as a continuous phenomenon, but as a sum of discrete stochastic events. This leads to an intrinsic dispersion of both the retention time and of the memory programming window. In Figure 3.74, we have represented the number of electrons per bit N as a function of the technological node, for NAND and NOR devices. First-ofall, we can see that floating gate memory devices use less and less electrons and naturally become few electron devices. Moreover, it appears that the number of electrons per bit is more critical in the case of NAND memory devices than in the case of NOR memory cells, given the smaller cell active area: the number of electrons per bit reduces by a factor ~0.77 for each NAND Flash generation, each generation being defined as a 0.9 size reduction. In other words, the number of electrons which should be stored in the FG in order to correctly set the state of the memory cell, dramatically decreases as the dimensions of Flash memory devices are reduced. For example, the number of electrons per bit for the 35 nm NAND technology node will be equal to 200. It should also be considered that these calculations have been done assuming only one bit per cell, while the use of multi-bit or mulitlevel cell memory technologies [ATW 97, SPA 08] will result in an even more reduced number of electrons per bit. These theoretical calculations can be validated by advanced NOR and NAND devices in the literature, calculated from the described structures, for technology nodes going from 130 nm to 65 nm. Finally, this trend will further strengthen if new technologies are introduced, using limited charge storage sites, such as in Si-Ncs memories [DES 03, MUR 03].

Number of electron per bit, N


161

NOR Flash Projection (ITRS 2003)

'V th-max=3V

1000

NAND Flash Projection (ITRS 2003)

Flash NAND Y.S.Yim, IEDM’03 Y.Sasago, IEDM’03 M.Ichige, VLSI’03 D.C.Kim, IEDM’02 J.D.ChoiI, IEDM’01 C.Park, IEDM’04 Flash NOR Y.Song, IEDM’01 Y.H.Song, VLSI’03 C.Park, VLSI’04 C.Servalli, IEDM’05

100

10 10

Si-nanocrystals memory (NAND )

100

Flash technology node [nm] Figure 3.74. Number of electrons representing one bit as a function of the Flash technology node according to the ITRS 2003 edition [MOL 06b]

Retention time TR probability density [s-1]

0.3

T R @ 20% c ha rge loss N um b er o f ele ctrons p er b it=250

0.2

N=50 0.1

N=10 N=5

0

0

10

20

30

40

50

R eten tio n tim e [ye ars ] Figure 3.75. Probability density of the retention time (TR) for memories with a reduced number of electrons per bit N. The mean TR is fixed at 10 years [MOL 06b]

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Retention time TR relative dispersion (%)

100 80

Model (Eq.5)

Devices: Poly-Si FG Si-nc FG

60 40

Model (Eq.7)

20 0

1

10

100

103

Number of electrons per bit N Figure 3.76. Experimental and theoretical evolution of the relative dispersion of the retention time as a function of the number of electrons per bit [MOL 06b]

In Figure 3.75, we represented the calculated retention time distribution for various numbers of electrons per bit N. This figure shows that a decreasing N implies a strong evolution of the retention time probability density, evolving from a Gaussian-like distribution (when N~250) to a pure exponential/Poisson-like distribution (when N~5). We can also see that the dispersion around the mean value increases as N is reduced. Note that if the memory working includes over-erase process, i.e. if the erased Vth is smaller than Vth0, the same single electron phenomena could occur during retention for the erased state. Indeed, charge gain could also take place, following stochastic behaviors. Widening of the retention time distribution, by scaling the number of electrons per bit, yields to an increase of the relative dispersion of the retention time following a 1/¥N law, which is consistent with the central limit theorem. It is also important to notice that the relative dispersion of the retention time does not depend on the mean retention time. For a retention criterion of 20% of charge loss, we reach a relative dispersion of 10% when the number of electrons involved in one bit is equal to 500, which corresponds to the 55 nm NAND technology node (according to 2003 ITRS edition). We can thus understand the difficulties and theoretical limits of few electron memories, extremely sensitive to the stochastic discharging behavior of the storage node. Figure 3.76 reports the retention time relative


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dispersion as a function of the number of electrons per bit. As the number of electrons per bit N is reduced, we measured an increase in the retention time relative dispersion, with a factor ~2 when we pass from 100 to 10 electrons. Finally, we should note that poly-Si and Si-nc based memories follow comparable dispersion laws, in an experimental and a theoretical way. In conclusion, in the first order, the retention time relative dispersion simply depends on the number of electrons per bit, and is slightly dependant on the nature of the floating gate. Also note that while the increasing of the measurement temperature accelerates the mean retention time, the retention time relative dispersion shows no temperature dependence. Indeed, experiments were performed on the same memory sample at 30°C and at 200°C, and it was found that the retention time relative dispersion remained unchanged, being respectively equal to 52% and 49%. 3.5. Conclusions In these last years, several evolutionary technologies, still based on variations of the well-proven floating-gate architecture, have been studied, in order to extend current floating gate Flash technologies. These approaches essentially consisted of the integration of new materials (such as Silicon- or metal-nanocrystals and nitride traps for the floating gate, and high-k materials for the cell active dielectrics) and in the use of new device architecture (such as multi-gate transistors). Through these solutions, it seems possible to extend current floating gate technologies to the 32 nm and possibly 22 nm nodes. Nevertheless, it should be stated that as the dimensions of Flash memories scale down, the number of electrons representing one bit dramatically reduces, enhancing the effects of the single electron phenomena. Moreover, the number of electrons per bit further reduces in mulitlevel memories which will thus become extremely sensitive to the stochastic discharging behavior of the storage node. This means that the charging and the discharging of ultra-scaled floating gate memories should no longer be considered as a continuous phenomenon, but rather as a sum of discrete stochastic events. This leads to an intrinsic dispersion of both the retention time and of the memory programming window. Finally, we argue that the few electron phenomena will be the intrinsic ultimate scaling limit of

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charge storage memory devices. For this reason, we believe that some disruptive technologies will be required beyond the 22 nm node. 3.6. References [ALE 06] M. Alessandri et al., “High-k materials in Flash memories”, ECS Transactions, 1, 91 (2006). [ATW 97] G. Atwood et al., “StrataFlash”, Intel Technol. J., vol. Q4-97, 1997, Available on line: http://www.intel.com/design/flash/isf/overview.pdf. [BEZ 07] R. Bez et al., “An overview of Flash memories”, ST Microelectronics (now Numonyx), International Workshop on “Emerging Non-Volatile Memories”, Satellite Workshop of ESSDERC 2007, Munich, 14 September 2007, http://www.mdm.infm.it/Versatile /Essderc2007/9-00.pdf [BOC 07] M. Bocquet et al., “NH3 treatments of Hf-based layers for application as NVM active dielectrics”, Proc. of IEEE SISC (Semiconductor Interface Specialists Conference), p.13, 2007. [BOC 08] M. Bocquet et al., “On the role of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories”, Proc. of IEEE ESSDERC, pp. 119–122, 2008. [BOH 04] P. Boher et al., “Automated metrology system including VUV spectroscopic ellipsometry and X-ray reflectometry for 300 mm silicon microelectronics”, Thin Solid Films, vol. 455–456, pp.798-803, 2004. [CAP 99] P. Cappelletti, C. Golla (Eds), Flash Memories, Kluwer Academic Publishers, MA, USA, 1999. [CAM 05] G. Campardo, R. Micheloni, D. Novosel, VLSI-Design Of Non-Volatile Memories, Springer, 2005. [CHE 08] C.H.Chen et al., “Tungsten oxide/tungsten nanocrystals for nonvolatile memory devices”, Appl. Phys. Lett., vol. 92, issue 1, 013114, 2008. [CHI 05] A. Chin et al., “Low voltage high speed SiO2/AlGaN/AlLaO3/TaN memory with good retention”, Techn. Dig. of IEDM, pp.165–168, 2005. [COL 07] J.P. Colonna et al., “Realization of hybrid silicon core/silicon nitride shell nanodots by LPCVD for NVM application”, Proceedings of Materials Research Society Symposium, Vol. 1071, Materials Science and Technology for Nonvolatile Memories, p.17, March 24-27, 2008, San Francisco, USA. [COO 08] J. Cook, “Introduction to Flash memory (T1A)”, Micron Technology Inc., Tutorial at the Flash Memory Summit 2008, http://www.flashmemorysummit.com/English/Conference/ Presentations_Chrono.html. [DEB 02] J. DeBlauwe, “Nanocrystal nonvolatile memories”, IEEE Trans. on Nanotech., vol. 1, no. 72, 2002.


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Technology

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Semiconductors,

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Edition,

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Chapter 4

Future Paths of Innovation

In this chapter, we will try to provide a perspective on the work accomplished up to now and the main paths of research for the future. As discussed in-depth in previous chapters, to reduce bit cost and increase bit density, the shrinking of Flash memories has been aggressively driven by reducing the cell size and introducing multi-level technologies. Nevertheless, the linear scaling-down of multi-level-cell NAND Flash memories is approaching critical physical, electrical and reliability limits. Conventional cost-reduction approaches, notably smaller design rules, are having less effect and new paths should be explored. According to the main IC companies, the short-term way to circumvent these barriers is to stack memory cells on a single Si wafer, so that advanced integration paths suitable for 3D integration of standard IC memory circuits and new design/system solutions should be investigated. Conversely, “new breakthrough memory technologies”, such as phasechange memories, resistive RAMs, insulator and organic polymer crossbar memories, are also considered as possible candidates for future memory applications. In the last part of this chapter, we will give a general overview of their main advantages and disadvantages in view of future memory applications.

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4.1. 3D integration of charge-storage memories Today, three-dimensional (3D) integration is recognized as an enabling technology for several types of future ICs and low-cost micro/nano/electroopto/bio heterogenous systems [SIL 08]. It can form highly integrated systems by vertically stacking and connecting various materials, technologies and functional components together [LU 09] (see Figure 4.1).

Figure 4.1. Diagram of a heterogenous system formed by 3D integration [LU 07, LU 09]

Figure 4.2. Roadmap for the introduction of 3D technologies in different integrated circuits [NIK 07]

Future Paths of Innovation 173

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The potential benefits of 3D integration can vary depending on the approach; they include multifunctionality, increased performance, reduced power, small form factor, reduced packaging, increased yield and reliability, flexible heterogenous integration and reduced overall costs. A small form factor is achieved by stacking active component layers on top of one another in any 3D approach. Looking forward, the first killer 3D applications would probably be extremely high-density heterogenous memory stacks (e.g. NAND Flash, SRAM, DRAM) and high-resolution/low-cost imagers, followed perhaps by 3D integration of mixed signal/RF circuits with digital CMOS (see Figure 4.2, [NIK 07]). Advanced handheld devices will also continue to drive the mix and match of various 3D approaches. A variety of 3D approaches may be combined to offer more flexible integration with even higher functionality, signal integrity or added value [LU 09]. Various 3D technologies are currently pursued by different companies. According to [LU 07, LU 09], these can be divided into three main categories (Figure 4.3): – 3D packaging technologies: (a) system-in-package (SiP) and packageon-package (PoP), enabled by wire bonding and flip-chip bonding; today’s new cell phone products have at least one SiP or PoP. (b) Die-to-die 3D integration enabled by thinned die-to-die bonding and through-silicon-via (TSV) interconnections. (c) Die-to-wafer bonding; this approach uses techniques from both packaging and wafer fab, such as die pick-and-place and TSV formation, respectively. – Transistor buildup 3D technologies: (d) transistors formed on recrystallized silicon film, where an amorphous silicon film is deposited with a catalyst followed by either laser heating or rapid thermal anneal to recrystallize the silicon. Transistors are then formed by BEOL compatible processing (e.g. Stanford University in the USA). (e) Transistors formed on poly-silicon films layer by layer with W interlayer vias, where an amorphous silicon film is deposited and converted to poly-silicon (e.g. MATRIX SEMI in the USA). W vias can tolerate the relatively high temperatures (~600qC) needed for poly-silicon conversion and transistor formation. These transistors may be used to fabricate low-performance nonvolatile memory [CRO 03]. (f) Transistors formed on single-crystal silicon films layer by layer, where the silicon layer can be bonded onto the oxide surface of a previously fabricated transistor layer by transferring the crystal silicon film from a silicon-on-insulator (SOI) wafer. Then the interstrata via is filled with poly-silicon and/or tungsten, enabling device fabrication at relatively high


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temperatures. Very high-density SRAMs and NANDs (see Figure 4.4) are demonstrated with this approach [HWA 06, JUN 04, JUN 06]. – Monolithic, wafer-level, back-end-of-the-line (BEOL)-compatible 3D hyper-integration: enabled by wafer alignment, bonding, thinning and interwafer interconnections (see Figure 4.3g). All approaches use TSVs to form the interstrata interconnections. They differ as to when the via is formed, before/during bonding (via-first) or after bonding (via-last); in addition, a variety of bond layer types can be chosen: (h) via-last, oxide-tooxide bonding, (i) via-last, adhesive (polymer) bonding, (j) via-first, copperto-copper bonding and (k) via-first, metal/adhesive redistribution layer bonding.

Figure 4.3. Illustrations of major 3D integration technologies according to [LU 07, LU 09]

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As previously mentioned, the multi-chip package (MCP), using wirebonding to mount multiple chips in one package is already in production. In November 2006, Samsung announced the development of the industry’s first process to enable innovative production of a 16-chip MCP of memory [SAM 06a]. The new MCP technology supports the industry-wide demand for small form factors and high-densities that will accommodate multimedia-intensive user mobile applications. Samsung’s new 16-chip MCP technology, when applied to 8Gb NAND flash chips, can enable up to a 16 gigabyte (GB) MCP solution. Advanced multi-chip package technology requires a combination of key processes such as wafer thinning technology, redistribution layer technology, chip sawing technology and wire bonding technology. At ISSCC 2009 the University of Tokyo and Toshiba [ISH 09] jointly presented a 3D integrated solid-state drive (SSD) that addresses what they called the key design issue for SSD development – decreasing power consumption (see Figure 4.4). The solution was a stack of NAND Flash chips, DRAM, a NAND controller, and a new low-power voltage generator. In this application, the 3D integration lowers power consumption, because of its short interconnects. At the same conference, Samsung described the use of 3D TSV stacking to overcome future DRAM performance issues. Nevertheless the 3D packaging technologies have been aimed at users who demand smaller mounting footprints even at a higher cost. In fact, simple stacking of chips or packages with bonding and packing technologies cannot reduce the bit cost, because the already completely integrated chips are stacked.


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Figure 4.4. (a) Comparison of the power consumption of NAND Flash memories and (b) structure of the 3D-integrated SSD proposed by Toshiba and the University of Tokyo [ISH 09]

Conversely, wafer-level processing can also reduce costs for high-volume production. In transistor buildup 3D technology, layers are stacked with minimum processes and are interconnected simultaneously with bottom cell arrays and peripheral circuits. This offers the highest density of Si transistors using advanced photolithography. However, the processing constraints (particularly the thermal budget) affect the properties of the transistors and limit the material choices mostly to silicon and tungsten. The Si recrystallization approach (Figure 4.3d) could be used for fabrication of repeaters within interconnect to alleviate interconnect delay. The poly-Si layer approach (Figure 4.3e) is used for low performance memory. The bonded crystal Si approach (Figure 4.3f) can be used for an NAND flash memory stack (see Figures 4.5 and 4.6).

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Companies that manufacture cell phones and handhelds see great potential for a high-density memory stack [PAR 08, ILK 08]. This approach can provide a reduction in manufacturing costs because it does not require state-of-the-art production lines. The prices of manufacturing equipment have soared with each new generation, and using depreciated equipment would have a major impact on cost. High-volume production would drop manufacturing costs even further. At ISSCC 2008, Samsung presented a 3D double stacked 45 nm 4 Gb MLC NAND Flash memory device [PAR 08] with shared bitline structure. Nevertheless, with the memory array stacking approach, the bit cost could increase if the number of stacked layers increases significantly, due to yield loss and area penalty (in terms of peripheral circuits).

2D Approach

3D Integration Moore rule continuity

Figure 4.5. NAND Flash memory manufacturing costs. 3D IC technology would make it possible to maintain the current pace of cost reduction [NIK 07, SAM 06]


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(a)

(b) Figure 4.6. (a) Vertical structure (top: diagram; bottom: SEM photograph) of the 3D stacked TANOS Nand cell string. Bit-line and common source line (CSL) are formed through 2nd active layer. The 2nd active layer is SOI-like perfect single crystal [SAM 06]. (b) 4Gb memory array with 3D double stacked memory devices [PAR 08]

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To solve this issue, a new 3D memory cell array structure has recently been introduced by Toshiba (see Figure 4.7) [TOS 07]. In the new structure, pillars of stacked memory elements pass vertically through multi-stacked layers of electrode material and utilize shared peripheral circuits. Toshiba’s cutting edge etching technology drives a hole down through a stacked substrate, i.e. a multi-layer sandwich of gate electrodes and insulator films. Pillars of silicon lightly doped with impurities are deposited to fill in the holes. The gate electrode wraps around the silicon pillar and the ONO gate stack at even intervals. This new NAND array increases density without increasing chip dimension, as the number of connected elements increases in direct proportion to stack height. For example, a 32-layer stack realizes 10 times the integration of a standard chip formed with the same generation of technology.

Figure 4.7. Diagram (top) and SEM image (bottom) of the 3D SONOS NAND array [TOS 07]


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In [TOS 07b], an optimized process integration for array devices of bitcost scalable (BiCS) flash memory is presented. They adopted SiN-based gate dielectrics for consistency with the “gate-first” process, which is unique to BiCS Flash technology, and “macaroni” body FETs for better controllability over the sub-threshold characteristics of depletion-mode polysilicon transistors. With these technologies and a newly devised 4F2 cell array, BiCS Flash is ascribed as a promising candidate for future ultra-high density memory. Nevertheless, we believe that this approach, which makes use of vertical poly-Si transistors, will probably require many years of optimization to achieve a competitive reliable product.

(a)

(b) Figure 4.8. (a) The initial (SiGe/Si)xn hetero-epitaxy on SOI determines the number of stacked wires, thickness and spacing. After fin etching, the wires are freed in situ (i.e. the same etching reactor). (b) The developed technology opens new integration opportunities for ultimate integration like new 3D memory concepts The bitcost reduction on flash may continue thanks to 3D crystalline stacking with common gates [ERN 08]

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In [ERN 08], we also presented at IEDM 2008 an original 3D memory structure based on silicon-on-insulator (SOI) or innovative silicon-onnothing (SON) 3D nanowires. We used standard microelectronics equipment for SiGe/Si superlattice epitaxy, its anisotropic etching and a SON-like selective SiGe etching (Figure 4.8a). For memories, we proposed an application example of a 3D crystalline nanowires matrix with common gates for word lines (control gates) as an opportunity to limit the number of technological steps and continue flash memory density increase (Figure 4.8b). Finally, it is commonly assumed that the appearance of 3D IC technology will significantly reshape the semiconductor industry and the related applied research fields, which have been dominated until now by the pursuit of evershrinking design rules. There are however strong challenges [LU 09]. Even though in theory 3D IC promises lower costs and higher performance, there is no guarantee that the theory can be put into practice in actual products. 3D IC technology has its own hurdles, different from those of design rules; including thermal management, reliable co-design and simulation tools, industrial wafer-to-wafer bonding tools, through-wafer via structures and via fill processes combined with low cost and high yield. New integration diagrams, new device architectures (with new operational diagrams), manufacturing and test methods for debugging technologies are today challenging research fields. Moreover, the optimal utilization of the third dimension requires a careful design of the overall 3D system architecture. Planar design involves placing each component in (x,y) space with a rotation. In 3D design, developers must determine the number of layers in a stack and place components in (x,y,z) with rotation and flip. Very strong spatial visualization and reasoning are essential prerequisites for successful 3D design. It is worth mentioning that some of the technological issues of future ultra-scaled memories could probably be solved by improved design methods and embedded system management techniques. With regard to the design techniques we can mention, for example, the “better-than-worst-case” (BTWC) techniques [MAR 07, CON 03], which aim to correct at a design level the manufacturing uncertainties of nano-scale technologies (giving rise to functional and parametric yield loss). This includes for example: statistical


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design optimization to avoid the accumulation of design margins; and extensions for self-adaptive architectures, enabling the system to tune its available hardware to the actual (performance/power) requirements. Concerning the system management techniques, it is widely believed that different application will require specific system level solutions as technology scales (see Figure 4.9, [DOL 06]). For example, it is clear that deploying NAND systems in today’s SoC designs requires highly integrated solutions to address mulitlevel-cell (MLC) issues of data integrity and system performance. Hardware and software solutions are necessary, including error correction codes (ECC) to repair bad bits, similar to SS HDD, wear leveling, and block management. Sensing diagram accuracy and speed, programming algorithm flexibility (for charge placement) and page segmentation are other significant features.

Figure 4.9. Application requirements in terms of technology and system solutions [DOL 06]

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In this context, in recent years significant efforts have been made by the designers’ community [KAM 07] to alleviate system design problems caused by the lack of standardization of NAND Flash. This standardization is necessary to support the continued proliferation of NAND Flash into new applications such as PMP (personal media players) and solid state disks, as well as migration into the PC platform as cache to enable fast boot. One solution for example, is the implementation of block abstraction (BA). Current NAND Flash devices feature physical address access that defines each physical memory array from the block, to the page and down to the byte of data. The driver in the host controller must recognize and accommodate this complicated physical addressing. Any change in device density requires modifications to the driver in the host controller, hindering use of the new component. BA simplifies host controller design by allowing the host to treat the Flash as a pool of addressable blocks of data, without having to manage those blocks. BA, therefore, eliminates the sensitivity host controllers might have to changes in NAND Flash device requirements such as advanced ECC, which cannot be readily accommodated without host controller redesign. In other words, BA frees the host controller from the traditional NANDspecific functions such as ECC (error correction and checking), wearleveling, and bad block management, which may now be performed by the NAND Flash controller along with other Flash memory management functions. The emergence of MLC NAND requires the use of advanced ECC and complex software drivers. BA would simplify the overall system design. This method of addressing the memory is similar to what is used currently in hard drives, whereby the drive is accessed by linearly addressing sector addresses. Figure 4.10 shows the differences in the two NAND Flash architectures [KAM 07].


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Low Level Driver

Low Level Driver

Figure 4.10. Top: diagram of physical addressed NAND based system; bottom: diagram of block abstracted NAND based system [KAM 07]

4.2. Alternative technologies As previously mentioned, today the majority of non-volatile memory is based on charge storage and is fabricated by materials available in CMOS processes. These devices have some general shortcomings like slow programming (from microseconds up to milliseconds), limited endurance (typically 105 – 106 write/erase cycles) as well as the need for high voltages (10–20 V) during programming and erase. These shortcomings imply some severe restrictions on the system design side. A memory that works like a random access memory (similar to DRAM or SRAM) and is also nonvolatile would therefore greatly simplify system design, since one “universal memory” could be used, where two or three memories are required today.

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Moreover, much higher data densities than the current ones will be required for storing multimedia data such as videos. This calls for a memory with an extremely small bit cell size. To achieve these goals, novel materials showing new switching mechanisms have to be introduced into the CMOS process flow. Figure 4.11 shows the hierarchy of possible CMOS memory material extensions [MIK 02, MIK 07]. In the following, we will give a general outlook of some possible newtechnologies currently studied in the literature. Among the different approaches, we will focus our attention on an emerging concept based on the exploitation of resistive switching phenomena and on the use BEOL (backend-of-line) processes.

Figure 4.11. The hierarchy of options for today’s and future non-volatile memories [MIK 02, MIK 07]


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4.2.1. Ferro RAMs Ferro RAMs (FeRAM) exploit the direction of the electrical polarization in ferroelectric materials (like PZT, i.e. PbZrxTi1-xO3, and SBT). Intensive studies during the last two decades have enabled FRAM to be successful in limited products of ~4 Mb in density. Even though FRAM is still struggling with large cell size, reliability of FRAM has been greatly improved to guarantee more than 1,015 endurance and 10 year retention at 85°C by the successful introduction of MOCVD PZT-film technology and oxide electrode technology [LEE 06, KIM 07]. High endurance has been obtained and a 64 Mb memory has been demonstrated [HOY 06]. FRAM, whose cell architecture is identical to DRAM, can ideally reach its cell size down to 6F2, which is the cell size of current DRAM in the case of open bit-line architecture. However, cell size of current FRAM, where most advanced 1Transistor-1Capacitor technologies have been implemented, is 15F2 at a 150 nm technology node, still far from its ideal size. The most important parameter in FRAM is the sensing signal margin like in DRAM. 3D capacitors are required for sub-90 nm technology [KIM 07]. Material engineering is required at each scaling node. Reading is destructive and scalability is very poor. The main advantage is the low power consumption. 4.2.2. Magnetic RAMs In Magnetic RAMs (magnetoresistive random access memories (MRAM, the data is stored as the spin state in a magnetic medium. They offer fast write/read and high endurance, but they need a high write current. MRAM scalability is difficult because of increased current density for smaller cell size. MRAMs have been in development for over 15 years, but only recently has come onto the market with Freescale Semiconductor’s 4 Mbit, which offers 35 ns symmetrical read/write with a data retention greater than 10 years, making it a solid alternative to battery-backed SRAM [PRI 06]. It is worth mentioning that, as one of the most promising spintronic applications, MRAM combines the advantages of high writing and reading speed, limitless endurance and non-volatility. So, the integration of MRAM in FPGA (field programmable gate array) has recently been invoked, this

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will allow the logic circuit to rapidly configure the algorithm, the routing and logic functions and easily realize the dynamic reconfiguration and multicontext configuration. In [ZHA 07], a French group addressed some design techniques for FPGA logic circuits based on thermally assisted switching (TAS) MRAM technology. 4.2.3. Phase-change RAMs Phase-change RAMs (PCRAM) use the reversible phase change between the crystalline and amorphous state of chalcogenide materials, such as Ge2Sb2Te5 (GST), by joule heating. With passage of switch current from electrode to the GST, the region around the contact heats up (see Figure 4.12) and can be quenched in the high resistance amorphous phase [LAI 02, LAI 08].

Top Electrode Poly Crystalline GST Amorphous

Heater

Bottom Electrode

Figure 4.12. PCRAM memory element


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Table 4.1. PCRAM technology benchmarking [LAC 07]

The highly resistive amorphous phase (RESET state, with several M: resistance) is formed by short pulses of intense electric power. This can be obtained through a large current flow (~l mA) with a short time pulse (~100 ns). Alternatively, the poly-crystalline state (SET state, with only a few k: resistance) can be obtained through a relatively small current flow with a longer pulse (~500 ns), thus heating it between melting and crystalline temperature from which gradual crystal growth occurs. Since 4 Mb density PCRAM was firstly introduced in 2002 by Intel, it has displayed the fastest technology evolution [LAC 06, KIM 07, RAU 08]. Today, several companies are working on PCRAMs (see Table 4.1), and the technology is expected to be mass-produced in the near future. PCRAM has great potential not only to provide adequate solutions for solving the scaling issues that other conventional non-volatile memories might face in the near future, but it can also create new functions and applications with its fast write programming speed and direct overwrite capability [KIM 07].

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PCRAMs are foreseen as a valuable solution for different memory systems [EIL 09], for short-term code storage (NOR replacement) and for long-term data storage applications (NAND replacement), when multilevel solutions will be available. Furthermore, PCRAM can be easily merged with logic technologies with minimized additional photo-mask steps, thus offering great opportunities in the embedded memory applications. They are also studied as storage class memories for future replacement of disk drives [FRE 08]. A PCRAM cell must be formed by the variable resistor (heater and GST) in series with a selector device. Hence, the basic PCM cell has a 1transistor/1resistor structure. The type of transistor and of data-storage varies respectively as a function of the application, and of the process architecture strategy [BEZ 08] (see Figure 4.13). For embedded memory the transistor can be a n-channel MOS, where a larger cell size is balanced by a minimum process cost overhead with respect to the reference CMOS. The integration of the resistor occurs between the front-end and the backend of the CMOS process [BEZ 08]. For high-density memory, a compact cell layout has been achieved via the vertical integration of a pnp bipolar transistor [PEL 04]. Since PCRAM is a kind of resistive RAM where a uni-directional pulse is used for cell programming and reading, a diode with large current driving capability could also be used as cell switch for improving serial resistance [OH 06, KIM 07]. A diode-type switch enables PCRAM to achieve a minimum 4F2 cell size (see Figure 4.14).

Figure 4.13. Possible integration paths of PCRAM cells [PEL 04, PIR 07]

Future Paths of Innovation 191

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Figure 4.14. SEM image of unit cell of Samsung 512b PCRAM with diode type cell switch [OH 06]

One of the critical topics to be solved in view of optimization of the PCRAM technology is represented by the reset current, which is substantially high, limiting the minimum width of the transistor needed to drive and sustain this current, thus resulting in a larger cell size. The reset current controllability and reduction is fundamental to guaranteeing a compact and scalable cell size (see Figure 4.15), a competitive writing power consumption and enhanced reliability. Solutions studied in the literature to solve this issue follow two main paths: device architecture and material innovation. Power delivered to a heating element is the key parameter for determining a stable operation of PCRAM and can be formulated as follows [KIM 07]: PRESET = RH x V2 / (RH + RS) 2 = RH x V2 / RS2 where RH is the resistance of the heating element (RH

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