Power Electronics: Principles and Elements

Power Electronics ii Table of Contents 1 1 Principles and Elements Basic Semiconductor Physics and Technology of ...

Author: B.W. Williams

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Power Electronics

ii

Table of Contents

1 1

Principles and Elements

Basic Semiconductor Physics and Technology

of

1.1

Example 1.1: Resistance of homogeneously doped silicon 2 Processes forming and involved in forming semiconductor devices 4 1.1.1 Alloying 1.1.2 Diffused Example 1.2: Constant Surface Concentration diffusion – predepostion 7 Example 1.3: Constant Total Dopant diffusion – drive in-1 8 Example 1.4: Constant Total Dopant diffusion – drive in-2 8 1.1.3 Epitaxy growth - deposition 1.1.4 Ion-implantation and damage annealing Example 1.5: Ion implantation 12

POWER ELECTRONICS Devices, Drivers, Applications, and Passive Components

1.2

Thin Film Deposition 1.2.1 1.2.2

1.3

Thermal oxidation and the masking process

17

1.4

Polysilicon deposition

20

Lithography – optical and electron

21

1.5.

1.5.1 1.5.2 1.6

Barry W Williams

1.7

B.Sc., Dipl.Eng., B.Eng., M.Eng.Sc., Ph.D., D.I.C. Professor of Electrical Engineering University of Strathclyde Glasgow

BWW

Optical Lithography Electron Lithography

Etching 1.6.1 1.6.2

Published by Barry W Williams ISBN 978-0-9553384-0-3 © Barry W Williams 2006

13

Chemical Vapour Deposition (CVD) Physical Vapour deposition (PVD)

26

Wet Chemical Etching Dry Chemical Etching

Lift-off Processing

32

1.8

Resistor Fabrication

32

1.9

Isolation Techniques

33

1.10

Wafer Cleaning

33

1.11

Planarization

35

1.12

Gettering

35

1.13

Lifetime control

36

1.14

Silicide formation

36

1.15

Ohmic contact

38

1.16

Glassivation

41

1.17

Back side metallisation and die separation

41

1.18

Wire bonding

41

Power Electronics

iii

1.19

Power Electronics

Types of silicon

43

3.2

1.19.1 Purifying silicon 1.19.2 Crystallinity 1.19.3 Single crystal silicon 1.19.3i Czochralski process 1.19.3ii Float-zone process 1.19.3iii Ribbon silicon 1.19.4 Multi-crystalline Silicon 1.19.5 Amorphous Silicon Silicon Carbide

48

1.21

Si and SiC physical and electrical properties compared

48

51

The pn Junction Example 2.1:

2.2

Built-in potential of an abrupt junction

52

The pn junction under forward bias (steady-state)

53

The pn junction under reverse bias (steady-state)

53

2.2.1 2.2.2 2.2.3

Punch-through voltage Avalanche breakdown Zener breakdown

2.3

Thermal effects Example 2.2: Diode forward bias characteristics

2.4

Models for the bipolar junction diode 2.4.1 Piecewise-linear junction diode model Example 2.3: Using the pwl junction diode model Example 2.4: Static linear diode model 2.4.2 Semiconductor physics based junction diode model Example 2.5:

3.3 54

Thyristors 3.3.1

55

3.3.2 3.3.3 3.3.4 3.3.5

56 56

2.4.2i - Determination of zero bias junction capacitance, Cjo 2.4.2ii - One-sided pn diode equations Space charge layer parameter values 61

65

Power Switching Devices and their Static Electrical Characteristics The pn fast-recovery diode The p-i-n diode The power Zener diode The Schottky barrier diode The silicon carbide Schottky barrier diode

86

The silicon-controlled rectifier (SCR)

The asymmetrical silicon-controlled rectifier (ASCR) The reverse-conducting thyristor (RCT) The bi-directional-conducting thyristor (BCT) The gate turn-off thyristor (GTO) The gate commutated thyristor (GCT) 3.3.6i - GCT turn-off 3.3.6ii - GCT turn-on

3

Power diodes

73

3.3.5i - GTO turn-off mechanism

3.3.6

3.4

3.1.1 3.1.2 3.1.3 3.1.4 3.1.5

70 70

3.3.1i - SCR turn-on 3.3.1ii - SCR cathode shorts 3.3.1iii - SCR amplifying gate

55

3.3.7 3.3.8

3.1

The bipolar npn power switching junction transistor (BJT)

3.2.1i - BJT gain 3.2.1ii - BJT operating states 3.2.1iii - BJT maximum voltage - first and second breakdown 3.2.2 The metal oxide semiconductor field effect transistor (MOSFET) 3.2.2i - MOSFET structure and characteristics 3.2.2ii - MOSFET drain current 3.2.2iii - MOSFET transconductance and output conductance 3.2.2iv - MOSFET on-state resistance 3.2.2v - MOSFET p-channel device Example 3.1: Properties of an n-channel MOSFET cell 78 3.2.2vi - MOSFET parasitic BJT 3.2.2vii - MOSFET on-state resistance reduction 1 - Trench gate 2 - Vertical super-junction 3.2.3 The insulated gate bipolar transistor (IGBT) 81 3.2.3i - IGBT at turn-on 3.2.3ii - IGBT in the on-state 3.2.3iii - IGBT at turn-off 3.2.3iv - IGBT latch-up 1 - IGBT on-state SCR static latch-up 2 - IGBT turn-off SCR dynamic latch-up 3.2.4 Reverse blocking NPT IGBT 84 3.2.5 Forward conduction characteristics 85 3.2.6 PT IGBT and NPT IGBT comparison 85 3.2.7 The junction field effect transistor (JFET) 85

2

2.1

Power switching transistors 3.2.1

1.20

iv

65

The light triggered thyristor (LTT) The triac

Power packages and modules

98

4 101

Electrical Ratings and Characteristics of Power Semiconductor Switching Devices 4.1

General maximum ratings of power switching semiconductor devices 101 4.1.1 4.1.2 4.1.3 4.1.4

Voltage ratings Forward current ratings Temperature ratings Power ratings

Power Electronics

v

4.2

The fast-recovery diode 4.2.1 4.2.2 4.2.3

4.3

Power Electronics

5.4

103

Transistor ratings 4.3.1i - BJT collector voltage ratings 4.3.1ii - BJT safe operating area (SOA)

4.3.2

Transistor switching characteristics

5.5

4.3.2i - BJT turn-on time 4.3.2ii - BJT turn-off time

4.3.3 4.4

5.6

111

Dynamic characteristics 4.4.2i - MOSFET device capacitances 4.4.2ii - MOSFET switching characteristics 1 - MOSFET turn-on 2 - MOSFET turn-off

4.5

5.7 116

The insulated gate bipolar transistor 4.5.1 4.5.2

4.6

MOSFET drain characteristics

4.6.2 4.6.3

5.7.1

Switching transition power loss, Ps Off-state leakage power loss, PA Conduction power loss, Pc Drive input device power loss, PG 150

Heat-sinking for diodes and thyristors

Example 5.6: Heat-sink design for a diode 152 5.7.2 Heat-sinking for IGBTs Example 5.7: Heat-sink design for an IGBT - repetitive operation at a high duty cycle 153 5.7.3 Heat-sinking for power MOSFETs Example 5.8: Heat-sink for a MOSFET - repetitive operation at high peak current, low duty cycle 154 Example 5.9: Heat-sink design for a mosfet - repetitive operation at high duty cycle 155 Example 5.10: Two thermal elements on a common heatsink 155 156 Example 5.11: Six thermal elements in a common package

119

SCR ratings 4.6.1i - SCR anode ratings 4.6.1ii - SCR gate ratings

Static characteristics 4.6.2i - SCR gate trigger requirements 4.6.2ii - SCR holding and latching currents

5.8

High-performance cooling for power electronics

157

Dynamic characteristics

5.9

Conduction and heat spreading

157

Heat-sinks

159

The gate turn-off thyristor

5.10

5.10.1 5.10.2 5.10.3 5.10.4 5.10.5

122

4.7.1 Turn-on characteristics 4.7.2 Turn-off characteristics 4.8

148

5.7.1i - Low-frequency switching 5.7.1ii - High-frequency switching

4.6.3i - SCR anode at turn-on 4.6.3ii - SCR anode at turn-off

4.7

Graphical integration Practical superposition

Heat-sinking design cases

117

IGBT switching IGBT short circuit operation

The thyristor 4.6.1

148

Power losses from manufacturers’ data sheets 5.6.1 5.6.2 5.6.3 5.6.4

MOSFET absolute maximum ratings

Example 4.1:

136

Average power dissipation 5.5.1 5.5.2

BJT phenomena

The power MOSFET 4.4.1 4.4.2

Modes of power dissipation

5.4.1 Steady-state response 5.4.2 Pulse response Example 5.1: Semiconductor single power pulse capability 139 Example 5.2: A single rectangular power pulse 141 5.4.3 Repetitive transient response Example 5.3: Semiconductor transient repetitive power capability 142 Example 5.4: Composite rectangular power pulses 143 Example 5.5: Non-rectangular power pulses 145

Turn-on characteristics Turn-off characteristics Schottky diode dynamic characteristics

The bipolar, high-voltage, power switching npn junction transistor 106 4.3.1

vi

Appendix: Effects on MOSFET switching of negative gate drive

124 5.11 5.12

5 Cooling of Power Switching Semiconductor Devices

Required heat-sink thermal resistance Heat-sink selection Heat sink types Heatsink fin geometry Thermal performance graph

Heatsink cooling enhancements

166

Heatsink fan and blower cooling

166

5.12.1 Fan selection 5.12.2 The fan Laws Example 5.12: Fan laws 5.12.3 Estimating fan life Example 5.13: Fan lifetime Example 5.14: Fan testing

125

173 177 178

5.1

Thermal resistances

128

5.13

Enhanced air cooling

179

5.2

Contact thermal resistance

128

5.14

Liquid coolants for power electronics cooling

180

5.2.1 5.2.2 5.3

5.14.1 Requirements for a liquid coolant 5.14.2 Dielectric liquid coolants 5.14.3 Non-dielectric liquid coolants

Thermal Interface Materials Phase Change Gasket Materials (solid to liquid)

Heat-sinking thermal resistance

132

5.15

Direct and indirect liquid cooling

184

Power Electronics

vii

5.16

Indirect liquid cooling 5.16.1 Heat pipes – indirect cooling Example 5.15: Heat-pipe 5.16.2 Cold plates – indirect cooling Example 5.16: Cold plate design

5.17

Power Electronics

7

184

247 191

Driving Transistors and Thyristors

199

7.1

Direct liquid cooling

Application of the power MOSFET and IGBT

200

7.1.2 Gate drive design procedure Example 7.1: MOSFET input capacitance and switching times 255

5.18

Microchannels and minichannels

205

5.19

Electrohydrodynamic and electrowetting cooling

207

5.20

Liquid metal cooling

208

5.21

Solid state cooling

209

7.2

Appendix: Comparison between aluminium oxide and aluminium nitride 217

5.24

Appendix: Properties of substrate and module materials

219

5.25

Appendix: Emissivity and heat transfer coefficient

221

5.26

Appendix: Ampacities and mechanical properties of rectangular copper busbars 223

267

8.1

The non-polarised R-C snubber

268

8.1.1 R-C switching aid circuit for the GCT, the MOSFET, and the diode 269 Example 8.1: R-C snubber design for MOSFETs 8.1.2 Non-polarised R-C snubber circuit for a converter grade thyristor and a triac Example 8.2: Non-polarised R-C snubber design for a converter grade thyristor 271 8.2

The soft voltage clamp Example 8.3:

8.3

Soft voltage clamp design

272 273

Polarised switching-aid circuits

275

8.3.1 The polarised turn-off snubber circuit - assuming a linear current fall 8.3.2 The turn-off snubber circuit - assuming a cosinusoidal current fall Example 8.4: Capacitive turn-off snubber design 282 8.3.3 The polarised turn-on snubber circuit - with air core (non-saturable) inductance Example 8.5: Turn-on air-core inductor snubber design 288 8.3.4 The polarised turn-on snubber circuit - with saturable ferrite inductance Example 8.6: Turn-on ferrite-core saturable inductor snubber design 291 8.3.5 The unified turn-on and turn-off snubber circuit

229

6.1.1 The resistive load Example 6.1: Resistive load switching losses 232 Example 6.2: Transistor switching loss for non-linear electrical transitions 233 6.1.2 The inductive load Example 6.3: Zener diode, switch voltage clamping 235 Example 6.4: Inductive load switching losses 239 6.1.3 Diode reverse recovery with an inductive load Example 6.5: Inductive load switching losses with device models 240

8.4

Snubbers for bridge legs

294

Switch characteristics

242

8.5

Appendix: Non-polarised turn-off R-C snubber circuit analysis

297

Switching classification

242

8.6

Appendix: Polarised turn-off R-C-D switching aid circuit analysis

298

6.3.1 6.3.2 6.3.3 6.3.4 6.4

264

Protecting Diodes, Transistors, and Thyristors

224

Load, Switch, and Commutation Considerations

6.3

Drive design for GCT and GTO thyristors

8

229

6.2

263

215

6 Load types

255

Thyristor gate drive circuits i. Vacuum cleaner suction control circuit ii. Lamp dimmer circuit iii. Back EMF feedback circuits

7.3

5.23

6.1

Application of the Thyristor 7.2.1

7.2.2 Thyristor gate drive design Example 7.2: A light dimmer

Cooling by phase change

Appendix: Isolated substrates for power modules

Gate drive circuits 7.1.1i - Negative gate drive 7.1.1ii - Floating power supplies 1 - capacitive coupled charge pump 2 - diode bootstrap

210 211

5.22

5.27

247

7.1.1

5.17.1 Immersion cooling – direct cooling 5.17.2 Liquid jet impingement – direct cooling 5.17.3 Spray cooling – direct cooling

5.21.1 Thermoelectric coolers Example 5.17: Thermoelectric cooler design Example 5.18: Thermoelectrically enhanced heat sink 5.21.2 Superlattice and heterostructure cooling 5.21.3 Thermionic and thermotunnelling cooling

viii

Hard switching Soft switching Resonant switching Naturally-commutated switching

Switch configurations

244

Power Electronics

ix

Power Electronics

9

10.2 303

Switching-aid Circuits with Energy Recovery 9.1

Energy recovery for inductive turn-on snubber circuits-single ended 9.1.1 9.1.2

9.2

9.3.1 9.3.2 9.4

Snubbers for series connected devices 9.6.1 9.6.2 9.6.3 9.6.4

Example 10.5: AC circuit fuse link design 10.3.1v – Pulse derating

314

364 2

Example 10.6: AC circuit fuse link design for I t surges 10.3.1vi - Other fuse link derating factors Example 10.7: AC circuit fuse link derating 10.3.1vii - Fuse link dc operation Example 10.8: DC circuit fuse link design 10.3.1viii - Alternatives to dc fuse operation 10.3.2 Protection with resettable fuses

320

Example 10.9: Resettable ceramic fuse design 10.3.3 Summary of over-current limiting devices 10.4

324

General passive snubber energy recovery concepts

369

379

Overvoltage

Example 10.10: Non-linear voltage clamp 10.4.2 Transient voltage fold-back devices

9.8

367

381

10.4.1 Transient voltage suppression devices 10.4.1i - Comparison between Zener diodes and varistors

Turn-off snubber circuit active energy recovery Turn-on snubber circuit active energy recovery Turn-on and turn-off snubber circuit active energy recovery General active recovery concepts

Snubber energy recovery for magnetically coupled based switching circuits 331 9.7.1 Passive recovery 9.7.2 Active recovery

366

10.3.2i Polymeric PTC devices 10.3.2ii Ceramic PTC devices

323

9.7

388

10.4.2i The surge arrester 10.4.2ii Thyristor voltage fold-back devices 10.4.2iii Polymeric voltage variable material technologies 10.4.2iv The crowbar

10.4.3 Coordination protection 10.4.4 Summary of voltage protection devices 10.5

333

Interference

397

10.5.1 Noise 10.5.1i - Conducted noise 10.5.1ii - Radiated electromagnetic field coupling 10.5.1iii - Electric field coupling 10.5.1iv - Magnetic field coupling

10

10.5.2 Mains filters 10.5.3 Noise filtering precautions

339

Device Series and Parallel Operation, Protection, and Interference 10.1

356 2

9.5.1 Snubbers for the cascaded H-bridge multi-level inverter 9.5.2 Snubbers for the diode-clamped multi-level inverter 9.5.3 Snubbers for the flying-capacitor clamped multi-level inverter 9.6

Over-current Protection 10.3.1i - Pre-arcing I t 2 10.3.1ii - Total I t let-through 2 10.3.1iii - Fuse link and semiconductor I t co-ordination 10.3.1iv - Fuse link derating and losses

Turn-on snubbers Turn-on and turn-off snubbers

Snubbers for multi-level inverters

353

10.3.1 Protection with fuses

Passive recovery Active recovery

Inverter bridge legs 9.4.1 9.4.2

9.5

10.3


Unified turn-on and turn-off snubber circuit energy recovery

Protection overview - over-voltage and over-current 10.2.1 Ideal secondary level protection 10.2.2 Overvoltage protection devices 10.2.3 Over-current protection devices

Energy recovery for capacitive turn-off snubber circuits-single ended 307 9.2.1 9.2.2

9.3

303


x

Parallel and series connection and operation of power semiconductor devices 339 10.1.1 Series semiconductor device operation 10.1.1i - Steady-state voltage sharing

Example 10.1: Series device connection – static voltage balancing 341

Earthing

400

11 Naturally Commutating AC to DC Converters - Uncontrolled Rectifiers

10.1.1ii - Transient voltage sharing

Example 10.2: Series device connection – dynamic voltage balancing 344 10.1.2 Parallel semiconductor device operation 10.1.2i - Matched devices 10.1.2ii - External forced current sharing

Example 10.3: Resistive parallel current sharing – static current balancing

10.6

11.1 347

(a) current sharing analysis for two devices:– ro = 0 (b) current sharing analysis for two devices:– ro ≠ 0 (c) current sharing analysis for n devices:– ro = 0 Example 10.4: Transformer current sharing–static and dynamic current balancing 352

Single-phase uncontrolled converter circuits - ac rectifiers

403

11.1.1 Half-wave circuit with a resistive load, R 11.1.2 Half-wave circuit with a resistive and back emf R-E load Example 11.1: Half-wave rectifier with resistive and back emf load 405 11.1.3 Single-phase half-wave circuit with an R-L load 11.1.3i - Inductor equal voltage area criterion 11.1.3ii - Load current zero slope criterion

403

Power Electronics

xi

Power Electronics

11.1.4x Half-wave rectifier circuit with a R load and capacitor filter Example 11.2: Half-wave rectifier with source resistance 410 11.1.4 Single-phase half-wave circuit with an R-L load and freewheel diode Example 11.3: Half-wave rectifier – with load freewheel diode 414 11.1.5 Single-phase full-wave bridge rectifier circuit with a resistive load, R 11.1.6 Single-phase full-wave bridge rectifier circuit with a resistive and back emf load Example 11.4: Full-wave rectifier with resistive and back emf load 417 11.1.7 Single-phase full-wave bridge rectifier circuit with an R-L load 11.1.7i

12.1

12.2

Example 12.1: Half-wave controlled rectifier 12.2.2 Single-phase half-wave half-controlled

12.2.3 Single-phase full-wave controlled rectifier circuit with an R-L load 12.2.3i - α > φ , β - α < π , discontinuous load current 12.2.3ii - α = φ , β - α = π , verge of continuous load current 12.2.3iii - α < φ , β- π = α, continuous load current (and also purely inductive load) 12.2.3iv Resistive load, β = π

11.2.2i - Three-phase full-wave bridge rectifier circuit with continuous load current 11.2.2ii - Three-phase full-wave bridge rectifier circuit with highly inductive load 11.2.2iii Three-phase full-wave bridge circuit with highly inductive load with an EMF source 11.2.2iv Three-phase full-wave bridge circuit with capacitively filtered load resistance Example 11.7: Three-phase full-wave rectifier 435 Example 11.8: Rectifier average load voltage 436

Example 12.2: Controlled full-wave converter – continuous and discontinuous conduction 495 12.2.4 Single-phase full-wave, fully-controlled circuit with R-L and emf load, E 12.2.4i - Discontinuous load current 12.2.4ii - Continuous load current Example 12.3: Controlled converter - continuous conduction and back emf 502 Example 12.4: Controlled converter – constant load current, back emf, and overlap 503

437 12.3

11.3.1 Effect of multiple coils on multiple limb transformers 11.3.2 Single-phase toroidal core mmf imbalance cancellation – zig-zag winding 11.3.3 Single-phase transformer connection, with full-wave rectification 11.3.4 Three-phase transformer connections 11.3.5 Three-phase transformer, half-wave rectifiers - core mmf imbalance 11.3.6 Three-phase transformer with hexa-phase rectification, mmf imbalance 11.3.7 Three-phase transformer mmf imbalance cancellation – zig-zag winding 11.3.8 Three-phase transformer full-wave rectifiers – zero core mmf Voltage multipliers 11.4.1 Half-wave series multipliers 11.4.2 Half-wave parallel multipliers 11.4.3 Full-wave series multipliers Example 11.9: Half-wave voltage multiplier Example 11.10: Full-wave voltage multiplier 11.4.4 Three-phase voltage multipliers 11.4.5 Series versus parallel voltage multipliers

489

12.2.2i - discontinuous conduction 12.2.2ii - continuous conduction

11.2.1 Three-phase half-wave rectifier circuit with an inductive R-L load 11.2.2 Three-phase full-wave rectifier circuit with an inductive R-L load

11.4

485

12.2.1i - Case 1: Purely resistive load 12.2.1ii - Case 2: Purely inductive load 12.2.1iii - Case 3: Back emf E and R-L load

428

DC MMFs in converter transformers

Single-phase controlled thyristor converter circuits 12.2.1 Single-phase half-wave circuit with an R-L load

11.1.7ii - Single-phase full-wave bridge rectifier with highly inductive loads–constant load current 11.1.7iii - Single-phase full-wave bridge rectifier circuit with a C-filter and resistive load Example 11.6: Single-phase full-wave bridge circuit with C-filter and resistive load 426 11.1.7iv - Other single-phase bridge rectifier circuit configurations

11.3

478

12.1.2 Single-phase, full-wave, half-controlled circuit with R-L and emf load, E

- Single-phase full-wave bridge rectifier circuit with an output L-C filter

Three-phase uncontrolled rectifier converter circuits

Single-phase full-wave half-controlled converter 12.1.1i - Discontinuous load current 12.1.1ii - Continuous load current

11.1.7ii Single-phase, full-wave bridge rectifier circuit with an R-L-E load Example 11.5: Full-wave diode rectifier with L-C filter and continuous load current 423

11.2

xii

Three-phase half-controlled converter

503

12.3i - α ≤ ⅓π 12.3ii - α ≥ ⅓π

12.4

Three-phase fully-controlled thyristor converter circuits

506

12.4.1 Three-phase half-wave, fully controlled circuit with an inductive load 12.4.2 Three-phase half-wave converter with freewheel diode 12.4.2i - α < π/6 12.4.2ii - α > π/6 12.4.2iii - α > 5π/6

462

Example 12.5: Three-phase half-wave rectifier with freewheel diode 508 12.4.3 Three-phase full-wave fully-controlled circuit with an inductive load 12.4.3i - Resistive load 12.4.3ii - Highly inductive load – constant load current 12.4.3iii - R-L load with load EMF, E

466 467

Example 12.6: Three-phase full-wave controlled rectifier with constant output current 514 12.4.4 Three-phase full-wave converter with freewheel diode Example 12.7: Converter average load voltage 517

11.5

Marx voltage generator

467

11.6

Definitions

469

11.7

Output pulse number

470

11.8

AC-dc converter generalised equations

470

12.7

Overlap

518

12.6

Overlap – inversion

522

12.7

Summary

Example 12.8: Converter overlap

523

524

(i) Half-wave and full-wave, fully-controlled converter (ii) Full-wave, half-controlled converter (iii) Half-wave and full-wave controlled converter with load freewheel diode

12 Naturally Commutating AC to DC Converters - Controlled Rectifiers

477

12.8

Definitions

526

12.9

Output pulse number

526

12.10


528

Power Electronics

xiii

Power Electronics

13

13.6 537

Single-phase ac regulator

537

13.7

13.2

Resistive Load Pure inductive Load Load sinusoidal back emf Semi-controlled single-phase ac regulator

Example 13.1a: Single-phase ac regulator – 1 547 Example 13.1b: Single-phase ac regulator - 2 549 Example 13.1c: Single-phase ac regulator – pure inductive load 549 Example 13.1d: Single-phase ac regulator – 1 with ac back emf composite load 551 13.1.2 Single-phase ac regulator – integral cycle control – line commutated Example 13.2: Integral cycle control 554 13.1.3 The solid-state relay (SSR)

14

13.1.3i Principle of operation 13.1.3ii Key power elements in solid-state relays 13.1.3iii Solid-state relay overvoltage fault modes 13.1.3iv Standard transient voltage protection devices, reviewed in terms of SSR requirements 13.1.3v Solid-state relay internal protection methods 13.1.3vi Application considerations Example 13.3: Solid-state relay turn-on 563 Example 13.4: Solid-state relay heatsink requirements 563 13.1.3vii DC output solid-state relays

14.2

Single-phase transformer tap-changer – line commutated Example 13.5: Tap changing converter

13.3 13.4

613

14.1

Three-phase ac regulator

570

13.4.1 Fully-controlled three-phase ac regulator with wye load and isolated neutral Purely resistive load i. 0 ≤ α ≤ ⅓π [mode 3/2] ii. ⅓π ≤ α ≤ ½π [mode 2/2] iii. ½π ≤ α ≤ π [mode 2/0]

614

14.2.2 Discontinuous load current Steady-state time domain analysis of first quadrant chopper - with load back emf and discontinuous output current i. Fourier coefficients ii. Time domain differential equations

Example 14.1: DC chopper (first quadrant) with load back emf 622 Example 14.2: DC chopper with load back emf - verge of discontinuous conduction 626 Example 14.3: DC chopper with load back emf - discontinuous conduction 627 14.3

Second Quadrant dc chopper

630

14.3.1 Continuous load inductor current 14.3.2 Discontinuous load inductor current Example 14.4: Second quadrant DC chopper - continuous inductor current 635

14.5

13.4.2 Fully-controlled three-phase ac regulator with wye load and neutral connected 13.4.3 Fully-controlled three-phase ac regulator with delta load 13.4.4 Half-controlled three-phase ac regulator Resistive load i. 0 ≤ α ≤½π ii. ½π ≤ α ≤ ⅔π iii. ⅔π ≤ α ≤ 7π/6

Two quadrant dc chopper - Q I and Q II

637

13.4.6i The induction motor 13.4.6ii Background to induction machine starting 13.4.6iii Solid-state soft-starter 13.4.6iv Soft-starter control and application

599

Two quadrant dc chopper – Q 1 and Q IV

644

14.5.1 dc chopper: – Q I and Q IV – multilevel output voltage switching (three level) 14.5.2 dc chopper: – Q I and Q IV – bipolar voltage switching (two level) 14.5.3 Multilevel output voltage states, dc chopper Example 14.6: Asymmetrical, half H-bridge, dc chopper 649 14.6

Purely inductive load 13.4.5 Other thyristor three-phase ac regulators i. Delta connected fully controlled regulator ii. Three-thyristor delta connected regulator Example 13.6: Star-load three-phase ac regulator – untapped neutral 583 13.4.6 Solid-state soft starters

Cycloconverter

First Quadrant dc chopper

Example 14.5: Two quadrant DC chopper with load back emf 640

i. ½π ≤ α ≤ ⅔π [mode 3/2] ii. ⅔π ≤ α ≤ π [mode 2/0]

13.5

613

i. Fourier coefficients ii. Time domain differential equations

14.4

Inductive-resistive load Purely inductive load

DC chopper variations

14.2.1 Continuous load current Steady-state time domain analysis of first quadrant chopper - with load back emf and continuous output current

565

568

607

DC Choppers

567

Single-phase ac chopper regulator – commutable switches

Power Quality: load efficiency and supply current power factor

13.7.1 Load waveforms 13.7.2 Supply waveforms Example 13.7: Power quality - load efficiency 609 Example 13.8: Power quality - sinusoidal source and constant current load 610 Example 13.9: Power quality - sinusoidal source and non-linear load 610

13.1.1 Single-phase ac regulator – phase control with line commutation Case 1: α > φ Case 2: α ≤ φ 13.1.1i 13.1.1ii 13.1.1iii 13.1.1iv -

601

13.6.1 High frequency resonant dc to ac matrix converter

AC Voltage Regulators 13.1

The matrix converter

xiv

Four quadrant dc chopper

651

14.6.1 Unified four quadrant dc chopper - bipolar voltage output switching 14.6.2 Unified four quadrant dc chopper - multilevel voltage output switching Example 14.7: Four quadrant dc chopper 658

Power Electronics

xv

Power Electronics

15

661

DC to AC Inverters - Switched Mode 15.1

dc-to-ac voltage-source inverter bridge topologies

xvi

16

719

DC to AC Inverters - Resonant Mode 661

15.1.1 Single-phase voltage-source inverter bridge 15.1.1i - Square-wave (bipolar) output 15.1.1ii - Quasi-square-wave (multilevel) output

Example 15.1: Single-phase H-bridge with an L-R load 657 668 Example 15.2: H-bridge inverter ac output factors Example 15.3: Harmonic analysis of H-bridge with an L-R load 670 Example 15.4: Single-phase half-bridge with an L-R load 671

16.1

Resonant dc-ac inverters

719

16.2

L-C resonant circuits 16.2.1 - Series resonant L-C-R circuit 16.2.2 - Parallel resonant L-C-R circuit

720

16.3

Series resonant inverters 16.3.1 - Series resonant inverter – single inverter leg

724

1 - Lagging operation (advancing the switch turn-off angle) 2 - Leading operation (delaying the switch turn-on angle)

15.1.1iii - PWM-wave output

15.1.2 Three-phase voltage-source inverter bridge

16.3.2 - Series resonant inverter – H-bridge voltage-source inverter 16.3.3 - Circuit variations

15.1.2i - 180° (π) conduction 15.1.2ii - 120° (⅔π) conduction

15.1.3 Inverter ac output voltage and frequency control techniques 15.1.3i - Variable voltage dc link 15.1.3ii - Single-pulse width modulation

Example 15.5: Single-pulse width modulation

681 15.1.3iii - Multi-pulse width modulation 15.1.3iv - Multi-pulse, selected notching modulation – selected harmonic elimination 15.1.3v - Sinusoidal pulse-width modulation (pwm) 1 - Natural sampling 2 - Regular sampling 3 - Frequency spectra of pwm waveforms 15.1.3vi - Phase dead-banding 15.1.3vii - Triplen Injection modulation 1 - Triplens injected into the modulation waveform 2 - Voltage space vector pwm

16.4

Parallel-resonant voltage-source inverter – single inverter leg

16.5

Series-parallel-resonant voltage-source inverter – single inverter leg 729

728

Summary of voltage source resonant inverters 16.6

Parallel resonant current-source inverters

731

16.6.1 - Parallel resonant inverter – single inverter leg 16.6.2 - Parallel resonant inverter – H-bridge current-source inverter

Example 16.1: Half-bridge with a series L-C-R load 16.7

733

Single-switch, current source, series resonant inverter

736

15.1.4 Common mode voltage 15.1.5 DC link voltage boosting 15.2

dc-to-ac controlled current-source inverters

698

15.2.1 Single-phase current source inverter 15.2.2 Three-phase current source inverter 15.3

Multi-level voltage-source inverters 15.3.1 15.3.2 15.3.3 15.3.4 15.3.5

17

702

Diode clamped multilevel inverter Flying capacitor multilevel inverter Cascaded H-bridge multilevel inverter Capacitor clamped multilevel inverter PWM for multilevel inverters

17.1

The forward converter 17.1.1 17.1.2 17.1.3 17.1.4

15.3.4i - Multiple offset triangular carriers 15.3.4ii - Multilevel rotating voltage space vector

15.4

Reversible dc link converters

Standby inverters and uninterruptible power supplies

Power filters

Continuous inductor current Discontinuous inductor current Load conditions for discontinuous inductor current Control methods for discontinuous inductor current

17.1.5 Output ripple voltage 745 Example 17.1: Buck (step-down forward) converter 17.1.6 Underlying operational mechanisms of the forward converter Example 17.2: Hysteresis controlled buck converter 752

712

17.2 715

15.5.1 Single-phase UPS 15.5.2 Three-phase UPS 15.6

740

17.1.4i - fixed on-time tT, variable switching frequency fvar 17.1.4ii - fixed switching frequency fs, variable on-time tTvar

15.4.1 Independent control 15.4.2 Simultaneous control 15.4.3 Inverter regeneration 15.5

739

DC to DC Converters - Switched Mode

717

17.3

Flyback converters

753

The boost converter

754

17.3.1 17.3.2 17.3.3 17.3.4 17.3.5

Continuous inductor current Discontinuous capacitor charging current in the switch off-state Discontinuous inductor current Load conditions for discontinuous inductor current Control methods for discontinuous inductor current 17.3.5i - fixed on-time tT, variable switching frequency fvar 17.3.5ii - fixed switching frequency fs, variable on-time tTvar

17.3.6 Output ripple voltage Example 17.3: Boost (step-up flyback) converter 758 Example 17.4: Alternative boost (step-up flyback) converter 760

Power Electronics

xvii

17.4

The buck-boost converter 17.4.1 17.4.2 17.4.3 17.4.4 17.4.5

17.6

822


18.4

Resonant coupled-load configurations

825

Example 18.1: Transformer-coupled, series-resonant, dc-to-dc converter 827 767

18.5 769

The output reversible converter

772

829

18.5.1i - Zero-current, full-wave resonant switch converter

18.5.2 Zero-current, resonant-switch, dc-to-dc converter -½ wave, CR parallel with switch version 18.5.3 Zero-voltage, resonant-switch, dc-to-dc converter

Continuous inductor current Discontinuous inductor current Load conditions for discontinuous inductor current Control methods for discontinuous inductor current

-½ wave, CR parallel with switch version

18.5.3i - Zero-voltage, full-wave resonant switch converter

The Ćuk converter 17.7.1 Continuous inductor current 17.7.2 Discontinuous inductor current 17.7.3 Optimal inductance relationship 17.7.4 Output voltage ripple Example 17.7: Cuk converter

Resonant switch, dc to dc step-down voltage converters

18.5.1 Zero-current, resonant-switch, dc-to-dc converter -½ wave, CR parallel with load version

18.5.4 Zero-voltage, resonant-switch, dc-to-dc converter -½ wave, CR parallel with load version Example 18.2: Zero-current, resonant-switch, dc-to-dc converter - ½ wave 842 Example 18.3: Zero-current, resonant-switch, dc-to-dc converter - full-wave 844 Example 18.4: Zero-voltage, resonant-switch, dc-to-dc converter - ½ wave 845

Example 17.6: Reversible forward converter 775 17.6.5 Comparison of the reversible converter with alternative converters

17.8

819

Series–parallel load resonant dc to dc converters 18.3.1 LCC resonant tank circuit 18.3.2 LLC resonant tank circuit


17.7

Parallel loaded resonant dc to dc converters 18.2.1 Modes of operation- parallel resonant circuit 18.2.2 Circuit variations

18.3

Flyback converters – a conceptual assessment

17.6.1 17.6.2 17.6.3 17.6.4

18.2

762

xviii

Continuous choke (inductor) current Discontinuous capacitor charging current in the switch off-state Discontinuous choke current Load conditions for discontinuous inductor current Control methods for discontinuous inductor current

17.4.6 Output ripple voltage 17.4.7 Buck-boost, flyback converter design procedure Example 17.5: Buck-boost flyback converter 17.5

Power Electronics

777 18.6

Resonant switch, dc to dc step-up voltage converters

846

18.6.1 ZCS resonant-switch, dc-to-dc step-up voltage converters 18.6.2 ZVS resonant-switch, dc-to-dc step-up voltage converters 779

Comparison of basic converters

Summary and comparison of ZCS and ZVS Converters 780

18.7

Appendix: Matrices of resonant switch buck, boost, and buck/boost converters 850

17.8.1 Critical load current 17.8.2 Bidirectional converters 17.8.3 Isolation 17.8.3i - The isolated output, forward converter 17.8.3ii - The isolated output, flyback converter

Example 17.8: Transformer coupled flyback converter Example 17.9: Transformer coupled forward converter 17.9

19

786 788

Multiple-switch, balanced, isolated converters 17.9.1 The push-pull converter 17.9.2 Bridge converters

17.10

Basic generic smps transfer function mapping

793

17.11

Appendix: Analysis of non-continuous inductor current operation

795

19.1

HVDC electrical power transmission

855

19.2

HVDC Configurations

856

19.2i - Monopole and earth return 19.2ii - Bipolar 19.2iii - Tripole 19.2iv - Back-to-back 19.2v - Multi-terminal

Operation with constant input voltage, Ei Operation with constant output voltage, vo

18 18.1

Series loaded resonant dc to dc converters 18.1.1 Modes of operation - series resonant circuit 18.1.2 Circuit variations

19.3

Typical HVDC transmission system

857

19.4

Twelve-pulse ac line frequency converters

858

19.4.1 Rectifier mode 19.4.2 Inverter mode

813

DC to DC Converters - Resonant Mode 814

855

HV Direct-Current Transmission

790

19.5

Twelve-pulse ac line frequency converter operation control 19.5.1 Control and protection 19.5.2 HVDC Control objectives

866

Power Electronics

xix

19.6

Power Electronics

Filtering and power factor correction

870

20.10

VSC-Based HVDC

873

19.7.1 VSC-Based HVDC control 19.7.2 Power control concept 19.8

HVDC Components

924

20.10.1 - Current compensation – shunt filtering 20.10.2 - Voltage compensation – series filtering 20.10.3 – Hybrid Arrangements 20.10.4 - Active and passive combination filtering

Example 19.1: Basic six-pulse converter based hvdc transmission 870 Example 19.2: 12-pulse hvdc transmission 871 19.7

Combined Active and Passive Filters

xx

877

20.11

Summary of Compensator Comparison and Features

928

20.12

Summary of General Advantages of AC Transmission over DC Transmission 928

Example 19.3: HVDC transmission with voltage source controlled dc-link 878 19.9

Twelve-pulse transformer based HVDC

880

19.10

HVDC VSC Features

881

19.11

Features of conventional HVDC and HVAC transmission

881

21 929

Inverter Grid Connection for Embedded Generation 21.1

Distributed generation

929

21.1.1 DG Possibilities 21.1.2 Integration and Interconnection Requirements 21.2

20

20.1

Flexible AC Transmission Systems - FACTS

883

20.2

Power Quality

884

20.3

Principles of Power Transmission

884 886

20.4

The theory of instantaneous power in three-phase

887

20.5

FACTS Devices

890

20.6

Static Reactive Power Compensation

891

20.7

Static Shunt Reactive Power Compensation

892

20.7.1 - Thyristor controlled reactor TCR 20.7.2 - Thyristor switched capacitor TSC 20.7.3 - Shunt Static VAr compensator SVC (TCR//TSC) Example 20.2: Shunt thyristor controlled reactor specification 898 20.8

Static Series Reactive Power Compensation

Custom Power

22 937

Energy Sources and Storage - Primary Sources 22.1

Hydrocarbon attributes

937

22.2

The fuel cell

939

22.3

Materials and cell design

941

22.3.1 22.3.2 22.3.3 22.3.4 22.3.5 22.4

Electrodes Catalyst Electrolyte Interconnect Stack design

Fuel Cell Chemistries

944

+

22.4.1 Proton H Cation Conducting Electrolyte 22.4.2 Anion (OH-, CO32-, O2-) Conducting Electrolyte 899

20.8.1 - Thyristor switched series capacitor TSSC 20.8.2 - Thyristor controlled series capacitor TCSC 20.8.3 - Series Static VAr compensator SVC (TCR//C) Example 20.3: Series thyristor controlled reactor specification – integral control 903 Example 20.4: Series thyristor controlled reactor specification – Vernier control 905 20.8.4 Static series phase angle reactive power compensation/shift SPS 20.9

933

883

FACTS Devices and Custom Controllers

Example 20.1: AC transmission line VAr

Interfacing conversion methods

909

20.9.1 - Static synchronous series compensator or Dynamic Voltage Restorer - DVR 20.9.2 - Static synchronous shunt compensator – STATCOM 20.9.3 - Unified power flow controller - UPFC

22.5

Six different Fuel Cells

947

22.6

Low-temperature Fuel Cell Types

947

22.6.1 Polymer exchange membrane fuel cell 22.6.2 Alkaline fuel cell 22.6.3 Direct-methanol fuel cell 22.7

High-temperature Fuel Cell Types

950

22.7.1 Phosphoric-acid fuel cell 22.7.2 Molten-carbonate fuel cell 22.7.3 Solid oxide fuel cell 22.8

Fuel Cell Summary

954

Power Electronics

xxi

Power Electronics

22.9

Fuels

954

22.10

Fuel Reformers

956

23 999

Energy Sources and Storage - Secondary Sources

22.10.1 Natural gas reforming 22.11

Hydrogen storage and generation from hydrides

958

23.1

22.12

Fuel Cell Emissions

960

23.2

22.13

Fuel Cell Electrical characteristics

960

22.14

Thermodynamics Example 22.1: Formation of water vapour Example 22.2: Derivation of Ideal Fuel Cell Voltage Example 22.3: Carbon fuel cell Fuel Cell features

966

22.16

Fuel Cell Challenges

967

Fuel cell summary

968

22.18

Photovoltaic Cells: Converting Photons to Electrons

971

22.19

Silicon structural physics

971

22.20

Semiconductor materials and structures

972

22.21

Characteristics of Secondary Batteries

1004 1007

23.4.1 Basic lead-acid cell theory 23.4.2 Cell/battery construction 23.4.3 Characteristics of the flooded lead-acid cell 23.4.4 Different lead-acid cell and battery arrangements 23.4.5 Lead acid battery charging and storage regimes 23.4.6 Valve-regulated battery discharge characteristics Example 23.1: Lead-acid battery discharge characteristics 1023 Example 23.2: Lead acid battery life 1025 23.4.7 Gassing and internal recombination 23.4.8 User properties and cell type comparisons

Example 22.4: Solar cell characteristics 22.24

Module (or array) series and parallel PV cell connection Example 22.5: PV cell and module characteristics

23.10

Battery storage

991

22.26

The organic photovoltaic cell

992

22.27

Summary of PV cell technology

994

The lithium-ion battery

1049

Cathode variants cells General Lithium-ion Cell characteristics General Lithium-ion Cell properties Cell protection circuits

Battery Thermodynamics

1061

Summary of key primary and secondary cell technologies

1064

The Electrochemical Double Layer Capacitor - supercapacitor

1065

23.10.1 Double layer capacitor model Example 23.6: Ultracapacitor module design using a given cell 1069 23.10.2 Cell parameter specification and measurement methods 23.10.3 Cell characteristics 23.10.4 Thermal Properties 23.10.5 Estimated life duration 23.10.6 Cell Voltage Equalization in a Series Stack of Ultracapacitors 23.10.7 Supercapacitor general properties 23.10.8 Pseudocapacitors Example 23.7: Ultracapacitor constant current characteristics 1079

990

22.25

1042

Example 23.5: Electrochemistry – battery thermodynamics 1063 23.9

989

The nickel-metal-hydride battery

23.7.1 23.7.2 23.7.3 23.7.4

987 988

1033 1038 1040

23.6.1 Nickel-metal-hydride battery properties 23.6.2 Nickel-metal-hydride battery characteristics 23.6.3 Comparison between NiCd and NiMH Cells

23.8

Photovoltaic cell efficiency factors

The nickel-cadmium battery Example 23.3: NiCd battery electrolyte life Example 23.4: NiCd battery requirement 23.5.1 Nickel-Cadmium battery properties

985

22.22.1 Ideal PV cell model 22.22.2 Practical PV cell model 22.22.3 Maximum-power point 22.23

23.5

23.7

Equivalent circuit of a PV cell

1000

The lead-acid battery

982

Homojunction Device Heterojunction Device p-i-n and n-i-p Devices Multi-junction Devices

The secondary electro-chemical cell

23.4

23.6

PV Cell Structures 22.21.1 22.21.2 22.21.3 22.21.4

22.22

Silicon Polycrystalline thin films Single-Crystalline Thin Film Nanocrystalline

999

23.3

22.16.1 Chemical Technology Challenges 22.16.2 System Technology Challenges 22.17

Batteries

23.2.1 REDOX Galvanic Action 23.2.2 Intercalation Action

961 962 963 965

22.15

22.20.1 22.20.2 22.20.3 22.20.4

xxii

23.11

Thermoelectric modules 23.11.1 Background

1081

Power Electronics

xxiii

23.11.2 Thermoelectric materials 23.11.3 Mathematical equation for a thermoelectric module 23.11.4 Features of Thermoelectric Cooling - Peltier elements 23.11.5 TE cooling design Example 23.8: Thermoelectric cooler design 23.11.6 Thermoelectric power generation Example 23.9: Thermoelectric generator design 23.11.7 Thermoelectric performance

Power Electronics

24.3.5 DC plastic capacitors 24.4 1093 1097

24.5

Appendix:

Primary cells

1100

23.13

Appendix:

Empirical Battery Model

1102

Ceramic dielectric capacitors

1136

Mica dielectric capacitors

1139

24.6.1 Properties and applications

24 1103

Capacitors Capacitor general properties 24.1.1 Capacitance 24.1.2 Volumetric efficiency 24.1.3 Equivalent circuit 24.1.4 Lifetime and failure rate Example 24.1: Failure rate Example 24.2: Capacitor reliability 24.1.5 Self-healing 24.1.6 Temperature range and capacitance dependence 24.1.7 Dielectric absorption

1104

24.7

Capacitor type comparison based on key properties

1141

24.8

Appendix: Minimisation of stray capacitance

1141

24.9

Appendix: Capacitor lifetime derating

1142

1108 1109

25

Liquid (organic) and solid, metal oxide dielectric capacitors 24.2.1 Construction 24.2.2 Voltage ratings 24.2.3 Leakage current 24.2.4 Ripple current Example 24.3: Capacitor ripple current rating 24.2.5 Service lifetime and reliability

1111

Example 24.4: A1203 capacitor service life

25.1 25.2 1115

1117 1118

Plastic film dielectric capacitors

25.3 1119

1146

Resistor construction

1146

1148

Electrical properties

1149

25.3.1 Resistor/Resistance coefficients 25.3.1i - Temperature coefficient of resistance

24.3.1 Construction

Example 25.2: Temperature coefficient of resistance for a thick film resistor 1152

24.3.1i - Metallised plastic film dielectric capacitors 24.3.1ii - Foil and plastic film capacitors 24.3.1iii - Mixed dielectric capacitors

25.3.1ii - Voltage coefficient of resistance

25.3.2 Maximum working voltage 25.3.3 Residual capacitance and residual inductance Example 25.3: Coefficients of resistance for a solid carbon ceramic resistor 1155

24.3.2 Insulation 24.3.3 Electrical characteristics 24.3.3i - Temperature dependence 24.3.3ii - Humidity dependence 24.3.3iii - Time dependence 24.3.3iv - Dissipation factor and impedance 24.3.3v - Voltage derating with temperature 24.3.3vi – Voltage and current derating with frequency

Example 24.6: Power dissipation limits - ac voltage

Resistor types

25.2.1 Film resistor construction 25.2.2 Carbon composition film resistor construction Example 25.1: Carbon film resistor 25.2.3 Solid Carbon ceramic resistor construction 25.2.4 Wire-wound resistor construction

24.2.5ii - Solid, oxide capacitors

Example 24.5: Lifetime of tantalum capacitors

1145

Resistors

24.2.5i - Liquid, oxide capacitors

24.3

1134

24.5.1 Class I dielectrics 24.5.2 Class II dielectrics 24.5.3 Applications 24.6

24.2

Emi suppression capacitors 24.4.1 Class X capacitors 24.4.2 Class Y capacitors 24.4.3 Feed-through capacitors

23.12

24.1

xxiv

25.4

Thermal properties

1155

25.4.1 Resistors with heatsink Example 25.4: Derating of a resistor mounted on a heatsink 1158 25.4.2 Short time or overload ratings Example 25.5: Non-repetitive pulse rating 1159 1129

24.3.3vii - Pulse dVR /dt rating

24.3.4 Non-sinusoidal repetitive voltages Example 24.7: Capacitor non-sinusoidal voltage rating 1131 Example 24.8: Capacitor power rating for non-sinusoidal voltages 1131

25.5

Repetitive pulsed power resistor behaviour Example 25.6: Pulsed power resistor design 25.5.1 Empirical pulse power 25.5.2 Mathematical pulse power models

1159 1160

Power Electronics

xxv

Example 25.7: Solid carbon ceramic resistor power rating 25.6

1161

Stability and endurance Example 25.8: Power resistor stability

25.7

Power Electronics

1164

Example 26.4: Inductor design including copper loss 26.5.2 Saturable inductors 26.5.3 Saturable inductor design Example 26.5: Saturable inductor design 26.6

Appendix: Carbon ceramic electrical and mechanical data and formula 1172

25.9

Appendix: Characteristics of resistance wire

25.10

Appendix: Preferred resistance values of resistors (and capacitors) 1172

26 1175

26.1

Inductor and transformer electrical characteristics

1176

Magnetic material types

1178

26.2.1i - Steel 26.2.1ii - Iron powders 26.2.1iii - Alloy powders 26.2.1iv - Nanocrystalline

Comparison of material types

1179

26.4

Ferrite characteristics

1180

26.4.1 Dimensions and parameters 26.4.2 Permeability Initial or intrinsic permeability, µi ∧ Amplitude permeability, µa and maximum permeability, µ Reversible or incremental permeability, µrev, µ∆ Effective permeability, µe Complex permeability, µ

26.4.3 Coercive force and remanence 26.4.4 Core losses

26.8

Appendix: Soft ferrite general technical data

1221

26.9

Appendix: Technical data for a ferrite applicable to power applications

1221

26.10

Appendix: Technical data for iron, nickel, and cobalt applicable to power applications 1222

26.11

Appendix: Cylindrical inductor design

1223 1223 1224

26.12

Appendix: Copper wire design data

1225

26.13

Appendix: Minimisation of stray inductance

1225

26.11.2i - Capacitors 26.11.2ii - Capacitors - parallel connected 26.11.2iii - Transformers

26.14

Appendix: Laminated bus bar design

1228

26.15

Appendix: Insulating material for between bus bar conductors

1231

26.16

Appendix: Materials by types of magnetization

1231

1235

Hard Magnetic Materials - Permanent Magnets

26.4.5 Temperature effects on core characteristics 26.4.6 Inductance stability 26.4.6i - Parameter effects 26.4.6ii - Time effects 1190

26.4.6iii - Temperature effects

Example 26.2: Temperature effect on inductance 26.4.7 Stored energy in inductors

1211

27

26.4.4i - Core losses at low H 26.4.4ii - Core losses at high H

Example 26.1: Inductance variation with time

1205

26.11.1 Reduction in wiring residual inductance 26.11.2 Reduction in component residual inductance

26.3

-

1201

1217

26.2.2 Ferrimagnetic materials- soft ferrites

26.4.2i 26.4.2ii 26.4.2iii 26.4.2iv 26.4.2v

1201

Auto-transformers

Example 26.8: Wound strip air core inductor Example 26.9: Multi-layer air core inductor

26.2.1 Ferromagnetic materials

1197

26.7

26.1.1 Inductors 26.1.2 Transformers or magnetically coupled circuits 26.2

1194

Power ferrite transformer design 26.6.1 Ferrite voltage transformer design Example 26.6: Ferrite voltage transformer design 26.6.2 Ferrite current transformer 26.6.3 Current transformer design requirements 26.6.4 Current transformer design procedure Example 26.7: Ferrite current transformer design 26.6.5 Current measurement: closed loop ferrite transformer 26.6.6 Current measurement: Rogowski Coil

1172

Soft Magnetic Materials - Inductors and Transformers

1192

26.5.1i - Core temperature and size considerations

Fusible resistors Circuit breaker resistors Temperature sensing resistors Current sense resistors Thermistors Other specialised resistors

25.8

Ferrite inductor and choke design, when carrying dc current 26.5.1 Linear inductors and chokes Example 26.3: Inductor design with Hanna curves

1164

Special function power resistors 25.7.1 25.7.2 25.7.3 25.7.4 25.7.5 25.7.6

26.5 1163

xxvi

1190

27.1

Magnetic properties

1239

27.2

Classification of magnetic materials

1240

27.2.1 Alloys 27.2.2 Ceramics 27.2.3 Bonded

Power Electronics

xxvii

Power Electronics

27.2.4 Flexible (rubber)

28.7

DC power switching

1308

The physics of vacuum high-voltage relays

1312

Gas filled relays

1313

27.3

Properties of hard magnetic materials

1253

28.8

27.4

Permanent Magnet Magnetization Curve (hysteresis loop) and recoil 1258

28.9

27.5

Permanent Magnet model

1260

27.6

Load lines

1263

27.6.1 Magnetic Circuit Equations 27.6.2 Intrinsic permeance coefficient Example 27.1: Magnet load dependant operating point 27.6.3 Demagnetizing field

xxviii

28.9.1 SF6 as a dielectric 28.9.2 Hydrogen as a dielectric

1267

28.10

High voltage relay designs

1314

28.11

Contact ratings

1317

28.12

High voltage relay grounding

1318

28.13

A LV voltage, 750V dc, high-current, 350A dc, make and break relay 1320

28.14

X-ray emissions in vacuum relays

1321 1321

27.7

Generalising equivalent magnetic circuits

1272

27.8

Permanent magnet stability - Loss of magnetism

1274

28.15

Power reconstitution conservation method

27.9

Recoil operation and associated losses

1277

28.16

MV AC vacuum Interrupts for contactor, switch, and circuit-breaker application 1323 28.16.1 Basic Interruption Principle 28.16.2 Medium-Voltage AC Vacuum circuit breaker characteristics 28.16.3 Altitude derating Example 28.2: Vacuum circuit breaker altitude properties 1330

27.9.1 Losses due to reverse magnetic fields 27.9.2 Demagnetisation due to temperature increase Example 27.2: Magnet load and temperature dependant operating point 1281 27.10

Energy transfer

1283

27.11

Force of attraction within an air gap

1286

27.12

Appendix: Magnet processing and properties

1287

27.13

Appendix: Magnetic Basics

1289

27.14

Appendix: Magnetic properties for Sintered NdFeB and SmCo Magnets 1289

27.15

Appendix: Magnetic Axioms

1291

28 1293

Contactors and relays 28.1 28.2

Mechanical requirements for relay operation

1293

Relay Contacts

1294

28.17

Corona

1331

28.19

Appendix: Contact metals

1333

Nomenclature and symbols

1335

Degrees of protection IP codes according to IEC 60529 standard

1350

IEC 947 and IEC 947-3 Standards Selecting contactors according to IEC 947-3 standard

1351

Glossary of terms

1352

Glossary of Wafer Processing terminology Glossary of Fuselink terminology (Fuseology) Glossary of Relay terminology Glossary of Varistor terminology Glossary of PTC and NTC Thermistor terminology Glossary of Electrochemical Battery terminology Glossary of Fuel Cell terminology Glossary of Solar Electric terminology Glossary of Capacitor terminology Glossary of Thermoelectric terminology Glossary of Fan Cooling and other Heating and Cooling terminology Glossary of Magnetic terminology

28.2.1 Contact characteristics 28.2.2 Contact materials 28.2.3 Contact life – material loss and transfer 28.3

Defining relay performance

1298

28.4

AC and DC relay coils

1300

28.5

Temperature consideration of the coils in dc relays

1301

Example 28.1: Relay coil thermal properties 28.6

Relay voltage transient suppression

1302

1303

28.6.1 Types of transient suppression utilized with dc relay coils 28.6.2 Relay contact arc suppression protection with dc power switching relays

1352 1356 1360 1370 1371 1374 1379 1382 1388 1392 1395 1402

Bibliography

1413

Physical constants

1424

INDEX

1425

Power Electronics

xxix

PREFACE

The book is in four parts. Part 1 covers power semiconductor switching devices, their static and dynamic electrical and thermal characteristics and properties. Part 2 describes device driving and protection, while Part 3 presents a number of generic applications. The final part, Part 4, introduces capacitors, magnetic components, resistors, and dc relays and their characteristics relevant to power electronic applications. 1 2 3 4 5

Basic Semiconductor Physics and Technology The pn Junction Power Switching Devices and their Static Electrical Characteristics Electrical Ratings and Characteristics of Power Semiconductor Switching Devices Cooling of Power Switching Semiconductor Devices

6 7 8 9 10

Load, Switch, and Commutation Considerations Driving Transistors and Thyristors Protecting Diodes, Transistors, and Thyristors Switching-aid Circuits with Energy Recovery Series and Parallel Device Operation, Protection, and Interference

11 12 13 14 15 16 17 18 19 20 21 22 23

Naturally Commutating AC to DC Converters – Uncontrolled Rectifiers Naturally Commutating AC to DC Converters – Controlled Rectifiers AC Voltage Regulators DC Choppers DC to AC Inverters – Switched Mode DC to AC Inverters – Resonant Mode DC to DC Converters - Switched-mode DC to DC Converters - Resonant-mode HV Direct-Current Transmission FACTS Devices and Custom Controllers Inverter Grid Connection for Embedded Generation Energy Sources and Storage: Primary Sources Energy Sources and Storage: Secondary Sources

24 25 26 27 28

Capacitors Resistors Soft Magnetic Materials: Inductors and Transformers Hard Magnetic Materials: Permanent Mmagnets Contactors and Relays

The 156 non-trivial worked examples cover the key issues in power electronics.

BWW April 2010

Chapter 1

2


Electrons in n-type silicon and holes in p-type are called majority carriers, while holes in n-type and electrons in p-type are called minority carriers. In a given silicon material, at equilibrium, the product of the majority and minority carrier concentration is a constant: po × no = ni2 (1.1) where po and no are the hole and electron equilibrium carrier concentrations.

CHAPTER

1


The majority of power electronic circuits utilise power semiconductor switching devices which ideally present infinite resistance when off, zero resistance when on, and switch instantaneously between those two states. It is necessary for the power electronics engineer to have a general appreciation of the semiconductor physics aspects applicable to power switching devices so as to be able to understand the vocabulary and the non-ideal device electrical phenomena. To this end, it is only necessary to attempt a qualitative description of switching devices and the relation between their geometry, material parameters, and physical operating mechanisms. Typical power switching devices such as diodes, thyristors, and transistors are based on a monocrystalline group IV silicon semiconductor structure or a group IV polytype, silicon carbide. These semiconductor materials are distinguished by having a specific electrical conductivity, σ, somewhere between that of good conductors (>1020 free electron density) and that of good insulators (> p in the n-type silicon 1 = ρ=

q µn n

)

1 = 0.086Ωcm 1.6 × 10−19 × 720 × 1017

3

Power Electronics

For a length of 100µm, the resistance is

Length L 100 × 10−4 R =ρ× =ρ× = 0.086 × = 8.6kΩ Area w ×t 10 × 10−4 × 1 × 10−4 From equation (1.5) the sheet resistance is given by W 10 × 10−4 Rs = R = 8.6kΩ × = 860 Ω/square L 100 × 10−4 If the length is assumed to be one of the shorter dimensions, then for a length 10µm or 1µm, the resistance is 86Ω or 0.86Ω, respectively, while the sheet resistance possibilities, depending on the thickness reference axis, are 86 Ω/square and 8.6 Ω/square. For a p-type material, the 40% decrease in mobility of holes µp increases resistivity by a factor of 1/0.4 = 2.5. Each aspect resistance therefore increases by a factor 2.5, viz., increases to 21.5kΩ, 215Ω, and 2.15Ω for lengths 100µm, 10µm, and 1µm, respectively. From equation (1.4) the sheet resistances are increased to 2.15kΩ/square, 215Ω/square, and 21.5Ω/square.

Chapter 1


1.1

Processes forming and involved in forming semiconductor devices

1.1.1

Alloying

At the desired region on an n-type wafer, a small amount of p-type impurity is deposited. The wafer is then heated in an inert atmosphere and a thin film of melt forms on the interface. On gradual, slow cooling, a continuous crystalline structure results, having a step or abrupt pn junction as shown in figure 1.2. This process is not employed to form modern p-n junctions but can be used at the metallisation stage of wafer fabrication.

step junction

♣

The carrier concentration equilibrium can be significantly changed by irradiation by photons, the application of an electric field or by heat. Such carrier injection mechanisms create excess carriers. If n-type silicon is irradiated by photons with enough energy to ionise the valence electrons, electronhole pairs are generated. There is already an abundance of majority electrons in the n-type silicon, thus the photon-generated excess minority holes are of more relative and detectable importance. If the light source is removed, the time constant associated with recombination, or decay of excess minority carriers, is called the minority carrier hole lifetime, τh. For a p-type silicon, exposed to light, excess minority electrons are generated and after the source is removed, decay at a rate called the minority carrier electron lifetime, τe. The minority carrier lifetime is often called the recombination lifetime. A difficulty faced by manufacturers of high-voltage, large-area semiconductor devices is that of obtaining uniformity of n-type phosphorus doping throughout the usual high-resistivity silicon starting material. Normal crystal growing (by liquid encapsulated, contactless, Czochralski crystal growth – see section 1.19.3i) and doping techniques give no better than ±10 per cent fluctuation around the wanted resistivity at the required low concentration levels ( 10cm

Czochralski, float-zone

multicrystalline silicon

mc-Si

1mm-10cm

Cast, sheet, ribbon

polycrystalline silicon

pc-Si

< 1mm-1mm

Chemical-vapour deposition

microcrystalline silicon

µc-Si

< 1mm

Plasma deposition

molten silicon

single crystal Si

heating coil elements

T > 1420°C

furnace crucible graphite with fused silica liner

back-filled inert gas 82% argon (a)

1.19.3 Single crystal silicon Several different processes can be used to grow an ingot or boule of single or mono-crystal silicon. The most established and dependable processes are the Czochralski method and the float-zone technique. The ribbon-growth technique is used for lower cost and quality silicon crystal growth. 1.19.3i Czochralski process The most commonly used process for creating the boule is called the Czochralski method, as illustrated in figure 1.22a. Electronic grade polysilicon silicon is heated in a quartz crucible to 1400°C in an argon atmosphere, using RF or resistance heating. A starter seed of single-crystal silicon on a puller contacts the top surface of molten polycrystalline silicon at 1415°C to 1420°C. As the seed crystal is slowly withdrawn - pulled and rotated, if the temperature gradient of the melt is adjusted so that the melting/freezing temperature is just at the seed-melt interface, atoms of the molten silicon solidify in the pattern of the seed and extend its single-crystal structure, forming a cylindrical boule of near perfect, pure silicon. • The ingot pull is unusually pure, because impurities either burn or tend to be drawn into the liquid silicon. An argon atmosphere precludes any oxygen impurity. The rod and crucible are rotated in opposite directions to minimise the effects of convection in the melt. The pull-rate (1µm to 1mm/s), the rotation-rate (10 to 40 turns per minute), and the temperature gradient are carefully optimised for a particular wafer diameter (up to 30mm) and lattice structure orientation growth direction (direction , along the diagonal of the sides of the cube crystal structure, for bipolar devices). Lengths of boule of several metres are attainable. • A small amount of boron (or phosphorous) is usually added during the Czochralski process to pre-dope the substrate silicon. 1.19.3ii Float-zone process The float-zone process produces purer crystals than the Czochralski method, because the pull is not contaminated by the crucible used in growing Czochralski crystals. In the float-zone process, as illustrated in figure 1.22b, a polycrystalline silicon rod is set atop a seed mono-crystal and then

melt

mono-Si boule

initial crystal seed

vacuum or inert gas 82% argon

(b)

Figure 1.22. Techniques for producing a single crystal silicon boule: (a) Czochralski method and (b) the float-zone method.

Wafer preparation The next step is the same for both single-crystal formation methods. The boule ends are cropped using a water-lubricated, single-blade diamond saw. The ingot is then ground to a uniform diameter in a lathe, and each end is bevelled with a sand belt to reduce the possibility of shattering the ingot. X-ray diffraction can then be used to determine the crystal structure orientation, which is marked by grinding the length of the cylindrical side of the boule. The cylindrical single-crystal ingot is sawed, using a multi-blade, inner-diameter saw in conjunction with a wet lubricant, into thin wafers for further processing. The sawing wastes 20% to 50% of the silicon as sawdust, known as kerf. The sliced wafers are mechanically lapped under pressure using a counter-rotating machine to achieve flatness and parallelism on both wafer sides. Most lapping operations use slurries of either aluminium oxide or silicon carbide. The edges of the individual wafers are also rounded by wet automatic grinders. After lapping, the wafers are etched with a solution containing nitric, acetic, and hydrofluoric acids (HF, CH3C00H, and HN03). This etching process removes external surface damage and reduces the thickness of the wafer. Next, the wafers are polished using an aqueous mixture of colloidal silica and sodium hydroxide. The wafers are mounted onto a metal carrier plate that is attached by vacuum to the polishing machine. The chemical polishing process usually involves two or three grinding and polishing steps with progressively finer slurry, which decreases wafer thickness and results in a mirror-like lustre finish. Sometimes carrier pads must be stripped from the metal carrier plates. The pads are usually stripped with solvents such as methylene chloride, methyl ethyl ketone, or a glycol ether mixture. Finally, the wafers are cleaned to remove any particles or residue remaining on the exterior surface of the polished wafer. Various cleaning steps and solutions containing ammonia, hydrogen peroxide, hydrofluoric acid, hydrochloric acid (NH3, H202, HF, and HCℓ), and deionised water may be used. The finished wafers are inspected and packaged for shipping, since most semiconductor manufacturers purchase wafers from specialist wafer producers.

47

Power Electronics

1.19.3iii Ribbon silicon Although single-crystal silicon technology is well developed, the Czochralski and float-zone processes are complex and expensive, as are the ingot-casting processes discussed under multi-crystalline silicon. Another crystal-producing process is ribbon silicon growth, where the single crystals cost less than from other processes, because they form the silicon directly into thin, usable wafers of single-crystal silicon. By forming thin crystalline sheets directly, sawing and slicing steps of cylindrical boules are avoided. One ribbon growth technique, termed edge-defined film-fed growth, starts with two crystal seeds that grow and capture a sheet of material between them as they are pulled from a source of molten silicon. A frame entrains a thin sheet of material when drawn from a melt. This technique does not waste much material, but the quality of the material is not as high as Czochralski process and float zone produced silicon. The resultant silicon quality is inferior for large-area, high-voltage, power semiconductor switching devices. 1.19.4 Multi-crystalline Silicon Multi-crystalline (or poly-crystalline) silicon describes when the active portion of the silicon is made up of several relatively large crystals, called grains, up to a square centimetre or so in area. Having several large crystals in a cell introduces a problem. Charge carriers can move around relatively freely within one crystal, but at the interface between two crystals, called the grain boundary, the atomic order is disrupted. Free electrons and holes are much more likely to recombine at grain boundaries than within a single crystal. There are several ways to minimize the problems caused by grain boundaries: • adjusting growth conditions through treatments such as annealing (heating followed by a slow cooling rate stage) the semiconductor material so that grains are columnar and as large as possible. The impurities are also better distributed; • designing cells so that the charge carriers are generated within or close to the built-in electric field; and • filling broken bonds at grain edges with elements such as hydrogen or oxygen, which is called passivating the grain boundaries. Multi-crystalline silicon based devices are generally less efficient than those made of single-crystal silicon, but they can be less expensive to produce. Multi-crystalline silicon is produced in a variety of ways. • The most common commercial methods involve a casting process in which molten silicon is directly cast into a mould and allowed to slowly solidify into an ingot. The starting material can be a refined lower-grade silicon, rather that the higher-grade semiconductor grade required for single-crystal material. The mould is usually square, producing an ingot that can be cut and sliced into square cells, minimising wasted silicon. • The procedure of extracting pure multi or poly-crystalline silicon from tri-chlorine-silane can be (among others) performed in special furnaces. Furnaces are heated by electric current, which flows through (in most cases) silicon electrodes. The 2m long electrodes measure 8mm in diameter. The current flowing through electrodes can reach up to 6000A. The furnace walls are additionally cooled preventing the formation of any unwanted reactions due to gas side products. The procedure results in pure polycrystalline silicon used as a raw material for solar cell production. Poly-crystalline silicon can be extracted from silicon by heating it up to 1500°C and then cooling it down to 1412°C, which is just above solidification of the material. The cooling is accompanied by origination of an ingot of fibrous-structured poly-crystalline silicon of dimensions 40x40x30 cm. The structure of poly-crystalline silicon in part of the material is settled, yet it is not adjusted to the structure of the other part. 1.19.5 Amorphous Silicon Amorphous silicon is produced in high frequency furnaces in a partial vacuum atmosphere. In the presence of a high frequency electrical field, gases like silane, B2H6 or PH3 are blown through the furnaces, supplying the silicon deposit with boron and phosphorus. Amorphous solids, like common glass, are materials whose atoms are not arranged in any particular order. They do not form crystalline structures, and they contain large numbers of structural and bonding defects. Economic advantages are that it can be produced at lower temperatures and can be deposited on low-cost substrates such as plastic, glass, and metal. These characteristics make amorphous silicon the leading thin-film material.

Chapter 1


48

Since amorphous silicon does not have the structural uniformity of single or multi crystalline silicon, small structural deviations in the material result in defects such as dangling bonds, where atoms lack a neighbour to which they can bond. These defects provide sites for electrons to recombine with holes, rather than contributing to the electrical circuit. Ordinarily, this kind of material would be unacceptable for electronic devices, because defects limit the flow of current. However, amorphous silicon can be deposited so that it contains a small amount of hydrogen, 5% to 10%, in a process called hydrogenation. The result is that the hydrogen atoms combine chemically with many of the dangling bonds, as shown in figure 1.23, essentially neutralising or removing them and permitting electrons to move through the material. Staebler-Wronski Effect Instability currently retards amorphous silicon exploitation in some semiconductor applications. In the case of photo-voltaic cells, the amorphous cells experience an electrical output decreases over a period of time when first exposed to sunlight. The electrical output stabilizes with a net output loss of 20%. The reason is related to the amorphous hydrogenated nature of the material, including tiny microvoids or atomic-level gaps in the amorphous silicon structure several angstroms in diameter (1 angstrom =10-10 m). Other causes include oxygen or carbon impurities that are in the cells and ordinary stresses in the system that break silicon-silicon bonds in the region of the imperfections. hydrogen atom dangling bond silicon atoms

Figure 1.23. Amorphous silicon showing the dangling bonds and hydrogen sites.

Devices suffering from light induced degradation can recover their effectiveness if they are annealed at 150°C for a few minutes. Annealing is also effective at the normal operating temperatures of silicon, about 50° to 80°C. This is called self-annealing.

Summary of substrate structural features Monocrystalline: An inorganic or organic compound functions in a device in a single crystal form (monocrystal). Only small molecules/oligomers (finite monomers) can be used. • Advantages: high reproducibility of properties, very high conductivity and carrier mobility. • Drawbacks: complexity of fabrication of devices, low mechanical strength. Polycrystalline: An inorganic or organic compound functions in a device in a form of a film/layer/bulk of many microscopic crystals. Both small molecules and low molecular weight polymers can be used. • Advantages: good reproducibility of properties, high conductivity and mobility. • Drawbacks: poor luminescent/optoelectronic properties. Microcrystalline: composed of micrometre-size well-shaped crystals/lamellas (thin plates or layers). Nanocrystalline: composed of nanometre-size crystals, often featured in shape (porous, hollow, etc). Small-molecule amorphous solids: • Advantages: simple fabrication of devices, good reproducibility of properties, good luminescent/ optoelectronic properties. • Drawbacks: low thermal stability (glass transition). Amorphous polymers: • Advantages: simple fabrication of devices, high mechanical and thermal stability, good luminescent/ optoelectronic properties. • Drawbacks: low reproducibility of properties, low conductivity and carrier mobility.

49

1.20

Power Electronics

Si and SiC physical and electrical properties compared

The processing of silicon is a mature, cost efficient technology, with 300mm wafers and submicron resolution common within the microelectronics industry. So-called wide bandgap semiconductors like silicon carbide (processed on 100mm wafers) offer promising high voltage and temperature power switching device possibilities as material quality and process yields improve. Figure 1.23 shows and allows comparison of the key physical and electrical properties of the main semiconductor materials applicable to power switching device fabrication. The higher • the energy bandgap, Eg, the higher the possible operating temperature before intrinsic conduction mechanisms produce adverse effects; • the avalanche breakdown electric field, ξb, the higher the possible rated voltage; • the thermal conductivity, λ, the more readily heat dissipated can be removed; and • the saturation electron drift velocity, νsat, and the electron mobility, µn, the faster possible switching speeds. Although the attributes of wide bandgap materials are evident, processing is more difficult than with Si and some of the parameters vary significantly with a wide operating (and processing) temperature range. SiC performance characteristic figures are slightly better than those for GaN, except, importantly, GaN has better carrier mobility. GaN growth is complicated by the fact that nitrogen tends to revert to the gaseous state, and therefore only thin layers are usually grown on sapphire or SiC substrates. Lattice-substrate boundary misfit occurs because of the significant difference in molecule sizes and packing. This limitation is more accentuated with GaN on silicon. There is a 17% misfit in molecule package and a 56% mismatch in thermal expansion (αGaN = 5.59×10-6 and αSi = 3.59×10-7 @ 300K). To prevent cracking during processing cooling, an intermediate transition layer like AℓN, is introduced. Wide band gap based, low-voltage (1800

2500

phase change

density

ρ

g / cm3

2.33

3.17-3.21

6.15

3.52

electrical resistivity

ρe

Ωm

10-3

1100

10-3

Reading list Streetman, B. G. and Banerjie, S. K., Solid State Electronic Devices, Prentice-Hall International, 6th Edition, 2005. Van Zeghbroeck, B., Principles of Semiconductor Devices, http://ece-www.colorado.edu/~bart/book/ Zetterling, C. M., Process technology for Silicon Carbide devices, IEE, 2002. http://www.siliconfareast.com/ http://www.semiconductorglossary.com/

Chapter 2

The pn Junction

52

One important feature of the pn junction is that current (holes) flows freely in the p to n direction when forward-biased, that is, the p-region is biased positive with respect to the n-region. Only a small leakage current flows in the reverse voltage bias case. This asymmetry makes the pn junction diode useful as a rectifier, exhibiting static voltage-current characteristics as illustrated in figure 2.2.

2

on

+ -

Vb

The pn Junction The diode is the simplest bipolar semiconductor device. It comprises p-type and n-type semiconductor materials brought together, usually after diffusion, to form a (step or abrupt) junction as shown in figures 2.1a and 2.2a. A depletion layer, or alternatively a space charge layer, scl, is built up at the junction as a result of diffusion caused by the large carrier concentration gradients. The holes diffuse from the p-side into the n-side while electrons diffuse from the n-side to the p-side, as shown in figure 2.1b. The n-side, losing electrons, is charged positively because of the net donor charge left behind, while the p-side conversely becomes negatively charged. An electric potential barrier, ξ, builds up, creating a drift current which opposes the diffusion flow, both of which balance at thermo-dynamic equilibrium as shown in figure 2.1c. The electric field is a maximum at the junction and zero at the scl edges. There are no free carriers in the scl. The zero external bias, built-in, junction potential or scl potential is given by

Φ =

kT j N N An A 2 D q ni

(V)

(2.1)

 −kTqV  I = I o  e − 1     j

+

off

-

Figure 2.2. Typical I-V static characteristics of a silicon pn junction diode, and the effects of junction temperature, Tj.

Example 2.1:

Built-in potential of an abrupt junction

A silicon abrupt p-n junction has a p-type region of 2x1016 cm-3 acceptors and an n-type region containing 2x1016 cm-3 acceptors in addition to 1017 cm-3 donors.

where q is the electron charge, 1.6 x 10 -19 C k is Boltzmann’s constant, 1.38 x 10-23 J/K Tj is the junction temperature, K. Thus Φ= k T j / q = 0.0259 eV at room temperature, 300 K.

Calculate i. the thermal equilibrium density of electrons and holes in the p-type region, and both densities in the n-type region ii. the built-in potential of the p-n junction at room temperature iii. the built-in potential of the p-n junction at 400K, assuming the intrinsic concentration increases 300 fold over that at 300K Solution i. The thermal equilibrium densities, using n i2 = p × n from chapter 1, are: in the p-type region p = N A = 2 × 1016 cm−3

(a)

n = ni

p

p = ni IDIFFUSION

Ф

Figure 2.1. The step junction: (a) the junction if carriers did not diffuse: + ionised donors, - ionised acceptors, + holes and - electrons; (b) electron and hole movements: ---- diffusion flow, ─── drift flow; (c) ionised impurities and free carriers equilibrium distribution; and (d) scl electric field and voltage.

BWW

(1.5 × 10 ) 10

2

xp

=

2

2 × 1016 cm3

= 1.125 × 103 cm−3

in the n-type region n = N D − N A = 8 × 1016 cm−3

IDRIFT

xn

(1.5 × 10 ) 10

2

Io

n

=

2

8 × 1016 cm3

= 2.813 × 103 cm−3

ii. The built-in potential at room temperature from equation (2.1) is   kT j p n 2 × 1016 × 8 × 1016  = 0.766V Φ = An n 2 p = 0.0259V × An  2 10   q ni  (1.5 × 10 )  iii. The intrinsic carrier density is temperature dependant, and increases to 300 x 1.5x1010 = 4.5x1012 at 400K.

Power Electronics

53

Chapter 2

2.2.1

The built-in potential at 400K is   kT p n 400K 2 × 1016 × 8 × 1016  × An  = 0.630V Φ = j An n 2 p = 0.0259V ×  ( 4.5 × 1012 )2  300K q ni 



♣

The pn Junction

Punch-through voltage

The reverse voltage extends the scl to at least one of the ohmic contacts and the device presents a short circuit to that voltage in excess of the punch-through voltage, VPT. Punch-through tends to occur at low temperatures with devices which employ a low concentration region (usually the n-side), as is usual with high-voltage devices. The punch-through voltage for silicon can be approximated by

VPT = 7.67 × 10 −16 Nc Wc 2 2.1

The pn junction under forward bias (steady-state)

where

If the p-region is externally positively-biased with respect to the n-region as shown in figure 2.3b, the scl narrows and current flows freely. The emf positive potential supplies holes to the p-region, while the negative emf potential provides electrons to the n-region. The carriers both combine, but are continuously replenished from the emf source. A large emf source current flows through the diode, which is termed forward-biased.

2.2

The pn junction under reverse bias (steady-state)

If a bias voltage is applied across the p and n regions as shown in figure 2.3c, with the p-terminal negative with respect to the n-terminal, then the scl widens. This is because electrons in the n-region are attracted to the positive external emf source while holes in the p-region are attracted to the negative emf potential. As the scl widens, the peak electric field ξm at the junction increases as shown in figure 2.3d. The only current that flows is the small leakage current which is due to carriers generated in the scl or minority carriers which diffuse to the junction and are collected. The junction condition is termed reverse-biased. Increasing applied reverse bias eventually leads to junction reverse voltage breakdown, Vb, as shown in figure 2.2 (third quadrant), and the diode current is controlled (limited) by the external circuit. Junction breakdown is due to one of three phenomena, depending on the doping levels of the regions and, most importantly, on the concentration of the lower doped side of the junction.

2.2.2

(V)

Avalanche breakdown

Avalanche breakdown or multiplication breakdown, is the most common mode of breakdown and occurs when the peak electric field, ξm, in the scl at the junction exceeds a certain level which is dependent on the doping level of the lighter doped region. Minority carriers associated with the leakage current are accelerated to kinetic energies high enough for them to ionise silicon atoms on collision, thereby creating a new hole-electron pair. These are accelerated in opposite directions, because of the high electric field strength, colliding and ionising repeatedly - hence the term avalanche, impact ionisation or carrier multiplication. If the lighter doped silicon region has a concentration of 1013 < N c < 5 × 1014

( /cc)

then the avalanche voltage may be approximated by

V b = 5.34 × 1013 N c - ¾

(V)

(2.3)

(V/m)

(2.4)

The peak electric field at the junction will be

ξb = 3.91 × 105 Nc 1 / 8

and the width of the scl, mainly in the lighter doped region, at breakdown is given by = 2.73 × 108 Nc -7 / 8

2.2.3 n

(2.2)

Nc is the concentration in /cc of the lighter doped region and Wc is the width of that region in µm.

Wscl = 2 Vb / ξb

p

54

(≈

1 × 10

−14

Vb

)

(m)

(2.5)

Zener breakdown

Field or Zener breakdown occurs with heavily doped junction regions and at usually less than 5V reverse bias. It occurs when the scl is too narrow for avalanche yet the electric field grows very large and electrons tunnel directly from the valence band on the p-side to the conduction band on the n-side. This reverse current is called the Zener effect. These three modes of reverse voltage breakdown are not necessarily destructive provided the current is uniformly distributed and limited by the external circuit. If the current density in a particular area is too high, a local hot spot may occur, leading to device thermal destruction. 2.3

Thermal effects

The pn junction current, I, shown in figure 2.2, is related to the scl voltage, v, according to

I (v ) = I o [e p

-q v / k Tj

- 1]

(A)

(2.6)

where Io is the reverse (saturation) leakage current in amps.

n

xp

xp

(d)

Figure 2.3. Diagrammatic representation of a pn junction diode showing minority carrier flow: (a) without external applied voltage; (b) with forward applied voltage; (c) with reverse applied voltage; and (d) electric field and scl change with increased reverse applied voltage.

The forward conduction voltage decreases with increased junction temperature, Tj. That is, the on-state voltage has a negative temperature coefficient. In practical silicon pn diodes, at low currents, the temperature coefficient is typically -2.4 mV/K, becoming less negative with increased current. At higher currents, the coefficient becomes positive because of the reduced carrier mobility at higher temperatures, which causes non-scl regions to increase in resistance. The effects of the change in temperature coefficient at higher currents, in practical devices, are shown dotted in figure 2.2. Neglecting the exponential silicon bad gap temperature dependence, the temperature effects at high current, on the diffusion constant component of the leakage current Io in equation (2.6), called the saturation current, is given by 1.8

 T    300 

I o (T ) = I o (25°C) × 

(2.7)

Power Electronics

55

Chapter 2

The pn Junction

56

Silicon carbide diodes have a higher temperature coefficient, typically +8mV/K. The avalanche voltage increases with temperature, as does the reverse leakage current. The effects of temperature on the reverse bias characteristics are shown in figure 2.2. In the case of silicon carbide, increased temperature decreases the avalanche voltage and increases the leakage current. The silicon temperature coefficient for avalanche is positive since the mean distance between collisions is reduced due to the increased thermal energy, which increases the vibrational amplitude. Higher electric fields are necessary for the carriers to gain sufficient kinetic energy for ionisation. Equation (2.6) also indicates that the reverse bias current increases with increased junction temperature. This positive temperature coefficient does not generally result in thermal instability with silicon devices, provided sufficient heat sinking is employed on smaller devices. Example 2.2:

Diode forward bias characteristics

A pn junction diode has a reverse saturation current of 100nA at a junction operating temperature of 28°C. What is the forward current when the forward bias voltage is 0.5V and the dynamic ac resistance at that current? Solution The diode current is given by equation (2.6), namely

I (v ) = I o [e

-q v / k Tj

- 1] (A) where VT = q/kTj = 0.0259V at 300K, 28°C. I (0.5V) = 100 × 10−9 × [e v / 0.0259 - 1] = 26.1A Differentiating the diode V-I equation with respect to voltage gives

I di = oe dv VT

VF VT

=

1

Rac

0.5V 100 × 10 −9 A × e 0.0258 V 0.0258V ⇒ Rac = 1.0mΩ

Figure 2.4. Piecewise-linear approximations of junction diode characteristics: (a) ideal diode with an offset voltage and resistance to account for slope in the forward characteristic and (b) model including reverse bias characteristics.

=

Example 2.3: ♣

Using the pwl junction diode model

An approximation to the forward I-V characteristic of the diode shown in figure 2.4a, is given by VF ( I ) = 1.0 + 0.01 I F . For a constant current of 45A for ⅔ of a cycle, calculate the diode i. on-state voltage; ii. mean power loss; and iii. rms current. F

2.4

Models for the bipolar junction diode

Semiconductor device electrical models are used extensively for power electronic circuit simulation. A basic piecewise-linear model is applicable to simple manual calculations, where the terminal I-V characteristics are empirically modelled based on ideal circuit elements. A more complex and accurate model is required for computer transient circuit analysis simulation. Such accurate models are based on the semiconductor physics of the device. Many power switching semiconductor device manufacturers provide values for the model parameters suitable for circuit simulation in the packages PSpice and SABER. 2.4.1

Piecewise-linear junction diode model

The pn junction diode is a unilateral device that, to a good approximation, conducts current in only one direction. Figure 2.4a shows a piecewise-linear (pwl) model of the diode that is suitable for static modelling in power electronic circuits. It includes a perfect diode, an on-state voltage source Eo, and a series resistor of resistance value Ro to account for the slope in the actual forward conduction characteristic. The forward I-V characteristic at a given temperature is given by VF ( I F ) = E0 + IF R0 for VF > E0 (V) (2.8) The model in figure 2.4a does not incorporate the static reverse characteristics of leakage and avalanche. These are shown in figure 2.4b, where Vb from equation (2.3) models the avalanche limit and Ri ( = Vb / I o ) gives linear leakage current properties for a given junction temperature. The three diode components in figure 2.4b are assumed ideal. The model given by equation (2.8) is adequate for calculation of static balancing requirements of parallel and series connected diodes and thyristors, as considered in section 10.1 and the associated problems, 10.4, 10.5, and 10.9 to 10.12.

Solution i. ii.

The on-state voltage at 45A is given by VF (45A) = 1.0 + I F 0.01 = 1.0V + 45A × 0.01Ω = 1.45V If the on-state duty cycle is δ = ⅔, the average power loss is

iii.

P = δ × VF × I F = ×1.45V × 45A = 43.2W The diode rms current is given by

−

I rms = δ × I dc =  × 45A = 36.7A

♣ Example 2.4:

Static linear diode model

A Schottky diode is used to half-wave rectify a square wave ±15V source in series with a 1Ω load resistor. If the diode model shown in figure 2.4b is modelled with Ro = 0.01 Ω, Eo = 0.2V, Ri = 1000Ω, and Vb = 30V, determine: i. the diode model forward and reverse bias operating point equations for the series circuit ii. the load current and diode voltage iii. the rectifier losses (neglecting any recovery effects) and the load power dissipation iv. estimate the power dissipated in the load if the source is ac with the same fundamental component as the square wave v. what is the non-fundamental power dissipated with the square wave source?

Power Electronics

57

Chapter 2

Solution When the diode is forward biased 1 iF = ( vDF − Eo ) for vDF ≥ 0.2V Ro Kirchhoff’s voltage law for the series circuit gives Vs = iF RL + vD F Eliminating the diode voltage vDF gives the series circuit current V − Eo iF = s Vs ≥ Eo for Ro + RL

IF

i.

V DF

IR V DR Ri =1000Ω

E o =0.2V

for 0 < Vs < Eo iF = 0 The diode forward voltage is therefore given by R L =1Ω V R + Eo RL vDF = s o = Eo + iF Ro for i > 0 Ro + RL When the diode is reversed biased, below the reverse breakdown voltage Vb = 30V 1 iR = vDR for vDR < Vb Ri

Vs = iR RL + vDR Eliminating the diode voltage vDR gives the series circuit leakage current Vs iR = Ri + RL The diode reverse voltage is thus given by VR vDR = s i = iR Ri Ri + RL

ii.

rms

.

rms

= ( 9.352 + 0.00952 ) × 1Ω = 87.42W + 90µW = 87.42W VL

Clearly, if RL > Ro, the diode forward current equation can be simplified using Ro = 0. When the diode is reverse biased 15V = 15.0mA iR = 1000Ω + 1Ω VD = 15mA×1000Ω = 15.0V R

If Ri >> RL the diode reverse current and voltage equations can be simplified using RL = 0. iii.

The rectifier losses are, when forward biased, Pd = v D × iF F

F

= 0.35V × 14.65A = 5.127W and when reverse biased Pd = vD × iR R

58

The rms of a sine is 1/√2 its magnitude and 1/√2 again for a half-wave rectified sine. That is 18.7A iFrms = = 9.35A rms 2 2 The reverse leakage current is given by 19.1V iR = × sin ωt = 0.019 × sin ωt 1000Ω + 1Ω which gives an rms current of 19mA iRrms = = 9.5mA rms 2 2 The power dissipated in the 1Ω load resistor is PL = ( iF2 + iR2 ) × RL .

Ro =0.01Ω

V=±15V

The pn Junction

qA Dp ni2 Io ≈ wn N D

 V −m for V ≤ η Φ else  C jo (1 − Φ )  C j (V) =  (1 − η (1 + m ) + mΦV )   C jo (1 − η ) − (1+ m )  C t (V) = tt

Cj+Ct V / γϕ

I(V) = Io (e

− 1)

I b (V) = IV e− (V +V ) /ϕ b

dI dV

I+Ib

b

ϕ = kT /q cathode

Figure 2.5. PSpice transient analysis circuit model of the pn junction diode.

R

=15V × 15mA = 0.225W Total diode losses for a square wave are therefore ½×(5.127W + 0.225W) = 2.68W. The power from the square wave supply is ½× (15V×14.65A + 15V×15mA ) = 110.0 W

with 110W – 2.68W = 107.32W dissipated in the 1Ω load resistor. iv. The magnitude of the fundamental of a square wave is 4/π times the square wave magnitude, that is, 15V×4/π = 19.1V peak. The forward biased diode does not conduct until the supply voltage exceeds 0.2V. This is a small percentage of the sine wave magnitude (≈1%), hence can be neglected in the loss estimate. The forward current flow is approximately 19.1V - 0.2V iF = × sin ωt = 18.7 × sin ωt 1Ω + 0.01Ω

The ideal diode current I is given by equation (2.6). The diode current Ib models reverse voltage breakdown, where the breakdown voltage Vb is assumed due to avalanche and is given by equation (2.3). The voltage dependant transit capacitance, Ct, which is dominant under forward bias, is related to the minority carrier lifetime tt. The voltage dependant scl (depletion layer) capacitance Cj, which is dominant under reverse bias, involves the zero bias junction potential voltage Φ, given by equation (2.1) and the zero bias junction capacitance Cjo. In the case of the silicon carbide Schottky diode, Cj >> Ct. The scl capacitance, Cj (V) can be evaluated from the pn diode structure and doping profile, as follows. 2.4.2i - Determination of zero bias junction capacitance, Cjo Poisson’s equation, in conjunction with Gauss’s law, for the one dimensional step junction shown in figure 2.6, give d 2V dξ q ND qN =− = =− A (2.9) εs εs d x2 dx

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59

Chapter 2

The pn Junction

 2ε (Φ -V )  1 1 +  s  N q N  A D 

Wscl =

space charge layer

60

   

(2.14)

The scl width voltage dependence can be expressed in terms of the zero bias scl width, Wo Q

Qn=qAxnND

(cm-3)

Qn= -Qp

qND + xp xp

o

xn

ξ

Qp=-qAxpNA

(V/cm)

xn0 =

ξm

V = ∫ξ

Φ W0 1+ ND / N A

xn (V ) = xn0 1 -

o

 V  1 Φ  

(2.15)

V

= W0 1 -

qNA

qN x qN x ξm = − D n = − A p εs εs

 2ε Φ  1 1 +  s   q  NA ND

Wscl (V ) =

x p0 =

V Φ

W0 1+ NA / ND

x p (V ) = x p0 1 -

(2.16)

V Φ

The magnitude of the voltage dependant charge on each side of the junction is

(V)

1

Q(V ) = q A

o

= Wscl

 ND NA N N 2 V W = A  2 qε sΦ D A  1ND + NA ND + NA  Φ 

Q0 1-

(2.17)

V Φ

The junction capacitance is given by differentiation of equation (2.17) with respect to V 1

Figure 2.6. The charge Q, electric field ξ, and voltage potential V, in the space charge layer of a step pn junction.

The dielectric permittivity εs = εr εo comprises the free space permittivity εo = 8.854x10-12 F/m and the relative permittivity εr = 11.8 for silicon and 9.7 for SiC.  q ND for − xn < x < 0  d ξ ( x)  ε s (2.10) = dx − q N for 0 < x < xp  ε s A Integrating both parts of equation (2.10) over the shown bounds, gives ξ(x):  q  ε s ND x + ξ m for − xn < x < 0 dV( x)  = ξ ( x) =  dx  − q N x + ξ for 0 < x < xp m  ε s A q q where the maximium field intensity (at x = 0) is ξm = ε ND xn = NA xp

(2.11)

The electric field at the metallurgical junction, from equation (2.12) is given by V ξ j (V ) = ξ 0 1 where ξ 0 = 2Φ / W0 Φ

(2.20)

2.4.2ii - One-sided pn diode equations When NA >> ND, which is the usual case in high voltage pn diodes, equations (2.12) to (2.20) are approximated by the following one-sided diode equations.

εs

s

 ND NA  2 ε s A dQ q (2.18) = εs A   = dV W  2ε s (Φ -V) ND + NA  Equation (2.18) can be rearranged to give the PSpice capacitance form, in terms of the zero bias junction capacitance Cjo. Cjo Cj (V ) = 1  V 2 1 1 − Φ  (2.19)    q ND NA  2 ε s A where Cjo = ε s A   = W 2 ε Φ N N + o D A   s Cj =

The piece-wise parabolic voltage potential across the scl shown in figure 2.6, is given by integration of the electric field, that is 0 x q q V = ∫ ( ND x + ξ m ) dx + ∫ (− NA x + ξ m ) dx εs −x εs 0 (2.12) = ½ ξ m Wo Since the charges each side of the metallurgical junction must balance, equation (2.12) can be rearranged to give the scl width. p

W0 =

 2 εs Φ    ≈  q ND 

xno

and

x po ≈ 0

n

Wo =

 2ε V  s  q

 1 1  +   N N  D   A

(2.13)

From equation (2.1), a zero bias voltage Φ exists without the presence of any external voltage. Therefore, to incorporate non-equilibrium conditions, the electrostatic barrier potential becomes Φ-V, where V is the externally applied reverse bias voltage. Consequently the scl width expression becomes:

Q0 = A 2 qε sΦND Cjo = εs A

(2.21)

εs A q ND = 2ε s Φ Wo

These equations show that the scl penetrates mostly into the n-side, (hence the name one-sided), which supports most of the voltage, as shown in the last diagram in figure 2.6.

Power Electronics

61

Example 2.5:

Chapter 2

Space charge layer parameter values

iv.

The pn Junction

From equation (2.15) the scl width at -1000V reverse bias is

A 10µm thick p-type 2x1016 /cc silicon epitaxial layer is grown on an n- - type 1x1014 /cc silicon substrate, of area 1 cm2, to form an abrupt pn junction.

Wscl = W0 1-

Calculate the following PSpice parameter values, at room temperature: i. ii. iii.

scl width and penetration depth each side of the junction, W, xn, xp; charge each side of the junction, maximum electric field, and the capacitance, Q, ξj, Cj.

Solution i.

From equations (2.15), (2.20), (2.17), and (2.19) W0 =

 2Φ ε  1 1  s × +    q N N  D   A 

W0 =

2 × 0.53 V × 11.8 × 8.85 × 10  1.6 × 10−19 

xn = 114.0µm

x p = 0.57µm

Note that when NA >> ND, xn ≈ Wscl, thus the lower the relative concentration of ND, the deeper the scl penetration and the higher the portion of V supported in ND. The junction scl can under these circumstances be analysed based on simplified equations – called one-sided junction equations.

V Φ

= 0.40M × 1+

ξ j = 17.5 MV/m  1  1 × +  22 1× 1020  2 × 10

= 2.65µm

ξ 0 = 2 Φ / W = 2 × 0.534 / 2.65µm ξ 0 = 0.40 MV/m  ND NA  Qo = A  2Φqε s  ND + NA  

1000V 0.533V

From equation (2.16) the scl penetration into each side of the junction at -1000V is Wscl Wscl 114.6 114.6 xn = xp = = = 1 + ND / NA 1 + 0.005 1 + NA / ND 1 + 200

ξ j = ξ 0 1-

−12

= 2.65µ 1+

v. The charge magnitude each side of the junction, shown in figure 2.6, is given by equation (2.17). The electric field at the junction is given by equation (2.20), while the junction capacitance at -1000V is given by equation (2.19): 1000V V = 4.2nC × 1+ Q j = Q0 10.533V Φ = 182.4 nC

From equation (2.1), the zero bias built-in voltage is kT N N 2 × 1016 × 1× 1014 Φ = j An A 2 D = 0.0259 An q ni 2.25 × 1020

= 0.0259 × An(8.89 × 109 ) = 0.534V ii.

V Φ

= 114.6µm

zero bias junction potential, Φ; zero bias scl width, maximum electric field, charge, and junction capacitance, W0, ξ0, Qo, Cjo; and avalanche breakdown voltage, Vb.

If the substrate is 150µm thick, for a 1000V reverse bias, calculate: iv. v.

(>ND. Calculate the percentage error in using the assumptions. 2.6. A silicon pn diode with NA = 1018 cm-3 has a capacitance of 10-7 F/cm2 at an applied reverse voltage of 1V. Calculate the donor density ND. 2.7. A silicon pn diode has a maximum electric field magnitude of 107 V/cm and a scl width of 200µm. The acceptor concentration is 100 times the donor density. Calculate each doping density. 2.8. Repeat example 2.2 for the equivalent 4H silicon carbide junction diode having the same electrical operating conditions. Use the silicon carbide data given below.

See problems 10.4, 10.5, and 10.9 to 10.12. Useful SI data for silicon and silicon carbide: q = -1.6x10-19 C ξo = 8.85x10-12 F/m ξr Si = 11.8 ξr SiC = 9.7 kT/q = 0.0259 eV at 300K ni Si = 1.5x1016 m-3 ni SiC = 2.5x10-3 m-3

The pn Junction

64

Chapter 3

3 Power Switching Devices and their Static Electrical Characteristics

Power Switching Devices and their Static Electrical Characteristics

66

control bevelling on more complex junction structures is achieved with double-negative or doublepositive bevelling as shown in parts e and f of figure 3.1. The bevelling is accomplished by grinding, followed by etching of the bevel surface to restore the silicon crystalline mechanical and structure quality. The processed area is passivated with a thin layer of polyimide, which is covered in silicon rubber. Negative bevels tend to be more stable electrically with ageing. The foregoing discussion is directly applicable to the rectifier diode, but other considerations are also important if fast switching properties are required. The turn-on and reverse recovery time of a junction are minimised by reducing the amount of stored charge in the neutral regions and by minimising carrier lifetimes. Lifetime killing is achieved by adding gold or platinum, which is an efficient recombination centre. Electron and proton irradiation are preferred non-invasive lifetime control methods. Irradiation gives the lowest forward recovery voltage and the lowest reverse leakage current. The improved switching times must be traded off against increased leakage current and on-state voltage. Switching times are also improved by minimising the length (thickness) of the n-region.

cathode

anode cathode (a)

There is a vast proliferation of power switching semiconductor devices, each offering various features, attributes, and limitations. The principal device families of concern in the power switching semiconductor range are the diode, transistor, and thyristor. Each family category has numerous different members. The basic characteristics of the three families and a range of their members will be presented.

3.1

anode

anode

Power diodes n

The homojunction p-n diode is the simplest semiconductor device, comprising one pn junction. In attempts to improve both static and dynamic diode electrical properties for different application conditions, numerous diode types have evolved.

n+

+

cathode

cathode (c)

3.1.1

(d)

The pn fast-recovery diode

The doping concentration on each side of the junction influences the avalanche breakdown voltage, the contact potential, and the series resistance of the diode. The junction diode normally has the p-side highly doped compared with the n-side, and the lightly doped n-region determines many of the properties of the device. The n-region gives the device its high-voltage breakdown and under reverse bias, the scl penetrates deeply into the n-side. The lower the n-type concentration and the wider the nside, the higher will be the reverse voltage rating and also, the higher the forward resistance. These nregion requirements can lead to thermal I2R problems in silicon. Larger junction areas help reduce the thermal instability problem. It is usual to terminate the lightly doped n-region with a heavily doped n+ layer to simplify ohmic contact and to reduce the access resistance to the scl. For better n-region width control, n-type silicon is epitaxially grown on an n+ substrate. The p+ anode is diffused or implanted into the epitaxial region, forming an epitaxial diode. In devices specifically designed for high reverse bias applications, care must be taken to avoid premature breakdown across the edge of the die or where the junction surfaces. Premature edge breakdown is reduced by bevelling the edge as shown in figure 3.1a, or by diffusing a guard ring as shown in figure 3.1b, which isolates the junction from the edge of the wafer. The scl electric field is lower at the bevelled edge than it is in the main body of the device. In the case of a lightly doped p-type guard ring, the scl is wider in the p-ring, because of its lower concentration, than in the p+ region. The maximum electric field is therefore lower at the pn-ring junction for a given reverse bias voltage. Negatively charged glass film techniques are also employed to widen the scl near the surface, as shown in figures 3.1c and 3.1d. Multiple guard rings are sometimes employed for very high breakdown voltage devices. Similar techniques are extendable to devices other than diodes, such as thyristors. Field

BWW

(b)

(e)

(f)

Figure 3.1. To prevent edge breakdown under junction reverse bias: (a) reduction of the space charge region near the bevel; (b) p-type guard ring; (c) glass guard ring; (d) glass plus p-type guard ring; (e) double negative bevel; and (f) double positive bevel angle.

3.1.2

The p-i-n diode

The transient performance of diodes tends to deteriorate as the thickness of the silicon wafer is increased in attaining higher reverse voltage ratings. Gold lifetime killing only aggravates the adverse effects incurred with increased thickness. The p-i-n diode allows a much thinner wafer than its conventional pn counterpart, thus facilitating improved switching properties.

Power Electronics

67

Chapter 3


The p-i-n diode is a pn junction with a doping profile tailored so that an intrinsic layer, the i-region, is sandwiched between the p-layer and the n-layer, as shown in figure 3.2. In practice, the idealised iregion is approximated by a high resistivity n-layer referred to as a v-layer. Because of the low doping in the v-layer, the scl will penetrate deeply and most of the reverse bias potential will be supported across this region.

n

68

forward bias

i reverse bias

p.d. = area p.d. = area

Figure 3.3. Diodes: (a) static I-V characteristic; (b) symbol for a rectifier diode; (c) voltage reference or Zener diode; and (d) Schottky barrier diode. Figure 3.2. Cross-section and electric field distribution of: (a) a pn diode and (b) a p-i-n diode.

3.1.4

The power p-i-n diode can be fabricated by using either the epitaxial process or the diffusion of p and n-regions into a high-resistivity semiconductor substrate. The i-region width Wi , specifies the reverse voltage breakdown of the p-i-n diode, which is the area under the electric field in figure 3.2b, viz., Vb ≈ ξb W ≈ 25Wi

(in µm )

(V)

(3.1)

The thickness Wi , along with the distribution of any gold within it, determines the nature of the reverse and forward-conducting characteristics. These characteristics are more effective and efficient in fast p-in diodes than in the traditional pn structures.

3.1.3

The power Zener diode

Zener diodes are pn diodes used extensively as voltage reference sources and voltage clamps. The diode reverse breakdown voltage is used as the reference or clamping voltage level. The leakage current in a good pn diode remains small up to the reverse breakdown point where the characteristic has a sharp bend. Such an electrical characteristic is called hard. Premature breakdown at weak spots in the junction area or periphery cause high leakage currents before final breakdown, and such diodes are said to have soft breakdown characteristics. Zener diodes are especially made to operate in the breakdown range. Above a few volts, the breakdown mechanism is avalanche multiplication rather than Zener and the breakdown reference voltage VZ is obtained by proper selection of the pn junction doping levels. Once in breakdown VZ remains almost constant provided the manufacturer’s power rating, P = VZ I, is not exceeded. Where the breakdown mechanism is due to the Zener effect, the temperature coefficient is negative, about -0.1 per cent/K, changing to positive, +0.1 per cent/K, after about 4.5V when the avalanche multiplication mechanism predominates. Zener diodes require a hard breakdown characteristic not involving any local hot spots. They are available in a voltage range from a few volts to about 280V and with power dissipations ranging from 250mW to 75W, with heat sinking. Transient suppressing Zener diodes can absorb up to 50kW, provided energy limits and number of cycles are not exceeded, as shown in figure 10.21. Practically, Zener diodes are difficult to make, less than ideal in application, and should be avoided if possible. The basic I-V characteristics, and electrical circuit symbol for the different types of diodes, are shown in figure 3.3.

The Schottky barrier diode

The Schottky diode is a metal-semiconductor diode device which offers low on-state voltages, but in silicon is presently restricted to applications imposing a reverse bias of less than 400V. At lower voltages, less than 40V, devices of up to 300A are available and the maximum junction operating temperature is 175°C, which is higher than for conventional silicon pn junction devices. The Schottky diode is formed by a metal (such as chromium, platinum, tungsten or molybdenum) in homogeneous contact with a substrate piece of n-type silicon, as shown in figure 3.4a. The contact is characterised by a potential barrier Φb > 0 (termed Schottky barrier height) which determines the forward and reverse properties of the Schottky diode. In forward conduction, electrons are emitted from the negative potential n-type silicon to the positive potential metal, passing over the barrier potential. Unlike the bipolar pn diode, only electrons are carriers, hence the Schottky barrier diode is a unipolar device. The forward on-state voltage drop is dominated by and proportional to the barrier potential Φb, while unfortunately the reverse leakage current is approximately inversely related. Thus a Schottky diode with a very low forward voltage drop will have very high reverse leakage current relative to the pn diode counterpart, as shown in figure 3.5. Chromium provides the lowest forward voltage drop but is limited to an operating temperature of 125°C and has a high leakage current. Platinum allows operating temperatures to 175°C with a leakage current several orders of magnitude lower than chromium. The trade-off is a higher forward voltage. A guard ring is used to improve device robustness, but its function is to act like a Zener diode and thus protect the Schottky barrier under excessive reverse bias. An optimally designed epitaxial layer, as shown in figure 3.4b, is also employed which reduces the field at the less than perfect metalsemiconductor interface and allows the whole interface to go safely into reverse bias breakdown. There are a number of important differences between Schottky barrier and pn junction diodes. • In a pn diode, the reverse bias leakage current is the result of minority carriers diffusing into the scl and being swept across it. This current level is highly temperature-sensitive. In the Schottkybarrier case, reverse current is the result of majority carriers that overcome the barrier. A much higher leakage value results at room temperature, but is not temperature-dependent. • The forward current is mostly injected from the n-type semiconductor into the metal and very little excess minority charge is able to accumulate in the semiconductor. Since minimal minority carrier recombination occurs, the Schottky barrier diode is able to switch rapidly from forward conduction to reverse voltage blocking. • Since under forward bias, barrier injection comes only from the semiconductor, and there is little recombination in the scl; thus the device can be represented by the ideal diode equation (2.6). • The majority electrons injected over the barrier into the metal have much higher energy than the other metal electrons which are in thermal equilibrium. Those injected electrons are therefore called hot, and the diode in some applications is referred to as a hot electron diode.

Power Electronics

69

Chapter 3


70

An important point arising from this brief consideration of the Schottky barrier diode is the importance of the connection of an n-type semiconductor region to aluminium metallization that occurs in unipolar and bipolar semiconductor devices. A practical method of forming aluminium ohmic contacts on n-type materials where Φb > 0, is by doping the semiconductor very heavily (>1019 /cm3), above the degeneracy level. Thus, in the contact region, if a barrier exists, the scl width is small enough ( Vth and V gs −Vth > Vds > 0 , the drain current is given by

Id = µ

Wc C (V −VTH )Vds − ½ Vds2 Lc a gs

(3.9)

and when the gate voltage is below the threshold level, V gs < VTh ,

Id = 0

(3.10)

DRAIN

s

g d

Figure 3.11. Two designs for the n-channel MOSFET and its circuit symbol (courtesy of Infineon and International Rectifier).

The obtainable drain-to-source breakdown voltage is not limited by the gate geometry. The scl associated with voltage blocking penetrates mostly in the n-type epitaxial layer. Thickness and doping concentration of this layer are thus decisive in specifying the blocking capability of the power MOSFET. The basic drain current versus drain to source voltage static operating characteristics (and their temperature dependence) of the power MOSFET are illustrated in figure 3.10c. For a given gate voltage, there are two main operating regions on the drain current-voltage characteristic. • The first is a constant resistance region, where an increase in drain to source voltage results in a proportional increase in drain current. (In practice, the effective resistance increases at higher drain currents.) • At a certain drain current level, for a given gate voltage, a channel pinch-off effect occurs and the operating characteristic moves into a constant current region. 3.2.2ii - MOSFET drain current When the power MOSFET is used as a switch, it is controlled in the on-condition, such that it is forced to operate in the resistive region. This ensures that the voltage drop across the device is low so that the drain current is essentially defined by the load and the device power dissipation is minimal. Thus for switching applications, the on-resistance Rds(on) is an important characteristic because it will specify the on-state power loss for a given drain current. The lower Rds(on) is, the higher the current-handling capabilities of the device; thus Rds(on) is one important figure of merit of a power MOSFET. A quadratic MOSFET model allows the inversion layer charge between the source and the drain to vary. For power MOSFETs that have short channels, the drain current Id is related to the channel dimensions and the gate voltage Vgs according to at low current, above pinch-off Id = ½µ

Wc Lc

Ca (Vgs − VTh )2

(A)

(3.7)

if Vds ≥ Vgs − VTh > 0 for n-channel MOSFETs, as shown to the left of the pinch-off locus in figure 3.10c.

Figure 3.12. MOSFET gate voltage characteristics: (a) transfer characteristics of gate voltage versus drain current and (b) transconductance characteristics of gate voltage versus transconductance, gfs.

Figure 3.12a shows that drain current exhibits both a positive and negative temperature coefficient with the drain current IDQ being the boundary condition. If the drain current is greater than IDQ there is a possibility of destruction by over-current at low temperatures, while if the drain current is less than IDQ, over-current can produce thermal runaway and destruction. Operation with a gate voltage corresponding to IDQ avoids the need for any gate drive temperature compensation. At high gate voltages, the on-resistance of the resistive region and the drain current in the constant current region, become somewhat independent of the gate voltage. This phenomenon is best illustrated in the Id vs Vds characteristic by the curve cramping at high gate voltages in figure 3.10c. 3.2.2iii - MOSFET transconductance and output conductance Inspection of the static drain source characteristics of figure 3.10c reveals that as the gate voltage increases from zero, initially the drain current does not increase significantly. Only when a certain threshold gate voltage, VTh, has been reached, does the drain current start to increase noticeably. This is more clearly illustrated in figure 3.12b which shows the characteristics of drain current Id and small signal transconductance gfs versus gate voltage, at a fixed drain voltage. It will be seen from these characteristics that no conduction occurs until Vgs reaches the threshold level, VTh, after which the Id versus Vgs characteristic becomes linear, the slope being the transconductance gfs. The amplification factor, forward transconductance, gfs, is defined as g fs

(A)

(3.8)

Vds = constant

Differentiating equations (3.7) and (3.8), for Vds ≥ Vgs − VTh , with respect to gate voltage, gives at low current g fs = µ

at high current after electron velocity saturation, the quadratic model is invalid and I d = ½ vsat Wc Ca (Vgs − VT h )

∂I d ∂Vgs

Wc Lc

Ca (Vgs − VTh ) = 2

Wc µn Ca I Dn Lc

(mho)

(3.11)

at high current

g fs = ½ vsatWc Ca

(mho)

(3.12)

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Chapter 3

At high electric fields, that is high currents, the carrier velocity νsat saturates. In the ohmic region, V gs > 0 and V gs −Vth > Vds , the forward transconductance is

g fs = µ

Wc CV Lc a ds

The output conductance, gd, is defined as ∂I d gd ∂Vds

(3.13)

Differentiating equations (3.7) and (3.8), with respect to drain voltage, gives zero, gd = 0, for each case in the saturation region. In the ohmic region the output conductance is

gd = µ

Wc C (V −V −V ) Lc a gs Th ds

(3.14)

A typical minimum threshold voltage is about 2V and exhibits temperature dependence of approximately -10mV per K (α = 0.5 per cent/K), as shown in figure 3.13. At high gate voltages, the drain current becomes constant as the transconductance falls to zero, implying the upper limit of forward drain current. The temperature variation of transconductance is small, typically -0.2 per cent/K, which results in extremely stable switching characteristics. The typical temperature coefficient for the gain of a bipolar junction transistor, the MOSFET equivalent to gfs , is +0.8 per cent/K. The temperature dependence of the MOSFET forward conductance is approximated by

78

3.2.2v - MOSFET p-channel device P-channel MOSFETs are very similar to n-channel devices except that the n and p regions are interchanged. In p-channel devices the on-resistance, for a given die area, will be approximately twice that of a comparable n-channel device. The reason for this is that in the n-channel device the majority carriers are electrons but in the p-channel device, the majority carriers are holes which have lower mobility. If the area of a p-channel device is increased to produce an equal Rds(on), then the various capacitances of the p-channel device will be larger, and the device costs will be greater. In the linear region, the drain current is −I d p =

Vgs = constant

The output conductance quantifies the drain current variation with gate voltage variation for a constant gate voltage.


Wc µpC a (V gs +VTh p )Vds − ½Vds2  Lc

For saturation

Wc µpC a (V gs +VTh p )2  Lc The transconductance in the saturation region is ∂i W  W g fs p = D p =  c  µpC a (V gs +VTh p ) = 2  c ∂v gs Q  Lc   Lc −I d p = ½

  µ p C a ( −I d p ) 

−2.3

 T  g fs (T ) ≈ g fs (25°C) ×  (mho)   300  since temperature effects are dominated by mobility variation with temperature.

(3.15)

V(BR)DSS

Vgs(TH)

Vgs =0V

ID=1mA

Inherent in the MOSFET structure are voltage-dependent capacitances and on-state resistance.

3.2.2iv - MOSFET on-state resistance In the fully on-state the drain-source conduction characteristics of the MOSFET can be considered as purely resistive. The on-resistance Rds(on) is the sum of the epitaxial region resistance, the channel resistance, which is modulated by the gate source voltage, and the lead and connection resistance. One reason for the wide proliferation of special gate geometries is to produce extremely short, reproducible channels, in order to reduce Rds(on). In high-voltage devices, the on-resistance is dominated by the resistance of the epitaxial drain region when the device is fully enhanced. For high-voltage n-channel devices, the on-state resistance is approximated by Rds (on) = 6.0 × 10−7 × Vb2.5 / A (Ω) (3.16) where Vb is the breakdown voltage in volts A is the die area in mm2. A p-channel device with the same Vb as an n-channel device has an Rds(on) two to three times larger as given by Rds (on) = 1.6 × 10−6 × Vb2.5 / A (Ω) (3.17) The factor l/gfs of Rds(on) is added to give the total Rds(on). On-state drain-source loss can therefore be based on Id2Rds(on). On-resistance Rds(on) increases with temperature and approximately doubles over the range 25°C to 200°C, having a positive temperature coefficient of approximately +0.7 per cent/K above 25ºC, as shown in figure 3.13. The temperature dependence of the on-state resistance is approximated by 2.3

 T  Rds (on) (T ) = Rds (on) (25°C) ×  (Ω ) (3.18)   300  where the temperature T is in degrees Kelvin. This relationship (as does forward conductance in equation (3.15)) closely follows the mobility charge dependence with temperature.

Since Rds(on) increases with temperature, current is automatically diverted away from a hot spot. Thus unlike the bipolar junction transistor, second breakdown cannot occur within the MOSFET. The breakdown voltage Vb has a positive temperature coefficient of typically 0.1 per cent/K as shown by V(BR)DSS in figure 3.13.

gfs Vds=50V

Figure 3.13. Normalised drain-source on-resistance, transconductance, gate threshold voltage, and breakdown voltage versus junction temperature.

Example 3.1:

Properties of an n-channel MOSFET cell

A silicon n-channel MOSFET cell has a threshold voltage of VTh = 2V, Wc = 10µm, Lc = 1µm, and an oxide thickness of tox = 50nm. The device is biased with Vgs = 10V and Vds = 15V. i. Assuming a quadratic model and a surface carrier mobility of 300 cm2/V-s, calculate the drain current, cell dissipation, forward transconductance, and output conductance. ii. Assuming carrier velocity saturation (5x106 cm/s), calculate the drain current, cell dissipation, forward transconductance, and output conductance. Solution i. The MOSFET is biased in saturation since Vds > Vgs - VTh . Therefore, from equation (3.7) the drain current equals:

I d = ½ µ Ca

Wc (Vgs − VTh ) 2 where Ca = ε / tox Lc

3.85 × 8.85 × 10−12 10µm × × (10V − 2V) 2 = 6.5 mA 50 × 10−9 1µm The dc power dissipation is 6.5mAx15V=97.5mW. From equation (3.11), the transconductance equals: = ½ × 300 × 10−4 ×

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79

g fs = µ C a

Chapter 3

Wc (Vgs − VTh ) Lc

3.85×8.85×10-14 10 × ×(10V - 2V) = 1.64 mho 50×10-9 1 The output conductance gd is zero. = 300×10-4 ×

ii. When the electron velocity saturates, the drain current is given by equation 3.8 I d = ½ vsat Wc Ca (Vgs − VT h ) 3.85×8.85×10-12 × (10V - 2V) = 136 mA 50×10-9 The dc power dissipation is 136mA x 15V=2W, a dc operating condition well in excess of the cell capabilities. The transconductance is given by equation 3.10 g fs = ½ vsatWc Ca = ½ × 5×104 × 10-5 ×

3.85×8.85×10-12 = ½ × 5×10 × 10 × = 16.1 mho 50×10-9 The output conductance gd is zero. 4

-5


3.2.2vii - MOSFET on-state resistance reduction Most power switching devices have a vertical structure, where the gate and source of the MOSFET (or emitter in the case of the IGBT) are on one surface of the substrate, while the drain (or collector) is on the other substrate surface. The principal current flows vertically through the substrate but the conductive channel is lateral due to the planar gate structure, as shown in figure 3.11. The structure resistance components between the drain and source are: • the drift region; • the JFET region; • the accumulation region; and • the channel region. The drift region contribution dominates whilst the contribution from the ohmic contacts and n+ substrate are not significant, in high voltage devices. The channel voltage drop is proportional to channel length and inversely related to width. The channel should therefore be short, but its length is related to voltage rating since it must support the off-state scl.

Whilst retaining the necessary voltage breakdown length properties, two basic approaches have been pursued to achieve a more vertical gate (channel) structure, viz., the trench gate and vertical superjunction, as shown in parts b and c of figure 3.15. Both techniques involve increased fabrication complexity and extra costs. 1 - Trench gate

♣ 3.2.2vi - MOSFET parasitic BJT Figure 3.14 shows the MOSFET equivalent circuit based on its structure and features. The parasitic npn bipolar junction transistor shown in figure 3.14b is key to device operation and limitations. Capacitance exists within the structure from the gate to the source, Cgs, the gate to the drain, Cgd, and from the drain to the source, Cds. The capacitance Cgs varies little with voltage; however Cds and Cgd vary significantly with voltage. Obviously these capacitances influence the switching intervals, an aspect considered in chapter 4.4.2. The emitter of the parasitic npn transistor is the source of the MOSFET, the base is the p-type body and the collector is the drain region. In the construction of the MOSFET, the emitter and base of the npn transistor are purposely shorted out by the source metallization to disable the parasitic device by reducing its injection efficiency. However, this short circuit cannot be perfect and Rbe models the lateral p-body resistance, while Cob is essentially Cds. The npn transistor has a collector-emitter breakdown voltage, between Vcbo and Vceo. If an external dv/dt is applied between the drain and source as shown in figure 3.14b, enough displacement current could flow through Cob to generate a voltage drop across Rbe sufficient to turn on the parasitic bipolar device, causing MOSFET failure in second breakdown. When the drain to source voltage is negative, current can flow from the source to drain through Rbe and the base to collector junction of the parasitic npn transistor within the structure, the dashed line shown in figure 3.14b. This is termed the body diode, inherent in the MOSFET structure. Drain

n+

A channel is formed on the vertical sidewalls of a trench etched into the die surface as shown in figure 3.14b. The JFET resistive region is eliminated, which not only reduces the total resistance but allows smaller cell size thereby increasing channel density and decreasing the short-circuit capacity. The trench corners must be rounded to avoid high electric field stress points. By extending the gate into the drift region, the gate to drain capacitance increases, hence increasing gate charge requirements. S o urc e

g a te n+ p

n

-

epi

n +s u b

D rain (a )

S o urce

S o u rce g a te

ga te

n ++ p

n p

n

g a te

-

n

-

D ra in

RD

Cgd

C gd p+

n

C ds

Cds

Rbe

2 - Vertical super-junction

Cgs Idiode

Source

Gate

Rg

C gs

(a)

SiO 2

n

-

e pi

D ra in

(b ) (c ) Figure 3.15. Three MOSFET channel structures: (a) conventional planar gate; (b) trench gate; and (c) vertical superjunction.

R be

+

p

n +s u b

n n

80

Source

(b)

Figure 3.14. MOSFET – n-channel enhancement mode: (a) structure and (b) equivalent circuit diagram with parasitic npn bipolar transistor forming an inverse diode.

The structure has vertical p-conducting regions in the voltage sustaining n- drift area, that are extend to the p-wells below the gate, as shown in figure 3.15c. In the off-state, the electric field is not only in the vertical direction but also in the horizontal plane. This means the n-drift region width can be decreased, the on-state resistance is decreased, and the gate charge is reduced for a given surface area. Up to sixteen mask steps are needed which involves repeated cycles of n-type epi-layer growth, masked boron implantation, and finally diffusion. The resultant specific resistance is near linearly related to breakdown voltage, as opposed to Rds (on) × Area ∝ Vbr2.5 , equation (3.16). Typically Rds(on) is five times lower than for the conventional MOSFET, which only uses up to six mask steps.

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Chapter 3

Whilst the trench gate concept can be readily applied to other field effect devices without voltage rating limits, the vertical super-junction is confined to the MOSFET, and then at voltage ratings below about 1000V. 3.2.3

The insulated gate bipolar transistor (IGBT)

The high off-state and low on-state voltage characteristics of the bipolar junction transistor are combined with the high input impedance properties of the MOSFET to form the insulated gate bipolar transistor, + IGBT, as shown in figure 3.16. The basic structure is that of a MOSFET but with a p implanted into the drain region. This p+ collector provides reverse blocking capabilities of typically 40V, which can be enhanced if p-wells through the substrate are used to isolate the die periphery. 3.2.3i - IGBT at turn-on When the IGBT is in the forward blocking mode, and if the positive gate bias (threshold voltage) is applied, which is enough to invert the surface of p-base region under the gate, then an n-type channel forms and current begins to flow. Simultaneously the anode-cathode voltage must be above 0.7V, the potential barrier, so that it can forward bias the p+ substrate / n- drift junction, J1. The electron current, which flows from the n+ emitter via the channel to the n- drift region, is the base drive current of the vertical pnp transistor. It induces the injection of hole-current from the p+ region to the n- base region. The conductivity modulation improves because of this high-level injection of minority carriers holes. This increases the conductivity of the drift region, significantly reducing the drift region resistance, which is why the IGBTs can be used in high voltage applications. Two currents flow into the emitter electrode. One is the MOS electron-current flowing through the channel, and the other is the bipolar hole-current flowing through the p+ body / n- drift junction, J2.


3.2.3ii - IGBT in the on-state The p+ substrate conductively modulates the n- region with minority carriers, which whilst conducting the main collector current, produces a low on-state voltage at the expense of a 0.6 to 0.8V offset in the output voltage characteristics due to the collector pn junction. From figure 3.16c, the IGBT collector current is approximated by

I c = I mos (1 + β pnp )

(3.19)

3.2.3iii - IGBT at turn-off The gate must be shorted to the emitter or a negative bias must be applied to the gate. When the gate voltage falls below the threshold voltage, the inversion layer cannot be maintained, and the supply of electrons into the n- drift region is blocked, whence, the turn-off process begins. However, the turn-off cannot be quickly completed due to the high concentration minority carrier injected into the n- drift region during forward conduction. Initially, the collector current rapidly decreases due to the termination of the electron current through the channel (MOSFET turn-off), and then the collector current gradually reduces, as the minority carrier density decays due to recombination, in the externally inaccessible ndrift region. This storage charge produces a tail current. The operational mechanisms are those of any minority carrier device and result in slower switching times than the majority carrier MOSFET. On-state voltage and switching characteristics can be significantly improved by using the trench gate technique used on the MOSFET, as considered in section 3.2.2 and shown in figure 3.15b. A less stable structure improvement involves using wider trenches, judiciously spaced, so that accumulated holes under the trench, enhance emitter injection of electrons. This injection enhancement reduces the on-state voltage without degrading the switching performance.

collector

Ic

J1

p+

Icp

Icp

Imos

J1

n+

minority carrier injection

collector

n+ buffer

J2

n-

J3

p

J2

J3

n

emitter

emitter

(a)

(b)

gate

emitter

Si02

(a)

emitter

gate

collector

Ic Ic

p

αpnp

J1

minority carrier injection

Icp

Ic

Imos

n- substrate

αnpn

J2

Icp

p J3

n

(c)

(d)

Figure 3.16. Insulated gate bipolar transistor (IGBT): (a) circuit symbol; (b) physical structure showing current paths: (c) normal operation equivalent circuit; and (d) high current latching equivalent circuit.

82

emitter

gate

emitter

(b)

Figure 3.17. Insulated gate bipolar transistor structures and electric field profile: (a) fieldstop PT-IGBT and (b) conventional NPT-IGBT.

83

Power Electronics

Further performance enhancement is gained by using the punch through, PT-IGBT, structure shown in figure 3.17a, which incorporates an n+ buffer region. The conventional non-punch through NPT-IGBT structure is shown in figure 3.17b. Both collector structures can have the same emitter structure, whether a lateral gate as shown, or the MOSFET trench gate in figure 3.15b. Figure 3.17 shows the electric field in the off-state, where the PT-IGBT develops a field as in the pin diode in figure 3.2b, which allows a thinner wafer. The NPT-IGBT requires a thicker wafer (about 200µm for a 1200V device) which results in a larger substrate resistance and a slower switching device. • The PT-IGBT has n+ and p+ layers formed by epitaxial growth on an n- substrate. The electric field plot in figure 3.17a shows that the off-state voltage scl consumes the n- substrate and is rapidly reduced to zero in the n+ buffer. • The NPT-IGBT has a lightly doped n- substrate with the p-regions (p wells and p collector) formed by ion implantation. The electric field distribution in figure 3.17b shows that the n- drift region has to be wide enough to support all the off-state voltage, without punch through to the p collector implant. 3.2.3iv - IGBT latch-up The equivalent circuit in figure 3.16d shows non-ideal components associated with the ideal MOSFET. The parasitic npn bipolar junction transistor (the n+ emitter/ p+ well/ n- drift region are the npn BJT e-b-c) and the pnp transistor (p+ collector/ n- drift/ p+ well are the pnp BJT e-b-c) couple together to form an SCR thyristor structure, as considered in section 3.3. Latching of this parasitic SCR can occur: • in the on-state if the current density exceeds a critical level, which adversely decreases with increased temperature or • during the turn-off voltage rise when the hole current increases in sensitive regions of the structure due to the charge movement associated with the scl widening. 1 - IGBT on-state SCR static latch-up is related to the temperature dependant transistor gains which are related to the BJT base transport factor bt and emitter injection efficiency γi, defined for the BJT in equation (3.2) (3.20) α pnp + α npn = bt γ i pnp + bt γ i pnp = 1 pnp

pnp

Since the conductivity of the drift region under the gate electrode is increased by the introduction of electron current through the channel, most of the holes injected into the drift region are injected at the pbody region under the channel and flow to the source metal along the bottom of n+ source. This produces a lateral voltage drops across the shunting resistance (Rbe in figure 3.16b) of the p-body layer. If this voltage drop becomes greater than the potential barrier of the n+ source / p body layer junction, J3, electrons are injected from the n+ source to the p-body layer, and the parasitic npn transistor (n+ source, p body and n- drift) is turned-on. If the sum of the two (npn and pnp) parasitic transistors’ current gains reach unity in equation (3.20), latch-up occurs. To avoid loss of control and possible IGBT failure, the factors in equation (3.20), which is valid for onstate latch-up, are judiciously adjusted in the device design. Common to both device types is the gate structure, hence the base-emitter junction of the npn parasitic BJT have the same properties. In each structure, the shorting resistor Rbe decreases the injection efficiency of the npn BJT emitter. This resistance is minimized by highly doping the p+ wells directly below the n-emitters and by shortening the length of the n-emitter. The gain αnpn in equation (3.20) is decreased since the injection efficiency γi npn is lowered. Reduction of the pnp BJT gain of the PT-IGBT and NPT-IGBT is achieved with different techniques. • For the NPT-IGBT, the emitter injection efficiency of holes from the p+ zone into the n- drift region is high because of the large difference in doping concentrations at the junction. Adversely this yields a high injection efficiency γipnp. The base transport factor bt pnp is already low because of the large width of the n- drift region, and is further reduced by lifetime killing of minority carriers in the n- drift region by using gold doping or electron beam radiation. • For the PT-IGBT, the p+ emitting junction at the collector is a well-controlled shallow implant thus reducing the injection efficiency γi pnp. Charge carrier lifetime killing in the n- drift region to reduce the base transport factor bt pnp, is therefore not necessary. 2 - IGBT turn-off SCR dynamic latch-up can occur while the collector voltage is rising, before the collector current decreases. When the IGBT is switched off, the depletion layer of the n- drift / pbody junction, J2 in figure 3.17, is abruptly extended, and the IGBT latches up due to the displacement current. This limits the safe operating area. Equation (3.20) is modified by equation (3.5) to account for voltage avalanche multiplication effects.

Chapter 3


84

Mnpn αnpn + Mpnp α pnp = 1 where

M =

(3.21)

1 1 − (v ce /Vb )m

This dynamic latch-up mode is adversely affected by increased temperature and current magnitude during the voltage rise time at turn-off. Since vce Vb , M → 1 , and the multiplication effect is not significant in the on-state static latch-up analysis. IGBTs are designed and rated so that the latch-up current is 10 to 15 times the rated current. High temperature characteristics (latching current density) With a rise in temperature, the current gains of the npn and pnp transistors increase. This decreases the latching current. The effect is aggravated by an increase in the resistance of the p base region due to a decrease in hole mobility. 3.2.4

Reverse blocking NPT IGBT

The conventional IGBT inherently has reverse voltage blocking capabilities, albeit low. Normally, the collector boron ion p+ implant forms a transparent abrupt junction, optimised for on-state voltage and turn-off speed. When negative voltage is impressed at the collector in figure 3.16, the p+ substrate / n- drift junction, J1, is reverse biased, and the depletion layer expands to the n- drift region. An optimal design in resistivity and thickness for the n- drift region is necessary in obtaining desirable reverse blocking capability. The width of the n- drift region is equivalent to the sum of depletion width at maximum operating voltage and minority carrier diffusion length. It is important to optimize the breakdown voltage while maintaining a narrow n- drift region width, as the forward voltage drop increases with an increase in n- drift region width. The following equation calculates the n- drift region width: 2εV b + Lp (3.22) d1 =

qN D

where d1: n- drift region width Vb: maximum blocking voltage ND: doping concentration Lp: minority carrier diffusion length =√Dpτp Processing alternative for reverse blocking Because the n region surfaces on the emitter side of the device, the uncontrolled field in this region produced by a reverse voltage, causes premature breakdown. To avoid this, the first processing step is to surround each IGBT die region on the wafer by a deep boron p-well which is selectively driven in from the emitter side. The collector side is mechanically ground to about 100µm, so as to expose to boron diffusion. The remaining processes are essentially as for the conventional NPT IGBT, which results in a structure as shown in figure 3.18. The reverse bias scl is modified and silicon nitride passivation of the emitter surface and an n-channel field stop results in a controlled scl profile, as shown dashed in figure 3.18. Other than increased processing complexity (hence costs) minimal on-state voltage - switching speed compromise arises. Effectively, a device with the performance lagging by one technology generation is achieved. Reverse blocking capability extension to the desirable PT IGBT structure is problematic since the nbuffer region is of a higher concentration than the n-substrate. Thus the formed pn junction will have a significantly lower avalanche breakdown voltage level, as predicted by equation 2.3. Conventional NPT igbt section

reverse E fielded modified

collector metallization p+ collector implant n

die edge Deep p diffusion from emitter side

p n emitter metal gate

2 p guard rings

n channel stop

Figure 3.18. Reverse voltage blocking NPT-IGBT structure.

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85

3.2.5

Chapter 3

Forward conduction characteristics

Structurally, the IGBT can be viewed as a serial connection of the MOSFET and PiN diode. Alternatively, it is sometimes considered a wide base pnp transistor driven by the MOSFET in a Darlington configuration. The former view can be used to interpret the behaviour of the device, but the latter better describes the IGBT. The width of the undepleted n- drift region does not change rapidly with the increase in the collector voltage due to the high concentration of the buffer layer, but maintains the same width as the n+ buffer layer for all collector voltages. This results in a constant value of the pnp transistor’s current gain. Additionally, the n+ buffer layer reduces the injection efficiency of the p+ substrate / n+ buffer junction, J1. This reduces the current gain of the pnp transistor. Also, the collector output resistance can be increased with electron irradiation to shorten the minority carrier lifetime, which reduces the diffusion length. The IGBT saturated collector current expression involves the MOSFET current given by equation (3.7), giving: W 1 Id = × ½ µ c C a (V gs −VTh )2 (3.23) (A) 1 − α pnp Lc


control the effective cross-sectional area of a conducting channel. If the zero bias voltage cuts off the channel then the JFET is normally off, otherwise if a reverse bias is needed to cut-off the channel, the JFET is termed normally on. The electrical properties of SiC make the JFET a viable possibility as a power switch. Two normally on JFET structures are shown in figure 3.19, where it is seen how the scl layer decreases the channel width as the source to gate voltage reverse bias increases. In SiC, the channel has a positive temperature coefficient, Ron ∝ T 2.6 , hence parallel connection is viable. Natural current saturation with a positive temperature coefficient means lengthy short-circuit currents of over a millisecond can be sustained. Although the channel is bidirectional, in the biased off-state an integral fast, robust pn body diode is inherent as seen in figure 3.19b. The natural off-state properties of the MOSFET make the SiC variant more attractive than the JFET. The simpler JFET structure has revived interest in its SiC fabrication. s o u rc e

-

s o u rc e

+

g a te

n

+

n

-

n

p

p

s o u rc e

p

+

switching speed (same on-state loss)

+

n

g

s o u rc e

g a te p

+

n

(b )

n b u ffe r 4 H n + s u b s tr a te

b o d y d io d e

Figure 3.19. Cross-section of the SiC vertical junction field effect transistor: (a) trench gate with channel shown and (b) variation incorporating a pn body diode.

NPT IGBT

More rugged due to wider base and low pnp gain

short circuit rating

d p+

-

Higher vce(sat)

Faster switching due to high gain and reduced minority carrier lifetime

+

n d r ift r e g io n

d r a in

Increases with temperature Suitable for parallel connection

-

(a )

d r a in

Table 3.1: PT versus NPT IGBTs

(same switching speed)

n

s

m e ta l

The N+ buffer layer improves turn-off speed by reducing minority carrier injection and by increasing the recombination rate during the switching transition. In addition, latch-up characteristics are improved by reducing the PNP transistor current gain. The trade-off is that the on-state voltage increases. However, the thickness of the N- drift region can be reduced with the same forward voltage blocking capability because the N+ buffer layer improves the forward voltage blocking capability. As a result, the on-state voltage can be decreased. Hence, the PT-IGBT has superior trade-off characteristics as compared to the NPT-IGBT in switching speed and forward conduction voltage. Most IGBTs are PT-IGBTs. The IGBT static forward and reverse blocking capabilities for both types are similar because these characteristics are determined by the same N- drift layer thickness and resistance. The reverse-blocking voltage of PTIGBTs that contain the N+ buffer layer between the P+ substrate and N- drift region is lowered to tens of volts due to the heavy doping regions bounding J1.

PT IGBT

+

scl

channel

Generally, faster switching speed is traded for higher on-state losses, and vice versa.

conduction loss

n+

scl

PT IGBT and NPT IGBT comparison

Lower vce(sat) Decreases slightly with temperature A slight positive temperature co-efficient at high current densities allows parallel connection.

g a te

+

+

n

IGBT TYPE

-

m e ta l

Transconductance in the active region is obtained by differentiating the drain current with respect to Vge. The IGBT’s saturated collector current and transconductance are higher than those of the power MOSFETs of the same aspect ratio (Wc /Lc). This is because the pnp transistor’s current gain αpnp is significantly less than 1. W 1 g fs = × µ c C a (V gs −VTh ) (mho) (3.24) Lc 1 − α pnp 3.2.6

86

3.3

Thyristors

The name thyristor is a generic term for a bipolar semiconductor device which comprises four semiconductor layers and operates as a switch having a latched on-state and a stable off-state. Numerous members of the thyristor family exist. The simplest device structurally is the silicon-controlled rectifier (SCR) while the most complicated is the triac.

turn-on switching loss

Largely unaffected by temperature

Largely unaffected by temperature

3.3.1

turn-off switching loss

Loss increases with temperature but start lower than NPT devices

Virtually constant with temperature

The basic SCR structure and doping profile in figure 3.20 depicts the SCR as three pn junctions J1, J2, and J3 in series. The contact electrode to the outer p-layer is called the anode and that to the outer nlayer is termed the cathode. With a gate contact to the inner p-region, the resultant three-terminal, 4 layer thyristor device is technically called the silicon-controlled rectifier (SCR). A low concentration n-type silicon wafer is chosen as the starting material. A single diffusion process is then used to form simultaneously the p1 and p2 layers. Finally, an n-type layer, n1, is diffused selectively into one side of the wafer to form the cathode. The masked-out areas are used for the gate contact to the p1 region. To prevent premature breakdown at the surface edge, bevelling is used as in figure 3.1, to ensure that breakdown will occur uniformly in the bulk.

3.2.7

The junction field effect transistor (JFET)

The field effect for a FET may be created in two ways: • A voltage signal controls charge indirectly using a capacitive effect as in the MOSFET, section 3.2.2. • In a junction FET (JFET), the voltage dependant scl width of a junction is used to

The silicon-controlled rectifier (SCR)

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A number of observations can be made about the doping profile of the SCR which relate to its electrical characteristics. The anode and cathode would both be expected to be good emitters of minority carriers into the n2 and p1 regions respectively because of their relative high concentrations with respect to their injected regions. The n2 region is very wide, typically hundreds of micrometres, and low concentration, typically less than 1014 /cc. Even though the hole lifetime may be very long, 100µs, the base transport factor for hole minority carriers, bt-n2 is low. The low-concentration provides high forward and reverse blocking capability and the associated reverse-biased scl’s penetrate deeply into the n2 region. Gold lifetime killing or electron irradiation, most effective in the n2 region, is employed to improve the switching speed by increasing the number of carrier recombination centres.

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bias leakage current. The collector current of the npn transistor T1 with a dc current gain of α1 is given by I c1 = α1 I K + I co1

By equating Ib2 and Ic1 (1 - α 2 ) I A - I co 2 = α1 I K + I co1

Since IK = IA + IG IA =

α1 I G + I co1 + I co 2 α1 I G + I co1 + I co 2 = 1 - (α1 + α 2 ) 1 - G1

(A)

(3.25)

where α1 + α2 is called the loop gain, G1.

Ib2 = α1IK

Ib1

Figure 3.21. Cross-section of the SCR showing its model derivation: (a) schematic of the SCR cross-section; (b) the division of the SCR into two transistors; and (c) the npn-pnp two-transistor model of the basic SCR.

At high voltages, to account for avalanche multiplication effects, the gains are replaced by Mα, where M is the avalanche multiplication coefficient in equation 3.15. Hence, G1 becomes M1α1 + M2α2. By inspection of equation (3.25) it can be seen that a large anode current results when G1 → 1, whence the circuit regenerates with each transistor driving its counterpart into saturation. All junctions are forwardbiased and the total device voltage is approximately that of a single pn junction, with the anode current limited by the external circuit. The n2-p1-n1 device acts like a saturated transistor and provides a remote contact to the n2 region. Therefore the device behaves essentially like a p-i-n diode (p2-i-n1), where the voltage drop across the i-region is inversely proportional to the recombination rate. Typical SCR static IV characteristics are shown in figure 3.22. Figure 3.20. The silicon-controlled rectifier, SCR: (a) net impurity density profile; (b) circuit symbol; and (c) cross-sectional view.

The two-transistor model of the SCR shown in figure 3.21 can be used to represent the p2-n2-p1-n1 structure and explain its electrical and thermal characteristics. Transistor T1 is an npn BJT formed from regions n2-p1-n1 while T2 is a pnp BJT formed from SCR regions p2-n2-p1. The application of a positive voltage between anode and cathode does not result in conduction because the SCR central junction J2 is reverse-biased and blocking. Both equivalent circuit transistors have forward-biased emitter junctions and with reverse-biased collector junctions, both BJT’s can be considered to be cut off. 3.3.1i - SCR turn-on It is evident from figure 3.21c that the collector current of the npn transistor provides the base current for the pnp transistor. Also, the collector current of the pnp transistor along with any gate current IG supplies the base drive for the npn transistor. Thus a regenerative current situation occurs when the loop gain exceeds unity. The base current of the pnp transistor T2 with dc current gain α2 is I b 2 = (1 - α 2 ) I A - I co 2 which is supplied by the collector of the npn transistor. The current Ico is the collector junction reverse

Figure 3.22. The silicon-controlled rectifier static I-V characteristics.

At low current levels, α1 and α2 are small because of carrier recombination effects, but increase rapidly as the current increases. The conventional gate turn-on mechanism is based on these current gain properties. External gate current starts the regeneration action and the subsequent increase in

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anode current causes the gains to increase, thus ensuring a high loop gain, whence the gate current can be removed. The I-V characteristics in figure 3.22 show this property, where a minimum anode current ILatch is necessary for the loop gain to increase sufficiently to enable the SCR to latch on by the regeneration mechanism. The SCR can be brought into conduction by a number of mechanisms other than via the gate (other than the light triggered SCR used in high-voltage dc converters). • If the anode-cathode voltage causes avalanche multiplication of the central junction, the increased current is sufficient to start the regenerative action. The forward anode-cathode breakover voltage VBF is dependent on the central junction J2 avalanche voltage and the loop gain according to VBF = Vb (1 - α1 - α 2 )1/ m (V) (3.26) where the avalanche breakdown voltage, at room temperature, for a typical SCR p+n central junction J2 is given by equation (2.3) Vb = 5.34 × 1013 × N D-¾ (V) (3.27) where ND is the concentration of the high resistivity n2 region when 1013 < ND < 5x1014 /cc. • Turn-on can also be induced by means of an anode-to-cathode applied dv/dt where the peak ramp voltage is less than VBF. The increasing voltage is supported by the central blocking junction J2. The associated scl width increases and a charging or displacement current flows according to i = d(Cv)/dt. The charging current flows across both the anode and cathode junctions, causing hole and electron injection respectively. The same mechanism occurs at the cathode if gate current is applied; hence if the terminal dvldt is large enough, SCR turn-on occurs. • The forward SCR leakage current, which is the reverse-biased pn junction J2 leakage current, doubles approximately with every 8K temperature rise. At elevated temperatures, the thermally generated leakage current (in conjunction with the gains increasing with temperature and current) can be sufficient to increase the SCR loop gain such that turn-on occurs. 3.3.1ii - SCR cathode shorts All SCR turn-on mechanisms are highly temperature-dependent. A structural modification commonly used to reduce device temperature sensitivity and to increase dv/dt rating is the introduction of cathode shorts. A cross-sectional structure schematic and two-transistor equivalent of the cathode shorting technique are shown in figure 3.23. It will be seen that the cathode metallization overlaps the p1 region, which is the gate contact region. The technique is based on some of the anode forward-blocking current being shunted from the cathode junction via the cathode short. The cathode electron injection efficiency is effectively reduced, thereby decreasing α1 which results in an increase in the forward voltage-blocking rating VBF and dv/dt capability. The holding and latching currents are also increased.

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The cathode-anode, reverse breakdown voltage VBR is shown in figure 3.22. The anode p2+n2 junction J1 characterises SCR reverse blocking properties and VBR is given by (equation (3.6)) VBR = Vb (1 - α 2 )1/ m

If a very high resistivity n2 region, NDn2, is used (in conjunction with low temperature) and breakdown is due to punch-through to J2, then the terminal breakdown voltage will be approximated by (equation (2.2)) VPT = 7.67 × 10-16 N Dn2 Wn22 where Wn2 is the width of the n2 region. This relationship is valid for both forward and reverse SCR voltage breakdown arising from punch-through.

Figure 3.24. The amplifying gate SCR: (a) cross-section of the structure and (b) two-SCR equivalent circuit.

3.3.1iii - SCR amplifying gate At SCR turn-on, only a small peripheral region of the cathode along the gate region conducts initially. The conducting area spreads at about 50m/s, eventually encompassing the whole cathode area. If at turn-on a very large anode current is required, that is a high initial di/dt, a long gate-cathode perimeter is necessary in order to avoid excessively high, localised initial cathode current densities. The usual method employed to effectively enlarge the SCR initial turn-on area is to fabricate an integrated amplifying gate, as shown in figure 3.24. A small gate current is used to initiate the pilot SCR, which turns on very rapidly because of its small area. The cathode current of this pilot SCR provides a much larger gate current to the main SCR section than the original gate triggering current. Once the main device is fully on, the pilot device turns off if the gate current is removed. An important property of the SCR is that once latched on, the gate condition is of little importance. The regenerative action holds the device on and SCR turn-off can only be achieved by reducing the anode current externally to a level below which the loop gain is significantly less than unity. 3.3.2

Figure 3.23. Shorted cathode SCR: (a) SCR cross-section showing some anode current flowing through cathode shorts and (b) the SCR two-transistor equivalent circuit SCR with cathode shorts.


The asymmetrical silicon-controlled rectifier (ASCR)

The doping profiles and cross-sectional views comparing the asymmetrical SCR and conventional SCR are shown in figure 3.25. In each case the electric field ξ within the p1n2 junction reverse-bias scl is shown and because the n2 region is lightly doped, the scl extends deeply into it. The scl applied reverse-bias voltage is mathematically equal to the integral of the electric field, ξ (area under the curve). If, in the conventional SCR, the scl edge reaches the p2+ layer, then punch-through has occurred and the SCR turns on. To prevent such a condition and to allow for manufacturing tolerances, the n2 region is kept thick with the unfortunate consequence that on-state losses, which are proportional to n2 layer thickness, are high. In the case of the ASCR, a much thinner n2- region is possible since a highly doped n layer adjacent to the p2+ anode is utilised as an electric field stopper. The penalty paid for this layer construction is that in the reverse voltage blocking mode, the n2p2+ junction avalanches at a low voltage of a few tens of volts. Thus the ASCR does not have any usable repetitive reverse-blocking ability, hence the name asymmetrical SCR. By sacrificing reverse-blocking ability, significant improvements in lower on-state voltage, higher forward-blocking voltage, and faster turn-off characteristics are attained.

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92

p

Figure 3.26. Reverse conducting thyristor with an amplifying gate structure: (a) cross-section of the structure and (b) typical doping profile of the SCR section. Figure 3.25. Doping profile, cross-section, and the electric field of J2 in the forward biased off-state for: (a) and (b) the conventional SCR; (c) and (d) the asymmetrical SCR.

3.3.3

The reverse-conducting thyristor (RCT)

The RCT is electrically equivalent to an SCR in anti-parallel with a diode, but both are integrated into the same wafer. The reason for integrating the SCR and diode is to minimise external interconnecting lead inductance. The circuit symbol, cross-sectional wafer view, and typical doping profile are shown in figure 3.26. Since no reverse voltage will be applied to the RCT there is only the cathode-side deep p-diffused layer. This and the ASCR n-region type field stopper result in low forward voltage characteristics. As in the ASCR case, the highly n-type doped anode end of the wide n-region also allows higher forward voltages to be blocked. Both anode and cathode shorts can be employed to improve thermal and dv/dt properties. As shown in figure 3.26a, an amplifying gate can be used to improve initial di/dt capability. The integral anti-parallel diode comprises an outer ring and is isolated from the central SCR section by a diffused guard ring, or a groove, or by irradiation lifetime control techniques. The guard ring is particularly important in that it must confine the carriers associated with the reverse-blocking diode to that region so that these carriers do not represent a forward displacement current in the SCR section. If the carriers were to spill over, the device dv/dt rating would be reduced - possibly resulting in false turnon. Gold or irradiation lifetime killing can be employed to reduce the turn-off time without significantly increasing the on-state voltage.

3.3.4

The bi-directional-conducting thyristor (BCT)

Two anti-parallel connected SCRs can be integrated into one silicon wafer, as shown in figure 3.27. As a result of integrated symmetry, both devices have near identical electrical properties. The mechanical feature different to the triac, is that there are two gates – one on each side of the wafer. Also, unlike the triac, the two SCR sections are physically separated in the wafer to minimise carrier diffusion interaction. The equivalent circuit comprises two SCRs connected in anti-parallel. As such, one device turning off and supporting a negative voltage, represents a positive dv/dt impressed across the complementary device, tending to turn it on. Also, any charge carries which diffusion from the SCR previously on, exasperate the dv/dt stress on the off SCR. The two central amplifying gate structures are as for the RCT, in figure 3.26a. A separation of a few minority carrier lateral diffusion lengths, along with an increased density of cathode shorts along the separating edge of each cathode and in the amplifying gate region close to the anode of the complementary SCR, enhance the physical separation. The amplifying gate fingers are angled away from the separation regions to minimise the shorting effect of the complementary SCR anode emitter shorting. The on-state voltage of each SCR is fine tuned, match for on-state loss, using electron irradiation. 3.3.5

The gate turn-off thyristor (GTO)

The gate turn-off thyristor is an SCR that is turned on by forward-biasing the cathode junction and turned off by reverse-biasing the same junction, thereby preventing the cathode from injecting electrons into the p1 region. Other than its controlled turn-off properties, the GTO’s characteristics are similar to the conventional SCR. The basic structure and circuit symbol are shown in figure 3.28.

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94

The turn-off gain of the GTO, βQ, is defined as the ratio of anode current IA to reverse gate current IGQ, that is β Q ≡ I T / I GQ (3.28) < α1 / (α1 + α 2 - 1) Thus for high turn-off gain it is important to make α1 for the npn section as close to unity as possible, while α2 of the pnp section should be small. A turn-off current gain of 5 is typical. During the turn-off process, the conducting plasma is squeezed to the centre of the cathode finger, since the lateral p1 region resistance causes this region to be last in changing from forward to reverse bias. This region has the least reverse bias and for reliable GTO operation, the final area of the squeezed plasma must be large enough to prevent an excessive current density. Device failure would be imminent because of localised overheating. The doping profile is characterised by a low p1 region sheet resistance and an inter-digitated cathode region to ensure even distribution of the reverse bias across the cathode junction at turn-off. Both turnoff and temperature properties are enhanced by using an anode shorting and defocusing technique as shown in figure 3.29a, but at the expense of any reverse-blocking capability and increased on-state voltage. The shown two-level cathode and gate metallization used on large-area devices allow a flat metal plate for the cathode connection. As with the conventional SCR, a reverse conducting diode structure can be integrated, as shown in figure 3.29b. Figure 3.27. Cross-section structure of the bidirectional conducting phase-control SCR with an amplifying gate structure.

3.3.5i - GTO turn-off mechanism In the on-state, due to the high injection efficiency of junctions J1 and J3, the central p-base is flooded with electrons emitted from the n-cathode and the central n-base is flooded with holes emitted from the p-anode. If a reverse gate current flows from the cathode to the gate, with a driving voltage tending to reverse bias the gate-cathode junction – then p-base holes are extracted from the gate, suppressing the cathode junction from injecting electrons. Eventually the cathode junction is cut-off and the pnp transistor section, now without base current turns off, thereby turning off the GTO. The turn-off mechanism can be analyzed by considering the two-transistor equivalent circuit model for the SCR shown in figure 3.21c. The reverse gate current IGQ flows from the gate and is the reverse The base current for transistor T1 is given by base current of the npn transistor T1. I B = α 2 I A − I GQ , where I GQ = − I G . The reverse base current in terms of the gain of T1 is I RB = (1 − α1 ) I K . The GTO as a three terminal device must satisfy I A = I K + I GQ and to turn-off the GTO, IB < IRB. These conditions yield (α1 + α 2 − 1) I A < α 2 IGQ

3.3.6

The gate commutated thyristor (GCT)

GTO frequency limitations and the need for an external parallel connected capacitive turn-off snubber (to limit re-applied dv/dt), have motivated its enhancement, resulting in the gate commutated thyristor, GCT. As shown in figure 3.29c, a number of processing and structural variations to the basic GTO result in a more robust and versatile high power switch.

•

•

•

n-type buffer An n-type buffer layer allows a thinner n-drift region. A 40% thinner silicon wafer, for the same blocking voltage, reduces switching losses and the on-state voltage. An integral reverse conducting diode is also possible, as with the conventional SCR and GTO. transparent emitter A thin lightly doped anode p-emitter is used instead of the normal GTO anode shorts. Some electrons pass through the layer as if the anode were shorted and recombine at the anode contact metal interface, without causing hole emission into the n-base. Effectively, a reduced emitter injection efficiency is achieved without anode shorts. Consequently, gate current triggering requirements are an order of magnitude lower than for the conventional GTO. low inductance A low inductance gate structure, contact, and wafer assembly ( 3.3kV).

4

4.1.2

Electrical Ratings and Characteristics

Forward current ratings

The forward current ratings are usually specified after consideration of the following factors. • • •

of Power Semiconductor Switching Devices

Current at which the junction temperature does not exceed a rated value. Current at which internal leads and contacts are not evaporated. External connector current-handling capabilities.

Semiconductor device characteristics and ratings are primarily concerned with electrical and thermal properties. The thermal properties and cooling design aspects are similar for all power switching semiconductor devices. A common, unified thermal design approach is applicable since manufacturers use the concept of a semiconductor device being thermally represented by one virtual junction. This virtual junction is considered as the point source of all losses, which comprise on-state and off-state losses as well as switch-on and switch-off losses and any control input loss. Not only are the power dissipation characteristics similar for all semiconductor devices, but many similarities exist in the area of maximum device ratings. 4.1

General maximum ratings of power switching semiconductor devices

The maximum allowable limits of current, applied voltage, and power dissipation are defined as the maximum ratings for that device. These absolute maximum ratings are important and the device must not experience a condition under which any one limit is exceeded if long life and reliability are to be attained. Generally, at worst, the device should experience only one near maximum rating at any instant. Ratings are dependent on the materials used, the structure, the design, the mount, and the type of processes employed. The one property inherent in these physical features is temperature dependence and its interaction on electrical properties. Maximum ratings are therefore generally based on the variation of electrical characteristics that arises from the created variations. Because of this close correlation between properties, different ratings cannot be considered independently. Also, ratings are highly dependent on the device external circuit conditions. This interdependence of device properties and the effects of external circuit conditions are no more evident than during thermal runaway - a condition to be avoided. Such a condition can occur in all devices that have bipolar junctions. For example, with the diode, thyristor, and the MOSFET’s parasitic diode; reverse recovery current increases junction temperature. The reverse recovery charge increases with temperature, thus increasing junction power dissipation and further raising the junction temperature. This endless increasing of temperature and recovery charge results in thermal runaway and eventual device destruction. A similar thermal runaway condition occurs in the bipolar transistor and devices employing BJT mechanisms, like the thyristor and the IGBT. Here, collector current causes an increase in temperature which increases the conductivity of the bipolar transistor. More current then flows, further increasing the device temperature. If external circuit conditions allow, thermal runaway occurs, eventually resulting in irreversible device damage. Figure 4.1 shows the electrical operating bounds of common semiconductor power switches, where the general trend is the higher the I-V ratings the slower the possible switching frequency, (because of increased losses associated with attaining higher sustaining voltages), hence increased junction temperature. High-frequency low-power switching applications are dominated by the MOSFET or possibly trench-gate IGBTs while high-power low-frequency switching applications are dominated by thyristor type devices or possibly IGBT modules. Rectifying or fast recovery diodes, as appropriate, are available with matched I-V ratings for all the switch device types in figure 4.1.

BWW

4.8kV, 5kA SCR 12kV, 1.5kA SCR 6kV, 6kA GTO 6.5kV, 4.2kA GCT

1700V 3600A 6500V 600A

SiC: Schottky diode 1200V, 50A MOSFET 1200V, 20A, 75mΩ JFET 1200V, 20A, 63mΩ JFET 1700V, 5A, ½Ω BJT 1200V, 100A, β=135

Figure 4.1. Electrical rating bounds for power switching silicon devices, where (a) frequency related losses limit upper power through-put and (b) voltage is restricted by silicon limitations while current is bounded by packaging and die size constraints.

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4.1.3

Chapter 4

Temperature ratings

The maximum allowable junction temperature Tl j , is dependent on the quality of the materials used and the type of junction, and is traded off against the reduced reliability that arises from deterioration and accelerated service life. The higher the junction temperature, the higher the rate of deterioration. The relationship between service life Lt in hours, and the junction temperature Tj (K) is approximated by log10 Lt ≈ A + B / T j

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104

Initially at turn-on, the device resistance is dominated by the ohmic resistance of the lowconcentration n-region. As the concentration of the injected minority carriers increases, the n-region becomes conductively modulated and the associated ohmic voltage drop decreases significantly. These charging effects contribute to a minor initial capacitive component which serves to clamp Vfp initially to zero.

(4.1)

where A and B are constants which are related to the device type. 4.1.4

Power ratings

Power dissipated in a semiconductor device is converted into thermal energy which produces a l are the temperature rise. The major parameters limiting the maximum allowable power dissipation P d maximum allowable junction temperature and the device case temperature Tc. These parameters are related to one another by the thermal resistance Rθ, according to l l = T j - Tc P (W) (4.2) d Rθ j-c The virtual junction to case thermal resistance Rθ j-c is a physical value representing the ratio, junction temperature rise per unit power dissipation. Thermal resistance is a measure of the difficulty in removing heat from the junction to the case. Most maximum power values are specified at a case temperature of 25°C, and are derated linearly to zero as the case-operating temperature increases to Tl j , which is typically a maximum of 175°C for silicon power switching devices. 4.2

The fast-recovery diode

Static I-V diode characteristics were considered in chapter 2 and chapter 3.1. In low-frequency applications the only problem posed by a rectifier is heat dissipation, which can be readily calculated if the current waveform is known. On the other hand, calculation of losses in rectifiers for high-frequency application requires knowledge of device switching phenomena. The forward and reverse recovery characteristics are the most important fast-recovery bipolar pn diode electrical switching properties.

Figure 4.3. Diode forward turn-on characteristics for two initial anode di/dt cases: (a) forward current and effective change in resistive component, r and (b) anode voltage and voltage contribution vℓ, as a result of die inductance.

The forward diF /dt causes a voltage drop across the internal device inductance. This inductance comprises both the diode wafer internal inductance and the bonding and connection inductance. In bipolar power devices, the inductance of the wafer predominates. Any inductance contribution to the forward transient voltage ceases when the steady-state current level IF is reached, as shown in figure 4.3. It will be seen that the peak forward transient voltage increases as diF /dt increases. The resistive component predominates at low diF /dt. As with most minority carrier based power semiconductor characteristics, the turn-on phenomenon is significantly worsened by an increase in junction temperature. That is, both tfr and Vfp are increased with increased temperature. Although a pre-reversed biased junction condition does not significantly prejudice the turn-on characteristics, if the junction is pre-forward biased slightly, the turn-on transitional phase can be significantly reduced. The Schottky diode, a majority carrier device, does not suffer from forward turn-on transient effects. Package inductances dominate at turn-on. 4.2.2

Turn-off characteristics

When a forward-conducting bipolar junction diode is abruptly reverse-biased, a short time elapses before the device actually regains its reverse blocking capabilities. Most importantly, before the diode does regain blocking ability, it may be considered as a short circuit in its normally blocking direction. During forward conduction there is an excess of minority carriers in each diode region and the holes in the n-region and electrons in the p-region must be removed at turn-off. The attempted reverse bias results in a reverse current flow as shown in figure 4.4. The total recovery charge QΣ is given by

Figure 4.2. Diode forward recovery measurement: (a) specification of forward recovery time, tfr and peak forward voltage, Vfp and (b) diode anode current test waveform.

4.2.1

Turn-on characteristics

During the forward turn-on period of a rectifier, an overshoot voltage is impressed in a forward bias direction across the diode as the forward current increases. The forward recovery characteristics of time tfr and peak forward voltage Vfp are measured as shown in figure 4.2, with a specified increase in forward current diF/dt, rising to a maximum forward current level IF. Two mechanisms predominate and contribute to the forward voltage overshoot phenomenon. The first mechanism is resistive, while the second is inductive.

QΣ = τ I F (4.3) where IF is the forward current before switching. In the usual p+n diode, the excess minority holes in the n-region are more dominant. The lifetime τ is therefore the hole lifetime τh. Since carrier lifetime increases with temperature, recovery charge increases with temperature. The recovery charge QΣ has two components, one due to internal excess charge natural recombination and the other, the reverse recovery charge QR, due to the reverse diode current shown in figure 4.4. The excess charges reside in the neutral scl regions of the diode that border the junction. The excess charge concentration is largest at the scl edge on the n-side, reducing to zero well before the cathode contact. Turn-off is initiated at tf and the reverse recovery current irr commences. The rate of rise of this current is determined solely by the external inductance L of the switching circuit and the circuit applied reverse voltage E, according to dI F E (A/s) (4.4) =− dt L

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Until the time to, the diode carries forward current and is forward-biased. When the current reverses, the forward voltage drop decreases slightly but the device still remains positively biased. The external circuit inductance L supports the voltage E. The excess carrier concentrations now begin to reduce as holes leave via the junction, in providing the reverse current, irr. Holes are therefore extracted first and quickest at the edge of the scl.

Figure 4.4.

106

Reverse recovery is dominated by the barrier charging – a capacitive effect, which increases slightly with increased temperature, reverse di/dt, and IF. The barrier charge requirements are significantly less than the highly temperature dependant minority carrier charge QΣ, associated with the bipolar pn junction diode. Unlike the pn diode, as Schottky junction charging occurs, the junction reverse bias voltage begins to increase immediately. Turn-off voltages are well controlled, less snappy, as the scl capacitor barrier junction acts like a capacitive turn-off snubber, as considered in chapter 8.3. Whereas the transient performance is virtually independent of temperature, the static forward and reverse I-V characteristics are highly temperature dependant. In the case of silicon carbide, the reverse leakage current increases by 4% /K, the reverse breakdown voltage decreases by -4% /K while a 0.45% /K increase in on-state voltage means die can be readily parallel connected. In contrast, it will be noticed in figure 2.2 that reverse breakdown voltage and leakage current of a bipolar junction diode, both have a positive temperature co-efficient.

Diode voltage and current during reverse recovery at turn-off.

At time t1, the hole concentration at the scl edge reaches zero, the charge Q1 has been removed (plus natural recovery) and charge Q2 remains. The reverse current now reduces rapidly since insufficient holes exist at the scl edge. The scl widens quickly, as it is charged. That is, the diode regains its ability to support reverse voltage and at the maximum reverse current IRM, dIF /dt reduces to zero. Since dIF / dt = 0, the voltage across the circuit inductance L drops rapidly to zero and E is applied in reverse bias across the diode. Between t1 and t2 the rate of change of reverse current dirr /dt is high and, in conjunction with L, produces a reverse voltage overshoot to VRM. After time t2, dirr /dt reduces to zero, the circuit inductance supports zero volts, and the diode blocks E. In specifying the reverse recovery time, trr = t2 - t0, the time t2 is defined by projecting irr through ¼IRM as shown in figure 4.4. The reverse recovery time trr and peak reverse recovery current IRM, at high magnitude dIF I dt such that QR ≈ QΣ, are approximated by trr ≈ 2.8 × 10-6 Vb I F / dI F / dt and


I RM ≈ 2.8 × 10-6 Vb I F × dI F / dt

(s) (A)

(4.5)

Figure 4.5. Comparison of fast recovery diode dirr/dt characteristics of: (a) short current tail, producing snap-off (low Sr) and (b) gradual current tail, producing soft recovery (high Sr).

4.3

The bipolar, high-voltage, power switching npn junction transistor

The electrical properties of the high-voltage power switching npn transistor are related to and dominated by the wide low-concentration n- collector region employed to obtain high-voltage characteristics in all semiconductor devices. Many of the limitations and constraints on the MOSFET, IGBT, and the different thyristors are due to their parasitic bjt structures, which introduce undesirable BJT characteristics and mechanisms. It is therefore essential to understand the electrical characteristics and properties of the BJT if the limitations of other switching semiconductor devices are to be appreciated.

where the avalanche breakdown voltage for a step junction, Vb, is given by equation (2.3). The reverse recovery charge QR is therefore given by QR = ½ I RM trr = 3.92 × 10-12 Vb2 I F

(C)

(4.6)

that is, the reverse recovery charge is proportional to the forward current, as shown in figure 5.9a for dIF /dt >100 A/µs. Figure 4.5 illustrates snap-off and soft recovery diode properties (Sr) which are characterised by the recovery dirr /dt magnitude. The higher the value of dirr /dt, the higher is the induced diode overshoot VRM and it is usual to produce soft recovery diodes so as to minimise voltage overshoot VRM, resulting from inductive ringing.

4.3.1

4.3.1i – BJT collector voltage ratings The breakdown voltage ratings of a transistor can be divided into those inherent to the actual transistor (Vceo, Vcbo) and those that are highly dependent on the external base circuit conditions (Vcer, Vces, Vcev). Figure 4.6 shows the various voltage breakdown modes of the BJT, which are defined as follows. Vcbo

Reverse recovery properties are characterised for a given temperature, forward current IF, and dIF/dt as shown in figure 5.9.

Vceo

4.2.3

Vces

Schottky diode dynamic characteristics

Being a minority carrier device, the Schottky barrier diode, both in silicon and silicon carbide, is characterised by the absence of forward and reverse recovery, plus the absence of any temperature influence on switching. Forward recovery traits tend to be due to package and external circuit inductance.

Transistor ratings

Vcer Vcev

Collector to base voltage-current characteristics with the emitter open; that is, Ie = 0, where V(BR)cbo is the collector to base breakdown voltage with Ie = 0 and the collector current Ic specified as Icbo. Collector to emitter characteristics with the base open circuit such that the base current Ib = 0, where V(BR)ceo is the collector to emitter breakdown voltage with Ib = 0 and Ic specified as Iceo. Collector to emitter characteristics with the base shorted to the emitter such that Vbe = 0, where V(BR)ces is the collector to emitter breakdown voltage with Ic specified as Ices. Collector to emitter characteristics with resistance R between the base and the emitter such that Rbe = R, where V(BR)cer is the collector to emitter breakdown voltage with Ic specified as Icer. Collector to emitter characteristics with reverse base to emitter bias Veb = X, where V(BR)cex is the collector to emitter breakdown voltage with Ic specified as Icex.

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Each breakdown voltage level and its relative magnitude can be evaluated. 1 – BJT V(BR)cbo - maximum collector-base voltage with the emitter open circuit The V(BR)cbo rating is just less than the voltage Vb, where the base to collector junction breaks down because of avalanche multiplication, as illustrated in figure 4.6. The common base avalanche breakdown voltage Vb is determined by the concentration of the collector n-region, Nc /cc, and as its resistivity increases, Vb increases according to (equation (2.3)) Vb = 5.34 × 1013 × N c-¾

(4.7)

(V)

It can be assumed that V(BR)cbo ≈ Vb. 2 – BJT V(BR)ceo - maximum collector-emitter voltage with the base open circuit

Avalanche multiplication breakdown of a common emitter connected transistor occurs at a collector voltage Va when the common emitter amplification factor β becomes infinite. The gain β, from equation 3.4 and accounting for avalanche multiplication, is defined by αM β= 0 (4.8) 1 − α0 M where M is the avalanche multiplication factor, which is collector junction voltage Vcb dependent, according to (equation 3.17) m

 V  M = 1 /  1- cb  (4.9)  Vb  The factor m is empirically determined and is between 2 and 4 for the collector-base doping profile of the high-voltage silicon npn transistor. The common base current amplification factor α0 is for a voltage level well below any avalanche.


It can be shown that (see figure 4.6) V( BR )cbo > V( BR )cex > V( BR )ces > V( BR )cer > V( BR )ceo

108

(4.11)

With low-gain BJTs, Va is almost Vb in value, but with high-gain devices Vb may be 2 to 3 times that of Va. Notice in figure 4.6 that negative resistance characteristics occur after breakdown, as is the case with all the base circuit-dependent breakdown characteristics. The inserted diagram in figure 4.6 shows how base-emitter resistance affects collector-emitter voltage breakdown. Importantly, the breakdown voltage increases as the base-emitter resistance decreases. This is because the injection efficiency of the emitter is reduced. This shorting feature is exploited extensively in alleviating parasitic problems in the MOSFET, IGBT, and thyristor devices, and is discussed in the respective device sections. 4.3.1ii – BJT safe operating area (SOA) The safe operating area represents that electrical region where a transistor performs predictably and retains a high reliability, without causing device destruction or accelerated deterioration. Deterioration or device destruction can occur when operating within the absolute maximum device ratings, as a result of second breakdown (s/b) or excessive thermal dissipation. Typical SOA characteristics are shown in figure 4.7. These collector characteristics are for a single pulse, of a given duration, such that the transistor operates in the linear region and at a case temperature of 25°C. The dc or continuous operation case has the most restrictive SOA curve, while a short single pulse of 1µs duration enables the full device I-V ratings to be exploited. The SOA is basically bounded by the maximum collector Ilc and the collector emitter breakdown voltage V(BR)ceo. In figure 4.7 it will be seen that four distinct operating region limits exist, viz., A to D. A Maximum collector current which is related to allowed current density in the leads and contacts and the minimum gain of the transistor. The maximum lead current is given by I = K w d 2/3 where the diameter d is in mm and Kw depends on the type and length of wire. For lengths greater than 1mm, Kw = 160 for both copper and silver.

B Maximum thermal dissipation, which is related to the absolute maximum junction temperature Tlj , and the thermal resistance or impedance from the virtual junction to the case. -1 In this thermally limited region, the collector power loss is constant and Ic = P Vc . Thus the thermal limit gradient is -1, when plotted on logarithmic axes as in figure 4.7.

I0

Iceo

V(BR)ceo

Icer

V(BR)cer

Ices

V(BR)ces

Icex

V(BR)cex

Icbo

V(BR)cbo

Figure 4.6. Relative magnitudes of npn transistor collector voltage breakdown characteristics, showing first and second breakdown.

At high Vcb voltages, near Va, avalanche multiplication causes a high injection of hole carriers. Thus no base current is required and a β → ∞ condition effectively occurs. With such conditions, equation (4.8) indicates that α0 M → 1 which, upon substitution into equation (4.9), yields Va = Vb m 1- α 0 ≈ V( BR )ceo (V) (4.10) Va becomes the common emitter avalanche breakdown voltage V(BR)ceo which is commonly called the collector emitter sustaining voltage, Vceo(sus).

Limit of forward second breakdown (s/b). This breakdown occurs when the local current C density is too high and a hot spot is created which causes thermal runaway. The physical causes of the high current concentration phenomenon are a fall in electrical potential or instability of lateral temperature distribution in the base area. These occur as a consequence of base-width concentration non-uniformity, a faulty junction or improper chip mounting. A typical s/b characteristic is shown in figure 4.6, and is characterised by a rapid drop in collector -n voltage to the low-impedance area after s/b. The s/b SOA limit can be modelled by I s / b = PV , where n, the gradient in figure 4.7, ranges from 1.5 to 4 depending on the fabrication processes and structures that have been employed. S/b, with a forward-biased base emitter is usually characterised by a short circuit at the emitter periphery, since this area is more forward-biased than central regions because of lateral base resistance effects. S/b, with a reverse-biased base-emitter junction, occurs in the central emitter region because of current focussing to that area as a result of the same lateral base resistance effects. D Maximum collector voltage under worst case conditions. In switching applications the V(BR)ceo limit can be exceeded provided suitable base conditions exist. At turn-off, when the collector current has fallen below Icex, the collector supporting voltage can be increased from V(BR)ceo to V(BR)cex if the proper reverse bias base emitter junction conditions exist. The SOA together with this small extension area form the reverse bias SOA. Turn-on in switching applications can take place from a V(BR)cex condition, provided the collector current rise time is very short, usually much less than 1µs. As the rise time value decreases, the current that can be switched at turn-on increases. Under such conditions a significant portion of Ic can be switched from V(BR)cex. The SOA together with this large switch-on extension area form the forward bias SOA, as shown in figure 4.7.

The SOA is usually characterised for a case temperature of 25°C. In practice much higher case temperatures are utilised and then the power and s/b SOA limits are modified with the aid of the derating curves of figure 4.8. At a given case temperature, above 25°C, power derating is greater than s/b derating. No derating is necessary for case temperatures below 25°C.

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110

4.3.2ii – BJT turn-off time: toff = ts + tfi In order to cut-off a transistor from the saturated state, all the accumulated charges must be neutralised or removed from the base and from the lightly doped n- region of the collector. The turn-off process is started by removing the forward base current Ibf, and applying the reverse base current Ibr. The excess minority carriers, namely holes, in the collector n- region are progressively reduced in the process of providing the collector current. The excess minority carriers in the base are removed by the reverse base current. The reverse base current does not influence the collector n- region recombination process. The period after the cessation of positive base current until the transistor enters the linear region is termed storage or saturation time, ts. Generally, and undesirably, the larger the forward gain βf, the greater the saturation time, ts.

Ic

Figure 4.7. Safe operating area (SOA) bounds of an npn high-voltage power switching transistor including forward and reverse bias SOA. Temperature derating for a case temperature of 75°C is shown.

Figure 4.7 shows the derating, according to figure 4.8, of the dc and 1ms operating loci when the case temperature is increased from 25°C to 75°C. Figure 4.8 indicates that the power limit line B is derated to 71.5 per cent, while the s/b limit line C is reduced to 80 per cent. The slope of the 10µs single pulse limit line indicates that no s/b component exists, thus only power derating need be employed. This is because the pulse period of a few microseconds is short compared to the die thermal constant, whence the rate of local heating is too brief to disperse and cause second breakdown.

Figure 4.9. Defining transistor base and collector current switching times for turn-on and turn-off.

75ºC

Figure 4.8. Power and second breakdown derating versus case temperature.

It is important to note that when a transistor is employed in a switching application, where the device is either cut-off or hard-on, the full SOA bounded by Ic and V(BR)ceo can usually be exploited. As indicated in figure 4.7, provided the collector switching times are of the order of a microsecond or less, no power or s/b derating need be factored. Design is based on total power losses, such that the maximum allowable junction temperature, Tlj is not exceeded. For high reliability and long device lifetime only one electrical limit, either Ic or V(BR)ceo, should be exploited in a given application. 4.3.2

Transistor switching characteristics

If a current pulse is supplied into the base of a common emitter connected transistor, as shown in figure 3.8, the resultant collector current waveform is as shown in figure 4.9. The collector voltage waveform is essentially collector load circuit dependent and therefore is not used to characterise transistor switching. 4.3.2i – BJT turn-on time: ton = td + tri Turn-on consists of a delay time td followed by a current rise time tri. The delay time corresponds mainly to the charging of the base-emitter junction diffusion capacitance. The turn-on delay time can be significantly reduced by increasing the applied rate and magnitude of the forward base current Ibf. The current rise time is related to the effective base zone width and, as the base charge increases because of the base current, the collector current increases.

Optimal turn-off occurs when the emitter junction cuts off, as a result of Ibr, just as the collector junction cuts off and enters the linear region. Thus the collector current fall time can be decreased by increasing the reverse base current immediately after the collector junction has cut off, which monimises the current fall time tfi. In switching applications, operation in the linear region is to be avoided, or at least traversed rapidly, because of the associated high device power losses. Although in the saturated state, with Ibf >> Ic / βf, gives minimum forward gain and losses, this state is not conducive to a rapid turn-off transition to the cut-off region. In switching applications, in order to increase turn-off speed (decrease ts and tfi), the transistor may be held in the quasi-saturation region by reducing and controlling the forward base current magnitude such that the device is on the verge of saturation, Ibf ≈ Ic / βf, but is not in the linear region. The quasi-saturation on-state losses are slightly higher. In the quasi-saturated on-state the collection n- region can be considered as extra series collector circuit resistance, which decreases as the neutral base region penetrates and reduces to zero when saturation occurs. 4.3.3

BJT phenomena

Although the BJT is virtually obsolete as a discrete power switching device for new circuit designs, it has been considered in some detail both in this chapter and chapter 3.2.1. This is because its operating electrical mechanisms explain the major limiting electrical operating factors of all controlled power switching devices. • mosfet: In chapter 3.2.2 the reverse conducting inherent body diode in the MOSFET is part of a parasitic npn transistor. This BJT structure can produce unwanted MOSFET dv/dt turn-on. Notice in figure 3.14a that the source metallization overlaps the p+ well, there-in producing a base to emitter shunting resistor, as shown by Rbe in figure 3.14b. The emitter shunts perform two essential functions, but inadvertently creates a non-optimal diode. o First, the shunt decreases the injection efficiency hence gain of the npn BJT, decreasing the likelihood of a drain dv/dt resulting in sufficient Miller capacitance current to turn-on the parasitic BJT, as considered in chapter 3.2.1.

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Second, by decreasing the BJT gain, the npn section voltage rating is increased from Vceo to Vcer as considered in section 4.3.1. • igbt: In figure 3.16d the equivalent circuit of the IGBT has a parasitic pnp-npn thyristor structure. Once again, the emitter metallization (Rbe) shunts the base to emitter of the npn BJT, helping to avoid latch-up of the SCR section, as modelled by the derivation of equation (3.18). Also the voltage rating of the npn section is increased from Vceo to Vcer. Improved thermal stability also results. Judicious profiling of the transistor sections is essential. • gto thyristor: All the electrical operating mechanisms of the SCR are explainable in terms of BJT mechanisms, including turn-on, turn-off, and thermal stability. Emitter shorts (Rbe shunts) are used extensively to decrease gain, increase thermal stability, and increase voltage ratings and are essential in providing separation in the bi-directional conducting thyristor, as considered in chapter 3.3.4. The GTO thyristor also uses emitter shorts in order to achieve a stable device at turn-off, as shown in figure 3.28.


112

o

C

D B

An understanding of BJT electrical operating mechanisms is fundamental to the design and operation of semiconductor power switching devices, whether principally bipolar operating devices or unipolar devices which have bipolar parasitic structures. 4.4

The power MOSFET

The main electrical attributes offered by power MOSFETs are high switching speeds, no second breakdown (s/b), and high impedance on and off voltage control. MOSFETs, along with IGBTs, have replaced the bipolar junction transistor due to their superior switching performance and simpler gate control requirements. 4.4.1

MOSFET absolute maximum ratings

The basic enhancement mode power MOSFET structure and electrical circuit symbol are shown in figure 3.11. The SOA bounds shown in figure 4.10 is confined by four outer bounds. A The n- epitaxial layer concentration and thickness is the key parameter in specifying the drain high-voltage ratings, such as Vds and Vdg, which increase with temperature at approximately +0.1 per cent/K, as shown in figure 3.13. B One important rating feature of the power MOSFET is that it does not display the s/b that occurs with the bipolar transistor. Figure 4.10 shows the safe operating area for transistors, with the bipolar junction transistor s/b limitation area shaded. The physical explanation as to why MOSFETs do not suffer from s/b is based on the fact that carrier mobility in the channel decreases with increased temperature at -0.6 per cent/K. If localised heating occurs, the carrier mobility decreases in the region affected and, as a consequence, the localised current reduces. This negative feedback, self-protection mechanism forces currents to be uniformly distributed along the channel width and through the silicon die. This property is exploited when paralleling MOSFET devices. As a result of the enlarged SOA, the power MOSFET is generally a much more robust device than its bipolar counterpart. This region is thermally limited, as defined by I = P / V −1 giving the -1 slope on the log-log axes in figure 4.10. C The drain current rating is also related to the epitaxial properties. Its resistance specifies the I d2 Rds (on) power loss, which is limited by the junction to case thermal resistance, Rθ j-c. The continuous, usable drain current above 25°C is thus given by Tl j − Tc (A) Id = (4.12) Rds (on) Rθ j-c

A

Figure 4.10. The safe operating area of the power MOSFET, which does not suffer second breakdown.

4.4.2


The important power MOSFET dynamic characteristics are inter-terminal voltage-dependent capacitance and drain current-switching times. The various MOSFET capacitances are dominant in specifying switching times. 4.4.2i – MOSFET device capacitances Figure 4.11 shows an equivalent circuit for the power MOSFET, extracted from figure 3.14, which includes three inter-terminal, non-linear voltage-dependent capacitances Cgd, Cgs, and Cds. The magnitudes are largely determined by the size of the chip and the cell topology used. Therefore higher current devices inherently have larger capacitances. Electrically, these capacitances are strongly dependent on the terminal drain-source voltage. Manufacturers do not generally specify Cgd, Cgs, and Cds directly but present input capacitance Ciss, common source output capacitance Coss, and reverse transfer capacitance Crss. These capacitances, as a function of drain to source voltage, are shown in figure 4.12a. The manufacturers’ quoted capacitances and the device capacitances shown in figure 4.12b are related according to Ciss = Cgs + Cgd ;

Cds shorted

Crss = Cgd

Coss = Cds +

(F) (F)

Cgs . Cgd Cgs + Cgd

≈ Cds + Cgd

;

Cgs shorted

(4.15)

(4.16) (F)

D When the MOSFET is on, with minimum drain voltage at maximum drain current, it operates in the resistive mode where the drain current is given by 1 (A) Id = Vds (4.13) Rds (on)

The SOA region at high currents and low voltages is thus characterised by a line of slope 1, on logarithmic axes, as shown in figure 4.10. The gate to source voltage Vgs controls the channel and the higher the value of Vgs, the higher the possible drain current. The gate to source is a silicon dioxide dielectric capacitor which has an absolute forward and reverse voltage that can be impressed before dielectric breakdown. Typical absolute maximum voltage levels vary from ±10V to ±40V, as the oxide layer thickness increases and capacitance advantageously decreases.

(4.14)

Figure 4.11. MOSFET equivalent circuit including terminal voltage dependent capacitance and inductance for the TO247 package.

113

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Chapter 4


114

1 – MOSFET turn-on Period I - turn-on delay, td on The gate voltage rises exponentially to the gate threshold voltage VTH according to equation (4.17), that is - t / Cin Rg Vgs (t ) = Vgg [1 - e ] (V) (4.17)

where Cin, the gate input capacitance is approximated by Cgd + Cgs, or Ciss. The drain voltage remains unchanged, that is, it supports the supply voltage Vdd and virtually no MOSFET drain current flows. The turn-on delay time is given by -1

 V  td on = Cin Rg An  1 - Th  (s) (4.18)   V gg   Equations (4.17) and (4.18) can be modified to account for a negative initial gate voltage (as presented in Appendix 4.1), a condition which increases the turn-on delay time, but increases input noise immunity. QT

Figure 4.12. MOSFET capacitance variation with drain-to-source voltage: (a) manufacturers’ measurements and (b) inter-terminal capacitance values.

The measurement frequency is usually 1 MHz and any terminals to be shorted are connected with large, high-frequency capacitance, so as to present a short circuit at the measurement frequency. Device capacitances are predominant in specifying the drain current switching characteristics, particularly Cgd with its large capacitance variation at low drain voltage levels. 4.4.2ii – MOSFET switching characteristics The simple single-ended MOSFET circuit with an inductive load LL in figure 4.13, can illustrate how device capacitances influence switching. The MOSFET gate is driven from a voltage source whose output impedance is represented by Rg, which also includes any MOSFET gate series internal resistance. The dc input resistance of a power MOSFET is in excess of 1012 Ohms and when used as a switch, the power required to keep it on or off is negligible. However energy is required to change it from one state to the other another, as shown in figure 4.14. This figure shows the relationship between gate charge, gate voltage, and drain current for a typical MOSFET. The initial charge Qgs is that required to charge the gate-source capacitance and Qgd is that required to supply the drain-gate Miller capacitance. For a given gate charging current, switching speed is proportional to gate voltage. The gate charge required for switching, and hence switching speed, is not influenced significantly by the drain current magnitude, and not at all by the operating temperature. The switching speed is directly related to time delays in the structure because of the channel transit time of electrons. External to the device, the switching time is determined by the energy available from the drive circuit. A gate drive design example based on gate charge requirement is presented in chapter 7.1.2. The switching transients can be predicted for an inductive load, when the load is the parallel inductor and diode, with no stray unclamped inductance, as shown in figure 4.13. It is assumed that a steady load current IL flows. The various turn-on and turn-off periods shown in figure 4.15 are related to the sequential charging periods shown in figure 4.14. Any gate circuit inductance is neglected.

Vgg

Ig t Id

IL Vdd

Vds

t

Figure 4.14. Typical relationships between gate charge, voltage, and current and magnitude of drain current and voltage being switched.

Period II - current rise, tri LL

Drain current commences to flow in proportion to the gate voltage as indicated by the transconductance characteristics in figure 3.12a. The gate voltage continues to rise according to equation (4.17). The drain voltage is clamped to the rail voltage Vdd and the drain current rises exponentially to the load current level IL, according to - t / Rg Cin I d (t ) = g fs (Vgg − VTh ) [1 - e ] (A) (4.19) The current rise time tri can be found by equating Id = IL in equation (4.19).  g fs (V gg −VTh )   t ri = R g C in A n   g fs (V gg −VTh ) − I L   

Figure 4.13. MOSFET basic switching circuit used to demonstrate current switching characteristics.

(4.20)

Period III - voltage fall, tfv When the drain current reaches the load current level, the drain voltage will fall from Vdd to the low onstate voltage. This decreasing drain voltage produces a feedback current via Cgd to the gate, which must

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be provided by the gate drive. This feedback mechanism is called the Miller effect and the effective gate input capacitance increases to Cin = Ciss + (1 - Av)Cgd where Av = ∆Vds /∆Vgs. For a constant load current, from figure 3.12a, the gate voltage remains constant at Vgs = VTh + I L / g fs

(V)

(4.21)

as shown in figure 4.15b. Since the gate voltage is constant, the Miller capacitance Cgd is charged by the constant gate current V - Vgs V - (VTh + I L / g fs ) I g = gg = gg (A) (4.22) Rg Rg and the rate of change of drain voltage will be given by dVgd dVds I = = g dt dt Cgd

(V/s)

(4.23)

Vds (t ) = Vdd -

Cgd

116

2 – MOSFET turn-off Period V - turn-off delay, td off The MOSFET is fully on, conducting the load current IL, and the gate is charged to Vgg. The gate voltage falls exponentially from Vgg to VTh + IL/ gfs according to -t / R C Vgs (t ) = Vgg e g in (V) (4.26)

in a time given by td off = Rg Cin An

Vgg VTh + I L / g fs

(4.27)

(s)

This delay time can be decreased if a negative off-state gate bias is used. The drain conditions are unchanged. Period VI - voltage rise, trv

that is Ig


(V)

t

(4.24)

The drain voltage decreases linearly in time and the voltage fall time is decreased by increasing the gate current. Assuming a low on-state voltage, the voltage fall time tfv is given by t fv = Vdd Cgd / I g = Vdd Cgd Rg / (Vgg − VTh ) (s) (4.25)

The drain voltage rises while the drain current is fixed to the load current level, IL. Accordingly the gate voltage remains constant and the gate current is given by V + I L / g fs (4.28) I g = Th (A) Rg This current discharges the Miller capacitance according to I dVds dVdg = = g dt dt Cgd

Period IV

Once the drain voltage reaches the low on-state voltage, the MOSFET is fully on and the gate voltage increases exponentially towards Vgg.

Vds (t ) =

Thus

Ig Cgd

t

where the low on-state voltage has been neglected. The voltage rise time trv is given by C V trv = gd dd Ig

(V/s)

(4.29)

(V)

(4.30)

(4.31)

(s)

and is decreased by increasing the gate reverse current magnitude. The drain voltage rises linearly to the dc supply Vdd. Period VII - current fall, tfi

When the drain voltage reaches the supply rail, the load current in the MOSFET begins to decrease, with load current being diverted to the diode Df. The gate voltage decreases exponentially according to -t / R C Vgs (t ) = (VTh + I L / g fs ) e g in (V) (4.32) and is mirrored by the drain current -t / R C I d (t ) = ( I L + g fsVTh ) e g in - g fsVTh

ig

ig

(A)

(4.33)

The current fall time tfi is given by Id = 0 in equation (4.33) or when the gate-source voltage reaches the threshold voltage, that is, from equation (4.32)  IL  (4.34) t fi = Rg Cin An  1 + (s)   g fs VTh   Period VIII – off-state The MOSFET drain is cut-off and the gate voltage decays exponentially to zero volts according to -t / R C Vgs (t ) = VTh e (V) (4.35) g in

Based on the total gate charge QT delivered by the gate source Vgg, shown in figure 4.14, the power dissipated in the MOSFET internal gate resistance, hence contributing to device losses, is given by Rg int (W) (4.36) PG ( Rint ) = Vgg QT f s Rg int + Rg ext Example 4.1:

Figure 4.15. Distinct switching periods of the MOSFET with an inductive load at: (a) (b) (c) (d) comprising turn-on; (e) (f) (g) (h) forming turn-off.

MOSFET drain characteristics

A power mosfet with Cgs=1nF, Cgd=200pF, gfs=4 and the threshold voltage is 3V, is used to switch a 200V dc 20A load. If the gate is sourced from a 15V voltage source via a 10Ω gate resistance, what is the maximum rate of rise of drain current and voltage?

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Solution


118

Period VII - current fall, tfi

The current falls in two stages, the first, phase VII, due to MOSFET action, as are the previous two phases (periods V and VI). As with the conventional MOSFET the current falls rapidly as the MOSFET section current, shown in figure 4.16b reduces to zero.

From equation (4.21), during turn-on:

i D = g fs (V gs −VTh )

whence

dV gs di D = g fs dt dt

From equation 4.23

(C

gs

+ C gd

)

V

dV gs V −V gs = I g = gg dt Rg

VI

VII

VIII

Combining these equations

dV gs Ig V gg −V gs di D = g fs = g fs =g dt dt (C gs + C gd ) fs (C gs + C gd ) Rg The maximum drain di/dt occurs at the gate threshold voltage, that is

di D dt

= max

= =

(C

gs

(C

gs

g fs g fs I gmax = (V −V min ) + C gd ) (C gs + C gd ) Rg gg gs g fs

+ C gd ) R g

(V

gg

4

−VTh )

(1nF + 200pF ) × 10Ω

(15V − 3V ) = 4kA/µs

From equation (4.23)

dV gd dVds I V −V gs = = g = gg dt dt C gd C gd R g

(V/s)

The maximum drain dv/dt occurs at the gate threshold voltage, that is I max V −V gsmin dVds = g = gg

dt

C gd

max

C gd R g

V −VTh = gg C gd R g =

15V − 3V = 6kV/µs 200pF × 10Ω ♣

4.5

The insulated gate bipolar transistor

4.5.1

IGBT switching

The IGBT gate charge characteristics for switching and the switching waveforms are similar to those of the MOSFET, shown in figures 4.14 and 4.15 respectively, whilst the I-V on and off state characteristics are similar to the BJT. The collector switching characteristics depend on the injection efficiency of the collector p+ emitting junction. The higher the injection efficiency, the higher the pnp transistor section gain and the lower the on-state voltage. The poorer the injection efficiency, the more the characteristics resemble a MOSFET. The turn-on waveforms and mechanisms are essentially those for the MOSFET shown in figure 4.15. Figure 4.16 shows IGBT turn-off which has components due to MOSFET and BJT action. As with the MOSFET, distinct turn-off stages exist when switching an inductive load. Period V - turn-off delay, td off The gate voltage falls to a level determined by the gate threshold, VTH, the forward transconductance, gfs and the MOSFET section current level. Period VI - voltage rise, trv

As the collector voltage rises the collector current remains constant, hence the gate voltage remains constant while charging the Miller capacitance. For a high gain pnp section the voltage rise time is virtually independent of gate resistance, while for an IGBT closely resembling a MOSFET the voltage rise is gate current magnitude dependent.

Figure 4.16. IGBT: (a) turn-off waveforms and (b) equivalent circuit during turnoff.

Period VIII – current tail time With the gate voltage at the threshold level, the pnp transistor section turns off in a Vceo mode, phase VIII. A relatively low-magnitude, lengthy current tail results which is dependent on the pnp transistor section minority carrier lifetime in the n base and the injection efficiency of the p+ collector region.

The switching frequency and current rating of an IGBT are both limited by the minimum of the package dissipation limit (as with any other semiconductor device) and a factor solely dependant on the switching times at turn-on and turn-off. As the switching frequency increases, the current rating decreases. The MOSFET upper frequency is restricted solely by losses, that is, temperature. 4.5.2

IGBT short circuit operation

Under certain electrical conditions the IGBT may be subjected to short circuits, and safely turned off with out damage. Two different short circuit conditions are characterised: I. II.

IGBT turn-on into a pre-existing load short circuit Subsequent to IGBT turn-on, a short circuit load

condition occurs during the on-state period I. Pre-existing short circuit at turn-on The collector electrical characteristics are determined by the gate drive parameters and conditions. As the collector voltage falls, the collector current di/dt is determined by the stray inductance, characterised at less than 25µH. In this fault mode the IGBT is characterised for up to ten times the rated current, provided the IGBT is turned off within 10us, but at a slower rate than normal.

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II. Short circuit arising during the normal on-period When a load short circuit occurs during the IGBT on period, the collector current rises rapidly and is determined by the supply voltage Vs and stray inductance Ls according to dirise /dt = Vs /Ls. The collector voltage de-saturates and as the collector voltage rise towards the supply Vs the resultant dv/dt produces a Miller capacitance charging current, which flows into the gate circuit. Depending on the gate drive impedance, the gate voltage rises, which adversely allows higher collector current. When turn-off is initiated, by reducing the gate voltage to below the threshold level, the resultant collector current fall produces a high voltage across the stray inductance, VLs = Ls difall /dt, which adds to the collector voltage which is already near the supply rail Vs. Because of this over voltage, this mode of short circuit turn-off is more severe than turning off from a pre-existing short circuit. The maximum allowable short circuit current at turn-off is dependant on the gate voltage and reduces from ten times rated current at a gate voltage of 18V down to five times rated current at 12V. The short circuit must be commutated within 10us at a slower than normal rate so as to ensure the over voltage due to stray inductance remains within rated voltage limits. Repetitive short circuits are restricted to a frequency of less than one Hertz and can only accumulate to 1000 before device deterioration accelerates; both mechanical bonding and electrical. Stress during the fault period can be reduced if the gate voltage is clamped so that it cannot rise during the Miller capacitance charge period. A Zener diode (plus a reverse series diode if reverse gate bias is used) across the gate to emitter provides low inductance gate voltage clamping, but the Zener standby to clamping voltage ratio of 1:1.4 limits clamping effectiveness. The preferred method is to clamp the gate to the gate supply voltage by a Schottky diode between the gate (diode anode) and gate positive supply (diode cathode). Judicious gate supply ceramic capacitance decoupling will minimise loop inductance which otherwise would deteriorate clamping effectiveness. A difficulty arises when attempting to utilise the 10µs short circuit capabilities of the IGBT. To improve device robustness, short circuit turn-off is staged, or slowed down. It is prudent to utilise the over current capability of the IGBT in order to reduce nuisance tripping or to briefly ignore capacitor charging which are not true faults. A difficulty arises when a demand pulse is significantly less than 10µs. The gate drive must be able to cater for sub 10µs pulses with normal turn-off yet differentiate 10µs delayed slow turn-off when a short circuit fault is serviced.


120

The repetitive peak thyristor voltage rating is that voltage which the device will safely withstand in both the forward off-state VDRM, and reverse direction VRRM, without breakdown. The voltage rating is primarily related to reverse leakage or forward blocking current IRRM and IDRM respectively, at a given junction temperature, usually 125°C. Since forward blocking current doubles with every 10K rise in junction temperature Tj, power dissipation increases rapidly with Tj, which may lead to regenerative thermal runaway, turning the device on in the forward direction. Current related maximum ratings reflecting application requirements include • peak one cycle surge on-state current ITSM • repetitive and non-repetitive di/dt • I2t for fusing. The maximum junction temperature can be exceeded during non-recurrent over-current cycles. The maximum non-repetitive on-state surge current is generally quoted for one 10 millisecond sinusoidal period at Tlj . Any non-recurrent rating can be tolerated only a limited number of times before failure results. Such non-recurrent ratings are usually specified to allow fuse and circuit breaker short-circuit protection. The I2t rating for a 10ms period is another parameter used for fuse protection, where I is non-repetitive rms current. When used in 60Hz systems, the ratings are specifies with respect to 8.33ms If the device is turned on into a fault, the initial current-time relationship, di/dt, during turn-on must be within the device’s switching capability. In cases where the initial di/dt is rapid compared with the active plasma area-spreading velocity of 50 µm/µs, local hot spot heating will occur because of the high current densities in those areas that have started to conduct. A repetitive di/dt rating is also given for normal operating conditions, which will not lead to device deterioration. This repetitive di/dt rating will be specified for a given initial blocking voltage and peak forward current. Certain gate drive conditions are specified and the device must survive for 1000 hours.

Table 4.1: The IGBT Characteristics Comparison with the BJT and MOSFET Features

BJT

MOSFET

IGBT

Drive Method

Current

Voltage

Voltage

Drive Circuit

Complex

Simple

Simple

Low

High

High

Input Impedance Drive Power Switching Speed S.O.A. Saturation Voltage Series Avalanche Operation

4.6

High

Low

Low

Slow (µs)

Fast (ns)

Middle

Narrow

Wide

Wide

Low

High

Low

excellent

poor

poor

The thyristor

Most of the thyristor ratings and characteristics to be considered are not specific to only the siliconcontrolled rectifier, although the dynamic characteristics of the gate turn-off thyristor are considered separately. 4.6.1

SCR ratings

The fundamental four layer, three junction thyristor structures and their basic electrical properties were considered in chapter 3.3. 4.6.1i - SCR anode ratings Thyristors for low-frequency application, such as in 50-60 Hz and 300-360Hz ac supply systems, are termed converter-grade thyristors. When a higher switching frequency is required, so-called gate commutated devices like the GTO and GCT are applicable. Such devices sacrifice voltage and current ratings for improved self-commutating capability.

IG T , V G T

IG , V G

(a)

(b)

Figure 4.17. Thyristor gate ratings illustrating: (a) the preferred operating region and (b) minimum gate requirements and their temperature dependence.

4.6.1ii - SCR gate ratings The gate ratings usually specified are • peak and mean gate power, PGM and PG • peak forward and reverse gate to cathode voltage, VGFM and VGRM • peak forward gate current, IFMG. These gate ratings are illustrated in figure 4.17. The peak gate power rating is obtained by using a low duty cycle pulse, with a mean power that does not exceed PG. The reverse gate voltage limit, VGRM, is specified by the avalanche voltage breakdown limit of the reverse-biased gate-to-cathode junction. Figure 4.17 not only shows limit ratings, it also indicates the preferred gate voltage and current, and the minimum requirements which will ensure turn-on at different junction temperatures.

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4.6.2

Static characteristics

The static anode voltage-current characteristics of a thyristor are similar to those of a diode. Gate commutated thyristors tend to have higher on-state voltages for a given current than comparable converter-grade devices. This higher on-state voltage is one of the trade-offs in improving the switching performance. 4.6.2i - SCR gate trigger requirements Below a certain gate voltage, called the gate non-trigger voltage VGD, the manufacturer guarantees that no device will trigger. This voltage level is shown in figure 4.17b. The hatched insert area in figure 4.17a (figure 4.17b) contains all the possible minimum trigger values (IGT, VGT) for different temperatures, that will result in turn-on. The gate requirements (IGT, VGT) have a negative temperature coefficient as indicated in figure 4.17b. To ensure reliable turn-on of all devices, independent of temperature, the trigger circuit must provide a dc signal (IG, VG) outside the shaded area. This area outside the uncertainty area, but within the rating bounds, is termed the preferred gate drive area. An increase in anode supporting voltage tends to decrease the gate drive requirements. But if the gate signal is a pulse of less than about 100µs, the turn-on (IG, VG) requirement is increased as the pulse duration is decreased. The gate current increase is more significant than the voltage requirement increase. Typically, for a pulse reduced from 100µs to 1µs, the voltage to current increase above the original requirement is 2:10 respectively. This increased drive requirement with reduced pulse time is accounted for by the fact that some of the initial gate p-region charge recombines. When the free charge reaches a certain level the device triggers. Thus, to get the required charge into the gate in a relatively short time compared with the recombination time requires higher current, and hence higher voltage, than for dc triggering. 4.6.2ii – SCR holding and latching currents If the on-state anode current drops below a minimum level, designated as the holding current IH, the thyristor reverts to the forward blocking state. This occurs because the loop gain of the equivalent circuit pnp-npn transistors falls below unity and the regenerative hold-on action ceases. The holding current has a negative temperature coefficient; that is, as the junction temperature falls, the device holding current requirement increases. The holding current is typically about 2% of the rated anode current, and increases as switching performance is improved (and on-state voltage increases). A somewhat higher value of anode on-state current than the holding current is required for the thyristor to latch on initially (ILatch >IH). If this higher value of anode latching current ILatch is not reached, the thyristor will revert to the blocking state as soon as the gate trigger signal is removed. After latch-on, however, the anode current may be reduced to the holding current level, without turn-off occurring. These two static current properties are shown in the I-V characteristics in figure 3.22. With inductive anode circuits, it is important to ensure that the anode current has risen to the latching current level before the gate turn-on signal is removed. Continuous gate drive avoids this inductive load problem but at the expense of increased thyristor gate power losses. 4.6.3


The main thyristor dynamic characteristics are the turn-on and turn-off switching intervals, which are associated with the anode and gate circuit interaction. 4.6.3i – SCR anode at turn-on Turn-on comprises a delay time td and a voltage fall time tfv, such that the turn-on time is ton = td + tfv. The turn-on delay time for a given thyristor decreases as the supporting anode voltage at turn-on is increased. The delay time is also decreased by increased gate current magnitude. The gate p-region width dominates the high gate current delay time characteristics while carrier recombination is the dominant factor at low gate current levels. The anode voltage fall time is the time interval between the 90 per cent and 10 per cent anode voltage levels. The associated anode current rise characteristics are load dependent and the recurrent di/dt limit must not be exceeded. As introduced in chapter 3.3.1, a thyristor can be brought into conduction by means of an anode impressed dv/dt, called static dv/dt capability, even though no gate external current is injected. The anode voltage ramp produces a displacement current according to i = dQ/dt as the central junction scl charges and its width increases. The resultant displacement current flows across the cathode and anode junctions causing minority carrier emission and, if sufficient in magnitude, turn-on occurs. Static dv/dt capability is an inverse function of device junction temperature and is usually measured at Tlj .

Chapter 4


122

4.6.3ii – SCR anode at turn-off As analysed in chapter 3.3.1, once a thyristor is turned on, it remains latched-on provided • the holding current remains exceeded • it is forward biased. If the supply voltage is ac, a thyristor will turn off after the supply voltage has reversed and the anode current attempts to reverse. The thyristor is thus reverse-biased and this turn-off process is called line commutation or natural commutation, as defined in chapter 6.3.4. If the supply voltage is dc and the load is a series L-C resonant circuit, the anode current falls to zero when the capacitor is charged. The load current falls below the holding current level and the SCR turns off. This is termed load commutation, which is a form of load resonant switching as defined in 6.3.3. In thyristor applications involving dc supplies and resistive/inductive loads, a thyristor once on will remain on. Neither the supply nor the load is capable of reducing the anode current to below the holding current level, or producing a reverse bias across the thyristor. Such a thyristor can be turned off only if the anode current is interrupted or forced below the holding current level. External circuitry, called a commutation circuit, is employed to accomplish turn-off, by reverse-biasing the thyristor and reducing the anode current to near zero. This external turn-off approach, now obsolete, is called thyristor forced commutation. A topological variation of the forced commutated circuitry method is called resonant link commutation. The gate turn-off thyristor eliminates the need for this external commutation circuitry since the GTO can be commutated from its gate using reverse gate current.

4.7

The gate turn-off thyristor

In essence, the gate turn-off (GTO) thyristor has similar ratings and characteristics to those of the conventional converter grade SCR, except those pertaining to turn-off. Both GTO turn-on and turn-off are initiated from the gate, hence the power-handling capabilities of the GTO gate are much higher than those of SCR devices. 4.7.1

Turn-on characteristics

Because of the higher p1 gate region concentration, the GTO thyristor holding current level and gate trigger requirements are somewhat larger than those of the conventional SCR. Higher anode on-state voltages also result. At low anode current levels, a steep trailing edge at the end of the gate on-pulse may cause the GTO to unlatch even though the anode current is above the dc holding current level. For this reason, together with the fact that the cathode comprises many interdigitated islands, a continuous, dc gate on-drive is preferred. Continuous gate current prevents any cathode islands from falling out of conduction should the anode current be reduced to near the holding current level. If cathode islands should turn off prematurely and the anode current subsequently rise, the GTO no longer has its full current handling capability and it could overheat specific islands, leading to device destruction. With very high voltage GTO’s, turn-on is like that of a high voltage npn transistor which has low gain, limiting the initial rate of rise of anode current, until the regenerative latching action has occurred. Hence an initial, high current of up to six times the steady-state gate requirement is effective for a few microseconds. 4.7.2

Turn-off characteristics

Before commencing turn-off, a minimum on-time of tens of microseconds must be observed so that the principal current may distribute uniformly between the cathode islands. This is to ensure that all cells conduct, such that turn-off occurs uniformly in all cells, rather than being confined to a few cells, where the current to be commutated may be higher than individual cells can survive. The anode current of a GTO in the on-state is normally turned off via a low voltage source, negative gate current, IRG. The negative gate current IGQ, which is just sufficient to turn-off the on-state current IT is defined as the minimum turn-off current. Turn-off amplification (equation 3.21) is defined as βQ = I TGQ / I GQ (4.37) where βQ is related to the internal construction of the GTO thyristor. Figure 4.18 illustrates typical gate and anode turn-off waveforms for the GTO. Application of reverse gate current causes the anode current to reduce after a delay period ts. This delay time is decreased as the reverse gate current diGQ/dt increases; that is, as IRGM increases and ts decreases. Increased anode on-state current or junction temperature increases the delay time and turn-off time.

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Chapter 4

The reverse gate current prevents cathode injection and the anode current rapidly falls to the storage current level, Itail. The subsequently slow current fall time, ttail, is due to charges stored in regions other than the gate and cathode that are not influenced by the reverse gate current and must decrease as a result of natural recombination, producing a decaying principal anode current. Anode n+ shorts are used to accelerate the recombination process, reducing both storage current and storage time, but at the expense of reverse blocking ability and on-state voltage. Avalanche of the cathode junction (typically 20V) is acceptable during turn-off for a specified time. Reverse gate bias should be maintained in the off-state in order to prevent any cathode injection.

VA, IA

PFQ

Appendix: Effects on MOSFET switching of negative gate drive

The effects of negative gate voltage on MOSFET turn-on and turn-off delays, which were analysed in section 4.4.2, are given by

>IH

Vgs (t ) = (Vgg - Vgg - ) [1 - e

VA(t)

td on = Rg Cin An

IA(t)

td off = Rg Cin An

- t / Cin Rg

] + Vgg -

Vgg − Vgg − Vgg − VTH

Vgs (t ) = (Vgg - Vgg − ) e

- t / Rg Cin

+ Vgg −

Vgg − Vgg − VTH + I L / g fs − Vgg −

(V)

(4.39)

(s)

(4.40)

(V)

(4.41)

(s)

(4.42)

T

toff > toff min

ton > ton min

Reading list See Chapter 3 reading list Van Zeghbroeck, B., Principles of Semiconductor Devices, //ece-www.colorado.edu/~bart/book, 2004.

Power device manufacturers

Vbr

Figure 4.18. Schematic representation of GTO thyristor turn-off waveforms.

After turn-off some dispersed charges still exist. A minimum off-time of the order of tens of microseconds is needed for these charges to recombine naturally. This time increases with increased blocking voltage rating. If a turn-on were to be initiated before this recombination is complete, the area of un-combined charge will turn-on first, resulting in a high di/dt in a confined area, which may cause a hot spot and possibly destruction. During the storage and fall time, power loss PRQ occurs as illustrated in figure 4.18 and is given by T

1 (4.38) (W) VA (t ) I A (t )dt T ∫0 where T = t gq + ttail . The cathode junction loss, due to the gate turn-off reverse current can also be incorporated, which may become significant as the turn-off gain reduces to unity. PRQ =

124

The actual anode voltage turn-off waveform is dependent on the load circuit. Care is needed in preventing excessive loss at turn-off, which can lead to device destruction. One technique of minimising turn-off loss is to increase the rate at which the reverse gate current is applied. Unfortunately, in reducing the turn-off time, the turn-off current gain βQ is decreased, from typically 25 to 3. The anode turn-off voltage VA(t) in figure 4.18 assumes a capacitive turn-off snubber is used. Such a capacitive switching aid circuit is not essential with the GCT, which uses unity reverse gain at turn-off, as considered in chapter 3.3.5. 4.8

PRQ


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Cooling of Power Switching Semiconductor Devices

Chapter 5

The one-dimensional model for general molecular (non-radiation) heat transfer is given by δT δT + ρ m AA (W) (5.2) Pd = −λ A δA δt where δT =T2 -T1 or ∆T, is the temperature difference between regions of heat transfer λ is thermal conductivity, W/m K, see Appendix 5.24 ρm is density of the heatsink material cp is specific heat capacity, J/kg K, such that ∆T = W/mcp (W is energy, m is mass) A is distance (thickness). Equation (5.2) shows that the thermal power generated Pd is balanced by the stored thermal power (first term on the right hand side) and the thermally dissipated power (second term on the right hand side).

5

Conduction heat transfer Conductive heat transfer occurs when energy exchange takes place, by direct impact of molecules, from a high temperature region to a low temperature region. Conductive heat loading on a system may occur through lead wires, mounting screws, etc., which form a thermal path from the device being cooled to the heat sink or ambient environment.


Semiconductor power losses are dissipated in the form of heat, which must be transferred away from the switching junction, if efficient switching is to be maintained. The reliability and life expectancy of any power semiconductor are directly related to the maximum device junction temperature experienced. It is therefore essential that the thermal design determine accurately the maximum junction temperature from the device power dissipation. Every 10°C junction temperature decrease, doubles device lifetime. i. Heat load The heat load may be active or passive, then there is a combination of the two. An active load is the heat dissipated by the device being cooled. It is generally equal to the input power to the device, for example, P = V × I = I 2 × R = V 2 / R . Passive heat loads are indirect, are parasitic in nature, and may consist of radiation, convection or conduction. Heat energy, due to a temperature difference, can be transferred by any of, or a combination of, three mechanisms, viz., • Convection - heat transferred to a moving fluid which takes the heat away • Conduction - heat flows through a thermal conducting material, away from the heat source • Radiation - heat flow by long-wave electromagnetic radiation, e.g. infrared. Electromagnetic thermal radiation heat transfer When two objects at different temperatures come within proximity of each other, heat is exchanged between them. Electromagnetic wave propagation, radiation is emitted from one object and absorbed by the other. As a result of the temperature difference, the hot object experiences a net heat loss and the cold object undergoes a net heat gain. This is termed thermal radiation. Radiation heat loads are usually considered insignificant when the system is operated in a gaseous environment since other passive heat loads are usually greater. Radiation loading is usually significant in systems with small active loads and large temperature differences, especially when operating in a vacuum environment, where convection processes are absent. Electromagnetic thermal radiation heat loading (for a grey body, ε < 1) is given by Pd = σ ε A (T 14 − T 24 ) where Pd is the rate of radiated heat transfer (that is, the power dissipated), W σ is the Stefen-Boltzmann constant (5.667×10-8 W/m2K4) ε is a surface property, termed emissivity, 0 ≤ ε ≤ 1, see Table 5.6 and Appendix 5.25 A is the surface area involved in the heat transfer, m2 T is absolute temperature, K The ideal emitter, or black body, is one which gives off radiant energy with ε = 1 in equation (5.1).

BWW

126

(5.1)

Assuming steady-state heat dissipation conditions, then δ T / δ t = 0 in equation (5.2). Conduction through a homogeneous solid, from Fourier’s law of heat conduction, is therefore given by Pd =

λ A

A ∆T

(W)

(5.3)

Convection heat transfer When the temperature of a fluid (a gas or liquid) flowing over a solid object differs from that of the object surface, heat transfer occurs. The amount of heat transfer varies depending on the fluid flow rate. Convective heat loads are generally a result of natural (or free) convection. This is the case when gas flow is not artificially created as by a fan or pump (forced convection), but rather occurs naturally from the varying density in the gas caused by the temperature difference between the object being cooled and the gas. Heat transfer processes that involve change of phase of a fluid (for example evaporation or condensation) are also considered to be convection. The convective loading is a function of the exposed area and the difference in temperature between the load and the surrounding gas. Convective loading is usually most significant in systems operating in a gaseous environment with small active loads or large temperature differences. Convection heat transfer through a fluid or air, under steady-state conditions in equation (5.2), is given by Newton’s law of cooling, that is Pd = h A ∆T (W) (5.4) The convection heat transfer coefficient h (= λ / A ), W/m2K, depends on the heat transfer mechanism used and various factors involved in that particular mechanism. It is not a property of the fluid. Natural or free convection is essentially still to slightly stirred air with h values ranging from 1 to 25. Forced convection is air moved by a fan or other active method, giving h values range from 10 to 100. Values for forced liquid convection are 50 to 20,000, while the range for boiling and condensation is 2,500 to 100,000. For natural vertical convection in free air, the losses for a plane surface may be approximated by the following empirical formula ∆T 5 ∆T (W) = 1.35 A 4 ∆T = hA∆T A A where ℓ is the vertical height in the direction of the airflow and h is of the form ¼  ∆T  h =K    A  Two cases occur for forced airflow, and the empirical losses are

Pd = 1.35 A 4

•

(5.6)

for laminar flow v A ∆T A

Pd = h A ∆T = 3.9

•

(5.5)

(W)

(5.7)

(W)

(5.8)

for turbulent flow

v4 A ∆T A where v is the velocity of the vertical airflow. Pd = h A ∆T = 6.0

5

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Chapter 5

Combined convection and conduction heat transfer Heat Loss (or gain) - through the walls of an insulated container (combined convection and conduction, estimation) is ∆T Pd = A × A /λ + 1 /h where Pd is the heat lost or gained, W ℓ is the thickness of insulation, m λ is the thermal conductivity of the insulation material, W/m K A is the outside surface area of the container, m2. h is the convection heat transfer coefficient of the surface material, W/m2 K ∆T= To/s - Ti/s To/s is the outside temperature, °C Ti/s is the inside temperature, °C ii. Transient heating Some designs require a set amount of time to reach the desired temperature. The estimated time required to heat (or cool) an object (also known as Newton’s Law of Cooling) is m × c p × ∆T t =

P

Pd

hA

For radiation, from equation (5.1), the effective thermal resistance of radiation is ∆T 1 1 Rθ = = = Pd σε A × (T 1 + T 2 ) (T 12 + T 22 ) hr A

(5.13)

(5.14)

2

where the radiation heat transfer coefficient, hr, in W/m K, is 3 hr = σε × (T 1 + T 2 ) (T 12 + T 22 ) ≈ 4 × σε ×T mean

(5.15)

where Tmean is the arithmetic mean of T1 and T2, specifically ½( T1 + T2). 5.1

Thermal resistances

A general thermal dissipation model or thermal equivalent circuit for a mounted semiconductor is shown in figure 5.1. The total thermal resistance from the virtual junction to the open air (ambient), Rθ j-a, is R × ( Rθ c-s + Rθ c-a ) (5.16) Rθ j-a = Rθ j-c + θ c-a (K/W) Rθ c-a + Rθ c-s + Rθ s-a

Generally, when employing heat sinking, Rθ c-a is large compared with the other model components and equation (5.16) can be simplified to three series components: Rθ j-a = Rθ j-c + Rθ c-s + Rθ s-a (K/W) (5.18)

)

Pto is the initial heat pumping capacity when the temperature difference across the cooler is zero. Ptt is the heat pumping capacity when the desired temperature difference is reached and heat-pumping capacity is decreased. Heat loading may occur through one or more of four modes: active, radiation, convection or conduction. By utilizing these equations, the heat load can be estimated. iii. Thermal resistance It is generally more convenient to work in terms of thermal resistance, which is defined as the ratio of temperature change to power. Thermal capacity is the reciprocal of thermal resistance. For conduction, from equation (5.4), thermal resistance Rθ is ∆T 1 A (5.9) Rθ = (K/W) = = Pd hA λ A where the conduction thermal heat transfer coefficient, h, is

h=

For convection, from equation (5.4), the effective thermal resistance is ∆T 1 Rθ = =

128

In applications where the average power dissipation is of the order of a watt or so, power semiconductors can be mounted with little or no heat sinking, whence Rθ j-a = Rθ j-c + Rθ c-a (K/W) (5.17)

P is the mean heat added (or being removed) from the object, W, watts m is the mass (weight) of the object, kg (density x volume) cp is the specific heat of the object material, J/kg K t is the time required to cool down (or heat up) the object in seconds ∆T = To – Tf To is the starting temperature, °C Tf is the final temperature, °C P = ½ Pt o + Ptt

(


λ

(5.10)

A The average power dissipation Pd and maximum junction temperature Tl j , in conjunction with the ambient temperature Ta, determine the necessary heat sink, according to equation (5.9) Tl − Ta (W) (5.11) Pd = j Rθ j-a

where Rθ j-a is the total thermal resistance from the junction to the ambient air. The device user is restricted by the thermal properties from the junction to the case for a particular package, material, and header mount according to Tl − Tc (W) (5.12) Pd = j Rθ j-c where Tc is the case temperature, K and Rθ j-c is the package junction-to-case mounting thermal resistance, K/W. An analogy between the thermal equations and Ohm’s law and Kirchhoff’s laws is often made to form models of heat flow. The temperature difference ∆T could be thought of as a voltage drop ∆V, thermal resistance Rθ corresponds to electrical resistance R, and power dissipation Pd is analogous to electrical current I. [viz., ∆T = Pd Rθ ≡ ∆V = IR]. See Table 5.10.

virtual junction

Tjunction

package case at mount

Tcase

heatsink

Theatsink

ambient

Tambient

Rθ c-a Rθ j-c Rθ c-hs

Rθ hs-a

Figure 5.1. Semiconductor thermal dissipation equivalent circuit.

5.2

Contact thermal resistance, Rθ c-s

The case-to-heat-sink thermal resistance Rθ c-s (case means the device thermal mounting interface surface) depends on the package type, interface flatness and finish, mounting pressure, and whether thermal-conducting grease and/or an insulating material (thermal interface material, TIM) is used. In general, increased mounting pressure decreases the interface thermal resistance, and no insulation but thermal grease results in minimum Rθ c-s. Common electrical insulators are mica, aluminium oxide, and beryllium oxide in descending order of thermal resistance, for a given thickness and area. Table 5.1 shows typical contact thermal resistance values for smaller power device packages, with various insulating and silicone grease conditions. Silicon based greases are best, for example Assmann V6515, spread at a thickness of 100µm to 150µm, on both surfaces. Grease in excess of this will be squeezed out under clamping pressure. Initial grease thermal resistance decreases slightly after a few normal deep thermal cycles.

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Chapter 5

Table 5.1: Typical case-to-heat-sink thermal resistance value for various small packages

Package

Rθc-s (K / W)

Insulating washer

Silicone grease with without 0.10 0.3 0.7-0.8 1.25-1.45 0.5-0.7 1.2-1.5

No insulating washer Teflon Mica (50 -100 µm) No insulating washer Mica (50 -100 µm) No insulating washer Mica (50 -100 µm) No insulating washer Mica (50 -100 µm)

TO-3 TO-220 TO-247 SOT-227 ISOTOP

1.5-2.0 4.0-6.0 0.4-1.0 1.2-1.5 0.3-0.4 1.0-1.2

0.3-0.5 2.0-2.5 0.1-0.2 0.5-0.7 0.1-0.2 0.5-0.7

Thermal resistance

2

K/m W pu

The thermal resistance of a heat-conducting layer is inversely proportion to heat conductivity of the material and in direct ratio to its thickness. If the clamping pressure is increased, the layer thermal resistance falls. In figure 5.2, the exemplary dependence of the gasket thermal resistance per surface unit on pressure is shown. However, with a growth of pressure it is necessary to find an optimum, as the clamping effort should not exceed a package recommended value or introduce differential thermal expansion problems into the clamping arrangement.

1 0.9 0.8 0.7 0.6 0.5 0

50

100 Pressure

150

200

psi

Figure 5.2. Exemplary dependence of the gasket thermal resistance on clamping pressure.

5.2.1

Thermal Interface Materials

To be effective, heatsinks require intimate surface-to-surface contact with the component to be cooled. Unfortunately, irregular surface areas, both on the electronic components and on the heatsink mating surface prevent good contact. Up to 99% of the surfaces are separated by a layer of interstitial air, which is a poor conductor of heat thus presents a thermal barrier. Therefore, a thermally conductive interface material is necessary to fill the interstices and microvoids between the mating surfaces. To ensure that electrical problems are not inadvertently introduced while solving the thermal problems, it is often essential that the thermal interface materials also perform an electrical isolation function. Thermal interface materials TIMs vary widely in terms of their performance (that is, thermal, electrical, and physical properties), their general appearance, and their mode of application. Among the most commonly used classes of thermal interface materials are: thermal greases, cure-in-place thermally conductive compounds, gap filling thermally conductive elastomeric pads, thermally conductive adhesive tapes, and phase change materials, all of which are summarised in Table 5.2 and are briefly described.

• Thermal Greases Comprised of thermally conductive ceramic fillers in silicone or hydrocarbon (organic) oils, as shown in Tables 5.2a and b, a thermal grease is a paste, which is applied to at least one of the two mating surfaces. When the surfaces are pressed together, the grease spreads to fill the void. During compression, excess grease squeezes out from between the mated surfaces. Some form of clip or other mounting hardware is needed to secure the joint. Although it is comparatively inexpensive and thermally effective, thermal grease is not an electrical insulator. Disadvantageously, it can be inconvenient to dispense and apply, and requires cleanup to prevent contamination problems.


130

• Cure-in-Place Thermally Conductive Compounds A thermally conductive compound again incorporates thermally conductive ceramic fillers, shown in Table 5.3, but unlike thermal greases, the binder is a rubber material. When first applied, the paste-like compound flows into the interstices between the mating surfaces. Then, when subjected to heat, it cures into a dry rubber film. Besides its thermal properties, this film also serves as an adhesive, allowing a tight, void-free joint without the need for additional fasteners. Thermally conductive compounds can fill larger gaps in situations where thermal greases might ooze from the joint. Although application and performance is similar to that of thermal grease, cleanup is easier, simply involving removal of the excess cured rubber film. • Thermally Conductive Elastomeric Pads A thermally conductive elastomeric pad consists of a silicone elastomer filled with thermally conductive ceramic particles and may incorporate woven glass fibre or dielectric film reinforcement. Typically ranging in thickness from 0.1 - 5 mm and in hardness from 5 to 85 Shore A, these pads provide both electrical insulation and thermal conductivity, making them useful in applications requiring electrical isolation. Thicker pads prove useful when large gaps must be filled. During application, the pads are compressed between the mating surfaces to make them conform to surface irregularities. Mounting pressure must be adjusted according to the hardness of the elastomer to ensure that voids are filled. A mechanical fastener is essential to maintain the joint once it is assembled. • Thermally Conductive Adhesive Tapes A thermally conductive adhesive tape is a double-sided pressure sensitive adhesive film filled with thermally conductive ceramic powder. To facilitate handling, aluminium foil or a polyamide film may support the tape; the latter material also provides electrical insulation. When applied between mating surfaces, the tape must be subjected to pressure to conform to the surfaces. Once the joint is made, the adhesive holds it together permanently, eliminating the need for supplemental fasteners. No bond curing is needed. One limitation of thermally conductive tapes is that they cannot fill large gaps between mating surfaces as well as liquids; hence, the convenience of tape mounting is traded against a nominal sacrifice in thermal performance. • Phase Change Materials Solid at room temperature, phase change materials, shown in Table 5.3, melt (that is, undergo a phase change) as the temperature rises to the 40° to 70°C range. This makes the material (0.13 mm thick in its dry film form) as easy to handle as a pad, while assuring, when subjected to heat during the assembly process, the melt flows into voids between mating surfaces as effectively as a thermal grease. Applying power to the power electronic component introduces the needed heat for the phase change to occur, establishing a stable thermal joint. These materials consist of organic binders (that is, a polymer and a low-melt-point crystalline component, such as a wax), thermally conductive ceramic fillers, and, if necessary, a supporting substrate, such as aluminium foil or woven glass mesh. See section 5.2.2 for further details.

Table 5.2: Thermal Interface Material (TIM) thermal resistances

mm

Thermal Conductivity λ W / m.K

Thermal resistance Rθc-s K/W

n/a

n/a

2.9

1.8 - 2

0.076

0.7

0.9

0.5 - 1.1 0.2 - 0.7

Thickness Interface Dry Joint Thermal Grease

Thermal resistance pu area K cm2/W

Thermal Compound

0.127

1.2

0.8

Elastomer

0.254

5.0

1.8

1-2

Adhesive Tape

0.229

0.7

2.7

0.5 - 1.5

Eutectic (soldering) Sn(91) Zn(9)

61

0.1

Power Electronics

(a) Thermal grease

λ, W / mK

Zinc Oxide/Silicone

0.74

Aℓ203 / Non-Silicone

2

> 10

AℓN / Non-Silicone

4

> 10

Non-silicone paste

2

Silicone paste

Thickness

ρ, Ω.cm

°C

mm

> 5×1014

< 150

5 years @ 25C

13

< 150

1 year @ 25°C

13

< 150

1 year @ 25°C

> 1×1013

n/a

1 year @ 25°C

14

Lifetime

> 1×10

n/a

1 year @ 25°C

Non-curing paste

4

> 1×1013

n/a

n/a

Non-silicon polysynthetic oils

> 7.5

1Å

-50…+150

n/a

thermal phase change

0.90

1×1014

-50…+200

n/a

13

-60…+180

5 years

Silicone

> 4.0

Temperature range

Resistivity

0.8-1.2

1×10

Silicon/Alumina filled

0.38

1×1014

-60…+150

0,08

Silicon/Boron Nitride

2.07

1×10

14

-60…+200

0,25

1000

Aℓ2O3 filled

1.7

n/a

< +150

0,10

15…300

AℓN filled

3.6

n/a

< +150

0,10

15…300

5

n/a

< +450

0,13

15…300

(c) Phase changing heat conducting gaskets Black/self-adhesive layer

Phase Change Material 5

Grease 0

0

300 Time

3000

Clamping psi

Dry interface joint 10

Tensile Strength psi

(b) Heat conducting gaskets

97% Graphite filled

15

°C

Thermal Conductivity

132

decreases. Both of these processes act to reduce the thermal resistance of the interface and the temperature difference is seen to decrease rapidly, reaching the performance of thermal grease, 4°C. In effect, the solid PCM film has turned into thermal grease and a grease-like joint has been formed. The next time the thermal load is activated, the interface does not experience the large temperature difference because the void free thermal joint has already been established.

- Theatsink

Table 5.3: Thermal Interface material (TIM) parameters

Material parameters


Chapter 5

Tcase

131

600 seconds

Figure 5.3. Performance of a PCM, compared to a dry interface joint and thermal grease.

Phase Change Temperature °C

0.7

n/a

< +120

0.077

10…200

< +120

Grey/self-adhesive layer

1.0

5×10

15

-60…+125

0.13

20…60

-60…+125


0.6

5×1014

-60…+125

0.18

50…300

-60…+125


3

n/a

n/a

0.11

n/a

n/a

5.2.2 Phase Change Gasket Materials (solid to liquid) The inavertable heat produced by power electronics necessitates a carefully designed thermal path in which all of the thermal resistances are minimized. For the case-to-heatsink interface, this requires that thermal grease be used to minimize the interface resistance. Phase change materials, PCM's, are an alternative to the messy application and migration problems associated with thermal grease. The term phase change describes a class of materials that are solid at room temperature and change to a liquid as temperature increases. This phase change, or melting, occurs in the range of 40 to 70°C. PCM's are composed of a mixture of organic binders, fine particle ceramic fillers for thermal enhancement, and, optionally, a supporting substrate, such as aluminium foil or a woven glass mesh. The organic binder is a blend of a polymer and a low-melt-point crystalline component, such as a wax. The ceramic fillers may be Aℓ203, BN, AℓN or Zn0. The way a PCM performs compared to a dry interface joint and thermal grease is illustrated in figure 5.3, where the case to heatsink temperature difference is plotted against elapsed time after the commencement of power dissipated. The curve representing the dry interface shows rapid thermal equilibrium, at about 13°C. The curve involving the use of thermal grease shows the same rapid rise to thermal steady-state but at a lower temperature difference of 4°C. The thermal grease significantly reduces the interface resistance by eliminating the interstitial air. The PCM - a 0.1 mm thick dry film - behaves as a combination of the two interfaces. Initially at power up, the cool components give the dry interface behaviour, with the temperature difference rapidly increasing to about 12°C. As the system temperature increases, the PCM melts and the clamping pressure exerted by the clamping mechanism forces the liquid to spread in the thermal joint. As the liquid spreads, the molten PCM displaces the interstitial air and the distance between the surfaces

The thermal resistance across an interface depends on the thermal conductivity of the PCM in the interface and its conductive path length. Thermal conductivity is a function of the type and level of the ceramic filler in the formulation, typically between 0.7 and 1.5 W/m.K. The amount of filler that can be added is limited by the need to keep the viscosity as low as possible to achieve proper flow of the PCM in the interface. The thickness of the interface formed by a PCM is determined by the flatness of the mating surfaces, the clamping pressure, and the viscosity and rheology of the molten PCM. Most commercial surfaces deviate from true flatness by as much as 2µm/mm. This means that the thermal path between a module surface and the heatsink may be as much as 100µm, and more with large heatsinks. Critical applications may require a better surface flatness through additional machining operations to reduce the thermal path. The viscosity and the rheology of the PCM above its melt point represent another factor determining the thickness of the interface. As the PCM melts in the interface, the pressure applied by the mounting clamps forces the liquid to spread, eliminating the interstitial air and allowing the space between the two surfaces to decease. If the viscosity is high, the low force of the clamps will be insufficient to cause sufficient spreading and the conduction path will be long. Low viscosity on the other hand will allow the liquid to fill most of the joint, resulting in the thinnest joint. Using a stronger mounting force will aid the spreading process, but there is a package limit as to the amount of pressure that can be applied. Phase change materials offer the same thermal performance as thermal grease without the mess and contamination associated with grease. They can be supplied attached to a heatsink as a dry film. As soon as they are heated above their phase change temperature, they melt and perform as well as, or often better than, thermal grease. Once this interface has been formed, it remains stable until the sink is physically separated from the power module case-mounting surface.

5.3

Heat-sinking thermal resistance, Rθ s-a

The thermal resistance for a flat square plate heat sink may be approximated by 3.3 ¼ 650 (K/W) Rθ s-a = Cf + Cf A λb

(5.19)

Typical values of heatsink thermal conductance λ in W/K cm at 350 K, are shown in Appendix 5.24 and b is the thickness of the heat sink, mm A is the area of the heat sink, cm2 Cf is a correction factor for the position and surface emissivity of the heat-sink orientation according to Table 5.4.

Power Electronics

The correction factor Cf illustrates the fact that black surfaces are better heat radiators and that warm air rises, creating a ′chimney′ effect. Equation (5.19) is valid for one power-dissipating device, in the centre of the sink, at a static ambient temperature up to about 45°C, without other radiators in the near vicinity. In order to decrease thermal resistance, inferred by equation (5.9), finned-type heat sinks are employed which increase sink surface area. Figure 5.6 illustrates graphs of thermal performance against length for a typical aluminium finned heat sink. This figure shows that Rθ s-a decreases with increased sink length. Table 5.6: Emissivity coefficient of various surface treatments at 100°C Table 5.4: Heatsink correction factor Surface position Cf vertical horizontal

shiny

blackened

0.85 1.0

0.43 0.5

Emissivity

Surface

ε

Polished aluminium

0.05

Polished copper

0.07

Rolled sheet steel

0.66

Oxidised copper

Table 5.5: Fin spacing versus flow and fin length Fin length

(mm) H

Airflow

(m/s) v

75

150

225

Fin Spacing

natural convection

300

(mm) S

6.5

7.5

10

13

1.0

4.0

5.0

6.0

7.0

2.5

2.5

3.3

4.0

5.0

5.0

2.0

2.5

3.0

3.5

0.70

Black anodised aluminium

0.70 - 0.90

Black air-drying enamel

0.85 - 0.91

Dark varnish

0.89 - 0.93

Black oil (organic) paint

0.92 - 0.96

Al203

0.15

If the fin thickness, t, is small relative to the fin spacing, s, the following equation can be used for estimating the thermal resistance of a vertical heat sink in natural convection. 1 1 Rθ hs −a = = (5.20) h × total fin area h × ( 2nf LH ) where a fin efficiency of unity has been assumed and the number of fins, nf, is

nf =

Whs s +t

Minimal thermal reduction results from excessively increasing base length, H, as shown in figure 5.6b. The maximum distance between fins, s, depends on the fin depth, L, and width of the fins, t, with deep finned heat sinks needing more space between adjacent fins than a shallow design, unless fan cooling is used. The minimum spacing, s is determined by fin depth, L, and airflow. If the fins are packed too closely, the flow through them is significantly reduced and therefore the heat transfer coefficient, h, decreases. The deeper the fins, L, the more space needed between them since a portion of the heat is radiated to adjacent fins, which helps to stabilise the temperature, but does little to dispose of the heat (in figure 5.4a, about 30% of the heat is radiation transferred fin-to-fin, hence not all dissipated). Heat transfer co-efficient h decreases due to close proximity of adjacent fins

Whs

Thermal resistance Rθ decreases due to reduction in sink surface area

Ts

Rθhs-a

H

Heat sink thermal resistance

L

134

As the base flow height H is increased, the air at the top of a vertical heatsink is hotter than that entering at the bottom. If the fin depth L is increased, there is more mutual radiation between fins, and as the spacing is reduced, mutual radiation increases further. Airflow is also restricted because of the smaller physical area for air to pass, since more of the available space is occupied by the heatsink itself. The performance of a heatsink is linearly proportional to the base width Whs of the sink in the direction perpendicular to the flow and proportional to the square root of the fin base length H in the direction of the airflow. (The heat transfer coefficient h is inversely related to H). Therefore it is better to increase the width rather than the length, provided the width is not already excessive compared to the length. Heat transfer coefficient h can be defined in a number of ways. If it is defined referenced to the inlet fluid temperature of the heatsink, the heatsink thermal resistance is calculated by 1 Rθ hs −a = (5.21)

ηf hA

where A is the total surface area of fins and base between fins and ηf is the fin efficiency, defined as tanh (m × H ) h × P, ηf = and mf = mf × H λ × Ax

(5.22)

where H is the base height of the fin, m P□ is the fin perimeter, m Ax is the fin cross sectional area, m2 mf is the mass flow rate, equal to ρℓ ×Vf ×s×L, kg/s ρℓ fluid density (= 1/ν specific volume), kg/m3 Vf is the velocity between the fins If the heat transfer coefficient is defined based on the temperature between the fins, the thermal resistance expression involves a heat capacitance component: 1 1 Rθ hs −a = + (5.23) ηhA 2mf c p where cp is the fluid specific heat capacitance at constant pressure, kJ/kg.K. Estimating radiation heat transfer from an extruded heat sink The effect of radiation heat transfer (hence emissivity, ε) is important in natural convection, as it can be responsible for up to 40% of the total heat dissipation. Unless the heatsink is facing a hotter surface nearby, it is imperative to have the heat sink surfaces thinly painted or correctly anodised to enhance radiation. In natural convection situations where the convective heat transfer coefficient is relatively low, based on the dimensional parameters in figure 5.4a, the radiation heat transfer from all surfaces of the extruded heat sink can be calculated using 1 Rθ hs −a = (5.24) (nf − 1) ε a S + ε a nf t + 2 (L + B ) H σ (T s + T A ) (T s2 + T A2 ) where nf is the number of fins εa is the apparent emissivity of a channel Ts is the heatsink surface temperature and TA is the ambient temperature

{

}

3

Apparent Emissivity

b


Chapter 5

εa

133

L/H 1

2.5 Emissivity

2

0.8

ε = 0.8

0.4 1.5

0.2 0

1 0.5

Optimal fin spacing

Emissivity

ε = 0.08

0 0

2

4

6

8

10

L / Whs

s

t

g

Inside fin spacing

s

Figure 5.4. Heat sink dimension parameters and thermal resistance dependence on fin spacing.

Figure 5.5. Apparent emissivity εa of a channel heatsink of two different surface emissivities for different number of fins and dimensions.

Power Electronics

135

Chapter 5

The apparent emissivity is a function of heat sink dimensions and surface emittances of the sink material, as shown in figure 5.5, for two values of the surface emissivity, namely ε equals 0.08 and 0.8. The apparent emissivity εa is based on enclosure theory and assumes a diffuse grey surface and constant surface temperature.


136

The chimney effect results in an airflow velocity v, which increases further up the heatsink stack. This and the air density increase results in the upper heatsink being the coolest, even though the passing air is the warmest.

The emissivity coefficient, ε, indicates the radiation of heat from a body according the Stefan-Boltzmann Law, compared with the heat radiation from an ideal black body where the emissivity coefficient is ε = 1. Regardless of the composition of the emitting surface, the microscopic (and macroscopic) roughness of the surface causes differences in emissivity because a rougher surface has a larger emitting area. Generally, the emissivity of most opaque emitting surfaces increases as wavelength becomes shorter. The emissivity coefficient, ε, for some common surface qualities of aluminium and copper can be found in the Table 5.6 and in Appendix 5.25. The low emissivity coefficients of untreated, polished aluminium and copper means they have surface finishes that limit the radiated heat from a body. Two thin coats of flat white Krylon #1502 (or equivalent) which has an emissivity of 0.96, should be used on all untreated (emissivity-wise) areas. Unless otherwise stated, the heat sink is assumed anodised black (emissivity of up to 0.97) and vertically mounted with negligible thermal resistance from case to sink. In accordance with the data in Table 5.4, a general derating of 10 to 15 per cent for a bright surface and 15 to 20 per cent in the case of a horizontal mounting position, are usually adopted. Figure 5.6b also shows the improvement effects on dissipation due to the high thermal conductivity (heat spreader effect) of oxidised copper.

Figure 5.7. Improved cooling with forced air cooled heat-sink - relative thermal resistance improvement with surface airflow.

anodised

5.4

fan cooled

Cu

Cu

Al

Al

Al Cu

Figure 5.6. Heat-sink typical data (for aluminium and copper): (a) cross-section view; (b) heat-sink length versus thermal resistance for a matt black surface finish; (c) temperature rise versus dissipation for an anodised finish and different lengths; and (d) as for (c) but with a matt black surface finish.

Thermal resistance increases with altitude, z, above sea level, as air density decreases, according to Rθ ( z ) = RO metres / (1 − 5 × 10 −5 z ) . For example: a 1°C/W heatsink degrades to 1.11°C/W at an altitude of 2,000 metres, or 1.18° C/W at 3,000 metres. The effective sink thermal resistance can be significantly reduced by forced air cooling, as indicated in Table 5.5, figure 5.7 and by equations (5.7) and (5.8). If the airflow is • laminar, heat loss is proportional to the square root of air velocity, equation (5.7); • turbulent, heat loss is proportional to velocity to the power of 0.8, equation (5.8). When heatsinks (dissipating a total power of PDtotal) are vertically stack to share the same vertical natural convention airflow, the air temperature of the flow at the upper heatsink, after passing n-1 heatsinks, is

T air = T amb +

n −1 c v n

PD total

(5.25)

Modes of power dissipation

For long, >1ms, high duty cycle pulses the peak junction temperature is nearly equal to the average junction temperature. Fortunately, in many applications, a calculation of the average junction temperature is sufficient and the concept of thermal resistance is valid. Other applications, notably switches driving highly reactive loads, may create severe current-crowding conditions which render the traditional concepts of thermal design invalid. In these cases, transistor safe operating area or thyristor di/dt limits must be observed, as applicable. In yet other applications, heat cycling can cause power module faults, hence device failure, due to • thermal cycling – is associated with large base plate (case) temperature changes, ∆Tc • power cycling – is associated with large junction temperature changes, ∆Tj The die is connected to a low thermal impedance substrate, usually utilising copper in the form of socalled direct copper bonding, DCB, as shown in figure 5.8a and the forced water cooling effectiveness is shown in figure 5.8c. Direct copper bonding Direct copper bonding DCB is a process in which copper (on each side) and a ceramic material, usually either aluminium oxide or aluminium nitride, are fused together at high temperature. By avoiding a thick copper base, the base is thinner and lighter, with lower thermal resistance and much better thermal cycling capabilities. (See Appendix 5.27) The properties of DCB substrates are • High mechanical strength and stability • Good cohesion and corrosion resistance • High electrical insulation • Excellent thermal conductivity • Reliable thermal cycling stability • Matched thermal expansion coefficient to silicon and gallium arsenide • Good heat spreading • Processable, e.g. copper is etchable and millable like a pcb • Environmentally friendly • High copper current density The advantages of DBC substrates are high current carrying capability due to thick copper metallization and a thermal expansion close to the silicon at the copper surface due to high bond strength of copper to ceramic. Normally, DCB has two layers of copper that are directly bonded onto an aluminium-oxide (Aℓ2O3) or aluminium-nitride (AℓN) ceramic base. The DCB process yields a super-thin base and eliminates the need for the thick, heavy copper bases that were used prior to this process. Because power modules with DCB bases have fewer layers, they have a much lower thermal resistance. Because the expansion coefficient matches silicon, they have much better power cycling capabilities (up to 50,000 cycles).

Power Electronics

137

Chapter 5

The drawback of standard DCB substrates for high voltage applications is a start of partial discharge at relatively low voltages. Therefore substrates using expensive metal brazing technologies (AMB) are mainly used in high voltage semiconductor modules for traction applications. The initiation voltage for ceramic thickness of 0.63mm is less than 4kV. Main causes for this behaviour are small voids between the copper and ceramic and blurred straight border lines of the copper conductors at the copper/ceramic interface. Precision etching technology can alleviate these disadvantages. The other disadvantage of DCB is its deficiency for thermal shock because of the large residual stress on the substrate surface due to the coefficient of thermal expansion CTE mismatch of alumina and copper. Thermal cycling Intermittent equipment operation, start-up, and shutdown in extreme temperature conditions may cause power module thermal stresses due to the different linear expansion temperature co-efficients of the materials associated with the soldered substrate mounting to the copper base plate in multi-chip large area packages (see Tables 5.30 and 5.31 in Appendix 5.24). Large base plate (case) temperature changes in excess of 80K over a few minutes, stress the hard solder bonding between the copper base plate and the insulating substrate (usually AℓN or Aℓ203), as shown in figure 5.8a. This fatigue leads to eventual crack failure after a finite number of cycles N, approximated by k N= (5.26) A × ∆T 2 where A is the die area and ∆T is the thermal shock temperature change. The constant k depends on the package, type of hard soldering, etc. Large, multiple die IGBT modules suffer from thermal shock limitations and relatively low reliability, because of the sheer large number of die soldered to the substrate over a large base plate copper area in the module. Figure 5.8b shows how the number of thermal cycles to fracture for DCB substrates varies with copper thickness, when cycled between -40°C to +110°C. For a case temperature change of ∆T = 80K, lifetime can be as low as 3,500 cycles and may only involve powering up and shutting down the associated equipment. Thermal cycling is normally performed by cycling the inactive package between the maximum and minimum storage temperatures. Although Aℓ/SiC is far superior to copper from a differential thermal expansion perspective, its thermal conductivity is only a little better than that of aluminium. Floating silicon wafers in disc type packages suffer to a much lesser extent (an order) from the effects of differential thermal expansion when thermally cycled. power cycle crack

Aluminium wire

Si chip solder layer Cu foil

thermal cycle crack

insulation substrate with adhered copper foil both sides Cu foil


138

Power cycling Rapid cycling of the chip junction temperature causes mechanical stress around the silicon chip to aluminium wire bond interface, due to their different linear expansion temperature co-efficients. Eventually a crack occurs on the silicon side of the interface, as indicated in figure 5.8a. Short rapid junction temperature changes, over tens of seconds, of ∆Tj =100K, can lead to failure within 2500 cycles. The number of cycles to failure increases by just over an order for every 10°C decrease in ∆Tj. In a related thermal application, where the power dissipated in the semiconductor consists of pulses at a low duty cycle, the instantaneous or peak junction temperature, not average temperature, may be the limiting condition. Figure 5.9 shows by comparison such a condition, where the operating frequency, not the maximum power dissipated, is dominant in determining junction temperature. In this case thermal impedance Zθ j-c is used instead of thermal resistance Rθ j-c such that Zθ j-c = r(tp) Rθ j-c, where r(tp) is the normalising factor yielded from the normalised transient thermal impedance curves for the particular device. Appropriate values for the rectangular power pulse width tp and duty cycle factor δ are used. The power devices employed in power electronics are usually used in some form of on/off power pulse waveform mode. The following power waveforms are analysed • Periodic rectangular power pulses (steady-state thermal response); • Single rectangular power pulse; • Composite rectangular superimposed power pulses; • A burst of rectangular power pulses; and • Non-rectangular power pulses. 5.4.1

Steady-state response

Large cycle-by-cycle junction temperature fluctuations occur at low frequencies. As frequency increases, thermal inertia of the junction smoothes out instantaneous temperature fluctuations, as shown in figure 5.9b, and the junction responds more to average, rather than peak power dissipation. At frequencies above a kilohertz and duty cycles above 20 per cent, cycle-by-cycle temperature fluctuations usually become small, and the peak junction temperature rise approaches the average power dissipation multiplied by the steady-state junction-to-case thermal resistance, within a few per cent. Because of thermal inertia (long thermal time constant), the heat sink and package case respond only to average power dissipation, except at ultra low frequencies, < 1Hz. The steady-state thermal conditions for the case-mount and junction (equation (5.12)) are given by Tl − Tc Tc − Ta (W) (5.27) Pd = j = Rθ j −c Rθ c-s + Rθ s-a where Pd is the average power dissipation, which is the maximum power multiplied by the on-time duty cycle δ for rectangular power pulses. The difficulty in applying equation (5.27) often lies in determining the average power dissipation.

solder layer Cu base plate

tp

10

3

10

2

(b)

mK/W

4

(c)

10

1 0

0.2

0.4

0.6

copper thickness

0.8

1 mm

1.2

typical substrate thermal resistance

number of thermal cycles until failure

(a) 10

t2 T2

T2

T1

60

T1

80ºC

T 50

40 Al202 substrate

30

Al3N4 substrate 0

1

2

3 water flow

4

5

6

l/min

Figure 5.8. Direct copper bonding: (a) sectional view of power module substrate showing boundary regions where power cycle cracking and thermal cycle cracking, occur; (b) copper thickness affect on power failure; and (c) thermal resistance dependence on liquid cooling flow rate and substrate material.

Figure 5.9. Waveforms illustrating that peak junction temperature is a function of switching frequency: (a) lower switching frequency with 10 ms pulse and a 20 per cent duty cycle and (b) high frequency and 1 ms pulse with a duty cycle the same as in (a).

Power Electronics

139

Pulse response

When a junction dissipates power associated with a single pulse, the junction temperature increases during the pulse and decays to the original temperature after the energy pulse ceases. The junction temperature variation may vary from an ambient temperature to a level above the normal maximum operating limit, a change of over 150°C. The upper temperature due to the power pulse can cause silicon damage, if the maximum allowable limit is exceeded too often or by a large amount on just one occasion. Equation (5.2) is valid for one dimensional steady state and transient thermal conditions, and the transient temperature equation is given by the first order solution to λA δT Pd = − T + γ AA (W) (5.28) δt A The time domain solution for the temperature rise is ∆T (t ) = ∆Tl × 1 − e −t / τ (5.29)

(

)

where the maximum temperature eventually attained if the power pulse were maintained, above ambient, is P A P ∆Tl = d = d = Pd Rθ (5.30) (K )

λA

λ

Thus the thermal resistance Rθ is modified, or normalized, by Z 0.0001K/W = 0.181 r (10ms ) = θ = 0.5 K/W Rθ Table 5.7 shows the normalised thermal impedance factor, r(tp), for other pulse durations, which are plotted in the accompanying figure. Notice the similarity of the single pulse results given for a practical power device in figure 5.10. Table 5.7: Single pulse data

(s)

power per K, W/K

(

( )

(5.31)

)

(

)

(5.32)

Rθ

That is, thermal resistance Rθ is modified by the factor r(tp) to yield transient thermal impedance Zθ:

(

r (t p ) = 1 − e

−t p / τ

= ∆Tl / Rθ

Zθ = ∆T / Pd

r (tp) = Zθ / Rθ

pulse time

∆Tl t →∞ temperature rise

power dissipated

thermal impedance

normalised

s

K

W

K/W

pu

1

100

200

0.5

1

0.1

116

231

0.432

0.86

tp

The transient thermal impedance Zθ is defined as −t / τ ∆Tl × 1 − e p ∆T −t / τ Z θ = r t p Rθ = = = 1 − e p Rθ Pd ∆Tl

)

(5.33)

This one-dimensional solution assumes a homogeneous thermal conducting material with a single point heat source, producing a uniform heat flow path. Since the practical case is far from ideal, manufacturers provide data for dynamic temperature effects based on a concept termed thermal impedance. The thermal solution given by equation (5.29) gives acceptable results when applied to solid carbon resistors (being a homogeneous material), as considered in Chapter 25 (specifically, see Example 25.7).

0.01

552

1103

0.091

0.181

0.001

5050

10100

0.0099

0.0198

0.0001

50050

100100

0.0010

0.0020

0.00001

500050

1000100

0.0001

0.0002

Th e r m a l Im p e d a n c e 1

0.1

Semiconductor single power pulse capability

A semiconductor has a thermal capacity (mc) of 0.1J/K and a steady state thermal resistance to its case of Rθ = 0.5 K/W. If the junction temperature is not to exceed 125°C in a 25°C ambient, determine the allowable power dissipation, hence transient thermal impedance, as a function of single power pulse duration. Plot the results for five time decades, decreasing from 1s.

Pd

pu

Example 5.1:

( )

hA

and the thermal time constant γ A2 thermal capacity, J/K τ = =

140

which yields ∆Tl = 551.6K. That is, after a long period (>>10ms) the junction temperature would increase by 551.6K. From equation (5.30), this temperature rise corresponds to continuous power of ∆Tl 551.6 K Pd = = = 1103.3 W Rθ 0.5 K/W In 10ms the temperature must only rise 100K, hence, from equation (5.32) the transient thermal impedance Zθ is ∆T 100 K Z θ = r t p Rθ = = = 0.091K/W Pd 1103.3 W

single pulse

0.01

1−e

r = Z/R

5.4.2


Chapter 5

−t p / 0.05s

0.001

Solution The power dissipation per K is 1 = 2 W/K 0.5 K/W From equation (5.31) the thermal time constant τ is given by thermal capacity, J/K 0.1 J/K τ = = = 0.05s power per K, W/K 2 W/K After time tp, the junction temperature rise from 25°C must not exceed 125°C, that is ∆T(tp) = 100K, thus equation (5.29) gives −t / 0.05s ∆T t = ∆Tl × 1 − e −t / τ = ∆Tl × 1 − e p = 100K

Pd / K =

( ) p

(

1

Rθ

=

)

(

)

As a specific example of the procedure, consider a tp = 10ms energy pulse. ∆T (10ms ) = ∆Tl × 1 − e −10ms / 0.05s = 100K

(

)

0.0001 0.00001

0.0001

0.001

0.01

sin g le p u lse w id th , t p

0.1

1

(s)

♣ Figure 5.10 shows the thermal impedance curves for a power-switching device, normalised with respect to the steady-state thermal resistance Rθ j-c. The curve labelled ′single pulse′ shows the rise of junction temperature per watt of power dissipated as a function of pulse duration. The thermal impedance for repetitive pulses Z, of duty cycle δ, can be determined from the single pulse value z according to Zθ ( t p , δ ) = δ + (1 − δ ) z ( t p ) (K/W) (5.34)

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Chapter 5

5.4.3

The equation (5.12) becomes Tl − Tc Pp = j Zθ (t p , δ )

Tl j − Tc = r (t p ) Rθ j − c

(W)

(5.35)

Note that the peak power Pp is employed, and then only for thermal analysis from the junction to the case thermal mounting. That is, Zθ j-c is the only thermal impedance term that exists. See problem 5.8. Figure 5.10 shows that at the pulse width minimum extreme, tp < 1µs, as z(tp→0) →1 in equation (5.34): lim Z θ ( 0, δ ) = δ Rθ j −c = r (t p = 0 ) Rθ j −c (5.36) t p →0

that is, r(tp→0)→δ. Figure 5.10 also shows that at the pulse maximum extreme, that is, tp > 1s or continuous power dissipation, as z(tp→1) →0 in equation (5.34): lim Z θ ( ∞, δ ) = Rθ j −c (5.37) t p →∞

that is, r(tp→∞)→1, independent of duty cycle, that is, for all duty cycles.


142

Repetitive transient response

Minimal temperature variation occurs if the power switching period T is shorter than the junction to case mount thermal time constant, T < τ, whence the concept of steady state thermal resistance is applicable, as presented in 5.4.1. When the relative magnitudes are reversed such that T > 5 τ, then the temperature effects of the power pulse die away, and the single pulse transient thermal impedance approach presented in 5.4.2 is applicable. The transition or boundary between junction operation that can be assumed steady state junction temperature operation (T < τ) and that of a series of discrete non-interacting single pulses (T > 5 τ) can be analysed by extending the one-dimensional thermal transient equation (5.29) in conjunction with figure 5.9a. Figure 5.9a shows how the temperature increases from T1 to T2 during the time tp when power is dissipated, and decreases from T2 to T1 during time t2 when no power is being dissipated by the virtual junction. This increasing and decreasing of the junction temperature occurs cyclically over each period T. Based on equation (5.29) the junction temperature increases exponentially according to T (t ) = ∆Tl − ∆Tl − T e −t /τ (5.38)

(

1

)

and decreases exponentially according to T (t ) = T 2 e −t /τ

(5.39)

where the thermal time constant τ and maximum possible junction temperature rise are defined by equations (5.31) and (5.30), respectively. Since these temperature variations are in steady state, the temperature constants T1 to T2 can be solve using the boundary conditions. This gives −t / τ 1−e p T 2 = ∆Tl (5.40) and T1 = T 2 e −t 2 /τ 1 + e −T /τ The junction temperature swing, ∆T is ∆T j = T 2 − T1 = ∆Tl

Figure 5.10. Transient thermal impedance curves; normalised with respect to the steady state thermal resistance, Rθ j-c.

Example 5.2:

A single rectangular power pulse

A semiconductor with a junction to case thermal resistance of 1 K/W absorbs a single 100W power pulse for 20µs. Based on the thermal impedance characteristics in figure 5.10, what is the expected junction temperature rise, assuming the case-mount temperature does not respond to this short pulse? Solution The period for a single power pulse is infinite T→∞, therefore the duty cycle is zero, δ=0. ∆T j −c = P × Z θ j −c = P × r (t p ) × Rθ j −c From figure 5.10, for a single 20µs pulse r(tp = 20µs) = 0.035. The junction temperature change is therefore ∆T j −c = P × r (t p = 20µs ) × Rθ j −c = 100W × 0.035 × 1K/W = 3.5K The peak junction temperature will rise to 3.5K above the case mount temperature at the end of the 100W rectangular power pulse.

♣

The basic single rectangular power pulse approach can be extended to analyse composite rectangular power pulses by algebraic superposition of a series of accumulating rectangular pulses. Because each composite power pulse extends to the end of the temperature-calculating period, any positive rectangular pulse is subsequently cancelled by a negative power pulse. The technique is illustrated in example 5.4.

(1 − e

−t p / τ

) (1 − e

−t 2 / τ

)

(5.41) 1+e The maximum variation in junction temperature occurs for square wave power, that is tp = t2 = ½T, δ=½: T  ∆T jmax = ∆Tl tanh   (5.42)  4τ  −T / τ

This equation highlights that the magnitude of the temperature change is highly dependant on the power switching frequency 1/T relative to the thermal time constant τ of the semiconductor package.

Example 5.3:

Semiconductor transient repetitive power capability

A semiconductor with a thermal capacity of 0.02J/K and a thermal resistance from the junction to the case of ½K/W, dissipates 100W at a repetition rate of i. 50Hz ii. 300Hz. By calculating the worst-case junction temperature variation, indicate whether steady-state constant junction temperature-based analysis (a thermal resistance approach) is a valid assumption. Solution The long-term junction temperature rise with 100W continuous is given by equation (5.30), which yields ∆Tl = P R = 100W × ½K/W = 50K d

θ

The thermal time constant τ is given by equation (5.31), giving thermal capacity, J/K 0.02 τ = = = 0.01 (s ) 1 power per K, W/K ½ Worse case temperature variation occurs with a 50% power duty cycle, as given by equation (5.42) T T    ∆T jmax = ∆Tl tanh   = 50K × tanh    4τ   4 × 0.01s  From this equation: at 50Hz, T = 20ms, ∆T jmax = 23.1K at 300Hz, T = 3.33ms, ∆T jmax = 4.1K

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The temperature variation of 4.1K at 300Hz is small compared to the maximum allowable junction temperature, typical between 125°C and 175ºC, thus thermal analysis of this device in a 300Hz application, can be thermal resistance calculation based as presented in 5.4.1. On the other hand, the same device used in a 50Hz application will experience 5.6 times the junction temperature swing. This 23.1K variation represents a significant portion of the allowable junction operating temperature, and could mean a thermal resistance approach is unsafe. A thermal impedance design approach is recommended, as in example 5.2 and 5.4.2.

♣

Example 5.4:


Chapter 5

Composite rectangular power pulses

A semiconductor with a junction to case thermal resistance of 1 K/W absorbs the composite power pulse shown in figure 5.11. Based on the thermal impedance characteristics in figure 5.12, what is the expected junction temperature rise at indicate times tx and ty, assuming the case temperature does not respond to this short pulse? That is, the heatsink-case interface temperature is held constant. What is the average junction to case temperature rise, in the repetitive case?

Table 5.8: Rectangular, composite pulse example data

tp1

tp2

tp3

tp4

tp5

tp6

tp7

tp8

180µs

170µs

150µs

30µs

480µs

360µs

330µs

10µs

Pulse duration single pulse

δ = tp / T

0

0

0

0

0

0

0

0

T→∞

r(tp)

0.06

0.055

0.05

0.025

0.10

0.085

0.08

0.015

period

δ = tp / T

0.36

0.34

0.30

0.06

0.96

0.72

0.66

0.02

T = 500µs

r(tp)

0.38

0.36

0.35

0.075

0.96

0.73

0.73

0.035

In figure 5.11b, power pulse P1 = 40W lasts for 180µs, which represents a duty cycle of δ =180µs/500µs = 0.36. The thermal impedance normalised factor of r(tp1=80µs) = 0.38 corresponds to δ = 0.45 in figure t p6 t p2 5.12. r(tp)

t p4

δ = tp / T

t p4

t p3 t p1

↓

t p7

t p5

1 ty

100 80 60 40 20 0

0

50

100

150

200

450

500

time

160 140 120 100 80 60 40 20 0 -20 -40 -60

550

µs

t (a)

t1 = 180µs t2 = 170µs t3 = 150µs t4 = 30µs

0.2

0.2

0.1 0.1

0.05

0.05

0.02 0.01

0.02

Single pulse

0.01

10µs

20µs

50µs

100µs

square-wave pulse duration

200µs

400µs tp

Figure 5.12. Normalise junction to case-mount thermal impedance characteristics.

P3 = 100W P2 = 20W

The junction temperature (rise) at tx, is given by T jt−xc = P1Z θtpj 1−c − P1Z θtpj 2−c + P2 Z θtpj 3−c − P2 Z θtpj 4−c + P3 Z θtpj 4−c

P1 = 40W 50

100

150

P1 = 40W 450 P2 = 20W

500

time

450

µs

t (b)

160 140 120 100 80 60 40 20 0 -20 -40 -60 -80 -100 -120

0.5

0.5

r(tp) = Zθj-c (tp, δ) / Rθj-c

tx

normalising thermal factor

Rectangular power pulses P (W) Composite rectangular power pulses P (W)

ty

tx

Solution

Composite rectangular power pulses P (W)

144

P1 = 40W

tx repetitive T jt−xc = 40 × Z θtpj 1−c − 40 × Z θtpj 2−c + 20 × Z θtpj 3−c − 20 × Z θtpj 4−c + 100 × Z θtpj 4−c

P3 = 100W

= 40 × 0.38 × 1K/W − 40 × 0.36 × 1K/W + 20 × 0.35 × 1K/W − 20 × 0.075 × 1K/W + 100 × 0.075 × 1K/W = 13.8K

P2 = 20W 50

100

time

150

200

350

400

P2 = 20W 450 P3 = 100W

T = 500µs t5 = 480µs t6 = 360µs t7 = 330µs t8 = 10µs

The junction temperature (rise) at ty, is given by t T j −yc = P2 Z θtpj 5−c − P2Z θtpj 6−c + P3 Z θtpj 6−c − P3Z θtpj 7−c + P1Z θtpj 8−c

tx single pulse T jt−xc = 40 × Z θtpj 1−c − 40 × Z θtpj 2−c + 20 × Z θtpj 3−c − 20 × Z θtpj 4−c + 100 × Z θtpj 4−c

t

= 40 × 0.06 × 1K/W − 40 × 0.055 × 1K/W + 20 × 0.05 × 1K/W − 20 × 0.025 × 1K/W + 100 × 0.025 × 1K/W = 2.7K (c)

Figure 5.11. Composite power pulses: (a) original rectangular pulse; (b) composite rectangular pulse, reference tx; and (c) composite rectangular pulse, reference ty.

ty repetitive t T j −yc = 20 × Z θtpj 5−c − 20 × Z θtpj 6−c + 100 × Z θtpj 6−c − 100 × Z θtpj 7−c + 100 × Z θtpj 8−c = 20 × 0.96 × 1K/W − 20 × 0.73 × 1K/W + 100 × 0.73 × 1K/W − 100 × 0.67 × 1K/W + 40 × 0.035 × 1K/W = 12.2K


Chapter 5

equal areas

80 60 40 20 0 0

20

40 time

60 t

80 µs

100µs, 100W

62.5µs, 100W

100 80 60

50µs, 50W

25µs, 50W

40 20 0

100

0

20

40 time

60 t

80 µs

100

tp3 tp1

Power composites, P

Non-rectangular power pulses The concept and characterisation of thermal impedance is based on rectangular power pulses. Nonrectangular pulses are converted to equivalent energy, rectangular pulses having the same peak power, Pp, of period tp, as shown in figure 5.13. The resultant rectangular power pulse will raise the junction temperature higher than any other wave shape with the same peak and average values, since it concentrates its heating effects into a shorter period of time, thus minimising cooling during the pulse. Worse case semiconductor thermal conditions result. Improved thermal accuracy is obtained if each non-rectangular pulse is further sub-divided into numerous equivalent total energy rectangular pulses, as considered in example 5.5.

Power dissipated, Pd W

♣

100µs, 100W

50µs, 100W

100

160

160

140

140 tp

120

W

In the repetitive composite pulse case, the average power dissipated over 500µs is 10µs × 40W + 120µs × 20W + 30µs × 100W = 11.6W 500µs The average junction to case mounting temperature rise is T j −c = Pave × Rθ j −c = 11.6W × 1K/W = 11.6W

Power dissipated, Pd W

= 20 × 0.10 × 1K/W − 20 × 0.085 × 1K/W + 100 × 0.085 × 1K/W − 100 × 0.08 × 1K/W + 40 × 0.015 × 1K/W = 1.4K

146

Figure 5.14 also shows the two rectangular pulse representations, where successive 50µs portions of the triangle are represent by pulses, 100W, 37.5µs and 50W, 25µs, such that the total area is maintained and the peak junction temperature rise occurs at the end of the power pulse sequence. The two pulses are subsequently decomposed into three equivalent composite rectangular power pulses, which sum at any time to give the original two rectangular pulses.

W

ty single pulse t T j −yc = 20 × Z θtpj 5−c − 20 × Z θtpj 6−c + 100 × Z θtpj 6−c − 100 × Z θtpj 7−c + 100 × Z θtpj 8−c

100

Power composites, P

Power Electronics

145

80 60 40 20 0 -20

0

20

-40

40 time

60 t

80 µs

100

120 100

P2

80 60 40 20

P1

0 -20 -40

-60

tp2

40

60

80

P1

100 t µs

-60


The thermal impedance normalising factor r(tp) for the applicable device can be read from figure 5.15, using the pulse periods and duty cycles shown in figure 5.14, and are shown in Table 5.9. Figure 5.13. Conversion of non-rectangular power pulse (a) into equivalent rectangular pulse (b).

Non-rectangular power pulses

i. A single pulse, T → ∞ ii. 50% power duty cycle, T = 200µs iii. 10% duty cycle, T = 100µs Represent the triangular power pulses by firstly one equivalent rectangular power pulse, secondly two equivalent rectangular power pulses, and compare the predicted peak junction temperature rise results. Assume the case temperature is maintained at a constant temperature. Where applicable, calculate the average junction to case thermal mounting temperature, Tj-c. Solution

t p2 t p3

t p1

↓

1 0.5

0.5

r(tp) = Zθj-c (tp, δ) / Rθj-c

Switch losses are a series of triangular power pulses rising linearly to 100W in 100µs after switch turnon. If the thermal resistance junction to case mounting is 1 K / W and the thermal impedance characteristics are represented by figure 5.15, calculate the case to junction peak temperature rise for

δ = tp / T

r(tp)

normalising thermal factor

Example 5.5:

0.2

0.2

0.1 0.1

0.05

0.05

0.02 0.01

0.02

Single pulse

0.01

10µs

20µs

50µs

100µs

square-wave pulse duration

Each saw-tooth power pulse is represented by a single rectangular power pulse, 100W and 50µs duration in figure 5.14, therein fulfilling the requirements of the same maximum power occurring simultaneously in both waveforms and both containing the same energy, area.

200µs tp


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Chapter 5

Table 5.9: Non-rectangular, composite pulse example data One composite power pulse Pulse duration

Pd = =

Two composite power pulses

tp

tp1

t p2

t p3

50µs

75µs

37.5µs

50µs

Single pulse T→∞

δ = tp / T

0

0

0

0

r(tp)

0.045

0.04

0.040

0.045

50% duty cycle T = 200µs

δ = tp / T

¼

⅜

0.188

¼

r(tp)

0.32

0.40

0.22

0.32

δ = tp / T

0.05

0.075

0.0375

0.05

r(tp)

0.08

0.12

0.066

0.08

10% duty cycle T = 1000µs

For a single pulse rectangular power waveform ∆T j −c = P × Z θ j −c = P × r (t p ) × Rθ j −c = 100W × r (t p = 50µs ) × 1K/W

= δ × 50 W

Both rectangular composite power pulse decomposition assumptions produce similar thermal results. At cycle frequencies of 5kHz and 1kHz, together with high duty cycles, the peak junction temperature is marginally higher than the average junction temperature. Using the concept of thermal resistance is adequate under the switching frequency and duty cycle conditions of this problem.

♣

5.5.2

= 100W × 0.08 × 1K/W = 8K

For a two pulse rectangular power waveform representation ∆T j −c = P1 × Z θ j −c t 1 − P1 × Z θ j −c t 3 + P2 × Z θ j −c t 2 + P2 × r (t p 2 ) × Z θ j −c

T

Average power dissipation

Graphical integration

Graphical integration may be formulated by digitally storing a complete cycle of test device voltage and current under limiting steady-state temperature conditions. Each voltage and current time-corresponding pair are multiplied together to give instantaneous values of power loss. Numerical integration techniques are then employed to give the average power dissipation.

= 100W × 0.32 × 1K/W = 32K For a 10% duty cycle, δ = 0.1 ∆T j −c = 100W × r (t p = 50µs ) × 1K/W

t3

T ½ × 100W × 100µs

= δ × 50W × 1K/W = 50 × δ K For 50% and 10% duty cycles, this gives average temperature drops of 25K and 5K respectively.

5.5.1

= 100W × 0.045 × 1K/W = 4.5K For a 50% duty cycle, δ = 0.5 ∆T j −c = 100W × r (t p = 50µs ) × 1K/W

− P1 × r (t p 3 ) × Rθ j −c

sawtooth area

Two commonly used empirical methods for determining power dissipation Pd are • graphical integration and • power superposition.

For a single pulse, δ =0 ∆T j −c = 100W × r (t p = 50µs ) × 1K/W

t1

148

Thus the average case to junction temperature is T j −c = P d × Rθ j −c

5.5

= P1 × r (t p 1 ) × Rθ j −c


t2

= 50W × r (t p 1 = 75µs ) × 1K/W − 50W × r (t p 3 = 50µs ) × 1K/W + 100W × r (t p 2 = 37.5µs ) × 1K/W

For a single pulse, δ = 0 ∆T j −c = 50W × r (t p 1 = 75µs ) × 1K/W − 50W × r (t p 3 = 50µs ) × 1K/W + 100W × r (t p 2 = 37.5µs ) × 1K/W = 50W × 0.04 × 1K/W − 50W × 0.045 × 1K/W + 100W × 0.04 × 1K/W = 3.75K For a 50% duty cycle ∆T j −c = 50W × r (t p 1 = 75µs ) × 1K/W − 50W × r (t p 3 = 50µs ) × 1K/W + 100W × r (t p 2 = 37.5µs ) × 1K/W = 50W × 0.40 × 1K/W − 50W × 0.32 × 1K/W + 100W × 0.22 × 1K/W = 26K For a 10% duty cycle ∆T j −c = 50W × r (t p 1 = 75µs ) × 1K/W − 50W × r (t p 3 = 50µs ) × 1K/W + 100W × r (t p 2 = 37.5µs ) × 1K/W = 50W × 0.12 × 1K/W − 50W × 0.08 × 1K/W + 100W × 0.066 × 1K/W = 8.6K

The average junction to case temperature for a single pulse is zero, and the average junction temperature is the heatsink/ambient temperature. The average junction to case temperature during repetitive operation is independent of whether one or two composite rectangular pulses are used to analyse the saw-tooth pulse pulses, since both model the same original power waveform, each having the same waveform area, energy. The junction to case temperature is dependant on the duty cycle, with specifies the average power dissipation.

Practical superposition

This technique is based on substituting a smooth dc voltage source for a complex waveform. A two-pole, two-position switching arrangement is used, which firstly allows operation of the load with the device under test, until the monitored case temperature stabilises. Then, by throwing the switch to the test mode position, the device under test (DUT) is connected to a dc power supply, while the other pole of the switch supplies the normal power to the load to keep it operating at full power level conditions. The dc supply is adjusted so that the semiconductor case temperature remains approximately constant when the switch is thrown to each position for about 10 seconds. The dc source voltage and current values are multiplied together to obtain the average power dissipated. 5.6

Power losses from manufacturers’ data sheets

The total power dissipation Pd is the sum of the switching transition loss Ps, the on-conduction loss Pd, drive input device loss PG, and the off-state leakage loss PA . The average total power loss is given by Pd = f s ∫

1 / fs 0

v(t ) i (t ) dt

(W)

(5.43)

where fs is the switching frequency and v(t) and i(t) are the device instantaneous voltage and current over one complete cycle of period 1/fs. The usual technique for determining total power loss is to evaluate and sum together each of the individual average power loss components. 5.6.1

Switching transition power loss, Ps

Figure 5.16 shows typical power device voltage-current switching waveforms. Normally an exact solution is not required and an approximation based on straight-line switching intervals is usually adequate. For a resistive load, as derived in Chapter 6 Ps = 61 Vs I mτ f s (W) (5.44) and for an inductive load, as derived in Chapter 6 Ps = ½Vs I mτ f s (W) (5.45) where τ is the period of the switching interval (both on and off), and Vs and Im are the maximum voltage and current levels as shown in figure 5.16. Switching losses occur at both turn-on and turn-off.

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5.6.2

Off-state leakage power loss, PA

During the switched-off period, a small, exponentially temperature dependent current Iℓ, will flow through the switch. The loss due to this leakage current is PA = IA Vs (1 − δ ) (W) (5.46) where δ is the on-time duty cycle of the switch. Normally Pℓ is only a small part of the total loss so that the error in neglecting Pℓ is not significant.

Chapter 5

5.7


150

Heat-sinking design cases

Heat-sink design is essentially the same for all power devices, but the method of determining power loss varies significantly from device type to device type. The information given in data sheets, in conjunction with the appropriate equation in Table 5.11, allows the designer to calculate power semiconductor thermal rating for a variety of conditions. Generally, heatsink design is more readily visualised if a thermal equivalent electrical circuit model approach is adopted, as shown in figure 5.1. The equivalence of parameters is shown in Table 5.10. The examples to follow illustrate the approach. Table 5.10: Thermal equivalent electrical circuit parameters thermal parameter temperature degrees drop Kelvin power Watts dissipated thermal K/W resistance

Figure 5.16. Typical voltage and current at turn-off switching transition for: (a) an inductive load and (b) a resistive load. Current and voltage are interchanged at turn-on.

5.6.3

Conduction power loss, Pc

The average conduction power loss under a steady-state current condition is given by Pc = δ I onVon (W) (5.47) although equation (5.43) is valid in the general case when the integration is performed over the interval corresponding to δ. The conduction loss for the MOSFET is usually expressed in terms of its on-state resistance (equations (3.14) and (4.12)) Pc = δ I d2( rms ) Rds ( on ) T −25°C (5.48) α j  (W) δ I d2( rms ) Rds ( on ) (25°C) 1 +   100  where α is the temperature coefficient of the on-state resistance, which is positive. A linear resistance approximation of equation (5.48) is quite accurate above 25°C if α is small, such that Pc can be approximated by Pc ≈ δ I d2( rms ) Rds ( on ) (25°C) {1 + α (T j − 25°C)} (W) (5.49)

5.6.4

Drive input device power loss, PG

A portion of the drive power is dissipated in the controlling junction or, in the case of the MOSFET, in the internal gate resistance. Usually more power is dissipated in the actual external drive circuit resistance. Drive input loss is normally small and insignificant compared with other losses, and can usually be ignored. Two possible exceptions are: • One notable exception is in the case of the power GTO thyristor, where continuous gate drive is used to avoid loss of latching or when the holding current is high. The holding current can be 3% of the anode current thus, the gate to cathode junction loss can be included in the total loss calculation for better accuracy. Thus, for a gate junction voltage VGC the gate losses are given by (5.50) Pg = δ I G VGC The recovery loss of the gate commutated thyristor (GCT) cathode junction can be included since it is significant because the full anode current is extracted from the gate, thus is involved in recovery of the cathode junction. • A second exception is the MOSFET and IGBT at high switching frequencies, >50kHz, when the loss in the device, associated with providing the gate charge QT is given by equation (4.35): RG int (5.51) (W) PG ( Rint ) = Vgg QT f s RG int + RGext

5.7.1

∆T

thermo-electric model potential Volts ∆V difference

P

current flow

Rθ

Ohm’s resistance

Amps Ohms

I R

magnetic model magneto motive Ampforce turns

ℑ

flux

Wb

Φ

reluctance

Ampturns/Wb

ℜ

Heat-sinking for diodes and thyristors

At low switching frequencies (500K). Vacuum thermionic devices based on resonant tunnelling have cooling capabilities of 20 to 30°C with kW/cm2 cooling power densities achievable. However, since the operating currents for the device are as high as 105A/cm2, effects such as Joule heating (I2R) at the metalsemiconductor contact resistance and reverse heat conduction limit cooling to 2200/800 oxidizing 98%

white

white

2054/1700

2507/1800

99.6%

99.5

3


http://www.1-act.com/

Aluminium nitride

symbol

>3.25

>3.65

2.85

3.2

100 - 300

27

265

270

12

9.5

8.7

9.2

6.6

3-7

Volume Resistivity

(ohm-cm)

>1014

Flexural Strength

(kgf /mm) MPa

3.7 750

3

40

4

>1012 at 20oC >108 at 500oC >280 345 372

1015

102-106

120-150 150-200 345

450 550 410

Modulus of elasticity

GPa

>250 300 331

Hardness (Knoop)

GPa

11.8

14.1

9.8

27

0.22

0.21

0.26

0.14

nontoxic

nontoxic

toxic

nontoxic

Poisson’s ratio toxicity

Substrate Specification Maximum Dimension

(mm)

140 x 100mm,

100 x 200

Thickness

(mm)

0.63 - 0.2 mm

0.63 - 0.30mm

(micron)

as fired - 0.3 as lapped - 0.075 as polished - 0.025

as fired - 0.3 as lapped - 0.075 as polished - 0.025

Surface Roughness

as fired - 0.3 as lapped - 0.1 as polished-0.08

At room temperature, the thermal conductivity of aluminium nitride ceramics is independent of Aℓ3N4 grain size or number of grain-boundaries, but is controlled by the internal structure of the grains, such as the degree of oxidation (oxygen contamination). The coefficient of thermal expansion for direct copper bonded (DCB) substrates with a layer of 0.6 mm alumina sandwiched between Cu layers of various thicknesses, as shown in figure 5.62. 5.24

Appendix: Properties of substrate and module materials Zn

Ag

pure metals Ni

Al

alloys

9 plastics

ice

oxides

nonmetallic solids

8 Foams

fibres

insulation systems

7

Oils

H2 O

Hg

liquids

6 0.2

0.4

0.6

copper thickness

0.8

1

-/1650

(g/cm )

10

0

Silicon carbide

(W/m. K) -6 (x10 /K) @ >20°C (J/kg K)

Density

http://www.aavidthermalloy.com/

Aluminium oxide

CO2

1.2

H2

gases

mm

Figure 5.62. Thermal expansion dependence on copper base plate thickness. 0.01

0.1

1 Thermal conductivity

10 W /mK

100

1000

Power Electronics

219


Chapter 5

220

Table 5.31: Power electronic component properties Table 5.29: Coolant properties

Specific Heat

Density


cp

ρℓ

λ

Material

3

J/ kg K

kg/m

air (STP)

ppm/K

0.026

1004

1.2

-

ρℓ 3

temperature coefficient of expansion CTE

Melting point K

kg/m

W/mK

1,838

903

0.12

silicon

Si

120

700

2330

3.5

0.14

solder

PbSn

50

150

8400

24.1

183

copper

Cu

385

385

8930

17

1358

Diala-X

1,840

870

1685

20/80 EGW Solution

3,817

1023

0.57

50/50 EGW Solution

3,283

1064

0.39

Fluorinert®, FC-77

1,028

1771

0.063

Hydraulic Oil

1,842

868

0.12

polyimid

0.2

1100

1400

Polyalphaolefin

2,180

794

0.14

dielectric layer

0.3

1400

1120

SAE 10W Oil

1,901

875

0.12

encapsulation

0.5

SAE 30W Oil

1,901

875

0.12

aluminium

Aℓ

205

900

2710

22.5

775

gold

Au

315

126

19320

14.2

1336

platinum

Pt

70.9

1448

21450

9.0

1728

tungsten

W

188

130

19300

4.6

3410

molybdenum

Mo

140

250

10200

4.9

2610

lead

Pb

235

130

11340

23

327

tin

Sn

66

227

7300

23

232

SiC

700

250

3.21

3.7

sapphire

2700

419

3900

8.4

2040

diamond

2300

509

3500

2.4

3100

111

343

8490

18.0

920

48

460

7850

11.5

1370

230

1088

2880

5.9

1280

silicon thermal grease

0.8

2093

2.8

-

thermal conducting plastic

20

Stainless Steel, 316

500

8025

16.20

Water, H2O

4,184

998

0.59

Air

1,008

1.1

0.27

137

13,800

137

Mercury

material

relative permittivity

dielectric loss factor

@1MHz

tanδε -4

×10

Aℓ203

22

80

3720

6.5

aluminium nitride

Aℓ3N4

170

725

3300

4.5

aluminium silicon carbide

AℓSiC

170

3000

7

2000

31.1

Cu/Mo/Cu

5.8

silicon carbide specific thermal conductivity

10GHz, 25°C

εr

alumina

platinum (90%) Iridium (10%)

Table 5.30: Properties of module materials linear thermal expansion coefficient

temperature coefficient of εp

type

brass

@25°C λ

∆l / l /∆T

∆ε / ε∆T

W/m K

10 /K

-6

10 /K

CuZn

steel (low carbon) Mica

-6

Aℓ203 99.5%

9.8

1

37

6.5

136

insulator

sapphire

9.4

1

42

6

110

insulator

Quartz glass Beryllium oxide ceramic Be0 GaAs Silicon ρ = 103 Ωcm PTFE

3.78

1

1.7

0.55

13

insulator

6.3

60

210

6.1

107

insulator 3 8900kg/m

12.9

20

46

5.7

semiconductor

11.9

150

145

4.2

semiconductor

2.2

3

0.2

106

350

plastic

polyolefin

2.32

7

0.5

108

480

plastic

393

17

24.1

metal

220

23.8

aluminium

W /m K

20°C

density

J/kgK Coolanol 25

copper

λ

specific heat capacity c

thermal conductivity

material

K Mg3 AlSi3 O10 (OH)2

beryllium

0.6 Be

1700

Table 5.32: Substrate characteristics

1.0 −1300+i1.3×10

14

metal

Material

Al2O3, BeO, AIN, Quartz, Silicon, Sapphire, Ferrite

Surface Finish

Al2O3 As Fired, 0.05µm maximum;

Polished

to 0.12µm0

Dimensions

0.5mm x 0.5mm to 100mm x 100mm

Dimensional Tolerance

± 0.01mm scribed; (± 0.002mm saw cut)

Thickness

0.012mm inches to1.2mm

Thickness Tolerance

0.12mm standard to as tight as 0.04mm

Sputtered Resistor Material

NiCr, Ta2N Sputtered Metallization Ti, TiW, Pd, Ni, Au, Al

Electro-Plated Metals

Au, Cu, Ni, Solder

Electroless Plated Metals

Sn, Ni, Au

Power Electronics

221

5.25


Chapter 5

Appendix: Emissivity and heat transfer coefficient

Table 5.33: Normal total emissivity values @ 20°C

Emissivity is not only a material property but also a surface property, at least for opaque materials. Consequently, coatings (oxides, grease, and water film) influence the value measured under pristine conditions. For example, the emissivity of a copper surface covered with 2 µm oxide increases from 0.03 to 0.2. In practice, surfaces that are initially shiny are covered with oxide and dust after one year of operation. Additionally, surface texture can influence the emissivity because of a strong dependence on the angle. For heat transfer calculations, total hemispherical emissivity is found by integration over all wavelengths and all angles. What is being measured with an IR camera is the normal spectral emissivity. To use an IR camera to measure the emissivity is not recommended because it returns the normal emissivity restricted to the wavelength band of the detector. As a rule of thumb: for unpolished metals the ratio of hemispherical to total emissivity is 1.1 to 1.3, and for non-conductors 0.95 to 0.97. Another angle-dependent difference between metals and insulators is the fact that under a shallow incident angle, the emissivity of metals tends to one and insulators tend to zero. To make things more complex, the emissivity of many materials of interest is strongly dependent on the wavelength. In other words, there is a big difference between the visible band and most common IR bands (0.8 to 3 µm, 3 to 8 µm, 8 to 14 µm). Si and Ge are notorious examples. It is relevant to lowtemperature applications ( 0.1mm)

0.95

2600 K

0.29

Wood

0.9

Silver

polished

0.025

Steel

polished

0.06

Silicon

oxidized

0.6

difficult

0.3 - 0.8

Tin

bright

0.07

Tungsten

polished

0.05

metals untreated metals oxidised oxides and ceramics carbon, graphites minerals, glasses vegetation, skin, water special paints, anodised finishes

0.4

0.6

Surface emissivity

0.8

0.75 0.8-0.9

polished

polished metals

0.2

0.3

Various

highly polished metals, foils, and films

0

ε

polished

Mercury

0.04

Coatings

Aluminium

1

ε Electromagnetic spectrum

222

Power Electronics

223

Natural convection heat transfer coefficient

Substrates Metal sheets:

The convective heat transfer coefficient h, for various geometry arrangements are given by equations (5.93) and (5.94), as applicable, in conjunction with Table 5.34. ¼

 ∆T  h = kh    D 

(5.94)

Table 5.34: Heat transfer coefficient constant, kh constant kh

equation

Vertical height L

1.42

(5.94)

Diameter D

1.32

(5.93)

Vertical cylinder or plate Horizontal cylinder

4 × area perimeter

L=

Horizontal plate Vertical populated PCB

Upper surface hot

1.32

Lower surface hot

0.59 2.44

(5.94)

Diameter D

1.92

(5.93)

IMS (Insulated Metal Substrate) Multilayer-IMS

DCB

AMB

copper

Eutectic coppercopper oxide

(5.94)

Vertical height L

Sphere

Metal sheets:

DCB (Direct Copper Bonding) Power modules with IGBTs (or MOSFETs) and freewheel diodes commonly use substrates made of DCBceramics with Aℓ203 or AℓN isolation that combine good thermal conductivity and high isolation voltage. For DCB, copper surfaces 200µm to 600µm thick, 300µm thick, are applied to the top and bottom surfaces of the isolation substrate material (0.25mm to 0.85mm thick, typically 0.5mm thick) by eutectic melting at between 1065°C and 1083°C. The sandwiched copper oxide layer helps adjust for the different thermal expansion rates. After the necessary track structure for the module circuitry has been etched into the top side copper surface, the chips are soldered on, and contact connection on the chip top side is effected by bonding. The bottom side copper of the DCB-ceramic substrate is fixed to the module base plate (usually 3mm thick copper) usually by soldering, as seen figure 5.8. Other module types do not necessarily require a base plate and the soldering procedure may be avoided. In these modules, the DCB-substrate is pressed on to the heatsink by means of a suitable case.

¼

Dependant geometrical parameter

DCB (Direct Copper Bonding) AMB (Active Metal Brazing)

224

Thick film layers: TFC (Thick Film Copper)

(5.93)

 ∆T  h = kh    L  where ∆T is temperature difference, K L is length, m D is diameter, m

Geometry


Chapter 5

Solder Silver/copper/titanium

Ceramic Aluminium oxide

initial fracture

Figure 5.63. Direct copper bonding, DCB and active metal brazing, AMB.

5.26

Advantages of the DCB-technology compared to other structures are mainly the high current conductivity due to the copper thickness, good cooling features due to the ceramic material, the high adhesive strength of copper to the ceramic (reliability), and the optimal thermal conductivity of the ceramic material. Possible failure due to cracking, termed conchoidal fracture, starts at the copper edge, as shown in figure 5.63, and progressively extends under the copper interface area.

Appendix: Ampacities and mechanical properties of rectangular copper busbars

Effect of emissivity and number of busses on ampacity (current carrying capacity) – data in Table 5.35 shows how higher emissivities improve ampacity. Multiple busses also affect ampacity in a nonlinear relationship. Ampacity may be raised by increasing heat dissipation with convection cooling or surface treatments. Surface treatments which improve emissivity are oxidation or thinly coated, flat, inorganic based spray paints.

AMB (Active Metal Brazing) The AMB process (brazing of metal foil to a substrate) has been developed based on DCB technology. The advantages of AMB-substrates with AℓN-ceramic materials compared to substrates with Aℓ203ceramic materials are lower thermal resistance, lower coefficient of expansion, and improved partial discharge capability. Figure 5.63 illustrate the differences between DCB and AMB.

Table 5.35: Ampcapacity Ampacity, A number of 6mmx100mm busses

30°C rise

50°C rise

65°C rise

emissivity ε

emissivity ε

emissivity ε

IMS

0.15

0.4

0.7

0.9

0.15

0.4

0.7

0.9

0.15

0.4

0.7

0.9

1

1100

1250

1400

1600

1500

1700

1900

2000

1700

1950

2200

2300

2

1900

2050

2200

2300

2550

2750

2950

3100

2950

3200

3400

3600

3

2500

2700

2850

3000

3400

3600

3850

4000

3950

4200

4500

4600

4 3100 3300 3450 3600 4200 4400 4700 4800 4900 5100 5400 5600 6mm spacing. Ampacities of bus bar systems of other configurations must be calculated taking into account size, spacing, number of bus bars, and overall skin-effect ratio.

copper Cu 100µm

TFC Chip: Si, 280µm Solder: SnAg, 80µm

Printed conductor Cu, 30 - 200µm Isolation Al2O3, 380µm

Isolation Polyimid 25µm

Adhesive: silicone, 35µm Baseplate Cu or Al, 3mm

Figure 5.64. Basic module structure of: (a) an IMS power module and (b) a TFC power module.

5.27

Appendix: Isolated substrates for power modules

Currently used isolated substrates for power modules are: Isolation material Ceramic: aluminium oxide Aℓ203 aluminium nitride AℓN (beryllia oxide Be0) (silicon nitride Si3N4)

Organic:

epoxy polyimide (Kapton)

IMS (Insulated Metal Substrate) IMS is mainly used in the low-cost, low-power range and is characterized by direct connection of the isolation material to the module base plate. For insulation, polymers (such as epoxies, polyamides) are applied to an aluminium base plate, as seen in figure 5.64a. The upper copper layer is produced in foil form and glued onto the isolation substrate (similar to PCB production) and is patterned by etching. Advantages of IMS are low costs, filigree track structure (possible integration of driver and protection circuitry), substrate high mechanical robustness, and relatively wide substrate areas, compared to DCB.

225

Power Electronics


Chapter 5

The thin isolation layer, however, leads to comparably high coupling capacitances associated with the mounting surface. Also the thin upper copper layer only provides a comparably low heat spreading, which is improved by additional metallised heat spreading layers under the chips or by adding Aℓparticles to the isolation layer.

Al bonding wire Bond

Ptot1

IGBT

Soldered Cu terminal

Bond

Diode

TFC (Thick-Film-Copper)-thick film substrates Just as with DCB, the basic material for thick film substrates is an isolation ceramic, which is glued directly on to the base plate or a heatsink by means of silicone or applied by soldering, as shown in figure 5.64b. The tracks on the top of the ceramic substrate are made of copper and are applied by screen printing. The power semiconductor chips or other components are soldered or glued on to the track pads.

TFC technology can also be combined with standard thick film technology. Since low resistances may be produced by the paste materials which are usually applied in thick film technology, and since isolated tracks can be arranged on top of one another and connected together, quite a number of system components may be densely integrated. However, the filigree tracks, typically 15µm thick, limit the current capability of such structures to about 10A.

Bond

226

Chip Solder

Substrate Base Plate Solder Screw Thermal Grease

Base plate

Heatsink

Ptotn

Figure 5.65. Power module with DCB substrate: (a) basic structure and (b) thermal model.

High-temperature lead-free transient liquid phase (TLP) die and substrate attach methods

While silicon semiconductor technology is limited to junction temperatures of about 200°C, emerging SiC technology could exploit 600°C operating temperatures, were it not for die and substrate attachment limitations and aluminium thermal bonding stressing. The high-temperature, lead-free silver-tin transient liquid phase (TLP) die attach process for connecting the SiC power devices to a nickel-plated direct bond copper (DBC) or direct bond aluminium (DBA) power substrate (aluminium nitride or silicon nitride) shown in figure 5.66a, allows junction temperature operation to in excess of 400°C. Similarly the high-temperature, lead-free nickel-tin TLP attachment process for connecting the nickelplated DBC or DBA power substrate to the MMC base-plate allows operation to temperatures in excess of 400°C. The baseplate of the power module utilizes a lightweight copper-molly (CuMo) metal matrix composite (MMC) that has a coefficient of thermal expansion (CTE) characteristic closely matching that of the SiC power die. This CTE matching reduces thermal-stress mismatches, thus improving the long-term thermal stressing reliability of the power module.

SiC die

DBA substrate

to

to

DBA substrate

base-plate (a)

(b)

Figure 5.66. Cross-section of various layers in the lead-free 400°C high temperature SiC power module: (a) Ag-Sn TLP die attach and (b) Ni-Sn TLP substrate attach.

Power Electronics

227

CONVERSIONS

Chapter 5

5.3.

STATIC PRESSURE

1 mmH2O = 0.0394 inch H2O 1 mmH2O = 9.8 Pa 1 mmH2O = 25.4 mm H2O 1 Pa = 0.102 mm H2O 1 inch H2O = 249 Pa


228

Figure 5.68a shows the circuit diagram for a power current sink which utilises a 40V source. Both the IGBTs T and wire wound resistors R are mounted on a common heat-sink, of thermal resistance Rθ hs-a = 1 K/W. The transistor has a thermal resistance of 2 K/W from the junction to the heat-sink, and 10 K/W from the junction to air via the transistor casing exposed to the air. The resistor has a mounting thermal resistance from the insulated wire to the heat-sink of 1 K/W and 10 K/W from the wire to the air via its casing exposed to the air. The maximum transistor junction temperature is 423 K, the maximum resistor wire temperature is 358 K and the ambient air temperature is 303 K.

1 Pa ≡ 1 N/m2 = 10-5 bar = 10-6 N/mm2 = 0.102 kp/m2 = 0.987×10-5 atm = 0.0075 Torr = 145.04×10−6 psi AIRFLOW

1 m3/min = 35.31 ft3/min (cfm) 1 cfm = 0.0283 m3/min 1 m3/min = 16.67 litre /s 1 cfm = 0.472 litre /s 1 litre /s = 0.06 m3/min 1 cfm = 1.7m³/h 1 litre/s = 3.6 m³/h 1 m³/s = 3600 m³/h

Figure 5.68. Problem 5.3.

Based on thermal considerations, what is the maximum current rating of the current sink and under such conditions, what is the heat-sink temperature? What power rating would you suggest for the 1 Ohm current measurement resistor? Are there any difficulties in operating the transistor in the linear region in this application if it is in a 120 W dissipation package which is derated according to figure 5.67b? [1.36 A, 69°C, > 2 W]

Problems

5.1.

5.2.

A thyristor bridge switches at 1 kHz and the total energy losses per thyristor are 0.01 Joule per cycle. The thyristors have isolated studs and a thermal resistance of 2 K/W. The heat sink has a thermal resistance of 1.8 K/W. Calculate the maximum number of thyristors that can be mounted on one heat sink if the thyristor junction temperature is not to exceed 125°C in an ambient of 40°C. What is the heat sink temperature? [3 devices, Ts= 94°C]

5.4.

A power IGBT switches a 600 V, 25 A inductive load at 100 kHz with a 50 per cent on-time duty cycle. Turn-on and turn-off both occur in 100 ns and the collector on-state voltage is to be 2 V. Calculate the total power losses, Pd, of the switch. The switch has a thermal resistance Rθj-hs = 0.05 K/W, and the water-cooled heatsink provides a thermal resistance Rθhs-w = 0.05 K/W. Calculate the operating junction temperature if the water for cooling is maintained at 35°C. The 25 A steady state load current is stepped to 200 A. Calculate the surge power dissipation Ps, at 200 A, assuming transistor switching and on-state characteristics remain unchanged. The junction temperature for a power surge during steady-state operation is given by case (e) in Table 5.11. With the aid of figure 5.10, determine the junction temperature at the end of a 0.1s, 200 A pulse. How long is it before the junction temperature reaches Tl j = 125°C, with a collector current of 200 A? (Assume Rθc-hs = 0). [175 W, 52.5°C, 1400 W, 112.6°C, 0.5 s]

5.5

Rework example 5.6 finding the case temperature when the switching losses equal the on-state loss.

5.6

A 20kHz, step-down, 340V dc chopper feeds an inductive load with an average current of 20A and a peak-to-peak ripple of 20A. Thus the MOSFET switch on-state current rise from 10A to 30A while the freewheel diode current falls from 30A to 10A when the switch is off. The MOSFET on-state resistance is 0.1Ω and has switch on and off times of 100ns and 200ns respectively. The switch duty cycle is 75% and it has a thermal resistance Rθ j-c of 0.4K/W and is mounted on a heatsink of thermal resistance Rθc-a of 0.6K/W in a maximum ambient temperature is 40°C. Calculate: i. switching losses, using equations 6.9 and 6.10 ii. switch on-state losses iii. MOSFET junction operating temperature [3.4W + 20.4W = 23.8W; Irms = 15.8A, 25W; Tj = 88.8°C]

A transistorised switch consists of two IGBTs and two 1 Ohm current-sharing resistors, as shown in figure 5.67, mounted on a common heat-sink. Each transistor has a thermal resistance Rθj-hs of 2 K/W, while each resistor has a thermal resistance Rθ r-hs of 1 K/W. The maximum switching frequency is 1 kHz and the maximum duty cycle is 99.99 per cent. The heat-sink thermal resistance Rθ hs-a is 1 K/W. The energy losses per transistor are 5 mJ/A per cycle. If the ambient temperature is 30°C, maximum allowable junction temperature is 150°C, and the maximum allowable resistor internal temperature is 100°C, calculate the switch maximum current rating based on thermal considerations. What are the operating temperatures of the various components, assuming ideal current sharing? [6.88 A, Tr = 100°C, Ths = 88°C, Tj = 122.5°C]

T

T


Chapter 6


230

6 Vg

Load, Switch, and Commutation Considerations Figure 6.1. A typical IGBT transistor switching circuit incorporating a resistive load.

Power switching devices are employed for controlling inductive, resistive or capacitive loads. Inductive loads include electrical machines, transformers, solenoids, and relays. High-current in-rush occurs with loads such as incandescent lamps, pulse-forming networks, snubbers, and motors. Incandescent lamps are essentially resistive, but the cold resistive in-rush current during turn-on is 12 to 18 times the steadystate current. This turn-on surge presents special switch-on problems. Capacitive loads, such as fluorescent lighting, also present high-current in-rush at turn-on. Electromechanical loads, such as shakers, present loads that vary between capacitive and inductive over their operating frequency range. The interaction of the load circuit on the switch arrangement and its commutation depends on three inter-related factors. • The type of load, usually inductive, and rarely purely resistive. • Switching mechanism classification, how the load effects switching commutation, namely hard switching, resonant, etc. • The switch characteristics required to fulfil the supply and load I-V requirements, such as a bidirectional current switch, an asymmetrical sustaining voltage switch, etc.

Figure 6.3 shows the safe operating area (SOA) characteristics for an IGBT, on logarithmic axes. Illustrated are the collector switch-on and switch-off trajectories, which are virtually coincident. In the offstate, point A on figure 6.2b, the transistor supports the supply rail voltage Vs while in the fully on-state, point C on figure 6.2b, the collector current Im is Vs /RL, neglecting the low on-state voltage of the transistor. During switching the collector voltage and current traverse the I-V switching trajectory between the steady-state operating conditions on → Vs /RL and off → Vs, as shown in figure 6.3.

Vg ON

OFF

Each of the three factors and their interdependence with the switching mechanisms are considered separately. 6.1

Load types

The two principal load types of general interest in power electronics are • the resistive load and • the inductive load. Turn-on and turn-off voltage and current switching waveforms, hence losses in a switch, depend on the type of load.

turn-on

on-state

turn-off

off-state

6.1.1 The resistive load A purely resistive load is rarely encountered in power switching applications (other than at load resonance). Figure 6.1 shows a simple resistive load being switched by a common emitter-connected IGBT transistor, which could equally be another appropriate semiconductor switch, for example, a MOSFET. When the gate is driven by the voltage waveform shown in figure 6.2a, the resultant collector voltage and current waveforms are as shown in figures 6.2b and 6.2c. These figures show that at turnon, as the collector current increases, the voltage across the resistive load increases proportionally, as the collector voltage vce decreases at the same rate. That is, at turn-on, vc e (t ) = Vs − ic (t ) RL , while at turnoff the inverse process occurs. Figure 6.2d shows transistor instantaneous power loss during turn-on and turn-off, which in each case has a peak value of ¼VsIm when the collector voltage and current reach half their respective maximum values. The energy loss W during switching is given by W =

∫v

ce

(t ) ic(t ) dt

(J)

where the integration is performed over the switching transition period.

BWW

(6.1)

Figure 6.2. Transistor switching waveforms for a resistive load: (a) on-off gate drive voltage; (b) collectorto-emitter voltage; (c) collector and load current waveform; and (d) instantaneous collector-emitter losses.

Power Electronics

231

Chapter 6

It is important that this trajectory does not exceed the shown SOA bounds set by the device voltage and current limits, and that the SOA region be traversed rapidly. For slow transitions, greater than a few microseconds, power dissipation considerations become the limiting design factor, which is a thermal limitation. In order to perform the required thermal design calculations (for heatsink determination) it is necessary to be able to specify device-switching losses. To simplify analysis, the switching waveforms shown in figure 6.2 are linearised as shown in figure 6.4. As indicated on these waveforms, the collector voltage fall at turn-on is given by vce (t ) = Vs (1 − t / ton ) while the collector current rise is ic (t ) = I m t / ton , where I m = Vs / RL . Combining vce(t) and ic(t) by eliminating time t, gives ic = Vs (1 − vce / Vs ) / RL (6.2)


off

on

on

232

off

As shown in figure 6.3, this describes the linear turn-on transition of slope -1/RL from the on-state voltage with Vs / RL collector current, shown as C, to the off-state at A where no current flows and the collector supports the supply Vs. Note figure 6.3 uses logarithmic axes, so the transition trajectory does not appear as a straight line (the inset figure is for linear axes). Using equation (6.1), the switch-on loss for a resistive load is given by t t t Wonr = ∫ Vs (1 − ) I m dt ton ton 0 on

Vs2 ton (J) RL where I m = Vs / RL and ton is the period of the switch-on interval, as shown in figure 6.4. =  I mVs ton

Ic

C

(6.3)



or

B Figure 6.4. Linear approximations of switching intervals for a purely resistive load: (a) collector voltage and current linear waveforms and (b) corresponding energy and power losses.

Example 6.1: I

An IGBT switches a 10 ohms resistive load across a 100V dc supply. If the switch on-state duty cycle is 25%, (δ = ¼), calculate the average load voltage and current. Calculate the switch losses if the switch-on time is ton =1µs, switch-off time is toff =2µs, and the on-state voltage is 2V.

SOA

C -1/RL

A

Resistive load switching losses

Solution

V

When the switch is on, the current in the resistor is IL =Vs /R = 100V/10Ω = 10A. VCES

Figure 6.3. Transistor I-V characteristics showing safe operating area and the switching trajectory with a resistive load, on logarithmic axes, and inset, on linear axes.

Similarly, using the time dependant collector voltage and current equations shown on figure 6.4a, the turn-off switching loss is given by t t t Woffr = ∫ Vs I (1 − ) dt toff m toff 0 (6.4) V2 =  I mVs toff or (J)  s toff RL where toff is the turn-off period as shown in figure 6.4. The average power loss due to switching, which is required for the thermal design outlined in chapter 5, is obtained by multiplying energy loss W by the switching frequency fs. That is, the turn-on switching loss is given by Pon =  ImVs ton fs (W) (6.5) while the turn-off loss is given by Poff =  Im Vs toff fs (W) (6.6) off

Because of IGBT current tailing and voltage overshoot at turn-off, the practical switching losses will be larger than those given by the linear approximating methods outlined.

The average load voltage is Vo = δ Vs = 0.25 × 100V = 25V The average load current is I o = Vo / R = 25V/10Ω = 2.5A

The total switch losses PT are made up of three components. PT = on-state loss + loss at switch-on + loss at switch-off 1 1 PT = δ × vce × I L + + 6 Vs I L ton f s 6 Vs I L toff f s = ¼×2V×10A + 16 ×100V×10A×1µs × 10kHz + 16 ×100V×10A×2µs × 10kHz =

5W

+

5 3

W

+

10 3

W

= 10W

Since the off-state leakage current and gate power losses are not specified, it is assumed these are insignificant. Technically the load current should be calculated based on 98V across the load since the switch supports 2V. Also the switching loss calculations should use a voltage of 98V, rather than 100V and a load current of 9.8A rather that 10A. The percentage error is small, and becomes increasingly insignificant at higher voltages.

♣

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Example 6.2:

Chapter 6


234

Transistor switching loss for non-linear electrical transitions

Assume the transistor collector current at turn-off falls according to ic = ½ I m (1 + cos π t / T0 ) for 0 ≤ t ≤ T0 For a resistive load, RL

(6.7)

Df

i. Calculate transistor loss at turn-off. ii. Show that the switching trajectory across the SOA is as for the linear current fall case, as given by equation (6.2) and shown in figure 6.3. iii. Calculate the peak power dissipation and the time when it occurs. Vg

Vg

Solution i.

The collector voltage for a resistive load, on a dc supply Vs, is given by vce (t ) = Vs − ic (t ) RL = Vs − ½ I m (1 + cos π t / T0 ) RL

and since Vs = I m RL

vce (t ) = ½Vs (1 − cos π t / T0 ) The turn-off energy loss is given by

∫ =∫

Woff =

T0 0 T0 0

p(t ) dt =

∫

T0 0

R

ic (t )vce (t ) dt

½ Im (1 + cos π t / T0 ) × ½ Vs (1 − cos π t / T0 ) dt

=  Vs Im T0

D Vg

Combining vce(t) and ic(t) so as to eliminate the time variable, yields V v ic = s (1 − ce ) RL Vs which is the same straight line expression as in equation (6.2) and shown in figure 6.3, for the linear switching transition case.

Vg

ii.

iii.

Instantaneous power dissipation is given by V v P = vceic = vce s (1 − ce ) RL Vs

Peak power Pˆ occurs when dP/dvce = 0, that is, when vce = ½Vs, whence on substitution into the power expression P, yields Pˆ = ¼ Vs 2 / RL = ¼ Vs I m at t = ½T0

♣ Turn-on loss can be similarly analysed to yield virtually identical expressions, as is required in problem 6.4.

6.1.2

The inductive load

The voltage spikes generated by inductive loads at turn-off may have high energy content, and the power generated may cause excessive device temperature, voltage stressing, and device failure. At turn-off, the switch decreases the inductive load current from Im to zero at a high di/dt and the resultant inductive voltage spike is given by di v (t ) = L (V) dt where L is the load inductance. The spike energy to be absorbed by the switch is given by W = ½ LI m2 (J) Both the voltage spike and its associated energy may be well outside the capabilities of the switching device. The peak voltage induced must be limited to a value below the breakdown rating of the device. Four commonly employed voltage limiting techniques are shown in figure 6.5.

(d)

Figure 6.5. Four methods of limiting inductive load turn-off voltage spike and of absorbing the associated energy: (a) freewheel clamping diode; (b) Zener diode clamp; (c) R-C snubber circuit; and (d) capacitor soft voltage clamp.

The freewheel diode Df in figure 6.5a is used to clamp the maximum device voltage to the supply rail voltage. The stored load energy is dissipated after turn-off as a result of the current that flows in the diode and load. The low impedance of the diode causes the current to decay slowly, since the inductor stored energy can only dissipate slowly in the freewheeling loop resistive components. A shorter current decay time can be achieved if series loop resistance R is added, as shown in figure 6.5a. Now the peak off-state voltage experienced by the switch is increased from Vs in the case of only the diode, to Vs + ImR because of the initial voltage drop across the optionally added resistor. This extra voltage drop, ImR, decreases exponentially to zero. The resistor in figure 6.5a can be replaced by a Zener diode, thereby clamping the switch voltage at turn-off to Vs + VZ. The load now freewheels at a fixed voltage VZ thereby improving the rate of current decay, which is now constant. The inductive load current will fall linearly from Im to zero in a time given by t = LI m / Vz (s) An alternative Zener diode clamping circuit, as shown in figure 6.5b, can be employed in low power applications. The Zener breakdown voltage Vz is selected between the rail voltage Vs, and the switch breakdown voltage (Vs < Vz < VBR ) . At turn-off, the Zener diode clamps the switch voltage to a safe level VZ and absorbs the stored inductive load energy. The higher the clamping voltage level, the faster the energy is dissipated. The inductive load current decays linearly to zero in a time given by t = LIm /(Vz - Vs ) (s) (6.8) The two different Zener diode approaches perform the same switch clamping function in the same current decay time, if the voltage experienced by the switch is the same, but with different Zener diode losses. The desirable feature in the case of the Zener diode in parallel to the switch as in figure 6.5b, is that the protection component is directly across the element to be voltage protected. When placed in parallel with the load as in figure 6.5a, the switch is indirectly voltage protected, relying on the supply decoupling being a low inductance path. A reverse blocking diode Df in figure 6.5a is mandatory.

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Chapter 6


• • •

100V

100V

The parallel-switch Zener diode approach in figure 6.5b has a number of disadvantages The Zener diode voltage rating must be in excess of the supply rail, Vs, while any Zener value can be used when the Zener diode is in parallel with the load. At higher voltages, >280V, Zener diodes will have to be series connected, thus the low inductance advantage of clamping with just one component is diminished. Assuming no resistance in the load, the energy dissipated with the two Zener diode approaches differs. When in parallel with the load, the load energy ½ LI m2 is dissipated while in the second case, load and supply energy are dissipated in the clamping Zener diode. The extra supply energy, in addition to ½ LI m2 , dissipated in the Zener diode, is ½ LIm2 Vs /(Vz − Vs ) . This is derived by recognising that, assuming a purely inductive load, the dc supply Vs delivers a current Im which linearly falls to zero over the period given by equation (6.8).

Df

Z1 25V

Z2

Figure 6.6a. Three inductive load clamping circuits. Icoil

Icoil 1A

Figure 6.5d shows a capacitive voltage clamp used to soft clamp the switch voltage overshoot caused by the inductive energy stored in the load. The capacitor retains a charge of at least Vs. At switch turnoff, when the switch collector voltage reaches the capacitor (supply Vs) voltage level, the inductive stored load energy is transferred to the capacitor and concurrently, the capacitor discharges the energy in excess of Vs into the supply. When the capacitor is over charging, energy is taken from both the load inductance and the supply. When the capacitor discharges through the resistor back into the supply, the earlier energy taken from the supply is returned. The net effect is that only the energy ½ LI m2 is dissipated in the resistor. A reset resistor of low inductance is not necessary – a wirewound resistor can be used. This capacitive soft voltage clamp is analysed in detail in chapter 8.2.

1A

Iswitch 0

IZener

Iswitch

10

50 t (µs) switch voltage

Zener diode, switch voltage clamping

Solution The three voltage clamping circuits being considered are shown in figure 6.6a. i.

With a 20kHz switching frequency, the coil current rises and falls every 50µs, with an on-state duty cycle representing 10µs for the current to increase in the coil and 40µs for the current reset decay to reach zero. From V=Ldi/dt, in steady-state, with zero coil resistance and zero initial current, the peak coil current is I = Vs t /L = 100Vx10µs/1mH = 1A. Thus the coil current rises linearly from zero to 1A in 10 µs. During reset, the coil current waveform depends on the reset circuit. For Zener diode (constant voltage) reset, the current falls linearly, while with a resistor the reset current decays with an L / R exponential time constant, as shown in figure 6.6b, for each case. The various circuit voltage and current waveforms are shown in figure 6.6b, where data derived from the rest of this example has been incorporated.

0

IResistor

10

50 t (µs) switch voltage

175V

125V 100V

A reed relay coil of 1 mH inductance is switched at 20 kHz with a 20 per cent on-time duty cycle, across a 100 V dc rail. The energy stored in the coil at turn-off is dissipated in a 25 V Zener diode connected as shown in figure 6.5a. i. Sketch the coil current and voltage, and the switch voltage waveforms. ii. What is the average coil voltage? iii. What Zener diode voltage is required for the circuit in figure 6.5b so as to produce the same coil current waveform as in figure 6.5a when using a 25 V Zener diode? iv. For each circuit, calculate the power requirement of the Zener diode and the average power delivered from the 100 V supply. v. Calculate the minimum resistance that replaces the Zener diode in figure 6.5a if the coil is to be switched on with almost zero current. Draw the coil current and switch voltage waveform, showing the switch peak voltage at turn-off. vi. Discuss the relative features of each voltage clamping approach.

100V

Df

The R-C snubbing circuit shown in figure 6.5c is commonly used in power conversion circuits to limit spikes caused by transformer leakage inductance, diode recovery, and interconnection wire inductance. The stored load energy is resonated to the snubber capacitor at switch turn-off. The reset resistor R (non-inductive) must overdamp the L-C-R oscillation by absorbing the transferred energy. The resistor also limits the snubber capacitor discharging current to a maximum of Vs /R at switch turn-on. For a purely inductive load, the snubber resistor power losses are given by the sum of the turn-off and turn-on losses, that is P = (½ LI m2 + ½CVs2 ) f s (W)

Example 6.3:

236

100V

Coil voltage equal areas 0V -25V

Coil voltage equal areas t

0V

t

-25V -75V

Figure 6.6b. Coil voltage and current waveforms.

ii.

From V=Ldi/dt, for a steady-state continuous waveform, ∫ VL (t )dt = 0 , thus 1/ T ∫ v (t )dt = Vave = 0 , as shown on the coil voltage waveform (the coil voltage areas cancel to zero).

iii. The parallel Zener diode requirement is VZ2 = Vs+VZ1 = 100V+25V = 125V. iv. Zener diode VZ1 in the parallel-load reset circuit: The energy ½LI 2 is transferred from the coil to the Zener diode when the switch is turned off. The power dissipated in the Zener diode at 20kHz is therefore ½ LI 2 f s = ½×1mH×1A 2 ×20kHz = 10 W . The total power drawn from the supply is the power stored by the coil at the end of the 10µs ontime, namely 10W. Zener diode VZ2 in the parallel-switch reset circuit: When the coil releases its stored energy (10W) into the Zener, current is also drawn from the supply. The total average power delivered by the supply over the 50µs period is given by Vs I ave = ½ × 100V×1A = 50W . This comprises ½LI 2 (10W) from the supply into the coil when the switch is on for 10 µs, and the remainder (40W) into the Zener diode (plus the coil energy, 10W), when the switch is off for 40 µs. The Zener diode losses are 50W during the switch off period. v. When a resistor is used in the reset circuit, the current decays exponentially from 1A to 0A. The resistance determines the peak switch voltage. The resistance does not affect the amount of energy dissipated, only the period over which the coil energy is released, dissipated as heat. Assume the coil current to be near zero after three L/R time constants, that is 3L/R = 40µs = toff.

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Chapter 6

For L = 1mH, this gives R = 75Ω, with a power dissipation rating of 10W from part iv. At switch turn-off the collector voltage rises to (100V+1A×75Ω) 175V and then decays to 100V. Use an 82Ω (preferred value, exceeding 75Ω which reduces the time constant), 15W metal oxide resistor for low inductance. vi.

A Zener diode approach gives a fixed over-voltage on the switch, independent of current or stored energy. When clamping is in parallel with the switch, only one clamping element is needed, but its power requirement is significantly higher than when the clamp (Zener plus diode) is in parallel to the load. Any resistive element must have low inductance. This is restrictive given the power levels involved, and may result in only less effective wire wound elements being viable.

♣


It will be seen in figure 6.7 that during both turn-on and turn-off the switch must support instantaneously a maximum voltage, Vs, and full load current, Im, condition. These severe electrical conditions are shown on the SOA characteristics in figure 6.8. In switching on from the operating point A to C, a maximum voltage and current condition (Vs, Im) occurs at point D. Because of freewheel diode current reverse recovery effects at turn-on, an SOA trajectory point B is reached. At turn-off, due to stray inductance, voltage over shoot occurs and the point E is reached. By comparison with figure 6.2, it is seen that power losses during the switching intervals are higher for an inductive load than a resistive load. diode recovery

Ic Icmax

By far the most common technique used to limit inductive switch-off voltage spikes in power circuits involves the use of a freewheel diode without Ropt, as shown in figure 6.5a and 6.7a. Typical switching waveforms for an inductive load clamped by a freewheel diode are shown in figure 6.7.

•

At turn-off, the switching device conducts the full load current as the collector voltage rises to the supply rail. When the collector voltage reaches the supply rail level the freewheel diode becomes forward-biased and begins to conduct. Only then can the switch current fall to zero. The freewheel diode conducts the load current.

•

At switch turn-on, assuming the diode is still freewheeling load current, the switch current increases, displacing freewheeling diode current, while the load is clamped to the rail voltage by the conducting freewheel diode. Only when the switch conducts the full load current can the freewheel diode recovered (and block), so that the switch voltage can fall to the low on-state level.

238

Voltage overshoot

tfv

on-state

E

trv

tfi

Rds(on) limit

tri

Vs

off-state

A VCES

Figure 6.8. I-V characteristics for an IGBT showing its safe operating area and switching trajectory for an inductive load (linear axes).

Vg

V Vgg (V)

ON

Switching losses can be calculated by using linear approximations to the switching transitions. It can be assumed that a silicon carbide Schottky freewheel diode is employed so as to allow reverse recovery effects to be neglected. Figure 6.9 shows the linearised switching waveforms for an inductive load, where maximum voltage Vs and current Im occur simultaneously during both turn-on and turn-off. The equations for the collector voltage and current at turn-on and turn-off are also shown in figure 6.9. The turn-on switching interval loss is given by the time integral over the current rise period plus the voltage fall period, t t t t Won = ∫ Vs Im dt + ∫ Vs (1- ) Im dt tri t fv 0 0 (6.9)

OFF

di × c L stray dt

ri

fv

= ½ Vs Im ton (J) where ton = tri + tfv, as shown in figure 6.9. The current rise time at turn-on is termed tri, while the switch voltage fall time at turn-on is termed tfv.

B A D

Similarly, from figure 6.9c, the turn-off loss is given by t t t t Wof f = ∫ Vs I dt + ∫ Vs I m (1- ) dt tri m 0 0 t fv rv

= ½ Vs I m toff

fi

(6.10) (J)

where toff = trv + tfi, as shown in figure 6.9c. The switch voltage rise time at turn-off is termed trv, while the switch current fall time is termed tfi.

Won

Woff

Figure 6.7. Inductive load switching waveforms: (a) the circuit including the freewheel diode Df; (b) on-off gate drive voltage; (c) collector-to-emitter voltage; (d) collector and freewheel diode current; and (e) switch instantaneous power losses.

Comparison of switching losses for a resistive load, equations (6.3) and (6.4), and an inductive load, equations (6.9) and (6.10), shows that inductive switching losses are three times those for the resistive load case. The peak power experienced by the switch during switching of an inductive load, Vs Im, is four times greater than that experienced with a resistive load, ¼VsIm. As for the resistive load switching circuit, actual switch losses with an inductive load are higher than those predicted by equations (6.9) and (6.10). The effects of current tailing, voltage over-shoot, and freewheel diode reverse recovery can together produce losses of the same order as those predicted for theoretical switching by equations (6.3), (6.4), (6.9), and (6.10).

Power Electronics

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iDf

Chapter 6

Im = iDf + ic

ic

KCL

ic

Kirchhoff’s current law

6.1.3

iDf t

(a)

vDf

vce

Vs = vDf + vce

vDf

Vs

KVL

vce

KVL

Im

vDf

iDf ic

t

vce (b)


240

Diode reverse recovery with an inductive load

When a bipolar diode conducts the pn junction scl region accumulates charges. When the diode turns off and the current falls to zero, the junction retains charge that must recovery before diode reverse voltage can be supported. Negative diode current flows. This phenomenon was considered in chapter 4.2.2 and is shown in figure 6.10a. The maximum collector current at turn-on is increased above the load current level Im by the reverse recovery current Irr, to Im+Irr. The diode begins to support reverse voltage once the peak reverse recovery current is reached. As a consequence the turn-on losses are increased as shown in figure 6.10c. The circuit current at peak recovery has a discontinuous derivative, and as a consequence, high circuit voltages are induced across circuit stray inductance due to v = Ldi/dt. High-frequency voltage ringing occurs as the stored energy in the stray inductance is dissipated and reverse voltages far in excess of Vs are experienced by the recovering diode. Im+Irr Im = iDf + ic

iDf

off

on

on

ic

off

iDf

Kirchhoff’s current law Schottky diode

ic t

bipolar diode

(a)

Irr

(c) Vs = vDf + vce

vce

vDf

off

vce

Kirchhoff’s voltage law

on

vDf

off

on t

(b)

(d)

(Im+Irr)Vs

Vs

Figure 6.9. Linear approximations of transistor switching intervals for an inductive load: (a) Kirchhoff’s current law Im = iDf + ic; (b) Kirchhoff’s voltage law Vs = vDf + vce; (c) collector voltage and current waveforms with switching parameters defined; and (d) corresponding switching losses.

Example 6.4:

Im V s PD

vDf = Vload

Inductive load switching losses

Solution Maximum switch losses occur when the duty cycle approaches one (δ →1) such the both turn-on and turn-off still occur. The total switch losses PT are made up of three components loss at switch-on + loss at switch-off PT = on-state loss + PT = δ × I L2 × Rds ( on ) + ½Vs I L ton f s + ½Vs I L toff f s = 1×10 2 ×0.2Ω + ½×100V×10A×1µs × 10kHz + ½×100V×10A×2µs × 10kHz 20W

+

t

ic

A power n-channel MOSFET switches a 10A, 100V dc, highly inductive load at 10kHz. Calculate the worse case switch losses if the switch turn-on time is ton = 1µs, switch turn-off time is toff = 2µs, and the MOSFET channel on-state resistance is 0.2Ω at 10A. Calculate the maximum instantaneous power dissipation in the switch, and determine when it occurs.

=

Im iDf

5W

+

10W

= 25W Since the off-state leakage current and gate power losses are not specified, it is assumed these are insignificant. The switching loss calculations should use a voltage of 98V, rather than 100V, since (10A×0.2Ω) 2V is dropped across the channel resistance of the MOSFET. The percentage error is small, and becomes insignificant at higher voltages.

Maximum switch loss occurs when during the switching transitions, the drain current is 10A and the drain voltage is 100V. The maximum instantaneous loss is 10A×100V=1000W, (IL ×Vs).

♣

ton

vce

PD (c)

Figure 6.10. Linear approximations of transistor switching turn-on interval for an inductive load showing freewheel diode reverse recovery effects on the right: (a) Kirchhoff’s current law Im = iDf + ic; (b) Kirchhoff’s voltage law Vs = vDf + vce; and (c) corresponding switching losses.

Example 6.5:

Inductive load switching losses with device models

A MOSFET 340V dc chopper feeds an inductive dc motor load at 50kHz. In steady state the load current rises from 10A to 25A when the switch is on with a 75% on-state duty cycle (δ = ¾). The MOSFET switch turn-on time is ton = 100ns, switch turn-off time is toff = 200ns, and the channel on-state resistance is Rds on = 0.025Ω. The freewheel diode is modelled by a 1V on-state voltage and on-state resistance of 0.05 Ω. Neglecting diode recovery and diode turn-on losses, calculate i. ii. iii. iv.

the MOSFET total losses diode losses power delivered to the motor load, if the armature resistance is 1 Ω and back emf is 170V electromagnetic energy conversion efficiency and total circuit efficiency

Power Electronics

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Chapter 6


242

Solution

6.2

i. The MOSFET losses comprise turn-on, turn-off, and conduction losses. The rms current in the MOSFET is given by

Having considered the switching of inductive and resistive loads, the following are the electrical and thermal characteristics desirable of commutable switching devices (as well as low cost):

I M − rms =

δ  2 ∨ ∨2  I + I ×I+ I

off-state (ideally open circuit): • Low, temperature independent leakage current in the off-state, to minimise off-state power loss, and to simplify resistive networks for device series connection. • High forward and reverse voltage blocking ratings to reduce the need for series device connection, which would otherwise complication control and protection circuitry requirements. Series connection increases the on-state voltage, hence on-state loss. When a diode is used in antiparallel across the switch to allow reverse principal current flow, the switch does not require a significant reverse voltage blocking rating. • High static off-state avalanche capability to absorb transient overvoltage stresses. • High static and re-applied dv/dt capability to withstand high applied off-state voltages without avalanche or false turn-on, with minimal displacement current.

 3   0.75 2 = × ( 25A +25A×10A+10A 2 ) = 15.6A 3 The MOSFET conduction losses are therefore 2 Pc = I rms Rds on = 324.75 × 0.025Ω = 8.1W

The switching losses are ∨

at turn-on Pt -on = ½ Vs I ton f s = ½×340V×10A×100ns×50kHz = 8.5W ∧

at turn-off Pt -off = ½ Vs I toff f s = ½×340V×25A×200ns×50kHz = 42.5W

on-state (ideally short circuit): • Low on-state conducting voltage or low on-state resistance, in order to minimise onstate conduction power loss: with a slight positive temperature co-efficient at high current densities, to allow reliable parallel device connection. • High on-state current density capability so as to avoid need for and problems associated with parallel device current sharing and differential thermal coefficients. • Safe controlled switch off from a short circuit current condition.

Total MOSFET losses are PMOSFET = Pc + Pt − on + Pt −off = 8.1W+8.5W+42.5W = 59.1W ii. The diode RMS current is 1− δ  2 ∨ ∨ 2  I + I × I+ I  3   0.25 = × ( 25A 2 +25A×10A+10A 2 ) = 9A 3 The average diode current is ∨ I d = ½ (1 − δ )  I + I  = ½× (1 - ¾ ) × ( 25A+10A ) = 4.375A   The total diode losses are Pdiode = I D2 −rms RD−on + I × VD−on I D−rms =

Switching (ideally instantaneous): • Low control power to produce switching between states, with no ‘Miller’ interaction. • Short, temperature independent, turn-on and turn-off times to result in low switching losses which will allow high frequency switching. • High initial di/dt capability at turn-on to allow rapid low loss build-up of the turn-on principal current. • High surge current capability to withstand transient over current fault conditions, resulting in better fault tolerance and nuisance tripping ride through. • Large switching safe operating area, being able to simultaneously, but briefly, support rated voltage and rated current, without the need for switch snubber circuits.

=81.25×0.05Ω + 4.375A×1V = 8.4W

iii.

The power delivered to the load comprises losses in the 1Ω armature resistance and the power delivered into the 170V dc back emf. The rms load current is given by

Thermal/mechanical: • Easy to electrically connect and mechanically mount, with low thermal resistance and impedance for efficient heat removal. • Mechanically, electrically, and thermally robust, with the ability to operate at high (and low) junction temperatures in high (and low) ambient, pressure, humidity conditions. • Matching substrate structure and thermal properties to minimise stressing due to thermal, mechanical, and power stressing.

1  2 2  I + I × I+ I  3   1 = × ( 25A 2 +25A×10A+10A 2 ) = 18A 3 The load resistor loss is PRa = I a2−rms Ra = 325 × 1Ω = 325W I M − rms =

∨

∨

The average load current is ∨ I a = ½  I + I  = ½× ( 25A+10A ) = 17.5A   The power delivered to the back emf is PE −a = I a Ea = 17.5A×170V = 2975W

6.3

♣

Switching classification

There are four principal I-V switching conditions during the commutation (turn-on or turn-off) of a switch, viz.:

• • • •

The total power delivered to the dc motor is Pmotor = PRa + PE −a = 325W+2975W = 3300W iv. The dc motor efficiency is power output 2975W η dc = = × 100 = 90.2% 3300W power input Including switch and diode losses yields total circuit efficiency, that is power output power output ηcircuit = = dc supply power input chopper circuit losses + dc motor power input 2975W = × 100 = 88.3% ( 59.1W+8.4W ) +3300W

Switch characteristics

Hard switching; Soft switching; Resonant switching; and Naturally-commutated switching.

These four possibilities are classified in terms of the switching time ts and the commutation time tq, where tq ≤ ts. Figure 6.11 shows the four electrical cases and specifies the switching and commutation times for each.

• •

Switching time ts is the time for a switch to change from fully on (v = 0, i = IL) to fully off (v =Vs, i = 0), such that no further change occurs in the switch voltage or current due to the change of state. Commutation time tq is associated with the external circuitry and is defined as the time the switch takes to reach zero current at turn-off or to reach zero volts at turn-on. Alternatively, commutation time is the period of switch power loss at turn-on or turn-off, due to the switch changing states.

Power Electronics

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Vs

Vs

vc

IL

W on

on

W off t

tq ts

Vs

vc

W on

IL

ic

t

tq

on

(b)

vc ic

off

W off t

tq

Soft Switching

ts

ts

t q < ts

Vs

vc

IL

W on

IL

ic

t

tq

on

(c)

vc ic

W off

off

ts

t q < ts

Vs

vc

W on = 0

IL

tq

IL

ic

vc

W off ic

(d)

t

off

Naturally-commutated Switching

ts

tq = 0

ts

Figure 6.11. Switch voltage (vc), current (ic), and power loss (Won and Woff) of four switching classifications: (a) hard switching; (b) soft switching; (c) resonant switching; and (d) naturally-commutated switching.

Generally, the switch loss magnitude (stress) for a given set of electrical and thermal operating conditions, decreases when progressing from severe hard switching through to virtually lossless naturally-commutated switching. 6.3.1 Hard switching: tq = ts The turn-on and turn-off switching waveforms in figure 6.11a for an inductive load show that hard switching is characterised by tq = ts. The resistive and inductive switching considered in sections 6.1.1 and 6.1.2 are examples of hard switching. In figure 6.4 for a resistive load, the switching periods ton and toff (ts) correspond to the period of switch losses (tq) during each state transition. In figure 6.9 for the inductive load, the tq periods correspond to the power loss periods at switching (trv + tfi and tfv + tri).


244

6.3.2 Soft switching: tq < ts Figure 6.11b shows typical soft-switching waveforms for turn-on and turn-off. The switching losses are complete before the switch has reached its final steady-state condition. That is, ts > tq such that the periods ts and tq both commence at the same time. At turn-on, the switch voltage reaches zero before the switch current reaches the steady-state full-load value IL. Once the switch voltage reaches zero, the rising current no longer results in a power loss. This I-V characteristic at turn-on (usually involving inductance in series with the switch) is a form of quasi zero current switching, ZCS. The inverse occurs at turn-off. The switch current reaches zero before the switch voltage has settled at the supply voltage level Vs. (Usually involving capacitance in parallel with the switch.) This is a form of quasi zero voltage switching, ZVS. Soft-switching results when auxiliary stress diverting circuits, called snubber circuits, are used, as will be considered in chapters eight and nine. 6.3.3 Resonant switching: tq tq. Switching of the voltage when the switch current is zero, usually at turn-on, is called zero current resonant switching, ZCRS, while commutating the current while the switch voltage is zero, usually at turn-off, is called zero voltage resonant switching, ZVRS. Because the exact instant of zero may vary, being load circuit dependant, some control restriction is inevitable. Zero voltage or current switching can be readily attained with ac mains converter circuits since switching can be synchronised with supply zero voltage crossing, or zero current when the load current reverses due to the supply voltage reversal. 6.3.4 Naturally-commutated switching: W = 0, tq = 0 Figure 6.11d shows switching when the voltage and current are both zero, called naturally-commutated switching. This was a commonly used technique for force turn-off of thyristors before the exploitation of the GTO thyristor. Current from an auxiliary commutation circuit displaces (exceeds) the device principal current and reverse biases the device, at turn-off. The method was not used at turn-on. Commutated turn-on and turn-off occurs in inverter circuits where the switch has an anti-parallel connected diode. When the diode conducts and the switch is on but not conducting, if the load power factor causes the current to reverse, then the main switch automatically starts conducting with the switch voltage at zero because the diode was previously conducting, clamping the switch voltage slightly negative. Naturally-commutated switching occurs for ac mains zero crossing switching, with a purely resistive load such that the load V and I are in phase. Switching losses are virtually zero. 6.4

=0

tq

t

on

t

tq

Resonant Switching

ts

Vs

off

t q = ts

IL

Vs

(a)

ic

Hard Switching

ts

Vs

vc

IL

ic

t

tq

Chapter 6

Switch configurations

Most semiconductor switches are unipolar, that is, allow current and/or voltage to be supported in one direction. The MOSFET allows uncontrolled reverse current flow; hence can not support reverse voltage because of its parasitic body diode. Some structures, like the RCT considered in chapter 3.3.3, integrate an anti-parallel diode with a thyristor. Generally, such integrated approaches sacrifice some electrical characteristics. Many applications require a bi-directional current and/or bi-directional supporting voltage switches, so the basic switches can be configured as shown in figure 6.12, to give the necessary I-V characteristics. The net effect of the bi-directional voltage arrangements is good dynamic electrical characteristics but poor static characteristics. Specifically, the switching performance is as for the principal switch but the on-state loss is that of two series connected devices. In the case of the bidirectional blocking thyristor, the on-state voltage is increased slightly because an n-buffer can not be used in its fabrication. The bi-directional conducting thyristor discussed in chapter 3.3.4 attempts to minimise the sacrificed on-state voltage limitation. A reverse blocking IGBT can also be realised. Die edge passivation of the diode region by a through the die p+ diffusion, plus guard rings, increase processing complexity, and hamper voltage ratings. A punch through IGBT version with reverse voltage blocking properties, is therefore problematic. On-state voltages are increased for a given switching speed and, as with the MOSFET body diode, the non-optimal diode recovery characteristics are a compromise because of the overriding n-substrate low resistivity requirements. See chapter 3.2.4. • Controllable switching devices with reverse blocking capability are usually required for ac to ac converters, half-wave resonant converters, and current fed inverters. • Voltage source inverters, full-wave resonant converters, and dc to dc converters usually do not require switching devices with reverse blocking properties, but may use an antiparallel connected diode.

Power Electronics

245

Chapter 6


246

Problems

I V

6.1.

P rin c ip a l C u rre n t u n id ir e c tio n a l b id ir e c tio n a l

During turn-on and turn-off of a power transistor the current-voltage relationships are as shown in figure 6.13. Calculate the energy loss during both turn-on and turn-off periods and the mean power loss if the transistor is being switched at a frequency of 10 kHz. What is the maximum instantaneous power dissipated? [1.66 mJ, 16.6 mJ, 183 W, 5kW]

unidirectional

RCT

AS C R

AS C R

Voltage

IG B T

tria c

bidirectional

Figure 6.13.

SSCR

6.2.

The equivalent circuit in figure 2.4a involving parameters Eo and Ro can be extended to model a thyristor by replacing the ideal diode by an ideal thyristor. Derive general expressions for the thyristor mean power loss Pd and rms current io with a constant load current Io and switch ontime duty cycle δ. If Eo = 1 V and Ro = 0.01 Ohms, for Io = 50 A and a 25 per cent on-time duty cycle, calculate the thyristor: i. On-state voltage, VF ii. Mean power, Pd iii. rms current, io. [See example 2.1: 1.5 V, 18.75 W, 25 A]

6.3.

If the collector voltage at turn-on falls according to vc = ½Vs (1 + cos π t / To ) for 0 ≤ t ≤ To i. For a resistive load, RL, calculate transistor loss at turn-off. ii. Show that the switching trajectory across the SOA is as for the linear current fall case. iii. Calculate the peak power dissipation and when it occurs.

¥ SSCR

SSCR

RB-IGBT

¥ Can be arranged so that emitters are at the same potential. Switches may be reverse blocking IGBTs. Figure 6.12. Switch configurations for uni-directional and bi-directional I-V characteristics.

6.4.

Reading list Peter, J. M., The Power Transistor in its Environment, Thomson-CSF, Sescosem, 1978.

A transistor is used to switch an inductive load with a current of Im. At transistor turn-off, the collector voltage rises to the supply rail Vs according to vce = ½Vs (1 - cos π t /Tov) for t ≤ Tov, then the collector current falls according to ic = ½Im(1 + cos π t /Toi) for t ≤ Toi. Using the same integration form as in equation (6.10), show that the turn-off loss is P = ½VsIm To where To = Tov + Toi.

Chapter 7


248

Turn off - reducing the drain current to the leakage current level - is achieved by reducing the gate voltage to below the gate threshold voltage level. The drain switching speeds are essentially determined by that speed at which the gate voltage can reach a level above the threshold voltage (for turn-on) or below the threshold voltage (for turn-off). Although the gate-to-source capacitance is an important parameter, the gate-to-drain capacitance is more significant because of the Miller effect, as considered in section 4.4.2. During switching, the dynamic gate-to-drain capacitance can be effectively much larger than the gate-to-source capacitance. The Miller capacitance typically requires more charge for switching than the gate-to-source capacitance.

7 Driving Transistors and Thyristors The thyristor, being a multiple (three) bipolar junction device, is essentially a current-controlled device. As illustrated in figure 7.1a, a current must be supplied between the gate and cathode terminals to produce cathode injection, hence anode current flow, provided the anode is forward biased. The magnitude of gate drive current determines the delay time and the anode current rise time. In gate commutated thyristors, a negative gate current must be produced, the magnitude determining the turnoff delay time and anode current fall time. The power MOSFET and IGBT are voltage controlled devices with turn-on and turn-off requirements fundamentally different to bipolar devices. With the n-channel enhancement-mode power MOSFET and IGBT, a positive voltage must be applied between the gate and source terminals to enhance a channel which allows a drain current, if the drain is positively biased with respect to the source, as shown in figure 7.1b. Generally the MOSFET and IGBT are easier to drive than the bipolar thyristor, and only a few basic considerations are required for MOSFET and IGBT gate circuit implementation. Gate current produces anode current

IA

+

iG

+

MOSFET

74AC132

Figure 7.1. Thyristor and transistor drive requirements: (a) current drive for the bipolar junction thyristor and (b) voltage drive for the MOSFET and IGBT.

7.1

Application of the power MOSFET and IGBT

The MOSFET gate is isolated electrically from the source by a dielectric layer of silicon dioxide. Theoretically no current flows into the gate when a dc voltage is applied to it. In practice, gate current is required to charge device capacitances and a small leakage current of the order of nano-amps does flow in order to maintain the gate voltage. When no voltage is applied between the gate and source terminals (but with zero impedance), the drain-to-source impedance is very high and only a small leakage current of less than a milli-amp flows in the drain, until the applied voltage exceeds the drain-to-source avalanche voltage, VDSS. When a positive gate voltage is applied, an electric field is produced which modulates the drain-tosource resistance. When a gate voltage exceeds the threshold voltage level the channel resistance reduces to a low resistance and drain current flows. The maximum drain current depends on the gate voltage magnitude, assuming that the impedance of the external drain circuit is not current-limiting.

BWW

dv/dt=15kV/µs > td=0.1µs io =±2A 15V-30V

HCPL3210

Power Electronics

249

Chapter 7


250

MOSFETs can also be driven directly from ttl gates. Table 7.2 shows ttl typical current source and sink

capabilities and switching speeds. Low supply voltage, typically 5V, and high internal sourcing impedance characteristics, restrict MOSFET switch-on speed and gate voltage level. The ttl sink capability is significantly higher than source capability, hence a pull-up resistor as shown in figure 7.2c enables the sinking capability to be exploited at turn-on, as well as at turn off. A limitation of using ttl for driving MOSFETs is that the gate voltage is restricted to less than 5V, hence if the drain current is not to be restricted, low gate threshold voltage trench gate MOSFETs and IGBTs are used. An open collector ttl drive technique as shown in figure 7.2d overcomes the gate voltage limitation as well as improving the current source limit. Very fast switching speeds are attained with the capacitive driver shown in figure 7.2e. Such drivers can both source and sink typically 1.5 A in tens of nanoseconds. An isolated gate-to-source drive version is shown in figure 7.2f, where a floating 15 V rail is used and the gate control signal is optically transmitted with high dv/dt capability. The driver incorporates high current output, with modest propagation delays.

74AC132

Figure 7.2. Gate drive circuits for the MOSFET and IGBT: (a) driven from cmos; (b) driven from cmos and an emitter follower; (c) driven from ttl with pull-up resistor which increases sourcing capability; (d) driven from open collector ttl with an external current source; (e) driven from a high-current cmos clock driver; (f) opto-isolated driver circuit; (g) drive circuits for a totem pole connected p and n-channel MOSFET leg; (h) driven from a pulse transformer; and (i) fibre optic translation stage.

7.1.1

(a)

Gate drive circuits

The trench gate n-channel enhancement-mode power MOSFET (or IGBT) with a low threshold voltage interfaces easily with logic level integrated circuits. This allows low-power digital logic circuits to control directly high-power levels. Figure 7.2 shows a series of ttl and cmos circuits driving power MOSFETs, each circuit offering different levels of switching speed and performance. When driving a MOSFET directly from a cmos gate output, as shown in figure 7.2a, only modest rise and fall times can be expected because of the limited source and sink current available from a cmos gate. Figure 7.3a illustrates the output configuration of a typical cmos output stage, which consists of a seriesconnected p and n-channel MOSFET with the gates connected together. The cmos totem pole output stage is driven by a common signal, hence the name complementary mos - cmos - and when the input is high the n-channel device is on and the p-channel off, while when the input is low, the p-channel turns on and the n-channel turns off. However, cmos has a limited current output capability as shown in the 4049 source-to-sink output characteristics in figure 7.3b and c. The cmos gate output has to drive as a load the power MOSFET capacitive gate. In this configuration, the turn-on current is supplied from the pchannel fet, which has the poorer characteristics of the cmos pair. The turn-off current is sunk by the nchannel fet. Table 7.1 shows cmos typical current source and sink capabilities, switching speeds, and output impedance. It will be seen that the best performance, by far, is achieved from the 4049 and 4050 buffers. If shorter delays and faster drain rise and fall times are required there are several ways to obtain them. The simplest is to parallel a number of identical cmos inputs and outputs as shown dotted in figure 7.2a. The additional current capability, with the six parallel connected gates of the 4049, will significantly improve MOSFET switching performance. In figure 7.2b the gate drive current is the output current of the cmos gate multiplied by the gain β of the bipolar transistors. No bipolar saturation times are incurred since the transistors are operating as emitter followers, which cannot saturate. The operating frequency is no longer restricted by the cmos output current limitations.

(b)

(c)

Figure 7.3. CMOS 4049 inverter output: (a) output cmos totem pole; (b) p-channel drain sourcing; and (c) n-channel drain sinking, both at 25°C.

251

Power Electronics

Chapter 7


252

Drive circuits for p-channel MOSFETs may be complicated by the reference signal voltage level, as shown in the series n and p-channel totem pole in figure 7.2g. This figure illustrates how the p-channel drive may be derived by means of a level shifter. The emitter follower, pnp transistor used for turn-on must have a breakdown voltage rating in excess of the totem pole rail voltage. Above 300 V the pnp transistor can be replaced by a diode as shown in figure 7.2d, or a low current high voltage MOSFET. Restricted charging of the translation MOSFET output capacitance can lead to increased delay times. The resistor divider, R1-R2, ensures that the p-channel gate voltage limit is not exceeded. In order to increase gate drive capability R2 can be decreased provided a 15 V Zener is used across the p-channel MOSFET gate to source. The low-voltage npn transistor in the p-channel driver stage is used for fast turn-off, shorting the p-channel source to its gate. A simple method of driving an n-channel MOSFET, with its source not referenced to ground, is shown in figure 7.2h. Electrical (galvanic) isolation is achieved by means of a pulse transformer. The internal parasitic diode in Q1 provides the path for the n-channel MOSFET gate to charge. When the pulse transformer saturates, Q1 blocks any discharge of the gate until turn-off, when a negative transformer pulse turns on Q1, thereby discharging the n-channel gate charge. An alternative translation method using a fibre optic stage is shown in figure 7.2i. The temperatureindependent, high threshold characteristics of 74AC technology is used for a simple detector comparator. A Schmitt input (hysteresis) gate (74AC132) improves noise immunity. In general, translation from ttl levels can be achieved with Zener diode bias circuits. From the circuits in figure 7.2 it is seen that there are two basic types of gate drives. • Low-side • High-side Essentially a low-side driver is one where the control signal and the power device gate are at almost the same potential. The lower switches in bridge legs normally use low-side drivers, while the upper switches require high-side drivers which translate the control signal and gate power to a different potential. The gate drive circuits 7.2a to 7.2e are basic low-side gate drive circuits. The high-side drivers in figures 7.2f to 7.2i translate the control signal to the gate level. Although the gate drive circuits in figures 7.2a to 7.2i translate the control signal to the device gate, these circuits do not address two important gate drive issues. • The derivation of the gate drive supply, particularly for floating gate drives as encountered in inverters. • The derivation of negative gate bias at turn-off for better immunity to false turn-on due to noise and induced Miller charging effects. 7.1.1i - Negative gate drive The gate drive circuits shown in figure 7.2 only clamp the gate to near zero volts during the off period. The lower bridge leg switch in figure 7.4 uses ±15V gate voltages. The complementary buffers drive the gate-source of the shown device in an H-bridge configuration. The buffers require an isolated 15V dc supply. Since the 15V dc supply is isolated, the complementary buffers can be used for high side gate drives, provided the control signal is isolated, as in figure 7.2i. Practically a negative gate bias of -5V is sufficient for noise immunity while any voltage in excess of this unnecessarily increases turn-on delay and increases gate power requirements. Manufacturers are continually improving power device properties and characteristics. Gate threshold voltage levels are constantly being decreased, and coupled with the fact that the threshold voltage decreases with temperature, negative voltage gate drive is necessary for high noise immunity to prevent false turn-on with high power devices. Gate capacitance improves noise immunity. 7.1.1ii - Floating power supplies There are three basic methods for deriving floating power supplies for gate drives. • A low inter-winding capacitance, high-frequency transformer • A capacitive coupled charge pump • A diode bootstrap The upper bridge leg switch Tu in figure 7.4 uses both a diode bootstrap via Dbs and a single ended capacitor charge pump via Ccp, in order to derive gate power. 1 - capacitive coupled charge pump By switching Tcp at high frequency the low-capacitance, high-voltage capacitor Ccp is successively charged through Dcp1 and discharged through Dcp. Discharge through Dcp involves charging Cgs, the gate voltage supply capacitor. The shown charge and discharge paths both rely on either the upper switch Tu or diode Du being in a conducting state.

Power Electronics

253

Chapter 7


254

Vs

Dcp

Vgg

+15V wrt 0V

Dbs

+

Tu

on/off

Cgs

Du

bootstrap circiut Dcp1

off on

+ charge-pump circiut

output

Single rail floating supply

Ccp on/off

Tℓ

Q _ Q

Tcp

Dℓ

0V

Figure 7.4. Typical IGBT bridge leg showing ±15V gate drive on the leg lower switch and charge pump plus boot strap gate supply circuits for the leg upper switch.

2 - diode bootstrap When the lower switch Tℓ or diode Dℓ conduct, high voltage diode Dbs allows the upper gate supply capacitor Cgs to charge from a 15V dc supply which is referenced to the 0V dc rail. When the upper switch or diode conduct, the bootstrap diode is reverse bias and supports Vs + Vgg. Start-up is a problem since the gate of the upper switch Tu is in a high impedance state while its supply is being charged after the lower switch is turned on. For this reason, the boot strap is usually used in conjunction with a capacitor charge pump. The only foolproof method to ensure gate power at all times, particularly at start-up and during prolong on-state periods, is to use a high-frequency (power and/or signal) transformer approach. 7.1.2

Figure 7.5. Typical MOSFET charge transfer characteristics at: (a) turn-on; (b) turn-off; (c) turn-on showing switching parameters; and (d) turn-off showing switching parameters.

Gate drive design procedure

The effective gate to source capacitance, Cin, can be calculated from Cin δ Qg / δVgs

(7.1)

The initial slope of the charge in figure 7.5a, 740 pF, is due to the gate source capacitance charging below the gate threshold level. The next charge section between Qg1 and Qg2 in figure 7.5c is due to the Miller effect. The horizontal charge portion is due to the very high drain-source depletion field capacitance as the drain falls below the gate voltage level. The drain switching times, similar to those derived in 4.4.2, can be calculated from the charge transfer characteristics in figure 7.5, using the following equations. (i) From figure 7.5c, for turn-on Qg 1 Vgg td on = Rg An ( ) (s) (7.2) Vg 1 Vgg - Vg 1 tr =

(ii)

Qg 2 - Qg 1 Vg 2 - Vg 1

Rg An (

Vgg - Vg 1 Vgg - Vg 2

)

From figure 7.5d, for turn-off Qg 2 - Qg 2 Vgg td off = Rg An Vg 2 - Vg 2 Vg 2 tf =

Qg 2 - Qg 1 Vg 2 - Vg 1

Rg An

Vg 2 Vg 1

where Rg is the gate equivalent series resistance and Vg1 = VTH.

(s)

(7.3)

(s)

(7.4)

(s)

(7.5)

The energy required for switching is given by W = ½Qg 3Vgg

(J)

(7.6)

which will be dependent on the drain current and voltage. The gate drive power requirements are given by P = Qgs Vg 3 f s (W) (7.7) Obviously the faster the switching speed requirement, the higher and faster the gate drive current delivery necessary. If only 15 mA is available for gate drive then, based on figure 7.5, switching occurs in about 1 µs (from Q = I×t). This level of performance could be expected with circuit 7.2a, and slower switching for the circuit in figure 7.2c. By employing the gate drive in figure 7.2c, the gate voltage is limited to 5 V, hence the MOSFET represented by figure 7.5 could not be switched. The circuits in figures 7.2b and 7.2d are capable of delivering about 100 mA, which yields switching speeds of the order of 150 ns, with only 50 mW of drive power dissipation at 100 kHz. The drive circuit in figure 7.2e is capable of delivering ± 1.5 A. Hence the device characterised by figure 7.5 can be switched in only 10 ns. Switching times deteriorate slightly if reverse gate-to-source biasing is used for higher noise immunity in the off-state. Analysis of the increase in turn-on delay as a result of the use of negative gate drive is presented in Appendix 4.8.

Power Electronics

255

Example 7.1:

Chapter 7

MOSFET input capacitance and switching times

7.2.1

A MOSFET switching a resistive load has the following circuit parameters: Rg = 47Ω, RL = 100Ω Vgg = 10 V,

Vds = 400 V

Based on the charge transfer characteristics in figure 7.5, calculate the gate input capacitance and switching times for MOSFET turn-on and turn-off. Solution The charge transfer characteristics shown in figure 7.5 are valid for a 100 Ω resistive load and a 0-10 V gate voltage. A 400 V drain switching characteristic is shown.


256

Thyristor gate drive circuits

Only low-power thyristors with amplifying gates can be triggered directly from ttl or cmos. Usually a power interface stage is employed to convert ttl current sink and source levels of a few milliamps up to the required gate power levels. Figure 7.7a and b shows two power interface circuits for triggering a triac. The triac could equally be another thyristor device. An important safety default feature of both these circuits is that no active device exists between the gate and Ml. During the off-state the gate is passively clamped by the resistor Rg to a voltage well below the minimum voltage level for turn-on. Bidirectional gate current can bring the triac into conduction. Figures 7.7c and d show how negative gate turn-on current can be derived.

At turn-on, from figure 7.5a and using equations (7.2) and (7.3) (i) Cin = Cgs = Qg1 / Vg1 = 4.4 nC / 6V = 740 pF td on = 740 pF × 47Ω ℓn (10V/10V-6V) = 31.9 ns (ii)

Cin = (Qg2 - Qg1) / (Vg2 - Vg1) = 5.6 nC / 1.5V = 3.7 nF tr = 3.7 nF × 47Ω ℓn 5.6V/2.5V = 141.3 ns

At turn-off, from figure 7.5b and using equations (7.4) and (7.5) (i) Cin = (Qg3 - Qg2) / (Vgg - Vg2) = 7.5 nC / 2.5V = 3 nF td off = 3 nF × 47Ω ℓn 10V/7.5V = 40 ns (ii) Cin = (Qg2 - Qg1) / (Vg2 - Vg1) = 7.5 nC / 0.9V = 8.3 nF = 8.33 nF × 47Ω ℓn 7.5V/6.6V = 50 ns tf An underestimate of the fall time results if figure 7.5a is used for both turn-on and turn-off calculations (Cin = 3.7 nF and tf = 39.1 ns).

♣

7.2

Application of the Thyristor

The basic gate requirements to trigger a thyristor into the conduction state are that the current supplied to the gate is • of adequate amplitude and sufficiently short rise time • of sufficient duration. The gate conditions are subject to the anode being forward-biased with respect to the cathode. Figure 7.6 illustrates a typical thyristor gate current waveform for turn-on. The initial high and rapid current quickly turns on the device so as to increase the anode initial di/dt capability. After a few microseconds the gate current can be decreased to a value in excess of the minimum gate requirement. After the thyristor has latched on, the gate drive may be removed in order to reduce gate power consumption, namely the losses. In some inductive load applications, where the load current lags, a continuous train of gate pulses is usually applied to ensure turn-on. Gate drives can be divided broadly into two types, either electrically isolated or non-isolated. To obtain electrical isolation usually involves the use of a pulse-transformer or an opto-coupler but above a few kilovolts fibre-optic techniques are applicable. fast rise-time for improved anode initial di/dt

slow fall to prevent unwanted turn-off

(c)

(d)

IG

continuous gate current to maintain all GTO cathode islands in conduction

minimum pulse length to ensure all GTO cathode islands conduct

Figure 7.6. Ideal thyristor gate current waveform for turn-on.

(e)

(f)

Figure 7.7. Integrated circuit compatible triac gate drive circuits: (a) high level ttl activation; (b) low level ttl activation using an interfacing pnp transistor; (c) negative gate drive interface with high ttl output for triac activation; (d) negative gate drive interface with low ttl level for triac turn-on; (e) a triac opto-coupler isolated gate drive used to gatedrive a higher power triac; and (f) a pulse transformer drive isolated gate drive for a thyristor.

Power Electronics


2.5mH is generally sufficient for the circuit to meet the EMC limits. Circuits with intermittent loads, as with drills, sawing machines, and food mixers, are generally outwith EMC filtering regulations.

ac mains voltage

ac mains voltage

(V)

300

R1 5k6Ω

Th2

R2 1k0Ω

3 2 1

R2 D2

R3 150Ω

D1

200

R4 470Ω v

motor

D1

3

100

2 1 0 0

(a)

3 2 1

D2

ac mains voltage

200

R4 470Ω v

C1

motor

D1

180

v

R2

R3 150Ω

135

(degrees, °)

(V)

Th2

R2 2k0Ω

C1 22µF

90

300

R1 5k6Ω ac mains voltage

45

angle

(b)

D1

voltage

i. Vacuum cleaner suction control circuit In the vacuum cleaner suction control circuit in figure 7.8aX the triac is the power control element, itself controlled by a diac which is switched on by charging of C1 through potentiometer R2. The resistance of the diac is virtually infinite as long as its voltage it remains within the breakover voltage limits, ±VBO. During each half cycle of the mains sinewave, C1 charges until the voltage across it exceeds the diac breakover voltage. The diac then switches on and C1 discharges itself into the gate of the triac which then switches on. Diodes D1 and D2 stabilise the supply voltage to the charging circuit so that its operation is independent of mains voltage fluctuations. If -VBO and +VBO are equal and opposite, the triac will be triggered at the same time after the start of either a positive or negative half sinusoidal cycle. The conduction angle, and therefore the speed of the motor and the cleaner suction, is determined by the adjustment of R2. Preset potentiometer R3 is used to set the minimum suction level. The width and amplitude of the trigger pulses are kept constant by gate resistor R4. The zinc oxide voltage dependent resistor, U, minimises the possibility of damage to the triac due to high voltage transients that may be superimposed on the mains supply voltage.

258

v

If electrical isolation between the control circuitry and the power thyristor circuit is required, a simple triac opto-coupler can be employed as shown in figure 7.7e. The photo-triac is optically turned on which allows bidirectional main triac gate current to flow, the magnitude of which is controlled by the highvoltage resistor Rg. If the main device is an SCR, an opto-coupled SCR can be used for isolation and unidirection gate triggering current. When suitable voltage rails are not available or isolation is required, a pulse transformer drive circuit can be employed as shown in figure 7.7f. The diode/Zener diode series combination across the pulse transformer primary provides a path for primary magnetising current decay at turn-off and prevents saturation. The resistor R limits the secondary current into the SCR gate. This resistor can be placed in the pulse transformer primary or secondary by transforming the resistance in the turns ratio squared. If R is in the primary circuit and transformer saturation inadvertently occurs, the resistor R limits the current and protects the switching transistor Ts. The transformer secondary resistor R2 is employed to decrease the gate to cathode impedance, thereby improving dv/dt capability, while the gate diode Dr prevents possible reverse gate voltage breakdown after Ts is turned off and the output voltage reverses during core reset. The transformer duty cycle must satisfy toff Vz ≥ ton Vs, neglecting R.

Chapter 7

voltage

257

3

100

2 1 0 0

(c)

ii. Lamp dimmer circuit A light dimmer circuit using a triac power control element, triggered via the diac, is shown in figure 7.8b. The potentiometer R2 setting determines the phase difference between the mains sine wave and the voltage across C2. This in turn sets the triac triggering angle and the lamp intensity. The resistance of the diac is high as long as the voltage across it remains within its breakover voltage limits, ±VBO. Each half cycle of the mains charges C2 via R1, R2 and R3 until the voltage being applied to the diac reaches either of its breakover levels. The diac then conducts and C2 discharges into the gate of the triac, switching it on. If –VBO and +VBO are equal and opposite, the triac will be triggered at the same time after the start of either a positive or negative half sinusoidal cycle. C1 prevents the voltage across C2 from changing abruptly after triggering, thus preventing progressively alteration of the phase relationship between the mains voltage and voltage across C2. It thus prevents an undesirable hysteresis effect. The voltage across C1 partially restores the voltage across C2 after triggering and thereby minimizes the hysteresis effect. Gate resistor R4 keeps the width and amplitude of the trigger pulses constant. The VDR minimizes the possibility of the triac being damaged by high voltage transients that may be superimposed on the mains supply voltage. Some form of filter is needed to comply with regulations concerning conducted and radiated interference. The simple LC filter shown within the dashed-lined box in figure7.8b is often adequate. The values of the filter components will vary, but a combination of 0.15mF capacitor and a low Q inductor of

R3 150Ω

C1 22µF 40V

3 2 1

C1 R4 500Ω

v D1

ac mains voltage

200

R3

motor

180

(V)

R2

D2

135

(degrees, °)

v

R2 2k0Ω 1W

90

300

R1 Th2

45

angle

D1

voltage

Figure 7.8. Circuit diagram of: (a) vacuum cleaner suction controller and (b) a lamp dimmer.

ac mains voltage

R1 5k6Ω 6W

(d)

3

100

2 1 0

(e)

(f)

0

45

angle

90

135

180

(degrees, °)

Figure 7.9. Thyristor speed control circuit and gate waveforms using back EMF feedback: (a) basic controller, (b) improved low speed controller, and (c) improved low and high speed controller.

iii. Back EMF feedback circuits A motor speed control circuit, for electric drills, that employs back EMF to compensate for changes in motor load and mains voltage is shown in figure 7.9a. The series resistors R1, R2, R3 and diode D1 provide a positive going reference potential to the thyristor gate via diode D2. Diode D1 is used to reduce the dissipation in the series resistors and diode D2 isolates the trigger circuit with the thyristor in the onstate. When the thyristor is not conducting the motor produces a back EMF voltage across the armature proportional to residual flux and motor speed. This appears as a positive potential at the thyristor cathode.

Chapter 7

(V)

300

ac mains voltage

voltage

v

200

100

motor back emf

As described, the charging of capacitor C1 through resistor R1 determines the rate of rise of voltage at the thyristor gate during the positive half cycle. However, resistor R1 must also have a resistance such that several times the maximum thyristor gate current passes through the RC network to D1. This current will then give consistent speed settings with the spread of thyristor gate currents when the minimum speed is set by resistor R4. The positive slope value of the thyristor gate voltage is fixed according to the motor used. A motor that gives a smooth back EMF voltage will allow a low slope value to be used, giving good torque speed characteristics. Some motors have coarser back EMF waveforms, with voltage undulations and spikes, and a steeper slope of thyristor gate voltage must be used in order to obtain stable motor operation. The value of capacitor C1 is chosen to provide the required positive slope of the thyristor gate voltage. Some calculations have been made on the circuit of figure 7.9e simplified to the form of figure 7.11a, where it is assumed that current flowing to the thyristor gate is small compared with the current flowing through resistor R1. An expression is derived later for the voltage that would appear at the anode of D2 in terms of R1, R2 and C1. Component values have been substituted into the expression to give the thyristor gate waveforms shown in figure 7.11b.

45

angle

90

135

180

(V)

0 0

R1

(degrees, °) R2

C1

R3

Stable Firing at Small Conduction Angles The trigger network of the circuit shown in figure 7.9c has been modified by the addition of a capacitor C1 and diode D1. The diode clamps the capacitor potential at zero during the negative going half cycles of the mains input. The waveform developed across the capacitor has a positive slope to some 140°, allowing thyristor triggering to be delayed to this point. As R2 is decreased, the peak of the waveform at the gate moves towards 90° as shown in figure 7.9d. As the speed increases, the no load firing angle also advances by a similar amount so stability will be maintained. This circuit will give smoother and more stable performance than the circuit of figure 7.9a. It will, however, give a marginally greater speed drop for a given motor loading at low speed settings. At the maximum speed settings the circuit of figure 7.9a approximates to that of figure 7.9c. Improved Motor Performance with Stable Firing The circuits in figure 7.9 a and c have gate voltage waveforms that are of near linear slope from the zero point of each positive half cycle, as seen in figures 7.9 b and d. This means that the only time that the thyristor can be fired early in the mains cycle, say at 20°, is when the back EMF and hence motor speed is low. This effect tends to prevent smooth running at high speeds and high loads. Stable triggering, at low angles, can be achieved if the gate voltage ramp starts each cycle at a small positive level. This means that the time to reach the minimum trigger voltage is reduced. This is achieved by the circuit in figure 7.9e, where the capacitor C1 is charged during positive half cycles via resistor R1 and diode D1. During negative half cycles the only discharge path for capacitor C1 is via resistors R2 and R3. Diode D1 also prevents C1 from being discharged as the thyristor switches off by the inductively generated pulse from the motor. As the value of resistor R2 is increased, capacitor C1 is discharged less during negative half cycles but its charging waveform remains substantially unchanged. Hence the result of varying R2 is to shift the dc level of the ramp waveform produced across C1. Diode D2 isolates the triggering circuit when the thyristor is ON. Resistor R4 adjusts minimum speed, and by effectively bleeding a constant current, in conjunction with the gate current from the triggering circuit, it enables resistor R2 to give consistent speed settings.

i2

C1

30

R2 = 1500Ω

33µF 47µF 68 µF

25

i D2

Figure 7.10. Waveforms with a dc gate supply.

260

Circuit Design If the speed controller is to be effective it must have stable thyristor firing angles at all speeds and give the best possible speed regulation with variations of motor load. The circuit in figure 7.9e gives a motor performance that satisfies both these requirements. There are two factors that are important in the circuit operation in order to obtain the mentioned requirements. - The value of positive slope of the waveform appearing at the thyristor gate. - The phase angle at which the positive peak gate voltage is reached during a positive half cycle of mains input.

i1

v D1

vg

A thyristor fires when its gate potential is greater than cathode potential by a fixed amount. Depending on the waveform shape and amplitude at the gate, the circuit may function in several modes. If, for example, during positive half cycles a constant dc potential was applied at the gate, figure 7.10, the thyristor would continue to fire at the beginning of each cycle until the back EMF was large enough to prevent firing. Thyristor firing would then continue intermittently at the beginning of the positive cycles to maintain some average motor speed. Referring to figure 7.9a the waveform appearing at the thyristor gate will approximate to a half sine wave, figure 7.9b. As a result it is impossible for the firing angle to be after 90° - the most positive value of the trigger potential. At lower motor speeds the firing angle might need to be 130° for smooth operation. If the maximum firing angle is limited to 90° then intermittent firing and roughness of motor operation will result. If, however, the waveform at the gate has a positive slope value to an angle of at least 130° then it will be possible to have a stable firing point at low speeds. Such a waveform can be produced if there is some phase shift in the trigger network.


20

Gate voltage

Power Electronics

259

15

33µF 47µF 68 µF

R2 = 820Ω

10 33µF 47µF 68 µF

R2 = 220Ω

5 0 0

50

100

Phase angle delay

150

α

(degrees, °)

Figure 7.11. Improved controller: (a) simplified firing circuit and (b) calculated gate waveforms.

In order to adjust the circuit to suit a given motor, the back EMF of the motor must be known. This may be measured using the arrangement shown in figure 7.12. The voltage appearing across the motor is measured during the period when the series diode is not conducting (period A). The voltage so obtained will be the motor back EMF at its top speed on half wave operation, and corresponds to the back EMF that would be obtained from the unloaded motor at its highest speed when thyristor controlled. In practice, since the mains input is a sine wave, there is little increase in the ’no load’ speed when the firing angle is reduced to less than about 70°. The value of resistor R2 in figure 7.9e determines the motor ’no load’ speed setting. The waveforms of figure 7.11b may be used as a guide to obtaining the value of this resistor. It must be chosen so that at 70° and at its highest value, the gate voltage is higher than the measured back EMF by about 2V - the forward gate/cathode voltage of the thyristor. The thyristor is turned ON when a trigger waveform, shown in figure 7.11b, exceeds the back EMF by the gate/cathode voltage. So, if the back EMF varies within a cycle then there will be a cycle to cycle variation in the firing angle. Normally, random variations of the firing angle by 20° are tolerable. If, for example, there were variations in the back EMF of 1V, then with a firing angle of 70°and a capacitor of 32µF, the variation of firing angle would be about 12°. With capacitor values of 50µF and 64µF the firing angles variations would be 19° and 25° respectively. Therefore, a capacitance of 50µF would be suitable.

Power Electronics

261

Chapter 7

Back emf period A

Diode conducting period B

300

ac mains voltage

Simplifying

100

C1 Vback emf 0 0

45

90

angle

135

180

(degrees, °)

Figure 7.12. Back EMF measurement circuit and typical voltage waveforms.

series diode figure 7.12 circuit figure 7.9a circuit figure 7.9e

Motor speed

1500

500 0 0

½

1

Motor torque

1½

T

2

2½

4000

0 0.1

0.3

0.4

Motor torque

0.2

T

0.5

0.6

(Nm)

Figure 7.13. Torque-speed load performance: (a) hand drill and (b) food mixer.

Circuit Calculations The following analysis derives an expression for voltage v at the anode of D2. This expression can be used to produce the gate voltage waveforms shown in figure 7.11b. The analysis assumes that the current drawn by the thyristor gate is negligible in comparison with the current flowing in R1. The charging current i1 for capacitor C1 in figure 7.11a, is given by:

i1 =

dq dv = C1 dt dt

and

i1 =

v R2

1 dv 1  E E +v  +  − = dt  R1 R2  π R1 R1

2   cos 2ωt  ½ sin ωt − 3π  

Solving for v, the voltage that the trigger circuit would apply to the gate (assuming the gate draws no current), assuming R1+R2 >> √2ωC1R1R2:

R2E π (R1 + R2 ) R2E 2 1  ωC 1R1R2 sin 2ωt − (R1 + R2 ) cos 2ωt  (R1 + R2 ) sin ωt − ωC 1R1R2 cos ωt − 2ω 2C 12R12R22  3π 3π 

Solving this equation for different values of C1 and resistances for R2 gives the curves shown in figure 7.11b. 7.2.2

2000

0

(Nm)

C1

+

circuit figure 7.9a

6000

circuit figure 7.9c

1000

Then

circuit figure 7.9e

8000

1 dv 1  f (E ) +v  +  = dt R1  R1 R2 

Fourier analysis of a half sinewave gives: 1 2 cos n θ  f (E ) = E  + ½ sin θ −  ∑ π n =0,2,4,6.. n 2 − 1  π Neglecting the Fourier terms for n > 2, then 1 dv 1  E 1 2  +v  +  = C1 cos 2ωt   + ½ sin ωt − dt 3π   R1 R2  R1  π

v =

series diode figure 7.12

12000 10000

N

N

rpm

3000

Motor speed

rpm

Performance The torque speed characteristics of the three circuits, when used to drive an electric drill, are compared in figure 7.13a. It may be seen that the circuit of figure 9c has a poorer performance than the two other circuits. That of figure 7.9e may be seen to give a similar performance to the circuit of figure 7.9a at low speeds but, at high speeds and torques, it is better. It should be noted that the circuits of figure 7.9 parts c and e provide low speed operation free from the intermittent firing and noise of the figure 7.9a circuit. Figure 7.13b compares the circuits of figure 7.9a and e when the load is a food mixer motor.

2000

f (E ) − v dv v = C1 + R1 dt R2

where i, i1 and i2 are instantaneous currents.

v voltage

ac motor

2500

R1

Therefore

200

ac mains voltage

262

Representing a mains half sine wave by f(E) , where E is the peak mains voltage. f (E ) − v = i1 + i 2 i =

(V)

D


Thyristor gate drive design

In order to design a thyristor gate interface circuit, both the logic and thyristor gate requirements must be specified. Consider interfacing a typical ttl-compatible microprocessor peripheral which offers the following specification I OH = 0.3mA @ VOH = 2.4V I OL = 1.8mA @ VOL = 0.4V Vcc = 5V

These specifications are inadequate for turning on a power thyristor or an optical interfacing device. If the power thyristor gate, worst case requirements are I GT = 75 mA, VGT = 3 V @ - 65°C then a power interfacing circuit is necessary. Figure 7.14 shows an interfacing circuit utilising a pchannel MOSFET with the following characteristics Cgs = 400 pf VTH = 3.0V Rds ( on ) = 10 ohms

I d = 0.5A

The resistor R1 limits the MOSFET Cgs capacitance-charging current and also specifies the MOSFET turnon time. If the charging current is to be limited to 1.8 mA when VOL = 0.4 V, then R1 = (Vcc - VOL ) / I OL (ohms)

= (5V - 0.4V) /1.8mA = 2.7 kilohms

Power Electronics

263

Chapter 7

i.


For R = 1 kΩ vc = 237.36 ∟-8.4° that is, vc = 335.8 sin (ωt - 8.4°) The diac conducts when vc = 30V, that is minimum delay = ωt = 8.4° + sin-1 (30V/335.8V) = 13.5°

Figure 7.15. Light dimmer.

Figure 7.14. Interfacing a microprocessor to a power thyristor.

A smaller resistance could be used but this would not preserve the microprocessor low-voltage output level integrity if it were also being used as input to ttl logic. The MOSFET will not turn on until Cgs has charged to 3 V or, with a 5 V rail, approximately one R-C time constant. That is tdelay = Ri Cgs (s) = 2.7 kilohms × 400 pF = 1 µs The MOSFET must provide the thyristor gate current and the current through resistor R3 when the gate is at 3 V. The maximum value of resistor R2 is when R3 = ∞ and is given by Vcc - VGT - I GT × Rds ( on ) R2 = I GT 5V - 3V - 75 mA x 10Ω = 75 mA

= 16.6 ohms

Use R2 = 10 ohms. The resistor R3 provides a low cathode-to-cathode impedance in the off-state, thus improving SCR noise immunity. When VGT = 3 V V - VGT I d = cc (A) Rds ( on ) + R2 5V-3V = = 100 mA 10Ω+10Ω of which 75 mA must flow into the gate, while 25 mA can flow through R3. That is R3 = VGT /( I d - I GT ) (ohms) = 3 V/25 mA = 120 ohms After turn-on the gate voltage will be about 1 V, hence the MOSFET current will be 200mA. Assuming 100 per cent on-state duty cycle, the I2R power loss in the MOSFET and resistor R2 will each be 0.4 W. A 1 W power dissipation 10 ohm resistor should be used for R2.

Example 7.2:

A light dimmer

A diac with a breakdown voltage of ±30V is used in a light dimming circuit as shown in figure 7.15. If R is variable from 1kΩ to 22kΩ and C = 47nF, what are the maximum and minimum firing delays? What is the controllable output power range with a 10Ω load resistor? Solution The capacitor voltage vc is given by - j / ωC vc = × 240∠0° R - j / ωC 1 = × 240∠0° 1 + jωCR

264

ii.

For R = 22 kΩ vc = 70.6 ∟-72.8° that is, vc = 99.8 sin (ωt – 72.8°) The diac conducts when vc = 30V, that is minimum delay = ωt = 72.8° + sin-1 (30V/99.8V) = 92° The maximum power output, if continuous conduction were possible, is Plo = 240V 2 /10Ω = 5760W. From equation (12.16), the output power for a resistive load is given by 2 2 2α −sin2α V Po = rms = V 1 − (W) 2π R R 2402 × 1 − 2×92°−sin2×92° = 2862W Minimum power at α = 92° (1.6 rad) is Po = 2π 10Ω

{

}

{

}

{

}

2402 × 1 − 2×13½°−sin2×13½° = 5536W Maximum power at α =13½° (0.24 rad) is Po = 2π 10Ω

♣

7.3

Drive design for GCT and GTO thyristors

The gate turn-off thyristor is not only turned on from the gate but, as its name implies, is turned off from its gate with negative gate current. Basic GTO thyristor gate current requirements are very similar to those for the power bipolar transistor (now virtually obsolete) when reverse base current is used for fast BJT turn-off. Figure 7.16 shows a gate drive circuit for a GTO thyristor which is similar to that historically used for power bipolar junction transistor base drives. The inductor L, in figure 7.16, is the key turn-off component since it controls the di/dt of the reverse gate current. The smaller the value of L, the larger the reverse di/dt and the shorter the turn-off time. But with a shorter turn-off time the turn-off gain decreases, eventually to unity. That is, if the GTO thyristor is switched off rapidly, the reverse gate current must be of the same magnitude as the anode current to be extinguished. A slowly applied reverse gate current di/dt can produce a turn-off gain of over 20 but at the expense of increased turn-off saturation delay and switching losses. For the GTO thyristor L is finite to get a turn-off gain of more than one, while to achieve unity gain turn-off for the GCT, L is minimised. The GTO thyristor cathode-to-gate breakdown voltage rating VRGM specifies the maximum negative rail voltage. A level of -15 to -20V is common, and for supply rail simplicity a ± 15 V rail may be selected. Resistor R4 limits the base current of Tt. If an open collector ttl driver is employed, the current through R4 is given by I OL = (Vcc − VbeT − VDb − VOL ) / R4 (A) t

For the open collector 74 ttl series, IOL = 40 mA when VOL = 0.5 V whence R4 can be specified. The resistor R3 speeds up turn-off of Tt. It is as large as possible to ensure that minimal base current is diverted from Tt. Diodes Db and Das form a Baker’s clamp, preventing Tt from saturating thereby minimising its turn-off delay time.

Power Electronics

265

Chapter 7

Ron

DDbb DDasas R1

R4

266

The turn-on and turn-off BJT output totem pole in figure 7.16 can be replaced by suitable n-channel MOSFET circuitry in high power GCT and GTO thyristor applications. In high power IGCT applications, MOSFETs and rail decoupling electrolytic capacitors are extensively parallel connected. Typically 21 capacitors and 42 MOSFETs are parallel connected to provide a low impedance path for unity anode current extraction from the GCT gate. The gate inductance (including the GCT internal package inductance) is minimised, whence L is zero. Typically, the IGCT gate drive, gate connection, and internal package inductance are each about 2nH. This is achieved by minimising lengths, capacitive decoupling, and using parallel go and return paths. As a result, gate reverse di/dt’s of over 5kA/µs are attainable with a -15V dc negative gate supply.

R3 Tt


Ls

Table 7.3: Gate drive isolation techniques summary

Tn

X Tp

Roff

R2

Technique

data transfer

power transfer

Transformer

direct signal coupling

direct magnetic transfer

opto-coupler

slow, with capacitive effects

n/a

fibre optics

fast, virtually no voltage limit

n/a

charge couple

n/a

requires switching

bootstrap

n/a

requires switching

comments duty cycle limited corona breakdown limit voltage and dv/dt limit best signal transmission at MV and HV induced effects between ground level and gate level, LV application

Figure 7.16. Gate drive circuit and anode snubber circuits for a GTO thyristor.

The two driver transistor Tn and Tp should

• • •

Reading list

have high gains be fast switching have collector voltage ratings in excess of Vcc + VEE.

International Rectifier, HEXFET Data Book, HDB-5, 1987. Peter, J. M., The Power Transistor in its Environment, Thomson-CSF, Sescosem, 1978.

The GTO thyristor gate turn-on current is determined by resistor Ron, which is specified by V − V − VGC (Ohms) Ron = cc ceT IG The power rating of Ron is given by PR = δ (Vcc − VceT − VGC ) I G (W) n

on

Siliconix Inc., Mospower Design Catalog, January 1983.

n

where δ is the maximum on-state duty cycle. The capacitor Con, in parallel with Ron, provides a short current boost at turn-on, as shown in figure 7.6, thereby speeding up turn-on, increasing turn-on initial di/dt capability, and reducing turn-on losses. The series resistors R1 and R2 bias the bases of the totem pole level shift driver and, for an on-condition, the potential of point X in figure 7.16 is given by VX = VbeTn + VGC (V) The total current flow through R1 is made up of the transistor Tn base current and that current flowing through R2, that is I V + VEE I R1 = G + X (A) R2 βT n

Grafham, D. R. et al., SCR Manual, General Electric Company, 6th Edition, 1979.

Problems 7.1.

Calculate suitable resistor values for the triac gate drive circuit in figure 7.7a, assuming a minimum gate current requirement of 50 mA and the gain of Q1 is 50 at 50 mA.

7.2.

Repeat problem 7.1 for the circuits in figures • 7.7b • 7.7c • 7.7d.

7.3.

Repeat example 7.2 assuming a 2V triac gate threshold voltage for turn-on.

from which R1 = (Vcc - VX ) / I R1

The power rating of R1 is

PR = δ (Vcc − VX ) I R 1

1

(ohms)

(W)

For fast turn-off, if the reverse gate current at turn-off is to be of the same magnitude as the maximum anode current, then R2 must allow sufficient base current to drive Tp. That is VX + VbeT R2 = (ohms) I c / ββ p p

Once the gate-to-cathode junction of the GTO has recovered, the reverse gate current decays to the leakage level. The power rating of R2 can be low at lower switching frequencies. The small inductor L in the turn-off circuit is of the order of microhenrys and it limits the rate of rise of reverse gate current, while Roff damps any inductor current oscillation.

Chapter 8

8.1

s t r a y

All power switching devices attain better switching performance if some form of switching aid circuit, called snubber, is employed. Snubber activation may be either passive or active which involves extra power switches. Only passive snubbers, which are based on passive electrical components, are considered in this chapter, while active snubbers are considered in Chapter 9. Fundamentally, the MOSFET and IGBT do not require switching aid circuits, but circuit imperfections, such as stray inductance and diode recovery, can necessitate the need for some form of switch snubber protection. Protection in the form of switching aid circuits performs three main functions: Divert switching losses from the switch thereby allowing a lower operating temperature, or higher electrical operating conditions for a given junction temperature. Prevent transient electrical stressing that may exceed I-V ratings thereby causing device failure. Reduce conducted and radiated electromagnetic interference

Every semiconductor switching device can benefit from switching protection circuits, but extra circuit component costs and physical constraints may dictate otherwise. The bipolar diode suffers from reverse recovery current and voltage snap which induces high but short duration circuit voltages. These voltage transients may cause interference to the associated circuit and to nearby equipment. A simple series non-polarised R-C circuit connected in parallel to the stressed or offending device is often used to help suppress the voltage oscillation at diode turn-off. Such a suppression circuit can be effectively used on simple mains rectifying circuits when rectification causes conducted and radiated interference. Although the MOSFET and IGBT can usually be reliably and safely operated without external protection circuitry, stringent EMC application emission restrictions may dictate the use of snubbers. In specific applications, the IGBT is extensively current derated as its operating frequency increases. In order to attain better device current utilization, at higher frequencies, various forms of switching aid circuits can be used to divert switching losses from the stressed semiconductor switch. Generally, all thyristor devices benefit from a polarised turn-on switching aid circuit, which is based on a series connected inductor that is active at thyristor turn-on. Such an inductive turn-on snubber is obligatory for the high-power GCT and GTO thyristor. In order to fully utilise the GTO thyristor, it is usually used in conjunction with a parallel-connected capacitive turn-off snubber, which decreases device stressing during the turn-off transient. Triacs and rectifier grade SCRs and diodes tend to use a simple R-C snubber connected in parallel to the switch to reduce interference. The design procedure of the RC snubber for a diode is different to that for the R-C snubber design for a thyristor device, because the protection objectives and initial conditions are different. In the case of a thyristor or rectifier diode, the objective is to control both the voltage rise at turn-off and recovery overshoot effects. For the fast recovery diode or any high-speed switch, the principal objectives are to control the voltage overshoot magnitude at diode snap recovery or at turn-off respectively, which are both exacerbated because of stray circuit inductance carrying current.

BWW

The non-polarised R-C snubber

L O A D


• •

268

The series R-C snubber is the simplest switching aid circuit and is connected in parallel to the device being aided. It is characterized by having low series inductance and a high transient current rating. These requirements necessitate carbon type resistors for low inductance, below a few watts, and metal film resistors at higher powers. The high current and low inductance requirements are also provided by using metallised, polypropylene capacitors with high dv/dt ratings of typically hundreds of V/µs. Theoretically a purely capacitive snubber would achieve the required protection objectives, but series resistance is added to decrease the current magnitude when the capacitor is discharging and to damp any voltage oscillation by dissipating the oscillatory energy generated at turn-off when an over-voltage tends to occur.

8

•


s n u b b e r

Figure 8.1. MOSFET drain to source R-C snubber protection: (a) MOSFET circuit showing stray inductance, Ls, and R-C protection circuit and (b) R-C snubber optimal design curves.

8.1.1

R-C switching aid circuit for the GCT, the MOSFET, and the diode

In figure 8.1a, at switch turn-off, stray inductance Ls unclamped by the load freewheel diode, Df, produces an over voltage Vˆ on the MOSFET or IGBT. The energy associated with the inductor can be absorbed in the shown drain to source connected R-C circuit, thereby containing the voltage overshoot to a controlled safe level. Such an R-C snubber circuit is used extensively in thyristor circuits, 8.1.2, for dv/dt protection, but in such cases the initial current in the stray inductance is assumed zero. Here the initial inductor current is equal to the maximum load current magnitude, Iℓ. The design curves in figure 8.1b allow selection of R and C values based on the maximum voltage overshoot Vˆ and an initial current factor χ, defined in figure 8.1b. The C and R values are given by C = Ls ( IA / χ Vs ) 2 (F) (8.1) R = 2 ξ Vs χ / IA (Ω) (8.2) If the R-C circuit time constant, τ = RC, is significantly less than the MOSFET voltage rise and fall times, trv and tfv, at reset (when the capacitor is discharged through the resistor and switch at turned on), a portion of the capacitor energy ½CV , is dissipated in the switch, as well as in R. The switch appears as a variable resistor in series with the R-C snubber. Under these conditions (tfv and trv > RC) the resistor power loss is approximately by PR = PRon + PRoff 2

s

=

τ τ P + ( P + PL 0 ) τ + t fv C 0 τ + trv C 0

(W)

(8.3)

where PC 0 = ½CVs f s and PL 0 = ½ Ls I f s otherwise (tfv and trv < RC) the resistor losses are the energy to charge and discharge the snubber capacitor, plus the energy stored in the stray inductance, that is 2PC0 + PL0. Note the total losses are independent of snubber resistance. The snubber resistor determines the time over which the energy is dissipated, not the amount of energy dissipated. When the R-C snubber is employed across a fast recovery diode, the peak reverse recovery current is used for Iℓ in the design procedure. 2

2 A

Power Electronics

269

Chapter 8


270

Example 8.1: R-C snubber design for MOSFETs A MOSFET switches a 40 A inductive load on a 200 V dc rail, at 10 kHz. The unclamped drain circuit inductance is 20 nH and the MOSFET voltage rise and fall times are both 100 ns. Design a suitable R-C snubber if the MOSFET voltage overshoot is to be restricted to 240 V (that is, 40V overshoot, viz. 20%). Solution From figure 8.1b, for 20 per cent voltage overshoot R-C snubber

ξ = 1.02, χ = 0.52 Using equations (8.1) and (8.2) for evaluating C and R respectively, 2

40A   C = Ls ( I A / χ Vs ) 2 = 20nH   = 3nF  0.52×200V  0.52×200V R = 2 ξ Vs χ / I A = 2 × 1.02 × = 5.3Ω 40A Use C = 3.3 nF, 450V dc, metallised polypropylene capacitor and R = 5.6 Ω.

Figure 8.2. Thyristor (triac) ac circuit with an R-C snubber circuit.

Since the RC time constant, 18.5ns, is short compared with the MOSFET voltage transient times, 100ns, the resistor power rating is given by equation (8.3). PC 0 = ½CVs2 f s = ½×3.3nF ×200 2 ×10kHz = 2.64W PL 0 = ½ Ls I A2 f s = ½×20nH × 402 × 10kHz = 0.16W PR =

18.5ns 100ns + 18.5ns

×2.64W +

18.5ns 100ns + 18.5ns

× (2.64W + 0.16W) = 0.85W

Use a 5.6 Ω, 1 W carbon composition resistor for low self inductance, with a working voltage of at least 250V dc. Parallel connection of two 12Ω ½W, carbon composition resistors may be necessary since resistance values below 10Ω are uncommon. The MOSFET switching losses are 2WC 0 + PL 0 − 0.85W = 4.95W higher than those incurred by switching un-aided at 200V and 40A. From equations 6.9 and 6.10, the switching losses would be at least 8W, (4W+4W).

Figure 8.3. Non-polarised R-C snubber equivalent circuit showing the second-order output response eo to a step input voltage es.

♣

8.1.2

Non-polarised R-C snubber circuit for a converter grade thyristor and a triac

The snubber circuit for a low switching frequency thyristor is an anode-to-cathode parallel connected RC series circuit for off-state voltage transient suppression. Thyristor series inductance may be necessary (forming a turn-on snubber) to control anode di/dt at turn-on. This inductive snubber is essential for the GCT and the GTO thyristor, and will be considered in section 8.3.3. Off-state dv/dt suppression snubber Thyristors, other than the GCT and the GTO thyristor, normally employ a simple R-C snubber circuit as shown in figure 8.2. The purpose of the R-C snubber circuit is not primarily to reduce turn-off switching loss but rather to prevent false triggering (turn on) from applied or reapplied anode dv/dt, when the switch is in a forward voltage blocking off-state. Any thyristor rate of rise of forward-voltage anode dv/dt produces a central junction charging current which may cause the thyristor to inadvertently turn on. The critical dv/dt is defined as the minimum value of dv/dt which will cause switching from the off-state to the on-state. In applications as shown in figure 8.2, an occasional false turn-on is generally not harmful to the triac or the load, since the device and the load only have to survive the surge associated with a half-a-cycle of the ac mains voltage supply. In other applications, such as reversible converters, a false dv/dt turn-on may prove catastrophic. A correctly designed snubber circuit is therefore essential to control the rate of rise of anode voltage. The action of this R-C snubber circuit relies on the presence of inductance in the main current path. The inductance may be stray, from transformer leakage or a supply, or deliberately introduced. Zero inductor current is the initial condition, since the device is in the off-state when experiencing the anode positive dv/dt. Analysis is based on the response of the R-C portion of an L-C-R circuit with a step input voltage and zero initial inductor current. Figure 8.3 shows an L-C-R circuit with a step input voltage and the typical resultant voltage across the SCR or R-C components. The circuit resistor R damps (by dissipating power) any oscillation and limits the capacitor discharge current through the SCR at subsequent SCR device turn-on initiated from the gate. The snubber resistor dissipates power even if the triac is not switching, since the snubber capacitor voltage alternates, tracking the ac voltage supply.

1

(0.265, 0.81)

∧

Figure 8.4. Variation of snubber peak voltage, eo, maximum deo /dt, S ; and peak current, Ip; with L-C-R damping factor ξ.

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Based on the snubber∧ circuit analysis presented in the appendix in section 8.5 at the end of this chapter, the maximum dv/dt, S , which is usually specified for a given device, seen by the SCR for a step input of magnitude es, is given by ∧

S = es R / L (V/s) for a damping factor of ξ > ½. That is, after rearranging, the snubber resistance is given by ∧

R = L S / es while the snubber capacitance is given by 4ξ 2 es C= ∧ RS

(8.4)

(ohms)

(8.5)

(F)

(8.6)

and the peak snubber current is approximated by e 2ξ Iˆ = s (A) for ξ < 1. R 1−ξ 2


Chapter 8

272

Variations of the basic R-C snubber circuit are shown in figure 8.5. These circuits use extra components in an attempt to control SCR initial di/dt arising from snubber discharge through RL at thyristor turn-on. Figure 8.5a has the disadvantage that three series devices (C-Rs-D) provide turn-off protection. The parasitic series inductance can be decreased by using a turn-off snubber with two series components (C-D), as shown in figure 8.5b. An R-C snubber can be used across a diode in order to control voltage overshoot at diode snap-off during reverse recovery, as a result of stray circuit inductance, as considered in 8.1.1. The R-C snubber can provide decoupling and transient overvoltage protection on both ac and dc supply rails, although other forms of R-C snubber circuit may be more applicable, specifically the soft voltage clamp.

(8.7)

Figure 8.4 shows the variation of the different normalised design factors, with damping factor ξ.

Example 8.2:

Non-polarised R-C snubber design for a converter grade thyristor

Design an R-C snubber for the SCRs in a circuit where the SCRs experience an induced dv/dt due to a complementary SCR turning on, given

D

• peak switching voltage, es = 200 V • operating frequency, fs = 1 kHz • dv/dt limit, S = 200 V/µs. Assume • stray circuit L = 10 µH • 22 per cent voltage overshoot across the SCR • an L-C-R snubber is appropriate.

D C

Solution Figure 8.5. Polarised variations of the basic thyristor R-C snubber: (a) Rs Vs; and (d) using a soft voltage clamp.

m

s fv

∨

t off = 5 L / R 5% of 1/10kHz = 5 × 0.6µH / R that is R = 0.6 Ω Use the preferred value 0.68Ω (nearest higher preferred value), which reduces the L/R time constant.

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289

The discharge resistor power rating is independent of resistance and is given by P0.68Ω = ½ LI m2 f s = ½ × 600nH × 100A 2 × 10kHz = 30W The resistor in the circuit in figure 8.19a must have low inductance to minimise voltage overshoot at switch turn-off. Parallel connection of metal oxide resistors may be necessary to fulfil both resistance and power rating requirements. The maximum switch over-voltage at turn-off, (assuming zero resistor inductance), at the commencement of core reset, which is added to the supply voltage, 600V, is V0.68Ω = I m R = 100A × 0.68Ω = 68V which decays exponential to zero volts in five time constants, 5µs. The maximum switch voltage is 600V + 68V = 668V, at turn-off. The reset resistor should be rated at 0.68Ω, 30W, metal film, 750V dc working voltage. ∨ A Zener diode, as in figure 8.19b, of Vz = L I m / t off = 0.6µH×100A/5µs = 12V , will reset the inductor in the same time as 5 L/R time constants. The switch voltage is clamped to 612V during the 5µs inductor reset time at switch turn-off. At turn-on when the switch voltage reduces to zero, the snubber inductor current (hence switch current) is less than the load current, 100A, specifically 1 i0 = ∫ vind dt L 100ns 1  t  = 600V ×   dt = 50A 600nH ∫0  100ns 

The switch turn-on loss is reduced from 30W to 100ns

Pon = f s

∫

100ns

ic vc dt = f s

0

100ns

= fs

∫ 0



t







t

∫ V 1- 100 ns  × i  100ns  s

0

2

dt

0

2

0

that is L = 300nH The necessary reset resistance to reduce the 300nH inductor current to zero in 5µs is ∨

t off = 5µs = 5 × 0.3µH / R that is R = 0.3Ω Use the preferred value 0.33Ω in order to reduce the time constant. The power dissipated in the 0.33Ω reset resistor, which is independent of resistance, is P0.33Ω = ½ LI m2 f s = ½ × 300nH × 100A 2 × 10kHz = 15W The resistance determines the voltage magnitude and the period over which the inductor energy is dissipated, not the amount of inductor energy to be dissipated. The inductor peak reset voltage is 100A×0.33Ω = 33V, which is added to the supply voltage of 600V, giving 633V across the switch at turnoff. That is, use a 0.33Ω, 15W metal film (for low inductance), 750V dc working voltage resistor. ∨ A Zener diode, as in figure 8.19b, of Vz = L I m / t off = 0.3µH×100A/5µs = 6V (use 6.8V), will reset the inductor in the same time as 5 L/R time constants. The switch voltage is clamped to 606.8V during the ∨ t off = 5µs inductor reset time at turn-off. The energy dissipated in the switch at turn-on is reduced from 30W to 100 ns

= fs

0

P(t)

ic=100(t/tfv)2

t

vind

t

vind 600V

600V

VDf

VDf=Vload

tfv

Example 8.5. part (b)

1.5tfv

t

 t   100 ns  dt   2

t    t  600V  1 × 100A  100 ns  dt = 5W  100ns   

The polarised turn-on snubber circuit - with saturable ferrite inductance

The purpose of a turn-on snubber circuit is to allow the switch collector voltage to fall to zero while the collector current is low. Device turn-on losses are thus reduced, particularly for inductive loads, where during switching the locus point (Vs, Im) occurs in the un-aided transition case. This turn-on loss reduction effect can be achieved with a saturable inductor in the circuit shown in figure 8.21a, rather than using a non-saturable (air core) inductor as previously considered in section 8.3.3. The saturable inductor in the snubber circuit is designed to saturate after the collector voltage has fallen to zero, at point Y in figure 8.21. Before saturation the saturable inductor presents high reactance and only a low magnetising current flows. Once the collector voltage has reached zero, the inductance can saturate since the switch-on loss period is finished. From Faraday’s equation, assuming the collector voltage fall to be linear, Vs (1 − t / t fv ) , the saturable inductor ℓs must satisfy dφ dB = NA (8.27) vA = N dt dt Rearranging, using an inductor voltage vA (t ) = Vs − vc (t ) = Vs t / t fv , and integrating gives

0

1 NA

tfv

Example 8.5. part (c)

t

t fv

1

t fv

∫ v (t ) dt = NA ∫ V A

0

s

0

t t fv

dt

(8.28)

which yields the identity Vs =

100A=Area/L 0

m

The total turn-on snubber losses (switch plus snubber resistor) are 5W+15W = 20W, which is less than the 30W for the unaided switch. The switch losses, with an inductive turn-on snubber, are decreased by 83⅓%, from 30W to 5W.

Bs = 100A=Area/L

2



t

s

vc=600(1-t/tfv) 100A

50A

∫



∫ V 1- 100ns  × I 0

100ns

8.3.4

P(t)

100 ns

ic vc dt = f s

0

100A

ic=50(t/tfv)2

∫

Pon = f s

♣

600V

vc=600(1-t/tfv)

290

iii. As the voltage across the switch falls linearly to zero from 600V, the series inductor voltage increases linearly to 600V (k = 1), such that the voltage sum of each component adds to 600V. The inductor current increases in a quadratic function according to 1 iind (t ) = ∫ vind dt L The inductor current increases quadratically to 100A in 100ns, as its voltage increases linearly from zero to 600V, that is 100 ns 1 dt 100A = 600V t 100ns L ∫

t    t  600V  1 × 50A  100ns  dt = 2.5W  100 ns   

The total turn-on losses (switch plus snubber resistor) are 2.5W + 30W = 32.5W, which is more than the 30W for the unaided switch. Since the current rise time tri has been neglected in calculating the 30W un-aided turn-on losses, it would be expected that 32.5W would be less than the practical un-aided case. The switch loss is decreased by 92⅔%, from 30W down to 2.5W.

600V


Chapter 8

2 NA Bs t fv

(V)

where N is the number of turns, A is the core area, and Bs is the core ferro-magnetic material saturation flux density.

(8.29)

Power Electronics

291


Chapter 8

The inductor magnetising current IM should be much less than the load current magnitude Im, IM Cs D

Co Dc

+

Im

Ls

Cs

+

+

Cs Ds

Ls

Dc

Ds

0

(a)

(b)

(c)

(d)

Figure 9.3. Inductive turn-on snubber with snubber energy recovery intermediate capacitors: (a) circuit diagram; and successive (b) turn-off; (c) turn-on; and (d) turn-off.

9.1.2

Active recovery

i. Recovery into the dc supply Figure 9.4 shows an inductive turn-on snubber energy recovery scheme which utilises a switched-mode power supply (smps) based on the boost converter in 15.4, and shown in figure 9.26a. At switch turn-off the energy stored in the snubber inductor Ls is transferred to the large intermediate storage capacitor Co via the blocking diode, Db. The inductor current falls linearly to zero in time Ls Im / VCo. The smps is then used to boost the relatively low capacitor voltage into a higher voltage suitable for feeding energy back into a dc supply. The capacitor charging rate is dependent on load current magnitude. The smps can be controlled so as to maintain the capacitor voltage constant, thereby fixing the maximum switch collector off-state voltage, or varied with current so as to maintain a constant snubber inductor reset time. One smps and storage capacitor can be utilised by a number of switching circuits, each with a blocking/directing diode as indicated in figure 9.4. The diode and switch are rated at Vs+VCo. The smps is operated in a discontinuous inductor current mode in order to reduce switch and diode losses and stresses. If the load and inductive turn-on snubber are re-arranged to be in the cathode circuit, then the complementary smps in figure 9.26b can be used to recover the snubber energy from capacitor Co.

(9.7)

Co

Lsmps

VCo

on Tsmps

(9.8)

off

Db see figure 9.26a

fsmps

The final stage of recovery is shown in figure 9.3d where the capacitor Co dumps its charge at a constant rate into the load as its voltage falls linearly to zero in a time, independent of the load current

VCo = Ls C o Im

Dsmps

(9.9)

fsmps > fT

during which time the capacitor Co voltage falls according to

VCo (ωt ) = VCot =0 −

L Im I t = Im s − m t Co Co Co

The load freewheel diode Df then conducts the full load current Im.

(9.10)

+

Cs

Lr

During the transfer of energy from Cs to Co the circuit voltage and current waveforms are given by equations (9.11) to (9.14). The voltage on Co given by (9.8) is retained until subsequent switch turn-off.

t Co = C o

Co

Lr T

Dr

Dr

When switch T subsequently turns on, the energy stored in Cs is resonantly transferred to the intermediate storage capacitor Co, through the path Cs - Lr - D - Co- T shown in figure 9.3c. All the energy in Cs is transferred provided Co > Cs, in which case the diode Dc across Cs conducts, clamping Cs to zero volts. The final voltage on Co is

VCo = VCs

306

0V

0V

Figure 9.4. Turn-on snubber with active snubber inductor energy recovery.

Power Electronics

307

Chapter 9

9.2.1

Df

OFF

ON

+

+

Switching Aid Circuits with Energy Recovery

308

Passive recovery

i. Recovery into the load Figure 9.6 illustrates a passive, lossless, capacitive turn-off snubber energy recovery scheme which dumps the snubber energy, ½CVs2 f s , into the load. The switch turn-off protection is that with a conventional capacitive snubber circuit. At turn-off the snubber capacitor Cs charges to the voltage rail Vs as shown in figure 9.7a. At subsequent switch turn-on, the load current diverts from the freewheeling diode Df to the switch T. Simultaneously the snubber capacitor Cs resonates its charge to capacitor Co through the path shown in figure 9.7b, T - Cs - L - Do - Co. When the switch next turns off, the snubber capacitor Cs charges and the capacitor Co discharges into the load. When Co is discharged, the freewheeling diode conducts. During turn-off Co and Cs act effectively in parallel across the switching device. A convenient starting point for the analysis of the recovery scheme is at switch turn-on when snubber energy is transferred from Cs to Co.

Figure 9.5. Conventional capacitive turn-off snubber showing currents at IGBT transistor: (a) turn-off and (b) turn-on.

9.2

Energy recovery for capacitive turn-off snubber circuits – single ended

Figure 9.5 shows the conventional capacitive turn-off snubber circuit used with both the GTO thyristor and the IGBT transistor. At turn-off, collector current is diverted into the snubber capacitor C via D. The switch turns off clamped to the capacitor voltage which increases quadratically from zero. At the subsequent switch turn-on the energy stored in C, ½CVs2 is dissipated as heat, mainly in the resistor R. A full functional description and design procedure for the capacitive turn-off snubber circuit is to be found in chapter 8.3.1. At high voltages and switching frequencies, with slow switching devices, snubber losses ( ½CVs2 f s ) may be too high to be readily dissipated. An alternative is to recover this energy (either into the load or back into the dc supply), using either passive or active recovery techniques.

T

T

+

+

Figure 9.7. Energy recovery turn-off snubber showing the energy recovery stages: (a) conventional snubber action at turn-off; (b) intermediate energy transfer at subsequent switch turn-on; and (c) transferred energy dumped into the load at subsequent switch turn-off.

+ +

Do

Co

T

Rs

L

+

Ds

Cs

At switch turn-on The active equivalent circuit portions of figure 9.7b are shown in figure 9.8a. Analysis of the L-C resonant circuit with the initial conditions shown yields the following capacitor voltage and current equations. The resonant current is given by V i (ωt ) = s sin ωt (A) (9.11) Z As 1 n + 1 where Z = ω A s = = Zo (ohms) Zo = (ohms)

ωC o

ω = ωo

+

n = (a)

(b)

Figure 9.6. A capacitive turn-off snubber with passive capacitor energy recovery into the load: (a) with a capacitive turn-off snubber and (b) with an RC turn-off snubber.

n + 1 n

n

Co

(rad/s)

ωo =

1 AsC o

(rad/s)

Cs Co

The snubber capacitor voltage decreases from Vs according to 1  VCs = Vs 1 − (V) (1 − cos ωt )  1+ n  while the transfer capacitor voltage charges from zero according to n VCo = Vs (V) (1 − cos ωt ) 1+ n

(9.12)

(9.13)

Power Electronics

309

Chapter 9


310

At switch turn-off Energy dumping from Co into the load and snubber action occur in parallel and commence when the switch is turned off. As the collector current falls to zero in time tfi a number of serial phases occur. These phases, depicted by capacitor voltage and current waveforms, are shown in figure 9.10. Phase one Capacitor Co is charged to n Vs , so until the snubber capacitor Cs charges to 1 − n Vs , Co is inactive. Conventional snubber turn-off action occurs as discussed in chapter 8.3.1. The snubber capacitor voltage increases according to I (V) (9.15) VCs = ½ m t 2 Cs t fi

(

Figure 9.8. Equivalent circuit for the intermediate energy transfer phase of snubber energy recovery, occurring via: (a) the main switch T and (b) then via the snubber diode Ds.

)

while Co remains charged with a constant voltage of n Vs . This first phase is complete at to when I t2 VCs = vo = ½ m o = 1 − n Vs (V) (9.16) Cs t fi

(

)

whence

to =

and the collector current

(

2 1 − n Vs Cs t fi

(

I o = I m 1 − to t

equation (9.11)

)

(s)

Im

fi

)

(A)

(9.17)

(9.18)

equation (9.14)

equation (9.12)

equation (9.13)

Figure 9.9. Circuit waveforms during intermediate energy transfer phase of snubber energy recovery: (a) transfer capacitor C0 current; (b) snubber capacitor voltage; and (c) transfer capacitor voltage.

Examination of equation (9.12) shows that if n > 1, the final snubber capacitor Cs voltage at ωt = π will be positive. It is required that Cs retains no charge, ready for subsequent switch turn-off; thus n ≤ 1, that is Co ≥ Cs. If Co is greater than Cs equation (9.12) predicts Cs will retain a negative voltage. Within the practical circuit of figure 9.6, Cs will be clamped to zero volts by diode Ds conducting and allowing the remaining stored energy in L to be transferred to Co. The new equivalent circuit for ωt = cos −1 ( − n ) is shown in figure 9.8b. The resonant current, hence transfer capacitor voltage are given by V i (ωt ) = s sin (ωo t + φ ) (A) Z (9.14) VCo = n Vs cos (ωo t + φ ) (V)

Figure 9.10. Circuit waveforms at switch turn-off with turn-off snubber energy recovery when: (a) the snubber Cs is fully charged before the switch current at turn-off reaches zero and (b) the switch collector current has fallen to zero before the snubber capacitor has charged to Vs.

2

where t ≥ 0 and φ = − tan −1 1−nn . In maintaining energy balance, from equation (9.14) when the inductor L current i(ωt) = 0, the final voltage on Co is n Vs and Cs retains no charge, VCs = 0. The voltage and current waveforms for the resonant energy transfer stage are shown in figure 9.9.

Phase two When Cs charges to 1 − n Vs , the capacitor Co begins to discharge into the load. The equivalent circuit is shown in figure 9.11a, where the load current is assumed constant while the collector current fall is assumed linear. The following Kirchhoff conditions must be satisfied

(

)

Power Electronics

311

Chapter 9

Switching Aid Circuits with Energy Recovery Vs

Vs = VCs + VCo (V) I m = iCo + iCs + I o (1 − t / t fi ) (A)

(9.19) (9.20) Df

for 0 ≤ t ≤ tfi – to Under these conditions, the snubber capacitor voltage increases according to n 1  ( I m − I o ) t + ½t 2 / to  + 1 − n Vs VCs = (V) 1 + n Cs  with a current 1 (A) iCs = {I m − I o (1 − t / to )} 1+ n

(

Im

)

Vs

L O A D

Lr

Im

L O A D

Df/b

1:N on on Lp

(9.22)

Ls

N>2

Ds

(9.23)

T

Cs

Phase three If the snubber capacitor has not charged to the supply rail voltage before the switch collector current has reached zero, phase three will occur as shown in figure 9.10b. The equivalent circuit to be analysed is shown in figure 9.11b. The Kirchhoff equations describing this phase are similar to equations (9.19) and (9.20) except that in equation (9.20) the component Io(1- t/t0) is zero. The capacitor Cs, charging current is given by n (9.24) (A) iCs = Im 1+ n while the dumping capacitor Co current is iCo = iCs / n (A) (9.25) The snubber capacitor charges linearly, according to n Im (9.26) (V) VCs = vio + t 1 + n Cs When Cs is charged to the rail voltage Vs, Co is discharged and the load freewheeling diode conducts the full load current Im. Since the snubber capacitor energy is recovered there is no energy loss penalty for using a large snubber capacitance and the larger the capacitance, the lower the switch turn-off switching loss. The energy to be recovered into the load is fixed, ½CsVs2 and at low load current levels the long discharge time of Co may inhibit proper snubber circuit action. This is generally not critical since switching losses are small at low load current levels. Output voltage regulation is reduced, since the amount of energy recovered into the load is independent of the load current. ii. Recovery into the dc supply Figure 9.12 show two turn-off snubber circuits where the energy is recovered back into the dc supply. The ac circuit operational mechanisms are the same for both circuits. When the switch T is turned off the snubber capacitor Cs charges to the dc rail voltage Vs.

Ds

on Lp

Ls

Lr

(b)

Figure 9.12. A capacitive turn-off snubber with passive energy recovery into the supply: (a) basic capacitive turn-off snubber and (b) an alternative configuration.

+

Figure 9.11. Turn-off snubber equivalent circuit during energy recovery into the load when: (a) Co begins to conduct and (b) after the switch has turned off.

1:N

Cs T

on

0 (a)

+

+

Do

+

Do

0

+

Df

Df/b

(9.21)

The transfer dump capacitor Co discharges with a current given by iCo = iCs / n

+

312

At switch T turn-on, the snubber capacitor Cs resonates with inductor Lr through the coupled transformer primary Lp, in the loop Cs - Do – Lp - Lr - T, returning energy to the dc supply through the coupled secondary circuit. The primary voltage is Vs /N, and provided this referred voltage is less than a half Vs, all the energy on Cs is transferred to the dc supply via the transformer. The snubber diode Ds clamps the capacitor Cs voltage to zero, and excess energy in Lr is transferred to the dc supply, in the loop Do – Lp Lr – Ds, as the inductor Lr current falls linearly to zero when opposed by the referred dc link voltage via the transformer. In figure 9.12a, the winding secondary can be connected to the other terminal of Cs. Once the energy transfer is complete, the transformer core magnetising current resets to zero in the same Kirchhoff loop, but at a low voltage. Reset must be complete in one complete period of switch T. iii RC snubber recovery The IGCThyristor is commonly used and characterised with an RC snubber. The figure 9.6b shows how the snubber diode Ds in figure 9.6a can be replaced by a resistor to form an RC snubber, provided diode Ds is used to clamp the minimum snubber capacitor voltage to zero. The resistor losses are ½CsV2. The snubber capacitor stored energy after turn-off, ½CsV2, can be recovered at switch turn-on, provided the RsCs time constant is at least comparable with the LC resonant period – an unlikely condition. 9.2.2

Active recovery

i. Recovery into the dc supply Active energy recovery methods for the turn-off snubber are simpler than the technique needed for active recovery of turn-on snubber circuit stored energy. This is because the energy to be recovered from the turn-off snubber is fixed at ½CsVs2 and is independent of load current. In the case of the turn-on snubber, the energy to be recovered is load current magnitude dependent ( α IL2 ) which complicates active recovery. Active turn-off snubber energy recovery usually involves the production of an intermediate capacitive energy storage stage involving a positive or negative voltage rail (with respect to the emitter of the principal switch). a Negative intermediate voltage rail At switch T turn-on the snubber capacitor stored energy is resonated into a large intermediate storage capacitor Co as shown in figure 9.13a. Recovery from Cs to Co at switch T turn-on occurs through the following loops: at switch T turn-on when VCs > 0: Cs -T- Co - L- Da (as shown in figure 9.8a and equations (9.12) - (9.13)) then when VCs = 0: Ds - Co - L- Da (as shown in figure 9.8b and equation (9.14)) The switch current is increased by the resonant current, which has a maximum of VCo / L / C s . It is possible to use the energy in Co as a negative low-voltage rail supply. This passive recovery technique suffers from the problem that the recovered energy ½CsVs2 may represent more energy than the lowvoltage supply requires. An independent buck-boost smps can convert excess energy stored in Co to a more useful voltage level. Producing the gate drive for the smps switch Tsmps presents few difficulties since the gate-emitter has a low dc offset and does not experience any dv/dt relative to the emitter reference voltage of the main switch T.

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Chapter 9

The basic recovery circuit, with the buck-boost smps, can form the basis of an active turn-off snubber energy recovery circuit when switches are series connected, as considered in section 9.4. It may be noticed that the ‘Cuk’ converter in chapter 17.6 is in fact the snubber energy recovery circuit in figure 9.13a, controlled in a different mode.


314

Whether a positive or negative intermediate voltage is produced on Co, (typically a few tens of volts, but much higher if part of a turn-on snubber recovery circuit), the energy on Co is usually smps converted to stable gate voltage levels of the order of ±15V. Since a dual rail polarity gate level supply is needed, the polarity of the voltage on Co (viz., positive or negative) is inconsequential.

Dc

Da Cs

T

Rs

Dsmps

Tsmps

Lsmps on

on

(a) Vs SMPS L O A D

Passive recovery

Vs

Im

Dsmps

off

+

9.3.1

i. Recovery into the load The snubber capacitor energy is recovered by the transfer process outlined in section 9.2.1. Figure 9.14a shows the energy transfer (recovery) paths at switch turn-off. The capacitor Co and inductor ℓs transfer their stored energy to the load in parallel, such that the inductor voltage is clamped to the capacitor voltage VCo. As Co discharges, the voltage across ℓs decreases to zero, at which time the load freewheel diode Df conducts. Any remaining inductor energy is dissipated as unwanted heat in circuit resistance. Proper selection of ℓs and Cs ( ½ Ls I m2 ≤ ½CsVs2 ) can minimise the energy that is lost although all the snubber capacitor energy is recovered, neglecting diode and stray resistance losses. The energy (controlled by and transferred to the turn-on snubber inductor ℓs) associated with freewheel diode reverse recovery current, is also recovered.

off

Df

Unified turn-on and turn-off snubber circuit energy recovery – single ended

Conventional inductive turn-on and capacitive turn-off snubber circuits can both be incorporated around a switching device as shown in figure 8.20 where the stored energy is dissipated as heat in the reset resistor. Figure 9.14 shows unified turn-on and turn-off snubber circuits which allow energy recovery from both the snubber capacitor Cs and inductor ℓs.

SMPS

L

9.3

Cs

Da

T Ds

Lsmps

Trev

off

+

on

L

Co

L

Ds

T

on

b Positive intermediate voltage rail A positive voltage source, with respect to the main switch emitter, can be produced with the recovery circuit in figure 9.13b. Practically, an extra switch, Trev, is needed in order to minimise the time of current decay in the loop L - Ds, after the switch T is turned on and the voltage on the snubber capacitor Cs has resonated to zero. A passive resistor-capacitor network can be used to synchronise the turn-on (due to the main switch T turning on) and turn-off (due to diode Ds becoming forward biased) of the low-voltage switching device Trev. Recovery from Cs to Co at switch T turn-on occurs through the following Kirchhoff current loops: at switch T turn-on when Trev is on and VCs > 0: Cs -T - L- Trev for a period ½π√LCs then when Trev is off and VCs = 0: Co - L- Da for a period Vs /ωoVCo A boost smps controls and transfers the energy on Co to the dc rail through diode Dsmsp. The basic recovery circuit, with the boost smps, when cascade connected, can form the basis of an active turn-off snubber energy recovery circuit for series connected switches, as considered in 9.4. ii. RC snubber recovery The IGCThyristor is commonly used and characterised with an R-C snubber (as opposed to a parallel connected series capacitor-diode turn-off snubber). The insert in figure 9.13a, for use in figures 9.13a and b, shows how the snubber diode Ds can be replaced by a resistor to form an R-C snubber, provided diode Dc is used to clamp the minimum snubber capacitor voltage to zero. The resistor losses are ½CsV2. Most of the snubber capacitor stored energy after turn-off, ½CsV2 at switch turn-off, (depending on the Rs-Cs time constant), can be recovered using either of the basic circuits in figure 9.13, or the circuits in figures 9.6 and 9.14, provided the RsCs time constant is greater than the LC resonant period.

Dc Co

Vs + Lo

Rs Cs

(b) Figure 9.13. Switching circuit for recovering turn-off snubber capacitor energy, and for providing either (a) a negative voltage rail and/or transferring to Vs, via a buck-boost smps or (b) a positive voltage rail and/or transferring to Vs, via a boost smps.

Df

Do Da

Tsmps 0V

Df

Co

+

DR

Df/b

1:N

on

D1

Do Do

+

(c)

(a)

on

(b)

Figure 9.14. Switching circuits incorporating unified turn-on and turn-off snubber, showing recovery path of energy (a) in Co and ℓs; (b) in Cs and ℓs through Dr.; and (c) recovery circuit when an RC snubber is employed.

At switch turn-on When the switch is off, the freewheel diode Df conducts the load current Im, capacitor voltage VCs = Vs and VCo = 0. Phase one: t P 1 When the switch is turned on, the series inductor ℓs performs the usual turn-on snubber function of controlling the switch di/dt according to (assuming the switch voltage fall time is relatively short) on

i (t ) =

Vs

As

t

(9.27)

The switch current rises linearly to the load current level Im and then continues to a level IRR higher as the freewheel diode Df recovers with currents in the paths shown in figure 9.15a. This diode reverse recovery current IRR is included in the analysis since the associated energy transferred to the turn-on inductor is subsequently recovered.

Power Electronics

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Chapter 9

on The peak switch current Im + IRR is reached after the duration t P 1 As on t P 1 = ( I m + I RR )

and

As long as the freewheel-diode conducts, the load is clamped to near zero volts, thus Cs remains charged to Vs.

Df

Vs

Vs

L

L

Im O

Im O

A D

Im

A D

Co

L O A D

ℓs

T

+

T

0V

ℓs

Do

0V

Do

Ds

T

Cs

(b)

VCo (t Pon3 ) = nV s2 + ( Z o I RR )

0V

(c)

Phase two: t P 2 The turn-off snubber capacitor Cs charge resonates in the path Cs - Do - Co - ℓs and through the switch T, as shown in figure 9.15b. The capacitor voltages and resonant current are given by (n = Cs / Co) on

Vs sin ωt + I RR cos ωt Z ω Z 1  VCs (ωt ) = V s  1 − (1 − cos ωt )  + o I RR sin ωt 1+n   ω n ω n VCo (ωt ) = V s (1 − cos ωt ) + o Z I RR sin ωt 1+n ω i Cs (ωt ) = i Co (ωt ) =

ω = ωo

1

ωC o

= Zo

n + 1 n

(ohms)

n + 1 n

(rad/s)

The freewheel diode Df voltage is V Df (ωt ) = V s + VCo −VCs = V s (1 − cos ωt ) + I RR Z sin ωt

Zo = ωo =

(9.29)

(9.31) As 1 AsC o

(ohms)

n =

i Co (t Pon2 ) =

Vs (1 − n 2 ) Z

Vs

L

L

Df Im O

Df Im O

A D

Vs

Vs

L

L Df Im O

DR

A D

DR

A D

Co

0V

+ Cs

Ds

T

(a)

+ Cs

(b)

DR Co

+

Do

Ds

T

T 0V

0V

0V

A D

+ ℓs

ℓs

Ds

T

(9.32)

Df Im O

Co

+

(rad/s)

(9.34)

(9.39)

Vs

ℓs

ω

2

At switch turn-off When the switch is on, it conducts the load current Im and the snubber capacitor Cs voltage is zero, on while the transfer capacitor voltage VCo( t P 3 ) = √n Vs = Vo (neglecting the IRR component) is a result of the previous switch turn-on. When the switch T is turned off, the collector current decreases linearly from Im towards zero in time tfi.

Cs Co

When the freewheel-diode current reaches its peak recovery level, IRR, it is able to support a voltage which from equation (9.32) sinusoidally increases from zero. Specifically the freewheel-diode reverse bias VDf is controlled such that zero voltage turn-off occurs resulting in low recovery power losses. Stray or inductance deliberately introduced in series with Do (to decrease the resonant peak current given by equation (9.29) as approximately Vs / Z) produces a freewheel-diode recovery step voltage Vs ℓs /( ℓs + Lstray), but the step is always less than Vs. The resonant period prematurely ends (since n < 1) when the snubber capacitor Cs voltage reduces to zero and is clamped to zero by conduction of the snubber diode Ds, as shown in figure 9.15c. Assuming on IRR = 0 (to obtain a tractable solution), equating equation (9.30) to zero yields the time for period 2, t P 2 , that is cos −1 ( −n ) (9.33) t Pon2 = at which time

(9.38)

The turn-on equations (9.29) to (9.37) are essentially the same as equations (9.11) to (9.14) for the turn-off snubber energy recovery circuit considered in section 9.2.1, except free-wheel diode reverse recovery has now been included. The circuit turn-on voltage and current waveforms shown in figure 9.9 are also applicable.

(9.30)

Co

(9.37)

If the diode reverse recovery energy is reintroduced, based on energy transfer balance, the final voltage on Co is

Figure 9.15. Unified turn-on and turn-off snubber at switch turn-on, showing (a) current build-up in ℓs; (b) energy resonant transfer from Cs to Co; and (c) energy transfer from ℓs to Co through Ds.

where Z = ω A s =

Vs cos (ωo t + φ ) Zo

ωo

0V

(a)

(9.36)

The resonant current reaches zero and energy transfer to Co is complete, after a period ½π − φ t Pon3 =

IRR ℓs

VCo (ωo t ) = n V s sin (ωo t + φ ) i (ωo t ) = n

Co

+

(9.35)

on Phase three: t P 3 The remaining energy stored in ℓs is resonantly transferred into Co in the path Do - Co - ℓs - Ds, with initial conditions given by equations (9.34) and (9.35), according to

and

+

316

VCo (t Pon2 ) = nV s

(9.28)

Vs

Vs


(c)

(d)

Figure 9.16. Unified turn-on and turn-off snubber at switch turn-off, showing (a) current diversion to snubber capacitor Cs; (b) transfer capacitor Co releasing energy (c) energy transfer to the load simultaneously from ℓs and Co through DR; and (d) energy transfer from Co into the load through DR.

Phase 1: t P 1 The load current is progressively diverted to the snubber capacitor as the collector current decreases, giving a capacitor (and collector) voltage of I t2 t 1 t 1 t v ce = VCs (t ) = (9.40) 0 ≤ t ≤ t fi ( I − i ) dt = ∫ I m dt = m C s ∫0 m c C s 0 t fi C s 2t fi If the collector current reaches zero before any other associated recovery processes occurs, then after the collector current has reached zero, the collector and snubber voltages rise linearly (being clamped in parallel), with currents in the paths shown in figure 9,16a, according to off

Power Electronics

317

v ce = VCs (t ) = ½

I m t fi I m t + Cs Cs

provided ½

I m t fi ≤ V s −V o Cs

Chapter 9

(9.41)

The collector voltage reaches Vs at a time given from equation (9.41) when VCs = Vs – VCo as

t Poff1 =

Cs (V −Vo ) + ½t fi Im s

(9.42)

where Vo is given by equation (9.39) and the period duration includes the collector linear fall period tfi. Phase 2: t P 2 When the collector (and snubber) voltage VCs reaches Vs -Vo capacitor Co begins to discharge into the load providing the load current Im. Simultaneously Cs charges to Vs through ℓs, as shown in figure 9.16b. The relevant circuit capacitor voltages and current are n  1  (9.43) i As (ωt ) = I m 1 + cos ωt  1 + n  n 


318

iii. Recovery into the load and supply Figure 9.14b shows a dual snubber energy recovery technique where a portion of the resonance energy is transferred back to the dc supply (as opposed to the load) at switch turn-on, through a magnetically coupled circuit where it is required of the turns ratio that N > 2. This reduces the energy transferred from the snubbers to the load, giving better load regulation under light load conditions. Load regulation with light loads is poor since the snubber capacitor energy is fixed, ½C sV s2 , independent of the load, Im. In the analysis to follow, the recovery contribution of the freewheel diode reverse recovery energy is neglected.

off

 (9.44) sin ωt + ωo t  + V s −Vo   1  1 VCo (ωt ) = I m Z o (9.45) sin ωt − ωo t  + Vo  n +1 n +1  This phase is complete when the snubber capacitor Cs is charged to the supply voltage, Vs, assuming the inductor current is greater than zero at that time. Let the inductor current be I2 at the end of the offoff period t P 2 and the capacitor Co voltage be V2.

VCs (ωt ) = I m Z o

1

 

1

n +1 n +1

Phase 3: t P 3 The snubber capacitor is clamped to the rail voltage. The transfer capacitor Co and snubber inductor ℓs both release energy in parallel into the load through the paths shown in figure 9.16c. The inductor voltage is clamped to the capacitor Co voltage. The snubber inductor current is off

V i As (ωo t ) = I m + 2 sin ωo t + ( I 2 − I m ) cos ωo t Zo

while the transfer capacitor voltage is VCo (ωo t ) = V 2 cos ωo t + Z o ( I 2 − I m ) sin ωo t

(9.46) (9.47)

One of two conditions form the completion of this phase • •

the transfer capacitor voltage reaches zero before the snubber inductor current reaches zero the snubber inductor current reaches zero before the transfer capacitor voltage reaches zero

The first condition represents the case where the remaining inductor current associated energy is lost as it freewheels to zero in the low voltage path ℓs - Do - DR and the load. In the second case, the inductor current given by equation (9.46) reaches zero, while the transfer capacitor Co continues to discharge into the load as shown in figure 9.16d. The inductor current is prevented from reversing by diode Ds. Once the inductor current has fallen to zero, the transfer capacitor voltage falls linearly to zero as it provides the load current Im. This second case represents the situation when 100% of all snubber (inductor ℓs and capacitor Cs) and diode reverse recovery energy is recovered, that is ½A s ( I m + I RR ) ≤ ½C sV s2 2

(9.48)

Snubber reset and recovery is complete when the snubber inductor current and transfer capacitor voltage are both zero, the collector voltage has ramped to Vs, and the free-diode conducts the full load current Im. From equation (9.47), this stage is complete when VCo( t Poff3 ) = 0, that is

t Poff3 =

1

ωo

  V2 tan−1   Z ( I − I )  m   o 2

(9.49)

Now the switch can be turned on. ii. RC-L dual snubber recovery The IGCThyristor is commonly used and characterised with an RC snubber and an inductive turn-on snubber. Figure 9.14c shows how the snubber diode Ds in figure 9.14a can be replaced by a resistor to form an RC snubber, provided diode combination Da - Ds is used to clamp the minimum snubber capacitor voltage to zero. The resistor losses are ½CsV2. The snubber capacitor stored energy after turn-off, ½CsV2, can be recovered at switch turn-on, while the inductive turn-on energy ½LsI2 is recovered at switch turn-off, provided the RsCs time constant is greater than the LC resonant period.

At switch turn-on The turn-on phase is essentially the same as the circuit considered in figure 9.14a, except the transformer is seen as an opposing emf voltage source Vs /N. Phase one: t P 1 The switch current fall period is described by equation (9.27) and the time of the first turn-on period is given by equation (9.28). on

Phase two: t P 2 The equations (9.29) to (9.35) are modified to account for the transformer referred voltage Vs /N N − 1 Vs × sin ωt i As (ωt ) = i Cs (ωt ) = i Co (ωt ) = (9.50) on

N

VCs (ωt ) = V s × VCo (ωt ) = V s

Z

1 × 1 + Nn + (N − 1) cos ωt  N (1 + n ) 

(9.51)

n (N − 1) (1 − cos ωt ) N ( n + 1)

(9.52)

The instantaneous power being returned to the supply through the transformer is given by

p (ωt ) =

Vs V N − 1 Vs N − 1 Vs × i (ωt ) = s × × sin ωt = × sin ωt N As N N Z N2 Z 2

(9.53)

The time for this period is given by equation (9.51), when the snubber capacitor voltage is zero 1  nN + 1  t Pon2 = × cos −1  − (9.54)  ω  N −1  The energy returned to the supply is 1 n + 1 V s2 × = × C sV s2 < ½C sV s2 since N > 2 (9.55) w Trans t Pon2 = ( J)

( )

N

ωZ

N

on Phase three: t P 3 Energy continues to be recovered back into the supply Vs through the transformer when the resonant current transfers to the diode Ds. Capacitor Cs charges to Vs and is clamped to Vs by diode Dc. The final voltage on the transfer capacitor Co is

VCo (t Pon3 ) =

Vs  1 + nN 2 − 1  N 

(9.56)

The total energy transferred to the supply through the transformer is the difference between the initial energy in ℓs and Cs and the final energy in Co.

w Trans (t Pon2 + t Pon3 ) = ½C sV s2 + ½A s I m2 − ½C o

V s2

2

 1 + nN 2 − 1 (9.57)  If the turn-on inductor current reaches zero before the third phase can commence (due to N being too small), then the turn-off snubber does not fully discharge, and will act as a soft clamp in the subsequent switch turn-off cycle. The capacitors retain the following voltages 2 + Nn − N 2 =Vs − VCs = V s V (9.58) N ( n − 1) N ( n − 1) s

VCo = V s

2n (N − 1)

N ( n + 1)

N2 

(9.59)

At switch turn-off The circuit recovery operation at turn-off is essentially the same as when no transformer is used (N→∞), except that the voltage on Co at the begin of turn-off is given by equation (9.59) or equation (9.56), as appropriate.

Power Electronics

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Chapter 9


Operating regions of the dual energy recovery circuits

9.3.2 Active recovery

Both the passive unified recovery circuits analysed can be assessed simultaneously for their operational bounds, since the bounds for the transformerless version in figure 9.14a are obtained by setting N to infinitely in the appropriate equations for the recovery circuit in figure 9.14b. Figure 9.17 shows various operational boundaries for the two unified passive energy recovery circuits analysed. The various boundaries are determined from the operating equations for the circuits. The boundaries in figure 9.17a show the regions of full snubbering and for soft snubbering where the capacitor Cs is not reset to zero voltage during the resonant cycles at turn-on. The boundaries are summarised as follows N −2 n< (9.60)

i. Recovery into the dc supply

N N

n< (9.61) N −2 The boundaries in parts b and d of figure 9.17 satisfy equation (9.57), namely the capacitor energy is less than the inductor energy. The current is normalised with respect to √nVs / Zo. Part d shows that the ∨ relative range for 100% recovery, defined as (I − I ) / I , is independent of the transformer turns ratio.

Both turn-on and turn-off snubber energy can be recovered into the dc supply using a dedicated buckboost smps formed by Tsmps, Dsmps and Lsmps, shown in figure 9.18. Both snubbers (capacitor Cs and inductor Ls) transfer their energy to the intermediated storage capacitor, Co, from which the energy is smps transferred to the dc supply Vs. The buck-boost smps also maintains a fixed voltage on Co, which facilitates rapid energy transfer of the turn-on snubber inductor Ls energy to Co at switch T turn-off, in time LsIm / VCo. The maximum switch off-state voltage is Vs+VCo. At switch T turn-on, the turn-off snubber capacitor Cs energy is resonated to Co through the loop Cs - T - Co - ℓ - Do, as considered in detail in section 9.3.1. The smps is operated in a discontinuous inductor current mode in order to minimise smps switch and diode losses and stresses. The maximum smps switch and diode voltages are Vs+VCo. Figures 9.18b and c show circuit versions with a reduced component count. With the inductor ℓ removed, the resonant reset current magnitude and period is now only controlled by the turn-on snubber inductor. A further diode can be removed as shown in figure 9.18c, but the number of series components in the turn-on inductor reset path is increase as is the loop inductance associated with the path. Vs

Figure 9.17c shows the normalised (with respect to 2π√n/ωo) reset time at turn-off. The reset time at turn-on is the sum of periods one and two, but is dominated by the second turn-on period, namely ∨ 1 t on = cos −1 ( −n ) (9.62)

Df

normalised current

full snubbering

4

soft snubbering

2

N infinite

100% energy recovery

(a) 0

2

Co / Cs

0

N=4

0.4

N=2

2

N=100

max min

1 min

0 0

2

4

capacitance ratio

6

8

Co / Cs

10

1/n

Ls

Do Co

Lsmps Ls

Dsmps

+ Df

+

Ds Do Co

Tsmps

Lsmps +

0

0

(a)

2

4

capacitance ratio

(d)

max

3

Lsmps

Ds Tsmps

+

I

0

4

Co

Ls

∨

+ Df

on

N=10 0.6

Cs T

(b)

(c)

Figure 9.18. Unified, active turn-on and turn-off snubber energy recovery circuits: (a) basic circuit and (b) and (c) reduced component variations.

0

(b)

(c)

off

0.8

4

1/n

Tsmps

Dsmps

Cs T

ℓ Ds

Im

Im

Dsmps

Do

+ Df

< 100% recovery

0

normalised reset time

Fig 9.14a

0.2

N=2

normalised recovery range

transformer turns ratio N:1

8 6

I

1

T

Df

Df

Im

Cs n>1 n>1

Vs

Vs

ω

10

320

0.8

6

8

Co / Cs

10

1/n

9.4

Inverter bridge legs

Capacitive turn-off snubbers (without any turn-on snubber circuit inductance), both active and passive are not normally viable on bridge legs because of unwanted capacitor discharging and subsequent uncontrolled charging current, as considered in chapter 8.4. At best capacitive soft turn-off voltage clamps (operational at >Vs) can be employed to reduce turn-off losses, as shown in figure 8.24.

Independent of N

0.6

9.4.1 Turn-on snubbers

0.4

∨

I − I

all N

I

0.2 0 0

2

4

capacitance ratio

6

8

Co / Cs

10

1/n

Figure 9.17. Unified, passive snubbering characteristics: (a) operating regions with recovery transformer; (b) 100% recovery regions with different transformer turns ratios; (c) normalised circuit reset limits; and (d) normalised recovery range independent of transformer turns ratio.

i. Active recovery - recovery into the dc supply Figure 9.19 shows inverter bridge legs where both switches benefit from inductor turn-on snubbers and active energy recovery circuits. The circuits also recover the energy associated with freewheel diode reverse recovery current. The turn-on energy and diode recovery energies are both recovered back into the dc supply, Vs, via a buck-boost smps. At switch turn-off, the energy stored in Ls is transferred to capacitor Co via diode Ds. For given turn-on snubber inductance Ls, both circuits give the same di/dt in the switches. The capacitor voltages determine the snubber reset time. When both circuits result in the same switch maximum voltages, the reset times are the same. But the capacitor voltages in figure 18.9a are half those for the circuit in figure 9.19b. The main operational difference between the two configurations is the periods when the capacitors are charged. In figure 9.19a, both capacitors are charged at both switch turn-on and turn-off. In figure 9.19b, each capacitor charges once per cycle, one capacitor is charged at turn-on, the other at turn-off. Coupling of the turn-on inductors results in virtual identical waveforms as to when the inductors are not coupled. No net energy savings or gains result. Close coupling is therefore not necessary.

Power Electronics

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Chapter 9

Vs Ls

Co

T

Tsmps

Df

T

Lsmps

+

Dsmps

o/p

Co

Df

+

Ls

Ds

Ls

Ds

Tsmps

Lsmps

Dsmps

1. 2.

o/p Df

Tsmps

Dsmps

T

Tsmps

Dsmps

3. Ds

Ls

T

Lsmps

Co

Df

Co

+

4.

Lsmps

+

0

0

(a)

5.

(b)

Im

Im

IDf

IDf

0

t

Irr

0

The energy stored in CS1 is resonantly transferred to Co1 when switch S1 is switched on, in the path CS1 - Dt1 - Co1 - LS2 - LS1 - S1. The energy stored on Co1 is resonantly transferred to the dc supply Vs through transformer T1 when switch S1 is turned off and (after an underlap period) S2 is turned on (in the path Co1 Lr1 - T1 - S2). When S2 is turned on, the turn-on snubber inductor LS1 releases its energy in parallel with capacitor Co1 (in the path LS1 - Ds1 – Dt1 - Lr1 - T1 - S2 - LS2). The diode Dr1 prevents (by clamping) the transfer capacitor Co1 from reverse charging, by providing an alternate path for the remaining energy in the resonant inductor Lr1 to be returned to Vs via the coupling transformer T1. The transformer T1 magnetising current is also returned to the dc supply Vs, thereby magnetically resetting the coupling transformer T1.

The numerical subscripts ‘1’ and ‘2’ are interchanged when considering the recovery processes associated with switch S2. The recovery circuit can operate at switching frequencies far in excess of those applicable to the IGCThyristor and the high power IGBT. The limiting operational factor tends to be associated with the various snubber reset periods which specify the switch minimum on and off times. Although adequate for IGCThyristor requirements, minimum on and off times are a restriction with the IGBT.

Im+Irr

Im+Irr Im

IT

t

Irr

322

load gives poor regulation at low load current levels where the capacitor turn-off energy, which is fixed, may exceed the load requirements. Energy recovery involves a coupled magnetic circuit which can induce high voltage stresses across semiconductor devices. Such conditions can be readily avoided if a split capacitor (multilevel) voltage rail, fed from multiple secondaries, is used, as shown in figure 9.2c. Dual snubber (inductor and capacitor) energy recovery occurs as follows. For switch S1, the turn-off snubber is formed by CS1 and DS1, and the turn-on snubber comprises LS1.

Vs

Ds


Im

IT

0

t

0

Vs+2VC

t +

Vs+VC

Vs VDf

Vs

VDf

+ 0

t

0

t

Vs+2VC Vs

V VT 0

Vs + VC

V

Vs

VT

off

on

off

0

off

on

off

t Vs + VC

t Vs+½VC

Vs

Vo/p

+

Vs

Vo/p ½Vs

0

+

½Vs -VC

(c)

t

0

-½VC

t

(d)

Figure 9.19. Active inductive turn-on snubber energy recovery circuits: (a) multiple single-ended circuit; (b) cross-coupled high frequency circuit; and (c) and (d) respectively circuit waveforms.

9.4.2 Turn-on and turn-off snubbers i. Passive recovery - recovery into the dc supply Figure 9.20 shows an inverter bridge leg where both switches have inductor turn-on and capacitor turnoff snubbers and passive energy recovery circuits. The circuit also recovers the energy associated with freewheel diode reverse recovery current. Both the turn-on energy and turn-off energy are recovered back into the dc supply, Vs. Although this decreases the energy transfer efficiency, recovery into the

Figure 9.20. Unified, passive snubber energy recovery circuits for GTO and GCT inverter bridge legs.

ii. Active recovery - recovery into the dc supply Figure 9.21 shows two similar turn-on and turn-off snubber, active energy recovery circuits, which are particularly suitable for bridge leg configurations. In figure 9.21a, the turn-on snubber section is similar in operation to that shown in figure 9.4 while the turn-off snubber section is similar in operation to that shown in figure 9.13a. A common buck-boost smps is used for each turn-on and turn-off snubber pair. This arrangement is particularly useful when the two power switches and associated freewheel diodes are available in a single isolated module package. The active recovery circuit in figure 9.21b shows the inductive turn-on snubbers relocated. The buckboost smps inputs are cross-coupled, serving the turn-on snubber of one switch and the turn-off snubber of the other switch.

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The interaction of turn-off snubbers in both circuits can create high L-C resonant currents as discussed in section 8.4. In each case, two buck-boost smps and intermediate storage capacitors Co can serve numerous bridge legs, as in a three phase inverter bridge. Theoretically the recovery smps diodes Dr can be series connected, thereby eliminating a diode, as shown in figure 9.21c. But to do so assumes the two inductor recovery currents are both synchronised and equal in magnitude. Extra diodes, Di are needed to divert any inductor current magnitude imbalance, as shown in figure 9.21c, which negates the diode saving in having series connected the recovery diodes Dr. Alternatively, the single inductor recovery circuit in figure 9.21d may be used provided the smps switches are not conducting simultaneously. Synchronisation of the smps switch to its associated main switch avoids such simultaneous operation. The recovery circuits in figure 9.21 parts c and d are applicable to both the bridge leg circuits in figure 9.21 parts a and b. The circuit in figure 9.21a is readily reduced for single-ended operation, as shown in figure 9.18.

Co

Co

+

Dr

x

Tsmps

x

Dr

Cs

see figure 9.4

Lsmps

y

Dr

Dr

Co

324

9.5.1 Snubbers for the cascaded H-bridge multi-level inverter Since the cascade multilevel inverter (see figure 15.38) is comprised of identical H-bridge modules, any of the snubbers for bridge legs considered in section 9.4 are applicable. Snubbers can be active or passive, incorporating only an inductive turn-on snubber or a capacitive soft turn-off snubber or both turn-on and turn-off snubbers. When the cascaded H-bridge approach is used for three-phase VAr compensation, real power must be returned to the ac system if the recovered energy is in excess of the inverter losses. 9.5.2 Snubbers for the diode-clamped multi-level inverter Various snubbers have been proposed for the neutral point clamped inverter which involves a split dc rail composed of two series connected capacitors, as shown in figure 15.38. Generally devices are asymmetrically stressed or indirectly snubbered. Indirect snubbering approaches should be avoided since the main problem with high power multilevel inverters is the decoupling of circuit inductance. For levels higher than three, only the outer switches have a fixed dc reference, viz., 0V or Vdc, hence recovery circuits on these switches can return energy to the outer link capacitors. Energy recovery from snubbers on the inner switches is hampered by the clamping diodes. Thus recovery of snubber energy in a three-level inverter is viable since the two link capacitors are in fact two outer capacitors, referenced to the dc rails. Recovery must be into the associated level capacitor of a given switch, if recovery circuit component voltage ratings are to be limited to that of the main switching elements. 9.5.3 Snubbers for the flying-capacitor clamped multi-level inverter

y

Tsmps


Co

Turn-off snubbers for the flying capacitor clamped inverter are problematic since the switch clamping principle is based on indirect clamping and the level clamping capacitors support multiple-voltages in excess of the individual device operating voltage ratings. As seen in figure 15.40, the flying capacitors associated with inner switches support lower voltages than the outer capacitors.

+ (d)

Lsmps Tsmps

Co

Co +

x

Dr

x

9.6

y

Two basic approaches are adopted when power-switching devices are series connected in order to operate circuits at voltages in excess of individual device voltage ratings. • Use a multilevel structure as considered in Chapter 15.3, where individual switches are effectively soft clamped or • series connect devices with fast turn-on and turn-off, minimising device switching delays thereby improving transient voltage sharing; possibly using simple R-C snubbers

Di see see figure figure 9.3 9.4

Dr Di

Dr y Co

Tsmps

Co

+

Lsmps (c)

Figure 9.21. Unified, active snubber energy recovery circuits: (a) multiple single-ended circuit; (b) cross-coupled high frequency circuit; and (c) and (d) coupled smps variations.

9.5

As a general rule, if snubbering is being considered, then a series connection approach as in section 9.6 is viable, provided device switching delays are minimised. The turn-off delay of the GCThyristor can be reduced to less than 400ns if high di/dt reverse gate current drive is employed. The key limitation in reverting to series connected device operation is the loss of amplitude modulation offered by multi-level circuits. As a consequence, series connected devices produce higher output dv/dt voltages. The diode clamped inverter with numerous series connected devices is a favoured medium voltage compromise.

Snubbers for multi-level inverters

The multi-level inverter introduced in Chapter 15.3 utilises series connected switching elements with each switch operated in a voltage clamped mode. Three multi-level inverter configurations are commonly presented • the diode clamped multi-level inverter – see figure 15.38 • the flying capacitor clamped multi-level inverter – see figure 15.40 and • the cascaded H-bridge multi-level inverter – see figure 15.41

Snubbers for series connected devices

The use of turn-on and turn-off snubbers greatly increases system complexity and size but does offer a method for reliably operating series connected devices, a modular structure, and the possibility of obtaining gate drive power for individual series connected cells. Fast, noise free, isolated uni/bidirectional signal transmission, without any isolation or dv/dt problems, to virtual any voltage potential is possible with fibre optics. The production of isolated gate drive supply power at tens, possibly hundreds of kilovolts is problematic. The usual approach for deriving emitter level supplies involves tapping energy from static voltage sharing resistors, resulting in high resistor losses, or tapping energy from the R-C snubber during switching transitions. Both methods do not provide fail-safe device operation (in the off-state, with static dv/dt capability) at the application of the HV dc link voltage. The use of inductive and capacitive switching snubbers offers two advantages, other than enforcing transient voltage sharing of series connected devices, which may mitigate the associated increased cost and complexity • Better device I-V utilisation and a higher switching frequency • The derivation of cell level gate power supplies from snubber recovered energy Many of the previously presented active snubber energy recovery circuits in this chapter are directly transferable to multilevel inverter configurations, thereby extending the current and frequency capabilities of the main switching devices, particularly the GCThyristor, and freewheel diodes. Once

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snubbers are employed, traditional series device connection with snubbers is simpler than a multilevel approach, but does not offer the multilevel output voltage features (amplitude modulation and reduced dv/dt) of multi-level inverter configurations. The snubber recovered energy is usually far in excess of that that can be utilised for gate drive power. The topological nature of series connected devices precludes any form of relatively simple snubber energy recovery (active or passive) other than recovery back into the dc link supply. 9.6.1

Turn-off snubber circuit, active energy recovery for series connected devices

i. Recovery into the dc supply Series connection of switches and diodes requires static voltage sharing (resistors) and transient voltage sharing circuitry, viz., capacitive turn-off snubbers for voltage sharing during turn-off and inductive turnon snubbers for voltage sharing during turn-on. Figure 9.22 shows series connected devices, each modular cell level incorporating a main switch and inverse parallel connected freewheel diode, plus a turn-off snubber Cs - Ds, a resonant circuit L - Do, an intermediate energy storage capacitor Co, and buckboost smps recovery circuitry Tsmps - Lsmps - Dsmps, as shown in figure 9.13a and considered in 9.2.2. The recovery smps is operated so as to maintain a near constant voltage on the intermediate storage capacitor Co. The cell energy recovery switches Tsmps are synchronised, all being turned on for up to the switch minimum on-time (immediately before the switches T are turned off), and turned off when the main switches T are turned off. The timing sequence for the control signal, switch T and recovery switch Tsmps is shown in figure 9.22b. Note that the transmitted control signal is truncated at the switch T turnoff edge, by the switch minimum on-time, tdelay, which is approximately ½π√LCs. When Tsmps are turned off, the inductive stored energy in each Lsmps is returned to the dc link through each corresponding diode Dsmps as shown in figure 9.22a. Any imbalance in the individual inductor current magnitudes, involves currents in excess of the minimum of all the inductor currents being diverted to the cell snubber capacitor Cs through Dsmps - Cs - Ds - Lsmps. The inductor recovery current differentials are minimal compared to the principal current in the switches, hence do not unduly affect capacitive turn-off snubber charging, hence transient turn-off voltage balancing action. Vs Ls

T

Df DC rail

Io

Dsmps

+ T

Df

Cs

Da

L

Ds

Tsmps Co

+

Lsmps tdelay

signal

on

T

Df

t

Dsmps

+

T

Cs

Da

L

Ds

on

Tsmps Co

+

t

Lsmps Tsmps

on t

Dsmps

+ T

Df

Cs

Da

L

Ds

Tsmps Co

Co >>Cs

ILsmps

+

t

Lsmps

0V rail

(a)

(b)

Figure 9.22. Active turn-off snubber energy recovery for series GCT connected, inverter bridge legs: (a) modular cell circuit and (b) timing diagram.


326

The turn-on snubber Ls in figure 9.22 is indirectly clamped, with the stored energy released into the series string of turn-off snubber capacitors. Link inductance is mandatory in order to control recharging of the turn-off snubber capacitors as considered in section 8.4. Although the smps switch Tsmps and diode Dsmps are high voltage devices, rated at the cell voltage level, both are not particularly stressed during energy recovery switching, since the recovery buck-boost smps are operated in a discontinuous inductor current mode. The switch Tsmps turns on with zero current, without any diode reverse recovery effects, while the diode Dsmps suffers minimal reverse recovery, since its principal current reduces to zero controlled by Lsmps, with recovery di/dt current (or voltage) controlled (or supported) by the smps inductors Lsmps. A static voltage-sharing resistor across each cell (not shown in figure 9.22) compensates for various static voltage and current imbalance conditions on both the main switch T and smps diode Dsmps network, particular during converter start-up and shutdown sequencing. System start-up The intermediate transfer stage capacitor Co can be used to provide a source of gate level power, via a dedicated smps. One of two start-up sequences are used to build-up gate power and cell voltages before normal switching operation can commence. In both cases, an ac to dc single or three phase halfcontrolled converter is used to ramp charge the intermediate capacitor Co associated with the lowest potential cell (typically Co operates at about 50V to 100V). This capacitor Co in turn provides gate power, via a dedicate 100V dc to ±15Vdc smps, for the lowest level switch T. By using series blocking/directing diodes, rated at the cell voltage rating, one ac to dc converter can supply the lowest potential cell of all bridge legs, as shown in figure 9.23a. Proprietary pre-charging sequences are used to charge Co on higher cell levels, depending on whether the dc link voltage is established or not. As each Co is progressively charged, its associated gate supply smps is self-activated, enabling external control of that switching cell. Inverter start-up can involve the application of the dc link voltage before gate level power has been established. This does not present a problem for GCThyristors, but in the case of the IGBT, a low passive impedance gate to emitter circuit is needed to avoid inadvertent device turn-on due to Miller capacitor dv/dt effects. (a) Start-up with an established dc link voltage In the case of an inverter with an established dc link voltage, each level switch, hence cell, supports half its normal operating voltage, and each snubber capacitor Cs is charged to the cell voltage level. All the intermediate energy storage capacitors Co are discharged, except for the lowest potential cell capacitor, which has been ramp charged by the ac to dc converter. The recovery smps (and main switch) of the lowest potential cell is operable. Tsmps of the lowest potential cell is turned on, then off and the current in the associated Lsmps tends to overcharge Cs of the lowest potential cell. This forces current to increase through the Co - L - Ds combinations of the higher potential cells as each Cs is forced to decrease its charge, therein charging higher-level capacitors Co. The voltage on Cs of the lowest potential cell can be doubled before the cell reaches it normal operating voltage level. Thus for n series connected cells, the operating limit of the intermediate capacitor Co voltage satisfies (n-1)VCo < 2Vs /n. That is, any smps sourcing from Co used to provide gate supply voltage rails for the main switch T, must be able to function (convert) down to a voltage level satisfied by this inequality equation. When a cell voltage reaches its operating voltage limit, the associated main switch is turned on briefly to resonantly discharge the snubber capacitor Cs. The supported voltage is redistributed among the other cells, which typically, are only supporting half the normal cell operating voltage. (b) Start-up with no pre-existing dc link voltage In the case where the dc link voltage has not been established, a similar charging process is used as for the case of a pre-existing dc link voltage. The dc link capacitance must be on the inverter side of the isolation. The dc link capacitor is initially charged through series diodes Df to the maximum cell voltage as capacitor Cs of the lowest potential cell is parallel charged from Co by its associated recovery smps. The lowest potential recovery smps is commutated numerous time in order to charge the dc link capacitance which is usually significantly larger in capacitance than Cs. Once the link capacitor is charged to the maximum allowable cell voltage, the main switch T of the lowest potential cell is turned on to reset its associated snubber Cs voltage to zero. The start-up mechanism used with a pre-existing dc link voltage can then be used. Once Co in each cell is charged sufficiently to enable its gate voltage smps to become operational, synchronised use of the recovery smps at each level allows charging of the dc link capacitor to the operational voltage level (in fact slightly in excess of the rectified peak level). Then the vacuum circuit breakers before the rectifier, feeding the series connected device circuit, can be closed, which results in zero line current in-rush. Connection of the load and an interfacing filter may be problematic without dedicated contactors, as is the influence of the output filter on the cell charging mechanism previously outlined. Other gate power derivation methods Gate power derived from switching recovered energy cannot be maintained during prolonged standby periods. Using dropper resistors (as for static voltage sharing) to provide all gate level power

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requirements results in high dissipation losses, particularly during continuous standby periods (that is, 100% dissipation duty cycle). Although resistors are used for steady-state series voltage sharing, the current associated with this mechanism (≈10mA, depending of the degree of device matching and operating temperature range) is well below that needed for gate power (≈50W for IGCThyristors but much less for IGBTs). But this level of sharing resistor current (≈10mA) may be sufficient to trickle maintain gate level supplies of cells in the off-state during prolong standby periods, using variations on the circuits shown in figure 9.23c. Depending on the load and output filter, it may be possible during prolong standby periods to sequence the inverter between 000 and 111 states, thereby producing zero average voltage output between phases but activating the snubbers hence resonant recovery circuits that charge each Co. Provided sufficient switch voltage redundancy is available, sequential bootstrapping is possible where each level is boot strapped supplied from the immediate next lower level, as shown in figure 9.23b. (See figure 7.4). In the case of a positive voltage as shown in figure 9.23b, each switch, starting from the lowest level is sequentially turned on and off, thereby transferring gate energy from the lowest level to the highest level. (An expanding repetitive simultaneous on-state sequence is used, progressively involving higher potential cells.) This approach is viable in single-ending series connected switch applications. Although each bootstrap diode Dbs is rated at the cell level voltage, in the case of inverter legs, only half the inverter leg devices can be supplied, since any bootstrap diode bridging the pole centre take-off node must be rated at the full dc link voltage (actually ½n-1 levels can be charged since the lowest level cell is not bootstrapped). If the bootstrapping voltage is referenced with respect to the high potential terminal of the cell, then the supply voltage on Co is bootstrap by transferring energy from the highest potential cell down to the lowest potential cell. A similar approach can be used with transformer isolated smps’s transferring power between adjacent levels, which need only be rated at the cell level voltage. Again, this approach is viable in single-ended applications, but in the case of inverter legs, the pole output take-off node cannot be readily bridged by an smps because of the high dc link voltage blocking and isolation requirement. Also, each smps experiences dv/dt stresses when the level switches are commutated. Possibly the simplest and most reliable method to derive gate power in series connected circuits, up to a few 100kV, is to use ac current transformers with series connected single-turn primaries, where each level short-circuits the secondary when not charging.


maintains the voltage near constant on its associated Co and the higher this voltage the faster the inductor Ls current is linearly reset to zero, in time treset = LsIm / VCo. Excess energy on Co is transfer (recovered) to the dc link by synchronised switching of Tsmps. Mismatched inductor Lsmps current magnitudes and durations are diverted to charge Co of any cell attempting to recover a lower current magnitude, by turning off all Tsmps just before all the main switches T are turned off, as shown in figure 9.24b. This balancing effect is minimal (but does eliminate any smps diode forward recovery effects) and any current imbalance subsequently tends to overcharge the output capacitance of the main switch of the cells with recovery current in excess of the minimum of all the smps recovery currents. Some form of turn-off snubbering is therefore necessary in order to avoid excessive main switch T voltages at turn-off. The voltage rating of the various cell circuit semiconductors is increased by the voltage on Co. A cell static voltage sharing resistor helps maintain steady-state voltage balance of both the main switch T and the smps diode Dsmps. a Start-up One ac to dc converter can be used to pre-charge each lowest level capacitor Co of each inverter leg, as shown in figure 9.23a, provided the path to each inverter leg incorporates a series blocking/directing diode, rated at the cell voltage level. The start-up sequence, using the lowest level smps to charge higher level Co and the dc link to the sum of all Co voltages, is straightforward. Synchronised operation of all the smps can then gradually fully charge the dc rail, if it is not already pre-charged.

Vs

on T

Df

t

Dsmps T

Ds

on

Tsmps

t

Ls + Co3 Db2

+

+

Co2

Co1 +

Vo

+

15V

+ Co1

(b)

15V

Lsmps

on

Ds

ILsmps

Dsmps

t

Tsmps

Ls 15V

Cell 1

0

(c)

Figure 9.23. Gate supply derivation methods: (a) ac to dc half-controlled converter for ramp precharging of all lowest leg level capacitors Co; (b) bootstrapping a positive voltage supply; and (c) Zener diode based sources using static voltage sharing resistors or/and R-C snubber resistors.

9.6.2

Df

0

+

Co

Tsmps

t

T

+

Cell 2

Dbs 0V

(a)

+ 0

+ Co2

+

Dbs Db1

Co3

hv

Cell 3

tdelay

signal

Io

hv

Db3

328

Turn-on snubber circuit active energy recovery for series connected devices

i. Recovery into the dc supply An active energy recovery, inductive turn-on snubber as shown in figure 9.4 (usually with an R-C turn-off snubber), can be adapted and used at each series cell level, therein providing gate level power possibilities from Co and energy recovery through series connect buck-boost smps recovery circuitry, as shown in figure 9.24a. The capacitor Co is configured to be connected to the emitter of switch Tsmps. Energy stored in the turn-on snubber inductor Ls is transferred to the intermediate storage capacitor Co via diode Ds at switch T turn-off. The switching sequence is shown in figure 9.24b. Each recovery smps

+

Co

Lsmps

(a)

(b)

Figure 9.24. Active turn-on snubber energy recovery for series GCT connected, inverter bridge legs: (a) modular cell circuit and (b) timing diagram.

9.6.3

Turn-on and turn-off snubber circuit active energy recovery for series connected devices

i. Recovery into the dc supply If a single inductive turn-on snubber Ls is used in the dc link as in figure 9.22a, its stored inductor energy at switch turn-off is transferred to the capacitive turn-off snubbers of cells supporting off-state voltage. During switching, this causes voltage ringing between the cells and the link inductor. This inductor is rated at the full dc link voltage and cannot be clamped by the usual resistor-diode parallel connected reset circuit as in figure 8.19a. This is because any reset components (R-D) need high voltage ratings – in excess of the dc link voltage during diode Df reverse recovery. For this reason, an inductor snubber (possibly saturable) may be used at each cell level, giving a complete modular cell structure. Active snubber energy recovery of both inductive and capacitive energy is possible, although it may be convenient to resistively dissipated the turn-on inductive snubber energy, which is load current dependant, ½LsI2.

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Dual, unified active snubber energy recovery can be achieved by using the recovery circuits shown in figure 9.21b, but with the smps diodes series connected as shown in figure 9.25a. For a modular cell structure, all the cells are configured as for the lower switch in figure 9.21a. This switch configuration in figure 9.21a is preferred since capacitor Co can be readily pre-charged to initiate the start-up sequence for charging higher level Co, which can be used to derive gate level power for the associated cell. A relatively low voltage on capacitor Co (if Co operates at about 5 to 10% of the cell operating voltage) may necessitate a long switch T minimum off-time in order to ensure reset of the turn-on inductor current to zero. This is not a problem for GTO type devices which have minimum on and off time limitations. Higher operating voltages for Co necessitates a more complicated smps to derive gate level power for switch T. At higher cell operating voltages, the intermediate storage capacitor Co can be modified to the circuit in figure 9.25b. The low voltage output lv can be used to power cell start-up circuitry. The resonance inductor ℓ (in series with the turn-on snubber inductance Ls) is used to control the magnitude and duration of the resonant period of Cs transferring its charge to Co. The minimum value of inductor ℓ can be zero if Ls is large enough to satisfactorily control resonant reset circuit conditions without ℓ. A further simplification can be made by removing a resonant circuit diode as shown in figure 9.25c, which is derived from the circuits in figure 9.18. The timing sequence in figure 9.22b for turn-off snubbers is used. One functional design constraint should be observed. At switch turn-on, current builds up in Lsmps because of the voltage on Ls, during the later part of the cycle when Cs resonates its charge to Co. This relatively small current magnitude linearly increases to a magnitude dependant on the relative magnitudes of Ls to ℓ and Lsmps, and the magnitude of the voltage retained on Co. Once established, a near constant, slowly decreasing current flows in a zero voltage loop, Lsmps - Dsmps - T - Ls, and is recovered during recovery smps action at switch turn-off. 0

Vs

Co1 +

lv

Io

Cs T

+

ℓ

Df

Dsmps

Ls

General active recovery concepts for series connected devices

In each of the three snubber circuits considered for series connected devices, the common key recovery mechanism is performed by a buck-boost smps, with components rated at the cell voltage level. Figure 9.26 shows two basic underlying recovery techniques for transferring energy from Co through an inductor, into the dc supply at a higher potential. The key difference between the two techniques is the polarity orientation of the energy source Co and the dc supply Vs, with respect to their common node. • Figure 9.26 parts a and b show boost converters, where energy is drawn from Co when energy is being delivered to the supply Vs, via an inductor. • Figure 9.26 parts c and b show buck-boost converters, which do not involve Co during the period when energy is being delivered to the supply Vs, via an inductor.

+

Lsmps

Ls

+

ON

Cs

+

ℓ

Dsmps

T

+

+

T

OFF

OFF

T Vs

Ls

Co

D

Tsmps

Df

Tsmps

Ds

Dsmps

D

Vs

Co

Co1 >> Co2

Cs

Df

9.6.4

+

+

T

gate power, hence external control is established on each cell, judicious operation of each smps and main switch T can facilitate charging of the dc link capacitor and contains all cell voltages to within the rated cell voltage. The start up mechanism may necessitate a suitable diode connected in series or anti-parallel with Tsmps. (b) Shut down After the dc link has been isolated, under zero inverter output current conditions, using a vacuum circuit breaker on the ac side, the intermediate capacitor of the lowest potential cell (in each bridge leg) is maintained in a partially discharged state by a resistive load which is switch connected to the capacitor Co of the lowest potential cell. The auxiliary ac to dc converter used to initially charge Co is disabled during normal operation and shut-down, with all the ac to dc converter thyristors off, therefore blocking current in both directions. Alternatively, if this ac to dc converter has suitable two quadrant operational modes, then the energy continually being transferred to Co from other cells, can be recovered into the low voltage ac source. The various smps and main switches are operated so as to maintain equal voltage across all cells (by sequentially commutating each main switch on then off), gradually decreasing the dc link voltage as energy is continually, but controlled, being transferred to and removed from the lowest potential cell capacitor Co.

Co2 hv

Do Co

330

(b)

Tsmps

Ds


+ ON

Ls

Ds

Do Co

Lsmps +

Ls

Co

(a)

Lsmps

(b)

+

0

(a)

(c)

Figure 9.25. Active turn-on and turn-off snubber energy recovery: (a) circuit for series GCT and IGBT inverter bridge legs; (b) high voltage replacement circuit for Co; and (c) reduced component variation of part a.

+

Co

Vs Ls R

Ls

(a) Start-up The capacitor Co of the lowest potential cell (in each bridge leg) is negatively ramp charged by a dedicated ac to dc converter as shown in figure 9.23a. This establishes cell internally generated gate supply power and hence external control of both switches of the lowest potential cell. The recovery smps of the lowest potential cell is operated in a discontinuous mode, which charges up the turn-off snubber capacitor Cs of that cell. Simultaneously current flows in three other parallel paths, tending to charge up the dc link capacitor, viz. • the series connected Lsmps - Dsmps • the series connected Ls - Df • the series connected Co - Do - Df Thus provided the smps of the lowest cell delivers a high current, each Co receives charge before the current is diverted and built up in inductors Lsmps and Ls. The dc link capacitor simultaneously receives charge. The switch Tsmps on-time, hence its current, is not restricted during the start-up procedure. Once

+

Co

Vs

(c)

(d)

Figure 9.26. Underlying energy recovery circuits when energy in Co is stored at different potentials: (a) and (b) boost smps recovery and (c) and (d) buck-boost smps recovery.

A common requirement is that an smps output (whether inductor-diode for buck-boost and inductordiode-Co for boost) span a cell, thereby inherently interconnecting in series any number of cells. Each intermediate storage capacitor Co must therefore be connected to one cell terminal. To confine further

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Chapter 9

the possibilities, it is unlikely that Co referenced with respect to the cell collector will yield a useful active recovery circuit. If the capacitor Co is referenced with respect to the switch collector/anode, Co undergoes high dv/dt voltages with respect to the switch gate. This complicates any smps using the stored capacitor Co energy for gate drive purposes. The polarity orientation of Co and the recovery smps components are therefore restricted to the four possibilities shown in figure 9.27. Series recovery assumes the smps inductors conduct an identical instantaneous maximum magnitude and same duration current. (a) Start up The general cell structures and their recovery smps can inherently be used to charge other series connected cells and the dc link, and to provide a dc source (the intermediate storage capacitor Co) from which to derive cell level power supplies for the gate level circuitry. Specific proprietary switching sequences are required at start-up, depending on the cell circuit arrangement, the output filter and load, the dc link and ac rectifier input arrangement and initial conditions. (b) Shut down At shut down, once the inverter is in standby, the dc link supply is isolated (by opening the ac side vacuum circuit breakers) under zero current conditions, then the dc link voltage is cyclically discharged into the load via the series connected cells. Such link discharge using cell switching sequences is problematic when • each cell voltage reaches a level where Co falls below a level to maintain operation of the smps used to provide gate level voltage which allows the cell switches to operate; or • cells in another inverter legs cease to operate sooner. Such limitations are mitigated by ensuring the smps that operates across Co has a wide (low minimum bounds) input voltage operating range. If the load is isolated at shut down, then the dc link energy can be sequentially transferred to Co of the lowest potential cell in each leg and dissipated in a single ended resistive dumping circuit or recovery from Co via the ac to dc converter (fully controlled) used during the start-up sequence, as shown in figure 9.23a. The sequence involves progressively, but sequentially, not using higher-level recovery smps. Fail-safe start-up and shut down sequencing, so as not to over-volt any cell, usually require cell operational coordination. The fibre optic communications link for cell level on/off control of the main switch T, is therefore bidirectional.


• •

332

leakage or uncoupled inductance energy release time-displaced energy-transfer coupled-circuits, as with the buck-boost converter or coupled voltages as with push-pull centre tapped transformer circuits

Both factors come into operation with the two buck-boost isolated output converters shown in figure 9.28. When energy is drawn by the coupled circuit secondary, a voltage is induced into the primary, increasing the voltage experience by the switch in the off-state. Energy associated with leakage inductance further increases the switch T voltage. If a basic R-C-D turn-off snubber is used, the capacitor stored energy is increased from ½C sV s2 , if the switch voltage were to be limited to Vs, to in 2 excess of ½C s (V s + v o /N ) , where N is the transformer turns ratio as defined in figure 9.28. The leakage energy adds to the voltage component. 9.7.1 Passive recovery Figure 9.28a shows a passive turn-off snubber energy recovery configuration for an isolated buck-boost converter. It is based on the circuit in figure 9.31j, where the transformer leakage inductance, Lℓ, is effectively the turn-on snubber inductance. When the switch T is turned off, the snubber capacitor Cs charges from - Vs to a voltage vo /N, controlled by the leakage inductance Lℓ which causes the capacitor Cs to charge to a higher voltage. Turn-off capacitor Cs snubbering of the switch is achieved indirectly, through the dc supply Vs. At switch T turn-on, the charge on Cs resonates in the loop Cs - T – Lr - Dr, reversing the polarity of the charge on Cs. This reverse voltage is clamped to Vs, as the diode Ds conducts and the remaining energy in Ls is transferred (recovered) to the dc supply Vs. The switch minimum on-time is ½ π Lr C s , whilst the energy recovered from Lr to Vs occurs independent of the state of the switch. At switch T turn-off, after snubber capacitor Cs is fully charged, an oscillation can occur through Lr - Dr Cs and the transformer primary back into the supply Vs. Although a lossless oscillation, it can effect the output voltage regulation, increase output rectifier recovery losses, but can be prevented by using a series switch in the Lr - Dr path as shown in figure 9.28d. Then recovery occurs during switch T onperiod, back into the supply Vs, without affecting the output regulation. Once a switch has been used, other active recovery possibilities may be more attractive. The same leakage voltage control and recovery technique can be used on the push-pull converter in figure 9.28c, where two recovery circuits are used. Tr

+

Cs

1:N Do

Ds + Co

Vs

Co

Lp

+

Ls Co

+

Lr R

Do

Ds

vo Vs

Lℓ

Ls Co

Lp

+

Lℓ

+ R

1:N

+ Dr

(a)

(c)

(b)

(d)

Dr

Cs

T

Lr

(a)

(b)

Lℓ + Co

T

Cs

Co

Ds

Ds

Lℓ

Lℓ

Cs

Cs

Lℓ Ds

Ds

Cs

+

Figure 9.27. Cell active energy recovery from Co with: (a) and (b) a boost converter and (c) and (d) a buck-boost converter.

T

Dr Lr

+

Vs

Dr

T

Vs +

T

Lr Lr

Dr

(c)

9.7

Snubber energy recovery for magnetically-coupled based switching circuits

Coupled circuits can induced circuit and in particular switch voltages that exceed the supply voltage. These increased voltages are associated with two factors:

T

Figure 9.28. Recovery of leakage inductance energy: (a) and (c) passive and (b) and (d) active recovery.

(d)

vo

333

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Chapter 9

9.7.2 Active recovery Figure 9.28b show the circuit of an active turn-off soft snubber energy recovery configuration. Coupled circuit leakage inductance Lℓ energy is transferred to the intermediate storage capacitor Cs via Ds at switch turn-off. The voltage on Cs is maintained at a voltage related to vo /N by the buck-boost smps formed by Tr, Lr and Dr, which returns leakage energy to the dc supply Vs. The circuit function is to clamp the switch voltage rather than to perform a turn-off snubber action. The maximum switch voltage is near constant, where as the voltage experience by the switch at turn-off in figure 9.28a, although variable, is snubbered, but dependant of the output voltage vo. In both circuits, an R-C snubber may be required across the switch T since the recovery snubber circuits do not decouple stray inductance not associated with the coupled magnetic circuit. Similar active snubber or clamping circuits can be used with push-pull converters which utilise a centretapped transformer, as in figure 9.28d, where, with a full-wave rectified forward converter secondary circuit, the overvoltage is independent of the transformer turns ratio. The recovery circuit switches prevent undesirable lossless oscillations after main switch turn-off, particularly when the switch duty cycle is less than 50%. The diode Dr allows the active recovery switches to be activated with the same control signal timing as the corresponding main switch T, provided the switch minimum on-time is at least ½ π Lr C s . In the active recovery form, only one common reset inductor Lr is necessary. 9.8

General passive snubber energy recovery concepts for single-ended circuits

Snubbers are used for stress reduction at • switch turn-on - involving series inductance • switch turn-off – involving shunt capacitance • freewheel diode recovery - involving series inductance and the snubber may incorporate more than one of these stress arresting functions. A single ended switching circuit usually incorporates a switch T, a freewheel diode Df and an inductive load, where the load may be configured to be in • the emitter/cathode circuit of T or • the collector/anode circuit of T. The input energy source, the switch, diode and load may be configured to perform any of the following functions • forward converter • buck converter • boost converter or • buck-boost converter The differentiation between the forward converter and the buck converter is that the inductive element is part of the active load in the case of the forward converter. Figure 9.29a shows a switch-diode and inductor circuit combination, assuming a collector load circuit, which can be configured as any type of converter viz., forward, buck, boost, etc. Equivalent emitter load circuits, as well as collector loadings, are shown in figures 9.30 and 9.31, which present systematically a more complete range of circuit possibilities, in each case, all with exactly the same functional snubber circuit. Energy recovery into the load is usually associated with a parallel connected capacitor discharging (instantaneous change in capacitor current to match the load current is possible) while recovery back into the source is usually associated with a parallel connected inductor or magnetically coupled circuit releasing its energy (instantaneous change in inductor terminal voltage to equal the supply voltage is possible). Ac and dc circuit theory allows all these circuit configuration combinations to be generalised. This is because a snubber is an ac circuit – performing a transient function - while the source and load tend to be dc components (constant voltage and constant current sources respectively). Therefore it is possible to interchange the connections of the snubber (an ac circuit) with the connections to the dc voltage source, since ac-wise, a dc source appears as a short circuit. The snubber function can be achieved directly (across the switch) or indirectly (assuming a well decoupled supply). An operational mechanism to be appreciated is the topological relative orientation within the principal circuit of the turn-on snubber inductor or turn-off snubber capacitor. Turn-off snubber - capacitor: Circuits in figure 9.29c and d show the turn-off snubber Ds - Cs combination parallel to the switch (direct snubbering) or alternatively connected across the freewheel diode to the dc rail (indirect snubbering). AC circuit wise these are the same connection since the dc source can be considered as a short circuit at high frequency. When Ds - Cs are parallel connected to the switch (direct


334

snubbering), the capacitor charges as the switch voltage rises at turn-off, while in the case of the snubber being across the freewheel diode (indirect snubbering), the capacitor discharges, and by Kirchhoff’s voltage law, the switch voltage is indirectly controlled to be the difference between the capacitor voltage and the source voltage. Practically it is preferred to place the Ds - Cs snubber directly across the element to be protected, the switch, since the source may not be well decoupled. Turn-on and diode reverse recovery snubber - inductor: Circuits in figure 9.29a and b show the inductor L configured such that the snubber turn-on inductor is in series with the switch (direct snubbering) or alternatively in series with the freewheel diode (indirect snubbering). Both arrangements perform the same function at switch turn-on. Assuming a constant current in the inductor L, by Kirchhoff’s current law, whether the turn-on inductor controls the rate of rise of current in the collector (direct snubbering) or rate of current fall in the diode (indirect snubbering), the complementary element has its current inversely controlled. Figure 9.30 shows variations of a snubber for recovering the energy associated with freewheel diode reverse recovery. All twelve circuits have the same functional ac operating mechanism, although a number have been published – even patented - as different. US patent 5633579, 1997, according to the three claims, explicitly covers the boost converter snubber circuit in figure 9.30a. In protecting the specific boost converter circuit, all the other topological variations are inadvertently and unwittingly implicitly precluded. Although a highly skilled expert in the art, Irving, IEEE APEC, 2002, published the next recovery circuit, figure 9.30b, as a new diode recovery snubber for the boost converter. Passive inductive turn-on snubber energy recovery circuit variations are shown in figure 9.31, for collector and emitter connected buck, boost, forward and buck boost converters. Six versions exist with the circuitry in each of the switch emitter and collector circuits. Figure 9.32 shows turn-off and turn-off plus turn-on passive recovery circuit variations. The circuitry can be in the emitter or collector (as shown) circuit.

Reading list Boehringer, A. et al., ‘Transistorschatter im Bereich hoher Leistungen und Frequenzen’, ETZ, Bd. 100 (1979) pp. 664-670. Peter, J. M., The Power Transistor in its Environment, Thomson-CSF, Sescosem, 1978. Williams, B. W., et al., ‘Passive snubber energy recovery for a GTO thyristor inverter bridge leg’, Trans. IE lEEE, Vol. 47, No. 1, Feb. (2000) pp. 2-8. Williams, B. W., ‘High-voltage high-frequency power-switching transistor module with switching-aidcircuit energy recovery’, Proc. lEE, Part B, Vol. 131, No. 1, (1984) pp. 7-12. Finney, S. J. et al., ‘High-power GTO thyristor chopper applications with passive snubber energy recovery’, Proc. lEE, EPA, Vol. 144, No. 6, (1997) pp. 381-388.

Problems 9.1.

For the circuit in Figure 9.14a show that the upper current limit for total energy recovery is given by ½ Ls I m2 ≤ ½CsVs2 .

9.2.

Derive capacitor Cs voltage and current equations which describe the operation of the turn-off snubber energy recovery circuit in figure 9.13. Assume the storage capacitor Co to be an ideal voltage source with polarity as shown.

Power Electronics

335 +

Df Ls

Cs


+

Df

+

Df

Dr

+

Dr

Vi

Ds Ls

L

+

Df

Dr

Cs

L

Cs Ds

Ls

Dr Co

Df

Do

Ls

L

(d) T T

Df

C

Ls

Ds

L

Cs

T

+ Cs

Df

Generalised switched-mode circuit

B

+

T

Df

+

+

+

+

Vi

T

Cs

T 0

0

(d)

+

Ls

Ds

Vi

+

Ds

Vo

Df

0

0

(e)

(f)

Dr

buck/forward

+

0V

+

T

ℓ

(b)

+

Df

Cs Ds

Ls

Dr

Ds

L

Cs

T

0

inductive turn-on snubber - passive energy recovery

+

Df

0

0

(h)

Vo

Df

Dr

+

T

Vo

Vi

Ds

Ls

Ds L

+

+ Vo

Df

Vi

Dr

T

0

0

(j)

buck-boost

Vi

Ls

Ds

Ls

Cs

Vi

(i)

T

L

L+

Cs

+

+

L

Cs

Df

Dr

0

0

(k)

(l)

+ Vo

0 +

T

capacitive turn-off snubber - passive energy recovery

T

Ls

ℓ

Df

Co

L

Cs

Dr

ℓ

+

Df

Ds

Do

(c)

0

+

Dr

L

Cs Dr

(g)

Vo

L

Ls

Ds

Ls

Cs

T

Vi

0

Cs

Dr

T

L

z Ls

+

T

Vo

Cs

T

Ds

Dr

Df

L Vi

Ds

Ls

Ds

L

(c)

+

Df

Dr

Ls

L

C

Ls

C

+

Df

Vo

Cs

0

boost

Ds

Ls

Vo

Vo

Df

Dr Do

L

L

Ds

0

(b)

L

Do

y

A

+

0

0

Df

Dr Co

Vi Ds Cs

Ls

Dr

(a)

Cs x

Vo

T

+

0 +

T

L

Vi

Dr

0

Ds

+

+

Cs Ls

T

+

Dr Do

Ds

(a)

+

+

T

Df

Vi +

L

Vo

+ L

0 +

+

Cs Ds

inductive turn-on and capacitive turn-off snubber - passive energy recovery

T

+

336

inductive freewheel diode reverse recovery snubber - passive energy recovery

+

Dr

Chapter 9

Ds

ℓ

Df

Co Dr Do

+

Figure 9.30. Passive energy recovery of freewheel diode recovery energy: (a)-(d) a boost converter; (e)-(h) a buck/forward converter; and (i)-(l) a buck-boost converter.

L

Cs T 0

converter

ports

transfer function

nodes

forward /buck

B/A

δ

xy/xz

boost

A/C

1 / (1- δ)

xz/yz

buckboost

-B/C

-δ/ (1- δ)

yx/yz

Figure 9.29. Snubber energy recovery circuits for generalised switch-diode-inductive element circuit.

Power Electronics

337

Chapter 9

Switching Aid Circuits with Energy Recovery Df

338

+

Dr

Df

+

Dr

Cs

+

Df Ls

+

Cs

+

Df

Ds

Vi

Cs

Ls

Vo

T

Dr T

ℓ

Ls

Vo

0

0

(a)

(b)

Df

Ds

Co ℓ

L

Df

boost

+

Dr

Df

+

0

0

(c)

(d)

+ L

Ds

Vi

+

+

Df

Ds

Ds

Vo

Vo

Ls

L

ℓ Ls

Vi

Dr

Dr T

ℓ

+

T

Dr

L +

Cs

Ls Vo

Ds

ℓ

Df

0

(e)

(f)

buck/forward

Df

Ds

Ds

+

Vo

(g)

(h)

ℓ

Ls

Cs

Cs L Dr T

ℓ

+ Vi

Ls

Cs

Vo

Ds

ℓ

Df

Dr Co

T

Do

Df

0

(i)

(j)

0

buck-boost

Dr

ℓ Vi

Do

Ds

Vo

Cs

T 0

Dr Co

Df

Do

Ls

T

Do

Vo

Dr

Df

C

Ls

+ Vo

Vi

T

Ds

L

Cs

T

0 +

Ds

L

Cs

T

0

Cs

Df

Dr Co

+

0

Ls

Ds

(c)

T

Cs

T

(d)

Vo

L

C

Vi

Ls

+

Df

Dr Do

L

Do

Vi

+ Vo

Ds

buck/forward

+

+

Vo

C

0 Vi

+

L

+

Df

0

0

Turn-on and off snubber

Vo

0

(k)

Co

Ls

0

Do

L

Turn-off snubber L

Ds

+

Vo

ℓ

Ls

Cs

+

Df

Dr

T

0

L

Vo Vi

Ds

Cs

ℓ

Ls

Vi

Dr

(b)

Vo

+

+

+

Do

Turn-on and off snubber

Vi

+

+

L

L+

+

Dr

T

(a)

+

Df

Vi

Df

Ds

Cs

L

Ds

0

T

Co

Vi

+

0

Dr

Vo

L Ls

Ls

Cs

Ds Df

+

Dr

T

Vi

Vi

+

+

boost

T

0

T

Cs

0

Dr

Vo

Cs

0

Df

T

0

ℓ

L

Cs

Vi

Cs

Vi

+

+

Df

Vo

Do

Ds

Vi

Cs

Ds

Vi

T

Turn-off snubber +

Do

Vo

Co

+ L

0

ℓ

Co

Do

Ls

Vo

T

+

Dr

Cs

ℓ

Do

Ds

Vi Vo

Cs

L

Ds

Co

+

ℓ

Vi

Cs

Ls

L

Dr T

ℓ

Df

+

+

Dr

Ls

Vi Dr

+

T L

L

Vo

+ L Vi

+

Ds

Cs

(l)

Figure 9.31. Passive energy recovery for inductive turn-on snubber: (a)-(d) a boost converter; (e)-(h) a buck/forward converter; and (i)-(l) a buck-boost converter.

Cs

Do

Dr Co

+

Df

Vo

ℓ L

Ds

T

Dr

ℓ

Df

Vi

0

Co

L

L T

Dr Do

+ Vi

L

Cs

T

Df

+ Vo

C

L

Ds

L

Cs

T

0 Ds

+ Vi

0

+ Vi Cs

0

buck/boost

Do

+ Vo

Ds

+

Df

Dr Co

L

Do

(e) Turn-off snubber

Df

Vo

Do

+

Dr Co

(f)

+ Vo +

Do

L

C

Vi T

Turn-on and off snubber 0

Vo

+

L

L

Ds

+

Df

Dr

Vi

Ds T

Cs 0

Figure 9.32. Passive energy recovery circuits for the capacitive turn-off snubber and both turn-on and turn-off snubber circuits, for the different types of switched mode converters.

Chapter 10

Series and Parallel Device Operation and Protection

340

V1 Ileakage

10 Device Series and Parallel Operation, Protection, and Interference

V2

Figure 10.1. Collector (transistor) or anode (thyristor) forward blocking I-V characteristics showing voltage sharing imbalance for two devices in series.

∨

Ib

This chapter considers various areas of power device application that are often overlooked, or at best, underestimated. Such areas include parallel and series device utilisation, over-current and overvoltage protection, radio frequency interference (rfi) noise, filtering, and interactive noise effects.

VD a ∧

Po

Ib

10.1

Parallel and series connection and operation of power semiconductor devices

The power-handling capabilities of power semiconductor devices are generally limited by device area utilisation, encapsulation, and cooling efficiency. Many high-power applications exist where a single device is inadequate and, in order to increase power capability, devices are paralleled to increase current capability or series-connected to increase voltage ratings. Extensive series connection of devices is utilised in HVDC transmission thyristor and IGBT modules while extensive paralleling of IGBTs is common in inverter applications. Devices are also series connected in multilevel converters. When devices are connected in series for high-voltage operation, both steady-state and transient voltages must be shared equally by each individual series device. If power devices are connected in parallel to obtain higher current capability, the current sharing during both switching and conduction is achieved either by matching appropriate device electrical and thermal characteristics or by using external forced sharing techniques. 10.1.1 Series semiconductor device operation Owing to variations in blocking currents, junction capacitances, delay times, on-state voltage drops, and reverse recovery for individual power devices, external voltage equalisation networks and special gate circuits are required if devices are to be reliably connected and operated in series (or parallel).

∧

Ib I2 Figure 10.2. Series IGBT string with resistive shunting for sustaining voltage equalisation in the off-state.

From figure 10.2, Kirchhoff’s current law at node ‘a’, gives ∧

∨

∆I = I b − I b

= I1 − I 2 where I1 > I2. The voltage across cell D1 is VD = I1 R

(A) (A) (V)

(10.1) (10.2) (10.3)

10.1.1i - Steady-state voltage sharing Figure 10.1 shows the forward off-state voltage-current characteristics of two power switching devices, such as SCRs or IGBTs. Both series devices conduct the same off-state leakage current but, as shown, each supports a different voltage. The total voltage blocked is V1 + V2 which can be significantly less than the sum of the individual voltage capabilities. Forced voltage sharing can be achieved by connecting a resistor of suitable value in parallel with each series device as shown in figure 10.2. These equal value sharing resistors will consume power and it is therefore desirable to use as large resistance as possible. For worst case analysis consider n cells in series, where all the cells pass the maximum leakage current except cell D1 which has the lowest leakage. Cell D1 will support a larger blocking voltage than the remaining n - 1 which share voltage equally. Let VD be the maximum blocking voltage for any cell which in the worst case analysis is supported by ∨ ∧ D1. If the range of maximum rated leakage or blocking currents is from I b to I b then the maximum ∨ ∧ imbalance occurs when member D1 has a leakage current of I b whilst all the remainder conduct I b .

BWW

By symmetry and Kirchhoff’s voltage law, the total string voltage to be supported, Vs, is given by Vs = (n - 1) I 2 R + VD (V) (10.4) Eliminating ∆I, I1, and I2 from equations (10.1) to (10.4) yields nVD − Vs l≤ R (10.5) ( ohms ) ∧ ∨ n − ( 1)  I b − I b    for n ≥ 2. Generally only the maximum leakage current at rated voltage and maximum junction temperature is ∨ specified. By assuming I b = 0, a conservative value of the maximum allowable resistance is obtained, namely l ≤ nVD − Vs = n (1 − k s )VD R (10.6) ( ohms ) ∧ ∧ ( n − 1) I b ( n − 1) I b

Power Electronics

341

The extent to which nVD is greater than Vs, is termed the voltage sharing factor, namely V (10.7) ks = s ≤1 nVD As the number of devices is minimized the sharing factor approaches one, but equation (10.5) shows that undesirably the resistance for sharing decreases, hence losses increase. The power dissipation of the resistor experiencing the highest voltage is given by l =V2 / R l P (W) (10.8) d D If resistors of ± l00a per cent resistance tolerance are used, the worst case occurs when cell D1 has a parallel resistance at the upper tolerance while all the other devices have parallel resistance at the lower limit. After using VD = (1+a)I1R and Vs = (n-1)×(1-a)I2R + VD for equations (10.3) and (10.4), the maximum resistance is given by l ≤ n (1 - a ) VD - (1 + a ) Vs R (ohms) (10.9) ∧ ( n - 1) (1 − a 2 ) I b for n ≥ 2. The maximum loss in a resistor is l =V2 / R l (1 - a ) P (10.10) D D If the dc supply toleration is incorporated, then Vs in equations (10.6) and (10.9) is replaced by (1+b)×Vs where +100b is the supply percentage upper tolerance. This leads to a decreased resistance requirement, hence increased resistor power losses. l ≤ n (1 − a ) VD - (1 + a )(1 + b ) Vs R (ohms) (10.11) ∧ ( n - 1) (1 − a 2 ) I b The effects and importance of just a few per cent resistance or supply voltage tolerance on the maximum value for the sharing resistors and their power losses, are illustrated by example 10.1.

Example 10.1: Series device connection – static voltage balancing Ten, 200 V reverse-blocking, ultra fast 35 ns reverse recovery diodes are to be employed in series in a 1500 V dc peak, string voltage application. If the maximum device reverse leakage current is 10 mA (at maximum junction temperature) calculate the voltage sharing factor, and for worst case conditions, the maximum value of sharing resistance and power dissipation. i. ii.

If 10 per cent tolerance resistors are employed, what is the maximum sharing resistance and its associated power rating? If a further allowance for supply voltage tolerance of ±5% is incorporated, what is the maximum sharing resistance and its associated power rating?

Solution ∧

When n = 10, VD = 200 V dc, Vs = 1500 V dc, and I b = 10mA, the voltage sharing factor is k s = 1500V/10×200V = 0.75. Equation (10.6) yields the maximum allowable sharing resistance l ≤ nVD − Vs = 10×200V - 1500V = 5.55kΩ R ∧ ( n − 1) I b (10 - 1) ×10mA The nearest (lower) preferred value, 4.7kΩ, would be used. Maximum resistor power losses occur when the diodes are continuously blocking. The maximum individual supporting voltage appears across the diode which conducts the least leakage current. Under worst case conditions this diode therefore supports voltage VD, hence maximum power loss lD is P l = V2 /R l P D D = 200V 2 /4700Ω = 8.5 W Since the worse device, (in terms of sharing has lowest leakage current), is randomly located in the string, each 4.7kΩ resistor must be capable of dissipating 8.5W.

The maximum 1500V dc supply leakage current is 42.5mA (10mA+1500V/10×4.7kΩ) giving 63.8W total losses (1500V×42.5mA), of which 15W (10mA×1500V) is lost in the diodes.


Chapter 10

342

i. If 10% resistance tolerance is incorporated, equation (10.9) is employed with a = +0.1, that is l ≤ n (1 - a ) VD - (1 + a ) Vs R ∧ ( n - 1) (1 − a 2 ) I b l ≤ 10 × (10 - 0.1) × 200V - (1 + 0.1) × 1500V R (10 - 1) × (1 - 0.12 ) × 10mA

= 2.13 kΩ The nearest (lower) preferred value is 1.8kΩ, which is much lower resistance (higher losses) than if closely matched resistors were to be used. Worst case resistor power dissipation is l =V2 / R l (1 - a ) P D

D

= 200V 2 /1800Ω × (1 - 0.1) = 27.7 W The maximum total module losses are 165W (1500V×103mA) arising from 103mA (10mA + 1500V/1.8kΩ×(1- 0.1)) of leakage current.

ii. If the device with the lowest leakage is associated with the worse case resistance (upper tolerance band limit), and simultaneously the supply is at its upper tolerance limit, then worse case resistance is given by equation (10.11), that is l ≤ n (1 − a ) VD - (1 + a )(1 + b ) Vs R ∧ (n - 1) (1 − a 2 ) I b =

10 × (1 - 0.1) × 200V - (1 + 0.1) × (1 + 0.05 ) × 1500V (10 - 1) × (1 - 0.12 ) × 10mA

= 758Ω

Each resistor (preferred value 680Ω) needs to be rated in excess of 200V 2 /680Ω × (1 - 0.1) = 68.6 W ♣

When resistance tolerances are considered, sharing resistors of lower value must be used and the wider the tolerance, the lower will be the resistance and the higher the power losses. A number of solutions exist for reducing power losses and economic considerations dictate the acceptable trade-off level. Matched semiconductor devices would allow a minimum number of string devices (voltage sharing factor ks → 1) or, for a given string device number, a maximum value of sharing resistance (lowest losses). But matching is complicated by the fact that semiconductor leakage current varies significantly with temperature. Alternatively, by increasing the string device number (decreasing the sharing factor ks) the sharing resistance is increased, thereby decreasing losses. By increasing the string device number from 10 (ks = ¾) to 11 (ks = 0.68) in example 10.1, the sharing resistance requirement increases from 4.7kΩ to 6.8kΩ and resistor losses are reduced from a total of 50.8 W to 31 W. Another method of minimising sharing resistance losses is to minimise resistance tolerances. A tolerance reduction from 10 per cent to 5 per cent in example 10.1 increases the sharing resistance requirements from 1.8kΩ to 3.9kΩ, while total power losses are reduced from 140 W to 64 W. These worse case losses assume a near 100% off-state duty cycle. 10.1.1ii - Transient voltage sharing During steady-state or at very low frequencies, sharing resistors as shown in figure 10.2 are sufficient to prevent individual device overvoltage. Mismatching of turn-on delay times of thyristors and transistors can be minimised by supplying high enough turn-on drive with very fast rise times. A higher initial di/dt is then allowable. Before a conducting string of diodes or thyristors can reverse-block, reverse recovery charge must flow. Those elements with least recovery charge requirements recover first and support the reverse bias. The un-recovered devices recover slowly, since recovery now occurs as a result of the low leakage current though the recovered devices, and natural recombination. The transient reverse-blocking voltage can be shared more equally by placing capacitance across each string element as shown in figure 10.3. The capacitor action is to provide a transient current path bypassing a recovered device to allow a slower device to recover and to support volts. In the case of thyristors, low value resistance is connected in series with each capacitor to avoid high capacitor discharge through the thyristors at turn-on. Figure 10.4 shows the I-V characteristics of two unmatched thyristors or diodes during reverse recovery.

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∧

ℓℓ

( n − 1) Q (1 − a )( nV − V )

∨

C≥

∆Q

D

344

∧

=

s

( n − 1) Q n (1 − a )(1 − k ) V s

(F)

(10.17)

D

where -100a is the capacitor negative percentage tolerance and n ≥ 2. Voltage sharing resistors help minimise capacitor static voltage variation due to capacitance variations. If the supply tolerance is incorporated, then Vs in equations (10.16) and (10.17) are replaced by (1+b)×Vs where +100b is the supply percentage upper tolerance. This leads to an increased capacitance requirement, hence increased energy losses, ½CVD2 . ∧

∨

C≥

( n − 1) Q (1 − a ) ( nV − (1 + b )V ) D

(10.18)

(F)

s

Figure 10.3. A series diode string with shunting capacitance for transient reverse blocking voltage sharing.

Example 10.2: Series device connection – dynamic voltage balancing The string of ten, 200 V diodes in worked example 10.1 is to incorporate capacitive reverse recovery transient sharing. Using the data in chapter 5, figure 5.9, specify a suitable sharing capacitance based on zero capacitance and supply tolerances (a = b = 0), ± 10 per cent capacitance tolerances (a = 0.1, b = 0), ± 5 per cent supply tolerance (a = 0, b = 0.05), then both tolerances (a = 0.1, b = 0.05). Estimate in each case the capacitor energy loss at capacitor discharge. Solution Figure 5.9 shows that worst case reverse recovery conditions occur at maximum junction ∧ temperature, di/dt, and IF, and a value of Q = 6µC is appropriate. The minimum possible sharing capacitance occurs when the capacitance and dc rail voltage are tightly specified. From equation (10.16) ∧

Figure 10.4. Reverse recovery current and voltage for two mismatched series connected diodes.

The worst∨ case assumptions for the analysis of figure 10.3 are that element D1 has minimum stored ∧ charged Q while all other devices have the maximum requirement, Q . The charge difference is ∧

∨

∆Q = Q − Q (C) (10.12) The total string dc voltage Vs, comprises the voltage across the fast-recovery device VD plus the sum of each of the voltages across the slow n - 1 devices, Vslow. That is Vs = VD + ( n - 1) Vslow (V) The voltage across each slow device is given by ∧ Vslow = 1n  Vs − ∆ V  (V)   ∧ ∧ where ∆ V = ∆ Q/ C . Eliminating Vslow from equations (10.13) and (10.14) yields ∨ ( n − 1) ∆Q = ( n − 1) ∆Q C≥ (F) nVD − Vs n (1 − k s )VD

(10.13)

∧

∨

( n − 1) Q

(10.14)

(10.15)

nVD − Vs

∧

=

( n − 1) Q n (1 − k ) V s

( n − 1) Q

∧

∨

C≥

( n − 1) Q (1 − a )( nV − V ) D

=

s

(10 - 1) × 6µC (1 - 0.1) × (10×200V-1500V )

A further increase in capacitance requirements results if the upper tolerance dc rail voltage is used. From equation (10.18) ∧

∨

( n − 1) Q (1 − a ) ( nV − (1 + b )V ) (10 - 1) × 6µC = (1 - 0.1) × (10×200V - (1+0.05) ×1500V ) D

s

(10.16)

D

Voltage sharing circuit design is complicated if the effects of reverse steady-state leakage current in ac thyristor blocking are taken into account. Supply and sharing capacitance tolerances significantly affect the minimum capacitance requirement. Worst case assumptions for capacitance tolerances involve the case when the fastest recovering diode is in parallel with capacitance at its lower tolerance limit while all the other sharing capacitances are at their upper tolerance limit. Assuming the minimum reverse recovery charge is zero, then the minimum sharing capacitance requirement is

= 0.14µF @ 200Vdc

In each tolerance case the next larger preferred capacitance value should be used, namely, 120nF, 120nF, and 150nF respectively, all rated at 200V dc. The total series capacitance, using the upper tolerance limit is ∨

CT =

(1 + a ) C n

The stored energy with a 1500V dc rail in the 10 series connect 120nF capacitors, and subsequently loss when the string voltages reduces to zero at diode forward bias, is therefore ∨

(F)

= 0.12µF @ 200Vdc

C≥

This equation shows that as the number of devices is minimized, the sharing factor, ks, which is in the denominator of equation (10.15), tends to one and the capacitance requirement undesirably increases. Manufacturers do not specify the minimum reverse recovery charge but specify the maximum reverse recovery charge for a ∨given initial forward current, reverse recovery di/dt, and temperature. For worst case design, assume Q = 0, thus

C≥

(10-1) ×6µC = 108nF @ 200Vdc = nVD − Vs 10×200V - 1500V The sharing capacitance requirement with 10% tolerance capacitors, is given by equation (10.17) ∨

C≥

2 (1 + a ) C 2 2 WT = ½CT Vls = ½ Vs (1 + b ) n (1 + 0.1) ×120nF 2 =½ ×1500V 2 × (1 + 0.05 ) = 16.4mJ 10 The energy stored in the 10 series connect 150nF capacitors, and subsequently loss when the string voltage reduces to zero at diode forward bias, is (1 + 0.1) ×150nF WT =½ × ×1500V 2 × (1 + 0.05) 2 = 20.5mJ 10 ♣

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When capacitive sharing is used with switching devices, at turn-on the transient sharing capacitor discharges into the switching device. The discharge current magnitude is controlled by the turn-on voltage fall characteristics. If a linear voltage fall at turn-on is assumed, then the transient sharing capacitor maximum discharge current idis is a constant current pulse for the fall duration, of magnitude V ∆V idis = C D = C D (A) (10.19) ttv ∆t The discharge current can be of the order of hundreds of amperes, incurring initial di/dt values beyond the capabilities of the switching device. In example 10.2 the discharge current for a switch rather than a diode is approximately 150nF×200V/1µs =30A, assuming a 1µs voltage fall time. This 30A may not be insignificant compared to the switches current rating. But, advantageously, the sharing capacitors do act as turn-off snubbers, reducing switch turn-off stressing. In the case of the thyristor, the addition of low-valued, low inductance, resistance in series with the transient capacitor can control the capacitor discharge current, yet not significantly affect the transient sharing properties. The resultant R-C discharge current can provide thyristor latching current while still offering transient recovery sharing, dv/dt, and voltage spike suppression. Thyristor snubber operation and design are considered in chapter 8.1.2. Figure 10.5 shows the complete steady-state and transient-sharing networks used for diodes, thyristors, and transistors. Transient voltage sharing for transistors involves the use of the conventional R-D-C snubber shown in figure 10.5c and considered in chapter 8. The series inductor used with thyristor and transistor strings provides transient turn-on voltage protection. The inductor supports the main voltage while each individual element switches on. Such an inductive turn-on snubber is mandatory for the GCT and the GTO thyristor. No one device is voltage-stressed as a consequence of having a longer turn-on delay time, although gate overdrive at turn-on minimises delay variations.


346

10.1.2i - Matched devices Figure 10.6 shows the static I-V on-state characteristics of two SCR’s. If these two devices are connected in parallel, for the same on-state voltage, the resultant current flow is I1 + I2 where I1 and I2 can be very different in value. The total current rating of the pair is not the sum of the maximum current rating for each but rather a value which can be just larger than the rating of one device alone. The percentage parallel derating pd for n parallel connected devices is defined as  I  pd =  1 − T  × 100 = (1- k p ) × 100 per cent (10.20)  nI m  where IT = total current through the parallel arrangement Im = maximum allowable single device current rating n = number of parallel devices kp = current parallel sharing factor = IT /nIm ≤ 1 Parallel connection of IGBT die within a module is made possible by using die from the same wafer/batch. On-state voltage matching for single large area wafers is expensive and complicated by the high temperature dependence of both static and dynamic electrical device characteristics. Derating does not account for effects such as layout and electrical and thermal impedance imbalance. The amount of derating is traded off against the extra cost involved in selecting devices with closer (matched) static characteristics.

Im = 100A

ℓℓ

R

R

R

R

Figure 10.6. Forward conduction characteristics of two unmatched devices.

Figure 10.5. Transient and steady-state voltage sharing circuits for series connected: (a) diodes; (b) thyristors; and (c) igbt transistors.

10.1.2 Parallel semiconductor device operation It is common practice to parallel power devices in order to achieve higher current ratings or lower conducting voltages than are attainable with a single device. Although devices in parallel complicate layout and interconnections, better cooling distribution is obtained. Also, built-in redundancy can give improved equipment reliability. A cost saving may arise with extensive parallel connection of smaller, cheaper, high production volume devices. The main design consideration for parallel device operation is that all devices share both the steadystate and transient currents. Any bipolar device carrying a disproportionately high current will heat up and conduct more current, eventually leading to thermal runaway as considered in section 4.1. The problem of current sharing is less severe with diodes because diode characteristics are more uniform (because of their simpler structure and manufacturing) than those of thyristors and transistors. Two basic sharing solutions exist • •

matched devices external forced current sharing.

10.1.2ii - External forced current sharing Forced current sharing is applicable to both steady-state and transient conditions. For a current derating of less than 5 per cent it is usually cheaper to use forced sharing techniques rather than matched devices. Figure 10.6 shows the maximum variation of I-V characteristics in devices of the same type. When parallel connected the maximum current is restricted to Im+I2, (= 100A+70A = 170A at 1.6V). The maximum current rating for each device is Im, (100A); hence with suitable forced sharing a combination in excess of Im + I2 (170A) should be possible. The resistive network in figure 10.7 is used for forced current sharing and in example 10.3 it is required that Im, 100A, flows through D1 and (1-2×pd)×Im > I2, (90A) flows through D2, for a pd (5%) overall derating. From Kirchhoff’s voltage law in figure 10.7 V1 + V3 = V2 + V4 (10.21) VD1 + I m R = VD2 + ( IT − I m ) R From equation (10.20), rearranged for two devices, n = 2

IT = 2 × (1 − pd ) I m = 2k p I m Substituting for IT in equation (10.21) gives VD − VD1 R= 2 2 pd I m

(ohms)

(10.22)

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For δ = ½ I D1 = δ × I D1 = ½ × 100 A = 50 A

δ × I D1 =

I D 1 rm s =

I D2 1 rm s − I D 1 =

2

(10.23)

which after substituting for IT from equation (10.20), for maximum device voltage variation, gives R=

VD − VD ( n − 1) Im n × pd ∨

(ohms)

(10.24)

Although steady-state sharing is effective, sharing resistor losses can be high. The total resistor losses in general terms for n parallel connected devices and a conduction duty cycle δ, are given by 2   n   × pd   I 2 R (W) (10.25) Pt = δ 1 + 1 − − 1 n     2 Since the devices are random in characteristics, each resistor must have a power rating of I m R . m

Example 10.3: Resistive parallel current sharing – static current balancing For the two diodes shown in figure 10.6, with I = 100A , what derating results when they are parallel connected, without any external sharing circuits? The maximum current rating for each device is Im, 100A; hence with suitable forced sharing a 190A combination should be possible. Using the network in figure 10.7 for current sharing, it is required that 100A flows through D1 and 90A through D2. Specify the per cent overall derating, the necessary sharing resistors, their worse case losses and diode average, rms, and ac currents at a 50% duty cycle and worse case.

I D2 2 rm s − I D 2 =

PD 1 = I D 1 V D 1 = 5 0 A × 1 .6 V = 8 0 W

PR 2 = I D 2 V D 2 = 4 5 A × 1 .7 V = 7 6 .5 W

δ × I D1 = I

2 D 1 rm s

PR 1 = I

2 D 1 rm s

PD 1 = I

D1

− I D1 =

100 − 100 2

2

I D 2 rm s =

= 0A

I D 2 ac =

R 1 = 1 0 0 × 0 .0 1m Ω = 1 0 0 W

PR 2 = I

2

V D 1 = 1 0 0 A × 1 .6 V = 1 6 0 W

P to ta l = P R + P D = (1 0 0 W + 8 1 W

+ 1 5 6 .5 W = 2 4 7 W

I D2 = δ × I D2 = 1× 90A = 90A

1 × 100A = 100A 2

) = 9 0 .5 W

) + (1 6 0 W

δ × ID2 = I

2 D 2 rm s

2 D 2 rm s

1 × 90A = 90A 2

− I D2 =

902 − 902 = 0A

R 2 = 9 0 × 0 .0 1m Ω = 8 1 W 2

PR 2 = I D 2 V D 2 = 9 0 A × 1 .7 V = 1 5 3 W + 153W

) = 181W

+ 313W = 494W

The general form in equation (10.25) gives the same total resistor losses for each conduction duty cycle case, namely for δ = ½: 50W+40.5W = 90.5W and for δ → 1: 100W+81W = 181W. ♣ A more efficient method of current sharing is to use coupled reactors as shown in figure 10.8. In these feedback arrangements, in figure 10.8a, if the current in D1 tends to increase above that through D2, the voltage across L1 increases to oppose current flow through D1. Simultaneously a negative voltage is induced across L2 thereby increasing the voltage across D2 thus increasing its current. This technique is most effective in ac circuits where the core is more readily designed to reset, not saturate. IF

X to X

Np Ns

Np Ns

Np Ns X to X

T1

T2

D2

D1

Solution The derating for the parallel situation depicted in figure 10.6, without external sharing, is 170A  100A+70A  pd =  1 ×100 = 15 per cent (k p = =0.85) 2×100A  2 × 100A  With forced resistive sharing, the objective derating is reduced from 15% to 190A  100A+90A  pd =  1 ×100 = 5 per cent (k p = = 0.95) 2×100A  2 × 100A  From figure 10.6

6 3 .6 2 − 4 5 2 = 4 5 A

PR 2 = I D2 2 rm s R 2 = 6 3 .6 2 × 0 .0 1m Ω = 4 0 .5 W

I D 1ac =

For n devices connected in parallel, equation (10.21) becomes (I − I ) VD + I m R = VD + T m R n −1

½ × 9 0 A = 6 3 .6 A 2

I D 2 ac =

PR 1 = I D2 1 rm s R 1 = 7 0 .7 2 × 0 .0 1m Ω = 5 0 W

I D 1 rm s =

Figure 10.7. Forced current sharing network for parallel connected devices.

∧

7 0 .7 2 − 5 0 2 = 5 0 A

For worse case losses, δ →1 I D1 = δ × I D1 = 1 × 1 0 0 A = 1 0 0 A

IT

δ × ID2 =

I D 2 rm s =

Pto ta l = PR + PD = ( 5 0 W + 4 0 .5 W ) + ( 8 0 W + 7 6 .5 W

Im

1

I D 2 = δ × I D 2 = ½ × 90A = 45A

½ × 1 0 0 A = 7 0 .7 A 2

I D 1 ac =

348

(c)

T3

D3

I n τ2 I F = F + × ∆VF n n − 1 2TLM

I τ2 I F = F + 0.016n 2 × ∆VF n 2TLM for n > 6

1.6V + 100A×R = 1.7V + 90A×R

that is R = 10 milliohm Equation (10.22), being based on the same procedure, gives the same result. The cell voltage drop is increased to 1.6V+100A×0.01Ω = 1.7V+90A×0.01Ω = 2.6V . Thus, for an on-state duty cycle δ, the total losses are δ×2.6V×190A = δ×494W.

Figure 10.8. External forced current sharing networks using cross-coupled reactors: (a) for two devices; and (b) and (c) for many devices.

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Equalising reactor arrangements are possible for any number of devices in parallel, as shown in figures 10.8b and c, but size and cost become limiting constraints. The technique is applicable to steady-state and transient sharing. At high current densities, the forward I-V characteristic of diodes and thyristors (and some IGBTs) has a positive temperature dependence which provides feedback aiding sharing. The mean current in the device with the highest current, therefore lowest voltage, of n parallel connected devices in figure 10.8c (with one coupled circuit in series with each device), is given by I I I n −1 τ 2 n −1 δ2 × ∆VF = F + × ∆VF I F = F + ∆I F = F + (10.26) 2TLM 2 f s LM n n n n n where ∆VF is the maximum on-state voltage drop difference LM is the self-inductance (magnetising inductance) of the coupled inductor Τ is the cycle period, 1/fs and τ is the conduction period (τ < T) (a) current sharing analysis for two devices:– ro = 0 Consider two thyristors (n = 2) connected in parallel as show in figure 10.9. The coupled circuit magnetising current is modelled with the magnetising inductor LM. The transformer turns ratio is 1:1, hence the winding voltages and currents are equal, taking into account the relative winding flux orientation shown by the dots. Commutation inductance overlap is ignored. From Kirchhoff’s voltage law vT 1 + v1 = vT 2 − v1 (10.27) That is v1 = ½ × ( vT 1 - vT 2 ) = ½ × ∆v (10.28) From Kirchhoff’s current law I M = i1 − i2

(10.29)

dI M dt

(10.30)

From Faraday’s equation v1 = LM

which after integrating both sides gives 1 τ 1 IM = v1 dt = ½ ∆VFτ (10.31) LM ∫ 0 LM As a condition it is assumed that the voltage difference ∆v does not decrease as the operating point moves along the I-V characteristics. That is, both devices are modelled by v = vo + i × ro, where the linear resistance ro, is zero, each have different zero current voltages that is different vo, ∆vo = ∆VF. Actually D1 moves further up the I-V characteristic with time as it conducts more current while D2 moves towards the origin, as shown in figure 10.9b. i

IT

IT

IM = i 1 - i2 i2

+ v1

i2

-

LM

magnetising inductance

IT1

t>0

+

i1

t=0

IM

VT1

VT2

-

-

t

T2 IF

t>0

i2 VF

IT (a)

∆VF (b)

iF 1/ro ∆vo

vF

Figure 10.9. External forced current sharing network using cross-coupled reactors: (a) circuit (including magnetising inductance LM) for two devices and (b) I-V operating points.

(b) current sharing analysis for two devices:– ro ≠ 0 If static resistance is included into the device model for current sharing analysis, then equation (10.30), assuming both devices have the equal resistance, becomes ∆v o = LM

dI M + 2I M ro dt

(10.32)

350

The solution to this differential equation gives the magnetizing current as 2r −t o  ∆v o  L IM = 1 − e M  2ro  

(10.33)

The maximum magnetizing current increases from zero and reaches a maximum at the end of the current conduction period τ. Re-arranging equation (10.33) gives the magnetizing inductance as 2ro τ LM = (10.34)   ∆v o An   ∆v o − I M 2ro 

(c) current sharing analysis for n devices:– ro = 0 When more than two devices are parallel connected, sharing can be enforced with the multiple transformer technique shown in figure 10.8c, where the n transformer secondary windings are series connected. Each transformer has a turns ratio of η = Np:Ns, and the magnetising inductance is assumed to be on the primary side of each transformer. The semiconductor devices are assumed to have a constant on-state voltage vo. The total current is IT, and zero commutation inductance is assumed. Using Kirchhoff’s voltage law on the primary side: Since the secondary voltages sum to zero v s 1 + v s 2 + v s 3 + ... + v sn = 0 then the transformer primary voltages also sum to zero

v p 1 + v p 2 + v p 3 + ... + v pn =

(10.35)

Ns (v + v s 2 + v s 3 + ... + v sn ) = 0 N p s1

Since the legs are parallel connected VT 1 + v p 1 = VT 2 + v p 2 = ..... = VTn + v pn

(10.36)

∨

(10.37)

For worst case analysis, let one device (n = 1) operate at minimum on-state voltage, V T , while the other n - 1 devices have a maximum on-state voltage VlT , therefore potentially conduct less current than the device operating at minimum voltage. ∨ V + v = Vl + v = ..... = Vl + v (10.38) T

T

p1

p

T

p

These equations yield the following primary voltages ∨ ∨ n −1 l 1 l   v p1 = V −V T  and v p 2 = v p 3 ... = v pn = − V T −V T  n  T n   

(10.39)

Using Kirchhoff’s current law on the primary side: I T = I T 1 + I T 2 + ... + I TN (10.40) But a thyristor current, which is the transformer primary current, can be expressed in terms of the transformer secondary current plus the parallel magnetising current on the primary side. That is N 1 (10.41) I T i = i p i + iM i = s is + iM i = is + iM i

Np

IM

+

+ T1

Im ½IT

IT2

v1

-


Chapter 10

η

where, because the secondary windings are series connected, the secondary current is the same for each transformer. The transformer magnetising current iMi is the same for transformers i = 2 to n, iM. Thus the total current n n 1  IT = ∑ IT i = ∑  i s + i m i  i =1 i =1  η  (10.42) 1 I T = n i s + i m 1 + ( n − 1) i m

η

Using Kirchhoff’s voltage law on the secondary side: Since the transformers are identical, each has the same value of magnetising inductance (selfinductance) LM. Because the secondary windings are series connected the sum of the secondary voltages, hence sum of primary voltages, are zero.

Power Electronics

351

v p1

v p2

+

+ v p 3 + ...

+v pn

Chapter 10

= 0

d iM n d iM1 d iM 2 = LM + LM + ...... + LM =0 dt dt dt d iM   d iM1 = LM  + ( n − 1) =0 dt   dt d i + ( n − 1) i M  = 0 = LM dt  M 1

(10.43)

This component inside the square bracket must be a constant. i M 1 + ( n − 1) i M = c

(10.44)

Substituting the constant c into equation (10.42) gives the secondary current as 1 i s = η (IT − c )

(10.45)

n

LM

From equation (10.39), when t = τ, the maximum magnetising current, in terms of the device voltage extremes, is ∨ 1 n −1 l  ∆i M 1 (t = τ ) = ∆iM 1 = × (10.47) V −V T  × τ LM n  T  Re-arranging gives the necessary minimum transformer self-inductance with respect to the primary side. 1

∆iM 1

×

∨ n −1 l 1 n −1  × ∆V F × τ V −V T  × τ = × n  T n  ∆i M 1

(10.48)

The maximum magnetising current ∆iM 1 can be expressed in terms of devices current rating Im and device percentage derating, pd, or device utilisation, kp =1 - pd. If the device current rating is Im, then n devices in parallel can theoretically conduct n×Im. When derated by pd to kp, the total current is kp×nIm where each device initially conducts kp×Im. The current in the worst case device increases from kpIm to Im ( ∆iM 1 = (1 − k p ) I m = pd × I m ) in the maximum period the device conducts, τ. (10.49) I = k I + ∆i M = k I + (1 − k ) I = I T

p

m

p

m

p

m

m

n×Im kpnIm

Derated current

pd×nIm

Device rating

Im

Im

IT1

pd×Im

kp Im Im

kp Im

 nk p − 1    n −1 

Im 

1 − kp

n −1

t o

The current in each of the remaining n -1 devices decreases from kp Im by (1-kp) Im /n -1 to ∨ 1 − kp  nk p − 1  (10.50) I T = kpIm − Im = Im   n −1  n −1  such that the necessary total current is maintained: ∨  nk − 1  IT + ( n − 1) I T = I m + ( n − 1) I m  p  = nk p I m  n −1  These various current components are shown in figure 10.10. By assuming a current quadratic dependence on time, equations similar to equations (10.26) can be obtained.

Two thyristors with the same forward conduction characteristics as the diodes in figure 10.6 are parallel connected using the coupled circuit arrangement in figure 10.8a. The maximum current rating for each device is Im, 100A; hence with suitable forced sharing a 190A combination should be possible. Using the network in figure 10.9a for current sharing, it is required that no more than rated current flow through the lower conducting voltage device, D1. Specify the per cent overall derating and the necessary sharing transformer properties assuming a half-wave, 180º conduction, phase-controlled, 50Hz, highly inductive load application. What are the transformer core reset requirements? Estimate inductance requirements if the thyristors have a static on-state resistance of 1mΩ. Solution As in example 10.3, the derating for the parallel situation depicted in figure 10.6, without external sharing, is 170A   pd =  1 ×100 = 15 per cent (k p = 0.85) 2×100A   With forced transformer sharing, the objective derating is reduced from 15% to 190A   pd = 1 ×100 = 5 per cent (k p = 0.95) 2×100A   When the two thyristors are turned on, the magnetizing current is assumed zero and transformer action will force each device to conduct 95A, giving 190A in total. From figure 10.6, the voltage difference between the thyristors, ∆VF is about 0.1V, thus the transformer winding voltages will be 0.05V each, with polarities as shown in figure 10.9a. In time the magnetizing current increases and the current in T1 increases above 95A due to the increasing magnetizing current, while the current in T2 decreases below 95A, such that the total load current is maintained at 190A.

The worse case conduction period in this ac application, giving maximum magnetising current, is for 180º conduction, that is, 10ms. Thus it is required that T1 current rises to 100A and T2 current falls to 90A after τ =10ms, that is, the magnetising current is 100A - 90A = 10A. Substitution into equation (10.31) gives 1 10ms 1 LM = ½ ∆vdt = ½ × × 0.1V×10ms = 50µH 10A IM ∫ 0 where it is assuming that the voltage differential ∆VF between the two devices is constant during the conduction period. In fact figure 10.9b shows that the voltage difference decreases, so assuming a constant value gives an under-estimate of requirements.

I theoretical current limit

352

Example 10.4: Transformer current sharing – static and dynamic current balancing

In conjunction with Faraday’s Equation, the magnetising current is a linear function of time, starting from zero. Applying these conditions to the worst case device, T1, then as the magnetising current in transformer Tr1 increases and the associated thyristor current IT1 increases, from equation (10.44), the opposing magnetising current in the other transformers reduces the associated device principal current. At the maximum on-time, the current in device T1 should not exceed its permitted rated limit, Im. 1 ∆i M 1 (t ) = × v p 1t (10.46)

LM =


τ

Figure 10.10. External forced current sharing network using series connected secondary windings.

The core volt-µs during conduction is 0.05V×10ms = 500 V-µs. That is, during core reset the reverse voltage time integral must be at least 500 V-µs to ensure the core flux is reset, (magnetising current reduced to zero). Using equation (10.34), with ro = 1mΩ, gives 2ro τ 2 × 1mΩ × 10ms = = 90µH LM = 0.1V     ∆v o An  A n  0.1V − 10A × 2 × 1mΩ     ∆v o − I M 2ro  The inductance, 50µH, given by equation (10.31) when neglecting model resistance, under-estimates requirements. ♣

Protection overview - over-voltage and over-current

All electrical systems are vulnerable to inference and damage from lightning or other short duration electrical surges or long duration supply system swells. As systems become more electronically complex, they also become more vulnerable to external and internally generated interference. A fault can be caused by a device failure or noise which causes undesired device turn-on. This will cause semiconductor device and equipment failure unless protective measures are utilised. Protection against fault current effects usually involves fuses which clear in time to protect endangered devices, or voltage transient absorption devices which absorb spike energy and clamp the equipment voltage to a safe level. The crowbar fault protection technique can be employed to divert the fault from sensitive components to the crowbar which is a robust circuit. The crowbar clamps the sensitive circuit to zero volts and initiates an isolation breaker or fuse action. An electrical surge is a temporary increase in voltage, current or both. The size, waveform, and form of the transient surge which can occur within a system are many and varied. i. Lightning - Although direct strike lightning current can potentially generate transients in the millions of volts and tens of thousands of amps, electronic equipment is rarely exposed to surges of this magnitude. The greatest exposure in power electronics systems is through interconnection and transmission lines. Domestic ac lines can only carry voltages up to 5kV and currents of the order of 1kA. Therefore, for the vast majority of instances where the chance of a lightning strike directly to the equipment is low, 5kV and 1kA is the limit of the direct strike or inductively generated surges. Exposed equipment, such as wind turbines, although suitable earthed, can experience significantly higher electrical surge stresses. ii. Power Induction - Although power induction voltages can be high in voltage and current, they are often limited in duration. These voltages are caused by faults on the power system which couple into the system (usually inductively as a consequence of the surge causing a large fault current). In virtually all modern power transmission systems, these faults are quickly terminated by circuit breaker and re-closer equipment. This can occur in as short as a couple of cycles of power frequency voltage and rarely takes longer than a second. These transients are typically modelled as a 600Vrms waveform lasting up to a second. iii. Power Cross - Alternatively, power cross voltages are low voltage events but the exposure can occur for long durations. They are often caused by maintenance error or cabling faults and can result in moderate currents flowing for a long period of time, for example, in domestic applications, 25A for 15 minutes. They are predominately at mains power supply voltage levels (100 to 220Vrms). iv. Earth Potential Rise (EPR) - EPR can be categorized in two forms: 1. as a result of power system faults and 2. lightning discharges. In normal industry, where fault currents from the power system are limited in magnitude by fuses and circuit breakers, power system EPR is not usually a considerable risk. EPR only becomes a significant risk when power earthing systems are significantly below standard or where high power transmission systems are used such as at power generation and distribution facilities, within the high power industry, and in the vicinity of electrical traction systems (electric rail). Lightning EPR can only result from a direct strike to the building housing the equipment or in its immediate vicinity. Such events are uncommon, unless the installation is particularly vulnerable due to location or extreme height (for example, wind turbine and cellular phone base-station antennae). The equipment exposure as a result of EPR can be high, and at high earth resistance locations, may become a significant portion of the lightning current. Surge protection is the process of protecting electronic systems or equipment from voltages and currents which are outside their safe operating limits. These surge voltages and currents can be generated by short circuits, lightning or faults from a power system and usually enter the electronic system along inter-equipment wiring. The surges may be galvanically coupled into the system as in the case of a direct lightning strike, through an inadvertent connection of the power system to the wiring, or as a result of an earth potential rise. They may be capacitively coupled into the system which may occur when a data system is used in the vicinity of a high voltage power line. They may be inductively coupled into the system as may occur if the wiring is run in parallel with large currents running in a power circuit feeding a high power motor. Such events can result in a wide variety of potential consequences. Electrical surge protection performs several key functions: • it must prevent or minimize damage caused by a surge; • it must ensure that the system returns to a working condition with minimal disruption to service. • under normal conditions the protection must not interfere with any signals or control circuitry, creating challenges for power electronics technologies. • the protection must operate and fail in a safe manner during overstress.


Chapter 10

354

10.2.1 Ideal secondary level protection Power electronic equipment is generally within a system that has primary protection, associated with the ac grid protection, for example. The installed equipment therefore may only require secondary protection. Secondary protection prevents the let-through energy of the primary protector (the energy of the surge which gets past the primary protector) from damaging the load. The peak open circuit voltage of the let-through energy past the primary protector is smaller than the initial external surge. Therefore, a secondary protector can effectively block (series) and or divert (shunt) the reduced surge energy. The requirements for this ideal blocking device are: i. As the device needs to block the let-through energy of the primary protector, it can be a series component (in series with the transmission line), located just after the primary protector. As a series component, the device will react to the current through the device rather than, as with a shunt protector, voltage across the interface. ii. A series device should have a predictable, stable and low trigger current (current at which the device changes between its conductive and non-conductive state) to provide effective protection for sensitive downstream equipment. A shunt device should operate (clamp or foldback) at a level just above the maximum working voltage. iii. It should be fast acting (less than 10ns) to protect equipment from surges which rise at 5kV/µs as with direct lightning strikes or lightning EPR; iv. As a series device it should have low impedance (resistive, capacitive and inductive) so that it does not effect normal circuit operation, while for the same reasons, a shunt device should have a high standby impedance; v. In the blocking mode, a series protector should have high impedance so that it does not dissipate significant energy during long duration surges, while for the same reasons, a shunt device should have a low clamping impedance; vi. It should reset after the surge to reinstate the system and continue to allow normal system operation; vii. Reset to normal after an incident, returning the equipment to pre-event opration; viii. Debatably, after excessive stress, a shunt device should fail-safe open circuit, while a series device should failure short-circuit, so as to enable continued unprotected operation, but system protection is afforded. In addition, for practical and economic reasons it should be small in size and low in cost.

Electrical protection devices fall into two key category, overvoltage (usually shunt connected) and overcurrent (usually series connected). Over-voltage devices divert or shunt surge current produced by an over-voltage (such as lightning), as shown in Figure 10.11, while most over-current devices increase in resistance (possibly becoming open-circuit) to limit the surge current flowing from longer duration surge currents (50/60 Hz power fault), as shown in the parts of figures 10.12 . There are two types of voltage limiting protectors: switching devices (gas discharge tube GDT and thyristor) that crowbar (voltage fold-back) the line, and voltage clamping devices (metal oxide varistor MOV and transient voltage suppressor TVS). The waveforms of figure 10.11 highlight that switching devices result in lower stress levels than clamping devices (shaded area) for protected equipment during their operation. Functionally, all voltage protectors reset after the surge, while current protectors may or may not reset, depending on their operating mechanisms. For example, PTC thermistors are resettable; over-voltage fuses are non-resettable. v

clamping over-voltage protection

source impedance

surge voltage

surge current diversion

Load to be protected

10.2

Power Electronics

over-voltage protection

353

threshold voltage t

v

over-voltage threshold voltage

switching over-voltage protection t Figure 10.11. Two shunt voltage control mechanisms, namely voltage clamping and voltage fold-back by switching action, with source and load voltages shown.

Power Electronics

355

Chapter 10

10.2.2 Overvoltage protection devices Gas Discharge Tubes (GDT) create a quasi short circuit across the line when the internal gas is ionized by an overvoltage, returning to a high impedance state after the surge has ceased. These robust devices have the highest impulse current capability of any technology, and combined with negligible capacitance, make them attractive for the protection of high-speed digital and ac switching converter applications. Thyristor-based devices initially clamp the line voltage, and then switch to a low voltage on-state. After the surge, when the current drops below the holding current, the protector recovers and returns to its original high impedance blocking state. Transient Voltage Suppressor (TVS) or Zener diodes operate by rapidly moving from a high impedance to a non-linear resistance characteristic that clamps surge voltages. TVS diodes provide a fast-acting and controlled clamping voltage, however they have high capacitance and low energy capability which restricts the maximum surge current. Electrostatic discharge (ESD) devices clamping protectors consists of multilayer varistors (MLV) designed to protect equipment against ESD conditions. They have low leakage currents that make the devices transparent under normal operation. ESD transients cause the device to clamp the voltage by reducing its effective resistance and it will reset to a high impedance state after the disturbance. Diode arrays for ESD protection combine thin film on silicon wafer fabrication technology and chip scale packaging. Such devices are used in portable electronics applications where a particular electrical response characteristic is specified for a minimum volume.

interruption

surge

reduction

i

surge current diversion

prospective over-current

356

open. Low current power induction may not break-open the LFR, creating long-term surface temperatures of more than 300°C. To avoid heat damage to adjacent components, the maximum surface temperature can be limited to about 250°C by mounting a series thermal fuse link on the LFR. This capability is exploited in modules incorporating both over-current and over-voltage devices on one ceramic substrate. The incorporation of silicon die and discrete components gives modules with high performance and specific functionality. A concise overview of generally available over-voltage and over-current protection devices is presented in Table 10.1. The following sections will consider each technology in detail. Table 10.1: Overview of over-current and over-voltage protection devices and technologies Device

action

connection

speed

accuracy

current rating

Over-voltage GDT

voltage switching

shunt

fair

fair

very high

Thyristor

voltage switching

shunt

fair

good

high

MOV

voltage clamping

shunt

fair

poor

high

TVS

voltage clamping

shunt

fast

good

low

Polymer PTC thermistor

resettable

series

fair

good

low

Ceramic PTC thermistor

resettable

series

slow

good

low

non-resettable

series

very slow

Fair

medium/high

Heat coil

non-resettable

shunt or series

very slow

Poor

low

Thermal switch, LFR

non-resettable

series

very slow

poor

high

Over-current

Fuse

(c) i

reduction

t

t


surge

(b)

interruption

overcurrent protection

source impedance

surge current

(a) i



surge current

source impedance


surge



source impedance


diversion

10.3

t


Figure 10.12. Three current limiting mechanisms: (a) current flow interruption, (b) current reduction, and (c) current diversion.

10.2.3 Over-current protection devices Polymer Positive Temperature Coefficient (PPTC) Thermistor resettable fuses are used in circuit current protection applications. Under high-current fault conditions, its resistance increases by many orders of magnitude and remains in a tripped state, continuing to provide continuous circuit protection until the fault is removed. Then after the power is cycled, the device returns to its normal low-resistance, low-loss state. Traditional fuses are constructed from a metal element encapsulated in a ceramic housing. The fuse element heats up at the rate related to I2R. When the metal element temperature exceeds its melting point, it vaporizes and opens the circuit. The low resistance and losses of fuses are attractive for ac applications. Line Protection Modules (LPM) are based on a basic form of current protection; the Line Feed Resistor (LFR), normally fabricated as a thick-film resistor on a ceramic substrate. LPMs can withstand highvoltage impulses without breaking down. AC current interruption results when the high temperature developed by the resistor produces mechanical expansion stresses that cause the ceramic to break

Over-current Protection

Current limiting devices provide a slow response, and are primarily aimed at protection from surges lasting hundreds of milliseconds or more, including power induction or contact with AC power. By combining a fixed resistor in series with a resettable protector, an optimum balance of nominal resistance and operating time is obtained. The inherent resistance of certain over-current protectors can also be useful in coordination between primary and secondary overvoltage protection. Positive Temperature Coefficient (PTC) Thermistors Heat generated by current flowing in a PTC thermistor causes a step function increase in resistance towards an open circuit, gradually returning close to its original value once the current drops below a threshold value. The resistance stability after surges over time is a key aspect for preserving line balance. PTCs are commonly referred to as resettable fuses, and since low-level current faults are common, automatically resettable protection can be particularly important. Fuses A fuse heats up during surges, and once the temperature of the metallic element exceeds its melting point, the normal low resistance creates an open circuit. The low resistance of fuses is attractive for power applications, but their operation is relatively imprecise and time-dependant. Once operated, they do not reset. Fuses also require additional resistance for primary coordination. Since overvoltage protection usually consists of establishing a low impedance path across the equipment input, overvoltage protection itself will cause high currents to flow. Although relatively slow acting, fuses play a safety role in removing longer-term faults that would damage protection circuitry, thus reducing the size and cost of other protection elements. It is important to consider the I-t performance of the selected fuse, since even multiples of the rated current may not cause a fuse to rupture except after a significant delay. Coordination of this fuse behaviour with the I-t performance of other protection is critical to ensuring that there is no combination of current-level and duration for which the protection is ineffective. By including structures intended to rupture under excess current conditions or separate components, it is also possible to produce hybrid fusible resistors.

357

Power Electronics

Heat Coils Heat coils are thermally activated mechanical devices connected in series with the line being protected, which divert current to ground. A series coil operates a parallel shunt contact, typically by melting a solder joint that is restraining a spring-loaded contact. When a current generates enough heat to melt the joint, the spring mechanically forces two contacts together, short-circuiting the line. Heat coils are ideal to protect against ‘sneak currents’ that are too small to activate other methods. Their high inductance makes them unsuitable for digital lines. It is also possible to construct current interrupting heat coils which open the circuit as a result of over-current. Line Feed Resistors A Line Feed Resistor (LFR) is the most fundamental form of current protection, normally fabricated as a thick-film device on a ceramic substrate. With the ability to withstand high voltage impulses without breaking down, AC current interruption occurs when the high temperature developed by the resistor causes mechanical expansion stresses that result in the ceramic breaking open. Low current power induction may not break open the LFR, creating long-term surface temperatures of more than 300°C. To avoid heat damage to the adjacent components, the maximum surface temperature can be limited to about 250°C by incorporating a series thermal fuse link on the LFR. The link consists of a solder alloy that melts when high temperatures occur for periods of 10 seconds or more. Along with the high precision needed for balanced lines, LFRs have significant flexibility to integrate additional resistors, multiple devices, or even different protection technology within a single component. One possible limitation is the need to dimension the LFR to handle the resistive dissipation under surge conditions. Along with combining multiple non-inductive thick-film resistors on a single substrate to achieve matching to 2kV/ms) • Compared with the MOV, the total energy dissipated is lower, since the crowbar characteristic is not possessed by MOV devices • Similar current surge capabilities as the GDT • Short circuit mechanism for protection of the equipment

Disadvantages: • Very high current surge pulse limitation, where more silicon is needed • Temperature dependency of the electrical parameters • Surge performance limited at low temperatures (0

i p1 =

Ns i N p s1

(11.214)

π

Such that 2 Io 3

Ns N 3 Is = s Np Np The secondary harmonic currents are given by

Ish =

1

h

I s1 =

1

6

h π

Io

for h = 6n ± 1

i p3 =

Ns i Np s3

(11.223)

Ns (i − i ) = i p 2 − i p 3 Np s2 s3

iL2 =

Ns (i − i ) = i p 3 − i p1 N p s 3 s1

(11.224)

Thus the transformer currents are related to the supply line currents by

i p1 =

Ns i = 2i − 2i N p s 1 3 L1 3 L 2

i p2 =

Ns i = 2i − 2i N p s 2 3 L2 3 L3

i p3 =

Ns 2 2 i = i − i N p s 3 3 L 3 3 L1

(11.225)

i L1 + i L 2 + i L 3 = 0

(11.226)

Ns N 2 2 I = s ½I o Np s Np 3

(11.227)

Generally

The secondary phase currents in figure 11.25b are the same as for the Y-y connection, but the line currents are composed as follows i L1 = i p 1 − i p 3 i L 2 = i p 2 − i p1 iL3 = i p 3 − i p 2 (11.217)

IL = 3 I p =

Ns i Np s2

i L2 =

where

delta connected primary ∆-y (Delta-wye)

Ns N I = s Np s Np

i p2 =

Ns (i − i ) = i p 1 − i p 2 N p s1 s 2

Since with a star primary the line currents are the primary currents, the supply power factor is P 3 pf = o = = 0.955 (11.216)

Ip =

(11.222)

i L1 =

The fundamental ripple in the output voltage, at six times the supply frequency, is 0.057Vo.

ii.

= 0.955

where (11.213)

π

S

3

π

and i s 1 + i s 2 + i s 3 = 0

The full-wave, three-phase rectified average output voltage (assuming the appropriate turns ratio, 1:1, to give the same output voltage for a given input line voltage) is 3 3 3 Vo = V p = VL (11.215)

π

(11.221)

star connected primary Y-δ (Wye-delta)

(11.212)

 2π 2π  S = ½  Po + Po  = 1.35Po 3 3 3   The secondary harmonic currents are given by 1 1 6 I s h = I s1 = I o for h = 6n ± 1 ∀

h

S = 1.05Po

The supply power factor is

whence

Sp =

π

In the Y-δ configuration in figure 11.26a, there are no zero sequence currents hence no mmf bias arises, mmfo = 0, and both transformer sides have positive and negative sequence currents.

Generally

N N Ip = s Is = s Np Np

The full-wave, three-phase rectified average output voltage (assuming the appropriate turns ratio, √3:1, to give the same output voltage for a given input line voltage) is 3 3 3 Vo = V p = VL (11.220)

pf =

and the secondary currents always sum to zero, then mmfo = 0. Additionally

i L1 = i p 1 =

458

The fundamental ripple in the output voltage, at six times the supply frequency, is 0.057Vo.

3

3 × mmf o = N p ∑ i pi − N s ∑ i si

but

Naturally Commutating AC to DC Converters- Uncontrolled Rectifiers

Ip =

The full-wave, three-phase rectified average output voltage (assuming the appropriate turns ratio, √3:1, to give the same output voltage for a given input line voltage) is 3 3 3 Vo = V p = VL (11.228)

π

π

(11.218) The fundamental ripple in the output voltage, at six times the supply frequency, is 2/5×7 = 0.057Vo.

2 Io

The supply power factor is ∀

n >0

pf =

(11.219) for an output power, Po = Vo Io,

3

π

(11.229)

Power Electronics

459

iv.

Chapter 11

Naturally Commutating AC to DC Converters- Uncontrolled Rectifiers A

delta connected primary ∆-δ (Delta-delta) A

The phase primary and secondary voltages are in phase. As shown in figure 11.26b the line currents are composed as follows i L1 = i p 1 − i p 3 i L 2 = i p 2 − i p1 iL3 = i p 3 − i p 2 The transformer primary and secondary currents are

i p1

N = s is1 Np

i p2

and

N = s is2 Np

i p3

B

Vp1

(11.230)

Np

Np

ip12

ip2

ip3 mmfo

Vp1

-ip1Np

Vp3

Np

mmfo

mmfo

N = s is3 Np

IL12

C Vp2

B

VL1

N

C

VL2

IL2

IL3 Vp2

Np

Np

ip12

ip2

Vp3

Np ip3

mmfo

mmfo

460

mmfo

n

n

(11.231) Vs1

Ns

Vs1

Vs3

Vs2 Ns

Ns

Ns

Ns

is1

is2

Vs3

Vs2 Ns

+is1Ns

i p1 + i p 2 + i p 3 = 0

a

is1 + is 2 + is 3 = 0 i L1 + i L 2 + i L 3 = 0 Generally

Ip =

(11.233)

The full-wave, three-phase rectified average output voltage (assuming the appropriate turns ratio, 1:1, to give the same output voltage for a given input line voltage) is 3 3 3 Vo = V p = VL (11.234)

π

3 9 3 + 2 4π The fundamental ripple in the output voltage, at six times the supply frequency, is 0.057Vo.

Vo rms = 2V s

3

a

(11.235)

D1

D6

D3

D2

D5

LL

RL

ab

V

ac

bc

is3 c

b

D4 Σ mmf Io

ba

ca

cb

ab

Vo =

ac

Vbn

Vcn

Van

Vs1

Vs2

Vs3

Vs1

D6

D3

D2

D5

3 3

π

Vs 1

ab

V

LL

RL

ac

bc

ba

ca

cb

ab

Vbn

Vcn

Van

Vs1

Vs2

Vs3

Vs1 ωt

π

2π

2π

Io

ip1=is1

D1

(11.236)

ωt

D1 D4

D4

-Io

Thus the supply power factor is

pf =

VD4

3

π

ID

1 = Io 3

Vp =

3 Ns

π Np

I D rms =

1 3

VL Io

pf = Vl

DR

Io

ip1=is1

D1

ip2=is2 D6

D5

D2

ωt

D2

-Io

Io

iL1

ωt

D3

-Io ip1=is3

Io

D5 D2

mmf

Io

D5

ωt

D6

π

= 3 2V s

ip1=is3

2Io

Io

D3

3

D6

D4

-Io

ωt

D3

D6

ωt

D1 D4

Io

D3

-Io

ωt

o

3 3

π

√6Vs

Io

Io

In summary, when the primary and secondary winding configurations are the same (∆-δ or Y-y) the input and output line voltages are in phase, otherwise (∆-y or Y-δ) the input and output line voltages are shifted by 30º relative to one another. Independent of the transformer primary and secondary connection, for a specified input and output voltage, the following electrical equations hold.

Vo =

ip2=is2

VD1

(11.237)

for an output power, Po = Vo Io,

Io

ac

Van

ωt π

Po = 1.05Po

D1

Vo

Van

The primary and secondary apparent powers are

π

c

is3

Vo

The rms output voltage is

Sp = Ss =

b

is2

D4

Ns I Np s

π

is1

(11.232)

D5

-Io -2Io

ωt

D2

-Io

Io

iL2

ωt

o

(a)

(b)

mmf

-2Io o

ωt

ωt

Figure 11.25. Three-phase transformer wye connected secondary winding with full-wave rectification and no resultant dc mmf bias: (a) star connected primary Y-y and (b) delta connected primary ∆-y.

Power Electronics

461

Chapter 11 A

A Vp1

B

Np

Np

ip12

ip2

C Vp2

Np ip3

mmfo

mmfo

a

Ns

Ns

is1

is2

mmfo

D4

D1 D3 LL

RL

N

D5

IL12

IL2

Np

Np

ip12

ip2

+is1Ns

a

Σ mmf

Ns

Ns

is1

is2

Vbn

Vs1

V

Vp2

ip3 mmfo

Vs3

Ns

b

is3 c D1 D3 LL

RL

D5

Van

Vs3

Vo =

Vs1

3 3

π

Voltage multipliers

Io

ID3

ID2

C1

C3

Vs 1 +

+ D2 ID1

2π

0V √2Vs

VD1 Io

Io

Io

ip1=is1

D1

ωt

D1

ωt

D1 D4

-Io

D6

ip2=is2

D4

Io

D5 D2

D5

D5

ωt

D2

-Io 2Io

ωt

D2

-Io

Io

D5 D2

-Io ip1=is3

ωt

D3

ip1=is3

D6

Io

iL1

ωt

ωt

o

-Io -2Io Io

iL2

(a)

(b)

mmf

-2Io o

C2

+ C4

Vout

+ hv dc

Figure 11.27. Charging sequence of a half-wave series positive output voltage multiplier.

D6

-Io ωt

D3

+

D3

ID4

Io

D3 D6

Io

D3

mmf

D4

-Io

Io

D1

ωt

D1 D4

o

ip1=is1

D4

Vac

ωt π

462

Voltage multipliers are ac to dc power conversion circuits, comprised of diodes and capacitors that are interconnected so as to produce a high potential dc voltage from a lower voltage ac source. As in figure 11.27, multipliers are made up of cascaded stages each comprised of a diode and a capacitor. Voltage multipliers are a simple way to generate high voltages at relatively low currents. By using only capacitors and diodes, the voltage multipliers can step up relatively low voltages to extremely high values, while at the same time being far lighter and cheaper than transformers. The advantage of the circuit is that the voltage across each cascaded stage is only equal to twice the peak input voltage, so it requires relatively low cost components and is easy to insulate. One can also tap the output from any stage, like a multi-tapped transformer. The voltage multiplier has poor voltage regulation, that is, the voltage drops rapidly as a function the output current. The output I-V characteristic is approximately hyperbolic, so it is suitable for charging capacitor banks to high voltages at near constant charging power. Furthermore, the ripple on the output, particularly at high loads, is high. The output voltage is not isolated from the input voltage source, although transformer coupling provides general isolation. The most commonly used multiplier circuit is the half-wave series multiplier. Other multiplier circuits can be derived from its operating principles.

Vp3

Np

Vo

Vcn

Vs2

11.4

IL3

D4

Vo

Van

C

D6 D2

Io

VL22

mmfo

mmfo

is3 c

D6 D2

-ip1Np

Vs3

Ns

b

Vp1

Vp3

B

VL12


The following description for a two-stage series voltage multiplier assumes no losses and represents sequential reversals of polarity of the source transformer Ts in the figure 11.27. The number of stages is equal to the number of smoothing capacitors between ground and Vout, which in this case is two, capacitors C2 and C4. • Vac = Negative Peak: C1 charges through D1 to Vpk by current ID1 • Vac = Positive Peak: Vpk of Ts adds arithmetically to existing potential C1, thus C2 charges to 2 Vpk thru D2 by current ID2 • Vac = Negative Peak: C3 is charged to 2Vpk through D3 by current ID3 • Vac = Positive Peak: C4 is charged to 2Vpk by current ID4 through D4 then Vpk. For N stages (series capacitors) the output voltage is N×Vpk. 11.4.1 Half-wave series multipliers

ωt

ωt

Figure 11.26. Three-phase transformer with delta connected secondary winding with full-wave rectification and no resultant dc mmf bias: (a) star connected primary Y- δ and (b) delta connected primary ∆- δ.

The capacitors are in series, so effectively capacitance is as for series connected capacitors, C/N, but voltage rating is the cumulative sum of the series capacitors between the output terminals. This multiplier is the most common, and is versatile, being used in high-voltage, low-current applications. The basic charging sequence in figure 11.28 is as for the circuit shown in figure 11.27, where the diodes conduct in the order D1 to D4, for both output polarity versions. Half-wave series voltage multiplier features include: • A wide range of multiplication stages • Low cost • Uniform stress per stage on diodes and capacitors, 2Vpk and Vpk Any one capacitor can be eliminated from the capacitor filter bank if the load is capacitive. Whether full wave or half-wave, the series diodes prevent the output voltage from swinging negative. At high discharges, part of the output current is also drawn via a diode, hampering rapid high current discharge.

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Chapter 11

Dual polarity output voltage is produced by connecting positive and negative multipliers as shown in the four stage circuit is shown in figure 11.28c, where an unlimited stage number can be cascaded. Since regulation is proportional to N³, a large number of stages eventually becomes ineffective. A centre tapped capacitor string connection reduces the maximum voltage potential with respect to ground. An odd number of stages can be produced as well as an even number of stages. The output voltage may be tapped at any point on the capacitor series filter bank.

+

D4

Vout

+ hv dc

-

D4

C4 +

- hv dc

N

D3

C3

Regulation voltage droop is not a power losses in a multiplier. Power losses are primarily diode forward conduction and rarely result in excessive multiplier temperatures at the low current loadings. Substituting Vreg from equation (11.239): 4N 3 + 3N 2 − N Vout = Vo /c −V reg = 2NV pk − I o × (11.240) 6f × C

D3

C3 +

C1

C1

D1

Vac

0V

(a)

Output Voltage Ripple Ripple voltage is the magnitude of fluctuation in dc output voltage at a specific output current. This assumes the ac input voltage and frequency are maintained constant. The ripple voltage in the case where all stage capacitances, C1 through C2N, are equal, is: N2 +N V ripple = I o × (11.241) 2f × C The ripple grows rapidly as the number of stages increases, with N squared. A common modification to the design is to make the stage capacitances larger at the input, with C1 = C2 = N×C, C3 = C4 = (N-1)×C, and so forth. Then the ripple is:

C2

-

D1

Vac

-

D2

C2

+

0V

(c)

(b)

V ripple =

Vac C1

C6

+

+

+

+ C2

C5

C3

+

-Vout

Io is the load or output dc current (A) C is the stage capacitance (F) f is the ac frequency (Hz) N is the number of stages C/N is the effective output capacitance.

C4

-

D2

464

Output Voltage Regulation DC output voltage drops as the dc output current increases. Regulation is the drop in dc output voltage from the ideal at a specified dc output current (assuming the ac input voltage and ac input frequency are constant). The voltage drop under load is mostly reactive and is calculated as: 4N 3 + 3N 2 − N 4N 2 + 3N 2 − 1 = Io × V reg = I o × (11.239) 6f × C 6f × C

where: Vout


0V

+

+ C6

C4

+

+Vout

C8

Vac

Figure 11.28. Series half-wave voltage multipliers: (a) two stage positive hv output voltage; (b) two stage negative hv output voltage; and (c) four stage multiplier configured with ± output hv voltage.

Once a load is connected at the output, the output voltage decreases due to the voltage regulation. Also, any small fluctuation of load impedance causes a large fluctuation in the multiplier output voltage due to the number of stages involved. For this reason, voltage multipliers are used only in special applications where the load is constant and has a high impedance or where voltage stability is not critical. Half-wave Output Voltage The open-circuit output voltage Vo/c of each stage is nominally twice the peak input voltage Vpk. Assuming the ac input voltage and frequency are constant, for N cascaded stages, the output voltage is Vo /c = 2N ×V pk (11.238)

In practice, several cycles are required to reach full output voltage. The output voltage follows an RC network exponential curve, where R is the output impedance of the ac source, whilst C is the effective dynamic capacitance of the voltage multiplier, N×C. This charging occurs only upon switch-on of the voltage multiplier from a discharged state, and does not repeat itself unless the output is short circuited. The most common input ac waveforms are sine waves and square waves.

Io f ×C

(11.242)

For a large number of stages, N ≥ 5, the N3 term in the voltage drop equation dominates. Differentiating the Vout equation without the negligible terms, with respect to the number of stages and equating to zero, gives an equation for the optimum (integer) number of stages Nopt for the equal valued capacitor design: dVout Io d   = × 4N 3  = 0 2NV pk − dN dN  6f × C  :  V f × C ½  (11.243) N opt = int  pk     I o   Increasing the frequency can dramatically reduce the ripple, and the voltage drop under load, which accounts for the popularity driving a multiplier stack with a switching power supply. If the driving voltage Vpk and the required output voltage Vo/c are known, the optimum number of cascaded stages is:  3V  (11.244) N opt = int  out   4V pk  11.4.2 Half-wave parallel multipliers

Opposite polarity half-wave parallel voltage multipliers are shown in figure 11.29. The output capacitors share a common connection but must have a high voltage rating. The output is usually low voltage but with high currents. The basic charging sequence in figure 11.29 is the same as shown in figure 11.27, where the diodes conduct in the order D1 to D4, for both output polarity versions. Parallel multipliers offer the following features: • Uniform stress on diodes • compact • Voltage stress on capacitors increases with successive stages by Vpk • Highly efficient

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Chapter 11

Vout

- hv dc

D4

C3

Output Voltage Regulation DC output voltage decreases as dc output current increases. Regulation is the drop in dc output voltage from the ideal at a specified dc output current, assuming constant ac input voltage and frequency. The voltage drop under load is mostly reactive and is: N 3 + 2N N2 + 2 = Io × V reg = I o × (11.246) 6f × C 6f × C

+

+

D3

C4

+

C4

D3

N

+

D2

C1 +

where:

D2

C1

+

+

C2

C2 +

D1

D1

Vac

Vac

0V

0V

(a)

466

Full-wave Output Voltage As with the half-wave voltage multiplier, the full wave voltage multiplier output voltage is given by: Vo /c = 2NV pk (11.245)

Vout

+ hv dc

D4

C3


(b)

Figure 11.29. Parallel half-wave voltage multipliers: (a) two stage positive hv output voltage and (b) two stage negative hv output voltage.

Io is the load or output dc current (A) C is the stage capacitance (F) f is the ac frequency (Hz) N is the number of stages C/N is the effective output capacitance.

Regulation voltage droop is not a power losses in a multiplier. Power losses are primarily diode forward conduction and rarely result in excessive multiplier temperatures at the low current loadings. Substituting equation (11.246) for Vreg: N 3 + 2N (11.247) Vout = Vo /c −V reg = 2N ×V pk − I o × 6f × C Output Voltage Ripple The ripple voltage, in the case where all stage capacitances are equal, is given by:

11.4.3 Full-wave series multipliers

V ripple = I o ×

Increasing the frequency can dramatically reduce the ripple, and the voltage drop under load, which can be achieved by driving a multiplier stack with a switched mode power supply. Figure 11.30 shows a typical full-wave two-stage series voltage multiplier. It is comprised of two antiphase ac input half-wave multipliers sharing a common series output capacitor string. This effectively doubles the number of charging cycles per second, and thus reduces the voltage drop and ripple factor. The input is usually fed from a centre-tapped ac transformer or MOSFET H-bridge circuit. Vac

C1

If the driving voltage Vpk cascaded stages is:

N

(11.248) 2f × C and the required output voltage Vo/c are known, the optimum number of  0.521Vout    V pk 

N opt = int 

(11.249)

C3

Example 11.9: Half-wave voltage multiplier +

+

+ 0V

A three-stage half-wave series voltage multiplier, is driven by a 50kHz peak voltage of 10kV, with 1nF capacitances, and a load current of 10mA. i. Calculate the open circuit output voltage, regulated output voltage, ripple voltage, and optimal number of stages for the required voltage transfer function. ii. What is the capacitance and voltage rating of each stage of a parallel connected multiplier? iii. What is the output ripple if progressively smaller capacitance is used?.

+

C5

C6 Vout

+ Vac

C2

+

Solution

i.

C4

Vout = 60kV - 1.7kV = 58.3kV So the output voltage will swing between 6kV and 58.3kV, depending on the load current. The output ripple voltage is N2 +N 32 + 3 = 10mA = 3kV V ripple = I o 2f × C 2 × 50kHz × 1nF The optimal number of stages, from equation (11.249), is  0.521 ×Vout   0.521 × 58.3kV  N opt = int   = int  =3 10kV V pk    

Figure 11.30. Two-stage series full-wave voltage multiplier.

The full-wave series voltage multiplier has the following general features: • Uniform stress on components • Highly efficient • High Voltage • High power capability • Easy to produce • Increased voltage stress on capacitors with successive stages • Wide range of multiplication stages

In a three-stage voltage multiplier, the no load voltage Vo/c = 2×N×Vpk = 2×3×10kV = 60kV 4N 3 + 3N 2 − N 33 + 3 × 32 − 3 = 10mA × = 1.7kV V reg = I o 6f × C 6 × 50kHz × 1nF

ii.

An equivalent parallel multiplier would require each capacitor stage to equal the total series capacitance of the AC capacitor bank.

Power Electronics

467

In this case, the three capacitors in the dc bank would equal 1000pF/3 or 330pF. The parallel equivalent would require 330pF capacitors in each stage. However, each successive stage, from the input, would require a higher voltage capacitor, 20kV, 40kV and 60kV, respectively. iii.

Chapter 11

Naturally Commutating AC to DC Converters- Uncontrolled Rectifiers D1

(a)

C1

D4 C4

+

C2

D5 C5

+

D8

+ D6

D3 C3

D7

+

D2

When C1 = C2 = N×C = 3nF, C3 = C4 = (N-1)×C = 2nF, C5 = C6 = (N-2)×C = 1nF. I 10mA V ripple = o = = 200V f × C 50kHz × 1nF This modification reduces the ripple voltage from 3kV to just 200V. ♣

468

C6

+

Vout D9

+

Example 11.10: Full-wave voltage multiplier

A three-stage full-wave parallel voltage multiplier, is driven by a 50kHz peak voltage of 10kV, with 1nF capacitances, and a load current of 10mA. Calculate the output voltage and ripple voltage.

(b)

Solution Vpk

In a three-stage voltage multiplier, the no load voltage Vo/c = 2×N×Vpk = 2×3×10kV = 60kV. N 3 + 2N 33 + 2 × 3 = 10mA = 1.1kV V reg = I o 6f × C 6 × 50kHz × 1nF Full-wave rectification reduces the regulation voltage drop from 1.7kV in example 11.21, to 1.1kV. The output voltage is increased by 600V, from 58.3kV in example 11.21, to Vout = 60kV - 1.1kV = 58.9kV. The ripple voltage reduces from 3kV for half-wave multiplication in example 11.21, to N 3 V ripple = I o = 10mA = 200V 2f × C 2 × 50kHz × 1nF ♣

Vpk

C3

+

C2

+

C1

+ D1

Vpk

D2

D3

D4

D5

D6 Vout

+

0V

2Vpk

C4

(c)

11.4.4 Three-phase voltage multipliers

C3 +

The full-wave multiplier in figure 11.31 is a special case of a poly-phase (0° and 180°) multiplier where more than one multiplier share a common series stack of load capacitors. In figure 11.31, the phase angle between phases is 0°, 120°, and 240°, respectively. The peak voltage supplied by each secondary winding is Vpk. The three-phase circuit in figure 11.31b can be modified by disconnecting the centre point of the Y configuration from ground and omitting the first capacitor in each charging stack, as shown in figure 11.31c. As a result, the open-circuit dc voltage per stage is reduced from 2×Vpk to √3×Vpk. The output impedance, however, decreases dramatically, so the output voltage under load may be even higher, depending on the load current. Therefore, this variant is preferred if the multiplier has to supply higher currents.

Vpk

C2 +

C1 + Vpk

D1

Vpk

D2

D3

D4

D5

D6

D7

D8

+ 0V

D9

D11

D10

D12

Vout

+

C4

√3NVpk

C5

11.4.5 Series versus parallel voltage multipliers Figure 11.31. Three-phase Y configuration voltage multipliers: (a) series diode output stage; (b) grounded centre point; and (b) floating centre point.

The theory of operation is the same for both series and parallel connected voltage multipliers. Parallel multipliers require less capacitance per cascaded stage than their series counterparts, however parallel multipliers require higher capacitor voltage ratings on successive cascaded stages. The parallel multiplier output is easier to RC filter in applications requiring low output ripple voltage. 11.5

Marx voltage generator

The Marx generator shown in figure 11.32, charges the energy storage capacitor of each stage in parallel with a relatively low voltage (1kV to 6kV), and then discharges them by means of active switches in series, into the load. The output voltage is then equal to the charging voltage multiplied by the number of stages. The series inductance of this type of generators is low, as a result the rise time and fall time of the output pulses can be less than 1µs. The pulse repetition rate can be more than 20kHz for short pulses, and the pulse length can be several ms.

L

L

Vdc

+

SG

L

+

L

L C

C SG

L

+

C

C SG

+

L

SG

L

Vout Figure 11.32. The hv Marx generator.

+

Power Electronics

469

11.6

Chapter 11

11.7

Definitions

The average (or mean or dc) rms (or effective) values, respectively, of a waveform, are defined by T 1 Vo = ∫ v o (t ) dt

T

1

p =

T

∫v (t ) dt 2

o

T

o

Load current form factor = FF i =

Irms

l Load voltage crest factor = CFv = V

Vo

Load current crest factor = CF i = I

Io

∞  =  ∑ 12 (v an2 + v bn2 )  n =1 

Vo

similarly the current ripple factor is RF i =

Vrms Irms

effective values of acV (or I ) VRi = average value of V (or I ) Vo 2 2 V −V = rms 2 o = FFv 2 − 1

½

I Ri = FF i 2 − 1 Io

period of input supply voltage period of minimum order harmonic in the output V or I waveform

The pulse number p is specified in terms of q the number of elements in the commutation group r the number of parallel connected commutation groups s the number of series connected (phase displaced) commutating groups

I o average output current I rms rms output current l I peak output current

Waveform smoothness = Ripple factor = RFv =

VRi

Output pulse number

o

Vo average output voltage Vrms rms output voltage Vl peak output voltage V Load voltage form factor = FFv = rms

where

470

Output pulse number p is the number of pulses in the output voltage that occur during one ac input cycle, of frequency fs. The pulse number p therefore specifies the output harmonics, which occur at p x fs, and multiples of that frequency, m×p×fs, for m = 1, 2, 3, ...

and

Vrms =


Parallel connected commutation groups, r, are usually associated with (and identified by) intergroup reactors (to reduce circulating current), with transformers where at least one secondary is effectively star connected while another is delta connected. The rectified output voltages associated with each transformer secondary, are connected in parallel. Series connected commutation groups, s, are usually associated with (and identified by) transformers where at least one secondary is effectively star while another is delta connected, with the rectified output associated with each transformer secondary, connected in series. q =3 r =2 s =2 p=qxrxs p = 12

The mean rectifier output voltage Vo can be specified by

Vo = s

RF i = RFv for a resistive load dc load power ac load power + rectifier losses

Rectification efficiency = η =

Vo I o V rms I rms + Lossrectifier Waveform fundamental and harmonic rms components are define by =

V1 = ½ (V12a +V12b )

q π

2 Vφ × sin

π q

(11.250)

For a full-wave, single-phase rectifier, r = 1, q = 2, and s = 1, whence p = 2 π 2 2Vφ 2 Vo = 1 × 2 Vφ × sin = π π 2 For a full-wave, three-phase rectifier, r = 1, q = 3, and s = 2, whence p = 6 π 3 2Vφ 3 Vo = 2 × 2 Vφ × sin = 3 π π

where 2

V 1a =

T

V 1b =

2

T

T

∫v (t ) cos 2π t T dt o

T

∫v (t ) sin 2π t T dt o

and for the kth harmonic component

11.8


Alternating sinusoidal voltages V1 = 2V sin ωt .

V k = ½ (V ka +V kb ) 2

2

where

V ka = V kb =

2

T T

T

∫v (t ) cos 2π kt T dt

Vq = 2V sin ωt − (q − 1) 2qπ

)

o

Voltage form factor

∫v (t ) sin 2π kt T dt V1 V rms

The total harmonic distortion is ∞

)

On the secondary or converter side of any transformer, if the load current is assumed constant I o then the power factor is determined by the load voltage harmonics.

DFv =

2

1 − DFv 2 V k   = DFv 2  1

∑ V

k =0 k ≠1

q

T

Distortion factor is defined as

THDv =

(

2π

where q is the number of phases (number of voltage sources)

o

2

(

V 2 = 2V sin ωt −

FFv =

V rms Vo

whence the voltage ripple factor is ½ ½ 1 2 RFv = V rms −Vo2  = FFv 2 − 1 V o

The power factor on the secondary side of any transformer is related to the voltage ripple factor by P V I 1 pf = d = o o = S qVI rms RFv 2 + 1

Power Electronics

471

Chapter 11

On the primary side of a transformer the power factor is related to the secondary power factor, but since the supply is assumed sinusoidal, the power factor is related to the primary current harmonics. Relationship between current ripple factor and power factor 1 ∞ 2 1 2 RFi = − I 12 ∑ I h = I rms

I1

I1

h =3

I1

pf =

I rms

=

1


The apparent power is

S = qVI rms The power factor on the secondary side of any transformer is P V I 1 pf = d = o o = S qVI rms RFv 2 + 1

1 + RFi 2

=

q π

2 V sin

π × Io q 1

qV × I o

The supply power factor is related to the primary power factor and is dependent of the supply connection, star or delta, etc.

2q π sin q π

=

q

The primary side power factor is supply connection and transformer construction dependant. Half-wave diode rectifiers [see figures 11.2, 11.10]

For two-phase half-wave p=q=2

Pulse number p=q. Pulse number is the number of sine crests in the output voltage during one input voltage cycle. There are q phases and q diodes and each diode conducts for 2π/q, with q crest (pulses) in the output voltage

pf 1φ ,½ = For three-phase half wave p=q=3

q  2π

∫

½π + π q

½π − π q

(

 2π  q = 2V ½ + sin q  4π  Normalised peak to peak ripple voltage

v p − p = 2V − 2V cos Vnp − p

π q

pf 6φ ,½ =

q π

2



2 V sin

π q



V rms Vo

π q

sin

 q 2π  ½ + 4π sin q    = π q sin

π

½

q

whence the voltage ripple factor is ½ ½ 1 2 RFv = V rms −Vo2  = FFv 2 − 1 V Diode reverse voltage

DR

if q is even

π = 2 2 V cos 2q

ID =

Io q

= 0.995

ωLc

π 2 2V sin ωLc q

For a constant load current Io the output power is Pd = Vo I o

q

=

2 sin

π q

ωLc I o π q

The commutation voltage drop

v com = q ωL I where 2Lc = Ls / c c o 2π p=q=

Isec rms

2

Io /√2

3

Io /√3

6

Io /√6

Vo

VlD

%Vp-p

Ks/c

pfsec

0.90V

2√2 V

0.157

1

0.636

0.90

0.68

1.17V

√6 V

0.604

1.73

0.675

0.827

0.31

1.35V

2√2 V

0.140

6

0.55

0.995

RFv

N

1

.

×

V 1 + R 3

.3 4π

−

Io q

.

3 2π 2

N

 

½

I L∆ =

N

1

×

V 2 + R 3

.3  2π 

½

V ×  2 + .3  1 R  9 6π  Time domain half-wave single phase R-L-E load E Z  − ωt −α E 2V  − sin (ωt − φ )  e tanφ i o (ωt ) = − +  sin (ωt − φ ) +  R Z  R 2 V   k   ∞ −2 −1 ( ) v o (ωt ) = Vo 1 + ∑ 2 2 cos ( kq ωt )    k =1 k q − 1   I LY =

I D rms =

(Y conection)

2V sin

I p∆ =

if q is odd

For a constant load current Io, diode currents are

ID = I o

π q

π q

.

Vl DR = 2 2V

3

π

For three-phase resistive load, with transformer turns ratio 1:N ½ 2V 3 3 V Io = I o rms =  13 + 4.3π  R 2π R ½ π2 + π  FFi output =  227 6 .3 

o

Vl

K s/c =

1 − cos

Voltage form factor

FFv =

==

Commutation overlap angle

=

π q

3 3 = 0.827 2π

The short circuit ratio (ratio actual s/c current to theoretical s/c current) is q 2V

½

d ωt 

½

Vo I o

3V I o

1 − cos µ =

2 V − 2 V cos

v p −p = = Vo

)

2 V sin ωt

=

3V I o

For six-phase half-wave p=q=6

RMS voltage

V rms = 

Vo I o

pf 3φ ,½ =

Mean voltage

q ½π + π q Vo = 2V sin ωt d ωt 2π ∫½π − π q π q 2 V sin = π q

Vo I o 2 2 = = 0.90 V Io π

½

   

pfprim

472

Power Electronics

473

Chapter 11

Full-wave diode bridge rectifiers - star [see figures 11.7, 11.12]


For single phase p=2

RFi =

q phases and 2q diodes

1

2 I rms − I 12

I1

 1 4

Mean voltage

I o2 − 

q ½π + π q Vo = ∫ π 2V sin ωt d ωt π ½π − q π 2q = 2V sin π q if q is even if q is odd

VlDR = 2 2V if q is even π VlDR = 2 2V cos if q is odd 2q For a constant load current Io, diode currents are

ID =

Io q

I D rms =

1 + RFi 2



Ih =

Io

1

= 1+

q

π2 p2

RFv =

q π 2V sin × I o q

π Pd VI = o o = S qVI rms

2

qV × I o

=

2 q

π

sin

π q

pf =

q

1

Vo I o = π 3VI o

2V × ½I o

=

3

π

v com = q ωL I where 2Lc = Ls / c π c o = 0.955

For p=q=2, only 1 − cos µ =

%Vp-p

Ks/c

0.483

1.80V

2√2 V

0.157

2/π

0.90

0.90

0.31

2.34V

√6 V

0.140

6/π

0.995

0.995

Io √⅔ Io

pfY prim

2ωLc I o

v com = 4 ωL I π c o

pfsec

The short circuit ratio (ratio actual s/c current to theoretical s/c current) is

q 2π sin

q π

1

∞

1

I 1 h =3 I1 I 1 pf = 1 = I rms 1 + RFi 2

q Io

=

2

q

V 2 sin

for q = 2

∑ I h2 =

2

Io

Same expression as for delta connected secondary, except supply voltages V are replaced by

Relationship between current ripple factor and supply side power factor on the primary

RFi =

I o rms = Io

Full-wave diode bridge rectifiers – delta

π q

which is smaller by a factor π than the half-wave case.

K s/c =

2V

Load characteristics Current Form Factor = FF I =

K s/c =

π q

The commutation voltage drop

VlD

p=q=2

= 0.90

−1

2V sin

Vo

p=2 q=6

.

π

ωLc I o

1 − cos µ =

2 3V × I 3 o

RFv

2 2

p π sin π p

=

1 + RFv 2

Commutation overlap angle

V I 2 2 pf 1φ = o o = = 0.90 π V Io For three-phase full-wave p=2 q=6 6

π p

sin2

For single-phase, full-wave p=q=2

Isec

=

π2 − 8

.

which is √2 larger than the half-wave case.

p, q

= 0.483

8

Io

I1 I1 = for k ≥ 1, 2, 3... h kp ± 1

2

pf 3φ =

π2 − 8

=

For p-pulse

2q

pf =

1

2

.

The current and power factor are

I rms = I o

2π



Io 

8 The rms of the fundamental component is 1 4 I1 = Io 2π The rms of the harmonic components are

Diode reverse voltage

ID = I o

.

.

pf = p=q p=2q

 1 4

=

Pulse number

2π

2 I rms − I 12

π q

For example in three-phase, V is replaced by V/√3, that is, V L −L = The mean output voltage is π 2q 2q Vo = 2V ∆ sin =

π

q

π

2

V 2 sin

π q

sin

π q = q π

2V

.

3V L −N =

.

3V phase

474

Power Electronics

475

Chapter 11


476

Pulse number p=q if q is even p=2q if q is odd diode reverse voltage and currents 2V VlDR = if q is even π sin

Problems

q 2V l V DR = if q is odd π 2 sin 2q I D = I o I D = Io /q I D rms = I o / q

11.1.

Derive equations (11.35) and (11.36) for the circuit in figure 11.5.

11.2.

Assuming a constant load current, derive an expression for the mean and rms device current and the device form factor, for the circuits in figure 11.7.

11.3.

The single-phase full-wave uncontrolled rectifier is operated from the 415 V line-to-line voltage, 50 Hz supply, with a series load of 10 Ω + 5 mH + 40 V battery. Derive the load voltage expression in terms of a Fourier series. Determine the rms value of the fundamental of the load current.

11.4.

A single-phase uncontrolled rectifier has a 24Ω resistive load a 240V ac 50Hz supply. Determine the average, peak and rms current and peak reverse voltage across each rectifier diode for i. an isolating transformer with a 1:1 turns ratio ii. centre-tapped transformer with turns ratio 1:1:1.

11.5.

A single-phase bridge rectifier has an R-L of R = 20Ω and L = 50mH and a 240V ac 50Hz source voltage. Determine: i. the average and rms currents of the diodes and load ii. rms and average 50Hz source currents iii. the power absorbed by the load iv. the supply power factor

11.6.

A single-phase, full-wave uncontrolled rectifier has a back emf Eb in its load. If the supply is 240Vac 50Hz and the series load is R = 20Ω, L = 50mH, and Eb = 120V dc, determine: i. the power absorbed by the dc source in the load ii. the power absorbed by the load resistor iii. the power delivered from the ac source iv. the ac source power factor v. the peak-to-peak load current variation if only the first ac term of the Fourier series for the load current is considered.

11.7.

A three-phase uncontrolled rectifier is supplied from a 50Hz 415V ac line-to-line voltage source. If the rectifier load is a 75 Ω resistor, determine i. the average load current ii. the rms load current iii. the rms source current iv. the supply power factor.

11.8.

A three-phase uncontrolled rectifier is supplied from a 50Hz 415V ac line-to-line voltage source. If the rectifier load is a series R-L circuit where R = 10Ω and L = 100mH, determine: i. the average and rms load currents ii. the average and rms diode currents iii. the rms source and power current iv. the supply power factor.

.

rms current and power factor

I rms even =

Io

.

pf q even

2

I o q − 1 2 q 2

I rms odd =

q 2V I o V I 2 2 = o o = π = π qVI rms qV ½I o .

½

pf q odd =

Vo I o 2 2 q = π q 2 − 1½ qVI rms   .

Commutation angle and voltage 1 − cos µ =

ωLI o

v com = q ωL I c o 2π  1 q v com = ωLc I o 1 − q    2π

2V .

1 − cos µ =

ωLI o  1 1 −  q 2V  .

q even q odd

The short circuit ratio (ratio actual s/c current to theoretical s/c current) is q π q −1 π K s/c even = sin K s/c odd = sin

π

π

q

q

For single-phase resistive load, with transformer turns ratio 1:N 2V 4 2V Io = I o rms = .

R

FFi output =

π π

R

RFv = FF 2 − 1 =

2 2

π2 8

.

Ip =

N 1

I sec =

N 1

×

2V

R

pf =

1

RF 2 + 1

=

−1

2 2 .

π

Reading list

Dewan, S. B. and Straughen, A., Power Semiconductor Circuits, John Wiley and Sons, New York, 1975. Sen, P.C., Power Electronics, McGraw-Hill, 5th reprint, 1992. Shepherd, W et al. Power Electronics and motor control, Cambridge University Press, 2nd Edition 1995. http://www.ipes.ethz.ch/ http://www.celnav.de/hv/hv9.htm http://www.physiqueindustrie.com/custom_converter.php http://www.voltagemultipliers.com/html/multdesign.html

Chapter 12

12.1

Naturally Commutating AC to DC Converters – Controlled Rectifiers

478

Single-phase full-wave half-controlled converter

12.1.1 Single-phase, full-wave half-controlled circuit with an R-L load

12 Naturally Commutating AC to DC Converters

When a converter contains both diodes and thyristors, for example as shown in figure 12.1 parts a to d, the converter is termed half-controlled (or semi-controlled). These four circuits produce identical load and supply waveforms, neglecting any differences in the number and type of semiconductor voltage drops. The power to the load is varied by controlling the angle α, shown in figure 12.1e, at which the bridge thyristors are triggered (after first becoming forward biased). The circuit diodes prevent the load voltage from going negative, extend the conduction period, and reduce the output ac ripple. The particular application will determine which one of the four circuits should be employed. For example, circuit figure 12.1a contains five devices of which four are thyristors, whereas the other circuits contain fewer devices, of which only two are thyristors. The circuit in figure 12.1b uses the fewest semiconductors, but requires a transformer which introduces extra cost, weight, and size. Also the thyristors experience twice the voltage of the thyristors in the other circuits, 2√2 V rather than √2 V. The transformer does provide isolation and voltage matching.

- Controlled Rectifiers

T1 q =2 r =1 s =1 p=qxrxs p=2

T2

(a)

The converter circuits considered in this chapter have in common an ac voltage supply input and a dc load output. The function of the converter circuit is to convert the ac source energy into controllable dc load power, mainly for highly inductive loads. Turn-off of converter semiconductor devices is brought about by the ac supply voltage reversal, a process called line commutation or natural commutation. Converter circuits employing only diodes are termed uncontrolled (or rectifiers) while the incorporation of only thyristors results in a (fully) controlled converter. The functional difference is that the diode conducts when forward-biased whereas the turn-on of the forward-biased thyristor can be controlled from its gate. An uncontrolled converter provides a fixed output voltage for a given ac supply and load. Converters employing a combination of both diodes and thyristors are generally termed half-controlled (or semi-controlled). Both fully controlled and half-controlled converters allow an adjustable output voltage by controlling the phase angle at which the forward biased thyristors are turned on. The polarity of the output (load) voltage of a fully controlled converter can reverse (but the current flow direction is not reversible), allowing power flow into the supply, a process called inversion. Thus a fully controlled converter can be described as a bidirectional converter as it facilitates power flow in either direction. The half-controlled converter, as well as the uncontrolled converter, contains diodes which prevent the output voltage from going negative. Such converters only allow power flow from the ac supply to the dc load, termed rectification, and can therefore be described as unidirectional converters. Although all these converter types provide a dc output, they differ in characteristics such as output ripple and mean voltage as well as efficiency and ac supply harmonics. An important converter characteristic is that of pulse number, which is defined as the repetition rate in the direct output voltage during one complete cycle of the input ac supply. A useful way to judge the quality of the required dc output, is by the contribution of its superimposed ac harmonics. The harmonic or ripple factor RF is defined by

RFv =

vo

vo

(c)

(d)

2 V rms −Vdc2 V2 = rms2 − 1 = FF 2 − 1 2 Vdc Vdc

where FF is termed the form factor. RFv is a measure of the voltage harmonics in the output voltage while if currents are used in the equation, RFi gives a measure of the current harmonics in the output current. Both FF and RF are applicable to the input and output, and are fully defined in section 12.8. The general analysis in this chapter is concerned with single and three phase ac supplies mainly feeding inductive dc loads. A load dc back emf is used in modelling the dc machine. Generally, uncontrolled rectifier equations can be derived from the corresponding controlled converter circuit equations by setting the controlled delay angle α to zero. Also purely resistive load equations generally can be derived by setting inductance L to zero in the L-R load equations and R-L load equations can be derived from R-L-E equations by setting E, the load back emf, to zero.

BWW

Df

D1

(b)

Circuit a

T1 and T4

D1

b

T1

D1

T2

D1

c

T1 and D2

T1 and D1

T2 and D1

T2 and D2

d

T1 and D2

D2 and D1

T2 and D1

D1 and D2

(e)

T2 and T3

D1

Figure 12.1. Full-wave half-controlled converters with freewheel diodes: (a), (b), (c), and (d) different circuit configurations producing the same output; and (e) circuit voltage and current waveforms and device conduction table.

Power Electronics

479

Chapter 12

The thyristor triggering requirements of the circuits in figures 12.1b and c are simple since both thyristors have a common cathode connection. Figure 12.1c may suffer from prolonged shut-down times with highly inductive loads. The diode in the freewheeling path will hold on the freewheeling thyristor, allowing conduction during that thyristors next positive cycle without any gate drive present. The extra diode Df in figure 12.1c bypasses the bridge thyristors allowing them to drop out of conduction. This is achieved at the expense of an extra device, but the freewheel path conduction losses are decreased since that series circuit now involves only one semiconductor voltage drop. This continued conduction problem does not occur in circuits 12.1a and d since freewheeling does not occur through the circuit thyristors, hence they will drop out of conduction at converter shut-down. The table in figure 12.1e shows which semiconductors are active in each circuit during the various periods of the load cycle. Circuit waveforms are shown in figure 12.1e. Since the load is a passive L-R circuit, independent of whether the load current is continuous or discontinuous, the mean output voltage and current (neglecting diode voltage drops) are Vo = I o R = I o = Vo R =

1

∫

π

2V

πR

π α

2

2

V sin(ωt ) d ωt =

(1 + cos α )

π

V

(1 + cos α )

(V)

(12.1)

(A)

where α is the delay angle from the point at which the associated thyristor first becomes forward-biased and is therefore able to be turned on and conduct current. The maximum mean output voltage, Vo = 2 2 V / π (also predicted by equation 11.54), occurs at α = 0. The normalised mean output voltage Vn is Vn = Vo / Vo = ½(1 + cos α ) (12.2) The Fourier coefficients of the 2-pulse output voltage are given by equation (12.128). For the singlephase, full-wave, half-controlled case, p = 2, thus the output voltage harmonics occur at n = 2, 4, 6, …

Equation (12.1) shows that the load voltage is independent of the passive load (because the diodes clamp the load to zero volts thereby preventing the load voltage from going negative), and is a function only of the phase delay angle for a given supply voltage. The rms value of the load circuit voltage vo is 2 1 π π − α + ½ sin 2α Vrms = (12.3) (V) ∫ ( 2 V sin ωt ) dωt = V

π

π

α

From the load voltage definitions in section 12.7, the load voltage form factor is

FFv =

π (π − α + ½ sin 2α ) Vrms = Vo 2 (1 + cos α )

I ½F = ½ I ½s = ½I o - I ½F = ½

2 Vrms − Vo2

(12.5)

VRi / Vo = FFv2 − 1

(12.6)

2V

πR 2V

πR

(

sin φ sin φ − sin (α − φ ) e(

α −π ) / tan φ

)

( cos φ + cos α + sin φ sin (α − φ ) e 2

480

(12.9) (α −π ) / tan φ

)

(12.10)

12.1.1ii - Continuous load current, with α < φ and β − α ≥ π , the load current is given by equations similar to equations 11.20 and 11.21, specifically  sin φ e −α / tan φ − sin(α − φ ) −ωt +α tan φ  i (ω t ) = is (ω t ) = 2 V  sin(ωt − φ ) + e  Z (12.11) 1 − e −π / tan φ   α ≤ ωt ≤ π (A) while the load current when the freewheel diode conducts is i (ω t ) = iDf (ω t ) = I 01π e −ωt / tan φ (A) (12.12) 0 ≤ ωt ≤ α where, for ωt = π in equation (12.11) sin φ − sin(α − φ )e −π +α / tanφ I 01π = 2 V (A) Z 1 − e −π / tanφ The various semiconductor average current ratings can be determined from the average half cycle freewheeling current, I ½ F , and the average half cycle supply current, I ½ s . For continuous load current sin φ − sin (α − φ ) e −π +α / tan φ 2V sin φ I ½F = ½ (12.13) (1 − e−α / tan φ ) 1 − e −π / tan φ πR I ½s = ½I o - I ½F

=½

2V

πR

(

)

− π +α / tan φ −α   1− e ( ) cos φ  tan φ e tanφ sin φ − sin (α − φ ) + cos φ + cos (α − φ )  −π / tan φ 1 − e  

(12.14)

Table 12.1: Semiconductor average current ratings Bridge circuit figure 12.1 a

(12.4)

The ripple voltage is VRi


Number of devices 4T+1D

Average device current Thyristor Diode 1× I ½ s 2× I ½ F

b

2T+1D

1× I ½ s

c

2T+2D

½× I o

2× I ½ F ½× I o

d

2T+2D

1× I ½ s

1× I ½ s + 2× I ½ F

hence the voltage ripple factor RFv is RFv

The load and supply waveforms and equations, for continuous and discontinuous load current, are the same for all the circuits in figure 12.1. The circuits differ in the device conduction paths as shown in the table in figure 12.1e. After deriving the general load current equations, the current equations applicable to the different circuit devices can be decoded. 12.1.1i - Discontinuous load current, with α < π and β – α < π, the load current (and supply current) is based on equation 11.14 namely i (ωt ) = is (ωt ) =

2V

Z

(sin(ωt − φ ) − sin (α − φ ) e

− ωt +α

tanφ

)

(A)

(12.7)

α ≤ ωt ≤ π where Z = R 2 + (ω L ) and φ = tan −1 ω L 2

R After ωt = π the load current decreases exponentially to zero through the freewheel diode according to i (ω t ) = iDf (ω t ) = I 01π e −ωt / tan φ (A) 0 ≤ ωt ≤ α (12.8)

where for ωt = π in equation (12.7) I o1π =

2V Z

sin(φ − α )(1 − e −π / tanφ )

The various semiconductor average current ratings can be determined from the average half-cycle freewheeling current, I ½ F , and the average half-cycle supply current, I ½ s . For discontinuous load current

The device conduction table in figure 12.1e can be used to specify average devices currents, for both continuous and discontinuous load current for each of the circuits in figure 12.1, parts a to d. For a highly inductive load, constant load current, the supply power factor is pf = 2 π √2cosα. Critical load inductance The critical load inductance, to prevent the current falling to zero, is given by ω Lcrit α + sin α + π cos θ = θ − α − ½π + (12.15) 1 + cos α R for α ≤ θ where V 1 + cos α θ = sin −1 o = sin −1 (12.16) π 2V The minimum current occurs at the angle θ, where the mean output voltage Vo equals the instantaneous load voltage, vo. When the phase delay angle α is greater than the critical angle θ, θ = α in equation (12.16) yields (see figure 12.14) ω Lcrit α + sin α + π cos α = −½π + (12.17) R 1 + cos α It is important to note that converter circuits employing diodes cannot be used when inversion is required. Since the converter diodes prevent the output voltage from being negative, (and the current is unidirectional), regeneration from the load into the supply is not achievable.

Power Electronics

481

Chapter 12


Figure 12.1a is a fully controlled converter with an R-L load and freewheel diode. In single-phase circuits, this converter essentially behaves as a half-controlled converter.

Z = R 2 + (ωL ) and φ = tan−1 ωL 2

where

482

R

In the period π ≤ ωt ≤ π+α

v o (t ) = 0 = Ri + L

12.1.2 Single-phase, full-wave, half-controlled circuit with R-L and emf load, E

di +E dt

(12.22)

Solving gives

i (ωt ) = I 1e

Vs E is

o

io T1

∨

α

is

α

is

Vs

D4

D2

= I 1e

2π

π+α

io

tan φ

+

∨   2V  −ωt +π tan φ sin α  e sin φ − Z  cos φ 



T3 ωt

For continuous current, satisfying continuous and periodic boundary conditions  sin φ − α − e −α tan φ sin φ  ( )  2V   I = 1

Z

1−e

vo io

(a) (b)

α

π

tan φ

∨   −ωt +α tan φ −α 2V  e sin α   tan φ sin φ  + sin (ωt − φ ) −    sin (φ − α ) + e −π Z  1 − e tan φ  cos φ    

(12.24)

∨   −ωt +α tan φ 2V  e  sin φ − α + e −α tan φ sin φ  + e −ωt +α tan φ sin φ − sin α  )    (  −π Z  1 − e tan φ  cos φ    

(12.25)

i (ωt ) =

ωt

For π ≤ ωt ≤ π+α

VD4

o

−π

For α ≤ ωt ≤ π

E

E

o

(12.23)



∨

D2

vo

− ωt +α

 −ωt +π tan φ E  sin φ − e  2V  

α ≥ α and i (ωt = π ) > 0

D4

E

2V Z

π

π

T3

vo

+

ωt

T1

R

tan φ

E is

L

T3

− ωt +α

π+α

i (ωt ) =

2π

α

ωt VD2

Figure 12.2. Full-wave half-controlled converter with freewheel diodes and back emf: (a) circuit configurations and (b) circuit voltage and current waveforms and device conduction table.

Discontinuous conduction At ωt ≤ α equation (12.24) must be greater than zero for continuous conduction, that is sin (φ − α ) + e 1−e

In figure 12.2a, with a load back emf, current begins to flow when the supply instantaneous voltage exceeds the back emf magnitude E, that is when ∨

α = sin

−1

E

(V)

(12.19) (A)

The time domain solution for the load current has two components.

e

= I 1e

− ωt +α

tan φ

tan φ

+

tan φ

+ sin (α − φ ) −

∨

sin α ≥0 cos φ

−π

tan φ

sin (φ − α ) + e −π

−α

tan φ

sin φ

tan φ

∨

−

sin α ≥0 cos φ

(12.26)

Two discontinuous conduction conditions exist: i. The current is forced to ∨zero before load freewheeling, when E exceeds the instantaneous source voltage, that is π- α < β ≤ π ii. The current is forced to zero during load freewheeling, that is π < β ≤ π+α

I o = Vo − E R di +E dt

(12.20)

i. In the first case The average output voltage is

∨

Assuming continuous current conduction, using R = Z cosΦ and E = √2V sin α , which yields

i (ωt ) = I 1e

sin φ

In both cases average output current is

In the period α ≤ ωt ≤ π When current flows, Kirchhoff’s voltage law gives

− ωt +α

tan φ

1−e

2V (1 + cos α ) π α π ∨ V −E 2V = Io = o π R (1 + cos α − π sin α ) R

v o (t ) = 2V sin ωt = Ri + L

−α

That is

(12.18)

2V The average load voltage and current are given by 1 π Vo = ∫ 2 V sin(ωt ) d ωt =

−π

Vo =

2V  E  sin (ωt − φ ) −  Z  2V 

∨   2V  sin α  sin (ωt − φ ) − + Z  cos φ    ∨

α ≥ α and i (ωt = π ) > 0

β π +α  ∨ 1  ∫ 2V sin ωt d ωt + ∫ 2V sin α d ωt  π α π 

Vo = (12.21)

β ≤π

∨ 2V  − cos β + cos α + α sin α  π  

(12.27)

Hence

I o = Vo − E = 2V R πR

 − cos β + cos α + α − π sin α∨  ( )  

(12.28)

Power Electronics

483

The rms output voltage is 1 β Vo rms =  ∫ 2V sin ωt πα

(

) d ωt + ∫ 2

π +α

π

2  ∨    2V sin α  d ωt    

(12.29)

½ 2V ½ ( β − α ) + ¼sin 2α − ¼sin 2β + α  π 

=

E

o

is ∨

α

is

α

is

2π

π+α

ωt

o

π

is ∨

α

is

α

D4

D2 ωt

io

vo E

E

o

io

io α

π

io

(a)

βπ

π +α

β

2  2V sin α∨  d ωt       

∨ 2V  ½ (π − α ) + ¼sin 2α + (π + α − β ) sin2 α  π  

½

(12.35)

di +E dt

(12.36)

yielding

i (ωt ) = I o e

E

ωt

2


ωt

E α

) d ωt + ∫

(12.34)

For α ≤ ωt ≤ π

T3 D4

vo

o

β π+α

(

=

π

vo

(12.33)

1 + cos α + α − β sin α∨  ( )  

The rms output voltage is 1 π Vo rms =  ∫ 2V sin ωt πα

π+β

T1 D2

T3 D4

ωt

π

π vo

2π

π+α

β

T1 D2

β ≥π

∨ 2V  1 + cos α + (π + α − β ) sin α  π  

I o = Vo − E = 2V R πR

E

β

T3 D2

ii. In the second case: The average output voltage is π π +α  ∨ 1 Vo =  ∫ 2V sin ωt d ωt + ∫ 2V sin α d ωt  π  α β 

484

hence E

E


Vo =

Vs

Vs is

Chapter 12

π+α

ωt

(b)

Figure 12.3. Full-wave half-controlled converter with freewheel diodes and back emf during ∨ discontinuous conduction: (a) π- α < β ≤ π and (b) π < β ≤ π+α.

In each case the rms output current can be derived from the time current equations, which are used to find the current extinction angle β.

− ωt +α

tan φ

+

∨   2V  sin α  sin (ωt − φ ) − Z  cos φ 

  where a zero initial current boundary condition gives ∨   2V  sin α  Io = sin (φ − α ) + Z  cos φ    That is ∨ ∨    2V   sin α  −ωt +α tan φ sin α  + sin (ωt − φ ) − i (ωt ) = sin (φ − α ) + e  Z  cos φ  cos φ    

(12.37)

For π ≤ ωt ≤ β

For α ≤ ωt ≤ β ≤ π


di +E dt

(12.30)

   sin (ωt − φ ) − sin α   cos φ    where a zero initial current boundary condition gives ∨   2V  sin α  Io = sin (φ − α ) + Z  cos φ    That is ∨ ∨    2V   sin α  −ωt +α tan φ sin α  i (ωt ) = sin (φ − α ) + e + sin (ωt − φ ) − Z  cos φ  cos φ     − ωt +α

tan φ

+

2V Z

∨

At ωt = β ≤ π, i(β) = 0, that is β is found iteratively from ∨ ∨   − β +α sin α tan φ  sin (φ − α ) + sin α  e + sin ( β − φ ) =  cos φ  cos φ  

(12.31)

(12.32)

di +E dt

(12.38)

which yields

i (ωt ) = I 1e

which has the general solution

i (ωt ) = I o e

v o (t ) = 0 = Ri + L − ωt +π

∨

tan φ

−

2V sin α Z cos φ

where for continuous current at the boundary ∨    α −π 2V  sin α   I1 = sin φ + e tan φ  sin (φ − α ) +   Z  cos φ      That is ∨ ∨    − ωt +π 2V   sin α  −ωt +α tan φ sin α  tan φ sin (φ − α ) + sin φ − +e i (ωt ) = e cos φ  cos φ  Z     Equating to zero at the conduction extinction angle β gives ∨ ∨   − β +α − β +π sin α tan φ tan φ  sin (φ − α ) + sin α  e sin φ − +e =0  cos φ  cos φ   ∨    α π   sin (φ − α ) + sin α  e tan φ + e tan φ sin φ    cos φ     β = tan φ × n    ∨   sin α   cos φ  

(12.39)

(12.40)

(12.41)

Power Electronics

485

12.2

Chapter 12

Single-phase controlled thyristor converter circuits

12.2.1 Single-phase, half-wave controlled circuit with an R-L load The rectifying diode in the circuit of figure 11.1 can be replaced by a thyristor as shown in figure 12.4a to form a half-wave controlled rectifier circuit with an R-L load. The output voltage is now controlled by the thyristor trigger angle, α. The output voltage ripple is at the supply frequency. Circuit waveforms are shown in figure 12.4b, where the load inductor voltage equal areas are shaded. The output current, hence output voltage, for the series circuit are given by di (V) vo ( t ) = L + Ri = 2V sin ωt (12.42) dt (rad) α ≤ ωt ≤ β where phase delay angle α and current extinction angle β are shown in the waveform in figure 12.4b and are the zero load (and supply) current points. Solving equation (12.42) yields the load and supply current 2V i (ωt ) = {sin(ωt - φ ) - sin(α - φ )e(α - ωt ) / tan φ } Z where Z =

R 2 + (ω L) 2

Vo =

1 2π

∫

β

2 V sin ωt d ωt

α

(12.45)

2V (cos α − cos β ) 2π

Vo = Io R =

(V)

where the angle β can be extracted from figure 12.5a. The rms load voltage is β

(

2V

) sin ωt dωt  2

½

2

= V  12π {( β − α ) − ½(sin 2 β − sin 2α )}

(A)

(12.43)

486

The current extinction angle β is dependent on the load impedance and thyristor trigger angle α, and can be determined by solving equation (12.43) with ωt = β when i(β) = 0, that is sin( β - φ ) = sin(α - φ ) e(α - β ) / tanφ (12.44) This is a transcendental equation. A family of curves of current conduction angle versus delay angle, that is β - α versus α, is shown in figure 12.5a. The straight line plot for φ = ½π is for a purely inductive load, whereas ø = 0 is a straight line for a purely resistive load. The mean load voltage, whence the mean load current, is given by

Vrms =  12π ∫ α 

α ≤ ωt ≤ β

(ohms)


(12.46) ½

The rms current involves integration of equation (12.43), squared, giving ½

sin ( β − α ) cos(α + φ + β )   (12.47)   (β − α ) −   Z  2π  cos φ    Iterative solutions to equation (12.44) are shown in figure 12.5a, where it is seen that two straight-line relationships exist that relate α and β-α. Exact solutions to equation (12.44) exist for these two cases. That is, exact tractable solutions exist for the purely resistive load, Φ = 0, and the purely inductive load, Φ = ½π.

tan φ = ω L / R and i is zero elsewhere.

I rms =

V  1 

q =1 r =1 s =1 p=qxrxs p=1

(a) (a) straight line β=π-α

straight line β = π

π

⅓π

½π

(b)

vo

α

π

2π-α vL

Eqn (12.56)

√2V × Io Z

iL

vL 0

⅔π

ωt

vT

1/π

Eqn (12.49)

π

⅓π

½π

π

v (c)

Figure 12.4. Single-phase half-wave controlled converter: (a) circuit diagram; (b) circuit waveforms for an R-L load; and (c) purely inductive load.

Delay angle α (degrees)

Figure 12.5. Half-wave, controlled converter thyristor trigger delay angle α versus: (a) thyristor conduction angle, β-α, and (b) normalised mean load current.

Power Electronics

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Chapter 12

12.2.1i - Case 1: Purely resistive load. From equation (12.43), Z = R, φ = 0 , and the current is given by 2V i (ωt ) = sin(ωt ) (A) (12.48) R α ≤ ωt ≤ π and β = π ∀α The average load voltage, hence average load current, are Vo =

1 2π

∫

π

2V sin ωt d ωt

α

2V (1 + cos α ) 2π

Vo = I o R =

12.2.1iii - Case 3: Back emf E and R-L load. With a load back emf, current begins to flow when the supply instantaneous voltage exceeds the back emf magnitude E, that is when

π


(12.50)

(π − α ) + ½ sin 2α

(1 + cos α ) The supply power factor, for a resistive load, is Pout /Vrms Irms, that is

α

pf = ½ -

2π

+

sin 2α 4π

(12.51)

(12.52)

=

2V

ωL

( sin(ωt − ½π ) ( cos α

- sin (α -½π ) )

- cos ωt )

(A)

(12.54)

α ≤ ωt ≤ β and β = 2π − α

The average load voltage, based on the equal area criterion, is zero 1 2π

Vo =

∫

2π-α

2V sin ωt d ωt = 0

α

(12.55)

The average output current is I o = 12π ∫ =

2π −α

2 V

πω L

2 V

ωL

α

{cos α - cos ωt} d ωt

∨

The load power is given by 2 PL = I rms R + I oR while the supply power factor is given by

(

2V

)

∨

α −β α −β sin α   1 − e tan φ  − e tan φ sin (α − φ ) = 0 (12.65) cos φ   In the interval between β ≤ ωt ≤ 2π+α no current flows and the output voltage is the load back emf, E =

sin ( β − φ ) −

√2Vssin α . The average output voltage, hence current are given by β

∫ β

=

½

∫

α ½

(12.57)

2V sin ωt d ωt +

Vo =

2π +α

∫

E d ωt

β

2V sin ωt d ωt +

2π +α

∫

∨

2V sin α d ωt

β

∨ 2V  cosα − cos β + ( 2π + α − β ) × sin α  2π  

(12.66)

Therefore ∨

½

(12.58)

= V  {(π − α ) + ½ sin 2α )} Since the load is purely inductive, Po = 0 and the load voltage ripple factor is undefined since Vo = 0. 1π

∨

sin α (12.64) cos φ With discontinuous conduction, the output current is still given by equation (12.61), until the current falls to zero at the extinction angle β. The extinction angle β is found from the boundary condition i(ωt) = i(β) = 0, for 2π+α > β > ½π, in equation(12.61). That is, β is found iteratively from: sin (α − φ ) ≥

α

sin 2 ωt d ωt  

(12.63)

The boundary for continuous current conduction is when i > 0 at the end of the conduction period when ωt = 2π+α, that is ∨ ∨   sin α  sin α  −2π tan φ sin (α − φ ) − e − sin (α − φ ) − ≥0 cos φ  cos φ    That is, continuous conduction occurs when

=

Vrms =  12π ∫  α

I 2 R + I oR PL = rms V I rms V I rms ∨

Vo =

The rms output current is derived from ½ 2π −α 2 V 1 2 I rms = ( cos α - cos ωt ) dωt  2π ω L  ∫ α

2

(12.62)

The solution for the uncontrolled converter (a half-wave rectifier) is found by setting α = α , eqn (12.59).

 (π − α ) cos α + sin α 

2π −α

(12.61)

∨

(12.56)

3 V 1    (π − α )( 2 + cos 2α ) + sin 2α   X  π  2  The rms output voltage is

 −ωt +α tan φ  e 

α ≥ α and i (ωt = 2π + α ) > 0

pf =

12.2.1ii - Case 2: Purely inductive load. Circuit waveforms showing equal inductor voltage areas are shown in figure 12.4c. From equation (12.43), Z = ωL, φ = ½π , and the output voltage and current ares given by  2V sin ωt α ≤ ωt ≤ 2π − α (12.53) v o (ωt ) =  elsewhere 0 2V

(12.60) ∨

∨ ∨     2V  sin α  sin α  −ωt +α tan φ  sin (ωt − φ ) − − sin (α − φ ) − e  cos φ  cos φ  Z     

=

½

The output voltage form factor is

ωL

2V E  2V E sin (ωt − φ ) − −  sin (α − φ ) − Z R  Z R

2

Since the load is purely resistive, I rms = Vrms / R and the voltage and current factors (form and ripple) are 2 R. equal. The power delivered to the load is Po = Irms

V FFvo = rms = Vo

di +E dt

Assuming continuous current conduction, using R=ZcosΦ and E=√2Vssin α , which yields

½

2

α

(12.59)

2V When current flows, Kirchhoff’s voltage law gives

i (ωt ) =  ∫ ( 2 V ) sin ωt dωt  = V  12π {(π − α ) + ½ sin 2α )}

E

∨

α = sin−1

The rms output voltage is Vrms =  12π 

488

By setting α = 0, the equations (12.48) to (12.58) are valid for the uncontrolled rectifier considered in section 11.1.3, for a purely resistive and purely inductive load, respectively.

(12.49) (V)

where the maximum output voltage is 0.45V for zero delay angle.

i (ωt ) =


I o = Vo − E = Vo − 2V sin α R R ∨ I o = 2V 1 cos α − cos β + (π + α − β ) × sin α  R 2π  

(12.67)

Power Electronics

489

Example 12.1: Single-phase, half-wave controlled rectifier The ac supply of the half-wave controlled single-phase converter in figure 12.4a is v = √2 240 sinωt. For the following loads Load #1: R = 10Ω, ωL = 0 Ω Load #2: R = 0 Ω, ωL = 10Ω Load #3: R = 7.1Ω, ωL = 7.1Ω Determine in each load case, for a firing delay angle α = π/6 • • • •

the conduction angle γ=β - α, hence the current extinction angle β the dc output voltage and the average output current the rms load current and voltage, load current and voltage ripple factor, and power dissipated in the load the supply power factor

Solution Load #1: Z = R = 10Ω, ωL = 0 Ω From equation (12.43), Z = 10Ω and φ = 0° . From equation (12.48), β = π for all α, thus for α = π/6, γ = β - α = 5π/6. From equation (12.49) Vo = I o R =

=

2V (1 + cos π / 6) = 100.9V 2π

½

= 240V ×  12π {(π − π / 6 ) + ½ sin π / 3} = 167.2V ½

Since the load is purely resistive, the power delivered to the load is 2 Po = Irms R = Vrms2 / R = 167.2V 2 /10Ω = 2797.0W I rms = Vrms / R = 167.9V /10Ω = 16.8A For a purely resistive load, the voltage and current factors are equal: 167.2V 16.8A FFi = FFv = = = 1.68 100.9V 10.1A RFi = RFv = FF 2 − 1 = 1.32 The power factor is 2797W pf = = 0.70 240V × 16.7A Alternatively, use of equation (12.52) gives π /6 sin π /6 pf = ½ + = 0.70 2π 4π

Load #2: R = 0 Ω, Z = X = ωL = 10Ω From equation (12.43), Z = X =10Ω and φ = ½π . From equation (12.54), which is based on the equal area criterion, β = 2π - α, thus for α = π/6, β = 11π/6 whence the conduction period is γ = β – α = 5π/3. From equation (12.55) the average output voltage is Vo = 0V The average load current is

=

(π − α ) cos α + sin α  π ωL  2 V

2 240

π × 10

{

I rms =

240V  1 10Ω  π

}

{(π − π 6 ) ( 2 + cos 2α ) +

3

2 sin

π

}

½

 = 37.9A 3 

Since the load is purely inductive, the power delivered to the load is zero, as is the power factor, and the output voltage ripple factor is undefined. The output current ripple factor is I 37.9A FFi = rms = = 2.54 whence RFi = 2.542 − 1 = 2.34 14.9A Io Load #3: R = 7.1Ω, ωL = 7.1Ω From equation (12.43), Z = 10Ω and φ = ¼π . From figure 12.5a, for φ = ¼π and α = π / 6 , γ = β – α =195º whence β = 225º. Iteration of equation (12.44) gives β = 225.5º = 3.936 rad From equation (12.45) Vo = Io R =

2V (cos α − cos β ) 2π

2 × 240 (cos 30° − cos 225°) = 85.0V 2π

The average load current is Io = Vo / R

2V (1 + cos α ) = 100.9V/10Ω =10.1A. 2π R

Vrms = V  12π {(π − α ) + ½ sin 2α )}

490

Using equations (12.57) and (12.58), the load rms voltage and current are ½ 1  Vrms = 240V  π − π + ½ sin π  = 236.5V 6 3  π

=

The rms load voltage is given by equation (12.50), that is

Io =


2V (1 + cos α ) 2π

The average load current is I o = Vo / R =

Chapter 12

× ( 5π / 6 ) cos π / 6 + sin π / 6  = 14.9A

= 85.0V/7.1Ω = 12.0A Alternatively, the average current can be extracted from figure 12.5b, which for φ = ¼π and α = π / 6 gives the normalised current as 0.35, thus Io = 2V × 0.35 Z 2×240V = ×0.35 = 11.9A 10Ω

From equation (12.47), the rms current is I rms =

V  1 

  (β − α ) − Z  2π  

sin ( β − α ) cos(α + φ + β )     cos φ  

(

½

)

½

  sin 3.93 − π cos(π + ¼π + 3.93)   1 6 6   = 18.18A = ×   (3.93 − π ) −   6 10Ω 2π cos¼π     The power delivered to the load resistor is 2 Po = Irms R = 18.18A 2 × 7.1Ω = 2346W The load rms voltage, from equation (12.46), is 240V

Vrms = V  12π {( β − α ) − ½(sin 2 β − sin 2α )} = 240V  12π 

½

{( 3.94 − 16 π ) − ½ × (sin ( 2 × 3.94 ) − sin ( 2 × 16 π ))}

The load current and voltage ripple factors are 18.18A FFi = RFi = FFi 2 − 1 = 1.138 = 1.515 12.0A 175.1V FFv = RFv = FFv2 − 1 = 1.8 = 2.06 85V The supply power factor is pf =

2346W = 0.54 240V × 18.18A ♣

½

= 175.1V

Power Electronics

491

Chapter 12

The half-wave controlled converter waveform in figure 12.4b shows that when α < ωt < π, during the positive half of the supply cycle, energy is delivered to the load. But when π < ωt < 2π, the supply reverses and some energy in the load circuit is returned to the supply. More energy can be retained by the load if the load voltage is prevented from reversing. A load freewheel diode facilitates this objective. The single-phase half-wave converter can be controlled when a load commutating diode is incorporated as shown in figure 12.6a. The diode will prevent the instantaneous load voltage v0 from going negative, as with the single-phase half-controlled converters shown in figure 12.1. The load current is defined by equation 11.31 for α ≤ ωt ≤ π and equation 11.32 for π ≤ ωt ≤ 2π + α, namely: di L + Ri = 2 V sin ωt (A) α ≤ ωt ≤ π dt (12.68) di L + Ri = 0 (A) π ≤ ωt ≤ 2π + α dt At ωt = π the thyristor is line commutated and the load current, and hence freewheel diode current, is of the form of equation 11.33. As shown in figure 12.6b, depending on the delay angle α and R-L load time constant (L/R), the load current may fall to zero, producing discontinuous load current. The mean load voltage (hence mean output current) for all conduction cases, with a passive L-R load, is 1 2π

∫

π α

Vo = Io R =

2 V sin ω t d ω t 2V (1 + cos α ) 2π

492

∧

12.2.2 Single-phase, half-wave half-controlled

Vo =


(12.69) (V)

which is half the mean voltage for a single-phase half-controlled converter, given by equation (12.1). is

i

q =1 r =1 s =1 p=qxrxs p=1

The maximum mean output voltage, V o = 2V / π (equation 11.27), occurs at α = 0. The normalised mean output voltage Vn is ∧

Vn = Vo / V o = ½ (1 + cos α )

(12.70)

The Fourier coefficients of the 1-pulse output voltage are given by equation (12.128). For the singlephase, half-wave, half-controlled case, p = 1, thus the output voltage harmonics occur at n = 1, 2, 3, … The rms output voltage for both continuous and discontinuous load current is  ∫ ( 2 V ) sin ωt dωt  = V  12π {(π − α ) + ½ sin 2α )}

Vrms =  12π 

π

2

½

2

α

(12.71) ½

12.2.2i - For discontinuous conduction the load current is defined by equation (12.43) during thyristor conduction i (ω t ) = is (ω t ) =

(

)

2 V × sin(ωt − φ ) − sin α − φ e −ωt +α tanφ ( ) Z α ≤ ωt ≤ π

(A)

i (ω t ) = iDf (ω t ) = I 01π e −ωt / tan φ −π / tan φ   )  e −ωt +π / tan φ =  2 V × sin(φ − α ) (1 − e  Z   π ≤ ωt ≤ 2π + α The average thyristor current is V × ( cos 2 φ + cos α + sin φ × sin (α − φ ) × eα −π / tan φ ) IT = 2π R while the average freewheel diode current is V sin φ I Df = I o − I T = × ( sin φ − × sin (α − φ ) × eα −π / tan φ ) 2π R

(12.72) (A)

(12.73)

(12.74)

12.2.2ii - For continuous conduction the load current is defined by  sin φ e −α / tan φ − sin(α − φ ) −ωt +α tanφ  i (ω t ) = is (ω t ) = 2 V ×  sin(ωt − φ ) + ( )e  Z 1 − e −2π / tan φ  

α ≤ ωt ≤ π

(A)

i (ω t ) = iDf (ω t ) = I 01π e−ωt / tan φ

vo = v = vL+vR

vo = 0 = vL+vR

I o 1π R

vR

vL = vR v L for ωt > π

Figure 12.6. Half-wave half-controlled converter: (a) circuit diagram and (b) circuit waveforms for an inductive load.

sin φ − sin(α − φ ) e −π −α / tan φ  −ωt +π / tan φ  = 2V × e 1 − e −π / tan φ   Z

(12.75) (A)

π ≤ ωt ≤ 2π + α The advantages of incorporating a load freewheel diode are • the input power factor is improved and • the load waveform is improved (less ripple) giving a better load performance 12.2.3 Single-phase, full-wave controlled rectifier circuit with an R-L load Full-wave voltage control is possible with the circuits shown in figures 12.7a and b. The circuit in figure 12.7a uses a centre-tapped transformer and two thyristors which experience a reverse bias of twice the supply. At high powers where a transformer may not be applicable, a four-thyristor configuration as in figure 12.7b is suitable. The voltage ratings of the thyristors in figure 12.7b are half those of the devices in figure 12.7a, for a given converter input voltage. Load voltage and current waveforms are shown in figure 12.7 parts c, d, and e for three different phase control angle conditions. The load current waveform becomes continuous when the phase control angle α is given by α = tan −1 ω L / R = φ (rad) (12.76) at which angle the output current is a rectified sine wave. For α > ø, discontinuous load current flows as shown in figure 12.7c. At α = ø the load current becomes continuous as shown in figure 12.7d, whence β = α + π. Further decrease in α, that is α < ø, results in continuous load current that is always greater than zero (no zero current periods), as shown in figure 12.7e.

Power Electronics

493

Chapter 12

12.2.3i - α > φ , β - α < π , discontinuous load current The load current waveform is the same as for the half-wave situation considered in section 12.2.1, given by equation (12.43). That is 2V

i (ωt ) =

Z

[sin(ωt - φ ) - sin(α - φ ) e

{(α

- ωt ) / tan φ }

]

(A)

(rad) The mean output voltage for this full-wave circuit will be twice that of the half-wave case in section 12.2.1, given by equation (12.45). That is Vo = Io R = =

2V

π

π

∫

β α

2 V sin ωt

current, when α = ø; and (e) continuous load current.

Vrms =  π1 

(12.78) (V)

where β can be extracted from figure 12.5. For a purely resistive load, β = π. The average output current is given by I o = Vo / R and the average and rms thyristor currents are ½ I o and I rms / 2 , respectively.

∫

β α

2V 2 sin 2 ωt d ωt  

½

= V  1 {( β − α ) − ½(sin 2 β − sin 2α )}  π 

(12.79)

½

The rms load current is I rms =

d ωt

(cos α - cos β )

494

The rms load voltage is

(12.77)

α ≤ ωt < β

1


V 1 

  (β − α ) − Z  π  

sin ( β − α ) cos(α + φ + β )     cos φ  

½

(12.80)

2 R. The load power is therefore P = I rms

12.2.3ii - α = φ , β - α = π , verge of continuous load current When α = φ = tan -1 ω L / R , the load current given by equation (12.77) reduces to i (ωt ) =

Vo

q =2 r =1 s =1 p=qxrxs p=2

2V

sin(ωt − φ ) (A) (12.81) Z for φ ≤ ωt ≤ φ + π (rad) and the mean output voltage, on reducing equation (12.78) using β = α+π, is given by 2 2V cos α (V) Vo = (12.82) π which is dependent on the load such that α = φ = tan -1 ω L / R . From equation (12.79), with β − α = π , the rms output voltage is V, Irms = V/Z, and power = VI rms cos φ .

12.2.3iii - α < φ , β - π = α, continuous load current (and also a purely inductive load) Under a continuous load current conduction condition, a thyristor is still conducting when another is forward-biased and is turned on. The first device is instantaneously reverse-biased by the second device which has been turned on. The first device is commutated and load current is instantaneously transferred to the oncoming device. The load current is given by i (ωt ) =

2V Z

2 sin(α - φ )

[sin(ωt - φ ) -

1− e

− π / tan φ

e

{(α

- ωt ) / tan φ }

]

(12.83)

This equation reduces to equation (12.81) for α = φ and equation 11.52 for α = 0. The mean output voltage, whence mean output current, are defined by equation (12.82) 2 2V cos α (V) π ∧ which is uniquely defined by α. The maximum mean output voltage, Vo = 2 2 V / π (equation 11.54), occurs at α = 0. Generally, for α > ½π, the average output voltage is negative, resulting in a net energy transfer from the load to the supply. Vo = Io R =

The normalised mean output voltage Vn is ∧

Vn = Vo / Vo = cos α The rms output voltage is equal to the rms input supply voltage and is given by Vrms =

1

π

∫ ( π +α

α

2V

) sin ωt dωt 2

2

= V

(12.84) (12.85)

The ac in the output voltage is 2 V ac = V rms −Vo2 = V 1 +

8

π

cos 2 α

The ac component harmonic magnitudes in the load are given by 2V  1 1 2 cos 2α  × + − Vn =  2 2 2π  ( n − 1) ( n + 1) ( n − 1)( n + 1)  for n even, namely n = 2, 4, 6… The load voltage form factor, (thence ripple factor), is Figure 12.7. Full-wave controlled converter: (a) and (b) circuit diagrams; (c) discontinuous load current; (d) verge of continuous load

FFv =

π 2 2 cos α

(12.86)

(12.87)

(12.88)

Power Electronics

495

Chapter 12

The current harmonics are obtained by division of the voltage harmonic by its load impedance at that frequency, that is V Vn In = n = n = 0, 2, 4, 6,.. (12.89) 2 2 Zn R + ( nω L ) Integration of equation (12.83), squared, yields the load rms current (or equation 11.53 for α = 0) ½

   2sin (α − φ )   2sin (α − φ )  V  1  −2π / tan φ (12.90)  tan φ (1 − e ) − 4  1 − e−π / tan φ  sin α sin φ (1 − e−π / tan φ ) π +  − π / tan φ 1 Z π  e −        Thyristor average current is ½ I o , while thyristor rms current rating is I rms / 2 . The same thyristor current rating expressions are valid for both continuous and discontinuous load current conditions. 2

I rms =

For a highly inductive load, constant load current, the supply power factor is pf = 2 π (1 + cos α ) π π The harmonic factor or voltage ripple factor for the output voltage is

RFv =

2 V rms −Vo2  π 2  = − cos 2 α  Vo  8 

−α .

½

(12.91)

which is a minimum of 0.483 for α=0 and a maximum of 1.11 when α=½π. Critical load inductance (see figure 12.14) The critical load inductance, to prevent the load current falling to zero, is given by ω Lcrit π   2 2 = (12.92)  cos θ + π sin α − π cos α (½π + α + θ )  R 2 cos α   for α ≤ θ where V 2 cos α θ = sin −1 o = sin −1 (12.93) π 2V The minimum current occurs at the angle θ, where the mean output voltage Vo equals the instantaneous load voltage, vo. When the phase delay angle α is greater than the critical angle θ, substituting α = θ in equation (12.92) gives ω Lcrit = − tan α (12.94) R For a purely resistive load 2V Vo = (12.95) (1 + cos α ) .

π


Solution The load natural power factor angle is given by φ = tan -1 ω L / R = tan -1 ( 2π 50 × 50mH /10Ω ) = 57.5°=1 rad Continuous conduction Since α < φ ( 45° < 57.5° ) , continuous load current flows, which is given by equation (12.83). 2 × 240V 2 × sin(1.31 -1) [sin(ωt - 1) e 18.62Ω 1 − e−π / 1.56 = 18.2 × [sin(ωt - 1) - 1.62 × e - ωt / 1.56 ]

i (ωt ) =

{(1.31 - ωt ) / 1.56}

π

π

Io = Vo / R = 152.8V /10Ω = 15.3A Each thyristor conducts for 180°, hence thyristor mean current is ½ of 15.3A = 7.65A.

ii. The rms load current is determined by harmonic analysis. The voltage harmonics (peak magnitude) are given by equation (12.87) 2V  1 1 2 cos 2α  × + − for n = 2, 4, 6,.. Vn =   ( n − 1)2 ( n + 1)2 ( n − 1)( n + 1)  2π   and the corresponding current is given from equation (12.89) V Vn In = n = 2 2 Zn R + ( nω L )

V rms = I rms R = V  1 {(π − α ) − ½ sin 2α } π 

½

Vn

0

(152.79)

10.00

15.28

(233.44)

2

55.65

32.97

1.69

1.42

4

8.16

63.62

0.13

0.01

6

3.03

94.78

0.07

Z n = R 2 + ( nω L )

In =

2

Example 12.2: Controlled full-wave converter – continuous and discontinuous conduction The fully controlled full-wave, single-phase converter in figure 12.7a has a source of 240V rms, 50Hz, and a 10Ω 50mH series load. If the delay angle is 45°, determine i. the average output voltage and current, hence thyristor mean current ii. the rms load voltage and current, hence thyristor rms current and load ripple factors iii. the power absorbed by the load and the supply power factor If the delay angle is increased to 75° determine the load current in the time domain numerically solve the load current equation for β, the current extinction angle the load average current and voltage the load rms voltage and current hence load ripple factors and power dissipated the supply power factor

∑½I

½ I n2

0.00 2 n

=

234.4

The dc output voltage component is given by equation (12.82). From the calculations in the table, the rms load current is

I rms = I o2 + ½

∑I

2 n

= 234.4 = 15.3A

Since each thyristor conducts for 180°, the thyristor rms current is (12.97)

Vn Zn

harmonic n

I o2 +

π

iv. v. vi. vii. viii.

]

i. The average output current and voltage are given by equation (12.82) 2 2V 2 2V Vo = Io R = cos α = cos 45° = 152.8V

12.2.3iv Resistive load, β = π When the load is purely resistive, that is L = 0, the average and rms output voltage and currents are given by substituting Z = R and β = π in to equations (12.78), (12.79) and (12.80). That is 2V Vo = I o R = (12.96) (cos α + 1) (V)

496

1

2

of 15.3A = 10.8A

The rms load voltage is given by equation (12.85), that is 240V. I 15.3A = 1.0 FFi = rms = RFi = FFi 2 − 1 = 1.002 − 1 = 0.0 I o 15.3A V 240V FFv = rms = RFv = FFv2 − 1 = 1.57 2 − 1 = 1.21 = 1.57 V o 152.8V iii. The power absorbed by the load is 2 PL = I rms R = 15.3A 2 × 10Ω = 2344W The supply power factor is PL 2344W pf = = = 0.64 Vrms I rms 240V × 15.3A Discontinuous conduction iv. When the delay angle is increased to 75° (1.31 rad), discontinuous load current flows since the natural power factor angle φ = tan -1 ω L / R = tan -1 ( 2π 50 × 50mH /10Ω ) = 57.5° ≡ 1rad is exceeded. The load current is given by equation (12.77)

Power Electronics

497

2 × 240V [sin(ωt - 1) - sin(1.31 -1) e 18.62Ω = 18.2 × [sin(ωt - 1) - 0.71× e - ωt / 1.56 ]

i (ωt ) =

{(1.31 - ωt ) / 1.56}

Chapter 12

The load current is given by i (ωt ) =

for

for

2V sin ωt d ωt +

]

(12.102)

{(α

- β ) / tan φ }

=0

(12.103)

π +α

∫

E d ωt

π +α

∫

∨

2V sin α d ωt

β

2V π

Vo =

cos α − cos β + π + α − β × sin α∨  ( )  

2V   cos α − cos β + (π + α − β ) π 

   0 < β −α < π

Vo =

E

2V

(V)

(12.104) (rad)

The current extinction angle β is load-dependent, being a function of Z and E, as well as α. Since Vo = E + I o R , the mean load current is given by ∨

I o = Vo − E = Vo − 2V sin α R R Io =

∧

½π < α < π

∨

0< α < ½π

α ≤α ≤α (rad) The load circuit current can be evaluated by solving di 2 V sin ωt = L + Ri + E (V) dt The load voltage and current ripple are both at twice the supply frequency.

Vo − E R

=

2V

πR

E   (β − α )   cos α − cos β − 2V  

(A)

∨ I o = 2V 1 cos α − cos β + (α − β ) × sin α  R π   0 < β −α < π

(12.98)

(12.99)

Load current can always flow with a firing angle defined by ∨

- ωt ) / tan φ }

β

α

where it has been assumed the emf has the polarity shown in figure 12.8a. With discontinuous output current, load current cannot flow until the supply voltage exceeds the back emf E. That is (rad)

}

- cos φ sin(α - φ ) e

2V sin ωt d ωt +

∫

=

An emf source and R-L load can be encountered in dc machine modelling. The emf represents the machine speed back emf, defined by E = kφω . DC machines can be controlled by a fully controlled converter configuration as shown in figure 12.8a, where T1-T4 and T2-T3 are triggered alternately. If in each half sine period the thyristor firing delay angle occurs after the rectified sine supply has fallen below the emf level E, then no load current flows since the bridge thyristors will always be reversebiased. Thus the zero current firing angle α is:

)

E 2V

β

12.2.4 Single-phase, full-wave, fully-controlled circuit with R-L and emf load, E

(

{

α

viii. The supply power factor is PL 1836W pf = = = 0.56 Vrms I rms 240V × 13.55A ♣

∨

+

β

∫

Vo =

The load voltage and current form and ripple factors are I 13.55A = 1.49 FFi = rms = RFi = FFi 2 − 1 = 1.492 − 1 = 1.11 9.08A Io V 216.46V FFv = rms = RFv = FFv2 − 1 = 2.382 − 1 = 2.16 = 2.38 90.8V Vo The power dissipated in the 10Ω load resistor is 2 P = I rms R = 13.552 × 10Ω = 1836W

α = sin −1 E / 2V

{(α

∨

1  sin ( 4.09 − 1.31) × cos(1.31 + 1 + 4.09)   ×   ( 4.09 − 1.31) −   = 13.55A  π cos1    

(rad)

}

- cos φ sin(α - φ ) e

√2Vssin α . The average output voltage, hence current are given by

½

)

E 2V

In the interval between β ≤ ωt ≤ π+α no current flows and the output voltage is the load back emf, E =

Vrms = 240V ×  1 {(4.09 − 1.31) − ½(sin 8.18 − sin 2.62)} = 216.46V  π  The rms current from equation (12.80) is

2V

{

The mean output voltage can be obtained from equation (12.78), which is valid for E = 0.

½

(E /

E 2V

cos φ sin( β - φ ) -

vii. The rms load voltage is given by equation (12.79)

α = sin

+

(rad) For discontinuous load current conduction, the current extinction angle β, shown on figure 12.8b, is solved by iterative techniques for i(ωt=β) = 0 in equation (12.102).

π

−1

E 2V

[cos φ sin(ωt - φ ) -

α ≤ ωt ≤ β < π + α

V 90.8V Io = o = = 9.08A R 10Ω

240V

2V R

∨

vi. The average load voltage from equation (12.78) is 2 240V Vo = (cos 75° - cos 234.5°) = 90.8V

18.62Ω

498

12.2.4i - Discontinuous load current

]

v. Solving the equation in part iv for ωt = β and zero current, that is 0 = sin( β - 1) - 0.71× e - β / 1.56 gives β = 4.09 rad or 234.3°.

I rms =


(12.100) (12.101)

(12.105) (rad)

The rms output voltage is given by ½

2  2 β −α  β −α V 2  V π + E (1 − π ) − 2π (sin 2 β − sin 2α )    The rms voltage across the R-L part of the load is given by

Vrms =

2 VRLrms = Vrms − E2

(V)

(12.106)

(12.107)

The total power delivered to the R-L-E load is 2 Po = I rms R + IoE (12.108) where the rms load current is found by integrating the current in equation (12.102), squared, etc. The boundary for continuous current conduction is when i > 0 at the end of the conduction period when ωt = π+α, that is ∨ ∨   sin α  sin α  −π tan φ − sin (α − φ ) − − sin (α − φ ) − ≥0 e cos φ  cos φ    That is, continuous conduction occurs when sin (α − φ ) ≥

∨

 -½π  sin α × tanh   cos φ  tan φ 

(12.109)

With discontinuous conduction, the output current is still given by equation (12.61), until the current falls to zero at the extinction angle β. The extinction angle β is found from the boundary condition i(ωt) =

Power Electronics

499

Chapter 12

∨

α −β α −β  tan φ  tan φ sin (α − φ ) = 0 1 − e  −e  

q =2 r =1 s =1 p=qxrxs p=2

T1

T2

T3

T4

500

The load current is given by

i(β) = 0, for π+α > β > π, in equation(12.61). That is, β is found iteratively from: sin α sin ( β − φ ) − cos φ


(12.110)

i (ωt ) =

2V

Z

[sin(ωt - φ ) -

∨

2V

+2

sin(α - φ ) e e −π / tan φ − 1

{(α

- ωt ) / tan φ }

]

α ≤ ωt ≤ π + α

(12.111) (rad)

The periodic minimum current is given by ∨  ½π  E e −π / tan φ + 1 E 2V 2V (12.112) I= − = sin (α − φ ) −π / tan φ sin (α − φ ) tanh  − Z e Z −1 R  tan φ  R For continuous load current conditions, as shown in figures 12.8c and 12.8d, the mean output voltage is given by equation (12.104) with β = π − α Vo = π1 =

α

E

cos φ

∫

π +α

α

2 2V π

2 V sin ωt d ωt cosα

(= E + I R) o

(12.113)

(V)

  p π  = 2 V π sin p cos α    The average output voltage is dependent only on the phase delay angle α (independent of E), unlike the mean load current, which is given by V −E 2V  2 E  = Io = (A) (12.114)  cosα −  R R 2V  π The power absorbed by the emf source in the load is P = I o E , while the total power delivered to the R-L2 E load is Po = I rms R + IoE . The output voltage can be expressed as a Fourier series. o

α

∞

v o (t ) = Vo + 2V ∑ [an cos 2n ωt + bn sin 2n ωt ] n =1

∞   = 2V bo + ∑ [an cos 2n ωt + bn sin 2n ωt ] n =1   1 π 1 π 2 Vo = ∫ v o (t ) d ωt = ∫ 2V sin ωt d ωt = 2V cos α = 2V × bo

π

π

0

an =

π

0

(12.115)

2  cos ( 2n + 1 ) α cos ( 2n − 1 ) α  −   2n + 1 2n − 1 

π 

(12.116) 2  sin ( 2n + 1 ) α sin ( 2n − 1) α  − bn =   2n + 1 2n − 1 π   Each harmonic current can be found by dividing each harmonic current by its associated impedance, that is in = Vn / Zn where Zn = √R2 + (2nωL) 2. The output current and voltage ripple is at multiples of twice the supply frequency. The output voltage harmonic magnitudes for continuous conduction, given by equation (12.87), are 2V  1 1 2 cos 2α  Vn = for n = 2, 4, 6, .. (12.117) × + −  2 2 2π  ( n − 1) ( n + 1) ( n − 1)( n + 1)  The dc component across the R-L (and just the resistor) part of the load is Vo R−L = Vo − E (12.118) 2 2V = × cos α − E .

α

Figure 12.8. A full-wave fully controlled converter with an inductive load which includes an emf source: (a) circuit diagram; (b) voltage waveforms with discontinuous load current; (c) verge of continuous load current; and (d) continuous load current.

12.2.4ii - Continuous load current With continuous load current conduction, the load rms voltage is V.

π

The ac component of the output voltage is  2 2 cos α 2 2 −V o = 1−  Vac = Vrms  π  and the output voltage form factor is FFv =

π

  

2

(12.119)

(12.120) 2 2 cos α Thyristor average current is ½ I o , while thyristor rms current rating is I rms / 2 . These same two thyristor expressions are valid for both continuous and discontinuous load current conditions.

501

Power Electronics

Chapter 12

Critical load inductance


Example 12.3:

From equation (12.112) set to zero (or i = 0 in equation (12.111)), the boundary between continuous and discontinuous inductor current must satisfy  ½π  R E (12.121) sin (α − φ ) tanh   > Z 2V  tan φ  Inversion If the polarity of the back emf E is reversed as shown in figure 12.9a, waveforms as in parts b and c of figure 12.9 result. The emf supply can provide a forward bias across the bridge thyristors even after the supply polarity has gone negative. The zero current angle α now satisfies π < α < 3π/2, as given by equation (12.98). Thus load and supply current can flow, even for α > π. The relationship between the mean output voltage and current is now given by p π Vo = − E + I o R = 2 V sin cos α with p = 2 (12.122) p π That is, the emf term E in equations (12.98) to (12.121) is appropriately changed to - E. The load current flows from the emf source and if α > ½π, the average load voltage is negative. Power is being delivered to the ac supply from the emf source in the load, which is an energy transfer process called power inversion. In general 0 < α < 90° → Vo > 0 Po > 0 io > 0 rectification 90° < α < 180° → Vo < 0 Po < 0 io > 0 inversion

502

Single-phase, controlled converter – continuous conduction and back emf

The fully controlled full-wave converter in figure 12.7a has a source of 240V rms, 50Hz, and a 10Ω, 50mH, 50V emf opposing series load. The delay angle is 45°. Determine i. ii. iii. iv. v. vi.

the average output voltage and current the rms load voltage and the rms voltage across the R-L part of the load the power absorbed by the 50V load back emf the rms load current hence power dissipated in the resistive part of the load the load efficiency, that is percentage of energy into the back emf and power factor the load voltage and current form and ripple factors

Solution From example 12.2, continuous conduction is possible since α < φ

( 45° < 57.5° ) .

i. The average output voltage is given by equation (12.113) 2 2V cosα Vo = π

2 2 × 240

=

π

× cos45° = 152.8V

The average current, from equation (12.114) is V − E 152.8V − 50V Io = = = 10.28A R 10Ω o

T1

T2

T3

T4

ii. From equation (12.85) the rms load voltage is 240V. The rms voltage across the R-L part of the load is 2 VRLrms = Vrms − E2 = 240V 2 − 50V 2 = 234.7V q =2 r =1 s =1 p=qxrxs p=2

iii. The power absorbed by the 50V back emf load is P = I o E = 10.28A × 50V = 514W iv. The R-L load voltage harmonics (which are even) are given by equations (12.117) and (12.118): 2 2V × cos α − E Vo R−L = .

π

Vn =

α

2V 2π

 1 1 2 cos 2α  × + −   ( n − 1)2 ( n + 1)2 ( n − 1)( n + 1)   

for

n = 2, 4, 6,..

The harmonic currents and voltages are shown in the table to follow. harmonic

α

Z n = R 2 + ( nω L ) (Ω )

Vn

n 0

102.79

2

60.02

4

8.16

6

3.26

2

In =

Vn Zn

(A)

½ I n2

10.00

10.28

105.66

32.97

1.82

1.66

63.62

0.13

0.01

94.78

0.04

I o2 +

∑ ½ I n2 =

From the table the rms load current is given by

I rms = I o2 + ½ Figure 12.9. A full-wave controlled converter with an inductive load and negative emf source: (a) circuit diagram; (b) voltage waveforms for discontinuous load current; and (c) continuous load current.

∑I

2 n

= 107.33 = 10.36A

The power absorbed by the 10Ω load resistor is 2 PL = I rms R = 10.36A 2 × 10Ω = 1073.3W v. The load efficiency, that is, percentage energy into the back emf E is

0.00 107.33

Power Electronics

503

η=

514W × 100 o o = 32.4 o o 514W + 1073.3W

The power factor is pf =

PL 514W+1073.3W = = 0.64 240V × 10.36A Vrms I rms

vi. The output performance factors are I 10.36A = 1.011 FFi = rms = RFi = FFi 2 − 1 = 1.0232 − 1 = 0.125 I o 10.28A V 240V FFv = rms = RFv = FFv2 − 1 = 1.57 2 − 1 = 1.211 = 1.57 V o 152.8V Note that the voltage form factor (hence voltage ripple factor) agrees with that obtained by substitution into equation (12.120), 1.57. ♣

Chapter 12


504

Then the line to line voltage phase a to phase b is v ab = v a − v b = 2V sin ωt − 2V sin (ωt − 120° ) = 2V sin ωt − ½ 2V sin ωt −

3 2V cos ωt 2

= 3 2V sin (ωt + 30° ) = 3 2V sin (ωt + 1 6 π )

R-L

Example 12.4: Controlled converter – constant load current, back emf, and overlap The fully controlled single-phase full-wave converter in figure 12.7a has a source of 230V rms, 50Hz, and a series load composed of ½Ω, infinite inductance, 150V emf non-opposing. If the average load current is to be 200A, calculate the delay angle assuming the converter is operating in the inversion mode, taking into account 1mH of commutation inductance.

q =3 r =1 s =2 p=qxrxs p=6

Solution The mean load current is

Io = 200A =

V o (α ) − E R Vo (α ) − −150V

½Ω which implies a load voltage Vo(α) = -50V. The output voltage is given by equation (12.82) Vo = 2 π2 V cos α . Commutation of current from one rectifier to the other takes a finite time. The effect of commutation inductance is to reduce the output

voltage, thus according to equation (12.194), the output voltage becomes

Vo =

2V sin π n cos α − n ω Lc I o / 2π π /n

where n = 2

2 × 230V × cos α − 2 × 50Hz × 1mH × 200A π /2 = 207V × cos α − 20V which yields α = 98.3º. The commutation overlap causes the output voltage to reduce to zero volts and the overlap period γ is given by equation (12.195) −50V =

Io =

2V

2π f Lc

( cos α − cos (γ + α ) )

2 230V ( cos 93.8° − cos (γ + 93.8° ) ) 2π 50Hz × 1mH This gives an overlap angle of γ = 11.2º. ♣ 200A =

12.3

Three-phase half-controlled converter

Assuming three phase voltages Van = v a = V ∠0° = V sin ωt

V bn = v a = V ∠ − 120° = V sin (ωt − 120° ) Vcn = v a = V ∠ + 120° = V sin (ωt + 120° )

Figure 12.10. Three-phase half-controlled bridge converter: (a) circuit connection; (b) voltage and current waveforms for a small firing delay angle α; and (c) waveforms for α large.

Power Electronics

505

Chapter 12

The three-phase line input voltages are: v ab = V max sin (ωt + 1 6 π )

12.4

v bc = V max sin (ωt − ½π )

(12.123)

v ca = V max sin (ωt + ½π )


Three-phase, controlled thyristor converter circuits

The three-phase line input voltages are: v ab = V max sin (ωt + 1 6 π )

v bc = V max sin (ωt − ½π )

Figure 12.10a illustrates a half-controlled (semi-controlled) converter where half the devices are thyristors, the remainder being diodes. As in the single-phase case, a freewheeling diode can be added across the load so as to allow the bridge thyristors to commutate and decrease freewheeling losses. The output voltage expression consists of √2V 3√3/2π due to the uncontrolled half of the bridge and √2V 3√3 × cos α /2π due to the controlled half which is phase-controlled. The half-controlled bridge mean output is given by the sum, that is 3 3 3 Vo = 2 V (1 + cos α ) = 2 VL (1 + cos α ) 2π 2π = 2.34V (1 + cos α ) (V) (12.124) 0 ≤ α ≤ 23π (rad) Vo = I o R At α = 0, V o = √2 V 3√3/π = 1.35 VL, as in equation (11.93). The normalised mean output voltage Vn is Vn = Vo / V o = ½(1 + cos α )

506

(12.129)

v ca = V max sin (ωt + ½π ) 12.4.1 Three-phase, fully-controlled, half-wave circuit with an inductive load When the diodes in the circuit of figure 11.10 are replaced by thyristors, as in figure 12.11a, a threephase fully controlled half-wave converter results. The output voltage is controlled by the delay angle α. This angle is specified from the thyristor commutation angle, which is the earliest point the associated thyristor becomes forward-biased, as shown in parts b, c, and d of figure 12.11. (The reference is not the phase zero voltage cross-over point). The thyristor with the highest instantaneous anode potential will conduct when fired and in turning on will reverse bias and turn off any previously conducting thyristor. The output voltage ripple is three times the supply frequency and the supply currents contain dc components. Each phase progressively conducts for periods of π, displaced by α, as shown in figure 12.11b.

(12.125)

The diodes prevent any negative output, hence inversion cannot occur. Typical output voltage and current waveforms for a highly inductive load (constant current) are shown in figure 12.10b.

q =3 r =1 s =1 p=qxrxs p=3

12.3i - α ≤ ⅓π When the delay angle is less than ⅓π the output waveform contains six pulses per cycle, of alternating controlled and uncontrolled phases, as shown in figure 12.10b. The output current is always continuous (even for a resistive load) since no output voltage zeros occur. The rms output voltage is given by 2 2 α + 2π / 3 3 2π / 3 Vrms = 2VL sin 2 ωt d ωt + ∫ 2VL sin 2 ωt d ωt π /3 2π ∫α +π / 3

{

(

)

(

 3 3  = VL  1 + (1 + cos 2α )   π 4  

)

}

½

(12.126) for 0 ≤ α ≤ π / 3

12.3ii - α ≥ ⅓π For delay angles greater than ⅓π the output voltage waveform is made up of three controlled pulses per cycle, as shown in figure 12.10c. Although output voltage zeros result, continuous load current can flow through a diode and the conducting thyristor, or through the commutating diode if employed. The rms output voltage is given by 2 3 π Vrms = 2 VL sin 2 ω t d ωt 2π ∫α

(

)

½

 3 = VL  (π − α + ½ sin 2α )   2π 

(12.127) for α ≥ π / 3

The Fourier coefficients of the p-pulse output voltage are given by cos ( n + 1) α cos ( n − 1) α  2V  −2 an = − +   2π  n 2 − 1 n +1 n −1  p

bn =

2V  sin ( n + 1) α sin ( n − 1) α  −   2π  n +1 n −1  p

(12.128)

where n = mp and m = 1, 2, 3, .. For the three-phase, full-wave, half-controlled case, p = 6, thus the output voltage harmonics occur at n = 6, 12, …

Figure 12.11. Three-phase half-wave controlled converter: (a) circuit connection; (b) voltage and current waveforms for a small firing delay angle α; (c) and (d) load voltage waveforms for progressively larger delay angles.

The mean output voltage for an n-phase half-wave controlled converter is given by (see example 12.7) 2 V α +π / n cos ωt d ωt Vo = 2π / n α −π / n (12.130) sin(π / n ) cos α (V) = 2V π /n

∫

Power Electronics

507

Chapter 12

which for the three-phase circuit considered with continuous or discontinuous (R) load current gives 3 3 Vo = Io R = (12.131) 0 ≤α ≤π /6 2 V cos α = 1.17 V cos α 2π For discontinuous conduction, and a resistive load, the mean output voltage is 3 Vo = Io R = 2 V (1 + cos (α + π / 6 ) ) π / 6 ≤ α ≤ 5π / 6 (12.132) 2π The mean output voltage is zero for α = ½π. For 0 < α < π, the instantaneous output voltage is always greater than zero. Negative average output voltage occurs when α > ½π as shown in figure 12.11d. Since the load current direction is unchanged, for α > ½π, power reversal occurs, with energy feeding from the load into the ac supply. Power inversion assumes a load with an emf to assist the current flow, as in figure 12.9. If α > π no reverse bias exists for natural commutation and continuous load current will freewheel. The maximum mean output voltage V o = √2V 3√3 /2π occurs at α = 0. The normalised mean output voltage Vn is Vn = Vo / Vˆo = cos α (12.133) With an R-L load, at Vo = 0, the load current falls to zero. Thus for α > ½π, continuous load current does not flow for an R-L load. The rms output voltage (for inductive and resistive loads) is given by 2 3 α +π / 3 2 Vrms = 2 V sin (ωt ) d ωt 2π ∫ α −π / 3

(

)

½

3 3 sin 2α  0 ≤ α ≤ 5π / 6 = V  1 + 4π   From equations (12.131) and (12.134), the ac in the output voltage is 2 Vac = V rms −Vo2 = V  1 +

 The output voltage distortion ripple factor is

RFv = 12.4.2

2π 2 27

+

3π 18

sin 2α − cos2 α

3 3 4π

sin 2α −

9

π

(min ( at α =0 ) = 0.173; max ( at α =½π ) = 0.66)

508

The maximum mean output Vo = √2V 3√3/2π occurs at α = 0. The normalised mean output voltage, Vn is given by Vn = Vo / V o = cos α (12.138) The Fourier coefficients of the 3-pulse output voltage are given by (12.128). For the three-phase, halfwave, half-controlled case, p = 3, thus the output voltage harmonics occur at n = 3, 6, 9, …

12.4.2ii - α > π/6. Because of the freewheel diode, voltage zeros occur and the negative portions in the waveforms in parts c and d of figure 12.11 do not occur. The mean output voltage is given by 2V π sin ωt d ωt Vo = Io R = 2π / 3 ∫ α −π / 6 2V = (V) (12.139) (1 + cos (α + π / 6 ) ) 2π / 3 π / 6 ≤ α ≤ 5π / 6 The normalised mean output voltage Vn is Vn = Vo / V o = [1 + cos(α + π / 6)]/ 3 The average load current (with an emf E in the load) is given by V −E Io = o R These equations assume continuous load current.

(12.140) (12.141)

(12.134)

12.4.2iii - α > 5π/6. A delay angle of greater than 5π/6 would imply a negative output voltage, clearly not possible with a freewheel load diode.

(12.135)

Example 12.5: Three-phase half-wave rectifier with freewheel diode

(12.136)

The half-wave three-phase rectifier in figure 12.12 has a three-phase 415V 50Hz source (240V phase), and a 10Ω resistor and infinite series inductance as a load. If the delay angle is 60º determine the load current and output voltage if: i. the phase commutation inductance is zero ii. the phase commutation reactance is¼Ω

½

cos 2 α  


Three-phase, half-wave converter with freewheel diode

Figure 12.12 shows a three-phase, half-wave controlled rectifier converter circuit with a load freewheel diode, Df. This diode prevents the load voltage from going negative, thus inversion is not possible.

q =3 r =1 s =1 p=qxrxs p=3

Solution i. The output voltage, without any line commutation inductance and a 60º phase delay angle, is given by equation (12.139)

Vo = I o R =

2V

2π / 3

(1 + cos (α + π / 6 ) )

2 240 V (1 + cos ( 60° + π / 6 ) ) = 162V 2π / 3 The constant load current is therefore V 162V = 16.2A Io = o = 10Ω R

=

Df

Figure 12.12. A half-wave fully controlled three-phase converter with a load freewheel diode.

12.4.2i - α < π/6. The output is as in figure 12.11b, with no voltage zeros occurring. The mean output voltage (and current) is given by equation (12.131), that is 3 3 Vo = Io R = (12.137) 2V cos α = 1.17V cos α (V) 0 ≤α ≤π /6 (rad) 2π

ii. When the current changes paths, any inductance will control the rate at which the commutation from one path to the next occurs. The voltage drops across the commutating inductors modifies the output voltage. Since the voltage across the freewheel diode is not associated with commutation inductance, the output voltage is not effected when the current swaps from a phase to the freewheel diode. But when the current transfers from the diode to a phase, while the commutation inductance current in the phase is building up to the constant load current level, the output remains clamped at the diode voltage level, viz. zero. The average voltage across the load during this overlap period is therefore reduced. The commutation current is defined by

di c di c = Xc dt d ωt  2V  π  ic =  cos  α +  − cos ωt  Xc  6   2V sin ωt = Lc

Power Electronics

509

Chapter 12

Solving for when the current rises to the load current I oγ gives 2V  π π    I oγ =  cos  α +  − cos  α + + γ   Xc  6 6   


510

q =3 r =1 s =2 p=qxrxs p=6

but

Io = γ

Voγ 2V = (1 + cos (α + π / 6 + γ ) ) R R 2π / 3

Xc π  cos  α +  − π 6  R 2π / 3    = cos  α + + γ  Xc 6   +1 R 2π / 3 Xc   π   cos  α +  −  π 6  R 2π / 3     γ = cos − α +  = 0.68° Xc    6 1 +   R 2π / 3   The load current and voltage are therefore 2V  π π 2 240V    I oγ = ( cos ( 90° ) − cos ( 90.68 ) ) = 16.11A  cos  α +  − cos  α + + γ   = Xc  ¼Ω 6 6    −1

Voγ = I oγ R = 16.11A × 10Ω = 161.1V ♣ 12.4.3 Three-phase, full-wave, fully-controlled circuit with an inductive load A three-phase bridge is fully controlled when all six bridge devices are thyristors, as shown in figure 12.13a. The frequency of the output ripple voltage is six times the supply frequency and each thyristor always conducts for ⅔π. Circuit waveforms are shown in figure 12.13b. The output voltage is continuous, and the mean output voltage for both inductive and resistive loads is given by 3 α +½ π Vo = ∫ 3 2 V sin (ω t + π / 6 ) d ω t

π

=

α +π / 6

3 3

π

2 V cos α = 2.34 V cos α

(12.142)

(V)

0 ≤ α ≤ 2π / 3 which is twice the voltage given by equation (12.131) for the half-wave circuit, but for a purely resistive load the output voltage is discontinuous and equation (12.142) becomes Vo =

3

π

Vmax 1 + cos (α + π / 6 ) =

3 3

2 V 1 + cos (α + π / 6 )

π

(V)

(12.143)

π / 3 ≤ α ≤ 2π / 3

Vn = Vo / V o = cos α

(12.145)

For delay angles up to ⅓π, the output voltage is at all instances non-zero, hence the load current is continuous for any passive load (both resistive and inductive). Beyond ⅓π the load current may be discontinuous (always discontinuous for a resistive load). For α > ½π the current is always discontinuous for passive loads (no back emf, E) and the average output voltage is less than zero For continuous load current, the load current is given by 3 2V

Z

(

sin ωt + π

6

)

−φ −

E R

+

3 2V

Z

The maximum and minimum ripple current magnitudes are I =

The average output current is given by I o = Vo / R in each case. If a load back emf exists the average current becomes Vo − E (12.144) Io = R The maximum mean output voltage V o = √2V 3√3/π occurs at α = 0. The normalised mean output Vn is

i ( ωt ) =

Figure 12.13. A three-phase fully controlled converter: (a) circuit connection and (b) load voltage waveform for four delay angles.

3 2V

Z

(

sin α + π

)

−φ −

2

E R

+

3 2V

Z

e

sin (α − φ )

e

−

π 6

π 3

tan φ

(12.147) tan φ

−1

at ωt = α +nπ for n = 0, 6, 12, .. ∨

I =

3 2V

Z

(

sin α + π

)

−φ −

3

E R

+

3 2V

Z

1

sin (α − φ )

e

−

π 3

tan φ

(12.148) −1

at ωt = α - π +n π for n = 0, 6, 12, .. ∨

With a load back emf the critical inductance for continuous load current must satisfy I = 0 in equation (12.148), that is sin (α − φ )  R  E × sin (α − φ + 13 π ) + −π / 3 tan φ (12.149) ≥ −1 Z  e 3 2V where tan φ = ω L / R . The rms value of the output voltage for an inductive and purely resistive load is given by

sin (α − φ )

e e

− ωt + π 6 + α

− π 3 tan φ

tan φ

−1

(12.146)

3 Vrms =  π

∫

α +π / 2 α −π / 6

3

(

= 3 2V ½ +

2V

½

) sin (ωt ) dωt 

3 3 4π

2

2

cos 2α

0 ≤α ≤ π /3

(12.150)

Power Electronics

511

Chapter 12

but for a purely resistive load Vrms = 3 2 V 1 −

3α 2π

−

3 4π

sin ( 2α − π / 3)

π / 3 ≤ α ≤ 2π / 3

(12.151)

The output voltage ripple factor (with continuous current) is π

RFv =

2

18

3π

+

12

(min ( at α =0 ) = 0.025; max ( at α =½π ) = 0.3)

cos 2α − cos 2 α

(12.152)

The normalise voltage harmonic peak magnitudes in the output voltage, with continuous load current, are VL n = 2 V .

3 3 1 1 2 cos 2α  + −   π  ( n − 1)2 ( n + 1)2 ( n − 1)( n + 1) 

1 2

(12.153)

.

for n = 6, 12, 18… The harmonics occur at multiples of six times the fundamental frequency. For discontinuous load current, at high delay angles, when the output current becomes discontinuous with an inductive load, the output current is given by

i (ωt ) =

(

3 2V  sin ωt + π



Z

6

)

(

− φ − sin α + π

3

)

−φ e

− ωt − π 6 + α

 − E 1 − e −ωt −π 6 +α tan φ   R   α ≤ ωt ≤ α + θc

tan φ

(12.154)

where θc is the conduction period, which is found by solving the transcendental equation formed when in equation (12.154), i(ωt = α+π+θc) = 0. The average output voltage can then be found from

(

3 3 2V  cos α + π

Vo =

π



3

) − cos (α + π 3 + θ ) − 3πE π 3 − θ  c

(12.155)

c

delay angle α 20°

30°

¼π

60°

an =

cos ( n + 1) α cos ( n − 1) α  2V  −2 − −   2π  n 2 + 1 n +1 n −1   p

bn =

2V  sin ( n + 1) α sin ( n − 1) α  −   2π  n +1 n −1  p

70°

80°

½π°

512

(12.156)

for n = pm and m = 1, 2, 3, .. The harmonics occur at multiples of six times the fundamental frequency, for a 6 - pulse (p = 6) per cycle output voltage. 12.4.3ii - Highly inductive load – constant load current As with a continuous load current, with a constant load current the input current comprises ⅔π alternating polarity blocks of current, with each phase displaced relative to the others by ⅔π, independent of the thyristor triggering delay angle. At maximum voltage hence maximum power output, the delay angle is zero and the phase voltage and current fundamental are in phase. As the phase angle is increased, the inverter output voltage, hence power output is decreased, and the line current block of current (fundamental) shifts by α with respect to the line voltage. Reactive input power increases as the real power decreases. At α = ½π, the output voltage reduces to zero, the output power is zero, and the ⅔π current blocks in the ac input are shifted ½π with respect to the line voltage, producing only VAr’s from the ac input. When the delay angle is increased above ½π, the inverter dc output reverses polarity and energy transfers back into the ac supply (inversion), with maximum inverted power reached at α = π, where the reactive VAr is reduced to zero, from a maximum at α = ½π. For a highly inductive load, that is a constant load current I o : the mean diode current is I Th = 1n I o = and the rms diode current is ITh rms = 1 n I o rms ≈

fully-controlled converter 0


1

3 Io

1

n Io

(12.157)

(A)

=

1

3

Io

(A)

The diode current form factor is FFITh = ITh rms / I Th = 3

(12.158) (12.159)

The diode current ripple factor is

RF ITh = FF ITh2 − 1 = 2

10 Single-phase 2 pulse

ω Lcrit / R

5

sing

le -ph

as e

full

ntr y -co

I L rms =

single-phase 1

1

0.8

0.05

thre e

0

30°

-pha

¼π

se fu

0.6 on lly-c

60°

trolle

0.2

0.4

←

d

0

per unit dc output voltage Vo

Three-phase 6 pulse

75°

½π

105°

(12.161)

v a = 2 V sin ωt with phases b and c shifted by ⅔π. That is substitute ωt with ωt±⅔π.

three-phase

0.1

2 I o rms = 0.816 I o rms 3

A phase voltage is given by

Semi-controlled

0.5

(12.160)

The rms input line currents are

olle d

120°

¾π

150°

π

delay angle α semi-controlled converter

Figure 12.14. Critical load inductance (reactance) of single-phase (two pulse) and three-phase (six pulse), semi-controlled and fully-controlled converters, as a function phase delay angle α whence dc output voltage Vo. For rectifier, α = 0.

The line current ia is given by 1 1 1 sin 7ωt + sin11ωt + sin13ωt 7 11 13 1 1 − sin17ωt − sin19ωt + .....) 17 19 where Φ1 is the angle between the supply va and the fundamental line current ia1. From Fourier coefficients of the line current harmonics are 2π 1 an = ∫ i i (t ) cos n ωt d ωt

i a (ωt − φ1 ) =

2 3

π

1 5

I o (sin ωt − sin 5ωt −

π

For a resistive load, the load voltage harmonics for p pulses per cycle, are given by

(12.163)

0

11π +α  5π + α  6 16 I cos n ωt d ωt − ∫ I o cos n ωt d ωt  = o ∫  π π 7π +α  6 +α  6

=−

12.4.3i - Resistive load

(12.162)

4I o

nπ

sin

nπ 3

sin n α

n = 1, 3, 5, … odd

(12.164)

Power Electronics

513

1

bn =

π

2π

∫i

s

(t ) sin n ωt d ωt

0

11π +α  5π + α  6 16 =  ∫ I o sin n ωt d ωt − ∫ I o sin n ωt d ωt  π π 7π +α  6 +α  6

=

4I o

sin

nπ

cos n α

π

2

I 1rms = 3

(12.165)

n = 1, 3, 5, … odd

3 nπ The input line current, which has no dc component (an = 0), is ∞ 4I o nπ i i (t ) = ∑ sin sin(n ωt − n α ) 3 n =1,3,5,… n π The fundamental input current and rms are 2 3 Io I i 1 (t ) = sin(ωt − α ) = 2 I 1rms sin(ωt − α )

where

Chapter 12

(12.166)

(12.167)

Io

2 I o cos α 3 Vrms 3 3 Vrms I1rms cos α 3 π = = cos α = 0.995cos α (12.168) π 2 2 Io Io 3 Vrms × 3 Vrms × 3 3 where cosα is the displacement factor, DF, the cosine of the angle between the fundamental input voltage and current, Φ1, as given in equation (12.167). The supply fundamental apparent power, S1, active power P and reactive power Q, are given by pf =

2

π

Io =

3 2V

π

I o = Pd2 + Qq2

Pd = P1 = S max cos α Qq = Q1 = S max sin α

(12.169) where Pmax =

3 2V

π

I o = Q max = S max

The apparent power drawn by the 6-pulse converter, for a constant load current is S d = Pd + j Qd = S max ( cos α + j sin α )

514

The supply apparent power is constant for a given constant load current, independent of the thyristor turn-on delay angle. Maximum power is drawn for zero delay angle, while maximum apparent power is drawn at α = ½π. Diving equation (12.170) by S1 gives the system power locus in per unit. The semicircle shown in figure 12.15 with centre ‘0’ and a radius of 1 pu is the P-Q locus of the 6-pulse converter obtained by varying α from 0 to π in equation (12.170). The pu output voltage is cosα. The supply power factor, equation (12.168), is defined as the ratio of the supply power delivered P, to apparent supply power S, 3 P I DPF pf = = s 1 cos α = cos α = DF × DPF = (12.171) S Is π 1 + THD 2 where DPF = cosα = cosΦ1, DF = 3/π, and the total harmonic input current distortion, THD, from equations (12.161) and (12.167) is 2 I s2 − I s21 I s2 π  = − 1 =   − 1 = 0.311 2 I s1 I s1 3

THD =

π The power factor for a constant load current is

S 1 = 3VI 1rms = 3V


(12.172)

The dc-side voltage harmonics of the 6-pulse converter are generated at 6n times the fundamental line frequency. The output voltage, Vo, can be expressed as a Fourier series (see equation (12.153)): ∞  3 2VL  1 1 2 cos 2α  cos α + ∑ sin ( 6n ωt + λ6n )  Vo = (12.173) + + 2 2 2  π  n =1 6 1 6 1 6 1 6 1 n n n n − + − + ( ) ( ) ( )( )   where  cos ( 6n + 1) α cos ( 6n − 1) α  −   6n + 1 6n − 1 λ6n = −n π + tan−1   n n α α sin 6 1 sin 6 1 + − ( ) ( )   −   6n + 1 6n − 1 Undesirably, if triggering pulses to all the thyristors are removed, the dc current decays slowly and uncontrolled to zero through the last pair of thyristors that were triggered. Converter shut down is best achieved regeneratively by increasing (and controlling) the delay angle to greater than ½π such that the output voltage goes negative, which results in controlled power inversion back into the ac supply. Series and parallel connection of fully-controlled, phase-shifted converters is considered in Chapter 19, in relation to HVDC transmission. 12.4.3iii - R-L load with load EMF, E

(12.170)

The load current during the interval α ≤ ωt ≤ α+⅓π is defined by

Ri + L

di + E = 2VL sin (ωt + 1 3 π ) dt

(12.174)

which yields

i (t ) =

∨ − ωt +α   2VL  sin (φ − α ) tan φ sin α  e + sin (ωt + 1 3 π − φ ) − −π  cos φ Z   1 − e 3 tan φ 

where Z = R 2 + ω 2L2 ;

tan φ = ωL / R ;

(12.175) ∨

R = Z cos φ ; and E = 2VL sin α .

Example 12.6: Three-phase full-wave controlled rectifier with constant output current The full-wave three-phase controlled rectifier in figure 12.13a has a three-phase 415V 50Hz source (240V phase), and provides a 100A constant current load. Determine: i. the average and rms thyristor current ii. the rms and fundamental line current iii. the apparent fundamental power S1 If 25kW is delivered to the dc load, calculate:

Figure 12.15. Power locus of 6-pulse converter and per unit output voltage.

iv. iv. v. vi.

the supply power factor the dc output voltage, load resistance, hence the converter phase delay angle the real active and reactive Q1 ac supply power the delay angle range if the ac supply varies by ±5% (with 25kW and 100A dc).

Power Electronics

515

Chapter 12

Solution i.

ii.

1

3

Io =

1

3

× 100A = 57.7A

The rms and fundamental line currents are 2 2 I L rms = I o rms = × 100A = 81.6A 3 3 2 2 I1rms = 3 Io = 3 × 100A = 78.0A

π

516

q =3 r =1 s =2 p=qxrxs p=6

From equations (12.157) and (12.158) the thyristor average and rms currents are I Th = 1 3 I o = 1 3 × 100A = 33 1 3 A

I Th rms =


ia

π

(a)

iii.

The apparent power is

S 1 = 3VI 1rms = 3 × 415V × 78A = 56.1kVA iv.

The supply power factor, from equation (12.168), is PL 25kW  3  pf = = = 0.426  = π cos α  3 Vrms I rms 3 × 415V × 81.6A  

v.

The output voltage is Vo = power = 25kW

Io

T4 /D4

= 250V dc α

α

2π

o

The load resistance is

RL =

T2 /D2

vbc

vbc

100A

T6 /D6

1 π

Vo 250V = = 2.5Ω I o 100A

2π

o ωt

ωt

π

π

π

Thyristor delay angle is given by equation (12.142), that is Vo = 2.34 V cos α 250Vdc = 2.34 × 415V

× cos α 3 which yields a delay angle of α = 1.11rad = 63.5°

vi.

T1

For a constant output power at 100A dc, the output voltage must be maintained at 250V dc independent of the ac input voltage magnitude, thus for equation (12.142) 250Vdc α = cos −1 2.34 × ( 415 ± 5% ) 3 ∨

α = cos −1

250Vdc 2.34 × ( 415 − 5% ) 3

α = cos −1

250Vdc 2.34 × ( 415 + 5% )

D4

io

io

2 V cos α = 2.34V cos α

0 ≤α ≤π /3

D4

vo io

π

va

(rad)

The maximum mean output voltage V o = √2V 3√3/π occurs at α = 0.

π+α

2π

ωt

is

ωt

o

ωt

is

is

(b)

(V)

ωt

is

= 1.13 rad = 64.9°

(c)

Figure 12.16. A full-wave three-phase half-controlled converter with a load freewheeling diode: (a) circuit; (b) α = π; and (c) α = ½π.

The freewheel diode is active for α > ⅓π. The output is as in figure 12.13b for α < ⅓π. The mean output voltage is

π

ωt

is

Both half-controlled and fully controlled converters can employ a discrete load freewheel diode. These circuits have the voltage output characteristic that the output voltage can never go negative, hence power inversion is not possible. Figure 12.16 shows a fully controlled three-phase converter with a freewheel diode D. Thyristor/diode variations similar to those shown in figure 12.1 are possible.

3 3

D6

o

2π

π π+α

T5

T3

D2

io

o

o

12.4.4 Three-phase, full-wave converter with freewheel diode

Vo = I o R =

T1

T5 ωt

vo

3 ♣

•

T1 D6

vo

vo

va is

= 1.08 rad = 61.9°

T5

T3 D2

(12.176)

The normalised mean output voltage Vn is given by Vn = Vo / V o = cos α The rms output voltage is 3 V rms = 3 2V (π − α + ½ sin 2α )

(12.177) (12.178)

π

•

while Vo = I o R =

3 3

π

(

2 V 1 + cos (α + π / 3)

)

π / 3 ≤ α ≤ 2π / 3

(V) (rad)

(12.179)

Power Electronics

517

Chapter 12


518

The normalised mean output, Vn, is

Vn = Vo / V o = 1 + cos (α + π / 3)

(12.180)

The rms output voltage, assuming continuous conduction, is 3 2π V rms = 3 2V + 3 cos 2 α 3 π

(

•

)

(12.181)

while

Vo = 0

(V)

2π / 3 ≤ α

(rad)

− πp

(12.182)

+ πp

0

In each case the average output current is given by I o = Vo / R , which can be modified to include any load back emf, that is, I o = (Vo − E ) / R . With continuous load current, with an R-L-E load, the closed form solution for the current is For 0 ≤ α ≤ ⅓π 1 − ωt  −ωt +α + 3π ∨  2V  e tan φ e tan φ sin α  i (t ) = sin (φ − α ) + sin φ + sin (ωt + 1 3 π − φ ) − −2π −2π  Z cos φ   1 − e 3 tan φ  1 − e 3 tan φ   For ⅓π ≤ α ≤ ⅔π − ωt +α + 1 3π − ωt   −ωt +α + 1 π  ∨  3 2V   e tan φ  e tan φ sin α  tan φ + − + + − − φ α φ ω φ i (t ) = e sin sin sin t ( ) ( )  −2π  −2π Z   cos φ  1 − e 3 tan φ  1 − e 3 tan φ   ∨ where Z = R 2 + ω 2L2 ; tan φ = ωL / R ; R = Z cos φ ; and E = 2VL sin α .

2π

(12.183)

pπ

(12.184)

rectify

½

Derive a general expression for the average load voltage of an p-pulse controlled converter. Solution Figure 12.17 defines the general output voltage waveform where p is the output pulse number per cycle of the ac supply. From the output voltage waveform π / n+α 1 Vo = 2 V cos ω t d ω t 2π / p ∫ −π / n+α 2V ( sin(α + π / p) − sin(α − π / p) ) 2π / p

=

2V 2sin(π / p ) cos α 2π / p

Vo =

2V

π/p

sin(π / p ) cos α

= Vo cos α

(V)

where for p = 2 for the single-phase (n = 1) full-wave controlled converter in figure 12.7. for p = 3 for the three-phase (n = 3) half-wave controlled converter in figure 12.11. for p = 6 for the three-phase (n = 3) full-wave controlled converter in figure 12.13. ♣

π

π

invert

−

Example 12.7: Converter average load voltage

=

(a)

p 2V 2 V s i n n π + n πsin p π

2V2 V s i n n π sin p π − p πn π

(b)

Figure 12.17. A half-wave n-phase controlled converter: (a) output voltage and current waveform and (b) transfer function of voltage versus delay angle α.

12.5

Overlap

In the previous sections of this chapter, impedance of the ac source has been neglected, such that current transfers or commutates instantly from one switch to the other with higher anode potential, when triggered. However, in practice the source has inductive reactance Xc and current takes a finite time to fall in the device turning off and rise in the device turning on. Consider the three-phase half-wave controlled rectifying converter in figure 12.11a, where it is assumed that a continuous dc load current, Io, flows. When thyristor T1 is conducting and T2 (which is forward biased) is turned on after delay α, the equivalent circuit is shown in figure 12.18a. The source reactances X1 and X2 limit the rate of change of current in T1 as i1 decreases from Io to 0 and in T2 as i2 increases from 0 to Io. These current transitions in T1 and T2 are shown in the waveforms of figure 12.18d. A circulating current, i, flows between the two thyristors. If the line reactances are identical, for a constant output current, the inductor di/dt currents are equal and opposite, the output voltage during commutation, vγ, is mid-way between the conducting phase voltages v1 and v2, as shown in figure 12.18b. That is vγ = ½(v1 + v2), creating a series of notches in the output voltage waveform as shown in figure 12.18c. This interval during which both T1 and T2 conduct (i ≠ 0) is termed the overlap period and is defined by the overlap angle γ. Ignoring thyristor voltage drops, the overlap angle is calculated as follows:

v 2 − v 1 = 2L

di dt

With reference t = 0 when T2 is triggered v2 − v1 = vL = 3 v phase = 3 2 V sin (ωt + α ) where V is the line to neutral rms voltage. Equating these two equations 2 L di / dt = 3 2 V sin (ωt + α )

Power Electronics

519

Chapter 12

0º


Rearranging and integrating gives

α α+γ

γ

α

520

i (ωt ) =

3 2V

2ω L

( cos α − cos (ωt + α ) )

(12.185)

Commutation from T1 to T2 is complete when i = Io, at ωt = γ, that is Io =

3 2V

2ω L

( cos α − cos (γ + α ) ) = 23πωVL ( cos α − cos (γ + α ) )

This equation holds for γ≤⅓π, provided 3V Io ≤ cos (α − 1 3 π ) 2 ωL Vγ = ½ (v1 + v2)

(b)

√2 VLL

0º

α

2π Vo   1 I o ≤ 3ωL cos (α − 3 π )  

Figure 12.18b shows that the load voltage comprises the phase voltage v2 when no source inductance exists minus the voltage due to circulating current vγ (= ½(v1 + v2)) during commutation. The mean output voltage Voγ is therefore Voγ = Vo − v γ

VT3 v3-1

α+γ

=

(e)

1  2π / 3 

α + 5π / 6

∫v

2

 

γ +α +π / 6

d ωt − ∫ vγ d ωt

α +π / 6

α +π / 6

where vγ = ½(v1 + v2)

π

 α +5π / 6 3  ∫ α +π / 6 2 V sin (ωt + α ) d ωt Vo = γ +α +π / 6 2π  −∫ 2 V sin (ω t + 2π 3 ) + sin ωt d ω t  α +π / 6 γ

commutation voltage

(12.186)

(A)

o

δ

{

}

   

v2 − v1 = 2 L di / dt

recovery angle = ωtq

Voγ =

3 2π

3 2 V cos α −

3 3 2 V ( cos α − cos (α − γ ) ) 2π 2

(12.187)

3 3 2 V  cos α + cos (α + γ )  = ½Vo  cos α + cos (α + γ )  (12.188) 4π which reduces to equation (12.131) when γ = 0. Substituting cos α - cos (α + γ) from equation (12.186) into equation (12.187) yields 3 3 3 3 3 3 Voγ = ω LI o = Vo − ω LI o where Vo = (12.189) 2 V cos α − 2V 2π 2π 2π 2π From equation (12.186) the commutation angle γ is    2ωL 3ωL  γ = cos −1  cos α − (12.190) I o  − α = cos −1  cos α − Io  − α 2πVo  3 2V    Voγ =

(c)

commutation voltage

The displacement power factor angle is displaced by half the overlap angle, that is DPF = cos φ1 = cos (α + ½γ ) while the overall power factor is

pf = DPF × DF = (d)

ia1

cos (α + ½γ )

(12.191)

(12.192)

1 + THD 2

The mean output voltage Vo is reduced or regulated by the commutation reactance Xc = ωL and this regulation varies with load current magnitude Io. Converter semiconductor voltage drops also regulate (decrease) the output voltage. The component 3ωL/2π is called the equivalent internal resistance. Being an inductive phenomenon, it does not represent a power loss component. As shown in figure 12.19, the overlap occurs immediately after the delay α. The commutation voltage, v2 - v1, is √3 √2 V sin α. The commutation time is inversely proportional to the commutation voltage v2 v1. For rectification, as α increases from zero to ½π, the commutation voltage increases from a minimum of zero volts to a maximum of √3 √2 V at ½π, whence the overlap angle γ decreases from a maximum of ∧ ∨ γ at α = 0 to a minimum of γ at ½π.

Figure 12.18. Overlap: (a) equivalent circuit during overlap; (b) angle relationships; (c) load voltage for different delay angles α (hatched areas equal to IoL; last overlap shows commutation failure); (d) thyristor currents showing eventual failure; and (e) voltage across a thyristor in the inversion mode, α >90°.

∨

∧

[For inversion, the overlap angle γ decreases from a minimum of γ at ½π to a maximum of γ at π, as the commutation voltage reduces from a maximum, back to zero volts.]

Power Electronics

521

Chapter 12

vo v2-v1

v1

I h1

vγ

2 2      2 3  cos 2α - cos 2 (α + γ )  + 2γ + sin 2α − sin 2 (α + γ )  = Io π 4  cos α − cos (α + γ ) 

½

(12.197)

The single-phase, full-wave, converter voltage drop is 2ωLIo /π and the overlap output voltage is zero.

i(ωt) 2

The general effects of line inductance, which causes current overlap are: • the average output voltage is reduced • the input voltage is distorted – notching in the ac voltage • the inversion safety angle to allow for thyristor commutation, is increased • the output voltage spectrum component frequencies are unchanged but there magnitudes are decreased slightly • thyristor di/dt is reduced.

δ

2 3V

ωL

i1

Io

γ

Io

i2

α = 135°

rectifying Vo > 0

nX/2π

Inverting Vo < 0 i1

Io

∨

γ

Io

γ

Io=0, γ

Vo

Io

i2

rectification

ωL

α = 90° i1

Io

γ

Io

equation

γ

γ

Io

γ

Vo =0, γ

Vo

(12.185) i2

n 2 V/π×sinπ/n×cosα

Mean output voltage

slope =

-nX/2π Io

i2

0

ωt α = 0°

=π

from equation (12.195) Io = 2×2½V/X×sinπ/n×cosα

½

α = 60° Io

=0

from equation (12.194)

Voγ = n 2½ V/π×sinπ/n×cosα

2 3V

i1

522

In the three-phase case, for a constant dc link current Io, without commutation effects, the rms phase current and the magnitude of the nth current harmonic are 2I o 2 3 (12.196) I rms = Ihn = Io nπ 3 When accounting for commutation reactance effects the fundamental current is

v2

½(v1+v2 )


½π

Load current (a)

π

inversion

(b)

Figure 12.20. Overlap regulation model: (a) equivalent circuit and (b) load plot of overlap model. Figure 12.19. Overlap γ for current commutation from thyristor 1 to thyristor 2, at delay angle α.

From equation (12.186), with α = π

Table 12.2. Summary of overlap effects on rectifier circuits

∨

γ = arc sin(2ω LI o / 2 3 V ) The general expressions for the mean load voltage Voγ of an n-pulse, fully-controlled converter, with underlap, are given by 2V Voγ = sin π n cos α + cos (α + γ )  (12.193) 2π / n and 2V Voγ = sin π n cos α ∓ nX c I o / 2π (12.194) π /n where V is the line voltage for a full-wave converter and the phase voltage for a half-wave converter and the plus sign in equation (12.194) accounts for inversion operation.

configuration

Effectively, as shown in figure 12.20, during rectification, overlap reduces the mean output voltage by nfLIo or as if α were increased. The supply voltage is effectively distorted and the harmonic content of the output is increased. Equating equations (12.193) and (12.194) gives the mean output current

12.6

2V

sin π n ( cos α − cos (γ + α ) ) (A) Xc which reduces to equation (12.186) when n = 3. Harmonic input current magnitudes are decreased by a factor sin (½ nγ ) / ½ nγ . Io =

(12.195)

single-phase full-wave

∆V c

Xc I π o

cos α − cos (γ + α )

Io X c 2V

single-phase bridge 2X c

three-phase half-wave 3X c Io 2π

three-phase bridge 3X c

2I o X c

2I o X c

2I o X c

π

Io

2V

6V

π

Io

6V

m-pulse rectifier

nX c Io 2π Io X c 2V sin

π n

Overlap - inversion

A fully controlled converter operates in the inversion mode when α > 90° and the mean output voltage is negative and less than the load back emf shown in figure 12.18a. Since the direction of the load current Io is from the supply and the output voltage is negative, energy is being returned, regenerated into the supply from the load. Figure 12.21 shows the power flow differences between rectification and inversion. As α increases, the returned energy magnitude increases. If α plus the necessary overlap γ exceeds ωt = π, commutation failure occurs. The output goes positive and the load current builds up uncontrolled.

Power Electronics

523

Chapter 12

The last commutation with α ≈ π in figures 12.18c and d results in a commutation failure of thyristor T1. Before the circulating inductor current i has reduced to zero, the incoming thyristor T2 experiences an anode potential which is less positive than that of the thyristor to be commutated T1, v1 - v2 < 0. The incoming device T2 fails to stay on and conduction continues through T1, impressing positive supply cycles across the load. This positive converter voltage aids the load back emf and the load current builds up uncontrolled.

Using equations (12.193) and (12.194) with n = 6 and V = 415 V ac, the mean supply reactance voltage n 6 × 2π 50 × 10−4 × 102 vγ = 2π f LI o = 2π 2π = 3V (i) α = 0° - as for uncontrolled rectifiers. From equation (12.194), the maximum output voltage is 2V sin π n cos α − nX c I o / 2π Voγ = 2π / n 2 × 415 π = sin 6 × cos 0 − 3V = 560.44V - 3V = 557.44V 2π / 6 where the mean output voltage without commutation inductance effects is 560.4V. The power output for 100A is 560.4V×100A = 56.04kW and the load resistance is 560.4V/100A = 5.6Ω. From equation (12.193) 2V Voγ = sin π / n  cos α + cos (α + γ )  2π / n 2 × 415 × sin π / 6 × [1 + cos γ ] 557.44 = 2π / 6 that is γ = 8.4°

The input power is equal to the dc power

cos φ =

Vo I o

3V I

(12.199)

≈ ½ cos α + cos (α + γ ) 

(12.200)

(ii)

α = 60º Voγ =

i

rectification

vs

vs i>0 vs > 0

power in

0 < α < ½π

2 × 415 sin π 6 × cos 60° − 3V = 280.22V - 3V = 277.22V 2π / 6 where the mean output voltage without commutation inductance effects is 280.2V. The power output for 100A is 280.2V×100A = 28.02kW and the load resistance is 280.2V/100A = 2.8Ω.

i>0 vs < 0

½π < α < π

+

power out

2V sin π n cos α − nX c I o / 2π 2π / n

=

i

+

power in

(a)

Voγ =

power out

+ inversion

2V sin π / n cos α + cos (α + γ )  2π / n

2 × 415 × ½ × cos 60° + cos ( 60° + γ )  2π / 6 that is γ = 0.71°

277.22 =

+

Equation (12.198) gives the maximum allowable delay angle as

(b)



 X Io − 1  2 V sin π / n 

α = cos −1 

Figure 12.21. Controlled converter model showing: (a) rectification and (b) inversion.

 2π50×10-4 ×102  = cos-1  -1 2 ×415×½   = 171.56° and Voγ = −557.41V ♣

Example 12.8:

524

Solution

Equations (12.193) and (12.194) are valid provided a commutation failure does not occur. The controllable delay angle range is curtailed to 0 ≤ α ≤ π −γ ∧ ∧ The maximum allowable delay angle α occurs when α + γ = π and from equations (12.193) and (12.194) with α + γ = π gives XI o   (12.198) α = cos−1  (rad) − 1 < π  2V sin π / n  In practice commutation must be complete δ rad before ωt = π, in order to allow the outgoing thyristor to regain a forward blocking state. That is α + γ + δ ≤ π . δ is known as the recovery or extinction angle, and is shown in figure 12.23e. The thyristor recovery period increases with increased anode current and temperature, and decreases with increased voltage.

P = 3VI cos φ = Vo I o The input power factor is therefore


Converter overlap

A three-phase full-wave converter is supplied from the 415 V ac, 50 Hz mains with phase source inductance of 0.1 mH. If the average load current is 100 A continuous, for phase delay angles of (i) 0º and (ii) 60º determine i. the supply reactance voltage drop, ii. mean output voltage (with and without commutation overlap), load resistance, and output power, and iii. the overlap angle Ignoring thyristor forward blocking recovery time requirements, determine the maximum allowable delay angle.

12.7

Summary

General expressions for n-phase converter mean output voltage, Vo (i) Half-wave and full-wave, fully-controlled converter sin(π / n ) Vo = 2 V cos α π /n where V is the rms line voltage for a full-wave converter or the rms phase voltage for a half-wave converter. cos α = cosψ , the supply displacement factor From L’Hopital’s rule, for n→∞, Vo = √2 V cosα

Power Electronics

525

Chapter 12

12.8


Definitions (see Chapter 11.6)

(ii) Full-wave, half-controlled converter sin(π / n ) Vo = 2 V (1 + cos α ) π /n where V is the rms line voltage.

Vo

Vrms = V ½ +

cos ( 2α − 2π / n ) n α − − 4 2π / n 4π / n

average output voltage

Vrms rms output voltage V

(iii) Half-wave and full-wave controlled converter with load freewheel diode sin(π / n ) Vo = 2 V cos α 0 < α < ½π − π / n π /n 1 + cos (α + ½π − π / n ) Vo = 2 V ½π − π / n < α < ½π + π / n 2π / n the output rms voltage is given by cos 2α sin 2π / n Vrms = V 1 + α + π / n ≤ ½π 2π / n

526

Io

average output current

Irms rms output current

peak output voltage I peak output current Vrms Load voltage crest factor = CFv = V Vo Vrms

Load voltage form factor = FFv = Load current form factor = FFi =

Irms

Load current crest factor = CFi = I

Io

Irms

dc load power ac load power + rectifier losses Vo I o = Vrms I rms + Loss rectifier

Rectification efficiency = η =

Waveform smoothness = Ripple factor = RFv =

α + π / n > ½π

where V is

=

the rms line voltage for a full-wave converter or the rms phase voltage for a half-wave converter. n = 0 for single-phase and three-phase half-controlled converters = π for three-phase half-wave converters = ⅓π for three-phase fully controlled converters

 ∞  VRi =  ∑ 12 ( van2 + vbn2 )   n=1 

where

effective values of ac V (or I ) VRi = average value of V (or I ) Vo

2 Vrms − Vo2 = FFv2 − 1 Vo2

½

similarly the current ripple factor is RFi =

I Ri

= FFi 2 − 1 Io RFi = RFv for a resistive load

These voltage output characteristics are shown in figure 12.22 and the main converter circuit characteristics are shown in table 12.2. 12.9

Output pulse number

Output pulse number p is the number of pulses in the output voltage that occur during one ac input cycle, of frequency fs. The pulse number p therefore specifies the output harmonics, which occur at p x fs, and multiples of that frequency, m×p×fs, for m = 1, 2, 3, ...

p =

period of input supply voltage period of minimum order harmonic in the output V or I waveform

The pulse number p is specified in terms of q the number of elements in the commutation group r the number of parallel connected commutation groups s the number of series connected (phase displaced) commutating groups Parallel connected commutation groups, r, are usually associated with (and identified by) intergroup reactors (to reduce circulating current), with transformers where at least one secondary is effectively star connected while another is delta connected. The rectified output voltages associated with each transformer secondary, are connected in parallel. Series connected commutation groups, s, are usually associated with (and identified by) transformers where at least one secondary is effectively star while another is delta connected, with the rectified output associated with each transformer secondary, connected in series. q =3 r =2 s =2 p=qxrxs p = 12

The mean converter output voltage Vo can be specified by

Vo = s

Figure 12.22. Converter normalised output voltage characteristics as a function of firing delay angle α.

q π

2 Vφ × sin

π × cos α q

For a full-wave fully-controlled single-phase converter, r = 1, q = 2, and s = 1, whence p = 2 2 2 Vφ 2 π 2Vφ × sin × cos α = Vo = 1 × × cos α 2 π π For a full-wave, fully-controlled, three-phase converter, r = 1, q = 3, and s = 2, whence p = 6 3 2 Vφ π 3 2 Vφ × sin × cos α = Vo = 2 × × cos α π π 3

(12.201)

Power Electronics

527

Chapter 12

Table 12.3: Main characteristics of controllable converter circuits


528

12.10 AC-dc converter generalised equations Alternating sinusoidal voltages V1 = 2V sin ωt

(

V 2 = 2V sin ωt − .

2π

q

)

(

Vq = 2V sin ωt − (q − 1) 2qπ

)

where q is the number of phases (number of voltage sources)

12.2a

12.7a

12.1

12.6b

12.11a

12.12a

12.10a

On the secondary or converter side of any transformer, if the load current is assumed constant I o then the power factor is determined by the load voltage harmonics. Voltage form factor

FFv =

V rms Vo

whence the voltage ripple factor is ½ ½ 1 2 RFv = V rms −Vo2  = FFv 2 − 1 V o

The power factor on the secondary side of any transformer is related to the voltage ripple factor by P V I 1 pf = d = o o = S qVI rms RFv 2 + 1 On the primary side of a transformer the power factor is related to the secondary power factor, but since the supply is assumed sinusoidal, the power factor is related to the primary current harmonics.

12.6a

12.1

12.12

12.10a

12.15

Relationship between current ripple factor and power factor 1 ∞ 2 1 2 RFi = − I 12 ∑ I h = I rms

I1

I1

h =3

pf =

I1 I rms

=

1 1 + RFi 2

The supply power factor is related to the primary power factor and is dependent of the supply connection, star or delta, etc. Half-wave controlled rectifiers – star connected secondary supply [see figures 12.4, 12.11] q phases and q thyristors, and a phase delay angle of α. The pulse number is p (=q). Mean output voltage is

Is α≤ 2

1

3

1

3

π

π −α Io π λ α≤

1

3

π

(1 + cos α )

2π α≥

1

3

π

3 (1 + cos α )

π −α

q 2π

∫

½ π + π q +α

2V sin ωt d ωt

½ π − π q +α

q π = 2V sin cos α π q = Vo (α = 0 ) cos α

Io

3

α≥

3

Vo =

π


q

½π + π q + α

(

)

2

2V sin ωt d ωt 2π ∫½π − π q +α ½   q 2π = 2V ½ + sin cos α  q 4π   The maximum and minimum voltages in the output are

V rms =

v = 2V .

 π  = 2V cos  − + α   q  ∨ π  v = 2V cos  + α  q  .

.

= − 2V .

for 0 < α < for α >

π q

π q

3π π + 2 q 3π π + for α > 2 q for α
½π -

Vo =

Power factor (is related to the equivalent diode circuit)

=

2q

π sin cos α = pf α =0 cos α pf = q π

v com =

ωLc I o 2V sin

q 2π

(V)

Z

- ωt ) / tanφ

p

p 2π



1−e

π

R

Discontinuous current Boundary condition

Io  pα  ½ - 2π + ¼p  q  

I rmsTh =

p

2V R sec 2 φ

½

Full-wave fully controlled thyristor converters–star connected supply [see figures 12.7, 12.8, 12.9, 12.13] q phases 2q thyristors Pulse number, p p=q p=2q Mean voltage

π π + tanh p p tan φ tan α = π π tan − tan φ tanh p p tan φ tan φ tan

i (ωt ) =

pα  - ¼p  2π 

 The thyristor conductor for 2π/p without a load freewheel diode and 2π/p-(π/p+α+½π) when the diode is present. The thyristor rms current is

2π p tan φ

.

R

½

I rms Df = I o  ½ +

2π

  − π π π π cos( + α ) + tan φ sin( + α ) − cos( − α ) − tan φ sin( − α )  e p tan φ p p p p  

with an average value of V p 2V π Io = o = sin cos α

½

−

The freewheel diodes conduct for p periods of duration π/p+α, and the currents are pα   - ¼p  I Df = I o  ½ + 2π  

(ohms)

−

p

}

where 2 V × R sec 2 φ

2 V cos ωt d ωt

  π  2 V 1 − sin  − + α   p   

 pα p 2π   sin  2α − + q   8 4 8 π π   π The maximum ripple occurs at ωt = − + α , with zero volts during diode freewheeling, thus p π  v p − p = 2V cos  − α  − 0 p  π  π  2V cos  − α  cos  − α  v p −p p p 2π     = = Vnp − p = p  π  π  p Vo 1 + sin  − α  2V 1 − sin  − α   2π p  p  

π q

Continuous current π ( − +α 2 V 2 V π i (ωt ) = cos(ωt - φ ) + { i o cos(− + α - φ ) e p

io =

½π

− π q +α

V rms = 2V ¼ −

ωLc I o

di + Ri = 2V cos ωt dt

Z where Z = R 2 + (ωL )2 tan φ = ωL / R

∫

RMS voltage

Time domain equations, for an R-L load

L

p 2π



.

π p

Mean rectified output voltage is

The thyristor currents are the same as the equivalent diode circuit

cos α − cos (α + µ ) =

for −

=0

1 + k 2q 2 tan2 α

q even π q odd = 2 2V cos 2q

Overlap angle and inductive voltage

π π + α < ωt < + α p p π π < ωt < + α for 2 p

v (ωt ) = 2V cos ωt

V DR = 2 2V V DR

530

Half-wave controlled rectifiers, with freewheel diode [see figures 12.6, 12.12]

π q

π sin q

k 2q 2 − 1


π  π  π   ( − p +α  cos ωt + tan φ sin ωt +  cos  − α  − tan φ sin  − α   e p  p   

The average output voltage is dependent on the current extinction angle, β   π  p Vo = 2 V  sin β − sin  − + α   2π  p  

- ωt ) / tanφ

  

if q is even if q is odd

Vo =

p π V sin cos α = Vo' cos α π p




Vo rms = V ½ +

 p 2π sin cos α  4π p 

½

 The maximum and minimum voltages in the output are

Power Electronics

531

for 0 < α

Chapter 12

π p

Pulse number in the rectified output is p=q for q even p=2q for q odd

π p

3π π + 2 p 3π π for α > + 2 p

Thyristor maximum forward and reverse voltages 2 2V VR = q even π q sin

π

where

π 1 V = ×Vo' p sin π p 2q π 2 V sin Vo' = π q

q

2 2 V cos

VR =

Half-controlled full bridges – delta connected secondary supply

q odd

In terms of the semiconductors and rectified voltage star and mesh behave the same. Mean voltage, for all q is

Io 2 I TH rms = I o q q q π pf = sin cos α = pf α =0 cos α π q

Vo =

I TH =

ωLc I o

cos α − cos (α − µ ) =

2V sin

.

v com =

q ωL I π c o

where Vo' =

.

2q

π

2 2 V sin

Io 

pf =

π

2



α   π 

π 1 −   

2

½

   

Reading list

π 2q

q even

Dewan, S. B. and Straughen, A., Power Semiconductor Circuits, John Wiley and Sons, New York, 1975.

q odd

Sen, P.C., Power Electronics, McGraw-Hill, 5th reprint, 1992.

π 1 + cos α pf = q sin 2 q π

α 6

q phases q thyristors and q diodes, each of which conduct for 2π/q Pulse number p=q for all q, odd or even Mean voltage

where Vo' =

2 V sin

π

.

= Vo'

2

2q

Is =

Half-controlled full bridges – star connected secondary [see figures 12.1, 12.10, 12.16]

q π

2 V sin

For a 3-phase half-controlled converter, the secondary current is

π q

Is =

Vo =

π (1 + cos α ) q 1 + cos α

q π

= Vo'

Overlap angle and inductive voltage

q

q odd

π q sin π q

q even

π 2q

RMS currents and power factor

Power factor 2 Is = Io

π 2q

The power factor is the same as for the star case.

Thyristor maximum reverse and forward voltage V R = 2 2V

V R = 2 2V cos

532

Full-wave fully-controlled bridges – delta connected secondary supply

for α
π −

2π

q 2π

q

Shepherd, W et al. Power Electronics and motor control, Cambridge University Press, 2nd Edition 1995. http://www.ipes.ethz.ch/

Power Electronics

533

12.8.

Problems 12.1.

Chapter 12

For the circuit shown in figure 12.23, if the thyristor is fired at α = ⅓π i. derive an expression for the load current, i ii. determine the current extinction angle, β iii. determine the peak value and the time at which it occurs iv. sketch to scale on the same ωt axis the supply voltage, load voltage, thyristor voltage, and load current.



534

Show that the average output voltage of a single-phase fully controlled converter is given by 2 2V Vo = cos α

π

Assume that the output current Io is constant. Prove that the supply current Fourier coefficients are given by 4I 4I an = − o sin nα bn = o cos nα nπ nπ for n odd. Hence or otherwise determine (see section 12.6) i. the displacement factor, cos ψ ii. the distortion factor, µ iii. the total supply power factor λ. Determine the supply harmonic factor, ρ, if ρ = Ih / I where Ih is the total harmonic current and I is the fundamental current. 12.9. Show that the average output voltage of a single-phase half-controlled converter is given by 2V vo = (1 + cos α )

π

Assume that the output current Io is constant. 12.2.

For the circuit shown in figure 12.24, if the thyristor is fired at α = ¼π determine i. the current extinction angle, β ii. the mean and rms values of the output current iii. the power delivered to the source E. iv. sketch the load current and load voltage vo.

Determine

i. the displacement factor, cos ψ ii. the distortion factor, µ iii. the total supply power factor, λ. Show that the supply harmonic factor, ρ (see problem 12.8), is given by  π (π − α )

ρ= 

 4 (1 + cos α )


12.10. A centre tapped transformer, single-phase, full-wave converter (figure 12.7a) with a load freewheel diode is supplied from the 240 V ac, 50 Hz supply with source inductance of 0.25 mH. The continuous load current is 5 A. Find the overlap angles for i. the transfer of current form a conducting thyristor to the load freewheel diode and ii. from the freewheel diode to a thyristor when the delay angle α is 30°.  ω LI o  γ t −d = cos−1 1 −  = 2.76°; 2V    

ω LI o 



2V  

γ t −d = cos −1 cos α − 12.3.

Assuming a constant load current derive an expression for the mean and rms device current and the device form factor, for the circuit in figure 12.1.

12.4.

Plot load ripple voltage KRI and load voltage ripple factor RFv, against the thyristor phase delay angle α for the circuit in figure 12.1.

12.5.

Show that the average output voltage of a n-phase half-wave controlled converter with a freewheel diode is characterised by sin(π / n ) Vo = 2 V cos α (V) π /n 0 < α < ½ -π / n 1 + cos α + ½π − 1 n π Vo = 2 V (V) 2π / n ½π − 1 n π < α < ½π + 1 n π

12.6.

Draw the load voltage and current waveforms for the circuit in figure 12.6a when a freewheel diode is connected across the load. Specify the load rms voltage.

12.7.

The converter in figure 12.6a, with a freewheel diode, is operated from the 240 V, 50 Hz supply. The load consists of, series connected, a 10 Ω resister, a 5 mH inductor and a 40 V battery. Derive the load voltage expression in the form of a Fourier series. Determine the rms value of the fundamental of the load current.

 − 1 

 − α = 0.13°

12.11. The circuit in figure 12.4a, with v = √2 V sin(ωt + α), has a steady-state time response of 2V

{sin(ωt + α − φ ) − sin(α − φ )e− Rt / L } Z where α is the trigger phase delay angle after voltage crossover and φ = tan −1 (ω L / R ) i (ωt ) =

Sketch the current waveform for α = ¼π and Z with i. R >> ωL ii. R = ωL iii. R φ both ac regulator thyristors will conduct and load current flows symmetrically as shown in figure 13.1b. The thyristor conduction period is given by the angle θ = β – α. The thyristor current extinction angle β for discontinuous load current can be determined with the aid of figure 11.9a, but with the restriction that β - α ≤ π, or figure 13.1d, or by solving equation 11.78, that is: sin( β - φ ) = sin(α - φ ) e(α -β ) / tan φ (13.4) From figure 13.1b the rms output voltage is

AC Voltage Regulators

Vrms =  1π ∫  α

β

(

2V

) sin ωt dωt  2

2

½

β = 2 V  1π ∫ (1 − cos 2ωt ) d ωt    α

½

= V 1π {( β − α ) − ½(sin 2β − sin 2α )} = V 1π {( β − α ) − sin ( β − α ) cos(α + β )} ½

AC voltage regulators have a constant voltage ac supply input and incorporate semiconductor switches which vary the rms voltage impressed across the ac load. These regulators generally fall into the category of naturally commutating converters since their thyristor switches are naturally commutated by the alternating supply. This converter turn-off process is termed line commutation. The regulator output current, hence supply current, may be discontinuous or non-sinusoidal and as a consequence input power factor correction and harmonic reduction are usually necessary, particularly at low output voltage levels (relative to the input ac voltage magnitude). A feature of direction conversion of ac to ac is the absence of any intermediate energy stage, such as a capacitive dc link or energy storage inductor. Therefore ac to ac converters are potentially more efficient but usually involve a larger number of switching devices and output is lost if the input supply is temporarily lost. There are three basic ac regulator categories, depending on the relationship between the input supply frequency fs, which is usually assumed single frequency sinusoidal, possibly multi-phased, and the output frequency fo. Without the use of transformers (or boost inductors), the output voltage rms magnitude VOrms is less than or equal to the input voltage rms magnitude Vs , Vo rms ≤ Vs . • output frequency increased, fo > fs, for example, the matrix converter • output frequency decreased, fo < fs, for example, the cycloconverter • output frequency fundamental = supply frequency, fo = fs, for example, a phase controller 13.1

∧

The maximum rms output voltage is when α = ϕ and β = ϕ + π in equation (13.5), giving V rms = V . The rms load current is found by the appropriate integration of equation (13.2) squared, namely 1 I rms =  π 

2

∫

β α

{

 2V  - ωt +α tan φ   sin (ωt - φ ) − sin (α − φ ) e  Z 

 sin ( β − α ) V 1  cos ( β + α + φ )   =   β −α −  Z  π  cos φ 

}

2

 d ωt   

½

(13.6)

½

∧

The maximum rms output current is when α = ϕ in equation (13.6), giving I rms = V / Z .

(c)

Single-phase ac regulator

Figure 13.1a shows a single-phase thyristor ac regulator supplying an L-R load. The two inverse parallel connected thyristors, possibly in the form of an ac output solid-state relay, SSR, can be replaced by any of the bidirectional conducting and blocking switch arrangements shown in figure 13.1c or figure 6.11. Equally, in low power applications the two thyristors are usually replaced by a triac. The ac regulator in figure 13.1a can be controlled by two methods • phase angle control – using symmetrical delay angles • integral (or half integral) cycle control – using zero phase angle delay

Φ = 90°

270°

vo

cos φ = 0 Φ = 75°

β=2π - α φ

Φ = 60° 240°

β=α + π

13.1.1 Single-phase ac regulator – phase control with line commutation VTH

For control by phase angle delay, the thyristor gate trigger delay angle is α, where 0 ≤ α ≤ π, as indicated in figure 13.1b. The fundamental of the output angular frequency is the same as the input angular frequency, ω = 2πfs. The thyristor current, shown in figure 13.1b, is defined by equation (11.76); that is

L

di + Ri dt

 = 2V sin ωt   = 0

(V)

α ≤ ωt ≤ β

(rad)

otherwise

(13.1)

The solution to this first order differential equation has two solutions, depending on the delay angle α relative to the load natural power factor angle, φ = tan −1 ω L R . Because of symmetry, the mean supply and load, voltages and currents, are zero. Case 1: α > φ When the delay angle exceeds the load power factor angle the load current always reaches zero before π+φ, thus the differential equation boundary conditions are zero. The solution for the current i is

BWW

(13.5)

½

Φ = 45°

β

Φ = 30°

210°

Φ = 15°

φ 180° 0

30°

60°

90° Delay angle

120°

150°

180°

α

(d)

Figure 13.1. Single-phase full-wave symmetrical thyristor ac regulator with an R-L load: (a) circuit connection; (b) load current and voltage waveforms for α>φ; (c) asymmetrical voltage blocking thyristor alternatives; and (d) current extinction angle β versus triggering delay angle α.

Power Electronics

539

Chapter 13

From equation (13.6), the thyristor rms current is given by ITh = I rms / 2 and is a maximum when α ≤ φ , that is I Th rms = I rms (13.7) =V 2 2Z Using the fact that the average voltage across the load inductor is zero, the rectified mean voltage (hence current) can be used to determine the thyristor mean current rating. .

rms

.

V o = I o R = 1π

∫

β

2 V sin ωt d ωt

α

= 2 V 1π {cos α − cos β }

(13.8)

(V)


The Fourier component magnitudes and phases are given by

c n = a n2 + bn2

½Vo 2V 1  π ( cos α − cos β )  (A) = R 2R  The maximum mean thyristor current is for a load α = φ and β = π+φ, that is ∧ 2 V cos φ 2V I Th = πR = πZ The thyristor forward and reverse voltage blocking ratings are both √2V. The load current form factor, using cosφ = R/Z, is

FFi load =

(13.10)

½

(13.11)

=

V I

=

S

2

P2

=

2 + V 2 I rms

+V

2 1

2 1

Q12

+ 2

2

2

(I

−V 2 I 12

2

rms

+

D

+

D2

− I 12 )

(13.17)

2

+ D2

The current harmonic components are found by dividing the load Fourier voltage components by the load impedance at that frequency. Equation (13.16) gives the current harmonic angles φn and magnitudes according to

= π /2 2 .

i Load

cn Vn Vn 2 = = 2 2 Zn R 2 + (ωL ) R 2 + ( ωL )

(13.18)

.

∧

i Th

= ½π .

The load power is 2 Po = I rms R

 cos φ )  β − α sin ( β − α ) − cos (α + φ + β )   π π φ cos R   2

V2

Z

2

½

 β − α sin ( β − α )  = − cos (α + φ + β )  × cos φ cos π π φ  

i (ωt ) =

2V Z

sin (ωt - φ )

(A)

α ≤ φ

(13.19)

(rad)

If a short duration gate trigger pulse is used and α < φ , unidirectional load current may result. The device to be turned on is reverse-biased by the conducting device. Thus if the gate pulse ceases before the previous half-cycle load current has fallen to zero, only one device conducts. It is therefore usual to employ a continuous gate pulse, or stream of pulses, from α until π, then for α < φ a sine wave output current results.

V  cos φ =   R . Z 

Po V I rms

Case 2: α ≤ φ (continuous gate pulses) When α ≤ φ , a pure sinusoidal load current flows, and substitution of α = φ in equation (13.2) results in

(13.12)

The supply power factor is

pf =

V 2 I 12

In =

2 FF i Load , which is a maximum when α = ϕ, FF

∧

=

where D is the supply current distortion due to the harmonic currents.

which is a maximum when α = ϕ, giving FF

which is a maximum when α = ϕ, giving P o =

V 2 I 12 + V 2 I 12 +V 2 I 32 + V 2 I 52 + ... −V 2 I 12

S = (VI 1 cos φ1 ) + (VI 1 sin φ1 )

The thyristor current form factor is FF i Th =

(V =

(13.16)

bn

=

2

.

∧

φn = tan−1 a n

The supply apparent power can be grouped into a component at the fundamental frequency plus components at the harmonic frequencies. S2 = V 2 I 12 + V 2 I 32 + V 2 I 52 + ...

(13.9)

I rms Io

   sin ( β − α ) cos φ  π1  β − α − cos ( β + α + φ )    cos φ    = 1   2  π ( cos α − cos β ) 

and

If α = φ , then continuous ac load current flows, and equation (13.14) reduces to a1 = 0 and b1 = √2V, when β = α + π = ϕ + α and α = φ are substituted.

The mean thyristor current I Th = ½ I o = ½V o / R , that is ITh =

540

(13.13)

∧

which is a maximum when α = ϕ, giving pf = cos φ . For an inductive L-R load, the fundamental load voltage components (cos and sin respectively) are 2V a1 = ( cos 2α − cos 2β ) 2π (13.14) 2V b1 = 2 ( β − α ) − ( sin 2 β − sin 2α ) ) ( 2π 2V  cos ( n + 1) α − cos ( n + 1) β cos ( n − 1) α − cos ( n − 1) β  − an =   n +1 n −1 π   (13.15) 2V  sin ( n + 1) α − sin ( n + 1) β sin ( n − 1) α − sin ( n − 1) β  bn = −   n +1 n −1 π   for n = 3, 5, 7, .. odd.

For both delay angle conditions, equations (13.5) to (13.14) are valid, except the simplification β=α+π is used when α ≤ φ , which gives the maximum values for those equations. That is, for α ≤ φ , substituting α =φ ∧ ∧ V =V =V I rms = I = V / Z ITh rms = ITh rms = V 2Z (13.20) rms

rms

∧

FF iLoad = FFiLoad = π / 2 2

rms

∧

2 R = V 2 cos φ / Z P o = Po = Irms

∧

pf = pf = cos φ

I Th =

.

2V / π Z

13.1.1i - Resistive load For a purely resistive load, the load voltage and current are related according to  2 V sin (ωt ) v (ωt )  α ≤ ωt ≤ π , α + π ≤ ωt ≤ 2π = io (ωt ) = o R R  0 otherwise

(13.21)

The equations (13.1) to (13.20) can be simplified if the load is purely resistive. Continuous output current only flows for α = 0, since φ = tan −1 0 = 0° . Therefore the output equations are derived from the discontinuous equations (13.2) to (13.14), with φ = 0. The average output voltage and current are zero. The mean half-cycle output voltage, used to determine the thyristor mean current rating, is found by integrating the supply voltage over the interval α to π, (β = π).

Power Electronics

541

2V

π

(1 + cos α )

∧

Vrms = =V

π

∫ (

2 V sin ωt

α

)

2

d ωt

2(π −α ) + sin 2α 2π

(13.23)

(V)

which has a maximum of V rms = V when α = 0. The rms output current and supply current from I rms = Vrms / R is Vrms V = R R = I rms / 2

I rms =

and

IT rms

α 1 − 2α −2sin2 π

= 2 I T rms

(A)

(13.24)

.

Therefore the output power, with Vrms = R Irms, for a resistive load, is 2 2 V 2 (W) Po = I rms R = rms = V 1 − 2α −sin2α 2π R R The input power is Pin = VI 1 cos φ1 ( = Pout ) .

{

S = VI rms

}

V 2  α sin 2α  1− + = R  π 2π 

2/π

Reciprocal of Distortion factor

Vn

rms

V3

rms

V5

rms

V7

rms

½

½π/10

(13.27)

(13.28)

π (π − α + ½ sin 2α )  =  1 + cos α I Th From equation (13.161) , the thyristor current crest factor is  2π 0 ≤ α ≤ ½π  I T 1 + cos α = δ = I T  2π sin α  ½π ≤ α ≤ π 1 + cos α

I Th rms

½

(13.29)

(13.30)

120 º π

150 º π

180 º π

α

Figure 13.2. Normalised RMS harmonics (voltage and current) for a single-phase full-wave ac regulator with a pure resistive load.

The fundamental supply current is

is1 = is1 =

v o1 1 = [b1 sin ωt + a1 cos ωt ] R R

2V  (π − α + ½ sin 2α ) sin ωt − (½ cos 2α − ½ ) cos ωt  πR 

(13.32)

b1 =

2V

π

V

½

( cos 2α − 1) + ( 2π − 2α + sin 2α )  (13.33)  2π R  When the power factor λ in equation (13.26) can be expressed in terms of the distortion factor and displacement factor, that is V i cos φ1 i average power P λ= = = s1 = s 1 cos φ1 apparent VA V I rms V I rms I rms

I s1 =

2

2

diplacement factor=cos φ1 where φ1 = tan−1

a1

b1

If the thyristors are modelled by

(π − α + ½ sin 2α )

(13.31) cos ( n − 1 ) α − 1  2 V  sin ( n + 1 ) α sin ( n − 1 ) α  − − bn =     n +1 n −1 n +1 n −1 π  π    for n = 3, 5, 7, … odd. Figure 13.2 show the relative harmonic rms magnitudes and dependence on α. The load current harmonics are found by dividing the voltage components by R, since i(ωt) = v(ωt)/R. 2 V  cos ( n + 1 ) α − 1

90 º π

= distortion factor × diplacement factor The current distortion factor is equation (13.33) divided by equation (13.24), while the fundamental current displacement factor from the fundamental components in equation (13.31) yields

The Fourier voltage components for a resistive load (with β = π in equations (13.14) and (13.15)) are

(½ cos 2α − ½ )

60 º π

which has an rms value of

V 2 cos 2α − 1 R 2π

The thyristor current (and voltage for a resistive load) form factor (rms to mean), shown in figure 13.2, is

FFiTh =

30º π

delay angle

½

2

Q1 =

an =

rms

(13.25)

and Q = S − P . The fundament reactive power is

2V

V1

Distortion factor FFi TH/10

1/FFi TH

0 0

The supply power factor λ is defined as the ratio of the real power to the apparent power, that is P V I V pf = λ = o = rms = rms = 2(π −α2)π+sin 2α (13.26) S VI V where the apparent power is

π

Power factor

0

I T rms = I rms / 2 = V / 2R .

a1 =

2(π −α ) + sin2α 2π

.

The maximum rms supply current is I rms = V / R at α = 0 when the maximum rms thyristor current is

2

542

V rms = V = V1 rms

(A)

The average thyristor current is I T = ½ I o , which has a maximum value of I T = 2V / π R when α = 0. From equation (13.5) the rms output voltage for a delay angle α is π

V rms = V

(13.22)

(V)

V 2V whence I o = o = (1 + cos α ) = 2 I T πR R

1

AC Voltage Regulators 1

2 V sin ωt d ωt

power factor and output voltage (rms) pu

=

π α

thyristor distortion factor FFiTh

Vo = 1π ∫

Chapter 13

v TH = v o + i × ro Then the thyristor losses are given by 2

PTH = v o I Th + ro × I Th2 rms = v o I TH + ro × I T h × FFi Th (α )

(W)

(13.34)

13.1.1ii - Pure inductive load For a purely inductive load, the load power factor angle is φ = ½π . Since the inductor voltage average is zero, current conduction will be symmetrical about π. Thus equations (13.2) to (13.14) apply except they can be simplified since β = 2π – α. These bounds imply that the delay angle should be greater than ½π,

Power Electronics

543

Chapter 13

but less than π. Therefore, if the delay angle is less than ½π, conduction extends into the next half cycle, and with short gate pulses, preventing the reverse direction thyristor from conducting, as shown in figure 13.3c. The output is then a series of half-wave rectified current pulses as with the case α ≤ φ considered in 13.3iii. For the purely inductive load case, the equations and waveforms for the half-wave controlled rectifier in section 11.3.1ii, apply. Kirchhoff’s voltage law gives

L

di = 2V sin ωt dt

The load current is given by: 2V cos α − cos (ωt ) i (ωt ) =

(

ωL


α < ½π i. short gate pulse period With a purely inductive load, the average output voltage is zero. If uni-directional current flows (due to the uses of a narrow gate pulse), as shown in figure 13.3c, the average load current, hence average thyristor current, for the conducting thyristor, is Io = IT =

(13.35)

=

)

α ≤ ωt ≤ 2π − α

(13.36)

544

1

2 V

πω L

2π

∫

2π −α

α

2 V

ωL


(13.37)

(π − α ) cos α + sin α 

which with uni-polar pulses has a maximum of √2 V/ωL at α = 0.

The current waveform is symmetrical about π. vo

o

β= 2π - α

ωt

π

α

2π

io iT1 o

π

2π

ωt iT2

β= 2π - α

iG1 Gate firing sequence

(a)

iG2

vo

normalised average and rms currents 1 pu = I (90º)

3 vo

short gate pulses equations (13.37) and (13.39) ITh ave

ITh rms

2

ITh ave ITh rms

1

Ireference symmetrical delay equations (13.43) and (13.45)

Long gate pulses equation (13.42) ITh ave

vo

0

30º

60º

90º Delay angle

o

α ½π

π

ωt

2π π

(b)

iT2


iG2

vo vs

ωt

2π- α o

α

π

2π

normalised rms output voltage

iT1

vo

120º

150º

180º

α

ωt

2π

io

o

ITh rms

symmetrical delay V

1

short gate pulses equation (13.41)

High dv/dt

symmetrical delay equation (13.46)

½

0 io

0 iT1 o

π

iT1

2π- α

2π

ωt

60º

iG2

Figure 13.3. Single-phase full-wave thyristor ac regulator with a pure inductor load: (a) α > ½π; (b) α < ½π, gate pulse until π; and (c) α < ½π, short gate pulse.

90º Delay angle

(c)


30º

120º

150º

180º

α

Figure 13.4. Normalised ac-chopper purely inductive load control characteristics of: (a) thyristor average and rms currents and (b) rectified average output voltage.

The rectified average load voltage is 2V Vo = (1 + cos α )

π

0 ≤ α ≤ ½π

(13.38)

Power Electronics

545


546

v

The rms load and supply (and one thyristor) current is ½ 2π −α 2 2 V 1 I rms = ( cos α - cos ωt ) dωt  2π ω L  ∫ α 3 V 1   =  (π − α )( 2 + cos 2α ) + sin 2α   2 X  π   The thyristor current form factor is ½π (π − α )( 2 + cos 2α ) + ¾π sin 2α FFi T = sin α + (π − α ) cos α

Chapter 13

Th1 ½

(13.39)

β

io = i L

Th2

Th2

VL

L

Vb ac

Vsinωt

v

Th1 VL

φ

vo/p Vb ac

(13.40)

α

α

VR

VR

R

vo/p Vbsin(ωt-ψ)

io

β v

Vsinωt

v

ψ

Vbsin(ωt-ψ)

VR

io = i L

Vb ac

φ

Vb ac

ψ

io

α α

which has a maximum value of ½π when α =½π. The rms load voltage is

∫ ( 2 V ) sin ωt dωt  = V 1π {(π − α ) + ½ sin 2α )}

Vrms =  12π 

2π −α

2



2

½

α

(13.41)

vo/p

vo/p

½

vo/p

v

ii. extended gate pulse period When the gate pulses are extended to π, continuous current flows, as shown in figure 13.3b, given by Irms=V/ωL, lagging V by ½π. Each thyristor conducts an average current and rms current of 2V I Th = πωL (13.42) I V ITh rms = rms = 2 πωL

VL

IT = =

1

2π

∫

2π −α

α

2 V

 πω L 

2 V

ωL

ψ

α

φ

φ β

2π-α

The rectified average load voltage over half a cycle is 2 2V Vo = (1 + cos α )

i

io

V 2 3  =  (π − α )( 2 + cos 2α ) + sin 2α   2 X  π   The rms load voltage is Vrms

(

2V

)

iL

sin ωt d ωt  

½

ωt o

α

2π-α

φ

α

½π

90º

ψ

½ π + ½ ϕ =

60º

1 0.9 0.8 0.6 0.4 0.2

(13.45)

ψ

½

30º

Vb leads V 30º

-90º

-60º

Vb lags V

(13.46)

(b)

φ

V

2

= V  2π {(π − α ) + ½ sin 2α )} The maximum rms voltage and current are V rms = V and I rms = V / X at α = ½π .

60º

-30º -30º

½

The rms equations for α greater than and less than ½π are basically the same except the maximum period over which a given thyristor conducts changes from π to 2π (respectively), hence the rms values differ by √2. Since the output power is zero, the supply power factor is zero, for bidirectional current. If the controller in figure 13.1a is use in the half-controlled mode (thyristor and anti-parallel diode), the resultant dc component precludes its use in ac transformer applications. The controller is limited to low power ac applications because of dc restrictions on the ac mains supply.

IR

ωt

o

.

2

vR = RiR

½π

(13.44)

The rms load and supply current is ½ 2 V  2 2π −α I rms = 2 I Th rms = ( cos α - cos ωt ) d ωt  π∫  α  ωL

io = i R

VL

Vb ac

π

2π −α =  1π ∫ α 

VR

(a)

which has a maximum of √2 V/πωL at α = ½π.

α

equal areas

(13.43) 

ωt o

o


(π − α ) cos α + sin α

Vb ac

ψ

ωt

io

π ≥ α ≥ ½π (symmetrical gate pulses) The output voltage and current are symmetrical, as shown in figure 13.3a, hence the average output voltage and current are both zero, as is the average input current. The average thyristor current is given by

vo/p

v Vb ac

(c)

ψ ½ π +

-60º

-90 º

φ

−½ ϕ =

ψ 90º 0.2 0.4 0.6 0.8 0.9 1

Vb ac V

Figure 13.5. AC-chopper characteristics with ac back emf and purely resistive or inductive load. Circuit, phasor diagram and circuit waveforms for: (a) purely resistive and ac source load and (b) purely inductive and ac source load. (c) Phase displacement of resultant voltage of an ac emf opposing the ac mains.

Power Electronics

547

Chapter 13


548

α = π

13.1.1iii - Load sinusoidal back emf

i.

When the ac controller load comprises an ac back emf vb ac of the same frequency as the ac supply v, as with embedded generation, then, when the thyristors conduct, the load effectively sees the vector difference between the two ac voltages, v-vb ac, as shown in figure 13.5. v R ,L = v − v b ac

(a) Since α = π / 6 < φ = π / 4 , the load current is continuous and bidirectional, ac. The rms load voltage is 240V.

= V ∠0 −V b ac ∠ψ = V + 0 j −V b ac ( cos ψ + j sinψ ) = V −V b ac cos ψ − jV b ac sinψ

(13.47)

(b) From equation (13.20) the power delivered to the load is V2 2 cos φ Po = Irms R= Z =

= v R ,L ∠ϕ

where

v R ,L =

(V

ϕ = tan−1

2

−V b ac sinψ

2

10Ω

cos¼π = 4.07kW

The rms output current and supply current are both given by I rms = Po / R

−V b ac cos ψ ) + (V b ac sinψ ) = V 2 + V b2ac − 2V V b ac cos ψ 2

240

(13.48)

V −V b ac cos ψ

The passive part of the load can now be analysed as in sections 13.1.1i and ii, but the thyristor phase triggering delay angles are shifted by φ with respect to the original ac supply reference, as shown in the phasor diagrams in figure 13.5. If the voltage is normalised with respect to the ac supply V, then the normalised curves in figure 13.5 can be used to obtain the phase angle φ, with respect to the ac mains reference. Therefore curves give the angle of the voltage (and the current in the case of a resistor load) across the passive part of the load. As seen in the waveforms in figure 13.5, the load current is dependent on the relative magnitudes and angle between the two ac sources, the type of load, and the thyristor phase delay angle. Performance features with a resistive load and inductive load are illustrated in Example 13.1d.

= 4.07kW / 7.1Ω = 23.8A The input power factor is the load natural power factor, that is P 4.07kW = 0.70 pf = o = S 240V × 23.8A = µ cos φ = µ / 2 Thus the current input distortion factor is µ = 1, for this sinusoidal current case.

ii.

α = ⅓π

(a) Since α = π / 3 > φ = ¼π , the load hence supply current is discontinuous. For α = π / 3 > φ = ¼π the extinction angle β = 3.91 rad or 224.15° can be extracted from figure 11.7a or determined after iteration using equation (13.4). The rms load voltage is given by equation (13.5). Vrms = V 1π {( β − α ) − ½(sin 2β − sin 2α )}

½

13.1.1iv - Semi-controlled single-phase ac regulator

= 240 × 1π {( 3.91 − 1 3 π ) − ½(sin 2 × 3.91 − sin 2 3 π )}

A semi-controlled single-phase ac regulator is formed by replacing one thyristor in figure 13.1a with a diode. A dc component results in the load current and voltage. For a resistive load, the diode average and rms currents are found by substituting α = 0 in equations (13.22) and (13.24). Using these equations, the load resistance average and rms currents (hence voltages) are I R = I D − I T = 2 2 − 2 2 (1 + cos α ) = 2 2 (1 − cos α ) = Vo πR πR πR R (13.49) ½ V rms V  2α - sin 2α  2 2 I R rms = I D rms + I T rms = =  π R 2R   The power dissipated in the resistive load is V 2  2α − sin 2α  (13.50) PR =  4π R  

= 240 ×

Example 13.1a:

Single-phase ac regulator – 1

If the load of the 50 Hz 240V ac voltage regulator shown in figure 13.1 is Z = 7.1+j7.1 Ω, calculate the load natural power factor angle, φ . Then, assuming bipolar load current conduction, calculate (a) the rms output voltage, thence (b) the output power and rms current, whence input power factor and supply current distortion factor, µ for

i. α = π ii. α = ⅓π

Solution From equation (13.3) the load natural power factor angle is φ = tan −1 ω L / R = tan −1 X L / R = tan −1 7.1/ 7.1 = ¼π (rad) Z = R 2 + (ω L) 2 = 7.12 + 7.12 = 10Ω

2.71

π

½

= 226.4V

(b) The rms output (and input) current is given by equation (13.6), that is I Orms =

V Z

1   sin ( β − α ) cos ( β + α + φ )     β − α −  π cos φ    

½

 sin ( 3.91 − 13 π ) 240  1    3.91 − 13 π − cos ( 3.91 + 13 π + ¼π )   = 18.0A  10  π  cos¼π   The output power is given by 2 Po = I rms R ½

=

= 18.02 ×7.1Ω = 2292W The load and supply power factors are P P 2292W 2292W pf o = o = = 0.562 pf = o = = 0.531 S 226.4V × 18.0A S 240V × 18.0A The Fourier coefficients of the fundamental, a1 and b1, are given by equation (13.14) 2V 2 240V a1 = cos 2 π − cos 2 × 3.91 = −28.8V ( cos 2α − cos 2β ) = 3 2π 2π 2V 2 240V b1 = ( 2 ( β − α ) − sin 2β + sin 2α ) = 2π 2 × 3.91 − π 3 − sin 2 × 3.91 − sin 2 × π 3 = 302.1V 2π

(

)

( (

The fundamental power factor is   a cos φ1 = cos  tan−1  1   = cos tan−1 −28.8V 302.1V  b1   

(

(

The current distortion factor is derived from pf = µ × cos φ1 0.531 = µ × 0.995 That is, the current distortion factor is µ = 0.533.

♣

)

)

)) = 0.995

Power Electronics

549

Chapter 13


550

Example 13.1b: Single-phase ac regulator – 2

Solution

If the load of the 50 Hz 240V ac voltage regulator shown in figure 13.1 is Z = 7.1+j7.1 Ω, calculate the minimum controllable delay angle. Using this angle calculate i. maximum rms output voltage and current, and hence ii. maximum output power and power factor iii. thyristor I-V and di/dt ratings

For a purely inductive load, the current extinction angle is always β = 2π-α, that is, symmetrical about π and tanΦ→∞. a. If the delay angle π > α > ½π and symmetrical, then the load current is discontinuous alternating polarity current pulses as shown in figure 13.3a. b. If the delay angle 0 < α < ½π, and a short duration gate pulse is used for each thyristor, then the output comprises discontinuous unidirectional current pulses of duration 2π-2α, as shown in figure 13.3c.

Solution As in example 13.1a, from equation (13.3) the load natural power factor angle is φ = tan −1 ω L / R = tan −1 7.1/ 7.1 = π / 4 The load impedance is Z=10Ω. The controllable delay angle range is ¼π ≤ α ≤ π . i.

a. α = ¾π: symmetrical gate pulses - discontinuous alternating current pulses. The average output voltage and current are zero, I o = v o = 0 . The maximum rms load voltage and current, with bidirectional output current and voltage, are when α = ½π

V rms = V = 240V V 240V = = 24A I rms = 10Ω X

The maximum controllable output occurs when α = ¼π. From equation (13.2) when α = φ the output voltage is the supply voltage, V, and 2V

i (ωt ) =

Z

sin (ωt -¼π )

(A)

The load hence supply rms maximum current, is therefore I rms = 240V /10Ω = 24A 2 ii. Power = I rms R = 242 × 7.1Ω = 4090W

∫

1 2π

2 I rms R 242 × 7.1Ω = = 0.71 ( = cos φ ) µ = 1 VI rms 240V × 10A

=

α +π =φ +π α =φ

2V

2 V sin (ωt − φ ) d ω t

2 × 240V

=

πZ π × 10Ω The thyristor rms current rating is  1 ITrms =   2π

∫

α +π =φ +π α =φ

{

= 10.8A

}

2  2 V sin (ωt − φ ) d ωt  

dt

2V

=

Z

2V

dt

Z

sin (ωt -¼π )

ω cos (ωt -¼π )

dt

=

2V ω

½

ii. Each thyristor conducts half the load current hence IT = 5.1A/√2=3.6A rms. Before start-up, at shutdown or during operation, each thyristor has to block bi-directionally √2 240 = 340V, peak. The average thyristor current is

=

2 V

(π − α ) cos α + sin α 

πω L 

2 240V

 π × 10Ω 

(π − ¾π ) cos ¾π + sin ¾π

2 × 240V × 2π × 50Hz = 10.7A/ms 10Ω Thyristor forward and reverse blocking voltage requirements are √2V = √2×240 = 340Vdc. =

♣

Example 13.1c: Single-phase ac regulator – pure inductive load

If the load of the 50 Hz 240V ac voltage regulator shown in figure 13.1 is Z = jX= j10 Ω, and the delay angle α is first ¾π then second ¼π calculate i. maximum rms output voltage and current, and hence ii. thyristor I-V ratings Assume the thyristor gate pulses are of a short duration relative to the 10ms half period.

 = 1.64A

b. α = ¼ π: short gate pulses – discontinuous unidirectional current pulses. The average output voltage and current are not zero, I o ≠ 0 and v o ≠ 0. i. The rms output current and voltage are given by equations (13.45) and (13.46), respectively, with Φ = π and β = 2π-α, that is I rms =

V 1  3   (π − α )( 2 + cos 2α ) + sin 2α   X  π  2 

½

½

=

240V  1  3   (π − ¼π )( 2 + cos½π ) + sin ½π   = 37.75A 10Ω  π  2 

Vrms = V 1π {(π − α ) + ½ sin 2α )}

Z

½

  3  = 240V  2π (π − ¾π ) + ½ sin π )  = 54.65V 2   

(A/s)

This has a maximum value when ωt-¼π = 0, that is at ωt = α = φ , then di ( ω t )

Vrms = V  2π {(π − α ) + ½ sin 2α )}

½

2V 2 × 240V I = = 17.0A = rms 2 2Z 2 × 10Ω Maximum thyristor di/dt is derived from =d

½

240V  2  3  3 3     (π − ¾π )  2 + cos π  + sin π   = 5.1A 10Ω  π  2  2 2   

IT =

=

d i (ω t )

V 2 3   (π − α )( 2 + cos 2α ) + sin 2α   X  π  2 

½

iii. Each thyristor conducts for π radians, between α and π+α for T1 and between π+α and 2π+α for T2. The thyristor average current is IT =

I rms = =

power output power factor = apparent power output

=

i. The rms output current and voltage are given by equations (13.45) and (13.46), respectively, with Φ = π and β = 2π-α, that is

½

= 240V 1π {(π − ¼π ) + ½ sin ½π )} = 228.8V ½

ii. Although only one thyristor conducts, which one that actually conducts may be random, thus both thyristor are rms rated for IT = 37.75A. Whilst operational, the maximum thyristor voltage is √2 240 sin¼π, that is 240V. But before start-up or at shut-down, each thyristor has to block bidirectionally, √2 240 = 340V, peak. The average thyristor (and supply and load) current is IT = =

2 V

(π − α ) cos α + sin α 

πω L 

2 240V

 π × 10Ω 

(π − ¼π ) cos¼π + sin ¼π ♣

 = 25.6A

Power Electronics

551

Example 13.1d:

Single-phase ac regulator – 1 with ac back emf composite load

A 230V 50Hz mains ac thyristor chopper has a load composed of 10Ω resistance in series with a138V 50Hz ac voltage source that leads the mains by 30º. If the thyristor triggering angle is 90º with respect to the ac mains, determine

Chapter 13

552

diagram in figure 13.5, the thyristor firing angle with respect to the load inductor voltage is αL = α + φ = 90º + 32.8º = 122.8º. Since the effective delay angle αL is greater than 90º, symmetrical, bipolar, discontinuous load current flows, as considered in section 13.1ii. i.

With a 20mH load inductor, the load rms current is given by equation (13.45), that is

VL  2   3 (π − αL )( 2 + cos 2αL ) + sin 2αL   X  π  2 

I rms =

The rms load current and maximum rms load current for any phase delay angle The power dissipated in the passive part of the load The thyristor average and rms current ratings and voltage ratings Power dissipated in the thyristors when modelled by vT = vo + ro×iT =1.2 + 0.01×iT

i. ii. iii. iv.


½

130.3V 122.8°  3  2− ( 2 + cos 2 × 122.8° ) + sin 2 × 122.8° 2π 50Hz × 0.02H  90°  π = 20.74A × 0.373 = 7.73A The maximum bipolar rms load current is when αR = 90º, Irms = 20.74, and α = 90 - φ = 32.8º. =

Repeat the calculations if the passive part of the load is a 20mH inductor and the ac back emf lags the 50Hz ac mains by 30º. Solution

ii.

The 20mH inductor losses are zero.

ac back emf with a pure resistive load From equation (13.48), the voltage across the resistive part of the load is

iii.

The thyristor current ratings are I T rms = I rms / 2 .

v R = V 2 + V b2ac − 2VV b ac cos ψ

= 7.73 / 2 = 5.47A From equation (13.43), the average thyristor current is .

= 2302 + 1382 − 2 × 230 × 138 × cos 30 = 130.3V with an angle of φ = -32.8º with respect to the ac mains, given by ψ = 30º and Vb ac / V = 138V/230V = 0.6 in the fourth quadrant of figure 13.5. From the phasor diagram in figure 13.5, the thyristor firing angle with respect to the load resistor voltage is αR = α - φ = 90º - 32.8º = 57.8º. i.

=

ii.

The 10Ω resistor losses are 2 P10 Ω = I rms × 10Ω

2  

iv.

The power dissipated in each thyristor is PT = v o I T + ro I T2 rms = 1.2V × 2.8A + 0.01Ω × 5.472 = 3.66W

♣

= 9.54 × 10Ω = 910.1W 2

iii.

The thyristor current ratings are

I T rms = I rms / 2

13.1.2 Single-phase ac regulator – integral cycle control - line commutated

.

= 16.83 / 2 = 11.9A From equation (13.22), the average thyristor current is 2 VR IT =½ (1 + cos α R ) .

πR

2 × 130.3V (1 + cos 57.8°) = 4.5A π × 10Ω The thyristors effectively experience a forward and reverse voltage associated with a single ac source of 130.3V ac. Without phase control the maximum thyristor voltage is √2×130.3V=184.3V. If the triggering angle α is less than 90º-φ=122.8 º (with respect to the ac mains) then the maximum off-state voltage is less, namely =½

V T = 2 × 130.3 × sin (α − 32.8° ) if α < 122.3° iv.



122.8° 

π 1− × cos122.8° + sin122.8°  = 2.80A π   180°   The thyristors effectively experience a forward and reverse voltage associated with a single ac source of 130.3V ac. Without phase control the maximum thyristor voltage is √2×130.3V=184.3V. Since αR ≥ 90º is necessary for continuous bipolar load current, 184.3V will always be experienced by the thyristors for any αR > 90º. = 20.74A

The load rms current is given by equation (13.24), that is 2α − sin 2α R V I rms = R 1 − R 2π R 130.3V 57.8° sin 2 × 57.8° + = 13.03A × 0.732 = 9.54A 1− 2π 10Ω 180° The maximum rms load current is 13A when is αR = 0, that is when α = -φ = 32.8º.

2 VL (π − α L ) cos α L + sin α L  πωL 

IT =

The power dissipated in each thyristor is PT = v o I T + ro I T2 rms

In thyristor heating applications, load harmonics are unimportant and integral cycle control, or burst firing, can be employed. Figure 13.6a shows the regulator when a triac is employed and figure 13.6b shows the output voltage indicating the regulator’s operating principle. Because of the low frequency sub-harmonic nature of the output voltage, this type of control is not suitable for incandescent lighting loads since flickering would occur and with ac motors, undesirable torque pulsations would result. In many heating applications the load thermal time constant is long (relative to 20ms, that is 50Hz) and an acceptable control method involves a number of mains cycles on and then off. Because turn-on occurs at zero voltage cross-over and turn-off occurs at zero current, which is near a zero voltage crossover, supply harmonics and radio frequency interference are low. The lowest order harmonic in the load is 1/Tp. For a resistive load, the output voltage (and current) is defined by v o = i o R = 2V sin (ωt ) for 0 ≤ ωt ≤ 2π m

= 1.2V × 4.5A + 0.01Ω × 11.9 = 6.8W

ac back emf with a pure reactive load The voltage across the inductive part of the load is the same as for the resistive case, namely 130.3V. In this case the ac back emf lags the ac mains. The phase angle with respect to the ac mains is φ = 32.8º, given by ψ = -30º and Vb ac / V = 138V/230V = 0.6 in the second quadrant of figure 13.5. Being a purely inductive load across the 130.3V ac voltage, the current lags this voltage by 90º. From the phasor

(13.51)

for 2π m ≤ ωt ≤ 2π N

=0 2

where Tp = 2πN/ω. The rms output voltage (and current) is  1 Vrms =   2π

∫

2π m / N 0

(

2V sin N ω t

Vrms = I rms R = V m / N = V δ .

)

2

½

 dω t  

where the duty cycle δ = m

(13.52) N

Power Electronics

553

Chapter 13

The Fourier coefficient and phase angle for each load voltage harmonic (for n ≠ N) are given by 2N c n = 2V sin π n δ 2 π N2 −n

(

)

φn = π (1 − n δ ) for n < N

(13.53)

φn = π ( n δ − 1) for n > N When n > N the harmonics are above 1/ Tp, while if n < N subharmonics of 1/ Tp are produced. For the case when n = N, the coefficient and phase angle for the sin πm term (an=N = 0) are m bn = N = c n = N = 2 V = 2 V δ and φn =N = 0 (13.54) N Note the displacement angle between the ac supply voltage and the load voltage frequency component at the supply frequency, n = N, is φn =N = 0 . Therefore the fundamental power factor angle cos φn =N = cos 0 = 1 .

Po w e r, cu rre n t, volta g e , a n d p o w e r fa cto r pu

δ =

m N

¾

Irms

Irms

Example 13.2: Integral cycle control

The power delivered to a 12Ω resistive heating element is derived from an ideal sinusoidal supply √2 240 sin 2π 50 t and is controlled by a series connected triac as shown in figure 13.6. The triac is controlled from its gate so as to deliver integral ac cycle pulses of three (m) consecutive ac cycles from four (N). Calculate i. ii. iii. iv. v.

V

vi.

R

V /R

Vrms /V

½

P

V

vii. viii.

2

554

phase angle control. The introduction of sub-harmonics tends to restrict this control technique to resistive heating type application. Temperature effects on load resistance R have been neglected, as have semiconductor on-state voltages. Finer resolution output voltage control is achievable if integral half-cycles are used rather than full cycles. The equations remain valid, but the start of multiplies of half cycles are alternately displaced by π so as to avoid a dc component in the supply and load currents. Multiple cycles need not be consecutive within each period.

1

pf =


R

The percentage power transferred compared to continuous ac operation The supply power factor, distortion factor, and displacement factor The supply frequency (50Hz) harmonic component voltage of the load voltage The triac maximum di/dt and dv/dt stresses The phase angle α, to give the same load power when using phase angle control. Compare the maximum di/dt and dv/dt stresses with part iv. The output power steps when m, the number of conducted cycles is varied with respect to N = 4 cycles. Calculate the necessary phase control α equivalent for the same power output. Include the average and rms thyristor currents. What is the smallest power increment if half cycle control were to be used? Tabulate the harmonics and rms subharmonic component per unit magnitudes of the load voltage for m = 0, 1, 2, 3, 4; and for harmonics n = 0 to 12. (Hint: use Excel)

Solution ¼

The key data is: m = 3 N = 4 (δ = ¾) V = 240 rms ac, 50Hz i.

0 0

¼

½

¾

1

δ=m/N

m

The power transfer, given by equation (13.55), is 2 2 m 2402 = V δ= P= V ×¾ = 4800×¾ = 3.6kW 12Ω R N R That is 75% of the maximum power is transferred to the load as heating losses.

ii. The displacement factor, cosψ, is 1. The distortion factor is given by m 3 µ= = δ= = 0.866 N 4 Thus the supply power factor, λ, is m λ = µ cosψ = = δ = 0.866×1 = 0.866 N

(c) m

.

.

Figure 13.6. Integral half-cycle single-phase ac control: (a) circuit connection using a triac; (b) output voltage waveforms for one-eighth maximum load power and nine-sixteenths maximum power; and (c) normalised supply power factor and power output.

iii. The 50Hz rms component of the load voltage is given by m = V δ = 240×¾ = 180V rms V50 Hz = V N iv. The maximum di/dt and dv/dt occur at zero cross over, when t = 0. dVs d = 2 240 sin 2π 50t | t =0 dt |max dt = 2 240 ( 2π50 ) cos2π50t|

The output power is m V 2 = δ × V = I rms (W) P= R R N R where n is the number of on cycles and N is the number of cycles in the period Tp. The average and rms thyristors currents are, respectively, 2V m 2V 2V m 2V = δ = δ IT = I T rms = 2R N 2R πR N πR 2

2

(13.55)

(13.56)

From equation (13.54), the supply displacement factor cosψ n= N is unity and supply power factor λ is m / N = P / P = δ . From pf = λ = µ cos φn =N = µ , the distortion factor µ is m / N = δ . The rms voltage at the supply frequency is V m /N = δV and the power transfer ratio is m/N = δ. For a given percentage of maximum output power, the supply power factor is the same for integral cycle control and .

.

t =0

= 2 240 ( 2π50 ) = 0.107 V/µs d Vs dt R

|

max

=

d 2 240 sin 2π 50t | t =0 dt 12Ω

= 2 20 ( 2π50 ) cos2π50t|

t =0

= 2 20 ( 2π50 ) = 8.89 A/ms

v. To develop the same load power, 3600W, with phase angle control, with a purely resistive load, implies that both methods must develop the same rms current and voltage, that is, Vrms = R P = V m / N = V δ . From equation (13.5), when the extinction angle, β = π, since the load is resistive .

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Vrms = R × P = V m / N = V δ = V 1π {(π − α ) + ½ sin 2α }


½

Normalised components

that is m δ = = 1π {(π − α ) + ½ sin 2α } = ¾ = 1π {(π − α ) + ½ sin 2α } N

Solving 0 = ¼π − α + ½ sin 2α iteratively gives α = 63.9°. When the triac turns on at α = 63.9°, the voltage across it drops virtually instantaneously from √2 240 sin 63.9 = 305V to zero. Since this is at triac turn-on, this very high dv/dt does not represent a turn-on dv/dt stress. The maximum triac dv/dt stress tending to turn it on is at zero voltage cross over, which is 107 V/ms, as with integral cycle control. Maximum di/dt occurs at triac turn on where the current rises from zero amperes to 305V/12Ω = 25.4A quickly. If the triac turns on in approximately 1µs, then this would represent a di/dt of 25.4A/µs. The triac initial di/dt rating would have to be in excess of 25.4A/µs.

cycles

period

duty

power

I Th

IThrms

m

N

δ

W

A

A

Delay angle α

Displacement factor cosψ

Distortion factor µ

Power factor λ

0

4

0

0

0

0

180°

1

4

¼

1200

2.25

7.07

114°

1

½

½

2

4

½

2400

4.50

10.0

90°

1

0.707

0.707

3

4

¾

3600

6.75

12.2

63.9°

1

0.866

0.866

4

4

1

4800

9

14.1

0

1

1

1

556

δ and m

n

Hz

0 0

¼ 1

½ 2

¾ 3

1 4

0 1 2 3 4 5 6 7 8 9 10 11 12

0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150

0 0 0 0 0 0 0 0 0 0 0 0 0

0 0.120 0.212 0.257 ¼ 0.200 0.127 0.055 0 -0.028 -0.030 -0.017 0

0 0.170 0 -0.364 ½ -0.283 0 0.077 0 -0.039 0 0.024 0

0 0.120 -0.212 0.257 ¾ 0.200 -0.127 0.055 0 -0.028 0.030 -0.017 0

0 0 0 0 1 0 0 0 0 0 0 0 0

all n

sum square

0

0.249

0.499

0.749

1

12

rms

0

0.499

0.707

0.866

1

all n check

exact rms

0

all n but not n=4

ac harmonic rms

n≤3

sub harmonics rms

0

upper harmonics rms

0

0.5

0.707

0.866

0

0.432

0.499

0.432

1

2

n

.

0.401

0.354

∑c

0

1

12

vii. The following table show harmonic components, rms subharmonics, etc., for N = 4, (up to the twelfth) which are calculated as follows.

0.249

0.298

0.249

0

pf = λ

power factor

0

½

0.707

0.866

1

power pu

0

¼

½

¾

1

0.247

0.297

0.247

∑c

0

5

δ

− c 42

3

0.354

0

)

∑c

0

2

n

=

4 12

upper harmonics rms

n≥5

m

1

check

For n ≠ 4, (that is not 50Hz) the harmonic magnitude is calculated from equation (13.53). 2 2V N 8 2V  π nm   π nm  cn = sin  × sin  =  when N = 4 and n ≠ 4 2 2  N  π 16 − n  4  π N2 −n

2

n

∑c

1

n≥5

(

∑c 12

all n

vii. Finer power step resolution can be attained if half cycle power pulses are used as in figure 13.6b. If one complete ac cycle corresponds to 1200W then by using half cycles, 600W power steps are possible. This results in nine different power levels if N = 4, from 0W to 4800W, in 600W steps.

)

m/N fundamental

1

vi. The output power can be varied using m = 0, 1, 2, 3, or 4 cycles of the mains. The output power in each case is calculated as in part 1 and the equivalent phase control angle, α, is calculated as in part v. The appropriate results are summarised in the table.

(

m/N

2

n

2

n

m

3 m  − ∑ c n2 −   4 1  4 

2

m

= δ 4 ¼m .

♣

Equation (13.54) gives the 50Hz load component (n = 4).

m m = 2V when N = 4 and n = 4 N 4 Component magnitudes (but not necessarily phase) are equal about δ=½ when N is even. The rms output voltage is given by equation (13.52) or the square root of the sum of the squares of the harmonics, that is c n =N = 4 = 2 V

Vrms = V m / N = V

∞

∑c

2 n

n=1

The ac subharmonic component (that is components less than 50Hz) is given by

V ac ,sub = 2 V c 12 + c 22 + c 32 

½

From equations (13.52) and (13.54), the non fundamental (50Hz ac) component is given by 2

2 V ac = V rms −V 502 Hz = V

m m  − = V δ (1 − δ ) N  N 

13.1.3 The solid-state relay (SSR)

A Solid-State Relay (SSR) is a normally-open, electrical switch comprising solid-state semiconductors and/or electronic components that can be used in place of a mechanical relay to switch electricity to a load. An SSR offers enhanced electrical performance and reliability over any electro-mechanical relay alternative. It is a totally electronic device that depends on the electrical, magnetic, and optical properties of semiconductors to control the flow of current in a circuit. It is normally comprised of a low current control side (equivalent to the coil on a mechanical relay) and a high-current load side (equivalent to the contacts of a conventional mechanical relay). SSRs typically feature electrical isolation up to several kilovolts between the control and load sides. Because of this isolation, the load side electronics of the relay is powered from the switched line, such that both the line voltage and a load (additionally to a control signal) must be present for the relay to operate. An SSR contains one or more LEDs in the input (drive) section and provides optical coupling to a phototransistor or photodiode array, which in turn connects to driver circuitry that functions as an interface to the switching device or devices at the output. The power switching device is typically a MOSFET or TRIAC (usually two anti-parallel connected silicon controlled rectifiers, SCRs).

557

Power Electronics

Chapter 13

The advantages of solid-state relays versus their electro-mechanical counterparts are numerous: • Higher reliability, reliable operation in harsh environments, longer life • Elimination of switch bounce since no moving parts, giving a longer lifetime than electromechanical devices • Smaller size • Faster switching times, typically 100µs • Elimination of HV arcing and pitting with reduced electromagnetic interference • Lower triggering currents, that is, low power consumption, compared to electromechanical devices • Robust packaging, resistant to shock and vibration, not dependent upon orientation • No moving parts, thus silent operation In order to utilize the benefits and flexibility of power MOSFET/IGBT technology, it may be required that sophisticated driver circuitry be used to drive these devices. MOSFET/IGBT based SSRs are more versatile than their TRIAC based counterparts. TRIAC based devices are limited only to ac load applications, while MOSFET/IGBT based devices can cater for ac and dc loads. Triac output SSRs are general-purpose relays typically used only for resistive type loads. SCR output solid-state relays are used to switch resistive or inductive loads, especially loads with high inrush currents. Thyristor technology is slower switching than MOSFET/IGBT SSR technology, but can handle higher voltage and current levels.


Input Circuit Commonly referred to as the ‘primary’, the input of an SSR may consist of a simple resistor in series with the optical-isolator, or of a more complex circuit with current regulation, reverse polarity protection, EMC filtering, etc. In either case, both serve the same function, which is to sense the application of a control signal commanding SSR turn on. Optical Isolation The optical isolator in an SSR provides isolation between the input circuitry / control system, and the output circuit connected to the ac mains. The type of optical isolator used may also determine whether it is a zero-crossing or random-fire output. Trigger Circuit This circuitry processes the input signal and switches the output state of the SSR. The trigger circuit may be internal or external to the optical-isolator. Switching Circuit This is the portion of the SSR that switches the power to the load. It usually consists of an IGBT or MOSFET in a dc application, and a triac or parallel connected back-to-back SCRs in an ac application. Protection Circuit Many applications require some form of electrical protection to prevent the SSR from being damaged in the application, or from misfiring due to environmental conditions. The protective devices (RC snubbers and transient voltage suppressors) may be incorporated into the design of an SSR, or mounted externally. output Control signal

Input

Optical Isolation

Power Switching Circuit

Trigger Circuit

Thyristor technology based SSRs are specifically considered in this section, although many of the aspects considered are applicable to MOSFET/IGBT based SSR technology. AC output solid-state relays are used to control the flow of electrical energy in alternating current power systems. The input control (equivalent to the electro-mechanical relay coil) voltages can be either ac or dc. The majority of solid-state relays require less power than electromechanical types to turn on and are readily interfaced. Another advantage of having no moving parts is that solid-state relays offer a fast response time with no contact bounce. For instantaneous turn-on types, the time between applying a command signal to the control circuit and the output circuit turning on is typically 20µs, although 100µs is usually quoted as a maximum. Alternatively, because of the nature of the electronic control circuitry, it is possible to delay the turn-on of a solid-state relay until the next voltage zero of the ac supply. Thus ac output solid-state relays can have two types of turn-on response: instantaneous (also known as phase control or random turn-on) and zero crossing. Zero voltage turn on refers to a control circuit which after the presence of a control signal, only permits the relay’s output to switch on load current if the ac line voltage is at or near a zero ac supply voltage point. Random turn on refers to a control circuit that energizes the relay’s output irrespective of the value of the ac line voltage at the time of the turn-on command. The opto-coupler design and selection determine the zero or random function. All ac output solid-state relays, which use SCRs or triacs as the output switch, after the removal of the control signal, will turn off at the next ac current zero. The relay may conduct for an additional half cycle of the ac supply frequency if the control signal is removed within 100µs of the next current zero. Because of the response time of solid-state relays, power to a load can be applied accurately and removed precisely. This is especially important when applications involve the switching of highly capacitive loads, and is a major advantage over electromechanical switching.

A random-fire SSR may also be used in resistive applications. Some applications require that the load only be energized for a portion of the ac cycle. This can be accomplished with a random SSR (due to its relatively fast turn-on time), given that an appropriate controller is used. However, the initial surge current will be higher due to the SSR switching power when the line voltage is closer to its peak. The key basic element of a solid-state relay is the output switch, sometimes a triac but more often (and more reliably) back-to-back SCRs. This output switch is the key part of a solid-state relay, being the component that handles the power. Circuit description The basic SSR comprises a number of stages, from the control signal input through to the power output stage and its voltage transient protection, as shown by the functional block diagram in figure 13.7.

LOAD

Protection

ac mains External trigger

Figure 13.7. Block diagram of the functional stages of a solid-state relay.

13.1.3i Principle of operation AC output solid-state relays are normally powered by the ac line, by connecting the two gates of the output SCRs through a controlled high voltage switch. In Figure 13.8a, when S1 is closed, the gates of SCR1 and SCR2 are connected, and current from the ac supply flows through either R1 or R2 into the gate of whichever SCR is forward biased; turning the SCR on and the relay conducts. While S1 is closed this action continues, reversing each half cycle of the ac supply and SCR1 and SCR2 conduct alternately. When S1 is opened, whichever SCR is conducting continues to conduct until reversed biased, when it turns off, and since the other SCR now has no gate current, the relay opens. load

R1

50/60Hz SCR

SCR1 SCR2

S1 C1

R2

(a)

Zero-crossing relays are used with resistive loads while random turn-on relays are used with inductive loads, for example motors, transformers, coils, etc. Zero-crossing relays may also be used with inductive loads, but consideration must be given to the power factor of the load. If the load is too inductive, then the output of a zero-crossing relay may half-wave (half-wave rectification of the ac source), whence a random-fire SSR should be used in the application.

558

(b)

S1

R3

Figure 13.8. SSR: (a) back-to-back SCR ac, normally-off output stage and (b) normally-on full-wave diode bridge version.

Either of two circuits can provide the S1 switch function, with both offering optical isolation between the control and output of the solid-state relay. The circuit in Figure 31.9a uses an opto-triac as the isolating element, while the circuit in Figure 13.9b uses an opto-transistor as the isolating element. Each approach has specific features. Optically coupled SCRs are also used, with photovoltaic couplers used in MOSFET output dc relays. The opto-transistor circuit in Figure 13.9b requires less control current to operate, conserving power, space and money in installations that use many relays. Another advantage of the opto-transistor approach is the flexibility offered to modify and tailor the control circuit characteristics in terms of a zero crossing voltage window, noise suppression, etc. The disadvantage of this approach is that it is more expensive. The opto-triac circuit in figure 13.9a requires a higher control current for reliable operation, especially with inductive loads. Additionally, the control circuit characteristics are not accessible so is inflexible. With fewer components, this type of circuit is usually less expensive. With a modified version of the opto-transistor circuit of Figure 13.9b, a normally closed solid-state relay can be designed.

Power Electronics

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Chapter 13

SCR3 R1

SCR2

Rs

(b)

Cs

R2

SCR1

Qp

TVS

R4 R3

R1

SCR2

TVS

(a) R2

Qp

SCR1

TVS

Figure 13.9. Opto-coupled output stage and optional over-voltage protection, interfaced using an: (a) opto-triac and (b) opto-transistor.

Solid-state relays can be either dc or ac voltage controlled, as shown in figure 13.10 parts a and b respectively. For ac input control, in figure 13.10b, the ac signal is rectified and filtered with capacitors to provide a dc signal to the opto-transistor or opto-triac LED in figure 13.9. The ac control versions can also be dc controlled by half-wave rectifying. AC input SSRs are slower to switch on due to the time it takes for the ac signal to increase in magnitude, to be rectified, and filtered to a useful dc current level for the opto-coupler input LED.


560

Although the aluminium oxide ceramic substrate used to isolate the solid-state relay from the copper base plate is a good compromise as a thermal conductor, it has its limitations. The ceramic substrate does not efficiently conduct heat laterally, so by separating the heat source into two elements, more of the substrate is used to conduct the heat vertically through the thickness of the ceramic. Additionally, the two SCRs are attached to their own substantial copper bus-bar lead frames, which further help to spread the heat over a larger area of the ceramic substrate. Even with the extensive use of copper lead frames to spread the heat, the ceramic substrate is the dominant source of thermal impedance, contributing approximately 50% to the total thermal impedance of the relay, from SCR chip to relay copper base-plate. The back-to-back SCR approach is preferred if the relay is subjected to surge currents, because each element is isolated from its partner both thermally and electrically (conduction 180° apart), unlike in a single element triac output. The control circuit determines turn-on and turn-off characteristics, but it is the output silicon switch that is the key to SCR performance. The smaller the SCR die, the lower the cost, but this also results in poorer performance, where the surge (or overload) current is reduced, plus power dissipation and thermal impedance are increased. Reducing the thickness of the silicon can marginally increase surge current rating, the forward voltage drop and, therefore, power dissipation will also be reduced. However, with thinner die, the SCR chip manufacturer experiences yield penalties owing to increased wafer breakage and lower blocking voltage yield, resulting in higher overall manufacturing cost. The blocking voltage of thinner SCR dies will be lower, making the final solid-state relay significantly more susceptible to transient overvoltage damage. This is especially true if the thickness is reduced such that SCR break-over is not due to avalanche break-over but due to punch-through breakdown. If the silicon is susceptible to punch-through breakdown, which is more likely at sub-zero temperatures, any overvoltage will destroy the SCR die, whereas in avalanche breakdown, the SCR will normally self turn-on, conduct for the remainder of the half cycle and then return to its normal blocking condition, undamaged. Thicker silicon die will generally be more rugged relative to overvoltage transients and have a higher blocking voltage rating. The forward voltage drop will be higher, resulting in higher power dissipation and lower surge current capability. The overall die yield will be higher due to less wafer breakage and a higher useful voltage yield, resulting in lower manufacturing cost. Optimized SCR design also involves considerations such as gate current and voltage to fire, holding current, latching current and dv/dt capability.

Current regulator maintains constant current level

LED R1

C3

R2

D1

C1

Q1

current regulator circuit

Q2

R3

Full-wave bridge and input capacitors convert the ac input into a dc signal. Some ac input SSR’s utilize a half-wave bridge, which is essentially a diode, resistor, and capacitor.

R13 33k

R11 6.8k R2 6.8k

D1 D4

R1 33k

D7

+

R12

D2 D3

C5

SSR LED

Q3

D6

+

D5

C1

+ R9 2.7k

C2

(a)

(b) R3 6.8k

series resistors

Input current flows through the input LED embedded in the coupler, which gates on the output device in the coupler.

R10 6.8k

Figure 13.10. SSR input control stage for: (a) regulated dc input circuit and (b) regulated ac input circuit control.

13.1.3ii Key power elements in solid-state relays In most power electronics cases, back-to-back SCRs are used as the output elements of ac output solidstate relays. The back-to-back SCR configuration shown in figure 13.8 has performance advantages when compared with triac outputs, notably higher dv/dt. Triacs have a dv/dt limitation when turning off: the commutating dv/dt of a triac is of the order of 10V/µs. Back-to-back SCRs do not have a commutating dv/dt limitation, just a critical dv/dt which is greater than 500V/µs. Using two output elements (anti-parallel connected, back-to-back SCRs) offers thermal benefits compared with a single triac as the heat dissipated is spread over a wider area of the SSR package substrate ceramic insulator.

13.1.3iii Solid-state relay overvoltage fault modes AC output solid-state relays operate in a wide variety of electrical environments. Some are benign with well-regulated and controlled ac supply lines, unlike others that are hostile with switching transients from a wide variety of sources. These transients can range from insignificant low-voltage, low-energy levels to high-voltage, high-energy pulses. Provided the amplitude of any line-borne voltage transients are below the rated transient voltage of the solid-state relay, safe reliable operation ensues. For relays, generally, these transient voltage ratings are 600V peak for 240V rms rated relays and 1,200V peak for 480V rms rated relays. However, if a relay’s transient voltage rating is exceeded, the relay may be damaged. Generally the relay will break over into uncontrolled conduction and recover at the next current zero with no damage. In other cases, depending on the frequency of break-over and the voltage capability of the various semiconductor elements that are exposed to the transient, the relay can be permanently damaged. Two control circuits used in the ac output of solid-state relays are shown in Figure 13.9. In the circuit in Figure 13.9b, seven elements are exposed to the ac line voltage: two output SCRs, four diodes in the bridge rectifier and the pilot SCR. Of these seven elements, if the lowest break down voltage is the reverse voltage of one of the output SCRs or a bridge diode, any overvoltage transient will permanently damage this element. The result will be a solid-state relay permanently on. If the lowest voltage breakdown voltage is the forward blocking voltage of any of the three SCRs, the SSR will likely break over into conduction without damage. The relay will conduct until the next current zero, then turn off and continue to operate normally. In practice, the lowest voltage breakdown element is normally the pilot SCR (SCR3), which is only forward biased, so it breaks over into conduction and turns on an output SCR (SCR1 or SCR2) through its gate, which is the normal turn-on mechanism for the main SCRs. The relay conducts until the next current zero and then regains control. In Figure 13.10a, three elements are exposed to the ac line voltage: the output SCRs (SCR1 and SCR2) and the opto-triac Qp. If the lowest breakdown voltage level is the reverse voltage of one of the output SCRs, then any over voltage transient will damage it and the relay output will be permanently on. If the lowest breakdown voltage is the forward voltage of one of the output SCRs, it will likely break over into conduction without damage. The relay will conduct until the next current zero, turn off and function normally. If the lowest breakdown element is the opto-triac, Qp, it will likely break over into conduction, turning on an output SCR (SCR1 or SCR2) through its gate, which is the normal turn-on sequence for the main SCRs. The break-over current through Qp is limited by the series resistor R3. If, however, Qp is repeatedly broken over into conduction, it will eventually fail, resulting in the relay being permanently on.

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13.1.3iv Standard transient voltage protection devices, reviewed in terms of SSR requirements MOVs and transorbs are commonly used transient voltage protection devices, in both ac and dc circuits. See Chapter 10.4.

• •

A MOV is a metal oxide varistor which is made from a metal oxide material, typically zinc oxide, and it dissipates energy in the grain structure of the device. It switches into conduction relatively slowly, but can dissipate large levels of energy. A Transient Voltage Suppressor, TVS, or transorb is made from traditional semiconductor silicon material and switches very fast. It can handle large amounts of power, but only for short periods (low energy). It is like a Zener diode and it is used to protect electronic devices from transients. A Transorb functions by clamping any excessive voltage to a specific limit. It does this by conducting when excessive voltage is impressed across its two terminals. For a short time, the transorb absorbs high power. The transorb also reacts within a few nanoseconds making it superior to any traditional transient protection solution.

An MOV can be used to protect a SSR from transients, which can cause the SSR to turn-on without the control voltage applied. An MOV is typically placed externally, in parallel with the output of the SSR, as shown in figure 13.9a. After a MOV reaches its life expectancy, it typically fails shorted. By contrast, a transorb typically does not fail shorted, rather fails open, and is normally installed within the SSR. MOVs are widely used to protect voltage-sensitive elements from overvoltage transients. The MOV has a voltage dependant resistance so that as the voltage increases, its impedance changes from a high resistance to a lower value at some specified voltage. The slope resistance of the characteristic is high, so that in the event of a relatively high current pulse, it can be difficult to coordinate and discriminate the MOV clamping voltage, the protected device voltage rating, and the system operating voltage. However, MOVs are available in a variety of energy absorbing sizes (joule rating) so that a suitable compromise can be made. A significant MOV feature is its wear-out mechanism: every time it absorbs transient energy, its characteristics are changed, normally by the clamping voltage being reduced. Obviously if the MOV clamping voltage degrades to the point where it overlaps the supply voltage, then it will overheat and create a potentially hazardous over-temperature condition. For this reason, MOVs are usually oversized and used with caution. Where transient energy levels are known and are of limited magnitude, the better option is to use TVS clamping diodes or break-over diodes. Both are silicon semiconductor devices with no deterioration mechanism but in modest sizes and costs, they cannot absorb the same amount of energy as an equivalent MOV. The TVS diode exhibits high impedance until its clamping voltage is reached and then essentially goes into a controlled avalanche mode with a low slope resistance. The break-over (or crowbar) diode exhibits a high impedance until its break-over voltage is reached and then breaks down to a low impedance (hence low voltage), thus protecting against high voltage transients. 480V relay rating

I

Option firing point

Peak of 530V rms MOV

20A 16A 12A 8A

V 1200

800

4

TVS 4A

2 2

4ATVS

4

800

1200

V

8A 12A 16A

MOV

20A

480V relay rating

Peak of 530V rms

I

Option firing point

Figure 13.11. Voltage-Current characteristic curves for MOVs, break-over diodes, and TVS’s.


562

Figure 13.11 shows the various voltage levels involved in the protection of a 480V ac solid-state relay, which has a maximum rms voltage rating of 530V rms, resulting in a peak voltage of approximately 750V, as shown on Figure 13.11. Solid-state relays rated at 480V rms are normally tested at three times this level, 1,200V peak, shown as the ‘480V relay rating’ in Figure 13.11. A typical MOV clamping curve is shown, starting to clamp at about 900V but with a relatively high resistive component taking the clamping voltage above the relay rating if the voltage transient can supply about 21A peak. Also shown in Figure 13.11, 1100V is the typical breakdown voltage of the type of TVS that is used to protect a relay. The current in the internal TVS will never reach the 4A shown, indicating the much lower slope resistance of TVS protectors. In most cases, the internal TVS diode will trigger the relay before the TVS current reaches 100mA. Although this energy level may appear high, it is spread over a number of series TVS elements, which yield excellent thermal management and dissipation paths. Figure 13.9 shows the SSR output stage protected by an external parallel-connected RC snubber circuit. An RC snubber is more effective for dv/dt suppression than for transient over-voltage protection. The snubber losses, CV2, are higher than those in MOV type protection, since the RC snubber is active during normal ac operation, as opposed to only being functional during a transient over-voltage situation in the MOV case. The energy associated with the MOV capacitance continually being cycled, limits its upper operating frequency. 13.1.3v Solid-state relay internal protection methods Because of the problems associated with MOVs, particularly the possibility of over heating and lifetime clamping voltage downward drift, solid-state relays tend not to be supplied with internal MOVs. Certain applications may employ TVS diodes (as shown by the dotted line connections in the two parts of Figure 13.9), connected to the gates of the output SCRs, which will conduct at voltages above maximum line voltage and below the voltage rating of the solid-state relay. If a transient voltage occurs, the TVS diodes conduct and normal gate current flows into the gates of the output SCRs, and the forward biased SCR turns on. This is the standard turn-on sequence for the solid-state relay output SCRs; they are turned on by the normal injection of gate current and no component is overstressed.

This internal overvoltage protection is available on specific solid-state relays. • Generally, for resistive loads TVS over-voltage protection is suitable, provided the load can tolerate the transfer of the transient to the load. • For capacitive loads, it is inadvisable to use internal TVS protection as this could lead to high inrush (surge) currents and possibly latent or catastrophic di/dt failures. • In some motor start and stop applications TVS protection may be suitable depending on the motor load, the effects of a sudden, undesired small movement of the motor, etc. This form of protection cannot be used with motor reversing applications. This poses the significant danger of two relays (for forward and reverse operation) being turned on by a transient, resulting in a line-to-line short that damages the relays and other circuit elements. 13.1.3vi Application considerations Different applications require different solid-state relay characteristics. Generally, the two turn-on methods, zero-crossing (for minimum EMC) or instantaneous, have specific application areas. However, there are general guidelines governing when either should be used, or not used. If the load requires proportional control every ac half cycle (such as incandescent lamp dimming or low thermal mass temperature control), the instantaneous turn-on type is used. For high thermal mass loads, a zero-crossing relay with complete cycles of conduction and non-conduction is usually the preferred method of temperature control. A zero-crossing relay is generally used for inductive loads. However, for these types of loads a random turn-on type should always be considered. Under certain low load current and low power factor conditions it is possible for a zero-crossing relay to conduct only on every other half cycle (half-waving). This is caused by the relay terminal voltage rising so rapidly through the zero cross voltage window (at the lagging current zero) that the relay control circuit does not have time to react and so is locked off until the next voltage zero. With a random turn-on SSR type, there is no zero crossing window so no possibility of the relay half-waving. If in doubt, use a random turn-on relay for inductive loads. Minimum load current is the least conducting current that the SSR will switch on and continue to carry with a nominal output voltage drop. Load currents less than this value, typically 50 to 100mA, may not be switched by the SSR.

The most common failure mode of an SSR is a shorted output, either half-wave or fully shorted, caused by excess load current flow or over temperature. The most common end of life failure is an open circuit as a result of thermal fatigue of internal solder joints and substrate. In general, the best means to avoid such failures or prolong the life of an SSR is to operate at the lowest possible temperature and avoid large temperature excursions. Applications that have repetitive current surges should employ a higher current rated SSR to accommodate the heating caused by the surges.

Power Electronics

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Chapter 13

Example 13.3: Solid-state relay turn-on


564

Relay Connections Because the input and output terminals of dc solid-state relays are electrically isolated by up to 3,750V rms, the relative electrical potentials of the input signal and load connections are irrelevant. As shown in Figure 13.12, the input can be supplied either from a source or sink configuration and the load can be connected to either the relay positive or negative output terminals. The solid-state relay can be used as a level shifter because no electrical relationship is required between the input control and power output sections of the relay.

Calculate the expected turn-on (trigger) voltage of an ac output SSR using SCRs and a trigger circuit, as in figure 13.9a, with the following parameters: Igt = 50mA, for both SCRs (minimum gate current for turn-on at 25°C) Vgt = 0.7V for each SCR (minimum gate voltage for turn-on at 25°C) Single opto-coupler with 1.0V Vf drop Trigger circuit impedance of 68Ω. No Rgk resistor.

Inductive Load Considerations When the dc load is inductive, precautions have to be taken to protect the solid-state relay at turn off. Energy is stored in the magnetic flux created by the current flowing through the inductive load. When the solid-state relay is turned off the collapse of the magnetic flux dΦ/dt creates an electro-magnetic force with a polarity that tries to maintain the pre-existing current flow. This is shown schematically in Figure 13.13.

Solution

With the aid of figure 13.9a: Trigger circuit drop: 50mA x 68Ω= 3.4V. SCR gate drops: 0.7V x 2 = 1.4V. The expected turn-on (trigger) voltage: 3.4V + 1.4V + 1.0V coupler drop = 5.8V.

VSSR = VBR

VSSR = E + VLOAD

inductive load

dc SSR

This turn on or trigger voltage constitutes the lower value of the zero turn-on ‘window’. ♣

+

E

Example 13.4: Solid-state relay heatsink requirements

R i

-

A solid-state relay carries 50A in an application with a forward voltage drop Vf of 1.1V pk, resulting in 55W of power being dissipated. The ambient temperature is 35ºC, giving a 45ºC difference between ambient and the maximum recommended base plate temperature of 80ºC. What is the heat-sinking requirement?

Z

+ VR = iR

E

--

L

inductive load

dc SSR

VL = L

+

+ +

VBR -

di

+

R

VR = iR

i

-

VL = iR + VBR − E

L

dt

(a)

+

(b)

Figure 13.13. Inductive loads with dc solid-state relays: (a) circuit connection and (b) induced voltages at turn-off.

Solution

If no electrical path is provided for the inductive load current to flow, the rapid collapse of magnetic flux will generate a voltage high enough to break-over any limiting voltage element in the output load circuit. One element is usually the solid-state relay, shown schematically as VBR. In the case of a solid-state relay, either the output power semiconductor device or one of the driving semiconductors will break-over into conduction, which may permanently damage the semiconductor resulting in a relay with a permanently shorted output. In most dc circuits, a circulating path for the inductive current can be created by the addition of a freewheel diode as shown in Figure 13.14a. Unless the solid-state relay is to be turned on while current is still flowing in the freewheel diode, the diode can be a standard recovery type. If, however, the solid-state relay may need to turn on before the load current has been completely decayed to zero, then a fast recovery diode must be used in the freewheel position. The use of a fast recovery diode reduces the instantaneous reverse recovery inrush current amplitude and duration when the relay is turned on into an existing freewheel diode current.

Division of the 45ºC temperature differential by the 55W of power being dissipated, results in a 0.82ºC/W heat sink requirement for the application. Prudently, 0.1ºC/W is deduced from the result to account for the thermal compound used in the assembly. Therefore, a 0.82ºC/W heat sink less 0.1ºC/W is 0.72ºC/W. The heat sink needed requires a thermal resistance of no more than 0.7ºC/W. ♣ 13.1.3vii DC output solid-state relays DC output SSRs rated to 400V dc are usually MOSFET output based, while 1000V dc, 25A SSRs have an IGBT output stage. Both dc SSR types are usually dc input controlled. DC output solid-state relays are used for switching dc since, unlike dc electromechanical relays, there are no moving parts, hence no contact arcing or wear-out mechanism. However, there are some precautions, which have to be assessed when using dc output solid-state relays with inductive dc loads. on/off

+ Econtrol

+ -

dc SSR

Epower

resistive load

-

VLoad = iR

R i

+ Econtrol

+

+ -

dc SSR

Epower

-

VLoad = iR

R i

+

on/off

VLoad = iR

on/off

Econtrol

+ -

dc SSR

+ R

resistive load

+ Epower

i

VLoad = iR

Econtrol

+ -

dc SSR

+ R

resistive load

inductive load

dc SSR

resistive load

-

VSSR = E + VD + V Z

V SSR = E + VD

E

R

+ VD

-

D L i

dc SSR

VSSR = E + VD + V Z inductive load

+ VR = iR

--

VL = iR + VD

+

E

+

R

VD

D

VZ

Z

i

L

+

VR = iR

-

VL = iR + VD + V Z

+

inductive load

dc SSR

E

+

R

Z

VZ

L

i

+

VR = iR

-

VL = iR + V Z − E

+

Figure 13.14. The dc output SSR with an inductive load incorporating: (a) a load freewheel diode; (b) load diode/Zener diode combination; and (c) a Zener diode across the dc SSR output alternative.

+ Epower

i

on/off

Figure 13.12. Control and load connection possibilities for dc output solid-state relays.

Generally, it is necessary to collapse the inductive current rapidly, for example, to open a solenoid as quickly as possible. If rapid current discharge is a requirement, then, the discharge path must be designed with a high voltage generated. This follows from the fact E = Ldi/dt, where E is the voltage generated by the collapse of magnetic flux, L is the inductance of the load and di/dt is the rate of change of current. The greater the value of E , for a fixed value of load L, then the greater the di/dt and the more rapidly the load current is reduced to zero. Increasing the voltage, which has to be generated to create a freewheel path, can be accomplished by adding to the diode shown in Figure 13.14a, a series Zener or

Power Electronics

565

Chapter 13

TVS diode as shown in Figure 13.14b. The voltage appearing across the solid-state relay is the sum of the supply voltage and the Zener or TVS diode voltage. So for a system using a dc supply of E and a solid-state relay voltage rated at VR, the voltage across the freewheel components cannot be greater than VBR - E at maximum load current. An alternate method to create the same inductor voltage is to connect the Zener or TVS diode externally across the output terminals of the solid-state relay, as shown in figure 13.14c (and internally in figure 13.13b), in this case the clamping voltage can be VBR, the voltage rating of the dc SSR. As this voltage is in series with the dc supply E, the net result is the same as putting the clamping component across the load, a voltage of VBR - E is generated by the inductive load. The energy loss in the clamping device is greater in this case, since the freewheel path involves energy being drawn from the dc source. However, importantly, the voltage clamping protection is directly across the primary component to be protected, viz., the SSR, and even better if placed inside the SSR module as shown in figure 13.14b. 13.2

Single-phase transformer tap-changer – line commutated

Figure 13.15 shows a single-phase tap changer using two ac output solid-state relays, where the tapped ac voltage supply can be provided by a tapped transformer or autotransformer. Thyristor T3 (T4) is triggered at zero voltage cross-over (or later), subsequently under phase control T1 (T2) is turned on. The output voltage (and current) for a resistive load R is defined by vo (ωt ) = io (ωt ) × R = 2 V2 sin ωt (V) (13.57) (rad) for 0 ≤ ωt ≤ α vo (ωt ) = io (ωt ) × R = 2 V1 sin ωt


Initially v2 is impressed across the load, via T3 (T4). Turning on T1 (T2) reverse-biases T3 (T4), hence T3 (T4) turns off and the load voltage jumps to v1. It is possible to vary the rms load voltage between v2 and v1. It is important that T1 (T2) and T4 (T3) do not conduct simultaneously, since such conduction shortcircuits the transformer secondary. Both load current and voltage information (specifically zero crossing) is necessary with inductive and capacitive loads, if winding short circuiting is to be avoided. With an inductive load circuit, when only T1 and T2 conduct, the output current is 2V io = sin (ωt − φ ) (A) (13.62) Z 2 2 −1 where Z = R + (ω L) (ohms) φ = tan ω L / R (rad) It is important that T3 and T4 are not fired until α ≥ φ , when the load current must have reached zero. Otherwise a transformer secondary short circuit occurs through T1 (T2) and T4 (T3). For a resistive load, the thyristor rms currents for T3, T4 and T1, T2 respectively are V2 1 ITrms = ( 2α − sin 2α ) 2R π (13.63) V1 1 ITrms = ( sin 2α − 2α ) + 2π 2R π

√2×11sinωt

Vo=IoR

(V)

566

√2×23sinωt

(13.58)

(rad) for α ≤ ωt ≤ π where α is the phase delay angle and v2 < v1. If 0 ≤ δ = V2 / V1 ≤ 1, then for a resistive load the rms output voltage is ½

 1 V 2  V2  Vrms =  π2 (α − ½ sin 2α ) + π1 (π − α + ½ sin 2α )  = V1  1 − π (1 − δ 2 ) (α − ½ sin 2α )     

ID2

ID1

½

(13.59)

o

IT1

IT2

IT1

α=90º

π

IT2

ID1

ID2

2π

3π

4π

ωt

Ip √2×23sinωt VT1

√2×5.26sinωt

ωt VD1

α=90º

α

Ip

Vo

Vp

α

Io

= δv1 o

VD1 Figure 13.15. An ac voltage regulator using a tapped transformer: (a) circuit connection and (b) output voltage waveform with a resistive load.

α=90º

π

2π

3π

4π

ωt

ID2 IT2

√2×230sinωt

√2×110sinωt

√2×340sinωt (b)

(a)

√2×120sinωt ωt

The Fourier coefficients of the output voltage, which has only odd harmonics, are 2 1−δ an = V  cos α cos n α + n sin α sin n α − 1 π 1 − n2  2 1−δ ( cos α sin nα − n sin α cos n α ) π 1 − n2 The amplitude of the fundamental quadrature components, n = 1, are 1 a1 = V (1 − δ ) sin2 α

α=90º

VT1

(13.60)

bn = V

π

b1 = V

1

(1 − δ ) (α sin π

2

α − cos 2 α − sin α cos α )

√2×230sinωt √2×460sinωt

(13.61)

Figure 13.16. An ac voltage regulator using a tapped transformer connected as a rectifier with a resistive load: (a) circuit diagram and symbols and (b) circuit waveforms, viz., output voltage and current, transformer primary current, diode reverse blocking voltage, and thyristor blocking voltages.

Power Electronics

567

Chapter 13

The thyristor voltages ratings are both v1 - v2, provided a thyristor is always conducting at any instant. An extension of the basic operating principle is to use phase control on thyristors T3 and T4 as well as T1 and T2. It is also possible to use tap-changing in the primary circuit. The basic principle can also be extended from a single tap secondary to a multi-tap transformer.

π I rmsT =  1 2π ∫



switch up in voltage when the load V and I have the same direction, delivering power switch down when V and I have the opposite direction, returning power.

2

The peak diode voltage is associated with the turn-on of the thyristor associated with the other half cycle of the supply and worst case is when α 1   n  The carrier (switching frequency) components can be filtered by using an output L-C filter, as shown in figure 13.17a, which has a cut-off frequency of f½ complying with fo < f½ < fs. .

.

The primary rms current has two components. When the diode conducts the primary current is 110V 110V sin ωt = 2 × 5.26 sin ωt i p1 = 2 × 230V 10Ω 230V 230V sin ωt = 2 × 23 sin ωt i p2 = 2 × 230V 10Ω

0 ≤ ωt ≤ α

α ≤ ωt ≤ π

I rmsD =  1 2π ∫ 

0

(

)

2 × 5.26 sin2 ωt d ωt   2

v o = 2V

½

½  1  = 2 × 5.26  1 4π {α − ½ sin 2α )} = 2 × 5.26   = 2.63A 2 2 

{

}

Rather than using a variable duty cycle to control the output magnitude, selective harmonic elimination, SHE, can be used, where the switches are commutated at pre-calculated angles so as to eliminate specific harmonics, and control the fundamental magnitude of the output voltage. T1/T3 are turned on at switching angles α1, α3, ….αM-1 and turned off at α2, α4, …αM per quarter cycle. The quarter-wave symmetry results in null even harmonics, including any dc component. By the proper choice of PWM switching angles, αi, the fundamental component can be controlled and selected low order harmonics can be eliminated. The Fourier series for the output voltage, which is expressed in terms of the M switching point variables per quarter cycle, is:

The rms of each component, on the primary side, is α

½

V D = 2 × 230V + 2 × 110V = 466.7V and 466.7×sinα for α>½π.

The converter circuit shown in figure 13.16 is a form of ac to dc tap changer, with a 230V ac primary. The inner voltage taps can deliver 110V ac while the outer tap develops 230V ac across the 10Ω resistive load. If the thyristor phase delay angle is 90º determine i. The mean load voltage hence mean load current ii. The average diode and thyristor current iii. The primary rms current iv. The peak thyristor and diode voltage, for any phase angle

iii.

)

2 × 23 sin2 ωt d ωt  

= 2.632 + 2.632 + 11.52 + 11.52 = 16.68A

Example 13.5: Tap changing converter

ii.

(

2 2 2 2 I p = I rmsD + I rmsD + I rmsT + I rmsT

iv.

i.

α

568

½  1  = 2 × 23  1 4π {(π − α ) + ½ sin 2α )} = 2 × 23   = 11.5A 2 2  The total supply side rms current comprised the contribution of two diodes and two thyristors

The basic operating principle of any multi-output tap changer, in order to avoid short circuits, independent of the load power factor is • •


where the value of an is:

an =

2

π

M

∑ ( −1) i =1

j

∞

∑

n =1,3,5....

an sin ωt

 sin (n − 1) αi sin (n + 1) αi  −   (n + 1)   (n − 1)

Power Electronics

569

Chapter 13

where n = 3, 5,..., 2M −1, M is the number of switching angles per quarter cycle, αi is the ith switching angles and √2V is the maximum value of the input voltage. The rms fundamental component is given by: j 2 ∞  V a1 =V  1 +  ∑ ( −1) αi − ½ sin 2αi  π  n =3,5,7..  The commutation angle selection to eliminate certain harmonics is addressed in Chapter 15.3.4viii.

T2 on T1

T4 on T3

T2 on T1 fs

δ=¾

13.4


570

Three-phase ac regulator

13.4.1 Fully-controlled three-phase ac regulator with wye load and isolated neutral

The power to a three-phase star or delta-connected load may be controlled by the ac regulator shown in figure 13.18a with a star-connected load shown. The circuit is commonly used to soft start three-phase induction motors. If a neutral connection is made, load current can flow provided at least one thyristor is conducting. At high power levels, neutral connection is to be avoided, because of load triplen currents that may flow through the phase inputs and the neutral. With a balanced delta connected load, no triplen or even harmonic currents occur. If the regulator devices in figure 13.18a, without the neutral connected, were diodes, each would conduct for ½π in the order T1 to T6 at ⅓π radians apart. As thyristors, conduction is from α to ½π. Purely resistive load

fundamental

0

In the fully controlled ac regulator of figure 13.18a without a neutral connection, at least two devices must conduct for power to be delivered to the load. The thyristor trigger sequence is as follows. If thyristor T1 is triggered at α, then for a symmetrical three-phase load voltage, the other trigger angles are T3 at α + ⅔π and T5 at α + 4π/3. For the antiparallel devices, T4 (which is in antiparallel with T1) is triggered at α + π, T6 at α + 5π/3, and finally T2 at α + 7π/3.

fo

δ≈¾

ωt

π

ia a

(c)

ZL

b T2 on T1

T4 on T3

T2 on T1

ib

fs

δ=¼

ZL

L O A D

ZL

c ic

(c)

fo

δ≈¼

0

v a = 2V sin (ωt ) .

T5 T6

T6 T1

T1 T2

T2 T3

v b = 2V sin (ωt − 23 π ) .

v c = 2V sin (ωt − 43 π ) .

ωt

π

1

Optional tapped neutral

T5 T6 T5 T6 T6 T1 T1 T6 T1 T1 T2 T2

fundamental

Power factor phasecontrol, α equation

(b)

¾

p e r u n it

4th

3rd

T3

Power factor acchopper, δ

2nd

½

va ½(va-vc)

(d)

fundamental

a c

¼

s u p p l y

½(va-vb)

L-C filter

T1

R

ac 2 V sin ωt

L T4

L O A D

vo

va

½(va-vc)

½(va-vc)

(a)

T2

0 0

¼

½ on-statedutycycle

¾

1

δ

Figure 13.17. An ac voltage regulator using a chopper, with commutable switches: (a) circuit configuration and output voltage waveform with a resistive load at (b) low modulation, δ≈¼; (c) high modulation, δ≈¾; and (d) harmonic characteristics.

T6 T1

T1 T2

T6 T1

T1 T2

Figure 13.18. Three-phase ac full-wave voltage controller: (a) circuit connection with a star load; (b) phase a, line-to-load neutral voltage waveforms for four firing delay angles; and (c) delta load.

Power Electronics

571

Chapter 13

Figure 13.18b shows resistive load, line-to-neutral voltage waveforms (which are symmetrical about zero volts) for four different phase delay angles, α. Three distinctive conduction periods, plus a nonconduction period, exist. The waveforms in figure 13.18b are useful in determining the required bounds of integration. When three regulator thyristors conduct, the voltage (and the current) is of the ∧ V form when two devices conduct, the voltage (and the current) is of the form 3 sin φ , while ∧ ∧ V sin ( φ − 1 π ) . V is the maximum line voltage,√3 √2V. 2 6 i. 0 ≤ α ≤ ⅓π [mode 3/2] – alternating every π between 2 and 3 conducting thyristors, Full output occurs when α = 0, when the load voltage is the supply voltage and each thyristor conducts for π. For α ≤ ⅓π, in each half cycle, three alternating devices conduct and one will be turned off by natural commutation. The output voltage is continuous. Only for ωt ≤ ⅓π can three sequential devices be on simultaneously. Examination of the α = ¼π waveform in figure 13.18b shows the voltage waveform is made from five sinusoidal segments. The rms load voltage per phase (line to neutral), for a resistive load, is Vrms

 1 =V  π  ∧

    

∫

π

α

3

1 3

sin 2φ dφ + ∫ +∫

2 2

1 1

3 π +α

3π

1 4

sin 2 ( φ + π ) dφ + ∫

3 π +α

3π

1 4

1

6

sin 2 (φ − π ) dφ + ∫ 1

6

Vrms = I rms R = V 1 − 23π α + 43π sin 2α 

π 2

1 3

2 1

3π

1 3

sin 2φ dφ

3π +α

sin 2φ dφ

3π +α

    

½

(13.66)

The Fourier coefficients of the fundamental frequency are 3 3 a1 = V ( cos 2α − 1) b1 = V ( sin 2α + 43 π − 2α ) (13.67) 4π 4π Using the five integration terms as in equation (13.66), not squared, gives the average half-wave (half-cycle) load voltage, hence specifies the average thyristor current requirement with a resistive load. That is π ½cycle 1 Vo = 2 × I T R = 2V sin ωt d ωt 2π α∫ (13.68) ½cycle 2V = 2 × IT R = Vo (1 + cos α )

π

∧

2V . πR

ii. ⅓π ≤ α ≤ ½π [mode 2/2] – two conducting thyristors The turning on of one device naturally commutates another conducting device and only two phases can be conducting, that is, only two thyristors conduct at any time. Two phases experience half the difference of their input phase voltages, while the off thyristor is reverse biased by 3/2 its phase voltage, (off with zero current). The line-to-neutral load voltage waveforms for α = ⅓π and ½π, which are continuous, are shown in figures 13.18b. Examination of the α = ⅓π or α = ½π waveforms in figure 13.18b show the voltage waveform is comprised from two segments. The rms load voltage per phase, for a resistive load, is ∧  Vrms = V  π1 

{∫

1 π +α 3

α

1 4

sin 2 ( φ + π ) dφ 1

6

+∫

2 π +α 3

1

1 π +4α 3

sin 2 (φ − π ) dφ 1

6

}

  

½

½

½

Vrms = I rms R = V ½ + 89π sin 2α + 38π3 cos 2α  = V ½ + 34π3 sin ( 2α + π 6 )      The Fourier co-efficients of the fundamental frequency are 3 3 a1 = V cos 2α − cos 2 (α − π3 ) b1 = V 23π + sin 2α − sin 2 (α − π3 ) 4π 4π The non-fundamental harmonic magnitudes are independent of α, and are given by 3 for h = 6k ± 1 k = 1, 2, 3,.. Vh = ×V × sin ( h ± 1) π 6 π ( h ± 1)

(

)

(

)

(13.69)

(13.70)

(13.71)

Using the same two integration terms, not squared, gives the average half-wave (half-cycle) load voltage, hence specifies the average thyristor current with a resistive load. That is 1 π +α 2 π +α ½cycle 1 3 Vo = 2 × I T R = 3 2V sin (ωt + 1 6 π ) d ωt + ∫ 13 sin (ωt − 1 6 π ) d ωt π +α 2π ∫ α 3 (13.72) ½cycle π 3 2V  = 2 × IT R = Vo sin  α +  π 3 

572

iii. ½π ≤ α ≤ π [mode 2/0] – either 2 or no conducting thyristors Two devices must be triggered in order to establish load current and only two devices conduct at anytime. Line-to-neutral zero voltage periods occur and each device must be retriggered ⅓π after the initial trigger pulse. These zero output periods (discontinuous load voltage) which develop for α ≥ ½π can be seen in figure 13.18b and are due to a previously on device commutating at ωt = π then re-conducting at α +⅓π. Except for regulator start up, the second firing pulse is not necessary if α ≤ ½π. Examination of the α = ¾π waveform in figure 13.18b shows the voltage waveform is made from two discontinuous voltage segments. The rms load voltage per phase, for a resistive load, is ∧  Vrms = V  π1 

{∫

5π 6

α

1 4

sin 2 ( φ + π ) dθ + ∫ 1

6

7π 6

1

}

 sin 2 (φ − π ) dφ   1

4 1π + α 3

6

½

½

Vrms = I rms R = V  45 − 23π α + 83π sin 2α + 38π3 cos 2α  = V  45 − 23π α + 43π sin ( 2α + 1 3 π ) (13.73)   The Fourier co-efficients of the fundamental frequency are 3 3 a1 = − V 1 + cos 2 (α − 13 π ) b1 = V 53 π − 2α − sin 2 (α − 13 π ) (13.74) 4π 4π Using the same two integration terms, not squared, gives the average half-wave (half-cycle) load voltage, hence specifies the average thyristor current with a resistive load. That is ½cycle 3 2V 1 + cos α + π Vo = 2 × IT R = (13.75) 6 π

(

½

The thyristor maximum average current is when α = 0, that is I T =


)

½

(

(

)

))

(

iv. π ≤ α ≤ π [mode 0] – no conducting thyristors The interphase voltage falls to zero at α = π, hence for α ≥ π the output becomes zero. In each case the phase current and line to line voltage are related by VLrms = 3 I rms R and the peak 2 voltage is V = 2 VL = 6 V . For a resistive load, load power 3I rms R for all load types, and V rms = I rms R . Both the line input and load current harmonics occur at 6n±1 times the fundamental. Inductive-resistive load

Once inductance is incorporated into the load, current can only flow if the phase angle is at least equal to the load phase angle, given by φ = tan−1 ωL R .Due to the possibility of continuation of the load current because of the stored inductive load energy, only two thyristor operational modes occur. The initial mode at φ ≤ α operates with three then two conducting thyristors mode [3/2], then as the control angle increases, operation in a mode [2/0] occurs with either two devices conducting or all three off, until α = π. The transitions between 3 and 2 thyristors conducting and between the two modes involves solutions to transcendental equations, and the rms output voltage, whence currents, depend on the solution to these equations. Purely inductive load

For a purely inductive load the natural ac power factor angle is ½π, where the current lags the voltage by ½π. Therefore control for such a load starts from α = ½π, and since the average inductor voltage must be zero, conduction is symmetrical about π and ceases at 2π - α. The conduction period is 2(π- α). Two distinct conduction periods exist. i. ½π ≤ α ≤ ⅔π [mode 3/2] – either 2 or 3 conducting thyristors Either two or three phases conduct and five integration terms give the load half cycle average voltage, whence average thyristor current, as ½cycle 2 2V 2 cos α − 3 sin α + 1 + 3 Vo = (13.76)

π

(

)

The thyristor maximum average current is when α=½π. When only two thyristors conduct, the phase current during the conduction period is given by 2V  3 3 π   i (ωt ) = cos  ωt +   (13.77)  cos α − ωL  2 2 6    The load phase rms voltage and current are

V rms = V

( 52 − π3 α + 23π sin 2α )

½

(

V 5 3 − α + 7 − π6 α cos 2 α + 29π sin 2α ωL 2 π The magnitude of the sin term fundamental (a1 = 0) is I rms =

V1 = b1 =

(

3 V 2π

)

( 53 π − 2α + sin 2α ) = I ωL 1

)

½

(13.78)

(13.79)

Power Electronics

573

while the remaining harmonics (ah = 0) are given by 3  sin ( h + 1) α sin ( h − 1) α V h = bh = V  + π  h +1 h −1

Equation (13.66)

normalised ave ½ half cycle voltages, R and L loads

normalised rms voltages, R and L loads

1 Equation (13.78)

0.75

VL

VR Equation (13.69)

0.5

V rms V

0.25

Equation (13.84) Equation (13.73)

0 0

30

60

90

120

(b)

(c)

(d)

Equation (13.78)

IL

I L ωL V

0.25

Equation (13.84)

0 0

30

60

90

120

IT = 2×

1 2π

5 π −α 3

∫

3 2V  π π     cos  α +  − cos  ωt +   d ωt 2ωL  6 6   

(13.82) 3 2V   5 π π     2 cos 2 sin π α α α − + − +      2πωL  3 6  6      When two thyristors conduct, the phase current during the conduction period is given by 2V 3  π π    i (ωt ) = (13.83)  cos  α +  − cos  ωt +   ωL 2  6 6    The load phase rms voltage and current are

1 2√2/π

Equation (13.68)

0.75

Equation (13.76)

V rms = V Equation (13.72)

0.5

I rms =

V½L

α

(

V ωL

5 2

− π3 α +

3 2π

sin ( 2α + 13 π )

)

½

 5 3α   6α  9 + 5 − cos 2 (α + 16 π ) + sin ( 2α + 16 π )   − π  2π  2 π 

(13.84)

½

V½R

Vo V

½

0.25


0 30

60

90

120

150

The magnitude of the sin term fundamental (a1 = 0) is 3 V1 = b1 = V 53 π − 2α − sin 2 (α − 13 π ) = I 1ωL (13.85) 2π while the remaining harmonics (ah = 0) are given by 3  sin ( h ± 1) α sin ( h ∓ 1)(α − 13 π )  (13.86) V h = bh = ± V  +  for h = 6k ∓ 1  h ±1 h ∓1 π   Various normalised voltage and current characteristics for resistive and inductive equations derived are shown in figure 13.19.

(

)

13.4.2 Fully-controlled three-phase ac regulator with wye load and neutral connected

1

If the load and supply neutral is connected in the three-phase thyristor controller with a wye load as shown in figure 13.20 and dashed in figure 13.18a, then (possibly undesirably) neutral current can flow and each of the three loads can be controlled independently. Undesirably, the third harmonic and its odd multiples are algebraically summed and returned to the supply via the neutral connection. At any instant iN = ia + ib + ic.

VRo Equation (13.67)

0.75

Equation (13.79)

v1 V

0.25

N

VLo

Equation (13.70)

0.5

Equation (13.85)

30

A

T1

B

T3

C

T5

RL T4

Equation (13.74)

0 0

150

574

=

delay angle α

normalised fundamental output voltage R & L load

normalised output current, with L load

1

0.5

(13.80)

0

(a)


The average thyristor current is given by    

150

delay angle α

0.75

Chapter 13

60

90

120

RL T6

150

delay angle α

delay angle α

Figure 13.19. Three-phase ac full-wave voltage controller characteristics for purely resistive and inductive loads: (a) normalised rms output voltages; (b) normalised half-cycle average voltages; (c) normalised output current for a purely inductive load; and (d) fundamental ac output voltage.

ii. ⅔π ≤ α ≤ π [mode 2/0] – either 2 or no conducting thyristors Discontinuous current flows in two phases, in two periods per half cycle and two integration terms (reduced to one after time shifting) give the load half cycle average voltage, whence average thyristor current, as ½cycle 2 2V 3 1 + cos α + π Vo = (13.81) 6 π

(

which reduces to zero volts at α = π.

(

))

RL T2

Figure 13.20. Three-phase ac full-wave 4-wire star-load ac controller.

For a resistive balanced load there are three modes of thyristor conduction. When 3 thyristors conduct ia + ib + ic =IN = 0, two thyristor conduct I N = − 2V .

one thyristor I N = I T =

2V

.

sin ωt . R

R

sin (ωt − 43 π ) , and for

Power Electronics

575

Mode [3/2]

Chapter 13

Mode [1/0]

0 ≤ α ≤ ⅓π

Periods of zero neutral current occur when three thyristors conduct and the rms of the discontinuous neutral current is given by

I N2 =

3

α +π 3

∫

π

π

 − 2V sin (ωt − 43 π ) dt  R  

I N2 =

IN =

½

(13.87)

3 2V

(1 − cos α )

πR

(13.88)

At α = 0°, no neutral current flows since the load is seen as a balance load supplied by the three-phase ac supply, without an interposing controller.

2

π

3  2V sin ωt   dt R π α∫   .

V 3 × (π − α + ½ sin 2α ) R  π 

½

(13.92)

The average neutral current is 3 2V

(13.93) (1 + cos α ) πR The neutral current is greater than the line current until the phase delay angle α > 67°. The neutral current reduces to zero when α = π, since no thyristors conduct. The normalised neutral current characteristics are shown plotted in figure 13.21.

IN =

The average neutral current is

Mode [2/1]

The neutral current is due to only one thyristor conducting. The rms neutral current is given by

.

3

576

⅔π ≤ α ≤ π

2

V 3  I N = ×  (α − ½ sin 2α )  R π 

IN =


13.4.3 Fully-controlled three-phase ac regulator with delta load

⅓π ≤ α ≤ ⅔π

From α to ⅔π two phase conduct and after ⅔π the neutral current is due to one thyristor conducting. The rms neutral current is given by

I N2 =

2π

3

2



3

2V

∫  −

π

R

.

α

sin (ωt − 43 π ) dt + 3 π 

α +π 3

∫

2π

A

T1

B

T3

C

T5

RL T4

2

 2V sin ωt    dt R   .

3

½

 V  3 3 I N = × 1 − cos 2 α  π R   Maximum rms neutral current occurs at α = ½π, when IN = V/R.

(13.89)

.

RL T6

The average neutral current is

IN =

3 2V

πR

(

3 sin α − 1

)

(13.90)

The maximum average neutral current, at α = ½π, is 3 2V V IN = 3 − 1 = 0.9886

(

rms and average neutral current

πR

)

(13.91)

R

Equation (13.89)

1

0.75


0.5

rms neutral current

I rms V R

average neutral current

IN V R

Equation (13.88)

Figure 13.22. Three-phase ac full-wave 3-wire delta-load ac controller.

The load in figure 13.18a can be replaced with the start delta in figure 13.18c or figure 13.22. Star and delta load equivalence applies in terms of the same line voltage, line current, and thyristor voltages, provided the load is linear. A delta connected load can be considered to be three independent single phase ac regulators, where the total power (for a balanced load) is three times that of one regulator, that is

Power = 3 ×VI 1 cos φ1 =

.

3VI L1 cos φ1

(13.94)

In load delta connection For delta-connected loads where each phase end is accessible, the regulator shown in figure 13.23 can be employed in order to reduce thyristor current ratings. Each phase forms a separate single-phase ac controller as considered in section 13.1 but the phase voltage is the line-to-line voltage, √3V.

Equation (13.93)

0 30

T2

Equation (13.92)

0.25

0

RL

60

90

120

150

180

delay angle

For a resistive load, the phase rms voltage, hence current, given by equations (13.23) and (13.24) are increased by √3, viz.: 2  1 π  Vrms =  2 ∫ 2V sin ωt dt  ½ 2 π α  

(

)

½

Figure 13.21. Three-phase ac full-wave voltage neutral-connected controller with resistive load, normalised rms neutral current and normalised average neutral current.

 α sin 2α  Vrms = 3 V 1 − + (13.95) = 3 I rms R 0≤α ≤π 2π   π The line current is related to the sum of two phase currents, each phase shifted by 120º. For a resistive delta load, three modes of phase angle dependent modes of operation can occur.

Power Electronics

577

Chapter 13

Mode [3/2]

1.75 Equation (13.99)

rms line current

1.5

The line current is given by

IL =

Equation (13.100)

1

Semicontrolled

Equation (13.97)

0.75

I rms V R

0.5 Equation (13.98)

0.25

controlled

0 0

30

60

90

120

150

180

delay angle (a)

Vab

Vab

Vbc

V 1 −

4 3π

α+

2 3π

sin 2α 

½

(13.96)

⅓π ≤ α ≤ ⅔π

The line current is given by 3 8 IL = V 9 −  R

1

.

=

Mode [1/0]

3

.

3

R

π

α+

V  89 − π1 α + 

3

6π

(1 +

.

)

3 sin 2α + cos 2α  

1 + 2 sin ( 2α + π ) )  6π (  3

1 6

½

(13.97)

½

⅔π ≤ α ≤ π

The line current is given by 3

V  23 − 32π α + 31π sin 2α  R The thyristors must be retriggered to ensure the current picks up after α.

Vca

2π 3π

π

Mode [2/1]

.

R

IL =

(b)

Vbc

578

0 ≤ α ≤ ⅓π

Equation (13.96)

1.25

Vca


ωt

.

(13.98)

Half-controlled When the delta thyristor arrangement in figure 13.23 is half controlled (T2, T4, T6 replaced by diodes) there are two mode of thyristor operation, with a resistive load. Mode [3/2] 0 ≤ α ≤ ⅔π The line current is given by ½ 3 IL = V 1 − 32π α + 31π sin 2α  (13.99) R .

α = ⅔π ig T1

T1 on

T1 on T2 on

ig T2

ig T6

ωt

T4 on

ig T4

ωt ωt

T3 on

ig T3

T5 on

T2 on

T5 on

ig T5

T6 on

T6 on

.

1 2π

α − 123π (1 − 2 sin ( 2α − 16 π ) ) 

½

(13.100)



ωt

13.4.4 Half-controlled three-phase ac regulator

ωt

The half-controlled three-phase regulator shown in figure 13.24a requires only a single trigger pulse per thyristor and the return path is via a diode. Compared with the fully controlled regulator, the halfcontrolled regulator is simpler and does not give rise to dc components but does produce more line harmonics. Figure 13.24b shows resistive symmetrical load, line-to-neutral voltage waveforms for four different phase delay angles, α.

ωt iab ωt ibc ωt ica ωt

Resistive load

Three distinctive conduction periods exist. i. 0 ≤ α ≤ ½π – [mode3/2]

ia ωt ib ωt ic

Mode [2/1] ⅔π ≤ α ≤ π The line current is given by 3 8 IL = V 9−  R

π

V rms = I rms R = V 1 −

3π

o

2π

Before turn-on, one diode and one thyristor conduct in the other two phases. After turn-on two thyristors and one diode conduct, and the three-phase ac supply is impressed across the load. The output phase voltage is asymmetrical about zero volts, but with an average voltage of zero. Examination of the α = ¼π waveform in figure 13.24b shows the voltage waveform is made from three segments. The rms load voltage per phase (line to neutral) is

ωt

(c) Figure 13.23. An in-delta connected three-phase ac regulator: (a) circuit configuration; (b) normalised line rms current for controlled and semi-controlled resistive loads; and (c) waveforms for an in-circuit resistive load with a 120° delay angle.

3 4π

α+

3 sin 2α  8π 

½

0 ≤ α ≤ ½π

(13.101)

The Fourier co-efficients for the fundamental voltage, for a resistive load are 3 3 a1 = V ( cos 2α − 1) b1 = V ( 83π − 2α + sin α ) (13.102) 8π 8π Using three integration terms, the average half-wave (half-cycle) load voltage, for both halves, specifies the average thyristor and diode current requirement with a resistive load. That is ½cycle 2V Vo = 2 × I T R = 2 × I Diode R = (13.103) 0 < α < 13 π ( 3 + cos α ) 2π

Power Electronics

579

Chapter 13


580

The resistive load fundamental is 2 3 3 3 a1 = − V b1 = V ( 116 π − 2α ) → V1 = V (13.106) 1 + ( 116 π − 2α ) = I 1R 4π 4π 4π Using two integration terms, the average half-wave (half-cycle) load voltage, for both halves, specifies the average thyristor and diode current requirement with a resistive load. That is ½cycle 2V Vo = 2 × I T R = 2 × I Diode R = (13.107) 1 + 3 + 2 cos α 2π .

)

(

(

)

iii. ⅔π ≤ α ≤ 7π/6 – [mode2/0] Current flows in only one thyristor and one diode and at 7π/6 zero power is delivered to the load. The output is symmetrical about zero. The output voltage waveform shown for α=¾π in figure 13.24b has one component. ½

3 3 π 7 3 3  Vrms = I rms R = V  78 − 43π α + 163π sin 2α − 16 π cos 2α  = V   8 − 4π α + 8π sin ( 2α − 3 )  2

3

½

π ≤ α ≤ 76π

(13.108)

with a fundamental given by 3 3 7 a1 = - V cos 2 (α − 23 π ) b1 = V π − α − ½ sin 2 (α − 23π )  (13.109) 4π 4π  6 Using one integration term, the average half-wave (half-cycle) load voltage, for both halves, specifies the average thyristor and diode current requirement with a resistive load. That is ½cycle 2V Vo = 2 × I T R = 2 × I Diode R = (13.110) 3 1 + cos α − π 6 2π

(

1

rms and average phase voltage ∧

∧

2V

πR

.

After α = ⅓π, only one thyristor conducts at one instant and the return current is a diode. Examination of the α = π and α = π waveforms in figure 13.24b show the voltage waveform is made from three segments, although different segments of the supply around ωt=π. Using three integration terms, the average half-wave (half-cycle) load voltage, for both halves, specifies the average thyristor and diode current requirement with a resistive load. That is ½cycle 2V Vo = 2 × I T R = 2 × I Diode R = α > 13 π (13.104) 1 + 2 cos α + 3 sin α 2π

(

)

ii. ½π ≤ α ≤ ⅔π – [mode3/2/0] Only one thyristor conducts at one instant and the return current is shared at different intervals by one (⅓π ≤ α ≤ ½π) or two (½π ≤ α ≤ ⅔π) diodes. Examination of the α = π and α = π waveforms in figure 13.24b show the voltage waveform comprises two segments, although different segments of the supply around ωt = π. The rms load voltage per phase (line to neutral) is 3  Vrms = I rms R = V { 11 8 − 2π α }

½

½π ≤ α ≤ 2 3 π

(13.105)

V rms V

Equation (13.100)

0.5

Equation (13.100)

Equation (13.100)

0.25

½ cycle

Vo V

½ average voltage

Equation (13.100)

rms voltage Equation (13.111)

0.75

V rms V

0.5 Equation (13.112)

Equation (13.113)

V1 V

0.25

fundamental voltage Equation (13.114)

0

0 0

The diode and thyristor maximum average current is when α = 0, that is I T = I Diode =

Equation (13.100)

Equation (13.100)

0.75

rms voltage

rms and fundamental phase voltage

1 Equation (13.100)

Figure 13.24. Three-phase half-wave ac voltage regulator: (a) circuit connection with a star load and (b) phase a, line-to-load neutral voltage waveforms for four firing delay angles.

))

(

60

120

180

90 (a)

delay angle α

(b)

120

150

180

210

delay angle α

Figure 13.25. Three-phase half-wave ac voltage regulator characteristics: (a) rms phase and average half cycle voltages for a resistive load and (b) rms and fundamental voltages for an inductive load.

Purely inductive load

Two distinctive conduction periods exist. i. ½π ≤ α ≤ π – [mode3/2] For a purely inductive load (cycle starts at α =½π)

V rms = I rms ωL = V

7 4

−

3 2π

α+

3 4π

sin 2α

½π ≤ α ≤ 56 π

while for a purely inductive load the fundamental voltage is (a1 = 0) 3 b1 = V1 = V ( 73π − 2α + sin 2α ) = I 1ωL 4π

(13.111) (13.112)

Power Electronics

581

ii. π ≤ α ≤

Chapter 13

For a purely inductive load, no mode 3/2/0 exist and rms load voltage for mode2/0 is

V rms = I rms ωL = V

.

(

7 4

−

3 2π

α+

3 4π

sin ( 2α − 2π 3

π

3

))

) = I ωL 1

582

Three output voltage modes can be shown to occur, depending of the delay control angle. Mode [2/1] -⅓π ≤ α ≤ π Mode [2/1/0] π ≤ α ≤ ⅓π Mode [1/0] ⅓π ≤ α ≤ π The control angle reference has been moved to the phase voltage crossover, the first instant the device becomes forward biased, hence able to conduct. This is ⅓π earlier than conventional three-phase fully controlled type circuits.

7 π – [mode2/0] 6

with a fundamental given by (a1 = 0) 3  7π b1 = V1 = V − 2α − sin 2 (α − 4π  3


(13.113)

(13.114)

Another simplification, at the expense of harmonics, is to connect one phase of the load in figure 13.18a directly to the supply, thereby eliminating a pair of line thyristors.

When α >π, the load current is dominated by harmonic currents. Normalised semi-controlled inductive and resistive load characteristics are shown in figure 13.25.

ia

-ib

13.4.5 Other thyristor three-phase ac regulators

-ic

ib

-ia

ic

-ib

i. Delta connected fully controlled regulator For star-connected loads where access exists to a neutral that can be opened, the regulator in figure 13.26a can be used. This circuit produces identical load waveforms to those for the regulator in figure 13.18 regardless of the type of load, except that mean device current ratings are halved (but the line currents are the same). Only one thyristor needs to be conducting for load current, compared with the circuit of figure 13.18 where two devices must be triggered. The triggering control is simplified but the maximum thyristor blocking voltage is increased by 2/√3, from 3V/√2 to √6V. ωt

Three output voltage modes can be shown to occur, depending of the delay control angle. Mode [2/1] 0 ≤ α ≤ ⅓π Mode [1] ⅓π ≤ α ≤ ½π Mode [1/0] ½π ≤ α ≤ π

ia

2 VL −L

3 2π

R

=

3 2π

3 2V

R

T2

T4

ib

T2

ib

T2 T6

T6

T6

ic

-ic

ic

(13.115)

-ia T4

-ib

In figure 13.26a, at α = 0, each thyristor conducts for π, which for a resistive line load, results in a maximum thyristor average current rating of

IT =

ia T4

ia

A half-controlled version is not viable.

-ia

-ia

T4

T4 -ib

T2

T4

ib

T2

T6

-ib

T2 T6

T6

-ic

-ic

ic

Figure 13.27. Open-star three-phase ac regulators with three thyristors (figure 13.26b): (a) thyristors currents and (b) six line current possibilities during consecutive 60° segments.

Table 13.1: Thyristor electrical ratings for four ac controllers Thyristor Circuit figure

13.18 Figure 13.26. Open-star three-phase ac regulators: (a) with six thyristors and (b) with three thyristors.

13.20

ii. Three-thyristor delta connected regulator The number of devices and control requirements for the regulator of figure 13.26a can be simplified by employing the regulator in figure 13.26b. In figure 13.26b, because of the half-wave configuration, at α = -⅓π, each thyristor conducts for ⅔π, which for a resistive line load, results in a maximum thyristor average current rating of

IT =

3

2 VL −L

2π

3R

=

3 2V 2π R

V

V

13.24 13.26a 13.26b

V V

Voltage ×

.

2V

3I ac2 R

3

3Z

3I ac2 R

2

3V

13.23

Max load power

3Z

3V

13.22

(13.116)

Two thyristors conduct at any time as shown by the six sequential conduction possibilities that complete one mains ac cycle in figure 13.27.

Max input line rms current, Iac

Z

I ac R

Z

I ac2 R

2

3Z

3I ac2 R

3Z

3I ac R

2

3

1.225

rms current / Iac

1 .

1 .

1 .

.

2

3

2

.

.

2

2

.

2

.

2

.

½ 23 1 .

Peak current / Iac

2

2

½ 23

2

0.766

2

2

2

2

2

2

0.816

.

Control delay angle range Mean current / Iac

2

2

2

0.816

π

2

π

π π π /√3

π /√3

Resistive load

0≤α ≤

5

6

Inductive load

½π ≤ α ≤ 5 6 π

π

0≤α ≤π 0≤α ≤π ½π ≤ α ≤ π

0≤α ≤π 0≤α ≤

7

0≤α ≤

5

6

π

6

π

− 13 π ≤ α ≤

5

6

π

½π ≤ α ≤

7

½π ≤ α ≤

7

6

π

6

π

Power Electronics

583

Example 13.6:

Chapter 13

Star-load three-phase ac regulator – untapped neutral

A 230V (line to neutral) 50Hz three-phase mains ac thyristor chopper has a symmetrical star load composed of 10Ω resistances. If the thyristor triggering delay angle is α = 90º determine i. The rms load current and voltage, and maximum rms load current for any phase delay angle ii. The power dissipated in the load iii. The thyristor average and rms current ratings and voltage ratings iv. Power dissipated in the thyristors when modelled by vT = vo + ro×iT =1.2 + 0.01×iT Repeat the calculations if each phase load is a 20mH. Solution (a)

10Ω Resistive load - α = 90º

i.

rms voltage from equation (13.69)

V rms = I rms R = V ½ + 

ii.

iii.

cos ( 2α + π 6 )  

½

= 230V ½ + 34π3 cos ( 2 × 90° + 30° )    Whence the rms current V 86.6V = 8.66A I rms = rms = 10Ω R The load power is 2 P10 Ω = I rms R = 8.662 × 10Ω = 750.7W

½

= 230V × 0.377=86.6V

Thyristor average current from equation (13.72) 3 2V IT = ( sin α − ½ ) 2π R

(

)

= 1.2 × 4.48A + 0.01 × 6.122 = 5.75W

(b)

20mH Inductive load - α = 90º

i.

rms voltage and current from equation (13.78)

I rms =

V ωL

½

( 52 − π3 α + ( 7 − π6 α ) cos

230V = 2π 50Hz × 0.02H

Thyristor loss PT = v o I T + ro iT2 rms = 1.2 × I T + 0.01 × iT2 rms = 1.2 × 25.88A + 0.01 × 36.62 = 44.45W

♣ 13.4.6 Solid-state soft starters

An electric motor soft starter is a device used to temporarily reduce the load and torque in the powertrain of any electric motor during start-up. This reduces the mechanical stress on the motor and shaft, as well as the electrodynamic stresses on the interconnecting power cables and electrical distribution network, thereby extending system lifetime. Motor soft starters can consist of mechanical or electrical devices, or a combination of both. Mechanical soft starters include clutches and several types of couplings using a fluid or magnetic forces. Electrical soft starters can be any control system that reduces the torque by temporarily reducing the voltage or current input, or a device that temporarily alters how the motor is connected in the electric supply circuit. In the case of the three-phase induction motor, electrical soft starters can utilize solid-state devices to control the current flow and therefore the voltage applied to the motor. The starter can be connected in series with the line voltage applied to the motor, or can be connected inside the delta loop of a deltaconnected motor, thus is able to control the voltage applied to each winding. Solid-state soft starters can control one or more phases of the voltage applied to the induction motor with the best results achieved by three-phase control. Typically, the voltage is controlled by inverse-parallel-connected siliconcontrolled rectifiers (SCR), but in some circumstances with three-phase control, the control elements can be a inverse-parallel-connected SCR and diode combination. A solid-state soft starter is basically a three-phase ac to ac fully controlled regulating converter as shown in figure 13.18, used to soft-start three-phase ac caged induction motors. A soft-starter is functionally two/three ac instantaneous controlled solid-state relays, as in section 13.1.3, with the two/three isolated dc control inputs connected together.

P

( 52 − π3 α + 23π sin 2α ) ½ = 230V ( 52 − π3 ½π ) = 230V

V rms = V

584

13.4.6i The induction motor The induction motor is the simplest and most rugged of all electric motors. They consist of two basic electrical assemblies: the wound stator and the rotor assembly. Three-phase voltage supplies the stator windings which produce a three-phase rotating magnetic field. The electrically isolated rotor consists of laminated, cylindrical iron cores with slots for receiving the conductors. On early motors, the conductors were copper bars with ends welded to copper rings known as end rings. Viewed from the end, the rotor assembly resembles a squirrel cage, hence the name squirrel-cage motor is used to refer to induction motors. In modern induction motors, the most common type of rotor has cast-aluminium conductors and short-circuiting end rings. The rotor turns when the stator rotating magnetic field induces a current in the rotor shorted conductors. This rotor current produces a rotor magnetic field which interacts with the stator field, producing a rotating torque. The speed at which the stator magnetic field rotates is the synchronous speed of the motor and is determined by the number of poles in the stator and the frequency of the ac power supply voltage. 60 × f (13.117) ns =

3 2 230V sin π − ½ = 4.48A 2 2π 10Ω Thyristor rms current I 8.66A = 6.12A I T rms = rms = 2 2 Thyristor loss PT = v o I T + ro iT2 rms = 1.2 × I T + 0.01 × iT2 rms =

iv.

3 3 4π

iv.


where ns = synchronous speed, rpm f = frequency, Hz P = number of pole pairs 2

( 52 − π3 ½π )

α+

½

9 2π

sin 2α

)

½

230V = = 36.6A 2π 50Hz × 0.02H

ii.

The load power is zero.

iii.

Since the delay angle is 90º, the natural power factor angle, continuous sinusoidal current flows and the thyristor average current is 1 2 2 1 2 2 IT = I rms = 36.6A = 23.3A 2 π 2 π Thyristor rms current I 36.6A = 25.88A I T rms = rms = 2 2

Synchronous speed is the absolute upper limit of motor speed. At synchronous speed, there is no difference between rotor speed and the rotating field speed, so no voltage is induced in the rotor bars, hence no torque is developed. Therefore, when running, the rotor must rotate slower than the magnetic field. The rotor speed is just slow enough to cause the proper amount of rotor current to flow, so that the resulting torque is sufficient to overcome windage and friction losses, and drive the load. This speed difference between the rotor and stator magnetic field, called slip, is normally referred to as a percentage of synchronous speed: n − nR s = s (13.118)

ns

where s = slip nR = actual rotor speed, rpm In order to appreciate the attributes of using an electronic motor controller, it is necessary to have an understanding of the characteristics and limitations of the three-phase ac caged induction (asynchronous) motor and the traditional electromechanical systems used to control it.

Power Electronics

Chapter 13

The standard, fixed-speed induction motor fulfils two basic mechanical requirements: • accelerates itself and its mechanically connected rotational load to full speed and • maintains the load at full speed efficiently and effectively over the full range of loadings.

% full-load torque and current

Design A Design D

300

Design C

% of rate torque

Due to the constraints of machine materials and design, it is difficult to achieve both mechanical objectives effectively and economically in one machine. Electromechanical motors convert electrical energy drawn from the ac power supply into a mechanical rotating form, usually as a shaft rotating at a speed related to the number of machine pole pairs, P, and the frequency of the ac supply, f. The mechanical power Pm (W) available from the shaft is equal to the mechanical torque Tm (N) multiplied by the shaft speed, nR (rad/s), Pm = Tm × nR. From an initial value at standstill, the torque varies as the machine accelerates, reaching a peak at about 80% full speed, finally reducing to zero at synchronous speed, ns = 60f/P (rpm). This characteristic means that induction motors always operates at slightly less than synchronous speed, the ‘slip speed’, nslip = s × ns (rpm), in order to develop power, hence the term asynchronous machine. The characteristics in figure 13.28a show an induction motor torque-speed curve, which illustrates the most important mechanical output characteristics.


200

100

Design B

0 0

speed speed

ns 100

load 0 1

speed slip (a)

ns 0

rpm rad/s pu

full-load torque FLT MN

accelerating torque

synchronous speed

load 0 1

speed slip

ns 0

rpm rad/s pu

(b)

Figure 13.28. Torque-speed curve for the induction motor showing: (a) the coupled load torque requirement and (b) the available accelerating torque.

Any load mechanically coupled to an induction motor has its own particular speed-torque characteristic requirement curve. The acceleration of a motor-load system is due to the difference between the motor developed torque and the load absorbed torque, as shown by the shaded area in figure 13.28b. The larger the torque difference, the higher the acceleration and the quicker full speed is reached, whence the greater the electrical and mechanical stresses experienced by the ac supply and drive system during the acceleration period. An ‘ideal’ starter accelerates the load with minimal intervention to reach full speed smoothly in a reasonable time, with minimum stress to the supply and drive train. The motor speed-torque characteristic can be controlled by the rotor cage resistance, where a motor with high rotor resistance can generate its peak torque (pull-out torque) at standstill giving a high breakaway torque characteristic, which progressively reduces, as the speed increases, to zero at synchronous speed, NEMA design D in figure 13.29a. A motor with a low rotor resistance will produce a low starting torque but will generate its peak torque closer to the synchronous speed, NEMA designs A and B. Consequently, this type of motor runs at full power with a higher operating efficiency and low slip speed. Induction motors that combine the dual requirements of high starting torque and efficient fullspeed operation within a single motor have a double-cage or deep bar design, and this motor characteristic, shown in Figure 13.29a, NEMA design C, is ideal for use with soft starter control. All motors, except class D types, operate at 5% slip or less at full (rated) load. Notice that all the design classes produce a starting torque and pull-up torque that are greater than the full-load torque level. Full load torque can be developed at any speed, but at the expense high current, low power factor, and low efficiency, hence increased motor heating. The important difference between the classes is the torque per ampere hence efficiency in the normal operating range, viz., at and above rated speed. A induction motor with two poles often has a lower starting torque than motors with four or more poles, thus oversized motors may be used to ensure that their mechanical load can be started and driven under all operating conditions.

current

break down torque 300

torque

200

full load torque and current

pull-up torque

100

locked rotor torque 0 1

speed slip

efficiency

100

η

80

torque

80

M

M pf η

pf η

% %

ns rpm rad/s 0 pu

(b)

60

power factor

60

pf torque power factor efficiency

full-load torque starting torque FLT MN locked rotor torque no-load speed LRT MA synchronous speed

locked rotor currrent

400

(a)

power factor efficiency

starting torque locked rotor torque LRT MA

Increasing rotor resistance

Torque, M, Nm

Torque, M, Nm

pull-in torque pull up torque

breakdown torque pull-out torque BDT MK

500

rpm rad/s pu %

100 breakdown torque pull-out torque BDT MK

586

0

%BDT pu %

585

40 20 0

power factor

40

pf FLT

20

efficiency

η

0 0

20

40

60

% full-load torque as s → 0

(c)

80

100

0

0.2

1

0.8

0.4 speed 0.6 slip

0.6 Ns = 1 pu 0.4 s pu

0.8

nrated 1

0.2

0

(d)

Figure 13.29. Induction motor characteristics: (a) torque-speed curves for various NEMA classes of three-phase ac caged induction motors; (b) speed versus torque and current characteristics; (c) power factor and efficiency versus full-load torque; and (d) torque and efficiency versus rotor speed/slip.

Power factor Induction motors present a lagging (inductive) power factor to the ac power line. The power factor in large fully loaded high-speed motors can be better than 0.90. At ¾ full-load, for large high-speed motors the power factor can be 92%. The power factor for small low-speed motors can be as low as 0.5. At starting, the power factor can be in the range of 0.1 to 0.25, improving (increasing) as the rotor gains speed.

Power factor (pf) varies considerably with the motor mechanical load as seen in figure 13.29c. An unloaded motor is analogous to a transformer without a secondary load. Little resistance is reflected from the secondary (rotor) to the primary (stator). Thus the ac line sees a reactive load, dominated by the magnetising current, resulting in a pf as low as 0.1 lagging. As the rotor is loaded, an increasing resistive component (representing the developed output power) is reflected from rotor to stator, increasing the power factor. Efficiency Large three-phase motors are more efficient than small three-phase motors. Large induction motor efficiency can be as high as 95% at full load, though better than 90% is common. Efficiency for a lightly load or no-load induction motor is poor because most of the current is involved with maintaining the magnetizing flux. As the torque load is increased, more current is consumed in generating torque, while current associated with magnetizing remains fixed. Efficiency at 75% FLT can be slightly higher than that at FLT. Efficiency is decreased a few percent at 50% FLT, and decreases more at 25% FLT. Efficiency only becomes poor below 25% FLT. The variation of efficiency with loading and speed is shown in Figure 13.29, parts c and d.

Power Electronics

587

Chapter 13

13.4.6ii Background to induction machine starting Traditionally there are several ways to start three-phase ac induction motors. Starting via the use of series resistors and chokes/reactors or shunt capacitors are not considered. Direct-on-line starting DoL The simplest starting approach is to connect the motor to the ac voltage power supply via contactors and overload relays, and start the motor at full line voltage. This method is called direct-on-line (DoL) motor starting. The motor high in-rush current (locked rotor current) can be 5 to 10 times the motor full load current, as seen in figure 13.29b. These high starting currents cause voltage dips and sag in a weak power supply system. DoL starting also causes excessive torques in the mechanical system being driven, causing undesirable shocks among mechanical components, such as gears, belts, sheaves, and connections. Systems exposed to such shock will require frequent inspection and maintenance that lead to costly down-time. Other viable approaches for electromechanical reduced-voltage starting use either a three-phase stepdown auto-transformer or wye-delta starters. Autotransformer starting An auto-transformer is a non-isolating transformer that can be tapped to deliver any percentage (including >100%) of full voltage, for example 58%. By starting the motor at reduced voltage, electromechanical starters are able to crudely reduce the in-rush current and developed torque. Although the voltage is increased in limited steps, there are sudden current changes and mechanical shock during transitions. Motor-start rated circuit breakers (slow opening operation to current surges) replace standard circuit breakers for starting motors of a few kilowatts. This interlocked breaker accepts high over-current for the duration of starting. In figure 13.30a, closure of the start contacts S applies reduced voltage during the start interval. The S contacts open and the run contacts R close after starting. This reduces the starting current to, say, 200% of full-load current. Since the autotransformer is only used for the short start interval, it may be sized considerably smaller than for a continuous duty application. By controlling two phases, which defines the third phase, the three autotransformer version can be reduced to two autotransformers, as shown in figure 13.30b, if phase current imbalances can be tolerated for the short transient start-up period. The basic auto-transformer starter has the disadvantage that at the contactor transition instant from 'start' to 'run' the supply to the motor is interrupted, termed an open transition start. This means that the electrical system insulation is stressed by the resultant high transient voltages. A closed transition start method keeps the motor connected to the supply continuously by means of the connection shown in figures 13.30, parts c and d for two and three controlled phases respectively. The three start-up sequence of stages, for one phase of the three machine phases, are shown in part e of figure 13.30, which can be described as follows: • First Stage-1, switches L and S close and the motor accelerates at a reduced voltage determined by the autotransformer tapping. • Then the second Stage-2, the star point of the transformer (switch S) is opened so that the motor continues to run with part of the transformer winding in circuit. • Next, Stage-3, this winding section is short-circuited by the 'run' contactor or switch (switch R closes).

R

Φ1

2

 applied voltage   × standstill current with full volts  full voltage  The factor of 1.1 compensates for the auto-transformer magnetizing current. The initial starting torque is approximately

(13.119)

588

L

Φ1

3Φ motor

R 3Φ motor

T1

T1

S S

S R

Φ2

R

L

Φ2

T2

T2

S S

S - start

S

R - run

R

Φ3

S - start

L

Φ3

T3

S S

S

(a)

(c)

(b)

(d)

open-transition

closed-transition

R

Φ1

R – run L line

R

T3

R

L

Φ1

3Φ motor

3Φ motor

T1

T1 S S

S R

Φ2

R

L

Φ2

T2

T2 S S - start

S

R - run

S - start

S

L line

L line

L line

line current

line current

line current

R run

R – run L line

L

Φ3

Φ3

The initial starting line current is approximately

Starting Current = 1.1 × 


R run

R run

2

 applied voltage   × standstill torque with full volts  full voltage 

Starting starting = 

(13.120)

These formulae for initial starting current and torque are approximate because it is assumed for simplicity that the standstill-reactance of a motor is constant at all voltages, that is, the short-circuit current varies in direct proportion to the applied voltage. Owing to magnetic saturation, particularly of the machine slot tips, the standstill reactance tends to be less on full volts than on reduced volts so the current and torque values tend to be less than those given by the formulae. A fully automatic three-phase starter comprises a triple-pole line contactor, start contactor, running contactor, three single-pole overload relays, auto-transformer with a set of links for tap-changing, a suitable timer, and 'start' and 'stop' pushbuttons. The two auto-transformer version shown in figure 13.30d, reduces the number of poles needed on the start ,S, and run, R, contactors, from three poles to two poles.

S start

3Φ motor

star

S start

3Φ motor

Stage #1

star Stage #2

S start

3Φ motor

star Stage #3

(e) Figure 13.30. Basic auto-transformer induction motor starter, with two and three-phase independent control: (a) and (b) open transition switching sequence, (c) and (d) closed transition switching sequence, and (e) three stages of the closed transition switching sequence.

Power Electronics

589

Chapter 13

Star-delta or wye-delta starter From equations (13.119) and (13.120), reduced voltage starting utilises the fact that motor torque and current are proportional to the square of the terminal voltage. This is exploited in the most familiar type of reduced-voltage starter, namely the star-delta or wye-delta starter, shown in figure 13.31. The stardelta starter consists of three contactors and a time switch (which can be mechanical, pneumatic, electrical or electronic). With the wye-delta starter, the special winding terminated motor (access to three individual windings) is first run as a wye motor so each motor winding only experiences 58% of full voltage, 1/√3. After a set period-of-time, the starter switches to run the motor as a delta connected motor and the motor windings experience the full ac line voltage. The change-over is controlled by the timer switch and is usually arranged to switch at 80% of full speed. The effect of starting in star, with each stator winding voltage reduced to 58%, 1/√3, of normal, is a reduction in the starting torque to a third of locked rotor torque (LRT) with a consequential reduction in starting current and acceleration force. Effectively, the voltage is reduced by a 1.732 factor,√3. The impedance seen by the power system is 3 times the impedance of the delta run connection. The starting sequence and resultant torque/current characteristics are shown in figure 13.36. For Wye Start, Delta Run, the starting characteristics are: • starting current is approximately 30% of that obtained with the normal delta connection. • starting torque is approximately 25-30% of that realised with the normal delta connection.


13.4.6iii Solid-state soft-starter The solid-state switches, in figure 13.18 for example, are phase controlled in a similar manner to a light dimmer, in that they are turned on for a part of each ac cycle. The rms voltage is controlled by varying the conduction angle of the switches. Decreasing the delay angle, α (increasing the conduction angle), as shown in figure 13.32, increases the rms output voltage. Controlling the rms output voltage by means of solid-state switches has a number of advantages, one being the improvement in system efficiency, due to the low on-state voltage of SCR solid-state switches. Another advantage of the solid-state starter is that the rms voltage can be easily altered to suit the required starting conditions. By varying the conduction angle, the output voltage can be increased or reduced, and this can be achieved automatically by the control electronics. The control electronics can be pre-programmed to provide a particular output voltage contour based on a timed sequence (open loop), or can dynamically control the output voltage to achieve an output profile based on measurements of characteristics such as current and speed (closed loop).V L-

L

output voltage

This starting method is only viable when the system is light loaded during the start. Although an improvement over the DoL system, disadvantages remain.

α4

α2 α1

L1

L2

α3

α6 = 0

ωt

α5 = 0

L3 U1

W1 L1 LINE

F1

F2

F3

U1

V1

W1

L2

L3

WYE

Initial WYE start-up winding

α1 > α2 > α3 > α4 > α5 = 0

U2

W2

V2

Figure 13.32. Smoothly ramped-up motor voltage by controlling the SCR’s firing angle, α.

DELTA

Switching elements Voltage control is achieved by means of solid-state ac switches in series with one or more phases. The ac switch possibilities comprise any of the combinations in figure 13.33.

V1

W2

3Φ motor U2

590

U1

DELTA run configuration

V2

W2

W1

U2 V2

V1 (a)

Figure 13.31. Basic wye-start, delta-run connection configuration for induction motor starting.

The transfer from a star to a delta connection momentarily disconnects the motor from the supply. During this time it is under the mechanical influence of the rotating load and, at the instant of disconnection, current continues to flow in the rotor bars due to the long time delay necessary for the magnetic flux to die away. Therefore, there is a residual flux ‘frozen’ on the surface of the rotating rotor, which cuts the stator windings, generating a voltage whose frequency depends on rotor speed. If the load inertia is small, such as in a pump, or if the friction is high, there could be a significant loss of speed during the time the supply is disconnected. In this case, when the delta run connection is made, a large phase differential can exist between the supply and the rotor fluxes. This can give rise to large current surges, possibly more than the full-voltage locked rotor current, together with large transient torque oscillations, as much as five times full-load torque. Although the effects are only transitory, typically one fifth of a second, they are sources of stress and potential damage to the drive system, and where frequent starting is necessary, incur high maintenance costs. There are methods of control, for example, the closed transition starter, which eliminate or reduce the reconnection transients. However, such starters are expensive and have reliability implications; for these reasons, they are not widely utilised. The star-delta starter also has disadvantages due to the restricted starting torque available. If 40% LRT is needed to breakaway, the motor size must be increased or direct-on-line starting is re-employed. Combined with the severe effects of the re-switching surges and the additional costs of bringing six cables from the motor to the starter instead of only three, star-delta starting offers a less than ideal solution to the problem of induction motor starting. As a starting alternative, auto-transformers and wye-delta starters are large and require extra wiring. Solid-state starting technology can overcome many of the problems associated with mechanical based starters and can provide stepless soft-starting of three-phase ac caged induction motors.

(b)

(c)

Figure 13.33. Possible ac switch combinations per phase: (a) a triac; (b) SCR and diode reverse parallel; and (c) reverse parallel connected SCRs.

The switching elements must be able to control the current applied to the motor at line voltage. In order to maintain high reliability, the switching elements need to be rated at least three times the line voltage. On a 400V ac supply, this means that the requirement is for 1200V (dc, bidirectional) devices, and 600V devices on a 200V ac supply. It is also important that the switching elements have a high transient current overload capacity. 1200V triacs with robust current transient overload characteristics are not readily available, so the choice is between the SCR-Diode and SCR-SCR for 400V ac applications. The major differences between the SCR-SCR option in figure 13.33c and the SCR-Diode options in figure 13.33b are cost and the harmonic content of the output voltage. The SCR-SCR approach provides a symmetrical output which is technically desirable from the point of supply disturbances and harmonics, while the SCR-Diode combination is inferior technically, it is commercially more effective and easier to implement. Harmonic regulation requirements have drastically reduced the viability of SCR-Diode type soft starters. The solid-state soft-starter can be designed to control • one phase, reducing the torque but not the current in two phases, (SCR/Diode cannot be used in this connection), Fig. 13.34a, or • two phases reducing the torque but the current will not be optimally reduced or balanced, there will be negative sequence currents heating the rotor and reducing the torque per unit start current, (SCR/Diode cannot be used in this connection), Fig. 13.34b, or • three phases, reducing current and torque, providing the optimum results for torque generated per unit of start current, Fig. 13.34c. The SCR/diode combination can be used.

Power Electronics

Chapter 13

L1

T1

L1

T1

L1

T1

L2

T2

L2

T2

L2

T2

L3

T3

L3

T3

L3

T3

(b)

(c)

Figure 13.34. Three possible line configurations: (a) single phase control; (b) control of two phases; and (c) three-phase fully-controlled regulator.

L1

L2

Solid-state soft-starter arrangements A reduced ac voltage can be delivered to a motor by controlling an SCR’s firing angle, as illustrated in Figure 13.32. This SCR’s firing angle control can ramp the voltage smoothly to full rating with the motorcontroller connection configurations shown in Figure 13.35. Figure 13.36 shows that the in-rush current with electronic soft starters is much lower, as is the starting torque available from the motor, compared with DoL ans star-delta starter. Therefore, both voltage dips and mechanical shock are reduced considerably with solid-state soft starters. In the in-delta circuit configuration in figures 13.35b/c the individual phases of the switching devices are connected in series with the individual motor windings (6 conductor connections as with the star-delta starter). The soft starter conducts about 58 % of the rated motor current. This allows the use of a significantly smaller device than the in-line approach, which only requires three motor connections, as shown in figure 13.35a. By using a by-pass contactor across the semiconductor switches, as shown in figure 13.35a, the softstarter power losses are reduced. Additionally, since the starter is only functional during in short infrequent start/stop periods, it is possible to reduce the starter enclosure size and use a higher IP-class since air ventilation is not required.

L3

main circuit breaker line contactor

Direct on Line Direct on Line

soft starter

L2

F2

F3

L3

L1

L2

L3

acceleration torque

M

F1

Torque

fuses

L1

592

DoL

M

(a)


torque at reduced voltage

1

Star/delta

2

Torque

591

1

3 Soft start

load torque line contactor option

T1

T2

Speed

U1

T3

Ns

Speed

(a)

V1 W1 Direct on Line

DoL

M

I

DELTA

W2

1

voltage ramp

3

V2

load torque

frame earth

L1

F2

F1

Speed

F3

Direct on Line

V

(b)

L3

Star delta

Soft start

100%

1

V1 V2

L1

W1 DELTA

U1

U2

L3

Figure 13.35. Three-phase voltage control of caged three-phase ac induction motor: (a) line delta or star controlled and (b) and (c) control within an in-delta configuration, both with a bypass relay.

3

TVR

2

time

kick-start pedestal voltage t

3

Isoft-start

(e)

Speed

Soft start

5

(f)

2

M∆

1 IY

2

MY 1

3

1

3

(c)

Ns

I∆

6

4

ramp time

58%

Istar/delta-start

1

2

1 pu = Trated

(c)

Motor voltage

W2

Star/delta

2

Irating

(b)

Ns

Direct on Line

1

Torque

(a)

LINE

L2

Idelta-start

Motor current

star or in-line delta motor connection

motor

1 pu = Irated

three-phase motor

U2

W

Current

V

current limited

Torque

U

Ns

(d)

MLoad Speed

Ns

Figure 13.36. Characteristics showing why solid-state soft starters significantly reduce voltage dip and mechanical shock.

593

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594

Bypass contactor

Solid-state soft starters can be connected in series with the line voltage applied to the motor (three-wire or standard connection) as in figure 13.35a, or can be connected inside the delta loop of a delta connected motor, controlling the voltage applied to each winding (six-wire or inside delta connection) as in figure 13.35b/c. There are usually three pairs of SCRs to control the voltage to a three-phase ac induction motor, that is, one pair for each phase, figure 13.35. Because SCRs are power components, they generate approximately 1W/A per phase of heat when on and the heat sink must dissipate the heat generated. Both the SCRs and the heat sink are components that add to the costs. Because a three-phase motor is a three-wire system, the Kirchhoff sum of its three-phase currents is constrained to zero at any instant. If the currents in two of the three phases are reduced, the current to the third phase will be reduced as well, even when the third phase is directly connected to the full line voltage. A two-phase-controlled solid-sate soft starter based on figure 13.34b, is able to control the three-phase currents and since only two pairs of SCRs are used, it has a smaller heat sink. Fewer SCRs and a smaller heat sink reduce the cost and size. Compared to an electromechanical starter, it offers superior performance in a compact size, where the cost of parts, installation, and maintenance are lower. A two-phase-controlled soft-starter can cause undesirable acoustical noise on larger motors at voltages less than 50%. The cause of the audible noise is related to the dc component in the phase current, which causes additional heating. Because of shorter starting times, motor heating is minimal. Polarity balancing control, balances the current in positive half and negative half cycles, eliminating the dc components. Then motors can be started at voltages less than 50% of full rating. This feature is particular applicable when soft starting a fan motor or pump motor at light load or no-load during the start period. Polarity balancing cannot balance the currents among the three phases and the phase without SCR control will have higher current. The imbalance between the three-phase currents is intrinsic to two-phase control and cannot be influenced. Because the imbalance among the three currents is generally within 10 to 25%, it is not critical in applications where the motor load reaches full speed quickly. A three-phase fully-controlled soft-starter is applicable if balanced phase currents are essential to within 10%. The functional block diagram in figure 13.37 shows a three-phase controlled soft-starter which offers features that include: • polarity balancing control allowing the motor to start at less than 50% full voltage • integrated ac motor thermal protection • selectable motor overload trip level • adjustable current limiting, start time, stop time, and starting voltage • built in by-pass contactors • detection of phase failure, faulty control voltage, locked rotor, SCR overheating, etc. Design features particular to power electronics knowhow include the use of isolating pulse transformers for SCR triggering and R-C snubbers across the SCRs. Series snubber resistors are used not so much because of the necessary power rating but to achieve the required 1200V voltage rating. Two series resistors allows low cost, low voltage, low inductance resistors to be used. 13.4.6iv Soft-starter control and application Open-loop control and the start voltage profile Open-loop soft starters produce a start voltage profile which is independent of the current drawn, or the speed of the motor. The start voltage profile is programmed to follow a predetermined contour against time, as shown in figure 13.36c. A basic Timed Voltage Ramp (TVR) system operates by applying an initial voltage to the motor, possibly involving a kick-start pedestal voltage, then slowly ramps from this voltage up to full voltage. On basic systems, the initial start voltage is not adjustable, but the ramp time is and may be a simple linear ramp or a complex shape to emulate a controlled current start. The voltage ramp time is referred to as the acceleration ramp time and is calibrated in seconds. This is not an accurate description, as it does not directly control the acceleration of the motor. Technically, it should be referred to as the voltage ramp time. On more sophisticated controllers, the start voltage is pre-setable, typically from 10% to 70% of full line voltage, and is set to achieve at least breakaway torque for the motor at start. There is no advantage in the motor stalling or straining to start due to insufficient torque. Eventually full voltage is applied under locked rotor load conditions, producing locked rotor torque and current which increases the heat dissipated in the motor, until any protection trips or failure. The starter does not have any programmed knowledge of the connected motor, so is unable to deliver a prescribed amount of torque under open loop conditions. The actual start torque produced is given by equation (13.119). The motor LRT can vary from as low as 60% FLT to as high as 350% FLT which is a range of almost 6 to 1.

i/o RS485

Outputs LCD display LED display relay contactors inputs keypad opto isolators relay coils

Figure 13.37. Functional block diagram of three-phase controlled SCR based soft starter, with voltage and current feedback control, with optional bypass contactor.

Closed-Loop Control Closed-loop soft-starters monitor an output characteristic or effect from the starting action and dynamically modify the start voltage profile to cause the desired response. The most common closed loop soft starter is the controlled current soft starter where the current drawn by the motor during start is monitored and controlled to give either a constant current, as shown in figure 13.36b, or a current ramp soft start. Another closed loop strategy is the constant acceleration soft start where the motor speed is monitored by a tacho-generator or shaft encoder and the voltage is controlled to maintain a constant rate of acceleration or a linear increase in motor speed. Closed-loop control can take the following forms. i. In basic closed loop systems, the soft starter is essentially a standard TVR soft starter with a ramp option where the current in one phase is monitored and compared to a set point. If the current exceeds the set point, the ramp is frozen until the current drops below that set point. At the other complexity extreme, a comprehensive closed loop soft starter monitors the current in two phases (effectively in all three phases) and dynamically changes the output voltage to correct the start current to the required profile. This system is able to both increase and reduce the start voltage to suit the control needs, and attempts to minimise any dc current component.

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ii.

iii.

iv.

A constant current starter commences at zero volts and rapidly increases the output voltage until the required current is delivered to the motor, and then adjusts the output voltage during motor starting until either full voltage is reached, or the motor overload protection operates. With a controlled current soft starter, the voltage reduction reduces as the motor accelerates due to the rising motor impedance. As the motor approaches full speed, the voltage rises quickly (against speed) to full voltage. When the torque curve for a motor started by a constant current starter is compared with that of a constant voltage starter such as an autotransformer starter, there is an increase in the torque as the motor accelerates with a constant current start. This is ideal because as the motor increases in speed, the actual load on the motor shaft increases. This characteristic enables a load to be started with a lower current on a soft starter than traditional starter methods. Constant current starters are ideal for high inertia loads, or loads with a near constant starting torque load requirements. The current ramp soft starter operates in the same manner as the constant current soft starter except that the current is ramped from an initial start current to a current limit setting over a period of time. The initial start current, current limit, and ramp time are all user adjustable to suit the application. Machines requiring a varying starting torque, such as load conveyers, or applications requiring a reduced initial torque such as pumping applications, or genset applications where the relatively slow application of current load will allow the genset to track the load, are examples where the current ramp soft start can be used to advantage over a constant-current soft-starter. In a torque control starter, the controller models the motor under high-slip and low-slip conditions and uses a mathematical model to calculate the current and shaft torque being produced by the motor. These are then used as a feed back source with the square law reduced start torque and current curves, given by equations (13.119) and (13.120), being used to control the start voltage applied to the motor. The torque curve generated by equation (13.119) can be superimposed onto the load speed torque curve, and provided the torque developed at all speeds exceeds the load torque, the motor accelerates to full speed. If the curves cross, the start current (or voltage) are increased to increase the motor starting torque. The difference between the developed and the load torques is the acceleration torque that accelerates the machine to full speed. A high acceleration torque may be desirable for a high inertia load in order to minimize the starting time.

Chapter 13


596

An induction motor with high-inertial load can be quickly stop by circulating dc current in a stator winding, where any two stator terminals can be connected to a dc source such that the resultant dc current produces stationary N-S poles in the stator. Since the number of stationary poles is the same as the number of rotating poles normally produced with ac currents, as the rotor bars sweeps past the dc field, an ac rotor voltage is induced. The I2R loss produced in the rotor circuit is converted kinetic energy stored previously in the rotating masses, hence the motor comes to rest by dissipating all the kinetic energy as heat. The benefit of dc braking is that efficient heat is produced, since the dissipated rotor losses are equal to the kinetic energy of the rotating masses and are independent of the dc current magnitude, while the braking torque is proportional to the square of the dc braking current. DC injection duration and frequency of occurrence should be minimised in order to minimise motor heating. The dc injection braking procedure shown in figure 13.38b, is as follows: • The motor contactor Cmotor is opened, then after a delay of 200ms to 2.5s (increased time as motor rating increases), the braking contactor Cbrake is closed, which allows the motor back emf to reduce. Any overlap between Cmotor and Cbrake is prevented by using interlocked contactors. • After a further 50ms delay, dc current is injected into two motor winding by firing the braking thyristor, until rotation stops. This second 50ms delays allows an ac breaking contactor Cbrake to be used, since dc current switching is avoided. The braking torque is a function of dc current, which is controlled by the thyristor firing angle. • After the thyristor triggering is removed (always before or when to rotor comes to a standstill), a delay of 200ms to 2s (increased time as motor rating increases) is allowed before the braking contactor Cbrake is opened, in order to avoid braking a dc current. • 200ms after the braking contactor Cbrake is opened, the motor can be enabled by closing the motoring contactor, Cmotor. L1

L2

L3

F1

F2

F3

Methods of stopping Soft-stop Soft-starters inherently incorporate soft-stop, which is the opposite to soft-start. The voltage is gradually reduced, reducing the torque capacity of the motor. The reduction of available torque causes the motor to decelerate when the motor shaft torque is less than the torque required by the load. As the torque is reduced, the speed of the load is reduced to the point where the load torque equals the shaft torque. Typically, soft stop is achieved using an open loop voltage ramp, but a torque control soft stop system can use torque feedback to provide better deceleration control. Open loop soft stop performance is dependent on the characteristics of the motor and driven load. On larger machines this can be non-linear, hence provides poor performance. Soft slope effectively adds inertia to the load and extends the braking time. It should only be applied to installations where the stopping time is too short and needs to be extended. Soft stop does not provide braking, and occurs over a period longer than it would take the rotational system to coast to standstill without any power applied. DC braking DC braking is used to apply a braking torque to the motor and load, making them stop quicker. Software controlled dc braking is possible for soft starters, but is not as effective as the braking that can be achieved with a specific dc brake electronic circuit. Software DC braking using the soft starter is achieved by turning on a positive SCR in one phase and a negative SCR on in a second phase for a small angle of each cycle. This causes a high pulse of dc current to flow through the motor windings and creates a stationary torque field in the stator. This causes the motor to slow down. The short pulses at line frequency also produce a synchronous component in the torque field that can limit the effectiveness close to synchronous speed. In some cases, a shorting contactor is connected across a motor winding to prolong the period of current flow and reduce the line frequency component. During dc braking, the energy of the driven load is dissipated in the rotor of the motor. Hardware A stop button, with two interlocked contactors initiates braking, as shown in figure 13.38, where a dedicated thyristor/diode braking circuit is shown.

soft starter

F4

F5 ac supply applied

brake

T1

T2

controller

T3

Cmotor

start

brake

Cmotor

open

Cbrake

closed

start

Cbrake

U

V

W

SCR

dc injection

three-phase motor frame earth

(a)

(b)

0.2s to 2.5s

0.2s to 2s

Figure 13.38. Braking circuit: (a) circuit connection and (b) timing sequence and delay times.

Reversing and plugging A mechanical contactor based reversing arrangement is shown in figure 13.39a, which uses two interlocked contactors. Contactors and fusing for reversing circuits are only used between the line and the soft-stater. It is required, with this contactor arrangement, to insert a 150 to 350ms delay between the opening of one contactor and the closing of the other, to allow any residual flux in the rotor to die away.

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Chapter 13

Figure 13.39c shows the machine torque and current conditions when the machine is reversed whilst operating at or near rated torque/speed, point A. On reversing two phase connections, the operating point A moves to point B, which represents a deceleration torque with a high machine current, point C. The machine accelerates to operating point D as a result of stopping and reversing rotation in a direction opposite to the original rotating direction. In attempting to traverse from point A to point D, the rotation passes through zero speed point E, at which time the controller is phased back to zero thyristor conduction. When plug-braking, (phase reversal at full voltage) there should be some form of zerospeed detection to stop the drive after braking has been completed, otherwise the drive may either accelerate the motor in the reverse direction or switch off before zero speed has been reached. A solid state solution to reversing and plugging is shown in figure 13.38b, which requires two extra sets of back to back parallel connected thyristors.

A

speed

B

L3

F1

F2

F3

Fuses Standard IEC 60947-4-2 defines two types of co-ordination according to the expected level of service continuity. Co-ordination requires that, under short-circuit conditions:

Semiconductor fuse curves do not follow the ratings curves for soft starters and only offer short circuit protection. Semi-conductor fuses (high speed fuses) are the only type of fuses that are fast enough to achieve type 2 co-ordination when using a softstarter. A separate overload relay for motor protection is required in combination with this type of fuse. If replacing the semi-conductor fuses with an MCB, protection reverts to type 1 co-ordination.

(c)

E

L2

Harmonics Harmonics are unwanted voltages and currents existing in almost every electrical system and are a multiple of the rated ac mains frequency. Typical harmonics are odd, viz., 3rd, 5th, 7th, 9th etc., which contribute to the unnecessary heating of motors, cables and other equipment and may shorten the lifetime of these devices if exposed for a long period of time. The resultant EMC may disturb other local electronic systems. Soft-starters generally fulfil EMC directives (EN 60947-4-2) on emission (EN55011 Class A) and immunity (IEC 6 1000-4/ 2 to 6) since their operation is non-continuous and intermittent.

Type 2: The soft-starter device shall cause no danger to persons or installation and shall be suitable for continued use. For hybrid controllers and starters, contact welding is a possibility, in which case equipment maintenance is required.

torque

D

L1

598

Type 1: The soft-starter device shall cause no danger to persons or installation and may not be suitable for further service without repair and replacement of parts.

current C B


soft starter L1

L2

L3

T1

T2

T3

V

W

Cforward Creverse soft starter

U

three-phase motor T1

T2

frame earth

T3

V U

three-phase motor

W frame earth

(a)

(b)

Figure 13.39. Reversing circuit: (a) mechanical contactor reversing; (b) electronic reversing (4 quadrant) with mechanical contactor bypassing; and (c) torque and current characteristic of reversal of two phase voltages.

Ratings As the rating of the soft-starter is essentially thermal, there is a strong relationship between the start time, start current, start/stop frequency of occurrence, ambient temperature, off-time, and the rating of the starter. Typically, the thermal inertia of the SCR heatsink assembly is quite long so there is not a large variation in the rating between say a 10-second rating and a 30-second rating. At altitudes above 1000m the rated current is usually derated at about 7% per 1000m increase in altitude, up to 4000m.

Figure 13.40. Single-phase cycloconverter ac regulator: (a) circuit connection with a purely resistive load; (b) load voltage and supply current with 180° conduction of each thyristor; and (c) waveforms when phase control is used on each thyristor.

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13.5

Chapter 13


600

Cycloconverter

A

C positive group

Figure 13.40b shows how an output frequency of one-fifth of the input supply frequency is generated. The P group conducts for five half-cycles (with T1 and T2 alternately conducting), then the N group conducts for five half-cycles (with T3 and T4 alternately conducting). The result is an output voltage waveform with a fundamental of one-fifth the supply with continuous load and supply current. The harmonics in the load waveform can be reduced and rms voltage controlled by using phase control as shown in figure 13.40c. The phase control delay angle is greater towards the group changeover portions of the output waveform. The supply current is now distorted and contains a subharmonic at the cycloconverter output frequency, which for figure 13.40c is at one-fifth the supply frequency. α

Three–phase ac voltage supply

B

The simplest cycloconverter is a single-phase, two-pulse, ac input to single-phase ac output circuit as shown in figure 13.40a. It synthesises a low-frequency ac output from selected portions of a higherfrequency ac voltage source and consists of two converters connected back-to-back. Thyristors T1 and T2 form the positive converter group P, while T3 and T4 form the negative converter group N.

negative group

intergroup reactor L

L O A D

single-phase ac load

N

V -π/m+α

(a)


π/m+α

A

α

B

√2V

2π/m -π/m

C

+ group -

+ group -

+ group -

IGR

IGR

IGR

π/m

Figure 13.41. Output voltage from an m-phase converter with firing delay angle α.

Φ1

In figure 13.41, if the firing delay angle α, the conduction period is from -π/m + α to +π/m + α, such that the conduction period is 2 π/m. The average output voltage is

Vdc =

m 2π

π +α m π − +α m

∫

2V cos ωt d ωt = 2V

Φ3

m m sin × cos α π π

N

3-phase load Φ2

(b)

For the cycloconverter output

B

v o (t ) = 2Vo sin ωot

A

C


Equating gives cos α =

That is

2V

2Vo sin ωot = ρ sin ωot m m sin π π

α = cos −1 ( ρ sin ωot ) where ρ is the output voltage modulation factor.

group 3

group 1

With inductive loads, one blocking group cannot be turned on until the load current through the other group has fallen to zero, otherwise the supply will be short-circuited. An intergroup reactor, L, as shown in figure 13.40a can be used to limit any inter-group circulating current, and to maintain a continuous load current. A single-phase ac load fed from a three-phase ac supply, and three-phase ac load cycloconverters can also be realised as shown in figures 13.42a and both of 13.42b and c, respectively. A transformer is needed in figure 13.42a, if neutral current is to be avoided. The three-pulse per ac cycle cycloconverter in figure 13.42b uses 18 thyristors, while the 6-pulse cycloconverter in figure 13.42c uses 36 thyristors (inter-group reactors are not shown), where the load (motor) neutral connection is optional. The output frequency, with considerable harmonic content, is limited to about 40% of the input frequency, and motor reversal and regeneration are achievable. If a common neutral is used, no transformer is necessary. Most cycloconverters are 6-pulse, and the neutral connection in figure 13.42c removes the zero sequence component.

Φ1

Φ3

N

group 2

3-phase load Φ2

(c)

Figure 13.42. Cycloconverter ac regulator circuits: (a) three-phase to single-phase; and three–phase supply to three-phase load (b) 3-pulse without neutral connection; and (c) 6-pulse with optional load neutral connection.

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Chapter 13

AC Voltage Regulators input line filter

The positive features of the cycloconverter are • Natural commutation • No intermediate energy storage stage • Inherently reversible current and voltage

VAN

The negative features of the cycloconverter are • High harmonics on the input and output • Requires at least 18 thyristors usually 36 • High reactive power

A

iA

L

C SAa

SAb

SAc

SBa

SBb

SBc

SCa

SCb

SCc

VBN B

iB

L

C C

3Φ ac supply

13.6

602

VCN

The matrix converter

Commutation of the cycloconverter switches is restricted to natural commutation instances dictated by the supply voltages. This usually results in the output frequency being significantly less than the supply frequency if a reasonable low harmonic output is required. In the matrix converter in figure 13.43c, the thyristors in figure 13.42b are replaced with fully controlled, bidirectional switches, like those shown in figures 13.43a and b. Rather than eighteen switches and eighteen diodes, nine switches and thirty-six diodes can be used if a unidirectional voltage and current switch in a full-bridge configuration is used as shown in figure 6.11. These switch configurations allow converter current commutation as and when desired, provide certain conditions are fulfilled. These switches allow any one input supply ac voltage and current to be directed to any one or more of the output lines. At any instant, only one of the three input voltages can be connected to a given output. This flexibility implies a higher quality output voltage can be attained, with enough degrees of freedom to ensure the input currents are sinusoidal and with unity (or adjustable) power factor. If the inputs are voltage sources, the outputs must be current sources, and vice versa. The input L-C filter prevents matrix modulation frequency components from being injected into the input three-phase ac supply system. In the usual case of voltage source inputs and current source outputs, the switch conditions must: • Never short-circuit two or more input phase voltages • Never open circuit any output line current Generally, the relationship between the n output voltages (va, vb, vc, .. vn) and the m input voltages (vA, vB, vC, .. vM) is determined by the states of the M×n bidirectional switches (Si,j), where Si,j = 1 = closed, Si,j = 0 = open, according to v a   S Aa S Ba S Ca S Ma  v A       S Mb  v B  v b  S Ab S Bb S Cb v c  = S Ac S Bc S Cc (13.121) (V) Vout = S V in S Mc  v C            v  S S Mn  v M   n   An S Bn S Cn where S is the switch connection matrix and i = A, B, … M and j = a, b, … n. If the n inputs are voltage sources, then the switches must satisfy M

M

M

M

i =A

i =A

i =A

i =A

∑ S ia = ∑ S ib = ∑ S ic = .....∑ S in = 1

M

n

i =A

j =a

∑ S ia ∑ S ij = n

(13.122)

The first set of equalities in equation (13.122) ensure that each output can only be connected (at most) to one input voltage supply, thus avoiding shorting two or more voltage inputs. Since the inputs are voltage sources, the output must be current sources, thus the second equality ensures a path for current in each of the n output phases. The relationships between the input and output currents, in terms of the switch connection matrix S, are given by T i A   S Aa S Ba S Ca S Ma  i a        S Mb  i b  i B  S Ab S Bb S Cb i C  = S Ac S Bc S Cc (13.123) (A) I in = S T Vout S Mc  i c              i   S S Mn  i n   M   An S Bn S Cn

L

C

SAa

VAN Sij

a

Vao SAc

SAc

SBa

SBa

VBN SBb

VOCc

o

SCa SCc

(a)

3Φ ac load

SBc

SCa VCN

c ic ZL

Vbo SBc

b

ia

Vco

ZL

(b)

ZL

(c)

Figure 13.43. Three-phase input to three-phase output matrix converter circuit: bidirectional switches (a) reverse blocking igbts conventional igbts; (b) switching matrix; and (c) three–phase ac supply to three-phase ac load.

For the three-phase voltage input to three-phase current output matrix converter, the relationship between the output voltages (va, vb, vc) and the input voltages (vA, vB, vC) is determined by the states of the nine bidirectional switches (Si,j), where Si,j = 1 = closed, Si,j = 0 = open, according to v a   S Aa    v b  =  S Ab v   S  c   Ac

S Ba S Bb S Bc

S Ca  v A  S Cb  v B  S Cc  v C 

(V)

Vout = S V in

(13.124)

From Kirchhoff’s voltage law, the number of switches on in each row must be either one or none, otherwise at least one input supply is shorted, that is (i refers to the input and j refers to the output) 3

∑Si j

≤1

for any j

(13.125)

i =1

With the balanced star load shown in figure 13.43c, the load neutral voltage vo is given by vo = 13 ( va + vb + vc )

(13.126)

The line-to-neutral and line-to-line voltages are the same as those applicable to svm (space voltage modulation, Chapter 14.1.3vii), namely  vao     vbo  = v   co 

−1 −1  va    2 −1  vb   −1 −1 2   v    c  2

1 −1 6

(V)

(13.127)

Power Electronics

603

Chapter 13

from which (13.128)

(V)

T

 cos ωot − ϕo + 30°   cos ωi t     v o = v i m  cos ωot − ϕo + 30° − 120°   cos ωi t − 120°   cos ω t − ϕ + 30° + 120°   cos ω t + 120°  i o o     cos ωot − ϕo + 30°    = V i max m  cos ωot − ϕo + 30° − 120°  × 3 2 cos ϕi  cos ω t − ϕ + 30° + 120°  o o  

Similarly the relationship between the input line currents (iA, iB, iC) and the output currents (ia, ib, ic) is determined by the states of the nine bidirectional switches (Si,j), according to

S Ba S Bb S Bc

T

S Ca  S Cb  S Cc 

 ia    ib  i   c

(A)

I in = S T I out

(13.129)

where the switches Sij are constrained such that no two or three switches short between the input lines or cause discontinuous output current. Discontinuous output current must not occur since no natural default current freewheel paths exist. The input short circuit constraint is complied with by ensuring that only one switch in each row of the 3×3 matrix in equation (13.124) (hence row in equation (13.129)) is on at any time, viz., equation (13.125), while continuous load current in equation (13.129) (hence column in equation (13.124)) is ensured by Kirchhoff’s current law, that is 3

∑Si j

≥1

for at least any two i

(13.130)

j =1

More than one switch on in a column implies that an input phase is parallel feeding more than one output phase, which is allowable. If each switch Sij is modulated m(t) (usually sinusoidally in time), the low frequency relationships between the input and output currents and voltages are given by (M is the low frequency transfer matrix) v a   m Aa (t ) mBa (t ) mCa (t )  v A       (13.131) ( V ) or Vout = M (t )v i v b  =  m Ab (t ) mBb (t ) mCb (t )  v B  v   m (t ) m (t ) m (t )  v  Bc Cc  c   Ac  C  T

 i A   m Aa (t ) mBa (t ) mCa (t )   i a         i B  =  m Ab (t ) mBb (t ) mCb (t )   i b   i   m (t ) m (t ) m (t )   i  Bc Cc  C   Ac  c

604

The instantaneous relationship between the input phase voltages and output line voltages is v o = v iT ph −L

 vab   1 −1 −1   v a       v ½ = bc    0 1 0   vb  v   −1 0 1   v   ca    c 

 i A   S Aa     i B  =  S Ab i  S  C   Ac


(A)

or I in = M (t ) i o T

(13.132)

9

Thus given Kirchhoff’s voltage and current law constraints, not all the 512 (2 ) states for nine switches can be used, and only 27 states, in three groups as summarized in Table 13.2, of the switch matrix can be utilised. • The first group, of six combinations, allows each output phase to be connected to a different input phase. • The second group (with 3 subgroups, each with 6 combinations), of 3x6 = 18 combinations, is when two output phases connect to the same input phase (two output phases shorted). • The third group, of three combinations, is when all the output line voltages are zero, shorted. For sinusoidal input phase voltages of frequency ωi and maximum voltage Vimax v A   cos ωi t      (13.133) v i = v B  = V i max  cos ωi t − 120°  v   cos ω t + 120°  i  C   If sinusoidal output line to line voltages are generated at frequency ωo and relative displacement φo, then, neglecting non-fundamental components v ab   cos ωot − ϕo + 30°      (13.134) v o = v bc  = 3 Vo max  cos ωot − ϕo + 30° − 120°  v   cos ω t − ϕ + 30° + 120°  o o  ca   

(13.135)

 cos ωot − ϕo + 30°    = 3 Vo max  cos ωot − ϕo + 30° − 120°   cos ω t − ϕ + 30° + 120°  o o   where m is the modulation index, φi is the input displacement factor, and T is the instantaneous transfer matrix.

Table 13.2: Three-phase voltage to three-phase current matrix converter switch combinations A

B

C

vab vbc vca

A

B

C

vAB vBC vCA

ia ib ic

A C B

-vAB -vCA -vBC

Ib ia ic

0 0 1

B A C

-vAB -vCA -vBC

ib ia ic

1 0 0

B C A

vBC vCA vAB

ic ia ib

1 0 0

0 1 0

C A B

vCA vAB vBC

ib ic ia

0 1

0 1 0

1 0 0

C B A

-vBC -vAB -vCA

ic ib ia

1

0

0

0

0

1

0

0

1

A C C

-vCA 0 vCA

ia 0 -ia

II-A

0

1

0

0

0

1

0

0

1

B C C

vBC 0 -vBC

0 -ia ia

II-A

0

1

0

1

0

0

1

0

0

B A A

-vAB 0 -vAB

ia ia 0

II-A

0

0

1

1

0

0

1

0

0

C A A

vCA 0 -vCA

-ia 0 ia

II-A

0

0

1

0

1

0

0

1

0

C B B

-vBC 0 vBC

0 –ia ia

II-A

1

0

0

0

1

0

0

1

0

A B B

vAB 0 -vAB

ia -ia 0

II-B

0 0 1

1 0 0

0 0 1

C A C

-vCA -vCA 0

ib 0 -ib

II-B

0 0 1

0 1 0

0 0 1

C B C

-vBC vBC 0

0 ib - ib

II-B

1 0 0

0 1 0

1 0 0

A B C

vAB -vAB 0

-ib ib 0

II-B

1 0 0

0 0 1

1 0 0

A C A

-vCA vCA 0

-ia 0 ib

II-B

0 1 0

0 0 1

0 1 0

B C B

vBC -vBC 0

0 –ib ib

II-B

0 1 0

1 0 0

0 1 0

B A B

-vAB vAB 0

ia -ib 0

II-C

0 0 1

0 0 1

1 0 0

C C A

0 vCA -vCA

ic 0 -ic

II-C

0 0 1

0 0 1

0 1 0

C C B

0 -vBC vBC

0 ic -ic

II-C

1 0 0

1 0 0

0 1 0

A A B

0 vAB -vAB

-ic ic 0

II-C

1 0 0

1 0 0

0 0 1

A A C

0 -vCA vCA

-ic 0 ic

II-C

0 1 0

0 1 0

0 0 1

B B C

0 vBC -vBC

0 -ic ic

II-C

0 1 0

0 1 0

1 0 0

B B A

0 -vAB vAB

ic -ic 0

III

1 0 0

1 0 0

1 0 0

A B C

0 0 0

0 0 0

III

0 1 0

0 1 0

0 1 0

A B C

0 0 0

0 0 0

III

0 0 1

0 0 1

0 0 1

A B C

0 0 0

0 0 0

Group

SAa SAb SAc

SBa SBb SBc

SCa SCb SCc

I

1

0

0

0

I

1

0

0

0 0 1

0 1 0

I

0

1

0

1 0 0

I

0

1 0

0 0 1

I

0

0 1

I

0

II-A

1

0

0

0

1

iA iB iC

By equating co-efficients in equation (13.135), the magnitude of the output line to line voltage, in terms of the input phase voltage magnitude is given by

Vo max = ½ 3 × m ×V i max cos ϕi

(13.136)

The maximum voltage gain, when m = 1 and unity input displacement pf, cosφi = 1, the ratio of the peak fundamental ac output voltage to the peak ac input voltage is ½√3 = 0.866. Above this level, called overmodulation, distortion of the input current occurs.

Power Electronics

605

Chapter 13

Expressions similar to equations (13.133) to (13.136) are applicable to the input and output currents. The output current is  i ab   cos ωot − ϕo + 30° − ϕL    I   i o =  i bc  = o max  cos ωot − ϕo + 30° − 120° − ϕL  3  i    ca   cos ωot − ϕo + 30° + 120° − ϕL  where cosφL is the load power factor and Iomax is the amplitude of the output line current.

(13.137)

The relationship between the input and output line currents is i A    i i =  i B  = T phT −L i o i  C  cos ωo t − ϕi    = ½ 3 I o max cos ϕL  cos ωo t − ϕi − 120°   cos ω t − ϕ + 120°  o i   By equating co-efficients, the relationship between the input and output current magnitudes is

I i max = ½ 3 I o max cos ϕL

(13.138)

(13.139)

Additionally the input power must equal the output power, that is

Pi = 3 v i i i cos ϕi = 3 v o i o cos ϕo = Po


606

As with standard sinusoidal PWM, by adding triplens (3rd harmonics from the input and output) q can be increased from ½ to ½√3 = 0.866, as illustrated in part b of figure 13.44.  cos ωot − 1 6 cos 3ωo t + 1 2 3 cos 3ωi t    (13.143) v o = qV i max  cos (ωot + 120° ) − 1 6 cos 3ωot + 1 2 3 cos 3ωi t    1 1  cos (ωot + 120° ) − 6 cos 3ωo t + 2 3 cos 3ωi t  Since no intermediate energy storage stage is involved, such as a dc link, this so called total silicon solution to ac to ac conversion provides no ride-through, thus is not well suited to ups application. The advantage of the matrix converter over a dc link approach to ac to ac conversion lies not in the fact that a dc link capacitor is not required. Given the matrix converter requires an input L-C filter, capacitor size and cost requirements are similar. The key feature of the matrix converter is that the capacitor voltage requirement is ac. For a given temperature, ripple current, etc., the lifetime of an ac capacitor is significantly longer than a dc voltage electrolytic capacitor, as is required for a dc link. The use of oil impregnated paper bipolar capacitors to improve dc-link inverter reliability, significantly increases capacitor volume and cost for a given capacitance and voltage. The key limitations of the matrix converter, hampering its exploitation are • The ac output voltage is restricted to 86.6% of the ac input voltage (without distortion) • The need for a capacitive over voltage 3Φ clamping circuit due commutation spikes • Inter dependence between the input and output voltage and current harmonics • The need for reverse blocking bidirectional current and voltage switches • Minimal ride-through capability

(13.140)

Since the switches are bidirectional and fully controlled, power flow can be bidirectional. Control involves the use of a modulation index, 0 ≤ m ≤ 1, that varies sinusoidally. Modulation strategies If the input currents and output voltages are to be sinusoidal, from equations (13.138) and (13.135), respectively, the voltage gain q=Vomax / Vimax between the output and input voltages is given by 1 + 2q cos ωmt − 120° 1 + 2q cos ωmt + 120°   1 + 2q cos ωmt  M 1 = 1 3  1 + 2q cos ωmt + 120° 1 + 2q cos ωmt 1 + 2q cos ωmt − 120°  (13.141)  1 + 2q cos ω t − 120° 1 + 2q cos ω t + 120° 1 + 2q cos ω t  m m m  

13.6.1 High frequency resonant dc to ac matrix converter

A combination of integral cycle control with a high-frequency single-phase to three-phase matrix converter is shown in figure 13.45. High frequency ac is produced by a H-bridge parallel resonant voltage converter, which is transformer coupled to the matrix converter. A key feature is that both the Hbridge and matrix converter switches, can be soft-switched for low switching losses. Figure 13.46 shows the output voltage waveforms constituted from half-sine resonant voltage pulse components.

where ωm = ω0 – ωi such that φi = φo and

M2 =

1

3

1 + 2q cos ωmt − 120° 1 + 2q cos ωmt + 120°   1 + 2q cos ωmt    1 + 2q cos ωmt − 120° 1 + 2q cos ωmt + 120° 1 + 2q cos ωmt   1 + 2q cos ω t + 120° 1 + 2q cos ω t 1 + 2q cos ωmt − 120°  m m 

(13.142)

where ωm = -(ω0 – ωi) such that φi = - φo

Vs

The solution φi = φo gives the same phase displacement at the input and output ports whereas the solution φi = - φo gives the reversed phase displacement. Combining both solutions provides for input displacement factor control. The maximum voltage ratio is when q = ½. input voltage

maximum output voltage

1

1

0.5

0.5 0

0 0° 0.5 1

120°

240°

maximum output voltage

input voltage

0°

120°

240°

Lr

VH-B

1:n

N

Cr nVCr

a Vab

Zbn

b

Zcn Vbc

360°

360° ωt

ωt 0.5

1

Figure 13.44. Three-phase input voltages and three-phase output voltages showing: (a) maximum output magnitude of 0.5pu and (b) output voltage increased to 0.866 pu with triplen injection.

n

Zan

VaN

Figure 13.45. Twelve switch high frequency ac to ac converter.

c

Vcn

Power Electronics

607

Chapter 13

ωt

VaN

ibn =

ωt

where φn = tan

VbN

-1

nω L

vbn R

cos φn

(13.147)

(A)

R

The load current io is given by io (ωt ) = ∑{ian cos ( nωt − φn ) + ibn sin ( nωt − φn )}

ωt

(A)

(13.148)

∀n

The load efficiency, η, which is related to the power dissipated in the resistive component R of the load, is defined by η = fundamental active power total active power

VcN ωt common mode voltage

=

ωt

½ ( ia21 R + ib21 R )

½∑ ( ian2 R + ibn2 R ) ∀n

Van

608

Derivation of the current waveform Fourier coefficients may prove complicated because of the difficulty of integrating an expression involving equation (13.2), the load current. An alternative and possibly simpler approach is to use superposition and the fact that each load Fourier voltage component produces a load current component at the associated frequency but displaced because of the load impedance at that frequency. That is ian = vRan cos φn (A)

nVCr

VnN


=

ia21 + ib21 ∑ (ian2 + ibn2 )

(13.149)

∀n

phase voltage

In general, the total load power is ∑ vn rms × in rms × cos φn .

ωt

∀n

Vbn

13.7.2 Supply waveforms

phase voltage

ωt

Vab line-to-line voltage

ωt

Figure 13.46. Quasi-square generated voltages of the twelve switch high frequency ac to ac converter.

13.7

Non-linear loads (e.g. rectification):

Power Quality: load efficiency and supply current power factor

One characteristic of ac regulators is non-sinusoidal load current, hence supply current as illustrated in figure 13.1b. Difficulty therefore exists in defining the supply current power factor and the harmonics in the load current may detract from the load efficiency. For example, with a single-phase motor, current components other than the fundamental detract from the fundamental torque and increase motor heating, noise, and vibration. To illustrate the procedure for determining load efficiency and supply power factor, consider the circuit and waveforms in figure 13.1. 13.7.1 Load waveforms

The load voltage waveform is constituted from the sinusoidal supply voltage v and is defined by vo (ωt ) = 2 V sin ωt (V)

α ≤ ωt ≤ β π + α ≤ ωt ≤ π + β

(13.144)

and vo = 0 elsewhere. Fourier analysis of vo yields the load voltage Fourier coefficients van and vbn such that vo (ωt ) = ∑{ van cos nωt + vbn sin nωt} (V)

Linear load: For sinusoidal single and three-phase ac supply voltages feeding a linear load, the load power and apparent power are given by P = Vs I s cos φ S = Vs I s (13.150) P = 3 VLL I s cos φ S = VLL I s and the supply power factor is P cos φ = (13.151) S

i. The supply distortion factor µ, displacement factor cosψ, and power factor λ give an indication of the adverse effects that a non-sinusoidal load current has on the supply as a result of SCR phase control. In the circuit of figure 13.1a, the load and supply currents are the same and given by equation (13.2). The supply current Fourier coefficients isan and isbn are the same as for the load current Fourier coefficients isa and isb respectively, as previously defined. The total supply (input) power factor λ can be defined as

λ = real power apparent power = total mean input power total rms input VA =

v1rms i1rms cosψ 1 = Vrms I rms

for all values of n. The load current can be evaluated by solving di Rio + L o = 2 V sin ωt (V) (13.146) dt over the appropriate bounds and initial conditions. From Fourier analysis of the load current io, the load current coefficients ian and ibn can be derived.

2

vsa2 1 + vsb2 1 × v×

1

1

2

isa2 1 + isb2 1 × cosψ 1

2

(13.152)

i +i 2 a1

2 b1

The supply voltage is sinusoidal hence supply power is not associated with the harmonic nonfundamental currents.

λ= (13.145)

1

v ½ ( isa2 1 + isb2 1 ) cosψ 1 v I rms

(13.153) is1 × cosψ 1 = DFi1 × DPF I rms I rms where cos ψ, termed the displacement power factor, DPF, is the fundamental power factor defined as =

½ ( i + isb2 1 ) cosψ 1 2 sa 1

=

(

cosψ 1 = cos − tan −1 isa1 isb1

)

Equating with equation (13.153), the total supply power factor is defined as λ = µ cosψ 1 0 ≥ λ ≥1

(13.154) (13.155)

Power Electronics

609

Chapter 13

The supply current distortion factor µ is the ratio of fundamental rms current to total rms current isrms, that is ½ ( isa2 1 + isb2 1 )

µ=

is1 I rms

=

irms

(13.156)

=

total harmonic (non - fundamental) rms current (or voltage) fundamental rms current (or voltage)

Ih

is1

=

Ih

I

=

i +i 2 sa1

2 sb1

2 rms

1

−1 =

i +i 2 sa1

2 sb1

µ

2

A half-wave rectifier with a load freewheel diode as shown in figure 11.3 has a 10A constant current load, Io. If rectifier circuit is supplied from the ac mains with voltage v(ωt) = √2 230×sin 2π50t determine: i. the supply apparent power and average load power ii. the total supply power factor, λ, hence distortion, µ, and displacement factors iii. the average and rms current rating of each diode and diode reverse voltage requirements Solution

(13.157)

−1

where Ih is the total harmonic (non-fundamental) current (assuming no dc component) 2 I h = I rms − i2

The rms supply voltage is 230V, at 50Hz. The supply current is a 10ms, 10A current block occurring every 20ms. The rms supply current is therefore 10/√2 = 7.07A. i. The supply apparent power is S = V rms I rms = 230V × 7.07A = 1626.1VAr

s1

=

∞

∑I

1 2

=

2 nrms

n≠1

∞

∑i

2 san

2 + isbn

(13.158)

The average load voltage is that for half wave rectification, viz., 2V Vo = = 103.5V

n≠1

The general relationships between the various current forms can be summarised as I rms = I dc2 + I12rms + I 22rms + I 32rms + .... = I dc2 + I12rms + I H2

(b) Alternatively, the supply total rms harmonic factor ρRMS is defined as: total harmonic (non - fundamental) rms current (or voltage) ρ RMS = total rms current (or voltage) =

Ih

irms

= 1−

π

The average load power, which must be equal to the input power from the 50Hz source, is Po = Pin = Vo I o = 103.5V × 10A = 1035W

(13.159)

= I dc2 + I ac2

or

is21 = 1− µ 2 2 I rms

The fundamental of a square wave, with a dc offset of half the magnitude is 1 ∧ 1 2 I 1rms = I1 = × × 10A = 4.50A 2 2 π which is in phase with the ac supply, that is cosØ50Hz = 1.

(13.160)

Alternately, the load power, hence input power, which is at the supply voltage frequency of 50Hz, can be confirmed by Pin = V rms I rms cos φ50Hz

iii. The supply crest factor δ is defined as the ratio of peak supply current i s to the total rms current:

δ = i s / I rms

(13.161)

iv. The energy conversion factor υ is defined by fundamental output power υ= fundamental input power =

1

2

v +v × 2 a1

2 b1

v×

1

1

2

i + i × cos φ1 2 a1

2 b1

= 230V × 7.07A × 1 = 1035W

ii.

Example 13.7: Power quality - load efficiency

If a purely resistive load R is fed with a voltage vo = 2 V sin ωt +

2V 3

sin 3ωt

what is the fundamental load efficiency? iii.

Solution


2V  1  sin ωt + sin 3ωt  3 R   The load efficiency is given by equation (13.149), that is io = vo R =

2

 2V    R  R  η= 2 2  2V   2V    R+  R  R   3R  1 = = 0.90 1 + 19

The introduced third harmonic component decreases the load efficiency by 10%.

♣

The power factor is

Pin 1035W = = 0.64 S 1626.1VAr The current distortion factor is I 4.50 A = 0.64 DF = µ = 1rms = 7.07 A I rms which, since the supply is single frequency sinusoidal, confirms that the displacement factor for the fundamental current is λ 0.64 cos ψ 1 = = = 1 = cos φ50Hz µ 0.64 that is φ50Hz = 0° pf = λ =

(13.162)

isa2 1 + isb2 1 × cosψ 1

2

610

Example 13.8: Power quality - sinusoidal source and constant current load

ii. (a) The supply fundamental harmonic factor ρF is defined as

ρF =


The average and rms current ratings of both the rectifying diode and the freewheel diode are the same, viz., I I 10A 10A = 5A = 7.07A ID = o = I D rms = o = 2 2 2 2 In reverse bias, each diode experiences alternate ac supply peak voltages of √2 230V = 325.3V

♣ Example 13.9: Power quality - sinusoidal source and non-linear load

An unbalanced single-phase rectifier circuit is supplied from the ac mains with voltage v(ωt) = √2 230×sin 2π50t. The dominant resultant harmonics in the supply current are i (ωt ) = 10 + 15 × sin (ωt + 1 6 π ) + 3 × sin ( 2ω t + ¼π ) + 2 × sin ( 4ω t − ¼π ) Determine i. the fundamental power factor hence power delivered from the supply ii. the total supply power factor, hence distortion factor iii. the harmonic current and the ac current

Power Electronics

611

iv. the total harmonic distortion with respect to the fundamental current and the total rms current v. the current crest factor.

Chapter 13

13.1.

Determine the rms load current for the ac regulator in figure 13.24, with a resistive load R. Consider the delay angle intervals 0 to ½π, ½π to ⅔π, and ⅔π to 7π /6.

13.2.

The ac regulator in figure 13.24, with a resistive load R has one thyristor replaced by a diode. Show that the rms output voltage is ½  1  Vrms =  ( 2π − α + ½ sin 2α )   2π  while the average output voltage is 2V Vo = ( cos α − 1) 2π

13.3.

Plot the load power for a resistive load for the fully controlled and half-controlled three-phase ac 2 regulator, for varying phase delay angle, α. Normalise power with respect to V / R .

13.4.

P50 Hz 2113W = = 0.62 S 230V × 14.8A 15A 2 = × 0.866 = 0.717 × 0.866 = µ cosψ 1 14.8A The total supply power factor λ is 0.62 and the current distortion factor µ is 0.717.

For the tap changer in figure 13.15, with a resistive load, calculate the rms output voltage for a phase delay angle α. If v2 = 200V ac and v1 = 240V ac, calculate the power delivered to a 10 ohm resistive load at delay angles of ¼π, ½π, and ¾π. What is the maximum power that can be delivered to the load?

13.5.

A. 0.01H inductance is added in series with the load in problem 13.4. Determine the load voltage and current waveforms at a firing delay angle of ½π. Assuming a 50 Hz supply, what is the minimum delay angle?

From equation (13.158) the supply harmonic (non 50Hz) current is

13.6.

The thyristor T2 in the single-phase controller in figure 13.1a is replaced by a diode. The supply is 240V ac, 50 Hz and the load is 10Ω resistive. For a delay angle of α = 90°, determine the i. rms output voltage ii. supply power factor iii. mean output voltage iv. mean input current. [207.84 V; 0.866 lagging; 54 V; 5.4 A]

13.7.

The single-phase ac controller in figure 13.6 operating on the 240 V, 50 Hz mains is used to control a 10Ω resistive heating load. If the load is supplied repeatedly for 75 cycles and disconnected for 25 cycles, determine the i. rms load voltage, ii. input power factor, λ, and iii. the rms thyristor current.

13.8

The ac controller in problem 13.3 delivers 2.88kW. Determine the duty cycle, m/N, and the input power factor, λ.

13.9

A single-phase ac controller with a 240Vac 50Hz voltage source supplies an R-L load of R=40Ω and L=50mH. If the thyristor gate delay angle is α = 30°, determine: i. an expression for the load current ii. the rms load current iii. the rms and average current in the thyristors iv. the power absorbed by the load v. sketch the load, supply and thyristor voltages and currents.

The power from the supply delivered to the load is only at the supply frequency P50 Hz = Vs 50 Hz I s 50 Hz cos φ50 Hz 15A

× cos 1 6 π = 2113W 2 The fundamental power factor cos 1 6 π = 0.866, leading. = 230V ×

ii.

The total supply power factor is P V I × cos φ50 Hz I s 50 Hz pf = λ = 50 Hz = s 50 Hz s 50 Hz = × cos φ50 Hz = µ cosψ 1 S Vs 50 Hz × I s Is The supply rms current Is is 2

2

2

 15A   3A   2A  I s = 10A 2 +   +  +  = 14.8A  2   2  2

Hence

λ=

iii.

2 I h = I rms − is21 2

 15  = 14.82 −   = 10.3A  2 and from equation (13.159) the ac supply current (non-dc) is 2 − I dc2 I ac = I rms = 14.8A 2 − 10A 2 = 10.9A

iv.

v.

612

Problems

Solution i.


From equations (13.157) and (13.160), total harmonic distortions on the supply current are total harmonic (non - 50Hz) rms current ρF = fundamental rms current 1 1 Ih = = −1 = − 1 = 0.97 is1 µ2 0.717 2 and total harmonic (50Hz) rms current ρ RMS = total rms current I = h = 1 − µ 2 = 1 − 0.717 2 = 0.70 irms The current crest factor is given by equation (13.161), namely δ = i s / I rms . The maximum supply current will be dominated by the dc and 50Hz components thus the maximum will be near ωt+π =½π, ωt =π. Iteration around ωt =π gives i s =28.85A at ωt =0.83 rad. is 28.85A δ= = = 1.95 I rms 14.8A ♣ Reading list

Hart, D.W., Introduction to Power Electronics, Prentice-Hall, Inc, 1994. Rombaut, C., et al., Power Electronic Converters – AC/AC Conversion, North Oxford Academic Publishers, 1987.

13.10. A single-phase thyristor ac controller is to delivery 500W to an R-L load of R=25Ω and L=50mH. If the ac supply voltage is 240V ac at 50Hz, determine i. thyristor rms and average current ii. maximum voltages across the thyristors. 13.11. The thyristor T2 in the single-phase controller in figure 13.1a is replaced by a diode. The supply is 240V ac, 50 Hz and the load is 10Ω resistive. Determine the i. an expression for the rms load voltage in terms of α ii. the range of rms voltage across the load resistor.

Chapter 14

DC Choppers

io

14

614

io

io io

DC Choppers Q1

Vo

A dc chopper is a dc-to-dc voltage converter. It is a static switching electrical appliance that in one electrical conversion, changes an input fixed dc voltage to an adjustable dc output voltage without inductive or capacitive intermediate energy storage. The name chopper is connected with the fact that the output voltage is a ‘chopped up’ quasi-rectangular version of the input dc voltage. In chapters 12 and 13, thyristor devices were used in conjunction with an ac supply that forces thyristor turn-off at ac supply current reversal. This form of thyristor natural commutation, which is illustrated in figure 14.1a, is termed line or source commutation. When a dc source is used with a thyristor circuit, energy source facilitated commutation is clearly not possible. If the load is an R-C or L-C circuit as illustrated in figure 14.1b, the load current falls to zero whence the thyristor in series with the dc supply turns off. Such a natural turn-off process is termed load commutation. If the supply is dc and the load current has no natural zero current periods, such as with the R-L load, dc chopper circuit shown in figure 14.1c, the load current can only be commutated using a selfcommutating switch, such as a GTO thyristor, GCT, IGBT or MOSFET. An SCR is not suitable since once the device is latched on in this dc supply application, it remains on. The dc chopper in figure 14.1c is the simplest of the five dc choppers to be considered in this chapter. This single-ended, grounded-load, dc chopper will be extensively analysed. See example 14.3. 14.1

DC chopper variations

There are five types of dc choppers, of which four are a subset of the fifth - the flexible but basic, fourquadrant H-bridge chopper shown in the centre of figure 14.2. Notice that the circuits in figure 14.2 are highlighted so that the derivation of each dc chopper from the fundamental H-bridge four-quadrant, dc chopper can be seen. Each chopper can be categorized depending on which output Io-Vo quadrant or quadrants it can operate in, as shown in figure 14.2. The five different choppers in figure 14.2 are classified according to their output Io - Vo capabilities as follows: (a) First quadrant I +Vo +Io using switch/diode T1 D1 (b) Second quadrant II +Vo -Io using switch/diode T2 D2 (c) Two quadrant I and II +Vo ±Io using switches/diodes T1 D1 T2 D2 (d) Two quadrant I and IV ±Vo +Io using switches/diodes T1 D1 T4 D4 (e) Four quadrant I, II, III, and IV ±Vo ±Io using switches/diodes T1-4 D1-4 In the five choppers in figure 31.2, the subscript of the active switch or switches and diodes specify in which quadrants operation is possible. For example, the chopper in figure 14.2d uses switches T1 and T3, (plus diodes D1 and D3) so can only operate in the first (+Io,+Vo) and third (-Io,-Vo) quadrants. The first-quadrant chopper in figure 14.2a (and figure 14.1c) can only produce a positive voltage across the load since the freewheel diode D1 prevents a negative output voltage. Also, the chopper can only deliver current from the dc source to the load through the unidirectional switch T1. It is therefore a single quadrant chopper and only operates in the first quadrant (+Io,+Vo), where Vo ≤ Vs. The second-quadrant chopper, (-Io,+Vo), in figure 14.2b is a voltage boost circuit and current flows from the load to the supply, Vs. The switch T2 is turned on to build-up the inductive load current. Then when the switch is turned off current is forced to flow through diode D2 into the dc supply. The two current paths (when the switch is on and when it is off) are shown in figure 14.2b.

BWW

io T

Io

on io

o ff

Figure 14.1. Three basic types of switch commutation techniques: (a) source commutation; (b) load commutation; and (c) switch commutation.

In the two-quadrant chopper, quadrants I and II chopper, (±Io,+Vo), figure 14.2c, the load voltage is clamped to between 0V and Vs, because of the freewheel diodes D1 and D2. Because this chopper is a combination of the first-quadrant chopper in figure 14.2a and the second-quadrant chopper in figure 14.2b, it combines the characteristics of both. Bidirectional load current is possible but the average output voltage is always positive. Energy can be regenerated into the dc supply Vs due to the load inductive stored energy which maintains current flow from the back emf source ( ½ produces a positive average load voltage. Since Vo is reversible, the power flow direction is reversible, for the shown current io. Zero voltage loops are created when one of the two switches is turned off. The four-quadrant chopper in the centre of figure 14.2 combines all the properties of the four subclass choppers. It uses four switched and is capable of producing positive or negative voltages across the load, whilst delivering current to the load in either direction, (±Io,±Vo). The step-up chopper, or boost converter, presented in Chapter 17.4, may be considered a dc chopper variation, which has second quadrant characteristics, while the step-down converter presented in Chapter 17.1 can be considered a first quadrant dc chopper. 14.2

First-Quadrant dc chopper

The basic first-quadrant dc chopper circuit reproduced in figure 14.3a can be used to control a dc load such as a dc motor. As such, the dc load has a back-emf component, E = kφ ω , the magnitude and polarity of which are dependant on the flux φ , (field current if) and its direction, and the speed ω and its direction. If the R-L load (with time constant τ = L /R) incorporates an opposing back emf, E, then when the switch T1 is off and the diode D1 is conducting, the load current can be forced towards zero by the opposing back emf. Therefore two output load current modes (continuous and discontinuous load current) can occur depending on the relative magnitude of the back emf, load time constant, and the switch on-state duty cycle. Continuous load current waveforms are shown in figure 14.3b, while waveforms for discontinuous load current, with periods of zero current, are shown in figure 14.3c.

Power Electronics

615

Chapter 14

DC Choppers

vo

on

on

Vs

616

T1

Vs

vo

T1

Vs

D4

vo

I

T1

io LOAD

LOAD

LOAD io

D1

D1

T4

D1

off

off (a)

(a)

vo

(d)

vo II

I

III

io

vo

I

I

IV io

IV io

on

T1

Vs

Vs io

io

Vs

T1

T3

D4

D2

R

vo

LOAD T2

D1

D3

vo

II

II (e)

(b) (a) conducting devices

io

Vs

T1

D1

T1

D1

T1

on

off

on

off

on

∧

∧

I

D1 ioiℓ

∧

I

I

T1

D2

vo

∨

on

I

LOAD T2

D1

T1

on

off

on

∧

I Io

t

t

vo

D1

tx

vo

Vs

Vs

Vo (b)

(c)

Figure 14.2. Fundamental four-quadrant chopper (centre) showing derivation of four subclass dc choppers: (a) first-quadrant chopper - I; (b) second-quadrant chopper - II; (c) first and second quadrants chopper – I and II; (d) first and fourth quadrants chopper – I and IV; and (e) four-quadrant chopper.

In both conduction cases, the average voltage across the load can be controlled by varying the on-to-off time duty cycle of the switch, T1. The on-state duty cycle, δ, is normally controlled by using pulse-width modulation, frequency modulation, or a combination of both. When the switch is turned off the inductive load current continues and flows through the load freewheel diode, D1, shown in figure 14.3a The analysis to follow for all the dc choppers, assumes • No source impedance • Constant switch duty cycle • Steady state conditions have been reached • Ideal semiconductors and • No load impedance temperature effects.

D1 off ∧

I

∨

I

LOAD

T1

Io

vo

T2

+ E

(c) (b)

I

off

D2

L

vo off

iioℓ

Vs

R

D D21

T4

vo

io

+ E

L

vo

E

t

t tT

tT

T (b)

Vo

E

T (c)

Figure 14.3. First-quadrant dc chopper and two basic modes of chopper output current operation: (a) basic circuit and current paths; (b) continuous load current; and (c) discontinuous load current after t = tx.

14.2.1 Continuous load current Load waveforms for continuous load current conduction are shown in figure 14.3b. The output voltage vo, or load voltage is defined by for 0 ≤ t ≤ tT  Vs vo ( t ) =   for tT ≤ t ≤ T  0

(14.1)

Power Electronics

The mean load voltage (hence mean load current) is 1 t 1 t Vo = ∫ vo ( t ) dt = ∫ Vs dt T 0 T 0 t V −E = T Vs = δ Vs whence I o = o R T where the switch on-state duty cycle δ = tT /T is defined in figure 14.3b. The rms load voltage is ½ ½ 1 t  1 t  Vrms =  ∫ vo2 ( t ) dt  =  ∫ Vs2 dt  T 0  T 0  T

Chapter 14

T

(14.2)

(14.3)

The output ac ripple voltage is 2 Vr = Vrms − Vo2

(

=

)

2

δ Vs − (δ Vs ) = Vs δ (1 − δ ) 2

(14.4)

The maximum rms ripple voltage in the output occurs when δ = ½ giving an rms ripple voltage of ½Vs. The output voltage ripple factor is RF =

2

V  =  rms  − 1 = FF 2 − 1 Vo  Vo  Vr

2

Steady-state time domain analysis of first-quadrant chopper - with load back emf and continuous output current

(14.7)

−1

(A)

(14.13) t Vs e τ − 1 E and I = − (A) T R τ R e −1 The output ripple current, for continuous conduction, is independent of the back emf E and is given by T

∨

∨

Vs (1 − e τ ) (1 − e −T R 1− e τ

1

(14.8)

− T + tT

τ

)

(14.14)

− (1−δ )T

τ

)

(14.15) T/τ

1

25 pu dc output mean

¾

5

¾

st

1 harmonic

½

Ipp

2

½

Vs / R

1

nd

2 harmonic

¼

½

¼

rd

3 harmonic 0

0 0

¼

½

¾

on-state duty cycle δ

such that vo ( t ) = Vo +

E R

−

−δ T

n

vn = cn sin ( n ωt + φn )

− tT

Vs 1 − e τ −T R 1− e τ

∧

where I =

I p− p =

φn = tan −1 an b

(14.10)

2

− tT

cn = a + b

where

∑

Vs (1 − e τ ) (1 − e −T R 1− e τ which in terms of the on-state duty cycle, δ=tT /T, becomes

2 n

sin 2π nδ = tan −1 cot π nδ = ½π − π nδ φn = tan 1 − cos 2π nδ

∑

=

∧

i. Fourier coefficients: The Fourier coefficients of the load voltage are independent of the circuit and load parameters and are given by V an = s sin 2π nδ nπ (14.6) V for n ≥ 1 bn = s (1 − cos 2π nδ ) nπ Thus the peak magnitude and phase of the nth harmonic are given by

π

n

I p − p = ∆io = I − I =

The time domain load current can be derived in a number of ways. • First, from the Fourier coefficients of the output voltage, the current can be found by dividing by the load impedance at each harmonic frequency. • Alternatively, the various circuit currents can be found from the time domain load current equations.

Substituting expressions from equation (14.6) yields 2V cn = s sin π nδ n

n=0

ii. Time domain differential equations: By solving the appropriate time domain differential equations, the continuous load current shown in figure 14.3b is defined by During the switch on-period, when vo(t) = Vs di L o + R io + E = Vs dt which yields −t V −E  ∨ −t (14.11) 1− e τ  + I e τ io ( t ) = s for 0 ≤ t ≤ tT R   During the switch off-period, when vo(t) = 0 di L o + R io + E = 0 dt which, after shifting the zero time reference to tT, in figure 14.3a, gives −t E  ∧ −t for 0 ≤ t ≤ T − tT (14.12) io ( t ) = −  1 − e τ  + I e τ R 

(14.5)

 δ Vs  1 1−δ =  −1 = −1 =  δ Vs  δ δ   Thus as the duty cycle δ → 1 , the ripple factor tends to zero, consistent with the output being dc, that is Vr = 0.

2 n

618

∞ ∞ cn sin ( n ωt − φn ) vn Vo V + = o+ R n =1 Z n R n =1 Zn where the load impedance at each harmonic frequency is given by ∞

∑i

io ( t ) =

Zn = R2 + ( n ω L )

T

tT Vs = δ Vs T

=

DC Choppers


T

harmonic rms as % of dc supply Vs

617

1

0

¼

½

¾

1

δ on-state duty cycle

Figure 14.4. Harmonics in the output voltage and ripple current as a function of duty cycle δ = tT /T and ratio of cycle period T (switching frequency, fs=1/T) to load time constant τ=L /R. Valid only for continuous load current conduction.

∞

∑ c sin ( n ωt + φ ) n =1

∞

n

n

2Vs = δ Vs + sin π nδ cos ( n (ωt − πδ ) ) nπ n =1

∑

(14.9)

The peak-to-peak ripple current can be extracted from figure 14.4, which shows a family of curves for equation (14.15), normalised with respect to Vs / R. For a given load time constant τ = L /R, switching frequency fs = 1/T, and switch on-state duty cycle δ, the ripple current can be extracted. This figure shows a number of important features of the ripple current.

Power Electronics

619

• • • •

Chapter 14

The ripple current Ipp reduces to zero as δ →0 and δ →1. Differentiation of equation (14.15) reveals that the maximum ripple current I p − p occurs at δ = ½. The longer the load L /R time constant, τ, the lower the output ripple current Ip-p. The higher the switching frequency, 1/T, the lower the output ripple.

If the switch conducts continuously (δ = 1), then substitution of tT=T into equations (14.11) to (14.13) gives a load voltage Vs and a dc load current is ∧ ∨ V − E  Vo − E  io = I = I = s (14.16) (A)  = R = Io  R   The mean output current with continuous load current is found by integrating the load current over two consecutive periods, the switch conduction given by equation (14.11) and diode conduction given by equation (14.12), which yields 1 Io = T

T

∫

0

(V i ( t ) dt =

o

−E

)

o

R

(δ V =

− E) s

(14.17) (A)

R The input and output powers are related such that Pin = Pout

 δ (Vs − E ) τ  ∧ ∨   Pin = Vs I i = VS  −  I − I  R T   T 1 Pout = ∫ vo ( t ) io ( t ) dt T 0

(14.18)

δV −E  = I o2rms R + E I o = I o2 rms R + E  s   R  from which the average input current can be evaluated.

DC Choppers

620

For an R-L load without a back emf, set E = 0 in the foregoing equations. The discontinuous load current analysis to follow is not valid for an R-L, with E=0 load, since the load current never reaches zero, but at best asymptotes towards zero during the off-period of the switch. 14.2.2 Discontinuous load current

With an opposing emf E in the load, the load current can reach zero during the off-time, at a time tx shown in figure 14.3c. The time tx can be found by ∧ • deriving an expression for I from equation (14.11), setting t = tT, • this equation is substituted into equation (14.12) which is equated to zero, having substituted for t = tx: yielding −t  V −E  1− e τ  (s) (14.24) t x = tT + τ ln  1 + s  E    T

This equation shows that tx > tT. Alternatively, for a given frequency, 1/T, discontinuous current will occur as the duty cycle is decreased. ∨ Rearranging equation (14.13), after setting I = 0 and extracting the duty cycle δ = t T /T yields   t E  T τ (14.25) δ = T ≤ A n 1 +  e τ − 1   T T V   s  Conversely, discontinuous conduction will occur as the frequency decreases for a given switch on-time, according to  V  tT  1 (14.26) T = ≥ τ A n 1 + s  e τ − 1   f E    Figure 14.5 can be used to determine if a particular set of operating conditions involves discontinuous load current.

Alternatively, the average input current, which is the average switch current, Iswitch , can be derived by integrating the switch current which is given by equation (14.11), that is 1 t I i = I switch = ∫ io ( t ) dt T 0 −t 1 t V − E   ∨ −t  (14.19) = ∫  s 1 − e τ  + I e τ  dt T 0  R    δ (Vs − E ) τ  ∧ ∨  = − I− I  R T  ∧ ∨ The term I − I = I p − p is the peak-to-peak ripple current, which is given by equation (14.15). By Kirchhoff’s current law, the average diode current Idiode is the difference between the average output current Io and the average input current, Ii , that is Idiode = Io − Ii

1

=

(δ V

s

− E)

R

−

δ (Vs − E ) R

E (1 − δ ) τ =  I − I  − T R  ∧

+

τ ∧ ∨ I− I  T 

E / Vs

¾

co nt in uo us

di sc on

T

tin uo us

po n ss o t ib le

T

δ

½

(14.20) T/τ

∨

Alternatively, the average diode current can be found by integrating the diode current given in equation (14.12), as follows −t 1 T −t  E   ∧ −t  Idiode = ∫  −  1 − e τ  + I e τ  dt T 0  R   (14.21) τ  ∧ ∨  E (1 − δ ) = I− I − T R 

0

1

2

5

10

∞ ?

¼

T

If E represents motor back emf, then the electromagnetic energy conversion efficiency is given by EI EI η= o = o (14.22) Pin Vs I i The chopper effective (dc) input impedance at the dc source is given by V Z in = s Ii

E / Vs

(14.23)

0 0

¼

½ δ switch on-state duty

¾

1

Figure 14.5. Bounds of discontinuous load current with E>0.

The load voltage waveform for discontinuous load current conduction shown in figure 14.3c is defined by for 0 ≤ t ≤ tT  Vs   (14.27) vo ( t ) = 0 for tT ≤ t ≤ t x  E for t x ≤ t ≤ T  

Power Electronics

621

Chapter 14

If discontinuous load current exists for a period T - tx, from tx until T, then the mean output voltage is t T 1 t  thence I o = Vo − E  Vo = Vs dt + ∫ 0 dt + ∫ Edt  R  t t T ∫0  (14.28) T − tx Vo = δ Vs + E (V) for t x ≥ tT T The rms output voltage with discontinuous load current conduction is given by ½ t T 1 t  Vrms =  ∫ Vs2 dt + ∫ 02 d + ∫ E 2 dt  0 t t T  (14.29) T − tx 2 2 (V) = δ Vs + E T The ac ripple voltage and ripple factor can be found by substituting equations (14.28) and (14.29) into

(

T

)

x

T

x

(

T

x

T

x

)

2 Vr = Vrms − Vo2

(14.30)

and

DC Choppers

622

∨

Since I = 0 , the mean output current for discontinuous conduction, is −t −t t -t − 1 t 1  t V −E   ∧ −t  E I o = ∫ io ( t ) dt =  ∫ s 1 − e τ  dt + ∫ 1 − e τ  + I e τ dt  0 R  T 0 T  0 R     x

=

(V

Io =

o

−E

T

)

R  t    R

δ Vs +  1 − x  E T

x T

tx    δVs − T E  E   − = R R

(A)

The input and output powers are related such that Pin = Vs I i Pout = Io2rms R + E I o Pin = Pout

(14.39)

(14.40)

from which the average input current can be evaluated. RF =

2

V  =  rms  − 1 = FF 2 − 1 Vo  Vo  Vr

(14.31)

Alternatively the average input current, which is the switch average current, is given by 1 t Ii = I switch = ∫ io ( t ) dt T 0 −t 1 t V −E  1 − e τ  dt = ∫ s T 0 R   T

T

Steady-state time domain analysis of first-quadrant chopper - with load back emf and discontinuous output current

i. Fourier coefficients: The load current can be derived indirectly by using the output voltage Fourier series. The Fourier coefficients of the load voltage are V E t sin 2π n x an = s sin 2π nδ − T nπ nπ (14.32) Vs E  bn = n ≥1 (1 − cos 2π nδ ) − 1 − cos 2π n tx T  nπ nπ   which using

=

Vs − E  τ   δ − 1 − e R  T

n

give ∞

vo ( t ) = Vo + ∑ cn sin ( n ωt + φn )

(14.33)

n =1

The appropriate division by Z n = R 2 + ( nω L ) yields the output current. 2

∨

ii. Time domain differential equations: For discontinuous load current, I = 0. Substituting this condition into the time domain equations (14.11) to (14.14) yields equations for discontinuous load current, specifically: During the switch on-period, when vo(t) = Vs, −t V −E  1− e τ  (14.34) io ( t ) = s for 0 ≤ t ≤ tT R   During the switch off-period, when vo(t) = 0, after shifting the zero time reference to tT, −t E  ∧ −t for 0 ≤ t ≤ t x − tT (14.35) io ( t ) = − 1 − e τ  + I e τ R  where from equation (14.34), with t = tT, −t Vs − E   1− e τ  (A) R   After tx, vo(t) = E and the load current is zero, that is io ( t ) = 0 for t x ≤ t ≤ T ∧

I=

T

(14.36) (14.37)

The output ripple current, for discontinuous conduction, is dependent of the back emf E and is given by equation (14.36), that is −t ∧ V −E  I p− p = I = s 1− e τ  (14.38)  R   T

τ

(14.41)

τ   Vs − E  = R δ − T I 

The average diode current Idiode is the difference between the average output current Io and the average input current, Ii , that is Idiode = Io − Ii t  E  x −δ  T   = I− T R

τ

cn = an2 + bn2

φn = tan −1 an b

− tT

∧

(14.42)

Alternatively, the average diode current can be found by integrating the diode current given in equation (14.35), as follows −t 1 t −t  E   ∧ −t  Idiode = ∫ 1 − e τ  + I e τ  dt − T 0  R    (14.43)  tx  E −δ  τ ∧ T   = I− T R x

T

If E represents motor back emf, then electromagnetic energy conversion efficiency is given by EI EI (14.44) η= o = o Pin Vs I i The chopper effective input impedance is given by V (14.45) Z in = s Ii Example 14.1: DC chopper (first quadrant) with load back emf

A first-quadrant dc-to-dc chopper feeds an inductive load of 10 Ω resistance, 50mH inductance, and back emf of 55V dc, from a 340V dc source. If the chopper is operated at 200Hz with a 25% on-state duty cycle, determine, with and without (rotor standstill, E = 0) the back emf: i. the load average and rms voltages; ii. the rms ripple voltage, hence ripple factor; iii. the maximum and minimum output current, hence the peak-to-peak output ripple in the current; iv. the current in the time domain; v. the average load output current, average switch current, and average diode current; vi. the input power, hence output power and rms output current; vii. effective input impedance, (and electromagnetic efficiency for E > 0); and viii. sketch the output current and voltage waveforms.

Power Electronics

623

Chapter 14

DC Choppers

Solution

∧

624

−t

io = I e τ

The main circuit and operating parameters are • on-state duty cycle δ = ¼ • period T = 1/fs = 1/200Hz = 5ms • on-period of the switch tT = 1.25ms • load time constant τ = L /R = 0.05mH/10Ω = 5ms

T1

δ=¼ T=5ms

Vs

−t

io ( t ) = 11.90 × e 5ms

Figure 14.6. Example 14.1. Circuit diagram.

10Ω 50mH

340V R

L

+ E

D1

55V

for 0 ≤ t ≤ 3.75ms

(A)

v. The average load current from equation (14.17), with E = 0, is I o = V o = 85V = 8.5A R 10Ω The average switch current, which is the average supply current, is δ (Vs − E ) τ  ∧ ∨  I i = Iswitch = − I− I  R T  ¼ × ( 340V - 0 ) 5ms = × (11.90A - 5.62A ) = 2.22A 10Ω 5ms The average diode current is the difference between the average load current and the average input current, that is Idiode = Io − Ii = 8.50A - 2.22A = 6.28A

i. From equations (14.2) and (14.3), assuming continuous load current, the average and rms output voltages are both independent of the back emf, namely t Vo = T Vs = δ Vs T = ¼×340V = 85V t Vr = T Vs = δ Vs T

vi. The input power is the dc supply voltage multiplied by the average input current, that is Pin = Vs I i =340V×2.22A = 754.8W Pout = Pin = 754.8W From equation (14.18) the rms load current is given by P I o = out R rms

= ¼ × 240V = 120V rms

=

ii. The rms ripple voltage hence ripple factor are given by equations (14.4) and (14.5), that is 2 Vr = Vrms − Vo2 = Vs δ (1 − δ )

= 340V ¼ × (1 - ¼ ) = 147.2V ac

and RF =

Vr 1 = − 1 = FF 2 − 1 δ Vo

1 = -1 = ¼

3 = 1.732

754.8W 10Ω

= 8.7A rms

vii. The chopper effective input impedance is V Z in = s Ii 340V = = 153.2 Ω 2.22A Load back emf, E = 55V

FF = 2

No back emf, E = 0

i. and ii. The average output voltage (85V), rms output voltage (120V rms), ac ripple voltage (147.2V ac), and ripple factor (1.732) are independent of back emf, provided the load current is continuous. The earlier answers for E = 0 are applicable. iii. From equation (14.13), the maximum and minimum load currents are − tT

iii. From equation (14.13), with E = 0, the maximum and minimum currents are − tT

∧

I=

Vs 1 − e τ 340V 1 − e × = 11.90A −T = -5ms R 1− e τ 10Ω 1 − e 5ms tT

V e τ − 1 340V e − 1 I= s T = × 1 = 5.62A R e τ − 1 10Ω e −1 1

∨

4

The peak-to-peak ripple in the output current is therefore ∧

∧

I=

-1.25ms 5ms

∨

I p− p = I − I

=11.90A - 5.62A = 6.28A Alternatively the ripple can be extracted from figure 14.4 using T/τ =1 and δ = ¼.

iv. From equations (14.11) and (14.12), with E = 0, the time domain load current equations are −t V   ∨ −t io = s  1 − e τ  + I e τ R  −t −t   io ( t ) = 34 ×  1 − e 5 ms  + 5.62 × e 5ms  

tT

Vs e τ − 1 E 340V e − 1 55V − = × 1 − = 0.12A T R eτ −1 R 10Ω e −1 10Ω The peak-to-peak ripple in the output current is therefore 1

∨

I=

∧

4

∨

I p− p = I − I

= 6.4A - 0.12A = 6.28A The ripple value is the same as the E = 0 case, which is as expected since ripple current is independent of back emf with continuous output current. Alternatively the ripple can be extracted from figure 14.4 using T/τ = 1 and δ = ¼.

iv. The time domain load current is defined by −t V −E  ∨ −t io = s 1− e τ  + I e τ R   −t −t   io ( t ) = 28.5 × 1 − e 5 ms  + 0.12e 5ms   −t

−t

= 34 − 28.38 × e 5ms

-1.25ms

Vs 1 − e τ E 340V 1 − e 5ms 55V − = × = 6.40A −T -5ms R 1− e τ R 10Ω 10Ω 1 − e 5ms

(A)

for 0 ≤ t ≤ 1.25ms

= 28.5 − 28.38e 5ms

(A)

for 0 ≤ t ≤ 1.25ms

Power Electronics

625

Chapter 14

= −5.5 + 11.9e

=

for

(A)

0 ≤ t ≤ 3.75ms

v. The average load current from equation (14.39) is I o = Vo − E R = 85V-55V = 3A 10Ω The average switch current is the average supply current, δ (Vs − E ) τ  ∧ ∨  I i = Iswitch = −  I− I  R T  ¼ × ( 340V - 55V ) 5ms = × ( 6.40A - 0.12A ) = 0.845A 10Ω 5ms The average diode current is the difference between the average load current and the average input current, that is Idiode = Io − Ii = 3A - 0.845A = 2.155A

=

Pout − E I o R

=

287.3W - 55V×3A = 3.5A rms 10Ω

io

Io

T1

D1

T1

-1.25ms  340V - 55V   = 1.25ms + 5ms × An  1 + ×  1 - e 5ms   = 5.07ms 55V   

8.5A

∆io=6.28A

Vs

I

T

t 5ms E=0

T1

D1

6.4A 3A

Io

Vs 85V

o 1¼ms

D1

Since the cycle period is 5ms, which is less than the necessary time for the current to fall to zero (5.07ms), the load current is continuous. From example 14.1 part iv, with E = 55V the load current falls from 6.4A to near zero (0.12A) at the end of the off-time, thus the chopper is operating near the verge of discontinuous conduction. A small increase in E, decrease in the duty cycle δ, or increase in switching period T, would be expected to result in discontinuous load current. ∧

∆io=6.28A∨ 0.12A I

t

tT

E

340V 85V o 1¼ms

i. E The necessary back emf can be determined graphically or analytically. Graphically: The bounds of continuous and discontinuous load current for a given duty cycle, switching period, and load time constant can be determined from figure 14.5. Using δ = ¼, T/τ = 1 with τ = 5ms, and T = 5ms, figure 14.5 gives E / Vs = 0.165. That is, E = 0.165×Vs = 0.165×340V = 56.2V

vo

340V

Vo

T1

∧

t tT

D1

I

∨

5.62A

vo

T1 io

I

the maximum back emf before discontinuous load current conduction commences with δ=¼; with 55V back emf, what is the minimum duty cycle before discontinuous load current conduction; and minimum switching frequency at E = 55V and tT = 1.25ms before discontinuous conduction.

T

D1

∧

11.9A

i. ii.

First it is necessary to establish whether the given conditions represent continuous or discontinuous load current. The current extinction time tx for discontinuous conduction is given by equation (14.24), and yields −t  V −E  t x = tT + τ An 1 + s 1− e τ  E   

Conducting device

D1

A first-quadrant dc-to-dc chopper feeds an inductive load of 10 Ω resistance, 50mH inductance, and back emf of 55V dc, from a 340V dc voltage source. If the chopper is operated at 200Hz with a 25% onstate duty cycle, determine:

The main circuit and operating parameters are • on-state duty cycle δ = ¼ • period T = 1/fs = 1/200Hz = 5ms • on-period of the switch tT = 1.25ms • load time constant τ = L /R = 0.05mH/10Ω = 5ms

vii. The chopper effective input impedance is V Z in = s Ii 340V = = 402.4 Ω 0.845A

T1

Example 14.2: DC chopper with load back emf - verge of discontinuous conduction

Solution

Pout = Pin = 287.3W From equation (14.18) the rms load current is given by rms

55V×3A = 57.4% 287.3W

viii. The output voltage and current waveforms for the first-quadrant chopper, with and without back emf, are shown in figure 14.7. ♣

iii.

vi. The input power is the dc supply voltage multiplied by the average input current, that is Pin = Vs I i =340V×0.845A = 287.3W

Io

626

The electromagnetic efficiency is given by equation (14.22), that is EI η= o Pin

−t E  ∧ −t 1− e τ  + I e τ R   −t −t   io ( t ) = −5.5 × 1 − e 5ms  + 6.4e 5 ms  

io = −

−t 5ms

DC Choppers

Vo

E=55V 5ms E = 55V

Figure 14.7. Example 14.1. Circuit waveforms.

t

tT

Analytically: The chopper is operating too close to the boundary between continuous and discontinuous load current conduction for accurate readings to be obtained from the graphical approach, using figure 14.5. Examination of the expression for minimum current, equation (14.13), gives tT

∨

I=

Vs e τ − 1 − T R eτ −1

E R

=0

Power Electronics

627

Chapter 14

DC Choppers

628

Rearranging to give the back emf, E, produces tT

E = Vs

e τ −1 e −1 τ

= 340V ×

e

1.25ms 5ms 5ms

Vs

-1

= 56.2V

e 5ms -1 That is, if the back emf increases from 55V to 56.2V then at and above that voltage, discontinuous load current commences. ∨

10Ω 50mH

R

R

340V

L

δ=¼ T=5ms

L

100V E

10Ω 50mH T1

E+ 100V

D1

0V (a)

0V

tT

Vs e τ − 1 E − =0 T R eτ −1 R Rearranging to isolate tT gives  E T  tT = τ An  1 +  e τ − 1  V  s  

Vs

340V

ii. δ ∨ Again, if equation (14.13) is solved for I = 0 then

+

D1

T1

δ=¼ T=5ms

T

(b)

∨

I=

 55V  5ms  = 5ms × An  1 + e 5ms - 1  340V    = 1.226ms If the switch on-state period is reduced by 0.024ms, from 1.250ms to 1.226ms (δ = 24.52%), operation is then on the verge of discontinuous conduction. ∧

iii. T If the switching frequency is decreased such that T = tx, then the minimum period for discontinuous load current is given by equation (14.24). That is, −t  V −E  t x = T = tT + τ An 1 + s 1− e τ   E    T

-1.25ms  340V - 55V   ×  1 - e 5ms   = 5.07ms T = 1.25ms + 5ms × An  1 + 55V    Discontinuous conduction operation occurs if the period is increased by more than 0.07ms.

In conclusion, for the given load, for continuous conduction to cease, the following operating conditions can be changed • increase the back emf E from 55V to 56.2V • decrease the duty cycle δ from 25% to 24.52% (tT decreased from 1.25ms to 1.226ms) • increase the switching period T by 0.07ms, from 5ms to 5.07ms (from 200Hz to 197.2Hz), with the switch on-time, tT, unchanged from 1.25ms. Appropriate simultaneous smaller changes in more than one parameter would suffice. ♣

Example 14.3: DC chopper with load back emf – discontinuous conduction

A first-quadrant dc-to-dc chopper feeds an inductive load of 10 Ω resistance, 50mH inductance, and an opposing back emf of 100V dc, from a 340V dc source. If the chopper is operated at 200Hz with a 25% on-state duty cycle, determine: i. ii. iii. iv. v. vi. vii. viii.

the load average and rms voltages; the rms ripple voltage, hence ripple and form factors; the maximum and minimum output current, hence the peak-to-peak output ripple in the current; the current in the time domain; the load average current, average switch current and average diode current; the input power, hence output power and rms output current; effective input impedance, and electromagnetic efficiency; and sketch the circuit, load, and output voltage and current waveforms.

Figure 14.8. Example 14.3. Circuit diagram: (a) with load connected to ground and (b) load connected so that machine flash-over to ground (0V), by-passes the switch T1.

Solution

The main circuit and operating parameters are • on-state duty cycle δ = ¼ • period T = 1/fs = 1/200Hz = 5ms • on-period of the switch tT = 1.25ms • load time constant τ = L /R = 0.05mH/10Ω = 5ms Confirmation of discontinuous load current can be obtained by evaluating the minimum current given by equation (14.13), that is tT

∨

I=

Vs e τ − 1 E − T R eτ −1 R 1.25ms

340V e 5ms -1 100V = 5.62A - 10A = - 4.38A × 5ms 10Ω 10Ω e 5ms -1 The minimum practical current is zero, so clearly discontinuous current periods exist in the load current. The equations applicable to discontinuous load current need to be employed. The current extinction time is given by equation (14.24), that is −t  V −E  τ t x = tT + τ An 1 + s 1 − e   E    ∨

I=

T

-1.25ms  340V - 100V   ×  1 - e 5ms   = 1.25ms + 5ms × An  1 + 100V    = 1.25ms + 2.13ms = 3.38ms

i. From equations (14.28) and (14.29) the load average and rms voltages are T − tx Vo = δ Vs + E T 5ms - 3.38ms = ¼×340 V + × 100V = 117.4V 5ms T − tx 2 Vrms = δ Vs2 + E T = ¼ × 3402 +

5ms - 3.38ms × 1002 = 179.3V rms 5ms

ii. From equations (14.30) and (14.31) the rms ripple voltage, hence voltage ripple factor, are 2 Vr = Vrms − Vo2 = 179.32 - 117.42 = 135.5V ac 135.5V = = 1.15 RF = FF = RF 2 + 1 = 1.152 +1 = 1.52 117.4V Vo Vr

Power Electronics

629

Chapter 14

iii. From equation (14.38), the maximum and minimum output current, hence the peak-to-peak output ripple in the current, are −t ∧ V −E  I= s 1− e τ  R   T

=

-1.25ms 340V-100V   ×  1 - e 5ms  = 5.31A 10Ω  

The minimum current is zero so the peak-to-peak ripple current is ∆io = 5.31A. iv. From equations (14.34) and (14.35), the current in the time domain is −t V −E  io ( t ) = s 1− e τ  R   =

−t 340V - 100V   ×  1 − e 5ms  10Ω  

−t   = 24 × 1 − e 5ms    −t E io ( t ) = −  1 − e τ R

v. From equations (14.39) to (14.42), the average load current, average switch current, and average diode current are Io =V o − E R = 117.4V - 100V = 1.74A 10Ω  tx  E  −δ  τ ∧ T  Idiode = I −  T R  3.38ms  100V ×  - 0.25  5ms  5ms  = 1.05A ×5.31A = 5ms 10Ω Ii = Io − Idiode =1.74A - 1.05A = 0.69A

Pin = Pout = Io2rms R + E I o

 ∧ −τt + I e 

Rearranging gives Io

−t −t 100V   =− × 1 − e 5ms  + 5.31e 5ms 10Ω  

= 15.31× e

−t 5ms

− 10

vo

for 0 ≤ t ≤ 2.13ms

(A)

C o n d u c tin g d e v ic e T D

η=

T

V s= 3 4 0 V 117.4V

Vo

=100V E E=100V

1.74A

iD

5 .3 1 A

ID

I

• • • • •

1.05A

iT

5 .3 1 A

0.69A

T

V s= 3 4 0 V 240V

1 .2 5

3 .3 7

5

tim e

6 .2 5

(m s )

No source impedance; Constant switch duty cycle; Steady-state conditions have been reached; Ideal semiconductors; and No load impedance temperature effects.

14.3.1 Continuous load inductor current

vT

0

Second-Quadrant dc chopper

The second-quadrant dc-to-dc chopper shown in figure 14.2b transfers energy from the load, back to the dc energy source Vs, a process called regeneration. Its operating principles are the same as those for the boost switch mode power supply analysed in chapter 15.4. The two energy transfer stages are shown in figure 14.10. Controlled energy transfer from the back emf E to the supply Vs, is achieved by varying the switch T2 on-state duty cycle. Two modes of transfer can occur, as with the first-quadrant chopper already considered. The current in the load inductor can be either continuous or discontinuous, depending on the specific circuit parameters and operating conditions. In this analysis, and all the choppers analysed, it is assumed that:

5 .3 1 A

Io

E Io E I o 100V×1.74A = = = 74.2% Pin 340V×0.69A Vs I i

viii. The circuit, load, and output voltage and current waveforms are plotted in figure 14.9. ♣ 14.3

io

= Pin − E I o / R

vii. From equations (14.44) and (14.45), the effective input impedance and electromagnetic efficiency, for E > 0 are V 340V Z in = s = = 493Ω I i 0.69A

for 3.38ms ≤ t ≤ 5ms

D

rms

= 234.6W - 100V×0.69A / 10Ω = 1.29A

io ( t ) = 0

T

630

vi. From equation (14.40), the input power, hence output power and rms output current are Pin = Vs I i = 340V×0.69A = 234.6W

for 0 ≤ t ≤ 1.25ms

(A)

DC Choppers

8 .3 7

t

Figure 14.9. Example 14.3. Chopper circuit waveforms.

10

1 1 .2 5

Load waveforms for continuous load current conduction are shown in figure 14.11a. The output voltage vo, load voltage, or switch voltage, is defined by for 0 ≤ t ≤ tT  0 vo ( t ) =   for tT ≤ t ≤ T  Vs

(14.46)

Power Electronics

631

Chapter 14

DC Choppers

Vo

−δ T

II

I p− p = Io

Vs io

R

ioff

D2

L

R

E

−T

Vs (1 − e τ ) (1 + e τ ) −T R 1− e τ

(14.54)

This is the same expression derived in 14.2.1 for the first-quadrant chopper. The normalised ripple current design curves in figure 14.3 are valid for the second-quadrant chopper.

io +

ion

632

L

vo

Conducting devices

+ E

T2

T2

D2

io

T2

D2

∧

T2

D2 ∧

∧

I

I

I

T2

D2

T2

io ∧

∧

I (a)

Io

(b)

I

1 T 1 T vo ( t ) dt = ∫ Vs dt T ∫0 T t T − tT Vs = (1 − δ ) Vs = T where the switch on-state duty cycle δ = tT /T is defined in figure 14.11a. T

Vs Vo

Vo

(14.47)

E

tT

T (a)

E t

t tT

Alternatively the voltage across the dc source Vs is 1 Vs = Vo (14.48) 1− δ Since 0 ≤ δ ≤ 1, the step-up voltage ratio, to regenerate into Vs, is continuously adjustable from unity to infinity. The average output current is E − V o E − Vs (1 − δ ) (14.49) Io = = R R The average output current can also be found by integration of the time domain output current io. By solving the appropriate time domain differential equations, the continuous load current io shown in figure 14.11a is defined by

t tx

vo

Vs

Vo =

Io

t

vo

The mean load voltage is

I

∨

∨

I

Figure 14.10. Stages of operation for the second-quadrant chopper: (a) switch-on, boosting current and (b) switch-off, energy into Vs.

D2

T (b)

Figure 14.11. Second-quadrant chopper output modes of current operation: (a) continuous inductor current and (b) discontinuous inductor current.

The average switch current, Iswitch , can be derived by integrating the switch current given by equation (14.50), that is 1 t Iswitch = ∫ io ( t ) dt T 0 −t 1 t E  ∨ −t  (14.55) = ∫   1 − e τ  + I e τ  dt T 0 R   T

T

During the switch on-period, when vo = 0 di L o + R io = E dt which yields −t E  ∨ −t io ( t ) =  1 − e τ  + I e τ for 0 ≤ t ≤ tT R  During the switch off-period, when vo = Vs di L o + R io + Vs = E dt which, after shifting the zero time reference to tT, gives −t E − Vs   ∧ −t io ( t ) = 1− e τ  + I e τ for 0 ≤ t ≤ T − tT  R   − tT

∧

where I =

(14.50)

(14.51)

(A)

(14.52)

− T + tT

E Vs 1 − e τ (A) − −T R R 1− e τ The output ripple current, for continuous conduction, is independent of the back emf E and is given by and

∨

I=

−T

− tT

− T + tT

Vs (1 + e τ ) − ( e τ + e τ ) −T R 1− e τ which in terms of the on-state duty cycle, δ = tT / T, becomes ∧

∨

I p− p = I − I =

δE

(14.53)

E − Vs (1 − δ )

τ ∧ ∨ +  I − I  (14.56) R T  τ ∧ ∨ (V − E )(1 − δ ) =  I − I  − s T R  The average diode current can also be found by integrating the diode current given in equation (14.51), as follows −t 1 T −t  E − Vs   ∧ −t  Idiode = 1 − e τ  + I e τ  dt   0 T   R   (14.57) τ  ∧ ∨  (Vs − E )(1 − δ ) = I− I − T R  =

−T

E Vs e τ − e τ − −T R R 1− e τ

τ ∧ ∨ −  I − I  R T  ∨ The term I − I = I p − p is the peak-to-peak ripple current, which is given by equation (14.53). By Kirchhoff’s current law, the average diode current Idiode is the difference between the average output current Io and the average switch current, I switch , that is Idiode = Io − I switch =

∧

R

∫

−

δE

T

The power produced (provide) by the back emf source E is  E − Vs (1 − δ )  PE = E Io = E   R  

(14.58)

Power Electronics

633

The power delivered to the dc source Vs is τ ∧ ∨ (V − E )(1 − δ )  PVs = Vs I diode = Vs   I − I  − s  R  T   The difference between the two powers is the power lost in the load resistor, R, that is 2 PE = PVs + I o R

Chapter 14

(14.59)

rms

E Io − Vs I diode R The efficiency of energy transfer between the back emf E and the dc source Vs is P V I diode η= V = s PE E Io Io =

(14.60)

rms

s

(14.61)

14.3.2 Discontinuous load inductor current

DC Choppers

During the switch on-period, when vo = 0 di L o + R io = E dt which yields −t E  for 0 ≤ t ≤ tT io ( t ) = 1 − e τ  R  During the switch off-period, when vo = Vs di L o + R io + Vs = E dt which, after shifting the zero time reference to tT, gives −t E − Vs   ∧ −t io ( t ) = for 0 ≤ t ≤ t x − tT 1− e τ  + I e τ R   ∧

With low duty cycles, δ, low inductance, L, or a relatively high dc source voltage, Vs, the minimum output current may reach zero at tx, before the period T is complete (tx < T), as shown in figure 14.11b. Equation (14.52) gives a boundary identity that must be satisfied for zero current, T −tT

∨

I=

E Vs 1 − e τ − −T R R 1− e τ

= 0

(14.62)

That is − T + tT

E 1− e τ = (14.63) −T Vs 1− e τ ∨ Alternatively, the time domain equations (14.50) and (14.51) can be used, such that I = 0. An expression for the extinction time tx can be found by substituting t = tT into equation (14.50). The resulting ∧ expression for I is then substituted into equation (14.51) which is set to zero. Isolating the time variable, which becomes tx, yields −t E  I =  1 − e τ  R  T

−t −t E − Vs   E  −t 0= 1 − e τ  + 1 − e τ  e τ R   R  x

T

x

where I =

T

x

x

)

t x − tT T − tx t   t  Vs + E =  x − δ Vs +  1 − x  E T T T   T (14.66) tx Vo = E − δ Vs + (Vs − E ) T where the switch on-state duty cycle δ = tT /T is defined in figure 14.11b. The average output current is tx E − V o δ Vs − T (Vs − E ) Io = = (14.67) R R The average output current can also be found by integration of the time domain output current io. By solving the appropriate time domain differential equations, the continuous load current io shown in figure 14.11a is defined by =

(A)

(14.68)

(14.69)

(14.70)

∨

(14.71)

The output ripple current, for discontinuous conduction, is dependent of the back emf E and is given by equation (14.70), −t ∧ E  (14.72) I p− p = I = 1 − e τ  R  T

The average switch current, Iswitch , can be derived by integrating the switch current given by equation (14.68), that is 1 t Iswitch = ∫ io ( t ) dt T 0 −t 1 t E  (14.73) = ∫   1 − e τ   dt T 0 R  T

T

δE

=

−t  E   τ t x = tT + τ An  1 + (14.64) 1 − e     Vs − E  This equation shows that t x ≥ tT . Load waveforms for discontinuous load current conduction are shown in figure 14.11b. The output voltage vo, load voltage, or switch voltage, is defined by for 0 ≤ t ≤ tT  0   vo ( t ) = Vs for tT ≤ t ≤ t x  (14.65) E  for t ≤ t ≤ T x   The mean load voltage is T 1 T 1 t Vo = ∫ vo ( t ) dt = Vs dt + ∫ E dt t T 0 T ∫t T

  τ 1 − e   

and I = 0 (A) After tx, vo(t) = E and the load current is zero, that is io ( t ) = 0 for t x ≤ t ≤ T

which yields

(

E R

− tT

634

R

−

τ T

∧

I

∧

The term I = I p − p is the peak-to-peak ripple current, which is given by equation (14.72). By Kirchhoff’s current law, the average diode current Idiode is the difference between the average output current Io and the average switch current, I switch , that is Idiode = Io − I switch t δ Vs − x (Vs − E ) δ E τ ∧ T = − + I (14.74) R R T  tx  − δ  (Vs − E ) τ ∧ T  = I−  T R The average diode current can as follows 1 t −t Idiode = ∫ T 0

also be found by integrating the diode current given in equation (14.69),

−t ∧ −t   E − Vs  τ  τ   1 − e  + I e  dt R      tx  V E δ − − ( )  s τ ∧ T  = I−  T R x

T

(14.75)

The power produced by the back emf source E is PE = E Io

(14.76)

The power delivered to the dc source Vs is PVs = Vs I diode

(14.77)

Power Electronics

635

Chapter 14

Alternatively, the difference between the two powers is the power lost in the load resistor, R, that is PE = PVs + I o2 R rms

(14.78)

E Io − Vs I diode R The efficiency of energy transfer between the back emf and the dc source is P V I diode η = Vs = s PE E Io Io =

(14.79)

Example 14.4: Second-quadrant DC chopper – continuous inductor current

A dc-to-dc chopper capable of second-quadrant operation is used in a 200V dc battery electric vehicle. The machine armature has 1 Ω resistance in series with 1mH inductance. i. The machine is used for regenerative braking. At a constant speed downhill, the back emf is 150V, which results in a 10A braking current. What is the switch on-state duty cycle if the machine is delivering continuous output current? What is the minimum chopping frequency for these conditions? ii. At this speed, (that is, E = 150V), determine the minimum duty cycle for continuous inductor current, if the switching frequency is 1kHz. What is the average braking current at the critical duty cycle? What is the regenerating efficiency and the rms machine output current? iii. If the chopping frequency is increased to 5kHz, at the same speed, (that is, E = 150V), what is the critical duty cycle and the corresponding average dc machine current? Solution

The main circuit operating parameters are • Vs = 200V • E = 150V • load time constant τ = L /R = 1mH/1Ω = 1ms Conducting devices

T2

II

D2

T2

D2

T2

D2

io io ∧

I ∨

I =0

Vs = 200V

T2

io

R

L

1Ω

1mH

∨

I =0

t

vo

+150V

Vs

The expression for the average dc machine output current is based on continuous armature inductance current. Therefore the switching period must be shorter than the time tx predicted by equation (14.64) for the current to reach zero, before the next switch on-period. That is, for tx = T and δ = 0.3 −t  E   τ t x = tT + τ An  1 + 1 − e   V E −   s  This simplifies to −0.3T 1ms  150V   1ms 1 = 0.3 + An  1 + 1 − e  T   200V - 150V  e0.7T = 4 − 3e −0.3T Iteratively solving this transcendental equation gives T = 0.4945ms. That is the switching frequency must be greater than fs =1/T = 2.022kHz, else machine output current discontinuities occur, and equation (14.49) is invalid. The switching frequency can be reduced if the on-state duty cycle is increased as in the next part of this example.

ii. The operational boundary condition giving by equation (14.63), using T=1/ fs =1/1kHz = 1ms, yields − T + tT

E 1− e τ = −T Vs 1− e τ

(δ -1)×1ms

150V 1 - e 1ms = -1ms 200V 1 - e 1ms Solving gives δ = 0.357. That is, the on-state duty cycle must be at least 35.7% for continuous machine output current at a switching frequency of 1kHz. For continuous inductor current, the average output current is given by equation (14.49), that is E − Vs (1 − δ ) E − Vo Io = = R R 150V - 200V×(1 - 0.357 ) 150V - Vo = = = 21.4A 1Ω 1Ω Vo =150V - 21.4A×1Ω = 128.6V The average machine output current of 21.4A is split between the switch and the diode (which is in series with Vs). The diode current is given by equation (14.56) Idiode = Io − I switch

τ  ∧ ∨  (Vs − E )(1 − δ ) I− I − T R  The minimum output current is zero while the maximum is given by equation (14.70). − tT -0.357×1ms ∧ E  150V   I = 1 − e τ  = × 1 - e 1ms  = 45.0A R 1Ω    Substituting into the equation for the average diode current gives ( 200V - 150V ) × (1 - 0.357 ) 1ms Idiode = × ( 45.0A - 0A ) = 12.85A 1ms 1Ω The power delivered by the dc machine back emf E is PE = E Io = 150V×21.4A = 3210W while the power delivered to the 200V battery source Vs is PVs = Vs I diode = 200V×12.85A = 2570W =

Io

D2

636

T

rms

vo

DC Choppers

=200V E=150V

Vo

t tT

T

Figure 14.12. Example 14.4. Circuit diagram and waveforms.

The regeneration transfer efficiency is P 2570W = 80.1% η= V = PE 3210W s

i. The relationship between the dc supply Vs and the dc machine back emf E is given by equation (14.49), that is E − V o E − Vs (1 − δ ) Io = = R R 150V - 200V × (1 - δ ) 10A = 1Ω that is

δ = 0.3 ≡ 30% and V o = 140V

The energy generated deficit, 640W (3210W - 2570W)), is lost in the armature resistance, as I2R heat dissipation. The output rms current is P 640W Io = = = 25.3A rms R 1Ω rms

iii. At an increased switching frequency of 5kHz, the duty cycle would be expected to be much lower than the 35.7% as at 1kHz. The operational boundary between continuous and discontinuous armature inductor current is given by equation (14.63), that is

Power Electronics

637

Chapter 14

DC Choppers

638 Vo

− T + tT

II

E 1− e τ = −T Vs 1− e τ

Vs

T1 D2

Q I io

T2 D1

vo

R

which yields δ = 26.9% . The machine average output current is given by equation (14.49) E − V o E − Vs (1 − δ ) Io = = R R 150V − Vo 150V - 200V×(1 - 0.269 ) = = 3.8A = 1Ω 1Ω such that the average output voltage Vo is 146.2V. ♣ 14.4

•

∨

II Io

D2

Vs

on R

L

+

off

E

R T2

vo

D1

D2

T1

D1

T2 D 2

L

+

E

vo

off

on

Conducting devices T1 D2

T2

D2

T2

vo Vs

Vs Vo E

I > 0

tT

T

t

o

tT

t

T

I < 0

∧

io

I

o

∨

Io

I 0

txD

txT

∨

I

∧

t

I

Io

t

∨

I 0, I > 0 and I o > 0 When the minimum current (hence average output current) is greater than zero, the chopper is active in the first-quadrant. Typical output voltage and current waveforms are shown in figure 14.3a. The switch T2 and diode D2 do not conduct during any portion of the operating period. ∨ ∧ ii. I < 0, I > 0 and I o > 0 When the minimum current is negative but the maximum positive current is larger in absolute magnitude, then for a highly inductive load, the average output current is greater than zero, and the chopper operates in the first-quadrant. If the load is not highly inductive the boundary is determined by the ∧average output current I o > 0. The various circuit waveforms are shown in figure 14.13b. ∨ iii. I < 0, I > 0 and I o < 0 For a highly inductive load, if the magnitude of the negative peak is greater than the positive maximum, the average is less than zero and the chopper is operating in the regenerative mode, quadrant II. If the load is not highly inductive the boundary is determined by the average output current I < 0. ∨ ∧o iv. I < 0, I < 0 and I o < 0 When the maximum current and the average current are both negative, the chopper is operational in the second-quadrant. Since the load current never goes positive, switch T1 and diode D1 never conduct, as shown in figure 14.13c.

Io

T1

Vs

The two independent choppers can be readily combined as shown in figure 14.13a. The average output voltage Vo and the instantaneous output voltage vo are never negative, whilst the average source current of Vs can be positive (Quadrant I) or negative (Quadrant II). If the two choppers are controlled to operate independently, with the constraint that T1 and T2 do not conduct simultaneously, then the analysis in sections 14.2 and 14.3 are valid. Alternately, it is not uncommon the unify the operation of the two choppers, as follows.

i.

Vo I

Devices T1 and D1 form the first-quadrant chopper shown in figure 14.2a, and is analysed in section 14.2. Energy is delivered from the dc source Vs to the R-L-E load. Devices T2 and D2 form the second-quadrant chopper shown in figure 14.2b, which is analysed in section 14.3. Energy is delivered from the generating load dc source E, to the dc source Vs.

The analysis for continuous inductor current in section 14.2 is valid, but the minimum current is not restricted to zero. Consequently four possible output modes can occur, depending on the relative polarity of the maximum and minimum currents shown in figure 14.13b and c.

E

Vo

Two-quadrant dc chopper - Q I and Q II

If the chopper is operated such that the switches T1 and T2 act in a complementary manner, that is either T1 or T2 is on, then some of the independent flexibility offered by each chopper is lost. Essentially the consequence of complementary switch operation is that no extended zero current periods exist in the output, as shown in figures 14.13a and b. Thus the equations describing the features of the firstquadrant chopper in section 14.2.1, for continuous load current, are applicable to this chopper, with slight modification to account for the fact that both the minimum and maximum currents can be negative.

+

L

(a)

Figure 14.13 shows the basic two-quadrant dc chopper, which is a reproduction of the circuit in figure 14.2c. Depending on the load and operating conditions, the chopper can seamlessly change between and act in two modes •

Io Q II io

( -1+δ )×0.2ms

150V 1 - e 1ms = -0.2ms 200V 1 - e 1ms

I

Is

o ∨

I

(b)

Is

∧

I

t

∨

I

(c)

Figure 14.13. Two-quadrant (I and II) dc chopper circuit where vo > 0: (a) basic two-quadrant dc chopper; (b) operation and waveforms for quadrant I; and (c) operation and waveforms for quadrant II, regeneration into Vs.

In all cases the average output voltage is solely determined by the switch T1 on-time duty cycle, since when this switch is turned on the supply Vs is impressed across the load, independent of the direction of the load current. When io > 0, switch T1 conducts while if io < 0, the diode in parallel to switch T1, namely D1 conducts, clamping the load to Vs. The output voltage, which is independent of the load, is described by for 0 ≤ t ≤ tT  Vs vo ( t ) =   for tT ≤ t ≤ T  0

(14.80)

Power Electronics

639

Chapter 14

DC Choppers

Thus 1 tT t Vs dt = T Vs = δ Vs T ∫0 T The rms output voltage is also determined solely by the duty cycle, Vo =

1 Vrms =  T

tT

∫

0

 Vs2 dt  

∨  I R  t xT = τ An  1 − with respect to t = 0  Vs − E      IR t xD = τ An  1 + with respect to t = tT   E  

(14.81)

½

(14.82)

= δ Vs The output ac ripple voltage, hence voltage ripple factor are given by equations (14.3) and (14.5), and are independent of the load: 2 Vr = Vrms − Vo2 = Vs δ (1 − δ )

(14.83)

640

(14.91)

The necessary integration for each device can then be determined with the aid of the device conduction information in the parts of figure 14.13 and Table 14.1. Table 14.1: Device average current ratings

and RF =

Vr

1

=

−1 =

δ

1− δ

FF = 1

δ

δ

(14.84)

Device and integration bounds, a to b

Vo The Fourier series for the load voltage can be used to determine the load current at each harmonic frequency as described by equations (14.6) to (14.10). The time domain differential equations from section 14.2.1 are also valid, where there is no zero restriction on the minimum load current value.

In a positive voltage loop, when vo(t) = Vs and Vs is impressed across the load, the load circuit condition is described by −t V −E  ∨ −t 1− e τ  + I e τ for 0 ≤ t ≤ tT (14.85) io ( t ) = s R   During the switch off-period, when vo = 0, forming a zero voltage loop −t E  ∧ −t io ( t ) = −  1 − e τ  + I e τ for 0 ≤ t ≤ T − tT (14.86) R  where − tT

∧

where I =

Vs 1 − e τ −T R 1− e τ

−

tT

∨

and I =

Vs e − 1 − T R τ e −1 τ

E R E R

1 T

Vo − E

T

0

(δ V =

o

)

R

− E)

(14.88)

(14.89)

(A) R The direction of the net power flow between E and Vs determines the chopper operating quadrant. If Vo > E then average power flow is to the load, as shown in figure 14.13b, while if Vo < E, the average power flow is back into the source Vs, as shown in figure 14.13c. Vs I s = ± I o2 R + E I o (14.90) s

∫

b a b

0

∨

∧

∨

I < 0, I < 0

−t Vs − E   ∨ −t 1 − e τ  + I e τ dt R  

0 to tT

t xT to tT

0 to 0

Vs − E   1 − e τ  + I e τ dt R  

0 to 0

0 to t xT

0 to tT

0 to 0

t xD to T - tT

0 to T - tT

0 to T - tT

0 to t xD

0 to 0

−t

IT 2 =

1 T

∫

a

ID2 =

1 T

∫

0

b

b

∨

−t

−

−t E 1− e τ R 

 ∧ −τt  + I e dt 

−

−t E  ∧ −t 1 − e τ  + I e τ dt R  

Vs I i E Io

(14.92)

for I o < 0

Example 14.5: Two-quadrant DC chopper with load back emf

−(1−δ )T

( ∫ i ( t ) dt =

1 T

∫

∧

I > 0, I < 0

η=

(A)

Vs (1 − e τ ) (1 − e τ ) −T R 1− e τ The average output current, I o , may be positive or negative and is given by

1 T

∨

The electromagnetic energy transfer efficiency is determined from EI η = o for I o > 0 Vs I i

(14.87)

I p− p =

Io =

I D1 =

(A)

The peak-to-peak ripple current is independent of E, −δ T

IT 1 =

∧

I > 0, I > 0

The two-quadrant dc-to-dc chopper in figure 14.13a feeds an inductive load of 10 Ω resistance, 50mH inductance, and back emf of 100V dc, from a 340V dc source. If the chopper is operated at 200Hz with a 25% on-state duty cycle, determine: i. the load average and rms voltages; ii. the rms ripple voltage, hence ripple and form factors; iii. the maximum and minimum output current, hence peak-to-peak output ripple in the current; iv. the current in the time domain; v. the current crossover times, if applicable; vi. the load average current, average switch current and average diode current for all devices; vii. the input power, hence output power and rms output current; viii. effective input impedance and electromagnetic efficiency; and ix. sketch the circuit, load, and output voltage and current waveforms. Subsequently determine the necessary change in x. duty cycle δ to result in zero average output current and xi. back emf E to result in zero average load current. Solution

rms

Thus the sign of I o determines the direction of net power flow, hence quadrant of operation. Calculation of individual device average currents in the time domain is complicated by the fact that the energy may flow between the dc source Vs and the load via the switch T1 (energy to the load) or diode D2 (energy from the load). It is therefore necessary to ascertain the zero current crossover time, ∧ ∨ when I and I have opposite signs, which will then specify the necessary bounds of integration. Equations (14.85) and (14.86) are equated to zero and solved for the time at zero crossover, txT and txD, respectively, shown in figure 14.13b.

The main circuit and operating parameters are • on-state duty cycle δ = ¼ • period T = 1/fs = 1/200Hz = 5ms • on-period of the switch tT = 1.25ms • load time constant τ = L /R = 0.05mH/10Ω = 5ms i. From equations (14.81) and (14.82) the load average and rms voltages are t 1.25ms vo = T Vs = ×340V = ¼ ×340V = 85V T 5ms Vrms = δ Vs = ¼ ×340V = 170V rms

Power Electronics

641

Chapter 14

DC Choppers

642

During the switch on-time -t

io ( t ) = 24 - 28.38 × e 5ms = 0

vo δ=¼ T=5ms

II

T1 D2

I

+E

R

L

10Ω

50mH

io

Vs=340V

−t

δ=¾ T=5ms

io ( t ) = −10 + 11.90 × e 5ms = 0

+100V

Figure 14.14. Example 14.5. Circuit diagram.

ii. The rms ripple voltage, hence voltage ripple factor, from equations (14.83) and (14.84) are 2 Vr = Vrms − Vo2 = Vs δ (1 − δ )

= 1702 - 852 = 340V ¼ × (1 - ¼ ) = 147.2V RF =

Vr Vo

=

1

δ

− 1=

1 - 1 = 1.732 ¼

FF = 1

δ

= 1

¼

=2

vi. The load average current, average switch current, and average diode current for all devices; Vo − E (δ Vs − E ) = Io = R R (85V - 100V ) = -1.5A 10Ω

(

∧

I=

Vs 1 − e τ −T R 1− e τ

−

-1.25ms 5ms

E 340V 1 - e = × -5ms R 10Ω 1 - e 5ms

tT

-

T

xT

I D1

100V = 1.90A 10Ω

I=

 = 24×  1- e 

-t 5 ms

  - 4.38×e  -t

= 24 - 28.38 × e 5ms

-t 5ms

for 0 ≤ t ≤ 1.25ms

−t E  ∧ −t 1− e τ  + I e τ R   −t −t 100V   =− × 1 − e 5ms  + 1.90 × e 5ms 10Ω  

=

ID2 =

= −10 + 11.90 × e

−t 5ms

for 0 ≤ t ≤ 3.75ms

v. Since the maximum current is greater than zero (1.9A) and the minimum is less that zero (- 4.38A), the current crosses zero during the switch on-time and off-time. The time domain equations for the load current are solved for zero to give the cross over times txT and txD, as given by equation (14.91), or solved from the time domain output current equations as follows.

1 T

∫

∫

T -tT t xD

0.84ms 0

−

1 5ms

∫

1 T

−

∫

t xD

0

-t

24 - 28.38 × e 5ms dt = − 0.357A

−t E 1− e τ  R

3.75ms 0870ms

 ∧ −τ t  + I e dt  −t

−10 + 11.90 × e 5ms dt = −1.382A

−t E 1− e τ R 

 ∧ −τt  + I e dt 

−t 0.870 ms 1 −10 + 11.90 × e 5ms dt = 0.160A 5ms 0 Check I o + I T 1 + I D1 + I T 2 + I D 2 = - 1.5A + 0.080A - 0.357A - 1.382A + 0.160A = 0

∫

=

vii. The input power, hence output power and rms output current;

(

Pin = PVs = Vs I i = Vs I T 1 + I D1

io ( t ) = −

−t −t   = −10 ×  1 − e 5ms  + 1.90 × e 5ms  

∫

IT 2 =

iv. The current in the time domain is given by equations (14.85) and (14.86) −t V −E  ∨ −t 1− e τ  + I e τ io ( t ) = s  R   -t -t 340V-100V   = × 1- e 5ms  - 4.38×e 5ms 10Ω  

∫

1 = 5ms

1.25ms 5ms

τ

-t 1.25ms 1 24 - 28.38 × e 5ms dt = 0.081A 5ms 0.838ms −t 1 txT Vs − E   ∨ −t = 1 − e τ  + I e τ dt T 0 R  

=

Vs e − 1 E 340V e -1 100V = × 5ms = - 4.38A − R Tτ R 10Ω 10Ω e −1 e 5ms - 1 The peak-to-peak ripple current is therefore ∆io = 1.90A - - 4.38A = 6.28A p-p. ∨

)

When the output current crosses zero current, the conducting device changes. Table 14.1 gives the ∧ ∨ necessary current equations and integration bounds for the condition I > 0, I < 0 . Table 14.1 shows that all four semiconductors are involved in the output current cycle. −t 1 t Vs − E   ∨ −t IT1 = ∫ 1 − e τ  + I e τ dt T t R  

iii. From equations (14.87) and (14.88), the maximum and minimum output current, hence the peak-topeak output ripple in the load current are given by − tT

where 0 ≤ t = t xD ≤ 3.75ms

11.90 t xD =5ms×An = 0.870ms 10 (1.250ms + 0.870ms = 2.12ms with respect to switch T1 turn - on)

vo

T2 D1

where 0 ≤ t = t xT ≤ 1.25ms

28.38 t xT = 5ms×An = 0.838ms 24 During the switch off-time

)

= 340V× ( 0.080A - 0.357A ) = -95.2W, (charging Vs )

From

Pout = PE = E I o = 100V × ( -1.5A ) = -150W, that is generating 150W

Vs I s = I o2 R + E I o rms

Io = rms

150W - 92.5W Pout − Pin = = 2.34A rms 10Ω R

viii. Since the average output current is negative, energy is being transferred from the back emf E to the dc voltage source Vs, the electromagnetic efficiency of conversion is given by VI η = s i for I o < 0 E Io 95.2W = = 63.5% 150W

Power Electronics

643

Chapter 14

14.5

The effective input impedance is V Vs 340V Z in = s = = = -1214Ω I i I T 1 + I D1 0.080A - 0.357A ix. The circuit, load, and output voltage and current waveforms are sketched in the figure 14.15.

D2

T1

Conducting devices T2 D2

D1

T1

D1

T2

vo 340V

E

DC Choppers

644

Two-quadrant dc chopper - Q 1 and Q IV

The unidirectional current, two-quadrant dc chopper, or asymmetrical half H-bridge shown in figure 14.16a incorporates two switches T1 and T4 and two complementary diodes D1 and D4. In using switches T1 and T4 the chopper operates in the first and fourth quadrants, that is, bi-directional voltage output vo but unidirectional load current, io. The chopper can operate in two quadrants (I and IV), depending on the load and switching sequence. Net power can be delivered to the load, or received from the load provided the polarity of the back emf E is reversed. Because of this need to reverse the back emf for regeneration, this chopper is not commonly used in dc machine control. On the other hand, the chopper circuit configuration is commonly used to meet the converter requirements of the switched reluctance machine, which only requires unipolar current to operate. Also see chapter 17.5 for a bidirectional smps variation. The asymmetrical half H-bridge chopper has three different output voltage states, where one state (the zero output state) has redundancy (two possibilities). Both the output voltage vo and output current io are with reference to the first quadrant arrows in figure 14.16a.

100V

Vo

85V o

Vs

vo

t

D4

T1 io

I

io ∧

1.9A

I

IV

t

LOAD io

+ vo

D1

T4

o

Io

-1.5A

txD

is

(a)

=0.87ms

-4.38A

∨

I

I

1.9A

t

o

Is

-0.28A

2.12ms ∨

I

txT =0.383ms tT =1.25ms

T1 T4

T1 D4

∧

D1 T4

T1 T4

T1 D4

T1 T4

Conducting devices D1 T1 D1 T4 D4 D4

1 δ

1

½

½

D1 T4

D1 D4

T1 D4

D1 D4

D1 T4

δ

-4.38A T =5ms

o

o T1

T1 on

T1 off

T1 on

T4 on

T4 off

T1

T1 off

T1 on

T4 on

T4 off

T1 off

Figure 14.15. Example 14.5. Circuit waveforms. T4

x. Duty cycle δ to result in zero average output current can be determined from the expression for the average output current, equation (14.89), that is δ Vs − E =0 Io = R that is E 100V δ= = = 29.4% Vs 340V xi. As in part x, the average load current equation can be rearranged to give the back emf E that results in zero average load current δ Vs − E =0 Io = R that is E = δ Vs = ¼×340V = 85V ♣

T4 on

+Vs

vo

T4

T4 off

o

vo

T

tT

2T

Vo

o

tT

T

Vo

-Vs

2T

∧

I

io

io

Io ∨

Io

I

∧

is

I

∨

I

(c)

-is

−Is

Is

(b)

Figure 14.16. Two-quadrant (I and IV) dc chopper (a) circuit where io>0: (b) operation in quadrant IV, regeneration into Vs; and (c) operation in quadrant I.

Power Electronics

645

Chapter 14

State #1 When both switches T1 and T4 conduct, the supply Vs is impressed across the load, as shown in figure 14.17a. Energy is drawn from the dc source Vs. T1 and T4 conducting: vo = Vs State #2 If only one switch is conducting, and therefore also one diode, the output voltage is zero, as shown in figure 14.17b. Either switch (but only one on at any time) can be the on-switch, hence providing redundancy, that is vo = 0 T1 and D4 conducting: vo = 0 T4 and D1 conducting: State #3 When both switches are off, the diodes D1 and D4 conduct load energy back into the dc source Vs, as in figure 14.17c. The output voltage is -Vs, that is vo = -Vs T1 and T4 are not conducting:

0V

Vs

D3 D 4

+Vs

T1

Vs

LOAD +

Vs

(a)

D4

Vs

-Vs

T1

LOAD

-

D D12

(b)

0V

D D34

LOAD

-

T4 T 3

D D12

D3

T1

TT34

D D21

Vs

•

DC Choppers

Bipolar switching (or two level switching) is when both switches operate in unison, where they turn on together and off together. Only two voltage output states (hence the term bipolar), are possible, +Vs and – Vs.

14.5.1 dc chopper:– Q I and Q IV – multilevel output voltage switching (three level)

The interleaved zero voltage states are readily introduced if the control carrier waveforms for the two switches are displaced by 180°, as shown in figure 14.16b and c, for continuous load current. This requirement can be realised if two up-down counters are displaced by 180°, when generating the necessary triangular carriers. As shown in figures 14.16b and c, the switching frequency 1/Ts is determined by the triangular wave frequency 1/2T, whilst advantageously the load experiences twice that frequency, 1/T, hence the output current has reduced ripple, for a given switch operating frequency. i. 0 ≤ δ ≤ ½ It can be seen in figure 14.16b that when δ ≤ ½ both switches never conduct simultaneously hence the output voltage is either 0 or -Vs. Operation is in the fourth quadrant. The average output voltage is load independent and for 0 ≤ δ ≤ ½, using the waveforms in figure 14.16b, is given by − Vs t 1 T Vo = ∫ − Vs dt = (14.93) (T − tT ) = − Vs 1 − T  T t T  T Examination of figure 14.16b reveals that the relationship between tT and δ must produce when δ = 0 : tT = T and vo = −Vs T

when δ = ½ :

+

646

tT = 0 and vo = 0

that is T34 T

(c)

Figure 14.17. Two-quadrant (I and IV) dc chopper operational current paths: (a) T1 and T4 forming a +Vs path; (b) T1 and D4 (or T4 and D1) forming a zero voltage loop; and (c) D1 and D4 creating a -Vs path.

The two zero output voltage states can most effectively be used if alternated during any switching sequence. In this way, the load switching frequency (load ripple current frequency) is twice the switching frequency of the switches. This reduces the output current ripple for a given switch operating frequency (which minimises the load inductance necessary for continuous load current conduction). Also, by alternating the zero voltage loop, the semiconductor losses are evenly distributed. Specifically, a typical sequence to achieve these features would be Vs T1 and T4 0 T1 and D4 Vs T1 and T4 0 (not T1 and D4 again) T4 and D1 Vs T1 and T4 0, etc. T1 and D4 The sequence can also be interleaved in the regeneration mode, when only one switch is on at any instant, as follows -Vs (that is T1 and T4 off) D1 and D4 0 T1 and D4 D1 and D4 -Vs 0 (not T1 and D4 again) T4 and D1 -Vs D1 and D4 T1 and D4 0, etc. In switched reluctance motor drive application there may be no alternative to using only ±Vs control loops without the intermediate zero voltage state. There are two basic modes of chopper switching operation. • Multilevel switching is when both switches are controlled independently to give all three output voltage states (three levels), namely ±Vs and 0V.

tT T (the period of the carrier, 2T, is twice the switching period, T) which after substituting for tT /T in equation (14.93) gives  t  Vo = − Vs  1 − T  (14.94)  T = − Vs (1 − 2δ ) = Vs ( 2δ − 1) for 0 ≤ δ ≤ ½

δ =½

Operational analysis in the fourth quadrant, δ ≤ ½, is similar to the analysis for the second-quadrant chopper in figure 14.2b and analysed in section 14.3. Operation is characterised by first shorting the output circuit to boost the current, then removing the output short forces current back into the dc supply Vs, via a freewheel diode. The characteristics of this mode of operation are described by the equations (14.50) to (14.79) for the second-quadrant chopper analysed in 14.3, where the output current may again be continuous or discontinuous. The current and voltage references are both reversed in translating equations applicable in quadrants Q II to Q IV. ii. ½ ≤ δ ≤ 1 As shown in figure 14.16c, when δ ≥ ½ and operation is in the first quadrant, at least one switch is conducting hence the output voltage is either +Vs or 0. For continuous load current, the average output voltage is load independent and for ½ ≤ δ ≤ 1 is given by 1 t V (14.95) Vo = ∫ Vs dt = s tT T 0 T Examination of figure 14.16c reveals that the relationship between tT and δ must produce when δ = ½ : tT = 0 and vo = 0 T

when δ = 1:

tT = T and vo = Vs

that is  tT  + 1 T  which on substituting for tT /T in equation (14.95) gives t Vo = Vs T = Vs ( 2δ − 1) for ½ ≤ δ ≤ 1 (14.96) T Since the average output voltage is the same in each case, equations (14.94) and (14.96) for (0 ≤ δ ≤ 1), the output current mean is given by the same expression, namely V o − E Vs (2δ − 1) − E (14.97) Io = = R R

δ = ½

Power Electronics

647

Chapter 14

Operation in the first quadrant, δ ≥ ½, is characterised by the first-quadrant chopper shown in figure 14.2a and considered in section 14.2 along with the equations within that section. The load current can be either continuous, in which case equations (14.6) to (14.23) are valid; or discontinuous in which case equations (14.24) to (14.45) are applicable. Aspects of this mode of switching are extended in 14.5.3. In applying the equations for the chopper in section 14.2 for the first-quadrant chopper, and the equations in section 14.3 for the second-quadrant chopper, the duty cycle in each case is replaced by • 2δ -1 in the case of δ ≥ ½ for the first-quadrant chopper and • 2δ in the case of δ ≤ ½ for the fourth-quadrant chopper. This will account for the scaling and offset produced by the triangular carrier signal decoding. 14.5.2 dc chopper: – Q I and Q IV – bipolar voltage switching (two level)

When both switches operate in the same state, that is, both switches are on simultaneously or both are off together, operation is termed bipolar or two level switching. From figure 14.18 the chopper output states are (assuming continuous load current) • T1 and T4 on vo = Vs • T1 and T4 off vo = - Vs From figure 14.18, the average output voltage is T 1 t Vo = Vs dt + ∫ −Vs dt t T ∫0 (14.98) V = s ( tT − T + tT ) = ( 2δ − 1)Vs T The rms output voltage is independent of the duty cycle and is Vs. The output ac ripple voltage is

(

T

T

)

2 Vr = Vrms − Vo2

(14.99)

= Vs2 − ( 2δ − 1) Vs2 = 2 Vs δ (1 − δ ) 2

which is a maxima at δ = ½ and a minima for δ = 0 and δ = 1.

Vs

T1

D4

LOAD D1

L

+ E T4

vo

(a) Conducting devices

T1 T4

D1 D4

T1 T4

io

D1 D4

T1 T4

D1 D4

∧

I Io ∨

∨

I

I

t

o T

vo Vs

Vo o

-Vs

t

tT

648

The output voltage ripple factor is RF =

Vr 2Vs δ (1 − δ ) 2 δ (1 − δ ) = = Vo ( 2δ − 1)Vs ( 2δ − 1)

(14.100)

Although the average output voltage may reverse, the load current is always positive but can be discontinuous or continuous. Equations describing bipolar output are presented within the next section, 14.5.3, which considers multilevel (two and three level) output voltage switching states. 14.5.3 Multilevel output voltage states, dc chopper

In switched reluctance machine drives it is not uncommon to operate the asymmetrical half H-bridge shown in figure 14.18 such that • both switches operate in the on-state together to form +V voltage loops; • switches operate independently to give zero voltage loops; and • both switches are simultaneously off, forming –V voltage output loops. The control objective is to generate a current output pulse that tracks a reference shape which starts from zero, rises to maintain a fixed current level, with hysteresis, then the current falls back to zero. The waveform shown in figure 14.19 fulfils this specification. The switching strategy to produce the current waveform in figure 14.19 aims at: • For rising current:- use +V loops (and zero volt loops only if necessary) • For near constant current:- use zero voltage loops (and ±V loops only if necessary to increase or decrease the current) • For falling current:- use – V loops (and zero volts loops only if necessary to reduce the fall rate) Operation is further characterised by continuous load current during the pulse. Energy is supplied to the load from the dc voltage source during +V loops, and returned to the dc supply during –V loop periods. The chopper output current during each period is described by equations previously derived in this chapter, but reproduced as follows.

io

R

DC Choppers

(b)

Figure 14.18. Two-quadrant (I and IV) dc chopper operation in the bipolar output mode: (a) circuit showing load components and (b) chopper output waveforms.

In a positive voltage loop, (T1 and T4 are both on), when vo(t) = Vs and Vs is impressed across the load, the load circuit condition is described by di L o + R io + E = Vs dt which yields −t V −E  ∨ −t (14.101) 1− e τ  + I e τ for 0 ≤ t ≤ t + io ( t ) = s R   ∨ ∨ During the first switching cycle the current starts from zero, so I = 0. Otherwise I is the lower − reference, I , from the end of the previous cycle. The current at the end of the positive voltage loop period is the reference level I+, whilst the time to rise to I+ is derived by equating equation (14.101) to I+ and solving for time t+ at the end of the period. Solving io(t+) = I+ for t+ , gives  V − E − I∨ R   t + = τ ln  s (14.102)  Vs − E − I + R    In a zero voltage loop, when vo(t) = 0, such as circuit loops involving T1 and D4 (or T4 and D1), the circuit equation is given by di L o + R io + E = 0 dt which gives −t E  ∧ −t (14.103) io ( t ) = −  1 − e τ  + I e τ for 0 ≤ t ≤ t o R  ∧ + where I equals the reference current level, I from the previous switching period. − − The current at the end of the period is the reference level I , whilst the time to fall to I is given by − equating equation (14.103) to I and solving for time, to at the end of the period.  E + I∧ R   (14.104) t o = τ An   E + I−R   

Power Electronics

649

T1 D4

T1 T4

T1 T4

Chapter 14

Conducting devices D1 T1 T1 T4 T4 D4

T1 T4

I+

I o

-

I t

o

t

+

t

o

t

+

t

o

t

+

o

I o

o

t

∨

Io

is

650

How do the on-state losses compare between the two control approaches?

D1 D4

io

DC Choppers

Solution

The main circuit and operating parameters are • E = 55V and Vs = 340V • load time constant τ = L /R = 0.05mH/10Ω = 5ms − • I+ = 10A and I = 5A Examination of the figure 14.20 shows that only one period of the cycle differs, namely the second period, t2, where the current is required to fall to the lower hysteresis band level, -5A. The period of the other three regions (t1, t3, and t4) are common and independent of the period of the second region, t2. ∨

o

o

t

energy recovered − I o

Vs vo o

o

t

-Vs

Figure 14.19. Two-quadrant (I and IV) dc chopper operation in a multilevel output voltage mode.

In a negative voltage loop, when both switches T1 and T4 are off, the current falls rapidly and the circuit equation, when vo(t) = -Vs, is di L o + R io + E = −Vs dt which gives −t − E − Vs   ∧ −t 1− e τ  + I e τ for 0 ≤ t ≤ t − (14.105) io ( t ) =  R   ∧ + where I equals the reference current level, I from the previous switching period. − − The current at the end of the period is I , whilst the time to reach I is given by equating equation − (14.103) to I and solving for time t − at the end of the period.  V + E + I∧ R   (14.106) t − = τ An  s  Vs + E + I − R    The same equation is used to determine the time for the final current period when the current decays to − zero, whence I = 0. The characteristics and features of the three output voltage states are illustrated in the following example, 14.6. Example 14.6: Asymmetrical, half H-bridge, dc chopper

The asymmetrical half H-bridge, dc-to-dc chopper in figure 14.18 feeds an inductive load of 10 Ω resistance, 50mH inductance, and back emf of 55V dc, from a 340V dc voltage source. The chopper output current is controlled in a hysteresis mode within a current band between limits 5A and 10A. Determine the period of the current shape shown in the figure 14.20: i. when only ±Vs loops are used and ii. when a zero volt loop is used to maintain tracking within the 5A band.

In each case calculate the switching frequency if the current were to be maintained within the hysteresis band for a prolonged period.

t1: The first period, the initial rise time, t+ = t1 is given by equation (14.102), where I+=10A and I = 0A.  V − E − I∨ R   t + = τ An  s  Vs − E − I + R     340V - 55V - 0A×10Ω  that is t1 = 5ms × An   = 2.16ms  340V - 55V - 10A×10Ω  t3: In the third period, the current rises from the lower hysteresis band limit of 5A to the upper band limit ∨ − 10A. The duration of the current increase is given by equation (14.102) again, but with I = I = 5A. ∨  V −E−I R   t + = τ An  s  Vs − E − I + R     340V - 55V - 5A×10Ω  that is t3 = 5ms × An   = 1.20ms  340V - 55V - 10A×10Ω  t4: The fourth and final period is a negative voltage loop where the current falls from the upper band ∧ − − limit of 10A to I which equals zero. From equation (14.106) with I =I+=10A and I = 0A ∧  V +E+IR   t − = τ An  s  Vs + E + I − R     340V + 55V + 10A×10Ω  that is t4 = 5ms × An   = 1.13ms  340V + 55V + 0A×10Ω  The current pulse period is given by Tp = t1 + t2 + t3 + t4 = 2.16ms + t2 + 1.20ms + 1.13ms = 4.49ms + t2

When only -Vs paths are used to decrease the current, the time t2 is given by equation (14.106), ∧ − with I =5A and I =10A,  V + E + I∧ R   t − = τ An  s  Vs + E + I − R     340V + 55V + 10A×10Ω  that is t2 = 5ms × An   = 0.53ms  340V + 55V + 5A×10Ω  The total period, Tp, of the chopped current pulse when a 0V loop is not used, is Tp = t1 + t2 + t3 + t4

i. t2:

= 2.16ms + 0.53ms + 1.20ms + 1.13ms = 5.02ms When a zero voltage loop is used to maintain the current within the hysteresis band,∧ the current − decays slowly, and the period time t2 is given by equation (14.104), with I = 5A and I =10A, ∧  E+IR   t o = τ An   E + I −R     55V + 10A×10Ω  that is t2 = 5ms × An   = 1.95ms  55V + 5A×10Ω  The total period, Tp, of the chopped current pulse when a 0V loop is used, is Tp = t1 + t2 + t3 + t4

ii. t2:

= 2.16ms + 1.95ms + 1.20ms + 1.13ms = 6.44ms

651

Power Electronics

Chapter 14

Conducting devices D1 / T1 T1 D1 D4 T4 D4

With the flexibility of four switches, a number of different control methods can be used to produce fourquadrant output voltage and current (bidirectional voltage and current). All practical methods should employ complementary device switching in each leg (either T1 or T4 on but not both and either T2 or T3 on, but not both) so as to minimise distortion by ensuring current continuity around zero current output. One control method involves controlling the H-bridge as two virtually independent two-quadrant choppers, with the over-riding restriction that no two switches in the same leg conduct simultaneously. One chopper is formed with T1 and T4 grouped with D1 and D4, which gives positive current io but bidirectional voltage ±vo (QI and QIV operation). The second chopper is formed by grouping T2 and T3 with D2 and D3, which gives negative output current -io, but bi-direction voltage ±vo (QII and QIII operation).

T1 T4

10A io 5A t2

t1

o

t4

t3

o

t

10A

DC Choppers

652

5A

is

vo 1.13ms

o 2.16ms

o

t

1.2ms

T1

Vs

D2

-V 0.53ms 0V 1.95ms

I

+340V

t3

t4

-V loop

-Vs

D1

E=55V

t2

I

III

IV

io

o

−

vo

T2 0V loop

t1

II

LOAD

-10A

o

T3

io

Vs vo

D4

D3

T4

t

-340V

Figure 14.21. Four-quadrant dc chopper circuit, showing first quadrant io and vo references.

Tp

Figure 14.20. Example 14.6. Circuit waveforms.

The current falls significantly faster within the hysteresis band if negative voltage loops are employed rather that zero voltage loops, 0.53ms versus 1.95ms. The switching frequency within the current bounds has a period t2 + t3, and each case is summarized in the following table. For longer current chopping, t2 and t3 dominate the switching frequency. Using zero voltage current loops (alternated) reduces the switching frequency of the H-bridge switches by a factor of over three, for a given peak-to-peak ripple current. If the on-state voltage drop of the switches and the diodes are similar for the same current level, then the on-state losses are similar, and evenly distributed for both control methods. The on-state losses are similar because each of the three states always involves the same current variation flowing through two semiconductors. The principal difference is in the significant increase in switching losses when only ±V loops are used (1:3.42). Table Example 14.6. Switching losses. Voltage loops

t2 + t3

Current ripple frequency

Switch frequency

±V

0.53ms+1.20ms =1.73ms

578Hz

578Hz

+V and zero

1.95ms+1.20ms = 3.15ms

317Hz

169Hz

Switch loss ratio 578 169

= 3.42 1

♣

14.6

Four-quadrant dc chopper

The four-quadrant H-bridge dc chopper is shown in figure 14.21 where the load current and voltage are referenced with respect to T1, so that the quadrant of operation with respect to the switch number is persevered. The H-bridge is a flexible basic configuration where its use to produce single-phase ac is considered in chapter 15.1.1, while its use in smps applications is considered in chapter 17.8.2. It can also be used as a dc chopper for the four-quadrant control of a dc machine.

The second control method is to unify the operation of all four switches within a generalised control algorithm. With both control methods, the chopper output voltage can be either multilevel or bipolar, depending on whether zero output voltage loops are employed or not. Bipolar output states increase the ripple current magnitude, but do facilitate faster current reversal, without crossover distortion. Operation is independent of the direction of the output current io. Since the output voltage is reversible for each control method, a triangular based modulation control method, as used with the asymmetrical H-bridge dc chopper in figure 14.16, is applicable in each case. Two generalised unified H-bridge control approaches are considered – bipolar and three-level output. 14.6.1 Unified four-quadrant dc chopper - bipolar voltage output switching

The simpler output to generate is bipolar output voltages, which use one reference carrier triangle as shown in figure 14.22 parts (c) and (d). The output voltage switches between + Vs and – Vs and the relative duration of each state depends on the magnitude of the modulation index δ. If δ = 0 then T1 and T4 never turn-on since T2 and T3 conduct continuously which impresses – Vs across the load. At the other extreme, if δ = 1 then T1 and T4 are on continuously and +Vs is impressed across the load. If δ = ½ then T1 and T4 are turned on for half of the period T, while T2 and T3 are on for the remaining half of the period. The output voltage is – Vs for half of the time and + Vs for the remaining half of any period. The average output voltage is therefore zero, but disadvantageously, the output current needlessly ripples about zero (with an average value of zero).

The chopper output voltage is defined in terms of the triangle voltage reference level v∆ by • v∆ > δ, vo = -Vs • v∆ < δ, vo = +Vs From figure 14.22c and d, the average output voltage varies linearly with δ such that T 1 t Vo = +Vs dt + ∫ −Vs dt t T ∫0 1  t  = ( 2tT − T )Vs =  2 T − 1Vs T  T 

(

T

T

)

(14.107)

Power Electronics

653

Chapter 14

Examination of figures 14.22c and d reveals that the relationship between tT and δ must produce when δ = 0 : tT = 0 and vo = −Vs when δ = ½ :

tT = ½T and vo = 0

when δ = 1:

tT = T

and vo = +Vs

that is tT T which on substituting for tT /T in equation (14.107) gives  t  Vo =  2 T − 1 Vs  T  = ( 2δ − 1) Vs for 0 ≤ δ ≤ 1

DC Choppers

D2 D2 T1 T3 D 3 T4

D 1 T2 D 2 T1 T4 D3 D3 T4

T1 D4

D2 D2 T1 T3 D 3 T4

Conducting devices D1 T1 D 1 T2 T4 D 4 D 4 T3

1 δ

1

½

½

o

δ o

δ=

T 1/2

T 1 on

T 2 on

T 1 on

T 4 on

T 3 on

T 3/4

vo

Vr = V

2 rms

−V

(14.109)

The ac ripple voltage is zero at δ = 0 and δ = 1, when the output voltage is pure dc, namely - Vs or Vs, respectively. The maximum ripple voltage occurs at δ = ½, when Vr = Vs. The output voltage ripple factor is Vr 2 Vs δ (1 − δ ) = Vo ( 2δ − 1)Vs 2 δ (1 − δ )

( 2δ − 1)

o

tT

T

T 4 on

T 3 on

T

tT

o

T 2 on

2T

-V s ∧

Io

I

(b)

D 1 T2 D 2 D4 T3 D3

T1 T4

Conducting devices D1 T1 D 1 D4 T4 D 4

1 δ

1

½

½

o

δ o

T 3/4

T 1 on

T 2 on

T 1 on

T 4 on

T 3 on

T 4 on

vo

T 1/2

T 3 on

o

+V s

I

∨

−I

(a)

T 1/2

Io

∨

is

∧

I

tT Vo

T 1 on

T 3/4 T o

vo

4

on

tT

T2 T3

D1 T1 D3 T4

D1 D4

T 2 on

T 1 on

T 2 on

T 3 on

T 4 on

T 3 on

T

+V s

Vo

−T

Vs 1 − 2e τ + e τ −T R 1− e τ tT

T 1 on

−

E R

−T

T2 D3

∨

T1 T4

During the on-period for T1 and T4, when vo(t) = Vs di L o + R io + E = Vs dt which yields −t V −E  ∨ −t io ( t ) = s 1− e τ  + I e τ for 0 ≤ t ≤ tT (14.111) R   During the on-period for T2 and T3, when vo(t) = - Vs di L o + R io + E = − Vs dt which, after shifting the zero time reference to tT, gives −t V +E  ∧ −t io ( t ) = − s 1− e τ  + I e τ for 0 ≤ t ≤ T − tT (14.112) R   ∧ ∨ The initial conditions I and I are determined by using the steady-state boundary conditions: − tT

T 2 on

I

is

Circuit operation is characterized by two time domain equations:

∧

T1 D 1 T2 D 4 D 4 T3

o

io

I

(14.110)

2

2T

∧

io

 1  2 =   − 1 = FF − 1  2δ − 1 

where I =

T 3 on

D2 T3

Vo

o

2 o 2

=

T 3/4

vo

Vo

= Vs2 − ( 2δ − 1) Vs2 = 2 Vs δ (1 − δ )

RF =

T 4 on

+V s

The rms output voltage is independent of the duty cycle and is Vs. The output ac ripple voltage is

T 2 D 1D 1 T 2 D 3 T4 D 4 T3

T 1/2

(14.108)

The average output voltage can be positive or negative, depending solely on δ. No current discontinuity occurs since the output voltage is never actually zero. Even when the average voltage is zero, ripple current flows though the load, with an average value of zero amps.

654

-V s

(A) ∧

(14.113)

Vs 2e τ − 1 + e τ E − (A) −T R R 1− e τ The peak-to-peak ripple current is independent of load emf, E, and twice that given by equation (14.15). The mean output current is given by Vo − E ( (1 − 2δ )Vs − E ) (A) (14.114) = Io = R R

I

io

T

-V s io

∧

I

Io

∨

and I =

(

)

which can be positive or negative, as seen in figure 14.22c and d.

∨

∨

is

∨

−I ∨

∧

−I

∨

is

I

I

(c)

Io

I

I

∧

−I ∧

I

∧

−I

∨

I

(d)

Figure 14.22. Four-quadrant dc chopper circuit waveforms: multilevel (three-level) output voltage (a) with Vo > 0 and I o > 0; (b) with Vo < 0 and I o < 0; bipolar (two-level) output voltage (c) with Vo > 0 and I o > 0; (d) with Vo < 0 and I o < 0.

Power Electronics

655

Chapter 14

Figures 14.22c and d show chopper output voltage and current waveforms for conditions of positive average voltage and current in part (c) and negative average voltage and current in part (d). Each part is shown with the current having a positive maximum value and a negative minimum value. Such a load current condition involves activation of all possible chopper conducting paths (sequences) as shown at the top of each part in figure 14.22 and transposed to table 14.3A. The table shows how the conducting device possibilities (states) decrease if the minimum value is positive or the maximum value is negative. Table 14.3A: Four-quadrant chopper bipolar (two-level) output voltage states Conducting devices sequences

V 0 ∨

I >0

T1

D1

T4

D4

V 0

T1

D1

D3

∨

T4

D4

I < 0

V 0 T2

D2

T3

D3

∧

I δ, vo= -Vs • v∆ < δ, vo= 0 For δ = ½ • v∆ > δ, vo= 0 • v∆ < δ, vo= 0 For ½ > δ ≥ 1 • v∆ > δ, vo= 0 • v∆ < δ, vo= Vs # From figure 14.22b for δ < ½, the average output voltage varies linearly with δ such that T 1 t 0 dt + ∫ −Vs dt Vo = t T ∫0 1 t  = ( tT − T )Vs =  T − 1Vs T T  Examination of figure 14.22b reveals that the relationship between tT and δ must produce when δ = 0 : tT = 0 and vo = −Vs

(

V >0 ∧

DC Choppers

)

T

T

when δ = ½ :

(14.115)

tT = T and vo = 0

that is tT T which on substituting for tT /T in equation (14.115) gives t  Vo =  T − 1 Vs T  = ( 2δ − 1) Vs

δ =½

∨

If the minimum output current is positive, that is, I is positive, then only components for a first and fourth of figure 12.14c quadrant chopper conduct. Specifically T2, T3, D2, and D3 do not conduct. Examination ∨ shows that the output current conduction states are as shown in table 14.3A for I > 0 . If the output current never goes positive, that is I is negative, then T1, T4, D1, and D4 do not conduct. ∧ The conducting sequence becomes as shown in table 14.3A for I < 0 . Because the output is bipolar (±Vs), the average chopper output voltage, Vo does not affect the three possible steady state sequences. Table 14.3A shows that the conducting devices are independent of the average output voltage polarity. That is, the switching states are the same on the left and right sides of table 14.3A. The transition between these three possible sequences, due to a current level polarity change, is seamless. The only restriction is that both switches in any leg do not conduct simultaneously. This is ensured by inserting a brief dead-time between a switch turning off and its leg complement being turned on. That is, dead-time between the switching of the complementary pair (T1 -T2), and in the other leg the complementary pair is (T3 -T4 ). 14.6.2 Unified four-quadrant dc chopper - multilevel voltage output switching

In order to generate three output states, specifically ±Vs and 0V, two triangular references are used which are displaced by 180° from one another as shown in figure 14.22a and b. One carrier triangle is used to specify the state of the leg formed by T1 and T2 (the complement of T1), while the other carrier triangle specifies the state of leg formed by switches T3 and T4, (the complement of T3). The output voltage level switches between +Vs , 0V, and –Vs depending on the modulation index δ, such that 0 ≤ δ ≤ 1. A characteristic of the output voltage is that, depending on δ, only a maximum of two of the three states appear in the output, in steady-state. The 0V state is always one of the two alternating states. An alternative method to generate the same switching waveforms, is to us one triangular carrier and two references, δ and 1-δ. If δ = 0 then T1 and T4 never turn-on since T2 and T3 conduct continuously which impresses –Vs across the load. As δ increases from zero, the 0V state appears as well as the – Vs state, the later of which decreases in duration as δ increases. At δ = ½ the output is zero since T2 and T3 (or T1 and T4) are never on simultaneously to provide a path involving the dc source. The output voltage is formed by alternating 0V loops (T1 and T3 on, alternating to T2 and T4 on, etc.). The average output voltage is therefore zero. At the extreme δ = 1, T1 and T4 are on continuously and Vs is impressed across the load. As δ is reduced from one, the 0V state is introduced, progressively lengthening to all of the period as δ reduces to ½.

# From figure 14.22a for δ > ½, the average output voltage varies linearly with δ such that T 1 t Vo = Vs dt + ∫ 0 dt t T ∫0 t = Vs T T Examination of figure 14.22a reveals that the relationship between tT and δ must produce when δ = ½ : tT = 0 and vo = 0

(

when δ = 1:

T

T

)

(14.116)

(14.117)

tT = T and vo = Vs

that is t    which on substituting for tT /T in equation (14.117) gives Vo = ( 2δ − 1)Vs

δ = ½  T + 1 T

(14.118)

Alternately, if one pole produces δ then the other pole produces the complement ,1 - δ, such that the output is the difference, δ – (1 - δ) = 2δ - 1. Since the same expression results for δ ≤ ½ with bipolar switching, the average output current is the same for the range 0 ≤ δ ≤ 1, that is

(V

)

( ( 2δ − 1)Vs − E ) (A) = R R which can be positive or negative, depending on δ and the load emf, E. Io =

o

−E

(14.119)

Although the average voltage equations of the multilevel and bipolar controlled dc choppers are the same, the rms voltage and ripple voltage differ, as does the peak-to-peak output ripple current. Unlike the bipolar controlled chopper, the rms voltage for the multilevel controlled chopper is not a single continuous function. # For δ ≤ ½ the rms load voltage is ½ 2 1 T  Vrms =  ∫ (Vs ) dt  t T  T

= 1 − 2δ Vs

(14.120)

Power Electronics

657

Chapter 14

The output ac ripple voltage is 2 Vr = Vrms − Vo2

(

=

1 − 2δ Vs

) − ( ( 2δ − 1)V ) 2

2

s

(14.121)

DC Choppers

which, after shifting the zero time reference, in figure 14.22a or b, gives −t E  ∧ −t io ( t ) = − 1 − e τ  + I e τ R  0 ≤ t ≤ tT and δ ≤ ½ ∧

The output voltage ripple factor is Vr Vo

V  =  rms  − 1 =  Vo 

FF 2 − 1

− tT

(14.122) 2  1  = 2× =   −1 1 − 2δ  1 − 2δ  Thus as the duty cycle δ → 0 , the ripple factor tends to zero, consistent with dc output voltage, that is Vr = 0. The ripple factor is undefined when the average output voltage is zero, at δ = ½. The minimum rms ripple voltage in the output occurs when δ=½ or 0 giving an rms ripple voltage of zero, since the average is a dc value at the extremes (0V and -Vs respectively). The maximum ripple occurs at δ = ¼, when Vr = ½Vs, which is the same as when δ = ¾, (but half that obtained with the bipolar output control method, Vs). # For δ ≥ ½ the rms load voltage is ½ 2 1 T  Vrms =  ∫ ( −Vs ) dt  t T 

(14.123)

T

= 2δ − 1 Vs

∧

where I =

=

(

tT

V e τ −1 − and I = s T R τ e −1

(A)

(14.129)

E R

(A)

Figures 14.22a and b show output voltage and current waveforms for conditions of positive average voltage and current in part (a) and negative average voltage and current in part (b). Each part is shown with the current having a positive maximum value and a negative minimum value. Such a load current condition involves the activation of all possible chopper conducting paths, which are shown at the top of each part in figure 14.22 and transposed to table 14.3B. The conducting device possibilities decrease if the minimum value is positive or the maximum value is negative. Table 14.3B: A Four-quadrant chopper multilevel (three-level) output voltage states Conducting devices sequences

−V

) − ( ( 2δ − 1)V ) 2

s

2

= 2 Vs

( 2δ − 1)(1 − δ )

(14.124)

The minimum rms ripple voltage in the output occurs when δ = ½ or 1 giving an rms ripple voltage of zero, since the average is a dc value at the extremes (0V and Vs respectively). The maximum ripple occurs at δ = ¾, when Vr = ½Vs, which is half that obtained with the bipolar output control method.

V 0

T1

D1

D1

D1

D4

D4

T4

D4

V >0

V 0

The output voltage ripple factor is RF =

E R

−

V >0

2 o

2δ − 1 Vs

Vs 1 − e τ −T R 1− e τ

∨

The output ac ripple voltage is Vr = V

∨

The initial conditions I and I are determined by using the usual steady-state boundary condition method and are dependent on the transition states. For example, for continuous steady-state transitions between +Vs loops and 0V loops, the boundary conditions are given by

2

δ

2 rms

(14.128)

0 ≤ t ≤ T − tT and δ ≥ ½

= 2 Vs δ (1 − 2δ )

RF =

658

∧

T1

D1

T2

T2

D1

D1

T2

D2

D4

D4

T3

D3

T4

D4

T3

T3

V >0 2

V  = FF 2 − 1 =  rms  − 1 Vo  Vo  Vr

2

1−δ  1  = 2× =   −1 2δ − 1  2δ − 1 

D2

D2

T2

D2

T3

D3

D3

D3

(14.125)

∧

I 1 ρ n = n = nµn (15.1) V1

15.1

662

α α Β=π-α

δ 1-δ

2

∧

∧

I ∨

I

T ½T

I

I1

T

½T

α

α

dc-to-ac voltage-source inverter bridge topologies

15.1.1 Single-phase voltage-source inverter bridge Figure 15.1a shows an H-bridge inverter (VSI) for producing an ac voltage and employing switches which may be transistors (MOSFET or IGBT), or at high powers, thyristors (GTO or GCT). Device

BWW

Figure 15.1. GCT thyristor single-phase bridge inverter: (a) circuit diagram; (b) square-wave output voltage; and (c) quasi-square-wave output voltage.

Power Electronics

663

Chapter 15

DC to AC Inverters – Switched Mode

664

∨

Under steady-state load conditions, the initial current is I as shown in figure 15.1b, and equation (15.4) yields iL (t ) =

Vs  Vs ∨  −τt − − I e (A) R  R  0 ≤ t ≤ t1 = ½T

for vL = Vs

(15.7) (s)

(V)

∨

I ≤0

(A)

During the second half-cycle (t1 ≤ t ≤ t2) when the supply is effectively reversed across the load, equation (15.5) yields V  V ∧  −t V    t   −t  iL (t ) = − s +  s + I  e τ = − s  1 −  1 + tanh  1   e τ  (A) R R R   (15.8)  2τ     0 ≤ t ≤ t2 − t1 = ½T (s) for vL = − Vs (V)

VI = s s (A) R R The rms output voltage is Vs and the output fundamental frequency fo is f o = 1 T =

− t1

V 1− e V  t  (A) I = -I = s (15.9) = s tanh  1  −t R R  2τ  1+ e τ The zero current cross-over point tx, shown on figure 15.1b, can be found by solving equation (15.7) for t = tx when iL = 0, which yields  I∨ R   t x = τ An  1 −  Vs    (15.10)   IR = τ An  1 + (s)   Vs    The average thyristor current, I T , average diode current, I D , and mean source current, I s can be found by integration of the load current over the appropriated bounds shown in the following integrals. 1 t I T = ∫ iL ( t ) dt t2 t (15.11) −t 1 V V   −t  =  s ( t1 − to ) + τ  s + I   e τ − e τ   t2  R  R  where iL is given by equation (15.7) and 1 t I D = ∫ −iL ( t ) dt t2 0 (15.12) 1 V V  − t  =  − s t x − τ  s + I  e τ − 1  t2  R  R  where iL is given by equation (15.8). Inspection of the source current waveform in figure 15.1b shows that the average dc voltage source current is related to the average semiconductor device currents by ∧

τ

∨

1

1

vo1 =

2 2

π Vs = 0.90Vs

∞

=

=

1

t2

.

(15.16) 4

π Vs

∑ =

which is an (15.17)

(V)

I n sin ( nωo t − φn )

(15.18)

n 1, 3, 5

where I n =

I 4 Vs whence I n rms = n π nZ n 2

φn = tan −1 nωo L R

Z n = R 2 + ( nωo L) 2

cos φ1 = R

such that

Z1

The fundamental output power is 2

2

v o1  V s2  2 2  2   cos φ1  R = Z R  π   1 The load power is given by the sum of each harmonic i2R power component, that is

P1 = I 12R = 

2

∞

∞

(

)

 In  R= I n2 R = Vs I s   rms 2 n=1, 3, 5  n=1, 3, 5 Alternately, after integrating equation (15.14), with the load current from equation (15.8) t  − 1  V2  t  2τ 1 − e τ  V s2  2τ = tanh  1   PL = s 1 − 1 − t − 1  R  t1 R  t1  2τ   τ  1+e   PL =

∑

∑

(15.19)

(15.20)

(15.21)

2 R the rms loads current is From PL = i rms

i L rms =

o

x

2t1

The load current can be expressed in terms of the Fourier voltage waveform series, that is ∞ 4 1 sin ( nωo t − φn ) iL (ωt ) = Vs ∑ π n =1, 3, 5 nZ n

x

1

(15.15) 1

The instantaneous output voltage expressed as a Fourier series is given by ∞ 1 4 VL = Vs ∑ sin nωo t (V) π n odd n where ωo = 2π f o = 2π / t2 and for n = 1 the magnitude of the fundament frequency fo is output rms fundamental voltage vo1 of

∧

I ≥0 (A) A new time axis has been used in equation (15.8) starting at t = t1 in figure 15.1b. Since in steady-state ∧ ∧ ∨ by symmetry, I = - I , the initial steady-state current I can be found from equation (15.7) when, at t = t1, ∧ iL = I yielding

PL

iLrms =

Vs R

1−

2τ

t1

t  tanh  1   2τ 

(15.22)

The load power factor is given by

i L rsm R t  P 2τ tanh  1  = = 1− S i L rmsv rms t1  2τ  2

pf =

(15.23)

x

(

Is = 2 I T − I D

)

1 V V   −t  =  s t1 + τ  s + I   e τ − 1  t2  R  R  1

(15.13)

The steady-state mean power delivered by the dc supply and absorbed by the resistive load component R is given by 1 t 2 PL = ∫ Vs iL( t ) dt = Vs I s ( = I Lrms R) (15.14) (W) t1 0 where iL(t) is given by equation (15.7). Rather than integration involving equations (15.7) and (15.8), the mean load power can be used to determine the rms load current: 1

15.1.1ii - Quasi-square-wave (multilevel) output The rms output voltage form a H-bridge can be varied by producing a quasi-square output voltage (2t1 = t2, t0 < t1) as shown in figure 15.1c. After T1 and T2 have been turned on (state 10), at the angle α one device is turned off. If T1 is turned off (and T4 is turned on after a short delay), the load current slowly freewheels through T2 and D4 (state 00) in a zero voltage loop according to di (15.24) 0 = L L + iL R (V) dt When T2 is turned off and T3 turned on (state 01), the remaining load current rapidly reduces to zero back into the dc supply Vs, through diodes D3 and D4. When the load current reaches zero, T3 and T4 become forward biased and the output current reverses, through T3 and T4. The output voltage shown in figure 15.1c consists of a sequence of non-zero voltages ±Vs, alternated with zero output voltage periods. During the zero output voltage period a diode and switch conduct, firstly T1 and D3 in the first period, and T3 and D1 in the second zero output period. In each case, a zero voltage loop is formed by a switch, diode, and the load. The next two zero output sequences would be T2 and D4 then T4 and D2, forming alternating zero voltage loops (sequence 10, 00, 01, 11, 10, ..) rather than repeating a continuous T1 and D3 then T3 and D1 sequence of zero voltage loops (sequence 10, 11,

Power Electronics

665

Chapter 15

01, 11, 10, .. or sequence 10, 00, 01, 00, 10, ..). By alternating the zero voltage loops (between states 00 and 11), losses are uniformly distributed between the semiconductors, device switching frequency is half that experienced by the load, and a finer output voltage resolution is achievable. With reference to figure 15.1c, the load current iL for an applied quasi square-wave voltage is defined as follows. (i) vL > 0 V V  −t iL (t ) = s −  s − I o  e τ 0 ≤ t ≤ to (15.25) R R  I

(A) −t

0 ≤ t ≤ t1 − to

II

∧

(15.26)

(A)

Vs  Vs  −t + + I1  e τ = −iL (t ) R  R  I1 ≥ 0 (A)

iL (t ) = −

for

0 ≤ t ≤ to

I

(15.27)

∧

The currents I o , I , and I1 are given by Io = −

Vs e R

− t1 +to

τ

− t1

−e τ

(15.28)

(A)

− t1

1+ e τ t −o

Vs 1 − e τ (A) (15.29) t −1 R 1+ e τ I1 = − I o (A) (15.30) The zero current cross-over instant, tx, shown in figure 15.1c, is found by solving equation (15.25) for t when iL equals zero current.  I R  I R (15.31) t x = τ An  1 − o  = τ An  1 + 1  Vs  Vs    ∧

I =

The average thyristor current, I T , average diode current, I D , and mean source current, I s can be found by integration of the load current over the appropriated bounds (assuming alternating zero volt loops). 1 t 1 t −t I T = ∫ iL ( t ) dt + iL ( t ) dt (15.32) t2 t 2t2 ∫ 0 where iL is given by equations (15.25) and (15.26) for the respective integrals, and 1 t 1 t −t I D = ∫ −iL ( t ) dt + iL ( t ) dt (15.33) t2 0 2t2 ∫ 0 where iL is given by equations (15.25) and (15.26) for the respective integrals. 1

x

1

n =1,3,5,...

n

(15.39)

o

I

II

Inspection of the source current waveform in figure 15.1c shows that the average source current is related to the average semiconductor device currents by 1 to I s = ∫ iL (t )dt = 2 I T − I D (15.34) t1 0 The steady-state mean load and dc source powers are 1 t 2 (W) PL = ∫ Vs iL( t ) dt = Vs I s R) (15.35) ( = I Lrms t1 0 where iL(t) is given by equation (15.25). The mean load power can be used to determine the rms load current:

(

I

)

o

R

=

Vs I s

The output fundamental frequency fo is f o =

1

2t1 =

1

t2

The variable rms output voltage, for 0 ≤ α ≤ π, is 1 t 2 vrms = Vs dt = 1 − α π Vs t1 ∫ 0 o

∑

n =1,3,5,...

The load current can be expressed in terms of the Fourier voltage waveform series, that is ∞ ∞ V 4 cos½ nα iL (ωt ) = L = Vs ∑ sin ( nωo t − φn ) = ∑ I n sin ( nωo t − φn ) Z L π n =1,3,.. nZ n n =1, 3, 5,.. where I n =

4 Vs

π nZ n

cos½ nα whence I n rms =

Z n = R + (nωo L) 2

2

In

2 nωo L φn = tan R −1

1 Vrms 0.9 V1 0.8

1−α squarewave α=0

0.6

π

Vrms

0.9 V1

n

0.4

0.9 cos ½n α 0.9 × cos½n α n

V3

V3

V5

0.2

V5

(15.36)

(A)

R

nπ

2V s

∞

sin (n (ωot − β ) ) nπ The output Vab is then given by the difference, that is ∞ ∞ 2V s 2V s Vao −V bo = V ab = ∑ sin n ωot − ∑ sin (n (ωo t − β ) ) n π n =1,3,5,... n =1,3,5,... n π ∞ 4V s nβ = ∑ sin cos n ωot 2 n =1,3,5,... n π Expressing the phase shift angle β in terms of the delay angle α, where β=π-α, yields equation (15.38).

V bo =

II

1

PL

n odd

An alternative approach is to consider the control of one leg phase shifted by β radians with respect of the other leg. The phase output voltage for each leg, with respect to the supply (artificial) mid point, o, is ∞ 2V s Vao = ∑ sin n ωot

o

I

x

I Lrms =

π

and for n = 1, the rms fundamental of the output voltage vo1 is given by 2 2 (V) vo1 = Vs cos½α = 0.90 × Vs × cos½α

π The characteristics of these load voltage harmonics are shown in figure 15.2.

iL (t ) = I e τ

for I ≥ 0 (iii) vL < 0

2

per unit

∧

666

and the output fundamental frequency fo is f o = 1 t . This equation for rms output voltage shows that only the nth harmonic can be eliminated when cos½nα = 0 , that is for α = π / n . In so eliminating the nth harmonic, from equation (15.38), the magnitude of the fundamental is reduced to 4 π Vs cos π n . The output voltage VL in its Fourier coefficient series form is given by ∞ 4 cos ½ nα sin nωo t (V) VL = Vs ∑ (15.38)

Output Voltage

for I o ≤ 0 (ii) vL = 0


V7

V7

0

.

0 0

20°

40°

60°

80°

100°

delay angle

(15.37)

120°

140°

160°

½π

α

180° π

α=π-β

Figure 15.2. Full bridge inverter output voltage harmonics normalised with respect to square wave rms output voltage, Vrms=Vs.

(15.40)

Power Electronics

667

The load power is given by the sum of each harmonic i2R power component, that is 2 ∞ ∞ I  R= PL = ∑  n = Vs I s  ∑ I n2 rms R 2 n = 1, 3, 5  n =1, 3, 5,...

(

)

Chapter 15

(15.41)

)

Vs R

t  tanh  1   2τ  The load power factor is independent of α and is given by equation (15.23), that is

i L rms =

1−α

π

1−

2τ

t1

i L rsm R t  2τ P = = 1− tanh  1  S i L rmsv rms t1  2τ 

(15.43)

2

pf =

(15.44)

A variation of the basic four-switch dc to ac single-phase H-bridge is the half-bridge version where two series switches (one pole or leg) and diodes are replaced by a split two-capacitor voltage source, as shown in figure 15.3. This reduces the number of semiconductors and gate circuit requirements, but at the expense of halving the maximum output voltage. Example 15.3 illustrates the half-bridge and its essential features. Behaviour characteristics are as for the full-bridge, square-wave, single-phase inverter but Vs is replaced by ½Vs in the appropriate equations. Only a rectangular-wave bipolar output voltage can be obtained. Since zero volt loops cannot be created, no rms voltage control is possible. The rms output voltage is ½Vs, while the output power is a quarter that of the full H-bridge. Example 15.1: Single-phase H-bridge with an L-R load

A single-phase H-bridge inverter, as shown in figure 15.1a, supplies a 10 Ω resistance with inductance 50 mH, from a 340 V dc source. If the bridge is operating at 50 Hz (output), determine the average supply current and the load rms voltage and current and steady-state current waveforms with i. ii.

a square-wave output a symmetrical quasi-square-wave output with a 50 per cent on-time.

Solution

The time constant of the load, τ = 0.05mH/10Ω = 5 ms, t1 = 10ms and t2 = 20ms. i.

The output voltage rms value is 340 V ac. Equation (15.9) gives the load current at the time when the supply polarity is reversed across the load, as shown in figure 15.1b, that is − to

Vs 1 − e τ (A) −t R 1+ e τ where t1 = 10 ms. Therefore ∧ ∨ 340V 1 − e −2 I = −I = × (A) 10Ω 1 + e −2 = 25.9A When vL = +340 V, from equation (15.7) the load current is given by iL = 34 - (34 + 25.9) × e-200 t = 34 - 59.9e-200 t 0 ≤ t ≤ 10 ms ∧

∨

I = −I =

1

From equation (15.10) the zero current cross-over time, tx, occurs 5ms × An (1 + 25.9A×10Ω/340V ) = 2.83ms after load voltage reversal. When vL = -340 V, from equation (15.8) the load current is given by iL = -34 + (34 + 25.9) × e-200 t = -34 + 59.9e-200 t 0 ≤ t ≤ 10 ms The mean power delivered to the load is given by equation (15.14), that is 10 ms 1 PL = 340V × {34 - 59.9 × e-200t } dt 10ms ∫ 0 = 2755 W From P = i 2 R , the load rms current is P P = 16.60A and I s = L = 2755W = 8.1A iLrms = L = 2755W 10Ω 340V R Vs

668

These power and rms current results can be confirmed with equations (15.21) and (15.22).

The load power and rms current can be evaluated from equations (15.21) and (15.22) provided the rms voltage given by equation (15.37) replaces Vs. That is  V2 2τ  t  tanh  1   = i L2rms R PL = s 1 − α  1 − (15.42) π R t1  2τ   

(


ii. The quasi-square output voltage has a 5 ms on-time, to, and a 5 ms period of zero volts. From equation (15.37) the rms output voltage is Vs 1 − 5ms /10ms = Vs 2 = 240V rms . The current during the different intervals is specified by equations (15.25) to (15.30). Alternately, the steady-state load current equations can be specified by determining the load current equations for the first few cycles at start-up until steady-state conditions are attained. First 5 ms on-period when vL = 340 V and initially iL = 0 A iL = 34 - 34 e-200 t and at 5ms, iL = 21.5A First 5 ms zero-period when vL = 0 V iL = 21.5 e-200 t and at 5ms, iL =7.9A Second 5 ms on-period when vL = -340 V iL = -34 + (34+7.9) × e-200 t

with iL = 0 at 1 ms and ending with iL = -18.6 A Second 5 ms zero-period when vL = 0 V iL = -18.6 e-200 t ending with iL = -6.8A Third 5 ms on-period when vL = 340 V iL = 34 - (34+6.8) × e-200 t with iL = 0 at 0.9 ms and ending with iL = 19.0 A Third 5 ms zero-period when vL = 0 V iL = 19.0 e-200 t ending with iL = 7.0A Fourth 5 ms on-period when vL = -340 V iL = -34 + (34+7.0) × e-200 t with iL = 0 at 0.93 ms and ending with iL = -18.9 A Fourth 5 ms zero-period when vL = 0 V iL = -18.9 e-200 t ending with iL = -7.0A Steady-state load current conditions have been reached and the load current waveform is as shown in figure 15.1c. Convergence of an iterative solution is more rapid if the periods considered are much longer than the load time constant (and vice versa). The mean load power for the quasi-square wave is given by 5ms 1 340V × {34 - 41× e-200 t } dt PL = 10ms ∫ 0 = 1378 W The load rms and supply currents are P P = 11.74A = 4.05A iLrms = L = 1378W I s = L = 1378W 10Ω 340V R Vs ♣

Example 15.2: H-bridge inverter ac output factors

In each waveform case (square and quasi-square) of example 15.1a calculate i. ii. iii. iv. v. vi.

the average and peak current in the switches the average and peak current in the diodes the peak blocking voltage of each semiconductor type the average source current the harmonic factor and distortion factor of the lowest order harmonic the total harmonic distortion

Power Electronics

669

Chapter 15


670

vi.

Solution Square-wave

thd = ∧

i. The peak current in the switch is I = 25.9 A and the current zero cross-over occurs at tx =2.83ms. The average switch current, from equation (15.11) is 10ms 1 (34 - 59.9 e −200 t ) dt IT = 20ms ∫ 2.83ms = 5.71 A ii. The peak diode current is 25.9 A. The average diode current from equation (15.12) is 2.83ms 1 (34 - 59.9 e −200 t ) dt ID = 20ms ∫ 0 = 1.66 A iii. The maximum blocking voltage of each device is 340 V dc. iv. The average supply current is

(

)

Is = 2 I T − I D = 2 × ( 5.71A - 1.66A ) = 8.10A

This results in the supply delivery power of 340Vdc × 8.10A = 2754W v. From equation (15.16), with the third as the lowest harmonic, the distortion factors are V hf = ρ3 = 3 = 1 , that is, 33 1 3 per cent 3 V1 V3 df = µ3 = 3V1

= 1 , that is, 11.11 per cent 9

vi. From equation (15.16) 2

V  ∑  nn  / V1

thd =

( ) +( ) +( )

=

1 3

2

1 5

2

1 7

2

+ ......

 ∞  Vn  2       n≥2  n  

∑

2

=

i. The peak switch current is 18.9 A. From equation (15.32) the average switch current, using alternating zero volt loops, is 5ms 5ms 1 1 IT = (34 - 41e-200 t ) dt + 19e-200 t dt 20ms ∫ 0.93ms 40ms ∫ 0 = 2.18 + 1.50 = 3.68 A ii. The peak diode current (and peak switch current) is 18.9 A. The average diode current, from equation (15.33), when using alternating zero volt loops, is given by 0.93ms 5ms 1 1 ID = ( −34 + 41e−200t ) dt + 40ms ∫ 0 19e-200t dt 20ms ∫ 0 = 0.16 + 1.50 = 1.66 A iii. The maximum blocking voltage of each device type is 340 V. iv. The average supply current is

(

)

I s = 2 I T − I D = 2 × ( 3.68A - 1.66A ) = 4.04A

This results in the supply delivery power of 340Vdc × 4.04A = 1374W v. The harmonics are given by equations (15.1) to (15.3) V hf = ρ3 = 3 = 1 = 1 , that is, 33 1 3 per cent / 1 3 3 2 2 V1 df = µ3 =

V3 nV1

=

ρ3

n

=

1

9

, that is, 11.11 per cent

2

2

2

 1   −1   1   1   3  +  5  +  7  +  9  + ...         ♣

= 46.2 per cent

Example 15.3: Harmonic analysis of H-bridge inverter with an L-R load

For each delay case (α = 0° and α = 90°) in example 15.1, using Fourier voltage analysis, determine (ignore harmonics above the 10th): i. the magnitude of the fundamental and first four harmonics ii. the load rms voltage and current iii. load power iv. load power factor Solution

The appropriate harmonic analysis is outline in the following table, for α = 0° and α = 90°. n

Zn

Vn (α=0)

harmonic

R + ( 2π 50nL )

1

Ω 18.62

3

48.17

102

2.12

-72.12

-1.50

5

79.17

61.2

0.77

-43.28

-0.55

7

110.41

43.71

0.40

30.91

0.28

9

141.72

34

0.24

24.04

0.17

332.95V

16.59A

235.43V

11.73A

2

= 46.2 per cent

Quasi-square-wave, α = ½π (5 ms) and from equation (15.31) tx = 0.93ms

/ V1

2

0.9Vs n V 306

In (α=0)

Vn

Zn

A 16.43

Vn (α=90°)

0.9Vs cos (½ nα ) n V 216.37

In (α=90°)

Vn

Zn

A 11.62

i. The magnitude of the fundamental voltage is 306V for the square wave and is reduced to 216V when a phase delay angle of 90° is introduced. The table shows that the harmonics magnitudes reduce ( 1 n ) as the harmonic order increases. ii. The rms load current and voltage can be derived by the square root of the sum of the squares of the fundamental and harmonic components, that is, for the current irms = I12 + I 32 + I 52 + .....

The load rms currents, from the table, are 16.59A and 11.73A, which agree with the values obtained in example 15.1a. Notice that the predicted rms voltages of 333V and 235V differ significantly from the values in example 15.1a, given by Vs 1 − α π , namely 340V and 240.4V respectively. This is because the magnitude of the harmonics higher in order than 10 are not insignificant. The error introduced into the rms current value by ignoring these higher order voltages is insignificant because the impedance increases approximately proportionally with harmonic number, hence the resultant current becomes much smaller (insignificant) as the order increases. iii. The load power is the load i2R loss, that is 2 PL = irms R = 16.592 × 10Ω = 2752W for α = 0 2 PL = irms R = 11.732 × 10Ω = 1376W for α = 90°

iv. The load power factor is the ratio of real power dissipated to apparent power, that is i2 R 2752W P = 0.488 for α = 0 pf = = rms = S irms vrms 16.59A × 340V i2 R 1376W P = rms = = 0.486 for α = 90° S irms vrms 11.79A × 240.4V Equations (15.23) and (15.44) confirm the load power factor is 0.488, independent of α. ♣ pf =

Power Electronics

671

Chapter 15

Example 15.4: Single-phase half-bridge inverter with an L-R load

A single-phase half-bridge inverter as shown in the figure 15.3, supplies a 10 Ω resistance with inductance 50 mH from a 340 V dc source. If the bridge is operating at 50 Hz, determine for the squarewave output i. steady-state current waveforms ii. the load rms voltage iii. the peak load current and its time domain solution, iL(t) iv. the average and peak current in the switches v. the average and peak current in the diodes vi. the peak blocking voltage of each semiconductor type vii. the power delivered to the load, rms load current, and average supply current Cl

Cl +

Cl

Cupper

VL

½Vs

+½Vs

½Vs

170V

δ

½ ½Vs

+

∧

½Vs

I

tx

Clower

-170V

t1 12.95A

I

From examples 15.1 and 15.2, τ = 5ms. i. Figure 15.3 shows the output voltage and current waveforms, with various circuit component current waveforms superimposed. Note that no zero voltage loops can be created with the half-bridge. Only load voltages ±½Vs , that is ±170V dc, are possible. ii. The output voltage swing is ±½Vs, ±170V, thus the rms output voltage is ½Vs, 170V. This is, half that of the full-bridge inverter using the same magnitude source voltage Vs, 340V dc. iii. The peak load current is half that given by equation (15.9), that is − t1

½Vs 1 − e τ ½Vs  t  = I = tanh  1  −t R R  2τ  τ 1+ e ½×340V  10ms  = × tanh   = 12.95A 10Ω  2×5ms  The load current waveform is defined by equations (15.7) and (15.8), specifically ½Vs  ½Vs ∨  −τt iL (t ) = − − I ×e R  R  ∧

1

I

−t ½ × 340V  ½ × 340V  = − + 12.95A  × e 5ms 10Ω  10Ω 

0 ≤ t ≤ 10ms

and ½Vs  ½Vs ∧  −τt + + I ×e R  R  −t ½×340V  ½×340V  =− + + 12.95  × e 5ms 10Ω 10Ω  

iL (t ) = − II

−t 5ms

= 638.5 W

= −17 + 29.95 e for 0 ≤ t ≤ 10ms By halving the effective supply voltage, the current swing is also halved.

= 638.5W

10Ω

= 8A

= 638.5W

340V

= 1.88A

(c)

Solution

for

vii. The load power (whence various currents) is found by averaging the instantaneous load power 10 ms 1 P P 170V × (17 - 29.95 × e-200t ) dt PL = irms = L Is = L R Vs 10ms ∫ 0

♣

Figure 15.3. GCT thyristor single-phase half-bridge inverter: (a) circuit diagram; (b) square-wave output voltage; and (c) output voltage transfer function.

−t

v. The peak diode current is I = 12.95A . The average diode current is given by −t 2.83ms  1  5ms ID =  17 − 29.95e  dt 20ms ∫ 0   = 0.83 A

-12.95A

(b)

= 17 − 29.95 e 5ms

iv. The peak switch current is I = 12.95A . The average switch current is given by −t 10ms 1 (17 − 29.95e 5ms ) dt IT = 20ms ∫ 2.83ms = 2.86 A

-½Vs

∨

(a)

1

t2

2.83ms

672

vi. When a switch or diode of a parallel pair conduct, the complementary pair of devices experience a voltage Vs, 340V dc. Thus although the load experiences half the supply voltage, the semiconductors experience twice that voltage, the same voltage experienced by the switches in the full bridge inverter.

Cu

Cu


15.1.1iii - PWM-wave output The output voltage and frequency of a single-phase voltage-source inverter bridge can be control using one of two forms of pulse-width modulation, termed: • bipolar • multi-level, usually (meaninglessly) called unipolar

Both pwm techniques have been analysed extensively for dc voltage outputs when applied to the two quadrant and four quadrant dc choppers considered in Chapter 14, sections 14.5 and 14.6. It will be seen that the same triangular modulation principles can be applied and extended, when producing lowharmonic single-phase ac output voltages and currents. The main voltage output difference between the two methods is the harmonic content near the carrier frequency and its harmonics. Three-phase pwm is a naturally extension to the single-phase case, except single-phase pwm offers more degrees of flexibility than its application to three phase inverters, although three-phase pwm does have the attribute of triplen harmonic cancellation, due to the use of one (co-phasal) triangular carrier. Bipolar pulse width modulation Bipolar modulation is the simplest pwm method and involves comparing a fixed frequency and magnitude triangular carrier with the ac waveform desired, called the modulation waveform. The modulation waveform is usually a sinusoid of magnitude (modulation index) M such that 0 ≤ M ≤ 1. The waveforms in figure 15.4 shown that the load voltage VL swings between the two voltage levels, +Vs and -Vs, (hence the term bipolar output voltage), according to • T1 and T2 are on when vref > v∆ (T3 and T4 are off ) such that VL = +Vs • T3 and T4 are on when vref < v∆ (T1 and T2 are off ) such that VL = -Vs Multi-level pulse width modulation Two multilevel output voltage techniques can be use with single-phase voltage fed ac bridges. In both case, two triangular carries displaced by 180° give the same output for the same switching frequency.

i. The waveforms in figure 15.5 show that the load voltage VL swings between the two voltage levels, +Vs and -Vs, with interspaced zero periods (hence the term multilevel, specifically three-level in this case, 0V and ±Vs ), according to • T1 is on when vref > v∆ such that Vao = +Vs • T4 is on when vref < v∆ such that Vao = 0V • •

T3 is on when vref < -v∆ such that Vbo = Vs T2 is on when vref > -v∆ such that Vbo = 0V

The multilevel load output voltage is the difference between the two leg voltage waveforms and can be defines as follows:

Power Electronics

673

Chapter 15

• •

T1 and T2 are on such that Vao = +Vs, Vbo = 0V, Vab = +Vs T2 and T3 are on such that Vao = 0V, Vbo = +Vs, Vab = -Vs

• •

T1 and T3 are on such that Vao = +Vs, Vbo = +Vs, Vab = 0V T2 and T4 are on such that Vao = 0V, Vbo = 0V, Vab = 0V +1


674

The two zero output states are interleaved to balance switching losses between all four bridge switches. Device switching is at the carrier frequency, but the bridge load voltage (hence load current) experiences twice the leg switching frequency since the two carriers are displaced by 180°. ii. A second multilevel output voltage approach is shown in figure 15.16, where the triangular carriers are not only displaced by 180° in time, but are vertically displaced, as for multilevel inverter pwm generation, which is considered in section 15.4 (half the magnitude and twice the frequency as in figure 15.6). The upper triangle modulates reference values greater than zero, while the lower triangle modulates when the reference is less than zero.

M

Spectral comparison between bipolar and multilevel pwm waveforms

The key features of the H-bridge inverter output voltage with bipolar pwm are (fig 15.6a): • a triangular carrier has only odd Fourier components, so the output spectrum only has carrier components at odd harmonics of the carrier frequency • the first carrier components occur at the carrier frequency, fc • side-band components occur spaced by 2fo from other components, around all multiples of the carrier frequency fc

-1

V∆

Vref

(a)

From figure 15.6b, the key features of the H-bridge inverter output voltage with multilevel pwm are: • the output switching frequency is double 2fc each leg switching frequency fc, since the switching of each leg is time shifted (by 180°), hence the first carrier related components in the output occur at 2fc and then at multiples of 2fc (effectively the carrier is 2fo) • no triangular carrier Fourier components exist in the output voltage since the two carriers are in anti-phase (180° apart), effectively cancelling one another in spectrum terms • side-band components occur spaced by 2fo from other components, around each multiple of the carrier frequency 2fc

Vs T1 T2 ON

VL

T1 T2 ON

T1 T2 ON

T1 T2 ON

T1 T2 ON

T3 T4 ON

T3 T4 ON

T3 T4 ON

T3 T4 ON

T3 T4 ON

(b)

-Vs

Figure 15.4. Bipolar pulse width modulation: (a) carrier and modulation waveforms and (b) resultant load pwm waveform.

M-

fc- 2fo fc- 4fo

fc

fc+ 2fo fc+ 4fo

2fc-3fo

+1

with single-phase bipolar pwm nfc = 0 for n even 2fc- fo

2fc+ fo 2fc+3fo

2 fo

M

fo

1×fc

2×fc

3×fc

4×fc

(a)

-1

V∆

-V∆

Vref

Vs

(a)

Mwith single-phase multilevel pwm nfc = 0 for all n

T1 on (T4 off)

2fc-3fo

2fc- fo

(suppressed carrier)

2fc+ fo 2fc+3fo

2 fo

Vao T4 on (T1 off) T3 on (T2 off)

Vs

fo

1×fc

2×fc

3×fc

4×fc

(b)

Vbo T2 on (T3 off) (b) Vs Vab VL

Figure 15.6. Typical phase output frequency spectrum, at a give switch commutation frequency, for: (a) bipolar pwm and (b) multilevel pwm.

Vab=Vao-Vbo

15.1.2 Three-phase voltage-source inverter bridge

-Vs

Figure 15.5. Multilevel (3 level) pulse width modulation: (a) carriers and modulation waveforms and (b) resultant load pwm waveforms.

The basic dc to three-phase voltage-source inverter (VSI) bridge is shown in figure 15.7. It comprises six power switches together with six associated reactive energy feedback diodes. Each of the three inverter legs operates at a relative time displacement (phase) of ⅔π, 120°.

Power Electronics

675

Chapter 15

Table 15.1: Quasi-square-wave six conduction states - 180° conduction Three conducting switches

Interval 1 2 3 4 5 6

T1

T2 T2

T3 T3 T3

T4 T4

T5

T4

T5

T6

T5

T6

T1

T6

T1

T2

leg state

voltage vector

101

v5

001

v1

011

v3

010

v2

110

v6

100

v4


676

With reference to figure 15.8b, the line-to-load neutral voltage Fourier coefficients are given by  nπ − 2nπ  cos  2 + cos  2 3 3  (15.45) Vn = Vs  n 3π L− N

The line-to-load neutral voltage is therefore ∞ 2 sin n ωt Vn = Vs ∑ π n =1, 6 r ±1 n L− N

r = 1, 2, 3, ..

(15.46)

that is vRN =

2

π

Vs [sin ωt + 15 sin 5ωt + 17 sin 7ωt + 111 sin11ωt + . . .]

(15.47)

(V)

similarly for vYN and vBN, where ωt is substituted by ωt+⅔π and ωt-⅔π respectively. 15.1.2i - 180° (π) conduction Figure 15.8 shows inverter bridge quasi-square output voltage waveforms for a 180° switch conduction pattern. Each switch conducts for 180°, such that no two series connected (leg or arm) semiconductor switches across the voltage rail conduct simultaneously. Six patterns exist for one output cycle and the rate of sequencing these patterns, 6fo, specifies the bridge output frequency, fo. The conducting switches during the six distinct intervals are shown and can be summarised as in Table 15.1.

T1

T5

T4

T3

T2

T6

0V VRo

VBo

VYo

110

100

101

001

011

010

VRB

VBY

v RB  v BY  v YR

VYR

Figure 15.7. Three-phase VSI inverter circuit: (a) GCT thyristor bridge inverter; (b) star-type load; and (c) delta-type load.

The three output voltage waveforms can be derived by analysing a balanced resistive star load and considering each of the six connection patterns, as shown in figure 15.9, using the maxtrix in figure 15.8c. Effectively the resistors representing the three-phase load are sequentially cycled anticlockwise one at a time, being alternately connected to each supply rail. The output voltage is independent of the load, as it is for all voltage source inverters. Alternatively, the generation of the three-phase voltages can be analysed analytically by using the rotating voltage space vector technique. With this approach, the output voltage state from each of the three inverter legs (or poles) is encoded as summarised in table 15.1, where a ‘1’ signifies the upper switch in the leg is on, while a ‘0’ means the lower switch is on in that leg. The resultant binary number (one bit for each of the three inverter legs), represents the output voltage vector number (when converted to decimal). The six voltage vectors are shown in figure 15.10 forming sextant boundaries, where the quasi-square output waveform in figure 15.8b is generated by stepping instantaneously from one vector position to another in an anticlockwise direction. Note that the rotational stepping sequence is arranged such that when rotating in either direction, only one leg changes state, that is, one device turns off and then the complementary switch of that leg turns on, at each step. This minimises the inverter switching losses. The dwell time of the created rotating vector at each of the six vector positions, is ⅓π (T) of the cycle period (T). Note that the line-to-line zero voltage states 000 and 111 are not used. These represent the condition when either all the upper switches (T1, T3, T5) are on or all the lower switches (T2, T4, T5) are switched on (represented as the origin in figure 15.10). Phase reversal can be obtained by interchanging two phase outputs, or as is the preferred method, the direction of the rotating vector sequence is reversed. Reversing is therefore effectively achieved by back-tracking along each output waveform.

VRN

 v RN − v BN    = v BN − v YN    v YN − v RN 1  =0  -1 

(iR) VBN

-1 1 0

    

 v RN   v BN  1  v YN 0

-1

    

(iB) (c) VYN (iY)

v6

v4

v5

v1

v3

v2

(b)

Figure 15.8. A three-phase bridge inverter employing 180° switch conduction with a resistive load: (a) the bridge circuit showing T1, T5, and T6 conducting (leg state v6 :– 110); (b) circuit voltage and current waveforms with each of six sequential output voltage vectors identified; and (c) phase voltage to line voltage conversion matrix.

Power Electronics

677

Chapter 15

The line-to-line voltage, from equation (15.38) with α = ⅓π, gives Fourier coefficients defined by  nπ  cos 6  4  (15.48) Vn = Vs  n π The line-to-line voltage is thus ∞ 2 3 sin n ωt Vn = Vs ∑ cos nπ r = 1, 2, 3, . (15.49) n 6 π n=1, 6 r ±1 L− L

.

L− L

(the

symbol provides the sign), that is 2 3

V [sin ωt - 15 sin 5ωt - 17 sin 7ωt + 111 sin11ωt + . . .] (V) (15.50) π s and similarly for vBY and vYR. Figure 15.8b shows that vRB is shifted π with respect to vRN, hence to obtain the three line voltages while maintaining a vRN reference, ωt should be substituted with ωt + π, ωt- ½π and ωt+π, respectively. Since the interphase voltages consist of two square waves displaced by ⅔π, no triplen harmonics (3, 6, 9, . . .) exist. The outputs comprise harmonics given by the series n = 6r ± 1 where r ≥ 0 and is an integer. The nth harmonic has a magnitude of 1/n relative to the fundamental. vRB =


By examination of the interphase output voltages in figure 15.8 it can be established that the mean halfcycle voltage is ⅔Vs and the rms value is √⅔ Vs, namely 0.816 Vs. From equation (15.50) the rms value of the fundamental is √6 Vs /π, namely 0.78 Vs, that is 3/π times the total rms voltage value. The three-phase inverter output voltage properties are summarised in Table 15.2. 15.1.2ii - 120° (⅔π) conduction The basic three-phase inverter bridge in figure 15.7 can be controlled with each switch conducting for 120°. As a result, at any instant only two switches (one upper and one non-complementary lower) conduct and the resultant quasi-square output voltage waveforms are shown in figure 15.11. A 60° (⅓π), dead time exists between two series switches conducting, thereby providing a safety margin against simultaneous conduction of the two series devices (for example T1 and T4) across the dc supply rail. This safety margin is obtained at the expense of a lower semi-conductor device utilisation and rms output voltage than with 180° device conduction. The device conduction pattern is summarised in Table 15.3. A feature with ⅔π conduction is that the phase currents can be measured from the dc link current. Interval # 4 T 4 T 5 T 6 on leg state 010 v 2 = V s e π j

Y

Interval # 3 T 3 T 4 T 5 on leg state 011 v 3 = V s e π j

000 111

Interval # 5 T 1 T 5 T 6 on leg state 110 v6 = V s e π j

T1 / T4

T5 / T2

678

Interval # 6 T 1 T 2 T 6 on leg state 100 v 4 = V s e π j

T3 / T6

Interval # 2 T 2 T 3 T 4 on leg state 001 v1 = V s e 0 j

Interval # 1 T 1 T 2 T 3 on leg state 101 v 5 = V s e -π j

R T5

T1

T1 VRN = Vs /3 VBN = -2Vs /3 VYN = Vs /3

VRN = 2Vs /3 VBN = -Vs /3 VYN = -Vs /3

T2

T6 B

100 v4

101 v5

T3 VRN = -Vs /3 VBN = 2Vs /3 VYN = -Vs /3

VRN = Vs /3 VBN = Vs /3 VYN = -2Vs /3

T4 T2

Figure 15.10. Generation and arrangement of the six quasi-square inverter output voltage states.

T2

R

Y

Figure 15.8b for 180° conduction and 15.11b for 120° conduction show that the line to neutral voltage of one conduction pattern is proportional to the line-to-line voltage of the other. That is, from equation (15.38) with α = ⅓π ∞ 2 nπ vRN ( 2 3 π ) = ½ vRY (π ) = ∑ Vs cos sin nωt 6 n =1,3,5 π n (15.51) 3 Vs [sin ωt - 15 sin 5ωt - 17 sin 7ωt + 111 sin11ωt + . . .] (V) =

Y

Y

Y

T5

T5

T3

110 v6

B

T3

B

010 v2

B

B T1

011 v3

T6

Y

R

001 v1

VRN = -2Vs/3 VBN = Vs/3 VYN = Vs/3

VRN = -Vs /3 VBN = -Vs /3 VYN = 2Vs /3

T6

T4

B

3

π

and vRY ( 2 3 π ) = 3 2 vRN (π ) =

T4

∞

∑

n=1,3,5

R

3

2π

Figure 15.9. Determination of the line-to-neutral voltage waveforms for a balanced resistive load and 180° conduction as illustrated in figure 15.8.

=

3

π

2 3 nπ Vs cos sin nω t πn 6

Vs [sin ωt + 15 sin 5ωt + 17 sin 7ωt +

1 11

(15.52) sin11ωt + . . .]

(V)

Also vRY = √3 vRN and the phase relationship between these line and phase voltages, of π, has not been retained. That is, with respect to figure 15.11b, substitute ωt with ωt + π in equation (15.51) and ωt + ⅓π in equation (15.52).

Power Electronics

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680

The output voltage properties for both 120° and 180° conduction are summarised in the Table 15.2.

15.1.3ii - Single-pulse width modulation

Independent of the conduction angle (120°, 180° or even 150°), quasi-square 180° conduction occurs with inductive loads, producing the six hexagon states shown in the upper part of figure 15.10. The resistive load assumptions made in this section for explanation purposes can be misleading.

Simple pulse-width control can be employed as considered in section 15.1.1b, where a single-phase bridge is used to produce a quasi-square-wave output voltage as shown in figure 15.1c. An alternative method of producing a quasi-square wave of controllable pulse width is to transformeradd the square-wave outputs from two push-pull bridge inverters as shown in figure 15.12a. By phaseshifting the output by α, a quasi-square sum results as shown in figure 15.12b.

Table 15.2: Quasi-squarewave voltage properties for a resistive load Conduction period

Fundamental voltage peak rms

180°

Characteristic Distortion Factor

THD

µ

thd

3

π2

Vl1

V1

Vrms

(V)

(V)

(V)

2

π Vs

2 V 3 s

π

= 0.450 Vs

= 0.471Vs

= 0.955

2

Phase Voltage V L- N

Total rms

π

Vs

= 0.637Vs 2 3

6

= 1.10 Vs

= 0.78 Vs

= 0.816Vs

120°

(V)

(V)

(V)

3

6 V 2π s

Phase Voltage V L- N Line Voltage V L- L

π

π

π Vs

Vs

Vs

= 0.551 Vs

3

π

Vs

= 0.955Vs

1

9

= 0.955

∞

∑v

an

sin nωt

(15.53)

(V)

n odd

π2

3

9

= 0.955

π

∫

½π −½ π

Vs cos nα dα =

4 V cos(½ nα ) nπ s

(15.54)

(V)

−1

−1

= 0.311

π2

3

Vs

van = 2

= 0.311

π

−1 9 = 0.311

π

2 = 0.707 Vs

= 0.673 Vs

π2

3

Vs 6 = 0.408Vs

3 V 2π s

−1 9 = 0.311

π

1

= 0.390 Vs

Vo =

where

2 V 3 s

Line Voltage V L- L

The output voltage can be described by

= 0.955

Table 15.3: Quasi-squarewave conduction states - 120° conduction Two conducting devices

Interval 1

T1

2 3 4 5 6

T2 T2

T3 T3

T4 T4

T5 T5

T6 T6

T1

15.1.3 Inverter ac output voltage and frequency control techniques

It is a common requirement that the output voltage and/or frequency of an inverter be varied in order to control the load power or, in the case of an induction motor, to control the shaft speed and torque by maintaining a constant V / f ratio. The six VSI modulation control techniques to be considered are: • • • • • • •

Variable voltage dc link Single-pulse width modulation Multi-pulse width modulation Multi-pulse, selected notching modulation Sinusoidal pulse width modulation Triplen injection Triplens injected into the modulation waveform Voltage space vector modulation Selected harmonic elimination

v RB  v BY  v YR

 v RN − v BN    = v BN − v YN    v YN − v RN 1  =0  -1 

-1 1 0

    

 v RN   v BN  1  v YN 0

-1

    

(c)

15.1.3i - Variable voltage dc link

The rms voltage of a square-wave can be changed and controlled by varying the dc link source voltage. A variable dc link voltage can be achieved with a dc chopper as considered in chapter 14 or an ac phase-controlled thyristor bridge as considered in sections 12.2 and 12.4. A dc link L-C smoothing filter may be necessary.

Figure 15.11. A three-phase bridge inverter employing 120° switch conduction with a resistive star load: (a) the bridge circuit showing T1 and T2 conducting; (b) circuit voltage and current waveforms; and (c) phase voltage to line voltage conversion matrix.

Power Electronics

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The rms output voltage is Vr = Vs 1- α

π

and the rms value of the fundamental is 2 2 V1 = Vs cos½α

π

(V)

va1 =

(15.55)

2 240V = (V)

(15.56)

As α increases, the magnitude of the harmonics, particularly the third, becomes significant compared with the fundamental magnitude. This type of control may be used in high power applications.

π

4

Vs cos(½α )

4

× 340V × cos(½α )

π

682

from which the phase shift is 76.7°, 1.34 radians. ii. The rms output voltage is given by equation (15.55), that is V = V 1- α = 340V 1- 1.34 = 257.5V rms

π

s

π

iii. The peak values of the first four harmonics are given in the table below.

harmonic n

van =

4 V cos(½ nα ) nπ s

van2

3

-61.4

3765.0

5

-84.7

7175.3

7

-1.4

1.9

9

46.6

2168.5 .

∑v

2 an

=

114.50

The rms value of the ac of the first four harmonics is 114.5/√2 = 81.0V. iv. The ac component of the harmonics above the 9th is given by 2 2 Vrms n>9 = Vrms − Vrms n≤9 = 257.5V 2 − ( 240V 2 + 81.0V 2 ) = 46.3V

v. The total harmonic voltage distortion is given by THDv =

V 2 −V 2 rms

Va1

a1

2

× 100 =

 Vrms    − 1 × 100  Va1 

2

=

Figure 15.12. Voltage control by combining phase-shifted push-pull inverters: (a) two inverters with two transformers for summing and (b) circuit voltage waveforms for a phase displacement of α.

 257.5V   240V  − 1 × 100 = 38.9%   ♣

+Vs

fo δ1

Example 15.5: Single-pulse width modulation

Two single-phase H-bridge inverter outputs are transformer added, as shown in figure 15.12. Each inverter operates at 50Hz but phase shifted so as to produce 240V rms fundamental output when the rail voltage of each inverter is 340V dc and the transformers turns ratios are 2:2:1. Determine i. ii. iii. iv. v.

the phase shift between the two single phase inverters the rms output voltage the frequency and magnitude of the first 4 harmonics of 50Hz and their rms ac contribution to the rms output rms voltage of higher order harmonics (higher frequencies than those in part iii.) the total harmonic distortion of the output voltage.

-Vs δ1 < δ2 Carrier frequency +Vs

fc

fo

δ2 -Vs

Solution i. The output is a quasi-square waveform of magnitude ±340V dc. The magnitude of the 50Hz fundamental is given by equation (15.54), for n =1:

Figure 15.13. Inverter control giving variable duty cycle of five notches per half cycle: (a) low duty cycle, δ1, hence low fundamental magnitude and (b) higher duty cycle, δ2, for a high fundamental voltage output.

Power Electronics

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15.1.3iii - Multi-pulse width modulation

An extension of the single-pulse modulation technique is multiple-notching as shown in figure 15.13. The bridge switches are controlled so as to vary the on to off time of each notch, δ, thereby varying the output rms voltage which is given by Vrms = δ Vs . Alternatively, the number of notches can be varied. The harmonic content at lower output voltages is significantly lower than that obtained with single-pulse modulation. The increased switching frequency does increase the magnitude of higher order harmonics and the switching losses. The Fourier coefficients of the output voltage in figure 15.13 are given by fc fo   f f 4 Vn = (15.57) ∑ cos 2π f o n ( 2 j − 1 + δ ) − cos 2π f o n ( 2 j − 1 − δ ) n π j =1,2,3,..  c c  where fo is the fundamental frequency, fc the triangular carrier frequency and 0 ≤ δ ≤ 1 is the duty cycle. 15.1.3iv - Multi-pulse, selected notching modulation – selected harmonic elimination

If a multi-level waveform (±Vs, 0) is used with quarter wave symmetry, as shown in figure 15.14a, then both the harmonics and total rms output voltage can be controlled. With one pulse per quarter wave, the kth harmonic is eliminated from the output voltage if the centre of the pulse is located such that sin k λ = 0 (15.58) that is λ = π

k

Independent of the pulse width δ, the kth harmonic is eliminated and the other Fourier components are given by 8 π sin n δ Vn = V s sin n (15.59)

nπ

k

The output voltage total rms is solely dependent on the pulse width δ and is given by 2 Vo rms = V s δ

(15.60)

π

On the other hand, the bipolar waveform (±Vs) in figure 15.14b has an rms value of Vs, independent of the harmonics eliminated.


684

Selected elimination of lower-order harmonics can be achieved by producing an output voltage waveform as shown in figure 15.14b. The exact switching points are calculated off-line so as to eliminate the required harmonics. For n switchings per half cycle, n selected harmonics can be eliminated. In figure 15.14b two notches per half cycle are introduced; hence any two selected harmonics can be eliminated. The more notches, the lower is the output fundamental. For example, with two notches, the third and fifth harmonics are eliminated. From 4

∫

bn = π

½π 0

f (θ ) sin nθ dθ

n = 1, 2, 3, ....

for

(15.61)

b3 = 4 Vs (1 − 2 cos 3α + 2 cos 3β ) = 0 3π and b5 = 4 Vs (1 − 2 cos 5α + 2 cos 5β ) = 0 5π Solving yields α1 = 23.6° and β1 = 33.3°. The total rms output voltage is Vs, independent of the harmonics eliminated. The magnitude (whence rms) of each harmonic component is 4 Vn = V s (1 − 4 × sin n λ × sin n δ ) (15.62)

nπ

The maximum fundamental rms component of the output voltage waveform is 0.84 of a square wave, which is (2√2/π)Vs when δ = ½π which produces a square wave. Ten switching intervals exist compared with two per cycle for a square-wave, hence switching losses and control circuit complexity are increased. In the case of a three-phase inverter bridge, the third harmonic does not exist, hence the fifth and seventh (b5 and b7) can be eliminated with α1 = 16.3° and β1 = 22.1. The 5th, 7th, 11th, and 13th can be eliminated with the angles 10.55°, 16.09°, 30.91°, and 32.87° respectively. Because the waveforms have quarter wave symmetry, only angles for 90° need be stored. The output rms voltage magnitude can be varied by controlling the dc link voltage or by transformeradding two phase-displaced bridge outputs as demonstrated in figure 15.12. The output voltage Fourier components in equation (15.62) are modified by equation(15.54) given 4 Vn = V s (1 − 4 × sin n λ × sin n δ ) cos ½n α (15.63)

nπ

vL

And the total rms output voltage is reduced from Vs , as given by equation (15.55), that is

Vo rms = Vs 1 - α

δ Vs

π

½π

λ

λ

(V)

π

(15.64)

Thus the fundamental rms magnitude can be changed by introducing an extra constraint to be satisfied, along with the harmonic eliminating constraints (as a result of the extra constraint, one fewer harmonic can now be eliminated for a given number of switchings per quarter cycle).

2π

ωt (a)

-Vs

δ (b)

The multi-pulse selected notching modulation technique can be extended to the optimal pulse-width modulation method, where harmonics may not be eliminated, but minimised according to a specific criterion. In this method, the quarter wave output is considered to have a number of switching angles. These angles are selected so as, for example, to eliminate certain harmonics, minimise the rms of the ripple current, or any other desired performance index. The resultant non-linear equations are solved using numerical methods off-line. The computed angles are then stored in a ROM look-up table for use. A set of angles must be computed and stored for each desired level of the voltage fundamental and output frequency. The optimal pwm approach is particularly useful for high-power, high-voltage GCT thyristor inverters, which tend to be limited in switching frequency by device switching losses. Generally sinωt+ksin3ωt is generated (since the third harmonic of the square wave is not eliminated) ½π ½π 4 4 bn = ∫ f (θ ) sin n θ d θ = ∫ 1 × sin n θ d θ

π

π

0

0

For a fundamental magnitude of √3m of the pu link voltage and to eliminate N-1 (N-1>2) harmonics:

1

N

(

-∑ ( −1) cos αk = ¼ 2 + ( −1 )

1

N

N −1

mπ

)

-∑ ( −1) cos n αk = ½

1

λ Figure 15.14. Output voltage harmonic reduction for a single-phase bridge using selected notching: (a) multilevel output voltage and (b) bipolar output voltage.

k

k =1

1

k =1

where

for n = 5, 7, ..., 3N - 3 2 − ½ ( −1)

k

N −1

(

(

α1 < α2 < ... < αN < ½π 1 − 1 6 1 − ( −1)

N −1

))

For N-1 even, all αk angles are less than ½π other wise ⅓π (when N-1 is odd).

(15.65)

Power Electronics 90

80

80

70

70

60

60

Angle (◦)

90

50 40

20

20

10

10

0

0.2

0.4

0.6

0.8

0

1.2 4/π

1

cos 5α1 − cos 5α 2 + cos 5α 3 = ½

The resultant angles are shown in figure 15.15. The maximum modulation index, with respect to a square wave is 1.166 and 1.188 for angles less that 60 degrees and greater, respectively. Any solution with all angles less than 60° represents dead banding of the three phases, where each phase is alternately clamped to the dc link zero and positive rails (see section 15.1.3vi). The total harmonic distortion is virtually the same in both cases, as is the maximum common mode voltage dv/dt, while the rms common mode voltage is greater for the case when the angles can exceed 60 degrees. 0

0.2

0.4

1.4

1.2

1.2

0.8

3 th

11

th

13

0.2

7 0

0.2

th

5

rd

rd

1.2 4/π

1

0.8

cos 5α1 − cos 5α 2 + cos 5α 3 − cos 5α 4 = ½

Fundamental

cos11α1 − cos11α 2 + cos11α 3 − cos11α 4 = ½ 0.8

11 9

0.6

th

As further harmonics are eliminated, multiple solutions arise, with at least one solution giving a maximum magnitude tending to 1.155 (π/3) in magnitude, compared to 1.27 (4/ π) for a square wave.

th

0.4

th

13

0

1.2 4/π

1

5 0

0.2

th

7

0.4

15.1.3v - Sinusoidal pulse-width modulation (pwm)

th

1 - Natural sampling

th

0.6

0.8

1.2 4/π

1

Modulation Index

Modulation Index

0.2 pu of dc link Voltage

0.5

0

-0.5 0

2

4

6

8

10

12

14

16

18

20

Time (ms)

0.1 0 -0.1 -0.2

M=1

0

2

4

6

8

10

12

14

16

18

20

Time (ms)

THD 0.5

20 18 16

Total Harmonic distortion

14 12

0-60° and 0-90° including triplens

10

0-60° excluding triplens

8

0-90° excluding triplens

6 4

To eliminate the 5th, 7th, and 11th harmonics (an odd number of harmonics), with a fundamental magnitude with modulation index m, four angles are required, N=4 and the four equations to be solved are cos α1 − cos α 2 + cos α 3 − cos α 4 = ¼ ( 2 − m π ) cos 7α1 − cos 7α 2 + cos 7α 3 − cos 7α 4 = ½

0.2

0.6

0.8

1

th

0.4

3

pu

9

0.4

0

½ dc link voltage

1.4

0.6

0.6

Modulation Index

Fundamental

686

cos 7α1 − cos 7α 2 + cos 7α 3 = ½

Modulation Index

1


To eliminate the 5th and 7th harmonics (an even number of harmonics), with a fundamental magnitude with modulation index m, three angles are required, N=3 and the three equations to be solved are cos α1 − cos α 2 + cos α 3 = ¼ ( 2 + m π )

40 30

0

Chapter 15

50

30

pu of dc link Voltage

Angle (◦)

685

0.45

0.4

0.35

0-90°

0-60°

0.3

0.25

Common mode voltage, rms

(a) Synchronous carrier The output voltage waveform and method of generation for synchronous carrier, natural sampling sinusoidal pwm, suitable for the single-phase bridge of figure 15.1, are illustrated in figure 15.16. The switching points are determined by the intersection of the triangular carrier wave fc and the reference modulation sine wave, fo. The output frequency is at the sine-wave frequency fo and the output voltage is proportional to the magnitude of the sine wave. The amplitude M (0 ≤ M ≤ 1) is called the modulation index. For example, figure 15.16a shows maximum voltage output (M = 1), while in figure 15.16b where the sine-wave magnitude is halved (M = 0.5), the output voltage is halved. If the frequency of the modulation sinewave, fo, is an integer multiple of the triangular wave carrierfrequency, fc that is, fc = nfo where n is integer, then the modulation is synchronous, as shown in figure 15.16. If n is odd then the positive and negative output half cycles are symmetrical and the output voltage contains no even harmonics. In a three-phase system if n is a multiple of 3 (and odd), the carrier is a triplen of the modulating frequency and the spectrum does not contain the carrier or its harmonics. f c = (6q + 3) f o = nf o (15.66) for q = 1, 2, 3. The Fourier harmonic magnitudes of the line to line voltages are given by  nπ   nπ  a n = V A cos   cos    2   3  (15.67) n n π π     bn = V A sin   sin    2   3  where Vℓ is proportional to the dc supply voltage Vs and the modulation index M. Sinusoidal pwm requires a carrier of much higher frequency than the modulation frequency. The generated rectilinear output voltage pulses are modulated such that their duration is proportional to the instantaneous value of the sinusoidal waveform at the centre of the pulse; that is, the pulse area is proportional to the corresponding value of the modulating sine wave.

0.2

2 0

0

0.2

0.4

0.6

0.8

Modulation Index (a)

1

1.24/π

0

0.2

0.4

0.6

0.8

1

1.2

4/π

Modulation Index (b)

Figure 15.15. SHE commutation angles, normalised as a function of the fundamental eliminating: the 5th and 7th harmonics with commutation angles (a) 0 to 90° and (b) 0 to 60°.

If the carrier frequency is very high, an averaging effect occurs, resulting in a sinusoidal fundamental output with high-frequency harmonics, but minimal low-frequency harmonics. Rather than using two offset triangular carriers, as shown in figure 15.16, a triangular carrier without an offset can be used. Now the output only approximates the ideal. Figure 15.17 shows this pwm generation technique and voltage bipolar output waveform, when applied to the three-phase VSI inverter in figure 15.7. Two offset carriers are not applicable to six-switch, three-phase pwm generation since complementary switch action is required. That is, one switch in the inverter leg must always be on.

687

Power Electronics

Chapter 15


688

upper triangular carrier wave fc

lower triangular carrier wave fc

reference modulation sinewave fo

Figure 15.16. Derivation of trigger signals for multi-level naturally sampled pulse-width modulation waveforms: (a) for a high fundamental output voltage (M = 1) and (b) for a lower output voltage (M = 0.5), with conducting devices shown.

Figure 15.17. Naturally sampled pulse-width modulation waveforms suitable for a three-phase bridge inverter: (a) reference signals; (b) conducting devices and fundamental sine waves; and (c) one output line-to-line voltage waveform.

It will be noticed that, unlike the output in figure 15.16, no zero voltage output periods exist. This has the effect that, in the case of GCT thyristor bridges, a large number of commutation cycles is required. When zero output periods exist, as in figure 15.11, one GCT thyristor is commutated and the complementary device in that leg is not turned on. The previously commutated device can be turned back on without the need to commutate the complementary device, as would be required with the pwm technique illustrated in figure 15.17. Commutation losses are reduced, control circuitry simplified and the likelihood of simultaneous conduction of two series leg devices is reduced. The alternating zero voltage loop concept can be used, where in figure 15.17b, rather than T1 being on continuously during the first half of the output cycle, T2 is turned off leaving T1 on, then when either T1 or T2 must be turned off, T1 is turned off leaving T2 on.

(b) Asynchronous carrier When the carrier is not an integer multiple of the modulation waveform, asynchronous modulation results. Because the output frequency, fo, is usually variable over a wide range, it is difficult to ensure fc = nfo. To achieve synchronism, the carrier frequency must vary with frequency fo. Simpler generating systems result if a fixed carrier frequency is used, resulting in asynchronism between fo and fc at most output frequencies. Left over, incomplete carrier cycles create slowly varying output voltages, called subharmonics, which may be troublesome with low carrier frequencies, as found in high-power drives. Natural sampling, asynchronous sinusoidal pwm is usually restricted to analogue or ASIC implementation. The harmonic consequences of asynchronous-carrier natural-sampling are similar to asynchronous-carrier regular-sampling in 2 to follow. 2 - Regular sampling

(a) Asynchronous carrier When a fixed carrier frequency is used, usually no attempt is made to synchronise the modulation frequency. The output waveforms do not have quarter-wave symmetry which produces subharmonics. These subharmonics are insignificant if fc >> fo, usually, fc > 20 fo. The implementation of sinusoidal pwm with microprocessors or digital signal processors is common because of flexibility and the elimination of analogue circuitry associated problems. The digital pwm generation process involves scaling, by multiplication, of the per unit sine-wave samples stored in ROM.

Power Electronics

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Chapter 15

•


690

Asymmetrical modulation

Asymmetrical modulation is produced when the carrier is compared with a stepped sine wave produced by sampling and holding at twice the carrier frequency, as shown in figure 15.18b. Each side of the triangular carrier about a sampling point intersects the stepped waveform at different step levels. The resultant pulse width is asymmetrical about the sampling point, as illustrated by the lower pulse in figure 15.19 for two modulation waveform magnitudes. The pulse width is given by 1 t pa = (15.69) (1-½ M ( sin 2π fo t1 + sin 2π fo t2 ) ) 2 fc where t1 and t2 are the times at sampling such that t2 = t1 + 1/2fc. Figure 15.19 shows that a change in the modulation index M varies the pulse width on each edge, termed double edge modulation. A triangular carrier produces double edge modulation, while a sawtooth carrier produces single edge modulation, independent of the sampling technique. t p 2s t p1s

M2

M1 t1

Triangular carrier

fc

Reference f o2

Reference f o1

t2 M2

Line of sym m etry

M1

Figure 15.18. Regular sampling, asynchronous, sinusoidal pulse-width-modulation: (a) symmetrical modulation and (b) asymmetrical modulation.

t p1a t p2a

The multiplication process is time-consuming, hence natural sampling is not possible. In order to minimise the multiplication rate, the sinusoidal sine-wave reference is replaced by a quantised stepped representation of the sine-wave. Figure 15.18 shows two methods used. Sampling is synchronised to the carrier frequency and the multiplication process is performed at twice the sampling rate for threephase pwm generation (the third phase can be expressed in terms of two phases, since v1 + v2 + v3 = 0). •

Symmetrical modulation

Figure 15.18a illustrates the process of symmetrical modulation, where sampling is at the carrier frequency. The quantised sine-wave is stepped and held at each sample point. The triangular carrier is then compared with the step sine-wave sample. The modulation process is termed symmetrical modulation because the intersection of adjacent sides of the triangular carrier with the stepped sinewave, about the non-sampled carrier peak, are equidistant about the carrier peak. The pulse width, independent of the modulation index M, is symmetrical about the triangular carrier peak not associated with sampling, as illustrated by the upper pulse in figure 15.19. The pulse width is given by 1 t ps = (15.68) (1- M sin 2π fo t1 ) 2 fc where t1 is the time of sampling.

Figure 15.19. Regular sampling, asynchronous, sinusoidal pulse-width-modulation, showing double edge: (upper) asymmetrical modulation and (lower) symmetrical modulation.

3 - Frequency spectra of pwm waveforms

The most common form of sinusoidal modulation for three-phase inverters is regular sampling, asynchronous, fixed frequency carrier, pwm. If fc > 20fo, low frequency subharmonics can be ignored. The output spectra consists of the modulation frequency fo with magnitude M. Also present are the spectra components associated with the triangular carrier, fc. For any sampling, these are fc and the odd harmonics of fc. (The triangular carrier fc contains only odd harmonics). These decrease in magnitude with increasing frequency. About the frequency nfc are components of fo spaced at ± 2fo, which generally decrease in magnitude when further away from nfc. That is, at fc the harmonics present are fc, fc ± 2fo, fc ± 4fo, … while about 2fc, the harmonics present are 2fc ± f0, 2fc ± 3fo,..., but 2fc is not present. The typical output spectrum is shown in figure 15.20. The relative magnitudes of the sidebands vary with modulation depth and the carrier related frequencies present, fh, are given by

(

f h = ½ 1 + ( −1)

n+1

) n f ± ( 2k − ½ (1 + ( −1) )) f n

c

where k = 1, 2, 3,.... (sidebands) and

o

(15.70)

n = 1, 2, 3,.... (carrier )

Power Electronics

691

Chapter 15

Mwith single-phase unipolar pwm fh = 0 for n odd

(suppressed carrier and n - odd side bands)

2fo

fo

2fo

1 fc


692

apart). A consequence of dead banding is increased ripple current. Dead banding is achieved with discontinuous modulating reference signals. Dead banding for a continuous 120° per phase leg is also possible but the switching loss savings are not uniformly distributed amongst the six inverter switches. The magnitude of the fundamental (with respect to the ac mains) when using standard PWM can be increased by 2/√3 from 3x√3/2π, 0.827pu to 3/π, 0.955pu without introducing output voltage distortion, by the injection of triplen components, which are co-phasal in a three-phase system, and therefore do not appear in the line currents. Two approaches can be used to affect this undistorted output voltage magnitude increase.

2 fc

3 fc

4 fc

Figure 15.20. Location of carrier harmonics and modulation frequency sidebands, showing all sideband separated by 2fm.

Although the various pwm techniques produce other less predominate spectra components, the main difference is seen in the magnitude of the carrier harmonics and sidebands. The magnitudes increase as the pwm type changes from naturally sampling to regular sampling, then from asymmetrical to symmetrical modulation, and finally from double edge to single edge. With a three-phase inverter, the carrier fc and its harmonics do not appear in the line-to-line voltages since the carrier fc and in particular its harmonics, are co-phase to the three modulation waveforms.

m = 0

Triplen injection into the modulation waveform or Voltage space vector modulation

15.1.3vii - Triplen Injection modulation

1 - Triplens injected into the modulation waveform An inverter reconstitutes three-phase voltages with a maximum magnitude of 0.827 (3√3/2π) of the fixed three-phase input ac supply, converted to dc before inversion. A motor designed for the fixed mains supply is therefore under-fluxed at rated frequency and not fully utilised on an inverter. As will be shown, by using third harmonic voltage injection, the flux level can be increased to 0.955 (3/π) of that produced on the three-phase ac mains supply. If overmodulation (M > 1) is not allowed, then the modulation wave M sin ωt is restricted in magnitude to M = 1, as shown in figure 15.22a. If VRN = M sinωt ≤ 1pu and VYN = M sin(ωt + ⅔π) ≤ 1 pu then VRY = √3 M sin(ωt - π) where 0 ≤ M ≤ 1

m = ¼

m = ½ ×1.155

m = ¾

m = 1

ωt o

1 π 3

2 π 3

π

4 π 3

5 π 3

2π

Figure 15.21. Modulation reference waveform for phase dead banding.

15.1.3vi - Phase dead-banding

Dead banding is when one phase (leg) is in a fixed on state, and the remaining phases are appropriately modulated so that the phase currents remain sinusoidal. The dead banding occurs for 60° periods of each cycle with the phase with the largest magnitude voltage being permanently turned on. Sequentially each switch is clamped to the appropriate link rail. The leg output is in a high state if it is associated with the largest positive phase voltage magnitude, while the phase output is zero if it is associated with the largest negative phase magnitude. Thus the phase outputs are cycled, being alternately clamped high and low for 60° every 180° as shown in figure 15.21. A consequence of dead banding is reduced switching losses since each leg is not switched at the carrier frequency for 120° (two 60° periods 180°

Figure 15.22. Modulation reference waveforms: (a) sinusoidal reference, sin ωt; (b) third harmonic injection reference, sin ωt +  sin 3ωt; and (c) triplen injection reference, sin ωt + (1/√3π){9/8 sin3ωt 80/81 sin9ωt + . ..} where the near triangular waveform b is half the magnitude of the shaded area.

Power Electronics

693

Chapter 15

In a three-phase pwm generator, the fact that harmonics at 3fo (and odd multiplies of 3fo) vectorally cancel can be utilised effectively to increase M beyond 1, yet still ensure modulation occurs for every carrier frequency cycle. Let VRN = M′ sinωt+ sin3ωt) ≤ 1 pu and VYN = M′ ( sin(ωt +⅔π) +  sin 3(ωt + ⅔π)) ≤ 1 pu then VRY = √3 M′ sin(ωt - π) VRN has a maximum instantaneous value of 1 pu at ωt = ±⅓π, as shown in figure 15.22b. Therefore 3 VRN (ωt = 13 π ) = M ' =1 2 that is m'= 2 M m = 1.155M m M (15.71) 3

DC to AC Inverters – Switched Mode #

694

#

Interval 4 T4 T5 T6 on leg state 010 πj v2 = V s e 

Interval 3 T3 T4 T5 on leg state 011 πj v3 = V s e  SECTOR

II

SECTOR

SECTOR

III

#

Interval 5 T1 T5 T6 on leg state 110 πj v6 = V s e

I

#

Interval 2 T2 T3 T4 on leg state 001 0j v1 = V s e

000 111 SECTOR

SECTOR

IV

VI

SECTOR

V

Thus the fundamental of the phase voltage is M′ sin ωt = 1.155 M sin ωt. That is, if the modulation reference sin ωt +  sin 3ωt is used, the fundamental output voltage is 15.5 per cent larger than when sin ωt is used as a reference. The increased fundamental is shown in figure 15.22b. The spatial voltage vector technique injects the triplens according to r   1 ∞ ( −1) VRN = M ' sin ωt + (15.72)  sin  ( 2r + 1) 3ωt  ∑ 1 1  + − + + 2 1 2 1 r r 3 π ( ) ( ) r 0 = 3 3     The Fourier triplen series represents half the magnitude of the shaded area in figure 15.22c (the waveform marked ‘b’), which is formed by the three-phase sinusoidal waveforms. The spatial voltage vector waveform is defined by 3 sin(ωt ) 0 ≤ ωt ≤ 16 π 2 (15.73) 3 1 sin(ωt + 16 π ) 6 π ≤ ωt ≤ ½π 2 The use of this reference increases the duration of the zero volt loops, thereby decreasing inverter output current ripple. The maximum modulation index is 2/√3, 1.155. Third harmonic injection, yielding M = 1.155, is a satisfactory approximation to spatial voltage vector injection.

#

#

Interval 1 T1 T2 T3 on leg state 101 - πj v5 = V s e 

Interval 6 T1 T2 T6 on leg state 100 πj v4 = V s e 

001 v1

011 v3

010 v2

110 v6

100 v4

101 v5

2 - Voltage space vector pwm

When generating three-phase quasi-square output voltages, the inverter switches step progressively to each of the six switch output possibilities (states). In figure 15.10, when producing the quasi-square output, each of these six states is represented by an output voltage space vector. Each vector has a ⅓π displacement from its two adjacent states, and each has a length Vs which is the pole output voltage relative to the inverter 0V rail. Effectively, the quasi-square three-phase output is generated by a rotating vector of length Vs, jumping successively from one output state to the next in the sequence, and in so doing creating six voltage output sectors. The speed of rotation, in particular the time for one rotation, determines the inverter output frequency. The sequence of voltage vectors {v1, v3, v2, v6, v4, v5} is arranged such that stepping from one state to the next involves only one of the three poles changing state. Thus the number of inverter devices needing to change states (switch) at each transition, is minimised. [If the inverter switches are relabelled, upper switches T1, T2, T3 - right to left; and lower switches T4, T5, T6 - right to left: then the rotating voltage sequence becomes {v1, v2, v3, v4, v5, v6}] Rather than stepping ⅓π radians per step, from one voltage space vector position to the next, thereby producing a six-step quasi-square fixed magnitude voltage output, the rotating vector is rotated in smaller steps based on the position being updated at a constant rate (carrier frequency). Furthermore, the vector length can be varied, modulated, to a magnitude less than Vs. 2 V sin 1 π − θ (3 ) o/ p Va ta 3 = = Tc v1 Vs Vb tb = = Tc v3

2 Vo / p sin θ 3 Vs

where v1 = v3

(15.74)

111 v7

000 v0

Figure 15.23. Instantaneous output voltage states for the three legs of an inverter.

To incorporate a variable rotating vector length (modulation depth), it is necessary to vary the average voltage in each carrier period. Hence pulse width modulation is used in the period between each finite step of the rotating vector. Pulse width modulation requires the introduction of zero voltage output states, namely all the top switches on (state 111, v7) or all the lower switches on (state 000, v0). These two extra states are shown in figure 15.23, at the centre of the hexagon. Now the pole-to-pole output voltage can be zero, which allows duty cycle variation to achieve variable average output voltage for each phase, within each carrier period, proportional to the magnitude of the position vector. To facilitate vector positions (angles) that do not lie on one of the six quasi-square output vectors, an intermediate vector Vo/p e jθ is resolved into the vector sum of the two quasi-square vectors adjacent to the rotating vector. This process is shown in figure 15.24 for a voltage vector Vo/p that lies in sector I, between output states v1 (001) and v3 (011). The voltage vector has been resolved into the two components Va and Vb as shown. The time represented by quasi-square vectors v1 and v3 is the carrier period Tc, in each case. Therefore the portion of Tc associated with va and vb is scaled proportionally to v1 and v3, giving ta and tb. The two sine terms in equation (15.74) generate two sine waves displaced by 120°, identical to that generated with standard carrier based sinusoidal pwm.

Power Electronics

695

Chapter 15

The sum of ta and tb cannot be greater than the carrier period Tc, thus ta + tb ≤ Tc

(15.75) ta + tb + to = Tc where the slack variable to has been included to form an equality. The equality dictates that vector v1 is used for a period ta, v3 is used for a period tb, and during period to, the null vector, v0 or v7, at the centre of the hexagon is used, which do not affect the average voltage during the carrier interval Tc. A further constraint is imposed in the time domain. The rotating voltage vector is a fixed length for all rotating angles, for a given inverter output voltage. Its length is restricted in both time and space. Obviously the resolved component lengths cannot exceed the pole vector length, Vs. Additionally, the two vector magnitudes are each a portion of the carrier period, where ta and tb could be both equal to Tc, that is, they both have a maximum length Vs. The anomaly is that voltages va and vb are added vectorially but their scalar durations (times ta and tb) are added linearly. The longest time ta + tb possible is when to is zero, as shown in figures 15.24a and 15.23a, by the hexagon boundary. The shortest vector to the boundary is where both resolving vectors have a length ½Vs, as shown in figure 15.24b. For such a condition, ta = tb = ½Tc, that is ta + tb = Tc. Thus for a constant inverter output voltage, when the rotating voltage vector has a constant length, Vlo /p , the locus of allowable rotating reference voltage vectors must be within the circle scribed by the maximum length vector shown in figure 15.24b. As shown, this vector has a length v1 cos30°, specifically 0.866Vs. Thus the full quasi-square vectors v1, v2, etc., which have a magnitude of 1×Vs, cannot be used for generating a sinusoidal output voltage. The excess length of each quasi-square voltage (which represents time) is accounted for by using zero state voltage vectors for a period corresponding to that extra length (1- cos30° at maximum output voltage). Having calculated the necessary periods for the inverter poles (ta, tb, and to), the carrier period switching pattern can be assigned in two ways. • •


696

Each approach is shown in figure 15.25, using single edged modulation. The waveforms are based on the equivalent of symmetrical modulation where the pulses are symmetrical about the carrier trough. By minimising the current ripple, seven switching states are used per carrier cycle, while for loss minimisation (dead banding) only five switching states occur, but at the expense of increased ripple current in the output current. When dead banding, the zero voltage state v0 is used in even numbered sextants and v7 is used in odd numbered sextants. Sideband and harmonic component magnitudes can be decreased if double-edged modulation placement of the states is used, which requires recalculation of ta, tb, and to at the carrier crest, as well as at the trough. Over-modulation is when the magnitude of the demanded rotating vector is greater than Vlo /p such that the zero voltage time reduces to zero, to = 0, during a portion of the time of one rotation of the output vector. Initially this occurs at 30° ( 16 π ( 2 N sector − 1) ) when the output vector length reaches Vlo /p , as shown in figure 15.24b. As the demand voltage magnitude increases further, the region around the 30° vector position where to ceases to occur, increases as shown in figure 15.24c. When the output rotational vector magnitude increases to Vs, the maximum possible, angle α reduces to zero, and to ceases to occur at any rotational angle. The values of ta, tb, and to (if greater than zero), are calculated as usual, but pulse times are assigned pro rata to fit within the carrier period Tc. The switching frequency can be decreased by using dc-link clamping like in 15.1.3vi. Each leg is successively clamped, alternately to each dc rail (that is states 000 and 111 are alternated every 60° when a zero state is required). For example, in sector 1, an odd sector number, the sequence would be states [111] [011] [001] [011] [111]. In sector 2, an even sector number, the sequence would be states [000] [010] [001] [010] [000]. In odd sector number zero vector [111] is used, while [000] is used in even numbered sector.

Minimised current ripple Minimised switching losses, using dead banding

v0

v1

v3

v7

v7

v3

v1

v0

0 00

0 01

011

111

1 11

01 1

001

0 00

¼ to

½ ta

½ tb

¼ to ¼ to

½ tb

¼ ta

¼ to

ΦR V 3 =V s e

j?π

V 3 =V s e

011

j?π

Tc

011

ΦY SECTOR I

SECTOR I

Tc

ωt

ΦB

∧

Vo / p

tb Vb = 2 VO / P sin θ 3 000 111

Tc

V s cos30°

VoV/ pO/P e jθ

½v 3 = ½V s

θ

ta

Va = 2 VO / P sin ( 13 π − θ ) 3

v 1 =V s e

½v 1 = ½V s

j0

(a )

Tc

30°

000 111

v 1 =V s e

j0

001

001

(a)

(b) V 3 =V s e

j?π

Tc

v1

v3

v7

v7

v3

v1

001

01 1

111

111

011

001

½ ta

½ tb

¼ to

¼ to

½ tb

¼ ta

ΦR

tb + ta < T c reduced to

011

ΦY

60°-α

tb + ta > T c no to

V o /p > Vo /p

TTcc

ΦB

Vlo / p

Tc α

000 111

Tc v 1 =V s e

tb + ta < T c reduced to

j0

(b )

Figure 15.25. Assignment of pole periods ta and tb based on: (a) minimum current ripple and (b) minimum switching transitions per carrier cycle, Tc.

001

(c)

Figure 15.24. First sector of inverter operational area involving pole outputs 001 and 011: (a) general rotating voltage vector; (b) maximum allowable voltage vector length for undistorted output voltages; and (c) over modulation.

15.1.4 Common mode voltage

The common mode CM voltage is a remanent voltage with respect to a reference zero ‘o’ as shown in figure 15.26(a). The line voltages and a common mode voltage Vcm can be derived based on leg phase voltages (Vao, Vbo, Vco) of a two-level three-phase inverter, as follows:

Power Electronics

697

Chapter 15

Vao = Van +Vcm V bo = V bn +Vcm Vco = Vcn +Vcm The sum of the leg voltages is given by : Vao +V bo +Vco = (Van +Vbn +Vcn ) + 3Vcm In a three-phase system: Van +V bn +Vcn = 0 thus the common mode voltage source in a three-phase system is: Vcm (t ) = 1 3 (V ao (t ) +V bo (t ) +Vco (t ) ) = 1 3 (Va (t ) +V b (t ) +Vc (t ) )

V1

V2

The CM voltage is a staircase function with steps of ⅓Vdc (Vdc - dc link voltage) within a frequency of three time the inverter modulation frequency, plus carrier related modulation steps superimposed, as shown in figure 15.26. Because the Kirchhoff voltage loop is usually completed by capacitance, a train of damped sinewave pulses of CM current flows as a result of each CM voltage step. In electrical machines such currents cause bearing deterioration. Generally, in electrical circuits, the CM currents through substrates, isolation capacitance, etc., produce and inject electrical noise and cause EMC interference.

V3

Vao

(b)

i1

Lin

i2

Lin

i3

S1

S5

S3

+

S4

S2

L O A D

Vdc

S6

Figure 15.27. PWM boost three-phase rectifier.

15.2

dc-to-ac controlled current-source inverters

15.2.1 Single-phase current source inverter n

(a)

Vno Two-level inverter

Lin

In the current source inverter, CSI, the dc supply is of high reactance, being inductive so as to maintain the required inverter output bidirectional current independent of the inverter load.

Van o

698

Io

where Va, Vb, Vc are the phase voltages, n is the load neutral, and o is the split dc link centre voltage node.

a


Three-level inverter

(c)

A single-phase, controlled current-sourced bridge is shown in figure 15.28a and its near square-wave output current is shown in figure 15.28b. No freewheel diodes are required and the thyristors require forced commutation and have to withstand reverse voltages. An inverter current path must be maintained at all times for the source controlled current. Consider thyristors T1 and T2 on and conducting the constant load current. The capacitors are charged with plates X and Y positive as a result of the previous commutation cycle. • Phase I Thyristors T1 and T2 are commutated by triggering thyristors T3 and T4. The capacitors impress negative voltages across the respective thyristors to be commutated off, as shown in figure 15.29a. The load current is displaced from T1 and T2 via the path T3-C1-D1, the load and D2-C2-T4. The two capacitors discharge in series with the load, each capacitor reverse biasing the thyristor to be commutated, T1 and T2 as well as diodes D3 to D4. The capacitors discharge linearly (due to the constant current source). • Phase II When both capacitors are discharged, the load current transfers from D1 to D2 and from D3 to D4, which connects the capacitors in parallel with the load via diodes D1 to D2. The plates X and Y now charge negative, ready for the next commutation cycle, as shown in figure 15.29b. Thyristors T1 and T2 are now forward biased and must have attained forward blocking ability before the start of phase 2.

Figure 15.26. Inverter common mode voltage: (a) source voltages, (b) two level inverter common mode voltage, and (c) three level inverter common mode voltage.

15.1.5 DC link voltage boosting

Both triplen injection and SVM under flux a 50/60Hz machine designed to operate from a given threephase ac mains supply. Increased dc rail voltage (over that produced from rectification) can be achieved with the three-phase boost converter shown in figure 15.27. Additionally, being a boost converter, the ac input current can be continuous, and force to track any reference whilst maintaining the transferred power balance between the input and the output. By using the ac mains as references, the input current can be sinusoidal, of high quality and at any desired angle, usual in phase with supply voltage - unity power factor. The bridge acts as an uncontrolled rectifier when the output voltage is below the mains rectified level, as during start-up when the dc link capacitor is uncharged. Near instantaneous power reversal (by current direction reversal) is possible when the converter acts as a dc to ac inverter. The power factor angle and three-phase voltage magnitude can be varied to control the active and reactive power flows back into the ac grid. PWM or SVM control can insure sinusoidal current in both conversion directions.

Figure 15.28. Single-phase controlled-current sourced bridge inverter: (a) bridge circuit with a current source input and (b) load current waveform.

Power Electronics

699

Chapter 15

-

+

+

-

-

+

-

+


700

+

+

-

+

+

-

(a)

(b)

Figure 15.29. Controlled-current sourced bridge inverter showing commutation of T1 and T2 by T3 and T4: (a) capacitors C1 and C2 discharging and T1, T2, D3, and D4 reversed biased and (b) C1, C2, and the load in parallel with C1 and C2 charging.

The on-going thyristor automatically commutates the outgoing thyristor. This repeated commutation sequencing is a processed termed auto-sequential thyristor commutation. The load voltage is load dependent and usually has controlled voltage spikes during commutation. Since the GTO and GCT both can be commutated from the gate, the two commutation capacitors C1 and C2 are not necessary. Commutation overlap is still essential. Also, if the thyristors have reverse blocking capability, the four diodes D1 to D4 are not necessary. IGBTs require series blocking diodes, which increases on-state losses. In practice, the current source inverter is only used in very high-power applications (>1MVA), and the ratings of the self-commutating thyristor devices can be greatly extended if the simple external capacitive commutation circuits shown in figure 15.28 are used to reduce thyristor turn-off stresses. 15.2.2 Three-phase current source inverter

A three-phase controlled current-source inverter is shown in figure 15.30a. Only two thyristors can be on at any instant, that is, the 120° thyristor conduction principle shown in figure 15.11 is used. A quasisquare line current results, as illustrated in figure 15.30b. There is a 60° phase displacement between commutation of an upper device followed by commutation of a lower device. An upper device (T1, T3, T5) is turned on to commutate another upper device, and a lower device (T2, T4, T6) commutates another lower device. The three upper capacitors are all involved with each upper device commutation, whilst the same constraint applies to the lower capacitors. Thyristor commutation occurs in two distinct phases. • Phase I In figure 15.31a the capacitors C13, C35, C51 are charged with the shown polarities as a result of the earlier commutation of T5. T1 is commutated by turning on T3. During commutation, the capacitor between the two commutating switches is in parallel with the two remaining capacitors which are effectively connected in series. Capacitor C13 provides displacement current whilst in parallel, C35 and C151 in series also provide thyristor T1 displacement current, thereby reverse biasing T1. • Phase II When the capacitors have discharged, T1 becomes forward biased, as shown in figure 15.31b, and must have regained forward blocking capability before the applied positive dv/dt. The capacitor voltages reverse as shown in figure 15.31b and when fully charged, diode D1 ceases to conduct. Independent of this commutation, lower thyristor T2 is commutated by turning on T4, 60° later.

As with the single-phase current sourced inverter, assisted capacitor commutation can greatly improve the capabilities of self-commutating thyristors, such as the GTO thyristor and GCT. The output capacitors stiffen the output ac voltage.

Figure 15.30. Three-phase controlled-current sourced bridge inverter: (a) bridge circuit with a current source input and (b) load current waveform for one phase showing 120° conduction.

An important advantage of the controlled current source concept, as opposed to the constant voltage link, is good fault tolerance and protection. An output short circuit or simultaneous conduction in an inverter leg is controlled by the current source. Its time constant is usually longer than that of the input converter, hence converter shut-down can be initiated before the link current can rise to a catastrophic level.

+

Io +

-

-

-

+

+

Io

-

+

C35

C13

-

C51

D1

-

+

D3

-

+ C51

Io

Io Io

Io

Io

(a)

A typical application for a three-phase current-sourced inverter would be to feed and control a threephase induction motor. Varying load requirements are met by changing the source current level over a number of cycles by varying the link inductor input voltage.

-

C35

C13 D1

+ +

Io

(b)

Figure 15.31. Controlled-current sourced bridge three-phase inverter showing commutation of T1 and T3: (a) capacitors C13 discharging in parallel with C35 and C51 discharging in series, with T1 and D3 reversed biased (b) C13, C35, and C51 charging in series with the load , with T1 forward biased.

Power Electronics

701

Chapter 15

PWM techniques are applicable to current source inverters in order to reduce current harmonics, thereby reducing load losses and pulsating motor shaft torques. Since current source inverters are most attractive in very high-power applications, inverter switching is minimised by using optimal pwm (selected harmonic elimination). The central 60° portion about the maximums of each phase cannot be modulated, since link current must flow and during such periods both the other phases require the opposite current direction. Attempts to over come such pwm restrictions include using a current sourced inverter with additional parallel current displacement paths as shown in figure 15.32. The auxiliary thyristors, Tupper and Tlower, and capacitors, CR, CY, and CB, provide alternative current paths (extra control states) and temporary energy storage. The auxiliary thyristor can be commutated by the extra capacitors. The problem can be alleviated by triplen injection or SVM, which minimises the duration of any such periods in the central 60° blocks, so that the link can be shorted for the short periods. Characteristics and features of current source inverters • The inverter is simple and can utilise rectifier grade thyristors. The switching devices must have reverse blocking capability and experience high voltages (both forward and reverse) during commutation. • Commutation capability is load current dependent and a minimum load is required. This limits the operating frequency and precludes use in UPS systems. The limited operating frequency can result in torque pulsations. • The inverter can recover from an output short circuit hence the system is rugged and reliable – fault tolerant. • The converter-inverter configuration has inherent four quadrant capability without extra power components. Power inversion is achieved by reversing the converter average voltage output with a delay angle of α > ½π, as in the three-phase fully controlled converter shown in figure 12.11 (or 15.4.3). In the event of a power supply failure, mechanical braking is necessary. Dynamic braking is possible with voltage source systems. • Current source inverter systems have sluggish performance and stability problems on light loads and at high frequency. On the other hand, voltage source systems have minimal stability problems and can operate open loop. • Each machine must have its own controlled rectifier and inverter. The dc link of the voltage source scheme can be used by many inverters or many machines can utilise one inverter. A dc link offers limited ride-through. • Current feed inverters tend to be larger in size and weight, because of the link inductor and filtering requirements.

15.3


Multi-level voltage-source inverters

The conventional three-phase, six-switch dc to ac voltage-source inverter is shown in figure 15.7. Each of the three inverter legs has an output which can provide one of two voltage levels, Vs, when the upper switch (or diode) is on, and 0 when the lower switch (or diode) conducts. The quality of the output waveform is determined by the resolution and switching frequency of the pwm technique used. A multilevel inverter (directly or indirectly) divides the dc rail, so that the output of the leg can be more than two discrete levels, as shown in figure 15.33 for a diode clamped multilevel inverter model. In this way, the output quality is improved because both pulse width modulation and amplitude modulation can be used. The output pole is made from more than two series connected, clamped switches, so the total dc voltage rail can be the sum of the voltage rating of the individual switches. Very high output voltages can be achieved, where each device does not experience a voltage in excess of its individual rating. A multilevel inverter allows higher output voltages with low distortion (due to the use of both pulse width and amplitude modulation) and reduced output dv/dt. There are three main types of multilevel converters • Diode clamped • Flying capacitor, and • Cascaded H-bridge ½Vs

½Vs

½Vs Vs /N-1

½Vs a Vs

0 Va0

Vs /N-1

a

0 ½Vs

Va0

T5

-½Vs +½Vs

+½Vs t

+½Vs

+¼Vs

0V

0V

t

-½Vs

(a)

-¼Vs

(b)

(c)

-½Vs

Figure 15.33. One phase leg of a voltage-source bridge inverter with: (a) two levels; (b) three levels; and (c) N-levels, with N-1 capacitors and waveform for five levels.

CR CY

15.3.1 Diode clamped multilevel inverter

CB T4

T2

T6

(a)

IR

t

T3

Tupper

Tlower

Va0

Vs /N-1

-½Vs

-½Vs

a

0

-½Vs T1

702

+Io ωt

-Io (b)

Figure 15.32. Three-phase controlled-current sourced bridge inverter with alternative commutation current paths: (a) bridge circuit with a current source input and two extra thyristors and (b) load current waveform for one phase showing 180° conduction involving pwm switching.

Figure 15.33 shows the basic principle of the diode clamped (or neutral point clamped, NPC) multilevel inverter, where only one dc supply, Vs, is used and N is the number levels present in the output voltage between the leg output and the inverter negative terminal, Va-neg. The capacitors split the dc rail voltage into a number of lower voltage levels, each of which can be tapped and connected to the leg output through switches (and diodes). Only one string of series connected capacitors is necessary for any number of output phase legs. The number of levels in the line-to-line voltage waveform will be k = 2N −1 (15.76) while the number of levels in the line to load neutral of a star (wye) load will be p = 2k − 1 (15.77) The number of capacitors required, independent of the number of phase, is (15.78) N cap = N − 1 while the number of clamping diodes per phase is Dclamp = 2 ( N − 2 ) but ( N − 1)( N − 2 ) if rated at switch voltage The number of possible switch states is nstates = N phases and the number of switches (and inverse parallel diodes) in each leg is Sn = 2 ( N − 1)

(15.79) (15.80) (15.81)

Power Electronics

703

Chapter 15

The basic three-level inverter (±½Vs, 0) is shown in figure 15.34, along with the basic three-level voltage from the leg output to centre tap of the capacitor string, R (neutral point). When switch T1 is on, its complement T1′ is off, and visa versa. Similarly for the pair of switches T2 and T2′. Specifically T1 and T2 on give the output +½Vs, T1′ and T2′ on give the output -½Vs, and T2 and T1′ on give the output 0. Essential to attaining these output levels, are the clamping diodes Du and Dℓ. These two diodes clamp the outer switches to the capacitor string mid-point, which is half the dc rail voltage. In this way, no switch experiences a voltage in excess of half the dc rail voltage. Inner switches must be turned on (or off) before outer switches are turned on (or off). The five-level inverter uses four capacitors, and eight switches in each inverter leg. A set of clamping diodes (three in total for each leg) clamp the complementary switches in each leg. The output is characterised by having five levels, ±½Vs, ±¼ Vs, and zero. Some of the clamping diodes experience voltages in excess of that experienced by the main switches. Series connection of some of the clamping diodes avoids this limitation, but at the expense of increasing the number of clamping diodes from 2× (N-2) to (N-1)×(N-2) per phase. Thus, depending on the diode position in the structure, two diodes have blocking requirements of N −1− k VRB = Vs (15.82) N −1 where 1 ≤ k ≤ N-2. These diodes require series connection of diodes, if all devices in the structure are to support Vs /(N-1). For N > 2, capacitor imbalance occurs at high modulation indices. The general output voltage, to the centre of the capacitor string is given by V Van = s (T1 + T2 + .. .. + TN −1 − ½ ( N − 1)) (15.83) N −1 Common to all diode clamped inverter, each phase leg is identical in structure, and all legs share a common dc link capacitor string. Table 15.5 in combination with the six parts of figure 15.35, show the conducting devices for the six different output voltage and current combinations of the NPC inverter leg. The commercial inverter, HVDC Light, uses the NPC structure in figure 15.34, but uses extensive series connection of devices to achieve a high dc link voltage. The main problem in increasing the number of output voltage levels, other than increased circuit complexity, is voltage balancing the dc link series connected capacitors at higher modulation levels, M>½(N-1). This capacitor voltage balancing problem can be avoided when two multilevel inverters are used in an ac-dc-ac back to back converter arrangement, where the link capacitors are common to both converters.

Cu

T1 ½Vs


Table 15.5: Conduction paths in the diode clamped three-level inverter On switches

Vout

Active clamping diodes

T1 T2

T1 T2

Fig 15.35a

D1 D2

Fig 15.35d

none

0

T1 ′ T2

Dcu T2

Fig 15.35b

T1′ Dcℓ

Fig 15.35e

Dcu Dcℓ

-½ Vs

T1 ′ T2 ′

D1′ D2′

Fig 15.35c

T 1 ′ T2 ′

Fig 15.35f

none

+½Vs

D1

T2

D2

0 T1

′

D1

′

D2

T2

-½Vs iL > 0

+½Vs

′

T1

′

vo iL > 0

vo = ½Vs

T2

D2

T1

′

D1

′

D2

iL > 0

(a)

′

vo iL > 0

′

D1

T2

D2

T1

′

D1

′

D2

T2

-½Vs

vo = 0

vo i >0

iL > 0

′ L

′

vo = -½Vs (c)

+½Vs

′

′

T1

0

(b)

+½Vs

D2

D1

T2

-½Vs

+½Vs

′

T1

0

′

+½Vs

′

′

T1

D1

T1

D1

T1

D1

T2

D2

T2

D2

T2

D2

T1

′

D1

T1

′

D1

T1

′

D1

′

D2

′

D2

′

D2

0

T2

Output current and path + iL I - iL

½ Vs

D1

Dcu

704

′

vo iL < 0

0 ′

vo iL < 0

0 ′

vo iL < 0

Vs R

T2

-½Vs C Cℓ?

T1’

½Vs Dcℓ D c?

T2’

D1’

iL < 0

ia

0 -½Vs

vo = ½Vs

iL < 0

vo = 0 (e)

′

T2

-½Vs iL < 0

′

vo = -½Vs (f)

Figure 15.35. The six output voltage and current combinations for the NPC bridge inverter: (a), (b), (c) output current iL > 0; and (d), (e), (f) output current iL < 0.

ib

ic

b

+½Vs t

T2

-½Vs

(d)

D2’

neg

VaR

′

Vba a

o

c

Vao

Figure 15.34. Three-phase, voltage-source, three-level, diode-clamped (NPC) bridge inverter.

15.3.2 Flying capacitor multilevel inverter

One leg of a fly-capacitor clamped five-level voltage source inverter is shown in figure 15.36b, where capacitors are used to clamp the switch voltages to ¼Vs. The available output voltages are ±½Vs, ±¼Vs, and 0, where the output is connected to the dc link (Vs and 0) indirectly via capacitors. Figure 15.36 shows that in general, switches Tn and Tn+1 connect to capacitor Cn. The configuration offers more usable switch states than the clamped diode inverter, and this redundancy allows better, flexible control of capacitor voltages. For example, Table 15.5 shows that there are six states for obtaining 0V output, and four states for each of ±¼Vs. The output states ±½Vs do not involve the capacitors, hence they offer no redundant states. The basic switch restriction is that only one complementary switch (for example, T4 or T4′ ) is on at any time, so as to prevent shorting of a flying capacitor (e.g., T4 and T4′ would short C3).

Power Electronics

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The number of levels in the line-to-line voltage waveform will be k = 2N −1 (15.84) while the number of levels in the line to load neutral of a star (wye) load will be p = 2k − 1 (15.85) The number of capacitors required, which is dependent of the number of phase, is for each phase (15.86) N cap = ½ ( N − 1)( N − 2 )


Table 15.6: Five-level flying-capacitor inverter output states (phase A to R) mode

VAR

1

½Vs

2

The number of possible switch states is nstates = N phases and the number of switches in each leg is Sn = 2 ( N − 1)

(15.87)

¼Vs

N-1 states

(15.88)

The current output paths in Table 15.6 are made up by the series (and parallel) connection of the flying capacitors through the turn-on of the appropriate switches. Capacitors shown as negative are discharging in the formed path, while those shown as positive are charging. Use of the shown redundant states allows control to maintain the necessary voltage level on all the flying capacitors, while providing the desired output voltages. A feature of the flying capacitor multilevel inverter is its ride through capability due to the large capacitance used. On the other hand, the capacitors have a high voltage rating and suffer from high current ripple, since they conduct the full load current when connected into an active output voltage state. Capacitor initial charging is also problematic, especially given the capacitors for each leg, and between the different legs, are independent. If all the flying capacitors are voltage rated at the switch voltage level, then C2 comprises two series connect capacitors and C3 comprises three series capacitors, and all the same voltage rating as C1.

706

3 0

2

N -4N+1 states

4 -¼Vs

N-1 states

5

-½Vs

T1

switching states T2 T3 T4

C1

capacitors C2 C3

paths

1

1

1

1

=

=

=

½Vs

1

1

1

0

=

=

+

½Vs

-VC3

1

1

0

1

=

+

-

½Vs

-VC2+VC3

1

0

1

1

+

-

=

½Vs-VC1+VC2

0

1

1

1

-

=

=

-½Vs+VC1

1

1

0

0

=

+

=

½Vs

1

0

1

0

+

-

+

½Vs-VC1+VC2 -VC3

0

1

1

0

-

=

+

-½Vs+VC1-VC3

1

0

0

1

+

=

-

½Vs-VC1+-VC3

0

1

0

1

-

+

-

-½Vs+VC1-VC2+VC3

-VC2

0

0

1

1

=

-

=

-½Vs

1

0

0

0

+

=

=

½Vs-VC1

0

1

0

0

-

+

=

-½Vs+VC1-VC2

0

0

1

0

=

-

+

-½Vs

-VC2 -VC3

0

0

0

1

=

=

-

-½Vs

+VC3

0

0

0

0

=

=

=

-½Vs

+VC2

15.3.3 Cascaded H-bridge multilevel inverter

VC1 T1 D1

Vs

VC1

VCu

T1 D1

Cu C1

VCu

R

T2 D2

VC2

Cℓ C ?

Cu

T2 D2

T2?D2?

VCℓ

VC?

VC3

T1?D1?

T3 D3

phase a

The N-level cascaded H-bridge, multilevel inverter comprises ½(N-1) series connected single-phase Hbridges per phase, for which each H-bridge has its own isolated dc voltage source. For each bridge, as shown in table 15.7, three output voltages are possible, ±Vs, and zero, giving a total number of states of 3½( N −1) , where N is odd. Figure 15.37 shows one phase of a seven-level cascaded H-bridge inverter. The cascaded H-bridge multilevel inverter is based on multiple two level inverter outputs (each Hbridge), with the output of each phase shifted. Despite four diodes and switches, it achieves the greatest number of output voltage levels for the fewest switches. Its main limitation lies in the need for isolated power sources for each H-bridge and for each phase, although for VA compensation, capacitors replace the dc voltage supplies, and the necessary capacitor energy is only to replace losses due to inverter losses. Its modular structure of identical H-bridges is a positive design feature.

Vs C1 VCℓ V C?

C2

C3

T4 D4

R ¾Vs C Cℓ?

½Vs

¼Vs

phase a

(a)

′ D′4? T4?

The number of possible switch states is nstates = N phases and the number of switches in each leg is S n = 2 ( N − 1)

′ D′3? T3?

′ D′2? T2?

The number of levels in the line-to-line voltage waveform will be k = 2N −1 while the number of levels in the line to load neutral of a star (wye) load will be p = 2k − 1 The number of capacitors or isolated supplies required per phase is N cap = ½ ( N − 1)

(b)

′ D′1? T1?

Vs

Figure 15.36. One leg of a voltage-source: (a) three-level and (b) five-level, flying capacitor clamped bridge inverter.

On switches T2 T3

(15.90) (15.91) (15.92) (15.93)

Table 15.7: Three output states of H-bridges and their current paths. Vℓ

(15.89)

Bidirectional current paths + iL - iL T2 T3 D2 D3

0

none

D4 D1

D2 D3

-Vs

T1 T4

T1 T4

D2 D3

Power Electronics

707

Vs

Chapter 15

D2 T2

T1 D1 V1

D4 T4

T3 D3


1. For voltage level Vxo = ½Vdc, turn on all the upper main switches (Sy1 and Sy2) and all the lower auxiliary switches (Sx3 and Sx4). 2. For voltage level Vxo = 0, there are four different switch combinations: a) Turn on Sy1, Sy3, Sx2 and Sx4. b) Turn on Sy2, Sy3, Sx1 and Sx4. c) Turn on Sy2, Sy4, Sx1 and Sx3. d) Turn on Sy1, Sy4, Sx2 and Sx3. 3. For voltage level Vxo = -½Vdc, turn on all the upper auxiliary switches (Sx1 and Sx2) and all the lower main switches (Sy3 and Sx4).

Dc Vs

D2 T2

T1 D1

Vs

D4 T4

T1 D1

D2 T2

Io

Sc

+ Vdc

V1 T3 D3

708

C

State (0,0)

Sm

Vo

Dm

State (1,0)

State (0,1)

V1 T3 D3

D4 T4

Icell > 0

Sa1

Da1

Sa2

Figure 15.37. One leg of a voltage-source, seven-level, cascaded H-bridge inverter.

15.3.4 Capacitor clamped multilevel inverter The capacitor-clamped multilevel inverter has several advantages compared to conventional multilevel inverters, such as: modular construction; can be extended to any number levels; capacitor voltage balance is attainable for any number of voltage levels; for a large number of voltage levels extremely low total harmonic distortion can be achieved without the need for filters. In addition, to reduced voltage stress on switching device dv/dt; and it has failure management capability in the case of device failures. Figure 15.38 shows one cell of a capacitor-clamped multilevel converter, when the switching device Sm is turned on and Sc is turned off, the voltage Vo = 0; when the switching device Sm is turned off and Sc is turned on, the voltage Vo = Vdc. Table 15.8 and figure 15.38b summarizes the switching states of a cell shown in Fig. 15.38 and their influence in capacitor voltage. Switches Sm and Sc are complementary, when any one of them is on. Figure 15.39 shows one-phase of the three-level capacitor-clamped inverter in which each voltage level can be synthesized by turning four switching devices simultaneously; in each instant two switches must belong to (Sy1, Sy2, Sy3 and Sy4) and the remaining two from auxiliary switches (Sx1, Sx2, Sx3 and Sx4). There are four complementary switch pairs in each phase, turning on one of the pair switches will excluded the other from being turned on. The four complementary switches are (Sy1, Sx1), (Sy2, Sx2), (Sy3, Sx3) and (Sy4, Sx4). For a dc bus of Vdc, the voltage across each cell capacitor is ½Vdc and each switching device voltage stress is limited to one capacitor voltage. For an n-level converter, the voltage across each capacitor and switching device is limited to Vdc /(n-1) while the number of switching devices (IGBT plus free wheeling diode) required per phase is doubled that for multipoint clamped converters. The number of capacitors required for three-phases is 6n-6 (2n-2 per phase), while no clamping diodes are required. To explain how the multilevel waveform voltage is synthesized, the supply mid point is assumed the output voltage reference. Using the three-level converter circuit shown in Figure 15.39 as an example, there are six switching combinations to synthesize three-level voltages between x and o.

Sa1

Sa2

Da2

Sa1 off Sa2 off Icell < 0

Sa1

Da1

Sa2

Da1

+

Sa1

Sa2

Da2

Sa1 on Sa2 off Sa1

+ Sa2

Da2

Da1

Da1

+

+

Da2

Sa1 off Sa2 on Sa1

+ Sa2

Da2

Da1

+

Da2

Figure 15.38. Structure of one cell in capacitor-clamped multilevel converter and its current direction dependant conduction states.

Table 15.8: Switching states of one cell Sm

Sc

Vo

Current direction

Power path

ON

OFF

0

io > 0

Sm

Capacitor state unchanged

ON

OFF

0

io < 0

Dm

unchanged

OFF

ON

Vdc

io > 0

Dc

charging

OFF

ON

Vdc

io < 0

Sc

discharging

Power Electronics

709

Chapter 15


710

Table 15.10: Multilevel inverter component count, per phase Dx1

+ ½Vdc

+

C1

Sx1

Dy1

Dx2

+ C2

+ ½Vdc

+

C3

Sy3

Dy3

C4

N

2N-1

4N-3

2(N-1)

(N-1)(N-2)

0

(N-1)

0

0

flying capacitor

N

2N-1

4N-3

2(N-1)

0

½(N-1)(N-2)

(N-1)

0

yes

N (odd)

2N-1

4N-3

2(N-1)

0

0

½ (N-1)*

½(N-1)*

n/a

N

2N-1

4N-3

2(N-1)

0

0

2(N-1)

0

yes

Sx4

diodes

Various sinusoidal pwm techniques were considered in sections 15.1.3v and 15.1.3vi of this chapter. Figure 15.40 shows how a triangular carrier is associate with each complementary switch pair, four carriers (N-1) for the five-level inverter as illustrated. The parts of figure 15.40 show how the four individual carriers can be displaced with respect to one another. The figure also shows how triplen injection is incorporated. The appropriate five-level switch states, as in tables 15.4 to 15.6, can be used to decode the necessary switching sequences. To minimise losses, switching is restricted to only occur between adjacent levels.

Dx4

+

diode clamped

15.3.4i - Multiple offset triangular carriers

Vyo

½Vdc

½Vdc

Outer hex redundant states

Two basic approaches can be used to generate the necessary pwm signals for multilevel inverters. Each approach is based on the extension of a two level equivalent. • Modulating waveform comparison with offset triangular carriers • Space vector modulation based on a rotating vector in multilevel space

L

Sx3

isolated supplies

15.3.5 PWM for multilevel inverters

Iy

L

Dx3

level capacitors

Dy2

y

0

flying capacitors

VA-N

capacitor clamped

Sy2

diodes clamping

& //

VA-B

cascade Sx2

switches

VA-0V

* either /or

Sy1

½Vdc

½Vdc

levels

Inverter type

Sy4

Dy4

1.5

Figure 15.39. Schematic for one-leg of a three-level capacitor-clamped multilevel inverter.

1

½Vs

π 0.5

0

Voltage(pu)

Table 15.9 lists the voltage levels and their corresponding switch states. State condition 1 means the switch is on, and 0 means the switch is off. In order to maintain equal voltage stressing on the switching devices, the voltage across each cell capacitor must be maintained at ½Vdc.

¼Vs

0 0

π -0.5

-¼Vs

0 -1

-½Vs

Table 15.9: Switching combinations for three-level capacitor-clamped converter

-1.5

1 0

0.002

0.004

0.006

0.008

0.01 t(s)

0.012

0.014

0.016

0.018

0.02

1.5

½Vdc

0

switch states Sy1

Sy2

Sy3

Sy4

Sx1

Sx2

Sx3

Sx4

1

1

0

0

0

0

1

1

1

0

1

0

0

1

0

1

0 0.5

(a)

0

1

1

0

1

0

0

1

(b)

0

1

0

1

1

0

1

0

(c) (d)

1

0

0

1

0

1

1

0

0

0

1

1

1

1

0

0

0

0

0

π -0.5

π

-½

-1

-1.5

½Vdc

½

1

Voltage(pu)

output voltage Vxo

0

0.002

0.004

0.006

0.008

0.01 t(s)

0.012

0.014

0.016

0.018

0.02

-1

1.5

1

0 0.5

Voltage(pu)

Multilevel topology comparison A comparison between the three basic multilevel inverters is possible from the numerical summary of component numbers for each inverter, as in Table 15.10. The diode clamped inverter requires many clamping diodes; the flying capacitor inverter requires many independent capacitors; while the cascaded inverter requires many isolated dc voltage power supplies.

0 0

0 -0.5

0 -1

-1.5

0

0.002

0.004

0.006

0.008

0.01 t(s)

0.012

0.014

0.016

0.018

0.02

Figure 15.40. Multi-carrier based pwm generation for a voltage-source, 5-level, inverter.

Power Electronics

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Chapter 15

15.3.4ii - Multilevel rotating voltage space vector

Space vector modulation for the two-level inverter was considered in section 15.1.3vi of this chapter. The basic hexagon shape for two levels is extended to higher levels as shown in figure 15.41, for three levels. The number of triangles, vectors, and states increases rapidly as the level number increases. Table 15.11: Properties of N-level vector spaces levels

states

triangles

vectors

N

N3

6(N-1)2

3N(N-1)+1

vectors in each hexagon

2

8

6

7

(1+6)

3

27

24

19

(1+6)+12

5

125

96

61

(1+6)+12+18+24

The 2-level inverter The zero state matrix is [000 111] The first and only hexagon is shown in figure 15.23a. [100 110 010 011 001 101] The three level inverter The zero state matrix is [000 111 222] The first hexagon matrix is 100 110 010 011 001 101   211 221 121 122 112 212    The second hexagon matrix is [ 200 210 220 120 020 021 022 012 002 102 202 201]

120

010 121

021

000 111 222

011 122

022

001 112

012

002

β

parallelogram

V3

α 201

JG

p2

parallelogram

V

JG

JG

JG

V4

p1

JG

V2

JG

p1 JG

JG

V1

V1 α

)

(

)

(

)

(

)

Reversible dc link converters

15.4.1 Independent control

202

102

β

V

JG JG

101 212

200

JG

JG

V2 p2

210 100 211

(

Power inversion by phase angle control is attained with a fully controlled single-phase converter as discussed in section 12.2.3. Power regeneration is also possible with the fully controlled three-phase converter shown in figure 12.11. If a fully controlled converter supplies a dc machine, two-quadrant control is possible (QI and QIV), motoring in one direction of rotation and generating in the other direction. Power regeneration into the supply is achieved by reversing the dc output voltage by controlling the converter phase delay angle. The converter current is uni-directional, that is, the converter output current can not reverse. The dual or double converter circuit in figure 15.42a and b will accommodate four-quadrant dc machine operation, where the circuit performs as two fully controlled converters in anti-parallel. Each converter is able to rectify and invert, but because of their inverse parallel connection, one converter (the positive converter P) operates in quadrants QI and QIV, while the other (the negative converter N) operates in quadrants QII and QIII, as shown in figure 15.43. The two converters can be operated synchronously, called simultaneous control or independently where one is always blocking, called independent control.

220 110 221

A 0  represents the minimum voltage obtainable from the multilevel converter and N-1 represents the maximum value. For example, in a two-level converter, 0  is equivalent to 0V and 1  is equivalent to Vs, where Vs is the converter DC link voltage. In a three-level converter 0  is equivalent to -½Vs, 1  is equivalent to 0 V, and ‘2’ is equivalent to ½Vs where Vs is the dc link voltage of the multilevel converter. When the rotating vector is drawn in the vector space, it is decomposed into vectors bordering the triangle it lies in. When operating in the outer hexagon, the vectors states used in the inner most hexagon mean that that level of the converter is operating with a six-step quasi-square output voltage waveform, to which is added a modulated square waveform for the next higher level.

15.4

β 020

712

Generally, the rotating vector can lay in one of two triangles of any parallelogram. Once the parallelogram has been uniquely decoded, for the triangle nearer the origin: JG JG JG JG JG JG JG JG JG V = p1 V 1 −V 3 + p 2 V 2 −V 3 +V 3 = p1V 1 + p 2V 2 + (1 − p1 − p 2 )V 3 (15.94) JG JG JG = p 1 + p 2 +V 3 while for the triangle further from the origin: JG JG JG JG JG JG JG JG JG V = p1 V 1 −V 4 + p 2 V 2 −V 4 +V 4 = p1V 1 + p 2V 2 + (1 − p1 − p 2 )V 4 (15.95) JG JG JG = p 1 + p 2 +V 4 where p1 and p2 are the relative duration lengths of the active vectors V1 and V2. The zero vectors, V3 and V4, constitute the remaining time in the carrier period not assigned to the V1 and V2 associated duration components. The periods associated with p1V1 and p2V2 are distributed within the carrier period as for to level SVM in section 15.1.3vii-2. Since SVM decomposes a single rotating vector into three identical components displaced by 120°, such a modulation strategy may not be applicable to any inverter used for FACTS type applications since phases may be unbalanced, distorted or phase shifted.

From Table 15.11, the states for the two and three level inverters can be specified as follows.

These pole states are shown figure 15.41.


α

Figure 15.41. Rotating voltage space vector approached applied to three phases of a voltage-source three-level, inverter and decomposition of the vector in a given parallelogram.

Simultaneous converter control can be used if continuous load current can be guaranteed. Otherwise only one converter, depending on the quadrant, need operate at anyone time (the other is in a blocking state), as shown in figure 15.42a. No circulating currents arise due to possible mismatched N and P converter output voltages. The continuous current condition may be difficult to ensure at light load levels. Additional series armature inductance, L in figure 15.42a and b, helps with current smoothing and ensuring continuous machine current. A machine rotational direction change is affected by the following converter operating procedure. • Initially the motor is operating in quadrant I, with 0° ≤ α1 ≤ 90° for the positive converter P. The negative converter, N, is in the fully blocking state, with all thyristors turned off. • The positive converter is put into the inverting mode with 90° ≤ α1 ≤ 180°, changing the average output voltage from positive to negative. The machine current rapidly falls to zero. The machine rotational speed slows, the rate depending on the load inertia. • After a dead time, the positive converter blocks and the negative converter N starts in a motor braking mode in quadrant II. The motor speed falls rapidly to zero. • The second converter operates in quadrant III and rapidly accelerates the motor in the opposite direction, with 0° ≤ α2 ≤ 90°.

Power Electronics

713

Chapter 15


714

sp eed vo

α1

Ia

Ia

L

+

N

α2

P

E

(a )

α1

+ E

vo

vo

α2 P

N d c lin k

α1

L N

α2

rege nera tive brak in g /in vers io n

II

I

m o to r/rectification

to rq u e

m o to r/rectification

III

IV

rege nera tive brak in g /in versio n

Ia

Ia

(b )

E

α2 P

P

+

vo

Ia

α1

E

vo

+

N Figure 15.43. Four quadrants of reversible converter operation.

α1

15.4.2 Simultaneous control

α2

(c )

P

N (d ) d c lin k

in p u t L -C filte r

o u tp u t filte r re ctifier/ co n ve rter

3Φ in p u t

in verte r

3Φ o u tp u t

½L

Figure 15.42. Reversible converter allowing four-quadrant control of: (a) a dc machine with independent converters; (b) a dc machine with simultaneously controlled converters; and (c) voltage and (d) current fed induction machine.

The dead time before turning on the negative converter N is to ensure the positive converter P is fully off, otherwise the three-phase input voltage lines may short through the two converters. Such a current condition cannot be controlled with line-commutated thyristors. Operation is characterised by transitions from QI to QII to QIII for reversal, and transitions from QIII to QIV to QI for returning to the original direction of rotation.

Simultaneous converter control, also called circulating current control, functions with both converters always in operation which gives a faster dynamic response than when the converters are used mutually exclusively. To avoid supply short circuits requires that the output voltage of both converters (rectifier Vr and inverter Vi) be the same in order to minimise circulating currents. Vr + Vi = 0 V cos α1 + V cos α 2 = 0 (15.96) cos α1 + cos α 2 = 0 that is α1 + α 2 = 180° Equation (15.96) implies that both converters operate with firing angles that sum to 180°. Each converter produces the opposite polarity output voltage, which is cancelled by reversing the relative output connections. Under such conditions the load current can be maintained continuous. To minimize any circulating current due to ripple voltage produced by instantaneous voltage differences between the two converters, inductance is usually inserted between each converter and the dc machine load, as shown in figure 15.42b. Adversely the cost and weight are increased, and the supply power factor and drive efficiency are decreased, compared to that obtained with independently controlled converters.

A machine rotational direction change is affected by the following converter operating procedure. • Initially the motor is operating in quadrant I for the rectifying, positive converter, with 0° ≤ α1 ≤ 90°. The other converter is operating in the inverting mode with 90° ≤ α2 ≤ 180°, such that α1 + α2 = 180°. The output voltage for both converters is the same, and the negative converter N carries only the circulating current. • For rotational direction reversal, α1 ≥ 90° and α2 ≤ 90°, such that α1 + α2 = 180°. The armature back emf voltage now exceeds the converter output voltages, and current diverts to the negative converter N and the machine regeneratively brakes, operating in quadrant II. The current rapidly falls to zero and the positive converter P carries only the ac circulating current. • The speed rapidly falls to zero, with α1 = α2 = 90° giving zero output voltage, so as to control the armature current since the back emf is zero. Then with α2 < 90° the machine rapidly accelerates in quadrant III, in the reverse direction to the original rotation. For reversing the direction of rotation from Q III the operation sequence is QIII to QIV to QI. Since no converter dead time is introduced, a fast dynamic response can be attained. A small dc circulating current is deliberately maintained, that is greater in magnitude than the peak of the ac ripple current. The ac current can then flow continuously in both converters, both of which can operate in the continuous conduction mode without the need for continuous converter current reversal operation.

Power Electronics

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Chapter 15

DC to AC Inverters – Switched Mode ½ wave rectifier

15.4.3 Inverter regeneration The bridge freewheel diodes of a three-phase inverter restrict the dc rail or dc link voltage from reversing. The dual or double converter circuit in figure 15.42c will allow inversion with a three-phase voltage source inverter. One converter rectifies, the other converter inverts, functioning as a selfcommutated inverter, transferring power from the dc link to the ac supply. Complete four-quadrant control of the three-phase ac machine on the inverter is achieved in conjunction with control of the dc to ac inverter. That is, motor reversal is achieved by effectively interchanging the pwm control signals associated with two phases. The real power flow back into the ac supply is controlled by the converter phase delay angle, while the reactive power flow is controlled by the voltage magnitude. The angle and voltage are not independent. In the case of a pwm controlled inverter fed ac machine, the ac to dc converter can be uncontrolled, using all diodes, since dc output voltage reversal is not utilised. Figure 15.42d shows a fully reversible current controlled converter/inverter configuration, using selfcommutating devices. The use of self-commutated switches (rather than mains commutated converter thyristors) offers the possibility to minimise the input current distortion and to reduce the inductor size hence improve the dynamic current response. The switch series diodes are essential since the shown IGBTs have no useable reverse blocking capability. The use of reverse blocking GCTs avoids the need for the series blocking diodes, which reduces the on-state voltage losses but increases gate drive complexity and power rating. Series connection of devices is necessary above a few kV, and above 1 MVA the GCT dominates. 15.5

+

DR ac

+

boost converter

+

L

H-bridge inverter

V

L-C filter

+

T3

D

DB

+

716

+

T

+

C

+

-

T1

D1

D3

Lo Co

N

N V

-

T

-

C

+

-

D4

D2

o/p

T2

-

DB

DR

T4

L

D

-

Figure 15.44. Single-phase uninterruptible power supply.

Standby inverters and uninterruptible power supplies

Standby inverters and uninterruptible power supplies (UPS’s) provide a 50/60 Hz supply in the event of an ac mains failure. A UPS must provide ac output such that mains failure is undetected by the load. To achieve this, a UPS continually feeds the load from an inverter. A load that can tolerate a short interruption of the ac supply is fed from a standby inverter which becomes operational within 1-5 ms after the ac supply failure. In communications, computing, and automated production lines, UPS’s are essential for even brownouts (V and f outwith bounds for reliable equipment operation), while in lighting and heating applications, standby inverters are used since a few missing ac cycles (due to a blackout – total interruption of the mains power) may be tolerated. In each power supply case, the alternative energy source is a standby dc battery. The UPS keeps the battery charged when the ac input is supplying the output power.

DB

15.5.1 Single-phase UPS A basic single-phase UPS is shown in figure 15.44. A key safety objective is to retain the supply neutral at both the supply input and the ac output, without resorting to any from of isolating transformer. Consequently, the input ac mains is half-wave rectified by diodes DR+ and DR− . Boost converters on the positive and negative groups ensure supply sinusoidal input current and unity power factor. The output H-bridge (T1-T4) uses pwm and feedback control to produce a fixed frequency and magnitude output (and ac mains phase synchronisation if required), which is filtered by an L-C filter. In the event of a loss of the ac supply, the backup batteries, V+ and V -, provide energy to the boost converters, hence to the output inverter. The battery backup voltage magnitude is much less than the ac supply magnitude and diodes, DB+ and DB− , isolate the batteries from the rectified ac supply voltage. The shown UPS has two basic limitations that manufactures strive to overt. • •

If the battery is to be connected to neutral, then two batteries are necessary. Proprietary attempts using only one battery involve circuit complications and limitations. At best, with one battery, it is one forward biased diode voltage drop from neutral. Because the batteries supplies are not isolated during normal operation, during part of the mains cycle near zero voltage, the batteries alternately provide energy. This decreases their lifetime and necessitates more complicated trickle charge circuits. The input current is also distorted at the 0V crossover. Replacement of the blocking diodes DB by switches involves complexity and battery backup operation requires detection and is not fail safe.

Figure 15.45. Three-phase uninterruptible power supply.

15.5.2 Three-phase UPS Figure 15.45 shows a basic three-phase UPS, used up to a few tens of kilowatts. The ac supply is rectified and filtered. A forward converter controls the dc link voltage to just above the battery voltage level. This dc voltage is boosted to a dc level such that after inversion it provides the required output voltage magnitude. If the input ac fails or droops, the dc link power is provided by the battery via diode DB. The output inverter is usually operational in a pwm mode, which allows precise frequency control, voltage control, ac mains phase synchronisation, and minimisation of low frequency output harmonics. With pwm control minimal filtering is required, which minimises the filter weight, cost, size, and losses. A three-phase UPS can utilise third harmonic injection (15.1.4(iv)). A three-phase boost input converter can be used to maintain sinusoidal ac supply input currents at unity power factor.

Power Electronics

717

15.6

Power filters

Chapter 15

The simplest design approach is to assume a non-load condition, ZL → ∞, whence the filter cut-off frequency is f o = 1/ 2π LC . Frequency components below fo, including dc, are passed. Those components above fo are attenuated by a second order fall-off in gain. Any frequency components inadvertently around the resonant frequency, fo, will be amplified. For this reason, the filter may be damped with parallel connected R-C snubbers.

(

With the aid of figure 15.11 determine the line-to-neutral and line-to-line output voltage of a dc to three-phase inverter employing 120° device conduction. Calculate the interphase: i. mean half-cycle voltage ii. rms voltage iii. rms voltage of the fundamental.

15.5.

The three-phase inverter bridge in figure 15.4 has a 600V dc rail and a 10Ω per phase load. For 180° and 120° conduction calculate: i. the rms phase current ii. the power delivered to the load iii. the switch rms current. [24.5 A, 18 kW, 17.3 A; 28.3 A, 24 kW, 14.15 A]

15.6

A single-phase square-wave inverter is supplied from a 340V dc source and the load is a 17Ω resistor. Determine switch average and rms current ratings. What power is delivered to the load?

15.7

A single-phase square-wave inverter is supplied from a 340V dc source and the series R-L load is a 20Ω resistor and L=20mH. Determine: i. an expression for the load current, hence the maximum switch current ii. rms load current iii. average and rms switch current iv. maximum switch voltage v. average source current, hence power delivered to the load vi. load current total harmonic distortion.

)

Reading list

See chapter 11 reading list. Hart, D.W., Introduction to Power Electronics, Prentice-Hall, Inc, 1994. Mohan, N., Power Electronics, 3rd Edition, Wiley International, 2003.

Problems

15.1.

The inverter in figure 15.7 is supplied from a 340 V dc source. The load has a resistance of 10Ω and an inductance of 10mH. The basic operating frequency is 50 Hz, with three notches per half cycle giving half the maximum output, similar to that shown in figure 15.13. Determine the load current waveform over the first two cycles and determine the power delivered to the load based on the current waveform of the final half cycle.

15.2.

The inverter and load in problem 15.1 are controlled so as to eliminate the third and fifth harmonics in the output voltage. Determine the load current waveform over the first two cycles and the power delivered to the load based on the current waveform of the last half cycle.

15.3.

Output voltage harmonic reduction can be achieved by employing multiphase, selected notching modulation control on a three-phase bridge as discussed in 15.1.4. An output as in figure 15.14b with α1 = 16.3° and β1 = 22.1° eliminates the 5 th and 7 th harmonics. Determine the fundamental voltage output component and compare it with that of a square wave. Determine the output rms voltage.

718

15.4.

Power L-C filters are used to reduce harmonics or ripple from • the rectifier output (dc filter) • the inverter output (ac filter). L-C low-pass, second-order filters are shown in figures 15.42, 15.44, and 15.45. In figure 15.45, the L-C smoothing filter at the rectifier output, filters the ac mains frequency components leaving dc. The same type of filter is used in the inverter output to filter pwm harmonics, leaving the relative low frequency modulation frequency. The L-C filter fundamental cut-off frequency is dependent on L, C, and the load impedance ZL vo 1 1 = = (15.97) vi 1 + jω L ( Z1L + jωC ) 1 − ω 2 LC + j ωZ LL


Chapter 16

16 DC to AC Inverters – Resonant Mode Inversion (in this chapter) is the conversion of dc power to ac power at a desired output voltage or current and frequency. A static semiconductor inverter circuit performs this electrical energy inverting transformation. The terms voltage-source and current-source are used in connection with the output from inverter circuits. A voltage-source inverter (VSI) is one in which the dc input voltage is essentially constant and independent of the load current drawn. The inverter specifies the load voltage while the drawn current shape, near sinusoidal, is dictated by the series resonant load, in this case. A current-source inverter (CSI) is one in which the source, hence the load current is predetermined and the load impedance, a parallel resonant circuit in this case, determines the, near sinusoidal output voltage. The supply current cannot change quickly. This current is controlled by series dc supply inductance which prevents sudden changes in current. Being a current source, the inverter can survive an output short circuit thereby offering fault ride-through properties. Inverter switching losses (either turn-on or turn-off) can be significantly reduced if zero current or voltage switching can be utilised. This switching loss reduction allows higher operating frequencies hence smaller L and C components (in size, weight, and value). Also radiated switching noise is significantly reduced. Two main techniques can be used to achieve near zero switching losses a resonant load that provides natural voltage or current zero instances for switching a resonant circuit across the switch which feeds energy to the load as well as introducing zero current or voltage instances for switching. The inverter and its output are single-phase and the output is controlled around the load resonant frequency. Zero current, ZCS, and zero voltage, ZVS, switching occurs when the inverter switches are operated either side of resonance. 16.1

Resonant dc-ac inverters

The voltage source inverters considered in 15.1 involve inductive loads and the use of switches that are hard switched. That is, the switches experience simultaneous maximum voltage and current during turn-on and turn-off with an inductive load. The current source inverters considered in 15.2 required capacitive circuits to commutate the bridge switches. When self-commutatable devices are used in current source inverters, hard switching occurs. In resonant inverters, the load enables commutation of the bridge switches with near zero voltage or current switch conditions, resulting in low switching losses. A characteristic of L-C-R resonant circuits is that at regular, definable instants for a step load voltage, the series L-C-R load current sinusoidally reverses or for a step load current, the parallel L-C-R load voltage sinusoidally reverses. If the load can be resonated, as considered in chapter 6.2.3, then switching stresses can be significantly reduced for a given power through put, provided switching is synchronised to the V or I zero crossing. Three types of resonant converters utilise zero voltage or zero current switching. load-resonant converters resonant-switch dc-to-dc converters resonant dc link and forced commutated converters

BWW

DC to AC Inverters – Resonant Mode

720

The single-phase load-resonant converter, which is extensively used in induction heating applications, is presented and analysed in this chapter. Such resonant load converters use an L-C load which oscillates, thereby providing load zero current or voltage intervals at which the converter switches can be commutated with minimal electrical stress. Resonant switch dc-to-dc converters are presented in chapter 18. Two basic resonant-load single-phase inverters are used, depending on the L-C load arrangement: current source inverter with a parallel L-C resonant (tank) load circuit: switch turn-off at zero load voltage instants and turn-on with zero voltage switch overlap is essential (a continuous source current path is required) voltage source inverter with a series connected L-C resonant load: switch turn-off at zero load current instants and turn-on with zero current switch under lap is essential (to avoid dc voltage source short circuiting) Each load circuit type can be fed from a single leg (or arm) circuit or H-bridge circuit depending on the load Q factor. This classification is divided according to symmetrical full bridge for low Q load circuits (class D) single bridge leg circuit for a high Q load circuit (class E) High Q circuits can also use a full bridge inverter configuration, if desired, for higher through-put power. In induction heating applications, the resistive part of the resonant load, called the work-piece, is the active load to be heated - melted, where the heating load is usually transformer coupled. Energy transfer control complication is usually associated with the fact that the resistance of the load work-piece changes as it heats up and melts, since resistivity is temperature dependant. However, control is essentially independent of the voltage and current levels and is related to the resonant frequency which is L and C dependant. Inverter bridge operation is near the load resonant frequency so that the output waveform is essentially sinusoidal. By ensuring operation is below the resonant frequency, such that the load is capacitive, the resultant leading current can be used to self commutate thyristor converters which may be used in high power series resonant circuits. This same capacitive load commutation effect is obtained for parallel resonant circuits with thyristor current source inverters operating just above resonance. The output power is controlled by controlling the converter output frequency, with maximum power being transferred at the resonant frequency.

16.2

L-C resonant circuits

L-C-R resonant circuits, whether parallel or series connected are characterised by the load impedance being capacitive at low frequency and inductive at high frequency for the series circuit, and vice versa for the parallel case. The transition frequency between being capacitive and inductive is the resonant frequency, ωo, at which frequency the L-C-R load circuit appears purely resistive and maximum power is transferred to the load, R. L-C-R circuits are classified according to circuit quality factor Q, resonant frequency, ωo, and bandwidth, BW, for both parallel and series circuits. The characteristics for the parallel and series resonant circuits are related since every practical series L-C-R circuit has a parallel equivalent, and vice versa. The parallel circuit can be series R-L in parallel with the capacitor C. As shown in figure 16.1 each resonant half cycle is characterised by the series resonant circuit current is zero at maximum capacitor stored energy the parallel resonant circuit voltage is zero at maximum inductor stored energy The capacitor in a series resonant circuit must have an external path through which to release its stored energy. The parallel resonant circuit can release its stored inductive energy within its parallel circuit, without an external circuit. The stored energy can internally resonate, transferring energy back and forth between the L and C, gradually dissipating energy in the circuit R, as heat. 16.2.1 - Series resonant L-C-R circuit The series L-C-R circuit current for a step input voltage Vs, with initial capacitor voltage vo and series inductor current io is given by V −v ω i (ωt ) = s o × e −α t × sin ωt + io × e −α t × o × cos (ωt + φ ) (16.1) ω ωL where 1 R 1 R ω 2 = ωo2 (1 − ξ 2 ) = ωo2 − α 2 ωo = α= =ξ = and tan φ = α ω 2L 2Qs 2ωo L LC ξ is the damping factor. The capacitor voltage is important because it specifies the energy retained in the L-C-R circuit at the end of each half cycle. ω i vc (ωt ) = Vs − (Vs − vo ) o e −αt cos (ωt − φ ) + o e −α t sin ω t (16.2) ω ωC

Power Electronics

721

Chapter 16

jωL

Is

low Q

Vs

Table 16.1: Characteristics and parameters of parallel and series resonant circuits

Is

characteristic

vcapacitor

iinductor

vparallel

ωt

ideal commutation

instants

instants

∞

|Z(ω)| R

Qs

→

BWs

√2

∞

+90°

θZ(ω) Z

capacitive

θZ(ω) 0

ωo

ωu

s

Resonant angular frequency

rad/s

Damping factor

pu

Damping constant

/s

Characteristic impedance

Ω

ωo = 2π f o = ξs = ½

→

ω=2πf

ωℓ

ωu ωo

ω=2πf Z capacitive

Qs =

Quality factor 1 Qs =

pu

Qp

=

-90°

-90° (a)

(b)

Bandwidth

rad/s

Figure 16.1. Resonant circuits, step response, and frequency characteristics: (a) series L-C-R circuit and (b) parallel L-C-R circuit.

At the series circuit resonance frequency ωo, the lowest possible circuit impedance results, Z = R as shown in figure 16.1a, hence it can be termed, low-impedance resonance. The series circuit quality factor or figure of merit, Qs, is defined by reactive power 2π × maximum stored energy Qs = = average power energy dissipated per cycle (16.3) 2 ωo L 1 Z o 2π ½ Li = = = = 2 R R ½ Ri / f o 2ξ where the characteristic impedance is L (Ω) Zo = C The series circuit half-power bandwidth BWs is given by ω 2π f o BWs = o = Qs Qs and upper and lower half-power frequencies are related by ωo = ωA ωu .

(16.4)

=

R

1

=

(½RI ) τ 2

p

ωo Qs

1 2CR

L 1 = ωo L = C ωo C

L ωL C = o R R 2π (½LI p2 )

BW s =

ωo L 1 =½ R ωo C R

αp =

Z 1 = o = R 2ξs

ωo CR

1

LC

ξp = ½

ω = ωo 1 − ξ p2

ω = ωo 1 − ξs2

Z inductive

1

τ

2L

Zo =

rad/s

ω = ωo 1 − ξ 2 = ωo2 − α 2

R = ½ ωo C R ωo L

αs =

Damped resonant angular frequency

Qp

decreasing

BWp

parallel

τ = LC

Resonant period/time constant

0

Z inductive

ωℓ

1 1 √2 +90°

series

ωt

ideal commutation

decreasing

0

Figure 16.1a shows the time-domain step-response of the series L-C-R circuit for a high Q load and a lower Q case. In the lower Q case, to maintain and transfer sufficient energy to the load R, the circuit requires re-enforcement every half sine cycle, while with a high circuit Q, re-enforcement is only necessary once per sinusoidal cycle. Thus for a high circuit Q, full bridge excitation is not essential, yielding a simpler power circuit as shown in figure 16.2a and b.

high Q low Q

(16.5)

R 4π L

v

R

−j ωC

high Q

1

f Au = f o ±

jωL

Is

R

iseries

722

ωAu = ωo ± α i

Vs

|Z(ω)| R


−j ωC

Qp =

R 1 R = = = ωo CR L 2ξ p Z o C

2π (½CV p2 ) R = =  V p2  ωo L  ½  τ  R 

BW p =

ωo Qp

The energy transferred to the load resistance R, per half cycle 1/2fr, is π

W½ = ∫ i (ω t ) R d ω t 2

0

The active power transferred to the load depends on the repetition rate of the excitation, fr. P = W½ × f r (W)

(16.6) (16.7)

16.2.2 - Parallel resonant L-C-R circuit The load for the parallel case is a parallel L-C circuit, where the active load is represented by series resistance in the inductive path. For analysis, the series L-R circuit is converted into its parallel R-L equivalent circuit, thus forming the equivalent parallel L-C-R circuit shown in figure 16.1b. A parallel resonant circuit is used in conjunction with a current source inverter, thus the parallel circuit is excited with a step input current. The voltage across a parallel L-C-R circuit for a step input current Is, with initial capacitor voltage vo and initial inductor current io is given by I −i ω v (ωt ) = vc (ωt ) = s o × e −α t × sin ωt + vco × e −αt × ωo × cos (ωt + φ ) (16.8) ωC

Chapter 16

The inductor current is important since it specifies the tank circuit stored energy at the end of each half cycle. ω v iL (ωt ) = I s − ( I s − io ) × o × e −αt × cos (ωt − φ ) + o × e −α t × sin ωt (16.9) ω ωL where 1 α= 2CR The parallel circuit Q for a parallel resonant circuit is 2π ½Cv 2 R R 1 = ωo RC = = = (16.10) Qp = ½v 2 / R f o ωo L Z o Qs where Zo and ωo are defined as in equations (16.1) and (16.3), except L, C, and R refer to the parallel circuit values. The half-power bandwidth BWp is given by ω 2π f o BWp = o = (16.11) Qp Qp and upper and lower half power frequencies are related by ωo = ωAωu . At the parallel circuit resonance frequency ωo, the highest possible circuit impedance results, Z = R as shown in figure 16.1b, hence it can be termed, high-impedance resonance. The energy transferred to the load resistance R, per half cycle 1/2fr, is π

W½ = ∫ v (ω t ) / R d ω t 2

16.3


724

Series-resonant voltage-source inverters

Series resonant circuits use a voltage source inverter (class D series) as considered in 16.1.1 and shown in figure 16.3a and b. If the load Q is high, then the resonance of energy from the energy source, Vs, need only be re-enforced every second half-cycle, thereby simplifying converter and control requirements. A high Q circuit is characterised by successive half-cycle capacitor voltage peak magnitudes being of similar magnitude, that is the decay rate is π vc = e 2 Q ≈ 1 for Q 1 (16.14) vc n

n +1

Thus there is sufficient energy stored in C to be transferred to the load R, without need to involve the supply Vs. The circuit in figure 16.3a is simpler and control is easier. capacitive

1 T1

D1

Vs

D4 T4

C

L

R

voltage transfer ratio

Power Electronics

723

inductive

positive slope

ZCS

The active power to the load depends on the repetition rate of the excitation, fr. P = W½ × f r (W)

(16.13)

½

2

ZVS

5 10

½ (a)

negative slope

3

(16.12)

0

Q

¾ (b)

1

1¼

1½

f/fo

Figure 16.3. Series resonant voltage source converter: (a) circuit and (b) voltage transfer function.

T3 D3 T1 D1

Vs

LR

T1 D1

Vi C

L

C R

R

T4 D4

CR

RLOAD

T2 D2

T4D4

VSI

(a)

16.3.1 – Series-resonant voltage-source inverter – single inverter leg Operation of the series load single leg circuit in figure 16.3a depends on the timing of the switches. (b)

CSI

I constant

LR and CR can be interchanged RLOAD can be transformer coupled

I constant L large

L large C

Vs

L

L

R

T1 D1

C

Vs

(c)

LR

T3 D3

Iin CR

L

T1 D1

T3 D3

Also, for any Q, each converter can be used with or without the shown freewheel diodes. Without freewheel diodes, the switches have to block high reverse voltages due to the energy stored by the capacitor. MOSFET and IGBTs require series diodes to achieve the reverse voltage blocking requirements. In high power resonant applications, the reverse blocking abilities of the GTO and GCT make them ideal converter switches. Better load resonant control is obtained if freewheel diodes are not used.

T4 D4

R

RLOAD

T2 D2

(d)

Figure 16.2. Resonant converter circuits: (a) series L-C-R with a high Q; (b) low Q series L-C-R; (c) parallel L-C-R and high Q; and (d) low Q parallel L-C-R circuit.

1 - Lagging operation (advancing the switch turn-off angle, f > fo) If the converter is operated at a frequency above resonance (effected by commutating the switches before the end of an oscillation cycle), the inductor reactance dominates and the load appears inductive. The load current lags the voltage as shown in figure 16.4. This figure shows the conducting devices and that a switch is turned on when its parallel connected diode is conducting. Turn-on therefore occurs at a low voltage (hence low switch turn-on loss and no need for fast recovery diodes), while turn-off (premature) is as with a hard switched inductive load (associated with switch high turn-off loss and turnoff Miller capacitance effects). The turn-off switching loss can be eliminated by adding a shunt capacitor across one of the leg switches and using a dead time between the gate drive voltages. Operation and switch timing are as follows: Switch T1 is turned on while its anti-parallel diode D1 is conducting and the current in the diode reaches zero and the current transfers to, and begins to oscillate through the switch T1. The capacitor charges to a maximum voltage and before the current reverses, the switch T1 is hard turned off. The current is diverted through diode D4. T4 is turned on which allows the oscillation to reverse. Before the current in T4 reaches zero, it is turned off and current is diverted to diode D1, which returns energy to the supply. The resonant cycle is repeated when T1 is turned on before the current in diode D1 reaches zero and the process continues. 2 - Leading operation (delaying the switch turn-on angle, f < fo) By operating the converter at a frequency below resonance (effectively by delaying switch turn-on until after the end of an oscillation cycle), the capacitor reactance dominates and the load appears capacitive. The load current leads the voltage as shown in figure 16.5. This figure shows the conducting devices and that a switch is turned off when its parallel diode is conducting. Turn-off therefore occurs at a low current, while turn-on (diode reverse recovery) is as with a hard switched inductive load. Fast recovery diodes are therefore essential. Switch output capacitance charging and discharge (½CV2) and the Miller effect at turn-on (requiring increased gate power) are factors to be accounted for.

Power Electronics

725

Chapter 16

asymmetrical bridge conducting devices T1

D4

T4

D1

T1

D3 D4

T3 T4

D1 D2

T1 T2

which is valid for the + Vs loop (through T1) and zero voltage loop (through T4) modes of cycle operation at resonance, provided the time reference is moved to the beginning of each half-cycle.

D3 D4

In steady-state the successive capacitor voltage absolute maxima are ∧ ∨ 1 e −απ / ω Vc = Vs and Vc = − Vs −απ / ω 1− e 1 − e −απ / ω

φ lagging IT1

H-bridge output voltage

726

D4

symmetrical H-bridge conducting devices T1 T2


(16.16)

The peak-to-peak capacitor voltage is therefore 1 + e −απ / ω 2ω Vc = × Vs = Vs × coth (απ / 2ω ) ≈ × Vs απ 1 − e −απ / ω

IT1

(16.17)

p− p

t 0

The energy transferred to the load R, per half sine cycle (per current pulse) is 2

IT4

Zero for half bridge

W=

∫

π /ω 0

i 2 Rdt =

∫

π /ω 0

(

= ½CVs coth απ 2

2ω

(16.18)

)

The input impedance of the series circuit is

φ lagging IT1

 1  V  × s × e −αt × sin ωt  R dt −απ   ω L  1− e ω 

switch T1/T2 hard turn-off

  ω ωo   1   = R  1 + jQ s  − Z s = Ze j ϕ = R + j  ωL −   ωC  ω     ωo 

IT1

 where ϕ = tan−1 Q s 

t 0

(16.19)

 ω ωo   −   ω    ωo asymmetrical bridge conducting devices

Vref

Vref

T1

Vref

D1

T4

D4

T1

D1

T1 T2

D1 D2

symmetrical H-bridge conducting devices IT4

T1 T2

switch T4/T3 hard turn-off

D1 D2

IT1

IT1 t

Zero for half bridge

IT4

φ leading IT1

switch T1/T2 hard turn-on

IT1 t

0

Analysis – single inverter leg – figure 16.3a For a square wave input voltage, 0 to Vs, of frequency ω ≈ ωo , the input voltage fundament of magnitude 2 Vs / π produces the dominant load current component, since higher frequency components are attenuated by second order L-C filtering action. That is, the resonant circuit excitation voltage is V i = 2Vs π . Key characteristic equations are ωo = 1/√LC, Zo = √L/C, and Q = Zo/R. The series circuit steady-state current at resonance for the single-leg half-bridge can be approximated by assuming ωo≈ω, such that in equation (16.1) io = 0: V 1 × s × e −αt × sin ωt (16.15) 0 ≤ ωt ≤ π i (ωt ) = −απ ωL 1− e ω

H-bridge output voltage

0

Operation and switch timing are as follows: Diode D4 is conducting when switch T1 is turned on, which provides a step input voltage Vs to the series L-C-R load circuit, and the current continues to oscillate. The capacitor charges to a maximum voltage and the current reverses through D1, feeding energy back into the supply. T1 is then turned off with zero current. The switch T4 is turned on, commutating D1, and the current oscillates through the zero volt loop created through T4 and the load. The oscillation current reverses through diode D4, when T4 is turned off with zero current. T1 is turned on and the process continues. Without the freewheel diodes the half oscillation cycles are controlled completely by the switches. On the other hand, with freewheel diodes, the timing of switch turn-on and turn-off is determined by the load current zeros, if maximum energy transfer to the load is to be gained.

D3 D4

φ leading

t 0

Figure 16.4. Series L-C-R high Q resonance using the converter circuit in figure 16.2a and b, with f > fo, a lagging power factor φ.

T3 T4

Vref

switch T4/T3 hard turn-on

Vref

Vref

IT4 t

0

Figure 16.5. Series L-C-R high Q resonance using the converter circuit in figure 16.2a and b, with f < fo, a leading power factor φ.

Power Electronics

727

Chapter 16

The frequency ratio terms in the equation for the input phase angle φ show that the resonant circuit is inductive (φ > 0, lagging current) when ω > ωo and capacitive (φ < 0, leading current) when ω 0, lagging current) when ω > ωo and capacitive (φ < 0, leading current) when ω fr. The voltage gain magnitude transfer function, shown in figure 16.7b, is

v R (ω ) = V i

1 2

(16.32)

2  ω   1 ω  1 −    + 2   ω ω   o   Q  o  2

which for a large Q tends to 1 as Q → ∞ 2 ω  1−   ωo  The output voltage can be in excess of the input voltage magnitude.

v R (ω ) = V i

16.5

Z (ωo ) =

(16.33)

Series-parallel-resonant voltage-source inverter – single inverter leg

The topology of this inverter is similar to that of the parallel resonant inverter except for an additional capacitor in series with the resonant inductor, or the same as that of the series resonant inverter except for an additional capacitor in parallel with the load, as shown in figure 16.8a. As a result, the inverter exhibits third-order characteristics that are intermediate between those of the series and parallel resonant inverters. In particular, it has a high light-load efficiency. The resonant circuit input impedance magnitude is 2 2 2     (1 + A 2 ) 1 −  ω   + 1  ω − ωo A         + Q 1 A ω ω ω  o    o    Z = Z oQ  2  ω  + 1 + Q 1 A ( )  ωo  where A=C2/C1 and C=C1C2/(C1+C2) such that ωo = 1/√LC = fo/2π, Zo = √L/C, and Q = R/Zo > 1.

(16.34)

2 2 Q 2 (1 + A ) − 1 + Q 2 (1 + A ) − 1 + 4Q 2 A (1 + A ) fr   = 2 fo 2Q 2 (1 + A )

(16.36)

When the bridge voltage excitation frequency is less than the circuit resonant frequency, f < fr, the resonant circuit appears capacitive, and inductive if f > fr. The voltage gain magnitude transfer function, shown in figure 16.8b, is 1 v R (ω ) = V i 2 2   ω 2  2 1 ω ω A  (1 + A ) 1 −  ω   + Q 2  ω − ωo 1 + A    o    o  The output voltage can be in excess of the input voltage magnitude.

(16.37)

The inverter is not safe under short-circuit and the open-circuit conditions. At R = 0, the capacitor C2 is shorted-circuited and the resonant circuit consists of L and C1. If the switching frequency f is equal to the resonant frequency of this circuit fr1= 1/2π√LC1, the magnitude of the current through the switches and the L-C1 resonant circuit is limited only by low switch resistance and the reactive components. This current may become excessive and destroy the circuit. If f is remote from fr1, the current amplitude is limited by the reactance of the resonant circuit. Because fr1 < fo, the inverter is safe for switching frequencies above fo. At R = ∞, the resonant circuit consists of L and the series combination of C1 and C2. Consequently, its resonant frequency is equal to fo and the inverter is not safe at or close to this frequency, as with the series resonant inverter under light loads. Summary of voltage source resonant inverters The maximum voltage across the switches in voltage-source inverters (both half-bridge and full-bridge) is equal to the dc input voltage Vs. • Inverter operation above the resonant frequency fr is preferred. Such operation results in an inductive load seen by the bridge switches. The switches turn on at zero voltage, thereby reducing the turn-on switching loss, Miller’s effect is absent, the switch input capacitance is low, the switch drive-power requirement is low, and turn-on speed is fast. However, switch turn-off is hard switched. The anti-parallel diodes turn off with a low di/dt and without diode recovery voltage snap. • During operation below resonance, the anti-parallel fast recovery diodes turn off with a high di/dt and generate reverse recovery current spikes. These spikes are present in the switch current at both turn-on and turn-off and stress the switches. For operation below resonance, the switches are turned on at the supply voltage Vs and the switch output capacitance is discharged into a low switch on-resistance, producing a high turn-on switching loss. The resonant frequency fr = fo is constant in the series resonant inverter but fr depends on the load R in the parallel and series-parallel resonant inverters.

Power Electronics

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Chapter 16

The series resonant inverter can operate safely with an open circuit output, although the output voltage can not be regulated. It is, however, exposed to excessive currents, >Vs/Zo,, which builds up with successive operational cycles, if the output is short-circuited at the operating frequency f close to the resonant frequency f = fo. Any output short circuit protection can exploit the time it takes for the current build up. The parallel resonant inverter output is protected by the impedance of the inductor from a short circuit output at any switching frequency. Large output currents occur when the output is open-circuited at a switching frequency close to the corner frequency fo. Series-parallel resonant inverter operation is not safe with an open-circuited output at frequencies close to the corner frequency fo and with a shortcircuited output at frequencies close to the resonant frequency fr. The output voltage of resonant inverters is regulated by changing the switching frequency. However, the required frequency changes in the series resonant inverter are large for no-load or light-load conditions. The series resonant inverter output voltage can be controlled by varying the duty cycle of the squarewave excitation, whilst operating at the resonance frequency. The parallel resonant inverter exhibits good light-load regulation, by operating above resonance. The output voltage at resonance is a function of load, thus can rise to high voltages at no load, if the operating frequency is no increased. It has, however, a low light-load efficiency due to a relatively constant current through the resonant circuit. The series-parallel resonant inverter combines the advantages, and eliminates the weaknesses, of the series and parallel resonant inverter topologies at the expense of an additional resonant capacitor. Alleviated are the poor light load regulation of the series resonant converter and the circulating current independent of load of the parallel resonant inverter. In the series resonant converter, the series capacitor tends to act is a dc blocking capacitor, facilitating H-bridge operation, prevent core saturation when the load is magnetically coupled. Also the current in the semiconductors decreases as the load decreases, which helps maintain the efficiency at light loads. The input voltage of the resonant circuit in the switched mode full-bridge inverters is a square wave with the with voltage levels of ±Vs. The peak-to-peak voltage across the resonant circuit in the full-bridge inverter is twice that in the half-bridge inverter. Therefore, the output voltage of the full-bridge inverter is also twice as high and the output power is four times higher than that from the half-bridge inverter at the same operating conditions (load, input voltage, and switching frequency). 16.6


To drive a parallel circuit from a voltage source inverter leg the resonant circuit inductance is series connected to the parallel R-C circuit. The input impedance of the series plus parallel circuit is 2  ω  1 ω  1 −   + j  Q p ωo    ωo  Z p = Ze j ϕ = R   ω   1 + jQ p (16.41) ω   o   2   1 ω  ω     − 2 − 1  where ϕ = tan−1 Q p   ωo   ωo  Q p    For a voltage source inverter leg, from the series plus parallel ac circuit, the voltage across the resistor, vR, at a given frequency, ω, is given by R jωC 1 R+ 1 jωC (16.42) = Vi vR (ω ) = Ve jϕ = Vi 2 R ω 1 ω 1−   + j jωC Q p ωo jω L +  ωo  1 R+ jωC The magnitude of the resistor voltage is therefore vR (ω ) = Vi

1 ω Q p ωo

Parallel-resonant current-source inverters

Parallel resonant circuits use a current source inverter (class D, parallel) as considered in 16.2.1 and shown in figure 16.2 parts c and d. If the load Q is high, then resonance need only be re-enforced every second half-cycle, thereby simplifying converter and control requirements. A common feature of parallel resonant circuits fed from a current source, is that commutation of the switches involves overlap where the output of the current source can be briefly shorted.

732

where ϕ = − tan

−1

1 2

2  ω   1 ω  1 −    + 2   ω ω Qp  o    o   2

(16.43)

2

ω  1−    ωo  The maximum resistor voltage is Q p / 1 − 1 / 4Q p2 at f = f o 1 − 1 / 2Q p2 . The effective input voltage Vi is 2Vs /π.

16.6.1 – Parallel-resonant current-source inverter – single inverter leg – figure 16.2c Figure 16.2c shows a single-leg half-bridge converter for high Q parallel load circuits. Energy is provided from the constant current source every second half cycle by turning on switch T1. When T1 is turned on (and T3 is subsequently turned off) the voltage across the L-C-R circuit resonates from zero to a maximum and back to zero volts. The energy in the inductor reaches a maximum at each zero voltage instant. T3 is turned on (at zero volts) to divert current from T1, which is then turned off with zero terminal voltage. The energy in the load inductor resonates within the load circuit, with the load in an open circuit state, since T1 is off. The sequence continues when the load voltage resonates back to zero as shown in figure 16.1b. The parallel circuit steady-state voltage at resonance for the single-leg half-bridge can be approximated by assuming ωo ≈ ω, such that in equation (16.8) vo = 0: I 1 0 ≤ ωt ≤ π × s × e −α t × sin ωt (16.38) v (ω t ) = −απ ωC ω 1− e which is valid for both the +Is loop and open circuit load modes of cycle operation, provided the time reference is moved to the beginning of each half-cycle. In steady-state the successive inductor current absolute maxima are ∧ ∨ 1 −e −απ / ω I L = Is and I L = I s (16.39) 1 − e −απ / ω 1 − e −απ / ω The energy transferred to the load R, per half sine cycle (per voltage pulse) is 2

W =∫

π /ω 0

v2

R

dt = ∫

 απ  = ½ LI s2 coth    2ω 

π /ω 0

 1  I  × s × e −α t × sin ωt  dt −απ   /R ω C  1− e ω 

16.6.2 – Parallel-resonant current-source inverter – H-bridge current-source inverter–figure 16.2d If the load Q is low, or maximum energy transfer to the load is required, the full bridge converter shown in figure 16.1d is used. Operation involves T1 and T2 directing the constant source current to the load and when the load voltage falls to zero, T3 and T4 are turned on (and T1 and T2 are then turned off). Overlapping the switching sequence ensures a path always exists for the source current. At the next half sinusoidal cycle voltage zero, T1 and T2 are turned on and then T3 and T4 are turned off. The parallel circuit steady-state voltage for the symmetrical H-bridge can be approximated by assuming ωo ≈ ω, such that in equation (16.8) vo = 0: I 2 0 ≤ ωt ≤ π v (ω t ) = × s × e −α t × sin ωt (16.44) −απ ωC 1− e ω which is valid for both the + Is loops of cycle operation, provided the time reference is moved to the beginning of each half-cycle. In steady-state the successive inductor current absolute maxima are ∧ ∨ 1 + e −απ / ω = I s × coth (απ / 2ω ) = − I L I L = Is 1 − e −απ / ω The energy transferred to the load R, per half sine cycle (per voltage pulse) is 2

(16.40)

W =∫

π /ω 0

v2

R

dt = ∫

 απ  = 2 LI s2 coth    2ω 

π /ω 0

 2  I  × s × e −αt × sin ωt  / R dt −απ   ωC ω  1− e 

(16.45)

Power Electronics

733

Chapter 16

As with a series resonant circuit, the full bridge delivers four times more power to the load than the single-leg half-bridge circuit. Similarly, the load power and power factor can be controlled by operating above or below the resonant frequency, by delaying or advancing the appropriate switching instances. In the case of a voltage source, the expressions for the voltage across the load resistor are the same as equations (16.41) to (16.43), except the input voltage Vi is doubled, from 2Vs /π to 4Vs /π.


734

From equation (16.16) the maximum capacitor voltage extremes are ∧ ∨ 1 −e −απ / ω Vc = Vs and Vc = Vs 1 − e −απ / ω 1 − e −απ / ω 340V 340Ve −0.25 = =− 1 − e −0.25 1 − e −0.25 = 1537V = −1197V

Example 16.1: Single-leg half-bridge with a series L-C-R load A single-leg half-bridge inverter as shown in the figure 16.2a, with the dc rail L-C decoupling shown in figure 16.9, supplies a 1 ohm resistance load with series inductance 100 µH from a 340 V dc source. If the bridge is to operating at a resonant frequency of 10kHz, determine: i. ii. iii. iv. v. vi. vii. viii. ix.

the necessary series C for resonance at 10kHz and the resultant Q the peak load current, its steady-state time domain solution, and peak capacitor voltages the bridge rms voltage and fundamental voltage across the series L-C-R load the power delivered to the load and the frequency when half power is delivered to the load. What is the switching advance/delay time? the peak blocking voltage of each semiconductor type (and for the case when the freewheel diodes are not employed) the average, rms, and peak current in the switches and diodes the resonant capacitor specification the dc supply current and the dc link capacitor rms current summarise conditions if the load is supplied from an H-bridge and also calculate the load power supplied at the third harmonic frequency, 3ωo.

Ldc Idc

iii.

Since the load is at resonance, the current is in phase with the fundamental of the bridge output voltage. The fundament voltage magnitude is given by 2V 1 π b1 = ∫ Vs sin1ωt = π s = 216.5V peak

π

The rms load current results because of the fundamental voltage, that is, the peak sine current is 216.5V/1Ω = 216.5A peak or 153V/1Ω = 153A rms. This agrees with the current values calculated in part b. iv.

T1

= 340V×0.45 × 153A=23.42kW The half-power frequencies are when the reactive voltage magnitude equals the resistive voltage magnitude. R f Au = f o ± 4π L = 10kHz ± 796Hz Thus at 9204 Hz and 10796 Hz the voltage across the resistive part of the load is reduced to 1/√2 of the inverter output voltage, since the voltage vectors are perpendicular. The power (proportional to voltage squared) is therefore halved (11.71kW) at the half-power frequencies.

D1

340V

D4

C

100µH

1Ω

T4

Single-leg half-bridge series-resonance circuit.

Operating above resonance, f > fo produces an inductive load and this is achieved by turning T1 and T4 off prematurely. Zero current turn-on occurs, but hard switching results at turn-off. To operate at the 10796Hz (92.6µs) upper half-power frequency the period has to be reduced from 100µs (10kHz) to 92.6µs. The period of each half cycle has to be reduced by ½×(100µs 92.6µs) = 3.7µs

Solution i.

From ωo = 2π f o = 1/ LC the necessary capacitance for resonance at 10kHz with 100µH is 1 C= = 2.5µF 2 ( 2 × π × 10kHz ) ×100µH The circuit quality factor Q is given by Z 100µH L /R= /1Ω = 6.3 Q= o = 2.5µF R C Therefore ω = 62.6 krad/s (9.968 kHz) α = 5×103 Ω/H ξ = 0.079 BWs = 9.97 krad/s (1.587kHz)

ii.

The power delivered to the load is given by 2 P = irms R = ib21 R = 153A 2 × 1Ω = 23.41kW Substitution into equation (16.18) gives 23.15kW at a pulse rate of 2×10kHz. Alternately P = Vs × I = Vs ×0.45 × I rms

Vs

Figure 16.9.

0

2V ≡ π s = 153V rms

iC Cdc

The bridge output voltage is a square wave of magnitude 340V and 0V, with a 50% duty cycle. The rms output voltage is therefore 340/√2 = 240.4V.

Operating below resonance, f < fo produces a capacitive load and this is achieved by turning T1 and T4 on late. Zero current turn-off occurs, but hard switching results at turn-on. By delaying turn-on of each switch by ½×(109µs - 100µs), 4.5µs, the effective oscillation frequency will be decreased to the lower half-power frequency, 9204Hz. v.

Zo = 6.3 Ω

The steady-state current is given by equation (16.15) V 1 i (ωt ) = × s × e −αt × sin ωt −απ ωL 1− e ω = 245.5 × e −5000 t × sin ( 2π 10kHz × t ) Since the Q is high (6.3), a reasonably accurate estimate of the peak current results if the ∧ current expression is evaluated at sin(½π), that is t = 25µs, which yields i = 216.7A. The rms load current is 216.7A/√2 = 153.2A rms.

The bridge diodes, which do not conduct at resonance, clamp switch and diode maximum supporting voltages to the rail voltage, 340V dc. Note that if clamping diodes were not employed the device maximum off-state voltages would occur during switch change over, when one switch has just been turned off, and just before the on-going switch is turned on. The load current is zero, so the load terminal voltage is the capacitor voltage. Switch T1 would need to support ∨ ∧ a forward voltage of Vs - v = 340V + 1197V = 1537V = v and ∧ ∨ a reverse voltage of v - Vs = 1537V - 340V = 1197V = - v , while Switch T4 supports ∧ a forward voltage of v = 1537V and ∨ a reverse voltage of - v = 1197V.

Power Electronics

735

Chapter 16

Thyristor family devices must be used, or devices with a series connected diode, which will increase the converter on-state losses. vi.

At resonance the two freewheel diodes do not conduct. The rms load current is 153.2 A at 10 kHz, where switch T1 conducts half the cycle and T4 conducts the other half which is the opposite polarity of the cycle. Each switch therefore has an rms current rating of 153.2/√2 = 108.3A rms. Since both switches conduct the same current shape, each has an average current rating of a half-wave rectified sine of magnitude 216.5A, that is 1 π 1 I T1 = 216.5sinωt dt = × 216.5A 2π ∫ 0 π = 0.45 × 216.5 / 2 = 68.9A By Kirchhoff’s current law, this current value for T1 is also equal to the average dc input current from the supply Vs.

vii.

The 2.5µF capacitor has a bipolar voltage and current requirement of ±1537V and ±216.7 A. The rms ratings are therefore ≈1087V rms and 153A rms. A metallised polypropylene capacitor capable of 10kHz ac operation, with a maximum dv/dt rating of approximately ½×(1537+1197)×ω, that is 85.6V/µs, is required.

viii.

The dc supply current is the average value of the half-wave rectified sinusoidal load current, which is the average current in T1. That is I dc = 0.45 × 153.1A rms


= 13 ×

4 × 340V

π

736

1

×

2

10   3 × 9.204 1 + 6.32  − 3 × 9.204   10 = 144.3V × 0.066 = 9.53V The magnitude of the third harmonic current is therefore 9.5V/1Ω = 9.5A or 6.7A rms. The load power at this frequency is 6.7V2/1Ω = 45.1W. This is clearly insignificant compared to the fundament power of 93.88kW being delivered to the 1 Ω load. ♣

16.7

Single-switch, current source, series resonant inverter

The single switch inverter in figure 16.10 is applicable to high Q load circuits such that the output is essentially sinusoidal, with zero average current. Based on the operating mechanisms, a sinusoidal current implies the switch has a 50% duty cycle. The switch turns on and off at zero volts so switch losses are low, thus the operating frequency can be high. The input inductor Llarge in conjunction with the input voltage source, during steady state operation, act as a current source input, Is, for the resonant circuit, such that Vs Is is equal to the power delivered to the load R.

Llarge Vs

Is

= 68.9A dc The rms current in the dc link capacitor Cdc is related to the dc input current and switch T1 rms current (as found in part vi.), by

iT

iD1

T1 D1

2 − I dc2 I c = I rms

iCs

Lo

Co

io Rload

Cs

= 108.32 − 68.92 = 83.6A rms

ix.

For the full H-bridge, the load dependant parameters C, ωo, ω, α, Q, BW, ξ, and half power points remain unchanged, being independent of bridge type and switching frequency. From equation (16.22) the steady-state current is double that for the asymmetrical bridge, V 2 × s × e −α t × sin ωt i (ωt ) = −απ ωL 1− e ω = 491× e −5000 t × sin ( 2π 10kHz × t )

switch conducting δ=½

io

switch off 1/2fo

switch conducting 1/2fo

Is

∧

The peak current is i = 433.4A. The rms load current is 433.4A/√2 = 306.4A rms From equation (16.23) both the maximum capacitor voltages are ∧ ∨ 1 + e −απ / ω Vc = Vs = − Vc 1 − e−απ / ω 1 + e −0.25 = 340V = 2734V 1 − e−0.25 The power delivered to the load is four times the single-leg half-bridge case and is 2 P = irms R = 306.4A 2 × 1Ω = 93.88kW The average switch current is 194.8A, but the average supply current is four times the single-leg half-bridge case and is 275.5.6A. For a square wave, the third harmonic voltage is a third the magnitude of the fundamental. From equation (16.27), for operation at the lower half power frequency 9204Hz, (which would result in the largest harmonic component magnitude after L-C filtering attenuation) f3 = 27.6kHz. 4V 1 vR (ω½− ) = 13 × s × 2 π  3ω½− ωo  2 1+ Q  − − ω 3 ω o ½   4 × 340V 1 = 13 × × 2 π 2π 10kHz  2  3 × 2π 9.204kHz 1 + 6.3  −  2π 10kHz 3 × 2π 9.204kHz  

Is

iT1

IT1 = Is + io

Is

iCs = Is + io

iCs iD1

VT1

io

io

↑

Is

IT1

Rload

↑

Is

ICs

Rload

Figure 16.10. Single-switch, current-source series resonant converter circuit and waveforms.

Power Electronics

737

When the switch T1 is turned on, with zero terminal voltage, it conducts both the constant current Is and the current io resonating in the output circuit, as shown in the circuit waveforms in figure 16.10. The resonating load current builds up. The switch T1, which is in parallel with Cs, is turned off. Current from the switch is diverted to Cs, which charges from an initial voltage of zero. Cs thus forms a turn-off snubber in parallel with T1. The charge on Cs eventually resonates back to zero at which instant the switch is turned on, again, with zero turn-on loss. The resonant frequency is ωo = 1/ Lo Co and because of the high Q, a small change in the switching frequency significantly decreases the output current, hence output voltage. As with any current source inverter, the peak switch voltage is in excess of Vs. Since the current is sinusoidal, the average load voltage and inductor voltage are zero. Therefore the average voltage across Co and Cs is the supply voltage Vs. The peak switch voltage can be estimated to be in excess of Vs /0.45 which is based on a half-wave rectified average sinusoidal voltage. If the load conditions change and the switch duty cycle is varied from δ = ½, circuit voltages increase and capacitor Cs voltage discharges before the circuit current reaches zero. The capacitor and switch are bypassed with current flowing through the diode D1. This diode prevents the switch from experiencing a negative voltage and the capacitor Cs from charging negatively. Although such resonant converters offer features such as low switching losses and low radiated EMI, optimal control and performance are difficult to maintain and extremely high circuit voltages occur at low duty cycles.

Reading list Hart, D.W., Introduction to Power Electronics, Prentice-Hall, Inc, 1994. Mohan, N., Power Electronics, 3rd Edition, Wiley International, 2003. Problems

Chapter 16

Blank


738

739

Chapter 17

Switched Mode DC to DC Converters

740

Depending on the requirements of the application, the dc-to-dc converter can be one of four basic converter types, namely • • • •

17 17.1

DC to DC Converters - Switched-Mode

A switched-mode power supply (smps) or switching regulator, efficiently converts a dc voltage level to another dc voltage level, via an intermediate magnetic (inductor) storage/transfer stage, such that a continuous, possibly constant, load current flows, usually at power levels below a few kilowatts. Shunt and series linear regulator power supplies dissipate much of their energy across the regulating transistor, which operates in the linear mode. An smps achieves regulation by varying the on to off time duty cycle of the switching element. This switching minimises losses, irrespective of load conditions. Figure 17.1 illustrates the basic principle of the ac-fed smps in which the ac mains input is rectified, capacitively smoothed, and supplied to a high-frequency transistor chopper. The chopped dc voltage is transformed, rectified, and smoothed to give the required dc output voltage. A high-frequency transformer is used if an isolated output is required. The output voltage is sensed by a control circuit that adjusts the duty cycle of the switching transistor in order to maintain a constant output voltage with respect to load and input voltage variation. Alternatively, the chopper can be configured and controlled such that the input current tracks a scaled version of the input ac supply voltage, therein producing unity (or controllable) power factor I-V input conditions. The switching frequency can be made much higher than the 50/60Hz line frequency; then the filtering and transformer elements used can be made small, lightweight, low in cost, and efficient.

forward flyback balanced resonant.

The forward converter

The basic forward converter, sometimes called a step-down or buck converter, is shown in figure 17.2a. The input voltage Ei is chopped by transistor T. When T is on, because the input voltage Ei is greater than the load voltage vo, energy is transferred from the dc supply Ei to L, C, and the load R. When T is turned off, stored energy in L is transferred via diode D to C and the load R. If all the stored energy in L is transferred to C and the load before T is turned back on, operation is termed discontinuous inductor current, since the inductor current has reached zero. If T is turned on before the current in L reaches zero, that is, if continuous current flows in L, inductor operation is termed continuous. Parts b and c respectively of figure 17.2 illustrate forward converter circuit current and voltage waveforms for continuous (figure 17.1b) and discontinuous (figure 17.1c) current conduction of inductor L. For analysis it is assumed that components are lossless and the output voltage vo is maintained constant because of the large magnitude of the capacitor C across the output. The input voltage Ei is also assumed constant, such that Ei ≥ vo. iL = io

tD

tD

ac mains voltage feed-back for unity input power factor

Figure 17.1. Functional block diagram of a switched-mode power supply.

BWW

Figure 17.2. Non-isolated forward converter (buck converter) where v0 ≤ Ei: (a) circuit diagram; (b) waveforms for continuous output (inductor) current; and (c) waveforms for discontinuous output (inductor) current.

Power Electronics

741

Chapter 17

17.1.1 Continuous inductor current

vo I o v = o =δ (17.11) 1× Ei × I o Ei which assumes continuous inductor current. This result shows that the higher the duty cycle, that is the closer the output voltage vo is to the input voltage Ei, the better the switch I-V ratings are utilised. SUR =

The inductor current is analysed first when the switch is on, then when the switch is off. When transistor T is turned on for period tT, the difference between the supply voltage Ei and the output voltage v0 is impressed across L. From V = L di/dt = L ∆i/∆t, the linear current change through the inductor will be ∧ ∨ E −v ∆iL = i L − i L = i o × tΤ (17.1) L When T is switched off for the remainder of the switching period, tD=τ- tT, the freewheel diode D conducts and -v0 is impressed across L. Thus, using V = L ∆i/∆t, rearranged, assuming continuous conduction v ∆iL = o × (τ − tΤ ) (17.2) L Equating equations (17.1) and (17.2) gives ( Ei - vo ) tT = vo (τ - tT ) (17.3) This expression shows that the inductor average voltage is zero, and after rearranging (Pout = Pin): vo I i tT (17.4) = = = δ = tT f 0 ≤δ ≤1 Ei I o τ This equation also shows that for a given input voltage, the output voltage is determined by the transistor conduction duty cycle δ and the output is always less than the input voltage. This confirms and validates the original analysis assumption that Ei ≥ vo. The voltage transfer function is independent of the load R, circuit inductance L and capacitance C. The inductor rms ripple current (and capacitor ripple current in this case) from equations (17.1) and (17.2) , for continuous inductor current, is given by ∆i 1 vo 1 Ei (17.5) iL r = L = (1- δ )τ = (1- δ ) δτ 2 3 2 3 L 2 3 L .

.

17.1.2 Discontinuous inductor current ∨

The onset of discontinuous inductor current operation occurs when the minimum inductor current i L , ∨ reaches zero. That is, with i = 0 in equation (17.9), the last equality 1 (1 − δ ) (17.12) − =0 R 2f L relates circuit component values (R and L) and operating conditions (f and δ) at the verge of ∨ discontinuous inductor current. Also, with i = 0 in equation (17.9) I L = I o = ½ ∆iL (17.13) which, after substituting equation (17.1) or equation (17.2), yields (E − v ) Ei τδ (1 − δ ) (17.14) I L = I o = i o τδ or 2L 2L L

L

If the transistor on-time tT is reduced (or the load current is reduced), the discontinuous condition dead ∨ time tx is introduced as indicated in figure 17.2c. From equations (17.1) and (17.2), with i = 0 , the output voltage transfer function is now derived as follows L

.

while the inductor total rms current is

∧

iL =

2

2 ∨  1  ∧2 ∧ ∨  ½ ∆iL  = iL rms = I + i = I +  i + i × i + iL  3  3    The switch and diode average and rms currents are given by IT = Ii = δ Io ITrms = δ iL rms 2 L

2 Lr

742


2 L

L

L

L

(17.6)

.

I D = I o − I i = (1 − δ ) I o

I Drms = 1 − δ iL rms

( Ei − vo ) v tT = o (τ − tT − t x ) L L

(17.15)

that is vo = Ei

(17.7)

δ 1−

0 ≤ δ < 1 and t x ≥ 0

tx

(17.16)

τ

If the average inductor current, hence output current, is I L , then the maximum and minimum inductor current levels are given by ∧ v i = I L + ½ ∆iL = I o + ½ o (1- δ )τ L (17.8)  1 1−δ  = vo  +  R 2f L and ∨ v i = I L − ½ ∆iL = I o − ½ o (1- δ )τ L (17.9)  1 1− δ  = vo  −  R 2f L respectively, where ∆iL is given by equation (17.1) or (17.2). The average output current is ∧ ∨ I L = ½(i + i ) = I o = vo / R . The output power is therefore vo2 / R , which equals the input power, namely E i I i = E i I T . Circuit waveforms for continuous inductor current conduction are shown in figure 17.2b.

This voltage transfer function form may not be particularly useful since the dead time tx is not expressed in term of circuit parameters. Accordingly, from equation (17.15) ∧ (E − v ) (17.17) i L = i o tT L and from the input current waveform in figure 17.2c: ∧ t (17.18) Ii = ½ i L × T

Switch utilisation ratio

Assuming power-in equals power-out, that is, Ei I i = vo I o = vo I L , the input average current can be eliminated, and after re-arranging yields: vo 1 1 = = (17.21) Ei 2 LI o 2 LI i 1+ 2 1+ 2 δ τ Ei δ τ vo

L

L

L

L

The switch utilisation ratio, SUR, is a measure of how fully a switching device’s power handling capabilities are utilised in any switching application. The ratio is defined as P (17.10) SUR = out p VT I T where p is the number of power switches in the circuit; p=1 for the forward converter. The switch maximum instantaneous voltage and current are VT and I T respectively. As shown in figure 17.2b, the maximum switch ∧voltage supported in the off-state is Ei, while the maximum current is the maximum inductor current i which is given by equation (17.8). If the inductance L is large such that the ripple current is small, the peak inductor current is approximated by the average inductor current I T ≈ I L = I o , that is L

τ

∧

Eliminating i L yields

2Ii

δ

= (1 −

vo τδ Ei ) Ei L

(17.19)

that is vo 2 LI = 1− 2 i Ei δ τ Ei

(17.20)

At a low output current or high input voltage, there is a likelihood of discontinuous inductor conduction. To avoid discontinuous conduction, larger inductance values are needed, which worsen transient response. Alternatively, with extremely low on-state duty cycles, a voltage-matching transformer can be used to increase δ. Once a transformer is used, any smps technique can be used to achieve the desired output voltage. Figures 17.2b and c show that the input current is always discontinuous.

Power Electronics

743

Chapter 17

17.1.3 Load conditions for discontinuous inductor current As the load current decreases, the inductor average current also decreases, but the inductor ripple current magnitude is unchanged. If the load resistance is increased sufficiently, the bottom of the ∨ triangular inductor current, i L , eventual reduces to zero. Any further increase in load resistance causes discontinuous inductor current and the linear voltage transfer function given by equation (17.4) is no longer valid and equations (17.16) and (17.20) are applicable. The critical load resistance for continuous inductor current is specified by v v (17.22) Rcrit ≤ o = o I o ½ ∆iL Substitution for vo from equation (17.2) and using the fact that I o = I L , yields v ∆i L L Rcrit ≤ o = I o I L (τ − tΤ )

(17.23)

Eliminating ∆iL by substituting the limiting condition given by equation (17.13) gives

Rcrit ≤

vo ∆iL L 2ILL 2L = = = I o I L (τ − tΤ ) I L (τ − tΤ ) (τ − tΤ )

(17.24)

Dividing throughout by τ and substituting δ = tT / τ yields v 2L 2L = (17.25) Rcrit ≤ o = I o (τ − tΤ ) τ (1 − δ ) The critical resistance can be expressed in a number of forms. By substituting the switching frequency ( f s = 1/ τ ) or the fundamental inductor reactance ( X L = 2π f s L ) the following forms result. v v 2 fs L XL 2L 2L Rcrit ≤ o = = o× = = (17.26) (Ω ) I o τ (1 − δ ) Ei τδ (1 − δ ) (1 − δ ) π (1 − δ ) Notice that equation (17.26) is in fact equation (17.12), re-arranged. If the load resistance increases beyond Rcrit, the output voltage can no longer be maintained with duty cycle control according to the voltage transfer function in equation (17.4). 17.1.4 Control methods for discontinuous inductor current Once the load current has reduced to the critical level as specified by equation (17.26), the input energy is in excess of the load requirement. Open loop load voltage regulation control is lost and the capacitor C tends to overcharge. Hardware approaches can solve this problem – by producing continuous inductor current • increase L thereby decreasing the inductor current ripple peak-to-peak magnitude • step-down transformer impedance matching to effectively reduce the apparent load impedance


That is, once discontinuous inductor current occurs, if the switching frequency is varied inversely with load resistance and the switch on-state period is maintained constant, output voltage regulation can be maintained. Load resistance R is not a directly or readily measurable parameter for feedback proposes. Alternatively, since vo = Io R substitution for R in equation (17.28) gives R f var = f s crit × Io vo (17.29)

α

f var

Io

That is, for I o < ½∆iL or Io < vo / Rcrit , if tT remains constant and fvar is varied proportionally with load current, then the required output voltage vo will be maintained. 17.1.4ii - fixed switching frequency fs, variable on-time tTvar

The operating frequency fs remains fixed while the switch-on time tTvar is reduced, resulting in the ripple current being reduced. Operation is specified by equating the input energy and the output energy as in equation (17.27), thus maintaining a constant capacitor charge, hence voltage. That is v2 1 (17.30) ½ ∆iL Ei tT var = o R fs Isolating the variable on-time tTvar yields vo2 1 tT var = ½ ∆i L Ei f s R Substituting ∆iL from equation (17.2) gives 1 tT var = tT Rcrit × R (17.31) 1 tT var α R That is, once discontinuous inductor current commences, if the switch on-time is varied inversely to the square root of the load resistance, maintaining the switching frequency constant, regulation of the output voltage can be maintained. Again, load resistance R is not a directly or readily measurable parameter for feedback proposes and substitution of vo / Io for R in equation (17.31) gives .

.

Rcrit × vo

tT var = tT

α

tT var

.

.

Io

(17.32)

Io

Two control approaches to maintain output voltage regulation when R > Rcrit are • vary the switching frequency fs, maintaining the switch on-time tT constant so that ∆iL is fixed or • reduce the switch on-time tT , but maintain a constant switching frequency fs, thereby reducing ∆iL.

That is, if fs is fixed and tT is reduced proportionally to required output voltage magnitude vo will be maintained.

If a fixed switching frequency is desired for all modes of operation, then reduced on-time control, using output voltage feedback, is preferred. If a fixed on-time mode of control is used, then the output voltage is control by varying inversely the frequency with output voltage. Alternatively, output voltage feedback can be used.

17.1.5 Output ripple voltage

17.1.4i - fixed on-time tT, variable switching frequency fvar The operating frequency fvar is varied while the switch-on time tT is maintained constant such that the ripple current remains unchanged. Operation is specified by equating the input energy and the output energy, thus maintaining a constant capacitor charge, hence output voltage. That is, equating energies v2 1 (17.27) ½ ∆iL Ei tT = o R f var Isolating the variable switching frequency fvar gives vo2 1 f var = ½ ∆iL Ei tT R 1 f var = fs Rcrit × R (17.28) 1 f var α R

744

.

Io , when I o < ½∆iL or Io < vo / Rcrit , then the

Three components contribute to the output voltage ripple • Ripple charging/discharging of the ideal output capacitor, C • Capacitor equivalent series resistance, ESR • Capacitor equivalent series inductance, ESL The capacitor inductance and resistance parasitic series component values decrease as the quality of the capacitor increases. The output ripple voltage is the vectorial summation of the three components that are shown in figure 17.3 for the forward converter. Ideal Capacitor: The ripple voltage for a capacitor is defined as ∆vC =

1 C

∫ i dt = C ∆Q 1

Figures 17.2 and 17.3 show that for continuous inductor current, the inductor current which is the output current, swings by ∆i around the average output current, I o , thus ∆vC =

1 C

∫ i dt = ½ C1

∆i τ 2 2

Substituting for ∆iL from equation (17.2) ∆vC =

1 C

∫ i dt = ½ C1

∆i τ 2 2

=

1

8

(17.33) 1 vo C L

× (τ − tΤ )τ

(17.34)

Power Electronics

745

Chapter 17

If ESR and ESL are ignored, after rearranging, equation (17.34) gives the percentage voltage ripple (peak to peak) in the output voltage ½ ∆vC ∆vo 1 1 f (17.35) = = 8 LC × (1 − δ )τ 2 = ½π 2 (1 − δ )  c  vo vo  fs  In complying with output voltage ripple requirements, from this equation, the switching frequency fs=1/τ must be much higher that the cut-off frequency given by the forward converter low-pass, second-order LC output filter, fc = 1/2π√LC. The voltage switching harmonics before filtering are the dc part δEi and 2 Ei 1 − cos 2π nδ Vn = (17.36) nπ ESR: The equivalent series resistor voltage follows the ripple current, that is, it swings linearly about VESR = ±½ ∆i × RESR (17.37) ESL: The equivalent series inductor voltage is derived from v = Ldi / dt , that is, when the switch is on V + = L∆i / ton = L∆i / δτ (17.38)


746

Hence calculate the switch utilisation ratio as defined by equation (17.11). iv. v. vi. vii.

viii. ix.

calculate the mean and rms current ratings of diode D, switch T and L. calculate the capacitor average and rms current, iCrms and output ripple voltage if the capacitor has an internal equivalent series resistance of 20mΩ, assuming C = ∞. calculate the maximum load resistance Rcrit before discontinuous inductor current. Calculate the output voltage and inductor non-conduction period, tx, when the load resistance is triple the critical resistance Rcrit. if the maximum load resistance is 1Ω, calculate • the value the inductance L can be reduced, to be on the verge of discontinuous inductor current and for that L • the peak-to-peak ripple and rms, inductor and capacitor currents. specify two control strategies for controlling the forward converter in a discontinuous inductor current mode. output ripple voltage hence percentage output ripple voltage, for C = 1,000µF and an equivalent series inductance of ESL = 0.5µH, assuming ESR = 0Ω.

ESL

When the switch is off

− VESL = − L∆i / toff = − L∆i / (1 − δ )τ

(17.39)

The total instantaneous ripple voltage is ∆vo = ∆vC + VESR + VESL (17.40) Forming a time domain solution for each component, then differentiating, gives a maximum ripple when t = 2CRESR (1 − δ ) (17.41) This expression is independent of the equivalent series inductance, which is expected since it is constant during each operational state. If dominant, the inductor will affect the output voltage ripple at the switch turn-on and turn-off instants.

Solution i. From equation (17.4), assuming continuous inductor current, the duty cycle δ is v 48V δ= o = = ¼ = 25% Ei 192V Also, from equation (17.4), for a 10kHz switching frequency, the switching period τ is 100µs and the transistor on-time tT is given by vo tT 48V t = = = T Ei τ 192V 100µs whence the transistor on-time is 25µs and the diode conducts for 75µs. vo 48V = 48A = I L = 1Ω R From power-in equals power-out, the average input current is I i = vo I o / Ei = 48V×48A/192V = 12A

ii. The average load current is I o =

∆i

o

iC

τ∆i/8C

o

VC

∆i R

o

VESR

iii. From equation (17.1) (or equation (17.2)) the inductor peak-to-peak ripple current is E −v 192V-48V ∆iL = i o × tΤ = ×25µs = 18A L 200µH

v c = vo

L∆i/ton

-

From part ii, the ∨average inductor current is the average output current, 48A. The inductor current is continuous since i L = 39A. Circuit voltage and current waveforms are shown in the figure to follow. The circuit waveforms show that the maximum switch voltage and current are 192V and 57A respectively. The switch utilising ratio is given by equation (17.11), that is v2 48V 2 Pout 1Ω ≡ 21% R = SUR = = Ei × i o Ei × i o 192V × 57A o

o

VESL

L∆i/tD

Figure 17.3. Forward converter, three output ripple components, showing: left - voltage components; centre – waveforms; and right - capacitor model.

Example 17.1: Buck (step-down forward) converter

The step-down converter in figure 17.2a operates at a switching frequency of 10 kHz. The output voltage is to be fixed at 48 V dc across a 1 Ω resistive load. If the input voltage Ei =192 V and the choke L = 200µH: i. calculate the switch T on-time duty cycle δ and switch on-time tT. ii. calculate the average load current I o , hence average input current I i . iii. draw accurate waveforms for • the voltage across, and the current through L; vL and iL • the capacitor current, ic • the switch and diode voltage and current; vT, vD, iT, iD.

If the ripple current were assume small, the resulting SUR value of δ = 33% gives a misleading underestimate indication. iv. Current iD through diode D is shown on the inductor current waveform. The average diode current is τ − tT ID = × I L = (1 − δ ) × I L = (1 − ¼)×48A = 36A

τ

The rms diode current is given by 75µs ∆iL 2 1 τ −t ∧ 1 18A 2 (i L − (57AiDrms = t ) dt = t ) dt = 41.8A τ − tT 100µs ∫ 0 75µs τ ∫0 Current iT through the switch T is shown on the inductor current waveform. The average switch current is t I T = T I L = δ I L = ¼×48A = 12A T

.

.

τ

Alternatively, from power-in equals power-out I T = I i = vo I o / Ei = 48V×48A/192V = 12A

Power Electronics

747

Chapter 17


=

Ei -vo

748

2×200µH = 16/3Ω 100µs × (1-¼)

= 5 1 3 Ω when I o = 9A Alternatively, the critical load current is 9A (½ ∆iL), thus from the equation immediately above, the load resistance must not be greater than vo / I o = 48V/9A = 5⅓Ω, if the inductor current is to be continuous.

3.6mV.s

When the load resistance is tripled to 16Ω the output voltage is given by equation (17.20), which is shown normalised in table 17.2. That is  8  Rτ 16Ω × 100µs = = 8 thus vo = Ei × ¼kδ 2  −1 + 1 + 2  where k = δ k L 200µH   8  i L = 14.625A  vo = 192V × ¼ × 8 × ¼ 2 ×  −1 + 1 + 2  = 75V   ×8  ¼  The inductor current is zero for an interval of the 100µs switching period, and the time is given by the appropriate normalised expression involving tx for the forward converter in table 17.2 or by equation (17.16), which when re-arranged to isolate tx becomes     δ  ¼  = 36µs [tT = 25µs tD = 39µs ] tx = τ 1 −  = 100µs ×  1 − 75V v  o   50V   E i  

(V) 192V

Icap 0

VTran

VDiode

VDiode

VTran 18A

25 125

vii. The critical resistance formula given in equation (17.26) is valid for finding critical inductance when inductance is made the subject of the equation, that is, rearranging equation (17.26) gives Lcrit = ½ × R × (1 − δ ) × τ (H) = ½×1Ω×(1-¼)×100µs = 37½µH This means the inductance can be reduced from 200µH with a 48A mean and 18A p-p ripple current, to 37½µH with the same 48A mean plus a superimposed 96A p-p 2I L ripple current. The rms capacitor current is given by iCrms = ∆iL / 2 3

Figure: Example 17.1

( )

.

The transistor rms current is given by 25µs 1 t ∨ ∆iL 2 1 18A 2 iT rms = τ ∫ 0 (i + tT t ) dt = 100µs ∫ 0 (39A+ 25µs t ) dt

= 96A/2 3 = 27.2A rms .

T

L

.

.

The inductor rms current requires the following integration τ −t ∧ ∆iL 2  1  t ∨ ∆iL 2 (i + iLrms = t ) dt + ∫ (i L − t ) dt  τ  ∫ 0 0 tT τ − tT 

= 24.1A

T

The mean inductor current is the mean output current, Io = I L = 48A . The inductor rms current is given by equation (17.6), that is 2

2

½ ∆iL  = 48A 2 +  ½ × 18A  = 48.3A I L rms = I L2 +     3 3  

v. The average capacitor current I C is zero and the rms ripple current is given by iC rms = =

1

∆i

tT

∆i

τ −tT



L (− 1 2 ∆iL + L t ) 2 dt + ∫ ( 1 2 ∆iL − t ) 2 dt  τ  ∫ 0 0 tT τ − tT 

.

1  18A 2 18A 2  t ) dt + ∫ (9At ) dt  (-9A+  0 100µs  ∫ 0 25µs 75µs  25µs

.

=

.

T

L

.

75µs  25µs 1 96A 2 96A 2  × (0 + t ) dt + ∫ (96A t ) dt  0 100µs  ∫ 0 25µs 75µs 

= 96/ 3 = 55.4 A rms or from equation (17.6) iLrms = I L2 + iL2ripple = 482 + (96 / 2 3) 2 = 55.4 A rms

75µs

= 5.2A (= ∆iL / 2 3) The capacitor voltage ripple (hence the output voltage ripple), assuming infinite output capacitance, is determined by the capacitor ripple current which is equal to the inductor ripple current, 18A p-p, that is vo ripple = ∆iL × RCesr

= 18A×20mΩ = 360mV p - p and the rms output voltage ripple is vo rms = iCrms × RCesr = 5.2A rms×20mΩ = 104mV rms

vi. Critical load resistance is given by equation (17.26), namely v 2L Rcrit ≤ o = τ (1 − δ ) Io

viii. For R >16/3Ω, or I o < 9A , equations (17.29) or (17.32) can be used to develop a suitable control strategy. (a) From equation (17.29), using a variable switching frequency of less than 10kHz, R 5 13 Ω f var = f s crit Io = 10kHz Io vo 48V 10 × Io kHz 9 (b) From equation (17.32), maintaining a fixed switching frequency of 10kHz, the on-time duty cycle is reduced (from 25µs) for I o < 9A according to f var

=

tT var = tT tT var

=

Rcrit vo

.

25 × Io 3 .

I o = 25µs µs

5 13 Ω 48V

.

Io

From equation (17.33) the output ripple voltage with an ideal 1,000µF capacitor is given by ∆i τ ∆vC = 8C 18A × 100µs = 225mV p - p = 8 × 1000µF The voltage produced because of the equivalent series 0.5 µH inductance is V + = L∆i / δτ ix.

Chapter 17

IL

IL

Rload

L

IL

vo/R

Ω

72A

ESL

=0.5µH×18A/0.25×100µs = 360mV

decreasing R LOAD

V − = − L∆i / (1 − δ )τ ESL

= - 0.5µH×18A/(1 - 0.25)×100µs = -120mV Time domain summation of the capacitor and ESL inductor voltages show that the peak to peak output voltage swing is determined by the ESL inductor, giving + − ∆vo = VESL − VESL

48A

= 360mV + 120mV = 480mV The percentage ripple in the output voltage is 480mV/48V = 1%. ♣

24A

The first concept to appreciate is that the net capacitor charge change is zero over each switching cycle. That is, the average capacitor current is zero: 1 t +τ Ic = ic ( t ) dt = 0

τ∫

t

In so being, the output capacitor provides any load current deficit and stores any load current (inductor) surplus associated with the inductor current within each complete cycle. Thus, the capacitor is a temporary storage component where the capacitor voltage is fixed on a cycle-by-cycle basis, and because of its large capacitance does not vary significantly within a cycle. The second concept involved is that the average inductor voltage is zero. Based on v = L di / dt , the equal area criteria in chapter 11.1.3i, 1 t +τ it +τ − it = ∫ vL ( t ) dt = 0 since it +τ = it in steady - state L t Thus the average inductor voltage is zero: 1 t +τ VL = vL ( t ) dt = 0

τ

∫

t

The most enlightening way to appreciate the converter operating mechanisms is to consider how the inductor current varies with load resistance R and inductance L. The figure 17.4 shows the inductor current associated with the various parts of example 17.1. For continuous inductor current operation, the two necessary and sufficient equations are Io = vo /R and equation (17.2). Since the duty cycle and on-time are fixed for a given output voltage requirement, equation (17.2) can be simplified to show that the ripple current is inversely proportional to inductance, as follows v ∆iL = o × (τ − tΤ ) L (17.42) 1 ∆i L α L Since the average inductor current is equal to the load current, then, at a given output voltage, the average inductor current is inversely proportional to the load resistance, that is I L = I o = vo / R (17.43) 1 IL α R

ILp-p

96A

36A 18A

200µH

1Ω

vo/R

100µH 37½µH

2Ω

17.1.6 Underlying operational mechanisms of the forward converter

The inductor current is pivotal to the analysis and understanding of any smps. For analysis, the smps internal and external electrical conditions are in steady-state on a cycle-by-cycle basis and the input power is equal to the output power.

750


decre asing L

Power Electronics

749

verge of discontinuous

9A

16/3Ω inductor current δ

0

1-δ

25µs

δ

100µs

t

0

1-δ

25µs

(a)

100µs

t

(b)

Figure 17.4. Forward converter (buck converter) operational mechanisms showing that: (a) the average inductor current is inversely proportional to load resistance R (fixed L) and (b) the inductor ripple current magnitude is inversely proportional to inductance L (fixed load R).

Equation (17.43) predicts that the average inductor current is inversely proportional to the load resistance, as shown in figure 17.4a. As the load is increased (load resistor decreased), the triangular inductor current moves vertically up, but importantly, from equation (17.42), the peak-to-peak ripple current is constant, that is the ripple current is independent of the load. As the load current is progressively decreased, by increasing R, the peak-to-peak current is unchanged; the inductor minimum current eventually reduces to zero, and discontinuous inductor current operation occurs. Equation (17.42) indicates that the inductor ripple current is inversely proportional to inductance, as shown in figure 17.4b. As the inductance is varied the ripple current varies inversely, but importantly, from equation (17.43), the average current is constant, and specifically the average current value is not related to inductance L and is solely determined by the load current, vo /R. As the inductance decreases the magnitude of the ripple current increases, the average is unchanged, and the minimum inductor current eventually reaches zero and discontinuous inductor current operation results. 17.1.7 Hysteresis voltage feedback control of the forward converter

The main function of a dc-to-dc converter is to provide a regulated output voltage, independent of input voltage or load changes, and it must respond quickly to maintain the output voltage due to any input voltage or load changes. Figure 17.5a shows a hysteresis controller for the buck and forward converters. The comparator compares the output voltage Vo to a reference voltage Vref. If Vo < Vref, the switch T1 is turned off. If Vo < Vref, the switch is turned on. This process is repeated continuously such that Vo is maintained at a value close to Vref. Undesirable high frequency switching action, chattering, is avoided by creating a dead band around Vref. The dead band is created by using an upper boundary Vupper and a lower boundary Vlower. The region between the two boundaries is the dead band. Resistors Rf/b and Rref produce the required dead band and their values determine the upper and lower boundaries of the dead band.

Power Electronics

751

Vref

Chapter 17

vo/p

upper boundary

Rref

Rf/b

switch off switch on

+

T1

_

vo/p

Vs

L

lower boundary

C

Io

+

Rload

D1

Vo

Vgs t

(a)

(b) Figure 17.5: The hysteresis controller with a dead band.


752

hysteresis control, fs and δ are not fixed, but change with the converter conditions. For a given set of converter parameters, both fs and δ are determined by the hysteresis boundaries, thus frequency fs and the duty ratio δ are not control parameters in the design of hysteresis controllers. No matter what type of control is used, the basic operating principles of the buck converter do not change. The converter output voltage ripple depends on the dead band of the controller. As the dead band increases (or decreases), the output voltage ripple increases (or decreases) in conjunction with the switching frequency decreasing (or increasing). The voltage ripple specification can be ensured by setting the dead band of the controller at 50% of the ripple specifications with a suitable inductor value. A properly designed hysteresis controller has excellent steady-state and dynamic properties. It responds quickly to step voltage set point changes. Fixed boundary controllers are stable under extreme disturbance conditions and can be chosen to guarantee ripple specifications or other converter operating constraints. Example 17.2: Hysteresis controlled buck converter

+

The comparator in figure 17.5a is a Schmitt trigger. The input voltage v of the positive op-amp input depends on Vref, vo/p, Rf/b, and Rref. It switches from one boundary of the dead band to the other. During initial start-up of the buck converter, the op-amp negative input v- is a small positive voltage and is less than v+. The amplifier saturates such that vo/p attains the op-amp supply, thus the switch is turned on and v+ is given by equation (17.44).

v+ =

Rf / b Rref v + V Rref + Rf /b o / p Rref + Rf /b ref

(17.44)

Progressively the output voltage Vo increases. The op-amp output voltage, vo/p, remains unchanged until Vo is equal to v+. The op-amp then enters its linear region and vo/p decreases, as does v+. This continues until vo/p reaches zero and the op-amp saturates again. The voltage v+ is now given by equation (17.45).

Rf / b v+ = V Rref + Rf /b ref

(17.45)

Equations (17.44) and (17.45) represent the control boundaries of the control circuit where equation (17.44) defines the upper boundary and equation (17.45) gives the lower boundary of the dead band. The dead band is derived by subtracting equations (17.45) and (17.44), and is given by equation (17.46) ∆D band =

Rf / b v Rref + Rf /b o / p

(17.46)

Rf/b and Rref are chosen to give the required ∆Dband / vo/p.

When the output voltage Vo is inside the dead band, the switch is off. Regardless of where the voltage starts, switching starts as soon as a boundary is traversed. In figure 17.5b the converter start-up process is illustrated. The switch T1 turns on initially because the output voltage Vo is below the turn-on boundary, Vlower. The output voltage rises from zero to Vupper at a rate limited by the inductor L, the capacitor C, and the load. The switch then turns off as the output voltage crosses the upper boundary Vupper and remains off until the output voltage falls crosses below the lower boundary Vlower where the switch is turned on. Once the voltage is between the boundaries, within the hysteresis bounds, on-off switching action attempts to maintain the current within the boundaries under all conditions. The operation of the system becomes independent of the input, the load, the inductor, and the capacitor values. The system tracks the desired voltage Vref even if the component values or the load changes drastically. A drawback is that the controller gives rise to an overvoltage during start-up. This problem can be solved by the correct selection of the inductor and capacitor values that allow the output voltage to rise exponentially and settle somewhat close to the desired output voltage, while maintaining the desired ripple voltage. In power electronics terms, the major limitation is possible broadband EMC generation due to a widely varying switching frequency. The closer the hysteresis bounds, the higher the upper frequency, the wider the frequency variation. Design Procedure In the steady-state, the converter output voltage depends on the input voltage Vs, the switching frequency fs, and the on duration of the switching period ton and is given by equation (17.4): Vo = t on f sV s = δ V s The product tonxfs is defined as the duty ratio δ. The output voltage Vo is regulated by changing δ while fs is kept constant. This pulse width modulation method is widely used in dc-dc converters. Another approach to regulate Vo is to vary fs, keeping δ constant. However, this is undesirable because it is difficult to filter the wide bandwidth ripple in the input and output signals of the converter. Hysteresis control of the buck converter is fixed boundary control. Vo is regulated by the switching action of the switch T1 as the output Vo crosses the upper or the lower boundary of the hysteresis dead band. In

A dc-dc buck converter is to be regulated with voltage-based hysteresis control. The output voltage Vo = 5V and the load varies between 1 and 5Ω. The input voltage Vs also varies between 16V and 24V with a nominal value of 20V. The maximum ripple voltage is to be limited to ±1% and the nominal switching frequency is fs = 100kHz. Design to necessary controller and specify the converter L and C values. Solution

The output voltage ripple is

∆V o

= 2%

Vo ∆Vo = 0.02 × 5V = 0.1V

To fulfil the required voltage ripple specification, the hysteresis band is chosen to be 50% of the output voltage ripple to account for an increase in the ripple magnitude due to the natural response of the converter RLC circuit, after the switch is turned off. The hysteresis band is ∆Dband = 0.5 × 0.1V = 0.05V Solving equation (17.46) for Rf/b:  V  Rf /b = Rref  o − 1  ∆ D b   Let Rref = 100Ω and vo = 10V. Then Rf/b is  10V  - 1  = 19.9kΩ Rf /b = 100   0.05V  These resistances produce a hysteresis band that fulfils the output ripple requirement. The maximum and minimum values of the load current are V 5V = 5A Io = o = Rmin 1Ω and ∨ V 5V Io = o = = 1A Rmax 5Ω Let the inductor current and the capacitor voltage swings be 10%. The inductor must limit the current swing at maximum load. The total current swing is as follows. Since ∆I L = 10%

Io

∆I L = 0.1 × 5A = 0.5A The capacitor voltage swing is ∆V c = 10% ∆V o ∆Vc = 0.1 × 0.1V = 0.01V Since the waveform of the output ripple voltage is approximately sinusoidal, accounting for the equivalent series resistance, ESR, of the capacitor C, the output ripple voltage is then 2 ∆Vo = ∆Vc2 + ∆VESR

Power Electronics

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where ∆VESR is the voltage ripple across the capacitor resistance RESR. The ∆VESR is usually much greater than ∆Vc, thus a close approximation of the peak-to-peak output voltage ripple is: ∆Vo ≅ ∆V ESR ≅ ∆I c RESR

≅ ( ∆I L - ∆ I R

) RESR

With the result for ∆IL, the inductor L is V (V −Vo ) 5V ( 20V − 5V ) L= o s = = 75µH V s f s ∆I L 20V × 100kHz × 0.5A The capacitance is ∆I L 0.5A C = = = 62.5µF ≅ 68µF 8f s ∆Vc 8 × 100kHz × 0.01V The ESR of the capacitor can be determined from Eq. (7.13): ∆V o 0.1V RESR = = = ¼Ω ∆I L − ∆I R 0.5A − 0.1A Transient overshoot, undershoot, and recovery time to step load and input changes are important performance parameters in buck converters. Since the current in the inductor cannot change instantaneously, the transient response is inherently inferior to that of the linear regulators. The recovery time to step changes in the line and the load is controlled by the characteristic of the controller feedback loop. Transient overshoot and undershoot resulting from step load changes can be analyzed and calculated as follows. The ac output impedance is V −V o Z out = s ∆I load Since

VL = −L

Chapter 17

17.3


The boost converter

The boost converter transforms a dc voltage input to a dc voltage output that is greater in magnitude but has the same relative polarity as the input. The basic circuit configuration is shown in figure 17.6a. It will be seen that when the transistor is off, the output capacitor is charged to the input voltage Ei. Inherently, the output voltage vo can never be less than the input voltage level. When the transistor T is turned on, the supply voltage Ei is applied across the inductor L and the diode D is reverse-biased by the output voltage vo. Energy is transferred from the supply to L and when the transistor is turned off this energy is transferred to the load and output capacitor through D. While the inductor is transferring its stored energy into C and the load, energy is also being provided from the input source. The output current is always discontinuous, but the input current can be either continuous or discontinuous. For analysis, assume vo > Ei and a constant input and output voltage. Inductor currents are then linear and vary according to v = L di/dt. 17.3.1 Continuous inductor current

The circuit voltage and current waveforms for continuous inductor conduction are shown in figure 17.6b. The inductor current excursion, from v = L di/dt, which is the input current excursion, during the switch ontime tT and switch off-time τ- tT , is given by (v - E ) E ∆iL = o i (τ − tT ) = i tT (17.47) L L After rearranging, the voltage and current transfer function is given by vo I i 1 = = (17.48) Ei I o 1 − δ where δ = tT /τ, tT is the transistor on-time, and Pin = Pout, that is, Ei Ii = vo Io is assumed.

di L dv and I o = C dt dt

thus

Z out =

(Vs

754

ii = iL

LI o −V o ) C

As a result, for an increasing load current, from 1A to 5A, the change in the output voltage (transient undershoot) is: ∨ L ∆I o2 ∆V o = ∆I o Z out = (V s −Vo ) C 75µH × (5A − 1A ) = 1.231V (20V − 5V ) × 68µF 2

=

and for a decreasing load current, from 5A to 1A, the change in the output voltage (transient overshoot) is ∆V o = =

LI o2 VoC 75µH × (5A − 1A ) 5V × 68µF

tD

tD

2

= 3.692V

♣ 17.2

Flyback converters

Flyback converters store energy in an inductor, (‘choke’), before transferring any energy to the load and output capacitor such that controllable output voltage magnitudes in excess of the input voltage are attainable. The key characteristic is that whilst energy is being transferred to the inductor, load energy is provided by the output capacitor. Such converters are also known as ringing choke converters. Two basic (minimum component count and transformerless) versions of the flyback converter are possible, both are integral to the same underlying fundamental circuit configuration (see section 17.5). • The step-up voltage flyback converter, called the boost converter, where the input and output voltage have the same polarity - non-inversion, and vo ≥ Ei. • The step-up/step-down voltage flyback converter, called the buck-boost converter, where output voltage polarity inversion occurs, that is vo ≥ 0.

Figure 17.6. Non-isolated, step-up, flyback converter (boost converter) where v0 ≥E1: (a) circuit diagram; (b) waveforms for continuous input current; and (c) waveforms for discontinuous input current.

Power Electronics

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Chapter 17


∧

The maximum inductor current, which is the maximum input current, i L , using equation (17.47) and vo = IoR, is given by ∧ Et i = I L + ½ ∆iL = I i + ½ i T L (17.49)  (1- δ ) δτ  Io vo 1 = + ½ (1- δ ) δτ = vo  +  L δ 1− δ 1 − 2 R L ( )  

∨

IL− Io ≤ 0 I L − ½ ∆iL − I o ≤ 0

(17.58)

E δτ Io −½ i − Io ≤ 0 L 1− δ

L

which yields

δ ≤ 1−

∨

while the minimum inductor current, i is given by ∨ Et i = I L − ½ ∆iL = I i − ½ i T L

756

L

2L

(17.59)

τR

L

=

 (1- δ ) δτ  Io v 1 − ½ o (1- δ ) δτ = vo  −  L 1−δ 2 L   (1 − δ ) R

(17.50)

17.3.3 Discontinuous inductor current

(17.51)

If the inequality in equation (17.51) is not satisfied, the input current, which is also the inductor current, reaches zero and discontinuous inductor conduction occurs during the switch off period. Various circuit voltage and current waveforms for discontinuous inductor conduction are shown in figure 17.6c. ∨ The onset of discontinuous inductor current operation occurs when the minimum inductor current i L , ∨ reaches zero. That is, with i L = 0 in equation (17.50), the last equality (1- δ ) δτ 1 − =0 (17.60) 2L (1 − δ ) R

∨

For continuous conduction i ≥ 0 , that is, from equation (17.50) Et v (1 − δ ) tT IL ≥ ½ i T = ½ o L L The inductor rms ripple current (and input ripple current in this case) is given by ∆i 1 vo iLr = L = (1- δ ) δτ 2 3 2 3 L L

.

(17.52)

relates circuit component values (R and L) and operating conditions (f and δ) at the verge of discontinuous inductor current.

.

The harmonic components in the input current are 2 Eiτ sin nδπ 2 voτ sin nδπ = I in = 2π 2 n 2 (1 − δ ) L 2π 2 n 2 L

(17.53)

while the inductor total rms current is

L

2

2 ∨  1  ∧2 ∧ ∨  = iLrms i L + i L× i L + iL  3  3   The switch and diode average and rms currents are given by IT = Ii − Io = δ Ii = δ I L ITrms = δ iL rms

 ½ ∆iL = I +i = I +  2 L

∨

With i L = 0 , the output voltage is determined as follows ∧ Et ( v − Ei ) i = iT = o (τ − tT − t x ) L L yielding t 1 − τx vo = Ei 1 − t x − δ τ

2 Lr

I D = (1 − δ ) I i = I o

2 L

(17.54)

.


(17.55)

(17.62)

Alternatively, using ∧

i = L

Switch utilisation ratio

(17.61)

Ei tT L

and ∧

The switch utilisation ratio, SUR, is a measure of how fully a switching device’s power handling capabilities are utilised in any switching application. The ratio is defined as P (17.56) SUR = out p VT I T where p is the number of power switches in the circuit; p=1 for the boost converter. The switch maximum instantaneous voltage and current are VT and I T respectively. As shown in figure 17.6b, the maximum switch voltage supported in the off-state is vo, while the maximum current is the maximum inductor ∧ current i L which is given by equation (17.49). If the inductance L is large such that the ripple current is small, the peak inductor current is approximated by the average inductor current such that I T ≈ I L = I o /1 − δ , that is vo I o (17.57) = 1− δ SUR = vo × I o 1− δ which assumes continuous inductor current. This result shows that the lower the duty cycle, that is the closer the step-up voltage vo is to the input voltage Ei, the better the switch I-V ratings are utilised. 17.3.2 Discontinuous capacitor charging current in the switch off-state

It is possible that the input current (inductor current) falls below the output (resistor) current during a part of the cycle when the switch is off and the inductor is transferring energy to the output circuit. Under such conditions, towards the end of the off period, part of the load current requirement is provided by the capacitor even though this is the period during which its charge is replenished by inductor energy. The circuit independent transfer function in equation (17.48) remains valid. This C discontinuous charging ∨ condition commences when the minimum inductor current i L and the output current Io are equal. That is

I L − I o = ½δ i

L

yields 2

Ei tT L Assuming power-in equals power-out and I L = I i 2 v Et I o ( o − 1) = i T Ei L δ that is vo E τδ 2 v τδ 2 = 1+ i = 1+ o Ei 2 LI o 2 LI i or vo 1 = E τδ 2 Ei 1− i 2 LI i

δ

( I L − Io ) =

(17.63)

(17.64)

On the verge of discontinuous conduction (when equation (17.48) is valid), these equations can be rearranged to give E I o = i τδ (1 − δ ) (17.65) 2L At a low output current or low input voltage, there is a likelihood of discontinuous inductor current conduction. (See appendix 17.11.) To avoid discontinuous conduction, larger inductance values are needed, which worsen the transient response. Alternatively, with extremely high on-state duty cycles, (because of a low input voltage Ei) a voltage-matching step-up transformer can be used to decrease δ. Figures 17.6b and c show that the output current is always discontinuous.

Power Electronics

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Chapter 17

17.3.4 Load conditions for discontinuous inductor current

f var = f s

As the load current decreases, the inductor average current also decreases, but the inductor ripple current magnitude is unchanged. If the load resistance is increased sufficiently, the bottom of the ∨ triangular inductor current, i L , eventually reduces to zero. Any further increase in load resistance causes discontinuous inductor current and the voltage transfer function given by equation (17.48) is no longer valid and equations (17.62) and (17.63) are applicable. (Certain circuit parameter values - L, R, and τ can avoid discontinuous conduction for all δ. See appendix 17.11.) The critical load resistance for continuous inductor current is specified by v (17.66) Rcrit ≤ o Io Eliminating the output current by using the fact that power-in equals power-out and I i = I L , yields Rcrit ≤

vo v2 = o I o Ei I L

(17.67)

Using I L = ½ ∆iL then substituting with the right hand equality of equation (17.47), halved, gives vo v2 v2 2L 2L = o = o = (17.68) I o Ei I L Ei2tT τδ (1 − δ ) 2 The critical resistance can be expressed in a number of forms. By substituting the switching frequency ( f s = 1/ τ ) or the fundamental inductor reactance ( X L = 2π f s L ) the following forms result. Rcrit ≤

vo v 2 fs L XL 2L 2L (Ω ) = = o × = = (17.69) I o τδ (1 − δ ) 2 Ei τδ (1 − δ ) δ (1 − δ ) 2 πδ (1 − δ ) 2 Equation (17.69) is equation (17.60), re-arranged. If the load resistance increases beyond Rcrit, generally the output voltage can no longer be maintained with purely duty cycle control according to the voltage transfer function in equation (17.48). Rcrit ≤

758


Rcrit × Io vo

(17.72) α Io That is, for discontinuous inductor current, namely I i < ½∆iL or Io < vo / Rcrit , if the switch on-state period tT remains constant and fvar is either varied proportionally with load current or varied inversely with load resistance, then the required output voltage vo will be maintained. f var

17.3.5ii - fixed switching frequency fs, variable on-time tTvar

The operating frequency fs remains fixed while the switch-on time tTvar is reduced such that the ripple current can be reduced. Operation is specified by equating the input energy and the output energy as in equation (17.70), thus maintaining a constant capacitor charge, hence voltage. That is v2 1 (17.73) ½ ∆iL Ei tT var = o R fs Isolating the variable on-time tTvar gives vo2 1 tT var = ½ ∆i L Ei f s R Substituting ∆iL from equation (17.47) gives 1 tT var = tT Rcrit × R (17.74) 1 tT var α R Again, load resistance R is not a directly or readily measurable parameter for feedback proposes and substitution of vo / Io for R in equation (17.74) gives Rcrit tT var = tT × Io vo (17.75) .

.

.

17.3.5 Control methods for discontinuous inductor current

tT var α Io That is, if the switching frequency fs is fixed and switch on-time tT is reduced proportionally to Io or inversely to R , when discontinuous inductor current commences, namely I i < ½∆iL or Io < vo / Rcrit , then the required output voltage magnitude vo will be maintained. .

Once the load current has reduced to the critical level as specified by equation (17.69), the input energy is in excess of the load requirement. Open loop load voltage regulation control is lost and the capacitor C tends to overcharge, thereby increasing vo. Hardware approaches can be used to solve this problem – by ensuring continuous inductor current • increase L thereby decreasing the inductor current ripple p-p magnitude • step-down transformer impedance matching to effectively reduce the apparent load impedance Two control approaches to maintain output voltage regulation when R > Rcrit are • vary the switching frequency fs, maintaining the switch on-time tT constant so that ∆iL is fixed or • reduce the switch on-time tT , but maintain a constant switching frequency fs, thereby reducing ∆iL. If a fixed switching frequency is desired for all modes of operation, then reduced on-time control, using output voltage feedback, is preferred. If a fixed on-time mode of control is used, then the output voltage is control by inversely varying the frequency with output voltage. Alternatively, output voltage feedback can be used. 17.3.5i - fixed on-time tT, variable switching frequency fvar

The operating frequency fvar is varied while the switch-on time tT is maintained constant such that the ripple current remains unchanged. Operation is specified by equating the input energy and the output energy, thus maintaining a constant capacitor charge, hence output voltage. That is, equating energies v2 1 (17.70) ½ ∆iL Eiτ = o R f var Isolating the variable switching frequency fvar gives vo2 1 1 f var = = fs Rcrit × R ½ ∆iL Eiτ R 1 f var α (17.71) R Load resistance R is not a directly or readily measurable parameter for feedback proposes. Alternatively, since vo = Io R , substitution for R in equation (17.71) gives

.

.

17.3.6 Output ripple voltage

The output ripple voltage is the capacitor ripple voltage. The ripple voltage for a capacitor is defined as ∆vo =

1 C

∫ i dt = C ∆Q 1

Figure 17.6 shows that for continuous inductor current, the constant output current I o is provided solely from the capacitor during the period tT when the switch is on, thus ∆vo =

1 C

∫ i dt = C1 t

T

Io

Substituting for I o = vo / R gives ∆vo =

1 C

∫ i dt = C1 t

Io =

1 C

tT

vo

R Rearranging gives the percentage voltage ripple (peak to peak) in the output voltage ∆vo δτ (17.76) = vo RC The capacitor equivalent series resistance and inductance can be account for, as with the forward converter, 17.1.4. When the switch conducts, the output current is constant and is provided from the capacitor. Thus no ESL voltage effects result during this constant capacitor current portion of the cycle. T

Example 17.3: Boost (step-up flyback) converter

The boost converter in figure 17.6 is to operate with a 50µs transistor fixed on-time in order to convert the 50 V input up to 75 V at the output. The inductor is 250µH and the resistive load is 2.5Ω. i. Calculate the switching frequency, hence transistor off-time, assuming continuous inductor current. ii. Calculate the mean input and output current. iii. Draw the inductor current, showing the minimum and maximum values.

Power Electronics

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Chapter 17

iv. Calculate the capacitor rms ripple current. v. Derive general expressions relating the operating frequency to varying load resistance. vi. At what load resistance does the instantaneous input current fall below the output current. Solution i. From equation (17.48), which assumes continuous inductor current vo t 1 = where δ = T Ei 1 − δ τ that is 75V 1 50µs 1 = where δ = = 3 τ 50V 1 − δ That is, τ = 150 µs or fs = 1/τ = 6.66 kHz, with a 100µs switch off-time. ii. The mean output current I o is given by I o = vo / R = 75V/2.5Ω = 30A From power transfer considerations I i = I L = vo I o / Ei = 75V×30A/50V = 45A

iii. From v = L di/dt, the ripple current ∆iL = Ei tT /L = 50V x 50µs /250 µH = 10 A

760


that is 2vo2 2×75V 2 = = 22½Ω Ei ∆i 50V×10A Alternatively, equation (17.69) or equation (17.51) can be rearranged to give Rcrit. For a load resistance of less than 22½ Ω, continuous inductor current flows and the operating frequency is fixed at 6.66 kHz with δ = , that is Rcrit =

fs = 6.66 kHz for all R ≤ 22½ Ω

For load resistance greater than 22½ Ω, (< vo /Rcrit = 3⅓A), the energy input occurs in 150 µs burst whence from equation (17.70) v2 1 ½ ∆iL Ei × 150µs = o R f var that is R 1 22½Ω 1 = f var = crit τ R 150µs R 150 f var = kHz for R ≥ 22½ Ω R vi. The ±5A inductor ripple current is independent of the load, provided the critical resistance is not exceeded. When the average inductor current (input current) is less than 5A more than the output current, the capacitor must provide load current not only when the switch is on but also when the switch is off. The transition is given by equation (17.59), that is

that is ∧

i = I L + ½ ∆iL = 45A + ½×10A = 50A L

∨

i = I L − ½ ∆iL = 45A - ½×10A = 40A L

δ ≤ 1− Figure: Example 17.2a

2L

τR

1 2×250µH ≤1 3 150µs × R

This yields R ≥ 7½Ω and a load current of 10A. The average inductor current is 15A, with a minimum value of 10A, the same as the load current. That is, for R < 7½Ω all the load requirement is provided from the input inductor when the switch is off, with excess energy charging (replenishing) the output capacitor. For R > 7½Ω insufficient energy is available from the inductor to provide the load energy throughout the whole of the period when the switch is off. The capacitor supplements the load requirement towards the end of the off period. When R > 22½Ω (the critical resistance), discontinuous inductor current occurs, and the duty cycle dependent transfer function is no longer valid. ♣

iv. The capacitor current is derived by using Kirchhoff’s current law such that at any instant in time, the diode current, plus the capacitor current, plus the 30A constant load current into R, all sum to zero. τ −t ∧  ∆iL 1 t 2 2 iCrms = τ  ∫ 0 I o dt + ∫ 0 (τ − tT t − i + I o ) dt    100 µs  1  50 µs 10A = 30A 2 dt + ∫ ( t − 20A) 2 dt  = 21.3A  0 150µs  ∫ 0 100µs  T

T

L

.

Example 17.4: Alternative boost (step-up flyback) converter

The alternative boost converters (producing a dc supply either above Ei (left) or below 0V (right) – see figure 17.9b) shown in the following figure are to operate under the same conditions as the boost converter in example 17.3, namely, with a 50µs transistor fixed on-time in order to convert the 50 V input up to 75 V at the output. The energy transfer inductor is 250µH and the resistive load is 2.5Ω.

.

ic vC

equal areas (charges) 1.5mC

io = vo /R

io = vo /R

R L

Figure: Example 17.3 - circuits

Figure: Example 17.2b

v. The critical load resistance, Rcrit, produces an input current with ∆iL = 10 A ripple. Since the energy input equals the energy output ½ ∆i × Ei × τ = vo × vo / Rcrit × τ

i.

vC

Derive the voltage transfer ratio and critical resistance expression for the alternative boost converter, hence showing the control performance is identical to the boost converter shown in figure 17.6.

Power Electronics

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Chapter 17

By considering circuit voltage and current waveforms, identify how the two boost converters differ from the conventional boost circuit in figure 17.6. Use example 17.3 for a comparison basis.

ii.

Solution i. Assuming non-zero, continuous inductor current, the inductor current excursion, from v = Ldi/dt, which for this boost converter is not the input current excursion, during the switch on-time tT and switch off-time τ - tT, is given by L∆iL = Ei tT = vC (τ − tT ) but vC = vo − Ei , thus substitution for vC gives Ei tT = ( vo − Ei )(τ − tT ) and after rearranging vo I i 1 δ   : that is vo ≥ Ei alternately Ei + δ vo = vo  = = = 1+ 1− δ Ei I o 1 − δ   where δ = tT /τ and tT is the transistor on-time. This is the same voltage transfer function as for the conventional boost converter, equation (17.48). This result would be expected since both converters have the same ac equivalent circuit. Similarly, the critical resistance would be expected to be the same for each boost converter variation. Examination of the switch on and off states shows that during the switch on-state, energy is transfer to the load from the input supply, independent of switching action. This mechanism is analogous to ac autotransformer action where the output current is due to both transformer action and the input current being directed to the load. The critical load resistance for continuous inductor current is specified by Rcrit ≤ vo / I o . By equating the capacitor net charge flow, the inductor current is related to the output current by I L = I o /(1 − δ ) . At minimum inductor current, I L = ½ ∆iL and substituting with ∆iL = Ei tT / L , gives v vo vo vo 2L Rcrit ≤ o = = = = I o (1 − δ ) I L (1 − δ )½ ∆iL (1 − δ )½ Ei tT / L τδ (1 − δ ) 2 Thus for a given energy throughput, some energy is provided from the supply to the load when providing the inductor energy, hence the discontinuous inductor current threshold occurs at the same load level for each boost converter, including the basic converter in figure 17.6. ii. Since the boost circuits have the same ac equivalent circuit, the inductor and capacitor, currents and voltages would be expected to be basically the same for each circuit, as shown by the waveforms in example 17.3. Consequently, the switch and diode voltages and currents are also the same for each boost converter. The two principal differences are the supply current and the capacitor voltage rating. The capacitor voltage rating for the alternative boost converter is lower, vo - Ei, as opposed to vo for the conventional converter. The supply current for the alternative converter is discontinuous (although always non-zero), as shown in the following waveforms. This will negate the desirable continuous current feature exploited in boost converters that are controlled so as to produce sinusoidal input current or draw continuous input power.


762

An isolated version, with the input supply isolated from the load, is not possible. But the couple inductor version shown in the example figure can be useful in avoiding very short (or long) switch duty cycles and help control (both avoiding or ensuring) continuous inductor current conduction conditions. ♣ 17.4

The buck-boost converter

The basic buck-boost flyback converter circuit is shown in figure 17.7a. When transistor T is on, energy is transferred to the inductor and the load current is provided solely from the output capacitor. When the transistor turns off, inductor current is forced through the diode. Energy stored in L is transferred to C and the load R. This transfer action results in an output voltage of opposite polarity to that of the input. Neither the input nor the output current is continuous, although the inductor current may be continuous or discontinuous.

tD

tD

iC

vC

io = vo /R Ls

Figure 17.7. Non-isolated, step up/down flyback converter (buck-boost converter) where vo ≤ 0:

Lp I su p p ly

17.4.1 Continuous choke (inductor) current

(A )

80 70 30

(a) circuit diagram; (b) waveforms for continuous inductor current; and (c) discontinuous inductor current.

I lo a d

t (µ s )

Figure: Example 17.3 – waveforms and transformer coupled version.

Various circuit voltage and current waveforms for the buck-boost flyback converter operating in a continuous inductor conduction mode are shown in figure 17.7b. Assuming a constant input and output voltage, from v = Ldi/dt, the change in inductor current is given by E −v ∆iL = i tT = o (τ − tT ) (17.77) L L

Power Electronics

763

Thus assuming Pin = Pout, that is v o I o = E i I i vo I i δ = =− 1−δ Ei I o

Chapter 17

17.4.3 Discontinuous choke current

(17.78)

where δ = tT /τ. For δ < ½ the output magnitude is less than the input voltage magnitude, while for δ > ½ the output voltage is greater in magnitude (but as for δ < ½, opposite in polarity) than the input voltage. The maximum and minimum inductor current is given by  ∧ (1- δ )τ  I v 1 + (17.79) i = o + ½ o (1- δ )τ = vo   L 2 L  1−δ  (1 − δ ) R and ∨  (1- δ )τ  I v 1 − i = o − ½ o (1- δ )τ = vo  (17.80)  L 2 L  1−δ  (1 − δ ) R The inductor rms ripple current is given by ∆i 1 vo iL r = L = (17.81) (1- δ ) δτ 2 3 2 3 L while the inductor total rms current is L

∨

The onset of discontinuous inductor operation occurs when the minimum inductor current i L , reaches ∨ zero. That is, with i = 0 in equation (17.80), the last equality (1- δ )τ 1 − =0 (17.88) (1 − δ ) R 2 L L

relates circuit component values (R and L) and operating conditions (f and δ) at the verge of discontinuous inductor current. The change from continuous to discontinuous inductor current conduction occurs when ∧

I L = ½ i = ½ ∆iL

.

2

2 ∨  1  ∧2 ∧ ∨  ½ ∆iL  iL rms = I L2 + iL2r = I L2 +  i L + i L × i L + iL   = 3 3   

(17.82)

.

The switch and diode average and rms currents are given by IT = Ii = δ I L ITrms = δ iL rms I D = (1 − δ ) I L = I o


∧

i = vo (τ − tT ) / L

where from equation (17.77)

L

The circuit waveforms for discontinuous conduction are shown in figure 17.7c. The output voltage for discontinuous conduction is evaluated from ∧ E v i = i t = − o (τ − tT − t x ) (17.90) L L which yields vo δ =− (17.91) t Ei 1−δ − x L

τ

(17.83)

Alternatively, using equation (17.90) and ∧

I i = ½δ i

(17.92)

L

yields

Switch utilisation ratio The switch utilisation ratio, SUR, is a measure of how fully a switching device’s power handling capabilities are utilised in any switching application. The ratio is defined as P SUR = out (17.84) p VT I T

where p is the number of power switches in the circuit; p=1 for the buck-boost converter. The switch maximum instantaneous voltage and current are VT and I T respectively. As shown in figure 17.7b, the maximum switch ∧voltage supported in the off-state is Ei + vo, while the maximum current is the maximum inductor current i which is given by equation (17.79). If the inductance L is large such that the ripple current is small, the peak inductor current is approximated by the average inductor current which yields I T ≈ I L = I o /1 − δ , that is vo I o SUR = = δ (1 − δ ) (17.85) ( Ei + vo ) × I o /1 − δ L

which assumes continuous inductor current. This result shows that the closer the output voltage vo is in magnitude to the input voltage Ei, that is δ = ½, the better the switch I-V ratings are utilised. 17.4.2 Discontinuous capacitor charging current in the switch off-state

It is possible that the inductor current falls below the output (resistor) current during a part of the cycle when the switch is off and the inductor is transferring (replenishing) energy to the output circuit. Under such conditions, towards the end of the off period, some of the load current requirement is provided by the capacitor even though this is the period during which its charge is replenished by inductor energy. The circuit independent transfer function in equation (17.78) remains valid. This discontinuous capacitor charging condition occurs when the minimum inductor current and the output current are equal. That is ∨

IL− Io ≤ 0 I L − ½ ∆iL − I o ≤ 0

(17.89)

L

L

.

(17.86)

Io I R − ½ o (1- δ )τ − I o ≤ 0 L 1− δ

which yields

Eiτδ 2 (17.93) 2L The inductor current is neither the input current nor the output current, but is comprised of separate components (in time) of each of these currents. Examination of figure 17.7b, reveals that these currents are a proportion of the inductor current dependant on the duty cycle, and that on the verge of discontinuous conduction: Ii =

∧

I i = ½δ i

L

and

I o = ½δ off i = ½ (1- δ ) i ∧

∧

L

L L   − 1 +  −1 τR  τR

(17.87)

∧

L

where i = ∆iL L

Thus using power in equals power out, that is Ei I i = vo I o , equation (17.93) becomes vo Eiτδ 2 voτδ 2 τR = = =δ Ei 2L 2 LI o 2 LI i On the verge of discontinuous conduction, these equations can be rearranged to give E v I o = i τδ (1 − δ ) = o τ (1 − δ ) 2 2L 2L

(17.94)

(17.95)

At a low output current or low input voltage there is a likelihood of discontinuous conduction. To avoid this condition, a larger inductance value is needed, which worsen the transient response. Alternatively, with extremely low on-state duty cycles, a voltage-matching transformer can be used to increase δ. Once a transformer is employed, any smps technique can be used to achieve the desired output voltage. Figures 17.7b and c show that both the input and output current are always discontinuous. 17.4.4 Load conditions for discontinuous inductor current

As the load current decreases, the inductor average current also decreases, but the inductor ripple current magnitude is unchanged. If the load resistance is increased sufficiently, the bottom of the ∨ triangular inductor current, i L , eventually reduces to zero. Any further increase in load resistance causes discontinuous inductor current and the voltage transfer function given by equation (17.78) is no longer valid and equations (17.90) and (17.94) are applicable. The critical load resistance for continuous inductor current is specified by v (17.96) Rcrit ≤ o Io ∧

2

δ ≤ 1+

764


Substituting for, the average input current in terms of i yields

L

and vo in terms of ∆iL from equation (17.77),

Power Electronics

765

vo 2L (17.97) = I o τ (1 − δ ) 2 By substituting the switching frequency ( f s = 1/ τ ) or the fundamental inductor reactance ( X L = 2π f s L ) the following critical resistance forms result. v v 2 fs L XL 2L 2L Rcrit ≤ o = (Ω ) = o × = = (17.98) I o τ (1 − δ ) 2 Ei τδ (1 − δ ) (1 − δ ) 2 π (1 − δ ) 2 Equation (17.98) is equation (17.88), re-arranged. Rcrit ≤

If the load resistance increases beyond Rcrit, the output voltage can no longer be maintained with duty cycle control according to the voltage transfer function in equation (17.78).

Chapter 17

Isolating the variable on-time tTvar gives vo2 1 ½ ∆i L E i f s R Substituting ∆iL from equation (17.77) gives 1 tT var = tT Rcrit × R (17.103) 1 tT var α R Again, load resistance R is not a directly or readily measurable parameter for feedback proposes and substitution of vo / Io for R in equation (17.74) gives tT var =

.

.

tT var = tT


Once the load current has reduced to the critical level as specified by equation (17.98), the input energy is in excess of the load requirement. Open loop load voltage regulation control is lost and the capacitor C tends to overcharge. Hardware approaches can solve this problem – by ensuring continuous inductor current • increase L thereby decreasing the inductor current ripple p-p magnitude • step-down transformer impedance matching to effectively reduce the apparent load impedance Two control approaches to maintain output voltage regulation when R > Rcrit are • vary the switching frequency fs, maintaining the switch on-time tT constant so that ∆iL is fixed or • reduce the switch on-time tT , but maintain a constant switching frequency fs, thereby reducing ∆iL. If a fixed switching frequency is desired for all modes of operation, then reduced on-time control, using output voltage feedback, is preferred. If a fixed on-time mode of control is used, then the output voltage is control by inversely varying the frequency with output voltage. Alternatively, output voltage feedback can be used. 17.4.5i - fixed on-time tT, variable switching frequency fvar

The operating frequency fvar is varied while the switch-on time tT is maintained constant such that the ripple current remains unchanged. Operation is specified by equating the input energy and the output energy, thus maintaining a constant capacitor charge, hence output voltage. That is, equating energies v2 1 ½ ∆iL Ei tT = o (17.99) R f var Isolating the variable switching frequency fvar gives vo2 1 1 = fs Rcrit × f var = ½ ∆iL Ei tT R R 1 (17.100) R Load resistance R is not a directly or readily measurable parameter for feedback proposes. Alternatively, since vo = Io R , substitution for R in equation (17.100) gives R f var = f s crit × Io vo (17.101)

α

f var

f var

α

Io

That is, for discontinuous inductor current, namely I L < ½ ∆iL or Io < vo / Rcrit , if the switch on-state period tT remains constant and fvar is either varied proportionally with load current or varied inversely with load resistance, then the required output voltage vo will be maintained.

766


Rcrit × vo

.

Io

(17.104)

tT var α Io That is, if the switching frequency fs is fixed and switch on-time tT is reduced proportionally to Io or inversely to R , when discontinuous inductor current commences, namely I L < ½∆iL or Io < vo / Rcrit , then the required output voltage magnitude vo will be maintained. .

.

.

Alternatively the output voltage is related to the duty cycle by vo = −δ Ei Rτ / 2 L . See table 17.2. 17.4.6 Output ripple voltage

The output ripple voltage is the capacitor ripple voltage. Ripple voltage for a capacitor is defined as ∆vo =

∫ i dt

1 C

Figure 17.7 shows that the constant output current I o is provided solely from the capacitor during the on period tT when the switch conducting, thus ∆vo =

1 C

∫ i dt = C1 t

T

Io

Substituting for I o = vo / R gives ∆vo =

1 C

∫ i dt = C1 t

Io =

1 C

tT

vo

R Rearranging gives the percentage peak-to-peak voltage ripple in the output voltage ∆vo (17.105) = 1 tT = δ τ RC RC vo The capacitor equivalent series resistance and inductance can be account for, as with the forward converter, 17.1.5. When the switch conducts, the output current is constant and is provided solely from the capacitor. Thus no ESL voltage effects result during this constant capacitor current portion of the switching cycle. T

17.4.7 Buck-boost, flyback converter design procedure

The output voltage of the buck-boost converter can be regulated by operating at a fixed frequency and varying the transistor on-time tT. However, the output voltage diminishes while the transistor is on and increases when the transistor is off. This characteristic makes the converter difficult to control on a fixed frequency basis. A simple approach to control the flyback regulator in the discontinuous mode is to fix the peak inductor current, which specifies a fixed diode conduction time, tD. Frequency then varies directly with output current and transistor on-time varies inversely with input voltage. With discontinuous inductor conduction, the worst-case condition exists when the input voltage is low while the output current is at a maximum. Then the frequency is a maximum and the dead time tx is zero because the transistor turns on as soon as the diode stops conducting. Given Worst case

17.4.5ii - fixed switching frequency fs, variable on-time tTvar

Ei (min)

Io (max)

The operating frequency fs remains fixed while the switch-on time tTvar is reduced such that the ripple current can be reduced. Operation is specified by equating the input energy and the output energy as in equation (17.99), thus maintaining a constant capacitor charge, hence voltage. That is v2 1 ½ ∆iL Ei tT var = o (17.102) R fs

Vo

f (max)

Ei = Ei (min) ∆eo

tx = 0

Io = Io(max)

∧

Assuming a fixed peak inductor current i and output voltage vo, the following equations are valid i

∧

Ei (min)tT = votD = i × L

(17.106)

τ (min) = 1/ f (max)

(17.107)

i

Power Electronics

767

Chapter 17

768


Solution

Equation (17.106) yields tD =

1 v f (max) ( o + 1) Ei (min)

(17.108) ∧

Where the diode conduction time tD is constant since in equation (17.106), v0, i , and L are all constants. The average output capacitor current is given by i

∧

Io = ½ i (1 − δ ) and substituting equation (17.108) yields i

∧

Io (max) = ½ i × f (max) × i

1 v f (max) ( o + 1) Ei (min)

i. From equation (17.91), which assumes continuous inductor current vo δ =− where δ = tT / τ Ei 1−δ that is 75V δ = thus δ = 3 5 50V 1 − δ That is, τ = 1/ fs = 100 µs with a 60µs switch on-time. ii. The mean output current I o is given by I o = vo / R = 75V/2.5Ω = 30A From power transfer considerations I i = vo I o / Ei = 75V×30A/50V = 45A

therefore ∧

i = 2 × Io (max) × ( i

vo + 1) Ei (min)

and upon substitution into equation (17.106) tD vo L= v 2 Io (max) ( o + 1) Ei (min)

iL (A)

(17.109)

80

∨

C=

10A

75

∧

IT

∆Q i t D = ∆eo 2∆eo

ID

i

0

Io (max) t D C= v ∆eo ( o + 1) Ei (min)

IT

ID

60µs

that is ∨

IL=75A

70

The minimum capacitance is specified by the maximum allowable ripple voltage, that is

50

100

150

t (µs)

iC (A)

(17.110)

Io=30A

30 1.8mC

For large output capacitance, the ripple voltage is dropped across the capacitor equivalent series resistance, which is given by ∆e ESR(max) = ∧ o (17.111) i The frequency varies as a function of load current. Equation (17.107) gives ∧ Io (max) Io = ½ i tT = f f (max) therefore I f = f (max) × o (17.112) Io (max) and I f (min) = f (max) × o (min) (17.113) Io (max)

0 0

50

100

150

t (µs)

1.8mC

i

40

i

50

Figure: Example 17.4

iii. The average inductor current can be derived from I i = δ I L or I o =(1- δ ) I L That is I L = I i /δ = I o /(1- δ ) = 45A/ 3 5 = 30A/ 2 5 = 75A From v = L di/dt, the ripple current ∆iL = Ei tT /L = 50V x 60µs /300 µH = 10 A, that is

Example 17.5: Buck-boost flyback converter

∧

i L = I L + ½ ∆iL = 75A + ½×10A = 80A

The 10kHz flyback converter in figure 17.7 is to operate from a 50V input and produces an inverted nonisolated 75V output. The inductor is 300µH and the resistive load is 2.5Ω.

∨

i L = I L − ½ ∆iL = 75A - ½×10A = 70A

∨

Calculate the duty cycle, hence transistor off-time, assuming continuous inductor current. Calculate the mean input and output current. Draw the inductor current, showing the minimum and maximum values. Calculate the capacitor rms ripple current and output p-p ripple voltage if C = 10,000µF. Determine • the critical load resistance. • the minimum inductance for continuous inductor conduction with 2.5 Ω load vi. At what load resistance does the instantaneous inductor current fall below the output current? vii. What is the output voltage if the load resistance is increased to four times the critical resistance? i. ii. iii. iv. v.

Since i L = 70A ≥ 0A, rhe inductor current is continuous, thus the analysis in parts i, ii, and iii, is valid. iv. The capacitor current is derived by using Kirchhoff’s current law such that at any instant in time, the diode current, plus the capacitor current, plus the 30A constant load current into R, all sum to zero. τ −t ∧  ∆iL 1 t 2 2 iCrms = τ  ∫ 0 I o dt + ∫ 0 (τ − tT t − i + I o ) dt    40 µs 10A  1  60 µs 2 = t − 50A) 2 dt  = 36.8A 30A dt + ∫ (  0 100µs  ∫ 0 40µs  T

T

L

.

.

Power Electronics

769

The output ripple voltage is given by equation (17.105), that is 3 ∆vo δτ 5 × 100µs = = ≡ 0.24% vo CR 10, 000µF × 2½ Ω The output ripple voltage is therefore ∆vo = 0.24 × 10−2 × 75V = 180mV v. The critical load resistance, Rcrit, produces an inductor current with ∆iL = 10 A ripple. From equation (17.98) 2L 2×300µH = Rcrit = = 37½Ω τ (1 − δ ) 2 100µs × (1- 35 ) 2

The minimum inductance for continuous inductor current operation, with a 2½Ω load, can be found by rearranging the critical resistance formula, as follows: Lcrit = ½ Rτ (1 − δ ) 2 = ½×2.5Ω×100µs×(1- 3 5 ) 2 = 20µH vi. The ± 5A inductor ripple current is independent of the load, provided the critical resistance of 37½Ω is not exceeded. When the average inductor current is less than 5A more than the output current, the capacitor must provide load current not only when the switch is on but also for a portion of the time when the switch is off. The transition is given by equation (17.87), that is

Chapter 17

v1

½

I1 1

Ii

δ

-

-δ 1-δ

+ I1

1 − f (δ ) v1

+

vo

Ismps

f(δ)

Ei

Ei

vo

Io +

vo = Ei ×

1 1-δ

(a)

boost output

Ei

1

I1

vo = δEi Ii v1= (1-δ)Ei

v 1 = E i × (1 − δ )

+

1 − f (δ ) v1

+ Ei

Ei

I1 vo

f(δ)

Ismps

Io +

vo = Ei ×δ

(b)

buck output

δ

0

½

2

Alternately, when

1

Figure 17.8. Basic converters shown as a three-port block diagrams for: (a) the flyback converter and (b) the forward converter.

I L − I o = 5A Io − I o = 5A 1−δ For δ = ⅗, I o = 3⅓A. whence v 75V R= o = = 22½Ω I o 10 3 A

The average inductor current is 8⅓A, with a minimum value of 3⅓A, the same as the load current. That is, for R < 22½Ω all the load requirement is provided from the inductor when the switch is off, with excess energy charging the output capacitor. For R > 22½Ω insufficient energy is available from the inductor to provide the load energy throughout the whole of the period when the switch is off. The capacitor supplements the load requirement towards the end of the off period. When R > 37½Ω (the critical resistance), discontinuous inductor current occurs, and the purely duty cycle dependent transfer function (circuit parameter independent) is no longer valid. vii. When the load resistance is increased to 150Ω, four times the critical resistance, the output voltage is given by equation (17.94): τR 100µs × 150Ω vo = Ei δ = 50V × 3 5 × = 150V 2L 2 × 300µH

♣ Flyback converters – a conceptual assessment

In section 17.2, the boost and buck-boost converters were both introduced as flyback or ringing choke converters. This is not the traditional approach adopted to the classification of these two converters. This text has classified both as flyback converters since they are in fact the same converter. A converter is considered a two port network – an input Ei and an output vo – that are related by a transfer function which is expressed in terms of the switch on-state duty cycle δ.

vo = f (δ ) Ei A second output v1 exists between the input Ei and the output vo, as shown in figure 17.8. By Kirchhoff’s voltage law, this auxiliary output is v 1 = E i −v o

v v1 = 1 − o = 1 − f (δ ) Ei Ei

v1 = Ei ×

Ei

1

L L   δ ≤ 1+ − 1 +  −1 τR  τR

17.5

buck-boost output

v

-1

770


The flyback converter – figure 17.8a If f(δ) represents a boost converter, with a voltage transfer function 1/ 1- δ, then 1 - f(δ) = - δ /1- δ, which is the buck-boost converter transfer function. The converse is also true. Thus if a boost converter output exists, a buck-boost output is inherently available, independent of the connection position of the output capacitor Co. In terms of dc circuit theory, the output capacitor can be connected across vo (as in figure 17.2), v1 (as in example 17.3), or apportioned between both outputs. The circuit permutations in figure 17.9 show how the boost converter, using ac and dc circuit theory, can be systematically translated to the buck-boost converter, and vice versa. The schematic of an auto-transformer (variac) is interposed since it too can provide the equivalent two ac output possibilities. Whether a dc converter or an ac variac, power can be drawn from either output separately or from both outputs simultaneously. The output ports of both converters, when an extra switch and diode are added, are bidirectional reversible as considered in section 17.7.2. The forward converter – figure 17.8b Just as the boost and buck-boost outputs are complementary, the buck converter has a complementary output possibility. If the output vo is defined by the buck converter transfer function δ then the supplementary output v1 is defined by 1-δ. The output 1-δ cannot exist independently of the output δ. In order to maintain output voltage transfer function integrity according to the duty cycle dependant transfer functions, the current sourced from port vo (the buck output) must exceed the current sunk by port v1. That is, if the outputs vo and v1 are resistively loaded, in figure 17.8a I smps > 0

Io ≥ I1 vo v1 ≥ Ro R1 or

R1 ≥ Ro

1−δ

δ

Notice in figure 17.8a, in the flyback converter case, Ismps is always positive. Therefore no load resistance restrictions exist for the two outputs, save the inductor current is continuous. Thus only two fundamental single-switch, single-inductor converters (flyback and forward) exist, each offering two output voltage transfer function possibilities. One of the four output possibilities, 1- δ, cannot uniquely exist.

771

Power Electronics

Chapter 17

17.6

772


The output reversible converter

The basic reversible converter, sometimes called an asymmetrical half bridge converter (see chapter 14.5), shown in figure 17.10a allows two-quadrant output voltage operation. Operation is characterised by both switches operating simultaneously, being either both on or both off. The input voltage Ei is chopped by switches T1 and T2, and because the input voltage is greater than the load voltage vo, energy is transferred from the dc supply Ei to L, C, and the load R. When the switches are turned off, energy stored in L is transferred via the diodes D1 and D2 to C and the load R but in a path involving energy being returned to the supply, Ei. This connection feature allows energy to be transferred from the load back into Ei when used with an appropriate load and the correct duty cycle. Parts b and c respectively of figure 17.10 illustrate reversible converter circuit current and voltage waveforms for continuous and discontinuous conduction of L, in a forward converter mode, when δ > ½.

T1

+

D1 D2 T2 (a) ON

switch period iL Io ∨ iL

T

D

tT

T

tD

D tD

tT io

τ

t

iL

tx

τ

t

ii

∨

iL t

∨

-iL

t iD

iL ∨

iL t

Ei

t

vD

t (b)

t (c)

Figure 17.10. Basic reversible converter with δ>½: (a) circuit diagram; (b) waveforms for continuous inductor current; and (c) discontinuous inductor current.

For analysis it is assumed that components are lossless and the output voltage vo is maintained constant because of the large capacitance magnitude of the capacitor C across the output. The input voltage Ei is also assumed constant, such that Ei ≥ vo > 0, as shown in figure 17.10a. 17.6.1 Continuous inductor current

Figure 17.9. Basic: (a) boost to (e) buck-boost converter systematic translations.

When the switches are turned on for period tT, the difference between the supply voltage Ei and the output voltage v0 is impressed across L. From V = Ldi/dt, the rising current change through the inductor will be ∧ ∨ E −v ∆iL = i L − i L = i o × tΤ (17.114) L

Power Electronics

773

Chapter 17

When the two switches are turned off for the remainder of the switching period, τ - tT, the two freewheel diodes conduct in series and Ei + vo is impressed across L. Thus, assuming continuous inductor conduction the inductor current fall is given by E +v ∆iL = i o × (τ − tΤ ) (17.115) L Equating equations (17.114) and (17.115) yields vo I i 2t − τ 0 ≤ δ ≤1 (17.116) = = T = 2δ − 1 τ Ei I o The voltage transfer function is independent of circuit inductance L and capacitance C. Equation (17.116) shows that for a given input voltage, the output voltage is determined by the transistor conduction duty cycle δ and the output voltage |vo| is always less than the input voltage. This confirms and validates the original analysis assumption that Ei ≥ |vo|. The linear transfer function varies between 1 and 1 for 0 ≤ δ ≤ 1, that is, the output can be varied between vo = - Ei, and vo = Ei. The significance of the change in transfer function polarity at δ = ½ is that • for δ > ½ the converter acts as a forward converter, but • for δ < ½, if the output is a negative source, the converter acts as a boost converter with energy transferred to the supply Ei, from the negative output source. Thus the transfer function can be expressed as follows vo I i = = 2δ − 1 = 2 (δ − ½) ½ ≤ δ ≤1 Ei I o and Ei I o 1 1 = = = 0≤δ ≤ ½ vo I i 2δ − 1 2 (δ − ½) where equation (17.118) is in the boost converter transfer function form.

(17.117)

(17.118)

774

vo (2δ − 1) L (17.124) = Io (1 − δ )δτ By substituting the switching frequency ( f s = 1/ τ ) or the fundamental inductor reactance ( X L = 2π f s L ), critical resistance can be expressed in the following forms. v 2(δ − ½ ) L 2(δ − ½ ) fs L (δ − ½ ) XL (17.125) = = Rcrit ≤ o = (Ω ) π (1 − δ )δ Io (1 − δ )δτ (1 − δ )δ If the load resistance increases beyond Rcrit, the output voltage can no longer be maintained with duty cycle control according to the voltage transfer function in equation (17.116). Rcrit ≤


Once the load current has reduced to the critical level as specified by equation (17.120) the input energy is in excess of the load requirement. Open loop load voltage regulation control is lost and the capacitor C tends to overcharge. As with the other converters considered, hardware and control approaches can mitigate this overcharging problem. The specific control solutions for the forward converter in section 17.3.4, are applicable to the reversible converter. The two time domain control approaches offer the following operational modes. 17.6.4i - fixed on-time tT, variable switching frequency fvar

The operating frequency fvar is varied while the switch-on time tT is maintained constant such that the magnitude of the ripple current remains unchanged. Operation is specified by equating the input energy and the output energy, thus maintaining a constant capacitor charge, hence output voltage. That is, equating energies v2 1 (17.126) ½ ∆iL Ei tT = o R f var Isolating the variable switching frequency fvar and using vo = Io R to eliminate R yields


In the forward converter mode,∨ δ ≥ ½, the onset of discontinuous inductor current operation occurs when the minimum inductor current i L , reaches zero. That is, I L = ½ ∆i L = I o (17.119) If the transistor on-time tT is reduced or the load resistance increases, the discontinuous condition dead ∨ time tx appears as indicated in figure 17.10c. From equations (17.114) and (17.115), with i = 0 , the following output voltage transfer function can be derived ∧ E −v E +v (17.120) ∆iL = i L − 0 = i o × tΤ = i o × (τ − tΤ − t x ) L L which after rearranging yields L

tx vo 2δ − 1 − τ = t Ei 1 − τx


0 ≤δ ½ and provides part of the voltage function of the buck-boost converter when δ < ½ but with energy transferring in the opposite direction. Comparison of example 17.1 and 17.5 shows that although the same output voltage range can be achieved, the inductor ripple current is much larger for a given inductance L. A similar result occurs when compared with the buck-boost converter. Thus in each case, the reversible converter has a narrower output resistance range before discontinuous inductor conduction occurs. It is therefore concluded that the reversible converter should only be used if two quadrant operation is needed. ∼ The ripple current I f given by equation (17.2) for the forward converter and equation (17.114) for the reversible converter when vo > 0, yield the following current ripple relationship. I f = (2 − 1/ δ r ) × I r (17.130) where 2δ r − 1 = δ f for 0 ≤ δ f ≤ 1 and ½ ≤ δ r ≤ 1 ∼

This equation shows that the ripple current of the forward converter I f is never greater than the ripple ∼ current I r for the reversible converter, for the same output voltage. In the voltage inverting mode, from equations (17.77) and (17.114), the relationship between the two corresponding ripple currents is given by 2(δ r − 1) × Ir I fly = 2δ r − 1 (17.131) 2(δ r − 1) = δ fly for 0 ≤ δ fly ≤ ½ and 0 ≤ δ r ≤ ½ where 2δ r − 1

Power Electronics

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Chapter 17

Again the reversible converter always has the higher inductor ripple current. Essentially the higher ripple current results in each mode because the inductor energy release phase involving the diodes, occurs back into the supply, which is effectively in cumulative series with the output capacitor voltage. The reversible converter offers some functional flexibility, since it can operate as a conventional forward converter, when only one of the two switches is turned off. (In fact, in this mode, switch turn-off is alternated between T1 and T2 so as to balance switch and diode losses.)

17.7

The Ćuk converter

The Ćuk converter in figure 17.11 performs an inverting boost converter function with inductance in the input and the output. As a result, both the input and output currents can be continuous. A capacitor is used in the process of transferring energy from the input to the output and ac couples the input boost converter stage (L1, T) to the output forward converter (D, L2). Specifically, the capacitor C1 ac couples the switch T in the boost converter stage into the output forward converter stage. 17.7.1 Continuous inductor current


778

I i = I L1 ≥ ½ ∆iL1 (17.139) which yields a maximum allowable load resistance, for continuous inductor current, of v 2 f Lδ 2δ L1 δ X L1 Rcrit ≤ o = = s 1 = (17.140) I o τ (1 − δ ) 2 (1 − δ ) 2 π (1 − δ ) 2 This is the same expression as that obtained for the boost converter, equation (17.69), which can be rearranged to give the minimum inductance for continuous input inductor current, namely 2 ∨ (1 − δ ) Rτ (17.141) L1 = 2δ The current rise in L2 occurs when the switch is on and the inductor voltage is Ei, that is δτ Ei (17.142) ∆i L 2 = L2 For continuous current in the output inductor L2, I o = I L 2 ≥ ½ ∆i L 2 (17.143) which yields X 2 f s L2 v 2 L2 Rcrit ≤ o = = = (17.144) I o τ (1 − δ ) (1 − δ ) π (1 − δ ) This is the same expression as that obtained for the forward converter, equation (17.26) which can be rearranged to give the minimum inductance for continuous output inductor current, namely L2

When the switch T is on and the diode D is reversed biased iC 1( on ) = − I L 2 = I o

(17.132)

When the switch is turned off, inductor currents iL1 and iL2 are divert through the diode and iC 1(off) = I i

(17.133)

∨

L 2 = ½ (1 − δ ) Rτ

(17.145)

17.7.3 Optimal inductance relationship C1

L1

Optimal inductor conditions are that both inductors should both simultaneous reach the verge of discontinuous conduction. The relationship between inductance and ripple current is given by equations (17.138) and (17.142). δτ Ei δτ Ei ∆iL1 = and ∆iL 2 = L1 L2 After diving these two equations L2 ∆iL1 = (17.146) L1 ∆iL 2 Critical inductance is given by equations (17.141) and (17.145), that is 2 ∨ ∨ (1 − δ ) Rτ L 2 = ½ (1 − δ ) Rτ and L1 = 2δ After dividing

L2

vo

C2 -

Figure 17.11. Basic Ćuk converter.

∨

L2

Over one steady-state cycle the average capacitor charge is zero, that is iC 1(on)δτ + iC 1(off) (1 − δ )τ = 0

(17.134)

which gives iC 1(on) iC 1(off)

δ

I = = i (1 − δ ) I o

(17.135)

From power-in equals power-out vo I I = i = L1 Ei I o I L 2

Thus equation (17.135) becomes vo I I δ = i = L1 = − Ei I o I L 2 (1 − δ )

(17.136)

(17.137)


The current rise in L1 occurs when the switch is on, that is δτ Ei ∆i L 1 = L1 For continuous current in the input inductor L1,

(17.138)

δ

= ∨ L1 1 − δ At the verge of simultaneous discontinuous inductor conduction

(17.147)

∨

v ∆i δ (17.148) = = L1 = o ∨ Ei L1 1 − δ ∆iL 2 That is, the voltage transfer ratio uniquely specifies the ratio of the minimum inductances and their ripple current. L2

17.7.4 Output voltage ripple

The output stage (L2, C2, and R) is the forward converter output stage; hence the per unit output voltage ripple on C2 is given by equation (17.35), that is ∆vC 2 ∆vo 1 (1 − δ )τ 2 (17.149) = = 8× vo vo L2 C2 If the ripple current in L1 is assumed constant, the per unit voltage ripple on the ac coupling capacitor C1 is approximated by ∆vC1 δτ (17.150) = vo R C1

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Example 17.7: Ćuk converter

The Ćuk converter in figure 17.11 is to operate at 10kHz from a 50V battery input and produces an inverted non-isolated 75V output. The load power is 1.8kW. Calculate the duty cycle hence switch on and off times, assuming continuous current in both inductors. ii. Calculate the mean input and output, hence inductor, currents. iii. At the 1.8kW load level, calculate the inductances L1 and L2 such that the ripple current is 1A p-p in each. iv. Specify the capacitance for C1 and C2 if the ripple voltage is to be a maximum of 1% of the output voltage. v. Determine the critical load resistance for which the purely duty cycle dependant voltage transfer function becomes invalid. vi. At the critical load resistance value, determine the inductance value to which the noncritically operating inductor can be reduced. vii. Determine the necessary conditions to ensure that both inductors operate simultaneously on the verge of discontinuous conduction, and the relative ripple currents for that condition. i.

Solution

The voltage transfer function is given by equation (17.137), that is vo δ 75V =− =− = −1½ (1 − δ ) 50V Ei from which δ = 3 5 . For a 10kHz switching frequency the period is 100µs, thus the switch on-time is 60µs and the off-time is 40µs. i.

ii. The mean output current is determined by the load and the mean input current is related to the output current by assuming 100% efficiency, that is I o = I L 2 = Po / vo = 1800W / 75V = 24A I i = I L1 = Po / Ei = 1800W / 50V = 36A

The load resistance is therefore R = vo /Io = 75V/24A = 3⅛Ω. iii.

The inductor ripple current for each inductor is given by the same expression, that is equations (17.138) and (17.142). Thus for the same ripple current of 1A pp δτ Ei δτ Ei ∆iL1 = = ∆iL 2 = L1 L2 which gives δτ Ei 35 × 100µs × 50V L1 = L2 = = = 3mH ∆i 1A

iv.

The capacitor ripple voltages are given by equations (17.150) and (17.149), which after rearranging gives v δ τ 100 35 ×100µs = × = 1.92mF C1 = o × 25 ∆vC1 R 1 8Ω C2 =

vo (1 − δ )τ 2 100 1 (1 − 35 ) × 100µs 2 × 18 × = × 8× = 16.6µF ∆vC 2 L2 1 3mH

The critical load resistance for each inductor is given by equations (17.140) and (17.144). When both inductors are 3mH: 2δ L1 2 × 35 × 3mH = = 225Ω Rcrit ≤ τ (1 − δ ) 2 100µs × (1 − 35 ) 2 2 L2 2 × 3mH = = 150Ω Rcrit ≤ τ (1 − δ ) 100µs × (1 − 35 ) The limiting critical load resistance is 150Ω or for Io = vo /R = 75V/150Ω = ½A, when a lower output current results in the current in L2 becoming discontinuous although the current in L1 is still continuous. v.

Chapter 17

vi.


780

From equation (17.140), rearranged τ R(1 − δ ) 2 100µs × 100Ω × (1 − 35 ) 2 = = 2mH L1 crit ≥ 2δ 2 × 35 That is, if L1 is reduced from 3mH to 2mH, then both L1 and L2 enter discontinuous conduction at the same load condition, 75V, ½A, and 150Ω.

vii. For both converter inductors to be simultaneously on the verge of discontinuous conduction, equation (17.148) gives ∨

v ∆i δ = = L1 = o ∨ Ei L1 1 − δ ∆iL 2 3 3mH 1A 75V 3 5 = = = = 2mH 1 − 3 5 2 3 A 50V 2 ♣ L2

17.8

Comparison of basic converters

The converters considered employ an inductor to transfer energy from one dc voltage level to another dc voltage level. The basic converters comprise a switch, diode, inductor, and a capacitor. The reversible converter is a two-quadrant converter with two switches and two diodes, while the Ćuk converter uses two inductors and two capacitors. Table 17.1 summarises the main electrical features and characteristics of each basic converter. Figure 17.12 shows a plot of the voltage transformation ratios and the switch utilisation ratios of the converters considered. With reference to figure 17.12, it should be noted that the flyback step-up/stepdown converter and the Ćuk converter both invert the input polarity. Every converter can operate in any one of three inductor current modes: • • •

discontinuous continuous both continuous and discontinuous

The main converter operational features of continuous conduction compared with discontinuous inductor conduction are • The voltage transformation ratio (transfer function) is independent of the load. • Larger inductance but lower core hysteresis losses and saturation less likely. • Higher converter costs with increased volume and weight. • Worse transient response (L /R). • Power delivered is inversely proportional to load resistance, P = Vo 2 / R . In the discontinuous conduction mode, power delivery is inversely dependent on inductance. 17.8.1 Critical load current

Examination of Table 17.1 shows no obvious commonality between the various converters and their performance factors and parameters. One common feature is the relationship between critical average output current Io and the input voltage Ei at the boundary of continuous and discontinuous conduction. Equations (17.14), (17.65), and (17.95) are identical, (for all smps), that is Eτ = i δ (1 − δ ) (A) (17.151) Io 2L This quadratic expression in δ shows that the critical mean output current reduces to zero as the on-state duty cycle δ tends to zero or unity. The maximum critical load current condition, for a given input voltage Ei, is when δ = ½ and critical

I oc = Eiτ / 8L

(17.152)

Since power-in equals power-out, then from equation (17.151) the input average current and output voltage at the boundary of continuous conduction for all smps are related by vτ = o δ (1 − δ ) (A) (17.153) Ii 2L The maximum output current at the boundary (at δ = ½), for a given output voltage, vo, is critical

I ic = voτ / 8 L

(17.154)

Power Electronics

781

The smps commonality factor reduces to Rcrit =

Chapter 17

vo 2L × . E i τ δ (1 − δ )

Table 17.1: Converter characteristics comparison with continuous inductor current

The reversible converter, using the critical resistance equation (17.125) derived in section 17.6.3, yields twice the critical average output current given by equation (17.151). This is because its duty cycle range is restricted to half that of the other converters considered. Converter normalised equations for discontinuous conduction are shown in table 17.2. A detailed analysis summary of discontinuous inductor current operation is given in Appendix 17.11.

converter Forward Step-down Output voltage continuous I

vo /Ei

Output voltage discontinuous I

vo /Ei

δ 1−

Output polarity with respect to input Current sampled from the supply Maximum transistor voltage Maximum diode voltage

¾

½

buck-boost /Cuk 2 reversible 4

¼

full bridge

¼

½

¾

2δ − 1

1−δ Eiδ 2τ 2 LI o

Non-inverted

inverted

any

discontinuous

continuous

discontinuous

bi-directional

continuous

discontinuous

discontinuous

continuous

V

Ei

vo

Ei + vo

Ei

V

Ei

vo

Ei + vo

Ei

Ripple current

∆i

A

Eiδτ (1 − δ ) / L

Eiδτ / L

2 Eiδτ (1 − δ ) / L

Maximum transistor current

iˆT

A

Io +

voτ (1 − δ ) 2L

SUR

Eiδτ / L Ii +

Eiτδ 2L

IL +

Eiτδ 2L

Io +

( Ei − vo )τδ 2L

δ

1-δ

δ (1-δ)

low

high

high

low

2L τδ (1 − δ ) 2

2L τ (1 − δ ) 2

2(δ − ½ ) L τδ (1 − δ )

½ Rτδ (1 − δ ) 2

½ Rτ (1 − δ ) 2

½ R (1 − δ )δτ (δ − ½ )

Critical load resistance

Rcrit

Ω

2L τ (1 − δ )

Critical inductance

Lcrit

H

½ R (1 − δ )τ

o/p ripple voltage

∆vo

V

k=

0

−

Reversible

δ

τ 2 (1 − δ ) 8LC

vo

τδ RC

τδ

vo

RC

½δ

τδ

vo

RC

vo

Table 17.2: Comparison of characteristics when the inductor current is discontinuous, δ < δ critical

step-down 3

Po / PT

Flyback Step-up/down

1 1− δ E δ 2t 1+ i T 2L I o

V

p-p

step-up 1

Flyback Step-up

V

switch utilisation ratio Transistor rms current

1

2 LI i Eiδ 2τ

Non-inverted

Load current

& Cuk

782


1

δ = tT/τ Figure 17.12. Transformation voltage ratios and switch utilisation ratios for five converters when operated in the continuous inductor conduction mode.

t Rτ ; δ= T τ L

δ critical ( k ) = vo IoR ( k,δ ) = Ei Ei

δD =

tD

δx =

tx

τ τ

( k,δ ) ( k,δ )

Forward step-down

δ ≤ 1−

 8  ¼ kδ 2  −1 + 1 + 2  kδ    v  v δ × 1 − o  / o Ei  Ei  1− δ/

= 1− δ − δD ∧

I L×

R ( k,δ ) Ei

2 k



vo Ei

k δ × 1 − 

vo   Ei 

converter Flyback step-up

k>

27 2 2 then δ (1 − δ ) ≤ k 2

½ 1 + 1 + 2kδ 2   

v o

δ /

Ei

1−δ ×

 − 1 

vo v Ei / o −1 Ei

kδ

Flyback step-up/down

δ ≤ 1−

2 k

−δ ½ k

δ/

vo Ei

 vo  v  o 1 − δ  1 + E i  / E  i

kδ

Power Electronics

783

Ii Io Ei

Chapter 17

Ton

+

Ii +

δ 1-δ

•

Io

L

R

vo

C Toff

• Ii Io Ei

Io

L

Ton

Toff

+

Ii +

1-δ δ

Io

∆vC (1 − δ )τ 2 = vo 8 LC

vo

∆vC δτ = vo RC

Io Ton

+

Figure 17.14a illustrates an isolated version of the forward converter shown in figure 17.2. When the transistor is turned on, diode D1 conducts and L in the transformer secondary stores energy. When the transistor turns off, the diode D3 provides a current path for the release of the energy stored in L. However when the transistor turns off and D1 ceases to conduct, the stored transformer magnetising energy must be released. The winding incorporating D2 provides a path to reset the core flux. A maximum possible duty cycle exists, depending on the turns ratio of the primary winding and freewheel winding. If a 1:1 ratio (as shown) is employed, a 50 per cent duty cycle limit will ensure the required volts-second for core reset. The step-up flyback isolated converter in part b of figure 17.14 is little used. The two transistors must be driven by complementary signals. Core leakage and reset functions (and no-load operation) are facilitated by a third winding and blocking diode D2.

C

Ii

Ei

R

784


Ii

Toff

C

δ L

R

vo

1-δ +

∆vC δτ = vo RC

Figure 17.13. The three basic bidirectional current converter configurations: (a) the forward converter; (b) step-up flyback converter; and (c) step up/down flyback converter.

17.8.2 Bidirectional converters

Discontinuous inductor current can be avoided if the smps diode is parallel connected with a shunt switch as shown in figure 17.13. If the switch has bipolar conduction properties, as with the MOSFET, then it can perform three functions • Synchronised rectification: If the shunting switch conducts when the diode conducts, during period δD, then the diode is bypassed and losses are reduced to those of the MOSFET, which can be less than those of a Schottky diode. • Guaranteed continuous inductor current conduction: If the shunting switch conducts for the period 1- δD, (complement to the main smps switch) then if the inductor current falls to zero, that current can reverse with energy taken from the output capacitor. Seamless, continuous inductor current results and importantly, the voltage transfer function is then that for continuous inductor current, independent of the load resistance. • Bidirectional energy transfer: If the output diode has a shunting switch and an inverse parallel diode is added across the converter main switch (or both switches have bidirectional conduction properties, as with the MOSFET) then power can be efficiently and seamlessly transferred in either direction, between Ei and vo. The voltage polarities are unchanged – it is the current direction that reverses. The buck and boost converters interchange transfer functions when operating in the reverse direction, while the buck/boost converter has the same transfer function in both current directions of operation. 17.8.3 Isolation

In each converter, the output is not electrically isolated from the input and a transformer can be used to provide isolation. Figure 17.14 shows isolated versions of the three basic converters. The transformer turns ratio provides electrical isolation as well as matching to obtain the required output voltage range.

Figure 17.14. Isolated output versions of the three basic converter configurations: (a) the forward converter; (b) step-up flyback converter; and (c) step up/down flyback converter.

•

The magnetic core in the buck-boost converter of part c of figure 17.14 performs a bifilar inductor function. When the transistor is turned on, energy is stored in the core. When the transistor is turned off, the core energy is released via the secondary winding into the capacitor. A core air gap is necessary to prevent magnetic saturation and an optional clamping winding can be employed, which operates at zero load.

The converters in parts a and c of figure 17.14 provide an opportunity to compare the main features and attributes of forward and flyback isolated converters. In the comparison it is assumed that the transformer turns ratio is 1:1:1. 17.8.3i - The isolated output, forward converter – figure 17.14a: • vo = nT δ Ei or I i = nT δ I o • The magnetic element acts as a transformer, that is, because of the relative voltage polarities of the windings, energy is transferred from the input to the output, and not stored in the core, when the switch is on. A small amount of magnetising energy, due to the magnetising current to flux the core, is built up in the core. • The magnetising flux is reset by the current through the catch (feedback) winding and D3, when the switch is off. The magnetising energy is recovered and returned to the supply Ei. • The necessary transformer Vµs balance requirement (core energy-in equals core energy-out) means the maximum duty cycle is limited to 0 ≤ δ ≤ 1/ ( 1 + nf / b ) < 1 for 1:nf/b:nsec turns ratio. For example, the duty cycle is limited to 50%, 0 ≤ δ ≤ ½, with a 1:1:1 turns ratio.

Power Electronics

785

• • •

Chapter 17

Because of the demagnetising winding, the off-state switch supporting voltage is Ei + vo. The blocking voltage requirement of diode D3 is Ei, vo for D1, and 2Ei for D2. The critical load resistance for continuous inductor current is independent of the transformer: 4L Rcrit ≤ (17.155) τ (1 − 2δ )

17.8.3ii - The isolated output, flyback converter – figure 17.14c: • vo = nT Eiδ /(1 − δ ) or I i = nT I oδ /(1 − δ ) • The magnetic element acts as a magnetic energy storage inductor. Because of the relative voltage polarities of the windings (dot convention), when the switch is on, energy is stored in the core and no current flows in the secondary. • The stored energy, which is due to the core magnetising flux is released (reset) as current into the load and capacitor C when the switch is off. (Unlike the forward converter, where magnetising energy is returned to Ei, not the output, vo.) Therefore there is no flyback converter duty cycle restriction, 0 ≤ δ ≤ 1. • The third winding turns ratio is configured such that energy is only returned to the supply Ei under no load conditions. • The switch supporting off-state voltage is Ei + vo. • The diode blocking voltage requirements are Ei + vo for D1 and 2Ei for D2. • The critical load resistance for continuous inductor current is independent of the transformer turns ratio when the magnetising inductance is referenced to the secondary: 4 ηT2 Lm prim 4 Lm sec (17.156) = Rcrit ≤ 2 2 τ (1 − 2δ ) τ (1 − 2δ )

Two examples illustrate the features of magnetically coupled circuit converters. Example 17.8 illustrates how the coupled circuit in the flyback converter acts as an inductor, storing energy from the primary source, and subsequently releasing that energy in the secondary circuit. In example 17.9, the forward converter coupled circuit acts as a transformer where energy is transferred through the core under transformer action, but in so doing, self-inductance (magnetising) energy is built up in the core, which must be periodically released if saturation is to be avoided. Relative orientation of the windings, according to the flux dot convention shown in figure 17.14, is thus important, not only the primary relative to the secondary, but also relative to the feedback winding. Io = Io = 10A 10A I i = 45A

n = s = nT is n p

Z s  ns = Z p  n p

'

I i = 45A

∧

Ei δ = ∧

δ=

( )

0≤δ ≤

30A

30A

300µH

vo' = 75V Rp = 2½Ω

Figure 17.15. Isolated output step up/down flyback converter and its equivalent circuit when the secondary output is referred to the primary.

The 10kHz flyback converter in figure 17.14c operates from a 50V input and produces a 225V dc output from a 1:1:3 (1:nf/b:nsec) step-up transformer loaded with a 22½Ω resistor. The transformer magnetising inductance is 300µH, referred to the primary (or 300uH×32 = 2.7mH referred to the secondary): i. Calculate the switch duty cycle, hence transistor off-time, assuming continuous inductor current. ii. Calculate the mean input and output current. iii. Draw the transformer currents, showing the minimum and maximum values. iv. Calculate the capacitor rms ripple current and p-p voltage ripple if C = 1100µF. v. Determine • the critical load resistance • the minimum inductance for continuous inductor conduction for a 22½ Ω load. Solution

(17.159)

1 1+ nf /b

From Faraday’s Law, the magnetizing current starts from zero and increases linearly to ∧

Io =

Example 17.8: Transformer coupled flyback converter

∧ Ei 1−δ nf /b

1 1+ nf /b

'

Io =

9Cs

Ei = 50V

(17.157)

Time, that is switching frequency, power, and per unit values (δ, ∆vo /vo), are invariant. The circuit is then analysed without a transformer. Subsequently, the appropriate parameters are referred back to their original side of the magnetically coupled circuit. If the coupled circuit is used as a transformer, magnetising current (flux) builds, which must be reset to zero each cycle. Consider the transformer coupled forward converter in figure 17.14a. From Faraday’s ∧ equation, v = Ndφ / dt , and for maximum on-time duty cycle δ the conduction V-µs of the primary must equal the conduction V-µs of the feedback winding which is returning the magnetising energy to the supply Ei. E Ei ton = i toff and ton + toff = τ (17.158) nf /b That is

Rs = 22½Ω 1:3

2

 2  = nT 

vo = 225V

300µH

The basic approach to any transformer (coupled circuit) problem is to transfer, or refer, all components and variables to either the transformer primary or secondary circuit, whilst maintaining power and time invariance. Thus, maintaining power-in equals power-out, and assuming a secondary to primary turns ratio of nT is to one (nT:1), gives ip

Cs

Ei =50V

The operational characteristics of each converter change considerably when the flexibility offered by tailoring the turns ratio is exploited. A multi-winding magnetic element design procedure is outlined in section 9.1.1, where the transformer turns ratio (np :ns) is not necessarily 1:1.

vs ns = = nT v p np

786


I M = Ei ton / LM (17.160) where LM is the magnetizing inductance referred to the primary. During the switch off period, this current falls linearly, as energy is returned to Ei. The current must reach zero before the switch is turned on again, whence the energy taken from Ei and stored as magnetic fluxing energy in the core, has been returned to the supply.

The feedback winding does not conduct during normal continuous inductor current operation. winding can therefore be ignored for analysis during normal operation. Figure 17.15 shows secondary parameters referred to the primary, specifically vo = 225V vo' = vo / nT = 225V/3 = 75V

This

Rs = 225Ω R p = Rs / nT2 = 225Ω / 32 = 22½Ω

Note that the output capacitance is transferred by a factor of nine, nT2 , since capacitive reactance is inversely proportion to capacitance (X = 1/ωC). It will be noticed that the equivalent circuit parameter values to be analysed, when referred to the primary, are the same as in example 17.5. The circuit is analysed as in example 17.5 and the essential results from example 17.5 are summarised in Table 17.3 and transferred to the secondary where appropriate. The waveform answers to part iii are shown in figure 17.16.

Power Electronics

787

Chapter 17

Table 17.3: Transformer coupled flyback converter analysis

Ei

V

value for primary analysis 50

vo

V

75

3 2

parameter

transfer factor nT = 3 → 3

value for secondary analysis 150 225

Ω

2½

3

22½

Co

µF

10,000

3-2

1100

LM

µH

300

3-2

2700

Io(ave)

A

30

⅓

10

Po

W

2250

invariant

2250

Ii(ave)

A

45

⅓

15

δ

p.u.

⅗

invariant

⅗

τ

µs

100

invariant

100

ton

µs

60

invariant

60

tD

µs

40

invariant

40

fs

kHz

10

invariant

10

∆iL

A

10

⅓

10/3

IL

A

75

⅓

25

A

80

⅓

80/3

∧

∨

IL

A

70

⅓

70/3

iCrms

A rms

36.8

⅓

13.3

Rcrit

Ω

37½

32

337½

2

Lcrit

µH

20

3

180

VDr

V

125

3

375

∆vo

mV

180

3

540

∆vo /vo

p.u.

0.24%

invariant

0.24%

1 =¼ 1+ 3 The maximum conduction time is 25% of the 100µs period, namely 25µs. The secondary output voltage is therefore vsec = δ nT Ei =

= ¼×2×192 = 96V The load current is therefore 96V/4Ω = 24A, as shown in figure 17.17a.

Figure 17.17b shows secondary parameters referred to the primary, specifically Rs = 4Ω Rp = Rs / nT2 = 4Ω / 22 = 1Ω vo = 96V vo' = vo / nT = 96V/2 = 48V Lo =800µH L'o = Lo / nT2 = 800µH/22 = 200µH Note that the output capacitance is transferred by a factor of four, nT2 , since capacitive reactance is inversely proportion to capacitance, X = 1/ωC.

∧

I M = Ei ton / LM

70A

= 192V×25µs/1.2mH = 4A

I primary

80/3A 70/3A I secondary

Inspection of example 17.1 will show that the equivalent circuit in figure 17.17b is the same as the circuit in example 17.1, except that a magnetising branch has been added. The various operating conditions and values in example 17.1 are valid for example 17.9. ii. The mean output current is the same for both circuits (example 17.1), 48A, or 24 A when referred to the secondary circuit. The mean input current from Ei remains 12A, but the switch mean current is not 12A. Magnetising current is provided from the supply Ei through the switch, but returned to the supply Ei through diode D2, which bypasses the switch. The net magnetising energy flow is zero. The magnetising current maximum value is given by equation (17.160)

I primary

Io = 10A

Calculate the maximum switch duty cycle, hence transistor off-time, assuming continuous inductor current. At the maximum duty cycle: ii. Calculate the mean input and output current. iii. Draw the transformer currents, showing the minimum and maximum values. iv. Determine • the critical load resistance • the minimum inductance for continuous inductor conduction for a 4 Ω load i.

i. The maximum duty cycle is determined solely by the transformer turns ratio between the primary and the feedback winding which resets the core flux. From equation (17.159) ∧ 1 δ= 1+ nf /b

80A

70A

The 10kHz forward converter in figure 17.14a operates from a 192V dc input and a 1:3:2 (1:nf/b:nsec) stepup transformer loaded with a 4Ω resistor. The transformer magnetising inductance is 1.2mH, referred to the primary. The secondary smps inductance is 800µH.

Solution

Note the invariance of power, Po; normalised parameters δ, and ∆vo/vo; and time ton, tD, τ, and 1/f.

I transformer

I secondary

70/3A Io

This current increases the switch mean current from 12A to I T = 12A + ½ × δ × 4A = 12½A Figure 17.17c show the equivalent circuit when the switch is off. The output circuit functions independently of the input circuit, which is returning stored core energy to the supply Ei via the feedback winding and diode D2. Parameters have been referred to the feedback winding which has three times the turns of the primary, nf/b =3. The 192V input voltage remains the circuit reference. Equation (17.160)Faraday’s law, referred to the feedback winding, must be satisfied during the switch off period, that is ∧

0µs

60 µs

100 µs

t

Figure 17.16. Currents for the transformer windings in example 17.8.

♣

788

Example 17.9: Transformer coupled forward converter

RL

IL


IM nf /b

=

Ei toff n 2f / b LM

4 192V×75µs = 2 3 3 × 1.2mH

Power Electronics

789

Chapter 17

The diode D2 voltage rating is (nf/b+1)×Ei, 768V and its mean current is I 4A = ½A I D 2 = ½ (1 − δ ) M = ½ × (1 - 0.25 ) × 3 nf / b

17.9

800µH

24A

RL = 4Ω Ei=192V

vo = 96V

790


Multiple-switch, balanced, isolated converters

The basic single-switch converters considered have the limitation of using their magnetic components (whether as an inductor or transformer) only in a unipolar flux mode. Since only one quadrant of the B-H characteristic is employed, these converters are generally restricted to lower powers because of the limited flux swing, which is reduced by the core remanence flux. The high-power forward converter circuits shown in figure 17.19 operate the magnetic transformer component in the bipolar or push-pull flux mode and require two or four switches. Because the transformers are fully utilised magnetically, they tend to be almost half the size of the equivalent single transistor isolated converter at power levels above 100 W. Also core saturation due to the magnetising current (flux) not being fully reset to zero each cycle, is not a major issue, since with balanced bidirectional fluxing, the average magnetising current (flux) is zero. In each case, the transformer can be simplified to an auto-transformer, if isolation is not a requirement.

1:3:2 (a)

C IM/3

48A

24A 800µH

200µH RL=1Ω

Ei=192V

LM

4C

Ei=192V

vo=48V

1.2mH

∆vC (1 − 2δ )τ 2 = vo 32 LC

RL=4Ω

10.8mH

vo=96V

9LM

IM

Autotransformer variation

(b)

(c)

Figure 17.17. Isolated output forward converter and its equivalent circuits when the output is referred to the primary.

C

iii. The three winding currents for the transformer are shown in figure 17.18. iv. The critical resistance and inductance, referred to the primary, from example 17.1 are 5⅓Ω and 37½µH. Transforming into secondary quantities, by multiplying by 22, give critical values of RL = 21⅓Ω and L = 150µH. switch voltage

I transformer

∆vC (1 − 2δ )τ 2 = vo 16 LC

256V 192V

0V 61A

C

IM =4A

57A 39A I primary

I primary

∆vC (1 − 2δ )τ 2 = vo 32 LC

57/2A I secondary I sec

39/2A

IM

4A 4/3A

0µs

25 µs

100 µs

t

Figure 17.18. Currents for the three transformer windings in example 17.9.

♣

Figure 17.19. Multiple-switch, isolated output, pulse-width modulated converters: (a) push-pull plus autotransformer option; (b) half-bridge; and (c) full-bridge.

Power Electronics

791

Chapter 17

17.9.1 The push-pull converter

Figure 17.19a illustrates a push-pull forward converter circuit which employs two switches and a centretapped transformer. Each switch must have the same duty cycle in order to prevent unidirectional core saturation. Because of transformer coupling action, the off switch supports twice the input voltage, 2Ei, plus any voltage associated with leakage inductance stored energy. Advantageously, no floating gate drives are required and importantly, no switch shoot through (simultaneous conduction) can occur. The voltage transfer function, for continuous inductor current conduction, is based on the equivalent secondary output circuit show in figure 17.20. Because of transformer action, the input voltage is N×Ei where N is the transformer turns ratio. When a primary switch is on, current flows in the outer loop shown in figure 17.20. That is ∧ ∨ N × Ei − vo ∆iL = i L − i L = × tΤ (17.161) L When the primary switches are off, the secondary voltage falls to zero and current continues to flow through the secondary winding due to the energy stored in L. Efficiency is increased if the diode Df is used to bypass the transformer winding, as shown in figure 17.20. The secondary winding i2R losses are decreased and minimal voltage is coupled from the secondary back into the primary circuit. The current in the inner off loop shown in figure 17.20 is given by v ∆iL = o × (τ − tΤ ) (17.162) L Equating equations (17.161) and (17.162) gives the following voltage and current transfer function t vo I i (17.163) = = 2 N T = 2 Nδ 0≤δ ≤ ½ τ Ei I o The output voltage ripple is similar to that of the forward converter ∆vC ∆vo (1 − 2δ )τ 2 = = vo vo 32 LC

(17.164)

L 1 +

N +

Df

off on

Ei

Vo

N×Ei


The output ripple voltage is given by ∆vC ∆vo (1 − 2δ )τ 2 = = vo vo 16 LC

792

(17.166)

ii. Full-bridge

The full bridge in figure 17.19c replaces the capacitor supplies of the half-bridge converter with switching devices. In the off-state each switch must support the rail voltage Ei and two floating gate drive circuits are required. This bridge converter is usually reserved for high-power applications. Using similar analysis as for the push-pull converter in 17.9.1, the voltage transfer function of the full bridge with a forward converter output stage, with continuous inductor conduction is given by t vo I i (17.167) = = 2 N T = 2 Nδ 0≤δ ≤ ½ τ Ei I o Any volts-second imbalance (magnetising flux build-up) can be minimised by using dc blocking capacitance Cc, as shown in figures 17.19b and c. The output ripple voltage is given by ∆vC ∆vo (1 − 2δ )τ 2 (17.168) = = 32 LC vo vo

Output stage variations

In each forward converter in figure 17.19, a single secondary transformer winding and full-wave rectifier can be used. Better copper utilisation results. If the output diode shown dashed in figure 17.19c is used, the off state loop voltage is decreased from two diode voltage drops to one. The core magnetising current conducts through the secondary winding into the load circuit. The three converters in figure 17.19 all employ the same forward converter output stage, so the critical load resistance for continuous inductor current is the same for each case, viz., 4L (17.169) Rcrit = τ (1 − 2δ ) Re-arrangement of this equation gives an expression for minimum inductance in terms of the load resistance. If the output inductor is not used, conventional unregulated transformer square-wave voltage ratio action occurs for each transformer based smps, where, independent of δ: vo I i n (17.170) = = s =N no Ei I o Zero voltage switching (ZVS) of the H-bridge semiconductors

Figure 17.20. Equivalent circuit for transformer bridge converters based on a forward converter in the secondary.

17.9.2 Bridge converters

Figures 17.19b and c show half and full-bridge isolated forward converters respectively. i. Half-bridge

In the half-bridge the transistors are switched alternately and must have the same conduction period. This ensures the core volts-second balance requirement to prevent saturation due to bias in one flux direction. Using similar analysis as for the push-pull converter in 17.9.1, the voltage transfer function of the half bridge with a forward converter output stage, for continuous inductor conduction, is given by t vo I i (17.165) = = N T = Nδ 0≤δ ≤ ½ τ Ei I o A floating base drive is required. Although the maximum winding voltage is ½Ei, the switches must support Ei in the off-state, when the complementary switch conducts.

The H-bridge load circuit in figure 17.19 parts b and c, is a transformer, and all transformers have leakage inductance. This leakage inductance can be utilised as a turn-on snubber, producing H-bridge zero voltage switching ZVS conditions, which eliminate both switch turn-on losses and diode reverse recovery current injection problems. A consequence of ZVS is purely capacitive snubbers (no snubber diode or reset resistor) also become lossless. The sequence of circuit diagrams in figure 17.21 illustrate how the transformer leakage inductance is used to achieve ZVS. When any switch that is conducting current is turned off, current associated with the leakage inductance diverts to a diode, as shown in the off-loops in figures 17.21 parts b, c, and d. The switch in anti-parallel with that conducting diode in figure 17.21 can be turned on, while the diode conducts, without any switch turn-on losses, ZVS. The magnetising current circulates in a zero volt loop created in the secondary, as shown in figure 17.21. The zero volt loops, figures 17.21 b and c, are alternated on a cycle-by-cycle basis. At a maximum duty cycle, the negative voltage sequence in figure 17.21d is used, where the leakage inductance current falls rapidly to zero. An inherent consequence of ZVS is that lossless capacitive turn-off snubbers can be employed across the bridge switches, as highlighted in chapter 18.1.1ii. The snubber capacitance can be optimally designed if the converter is operated in a constant current mode.

Power Electronics

793

T2 off then T3 on when D3 conducts

T1 D1

D3

Chapter 17

Table 17.4: Mapped transfer functions

T3

L?

duty cycle mapping Tx

D3 T3

T1 D1

D3 T3

L?

0 13½, discontinuous inductor current occurs for δ around ⅓ as given by the two (of the three) real roots of equation (17.171) associated with the local minimum turning point of the cubic equation (17.171).

vo /Ei

step-down

vo

0.6

Operation with constant output voltage, vo In applications were the output voltage vo is fixed, as required with regulated dc power supplies, the effects of varying input voltage Ei can be controlled and compensated by varying the duty cycle. In the inductor continuous current conduction region, the transfer function is determined solely in terms of the on-state duty cycle, δ. Operation in the discontinuous region, for a constant output voltage, can be characterised in terms of duty cycle and the normalised output or input current, as shown in figure 17.29. Key region and boundary equations, for a constant output voltage vo, are summarised in tables 17.7 and 17.8.

•

= 4δ (1 − δ )

0.8

0.4

Generalised characteristics, with operating condition k (=Rτ/L), for the three basic converters, are summarised in Table 17.9. The associated monographs in figures 17.30, 17.31, and 17.32, with a specific load condition, k, for each converter, yield the inductor current waveforms for any on-state duty cycle δ. The three graphs illustrate operational boundaries between continuous inductor current at high δ and discontinuous inductor current at lower δ.

Io

0.2

0.4

0.6

1

Io Io

0.8

0.8

1.0

step-up/down

= 4δ (1 − δ )

vo

-4

δ = 0.6

δ

v × o Ei I

Io

δ =½

0.4

-1½

1,½

discontinuous

0.2

−1

continuous -¼

0 0.2

Ei

- 23

o

0

Ei vo

0.4

0.6

0.8

1.0

Figure 17.24. Characteristics for three dc-dc converters with respect to I o , when the input voltage Ei is held constant. See table 17.5.

Io /Io

Power Electronics

797

Chapter 17

1

Ii

Table 17.5: Transfer functions with constant input voltage, Ei, with respect to I o

Ii

0.8 step-up

step-up/down

(17.4)

(17.48)

(17.78)

continuous inductor current conduction (and change of variable)

reference equation

vo =δ Ei

vo 1 = Ei 1 − δ

v δ= o Ei

vo −1 Ei δ= vo Ei

(17.21)

(17.63)

vo = Ei

discontinuous inductor current conduction

1 1+

δ

vo = Ei ∧

vo = Ei

Eiτ 8L

∧

δ=

change of variable ∧

=

Io change of variable δ= all with a boundary

δ = ½ + ½ 1 − I∧ o Io

conduction boundary

vo Ei δ =½ ∧ × v I o 1− o Ei Io

Io ∧

Io

δ = ½ + ½ 1−

× (1 − δ ) δ

vo −1 Ei

= 4×

vo  vo  1 −  Ei  Ei 

Io ∧

Io

= 4δ (1 − δ )

Io ∧

Io

= 4δ 2 ×

1 vo −1 Ei

Io ∧

v  δ = ½ I∧ o ×  o − 1 Ei   Io

0

1−

0.2

δ =

0.8

= 4δ (1 − δ )

∧

Io

= −4 ×

vo Ei

5

continuous 2 5

0.4

Ii

×

0.8

5

Ii /Ii

vo Ei

Ii Ii

=δ

1.0 step-up

vo 5

vo

δ =

1¼

0

0.2

0.4

1

δ =

2

0.8

Ii Ii

Ii /Ii

1.0

vo

= δ2 -4 δ =

Ii

Ei vo Ei

Ii discontinuous

δ

0.6

step-up/down

0.8

vo Ei

Ei

123

0

1 vo Ei

vo

2½

continuous

−1

Ei

Ei

0.2

vo = −1 Ei

 vo  1 −   Ei  = 4δ (1 − δ )

+ 1−

0.6

0.4

v δ = ½ I∧ o × o Ei Io

Io

3

3

Ei

discontinuous

δ

0.6  vo   − 1 Ei Io   = 4× 2 ∧  vo  Io    Ei 

×

1

= −4δ 2 ×

Io

27

1,

Ii vo

0

vo I = − 4δ 2 / ∧ o Ei Io

δ = ½;

4

5

δ = 2

1

vo δ 2 Eiτ =− Ei 2 LI o

vo =2 Ei

vo /Ei

step-down 4

δ =

0.6

δ = ½;

2

0.2

vo Ei

(17.94)

vo I = 1 + 4δ 2 / ∧ o Ei Io

vo =½ Ei

 vo  1 −  Ei  Io 2 = 4δ ×  ∧ vo Io Ei

discontinuous

Ii

1 1 I 1+ 2 × ∧o 4δ Io

δ = ½;

I o = I o = 1pu @

Io

27

0.4

vo −δ = Ei 1 − δ

vo δ 2 Ei τ = 1+ Ei 2 LI o

2 LI o δ 2τ Ei

0.6

normalised

Io =

4

Ii

step-down

reference equation

where

=

converter

Ei constant

798


−1

-1½

continuous

0.4

- 23

0.2 -¼ 0 0

0.2

0.4

0.6

0.8

1.0

Figure 17.25. Characteristics for three dc-dc converters with respect to I i , when the input voltage Ei is held constant. See table 17.6.

Ii /Ii

Power Electronics

799

Chapter 17

Table 17.6: Transfer functions with constant input voltage, Ei, with respect to I i

Io

1

Io converter

Ei constant

step-down

reference equation


reference equation discontinuous inductor current conduction

vo −1 Ei δ= vo Ei (17.64)

4 Eiτ × 27 2 L

δ=

4

δ=

27 ×

Ii

∧

Ii

×

 v  v  = 27 4 × 1 − o   o   Ei   Ei  Ii Ii

conduction boundary

Ii

∧

Ii

27

4δ

2

∧

(1 − δ )

= 27 4 δ 2 (1 − δ )

=δ2×

Ii

1 vo 1− Ei

∧

=

Ii

2

δ=

2

   

vo −1 Ei ∧ × v o Ii Ei

 vo   − 1 Ei   = ∧ vo Ii Ei =δ

δ = ∧I i Ii

1

0.4

0.6

0.8

5

1.0

Io

=

4

27

× δ (1 − δ )

step-up

2

vo

5

δ =

0.6

δ =

0.4

4

27

×

1, 1 3

discontinuous

1 23 continuous

Io /Io

0 =δ

0

0.2

0.4

0.6

0.8

1.0

1 Ii

Io

0.8

∧

Io

Ii

= (1 − δ )

step-up/down

2

vo

-4

δ =

0.6  vo   E  i   = ∧ v I i  o − 1   Ei  =δ2 Ii

δ=

vo Ei

1¼

2

−1

Ei

2½

vo vo Io  1 −  Ei  Ei Io 

0.2

vo → −∞ Ei

δ=

continuous

∧

Ii

Ii

discontinuous

Ei

0.2

Io

Eiτ Ii = 2L

∧

1−

0

∧

 vo   − 1  Ei 

Ei

5

Io /Io

δ

Ii

Io vo

1

where

vo Ei

Ei

5

0

Ii

δ = 1;

2

vo

0.2

Ii

1=δ2 /

Eiτ 2L

Ii

δ =

0.8

vo →∞ Ei

δ = 1;

 v  = 27 4 δ  1 − o  ∧  Ei  Ii Ii

=

I 1− δ 2 /  ∧i   Ii

∧

0.4

vo voτδ 2 = Ei 2 LI i

1

vo

Io

δ

vo −1 Ei

5

δ =

0.6

(17.94)

1 Ei τ δ 2 1− 2 LI i

Ii =

vo 2 = 3 Ei

δ = ⅔;

Ii

conduction boundary

vo = Ei

4

3

vo Ei

δ=

where

Ii =

change of variable

change of variable

v δ= o Ei

∧

∧

∧

(17.78)

vo −δ = Ei 1 − δ

where

I i = I i = 1pu @

Ii

(17.48)

vo 1 = Ei 1 − δ

vo 4 I =1− × ∧i Ei 27δ 2 I i

normalised

vo = Ei

(17.4)

vo 2 LI = 1− 2 i Ei δ τ Ei

vo /Ei

step-down

step-up/down

vo =δ Ei

vo = Ei

=1−δ

0.8

step-up

(17.20)

800


2

-1½

δ 0.4

δ =

0.2

vo

Io

Ei

Io

Ii

discontinuous

0 0.2

−1

continuous -¼

0

Ei

- 23

Ii

∧

Ei vo

0.4

0.6

0.8

1.0

Figure 17.26. Characteristics for three dc-dc converters with respect to I o , when the output voltage vo is held constant. See table 17.7.

Io /Io

Power Electronics

801

Chapter 17

802


1

Ii Ii

Table 17.7: Transfer functions with constant output voltage, vo, with respect to I o

= 4δ (1 − δ )

vo /Ei

step-down 4

0.8

step-down

step-up

step-up/down

(17.4)

(17.48)

(17.78)

vo =δ Ei

vo 1 = Ei 1 − δ

vo −δ = Ei 1 − δ

vo Ei


reference equation


δ=

reference equation

(17.20)


vo 2 LI = 1− 2 i Ei δ τ Ei

normalised

vo = Ei

vo 1 I v  = 1 − 2 × ∧o ×  o  4δ Ei E Io  i  where

voτ Io = 2L ∧

∧

I o = I o = 1pu @ change of variable

Io ∧

=

Io change of variable δ=

v δ= o Ei

Io ∧

conduction boundary

conduction boundary

(17.64)

vo = Ei 2

vo = Ei

Io

1 × ∧ v Io 1− o Ei

Io

1 − 27

 I  v 2  o o   4δ /  ∧ ×   E   Io  i   2

∧

=

27

4δ

2

×

Io

 vo  vo  − 1  Ei  Ei

Io

δ=

4

27

 vo v − 1 o  Ei  Ei

× I∧ o ×  Io

 vo   − 1 I o 27  Ei  = 4× 3 ∧  vo  Io    Ei 

= 1− δ

= 27 4 δ (1 − δ )

Io

0

Io ∧

Io

0.2

0.4

Ii Ii

0.8 0.6

∧

2

= 27 4 δ (1 − δ )

2

δ=

Io ∧

Io

=

vo Ei

0.8

= 4δ (1 − δ )

5

Ii /Ii

1.0

5

v  ×  o − 1 δ =½ E  Ii  i

δ

vo

step-up

δ =

 vo     Ei 

Ei

2½ 1,½

discontinuous

continuous

0

0.2

0.4

0.6

0.8

1.0

1

2

Ii Ii

= 4δ (1 − δ )

vo

step-up/down

-4

δ =

Io ∧

0.6

δ

 vo  1 −   Ei 

2

δ =½

0.4

Ii Ii

×

vo Ei

Io

- 23 discontinuous

continuous -¼

0 0

0.2

−1

-1½

1,½

2

Io

Ei vo Ei

0.2 = (1 − δ )

Ii /Ii

0

Io

∧

vo

1¼

1

−1

Ei

123

0.2

1

δ = 1−

0.6

Ii

0.4

=δ2×

5

continuous 1

0.8

v = 1− o Ei

δ = 1 − I∧ o

discontinuous

1

v δ = 0; o = 0 Ei Io

2

0

voτ Io = 2L

1

1,½

Ei

5

Ei

∧

v δ = ⅓; o = 1½ Ei Io

vo −1 Ei

I vo v  = δ 2 /  ∧o × o   Ei Ei   Io 

4 voτ × 27 2 L

∧

1−

0.2

where

Io =

3

Ei vo

×

Ii

0.4

vo voτδ 2 = Ei 2 LI i

1

Ii

δ =½

δ

(17.94)

1 Ei τ δ 2 1− 2 LI i

where

v δ = 0; o = 0 Ei  vo  1 −  Ei  Io 2 =δ × 2 ∧  vo  Io    Ei 

δ=

vo

0.6

vo Ei

vo

δ =

converter

vo constant

5

0.4

0.6

0.8

1.0

Figure 17.27. Characteristics for three dc-dc converters with respect to I i , when the output voltage vo is held constant. See table 17.8.

Ii /Ii

Power Electronics

803

Chapter 17

1

Table 17.8: Transfer functions with constant input voltage, vo, with respect to I i

vo

converter

vo constant

step-up

step-up/down

(17.4)

(17.48)

(17.78)

reference equation


reference equation

vo =δ Ei

vo 1 = Ei 1 − δ

v δ= o Ei


(17.21)

vo = Ei


δ=

vo = Ei

where ∧

Ii =

voτ 8L

∧

change of variable ∧

vo I = 1 + 4δ 2 / ∧ i Ei Ii

o

4δ

E

Ei

E

1

27

2

−1

vo

i

Ii

2

change of variable δ= all with a boundary

δ = ½ + ½ 1 − I∧ o

vo E δ = ½ I∧ i × iv Ii

1−

Io

conduction boundary

Ii ∧

Ii

=4

o

Ei

vo  vo  1 −  Ei  Ei 

δ = ½ + ½ 1 − I∧ o Io

δ = ½;

 vo  1 −  Ei  = 4δ ×  ∧ vo Ii Ei Ii

=

vo =½ Ei

δ = ½;

= 4δ (1 − δ )

Ii ∧

= 4δ 2 ×

Ii

δ = ½;

1 vo −1 Ei

Ii ∧

v  δ = ½ I∧ i ×  o − 1 Ii

 Ei

 vo   − 1 E Ii i  = 4×  2 ∧  vo  Ii    Ei  = 4δ (1 − δ )

= −4δ 2 ×

δ=¼

27 δ2 4

=δ

Ei

Ii

Ii ∧

Ii

= −4 ×

Ei

−1

vo

discontinuous

δ=¼

1

δ=0 δ=1

( ) 1−

v

o

½

E i

discontinuous

o

E

= i

 v  4δ 21− o  Ei   vo Ei

=δ

Ei

1 1− δ

δ=½

δ=¼   1−vo   Ei  

δ=0 ∧

1

Io / Io

δ=¼

-½

−δ

v

o

1−δ

E

=

i

-1 δ=½

Ei

vo

0

δ=¼

v

=

Ei

2

1

I i / Ii

1 vo Ei

− 4δ vo Ei

−δ 1−δ

2

δ=½

continuous

vo Ei

 vo  1 −   Ei  = 4δ (1 − δ )

2

δ=½

Ei

v 4 oE i

∧

v δ = ½ I∧ i × o



vo

1− δ

 vo  vo  4 1 − E  E  i  i  

−1

Ei

δ=¾

vo

vo = −1 Ei

Ii

vo

δ=¾

vo I = − 4δ 2 / ∧ i Ei Ii

vo =2 Ei

( ) ( )

2

δ=0

I i = I i = 1pu @

Ii

=

δ=½

1 1 I 1+ 2 × ∧i 4δ Ii

v

2

v

δ=0 δ=1

normalised

vo = Ei

Ei

δ=¼

vo δ 2 voτ =− Ei 2 LI i

4

i

vo

vo −1 Ei

0

−1

o

vo Ei

vo Ei

2

0

δ=½

(17.94)

vo δ 2 voτ = 1+ Ei 2 LI i

2 LI 1+ 2 i δ τ vo

δ

δ

vo −δ = Ei 1 − δ

(17.63)

1

Ei

vo

step-down

804


 v E  − v  E −1 

2

o

i

o

i

    

discontinuous

2

−4

(

1−

-2

1

vo

Ei

Ei

)

2

∧

Ii / Ii

Ei constant

vo

=δ

2

Ei constant 0

0

Figure 17.28. Characteristics for three dc-dc converters, when the input voltage Ei is held constant.

(

δ=½

1−

vo

∧

v

i

E =

vo constant

vo

( 1− 27 4

v

vo o i

E

Ei = δ

1

o

−1

Ei

)

δ

−1

δ=0

v

)

−δ

( ) o

E o

δ=0 δ=1

Ei ½

 v

2

δ=¼

δ=½

-1

0

vo Ei

i 2  vo   E i 

0

δ=¾

vo



4

0

discontinuous

2

0 vo Ei

Ei

  1− v o  

continuous

1−

(

Ei

−4

vo

Ei

−δ v

vo

Ei Ei

)

v

1

=δ

 v  4 δ 2  1− o E i   vo Ei

δ 21− o E  

   

-½ o

1− δ −4δ 2 vo Ei E

2

δ=¼

i

E

δ=0 δ=1 δ=¾

δ=½

δ=¼

δ=0

2

1

I i / Ii

∧

i

δ=¼

i

= 1−δ

−δ

δ=½

2

-2

vo constant

Figure 17.29. Characteristics for three dc-dc converters, when the output voltage vo is held constant.

2 ×

vo

τ

 

R Ei I L = ½  i L + i L  (δ + δ D )

∨

IL ×

∨ R R , IL × Ei Ei

= 1 − (δ + δ D )

τ

tx

δD =

tD

vo I R ( k , δ ) = i = Io × Ei Ei Io

δ (1 − δ ) Ei

i L (δ ≤ t ≤ δ + δ D ) ≤ I o

2 1−δ

tτ

tτ

tT fo; (b) ½fo < fs < fo; and (c) fs < ½fo.

Figure 18.7. Series-parallel LCC resonant dc-to-dc converter: (a) basic series–parallel resonant circuit; (b) series–parallel load resonant converter circuit; (c) dc characteristics; (d) equivalent ac circuit; and (e) equivalent fundamental input voltage circuit.

Power Electronics

823

Chapter 18 CR

18.3.1 LCC resonant tank circuit A further load resonant converter variation is a combined series-parallel (third order) resonant stage as shown in figure 18.7a and the implemented circuit is figure 18.7b. This resonant approach combines the properties of the series and the parallel resonant approaches. Analysis is based on the same assumptions as for the parallel resonant cases, namely the H-bridge produces a square-wave voltage VH-B at a frequency near the filter resonance frequency fo which results in a near sinusoidal voltage across the parallel resonance capacitor Cp. The voltage across the parallel output capacitor is rectified by the output bridge rectifier, while the bridge output inductor, under steady state conditions, ensures near constant load current Io.

The magnitude of the dc to ac voltage transfer function is 1 vo = 2 2 2 Vs  ω   2 1 ω ω λ  (1 + λ )  1 −    + 2 ×  − o   ωo   Q  ωo ω 1 + λ   where λ = Cs/Cp.

(18.22)

The inductive elements in the tank circuit shown in figure 18.8a form the leakage inductance and magnetising inductance when the load is transformer coupled. The circuit is less sensitive to load changes than series resonant circuits and has lower circulating current under light and no-load conditions, than parallel resonant circuits. Two resonant frequencies occur 1 1 λ and f o 2 = fo 1 = = fo 1 (18.24) 2π LRC R λ +1 2π (Lp + LR ) C R The voltage transfer function is approximately (expression is correct at resonance)

Lp Ls 1 =  Lp Z π2  1  Lp (1 − ω 2 ) Z π 2 λ 2  j ω  + 1 − 2  + (1 − ω ) 1 + λ − ω 2  − j L L R 8 ω Rdc 8 ω s dc  s   

vo /p = Vs

where Q =

jω

Req

(18.25)

L = 2 Rdc , λ = R , and ω = ωs / ωo is the normalised switching frequency. Then π Lp 8

1 2

2

2 λ  1    Z π  1 + λ − ω 2  +  ω − ω   R 8       dc 

2

=

1 2

λ    2  1 1 + λ − ω2  + Q  ω − ω     

2

(18.26)

Zo Zo π 2Z o π 2Z o Pout = = = . A transformer is account for by the turns ratio n:1 term n. 8n 2Vdc2 Req n 2Req 8n 2Rdc

R

increasing λ

fo2

2½ 2

(a)

Cs Ls

Q

positive slope

(b)

Lp

0.2

ZCS ZCS

negative slope

1½

Load independent point Q

ZVS ZVS

capacitive

0.6

1

1

inductive

0 0

½

+

Vs

1

LR

1½

(c)

0.2 0.6 1 2 3 5

fo1

½

Cs

18.3.2 LLC resonant tank circuit

Vo/p

VH-B Lp

5

At light and no-load, the operating point tends to the resonant peak at the upper resonant frequency C +Cs 1  1 1  1 1 (18.23) + = p ωo22 =  = LR  C p C s  LR C equiv LRC pC s 2 The lower resonant frequency is ωo 1 = 1 / LRC s All the circuit variations applicable to the parallel resonant circuit are also applicable to the series – parallel resonant converter. Additional advantage can be gained by the fact that a series resonant capacitor can be used to form the ac split dc rail arrangement shown in figure 18.4c.

Ls , where Z = Cs

Cs LR

VD-B

VD-B

π2

R (18.20) 8 In this case, the voltage transfer ratio, in terms of the fundamental input component, is given by vo 8 1 (18.21) = × 2 2 Vs π 2  Cp  1   8   2 ω ω 1 + − + × − L C L  R p   2   R ωC  s   Cs  π R  

Lo

Vs

Gain

Req =

824

Ls

Lp

VH-B

Figure 18.7d shows the converter equivalent circuit, while figure 18.7e shows the ac equivalent circuit where it is assumed that the bridge square wave frequency, which is its fundamental frequency, is near the resonant frequency. The ac equivalent resistance is the same as for the parallel resonant case, namely

vo /p = Vs

Resonant Mode DC to DC Converters

2

(d)

ωs ωo

(e)

Cs

LR jXL Lp

Lp Io

jXLp

Req

4 V π

o

Figure 18.8. Series-parallel LLC resonant dc-to-dc converter: (a) basic series–parallel resonant circuit; (b) series–parallel load resonant converter circuit; (c) dc characteristics; (d) equivalent ac circuit; and (e) equivalent fundamental input voltage circuit.

The dc characteristic on the right of fo1 for the LLC converter are same characteristic as a SRC. On the left of fo1, the PRC and SRC characteristics emerge but oppose. At heavy loading, SRC characteristics dominant. At lighter loads, PRC characteristic dominate and the no load output magnitude, as Q tends to zero, is vo /p 1 = (18.27) λ Vs 1+λ − 2

ω

By operating the LLC converter at a resonant frequency lower than that of a SRC, it retains a ZVS characteristic because PRC characteristics dominant in that frequency range. Load resonant circuit comparison The series-parallel approach combines the better switching properties of the series converter and the parallel converter, which are summarised in table 18.1. In common, a positive slope on the voltage transfer function versus frequency characteristics are associated with zero current switching ZCS, while a negative slope is indicative of zero voltage switching ZVS characteristics. Basically, the tank circuit is capacitive below resonance and becomes inductive above the resonance frequency.

Power Electronics

825

Chapter 18

Unlike the series converter, both the parallel and series-parallel converters can operate at zero load current, without output voltage over-charging. But advantageously, because of the LCC series input capacitor Cs, the efficiency at low power output levels is like that of the series converter, which is much higher than that of the series–parallel converter. The resonant currents with either parallel approach tend to be independent of the load. Series resonant converter SRC The resonant tank is in series with the load. The resonant tank and the load act as a voltage divider. By changing the frequency of input excitation voltage, the impedance of resonant tank will change, which allows to load voltage to be varied. As a voltage divider, the DC gain of SRC is always less than 1. At the resonant frequency, the maximum voltage gain frequency, the impedance of series resonant tank is small; all the input voltage (fundamental) is developed across the load. Operating region is on the right side of resonant frequency fo is preferred because zero voltage switching (ZVS) is preferred for the LC series converter. When the switching frequency is below the resonant frequency, the converter operates with zero current switching (ZCS). When the DC gain slope is negative, the converter operates under a zero voltage switching condition. When the DC gain slope is positive, the converter switches under a zero current switching condition. The voltage gain characteristics indicate that at light load, the switching frequency needs to increase, to reduce the gain, in order to maintain output voltage regulation. The major problems are: light load regulation, high circulating energy and turn off current at high input voltage condition. Parallel resonant converter PRC For the parallel resonant converter, the resonant LC tank is again in series. It is called parallel resonant converter because the load is in parallel with the resonant capacitor (or inductor). Technically this converter should be termed a series resonant converter with a connected parallel load. Compare with a SRC, the operating region is much smaller. At light load, the frequency is minimally changed to maintain output voltage regulation. So light load regulation is not a problem with the PRC. For the PRC, circulating energy is high even at light load. Since the load is in parallel with the resonant capacitor, even at no load condition, the input sees the impedance of the series resonant tank. This induces a high circulating energy even when the load is zero. The major problems are: high circulating energy, high turn-off current at high input voltage condition. Series-parallel resonant converter SPRC The resonant tank of SPRC can be considered a combination of SRC and PRC converters, producing the best characteristics of each. With load in series with series tank L and C, the circulating energy is smaller than with the PRC. With the parallel capacitor, the SPRC can regulate the output voltage at a no load condition, by operating at a frequency above resonance. The operating region of the SPRC has a narrower switching frequency range with load change than the SRC. The input current in much smaller than that of the PRC and slightly larger than for the SRC. This means for the SPRC, the circulating energy is less than with the PRC. A SPRC combines the better characteristics of a SRC and a PRC. Smaller circulating energy and is not too sensitive to load change.

LR

fs fo

switch diode on off

switch diode off on

power factor

zcs

zcs zvs

zcs

zcs zvs

N/A

zcs zvs

zcs zvs

hard*

hard+ zcs zvs

zcs zvs hard*

iR

Req =

1

×

8

N 2 π2

LR

Rload

CR

VCR

Req =

1

N2

×

π2 8

Rload

1:N

(a)

(b)

Figure 18.9. Voltage-source transformer resonant converter circuits: (a) series transformer LC resonant circuit and (b) parallel transformer LC resonant circuit.

In series, as shown in figure 18.9a, the primary current is a controlled sinusoid, hence by Ampere-turns transformer action, the secondary is a current source sinusoidal waveform. The secondary current is faithfully delivered into any voltage. This mode of transformer action is therefore termed ‘current’ transformer operation since the transformer primary is driven to obey Iprim = N×Isec. However, the secondary circuit must have low series inductance, since the secondary is driven by a current source.

CR

LR

LR

VL 1:N

CR

VC 1:N

gain

8

positive slope

Positive slope

positive slope

ZCS

ZVS

ZCS

6

No turn-on loss

Positive slope

ZVS

4

No turn-on loss inductive

inductive

2

0 0.8

1

1.2

0.8

fo/fs

1

1.2

fo/fs

(a)

switch diode off on

hard+

CR

1:N

parallel load resonance

switch diode on off

826

In the case of a parallel transformer resonant circuit, a voltage transformer is used across the resonant capacitor (or inductor) as shown in figure 18.9b, while for a series transformer resonant circuit, a current transformer is used in series with the resonant circuit inductor and capacitor, as shown in figure 18.9a.

Table 18.1: Switch and diode turn-on/turn-off conditions for resonant switch converters series load resonance


(b)

Gain

CR

L

LR

3

LR

C

CR

positive slope

positive slope

2

ZCS

ZCS

negative slope

leading

ZVS lagging

negative slope

1

ZVS

+

Lossless, * capacitive turn-off or inductive turn-on snubbers can be used, as appropriate 0

18.4

Resonant coupled-load configurations

The concept of voltage and current transformer coupling is introduced. A series LC resonant circuit produces a resonant sinusoidal current and anti-phased sinusoidal voltages across both the circuit L and C components. A current transformer can therefore be used in series with the resonant circuit, while, alternatively a voltage transformer can be used in parallel with either the circuit L or C.

(c)

(d)

Figure 18.10. Voltage transformer coupled, resonant converter circuits, LC, LLC, LCC: (a) and (c) parallel resonant inductor LR transformer coupling circuits and (b) and (d) parallel resonant capacitor CR transformer coupling circuit.

Power Electronics

827

Chapter 18


828

A voltage coupling transformer requires a voltage source, so the voltage across the capacitor CR (or alternatively inductor LR) of a series resonant circuit can be utilised as shown in figure 18.9b and figure 18.10. The primary voltage is controlled by the capacitor CR voltage, as is the secondary voltage when complying with Vsec = N×Vprim. Although the voltage is faithfully reproduced on the secondary, the secondary current, hence primary current, are determined by the secondary load circuit. A transformer used in this mode is termed a ‘voltage’ transformer. However, in order to prevent uncontrolled secondary currents, the secondary inductor, Lo, in figures 18.5, 18.7 and 18.8, is introduced to give controlled output current source properties.

Again the secondary current has been referred to the primary. Solving the two average primary current equations gives vo / p I = 0.81× ( 340 − ½ vo ) = 5 vo / p = 456V and I = 91.2A

The advantage of the parallel transformer resonant circuit over the series approach is that the turns ratio of the transformer can be reduced (increased primary turns for a given output specification) because of the higher gain (greater than unity) of parallel-coupled resonant circuits (see figures 18.2b and 18.5b). For example, if the circuit Q is four, the transformer turns ratio can be decreased by a similar factor over that needed for a series transformer resonance circuit. Both the parallel transformer coupled circuits in figure 18.10 can take advantage of inherent voltage gain in order to reduce the necessary transformer turns ratio. Figure 18.10 shows that the voltage transformer can by parallel coupled to the inductor, as in figure 18.10a, or the capacitor, as in figure 18.10b. At resonance, the two circuits behave identically. The off-resonance characteristics are different (opposite), particular at frequencies above resonance, where ZVS and inductive operation occur in both cases. Above resonance, the inductor supports an increasing amount of the H-bridge output ac voltage as the capacitor reactance, hence voltage and output gain diminish to zero in figure 18.10b, but the output is unity in figure 18.10a. The ability to reduce the gain to near zero, with ZVS, is important at converter start-up, and enables the start-up current inrush into any output capacitor to be better controlled. The inductance of the output inductor Lo can thereby be minimised.

iii. From part ii, the capacitor dc voltage requirement is at least 456V dc. The secondary rms current is 1 ∧ 1 π I Srms = nT × I Prms = nT × × I = ½× × ×I 2 2 2

Example 18.1: Transformer-coupled, series-resonant, dc-to-dc converter The series resonant dc step-down voltage converter in figure 18.1a is operated at just above the resonant frequency of the load circuit and is used with a step up transformer, 1:2 (nT = ½), as shown in figure 18.4a. It produces an output voltage for the armature of a high voltage dc motor that has a voltage requirement that is greater than the 50Hz ac mains rectified, 340V dc, with an L-C dc link filter. The resonant circuit parameters are LR =100µH, CR =0.47µF, and the coil resistance is Rc = 1Ω. For a 10Ω armature resistance, Rload, calculate i. the circuit Q and ωo ii. the output voltage, hence dc armature current and power delivered iii. the secondary circuit dc filter capacitor voltage and rms current rating iv. the resonant circuit rms ac current and capacitor rms ac voltage v. the converter average input current and efficiency vi. the ac current in the input L-C dc rectifier filter decoupling capacitor vii. the H-bridge square-wave switching frequency ωs, greater than ωo. Solution i. The resonant circuit Q is Q=

LR 100µH / Rc = /1Ω = 14.6 0.47µF CR

For this high Q, the circuit resonant frequency and damped frequency will be almost the same, that is ω ≈ ωo = 1/ LR CR = 1/ 100µH × 0.47µF = 146 krad/s

That is, the load voltage is 456V dc and the load current is 456V/10Ω = 91.2A/2 = 45.6A dc. The power delivered to the load is 4562/10Ω = 20.8kW.

P

.

= 0.555 × I = 0.555 × 91.2A P

= 50.65A rms The primary rms current is double the secondary rms current, 101.3A rms. By Kirchhoff’s current law, the secondary current (50.65A rms) splits between the load (45.6A dc) and the decoupling capacitor. That is the rms current in the capacitor is 2

2 I Crms = I Srms − I S = 50.65A 2 − 45.6A 2 = 22A rms

That is, the secondary dc filter capacitor has a dc voltage requirement of 456V dc and a current requirement of 22A rms at 46.5kHz, which is double the resonant frequency because of the rectification process. iv. The primary rms current is double the secondary rms current, namely from part iii, IP rms = 101.3A rms (essentially 101.3A at 23.25kHz). The 0.47µF resonant capacitor voltage is given by I vcap = I Prms X c = Prms ωo C R 101.3A = 1476V rms (predominately at 23.25kHz)) 146krad/s × 0.47µF The resonant circuit capacitor has an rms current rating requirement of 101.3A rms and an rms voltage rating of 1476 V rms. =

v. From part ii, the average input current is 91.2 A. The supply input power is therefore 340Vdc×91.2A ave = 31kW. The power dissipated in the resonant circuit resistance Rc =1Ω is given by 2 I Prms × Rc = 101.32 × 1Ω = 10.26kW. The coil power plus the load power (from part ii) equals the input power (20.8kW+10.26kW = 31kW). The efficiency is output power η= × 100% input power 20.8kW = × 100 = 67.1% 31kW

I s = 2 × 45.6A

I p rms = 2 × 50.65A

= 91.2A dc

ii. From equation (18.7), which will be accurate because of a high circuit Q of 14.6, 2 ∧ 8 (Vs − nT × vo / p ) 8 ( 340 V − ½ vo / p ) I= I= 2 = 2× π π π Rc 1Ω = 0.81× ( 340 V − ½ vo / p )

Note that the output voltage vo/p across the dc decoupling capacitor has been referred to the primary by nT, hence halved, due to the turns ratio of 1:2. The rectified resonant current provides the load current, that is v v 1 v I = × o/ p = 2 × o/ p = o/ p nT Rload 10Ω 5

= 101.3A rms 2

2

2

I p rms = I s + I ac

LR=100µH

= 2π f f = 146 krad/s /2π = 23.25 kHz

P

.

CR=0.47µF

I ac = 2 × 22A = 44.1A ac

vi. The average input dc current is 91.2A dc while the resonant bridge rms current is 101.3A rms. By Kirchhoff’s current law, the 340V dc rail decoupling capacitor ac current is given by 2 2 I ac = I Prms − I Pave

= 101.32 − 91.2 2 = 44.1A ac This is the same ac current magnitude as the current in the dc capacitor across the load in the secondary circuit, 22A, when the transformer turns ratio, 2, is taken into account.

Power Electronics

829

Chapter 18

vii. The voltage across the load resistance is given by equation (18.13) 8 × n2 × R Load Req vo π2 T = = Vs   1  1  2 8 Req + Rc + j  ω LR − 2 × nT × RLoad + Rc + j  ω LR − ωs CR  π ωs CR    s

s

8 × ¼ × 10Ω 228V π2 = 340V  1 8 × ¼ × 10Ω + 1Ω + j  ω 100µH −  s π2 ωs 0.47µF   which yields ωs ≈ ωo =146krad/s. Because of the high circuit Q = 14.6, but an infinite Q being assumed to evaluate vo, and relatively high voltage transfer ratio vo / Vs = 0.66 , ωs is very close to ωo, as can be deduced from the plots in figure 18.2b. The output voltage control will be very sensitive to changes in the H-bridge switching frequency. ♣


Both full-wave or half wave resonance switching is possible, depending on whether half a resonant cycle or a full resonant cycle is allowed by the circuit configuration. Figure 18.11 shows the basic resonant switch building blocks. A common feature, with a dc voltage source, is that the resonant inductor LR is in series with the switch to be losslessly commutated. Essentially a diode across the switch determines whether full or half wave commutation can occur. In the case of ZCS, the anti-parallel diode allows the resonant current to continue for a full ac resonant cycle, while the same diode prevents a full resonant capacitor voltage cycle since the diode clamps any switch negative voltage to zero. CR parallel output

T1

CR parallel switch

CR

LR Lo CR

Vs 18.5

D1 Co

In resonant current commutation the switch current is reduced to zero by an L-C resonant circuit current greater in magnitude than the load current, such that the switch is turned on and off with zero current. In resonant voltage commutation the switch voltage is reduced to zero by the capacitor of an L-C resonant circuit with a voltage magnitude greater than the output voltage, such that the switch can turn on and off with zero voltage. ZVS full-wave

T

T

CR

ZVS

CR LR

Ii

full - wave

CR

T1 T1

T

LR

Ii

T

CR

T1

CR CR

ZCS full-wave

(d)

LR T

CR

DR

CR

Vs CR

CR LR

T1

ZVS

Ii

LR

full - wave

T

ZCS

T

-

(a)

LR

T1

½- wave

(e)

CR

LR

LR

DR Lo

Ii

+ vo

D1Co

LR

add switch antiparallel diode subtract

ZCS half-wave

Vs

CR Ii

LR

DR

LR

Ii

-

CR

ZCS

T1

+ vo

½- wave (c)

Lo LR

D1 Co

LR

DR

ZVS half-wave

Ii

T1

Vs

(b)

LR Lo

+ vo

Resonant-switch, dc-to-dc step-down voltage converters

There are two forms of resonant switch circuit configurations for dc-to-dc converters, namely resonant voltage and resonant current switch commutation. Each type reduces the switching losses to near zero. The technique can be used on any hard switch circuit, for example, resonant switching is applicable to the switch in the buck, boost, buck/boost, Cuk, etc. converters.

830

CR

D1 Co

+ vo

-

Lo Vs

T1

D1 Co

+ vo

-

LR

Ii

T

Figure 18.11. Resonant switches, showing half-wave and full-wave circuits for both ZCS and ZVS.

Figure 18.12. Dc to dc resonant switch step-down converters: (a) conventional switch mode forward step-down converter; (b) and (c) half-wave zero current switching ZCS resonant switch converters; and (d) and (e) half-wave zero voltage switching ZVS resonant switch converters. Topological translations between half-wave and full-wave versions also shown.

Power Electronics

831

Chapter 18

Although resonant switching is applicable to boost and buck/boost converters, only its application to the buck converter will be specifically analysed. In mitigation, the basic resonant switch possibilities for the buck, boost, and buck/boost converters are shown in matrix form, in the figures 18.20, 18.21, and 18.22 of the Appendix 18.7 at the end of this chapter. Figure 18.12a shows the basic single switch, forward, step-down voltage switch mode dc-to-dc converter. Resonant switch forward converters are an extension of the standard switch mode forward converter, but the switch is supplement with passive components LR - CR to provide resonant operation through the switch, hence facilitating zero current or voltage switching. Common to each circuit is a resonant inductor LR in series with the switch to be commutated. Parasitic series inductance is therefore not an issue with most resonant switch converters. An important operational requirement is that the average load current never falls to zero, otherwise the resonant capacitor CR can never fully discharge in order to fulfil its zero switch voltage/current electrical condition function. The resonant capacitor CR, can be either in a parallel or series arrangement as shown in figure 18.12, since small-signal ac-wise, thence resonance wise, the connections are the same. A well-decoupled supply is essential when the capacitor CR is used in the parallel switch arrangement, as shown in figure 18.12d. A further restriction shown in figure 18.12, is that a diode must be used in series or in antiparallel with T1 if a switch without reverse blocking capability is used. The use of a diode DR in anti-parallel to the switch (shown shaded below figures 18.12 b and c) changes the switching arrangement from half-wave resonant to full-wave resonant operation, where switch reverse voltage block capability is not necessary. Conversely, removal of the diode DR in figures 18.12 d and e (shown shaded above figures 18.12 d and e) changes the switching arrangement from half-wave resonant to full-wave resonant operation, where switch reverse voltage block capability is necessary. Reconnecting the capacitor CR terminal not associated with Vs, to the other end of inductor LR in the half-wave circuit in figures 18.12b-e, will create four full-wave resonant switch circuits, with the commutation type, namely ZVS or ZCS, interchanged. Full and half wave operation is dependent on whether the circuit configuration allows the resonant capacitor to complete a full or half resonant sinusoidal cycle.

Time interval IIA When the current in LR reaches Io at time t1, the capacitor CR and LR are free to resonant. The diode D1 blocks as the voltage across CR sinusoidally increases. The constant load current component in LR does not influence its ac performance since a constant inductor current does not produce any inductor voltage. Its voltage is specified by the resonant cycle, provided Io < Vs / Zo. The capacitor resonantly charges to twice the supply Vs when the inductor current falls back to the load current level Io, at time t3. Time interval IIB Between times t3 and t4 the load current is displaced from LR by charge from CR, in a quasi resonance process. The resonant cycle cannot reverse through the switch once the inductor current reaches zero at time t4, because of the series blocking diode (the switch must have uni-directional conduction characteristics). T1

type

period

half-wave

π

½ resonant cycle

full-wave

2π

1 resonant cycle

ZVS

ZCS no turn-on loss constant on-time

switch

Vcap

switch

current resonates

anti-parallel diode

voltage resonates

reverse blocking

current resonates

reverse blocking

voltage resonates

anti-parallel diode

> twice the dc supply

controlled dv/dt’s

CR

Vs

+ vo

Co

-

(a)

ZCS

T1 on

0

T1 on

T1 off

IT1

> twice the output current

Io

-Vs /LR t0

t1

t2

t3

according to (18.29)

t4

2Vs

t5

t

t0

VCR

I

IIA

IIB

III

IV

Vs

INTERVALS

Vs

-Io /CR

The zero current switching of T1 in figure 18.13 (18.12b) can be analysed in five distinctive stages, as shown in the capacitor voltage and inductor current waveforms in figure 18.13b. The switch is turned on at to and turned off after t4 but before t5. Assume the circuit has attained steady state load conditions from one cycle to the next. The cycle commences, before to, with both the capacitor voltage and inductor current being zero, and the load current is freewheeling through D1. The output inductor Lo, is large enough such that its current, Io can be assumed constant. The switch T1 is off. Time interval I At to the switch is turned on and the series inductor LR acts as a turn-on snubber for the switch. In the interval to to t1, the supply voltage is impressed across LR since the switch T1 is on and the diode D1 conducts the output current, thereby clamping the associated inductor terminal to zero volts. Because of the fixed voltage Vs, the current in LR increases from zero, linearly to Io in time tI = I o LR / VS (18.28)

ID1

ICR

18.5.1 Zero-current, resonant-switch, dc-to-dc converter - ½ wave, CR parallel with load version

V iLR ( t ) = s t LR

D1

τ

Icap

controlled di/dt’s

LR Lo

Io + Vs/Zo

no turn-off loss constant off-time

832

During this interval the resonant capacitor voltage is clamped to zero since CR is in parallel with D1 which is conducting a current decreasing from Io to zero: (18.30) vc ( t ) = 0

Table 18.2: ZCS and ZVS circuit characteristics Characteristics and properties


t1

t

t2

t5

t1

(b)

VLR (c)

IT1

IT1 Io

Vs

Io

Io Vs

Vs

Io

Io

Io

Vs

Figure 18.13. Zero current switching, ZCS, half-wave resonant switch dc to dc converter with the resonant capacitor across the output: (a) circuit; (b) waveforms; and (c) equivalents circuits.

Power Electronics

833

Chapter 18

The capacitor voltage and current for period IIA and approximately for period IIB, are given by equations 14.60 and 14.61 with the appropriate initial conditions of io = 0 and vo = 0:  ω  vc (ωt ) = Vs  1 − o e −α t cos (ωt − φ )  ω (18.31)   ≈ Vs (1 − e −α t cos ωt )

ic (ωt ) =

Vs

ωL

× e−α t × sin ωt

(18.32)

If the circuit Q is high these equations can be approximated by


vo =

R

iC ( t ) = R

v C = 2Vs R

Vs sin ωo t Zo

(18.33) (18.34)

The inductor current is the constant load current plus the capacitor current: V V iL ( t ) = I o + iC ( t ) = I o + s sin ωo t where iT 1 = i L = I o + s (18.35) Zo Zo s where Z o = LR / CR and ωo = 1/ LR CR . Equation (18.35) shows that the inductor current only returns to zero if Io < Vs / Zo, otherwise the switch is commutated with a non-zero current flow. R

R

R

.

Setting iL = 0 in equation (18.35) gives the time for period II as  I Z  tII =  π + sin −1  o o   / ωo Vs     after which time the capacitor voltage and inductor current reach 2  I Z   VC t 4 = Vs  1 + 1 −  o o     Vs    IL t4 = 0 R

(18.36)

(18.37)

R

Time interval III At time t4 the input current is zero and the switch T1 can be turned off with zero current, ZCS. The constant load current requirement Io is provided by the capacitor, which discharges linearly to zero volts at time t5 according to 2  I Z   I I vC ( t ) = VC t 4 − o × t = Vs  1 + 1 −  o o   − o × t (18.38)  CR V  s   CR  R

where VC

R

t4

R

is given by equation (18.37).

The inductor current is

iLR ( t ) = 0

(18.39)

The time for interval III is load current dependant and is given by setting equation (18.38) to zero: 2  VC t 4 CR I Z   C = R × Vs  1 + 1 −  o o   tIII = (18.40)  Io Io  Vs   

τ

(½t

I

+ t II + t III )

2 (18.41)     I Z  I Z   C Vs  1  I L π + sin −1  o o   + ½ o R + Vs 1 + 1 −  o o   × R  ×    τ  ωo  VS  Vs    Vs   I o     where the time intervals I, II, and III are given by equations (18.28), (18.36), and (18.40) respectively, the switching frequency f s = 1/ τ , and τ > t I + tII + tIII .

=

The output voltage based on the average capacitor voltage (after resetting time zero references) is t −t  1  t −t t   vo =  ∫ Vs (1 − cos ωt ) dt + ∫ VC t 4  1 −  dt  0 τ  0  t5 − t4   (18.42) 2 2   I Z  I Z  I Z   I Z   C 1 V  = ×  s  π + sin −1  o o  + o o  + ½ × Vs2 × 1 −  o o  ×  1 + 1 −  o o   × R   τ  ωo   Vs  Vs   Vs    Vs   I o    The output voltage in equation (18.42) reduces to equation (18.41). 4

vC ( t ) = Vs (1 − cos ωo t ) where

Vs

834

1

5

4

R

The minimum switch commutation period is tI + tII + tIII which limits the upper operating frequency, hence maximum output voltage. The output voltage,which is less than the input voltage, is inversely related to the switching frequency. The circuit has a number of features: i. ii. iii. iv.

Turn-on and turn-off occur at zero current, hence switching losses are minimal. Increasing the switch off period (interval VI) decreases the average output voltage. At light load currents the switching frequency may become extreme low. The capacitor discharge time is tIII ≤ VCR t 4 × CR / I o , thus the output voltage is load current dependant. v. LR and CR are dimensioned such that the capacitor voltage is greater than Vs at time t4, at maximum load current Io. vi. Supply inductance is inconsequential, and decreases the inductance LR requirement. vii. Being based on the forward converter, the output voltage is less than the input voltage. The output increases with increased switching frequency. viii. If a diode in antiparallel to the switch is added as shown below figure 18.12b, reverse inductor current can flow and the output voltage is vo ≈ Vs × f s / f o . A full-wave resonant zero current switch circuit is formed.

18.5.1i - Zero-current, full-wave resonant switch converter By adding a diode in anti-parallel to the switch, as shown in figure 18.14 (and the circuit below figure 18.12b), resonant action can continue beyond ωt ≥ π . Assume the circuit has attained steady state load conditions from one cycle to the next. The cycle commences, before to, with both the capacitor voltage and inductor current being zero, and the load current is freewheeling through D1. The output inductor Lo, is large enough such that its current, Io can be assumed constant. The switch T1 is off.

Time interval IV After t5, the switch is off, the current freewheels through D1, the capacitor voltage is zero, and the input inductor current is zero. At time t1 the cycle recommences. The switch off-time, interval IV, t5 to the subsequent t0, is used to control the rate at which energy is transferred to the load.

Time interval I At to the switch is turned on and the series inductor LR acts as a turn-on snubber for the switch. In the interval to to t1, the supply voltage is impressed across LR since the switch T1 is on and the diode D1 conducts the output current, thereby clamping the associated inductor terminal to Vs. Because of the fixed voltage Vs, the current in LR increases from zero, linearly to Io in time 1 Zo Io (18.43) tI = I o LR / VS = ωo Vs

Output voltage

according to

R

The output voltage can be specified by either evaluating the energy from the supply, through the input resonant inductor LR, or by evaluating the average voltage across the resonant capacitor CR (or the freewheel diode D1) which is filtered by the output filter Lo - Co. By considering the input inductor energy (volt-second integral) for each period shown in the waveforms in figure 18.13b, the output energy, whence voltage, is given by

iL ( t ) = R

Vs t LR

and also iD1 ( t ) = I o − iL ( t ) = I o − R

R

Vs t LR

(18.44)

Power Electronics

835

Chapter 18

During this interval the resonant capacitor voltage is clamped to -Vs (with respect to input voltage positive terminal) since CR is in parallel with LR which is conducting Io: vc ( t ) = − Vs (18.45) Time interval II When the current in LR reaches Io at time t1, the capacitor CR and LR are free to resonant. The diode D1 blocks as the voltage across CR sinusoidally decreases. The constant load current component in LR does not influence its ac performance since a constant inductor current does not produce any inductor voltage. Its voltage is specified by the resonant cycle, provided Io < Vs / Zo. The capacitor resonantly charges to the opposite polarity +Vs when the inductor current falls back to the load current level Io, at time t3. Between times t3 and t4 the load current is displaced from LR by charge from CR, in a quasi resonance process. The resonant cycle reverses through the switch parallel diode DR once the inductor current reaches zero at time t4. Assuming a high circuit Q, the capacitor voltage and inductor current for period II, are given by (18.46) vC ( t ) = Vs (1 − cos ωo t ) R

V sin ωo t (18.47) Zo where Z o = LR / CR and ωo = 1/ LR CR . Equation (18.47) shows that the inductor current only returns to zero if Io < Vs / Zo, otherwise the switch is commutated with non-zero current flow. iLR ( t ) = I o + iC ( t ) = I o + R

.

LR

DR

CR

T1 on

(a)

D1

Io + Vs/Zo

τ ID1

ICR t1

t2

t3

t4

t5

I

By adding a diode in anti-parallel to the switch, resonant action can continue beyond ωt ≥ π . The capacitor can resonant to a lower voltage level, hence the capacitor linear discharge period starts from a lower voltage, equation (18.49). 2  I Z   (18.49) VC t 4 = Vs  1 + 1 −  o o     Vs    The lower limit of load current for proper circuit action is therefore decreased with full wave resonant circuits. Equations (18.31) to (18.42) remain valid except the time for interval II is extended to the fourth quadrant where iL = 0 and the capacitor voltage at t4 is decreased. That is  IZ  (18.50) tII =  2π − sin −1  o o   / ωo Vs     R

Time interval III Before time t4 the input current is zero and the switch T1 can be turned off with zero current, ZCS. The constant load current requirement Io is provided by the capacitor, which discharges linearly to zero volts at time t5 according to 2  I Z   I I (18.51) vC ( t ) = VC t 4 − o × t = Vs 1 + 1 −  o o   − o × t  CR  Vs   CR  where VC t 4 is given by equation (18.49).

II

III

IV

R

R

The inductor current is

iLR ( t ) = 0

(18.52)

Output voltage Since switch turn-off is dependent on the resonant cycle, the output voltage does not depend on the duty cycle, but is resonant period depend according to 2π LR C R 2π v o =Vs =Vs (18.54)

t

t0

2Vs

Vs

(18.48)

Time interval IV After t5, the switch is off, the current freewheels through D1, the capacitor voltage is zero, and the input inductor current is zero. At time to the cycle recommences. The switch off-time, interval IV, t5 to the subsequent to, is used to control the rate at which energy is transferred to the load.

Io

IDR

Vs Zo

R

ILR

t0

iT 1 = i LR = I o +

The time for interval III is load current dependant and is given by setting equation (18.51) to 0: 2  VC t 4 CR I Z   C tIII = = R × Vs  1 + 1 −  o o   (18.53)  Io Io  Vs   

T1 on

T1 off

836

The peak inductor current hence maximum switch current, from equation (18.47), is

R

T1

0


INTERVALS

τ

Vs

ωo τ

VCR (b) t1

t2

t5

t

t1

VLR

DR IT1

IT1 Io

Vs

IDR Io

Vs

Io

Io Vs

Vs

Io

Io

Io

(c)

Vs

Figure 18.14. Zero current switching, ZCS, full-wave resonant switch dc to dc converter with the resonant capacitor across the output: (a) circuit; (b) waveforms; and (c) equivalents circuits.

18.5.2 Zero-current, resonant-switch, dc-to-dc converter - ½ wave, CR parallel with switch version Operation of the ZCS circuit in figure 18.15 (figure 18.12c), where the capacitor CR is connected in parallel with the switch, is essentially the same as the circuit in figure 18.13. The capacitor connection produces the result that the capacitor voltage has a dc offset of Vs, meaning its voltage swings between ± Vs rather than zero and twice Vs, as in the circuit in figure 18.13. The zero current switching of T1 in figure 18.15 is analysed in five distinctive stages, as shown in the capacitor voltage and inductor current waveforms in figure 18.15b. The switch is turned on at to and turned off after t4 but before t5. Assume the circuit has attained steady state load conditions from one cycle to the next. The cycle commences, before to, with the inductor current being zero, the capacitor charged to Vs with the polarity shown, and the load current freewheeling through D1. The output inductor Lo, is large enough such that its current, Io can be assumed constant. The switch T1 is off. Time interval I At to the switch is turned on and the series inductor LR acts as a turn-on snubber for the switch. In the interval to to t1, the supply voltage is impressed across LR since the switch T1 is on and the diode D1

Power Electronics

837

Chapter 18

conducts the output current, thereby clamping the associated inductor terminal to Vs. Because of the fixed voltage Vs, the current in LR increases from zero, linearly to Io in time 1 Zo Io tI = I o LR / VS = (18.55) ωo Vs according to


Between times t3 and t4 the load current is displaced from LR by charge from CR, in a quasi resonance process. The resonant cycle cannot reverse through the switch once the inductor current reaches zero at time t4, because of the series blocking diode (the switch must have uni-directional conduction characteristics). Assuming a high circuit Q, the capacitor voltage and inductor current for period II, are given by vC ( t ) = −Vs cos ωo t (18.58) R

V (18.56) iL ( t ) = s t LR During this interval the resonant capacitor voltage is clamped to -Vs (with respect to input voltage positive terminal) since CR is in parallel with LR which is conducting Io: (18.57) vc ( t ) = − Vs R

Time interval II When the current in LR reaches Io at time t1, the capacitor CR and LR are free to resonant. The diode D1 blocks as the voltage across CR sinusoidally decreases. The constant load current component in LR does not influence its ac performance since a constant inductor current does not produce any inductor voltage. Its voltage is specified by the resonant cycle, provided Io < Vs / Zo. The capacitor resonantly charges to the opposite polarity +Vs when the inductor current falls back to the load current level Io, at time t3. +

CR

T1

.

Setting iL = 0 in equation (18.59) gives the time for period II as  I Z  tII =  π + sin −1  o o   / ωo Vs     at which time the capacitor voltage and inductor current are I Z  VCR t 4 = Vs 1 −  o o   Vs  I LR t 4 = 0

+ vo

D1 Co

Vs

V sin ωo t (18.59) Zo where Z o = LR / CR and ωo = 1/ LR CR . Equation (18.59) shows that the inductor current only returns to zero if Io < Vs / Zo, otherwise the switch is commutated with non-zero current flow. iL ( t ) = I o + iCR ( t ) = I o +

vC ( t ) = VC

-

R

where VC

R

t4

R

t4

−

Io

CR

Io + Vs/Zo

T1 on

T1 off

IT1

tIII =

Io

t3

t4

t5

II

III

IV

INTERVALS

0

t

VCR

t2

t5

IT1

IT1 Io

Io

Io Vs

×t

(18.62)

(18.63)

VC

R

t4

Io

CR

2  I Z   CR × Vs  1 + 1 −  o o    Io V  s   

=

(18.64)

τ

-Vs t1

Io

CR

Output voltage By considering the input inductor energy (volt-second integral) for each period shown in the waveforms in figure 18.15b, the output energy, whence voltage, is given by V vo = s (½tI + t II + t III )

VLR

-Vs

−

Time interval IV After t5, the switch is off, the current freewheels through D1, the capacitor voltage is - Vs, and the input inductor current is zero. At time t1 the cycle recommences. The switch off-time, interval IV, t5 to the subsequent t0, is used to control the rate at which energy is transferred to the load.

t

t0

Vs

I

2

ID1

ICR t2

I Z  × t = Vs 1 −  o o   Vs 

The time for interval III is load current dependant and is given by setting equation (18.62) to - Vs:

τ

t0 t1

(18.61)

iLR ( t ) = 0

ZCS T1 on

2

is given by equation (18.61).

The inductor current is 0

(18.60)

Time interval III At time t4 the input current is zero and the switch T1 can be turned off with zero current, ZCS. The constant load current requirement Io is provided by the capacitor, which discharges linearly to - Vs volts at time t5 according to

LR Lo

Vs

838

Vs

t1

Io

Io

2 (18.65)     Io Zo   I Z   C Vs  1  I o LR −1 × + Vs  1 + 1 −  o o   × R   π + sin    + ½    V V V I τ  ωo  S o   s   s      where the time intervals I, II, and III are given by equations (18.55), (18.60), and (18.64) respectively, the switching frequency f s = 1/ τ , and τ > t I + tII + tIII . The output voltage based on the average diode voltage (after resetting time zero references) is t5 −t4  1  t4 −t1 t   vo =  Vs (1 − cos ωt ) dt + VC t 4  1 −  dt  0 τ  0  t5 − t4   (18.66) 2 2   I Z  I Z  I Z   I Z   C 1 V  = ×  s  π + sin −1  o o  + o o  + ½ × Vs2 × 1 −  o o  ×  1 + 1 −  o o   × R   τ  ωo   Vs  Vs   Vs    Vs   I o    The output voltage in equation (18.66) reduces to equation (18.65).

=

Io

Vs

Figure 18.15. Zero current switching, ZCS, half-wave resonant switch dc to dc converter with resonant capacitor across the switch: (a) circuit; (b) waveforms; and (c) equivalents circuits.

∫

∫

R

Power Electronics

839

Chapter 18

18.5.3 Zero-voltage, resonant-switch, dc-to-dc converter - ½ wave, CR parallel with switch version The zero voltage switching of T1 in figure 18.16 (18.12e) can be analysed in four distinctive stages, as shown in the resonant capacitor voltage and inductor current waveforms. The switch is turned off at to and turned on after t4 but before t5. The circuit has attained steady state load conditions from one cycle to the next. The cycle commences, before to, with the capacitor CR voltage being zero and the load current Io being conducted by the switch and the resonant inductor, LR. The output inductor Lo is large enough such that its current, Io can be assumed constant. The switch T1 is on.


Time interval I At time to the switch is turned off and the parallel capacitor CR acts as a turn-off snubber for the switch. In the interval to to t1, the supply current is provided from Vs through CR and LR. Because the load current is constant, Io, due to large Lo, the capacitor charges linearly from 0V until its voltage reaches Vs in time V C V 1 tI = s R = s Io I o ωo Z o (18.67) LR where Z o = and ωo = LR CR CR according to Io t × t = Vs × CR tI

vc ( t ) =

The inductor current is zero, that is

CR

Lo

+ vo

D1 Co

VD1

Vs

(a)

-

Vs + Io Zo

T1 off

T1 on

VCR

C

τ

t0 t1

t2

t3

t4

VD1

t5

t6

t

t0

(18.70)

s

o

o

The capacitor energy transfers back to the inductor which has resonated from + Io to – Io between times t1 to time t3. For the capacitor voltage to resonantly return to zero, Io > Vs / Zo. Between t3 and t4 the voltage Vs on CR is resonated through LR, which conducts – Io at t3, as part of the resonance process. Assuming a high circuit Q, the resonant capacitor voltage and inductor current during period II are given by vC ( t ) = Vs + I o Z o sin ωo t (18.72) iL ( t ) = I o cos ωo t

Vs Vo

The freewheel diode voltage, which is related to the output voltage, is given by  I t  VD1 = Vs − vc = Vs − o × t = Vs ×  1 −  CR  tI 

Time interval II When the voltage across CR reaches Vs at time t1, (equation (18.67)), the load freewheel diode conducts, clamping the load voltage to zero volts. The capacitor CR and LR are free to resonant, where the initial inductor current is Io and the initial capacitor voltage is Vs. The energy in the inductor transfers to the capacitor, which increases its voltage from Vs to a maximum, at time t2, of v = V +I Z (18.71)

ZVS T1 off

(18.68)

(18.69)

R

T1

0

iL ( t ) = 0

LR

DR

840

R

V

Io

s

R

Io

L

and the duration of interval II is

R

I

II

III

IV

0

 V  tII =  π + sin −1 s  / ωo Io Zo  

INTERVALS

IT1

(b) t

ICR

At the end of interval II the capacitor voltage is zero and the inductor and capacitor currents are

ILR

iC

-Io t1

t2

t5

t6

(18.73)

R

(t ) = i (t ) = I LR

4

4

and

t1

o

 V  cos ωo tII = − I o 1 −  s   Io Zo 

vC ( tII ) = 0

(c)

R

(18.74)

(18.75)

The freewheel diode current at the end of interval II is  V  iD1 ( t4 ) = I o + I o 1 −  s   Io Zo 

(18.76)

0V

ILR

ILR

ILR Io

Io

Vs

Vs

ID1

ILR Io

Vs

ID1

Io

Vs

Figure 18.16. Zero voltage switching, ZVS, half-wave, resonant switch dc to dc converter: (a) circuit; (b) waveforms; and (c) equivalents circuits.

Time interval III At time t4 the voltage on CR attempts to reverse, but is clamped to zero by diode DR. The inductor energy is returned to the supply Vs via diode DR and the freewheel diode D1. The inductor current decreases linearly to zero during the period t4 to t5. During this period the switch T1 is turned on. No turn-on losses occur because the diode DR in parallel with T1 is conducting during the period the switch is turned on, that is, the switch voltage is zero and the switch T1 can be turned on with zero voltage, ZVS. With the switch on at time t5 the current in the inductor LR reverses and builds up, linearly to Io at time t6. The current slope is supply Vs dependant, according to Vs = LR di/dt, that is V (18.77) iL ( t ) = iD ( t ) = s t + I o cos ωo t II LR R

R

Power Electronics

841

and the time of interval III is load current dependant: I L t III = o R × (1 − cos ωo t II ) Vs The freewheel diode current is given by i D 1 (t ) = I o + i DR (t )

Chapter 18


842

CR

(18.78)

LR

T1

D1

(a)

(18.79)

Time interval IV At t6, the supply Vs provides all the load current through the switch resonant inductor, and the diode D1 recovers with a controlled di/dt given by Vs /LR. The freewheel diode Df supports the supply voltage Vs. The switch conduction interval IV, t6 to the subsequent to when the switch is turned off, is used to control the rate at which energy is transferred to the load.

T1 off

T1 off

T1 on

Vs + Io Zo

Output voltage

VCR

The output voltage, which is always less than the input voltage, can be derived from the diode voltage (shown hatched in figure 18.16b) since this voltage is averaged by the output L-C filter. 1 vo = ( Volt × second area of interval I + Volt × second area of interval IV )

Vs

τ

=

Vs

τ

= 2π

+ τ − t6 ) = Vs (1 − f s ( t6 − ½t1 ) ) 1

(½t

Vs 



(18.80)

t0

t1

t2

t3

VT1

t4

t5

t

t0

2Io

Io Zo  

I

1 −  ½ +  ωoτ   2π Vs  

VD1

VLR

II

III

IV

Io

(b)

ILR ILR

ICR

The circuit has a number of features:

INTERVALS

ICR

0

i. ii. iii. iv.

Switch turn-on and turn-off both occur at zero voltage, hence switching losses are minimal. At light load currents the switching frequency may become extreme high. The inductor defluxing time is tIII ≤ I L tII × LR / Vs , hence the output voltage is load current dependant. LR and CR are dimensioned such that the inductor current is less than zero (being returned to the supply Vs) at time t5, at maximum load current Io. Also Io>Vs/Zo. v. Being based on the forward converter, the output voltage is less than the input voltage. Increasing the switching frequency decreases the output voltage since τ - t5 is decreased in equation (18.80). R

18.5.3i - Zero-voltage, full-wave resonant switch converter By removing the supply return diode in the half-wave ZVS converter in figure 18.12e (figure 18.16) a full wave ZVS resonant converter is formed, where the capacitor sinusoidal oscillation can continue past π, t4, as shown in figure 18.17. Consequently, the inductor current attains a level closer to the load level, Io, before the capacitor voltage oscillation is complete, thereby shortening the cycle time. 18.5.4 Zero-voltage, resonant-switch, dc-to-dc converter - ½ wave, CR parallel with load version Operation of the ZVS circuit in figure 18.12d, where the capacitor CR is connected in parallel with the load circuit (the freewheel diode D1), is essentially the same as the circuit in figure 18.17. The capacitor connection produces the result that the capacitor voltage has a dc offset of Vs, meaning its voltage swings between + Vs and -Io Zo, rather than zero and Vs - Io Zo, as in the ZVS circuit considered in 18.5.3. Specifically the inductor waveforms and expressions are unchanged, as is the output voltage expression (18.80). The expression for the time of each interval is the same and the capacitor voltage waveform equations are negated, with Vs then added. Any dc supply inductance must be decoupled when using the ZVS circuit in figure 18.12d. It will be noticed that, at a given load current Io, a ZCS converter has a predetermined on-time, while a ZVS converter has a predetermined off-time.

t1

t2

ICR

t5

t1

-Io

Figure 18.17. Zero voltage switching, ZVS, full-wave resonant switch dc to dc converter with the resonant capacitor across the switch: (a) circuit and (b) waveforms.

Example 18.2: Zero-current, resonant-switch, step-down dc-to-dc converter - ½ wave The ZCS resonant dc step-down voltage converter in figure 18.13a produces an output voltage for the armature of a high voltage dc motor and operates from the voltage produced from the 50Hz ac mains rectified, 340V dc, with an L-C dc link filter. The resonant circuit parameters are LR = 100µH, CR = 0.47µF, and the high frequency ac resistance of the resonant circuit is Rc = 1Ω. Calculate i. the circuit Zo, Q, and ωo ii. the maximum output current to ensure ZCS occurs iii. the maximum operating frequency, represented by the time between switch turn on and the freewheel diode recommencing conduction, at maximum load current iv. the average diode voltage (capacitor voltage), hence load voltage at the maximum frequency v. switching frequency for vo = 170V dc and RL = 17Ω, peak input current, and diode maximum reverse voltage. Solution i. The characteristic impedance is given by LR 100µH Zo = = = 14.6Ω CR 0.47µF The resonant circuit Q is Zo 100µH = /1Ω = 14.6 Rc 0.47µF For this high Q, the circuit resonant frequency and damped frequency will be almost the same, that is Q=

Power Electronics

843

Chapter 18

  −1  I o Z o   π + sin  Vs  I o LR   Vs + vo = ×  ½ VS τ ωo   

ω ≈ ωo = 1/ LR CR = 1/ 100µH × 0.47µF = 146 krad/s = 2π f f = 146 krad/s /2π = 23.25 kHz or T = 43µ s

ii. For zero current switching, the load current must not be greater than the peak resonant current, that is I o < Vs / Z o = 340V/14.6Ω = 23.3A iii.

The commutation period comprises the four intervals, I to IV, shown in figure 18.13b.

Interval I The switch turns on and the inductor current rises from 0A to 23.3A in a time given by tI = LR ∆I / Vs

=100µH×23.3A/340V = 6.85µs Interval II These two sub-intervals take over half a resonant cycle to complete. Assuming action is purely sinusoidal resonance then from equation (18.36)  IZ  tII =  π + sin −1  o o   / ωo Vs     = π + sin −1 23.3A × 14.6Ω /146krad/s = 32.27µs 340V The capacitor voltage at the end of this period is given by VC t 4 = Vs (1 − cos ωo t II )

(

))

(


   

844

  2   I o Z o   CR   + Vs 1 + 1 −   ×    Vs   I o    

  −1  10A × 14.6Ω   2    π + sin  340V  340V  10A × 100µH     10A × 14.6Ω  170V = × ½× + + 340V × 1 + 1 −     340V 146krad/s 340V τ      That is, τ = 108.2µs, or fs = 9.25kHz. The peak input current is the peak inductor current is V 340V I i /p = I LR = I o + s = 10A + = 33.3A Zo 14.6Ω The diode peak reverse voltage is 2×Vs = 640V ♣

  0.47µF   ×  10 A    

Example 18.3: Zero-current, resonant-switch, step-down dc-to-dc converter – full-wave In example 18.2, a diode is connected in anti-parallel with the switch (figure 18.14), forming a quasi resonant full-wave switch, dc converter. Using the data in example 18.2: i. Determine the maximum operating frequency with a 10A load current. ii. Repeat the calculations when an infinite Q is not assumed.

R

Solution

= 340V × (1 − cos 3 2 π ) = 340V

Interval III The capacitor voltage must discharge from 340V dc to zero volts, providing the 23.3A load current. That is tIV = VCR t 4 × CR / I o

= 340V×0.47µF/23.3A = 6.86µs The minimum commutation cycle time is therefore 6.85+32.27+6.86 = 46µs. operating frequency is 21.75kHz.

1

5

4

R

 1 = × 46µs 

∫

32.27µs o

340V × (1 − cos ωt ) d ωt +

∫

6.86µs 0

 t   340V ×  1 −  dt   6.86µs  

1    3π  43µs +1 × + ½ × 340V × 6.86µs  = × 340V ×  46µs   2  2π  1 × [13292Vµs + 1166Vµs ] = 314.3Vdc = 46µs

The maximum output voltage is 314V dc. Alternatively, using the input inductor energy based equation (18.41): V vo = s (½tI + t II + III + t IV )

τ

=

ωo = 1/ LR CR = 1/ 100µH × 0.47µF = 146 krad/s Zo =

LR 100µH = = 14.6Ω CR 0.47µF

α=

Thus the maximum

iv. The output voltage vo is the average reverse voltage of freewheel diode D1, which is in parallel with the resonant capacitor CR. Integration of the capacitor voltage shown in figure 18.13b gives equation (18.42) t −t  1  t −t t   vo =  ∫ Vs (1 − cos ωt ) dt + ∫ VC t 4  1 −  dt  0 t5  0  t5 − t4   4

Using the data in example 18.2:

340V × (½ × 6.85µs + 32.25µs + 6.86µs ) = 314.4V 46µs

v. When the output current is vo /RL=170V/17Ω=10A, the operating frequency is obtained from equation (18.41)

Q=

Zo 100µH = /1Ω = 14.6 Rc 0.47µF

R 1Ω = = 5, 000 2 L 2 × 100µH

ω = ωo2 − α 2 =

(146krad/s )

2

− 0.0052 = 146.1 krad/s

i. Three intervals are involved. Interval I is given by equation (18.29) tI = LR ∆I / Vs =100µH×10A/340V = 2.94µs The time for interval II is given by equation (18.50)  IZ  tII =  2π − sin −1  o o   / ωo Vs     /146krad/s = 40.0µs = 2π − sin −1 10A × 14.6Ω 340V The capacitor voltage at the end of interval II is VC t 4 = Vs (1 − cos ωo t II )

(

))

(

R

= 340V × (1 − cos (146krad/s × 40.0µs )) = 32.8V Interval III The capacitor voltage must discharge from 32.8V dc to zero volts, providing the 10A load current. That is tIV = VC t 4 × CR / I o R

= 32.8V×0.47µF/10A = 1.5µs The minimum commutation cycle time is therefore 2.94 + 40 + 1.5 = 44.44µs. Thus the maximum operating frequency is 22.5kHz. ii. Circuit Q does not affect the first interval, which from part i. requires 2.94µs. When a finite Q of 14.6 is used, equations (18.31) and (18.32) are employed for the second interval, the resonant part of the cycle. From equation (18.32)

Power Electronics

845

ic (ωt ) =

Vs

ωL

Chapter 18

× e −α t × sin ωt

− 1Ω t 340V × e 2×100µH × sin (146krad/s × t ) 146krad/s × 100µH which yields t = 39.27µs. The capacitor voltage at this time is given by equation (18.31), that is vc (ω × t ) = Vs (1 − e −α t cos ωt )

−10 A =

vc (146krad/s × 39.27µs) = 340V × (1 − e −5,000×39.27µs × cos (146krad/s × 39.27µs ) )

= 101.8V The time for interval III is given by equation (18.40), that is VC t 4 CR 101.8V × 0.47µF tIII = = = 4.78µs 10A Io The minimum commutation cycle time is therefore 2.94 + 39.27 + 4.78 = 47.0µs. Thus the maximum operating frequency is 21.3kHz, which is required for maximum voltage output at 10A. R

The main effect of a finite Q is to result in a higher voltage being retained on the capacitor to be discharged into the load at a constant rate, during interval III. Never-the-less this voltage is much less than that retained in the half-wave resonant switch case. ♣ Example 18.4: Zero-voltage, resonant-switch, step-down dc-to-dc converter - ½ wave The zero voltage resonant switch converter in figure 18.16 operates under the following conditions: Io = 25A Vs = 192V LR = 10µH CR = 0.1µF Determine i. ii. iii. iv.

the minimum output current the switching frequency fs for vo = 48V switch average current and the peak switch/diode/capacitor voltage.


846

iii. The switch current is shown by hatched dots in figure 18.16. The average value is dominated by interval IV, with a small contribution in interval II between t5 and t6.  I  ½ × t III + (τ − t6 )  IT = o ×  τ  1 + cos ωo t II   ½ × 2.136µs 1   = 25A × 114.7kHz  + − ( 0.768µs + 4.017µs + 2.136µs )    1 + cos (106 × 4.017µs )  114.7kHz    = 7.0A iv. The peak switch/diode/capacitor voltage is given by equation (18.71), namely v = V +I Z C

s

o

o

= 192V + 25A × 10Ω = 442V ♣

18.6

Resonant-switch, dc-to-dc step-up voltage converters

18.6.1 ZCS resonant-switch, dc-to-dc step-up voltage converters The zero current resonant ZCS (and ZVS) principle can be applied to the step-up converter (and buckboost converter), as shown in figure 18.18b. The resonant L-C circuit around the switch does not affect the primary boosting function, but only facilitates resonant switching of switch T. But now the output voltage is determined by the switch off-time. When the switch T is off, the input inductor L provides near constant current to the output circuit through diode D. The inductor current Ii comprises the load current Io and the output capacitor current Ic. The resonant capacitor CR is charged to the output voltage vo, as is the output capacitor C. Period 1: tP1 When the switch is turned on at to, the input current Ii is progressively diverted to the resonant inductor LR as its current builds up linearly according to

i LR (t ) =

vo t LR

(18.81)

The current to the output circuit, ID, through diode D, decreases linearly according to

Solution

ωo =

1 LR CR

=

1 10µH × 0.1µF Zo =

i D (t ) = I i − i LR (t ) = I i −

= 1× 106 rad/s that is f o = 159.2kHz

(18.82)

At time t1 the resonant inductor consumes all the input current, when

LR 10µH = = 10Ω 0.1µF CR

LR I i vo

tP1 =

i. For proper resonant action the maximum average output current must satisfy, I o > Vs / Z o , that is V 192V = 19.2A Io = s = 10Ω Zo Since the load current, 25A is larger than the minimum current requirement, 19.2A, the switch voltage will be reduced zero giving ZVS turn-off. ∨

ii. The period of interval I is given by equation (18.67), that is V C 192V × 0.1µF tI = s R = = 0.768µs 25A Io The period of interval II is given by equation (18.73), that is  V  192V   6 tII = t3 − t1 =  π + sin −1 s  / ωo =  π + sin −1  /10 rad/s = 4.017µs 25A × 10Ω  Io Zo    The period for the constant current period III is given by equation (18.78) I L 25A × 10µH × 1 − cos (106 × 4.017µs ) = 2.136µs t III = o R × (1 − cos ωo t I 1 ) = Vs 192V After re-arranging equation (18.80), the switching frequency is given by  vo  48V   1 −  1 −  Vs   192V  fs =  = = 114.7kHz t5 − ½t1 ( 0.768µs + 4.017µs + 2.136µs − ½ × 0.768µs )

(

vo t LR

)

(18.83)

Period 2: tP2 The resonant capacitor can now resonate through LR and the switch T. The inductor resonant current is superimposed on the constant input current, the constant current not producing any voltage across the inductor since di/dt is zero for a constant current. The inductor, hence switch, current is

i LR (t ) = I i + where

vo sin ωt Z

(18.84)

L 1 Z = R and ω = CR LR C R

while the resonant capacitor current is

i CR (t ) = −

vo sin ωt Z

(18.85)

The resonant capacitor and inductor are in parallel hence

v LR (t ) = v CR (t ) = LR

di LR = v o sin ωt t

(18.86)

The maximum switch capacitor and inductor currents occur at t2, namely ωt = ½π , when

iCR = −

vo Z

iT = i LR = I i +

vo Z

(18.87)

Power Electronics

847

Chapter 18

The resonant capacitor current is zero when the inductor current falls back to the input current level Ii, that is, at time t3 when ωt = π . The oscillation continues according to equation (18.84) and the resonant inductor current falls to zero at t3, namely time ZI 1 t LR =0 = π + sin−1 i (18.88)

ω


The inductor current returns to zero at time t5 ZI  1 t P 2 = 2π − sin−1 i  ω vo  The capacitor voltage is given by equation (18.86) at the time tP2, namely  ZI i    vo 

v LR (t P 3 ) = v CR (t P 3 ) = v o sin ωt P 3 = v o 1 − 

vo

when the resonant circuit voltage from equation (18.86) is  ZI i    vo 

v LR (t LR =0 ) = v CR (t LR = 0 ) = −v o 1 −  and the resonant capacitor current is

2

(18.89)

i CR (t LR =0 ) = I i

(18.90)

The input current now charges the resonant capacitor with a constant current Io. Ii

L Ei

Ii

Io

L

D T

+

+

R

vo

Vs

IC

LR

+

CR

+

R

v CR (t ) = v CR (t P 3 ) + vo

T

C

C DR

switch mode

ZCS full-wave

(a)

(b)

T on

The alternative boost resonant ZVS converter in figure 18.19a uses a constant current input as in figure 14.35 in chapter 14.3.4, but the output is half wave rectified by the diode Drect.

tP1 =

Ii ID

ICR

t3

t4

IDR

t5

t6

t

t0

-Ii

I

II

III

IV

vo

INTERVALS

VCR LR

VLR

VLR

-vo

t2

VCR

Ii t CR

(18.94)

VLR

t6

t1

(c)

Figure 18.18. Zero current switching, ZCS, full-wave resonant switch dc to dc step-up voltage converter: (a) conventional smps circuit; (b) ZCS resonant circuit; and (c) waveforms.

During period 2, all the load current Io is provided by the output capacitor C, and the output diode D is reverse biased. Due to the resonant capacitor retaining a negative voltage at time t4, the resonant oscillation current reverses for a negative half resonant cycle through the switch antiparallel diode DR. During this period when the antiparallel diode DR conducts, the switch can be turned off under a zero current condition.

vo C Ii R

(18.95)

Period 2: tP2 The output rectifying diode Drect is able to conducts and allows L-C resonance between LR and CR where the inductor is clamped to the output voltage vo and both LR and CR are fed from the constant current source Ii. These two dc conditions do not prevent an ac resonant oscillation from occurring. The voltage across the capacitor increasing from vo at time t1 according to v CR (t ) = v o + I i Z sin ωt (18.96) where Z =

0

t1

(18.93)

The capacitor and switch voltage rise linearly until equal to the output voltage vo, when the output rectifying diode becomes forward biased at time t1. The time for this first period is

ILR

t2

Ii t CR

Period 1: tP1 The resonant capacitor charges with the constant input current which is diverted by the turn-off of switch T. The capacitor and parallel connected switch voltages increases according to

Ii + vo / Z

t1

(18.92)

18.6.2 ZVS resonant-switch, dc-to-dc step-up voltage converters

VT (t ) = VCR (t ) =

t0

2

Initially, before to, the switch is on and the load requirement Io is being provided by the output capacitor C. The large input inductance ensures a constant input current Ii, which is conducted by the switch T. The resonant circuit capacitor voltage is zero, as is the initial resonant inductor current. The switch T is turned off at to and the resonant circuit waveforms as in figure 18.19 parts b and c occur.

T on

T off

(18.91)

Period 3: tP3 The constant input current Ii charges the resonant capacitor CR linearly to the output voltage level vo. At this voltage the output capacitor C ceases to provide load current Io since diode D conducts and the input current provides the load current Io and replenishes to output capacitor C with the remainder of the input current, Ii - Io. The charging time of the resonant capacitor CR is load current magnitude Io dependent.

Io

D

848

LR 1 and ω = CR LR C R

The inductor voltage hence current are v LR (t ) = v o − v CR (t ) = −I i Z sin ωt

i LR (t ) = I i (1 − cos ωt )

(18.97)

This inductor current replenishes to output capacitor C whilst providing a portion of the load current Io. The capacitor current resonantly decreases from Ii according to i CR (t ) = I i − i LR = I i cos ωt (18.98) This period continues until the capacitor voltage given by equation (18.96) reaches zero at time t4. This zero voltage condition is necessary if the switch is to turn-on with zero voltage and from equation (18.96) a zero voltage condition occurs provided Ii Z > vo. The capacitor voltage reaches zero and attempts to reverse at time t4. The duration of the resonant period is v  π + sin−1  o   Ii Z  tP 2 = (18.99)

ω

Power Electronics

849

Chapter 18

The inductor current (whence capacitor current) at the instant t4 is 2  V   i LR (t 2 ) = I i 1 + 1 −  o     I i Z   

Ii

+

L

T

(18.100)

 Vo    Ii Z  LR

Drect

2

t P 3a =

iT (t ) = I i − I LR (t ) = R

+

2

V  I 1 −  o  = LR i vo  Ii Z 

1 Ii Z ω vo

V  1− o   Ii Z 

2

(18.103)

At time t5, the resonant inductor current is the input current Ii and the switch is turned on between t4 and t5 in order to achieved zero voltage turn-on ZVS. The inductor current continues to fall at the same rate to zero as the switch current linearly increases to Ii

Io

Vs

(18.102)

And reaches zero at time t5 after a period

IC

CR

DR

850

 Vo  v o  + t LR  Ii Z 

i DR (t ) = I i − i LR (t ) = −I i 1 − 

2

i CR (t 2 ) = i LR (t 2 ) − I i = I i 1 − 


vo

vo t LR

(18.104)

The inductor current reaches zero time t6 that is input current Ii (hence load current Io) dependent. The time for the inductor current to fall from the input current level Ii at time t5 to zero at time t6 is:

C

(a)

ZVS

t P 3b = LR

Ii vo

(18.105)

The time for the third period (t3 to t6) is  V   Ii  1+ 1− o    vo  Ii Z   2

T off

t P 3 = T P 3a + t P 3b = LR

T off

T on

τ

0

vo + Ii Z

(18.106)

  At time t6 the switch conducts the input current Ii. and can be turned off so as to control the output voltage vo.

VCR

Summary and comparison of ZCS and ZVS Converters vo Vs

t0 t1

t2

t3

t4

t5

t6

t

t0

(b)

ILR ILR

V

o

L

R

Ii

Ii

I

II

III

IT

IV

INTERVALS

The main characteristics of ZCS and ZVS are: • Switch turn-on and turn-off occur at zero current or zero voltage, thus reducing switching losses. • Rapid switch current and voltage changes are avoided in ZCS and ZVS, respectively. The di/dt and dv/dt values are small, hence EMI is reduced. • In the ZCS, the peak current Io + Vdc /Zo conducted by the switch is more than twice as high as the maximum of the load current Io. • In the ZVS, the switch must withstand a forward voltage Vdc + ZoIo, while ZoIo must exceed Vdc. • The switching frequency varies the output voltage. • Switch parasitic capacitances are discharged during turn-on in ZCS, which can produce significant switching loss at high switching frequencies. This does not occur with ZVS. Table 18.3: Characteristics of resonant tank circuits characteristic

0 t

ICR

(c) -Ii

t1

t2

t5

t6

series

parallel

series/parallel

constant

Load dependent

Load dependent

Open circuit output

OK

Large current near resonance ωo

Short circuit output

High current near resonance ωo

Protected by L at all ω

Large current near resonance ωo High current near resonance ωo

Resonant frequency ωo

t1

Figure 18.19. Zero current switching, ZVS, full-wave resonant switch dc to dc step-up voltage converter: (a) ZCS resonant circuit; (b) resonant capacitor voltage; and (c) current waveforms.

Output voltage frequency sensitivity Equivalent load, Req

Period 3: tP3 At time t4 the diode DR conducts, preventing the resonant capacitor from charging negatively. The resonant inductor releases its energy into the load circuit at a constant voltage vo, according to 2  V   v (18.101) i LR (t ) = I i 1 + 1 −  o   − o t   I i Z   LR  The diode DR current decreases linearly to zero at time t5 according to

18.7

High at no load and light loads 8

π2

Rload

Good light load regulation but low efficiency π2 8

Rload

OK but extra resonant component π2 8

Rload

Appendix: Matrices of resonant switch buck, boost, and buck/boost converters

A series switch diode may not be necessary when an inverse parallel diode is used, as with full-wave ZCS and half-wave ZVS circuits. In the following circuits, the series diode (preferably in the drain circuit) is used to block the MOSFET internal parasitic diode, which may have poor recovery characteristics.

Power Electronics

851

Ii

Chapter 18


Io

L

Ii

Io

L Ei

T

+

+

R

852

vo

Ei

vo ≤ Ei

D T

+

+

C

vo

R

vo ≥ Ei

C

ZCS full-wave

ZCS half-wave

ZCS full-wave

ZCS half-wave Ii

Ii

Io

L

+

D1

T

Ii

LR

LR Ei

Io

L

+

CR

R

vo

Ei

+

T

D1

+

CR

R

vo

LR

+

+

CR

CR

CR

Ii

Io

L

Io

L

CR

Ii

Ei

+

D1

T

+

R

vo

Ei

+

D1

T

+

R

vo

LR

+


+

+

+

CR

R

vo

Ei

+

T

D1

+

CR

CR

CR

Ii

Io

L

+

T

R

vo

vo

Io

D

L Ei

LR

+

+ T

R

vo

C

ZVS half-wave

Ii

Io

D

Ei

D1

+

R

vo

Ei

+

T

D1

C

+ C

LR

+ CR

Io

L

L

L

vo

R

+ T

Ii

LR

LR Ei

R

CR

Ii

Io

D

R

C


Ii

C

C

Ii

+ T

LR D1

T

CR

C

ZVS full-wave Io

L

LR Ei

ZVS half-wave

Ii

Io

L

LR

+

L Ei

T

Ii

Ei

C

C

ZVS full-wave

vo

Io

D

LR

LR

R

C

T

Ii

Io

D L

L Ei

C

C

Ii

Io

D

R

vo

Ei

CR

Ii

Io

D

Ei

CR

vo

C

Io

D

+ T

C

R

vo

Ei

LR

+ CR

+ T

Figure 18.21. Setup (boost) voltage converter resonant switch circuits. Figure 18.20. Forward (buck) voltage converter resonant switch circuits.

R

L LR

+

+ T

C

L

vo

LR

+

C

R

vo

Power Electronics

853

Ii

Chapter 18


854

Io

D

Reading list Ei

T

+

C R

L

vo

Hart, D.W., Introduction to Power Electronics, Prentice-Hall, Inc, 1997.

vo ≤ 0 +

Mohan, N., et al., Power Electronics, 3rd Edition, Wiley International, 2003.

ZCS full-wave

ZCS half-wave Ii

Ii

Io

D

+

Problems

LR L

T

Io

D

LR Ei

Thorborg, K., Power Electronics – in theory and practice, Chartwell-Bratt, 1993.

C

CR

R

vo

Ei

+

T

L

C

CR

R

vo

18.1. The series resonant dc converter in figure 18.1a operates from a 340V dc supply at 100kHz with a 17Ω load. If the series L-C resonant components are 100µH and 47nF, determine the output voltage assuming high resonant circuit Q.

+

+

Series resonant dc to dc converter

18.2 If the operating frequency in problem 18.1 is decreased to 50kHz, determine suitable L-C values if the output voltage to be halved. CR

Ii

CR

Ii

Io

D

LR

LR Ei

+

L

T

Parallel resonant dc to dc converter

Io

D

C

R

vo

Ei

+

L

T

C

R

vo

+

+

18.3. The series resonant dc converter in figure 18.5a operates from a 340V dc supply at 100kHz with a 17Ω load. If the parallel L-C resonant components are 10µH and 470nF, determine the output voltage assuming high resonant circuit Q. 18.4 If the operating frequency in problem 18.3 is decreased to 50kHz, determine suitable L-C values if the output voltage to be halved. Zero-current resonant switch converter


ZVS full-wave Ii

+

L

T

C

CR

R

vo

Ei

+

T

Zero-voltage resonant switch converter L

C

CR

CR

CR

Ii

Io

D

+

T

vo

18.6 The zero current resonant switch converter in figure 18.16a operates with a 20V dc input supply and resonant L-C values of 10µH and 100nF, and a 5A output load requirement. Determine i. the output voltage if the switching frequency is 100kHz ii. the switching frequency if the output voltage is 10V In each case determine the maximum capacitor voltage and maximum inductor current.

Io

D

LR

LR Ei

R

+

+

Ii

Io

D LR

LR Ei

ZVS half-wave

Ii

Io

D

18.5 The zero current resonant switch converter in figure 18.13a operates with a 20V dc input supply and resonant L-C values of 5µH and 10nF, and a 5A output load requirement. Determine i. the output voltage if the switching frequency is 100kHz ii. the switching frequency if the output voltage is 10V In each case determine the maximum capacitor voltage and maximum inductor current.

L

C

R

vo

Ei

+

T

L

+

Figure 18.22. Setup/down (buck/boost) voltage converter resonant switch circuits.

C +

R

vo

Chapter 19 Y Y

CHAPTER

19

q =3 r =1 s = 2 p=qxrxs p = 12 Y Y

HV Direct-Current Transmission

HVDC

856

Y Y

Id

Y Y

Id

Y Y

(a)

Id

Y ∆

Y Y

∆ Y

(b)

q =3 r =1 s = 4 p=qxrxs p = 12

Y ∆

∆ Y

Y Y

Y Y

Y ∆

Id

∆ Y

(c)

Figure 19.1. HVDC transmission systems: (a) 6 pulse monopole; (b) 12 pulse monopole; and (c) 12 pulse bipolar, converter bridge configurations.

19.2

Originally electrical power generation, transmission, and distribution systems were direct current. The advent of the three-phase induction motor and the ability of transformers to converter one ac voltage to another ac voltage level (at the same frequency), saw the unassailable rise to dominance of ac electrical power systems. But for long distance electrical power transmission, of just a few hundred kilometres of typically about 200 to 350km, a dc transmission system is a viable possibility. For underwater or underground electrical power transmission, ac may not be viable at just 50km due to high capacitive charging currents because of the close proximity of the cables (particularly subsea cables). The highest functional dc voltage for dc transmission, HVDC, is ±600kV over 785km and 805km transmission lines in Brazil. Each of the two bipolar dc transmission systems carry 3.15GW. Also involved are three, threephase 765kV ac lines which are 1GVAr variable capacitor series compensated (FACTS) at two intermediate substations.

19.1

HVDC Electrical Power Transmission

Electrical power is generated in ac form and is also usually distributed and consumed in an ac form. Its long distance transmission between these two stages may be an ac or a dc transmission system. In a high-voltage dc (HVDC) system the generated 50/60Hz ac is controlled-rectified to dc, transmitted, then at the receiving end, converted from dc back to 50/60Hz ac. A HVDC system is two ac systems connected by a dc transmission system, where the ac systems can be totally independent. The dc-link of a HVDC transmission system is either • A controlled voltage dc-link or • A controlled current dc-link. A HVDC controlled current link has the following characteristics. The link in highly inductive, achieved with series inductance at each end. The converter/inverter technology is operated in a controlled current mode, thus the converter/inverter devices require reverse voltage blocking ability. Symmetrical blocking thyristor devices are applicable, but such devices are restricted to line commutation and phased control. A HVDC controlled voltage link has the following characteristics. The link in highly capacitive, achieved with parallel connected capacitance at each end. The converter/inverter technology is operated in a controlled voltage mode, thus the converter/inverter devices can be uni-directional voltage blocking IGBT technology. Since devices are gate commutatable, a switching frequency of kHz’s is possible, thus PWM techniques can be employed for harmonic minimisation.

BWW

HVDC Configurations

There are a number of different configurations for transmitting dc power, depending on the number of cables employed. Each uses a three-phase fully-controlled thyristor converter (rectifier) coupled through a dc link to another identical three-phase fully-controlled thyristor converter (inverter). Both converters have the same modular structure except the converter connections to the dc link are interchanged for one converter, hence power flow is fully reversible. Since the valves can only conduct current in one direction, power reversal is achieved by changing the polarity of the dc link terminal voltages through control of the converter thyristor firing delay angles. The rectification mode (positive dc link voltage) is achieved with thyristor firing angles of 0 < α < ½π while inversion (negative dc link voltage) is achieved with firing angles of ½π < α < π. Because one converter terminal connection is reversed, a rectifying voltage (0 < α < ½π) is opposed by an inverting voltage (½π < α < π) – subtractive not additive voltages. 19.2i - Monopole and earth return The monopole configurations shown in figure 19.1 parts a and b (6 pulse and 12 pulse respectively) use just one transmission cable and earth is used as the negative return. Occasionally, a metal earth return may be used, but importantly any return is at ground potential thus does not need the full transmission voltage insulation. The converter output terminals are reversed relative to one another, as indicated by the direction of the thyristors in the symbol blocks. Issues involved in using a ground return are • Electrochemical corrosion of buried metals objects, like pipelines • Electrode chemical reaction under the sea • Magnetic field disturbances when the go and return paths become unbalanced The monopole system is limited in power handling capability, typically 1.5GW above the ground, and 600MW below the ground or under the sea. 19.2ii - Bipolar In the bipolar arrangement two high voltage conductors, at opposite potentials with respect to ground, are used as shown in figure 19.1c. Any pole imbalance uses an earth return, if a low-voltage metal ground return is not used. The bipolar configuration has a number of advantages over the monopole arrangement. • Normally no earth-current flows which minimises earth losses and any earth related environmental effects, including minimal corrosion of underground system metal components • If a fault develops on one pole, the other pole can continue to operate in a monopole arrangement, using the earth as the return path • For a given power rating, each conductor has half the cross-sectional area of the monopole line, thus reducing the extra cost of using a second conductor • The same dc transmission line towers can carry two lines with a small additional capital cost A homopolar hvdc link is formed if the two high voltage conductors have the same polarity, with, undesirably, a high ground or metal return current. The bipolar system is capable of higher transmission powers than the monopole configuration. Bipolar systems can carry over 3GW at voltages of over ±500kV, over distances well in excess of 500km.

Power Electronics

857

Chapter 19

19.2iii - Tripole Two of the three conductors of an ac system are used in a bipolar configuration, with the third conductor used as a parallel monopole with bidirectional power flow capability. The bidirectional capability of the third conductor allows each of the two bipolar conductors to carry higher than rated current when each in turn is relieved periodically by the monopole system, such that all three conductors do not exceed rated I2R losses. In this way each of the three conductors experience the same thermal losses. This is achieved if the bipolar currents are cycled every few minutes between 0.366pu ½ 3 − 1 and 1.366 pu ½ 3 + 1 , with ±1 pu being appropriately alternated in the monopole. As a result, 80% more power can be transmitted compared with the ac equivalent, using the same conductors, towers, etc. Unlike the ac equivalent, the dc system can be fully loaded without system instability or need for reactive power compensation.

(

(

)

)

19.2iv - Back-to-back Two different asynchronous ac systems in close proximity, possibly operating at different frequencies, can be interconnected by either a monopole or bipolar system. Since no dc transmission cables are necessary, because of the close proximity of the two systems, the system type and voltage level are not restrictive.

19.4

858

Twelve-pulse ac line frequency converters

The six-pulse line-frequency fully-controlled thyristor converter was discussed in chapter 12.6. Harmonic filters are required on both the ac and dc side of the converter as shown in figure 19.4. The ac side harmonics occur at 6n±1 the fundamental, while the dc side harmonics are generated at 6n. In order to reduce the filtering requirements, and increase the effectiveness of the filtering, on both the ac and dc sides, most high power HVDC systems use 12-pulse, phase-shited transformer/converter arrangements. The ac side harmonics now occur at 12n±1 and the dc components are generated at 12n. Twelve-pulse converter operation is achieved by using the series bridge connection in conjunction with ∆-Y and Y-Y compound connected transformers as shown in figure 19.3b. (A delta connection is usually employed on the lower voltage side of the transformer.) Figure 19.7a shows the arrangement in more detail, with the necessary transformer turns ratio to ensure each converter bridge produces the same output voltage at the same thyristor firing delay angle. Voltage matching between the ac line and required dc link voltage is achieved with the transformer turns ratio N, shown in figure 19.7a. The series thyristors in each bridge provide paths which allow both converter currents to be equal.

19.2v - Multi-terminal More than two converters are connected to the same dc link, where simultaneously, at least one converter operates in the rectification mode and at least one other converter operates in an inversion mode. Mechanical switching of the converter terminals is necessary. The control system is more elaborate than for normal point-to-point transmission and power reversal is affected by current reversal.

19.3

HVDC

DC side

AC side a

Y Y 6 pulse valve group

Typical HVDC transmission system

b

A fully modular hardware structure is used. Each 8.8kV symmetrically blocking thyristor is configured in a module with its gate electronics and RC snubber as shown in figure 19.2. Many thyristors are connected in series to form a valve, with internal static voltage sharing resistors and a saturable reactor turn-on snubber as shown in figure 19.2a. Six valves are needed to form the 6 pulse valve group converter bridge in figure 19.3a, while 12 valves are used to form the twelve pulse value group converter in figure 19.3b. Each group of four valves in a single vertical stack form quadrivalves as shown in figure 19.3b. Each quadrivalve may contain hundreds of series connected thyristors to give the necessary hundreds of kV pole voltage rating. Typical six and twelve pulse valve group configurations are shown in figure 19.3, which form the unipolar converters in figure 19.1 parts a and b respectively. A more detailed circuit diagram of the 12-pulse converter and its MOV voltage protection and dc and ac harmonic filtering circuitry, in a substation installation, is shown in figure 19.4. The dc inductors Ldc in each pole assist in filtering harmonic currents and smooth the dc side current thereby reducing the current level for the onset of discontinuous current flow. Because the inductors control the dc link side di/dt, converter commutation is more robust. No dc filters may be necessary with the back-to-back HVDC converter configuration.

c

valves shaded

q =3 r =1 s =2 p=qxrxs p=6

Y Y (a)

Y ∆

AC side

Y∆

(b)

DC side

a Y∆

b Saturable reactor

Y Y

c

C1

RC snubber damping circuits

Valve electronics

a 3 Quadrivalves shaded

C2 C1>>C2 b

Static voltage sharing resistors

(a) Vf/b

(b)

Valve electronics

Figure 19.2. Thyristor valve: (a) modules components assembled into a valve and (b) valve symbol.

c

q =3 r =1 s =4 p=qxrxs p = 12 Y Y

(c)

(d)

Figure 19.3. Monopole converter bridges: Six-pulse valve group (a) converter bridge schematic and (b) six-pulse valve group converter symbol; Twelve-pulse valve group converter configuration with star-star and star-delta connected converter transformers: (c) converter schematic and (d) twelve-pulse valve group converter symbol.

Power Electronics

859

Chapter 19

As a result of the transformer configuration, the corresponding upper and lower transformer voltages are displaced by 30°, where VaYs-nY leads Va∆s-n∆ by π radians. The dc-link current Id is assumed constant because of the large smoothing inductor Ldc (linear and typically ½H). If source impedance is neglected, then the various circuit current waveforms are constituted from rectangular current blocks as shown in figure 19.7b. Each converter operates with the same firing delay angle α, with respect to the voltage references shown in figure 19.7b. Because the transformer primaries are in parallel, the input current is the sum of the appropriate two transformer phase currents, namely ia = iYa + i∆a for phase a. The Fourier series for each transformer primary phase current is obtained from analysis of the appropriate six-pulse converter current, for each converter 2 3 Id  1 1 1 1  iYa = (19.1)  cos θ − cos 5θ + cos 7θ − cos11θ + cos13θ .....  Nπ  5 7 11 13  and 2 3 Id  1 1 1 1  (19.2) i∆a =  cos θ + cos 5θ − cos 7θ − cos11θ + cos13θ .....  Nπ  5 7 11 13  Because of the symmetry of a three-phase system, no triplens exist in each input current. The total line current drawn is 4 3 Id  1 1 1  (19.3) ia = iYa + i∆a =  cos θ − cos11θ + cos13θ − cos 23θ .....  Nπ  11 13 23  The 12-pulse transformer/converter arrangement cancels harmonic components 6×(2n-1) ±1. The line current ia rms value is (1 +

1

3

)I

d

/ N and the rms fundamental is 2 6 I d / N π .

The ac line current harmonics occur at 12n±1. The valve side ac line current, shown as N×IYsa (or N×I∆sa) in figure 19.7b has an rms value of I d 2 / 3 , and once rectified, the valve unipolar current has an rms value of Id /√3. The more general equation are for the general case of asymmetrical converter firing when α1 ≠ α2. Assuming a turns ratio between the phase windings of the star connected primary and the star connected secondary is 2:1, and the turns ratio between the primary and the delta connected secondary is 2:√3, then i a = ½iYa + 3 2 i ∆a (19.4) Due to waveform symmetry, no dc component or even harmonics exist. The Fourier coefficients anY and bnY of iYa are 11π +α1  5π +α1  2π 6 1 1 6 anY = ∫ i a (t ) cos n ωt d ωt =  ∫ I d cos n ωt d ωt − ∫ I d cos n ωt d ωt  π 0 π π 7π +α1 (19.5)  6 +α1  6 4I d nπ n = 1, 3, 5, … sin sin n α1 =− nπ 3 11π +α1  5π +α1  2π 6 1 1 6 bnY = ∫ i a (t ) sin n ωt d ωt =  ∫ I d sin n ωt d ωt − ∫ I d sin n ωt d ωt  π 0 π π 7π +α1 (19.6) 6  6 +α1  =

4I d

nπ

sin

nπ 3

cos n α1

n = 1, 3, 5, …

The Fourier coefficients an∆ and bn∆ of the delta winding current i∆a are 2π 1 an ∆ = ∫ i a (t ) cos n ωt d ωt

π

bn ∆ =

1

π

2π

∫i

a

(19.7)

860

(t ) sin n ωt d ωt

0

π

=

2π +α 2  +α 2  π +α2 3 I 2I d 2 3 Id n ω t d ω t + sin sin n ωt d ωt + ∫ d sin n ωt d ωt  ∫ ∫  π 0 + α2 3 3 3 2π π +α +α2 3 2 3  

=

2I d 3n π

(19.8)

π 2π    cos n α2 + cos n ( 3 + α 2 ) − cos n ( 3 + α 2 ) − cos n (π + α 2 )    n = 1, 3, 5, …

The Fourier coefficients for the line current are then defined by an = ½anY + ½an ∆

bn = ½bnY + ½bn ∆

(19.9)

From which the input line current is defined by

i a (t ) =

∞

∑

n =1,2,3,…

2I an sin(n ωt + ϕn )

(19.10)

Output voltage The converter outputs are series connected, hence the output voltage is additive for each pole, namely Vdr = Vdr1 + Vdr2. The converter output voltage, with the constraint that both converters have a trigger delay of α, is V 6 2 Vdr = Vdr1 + Vdr 2 = VLL cos α = 2.70 LL cos α (19.11) N πN The peak output voltage occurs midway between the peak voltage from each converter, and for α = 0 V V Vdr = 2 2 LL cos 15° = 1.932 2 LL (19.12) πN πN

Each converter delivers six current blocks of magnitude Id, comprised of two ⅔π current blocks π radians apart in each converter arm. Since each converter output is the same but shifted by π radians, provided the two converters have equal delay angles, the resultant 12 current block per cycle results in the dc side voltage harmonics in Vdr being of the order 12n. If the two delay angles are controlled individually, the two outputs add but with harmonic components given by two six pulse converter, displaced by π, where  ∞ 3V  2 cos 2α1 1 1 sin ( 6n ωt + λ6n 1 )  Vdr 1 = max  cos α1 + ∑ + − 2 2 6 1 6 1 n n π  − +  ( ) ( ) n =1 6 1 6 1 n n − + ( ) ( )   (19.13)  ∞ 3V max  2 cos 2 α 1 1 2 1   cos α 2 + ∑ sin ( 6 ( n ωt − 6 π ) + λ6n 2 ) Vdr 1 = + − 2 2 π   n =1 ( 6n − 1) ( 6n + 1) ( 6n − 1) ( 6n + 1)   where  cos ( 6n + 1) α1 cos ( 6n − 1) α1  −  ( 6n + 1) ( 6n − 1)  −1  λ6n 1 = −n π + tan  sin ( 6n + 1) α1 sin ( 6n − 1) α1  −   ( 6n + 1) ( 6n − 1)  

λ6n 2 = −n π + tan

0

2π +α2  π3 +α2  3 Id 2I d   n ω t d ω t + n ω t d ω t cos cos ∫ ∫   3 3 π 2  0 + α2 +α 2  3 =   π α + π 2 I   d  + ∫ 3 cos n ωt d ωt   23π +α2  2I d  2π π  = − sin n α2 − sin n ( + α 2 ) + sin n ( + α 2 ) + sin n (π + α 2 ) 3n π  3 3 

HVDC

−1

 cos ( 6n + 1) α 2 cos ( 6n − 1) α 2  −  ( 6n + 1) ( 6n − 1)    sin ( 6n + 1) α 2 sin ( 6n − 1) α 2  −   ( 6n + 1) ( 6n − 1)  

When the two delays angles differ, α1 ≠ α2, the output voltage harmonics occur at order 6n.

Power Electronics

861

converter transformer

bridge converter

Converter unit 6 pulse

dc filters

Chapter 19

Pi = Vdi I d = 3 VLL I a1 cos αi = 3 VLL ×

dc bus surge capacitor

= Qi / tan αi

Ldc

hv dc

½H linear

Metallic return transfer breaker

ac filters Midpoint dc bus arrestor

hv ac

dc bus arrestor

Y Y

Neutral bus Neutral bus arrestor surge capacitor

earth line and electrode earth return transfer breaker

Y ∆ ½H linear

Converter unit 12 pulse

hv dc

Ldc

dc reactor and arrestor

HVDC

dc bus arrestor

dc line arrestor

Figure 19.4. Thyristor HVDC substation.

19.4.1 Rectifier mode Figure 19.7b shows that the angle between the input ac voltage and its fundamental current Ia1 is determine by and equals, the phase delay angle αr. The phasor diagram for rectification is shown in figure 19.8a. For a constant link current Id, the fundamental ac input power factor is cos αr while the input reactive power is given by Qr = 3 VLL I a1 sin α r = Pr tan α r (19.14) I 2 6 = 3 VLL × I d × sin α r = 2.7 × VLL × d × sin α r Nπ N The rms of the fundamental line current Ia1 is 2 6 I d / N π . The real power transfer, which is the rectifier output power, is given by Pr = Vdr I d = 3 VLL I a1 cos α r = Qr / tan α r (19.15) I 2 6 = 3 VLL × I d × cos α r = 2.7 × VLL × d × cos α r Nπ N

I 2 6 I d × cos αi = 2.7 × VLL × d × cos α i Nπ N

862

(19.17)

To maximize the inverted power flow and minimize the reactive power, the delay angle αi should be large (→ π). From equation (19.17), to minimise the link I2R loss, Id should be minimised (maximise dc link voltage) and the delay angle αi should be large (→ π). Thus the inversion voltage should be as large as possible, avoiding commutation failure. Then the maximum αi decreases as current increases since thyristor commutation time increases with current (and temperature). P-Q operation of the twelve pulse series connected converter

The theory of controlled active and reactive power operation of a series connected 12-pulse converter assumes an ideal input transformer, negligible source impedance, and a constant current from the converter dc output bus. The output voltage contribution due to each constituent 6-pulse converter is given by 3V Vdri = max cos αi (19.18)

π

where Vmax is the peak line voltage of the voltage applied to each converter, αi is the firing angle of the constituent converter, and i represents either converter 1 or 2. By multiplying (19.18) by the dc load current Idc, the active power is given by Qi = Pmax sin αi (19.19) where 3 Pmax = I oV max

π

which represents the maximum power delivered from each converter at αi = 0. Similarly, the reactive power absorbed by the converter is given by Qi = Pmax sin αi (19.20) The active power Pd and reactive power Qd, drawn by the 12-pulse converter are the sum of the contribution made by each converter, namely Pd = Pmax (cos α1 + cos α 2 ) (19.21) Qd = Pmax (sin α1 + sin α2 ) From these two equations, the 12-pulse converter draws active power of 2Pmax and zero reactive power at α1 = α2 = 0. Similarly, at α1 = α2 = ½π, the converter draws reactive power of 2Pmax and zero active power. Therefore, 2Pmax is the base power, 1 pu, and the equations in (19.21) become Ppu = ½(cos α1 + cos α2 ) (19.22) Q pu = ½(sin α1 + sin α 2 ) The variation of Ppu and Qpu with simultaneous variation of α1 and α2 is shown in the three-dimensional plots figure 19.5.

To maximize the power flow and minimize the reactive power, the delay angle αr should be small. From equation (19.15), to minimise the link I2R loss, both Id and the delay angle αr should be small. That is, from equation (19.11), the rectifier output voltage should be maximised. A low converter firing angle minimise the reactive power, reduce snubber losses, and reduces the harmonic content. 19.4.2 Inverter mode The same basic rectifier mode equations hold in the inversion mode except that αi > ½π. Operational waveforms and the phasor diagram for this mode are shown in figure 19.8b. The reactive power is I 2 6 Qi = 3 VLL I a1 sin αi = 3 VLL × I d × sin αi = 2.7 × VLL × d × sin α i (19.16) Nπ N = Pi tan αi and the real power transfer, which is inverted into the ac system is given by

Figure 19.5. Effects of varying of α1 and α2 on: (a) active power and (b) reactive power.

Power Electronics

863

Chapter 19

The 12-pulse converter may operate with symmetrical firing of each 6-pulse converter, where α1 = α2 or with asymmetrical firing where α1 ≠ α2 (or a combination of both). Different power loci can be realized by different combinations of firing angles (α1 and α2). Three power loci are shown in part ‘a’ of figure 19.6. The symmetrical firing P-Q locus is represented by the outer semicircle with centre ‘0’ and radius of 1 pu, and is obtained by the symmetrical firing of α1 and α2 from 0 to π using the parts of equation (19.22). All points in the P-Q plane within the outer semicircle can be achieved by unique combinations of α1 and α2. The figure also shows power loci for asymmetrical firing which are represented by the circumference of the two inner semicircles with radii of 0.5 pu. These are obtained by varying α1 from 0 to π while α2 is held at ‘0’ in the case of rectification and by varying α2 from 0 to π while α1 is held at π in the case of inversion. Part ‘a’ also shows the power locus for constant VAr operation indicated by the line parallel to the Ppu axis. With asymmetrical firing the maximum reactive power is decreased to one-half the case for symmetrical firing. Part ‘b’ of figure 19.6 shows the variation of input current THD with varied delay angles and reflects the adverse effect of asymmetrical firing on the THD.

HVDC

864 Ldc +

AC side a

DC side

ia

iYa

id(t) = Id = constant

+

+

iYsa

aYs

q =3 r =1 s =4 p=qxrxs p = 12

N:1 Vdr1

-

ia

cYs

b

nY bYs Id Y Y

c

a

+

Y Y

i∆a

a∆s

∆ Y

α1=α2

Vdr

ia = iYa + i∆a

√3N : 1

∆Y n∆

Vdr2

c∆s

b

Vdr

ia ib ic

i∆sa

b∆s (a) c

-

-

Vdr = Vdr1 + Vdr2

(a)

(b)

Figure 19.6: Twelve-pulse fully-controlled converter: (a) power loci and (b) input current THD.

The symmetrical firing power locus is associated with the best THD and the worst supply current power factor. On the other hand, asymmetrical firing decreases the reactive power flowing in the system, which improves the input power factor but deteriorates the input current THD, which limits the power factor improvement. As a result, asymmetrical firing of the 12-pulse converter offers the possibility of a smaller reactive power compensator for power factor compensation, at the expense increased input current harmonics.

Vdr2 Vdr1 VcYs-nY

-30°

o°

1 (cos α 1 + 1) , α 2 = 0 2

o°

VaYs-nY

αr

αr

N×iYa

Id

+

Ia 0

1 (cos α1 + cos α 2 ) , α 1 = α 2 2 1 (cos α 2 − 1) , α 1 = π 2

30°

180°

90°

330° -

Ia

150°

0° 30°

-Id N×i∆a − −

2I d

Id

3

3

N×ia −

( − 1 3 − 1) I

d

1

3

(b)

Id

( − 2 3 − 1) I

d

Ia1 fundamental of Ia

Figure 19.7X: Power locus of 6-pulse and 12-pulse converters and per unit output voltage. Figure 19.7. Twelve-pulse valve group converter configuration with star-star and star-delta connected converter transformers: (a) converter schematic and (b) twelve-pulse valve group waveforms.

Power Electronics

865

Chapter 19

P Q

q =3 r =1 s =4 p=qxrxs p = 12

Id Y Y

+ = Vdr1+Vdr2 Vdr2 ∆Y

Q Id

Rectification and inversion modes of converter operation and the line (or natural) commutation process of the three-phase fully-controlled thyristor converter have been considered in chapter 12.4 for rectification, with overlap in 12.5, and 12.6 for inversion with overlap. One converter operates as a rectifier (power flow from ac to dc) and the other dc link converter operates as an inverter (power flow from dc to ac). Either terminal converter can operate as an inverter or rectifier, since the delay angle determines the mode (voltage) of operation. The power flow between the two ac systems connected to the HVDC link is controlled by controlling the delay angle of each converter. Current only flows in one direction in the dc link, from the rectifier to the inverter. A simple system model is shown figure 19.9 where the link dc resistance is represented by Rdc and source reactance, hence overlap effects have been neglected. Let the transformer turns ratio factor N equal 1. The dc current Id is V + Vdi (19.23) I d = dr Rdc where 3 Vdr = 2 V LL cos αr for 0 ≤ αr ≤ ½π π (19.24) 3 2 VLL cos αi for ½π ≤ αi ≤ π Vdi =

-

ia = iYa + i∆a

Vdr

ia ib ic

19.5

Vdr

Vdr1

Vdr1

ia = iYa + i∆a

+ -

ia ib ic

-

= Vdr1+Vdr2

Vdr2

+

∆Y

Vdr2 ½Vdr Vdr1

Twelve-pulse ac line frequency converter operation control

π

VcYs-nY VcYs-nY

Id -30° o°

αi

+

o° αr

o°

αi

Vdr

Vdr1 ½Vdr -30° o° αr

N×iYa Ia

0 30°

180°

90°

+

Ia

300°

-

Ia

150°

-

360°

-Id

-Id

N×i∆a

Ia

0 30°

90°

Id

3

−

2Id

−

Id

−

( − 2 3 − 1) I

1

I

3 d

3

−

3

−

1

(a)

+ inversion αi > 90°

Vd

2I d

Vdi 3

Operating point

Ia1

N×ia

( − 1 3 − 1) I

Vdi

Rectification αr < 90°

180° 150°

Ia1

N×ia

-

Id

N×i∆a −

P

-

Vdr2

Id

+

Rdc

VaYs-nY

VaYs-nY

N×iYa

866

P

Y Y

+

HVDC

maximum αi decreases with increased Id

I

3 d

( − 1 3 − 1) I

d

d

d

( − 2 3 − 1) I

d

I dref α Vdr

(b)

Id

Figure 19.9. Basic HVDC transmission system: (a) circuit diagram and (b) load line characteristics. o

ℜ ( I a1 )

ℜ ( I a1 )

VaYs-nY

αr

VaYs-nY

o

The rectifier output power is

αi

ℑ ( I a1 )

ℑ ( I a1 ) Ia1 (a)

Ia1

Pr = Vdr I d

(19.25)

Pi = Vdi I d

(19.26)

Pr = Vdr I d = Vdi I d + I d2Rdc = Pi + I d2Rdc

(19.27)

while the power supplied to the inverter is where

(b)

Figure 19.8. Twelve-pulse valve group converter configuration with star-star and star-delta connected converter transformers operating in: (a) a rectifying mode and (b) an inverting mode.

If transformer per phase leakage inductance Ls, referred to the converter side, is accounted for, then the resultant overlap at commutation reduces the output voltage for each six-pulse converter. 3ω Ls  6 3 (19.28) Vdr = 2 ×  2 VLL cos α r − I = × 2 VLL cos α r − ω Ls I d π d  π π

(

)

867

Power Electronics

Both the rectifier and inverter dc output voltages can be compensated for leakage reactance commutation overlap. Remember the overlap voltage component is not a loss element in the resistor sense. It represents a ‘lossless’ loss of voltage which increases with current. If the link voltage is controlled by the inverter and the dc current controlled by the rectifier, then the load line characteristic in figure 19.9b results. The inverter voltage is kept slightly below the rectifier voltage. As the load current increases, the inverter terminal voltage is reduced. This is because the time to safely commutate the inverter thyristors increases with current, hence αi must decrease, as shown by the droop in the output characteristics in figure 19.9b. The more detailed practical approach to HVDC power transport control is considered in section 19.5.1.

Chapter 19

HVDC droop due to link resistance

Vdr

Inverter Under steady-state conditions, the inverter controls the dc voltage by one of two methods. • The inverter maintains a constant delay angle αi > 90°, or extinction angle γ, where γ = π - αi, This constant angle maintenance causes the dc voltage Vd to droop with increasing dc ∨ current Id, as shown in the minimum constant extinction angle γ characteristic in figure 19.10b and labelled A-B-C-D in figure 19.10c. The weaker the ac system at the inverter, the steeper the droop characteristic. • Alternatively, the inverter may operate in a dc voltage controlling mode which is the constant Vd characteristic shown dashed in figure 19.10b and labelled B-H-E in figure 19.10c. To achieve this, the extinction angle γ must increase beyond its minimum value characterised in figure ∨ 19.10b as γ . Rectifier If the inverter is operated in either a minimum constant γ or constant Vd mode, then the rectifier is used to control the dc link current Id. This is achievable provided the delay angle αr is not at its minimum limit. The steady-state constant current characteristic of the rectifier is shown in figure 19.10a as the vertical section of the characteristic S-T and is labelled S-C-H-T in figure 19.10c. The rectifier delay angle is increased toward αr = 90° if the link current attempts to increase beyond the reference level I dref . During an attempted short circuit fault, the rectifier delay angle reaches 90° which sets the rectifier output voltage to zero, as shown by equation (19.24), and controls the fault current to I dref as shown by trajectory S-T in figure 19.10a.

The operating point of the HVDC system is where the rectifier characteristic intersects the inverter characteristics, either at point C or point H on figure 19.10c, depending on which of the two inverter control methods is being employed. The operating point is tuned over a period of tens of seconds by adjusting the line-side tap changers of the converter transformers. The inverter controls the dc-link voltage as follows. • The inverter establishes the desired dc voltage Vd by tap changer adjustment, if it is operated in a constant minimum γ mode. • If the inverter is operated in a constant Vd mode, the tap changer ∨is adjusted to produce constant Vd with an extinction angle slightly larger than the minimum γ . The ac-side tap changers on the rectifier end transformers are adjusted so that the delay angle α is small but with a 5° working range, whilst maintain the constant current I dref. If the inverter is constant dc voltage operated at the operating point H, and if the dc current I dref is increased so that the operating point H moves towards A, the inverter control mode reverts to constant extinction angle γ control when operating in the droop region A-B. The voltage Vd droops to less than the desired value, so the inverter end transformer tap changer progressively boosts the dc-side voltage until dc voltage control recommences, in region B-C-D.

Vdi

I dref

S minimum rectifier delay angle characteristic

∨

γ

constant current operation °

D

Vdr

B

constant Id current operation°

Id

minimum rectifier delay angle characteristic S D C E

RECTIFIER

Vdi

VDCDL

Vdr

Imargin X

Operating point B

(a)

(b)

(c)

(d)

F

I dref

D

Vdr

A R

minimum extinction angle characteristic droop

E

S

Operating point

Vdi

INVERTER

∨

γ T

II

Id

I I < I dref

Vd

H

Y

αi =γ= 90° Vdi = 0

F

I dref

γ greater than minimum extinction angle

Vdi

T

R

A

E

αr = 90° Vdr = 0

Vd

INVERTER

minimum extinction angle characteristic droop

R

19.5.1 Control and protection

HVDC transmission systems must operate under tightly controlled conditions. Dc-link current and the two terminal voltages are precisely controlled to affect the desired power transfer. Accurate system quantities measurement are required, which include at each converter bridge, the dc-link current, the dcside voltages, and the delay angle α for each converter/inverter. Two terminal dc transmission systems have a preferred control mode during normal operation.

RECTIFIER

868

INVERTER

RECTIFIER

Imargin F

Id

II

I dref

Id

Figure 19.10. Steady-state Vd - Id characteristics for a two terminal HVDC system.

Not all HVDC transmission systems use constant dc voltage control, which is the horizontal characteristic B-H-E in figure 19.10c. Instead, the tap changer in conjunction with the constant extinction angle γ control characteristic A-B-C-D in figure 19.10c, provides dc voltage control. Current margin The rectifier and inverter controllers both receive the dc current demand I dref but the inverter current demand is decreased by an amount termed the current margin Imargin, as shown in Figure 19.10c. This current margin is usually a constant magnitude of about 10% of rated current. The inverter current controller endeavours to control the dc link current to II = I dref – Imargin but the rectifier current controller dominates and maintains the dc current at I dref. In steady-state the rectifier controller overrides the inverter controller which is not able maintain a dc current I dref - Imargin. The inverter current controller only becomes active when the rectifier current controller has reduced its delay angle αr to the minimum limit. This rectifier minimum delay angle limit is characterised by R-S in figure 19.10c. Control characteristic performance Variations in the ac voltages change the control operating point of the system as follows. i. When the rectifier side ac voltage decreases and/or the inverter side ac voltage increases, then the transformer tap adjustment mechanisms on both the rectifier and inverter transformers should attempt to remedy this ac voltage regulation problem. If the disturbance is large enough, the new stable operating point is shown in figure 19.10d. The R-S characteristic falls below points D or E, the operating point will shift from point H to somewhere on the vertical characteristic D-E-F where it is intersected by the lowered minimum αr R-S characteristic as shown in figure 19.10d. The inverter converts to current control, controlling the dc current Id to the value II = I dref - Imargin, approximately 10% of rated current and the rectifier effectively controls the dc voltage provided it is operating at its minimum delay angle characteristic R-S. The dc power flow is relatively unaffected and safely returns to the normal operating condition shown in figure 19.10c, once the ac disturbances have subsided. ii. If the rectifier ac voltage increases, the reference current, which is set by the rectifier, is unaffected. Since the link voltage is set by the inverter, any increase in rectifier ac voltage does not affect the power flow. This can be seen in figure 19.10c where increasing the rectifier characteristic R-S does not affect the intersection of the operating point C, whence power flow is unaffected by an increase in the rectifier ac-side voltage.

Power Electronics

869

HVDC

Chapter 19

iii. If the inverter side ac voltage is decreased, the link voltage decreases proportionally, but the current is unaffected because it is set by the rectifier. The power flow is therefore decreased in line with the inverter ac voltage decrease. This can be seen in figure 19.10c where the inverter side ac voltage decrease will lower the inverter characteristic A-B-C-D. The operating point C, the operating voltage, decreases but the current is unaffected. Thus the power transferred is decreased in-line with the inverter ac-side voltage. vi. Worse case conditions are a dc-link short circuit. As seen in figure 19.10a, the rectifier maximum current is I dref, while figure 19.10b shows that the maximum inverter current is II. The maximum fault current is therefore limited to the operational current margin Imargin. As seen in figures 19.10a and 19.10b, the control angle of both converters moves to 90°, which produces 0V converter output voltages, as shown by equation (19.24). Hence the power associated with any short circuit fault is low, unlike short circuit faults in ac transmission systems. Voltage dependant current demand limit (VDCDL) If the ac voltages sag significantly because of weak ac systems, it may not be possible to maintain full load current. In such a case the dc-link voltage is decreased, and the controller characteristics are dictated by the trajectories X and Y in figure 19.10c. A controller which reduces the maximum current demand in such conditions, is termed a voltage dependant current demand limiter, or VDCDL. The current is not reduced to zero so that recovery response is faster once the dc-link voltage has sufficiently recovered. Power flow reversal The controllers can be designed such that the transition from the rectifier controlling current to the inverter controlling current is automatic and smooth. That is, seamless automatic power flow reversal is achieved by interchanging the inverter and rectifier functions, as seen in figure 19.11. This is realised by appropriate control of the delay angles, hence terminal polarities, but the dc link current direction does not reverse. Such a bi-directional power flow requirement may be necessary when two ac systems are required to bi-directionally interchange power. The rectifier delay angle is progressively increased while the inverter delay angle is decreased, such that the rectifier and inverter voltage difference is control to be virtually constant. This is achieved if αr + αi ≈ 180° is maintained.

19.6

870

Filtering and power factor correction

As shown in figure 19.4, both ac and dc side filtering is used to reduce radiated EMC on the dc link and conducted EMC on the ac side which causes power losses and interference. On the dc-side, the large link inductance at each converter (typically between 0.2H and 0.5H) is supplemented with LC filters, tuned to eliminate selected 12n current harmonics in a 12-pulse system. A filter is notch tuned to eliminate (shunt) one specific harmonic, usually the most dominate 12th. At 50/60Hz, these filters are capacitive thus provide reactive power absorbed by the converters. Harmonics occur at 12n±1 on the ac-side. Again, tuned LC filters eliminate (shunt) specific low order harmonics and a general high pass shunt filter is used for components above the 11th and 13th. Generally, higher pulse order (>12) transformer/converter arrangements are not attractive in HVDC because of the difficulties in producing high-voltage transformers (auto-transformers tend to be used). Additional to the VAr compensation provided by the ac harmonic filters, pure capacitance may also be used. In order to avoid overcompensation voltage regulation problems which can occur at low power transmission levels, the extra capacitance tends to be switched in-circuit as needed. The main transformers may be provided with ac-side voltage taps to adjust the secondary voltage, as considered in section 19.5.1. The taps are switched automatically by motorised tap-changing drives, which only operate when large voltage changes occur for prolonged periods of time. If the transformers have only Y-Y winding configurations, they may also have a low-voltage delta tertiary winding for VAr compensation, provide ancillary supplies, and suppression of transformer core triplen harmonic fluxes. Example 19.1: Basic six-pulse converter based hvdc transmission

The basic six-pulse converter dc transmission system represented by figure 19.12 connects a 230kV ac rms, 50Hz system to a 220kV, 60Hz system. The 6-pulse converters at each transmission line end are interface by a ∆ac-Ydc transformers of turns ratio √3:2, as shown, such that the transformer dc-side line voltage is double the ac side line voltage. The power transmission is 500MW to the inverter which is maintained at a dc voltage level of 500kV. The total dc-line resistance is 8Ω.

+

-

-

Determine i. The inverter delay angle, αi. ii. The dc-link current, hence rectifier output voltage, thence rectifier delay angle, αr. iii. The rectifier input power and VAr, and inverter VAr, thence system efficiency.

Vdr

Vdi

Vdr

Vdi

Solution

-

-

+

+

Because of the transformer turns ratio, the transformer dc-side ac voltages are double the ac-side voltages.

Id

+

Id

P

Vdr > Vdi Rectification α < 90°

P

Vdr < Vdi inversion α > 90°

inversion α > 90°

Rectification α < 90°

i.

π

Figure 19.11. Power reversal in HVDC systems by voltage polarity reversal, not current reversal.

500kV =

3

π

2 2 × 220kV × cos αi

that is αi = 147.3°

19.5.2 HVDC Control objectives

The fundamental objectives of a CSI-based HVDC control system are as follows: • to control basic system quantities such as dc line current, dc voltage, and transmitted power accurately and with sufficient speed of response; • to maintain adequate commutation margin in inverter operation so that the valves can recover their forward blocking capability after conduction before their voltage polarity reverses; • to control higher-level quantities such as frequency in isolated mode or provide power oscillation damping to help stabilize the ac network; • to compensate for loss of a pole, a generator, or an ac transmission circuit by rapid readjustment of power; • to ensure stable operation with reliable commutation in the presence of system disturbances; • to minimize system losses and converter reactive power consumption; and • to ensure proper operation with fast and stable recovery from ac system faults and disturbances.

The inverter delay angle is derived from equation (19.24) 3 2 VLL cos αi Vdi =

ii.

From Pi = Vdi × Id, the link current is

Id =

500 × 10 6 W 500 × 10 3 V

= 1000 A

The rectifier output voltage is given by equation (19.23), rearranged Vdr = −Vdi + I d Rdc = − -500kV + 1000A×1Ω = 508kV The rectifier delay angle is derived from equation (19.24) 3 Vdr = 2 VLL cos αi

π

508kV =

3

π

yields αr = 35°

2 × 2 × 230kV × cos αr

Power Electronics

871

iii. The input power is the output plus dc-link resistive losses, that is Pr = I d2 × Rdc + Pi

From equation (19.23), the rectifier voltage is

V dr = V di + Rdc I d

= 10002×8Ω + 500MW = 508MW The input VAr from the ac side is Qr = Pr tan αr

= 500kV + 8Ω × 1000A = 508kV and the necessary transformer tap ratio is derive from

= 508MW × tan35° = 355.7MVAr Similarly, the inverter VAr into the ac side (indicated by the negative sign) is Qi = Pi tan αir

3ω Ls  3 Vdr = 2 ×  2 ar VLL cos α r − I π d  π 3 × 2 × π × 50Hz × 1 × 10−3 H 3  508 × 103 V = 2 ×  2 ar 230 × 103 V cos 30° − 1000A  π π  which gives a transformer tap ratio at the rectifier end of ar = 0. 945.

= 500MW × tan148° = -312.4MVAr

The efficiency is

η=

Pi Po

=

+

230kV 50Hz

VRdc = 8kV

+

220kV 60Hz

Vdi = 500kV

8MW

Rectification

αr = 35°

inversion

αi = 148°

500MW -312MVAr

♣ The following example is based on example 19.1. Example 19.2: 12-pulse hvdc transmission

The dc transmission line represented by figure 19.9 connects a 230kV ac rms, 50Hz system to a 220kV, 60Hz system. The 12-pulse bipolar converters at each transmission line end are interface by a Y-Y transformer of turns ratio 1:1 and a ∆-Y transformer of turns ratio 1:√3, each with a converter side inductance of 1mH. The rectifier delay angle is α = 30° for 500MW power transmission and the inverter advance angle is α = 160° (in order to avoid any reactive power increase), which maintains the dc voltage level at 500kV at the inverter end. The total line resistance is 8Ω and the dc link smoothing inductance is large enough to initially consider the dc current to be ripple free. Determine i. The transformer tap ratios at each end, the dc link efficiency, I2R losses, and both terminal VAr ii. If the rectifier tap ratio of 0.866 results in the transmission current limit giving a power of 600MW, find the delay angle and line efficiency for 500kV at the inverter. iii. The value of the dc link inductance Ldc such that the link peak to peak current is 0.1pu the average load current at full load (1200A), assuming the normalised magnitude of the dc side harmonic V12 is 0.15pu maximum (with respect to the 50Hz supply). Solution

From Pi = Vdi × Id, the link current is

Id =

500 × 10 6 W

508kV

× 100 = 98.4%

The I2R losses are 1000A2×8Ω = 8MW or (508-500)2/8 Ω, dissipated, distributed along the line. The rectifier reactive power is given by equation (19.14), that is Q r = Pr tan αr

Y:∆ 2:√3

-

508MW

500kV

= 440kV

Vdr = 508kV ∆:Y √3:2

i.

VI Pi × 100 = i d × 100 Pr Vr I d

η=

Id = 1kA

460kV

356MVAr

The link efficiency is

500MW ×100 = 98.43% 508MW

Figure 19.12. HVDC Example 19.1.

HVDC

Chapter 19

= 1000 A 500 × 10 3 V The inverter voltage, accounting for the transformer tapping is given by an equation similar to equation (19.28), that is 3ω Ls  3 Vdi = 2 ×  2 ai VLL cos α r − I π d  π 3 × 2 × π × 60Hz × 1× 10−3 H 3  500 × 103 V = 2 ×  2 ai 220 × 103 V cos (180° − 160° ) − 1000A  π π  which gives a transformer tap ratio at the inverter end of ai = 0.896.

= (500MW + 1000A 2×8Ω)×tan30° = 293.3MVAr This is 293.3MVAr from to rectifier ac side. The inverter reactive power is given by equation (19.16), that is Qi = Pi tan αi = 500MW × tan160° = - 182MVAr This is 182MVAr to the ac side of the inverter.

ii.

At 500kV and 600MW:

Id =

Pi 600MW = = 1200A 500kV Vdi

Accounting for the link resistive voltage drop

V dr = V di + Rdc I d = 500kV + 8Ω × 1200A = 509.6kV

The efficiency is

η=

VI Pi × 100 = i d × 100 Pr Vr I d

500kV × 100 = 98.1% 509.6kV The necessary rectifier angle, accounting for transformer reactive inductance, is 3ωLs 3  2 ai VLL cos αr − Vdr = 2 ×  I π d  π

=

3  3 × 2 × π × 50Hz × 1 × 10−3 H 509.6 × 103 V = 2 ×  2 × 0.866 × 230 × 103 V cos αr − × 1200A  π π   which gives a rectifier delay angle of αr = 18.5°.

iii. The maximum link voltage from the 50Hz rectifier, accounting for leakage at maximum current is 3ωLs 3  Vdr = 2 ×  I 2 VLL cos αr − π d  π 3  3 × 2π 50Hz × 1 × 10−3 H 2 230kV × cos 0° − 1200A  = 2× π π  = 620.5 kV

872

Power Electronics

873

The magnitude of the 600Hz component (12×50Hz) is 15% of 620.5kV, namely 93.1kV, which produces a ripple current of 10% of rated current, 1200A, namely 120A. Thus from v = Ldi/dt

Ldc = v 12

∆t 12 ∆i 12

= 93.1kV × Figure 19.13. HVDC Example 19.2.

1 12 × 50Hz × 120A

= 1.3H

Id = 1000A

Y:Y 1:1

+

230kV 50Hz

VRdc = 8kV

Vdr = 508kV

∆:Y √3:1

Y:Y 1:1

+

220kV 60Hz

Vdi = 500kV

-

Y:∆ 1:√3

-

508MW Rectification

293MVAr

19.7

αr = 30°

500MW

8MW

inversion

-182MVAr

αi = 160°

♣

VSC-Based HVDC

Voltage source converter-based (VSC) dc-transmission consists of a bipolar two-wire HVDC system with self commutatable converters connected pole-to-pole, as shown in figure 19.14. DC capacitors are used at each VSC dc-side to provide a stiff dc voltage source. The dc capacitors are grounded at their electrical centre point to establish the earth reference potential for filtering and the transmission system. The VSC is effectively mid-point grounded and DC filters and a zero-sequence blocking inductor are used to mitigate interference on any metallic communication circuits adjacent to the DC cables. There is no earth return operation. The converters are coupled to the ac system through ac phase inductors and power transformers, with harmonic filters located between the phase inductor and the transformer. The AC filters are tuned to multiples of the switching frequency, as shown in figure 19.18. This arrangement minimizes harmonic currents and avoids dc voltage stresses in the transformer, which allows use of a standard AC power transformer for matching the 50/60Hz AC network voltage to the converter AC voltage necessary to produce the desired DC transmission voltage. Converter valves AC transformer

DC capacitors

DC-link cables

HVDC

Chapter 19

DC capacitors

The IGBT valves used in VSC converters are comprised of series-connected IGBT cells. Present technology uses 2.5kV igbt die parallel connected on a common electrically-conducting substrate in 2500A sub-modules, with 30 series connected sub-modules in a string cell. Strings are then series connected to produce the required link valve voltage requirement. The IGBT switching frequency is limited to about 2 kHz. The valves are cooled with circulating water and water to air heat exchangers. The structure is constructed to shield electromagnetic interference (EMI) radiation. 19.7.1 VSC-Based HVDC control Power flow between the VSC and ac network can be controlled by changing the phase angle of the converter ac voltage VS with respect to the filter bus ac voltage VT, whereas the reactive power can be controlled by changing the magnitude of the fundamental component of the converter ac voltage VT with respect to the filter bus ac voltage VS. By independently controlling these two aspects of the converter voltage, operation in all four quadrants is possible. This means that the converter can be operated in the middle of its reactive power range near unity power factor to maintain dynamic reactive power reserve for contingency voltage support similar to a static VAr compensator. This also means that the real power transfer can be changed rapidly without altering the reactive power exchange with the ac network or waiting for switching of shunt compensation.

Reactive power control can be used for dynamic voltage regulation to support the ac interconnection, by synthesising a balanced set of three phase voltages. Black start (restoring system operation without an external energy source) capability is also a feature. Independent control of the VSC ac voltage magnitude and phase relative to the system voltage decouples the active and reactive power control loops for HVDC system regulation. The active power control loop can be set to control either the active power (dc-link current) or the dc-side voltage. In a dc link, one station is selected to control the active power while the other controls the dc-side voltage. The reactive power control loop controls either the reactive power or the ac-side voltage. Either of these two modes can be selected independently at either end of the dc link. Figure 19.14 shows the characteristic ac voltage phasors including the controlled variables Vdc, Id, Q, and VL. 19.7.2 Power control concept dc-link power The dc-link power flow concepts are not complicated by ac phasor considerations. No reactive power is involved with dc, only the real power flows. Consider the HVDC configuration depicted in figure 19.15 involving converter #1 and converter #2.

Converter valves

AC phase inductors

Idc

Rdc

AC transformer

AC phase inductors

874

VL1

XC1 I C1

IC2 XC2

Vdc2

Vdc1

IL1 Vac 1

IL2

Vac 2

VC1

VC2

Iac 2

Iac 1 Vdc-1

AC harmonic filters

Vdc-2

(a)

AC harmonic filters

2

1 Vac-ref2

Vac-ref1

PWM current control

{

ℜ −VC 1 I L 1 + VC 2 I L 2

Vdc-ref2

Vdc-ref1 ac voltage control

VL2

dc voltage control Pref 1 Qref 1

dc voltage control Pref 2 Qref 2

PWM

ac voltage control

VL1-n

*

*

}=I

2

dc

R dc

jXR1

jXR2

IC1

IC2

VC1-n

VC2-n

VL2-n (b)

current control

Figure 19.14. VSC HVDC transmission, using three-level (NPC) voltage source inverters.

Figure 19.15. VSC HVDC transmission dc-side, using two-level voltage source inverters.

Power Electronics

875

HVDC

Chapter 19

If one converter #1 produces an ac voltage represented by VC 1 = VC 1 ( cos δ1 + j cos δ1 )

Rectifier

(19.29)

= VC 1 ∠δ1

while the other converter #2 is represented by the voltage source VC 2 = VC 2 ( cos δ 2 + j cos δ 2 )

Inverter

VX

876 Reactive Power Consumed generated

VX

VX VX

(19.30)

= VC 2 ∠δ 2

Then if the power transmitted equals the power received, then ℜ {−VC 1I L*1 +VC 2I L*2 } = 0

VT

(19.31)

VS

VS

VT VS

δ

δ

VT

VS

VT

If the dc link resistive losses are incorporated equations (19.31) becomes IR

(19.32)

IR

ac-side powers The fundamental base apparent power ST at the filter bus between the converter reactor and the AC filter is defined as follows (see figure 19.16):

S T = PT + jQT = 3 ×VT × I R

jXR

(19.33)

VS-n

VT-n

The typical P-Q diagram, which is valid within the whole steady-state AC network voltage, is shown in the figure 19.18. This figure illustrates the grid real power, P, and reactive power, Q, capability of the HVDC VSC converter terminal, measured at the interconnection point, as a function of ac system voltage.

Power transformer

Vdc

VL-n

IR

XR

IL

IT

Icable limit

ITq

IT

VS

VS-n δ

ITp

VT-n

VT

VL Power transformer

Harmonic filter

VXR {Re}

IL

(a)

+½

1:N dc capacitance

VL

Figure 19.16. VSC HVDC transmission ac-side.

Harmonic filter

The active and reactive power components on the grid-side are defined as (see section 20.3 of ac power transmission): V ×V S × sin δ V ×V S × sin δ P = T = T

ωL

QT = VT

XR

V S × cos δ −VT XR

Rectifier

Vac

0.9 pu +½

Q(φ)

-½

pu

Q(φ)

Vac

pu

1.0 pu -½

Vac

1.1 pu

Idc limit

Q consumption inductive

1pu

reactive power

Inverter

Q generation capacitive

(19.34)

where: δ = phase angle between the filtered voltage VT and the converter output voltage VS L = inductance of the converter ac line inductance Changing the phase angle δ controls the active power flow P between the converter and the filter bus and consequently between the converter and the AC network. As shown in figure 19.17a, for active power flows • If the VS phase-lags VT, active power P flows from the AC to the DC side (rectifier). • If the VS phase-leads VT, the active power P flows from the DC to the AC side (inverter). Changing the amplitude difference between the filter voltage VT, and the converter voltage VS controls the reactive power flow between the converter and the AC network. As shown in figure 19.17b, for reactive power flows • If VT > VS, there is reactive power consumed from the ac network. • If VS > VT, there is reactive power generated into the ac network.

Vdc limit

Vdc

(c) (b)

pu 1pu

IGBT/diode valve Phase reactor XR

P(φ)

1pu

Idc

1:N {Im}

IR

Reactive power flow Q

(b)

With the PWM (Pulse-Width-Modulation, see Section 15.2.3) controlled VSC it is possible to create any phase angle and voltage amplitude (within limits set by the dc-link voltage magnitude) by changing the PWM modulation depth and the relative phase displacement respectively, by using phase-locked-loop grid synchronised displacement. This allows independent control of the active and reactive power.

Idc

VXR

(a)

Figure 19.17. Active and reactive power phasor diagrams.

Transformer IT

IR

Active power flow P

Active power

ℜ {−VC 1I L*1 +VC 2I L*2 } = I dc2 Rdc

Figure 19.18. P-Q active and reactive power control locus, showing varying voltage limits.

The 1st and 2nd quadrants represent rectification and the 3rd and 4th inversion. A positive Q indicates delivery of reactive power to the AC network. Because the dc-link decouples the two converters, reactive power can be controlled independently at each station. There are dc-link voltage (Q generation restrictions) and current (inverter - igbt - power) limitations that have been taken into account in this typical P-Q diagram. Depending on the cable design, the cable dc current maximum may restrict the rectifier power limit. There is also a steady state minimum dc-voltage level limit, which may prevent continuous absorption of large amounts of reactive power. The capacitive reactive power capability increases with decreasing voltage when it is needed most. Similarly, the inductive reactive power capability increases with increasing network voltage when it is needed most. For a given ac system voltage the converter can be operated at any point within its respective ‘circle’. At low ac voltages the VA limit dominates. For high ac voltages, the dc-voltage limit is restrictive but it is not desirable to inject reactive power when ac voltage already is high.

Power Electronics

877

19.8

HVDC

Chapter 19

878

HVDC Components

Ω

C1

i. Power transformer Because of the use of the converter ac inductors and the use of VSC PWM, the current in the transformer windings contains minimal harmonics and is not exposed to any DC voltage. The transformer is a 50/60Hz single or three phase power transformer, with taps and a tap-changer. The secondary voltage, the filter bus voltage, is controlled by the tap changer to achieve the maximum active and reactive power from the VSC, both consumed and generated. The tap changer is located on the secondary side, which has the largest voltage swing, and also to ensure that the ratio between the line winding and a possible tertiary winding is fixed. This tertiary winding feeds the station auxiliary power system and if delta connected suppresses any core triplen fluxes. In order to maximize the active power transfer, the converter generates a low frequency zero-sequence voltage ( δS corresponds to a power flow from the receiving to the sending bus. Similarly, from equation (20.9), both voltage magnitudes and line reactance affect the reactive power. If both voltage magnitudes are the same, that is, a flat voltage profile, each bus will send half of the reactive power absorbed by the line. The power flow is in a sending to receiving direction when VR < VS. Hence, the four parameters that affect real and reactive power flows are VS, VR, XL, and δ. At the receiving end T, equations (20.6) and (20.8) can be combined: 2



P 2 (δ ) + QT (δ ) + 

VT2  V SVT   =  XL   XL 

2

(20.12)

This equation represents a circle, centred ( 0, -VT / X L ) , radius VSVT / XL. It relates real and reactive powers received at bus T to the four parameters: VS, VT, δ, XL. 2

bus T

Similarly, the relationship between the real and reactive powers sent to the line from the sending bus S can be expressed as

jIXL

PS + jQS

As shown in figure 20.1c, the maximum active power is P = V 2 / X L at δ = 90° whilst the maximum reactive power is Q = 2V 2 / X L , at δ = 180°. Equation (20.6) can be used to specify how power and line current flow can be controlled (increased).

and the reactive power, with RL = 0, for the terminal and sending ends are V cos δ −VT QT = VT S

½XL

886

FACTS



P 2 (δ ) +  Q S (δ ) −

VM

VT



VT

VS I ½δ

½δ

2

V S2  V SVT   =  XL   XL 

2

(20.13)

Equations (20.7) and (20.8) show that any change in active power, changes the reactive power requirements of both the sending and terminal ends.

|VS|=|VT|=V

(a) P, Q

Q

(d)

If the line reactance of XL = 0.05pu in conjunction with operating conditions result in a terminal voltage which is 5% less than the sending end, for 1pu power flow calculate:

2

2V /XL

VS

Q =

VXL = jXLI δ ΦT

I

Iq

Ip

P

VT

(c)

VT XL

(V

S

− VT cos δ )

V /XL

P =

0

½π δ

V SVT XL

sin δ

For simplicity, if |VS| = |VT| = V, then, using the midpoint voltage VM as reference (see figure 20.1d), equations (20.6) to (20.10) simplify to V - VT 2V V + VT I= S VM = S sin ½δ ∠½π = = V cos ½δ ∠0 2 XL XL (20.11) 2 2

V sin δ XL

Q = Q S = - QT = V I sin ½δ =

V (1 − cos δ ) XL

The load angle δ The sending and terminal end reactive power requirements, QS, QT The line current, hence the line reactive power, QXL The midpoint shunt voltage that can be inserted that does not change operating conditions

Solution i.

From equation (20.6) rearranged, the load angle is X 0.05 sin δ = PT × L = 1.0 × = 0.0526 1.0 × 0.95 V SVT That is δ = 3.0° and cosδ = 0.9986.

ii.

From equation (20.8), the sending end VAr is V −VT cos δ Qs = VS × S

π

Figure 20.1. Basic HVAC transmission system: (a) circuit diagram; (b) phasor diagram; (c) power and VAr versus load angle load δ (maximum when |VS|=|VT|); and (d) phasor diagram for |VS|=|VT|.

PT = VM I =

i. ii. iii. iv.

2

ref

(b)

Example 20.1: AC transmission line VAr

XL

1.0 − 0.95 × 0.9986 = 1.0 × = 1.026pu 0.05 Since QS is positive, the sending end is generating VAr’s, that is, the power factor is lagging at the sending end (I is lagging VS). The terminal end VAr is given by equation (20.7)

Power Electronics

887

QT = VT

Chapter 20

V S cos δ −VT XL

1.0 × 0.9986 − 0.95 = 0.923pu 0.05 Since QT is positive, the terminal end is absorbing VAr’s, that is, the power factor is lagging at the terminal end (I is lagging VT).

eb

ec

90°

β

ic

1.0 × 0.0526 = 0.05 = 1.0526 pu

120°

c

b

Figure 20.3. Phase voltages and line currents in a three-phase three-wire system and transformation of a-b-c coordinates into α-β-0 coordinates.

I = 0.972+ j1.0526 pu = 1.433 j 42.3° pu wrt VT The line reactive power is given by Qs - QT = 1.026 - 0.923 = 0.103pu. Alternatively, the line reactive power can be calculated from I2XL = 1.4332×0.050 = 0.103pu.

The three-phase instantaneous imaginary power, q, is defined by q = eα i β − e β i α = 1 ( i a (v c − v b ) + i b (v a − v c ) + i c (v b − v a ) ) 3

The midpoint voltage is given by equation (20.10) V M = ½ (VT + V S ) ∠½δ

In matrix form, the two powers are:

= ½ ( 0.95 + 1.0 ) = 0.975pu

∠1.5°

 p   eα q  =  −e    β

wrt V s

If a voltage source with this magnitude and angle, with respect to the sending end, is shunt connected at the midpoint, then no current flows, hence no active or reactive power change occurs. IT =1.43pu ∟42.3°

Icosφ

VS-n =1pu

Isinφ

XL =0.05pu VS-n = 1pu

VT-n =0.95pu

IT = 1.43pu ∟42.3°

VT-n =0.95pu

QS =1.026pu

QS = 0.923pu

PS = 1pu

PT = 1pu

i α   e α  = i β   −e β

i α   e α  = i β   −e β

−e β   p   eα  q 

−1

(20.19)

−1

e β   p   eα e β  0  +   e α  0   −e β e α  q 

i α p   i α q  ≡  +  i β p  i β q 

The theory of instantaneous power in three-phase

Figure 20.3 shows a three-phase three-wire system in the a-b-c coordinates, where no zero-sequence voltage need be included in the three-phase three-wire system (eα + eb + ec = 0 and iα + ib + ic = 0). Threephase voltages and currents in a-b-c coordinates, shown in figure 20.3, can be transformed into the twophase voltages and currents in α-β coordinates, assuming the a and α axes coincide (θaα =0), as follows: e  -½ -½   a  e α  1 3 (20.14)  = 2  e b   0 ½ 3 -½ 3  e  e β   c i  -½ -½   a  1   i b   0 ½ 3 -½ 3  i  c

(20.20)

Let the instantaneous powers in the α-phase and the β-phase be pα and pβ, respectively, and are given by the conventional definition:  p α  e α i α  e α i α p  e α i αq  (20.21) +   = =  p β  e β i β  e β i β p  e β i β q  From equations (20.20) and (20.21), the three-phase instantaneous real power, p, is: p = p α + p β = e α i α p + e β i β p + e α i αq + e β i β q =

(20.15)

e α2

eα + e β 2

2

p+

e β2 eα + e β2 2

p+

−e αe β ee q + 2α β 2 q eα2 + e β2 eα + e β

(20.22)

= p α p + p β p + p αq + p β q

where

The instantaneous real power, p, either in a-b-c coordinates or in α-β coordinates is defined by

p = e a i a + e b i b + ec i c = eα i α + e β i β = dW

−1

eβ  p   eα 1 =   eα  q  e α2 + e β2  e β

The instantaneous currents in α-β coordinates, iα and iβ, can be separated into two instantaneous current components:

♣

3 2

(20.18)

 

e α  i β 

Since eα and eβ are at quadrature, the determinant of the voltage matrix in equation (20.18) is non-zero, hence the inverse of equation (20.18) always exists:

Figure 20.2. Example 20.1.

i α   = i β 

e β  i α 

(20.17)

eα⋅iα and eβ⋅iβ are the instantaneous real powers in the α-phase and the β-phase because both are defined as the product of the in-phase instantaneous voltage in one phase and the instantaneous current in the same phase. eα⋅iβ and eβ⋅iα are the instantaneous reactive powers because defined by the product of the instantaneous voltage in one phase and the instantaneous current in the other phase, which is at quadrature

QXL =0.103pu

20.4

Zb

Zc

α

ib

V sin δ I cos φ = S XL

1.0 × 0.9986 − 0.95 = 0.05 = 0.972pu

θaα

Za

ea

The current can be evaluated by equating equation (20.1) with equations (20.6) and (20.7) I = I cos φ + jI sin φ = I × e j φ

V cos δ −VT I sin φ = S XL

iv.

a

ia

= 0.95 ×

iii.

888

FACTS

dt

(20.16)

iαp, pαp are the instantaneous active current and active power on the α axis, iβp, pβp are the instantaneous active current and active power on the β axis, iβp, pβp are the instantaneous reactive current and reactive power on the α axis, iβp, pβp are the instantaneous reactive current and reactive power on the β axis,

Power Electronics

889

Chapter 20

The sum of the third and fourth terms on the right-hand side in equation (20.22) is always zero. From equations (20.21) and (20.22): p = eα i α p + e β i β p ≡ pα p + p β p (20.23)

0 = e α i αq + e β i β q ≡ p αq + p β q

SHUNT Compensators

Three-phase balanced voltage supply source

v

i

½XL

(20.24)

½XL

PCC

VT

Three-phase load

p

c

XC shunt

q

p

b

Midpoint shunt capacitance

characteristics

δ slightly increased

½XL

VPCC increased

½XL VT

Vs

Heavy load voltage stabilisation

Bc =

XC series

VARdemand -VARuncomp Midpoint series capacitance

V2

Is/c increased δ smaller long transmission lines and bulk power transmission

C = Bc / ω Is/c almost unchanged ½XL

PCC

½XL VT

VS

Figure 20.4. Graphical representation of the three phase power components decomposed into p-q power components.

XL shunt

Midpoint shunt reactance

• The sum of the power components, pαp and pβp, is the three-phase instantaneous real power, p, given by equation (20.16). Therefore, pαp and pβp are referred to as the α-phase and β-phase instantaneous active powers. • The other power components, pαq and pβq, cancel, making no contribution to the instantaneous power flow from the source to the load. Therefore, pαq and pβq are referred to as the α-phase and β-phase instantaneous reactive powers. • Thus, for example, in the case of a shunt active filter without energy storage, instantaneous compensation of the current components, iαq and iβq or the power components, pαq and pβq can be achieved. The theory based on equation (20.18) reveals the components that can eliminate from the α-phase and β-phase instantaneous currents, iα and iβ or the α-phase and β-phase instantaneous real powers, pα and pβ.

½XL VS

∼

∼

∼

∼

∼

q = q + q = q + q h + q 2f 1 p and q are average components p h and q h are oscillating components h harmonic p 2f 1 and q 2f 1 oscillating components with 2f1 being twice the fundamental frequency

The corresponding three phase currents, associated with the average and oscillating power components, decompose into i = i p + i q + i h + i 2f 1 From these power components, the current components in a-b-c coordinates can be calculated from equation (20.19). Instantaneous power theory as presented should not be used with unbalanced or distorted supply voltages. When a linear load is supplied with distorted periodic voltage, the distortions caused by the supply voltage harmonics are still present in the source current after compensation.

PCC

BL =

XL series

½XL VT

Vs

Light load voltage stabilisation

VARdemand -VARuncomp V

2

Midpoint series reactance

SVC

TCSC

Is/c almost unchanged ½XL VT

δ controlled

½XL

½XL

VS

VT

VPCC controlled

Static VAr Compensator STATCOM

Is/c decreased δ increased short transmission lines and short circuit limiting

reactive power control

power damping

Is/c controlled δ controlled pf correction

Thyristor controlled series compensator

Steady state dynamic voltage control Reactive power control of dynamic loads Active power oscillation damping System stability improvement * Is/c short circuit current

p = p + p = p + p h + p 2f 1 and

½XL

VPCC decreased

fast voltage control

When the load is non-linear and unbalanced the real and imaginary powers can be split into average and oscillating components, as follows: ∼

δ slightly decreased

L = 1 / ω Bc

Equations (20.23) and (20.24) imply the following conclusions:

where

SERIES Compensators

characteristics Is/c almost unchanged

VS

a

890

FACTS

P Oscillator Damper Sub-Sync Resonance mitigation

Fault current limiting

Reduction of

• load dependent voltage drops • system transfer impedance • transmission angle Increase of system stability Load flow control Active power oscillation damping

Figure 20.5. HVAC transmission system reactive power shunt and series compensation methods.

20.5

FACTS Devices

FACTS technology may be divided into two principal families:

i. ii.

line-commutated, thyristor based devices and self-commutated IGBT/IGCT devices.

i. Line-commutated FACTS Line commutated FACTS may be considered as providing a means of inserting variable impedance either in parallel (static VAr compensator, SVC) or in series (thyristor switched and thyristor controlled series compensation TSSC/TCSC). The use of thyristor technology readily achieves high-power handing capability with low losses and robust overload capability. These devices have relatively slow response times, of the order of several ac cycles, due to the limits of line frequency switching and the inherent time constant of the thyristor controlled reactive component. Line frequency switching imposes a need for filters and damping networks to eliminate harmonics and low multiples of the power frequency. The FACTS response allows for compensation of sub-cycle transients but they do not have the bandwidth to compensate for higher frequency disturbances. ii. Self-commutating FACTS devices Unlike line-commutated devices, self-commutating FACTS act as controlled energy sources which are capable of injecting voltage or current at the point of common coupling (PCC). This mechanism provides better decoupling between the compensation function and network conditions. Such FACTS devices employ switching devices capable of switching at high multiples of the power frequency (typically in the

891

Power Electronics

range of 1 to 2kHz). This allows elimination of the low order harmonics associated with line-commutated systems. If required this increased bandwidth may be used to achieve active management of harmonics and transients at frequencies above the power frequency (active power filters, APF). Self-commutating FACTS operate as controlled sources that may inject shunt current (STATCOM) or series voltage (dynamic voltage restorer, DVR). Simultaneous series and shunt compensation may be achieved through the integration of both shunt and series devices (unified power flow controller, UPF).

Chapter 20

892

FACTS

Series compensation is defined as any reactive power compensation utilising either switched or controlled devices, which are series connected into the transmission line at a selected node, called the point of common coupling, (PCC) of the transmission system. P

SVC

static VAr compensator

V

V

I

Systems generally use pulse-width modulated (PWM) voltage source inverter (VSI) technology, similar to that employed in variable speed drives. However, since FACTS do not contribute real power, no external power source is required.

XL

VS δs

VT δT

L

C C

VSI based FACTS devices achieve faster response times, improved transient response and reduced size relative to thyristor based systems. The size reduction results from the reduction in mains frequency rated reactive components. The use of PWM semiconductor switched devices increases losses both as a result of increased device conduction loss (relative to thyristors) and the increased loss associated with a high PWM switching frequency. Although low-frequency power harmonics are absent from the output spectrum, the output does contain harmonics at the switching frequency which must be removed using passive filters. These filters are smaller than those required for thyristor systems, however they may contribute to system resonances and incur damping loss.

P =

V SVT sin (δ S − δT XL

I

SPSC

Vσ

)

Vσ VS

load flow VS

Advances in self commutating FACTS devices Since FACTS devices do not contribute to the principal power flow, there is the option for transformer matching between the network voltage and the ratings of power semiconductors. This allows the use of conventional two-level VSI technology, which differs from HVDC where there is a basic requirement for high-voltage conversion systems. Raising the operating voltage of self-commutating FACTS has benefits in terms of increased VAr capability and direct transformerless connection. Increased operating voltage is achieved though series connection of semiconductors or by means of multi-level converters. Multi-level converters synthesis an output voltage comprised of a number of discrete steps, each of which is within the voltage rating of each individual power semiconductor device. This technique extends the achievable operating voltage, resulting in significant improvements in waveform quality, reduced filter size, and decreased losses. Intermediate voltage levels are provided by capacitors in a similar manner to the dc link capacitor of a conventional two-level inverter. However these capacitors require continuous charge balancing and must be sized according to the principal fundamental current; unlike a conventional two-level inverter, where the capacitance experiences only the switching frequency and unbalance components. Power circuits and control of multi-level converters are more complex than those of two level systems.

Static Reactive Power Compensation

In the steady state FACTS devices are used to manage power flows by manipulating the reactive power and impedance seen at different points on the network. There are a number of basic modes to affect static VAr compensation in a transmission system: i. shunt compensation • thyristor controlled reactor (TCR) • thyristor switched capacitor (TSC) • hybrid parallel connect TCR and TSC, termed a static VAr compensator (SVC) • Voltage Source Inverter (STATCOM) ii. series compensation • thyristor switched series capacitor (TSSC) • thyristor controlled series capacitor (TCSC) • hybrid parallel connected TCR and C, termed a static series VAr compensator (SVC) iii. static phase shift compensator (SPSC) iv. dynamic voltage restorer (DVR) v. combined shunt and series compensation, the unified power flow controller (UPFC) Parallel compensation is defined as any reactive power compensation utilising either switched or controlled devices, which are shunt connected at a selected network node, called the point of common coupling, (PCC) of the transmission system.

VS eff

VS eff

σ

series phase shift compensator

C

Vinj

unified power flow controller

½L

½L

VS eff

VS

α X thyristor controlled series compensator I

TCSC

VS eff

VS

Use of FACTS devices to improve network stability FACTS devices have the ability to damp network oscillations through the selective sourcing and sinking of reactive power. To achieve this, the ratings of the FACTS reactive storage components must be sized such that sufficient energy may be stored and released in anti-phase with the oscillation. 20.6

L

parallel - shunt

UPFC Vinj R

α

Figure 20.6. The influence of FACTS devices on the power transfer equation.

Compensators make use of capacitors, inductors and/or power electronic devices, and offer a higher transmission flexibility. Ideal compensators are lossless since their terminal voltage VT and current I are in quadrature. Shunt compensators tend to have minimal effect on the fault short circuit current level, Is/c. Figure 20.5 shows the basic transmission line connection of each type of static VAr compensator, and summaries their main characteristics. Their influence on the power transferred is shown in figure 20.6, which is based on equation (20.6) The relative terminating and sending angle difference is arranged into absolute terms as follows

P =

20.7

V S VT V V sin δ = S T sin (δ S − δT XL XL

)

(20.25)

Static Shunt Reactive Power Compensation

The objective of shunt compensation is to supply reactive power so as to increase the transmittable power by reducing the line voltage under light load conditions and increasing it under higher load conditions. The ideal compensator is lossless. It is located at the transmission line reactance midpoint and maintains the midpoint voltage such that |Vs| = |VT| = |VM|. Characteristically the generated and absorbed reactive powers are increased.

Power Electronics

893

Chapter 20

PS

Shunt static VAr compensators

PT ½QXL

QS

QM

j½XL

IMS

20.7.1 - Thyristor controlled reactor TCR

½QXL

QT

The basic phase angle controlled TCR is shown in figure 20.8b. If the thyristors are used purely as on/off switches with integral cycle control (without phase angle control) then the inductive arrangement is termed a thyristor switch reactor (TSR). Both modes are inductive thus are always associated with reactive power absorption.

j½XL

IMT

Principle of TCR operation The back-to-back connected thyristors conduct symmetrically on alternate half cycles of the ac supply.

IM

PS + jQS

VS

894

FACTS

PT + jQT

VT

i =

VM

(a)

2V ( cos α + cos ωt ) ωLsh

α < ωt < α + σ α + σ < ωt < α + π

=0

where σ = 2(π - α).

j½XLIMS

Qp =

XL

(1 − cos ½δ )

Q

VMT

VS

2

2P

VT

2V /XL

Qp =

IM IMS

4V

compensated

P

VM VMS

2

4V /XL

4P

j½XLIMT

2

2

P

IMT

V /XL

P =

V

2V

2

XL

(1 − cos ½δ )

2

XL

½δ

(b)

(c)

½π δ

0

=

π

I MS = I MT = I =

4V

XL

sin¼δ

(20.27)

With compensation, the transmitted active power is Pp = V MS I MS = VMT I MT = VM I cos ¼δ = V I cos ¼δ sin¼δ × cos ¼δ =

2V 2

XL

sin½δ

(20.28)

The reactive power Qs generated at the sending end and absorbed by the terminal end, QT is 4V 2 2V 2 (20.29) Q S = −QT = VI sin¼δ = sin2 ¼δ = (1 − cos ½δ )

XL

XL

The reactive power Qp provided by the shunt compensator is 8V 2 4V 2 Q p = Q S + QT = 2VI sin¼δ = sin2 ¼δ = (1 − cos ½δ )

XL

XL

(20.32)

[½ sin 2α + π − α ] = B L (α )V

Leff =

Ideally the sending, receiving, and midpoint voltage magnitudes are equal as shown in the compensated phasor diagram in figure 20.7b. The transmission line is then analysed as two independent halves. From this phasor diagram, with V = VM, the two newly formed midpoint current and voltage magnitudes are V MS = V MT = V cos ¼δ (20.26)

XL

π X Lsh

ωLsh

where X shL = ωLsh

If the delay angles of both thyristors are not equal, even harmonics are produced, including a dc component. The total harmonic distortion is increased. As the delay angle increases the current conduction angle σ decreases and the current decreases, as if the inductance were increasing, so that the TCR effective acts like controllable shunt susceptance.

Principle of shunt compensation

4V 2

− (π −α )

2 V

for ½π ≤ α ≤ π with respect to zero voltage cross-over.

Figure 20.7. Midpoint shunt compensation: (a) two source power system model; (b) phasor diagram for |VS|= |VT|= |VM| =V; and (c) power versus load angle.

=

The power factor of the fundamental component lags by 90º, always absorbing reactive power. The odd order rms harmonics shown in figure 20.8d vary with delay angle according to  4 V  sin ( n + 1) α sin ( n − 1) α sin n α (20.31) + − In = cos α  for n = 3, 5, 7...  n 2 ( n − 1) π X Lsh  2 ( n + 1)  and the 90º lagging fundamental rms is given by π −α 2 V I1 = ( cos α + cos ωt ) cosωt d ωt ∫

π

sin δ

uncompensated ½δ

The operation of this configuration has been treated extensively in Chapter 13.1.1ii, where it was shown that continuous conduction occurs at a delay angle of 90º and partial symmetrical decreasing current (decreasing inductive VAr’s) results for delay angles increasing from 90º to 180º, as shown in figure 20.8c. As the delay angle increases the fundamental current component decreases from a maximum, with the introduction of harmonics.

(20.30)

As shown in figure 20.7c, after compensation the maximum transmittable power is doubled, when δ=180º (which represent 90º across each half of the line) but at the expense of greatly increased VAr requirements, as seen in equations (20.29) and (20.30).

V ωI 1

Q1 = VI 1 =

V2 ωLeff

(20.33)

As the delay angle α increases and the current decreases, the thyristor and inductor conduction losses decrease. The maximum fundamental rms current component of V/ωLsh occurs at α=½π. If the three-phase TCR is configured in a delta arrangement, then the third harmonic current does not appear in the source line voltage. If two separate reactors are used in each phase as in figure 20.8a, then conduction up to 360º is possible resulting in the maximum possible fundamental with lower total harmonics, although energy cycling between the two inductors occurs. Alternatively, if transformer coupling is used, then the 5th and 7th order current harmonics can be eliminated if two three-phase delta connected TCR are used with a 12 pulse star-delta transformer secondary arrangement. (Alternatively, two discrete transformers can be used.) The use of a transformer means that voltage levels can be matched (usually a voltage step-down transformer in HVAC systems so that series semiconductor thyristor device connect is avoided). High leakage inductance minimizes the necessary TCR discrete inductance required. Two discrete TCR’s also offers redundancy possibilities. Further, a transformer offers the possibility of reducing the inrush current if used in conjunction with the capacitive TSC.

Power Electronics

895

Chapter 20

VM

VM IL2

IL1(α)

L1

20.7.2 - Thyristor switched capacitor TSC

IL(α)

L2

IL

The basic shunt phase angle controlled TSC is shown in figure 20.9a, where the thyristors are usually operated either continuously conducting or off. Normally capacitor banks are switched in parallel to give line susceptance discrete level adjustment, since phase angle control is not possible because of the uncontrolled capacitive turn-on currents that would result. Beneficially, no harmonics are produced with continuous thyristor conduction. Transformer coupling can be used for voltage matching, the leakage of which helps control the initial current inrush. The capacitive VAr produced is determined by the capacitive current and the resultant system midpoint voltage, VM:

Lsh VM α ≥ ½π

α α

α ≥ ½π (a)

L1 = L2

I

(b)

I =

V I L (½π ) = M ωLsh

VM

IL2

VM = ωCVM = BCVM Xc

(20.34)

VAr = Q p = V M I = − ωCVM2 = − BCVM2 At thyristor turn-on, α, with inevitable series inductance, the current into the formed LC circuit is given by  V n2 n  n2 V cos (ωt + α ) − cos α cos n ωt (20.35) i (t ) = VCo − 2 V sin α  sin n ωt −  2 Xc n −1 Xc  n −1 Xc 

VM

VM IL2(α)

896

FACTS

where n =

IL(½π) ILsh

ILsh

ωt

ω0 = ω

VM

IL(α)

ILsh

Xc and ω is the supply frequency and ωo = 1/√LC. X L sh VM

VM

i

i VCo

C

ISVC

VCo

C

IL(½π)

BC

IL1

Lsh

VM α = 45º

α = 90º

α = 120º

(a)

α = 157½º

VT

(b)

(c)

Vmax

(c) IL1(α)

VM IL2

L1

of I

(d)

IL(α)

L2

(e)

L

α

THD

V

α

1

delay angle δ 135º

120º

110º

105º

90º I=ωCVM

1.2

L1=L2

5% 1pu

VM

pu

α≥½π

I1

Bc

VM

α≥½π

I1

1.1 1

I1 IL1(α)

4% 0.8pu

THD

Vk

VM

jXLIL

System load characteristic

V = Vk +jXLIL

IL2

L1

3% 0.6pu

compensator characteristic

L1=L2

THD

IL

0% 0pu 30º

60º

90º

delayangle

120º α

150º

0

Figure 20.9. Thyristor switched capacitor compensation: (a) ideal capacitor TSC compensator; (b) capacitor TSC compensator with line/leakage inductance; (c)variable susceptance representation; (d) I-V TSC phasor characteristics; and (d) I-V TSC susceptance characteristics.

thenVCo = ∓

1% 0.2pu

0

ICmax

Equation (20.35) can be used to determine the necessary phase angle condition for transient free switch-in of the capacitors. The oscillatory components, the second and third terms in equation (20.35), are zero when cos α = 0, hence sin α = ±1 (20.36)

α

THD

(e)

L2

α

2% 0.4pu

(d)

180º

0

0.2

0.4

0.6

fundamental current

0.8 IL

1

pu

Figure 20.8. TCR compensation: (a) dual reactor TCR compensator; (b) single reactor TCR compensator; (c) line voltage and current waveforms for delay angles α=45º, 90º, 120º and 157½º; (d) harmonics (delta connected - no triplens); and (e) fundamental I-V TCR characteristics.

n2 V n2 −1

(20.37)

The first condition implies thyristor turn-on at either ac peaks or troughs. The second condition implies that the capacitors be pre-charged, then the start up current is given by (first term in equation (20.35))

i (t ) =

V n2 sin ωt Xc n2 −1

(20.38)

Such initial conditions are usual impractical, and a turn-on angle compromise is used which results in acceptable oscillatory transient currents. For capacitor disconnection, when the anode current reaches zero, the thyristors are no longer triggered, the system reactive energy changes abruptly and each capacitor retains a voltage

VCo = ±V

n2 n2 −1

(20.39)

Power Electronics

897

Chapter 20

898

FACTS

20.7.3 - Shunt Static VAr compensator SVC (TCR//TSC)

Example 20.2: Shunt thyristor controlled reactor specification

A static VAr compensator is comprised of a thyristor controlled reactor compensator and a thyristor switched capacitor compensator as shown in figure 20.10a. The leading reactive power is provided in discrete equal steps (or 2n steps) by banks of thyristor switched capacitor compensators (TSC) and precise continuous VAr adjustment is affected by a thyristor controlled reactor compensator (TCR). The maximum lagging current from the TCR is equal to the incremental capacitive leading current, such that the two can cancel to zero giving zero net reactive VA. As the phase angle of the TCR is increased, the net leading VAr increases. At zero TCR conduction, a capacitive bank is decremented and the TCR starts with full conduction, that is zero delay angle. Ideally, no active power is drawn from the system and the reactive power depends on the net fundamental impedance of the parallel capacitor-reactance combination, which is TCR delay angle dependent. PSVC = 0

A 50Hz 400V ac transmission line has line reactance of XL = 2.2 Ω and is delivering 100kW. Calculate i. the load angle δ ii. the line current iii. the TCR and line reactive powers iv. the TCR current and reactance and inductance at this current (with VM = 400V) v. the 50Hz reactance, thence inductance if the maximum TCR current is 100A (1.0 pu) vi. the TCR triggering delay angle, hence thyristor conduction period, if the reactor current is 0.5pu vii. the effective reactance, inductance and the reactive power at a TCR current of 0.5pu viii. delay angle α for VM = 400V, if the TCR inductance is 5mH Solution

V2 = − M = −VM2B SVC X SVC

Q SVC

The SVC is usually transformer coupled for voltage matching of the thyristors. The compensator bus usually incorporates permanent LC notch filters to minimise the injection of 5th and 7th order harmonics, produced by the TCR, back into the HV system. An advanced SVC that uses a voltage source inverter is called at static compensator, or STATCOM. VM

VM

VM

ISVC

ii.

Equation (20.27) gives the transmission line current 4V 4 × 400V I = sin¼δ = sin (¼ × 88.7° ) = 269A XL 2.2Ω

iii.

The reactive power given by equation (20.30) is 4V 2 4 × 400V Q p = Q S + QT = (1 − cos ½δ ) = 2.2Ω XL

BSVC α XC

2

(1 − cos ½ × 88.7° ) = 79, 647VAr

Q S = −QT = ½Q p = 39, 823VAr

α α

XL

Rearrangement of equation (20.28) gives the transmission load angle P X   100kW × 2.2Ω  δ = 2 sin−1  p 2L  = 2 sin−1   = 86.86° 2  2 × 400V   2V 

ISVC

ISVC

α

i.

(20.40)

XL

The TCR current is

Q p 82.445 × 103 VAr = = 199A 400V V Xp V 400V 1.93Ω Xp = = = 2Ω ⇒ L = = = 6.37mH I Q p 207.2A 2π f 2π 50Hz I Qp =

XCo

XC1

XC2

(a)

(b)

(c)

V

ly on or cit pa ca

v.

At 100A the TCR inductance at the fundamental frequency, 50Hz, is Xp 400V 4.0Ω V Xp = = = 4.0Ω thence Lp = = = 12.7mH I Q 100A 2π f 2π × 50Hz

vi.

Solving equation (20.32) gives the transmission angle for a TCR current of 50A 2 V I1 = ½ sin 2α + π − α  π X 

(d) capacitor + reactor

pu

nsat com pe

iv.

ac ed char

teristic

δ=90º re acto

r only

L

Vk

2 400V ½ sin 2α + π − α  π 4.0Ω  0 = ½ sin 2α − α + ¾π ⇒ α = 113.8°

50 A =

system load characteristic

vii.

IL

IC fundamental current

I1

Figure 20.10. Static VAr compensator (SVC): (a) basic SVC; (b) SVC with capacitor banks; (c) variable susceptance model representation; and (d) I-V SVC characteristics.

The effective inductance and reactive power are given by equation (20.33) V 400V Leff = = = 25.5mH 2π f I 1 2π × 50Hz × 50A

Q1 = VI 1 =

V2 = 400V × 50A = 20 × 103 VAr ωLeff

vii. From part iv, the effective inductance for 400V is 6.14mH, or 1.93Ω with 207.2A at the fundamental frequency. 2 L = Leff ½ sin 2α + π − α  π 5mH = 6.37mH ×

2

½ sin 2α + π − α  π

♣

⇒

α = 99.8°

Power Electronics

899

20.8

Chapter 20

Static Series Reactive Power Compensation

Transmission line capability can be increased by installing series compensation in order to reduce the transmission line net series reactance. Effectively the apparent transmission line length is varied. The insertion of inductance decreases transmission capability, but may be used to limit fault levels or to divert power flow, while the insertion of series capacitance acts to cancel the series inductive voltage drop, reducing the net line impedance, thus: • increases power flow capability and stability margins; • reduces the transmission load angle; • increases the virtual load; and • provides a means of damping power oscillations. Normally, series compensation is capacitive. Since distributed compensation along the line is impractical, as with shunt compensation, series compensation is normally inserted at the reactance midpoint. Series compensation is normally only used on very long ac transmission lines, thereby making long distance ac transmission viable. Principle of series compensation The ideal series compensator is effectively pure reactance, without any power loss. The ideal series line compensation of a transmission line is shown in figure 20.11a, where the compensator voltage is at quadrature to the line current. The line resistance is neglected. The effective line reactance is given by X eq = X L − X sc = X L (1 − k ) (20.41)

The voltage across the compensation element, as shown in the phasor diagram in figure 20.11b, at quadrature to the line current, is V sc = IX sc (20.43) The power equations are shown plotted in figure 20.11c. This figure shows that increased capacitance (k > 0), increases the transmittable power and the reactive power. Maximum power is transmitted with a load angle of δ = ½π, when k → 1, that is when ωLL = 1/ωCsc (line resonance at frequency ω). Series static VAr compensators 20.8.1 - Thyristor switched series capacitor TSSC A thyristor switched series capacitor compensator TSSC consist of a least one series capacitor, each shunted by a back-to-back pair of anti-parallel connected phase control thyristors, as shown in figure 20.12a. The thyristors when continuously triggered, provide a path for the line current to by-pass the series compensating capacitors. The thyristor are taken out of circuit when the gate triggering is removed and natural turn-off commutation occurs at the subsequently line current reversal, that is, the thyristors are line or naturally commutated. With this commutation process, the series capacitor charges with a dc bias as shown in figure 20.12b. Subsequent thyristor turn-on should only occur at the line zero current points in order to avoid high initial anode di/dt currents. Vℓ +

where k = Xsc / XL is the degree of series compensation. If the compensation is inductive the reactance is negative and k is negative (k < 0), while k is positive for capacitive compensation (k > 0). Assuming VS = VT = V, then from equation (20.11), the line current, midpoint voltage, transmitted power and reactive power are 2V sin ½δ ∠0 I= X L (1 − k ) Vm = V cos ½δ

Psc = Q sc = ½XL

½Xsc

I

½Xsc

V2

X L (1 − k ) 2V 2

XL

×

k

(1 − k )

½XL

2

VS

TH on

Q =

2V

k

2

XL

(1 − k )

2

2P

V

2

1

XL 1 − k

-½jXcsI

VM VS

VT

k=0.2 k=0

k = Q=0 k=0

½δ

VCn

Vm -

I

Cn

THi

(a) THn

TH on VCi =0

I

TH on

I

ωt

(b)

VCi

Better capacitor series voltage control is obtained if the thyristors in figure 20.12a are selfcommutatable, such as with symmetrical voltage blocking IGCThyristors. This series TCSC compensator is the dual to the shunt TSR in figure 20.8b.

sin δ

P

I ½δ

+

20.8.2 - Thyristor controlled series capacitor TCSC

k=0.4

-½jXcsI

-

Figure 20.12. Thyristor switched series capacitor compensation TSSC: (a) series connected capacitors and (b) zero current activation and zero voltage deactivation.

4P

p =

½jXLI

VCi

VCi

(1 − cos δ )

3P

½jXLI

+

Ci

TH off I=0

(1 − cos δ ) P

VT

VM

-

TH1

(20.42)

Q

VC1 C1

∠0 sin δ

900

FACTS

0

½π

π

transmission angle

Figure 20.11. Midpoint static series compensation: (a) two source power system model; (b) phasor diagram for |VS|= |VT|= V; and (c) power versus load angle.

δ

X cs XL

• Instead of thyristors in series with inductance, thyristors are in parallel with capacitance. • Instead of uni-directional voltage blocking, naturally commutating switches, the capacitive series compensator uses bidirectional voltage blocking, self-commutatable switches. • In the series compensator, compensation occurs when the series thyristors are on, while compensation is active in the series compensator case when the parallel IGC Thyristors are off. • The shunt compensator supports a sinusoidal voltage and produces current harmonics, while the series compensator conducts the sinusoidal line current and produces voltage harmonics. Typical series TCSC waveforms are shown in figure 20.13c, while the harmonics produced are shown in figure 20.8d. It will be noted that the same equations as in section 20.2.4i for the TCR hold, except that voltages and currents are interchanged, and capacitive reactance is used instead of inductive reactance. Specifically, if the line current is

i = I M sin ωt = 2I sin ωt

(20.44)

Power Electronics

901

Then the capacitor voltage is given by

v c (t ) = I M X C ( cos α + cos ωt ) =

Chapter 20

20.8.3 - Series Static VAr compensator SVC (TCR//C)-TCSC

IM ( cos α + cos ωt ) ωC

(20.45)

The power factor of the fundamental voltage component lags I by 90º, always producing reactive power. The odd order rms (total) harmonics shown in figure 20.8d vary with delay angle according to  sin ( n + 1) α sin ( n − 1) α sin n α  4 cos α  for n = 3, 5, 7... + − Vn = I X C  (20.46) π 2 ( n − 1) n  2 ( n + 1)  and the 90º lagging fundamental rms voltage is given by 2 I 2 V1 = where X C = 1 / ωC (20.47) ½ sin 2α + π − α  = I X C ½ sin 2α + π − α 

π ωC

π

for ½π ≤ α ≤ π with respect to zero current cross over. If the delay angles of both thyristors are not equal, even voltage harmonics are produced, including a dc voltage component. The total harmonic distortion is increased.

The TCR//C consists of a line series compensating capacitor in parallel with a thyristor controlled reactor (TCR), as shown in figure 20.14. By varying the delay angle of the TCR thyristors, the capacitive reactance can be decreased, since the fundamental reactance of the parallel combination is given by

X eff (α ) =

I = ωV1

Q 1 = V1 I =

I

XC

As with the shunt TCR, operation below 90º is possible if two capacitors are used as shown in figure 20.13b. Extra semiconductors (diodes) are needed, but the IGC Thyristors only need forward voltage blocking properties. Consequently, capacitors with uni-directional voltage properties can be used. The voltage harmonics are lower but at the expense of extra devices and losses. I

+

VC

-

-

C

C

D

D

TGTO

Vℓ

VC

+

I

+

XC

C

Vm

Pℓm-reg

C XL

L

L

TH

XSVC node ℓ

node m

The voltage harmonics produced by the reactor tend to be trapped in the parallel connected capacitor due to its the low capacitive reactance XC which is inversely proportion to harmonic frequency (relative to line reactance Xs which increases proportional to harmonic frequency). Accounting for the line reactance Xs and compensator fundamental reactance Xeff, the active and sending reactive powers are given by equations (20.6) and (20.8), that is

PT =

-

V S VT sin (δ S − δT X L + X eff

QS = VS ×

)

V S −VT cos (δ S − δT X L + X eff

)

(20.51)

The signs in these equations are appropriately changed for capacitive operation. (b)

TGTO

TGTO

(a)

The capacitor and inductor voltages and currents can be define during the period when the thyristors block and when a thyristor conducts. If the rms line current is IM then • when the thyristors block: Vc (t , α ) = 2I M X C  sin α 1 − sin (ωt − α ) − cos α cos (ωt + α )  + VC t =α +σ

Vc ( ½π ) =

I ωC

I

I C (t , α ) = 2I M sin ωt

I

I Th = I L = 0 VC

VC

GTO on

VC VC

GTO on

ωt

V L (t , α ) = Vc (t , α ) = 2I M X L

VC(α)

VC

I L (t , α ) = 2I M

I α=120º

ωk 2 1−k2

  cos (ωt − α ) − k sin (ωo t − k (α − ½π ) )      cos α     −  sin (ωt − α ) − cos (ωo t − k (α − ½π ) )   (20.53)  

 sin α sin (ωo t − (α − ½π ) / k ) − k cos (ωt − α )       1−k  − cos α  cos (ωo t − (α − ½π ) / k ) + sin (ωt − α )    

k

2

I C (t , α ) = I L (t , α ) + 2I M sin ωt

α=157½º

Figure 20.13. Thyristor controlled series capacitor compensation TCSC: (a) series connected capacitors with shunt self-commutable GTOs for α≥90º; (b) for α≥0º; and (c) line current and current waveforms for delay angles α=45º, 90º, 120º and 157½º.

(20.52)

+VC t =α cos (ωo t − k (α − ½π ) )

VC(½π)

α=90º

(= line current )

and V L (t , α ) = 0

• when a thyristor conducts:

VC(½π)

GTO on

α=45º

Vℓ

-

XL

C

I

VC(¼π)

VCn

+

Vm

VC

(c)

VC

-

(20.50)

Figure 20.14. Thyristor controlled reactance and series connected capacitance, SVC compensation and variable reactance model representation.

Also, as the delay angle α increases and the voltage decreases, thyristor conduction increases, hence thyristor losses increase.

Vℓ

VC1

+

(20.48)

I = I 2 X eff ω C eff

(20.49)

Vm

Vℓ

TH 2

X C X L 1 (α ) X C − X L 1 (α )

where, from equation (20.32), the reactance at the fundamental frequency is ½π X L 1 (α ) = XL where X L = ω L ½ sin 2α + π − α

As the delay angle increases the voltage period angle σ decreases and the voltage decreases, as if the capacitance were increasing, so that the series TCSC effective acts like controllable capacitive susceptance.

C eff

902

FACTS

where ωo =

1

LC

= k ω = 2π f , that is, k =

ωo ω

(20.54)

Power Electronics

903

Chapter 20

Example 20.3: Series thyristor controlled reactor specification – integral control A 50Hz 230kV three-phase ac transmission line has line reactance of XL = 52 Ω per phase and a maximum thermally limited line current of 2000A. The line voltage can vary by ±5% at each end and the load angle between the ends varies between 5° and 10°, where the load is lagging. Series TCSC SVC connected at the midpoint, comprised of four compensating three-phase modules has a capacitive reactance of 10Ω with 1.66Ω of switchable parallel inductance. Calculate i. the nominal power ii. the line current and powers under worse case conditions, before series compensation iii. the effective module reactance when the impedances are parallel connected iv. the effective line impedance at worse case, if 50% of rated power is the transmission objective, and the resultant transmission powers

904

FACTS

necessary line reactance, for half rated power, is given by V ×VR P = T sin δ

XL

= 50% of 796MW =

95%VNom × 105%VNom

XL

sin δ

95%230kV × 105%230kV

XL

sin10°

⇒ X L = 23Ω Figure 20.15 shows that with only one module activated, the line reactance can be compensated to 24Ω. The real power flow and reactive powers are: V ×VR sin δ P = T

XL

Solution

218.5kV × 241.5kV sin10° = 24Ω = 381.8MW

i. The nominal maximum power is given by P = 3V L I L = 3 × 230V × 2000A = 796MW

ii. Worse case power delivery conditions are when the sending end is 5% below the nominal ac voltage, while the receiving end is 5% above the nominal, at the highest load angle, δ=10°. The current can be evaluated by equating equation (20.1) with equations (20.6) and (20.7) I = I cos φ + jI sin φ = I × e j φ

V cos δ −VT QT = I sin φ = S XL VT

V sin δ P = I cos φ = S XL VT

218.5kV × cos10° − 241.5kV = 52Ω = −0.5051kA

218.5kV × sin10° = 52Ω = 0.730kA

The sending end reactive power is V −V cos δ Qs = VS × S T

XL

= 218.5kV ×

218.5kV − 241.5kV × cos10° = −176MVAr 24Ω

The terminal end reactive power is V cos δ −VT QT = VT S

XL

218.5kV × cos10° − 241.5kV = −264.8MVAr 24Ω The line reactive power is given by Qs - QT = -176MVAr + 264.8 MVAr = 88.8MVAr. = 241.5kV ×

I = −505.1+ j730.0 = 887.7 − j 55.3° pu wrt VT The real power flow is:

½XL = j26Ω

P =

VT ×VR sin δ XL

218.5kV × 241.5kV sin10° 52Ω = 176.2MW =

= 218.5kV ×

218.5kV − 241.5kV × cos10° = −81.2MVAr 52Ω

The terminal end reactive power is V cos δ −VT QT = VT S

218.5kV ∟0°

-96.4MVAr

j1⅔Ω

j1⅔Ω

j1⅔Ω

j1⅔Ω

j2Ω

j2Ω

j2Ω

j2Ω

37.1MVAr

37.1MVAr

37.1MVAr

218.5kV × cos10° − 241.5kV = −122.2MVAr 52Ω The line reactive power is given by Qs - QT = -81.2MVAr + 122.2 MVAr = 41.0MVAr. Alternatively, the line reactive power can be calculated from I2XL = 887.72×52 = 41.0MVAr

− j 10Ω × j 1.66Ω = j 2Ω − j 10Ω + j 1.66Ω

iv. Worse case power delivery conditions are when the sending end is 5% below the nominal ac voltage, while the receiving end is 5% above the nominal, at the highest load angle, δ. That is, the

-96.4MVAr

241.5kV∟15°

218.5kV ∟0°

382MW

1926A

1926A x°

218.5kV/√3

15°

iii. The inductor j1.66Ω in parallel with the capacitor –j10Ω give a parallel combination impedance of − jX cap × jX ind X cell = − jX cap + jX ind =

-7.4MVAr

89MVAr

XLeq = j24Ω

= 241.5kV ×

241.5kV∟15°

-265MVAr

-176MVAr

382MW

XL

½XL = j26Ω

-j10Ω

1926A

The sending end reactive power is V −VT cos δ Qs = VS × S

XL

-j10Ω

-j10Ω

-j10Ω

241.5kV/√3

Figure 20.15. Example 20.3.

46.2kV/√3

Power Electronics

905

Chapter 20

The current is

906

FACTS

Then ½π XL ½ sin 2α + π − α ½π × 1.11Ω 32.0Ω = ½ sin 2α + π − α ♣

I = I cos φ + jI sin φ = I × e j φ V cos δ −VT QT = I sin φ = S XL VT

X L 1 (α ) =

V sin δ P = I cos φ = S XL VT

218.5kV × cos10° − 241.5kV = 24Ω = −1.10kA

218.5kV × sin10° = 24Ω = 1.58kA

⇒

α = 167°

20.8.4 Static series phase angle reactive power compensation/shift SPS

I = −1100 + j1581 = 1926 − j 55.2° pu wrt VT The line reactive power can be calculated and confirmed from I2XL = 19262×24Ω = 89.0MVAr The sending power factor is

P = 3V s I L cos φ = 3 × 218.5kV × 1.926kA × cos 52.5° = 443.7MW ♣

Phase compensation is a specific case of series compensation, as shown in figure 20.16, where the phase angle change is used to control the power flow. Where as series reactive control is usually located at the line reactance midpoint, phase angle compensation is performed at the sending end of the transmission line. The compensator is an ac voltage source Vε of controllable magnitude and phase angle. The effecting sending end voltage VS eff becomes V S eff = V S + V ε (20.55) Series connected transformer

VS I

VT

Example 20.4: Series thyristor controlled reactor specification – Vernier control XL

A 50Hz 400V ac transmission line has line reactance of XL = 2.2 Ω and is delivering 100kW at a load angle of 80º. The TCSC comprising C=30µF and L=3.53mH is operated at a load angle of 80º. Calculate i. the degree of compensation k ii. the compensating capacitive reactance iii. the line current I iv. the reactive power Q v. the TCSC delay angle if the effective capacitive reactance is 200Ω

excitation transformer

(a) TH

Phase angle controller see right and figure 20.19

Solution i.

Thyristor network

From equation (20.42)

k =1−

VS

V2 4002 × sin 80° = 0.284 sin δ = 1 − X L Psc 2.2Ω × 100kW

VT

Φ I

(b) XL

ii.

iii.

iv.

v.

From equation (20.41), the compensation reactance is X sc = kX L = 0.284 × 2.2Ω = 0.624Ω

j½XsIδ

Vε+

From equation (20.42) 2V 2 × 400V I= sin ½δ = sin ½80° = 326.5A X L (1 − k ) 2.2Ω × (1 − 0.284 )

Vε

X eff

X X (α ) (α ) = C L 1 − X C + X L 1 (α )

200Ω =

106.1Ω × X L1 (α )

−106.1Ω + X L1 (α )

⇒

X L1 (α ) = 32.0Ω

XL

VS

TH

VT

Vs δ+

Vs eff(+ε)

Φ

From equation (20.42) 2V 2 k 2 × 4002 0.284 Q sc = × 1 − cos δ ) = × × (1 − cos 80° ) = 66,586 VAr 2 ( 2 X L (1 − k ) 2.2Ω (1 − 0.284 ) The compensator capacitive reactance is 1 1 1 Xc = = = = 106.1Ω ω C 2π f C 2π 50Hz × 30µF The compensator inductive reactance is X L = ω L = 2π f L = 2π 50Hz × 3.53mH = 1.11Ω From equations (20.49) and (20.50)

I

j½XsIε+

VS eff

+ε

VT

δ Iδ

(c)

Figure 20.16. Transformer series phase angle compensation: (a) series transformer with ac tap changing thyristor network; (b) variable phase angle representation; and (c) two port series phase angle compensator system.

The compensator can function in one of two ways.

•

The load angle is varied maintaining a voltage magnitude VS eff the same as the sending voltage Vs V s eff = V S = V S eff = V S = V (20.56)

•

The compensator phase angle is maintained at quadrature to the sending voltage

V S eff = V S eff = V S2 + V ε2

(20.57)

Power Electronics

907

Chapter 20

In both cases, power flow control is achieved at the expense of consuming reactive power from the network. The system transfer admittance has Vs replaced by Vs eff, that is I S eff  1 cos φ + j sin φ  V S eff  1  (20.58)  =    1   VT   I T  X L  − ( cos φ − j sin φ )

Vε+

j½XLIδ Φ =½π

Equations (20.59) and (20.60) show that • The maximum power and VAr are unchanged, only the load angle at which they occur can be controlled. • Unlike other series and shunt compensators, the phase compensator needs to handle both real power and VAr. From the phasor diagram in figure 20.17a, the shift compensator terminal voltage and current are V ε = 2V sin½ε (20.61) 2V sin½δ I =

XL

The apparent power of the compensator is therefore 4V 2 S comp = V ε I = sin½ε sin½δ

(20.62)

XL

If the compensation angle is negative, by effectively reversing the terminals of the compensator, then maximum power can be attaining for load angles of less than ½π, as indicated by the dashed sine curve portion in figure 20.17b. Vε-

P =

j½XLIε-

V2 XL

j½XLIδ

Vε+

2ε

j½XLIε+

VS

VS eff(-ε)

sin δ ± ε

2

V /XL

P VT

δ+ε unc

VS eff(+ε)

a te d

-ε

ens

+ε

om p

δ-ε δ

Iδ

(a)

-ε

0

+ε

½π δ

π

(b)

Figure 20.17. Transformer series phase angle compensation: (a) phasor diagram for phase shift ±ε and (b) transmission power versus load angle.

π+ε

2

VT

Vε=-½

Vε=½ Vε=0

Vε=0

-ε

V Vε

V /XL

δ-ε +ε

−1

Vε=1

δ+ε

VS eff(+ε)

tan

a te d

XL

VS eff(-ε)

 

cos δ 

ens

By controlling the compensator angle ε, the output power can be controlled independent of the transmission load angle δ. The peak power can be shifted from a load angle δ = ½π to any desired load angle, by maintaining the phase shifter angle such that δ - ε = ½π is maintained. The transmitted reactive power is 2V 2 (20.60) Qcomp = (1 − cos (δ − ε ) )

V

 sin δ +

om p

(20.59)

Vε

XL 

Vε=-1

j½XLIε+

VS

V s VT V2 sin (δ − ε ) = sin (δ − ε ) XL XL

Pquad =

j½XLIε-

unc

= PScomp −T

V  2

Vε-

Phase shifting (Φ 0 DVR

(a)

VS VS

VDVR

VDVR

XDVR

XL

VT

VT

V ∠ϕ

(b)

I

(c)

IDC

(d) C

VT

VDC

VS I @ 90º to VDVR

VDVR @ 90º to I VSI limit

V DVR

VSI

BWW

(c)

L L

L Clp VS VT VDC

VS

non-linear load

VT XL XS

(b) single-phase static synchronous compensators using dc-link capacitor voltage sources; and (c) static synchronous compensators using dc-link inductor current sources.

Clp IDC

Ish IDC

IDC Vse Ise IS XS XL I Vse Ise IS XS I Vse

If the DVR does not involve any active power source and the only real power drawn from the ac line is that necessary to maintain the capacitor voltage so as to compensate for inverter and coupling transformer power losses, then Vd = 0 and Vq is in quadrature to the compensator/line current. By varying the magnitude of Vq, the DVR performs the function of a variable reactance compensator, where Vd ≈ 0

input

IS

The static synchronous series compensator (is a dynamic voltage restorer without active power transfer) is a transformer coupled, PWM voltage source inverter that functions in series with the distribution line as shown in figure 20.21. Theoretically, it draws no power from the line since it uses a capacitor on its dc link which provides only reactive power. This makes the DVR a versatile regulating compensator. In steady-state it functions as a series phase shifter SPS, injecting a variable magnitude and angle voltage at one line end in order to control both the active and reactive power flow. The phase angle (which controls the real power if a suitable bidirectional dc-link source exits) is controllable between 0 and 2π, as shown in the phasor diagram in figure 20.21c. The magnitude of VDVR is controlled by the inverter PWM modulation depth. As well as being a SPS it also functions as a variable series impedance compensator. Generally, from figure 20.21a V DVR = VT −V S (20.64) = V DVR ( cos ϕ + j sin ϕ ) = Vd + jVq

Figure 20.20. Static synchronous compensator family: (a) transmission schematic of voltage source compensators (as power filters) transformer coupled to the ac network;

VT

I

XL

VT

XL I

I

XL

VT

20.9.1 - Static synchronous series compensator (SSSC) or Dynamic Voltage Restorer - DVR

Figure 20.21. Static synchronous series compensator (or dynamic voltage restorer DVR): (a) schematic and (b) block diagram of a voltage source inverter, transformer coupled in series with the ac network; (c) series connected DVR shown as a variable magnitude and phase angle voltage source SSSC; and (d) 50/60Hz operating phasor diagram of SSSC, where VDVR is always perpendicular to the line current, I.

BWW

913

Power Electronics

Within its energy limits, the DVR is suited for dynamically compensating any line feeding sensitive or critical equipment for • voltage harmonics • power factor correction and for a short duration • voltage sags and swells • voltage imbalances • outages

Chapter 20

Series Voltage regulation The terminal voltage VT in figure 20.22a draws a lagging current IT and the series compensator VDVR is to maintain the load voltage VT constant, but at any angle with respect to VS. From Kirchhoff’s voltage law V S = jI T X R +VDVR +VT (20.66) The series compensator can deliver any voltage up to a maximum V DVR , as shown by the circle outer locus with centre O for the series regulator in figure 20.22b. If VT is held constant then the source VS can have a magnitude and angle that lies anywhere within the circle. If VT sags and swells (changes length) then provided the variation is within the circle, VDVR can compensate to maintain a constant voltage VS. Maximum and minimum voltage compensation needed from VDVR occurs when the source VS forms a tangent to the circle as shown in figure 20.22c. In each case the current is not in phase with the compensation voltage, hence the compensating converter must transfer real power. The effective sending voltage VS eff is phasor N-O. The phasor O-W represents the case when power is delivered from the compensator in an effort to compensate for the sagging (reduced) VT voltage phasor N-W, while the phasor O-X represents the case when VT has swelled to phasor N-X and power is drawn by the compensating converter whilst attempting to decrease the line voltage. The inverter in figure 20.21a creating VDVR must have a bidirectional dc voltage supply maintaining the dc-link voltage. The converter dc-link voltage can be self-supporting if no energy is lost or gained by the dc-link when the line current is at quadrature to the compensator voltage, as shown in figure 20.22d. In this case, the source voltage VT can be compensated when its voltage phasor lies along the line W-O-X. The magnitude range of the voltage VT that can be compensated, is reduced. The range is reduced from phasor N-W to phasor N-X in figure 20.22c converter power can be transferred, to between N-Y to N-Z when only reactive energy can be transferred by the compensating converter, as in figure 20.22d. The series compensation is effective for a wide range of line impedances, including low impedance stiff feeders, provided the line impedance phasor is within the compensating circle. The basic series converter arrangement can also be using for voltage distortion compensation. The phasor diagrams in figure 20.23 show the series compensator operating in three different modes, namely, capacitive and inductive compensation and in a mode of reversing the power flow. The effective sending voltage VS eff is shown as a dashed line in each case. Series line resistance has been added, giving the voltage phasor VR in phase with the current in the parts of figure 20.23. The line voltage drop, Vline is therefore the line impedance voltage drop.

jXR

IT

VS eff

VS-n

O

VT-n

N φ

N

VS-n

W V DVR O

N φ

VXR

VT-n

IT

−V DVR

(a)

(b)

(c)

(d)

Z

VS-n

X φ

IT

−V DVR

VXR

VT-n

N

VXR

VT-n

VDVR

VS-n

VXR

VDVR

In the standby mode, the output voltage is zero and the inverter losses are low since no switching occurs. By turning on all the upper (or lower but not both) switches in the VSI inverter, the three singlephase transformers and inverter are seen in the line as a short circuit (as for a current transformer). Given transformers are necessary, voltage matching of the VSI devices facilitates the use of 3.3kV IGBT technology that allow modulation frequencies above 2kHz, which is necessary for active filtering. Specific single-phase transformer coupling can be avoided if the DVR is connected at the opened star point of the main ac supply Y configured transformer or autotransformer. Alternatively, access to the transformer star point allows the use of a three-phase autotransformer rather than three single-phase transformers. A CSI is well suited for series application (with an outer voltage loop) since it is normally operated with the switches in an on-state, thereby ensuring that the DVR is seen as a short-circuit in the standby/fault mode. Voltage harmonic cancellation Each of the three source voltages can be expressed in terms of a fundamental frequency phase voltage and its harmonics. Inserting appropriate voltages can compensate for harmonics associated with the terminal supply voltages under balanced an unbalanced conditions in three wire systems.

914

FACTS

IT

O

V DVR

Y

Figure 20.22. Static series voltage compensation: (a) series compensated network; (b) general series voltage compensation; (c) voltage sag and swell real-power compensation; and (d) quadrature reactive-power series voltage compensation.

Capacitive compensation SSSC capacitive compensation is shown in figure 20.23a. The phasor quadrature voltage VDVR is in the opposite direction of the phasor VXR and VDVR lags the current phasor I by 90°. For the same line total voltage drop Vline, the voltage phasor associated with the line reactance VXR increases and results in a transmission line current increase. Inductive compensation Inductive compensation is shown by the phasor diagram in figure 20.23b. The quadrature voltage is in the same direction as the phasor VXR and VDVR leads the current phasor I by 90°. For a constant Vline, the phasor VXR decreases. The transmission line current reduces and results in reduced power flow. Reverse power flow The ability of an SSSC to reverse power flow is illustrated by the phasor diagram in figure 20.23c. Operation is similar to inductive compensation but the VSC voltage is increased until larger in magnitude than VXR. For a constant Vline, VXR reverses direction and the current phasor I reverses, thence power flow is reversed. VDVR

VDVR

VDVR

voltage limit

voltage limit

VXR

voltage limit

VDVR VDVR

VXR

φ

φ

VS-n

VS-n

VS-n

VXR

φ VDVR

VR

IT

Vline

Vline

Vline

VR

IT

VT-n

VT-n

(a)

(b)

VT-n IT (c)

Figure 20.23. Phasor diagrams for the three series compensator modes of operation: (a) capacitive compensation; (b) inductive compensation; and (c) power flow reversal.

VR

Power Electronics

915

Chapter 20

20.9.2 - Static synchronous shunt compensator - STATCOM The STATCOM (static synchronous shunt compensator) is a shunt compensator comprising a current or voltage source inverter, shunt connected to the ac system through a first order passive filter, as shown in figure 20.24a for a VSI. The dc-side main reactive energy storage element is • a dc capacitor (voltage source, VSI) in which case the interconnect filter comprises series line inductance for attenuating VSI output voltage harmonics or • an inductor (current source, CSI) in which case the interconnect filter comprises shunt capacitance for bypassing CSI output current harmonics. Not favoured over the VSI. No net energy is needed, except to replace the energy dissipated in the inverter and filter components. The STATCOM function is to • regulate the line at the point of connection when functioning in a SVC mode and/or • minimise current harmonics by anti-phase current injection action – as an active filter. IDC C

IL

VSC

+ VDC

(a) VSC > VT

VT ISC

generates (leading) VAr capacitive

PCC

VSC VSI

ISC XSC

VT

ISC

VSC

IL

XSC

VT ∠δT

VSC ∠δ sc

ISC

VT

PCC

VSC

VSC

ISC = 0 VSC = VT ISC = 0 VAr = 0

VA VB

ISC

VC

VT

IDC VSC Rdump

VSC < VT

XSC I a

C

+

VDC

Ic

Ib

VSI

absorbs (lagging) VAr inductive

PCC VSC

ISC XSC

(b)

(d)

(c)

Figure 20.24. Active shunt regulator - STATCOM: (a) a voltage source inverter VSI, inductively shunt connected (transformer coupled) to the ac network; (b) shunt connected STATCOM shown as a variable magnitude and phase angle voltage source; (c) main VSI circuit; and (d) phasor diagrams for leading (upper phasor diagram) and lagging (lower phasor diagram) modes of operation.

Figure 20.24b shows the system model, while figure 20.24c shown the simplified VSI circuit. The series voltage harmonic filtering inductance can be the leakage inductance associated with the three singlephase line voltage matching transformers or three auto-transformers. A dc chopper, with a dumping resistor as load, may be used across the dc-link capacitor to limit VSI over-voltage during intermittent transients when the STATCOM acts as an uncontrolled rectifier, created by the VSI freewheel diodes

916

FACTS

shown in figure 20.24c. The phasor diagram in figure 20.24d, for the line to neutral voltage, is associated with the circuit in figure 20.24b, in conjunction with the power and reactive power equations given by equations (20.6) and (20.8), can be used to explain STATCOM operating principles.

P = Q SC = VT ×

V SC VT sin (δT − δ SC ) = 0 X SC

VT −V SC cos (δT − δ SC ) VT = (V −VSC X SC X SC T V −V sc −n I sc = T −n X sc

(20.67)

)

(20.68) (20.69)

In steady-state, the inverter output voltage fundamental VSC (which is controlled by the PWM modulation index) is in phase with the ac line voltage VT (δSC = δT), while the STATCOM current ISC always leads or lags the line voltage by 90º because of the inductive reactive coupling XSC therefore cos(δT - δSC) = cos0 = 1, Thus P ≈ 0 is maintained as given by equation (20.67) when sin(δT - δSC) = sin0 = 0. From equations (20.67) and (20.68), since δSC = δT, only reactive power flows and • when the STATCOM voltage VSC is less than the line voltage VT (│VSC││VT│, the STATCOM generates (capacitive) reactive power (which tends to increase the point of connection voltage). • When VSC =VT, the voltage VSC across the connecting inductance XSC is zero, so no STATCOM current flows Isc = 0. Thus a STATCOM behaves like a shunt inductor (I lags V) without a physical inductor or magnetic field, and like a shunt capacitor (I leads V) without a physical capacitor or electric field. When used in a voltage regulation mode (as opposed to a VAr control mode with constant reactive power output) the STATCOM terminal I-V characteristics are as shown in figure 20.10c for the SVC. The dc link capacitor is initially charged through the VSI freewheel diodes which form an uncontrolled three-phase line rectifier. Subsequently the STATCOM is controlled to self regulate its dc-link voltage, VDC, as follows. When the fundamental voltage of the STATCOM slightly leads the ac supply voltage, VSC leads VT, the capacitor voltage decreases resulting in VSC < VT, real power is transferred from the dc link to the ac line and reactive power is absorbed by the STATCOM – lagging power mode. When the STATCOM fundamental voltage slightly lags the ac supply voltage, the capacitor voltage increases, VSC > VT, real power is transferred from the ac line to the dc link and reactive power is generated by the STATCOM – leading power mode. Thus the STATCOM fundamental magnitude VSC controls the reactive power, while the phase angle between the STATCOM and the ac line, δT – δSC, controls real power flow. In practice, when VSC slightly lags VT (δSC lags δT), the capacitor voltage VDC is maintained whilst catering for system inverter and transformer power losses. In this way no separate dc power supply is needed to maintain the dc-link capacitor voltage. Notice that the dc-link voltage will always be greater than the rectified ac grid voltage due to the (uncontrolled) rectification action through the six inverter bridge freewheel diodes. Although practical limits exist on the magnitude of VSC, the STATCOM power load angle δSC is continuously adjustable between 0 and 2π, but operates near the line phase angle δT in order to minimize real power transfer. The SATCOM can generate more reactive power during a fault than the SVC since • from equation (20.40), SVC capacitive reactance power decreases proportionally to voltage VM while • from equation (20.68), STATCOM capacitive reactive power decreases linearly with voltage VSC. Shunt voltage regulation The terminal voltage VT in figure 20.25a draws a lagging current IT and the shunt compensator Vsh is to maintain the load voltage VT constant, but at any angle with respect to VS. From Kirchhoff’s voltage law for the right hand loop in figure 20.25a, VT = jI sh X sh +V sh −n (20.70) The shunt compensator can deliver any current from zero up to a converter maximum I sh , giving, for a fixed compensation reactance Xsh, the circle outer locus with centre O as shown in figure 20.25b. Thus a small change in the magnitude and phase of Vsh will cause the shunt reactance voltage to rotate through 360°. From Kirchhoff’s current law, the shunt regulator point of common contact, PCC, yields I S = I sh + I T (20.71)

Power Electronics

917 jXR

IS

Chapter 20 jXR

IT Ish

VXR

VXR

Vsh-n

jXsh

VT-n

VS-n

VXsh = - jXshIsh

N

Vsh-n

φ

Ish N

VS-n VT-n + jITXR N

φ IT

VT-n

jXsh

Ish

(a)

(b)

(c)

(d)

N

Vsh-n

VXsh = RshIsh

Ish

(a)

Y

jIshXR

-jIshXR Z

VS-n

Ish N

φ

VXsh = jXshIsh

(b)

Figure 20.26. Active shunt compensator used for power factor correction: (a) shunt compensated network and (b) phasor diagram.

O

I sh X R

VT-n

N

VT-n

IT

jIshXR

jITXR

IT

PCC

Vsh-n

IS

W

IS

Rsh

VS-n

O

VT-n

918

FACTS

VS-n φ

VT-n

jITXR

I sh X R Vsh-n

jIshXsh

IT

Figure 20.25. Active shunt compensation: (a) shunt compensated network; (b) general shunt voltage compensation phasor diagram; (c) shunt voltage compensation; and (d) quadrature reactive-power shunt current compensation.

These currents are shown in figure 20.25b. The outer voltage loop in figure 20.25a gives V S −n = jI S X R +VT −n Substituting equation (20.71) gives V S −n = j ( I T + I sh ) X R +VT −n = {VT −n + jI T X R } + jI sh X R

(20.72)

(20.73)

Since the load network VT in conjunction with the load network current IT specify the load power factor, the phasor N-O, {VT-n + jITXR} in figure 20.25c is fixed. Because Ish can be varied between zero and I sh , phasor VS-n can lie anywhere within the circle shown in figure 20.25c and not affect the load network VT. In figure 20.25c, the shunt regulator is delivering real power into the load network since the shunt compensating network PCC voltage VT-n and shunt current (angle given by phasor O-W in figure 20.25c) are not in quadrature. Figure 20.25d shows the loci for the case when no real power is transferred by the shunt compensator, since the compensator current Ish is in quadrature to the shunt voltage Vsh-n, which is in phase with the load network VT. The allowable range of variation on the source voltage VS-n is a minimum for phasor NY (voltage-swell) and a maximum for phasor N-Z (voltage-sag), as shown in figure 20.25d. This range of possible voltage compensation is determine by the line reactance XR, which specifies the inverter current rating Ish needed to produce the necessary compensation range, namely the diameter of the circle in figure 20.25c. That is, the lower the line reactance XR the higher the necessary compensating inverter current rating for a given voltage compensation range. The shunt compensator operates in a type of current push-pull or sourcing-sinking mode. • When the source voltage VS is too high, voltage swell, the shunt draws or sinks current additional to the load current in order to increase the voltage across the line reactance XR, thereby tending to decrease the load voltage VT. • When the source voltage VS sags, the shunt compensator sources current to the load network VT, thereby reducing the source current which decreases the voltage across the line reactance XR, making a higher component of the source voltage available across the load network VT. During each mode of operation, the phasor angular relationships must be observed within this simplistic explanation. The basic shunt converter arrangement can also be using for line current distortion compensation.

Power factor correction The shunt compensator can be used for power factor correction at the PCC. The compensator current Ish is set to be 90° behind the PCC voltage VT-n, with the magnitude of the current Ish determining the magnitude of the compensation. This is achieved by ensuring that the load voltage and shunt regulator voltage are in phase, but the relative magnitudes are varied (Vsh-n > VT-n). Since only VAr are involved from the shunt regulator, no shunt regulator dc voltage supply is needed to maintain the dc-link capacitor, except inverter losses must be accounted for. By ensuring the shunt voltage Vsh-n slightly lags the line voltage VT-n, the necessary inverter losses can be provided from the grid. If the inverter losses are incorporated, as represented by the resistor in figure 20.26a, then the resultant phasor diagram in figure 20.26b complies with the following output loop voltage equation. V sh −n = I sh Rsh + jX sh I sh +VT −n (20.74) The reactive power provided to the ac system from the shunt power factor controller is Q = Ish VT-n, while P = Vsh-n Ish cosφ real power is drawn from the line to cater for the inverter power losses. Since no separated dc-link voltage source is required, the shunt regulator is acting as a STATCOM, as considered earlier. Harmonic current compensation Figure 20.27 shows a system with a shunt active filter for harmonic current compensation of a nonlinear, diode rectifier, where the active filter circuit consists of a three-phase voltage-fed PWM inverter and a dc-link capacitor, Cdc. The active filter is controlled to draw the compensating current, iAF , from the utility that cancels the harmonic current flowing on the ac side of the diode rectifier with an inductive dc load. Equation (20.19) represents the α-phase and β-phase compensating currents:

i AF α   e α  = i AF β   −e β

−1

e β   p AF   e α  q AF 

(20.75)

diode rectifier iS

iL

L

R

pL qL

e iAF

shunt active filter

Cdc

+

vdc

pAF qAF Figure 20.27. Active shunt filter used for ac current distortion compensation.

The powers pAF and qAF are the three-phase instantaneous real and imaginary power on the ac-side of the active filter, and can be extracted from pL and qL, which are the three-phase instantaneous real and imaginary powers on the ac-side of a harmonic-producing (non-linear) load. When the active filter compensates for the harmonic current produced by the non-linear load:

p AF = − p L

q AF = −q L

(20.76)

Power Electronics

919

Chapter 20

where, p L and q L are the ac components of pL and qL, respectively. The dc components of pL and qL correspond to the fundamental current in iL and the ac components correspond to the harmonic current. Two high-pass filters can be used in the control circuit to extract p L from pL and q L from qL. The active filter draws and releases pAF from the utility, and delivers it to the dc capacitor, assuming no loss dissipation in the active filter. Thus pAF produces a voltage fluctuation on the dc capacitor. The amplitude of pAF is assumed constant, then the lower the frequency of the ac component, the larger the voltage fluctuation. The dc capacitor has to absorb or release electric energy given by the integration of pAF with respect to time. Thus, the relationship between the instantaneous voltage across the dc capacitor, vdc and pAF is: t

½C dcv dc (t ) = ½C dcv dc ( 0 ) + ∫ p AF dt 2

2

920

FACTS VT-n

N

Ish

φ

Vsh-n

+Qmax, p=0

Ish

(20.77)

o

VT-n

VAr to the grid capacitive

Vsh-n

VXsh

φ

N

VXsh

Ish

VXsh

Q>0 P=0

VT-n

N

Vsh-n > VT-n

Vsh-n

+Q

This implies that the active filter needs large dc capacitance to suppress the voltage fluctuation in order to harmonic compensate p L . The main purpose of the voltage-fed PWM inverter is to perform an interface conversion between the utility and the dc capacitor. The active filter draws qAF from the utility, as shown in Fig. 20.27. However, qAF makes no net contribution to energy transfer in the three-phase circuit. No energy source is required to the dc side of the active filter, independent of qAF, whenever pAF = 0.

VT-n

N

Vsh-n

Vsh-n

power from the grid

Q=0 P0

Vsh-n

power to the grid

Vsh-n N VT-n -Qmax, p=0

Ish

N

(20.78)

φ

φ N

VXsh

(20.79) Ish

Q LR the shunt compensator must produce an anti-phase voltage greater in magnitude than the harmonic line voltage. Series compensation techniques are more effective for line voltage distortion compensation, while shunt compensation methods are more effective for line current harmonic compensation. The four-quadrant P-Q and boundary phasor diagrams for the shunt regulator are shown in figure 20.29.

Table 20.1: Comparison of STATCOM and SVC property I-V characteristic Control range

Modularity

Response time Transient behaviour

STATCOM

SVC

Current source Good under-voltage performance Symmetrical Otherwise hybrid solution Redundancy Compensated aging degradation Common inverter to other applications 1 to 2 cycles No natural commutation delays

Impedance source Good overvoltage performance

Self protecting on critical system faults

Adjustable with cascaded TCR/TSC Redundancy Aging degradation TCR/TSC branches common additions to SVC 2 to 3 cycles Limited by supply frequency Active before, during and after transient conditions

Volume requirements

40% to 50% of SVC

100%

On-line availability

96% to 98% of time

>99% of the time

120% to 150% that of SVC

100%

Capital costs

Power Electronics

921

Chapter 20

The series and shunt converters are operated to give point of connection voltages V se = V se ( cos θse + j sin θse ) 0 ≤ θ se ≤ 2π

20.9.3 - Unified power flow controller - UPFC

(20.80) V sh = V sh ( cos θsh + j sin θ sh ) 0 ≤ θsh ≤ 2π The magnitudes of converter voltages Vsh and Vse are controlled by the turns ratio of the matching transformers, the PWM modulation depth, and are restricted by the operational voltage limits (both upper and lower voltage limits) imposed by the inverter technology. Vdc V SH = mSH 2 2 n SHVB (20.81) Vdc V SE = mSE 2 2 n SEV B where m is the inverter modulation index, n is the coupling transformer turns ratio, VB is the transmission side base voltage, and Vdc is the back to back inverter dc link voltage. The effective sending end voltage VS eff, hence power, is controlled by adjusting the series voltage Vse, that is V S eff = V S +V se (20.82) The active power drawn by the series converter should equal the active power generated by the shunt converter (minus inverter and transformer losses) and vice versa, that is ℜ {−V sh I sh* +V se I L* } = 0 (20.83)

The unified power flow controller shown in figure 20.30a consists of a shunt and a series static synchronous compensator, where the two compensating inverters are connected back to back, and are decoupled by sharing a common dc link energy storage element (inductor or capacitor). As such, the two converters can operate independently, giving a versatile compensator that can simultaneously perform the function of either or both of the static synchronous series and shunt compensators, namely • Active power flow • Reactive power flow • Voltage magnitude control • Voltage harmonic elimination (active power filtering, see section 20.2.8) • Current harmonic elimination (active power filtering, see section 20.2.8) The shunt compensator provides • voltage regulation at the point of connection by injecting reactive power into the line and • balance of the real power exchanged between the two compensators when providing for inverter and transformer losses and any real power transferred by the series compensator. The series compensator is used to • control the real and reactive power by injecting a controllable magnitude and phase compensating voltage in series with the line. The UPFC thereby fulfils the functions of reactive shunt compensation, active and reactive series compensation, and phase shifting. Additionally, the UPFC can provide transient stability control by suppressing system oscillations. As shown in figure 20.30, the UPFC can control simultaneously the three parameter associated with line power flow (line impedance, voltage, and phase angle). The UPFC is connected at either the sending or the terminal points of the distribution/transmission system. VS

VS eff

Vse

I

Series connected transformer nse:1

Ish shunt step-down transformer

IL

Transmission line

Ise

+VSEmax

PSE IDC

+VSE

θshunt + C

VS eff

VDC

Vse

VS-VSE

VS

PSH

VSI shunt

I

VSI series

V se

δT –δS eff

I

-VSEmax

VS eff P Qs eff

XL

P VT QT

VS eff *

+V I se

*

L

VS+VSE VS

+VSE +VSEmax

VS VS+VSE

+VSE

IL +VSE

(c) (b)

P of C

ℜ {−Vsh I sh

VS-VSE

+VSEmax

VS+VSE

-VSE

Xsh VS

+VSE

IL

IL Ish

+VSEmax

VS

-VSE

VS

(a) Vse

Xse

-VSEmax

VS-VSE

mSE, θSE

VS

Vsh

-VSE

-VSE +VSE

VSI limit

jIXL VT

mSH, θSH

-VSEmax

VS+VSE

nsh:1

Is

Because line energy can be transferred readily between both converters in compensating for converter and transformer losses, the dc-link capacitor can be small, yet be maintained at the necessary rated link voltage. A consequence of the back-to-back connection is that the dc-link capacitor decouples the two converters and the shunt and series converter reactive powers can be controlled independently. Both converters can provide reactive power, and power for the series converter can be provided through the shunt converter. Because the series converter can now provide (and absorb) real power, the injected shunt voltage magnitude and relative phase are unrestricted, within the I-V limits of the two inverters. This is shown by the circle in the phasor diagram in figure 20.30c, where unlike for the DVR, as shown in the phasor diagram in figure 20.21c, the line current IL and the series compensation voltage Vse are not restricted to be at quadrature (that is, real power transfer can be involved with UPFC operation).

VT

XL

922

FACTS

VT

}=0

Figure 20.30. Unified power flow controller - UPFC: (a) single line diagram of the UPFC showing decoupled back to back connected inverters and matching transformers; (b) UPFC equivalent circuit; and (c) phasor diagram for system voltages and line current, IL.

Figure 20.31. Phasor diagrams for the UPFC series operating modes.

The series converter can be operated in any of four modes: • Voltage regulation - figure 20.31a. The magnitude of the sending bus voltage VS is regulated (increased or decreased) by injecting a voltage VSE of maximum magnitude VSEmax, in phase (or out of phase) with VS, thus avoiding the need for a transformer tap changer. • Line compensation - figure 20.31b. Series reactive compensation is obtained by series injecting a voltage VSE of maximum magnitude VSEmax, orthogonal to the line current IL. The effective voltage across the line impedance XL is decreased (or increased) if the voltage VSE lags the current by 90° (or leads the current IL by 90°). • Phase angle regulation - figure 20.31c. The required phase shift is realized by injecting a voltage VSE of maximum magnitude VSEmax, that shifts the phase angle of VS by ±θ while keeping the magnitude of VS constant.

Power Electronics

923

•

Chapter 20

Power flow control - figure 20.31d. Unified simultaneous control of terminal voltage (figure 20.31a), line impedance (figure 20.31b), and phase angle (figure 20.31c) means the UPFC is able to perform multifunctional power flow control. The magnitude and the phase angle of the series injected voltage VSE is selected so as to produce a line current that results in the desired real and reactive power flow on the transmission line.

The complex conjugate of the complex power at the receiving end of the line is given by  V +V -V  S ∗ = P − jQ = VR*  S SE T  jX   After compensation, the real and reactive power flows between VS eff and VT are given by

V V V V P = S T sin δT + S eff T sin (δT − δ S eff ) = Po (δ ) + PSE (δ , δ S eff XL XL

QT = VT ×

V S eff cos (δT − δ S eff ) −VT

Q S eff = V S eff ×

XL

V S eff −VT cos (δT − δ S eff

Ish

VS-n

jXL

VT

VXR VT-n

VS eff

Vsh-n

V DVR

N

(20.84)

VS eff Ps-Pupfc Ps

)

(20.85)

)

PT

Vsh-n

δ Is

(P (δ , δ ) − P (δ ) ) + (Q (δ , δ ) − Q (δ )) 2

o

SE

o

2

V V  =  T SE max   XL 

δT=δ-φ

IT

VT-n

VS eff

φ

VT-n

δDVR

O

VXL

(a) (c)

N

If VS eff = 0 the real and reactive power of the uncompensated system result, as given by equations (20.6) and (20.8). The maximum P-Q compensation components, VTVSE max/XL, occur when δT - δSeff = ½π. The series DVR compensator can a voltage between 0 and VSEmax with a rotational angle between 0 and 360°. This circle can be defined by

VS-n

jXL

VDVR

VS-n

VDVR

δeff

N

Pupfc Pupfc

XL

SE

IT

VDVR

jXsh

)

V V + S eff T sin (δT − δ S eff ) = Qo (δ ) + Q SE (δ , δ S eff XL

924

FACTS VS eff

Vs

(b)

Figure 20.33. Unified power flow controller - UPFC: (a) single line diagram of the UPFC; (b) UPFC power flow diagram; and (c) phasor diagram for system voltages and line current, IT.

2

(20.86)

Figure 20.32 shows a series of loci of the reactive power Q demanded at the receiving bus versus the transmitted real power P as a function of the series voltage magnitude VSE and phase angle δSE at three different power angles δ, namely, δ = 0°, 45°, and 90°, with VS = VT = V, V2/XL = 1, and VTVSE max/XL = ½. Figure 20.32 shows that the UPFC can independently control real and reactive power flow at any transmission angle.

With the aid of the phasor diagram in figure 20.33c, the following power equations can be derived. The source grid VS delivered powers are PS = V S −n I T cos δ (20.87) Q S = V S −n I T sin δ The UPFC powers, from the phasor diagram in figure 20.33c are PUPFC = VDVR I T cos (δ DVR − δ ) (20.88) QUPFC = VDVR I T sin (δ DVR − δ ) The line inductance VAr is

Q XR = Q S eff − QT =

V XL2 = I T2 X L XL

(20.89)

Alternatively, using the phasor diagram in figure 20.33c, the terminal grid VT received powers are PT = VT −n I T cos (φ − δ ) (20.90) QT = VT −n I T sin (φ − δ )

δSE

Figure 20.32. Unified power flow controller – UPFC, P-Q relationship for a two-bus system for three power angles, δ = 0°, 45°, and 90°, with VS = VT = V, V2/XL = 1, and VTVSE max/XL = ½.

From equation (20.88) four modes of UPFC control can be deduced: • If δDVR = δ, no reactive power flow is contributed from or controlled by the series DVR, while maximum active power is contributed. • If δDVR is at quadrature to δ, the DVR acts as a phase shifter and controls the active power but the reactive power is at a maximum. • If δDVR is at quadrature to the line current IT, the active power flow is controlled with the DVR acting as a controllable series reactive element. • For other δDVR the UPFC becomes a combined phase shifter and variable series reactive compensator. An important feature of the UPFC is that any energy for compensation at 50/60Hz and/or for harmonic compensation, is drawn from the network as sinusoidal current. This is unlike when the energy for the dc-link capacitor is provided via a rectifier feed from the ac network, where the rectification process itself can produce substantial harmonic currents in the network. 20.10

If bidirectional transmission line power flow control is required, a shunt compensator is needed at the opposite line end to the UPFC. Therein lies the overlooked fundamental conceptual limitation of the UPFC. Ideally, shunt compensation is most effective at the line reactance midpoint, while series compensation is most effective at a transmission line end. With the UPFC, both forms of compensation, shunt STATCOM and series DVR, occur at the same single point of connection.

Combined Active and Passive Filters

The basic static synchronous compensators (shunt - STATCOM and series - DVR) can be used simultaneously for both 50/60Hz fundamental power quality improvement and control as well as for line harmonic filtering, by injecting current or voltage, as appropriate, at the PCC. In the harmonic filtering mode, the compensators basically inject anti-phase current and voltage harmonics. In order to do so, the PWM frequency of the compensator inverter must be at least twice that of the highest frequency harmonic to be cancelled.

Power Electronics

925

Chapter 20

926

FACTS

20.10.1 - Current compensation – shunt filtering

20.10.3 - Hybrid Arrangements

As shown in figure 20.34a, the static synchronous shunt compensator can be used to shunt inject equal but opposite magnitude harmonic compensating currents such that I S = I shunt + I L (20.91) The load current IL is non-linear, as with rectification for highly inductive loads. The compensator shunt injects a current Ishunt such that the supply current Is is a pure sinusoid at the fundamental frequency. The sending voltage source VL sees the transmission system as a purely resistive load, if STATCOM normal VAr compensation is also operational. The STATCOM output is second order L-C low pass filtered to prevent PWM carrier components from being injected into the ac system. A second order L-C high-pass shunt line filter is normally incorporate to cater for current frequency components at the modulation frequency and beyond the shunt compensator’s bandwidth. The high cut-off frequency, well beyond the power frequency, results in reduced size, as well as reduced possibility of resonant effects.

STATCOM-based hybrid arrangements can be used for both voltage regulation and load-compensation. STATCOMs are usually combined with SVCs or passive harmonics filters. While both provide improvement of compensation capabilities, the former are often used for voltage regulation, while the latter are utilised for load compensation. Additionally, in hybrid topologies the rated power of STATCOM constitutes a part of a hybrid controller’s rated power thus they allow the installation costs to be reduced. Shown in the parts of figure 20.35 are general topologies and V–I characteristics of STATCOM SVC hybrid arrangements. The parallel connected SVC part extends the current operating region of STATCOM. The combination of STATCOM and TSC (Figure 20.35a) extends the operating region towards the generation of reactive power (capacitive region). This property is important in practice, because it is often necessary in distribution systems to compensate inductive-type loads to provide terminal-voltage regulation. Extension of V–I characteristics of STATCOM towards absorption of reactive power (inductive region) is possible by paralleling it with TSR (figure 20.35b). The symmetrical extension of the V–I characteristics is provided by the hybrid arrangement shown in Figure 20.35c. In addition to improving V–I characteristics, a hybrid arrangement can be used to optimize losses, cost, and performance for a particular application.

VS

P of C

XS

VS

XL

I

XS

Vseries

XL

IL

Ishunt

ICmax

IL

IF

INL

Inductive load

Vshunt

IL

Vmax

IC t

t

ICmax

Inductive load

I

IL

t

L-C filter

t

Vs

Vs

Rectifier

Rectifier

Xsh

I

I

INL

ISTATCOM

BC

C

BC

Vseries+ Ifilter

I

STATCOM VS

XS

I

VS

XL

IL

t

XS

Vseries I

Ishunt

INL

Ishunt

Rectifier Inductive load

shunt step-down transformer

t

Series connected transformer

ITSRmax

XL

IL

IF

(a) shunt APF

ILmax

Vs

Rectifier

L-C filter

L-C filter

Inductive load

Vs

Vmax IL

C

VDC

BL

L

ISTATCOM

IDC

VSI

ILmax

INL

Iseries

VDC

max I statcom

0

(a)

IDC

C

max I statcom

BL I

STATCOM

VSI

I statcom max

(b)

I statcom max

0

ITSRmax

(b) series APF

Figure 20.34. Combined active and passive filters: (a) transformer voltage matched shunt APF and (b) transformer voltage matched series APF.

ICmax Vs

20.10.2 - Voltage compensation – series filtering As shown in figure 20.34b, the static synchronous series compensator can be used to series injects equal but opposite magnitude harmonic compensating voltages on the line such that V S = V series + VL (20.92) The load current IL and voltage VL are both non-linear, since the non-linear current associated with the rectification of highly inductive loads produces non-sinusoidal voltages across the series line inductance, normally around the peaks and troughs of the three-phase sine-waves. The compensator series injects a voltage Vseries such that the sinusoidal supply voltage Vs delivers a more sinusoidal current into the transmission line. Since the loads still draws a non-linear current, passive notch-shunt and high-pass shunt second order L-C filtering are needed to provide a bypass path for the current harmonics. The series compensator output is second order L-C low pass filtered to prevent PWM carrier components from being injected into the ac system.

ILmax

Vs

ISTATCOM

IL

IC L

C

BL

BC

I

STATCOM (c)

ITSRmax

I statcom max

I statcom max

ITSRmax

Figure 20.35. Combined STATCOM and thyristor and static controller and hybrid I-V characteristics: (a) STATCOM and TSC; (b) STATCOM and TSR; and (c) STATCOM plus TSR and TSC.

Power Electronics

927

Chapter 20

20.10.4 - Active and passive combination filtering All effective active filtering relies on the addition of passive filtering, even if only to filter compensator inverter pwm outputs. Semiconductor voltage ratings usually prevent the direct coupling of the compensator inverter to the ac grid. At 50/60Hz, transformer coupling provides a simple and efficient interface method. But for active filtering application, the coupling transformer must have sufficient bandwidth to transmit the necessary compensating harmonic components. Normal 0.3mm silicon steel laminated transformer cores produce transformers suitable for compensation of the 5th and 7th harmonics, but attenuation at the 12th and 13th harmonics results in the inverter dc-link voltage being ineffectively utilised. Special steels (higher silicon) and thinner laminations (0.1mm and 0.05mm) cater for higher frequency operation but as well as being more costly, maximum flux density levels are decreased and core losses are increased. High permeability, amorphous metal-based soft magnetic materials offer modest high frequency losses with high flux densities properties, but are expensive. Indirect filtering methods involving the normal 0.3mm 50/60Hz steels may therefore be preferred.

FACTS

In the case of ac transmission, transformerless series power filtering is possible since lower voltages are normally involved, but usually a separate isolated single-phase inverter is needed in each phase. The inverter default mode is to operate with all (upper or lower) switches on so that the series compensator is seen as a short circuit. 20.11

Summary of Compensator Comparison and Features

FACTS devices enhance high-voltage ac-grids by:

• • • • • • •

I IL t

t dc blocking capacitor

VS

XS

I

P of C

IL

+

XL

Idc

½Ldc

Cdc -

INL

Vseries+ Ifilter

Rectifier

Lsh

Inductive load

Csh

High pass L-C filter

t

C VSI

IDC

Controlled 12 pulse converter

½Ldc Ihar

Controlled 12 pulse converter

C

VDC VSI Single-phase

VDC

IDC

(a) ac APF (b) dc APF Figure 20.36. Combined transformerless active and passive power filters: (a) 50/60Hz ac decoupled shunt APF method and (b) dc decoupled shunt APF approach.

Figure 20.36 shows indirect filter coupling methods suitable for dc and ac lines where the active filter is dc or 50/60Hz decoupled to the transmission system. The series filter (Lsh//Csh and Cdc) supports the system voltage while the inverter experiences only its own low dc-link voltage. The method is effective for ac but has limitations: • the passive decoupling filter characteristics drift in time, namely the notch frequency and Q; • the large size and weight of the filter inductor, being based on 50/60Hz design concepts; and • the inverter is only capable of harmonic compensation without VAr compensation since the 50/60Hz decoupling filter blocks any transfer at the 50/60Hz line transmission frequency. For VAr compensation, the inverter fundamental output voltage must be of a similar magnitude as the line voltage, hence the use of a voltage-matching transformer. These ac limitations are not relevant to dc-link filtering since dc decoupling capacitor aging characteristics do not affect the block frequency, being dc (VAr compensation is not relevant to dc systems). A single-phase inverter bridge is used for dc-link harmonic compensation. Although the dc-link current harmonics at 12n can be cancelled (in a symmetrically triggered 12-pulse system), cancellation of the 11th and 13th order (12n±1) ac side current harmonics is more problematic since the rectifying process does not necessarily ensure harmonic current flow in the correct rectifier leg. This is problematic with 12-pulse (and >12) converters.

928

increase of power transfer without adding new transmission lines transmission cost minimization steady-state and dynamic voltage control reactive power control of dynamic loads active damping of power oscillations increase of reliability under system contingencies improvement of system stability and voltage quality high flexibility for embedding of various energy sources

A shunt compensator acts like a controllable current source and can draw or inject reactive leading or lagging current at the point of connection. Objectives of dynamic shunt compensation are • steady state and transient voltage control • Reactive power control of transient loads • Damping of active power oscillations • Increase of system stability A series compensator is a driving voltage at the line reactance midpoint, hence is more effective than a shunt compensator for controlling current and power flow, and for damping oscillations. It can only supply or absorb reactive power. When used as a phase angle controller, at the sending or receiving ends, a real power source is required. Objectives of dynamic series compensation are • Reduction of load dependent voltage drops • Reduction of system transfer impedance • Reduction of transmission angle • Increase of system stability • Load flow control to specific power branches • Damping of active power oscillations Two points to bear in mind when transformer coupling compensation FACTS type devices. • The transformer core must be able to transmit at the highest harmonic frequency. • Series coupling into a dc link imposes a dc bias current, hence flux in the coupling core. 20.12

Summary of the Advantages of AC Transmission over DC Transmission

The general advantages of ac transmission, over dc transmission, are • No costs associated with ac-dc-ac conversion equipment • Transformer (and autotransformer) voltage matching • Reactive power and harmonics readily compensated • Not restricted to only point-to-point connection, as is HVDC (there is one exception) • Established system control methods • No ac transformer dc voltage stressing due to asymmetrical phase control alignment, and no I2R and core losses due to high harmonic currents • ac switch gear and breakers, (and particularly vacuum circuit breakers up to 33kV) are very effective - compared with the difficulties in breaking dc current • Lower current harmonics Reading list Mohan, N., Power Electronics, 3rd Edition, Wiley International, 2003. Acha, E., et al., Power Electronic Control in Electrical Systems, Newes, 2002.

Chapter 21

930

Inverter Grid Connection for Embedded Generation

Another configuration normally adopted for supplying power to sensitive electrical load demand is to use DG in conjunction with a UPS unit. A UPS system normally incorporates an energy storage medium such as batteries to enable power supply continuity as well as improve power quality and reduce the influence of voltage surges, spikes and swells which could cause loss of production.

CHAPTER

21


Once the interconnection is established the hosting utility assumes responsibility of DG operation and contribution and treats it as part of its generation system. Current DG/distribution network interconnected systems practice is to revert the distribution network to its original configuration (radial or meshed distribution system) with all interconnected DG units deenergized whenever an unexpected disturbance occurs in the system. Since most distribution systems comprise radial feeders, this leads to the supply discontinuation for all the down-line customers. In this way the DG contribution is restricted to the hosting utility demand and conditions. AC Micro-grid architecture

Microturbine Generator set (ac)

Fuel cell inverter (dc-ac)

Micro-hydro (ac)

Wind turbine (ac)

Battery storage

inverter (dc-ac)

load

load

load load

PV array inverter (dc-ac)

AC Filters and FACTS compensators

load Diesel gen-set (ac)

PCC Point of Common Coupling

Optional interconnect

Distributed Generation (DG, or embedded generation) is a back-up electric power generating unit at or near the consumer premises that primarily is used by the energy user to provide emergency power when grid-connected power is unavailable. Installation of the back-up unit close to the demand centre avoids the cost of transmitting the power and the associated transmission losses. Back-up generating units are currently defined as distributed generation to differentiate from the traditional centralized power generation model. Although the centralized power generation model is economical and a reliable source of energy production, the lack of significant increase in new build generating capacity or even in expanding existing ones to meet the needs of current demand, presents a challenge to the electrical power industry, needing a solution. 21.1

Distributed generation

A typical DG energy conversion system is comprises two main energy converting stages. The first stage is the prime fuel converting block in which the prime fuel internal energy is converted into mechanical energy, as in the case of internal combustion engines. The second stage converts the mechanical energy into electrical power using an electromechanical energy conversion device such as synchronous alternator or induction generator, which produces AC power. Another way of converting prime fuel source into electrical energy is through a chemical or photosynthesis conversion process. Fuel cells and photovoltaic solar energy converter are examples that produce DC power. The interfacing unit is essential to convert the produced DC source into harmonized constant voltage and frequency AC power source. A DC to AC power electronic inverter system is used as the interfacing unit. The inverter must produce high quality AC power with a voltage waveform of limited supply frequency fluctuation and low THD at the point of common coupling (PCC), in accordance with the appropriate standard. The inverter must be capable of preventing the DG from islanding (anti-islanding capability) on the hosting grid. Islanding is a condition occurring when a generator or an inverter and a portion of the grid system separates from the remainder of the large distribution system and continues to operate in an energized state. Islanding may pose a safety threat or cause equipment problems; therefore cannot be permitted without system coordination. The inverter output produced must comply with hosting grid electricity voltage and frequency standards. A coupling transformer is needed to interface the DG generator with the grid to match the distribution voltage level at the point of connection. Only when it is safe and synchronised conditions exist is the DG interconnected with the permission and coordination of the grid operator.

BWW

PCC

EPS

Utility Electric Power System

Figure 21.1. AC microgrid architectural structure.

21.1.1 DG Possibilities DG is attractive for the following opportunities: • DG can be fuelled by locally available renewable and alternative mix of fuel sources to meet current energy demand. Renewable sources are wind and solar, while alternative fuels are those produced from waste products or biomass and can be in gas, liquid or solid form. Greater independency from importing petroleum fuel can be achieved by incorporating DG that are powered by various fuel sources; • DG can support the projected increase in demand, without investment in the expansion of existing distribution network, by installing the DG close to a new load centre; • Installing DG within the industrial/commercial premises avoids negotiating land use and the need for rights-of-way for electric transmission and distribution, thereby minimizing further capital investment; • DG can be used in reducing intermittent and peak supply burdens on utilities grid by injecting power as required by the controller; • DG has the ability to support the existing energy supply when needed and in a short time (black start) without incurring capital cost; • DG penetration in the energy market will create overall competitive pricing of energy. The current DG generation rate ($/kWh) is competitive with the centralized generation system as more efficient fuel energy conversion units such as fuel cells and micro turbines are continuously improved and diversified; • DG can decrease the vulnerability of the electric distribution system to external threats and hidden undetected faults that may cause blackout by feeding power to the sensitive infrastructure;

Power Electronics

DG is flexible, being capability of being configured to operate in a stand-by mode, isolated mode, or sharing the load through integration with the electric grid.

Using DG that is fuelled by various prime alternative fuel sources will reduced fossil fuel consumption hence reduce CO2 emissions. DC Micro-grid architecture

dc load

Wind turbine (ac-dc)

Grounding. Protective grounding is mainly designed to protect the operator. Grounding could also contribute to reducing the magnitude of transient over-voltages and lightning protection. Grounding components must be capable of carrying the maximum available fault current and withstanding a second strike within a few cycles after the first. Grounding cables must be connected directly to the equipment. No impedance, circuit breaker or measuring devices, etc., are permitted between the grounding cable and the equipment.

dc load

Fuel cell smps (dc-dc)

Optional interconnect

Micro-hydro (ac-dc)

PCC

EPS

DC to AC inversion

Microturbine Generator set (ac-dc)


VAr compensator

PV array smps (dc-dc)

Figure 21.2. DC microgrid architectural structure.

Battery storage

smps (dc-dc)

Diesel gen-set (ac-dc)

Fuel cell smps (dc-dc)

Microturbine Generator set (ac-dc)

DG protection relay controller

ac load Optional interconnect

Independent Power Producer PCC

EPS

DC to AC inversion

PV array smps (dc-dc)

Dispatch, communication, and control. These integration and communication components interface the DG units with the utility. Their functions include: • Regional load management, work order management, and billing services; • Distribution automation; • Feeder switching; • Short circuit analysis; • Voltage profile calculations and trouble calls management.

Protection relay controller

PT

DG

ac load

Micro-hydro (ac-dc)

Metering and monitoring. Monitored parameters can include current, voltage, real and reactive power, oil temperature, vibration, etc. Metered parameters also include power output, which may be used for billing that requires utility-grade metering accuracy.

DC – centralised AC Micro-grid architecture DC voltage bus link

Wind turbine (ac-dc)

DC injection level. Under abnormal operating conditions, grid tie inverters could inject low level DC current into the hosting grid. Similarly, transformer-less grid-tie inverters may inject DC current into the grid. It is part of the inverter feedback loop to detect the presence of the DC component and adjust the triggering sequence to the switching devices to remedy the situation. A coupling transformer could be used to isolate the DC current from flowing to the AC side. A low cost solution is to incorporate a DC detection device to disconnect the inverter in case of severe DC level injection.

VAr compensator


PT

utility disconnect

EPS

CT CT

PCC

CT CT

50

PT

metering

DG/utility disconnect

Diesel gen-set (ac-dc)

smps (dc-dc)

Voltage and frequency tolerance. For high quality power injection, both the voltage and frequency margins should not exceed the grid tolerance specification. Both voltage and frequency detection is part of the anti-islanding protection control.

Local load protection

Battery storage

932


Local load

•

Chapter 21

Generator protection switchgear

931


Figure 21.3. DC – centralised ac microgrid architectural structure.

Figure 21.4. DG-utility interconnection protection requirements.

21.1.2 Integration and Interconnection Requirements Key elements for the reliability of distributed generation power systems are the performance of the electrical switchgear, interconnection, controls, and communication features. The main components of interconnection according to the protection functions they perform are categorized as follows:

A typical interconnection line schematic with the protection elements between the DG and the hosting grid is shown in Figure 21.4. Typical minimum DG/utilities interconnection protection relay requirements are: • The DG protective switchgear should include an over/under voltage trip function, an over/under frequency trip function, and a means for disconnecting the DG from the utility when a protective function initiates a trip; • The DG and associated protective switchgear must not contribute to the formation of an unintended island; • DG switchgear must be equipped with automatic means to prevent DB reconnection with the utility distribution system unless the distribution system service voltage and frequency is of specified settings and is stable for specified time, typically 60s; • Circuit breakers or other interrupting devices at the PCC must be capable of interrupting the maximum available fault current.

Synchronization. Automatic sensing of the voltage and frequency can achieve fast interconnection to the hosting grid. Islanding. Islanding protection is a mandatory feature that the hosting grid requires from the DG operator. Islanding on part of the hosting network could jeopardize the maintenance crew safety and causes malfunction of nearby coordinated protection units. Relays are normally used to provide protection at both the grid and the DG end of the connection. DG inverters should incorporated built-in features to disconnect from the hosting grid once anti-islanding conditions are violated.

933

Power Electronics

21.2

Chapter 21

Interfacing conversion methods

Fuel cell and reformer

A common feature of embedded generation interfacing is voltage translation and stabilisation using the boost converter concept. The boost converter is used since its input current can be continuous thus drawing continuous energy from the energy source, for maximum source energy extraction efficiency. Fuel cell and reformer

dc to dc converter

dc to dc converter

dc to dc isolated hf converter

a n b

50/60Hz transformer

934


a n b

dc to ac PWM inverter

battery

fuel cell output 20 to 44Vdc

20kHz isolation dc to dc step-up converter

dc link filter

dc link and 20kHz PWM 1kHz cut-off 115/230V ac 48V battery storage 115V/230V ac LC filter 50/60Hz dc to ac inverter output voltage

battery

fuel cell output 20 to 44Vdc

dc to dc boost converter

dc link and 48V battery storage

20kHz PWM dc to ac inverter

LC filter 1kHz cut-off

line frequency isolation step-up transformer

115/230V ac 50/60Hz output voltage

Spp1

+ VFC

Lcm

Cdc

+ Cdc

D1-4

+

LB

DB

+

Cdc

Lf1

S1 S3

Vdc

Cf

Spp2

1:n:n

1:n

Lf

S1 S3

a

Vdc Vdc

Lf

Lcm

S2 S4

b Cf

Cf

a

n n

+ VFC

SB

Lf2

Figure 21.7. Dc to line frequency power conditioner with high frequency isolation and two power conversion stages: (a) block diagram and (b) circuit topology.

b

S2 S4

Figure 21.5. Dc to line frequency power conditioner: (a) block diagram and (b) circuit topology. ac utility input

Fuel cell and reformer

dc to dc converter

dc to ac isolated converter


SSB

a n b

three-phase load

SSA

battery

fuel cell output dc to dc 20 to 44Vdc boost converter

dc link and 48V battery storage

20kHz isolation dc to dc step-up converter

dc link filter

20kHz PWM 1kHz cut-off 115/230V ac dc to ac inverter LC filter 50/60Hz output voltage

hydrogen storage H2

PEFC fuel cells


ac isolation and voltage matching 1:n

Figure 21.8. Modular fuel cell power conversion system supplying a three phase load in parallel with the grid, via solid state circuit breaker for source isolation and islanding.

LB

Spp1

DB Cdc

Vdc

Lcm

+

Cdc

S1 S3

+ VFC

Lf

a

Lf

SB Spp2

1:n

Lcm

S2 S4

b Cf

Cf n

Figure 21.6. Dc to line frequency power conditioner with high frequency isolation: (a) block diagram and (b) circuit topology.

935

Power Electronics

Chapter 21

blank non-critical three-phase load

ac utility input

SSB

critical three-phase load

SSA

PEFC fuel cells

dc to dc hf converter

PEFC fuel cells

dc to dc hf converter

hydrogen storage H2

supercapacitor


bidirectional converter

Figure 21.9. Modular fuel cell power conversion system for grid connection with supply backup for critical loads.

Micro turbine generator

active ac to dc

converter

heat by-product for cogeneration

hydrogen storage H2

Vdc high temperature

fuel cell

dc to dc converter

+ Cdc

dc to three phase

ac inverter

three-phase 50/60Hz ac grid a b

Figure 21.10. Modular fuel cell power conversion system for three-phase grid connection, with cogeneration on to a common dc link.

Reading list

c


936

Chapter 22

CHAPTER

938

Primary Energy Sources

Thus, in summary, the specific energy of pure hydrogen (the energy per kilogram) is higher than any other fuel at better than 120 MJ/kg. However, its energy density (energy per m3) is very low, that is, it is difficult to get a large mass of hydrogen into a small volume, as shown in table 22.2. Cryo-adsorption of hydrogen into graphite at low temperature and pressures up to 5MPa, or the use of metal hydrides, provide higher hydrogen storage densities, as shown in table 22.2b. Table 22.1, in conjunction with figure 22.1, show that both batteries and super capacitors fall significantly short of the energy that can be released from hydrocarbons, on an equivalent volume and weight basis.

22

Table 22.1: Energy properties of hydrocarbons and alternative energy sources

Energy Sources and Storage -

Fuel Type

Fuel

solid

charcoal

Primary Sources

The progressive proliferation of embedded and distributed generation with renewable energy sources has spurred research into alternative energy sources and storage methods. Although this chapter is mainly concerned with primary sources, namely fuel cells and photovoltaic cells, their energy and power density capabilities can only be put into context by considering conventional energy sources, specifically, the hydrocarbons. In electrical terms, primary and secondary energy sources are defined as follows. Primary source is not a reversible energy source. During energy discharging, the original states are permanently changed as electrical energy is released until the original energy reactants, or any one of them, are depleted. A primary cell can be used only once. Secondary source is reversible and the original states can be reconstituted by the application of an electrical potential which injects energy into the source. A secondary cell can source and sink energy many times. 22.1

Hydrocarbon attributes

Table 22.1 shows that the energy density associated with the hydrocarbons dwarfs all other common sources such as batteries and supercapacitors. The table highlights why petrol is so firmly entrenched, while the limitations of hydrogen are made apparent. Although hydrogen offers 3 times more energy than petrol for a giving reactant weight, its volume per kg is grossly in excess of that of petrol. One mole of hydrogen H2 occupies 22.4 litres and weight just 2 grams. Thus the energy per unit volume for petrol is 2500 times more than that for hydrogen. Table 10.2a presents the basic properties of hydrogen. Pressurising hydrogen mitigates the volume limitation somewhat, but liquefaction is at an impractical temperature of 20K, with a density of 0.07g/cm3 (only helium has a lower boiling point). Pressure helps minimally since the boiling point rises to only 43K at 13 bar, with minimal temperature increase for higher pressures. On the other hand, propane has a boiling point of -42°C, but can be liquefied at 21°C and 13bar, with a gain in energy density. The expansion ratio for hydrogen is 1:850, that is, at atmospheric temperature and pressure, hydrogen gas occupies 850 times the volume as in its liquid state. The ratio is 1:240 at 250 bar and atmospheric temperature, but cannot approach the liquid ratio at much higher pressures, as shown in Table 22.2b. Basically, hydrogen has a poor molecular packing density. A cubic metre of water contains 111kg of hydrogen, whereas a cubic metre of liquid hydrogen contains only 71kg of hydrogen. In fact, water (111kg) contains more kg/m3 of hydrogen that methanol (100kg) and a similar weight of hydrogen as in heptane (113kg). The energy stored, in Joules, is given by mass times specific energy (calorific value).

BWW

kg/kWh

gas

Density 3

3

kWh/kg

MJ/Litre

MJ/m

30

10

-

6250

208

-

25

8

-

37500

1500

-

wood

16

5.4

-

8000

400-700

-

dung cake

7

2.3

-

5000

700

-

48

15

35

44000

820

0.73

kerosene

0.32

0.27

kg/m

Litres/kg

petrol

50

16

48

37000

751

1.36

diesel

45

15

39

38200

850

1.19

ethanol

30

10

30

23700

789

1.00

bio gas

38

12

46

1.2

butane(LPG)

0.23

50

16

29

30000

600

50

16

29

125

2.5

methane

55

18

0.9kJ/mol

39

0.668

hydrogen

150

49

13

0.0838

butane gas

battery

Calorific Value MJ/kg

coal

liquid

CO2

Lithium-ion

0

0.2

Lead acid

0

0.04

capacitor

double layer

0

0.02

fuel cell

hydrogen

0

26

PV cell

1.72

0

Flywheel

FES

0

0.13

fusion

U235

0

2.5×107

Table 22.2a: Hydrogen; high gravimetric energy density but low volumetric energy density Hydrogen property

unit

value

relative atomic mass

u

1.00794

density

kg/Nm3

0.0899

specific HHV energy

MJ/kg

142.0

specific LHV energy

MJ/kg

120.0

HHV energy density

MJ/Nm3

11.7

LHV energy density

MJ/Nm3

9.9

boiling point

K (°C)

20.268 (–252.88)

melting point

K (°C)

14.025 (–259.13)

critical point

K (°C)

33.250 (–239.90)

Power Electronics

Chapter 22

Form of hydrogen Storage 120 MJ/kg

Energy density by weight kWh/kg

Energy density by volume kWh/l

gas

20 MPa

33.3

0.53

gas

24.8 MPa

33.3

0.64

gas

30 MPa

33.3

0.75

liquid

-253°C

33.3

2.36

Hydrogen

metal hydride

0.58

3.18

U235

2.5×107

4.7×109

fusion

Comparisons The Ragone plot in figure 22.1 shows the energy storage and power handling capacity of some alternative storage techniques. Energy and power densities, in steady-state, are related by Energy = Power × time.

8

10

7

10

6

10

5

10

4

10

3

10

2

10

1

SMES flywheels Super capacitors

Redox-flow & reversible fuel cells

compressors

power batteries

Energy batteries

100 101 102 103 104 105 106 107 108 109 1010 energy

Watt-hours

W h/kg

1h

10 h

100 h

6 min

fuel cells

102

36s

360ms

3.6s

IC gas turbine

batteries Energy density

10

S

9

Hydro & large compressed air

U P

10

we ek ly st or Se ag as e on al st or ag e

Power

Watts

103

36ms

flywheel

101

3.6ms

double layer capacitors

100

super conductor magnetic

10-1

(ii) At the oxygen electrode - cathode Meanwhile, oxygen molecules O2 are diffusing through to the catalytic surface of the cathode electrode which facilitates the separation of the adsorbed oxygen molecule (oxygen bonds are broken) into oxygen atoms which are held momentarily in a receptive state on the active catalyst. The entering electrons diverted externally from the anode bypassing the electrolyte, the oxidant, and cathode electrode together causes another reaction to occur where negative ions and products are produced. If H+ ions are the free moving ions (because of the acid electrolyte used), they are attracted to the negative ions generated at the cathode and conduct through the acid electrolyte and product 2H2O, along with heat. If however, H+ ions are not able to travel through the electrolyte, then the cathode produced free moving negative ions move through the alkali electrolyte to combine with the H+ ions to complete the process at the anode. (iii) Through the electrolyte medium The electronically-insulated (does not conduct free electrons) electrolyte serves as the physical barrier preventing the fuel and oxidant gas streams from directly mixing allowing, only the appropriate ions to move freely through the layer. This requires that one of the reactants must be able to form the ionized specie needed to complete the process and form the primary by-product, water. Fuel cells that use hydrogen can be thought of as an electrochemical devices that perform the reverse of electrolysis, where passing an electric current through water splits it up into hydrogen and oxygen. In the fuel cell, hydrogen and oxygen are joined together to produce water and electricity. Although the majority of fuel cells use hydrogen as the fuel, some fuel cells work off methane, and a few use liquid fuels such as methanol.

capacitors

H2

H2

10-2 0

10

1

10

2

10

3

10

Power density

4

10

5

10

6

10

anode (-)

7

10

W/kg

Figure 22.1. Gravimetric energy and power densities of common energy sources.

anode (-)

catalyst acid electrolyte

cations

catalyst

H2O

cathode (+)

22.2

electrons

Energy carrier

940


(i) At the hydrogen electrode - anode The reaction at the anode involves the release of electrons from the hydrogen fuel that will then be conducted by the electrode to the electrical load. The hydrogen arrives at the anode as a diatomic gas 2H2 where each adsorbed hydrogen molecule ionizes into four hydrogen protons, H+ and four electrons, e-. The rate of this process is increased with the aid of a catalyst. Because the chemical reaction at this electrode produces positive ions, it is the anode. The negatively charged electrons are then forced to flow from the conductive electrode (anode) to an external electrical load before reentering the fuel cell at the cathode (that is, electrons diffuse naturally from a high concentration to a low concentration of electrons). However, the hydrogen ions may or may not conduct through the electrolyte since this depends on the pH and type of electrolyte used, meaning the hydrogen ions may have to temporarily remain at the anode in a receptive state.

Table 22.2b: Hydrogen; high gravimetric energy density but low volumetric energy density

electrons

939

H2O

catalyst base electrolyte

anions

catalyst cathode (+)

The fuel cell

The fuel cell is similar to a battery, in function and appearance. It produces electricity directly, using chemicals. A fuel cell is a solid-state electrochemical device that consists of two electrodes, an anode and cathode, sandwiched around an electrolyte, with a catalyst membrane between each electrode and the electrolyte, which enhances ionization of the fuel molecules. The oxidant oxygen, usually from air, passes over the cathode electrode and typically hydrogen fuel over the anode, generating electricity, and water and heat by-products. An ion-conducting membrane separates the anode and cathode, allowing the reaction to take place without affecting the electrodes. The fuel cell relies on a basic oxidation/reduction reaction, as with a battery, but the reaction takes place on the fuel rather than on the electrodes. As long as fuel is supplied and oxidized old fuel is disposed of, the cell will continue to generate energy, both electrical power and heat. Since conversion of the fuel to energy takes place via an electrochemical process, not combustion, the process is clean - no CO2, quiet and highly efficient - two to three times more efficient than fuel combustion. How the fuel cell operates The fuel cell process can be divided into three stages; two of these stages involve the chemical reactions at each electrode and the third is ion conduction through the electrolyte.

O2

(a)

(b)

O2

Figure 22.2. Pictorial representation of a fuel cell with electrolyte conduction of: (a) cations and (b) anions.

Two basic ion operating mechanism are possible. The first involves cations passing through an acid electrolytic membrane from anode to cathode, while the second mechanism involves anions passing through an alkali membrane in the opposite direction, namely from the cathode to the anode. The ion conducting membrane is non-conducting to electrons. •

Cation conduction: Pressurised hydrogen H2 gas fuel is fed into the anode of the fuel cell. The pressure forces the H2 through the catalyst. When an H2 molecule comes in contact with the platinum catalyst, it splits into two H+ ions (protons) and two electrons e-, which take different paths to the cathode. The catalyst increases the rate of this splitting process. The electrolyte membrane does not pass electrons. The electrons conduct externally from the anode, creating a current that can be utilized in an external circuit, then return to the cathode-side of the fuel cell where they are reunited with the hydrogen plus oxygen ions forming a molecule of water, as illustrated in figure 22.2a.

941

Power Electronics

Meanwhile, on the cathode-side of the fuel cell, oxygen gas O2 (or air) is being forced through the catalyst, where it is encouraged to form two oxygen atoms. Each of these atoms has a strong negative charge. This negative charge attracts two H+ ions, protons, at the anode side through the membrane, where they combine with an oxygen atom and two of the electrons from the external circuit to form a water molecule H2O, plus heat energy. •

Anion conduction: The operating principle of an anion conducting cell is illustrated in Figure 22.2b. Oxygen supplied at the cathode (air electrode) reacts with incoming electrons from the external circuit to form oxide ions, which migrate to the anode (fuel electrode) through the anion conducting electrolyte. At the anode, anions combine with hydrogen ions (and/or carbon monoxide) in the fuel to form water (and/or carbon dioxide), liberating electrons. Electrons (electricity) flow from the anode through the external circuit to the cathode.

In principle, fuel cells can operate on many reactant combinations but most fuel cells actually operate on a narrow range of fuels in combination with oxygen from the air. As considered in section 22.9, fuels range from pure hydrogen gas, liquid alcohols and other liquid or gaseous hydrocarbons to metals and solid carbon. For the fuel cell types restricted to operating only on pure hydrogen, it is necessary to involve systems that generate hydrogen. Electrolysis and fuel reforming technologies generate hydrogen, but storage at useful energy densities is problematic. Several types of fuel cell can be operated directly on readily available fuels such as methanol, ethanol and natural gas, thereby dispensing with the infrastructure issues of hydrogen. Traditionally these fuels come predominantly from fossil sources, but they are also increasingly available from renewable bio-sources. Since the fuel cell relies on electro-chemistry and not combustion, emissions are smaller than emissions from the cleanest fuel combustion processes. Fuel cells can be made in a wide range of sizes, from a few watts to MW. The potential power generated by a fuel cell stack depends on the number and size of the individual fuel cells that comprise the stack and the surface area of the membrane. Since the single fuel cell produces only about 0.7V, many separate fuel cells must be series connected to form a high-voltage fuel-cell stack. Bipolar plates are used to judiciously connect one fuel cell to another and are subjected to both oxidizing and reducing conditions and potentials. An issue with bipolar plates is stability. Metallic bipolar plates corrode, and the by-products of corrosion (iron and chromium ions) decrease the effectiveness of fuel cell membranes and electrodes. Low-temperature fuel cells use lightweight metals, graphite, and carbon plus high temperature thermoset composites, as bipolar plate material. The fuel cell offers a unique combination of benefits. In addition to low or zero emissions, benefits include high efficiency and reliability, multi-fuel capability, siting flexibility, durability, scalability and ease of maintenance. Fuel cells operate silently, so they reduce noise pollution as well as air pollution and the waste heat from a fuel cell can be used to provide domestic hot water or space heating. There are several different types of fuel cells, each using a different chemistry. Fuel cells are usually classified by their operating temperature and the type of electrolyte used. The materials for the cell components are selected based on suitable electrical conducting properties required of these components to perform their intended cell functions: • adequate chemical and structural stability at high temperatures encountered during cell operation as well as during cell fabrication; • minimal reactivity and interdiffusion among different components; and • matching thermal expansion among different components. 22.3

Materials and cell design

Like the battery, the fuel cell has few component parts although the materials may be sophisticated, involving rare earth transitional metals, high temperature composite ceramics, cermets, etc. The basic fuel cell component parts are: • Electrodes; • Catalysts; • Electrolyte; • Interconnects; and their • Stack construction. 22.3.1 Electrodes Fuel cell electrodes serve three functions: • To ensure a stable interface between the reactant gas and the electrolyte; • To catalyze the electrode reactions; and • To conduct electrons from or to the reaction sites

Chapter 22


942

An electrode forms part of the three-phase boundary, where the electrolyte, electrode, and gas all come together. i. Cathode The cathode is the positive electrode of the fuel cell because it is the electrode where negative ions are produced. It has etched channels that distribute the oxygen to the surface of the catalyst. It also conducts the electrons received from the external circuit to the catalyst, where they can recombine with the hydrogen ions and oxygen to form water. An integral part of the cathode is the metallic interconnect, a bipolar plate, which forms an integral part of the anode of the adjacent cell, when cells are series connected to give higher voltage output. The oxidant gas is air or oxygen at the cathode, and the electrochemical reduction of oxygen requires a series of elementary reactions and involves the receipt of multiple electrons. The cathode must meet the requirements of: • high catalytic activity and high surface area for oxygen molecule dissociation and oxygen reduction; • high electronic conductivity; • chemical and dimensional stability in environments encountered during cell fabrication and cell operation; • thermal expansion match with other cell components; • compatibility and minimum reactivity with the electrolyte and the interconnection; and • must have a stable, porous microstructure so that gaseous oxygen can readily diffuse through the cathode to the cathode/electrolyte interface. ii. Anode The anode is the negative electrode of the fuel cell because it is the electrode where positive ions are produced. It conducts away the electrons that are released from the hydrogen molecules so that they can be used in an external electrical circuit. An integral part of the anode is the metallic interconnect, a bipolar plate, which form parts of the cathode of an adjacent series cell. It has channels etched into it that disperse the hydrogen gas uniformly over the surface of the catalyst. The properties of the anode must include: • an excellent catalyst (in the case of high temperature fuel cells) with a large surface area for the oxidation of fuel (hydrogen, carbon monoxide); • stable in the reducing environment of the fuel; • electronically conducting; • have sufficient porosity to allow the transport of the fuel to and the transport of the products of fuel oxidation away from the electrolyte/anode interface where the fuel oxidation reaction takes place; • matching thermal expansion coefficient with that of the electrolyte and interconnect; • integrity of porosity for gas permeation; • chemical stability with the electrolyte and interconnect; • applicability to use with versatile fuels and impurities; and • cost effective is a commercialization factor. 22.3.2 Catalyst The catalyst facilitates and speeds up the rate of the ionization reaction of oxygen at the cathode and hydrogen at the anode. It is usually made of platinum for low temperature cells and nickel at higher temperatures. The catalyst is rough and porous so that the maximum surface area can be exposed to the hydrogen or oxygen. The catalyst faces the electrolyte and must be able to conduct electrons to/from the electrode. The effectiveness of the catalyst is paramount to fuel cell operation. Platinum is sufficiently reactive in bonding H and O intermediates as is required to facilitate the electrode process, then effectively releases the intermediate to form the final product. For example, the anode process requires Pt sites to bond H atoms when the H2 molecule reacts, and these Pt sites release the H atom as H+ + e-, as shown in the two equations: H 2 + 2 Pt → 2 Pt −H

2 Pt −H → 2 Pt + 2 H + + 2 e − Platinum can be oxidized which is a problem because it compete with hydrogen oxidation, reducing the half-cell potential: Pt + H 2O ↔ PtOH + H + + e −

Pt + H 2O ↔ PtO + 2H + + 2e − ½O 2 + 2H + + 2e − → H 2O

943

Power Electronics

Chapter 22

Hydrocarbon fuels, like CH3OH, tend to poison the anode platinum catalyst with COH and CO species. The poisoning can be prevented by the addition of Ruthenium, Ru. Ru + H 2O → RuOH + H + + e −

Pt x CO + RuOH → CO 2 + H + + e − + xPt + Ru Catalytic reduction action also occurs on the cathode: O 2 + 2 Pt → 2 Pt −O 2 Pt −O → 2 Pt + 2 O 2− − 4 e − The reaction effectiveness is dependant on temperature and platinum surface area. At lower temperature reactions, platinum particles are used, 2 nanometres in diameter, resulting in a large Pt area that is accessible to the gas molecules. At elevated temperatures, over 400C, transition metals, Ni and oxides NiO, become effective, low cost catalysts, that can also act as the electrode. NiO + CO 2 → Ni 2+ + CO 32− At higher again temperatures no catalyst is necessary. Reduction of oxygen at the cathode is less efficient than the catalytic action on hydrogen at the anode. In lower temperature fuel cell, various nanoparticle platinum alloys (AuPt and Pt3Ni-III) are used to increase the O2 reduction reaction activity. The tolerance to poisoning and the affects of an acidic environment are factors to be overcome with semi-formed alloy catalysts. 22.3.3 Electrolyte In terms of chemistries, there are two main types of fuel cells, depending on the pH of the electrolyte. Common to all electrolytes is that they must not conduct free electrons. • Acid electrolyte which allows H+ hydrogen ion (proton) migration and free movement through the electrolyte from the anode to the cathode, producing water at the cathode, while conversely • Alkaline electrolyte which allows anion migration, for example, OH- hydroxyl ion migration through the electrolyte from the cathode to the anode, producing excess water at the anode. bipolar flow-field plate, graphite gas diffusion backing layer anode catalyst 3nm electrolyte membrane 25µm cathode catalyst

membrane catalyst

Heat water H2O

anode

cathode

-

e

-

e

+

H

The electrolyte is the either a solid (< 200°C) or a liquid (> 200°C), depending on the operating temperature. The electrolyte can be acidic or alkali and must pass ions but importantly, the electrolyte does not conduct free electrons and does not react with reactant ions. There are several criteria that the electrolyte has to meet. The electrolyte must be: • Dense and leak tight; • Stable in reducing and oxidising environments; • A good ionic conductor at operating temperatures; • Non-electron conductor; • Thin to reduce ionic resistance; • Extended in area for maximum current capacity; • Thermal shock resistant; and • Economically processable. 22.3.4 Interconnect Since a single cell only produces a voltage of less than 1V and power around 1W/cm2, many cells are electrically connected together in a cell stack to obtain higher voltage and power. To connect multiple cells together, an interconnection is used in stacks. The requirements of the interconnection are the most severe of all cell components and include: • High, nearly 100 percent electronic conductivity, not only through the bulk material but also in in-situ-formed oxide scales; • strong adhesion between the as-formed oxide scale and the underlying alloy substrate; • resistance to corrosion and surface stability in both oxidizing and reducing atmospheres at the cell operating temperature since it is exposed to duel atmospheres, with air (or oxygen) on the cathode side and fuel on the anode side; • low permeability for oxygen and hydrogen to minimize direct combination of oxidant and fuel during cell operation; • chemical compatibility with other materials in contact with the interconnect, such as seals and cell materials; • mechanical reliability and durability at the cell operating temperature; • a thermal expansion coefficient close to that of other stack components, mainly the cathode and the electrolyte (particularly for stacks using a rigid seal design); and • non-reactivity chemical compatibility with other cell materials.

22.3.5 Stack design In the case of planar cell stacks, an effective seal must be provided to isolate air from the fuel. The seal must have a thermal expansion match to the fuel cell components, must be electrically insulating and must be chemically stable under the operational conditions of the stack. Also, the seal should: • exhibit no deleterious interfacial reactions with other cell components; • be stable under both the high temperature oxidizing and reducing operational conditions; • be created at a low enough temperature to avoid damaging cell components (under 850oC for some materials); and • should not migrate or flow from the designated sealing region during sealing or cell operation. In addition, the sealing system should be able to withstand thermal cycling between the cell operation temperature and room temperature. Sealing is more of a problem with cell which operate at higher temperatures, where different sealing approaches include rigid, bonded seals (for example, glassceramics and brazes), compliant seals (for example viscous glasses) and compressive seals (for example, mica-based composites); multiple sealants may also be used in any given stack design between different cell components. 22.4

air

hydrogen H2

944

Suitable metallic alloy interconnects offer advantages such as improved manufacturability, significantly lower raw material and fabrication costs, and higher electrical and thermal conductivity.

gas diffusion layer

hydrogen fuel


porous gas diffusion layers

Figure 22.3. The parts of a fuel cell/Membrane/electrode assembly with backing layers. Enlarged cross-section of a membrane/electrode assembly showing structural details.

air O2

Fuel Cell Chemistries

The two chemical ion mechanisms involving anions and cations, will be discussed in terms of: • an acid electrolyte and transfers cations, protons, H+, through the electrolyte, producing water at the cathode and • an alkaline electrolyte and transfers anions (OH-, CO32-, O2-) through the electrolyte, producing water at the anode.

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Chapter 22

22.4.1 Proton H+ Cation Conducting Electrolyte: e.g. PEMFC, DMFC, PAFC

The net fuel cell reaction, which is exothermic, is the algebraic summation of the half-cell reactions:

The Acidic electrolytic Fuel Cell utilises one of the simplest reactions of any fuel cell. In low temperature PEMFC and DMFC Fuel Cells, the electrolyte is a flexible acidic membrane that when saturated offers a number of desirable features: • Highly chemical resistant; • Mechanically strong, when only 50µm thick; • Acidic; • Highly water absorptive; • Good proton conductor, H+ cation, when saturated, but not flooded; • Electrically insulating, high resistance to electrons; and • Non-diffusive the gas molecules, no H2 and O2 crossover. Chemistry In both acid electrolyte and solid polymer fuel cells the electrolyte conducts mobile H+ ions, protons, generated at the anode. It is these H+ ions that are key to the reactions within the cell. At the anode, hydrogen gas is readily ionised, producing free electrons and H+ ions: 2 H 2( g ) → 4 H + + 4 e -

E ½o cell = 0.0V

(22.1)

The electrons from the anode conduct through the external circuit connected to the fuel cell, to the cathode. The H+ ions migrate or permeate through the electrolyte, and also reach the cathode. At the cathode the H+ ions and electrons react with the oxygen atoms, producing water. At the cathode the oxygen undergoes a two-step indirect reduction reaction. The stable H2O2 intermediate is undesirable as it lowers the cell voltage and H2O2 attacks and corrodes the carbonaceous electrodes commonly used in lower temperature cells. O 2 + 2H + + 2e − = H 2O 2 (22.2) H 2O 2 + 2H + + 2e − = 2H 2O Overall cathode half reaction: +

O 2 ( g ) + 4 H + 4 e → 2 H 2O -

E ½ cell = 1.23V o

(22.3)

This movement of ions through the electrolyte, and movement of electrons through the external circuit is illustrated in the diagram in figure 22.4a. electron flow

anode

∆G = 237kJ/mol

-

-

-

4e

4e

-

-

∆H = 286kJ/mol

+

-

H2 → 2H + 2e

2H2 2e

∆G = ∆H - T∆S

cathode

+

2H 2( g ) + O 2( g ) → 2H 2O + energy

o E cell = 1.23V

= 1.23 - 0 = 1.23V. Standard tables give the enthalpy as The chemistry of the fuel cell gives E 285.15kJ/mol and the number of electrons per H2, as n = 2. The dissociation kinetics of O2 and H2 improve with increased temperature but the cell potential decreases with temperature. Positive ions are produced at the anode and negative ions are produced at the cathode. The water molecules are always produced at the cathode, the production of which exceeds that which may be required (if any) at the anode. The H+ cations, as found in the Polymer Exchange Membrane Fuel Cell - PEMFC, Direct Methanol Fuel Cell – DMFC, and the Phosphoric Acid Fuel Cell - PAFC all behave the same within the fuel cell. That is, equations (22.1) to (22.4) are applicable to the three cation fuel cells presented. 22.4.2 Anion (OH-, CO32-, O2-) Conducting Electrolyte: e.g. AFC, MCFC, SOFC The important feature of an alkali is that there is an excess of anions, X- ions, generated at the cathode, and these are key to the reactions within the alkali electrolyte fuel cell. An electric current is produced as a result the half-cell reaction at each electrode. At the anode, hydrogen gas reacts with the X- ions, anions which have migrated through the electrolyte, producing water, and releasing electrons. The reaction is: 2H 2( g ) + 4 X (−aq ) → 4H 2 0(l ) + 4e -

-

H+

+ +

-

O 2( g ) + 2H 2O + 4e - → 4 X (-aq )

-

O

The X ions move through the electrolyte, and the electrons move round the external circuit. The complementary movement of ions and electrons is illustrated in the diagram in figure 22.5a. The net reaction, which is exothermic, is the algebraic half-cell reaction summation: 2H 2( g ) + O 2( g ) → 2H 2O + energy

4e

electron flow

O 2 ( g ) + 4 H + 4 e → 2 H 2O -

-

anode

-

-

4e

4e

+ +

-

-

-

-

air and water vapour H2O exhaust

cathode gas diffusion electrode

anode gas diffusion electrode Pt catalyst

O OH 2CO3

-

2H2

(g )

+ 2 H 2O + 4 e - → 4 X

4e −

O2

O2 oxygen from air

4e -

-

heat 200°C

water vapour H2O

-

X-

-

Pt catalyst cation exchange membrane

Figure 22.4. The chemistry mechanisms of an acidic electrolyte fuel cell.

2H2O CO2

2H2O

air

CO2/H2O

flow field plate

flow field plate

cathode O 2

2H2O

unused fuel recirculates exhaust

2 H 2( g ) + 4 X − → 4 H 2O + 4 e alkali electrolyte

+

4e -

O + 2H+ + 2e- → H2O heat 85°C T∆S = 49kJ/mol

(22.7)

2-

fuel, H2 hydrogen

-

(22.6)

-

or oxidant - oxidiser

O2

(22.5)

The electrons leave the fuel cell at the anode, passing through the external electrical circuit connected to the fuel cell, and reach the cathode. At the cathode the entering electrons react with the incoming oxygen, and water, producing more X- ions to replenish those used at the anode.

O2 oxygen from air

2e

(22.4)

o cell

+

2e -

fuel H2 hydrogen

2 H 2( g ) → 4 H + + 4 e acidic electrolyte

-

946


electrode - anode catalyst

electrode - cathode

anion exchange electrolyte

catalyst

Figure 22.5. The chemistry mechanisms of an alkaline electrolyte fuel cell.

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Power Electronics

Positive ions are produced at the anode and negative ions are produced at the cathode. Water molecules are always produced at the anode, and at a faster rate than those (if any) being consumed at the cathode. Anions, such as OH-, CO32- and O2- as found in the Alkaline Fuel Cell - AFC, Molten Carbonate Fuel Cell - MCFC, and Solid Oxide Fuel Cell - SOFC, behave similarly within the fuel cell, as given by equations (22.5) to (22.7). 22.5


•

•

Six main Fuel Cells

Some of the main types of fuel cells, with increasing operating temperature, include:

•

•

22.6

Chapter 22

Low-temperature Fuel Cell types (200°C) o Phosphoric-acid fuel cell (PAFC) - H+ o Molten-carbonate fuel cell (MCFC) - CO32o Solid oxide fuel cell (SOFC) - O2-

Low-temperature Fuel Cell types

22.6.1 Polymer exchange membrane fuel cell (PEMFC) (Proton Exchange Membrane FC) The PEMFC has a high power density and a relatively low operating temperature (ranging from 60 to 80°C). The low operating temperature means that the fuel cell can warm-up and begin to generate electricity quickly, resulting in less wear on system components, leading to better durability. Cells do not use corrosive fluids like some fuel cells. However, it requires a noble-metal catalyst (typically platinum) to separate the hydrogen's electrons and protons, adding to system cost. The platinum catalyst is also hyper-sensitive to CO poisoning, making it necessary to employ an external reactor to reduce CO in the fuel gas if the hydrogen is derived from an alcohol or hydrocarbon fuel. Platinum/ruthenium catalysts are more resistant to CO. The slow kinetics of oxygen at the cathode also necessitates the use of a catalyst. Higher-density liquid fuels such as methanol, ethanol, natural gas, liquefied petroleum gas, and gasoline can be used for fuel, but the system must have an external fuel processor to reform the methanol to hydrogen. Reforming releases minimal carbon dioxide. The PEMFC has a high power density, high efficiency, and can adapt to varying demands. It promises a high conversion efficiency of over 60% and an energy density of 120 W/Kg, with 2kW/l and 2W/cm2. The PEM fuel cell is currently favoured for electric motor vehicles. Other applications include air conditioning and domestic sized electronic equipment. Key features are: • Fast start-up, rapid transient power response, high power density, compact • H+ via polymer (ionomer) membrane electrolyte, Pt, 50°C to 150°C, H2 at < 5 atm. • Sensitive to impurities, CO, sulphur species, and NH3 • Anode and cathode gas sealing is simpler with a solid electrolyte therefore cheaper, no orientation restrictions, and low corrosion leads to a longer cell and stack life. • Portable applications, 50 to 500kW – automotive, small stationary auxiliary power units • Overall reaction ∆H = -286.0kJ/mol, with n = 2. PEMFC Pt

E ½o cell = 0.0V

Anode Reactions:

2 H 2( g ) → 4 H + + 4 e -

Cathode Reactions:

o Pt O 2( g ) + 4 H + + 4 e - → 2 H 2O E ½cell = 1.229V

Overall Cell Reactions: 2 H 2( g ) + O 2( g ) → 2 H 2O

o E cell = 1.229V

As shown in figure 22.3 for the PEMFC case, which is typical of the basic physical structure, there are four basic elements of the fuel cell: • The anode is the negative electrode and conducts the electrons that are released from the hydrogen molecules so that they can be used in an external electrical circuit. The carbon or metal interconnect, which makes electrical contact to the anode carbon sheet, has channels etched into it that disperse the hydrogen gas uniformly over the back surface of the catalyst layer.

•

948

The cathode is the positive electrode and also has etched channels that distribute the oxygen to the back surface of the catalyst layer. It also conducts the electrons received from the external circuit to the catalyst, where they can recombine with the hydrogen ions and oxygen to form water. The carbon or metal interconnect, like the anode interconnect, makes electrical contact to the cathode carbon sheet. The electrolyte is the proton exchange membrane. This specially treated organic material is a thin, 50µm, flexible plastic (poly-perfluorosulphonic acid) film, which only conducts positively charged ions when it is saturated with water. The membrane must be hydrated (by absorbing water) in order to function and remain stable. Importantly, the membrane blocks electrons. Being a solid, membrane helps minimise gas crossover. The catalyst is usually made of platinum nanoparticles thinly coated onto carbon paper or cloth, which is the effective anode or cathode. The catalyst is rough and porous so that the maximum platinum surface area can be exposed to the hydrogen or oxygen. The platinum-coated side of the carbon sheet, the catalyst, faces the polymer membrane.

The Backing Layers The fuel cell anode and cathode assemblies are designed to maximize the current that can be obtained from an electrode and catalyst assembly. The backing layers on which the catalyst is deposited, are usually made of a porous carbon paper or carbon cloth, typically 100 to 300 µm thick, that can conduct the electrons and effectively diffuse reactant gas ions created and reacted in the platinum catalyst. The platinum catalyst particles are deposited 50µm thick on one side of each backing layer; the side that faces the electrolytic. Diffusion refers to the flow of gas molecules from a region of high concentration, the outer side of the backing layer where the gas is flowing by in the flow fields, to a region of low concentration, the inner side of the backing layer next to the catalyst layer where the gas is consumed by the reaction. The porous structure of the backing layers allows the gas to spread out as it diffuses so that when it penetrates the backing, the gas will be in contact with the entire surface area of the catalyzed membrane. The backing layers also assist in water management during the operation of the fuel cell. An effective backing material allows the correct amount of water vapour to reach the membrane/electrode assembly to keep the membrane humidified. The backing material also allows the liquid water produced at the cathode to leave the cell to avoid flooding. The backing layers are often wet-proofed with Teflon to ensure that most of the pores in the carbon cloth (or carbon paper) do not become saturated with water, which would prevent the rapid gas diffusion necessary for a good rate of reaction, from occurring at the electrodes. The solid organic polymer electrolyte membrane The polymer electrolyte membrane is essentially PTFE containing a fraction of pendant sulphonic acid groups. (Nomenclature: ‘sulphonic acid group’ usually refers to the un-dissociated SO3H group, where as ‘sulphonate’ refers to the ionised SO3– group after the proton has dissociated). The ion containing component is normally given in terms of equivalent weight (that is, number of grams of dry polymer per mole of acidic groups). The useful equivalent weight for Nafion ranges from 800-1500 g/mol. The length of and the precise nature of the side chains vary between different brands of polymer. Common to all is the PTFE based fluorocarbon ‘backbone’ of the polymer that has several desirable properties: • PTFE is hydrophobic - this means the hydrophilic sulphonate groups are effectively repelled by the chains and cluster together; • PTFE is extremely resilient to chemical attack – the environment within the membrane is hostile and acidic. Hydrocarbon-based polymers would tend to degrade rapidly; and • PTFE is a thermoplastic with high mechanical strength – meaning very thin membranes can be produced, reducing the thickness of each cell and increasing the power density of the stack. As shown in figure 22.6, the thin permeable electrolyte sheet of poly-perflourosulphonic acid consists of three distinct regions. • A Teflon-like fluorocarbon backbone of hundreds of repeating chains −CF 2 − CF − CF 2 − • Side chains connecting the molecular backbone to the third region O − CF 2 − CF − O − CF 2 − CF 2 − • Ion clusters of sulphonic acid ions -

SO 3−H +

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Power Electronics

Chapter 22

When the membrane becomes hydrated, the hydrogen ions become mobile and bond to water molecules as they move from one SO3- site to another in the acid molecule. (-CF2 -)n = PTFE hydrophobic

main backbone

SO3 hydrophilic side chain ion cluster H+ and H3O+

950


Other catalysts are Ni, Ag, metal oxides, spinels and noble metals. The thin proton exchange membrane is covered on both sides with a sparse layer of platinum-based catalyst. DMFC do not use hydrogen fuel, but more convenient liquid methanol. The anode catalyst draws H2 from liquid methanol, thus eliminating the need for a fuel reformer. They are less efficient but offer compact and convenient designs suitable for future consumer electronics applications and in automotive areas because the fuel is convenient. One litre of methanol can theoretically provide 5kWh, but 1.7kWh outputs are typical. Key features are: • Use with liquid alcohol - methanol canisters, compact, no reforming • Methanol is liquid from -97°C to 65°C, with ×10 the energy/litre of highly compressed H2 • H+ via polymer electrolyte, Pt or alternatives (Ru), 90°C to 100°C • Cell efficiency of 40% and increases with temperature • Small portable, battery replacement in mobile phones and laptops, small transport • Overall reaction ∆H = -726.6kJ/mol, with n = 6. Direct Methanol

Figure 22.6. A PTFE fluorocarbon (NAFION) used for the PEM fuel cell electrolyte. Anode Reaction:

22.6.2 Alkaline fuel cell (AFC) This is one of the oldest designs for fuel cells, with modest cell efficiencies of nearly 70%. The AFC is susceptible to contamination, so requires pure hydrogen and oxygen. It is also expensive, which is hampering commercialization. Key features are: • Fast start-up, but bulky, 10kW to 100kW • OH via liquid or polymer electrolyte, KOH, non-Pt, 80°C to 160°C, gas or liquid fuels • Susceptible to carbon contamination by K2CO3 formation, needs pure H2 and O2 • Portable, small stationary/transport, space vehicles, submarines • Overall reaction ∆H = -286.0kJ/mol, with n = 2. The anode half-cell reaction involves two stages. Ni

2H 2 → 4H + + 4e − Ni

4H + + 4OH − → 4H 2O

The overall cell reactions are: Anode Reaction:

o Ni 2 H 2( g ) + 4 OH - → 4 H 2O + 4 e - E ½cell = -0.83V

Cathode Reaction:

O 2( g ) + 2 H 2O + 4 e - → 4 OH -

Ni

Overall Net Reaction: 2 H 2( g ) + O 2( g ) → 2 H 2O

E ½o cell = 0.401V o E cell = 1.231V

o = 0.401 - -0.83 = 1.231V. Standard tables give the enthalpy as The chemistry of this fuel cell gives E cell 286kJ/mol and the number of electrons per H2, as n = 2.

These fuel cells use an alkali solution of potassium hydroxide KOH in water as the electrolyte and can use a variety of non-precious metals as a catalyst at the anode and cathode. High-temperature AFCs operate at temperatures between 100°C and 250°C, with newer AFC designs operating at temperatures below 100°C. Concentration of electrolyte, KOH, which is contained in an asbestos matrix, decreases to 50% at lower temperatures. Electro-catalyst can by Ni, Ag, metal oxides, spinels, and noble metals. Aqueous alkaline solutions do not reject CO2. Thus a disadvantage of this fuel cell type is that it is readily poisoned by carbon dioxide CO2, which reacts to produce K2CO3 that irreversibly blocks the pores in the cathode. The levels of CO2 in the air affect cell operation, making it necessary to purify both the hydrogen and oxygen used in the cell. This purification process is costly. This susceptibility to catalyst poisoning affects the cell's lifetime and precludes the use of platinum as a catalyst. 22.6.3 Direct-methanol fuel cell (DMFC) The methanol fuel cell is an optimised PEMFC but is not as efficient. The efficiency is low due to the permeation of neutral methanol and water through the sulphonated organic hydrocarbon polymer membrane (e.g. Nafion), termed crossover. The low-temperature oxidation of methanol to hydrogen ions and carbon dioxide requires more active platinum catalyst, which makes these fuel cells expensive.

o Pt/Ru 2 CH 3OH + 2 H 2O → 2 CO 2( g ) + 12 H + + 12 e - E ½cell = 0.2V

Cathode Reaction: Overall Cell Reaction:

Pt

3 O 2( g ) + 12 H + + 12 e - → 6 H 2O 2 CH 3OH + 3 O 2( g ) → 2CO 2( g ) + 4 H 2O

E ½o cell = 1.23V o E cell = 1.214V

CO2

ote that H2O is required at the anode, with an excess over the anode requirement being produced at the cathode. 22.7

High-temperature Fuel Cell types (well in excess of 100°C)

22.7.1 Phosphoric-acid fuel cell (PAFC) The liquid phosphoric-acid fuel cell has potential for use in small stationary power-generation systems up to 10MW with 50% cell efficiency and better than 80% efficiency if steam produces cogeneration, CHP. It operates at a higher temperature than polymer exchange membrane fuel cells, so it has a longer warm-up time, restricting its application areas, and it must be continuously operated since H3PO4 electrolyte effloresces irreversibly and solidifies at 40°C. A silicon carbide matrix is used to retain the concentrated H3PO4 electrolyte and highly dispersed Platinum and Pt alloy anode catalysts particles. CO2 does not affect the electrolyte or cell performance, which can therefore be operated with reformed fossil fuel. Simple construction, low electrolyte volatility, and long-term stability are additional advantages. Key features are: • First commercially available, best suited to large size • H+ via liquid or polymer electrolyte, Pt, 150-250°C, with near 100% concentration H3PO4 • Carbon paper electrodes Pt coated, Pt unaffected by CO (15mm), or of much smaller diameter (

H2

O

(g)

1.0

0.6 (W/cm2)

2

(c)

500

700

Temperature T

900

(K)

Figure 22.10. Graphs of a hydrogen/air fuel cell: (a) voltage versus current density, (b) efficiency versus current density; and (c) open circuit voltage versus temperature.

22.14

Thermodynamics

Prediction of the maximum possible voltage from a fuel cell process involves evaluation of energy differences between the initial state of the reactants in the process, H2 + ½02, and the final state, H20. Such evaluation relies on state thermodynamic functions in a chemical process, primarily the Gibbs free energy. The maximum cell voltage, at electrical output open-circuit, or emf, ∆E, for the hydrogen/air fuel cell reaction (H2 + ½0 → H20) at a specific temperature and pressure is given by the relationship, in electrical terms: ∆G ∆G W ∆E = == (V) (22.14) n × e × No n ×F n ×F where ∆G is the Gibbs free energy change for the reaction or energy available for electrical work, W, n is the number of moles of electrons involved in the reaction per mole of reactant, H2, and F is Faraday’s constant, 96,487 C/mol (J/V) (26.8015Ah/kg-equiv), the charge transferred per mole of electrons. Faradays constant is Avogadro’s number No = 6.02×1023 multiplied by the charge of one electron, e = -19 1.60×10 . The product n×F or charge Q is the amount of electricity produced. At one atmosphere of pressure, the Gibbs net free energy change ∆G in the fuel cell process (per mole of H2), available for net useful work, is calculated from the reaction temperature T, and from changes in the reaction enthalpy, ∆H, and entropy, ∆S. ∆G = −n × F × ∆E = ∆H - T × ∆S (J) (22.15) where T is the absolute temperature, K ∆S is the entropy change for the reaction, (∆S60%; internal combustion engine is typically about 30%. High energy density. Silent operation and safe, with no moving parts, vibration free Portable, modular construction.

967

Power Electronics

Shortcomings • The environmentally friendly credentials of fuel cells overlook the processes needed to generate and distribute the necessary hydrogen fuel. Fuel cells merely shift the pollution from the fuel cell to the reforming location. • 98% of hydrogen is produced from fossil fuel sources. • No infrastructure exists to provide and distribute the necessary hydrogen fuel. • Electrolyte freeze-up at low temperatures. • Electrodes and catalysts are prone to contamination and are expensive. • Because of the exotic materials and complex design, the system is expensive. • Not yet proven commercially viable in common usage, compared to the alternatives. • Best as primary source. • Limited availability. • Low durability. • Low power density per unit volume, not volume efficient due to associated ancillaries. • Alternatively hydrogen can be generated in situ, as required, from hydrocarbon fuels such as ethanol, methanol, petrol or compressed natural gas from the reforming process. Reforming generates carbon dioxide as a waste product. It is also expensive with a chemical plant in situ, but this does simplify the fuel supply infrastructure problem, however the fuel could just as readily be used in an internal combustion engine. • Despite safety precautions, there is a perception that hydrogen fuel is unsafe. • The low cell voltage, 0.6V to 0.7V, means that many series connected cells are needed. • Pulse demands shorten lifetime. • The process is not reversible within the fuel cell and as with the primary cell, it cannot accept or store regenerative energy. The reactants must flow continuously. • Fuel cells have a low dynamic range and slow transient response which causes an unacceptable lag in responding to instant power demands. At low powers levels, a power boost from a battery or supercapacitor would improve transient performance. • Most designs operate at high temperatures so as to achieve reasonable operating efficiencies. To generate the same efficiencies at lower temperatures requires large quantities of expensive platinum catalysts. • Complex to operate.

Chapter 22

22.16.2

968


System Technology Challenges

Cost and durability are the major challenges to widespread fuel cell commercialization. However, hurdles vary according to the application in which the technology is employed. Size, weight, and thermal and water management are barriers to the commercialization of fuel cell technology. In transportation applications, fuel cell technologies face more stringent cost and durability hurdles. In stationary power applications, where cogeneration of heat and power is desired, use of PEM fuel cells would benefit from raised operating temperatures to increase efficiency performance. The key challenges include:

• •

•

•

•

22.17

Cost: The fuel cell power system is more expensive than conventional technologies. Durability and Reliability: The durability of fuel cell systems has not been established. For transportation applications, fuel cell power systems are required to achieve the same level of durability and reliability of current energy sources in terms of lifespan time, performance, and ambient operating temperature. System Size: The size and weight of fuel cell systems must be reduced to the levels of other technologies. This reduction applies to the fuel cell stack and the ancillary components and major subsystems (for example, fuel processor, compressor/expander, and sensors) making up the balance of power system. Improved Heat Recovery Systems: The low operating temperature of PEM fuel cells limits the amount and type of CHP applications. Technologies need to be developed that will allow higher operating temperatures and/or more effective heat recovery systems and improved system designs to enable CHP efficiencies exceeding 80%. Infrastructure: unfamiliar technology to power industry, with no infrastructure in place.

Fuel cell summary Types of fuels

Fuel Cell types

hydrogen methanol

22.16

Fuel Cell Challenges

The shortcomings of the fuel cell represent the possible challenges of this energy source.

liquid fuels

air

evaporation

SOFC internal thermal reforming

natural gas 22.16.1 Chemical Technology Challenges

•

•

•

•

Durability: More durable PEMFC membranes are needed that can operate at temperatures greater than 100°C and still function at sub-zero ambient temperatures. A 100°C temperature target is required in order for a fuel cell to have a higher tolerance to impurities in fuel. Also, water by-product at over 100ºC has better co-generation possibilities. Because of frequent start and stop, it is important for the membrane to remain stable under cycling conditions. Membranes tend to degrade with cycling, particularly as operating temperatures rise. Hydration: PEMFC membranes must be hydrated in order to transfer hydrogen protons. At around 80°C, hydration is lost without a high-pressure hydration system. Membranes are needed for sub-zero temperature operation, low humidity environments, and high operating temperatures. The SOFC durability: Solid oxide systems have issues with material corrosion. Seal integrity is also a major concern. The cost goal for SOFC’s is less restrictive than for PEMFC systems, but material costs are high. SOFC durability suffers with the cell temperature repeatedly heat cycled with start-up and shut down sequences. Aromatic-based membranes: An alternative to current perfluorosulphonic acid membranes are aromatic-based membranes like benzene, pyridine or indole. These membranes are more stable at higher temperatures, but still require hydration. They swell when they lose hydration, which reduces fuel cell efficiency.

sulphur removal xity ple om ure g c rat sin pe es em es roc g t l p ratin p tim ncy u ue g f ope rt - icie sin ng r sta eff rea asi rte ing inc ecre sho reas d c de

Fuel cell material development is mainly concern with electrolytic membrane materials. Many of the following challenges are orientate towards EV application using the PEM fuel cell.

MCFC

reforming

internal thermal reforming

800°C

650°C

to H2 and CO

PAFC shift reaction H2 and CO2

CO selective oxidation

CO 30 years • • 10% - 13% > 25 years

5% - 7%

•

• • • > 20 years • •

982

PV Cell Structures

Most PV devices use a single junction to create an electric field. In a single-junction PV cell, only photons with energy equal to or greater than the band gap of the cell material can elevate an electron into the conduction band. In other words, the photovoltaic response of single junction cells is limited to the portion of the sun's spectrum with energy above the band gap of the absorbing material. Lowerenergy photons are not used. One way around this limitation is to use two or more cells, with more than one band gap and more than one junction, to generate a series cell voltage. These structures are referred to as multi-junction cells. Multi-junction cells can achieve a higher total conversion efficiency because they can convert more of the energy spectrum of light to electricity. The actual structural design of a photovoltaic cell depends on the limitations of the material used in the PV cell. There are four basic device designs commonly used with the semiconducting materials. • Homojunction • Heterojunction • p-i-n/n-i-p • Multi-junction 22.21.1 Homojunction Device A single semiconductor material, crystalline silicon, is altered so that one side is p-type, dominated by positive holes, and the other side is n-type, dominated by negative electrons. The p-n junction is located so that the maximum amount of light is absorbed near it. The free electrons and holes generated by the light in the silicon diffuse to the p-n junction, then separate to produce an external current. In the homojunction design, several cell aspects are varied to increase the conversion efficiency: • Depth of the p-n junction below the cell's surface • Amount and distribution of dopant atoms on either side of the p-n junction • Crystallinity and purity of the silicon Numerous homojunction Si cell examples have been presented in previous sections of this chapter.

Characteristics of photovoltaic cells structure

22.21


Highest efficiency = least surface area. Expensive due to complicated manufacturing process. Highest achieved efficiency is 23%. Generate approximately 35mA/cm2 at a voltage of 550mV at full illumination. Most commonly used type of cell as it offers good efficiency at reasonable cost. Low efficiency hence requires large surface area. Made from flexible material. Better in diffused light than mono and polycrystalline. Current density of up to 15mA/cm2, and the cell opencircuit voltage of 0.8V, is more that a crystalline cell. Spectral response reaches maximum at the wavelengths of blue light therefore, ideal with fluorescent light sources.

The properties and features of the different PV technologies are summarised in tables 22.11 and 22.12.

22.21.2 Heterojunction Device An example of this type of device structure is a CIS cell (figure 22.19), where the junction is formed by contacting two different semiconductors, CdS and CuInSe2. This structure is often used for thin-film cells, which absorb light much better than silicon. The top and bottom layers in a heterojunction device have different functions. The top layer, or ‘window’ layer, is a material with a high bandgap selected for its light transparency. The window allows almost all the incident light to reach the bottom layer, which is a material with a low bandgap that readily absorbs light. This light then generates free electrons and holes near the junction, which separates the electrons and holes before they can recombine. A high band-gap window layer reduces the cell's series resistance. The window material can be made highly conductive, and the thickness can be increased without reducing the transmittance of light. Lightgenerated electrons can therefore readily flow laterally in the window layer to the electrical contact. 22.21.3 p-i-n and n-i-p Devices Typically, amorphous silicon thin-film cells use a p-i-n structure, whereas CdTe cells use an n-i-p structure. A three-layer sandwich is created, with a middle intrinsic (i-type or undoped) layer between ntype and p-type layers. This geometry sets up an electric field between the p and n type regions that breaches the middle intrinsic resistive region. Light generates free electrons and holes in the intrinsic region, which are then separated by the electric field. In the p-i-n amorphous silicon cell shown in figure 22.17, the top layer is p-type amorphous silicon, the middle layer is intrinsic silicon, and the bottom layer is n-type amorphous silicon. Amorphous silicon has many atomic-level electrical defects when it is highly conductive. Little current flows due to diffusion. However, in a p-i-n cell, current flows because the free electrons and holes are generated within the influence of an electric field, rather than having to move toward the field. Carrier lifetimes are long in the intrinsic layer. In a CdTe cell shown in figure 22.20, the device structure is similar to the amorphous silicon i cell, except the order of layers is inverted. Specifically, in a typical CdTe cell, the top layer is p-type cadmium sulphide (CdS), the middle layer is intrinsic CdTe, and the bottom layer is n-type zinc telluride (ZnTe). 22.21.4 Multi-junction Devices A multi-junction structure can achieve a higher total conversion efficiency by capturing a larger portion of the solar spectrum. In the typical multijunction cell shown in figure 22.21, individual cells with different bandgaps are stacked in descending bandgap order beneath one-another. The sunlight falls first on the material having the largest bandgap EG1. Photons not absorbed in the first cell are transmitted to the second cell EG2, which then absorbs the higher-energy portion of the remaining solar radiation while

983

Power Electronics

Chapter 22

•

remaining transparent to the lower-energy photons. These selective absorption processes continue through to the final cell, which has the smallest bandgap EG3.

light energy #

#

cell 3 EG3

cell 1 EG1

light G

The band gap of indium gallium arsenide can be altered by varying the ratio of the constituent materials. This offers possibilities for spectrally tuning the cell.

High efficiency multi-junction cells focus on gallium arsenide as one, or all, of the component cells which gives efficiencies of more than 35% under concentrated sunlight. Other multi-junction cells include the use of amorphous silicon and copper indium diselenide.

light G

#

cell 2 EG2

984


light

+

metal grid

EG1 > EG2 > EG3

e

-

light G

transparent conducting oxide

< 1.1 eV

< 1.43 eV

< 1.7 eV

+

+

#

cell 1: EG1

amorphous Si:H

p

#

+

cell 2: EG2

amorphous SiGe:H p

#

cell 3: EG3

amorphous SiGe:H

A multi-junction cell can be made in two different ways. • In the mechanical stack approach, two individual PV cells are made independently, one with a high bandgap and one with a lower bandgap. Then the two cells are mechanically stacked, the one with the highest bandgap on top of the other. • In the monolithic approach, one complete PV cell is made first, and then the layers for the second cell are grown or deposited directly on the first cell.

solar spectrum

e

n-AℓInP2 n-GaInP2

Power density

-2

W m µm

-1

i. The multi-junction device in figure 22.22 has a top cell of gallium indium phosphide, then a tunnel junction to allow the flow of electrons between the cells through a thin insulating layer, and a bottom cell of gallium arsenide.

1500

p-GaInP2 p+-GaAs n+-GaAs n-AℓGaAs n-GaAs

1000

500

p-GaAs 0

+

½

¾ wavelength

1 λ

1¼

p -GaAs

Antireflection coating Au grid Top cell: Eg = 1.8eV

light G

+

Eg = 1.8eV

Tunnel diode

Bottom cell: Eg = 1.43eV

+

+ i n

-

i n

+ -

i n

Figure 22.21. A typical multi-junction PV cell showing three progressively decreasing band gap cells.

2000

p

metal substrate

-

Figure 22.23. An amorphous silicon multi-junction p-i-n type PV cell.

i. Amorphous silicon multi-junctions Amorphous silicon cells, include silicon carbon alloyed p-i-n cells, n-i-p cells, and stacked cells. Multijunction devices not only achieve higher efficiencies than single-junction cells, but they also experience less light induced degradation. Because the intrinsic layers are so thin, the electric field sweeps charge carriers from these layers with minimal recombination. Multi-junction devices use two, or three, individual amorphous silicon cells stacked as shown in figure 22.23. To capture a broader portion of the sun's spectrum, the cells are made of materials with different band gaps. Amorphous silicon alloys with carbon, germanium, nitrogen, and tin can be used to vary the band gap and material properties to improve multi-junction devices. Since the depositions needed to make thin-film multi-junction devices do not use much energy, such devices are potentially inexpensive to fabricate. Making a multi-layered cell is similar to making one cell; just adding one thin-film after another. ii. Copper Indium Diselenide multi-junction Copper indium diselenide cells have a band gap of 1.0eV and are used as a single junction cell or with a higher band-gap material in a multi-junction device. Amorphous silicon, with a band gap of about 1.7eV, on top of CIS is an example of a multi-junction cell, as shown in figure 22.24. Copper indium diselenide, a versatile material, is used as a bottom cell in conjunction with top cells of materials such as CdTe and GaAs, which have band gaps of approximately 1.43 and 1.44eV.

Eg = 1.43eV

light

substrate

light

+

light G

µm

Figure 22.22. A monolithic multi-junction PV cell based on GaAs and GaInP.

ii. Another monolithic cell, a device that uses indium phosphide for the top cell and indium gallium arsenide for the bottom cell (InP/InGaAs), reaches 31.8% efficiency under 50 suns concentration. There are several aspects about this device. • Traditionally, for highest efficiency in a two-junction device, the top cell should have a high band gap of approximately 1.9eV while the bottom cell should have a band gap of about 1.4eV. For this device, the band gap of the top cell is 1.35eV and that of the bottom cell is about 0.75eV. • The cell is ideally suited for space applications because the resistance of indium phosphide to radiation is 50% better than that of silicon and 15% better than that of gallium arsenide, which are the two materials used for PV power in space. This means that arrays using InP/InGaAs cells are lighter, cheaper, more reliable, have longer lifetime, and are more powerful.

+ -

-

Zn0 p i n Zn0 insulator 0.1um Zn0 0.05um n 2um p 0.4um Mo substrate

+ Figure 22.24. A CID multi-junction PV cell.

+ +

Chapter 22

Equivalent circuit of a PV cell

The cell open circuit voltage VOC (the cell voltage at night, G = 0) is when the output current is zero, I = 0, such that the model diode current ID equals to photo generated current Iph. That is, equating equation (22.24) to zero  V  (22.28) I (V ) = I ph − I o e γ Vth − 1 = 0   gives I  Voc = γ Vth An  ph + 1  (22.29)  Io 

To understand the electronic behaviour of a PV cell, it is useful to create a circuit model which is electrically equivalent, and is based on discrete electrical components whose behaviour is well known. An ideal single PV cell may be modelled by a current source in parallel with a diode; in practice no PV cell is ideal, so shunt resistance and series resistance components are added to the model. 22.22.1 Ideal PV cell model During darkness the PV cell is not active and behaves as a diode, that is, a p-n junction diode, not producing current. The simplest PV cell model consists of diode and current source parallel connected as shown in figure 22.25a. The current source current Iph is directly proportional to the solar radiation G (with incident optical power Pin). The diode represents the pn junction of a PV cell. The equations of an ideal PV cell, which represents the ideal PV cell model, are: V qV     I D (V ) = I o e γ kT − 1 = I o e γ Vth − 1 (22.22)    

I ph = ηg × G × Ac = 2

q P h × v in

22.22.2 Practical PV cell model The equivalent circuit of a practical PV cell is a constant current source in parallel with an ideal diode and a shunt resistor Rsh, plus that all in series with a series resistor Rs. The equations which describes the relationship between the output current and output voltage characteristics, I-V, of the PV cell are V − IRs   V − IRs (22.30) I (V ) = I ph − I D − I shunt = I L − I o e γ Vth − 1 − Rsh   22.22.3 Maximum-power point

(22.23)

where G is the ambient irradiance, W/m , ηg is the generation efficiency, and Ac is the cell effective or active area, m2. I Iph

V

Vph

Rs Rsh

I V

G

maximum power point

(A)

(b)

Figure 22.25. PV cell electrical circuit model: (a) basic model and (b) extended model incorporating series and shunt resistances.

−q E G   1 1  γk −   T  η  e T T1  I o (T ) = I SC (T 1 )   VOC ,T   T 1   γ Vth ,T11  e − 1    I SC , nom ,T1  I SC ,T 2 − I SC ,T1  (T ) = G (T − T 1 )  1 + G nom  T 2 −T1 

Impp

(22.25)

1/R

1 Vmpp

0

0.1

0.2

0.3

0.4

PV cell voltage

4

VOC

Current

0.5 (V)

(b)

0.2

0.3

0.2

0.3

0.4

PV cell voltage

0.5

0.6

(V)

4

temperature

Pmax

2

½ suns ½ kW/m2

PV cell voltage

0.1

ISC

¼ suns ¼ kW/m2

0.1

VOC

0

1 suns 1 kW/m2

0

½

Vmpp

0

VOC 0.4

0.5

0.6

1 VOC

0 0

0.1

(V)

0.2

0.3

PV cell voltage

(c)

0.4

1½ 1

temperature

3

irradiance area

1

power

(a)

0

Gnom = 1kW/m2, termed 1 sun, EG is the band gap voltage, eV, VOC is the open circuit output voltage, which has a temperature coefficient of 2.3mV/°C for silicon, and ISC is the short circuit output current, the largest output current, when V = ID = 0 in equation (22.24), whence ISC = Iph.

2

Impp Pmpp

1

0.6

2 suns 2 kW/m2

ISC

2

(22.27)

ISC

2

3

(22.26)

4 3

0

3

I ph

1/Rmpp

ISC

2

Current

The net output current I is the difference between the photocurrent Iph and the normal diode current ID  V  I (V ) = I ph − I D = I ph − I o e γ Vth − 1 (22.24)   where V is the diode voltage (V) Iph is the photo-current from the current source (proportional to the incident light intensity), A Io is the diode dark saturation current or reverse saturation current, A (approximately 10-8/m2) k is Boltzmann’s constant, 1.38 x 10-23J/K, h is Planck’s constant, 6.626x10-34 J.s q is the charge on an electron, 1.6 x 10-19 J/V, C or As, v is the photon frequency, Hz, and T is the working temperature of the cell in degrees Kelvin, K.

kT Vth = q where Vth - thermal voltage, Vth = 25.7mV at 25°C, γ - diode non-ideal factor = 1 to 2 (γ = 1 for ideal diode) Both Io and Iph are strongly dependant on temperature.

4 3

(A)

(a)

(W)

Vph

Ishunt

0.5

0.6

(V)

(d)

Figure 22.26. A typical PV cell characteristics: (a) voltage-current I-V curve; (b) I-V and power characteristics; (c) effects of increased incident irradiance and cell area; and (d) effects of increased temperature on I-V characteristics.

power

Iph

ID

(A)

ID

A PV cell may operate over a wide range of output voltages V and currents I. The product of I and V is the power output of the cell P, and the solution of the equation that maximizes that product yields the voltage Vmpp and current Impp at the maximum power point Pm, as shown in equation (22.31). By increasing the load resistance on an irradiated cell, continuously from zero (a short circuit) to a very high value (an open circuit) the maximum-power point can be determine, the point that maximizes V×I, that is, the load for which the cell can deliver maximum electrical power at that level of irradiation. The output power is zero in both the short circuit and open circuit extremes. Pm = V mpp × I mpp (22.31)

Current

heat

986


(A)

22.22

Power Electronics

Current

985

987

Power Electronics

Chapter 22

A high quality, monocrystalline silicon PV cell, at 25°C cell temperature, may produce an open circuit output voltage of VOC = 0.60V. The cell temperature in full sunlight, even with a 25°C ambient air temperature, will probably be close to 45°C, reducing the open circuit voltage to 0.55 Volts per cell, as indicated in figure 22.26d. The voltage drops modestly, with this type of cell, until the short circuit current ISC is approached. Maximum power (with a 45°C cell temperature) is typically produced with 75% to 85% of the open circuit voltage (0.43V in this case) and 80% to 90% of the short circuit current. This output can be up to 70% of the VOC x ISC product. The power output of the cell is almost directly proportional to the intensity of the sunlight. For example, if the intensity of the sunlight is halved the power will also be halved, as shown in figure 22.26c. The short circuit current ISC from a cell is nearly proportional to the illumination, while the open circuit voltage VOC may drop only 10% with a 80% drop in illumination. Lower quality cells have a more rapid drop in voltage with increasing current and may produce only ½VOC at ½ISC. The usable power output could thus drop from 70% of the VOC x Isc product to 50% or even as little as 25%. [Typical temperature coefficients: VOC=-2 x10-3/°C, Vmpp=-2.5 x10-3/°C, Isc=0.6x10-3/°C, Impp=0.4x10-3/°C] 22.23

Photovoltaic cell efficiency factors

Energy conversion efficiency PV cell energy conversion efficiency η, is the percentage of power converted (from absorbed light to electrical energy) and collected, when a PV cell is connected to an electrical circuit. This efficiency is calculated using the ratio of the maximum power point, Pm, divided by the input light irradiance (G, in W/m²) under standard test conditions (STC) and the surface area of the PV cell, Ac in m².

η=

Pm G × Ac

(22.32)

STC specifies a temperature of 25°C, an irradiance of 1000W/m², and a 0 m/s wind speed with an air mass 1.5 (AM = 1/cosθ, where angle θ is relative to the zenith, the vertical,) spectrum. These correspond to the irradiance and spectrum of sunlight incident on a clear day upon a sun-facing 37° - tilted surface with the sun at an angle of 41.81° above the horizon. The losses of a PV cell are divided into: • reflectance losses, • thermodynamic efficiency, • recombination losses, and • resistive electrical loss. The overall efficiency is related to the product of each of these individual losses, but these losses are not directly measurable. Other measurable parameters are used instead to specify efficiency: • Thermodynamic Efficiency, • Quantum Efficiency, • Voc ratio, and • Fill Factor, FF. Reflectance losses are a portion of the Quantum Efficiency. Recombination losses make up a portion of the Quantum Efficiency, Voc ratio, and Fill Factor. Resistive losses are predominantly categorized under Fill Factor, but also make up minor portions of the Quantum Efficiency and Voc ratio. Thermodynamic efficiency limit PV cell efficiency is limited because it operates as a quantum energy conversion device. Photons with energy below the band gap of the absorber material can not generate a electron-hole pair, and as such the photon energy is not converted to useful output. When a photon of greater energy than the band gap is absorbed, the excess energy above the band gap is converted to heat as the excess kinetic energy is released as the electron slows to equilibrium velocity. This loss is termed the Thermodynamic Efficiency Limit. Quantum efficiency An elevated electron-hole pair may travel to the surface of the PV cell and contribute to the current produced by the cell; such a carrier is said to be collected. Alternatively, the electron may give up its energy and once again become bound to an atom within the PV cell without reaching the surface; this is called recombination, and carriers that recombine do not contribute to the production of electrical current. Quantum efficiency refers to the percentage of photons that are converted to electric current (that is, collected carriers) when the cell is operated under short circuit conditions. External quantum efficiency is the fraction of incident photons that are converted into electrical current, while internal quantum efficiency is the fraction of absorbed photons that are converted into electrical current. Mathematically, internal quantum efficiency is related to external quantum efficiency by the reflectance of the PV cell; given a perfect anti-reflection coating, they are the same.


988

VOC ratio Due to electron recombination, the open circuit voltage Voc of the cell will be below the band gap voltage of the cell semiconductor. Since the energy of the photons must be at or above the band gap to generate a carrier pair, a cell voltage below the band gap voltage represents a loss. This loss is represented by

VOC ratio =

VOC EG

(22.33)

Fill factor Another term in the overall efficiency behaviour of a PV cell is the fill factor, FF, which is the ratio of the maximum power divided by the product of the open circuit voltage Voc and the short circuit current Isc:

FF =

I V η Ac G Pm = mpp mpp = VOC I SC VOC I SC VOC I SC

The cell fill-factor can be expressed as a function of the open circuit voltage by: V  VOC − An  OC + 0.72  γV  γVth  FF ≈ th

VOC +1 γVth

(22.34)

(22.35)

Concentrators A concentrator is a PV cell designed to operate under illumination greater than 1 sun. The incident sunlight is focused or guided by optical elements such that a high intensity light beam shines on a small area PV cell. Concentrators have several potential advantages, including a higher efficiency potential than a one-sun PV cell and the possibility of lower cost. The short-circuit current from a PV cell depends linearly on light intensity, such that a device operating under 10 suns would have 10 times the shortcircuit current as the same device under one sun operation. However, this effect does not provide an efficiency increase, since the incident power also increases linearly with concentration. Instead, the efficiency benefits arise from the logarithmic dependence of the open-circuit voltage on short circuit. Therefore, under concentration, VOC increases logarithmically with light intensity, specifically:   I SC    X × I SC  VOCX = γVTH An  (22.36)  = γVTH  An   + AnX  = VOC + γVTH AnX  Io    Io   where X is the concentration of sunlight. From equation (22.36), a doubling of the light intensity (X=2) causes an 18 mV rise in VOC. The cost of a concentrating PV system may be lower than a corresponding flat-plate PV system since only a small area of PV cells is needed. The efficiency benefits of concentration may be reduced by increased losses in the series resistance as the short-circuit current increases and also by the increased operational temperature of the PV cell. As losses due to short-circuit current depend on the current squared, power loss due to series resistance increases as the square of the concentration. Example 22.4: Solar cell characteristics A 1cm2 silicon solar cell has a saturation current Io of 10-12A and is illuminated with sunlight yielding a short-circuit photocurrent ISC of 25mA. Calculate the solar cell efficiency and fill factor, assuming a power density of 1kW/m2. Solution The maximum power is generated when: Vmpp  Vmpp   V   dP d   1 Vth V I − I o  e Vth − 1    = 0 = I ph − I o  e Vth − 1  −V mpp I o e =      dV dV   ph V th       where the voltage, Vmpp, is the voltage corresponding to the maximum power point. This voltage is obtained by solving the following transcendental equation, with Vth = 25.7mV and Iph =25mA (since the short circuit current equals the photocurrent, ISC = Iph at VSC) at 25°C:

I ph 25 × 10−3 A 1+ Io 10−12 A = Vth ln = 0.0257V × ln V mpp V mpp 1+ 1+ 0.0257V Vth 1+

V mpp

Iteration gives Vmpp =0.536V. The corresponding maximum power point current Impp is

989

Power Electronics

Chapter 22

I M ,sc = k × I SC

 V  Impp (V mpp = 0.54V ) = I ph − I o  e Vth − 1      0.536V  −12  0.0257V = 25mA − 10 e − 1 = 25mA − 1.14 × 10−3 = 23.86mA   The efficiency, assuming the irradiance power G of the sun is 1kW/m2, equals: V I 0.536V × 0.0239A η = mpp mpp = = 12.8% Pin 1 × 10−4 m2 × 1kW/m2 The open circuit voltage is calculated from Error! Objects cannot be created from editing field codes. which rearranged gives I  VOC = Vth ln  ph + 1   Io   25mA  = 0.0257V × ln  −12 + 1  = 0.615V  10  The fill factor is: V I 0.536V × 0.0239A fill factor = FF = mpp mpp = = 83.3% VOC I SC 0.615V × 0.025A ♣

22.24

RM , s =

(A)

(A)

6 two cells ISC

RM ,sh =

I

one cell

2

VM,OC = n×VOC

Vtotal

V1 0 0

0.2

0.4

0.6

PV cell voltage

0.8

1.0

1.2

Itotal

one cell

2

(22.40) (22.41)

22.13:Typical and maximum module and cell conversion efficiencies at Standard Test Conditions Type

Typical module efficiency

Maximum recorded module efficiency

Maximum recorded laboratory efficiency

%

%

%

Single crystalline silicon

12-15

22.7

24.7

Multi-crystalline silicon

11-14

15.3

19.8

5-7

-

12.7

Cadmium telluride, CdTe

-

10.5

16.0

CuInGaSe2, CIGS

-

12.1

18.2

VOC

0 0

0.2

(V)

0.4

0.6

PV cell voltage

(a)

n R k sh

The module terminal voltage VM and current IM characteristic equation can be expressed in terms of each cell or the characteristics of the module, namely VM −VM ,OC +RM ,s ×I M   n γVth  I M (VM ) = I M ,SC  1 − e (22.42)     or, in terms of the individual cell characteristics: n VM −n ×VOC + Rs ×I M   k   n γVth I M (VM ) = k × I SC  1 − e (22.43)      In terms of the simple model in figure 22.25a  VM  I M (VM ) = k × I ph − k × I o  e n γVth − 1  (22.44)    

Amorphous silicon

V I1

(22.39)

The module maximum power PM deliverable to a resistive load is PM = n × k × Pm

two cells

4

Current

Current

IM,sc=k×ISC

6

4

-

8

n R k s

The same formula applies to the calculation of the equivalent module shunt resistance:

Module (or array) series and parallel PV cell connection

8

(22.38)

If each cell has a series resistance Rs, the Thevenin equivalent resistance of the module is

Identical PV cells are series and parallel connection to form high-voltage, high-current, modules. For high current applications, modules are connected in parallel. For high voltage applications, modules are connected in series. If all the PV cells in a module have identical electrical characteristics, and all experience the same insolation and temperature, then all the cells will operate at the same current and voltage. In this case, the I-V curve of the PV module has the same shape as that of the individual cells, except that the voltage and current are increased.

+

990


0.8

1.0

1.2

(V)

(b)

Figure 22.27. I-V characteristics of identical PV cells connected in (a) series and (b) parallel.

Series connection of n identical cells: • When series connected, voltage adds Vtotal = V1 + V2 +... + Vn • The current remains constant Itotal = I1 = I2 With a series connection of voltage sources, the voltage of each source adds incrementally. For n series connected PV cells, each with open circuit voltage VOC, the module open circuit voltage is VM ,OC = n ×VOC (22.37) Parallel connection of k identical cells: • When parallel connected, the currents add Itotal = I1 + I2 +..+ Ik • The voltage remains constant Vtotal = V1 = V2..... With the parallel connection of voltage sources, the currents add. The voltage corresponds to that of a single source. For k parallel connected PV cells, each with short circuit current ISC, the module short-circuit current is

Example 22.5: PV cell and module characteristics A 100cm2 PV cell has I-V characteristics as shown in figure 22.25 parts a and b, at 25°C, achieved using a concentrator which gives 2kW/m2 on each cell. The PV cell is characterised by VOC = 0.625V Vmpp = 0.50V Impp = 3.5A ISC = 3.7A With diode properties γ = 1.5 and Vth = 25.7mV at 25°C. Use this information (and figures 22.26 and 22.27, if necessary) to find i. The maximum cell power and optimal load resistance for delivering this power; ii The fill factor FF; iii The VOC efficiency ratio, if the band gap of the silicon cell is 1.11eV at 25°C; iv. The open-circuit voltage and short-circuit current values if a module uses 36 of such cells series connection, with three cells parallel connected at each voltage level; and v. The module maximum power output and optimal load resistance for the given conditions. Solution

991

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i.

The maximum cell power Pm is given by equation (22.31), that is Pm = V mpp × I mpp

ii.

The efficiency fill factor FF is

= 0.5V×3.5A = 1.75W

FF =

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992

modules, called AC modules, have a built-in system inverter, eliminating the need for a large, central inverter, and simplifying wiring and safety issues. A PV system requires little maintenance (especially if no batteries are used), and can provide electricity cleanly and quietly for 20 years or more.

Pm VOC I SC

light

1.75W = 75.7% 0.625V×3.7A Alternatively, using equation (22.35) V  VOC − An  OC + 0.72  γV  γVth  = 16.21 − A n (16.21 + 0.72 ) = 77% FF ≈ th VOC 16.21 + 1 +1 =

γVth

iii.

The VOC efficiency ratio is

VOC ratio = iv.

VOC 0.625V = 56.3% = E G 1.11eV

With 36 series connected cells the open circuit output voltage is VM ,OC = n ×VOC = 36 × 0.625V = 22.5V The short circuit output current for three parallel connected cells at each voltage level is I M ,sc = k × I SC = 3 × 3.7A = 11.1A

v.

The module maximum power PM is PM = n × k × Pm = 36 × 3 × 1.75W = 189W where the output voltage is 36×0.50V=18V and the output current is 3×3.5A=10.5A (18V×10.5A=189W) ♣

22.25

Battery storage

PV cells can only produce electricity during the day, and then only on clear days. To be independent of the grid, energy storage is needed but batteries add cost and maintenance to the PV system. This problem is avoided with connection to the utility grid, buying power when needed and selling when producing more than needed, as shown in figure 22.28. This way, the utility acts as a practically infinite bidirectional storage system. Suitable inverter equipment is needed to ensure that the power sold to the utility is synchronous with the grid, specifically the same sinusoidal waveform and frequency. The utility has to be assured that if there is a power outage, the PV system does not try to feed electricity into lines. This disconnection is called islanding. Batteries need regular maintenance, and replacement after a few years, although the PV modules last for 20 years or more. Batteries in PV systems can also be dangerous because of the voltage level at which the energy is stored and the acidic electrolytes they contain, so the protective environment must be well-ventilated and non-metallic. A lead-acid car type battery is a shallow-cycle battery and PV storage requires deep-cycle batteries which can discharge a significant amount of their stored energy while still maintaining long life. PV batteries generally have to discharge a small current for a long period (such as all night), while being charged during the day. The nickel-cadmium battery is the most commonly used deep-cycle battery, which is more expensive than the lead-acid battery, but last longer and can be discharged more completely without harm. Lead-acid batteries cannot be deep-cycled or discharged 100 percent without seriously shortening battery life. Generally, if a PV system uses lead-acid batteries, the system is designed to discharge the batteries by no more than 40 percent or 50 percent. For long battery life, a charge controller is needed to prevent overcharging and complete discharge. The other problem besides energy storage is that the electricity generated by PV modules, and extracted from the storage batteries if used, is in dc form while household appliances and the utility grid need ac voltage. Most distributed generation inverters automatically control the system. Some PV

Figure 22.28. Schematic of a typical residential PV system with battery storage.

Weather and temperature Weather naturally affects the performance of PV modules but not as may be expected. The amount of sunlight is most important in determining the output a PV electric system will produce at a given location, but temperature is also important. PV modules actually generate more power at lower temperatures with other factors being equal. This is because PV cells generate electricity from light, not heat. Like most electronic devices, PV cells operate more efficiently at cooler temperatures. In temperate climates, PV panels will generate less energy in the winter than in the summer but this is due to the shorter days, lower sun angles and greater cloud cover, not the cooler temperatures. PV module output is proportional to the sun’s intensity, so cloud cover will reduce the system output. Typically, the output of any industrial PV module is reduced to 5% to 20% of its full sun output when operated under cloudy conditions. During a typical sunny day, a PV array one metre square exposed to the sun at noon will receive approximately 1kW of power. Multi-crystalline cells convert roughly 15% of this irradiation energy into electricity, hence 1m² of cells generates 150W in full sunshine. The warmer the cells become, the higher the losses. At 60ºC the capacity decreases by about 18% to 123W, and at 70ºC output drops by 24% to 114W. As shown in figure 22.26d, this reduced power output is because: • The voltage decreases, at an increasing rate, with increased temperature. • The current increases minimally with increasing temperature. This means that the maximum power output of a PV cell decreases with increased temperature, especially under higher irradiation levels. 22.26

The organic photovoltaic cell

Following absorption of photons by the polymer, bound electron-hole pairs (excitons) are generated, subsequently undergoing dissociation, as shown in figure 22.29. Due to inherent limitations in organic materials (exciton lifetime and low charge mobility), only a small fraction of photon-generated electronhole pairs effectively contribute to the photocurrent. The organic cell facilitates volume distribution of the photogeneration sites, thereby enhancing exciton dissociation. This is achieved by increasing the junction surface area, with an interpenetrating network of the donor-acceptor type, effecting transport of holes to the indium-tin oxide anode, and of electrons to the aluminium metallic cathode. While quantum separation efficiency, for photo-induced charges in systems associating a semiconducting polymer, polythiophene, with a fullerene derivative, is thus close to unity, the objective is to restrict recombination and trapping processes, limiting charge transport and collection at the electrodes, to improve overall device efficiency, this currently still being low, less than 5%. The rise of the pathway is also dependent on the cell aging mechanisms and the thin-film technologies, to protect the device against atmospheric oxygen and water vapour ingress.

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22.27

Figure 22.29. Organic PV cell.

Organic PV cells Operation of organic PV cells is mechanistically more complex. First, a molecule of an organic compound absorbs a photon and forms an excited state (exciton). Further, the exciton diffuses to a junction border between n- and p-types of semiconductor where it dissociates to form free charge carriers. Organic p- and n-transporters are also known as donors and acceptors respectively. If there is no junction border nearby, the exciton may recombine (decay) via photoluminescence, or thermally, back into the ground state of the molecule. This is the main reason, why mono- and bilayered (the scheme in figure 22.29) organic PV cells were poorly performing devices. The bulk heterojunction shown in figure 22.30 is a compact blend of a p-type conductor (donor), and ntype conductor (acceptor) in the photoactive layer of a device, where the concentration of each component often gradually increases when approaching the corresponding electrode. This magnifies the p-n-junction's total surface and strongly facilitates exciton dissociation. The implication of this concept in practice allows increased power conversion efficiencies of up to 5% for all-organic PV cells. The realization of the bulk-heterojunction concept, the organic cells and materials need further development in order to foster commercial application. Advantages of organic PV cells are: lightweight, environmentally friendly, no requirements for rare metals and minerals, no high temperatures and purity demand at the production stage, potentially inexpensive, virtually unlimited possibilities for further material improvements.

Figure 22.30. Bulk heterojunction organic solar cell.


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Summary of PV cell technology

PV advantages • Infinite source of input energy. The 89 petawatts of sunlight reaching the earth's surface is plentiful - almost 6,000 times more than the 15 terawatts of average power consumed by humans. • The silicon cells manufactured from one ton of sand produce as much electricity as burning 500,000 tons of coal. • Solar electric generation has the highest power density (global mean of 170W/m²) among renewable energies. • Low maintenance and long service lifetime, durable with minimal degradation over 10 years. • No emissions of C02, S02, N02, radiation. • Peak output matches daily peak demand. • Can be installed near point of energy need. • Grid-connected PV electricity can be used locally thus reducing transmission/ distribution losses or used decentralized. • Grid system integration possible, or independent of the grid thereby avoiding lack any of transmission and distribution infrastructure. • Quick installation. • Modular and expandable, for increased power. • Low operating costs, no fuel, transport and storage costs. • No moving parts to wear, operate silently with minimal system movement. • Environmental benign, no waste, no noise, free energy, no fuel transport costs. • High public acceptance. • Excellent safety record, with no combustible fuels. • Suitable for harsh environments. • Can be portable. • Suitable for remote locations, including high-temperature, high-altitude environments, with improved performance, where hydrocarbon based systems are derated. PV disadvantages • Sunlight is a low intensity energy source, hence limited power density, 2 to 5 kW·h/m2. • Produces dc, which must be converted to ac with at least 4% losses. • Hi tech skills to create the technology, but not necessary for installation, operation and maintenance. • Some PV materials are toxic, for example the cadmium in cadmium telluride PV cells, therefore requiring careful end of life treatment. • Energy not available at night or during overcast weather. • Expensive initial cell costs, plus expensive component replacement costs. • High installation costs. • Poor ancillary equipment reliability of grid tie inverters and storage methods, e.g., batteries, although PVs are highly reliable if maintained (cleaned and protected). • Lack of commercial storage facilities. • Accelerated sunlight ageing of associated synthetic materials. • Local weather patterns and sun conditions directly affect the potential of photovoltaic systems. Some locations will not be able to use solar power. There are two disadvantages often used by environmentalist concerning high-tech PVs: • Production Pollution:- Fossil fuels are extensively utilized to extract, produce and transport PV panels. These processes also entail corresponding sources of pollution. The life cycle analysis of a PV system is a net positive for the environment because it can offset fossil fuel energy production over its approximately 25-year lifetime. • High energy cost:- Require much energy to produce. The three types of photovoltaic (PV) materials, which make up the majority of the active PV market: single crystal, polycrystalline, and amorphous silicon PV cells pay for themselves in terms of energy in a few years (1 to 5 years). They thus generate enough energy over their lifetimes to reproduce themselves many times (6 to 31 reproductions) depending on what type of material, balance of system, and the geographic location of the system.

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Table 22.14: Summary of PV cell technology (AR: - antireflective coating) Material

Thickness

Mono-crystalline Si

300µm

Polycrystalline Si

300µm

Polycrystalline transparent Si

300µm

Dark blue, black with AR coating, 15-18% grey without AR coating Blue, with AR coating, 13-15% silver-grey without AR coating Blue, with AR coating, 10% silver-grey without AR coating

Edge defined Film fed Growth EFG

280µm

14%

Polycrystalline ribbon Si

300µm

12%

Apex (polycrystalline Si)

30 to 100µm + ceramic substrate

9.5%

Monocrystalline dendritic web Si

130µm incl contacts

Amorphous silicon Cadmium Telluride (CdTe) Copper-Indium-Diselenide (CIS)

0.1µm + 1 to 3mm substrate 8µm + 3mm glass substrate 3µm + 3mm glass substrate 20µm

Hybrid silicon (HIT)

Colour

Efficiency

Blue, with AR coating Blue, with AR coating, silver-grey without AR coating Blue, with AR coating, silver-grey without AR coating

13%

Blue, with AR coating

5-8%

Red-blue, Black

6-9% (module)

8-10% (module)

18%

Features Lengthy production procedure - wafer sawing necessary. Highly researched PV cell material. Highest power/area ratio. Wafer sawing necessary. Currently the most important production procedure. Lower efficiency than monocrystalline PV cells. Limited use of this production procedure. Very fast crystal growth, no wafer sawing necessary . Limited use of this production procedure, no wafer sawing necessary. Decrease in production costs expected. Single source wafer production procedure, no wafer sawing, production in form of band possible. Significant decrease in production costs. Limited use of this production procedure, no wafer sawing, production in form of band possible. Lower efficiency, shorter life span. No sawing necessary, production in the form of band.

Dark green, Black

Poisonous raw materials. High production costs.

Black

Limited indium supply in nature. High production costs.

Dark blue, black

Limited use of this production procedure, higher efficiency, better temperature coefficient, and lower thickness.

Problems 22.1 Consider the decomposition of H2O2 (hydrogen peroxide) at 298 K and 1 atm pressure according to: 2 H2O2(l) ↔ 2 H2O(l) + O2(g) Substance H2O2(l) H2O(l) O2(g)

∆Gfo kJ/mol -120.2 -237.0 -

∆Hfo kJ/mol -187.6 -285.8 -

So J/ K.mol 109.5 69.4 205

Find the a) standard enthalpy of reaction. b) standard entropy of reaction. [-196.4 kJ; 125 J/K] 22.2. For the reaction in the previous question, find the a) standard (Gibbs) free energy of reaction b) the value of the (thermodynamic) equilibrium constant at 298 K, 1 atm [ -233.6 kJ; 8.85 x 1040] 22.3. Carbon monoxide in the atmosphere slowly converts to carbon dioxide at normal atmospheric temperatures according to: CO(g) + ½ O2(g) ↔ CO2(g) The standard enthalpy of reaction is -284 kJ and the standard entropy of reaction is -87 J/K. Estimate the temperature at which the equilibrium begins to favour the decomposition of CO2. Assume that the enthalpy and the entropy of reaction are not affected by temperature. [3260 K or 3300 K] 22.4. Indicate if TRUE or FALSE:

Reading list http://www.mpoweruk.com/ http://science.howstuffworks.com/solar-cell3.htm http://photovoltaics.sandia.gov/ http://americanhistory.si.edu/fuelcells/index.htm

The entropy of a gas increases with increasing temperature. The energy of a perfect crystal is zero at 0 K. Spontaneous processes always increase the entropy of the reacting system. All spontaneous processes release heat to the surroundings. An endothermic reaction is more likely to be spontaneous at high temperatures than at low temperatures. The entropy of sugar decreases as it precipitates from an aqueous solution. [T F F F T T] 22.5. For each type of fuel cell below, what are the charge carrying species, i.e., electrolyte type?

http://en.wikipedia.org/wiki/Solar_cell

(a) Polymeric exchange membrane (b) Immobilised alkaline solution (c) Direct methanol (d) Phosphoric acid (e) Molten carbonate (f) Ceramic solid oxide

http://www.pvresources.com/en/technologies.php

[ H+, OH–, H+, H+, CO32–, O2–]

http://www1.eere.energy.gov http://www.fctec.com/fctec_basics.asp

http://www.doitpoms.ac.uk/tlplib/index.php http://www.fuelcells.org/info/

22.6. Which cells in question 22.5 are able to internally reform? [High temperature, molten carbonate and solid oxide cells.]

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Power Electronics

22.7. The efficiency limit (voltage) of H2 cells reduces as operating temperature is increased. Why are high efficiency systems often run at high temperatures? [The heat produced can be more useful than the efficiency gained at lower temperatures. Running a system at a higher temperature allows the hot exhaust gasses to be utilised in a turbine-hybrid system, raising the overall efficiency of the system can be in excess of 80%.] 22.8. Give two reasons why fuel cells are not currently used in cars. [(i) High temperature fuel cells are not easily portable and low temperature ones require hydrogen as the fuel in order to produce any useful power. Hydrogen is not yet a readily available fuel. It is also difficult to store. (ii) Fuel cells also suffer from low reaction rates and therefore low power output.] 22.9. Why are nickel anodes used in SOFCs? How is it treated in order to aid bonding to YSZ? [It is cheap and although it functions effectively, it flakes off unless mixed with zirconia.] 22.10. Give three ways to provide a mobile fuel cell with pure hydrogen. [(i) Pure H2 may be stored as used either under pressure, cryogenically, in a metal hydride, in a high surface area carbon nano-tube arrangement or even in glass nano-spheres. (ii) Many fuels may be carried and reformed before use e.g. alcohols, alkali metal hydrides, ammonia, sodium borohydride, methane and even hydrazine. (iii) Alternately the cell could be run directly on methanol.]

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Chapter 23

CHAPTER

Secondary Energy Sources

1000

Primary electrochemical cell: The electrochemical reaction is not reversible. During discharge, the chemical compounds are permanently changed and electrical energy and heat are released until the original compounds, or any one of them, are depleted. A primary cell is assemble in the charged state, discharged during utilisation, used only once until discharged, then discarded, possibly involving recycling of components. Secondary electrochemical cell: The electrochemical reaction is reversible and the original chemical compounds can be reconstituted by the application of an electrical potential between the electrodes injecting energy into the cell. The cell discharge and charge current directions are opposite. A secondary cell can be discharged and recharged many times. It is usually assembled in a discharged state and has to be charged before under-going discharged.

23

Energy Sources and Storage -

Batteries come in a wide range of types, sizes and shapes, from wafer-thin to button-size devices to large industrial battery systems. All can be categorised as either primary storage or secondary storage batteries. Batteries function best at room temperature (expect lithium polymer batteries) and elevated temperature operation dramatically increases the internal resistance and shortens battery lifetime. Primary Batteries

Secondary Sources

Primary batteries have the following properties: • • • • •

Designed as a single use battery, used until exhausted then discarded or recycled after depletion High impedance which translates to long-life energy storage, and for low current loads Available in carbon-zinc, alkaline, silver oxide, lithium, zinc air and some lithium metal batteries (like lithium-thionyl-chloride) Lithium-thionyl-chloride batteries, for example, come in cylindrical form factors of AAA to D. Larger C and D size lithium-thionyl-chloride batteries are a chemical hazard and are restricted when transported by air Operating temperature range is typically -40ºC to +85ºC

Although primary cells may consist of the same active materials as secondary battery types, they are constructed so that only one continuous or intermittent discharge can be obtained. Secondary Batteries The progressive proliferation of embedded and distributed generation with renewable energy sources has spurred research into alternative energy sources and storage methods. This chapter is concerned with secondary energy sources, viz., so called super or double-layer capacitors, electro-chemical batteries, and thermoelectric modules. Their energy and power density capabilities (and those of primary electrical sources) have been put into context by considering conventional energy sources in Chapter 22.1, specifically the hydrocarbons and hydrogen gas. In electrical terms, primary and secondary energy sources are defined as follows. Primary source is not a reversible energy source. During energy discharge, the original states are permanently changed as electrical energy is released until the original energy reactant sources, or any one of them, are depleted. A primary cell can be used only once. Secondary source is reversible and the original states can be reconstituted by the application of an electrical potential that injects conversion energy into the source. A secondary cell can source and sink energy many times. 23.1

Batteries

An electrochemical battery cell is an ‘electron pump’ that stores energy in chemical form in its active materials and can convert this stored chemical energy to electrical energy on demand, typically by means of an electrochemical oxidation-reduction reaction or a physical reaction. This energy conversion is achieved by a chemical reaction in the battery that releases electrons. If a load is placed across the battery terminals, the chemical reaction produces electrical power. The process can be reversible. If electrical energy is directed into the battery (charging the battery), the chemical reaction reverses and restores the battery to a fully charged condition. Cells are classified as either primary cells or secondary cells, depending on whether or not the electrochemical cell is rechargeable.

BWW

Secondary batteries are recharged by a flow of direct current through them in a direction opposite to the current flow on discharge. By recharging after discharge, a higher state of oxidation is created at the positive electrode plate (cathode) and a lower state at the negative electrode plate (anode), returning the plates to approximately their original charged condition. Secondary batteries have the following properties: • Designed to be recharged • Can be recharged up to 1,000 times depending on the usage and battery type • Very deep discharges result in a shorter cycle life, whereas shorter discharges result in long cycle life for most secondary batteries • Charge time varies from one to twelve hours, depending upon battery condition, temperature, depth of discharge, and other factors • Include NiCd, lead-acid, NiMH, some lithium metal and Li-ion batteries • Lead-Acid and NiCd batteries are toxic and are subject to disposal regulations Some of the general limitations suffered by secondary batteries are limited life, limited power capability, low energy-efficiency, and disposal concerns. The secondary cell is the subject of this section. The primary cell is not specifically considered further. 23.2

The secondary electro-chemical cell

Each electro-chemical energy cell consists of at least three, sometimes four, components • The cathode or positive electrode (the oxidising electrode) accepts electrons from the external circuit and is chemically reduced during the electrochemical (discharge) reaction. It is usually a metallic oxide or a sulphide. The cathodic process is the reduction of the oxide ion - anion - to leave the metal. (To gain or to accept electrons is termed reduction). The cathode is the half-cell with the higher electrode potential.

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•

•

•

Chapter 23

and concentrations of the reactants and products. The Nernst equation (E = Eo – RT/nF×ℓnN, see Chapter 22.14, equation (22.18) and Chapter 23.8, equation (23.10)) can be used to calculate the EMF for non-standard cell conditions. The cell EMF decreases as the concentration of the active chemicals diminishes as they are consumed, until one of the reactants is exhausted. The half-cell zero reference potential is defined to be zero for the hydrogen electrode. All the equations are written as reductions. The two half-reaction potentials add to give the overall cell potential. The alkaline half-cell reactions, during discharge, for example, are shown in Table 23.1.

The anode or negative electrode (the reducing or fuel electrode) gives up electrons to the external circuit and is oxidised during the electrochemical (discharge) reaction. It is generally a metal or an alloy. The anodic process is the oxidation of the metal to form metal ions - cations. (To lose or to supply electrons is termed oxidation). The anode is the half-cell with the lower (least positive) electrode potential. The electrolyte (the ionic conductor) provides the medium for transfer of charge in the form of ions inside the cell in either direction between the cathode and anode. The electrolyte is typically a solvent containing dissolved chemicals providing ionic conductivity. It should be a non-conductor of electrons to avoid internal self-discharge of the cell. The separator electrically isolates the positive and negative electrodes but allows ions to travel back and forth in the electrolyte, between the electrodes.

Table 23.1: Half-cell electro-chemical equations for the alkaline cell

iii. Half-cell reaction Chemical reactions occur on both the anode electrode and the cathode electrode. Half cell reaction refers to the chemical processes occurring at each electrode (half-reactions), namely the negative anode and the positive cathode. The cell is modelled as two half-cells. Gibbs free energy equation (∆G = -nFEo, see Chapter 22.14, equation (22.14) and Chapter 23.8, equation (23.9)) is used to calculate electrode potentials and characterise the chemical reactions within the cell. The cell voltage or EMF to force the external current from a cell is the difference in the standard electrode potentials of the two half-cell reactions under standard conditions. The actual voltage of a chemical cell is dependant on the temperature, pressure,

185A-hr/kg

Anode - oxidation

Negative terminal Zn(s) + 2OH-(aq) → ZnO(s) + H2O + 2e-

Cathode - reduction

Positive terminal

Net REDOX reaction

Potential

E ½−cell = + 0.76V

2MnO2(s) + H2O + 2e- → Mn2O3(s) + 2OH-(aq)

E ½+cell = +2.31V

Zn(s) + 2MnO2(s) → ZnO(s) + Mn2O3(s)

o E cell = 1.55V

The cell potential under standard conditions (25°C, 1 mole, 1 Atmosphere) is o o o E cell = E ½+cell − E ½−cell = E cathode − E anode

23.2.1 REDOX Galvanic Action Galvanic action is when chemical reactions produce electricity, while electrolysis is the reverse process where electricity is used to produce chemicals. Different metals have different affinities for electrons. When two dissimilar metals (or metal compounds) are put in contact or connected through a conducting medium there is a tendency for electrons to pass from the metal with the smaller affinity for electrons, which becomes positively charged, to the metal with the greater electron affinity which becomes negatively charged. A potential difference between the metals will therefore build up until it just balances the tendency of the electron transfer between the metals. At this point, the ‘equilibrium potential’ is that which balances the difference between the propensity of the two metals to gain or lose electrons. A battery can be considered as an electron pump. The internal chemical reaction within the cell between the electrolyte and the negative metal electrode produces a build-up of free electrons, each with a negative charge, at the cell's negative terminal - the anode. The chemical reaction between the electrolyte and the positive electrode (the cathode) inside the cell produces an excess of positive ions (atoms that are missing electrons, thus with a net positive charge) at the cell cathode. The electrical (pump) pressure or potential difference between the positive and negative electrodes is called voltage or electromotive force, EMF.

ii. The Charging Process The charging process strips electrons from the cathode leaving it with a net positive charge and forces them onto the anode giving it a negative charge. The electrical energy pumped into the cell transforms the active chemicals back to their original state.

Reaction (discharge)

Location

The operation of lead-acid and nickel-cadmium batteries are based on oxidation and reduction chemistry, called REDOX. The nickel-metal-hydride and lithium-ion batteries are not based on REDOX reactions, but rather involve an ion transfer mechanism called intercalation, which is the insertion and extraction of ions into and out of the crystalline lattice of an electrode, without chemically altering its crystal structure.

(23.1)

The half-cell equations are reversed during cell charging, although the standard alkaline cell may not be rechargeable, that is primary and secondary variations exist. Table 23.2: Strength of Oxidizing and Reducing Agents (25°C, 1 mol, 1 Atmosphere) Anode Materials

Cathode Materials

(Negative Terminal)

(Positive Terminal)

BEST - Most Negative Standard Cathode (Reduction) Potential Half-cell Reaction E ½o (V)

BEST Most Positive

Li+(aq) + e− Æ Li(s) K+(aq)

Increasing activity

i. The Discharge Process When the cell is fully charged there is a surplus of electrons on the anode giving it a negative charge and an electron deficiency on the cathode giving it a positive charge, resulting in a potential difference between the cell electrodes. When the external electrical circuit is completed the surplus electrons flow in the external circuit from the negatively charged anode which loses its charge to the positively charged cathode which accepts it, neutralising its positive charge. This action reduces the potential difference across the cell to zero. The external circuit electron flow is balanced by the internal flow of positive ions through the electrolyte from the anode to the cathode. Since the electrons are negatively charged, the electrical current they conventionally represent flows in the opposite direction, from the cathode (positive terminal) to the anode (negative terminal). The battery’s chemical reaction continues to generate electrical current until at least one of the active materials involved in the reaction is depleted or the external load connection is removed.

1002


−

Standard Potential E ½o (V)

Cathode (Reduction) Half-cell Reaction F2(g) + 2e− Æ 2F−(aq)

-3.045

+ 4H+ + 2e− Æ MnO2(s) + 2H2O

+2.87

-2.925

MnO42−

Ca2+(aq) + 2e− Æ Ca(s)

-2.766

Co3O4(s) + 8H+ + 2e− Æ Co2+ + 4H2O

Mg2+(aq)

-2.353

PbO2(s) + SO42−(aq) + 4H+(aq) + 2e− Æ PbSO4(s)+ 2H2O(l)

+1.685

Al3+(aq) + 3e− Æ Al(s)

-1.66

FeO42− + 6H+ + 3e− Æ Fe(OH)2+ + 2H2O

+1.56

Zn2+(aq)

+ 2e Æ Zn(s)

-0.763

Fe2+(aq) + 2e− Æ Fe(s)

-0.440

Ni2+(aq) + 2e− Æ Ni(s)

+ e Æ K(s) −

+ 2e Æ Mg(s) −

MnO2 + 4H+ + 2e− Æ Mn2+ + 2H2O O2(g) + 4H+ + 4e− Æ 2H2O

+2.257 +2.11

+1.23 +1.229

-0.250

Ag2O(s) + 2H+ + 2e− Æ 2Ag(s) + H2O

+1.173

−

-0.126

HgO(s) + 2H+ + 2e− Æ Hg(l) + H2O

+0.93

2H+ + 2e− Æ H2(g)

0.00

CuO(s) + 2H+ + e− Æ Cu+ + H2O

+0.62

Pb2+(aq)

+ 2e Æ Pb(s)

Cu2+(aq) + 2e− Æ Cu(s)

+0.337

NiOOH + H2O + e− Æ Ni(OH)2 + OH−

+0.49

Ag+(aq) + e− Æ Ag(s)

+0.799

NiO2(s) + 2H2O + 2e− Æ Ni(OH)2(s) + 2OH−

+0.49

iv. Choice of Active Cell Chemicals The voltage and current generated by a galvanic cell is directly related to the types of chemical materials used for the electrodes and electrolyte. The propensity of an individual metal or metal compound to gain or lose electrons in relation to another material is known as its electrode potential. Thus the strengths of oxidizing and reducing agents are indicated by their standard electrode potentials. Compounds with a positive electrode potential are used for anodes and those with a negative electrode potential for cathodes. The larger the difference between the electrode potentials of the anode and cathode, the greater the EMF of the cell and generally the greater the amount of energy that can be produced by the cell.

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Power Electronics

Chapter 23

The Electrochemical Series is a table of metallic elements or ions arranged according to their electrode potentials, as shown in Table 23.2. The order shows the tendency of one metal to reduce the ions of any other metal below it in the series, at 25°C, standard pressure and 1mol of reactant. Table 23.2 shows some common chemicals used for battery electrodes arranged in order of their relative electrode potentials. Lithium has the most negative standard potential, -3.045V, indicating that it is the strongest reducing agent. The strongest practical oxidizing agent is fluorine with the largest positive standard electrode potential of +2.87V. Although halogen acids have high electrode potentials, they are usually too aggressive with the electrodes to be used in normal cells. Metals are commonly used in cells as anode materials, but the cathode is commonly an oxide. That is, in Table 23.2, metals appear in the left columns while oxides appear in the right columns. v. Gassing Cells using aqueous (containing water) electrolytes are limited in voltage to less than 2.4V because the oxygen and hydrogen in water dissociate producing H2 and O2 in the presence of voltages above this voltage. Lithium batteries use non-aqueous electrolytes hence do not have dissociation problems and are available in voltages between 2.7V and 3.7V. However, the use of non-aqueous electrolytes results in such cells having relatively high internal impedance. 23.2.2 Intercalation Action From intercalation process studies, it is known that small ions (such as ions of lithium, sodium, and the other alkali metals) can fit in the interstitial spaces of a carbon graphite lattice crystal. These metallic molecules force the graphitic planes apart to fit numerous layers of metallic molecules between the carbon sheets. This is an efficient way to store the metal-ion in a battery. The anode of a conventional alkali metal-ion cell is made from graphite (carbon), the cathode is a metal oxide, and the electrolyte is a metal salt in an organic solvent. Both the anode and cathode are materials into which metal-ions insert and extract, termed intercalation. The process of metal-ions moving into the anode or cathode lattice is referred to as insertion, and the reverse process, in which metal-ions move out of the anode or cathode is referred to as extraction. Using lithium as an example, the underlying chemical reaction that allows Li-ion cells to provide electricity (equations to the right) are: anode C 6Li + xLi + + xe − R C 6Li 1+ x negative electrode 0.1V wrt Li

LiCoO 2( s ) R Li 1− x CoO 2(s ) + xLi + + xe −

cathode

positive electrode

3.8V wrt Li

C 6LI + LiCoO 2 R Li 1− x CoO 2 + C 6Li 1+ x

3.7V net

Lithium-ion secondary rechargeable battery Charge mechanism

discharge mechanism

separator

+

Li Li+

Li

+

+

+

cathode

Li

+

Li

+

-

separator

+

Li

+

LixC6

+

polymer gel electrolyte

(b)

Figure 23.1. Cells charge mechanism and discharge mechanism.

The lithium-ions are not oxidized; rather, they are transported to and from the cathode or anode, with the transition metal, cobalt, in LiCoO2 being oxidized from Co3+ to Co 4+ during charging, and reduced from Co 4+ to Co3+ during discharge. At no stage is any alkali lithium metal present or involved. The intercalation host electrodes have two key properties • Open crystal structures which allow the insertion and extraction of alkali metal-ions • The ability to simultaneously accept compensating electrons - conductive When discharging a cell, the metal-ions are extracted from the anode and inserted into the cathode, via the electrolyte, as shown in figure 23.1b. That is, alkali metal ions move through the electrolyte from the negative electrode to the positive electrode and attach to the carbon. The electrolyte is non-conducting to electrons. At the same time compensating electrons, which form the external circuit current, transfer from the positive to the negative electrodes, and are accepted by the internally arriving metal-ions, thereby balancing the equation. When charging the cell, the reverse process occurs: metal-ions are extracted from the cathode and inserted into the anode, as shown in figure 23.1a. The metal ions move back to the anode from the carbon cathode, while external current electrons flow from the negative to positive electrodes. The anode graphite is a two-dimensional crystal structure, which under charging, is forced to laterally shift and simultaneously strain to 10% greater separation to accommodate the Li-ions. The lattice deformation is relieved when Li-ions are removed from the anode under cell discharge. 23.3

Characteristics of Secondary Batteries

A wide range of secondary batteries exists, each offering different attributes, limitations, properties, etc. The four secondary batteries to be considered are • Lead-acid • Nickel-cadmium • Nickel-metal-hydride • Lithium-ion Electrochemical lead-acid and nickel-cadmium battery technologies are mature. The lead-acid battery is economical for high power applications where weight is of little concern. It is an inexpensive, robust technology, found extensively in automotive applications and UPS equipment. The nickel-cadmium battery has a higher energy density than the lead acid battery, and offers longer lifetimes, higher discharge rates and a wider operating temperature range than the lead-acid battery. The nickelcadmium battery contains toxic metals, and is used in power tool applications. The nickel-metal-hydride battery trades a higher energy density than nickel-cadmium for reduced cycle life. Importantly it uses non-toxic metals, and is used in satellites, mobile phones and laptops. Lithiumion, a newer developing technology, offers higher again energy densities, but cell series connection poses sharing and balancing problems. Because of its high energy density properties, lithium-ion is increasingly being used in notebook computers, mobile phones, and power tools. Key technology properties and features of different battery technologies are summarised in tables 23.3a and 23.3b.

cathode

Table 23.3a. Anode capabilities of different metals

+

+

Li1-xCoO2 (a)

Li

+

Li

polymer gel electrolyte

anode

separator

Li

LixC6

electrons

electrons

separato

conventional current

conventional current

-

anode

1004


+

Li

+

Li

+

Li

+

Li

+

Li

+

Li

+

Li

+

Li

Li1-xCoO2

Anode

Symbol

Atomic Mass g

Standard Potential V

Density g/cm3

Melting Point °C

Electrochemical Equivalence Ah/g

Lithium

Li

6.94

-3.05

0.54

180

3.86

Sodium

Na

23.0

-2.7

0.97

97.8

1.16

Magnesium

Mg

24.3

-2.4

1.74

650

2.20

Aluminium

Aℓ

26.9

-1.7

2.7

659

2.98

Calcium

Ca

40.1

-2.87

1.54

851

1.34

Iron

Fe

55.8

-0.44

7.85

1528

0.96

Zinc

Zn

65.4

-0.76

7.1

419

0.82

Cadmium

Cd

112

-0.40

8.65

321

0.48

Lead

Pb

207

-0.13

11.3

327

0.26

1005

Power Electronics

Chapter 23

Table 23.3b: Basic comparison of different battery characteristics and technologies

In Table 23.3a, lithium is the lightest metal, and has the highest standard potential. Lithium metal is volatile (with water and nitrogen in air) and has a low reactivity with many cathode materials and nonaqueous electrolytes. Because of the energy density potential offered by lithium-ion technologies, different cathode material types have emerged. Three key performance aspects should be defined, namely power density, energy density, and capacity. i. Power density (specific power): Volumetric Power density is the ratio of the power available from a battery to its volume (W/litre). Specific power (or gravimetric power density) refers to the ratio of power to mass (W/kg). Comparison of power to cell mass is more common. Power Density (W/kg) indicates how much power a battery can deliver on demand. Manganese and phosphate-based lithium-ion, as well as nickel-based chemistries, give the best performance. High power density cell uses are power tools, medical devices and transportation systems. The focus is on power bursts, such as drilling through heavy steel, rather than runtime. ii. Energy density (specific energy): Volumetric Energy density refers to the ratio of a battery's available energy to its volume (Wh/litre). Specific energy (or gravimetric energy density) refers to the ratio of energy to mass (Wh/kg). The energy W is determined by the charge q that can be stored and the cell voltage E, that is, W = q×E. Energy Density (Wh/kg) is a measure of how much energy a battery can retain or store. The higher the energy density, the longer the possible runtime. Cell size and its chemistry determine energy storage density. Lithium-ion cells with cobalt cathodes offer the highest energy densities, 190Wh/kg. Typical applications are cell phones, laptops and digital cameras. An Ah/kg rating can be determined from the cell standard voltage, E and energy density rating Wh/kg, while power and energy densities are related by time, W = P×t, as shown in figure 23.2. An analogy between energy and power densities can be made with a water bottle. The size of the bottle is the energy density, while the opening area denotes the power density. A large volume bottle can carry a lot of water (energy), while a large opening can pour it quickly (power). A large container (energy) with a wide area mouth (power) is the best combination. Table 23.3 shows some typical relative energy and power per unit weight examples of common secondary cell chemistries. In general, higher energy densities are obtained by using more reactive chemicals. But reactive chemicals tend to be unstable and require safety precautions. The energy density is also dependent on the quality of the active materials used in the cell construction, with impurities limiting cell capacity.

Lead-acid

gravimetric energy density volumetric energy density power density cell voltage (theoretical) internal resistance

Battery capacity varies with the discharge rate. The higher the discharge rate, the lower the cell capacity. Fast charging or discharging can generate heat inside the battery that lowers its chemical efficiency, hence reduces its effective capacity. Lower discharge rates result in higher capacity, but very slow charging or discharging can also give lower effective capacity since all batteries suffer from internal self-discharging effects. Batteries are normally specified at several discharge rates (in amperes) along with the associated discharge time (in hours). The capacity of the battery for each of the discharge rates can be calculated as discussed above. The lead-acid battery does not perform well at a 1C discharge rate (discharged in one hour). The rated capacity for lead-acid batteries is usually specified at 10 or 20-hour rates (C/10, C/20). UPS batteries are rated at 8-hour capacities and telecommunications batteries are rated at 10-hour capacities.

Wh/kg

Nickelcadmium

sealed

sealed

30-50

45-70

Alkaline 80

90-120

220-350

270

170

50

250-1000

760

1800

1400

1.5

1.25

3.6

3.7

3.3

20

30

40

100

50

35

5 0.2 80%

20 1 100%

½ < 0.2

5 0.5 80%

35 100

N

3.4

4.9

LiBF6

151.9

>80

N

5.8

10.7

LiAsF6

195.9

>100

N

5.7

11.1

LiCℓO4

106.4

>100

N

5.6

8.4

Li Triphlate

155.9

>100

Y

1.7

Li Imide

286.9

>100

Y

5.1

1052


since the electrodes take up more space within the can there is less room for the electrolyte and so the potential energy storage capacity of the cell is reduced. This construction is used extensively for secondary cells. Figure 23.37 shows a Lithium-ion cell but this technology is also used for NiCd, NiMH and even some Lead-acid secondary cells designed for high rate applications. A spiral wound construction not limited to cylindrical shapes. The electrodes can be wound onto a flat mandrel to provide a flattened shape, which can fit inside a prismatic case. The cases may be made from aluminium or steel. This capacitor type of construction is ideally suited for production automation. positive external terminal gasket

resettable PTC switch

vent

top insulator 9.0 cathode tab

Liquid or gel electrolytes in Li-ion batteries consist of solid lithium-salt electrolytes, such as LiPF6, (although this has a problem with aluminium corrosion), LiBF4, or LiCℓO4, and liquid organic solvents, such as ether. The exact composition of the non-aqueous solvents varies (see Table 23.18X), but propylene carbonate (PC) – dimethyl ether is used for primary cells and ethylene carbonate (EC) with linear organic carbonates such as dimethyl carbonate (DMC), diethyl carbonate, and ethylmethyl carbonate are used in secondary cells. A liquid electrolyte conducts Li ions, which act as a carrier between the cathode and the anode when a battery produces an electric current through an external circuit. However, solid electrolytes and organic solvents are easily decomposed on the highly reactive anodes during charging, thus preventing battery activation. Nevertheless, when appropriate organic solvents are used for electrolytes, they are decomposed and form a solid electrolyte anode passivation interface layer (solid electrolyte interface) at first charge that is electrically insulating and imposes resistance to Li-ion conduction. The interface prevents decomposition of the electrolyte after the second charge but the layer limits the discharge rates and renders the battery unchargeable at low cold temperatures. For example, microporous polyethylene membranes such as ethylene carbonate, are decomposed at a relatively high voltage, (in contrast to only 0.7V for lithium), and forms a dense and stable interface, which separate the electrons from the ions. The electrolyte interface breaks down at about 120°C, at which temperature the highly reactive anode reacts with the electrolyte, producing excessive heat in a thermally runaway process. Since lithium reacts with water, the electrolyte is a non-aqueous organic lithium salt. Thus, unlike the lead-acid cell that uses water, no hydrogen or oxygen gases are produce by the Lithium-ion cell. Depending on the choice of material for the anode, cathode, and electrolyte, the voltage, capacity, life, and safety of a lithium-ion battery can vary dramatically. Adding more nickel in lieu of cobalt increases the ampere/hours rating and lowers the manufacturing cost but makes the cell less stable. ii. Construction As with most batteries there is an outer case made of a non-reactive metal. The use of metal is particularly important because the battery is pressurized. This metal case has a pressure-sensitive vent hole. If the battery ever gets so hot that it risks exploding from over-pressure, this vent releases the excess pressure. The battery becomes ineffective, so venting is to be avoided. The vent is a safety measure, as is the resettable terminal Positive Temperature Coefficient (PTC) switch, which prevents the battery from overheating. This cell chemistry and construction permits very thin separators between the electrodes that are made with high surface areas. This enables the cells to handle the high current rates necessary in high power applications. The metal case holds a long spiral comprising three thin sheets pressed together, not unlike a capacitor: • A positive electrode • A negative electrode • A separator The sheets are immersed in an organic solvent like ether that acts as the electrolyte. The separator is a thin sheet of microperforated polyethylene plastic, which separates the positive and negative electrodes while allowing ions to pass, but blocks internal electron migration. Spiral Wound Cylindrical Cell In order to increase current carrying capacity, it is necessary to increase the active surface area of the electrodes, however the cell case size sets limits on the size of electrodes which can be accommodated. One way of increasing the electrode surface area is to make the electrodes and the separator from long strips of foil and roll them into a spiral cylindrical shape. This provides low internal resistance cells. But

anode negative electrode

anode negative terminal steel can

separator cathode positive electrode

bottom insulator cathode

Figure 23.37. Spiral Cylindrically Wound Electrodes.

23.7.1

Cathode variants cells

i. The Lithium-Cobalt oxide Cell - LiCoO2 As shown in Table 23.16, the lithium-cobalt oxide cell voltage is typically 3.7V to 3.9V, and the half-cell reactions are shown in the following table. Half-Reaction (charge)

Location Anode

Negative terminal

C6Li + xLi+ + xe- → C6Li 1+x

Cathode

Positive terminal

LiCoO2 → Li1-xCoO2 + xLi+ + xe-

Net

C6Li + LiCoO2 → Li1-xCoO2 +C6Li1+x

Most lithium-ion batteries for portable applications are cobalt-based. The cell system consists of a cobalt oxide positive electrode (cathode) and a graphite carbon as the negative electrode (anode). Figure 23.38a illustrates the layered crystalline structure of cobalt oxide. An advantage of the cobalt-based battery is its high energy density, typically 140Ah/kg and energy of 500Wh/kg. A long run-time makes this chemistry attractive for cell phones, laptops, and cameras. The widely used cobalt-based lithium-ion has drawbacks; it offers a relatively low discharge current. A high load would overheat the pack, jeopardizing its safety. The safety circuit of the cobalt-based battery typically limits the charge and discharge rate to about 1C. Another drawback is the internal resistance increase that occurs with cycling and ageing. After 2 to 3 years of use, the battery often becomes unserviceable due to a large voltage drop under load caused by a high internal resistance. The use of cobalt is unfortunately associated with environmental and toxic hazards. ii. The Lithium-Manganese oxide Cell - LiMn2O4 Lithium manganese oxide, termed spinel, used as a cathode material, produces a 4V cell voltage with an energy density of better than 100Ah/kg and energy of 580Wh/kg. This substance forms a threedimensional spinel structure that improves the lithium ion flow between the electrodes, as shown in figure 23.38b. High ion flow lowers the internal resistance and increases current capability. The resistance remains low with cycling, however, the cell does age and the overall service life is similar to that of lithium-cobalt. Spinel has an inherently high thermal stability and needs simpler cell safety circuitry than a lithium-cobalt battery. The low internal cell resistance characteristic benefits fast-

1053

Power Electronics

Chapter 23

charging and high-current discharging. A spinel-based lithium-ion cell has ten times the current capability of the equivalent volume lithium-cobalt cell, with marginal heat build-up. One-second current pulses of twice the specified current are permissible. Some heat build-up cannot be prevented and the cell temperature should not exceed 80°C. C6Li + LiMn2O4 ⇄ Li1-xMn2O4 + C6Li1+x One significant drawback of the spinel cell is the lower energy capacity, approximately half, compared to the cobalt-based cell. But spinel still provides an energy density that is about 50% higher than that of a nickel-based equivalent. Manganese, unlike Cobalt, is a safe and more environmentally benign cathode material. iii. The Lithium-nickel-cobalt-manganese Cell – Li(NiCoMn)O2 The tri-element cathode incorporates nickel, cobalt and manganese (NCM) in the crystal structure that forms a multi-metal oxide material to which lithium is added. It is not possible to achieve a high energy density and high load capability in the same package; there is a compromise between the two. A NCM cell charges to 4.10V/cell, 100mV less than cobalt and spinel. Charging to 4.20V/cell provides higher capacities but the cycle life is more than halved, from 800 cycles to about 300.

1054

withstand high temperatures without decomposing. When abused, the phosphate based cathode material does not burn and is not prone to thermal runaway. Phosphate chemistry also offers a longer cycle life. v. The Lithium-Polymer Cell The most economical lithium-ion battery in terms of cost-to-energy ratio is cylindrical. Such cells are used for mobile computing and other applications that do not demand an ultra-thin prismatic (rectangular) geometry. If a slim pack is required, the prismatic lithium-polymer cell or alternatively the lithium-ion polymer cell, are the best choices but come at a higher cost in terms of stored energy. The lithium-polymer differentiates itself from conventional battery systems in the type of electrolyte used, as shown in figure 23.39. The lithium-polymer electrochemistry uses active materials such as LiCoO2, LiNiO2 and its Co doped derivatives, but generally not LiCoO2 chemistry. The dry solid polymer electrolyte resembles a plastic-like film that does not conduct electricity but allows ion exchange (electrically charged atoms or groups of atoms). The polymer electrolyte replaces the traditional porous separator, soaked with electrolyte. The dry solid polymer cell depends on heat to enable sufficient ion flow. This requires that the battery core be kept at an operation temperature above room temperature, 60°C to 100°C. Aluminium mesh

cobalt oxide CoO2

Positive electrode – plastic cathode

lithium ions Li+

Plastic electrolyte or separator Negative electrode – plastic anode

manganese oxide MnO2

(a)


Copper mesh

charge extraction

Figure 23.39. Lithium polymer cell construction layers.

(b)

When lithium polymer cells are first charged, lithium ions are transferred from the layers of the lithium cobaltite to the carbon material that forms the anode, according to: LiCoO 2 + 6C → Li 1− x CoO 2 + LixC 6 Subsequent discharge and charge reactions are based on the motion of lithium ions Li+ between the insertion anode and cathode electrodes. Li 1- x CoO 2 + Li x C ↔ Li 1-dx CoO 2 + Li x -dx C (c)

Figure 23.38. Cathode (positive electrodes) crystalline structures where during discharge, the lithium ions (shown in green) extracted from the cathode and are inserted in the anode: (a) layered cobalt oxide structure with the lithium ions shown bound to the cobalt oxide, (b) three-dimensional framework lithium manganese oxide structure. This spinel structure, which is usually composed of diamond shapes connected into a lattice, appears after initial formation; giving high conductivity but lower energy density. The lithium-ion flow reverses on cell charge, and (c) olivine structure of LiFePO4.

iv. The Lithium-Phosphate Cell - LiFePO4 Nano-phosphate materials are added to the cathode (shown in figure 23.38c), resulting in the highest power density in W/kg and energy density of 170Ah/kg, of any lithium-ion battery. The cell can be continuously discharged to 100% depth-of-discharge at 35C and can endure discharge pulses as high as 100C. The phosphate-based system has a nominal voltage of about 3.3V/cell and the peak charge voltage is 3.6V. This is lower than the cobalt-based lithium-ion, hence requires a dedicated charger. Phosphate based technology possesses superior thermal and chemical stability which provides better safety characteristics than those of lithium-ion cathode technologies. Lithium phosphate cells are incombustible during charge or discharge, more stable under overcharge or short circuit conditions, and

The dry polymer design offers simplifications with respect to fabrication, ruggedness, long life, safety and thin-profile geometry (flexible form factor), but it is expensive. Unfortunately, the dry lithium-polymer suffers from poor conductivity. To compromise, some gelled electrolyte is added. Cells have a separator/electrolyte membrane with the porous polyethylene or polypropylene separator filled with a polymer, which gels (plasticizes) upon filling with the liquid electrolyte. Thus, the commercial lithium-ion polymer cells are similar in chemistry and materials to their liquid electrolyte counter parts. With a cell thickness measuring less than a millimetre, virtually no restrictions exist in terms of cell form, shape, and size. Lithium-ion-polymer finds its market niche in lightweight, wafer-thin, flexible form-factor geometries, such as batteries for credit cards and other such applications. It is more stable and resistant to over-charge, but is expensive, has a lower energy density, discharge rate and cycle count than lithium-ion, but longer storage life. Advantages and Limitations of Li-ion Polymer Batteries Advantages

• • • • •

Low profile - batteries that resemble the profile of a credit card are feasible. Flexible form factor - manufacturers are not bound by standard cell formats. With high volume, any reasonable size can be produced economically. Light weight - gelled rather than liquid electrolytes enable simplified packaging, in some cases eliminating the metal shell. Improved safety - more resistant to overcharge; less chance for electrolyte leakage.

1055

Power Electronics

Limitations

• •

Chapter 23

Table 23.18: Lithium-ion chemistries Lower energy density and decreased cycle count compared to Li-ion - potential for improvements exist. Expensive to manufacture - once mass-produced, the Li-ion polymer has the potential for lower cost. Reduced control circuit offsets higher manufacturing costs.

Chemistry

Table 23.18 highlights a number of other alternative lithium-ion cell cathode types. Li-MnO2 (Li-Mn)

23.7.2

1056


General Lithium-ion Cell characteristics

Lithium-ion load characteristics are similarly to nickel-cadmium in terms of discharge. The high cell voltage of 3.6V allows battery pack designs with only one cell. Most mobile phones use a single cell. Lithium-ion is a low maintenance battery, an advantage that most other chemistries cannot claim. There is no memory and no scheduled cycling is required to prolong battery life. In addition, the self-discharge is less than half that of nickel-cadmium. Lithium-ion has drawbacks, specifically it is fragile and requires a protection circuit to maintain safe operation, as considered in section 23.7.4.

Cathode Heat-treated manganese dioxide

Li-SOCℓ2, BrCℓ, Li-BCX

Nominal voltage

Opencircuit voltage

Wh/kg

Wh/dm3

Lithium perchlorate in propylene carbonate and dimethoxyethane, M Wt 106.4

3V

3.7V

280

580

About 80% of the lithium battery market. Uses inexpensive materials. Suitable for lowdrain, long-life, low-cost applications. High energy density per mass and volume, 650Wh/l. Can deliver high pulse currents. Wide temperature range -40°C to 60°C, max. With discharge the internal impedance rises and the terminal voltage decreases. Thionyl chloride

Li-SOCℓ2

Electrolyte

Lithium aluminium chloride in thionyl chloride

Thionyl chloride with bromine chloride

Lithium aluminium chloride in thionyl chloride

670

3.75V

3.9V

350

770

3.7V

3.95V

330

720-1400

Lithium bromide in sulphur dioxide with small amount of acetonitrile

2.85V

3.0V

250

400

Liquid cathode. Can operate down to -55°C and up to +70°C. Contains liquid SO2 at high pressure. Requires safety vent, can explode in some conditions. High energy density 440Wh/l. High cost. At low temperatures and high currents performs better than Li-MnO2. Toxic. Acetonitrile forms lithium cyanide, and can form hydrogen cyanide in high temperatures. Addition of bromine monochloride can boost the voltage to 3.9V and increase energy density.

Carbon monofluoride Li-(CF)x

290

Liquid cathode. Similar to thionyl chloride. Discharge does not result in build-up of elementa sulphur, which is involved in some hazardous reactions, therefore is safer. The electrolyte tends to corrode the lithium anodes, reducing the shelf life. Chlorine is added to some cells t make them more resistant to abuse. Sulphuryl chloride cells give less maximum current than thionyl chloride, due to polarization of the carbon cathode. Sulphuryl chloride reacts violently with water, releasing hydrogen chloride and sulphuric acid. Sulphur dioxide on teflonbonded carbon

Li-SO2

3.65V

Liquid cathode. A variant of the thionyl chloride battery, with 300 mV higher voltage, which quickly drops back to 3.5V, as the bromine chloride is consumed during the first 10-20% of discharge. Added bromine chloride improve safety when abused. Wide temperature range 55°C to 80°C. 1420Wh/l. Sulphuryl chloride

Li-SO2Cℓ2

3.5V

Liquid cathode. Can operate down to -55°C, where it retains over 50% of its rated capacity. Negligible gas generated in nominal use, limited amount under abuse. Relatively high internal impedance and limited short-circuit current. High energy density, about 500Wh/kg. Toxic. Electrolyte reacts with water. After storage can form anode passivation layer, which leads to temporary voltage delay when first put into service. High cost and safety concerns. Can explode when shorted. Hazardous waste.

Lithium tetrafluoroborate in propylene carbonate, dimethoxyethane, and/or gamma-butyrolactone

2.8V

3.1V

360

680

Cathode material formed by high-temperature intercalation of fluorine gas into graphite powder. High energy density (250Wh/kg), 7 year shelf life. Used for low to moderate current applications, e.g. memory and clock backup batteries. Maximum temperature 85°C. Low self-discharge ( 1, thermoelectric module can be expressed as 1 CoPn = (23.52) n   1  1 +  − 1 n × (CoP1 + ½ ) − ½   assuming that each stage operates over a temperature difference of ∆T/n and CoP1 is applicable to a single stage TEC that operates over ∆T. For example, the CoP of a two-identical-stage module is 1 CoP2 = CoP1 + 8 × ( 2 × CoP1 + 1) The presented equations are simplified but show the basic idea behind the calculations involved. The actual differential equations do not have a closed-form solution because S, R, and K are temperature dependent. Assuming constant properties can lead to significant errors. 23.11.4 Features of Thermoelectric Cooling - Peltier elements The use of thermoelectric modules often provides solutions, and in some cases the only solution, to many difficult thermal management problems where a low to moderate amount of heat must be handled. While no one cooling method is ideal in all respects and the use of thermoelectric modules will not be suitable for every application, TE coolers will often provide substantial advantages over alternative technologies. TE Coolers typically have a CoP of approximately 2, which is lower than the CoP of 3 to 5 of vapour compression refrigerators. The lowest practically achievable temperature is about -100 ºC, since the efficiency of thermoelectric modules decreases considerably at very low temperatures. The highest practical temperature limit is about 80ºC, which is imposed mainly by the manufacturing techniques used to assemble thermoelectric modules.

CoP

S 2 ×T c 2 =½ R

1

Coefficient of performance

Pl

∆T / ∆Tmax

The peak maximum is when ∆T = 0, that is

5

0 0.1

Normalised temperature

(23.40)

1

CoP

R

Pc / Pmax

∆T / ∆Tmax

Substituting Iopt in to equation (23.36) gives the maximum heat pumping rate, Pc,max S 2 ×T c2 Pc ,max = ½ − K ∆T (W)

1090



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Power Electronics

Chapter 23

Some of the more significant features of thermoelectric modules include: Compared with standard designs using refrigeration cycles with compressors and cooling mediums (such as CFC's), thermoelectric cooling possesses the following traits: • There is no environmental damage since no cooling medium such as CFCs or any gas is used. Environmentally friendly and safe. No coolant gas, corrosive gas or fluid leakage, easy maintenance. • Small compact size - dimensions (small form factor) and lightweight, giving high cooling density. • Wide choice of configuration – flexible form. • By simply changing the applied dc current polarity, heating is possible in addition to cooling with the same module (including temperature cycling). Easy switching from cooling to heating mode. Since cooling and heating are both possible, it is also possible to regulate temperatures close to room temperature. Precise temperature control to within ±0.1°C, with smooth and fine adjustment of cooling capacity and temperature. • DC operation, with high power efficiency. • Good responsiveness to heat. (Quickly heats or cools.) Quick cooling to below ambient economically. Wide operating temperature range, sub-ambient cooling, cooling to low temperatures, below ambient, multistage cascades to below -100°C, wide range of operating temperatures. • Solid-state device, therefore no moving parts; there is no vibration or noise. Acoustically silent and electrically ‘quiet’. • Since there are no fatiguing or breakable machine parts it is the most long-lasting, highly reliable method of cooling. Maintenance-free, >200,000hr. • With only a power cord, it is easy to handle. • Spot Cooling: It is possible to cool one specific component or area only, thereby often making it unnecessary to cool an entire package or enclosure. • Operation in any orientation or any spatial position, zero gravity and high G levels, resistance to high mechanical loads, shocks and vibration.

°C

1091

Problems related to Peltier cooling • High power usage and high power dissipation are the biggest problems related to Peltier cooling. Large power dissipation requires a large heatsink, powerful (and thus loud) fans, and a dc supply. • Limited to power dissipation of the order of 600W. • Low temperatures may cause moisture condensation, leading to short circuits between the elements. Moisture condensation depends on the temperature inside the system block, the temperature of the cooled device and air moisture. The warmer the air and the higher the moisture, the more probable condensation occurs. • Low efficiency, or low CoP compared with compressor-based cooling. • Failure modes are thermal cycle fatigue of solder to chip, copper corrosion, copper migration, and crystal inclined cleavage planed defects. 23.11.5

TE cooling design

TEC design involves the initial specification of three parameters, the hot and cold side temperatures, Thot and Tcold, (or Th and Tc) hence the temperature gradient or difference ∆T = Th - Tc, (∆T > 0) and the amount of heat, in Watts, to be absorbed at the cold surface of the TEC, Pcold. The cold surface temperature, Tc, is the desired temperature of the object to be cooled, directly in contact with the TEC. The hot surface temperature, Th, is defined by two major parameters: • The temperature of the ambient environment to which the heat is being rejected. • The efficiency of the heat exchanger that is between the hot surface of the TEC and the ambient. The third parameter required is the amount of heat, the thermal load, Pcold, to be removed or absorbed by the cold surface of the TEC. The thermal load includes the active I2R type losses of the device to be cooled, as well as parasitic loads such as conduction through any mechanical object in contact with both the cold surface and any warmer environment, like conduction through mounting bolts and plates (and the radiation from the plates). Figure 23.61 show the thermal resistance components and system model. Performance characteristic charts, as in figure 23.62, are usually provided. These allowing the terminal dc voltage and dc current requirements to be determined from the temperature difference ∆T and heat to be absorbed on the cold side, Pcold. The maximum ∆T is about 67°C for a single TEC, higher than this requires cascading (stacking) of TECs. The negative quadratic shape in the lower plot on figure 5.57, represents the optimal operating curve. Further TE technical details can be found in Chapter 5.10.

Heat transfer without TEC

T Temperature

1092


Heat transfer with TEC

TTIM1

Tj Rθj-TIM1

Tspreader

Tcase

Theat sink

Tambient Rθsink-ambient

RθTIM1-spreader Rθspreader-case Rθcase-sink

PD + Ptec

Power dissipated PD

TEC Power dissipated

Ptec

Tobject Pactive + Ppassive R1

R1 cold-sink thermal resistance Ploss

R2

R2 cold-sink spreading resistance

R3

R3 module substrate and interface thermal resistance

Pcold = Pactive + Ppassive + Ploss Tcold Ptec = Vte x Ite

R6

Σ

R6 bolts, gasket, internal air and radiation thermal resistance

Thot R3

R3 module substrate and interface thermal resistance

R4

R4 heat-sink spreading resistance

R5

R5 heat-sink thermal resistance

Phot = Pactive + Ppassive + Ploss + Pe

Th/s Pactive + Ppassive + Pe Tambient

+ Vte -

Rθ convection

Re p+n legs

Tambient

+ Ite

(α p - α p)(Th - Tc)

Rθ ceramic

(α p - α p) I Th

Th

½I2Re p+n legs

Rθ p leg Rθ n leg

½I2Re p+n legs

(α p - α p) I Tc Tc

Rθ ceramic

Rθ convection

Tambient

Figure 23.61. TEC cooling models: (a) thermal resistance model; (b) equivalent electrical circuit model; and (c) PSpice electrical model.

1093

Power Electronics

Chapter 23

Example 23.8: Thermoelectric cooler design An application has an estimated heat load of 22W, a forced convection type heat sink with a thermal resistance of 0.15°C/W, an ambient temperature of 25°C, and an object that needs to be cooled to 5°C. The cold side of the thermoelectric cooler is in direct contact with the object to be cooled. The specifications for the thermoelectric module in figure 23.62 are as follows (at Th = 25°C): Imax = 6.0A Qmax = 51.4W Vmax = 15.4V ∆Tmax = 67°C Solution To determine if the thermoelectric cooler is appropriate for this application, it must be shown that the parameters ∆T and Qc are within the appropriate boundaries of the performance curves. The parameter ∆T follows directly from Th and Tc. Since the cold side of the thermoelectric is in direct contact with the object being cooled, Tc is estimated to be 5°C. Assuming a 10°C rise above ambient for the forced convection type heat sink, Th is estimated to be 35°C. Without knowing the power into the thermoelectric cooler, an exact value of Th cannot be found initially. The temperature difference across the thermoelectric cooler is: ∆T = Th – Tc = 35°C - 5°C = 30°C Figure 23.62 shows performance curves for the TEC at a hot side temperature of 35°C. Referring to figure 23.62b, the intersection of Pc = 22W and ∆T = 30°C show that this thermoelectric can pump 22W of heat at a ∆T of 30°C with an input current of 3.6A.

70

60

50

40

30

20

10

0 18

V

18 16

16

6A

14

14 4.8A

Ve

12 10

Voltage

8

= 25°C + 8.7°C = 33.7°C

The calculated Th (33.7°C) is close enough to the original estimate of Th (35°C), to conclude that the thermoelectric will work in the given application. If an exact solution is required, the process of solving for Th mathematically can be repeated until the value of Th does not change. The TEC operating coefficient of performance CoP is P 22W CoP = cold = = 0.61 36W Ptec

♣ 23.11.6

Thermoelectric power generation

A thermoelectric generator, TEG, is an energy conversion system that converts thermal energy to electrical energy. The fundamental physics of this type of energy conversion is summarize as, the temperature difference ∆T between the hot Th and cold Tc sources leads to a difference in the Fermi energy ∆EF across the thermoelectric material yielding a potential difference, which drives a current. Bismuth Telluride-based thermoelectric modules are designed primarily for cooling or combined cooling and heating applications where electrical power creates a temperature difference across the module. By using the modules ‘in reverse’, however, whereby a temperature differential is applied across the faces of the module, it is possible to generate electrical power. Although power output and generation efficiency are low, useful power may be obtained where a source of heat is available. A thermoelectric module used for power generation has certain similarities to a conventional thermocouple. A single thermoelectric couple or generator with an applied temperature difference is shown in Figure 23.63. Phot

(a)

6

1.2A

4

T h = 25°C + 0.15°C/W × 58 W

10

2.4A

6

The input power to the thermoelectric, Pin, is the product of the current and the voltage. Using the 3.6A line in Figure 23.62a for the current, the input voltage corresponding to ∆T = 30°C is almost 10V. Th can now be calculated from: Ph = Pc + Ptec = 22 W + 3.6 A × 10 V = 22 W + 36 W = 58 W Therefore, using T h = T amb + Rθ × Ph where T amb = 25°C and Rθ = 0.15°C/W

12

3.6A

9.8V

8

4

Thot

2

2

∆T = Thot - Tcold

60

60

W

a 50

4.8A

40

3.6A

30

20

2.4A

20

10

1.2A

10

Pc

30

-

-

n

p

---

+++

60

50

40

Temperature difference

30

20 ∆T=Th-Tc

10

b

+

Tcold

0

0 70

+

Ite

(b)

22W

Power

50

6A

40

1094


0

Pcold Electrical load

-

RL

+

Figure 23.63. Single thermoelectric couple where Thot > Tcold.

K

Figure 23.62. TEC performance curves: (a) upper plot ∆T versus Voltage and (b) lower plot, ∆T versus Pc.

These values are based on the estimate Th = 35°C. Once the power into the TEC is determined, the equations to follow can be used to solve for Th and to determine whether the original estimate of Th was appropriate.

With no load (RL not connected), the open circuit voltage as measured between points ‘a’ and ‘b’ is: V o / c = s × ∆T where: Vo/c is the output voltage from the couple (generator), V s is the average Seebeck coefficient, V/K ∆T is the temperature difference across the couple where ∆T = Th - Tc., K When a load is connected to the thermoelectric couple, the output voltage Vo drops as a result of internal couple thermoelectric materials resistance. Vo = s × ∆T − I te × Rc (23.53)

1095

Power Electronics

Chapter 23

The current through the load is:

I te =

s × ∆T Rc + RL

where the open circuit output voltage Vo/c is: V o / c = N s × S ∆T

(23.54)

where: Ite is the couple output current, A Rc is the average internal resistance of the thermoelectric couple, Ω RL is the load resistance, Ω The output power, in terms of the input heat PT and efficiency η, is given by Ptec = I teVo = ηPT Maximum efficiency is reached when the load and internal resistances are equal because this is the maximum power achieved from load matching. The total heat input to the couple, Ph, is: Ph = s ×T h × I te - ½ × I te2 × Rc + κ × ∆T (23.55) where: Ph is the heat input, W κ is the thermal conductance of the couple, W/K Th is the hot side of the couple, K The efficiency of the couple η, is: V ×I η = o te (23.56)

1096


(23.66)

and the generator Thevenin equivalent resistance Rgen is:

R gen = P1

P2

Ns ×R Np

(23.67)

I

Pn

I

S1

R gen =

RL

Vo

S2

+

Ns ×R Np

RL

Vo = RL V R gen + RL o / c

Ph

A complete module consists of a number of couples, it is therefore necessary to rewrite the various equations for an actual module, as follows: Vo / c = S × ∆T = I te × (R + RL ) (23.57) where: Vo/c is the generators open circuit output voltage, V S is the module’s average Seebeck coefficient, V/K R is the module’s average resistance, Ω The module Seebeck coefficient, resistance, and thermal conductance properties are temperature dependent. The values of S, R, and K must be selected at the average module temperature Tave where: (23.58) T ave = ½ (T h + T c ) The power output, Po, from the module in watts is: Po = RL × I te2 (23.59) The voltage at maximum power is half the open circuit voltage Vo/c (Vo/c = Sx∆T = 2Vmax) and the 2 maximum power changes with temperature difference as a function of ∆T . V2 V2 S 2 × ∆T 2 (23.60) Pmax = max = o / c = 4R 4R R The maximum efficiency of a thermoelectric material depends on two terms. The first is the Carnot efficiency: no heat engine can exceed the Carnot efficiency. The second is a term that depends on the thermoelectric properties, Seebeck coefficient, electrical resistivity and thermal conductivity, which together form a material property called zT, which is a good approximation for the thermoelectric module Figure of Merit ZT. For small temperature difference (Tc ≈ Th) this efficiency is given by: ∆T 1 + ZT − 1 ∆T 1 + ZT − 1 ηmax = (23.61) × ≈ × T Th Th 1 + ZT + 1 1 + ZT + c

Th

where

S 2T s 2T ZT = = module figure of merit ≈ zT = = material figure of merit RK ρκ

(23.62)

and ∆T

Th

= Carnot efficiency

(23.63)

ZT (involving S, K, and R) refers to the TEC module while zT (involving s, κ, and ρ) refers to the raw material property. That is, S, K, and R involve TEC dimensions and the number of couples. Most thermoelectric generators contain a number of individual modules which may be electrically connected in either a series, parallel, or series/parallel arrangement. A typical generator configuration is illustrated in figure 23.64. This generator has a total number of modules NT with Ns modules connected in series and Np modules connected in parallel. The total number of modules in the system is: NT = N S × N P (23.64) The current I in amperes passing through the load resistance RL is: Vo / c N × S × ∆T (23.65) I = s = Ns + RL R gen × R + RL

Np

V o / c = N s × S ∆T Sn

Figure 23.64. Typical thermoelectric generator with a series-parallel arrangement of modules.

The loaded output voltage Vo from the generator in volts is:

Vo = Vo / c

RL RL = N s × S ∆T Ns R gen + RL × R + RL Np

(23.68)

The output power Po from the generator in watts is:   N × S × ∆T 2 Po = I RL =  s  Ns  N × R + RL  p The heat input Ph to each module in watts is:

Ph = S ×T h ×

 I I -½× N Np  p

2

   RL   

(23.69)

  × R + K × ∆T 

(23.70)

2

The total heat input Ph to the generator in watts is:   I I -½× PH = NT ×  S ×T h × N Np   p 

2

  × R + K × ∆T 

   

Ns = N s × S ×T h × I - ½ × I × R + N T × K × ∆T Np

(23.71)

2

The efficiency η of the generator is:

η=

Po × 100% PH

Maximum efficiency occurs when the generator internal resistance Rgen equals the load resistance RL. That is, from equation (23.67), maximum output power occurs when

RL = R gen =

Ns ×R Np

(23.72)

Assuming temperature independent material parameters, the maximum efficiency is approximately ∆T ηmax = (23.73) 4 2 ×T ave + ½∆T −

Z

Power Electronics

Chapter 23

Example 23.9: Thermoelectric generator design

V o = N s × S ∆T

Solution The system parameters are: Th = +130°C ≡ 403.2K Vo = 12V I = 1.5A Tc = +30°C ≡ 303.2K therefore Tave = ½×(Th+Tc) = ½×(403.2+303.2) = 353.2K RL = Vo / Ite = 12V / 1.5A = 8.0 Ω Po = Vo x Ite = 12 x 1.5 = 18 W ∆T = Th - Tc = 403.2 - 303.2 = 100K It is usually desirable to select a relatively ‘high power’ thermoelectric module for generator applications in order to minimize the total system cost. Thus a 127 couple, 6A module is used in the design. The required power Po for the load is 12 x 1.5 = 18 W. The minimum number of modules needed to meet this load requirement is calculated from the maximum output power from one module, equation (23.60): 2 2 ( S × ∆T ) = ( 0.05544 × 100K ) = 2.48W Pmax = 4 ×R 4 × 3.0994Ω The minimum number of modules needed is: P 18 NT min = o = =7.3, use 8 Pmax 2.48 Because maximum generator efficiency occurs when Rgen = RL = 8 Ω, it is desirable for most applications to select the series/parallel module configuration that will best approximate this resistance matching. One possible exception to the equalizing Rgen with RL is when a relatively low current (in the mA range) and moderate voltage is required. In this case, the connection of all modules electrically in series may give better results. However, the maximum output voltage from the generator is obtained from a seriesconnected group of modules only when the resistance of the load is significantly higher than the internal resistance of the generator. The string series-connected configuration of eight modules gives an internal resistance of: N 8 R gen = s × R = × 3.0994Ω = 24.8Ω 1 Np This 24.8Ω generator resistance is considerably higher than the 8.0Ω load resistance, thereby indicating that a series module connection probably is not the best arrangement. For the all series case where Ns = 8 and Np = 1, the open circuit voltage 8×0.05544×100K = 44.35V and the loaded output voltage, from equation (23.68), is:

V o = N s × S ∆T ×

RL

Ns × R + RL Np

= 8 × 0.05544 × 100K ×

8Ω

RL Ns × R + RL Np

8Ω = 12.49V 4 × 3.0994Ω + 8Ω 2 Vo is close to the desired 12V value. If ‘fine tuning’ of Vo is required, this can be accomplished either by some form of electronic voltage regulation or by externally altering the applied temperature differential ∆T. If the output voltage is significantly out of range despite trying all possible series/parallel combinations, an alternate thermoelectric module having a different current rating and/or number of couples should be used. With Vo established, the output power Po is: V 2 12.492 = 19.51W Po = o = 8Ω RL and the load current is 12.49V/8Ω = 1.562A. = 4 × 0.05544 × 100K ×

The total heat input PH to the generator, at 1.56A, is: 2   I  I PH = NT ×  S ×T h × te - ½ ×  te  × R + K × ∆T  N  Np    p   2   1.562A  1.562  -½× = 8 ×  0.05544 × 403.2K × × 3.2Ω + 0.6632 × 100K  = 662.4W    2  2   

The generator efficiency η is:

η=

Po 19.51W × 100% = × 100% = 2.95% 662.4W PH

The heat transferred to the cold-side heat sink Po is: Pc = PH - Po = 662.4 - 19.5 = 642.9 W The maximum allowable thermal resistance Ps of the cold-side heat sink is: T 30°C − 10°C Ps = rise = = 0.031°C/W 642.9W Pc

♣ NT

A 12V, 1.5A thermoelectric power generator is needed to power telemetry electronics at a remotely located oil pipeline where the hot, continuously flowing oil produces a 130°C pipe casing temperature. Flowing water (having a temperature of 10°C) also is available at the remote site, and an efficient watercooled heat sink can maintain the TE generator cold-side at a temperature of +30°C. For a 127-couple, 6 A module, the following values are applicable at Tave = 353.2K: S = 0.05544 V/K R = 3.0994 Ω K = 0.6632 W/K

1098


500

Total number of modules

1097

100

75°C

100°C

125°C

150°C ← Th

50 10 5 1

= 10.82V

8 × 3.0994Ω + 8Ω 1 With a group of eight modules, a logical alternative generator connection configuration is two parallel strings of four series modules, i.e., Ns = 4 and Np = 2. Generator resistance for this configuration is thus: N 4 R gen = s × R = × 3.0994Ω = 6.2Ω 2 Np

While Rgen = 6.2Ω does not exactly match the 8.0Ω load resistance, this is the closest resistance match that can be obtained with the selected module type. The voltage for this arrangement is:

0

30

60

cold side temperature

90 Tc

120 °C

Figure 23.65. The total number of 127-couple, 6A Modules required for a 12V, 1A thermoelectric power generator

For any thermoelectric generator design, it is desirable to maximize the applied temperature differential in order to minimize the total number of modules in the system. This situation can be seen in figure 23.65. Module requirements for a typical 12V, 1A power generator are plotted for several values of Th based on the use of 127-couple 6A TE modules. From this graph, a large number of modules are needed when the cold side temperature Tc is high and the temperature differential is small. Performance of the cold-side heat sink is import and its thermal resistance must be low. In many cases, cold-side heat sink design will prove to be a challenging engineering problem.

1099

23.11.7

Power Electronics

Chapter 23

23.12

Thermoelectric performance

The best room temperature thermoelectric materials are alloys of Bi2Te3 with Sb2Te3 (giving a p-type semiconductor material) and Bi2Te3 with Bi2Se3 (giving an n-type semiconductor material). ZT is of the order of 1 at room temperature. This ZT value gives a Coefficient of Performance, CoP, of about 1, as shown in figure 23.66a, which compared to household refrigerators and air conditioners, with CoP’s from 2 to 4), makes thermoelectric cooling generally not competitive. The same holds for power generation, as shown by the low thermoelectric efficiencies in figure 23.66b. One of the problems with traditional Peltier elements is their limited capability of cooling heat fluxes over 5 to 10W/cm2. Because the cooling density of a Peltier cooler is inversely proportional to its length, scaling to smaller size is desirable. The material structure resulting from conventional crystal growth techniques for producing bismuth telluride thermoelectric materials impose significant limitations on thermoelectric element dimensions. Poor manufacturing yields prevent thermoelectric elements from being made very short. New fine-grain micro-alloyed bismuth telluride materials that do not suffer element geometry limitations, offer better performance. Nanocoolers use a monolithic process with thicknesses of about 1 to 2 micrometres, have a tunable performance of 10 to 1000W/cm2 with a single stage ∆T of 50 to 70K. Thin-film thermoelectrics offer cooling in excess of 160W/cm2. ZT ½1247


CoP

6

10

Stirling refrigerators

4

Primary cells

Zinc Carbon Battery (1.5V, -10°C to 55°C) The zinc/carbon cell uses a zinc anode and a manganese dioxide cathode. Carbon is added to the cathode to increase conductivity and retain moisture. The manganese dioxide takes part in the reaction, not the carbon. Negative (anode) reaction: Zn → Zn2+ + 2e– Positive (cathode) reaction: 2NH4+ + 2MnO2 + 2e– → Mn2O3 + H2O + 2NH3 The cathode reaction is complicated by the fact that the ammonium ion produces 2 gaseous products: 2NH4+ + 2e– → 2NH3 + H2 These two products are absorbed by 2 mechanisms in order to prevent pressure build up.: ZnCl + 2NH3 → Zn(NH3)2Cl2 2MnO2 + H2 → Mn2O3 + H2O Total reaction (discharge): Zn + 2MnO2 → ZnO + Mn2O3 Lithium Manganese Dioxide Battery (3V, -40°C to +125°C) The coin-type lithium manganese dioxide battery uses manganese dioxide (MnO2) as its positive active material, lithium (Li) as its negative active material, and an organic electrolyte. Positive reaction: MnO2 + Li+ + e- → MnOOLi Negative (anode) reaction: Li → Li++eTotal reaction (discharge): MnO2 + Li→ MnOOLi Lithium Thionyl Chloride Battery (3.6V, -55°C to 85°C) The lithium thionyl chloride battery uses liquid thionyl chloride (SOCl2) as its positive active material, and lithium (Li) as its negative active material. The reactions of the battery are shown below. Positive reaction: 2SOCℓ2 + 4Li+ + 4e- → 4LiCℓ + S + SO2 Negative (anode) reaction: Li → Li+ + eTotal reaction (discharge): 2SOCℓ2 + 4Li → 4LiCℓ + S + SO2

Carnot cycle

5

Appendix:

1100


household refrigerators air conditioning

3

Thermal refrigerators

2

Stirling cryrocoolers

Silver Oxide Battery (1.55V) The silver oxide battery uses stable monovalent silver oxide (Ag2O) as its positive (cathode) active material and fine zinc alloy (Zn) as its negative active material. Potassium hydroxide (KOH) – for high drain or sodium hydroxide (NaOH) – for low drain, are used as an electrolyte. Positive reaction Ag2O + H2O + 2e- → 2Ag + 2OHNegative (anode) reaction Zn + 2OH- → ZnO + H2O + 2eTotal reaction (discharge): Ag2O + Zn → 2Ag + ZnO

1 0 1

1.2

1.4

1.6

1.8

2.0

Thot / Tcold

4

(V)

Temperature ratio

0.6 Carnot cycle

0.5 Power generation efficiency

7

0.4

3

Thermal power plant

0.3

2 Alkali metals Thermal cells Electric cells Thermionic generators

0.1

Stirling generators ½

Diesel plant

Automotive engines

1

1.2

1.4

Temperature ratio

1.6

ML

2 SR

TC

LR

1

10-3

10-2

10-1

100

101

102

103

Capacity (Ah)

Thermoelectric power generators

0

Li-ion

ER

CR

ML

4

0.2

Li-ion

10

Cell voltage

η

ZT

1.8

2.0

Thot / Tcold

Figure 23.66. Comparison of thermoelectric technology with other energy conversion methods for: (a) cooling and (b) power generation.

Primary CR- Lithium Manganese Dioxide Battery E- Lithium Thionyl Chloride Battery SR- Silver Oxide Battery

Secondary Li-ion - Lithium Ion Rechargeable Battery ML- Lithium Manganese Dioxide Rechargeable Battery TC- Titanium Carbon Lithium Rechargeable Battery

1101

Power Electronics

Alkaline Manganese Battery (1.50V) Electrolytically produced powdered manganese dioxide (MnO2) is used for the active cathode material, and specially processed fine zinc-alloy powder is used for the active anode material. Concentrated aqueous potassium hydroxide (with added zinc oxide to retard anode corrosion) is used as an electrolyte. Positive reaction 2MnO2 + 2H2O + 2e- → 2MnOOH + 2OHNegative (anode) reaction Zn + 2OH- → ZnO + H2O + 2eTotal reaction (discharge): 2MnO2 + Zn+ H2O → 2MnOOH + ZnO Zinc Air Battery (1.4V) The cathode is catalyzed carbon that reduces oxygen from the air, with the anode a gelled mixture of amalgamated zinc powder and a highly conductive solution of KOH in water electrolyte. The electrode reactions for a zinc air battery are as follows Positive (cathode) reaction O2 + 2H2O + 4e- → 4OHAnode reaction 2Zn + 4OH- → 2ZnO + 2H2O + 4eOverall reaction: 2Zn + O2 → 2ZnO

Chapter 23

23.13


Appendix:

1102

Empirical Battery Model

The electrochemical battery can be modelled as a series resistor and a charge-dependent voltage source whose voltage as a function of charge has the following reciprocal relationship:  α (1 − x )  V = Vo 1 −  1 β (1 − x )  −  where: x is the ratio of the ampere-hours left to the number of ampere-hours, AH, for which the battery is rated. Vo is the voltage when the battery is fully charged, as defined by the nominal voltage, Vnominal parameter. The constants α and β are calculated to satisfy the following battery conditions: • the battery voltage is zero when the charge is zero, that is, when x = 0. • the battery voltage is V1 (the voltage V1 < Vnominal when charge is AH1 parameter value) when the charge is the charge AH1 when no-load volts are V1 parameter value, that is, when x = AH1/AH. The equation defines a reciprocal relationship between internal voltage and remaining charge. It is an approximation to a real battery, but it does replicate the increasing rate of voltage drop at low charge levels. It also ensures that the battery voltage becomes zero when the charge level is zero. Vnominal is the nominal voltage; the open circuit voltage at the output terminal when the battery is fully charged, typically 12 V. Ampere-Hour rating, AH, is the maximum battery charge in ampere-hours, typically 50 hr*A. Initial charge: the battery charge at the start, typically 50 hr*A. Rint is the internal resistance, typically less than 1Ω. Battery charge capacity models the charge capacity of the battery according to the battery voltage which decreases as charge decreases. Voltage V1 < Vnominal when charge is AH1. The battery no-load output voltage, typically 11.5 V, when the charge level is AH1, typically 25 hr*A hr*A. Self-discharge resistance of the battery, R2: the resistance across the battery output terminals in the model that represents battery self-discharge, typically 2kΩ. The state of charge SoC measures the fraction of charge remaining in the battery, and is defined as t  Q ∫ idt   SoC = 100  1 −  = 100  1 − o 0 ≤ SoC ≤ 1 C  C      where C is the battery capacity in Ah and Q is the charge already delivered in Ah. A fully charged battery has a SoC of 100%, while a fully discharged battery has a SoC of 0%. Depth of discharge DoD measures the fraction of discharge reached, and is DoD=1-SoC.

Rint

Iin

Vint

+ Vbattery

Figure 23.67. Battery model.

Reading list http://www.mpoweruk.com/ http://science.howstuffworks.com/solar-cell3.htm http://americanhistory.si.edu/fuelcells/index.htm http://www1.eere.energy.gov http://www.fctec.com/fctec_basics.asp

Chapter 24

Capacitors

1104

Aluminium

24 Capacitors

1nF

Selection of the correct type of capacitor is important in all power electronics applications. Just satisfying capacitances and voltage requirements is usually insufficient. In previous chapters, capacitors have been used to perform the following circuit functions: • turn-off snubbering (8.3.1) • dv/dt snubbering (8.1) • RFI filtering (10.2.4, 14.7) • transient voltage sharing of series connected devices (10.1.1) • voltage multipliers (11.1.3iv) • dc rail splitting for multilevel converters (15.3) • cascaded multilevel inverters for VAr compensation (15.3) • power L-C filters (15.6) • switched-mode power supply output filtering and dc blocking (17) • ac power factor correction and compensation (19.2) as well as • dc rail decoupling • motors for single phase supplies which is just to name a few uses of capacitors in electrical power applications. In each application, the capacitor is subjected to stresses, such as high temperature, dv/dt or high ripple current, which must be taken into account in the design and selection process. To make the correct capacitor selection it is necessary to consider various capacitor types, their construction, electrical features, and uses. Two broad capacitor types are found extensively in power electronic circuits, namely: • liquid and solid (wet and dry) electrolyte, oxide dielectric capacitors, for example an aluminium electrolytic capacitor • plastic film dielectric capacitors, for example a polyester capacitor. The first capacitor group has a metal oxide dielectric and offers large capacitance for a small volume. The second capacitor group, which uses a thin plastic film as a dielectric, offers high ac electrical stress properties. Ceramic and mica dielectric capacitors are also considered. Ceramic capacitors are used extensively in high power, high frequency switched mode power supplies where they offer small size, low cost, and good performance. The voltage and capacitance ranges for the four main types of dielectric capacitors are shown in figure 24.1. CERAMIC

Hi dielectric K

Single layer Multi-layer

Semiconductor

fixed

CAPACITORS

Polyester FILM

Polypropylene

Mixed Metallised Foil

1µF

Figure 24.1. Voltage/capacitance boundaries for the principal types of capacitors.

24.1

General capacitor properties

The following general principles, properties, and features are common to all capacitor dielectric types. 24.1.1 Capacitance The primary function of a capacitor is to store electrical energy in the form of a charge. The amount of electrical charge, Q, is given by

∫

Q = CV = i dt

[or i = C dv / dt ]

(C)

(24.1)

while the stored energy and force between the plates are given by W = ½QV = ½CV 2 [or W = ½ DE × Aw] (J) F = ½CV 2 / w = ½ε oε r AV 2 / w2 (N) (24.2) The value of capacitance, C, is directly proportional to surface area, A, and inversely proportional to the thickness of the dielectric layer (plate separation distance), w; that is A C = ε rεo (F) (24.3) w The dielectric constants εr (or K) for materials in common usage, are summarised in Table 24.1. Table 24.1: Dielectric constants for common dielectric materials Dielectric material

Relative dielectric constant

εr

εo = 4π×10-7 Vacuum Air (1 atmosphere) Polystyrene Polypropylene Polycarbonate (now obsolete) Polyethylene-terephthalate Impregnated paper Mica Al203 Glass Ta203 Ceramic

1 1.00059 2.5 2.5 2.8 3 2-6 6.5 - 8.7 7 4 - 9.5 10 - 25 20 -12,000

Dielectrics in capacitors have the property of changing the spacing effectively between two plates. This is manifested in two ways.

Polystyrene

ELECTROLYTIC

Aluminium Tantalum

MICA

BWW

First, placing a dielectric between two electric charges reduces the force (Coulomb’s Law) acting between them, just as if they were moved apart. Wet Dry

In a vacuum, the force between the two charges is:

Fo =

q 1q 2

4πε o r 2

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Chapter 24

Capacitors

With a dielectric of relative permittivity εr, the force between the two charges reduces to:

Fr =

q 1q 2 q 1q 2 = 4πεo ε r r 2 4πε εr r o

(

)

2

=

Z = Rs −

Fo εr

j

1106

(24.8)

(Ω)

ω CR

and

½

Rs 1 real power = = (24.9) X c Q reactive power where δ is the loss angle and tanδ is termed the dissipation factor, DF, which is the reciprocal of the circuit quality factor, Q. The angle δ is that necessary to make the capacitor current lead the terminal voltage by 90° in figure 24.2c and d, as for an ideal capacitor. tan δ = ω CR Rs = ω CR × ESR =

The dielectric increases the effective distance from r to εr xr. Secondly, the dielectric constant of a material affects how electromagnetic fields (light, radio waves, millimetre-waves, etc.) move through the dielectric material. A high dielectric constant increases the effective spacing. This means that light travels slower. It also ‘compresses’ the waves to behave as if the field has a shorter wavelength.

Q

In a vacuum, the electric field created by a charge q is:

q

Eo =

I

4πε o r 2 With a dielectric of relative permittivity εr, the electric field reduces to:

Er =

q

4πεo ε r r 2

=

q

4πε o

(

εr r

)

2

=

I

(a)

The effective capacitance of parallel, Cp, and series, Cs, connected capacitors are

=

1

C1

+

1

C2

+

1

C3

+ ...

Xc = 1

2π f C R

= 1

P

V

P

(c)

ωCR

i (b)

(24.4)

δ

In parallel, the capacitor with the lowest voltage rating specifies the parallel combination voltage rating. 24.1.2 Volumetric efficiency

The volumetric efficiency of a capacitor is a measure of the effectiveness of a given physical construction and dielectric material. Volumetric efficiency ηv, is defined by C ×V (24.5) ηv = R R ( C/m3 ) volume

Dimensionally, longer is better since there is less percentage dielectric wastage of the unused dielectric ends. Cylindrical is better than oval, except an oval cross-section may allow better stacking with parallel connected capacitors or may result in lower lead inductance for pcb mounted capacitors. 24.1.3 Equivalent circuit

The impedance of a capacitor can be modelled by one of the capacitor equivalent circuits shown in figure 24.2. In series with the ideal capacitor, CR, termed rated capacitance, is an equivalent series resistor Rs (ESR) and equivalent series inductor Ls (ESL). Rs is determined by lead and junction resistances, while Ls is the inductance of the electrodes due to the construction and the supply lines. The value of Ls is usually given for a specific package and capacitor type, and is generally neglected at lower frequencies, below the self-resonant frequency, which is given by 1 (rad/s) ωr = (24.6) Ls CR

(24.7)

I

Q

Rd

The electrical impedance Z of a capacitor, neglecting • Ri the leakage (insulation) resistance which is usually large, • Rd is the dielectric loss due to dielectric absorption and molecular polarisation (significant at high frequencies), and • Cd is the inherent dielectric absorption, only significant in electrolytic capacitors is 1 Z = Rs + jX = ESR + j 2π f × ESL − j (Ω) 2π f × CR Since the ESL is neglected, at lower frequencies, when 2πf (that is ωL) is small

V

(d)

I

C p = C 1 + C 2 + C 3 + ... 1

δ

Eo εr

The dielectric increases the effective distance from r to εr½xr. In the case of a capacitor it is the electric field effect created by the dielectric that is relevant, εr = Eo /Er. Since C=Q/V, the dielectric effectively decreases E (hence V), thus increases capacitance C.

Cs

i

Cd

Figure 24.2. Capacitor: (a) equivalent circuit for a film capacitor and; (b) electrolytic capacitor; and terminal V-I phasor diagram; (c) below resonance; and (d) above resonance.

If the insulating or dielectric dc leakage resistance, Ri (= ρi ℓ/A), is included, then 1 + ω CR Rs (24.10) tan δ = ω CR Ri and at low frequency (ω > ωo) tan δ u ≈ ω CR Rs (24.12) Both Rs and Xc are dependent on temperature and frequency as shown in figure 24.3. Figure 24.3a shows that the rated capacitance illustrated has a positive temperature coefficient, the value of which also depends on capacitance and rated voltage. Also shown is the negative temperature dependence of equivalent series resistance ESR. Figure 24.3b shows that CR and ESR both decrease with frequency. Since CR and ESR are temperature and frequency dependent, and are related to tan δ and Z, then tan δ and Z are frequency and temperature dependent as illustrated in figures 24.3c and 24.3d. Figure 24.3c shows the typical characteristics of the impedance of an oxide dielectric capacitor versus frequency, at different temperatures. At low frequencies the negative slope of Z is due to the dominance of the capacitive reactance, Z ≈ Xc = 1/ωCR, whereas the horizontal region, termed the resonance region, is where Z is represented by the ohmic resistance Rs, that is Z ≈ Rs. At higher frequencies the inductive reactance begins to dominate, whence Z ≈ ωLs and tan δ=Rs /ωsL. Figure 24.3d shows how the dissipation factor, tanδ, increases approximately proportionally with frequency to a high value at resonance, as would be expected from equation (24.9). At lower frequencies tanδ may be considered as having a linear frequency dependence, according to tanδ = tan δo + k f. ESR and tan δ dictate internal power dissipation hence self-heating, namely, for terminal voltage V

P = I 2 × ESR = 2π fC × tan δ ×V 2 = ( 2π fC ) × ESR ×V 2 2

(24.13)

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Capacitors

1108

In the case of voltage, current, and other stresses including temperature, which differ from those under which λo is specified, conversion or acceleration factors are used to calculate the new failure rate. Typical conversion factors are given in Table 24.2 for ambient temperature Ta, and operating voltage Vop, in relation to rated voltage VR. Alternatively conversion graphs are also used or the Arrhenius’ law n

Ea  1   T

 Vop  − K  e  VR 

λ = λo 

 − 1  To 

(24.16)

gradual deterioration usefull life

Figure 24.4. The bathtub curve showing variation of failure rate with operating hours.

Table 24.2: Stress conversion factors for an aluminium electrolytic capacitor

Vop

Conversion factor

Temperature Ta (°C)

100

1

≤40

1

75

0.4

55

2

VR

Figure 24.3. Variation of capacitor equivalent circuit parameters with frequency and temperature for a high voltage (47 µF, 350 V) metal oxide liquid dielectric:(a) Rs and CR as a function of temperature; (b) Rs and CR as a function of frequency; (c) impedance Z as a function of frequency and temperature; and (d) tan δ as a function of frequency and temperature.

%

Conversion factor

50

0.2

70

5

25

0.06

Tjmax

10

10

0.04 (a)

(b)

24.1.4 Lifetime and failure rate

The service life of a capacitor occurs when its parameters fall outside the specification limit, termed degradation. Such parameters are usually the capacitance, dissipation factor, impedance, and leakage current. The service life is specified under specific operating conditions such as voltage, ambient temperature, and current, and will increase • • • •

the lower the ambient temperature, Ta the lower the ripple current or voltage, Ir the lower the operating voltage in proportion to the rated voltage, Vop / VR the higher the ac load frequency, f.

Other factors may be relevant to specific dielectrics. Lifetime is the period until a given failure rate is reached. The failure rate, λ, is the ratio of the number of failures to the service life expected. It is usually indicated in failures per 109 component hours (fit – failure in time) and is an indicator of equipment reliability. If, in a large number N of identical components, percentage ∆N fail in time ∆t, then the failure rated λ, averaged over ∆t is expressed as 1 ∆N (/h) λ= × (24.14) N ∆t If the sample N is large, then the failure rate in time can be represented by a continuous ‘bathtub’shaped curve as shown in figure 24.4, such that 1 dN (/h) λ= (24.15) N dt This figure shows the three distinct failure periods, and the usual service life is specified according to the failure λo, which is constant.

Example 24.1: Failure rate

A component has a failure rate λo = 2 x 109/h, commonly termed 2 fit (failures in time) using 109/h as reference. With reference to Table 24.2, what is the failure rate if i. ii. iii.

the ambient temperature, Ta, is increased to 55°C the operating voltage is halved i. and ii. occur simultaneously?

Solution

Assume λo applies to conditions at Ta ≤ 40°C and VR. i.

If the ambient temperature is increased from 40°C to 55°C, then using a conversion factor of 2 from table 24.2b λ55 = 2 × λo = 4 fit that is, the failure rate has doubled, from 2 fit to 4 fit.

ii.

Similarly, by halving the operating voltage, a conversion factor of 0.2 is employed from table 24.2a. The new failure rate is λ ½V = 0.2 × λo = 0.4 fit That is, the failure rate has decreased by a factor of 5, from 2 fit to 0.4 fit.

Power Electronics

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iii.

Chapter 24

If simultaneously both the ambient temperature is increased to 55°C and the operating voltage is halved, then (assuming independence and superposition of factors) λ 55,½V = 2 × 0.2 × λo

= 0.8 fit The conversion factors are cumulative and the failure rate decreases from 2 fit to 0.8 failures in time. ♣

If the number of units surviving decreases exponential with time, then the probability of failure F after a service time t is given by F ( t ) = 1 − e−λt (24.17) Equipment failure rate can be calculated by summing the failure rates of the individual components, that is λtotal = λ1 + λ2 ..... + λn (24.18) If the failure rate is to be constant, then the instantaneous failure rate of the number of faults per unit time divided by the number of non-failure components must yield a constant dF ( t ) 1 =λ (24.19) 1 − F ( t ) dt For n components in a system, the probability of system survival is 1 − F ( t ) = (1 − F1 ( t ) ) × (1 − F2 ( t ) ) × .... (1 − Fn ( t ) ) = e − λ1t × e − λ2t × ..... e − λn t = nλ if, since the units are identical, λ1 = λ2 = … = λn. The mean time between failure (mtbf) is given by ∞ 1 mtbf = = 1 − F ( t ) dt =

∞

1

∫0 λtotal ∫ 0 λ The service operating life τ for a specified probability of failure is therefore given by e − λt dt =

1

1 τ= n λ 1− F

(24.20)

Capacitors

1110

v. For 1000 units, each with a failure rate of 10λ, the probability of one unit surviving 1 year is −9

1 - F (1 yr) = e-10 x 200 x 10 x 8760 = 98.2 per cent The probable number of first year failures with 1000 units is −9

F (1 yr) = 1 - e-200 x 10

x 8760

= 0.002 pu = 2 units

♣ The reliability concepts considered are applicable to all electronic components (passive and active) and have been used to illustrate capacitor reliability. 24.1.5 Self-healing

One failure mode of a capacitor is voltage breakdown in a defective area of the dielectric. As a result of the applied voltage, the defective area (due to pores and film impurities) experiences an abnormally high electric field which may cause failure by arcing within a few tens of nanoseconds. Oxide capacitors using an electrolyte and plastic film dielectric capacitors exhibit self-healing properties, which in the case of plastic film dielectrics allow the capacitor to remain functional after voltage breakdown. In the case of a defect in the dielectric oxide layer of an electrolytic capacitor, the maximum field strength is reached first in the defective region. This is effectively the process which occurs during the formation of the oxide layer, which results in the growth of new oxide, thereby repairing the defect. The reforming process is relatively slow compared with the healing time for non-polarised capacitors. By contrast, the high electric field at the defect in a metallised plastic film capacitor causes a continuous high pressure plasma arc which pushes the dielectric layers apart and evaporates the metallisation in the breakdown region. Temperatures can reach 6000K and insulated areas are formed around the original failure area, which after the arc self-extinguishes, isolate the faulty dielectric within 10µs..

(24.21) 24.1.6 Temperature range and capacitance dependence

(24.22)

Example 24.2: Capacitor reliability

A capacitor has a failure rate λ of 200 x 10-9 failure/hour, 200 fit. Calculate i. the probability of the component being serviceable after one year ii. the service life if the probability of failure is chosen to be 1% or 0.1% iii. the mean time between failure iv. the mean time between failure for 10 parallel connected capacitors v. the probability of survival for 1 year and of failure for units, if 1000 units each have 10 parallel connected capacitors.

The operating temperature upper and lower limits are either dictated by expected service life or the allowable variation limits on the nominal capacitance. Most capacitors can be used outside their nominal temperature limits, but at reduced lifetime, hence with reduced reliability. The extremes -55°C to 125°C are common, but obviously electrolytic capacitors must be restricted to a smaller range if the electrolyte is not either to freeze or to boil. Capacitor reversible temperature dependence can be expressed in terms of a temperature dependant capacitance co-efficient αc, by

C (T ) = C 20°C (1 + αc (T − 20°C ) )

(24.23)

where the temperature co-efficient of capacitance α, with respect to reference Cref at 20°C, is C − CT 1 αc = T 2 10-6 /K C ref (T 2 − T 1 )

Solution i. The probability of the capacitor being serviceable after 8760 h (1 yr) is given by 1 − F (1 yr ) = e − λt 9

= e−200×10 ×8760 = 0.998 (99.8%)

ii. Component lifetime is given by

τ=

1

λ

n

1 1− F

109 1 τ (1% ) = n = 50,000 h = 5.7 years 200 1 − 0.01 9 10 1 τ ( 0.1% ) = n = 5,000 h = 0.57 years 200 1 − 0.001

iii. The mean time between failure, given by equation (24.21) is 109 mtbf = 1/ λ = = 5 x 106 h = 570 years 200 iv. The failure rate for 10 capacitors is 10λ = 2000 fit and the mtbf is 1 109 = = 57 years 10λ 2000

24.1.7 Dielectric absorption

After a capacitor is discharged from a voltage Vi, a small voltage Vr reappears, due to a polarisation process in the insulating material. [This phenomena could be considered to be equivalent to remanence flux in magnetic materials]. The voltage tends to be independent of capacitance and dielelctric thickness and is defined at 20°C. The dielectric absorption factor δA is defined by

δA =

Vr × 100% Vi

(24.24)

Typical factor percentage values for various dielectric types are shown in the following table. Dielectric type δA

%

polypropylene KP 0.05 - 0.10

polyethyleneterephthalate (polyester) KT 0.21 - 0.25

mixed dielectric 0.12 - 0.15

ceramic X7R 0.60 - 1.00

Z5U 2.00 - 2.50

Power Electronics

1111

24.2

Liquid (organic) and solid, metal oxide dielectric capacitors

The oxides of metals such as aluminium and tantalum are capable of blocking current flow in one direction and conducting in the other. Operation of metal oxide dielectric capacitors is based on the socalled valve effect of these two metals.

Chapter 24

Capacitors

Long strips of the cross-sections are wound into cylindrical bodies and encased as shown in figure 24.6. Operation at high voltages causes oxide growth and the production of hydrogen. Any gas pressure relief valve provided should be orientated upwards, just as the anode terminal should be above the cathode if the capacitor is orientated horizontally. Ca

24.2.1 Construction

The capacitor dielectric layer consists of aluminium oxide Al203 or tantalum oxide Tn203 which is formed by an electrochemical oxidising process of aluminium foil (0.02 to 0.1mm thick) or sintered tantalum powder. These starting metals form the capacitor anode. The oxide layer withstands high electric field strengths, typically 8 x 108 V/m for Al203 which represents 1.45 nm per volt, and are excellent insulators (hence result in a high capacitor loss factor). This field strength is initially maintained constant (with constant current) during the oxidising process (this electrochemical process is aided by weak phosphoric acid in the case of tantalum capacitors and chloride solution for electrolytic capacitors), then constant voltage, so that the oxide thickness is dependent and practically proportional to the forming voltage VF. To avoid changing the oxide thickness during normal use, the component operated rated voltage VR should always be lower than the forming voltage, as shown in figure 24.5. The difference VF - VR is the over-oxidisation voltage and substantially determines the capacitor operational reliability. For generalpurpose electrolytic capacitors, the value of VR / VF is about 0.8, while solid capacitors are rated at 0.25.

1112

Ck

anode

1 cathode

C total

=

1

Ca

+

1

Ck

Al2O3 natural oxide

dielectric

highly etched aluminium foil

Etched aluminium foil

Electrochemical oxide layer forming

Paper spacer soaked in electrolyte

electrolyte solution

Figure 24.5. Current (leakage) dependence on voltage of Al electrolytic capacitors.

The oxide dielectric constant εr is approximately 8.5 for Al203 and 25 for Ta203, while in comparison paper-based dielectrics have a value of approximately 5. An oxide thickness of w = 0.7µm is sufficient for high voltage capacitors (≥ 160 V) as compared with minimum practical paper dielectric thickness of about 6µm. The metal oxide type capacitors potentially offer high capacitance per unit volume. To further improve the capacitance per unit volume, before oxidation, the aluminium anode surface area is enlarged 10-300 times (foil gain - depending on the voltage – 100x for low voltage and 20x for high voltage capacitors) by electrochemical deep etching processes. In the case of tantalum capacitors, the sintered tantalum sponge like lattice structure results in the same increase of area effect. In the case of tantalum capacitors, the oxide not only grows on the surface of the tantalum, about one third grows into the porous lattice. This tends to limit the maximum voltage rating of tantalum capacitors.

graphite

The capacitor is formed by the placement of the cathode on to the oxide layer. In the case of the electrolytic capacitor, a highly conductive organic acid electrolytic (based on dimethylacetamide) which is impregnated into porous paper, forms the capacitor cathode. The electrolyte largely determines the ESR hence it must have a low resistivity over a wide temperature range. It must also have a breakdown voltage well above the capacitor rated voltage at maximum operating temperature. For long life, electrolytes with a water content must be avoided. Teflon spacers are sometimes used rather than paper. The electrical contact to the cathode is a layer of etched aluminium, which has a thin oxide layer. In the case of solid capacitors, (with lower voltages), a high conductive cathode is formed by a solid semiconductor metal oxide, such as manganese dioxide. This is achieved by the pyrolysis (continued dipping and baking at 200°C) of manganese nitrate in to manganese dioxide. In solid oxide capacitors, the manganese dioxide is dipped into graphite which is coated with silver epoxy for soldering.

24.2.2 Voltage ratings

The four wet/dry oxide possibilities are shown in figure 24.6. A porous paper or glass fibre is used as a space keeping agent in order to avoid short circuits and direct mechanical contact.

Basic electrolyte (electrolytic) capacitors are suitable only for unipolar voltages, where the anode is positive with respect to the cathode. In the case of the aluminium electrolytic capacitor, the cathode

Figure 24.6. Construction of metal oxide capacitors.

1113

Power Electronics

connection metal does have a thin air-oxide layer which corresponds to an anodically generated layer with a blocking voltage capability of about 2 V. Above this voltage level, an electrolytic generated dielectric oxide film would be formed on the cathode foil. The effect is to decrease the capacitance and cause high internal heating and oxidation of the cathode foil thus gas formation, gas as shown in the following formula, which can lead to failure. 2A + 3H 2O - 6e - → Al 2O 3 + 6H + 6H + + 6e - → 3H 2 gas

This pressure build up may cause the safety vent to open or possibly destroy the capacitor. Deterioration is slow with a reverse voltage of a few volts.

Chapter 24

Capacitors

1114

When connecting electrolytic capacitors in series, parallel sharing resistors are necessary to compensate for leakage current variation between the capacitors. The design of the sharing network is as for the steady-state voltage sharing of semiconductors presented in 10.1.1, where the sharing resistance is nV R −V s where ∆I = 1.5 × 10 −3C RV R (24.25) R = ( n − 1 ) ∆I Additionally, the resistors provide a discharge path for the stored energy at power-off. When parallel connecting capacitors, highest reliability is gained if identically rated capacitors (voltage and capacitance) are used.

Solid, oxide capacitors are in principle capable of supporting bipolar voltage since the cathode is a semiconductor, manganese oxide. In practice, impurities such as moisture restrict the reverse voltage limits to 5-15 per cent of VF. The usable reverse voltage decreases with increased ambient temperature. The rated voltage VR may be exceeded under specified intermittent conditions, resulting in a maximum or peak voltage limit VP, as shown in figure 24.5, where for VR ≤ 315V VP = 1.15 VR for VR > 315V VP = 1.1 VR Both VR and VP, are derated with increasing temperature. Tantalum capacitors are linearly voltage derated above 85°C, to 66% at 125°C, which is the maximum operating voltage limit. 24.2.3 Leakage current

When a dc voltage is applied to capacitors, a low current, Iℓ k called the leakage current, flows through every capacitor, as implied by the presence of Ri in the equivalent circuit model in figure 24.2. With oxide dielectric capacitors, this current is high at first and decreases with working time to a final value, as shown in figure 24.7.

0.9VR

Figure 24.8. Typical leakage current of oxide capacitors versus: (a) voltage and (b) temperature.

24.2.4 Ripple current

The maximum superimposed alternating current, or ripple current Ir is the maximum rms value of the alternating current with which a capacitor is loaded, which produces a temperature difference of 10 K between the core and ambient. Ripple current results in power being dissipated in the ESR, according to 2

Figure 24.7. Leakage current variation with working time for a liquid aluminium oxide capacitor.

A low final leakage current is the criterion of a well designed dielectric, thus leakage current can be considered as a measure for the quality of the capacitor. The current is a result of the oxidising activity within the capacitor. The leakage current depends on both dc voltage and ambient temperature, as shown in figure 24.8. The purity of the anode metal, hence oxide dielectric determines the leakage current. Liquid, oxide capacitors have the lower leakage currents at rated voltage since when a voltage is applied; anions in the electrolyte maintain the dielectric electrochemical forming process. The Mn02 in solid oxide capacitors has lower reforming capabilities. From figure 24.8 it will be seen that leakage increases with both temperature and voltage. The increase in leakage current with temperature is lower in liquid capacitors than in the solid because, once again, the electrolyte can provide anions for the dielectric reforming process. For an aluminium electrolyte capacitor at 85°C, an expected lifetime of 2000 hours is achieved by selecting VR / VF = 0.8. However, VF is inversely proportional to absolute temperature so for the same leakage current at 125°C, the ratio of VR / VF must be decreased to VR 273 + 85 = 0.7 = 0.8 × 273 + 125 VF For higher temperature operation, a higher forming voltage is required. But since VF × CR (energy volume) is constant for any dielectric/electrode combination, CR is decreased.

Pd = I r Rs (W) (24.26) which results in an internal temperature rise until equilibrium with ambient occurs, see equation (24.13). The maximum power dissipation P d is dependent on the thermal dissipation properties of the capacitor, and from equation (5.4) where

Pd = h A ∆T (W) (24.27) h = heat transfer coefficient, W/m2K A = capacitor outer surface area, m2 ∆T = Ts - Ta = temperature difference between capacitor surface, Ts, and ambient, Ta ,K

Thus the maximum ripple current is given by Pd = Rs

Ir =

hA∆T Rs

(A)

(24.28)

The ESR, Rs, is both temperature and frequency dependent, hence rated ripple current Iro, is specified at a given temperature and frequency, and at rated voltage VR. Due to the square root in equation (24.28), conversion to other operating conditions is performed with the frequency multiplier √r and temperature multiplier √k, such that I r = k r I ro = k r I ro (A) (24.29) .

.

Typical multiplier characteristics for aluminium oxide capacitors are shown in figure 24.9. It will be seen from figure 24.9a that electrolytic capacitors are rated at 85°C, while as seen in figure 24.9b solid types are characterised at 125°C. For each type, a reference frequency of 100 Hz is used.

Power Electronics

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Chapter 24

Capacitors

1116

I r = 2.25 × 1.37 × 3.7A = 11.4A ♣

Figure 24.9. Frequency and temperature ripple current conversion multipliers for: (a) liquid and (b) solid A1203 capacitors.

Alternatively, the temperature derating multiplier is expressed in terms of the ambient, core and rated temperatures by T − T amb (24.30) k = core T core − T R .

No simple expression exist for the frequency derating factor, r, although it may be used to infer ESR frequency derating

ESRfreq =

ESR100Hz

(24.31)

r

Electrolytic capacitors usually have a thermal time constant of minutes, which can be exploited to allow intermittent overloads. Example 24.3: Capacitor ripple current rating

A 1000 µF, 385 V liquid, aluminium oxide capacitor has an rms ripple current rating Iro of 3.7 A at 100 Hz and 85°C. Use figure 24.9a to calculate the allowable ripple current at i. 60°C and 1 kHz ii. lowest stress conditions. Solution i.

Using equation (24.29) Ir =

.

k r I ro = k r I ro .

(A)

where from figure 24.9a at 60°C, √k = 1.85 at 1 kHz, √r = 1.33 whence I r = 1.33 × 1.85 × 3.7A = 9.1 A ii. This capacitor experiences lowest stressing at temperatures below 40°C, where √k = 2.25 and at frequencies in excess of 2 kHz when √r = 1.37. Under these conditions the ripple current rating is

Figure 24.10. Rms voltage limits of solid tantalum capacitors for different physical dimensions, temperature, voltage rating, and frequency.

Non-sinusoidal ripple currents have to be analysed such that at a given temperature, the individual frequency components satisfy 2 I2 Ir ≥ ∑ n (24.32) rn n where I r is for the appropriate rated ambient and reference frequency as indicated in figure 24.9. Liquid tantalum capacitors have a ripple current rating which is determined by the physical dimensions, independent of temperature over a wide range, and independent of frequency above 50 Hz. Ripple current ratings may not be specifically given for some capacitor types, for example solid tantalum capacitors. In this case an indirect approach is used. In satisfying ac voltage limitations as illustrated in figure 24.10, and any series resistance requirement, allowable ripple currents can be specified for a given temperature. 24.2.5 Service lifetime and reliability 24.2.5i - Liquid, oxide capacitors

As considered in 24.1.3, the reliability and lifetime of a capacitor can be significantly improved by decreasing the thermal and electrical stresses it experiences. Stress reduction is of extreme importance in the case of liquid aluminium oxide capacitors since it is probably the least reliable and most inappropriately used common electronic component. The reliability and service lifetime of an aluminium oxide electrolytic capacitor are dominated by its ripple current, operating temperature, and operating voltage. Figure 24.11 in conjunction with figure 24.9a, can be used to determine service life.

Power Electronics

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Chapter 24

Capacitors

1118

In comparison with liquid electrolytic capacitors, solid types, and, in particular, tantalum type capacitors, have a number of desirable characteristics:

• • •

higher capacitance per unit / volume due to the higher permittivity of Ta203 and the intrinsically high effective area per unit volume due to the sintered construction changes in parameters (CR, tan δ) are less because the specific resistance of Mn02 and hence temperature coefficient, is lower than that of liquid electrolytes electrolyte is stable, does not evaporate or corrode.

The failure rate of all capacitors can be improved by decreasing the stress factors such as temperature and operating voltage. But reliability of solid tantalum capacitors can be increased by placing a series resistor (of low inductance) in the circuit. The improvement is illustrated by the following design example, which compares the lifetime of both liquid and solid tantalum capacitors based on the conversion curves in figure 24.12.

Figure 24.11. Service life for an aluminium oxide liquid capacitor. Temperature dependence of lifetime variation with: (a) ripple current and (b) operating voltage.

Example 24.4: A1203 capacitor service life

A 1000 µF, 385 V dc aluminium oxide liquid capacitor with a ripple current rating Iro of 2.9 A at 100 Hz and 85°C ambient is used at 5 A, 4 kHz, in a 65°C ambient and on a 240 V dc rail. What is the expected service lifetime of the capacitor? Solution

From figure 24.9a at 4 kHz, √r =1.35, whence Io 1 5A 1 × = × = 1.28 I ro r 2.9A 1.35 From figure 24.11a, the coordinates 1.28 and 65°C correspond to a 24,000 hour lifetime with less than 1 per cent failures. Since a 385 V dc rated capacitor is used on a 240 V dc rail, that is, a ratio 0.64, an increase in service lifetime of 17½ per cent can be expected, according to figure 24.11b. That is, a service lifetime of 28,000 hours or greater than 3½ years is expected with a relative failure rate of less than 1 per cent. Generally, between 40 and 85°C aluminium electrolytic capacitor lifetime doubles for every 10°C decrease in ambient temperature. A service lifetime of 7 years could be obtained by decreasing the ambient temperature from 65°C to 55°C. ♣ .

With aluminium electrolytic capacitors, degradation failures are mostly due to factors such as • aggressiveness of the acidic electrolyte • diffusion of the electrolyte • material impurities.

(b)

Figure 24.12. Stress conversion factors for: (a) solid tantalum capacitors and (b) liquid tantalum capacitors.

Example 24.5: Lifetime of tantalum capacitors 24.2.5ii - Solid, oxide capacitors

The failure rate of solid aluminium and tantalum capacitors is determined by the occurrence of open and short circuits (the dominant failure mode for solid tantalum capacitors) as a result of dielectric oxide layer breakdown or field crystallisation. In general, for a given oxide operating at rated conditions, liquid capacitors have a shorter lifetime than the corresponding solid type. Solid aluminium capacitors are more reliable than solid tantalum types and failure is usually the degradation of leakage current rather than a short circuit.

A 22 µF tantalum capacitor is required to operate under the following conditions: ambient temperature Ta, 70°C operating voltage Vop, 15 V circuit resistance i. 1 Ω ii. 100 Ω Calculate the expected lifetime for solid and liquid tantalum capacitors.

Power Electronics

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Chapter 24

Liquid tantalum

Solid tantalum

R

Ω

1 and 100

1

100

Ri

Ω

3

n/a

0.1

Σ Ri

(1)

12

1

Χ

2.2

0.10

0.10

at Vop/VR=0.6 and 70°C

λo λ = λo×Σ fit τ (% failures) within λ∆t

-8

/h

4×10

/h

2.2×4×10 -8 8.8×10

1×10 -8

12×0.1×10 -8 1.2×10

88 45,000 (0.4%)

h

-8

1×10 -8

Dielectric constant, 25°C, 1kHz

-8

1 100,000 (0.1%)

C drift with time C temperature coefficient C humidity coefficient (50% …95%) Time constant, 25°C

PP

PS

PEN

2.8

2.2

2.5

3.0

250

180

350

150

-250

-150

105

70

%

3

10-6/K

+600

+150

°C

125

125

βc

10-6/% r.h.

500 … 700

-3

tanδ

10

5

τ=RiCR

103 s

25

% weight g/cm

3

3

2

40 … 100 1

0.6

+200

700 … 900 0.2

100

4 25

0.2

0.3

0.05

0.1

1.39

1.21

0.91

1.05

1.2

26.3.1 Construction

♣ Plastic film dielectric capacitors

Plastic (polymer) dielectric type capacitors are non-polarised capacitors and in general offer high dv/dt and pulse rating capability compared with oxide type capacitors. The most common dielectric plastics used (organic, hydrocarbons, as shown in figure 24.13) are: polye t hylene-terephthalate (polyester or PEPT or PET) T poly c arbonate (now obsolete) C poly p ropylene (PP) P poly s tyrene S polyphenylene sulph i de I polyethylene n aphthalate (PEN) N The letter shown after each type is the symbol generally used to designate the film type. The symbol K is used to designate plastic, which is Kunststoff in German. O

..

O

PC

3.2

αc

density

Based on figure 24.12, the capacitor lifetime calculation is summarised the previous table.

C

PEPT

∆C/C

Water dielectric absorption

Ri' = 100 Ω /15 V = 6.6 Ω/V which is > 3 Ω/V

CH3

V/µm

Max working temperature

Dissipation factor @ 1kHz

Capacitor used CR = 22 µF VR = 25 V For each capacitor type (solid or liquid) the voltage stress factor is Vop /VR = 0.60 For the solid tantalum, the circuit resistance factor is given by i. Ri' = 1 Ω /15 V = 0.07 Ω/V which is < 0.1 Ω/V

24.3

εr

Dielectric strength

-8

Solution

ii.

1120

Table 24.3: Characteristics of plastic film dielectrics – typical values dielectric

1×0.1×10 -8 0.1×10

12 83,000 (0.1%)

Capacitors

O

CH3 H

H

C

C

H

CH3

(a) (b)

Figure 24.13. Basic hydrocarbon structure of (a) polyethylene-terephthalate and (b) polypropylene.

Two basic types of plastic film dielectric capacitors are common. The first type involves metallisation deposited on to the plastic and the metal forms the electrodes. Typically such a capacitor would be termed MKP, that is metallised - M, plastic - K, polypropylene - P. A foil capacitor, the second type, results when interleaved and displaced metal foil is used for the electrode. Typically such a foil capacitor would be termed KS, that is plastic - K, polystyrene – S or MFT and MFP (F - foil). The plastic type is designated by the fifth letter of the plastic name, that is the letter after poly, with two exceptions.

24.3.1i - Metallised plastic film dielectric capacitors

The dielectric of these capacitors consists of plastic film on to which metal layers of approximately 0.020.1 µm are vacuum deposited. A margin of non-coated film is left as shown in figure 24.14a. The metallised films are either wound in a rolled cylinder or flattened to form a stacked block construction. In this construction, the metallised films are displaced so that one layer extends out at one end of the roll and the next layer extends out the other end as shown in figure 24.14a. This displaced layer construction is termed extended metallisation and facilitates electrical contact with the electrodes. A hot lead-free metal spray technique, called schooping, is used for making electrical contact to the extended edges of the metallised plastic winding. This large disk area contact method ensures good ohmic contact, hence low loss and low impedance capacitor characteristics result. The most common metallised plastic film capacitors are those employing polyester, MKT and polypropylene, MKP. All have self healing properties, hence use thinner dielectrics. Polyester has a higher dielectric constant than polypropylene, and because of its stronger physical characteristics, is available in thinner gauges than polypropylene. High capacitance values result in the smallest possible volume. But polypropylene has a higher dielectric strength and lower dielectric losses, hence is favoured at higher ac voltages, currents, and frequencies. 24.3.1ii - Foil and plastic film capacitors

Foil capacitors normally use a plastic film dielectric which is a flexible bi-axially aligned electro-insulator, such as polyester. Aluminium foils and/or tin foils (5 to 9µm) are used as the electrodes. The thin strips are wound to form the capacitor as shown in figure 24.14b. An extended foil technique similar to the extended metallisation method is used to enable contact to be made to the extended metal foil electrodes. Film foil capacitors do not have self-healing properties, hence use thicker dielectrics. 24.3.1iii - Mixed dielectric capacitors

To further improve the electrical stress capabilities of a capacitor, combinations of different dielectrics are commonly used. Such capacitors use combinations of metallised plastics, metallised paper, discrete foils and dielectrics, and oil impregnation. Figure 24.14c shows the layers of a mixed dielectric paper and polypropylene capacitor. A thin gauge of polypropylene dielectric is combined with textured metallised paper electrodes. The coarse porous nature of the paper allows for improved fluid impregnation of the dielectric material, which counters the occurrence of gas air bubbles in the dielectric. This construction has the electrical advantages of high dielectric strength, low losses, and a self-healing mechanism, all at high voltages. Two plastic dielectrics can be combined, as shown in figure 24.14d, to form a mixed layer capacitor, with two series connected elements. It involves a double metallised polyethyleneterephthalate film and polypropylene films. These dielectric combinations give low inductance, high dielectric strength, and low losses with high ac voltage capability. Other extended layer winding designs, involving two internally series connected elements as in figure 24.14d, but single sided, are extended metallised film and extended foil with a metallised film designs.

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Capacitors

1122

plastic film dielectric

extended single metallised film

metal sprayed contact ‘schooping’

extended metal foil

metal foil terminal weld or schooped

(a)

(b)

Doubled-sided metallised polyester carrier film

MFP

polypropylene dielectric film Single-sided metallised polypropylene film

MKN

metal sprayed contact ‘schooping’

(c)

MFT

(d)

Figure 24.14. Plastic capacitor constructions: (a) extended single metallization film; (b) extended foil; (c) mixed dielectric, extended double-sided metallised carrier film; and (d) mixed dielectric, extended double-sided metallised carrier film with internal series connection.

24.3.2 Insulation

The dc resistivity insulation characteristics of a capacitor are indicated either as a resistance value Ri, as shown in Figure 24.2 or for capacitance greater than 0.33µF, as a time constant, τ = Ri CR. The resistance comprises the insulation resistance of the dielectric (layer to layer) and the insulation resistance between layer and case. This later resistance is determined by the quality of the case insulating material and by the length of the surface leakage paths. Both the time constant and resistance are dependent on voltage, temperature, and significantly himidity, as is shown in figure 24.15. These characteristics illustrate that extremely high insulation resistance values can be obtained. 24.3.3 Electrical characteristics 24.3.3i - Temperature dependence

Figure 24.15. Plastic dielectric insulation resistance temperature dependence characteristics: (a) resistance Ri and (b) time constant τ.

24.3.3ii - Humidity dependence

The capacitance will undergo a reversible change in value due to ambient humidity variation. The humidity coefficient βc, is define for a 1% change in humidity, at a constant temperature, by 2 × (C F 2 − C F 1 ) βc = (C F 2 + C F 1 ) × (F 2 − F1 ) where CT1 is the capacitance at relative humidity F1 CT2 is the capacitance at relative humidity F2 Wide capacitance variations occur at relative humidity levels above 85%. Prolong contact of a film capacitor with high humidity or direct liquid water will produce irreversible effects due to reaction of the film metallisation. Typical plastic dielectric humidity coefficient variations are shown in figure 24.16c.

The capacitance of plastic film capacitors changes with temperature, humidity, and frequency, as shown in figure 24.16. The dependence is strongly dependent on the dielectric film although some foil types are virtually independent of frequency. Table 24.4 summarises capacitance temperature dependence for a range of dielectrics. The temperature coefficient αc is measured in parts per million per degree Kelvin, ppm/K. CT 2 − CT 1 αc = (24.33) C 20°C × (T 2 − T 1 )

24.3.3iii - Time dependence

where CT1 and CT2 are the measured capacitances at temperatures T1 and T2. (See equation (24.23)) Any small irreversible charge in capacitance at rated temperature, after a temperature variation between the allowable temperature extremes, is termed temperature cyclic capacitance drift. The temperature dependence of dissipation factor is shown in figure 24.23a.

Figure 24.17a shows the typical frequency dependent characteristics of the dissipation factor for a range of plastic dielectric capacitor types. It is important to note that polyester types have 50-100 times the losses of polypropylene capacitors. A low loss characteristic is important in power pulse applications where capacitor package heat dissipation may be a limiting factor, as indicated in figure 24.18. The dissipation factor, hence losses, are dependant on the ESR, as shown in equation (24.9). The ESR represents a complex set of loss mechanisms, many of which are strongly dependent on the measurement conditions. The ESR measured at the resonant frequency is not the worst-case value and is higher at lower frequencies.

Capacitance charges irreversibly with time, where the drift coefficient iz=|∆C/C| is measure over a period of at least a year and at a temperature above ambient, typically a maximum of 40°C. As shown in Table 24.3, typical drift values are about 2% to 3%. 24.3.3iv - Dissipation factor and impedance

Dielectric conduction losses are caused by the actual transport of charge across the volume of the dielectric or across internal dielectric interfaces. These losses are largest at low frequencies and higher temperatures. Because conduction in a dielectric material can be strongly nonlinear, non-Ohmic, conduction losses are often strongly dependent on applied capacitor voltage. Interfacial polarization losses are related to dielectric conduction. Many high voltage capacitors contain two or three different materials within their dielectric arrangements, film and oil or paper, film and oil. Each material has different conduction properties and permittivity. As a result, the application of a DC voltage over a period results in a build-up of conducted charge at the internal interfaces between materials. This polarization of the dielectric is a low frequency phenomenon, hence the energy stored in this way is not available for discharge at high frequency. Again, since the conduction is nonlinear, interfacial polarization is nonlinearly voltage dependent. This loss mechanism is important in pulse discharge applications, where the capacitor is charged over a relatively long period of time and then discharged rapidly. Partial discharge losses can occur within gas-filled or defective solid capacitors or even in liquid-filled capacitors at high voltages. It is also common to have external corona on capacitor terminals. Partial discharges are most energetic at high rates of change of voltage (high dv/dt), such as during a capacitor pulse discharge. Also, reversal of the voltage such as in a highly oscillatory ringing capacitor discharge will cause more numerous, energetic, partial discharges. Electromechanical losses result from the electrostriction, and sometimes piezoelectricity, acting within the capacitor dielectric itself and the flexing of internal wiring due to the Lorentz forces. Ohmic resistance losses occur within the metallic electrodes, the internal wiring, and the capacitor terminals. In electrolytic capacitors, ohmic resistance in the electrolyte itself represents the largest loss mechanism. The resistance losses in the metal are constant as a function of temperature and frequency, until the skin depth in the electrodes becomes important, usually above several megahertz. Losses in the internal wiring and the terminal is important in high current applications. When high voltage capacitors are internally configured as a series string of lower voltage capacitor windings or units, the ohmic resistance within a given container size increases at the square of the voltage (or as the number of series elements). Sparking can occur between conductors or different points on the same conductor during the discharge of pulse capacitors. For example, capacitors manufactured with an inserted tab connection to the electrode foil which is only a pressure contact exhibit points of localized melting after pulse discharge operation resulting from sparks between the adjacent metallic surfaces. This phenomenon is related to a high current rate of change, di/dt, during discharge, and is therefore frequency and voltage related. Eddy current losses are important in pulse forming networks where a high magnetic field can couple into any ferromagnetic materials within the capacitor. These losses depend strongly on frequency. Usually the internal inductance in a capacitor is small and does not generate significant eddy currents.

%

f = 1kHz

∆CR/C

MFT

Capacitance change

MKN

%

MFP

∆CR/C

Ferroelectric hysteresis losses are observed in certain high dielectric constant materials, most notably ceramics. These losses are a strong function of applied voltage. This loss mechanism arises when the internal polarization field has the same order of magnitude as the applied field. Under these conditions the dielectric response saturates. Capacitors made with such materials exhibit permanent polarization, variable capacitance as a function of voltage, and sensitivity to reversals of voltage.

1124

MFT

Capacitance change

Dielectric losses are usually the most important losses in a film capacitor. These losses are associated with the polarization and relaxation of the dielectric material in response to the applied capacitor voltage. The magnitude of the dielectric losses in a capacitor are therefore generally both frequency and temperature dependent, when the largest losses occur at low temperatures or high frequencies, which hinder dipole orientation. Dielectric losses essentially are not voltage-dependent. The dielectric losses of a given material can be described by its Dissipation Factor, DF. If the dielectric loss were the only loss mechanism operating in a capacitor, then the DF of the capacitor would be independent of its size, geometry and internal configuration. Capacitors of any size made with the same material would have the same DF under identical conditions. The ESR could then be computed using equation (24.9). However, the capacitor DF and ESR depend on the electrodes and their configuration.

Capacitors

MKN

MFT

3

MKN

%

Capacitor losses vary as a function of voltage, temperature, and other aspects of the applied waveform. This is because there are a variety of energy loss mechanisms which act within a capacitor. Some of these reside within the dielectric while others involve the conductors carrying the current. Some of the mechanisms and operating parameters which effect the magnitude of the losses, follow.

Chapter 24

2 ∆CR/C

Power Electronics

Capacitance change

1123

MKT MFT

1 MKP MFP

0 -1 -2 -3 0

20

40 Relative Humidity

60

80 %RH

100

Figure 24.16. Plastic film dielectric capacitance variation with: (a) ambient temperature; (b) frequency; and (c) relative humidity.

Generally, tanδ rises with increased frequency and increased capacitance. Tanδ is dominated by dielectric losses and the contact resistance of the leads. The extended foil/metallisation and schooping contact methods provide not only a low and constant ohmic contact, but because of the large contact area, result in a low self-inductance. The resonant frequency of such capacitors, because of their self-

Power Electronics

1125

Chapter 24

inductance and their capacitance, is high as shown by the minimum impedance in figure 24.17b. Minimum impedance decreases with increased capacitance and each capacitor in the range, here 1.5 nF to 4.7 µF, has its own Y-shaped impedance curve. The self-resonant frequency decreases with increased capacitance and can be used to determine the ESL, by ωo = √LCR. In figure 24.17b, the full impedance curves for maximum and minimum capacitance only have been shown. Table 24.4: Capacitor temperature coefficient for various dielectric materials Temperature coefficient αc (ppm/K or 10-6/K)

Dielectric type

metallised

Polypropylene Polyester Polyethylene naphthalate Polycarbonate Polystyrene Paper Mica Ceramic Aluminium Tantalum (solid and liquid)

MFT

film/foil

other

-170 400 180 150

100 + 1000 to -1000 1500

1126

24.3.3v - Voltage derating with temperature

The ac and dc voltages which may be applied continuously to a capacitor vary with ambient temperature and also frequency in the case of ac voltage rating. Typical characteristics showing temperature and frequency dependence are shown in figures 24.18 and 24.20 for plastic dielectric capacitor types. It will be seen that the ac voltage rating is significantly less than the dc voltage rating, while both voltage ratings are derated above 85°C and at higher frequencies. In all situations, the sum of the dc voltage and peak value of superimposed ac voltage must not exceed the rated dc voltage. An alternative approach for calculating the maximum ac voltage, allowable Vac, for a capacitor is based on the power dissipation limits, P, of the package. If Ri and ESL are neglected in the capacitor equivalent circuit shown in figure 24.2, then VR2 (24.34) P= = I 2 Rs (W) Rs and Rs2 VR2 = Vac2 (24.35) 1 2 Rs + 2 2 ω CR Since from equation (24.12) for plastic dielectric capacitors tan δ = ω CR Rs then equation (24.34) can be written as P = ωCR × tan δ × Vac2 = ( Rs CR ) ω 2CRVac2 (W) (24.36) s

-120 400 (non-linear) 160 -50 to -150 -125 300

300

Capacitors

s

(non-linear)

+200 to +1000

or alternatively 2 P = tan δ ω CRVac2 (= I rms ESR) (W) (24.37) The value of tan δ for equation (24.37) is available from figure 24.17a or, alternatively, the value of RsCR for equation (24.36) is available from figure 24.19. The equivalent series resistance is dominated by leakage and dielectric losses (f-1) at low frequency. At medium frequencies, conductor losses dominate, while at high frequencies losses are dominated by the skin effect (√f), as shown in figure 24.19b. The maximum permissible power dissipation, P which depends on the package dimensions and ambient temperature, is given in figure 24.18d. Thus when the power dissipation, for a given ac voltage, has been calculated, figure 24.18d can be used to specify the minimum size (dimensions) capacitor capable of dissipating that power. The example 24.6 illustrates the design approach outlined.

MKN

24.3.3vi – Voltage and current derating with frequency

The ac voltage/current dependence on frequency for film capacitors, has three distinct regions, as shown in figure 24.20. Region A Below a certain frequency, f1, the voltage threshold for corona discharge in capacitor air pockets is a limiting factor.

f res =

1 2π C R × ESL

Region B In the mid-frequency region, the package power dissipation limit restricts the internal loss limit. The internal losses are tanδ dependant (equation (24.37)) while the package limit is surface area, A and heat transfer coefficient dependant, h, equation 5.4. That is, the internal generated losses are Pint = tan δ ω C RVac2 while the heat dissipation from the capacitor surface A with a heat coefficient h, is defined by Pd = hA ∆T Since the internal losses must be less than that that can be dissipated, for a given internal temperature self-heating, ∆T: ωC R × hA ∆T hA ∆T Vac ≤ or I ac ≤ tan δ ωC R tan δ

The voltage and current are approximately related to frequency by

V ac ∝ f

Figure 24.17. Frequency characteristics for plastic dielectric capacitors: (a) maximum dissipation factor, tan δ and (b) typical impedance characteristics, Z, for metallised plastic dielectric capacitors.

−¾

or I ac ∝ f

¼

Region C At higher frequencies, above f2, with smaller capacitances and short contact lengths, the ac voltage is limited by the maximum current capabilities I2 of schooped plating connections.

V rms ≤

Ic

2π f × C R

or I rms ≤ I c

Power Electronics

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Chapter 24

Capacitors

1128

1.0VR

0.8%/K

1.25%/K

0.8VR

PEN

PP

0.7VR 0.5VR

(a)

PET

-55

-40

85 100 110 Temperature T

(b) equivalent series resistance ESR Ω

Maximum continuous voltage

(a)

125 °C

10

10

0

-1

f 10

-2

10

-3

f -½

ESR

10

150

-1

3

4

10 10 frequency

5

10 f

6

7

10 Hz

V

Figure 24.19. ESR characteristics: (a) maximum product of series resistance, Rs, and rated capacitance, CR, and (b) ESR as a function of frequency.

Vrms = constant

1

rms voltage limited by corona discharge

alternating voltage

(c)

Vrms

Vac

V ∼ ×f rms f

¼

(a)

a

b

f1 frequency

1

f

f2 f

Hz

limit by thermal power dissipation tanδ

A

current

Vrms ∼

c

voltage

(b)

Irms = constant

(d)

alternating current

Irms

Iac

I rms ∼ f

¼

rms current limited by scoop contact

I rms ∼ f

(b) a f1 frequency

b

c f2 f

Hz

(c)

Figure 24.18. Plastic dielectric capacitor, temperature derating characteristics: (a) general dc voltage derating; (b) dc voltage derating with ambient temperature; (c) ac voltage derating with temperature; and (d) power derating with temperature as a function of capacitor dimensions.

Figure 24.20. Capacitor rating limits: (a) maximum ac voltage; (b) ac current; and (c) ac voltage derating with frequency of different metallised plastic capacitors.

10

8

Power Electronics

1129

Chapter 24

Capacitors

1130

Example 24.6: Power dissipation limits - ac voltage

24.3.4 Non-sinusoidal repetitive voltages

A 0.1 µF plastic capacitor is used in a 100 V ac, 10 kHz and 50°C ambient application. Select suitable metallised polypropylene and polyester capacitors for this application.

Capacitors used for repetitive transient suppression, and for turn-off snubbers on GTO thyristors and diodes, experience high-magnitude short-duration voltage and current pulses which are not sinusoidal. High dv/dt capacitors based on metallised polypropylene are used, which are limited by their internal power losses, hence temperature rise and package power dissipation limit. A restrictive graphical design approach for capacitor selection with sinusoidal, sawtooth, and trapezoidal pulse trains is shown in figure 24.21. The design approach is illustrated by example 24.7.

Solution i.

Metallised polyester capacitor (MKT) From equation (24.36) P = ( Rs CR ) ω 2 CRVac2

(W)

From figure 24.19a, RsCR = 2 × 10-7 at 10 kHz. Thus P = (2 × 10-7 ) × (2π × 104 ) 2 × (0.1× 10-6 ) × (100) 2 = 780 mW From figure 24.18d, at 50°C a MKT capacitor of dimensions 11×20×31 (mm) can dissipate 930 mW. The applicable capacitor must have an ac voltage rating in excess of 100 V ac. From figure 24.20c, it can be seen that a 0.1 µF, 400 V dc MKT capacitor is necessary, given that the dimension constraints are met. ii.

Metallised polypropylene capacitor (MKP) From equation (24.37) P = tan δ ωCRVac2 (W) From figure 24.17a, tan δ = 4.0 × 10-4 at 10 kHz, for a 600 V dc type. Thus P = (4.0 × 10-4 ) × (2π × 104 ) × (0.1× 10-6 ) × 1002 = 25.6 mW From figure 24.18d, at 50°C, the smallest volume MKP capacitor, of dimensions 6.5×15×26 mm, can dissipate 300 mW. From figure 24.20c it can be seen that a 0.1 µF, 630 V dc (250 V ac) MKP capacitor is necessary. From figure 24.20c it can be seen that a 250 V dc 0.1 µF polypropylene foil capacitor (KP) is capable of 160 V ac at 10 kHz. Figure 24.17a shows the dissipation factor of KP type capacitors to be under half that of the metallised equivalent. That is, the expected losses are only P = (1.4 × 10-4 ) × (2π × 104 ) × (0.1× 10-6 ) × 1002 = 9 mW

♣ 24.3.3vii - Pulse dVR /dt rating

Related to the ac voltage rating and power handling capabilities of a capacitor is the rated pulse slope dVR /dt, which from i = CR dv / dt is specified by VR V = R (24.38) CR dV /dtmax I where R is the minimum series resistance including the ESR. The rating test is an accelerated test, carried out for 10,000 pulses at a 1Hz repetition rate. The capacitor is then dv/dt rated at 10% of that at which the pulse test was performed. R=

Generally for a given CR, dv/dt capability increases with rated voltage VR, and decreases as the distance between the metallised electrode contacts increases. If the capacitor operating voltage Vop is decreased below VR, at which voltage, dv/dt capability is specified, dv/dt capability increases according to d Vop d VR VR = × (V/s) (24.39) dt dt Vop The dv/dt capability depends on both the dielectric type and layer construction. Generally polystyrene (KS) and polyester (KT) foil type capacitors are not applicable to high dv/dt applications. Metallised polycarbonate capacitors (diminishing availability) offer slightly better dv/dt properties than those of metallised polyester. Metallised paper capacitors can withstand high levels of dv/dt, 30-50 times higher than those for metallised polyester. Capacitors using polypropylene, or even better a mixed dielectric involving polypropylene, offer extremely high dv/dt capability. With the construction shown in figure 24.14d, a 1 µF metallised polypropylene capacitor with VR of 2000 V dc and 1000 V ac, a 2500 V/µs capability is attainable. Practically the dv/dt limit may be restricted by the external connections. Such ratings are obtainable with polypropylene because of its extremely low losses, tan δ, as indicated in figure 24.17a. Under such high dv/dt stresses, it is important to ensure that the power dissipated (whence rms current) does not exceed the package limit.

Figure 24.21. Metallised polyester capacitor selection graph for sinusoidal and non-sinusoidal voltages.

When capacitor voltages are more abstract, the concept of pulse characteristic can be applied for frequencies lower than 10kHz and low duty cycles, which is based on the internally generated heat. 2

 dV  2  × Ri dt = ½ C × Ri × k o  dt  Thus ko, related the heat energy and pulse slope, is defined as

W =

∫

τ

o

I 2Ri dt =

∫

τ

o

C2

2

τ  dV  k o = 2∫   dt o  dt 

V 2 /s

(24.40)

where τ is the pulse width and Ri is the effective internal resistance, dominated by the contact resistance. For a ramp voltage change

dV V pp ≈ τ dt such that equation (24.40) gives

V2 k o ≅ 2 pp τ

and

k dV V pp ≅ = o dt τ 2V pp

(24.41)

This equation (24.41) shows that for a given capacitor, that is, a given ko, the lower the source peak to peak voltage, the higher the allowable dv/dt, hence higher peak current. For a passive RLC type discharges and short-circuit configurations, ko is

ko =

Vch2 RC

where R is the discharge circuit resistance and Vch is the source charging voltage.

Power Electronics

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Chapter 24

Capacitors

1132

Example 24.7: Capacitor non-sinusoidal voltage rating

24.3.5 DC plastic capacitors

A 0.15µF MKT capacitor is used to generate a 10 kHz maximum and 25µs rise-time minimum, saw-tooth ac voltage waveform. What voltage rated capacitor is applicable if the output voltage maximum is 100V p-p?

Significant increase in capacitance per unit volume per unit volt can be gained if plastic based capacitors are designed specifically for dc applications. Such applications include dc-link decoupling where electrolytic capacitors are avoided because of lifetime constraints and high-energy discharge capacitors; where voltage reversal is a critical parameter. Voltage reversal is the changing of the relative polarity of the capacitor terminals, such as experienced during ringing or oscillating pulse discharge, during ac operation, or as the result of dc charging the capacitor in the opposite polarity from which it had been previously dc charged. Voltage reversal is the percentage of the peak voltage that is experienced in the reverse polarity. In an ac application, the reversal is 100 %. Oscillating pulse discharges usually have between 0% and 100% voltage reversal. DC capacitors are designed for the highest level of voltage reversal (normal or fault) that may be experienced in service. Adversely, high reversal ratings result in significant reductions in energy density and increases in size and cost. The damage inflicted on a capacitor by a transient voltage reversal is a nonlinear function of the degree of reversal. As shown in Figure 24.22a, the change in life with between 80% and 85% reversal is much greater than the change between 20% and 30% reversal. The magnitude of the damage also depends on the rate of change of voltage during the reversal. The least deterioration is when the rate of change of voltage is slow, as in the case of dc charging the capacitor with the terminal connections reversed. The greatest damage occurs when the capacitor voltage ‘rings’ or oscillates at a high frequency, the effect of frequency on life is shown in Figure 24.22b.

Solution

Worst-case conditions are at maximum frequency, 10 kHz, and minimum risetime, 25 µs. With reference to figure 24.21, use f = 10 kHz (repetition frequency) τ = 25 µs (rise-time) C = 0.15 µF (capacitance) According to the dashed line in figure 24.21, starting from f = 10 kHz, yields VR = 100 V dc gives maximum peak voltage of 27 V VR = 250 V dc gives maximum peak voltage of 38 V VR = 400 V dc gives maximum peak voltage of 47 V VR = 630 V dc gives maximum peak voltage of 59 V The peak to peak requirement is 100 V, hence only a 630 V dc 0.1 µF MKT capacitor can fulfil the specification.

♣ An alternative approach to specify the voltage limits for non-sinusoidal repetitive voltages is to sum the power contribution due to each voltage harmonic. The total power due to all harmonics must not exceed the capacitor package power limits. The non-sinusoidal voltage v can be expressed in the form (24.42) v = ∑ Vi sin ( iωt + φi )

Capacitor life is extended by minimizing the degree of voltage reversal in the normal operating mode. A diode and series resistance in parallel with the capacitor can reduce voltage reversal. The smaller the series resistance, the lower the reversal on the capacitor.

where Vi is the magnitude of the ith voltage harmonic, which has an rms value of V vi = i 2 From equations (24.12) and (24.36), assuming capacitance is frequency independent Pi = ( Rs CR )i ωi2 CR vi2

i. Electric Fields Voltage reversals impact on the electric field magnitude in the capacitor dielectric. Dielectric overstresses result from the superposition of the applied reverse electric field and the remnant polarization field from the original dc polarity. At typical pulse capacitor discharge rates, the electronic, atomic, and permanent dipole polarizations reverse virtually in phase with the applied field. However, inherently ‘slow’ polarization mechanisms acting in the dielectric, such as interfacial polarization associated with charge injection and ionic conduction, do not. The longer the capacitor remains dc charged, the greater the remnant polarization field magnitude. This field (which is anti-parallel to the applied dc field) is added to the applied field during a voltage reversal, increasing the total field within the dielectric. Excessive fields can result in immediate breakdown or may produce partial discharging, treeing, or other degradation. Even in ac applications, where interfacial polarization may not have time to build up, charge can be injected from the electrodes into the adjacent dielectric, especially at sharp edges, one half-cycle, and then return to the electrode in the next half-cycle in a partial discharge process. Such discharges degrade the dielectric locally and eventually result in breakdown. Therefore, long-life ac capacitor elements are designed to operate at voltage levels where such charge injection is negligible. DC capacitors, on the other hand, can usually be operated at much higher stresses and can therefore be made smaller.

∀i

i

(24.43)

or Pi = tan δ i ωi CRi vi2

(24.44)

The total power dissipated is the sum of the powers associated with each frequency. The near-linear frequency dependence of tan δ and RS CR, as shown in figures 24.17a and 24.19, may be utilised to simplify the calculation procedure. Assuming the rated capacitance is independent of frequency may be a valid and helpful simplification, while the temperature dependence of CR initially could be accounted for by using a value at 10 K above ambient. Example 24.8: Capacitor power rating for non-sinusoidal voltages

The applied voltage across a 1 µF MKP capacitor, at 40°C ambient is √2 100 sin(2π × 104t) + √2 Y sin(2π× 3 x 104t) What is the maximum allowable third harmonic voltage Y? Solution From equation (24.44), the total power is given by Pi = tan δ1 ω1CR v12 + tan δ 3 ω3CR v32 1

3

From figure 24.16b we may assume that capacitance is independent of frequency for polypropylene types. From figure 24.16a, at 50°C, rated capacitance has reduced by only 1 per cent - thus temperature effects on CR may be neglected. From figure 24.17a, for a 600 V MKT capacitor tan δ1 at 10 kHz (ω1) = 2.5 × 10-4 tan δ3 at 30 kHz (ω3) = 4.2 × 10-4 From figure 24.18d it can be seen that 880 mW can be dissipated in the largest package at 50°C. Total power is given by 0.88W = 2.5 × 10-4 × 2π × 10 4 × 1× 10-6 × 1002 + 4.2 × 10-4 × 6π × 104 × 1× 10-6 × Y 2

Solving for Y, Y = 30.2 V rms.

♣

(W)

Operating mechanism during voltage reversal

ii. Heating The current waveform is used to determine the internal heating of a capacitor due to various energy loss mechanisms. The energy dissipated in the capacitor during a single charge/discharge cycle (Jcap) depends on the I2t integral of the current waveform and the equivalent series resistance (ESR) of the capacitor. The action involves the Joule's integral: T

J cap = ESR × ∫ I 2 (t ) dt 0

 Joules 

The ESR is not a true ohmic resistance and is a function of frequency, voltage, voltage reversal, temperature, and other parameters. The ESR includes a number of energy loss mechanisms, the two most important of which, in terms of voltage reversal mechanisms, are dielectric loss and electrode resistance. • The dielectric loss results from motion of bound charge within the dielectric (displacement current) such as molecular dipole rotation, in response to an applied electric field. It is the dissipation factor (DF), since the losses vary linearly with capacitance. • The electrode resistance is purely ohmic, with the skin effect becoming important at high frequencies. There are two basic types of electrodes used in film capacitors, discrete foils and

Power Electronics

1133

Chapter 24

metallisation. Foil electrode capacitors provide minimum ESR at high frequencies. Metallised electrodes can be used for relatively low frequency discharges (less than 10 kHz) where the ESR is dominated by the dielectric loss.

100

pu

90%

80% 70%

Lifetime multiplier

Life expectancy multiplier

Life expectancy multiplier pu

pu

pu

10

10

60% 50% 1

40% 30% 20%

30

40

50

Voltage reversal

60

tanδ

λo

dv/dt

self-healing

low

low

good

high

good

medium

high

poor

medium

good

polystyrene

low

low

good

high

poor

polycarbonate

low

medium

good

medium

good

medium

medium

good

medium

good

high

high

very good

high

very good

70 (pu)

80

mixed dielectric paper

24.4

Emi suppression capacitors

Non-polarised capacitors are used in rfi filters for electrical appliances and equipment, as was introduced in 10.2.4. The capacitors (7 classifications in all) used between line and neutral are termed class X while those used to earth are termed class Y. 24.4.1 Class X capacitors

X capacitors are suitable for use in situations where failure of the capacitor would not lead to danger of electric shock. X capacitors, for 250V ac application, are divided into two subclasses according to the ac power line voltage applied. • The X1 subclass must support a peak voltage in excess of 1.2 kV in service, while • X2 capacitors have peak service voltage capabilities of less than 1.2 kV. In order to obtain the peak voltage requirement of X1 capacitors, a construction comprising impregnated paper dielectric and metal foil electrodes is essential. The common X1 capacitance range is 10 nF to 0.2 µF. Class X1 is impulse tested to 4kV and 2.5kV for X2. Both are tested to higher voltages if C ≥ 1µF. The lower peak voltage requirement of X2 capacitors allows the use of a metallised plastic dielectric, of which polyester and polypropylene are common. Impregnated paper dielectrics may also be employed. Advantageously, metallised plastic film suppression capacitors yield high dv/dt capability with low associated losses, tan δ, as shown in figure 24.17a. These films also offer good insulation properties as shown in figure 24.15. Variation of capacitance with frequency and temperature is shown in figure 24.16, while percentage variation of losses, tan δ, with frequency and temperature is shown in figure 24.23. The typical capacitance range of X2 capacitors is from 10 nF to 1 µF, rated for 250 V ac application. 24.4.2 Class Y capacitors

0.1 20

εr

polypropylene

1

10% 0.1 10

dielectric type polyester

Capacitors designed to operate for long lifetimes (>107 pulses) at relatively low electric field stresses are more robust in the event of fault condition reversals, and capacitors being operated at well below their rated voltage are more likely to survive.

1134

Table 24.5: Properties of non-polarised plastic type capacitors

Capacitor design for voltage reversal

The critical aspects of the capacitor design in relation to voltage reversal effects are the dielectric materials, the rated voltage and rated electric field, and the type of electrode and internal connections. The resistance of different dielectrics to voltage reversal effects vary. • A paper dielectric is suitable for high reversal discharge applications. Mixed dielectrics such as paper and polypropylene laminates are more susceptible to damage in voltage reversal than allpaper dielectrics because of interfacial polarization. All-polypropylene dc capacitors are highly susceptible to foil edge failure at moderate voltage reversal. • Dry capacitors should be used in high reversal applications only at low voltage (less than 1kV) and low stress. A liquid impregnant should be incorporated in the dielectric to suppress partial discharges. Some impregnant materials are able to absorb gases and other decomposition products better than others. • Metallised capacitors are more robust than foil capacitors in terms of ability to survive high reversal discharges without immediate failure. As long as ratings are not exceeded, high reversals simply accelerate the rate of capacitance loss. If peak current or ratings are exceeded, however, failure of the internal connections may occur, resulting in large capacitance loss, increased DF and ESR, and reduced voltage capability.

Capacitors

10

3

4

10

Frequency

10 f

5

6

10

(Hz)

Figure 24.22. Effects of: (a) dc capacitor voltage reversal on lifetime and (b) lifetime versus frequency of voltage reversal oscillation.

The key properties of plastic type non-polarised capacitors are summarised in Table 24.5. The excellent dielectric properties of polypropylene lead to metallised polypropylene capacitors being extensively used in power applications. Polycarbonate film based capacitors (KC and MKC) are obsolete. Mixed dielectric alternatives, based on polyethylene-terephthalate and polypropylene are recommended, but no alternative matches the excellent temperature and high frequency properties of polycarbonate.

Class Y capacitors are suitable for use in situations where failure of the capacitor could lead to danger of electric shock. These capacitors have high electrical and mechanical safety margins so as to increase reliability and prevent short circuit. They are limited in capacitance so as to restrict any ac current flowing through the capacitor, hence decreasing the stored energy to a non-dangerous level. An impregnated paper dielectric with metal foil electrodes is a common construction and values between 2.5nF and 35nF are extensively used. Capacitance as low as 0.5nF is not uncommon. A Y-class capacitor for 250V ac application can typically withstand over 2500V dc for 2s, layer to layer. On an ac supply, 425V ac (√3 VR) for 1000 hours is a common continuous ac voltage test. Class Y1 is impulse voltage tested to 8kV, and 5kV for Y2. If dv/dt capability is required, polypropylene film dielectric Y-class capacitors are available, but offer lower withstand voltage capability than paper types. Generally paper dielectric capacitors offer superior insulation resistance properties, as shown in figure 24.15a. Metallised paper capacitors are also preferred to metallised plastic types because they have better selfhealing characteristics. Breakdown in metallised plastic film dielectrics causes a reduction of the insulation resistance because of a higher carbon deposit in the breakdown channel than results with paper dielectrics.

Power Electronics

1135

Chapter 24

Capacitors

1136

24.4.3 Feed-through capacitors

MFP

MKN

Feed-through or four-terminal capacitors are capacitors in which the operating current flows through or across the electrodes. High frequency rfi is attenuated by the capacitor and the main power is transmitted unaffected. That is they suppress emi penetration into or from shielded equipment via the signal or power path. Figures 24.23a and b show three terminal feed-through capacitors while figure 24.23c is a four-terminal capacitor. A three-terminal coaxial feed-through, wound capacitor cross-section is shown in figure 24.23d. The feed-through rod is the central current-carrying conductor: the outer case performs the function of an electrode plate and connector to produce an RF seal between the capacitor case and shielding wall. These capacitors are effective from audio frequencies up to and above the SW and VHF band (>300 MHz). Current ratings from signal levels to 1600 A dc, 1200 A ac are available, in classes X1 and X2, rated at 240 V ac, 440 V ac, and 1000 V dc. Class Y feed-through capacitors rated at 25 A and 440 V ac, 600 V dc are available. Important note: This section on emi-suppression capacitors does not imply those requirements necessary to conform to governmental safety and design standards.

24.5

Ceramic dielectric capacitors

Ceramic capacitors as a group have in common an oxide ceramic dielectric. The dielectric is an inorganic, non-metal polycrystalline structure formed into a solid body by high temperature sintering at 1000 to 1300°C. The resultant crystals are usually between 1 and 100µm in diameter. The basic oxide material for ceramic capacitors is titanium dioxide (Ti02) which has a relative permittivity of about 100. This oxide together with barium oxide (Ba02) forms barium titanate (BaTi03) which is a ferro-electric material with a high permittivity, typically 104. Alternatively, strontium titanate may be utilised. These same materials are used to make positive temperature coefficient resistors - thermistors, where dopants are added to allow conduction. Metal plates of silver or nickel (with minimal palladium and platinum) are used to form the capacitor. Single plate, or a disc construction, is common as is a multi-layer monolithic type construction. The ceramic dielectric is split into two classes, as shown in Table 24.6. Figure 24.23. RFI capacitance variation with: (a) ambient free-air temperature and (b) frequency.

Table 24.6: Ceramic dielectric capacitor characteristics Dielectric class EIA-designation* IEC/CECC designation Temperature range Dielectric constant

see table 24.8 °C εr

Temperature coefficient of CR

(typical) Dissipation factor

tan δ

I

II

(εr < 500) Low K COG CG -55 to 125

(εr > 500) Moderately high K High K X7R Z5U 2C1 2F4 -55 to 125 + 10 to 85

13 - 470 (N150) -150 ± 60 ppm 0.15% @ 1 MHz

700 (X7R) ±15% 2.5% < 4.7

Capacitance

C

nF

< 0.2

Rated voltage

VR

V

500-1k

to

50,000 (Z5U) +22% / -56%

3% < 40 100 to >2k

* In EIA designation, first letter and number indicate temperature range while last letter indicates capacitance change.

Figure 24.23. Feed-through capacitors for RFI attenuation: (a), (b) three user terminals; (c) four terminals; and (d) coaxial feed-through capacitor construction.

1137

Power Electronics

Chapter 24

Capacitors

1138

Table 24.7: Characteristics of class I and II type dielectrics Class I

Class II

Almost linear capacitance/temperature function

Non-linear capacitance/temperature function

No voltage dependency of capacitance and loss angle No ageing

Slight ageing of capacitance

High insulation resistance

High insulation resistance Extremely high capacitance value per unit volume

Very small dielectric loss High dielectric strength Normal capacitance tolerance ±1% to ±10%

Normal capacitance tolerance ±5% to -20+80%

Table 24.8: Class II ceramic capacitor parameter coding – EIA designation

Dielectric class II (and higher) capacitor ceramic code Letter code

Z

lower temperature

Number code

upper temperature

2

+45°C

+10°C

4

Y

-30°C 5

X

+65°C

-55°C

+85°C

6

+105°C

7 8 9

+125°C +150°C +200°C

A

∆C over temperature range, ∆T ±1.0%

B

±1.5%

C

±2.2%

D

±3.3%

E

±4.7%

Letter code

F

±7.5%

P

±10.0%

R

+15.0%

S

±22.0%

T

+22% to -33%

U

+22% to -56%

V

+22% to -82%

24.5.1 Class I dielectrics

This class of dielectric consists mainly of Ti02 and additions of Ba0, La203 or Nd205, which provides a virtually linear, approximately constant and low temperature coefficient as shown in figure 24.25a. COG [EIA or industry code alternative NP0] capacitors belong to the class I dielectrics and have a low temperature coefficient over a wide temperature range, as seen in Table 24.6. They provide stability and have minimum dissipation properties. In attaining these properties, a low dielectric constant results and these capacitors are termed low K. Because of the low dielectric constant, capacitance is limited. 24.5.2 Class II dielectrics

Figure 24.25. Typical properties of commercial ceramic capacitors: (a) capacitance change with temperature; (b) dissipation variation with temperature; (c) capacitance change with dc voltage; (d) ESR change with frequency; (e) capacitance change with ac voltage; (f) dissipation factor variation with ac voltage; (g) capacitance change with frequency; and (h) dissipation factor variation with frequency.

Ceramic capacitors in this class are usually based on a high permittivity ferroelectric dielectric, BaTi03, hence termed hi K. Large capacitance in a small volume can be attained, but only by sacrificing the temperature, frequency, and voltage properties, all of which are non-linear. Typical characteristics are shown in figure 24.25. Their characteristics are less stable, non-linear, and have higher losses than class I ceramic, as seen in table 24.6. See Table 24.7 for a comparison between types and Table 24.7 for class II dielectric coding for capacitance variation for different temperature ranges, e.g. X7R, Z5U.

Power Electronics

1139

Chapter 24

The mean time between failure λo is transformed from the rated voltage and temperature conditions to the operating conditions by equation (24.16), that is n

E

a V  − K λ = λo × acceleration factors = λo  op  e  VR 

1  T 

− 1

 

To 

where the activation energy Ea and voltage index n are shown in Table 24.9. K is Boltzmann’s constant, 8.625x105 eV/K. Table 24.9: Accelerated MTBF factors

NP0

Ea activation nergy eV 1.15

X7R

1.15

2.9

Y5V

1.07

2.4

Dielectric type

n

voltage index 2.9

Capacitors

1140

The assembled unit is encapsulated by dipping it into high melting temperature microcrystalline wax or by dipping in phenolic resin, then vacuum impregnating with liquid epoxy resin. Mica capacitors are non-magnetic, non-polar, low loss, and stable up to about 30 MHz, where the lead length and electrodes dominate as inductance, typically 5 to 10nH. They are characterised by extremely low capacitor coefficients of temperature and voltage over a wide parameter operating range. Mica has a typical impregnated relative permittivity of 4.5 to 6.5 and a density of 1.65 g/ cm3. Alternatively, synthetic fluorine mica, fluorophlogopite KMg3(AlSi3O10)F2, contains no (OH)- of the natural phlogopite KMg3(AlSi3O10)(OH)2. The (OH)- is fully substituted with F-. Large fluorine mica crystals of high quality are grown using platinum crucibles with seeds. It has properties similar to natural mica: Melting temperature Density Dielectric strength Volume resistivity Surface resistivity Dielectric constant Dielectric loss Tensile strength

o

C 1378 g/cm3 2.8 kV/mm ~180 Ω-cm 4x1016 Ω-cm 3x1012 ε ~6 tgδ 1MHz 3x10-4 2 kg/cm ~1500

24.5.3 Applications

Flat circular disc ceramic (Z5U dielectric, high K) capacitors have a 2000 V dc, 550 V ac rating with capacitances of up to 47 nF. An exploitable drawback of such a ceramic capacitor is that its permittivity decreases with increased voltage. That is, the capacitance decreases with increased voltage as shown in figure 24.25c. Such a capacitor can be used in the turn-off snubber for the GTO thyristor and diodes which are considered in 8.1.3 and 8.1. High snubbering action is required at the commencement of turnoff, and can subsequently diminish without adversely affecting losses or the switching area trajectory tailoring. The capacitor action is a dual to that performed by a saturable reactor, as considered in 8.3.4. Exploitation of voltage dependence capacitance is generally outside the capacitor specification. Advantageously, the disc ceramic capacitor has low inductance, but the high dissipation factor may limit the frequency of operation. Multi-layer ceramic capacitors can be used in switched mode power supply input and output filters. Piezoelectric effects (change of physical size when an electric field is applied) can cause failure due capacitor cracking in traditional X7R class II ceramic capacitors. Figure 24.26. Silver mica capacitor: (a) exploded construction view and (b) electrode pattern of a silvered mica plate.

24.6

Mica dielectric capacitors

The dielectric mica can be one of 28 mica types. It is a naturally occurring inorganic, chemical resistant, clear mineral aluminosilicate (usually India Ruby muscovite, is a hydrated silicate of potassium and aluminum, H2KAl3 (SiO4)3) which has a plane of easy cleavage enabling large sheets of single crystal to be split into thin 20-100 µm plates, typically 50 µm. The general formula for mica is AB2-3 (Aℓ, Si)Si-3 O-10 (F, OH)-2. In most micas the A is usually potassium, K, but can be calcium, Ca, sodium, Na, barium, Ba, or some other elements in the rarer micas. The B in most micas can be aluminum, Aℓ, and/or lithium, Li, and/or iron, Fe, and/or magnesium, Mg. Phlogopite mica is a hydrated silicate of potassium and magnesium. Ultra thin silver electrodes are screen printed on to both sides of the mica (and over the edge), as shown in figure 24.26b, which is then fired in an oxidisation atmosphere to obtain a permanent plated adhesive bond between the mica and silver. Variation of silver electrode thickness affects the dissipation factor, while the overlapped printed silver area and mica thickness control the capacitance. A number of different techniques (and combination of different techniques) are used to parallel connect (parallel stack) the silver coated mica plates in order to give high capacitances.

• •

Multiple layers of over-the-edge printed mica plates are stacked together (without any interposing foils), as shown in figure 24.26a. The printed silver at each opposite edge is bonded with silver paste, on to which the terminals are directly soldered. Multiple silver printed plates are stacked interleaved with metal outer foils for contacts, The foils are made of silver, copper, brass, tin or lead. The foil alternately extends from each end and covers a portion of the plated area. Joining the extended foils at each end, parallel connects each individual mica plate. The stack is held and compressed together either by the encapsulation or by bending the extended foils over the top of the stack which is held by a brass metal (tin coated) crimp, which also acts as a heat sink. Copper clad (for at least 30% conductivity) steel leads are spot-welded to each clip, which is then solder coated.

24.6.1 Properties and applications

Maximum ratings are a few nanofarads at 50 kV, to 5µF at 1500V, with dissipation factors of 0.1 per cent at 1 kHz. Low dissipation factor is countered by poor dielectric absorption. A 10nF, 50kV mica capacitor in a cylindrical volume of Φ = 150mm×H = 120mm, has 300

2

6

2

9 250

PR

W

Maximum temperature

Th

°C

150

125

300

175

100

235

275

160

150

200

Working voltage

Vm

V

500

500

500

1k

100k

650

2.5k

160

500

700

Voltage coefficient

φ

10-6/ V

200

50

5

10

-

0.1

200 V) are common in power circuits and the physical construction of a resistor places a limit to allowable voltage stress levels. Certain applications within the realm of power electronics may necessitate a power resistor with a low temperature coefficient of resistance (or even a negative temperature coefficient), a high operating temperature, a high pulse power ability or even a low thermoelectric voltage. Any one of these constraints would restrict the type and construction of resistor applicable.

Table 25.1: The main characteristics of electrical power resistors

glazed thick film

(6.1.2,8.1, 8.3) (6.1.2, 8.3.3) (8.2) (10.1.1) (10.1.2) (10.2.3) (10.2.3)

metal thin film

Series R-C circuit for diode, mosfet and thyristor snubbers (non-inductive) Series turn-on L-R-D snubbers R-C-D turn-off snubbers for GTO thyristors - inductance in R is allowable Static voltage sharing for series connected capacitors and semiconductors Static current sharing for parallel connected semiconductors Resistor divider for proportional voltage sensing Current sensing Damping, clamping, and voltage dropping circuits

Almost all types of power resistors ( ≥1W) have a cylindrical high purity ceramic core, either rod or tube as shown in figure 25.1. The core has a high thermal conductivity, is impervious to moisture penetration, is chemically inert, and is capable of withstanding thermal shock. The resistive element is either a carbon film, a homogeneous metal-based film or a wound wire element around the ceramic body. For high accuracy and reliability, a computer-controlled helical groove is cut into the film types in order to trim the required ohmic resistance. The resistance tolerance can be typically ± 5% for wire wound resistors and better than ± 0.1% for trimmed film types. The terminations are usually nickel-plated steel, or occasionally brass, force fitted to each end of the cylindrical former in order to provide excellent electrical and thermal contact between the resistive layer and the end-cap. Tinned connecting wires of electrolytic copper or copper-clad iron are welded to the end-caps, thereby completing the terminations. Axial cylindrical resistors without leads, used as surface mount resistive devices (SMD), are termed metal electrode leadless face, MELF. All fixed resistance resistor bodies are coated with a protective moisture-resistant, high dielectric field strength, and some times conformal coating, such that the wire terminations remain clear and clean. The resistors are either colour coded by colour bands or provided with an identification stamp of alphanumeric data.

carbon deposited film

Power resistors (≥1W) are used extensively in power electronic circuits, either as a pure dissipative element, or to provide a current limiting path for charging/discharging currents. Depending on the application, these energy transfer paths may need to be either inductive or non-inductive. Power resistors are used for the following non-inductive resistance applications.

Resistor construction

carbon composition

Resistors

Fuse Power Current sense Circuit breaker

BWW

Resistor types

The resistor tree illustrates the main types of resistors used in electrical power applications. The three main resistor types are carbon/metal film, solid, and wire wound. The main electrical and thermal properties of each resistor type are summarised in table 25.1. Typical property values for power resistors are shown, which may vary significantly with physical size and resistance value.

25

• • • • • • • •

1146

25.2.1 Film resistor construction Figure 25.1a shows a sectional view of a typical film resistor having a construction as previously described. The resistive film element is produced in one of four ways: • cracked carbon film • glaze of glass powder mixed with metals and metal compounds fired at 1000°C, giving a firmly bonded glass-like film on the core

1147

Power Electronics

Resistors

Chapter 25

1148

Thick film, as used for low cost surface mount (SMD) resistors, employs traditional liquid screen printing technology baked at 850°C, as opposed to spluttering type technology for thin film resistors. As a result thin film resistors are • more expensive than thick film resistors • have better tolerances, typical 0.1% to 1% and a temperature coefficient of ±5 to ±25 ppm, because the spluttering time can be used to control the film thickness Thick film tolerances are typically: 1 to 2% on resistance and a temperature coefficient of ±200ppm. 0

black

1 brown 2 red 3 orange 4 yellow 5 green 6 blue 7 8

violet grey

9

white

±1% ±2%

±½% ±¼% ±% ± 201 %

× gold

±5%

× silver

±10%

(d)

Resistive materials such as polymer and ruthenium oxide RuO2 are used for high voltage and high resistance resistors up to 100 kV, 1 GΩ and 20 kV, 150 GΩ respectively. Ruthenium oxide is called a cermet since it is a composite of a ceramic and a metal. At lower voltage ratings, the same oxide is used to produce planar thick film power resistors, which are mounted on an alumina substrate to give a low thermal resistance for better cooling. The planar strip structure gives a low inductance element with a high surface area for better heat transfer. Dissipation levels of over 200W, up to 900W, are possible when packaged in TO220, ISOTOP, etc. type packages, which can be heatsink mounted. 25.2.2 Carbon composition film resistor construction A sectional view of a moulded carbon composition film resistor is shown in figure 25.1b. The resistive carbon film is cured at 500°C and is unspiralled, hence non-inductive with excellent high frequency characteristics. The resistance value is obtained by variation of film composition and thickness, which may be between 0.01 µm and 30 µm. A component with a wide nominal value tolerance results since the film is not helically trimmed. A special formed one-piece talon lead assembly is deeply imbedded into the substrate for good uniform heat dissipation. These terminations are capless. The following example illustrates typical parameters and dimensions for carbon film resistors. Example 25.1: Carbon film resistor A 470 Ω resistor is constructed from a film of carbon with a resistivity 3.5 × 10-5 Ω m, deposited on a non-conducting ceramic bar 3 mm in diameter and 6 mm long. Calculate the thickness of film required, ignoring end connection effects. Solution Let thickness of the film be t metre, then cross-sectional area ≈ π × 3 × 10-3 × t (m2) Now R = ρℓ /area, that is 470Ω = 3.5×10-5×6×10-3/π×3×10-3×t t = 0.0474 µm

♣ 25.2.3 Solid carbon ceramic resistor construction Figure 25.1. Power resistor construction: (a) metal glaze, thick film; (b) moulded carbon composition film; (c) wire wound aluminium clad; and (d) resistance colour code and tolerances.

• •

precisely controlled thin film of metal alloy (Cr/Ni or Au/Pt) evaporated, baked or vacuum sputtered (vacuum deposition) on to the inert core and of thickness between 10-8m and 10-7m metal oxide (Sn02) resistive film deposited or sintered on to the core.

The film materials exhibit a wide range of resistivity, ρ, which extends from 40 × 10-6 Ω cm for gold/platinum to in excess of 102 Ω cm for layers of thick film mixture. The thinnest possible film, for maximum resistance, is limited by the need for a cohesive conductive film on the ceramic substrate while the thickest film, for minimum resistance, is associated with the problem of adhesion of the resistance film to the substrate. The helical groove shown in figure 25.1a, used to trim resistance (by increasing the length of the film width), is shown clearly and is either laser or diamond (abrasive) cut. The residual inductance is significantly increased because of the formed winding which is a spiral around the core. Below 100 Ω, a helical groove may not be used. The difference between thick and thin film is how the film is applied (not necessarily the film thickness).

Mixtures of finely ground, powdered clay, alumina, and carbon are blended with resin, pressurised into the desired shape (diameters from less than 0.3mm to over 15mm), and fired in a tunnel kiln, at high temperature and controlled pressure. The higher the carbon concentration, the higher the resistivity (resistance). This sintering process results in a 100% active homogeneous, solid volume resistive element, in a minimum size. Aluminium (and/or copper brass, silver, nickel) is then flame-sprayed on to the appropriate surfaces to provide electrical contact, followed by gold plated spring pin terminations, if to be used for pcb mounting. Then an anti-tracking epoxy resin coating is applied using a fluidised bed technique, to improve dielectric withstand, mechanical robustness, and minimise corrosion. Although the coating reduces the rate of moisture ingress, the element is not impervious to liquid, so after drying for 24 hours at 110-120°C, it is silca gel coated if the resistor is to be immersed in SF6 gas or oil. Because of the solid construction, the ceramic carbon element has a high surge energy rating, high voltage withstand, high transient voltage impulse withstand, inherent low inductance, higher thermal capacity, and is mechanical robust; with compact size and a wide range of geometries. It is brittle to direct mechanical impact. Also, because of its homogeneous physical and chemical structure, resistor mechanical, electrical, and thermal properties and characteristics can be defined mathematically or empirically. At high electrical stress levels, the resistivity property change. Mechanical, thermal, and electrical data is presented in Appendix 25.8 for solid ceramic carbon. Rod, disc, and tube shapes are common, with resistance tolerances of not better than ±5%.

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Chapter 25

Resistors

1150

The terminal resistance is a function of temperature, voltage, and frequency. Temperature dependence is due to the temperature dependence of resistivity α, typical values of which are shown in table 25.1. The temperature coefficient may vary with either or both temperature, as with carbon and metal film resistors, or resistance, as with thick film and noble metal film resistors. A reference for measurement is usually 25°C. Frequency dependence is due to a number of factors, depending on the type of resistive element and its resistance value. Typical factors are due to skin effects in the case of wire-wound resistors or residual capacitance in film types. Frequency dependent resistance, Rac, for carbon composition film and metal glaze thick film resistors, is shown in figure 25.3. A voltage dependence factor, which is called φ , is given in table 25.1 and is resistive element type dependent. For operation at low frequencies, resistance is given by R ( v, T ) = R ( 0, 25°C )(1 + φ v )(1 + α T ) (Ω) (25.3)

25.2.4 Wire-wound resistor construction The sectional view of an aluminium-housed power wire-wound resistor, shown in figure 25.1c can dissipate up to 300 W with a suitable heatsink in air or up to 900 W when water-cooled. The central former is a high purity, high thermal conductivity ceramic, of either Steatite or Alumina tube, depending on size. The matching resistive element is iron-free, 80/20 nickel-chromium for high resistance values or copper-nickel alloy for low resistance. These alloys result in a wire or tape which has a high tensile strength and low temperature coefficient. The tape or wire is evenly wound on to the tube former with a uniform tension throughout. This construction is inductive but gives a resistor which can withstand repeated heat cycling without damage. The assembled and wound rod is encapsulated in a high temperature thermal conducting silicone moulding material and then cladded in an extruded, hard, anodised aluminium housing, ensuring electrical and thermal stability and reliability. Alternatives to the aluminium-clad resistor are to encapsulate the wound rod in a vitreous enamel or a fire-proof ceramic housing. Power wire-wound resistors with a low temperature coefficient, of less than ±20×10-6 /K, use a resistive element made of Constantan (Nickel and Copper) or Nichrome (Nickel and Chromium). Constantan is used for lower resistance, up to several kilo-ohm, while Nichrome is applicable up to several hundred kilo-ohm. The resistance ranges depend on the ceramic core dimensions, hence power rating. The element is wound under negligible mechanical tension, resulting in a reliable, low temperature coefficient resistor which at rated power can safely attain surface temperatures of over 350°C in a 70°C ambient. Because these resistors can be used at high temperatures, the thermally generated emf developed at the interface between the resistive element and the copper termination can be significant, particularly in the case of Constantan which produces -40 µV/K. Nichrome has a coefficient of only + 1 µV/K, while gold, silver, and aluminium give +0.2, -0.2, and -4 µV/K, respectively, when interfacing with copper. EMF polarities cancel with identical resistor terminations.

Values for linearity coefficients φ and α are given in table 25.1. Ideally, electrically, the terminal voltage and current are in phase and related by Ohm’s law, namely v = i×R (V) (25.4) where it is usually assumed that R is constant. This electrical relationship is shown in the phase diagram in figure 25.2. In practice when a pure sinusoidal current is passed through a resistor its terminal voltage may not be a pure sinusoid, and may contain harmonic components. This voltage distortion is termed nonlinearity and is the harmonic deviation in the behaviour of a fixed resistor from Ohm’s law, equation (25.4). Another resistor imperfection is current noise which is produced by the thermal agitation of electrons due to resistive element conductivity fluctuation. The noise voltage is proportional to current noise flow. Johnson noise is given by E rms (t ) = 4k R T ∆f , where ∆f is the measurement bandwidth and k is Boltzmann’s constant. Wire-wound resistors generate negligible current noise. The resistance value itself can change: long term drift due to chemical-physical processes such as oxidation, re-crystallisation corrosion, electrolysis, and diffusion, as may be appropriate to the particular resistive element.

Ayrton-Perry wound wire elements can be used for low inductance applications. The resistive element is effectively wound back on itself, such that the current direction in parallel conductors oppose. Either a bifilar winding or an opposing chamber winding is used. The net effect is that a minimal magnetic field is created, hence residual inductance is low. The maximum resistance is one-quarter that for a standard winding, while the limiting element voltage is reduced, by dividing by √2. The low inductance winding method is ineffective below 4.7Ω. This winding style also lowers the maximum permissible winding temperature, called hot spot temperature, Th. The hot spot temperature is the resistor surface temperature at the centre of its length. 25.3

Electrical properties

An electrical equivalent circuit for a wirewound resistor is shown in figure 25.2. The ideal resistor is denoted by the rated resistance, RR, and the lumped residual capacitance and residual inductance are denoted by Cr and Lr respectively. A film type resistor is better modelled with the capacitance in parallel with the resistive component. The terminal resistance of a homogeneous element of length ℓ and area A is given by A A R ( v, f , T ) = ρ ( v , f , T ) = (Ω) (25.1) A σA where ρ is the resistivity of the resistive element and σ is the conductivity (= 1/ρ). The total effective resistance of series and parallel connected resistive elements are given by

(a)

R s = R1 + R 2 + R 3 + ... 1

Rp Z =

=

1

R1

+

1

R2

+

1

R3

(b)

(25.2)

+ ... Q

RR 2 RR ( X Lr − X Cr ) + X Cr2 X Cr2 2

+j

2 2 X Lr − (RR + X Lr ) / X Cr 

RR2 ( X Lr − X Cr ) + X Cr2 X Cr2

v

2

i

v

P Ω

i Figure 25.2. Equivalent circuit model of a resistor.

Figure 25.3. Resistor high frequency characteristics: (a) of a metal glaze thick film 3 W resistor and (b) moulded carbon composition film resistors.

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Resistors

Chapter 25

The power dissipated, Pd, in an ideal resistor, in general, is specified by 2 2 Pd = vi = irms R = vrms /R (W) (25.5) where the power dissipated is limited by the power rating, PR, of the resistor. In turn, the power limit may also set the maximum voltage that can be withstood safely. Joules law of heat generated is Q=I2Rt.

Alternatively, solid carbon ceramic resistive elements may have a temperature coefficient defined in terms of resistivity (in Ω-cm), as an empirical formula such as: α = +1600 × e− log ρ /1.4 − 1350 (25.8) (10-6 /°C or ppm/°C ) Example 25.2: Temperature coefficient of resistance for a thick film resistor

25.3.1 Resistor/Resistance coefficients Three mechanical, thermal or electrical coefficients are relevant to a resistor and its resistance • coefficient of linear expansion • temperature coefficient of resistance, α • voltage coefficient of resistance, Φ The coefficient of linear expansion is only relevant to solid carbon ceramic type resistors. It is dependant on resistivity, ρ, and is in the range +4×10-6 to +10×10-6 /°C. The voltage and temperature coefficients of resistance are also dependant on the resistivity of the resistive element. 25.3.1i - Temperature coefficient of resistance - α The resistance temperature coefficient α in equation (25.3) and in table 25.1 should not be taken as to imply a linear relationship between temperature and resistance, 1+Φ×V. Quite the contrary, for simplicity, it is only a linear approximation to a quadratic approximation of a non-linear function, as shown in figure 25.4. This figure shows the resistance behaviour of a typical thick film resistor, with varied temperature. The lower the temperature coefficient, the flatter the resistance-temperature curve. The temperature dependant relationship is modelled by a quadratic equation: R (T ) = Ro + aT 2 + bT + c (25.6) where a, b, and c are the quadratic coefficients and Ro is the minimum resistance value, which for this resistor type, usually occurs around 35°C. The temperature at which the minimum resistance Ro occurs can be varied by changing the resistor chemical composition. The temperature co-efficient α is related to the slope ∆R/∆T and is defined by R (T ) − R ( 25°C ) ∆R 106 × 106 = × α (T ) = (25.7) (10-6 /°C or ppm/°C ) ∆T × R ( 25°C ) ∆T R ( 25°C ) Given the normal temperature operating range for resistors, it is usual when characterising resistors, to use 25°C as a reference with a +50°C temperature change, that is ∆T = +50°C. The resultant resistance change for this ∆T = +50°C defines the temperature co-efficient. It will be seen that the definition coefficient slope is not necessarily the maximum slope in the range 25°C to 75°C. R pu

R(T) 1.0012

1.0010

Figure 25.4 shows a quadratic approximation for the variation of per unit resistance with temperature, with a minimum resistance of 0.999935pu occurring at 35°C, and 1pu resistance at 25°C and 45°C. Determine i. suitable model quadratic coefficients a, b, c ii. the 0°C pu resistance iii. the temperature co-efficient of resistance based on ∆T = +50°C and ∆T = +40°C and the resistance change in each case, with a 25°C reference, point x iv. the incremental temperature coefficient over the range 25°C to 75°C v. the temperature co-efficient of resistance based on ∆T = +50°C and ∆T = +40°C and the resistance change in each case, with a 20°C reference, point y vi. the minimum resistance occurs at 45°C, with the identical shape. Determine the resistance temperature coefficient (∆T = 75°C - 25°C) of the resultant resistor Solution i. Assuming the temperature dependant resistance data in figure 25.4 is curve fitted by a best fit quadratic, then that quadratic has roots at T = 25°C and T = 45°C, thus after shifting the Y-axis (Rpu) by 1pu: R pu − 1 = a (T − 25°C )(T − 45°C ) ∨

To ensure accuracy in the normal operating range, the minimum resistance point R , (35°C, 0.999935) is used to find the second order temperature term co-efficient, and R pu − 1 = a × (T − 25°C )(T − 45°C ) 0.999935 − 1 = a × ( 35°C − 25°C )( 35°C − 45°C ) ⇒ a = 6.5 × 10−7

The quadratic coefficients are thus R pu − 1 = 6.5 × 10 −7 × (T − 25°C )(T − 45°C ) R pu − 1 = 6.5 × 10 −7 T 2 − 4.55 × 10 −5 T + 7.3125 × 10−4 or R pu = 6.5 × 10 −7 T 2 − 4.55 × 10 −5 T + 1.00073125

ii. Substituting 0°C into the quadratic gives the constant c, that is 1.000731 - 0.999935 = 0.00080, as can be confirmed from the best fit plot in figure 25.4. iii. When using 25°C as the parameter specification reference, point x, the quadratic is used to give the pu resistance at points A (75°C) for ∆T = +50°C and B (65°C) for ∆T = +40°C shown in figure 25.4. For point A: R − Rpu −a α ∆TT==2550°°CC = pu− A TA − Ta o

A (75°,1.00098)

=

1.0008 C

0°C,1.00073

α ∆TT==2540°°CC = o

Slope = 20ppm/°C

B (65°,1.00052)

1.0004 z

∆R

=

D

∨

(15°,1.0002)

1.0002

(60°,1.00034)

R

y

∆T

(20°,1.00008)

0

10

20

x

30

Temperature

40 (°C)

50

60

70

Rpu −B − R pu −a TB − Ta 1.00052pu -1pu = 13.0 × 10−6 ( / °C ) or 13 ppm/°C 65°C − 25°C

iv. The tangential slope to the quadratic is the differential of the quadratic: α = 13.0 × 10 −7 × T − 4.55 × 10 −5 α 25°C = 13.0 × 10 −7 × 25°C − 4.55 × 10 −5 = −13 ppm/°C

(35°,0.999935)

1.0000

1.00098pu -1pu = 19.6 × 10−6 ( / °C ) or 19.6ppm/°C 75°C − 25°C

For point B:

(70°,1.00073)

1.0006

1152

α 35°C = 13.0 × 10 −7 × 35°C − 4.55 × 10 −5 =

80 T

Figure 25.4. Typical temperature characteristics of resistance for thick film resistors.

0 ppm/°C

α 75°C = 13.0 × 10 −7 × 75°C − 4.55 × 10 −5 = +52ppm/°C The temperature coefficient ranges from -13 to 52 ppm/°C.

Power Electronics

1153

v. When using 20°C as a parameter specification reference, point y, the quadratic is used to give the pu resistance at points C, ∆T = +50°C, and D, ∆T = +40°C, shown in figure 25.4. For point C: R − Rpu −b α ∆TT==2050°°CC = pu −C TA − Ta o

=

1.00073pu -100008pu = 13.0 × 10−6 ( / °C ) or 13.0 ppm/°C 70°C − 20°C

For point D:

α ∆TT==2040°°CC = o

1154

For voltage pulses in the range of t =10ms to 50ms, the maximum working voltage per cm of resistor length is 0.335 0.335 ρ  R A = 1.00 ×  Vl = 1.00 ×   (kV/cm ) in SF6 gas  t  t A (25.10) 0.3 0.3 ρ  R A kV/cm in air Vl = 0.87 ×   = 0.87 ×  ( )  t  t A Low resistance values (100Ω): For transient impulse voltages across high resistances, the maximum working voltage per cm length is    ρ  Vl = c ×  −1 + 1 + a (25.13) ( kV ) ρ A  = bR × −1 + 1 + a / R A   A   where a and b are specified for a given resistance (area and length). a increases with length and decreases with area b is independent of length and increases with area The constant a increases and b decreases, as the impulse period (time) increases. 5 4

5 4

(

)

25.3.3 Residual capacitance and residual inductance

Vl

Voltage limit

Power limit

Generally, all resistors have residual inductance and distributed shunt capacitance. Inductance increases with both resistance and power rating as shown by figure 25.6, while residual capacitance increases mainly with increased pulse rating. For example, a 2 W metal oxide film resistor (typical of film resistors) has ½ pF residual capacitance and inductance varying from 16 nH to 200 nH. A ¼ W family member has 0.13 pF of capacitance and 3 to 9 nH of inductance.

= 9kΩ

Figure 25.5. Resistor voltage limits for a given power rating.

25.3.2 Maximum working voltage ∧

The maximum working voltage V , either dc or ac rms, is the limiting element voltage that may be continuously applied to a resistor without flashover, subject to the maximum power rating PR not being exceeded. A typical characteristic is shown in figure 25.5, which illustrates the allowable voltage bounds for a 10 W resistor range, having a limiting flashover voltage of 300 V rms. At lower resistance, power dissipation capability limits the allowable element voltage, and above a ∧ certain resistance level, termed critical resistance, Rc, the maximum working voltage, V , is the constraint. Maximum working voltage decreases with decreased air pressure, typically a 30 per cent reduction for low pressures. Resistive elements intended for high voltage and surge applications have the maximum working voltage more rigorously defined, and for different possible operating conditions. The following empirical expressions are valid for solid carbon ceramic resistors. It will be seen that the maximum working voltage is fundamentally a property of resistivity, not resistance.

Figure 25.6. Resistor time constant versus resistance and power rating.

Power Electronics

1155

Resistors

Chapter 25

Film resistors, with resistance above 1 kΩ, having a helical grove, tend to be dominated by interspiral capacitance effects at frequencies above 10 MHz, as seen in figure 25.3a. Non-inductive elements have low shunt capacitance, such as in the case of carbon composition, while wire-wound resistors can have microhenries of inductance. For example from figure 25.6, a 25 W, 47 Ω, wire-wound resistor may have 6 µH of inductance. Residual inductance increases with resistance and decreases with frequency. Solid resistive elements, like carbon ceramic, have minimal self-inductance. The method of circuit connection tends to dominate inductance values. Their dielectric constant, εr, is about 5, and depends on resistivity. Example 25.3: Coefficients of resistance for a solid carbon ceramic resistor Solid carbon ceramic rods of length 1 cm and area 0.25 cm2, are used as voltage sharing resistors across each series connected switching device. If the ceramic resistivity is 7500Ω-cm, using equations (25.8) and (25.9), determine i. the resistance at 25°C, with zero supporting voltage ii. resistance for a 50°C temperature increase iii. resistance for a 1000V 20ms voltage pulse iv. resistance at 50°C and 1000V for 20ms, simultaneously v. maximum working voltage at (a) 50Hz in air and in SF6 (b) 10µs/1000 µs impulse in air, a = 2128 and b = 0.031

• •

1156

Stability of resistance when subjected to a dc cyclic load. Typical power dissipation is limited to give 5 per cent resistance change for 2000 hours continuous operation in a 70°C ambient air temperature. Proximity of other heat sources and the flow of cooling air.

The temperature rise of a resistor due to power dissipation is determined by the laws of conduction, convection, and radiation (see Chapter 5). The maximum body external temperature, the hot spot temperature, occurs on the surface - at the middle of the resistor length. As previously considered, any temperature rise will cause a change in resistance, depending on a temperature coefficient; examples are given in table 25.1. Within the nominal operating temperature range of a resistor, the hot spot temperature, Th, is given by (similar to equation 5.10) (25.14) Th = Ta + Rθh−a Pd (K) The steady state power dissipation is related to temperature rise (°C or K) and the exposed surface area (m2). A solid carbon ceramic resistor yields an excellent model for the relationship between temperature and power since it has a homogeneous composition and uniform cross section. For example, heat loss (power dissipated) by radiation and convection in still 25°C air, is given by Pd = 2.6 × ( ∆T ) × Asurface 1.4

(W)

(25.15)

where ∆T = Th - Ta and Asurface is the exposed radiating surface.

Solution i. From equation (25.1), resistance is A 1cm R = ρ = 7500Ω-cm × = 30kΩ A 0.25cm 2 ii. Resistance for a 50°C temperature increase is given from equation (25.8) R75°C = R25°C (1 + α × ∆T )

(

)

= 30kΩ 1 + (1600 × e − log ρ /1.4 − 1350 ) × 10−6 × 50°C = 0.9375 × 30kΩ = 28.12kΩ

iii. Resistance for a 20ms 1000V pulse is given by equation (25.9) R = R0V (1 + φ × A × V ) 1000V,20ms

(

)

= 30kΩ 1 − ( 0.62 × ρ 0.22 ) × 10−2 × 1cm × 1000V = 0.9558 × 30kΩ = 28.67kΩ

iv. For both a 50°C temperature increase and a 1000V, 20ms pulse, assume independence and superposition hold, that is, from parts i, ii, and iii R75°C ,1000V = R25°C (1 + α × ∆T )(1 + φ × A × V )

(

) (

= 30kΩ × 1 + (1600 × e − log ρ / 1.4 − 1350 ) × 10−6 × 50°C × 1 − ( 0.62 × ρ 0.22 ) × 10−2 × 1cm × 1000V

)

= 30kΩ × 0.9375 × 0.9558 = 26.88kΩ

v. The maximum working voltage at 50Hz is given by equation (25.10), that is 0.335 0.335 ρ  7500Ω-cm  Vl = 1.00 ×   × A = 1.00 ×   × 1cm = 9.18 kV in SF6 gas t   10ms  0.3

0.3

ρ  7500Ω-cm  Vl = 0.87 ×   × A = 0.87 ×   × 1cm = 6.33 kV in air t   10ms  The maximum working voltage, in air, for a 10µs/1000µs impulse is given by equation (25.13) Vl = bR × −1 + 1 + a / R

(

(

)

)

= 0.031× 30kΩ × −1 + 1 + 2128 / 30kΩ = 13.7 kV

♣ 25.4

Thermal properties

The continuous power rating of a resistor, PR, is based on three factors: • Maximum surface temperature, in free air, over the usable ambient temperature range, typically from -55°C to well over 100°C.

(a)

Figure 25.7. Power resistor thermal properties: (a) power derating with increased temperature and (b) surface temperature increase with increased power dissipation.

The hot spot temperature is limited, thus as the ambient temperature, Ta, increases the allowable power dissipated decreases, as shown in figure 25.7a for four different elements. These curves show that: • No power can be dissipated when the ambient temperature reaches the hot spot temperature. • No derating is necessary below 70°C. • Some resistors, usually those with higher power ratings, can dissipate higher power at temperatures below 70°C. The typical linear derating for power and energy of an element in an ambient temperature Ta, can usually be expressed in the form

Power Electronics

1157

Tl - Ta (25.16) Tl - TT reference for temperature Ta greater than the reference temperature and P(Tl ) = 0. Figure 25.7b shows the resistor surface temperature rise above ambient, nominally 20°C, at different levels of power dissipation. The lead lengths can significantly affect the thermal dissipation properties of resistors and an increase in lead length P(Ta ) = PT reference ×

• •

decreases the end of the lead, or soldering spot temperature increases the body temperature.

These characteristics are shown for 5 W and 20 W ‘cemented’ wire-wound resistors in figure 25.8. Figure 25.8a shows how the soldering spot temperature is affected by lead length. Figure 25.8b, on the other hand, is based on the assumption that the soldering spot is represented by an infinite heatsink. Therefore the shorter the lead length, the lower the body temperature for a given power dissipation. It is important to limit the solder pad temperature in order to ensure the solder does not melt – a distinct possibility with continuously dissipating power resistors soldered on pcbs.

Chapter 25

Resistors

1158

Example 25.4: Derating of a resistor mounted on a heatsink What power can be dissipated by an aluminium-clad, wire-wound resistor, (specified in figure 25.9), rated nominally at 50 W, in an ambient of 120°C with a heatsink reduced to 300 cm2 and 1 mm thick? Solution The heatsink area has been reduced to 56 per cent, from 535 to 300 cm2, hence from figure 25.9 the power rating below 70°C is reduced from 50W to 37.5 W. From figure 25.7a, curve 4, at 120°C ambient, derating to 75 per cent of the relevant power rating is necessary. That is, 75 per cent of 37.5 W, 28.1 W, can be dissipated at an ambient of 120°C and with a heatsink area of 300 cm2.

♣

25.4.1 Resistors with heatsinking Aluminium clad resistors suitable for heatsink mounting, as shown in figure 25.1c, are derated with any decrease in the heatsink area from that at which the element is rated. Figure 25.9 shows the derating necessary for a range of heatsink-mounted resistors. For a given heatsink area, further derating is necessary as the ambient temperature increases. Figure 25.7a, curve 4, describes the ambient temperature related power derating of the aluminium-clad resistors on the rated heatsink, characterised in figure 25.9. Figure 25.7a, curve 4, can be used to derate these resistors when operating in an ambient other than 20°C, with the rated heatsink area shown in figure 25.9. The same percentage derating is applicable to a heatsink area smaller than the nominal area.

Figure 25.9. Power dissipation of resistors mounted on a smaller heat sink than specified, right.

Figure 25.8. Wire-wound 5 W and 20 W resistor dissipation as a function of: (a) lead length and temperature rise at the end of the lead (soldering spot) and (b) temperature rise of the resistor body, for two lead lengths.

Figure 25.10. Permissible short time overload ratings for heavy-duty tape wound power resistors.

Power Electronics

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Resistors

Chapter 25

1160

∧

25.4.2 Short time or overload ratings Resistors with power ratings greater than a watt are designed to handle short-term overloads, either continuously for minutes, or repetitively in short bursts of a few seconds. Figure 25.10 can be used to determine allowable short-duration, repetitive pulses. It can be seen that high, short-duration power pulses of a few seconds can be handled if the repetition rate is low. As the pulse duration increases, the overload capability reduces rapidly, with minimal overload allowable with power pulses over a few minutes in duration. For power pulses of less than 100 ms, the power is absorbed by the thermal capacity of the resistive element and little heat is lost to the surroundings. The temperature rise ∆T of the resistive element in this adiabatic condition is given by (equation 5.2) W ∆T = (K) (25.17) mc where c is the specific heat capacity of the resistive element (J/kg/K) W is the energy in the pulse of time tp, (J) m is the mass of the resistive element (kg). Due to its homogeneous composition, the carbon ceramic rod resistor yields a good model for the relationship for temperature rise (°C) in free air due to an energy injection pulse. Using the data in appendix 25.8: W W ∆T = = mc γ × volume × c (25.18) W W = = (K) 1.57 × 106 × D 2 × A  π D2  2250 ×  × A  × 8.89 × 103  4  where the effective mass is calculated from the density, γ, and the active volume (all SI units).

power. The allowable square power pulse P, of duration tp and repetition time T, can be determined from figure 25.11a, which is typical for power film resistors, at a 70°C ambient. Within these bounds, any resistance change will be within the limits allowable at the continuous power rating. The pulse duration ∧ tp, restricts the maximum allowable pulse voltage V , impressed across a film resistor, as shown in figure 25.11b.

Example 25.5: Non-repetitive pulse rating A 100 A rms, sine pulse with a period of 50 ms is conducted by a wire-wound resistor, constructed of 1 mm2 cross-section Ni-Cr alloy (Nichrome). Calculate the temperature rise. Assume for Ni-Cr resistivity ρ = 1 × 10-6 Ω m specific heat c = 500 J/kg/K density γ = 8000 kg/m3 Solution The mass m of the element of length ℓ and area A is given by m = γ AA (kg) Resistance R of the wire is given by A R=ρ (Ω) A The pulse energy is given by tp

W = ∫ i 2 R dt = ∫ o

= 500 R

50ms

o

(

)

2

2 × 100sin (ωt ) R dt

(J)

A (J) A The temperature rise ∆T from equation (25.17) is given by ρA 1 1 W ∆T = = 500 × × × mc A c γ AA W = 500 × ρ

500 ρ 500 × 1× 10−6 = γ cA2 8000 × 500 × (1× 10−6 )2

= 125K

♣ 25.5

Example 25.6: Pulsed power resistor design A 1 kΩ-10 nF, R-C snubber is used across a MOSFET which applies 340 V dc across a load at a switching frequency of 250 Hz. Determine the power resistor requirements.

Substitution for R yields

=

Figure 25.11. Pulsed capabilities of a power metal film resistor, 2.5 W: (a) maximum permissible peak pulse power versus pulse duration and (b) maximum permissible peak pulse voltage versus pulse duration.

Repetitive pulsed power resistor behaviour

A resistor may be used in an application where the power pulse experienced at a repetition rate of kilohertz is well beyond its power rating, yet the average power dissipated may be within the rated

Solution The average power dissipated (charging plus discharging) in the resistor, which is independent of resistance, is: P = CV 2 f = (10 × 10-9 ) × 3402 × 250Hz = 0.29 W Figure 25.11 is applicable∧ to a 2.5 W metal film resistor, when subjected to rectangular power pulses. The peak power P occurs at switching at the beginning of an R-C charging or discharging cycle. ∧

P = Vi 2 / R = (340V) 2 /1000Ω = 116 W where Vi, 340 V, is the maximum voltage experienced across the resistor. The 2.5W element has a power rating greater than the average to be dissipated, 0.29W. Assuming exponential pulses, then t p = ½τ = ½CR = ½ × 10 × 10-9 × 103 = 5µs

The average pulse repetition time, T, is 2 ms, therefore T / tp = 400. From Figure 25.11, the peak allowable power is 150 W while the limiting voltage is 500 V. Both the experienced voltage, 340 V, and power, 116 W, are within the allowable limits. The proposed 2.5 W, 1 kΩ, metal thin film power

Power Electronics

1161

resistor is suitable. Furthermore from figure 25.7, curves 2, with an average power dissipation of 0.29 W, that is 11.6 per cent of PR, the maximum allowable ambient temperature is 213°C, while the hot spot temperature is 40°C above ambient for an ambient below 70°C. In terms of average power dissipated, this resistive element is lightly stressed. On the other hand, the transient stress is relatively high.

♣ 25.5.1 Empirical pulse power model An empirical formula for the maximum pulse power may be given in the case of a metal film resistor. Typically, for a 1 W @ 70°C, 700 V rated, 60 K/W, metal film resistor ∧ 15 (W) P≤ (25.19) tp where 1 µs ≤ tp ≤ 100 ms, such that the average dissipation is less than the rated dissipation. Using tp = 5 µs from example 25.2 in equation (25.19) indicates that this 1 W resistor is suitable for the application considered in example 25.4. In fact a ⅓W, 600 V rated, metal film resistor can fulfil the ∧ snubber function when using a quoted P = 5 / t p . 25.5.2 Mathematical pulse power models A more rigorous mathematical approach to power dissipation is possible for carbon ceramic resistive elements because of the symmetrical shapes and homogeneous composition. The thermal time l to maximum rated constant in free air at 25°C is defined by the ratio of the maximum rated energy W l , that is power P l W τ= (25.20) l P The temperature rise for a single energy pulse is given by equation (25.17), that is W ∆T = (K) mc If the temperature coefficient of resistance is assumed constant, then the peak temperature rise ∆Tp for n repetitive pulses of energy W and of period t, is t   − t n   −  ∆T p = ∆ T ×   1 −  e τ   +  1 − e τ   (25.21)           where ∆T is the temperature rise associated with each electrical pulse. For continuous pulses, this equation asymptotes to t −    ∆Tp = ∆T 1 +  1 − e τ     

(25.22)

Example 25.7: Solid carbon ceramic resistor power rating The resistor in example 25.3 has a maximum power rating of 4W at 25°C and a maximum energy rating of 1200J at 25°C. The element is subject to 2½ms, 1J energy pulses at a 20ms repetition rate. Determine i. the thermal time constant ii. the maximum power and energy limits at 100°C, if the resistor is linearly derated to zero at 200°C, from its rating at 25°C. What is the new thermal time constant? iii. the temperature rise due to • one energy pulse • after 1 second of pulses • continuous pulses Solution i. The thermal time constant at 25°C is defined by equation (25.20) l W 1200J τ = 25°C = = 300 s l 25°C 4W P

Resistors

Chapter 25

1162

ii. The power derating is given by  200°C - T  P (T ) = P25°C ×    200°C - 25°C   200°C-100°C  P (100°C) = 4W ×   = 2.28W 175°C   Similarly, the energy derating is given by  200°C - T  W (T ) = W25°C ×    175°C   200°C-100°C  W (100°C) = 1200J ×   = 686J 175°C   The thermal time constant remains unchanged after the two linear transformations l 100°C W 686J τ= = = 300 s l 100°C 2.28W P

iii. The temperature rise due to one energy pulse (20ms repetition rate) is given by equation W W ∆T = = (K) mc 1.57 × 106 × D 2 × A 1J = = 2°C 4 1.57 × 106 × × 0.25 × 10−4 × 1× 10−2

π

From equation (25.21) after 1 second, that is 50 pulses t   − t n   −  ∆T p − 2 = ∆ T ×   1 −  e τ   +  1 − e τ             20ms     − 20ms 50   −  = 2°C ×   1 −  e 300s   +  1 − e 300s   = 2°C × [0.003328 + 0.0000666] = 0.0007°C        In steady state, from equation (25.21), the peak temperature rise is t −    ∆Tp = ∆T × 1 +  1 − e τ      20 ms −    = 2°C × 1 +  1 − e 300 s   = 2°C × [1+0.0000666] = 2.0°C    ♣

All resistors are thermally derated, starting at about 70°C, linearly to zero power dissipation at a maximum operating temperature, which is shown in Table 25.5 for the various resistor types. Table 25.2: Zero rated power for thermally derated resistor types

Wire wound - power alumina former/ power beryllia former / precision

Maximum temperature °C 275 / 350 / 175

Metal foil

125

Type

(derating usually starts at 70°C)

Metal foil – power / precision

170 / 175

Nickel film

150

Tantalum nitride film

150

Cermet thin film

200

Metal oxide film

125

Carbon film – power / precision

100 / 120

Metal glazed – power / precision

200 / 200

Thick film - metal oxide / metal oxide power

150 / 275

Conducting plastic – power / precision

120 / 120

Carbon composition / ceramic

130 / 220

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25.6

Resistors

Chapter 25

Stability and endurance

1164

Example 25.8: Power resistor stability

The resistance stability of a resistor is dependent on power dissipation, ambient temperature, and resistance value. An endurance test gives the worst-case variation in resistance value or stability. It is the percentage resistance change at rated power and hot spot temperature after a specified time. An endurance specification is of the form: • 1000 hours at recommended maximum dissipation PR, • which will limit the hot spot temperature to 375°C: • ∆R less than 5 per cent of R The time, percentage change in R, and temperature are varied with resistor type and physical size. At power levels below rated dissipation, better stability than that for the endurance test is attainable, for the same duration. The stability period can be extended by the following empirical formula log t ∆R ∆R t (25.23) ≈Χ 1× R t R t 1

which is valid for 10-3 ≤ t ≤ 105 hours. The base χ depends on the resistor type and is between 1.1 and 5. Performance monograms as shown in figure 25.12 may be provided to enable a given resistor to be used at dissipation levels which will result in the stability required for that application. The first quadrant in figure 25.12 satisfies the thermal equation (25.14), while the third quadrant satisfies equation (25.19), with χ = 3.17. The following example illustrates many of the features of the stability performance monogram of figure 25.12.

A 1 kΩ, 7 W, power metal oxide film resistor dissipates 5 W. If the maximum ambient is 100°C, use the monograph in figure 25.12 to find i. ii. iii. iv.

the stability at 100°C while in circuit for 1000 hours but in a standby mode, that is, P = 0 W the hot spot temperature when dissipating 5 W the maximum expected resistance drift after 103 and 105 hours lifetime (5% = ∆R/R) dissipating 5W in a 60°C ambient.

Solution i. The resistance change given from the monogram for P = 0W at a 100°C ambient is indicative of the shelf-life stability of the resistor when stored in an 100°C ambient. The stability is determined by performing the following operations. Find the intersection of P = 0 and the diagonal for Ta = 100°C. Then project perpendicularly to the 1 kΩ diagonal. The intersection is projected horizontally to the 1000 hour diagonal. This intersection is projected perpendicularly to the stability axis. For example, from projections on figure 25.12, after 1000 hours, in a 100°C ambient, a 0.25 per cent change is predicted. For the 1 kΩ resistor there is a 95 per cent probability that after 1000 hours the actual change will be less than 2.5 Ω (0.25% of 1kΩ). ii. The 5 W load line is shown in figure 25.12. A hot spot temperature, Tm, of 150°C is predicted (100°C + 5 W × 10°C/W). iii. With a 1 kΩ resistor after 1000 hours, a ∆R/R of 0.57 per cent is predicted, as shown on figure 25.12. There is a 95 % probability that the actual change will be less than 5.7Ω. The monogram does not show stability lines beyond 10,000 hours. Equation (25.23), with χ=3.17, can be used to predict stability at 100,000 hours 105

log ∆R ≈ 3.17 103 × 0.57% = 18.25% R 105 After 100,000 hours, it is 95 per cent probable that the actual resistance change of the 1 kΩ resistor will be less than 182.5 Ω (18¼% of 1kΩ).

iv. from the first quadrant in figure 25.12, the hot spot temperature is 110°C when dissipating 5W in a 60°C ambient. Solving equation (25.23) for 5% = ∆R/R = 5%: x

log10 ∆R = 3.17 103 × 0.05 R 10 x gives x = 5. That is, there is a 95% probability that the resistor will survive 105 hours with a resistance variation of less that 5%.

ii

♣ 25.7 i

ii

i

ii

Special function power resistors

Film and wire-wound resistors are available which have properties allowing them to perform the following functions • fusing • circuit breaking • temperature sensing • current sensing. Table 25.3: Fusible resistor characteristics parameter

ii

i

Power

PR

Resistance range

R

Tolerance Temperature coefficient (resistance dependent)

α

Stability Figure 25.12. Performance monogram for power resistors, showing the relationship between power dissipation, ambient temperature, hot spot temperature, and maximum resistance drift in time.

Working voltage

Vm

condition @ 70°C

units W Ω

Metal alloy film

Wire wound

0.25 - 4.5

1-2

0.22 - 10k

0.1 - 1k

%

2

5

x 10-6

/K

± 500

-400 to + 1000

@ PR Ta = 70°C, 1000 hours

%

2

10

V

PR R

PR R

Power Electronics

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Chapter 25

Resistors

1166

25.7.1 Fusible resistors Resistors up to 2 W are available which fuse when subjected to an overload current. The resistive element fused is generally metal alloy film, although only wire-wound elements are suitable at low resistance levels. The power load and interruption time characteristic shown in figure 25.13a shows that rated power can be dissipated indefinitely, while as the power increases significantly above the rated dissipation, the interruption time decreases rapidly. Interruption generally means that the nominal resistance has increased at least 10 times. Irreversible resistance changes can be caused by overloads which raise the change in hot spot temperature beyond 150°C, for the elements illustrated by figure 25.13b. The nature of the resistive element makes it unsuitable for repetitive power pulse applications. Typical fusible resistors are summarised in table 25.3.

Figure 25.14. Two circuit breaker resistors construction: (a) type 1 and (b) type 2.

Figure 25.13. Fusible resistor characteristics: (a) time to interruption (10 x RR as a function of overload power and (b) temperature rise above ambient as a function of power dissipated.

Figure 25.15. Circuit breaker characteristics: (a) solder joint temperature rise versus power dissipated for resistor type 2 and (b) fusing times versus load for resistor types 1 and 2.

25.7.2 Circuit breaker resistors

25.7.3 Temperature sensing resistors

The construction of two types of wire-wound circuit breaker resistors is shown in figure 25.14. Under overload conditions the solder joint melts, producing an open circuit. After fusing, the solder joint can be resoldered with lead free solder. The joint melts at a specified temperature, and to ensure reliable operation the solder joint should not normally exceed 150°C. This allowable temperature rise is shown in figure 25.15a, while the circuit breaking time and load characteristics for both constructions are shown in figure 25.15b. This characteristic is similar to that of fusible resistors. A typical power range is 1 to 6 W at 70°C, with a resistance range of 75 mΩ to 82 kΩ and temperature coefficient of -80 to +500 × 10-6/K depending on the resistance values. The maximum continuous rms working voltage tends to be limited by the power, PR, according to PR R .

The temperature dependence of a resistive element can be exploited to measure temperature indirectly. Unlike normal resistors, temperature-sensing resistors require a large temperature coefficient to increase resistance variation sensitivity with temperature. Both metal film and wire-wound temperature sensing elements are available with a temperature coefficient of over +5000 × 10-6/K with 1 per cent linearity over the typical operating range of -55°C to 175°C. The high temperature sensitivity gives a 57 per cent increase in resistance between 25°C and 125°C. The low power elements, up to ¼W @ 70°C, tend to be metal oxide, with a typical resistance range at 25°C of 10 Ω to 10 kΩ. A conformal encapsulation is used to minimise thermal resistance, hence ensuring an extremely fast response. For example, a 1/20 W temperature sensing resistor can have a thermal time constant to a step temperature, in still air, of 3.7 s. This time constant increases to 31 s for a larger mass, ¼ W rated resistor.

Power Electronics

1167

Resistors

Chapter 25

At powers commencing at 1 W, wire-wound elements are employed which utilise positive temperature coefficient alloy resistance wire. The nominal resistance range is lower than the film types; typically from 0.1 Ω to 300 Ω at 25°C. Response is slower than film types, but can be improved if oil immersed. Glazed thick film temperature sensing resistors can be used to provide a negative temperature coefficient, -3000 × 10-6/K at 25°C. Power is limited to ¼ W with a dissipation constant of up to 8.1 mW/K at 25°C in still air. Low thermal time constants of only 2.9 s are possible with 1/20 W elements.

1168

Another type of thermistor is a Silistor - a thermally sensitive silicon resistor. Silistors are similarly constructed and operate on the same principles as other thermistors, but employ silicon as the semiconductive component material. Over small changes in temperature, if the right semiconductor is used, the resistance of the material is linearly proportional to the temperature. There are many different semiconducting thermistors with a range from 0.01 degree Kelvin to 2,000 K; -273.14°C to 1,700°C). The NTC thermistor is best suited for precision temperature measurement. The PTC thermistor is best suited for temperature compensation and current limiting, as considered, in detail, in chapter 10.3.2.

The allowable working voltage for all types is power limited, V=√PRR.

Negative temperature coefficient (NTC) thermistors

25.7.4 Current sense resistors The resistive element consists of a flat metal band, with spot-welded terminals, and a ceramic encapsulation. The flat-band construction results in a non-inductive resistor of both high stability and overload capacity. Low current third and fourth terminal voltage sensing (Kelvin) leads may be incorporated; alternatively a mΩ/cm correction factor for lead length is given. Power ratings of up to 20 W at 70°C and 20 A maximum, with a resistance range of 10 mΩ to 10 Ω are available. At these low resistance levels, the maximum continuous working voltage is power limited. The resistance temperature coefficient is typical of a wire-wound resistor, 100 to 600 × 10-6/K depending on the resistance level.

In practice, the linear approximation in equation (25.24) is only applicable over a small temperature range. For accurate temperature measurements, the resistance/temperature curve of the device is be described in more detail using the Steinhart-Hart third-order approximation equation: 1 = a + b ln R + c ln3 R

T

where a, b and c are called the Steinhart-Hart parameters, and must be specified for each device. T is the temperature in degree Kelvin and R is the resistance in Ohms. To give resistance as a function of temperature, the above equation can be rearranged into:

25.7.5 Thermistors

1

1

R = e ( β −½α )3 − ( β +½α )3

A thermistor is a type of resistor with resistance varying predictably and rapidly according to its temperature. The word is a portmanteau of thermal and resistor. Thermistors are widely used as inrush current limiters, temperature sensors, self-resetting overcurrent protectors, and self-regulating heating elements. The resistance of a thermistor is solely a function of its absolute body temperature. When testing for resistance accuracy it is essential that the surrounding environmental temperature is held at a constant, and power dissipated in the thermistor is low enough to insure no ‘self-heating’. With transition metals, the relationship between resistance and temperature is linear, first-order, that is: ∆R = k ∆ T

where

α=

NTC thermistors are made from chemically stabilised metallic oxides (such as manganese, iron, cobalt, nickel, copper and zinc), compressed and sintered at high temperatures between 1000°C and 1400°C to produce the polycrystalline NTC thermistor, which at a finally stage of manufacture is aged for stability. Most PTC thermistors are of the ‘switching’ type, which means that their resistance rises suddenly at a certain critical temperature. The devices are made of a doped polycrystalline ceramic containing barium titanate (BaTiO3) and other compounds. The dielectric constant of this ferroelectric material varies with temperature. Below the Curie point temperature, the high dielectric constant prevents the formation of potential barriers between the crystal grains, leading to a low resistance. In this region the device has a small negative temperature coefficient. At the Curie point temperature, the dielectric constant drops sufficiently to allow the formation of potential barriers at the grain boundaries, and the resistance increases sharply. At even higher temperatures, the material reverts to NTC behaviour. Another type of PTC thermistor is the polymer PTC. This consists of a slice of plastic with carbon grains embedded in it. When the plastic is cool, the carbon grains are all in contact with each other, forming a conductive path through the device. When the plastic heats up, it expands, forcing the carbon grains apart, and causing the resistance of the device to rise rapidly. Like the BaTiO3 thermistor, this device has a highly nonlinear resistance/temperature response and is used for switching, not for proportional temperature measurement.

3

½

b = 2.37 × 10−3

(25.24)

If k is positive, the resistance increases with increasing temperature, and the metal is termed a positive temperature coefficient (PTC) material. If k is negative, as with some sintered compounds, the resistance decreases with increasing temperature, and the compound is termed a negative temperature coefficient (NTC) material. Thermistors can be classified into two types depending on the sign of k, namely NTC and PTC thermistors. Resistors that are not thermistors are designed to have a k as close to zero as possible, so that their resistance remains near constant over a wide temperature range.

1

T and β =   b  + ¼α 2    3c   c

   The error in the Steinhart-Hart equation is generally less than 0.02°C in the measurement of temperature. As an example, typical values for a thermistor with a resistance of 3kΩ at room temperature (25°C = 298.15 K) are: a = 1.40 × 10−3

where: ∆R = change in resistance ∆T = change in temperature k = first-order temperature coefficient of resistance

a−

c = 9.90 × 10−8 Temperature coefficients valid over a small temperature range. i. NTC thermistors can also be characterised with the B parameter equation, which is essentially the Steinhart Hart equation with c=0. −1       1 1 1 R  or T =  1 ln  R  + 1  = + ln (K )    T T o B Ro B  Ro  T o       where the temperatures are in degree Kelvin. Rearranging yields: 1

R = Ro e

1  −  T To 

B 

(25.25)

Ro and To are rated temperature and resistance at that temperature (usually 25°C=298.15K), or

B =

T To T To R R ln = × 2.3026 × log10 T o − T Ro T o − T Ro

The B-parameter equation can also be arranged in the form y = mx + c by taking natural logs of both sides of the equation to give ℓnR = Bx + 1 / T. This can be used to convert the function of resistance against temperature of a thermistor, into a linear function of which the gradient can be found to give the B value (typically 2500K to 5000K. A quadratic approximation for B can be highly accurate, where B = a + bT + cT 2 The quadratic coefficients are device material dependant, typically 2000 < a < 4000, 1 < b < 8, and 0.0001 < c ≈ 1 ) materials are not considered. Two basic types of soft magnetic materials are common, depending on the application requirements. These materials are: •

L s = L1 + L 2 + L 3 + ...

Inductors and Transformers

•

Ferromagnetic materials based on iron and nickel, which are for lower frequencies, < 2kHz, while Ferrimagnetic materials (a subgroup of ferromagnetic materials), which are based on ceramic oxides of metals (ferrites), are applicable to frequencies from a few kilohertz to well over 80 MHz.

26.2.1 Ferromagnetic materials 26.1.2 Transformers or magnetically coupled circuits

26.2.1i - Steel

The ideal transformer shown in figure 26.1, with a primary and a secondary winding, in the turns ratio 1:ηT, is wound so as to produce the shown voltages according to the usual flux dot convention. Any two of the following electrical equations can be used to derive the third equation.

Pin = Pout I p × 1 = I s × ηT

(26.11)

Vs ηT = Vp 1 Impedance in one winding can be referred (transferred) to the other winding in the turns ratio – squared. Series impedance Zs in the secondary becomes Z p =

Z s = R + j ωL −

Zs

in the primary circuit. Specifically

ηT R L 1 becomes Z p = 2 + j ω 2 − ηT ηT j ωηT2C

1

j ωC

2

(26.12)

Note that secondary resistance and inductance referred to the primary are divided by the turns ratio squared, while capacitance is multiplied by ηT2 . For mutually coupled circuits (transformers), the relationships between the primary and secondary electrical parameters are

di p di ±M s dt dt di p di s ±M v s = Ls dt dt v p = Lp

(26.13)

where Ls and Lp are the primary and secondary self inductances given by any of equations (26.4) to (26.6).

∆φ for a coupling factor k (0 ≤ k ≤ 1). M is the mutual inductance, M = k Lp Ls = k N s ∆i p The stored magnetic energy in the core with current in the primary and secondary is

W = ½Lp i p2 ± Mi p i s + ½Ls i s2 =½

(

Lp i p ± Ls i s

(26.14)

)

In equation (26.14), it is required for a transformer, that no energy is stored in the core whence the negative sign is applicable and for energy W = 0, 1×ip = ηT×is. Faraday’s Law, equation (26.2), is applicable to transformers. In the case of a transformer, this equation shows that the advantage of a high core flux density is that more volts v, per turn N, for a given frequency f, results. When the primary and secondary coupled coils are series connected

Lseries = (Lp ± M ) + (Ls ± M ) = Lp + Ls ± 2M

=

(N

p

+ Ns )

2

ℜ

(26.15)

When the primary and secondary coils are parallel connected

Lparallel =

1

Lp ± M

+

1

Ls ± M

=

Lp × Ls Lp + Ls ± 2M

(26.16)

Note the extra mutual coupling terms, when compared to equation (26.10) for the uncoupled cases. Figure 26.1 shows how the coupled circuit model of the ideal transformer, is extended to give the usual transformer model, which includes copper winding resistance RCu, leakage inductance Lℓ, magnetising inductance Lm, and core losses (eddy current and hysteresis) Rcore.

Cold-rolled grain-oriented steel is a 3-4 per cent silicon iron, cold reduced to develop a high degree of grain orientation, which gives • increased flux for a given magnetising force and • decreased size for a given rating, hence reduced weight. Normally cores are produced in a number of material lamination thicknesses • 0.3 mm for frequencies up to 200 Hz • 0.1 mm for frequencies between 200 Hz to 2 kHz and • 0.05 mm for higher frequencies and pulse applications. Steel laminations for low frequency applications are available in different shapes. E and I laminations or strip C cores or toroids are extensively used for mains transformers and ac line inductors. Nonorientated silicon steels are extensively used for machine laminations. 26.2.1ii - Iron powders Two general forms of iron powder cores are employed • •

Cores are made by highly compacting insulated high quality spongy iron powder. High resistivity is required to reduce eddy current losses, so the iron powder is subjected to an acid treatment to produce an insulating oxide layer on the surface of each individual particle. This fine carbonyl iron is mixed with a bonding material and highly compressed. The bonding material used limits the maximum core temperature. Minute gaps appear between the particles, severely reducing the permeability. It is difficult to saturate such materials.

26.2.1iii - Alloy powders These cores are made by highly compacting insulated alloy powder. The alloy is usually 50-75 per cent nickel, the remainder being iron with a small percentage of copper and molybdenum. The higher the iron percentage, the higher the saturation flux density and the higher the core losses. Powder iron and alloy cores are available in toroidal or ring shapes, cylindrical and hollow cylindrical cores, as well as cup cores, bobbins, pot cores, and beads. 26.2.1iv - Nanocrystalline Nanocrystalline soft magnetic alloys are brittle, thin ribbon, 18µm, materials based on iron Fe, silicon Si and boron B with small additions of niobium Nb and copper Cu. They are produced via a rapid solidification technique, being initially in a precursor amorphous (non-crystalline) state and then crystallized into a precise mix of amorphous and nanocrystalline phases when subsequently heat annealed at around 500 to 600°C. An amorphous magnetic metal has high permeability due to no crystalline magnetic anisotropy. However when applying heat treatment on a typical amorphous metal at temperatures higher than its crystalline temperature, magnetic properties deteriorate for a rapid crystal growth of grains up to 1um. But if the recrystalline grains are restricted to the nano-order, about 10 nm in size, the soft magnetic crystal grains have good magnetic properties. Thus the suppressed grain growth recrystalization during annealing due to the enriching Nb and Cu gives the material it's unique magnetic properties. This extremely finegrained microstructure with grain sizes of 10 nanometres is termed nanocrystalline. Nanocrystalline alloys combine low magnetic anisotropy and low magnetostriction, both prerequisites for high magnetic permeability, with high magnetic flux density Bs and good thermal stability. Due to the exchange coupling of randomly oriented grains of Fe, the magnetocrystalline anisotropy averages out to zero. Magnetostriction can also be cancelled by a combination of positive values for the crystalline phase and negative values for the remaining amorphous phase, resulting in zero magnetostriction.

Power Electronics

1179

Chapter 26

Figure 26.2a shows permeability and saturation magnetic flux densities of representative nanocrystalline soft magnetic materials. Since the compositions of nonmagnetic elements can be reduced in the alloy design, higher saturation magnetic flux density can be obtained in the nanocrystalline soft magnetic materials compared to the existing bulk soft magnetic and amorphous materials.

Comparison of material types

Table 26.1 shows typical comparative data for the main classes of soft ferro and ferri magnetic materials. Generally, those materials with higher saturating flux densities, Bs, have higher initial permeability µi, and hence offer higher inductance but at the expense of higher core eddy current and hysteresis losses.

½ 10

1½

2 10

Permalloy

6

Nanocrystalline µi = 70,000

Nanocrystalline

µr

Co-based amorphous

Fe-Si 10

5

Fe-M-B

10

5

10

4

Fe, Co-M-B Fe-Al-Si 10

grains >1µm

4

Si-steel

10

Fe-based amorphous

Mn-Zn ferrite

3

0

½

Fe-Co alloy

1

Flux density

Table 26.1: Typical comparative data of soft magnetic materials Material

1

6

1kHz

relative permeability

26.3

1180

In rfi suppression and filtering applications, silicon steel is not effective since the initial permeability, µi, falls rapidly with frequency hence at the high suppression frequency, inductance is small. Thus iron powder or a high iron alloy may be used, which have relatively high flux densities and high losses. For rfi suppression, a high core loss aids suppression. At inaudible frequencies, >20 kHz, for a low core loss, ferrites are extensively used. Although ferrite flux densities are relatively low, typically 0.5 T for power application ferrites, eddy current and hysteresis losses are low. The low eddy current loss results from the high core material resistivity. With ferromagnetic materials, the eddy current loss is reduced by using thinner laminations or electrically isolated powder particles. A major disadvantage of a ferrite core is its poor temperature stability and low allowable core temperature. On the other hand, high initial permeabilities, >20,000, are obtainable. Ferrite materials, application, and component design are specifically considered, although the concepts developed are generally applicable to ferromagnetic materials.

26.2.2 Ferrimagnetic materials - soft ferrites Ferrites are grey/black, hard, brittle, chemically inert ceramic materials, which have a magnetic cubic (spinel) structure. The most general ferrites are polycrystalline magnetic isotropic (grains non-aligned) ceramic oxides, which are compounds of iron oxide, Fe203, about 50%, mixed with one or more oxides of bivalent transition metals such as Fe0, Ni0, Zn0, Mn0, Cu0, Ba0, Co0, and Mg0, to give the general compositional form MeFe204. At lower frequencies, below a few MHz, a Mn-Zn combination is added to iron oxide, while for higher frequencies, above a MHz, Ni-Zn is the additive. The raw pure oxide materials are mixed with organic binders, pre-sintered at 1000°C, a process called Calcining and then the partially formed ferrite structure pellets are wet ground by milling, to form a submicron particle slurry with water. After spray drying, the powder material is shaped by means of pressing and sintering at between 1150°C and 1300°C, which cause densification and substantial shrinkage. The sintering process involves raising the temperature to 1300°C in about 3 h, with 15 per cent oxygen present. The cores are cooled slowly without oxygen present to about 200°C in 20 h after entry. In producing the ferrite crystal structure, a 15 per cent linear, and 40 per cent by volume shrinkage occurs during sintering. A diverse range of ferrite core shapes is available, which include, E, I, U, toroid, drum, pot, rod, tube, and screw. Where appropriate, diamond-wheel-ground air gaps are available on the centre pole. Manufacturing yields limit the physical component in size. Toroid cores of 152 mm outside diameter are not uncommon, and exotic shapes such as motor stators are made for special applications.


1½ Bs

2 (T)

(a)

Bs

Br/Bs

Hc

µm

T

%

A/m

Hm=800A/m

Hm=800A/m

25°C

25°C

18

1.23

89

0.6

30

5

600

0

570

18

1.23

5

0.6

50

16

250

0

570

25

1.56

83

2.4

5

5

2200

+27

415

20

0.55

5

0.3

115

18

280

0

180

20

0.60

85

0.3

30

10

460

0

210

symbol

definition

units

3% Si steel

50

1.9

85

6.0

2.7

0.8

8400

-0.8

750

form factor, ℓe /Ae

c1

Σℓ/A

m

6½% Si steel

50

1.3

63

45

1.2

0.8

5800

-0.1

700

effective magnetic area

Ae

c1 / Σℓ/A

m

Effective magnetic length

le

Ae c1

m

effective magnetic volume

Ve

ℓe Ae

m

core permeance

c

µo /c1

H

Nanocrystalline Square Fe-Si Nanocrystalline hi-µr Fe-Si Fe based amorphous Co-based hi-µr amorphous Co-based square amorphous

50% Ni Permalloy 80% Ni hi-µr Permalloy 80% Ni square Permalloy Mn-Zn hi-µr ferrite Mn-Zn low-loss ferrite

Hm=800A/m

µr 3 ×10 1kHz Hm=0.5A/m

µr 3 ×10 100kHz Hm=0.5A/m

Pcv

λs

kW/m3

10

100kHz

25°C

25°C

25°C

25°C

-6

Tc

(b)

thickness

Figure 26.2. Magnetic alloy characteristics: (a) permeability versus saturation magnetic flux densities and (b) B-H characteristics.

°C

Bm=0.2T

26.4

25

1.5

95

12

-

-

3400

+25

500

25

0.74

55

0.5

50

5

1000

0

480

25

0.74

80

2.4

-

-

1200

0

460

-

0.44

23

8.0

5.3

5.3

1200

-0.6

150

-

0.49

29

12

2.4

2.4

680

-0.6

220

Ferrite characteristics

The definitions and explanations given are applicable to soft magnetic materials in general and are illustrated specifically by reference to ferrite materials. General mechanical and thermal properties of power ferrites are given in Appendix 26.8, while typical magnetic properties are given in Appendix 26.9. Table 26.2: Core effective magnetic dimensions and parameters core factor

2

-1 2

3

26.4.1 Dimensions and parameters The effective magnetic dimensions are constant for a given core and are defined in table 26.2. These effective constants are based on the length ℓ and area A of the individual limbs comprising the complete

Power Electronics

1181

Chapter 26

core. These effective dimensions are used for magnetic component design, such as transformer core loss, which is given per unit effective volume, Ve. From the parameters in table 26.2, inductance is calculated from equation (26.6) as L = µi cN 2 (H) (26.17) 26.4.2 Permeability Figure 26.2 shows that a non-linear relationship exists between B and H for magnetic materials, and is characterised by the dimensionless parameter µr - the relative permeability - according to B = µo µr H (where µo = 4π×10-7 H/m). Figure 26.3 shows a detailed B-H magnetising curve for a ferrite material along with its hysteresis loop. The case of an air core magnetic circuit, for which µr = 1, is also shown. Figure 26.3 illustrates various definitions for µr based on the ratio flux density to field strength, namely 1 B µr = (26.18) µo H


26.4.2iii - Reversible or incremental permeability, µrev, µ∆ When a core is magnetised with a polarising dc offset field upon which a small ac field is superimposed, the ac H field produces a small lancet-shape hysteresis loop which reduces to a straight line as the ac H field is reduced. The slope of this line, shown in figure 26.3, is called the incremental or reversible permeability 1 lim  ∆B  µ∆ = (26.21) µ ∆H → 0  ∆H  o

H = constant

The incremental permeability, µ∆ is a function of the dc magnetic bias, as shown in figure 26.5. It is usually a maximum when no dc field is present, while for a toroid it is identical with the initial permeability, µi. With increased current, µ∆, hence inductance, decreases.

µ∆µ

µ

0.1

µaµ

20

µ

J = B - µoH when the polarisation J >> µoH B ≈ µoH

µ

µ Figure 26.3. Hysteresis loop illustrating permeability definitions, remanence Br, and coercive force Hc. Figure 26.4. Temperature dependence of flux density B and amplitude permeability, µa.

26.4.2i - Initial or intrinsic permeability, µi The initial permeability, which is dependant on temperature and frequency, is the permeability at weak field strengths at H = 0 and ∆H tends to zero, that is  1 ∆B  µi =  (26.19)   µo ∆H  H = 0, ∆H → 0 ∧

26.4.2ii - Amplitude permeability, µa and maximum permeability, µ The amplitude permeability applies to large magnitude sinusoids (high excitation), with no dc field (offset) applied, and is the ratio of the sinusoid peak B and H  1 B µa =  (26.20)   µo H  H = 0 ∧ ∧ The maximum permeability µ is the maximum µa obtainable for any H, that is, µ = max [µa] for all values of H. The variation of amplitude permeability with magnetising force or flux density is shown in figure 26.4. Because of the non-linear nature of the B-H curve loop, the amplitude permeability is highly dependant of the applied field strength magnitude. The figure 26.4 is representative of a ferrite material suitable for a wide range of power electronic applications. More technical data for this material is presented in Appendix 26.9 and in the figures that follow.

1182

Figure 26.5. Variation of permeability with field strength.

Power Electronics

1183

Chapter 26

26.4.2iv - Effective permeability, µe


1184

Since the parallel and series circuits are equivalent

The inductance of a coil with a (air) gapped core of effective (or apparent) permeability µe is given by µ µ N2 L= o e = µe cN 2 = AL N 2 = µe Lo (H) (26.22) ∑ A hence L L 1 L µe = 2 = = (26.23) ∑ A cN Lo µo N 2 where Lo is the coil inductance if the core is removed (air, µr =1), whence the permeability drops. The term AL is the inductance factor and is equal to µe c. Conversely N =α L (26.24) where α = 1/√ AL and is termed the turns factor. If the air gap width, ε, is small compared with the core of effective length, ℓe, such that ε 2δ thick. A similar effect occurs within conductors carrying ac current, where the current is minimal at the conductor centre. The current density, J, is given by -x

J ( x) = J (0) e δ (A/m3 ) (26.51) Below 20-50 kHz and above a few megahertz, solid wire is preferred. In between these frequencies, individually insulated stranded wire, Litz wire (after Litzendraht) is preferred; decreasing from 0.07 mm to 0.03 mm in strand diameter as the frequency increases and interwinding capacitance dominates. Copper foil can also be employed.

Figure 26.8. Total per unit volume core losses as a function of: (a) core temperature, T; (b) maximum flux density, B ; and (c) frequency, f. µ20

2 - Nanocrystalline alloys The magnetic reversal loss characteristics of nanocrystalline material is similar to that of ferrite, but with lower losses and higher allowable flux swings. Based on equation (26.43), core losses are approximated by (26.46) Pv = 3.09 × ∆B 1.5 × f 1.5 (mW/cm3 ) Since the density is 7.35 g/cc, that is 1W/kg=7.35mW/cm3 Pv = 0.42 × ∆B 1.5 × f 1.5 ( W/kg)

10% of µ20

(26.47)

These empirical formula, shown in figure 26.8c and 28.23a, are valid for flux swings of up to ∆B = 2T and f ≤ 200kHz, at 25°C. 3 - Laminated silicon steel Hysteresis and eddy current losses for silicon steel can be calculated by using well established, classical empirical formulae.

Figure 26.9. Permeability, µi, and maximum density, B , as a function of core temperature, T.

26.4.5 Temperature effects on core characteristics

(a) Hysteresis loss Steinmetz equation predicts hysteresis loss according to n

Ph = λh B f Ve (W) where λh and n are characteristics of the core material: n = 1.7 λh = 500 for 4 per cent silicon steel = 3000 for cast iron

(26.48)

Generally ferrites have poor characteristic temperature stability. At higher temperatures, at the Curie point, core materials lose their ferromagnetic magnetic properties abruptly and become paramagnetic (µe ≈ 1). The temperature causes disruption of the magnet ordering in the crystalline lattice due to molecular thermal motion. The phenomenon is reversible and below the Curie temperature, Tc, the material becomes magnetic again. Typical magnetic material Curie temperatures are:

Power Electronics

1189

Chapter 26


1190

Table 26.3: Factors affecting the disaccommodation factor for ferrites

Fe

770°C

Co

1130°C

Ni

358°C

Nd2Fe14B

(N54)

ρ(Ω cm) µi

120°C

Ferrite Mn-Zn

180°C

Nanocrystalline Fe-Si

570°C

df

The temperature effect on initial permeability in figure 26.9 illustrates the sudden loss of permeability at 212°C, whence the permeability falls to 1, to that of air. The Curie temperature is usually defined as that temperature where the initial permeability falls to 10% of that permeability at 20°C. Generally, Curie temperature is inversely proportional to the initial permeability, µi. For most ferrites the initial permeability increases with temperature, and reaches a maximum just below the Curie temperature, as shown in figure 26.9. Other ferrite parameters are also affected by temperature. Increased temperature decreases flux density and hysteresis loss as shown in figures 26.4 and 26.9. The effects of temperature on total core loss per unit volume are shown in figure 26.8a. 26.4.6 Inductance stability Three factors affect inductance core stability: • Parameter effects • Time effects • Temperature effects 26.4.6i - Parameter effects From the differential of equation (26.22) dL d µe = µe L while differentiating equation (26.26) yields d µ e d µi = 2 2

µe

µi

(26.52)

(26.53)

Substituting equation (26.53) into equation (26.52) gives dL L1 − L2 d µi AL = = 2 (26.54) L L1 µi c 2 The factor d µi / µi is constant for a given temperature, hence any change in inductance is due to variations in AL and c. Thus in order to increase the stability of an inductor in a given material with ε t1 L L1 t1 The disaccommodation factor is defined by

df =

µ2 − µ1 µ22

°C

Tc

(26.56)

with units of ppm (/10-6). This expression is based on the fact that permeability is proportional to the logarithm of time. The df increases slightly with temperature. Generally the df decreases, as shown in table 26.3: • as the initial permeability increases for a given resistivity • as resistivity decreases. The effective disaccommodation factor dfe=df×µe is the actual disaccommodation of a magnetic circuit where material permeability has been reduced to µe by gapping.

× 10-6

105

500

≈ 20

11-250

800-2000

4000

450-300

250-170

145

50-10

20-2

3

Example 26.1: Inductance variation with time A pot ferrite core with an effective permeability of 100 (AL = 250) and a disaccommodation factor df < 35 x 10-6 has been in satisfactory operation for five weeks after production. What is the expected inductance variation after 10 years? Solution From equation (26.55) dL t 520 weeks = df µe log10 2 < 35 × 10−6 × 100 × log L t1 5 weeks that is, dL < 0.7 per cent can be expected. ♣

26.3.6iii - Temperature effects Figure 26.9 shows that between +5°C and +55°C the permeability µi variation as a function of temperature is approximately linear for this ferrite. The temperature coefficient of permeability α (or TC) is given by 1 µ i 2 − µ i1 1 ∆µ i = TC = α = (26.57) (K -1 ) µi1 T2 − T1 µ i 1 ∆T where ∆µi = µi2 - µi1 is the initial permeability variation over the temperature range ∆T =T2 - T1. The relative temperature factor tf is defined in terms of the temperature coefficient and intrinsic permeability by

α F = temperature factor = tf =

α 1 ∆µi = µi 1 µ i2 ∆T

(K -1 )

(26.58)

1

If the permeability variation is large, the temperature factor is modified to

αF = temperature factor = tf =

1 ∆µi µi 1 µi 2 ∆T

=

relative temperature coefficient

∆T

(K -1 )

(26.59)

In a magnetic circuit with an air gap and effective permeability, µe, the actual effective temperature coefficient of the core is reduced with gapping according to (see equation (26.42))

µ α e = α µe = α F µe = tf × µe i

(K -1 )

(26.60)

The term αF = αi /µi is called the relative temperature coefficient (per unit of permeability). The relative inductance change between two temperatures can be determined by µ − µi 2 dL L2 − L1 (26.61) = = α F µ e ∆T = i 1 × µe L L1 µi 1 µ i 2 For effective permeability µe < 80, (that is, a less dominant air gap), the temperature coefficient αe = µeαF should be increased by 10 to 30 × 106/K to account for the temperature influence of the winding. Example 26.2: Temperature effect on inductance The gapped pot core in example 26.1 is specified by a relative temperature coefficient of 1 x 106/K. What is the expected inductance variation over the temperature range 25 to 55°C? Solution From example 26.1 AL 250 = = 100 c 2.5 ∆T = 55 − 25 = 30°C

µe =

Power Electronics

1191

Chapter 26

From equation (26.61) dL = α F µe ∆T L = 1× 10−6 × 100 × 30 = 0.3 per cent inductance variation ♣


1192

Φ =BA

slope µoAe/ℓe

(Wb)

=Lo/N2

ε=0

Whilst permeability decreasing with aging for ferrite, and significantly so for Cobalt based amorphous metals, nanocrystalline and non-alloyed metals are comparatively stable. a

BAe

26.4.7 Stored energy in inductors

ε increasing →

b

c

The energy stored in the magnetic field in the core (before saturation) is given by ∨

E = ½ BH Ve

(J)

(26.62)

increasing air gap ε decreasing inductance L

energy

∨

where Ve is the effective minimum core volume. It can be shown that before saturation, the stored magnetic energy is equivalent to the stored electrical energy, whence

slope =

∨

E = ½ BH Ve = ½ Li 2 (J) (26.63) For un-gapped cores, like a toroid, the ferrite effective volume, Ve, is equal to the minimum effective ∨ volume, Ve . Inductors meeting this requirement may necessitate an excessive core size. However the introduction of an air gap, ε, can reduce the core size significantly, since a significant amount of the energy can be stored in the gap volume. The minimum effective volume is now larger than the ferrite core effective volume, and is given by = Ae ( le + µi ε )

(m 3 )

2

Lo Air

ε Hε o

(26.64)

Figure 26.10 shows modified B-H characteristics (no hysteresis) for air gap inductors. The line curve o-b represents the core without an air gap, which results in the largest inductance. The energy stored in the core for a flux BAe, in the linear portion of the curve, is the area of the shaded triangle 0-a-b, as defined by equation (26.62). When an air gap is introduced, the effective permeability falls as shown by the decreased slope of line o-c. The figure shows that as the air gap increases, the inductance decreases. It can be shown that the stored energy in the air gap and core is represented by the shaded area o-a-c, for a given flux, BAe. It can be seen that the energy stored in the gap of length ε, o-b-c, although its length is much shorter than the core length, ℓc, is much greater than that stored in the core, 0-a-b. The total energy stored o-a-c, ET, in the magnetic circuit comprises the energy stored in the air gap, o-bc, Eε, plus the energy stored in the magnetic core material, o-a-b, Ecore. These two energies are equal to the areas of the shaded triangles, o-b-c and o-a-b, respectively in figure 26.10. That is ET = Ecore + Eε (26.65) = ½ Bc H cVc + ½ Bε H ε Vε If leakage is neglected, then the air gap flux is the same as the core flux. If fringing is neglected then the area of the core at the air gap is the same as the area of the gap. Then ET = ½ BH c Ae c + ½ BH ε Ae ε (26.66) = ½ BAe ( H c c + H ε ε ) For a gapped core, as shown in figure 26.13, from Ampere’s current law (horizontal axis in figure 26.10) Ni = H c c + H ε ε (26.67) Therefore, substituting equation (26.67) into equation (26.66) gives the total stored energy as ET = ½ BAe ( H c c + H ε ε ) (26.68) = ½ BAe ( Ni ) which is equal to the area of the shaded triangle o-a-c.

ℜ

=L/N

∨

Ve = Ve + Ae µi ε

1

µoAe/ℓe

Ni

Hcℓc

NI

(At)

Figure 26.10. Effects of an air gap on inductance and stored energy.

The inductance L is given by equation (26.4), that is Nφ L= i Substitution of equation (26.67) for the current i gives N 2φ L= H c c + Hε ε =

N 2 Ae µo c

µr where

total

=

c

N 2 Ae µo  (  +ε  c

=

+ε

c c

+ ε ) µ r  N 2 Ae µo µe = + µr ε  total

(26.69)

(26.70)

+ ε and

µe =

(

c

+ ε ) µr

c

+ µr ε

(26.71)

Making the usual assumption that the length of the core is much greater than the length of the air gap, >> ε , yields equation (26.28) for the effective permeability. c 26.5

Ferrite inductor and choke design, when carrying dc current

Air gaps in magnetic circuits are introduced in order to reduce the influence of a superimposed dc current, manufacturing dispersion and/or to improve parameter stability. Saturable inductors for a semiconductor switch turn-on snubber normally do not employ an air gap, in order to reduce the stored energy, which may be subsequently dissipated, and to minimise the magnetising current magnitude. Empirical equations have been derived for cylindrical inductors with a cylindrical core, which give an inductor with a large air gap. Design equations and examples are given in Appendix 26.11.

1193

Power Electronics

Chapter 26

iii.


1194

At high dc currents, the core material saturates, and µ∆ tends to unity. Air core inductance results, where L = Lo = c N 2 (26.74)

Figure 26.11. Permeability as a function of: (a) air gap, ε and (b) superimposed dc field and air gap. Figure 26.12. Hanna curves, showing trajectories for different air gaps.

26.5.1 Linear inductors and chokes The introduction of an air gap reduces the effective permeability, µe such that the coil inductance is given by the equation (26.22) L = µe cN 2 = µe Lo = AL N 2 (H) (26.72) Figure 26.11a shows the variation of the effective permeability, µe at both low flux levels and without a dc bias, as a function of the relative air gap, ε/ℓe as specified by equation (26.27). As the air gap and the superimposed dc field are varied, the incremental permeability, µ∆ varies as shown in figure 26.11b. This figure indicates how inductance varies with dc bias current (H). Figure 26.11 does not specify the optimum inductor design since for a given inductance and dc current the optimum air gap and number of turns are not specified. The minimum number of turns and air gap requirements, for a dc current, can be determined by means of the Hanna curves in figure 26.12. This figure shows experimental families of curves of per unit core energy against magnetomotive force per unit length, for different air gap widths. The resultant curves are ferrite type dependent and dimensionally independent. Hanna curves therefore allow the determination of minimum turns N and air gap ε, from the required inductance L and dc current I. Three distinct energy levels are shown in the Hanna curves in figure 26.12. i. At low dc currents (H) the per unit energy increases linearly with H. This region corresponds to the horizontal regions in figure 26.11b, where L = µ∆ cN 2 (H) (26.73) and as H varies, µ∆ is constant. ii In the mid energy region, the per unit energy can decrease with increased H. The incremental permeability decreases, causing L to decrease at a greater rate than the increase in the dc current squared, I2. This region is characterised by the fall off in µ∆, hence inductance, as H increases as shown in figure 26.11b.

Example 26.3: Inductor design (ferrite) with Hanna curves A 20 µH, 10 A choke is required for a forward converter. The inductance must be constant for unidirectional currents to 10 A. An available E-core pair has the following effective parameters ℓe = 0.11 m, Ae = 175 × 10-6 m2, Ve = 19.3 × 10-6 m3 and µi = 2500 @ 25°C and 3000 @ 100°C (from figure 26.9) i.

At a core temperature of 25°C, determine the required air gap and turns. Allow a 5 per cent decrease in inductance at rated conditions. ii. Estimate the inductance at 20A dc. iii. Calculate the inductance at 10A and 20A dc, both at 100°C. Solution LI 2 20 × 10−6 × 102 = = 104 J/m 3 19.3 × 10−6 Ve From figure 26.12, restricted to the constant-L region, 104 J/m3 corresponds to (a) ε/ℓe = 3 × 10-3 whence ε = 3 × 10-3× ℓe = 3 × 10-3× 0.11 The required total air gap is 0.33 mm (b) H = 650A/m Since H = NI/ ℓe N = H ℓe /I = 650 × 0.11/10 = 7.15 turns Use 7 turns and a 0.33 mm total air gap.

i.

Evaluate

ii.

At 20 A, 25°C H = NI/ ℓe = 7 × 20/0.11 = 1270A/m

1195

Power Electronics

Chapter 26


1196

Two alternative design approaches may be used to estimate the inductance. (a) The effective permeability, µe, before saturation can be evaluated from equation (26.27) 1 1 ε 1 = + = + 3 × 10−3 µe µa le 2500 that is µe ≈ 300 From figure 26.11b, for µe = 300 it can be seen that the incremental permeability µ∆ is constant, as required to 650A/m, then µ∆ decreases as saturation commences. At H = 1270A/m, µ∆ has fallen to 75, from 300. The incremental inductance at 20 A is about ¼ of 20µH, namely 5.0µH. (b) Alternatively, a simpler approach uses only figure 26.12. H = 1270A/m projects 100 J/m3. Solving 100.0 = L20A I2 / Ve with I = 20A yields L20A = 5µH. iii. The effective permeability at 100°C is 1 1 ε 1 = + = + 3 × 10−3 µe µi le 3000 that is µe ≈ 300 It is seen that, although the initial permeability varies significantly with temperature, here the effective permeability is dominated by the air gap, hence is essentially temperature independent. Figure 26.11b, with H = 640A/m, projects µ∆ = 220 at 100°C. Using L α µ∆, the inductance falls to about 15µH at 100°C, 10 A. At 20A, 100°C, the effects of saturation are highly significant, and figure 26.11b indicates that the incremental permeability is low. The best approximation is to use the air coil curve in figure 26.12. Hence H = 1270A/m projects 9J/m3. From 9 = L20A I2 / Ve, at 20A, 100°C, an inductance of at least 0.43µH can be expected.

Figure 26.14. Comparison of inductance characteristics illustrating how inductance falls off faster with ferrite cores than with iron cores, at higher currents.

♣ Figure 26.5 shows how µ∆ and hence the inductance, falls off as H, and hence the current, increases for ferrite core materials. The larger the air gap, and hence the lower AL and the lower L, the higher H before inductance rolls off. Inductance rolls off faster, the wider the air gap, hence the higher the magnetic field strength, H. The decrease in effective permeability, µe and inductance factor, AL, with increase of air gap, ε, is shown in figure 26.13 for two E-cores. Figure 26.14 shows typical curves for the decrease in µ∆, hence inductance, with increased H, hence current, for both ferrites and alloy or iron powder cores. Because power ferrites have a squarer B-H curve than powder cores, the inductance of ferrites falls off faster. By increasing the core volume, the fall off rate of inductance can be reduced. Depending on core loss for a given volume, a powder core may be more effective than a ferrite; and would have better utilisation of the copper window area. The design approach previously considered in example 26.3 in fact neglects the optimisation of core size and copper I2R loss.

2

Figure 26.15. Magnetic biasing capability I L , copper loss I2R, effective permeability µe and over-temperature ∆T of five different effective volume Ve ferrite cores.

26.5.1i - Core temperature and size considerations Figure 26.15 relates stored energy, LI2, and copper loss, I2R, for different cores of the same ferrite type. Once L and I are fixed, figure 26.15 can be used to determine the optimum core size and air gap. This figure shows that with increasing air gap (decreasing µe), the magnetic biasing capability increases along with the associated copper loss, I2R. A flowchart is shown in figure 26.16, which outlines the inductor iterative design procedure to be used in conjunction with figure 26.15.

Figure 26.13. Characteristics of a pair of gapped E-cores. Core dimensional parameters are given in table 26.5.

1197

Power Electronics

Chapter 26


1198

For I = 10 A dc, I2RCu = 1.8 W, then RCu = 18 mΩ. The copper turns diameter is determined from RCu = N N RL (Ω) (26.75) where RL is the resistance per meter, Ω/m. ℓN is the mean turn length which is either provided for a given former or may be estimated from core physical dimensions. From table 26.5: ℓN = 52 mm RL = RCu / N ℓN = 18 ×10-3/21 × 52 × 10-3 = 0.165 Ω/m 26.14

Using standard wire tables, Appendix 26.12 for 0.165 Ω/m, use 28 SWG (0.154 Ω/m) which has a diameter of 0.36 mm and 0.434 when enamelled. The resultant copper current density is 77 A/mm2. In many applications 4 A/mm2 is used for finer gauge wires up to 20 A/mm2 for heavier gauge wires. These current densities represent about 5 per cent of the fusing current, Ifusing which is approximated by I fusing = 80 d 1.5 The diameter d is in mm. This constraint is unrealistic and inductor and transformer design is based on temperature rise. The approximate copper area is ACu = N × d 2 = 21× 0.4342

26.9

= 3.88mm 2 From table 26.5, the useful winding cross-section is AN = 56 mm2 Only 8 per cent of the former window area is filled, hence the actual copper length is overestimated and I2R loss, hence temperature rise, will be less than the allowed 1.8 W and 50°C respectively.

♣ Comparing the design of examples 26.3 and 26.4, it will be seen that the same design specification can be fulfilled with the latter core of 20 per cent the volume of the former. The bigger core required an 0.33 mm air gap to give µe = 300, while the smaller core required a larger gap of 2.7 mm to give µe = 40. Both cores are of the same ferrite type. The incremental inductance of the smaller core will fall off with current, much faster than with the larger core, as indicated by figure 26.5. For a switch mode power supply application, the rms value of current is less than the peak current at which the inductance is specified. The copper loss, hence temperature rise, is then based on an rms current basis. 26.5.2 Saturable inductors

Figure 26.16. Linear inductor design flowchart.

Example 26.4: Inductor design including copper loss With the aid of figure 26.15, design a 20 µH, 10 A dc inductor, calculating the copper loss and temperature rise for the predicted optimum air gap and number of turns. Solution Following the procedure outline in the flowchart of figure 26.16 Evaluating LI2 = 20 ×10-6 x 102 = 2 mJ From the monogram in figure 26.15 use core # 1, with µe = 40 and I2R = 1.8 W. This copper loss will produce a 50°C temperature rise above ambient on the core surface, beneath the winding. The thick bars in figure 26.15 represent a 30-50°C temperature increase range. The core type # 1 has AL and µe values versus total air gap, and effective parameters as shown in figure 26.13 and table 26.5. For µe = 40, AL = 45 nH, a total air gap of 2.7 mm is required. From L = AL N2 N = √20 × 103/45 = 21 turns

Saturable inductors are used in series with semiconductor switching devices in order to delay the rise of current, thereby reducing switch turn-on stress and loss. In the case of a power transistor, the collector current is delayed until the collector voltage has fallen (see 8.3.4). For thyristor devices, the delay time allows the gate activated cathode area to spread hence giving a high initial di/dt capability. In each case the inductor supports the supply voltage, then after a finite time saturates to a very low inductance, supporting little voltage, and does not influence the switch current. Ferrites are ideal as the core of a saturable inductor because of their low magnetic field strength, Hs, at the onset of flux density saturation, Bs. While the inductor supports voltage, v, the flux density increases, moving up the B-H curve at a rate according to Faraday’s law dB v = NAe (26.76) dt A low magnetising current results. After a finite time the flux density reaches the knee of the B-H curve (Bs, Hs), the core saturates and the incremental permeability falls from an initially high value to that of air, µ∆ = 1. The high initial permeability, hence high inductance, limits the initial current. The time ts, for the core to saturate should be equal to the switch turn-on voltage fall time, tfv. The low saturation inductance allows the switch current rapidly to build up to a level dictated by the load. If the switch voltage fall is assumed linear then the inductor voltage rise is Vs t / tfv. The time ts, taken to reach core saturation (Bs, Hs) from integration of Faraday’s law is (see Chapter 8.3.4) 2 NAe Bs ts = (26.77) Vs for ts ≤ tfv.

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Chapter 26

The flux density, hence H, and current increase quadratically with time, I s (t / t fv

)

2


1200

. At saturation the

magnetising current magnitude (hence switch current) is  2B H V  H Is = s e  = s s e  (A) N ts Vs  

(26.78)

which should be small compared with the switch on-state full-load current magnitude. The inductance before saturation is given by L = AL N 2 (H) (26.79) and falls to that of an air-cored inductor, viz.: Lsat = c N 2 (H) (26.80) after saturation, when leakage and lead length will, in practice, dominate inductance. The energy stored in the core (pre-saturation) and subsequently dissipated at core reset is given by E = ½ Bs H sVe ( = ¼ I sVs ts ) (26.81) = ½ Bs H s Ae e (J) which must be minimised.

(26.77))

Table 26.4 summarises saturable inductor requirements based on equations (26.77) to (26.81). Table 26.4: Design requirement of a saturable inductor Material dependent Bs Hs

Given Vs and tfv Minimise energy E = ½ Bs Hs Ae ℓe Maximise time ts =2NAeBs / Vs Minimise mag current Is = Hs ℓe /N Maximise inductance La = N 2Ae Bs / ℓeHs

Core shape dependent Ae ℓe N

E

(J)

low

low

low

low

×

ts

(s)

×

high

high

×

high

Is

(A)

low

×

×

low

high

L

(H)

(26.78))?

low

high

high

low

high

Requirement

low Hs (high µr)

-

-

short ℓe

high N

Compromise

-

high Bs if Hs is low

high Ae if ℓe is short

(26.81))?

Figure 26.17. Saturable inductor design flowchart.

26.5.3

Saturable inductor design

Figure 26.17 shows a saturable inductor iterative design flowchart. The design starting point is the type of ferrite. The desired ferrite should have minimal high frequency loss, associated with a low magnetic field intensity, Hs, at saturation. These features would be associated with ferrites having a low coercive force, Hc and remanence, Br. The ferrite material shown in figure 26.4 fulfils these requirements with H c = 12A/m Br = 0.18T H s = 200A/m Bs = 0.4T Ferrites with lower magnetic field strengths are available but tend to be limited in size. A material with a high initial permeability is one indicator of a suitable ferrite type. The next considerations are core shape and effective core parameters such as effective length, ℓe and area, Ae. The core should have a short effective length, ℓe. The area and length are traded in maintaining sufficient copper window area, AN. A core shape without an air gap will produce the highest possible initial, hence effective, permeability. Example 26.5, which follows, illustrates that a toroid (or tube) core offers a good solution. A high number of turns, N, is desirable, and preferred to an increase in area, Ae. Design should be based on the maximum core temperature. An increase in temperature decreases Hs at a faster rate than Bs, as shown in figure 26.4. From equation (26.77), many turns are required which, in combination with decreased Hs, advantageously decrease the magnetising current, Is.

Table 26.5: Pot, toroid, and E-core design data. Applicable magnetic data are presented in appendix 26.9

Pot core do = 25 h = 16

Physical dimensions (mm) E-core (pair) Toroid See figure 26.13 do = 39 di = 24.77 h = 6.61

Ve

cm3

3.63

3.86

3.02

Ae ℓe

cm2

0.398

0.525

cm

0.999 3.64

c1

cm1

3.64

9.71 24.4

5.75 10.9

Amin

cm2

0.95

0.398

0.45

AL

nH

4300

1540

(ε = 0)1750

1245

(µi) 3000

(ε = 0)1500

c

nH

3.45

0.51

1.15

AN ℓN

cm2

0.357 (0.266) 5.3 (5.35)

4.75 7.6

0.56 5.2

µe

cm

SA

cm2

18.4

48.7/58

20

Weight

g

23.4

19.3

2×8

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1202

Example 26.5: Saturable inductor design (also see example 8.6) A pot, toroid, and E-shaped core of the same Mn-Zn ferrite as characterised in appendix 26.9, and of similar volume, have characteristics and parameters as shown in table 26.5, with Hs = 200At/m. Design a saturable inductor for each core shape, for a switch having a 200 ns linear voltage fall time at turn-on when switching on a Vs = 600 V dc supply rail. The core is to saturate when the switch voltage reaches saturation (0 V), after 200ns. Estimate the core power removed at reset if the switching frequency is 20 kHz. Solution

From equation (26.77) N = Vs tfv /2AeBs = 1.875/Ae Ae is in cm2 From equation (26.78) Is = Hs ℓe /N = 2ℓe /N (A) ℓe is in cm From equation (26.79) 2 -3 (µH) L = AL N × 10 From equation (26.80) 2 Lsat = c N (nH) From equation (26.81) -1 (W) Pd = Ve×8×10 Ve is in cm3

Pot

Toroid

E-cores (ε = 0)

2

5

4

3.64

3.85

2.83

17.16)

17.11a)

20.2

38.5

28.0

13.8

12.75

18.4

2.90

3.09

2.42

17.11c)

(figure 26.15)

Based on the available copper window area, AN and number of turns, the cores would be applicable to switching currents in excess of 100 A. Smaller cores could be used for lower current levels, although window area AN tends to dictate the required core. From equation (26.81), the power dissipated at 20 kHz (last row in the table) is given by Pd = ½ Bs H sVe f s .

♣ Figure 26.18. Transmissible power, P, versus volume (ferrite plus copper), V, of transformers with ferrite Mn-Zn cores.

26.6

Power ferrite transformer design

Above a few kilohertz, Mn-Zn ferrite material is almost exclusively used for power transformer cores, and has been optimised by manufacturers for a wide frequency range. Specific core shapes have also been developed to cover a wide power range. In the case of voltage transformers, at 20 kHz and below 100 W, pot cores are used, or when low flux leakage and low emi are important. Such cores can be processed on automatic machines which wind and assemble the whole unit. At powers above 100 W, EE and E-I cores are extensively used. The usable power range of the pot core is increased by increasing frequency and at 500 kHz no alternative exists, because of the low leakage flux, low self-capacitance, and good shielding offered by pot cores. 26.6.1 Ferrite voltage transformer design To simplify ferrite core selection, manufacturers provide the characteristic curves given in figure 26.18 which show the power that can be transmitted by various core shapes. Specifically, these curves show power for the modes of operation commonly used in switch-mode power supplies; such as push-pull, forward, and flyback, as considered in chapter 17, versus the core plus copper volume. A formal transformer design approach based on copper and core losses is shown in the flowchart in figure 26.19 and is applicable to all smps types.

Stage 3 The difference between input power and output power is the total power loss, PL, which comprises copper and core losses. The maximum efficiency is obtained when the copper loss equals the core loss. Stage 4 The total power loss, PL, ambient temperature, Ta, and temperature rise, ∆T, specify the exposed copper and core surface area requirements, SA, according to (see equation 5.4) PL SA = (m 2 ) (26.82) ∆T Sd where Sd is a surface dissipation factor. Empirical equations are commonly provided for Sd. Based on the assumption that thermal stability is reached half by convection and half by radiation, the surface area requirement can be approximated by  1000  S A = 145 ×    Ta + 273 

Stage 1 and stage 2 The transformer, primary and secondary voltages, currents, and powers, hence efficiency, must be specified or determined. Other requirements are switching frequency, ambient temperature, and allowable temperature rise at the core to copper interface. The final specification should include V p Vs Ip

Is

Pp

Ps

η , f , Ta , ∆T

2.06

PL ∆T 1.22

(cm 2 )

(26.83)

Stage 5 A core with the minimum surface area, SA, is selected using manufacturers’ data, ensuring that the ferrite type is appropriate to the operating frequency and that the core shape meets any engineering, cost or other special requirements. The manufacturers’ data required include the effective dimensional parameters, copper winding area, AN, and average turn length, ℓN. Some manufacturers provide transformer design data for each core. This specific data can be employed, rather than the general procedure that follows.

1203

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Chapter 26


1204

while for a core used with a flux bias Bop ≤ 0.4 Bs These limits avoid operational saturation of the core in one direction. If the working flux density, Bop, is too high, either • reduce the efficiency and go to stage 1/2, or • reduce the allowable temperature rise and go to stage 4. Stage 8 The required number of primary turns, Np, can be calculated from Faraday’s law, which yields Vp (26.84) Np = k Bop Ae f where k = 4 for a square-wave voltage k = 4.44 for a sine wave. If Bop > 100 mT, the effective area, Ae, in equation (26.84) is replaced by the core minimum area section, Amin, since that portion experiences the highest flux density.

26.7c

The number of secondary turns is calculated according to V Ns = N p s Vp

(26.85)

Stage 9 The winding diameter, dp, for the allotted primary for a window area, Ap, is calculated according to Ap kw dp = 2 (m) (26.86) π Np where kw is a winding space factor, 0.7, which accounts for insulation, winding taps, shielding, air space, etc. A similar expression for the diameter of the secondary, dp, involves the number of secondary turns, Ns, and allotted area, AN. The total winding area Ap + As must not exceed the available winding area, AN. Standard copper wire tables, Appendix 26.12, provide the resistance per meter, RL, for the calculated diameters. From equation (26.75), the dc resistance of the primary can be calculated according to R p = N p N RLp (Ω) (26.87) Similarly for calculating the secondary dc resistance, Rs. The total copper loss can be calculated as PCu = I p2 R p + I s2 Rs

(W)

(26.88)

Stage 10 The core loss, Pc, and the copper loss, PCu are compared. If (i) PCu > Pc Either decrease the number of turns and increase the copper diameter. This will reduce the copper loss and increase Bop, and hence Pc. Recalculate from stage 6. or select a larger core, which will increase the copper window area, AN, hence increasing the allowable wire diameter. Recalculate from stage 5.

Figure 26.19. Voltage transformer design flowchart.

(ii) PCu < Pc Either increase the number of turns which will reduce diameter d, Bop hence Pc, and then recalculate from stage 6. or select a smaller core, which will require d to be reduced, and then recalculate from stage 5.

Stage 6

Proceed if PCu ≈ Pc.

Using the core volume, Ve, and core loss Pc = ½PL, whence core loss per cm3, Pw = Pc /Ve the maximum allowable operating flux density, Bop, for the specified frequency can be determined from the power loss curves in figure 26.8c.

Stage 11

Stage 7 The rated saturation flux density, Bs, cannot safely be used. For a transformer using both quadrants of the B-H characteristics, for example, a push-pull smps transformer Bop ≤ 0.8 Bs

Update the value of total losses, PL, and hence recalculate the power requirements and resultant efficiency. Calculate the actual core temperature rise from equation (26.83), rearranged 1.69

0.82

 1000   PL  ∆T = 59  (K)  ×   SA   Ta + 273  2 where SA is the heat dissipating area in cm of the chosen core.

(26.89)

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Chapter 26


1206

Example 26.6: Ferrite voltage transformer design

Stage 6

Consider the design requirements for the split dc rail push-pull smps shown in figure 15.15b, which is specified as follows

Using the technical data given in table 26.5, the core loss per unit volume is calculated P 0.35W Pw = = = 0.096W/cm 3 Ve 3.63V Stage 7

vo = 5 V io = 4A Po = 20 W

Vs = 48 V ± 15 per cent f = 20kHz Ta = 25°C, ∆T ≤ 35 K η = 97 per cent (excluding secondary stage losses)

Solution

From figure 26.8c, an operating flux density of 0.21 T at 20 kHz will result in the allowable core loss of 0.1 W/cm3. For push-pull operation, the maximum allowable flux density is about 80 per cent of Bs, that is, 80 per cent of 0.48 T, namely 0.38 T.

Based on the flowchart in figure 26.19 and the eleven stages outlined, design proceeds as follows.

Since 0.21 T < 0.38 T, a working flux density of 0.21 T is acceptable.

Stage 1

Stage 8

The transformer must deliver 20 W plus losses associated with an output inductor and the pair of Schottky diodes in the output rectifier. The inductor loss is estimated at 4 per cent of the output power, 0.8 W, while the diode total loss is 0.6 V × 4 A = 2.4 W. Thus the transformer output power requirement Ps is 23.2 W (20 W + 0.8 W + 2.4 W). With a 97 per cent efficiency, the transformer input power, Pp, requirement is 1/97 per cent of 23.2 W, namely 23.9 W. The nominal primary current, Ip, at the nominal voltage, 24 V is Pp 23.9W Ip = = = 1A V pn 24V

Since the operating flux density is greater than 100 mT, the pot core minimum area, Amin (0.95 cm2) is used for calculations, rather than the effective area, Ae (0.999 cm2). From equation (26.84), the required number of primary turns is given by 27.6V Np = = 17.3 4 × 0.21T × 0.95 × 10 −4 × 20 × 103 Use 17 turns.

The maximum primary voltage, Vp, is ½ ×1.15×Vsec = 27.6 V, since the 48 V supply is centre tapped and has + 15 per cent regulation. For worst case, it is assumed that the voltage drop across the switches is zero. The transformer secondary voltage, Vsec, for the centre tapped full-wave rectifier circuit, must be large enough to overcome the diode voltage drop, Vd, and must allow for averaging of the nominal low duty cycle switching action of the primary input power. With pwm regulation each input switch operates for approximately 25 per cent of the time, thus ½Vs = 2× (Vo + Vd ) where the ½ indicates that half of the secondary winding conducts at any one time, while the 2 approximates the pwm average on-time. Thus for Vd = 0.6 V and Vo = 5 V Vsec = 4 × ( 5 + 0.6 ) = 22.4V Stage 2 Extracting the transformer data from stage 1 Ip = 1A Vp = 27.6 V Pp= 23.9 W

Is = 4A Vsec = 22.4 V Ps = 23.2 W

η = 97 per cent, f = 20 kHz, Ta = 25°C, ∆T = 35 K Stage 3

The number of secondary turns is given by equation (26.85) V 22.4 N s = s Np = × 17 = 15.7 Vp 24 where the nominal primary voltage is used. Use 16 turns per secondary winding. Stage 9 From table 26.5, the available winding area, AN, is either 0.357 cm2 for a one-section former or 0.266 cm2 for a two-section former. Since the primary and secondary voltages are relatively low, insulation and isolation present few difficulties, hence single enamel copper wire and a single section former can be used. The available copper area, 0.357 cm2, is divided between the primary and secondary so as to provide a uniform current density within the winding area. The primary to secondary currents are in the ratio of 1:4, hence 0.285 cm2 is allocated to the secondary (approximately 80 per cent) while 0.072 cm2 is allocated to the primary winding. The copper wire diameter is calculated using equation (26.86) Ap k w 0.072 × 10−4 × 0.8 = 2× = 0.66 mm dp = 2 π Np 17π ds = 2

dCu dCu+en RL RCu

Stage 4

0.285 × 10−4 × 0.8 = 0.95 mm 32π

mm mm Ω/m Ω

Primary 0.6 0.65 0.06098 0.055

Secondary 0.95 1.017 0.02432 0.0206/16 turns

bare Cu single enamel

The total power copper loss is given by equation (26.88) PCu = I p2 Rp + I s2 Rs = 12 × 0.055 + 42 × 0.0206 = 0.055 + 0.330 = 0.385W

Stage 5 Either the pot core in table 26.5 or the pair of E-cores in figure 26.13 have sufficient surface area, 18.4 and 20 cm2 respectively, and both are of a ferrite material suitable for a 10 to 100 kHz operating frequency range. At the low power level of 23.9 W ( ts Either increase the number of turns, using a core with a larger window AN if necessary. or increase the core area, Ae, which can be achieved with the same window area, AN, either with a core of increased thickness or by using two stacked cores. go to stage 3 ∧

(ii)

If ts >> t on Either decrease the number of turns which may allow a smaller core size. or decrease the core cross-sectional area. go to stage 3 ∧ If ts ≥ ∼ t on , proceed to stage 5

(iii) Stage 5

∧

Calculate the magnetising current at t on ∧

∨

Ip =

H s e t on N p ts

(26.96)

(A)

Stage 6 ∨

Calculate the secondary current, taking the magnetising current I p into account ∧

∧

Is =

(26.92)) ∧

∨

Ip − Ip nT

(26.97)

Is β = I p / I s sufficiently large?

(26.96))

∧

∧

If I p > β I s Either decrease the magnetising current by increasing core area. or increase the turns ratio, nT. go to stage∧ 3 ∧ (ii) If I p β I s Either decrease the turns ratio, nT. or decrease the core cross-sectional area. go to stage∧ 3 ∧ (iii) If I p < ∼ β I s , proceed to stage 7 (i)

Stage 7 Calculate the core reset voltage ∧

Vsr = V p Figure 26.20. Current transformer design flowchart.

t on ∨

t off

(V)

(26.98)

Power Electronics

1211

Calculate the reflected primary on-state voltage during core reset Vsr N p ep = Ns

Chapter 26


1212

Stage 4 (26.99)

The time, ts, before core saturation is given by equation (26.92), and assuming Br = 0 15×0.4×0.4T×10-4 = 100 µs ts = 2.4V ∧

Example 26.7: Ferrite current transformer design

Since ts > t on , that is 100 µs > 46 µs, proceed to stage 5.

A current transformer primary is used in the collector of a bipolar junction transistor switching circuit and the secondary is used to provide transistor base current as shown in figure 26.21. The maximum collector current is 100 A and the transistor has a gain of 8 at 100 A, in saturation (vbe sat = 1.2V).

Stage 5

The transistor maximum on-time is 46 µs while the minimum off-time is 4 µs. Design a suitable current transformer using the toroid ferrite core, which has low flux leakage and is specified by the data in table 26.5 and appendix 26.9. Assume a core temperature of 25°C.

∧

The maximum primary magnetising current, I p is specified by equation (26.96) ∧ 46µs 200×9.71×10-2 × = 4.47A Ip = 100µs 2 Stage 6 The 4.47 A of magnetising current detracts from the primary current available for current transformer action. The maximum available secondary current under worst-case conditions is given by equation (26.97) ∧ 100A - 4.47A = 12.7A Is = 15

2

The maximum allowable collector current is this base current, 12.7 A, multiplied by the transistor gain, 8, which yields 102 A. This is larger than the specified maximum collector current of 100 A, hence the design is correct. Stage 7

Figure 26.21. Current transformer for BJT base drive.

Solution Based on the flowchart in figure 26.20 and the procedure previously outlined: Stage 1 The required turns ratio factor is nT = Np / Ns = β = 8/1. In allowing for the magnetising current component, choose nT = 15/2. The secondary winding voltage is the maximum transistor base to emitter voltage plus the maximum voltage drop across a series diode. Maximum voltage occurs at maximum current. Vs = Vbe + VD sat

= 1.2V + 1.2V = 2.4 V

Stage 2 The current transformer requirements can be summarised as follows ∧

nT = Np / Ns = 15/2

t on = 46µs

Vsec = 2.4V

t off = 4µs

∨

Stage 3 The ferrite toroid core specified in table 26.5, fulfils the following requirements Bs = 0.4 T at Hs = 200 A/m and A = 0.398 cm2, ℓe = 9.71cm while the available window area, AN, is 4.75 cm2. This window must accommodate two conductor turns of 100 A (plus magnetising current) each and fifteen conductor turns of 12 A each.

In the on-state, the secondary voltage is 2.4V and the reflected primary voltage is 0.32V. The maximum secondary voltage, Vsr, required to reset the core is given by equation (26.98) 46µs = 27.6V Vsr = 2.4V× 4µs The reflected primary voltage is 3.7 V. The available inherent circuit reset voltage is usually much larger, being clamped by a base circuit diode in avalanche. Therefore the core reset time will be shorter than 4 µs. At currents much lower than 100 A, the secondary voltage is decreased, hence the magnetising current is reduced. This reduced magnetising current could consume the full collector current at collector currents of a few amperes. It is therefore necessary to add extra base current to compensate for this deficiency at low currents. The minimum secondary voltage, Vsec, specifies the extra requirement according to ∨

∧

Vs I p × (26.100) Vs nT ∨ For V s = 1.2 V, the extra base current requirement is 1.2 4.47 × = 300mA I b΄ = 2.4 7.5 This current can be delivered from an inductive circuit since zero extra current is initially required, and the requirement rises linearly to 300 mA in 46 µs. A base start pulse of a few microseconds duration is required initially to turn the transistor on, whence collector current is established and current transformer action commences, and is self-sustaining. I b΄ =

♣ 26.6.5 Current measurement: closed loop ferrite transformer Figure 26.22 shows a ferrite current measurement transformer where a compensation winding maintains the air gap flux at zero, enabling dc (as well as ac) currents to be measured. Measurement bandwidth is typically dc to 200kHz. The current to be measured, primary current Ip, produces an mmf in the ferrite toroidal core. A Hall effect transducer detects the flux in the core air gap and an op amp compensation circuit drives current through the high turns winding in an attempt to zero the core flux. The current in the compensation winding is therefore proportional to the current being measured, according to N pI p = NsI s (26.101) The same transducer can be used to measure voltage by adding an external series resistor in the primary, which produces a current that is measured, which is proportional to the voltage. The number of

Power Electronics

1213

Chapter 26

primary turns is usually large so as to minimize the resistor current. The resistance, in conjunction with the primary self inductance (and leakage), limit the measurement bandwidth, to the time constant L/R. VH B

Hall effect transducer

VH ∝ I ⋅ B

Φ=o Ip

Is Hall

d

+ -

1: ηT

i(t)

Is

i(t)

RB

Vo = Is RB = ηT Ip RB

Figure 26.22. Current measurement transducer using a flux compensated toroidal ferrite core.

26.6.6 Current measurement: Rogowski Coil Rogowski coils, shown in figure 26.23, are used for passive detection and versatile non-invasive measurement of alternating current (AC) or high speed current pulses (non-dc). It is typically wound on an air-core so in theory there are no effects due to hysteresis, saturation, or non-linearity. The operating principle is that if a closely uniformly wound air-cored toroidal coil of N turns/m is placed axially around a straight conductor carrying current i in a closed path, the alternating magnetic field produced by the current in the conductor induces a coil output voltage E in the coil that is proportional to the rate of change of the cross section area A sq m which encircles any flux linked component produced by the current i, given by the expression:

E = −M

di dt

current i(t)

where M is the mutual inductance between the Rogowski coil and the conductor and di/dt is the rate of change of current in the conductor. If the coil outputs are connected to an integrator, the output signal reproduces the current waveform. Instead of measuring the short circuit current through the coil directly, the measurement is instead the integral of the open circuit voltage.

There are two advantages to the Rogowski coil. One advantage of a Rogowski coil over other types of current transformers is that it can be made openended and flexible, allowing it to be wrapped around a live conductor without disturbing it. A second advantage is that the Rogowski coil does not use a magnetically permeable core like a standard current transformer, making it of low inductance. Since it has no permeable core to saturate, it can respond linearly to extremely large currents. Being of low inductance it can also respond to very fast frequency pulses. A standard current transformer can have its core saturated at very high currents, and the inductance limits its frequency response. The closer in form to a perfectly symmetric toroidal uniform coil of wire, with equally spaced windings, the Rogowski coil is less susceptible to external electromagnetic interference. Rogowski coil operating principle A Rogowski coil works by sensing the magnetic field in the space around the conductor that carries the current. The relationship is given by the Ampere’s Law. According to it, the line integral of the magnetic field around a closed loop is equal to the net current encircled by it, no matter what path the loop takes.

∫ H cos α d

B = µo H =

emf induced by changes in magnetic field produced by conductor current

Substitution of B gives

Vcoil = −NA

u c to

integrator

(26.102)

where S is the mean circumference of the toroid and M is the mutual inductance between the coil and the conductor and is independent of the frequency. The self-inductance L of a coil uniformly wound with a toroidal shape toroid, which affects the output voltage frequency response, is L = µo N 2 R − R 2 − r 2  (26.103)   If a rectangular cross section ring is used then the emf produced is given by

µo NH c di n b dt 2π

In order to get a voltage proportional to current an integrator - either active or passive - must be used. An active integrator, as shown in figure 26.23, using an operational amplifier is a common solution. The op-amp needs to have sufficient frequency response (both upper and lower cut off half-power points) and current sourcing and sinking capability to drive the capacitor at the expected frequency.

C

Vcoil

dB dt

where H is the rectangular core height and b and c are the inner and outer diameter of the coil.

LP filter

r

dt

µ NA di µ NA di dB di =− o =− o = −M dt S dt dt 2π R dt

Vcoil = −

cond

µo i

2π R where µo = 4π×10-7 and R is the perpendicular radial distance from the conductor to the point at which the magnetic field is calculated (the major radius of the toroid). The direction of the magnetic field being tangentially perpendicular to the current and to the radius r, and determined by use of the right hand rule. Each turn of the Rogowski coil N turns produces a voltage proportional to the rate of change of the magnetic flux B through the turn. Assuming a uniform magnetic field density throughout the turn of area A, by Faraday’s equation, the rate of change magnetic flux is equal to the rate of change of magnetic field density times the cross-sectional area of the turn π×r2 (toroid cross section radius, r). dΦ dB = −A Vturn = −

Vcoil = −NA

current i(t)

R

= i (t )

The mathematical expression that shows this effect where dℓ is a small element of length along the loop, H is the magnetic field in dℓ and is the angle between the direction of the field and the direction of the element. The magnetic field due to a long straight conductor carrying current i, in air, is

dt

±

i(t)

1214

The output voltage from the coil with N turns, effectively series connected, is

B(t) magnetic field produced by conductor current

Rogowski coil


Vout

Figure 26.23. Rogowski coil and active integrator basic operation.

The integrator needs a resistor placed across the capacitor in order to be made into a leaky integrator. The resistance placed across the capacitor should be just small enough to leak off the capacitor and keep it zeroed but not so small that it interferes with the integration performance in the frequencies of interest. Ignoring any leaky resistance added to the integrator of figure 26.23 the output is 1 Vout = − ∫Vcoil dt

RC

Power Electronics

1215

Chapter 26

After integrating the signal of equation (26.102) the total output voltage is 1 di M Vout = ∫ M dt = i

RC

dt

τ

Vout M = i τ

dB

where Vout is the output voltage of the integrator, τ = RC is its time constant and i is the conductor current. Changing τ, operation range can be modified and it is possible to operate from mA to MA.

M/τ -3dB

Gain

fL

FH f

2 - Rigid Rogowski coil The rigid coils are wound on a solid plastic former, normally in a toroidal shape, and tend to be bulkier than flexible coils but have better stability. External insulation can be composed of one or several insulation layers. Alternatives are varnishing or encapsulated and potted. An electrostatic screen can be added to improve insulation to external influences. The output voltage is stable and the accuracy is good. A rigid coil lower measurement frequency range is lower than with flexible coil, hence is more applicable for low current and low frequency measurements. Disadvantageously, being a continuous ring, the current-carrying conductor must be disconnected and placed through the core centre hole before the measurement. It can be used for high precision measurements or for permanent installation. Typical electrical features are: Mutual inductance M: Maximum frequency: Minimum frequency: Current range: Accuracy:

V out/I

V/A

1216

Typical electrical features are: Mutual inductance M: between 30 and 300nH. Maximum frequency: between 100kHz and 1MHz depending on M. Minimum frequency: between 1 and 10Hz, depending on the integrator. Current range: from 1A to >1MA. Accuracy: 1%.

The transducer/amplifier sensitivity, or transfer function, is:

frequency (log scale)


Hz

Figure 26.24. Frequency response of a Rogowski coil and integrator. It is important to take into account linearity and bandwidth of integrator, and design it according to the kind of current to be measured. For high frequencies it is appropriate to use a passive integrator composed only of R and C, such that the mid-band gain is M/CR (V/A) The relationship Vout proportional to i is constant across the transducer bandwidth. The bandwidth is defined as the range of frequencies from fL to fH for which sinusoidal currents can be measured to within 3dB of the specified sensitivity M/CR, as shown in figure 26.24. At low frequencies, the integrator gain increases and theoretically becomes infinite as the frequency approaches zero. This would result in unacceptable dc drift and low frequency noise; hence the integrator gain is limited at low frequencies. This limitation is controlled by a low pass filter in parallel with the integrating capacitor C. The low pass filter sets the low frequency bandwidth fL, typically less than 1Hz. Furthermore, due to the distributed inductance, equation (26.103), and inter-turn capacitance of the Rogowski coil, there is a high frequency bandwidth fH, (generally >1MHz) above which the measurement is attenuated and significant phase delay occurs. Construction There are a number of Rogowski coil current transformer types. 1 - Flexible Rogowski coil The insulated winding is placed over a long and flexible plastic former typically between 3.5 and 15mm in diameter. The coil is fitted by wrapping it round the conductor to be measured and bringing the ends together. External insulation can be composed of one or several insulation layers (to increase the sensitivity), thermal shrinkable protection, electrostatic screen, which affects the flexibility of the coil. Electrostatic screen can be added to improve insulation of external influences. Although less sensitive and less accurate than the rigid form, a flexible coil is better for high frequency measurements. It is useful with large size or awkward shaped conductors or in places with limited access or where a lightweight transducer is needed which can be suspended on the conductor. As an open coil, it is not necessary to disconnect the conductor that carries the current to be measured and the user has only to unit the ends after the coil is placed around the conductor. Its form is compact and versatile.

between 3 and 5µH. between 10kHz and 30kHz depending on M. down to 0.1Hz, depending on the integrator from 100mA to >100A. 0.1%

3 - Planar coil The sensor can be manufactured using a planar coil rather than a toroidal coil. In order to reject the influence of conductors outside the sensors measurement region, planar Rogowski current sensors use a concentric coil geometry instead of a toroidal geometry to limit the response to external fields. The main advantage of the planar Rogowski current sensor is that the coil winding precision that is a requirement for accuracy can be achieved using low cost printed circuit board manufacturing. Features and applications A Rogowski coil used as current sensor has numerous advantages: • The air coil has no hysteresis, it does not saturate and is linear. The mutual inductance is independent of the current. • Non intrusive. • Good response to current transients, so they are appropriate for current pulse measurements or for protection systems. • High bandwidth. The high-frequency limit is determined by the self-resonance of the coil and depends on the coil design. Although not applicable to DC measurement, with an accurate integrator design, it is possible to measure frequencies lower than 1Hz. • Can measure ac signals superimposed on large dc currents. • The same coil can measure a wide range of currents, from mA to MA, with a typical sensitivity of 1.0mV/A for ± 6000A peak, and a di/dt typically from 1 to 25kA/µs, over a coil temperature range from –20Cº to 100ºC.. • Easy calibration. Because of its linearity, coils may be calibrated at any current level. • It is lightweight, compact and easy to install and to transport. Importantly, it is easy to use. • Output variation with the temperature is low. • Low power consumption, and can be totally passive. Low cost. • High frequency bandwidth (3dB) decreases with coil length, for example, 100mm 12MHz, 200mm 8MHz. • Rogowski Coil cross sectional diameter specifies electrical isolation, for example, 3.5mm for 2kV isolation and 4.5mm for 5kV isolation. Another useful feature of a Rogowski sensor is immunity to far-field interference. EMF components induced by the same far field source will cancel each other. Two components of EMF induced by the current passing through the wire inside the coil will be added to each other. One disadvantage is that the Rogowski coil produces an EMF proportional to di/dt. Therefore, at connecting or disconnecting instants, the EMF goes ‘infinite’. Transient voltage suppressors or other voltage protection is needed to prevent overloading the interfacing electronics. Also, accuracy is slightly dependant on position of the current carrying conductor in loop

Power Electronics

1217

Chapter 26

Table 26.7 highlights the differences between five current measurement techniques, namely the conventional current transformer, Hall effect sensor, current transformer based on a Rogowski coil, flux gate (which is a Rogowski coil with a magnetic core) and a shunt resistor.

Table 26.7: Features of five current measurement techniques Feature

Current transformer

Hall effect

Rogowski coil

Flux gate

Shunt resistor

N1I1 = N2I2

VH = I·B

V α µodI/dt

V α µoµrdI/dt

VS = I·RS

bandwidth

low

medium

high

medium

low

isolation

high

high

high

high

low

linearity

good

medium

excellent

good

low

High current measurement capability

Operating principle

good

good

very good

very good

low

Saturation and hysteresis problems

yes

yes

no

no

no

Power dissipation

low

medium

low

medium

low

Temperature effects on output

low

medium

very low

low

medium

Transient response

medium

medium

very good

medium

low

Low frequency response

medium

very good

good

medium

low

Dc offset

no

yes

no

yes

no

Easy of installation

medium

medium

medium

medium

low

weight

medium

medium

low

medium

low

dimensions

medium

medium

low

medium

low

cost

medium

high

low

high

low


1218

In the transformer, the power is transmitted from the primary to the secondary circuit via the magnetic field, such that the input VA is equal to the output VA, assuming losses windings and neglecting any magnetising current. That is S = VAXfm = V1I 1 = V 2I 2 (26.105) The energy flow through the autotransformer is the summation of magnetic transformation (induction) phenomena and input to output current conduction. The conduction results from the series connection of the autotransformer’s primary and secondary circuits. The accumulative (additive) series connection is assumed, as indicated by the dots in figure 26.25, since no advantages are gain when the windings are differentially connected. The VA capability of an auto-transformer does not depend on whether the common connection point forms an input terminal or output terminal. It is assumed that each winding exploits its full VA rating, as define by equation (26.105). When the common connection forms the auto transformer input, giving a step-up voltage, as in figure 26.25b, the voltage transfer ratio is Vout / Vin = (V1 + V2 )/ V1 = 1 + ηT and the input (and output) VA is: VAautoX −i / p = V1I in = V1 ( I 1 + I 2 )   I  1  = V 1  I 1 + 1  = V 1I 1  1 +  ηT  ηT     1  = VAXfm  1 +  ηT  

When the common connection forms the auto transformer output, giving a step-down output voltage, as in figure 26.25c, the voltage transfer ratio is Vout / Vin = V1 / (V1 + V2 ) = 1 / (1 + ηT) and the output (and input) VA is: VAautoX −o / p = V1I out = V1 ( I 1 + I 2 )   I  1  = V 1  I 1 + 1  = V 1I 1  1 +  ηT  ηT     1  = VAXfm  1 +  ηT  

An autotransformer is a single winding electrical transformer that has at least three electrical connections called taps. The voltage source and the load are each connected to two taps. One tap at the end of the winding is a common connection to both circuits (source and load). Each tap corresponds to a different source or load voltage. In an auto-transformer a portion of the same winding is part of both the primary and secondary winding.

In each case, the first term is associated with transformer action between the two windings, while the second term is that current component that conducts from the input to the output. Generally  1  VAautoX = VAXfm  1 ±  (26.106) ηT   where the plus sign is applicable to when the two windings are additively connected (as in figure 26.25b and 26.25c), while the negative sign implies the two windings are connected to oppose. Opposing windings offers poor copper utilisation.

When the primary side of a transformer with a winding of N1 turns is supplied with V1 voltage (satisfying V=Ndφ/dt), then on the secondary N2 turns, has induced V2 voltage, in accordance with the transformer turns ratio ηT:

The area, hence volume, thence weight, of copper required in a winding is proportional to the number of turns and to the cross sectional area of the wire. In turn the area is proportional to the current to be carried, that is, volume of copper is proportional to NI.

26.7

Auto-transformers

ηT =

V2 N 2 I 1 = = V1 N 1 I 2

(26.104) I2

I1 I2 V1

I1+I2

I2

V1+V2 N2

V2

V1

I1

N1

I2

I1 N2 V2

N2 V2

N1

Volume of copper ∝ length of the wire × cross sectional area of copper wire ∝N×I

V1+V2

I1+I2 I1

I2 V1

N2

Figure 26.25. Transformer and autotransformer connection diagram: (a) two winding transformer, (b) step-up voltage autotransformer, and (c) step-don voltage autotransformer.

V2

N1 - N2

N2 -N1 V2

N1

N1 V1

1:ηT

ηTI2

ηTI2

V1

I2

V1

ηTI2 - I2

N1

I2 -

ηTI2

N2

V2

1:ηT

Figure 26.26. Transformer and autotransformer diagram for V1 and V2 input and output voltages: (a) two winding transformer, (b) step-up voltage autotransformer, and (c) step-don voltage autotransformer.

Power Electronics

1219

Chapter 26

The magnetic circuit is assumed to be identical, satisfying V=Ndφ/dt. To quantify the copper saving, the total quantity of copper used in an auto-transformer is expressed as a fraction of that used in a two winding transformer, both with the same output VA, V2I2. The copper area in the two winding transformer in figure 26.26a is

For the step-up autotransformer, shown in figure 26.26b, with the same output VA rating (same input voltage V1 and same output voltage and current V2, I2) as the two winding transformer in figure 2a:  1  2N 2I 2  1 −  N (η I − I 2 ) + (N 2 − N 1 ) I 2 ηT  copper in auto-transformer 1  = 1 T 2 = =1− copper in two winding transformer 2N 2I 2 N 1I 1 + N 2I 2 ηT The pu copper saving for the step up autotransformer is 1/ ηT, where ηT ≥ 1.

) = 1 −η

(26.107)

The current in the common part of the autotransformer winding is small compared with input and output currents, being the difference between the two currents. Thus, the cross-section of this part of the winding may be decreased, resulting considerable savings. Although the iron area is unchanged, since the voltages are unchanged (V=Ndφ/dt=kNBAf), the core window area, hence core length, can be decreased because of the copper area saving. Using smaller quantities of iron and copper results in lower losses and increased efficiency. ηT I2

V1

Im

Rcore

Lmag

In figure 26.27, auto-transformer output side resistance R2 and reactance X2 transfer to the input according to: 2

Req autoX = R1 + 

2

X eq autoX

 1  = X1 +  − 1 X 2  ηT 

These equations show that the impedance transferred for the autotransformer is less than for the conventional two winding transformer. Thus in the case of an autotransformer, the short circuit impedance is lower. Having a smaller value of short circuit impedance is considered a disadvantage, since the short circuit currents are larger. But the full load regulation is lower (better). The autotransformer short circuit low voltage compared to a transformer is: V Z autoX  1  = 1 −  ηT  V Z Xfm 

Advantages of the auto-transformer • A saving in winding material (less copper or aluminium), since the secondary winding is part of the primary. Smaller volume, hence lower weight. • Lower copper loss, lower I2R losses, therefore efficiency is higher than in the two winding transformer. • Lower leakage reactances, lower magnetising current. • Variable output voltage can be obtained. • Lower %voltage regulation. Disadvantages of the auto-transformer • There is a direct electrical connection between the primary and secondary sides. No electrical isolation. • Should an open-circuit develop across the common winding portion, the full supply voltage is applied to the secondary. • The short-circuit current is much larger than for the normal two-winding transformer.

A variable autotransformer is known as a variac. A variac is a single coil with a sweeping arm for the tap-off, which allows the ratio of primary turns:secondary turns to be readily altered.

Equivalent circuit

 − 1  R2  ηT 

(26.109)

X2

The Korndorfer system presented in chapter 13.4.6ii, is a frequently applied solution when starting up asynchronous motors. The start-up takes place in two stages without voltage-free interruptions.

V2 / ηT

Figure 26.27. Autotransformer equivalent circuit.

 1

ηT

2

Autotransformers are used in electromagnetic systems for connecting networks with different voltage levels, in start-up systems for large squirrel-cage induction motors, and where primary and secondary circuits with galvanic non-isolation is permissible, and where lower weight and losses out weigh the expenditure associated with limiting the short circuit current.

Req Cu Leq leak

Io Ic

1

A second autotransformers disadvantage concerns the galvanic (electrical non-isolated) connection of the primary and secondary circuits, due to which, all disturbances, over-voltages, etc. are transmitted directly through conduction between the input and output sides.

T

Generally the copper saving is 1/ ηT±1 where the positive sign is applicable to a voltage step-up connection, while the negative sign implies voltage step-down (with cumulative windings, as opposed to subtractive connection, in each case).

I1

ηT

where: VZ autoX,VZ Xfm are auto-transformer and transformer short circuits voltage respectively.

The pu copper saving for the step down autotransformer is ηT, where ηT ≤ 1. Generally, for cumulatively connected autotransformer windings: copper in auto-transformer 1 = 1 − ±1 ηT copper in two winding transformer

1220

The two winding transformer equivalent equations are 1 Req Xfm = R1 + 2 R2

X eq Xfm = X 1 +

copper in two winding transformer = k (N 1I 1 + N 2I 2 ) = 2kN 1I 1

For the step-down autotransformer in figure 26.26c: N ( I − ηT I 2 ) + (N 1 − N 2 ) ηT I 2 2N 2I 2 (1 − ηT copper in auto-transformer = 2 2 = N 1I 1 + N 2 I 2 copper in two winding transformer 2N 2I 2


(26.108)

Power Electronics

1221

Chapter 26


1222

26.10 Appendix: Technical data for Iron, nickel, and cobalt applicable to power applications

2

100

N/mm

Vickers hardness HV15

8000

N/mm2

Breakage modulus

80-120 -3

N/mm N/mm

2

Thermal conductivity

4 - 7× 10

J/mm s K (W/mm/K)

Linear expansion coefficient

7-10×10-6

/K

Specific heat

0.75

J/g K

Density

4-5

g/cm (4 per cent Si, 7.63 g/cm )

Porosity

5

%

Poisson ratio

0.28

pu

ρ Ω cm 105 1

λs =

∆

nanocrystalline

(T)

1kHz

25°C 1 W/kg = 7.35 mW/cm3

100%

1 MHz

100 MHz

300 MHz

30/1

15/1

12/1

11/0.97

11/0.95

-

-

3

3

140×10 /1 50×10 /0.95 30×10 /0.65

* Magnetostriction, at saturation, contraction. ¶ Dielectric constant, εr → 10-20 at high frequency. § Resistivity normalised at low frequency.

B

Ferrite

1

(T)

(a)

(b)

(c)

(d)

nano crystalline

10

30

50

70

10

90

110

temperature °C

-50%

130

Bs ferrite

µ

∧

B Hs

#1

#2

T T A/m

25°C 25°C 100°C Bs, 25°C

2500±20% 0.48 0.37 Bs = 0.4T : 200

2200±25% 0.54 0.45 Bs = 0.5T : 200

25°C 100°C Rev temp coeff

1600 12/0.18 9.6/0.11 -0.11/-0.2

13/0.17 6.5/0.06 -0.11/-0.2

A/m

H Hc /Br α/β

A/m

/T

%/°C

ferrite

10

alloy

grain size

saturation flux density

saturation magnetostriction

°C

> 200

> 250

d

Bs

λs

ρ

Ω cm

100

700

nm

T

10

η B*

mT-1 × 10-6 g/cm3

fc

MHz * - Maximum hysteresis coefficient 10 G (gauss) = 1 mT (milliTesla) 10 e = 80A/m

10 kHz 25°C

3

10

100

1000 f

10000

(kHz)

Figure 26.28. Typical Fe-Si nanocrystalline material characteristics: (a) core losses; (b) B-H curves; (c) temperature dependence; and (d) permeability dependence on frequency.

Tc

Density

nanocrystalline

4

frequency

Test condition

10000 A/m

µi = 85,000

5

1

Unit

µi

1000 H

µi = 25,000 10

Appendix: Technical data for a ferrite applicable to power applications Symbol

100

µi = 50,000

0 -10

10 field intensity

µ and Bs

50%

-100%

26.9

FeNi 80%

½

1 flux density

100 kHz

FeSi

0 0.1

10 kHz

1 FeNi 50%

0.1

3

ε r¶ / ρ § ( pu )

3

10kHz

0.01

3

*

×10-16 -18 -1.5

1

µi

Resistivity

Nanocrystalline Fe-Si-B-Nb-Co Alloy

10

pu

150,000

1½

20kHz

initial permeability

Modulus of elasticity

2

50kHz

ferrite

N/mm

Resistance to compression

50kHz 20kHz

100

B

40

2

flux density

N/mm2

Pc

Flexural strength

20

core power losses

Tensile strength

W/kg

Appendix: Soft ferrite general technical data

% change permeability and flux density

26.8

-6

coercivity

initial permeability

Hc

µi

A/m

electrical resistivity

ribbon thickness

ρ

Pc

t

µΩcm

W/kg

µm

0.2T 100kHz

@ 1 kHz

0.9

core losses

4.8

4.9

Fe73.5Si15.5

14

1.23

0

0.4

100,000

115

35

21

1.8

1.6

Fe84Nb7B9

9

1.49

0.1

8

22,000

58

76

22

Fe86Cu1Zr7B6

10

1.52

0

3.2

48,000

56

116

20

Fe91Zr7B3

17

1.63

-1.1

5.6

22,000

44

80

18

Co68Fe4(MoSiB)28

amorphous

0.55

0

0.3

150,000

135

35

23

Fe76(SiB)24

amorphous

1.45

32

3

8,000

135

50

23

80% Ni-Fe

100,000

0.75

1

0.5

100,000

55

90

50

50% Ni-Fe

100,000

1.55

25

5

40,000

45

200

70

Power Electronics

1223

26.11

Chapter 26


1224

Appendix: Cylindrical inductor design

Figures 26.29a and b show cross-sectional views of single-layer and multi-layer cylindrical inductors. The inductance of a single-layer cylindrical inductor (all dimensions are in mm) is given by µeff r 2 N 2 L= (µH) (26.110) 228.6r + 254 while if the insulation spacing between the single layer turns are accounted for, inductance is given by 2

L= 3

b r

µeff N 1.3 (d + d w )

1.7

(nH) (26.111) 0.7 +S ) where the bare wire diameter is dw and S is the spacing between turns, all in mm.

(d w

For the multi-layer cylindrical inductor shown in figure 26.29b, inductance is given by µeff r 2 N 2 L= (µH) 152.4r + 228.6 + 254b

(c) start

3

4

2

5

11

1

6

12 finish

10

turns to minimise capacitance

(26.112)

Figure 26.29d shows a family of curves used to give the effective permeability from the former l /d ratio and the core material permeability. These curves are applicable to the single-layer inductor but are a fair approximation of the multi-layer inductor. The winding is assumed to be closely wound over 95 per cent of the core length. The inductance of a flat spiral air-core coil as shown in figure 26.29c is virtually independent of any axial core and is given by

L=

r 2N 2 203r + 279b

(mH)

(26.113)

For inductance levels below 100 µH, an air core strip wound inductor as shown in figure 26.29e, has an inductance approximated by r2 N 2 L= (µH) (26.114) l b  + 2r  225r + 250 + 250b + 82.5   r  + 4r  A toroidal core with a circular cross section has inductance given by

L = µo µeff

r 2N 2 D

(H)

(26.115)

(e)

(d) Figure 26.29. Cylindrical inductors: (a) single-layer coil; (b) multi-layer coil; (c) coil layer; (d) effective permeability for different aspect ratios, l/d; and (e) core strip wound air core inductor.

where r is the radius of the coil winding and D is the overall diameter of the toroid, all in metres. Inductor design using these equations may require an iterative solution. Always attempt to maximise the winding surface area ( S A ≈ π ( d + 2b ) ) for better cooling.

Example 26.8: Wound strip air core inductor An air core inductance of 50 µH is made as a wound strip of copper, 40 mm wide and 1.5 mm thick. For cooling purposes, ½ mm spacing is used between each turn with an inner diameter of 60 mm and an outer diameter of 160 mm as physical constraints: Can the required inductance be achieved? Solution First calculate the parameters shown in figure 26.29e. r = ¼ ( d o + d i ) = ¼ × (160 + 60 ) = 55 mm b = ¼ ( d o − di ) = ¼ × (160 − 60 ) = 25 mm

= 40 mm b 50 N= = = 25 turns tCu + tair 1.5 + 0.5 Substitution of the appropriate parameters values into equation (26.114) yields L = 51.6 µH.

♣

Example 26.9: Multi-layer air core inductor An air core inductor is to have the same dimensions as the inductor in example 26.8. The same conductor area (40 mm × 1.5 mm) but circular in cross-section and number of turns is to be used. Calculate the inductance. If a ferrite solid cylindrical core 42 mm long and 60 mm in diameter with a relative permeability of 25 is inserted, what will the inductance increase to? Solution From example 26.8 r = 55 mm ℓ = 40 mm b = 50mm N = 25 Substitution of these parameter values into equation (26.112) yields 62.5 µH. From figure 26.29c, ℓ / d = 40/60 = 0.66, whence µeff ≈ 3. That is, with a cylindrical core inserted, a three fold increase in inductance would be expected (188 µH). The use of end-caps and an outer magnetic sleeve would increase inductance, but importantly also help to contain the external magnetic field.

♣

Power Electronics

1225

26.12

26.13

Chapter 26


1226

Appendix: Copper wire design data Nominal wire diameter d

Outer diameter Approximate enamelled dc resistance grade 2 at 20°C

Bare copper Fusing weight current

mm

mm

Ω/m

gm/m

A

0.1

0.129

2.195

0.070

2.5

0.2

0.245

0.5488

0.279

7

0.376

0.462

0.136

1.117

18 27.5

0.5

0.569

8.781 × 10-2

1.746

0.6

0.674

6.098 × 10-2

2.50

36

0.8

0.885

3.430 × 10-2

4.469

57

0.95

1.041

2.432 × 10-2

6.301

79

1

1.093

2.195 × 10-2

6.982

82

1.5

1.608

9.67 × 10-3

15.71

145

2

2.120

5.44 × 10-3

27.93

225

2.5

2.631

3.48 × 10-3

43.64

310

3

3.142

-3

2.42 × 10

62.84

>

4

4.160

1.36 × 10-3

111.7

>

4.5

4.668

-3

1.08 × 10

141.4

>

5.0

5.177

8.70 × 10-4

174.6

>

Appendix: Minimisation of stray inductance

In many circuit layouts, it is essential to minimise stray and residual inductance. With high di/dt currents during switching, large voltages occur (v = L di/dt) which may impress excessive stresses on devices and components. Stray inductance within a package reduces its usable voltage rating. Stray inductance in the drain circuit of the MOSFET, within the package as shown in figure 4.11, reduces the usable voltage rail while source inductance increases the transient gate voltage. In the case of capacitors, residual inductance reduces the effectiveness of turn-off snubbers and can result in an unintentional resonant circuit. Inductance of a straight wire of length ℓ and radius r is µ  2   2  (H) or L = 0.2  n − ¾  (µ H) L = o  n − ¾ (26.116) 2π  r r    which as a rule of thumb is about 1µH/m. 26.13.1 Reduction in wiring residual inductance Wiring inductance can be decreased by cancelling magnetic fields in a number of ways • coaxial cable • parallel plates • parallel wiring conductors. In each case, the go and return paths are made parallel and physically close. Figure 26.30 shows the per unit length inductance for each wiring method. coaxial cable Minimum inductance results with coaxial cable, which is available for power application. The per unit inductance and capacitance are given by µµ r L= o r n o (H/m) ri 2π (26.117) r C = 2πε o ε r / n o (F/m) ri where ri is the inner radius and ro the outer radius (ri < ro).

Figure 26.30. Relative inductance of go and return wiring conductors.

parallel plates Very low inductance can be achieved by using parallel conducting copper plates separated by a thin insulation layer (µr ≈ 1). The inductance per unit length, neglecting skin effects, is approximated by d L = µo w (H/m) (26.118) ( w >> d ) where d is the separation of the plates and w is the plate width. The parallel plate capacitance is C = ε oε r w / d (F/m) (26.119) A complete analysis of the laminated parallel bus bar configuration is presented in appendix 26.14 parallel wiring conductors For parallel wiring cylindrical conductors of radius r and separation D, in air, µ µ  D2  D Llo − freq = o n   Lhi − freq = o cosh −1  2 − 1 ( H/m ) ( D > 2r ) 2π π r  2r 

(26.120) 2πε o (F/m) D n  r When the separation D is small over a long distance, ℓ, that is D/ℓ r (26.124) ( H/m ) 4π  r 

A current balancing transformer may be used to equalise the principal currents of two parallel-connected power devices, as shown in figure 10.8. Conventionally each coil is wound on separate legs of the core, resulting in a large leakage inductance. This large leakage inductance can result in high voltage transients, which are to be avoided. Leakage can be significantly decreased if two coils are bifilar wound on each limb and connected as shown in figure 26.31b. The same leakage flux cancelling technique can be used on the centre-tapped, push-pull transformer for the switch mode power supply shown in figure 15.16a. Because of the close proximity of bifilar wound conductors, high inter-winding capacitance and high dielectric fields may be experienced.

Figure 26.30 shows that go and return power cable residual inductance decreases as separation decreases. Physical and mechanical constraints may dictate which wiring technique is most viable. All other wiring should cross perpendicularly, in order to minimise coupling effects. Inductance of other conductor profiles The self-inductance of a rectangular conductor, not associated with a return path in close proximity is µ   2  2 w+t L = o  n (H/m) (26.125) +½ +  2π   w + t  9  When the bus bar and its return path are side-by-side in the same plane µ   D  3 L = o  n (H/m) + 2π   w + t  2  µ  2  D M = o  n   −1+  (H) 2π   D   or long cylindrical wire and its return path are side-by-side in the same plane µ D µ L = wire + n (H/m) r 8π 2π where w is the width of the conductors t is the thickness of the conductors D is the distance between the midpoints of the conductors ℓ is the conductor length.

(26.126)

(26.127)

The first component in equation (26.127) is the internal self-inductance component, which for copper and aluminium, µwire = µo, gives 50nH per metre. 26.13.2 Reduction in component residual inductance 26.13.2i - Capacitors The inductance of a cylindrical capacitor winding, employing extended foils and scooping connections is given by µ  2b  L = o  n r − ¾ (H) (26.128) 2π   where b is the length of the cylinder winding and 2r is its diameter. This equation shows that (undesirable) inductance is decreased by decreasing the length and by increasing the diameter.

Figure 26.31. (a) Parallel connected capacitors, inductance and (b) leakage inductance of a current balancing transformer.

26.13.2ii - Capacitors - parallel connected

26.14

Capacitors are extensively parallel connected, by manufacturers before potting, or by the user after potting, in order to increase capacitance. The low inductance feature of an extended foil, scoop connected capacitor can be obliterated by poor lead connection. Consider the parallel-connected capacitors shown in figure 26.31a, which shows the relative residual wiring inductance for three connections. Minimum inductance results when using a thin, double-sided copper printed circuit board arrangement, such that connections alternated between the top and bottom copper layers (go and return conductors). Cut-outs in the pcb, for the capacitors to fit into, only marginally decrease the inductance.

As shown in figure 26.30, the use of a parallel laminated bus bar arrangement shown in figure 26.32a for go and return paths, results in a low inductance loop. If the gap between the bus bars is laminated with a dielectric material (e.g., polyester, εr = 3.5, 1018Ω insulation resistance, and a dielectric strength of 300kV/mm), distributed capacitance properties are gained. Up to five layers are available. A laminated bus bar arrangement offers the following electrical mechanical and economic features in mitigation to the increased component costs:

Appendix: Laminated bus bar design

Power Electronics

1229

• • • • • • • • • •

Chapter 26

high packing density with good shielding better conductor cooling and thermal distribution because of flat surface area low voltage drop - low impedance high voltage and current capability modular, reliable, and eliminates wiring errors space saving, high packing density, low profile, low weight, and high mechanical strength increased capacitance for better noise suppression low inductance because thin parallel conductors allow flux cancellation low system costs, easy but low service costs, low installation costs applicable to voltages up to and in excess of 1kV

dielectric

busbars

¼R ¼L

¼L ¼R


1230

Skin effect Both the resistance and inductance are affected by the ac skin effect, which is frequency dependant. This was briefly treated in section 26.3.4ii, and specifically equation (26.50). The skin effect is when at high frequencies the current tends to flow on the surface of the conductor. The skin depth δ, from equation (26.50) is δ ( f ) = ρ / µoπ f (26.131) where ρ is the resistivity of the conductor at frequency f and a given temperature. The skin depth for copper and brass are 0.066 0.126 (m) (m) δ Cu = δ Brass = f f As the frequency increases L decreases and R increases.

(26.132)

Inductance, L There two inductive components,

t

supply

d

?ℓ

w

G

¼R ¼L

(a)

dielectric Cu dielectric Cu dielectric

C

load

¼L ¼R (b)

W

creepage (c)

Figure 26.32. Laminated bus bar: (a) parallel planar construction; (b) equivalent circuit distributed components; and (c) cross section showing creepage paths between copper conductors.

The physical bus bar dimensions determine the electrical parameters and characteristics. The two level bus bar comprises two parallel conducting plates of aluminium, brass or copper with resistivity σ, separated by a dielectric, with dielectric constant εr, and permeability µo, giving a conductance G, capacitance C, and resistance R that are uniformly distributed along the bus, as shown in the model in figure 26.32b. Capacitance, C The capacitance C is given by w (F/m) (26.129) d where w is the width of the conductors d is the distance between the bars, which is the dielectric thickness. An increase in capacitance decreases the characteristic impedance, Z o = L / C . Lower impedance gives greater effective signal suppression and noise elimination. This is achieved with • a smaller bar separation, d, • a higher permittivity dielectric material, εr, • wider conductors, w. C = ε oε r

Shunt conductance, G The shunt conductance G depends on the quality of the dielectric, specifically its conductivity at the operating frequency and temperature. 1 w G= ( /m) (26.130) σ d

• •

Lint - inside the conductor due to internal flux linkages, Lext - external inductance between the two conductors due to the orientation of the two conductors carrying current.

In power applications and at the associated frequencies, the external inductance is more dominant. d Lext = µo (H/m) (26.133) w At high frequency (taking the skin effect into account) the effective inductance is d +δ Le = µo (H/m) (26.134) w Thus to decreased inductance

• • •

decrease the dielectric thickness, d increase the conductor width, w decrease the skin depth δ by using a conductor of lower resistivity.

Resistance, R The dc resistance Rdc of the two conductors is 1 (Ω/m) Rdc (20°C) = 2 ρ wt where t is the thickness of the conductors The resistivity of copper and brass at 20°C are 1.7×10-8 and 7.0×10-8 Ωm, respectively. The temperature effects on resistance for copper are accounted for by R To = R 20°C (1 + 0.0043 × (To − 20°C ) ) (Ω)

(26.135)

(26.136)

At high frequency, taking the skin effect into account, assuming that the conductor thickness is at least twice the skin depth, 2 (Ω/m) Rac = 2 ρ (26.137) δw Characteristic impedance, Z The characteristic impedance Z of the go-and-return bus bar arrangement is given by R + jω L (26.138) Z= (Ω) G + jωC When the conductor resistance R and insulation conductance G are negligible L Z= (Ω) (26.139) C This equation illustrates that increasing the capacitance and decreasing the inductance reduces bus bar noise problems. Common to decreased inductance and increased capacitance are • decrease the dielectric thickness d and • increase the bus bar width w • increase permittivity and decrease permeability That is, characteristic impedance Z is proportional to d/w.

Power Electronics

1231

Chapter 26

Figure 26.33 compares the electrical parameters obtained for one metre of twist pair plastic coated 1mm diameter solid copper wire and one metre of laminated bus bar. The copper cross section area is the same in each case, giving a dc resistance of 44mΩ per metre. The most significant electrical factor is the reduction in inductance when a bus bar arrangement is used. Better electrical parameters are gained for a significant cost increase. The propagation delay time is approximately t pd = 0.04 × C × Z

(ps/mm)

(26.140)

R●=1500mΩ 10

3

L●=870mH C■=770pF

C■=730pF

L●

per

m 10

R■=810mΩ

C■

R●

L■=330mH

L●=590mH

R■

Paramagnetic: Ordering magnetic particles are unpaired electrons (spins). The magnetic moments tend to be randomly orientated due to thermal fluctuations when there is no magnetic field. They are ordered in one direction under external magnetic field such that magnetisation of the material is proportional to the applied field. Materials exhibit magnetization reinforcing (parallel, therefore - para) to the applied magnetic field. Magnetic field is strengthened in a material. Weak attracting effect to the magnetic field. Magnetization disappears when the field is removed. Example - aluminium metal (Al). Ferromagnetic: Ordering magnetic particles are unpaired electrons (spins). They are ordered in one direction under external magnetic field. Below Curie point, ferromagnets exhibit magnetization without of any external magnetic field (spontaneous magnetization) due to self-ordering of spins. Exhibit reinforcing magnetization to the applied magnetic field that usually remains when the field is removed (field-induced magnetization). Magnetic field is strengthened in a material. Strong attracting effect to the magnetic field. In the periodic table of elements only Fe, Co and Ni are ferromagnetic at and above room temperature. As ferromagnetic materials are heated then the thermal agitation of the atoms means that the degree of alignment of the atomic magnetic moments decreases and hence the saturation magnetisation also decreases. Eventually the thermal agitation becomes so great that the material becomes paramagnetic; the temperature of this transition is the Curie temperature, TC (Fe: TC =770°C, Co: TC =1131°C and Ni: TC =358°C). Example - iron metal (Fe).

L■

magnetism

L■=67mH

C●

C●=57pF

R●■=44mΩ

3

molecular: Inorganic compounds organic or organmetallic compounds and complexes

1

10

4

5

10

6

10

10

7

10

f

Traditional-atomic inorganic compounds

(Hz)

frequency

single molecule magnets (SMMs):

Figure 26.33. Comparison between electrical parameters for a twisted pair and a laminated bus bar, each with the same copper cross sectional area, that is, the same dc resistance.

26.15

1232

2

C●=57pF

10


0D: polynuclear metal complexes and clusters 1D: single chain magnets Spin rings

nanostructures magnets: 1D-magnets chained 2D-magnets plain

bulk magnets 3D

Appendix: Insulating material for between bus bar conductors

If the busbar is to be edge filled, epoxy glass is recommended for the top and bottom insulators. If it is to be sealed by pinching off the insulation, Nomex type materials are recommended. Material Mylar Epoxy glass

Minimum thickness

K-factor

Dielectric strength

mil

pu

kV/mil

2

3.3

7.5

2.5

4.3

0.5

Kapton

1

3.8

4.6

Nomex

3

2.6

0.5

conventional magnetic material Paramagnetic Ferromagnetic Antiferromagnetic Ferrimagnetic

multifunctional magnetic material light, pressure temperature properties

dual-function magnetic material Independent properties, electrical conductivity

spin-crossover compounds Prussian blue analogues Cyanide bridged clusters Chiral magnets

spin-crossover compounds molecular metallic conductivity magnetic molecular semiconductor magnetooptic materials

26.16

Appendix: Materials by types of magnetization

Diamagnetic: Ordering magnetic particles are electron pairs or magnetic nuclei. They are ordered in one direction under external magnetic field. Materials exhibit magnetization opposing to the applied magnetic field. Magnetic field is weakened in a material. Weak repelling effect to the magnetic field. The value of susceptibility is independent of temperature. Magnetization disappears when the field is removed. Example - most objects around - wood.

Figure 26.34. Classification of magnetic materials.

Antiferromagnetic: Ordering magnetic particles are unpaired electrons (spins). In contrast to paramagnetic and ferromagnetic, they are ordered in opposite directions in equal quantities under the action of magnetic field and since the field cancels out, the material appears to behave in the same way as a paramagnetic material. The ordering usually remains when the field is removed. Like ferromagnetic materials these materials become paramagnetic above a transition temperature, known as the Néel

1233

Power Electronics

Chapter 26


1234

temperature, TC. (Cr: TN = 37ºC). Below Neel point, self-ordering can be observed. Magnetic field is weakened in a material. Weak repelling effect to the magnetic field. In the periodic table the only element exhibiting antiferromagnetism at room temperature is chromium. Example - nickel oxide (Ni0). Ferrimagnetic: Ferrimagnetism is only observed in compounds, which have more complex crystal structures than pure elements. Ordering magnetic particles are unpaired electrons (spins). They are ordered in opposite directions in unequal quantities/sizes under the action of magnetic field. Behave as weak ferromagnets. Magnetic field is strengthened in a material. Weak to strong attracting effect to the magnetic field. Example - magnetite (Fe304).

Reading list cda.org.uk (copper development agency) EPCOS Ferrite design tool www.epcos.com

Metamagnetic: Materials that can change their magnetic properties depending on the strength of applied magnetic field. For example, paramagnets transform to ferromagnets or vice versa when the field is increased or reduced.

McLyman, W. T., Transformer and Inductor Design Handbook, Marcel Dekker Inc., 1978.

Magnetic materials - structural types Figure 26.34 classifies development in both inorganic and organic magnetic materials Relatively recently, the science of so-called molecular magnetism branched out from traditional magnetism that explored mainly magnetic behaviour of compounds at the level of atoms (in metals). Molecular magnetism researches magnetic behaviour of molecules rather than atoms. Magnetic behaviour of organic compounds belongs to the field of molecular magnetism. Molecules as well as atoms may form bulk magnets (traditional type of magnets), that are also known as 3D magnets. At the same time, two new types of molecular magnets recently evolved: single molecule magnets (SMMs) and nanostructured magnets. SMMs are fully functional magnets on a molecular level. They possess some unique properties, such as quantum tunnelling of magnetization. SMMs include: polynuclear metal complexes and clusters, singlechain magnets, spin rings and some others. Nanostructured magnets built of self-organized or self-assembled crystallites. They may possess many unique properties in addition to magnetic ones, (such as anisotropy, transparency, electrical conductance, porosity etc.). Low dimensionality (0D, 1D, 2D) is characteristic of self-aggregated molecular magnets. Bulk molecular (and atomic) magnets usually contain materials that may be either paramagnetic, ferromagnetic, anti-ferromagnetic, or ferrimagnetic. Recently, a new type of molecular magnetic materials evolved, that may change magnetic properties under the action of different external factors, such as light, temperature, pressure, etc. They are known as multifunctional magnetic materials, which include so-called spin-crossover compounds, Prussian Blue analogues, cyanide-bridged clusters, chiral magnets. The other type of new functional molecular magnetic materials are dual-function materials. They possess one or more independent physical properties in addition to magnetic properties, such as electrical conductivity, porosity, or optical properties. Magnetic molecular conductors are the most widely studied organic materials of this type.

Snelling, E. C., Soft Ferrites, CRC Press, Cleveland, Ohio, 1969. Manufacturers Data Handbooks, Catalogues, and www Siemens Thomson CSF SEI Telmag Magnetics Inc (mag-inc.com) Krystinel Corp Ferroxcube Inc Arnold Eng. Co. Pyroferric Inc Fuji Hitachi Metals

http://www.hitachi-metals.co.jp/e/

Vacuumschmelze

http://www.vacuumschmelze.de/dynamic/en/

Mecagis

http://www.mecagis.com/index.php

Magnetec

http://www.magnetec.de/magnetec.htm

Philips Neosid Stackpole Micrometals Co. Fair-rite

Problems 26.1.

Rework example 26.7, taking Br = 0.18 T into account.

26.2.

Rework example 26.7, when the core temperature is 100°C.

26.3.

Rework example 26.3 when Ve = 7.3 × 10-6 m3 Ae = 66 mm2 ℓe = 110 mm c = 0.75 nH What are the effects of decreasing the core volume for a given L and I? 3 [10A: 274 J/m , 0.53 mm, 1200 A/m, 13 turns; 20A: 2360 A/m, µe = 185]

26.4.

Show that the maximum flux density for a square-wave-excited transformer is given by V B= 4 NAf

26.5.

A 2:1 step-down transformer with an effective area of 10 cm2 is driven from a 240V, 1kHz square-wave source. The transformer has 240 primary turns and magnetising inductance of 10mH. i. Calculate the maximum flux density. ii. Calculate the peak primary current when the secondary is loaded with a 5 Ω resistor. Sketch the primary and secondary current waveforms. [0.25 T, 30 A]

Hard magnetic materials

Chapter 27

1236

Table 27.1. Magnetic behaviour of five different types of materials (µr = χ+1, B=µo(H+M)=(1+χ)µoH=µrµoH) Type of Magnetism Susceptibility

27

Small and negative χ0 M= χ H 1/χ(T) linear (weak)

-166 x10-6 Bi Au -34.7x10-6 -6 Cu -9.63x10 H2O -9.2x10-6 -6 SiO2 -6.2x10 CaCO3 -4.8x10-6

when H=0, B=0 Atoms have no magnetic moment

χ

Χ = slope < 0

No temperature dependence

Small and positive

Example/ Susceptibility χ

Atomic (H=0) / Magnetic Behaviour M(H)

Χ = constant

Atoms have randomly oriented magnetic moments

Super Con- ≈105 ductor

T

Χ=slope 1/χ T α 1/Χ

Aℓ β-Sn Pt Mn Air O2

21.1x10-6 -6 22.7x10 257x10-6 -6 904x10 0.36x10-6 -6 2.1x10

Fe Ni Co

~80,000

SiFe

7x10

T

All materials can be classified in terms of their magnetic behaviour, falling into one of five categories depending on their bulk magnetic susceptibility (permeability). The two most common types of magnetism are diamagnetism and paramagnetism, which account for the magnetic properties of most of the periodic table of elements at room temperature, as indicated in figure 27.1. The diamagnetic elements are usually referred to as non-magnetic, while those that are referred to as magnetic are classified as ferromagnetic. The only other type of magnetism observed in pure elements at room temperature is antiferromagnetism, Cr. Magnetic materials (as opposed to elements) can also be classified as ferrimagnetic although this is not observed in any pure element but is found in compounds, such as the mixed oxides, known as ferrites, from which ferrimagnetism derives its name. Magnetic susceptible falls into a particular range of values for each of the five material types as shown in Table 27.1, with some examples, with the five categories shown in figure 27.2.

Ferromagnetism

Large and positive, function of applied field, microstructure dependent

Atoms have parallel aligned magnetic moments

χ

χ >0, |χ| » 1

Small and positive χ >0

transition elements

Atoms have mixed parallel and antiparallel aligned magnetic moments

Cr 318x10-6 FeMn NiO MnO

1/χ TNėel Antiferromagnetism

Rare earth elements 64

Ferrimagnetism

Large and positive, function of applied field, microstructure dependent

Atoms have anti-parallel aligned magnetic moments

paramagnetism

T

~3000 Baferrite 1/χ

Fe3O4 100

TNėel

χ»1 Figure 27.1. Periodic table, classifying the type of magnetic behaviour of each element at room temperature.

BWW

4

paramagnetism

T

Antiferromagnetism

Gd

1/χ

TCurie

T

Power Electronics

1237

Chapter 27

i. Diamagnetism Diamagnetic metals have a weak, negative susceptibility to magnetic fields. In a diamagnetic material, there are no unpaired electrons and all the orbital shells are filled, hence no net magnetic moment. The intrinsic electron magnetic moments cannot produce any bulk effect, thus magnetization arises from electron orbital motion. Under the influence of an applied field, H, the spinning electrons precess and this motion, which is a type of electric current, produces a weak internal magnetisation, M (= χH = (µr - 1) ×H = J / µo), that opposes the externally applied magnetic field, thus causing a repulsive effect. The cause of this interaction is in accordance with Lenz's Law by which small, localized currents generated in the material created magnetic fields in opposition to the applied changing field. All materials have a diamagnetic effect, which is often masked by a larger paramagnetic or ferromagnetic component. Although diamagnetism is generally a weak effect in most materials, superconductors exhibit a strong effect, thus repel magnetic fields from their bulk. The dimensionless volumetric susceptibility value χ (µr = χ+1) is independent of temperature. Most elements in the periodic table, including copper, silver, gold, and helium are diamagnetic. The strongest diamagnetic elements are bismuth and carbon graphite, as highlighted in Table 27.1.

i.

ii.

iii.

iv.

v.

Figure 27.2. Types of natural magnetism.

ii. Paramagnetism Paramagnetic metals have a small, positive susceptibility to magnetic fields. They become magnetized in the same direction as the applied magnetic field and the magnetization magnitude is proportional to the applied magnetic field. In a paramagnetic material there are unpaired electrons, specifically, atomic or molecular orbitals with exactly one electron in them. While paired electrons are required by the Pauli exclusion principle to have their intrinsic (spin) magnetic moments pointing in opposite directions, causing their magnetic fields to cancel out, an unpaired electron is free to align its magnetic moment in any direction. When an external magnetic field, H, is applied, these magnetic moments tend to align in the same direction as the applied field, thus reinforcing it. Paramagnetic materials are attracted to magnetic fields, hence have a relative magnetic permeability slightly greater than one (that is, a positive magnetic susceptibility, χ). The force of attraction generated by the applied field is linear and weak. Unlike ferromagnets, paramagnets do not retain any magnetization in the absence of an externally applied magnetic field, because thermal motion causes the spins to return to a random orientation. Thus the total magnetization drops to zero when the applied field is removed. Even in the presence of a H field, the induced magnetization is small because only a small fraction of the spins are oriented by the field. This small fraction is linearly proportional to the field strength, H. The randomly oriented moments result from thermal agitation. A magnetic field slightly aligns these moments whence low magnetisation results, aligned with the applied field. As the temperature increases, the thermal agitation increases and it becomes harder to align the atomic magnetic moments, hence the magnetic susceptibility, χ, decreases. This behaviour is known as the Curie law, as is shown in equation (27.1), where C is a material-specific constant called the Curie constant.

M =H ×χ =H ×

C T

(= H × (µ

r

− 1) )

(27.1)


1238

M is the resultant magnetism (with reference to the permeability of a vacuum), T is absolute temperature, K, and H is the externally produced magnetic field, A/m. This law indicates that the susceptibility χ of paramagnetic materials is inversely proportional to temperature. Curie's law is only valid under conditions of low magnetisation, since it does not consider magnetisation saturation that occurs when the atomic dipoles are all aligned in parallel. After complete alignment, increasing the external field will not increase the total magnetisation since there can be no further alignment. However, such saturation typically requires extremely strong magnetic fields. The Curie law is a special case of the more general Curie-Weiss law, equation (27.2), which incorporates a temperature constant, TC, and derives from Weiss theory, proposed for ferromagnetic materials, that incorporates the interaction between magnetic moments.

χ=

C T − TC

(27.2)

In equation (27.2), TC , in degrees Kelvin, K, can be positive, negative or zero. When TC = 0, the CurieWeiss law equates to the Curie law. A non-zero TC indicates that there is interaction between neighbouring magnetic moments and the material is only paramagnetic above a certain transition temperature. If TC is positive then the material is ferromagnetic below the transition temperature and the value of TC corresponds to the transition temperature, the Curie temperature, TC. If TC is negative then the material is antiferromagnetic below the transition temperature, the Néel temperature, TN, however the value of TC does not relate to TN. Equation (27.2) is only valid for a paramagnetic material state and is not valid for many metals, as the electrons contributing to the magnetic moment are not localised. However, the law does apply to some metals, for example, the rare-earth elements shown in figure 27.1, where the 4f electrons, that create the magnetic moment, are closely bound. Paramagnetic materials include magnesium, molybdenum, lithium, sodium, and tantalum. Paramagnetic materials like aluminium, uranium and platinum become more magnetic when they are very cold. iii. Ferromagnetism Ferromagnetic materials have a large positive susceptibility to an external magnetic field. Ferromagnetism is the term for the basic mechanism by which specific materials (such as iron) form permanent magnets and/or exhibit strong magnetic interaction with magnets. A paramagnetic substance has unpaired electrons, but additionally ferromagnetism is only possible when atoms are arranged in a lattice and the atomic magnetic moments can interact to align parallel to each other. The effect is due to the presence of a molecular field within the ferromagnetic material, which is sufficient to magnetise the material to saturation. This creates a net internal magnetic field much greater than the applied field. Even when the applied external field is removed, the electrons in the material maintain each other orientated in the same direction. Magnetic domains within the material are the regions of atomic magnetic moments that are aligned. The movement of these domains determines how the material responds to a magnetic field and consequently the susceptible is a function of the applied magnetic field. Therefore, ferromagnetic materials are usually compared in terms of saturation magnetisation (magnetisation when all domains are aligned) rather than susceptibility. In the elemental periodic table, only the three consecutive elements Fe, Co and Ni are ferromagnetic at and above room temperature. As ferromagnetic materials are heated, thermal agitation of the atoms decreases the degree of alignment of the atomic magnetic moments, hence saturation magnetisation decreases. Eventually the thermally agitated disorder overwhelms the energy lowering due to ferromagnetic order and the material becomes paramagnetic; the temperature of this critical transition is the Curie temperature, TC (Fe: TC = 770°C, Co: TC = 1131°C and Ni: TC = 358°C). Above TC, susceptibility varies according to equation (27.2). iv. Antiferromagnetism Antiferromagnetic materials are similar to ferromagnetic materials but the exchange interaction between valance electrons of neighbouring atoms leads to the anti-parallel alignment (as opposed to parallel alignment) of the atomic magnetic moments. Therefore the magnetic field cancels out and the material appears to behave like a paramagnetic material. It is difficult to magnetize such materials in the direction of the applied field but they still demonstrate a relative permeability slightly greater than 1. The magnetic susceptibility of an antiferromagnetic material is typically a maximum at the Néel temperature. Like ferromagnetic materials, these materials become paramagnetic above a transition temperature, the Néel temperature, TN, where equation (27.2) is applicable. The Néel temperature is similar to the Curie temperature in ferromagnetism. In the periodic table, the only element exhibiting antiferromagnetism at near room temperature is chromium (Cr: TN = 37ºC). Alloys such as iron manganese (FeMn), and oxides such as nickel oxide (NiO), manganese oxide, and iron oxide (FeO), exhibit antiferromagnetism.

Power Electronics

1239


Chapter 27

1240

5

Tesla

ferromagnetic, χ ≈ 10 , µ >> µo Fe3O4, NiFe2O4

Magnetic flux density

B

ferrimagnetic, χ ≈ 104, µ >> µo Ferrite, Co, Ni, Gd

Paramagnetic, χ ≈ 10-4 , µ > µo Al, Cr, Mo, Na, Ti, Zr Vacuum χ=0, µo Diamagnetic, χ ≈ -10-5, µ < µo Al2O3, Cu, Au, Si, Ag, Zn Applied magnetic field strength

H

A-turns/m

Figure 27.3. Relative susceptibility χ (= µr - 1) of different materials. v. Ferrimagnetism Ferrimagnetism is only observed in compounds that have more complex crystal structures than pure elements. Within such materials, the exchange interactions lead to parallel alignment of atoms in some of the crystal sites and anti-parallel alignment of others. The material devolves into magnetic domains, just like a ferromagnetic material and the magnetic behaviour is also similar, although ferrimagnetic materials usually have lower saturation magnetisations. In an optimal geometrical arrangement, there are more magnetic moments from the sublattices of electrons which point in one direction, than from the sublattices which points in the opposite direction. Both ferrimagnetic and ferromagnetic materials retains spontaneous magnetization below the Curie temperature, and show no magnetic order (are paramagnetic) above this temperature. However, there may be a temperature below the Curie temperature at which the two sub-lattices have equal (but opposite polarity) moments, resulting in a net magnetic moment of zero; this is called the magnetization compensation point. Examples of ferrimagnetic materials are iron oxide (Fe3O4) and ferrite.

Temperature dependant anisotropy is caused by a coupling of the electron orbitals to the lattice, and in the easy direction of magnetisation, this coupling creates orbitals in the lowest energy state. The easy direction of magnetisation for a permanent magnet, based on ferrite or the rare earth alloys, is uniaxial. However, it is also possible to have materials with multiple easy axes or where the easy direction can lie anywhere on a certain plane or cone surface. The fact that a permanent magnet has uniaxial anisotropy means that it is difficult to demagnetise since it is resistant to rotation from the magnetisation direction. When no preferred crystallographic direction exists within a material, shape anisotropy may arise if there are non-spherical particles present within the material. The long axis of such particles is the preferred axis of magnetization, as with Alnico magnets. In addition to magnetocrystalline anisotropy, there is another effect related to spin-orbit coupling called stress anisotropy or magnetostriction. Magnetostriction (which is temperature dependant) arises from the strain dependence of the anisotropy constants. Upon magnetization, a previously demagnetized crystal experiences a strain that can be measured as a function of the applied field along the principal crystallographic axes. A magnetic material will therefore change its dimension when magnetized. The inverse affect or magnetization change with stress, also occurs. A uniaxial stress can produce a unique easy axis of magnetization if the stress is sufficient to overcome all other anisotropies. The third type of anisotropy is due to the shape of a grain. A magnetized body will produce magnetic charges or poles at its surface. This surface charge distribution, acting in isolation, is itself a magnetic field source, and is a demagnetizing field, opposing the magnetization that produced it. Anisotropy is temperature dependent, decreasing and vanishing at the Currie temperature. Table 27.2. The saturation polarisation, BS, and Curie temperature, TC, of a range of magnetic materials.

Material

Fe

The different magnetic types are summarised in figure 27.3 in terms of relative susceptibility. There are other types of magnetism, such as spin glass, superparamagnetism, superdiamagnetism, and metamagnetism. 27.1

Magnetic properties

The intrinsic properties of a magnetic material are those properties that are characteristic of the material and are unaffected by the microstructure (for example, grain size or crystal orientation of grains). These properties include Curie temperature, saturation magnetisation, and magneto-crystalline anisotropy. i. Saturation Magnetisation Saturation magnetisation, MS, is a measure of the maximum field that can be generated by a material. It depends on the strength of the dipole moments on the atoms that make up the material and how densely they are packed. The atomic dipole moment is affected by the nature of the atom and the overall electronic structure within the compound. The packing density of the atomic moments are determined by the crystal structure (that is, the spacing of the moments) and the presence of any nonmagnetic elements within the structure. For ferromagnetic materials, MS also depends on how well the moments are aligned, as thermal vibration of the atoms causes moment misalignment and a reduction in MS. For ferrimagnetic materials not all of the moments align parallel, even at zero degree Kelvin, hence MS depends on the relative alignment of the moments as well as the temperature. In the case of a single magnetic domain, its saturation magnetisation is referred to as the spontaneous magnetisation. Table 27.2 gives examples of the saturation polarisation, JS, (=µoMS) and Curie temperature, TC, of commonly used magnetic materials. ii. Magnetic Anisotropy In a crystalline magnetic material, magnetic properties vary depending on the crystallographic direction in which the magnetic dipoles are aligned. A measure of magnetocrystalline anisotropy in the easy direction of magnetisation, is the anisotropy field, Ha, which is the field required to rotate all the moments by 90° in a saturated single crystal.

27.2

Magnetic Structure Ferro

JS at 298K

TC

reversible coefficient

JS = µoMS

Curie temperature

α (Br)

β (Hci)

Tesla

ºC

%/ºC

%/ºC

2.15

770 1121

Co

Ferro

1.80

Ni

Ferro

0.62

368

Alnico 5/8

Ferro

1.08/0.80

900/860

-0.02

-0.03

Nd2Fe14B

Ferro

1.59

312

-0.11

-0.060

SmCo5

Ferro

1.14

720

-0.04

-0.3

Sm2Co17

Ferro

1.25

820

-0.03

-0.3

FeCrCo

Ferro

1.35

630

-0.03

-0.04

Fe, 3wt% Si

Ferro

2.00

740

Fe, 35wt% Co

Ferro

2.43

940

Fe, 78wt% Ni

Ferro

0.70

580

Fe 50wt% Ni

Ferro

1.55

500

Ba0.6Fe2O3

Ferri

0.48

450

-0.19

0.40

Sr0.6Fe2O3

Ferri

0.48

450

-0.19

0.40

MnO-Fe2O3

Ferri

0.51

300

-0.19

0.40

Classification of magnetic materials

Magnetic materials can be classified as either hard or soft. Magnetically soft materials can be readily magnetized, but the magnetism induced is only temporary. An alloy of iron with 4% silicon is used to make the cores of electromagnets and transformers. Stroking a magnet along a steel pin from one end to the other will weakly magnetize the steel pin. This is because large numbers of iron atoms (domains) of the steel become aligned in the same direction. Such materials typically have an intrinsic coercivity of less than 1000Am-1 and are primarily used to enhance and/or channel the flux produced by an electric current. A parameter often used as a figure of merit for soft magnetic materials is the relative permeability, µr, where µr = B/µoH, which is a measure of how readily the material responds to an applied magnetic field, H. Other important parameters are coercivity, saturation magnetisation, and electrical conductivity, plus as small hysteresis loop area.

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Chapter 27

Magnetically hard materials can be permanently magnetized by a strong magnetic field. Steel and special alloys, which contain various amounts of aluminium, nickel, cobalt, and copper, are used to make permanent magnets. Its magnetic properties are due to its atomic structure. The electrons in the outer orbit of an iron atom behave as an electric charge and produce a strong magnetic field. In magnetized iron, millions of individual iron atoms, called a domain, are aligned in the same direction. Each domain has a north and a south (seeking) pole. Iron is an example of a natural hard magnetic material. The strongest energy permanent magnets are NdFeB, made in a vacuum and at high temperature from powders of various alloy grains. Hard magnets, also referred to as permanent magnets, are of magnetic materials that retain their magnetism after being magnetised, when the inducing field energy source has been removed. Practically, this occurs with materials that have an intrinsic coercivity of greater than ~10kAm-1. The hysteresis loop area should be large, corresponding to a high stored energy. Saturation, coercive force and remanence should also be large. Figure 27.4 shows this intrinsic coercivity, Hc, variation difference between hard and soft magnetic materials. The development progress time-lines of hard magnetic materials is shown in figure 27.5.

2.

Hard magnetic ceramic material: Hard magnetic ceramic material (M.nFe2O3; M refers to Barium, Strontium and Plumbum; while n is within the range 4.5 to 6.5)

3.

Bonded hard magnetic material: bonded NiCoFeTi bonded RE Cobalt bonded NdFeB bonded ferrite

4.

Flexible hard magnetic material: Individually or mixed ferrite and neodymium magnetic powders N57 480

kJ/m3

Virgin magnetising curve

Neodymium-iron-boron Nd2Fe14B

400 320

(a)

1242

(b)

(BH)max

3

451kJ/m 780kA/m 1.52T

Samarium-cobalt Sm2(Co-Fe-Cu-Zr)17

240

(c)

2002

SmFeN

160 Alnico

80

ferrite

0 1940

1950

1960

1970

1980

1990

2000

2010

year Figure 27.5. The progressive development of permanent magnets.

Magnet alloys that utilize elements from the Lanthanide series of the periodic table shown in figure 27.1 are commonly referred to as Rare Earth (RE) magnets. Specific magnetic materials containing rare earth elements, plus transitional elements (TE), are Neodymium Iron Boron (NdFeB) and Samarium Cobalt (SmCo) magnets, as shown in figure 27.6. Ba, barium ferrite

Ferrite magnet

10-1

100

101

102 Coercivity Soft magnetic

103 Hc

104 At/m semi-hard

105

Metal magnet

106 Permanent magnets

hard magnetic

Figure 27.4. Typical hysteresis loop and intrinsic coercivity Hc for: (a) soft, (b) hard magnetic materials, and (c) an overview of magnetic metals, alloys, and materials.

1.

Hard magnetic alloy material: AℓNiCoTi FeCrCo FeCoVCr (RE - rare earth) RE Cobalt RE FeB, REFeN PtCo CuNiFe

1

2

3

4

5

6

7

8

9

Aℓnico magnet SmCo5

Sm-Co magnet

Relative magnetic material volume 0

Hard magnetic materials can be divided into four categories: hard magnetic alloy material, hard magnetic ceramic material, bonded hard magnetic material, and flexible (or rubber) hard magnetic material, which in turn have the following subcategories:

Sr, strontium ferrite

10

Rare earth (RE) magnet

Bonded (rubber/plastic) magnet

Sm2Co17 Nb-Fe-B magnet

SmFeN

Bonded ferrite magnet

Bonded RE magnet other magnets Figure 27.6. Family structure for hard magnetic materials and volume comparison.

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Chapter 27

27.2.1 Alloys

(b) CrFeCo hard magnet material

i. Nickel-iron alloys

Chemical composition:

Nickel-iron alloys, known as permalloy, are versatile and are composed of a wide range of magnietc material, from 30 to 80wt%Ni. Widely varying properties result and the optimum composition is selected for a particular application. High Ni content alloys have high permeability; around 50wt%Ni gives high saturation magnetisation while a low Ni content produces a high electrical resistance (low ac losses). Some Ni-Fe alloys have zero magnetostriction and zero magnetic anisotropy, such as mumetal which is produced by a specific heat treatment and incorporates minimal additions of Cu and Cr. Such alloys have extremely high relative permeability, up to 300,000, and an intrinsic coercivity as low as 0.4Am-1. ii. Cobalt alloys (a) Aℓnico hard magnet material: (alloys based on Al, Ni, and Co) Chemical composition: Wt %

Al

AℓNiCo

Ni

6 - 13.5 12 - 28

Co

Cu

0 - 42

2-6

Ti

Nb

Si

Alnico is classified as either an isotropic or anisotropic hard magnetic material. Aℓnico 2, 3 and 4 are unoriented – magnetic properties are isotropic and equal in all directions. Grades 5 to 9 are anisotropic.

20 permeance factor

1.4

(kJ/m ) Br

20

1.2 1.0

sintered 5

Pc

0.8 10

0.4

2 sintered 8

0.2

sintered 2

0 160

120

80

Demagnetisation field

40 -H

(a)

0 (kA/m)

Induction

0.6

cast 8

-1.0 B

cast 5

B

cast 7-8

(Te sla)

-B/ µo H

3

Energy product BH 50 40 30 maximum energy product BHmax

−B d

B-H

µo H d 2

0.5

J-H

Hci

B×H

Hc

-50 -40

0 -30 -20

Magnetic field intensity

-10 H

0 (kA/m)

(b)

Figure 27.7. Second quadrant hysteresis loop for: (a) Aℓnico family and (b) Aℓnico 5.

Magn etic flu x d ensity

10

(T)

There are two manufacturing techniques for AℓNiCo hard magnet, namely casting and powder metallurgy (sintering for smaller magnets). If the cobalt content is more than 15%, the introduction of an external magnetic field during heat treatment at 1260°C in a hydrogen (or inert gas or a vacuum) atmosphere creates anisotropy for the sintered magnet, allowing the magnetic property to be increased in the preferred direction. For column crystal or monocrystalline shaped material, a strong external magnetic field parallel to the column crystal axis during heat treatment (annealing), produces optimal properties for the cast (and sintered) hard magnetic material. Disadvantages of the Aℓnico materials are relatively low coercivity and mechanical brittleness. Anisotropic columnar Aℓnico 9, has an energy product of ~80kJm-3. However, although having a relative high Br, its main disadvantage is low intrinsic coercivity (Hc ~50kAm-1) thus it must be made in the form of horseshoes or long thin cylinders/rods, which cannot be exposed to significant demagnetising fields.

Pc

Cr

Co

Si, Ti, Mo, Al, V

Fe

25 - 35

7 - 25

0.1 - 3

balance

CrFeCo can be classified into isotropic and anisotropic hard magnetic materials. There are two production techniques for CrFeCo hard magnet alloy: casting and powder metallurgy. The material is ductile (good mechinability) and can be easily hot rolled or cold rolled into strip or drawn into bar shapes, or, after punching, turning or drilling, can be made into the required shape and still maintain its magnetic properties. It has a low coercivity, and is relatively high in cost. Although mostly iron, which is inexpensive, there is significant cobalt and chrome content which is considerably more expensive. Typically strong, hard, tough, but brittle. It is hydrogen resistant. [Br=1.35T, BHmax=52kJ/m3, Hc= 49kA/m, α=-0.03%/°C, β=-0.04%/°C, TC=640°C, Top=500°C and µrc = 2.5]

Chemical composition:

balance

A hard magnet that incorporates aluminium, nickel, cobalt, ferrum, and titanium, is called an AℓNiCo magnet. Typical weight% is: Fe-35, Co-35, Ni-15, Aℓ-7, Cu-4, Ti-4. This group of magnets offer far more magnetic hardness than magnetic steels. Their properties rely on the shape anisotropy improvement associated with the two-phase nanostructure comprised of ferromagnetic Fe-Co needles in a matrix of non-magnetic Aℓ-Ni. Due to their high Curie temperature, ~850°C, they have more stable properties around room temperature than some other alloys. This material has the lowest temperature coefficient (-0.02% per degree centigrade) of all permanent magnets, thus producing a constant field over a wide temperature range (-270°C to +500°C).

1.6

Wt % CrFeCo

(c) FeCoVCr hard magnetic material

Fe

0 - 9 0 - 3 0 - 0.8

1244

Wt %

Co

V+Cr

Fe

FeCoVCr

49 - 54

4 - 13

balance

FeCoVCr hard magnetic anisotropic alloy is produced using a casting process, and can be hot rolled or cool rolled into strip or drawn into wire shapes. Cool deformation (80% to 95%) and subsequent annealing heat treatment at 500 to 600ºC is a necessary processing step to obtain the required anisotropic magnetic properties. [Br = 0.85T, BHmax = 15kJ/m3, Hci Hc = 28kA/m, α=-0.01%/°C, β=0%/°C, TC=720°C, Top=500°C, and µrc= 5] iii. Samarium Cobalt alloys Chemical composition, typically: Wt %

Sm

Co

Fe and Cu

SmCo

35

60

balance

This alloy group combines cobalt, iron (transition metals - TM) and a light rare earth (RE) element to exhibit permanent magnetic properties. They exhibit high-energy hard-magnetic behaviour, but are costly. These magnets have good thermal stability, thus are used where magnets are exposed to high temperatures (>150°C) or very low temperatures (1433 -0.10

875 - 979 1173 >1593 -0.09

835

1082

kA/m

2705

1074

kA/m

-0.11

-0.11

%/°C

-0.55

-0.65

%/°C

Magnetising filed

Hs

1990 - 2785

3581

2785 - 3581

Recoil relative permeability

µrc

1.15 – 2.31

1.14

1.05 – 1.09

Maximum operating temperature Curie temperature

J-H

1.05

pu

Top-max

80 - 180

160 - 200

150 - 200

200

80

°C

TC

305 -470

325 - 370

325 - 370

365

310

°C

0.4

80°C 120°C

0.3

B-H

½

0.2

40 BH 3 kJ/m 24 12

kA/m 1.05

20°C

1

µRC B = Br + µoµrH

B

Maximum energy product

Br

(T)

NdFeB Grade

0.1

Induction

Table 27.3


Chapter 27

0 320

240 Demagnetisation field

160

80 -H

0

(kA/m)

vi. Amorphous and Nano-Crystalline Alloys

Figure 27.11. Second quadrant hysteresis loop demagnetization characteristics measured at different temperatures for a sintered ceramic ferrite magnet (with constant energy contours shown).

These materials can be produced in the form of a tape by melt-spinning. The alloys consist of iron, nickel and/or cobalt with one or more of the following elements: boron, carbon, phosphorous and silicon. They have extremely low coercivity, an order of magnitude less than standard Fe-Si, and consequently have lower hysteresis losses. However, they have a relatively low magnetisation and are not suitable for high current applications. Instead of casting the alloy onto a rotating wheel to produce tapes, it is also possible to direct a stream of molten alloy into a bath of water or oil to produce amorphous wires of typically 50mm thick. These wires exhibit a square hysteresis loop with large changes in magnetisation at low fields, making them ideal for sensing and switching. Nano-crystalline material is produced by annealing the amorphous material. These alloys can be single phase but are usually comprised of nano-sized grains, in the range 10 to 50nm, in an amorphous matrix. They have relatively high resistivity, low anisotropy, good mechanical strength, and are better suited for soft-magnetic applications.

A hexagonal ferrite structure is found in both BaO·6(Fe2O3) and SrO·6(Fe2O3), with Sr ferrite having slightly superior magnetic properties. Generally, magnet materials respond negatively to heat because thermal energy reduces the flux density and the ability of domains to remain aligned. Increased thermal energy increases the disorder present and at a particular temperature, the Curie point, the material loses its ferromagnetism. Excessive heating of a magnet may cause metallurgical changes to occur; in many magnets the safe operating temperature is well below the Curie point. The one exception is ferrites (ceramic magnets), which, due to their chemical nature, can withstand temperatures significantly past their Curie points. Ferrites also exhibit the unusual characteristic of increased coercivity with temperature, as shown in figure 27.11. Heat treatments during manufacturing are precisely controlled to precipitate desired phases and to control metallurgical changes.

27.2.2 Ceramics Hard Ceramic hexaferrites: (BaFe12O19 or SrFe12O19) Hard hexagonal ferrite materials, often referred to as ceramic magnets, are ferrimagnetic and considering the proportion of iron within the material, have a low remanence, ~400mT. The coercivity of these magnets is typically ~250kAm-1. The low remanence means that the maximum energy product is only ~40kJm-3, which is lower than the alnicos, but due to the high coercivity, these magnets can be made into thinner sections. The magnets can be exposed to moderate demagnetising fields, and coupled with good mechanical characteristics and low cost, are suitable for applications such as permanent magnet motors. Ceramic ferrites are made using an iron oxide powder, to which either barium or strontium (carbonate) is added to improve alignment of the crystal lattice structure. The chemical formula is M·n(Fe2O3), where M is Ba or Sr and 5.8 Pc2 Pz

Pc1

Pc2

(T)

Pc1

T1 < T2 < T3 < T4

Pw Px Py

20°C normal B-H

Br

T1 < T2 < T3 < T4 T1

T2

T3

-H

T4 (kA/m)

(a)

T1

B

B

Hci @ 20°C P4

Pc = Pci - 1 =1

Hc @ 20°C

I3: (Hi3, Ji3)

150°C curves extracted x

(µrc -1)

½Hx

µR

T3

i=0

µR

Pc = Pci - 1 =1

Hm

Hx

I3: (Hi3, Bi3)

x

Br @ 150°C i≠0

(µrc -1)

y

y Hx 320At/m

Br @ 150°C

(µrc -1)

N2: H2, B

i≠0

Br @ 150°C

½Hx

+1

µR

+1

Hm

B = µoH

N3: H3, B3

T2

J Bm

Pc = 1

N2: H2, B2 N1: H1, B1

× Hx

I2 (Hi2, Bi2)

Pci = 2

i=0

No: Ho, Bo

intrinsic J-H

2

150°C

Br @ 150°C

Hi2, Ji2

1

Pci = 2

µR

150°C I2

½H x =

µR

(T)

1600

B

20°C

-B/µoH

Induction

Permeance coefficient Pc ( = Pc i - 1) 1.0 1.5 2 3 5

(T)

The penalty of such temperature stability mechanisms is the use of additional magnet material. Since an irreversible loss has occurred in operating at point P3, the magnet can only be returned to its original condition if it is fully re-magnetized. -B/µoH


Chapter 27

N3: H3, B3

T4

-H

(kA/m) (b)

Figure 27.37. Load line and operating point temperature dependence.

SHx

(a)

(b)

Figure 27.38. Losses at elevated temperatures with demagnetisation in an external field at: (a) 20°C and 150°C with (b) 150°C operation extracted and expanded.

µoPc Hx

Hard magnetic materials 2

-B/µoH

4

1.6 1.4

J-H

1

1.2 20°C

60°C

80°C

100°C

Br′+20°

120°C

1

B-H

Magnet Stability: irreversible thermal losses The variation in a magnet's remanence Br, in figure 27.34c is approximately linear with increasing temperature and reversible up to its specific transition temperature. Once the change becomes nonlinear, an irreversible loss of Br occurs. This transition is associated with the onset of a reversal of the material's magnetization, and is represented by a knee in the demagnetization curve. The load line intersection with the demagnetization curve identifies the operating point (Bd, Hd) for the magnet supplying flux to a given magnetic circuit. As with the remanence, if the operating point is above the demagnetization curve knee, changes in the magnet's condition are reversible, but if the operating point falls below the knee, irreversible loss of part of Br occurs. The position of the knee, that is, the threshold for s irreversible loss component arising, depends on temperature, and as the temperature increases, the operating point may readily fall below the knee of the applicable demagnetization curve.

a

b

Br′+120°C

a c

b

½

loop width decreases to zero as Pc tends to minus infinity

0.8

d*

d

e*

c d

d*

0.6

Pc →-∞

1.5

Pc

Figure 27.38b shows the operating point trajectories at a higher temperature, 150°C, where coil excitation causes the operating points to locate well below the knee, in fact in the third quadrant. With no field bias, i = 0, operation at points I2 : N2 results in a small reduction in Br. Having applied a coil current corresponding to Hx = -320kAt/m, removal of the demagnetising bias field leaves the magnet with severe irreversible loss, with the operating points having reduced from I3 : N3 to x : y, respectively. When a bias field is applied, either the intrinsic or normal demagnetising curves readily illustrate the loss.

1282

(T)

Chapter 27

Flux density Bm

Power Electronics

1281

irreversible reversible

e*

e

0.4

e

0.2

-1000

-800

-600

Field intensity

-400

0

-200

Hm

30

-0.2

(kA/m)

60

90

120

Temperature Top (°C)

-0.4

µo B=

Example 27.2: Magnet load and temperature dependant operating point Consider the following two magnets to be operating in a magnetic circuit with a load line as specified:

Figure 27.39. Interpretation of irreversible and reversible temperature losses for a NdFeB magnet.

A fully dense anisotropic neodymium-iron-boron magnet with demagnetization curves as shown in figure 27.39, is temperature cycled between 20°C and 120°C. Determine the subsequent remanence flux density at 20°C and 120°C, if the load line slope is -1.5; and A ceramic ferrite magnet with demagnetization curves as shown in figure 27.40, is temperature cycled between -60°C and 60°C. Determine the subsequent remanence flux density at -60°C and 60°C, if the load line slope is -1.

Solution i. Sintered NdFeB a. Reversible loss:- magnet operating temperature is cycled between +20oC and +80oC. The second quadrant demagnetization B-H curves in figure 27.39 develop a knee in the second quadrant above about 0oC, with a knee apparent for a temperature of +20oC. The magnet's operating point at the intersection of the load line, Pci = -1.5, and the +80oC curve is above the knee, so no irreversible loss occurs for temperatures up to about 85oC. This reversible change is illustrated on the right of the B-axis, with magnet flux cycling between point ′a′ at 20oC, to point ′b′ at +60oC and point ′c′ at +80oC. b. Irreversible loss:- magnet operating temperature is cycled between +20oC and +120oC. The magnet begins again at 20oC, point ′a′, is heated first to +60oC, point ′b′, then to +80oC, point ′c′, and then up to +100oC - point ′d′. However, the intersection of the load line and the +100oC demagnetisation curve is now below the knee, and an irreversible loss of magnet flux occurs (starting just above +80oC). When the magnet is cooled to 20oC, the magnet's operating point on the load line, point ′d*′, is no longer on the 20oC demagnetization curve, but at some point within the major B-H curve in the second quadrant. If rather than cooling from 100oC, the magnet is heated to 120oC, the operating point moves to point ′e′. Now when the magnet is cooled to 20oC, operating point ′e*′ results. The magnet is no longer fully magnetised, having suffered irreversible loss. Operation up to 120C is stabilised but it must be remagnetized to saturate the material's magnetization once again, and to regain operation on the major BH curve. In summary: ′a′ to ′b′ to ′c′ is a linear change and is reversible, as described in part a. ′c′ to ′d′ then to ′e′ are non-linear changes and represent partial irreversible loss. ′e′ to ′e*′ is a linear change and is reversible, but with reduced magnetic properties. ′e*′ to ′a′ illustrates restoration of full magnetic properties after re-magnetizing the magnet. The recoil lines in figure 27.39 from ′e′ and ′e*′ predict remanence fluxes of 0.87T and 1.06T at +120oC and +20oC, respectively. The magnet is now temperature stabilised for operation up to 120oC. As the load line slope is increased, given the shape of these demagnetization curves, the transition temperature to an irreversible loss also progressively increases. A greater load line slope raises the flux produced by the magnet to the magnetic circuit and helps to stabilize the magnet against irreversible loss thermal effects.

ii. Ferrite When considering the change in coercivity, Hci decreases with temperature both for samarium-cobalt and for neodymium-iron-boron magnets; Hci increases with temperature in the case of ceramic ferrites (being based only on magneto-crystalline anisotropy). This means that the knee of the demagnetization curve can arise as the temperature falls. The magnet is cycled from +20oC to -60oC and back again. Figure 27.40 illustrates that, with a load line slope of -1.5, the transition to an irreversible loss occurs when the temperature falls below about -20oC.

Energy product BHmax 1.5

Pc

-B/µoH

2

4

32 24

-60°C

(T)

iv.

-0.6

3

(kJ/m )

0.5

Flux density Bm

iii.

H

-20°C 20°C

1 60°C

0.4

Br′-60°C

J-H

100°C

B-H c

½

b

d a

0.3

loop area (width) decreases as Pc increases

Br′+60°C 0.2

c

d

b

a

irreversible reversible

d*

d*

0.1

0 -240

-200

-160

Field intensity

-120 Hm

-80 (kA/m)

-60

-40 -0.1

-30

0

30

60

Temperature Top (°C)

B=µoH

Figure 27.40. Interpretation of irreversible and reversible temperature losses for a ferrite magnet.

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The sequence of thermal events is: a to b to c is a linear reversible change between +60oC and -20oC. c to d is a non-linear irreversible change from -20oC down to -60oC. c to d to d* is a linear reversible change from -60oC back to +60oC, but with reduced magnetism. The recoil lines in figure 27.40 from ′d′ and ′d*′ predict remanence fluxes of 0.38T (reduced from 0.46T) and 0.275T (reduced from 0.37T) at -60oC and +60oC, respectively. ♣ If operation of a magnet over its working temperature range is predicted to introduce unacceptable irreversible loss, then the magnet application should be reassessed to increase the load line slope and stabilize its operation without degrading the properties. 27.10

Energy transfer

One or more air gaps introduced into a magnetic circuit enable useful work to be performed. The mechanical energy used to separate a magnet from soft iron, there in creating an air gap, is stored as potential energy within that air gap and the magnet. This moves the point of operation on the intrinsic curve in the second quadrant. The normal curve in the second quadrant represents the energy output of the magnet and is used during magnet design. If the iron in the circuit is completely removed, the air gap becomes large and the operating point of the curve approaches Hc (the normal coercivity) in the second quadrant and the induction B approaches zero.

Stored energy 2 ½µH

(d)

Hd, Bd

b Br c

∫ B dH

(a)

(b)

(c)

c

c

b

b

− ∫ BdH − ∫ HdB = − [BH ]b c

(27.50)

The first term is the work done (energy) by the applied field, the second is the internal kinetic energy stored, and the sum equals the total potential energy per unit magnet material volume. After being magnetized to saturation, point a, the potential energy is reduced to zero at remanence (Bm = 0 at point b); the magnet conditions must move into the second quadrant to deliver its stored energy. Figure 27.41 shows how the three energy density components of equation (27.50) develop as the magnet moves from point b to point c. Considering the direction of integration, the three areas sum according to equation (27.50), namely, the work done as a result of the applied field ∫BdH equalling the change in potential energy [BH] plus the release of kinetic energy from the magnet ∫HdB. The higher the potential energy of a permanent magnet, the greater the release of its kinetic energy in establishing an external field. While magnet developments have focussed on improving the available (potential) energy density, it also requires a corresponding increase in the work to change the operating condition of the material. Consequently, the basis of most devices using high-energy magnets is a design that keeps the magnet close to a unique operating point with a minimum of dynamic operation. The kinetic energy released by a magnet of volume Vm, which is operating at a typical point c, (Hd, Bd), in figure 27.41, is (27.51)

Energy being delivered, is readily derived from the Norton equivalent circuit in figure 27.17c, where B2 Am 2 w = ½φm2 ℜm = ½ (B m Am ) = ½ m Am A m = ½B m H m × volume

d Hm

-Hc

Section 27.6 presented the method for determining a magnet's operating point (Bm, Hm), associated with which is stored energy, which may be instrumental in the conversion of electrical and mechanical work. In figure 27.41, the energy stored in volume Vm of a magnet, leading to the change in energy is:

This triangular area in figure 27.41b, the kinetic energy being released by the magnet, is the magnetic energy stored in the magnet reluctance, equivalent to w = ½LI2. For a given operating point, (Hd, Bd), this energy can be derived from the Thevenin or Norton equivalent circuits, specifically the magnetic energy in the magnet reluctance: w = ½φm2 ℜm = ½ℑ2r /ℜm

a

∫ H dB

1284

W = V m ∫ HdB

Operating point

Bm

Coenergy 2 B /2µ


Chapter 27

µm Am

[BH]

µm

This energy is only released if work is done, that is, power is released or absorbed. Mechanically this could be an air gap change or electrically a voltage developed across a current carrying coil. Note coil current alone is insufficient, the voltage component can only be produced by a changing flux, from v = N×dΦ/dt, which implies a magnet operating point flux change, dΦ. Energy delivered to an air gap

∫ B dH

∫ H dB

Bm Operating point Hd, Bd c

b c

[BH]

Bm

The following equation may be applied to the field in any volume, even an air gap Vg, where Bg = µoHg, that is:

Bm

b

b

+

Wg = V g ∫

c

=½

Hd, Bd

-

-

Bg dB µo

B g2 V = ½B g H g V g = ½µo H g2 V g µo g

If this is the air gap in the magnetic circuit of figure 27.21, then equations (27.18) and (27.19) may be used in equation (27.52) to show that all the energy released from the magnet is delivered into the gap:

W g = ½B g H g V g = −½B m H m V m Hm

Hm

(27.52)

Hm

Figure 27.41. Graphical demagnetisation change per unit volume: (a) applied field energy, (b) magnet kinetic energy, (c) total potential energy, and energy changes around the B-H loop.

If the air gap is closed again, the stored potential energy is used to perform the work of bringing the magnet and the iron together. However, the operating point does not return to Br. The magnet recoils along a so-called minor hysteresis loop to a point below Br, figure 27.16c. Repeated opening and closing of the air gap will result in the magnet cycling along this minor hysteresis loop. The average slope of the minor loop is the recoil permeability, µoµrc.

(27.53)

Note the energy density delivered to the gap is half the magnet's energy product. The work done by the externally applied field in establishing the air gap energy has two components as shown in figure 27.42a. The first component is the pu volume energy released into the air gap, equation (27.53), the second is the pu volume energy associated with establishing the operating point, namely the energy associated with increasing the air gap from zero at point b to length ℓg at point c. Once the magnet operates on a recoil line of relative permeability uR and recoil remanence Br, this equation is modified by B m = µo µrc H m + B r to

W g = ½B m H m V g = ½ ( − µo µrc H m − B r ) H m V g = ½ ( − µo µrc H m2 − B r H m ) V g

(27.54)

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The further down its demagnetization curve a magnet is driven, the greater the area swept by the load line, by which the applied field within the magnet does more work. This energy is recaptured by the magnet if the gap is re-closed and the load line returns to its original position. However, if this cycle includes driving the magnet beyond a knee in its characteristic, a return to the original load line along a recoil line involves the irreversible loss of magnet field energy, as shown in figure 27.42. Large dynamic excursions of a high-energy magnet can be restricted by increasing ℓg during installation of the magnet. Subsequent cycling along the recoil line incurs no further irreversible loss, only reversible changes in energy. While BH max is the most common figure of merit for a permanent magnet, operation at this point maximizes the release of magnet energy into the gap, namely -½ V m BH max. If the magnetization M is constant and the linear demagnetization characteristic is represented by Bm = µo (Hm+M), then the air gap energy, equation (27.53), may be written as

W g = −½µoVm (H m2 + MH m )

Coenergy can be considered a dual of stored energy that is often used to compute forces on electromechanical systems with permanent magnets and current-carrying coils. Force and torque can be deduced by changes in energy with respect to position, but the process is complicated by the need to compute the energy that is sunk or sourced by the supplies driving the coils over the change in position. Conversely, computing the change in coenergy for constant currents directly yields the mechanical work done on the system. An expedient lower bounds for coenergy computation, for the integral is Ho= -Hc. The coenergy density in the magnet wm' is, for the case in which the flux density is aligned with the magnetization:

w m' =

2

w m' =

Bm

B2 2µ

Bm Operating point Hd, Bd

Br

Br Coenergy 2 B /2µ

Energy dissipated during magnetisation

-Hc

[BH]

Hm

-Hc

Energy dissipated during magnetisation


Hm

Figure 27.43. Graphical representation of permanent magnetic energy components: (a) with applied bias +Hd to enable operation in the first quadrant and (b) demagnetisation quadrant operation energy components.

k Ak r

B×H

Operating point Hd, Bd


BmH m V k Ak r m

Constant energy contours

2

Stored energy and coenergy can be shown as regions associated to the demagnetization curve as shown in figure 27.43.

By adding a coil of N turns with current i, as in figure 27.26, and using equation (27.30), the air gap energy becomes V B  Ni  W g = −½ m m  H m −  k Ak r  Am  The last term represents the energy contribution from the coil. Since the flux in the circuit is Φ=BmAm, and the total flux linkage with the coil is defined as λ=N Φ, the gap energy can be written as: 1 Wg = ½ ( −Vm B m H m + λi ) Bm

3

(kJ/m )

As shown, the area swept in the first quadrant represents the energy per unit volume (the integral of H(B) dB) that was needed to magnetize the material. This energy can never be recovered, even if a large field intensity is applied to the magnet to push its operating point back into the first quadrant, as indicated in both parts of Figure 27.43. Remagnetisation only stores energy (½ µH 2 ) in the magnet without possibility of extracting the energy associated with the magnet’s magnetisation.

Increasing energy Pc1 Pc1 > Pc2

Br1

Hd1, Bd1

Pc

= B r H + ½µH 2|H−Hc = ½µ (H + H c )

2

A more realistic representation of the soft iron pole pieces requires the inclusion of the flux leakage coefficient kℓ and mmf loss factor kr via equations (27.19) and (27.18) within equation (27.52). Both loss factors reduce the amount of magnet energy delivered in to the gap

Load line

∫ B (H ) dH

The definition of magnet flux density B from equation (27.11) yields a simpler definition of coenergy within the magnet:

The magnet energy released is lower either side of the BH max point on the major demagnetization characteristic, and by virtue of a reduced alignment of the magnetization M, Wg is also smaller for operation on recoil lines within the major B versus H curve. The superimposed constant energy contours on the characteristic in figure 27.42 illustrate the energy penalty of non-optimal operation. Convention is to express these as constant energy product B mH m (as also seen in figures 27.8, 27.11, and 27.15, amongst others), rather than the actual energy density ½ BH max.

Bm

H

−Hc

(27.55)

W gmax = ½µoV m (½M ) ≈ ½µoVm (½B r )

1286

Coenergy

Differentiating, BH max occurs at Bm = ½µoM, -Hm =½M, for which

W g = ½B g H g V g = −½


Chapter 27

b c

Pc2

Energy change within the magnet

∫B

m

27.11

Br2,3

dH m − ½B m H m

Force of attraction within an air gap

The equation F = -dW/dx can be used to calculate the force of attraction between two pole faces bounding the air gap of figure 27.21 (figure 27.44) of area Ag and length ℓg. The energy in this gap is given by equation (27.52), which, with Bg = µoHg, becomes

Hd3, Bd3 Hd2, Bd2

Wg = ½

Hm

Hm Hc

(a)

(27.56)

Using Cartesian axes in the air gap, with flux along the gap length ℓg being in the x-direction, force is calculated by differentiating equation (27.56) with respect to ℓg, which yields

Energy released to the air gap

½B m H m

B g2 B2 V g = ½ g Ag A g µo µo

(b)

Figure 27.42. Per unit volume change: (a) of the magnet’s applied field energy and (b) magnetic field energy with load line slope.

Fx = −

dW g A B2 φ2 = − ½ g g = −½ d Ag µo µo Ag

(27.57)

The definition of -Fx acting into the air gap confirms this as a force of attraction, which will increase as the gap closes. Although ℓg, is not a parameter in equation (27.57), Fx is proportional to Φ2, where a flux increase results from decreasing ℓg, which causes an increase in load line slope as the magnet's operating point moves up its demagnetization characteristic. Similarly, there are forces acting to retard

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Chapter 27

the lateral displacement of one pole piece with respect to the other (Fy, Fx), which may also be determined from equation (27.56) by splitting Ag into its y and z components and differentiating with respect to the appropriate axis. N

S Bg Fx

Ag x ℓg Figure 27.44. Force of attraction between opposite pole faces bordering a uniform air gap.

• • • • •


Variety of pole configurations are possible Multistep and multi-component moulding to produce assemblies Dilution of magnetic phase produces lower energy product Anisotropic and isotropic powders offer a wide range of magnetic alignment and output options Relatively high tooling costs make them suited to high volume manufacturing

Compression bonded - low cost manufacturing: (Rare Earths and Ceramics) • Higher loading than injection moulded, but lower than fully dense creates a compromise in energy product • Limited to simple geometries: rectangles, cylinders, arcs – thin walled cylindrical shape possible • Tight geometric tolerancing except in pressed thickness • Brittle thus requires careful handling • Isotropic powder allows complex magnetizing patterns Casting: (Alnico) Extruded: (Bonded NdFeB and Flexible) Calendering: (Flexible)

27.12

Appendix: Magnet processing and properties Magnet Material Neodymium-Iron-Boron - high energy • Relatively abundant resource with large proven reserves • Refining costs are moderate • Manufacturing technology is established • Highest energy product output of all commercially available PM materials • High temperature, > 150ºC, applications require a compromise in energy product • Tendency to corrode requires protective coating, chips, cracks, and brittle • PrFeB variant for temperatures between a few degrees Kelvin and 135K Samarium Cobalt - stable • Relatively abundant resource with large proven reserves • Manufacturing technology is established; dominated by 2-17 grades • Second to NdFeB in magnetic output – high energy product and coercive force • Excellent high temperature performance with grades available for use to 550ºC • Corrosion resistance superior to NdFeB, but coatings generally advisable • Brittle, chips, cracks easily, and hard to machine • Refining costs are higher than for NdFeB SmFeN

Permanent magnet manufacturing Process Sintered / fully dense, anisotropic magnets - maximum output: (Rare Earths, Ceramics, and Alnicos) • Maximum energy product for magnet size and weight • Restricted to simple geometries • Brittle thus requires careful handling • No dilution effect due to non-magnetic phase Injection moulded - shape flexibility: (Rare Earths and Ceramics) • Complex geometries • Tight geometric tolerancing without finishing operations • Relatively robust, resistant to chippage • Insert and over moulding to reduce assembly costs

1288

Ferrite (Ceramic) - low cost • Abundant, low cost raw material • Magnets are lowest cost option • Manufacturing technology is well-established • Lower magnetic output than the rare earth materials, but high coercive force • Excellent high temperature performance with grades available for use to 250ºC • Limited low temperature performance, generally to -40ºC • Corrosion resistance is outstanding, but brittle and chips easily Alnico – stable properties • High corrosion resistance • High mechanical strength, tough but brittle • High temperature stability • High cost • Low coercive force and energy product

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Table 27.7 Typical magnetic properties for NdFeB and SmCo Table 27.6 Physical and mechanical properties of AlNiCo, FeCrCo, FeCoVCr, SmCo, NdFeB, and hard ferrite Neodymium Iron Boron (NdFeB) Material and production method Material

isotropic Production or method anisotropic

Physical properties Coefficient of Thermal Resistivity thermal conductivity expansion -6

10 /K

W/m.K

µΩ×m

11

10 - 15

0.45 - 0.55

10

10 - 13

0.7 - 0.8

AlNiCo

i or a

FeCrCo

i or a

casting or sintering

FeCoVCr

a

casting

SmCo5

a

Sm2Co17

a

NdFeB

a i or a

9 , 12, 11

hard ferrite

27.13

11.5 //6

sintering

Mechanical properties Tensile strength

Density g/cc

Compressive Young's strength modulus

MPa

MPa

80 - 300

300 - 400

MPa

1200 - 1400 600 - 700 2000 - 5000 2500 - 3500

0.55 - 0.65

HV

300 - 350 400 - 500

∟13

10 -13

0.5 - 0.6

8.2

30 -40

//8 ∟11

10 -13

0.75 - 0.85

8.4

40 - 50

800 - 900

150 - 200 600 - 700

//3. 4 ∟-5

8 - 10

1.4 - 1.6

7.4

80 - 90

1000 - 1100

150 - 200 500 - 600

4

> 10

50 - 60

600 - 700

4

900 - 1000

Higher Hci materials can be used up to 200°C, moderate Hci materials used up to 150°C. Low Hci materials limited to 100°C

SmCo can be used at substantially higher temperatures than NdFeB. Continuous operation at temperatures above 250°C Also significantly better at temperatures below 100K

Loss of flux density at elevated temperatures

Loses 0.11% of Br /°C. See NdFeB temperature effects on Br & Hci

Loses about 0.03% of Br /°C

General environmental conditions

Neodymium Iron Boron is highly reactive to environmental conditions, while Samarium Cobalt magnets are very corrosion resistant.

Humid environments

Surface treatment advisable, due to oxidation Options are nickel, IVD or polymer coatings.

Surface treatment is not required. Does not oxidize.

Hydrogen rich atmosphere

Not recommended, hydrogenation occurs, causing the magnet material to disintegrate

No known adverse effects

Cost of part

Lower cost generally

Higher cost than NdFeB because of Co content

Radiation environment

Damaged by radiation, mainly gamma rays

Higher grades are stable to radiation

Mechanical strength

Mechanically strong, not as brittle as SmCo

Brittle. Both alloys require diamond tooling, EDM, or abrasive grinding when machining.

Clean room environments

Surface treatment recommended

Surface treatment not required

Vacuum applications

Needs to be coated, with nickel or IVD recommended (metallic - do not outgas). Polymer coatings can be used, but not in an ultra high vacuum or high temperatures in a vacuum, due to outgassing.

Surface treatment is not required. However, fairly porous; parts may outgas for a limited duration before high vacuums can be achieved

High field requirements

Higher fields achievable, higher energy products (up to 440kJ/m3 )

Highest energy product is 240kJ/m3, difficult to obtain higher.

Cryogenic temperatures

Only special formulation grades

Operates well in cryogenic temperatures.

Aerospace applications

Gaining use in aerospace applications, optionally with surface treatments. Used in aircrafts, missiles, and satellites.

Established in aerospace, military, and defence applications.

Salt, open seas, and salt spray environments

Surface treatment essential, limited life

Stable in this environment

Acid and alkaline environments

Surface treatment is necessary, limited life

Stable in this environment, however, qualification tests recommended

Thin walled, thin crosssection applications (a dimension below 1mm)

Mechanically stable, parts as thin as mm

Poor in thin cross-sections. Under ½mm is not recommended

Single piece large parts

Better than SmCo, larger blocks can be sintered

Larger blocks (over 75mm in any dimension) are challenging

Nickel plating as per military specifications

Not available – proprietary plating to specifications, only electrolytic nickel

Electroless and electrolytic nickel plating

Plating as per military specifications

Not available. Plating as per proprietary specifications.

Not typically used.

Radial ring (for true radially oriented field)

Possible.

Not available

Sensitivity of flux density, Br, and coercivity, Hc, to temperature changes

Temperature coefficient of Br ranges from, negative, 0.11%/°C to 0.13%/°C. Higher coercivity materials (>160kA/m) are closer to negative, 0.11%/°C

Temperature coefficient of Br ranges from negative, 0.03%/°C to 0.04%/°C. Series Sm2Co17 less sensitive to temperature changes (about negative 0.03%/°C) than SmCo5 (about negative 0.04%/°C) Temperature coefficient of Hc ranges from negative, 0.15%/°C to ¼%/°C. Series Sm2Co17 less sensitive to temperature changes (about negative 0.15) than SmCo5 (about negative ¼)

Hardness

100 - 200 300 - 400

100 - 150 500 - 600

15 - 200

500 - 600

Appendix: Magnetic Basics

B = µo H B = magnetic flux density or magnetic induction, Vs/m2, 1 Tesla µo = magnetic permeability of a vacuum = 4π × 10–7 Vs/Am H = magnetic field strength, A/m If a material is present, the relation between magnetic field strength and magnetic flux density becomes B = µo µr H B can be split into the flux density in the vacuum plus the material part according to B = µo H+J J = µo M This gives B = µo (H+M) The definition of B yields M = (µr - 1)H = χmag H with χmag = (µr–1) = magnetic susceptibility. With superconductors (= ideal diamagnets), χSC = –1.

27.14 Appendix: Magnetic properties for Sintered NdFeB and SmCo Magnets Neodymium magnets are graded by the material they are made of. The higher the grade (the BHmax, following the ‘N’ in Table 27.3), the stronger the magnet. Table 27.7 can be used to determine whether it is better to use sintered Neodymium Iron Boron or sintered Samarium Cobalt in a particular application.

Samarium Cobalt (SmCo)

High temperature applications

Temperature coefficient of Hc ranges from, negative, ½%/°C to ¾%/°C. The higher the intrinsic coercivity, the lower the temperature coefficient of Hc

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Chapter 27

Based on table 27.7, in summary, do NOT use Neodymium Iron Boron magnets under the following conditions: • In an acidic, alkaline, or organic solvent (unless the magnet is hermetically sealed) • In water or oil (unless hermetically sealed, or a limited life results) • In an electrically conductive liquid, such as electrolyte containing water • In a hydrogen-containing atmosphere, especially at elevated temperatures. Hydrogenation, a process where the H2 molecule reacts with the NdFeB, causing rapidly deteriorate • Environments containing corrosive gasses, such as Cℓ2, NH3, N0X, etc. • In the path of radioactive rays

27.15 1.

2. 3. 4.

5.

6.

Appendix: Magnetic Axioms Flux lines, like electrical currents, follow the path of least resistance. In magnetic terms, this means that flux lines will follow the path of greatest permeance (lowest reluctance). Flux lines will always follow the shortest path through any medium. They therefore can only travel in straight lines or curved paths, and they can never take true right-angle turns. Flux lines repel each other, hence never cross, if their direction of flow is the same. For unsaturated ferromagnetic materials, flux lines will always leave and enter at right angles. All ferromagnetic materials have a limited ability to carry flux. When saturated, they behave as though they do not exist (like air, aluminium and so on). Below the level of saturation, a ferromagnetic material will substantially contain the flux lines passing through it. As saturation is approached, because of axioms one [1] and two [2], the flux lines may travel as readily through the air as through the material (which appear like air when saturated). Flux lines will always travel from the nearest north pole to the nearest south pole in a path that forms a closed loop. They need not travel to their own opposite pole; although they ultimately do if poles of another magnet are closer and/or there is a path of lower reluctance (greater permeance) between them. Magnetic poles are not unit poles. In a magnetic circuit, any two points equidistant from the neutral axis function as poles, so that flux will flow between them (assuring that they meet the other conditions stated above).

Table 27.8 The relationship between magnetic parameters in cgs and SI units.

Quantity Magnetic Induction

symbol

Gaussian

Gaussian (cgs units)

B

gauss

G

Applied Field strength

H

Oersted

Magnetisation

M

emu cm

Magnetisation

S.I.

Oe

S.I. Units

Conversion factor (cgs to S.I.)

Tesla, T

1G = 10-4 T

-1

10 / 4π

Am

-1

10 -

Am -3

-3

3

4πM

G

-

Magnetic Polarisation

J

-

T

-

Specific Magnetisation

s

emu g-1

JT-1 kg-1

1

Induction in free space Induction in medium

B=H

G

B= µo H

T

1G = 10-4 T

B=H+4πM

G

B = Bo + µoM

B = µo (H + M)

1G = 10-4 T

unity

Dimensionless

4π 10-7

H m-1

4 π . 10-7

Permeability of free space

µo

Relative Permeability

µr

-

Dimensionless

-

Susceptibility

χ

emu cm-3 Oe-1

Dimensionless

4π

BHmax

M G Oe

kJ m-3

1 MGOe =10 / 4 π

Maximum Energy Product

G = Gauss, Oe = Oersted, T = Tesla

2


Reading list http://www.magnets.bham.ac.uk/magnetic_materials/ http://www.mceproducts.com/ http://www.dextermag.com/Permanent-Magnet-Materials.aspx http://www.arnoldmagnetics.com/ http://www.intemag.com/magnet_materials.html http://www.magnetweb.com/ http://www.femm.info/wiki/PMEnergy

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Chapter 28

28

Contactors and Relays

1294

After the accelerated motion of contact transfer, the movable contact impacts and decelerates as it reaches its normally open fixed contact. Both contacts must deflect or deform to some degree as the desired contact force builds ups. Over-travel can be employed to provide contact cleaning action, through sliding, and to compensate for contact wear or erosion. When there are multiple sets of contacts (poles), allowance is made for manufacturing tolerances for the various stages of travel required for and their associated spring forces. The word normally (N) refers to a de-energized relay condition (no electrical power into the coil). The subsequent word open (O) or closed (C) refer to the position of the contacts in a de-energized condition, viz., normally open NO or normally closed NC. 28.2

Relay Contacts

28.2.1 Contact characteristics


A relay is an electrically operated switch. Generally, a relay is an electromagnetic device, within which an electro-magnet is fixed to cause controlled movement either by magnetic attraction or magnetic repulsion. Other hardware attached to the moving magnetic portion of the component, such as relay contacts, will cause switching of electrical circuits. Differentiation between contactor (or relay), circuit breaker, and mechanical switch is as follows: A relay is an electromagnetic device for remote or automatic control that is actuated by variations in conditions of an electric circuit and which, in turn, operates other devices (such as contacts) in the same or more often, a different (isolated) higher power circuit. A high power-handling relay is termed a contactor. A circuit breaker is a switch that automatically interrupts an electric circuit under an infrequent abnormal condition; e.g., a fault condition such as an overload or rupture of either high voltage or high current or both. A mechanical switch is a device for making, breaking, or changing the connections in an electrical circuit, usually mechanical and operated manually. 28.1

Mechanical requirements for relay operation

A relay comprises a coil (of insulated copper wire), a plunger, and contacts, all housed together within a case or body. Electrically energising the coil creates a magnetic field that moves the plunger. The movement of the plunger causes a moving low resistance contact to move toward (or away from) a nonmoving fixed contact. It is the coming together of these contacts (make) or separation of them (break) that has the effect of switching. The fixed contact may be mounted on compliant springs or fixed brackets. The movable contact (single throw, ST) is mounted on some form of spring that can be deflected or on a hinge arm. The force and travel needed for such motions serve a number of purposes. Relay coils are wound for a particular voltage, commonly 24V dc, a safe voltage for control automation, 115V ac is often used in North America and 230V ac is found in EU systems. A coil will activate its plunger as the voltage increases from zero to its normal rated level, nominal voltage, and this is know as the pull-in voltage (often around 80% of nominal). As power is removed from the coil the plunger returns to its rest position as the voltage drops below the drop-out voltage (often around 20% of nominal). Before the armature is actuated for a relay with double throw contacts, DT, the movable contacts must be held against the normally closed fixed contacts by a spring force sufficient to establish good electrical contact. When the armature is actuated, a number of things happen. Each movable contact is pushed or pulled away from the corresponding, normally closed, fixed contact. This requires a force sufficient to overcome one or more springs. Also, there is friction between the contacts if they slide before they separate, and in any actuator pivots. As contact motion takes place, various springs deflect according to Hook's law, and inertial forces must be overcome.

BWW

Contact characteristics that affect switching performance are: • Electrical conductivity • Thermal conductivity • Hardness, limit of elasticity: Young's Modulus • Resistance to erosion, welding or electrical sticking, cold welding, mechanical wear, oxidation, and atmosphere contamination (chemically active). • Tendency to bounce on impact, gaseous absorption, catalytic polymerization of hydrocarbons, metal transfer at contact closure and arcing at opening. Besides the physical and chemical properties of the contact metal, there are some geometrical and dynamic considerations: • Shape of contacts • Force between contacts • Amount of slide or wipe • Amount of rolling or twisting motion • Supporting structure resiliency and its tendency to enhance or inhibit bounce or chatter. When contacts meet, the metal at the point of the contact deforms until the actual touching area supports the contact force and provides metal-to-metal contact, unless some foreign material interferes. Deformation is at the point of contact, either in the elastic or plastic modes, contributes to the amount of contact bounce. Microscopically, many actual points of contact (often referred to as a-spots) form the electrical conductor and carry the current. The contact interface is also subject to mechanical abrasion and metal galling as it rubs, and cold welding. The surface absorbs a monomolecular layer of volatile molecules in direction proportion to the molecular weight and concentration of the volatile material and the ambient pressure and inversely proportional to the temperature. Water vapour is also a common substance forming thin absorbed layers. Each metal has particular pertinent chemical properties. Silver and its alloys, which have excellent electrical and thermal characteristics, tend to combine chemically with gaseous compounds of sulphur, the halogens (fluorine, chlorine, bromine, and iodine), and silicones, to form high electrical resistance, in the form of hard coatings. Unlike other noble metals (gold, platinum, rhodium, iridium, palladium, and ruthenium, all of which are used in contacts), silver has no catalytic effect (polymerization) in the sense of changing, under sliding pressure, the absorbed hydrocarbon molecules into a solid hydrocarbon material. Arcing, however, can accomplish the precipitation of solid carbon or carbonaceous products, usually in a ring around the actual point of contact. Molybdenum, tungsten, nickel and mercury are used alone or as alloying or sintering ingredients. Cadmium oxide, tungsten carbide, tin, magnesium, and carbon are sometimes added to silver to inhibit sticking or welding, particularly in high-current relays or contactors. When contacts are within an inert gas, like nitrogen, other contact materials are applicable. 28.2.2 Contact materials Low voltage and current contact material operating boundaries are summarised in figure 28.1. Fine Silver, Ag Fine silver has the best electrical and thermal properties of all metals. However, it is affected by sulphidation, which forms a film on its surface that increases contact interface resistance. Thus contact pressures must be sufficient to break through the film. While such pressures have no appreciable effect on silver-cadmium contacts, they do result in increased material wear of fine silver contacts. Also, an interface voltage of several hundred millivolts can occur with fine silver contacts because of the sulphide film. Controlled arcing burns off the sulphidation, and contact over-travel wipes away the residue. Breaking through this film generates electrical noise, consequently, fine silver contacts are not used for low-level switching, such as audio circuits. Therefore, fine silver and silver alloy contacts are for use in circuits of 12V, 0.4A, or more.

1295

Power Electronics

Gold-Flashed Silver, Au flash 3µm Ag For relays that are inoperative for long periods before initial operation, sulphidation of silver contacts can result in an impregnable contact interface resistance. Instead of specifying silver contacts for such conditions, gold-flashed silver contacts are specified. Gold flashing on each contact results in minimal sulphidation/corrosion/oxidation during storage, and provides good electrical make upon contact. Because gold has a low boiling temperature, any flashing burns off after just a few switch cycles if arc voltage and current limits are exceeded. The silver under-layment is then exposed, which may develop a sulphide film. Generally, gold-flashed contacts should not be subjected to arcing. Gold-flashed silver has the same qualities as 10µm plate Au, but is less durable. Gold Overlay, plated 10µm Au A common contact for use in dry and low-load level switching circuits (>1mA/100mV) is gold overlay. The overlay is of sufficient thickness so as to not wear through to the base metal unless subjected to arcing conditions. This plating is removed by friction and erosion after around 1 million switching cycles in dry circuits (no current is switched). Silver Nickel, AgNi 0.15 Depending on the application, material transfer may be prevalent with fine silver contacts. Typically, material tends to accumulate in the centre of one contact, while the loss of material on the other contact leaves a hole, or pit, leading to premature contact failure. In such applications, it is desirable to use fine grain silver contacts, in which alloying with 0.15% nickel gives the contacts a fine grain structure. As a result, material transfer is evenly distributed across the entire contact surface, resulting in longer contact life. Minimum contact load is 20V/50mA for a single contact. Silver Cadmium Oxide, AgCd0 Silver cadmium oxide contacts are used for switching loads that produce a high-energy arc. Such contacts are less electrically conductive than fine silver contacts, but have superior resistance to material transfer and material loss due to arcing. They exhibit greater interface resistance between mated contacts, and a slightly greater contact assembly temperature rise. It is used for high ac loads because it is more resistant to welding at high switching current peaks. Material evaporates/wears evenly across the surface. It is not recommended for strong dc breaking arcs because of the resultant wear (one-side reductions). The minimum arc voltage rating of silver cadmium oxide is 10V, minimum contact load is 20V/50mA, and, like fine silver contacts, the silver in this alloy will oxidize and sulphidate. Therefore, an arc is necessary to keep the contacts clean. This contact material is being replaced by Silver Tin Oxide (AgSn02) and AgMe0. Silver Tin Oxide, AgSn02 Tin oxide makes silver more resistant to welding at high making current peaks. It has a high burn out resistance when switching high loads and a low degree of material migration under dc loads. Minimum contact load is 20V/50mA. Such properties are useful where high inrush currents occur, such as lamp loads including fluorescent lighting. Silver Tin Oxide is frequently chosen as the replacement relay contact material for Silver Cadmium Oxide, which is being withdrawn. Silver Tin Indium Oxide, AgSn0In0 Silver tin indium oxide contacts, although not readily available, exhibit better resistance to arc erosion and welding than silver cadmium oxide contacts. They are less electrically conductive and are harder than silver cadmium oxide contacts. They have greater interface resistance between mating contacts and, therefore, a greater voltage drop and temperature rise. Silver tin indium oxide is more expensive than silver cadmium oxide, and the relay is limited to use in applications such as incandescent lamp loads and capacitors where there is an inrush current during contact bounce. For low and medium power resistive and inductive loads, silver cadmium oxide is most commonly used. Properties are similar to Silver Tin Oxide but it is more resistant to inrush. Minimum contact load is 12V/100mA. Silver Copper Nickel, Ag (97-98%), Cu+Ni The copper and nickel contents give the hardness. Single contact minimum load is 20V/50mA. Silver copper nickel contacts are for use in high inrush dc applications such as incandescent lamps and capacitive loads. These contacts exhibit good resistance to welding, with a long contact life, but tend to oxidise at higher temperatures. Gold Silver Nickel Alloy Gold silver nickel alloy contacts are used for switching loads generally of less than 1A, and are characterized by less electrical noise on make and break than fine silver contacts. Gold diffused silver contacts offer characteristics similar to gold silver nickel alloy, but are less expensive. Other gold-based alloy contact materials include AuPd (Pd 1W 1V - 150V 50mA - 5A

6V - 380V 10mA - 100A

6V - 24V 5A - 20A 12V - 380V > 0.5A > 10 W > 12V - 380V > 0.5A > 10W > 60V > 1A > 50W

Power Electronics

3

10

2

10

1

AgCdO

AgNi

PtNi PdNi PdCu

Rh 0

10

-1

10

-2

10

-3

10

-4

10

-5

10

-6

Au

Open or non-activated

Contact open

Coil current

Final actuation time

Bounce time 10

-4

10

-2

10

Current

10

I

0

2

10

(A)

Figure 28.1. Low voltage and current contact materials.

time

t

time

t

closed or seated armature

Operating time

-6

External circuit and L-R dependant no coil current

Open or at normal

Contact closed

AuPd

AuNi5

Voltage

Steady state current

L/R and voltage

Ag AuAg8

Make contact Current

V

10

1298

Seating time

Break contact Current

(V)

Mercury, Hg Mercury has a melting temperature of -38.9°C. Thus, as used in relays, it is in a liquid state. Mercury clings to the surface of any clean metal, and is used as the contacts in mercury-wetted reed relays. It has good electrical conductivity and, being liquid, there is no material transfer build-up from contact to contact. Any such material transfer is negated by the fact that when the contacts open and the mercury returns to the pool in the bottom of the relay, fresh mercury takes its place at the next switch operation. Mercury has a boiling temperature of 357°C. Because of this, mercury contacts cannot switch currents of more than a few amperes.

10


Chapter 28

Armature position

1297

Contact closed

normally open (make)

Chatter, dynamic resistance or grass

Release time

Bounce time

Final actuation time

normally closed (break) contact

Contact open Possible bounce time

Contact closed Chatter

Chatter Operate time and actuation time

Chatter

Contact open Contact open

time

Release time

t

Bounce time

Final actuation

The electrical life expectancy of general purpose and power relays is normally rated to be 100,000 operations minimum, while mechanical life expectancy may be in excess of one million operations. The reason electrical life is rated so low compared with mechanical life is because contact life is application dependent. The electrical rating applies to contacts switching their rated loads. Rated electrical life also takes into consideration arc destruction of the contacts. By the use of appropriate arc suppression, contact life may be lengthened. Contact life is terminated when the contacts stick or weld, or when excessive material is lost from one or both contacts and a good electrical make is not possible. These conditions are the result of cumulative material transfer during successive switching operations, and of material loss due to splattering. Material transfer occurs due to Joule I2R heat. Material loss is due primarily to splattering of the molten and boiling metal as contacts bounce on make. In dc applications, metal migration is predictable in that one contact is always negative, and the other, positive. In ac applications where switching is at random, either contact may be negative or positive when arcing occurs. Migration will not be in the same direction each time the contact breaks, and material loss from either contact should not be significant, unless load conditions cause splattering. Controlled arcing of short duration can be beneficial in achieving the rated life of the contacts, because such arcing burns off any deposits on the contacts that might prevent electrical make. Such control is achieved by arc suppression. Unless arcing and/or contact over-travel cleans the contacts, films may develop on the contact surfaces, or foreign matter may collect. For this reason, it is best to apply general purpose and power relays only in applications where the load voltage (or counter emf) and current are in excess of the arc voltage and current ratings of the contacts. A method of quenching an arc between separating contacts is with an RC network placed directly across the contacts. As the contacts just begin to separate and an arc ignites, load current feeding the arc is shunted into the capacitor through the series resistance, depriving the arc of some of its energy. As a result, arc duration will be shortened and material loss will be reduced.

Break-Make contact Current

28.2.3 Contact Life – material loss and transfer break contact closed

transfer (break-make) contact

Chatter Transfer time Initial actuation time operate time

Chatter, dynamic resistance or grass Break contact closed

Chatter

time

Chatter Make contact Closed Bounce time

Final actuation time (a)

Initial actuation time

transfer time

Release

Bounce time

Final actuation time (b)

Figure 28.2. Voltage and current waveforms typical of relay (a) pick-up and (b) drop-out. Contact currents for non-inductive load

28.3

Defining relay performance

There is a sequence of events in relay pick-up (operate) and drop-out (release) with respect to current rise and decay. The events are defined in terms of duration of coil current, armature motion, and contact actuation. Figures 28.2 (a) and (b) show contact performance as a series of time domain waveforms, for a relay with a normally open contact, a normally closed contact, and a transfer (break-make) contact. Figure 28.3 shows the relationship between parameters defining relay performance and their definitions, which follow.

t

Power Electronics

drop-out specified

12V

Rated Tamb, top

-25

0

25

0

Relay will never pick-up

ng nt asi rr e cr e cu de e or ltag vo

vo Inc ltag rea e o sin rc g urr en t

Ambient temperature

time

Figure 28.3. Graphical presentation of relay performance related definitions.

Pick-Up (figure 28.2a): Upon coil energization, current begins to rise exponentially at a decreasing rate, but no armature movement occurs until the power develops sufficiently to operate the contact spring load. This period is sometimes referred to as waiting time. Contact actuation occurs during the armature movement. The final actuation time exceeds the initial actuation time by the amount of the contact bounce. For normally closed contacts, operate time and initial operate time are identical. On break-make contacts, the time interval between initial opening of the normally closed contact and closure of the normally open contact is called transfer time. Drop-out (figure 28.2b): On de-energization of the coil, the magnetic flux does not cease immediately. The length of time it persists depends upon the release characteristics of the coil (fast-to-release, slowto-release, and the like). The sequence of events described under pickup is essentially reversed under dropout. A normally open contact may be momentarily re-closed as a result of armature rebound off the backstop. This effect, which is not always present, depends on many factors, such as contact spacing, contact spring load, backstop design, etc. Closing Arc As a contact is activated, and two points come together to carry current, an arc forms. This causes material to evaporate, and if high transient currents are present (say starting a motor or a fluorescent lamp) then large portions of the contact surface may melt causing the contacts to weld. The process is reinforced by contact bounce. As the contacts close, the arc is suppressed; it appears as a peak. Opening Arc To break a circuit, a contact will open. As it does, the effective contact surface is reduced due to the decreasing contact force and movement. The current flow is the same, and therefore the current density in the remaining pathway increases up to the melting point. An explosion like process can occur as the contact material springs out. An arc may be produced by: • resistive and capacitive loads in conjunction with high voltages • inductive loads Permanent or sustained arcs are produced mainly by dc currents. Alternating current quenches the arc when the current crosses the zero current level. Arcs are influenced by contact material, a reduction in arcing voltage and arcing current and the speed of the breaking elements. When switching high dc loads, a larger contact gap and blow out magnet may be critical.

16V

50

75

Tamb

(°C)

(ms) t release Contact release time

hold range Relay pick-up uncertainty

9V

Co il ope ra tin g voltage

(m s)

hold specified

pick-up range

non-pick-up specified

1300

Relay switching performance is affected by high ambient temperatures (as shown in figure 28.4), humidity, dust, and contaminant gases. A relay itself creates heat and oxidants as it operates. The other influencing factors on relays electrical service life is the arc produced when the contacts open and close. Contact friction, clearance mechanical quality, etc. are of lesser significance.

t op

Relay will always pick-up


Chapter 28

Cont act ope ra tin g time

ng nt asi rr e cr e cu de e or ltag vo

pick-up specified

vo Inc ltag rea e o sin rc g urr en t

1299

Rated Tamb, tde

-25

0

25

Ambient temperature

50

75

Tamb

(°C)

Figure 28.4. Contact operate and release time dependence on coil temperature.

28.4

AC and DC relay coils

i. AC across a DC coil relay In theory, ac can be used to operate a dc relay but this is not so in practice. Since alternating current decreases to zero every half-cycle (100 times per second for 50Hz voltage or 120 times per second for 60Hz voltage), the relay armature tends to release every half-cycle. This continual movement of the armature not only causes an audible buzz, but will cause the contacts to open and close as the armature moves. In order to operate a relay from ac, a device known as a shader ring (or shader coil) is used on top of the core. Because of the shader ring, the magnetism developed in part of the core lags the magnetism of the remainder of the core. That is, there is a slight phase displacement between the magnetism of parts of the core. Thus, as unshaded-core magnetic energy decreases to zero every half-cycle, the magnetic energy decreases to zero every half-cycle, the magnetic energy still present in the shaded portion of the core holds the armature sealed. By the time the energy in the shaded portion decreases to zero, coil and unshaded core magnetic energy have begun to increase once again as current increases in value. ii. DC across an AC coil relay An ac relay may be operated from dc provided two precautions are taken. i. The first precaution is to provide some type of a residual break between relay core and armature to prevent the armature from sticking as a result of any appreciable residual magnetism remaining in the core after coil power is removed. AC relays are so constructed that when the armature is in its seated position, it physically (magnetically) touches the core. (On dc relays, a small copper pin in the armature effectively prevents the armature from coming in magnetic contact with the core.) As long as the ac relay is operated from AC voltage, there is no problem with residual magnetism holding the armature seated after release of coil power. But when an ac relay is operated from dc voltage, there is a danger that residual magnetism may hold the armature seated. At the very least, the presence of residual magnetism in the core causes a reduction in the dropout voltage of the relay. To negate the effects of residual magnetism, a small piece of mylar tape may be stuck to the top of the ac relay core. This tape is extremely durable, and should last for perhaps hundreds (if not thousands) of operations. The tape is 0.05mm to 0.1mm thickness. ii. The second precaution to be taken is to ensure the dc voltage used is less than the ac voltage rating of the coil. To use an ac coil on dc requires lowering the amount of dc voltage to that value where coil power is within maximum limits. When using rectified ac to operate any relay coil, it is best to use capacitive filtering to reduce the voltage ripple to less than 25%

1301

28.5

Power Electronics

Chapter 28

Temperature consideration of the coils in dc relays

Relays and temperature are intertwined, where a rise in temperature causes a rise in electrical resistance. When a relay is exposed to various temperatures, its operating characteristics, specifically here, pull-in and dropout, change dependent upon the temperature. The most notable changes occur in the pick-up voltage VPI and coil resistance RC. The coil winding of a relay is produced with copper wire and thus the coil resistance varies with the temperature coefficient of copper. For the temperature range that a relay will normally be exposed to, the resistance change in copper is of the form: R1 = Ro × (1 + α × ∆T ) (28.1) where: R1 = Resistance at temperature T1, Ω Ro = Resistance at temperature To, Ω ∆T = T1 - To, change in temperature from To, °C α = Slope of a line from a point (-234.5, 0) through the point (To,,1) α = 0.003929 at To = 20°C or 0.003853 at To = 25°C, °C-1 T1 = New operating temperature, °C To = Reference temperature, where 20°C or 25°C are typically used references, °C

(28.3)

where: TRC = Temperature rise caused by coil power dissipation, °C RθCA = Thermal resistance from coil to ambient, °C/W Pd = Steady-state power dissipated in the coil, due to coil resistance RC and coil voltage VA, W For normal relay temperature ranges, this relationship is nearly linear and consistent under the following conditions: • The relay is in still air and not subjected to significant airflow or the value of θCA was determined with an airflow identical to the end application. • All power calculations deal with the coil resistance at the final coil temperature TC attained. If only room temperature coil resistance were used, the resulting non-linearity would result in significant errors at higher temperatures. The value for thermal resistance is specified when the relay carries no load current. The final coil temperature can be calculated using manufacturer’s parameter data under no load relay conditions. Under contact load conditions, the contact power dissipation may be treated as a separate heat source that adds heat into the relay package. Its effect on coil temperature is dependent upon many factors including package size, contact to coil distance, contact terminal size, connecting wire size, shared thermal paths, etc. These factors can be lumped into a contact to coil thermal resistance, which leads to T RL = Rθ CC × PK = Rθ CC × I L2RK (28.4) where: TRL = Temperature rise caused by load dissipation in the contacts, °C RθCC = Thermal resistance from the contacts to the coil, °C/W PK = Power dissipated in the contacts, W RK = Resistance of contact circuit, assumed temperature independent, Ω IL = Load current flowing through the created by the contacts, A

Based on practical data, the contact temperature rise can be approximated by T RL = k R I IL1.85 (28.5) The final coil temperature rise above ambient, is the sum of the two heat source components, selfheating and that due to contact heating, namely T C = T A + T RC + T RL = T A + Rθ CA ×

V A2 + k R I IL1.85 RC

(28.6)

For a dc relay under the following no-load conditions: To = 20°C, Vo = VPI = 6.8V, Ro = 90Ω, VA = 13.5V(the applied coil voltage) Il = 0A (no load current) RθCA] = 40°C/W, TA = 85°C,

While temperature changes affect relay parameters, the power dissipated within the relay also affects the temperature in most applications. The power dissipated within the relay comprises a number of components. Heat generated in the relay coil when voltage is applied to it. This heat creates a temperature rise in the relay coil and package. The temperature rise is dependent upon several factors such as the volume of copper wire used, insulation thickness, insulation type, bobbin material, bobbin thickness, terminal size, conductor size, and several other factors that are design related. Each of these factors will either enhance or resist the flow of generated heat from the coil assembly and into the ambient air. For a given relay design, these factors can be accumulated into the ‘coil to ambient thermal resistance’ of the relay, in °C/W. The thermal resistance is analogous to the electrical resistance and the temperature rise created by coil power dissipation follows the equation:

T RC = Rθ CA × Pd = Rθ CA

1302

Example 28.1: Relay coil thermal properties

For a dc relay, the magnetic force developed is proportional to the Ampere-turns developed in the coil. Since the mechanical forces are nearly constant over the normal temperature range (and the number of turns is fixed), the pick-up current, IPI, will be constant. If pick-up current is constant and coil resistance varies, the pick-up voltage, VPI = IPI x RC, varies directly as the coil resistance. This leads to a simple mathematical method to determine coil resistance and pick-up voltage VPI1 at any temperature if a reference point VPIo is known. VPI 1 = VPIo × (1 + α × ∆T ) (28.2)

V2 × A RC


determine: i. Cold-start pick-up voltage (with the coil previously un-energized) and coil resistance at TA ii. Final steady-state coil temperature TC and resistance for an applied coil voltage VA iii. Hot-start pick-up voltage (after coil energized at VA) at TA and VA; and iv. for a 20A contact load, with kR = 0.29 modelling the relay contacts, determine the new steadystate thermal operating conditions. Solution The pick-up current is virtually independent of thermal conditions since it is based on magnetic circuit Ampere-turns. Therefore the expected coil current is VPI / Ro = 6.8V/90Ω = 75.56mA, at all operating temperatures. i. The resistance at an operating temperature of 85°C is given by R1 = Ro × (1 + α × (T 1 - T o ) ) = 90Ω × (1 + 0.003929 × (85°C - 20°C) ) = 90Ω × 1.2554 = 113Ω The voltage at this temperature is obtained using the same scaling factor since the necessary current is assumed independent of temperature. V1 = Vo × 1.2554 = 8.54V 2

ii. Since TC = TA + TRC and Pd = VA / RC then

T C = T A + Rθ CA ×

V A2 RC

= 85°C + 40°C/W ×

13.5V 2

RC

Since RC is temperature dependant, an iterative solution is necessary to determine TC and RC. After several iterations TC =140°C, which leads to a coil resistance at this temperature of RC = Ro × (1 + α × (T 1 - T o ) ) = 90Ω × (1 + 0.003929 × (140°C - 20°C) ) = 90Ω × 1.4715 = 132.4Ω

iii. The hot-start relay pick up voltage is therefore V1 = 6.8V × 1.4714 = 10.0V Thus the necessary ampere-turns relay coil current is 10.0V/132.4Ω = 75.58mA, independent of temperature. iv. For a 20A load current through the contacts:

T C = T A + Rθ CA ×

V A2 + k R I IL1.85 RC

= 85°C + 40°C/W ×

13.5V 2

RC

+ 0.029 × 201.85

1303

Power Electronics

Again, since RC is temperature dependant, an iterative solution is necessary to determine TC and RC. After several iterations TC =146.5°C, which leads to a coil resistance at 146.5°C of RC = Ro × (1 + α × (T 1 - T o ) ) = 90Ω × (1 + 0.003929 × (146.5°C - 20°C) )

Chapter 28


1304

problem, the relay (except in the case of PC board applications where either may be used). Better switch transient voltage protection is afforded when the suppression circuit is across the controlling switch, as shown in figure 28.5. Suppression used in parallel with the switching element is likely to be either a Zener diode or a series resistor-capacitor snubber. The Zener diode control is most advantageous since it does not significantly reduce relay endurance.

= 90Ω × 1.4970 = 134.73Ω The hot-start relay pick up voltage is therefore V1 = 6.8V × 1.4970 = 10.18V Thus the necessary ampere-turns relay coil current is 10.18V/134.73Ω = 75.56mA, independent of temperature. ♣

Vs Relay coil

switch

The values obtained in example 28.1 apply to dc relay coils operated continuously at these values. Intermittent duty (with short, that is, less than one minute, on-times and longer off-times) may result in substantially lower temperatures. Therefore, if a specific duty cycle is given for the relay operation, testing at these conditions could yield acceptable results for final coil temperature when the continuous duty temperatures calculated in example 28.1 would not. The methods discussed are applicable to standard dc relays and while the coil resistance formula is applicable to polarized dc relays (one that utilizes a permanent magnet) and ac relays as well, the pick-up voltage equations will not work in such cases. With a polarized dc relay the temperature induced change in magnetic force of the magnet must be considered. This is normally such that it reverses part of the change in pick-up voltage caused by the copper wire resistance. In the case of ac relays, the inductance contributes a significant portion of the coil impedance and is related to the turns in the coil. Since the inductance varies only slightly with temperature, the pick-up voltage exhibits less variation over temperature than for dc coil relays. 28.6

Relay voltage transient suppression

Voltage suppression is applicable to relay coils and relay contacts. The circuitry used is similar for each suppression case. Although coil voltage suppression is used extensively, relays are normally designed and specified without taking into account the dynamic impact of suppressors. The optimum switching life (for normallyopen contacts) is therefore obtained with a totally unsuppressed relay and rated electrical life factors are then based on this premise. Improper relay coil suppression has the typical symptom of random tack welding of the normally-open contacts when switching an inductive load or high inrush currents like with a lamp load. The successful breaking of a dc load requires that the relay contacts move to open with a reasonably high speed. When an electromechanical relay is de-energized rapidly by a mechanical switch or semiconductor, the collapsing magnetic field produces a substantial voltage transient (V = Ndφ/dt) in an effort to release the coil stored energy (W = ½LI2) and oppose the sudden change of current flow. A 12V/28V dc relay coil, for example, may generate a voltage of over 1kV during unsuppressed turn-off. This relatively large voltage transient can create EMI, semiconductor breakdown, and switch wear problems. It is thus common practice to suppress relay coil voltages with other components which limit the peak voltage to a controlled defined level. The measure of successful coil suppression depends on the degree to which the method affects the operation of the relay contacts. Improper or excessive suppression can cause the relay to suffer from a long release time, slow contact transfer, and contact bounce on break. All of these conditions will increase contact arcing when load switching, which reduces relay life. 28.6.1 Types of transient suppression utilized with dc relay coils Coil de-activation A typical relay will have an accelerating motion of its armature toward the un-energized rest position during drop-out. The velocity of the armature at the instant of contact opening will play a significant role in the relay's ability to avoid tack welding by providing adequate force to break any light welds made during the make of a high current resistive load (or one with a high in-rush current). It is the velocity of the armature that is most affected by coil suppression. If the suppressor provides a conducting path, thus allowing the stored energy in the relay's magnetic circuit to decay slowly, the armature motion is retarded and the armature may even temporarily reverse direction. Any direction reversal and re-closing of the contacts (particularly when combined with inductive loads) can lead to random, intermittent tack welding of the contacts such that the relay may free itself if operated again or even jarred slightly. The basic techniques for suppression of transient voltages across relay coils are based on the suppression device in parallel with the relay coil or in parallel with the switch used to control the relay. It is normal to have the suppression parallel to the coil since it can be located closer to the source of the

Breakdown diode 0V Figure 28.5. Indirect coil voltage suppression.

When the suppression is in parallel with the relay coil, any of the topologies in figure 28.6 may be used. i. A reversed-biased rectifier diode. ii. A bilateral transient suppressor diode that is similar in V-I characteristics to two Zener diodes series connected cathode to cathode (or anode to anode). iii. A metal-oxide-varistor (MOV). iv. A reverse-biased rectifier diode in series with a Zener diode such that their anodes (or cathodes) are common and the rectifier prevents coil-activated current flow. The Zener voltage is two or three times the level of the nominal voltage of the relay. v. A reversed-biased rectifier diode in series with a resistor. vi. A resistor, when loss conditions permit its use, is often the most economical suppression. vii. A series resistor-capacitor snubber. Generally the least economical solution, figure 28.6e. viii. A bifilar wound coil with the second winding and series diode used as the suppression circuit. This is not practical since it adds significant cost, losses, and size to the relay. i. Diode clamped coil A diode as in figure 28.6a clamps the cut-off spike to approximately 0.7V. However, the energy maintained by the continued current flow increases the release time. Some relays can reverse their armature movement direction when returning to the rest position due to a current flow increase. This can causes the make contact to close again under certain circumstances and can lead to an increased arc duration. This results in reduced endurance, hence the clamped diode configuration is not recommended for higher load currents. The use of a rectifier diode alone to provide the transient suppression for relay coils may be cost effective and eliminates any transient voltage, but its impact on relay performance can be devastating, since the flux producing Ampere-turns decreases slowly, increasing the de-energized time. Problems of unexplained, random tack welding can occur. In some applications, this problem is only a minor nuisance or inconvenience and the relay can be cycled until the proper response is obtained. In some applications, the first occurrence of welding may cause a complete system failure or even present a hazardous situation. Energize time of a relay can be increased and high voltage transients eliminated with an inductor/diode combination placed between the power supply and the relay, as seen in figure 28.6b. ii. and iii. Silicon transient suppressor diode or MOV Based on armature motion impact and optimizing for normally open contacts, the best suppression method is to use a silicon transient suppressor diode, as shown in figure 28.6c. This suppressor will have the least effect on relay dropout dynamics since the relay transient will reach and be maintained at a predetermined voltage level and permits coil current to flow into a low dynamic impedance. This results in the stored energy being quickly dissipated by the suppressor. Bi-directional transient suppressor diodes permit the relay to be non-polarized when installed internally. If a uni-directional transient suppressor is used, it must be used with a series rectifier diode to block normal current flow and it has little advantage over the use of a Zener diode, as in figure 28.6d. The transient suppressor should be selected such that its pulse energy rating exceeds any anticipated transient, such as coil turnoff or motor ‘noise’. MOVs produce virtual identical waveforms as silicon suppression diode, but MOV clamping properties can deteriorate with continuous electrical stressing.

Power Electronics Relay contactor

Vs Freewheel and clamping diode

Relay coil

(a)

switch

(b)

switch

0V

0V

(c)

switch Relay coil

(e) optional Zener or resistor

switch MOV TVS

dc power source

Relay coil

Diode

switch ac or dc power source

Relay coil

R

A method to regulate the power consumption of a source supplying as relay is with a dc current driver, since the main electrical parameters of a relay (pull-in, pull-through and holding currents) are to a certain extent temperature independent. Since relay coils are usually voltage driven, those characteristics translate into the temperature dependent voltages for pull-in, pull-through and holding, due to the temperature dependence resistance of the coil copper wire. Once the relay has pulled in, it maintains this status (armature maintains the contact position on the core) unless the coil current falls below the holding current, as shown in figure 28.7. For shock and vibration tolerance, there is an overhead current required, which depends on the relay type, relay parameters, temperature variation, and shock and vibration requirements. PWM controlled drivers regulate the effective applied voltage by changing the fixed frequency duty ratio of dc voltage. Inductive systems like relay coils, in the presence of parallel connected freewheel components, respond to a negative going voltage edge with an exponential current decay. Relay coil inductances are relatively high, with low resistance, which results in comparatively long time L/R constant hence small current ripple. But the R and L values are not constant. The relay coil inductance depends on the coil current (saturation) and status of the relay (armature open or closed). The copper coil resistance is highly temperature dependant.

C

Relay contactor

Figure 28.6. Various relay coil voltage suppression techniques.

iv. Zener + diode If back EMF suppression of the relay coil is needed, use a Zener-Zener or diode-Zener series (figure 28.6d) combination with a Zener voltage at least twice the coil source voltage. The use of a reversedbiased rectifier diode in series with a Zener diode will provide the best solution when the relay can be polarized, since the Ampere-turns is reduced rapidly. In relay carry-only applications, the release time may not be important and less expensive coil suppression techniques can be used. However, if the release/reset time is important, or if the contacts are to interrupt a load, then the Zener-Zener or diode-Zener combination may not be applicable. v. Parallel resistance The parallel resistance should be so rated that its value corresponds to approximately six times the coil resistance. In this way, the external cut-off spike is limited to three times the operating voltage. At a nominal voltage of 12V, the external spike can be contained to less than 36V. At a cost increase, coil activation losses can be reduced by adding a series diode, as indicated in figure 28.6d. Table 28.2: The effects dc coil suppression on relay drop-out time Suppression technique

Drop-out Time

Theoretical Transient

ms

V

1.5

undefined

Diode + 24V Zener

1.9

-24.8

680Ω resistor

2.3

-167

82Ω resistor

6.1

-20.1

Diode

9.8

-0.8

Unsuppressed

These suppression techniques are based on normally-open contact performance, and must be qualified for normally-closed contacts. When the primary load is on, the normally-closed contacts (and a small load or none on the normally-open), it may be desirable to use a rectifier diode alone as relay suppression (or perhaps a rectifier diode and a lower value of series resistor). The retarded armature motion that adversely impacts normally-open contact performance will typically improve normally-closed contact performance. Improved performance results from less contact bounce during closure of the normally-closed contacts. This results from the lower impact velocity created by the retarded armature motion and can be utilized to improve normally-closed contact performance on certain relays. Table 28.2 show how increased coil reset voltage decreases relay drop-out time.

Freewheel and clamping diode

coil voltage

Vs

Relay coil

PWM

switch

Coil current

ac or dc power source

(d)

1306

Pulse Width Modulation (PWM) and relay coils

Vs

Relay coil


Chapter 28

gate volta ge

1305

0V

holding level

time

t

Figure 28.7. Coil current response to a PWM voltage, with a parallel freewheel diode.

Alternatively, using a series diode-Zener increases the ripple current, which must not fall below the minimum holding current level, as occurs in figure 28.7. Coil activation The definition of operate time is the interval between the application of the nominal coil voltage and closing of all normally open contacts (or opening of all normally closed contacts). This includes: • Time for the coil to build up the magnetic field due to the increasing current. • Transfer time of the moveable contact. • Bounce time after the initial make or break. Vs

Relay contactor

Relay coil

switch Breakdown diode 0V Figure 28.8. Reduction of relay activation time

1307

Power Electronics

Operate time is essentially a function of the coil power (specifically current, Ampere-turns) and inductance (L/R time constant). Standard circuit techniques can be used to alter relay timing characteristics. More than half of the switching time is taken to build up the coil field, thus the basic scheme for reducing operate-time is to apply more voltage across the coil. Faster relay operating speed can be accomplished by overdriving the coil with a higher than nominal voltage. For example, a 28V dc coil should not exceed 35V dc for continuous duty. To prevent overheating, the coil voltage should be reduced to the nominal value (or above the holding current level) shortly after the relay operates or a resistor equal to or greater in value than the coil resistance should be placed in series with the coil to keep total power applied at the specified level. Doubling the nominal voltage and adding an external resistor equal to the coil resistance can reduce the operate time by 40%. A fast operating speed can be achieved by using an over-voltage pulse that decays to normal operating potential in a few milliseconds, as shown in figure 28.8, which achieves this with a simple parallel RC network placed between the power supply and the relay coil.

The main drawback of any relay contact protection circuit that restricts the arc voltage, is increased release time. Protection (rectifier) diodes have a breaking voltage peak of 0.7V, and no effect on making behaviour but do delay drop out by a factor of 3 or 4 times. Vacuum and hydrogen gas-filled relays have some significant inherent advantages in switching high current dc loads. These include: • Long load life due to ability to use high temperature contact materials • Low contact resistance due to the elimination of contact oxidation/contamination • Light weight and small size due to small contacts and short contact gaps • Low coil power due to optimized magnetic circuits and small size • High integrity, durable ceramic to metal hermetic seals

1308

Hermetically sealed dc relays rated at 320V dc are available for lower dc voltage power applications, for example in electric vehicles and aircraft (see section 28.13).

Load ac or dc power source

Relay contacts

Relay contacts

MOV or TVS (a)

Load

28.6.2 Relay contact arc suppression protection with dc power switching relays Transient and arcing occurs during relay make (close), break (open) and contact bounce. Arcing can drastically lower the life expectancy of relays. Over 70% of relay failure occurs at the contacts. The most prevalent relay failure mechanisms are increased contact resistance, contact contamination, and material loss. Relay contact life expectancy is commonly a function of how much arcing can be withstood before failure occurs. Arc duration is often determined by the contact separation speed. Arcing, particularly during switching of inductive loads in high-voltage circuits, can be extremely destructive. To achieve maximum contact life, reliable arc suppression is important. It is difficult to prevent all arcing, but employing an arc suppression circuit will extend contact life. Vacuum and hydrogen gas filled relays and contactors are often use in direct current electrical systems. Switching a direct current load is onerous on a relay. The relay or contactor needs to clear the maximum fault current, which is usually several times higher than the normal load. Unlike ac power, where both voltage and current regularly pass through zero allowing the arc formed during switching to naturally extinguish, a dc load can only be interrupted by forcing the arc voltage higher than the effective source voltage. A number of mechanisms are used to increase the arc voltage, ranging from arc chutes or multiple contacts, to magnetic blow-out, which lengthens the arc path. Power switching relays are designed to interrupt rated power. However, reactive inductive loads can result in significant voltage overshoot, which can be suppressed by a variety of measures, usually more robust than the method used for relay-coil voltage suppression. Figure 28.9 shows methods used to reduce the load on contacts by limiting the peak voltage transient developed across the relay contacts when interrupting inductive loads. The same circuits across the load will protect the load and contacts from voltage overshoot. • Figure 28.9a shows a metal oxide varistor (MOV) across the power contacts. This circuit is suitable for most general-purpose ac and dc applications and MOV selection depends on transient energy, etc. MOVs are compact in size and low in cost. They protect from high breaking voltages with minimal additional drop out delay. They have limited switching frequency and are optimised for a specific voltage. Suppression diodes perform similarly. See chapter 10.X. • Figure 28.9b shows an MOV in series with an SVP (Surge Voltage Protector - spark gap). The MOV absorbs transient overshoot energy, the SOV provides excellent dielectric isolation once the circuit is open. This solution is also compact in size and low cost. See chapter 10.X. • Figure 28.9c illustrates the use of a traditional RC snubber, which will suffice for low power and energy ac and dc situations, but suffers a size and cost penalty at high power. RC elements are bidirectional, with minimal drop-out delay. A low overvoltage can be achieved, but is not suitable for low voltages. A disadvantage is a capacitor can lead to high making currents.


Chapter 28


Relay contacts

Spark gap


Relay contacts

Load

Relay contacts

MOV (b)

Load


cc power source

Load

Relay contacts

R C (c)


Load

MOV or TVS

Zener Diode

R C

Figure 28.9. Commonly used relay contact (direct and indirect) protection circuits.

28.7

DC power switching

i. Low-voltage power relays Relay loads are classified into four ranges. The load and voltage range definitions are: • Dry circuit is defined by 0 ≤ V ≤ 30mV and 0 ≤ I ≤ 10mA. The softening voltage U of the contact material is not reached. • Low load U ≤ 20V and I ≤ 100mA. • Intermediate load U ≤ 50V and I ≤ 1A. • High load U ≤ 250V and I ≤ 1A. Dry circuit loads: No current is switched. The contacts carry current only after they are closed or before they are opened. The currents may be high, but are not switched. The maximum voltage applied is less than the softening voltage of the contact materials. Usually loads up to a maximum of 30mV/10mA are considered dry circuit loads. Since there is no arcing, contact resistance is kept low by using gold plating or gold alloy contacts. An increase in the contact resistance can only occur due to corrosion or polymerization. Switches with gas-tight housings can perform more than 200 million operations, switching dry circuit loads, without a change in contact resistance. Low Loads: During contact break, the temperature in the constriction area increases to the melting and then boiling temperature of the contact material. Even though the open circuit voltage is lower than the minimum arc voltage, short arcs with low energy still occur due to inherent inductance and capacitance. Consequentially, carbon forms on the contacts (due to atmospheric hydrocarbons) but the arc does not have enough energy to remove the carbon. The sliding of the contact surfaces causes polymerization of the organic compounds with the result that deposits with high, unstable resistance are left on the contacts. This is a particular problem with metals of the platinum family. Typically, carbon or carbonized contacts have contact resistance between 2 and 4 Ohms. The solution is to use gold or gold alloy platings on the contacts. Intermediate Loads: For intermediate loads, short arcs and discharges from cables are the most common effects. Current is below the minimum level for even momentary arcing when the contacts are open. Loads of 50 to 400mA at 26V are typical for this range. Some arcing can occur during the make or break of the contacts, but extinguishes itself by contact transfer completion. This arcing is

usually just enough to carbonize any organic vapours present. The carbonized material eventually deposits on the contacts and contact resistance increases, possibly leading to failure. The objective is to minimize the amount of organic vapours by the choice of insulation, potting compounds, and cleaning agents.

(A)

(A) Contact current

Medium voltage applications (typically < 1,800V) Both vacuum and hydrogen filled relays are suitable for power switching applications at 1,800V dc and below. Vacuum relays typically have a longer life cycle rating than hydrogen filled relays, but do not carry or interrupt as much current. The most important parameter is the current the relay will be required to switch during ‘abnormal’ switching conditions. The relay may have to interrupt the entire current capacity of the system before a circuit breaker or fuse has time to function. An incorrectly selected relay could be vaporized during opening, resulting in electrical shorts within the system. Whenever a relay is power switched, an arc is generated. The arc duration and the current and voltage levels are critical factors in determining relay life and reliability. Whenever a relay is required to switch a load, there are several precautions that should be taken to ensure a satisfactory result. These are: 1. Circuit load elements can generally be characterised as basically capacitive, inductive, or reactive, even though they may be comprised of both active (tubes and solid-state devices) and passive elements (capacitors, resistors, inductors, etc.). Circuits with capacitive or inductive elements are more difficult to switch due to the reactive stored energy. Switching these different types of loads has a specific effect on relay voltage.

I

t

(A)

(A)

Make

break

charge

I

Break discharge

time

t

make

(A)

Misapplication of high voltage relays occurs most commonly in power switching applications. Since most relays are used only to isolate the load, it cannot be assumed that the rated carry current is the power switching rating. High voltage applications (typically above 1,800V) Make only applications - select a SF-6 gas filled relay whenever possible, since such relays are designed specifically for high voltage applications, but generally are not suitable for breaking the load. Make and Break applications - select a vacuum relay that has contacts made of a material with a high melting point, such as tungsten or molybdenum. Some vacuum relays have copper contacts for high current carry applications, and are not suited for power switching. In a vacuum relay, part of the contact material vaporizes during power switching and deposits itself on the inside walls of the relay. When this occurs, the dielectric stand off voltage decreases (leakage current increases) with the number of power switching cycles, possibly making it unsuitable for the application. The power switching rating of a vacuum relay is therefore dependent on the power to be switched, the number of cycles, the dielectric stand off voltage, and the maximum circuit leakage current allowed.

t

time

Contact current

There are two types of relays for hot-switching Make only relays, with pulse currents of up to a few kilo-amperes, with durations less than a few milliseconds Power switching relays, for current up to 150A.

time

Contact current

break

I

ii. Higher-voltage power relays Depending on the type of switching, higher-voltage power relays can be divided into two categories Cold-switching of high voltages 12 to 70kV (no current during contact movement) Hot-switching with voltages up to 25kV (current flow, hence arcing, during contact movement)

break

make

make

Contact current

Mixed level switching: In different applications, monitoring the contact position in the load circuit is required. The synchronised failsafe coupling between two different contacts is realized in safety relays by applying forcibly guided contacts. For example, one contact is used to switch the load, and another is in the load circuit. The power in the load circuit depends on the application and variants between mW and kW (kVA). The control circuit is normally on the logic level of devices such as FPGAs or ASICs. A frequent issue is the separation of the contacts connected to power from those connected to the control circuit. The switching arc produces a splash of oxides and carbon particles which disperse in the area, for example, undesirably on to the contacts through which the control signal is carried.

1310

Resistive loads Circuits primarily resistive have minimal effect upon the voltage across hv contact terminals. In resistive loads, the duration of the arc is primarily determined by the speed at which the contacts separate, a shown in Figure 28.10a. The interruption of an ac load is easier on the contacts than a dc load since the ac interrupts itself each half cycle as the current goes through zero. Resistive loads are the standard against which other load types are measured, that is, relay load switch ratings usually assume a resistive load.

I

High Loads: Arcing Contacts. Arcing is detectable with all normal operational high loads. Typically, the voltage must be greater than 12V and the current must be more than 400mA for arcing to occur with most metals. The arcing actually serves a useful function, as it cleans the mating surfaces. Depending on the voltage and current, switched contact erosion or material transfer is the main effect. Contact materials such as silver-cadmium oxide, minimize electrical erosion at these load levels.


Chapter 28

(a) (c)

(b) (d) (e)

time

t

make

I

Power Electronics

Contact current

1309

break

time

t

Figure 28.10. Typical load profiles: (a) resistive load; (b) inductive load; (c) capacitive load; (d) lamp load; and (e) motor load.

Inductive loads With inductive load elements, a high momentary voltage transient occurs when the circuit current is interrupted, which decays rapidly to the open line voltage. Inductive loads in high voltage circuits can be destructive. The release of stored energy when the load current is interrupted serves to maintain the current, as shown in Figure 28.10b, and cause voltage spikes that can damage associated circuit components, including the relay. Inductive loads in ac circuits are less stressful than in dc circuits. However, in both cases, the inductive load should be suppressed at its source with an appropriate protective device. If the inductive load is properly clamped, it becomes, in effect, a resistive load.

Power Electronics

1311

Capacitive, lamp, and other high in-rush loads When circuits with large capacitive elements break, a negative bias voltage appears equal to the stored energy of the capacitor. This stored energy can cause a momentary high current surge upon contact make. When switching on a lamp, charging, or discharging a capacitor, the inrush current may be many times the steady state current, as shown in Figure 28.10 parts c and d. The primary concern with high inrush loads is that contact bounce and associated arcing can cause the relay contacts to weld when making the load. For this reason, power-switching type relays specifically for lamp or capacitor charge or discharge applications should be used. Normally the maximum interrupt rating is used to determine the correct relay for lamp applications. SF-6 gas-filled relays are usually the best choice for capacitor discharge applications. A typical contact current profile for the high inrush associated with electric motors, is shown in figure 28.10e. 2. Are voltage spikes present in the circuit? Minimal inductance can generate extremely high voltage spikes that can damage circuit components. For this reason, steps should be taken to clamp any inductance at its source. 3. Select a ground isolated relay for high voltage load switching, whenever possible. Relays which do not have an internal ground plane are known as ground isolated and when such a relay is used for load switching, the potential for ground faults is virtually eliminated. If a ground-isolated relay is not available, locate the relay on the ground side of the load, as shown in figure 28.10. Then the load will limit the fault currents in the event of an internal arc-over to ground in the relay. Power switching applications for high-voltage relays High-voltage power switching applications are those that require the relay to make and/or break the load - hot loads. In most applications, it is important to know the highest potential fault current to be encountered and how many times the relay or contactor will be required to clear the fault, since these specify the required relay. Load switching in ac circuits is less stressful on the relay due to the natural arc extinction that occurs as the current periodically passes through zero. Because of this, available relay ratings are much higher for switching ac circuit loads. Switching of direct current loads creates specific problems for relays and requires relays, contactors, and power controllers that have been specially designed to handle the arcing problems of dc switching. When load switching occurs at voltages above 1000V, the typical power switching lifetime derating curves in Figure 28.11a are applicable. Higher current affects relay ratings more than higher voltage, and the life expectancy for double throw, DT, relays is lower due to greater contact bounce.

(A)

99.9

28.8

The physics of vacuum high-voltage relays

In terms to contact loads, understanding can make relay selection less problematic, allowing the correct selection for a given application. Table 28.3 provides a comparison that indicates the best dielectric and contact materials for specific applications. Table 28.3: High-voltage relay performance comparison with different dielectric and contact materials Application

Carry Only (dc)

70

SF6 Gas

SF6 Gas

Vacuum

Vacuum

Tungsten/Molybdenum

Copper (special applications)

Tungsten/Molybdenum

Copper

Better Good than hard contacts but But the gas increases the the gas increases the contact resistance contact resistance resulting is less current resulting is less current being carried than in being carried than in vacuum vacuum

Good But not as much current as copper contacts

Best

No The gas will interfere with the RF carry capabilities

No The gas will interfere with the RF carry capabilities


Best

Make and Break

Good for make but only low currents on break

Good for make but only low currents on break

Best

Fair Extremely low currents only

Make Only

Best

Better But not as good as hard contacts


Fair Extremely low currents only

Best Only relays termed ’Make only’

Better than hard contacts but the gas increases the contact resistance resulting is less current being carried than in vacuum

Good Generally will ‘burp’ when HV is applied

Good Generally will ‘burp’ when HV is applied

Carry Only (RF)

Long periods of on-use

Low and stable leakage current is needed

%

10

1312

variety of manufactured devices will tend to lie in a straight line. As the chart in figure 28.11b shows, this data can then be interpreted to estimate the likelihood of failure at a given life.

or where 20


Chapter 28

I

5

1

1

2kV dc

0.5

Failure

Current

10

1 kV dc

2

0.2

0.1

0.01

0.1 3

10

5

10

Cycles N

6

10

1

10

100

Operating cycle life N

Figure 28.11. (a) Typical contactor lifetime derating with increased load switched current and (b) reliability analysis Weibull data plot of end of life failures.

Weibull plotting is used to predict product reliability. It is a simple and efficient way to predict reliability from a small number of life tests and it is widely used for this purpose. The cumulative percent failure is plotted against life. The Weibull scales (loge-loge scales) are designed so the failure data of a wide

A vacuum is an ideal dielectric. The dielectric strength of a vacuum is about 8 times greater than that of air. Since there is no oxidation in a vacuum, low resistance copper contacts (rhodium for reed relays) are used that allow the relay to carry significantly more current than traditional air exposed relays. Vacuum relays with copper contacts are termed carry only relays. Since most high-voltage arcs are initiated by the ionization of the insulating medium, a hard vacuum, which, by definition, is the absence of any such media, produces the greatest possible isolation between contact electrodes. It is possible to obtain dielectric strengths of 100kV per mm contact gap in a vacuum relay. A vacuum dielectric has the additional advantage of providing an inert environment in which highvoltage contacts can operate completely oxide-free. Thus, vacuum relays typically have a contact resistance, which is lower and more stable than other relay types. Voltage breakdown can occur even within an absolute vacuum when the contact material itself becomes the source of ionized material to support an arc. Because (in make and break modes) soft contact materials like copper and rhodium vaporize easily as the contacts switch and deposit on the inner walls of a vacuum relay, a ‘plating out’ of the walls occurs over time, resulting in dielectric breakdown. Therefore, high strength and high work function materials like refractory metals (tungsten, molybdenum, etc.) are commonly used for contacts in order to raise the electrostatic field strength necessary to cause voltage breakdown. In addition, refractory metals have high melting temperatures, which reduce contact damage from arcs and result in longer life.

Power Electronics

make

Open circuit voltage

23V 18V

time Arc time in a vacuum

t

Contact current

Contact current

I

I

(A)

Open circuit voltage

time

t

1314

28.9.2 Hydrogen as a dielectric Some relays use a proprietary gas mixture consisting of, primarily hydrogen at various atmospheres of pressure. These mixtures do not have the same high dielectric and low leakage current as a vacuum or SF6, so are not normally used for high voltage applications above 3 kV, but are ideal for dc make and break load switching applications. The gas mixture, combined with the use of external magnets to control the direction of the arc, cools and extinguishes the arc in a predictable manner. Because there is no oxygen in the mixture, more conductive contact materials such as copper can be used that provide the lowest possible contact resistance. The gas mixtures and magnets provide high current interrupt capabilities up to 3,500A at 320Vdc with switching capabilities as high as 1800V dc. They also offer the ability to handle highly inductive dc load switching. Hydrogen and nitrogen gas relays are compared in Table 28.4.

Arc time in a air

Figure 28.12. Comparison of Arcs in air and a vacuum.

In load switching, an arc will always be created at the point when the contacts are close enough to allow voltage breakdown. Vacuum arcs are sustained at the relatively low voltage of 18 to 23V compared to arcs in air which are more erratic and range over a wider voltage, as seen in Figure 28.12. Vacuum arcs tend to be more easily controlled and extinguished than arcs in air. The high-pressure region formed around a vacuum arc has a strong tendency to dissipate or blow out into the surrounding low-pressure vacuum. This phenomena, along with the ability to use contact materials like pure tungsten and molybdenum which have high melting points, means that vacuum relays and contactors typically experience much less contact erosion and have a longer life than comparable air-break devices. The resultant vacuum relays are termed make and break. 28.9


Chapter 28

(A)

1313

Gas filled relays

28.9.1 SF6 as a dielectric Some relays contain a proprietary gas mixture consisting of, mainly, sulphur hexafluoride at several atmospheres of pressure. Pressurized sulphur hexafluoride has good insulating qualities and comes close to achieving the same standoff voltage as a vacuum. These gas-filled relays are usually recommended when an application involves changing or discharging a capacitor especially when the voltage is greater than 1kV. SF6 under pressure has many advantages over a vacuum because the leakage current is stable over long periods of non-operation and because of the way the gas performs during switching. SF6 is an excellent insulator but when the relay is switched, ionization of the gas causes electrical continuity to occur before mechanical continuity is achieved. If the relay bounces the SF6 becomes easily ionized and carries the arc current. This makes the relay electronically bounceless and dramatically reduces contact wear, which contributes to the long life that these relays exhibit in capacitive make and break applications, and reduces electrical noise during switching. These SF6 gas filled relays with hard contact materials are termed make only relays. However, this tendency to ionize makes gas-filled relays unsuitable for applications which require interruption of a load. There are two significant shortcomings to SF6 gas-filled relays: • Due to a film that forms on the relay contacts, SF6 gas-filled relays have a higher and less stable contact resistance at low voltages than vacuum relays. Contact resistance is typically between ½Ω and 1½Ω when measured at 28V dc on new relays. However, even in applications up to 100V, when the current is low, higher contact resistance may occur. When low contact resistance is important, and the voltage and/or current is low, a vacuum or other type of gas filled relay should be used instead of a SF6 gas-filled relay. • Due to the ease with which sulphur hexafluoride ionizes, gas-filled relays cannot normally be used to interrupt loads. SF6 gas filled relays do not emit hazardous X-rays because the electrons collide with the gas molecules and are unable to accumulate sufficient energy to create significant radiation. SF6 gas filled relays are recommended for many non-RF high voltage applications. For non-RF applications and for relays over 10kV, SF6 gas filled relays are the most forgiving of all the high voltage relays. Because they have SF6 gas inside rather than vacuum, the leakage current is generally lower and more repeatable over long periods of non-operation. Because of the gas, they are most tolerant should the contacts have to make an abnormal load. If the load is not RF, first consider relays rated for make only. Sealed high-voltage relay applications include high in-rush capacitive make and capacitive discharge such as - found in ESD test equipment, cable test equipment, heart defibrillators, and for applications where no high voltage is applied for long periods where low and or stable leakage current is needed. The sealing processes for vacuum relays can be used to back-filled and pressurized with SF6 gas, make and break relays with hard contacts. Where the inrush is not too high and where higher carry current is required, back-fills with pressurized SF6 gas of carry only relays is used.

Table 28.4: H2 and N2 gas and contact material performance comparisons for switching applications

Contacts

Copper

Molybdenum/Copper

Copper

Molybdenum/Copper

Best

Good pure copper is better

Better

Fair pure copper is better

Carry only Make only life Make and break life high overload make and break

28.10

N2 (Nitrogen)

H2 (Hydrogen)

Application

Good Molybdenum/Copper is better Good Molybdenum/Copper is better Good Molybdenum/Copper is better

Fair Molybdenum/Copper is better Fair Molybdenum/Copper is better Fair Molybdenum/Copper is better

Best Best Best

Better Better Better

High voltage relay designs

Typical high voltage relay designs for high-voltage switching are sealed, providing rugged, small, and efficient high-voltage designs for demanding switching applications. i. Internal hinged Armature Style This traditional design approach provides high mechanical reliability and is adaptable to a number of contact configurations. The contact is actuated by the movement of the spring-loaded armature when the coil is energized. The coil assembly is external to the vacuum package and readily replaceable. When power is applied to the external coil of these relays, a magnetic filed is transferred through a pole that runs through the centre of the coil to the armature, that is located inside the vacuum or gas filled sealed ceramic envelope switching chamber. The armature moves the common contact to the normally open contacts. A spring inside the sealed chamber returns the moving contact to the normally closed contact when coil voltage is removed. Glass/ceramic envelope Terminal lug Armature assembly Hinge pin Spring Coil Moulded bobbin

Terminal plate

(a)

(b)

Coil terminals Figure 28.13. Internal hinged armature style relay: (a) double throw relay design but (b) with built-in internal copper metal shield for power switching.

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Chapter 28

Figure 28.13a is a typical design used in many high-current, high-voltage relays. This is a single pole double throw relay, SPDT. Depending on the switching application, various contact materials are used inside the sealed chamber. Tungsten/molybdenum is used for making or breaking loads. Copper contacts have lower contact resistance and are used for higher current carry only applications such as for RF. Figure 28.13b shows the same design but with a built-in internal shield that extends relay life. When power switching a load using a vacuum relay, even hard contacts vaporize, and the material becomes deposited and plate-out the internal walls of the ceramic envelope. Over time, these deposits reduce the isolation voltage, which causes the relay’s end of useful life. This plate-out condition is solved by incorporating an internal metal shield as shown. The deposits hit the shield rather than the ceramic wall, resulting in a relay life many times longer than relays without the shield. ii. Diaphragm Style This simple, low-cost design approach makes use of a thin molybdenum diaphragm that allows contact movement to be transferred into the vacuum package enclosure from the external actuating assembly. Figure 28.14 parts a and b show diaphragm style relays. The contacts are sealed in a chamber at the top of the relay. The chamber is sealed with a braze joint at the top, and with a thin molybdenum diaphragm below. The external high voltage connections are integral to the braze seal. The relay armature is below the sealed chamber as shown on the cross sectional view in figure 28.14c. When power is applied to the non-polarised coil, the armature moves, and a ceramic insulating rod that is attached to the diaphragm moves the common contact to the normally open contact (a small rod) inside the sealed chamber. Figure 28.14a is a single throw, normally open configuration, where the top contact, A3, is open and the moving contact, A2, is below. Figure 28.14b is a double throw relay. The normally open contact is at the top, the normally closed contact is in the centre, and the moving contact is at the bottom. For this relay, the sealed chamber extends from the top of the relay down to the diaphragm that is the moving contact. Both the normally open and normally closed contacts are in a common sealed chamber.


1316

Figure 28.15. Encapsulated high-voltage single-pole double-throw diaphragm relay.

iv. Sealed Relay and Contactor Designs Impervious ceramic sealing technology is a low-cost, light, rugged, high temperature, high quality hermetic seal for relays and contactors. The ceramic header is welded, without a thick layer of epoxy, to a can with high-temperature plastics inside for the arc management. The ceramic seal allows high pressure sealing for a vacuum, or hydrogen or suitable inert gasses that facilitate high-current interruption. In turn, the controlled internal environment allows the use of low-resistance, highconductivity, high contact pressure, copper contacts. Formerly, sealed relays and contactors used all ceramic envelopes which are expensive, glass to metal seals which do not provide true seals over long periods of time, or epoxy and plastic seals that do not provide the high temperature ratings or the microsealing needed to exploit higher performance back fill gasses. The aerospace industry has adopted 270V dc high-voltage systems and many industrial applications such as solar power, fuel cells, micro-turbines, hybrid and electric vehicles, etc. have also involve dc systems.

A1, NO Normally open contact

A1 NO or A1 NC

Metal can

Normally closed fixed contact A3, NC

A2 common

Normally closed contact A2, common Common contact

Magnets

movable contact

Coil Economiser

Auxiliary contact actuator

weld

weld

diaphragm Ceramic insulators insulator

Return spring

Sealed volume

Armature

A2

A3

A1

Ceramic header

Sealed volume

Ceramic header

Figure 28.16. Sealed ceramic encapsulated dc relay.

A2

X2 X1

Coil assembly

A1 X2 X1

Coil connectors X1, X2

X1 X2 X1 X2 (a)

Metal can

Normally open fixed contact

(b)

(c)

Figure 28.14. Diaphragm style single-pole relay design: (a) single throw; (b) double throw relay design; and (c) cross sectional view.

iii. Package encapsulation design Figure 28.15 is a diaphragm style relay, where the relay in figure 28.13 or 28.14 is packaged inside a cup that provides more mounting and high voltage terminal options. Because the contacts are in a vacuum, they can withstand higher voltages than the distance between the external terminals. By potting the relay inside the cup, the high voltage capabilities are greatly improved.

vi. High-Voltage Reed Relays The principal function of a high voltage reed relay is to isolate a high voltage, with the use of evacuated reed switches. These are available with tungsten or rhodium contacts, depending on the switching requirements of the application. High-voltage reed relays are intended for use in dc or ac (50Hz to 60Hz) applications. (RF reed relays are not specifically considered). The reed switch consists of two ferromagnetic blades (generally composed of iron and nickel) hermetically sealed in a glass capsule, as shown in figure 28.17. The blades overlap inside the glass capsule with a gap separating them, and make contact with each other when a suitable external magnetic field is applied. The contact area on both blades is plated, welded or sputtered with a hard metal, usually tungsten for low frequency switching or rhodium or ruthenium for lower contact resistance. These hard metals potentially offer long life times if the contacts are not switched with heavy loads. The gas in the capsule is usually nitrogen or some equivalent inert gas. Some reed switches, to increase their ability to switch and standoff high voltages, exploit an internal vacuum. The reed blades act as magnetic flux conductors when exposed to an external magnetic field from either a permanent magnet or an electromagnetic coil. Poles of opposite polarity are created and the contacts close when the magnetic force exceeds the retarding spring force of the reed blades. As the external magnetic field is reduced, the force between the reeds falls below the restoring force of the reed blades, so the contacts open. The common blade (or armature blade), the only moving reed blade, is connected to the normally closed blade in the absence of a magnetic field. When a magnetic field of sufficient strength is present, the common blade is attracted to the normally open blade. The normally open and normally closed blades

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always remain stationary. All three reed blades are ferromagnetic; however, the contact area of the normally closed contact is a non-magnetic metal which has been welded to the ferromagnetic blade. When exposed to a magnetic field, both the fixed reeds assume the same polarity, which is opposite that of the armature. The non-magnetic metal interrupts the magnetic flux on the normally closed blade so that the armature experiences an un-interrupted flux path to the normally open blade, and to which it is attracted. If the attractive force is of sufficient magnitude between the normally open and armature, the contacts close. Using the proper design, materials, placing an electrostatic shield around the reed switch internal to the coil and driving the shield, will allow coupling or transmission of small signals (nV signals or fA currents) through the relay with little or no interference. This is virtually impossible with other technologies except at high cost. Thermoelectric voltage cancellation, with two series differentially connected contacts, is necessary at low signal voltage levels. Contact Materials – Rhodium versus Tungsten Rhodium offers superior low contact resistance, which, coupled with copper plated reed switch technology produces low loss RF reed relays, with exceptional current carry performance. Rhodium contacts are offered for high voltage applications, where low contact resistance and good current carry performance are required, provided the switching voltage is below 1000V dc or ac peak. Tungsten contacts are used exclusively for high voltage 15kV isolation (stand-off) reed relays, which are high voltage switching contacts able to switch voltages up to 12.5kV dc or ac peak at low current, 5A, 200W. Operate and release times are both about 2ms. Tungsten is a good general purpose switching contact material (109 dry switching and 108, 200W switching operating lifetime, which reduces with breaking current) but a higher contact resistance, 100mΩ, means it is not suited for RF applications. Low capacitance of less than ½pF between contacts, is typical. In a reed relay, the reed switch uses an electromagnetic coil for activation and is shown in its simplest form in figure 28.17. Reed relays require little power to operate and are generally gated using transistors, TTL directly or cmos drivers. Reed relay contacts, when switched dry, (zero current closure or less than 5V @ 10mA), function well into the billions of operations. Ferromagnetic blades

Inert gas or vacuum


Chapter 28

Cu coil

1318

needed to select compatible wire insulation, and to determine how much heat the contactor may dissipate in a sealed enclosure. Worst case, an applied current could exceed the contactor terminal rating, causing melt down of the contactor, leading to an electrical short or possibly fire. 2- Power switching rating – This rating is determined by contact wear and the resultant loss of dielectric withstanding voltage or insulation resistance, caused by the depositing of vaporized contact material near the contacts. The ability of a vacuum relay to switch both resistive and inductive loads greatly simplifies circuit design problems. In power switching applications non-isolated relays (which includes all relays not identified as ground isolated) must be used with caution when the relay mounting is at ground potential and the circuit to be switched is at a high potential. Fault conditions may cause internal arc over to the grounded housing. Ground isolated relays can be used within their voltage ratings without concern for ground faults because the switching part of the relay is completely isolated from ground. Vacuum relays are made in models designed to be switched hot or cold. Hot switching often entails contact arcing upon opening and during contact bounce. AC and dc circuits have extra considerations when switched ‘hot’. Cold switching is where the circuit is switched with no load through the relay terminals, so the relay acts either as an insulator or a conductor. In the make mode the contacts conduct the full load current, and contact current handling capacity is limited by heating caused by contact resistance. Special low resistance copper alloys are used for most cold switching relays to assure high current handling capabilities. In the break mode, the relay must perform as a high voltage insulator. Stand-off voltages are highest at dc and low ac frequencies, and reduce at higher frequencies due to RF heating of the insulator. Ceramic insulators provide the best withstand capabilities for high RF applications. Many dc applications involve controllers or inverters that have large dc capacitors across the dc link. Unless these capacitors are pre-charged, the contactor essentially experiences undefined current when the contacts first close, limited only by the internal resistance and stray inductance of the system. If there is no pre-charge of the capacitor, the contacts can weld on the first or second cycle. The difference in expected life rating with a pre-charge of 90% and 80%, is a factor of 100. If possible or appropriate, an ac contactor should be used on the three-phase ac input to any rectifier stage, thereby avoiding the need for less robust dc relay technology.

shield 28.12

High voltage relay grounding

It is normal practice to ground the base of all high voltage relays for electrical safety. Relay

Relay

I S

N NI

E

I V

Switch contacts

I LOAD

lead

LOAD

Arcing can transfer to ground, bypassing the load

E

Load limits current

Glass body Relay between load and supply

(a)

(b)

Relay between load and ground

Figure 28.17. A reed relay consisting of a wound coil with a reed switch.

28.11

Contact ratings

There are two elements in establishing contact ratings for a contactor. 1 - Contact carry-current rating – This rating is a matter of heat dissipation. The contact carry current rating is based on four parameters: • ambient temperature, • heat generated because of the contact resistance, • internal resistance of the contactor current carrying mechanisms, and • size of the cables connected to the terminals. By increasing the wiring diameter, removing more heat from the terminals, or if the ambient temperature is reduced, the more current that can be carried. The maximum allowable terminal temperature is important, otherwise there is no indication of how hot the terminals and connecting wire may get. It is

Figure 28.18. Contact position relative the load and dc source: (a) relay arcing shorting source to ground and (b) any relay arc draws controlled current through the load from the source.

The topological position of a relay in a series circuit can determine its maximum capabilities. For example, a relay with an internal ground plane within the vacuum envelope will break much more power when one contact is at ground than when the contacts are between the dc power supply and load, as shown in the two parts of figure 28.18. When a hot circuit is switched, an arc is usually created. This arc can transfer to ground when a relay with internal grounding is placed between the load and the power supply as in figure 28.19b. This ground fault or breakdown results from ionized gas and vaporized metal from the contacts that bypass the load and conducts between the high voltage lead and the ground plane of the actuator. The only limit to the resultant current surge is the inherent current limitation of the dc power supply itself. When one contact is at ground potential, however, the series load limits the surge current, as shown in figure 28.19b. To eliminate this type of breakdown problem, relays with ground

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Power Electronics

isolation from the vacuum enclosures should be used. Vacuum relays operated cold may be installed in any circuit location, as the relay does not interrupt power, but acts either as a low loss conductor or as a high voltage insulator. The mentioned grounding requirements are specified by the particular relay contact style.


Chapter 28

28.13

1320

A LV voltage, 750V dc, high-current, 350A dc, make and break relay

i. Diaphragm style relays need not have their base grounded. This is because there is no ground plane inside the sealed switching chamber that an arc can strike during hot switching, and because the external distance to ground, combined with the added insulation of the coil, is greater than the breakdown voltage between contacts. These relays can be used in hot switching applications on either the high-side or low-side of the load, as shown in figure 28.19.

dc source

dc source

(a)

(b)

Figure 28.19. Diaphragm style relays where grounding of the case is not necessary but is recommended for safety while the contacts can be on either side of load: (a) relay on the groundside of the load and (b) relay on the dc source-side of the ground connected load.

ii. Internal armature style relays must always have their relay base grounded, as shown in figure 28.20a, unless the voltage across the contacts is less than the specified dielectric voltage breakdown between the coil and case. When hot switching voltages above the coil to case dielectric voltage rating, the relay must be on the ground-side of the load as seen in figure 28.20a and the case must be grounded. For hot switching voltages lower than the coil to case dielectric voltage rating, the relay can be on either side of the load, that is, as in figure 28.20a or figure 28.20b, and the case does not have to be grounded but is recommended to be grounded for safety.

dc source

dc source

Figure 28.21. Typical 750V dc 350A dc relay.

Table 28.5: 750V dc, 350A make and break relay characteristics Specifications

unit

value

Contact Arrangement (main)

Form X

SPST-NO

Contact Arrangement (auxiliary)

Form C

SPDT

Mechanical Life

cycles

1 million

Contact Resistance Maximum @ rated carry current Typical @ rated carry current

mΩ mΩ

0.4 0.15 to 0.3

Operate time, 25˚C Close (includes bounce) Maximum Close (includes bounce) Typical Bounce on close, Maximum Release time (includes arc time at maximum break current)

ms ms ms ms

20 13 7 12

Insulation Resistance @ 500V dc (a)

(b)

Figure 28.20. Internal armature style relays should always have their case base grounded, plus: (a) should always be on ground-side of load if the source voltage is greater than the coil to case dielectric rating and (b) on the non-ground-side of load if the source voltage is lower than the coil to case dielectric rating.

In figure 28.20a, if arcing transfers to ground, the load limits the current. In figure 28.20b (and also figure 28.19), if arcing transfers to ground, current bypasses the relay and load, and is only controlled by the source impedance. Power control applications often must utilize figure 28.20b, although figure 28.20a is recommended for high-voltage circuit applications.

Dielectric withstand voltage at sea level (leakage < 1mA) Shock (peak) 11ms ½ sine

MΩ

100

V rms

2,500

G

20

Vibration, Sinusoidal (80 to 2000 Hz, peak)

G

15

Storage Ambient Temperature Range

˚C

-70 to +175

Mass

kg

0.44

Figure 28.21 pictures a 750V dc 30A make and break relay based on the relay construction, with the features as outlined in section 28.10iv. General properties are outline in Table 28.5, while make and break performance effect on lifetime is shown in figure 28.22. The maximum make current is 650Adc, at which level contact welding may occur. End of life is when the insulation resistance between terminals haves, that is, falls below 50MΩ @ 500V dc. Electrical life rating is based on a resistive load with 27µH maximum inductance in the circuit.

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Chapter 28


1322

Table 28.6: Range of available high-voltage dc relays 25kV @ 150A Make and break, hot

28kV @ 110A Carry only (no load switching), RF

70kV @ 10A Make only, capacitor charging and discharging, with high inrush

Figure 28.22. HV dc relay type upper V-I resistive load make and break limits and life cycling ratings.

28.14

X-ray emissions in vacuum relays

Above 15kV, all components that operate in a vacuum, including vacuum relays, can produce X-rays that are hazardous. When extremely high voltages are applied, charge carriers in the electrical field are accelerated and can cause radiation when they impact on the electrodes. This is one reason for using SF6 gas filled relays because the electrons collide with the gas molecules and are unable to accumulate sufficient energy to create significant radiation. Gas-filled high voltage relays can be operated safely at high-voltages without any concern for X-rays. Although many relays rated for use above 15 kV are gas-filled relays, when vacuum relays are used over 15kV, the equipment should be shielded with lead Pb that is at least 1.6mm thick. If shielding is not possible, then appropriate X-ray warnings should be labelled and a radiation X-ray monitoring programme should be implemented. 28.15

Power reconstitution conservation method

Vacuum relays may show signs of ‘gassiness’ after a relatively short period of non-use. A trace of gas released from an adsorbed state on the relay internal surface is usually responsible. This trace can normally be eliminated by the use of a high voltage processing procedure. High-voltage process procedure is as follows: • Connect a variable high voltage ac or dc power supply in series with a 10MΩ resister, a microammeter, and the relay normally open contacts (with the relay on the ground-side of the supply). • Immerse the relay in a dielectric fluid, such as transformer oil, but Fluorinert FC-77 is cleaner since it evaporates quickly from the relay surface. • Raise the source voltage slowly. If the peak voltage is made equal to the maximum specified test voltage and less than 5µA of current is drawn (or no glow is visible in a darkened room), then the vacuum is hard and no reconstituting processing is necessary. • If a glow occurs at a lower than maximum specified test voltage, hold the voltage just above the glow initiation level until the glow disappears; raise the voltage again to the onset of glow, or until the maximum specified test voltage is reached. If a dc supply is used, reverse the polarity and repeat the process. Processing is up to 20% above the maximum specified test voltage. Typical processing times range from one minute to several minutes for high-voltage relays. It is not necessary to high-voltage process gas-filled relays.

Ic-b DC or 60 Hz 2.5 MHz Coil hi-pot

Ceramic, vacuum dielectric, tungsten

Ceramic, vacuum dielectric, Cu

gas filled, SF6

SPDT

SPST NO / NC

SPST NO / NC, STDT, Latching

15uA

15uA

15uA

25kV,150A

28kV,110A / 25kV,55A

dc 70kV,10A

15kV,120A

22kV,60A / 22kV,30A

60Hz 30kV,10A

500V rms @ 60Hz

500V rms @ 60Hz

500V rms @ 60Hz

Cc-c

5pF

2.5pF

-

Cc-gnd

5pF

2.5pF

-

Rc-c

3mΩ

5mΩ / 10mΩ

2mΩ

top

100ms

18ms / 18ms

20ms

trel

15ms

10ms / 20ms

15ms 500,000 cycles

life

1,000,000 cycles

2,000,000 cycles

mass

1kg

0.342kg

0.336kg

Top

-55°C to +125°C

-55°C to +125°C

-50°C to +85°C

G52 (H-25:- 50kV,10A, 25mΩ 60ms / 60ms, +85°C)

KC20 / KC30

K70A/B/C G71L

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28.16

Chapter 28


1324

MV AC vacuum interrupts for contactor, switch, and circuit-breaker application

Vacuum interrupters with a contact gap of up to 7mm exhibit higher dielectric strength compared to SF6. With wider contact gaps have a higher dielectric strength when SF6 is used as the medium. At 16mm (corresponding to the distance between contacts in a 36kV vacuum circuit breaker), the measured dielectric strength is approximately 200kV, as shown in figure 28.23. This is slightly higher than the rated lightning impulse withstand voltage of a standard 38kV breaker. For higher system voltages, therefore, two or more vacuum interrupters would have to be connected in series, which is marginally economical. Therefore SF6 circuit breakers are typically used at voltages higher than 72.5kV.

Flexible conductor

Control circuit socket Vacuum Opening spring 16mm, 200kV

SF6 (0.1MPa)

Air (0.1MPa)

Figure 28.23. Dielectric strength comparison between different medium, breakdownm voltage versus gap distance. Figure 28.24. Typical three-phase ac vacuum circuit breaker: (a) vacuum interrupter and (b) MV mechanical three phase contactor. (source: www.ABB.com).

Medium voltage contactors are apparatus suitable for operating in ac power applications. The contactors in figure 28.24b consist of a moulded resin monobloc containing vacuum interrupter Al2O3 ceramic modules, figure 28.24a, moving parts, electromagnet, the multi-voltage control feeder, and auxiliary accessories. The monobloc is the support for the assembly of the fuse-holder frame. Closing of main contacts is carried out by means of the control electromagnet. Opening is affected by means of a special counteracting spring.

1. stem / movable terminal 2. twist protect and flange 3. metal bellows / seal diaphragm 4. interrupted lid 5. arc shield 6. Ceramic housing insulator 7. metal screen/shield 8. Upper moving contact Lower fixed contact 9. stem/terminal 10. interrupter lid and flange 11. fixed terminal

Vacuum interrupt

28.16.1 Basic Interruption Principle To ensure minimum maintenance and long life, the main contacts of the contactor operate inside the sealed vacuum interrupters (with a vacuum level of 13 x 10-5 Pa). On opening, there is rapid separation of the fixed and moving contacts in each contactor interrupter in a three-phase contactor. Overheating of the contacts - melting, generated the instant they separate, causes the formation of metallic vapours at the point of final contact which allows an electric arc to be sustained up to the first zero current passage associated with the ac supply. At zero current, cooling of the metallic vapours allows recovery of high dielectric rigidity able to withstand high values of return voltage. The contacts of the interrupters for contactors are made of WCAg alloy or more commonly used CuCr alloy (or also previously CuBi alloy). The hard-metal component, tungsten carbide WC, makes the contacts resistant to erosion caused by arcing. As a result, contacts have an electrical lifetime of several hundred thousand switching cycles at rated current. Also, with WCAg the chopping current is in the region of 0.5A, compared with 3 to 5 A for CuCr, which is used widely in circuit-breakers. In motor switching versions, the value of the commutated current is less than 0.5A with extremely limited over-voltages. Importantly, high-speed interruption reduces the level of fault damage to equipment. These interrupter components give high dielectric strength and rapid recovery after arc extinction. This high dielectric strength exhibits moderately low arc energy during high current interruption, thus minimizing contact erosion. The vacuum medium provides quick controlled arc extinction due to high velocity radial diffusion of vaporized special metal alloy contact surfaces during contact separation. This allows rapid recovery of dielectric strength and minimizes over voltages. The interruption capability is not affected by adverse conditions such as altitude, extreme temperature or humidity. When the current is small and the contact area is large, the arc spreads by itself, and interruption should be successful. If the current to be interrupted increases, on interruption the arc area contracts and remains station at a certain point. Therefore an arc control mechanical structure is used to increase interruption capacity. Two basic structures are used. Spiral contacts generate a radial magnetic force, RMF, in figure 28.25a to rotate the arc, and axial magnetic field, AMF, contacts in figure 28.25b diffuse the arc by axial magnetic force.

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Chapter 28


1326

Figure 28.26. Basic principle of a quadruple axial magnetic field contact: (a) ferromagnetic circuit arrangement; (b) magnetic circuit in an open position; (c) contact system, without electrical pole face slots; (d) electrical pole face electrode slots; and (e) electrical plus magnetic combined quadrupolar contact systems.

I

I

(a)

I

I I current B magnetic flux F Azimuthal electromagnetic force

(b)

Figure 28.25. Basic mechanical contacts, with arcing operation based on: (a) a spiral contact producing a radial magnetic force, RMF and (b) slots, axial magnetic field, AMF.

i. Quadruple axial magnetic field contact – AMF Constriction of vacuum arcs at high current levels depends on the contact material and the electrode principle. By applying a radial magnetic force/field, RMF, the constricted arc column is forced to move rapidly around the contact surface. Axial magnetic field AMF contacts within vacuum interrupters, however, prevent the vacuum arc from constricting due to the reduced charge carrier movement perpendicular to the magnetic flux and the magnetic field. This applies especially to the electrons, which have a smaller mass than the ions. The electrons gyrate around the magnetic lines of force, so that the contraction of the arc is shifted towards the higher currents. The diffused arc results in reduced energy impact on the electrodes which is also indicated by the small regular arcing voltage. Therefore, AMF contacts provide excellent high short-circuit current behaviour. Depending on the design, the local axial field distribution is different. For single-pole arrangements the direction of the AMF is the same within the whole inter-electrode gap. For multiple-pole arrangements the polarity of the field changes. The main reason in designing AMF contact systems is to achieve an AMF distribution that uniformly spreads the thermal stress of the vacuum arc over the entire contact surface.

In AMF contact designs, the magnetic field is generated by a coil arrangement behind the electrode faces. Compared to RMF spiral contacts, where the current flows directly from the stems through the electrodes in closed position of the vacuum interrupter, the continuous current performance is reduced due to the increased resistance of the coil construction. The heat generated by the resistive losses are virtually all dissipated via the oxygen-free high conductivity copper stems to the outside of the vacuum interrupter. The impact of thermal radiation is minimal. The AMF is generated by a hybrid principle. The first contribution is produced by a magnetic circuit, the second by slots incorporated into the electrodes. Both AMF generating measures do not disturb the direct current flow from the copper stems through the closed electrodes. The continuous current performance is therefore comparable to RMF spiral contacts, which is of vital importance for high continuous current applications. According to Ampere’s law, the magnetic field surrounds the copper stem during current flow. By arranging four ferromagnetic pieces as shown in figure 28.26a, the magnetic flux, B is guided in the created magnetic circuit as indicated by the arrows. The magnetic flux is forced to penetrate four times the plane between the ferromagnetic pieces and perpendicular in the poles, to the current flow, I. In the case of separating the ferromagnetic pieces as shown in figure 28.26b, the magnetic flux has to cross the gap between the ferromagnetic pieces in an axial direction four times. Due to the increasing distance between the ferromagnetic pieces in axial direction and therefore the increased magnetic reluctance of the magnetic circuit, a part of the magnetic flux does not penetrate the gap in the axial direction. Depending on the magnetic reluctances of the different circuits, a specific part of the magnetic flux closes in the azimuthal direction as indicated in figure 28.26b by the dashed circumferential arrows. This phenomenon progressively decreases the axial magnetic flux density with increased gap distance. Figure 28.26c shows the principle of a magnetic circuit applied to a contact system of a vacuum interrupter. After opening the electrodes in order to interrupt a current, the described quadrupolar AMF forces the arc into a diffuse mode. By incorporation of slots into the electrodes, as seen in figure 28.26d where the plates have a relative rotation of 90°, a part of the current is diverted from flowing directly through the contact plate to the vacuum arc position on the contact plate. Due to the forced diverted current loops, an auxiliary quadrupolar AMF is generated reinforcing the AMF provided by the magnetic circuit. Figure 28.26e displays the principle of the complete hybrid quadrupolar contact system. The slots of this hybrid principle impact on AMF performance. In a closed position, the dc current flow from the copper stems through the electrodes, results in a continuous current performance similar to RMF spiral electrodes. Compared to RMF spiral electrodes, additional losses are evoked by the eddy currents and the hysteresis within the ferromagnetic pieces. The thickness of the contact plate is important in dimensioning the contact design. An increased thickness results in a weakening of the AMF, due to the increased reluctance, hence less magnetic flux penetrates the electrodes and the inter-electrode gap. Flux, leakage, is diverted through the gap between the two ferromagnetic materials behind each electrode. However, an increased plate thickness increases thermal capacity during, after, and in-between short-circuit current operation.

1327

Power Electronics


Chapter 28

1328

Medium-Voltage AC Vacuum circuit breaker characteristics

i. Vacuum contactors HV contactors and relays require only a 2mm to 12mm contact opening to obtain voltage withstand of 20kV to 70kV pk (or more for series contacts) Operate times of 1 to 16 milliseconds are obtained using the simple operating mechanisms to move the lightweight contacts the short travel required. Contact resistance is low, usually less than 10µΩ to 1mΩ, depending on the type of contact used. Higher continuous currents are also available with the use of high current shunting switches with capacities of up to 63kA. The contacts are readily adaptable to series connection for higher voltages, with a maximum operating voltage of 30kV to 45kV peak per contact, enabling withstand voltage capabilities to in excess of 300kV. A typical three-phase MV ac contactor and its key characteristics are shown in figure 28.28. Vacuum contact mechanical life is generally at least 10,000 operations to several million operations, depending on interrupter type, speed of operation, and contact opening distance. Contact electrical life is 1 to 10 operations at maximum interrupt to several million at lower currents; and is much more dependent on closing current than on interrupt currents up to several times rated load current. Closing bounce and amp-seconds during arcing are the main electrical life determining factors. ii. Operate voltages Single contact, normally open, normally closed, latching and trip free type HV vacuum contactors and relays are used at 208V rms to 30kV pk, and 50 to 1,200A continuous. In most standard applications, voltage ratings are raised in multiples of 30kV (operating) above 15kV (operating) by placing contacts in series. For example, two 15kV rated type contacts in series per phase are suitable for 45kV, three contacts in series per phase are suitable for 75kV applications.

10

8

106

4.5kA, 106 cycles

105

Operating cycles

28.16.2

7

9

7 Short-time withstand current

ii. Spiral radial magnetic field contact – RMF The spiral contacts in a vacuum generate a radial magnetic field (RMF), as shown in figures 28.25a and 28.27, which causes an azimuthal electromagnetic force to act on the contracted vacuum arc. The contracted arc moves over the contact’s surface at a speed of 70 to 150 m/s. This high velocity ensures that there is less contact erosion and also significantly improves the current interrupting capability. The resultant arc voltage is higher with RMF contacts. The advantage of the RMF contact system is its simple physical structure, while another advantage of the spiral contact is that in the closed state the current can flow through the contacts directly via the stem, thereby ensuring lower power losses for the vacuum interrupter at nominal current. In most AMF contact based contactors, the axial magnetic field is generated by a coil located behind the contacts. As a result, the resistance of the interrupter is increased and the resultant additional resistive losses reduce the nominal current performance. The only practical way in which a vacuum interrupter can dissipate the generated heat is via the copper conductors, since convection is not possible in a vacuum and radiation is minimal because the larger surface areas are facing and the low emissivity of the contact metals. In the short-circuit current range above 63kA, the more complex AMF contact system is superior to conventional RMF contacts.

(A) rms

Figure 28.27. Basic principle of a spiral radial magnetic force contact, showing a current filament flow during interruption.

6 5 4

4

10

3

10

2

10

1

1

10

5kA, 10 cycles

100

3 0

1

2

3 4 Load time (s)

5

6

101

102 103 Breaking current (A) rms

104

Figure 28.28. Vacuum contactor, rated voltage=12kV, rated normal current=450A, rated make current=4500A, impulse withstand voltage=75kV.

iii. Current ratings Continuous current ratings are from 50A to in excess of 1,200A rms, with up to 36kA rms continuous with the use of a shunt switch to carry the continuous current while using the vacuum interrupter's capability for the actual interruption. This switchgear has 60Hz interrupt ratings of 2kA to 28kA, 10 cycle momentary ratings of 5kA to 60kA and capacitor discharge to 1,000kA. 50Hz maximum interrupt ratings are derated 10%.

iv. AC/DC current interruption DC: The single pole HV vacuum contactors and relays can be used on both ac and dc current interruption. The units dc rated vacuum contacts can normally be used for limited current interruption to 10A dc. Some ac rated contacts can interrupt dc at much higher currents with carefully controlled displacement pulses to create current zeros, and slow recovery voltage rates similar to those of 60Hz to 400Hz waveforms. Mechanism utilize special tungsten contacts for limited dc current interruption. In some cases, the interruption can be carried to as high as 20 to 40A dc. When interrupting dc, transient suppression such as non-linear resistance or a capacitor in series with a 1Ω/kV inrush limiting resistor should be used in parallel with the vacuum contacts and the load. For higher dc current interruption, that is, several hundred to several thousand amps or more at 15kV dc per contact, or 40kV dc for 2 contacts in series, ac rated contactors with copper alloy vacuum contacts can be satisfactory. This is possible if multiple displacement-pulses are applied with a controlled rate of recovery voltage that approximates 60Hz current zero and recovery voltage characteristics by means of a resistor/capacitor and switching network or if in combination with an inductive resonant circuit. AC: For ac interruption, the contacts are designed with copper alloy combinations to limit current chopping to less than a 1A to 8A level to minimize switching transients. AC current interruption generally occurs at the first current zero after contact separation. If the contacts are not sufficiently apart for the rate of recovery voltage, or arc energy is high, current may carry over to the next current zero before clearing. At higher contact voltages and currents, the contacts must not bounce after opening, which would temporarily reduce the contact spacing. v. Inductive load switching With highly inductive loads, wherever possible, transient suppressing non-linear resistance or protective capacitors should be placed across the line as close to the load equipment terminals as possible. Standard lightning arresters are not as effective as a protective shunt capacitor with approximately 2Ω/kV of inrush damping resistor in series directly connected across the load. This is essential for repeatedly switched inductive loads such as arc furnaces, motors, and many low current, transient generating inductive loads. Most switching devices create over voltages on switching and for iron core reactive loads, normal switching over voltages of 2 to 2½ times operating voltage occur with any type of interrupter. Dry type transformers and air core inductive loads can generate higher over voltages if there is insufficient shunt capacitance. vi. Closing and inrush currents When closing on to transformers and other iron core inductive loads, normal inrush currents of 5 to 10 times rated load current are expected, depending on the magnetic retentivity from the previous interruption. If iron core inductive loads can be re-energized on the opposite polarity from which they were de-energized, , thereby avoiding core saturation, then inrush is minimized, otherwise, it is limited primarily by the circuit and winding resistance and leakage. Repeated high inrush closing causes mechanical stress on the transformer windings as erosion of the vacuum contact (which can be over 10 times as great on closing as on interrupting even the same current). Therefore, transformers that have marginal insulation and mechanical bracing can deteriorate with repeated switching, regardless of type of switch. vii. Contact erosion Contact erosion and resultant internal vaporized metal deposit distribution generally determines the end of electrical life. A 2mm to 6mm of total erosion is generally the life limit. With the proper selection of contact material and with currents under 600 to 1kA, erosion should be small. At currents between 1kA and 3.5kA, erosion should be moderate. At currents approaching the maximum interruption rating, life may only be 1 to 100 operations. Even at low to moderate currents, closing generally causes 2 to 10 times as much erosion as interrupting the same currents. Thus, for long-life current closing, the closing current should be limited. Step-start dual closing contactors which use inrush current limiting resistors can be used. Voltage zero and current zero sensing devices for closing or opening are viable. viii. Actuator types and contactor configurations Normally open, normally closed, double throw, and latching type configurations are available. Standard actuator voltages are 115V, 60Hz for smaller units, 230V, 60Hz is recommended for larger, heavy-duty solenoid actuated units. 208V, 480V, 24V, 60Hz, 50Hz, and 24V dc, 100/125V dc, 400Hz, and other voltages are available. Actuator voltage is specified plus the applicable HV contact operating voltage and current, basic impulse level (BIL), insulation level for MV contacts and MV contacts to actuator or ground, maximum rms current interrupt, 1 cycle (16.6ms) momentary rms current, 10 cycle rms momentary current, or peak capacitor discharge current and the RC time constant of the current decay to 35% of peak. Other information may include type of load, number of operations per year, maximum current levels on closing and opening, speed of opening and closing, and number and type of auxiliary contacts required.


Chapter 28

1330

ix. Auxiliary contacts Two auxiliary SPDT contacts are usually standard. x. High voltage protection Safety regulations require high voltage and line to ground current protection. In 2 to 16 ms the contactor’s high speed trip, driven by a relay driver, can close the contacts and divert the fault current, or open the contacts and interrupt the load current, or both, thus minimizing damage to the controlled equipment. When proper ground fault or leakage current sensing is used, this may be fast enough to reduce personnel injury from accidental electrocution because of contact with one line and ground or voltages developed in the ground circuit from ground current. xi. Uses Basic MV contactors and relays with sealed vacuum contacts are available in single pole, two-pole, and three-pole variations. Models include normally open, normally closed, or double throw units. Latching actuators are also available. The contactors and relays are used in many high voltage power supplies for capacitor bank charging and discharging, current transfer, tap or load selection, or sealed arc interruption. The units are suited for high-speed interruption of up to 10A dc or 28kA ac. They are also reliable for high-speed crowbar or fault diversion to protect sensitive electronic devices. These various functions are accomplished with 1ms to 4ms contact closure or separation. A high-speed vacuum power interrupter can crowbar in 2ms, divert the fault, then interrupt up to its maximum rated current in approximately 3ms to 16ms, depending on type of system and current zero timing. 28.16.3 Altitude derating Insulating properties of air decrease as the altitude increases. This phenomenon must be taken into account during the design stage of insulating parts of equipment that will be installed at over 1000m above sea level. In such cases, a correction coefficient is used from the graph in figure 2729, which is calculated from:

ka = e

m ×( h −1,000) 8150

h altitude in metres; m value considered constant for simplification and equivalent to 1 for power frequency, lightning withstand impulse, and between phases. 1.50

m =1 ka

Power Electronics

Altitude correction factor

1329

1.40

1.30

1.20 2000m, 1.13

1.10

1.00 1

2 Altitude

3 h

4 (km)

Figure 28.29. Graph for determining the voltage correction factor ka according to the altitude.

Example 28.2: Vacuum circuit breaker altitude properties A vacuum circuit breaker is installation at an altitude of 2000m. If it used at • Rated voltage, 7kV • Power frequency withstand voltage 20kV rms • Impulse withstand voltage 50kV p determine its necessary contactor voltage requirements.

Power Electronics

1331


Chapter 28

1332

Corona surface factor

Solution From the graph or from the following equation: m ×( h −1,000)

2,000 −1,000 8150

ka = e =e = 1.13 For the above parameters, the apparatus will have to withstand the following values, based on test values at zero altitude, that is, at sea level. 8150

Table 28.7 gives empirically determined correction factors for various surface conditions. These factors are multiplied by the corona starting voltage (or field) to determine the corrected effective voltage. Eliminating or reducing corona Electrically, reduce or eliminate unwanted voltage transients, which can cause corona to start.

Power frequency withstand voltage equal to: 20 x 1.13 = 22.6kV rms Impulse withstand voltage equal to: 50 x 1.13 = 56.5kV p. For installations at an altitude of 2000m above sea level, with an operating voltage of 7kV, apparatus with a rated voltage of 12kV characterized by power frequency withstand voltage of 28kV rms and with 60/75kV p impulse withstand voltage must be used. ♣ 28.18

Corona can be avoided by minimizing the voltage stress and electric field gradient. Initially maximize the distance between conductors that have large voltage differentials. Use homogeneous insulators of void free solids, such as properly prepared silicone and epoxy potting materials. Smoothly radiusing the corners of objects at high voltages relative to nearby objects will reduce the local field strength. Put the sharp corner in contact with a substance with a higher breakdown strength than air. Corona can be reduced by making the high field occur within a substance with a higher breakdown than the surrounding air. Table 28.7: Correction factor for Corona breakdown

Corona

Corona (also known as partial discharge) is caused by the electric field next to an object exceeding the breakdown gradient for air, or whatever the field source is immersed in. Since the magnitude of the field is inversely proportional to the radius of curvature, sharper edges break down sooner. The corona initiation voltage is typically 30 kV/cm radius. Dust or water particles on the surface of the object reduce the corona starting voltage, by providing local areas of tighter curvature, and hence higher field stress. Corona hissing or cracking can often be heard, particularly with a safely placed stethoscope or ultrasonic detector. In addition, the ozone produced by the corona can sometimes smelt. The presence of corona can reduce the reliability of a system by degrading insulation. While corona is a low energy process, over long periods of time, it can substantially degrade insulators, causing a system to fail due to dielectric breakdown. The effects of corona are cumulative and permanent, and failure can occur without warning. Corona causes: • Light • Ultraviolet radiation • Sound (hissing, or cracking as caused by explosive gas expansions) • Ozone • Nitric and various other acids • Salts, sometimes seen as white powder deposits • Other chemicals, depending on the insulator material • Mechanical erosion of surfaces by ion bombardment • Heat (although generally minimal, and primarily in the insulator) • Carbon deposits, thereby creating a path for severe arcing The simplest case to analyze is that of a sphere where the magnitude of the electric field at the surface of the sphere in free space is the voltage/radius. If the sphere is near another conductor, the field is no longer uniform, as the charge will redistribute itself towards an adjacent conductor, increasing the field. Since corona is a breakdown phenomenon, it follows Paschen's law: the voltage is a function of potential difference, pd. Double all the dimensions and halve the gas pressure, and the corona voltage will be much the same. Arcing occurs instead of corona when the voltage is too high. Corona will not form when For Concentric Cylinders in Air: Ro / Ri < 2.718 For Parallel Wires in Air: x / r < 5.85 For Equal Spheres in Air: x / R < 2.04 Arcing is difficult to avoid when x / R < 8 where Ro = radius of outer concentric sphere Ri = radius of inner concentric sphere R = sphere radius r = wire radius x = distance between wires or between spheres

Condition of Conductor

mo

New, unwashed

0.67 - 0.74

Washed with grease solvent

0.91 - 0.93

Scratch-brushed Buffed Dragged and dusty

0.88 1.00 0.72 - 0.75

Weathered (5 months)

0.95

Weathered at low humidity

0.92

For general design

0.87 - 0.90

7 strand concentric lay cable

0.83 - 0.87

19, 37, and 61 strand concentric lay cable

0.80 - 0.85

Covering sharp corners with an insulating film increases the corona inception voltage at the points with high E-field stress. Generically known as corona dope, this is an enamel or polystyrene paint or gels that can be applied. Clear acrylic spray paint is a generic possibility, although the coating is quite thin. Potting the entire assembly in an insulator, room temperature vulcanising RTV silicone, achieves the same result. Immersing the assembly in oil or other insulating fluids is also effective. All of the potting and immersion techniques depend on removing the air or gas bubbles to be effective. Commercial manufacturers create a vacuum on the container while the assembly is being potted to facilitate the removal of the air bubbles. An approach to reducing corona on wires is to surrounding the conductor by a semiconducting film or layer of greater radius. This effectively increases the radius of the object, and hence lowers the field strength. Minimal copper may be needed to carry the required current (often micro or milliamps), but a large diameter conductor is required to reduce the corona. Field grading rings are often used on high voltage equipment to control the electric field distribution. Rather than rely the field that would exist in free space between two charged conductors, a series of other conductors are interposed at intermediate voltages. The intermediate voltages are derived from a capacitive or resistive divider. A capacitive divider may be a simple as the inter electrode capacitances of the grading rings themselves. Running the system in a tank at high pressure, or in an insulating gas, increases the corona starting voltage.

Power Electronics

1333

28.19

Chapter 28

blank

Appendix: Contact metals

Table 28.8. Rare and precious metals used for mechanical contacts

8

(Ω -m×10 )

Reading list http://relays.tycoelectronics.com/ http://www.gigavac.com/ http://www.jenningstech.com/index.html


1334

Bibliography

1336

Nomenclature and symbols APR BJT CoP CTE CVD DCB EBL EGS GTO IGBT LPCVD MBE MFD MMF MOSFET mtbf mttf NTD PC PCM PECVD POH PSG PVD PVT RIE s/b ScD SCR SOA TEC TIM α α α α αo αs β βf βQ βr ßs γ γi Γ

axial power rating bipolar junction transistor coefficient of performance coefficient of thermal expansion chemical vapour deposition direct copper bonding electron beam lithography electronic grade polysilicon gate turn-off (thyristor) insulated gate bipolar transistor low pressure CVD molecular beam epitaxy magneto-fluid-dynamic magnetomotive force metal oxide semiconductor field effect transistor mean time between failures mean time to failure neutron transmutation doping permeance coefficient (Bd / µo Hd) phase change material plasma enhanced CVD power on hours phospho-silicate glass physical vapour deposition physical vapour transport reactive ion etching second breakdown skeleton cemented diamond silicon controlled rectifier safe operating area thermoelectric cooler thermal interface material

gate threshold temperature dependence coefficient temperature coefficient of on-state resistance thermal coefficient of linear expansion, K-1 current transfer ratio current transfer ratio in mid current region characteristic life (hours) base-to-collector current amplification factor forward current gain GTO turn-off gain reverse current gain shape parameter surface tension, N/m injection efficiency gamma function

δ on-state duty cycle factor δT, ∆T temperature difference between regions of heat transfer, T2 -T1, K system static pressure loss [1Pascal = 1N/m²,] ∆P ∆Pcmax maximum capillary pressure difference between the evaporator and condenser ∆Pg hydrostatic pressure drop ∆Pliquid, ∆Pvavpour viscous pressure drops in liquid and vapour phases velocity pressure, ½ρv2 Pv ∆T ∆T ∆Tsa

thermal shock temperature desired air temperature differential (enclosure inlet to discharge ambient air), K average temperature difference between heat sink and ambient air

ε εa εo εr εs

surface property, termed emissivity, 0 ≤ ε ≤ 1 apparent emissivity of a channel free space permittivity, 8.854x10-12 F/m relative dielectric constant dielectric permittivity εs = εr εo

ηf ηv

fin efficiency volumetric heat transfer efficiency

θ θf

contact angle, rad, volume figure, dimensionless

λ λ λ λeff

thermal conductivity, W/cm.K latent heat, J/kg wavelength effective thermal conductivity for a heat pipe

µn, µp hole/electron mobility, cm2/V-s µo µm µrc permeability of vacuum/air, magnet, recoil ν

absolute fluid kinematic viscosity, Ns/m2, Pa

ξ ξb

electric potential, V/m breakdown field, V/m

ρ ρm ρℓ

resistivity, Ω.cm density of the heatsink material, kg/m3 density of working fluid (e.g. air, liquid) medium, (= 1/ν specific volume), kg/m3

σ σ σ σp

conductivity, Ω-1.cm-1 Stefen-Boltzmann constant, 5.667×10-8 W/m2K4 surface tension, N/m symmetrical standard deviation, cm

τ τ

τh, τe

period of the switching interval (both on and off), s thermal time constant, s minority carrier hole/electron lifetime, s

φ Φ Φb Φf

kT/q, thermal voltage, built in potential, V zero external bias, built-in, junction potential or scl potential, V Schottky barrier height pressure figure, dimensionless parameter

ω

rotational (angular) velocity at the perimeter

A Ae, Ac Ag, Am Ax

total surface area (of die/outside/heatsink fins and base between fins) involved in the heat transfer, cooling, m2 effective evaporator and condenser surface areas cross-sectional area of air gap, magnet cross sectional area (fin), m2

b bt B Bd Bg (BH)max Bi Br Bsat

thickness of the heat sink, mm base transport factor magnetic flux density (induction) flux density in magnet at operating point on demagnetization curve flux density in air gap maximum energy product intrinsic flux density (induction) in a magnet residual induction in magnet saturation flux density

cd cp C Ca

critical line width specific heat capacity of the cooling fluid at constant pressure, W/m∆T, J/kg.K linear rate constant capacitance per unit area of the gate oxide, ε / tox

Power Electronics

Cds Cgd Cgs Cf Cin Ciss Cj (v) Cjo Cob Coss Cr CR Crss Ct (v)

non-linear voltage-dependent drain to the source capacitance non-linear voltage-dependent gate to the drain capacitance non-linear voltage-dependent gate to the source capacitance correction factor for position and surface emissivity of heat-sink orientation gate input capacitance, approximately Cgd + Cgs, or Ciss input capacitance voltage dependant scl capacitance, F zero bias junction capacitance, F output capacitance, essentially Cds common source output capacitance basic dynamic load capacity, kg correction factor reverse transfer capacitance fluid surface combination constant voltage dependant transit capacitance, F

d d1 diF/dt dirr /dt dm/dt dv/dt D Do DH Dn, Dp DNL

diameter, m n- drift region width forward current rate of change, A/s reverse recovery current rate of change, A/s mass evaporation rate anode impressed dv/dt diffusion or diffusivity coefficient, µkT/q = λ / γcp, m2/s outer diameter of the fan impeller, m diameter (hydraulic/bore), mm hole/electron carrier diffusivity speed limit, rpm-mm

E Ea Eg Eo

emf, circuit applied reverse voltage activation or threshold energy, eV band gap, eV diode model on-state voltage source, V

f fs F(t)

ℑm

friction factor (loss coefficient) switching frequency, Hz cumulative distribution function, a function of age t magnetomotive force

g gf gfs gd G

gap gravitational acceleration, m/s2 amplification factor, forward transconductance n-channel, output conductance volumetric fluid flow rate, m3/s

h hr H HP H(t) H Hc Hci Hd Hg

convection/conduction thermal heat transfer coefficient (of surface material) W/m2K radiation heat transfer coefficient, W/m2K capillary or lifting height, height of the fin, length (of heat sink base), m impeller input power to rotate hazard rate, failure rate or hazard function magnetic field strength, magnetizing force, demagnetizing force coercive force intrinsic coercive force demagnetizing force at operating point of magnet on demagnetization curve magnetizing force in air gap

iR iF irr I Ib Ib Ibf Ibr Ic

leakage current, A forward current, A reverse recovery current current, A base current reverse voltage breakdown diode current, A forward base current reverse base current collector current

C sf'

1337

Bibliography

1338

Iceo collector current when Ib = 0 for V(BR)ceo Icer collector current when Rbe = R, for V(BR)cer collector current when Vbe = 0 for V(BR)ces Ices Icex collector current when Veb = X, for V(BR)cex drain current n-channel Id Idp drain current p-channel IDQ positive - negative temperature coefficient boundary Ite TE current drawn emitter current, A Ie reverse gate current, A IGQ IG, Ig SCR/triac gate current diode (maximum) forward current, A IF IFMG peak forward gate current, A gate current, A Ig IGT, VGT minimum trigger values IG, VG dc gate signal GTO minimum negative gate current at anode current IGTQ IGQ holding current, ILatch >IH IH IK IA SCR cathode/anode/gate current, A load current, A IL ILatch anode latching current, ILatch >IH Im maximum current level, A nominal current, A Inom Io reverse (saturation) leakage current, A IRG negative gate current, A IRM peak reverse recovery current, A IT GTO on-state current , A storage current level, A Itail IRRM, IDRM reverse leakage and forward blocking current, A ITSM peak one cycle surge on-state current, A Irms rms current, A 2 thermal energy crated rating, A2s It J flux – heat, impurities reverse recovery W.s/pulse, JR J1, J1, J1 SCR junctions k k kexp kℓ kr

constant Boltzmann’s constant, 1.38 x 10-23, J/K load factor specific to the system, determined experimentally leakage coefficient loss or reluctance factor

kD kT K K Kq, Km, Kw

characteristics dimension of the geometry grease temperature factor heat transfer coefficient constant units thermal resistance pu area, cm2/W Kp, KHP constants for geometrically and dynamic operation wire current constant

ℓ ℓ ℓ ℓ ℓg, ℓm ℓm L L L L L L, W, t Lc Leff Lp

vertical height in the direction of the airflow thickness of insulation, m distance (thickness) length length of air gap, magnet line resolution heat of vaporization per unit mass length (of cold plate), m characteristic passage length of the microchannel fin depth circuit inductance, H length/width/thickness, m effective channel length effective length, ½(Levaporator + Lcondenser) + Ladiabatic minority carrier diffusion length

Power Electronics

Lt Lw L2 L10

service life, hours sound pressure level, dB life for 98%, 90% survival, second and tenth percentiles

m m mf M Mℓ

breakdown multiplication exponent mass (weight) of object, kg (density x volume) mass flow rate of air/fluid through enclosure/heatsink, (equal to ρ vf s L), kg/s voltage dependant avalanche multiplication effect merit number (liquid transport factor), W/m2

n ni nf nq

exponent intrinsic carrier concentration, 1.4x1010 /cc number of fins airflow quality constant index of refraction donor/acceptor concentration, cm-3 speed (fan impeller), rps/rpm number of cycles numerical aperture background doping, cm-3 concentration of the lighter doped region /cc nominal speed Nusselt number, non-dimensional heat transfer coefficient, hδ/k, ARemPrn

n

N D, N A N N NA NB Nc Nnom Nu

1339

p, n po, no P P P P P Pcold Pc Pc Pd PD PDtotal l P

electron/hole concentration, cm-3 hole/electron equilibrium carrier concentrations, cm-3 mean heat added (or being removed - dissipated) from the object, W, watts heat transport rate equivalent dynamic bearing load, kg pressure permeance (inverse of reluctance) amount of heat absorbed at the cold surface of TEC, W conduction power loss permeance coefficient heat load (lost/gained), electrical power dissipated, rate of radiated heat transfer, W amount/conducted heat dissipated (in enclosure, transferred to cooling system), W total power to be dissipated

q Q Qflow Qo QR QT QΣ

electron charge, 1.602x10-19 C pool boiling heat transfer rate heat flow zero bias scl charge, C reverse recovery charge, Q1 + Q2, C total gate charge total recovery charge, C

r rc

radius, m effective capillary radius

maximum allowable power dissipation, W d reference pressure Pref maximum power Pmax Phot minimum total heat to be rejected by the heat exchanger on the hot side PG drive input device power loss PGM, PG peak and mean gate power off-state leakage power loss Pℓ load electrical power dissipation, W PL PRQ storage and fall time power loss Ps switching transition power loss Ptec TEC input dc power initial heat pumping capacity when ∆T is zero Pto Ptt heat pumping capacity at desired ∆T and heat-pumping capacity is decreased PT power transported by the heat pipe fin perimeter, m P□ PWL sound power level

1340

r(tp) R Rbe Rds(on) Rd Re Rg Rg int Rg ext Ri RL Ro Rs Rt Rθ Rθ j-c Rθ j-a Rθ c-s Rθ s-a

ℜm

Bibliography

normalising factor resistance, Ω models the lateral p-body resistance on-resistance n/p-channel deposition rate Reynolds number, ratio of inertia forces to viscous forces in the fluid, Vδ/v gate resistance internal gate resistance external gate resistance resistance modelling linear leakage current, Ω load resistance, Ω diode model series resistance, Ω sheet resistance, Ω/square thermal resistance of one channel thermal resistivity/resistivity virtual junction to case thermal resistance, K/W total thermal resistance from the virtual junction to the open air (ambient), K/W case-to-heat-sink thermal resistance, K/W heat-sinking thermal resistance magnet reluctance

s fin spacing S initial dose per unit area at the surface, cm-2 Sf, Sfm, Sfs selectivity (mask, substrate) SG grease half-life subtraction factor SN speed half-life subtraction factor load half-life subtraction factor SP SPL sound pressure level, decibels, dB(A) Sr snap-off and soft recovery diode properties S½ half-life subtraction factor S%s fraction of solids t fin/plate thickness t time (required to cool down (or heat up) object), s td delay time td off turn-off delay time td on turn-on delay tfi current fall time forward recovery characteristics of time tfr tfv voltage fall time tp power pulse width to time to zero current, s toff turn-off time, ts + tfi turn-on time, td + tri ton oxide thickness, m tox tri current rise time reverse recovery time, s trr trv voltage rise, time ts storage or saturation time minority carrier lifetime tt ttail current fall time T cycle or integration period T absolute temperature, K Ta ambient temperature TA is the ambient temperature Tbrg bearing temperature, K Tc case temperature, K final temperature, °C Tf Thot, Tcold, (or Th and Tc) Tin, Tout fluid (air, water, etc.) inlet and outlet temperatures, K inside temperature, °C Ti/s Tj junction temperature, K Tl maximum allowable junction temperature, K j

Tmax

maximum operating temperature or desired cold plate surface temperature, K

Power Electronics

Tmean Tmelt To To/s Ts Tsat Twall

arithmetic mean of T1 and T2, specifically ½( T1 + T2) melting temperature initial/starting temperature, °C outside temperature, °C heated surface temperature liquid saturation temperature (boiling point) heated surface temperature

v cooling fluid flow rate, fluid velocity (volumetric flow rate), m3/s v velocity of the vertical airflow vce collector to emitter voltage vDR reverse voltage νsat saturation velocity of electrons in silicon, 9.0x106 cm/s V, v voltage, V anode turn-off voltage VA(t) Vb avalanche voltage, V Vbe(sat) base to emitter saturation voltage VBF forward anode-cathode breakover voltage reverse breakdown breakover voltage VBR V(BR)cbo V(BR)ceo maximum collector-base voltage with the emitter open circuit, base open V(BR)cex maximum collector-emitter voltage with specific base V-R conditions V(BR)DSS drain breakdown voltage, V collector to base avalanche breakdown voltage Vcbo Vceo collector to emitter first breakdown Vceo, Vcbo BJT voltage characteristics Vcer, Vces, Vcev BJT voltage characteristics dependent on the external base circuit conditions Vce(sat) collector emitter saturation voltage VDRM forward off-state Vds drain to source voltage supply voltage Vdd Vte TE voltage applied VF diode forward voltage, V velocity between the fins Vf Vfp peak forward voltage Vg, Vm volume of air gap, magnet gate junction voltage VGC Vgg gate source voltage maximum VGFM, VGRM peak forward and reverse gate to cathode voltage gate voltage Vgs stray inductance VLs VPT punch-through voltage, V VRM diode recovery minimise voltage overshoot, V VRRM reverse direction maximum voltage level Vs Vt tip speed of impeller gate threshold voltage VTh VZ Zener breakdown voltage w W Wc Whs Wi Wn2 Wo Wref Wscl

width energy, J width of region/channel, µm width of heat sink base intrinsic i-layer thickness n-base width zero bias scl width, m acoustic reference power scl width

xj xn, xp Xp

metallurgical/impurity junction depth, m scl penetration into n/p sides, m penetration depth peak, m

Z Zθ j-c

altitude, above sea level, m thermal impedance, K/W

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Degrees of protection IP codes according to IEC 60529 standard

Degrees of protection are identified by IP followed by two numbers followed by an optional letter, as defined in the table to follow.

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Glossary of terms

IEC 947 and IEC 947-3 Standards Selecting contactors according to IEC 947-3 standard Glossary of Wafer Processing terminology Alloying:- The process of forming a low-resistance contact between the aluminium metal and silicon substrate on a metallised semiconductor wafer. Amorphous Si, a-Si:- non-crystalline thin-film silicon; features no long-range crystallographic order; inferior electrical characteristics as compared to single-crystal and poly Si but cheaper and easier to manufacture; used primarily to fabricate solar cells. Angstrom, Å:- unit of length commonly used in semiconductor industry, though not recognised as a standard international unit; 1 Å = 10-10 m = 10-4 micrometer = 0.1 nm. Annealing:- The process of combining hydrogen with uncommitted atoms at or near the silicon-silicon dioxide interface on a metallised semiconductor wafer. Ashing:- The process of removal (by volatilization) of organic materials (e.g. photoresist) from the wafer surface using strongly oxidizing ambient; e.g. oxygen plasma ashing. Backlapping:- The process of mechanically thinning the backside of a finished semiconductor wafer. Backside metallisation:- The process of depositing a metal layer on the backside of a finished wafer. Bandgap, energy gap Eg:- forbidden energy levels separating the valence and conduction bands. Electrons are allowed to have energies at these levels. Barrier metal:- thin layer of metal, e.g. TiN, sandwiched between other metal and semiconductor (or insulator) to prevent potentially harmful interactions between these two, e.g. spiking. Boat:- 1. a device made of high purity temperature resistant materials such as fused silica, quartz, poly Si, or SiC. designed to hold many semiconductor wafers during thermal or other processes; 2. device designed to simultaneously contain source material during evaporation while at the same time heating the source to its melting point; made of highly conductive, temperature resistant material through which current is passed. Chip:- The final integrated semiconductor circuit. Conduction band:- the upper energy band in a semiconductor separated from the valence band by the energy gap; The conduction band is not completely filled with electrons. Constant-source diffusion:- also know as unlimited-source diffusion or predeposition; concentration of diffusant (dopant) on the surface of the wafer remains constant during the diffusion process, i.e. while some dopant atoms diffuse into the substrate additional dopant atoms are continuously supplied to the surface of the wafer. Crystal pulling:- The process of forming a crystal ingot; a seed crystal of silicon is attached to a rod and "pulled" out of a silicon melt to form an ingot. Czochralski Crystal Growth, CZ:- process utilizing crystal pulling to obtain single-crystal solids; the most common method for obtaining large diameter semiconductor wafers (300mm Si wafers); desired conductivity type and doping level is accomplished by adding dopants to molten material. Wafers used in high-end Si microelectronics are almost uniquely CZ grown. Czochralski method:- The crystal pulling method used to form crystal ingots. Chemical vapour deposition:- The process of applying a thin film to a substrate using a controlled chemical reaction. Deposition:- A general term used to describe the addition of material layers on a semiconductor wafer. Die:- An individual device or chip cut from a semiconductor wafer. Diffusion:- A doping process; a high-temperature furnace is used to diffuse an applied layer of dopant into the wafer surface. Diffusion coefficient, D:- determines rate with which element moves in a given solid by diffusion; depends strongly on temperature; expressed in cm2/s; varies between elements by orders of magnitude, e.g. in the case of diffusion in silicon diffusion coefficient for gold, Au, is in the range of 10-3 cm2/s (fast diffusant) while for Sb is in the range of 10-17 cm2/s. Dopant:- element introduced intentionally into a semiconductor to establish either p-type or n-type conductivity; Common dopants in silicon are: Boron (p-type) and phosphorous, arsenic, and antimony (n-type). Doping:- The process of introducing impurity elements (dopants) into a semiconductor wafer to form regions of differing electrical conductivity. The two most common doping processes are diffusion and ion implantation. Drive in:- high temperature (>800oC) operation performed on semiconductor wafer in an inert ambient; causes motion of dopant atoms in semiconductor in the direction of concentration gradient (diffusion); used to drive dopant atoms deeper into semiconductor.

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Electron beam (e-beam) evaporation:- source material is evaporated as a result of highly localized heating by bombardment with high energy electrons; the electron beam is spatially confined and accelerated by electrostatic interactions. The direction and cross-section of the beam can be precisely controlled and rapidly altered to scan the target; evaporated material is very pure; bombardment of metal with electrons is accompanied by generation of low intensity X-rays which may create defects in the oxide present on the surface of the substrate; typically, an anneal is needed to eliminate those defects. Epi Layer:- The term epitaxial comes from the Greek word meaning 'arranged upon.' In semiconductor technology, it refers to the single crystalline structure of the film. The structure comes about when silicon atoms are deposited on a bare silicon wafer in a CVD reactor. When the chemical reactants are controlled and the system parameters are set correctly, the depositing atoms arrive at the wafer surface with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the wafer atoms. Thus an epitaxial film deposited on a oriented wafer will take on a orientation. Epitaxial layer:- layer grown in the course of epitaxy. Epitaxy:- process by which a thin epitaxial layer of single-crystal material is deposited on single-crystal substrate; epitaxial growth occurs in such way that the crystallographic structure of the substrate is reproduced in the growing material; also crystalline defects of the substrate are reproduced in the growing material. Although crystallographic structure of the substrate is reproduced, doping levels and the conductivity type of a epitaxial layer is controlled independently of the substrate; e.g. the epitaxial layer can be made more pure chemically than the substrate. Etching:- The process of removing silicon dioxide layers, accomplished by "wet etching" with chemicals or by "dry etching" with ionized gases. Evaporation:- common method used to deposit thin film materials; material to be deposited is heated in vacuum (10-6 - 10-7 Torr range) until it melts and starts evaporating; this vapour condenses on a cooler substrate inside the evaporation chamber forming smooth and uniform thin films; not suitable for high melting point materials; PVD method of thin film formation. External, extrinsic gettering:- process in which gettering of contaminants and defects in a semiconductor wafer is accomplished by stressing its back surface (by inducing damage or depositing material featuring different than semiconductor thermal expansion coefficient) and then thermally treating the wafer; contaminants and/or defects are relocated toward back surface and away from the front surface where semiconductor devices can be formed. Fick's law:- describe diffusion in solids; 1st and 2nd Fick's law; 1st Fick's law describes motion by diffusion of an element in the solid in the direction of the concentration gradient; 2nd Fick's law determines changes of concentration gradient in the course of diffusion (function of time and diffusion coefficient). Filament evaporation:- thermal evaporation; source material is contacted to the filament (a refractory metal) and melted by high current flowing through the filament; alternatively, a "boat" which contains material to be evaporated may be made out of refractory metal; Float-zone Crystal Growth, FZ:- method used to form single crystal semiconductor substrates (alternative to CZ); polycrystalline material is converted into single-crystal by locally melting the plane where a single crystal seed is contacting the polycrystalline material; used to make very pure, high resistance Si wafers; does not allow as large wafers (< 200mm) as CZ does; radial distribution of dopant in FZ wafer is not as uniform as in CZ wafer. Gettering:- process which moves contaminants and/or defects in a semiconductor away from its top surface into its bulk and traps them there, creating a denuded zone. HMDS:- Hexamethyldisilizane; improves adhesion of photoresist to the surface of a wafer; especially designed for adhesion of photoresist to SiO2; deposited on wafer surface immediately prior to deposition of resist. Hydrogenated a-Si:- amorphous silicon (a-Si) containing substantial quantities of hydrogen; hydrogen passivated Si dangling bonds and results in substantially improved electrical properties of A-Si Ingot:- circular piece of single-crystal semiconductor material resulting from a crystal growth process; an ingot is ready to be shaped and sliced into wafers used to manufacture semiconductor devices. Intrinsic gettering:- process in which gettering of contaminants and/or defects in a semiconductor is accomplished (without any physical interactions with the wafer) by a series of heat treatments. Ion implantation:- A doping process; the dopant material is ionized and magnetically accelerated to strike the wafer surface, thereby embedding the dopant into the substrate. Lapping:- The process of mechanically grinding the surface of a sliced wafer. Lead frame:- The die attachment surface and lead attachment points that a die or chip is attached to prior to wire bonding and packaging. limited-source diffusion:- also known as drive-in; concentration of diffusant (dopant) on the surface decreases during the diffusion process, i.e. while some dopant atoms diffuse into the substrate no new dopant atoms are supplied to the surface of the wafer. Metallization:- formation of metal contacts and interconnects in the manufacturing of semiconductor devices.

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Metal-semiconductor contact:- key component of any semiconductor device; depending on materials involved in the contact its properties can differ drastically; ohmic contact (linear, symmetric current-voltage characteristic)in the case when work function of metal matches work function of semiconductor (no potential barrier at the interface); rectifying contact(non-linear, highly asymmetric, diode-like current-voltage characteristic) in the case when work function of metal differs from the work function of semiconductor (potential barrier at the interface)- commonly referred to as a Schottky diode. Minority carriers:- one of two carrier types (electrons of holes)whose equilibrium concentration is lower than that of the other type; holes in n-type semiconductors, electrons in p-type semiconductors. N-type semiconductor:- semiconductor in which the concentration of electrons is much higher than the concentration of holes (p>>n); electrons are majority carriers and dominate conductivity. Ohmic contact:- metal-semiconductor contact with very low resistance independent of applied voltage (may be represented by constant resistance); to form an "ohmic" contact metal and semiconductor must be selected such that there is no potential barrier formed at the interface (or potential barrier is so thin that charge carriers can readily tunnel through it). Oxidation:- The process of oxidizing the wafer surface to form a thin layer of silicon dioxide. Passivation:- The process of applying a final passivating or protective layer of either silicon nitride or silicon dioxide to a wafer. Photolithography:- The process of creating patterns on a silicon substrate. The main steps of the process include photoresist application, mask alignment, photoexposure, developing, and etching the portions of the substrate that are unprotected by the resist. Photomask:- A mask that delineates the pattern applied to a substrate during photolithography. Photoresist:- A photo-sensitive material used in photolithography to transfer pattern from the mask onto the wafer; a liquid deposited on the surface of the wafer as a thin film then solidified by low temperature anneal; in the areas in which photoresist can be reached by UV radiation photochemical reactions change its properties, specifically, solubility in the developer; two types of photoresist:- positive and negative. Polishing:- process applied to either reduce roughness of the wafer surface or to remove excess material from the surface; typically polishing is a mechanical-chemical process using a chemically reactive slurry. Polycrystalline silicon:- An amorphous form of silicon with randomly oriented crystals, used to produce silicon ingots. Polycrystalline material, poly:- many (often) small single-crystal regions are randomly connected to form a solid; size of regions varies depending on the material and the method of its formation. Heavily doped poly Si is commonly used as a gate contact in silicon MOS and CMOS devices. Physical Vapour Deposition, PVD:- deposition of thin film occurs through physical transfer of material (e.g. thermal evaporation and sputtering)from the source to the substrate; chemical composition of deposited material is not altered in the process. P-type semiconductor:- semiconductor in which the concentration of holes is much higher than the concentration of electrons (n>>p); holes are majority carriers and dominate conductivity. Quartz:- single-crystal SiO2. Quartzite:- Silica sand used as a raw material to produce metallurgical grade silicon. Reactive ion etching RIE:-., RIE variation of plasma etching that uses physical sputtering and chemically reactive species in which during etching semiconductor wafer is placed on the RF powered electrode; wafer takes on potential which accelerates etching species extracted from plasma toward the etched surface; chemical etching reaction is preferentially taking place in the direction normal to the surface, i.e. etching is more anisotropic than in plasma etching but is less selective; leaves etched surface damaged; the most common etching mode in semiconductor manufacturing, also used to remove metal layers. Rectifying contact:- metal-semiconductor contact displaying asymmetric current-voltage characteristics, i.e. allowing high current to flow across under the forward bias condition and blocking current off under the reverse bias; this behaviour is controlled by the bias voltage dependent changes of the potential barrier height in the contact region. Seed crystal:- single crystal material used in crystal growing to set a pattern for the growth of material in which this pattern is reproduced. Semiconductor:- solid-state material in which (unlike in metals and insulators) (1) large changes in electrical conductivity can be effected by adding very small amounts of impurity elements known as dopants, (2) electrical conductivity can be controlled by both negatively charged electrons and positively charged holes and (3) electrical conductivity is sensitive to temperature, illumination, and magnetic field. Silicon:- A semi-metallic element used to create a wafer. Silicon dioxide, SiO2:- silica; native oxide of silicon; the most common insulator in semiconductor device technology; high quality films are obtained by thermal oxidation of silicon; thermal SiO2 forms smooth, low-defect interface with Si; can be also readily deposited by CVD; Key parameters: energy gap Eg ~ 8eV; dielectric strength 5-15 x 106 V/cm; dielectric constant k = 3.9; density 2.3

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g/cm3; refractive index n =1.46; melting point ~ 1700°C; prone to contamination with alkali ions and sensitive to high energy radiation (i.e. X-rays); single crystal SiO2 is known as quartz. Silicon Nitride, Si3N4:- dielectric material with energy gap = 5 eV and density ~3.0 g/cm3; excellent mask against oxidation of Si and KOH; properties depend on deposition method: dielectric strength ~107 V/cm, dielectric constant k ~6-7, bulk resistivity 1015-1017 ohm-cm; deposited by CDV. Silyation:- The process of introducing silicon atoms into the surface of an organic photoresist in order to harden the photoresist. Single-crystal:- crystalline solid in which atoms are arranged following specific pattern throughout the entire piece of material; in general, single crystal material features superior electronic and photonic properties as compared to polycrystalline and amorphous materials, but is more difficult to fabricate; all high-end semiconductor electronic and photonic materials are fabricated using single-crystal substrates. Slice orientation: - the angle between the surface of a slice and the growth plane of the crystal. The most common slice orientations are (100), (111) and (110). Slicing:- term refers to the process of cutting of the single-crystal ingot into wafers; high precision diamond blades are used. Slurry:- a liquid containing suspended abrasive component; used for lapping, polishing and grinding of solid surfaces; can be chemically active; key element of CMP processes. Spiking:- uncontrolled penetration of semiconductor substrate by contact metal; problem with Al in contact with silicon; may short ultra-shallow p-n junction underneath the contact. Sputtering, sputter deposition:- bombardment of a solid (target) by high energy chemically inert ions (e.g. Ar+); causes ejection of atoms from the target which are then re-deposited on the surface of a substrate purposely located in the vicinity of the target; common method of Physical Vapour Deposition of metals and oxides. Sputtering target:- source material during sputter deposition processes; typically a disc inside the vacuum chamber which is exposed to bombarding ions, knocking source atoms loose and onto samples. Sputter yield:- efficiency of the sputtering process (differs for different materials). Surface damage:- process related disruption of the crystallographic order at the surface of single-crystal semiconductor substrates; typically caused by surface interactions with high energy ions during dry etching and ion implantation. Staebler - Wronski effect:- degradation of electrical output of hydrogenated amorphous silicon solar cells as a result of prolonged illumination. Stripping:- process of material removal from the wafer surface; typically implies that removal is not carried out for the pattering purpose, e.g. resist stripping in which case entire resist is removed following lithography and etching. Target:- source material used during evaporation or deposition; In sputtering, typically in the form of high purity disc. In e-Beam evaporation, typically in the form of a crucible. In thermal evaporation, the source material is typically held in a boat which is heated resistively. Thermal oxidation, thermal oxide:- growth of oxide on the substrate through oxidation of the surface at elevated temperature; thermal oxidation of silicon results in a very high quality oxide, SiO2; most other semiconductors do not form device quality thermal oxide, hence, "thermal oxidation" is almost synonymous with "thermal oxidation of silicon". Valence band:- the lower energy band in a semiconductor that is completely filled with electrons at 0 K; electrons cannot conduct in valence band. Volume defect:- voids and/or local regions featuring different phase (e.g. precipitates or amorphous phase) in crystalline materials. Wafer:- thin (thickness depends on wafer diameter, but is typically less than 1 mm), circular slice of single-crystal semiconductor material cut from the ingot of single crystal semiconductor; used in manufacturing of semiconductor devices and integrated circuits; wafer diameter may range from 25 mm to 300 mm. Wafer bonding:- process in which two semiconductor wafers are bonded to form a single substrate; commonly applied to form SOI substrates; bonding of wafers of different materials, e.g. GaAs on Si, or SiC on Si; is more difficult than bonding of similar materials. Wafer fabrication:- process in which single crystal semiconductor ingot is fabricated and transformed by cutting, grinding, polishing, and cleaning into a circular wafer with desired diameter and physical properties. Wafer flat:- flat area on the perimeter of the wafer; location and number of wafer flats contains information on crystal orientation of the wafer and the dopant type (n-type or p-type). Work function difference:- defines characteristics of contact between two materials featuring different work function; for conductor-semiconductor contact w.f.d. determines height of potential barrier in the contact plane, and hence, determines whether contact is ohmic or rectifying.

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Glossary of Fuselink terminology (Fuseology) ‘A’ Fuselink (formerly Back-Up Fuselink):- A current limiting fuselink capable of breaking under specified conditions all currents between the lowest current indicated on its operating time-current characteristic and its rated breaking capacity. Ambient Temperature:- The temperature of the surrounding medium which comes in contact with the fuse. The medium is usually air. Fuse current carrying capacity tests are performed at 25°C and are affected by changes in ambient temperature. A fuse runs hotter as the normal operating current approaches or exceeds its current rating. At room temperature, 25°C, a fuse should last indefinitely if operated at no more than 75% of fuse ampere rating. The fuse ambient temperature may be significantly higher because it is enclosed or mounted near other heat producing components, such as resistors, transformers, etc. Ampacity:- The current a conductor can carry continuously without exceeding its temperature rating. Ampacity is a function of cable size, insulation type and the conditions of use. Ampere Rating:- Same as Current Rating or the current carrying capacity of a fuse. The continuous current carrying capability of a fuse under defined conditions. When a fuse is subjected to a current above its ampere rating, it will open the circuit after a predetermined period of time. Continuous load current should not exceed 75% of fuse ampere rating (at 25°C ambient) except fuses that may be specifically loaded to 100% of their ampere rating. Ampere Squared Seconds, I2t:- A measure of thermal (heat) energy associated with current flow during fuse clearing. I2t is equal to I2RMS x t, where t is the duration of current flow in seconds. It can be expressed as melting I2t, arcing I2t or their sum as Clearing I2t. Clearing I2t is the total I2t passed by a fuse as the fuse clears a fault, with t being equal to the time elapsed from the initiation of the fault to the instant the fault has been cleared. Melting I2t is the minimum I2t required to melt the fuse element. ‘I’ is the effective let-through RMS current, which is squared, and ‘t’ is the time of opening, in seconds. Arc Quenching Time:- As part of the Operating Time it is the time between the arc starting and the final current zero. Depending on the Melting Time the Arc Quenching Time is typically just a few ms up to a couple of 100 ms. Arcing Time:- The arcing time is the interval of time between the instant of the initiation of the arc and the instant of final arc extinction. That is the time from when the fuselink has melted until the over current is interrupted, or cleared. Arc Voltage:- The highest fuse voltage during the Operating Time of the fuse. Arcing withstand Time:- Longest time between separation of the melting element and the faultless interruption of the current through the fuse-switch. Typical values are above 100 ms. Breaking Capacity:- The breaking capacity is the highest value (for ac the rms. value of the ac component) of prospective current that a fuselink is capable of breaking at a stated voltage under specified conditions of use and behaviour. The rating which defines the fuses ability to safely interrupt and clear short circuits. This rating is much greater than the ampere rating of a fuse. The highest current at rated voltage that an over current protective device is intended to interrupt under specified conditions. During a fault or short circuit condition, a fuse may receive an instantaneous overload current many times greater than its normal operating current. Safe operation requires that the fuse remain intact (no explosion or body rupture) and clear the circuit. Also known as interrupting rating or short circuit rating. Breaking Range:- Breaking range is a range of prospective currents within which the breaking capacity of a fuselink is assured. Clearing Time:- The total time from the beginning of the over current to the final opening of the circuit at rated voltage by an over current protective device. Clearing time is the total of the melting time and the arcing time. Conventional Non-Fusing Current Inf:- A value of current specified as that which the fuselink is capable of carrying for a specified time (conventional time) without melting. The conventional time relates to the thermal time constant of the fuselink and varies between one and four hours depending on the current rating. Conventional Fusing Current If:- Current specified as that which causes operation of the fuselink within a specified time (conventional time). The conventional time relates to the thermal time constant of the fuselink and varies between one and four hours depending on the current rating. Coordination:- The use of over-current protective devices which will isolate only that portion of an electrical system which has been overloaded or faulted. Current-Limiting Fuselink:- A current-limiting fuse link limits the current to a substantially lower value than the peak value of the prospective current during and by its operation in a specified current range. Current Limitation:- Fuse operation relating to short circuits only. When a fuse operates in its current limiting range, it will clear a short circuit in less than ½ cycle. Also, it will limit the instantaneous peak let-thru current to a value substantially less than that obtainable in the same circuit if that fuse were replaced with a solid conductor of the same impedance.

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Current Rating:- The nominal amperage value of the fuse. It is established as a value of current which the fuse can carry, based on a controlled set of test conditions Cut-Off Current:- The cut-off or let-through current is the maximum instantaneous value reached by the current during the breaking operation of a fuselink when it operates in such a manner as to prevent the current from reaching the otherwise attainable maximum. In case of a short-circuit, the maximum value of the short circuit current. This value is required for the analysis of the dynamic impact of the short-circuit current on the protected equipment. Cut-off (current) characteristic:- The cut-off (current) characteristic or let-through current characteristic is a curve giving the cut-off current as a function of the prospective current, under specified operating conditions. Derating:- Term for reducing influences on the Rated Breaking Current of the fuse. The Derating value is multiplied by the Rated Current then divided by the loading current. Typical influencing factors include high surrounding temperature, terminal cross section, installation volume, pulse load, shock load, and over-waves. Discrimination:- Classification of relevant parameters (Time/Current-Characteristic; Integrals; Operating Times etc.) of two or more overload protection devices to each other. In the case of overloads, only the protection device should react. Sequential fuses with the same characteristic, are selected in the proportion 1:1.6. A fuse with a rated current of 100 A should be downstream of a fuse rated 160 A. For the short-circuit range the comparison of the melting integrals versus the Operating integral of the downstream fuse is important. Dissipated Power:- When a current passes through a fuse link, a small amount of energy is dissipated due to the fuse links resistance. Dual Element Fuse:- Often confused with time delay, dual element is a term describing fuse element construction. A fuse having two current responsive elements in series. Element:- A calibrated conductor inside a fuse which melts when subjected to excessive current. The element is enclosed by the fuse body and may be surrounded by an arc-quenching medium such as silica sand. The element is sometimes referred to as a link. Fast-Acting Fuse:- Fast-acting fuses have no intentional built in slow-blow and are used in circuits without transient inrush currents. Fast-acting fuses open quickly on overload and short-circuits. This type of fuse is not designed to withstand temporary overload currents. Fault current:- A current resulting from a fault, a circuit condition in which the current flows through an abnormal, unintended path. Fusing factor:- The fusing factor is the ratio, greater than unity, of the minimum fusing current to the fuse current rating. Fuse:- A fuse is a device that by the fusing of one or more of its specially designed and proportioned components, opens the circuit in which it is inserted by breaking the current when this exceeds a given value for a sufficient time. An over-current protective device containing a calibrated current carrying member which melts and opens a circuit under specified over-current conditions. It is common practice to refer to a ‘fuselink’ as a ‘fuse’. Fuse Element:- Part of the Fuse-Link, which melts when the fuse operates. It consists of perforated metal stripes. The dimension of the perforation reflects the Characteristic and the Rated Current of the Fuse-Link. Depending on the Rated Current the Fuse-Links contain several paralleled Fuse Elements. Typical materials are copper and pure silver. Fuse initiated opening time:- Time between separating of the melting elements and the faultless interruption of the failure current through the fuse. Typically between 30 and 100 ms. Fuse Selection Guide:- The fuse must carry the normal circuit load current without nuisance openings. However, when an over-current occurs the fuse must interrupt the over-current, limit the energy let-through, and withstand the voltage across the fuse during arcing. To select a fuse the following must be considered: Normal operating current (The current rating of a fuse is typically derated 25% for operation at 25°C to avoid nuisance blowing. For example, a fuse with a 10A current rating is not usually recommended for operation at more than 7.5A in a 25°C ambient.) Overload current and time interval in which the fuse must open. Application voltage (AC or DC Voltage). Inrush currents, surge currents, pulses, start-up currents characteristics. Ambient temperature. Applicable standards agency requirements, such as UL, CSA, VDE. Other considerations include: Reduce installation cost, ease of removal, mounting type/form factor, etc. Fuse Type:- There are three basic types of fuses: 1. Slow Blow/Time Lag/Time Delay fuses 2. Fast acting fuses 3. Very fast acting fuses A major type of Time Delay fuse is the dual-element fuse. This fuse consists of a short circuit strip, soldered joint and spring connection. During overload conditions, the soldered joint gets

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hot enough to melt and the spring shears the junction loose. Under short circuit conditions, the short circuit element operates to open the circuit. Slow-blow fuse allows temporary and harmless inrush currents to pass without opening, but is so designed to open on sustained overloads and short circuits. Slow-blow fuses are ideal for circuits with a transient surge or power-on inrush. These circuits include: motors, transformers, incandescent lamps and capacitate loads. This inrush may be many times the circuit's full load amperes. Slow-blow fuses allow close rating of the fuse without nuisance opening. Typically, Slow Blow fuses are rated between 125% to 150% of the circuit's full load amperes. Fusing Current:- Value of fuse current which will be interrupted within a given time. Valid for general purpose fuse-links. Normally the testing current is about 1.6 times the Rated Current. Gate:- Limiting values within which the characteristics, for example time-current characteristics, shall be contained. High Speed Fuses:- Fuses with no intentional time-delay in the overload range and designed to open as quickly as possible in the short circuit range. Often used to protect solid-state devices. Homogeneous Series of Fuselinks:- A series of fuselinks, within a given size. 2 I t (Joule Integral) :- See Joule integral. I2t (Ampere Squared Seconds):- A measure of the thermal energy associated with current flow. I2t is equal to I RMS2 x t , where t is the duration of current flow in seconds. Clearing I2t is the total I2t passed by a fuse as the fuse clears a fault, with t being equal to the time elapsed from the initiation of the fault to the instant the fault has been cleared. Melting I2t is the minimum I2t required to melt the fuse element. I2t Characteristic:- A curve giving I2t values (pre-arcing I2t and/or operating I2t) as a function of prospective current under specific operating conditions. Interrupting Rating (Abbreviated IR):- Same as breaking capacity or short circuit rating. The maximum current a fuse can safely interrupt at rated voltage. Some special purpose fuses may also have a Minimum Interrupting Rating. This defines the minimum current that a fuse can safely interrupt. Safe operation requires that the fuse remain intact. Interrupting ratings may vary with fuse design and range from 35A AC for some 250V metric size (5 x 20mm) fuses up to 200kA AC for the 600V industrial fuses. Joule integral:- The I2t or Joule integral is a measure of the thermal stress or thermal energy let through by the fuse during short circuit interruption. It is the integral of the square of the current over a given time and is expressed in ampere square seconds. Two values of I2t are provided for MV-fuse links: - Pre arcing or melting I2t - for high short circuit currents - this is practically a constant. - Operation I2t – this varies with circuit conditions. Let-through current:- The cut-off or let-through current is the maximum instantaneous value of current attained during the breaking operation of a MV-fuse link. This important when the MV-fuse link operates in such that the circuit prospective peak current is not reached. Let-through current characteristic:- The cut-off (current) characteristic or let-through current characteristic is a curve giving the cut-off current as a function of the prospective current, under specific operating conditions. Melting Current:- Current during an increase in prospective Short-Circuit Current, at which the Fuse Element melts. This current is usually lower than the Cut-off Current, because this normally increases during the Quenching Time. Melting Integral:- Current Integral for the Melting time of the fuse. The Melting Integral depends on the size of the Melting Elements and is therefore independent of voltage. The minimum value is normally given, for analysing discrimination. Melting time:- The amount of time required to melt the fuselink during a specified over current. The prearcing time or melting time is the interval of time between the beginning of a current large enough to cause a break in the fuse element and the instant when an arc is initiated. The Time/Current-Characteristic provides the virtual Melting Time for different current closing angles. Virtual Melting Time = Melting Integral / failure current. Minimum Breaking Current:- Smallest failure current at which a back-up fuse can operate at its rated voltage. Values are often between 3 to 4 times Rated Current. The minimum breaking current is a minimum value of prospective current that a link is capable of breaking at a stated voltage under specified conditions. Non fusing Current:- Defined value of current, at which (under certain circumstances) a fuse-link must not operate within a given time, Conventional Time. For a General Purpose Fuse, this value is normally 1.25 times Rated Current. Operating time:- The operating time or total clearing time is the sum of the pre-arcing time and the arcing time. Also the summation of Melting Time and Arc Quenching Time of the Fuse. Over a Melting Time of 100ms the Operating Time can generally be equated with the Melting Time. For shorter Melting Times, the Operating Time can be more than double of the Melting Time. Below 5ms, the Operating Time should be calculated via the Operating Integral.

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Operating Integral:- Current integral over the operating time of the fuse. Information is particularly valid for melting times less than 5ms, whence the fuse has operated with current limitation. Usually the datasheet value is the highest expect for the given reference voltage. Values at lower service voltage are calculated through the conversion diagram. Overcurrent:- An over-current is a current exceeding the rated current, normal load current, conductor ampacity or equipment continuous current rating. An over-current can be an overload current, fault current or short circuit current. Overcurrent Discrimination:- Co-ordination of the relevant characteristics of two or more over-current protective devices such that, on the occurrence of over-currents within specific limits, the device intended to operate within these limits does so, while the others do not. Overload:- Classified as an overcurrent which exceeds the circuit normal full load current. The operation of conductors or equipment at a current level that will cause damage if allowed to persist. The current does not leave the normal current carrying path of the circuit, that is, it flows from the source, through the conductors, through the load, back through the conductors to the source. Overload current:- A current resulting from an overload occurring in a normally working electrically circuit, for example an overloaded motor. If there is no protective device operating in a limited time of several seconds, the electrical system would overheat and cable isolation, etc. would melt and cause damage. Overload Curve of an Fuselink:- A curve showing the time for which a fuselink shall be able to carry the current without deterioration. Peak Let-Thru Current, IP:- The instantaneous value of peak current let-thru by a current limiting fuse, when clearing a fault current of specified magnitude in its current limiting range. Power Dissipation:- Power dissipation is the power released in a fuse link carrying a stated current under specified conditions of use and behaviour, usually including a constant rms. current until steady temperature conditions are reached. Pre-Arcing Time:- The pre-arcing time or melting time is the interval between the beginning of a current large enough to cause a break in the fuse element and the instant when an arc is initiated. Prospective Current of a Circuit (with respect to the fuse):- The prospective current is the current that would flow in a circuit if a fuse situated therein were replaced by a link of negligible impedance. The prospective current is the quantity to which the breaking capacity and characteristics of the fuse are normally referred, for example, I2t and cut-off current characteristic. Prospective Short Circuit Current:- The prospective short circuit current is the value of the current that would flow if there was no protection in the circuit. The lower the power factor of the installation, the higher the peak value of this destructive current. Rated Breaking Capacity (Low/High Voltage Fuses):- Capacity of a fuse to operate between the lowest and the Rated Breaking Current, which is a certified, effective value. Normally fuses can operate at higher currents. Typical values for Low-Voltage fuses are: 100, 120, 200 or 300 kA and for High-Voltage fuses 20kA to 63 kA. For miniature fuses, it is the current at which a fuse can operate normally under specified conditions at a fixed Voltage. Rated Current of a Fuselink In:- A value of current that the fuselink can carry continuously without deteriorating or without operating under specified standardised conditions, including in free air with a defined cable cross-sections. Often the Rated Current has to be reduced by the Deratingvalue. Rated Frequency:- The rated frequency is the frequency for which the fuse link has been designed and to which the values of the other characteristics correspond. Standard values of rated frequency are 50 Hz and 60 Hz. Rated Insulation Level:- The rated insulation level (of a MV-fuse base) is the voltage values (both powerfrequency and impulse) which characterize the insulation of the fuse base with regards to its capability of withstanding the dielectric stresses. Rated Values:- Rated values, usually stated for HV-fuse links, are - voltage - current - breaking capacity - frequency All given for specified operating conditions. Rated Voltage:- The Rated voltage, Vn, is the maximum value of voltage at which an fuse link can be used, and safely interrupt an over-current. This rated voltage must be higher or equal to the highest voltage of the system in which the fuse link is installed. Effective value of the Operating Voltage of a fuse; normally an alternating voltage, at a frequency between 42 to 62 Hz. Recovery Voltage:- The recovery voltage is the voltage which appears across the terminals of a fuse after the breaking of the current. This voltage is considered in two successive intervals of time, one during which a transient voltage exists, followed by a second during which the power frequency or the steady-state recovery voltage alone exists. Selectivity:- A main fuse and a branch fuse are said to be selective if the branch fuse will clear all overcurrent conditions before the main fuse opens. Selectivity is desirable because it limits outage to

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that portion of the circuit which has been overloaded or faulted. Also called selective coordination. Short Circuit:- A high value of over-current resulting from a fault of negligible impedance between conductors with difference potential and under normal operating conditions. A short circuit current can be many hundreds or even thousands of times larger than the normal load current. Striker:- A striker is a mechanical device forming part of a fuselink which, when the fuse operates, releases the energy required to cause operation of other apparatus or indicators or to provide interlocking. Switching voltage:- The switching voltage is the maximum instantaneous value of voltage, which appears across the terminals of a fuse during its operating time. Under short circuit conditions this will often exceed the peak system voltage for a period of time. It is typically two to three times the Rated Voltage. Time-current characteristic:- The time-current characteristic is a curve giving the time, for example prearcing time (or operating time), as a function of the prospective current and respectively shortcircuit currents. under specified operating conditions. The time-current curve is used to achieve co-ordination with the other fuses or devices in the same installation. Time/Current-Curve:- Curve for calculating the Melting Time of the fuse at designed overload and respectively short-circuit current. The opening time is considered nominal. Time/Current-Curves refer to a temperature between 20°C and 30°C, are given for times between 4ms and 10000s, and are drawn as a family of curves on a double logarithmic grid (opening time in seconds for the fuse for a range of over-currents). Time Delay Fuse:- A fuse which will carry an over-current of a specified magnitude for a minimum specified (in standards) time without opening. Take-Over Current:- at operating the Striker Pin: Value of the symmetrical three phase current at which the breaking varies between the fuse and the switch. Below this value the current will be interrupted in the first quenching pole through a fuse and the current in both other poles through the switch. Above the value, the current is interrupted in all 3 poles only through the fuses. Depending on the Rated Voltage of the switch, values are between 600A and 3000A. Threshold Current:- The minimum available fault current at which a fuse is current limiting. Total clearing time:- The operating time or total clearing time is the sum of the pre arcing time and the arcing time. Very Fast-Acting Fuses:- Very fast-acting (Current-Limiting) fuses will limit both the magnitude and duration of current flow under short circuit conditions. Because of their high current limiting ability, these fuses are frequently used to protect semiconductor circuits. Virtual time:- The virtual time is the value of Joule integral divided by the square of the prospective current value. Usually stated for a MV-fuse link, are the values of pre-arcing time and of operating time. Virtual Melting time:- Standardised value of melting time, which considers currents of types AC or DC and the different current curves and switching angles. The Melting Time in the Time/CurrentCharacteristics is generally given by the Virtual Melting Time. The value is calculated by the Melting integral of the Rated Current. Voltage Rating:- The maximum voltage at which a fuse is designed to operate. The maximum open circuit voltage in which a fuse can be used, yet safely interrupt an overcurrent. Exceeding the voltage rating of a fuse impairs its ability to clear an overload or short circuit safely. Voltage ratings are assumed to be for AC, unless specifically labelled as DC. Glossary of Relay terminology Arc:- An electric discharge between mating relay contacts when an energized circuit is interrupted. Plasma current flow between opening relay contacts. An arc is enabled by the electric power of the load circuit (turn off spark) ionizing the gas between the contacts. The stability of the arc depends on various parameters such as contact material, air pressure, contact gap, etc. An arc locally produces high temperature causing contact erosion. In cases of strong erosion, spark suppression becomes necessary. Arc suppression:- An arc will form as contacts come together and currents flow, and when they break apart. With ac current the condition is seldom a problem in relays, but with high dc loads the arc can be substantial causing contact damage. Arc suppression can be achieved using a blow out magnet. Bounce:- Occurs as a moving contact strikes a fixed contact and ‘bounces’ before remaining full at rest. This has to be minimised, as creates signal noise and contact wear. Bounce, armature:- See rebound, armature. Bounce Time:- The time from the first to the last closing or opening of a relay contact. Break:- The opening of closed contacts to interrupt an electrical circuit. Break-Before-Make:- Disconnecting the present circuit before connecting a new circuit. Also known as Break/Make.

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Break Contact:- NC contact. The break contact is closed in the release (rest) state of a monostable relay and opens (breaks) when the armature moves to the core (operate state). Bridging:- (1) Normal bridging: The normal make-before-break action of a make-break or D contact combination. In a stepping switch, the coming together momentarily of two adjacent contacts by a wiper shaped for that purpose in the process of moving from one contact to another. (2) Abnormal bridging: The undesired closing of open contacts caused by a metallic bridge or protrusion developed by arcing. Bunching, contact:- The undesired, simultaneous closure of make-and-break contacts during vibration, shock, or acceleration. Also, the simultaneous closure of the contacts of a continuity transfer or bridging contact combination. Changeover Contact:- Contact configuration with make and break contact. Changing the switch position opens the closed contact first and then closes the formerly open contact. Chatter, armature:- The undesired vibration of the armature due to inadequate ac performance or external shock and vibration. Chatter, Contact:- Externally caused, undesired vibration of mating contacts during which there may or may not be actual physical contact opening. If there is no actual opening but only a change in resistance, it is referred to as dynamic resistance. Closing Time:- Time between energization of the coil until the moment the contacts of the first current path to be closed actually close. Coil:- That part of a relay which is energised to create a magnetic field that attracts a lever that in turn carries out the switching function. An assembly consisting of one or more windings, usually wound over an un-insulated iron core on a bobbin or spool. May be self-supporting, with terminals and any other required parts such as a sleeve or slugs. 1. Concentrically Wound-: A coil with two or more insulated windings wound one over the other. 2. Double Wound-: A coil consisting of two windings wound on the same core. 3. Parallel Wound:- A coil having multiple windings wound simultaneously, with the turns of each winding being contiguous, termed bifilar wound. 4. Sandwich Wound:- A coil consisting of three concentric windings in which the first and third windings are connected series aiding to match the impedance of the second winding. The combination is used to maintain transmission balance. 5. Tandem Wound:- A coil having tow or more windings, one behind the other, along the longitudinal axis. Also referred to as a two, three, or four-section coil, etc. Coil Hi-Pot:- The minimum voltage (potential) which the relay coil terminals will isolate when the relay is properly mounted. Coil Operating Range:- Expressed as a multiple of the rated control circuit voltage Vc for the lower and upper limits. Coil Resistance:- The DC resistance of the energised relay coil measured at 25°C, not including a parallel device for coil suppression. Shock - The number of gravities (G's) a relay can sustain when tested by a ½ sine pulse (calibrated impact) for 11 milliseconds without the closed contacts opening or the open contacts closing. Vibration - The simple harmonic motion at rated gravities and frequency (G/Hz) that a relay can sustain without uncontrolled opening of closed contacts or closing of open contacts. Coil Suppression Circuit:- Circuit to reduce the inductive switch off voltage peak of the relay coil (EMC protection, switch off voltage peak). Note that most of the circuits reduce the armature release speed, which can decrease the relay lifetime, especially valid for diodes in parallel to the coil. From the various solutions, the use of a Zener diode is particularly suitable. Cold:- An unenergized electrical circuit. Cold Switching:- Closing the relay contacts before applying voltage and current, plus removing voltage and current before opening the contacts. (Contacts do not make or break current.) Also termed Dry Circuit Switching. Larger currents may be carried through the contacts without damage to the contact area since contacts will not arc when closed or opened. Maximises contact life. Contact:- Made out of contact material and part of the contact set where the electrical load circuit is opened or closed. Contact Arrangement:- Relays are typically one of the following arrangements and contact forms: single pole single throw (SPST) - Normally Open, NO, NO-double make Normally Closed, NC, NC-double break latching single pole double throw (SPDT) - latching double pole double throw (DPDT) four pole double throw (4PDT) Contact, Auxiliary:- A contact combination used to operate a visual or audible signal to indicate the position of the main contacts, establish interlocking circuits, or hold a relay operated when the original operating circuit is opened.

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Contact Bounce:- The intermittent undesirable opening of closed mechanical contacts or closing of open contacts. Internally caused intermittent and undesired opening of closed contacts, or closing of open contacts, of a relay, caused by one or more of the following: (1) Impingement of mating contacts; (2) Impact of the armature against the coil core on pickup or against the backstop on dropout; (3) Momentary hesitation or reversal of the armature motion during the pickup or dropout stroke. Contact bounce period depends upon the type of relay and varies from ½ms for small reed relays to 10-20ms for larger solenoid types. Solid-state or mercury wetted contacts (Hg) do not have a contact bounce characteristic. Contact, Break:- See contact, normally closed. Contact, break-before-make:- A contact combination in which one contact opens its connection to another contact and then closes its connection to a third contact. Contact, break-make:- See contact, break-before-make. Contact Capacitance:- The capacitance of the relay measured (a) between the open contact, or (b) between contact terminals and ground. Measured at 1 kHz. Contact Configuration:- Relay switch configuration (make, break or changeover contact). According to the application, various contact configurations are used. Contacts which are moved by the armature system are called → movable contacts, and non moving contacts stationary contacts. Contact, Double Break:- A contact combination in which contact on a single conductive support simultaneously open electrical circuits connected to two independent contacts. This provides two contact air gaps in series when the contact is open Note: In B combination is terminal is brought out form the movable contact. In the Y combination, it is not. Contact, Double Make:- A contact combination in which contacts on a single conductive support simultaneously close electrical circuits connected to the contact of two independent contacts, and provides two contact air gaps in series when the contact is open. (Sometimes called normally open, double-make contact.) Note: In U combination a terminal is brought out from the movable arm. In the X combination it is not. Contact, Double Throw:- A contact combination having two positions as in break-make, make-break, and the like. Contact Erosion:- Material loss at the contact surfaces, for example due to material evaporation by an arc. Contact Force:- The force which two contact tips (points) exert against each other in the closed position under specified conditions. Contact Gap:- The gap between the contact tips (points) under specified conditions, when the contact circuit is open. Contact Interrupter:- On a stepping relay or switch, a contact combination operated directly by the armature that opens and closes the winding circuit, permitting the device to step itself. Contact Life:- The maximum number of expected closures before failure. Life is dependent on the switched voltage, current, and power. Failure is usually when the contact resistance exceeds an end of life value. Typical failure mode is non-closure of the contact as opposed to a contact sticking closed. Contact, Low Level:- Contact that control only the flow of relatively small currents in relatively lowvoltage circuits; e.g., alternating currents and voltages encountered in voice or tone circuits, direct currents in the order of microamperes, and voltages below the softening voltages of record for various contact materials (that is, 0.080 volt for gold, 0.25 volt for platinum, etc.) Also defined as contacts switching loads where there is no electrical arc transfer of detectable thermal effect and where only mechanical forces can change the conditions of the contact interface. Contact, Main:- The primary set of contacts of a relay, usually defined as those having the highest current rating. Contact, Make:- See contact, normally open. Contact, make-before-break:-See contact, continuity transfer. Contact, make-break:- See contact, continuity transfer. Contact Material:- For relays a variety of contact materials are in use. They operate under a wide range of loads in terms of voltage and current. Inductive loads can cause high switch off voltages and strong arcs, capacitors create inrush current peaks. Arcs and improper coil suppression can reduce the lifetime of a contact. So far, no universal contact material is known, that can be used on all load types with optimum performance. Contact manufacturers, relay developers, and users have established the following criteria to describe a contact: • Electrical resistance • Resistance to contact erosion • Resistance to material transfer • Resistance to welding

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Contact, Normally Closed:- A contact combination which is closed when the armature is in its unoperated position. A pair of contacts are together at rest making an electrical circuit. Contact, Normally Open:- A contact combination that is open when the armature is in its unoperated position. A pair of contacts are separated at rest with no electrical connection. (Generally applies to monostable relays.) Contact, Off:- normal-A form C contact combination on a stepping switch that is in one condition when the relay or stepping switch is in its normal position and in the opposite condition for any other position of the relay or stepping switch; i.e., when not in its reset or home position. Contact, Operate Time:- Time from initial energization to the first opening of closed contact or first closing of open contact, prior to bounce. Contact Potential:- A voltage produced between contact terminals due to the temperature gradient across the relay contacts, and the reed-to-terminal junctions of dissimilar metals. (The temperature gradient is typically caused by the power dissipated by the energized coil.) Also known as contact offset voltage, thermal EMF, and thermal offset. This is a major consideration when measuring voltages in the microvolt range. There are special low thermal relay contacts available to address this need. Special contacts are not required if the relay is closed for a short period of time where the coil has no time to vary the temperature of the contact or connecting materials (welds or leads). Contact Rating:- The voltage, current, and power capacities of relay contacts under specified environmental conditions. Contact, Reed:1. A glass-enclosed, magnetically operated contact using thin, flexible, magnetic conducting strips as the contacting members. 2. Contact assembly, the contact members of which are blades either fully or partly of magnetic material and which are moved directly by a magnetic force. Contact Release Time:- Time form initial de-energization of the relay coil to the first opening of a closed contact prior to bounce. Contact Resistance:- The resistance between closed load contacts. In vacuum relays, this measurement is typically made at 6V dc with a 1A rms load. In gas-filled relays, 1A at 28V dc is used to measure contact resistance. ‘Kelvin’ connections should be used to obtain accurate readings. The resistance can be obtained from the ratio of the voltage drop across the relay and the load current (Ohm’s law). Surface layers (fritting) can result in non-linear contact resistances and increased voltage. Contact Transfer Time:- Time during which the moving contact first opens from a closed position and first makes with the opposite throw of the contact. It is floating in a non-contacting position prior to bounce and after energizing or de-energizing the coil. Contact Weld:- A contact failure due to fusing of contacting surfaces to the extent that the contacts fail to separate when intended. Continuous Current, Carry:- The maximum current that can be carried by the closed contacts of the relay for a sustained time period. This current rating is determined by the relay envelope temperature rise and must be derated at RF frequencies. A glass relay is allowed a 62°C rise, and a ceramic relay a 100°C temperature rise. Current ratings can be increased by external cooling, such as by forced air or heat sinks. Crosstalk:- The electrical coupling between a closed contact circuit and other open or closed contact on the same relay or switch, expressed in decibels down form the signal level. Current, maximum rate of rise on state (di/dt):- The maximum non-repetitive rate of current rise the output can withstand without being damaged. 1. With the relay output(s) turned on by the application or removal of the control voltage and/or current. 2. With the relay output(s) driven into break-over with the input at non-operate level. Current, minimum load, ITmin(rms):-The minimum current required to maintain the relay in the on-state (nominal load voltage applies). Applies mainly to solid-state relays. Current, non-repetitive surge, ITSM:- The maximum allowable, non-repetitive, peak, sinusoidal current that may be applied to the output for one full cycle at nominal line frequency. Relay control may be lost during and following the surge until the junction temperature falls below the maximum rated temperature. Current rated contact:- The current which the contacts are designed to handle for their rated life. Current, repetitive overload, ITO(rms) -The maximum allowable repetitive rms overload current that may be applied to the output for a specific duration and duty cycle while still maintaining output control. Applies mainly to solid state relays. De-energize:- To remove power from a relay coil. Dielectric:- An insulating medium capable of recovering, as electrical energy, all or part of the energy required to establish an electrical field (voltage stress). The field, or voltage stress, is accompanied by displacement or charging currents. A vacuum is the only perfect dielectric.

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Dielectric strength, VISO:- The maximum allowable ac rms voltage (50/60Hz) which may be applied between two specified test points such as input-output, input-case, output-case in solid state relays, and between current-carrying and non-current-carrying metal members in electromechanical relays, without a leakage current in excess of 1mA. Dropout, to drop out:- A monostable relay drops out when it changes from an energized to an unenergized condition. Not applicable latching relays. Dropout, time:- See time, release. Dropout Voltage:- The maximum coil voltage at which an operating relay releases and all normally closed contacts close. The voltage at which a relay (coil) de-energises sufficiently for the operating lever to move back to its rest position. It is normally expressed as a % of the nominal coil voltage. Dry Circuit Switching:- Switching below specified levels of voltage and current to minimize any physical and electrical changes in the contact junction. Also see Cold Switching. Dry reed relay:- See relay, reed. Dynamic contact resistance:- A change in contact electrical resistance due to a variation in contact pressure on a contacts mechanically closed; occurrence is during non-bounce condition. Electrical Endurance:- Number of on-load operating cycles (i.e. with current on the main contacts) a contactor can achieve, without failure, varies depending on the utilization category. The lifetime varies with the load. If not stated otherwise, the reference values apply for resistive or inductive loads with suitable spark suppression. Electrostatic screening:- Screening plate between coil and contact to provide electrostatic screening in reed relays. Energization:- The application of power to a coil winding of a relay to generate a magnetic field to move the armature. With respect to an operating coil winding, use of the word commonly assumes enough power to operate the fully. The energizing value is the product of the coil current and the number of wire turns of the coil. Expected Mechanical Life:- The minimum number of operations for which a relay can be expected to operate reliably. "Cold" switching applications approach this figure. Form:- A: Configuration which has one single-pole single-throw normally open (SPST no) contact. B: Configuration which has one single-pole single-throw normally closed (SPST nc) contact. C: Contact configuration which has one single pole-double throw (SPDT) contact. (One common point connected to one normally open and one normally closed contact.) Sometimes referred to as a transfer contact. Freezing, magnetic:- Sticking of the relay armature to the core due to residual magnetism. Fritting:- Electrical breakdown which can occur under special conditions (voltage, current) whenever thin contact films prevent electrical conductivity between closed contacts. Fritting is a process which generates (A-fritting) and/or widens (B-fritting) a conducting current path through such a semiconducting film on a contact surface. During A-fritting, electrons are injected into the undamaged film. The electron current alters the condition of the film producing a ‘conductive channel’. During the following B-fritting, the current widens the channel increasing the conductivity. Gaging, relay contact:- The setting of relay contact spacing to determine the point in the armature's stoke at which specified contacts function. Gap, contact:- The distance between a pair of mating relay contacts when the contacts are open. Gap, heel:- A gap or nonmagnetic separation in the magnetic circuit other than between the armature and pole face. Generally, located between the heel piece and pole piece of an ac relay. Gap, residual:- The thickness of nonmagnetic material in the magnetic circuit between the pole face centre and the nearest point on the armature when the armature is in the fully seated position. Grass:- See dynamic contact resistance. Hard failure:- Permanent failure of the contact being tested. Hermetic seal:- An enclosure that is sealed by fusion to ensure a low rate of gas leakage. In a reed switch, a glass-to-metal seal is employed. Hesitation, armature:- Delay or momentary reversal of armature motion in either the pickup or dropout stroke. Hold value specified:- As the current or voltage on an operated relay is decreased, the value at or above which all relay contacts must restore to their un-operated positions. Hold Voltage:- The lowest voltage that can be applied without any change in state of the contacts from their energized position. This is just above the maximum drop-out voltage. Hot:- An energized electrical circuit. Hot switching:- A circuit design that applies the switched load to the switch contacts at the time of opening and closure. Inrush:- Inrush current is the peak current passing across the contacts of a relay when the contact is first made and is dependent on the load being switched. A relay which has contacts rated for a continuous current, the nominal contact current, may be capable of withstanding much higher currents for short periods. Inrush current can form a surge flowing through a relay switching a

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low impedance source load - typically a highly reactive circuit, or one with a non-linear load characteristic such as a tungsten lamp load. Such abusive load surges are sometimes encountered when reed relays are inadvertently connected to test loads containing undischarged capacitors, or to long transmission lines with appreciable amounts of stored capacitive energy. Excessive inrush currents can cause switch contact welding or premature contact failure. Insulation resistance, RISO:- The minimum allowable dc resistance between input and output of solid state relays and between contacts and coil for electromechanical and reed relays, at a specified voltage, usually 500V dc. Isolation:- The value of insulation resistance, dielectric strength, and capacitance measured between the input and outputs, input to case, output to case, and output to output when applicable. Latching:- In relay or switching technology, this refers to the ability to keep the contact status in place even if power is removed from the equipment. Latching relay:- In a latching relay, after the coil input voltage is disconnected, the contacts remain in the last reached switching position. Normally latching relays are reset contact position. Latching relays only require a short set respectively reset impulse. A permanent coil power supply after setting/resetting the relay is neither necessary nor allowed: maximal pulse durations depend on the relay family. Hence the distinguishing characteristic of monostable relays in respect to a fail safe behaviour is the fact that the predefined contact rest position will be reached at break down of the power supply. This behaviour cannot be shown by latching relays due to the bistable working principle they are based on. Leakage Current:- The rms current conducted by the output circuit of the relay at maximum rated voltage with the contacts open. Limiting continuous current:- The highest current (effective value for AC loads) a relay can carry under specified conditions without exceeding its specified upper limit temperature. This is not the current that can be switched with any load over the specified lifetime. Load:- The electrical circuit which is being switched is measured and defined by 1. current in amperes, A 2. voltage in volts, V: dc or ac, and 3. load type (Inductive or resistive current flow when the contact is first made). A relay is generally limited by the amount of heat that occurs when an electrical current passes across its contacts. This represents the ‘load’ that a relay can switch and is normally presented as an electrical value This is usually stated as a contact current in A then a voltage often standardised at 250Vac/dc followed by a maximum capacity at a resistive load. This is the result of multiplying current by voltage, expressed as VA. It is usually the maximum permissible load at any time including starting and stopping. Load, curve:- The static force/displacement characteristics of the total spring-load of the relay. Load Life:- The minimum number of cycles the relay will make, carry, and break the specified load without contact sticking or welding, and without exceeding the electrical specifications of the device. Load life is established using various methods including Weibull probability methods. Magnet, blowout:- A device that establishes a magnetic field in the contact gap to help extinguish the arc by displacing it. Magnetic interaction:- Mainly relevant to reed relays. The tendency of a relay to be influenced by an external magnetic field. This influence can result in depression or elevation of the pull-in and drop out voltage of the affected relay, possibly causing operation outside its specification. Magnetic interaction can be minimized by alternating the polarity of adjacent relay coils, by magnetic shielding, or by placing two relays at right angles to each other. Magnetic shield:- Mainly relevant to reed relays. A ferromagnetic material used to minimize magnetic coupling between the relay and external magnetic fields. Make:- The closure of open contacts to complete an electric circuit. Maximum operate voltage (or must operate voltage):- Voltage at room ambient temperature (RT) a relay must operate at. To guarantee proper function of all relays, the applied coil voltage in the application must be above this specified operating voltage. The actual operate voltage of an individual relay, the maximum operate voltage and the application system value are sometimes all called operate voltage. Maximum voltage Umax or Vmax:- Maximum coil voltage at RT, at which the coil reaches the specified upper limit temperature without contact load (maximum continuous thermal load at 23°C). Maximum switching power:- Maximum permissible power switched by the relay contacts, i.e. the product of the switching current and switching voltage. Mechanical Endurance:- Number of off-load operating cycles (i.e. without current on the main contacts) a contactor can achieve. Mechanical Life:- This is the number of operations which a relay can be expected to perform while maintaining mechanical integrity. Mechanical life is normally tested with no load or voltage applied to the power contacts and is established using various methods including Weibull analysis.

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Mechanical shock, non-operating:- The mechanical shock level (amplitude, duration and wave shape) to which the relay may be subjected without permanent electrical or mechanical damage (during storage or transportation). Mechanical shock, operating:- That mechanical shock level (amplitude, duration and wave shape) to which the relay may be subjected without permanent electrical or mechanical damage during its operating mode. Mercury wetted (contact) relay:- A form of reed relay in which the contacts are wetted by a film of mercury (Hg) obtained by a capillary action from a mercury pool encapsulated within the reed switch. Usually has a required operating position (usually vertical) to avoid liquid mercury from shorting the contacts; other types are position insensitive. This type of relay is usually higher power and longer life, but at a higher dollar cost. Another benefit of this type of contact is the repeatability of contact resistance and virtually no contact bounce. Minimum recommended voltage:- Minimum load voltage to ensure an adequate contact cleaning (see also ‘fritting’). Minimum voltage Umin or Vmin:- Minimum coil voltage at RT where a relay is still able to operate. Minimum release voltage (must release voltage):- Voltage at RT a relay must release at. To guarantee proper function of all relays, the limit in the application must be below this specified release voltage .The release voltage of an individual relay, the guaranteed minimum (must) release voltage and the system value are sometimes all called release voltage. Minimal operation time:- Shortest control duration to ensure complete closing or opening of a contactor. NC contact (normally closed):- Same as break contact. The break contact is closed in the release (rest) state of a monostable relay and opens (breaks) when the armature moves to the core (operate state). NO contact (normally open):- Same as make contact. Contact is open in the release (rest) state of a monostable relay and closes (makes) when the relay coil is energized (operate state). Nonpickup value, specified:- As the current or voltage on an unoperated relay is increased, the value which must be reached before any contact change occurs. Nonrelease, specified:- See operating characteristics, hold value. Offstate dv/dt:- The application of both position and negative voltages with maximum specified rate of rise to the output terminals. Operate:- A relay operates when sequentially it starts, it passes from an initial condition towards the prescribed operated condition, and it switches. Operating characteristics:- Pickup, non-pickup, hold and dropout, voltage and current. Operating temperature range:- The ambient temperature range over which an un-mounted relay is specified to operate. Opening time:- Time from the beginning of state causing breaking until the moment when the contacts of the last current path to be opened are open.

Operate time:- The time in milliseconds between voltage being first applied to the relay coil and final closure of all normally open contacts or the time from energizing the relay coil till the first break of the NC contact. This includes time for the coil to build up its magnetic field (a significant limiting factor) and transfer time of the moveable contact between stationary contacts, and bounce time after the initial contact make. As the coil resistance depends on the ambient temperature, the operate time varies with the operate voltage and the ambient temperature. Overdrive:- A term used to indicate use of greater than normal coil current (applied voltage), and usually employed in obtaining well-controlled bounce and fast operate time or pulse response. Overload current:- Test done to make sure that relays withstand overload conditions, e.g. withstand short circuit conditions until the fuse opens. Relay will carry the specified currents at 23°C (Irated = rated current as given in contact data section for each relay).

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Overtravel armature dropout:- The portion of the armature travel that occurs between closure of the normally closed contact(s) and the fully released static position of the armature. Overtravel armature pickup:- The portion of the armature travel occurring between closure of the normally open contact(s) and the fully operated static position of the armature. Paschen test:- Test to detect sealing damage to a hermetically seal capsule. In the case of a cracked switch capsule or damaged switch seal, atmospheric oxygen can leak into the switch and eventually oxidize the switch contacts, causing increased contact resistance and possible contact failure. The presence of oxygen causes the breakdown avalanche voltage to increase, due to the ability of the electronegative oxygen to scavenge free electrons. The Paschen test observes the variation and magnitude of the breakdown voltage as a switch is opened, hence used to diagnose the presence of oxygen. Peak Test Voltage:- The peak AC voltage (at 60 Hz) which can be applied between external high voltage terminals or between the open terminals and ground for up to one minute with no evidence of failure. Peak test voltages must not be exceeded, even for very short pulses. Pole, double:- A term applied to a contact arrangement to denote that it includes two separate contact combinations, that is, two single-pole contact assemblies. Pole piece:- The end of an electromagnet, sometimes separable from the main section, and usually shaped so as to distribute the magnetic field in a pattern best suited to the application. Pole, single:- A term applied to a contact arrangement to denote that all contacts in the arrangement connect in one position or another to a common state. Pull-in Voltage:- The minimum coil voltage required to operate a relay for all normally open contacts to close. The voltage at which a relay (coil) operates and switches. It is normally expressed as a % of the nominal coil voltage. Sometimes known as threshold voltage. It is affected by temperature. Race, relay:- A deficient circuit condition wherein successful operation depends upon a sequence of two or more independent contacts and in which the sequence is not insured by electrical or mechanical interlocking restraints. Ratchet relay. See relay, stepping. Relay:- An electrically controlled mechanical device that opens and closes electrical contacts when a voltage (or current) is applied to a coil. A relay provides isolation of control signals from switched signals. Rated breaking capacity; Rated making capacity:- Value of rms current a contactor can break or make at a fixed voltage value, within the conditions specified by the standards, depending on the utilization category. Rated impulse withstand voltage, Vimp:- The highest peak value of an impulse voltage of prescribed form 1.2/50, which does not cause breakdown under specified conditions of test. Rated insulation voltage, Vi:- Voltage value which designates the unit and to which dielectric tests, clearance and creepage distances are referred. Rated operating current, Ie:- Current value stated by the manufacturer and taking into account the rated operating voltage, Ve, the rated frequency, the rated duty, the utilization category, the electrical contact life and the type of the protective Hammond Enclosure. Rated operating voltage, Ve:- Voltage value to which utilization characteristics of the contactor are referred, i.e. phase to phase voltage in 3 phase circuits. The voltage which can safely be applied to the relay for sustained periods of time without failure. This voltage rating decreases as AC frequency increases. Rated operating voltages approach peak test voltage only at lower frequencies. Rating, contact:- The electrical load-handling capability of relay contacts under specified conditions and for a prescribed number of operations. Rating, short time:- The value of current or voltage that the relay can stand, without injury, for specified short time intervals. (For ac circuits, the rms total value, including the dc component, should be used). The rating recognized the limitations imposed by both thermal and electromagnetic effects. Rebound, armature:- (1) The return motion or bounce-back toward the unoperated position after the armature strikes the pole face during pickup, referred to as armature pickup rebound; (2) The forward motion or bounce in the direction of the operated position when the armature strikes its backstop on dropout, referred to as armature dropout rebound. Relay:- An electric device that is designed to interpret input conditions in a prescribed manner and after specified conditions are met to respond to cause contact operation or similar abrupt change in an associated electric control circuit. Notes: (a) Inputs are usually electric, but may be mechanical, thermal or other quantities. (b) A relay may consist of several units, when responsive to specified inputs, the combination providing the desired performance characteristic. Relay, alternating current (ac):- A relay designed for operation from an alternating-current source. Relay, direct current (dc):- A relay designed for operation from a direct-current source. Relay, electrical:- A device designed to produce sudden, predetermined changes in one or more electrical output circuits, when certain conditions are fulfilled in the electrical input circuits

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controlling the device. 1. The term relay shall be restricted to a relay unit having a single relaying function between its input circuits and its output circuits. 2. The term relay includes all the components which are necessary for its specified operation. 3. The adjective ‘electrical’ can be deleted when no ambiguity may occur. Relay, electromechanical:- An electrical relay in which the designed response is developed by the relative movement of mechanical elements under the action of a current in the input circuits. Relay, latching:- A relay that maintains its contacts in the last position assumed without the need of maintaining coil energization. 1. Magnetic latching- A relay that remains operated, held either by remanent magnetism in the structure or by the influence of a permanent magnet, until reset. 2. Mechanical latching- A relay in which the armature or contacts may be latched mechanically in the operated or unoperated position until reset manually or electrically. Relay, mercury contact:1. Mercury-wetted contact-A form of reed relay in which the reeds and contacts are glass enclosed and are wetted by a film of mercury obtained by capillary action from a mercury pool in the base of a capsule vertically mounted. 2. Mercury contact-A relay mechanism in which mercury establishes contact between electrodes in a sealed capsule. Relay, over current:- A relay that is specifically designed to operate when its coil voltage reaches or exceeds a predetermined value. Relay, polarized:- A relay whose operation is dependent upon the polarity of the energizing current. 1. Bistable. A tow-position relay that will remain in its last operated position keeping the operated contacts closed after the operating winding is de-energized. 2. Centre-stable. A polarized relay that is operated in one of two energized positions, depending on the polarity of the energizing current, and that returns to a third, off position, when the operating winding is de-energized. 3. Double-biased. See bistable. 4. Magnetic latching. See bistable. 5. Monostable. A monostable polarized relay is a two-position relay that requires current of a pre-determined polarity for operation and returns to the off position when the operating winding is de-energized or is energized with reversed polarity. 6. Single-biased. See monostable. 7. Single-side-stable. See centre-stable. 8. Three-position centre-off. See centre-stable. 9. Un-biased. See centre-stable. Relay, reed:- A relay using glass-enclosed, hermetically sealed, magnetically actuated reeds as the contact members. No mercury or other wetting material is used. Typical atmosphere inside the glass enclosure is nitrogen. Relay, RF switching:- A relay designed to switch electrical ac energy frequencies >20kHz. Relay, solid state (SSR):- A relay with isolated input and output whose functions are achieved by means of electronic components and without moving parts. Relay, undercurrent:- A relay specifically designed to function when its energizing current falls below a predetermined value. (See relay, current sensing.) Relay, undervoltage:- A relay specifically designed to function when its energizing voltage falls below a predetermined value. Relay, vacuum:- A relay whose contacts are sealed in a low pressure environment. Release Time:- The time in milliseconds between removal of power from the relay coil and final closure of all normally closed contacts. This time includes contact bounce. Resistance, contact:- The electrical resistance of closed contacts measured at the associated terminals. Resistance, dynamic contact:- Variation in contact resistance due to changes in contact pressure during the period in which contacts are motion, before opening or after closing. Resistance to shock:- Requirements applicable for instance to vehicles, crane operation or switchgear slide-in module systems. At the quoted permissible ‘g’ values, contactors must not undergo a change in switching state and O/L relays must not trip. Resistance to vibration:- Requirements applicable to all the vehicles, vessels and other similar transport systems. At the quoted amplitude and vibration frequency values, the unit must be capable to achieve the required duty. Resistance, winding:- The total terminal-to-terminal resistance of a winding at a specified temperature. Self de-energize:- The removal of power from a relay coil by an auxiliary switch or contact within the relay itself. Usually applies to latching relays only. Self de-energizing switch:- A secondary relay or auxiliary contact usually enclosed within the primary relay which removes power from the primary relay coil after it has transferred position. Usually applies to latching relays only.

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Shield, electrostatic:- A conductive metallic sheath surrounding the relay’s reed switch, connected to at least one external relay pin, and designed to minimize capacitive coupling between the switch and other relay components, thus reducing high frequency noise pickup. Similar to a coaxial shield, but not necessarily designed to maintain a 50 Ohm RF impedance environment. Shield, magnetic:- An optional plate or shell constructed of magnetically permeable material such as nickel-iron or mu-metal, fitted external to the relay’s coil. Its function is to reduce the effects of magnetic interaction between adjacent relays, and to improve the efficiency of the relay coil. A magnetic shell also reduces the influence of external magnetic fields, which is useful in security applications. Magnetic shields can be fitted externally, or may be buried inside the relay housing. Soft failure:- Intermittent, self-recovering failure of a contact. Static contact resistance:- The DC resistance of closed contacts as measured at their associated contact terminals. Measurement is made after stable contact closure is achieved. Sticking (contacts):- A reed switch failure mechanism, whereby a closed contact fails to open by a specified time after relay de-energization. Can be sub-classified as hard or soft failures. Switch, dry reed:- See contact, reed. Switch, stepping:- A class of electromagnetically operated, multiposition switching devices. Their wipers are rotated in steps so that contact is successively made between the wiper tips and contacts that are separated electrically and mounted in a circular arc called a bank. Switching Capacity:- Switching capacity is the product of switching voltage and switching current. The current which a relay will switch will vary according to the voltage being used. Note that the maximum often includes the value occurring at peaks (see ‘inrush’). A minimum also applies, because contact materials that can withstand high current loads may be poor at making contact at low current loads. Switching frequency:- Number of operating cycles per hour. Short time current permissible:- Value of current which the contactor can withstand in closed position for a short time period and within specified conditions. Time, actuation:- The time interval from coil energization or de-energization to the functioning of a specified contact; same as time, contact actuation, subdivided as follows: 1. Time, final actuation-The sum of the initial actuation time and the contact bounce intervals following such actuation. 2. Time, initial actuation-The time from coil energization or de- energization to the first closing of a previously open contact or the first opening of a previously closed contact. Time, bridging:- The time in which all contacts of a continuity transfer combination are electrically connected during the transfer. Time constant:- Ratio of inductance to the resistance : L/R = mH/Ohm, ms. Time, contact bounce:- The time interval from initial actuation of a contact to the end of bounce. Time, contact stagger:- The time interval between the functioning of contacts on the same relay.(For example, the time difference between the opening of two normally closed contacts on pickup.) Time, operate:- (1) The time interval from coil energization to the functioning of the last contact to function. Where not otherwise stated, the functioning time of the contact in question is taken as its initial actuation time (that is, it does not include contact bounce time). (2) For a solid state or hybrid relay in a non-operated state, the time from the application of the pickup voltage to the change of state of the output. Time, release:- (1) The time interval from coil de-energization to the functioning of the last contact to function. Where not otherwise stated, the functioning time of the contact in question is taken as its initial actuation time (that is, it does not include contact bounce time). (2) For a solid state or hybrid relay in an operated state, the time from the application of the dropout voltage to the change of state of the output. Time, seating:- The time interval from coil energization to the seating of the armature. Time transfer:- The time interval between opening the closed contact and closing the open contact of a break-before-make contact combination. Type 1 co-ordination:- There has been no discharge of parts beyond the enclosure. Damage to the contactor and the overload relay is acceptable. Type 2 co-ordination:- No damage to the overload relay or other parts has occurred, except that welding of contactor or starter contacts is permitted, if they are easily separated. Voltage Breakdown:- An undesirable condition of arcing within a relay due to over-voltage. Voltage, off state:- In solid state relay, the following determine whether the relay will stay off under each load voltage condition: 1. Critical rate of rise of commutation voltage, dv/dt. The maximum value of the rate of rise of principal voltage which will cause switching from the off state to the on state. 2. Maximum off state voltage, VD max rms. The maximum effective steady state voltage that the output is capable of withstanding when in off state. 3. Maximum rate of rise of off state voltage, dv/dt. The rate of rise of the off-state voltage which the output can withstand without false operation.

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4. Minimum off state voltage, VD min rms. The minimum effective voltage which the relay will switch. 5. Non-repetitive peak voltage, VDSM. The maximum off-state voltage that the output terminals are capable of withstanding without breakover or damage. Voltage, on state:- In solid state relays, the output terminal wave form at rated current consists of repetitive half-cycles (+and-) of distinctive voltage drops. Each voltage state is necessary for load current conduction and may be specified for specific applications, as follows: 1. Instantaneous on state voltage, VT. The instantaneous voltage across the output when in the on condition. 2. Maximum RMS on state voltage, VT RMS. Maximum RMS voltage drop across the relay output at maximum load current IT RMS. 3. Minimum power factor load, PFMIN. The minimum power factor load the relay will switch and still meet all of its electrical specifications. 4. Peak on state voltage, VTM. The maximum value of VT excluding ± 20° of zero crossing of the voltage waveform. Voltage, rated coil:- The coil voltage at which the relay is intended to operate for the prescribed duty cycle. Note: The use of any coil voltage less than rated may compromise the performance of the relay. Voltage, reverse polarity:- The maximum allowable reverse voltage which may be applied to the input of a solid state relay without permanent damage. Winding, non-inductive:- A winding in which the magnetic fields produced by two parts of the winding cancel each other and provide non-inductive resistance. Glossary of Varistor terminology AC Standby Power (Varistor), PD:- Varistor AC power dissipation measured at rated rms voltage VM(ac). Capacitance (Varistor), C:- Capacitance between the two terminals of the varistor measured at C specified frequency and bias. Clamping Voltage, VC:- Peak voltage across the varistor measured under conditions of a specified peak VC pulse current and specified waveform. Peak voltage and peak currents are not necessarily coincidental in time. Dynamic Impedance (Varistor), ZX:- measure of small signal impedance at a given operating point as defined by: ZX =dVX /dIX Lifetime Rated Pulse Currents (Varistor):- Derated values of ITM for impulse durations exceeding that of an 8/20µs wave-shape, and for multiple pulses which may be applied over device rated lifetime. Nominal Varistor Voltage, VN(dc):- Voltage across the varistor measured at a specified pulsed DC current, IN(dc), of specific duration, IN(dc) of specific duration. IN(dc) is specified by the varistor manufacturer. Nonlinear Exponent, α:- A measure of varistor nonlinearity between two given operating currents, I1 and I2, as described by I = kVα where k is a device constant, I1 ≤ I ≤ I2, and α12=logI2 ⁄ I1 / log V2 ⁄ V1 Overshoot Duration (Varistor):- The time between the point voltage level (VC) and the point at which the voltage overshoot has decayed to 50% of its peak. For the purpose of this definition, clamping voltage is defined with an 8/20µs current waveform of the same peak current amplitude as the waveform used for this overshoot duration. Peak Nominal Varistor Voltage, VN(ac) Voltage across the varistor measured at a specified peak AC current, IN(ac), of specific duration. IN(ac) is specified by the varistor manufacturer. Rated DC Voltage (Varistor), VM(dc):- Maximum continuous DC voltage which may be applied. DC Standby Current (Varistor), ID:- Varistor current measured at rated voltage, VM(dc). Rated Peak Single Pulse Transient Currents (Varistor), ITM:- Maximum peak current applied for a single 8/20µs impulse, with rated line voltage also applied, without causing device failure. Rated Recurrent Peak Voltage (Varistor), VPM:- Maximum recurrent peak voltage which may be applied for a specified duty cycle and waveform. Rated RMS Voltage (Varistor), VM(ac):- Maximum continuous sinusoidal RMS voltage which may be applied. Rated Single Pulse Transient Energy (Varistor), WTM:- Energy which may be dissipated for a single impulse of maximum rated current at a specified wave-shape, with rated RMS voltage or rated DC voltage also applied, without causing device failure. Rated Transient Average Power Dissipation (Varistor), PT(av)M:- Maximum average power which may be dissipated due to a group of pulses occurring within a specified isolated time period, without causing device failure. Resistance (Varistor), RX:- Static resistance of the varistor at a given operating point as defined by: RX = VX / IX

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Response Time (Varistor):- The time between the point at which the wave exceeds the clamping voltage level (VC) and the peak of the voltage overshoot. For the purpose of this definition, clamping voltage as defined with an 8/20µs current waveform of the same peak current amplitude as the waveform used for this response time. Varistor Voltage, VX:- Voltage across the varistor measured at a given current, IX. Voltage Clamping Ratio (Varistor), VC / VP:- A figure of merit measure of the varistor clamping effectiveness as defined by the symbols VC / VM(ac), VC / VM(dc). Voltage Overshoot (Varistor), Vost:- The excess voltage above the clamping voltage of the device for a given current that occurs when current waves of less than 8µs virtual front duration are applied. This value may be expressed as a % of the clamping voltage (VC) for an 8/20µs current wave.

Glossary of PTC and NTC Thermistor terminology Amorphous:- Without crystallization in the ultimate texture of a solid substance. Used to describe the device material structure in the tripped state. Breakdown voltage:- The maximum voltage that a PTC thermistor can support under stipulated time and temperature conditions. The PTC thermistor will breakdown when exceeding this voltage. Carbon Black:- A conductive material used in PTC devices to provide a path for current flow under normal operating conditions. Conductive Plastic:- A plastic material, such as a polymer, containing conductive particles, such as carbon black, that provide a path for current flow. Current-time characteristic:- The current-time characteristic is the relationship at a specified ambient temperature between the current through a thermistor and time, upon application or interruption of voltage to it. Current, Hold, Ihold:- The maximum current a PTC device can pass without interruption. Current, Maximum, Imax:- The maximum fault current a PTC device can withstand without damage at the rated voltage. Current Rating:- The nominal amperage value marked on the fuse. It is established by the manufacturer as a value of current which the fuse can be loaded to, based on a controlled set of test conditions (see Rerating). Current, Trip, Itrip:- The minimum current that will switch a device from the low resistance to the high resistance state. Curie point temperature (Resistance - temperature characteristics):- A PTC fuse maintains almost the same resistance, until certain temperature. After this temperature is exceeded, the resistance rises up sharply. This transition point is called the Curie point. The critical temperature is defined to be the Curie point temperature, where the actual resistance value is twice the reference value measured at 25°C. Derating:- Fuses are essentially temperature-sensitive devices. Even small variations from the controlled test conditions can greatly affect the predicted life of a fuse when it is loaded to its nominal value, usually expressed as 100% of rating. The fuse temperature generated by the current passing through the fuse increases or decreases with ambient temperature change. Dissipation constant:- The dissipation constant is the ratio, (W/°C) at a specified ambient temperature, of a change in power dissipation in a thermistor to the resultant body temperature change. Electrode:- A device or material that emits or controls the flow of electricity. Nickel and Copper elements are used in PTC devices to aid even distribution of current across the surface of the device. Fault Current:- The peak current that flows through a device or wire during a short circuit or arc back. Form Factor:- The package that holds the chemical make-up of polymer and carbon. PTCs are packaged in the following forms; radial, axial, surface mount chips, disks, and washers. Fuse:- A current limiting device used for protection of equipment. Typically a wire or chemical compound which breaks a circuit when the current exceeds a rated value. Fuse Resistance:- The resistance of a fuse is usually an insignificant part of the total circuit resistance. Since the resistance of fractional amperage fuses can be several ohms, this fact should be considered when using them in low-voltage circuits. Most fuses are manufactured from materials which have positive temperature coefficients, and therefore, it is common to refer to cold resistance and hot resistance (voltage drop at rated current), with actual operation being somewhere in between. The factory should be consulted if this parameter is critical to the design analysis. Resistance data on all of our fuses is available on request. Heat capacity, H:- The heat capacity of a thermistor is the amount of heat required to increase the body temperature of it by one degree centigrade, 1°C. Heat capacity is a common rating of standard PTC thermistors and is expressed in Joules per cubic centimetre per degree C (J/cm3/°C). The heat capacity per unit volume relationship of standard PTC thermistors is approximately 5 J/cm3/°C.

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Hysteresis:- The period between the actual beginning of the signalling of the device to trip and the actual tripping of the device. Initial current (Iin):- the current that results instantaneously in the circuit switch when starting to closing. Initial resistance (R25°C):- This is the part’s resistance value at 25°C which is measured under conditions of 1.0V dc or less, and 10mA or less without self-heating. Inrush current:- Inrush current is the initial surge of current that results when power is first applied to a load having a low starting impedance, such as a discharged capacitor, a cold lamp filament, or a stopped motor's winding. Inrush current limiter:- Specially designed and constructed NTC thermistors may be used as inrush current limiters. Available in a wide range of current handling and zero-power resistance value combinations. Insulation thermistor:- thermistor stipulated insulation resistance and voltage test requirement. Interrupting Rating:- Also known as breaking capacity or short circuit rating, the interrupting rating is the maximum approved current which the fuse can safely interrupt at rated voltage. During a fault or short circuit condition, a fuse may receive an instantaneous overload current many times greater than its normal operating current. Safe operation requires that the fuse remain intact (no explosion or body rupture) and clear the circuit. Leakage Current:- An undesirable small value of stray current that flows through a device after the device has changed state to a high resistance mode. Let through Current:- The amount of current though a circuit after a device is signalled to trip and the device is at full operation limiting current. Low category temperature:- Minimum ambient temperature at which a PTC thermistor can operate continuously. Material constant (Beta , ß in K):- The material constant of a NTC thermistor is a measure of its resistance at one temperature compared to its resistance at a different temperature. Its value may be calculated by the formula shown below and is expressed in degrees Kelvin (K). The reference temperatures used in this formula for determining material constant ratings of thermistors are 298.15°K and 348.15°K. Maximum Fault Current:- The Interrupting Rating of a fuse must meet or exceed the maximum fault current of the circuit. Maximum Inrush Current:- The maximum current (effective value) through the PTC thermistor under maximum rated voltage. Exceeding this current may result in PTC device damage. Maximum operating temperature:- The maximum operating temperature is the maximum body temperature at which the thermistor will operate for an extended period of time with acceptable stability of its characteristics. This temperature is the result of internal or external heating, or both, and should not exceed the maximum value specified. Maximum operating voltage, Vmax:- The maximum operating voltage is the maximum rated voltage, either direct current or 50/60 Hz rms alternating current, expressed in volts (Vdc or Vac), that a standard PTC thermistor will continuous withstand for an extended period without affecting its normal characteristics. Maximum power rating:- The maximum power rating of a thermistor is the maximum power which a thermistor will dissipate for an extended period of time with acceptable stability of its characteristics. Maximum steady-state current (Imax):- The maximum steady-state current is the rating of the maximum current, normally expressed in amperes (A), allowable to be conducted by an inrush limiting NTC thermistor for an extended period of time. Maximum surge current:- The maximum surge current is the maximum permissible surge current in a circuit and, in conjunction with the maximum peak voltage, determines the minimum required zero-power resistance of the thermistor required to limit it adequately. Minimum switching current (Is):- The minimum switching current is the minimum amount of current, normally expressed in amperes (A), that, when conducted by a standard PTC thermistor, is required to cause it to switch to its high resistance state. Negative temperature coefficient (NTC):- A NTC thermistor is one in which the zero-power resistance decreases with an increase in temperature. Non-insulation thermistor:- thermistors that do not require an insulation voltage and insulation resistance test. Non-trip Current:- Also called rated current or holding current, or non-operating current， means the current at which PTC thermistor resistance does not exceed the specified value for designated time and temperature conditions. Overload Current Condition:- The current level for which protection is required. Fault conditions may be specified, either in terms of current or, in terms of both current and maximum time the fault can be tolerated before damage occurs. Time-current curves are used to match the fuse characteristic to the circuit needs, noting that the curves are based on average data. Peak current (Iin p-p):- Peak-peak value of initial current.

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Polymer:- A synthetic plastic material consisting of large molecules made up of a linked series of repeated simple monomers. The insulating medium used in PTC devices which maintains the carbon chains in suspension during over-current while permitting the carbon chains to form during normal operation. Polymeric Positive Temperature Coefficient (PPTC):- A characteristic of PTC devices that describes a large increase in resistance as the device reaches its trip temperature. Positive temperature coefficient (PTC):- A PTC thermistor is one in which the zero-power resistance increases with an increase in temperature. Pulses:- The general term ‘pulses’ is used in this context to describe the broad category of wave shapes referred to as surge currents, start-up currents, inrush currents, and transients, Electrical pulse conditions can vary considerably from one application to another. Different fuse constructions may not all react the same to a given pulse condition. Electrical pulses produce thermal cycling and possible mechanical fatigue that could affect the life of the fuse. The start-up pulse should be defined and then compared to the time-current curve and I2t rating for the fuse. Nominal melting I2t is a measure of the energy required to melt the fusing element and is pressed as Ampere squared seconds, (A2s). Recovery time:- The recovery time of a thermistor is the approximate time required for it to cool sufficiently after power is removed and allow it to provide the characteristics required when power is reapplied. Resistance at maximum current, RImax:- The resistance at maximum current is the approximate resistance of an inrush current limiting thermistor, expressed in ohms, when it is conducting its rated maximum steady-state current. Resistance ratio characteristic:- The resistance ratio characteristic identifies the ratio of the zero-power resistance of a thermistor measured at 25°C to that resistance measured at 125°C. Resistance-temperature characteristic:- The resistance-temperature characteristic is the relationship between the zero-power resistance of a thermistor and its body temperature. Resistance, Initial (Rmin - Rmax):- The resistance range of the PTC devices, before circuit insertion. Resistance, Post Trip (R1max):- The maximum post-trip resistance one hour after a PTC device has been tripped and power has been removed. Resistance, Post Reflow (R1max):- The maximum resistance one hour after a PTC surface mount device has been reflow soldered. Restore time:- Time to restore PTC thermistor resistance to twice the zero-power resistance after the power is removed. Silicon PTC thermistor:- A silicon PTC thermistor is a type PTC thermistor that has an approximately linear resistance-temperature characteristic and a temperature coefficient of resistance of approximately +0.7%/°C. Silicon PTC thermistors are distinguished from standard PTC thermistors. Stability:- Stability of a thermistor is the ability of a thermistor to retain specified characteristics after being subjected to designated environmental or electrical test conditions. Standard PTC thermistor:- A standard PTC thermistor is a type of PTC thermistor that has a switch temperature. Standard PTC thermistors are distinguished from silicon PTC thermistors. Standard Reference Temperature:- The standard reference temperature is the thermistor body temperature at which nominal zero-power resistance is specified, 25°C. Switch Temperature:- The temperature at which the resistance value of the PTC thermistor increases to twice the zero-power resistance, also called Curie temperature, or reference temperature or transition temperature. Switching time, ts:- If Vmax and Imax are known, the PTC thermistor's switch-off behaviour can be described in terms of switching time ts. This is the time it takes at applied voltage for the current passing through the PTC to be reduced to half of its initial value, at TA = 25 °C. Temperature - wattage characteristics:- The temperature-wattage characteristic of a thermistor is the relationship at a specified ambient temperature between the thermistor temperature and the applied steady state wattage. Temperature at minimum resistance (Trmin):- Temperature corresponding to minimum resistance. Temperature coefficient of resistance, α:- The temperature coefficient of resistance is the ratio at a specified temperature, T, of the rate of change of zero-power resistance with temperature to the zero-power resistance of the thermistor. The temperature coefficient is commonly expressed in percent per degree C (%/°C). Temperature range under maximum voltage:- Operating ambient temperature range that the PTC thermistor can continuously operate under maximum voltage. Thermal cooling time constant τth:- The thermal cooling time constant refers to the time necessary for an unloaded (zero power conditions) thermistor to vary its temperature by 63.2% of the difference between its mean temperature and the ambient temperature. Equation for temperature change: T(t2) = T(t1) ± 0.632x(T(t1) - TA) with t2 - t1 = τth Thermistor:- A thermistor is a thermally sensitive resistor whose primary function is to exhibit a change in electrical resistance with a change in body temperature.

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Trip Current:- Initial current which causes PTC thermistor resistance to leap, also called operating current. Trip Endurance:- A test used to determine the duration of time a PTC device will sustain its maximum rated voltage in the tripped state without failure. Trip Cycle Life:- A test used to determine the number of trip cycles (at Vmax and Imax) a PTC device will sustain without failure. Upper category temperature:- Maximum ambient temperature at which a PTC thermistor can operate continuously. Zero-power resistance, RT:- The zero-power resistance is the dc resistance value of a thermistor measured at a specified temperature with a power dissipation by the thermistor low enough that any further decrease in power will result in not more than 0.1% (or 1/10 of the specified measurement tolerance, whichever is smaller) change in resistance. Zero-power temperature coefficient of resistance, αT:- The Zero-power temperature coefficient of resistance is the ratio at a specified temperature, T, of the rate of change of zero-power resistance with temperature to the zero-power resistance of the thermistor.

Glossary of Electrochemical Battery terminology Absorption:- The retention of Hydrogen by the Misch Metal (Hydrogen-absorbing) alloys of the negative electrode. Active Material:- Chemicals that give rise to electro-chemical reactions, and which generate electrical energy in the battery. Ageing:- Permanent loss of capacity with frequent use or the passage of time due to unwanted irreversible chemical reactions in the cell. AGM (Absorbed Glass Mat) battery:- A lead acid battery using a micro-glass mat (which also act as a separator) to promote recombination of the gases produced by the charging process. AGM (Absorbed Glass Mat):- Micro-glass material used to contain the electrolyte and also function as a separator in a valve-regulated lead acid battery. Alkaline Electrolyte:- An aqueous alkaline solution (such as potassium hydroxide) which provides a medium for the ionic conduction between the positive and negative electrodes of a cell. Ampere (A):- A unit of electrical current or rate of flow of electrons. One volt across one ohm of resistance causes a current flow of one ampere. One ampere is equal to 6.235x1018 electrons per second passing a given point in a circuit. Ampere hours (Ah):- The unit of measure used for comparing the capacity or energy content of a batteries with the same output voltage. For automotive (Lead Acid) batteries the SAE defines the Amp-hour capacity as the current delivered for a period of 20 hours until the cell voltage drops to 1.75 V. Strictly - One Ampere hour is the charge transferred by one amp flowing for one hour. 1Ah = 3600 Coulombs. One C, 1C, means Ah current for 1 hour, ½C means current of half Ah for 2 hours, etc. Ampere-Hour Capacity:- The number of ampere-hours that can be delivered by a storage battery under specified conditions as to temperature, rate of discharge and final voltage. Ampere-Hour Efficiency:- The electrochemical efficiency of a storage battery expressed as the ratio of ampere-hours output to the ampere-hours input required for recharge. Anode:- An electrode through which current enters any non-metallic conductor. The electrode in an electrochemical cell where oxidation takes place, releasing electrons. During discharge the negative electrode of the cell is the anode. During charge the situation reverses and the positive electrode of the cell is the anode. Battery:- Two or more electrochemical cells enclosed in a container and electrically inter-connected in an appropriate series/parallel arrangement to provide the required operating voltage and current levels. Under common usage, the term battery also applies to a single cell if it constitutes the entire electrochemical storage system. Battery Life:- End of Life. The period during which a cell or battery is capable of operating above a specified capacity or efficiency performance level. For example, with lead-acid batteries, end-oflife is generally taken as the point in time when a fully charged cell can deliver only 80% of its rated capacity. Beyond this state of aging, deterioration and loss of capacity begins to accelerate rapidly. Life may be measured in cycles and/or years, depending on the type of service for which the cell or battery is intended. Burning Centre:- The centre-to-centre distance between adjacent plates of the same polarity. C Rate:- The discharge or charge current in amperes, expressed in multiples of the rated capacity. For example, the C5 rate is the capacity in ampere hours available at the 5-hour discharge rate to a specified end voltage. A discharge of 0.5C5 is a discharge at 50% of the C5 rate. Cadmium Electrode:- A third electrode in lead-acid battery for separate measurements of the electrode potential of positive and negative plate groups.

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Capacity:- The amount of electrical energy that can be supplied by a cell/battery - expressed in Ah, and in specified discharge conditions. Capacity Test:- A test that discharges the battery at constant current at room temperature to a cutoff voltage of usually 1.75V/cell in the case of a lead-acid battery. Cathode:- An electrode through which current leaves any non-metallic conductor. The electrode in an electrochemical cell where reduction takes place, gaining electrons. During discharge the positive electrode of the cell is the cathode. During charge the situation reverses and the negative electrode of the cell is the cathode. Cell (Primary):- A cell designed to produce electric current through an electrochemical reaction that is not efficiently reversible and hence the cell, when discharged, cannot be efficiently recharged by an electric current. Cell (Storage):- An electrolytic cell for generation of electric energy, in which the cell after discharge may be restored to a charged condition by an electric current flowing in a direction opposite to the flow of current when the cell discharges. Cell reversal:- A condition which may occur multi cell series chains in which an over discharge of the battery can cause one or more cells to become completely discharged. The subsequent volt drop across the discharged cell effectively reverses its normal polarity. Charge acceptance:- quantifies the amount of electric charge which accumulates in a battery. Charge Efficiency:- The ratio of the output of a cell during discharge to the input of a cell during charge. This ratio can be expressed in Efficiency of Capacity, Nominal Voltage, or Power. Charge:- The operation which inputs electrical energy to a cell/battery. Charge equalization:- brings all of the cells in a battery or string to the same state of charge. Charge Rate:- The current applied to a cell to restore its capacity. The charge rate is usually expressed in terms of the cells C Rate. Charge retention:- refers to a battery’s ability to hold a charge. It diminishes during storage. Charged and Dry:- A battery assembled with dry, charged plates and no electrolyte. Charged and Wet:- A fully charged battery containing electrolyte and ready to deliver current. Charge, state of:- Available or remaining capacity of a battery expressed as a % of the rated capacity. Cold Cranking Amps:-A performance rating for automobile starting batteries. It is defined as the current that the battery can deliver for 30 seconds and maintain a terminal voltage greater than or equal to 1.20 volts per cell, at -18°C, when the battery is new and fully charged. Starting batteries may also be rated for Cranking Amps, which is the same thing but at a temperature of 0°C. Constant Current Charge:- A charge that maintains the current at a constant value. For some types of batteries this may involve two rates, called a starting and a finishing rate. This procedure may damage the battery if performed on a repetitive basis. Constant Potential Charge or Constant Voltage Charge:- A charge that holds the voltage at the terminals at a constant value and the current is limited only by the resistance of the battery and/or the capacity of the charge source. Copper Contamination:- The formation of copper sulphate on the negative plates, usually caused by unintentional exposure of terminal posts' copper inserts to the electrolyte. Coulombic Efficiency:- The ratio (expressed as a percentage) between the energy removed from a battery during discharge compared with the energy used during charging to restore the original capacity. Also called Charge Efficiency or Charge Acceptance. Coup-de-Fouet:- The voltage dip followed by a subsequent voltage recovery that occurs when initially discharging a battery that has been on long-term float operation. Cut-off Voltage:- A set voltage that determines when the discharging of a cell/battery should end. Cycle:- A discharge and its subsequent recharge. Cycle Life:- The total number of charge/discharge cycles before the battery reaches end of life (generally 80% of rated capacity). Deep cycle battery - A battery designed to be discharged to below 80% Depth of Discharge. Used in marine, traction and EV applications. Deep discharge - Discharge of at least 80% of the rated capacity of a battery. Dendritic growth:- The formation from small crystals in the electrolyte of tree like structures which degrade the performance of the cell. Depth of discharge DOD:- The ratio of the quantity of electricity or charge removed from a cell on discharge to its rated capacity discharge, expressed as a percent of rated capacity. For example, the removal of 25 ampere-hours from a fully charged 100 ampere-hours rated cell results in a 25% depth of discharge. Under certain conditions, such as discharge rates lower than that used to rate the cell, depth of discharge can exceed 100%. Discharged:- A storage cell when, as a result of delivering current, in the case of the lead-acid cell, the plates are sulphated, the electrolyte is exhausted, and there is little or no potential difference between the terminals. Discharge Factor:- A number equivalent to the time in hours during which a battery is discharged at constant current usually expressed as a percentage of the total battery capacity, i.e., C/5 indicates a discharge factor of 5 hours. Related to discharge rate.

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Discharge Rate:- Any specified amperage rate at which a battery is discharged. Efficiency:- The ratio of the output of a rechargeable cell or battery on discharge to the input required to restore it to the initial state of charge. Electrochemical Cell:- A device containing two conducting electrodes, one positive and the other negative, made of dissimilar materials (usually metals) that are immersed in a chemical solution (electrolyte) that transmits positive ions from the negative to the positive electrode and thus forms an electrical charge. One or more cells constitute a battery. Electrode:- Positive or negative plate containing materials capable of reacting with electrolyte to produce or accept current. Electrode (Electrolyte) potential:- The voltage developed by a single electrode, determined by its propensity to gain or lose electrons. The difference in potential between the electrode and the immediately adjacent electrolyte, expressed in terms of a standard electrode potential difference. Electrolysis:- Electrochemical reaction that causes the decomposition of a compound. Electrolyte:- A substance which dissociates into ions (charged particles) when in aqueous solution or molten form and is thus able to conduct electricity. It is the medium which transports the ions carrying the charge between the electrodes during the electrochemical reaction in a battery. End Gravity:- The specific gravity of a lead-acid cell at the end of a prescribed discharge. Energy density:- The amount of energy stored in a battery. It is expressed as the amount of energy stored per unit volume or per unit weight (Wh/L or Wh/kg). Equalisation:- The process of bringing every cell in a battery chain to the same state of charge (SOC) Equalizing charge:- Charge applied to a battery which is greater than the normal float charge and is used to completely restore the active materials in the cell, bringing the cell float voltage and the specific gravity of the individual cells back to ‘equal’ values. Fauré Plate:- see Pasted Plate. Final Voltage:- The cut-off voltage of a battery. The prescribed voltage reached when the discharge is considered complete. Also known as end point voltage or EPV. This voltage is almost equivalent to limit of practical use. Typical values: 1.0 V per cell for NiCd and NiMH 1.75 V per cell for sealed lead acid 2.75 V per cell for lithium ion and lithium polymer 2.0 V per cell for primary lithium 0.9 V per cell for alkaline and carbon zinc Finishing Rate:- The rate of charge, in amperes, to which charging current is reduced near the end of the charge for some types of batteries to prevent gassing and temperature rise. Float Plate:- A pasted plate. Float Charging:- A recharge at a very low rate, accomplished by connection to a bus whose voltage is slightly higher than the open circuit voltage of the battery. A method of maintaining a battery in a charged condition by continuous, long term, constant voltage charging at level sufficient to balance self-discharge. Flooded Lead Acid cell:- In ‘flooded’ batteries, the oxygen created at the positive electrode is released from the cell and vented into the atmosphere. Similarly, the hydrogen created at the negative electrode is also vented into the atmosphere. This can cause an explosive atmosphere in an unventilated battery room. Furthermore the venting of the gasses causes a net loss of water from the cell. This lost water needs to be periodically replaced. Flooded batteries must be vented to prevent excess pressure from the build up of these gasses. Sealed Lead Acid (SLA) and Valve Regulated Lead Acid (VRLA) Cells overcome these problems. Fuel Cell:- An electrochemical generator in which the reactants are stored externally and may be supplied continuously to a cell. Gas Recombination:- The process by which oxygen gas generated from the positive plate during the final stage of charge is absorbed into the negative plate, preventing loss of water. Gassing:- The generation or evolution of a gaseous product at one or both electrodes as a result of the electrochemical action. Gassing commonly results from local action (self discharge) or from the electrolysis of water in the electrolyte during charging. In lead acid batteries gassing produces hydrogen and oxygen. Significant gassing occurs when the battery is nearing the fully charged state while recharging or when the battery is on equalizing charge. Gel cell:- An SLA battery which uses gelled electrolyte, an aqueous electrolyte that has been immobilised by the addition of a gelling agent. Grid:- A metallic framework used in a battery for conducting electric current and supporting the active material. Half Cell Reaction:- The electrochemical reaction between the electrode and the electrolyte. Hydration (Lead):- Reaction between water and lead or lead compounds. Gravities lower than those found in discharged cells are apt to produce hydration, which appears as a white coating on plate groups and separators in a cell. A condition whereby lead dissolves into the electrolyte in a discharged cell and plates out onto the separator during recharge, resulting in numerous short circuit paths between the positive and negative plates.

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Hydrometer:- A tool for testing the specific-gravity of a fluid, such as the electrolyte in a flooded battery. Typically a squeeze-bulb is used to suck up a sample of the fluid, and a float indicates the specific gravity. Immobilized Electrolyte:- A lead-acid batteries technique where the electrolyte (the acid) is held in place against the plates instead of being a free-flowing liquid. The two most common techniques are gel and glass mat. Impedance:- The resistive value of a battery to an AC current expressed in ohms (W). Generally measured when fully charged, at 1000 Hz. Intercalation:- This insertion of ions into the crystalline lattice of a host electrode without changing its crystal structure. A reaction where lithium Ions are reversibly removed or inserted into a host without a significant structural change to the host. Internal Pressure:- The pressure within a sealed cell caused by oxygen or hydrogen evolution. Internal Resistance:- The opposition or resistance to the flow of a direct electric current within a cell or battery; the sum of the ionic and electronic resistance of the cell components. Its value varies with the current, state of charge, temperature, and age. With an extremely heavy load, such as an engine starter, the cell voltage may drop significantly. This voltage drop is due to the internal resistance of the cell. A cell that is partly discharged has a higher internal resistance than a fully charged cell, hence it will have a greater voltage drop under the same load. This change in internal resistance is due to the accumulation of lead sulphate in the plates. Interstitial:- A space between things closely set, or between the parts, which compose a body; a narrow chink; a crack; a crevice; a hole. Lithium Cobaltite:- (LiCoO2) Dark blue powder; insoluble in water. The compound exhibits both the fluxing property of lithium oxide and the adherence-promoting property of cobalt oxide. Intercalates lithium ions in battery applications. Manchex:- A type of Planté cell in which the positive plate is cast with openings provided for the active material, which are buttons of soft-lead ribbon. The active material is corrugated and rolled into spirals, which are forced into the grids by hydraulic pressure. Memory effect (Voltage Depression):- Reversible, progressive capacity loss in nickel based batteries found in NiCad and to a lesser extent in NiMH batteries. It is caused by a change in crystalline formation from the desirable small size to a large size which occurs when the cell is repeatedly recharged before it is fully discharged. Metal Hydride (MH):- The negative electrode composed of Misch metal (Hydrogen-storing) alloys. MF (Maintenance Free Battery):- A VRLA sealed absorbed glass mat (AGM) battery. Microporous Separator:- A veneer or grooved-type separator made of any material that has many microscopically small pores. Migration:- The movement of charged ions under the influence of a potential gradient. Misch Metal (M):- The matrix of the negative electrode composed of Hydrogen-storing alloys. Nickel Metal Hydride (NiMH): A cell or battery system composed of a Nickel (Ni) positive electrode and a metal hydride (MH) negative electrode. Negative Plate:- The grid and active material that current flows to from the external circuit when a battery is discharging. Negative Terminal:- The terminal from which current flows through the external circuit to the positive terminal when the cell discharges. Nernst equation:- Used by cell designers to calculate the voltage of a chemical cell from the standard electrode potentials, the temperature and to the concentrations of the reactants and products. Nominal Voltage:- A general value to indicate the voltage of a battery in application. Open Circuit Voltage:- The voltage of a battery when it is not delivering or receiving power, and has been at rest long enough to reach a steady state (normally, at least 4 hours). Overcharge:- The forcing of current through a cell after all the active material has been converted to the charged state. In other words, charging continued after 100% state of charge is achieved. The result will be the decomposition of water in the electrolyte into hydrogen and oxygen gas, heat generation, and corrosion of the positive electrode. Oxygen Recombination:- The process in which oxygen generated at the positive electrode during overcharge reacts with hydrogen at the negative electrode to produce water. Pasted (Fauré) Plate:- A plate consisting of a grid filled with active material applied as a paste. Peukert's equation:- A formula that shows how the available capacity of a lead-acid battery changes according to the rate of discharge. The capacity of a battery is expressed in Amp-Hours, but it turns out that the simple formula of current times hours does not accurately represent the situation. Peukert found that the equation: C = I n×t fits the observed behaviour of batteries. ‘C’ is the theoretical capacity of the battery, I is the current, t is time, and n is the Peukert number, a constant for the given battery. The equation captures the fact that at higher currents, there is less available energy in the battery. Peukert number:- A value that indicates how well a lead-acid battery performs under heavy currents. The Peukert number is the exponent in Peukert's equation. A value close to 1 indicates that the

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battery performs well; the higher the number, the more capacity is lost when the battery is discharged at high currents. The Peukert number of a battery is determined empirically. Planté Plate:- A formed lead plate of large area, the active material of which is formed directly from a lead substrate. Polarization:- Change in voltage at terminals when a specified current is flowing; equal to the difference between the actual and the equilibrium (constant open circuit condition) potentials of the plates, exclusive of the internal resistance drop. Positive Plates:- The grid and active materials of a storage battery from which current flows to the external circuit when the battery is discharging. Positive Terminal:- The terminal that current flows toward in the external circuit from the negative terminal. Potassium Hydroxide (KOH):- The electrolyte provides the ion transport mechanism between the electrodes, used in NiMH cells. Primary cell:- A cell that is non-rechargeable. A cell or battery that can be discharged only once. Prismatic cell:- A slim rectangular sealed cell in a metal case. The positive and negative plates are stacked usually in a rectangular shape rather than rolled in a spiral as done in a cylindrical cell. Rapid Charge:- A rate of charging a cell or battery that results in fully charging a battery to full capacity between 2½ to 6 hours. Rated Capacity:- Ampere hours of discharge that can be removed from a fully charged cell or battery, at a specific constant discharge rate at a specified temperature and at a specified cut-off voltage. Recombinant system:- Sealed secondary cells in which gaseous products of the electrochemical charging cycle are made to recombine to recover the active chemicals. A closed cycle system preventing loss of active chemicals. Used in NiCd and SLA batteries. Resealable Safety Vent:- The resealable vent built into cylindrical and prismatic cells to prevent the build up of high internal pressures. Reversal:- A change in the normal polarity of a cell or battery. Safety Vent:- This is a device to release the gas when the internal pressure of the battery exceeds the pre-set value. Sealed cells:- A cell which remains closed and does not release gas or liquid when operated within the limits of charge and temperature specified by the manufacturer. An essential component in recombinant cells. Secondary cell:-– the process is reversible so that charging and discharging may be repeated over and over. Sediment:- The sludge or active material shed from plates that drops to the bottom of cells. Sediment Space:- The portion of a container beneath the element; sediment from the wearing of the plates collects here without short-circuiting. Self-discharge:- Loss of charge due to local action, without external current flow. The decrease in the state of charge of a cell or a battery, over a period of time during storage or not in use, due to internal electrochemical losses. Typical values: 1% per day for NiCd 2% per day for NiMH ~0% per day for Lithium Ion and Lithium Polymer Self Discharge Rate:- the percent of capacity lost on open circuit over a specified period of time. Separator:- A device in a storage battery that prevents metallic contact between plates of opposite polarity in a cell. In sealed lead acid batteries it normally is absorbent glass fibre to hold the electrolyte in suspension. Shelf Life:- The duration under specified conditions that at the end a cell or battery can be stored and retain its performance. SLA Battery:- Sealed Lead Acid battery. In sealed batteries the generated oxygen combines chemically with the lead and then the hydrogen at the negative electrode, and then again with reactive agents in the electrolyte, to recreate water. A recombinant system. The net result is no significant loss of water from the cell. Spalling:- Shedding of active material, usually from positives, during formation due to incomplete or improper plate curing. Sponge Lead (Pb):- A porous mass of lead crystals and the chief material of a full-charged negative plate. Standby Service:- An application in which the battery is maintained in a fully charged condition by trickle of float charging. State of Charge:- The amount of electrochemical energy left in a cell or battery. The available ampere hours in a battery at any given time relative to its full charge capacity. Starved Electrolyte:- A term occasionally applied to a VRLA cell, meaning that the cell contains little or no free electrolyte. Sulphation:- Growth of lead sulphate crystals in Lead-Acid batteries which inhibits current flow. Refers to the formation of hard lead sulphate crystals in the plates that are difficult, if not impossible, to reconvert to active material. Sulphation is caused by storage at low state of charge.

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Stratification:- Layering of high specific gravity electrolyte in lower portions of a cell, where it does not circulate normally and is of no use. Temperature Correction:- In storage cells, specific gravity and charging voltage vary inversely with temperature, while the open circuit voltage varies directly though slightly with temperature. Thermal Runaway:- A condition in which a cell or battery (especially valve-regulated types) on constant potential charge can destroy itself through internal heat generation being greater than that which can be externally dissipated. Can cause failure through cell dry-out, shortened life, and/or melting of the battery. Treeing:- Growth of a lead dendrite or filament through a crack or hole of a separator, short-circuiting the cell. Trickle Charge:- A low-rate continuous charge approximately equal to a battery’s internal losses and capable of maintaining the battery in a fully-charged state. Method of charging in which the battery is either continuously or intermittently connected to a constant current charging source to maintain the battery in a fully charged condition. Not recommended for use with AGM batteries. Tubular Plate:- A plate in which the active material is contained in porous tubes, each tube having a centrally located grid. Vent:- An opening that permits the escape of gas from a cell or mould. Venting:- A release of gas either controlled (through a vent) or accidental from a battery cell. Vent Valve:- A normally closed check valve located in a cell which allows the controlled escape of gases when the internal pressure exceeds its rated value. Volt Efficiency:- The ratio of the average voltage of a cell or battery during discharge to the average voltage during subsequent recharge. VRLA (Valve Regulated Lead Acid):- Sealed batteries which feature a safety valve venting system designed to release excessive internal pressure, while maintaining sufficient pressure for recombination of oxygen and hydrogen into water. Watthour:- A unit of electrical energy or work, equal to one watt acting for one hour. Watthour Capacity:- The number of watthours a storage battery can deliver under specific conditions of temperature, rate of discharge and final voltage. Watthour Efficiency:- A storage battery’s energy efficiency expressed as ratio of watthour output to the watthours of the recharge. Wet Shelf Life:- The time a wet secondary cell can be stored before its capacity falls to the point that the cell cannot be easily recharged.

Glossary of Fuel Cell terminology Alkali:- A chemical base produces negative ions, the opposite of an acid. Certain types of alkalis (especially potassium hydroxide) are used as fuel cell electrolytes. Alkaline Fuel Cell (AFC):- A type of hydrogen/oxygen fuel cell in which the electrolyte is concentrated KOH (varies between 35 to 85 wt% depending on the intended operating temperature) and hydroxide ions(OH-) are transported from the cathode to the anode. Temperature of operation can vary from

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