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Biopotential Readout Circuits for Portable Acquisition Systems

ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES Consulting Editor: Mohammed Ismail. Ohio State University Titles in Series: OMNIDIRECTIONAL INDUCTIVE POWERING FOR BIOMEDICAL IMPLANTS Lenaerts, Bert, Puers, Robert ISBN: 978-1-4020-9074-5 BIOPOTENTIAL READOUT CIRCUITS FOR PORTABLE ACQUISITION SYSTEMS Yazicioglu, Refet Firat, Van Hoof, Chris, Puers, Robert ISBN: 978-1-4020-9092-9 STRUCTURED ANALOG CMOS DESIGN Stefanovic, Danica, Kayal, Maher ISBN: 978-1-4020-8572-7 LOW POWER UWB CMOS RADAR SENSORS Paulino, Nuno, Goes, João, Steiger Garção, Adolfo ISBN: 978-1-4020-8409-6 ANALYSIS AND DESIGN OF QUADRATURE OSCILLATORS Oliveira, L.B., Fernandes, J.R., Filanovsky, I.M., Verhoeven, C.J.M., Silva, M.M. ISBN: 978-1-4020-8515-4 THE GM/ID DESIGN METHODOLOGY FOR CMOS ANALOG LOW POWER INTEGRATED CIRCUITS Jespers, Paul G.A. ISBN-10: 0-387-47100-6 LOW-POWER HIGH-SPEED ADCS FOR NANOMETER CMOS INTEGRATION Cao, Zhiheng, Yan, Shouli ISBN: 978-1-4020-8449-2 SUBSTRATE NOISE COUPLING IN RFICS Helmy, Ahmed, Ismail, Mohammed ISBN: 978-1-4020-8165-1 CIRCUIT AND INTERCONNECT DESIGN FOR HIGH BIT-RATE APPLICATIONS Veenstra, Hugo, Long, John R. ISBN: 978-1-4020-6882-9 HIGH-RESOLUTION IF-TO-BASEBAND SIGMADELTA ADC FOR CAR RADIOS Silva, Paulo G.R., Huijsing, Johan H. ISBN: 978-1-4020-8163-7 MULTI-BAND RF FRONT-ENDS WITH ADAPTIVE IMAGE REJECTION A DECT/BLUETOOTH CASE STUDY Vidojkovic, V., van der Tang, J., Leeuwenburgh, A., van Roermund, A.H.M. ISBN: 978-1-4020-6533-0 SILICON-BASED RF FRONT-ENDS FOR ULTRA WIDEBAND RADIOS Safarian, Aminghasem, Heydari, Payam ISBN: 978-1-4020-6721-1 DESIGN OF HIGH VOLTAGE XDSL LINE DRIVERS IN STANDARD CMOS Serneels, Bert, Steyaert, Michiel ISBN: 978-1-4020-6789-1 HIGH-LEVEL MODELING AND SYNTHESIS OF ANALOG INTEGRATED SYSTEMS Martens, Ewout S.J., Gielen, Georges ISBN: 978-1-4020-6801-0 BASEBAND ANALOG CIRCUITS FOR SOFTWARE DEFINED RADIO Giannini, Vito, Craninckx, Jan, Baschirotto, Andrea ISBN: 978-1-4020-6537-8 CMOS MULTI-CHANNEL SINGLE-CHIP RECEIVERS FOR MULTI-GIGABIT OPT... Muller, P., Leblebici, Y. ISBN 978-1-4020-5911-7 ANALOG-BASEBAND ARCHITECTURES AND CIRCUITS FOR MULTISTANDARD AND LOW-VOLTAGE WIRELESS TRANSCEIVERS Mak, Pui In, U, Seng-Pan, Martins, Rui Paulo ISBN: 978-1-4020-6432-6 FULL-CHIP NANOMETER ROUTING TECHNIQUES Ho, Tsung-Yi, Chang, Yao-Wen, Chen, Sao-Jie ISBN: 978-1-4020-6194-3

Refet Fırat Yazıcıo˘glu Chris Van Hoof Robert Puers •

•

Biopotential Readout Circuits for Portable Acquisition Systems

Dr. Refet Fırat Yazıcıo˘glu Katholieke Universiteit Leuven Interuniversity Microelectronics Center (IMEC) Kapeldreef 75 3001 Leuven Heverlee Belgium Email: [email protected]

Prof. Dr. Robert Puers Katholieke Universiteit Leuven Dept. Electrical Engineering (ESAT) Kasteelpark Arenberg 10 3001 Leuven Belgium Email: [email protected]

Prof. Dr. Chris Van Hoof Katholieke Universiteit Leuven Interuniversity Microelectronics Center (IMEC) Kapeldreef 75 3001 Leuven Heverlee Belgium Email: [email protected]

ISBN 978-1-4020-9092-9 e-ISBN 978-1-4020-9093-6 Library of Congress Control Number: 2008934402 All Rights Reserved © 2009 Springer Science + Business Media B.V. No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Printed on acid-free paper 9 8 7 6 5 4 3 2 1 springer.com

To my parents and sister, Hüseyin, Betil, and Gözde Yazıcıo˘glu; and to my wife, Begüm Yazıcıo˘glu

Acknowledgements

Before the start of this text I would like to express my sincere gratitude to friends, colleagues, and family. First of all, I would like to express my appreciation and thanks to my supervisors Prof. Chris Van Hoof and Prof. Robert Puers for their valuable guidance, support and comments. I would like to thank my M.S. thesis supervisor Prof. Tayfun Akin and METUMEMS group members. Prof. Akin is actually the person, who has introduced me to microelectronics and circuit design. I would like to thank the members of ULPEXEL team of IMEC vzw, Belgium. To start with, many thanks goes to Prof. Patrick Merken for the valuable discussions and guidance and also for turning the office environment into a fun place. I would like to thank Tom Torfs for his helps during the testing of the ASICs and discussions we had about the system implementations. He has written lots of test softwares for me. I would like to thank Jan Putzeys for helping me during the usage of the instruments in his lab. Many thanks also go to Munir Abdalla, Ybe Creten, Inge Doms, Burak Okcan, Junaid Aslam, and Tim Souverijns for the enjoyable office and research environment that they have created at IMEC. I also would like to thank many past and present colleagues. Just a few to name: Mehmet Akif Erismis, Deniz Sabuncuoglu, Didem Ernur, Mustafa Badaroglu, Kris Verheyen, Koen De Munck, Caroline Geuens, Hercules Pereira Neves, Christophe Winters, Xavier Rottenberg, Kuba Raczkowski, Tom Sterken, Fre Vanaverbeke, and Vladimir Leonov. I am grateful to IMEC and the Katholieke Universiteit Leuven (K.U. Leuven). Both IMEC and K.U. Leuven provide me the necessary means to conduct my Ph.D. research in an excellent environment. I am also grateful to the employees of INVOMEC department, Steve Mattheus, Greta Milzanowski, Marc Van Eylen, and Kurt Van Genechten, for their patience to my endless questions and for their help with all my software and tape-out related problems. I would like to thank my dear friends, Arda, Sencer, and Emrah for the fun we had for all those years. Other friends to mention are Rana, Ozlem, and Onur. I also would like to express my sincere greetings to my cousin and her husband, Tugba and Fatih Vardareli. I would like to open a special paragraph for my parents and my sister. Without their unlimited love and support, it would not be possible to overcome the tough challenges of Ph.D. research and living abroad. I am grateful to them and my love for them is endless. I also would like to thank my aunt, Yildiz Sakin, and my grandfather, Hilmi Gozen, who are as close as a mother and a father to me. When it comes to thank my wife, Begum Yuksel, words are just not enough. I am grateful for her patience and support for me. Leuven, Belgium

Refet Fırat Yazıcıo˘glu July 2008 vii

Contents

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Introduction . . . . . . . . . . . . . . 1.1 Ambulatory Health Care Systems 1.2 Body Area Networks . . . . . . . 1.3 Scope of the Book . . . . . . . .

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Introduction to Biopotential Acquisition . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Introduction to Biopotential Signals . . . . . . . . . . . . . . . . 2.3 Introduction to Biopotential Electrodes . . . . . . . . . . . . . . 2.3.1 Equivalent Circuit Model . . . . . . . . . . . . . . . . . 2.3.2 Types of Biopotential Electrodes . . . . . . . . . . . . . 2.4 Introduction to Biopotential Amplifiers . . . . . . . . . . . . . . 2.4.1 Interference Theory . . . . . . . . . . . . . . . . . . . . 2.4.2 Noise-Efficiency Factor (NEF) of Biopotential Amplifiers 2.4.3 State-of-the-Art in Instrumentation Amplifier Design . . 2.5 Introduction to Chopper Modulation Technique . . . . . . . . . . 2.5.1 Noise Analysis of Chopper Modulation Technique . . . . 2.5.2 Charge Injection and Residual Offset of Chopper Modulated Amplifiers . . . . . . . . . . . . . . . . . . . 2.5.3 Signal Distortion in Chopper Modulated Amplifiers . . . 2.5.4 CMRR of the Chopper Modulated Amplifiers . . . . . . 2.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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24-Channel EEG Readout Front-End ASIC . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 ASIC Architecture . . . . . . . . . . . . . . . . . . . . . . . 3.3 Current Balancing IA . . . . . . . . . . . . . . . . . . . . . 3.3.1 Implementation . . . . . . . . . . . . . . . . . . . . 3.3.2 Measurement of Performance . . . . . . . . . . . . . 3.4 CMRR Model for Biopotential Instrumentation Amplifiers . . 3.4.1 Systematic CMRR . . . . . . . . . . . . . . . . . . . 3.4.2 CMRR Limit Due to Differential DC Electrode Offset 3.4.3 Verification of the CMRR Model . . . . . . . . . . . 3.5 Programmable Gain Stage . . . . . . . . . . . . . . . . . . . 3.5.1 Finite-Gain Compensated SC Amplifier . . . . . . . . 3.5.2 Programmable Gain Stage Implementation . . . . . . 3.6 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . .

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Biopotential Readout Front-End ASICs . . . . . . 4.1 Introduction . . . . . . . . . . . . . . . . . . . 4.2 AC Coupled Chopper Modulated IA (ACCIA) . 4.2.1 Architecture of the ACCIA . . . . . . . 4.2.2 Architecture of the CBIA . . . . . . . . 4.2.3 Power-Noise Performance of the ACCIA 4.3 Chopping Spike Filter (CSF) . . . . . . . . . . 4.4 Low-Power Programmable Gain Stage . . . . . 4.5 Single-Channel ExG Readout Front-End . . . . 4.5.1 Implementation . . . . . . . . . . . . . 4.5.2 Measurement of Performance . . . . . . 4.5.3 Biological Test Results . . . . . . . . . 4.6 Eight-Channel EEG Readout Front-End . . . . . 4.6.1 Implementation . . . . . . . . . . . . . 4.6.2 Measurement of Performance . . . . . . 4.6.3 Biological Test Results . . . . . . . . . 4.7 Comparison with the State-of-the-Art . . . . . . 4.8 Conclusions . . . . . . . . . . . . . . . . . . .

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A Complete Biopotential Acquisition ASIC . . . . . 5.1 Introduction . . . . . . . . . . . . . . . . . . . . 5.2 ASIC Architecture . . . . . . . . . . . . . . . . . 5.3 Bias Generator Circuit . . . . . . . . . . . . . . . 5.4 Class-AB Buffer Architecture . . . . . . . . . . . 5.5 ACCIA with Coarse-Fine Servo-Loop . . . . . . . 5.5.1 Structure of the ACCIA . . . . . . . . . . 5.5.2 Coarse Transconductance (CGM) Stage . . 5.5.3 Fine Transconductance (FGM) Stage . . . 5.5.4 Integrator Stage . . . . . . . . . . . . . . 5.5.5 Current Balancing IA (CBIA) Architecture 5.5.6 Gain Stage . . . . . . . . . . . . . . . . . 5.5.7 Implementation of the ACCIA . . . . . . 5.5.8 Fast Start-Up of the ACCIA . . . . . . . . 5.5.9 Power-Noise Performance of the ACCIA . 5.5.10 Measurement of Performance . . . . . . . 5.5.11 Comparison with State-of-the-Art . . . . . 5.6 Chopping Spike Filter . . . . . . . . . . . . . . . 5.7 Low-Power Programmable Gain Stage . . . . . . 5.8 Readout Front-End Channel Test Results . . . . . 5.9 Square Wave Relaxation Oscillator . . . . . . . . 5.10 Analog-to-Digital Converter . . . . . . . . . . . . 5.10.1 Basic Operation Principle . . . . . . . . . 5.10.2 Architecture . . . . . . . . . . . . . . . . 5.10.3 Capacitive DAC Implementation . . . . . 5.10.4 Low-Offset Comparator Implementation .

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Wireless Biopotential Acquisition Systems . . . . . . . . . . . 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 A Wireless VEMP Acquisition System . . . . . . . . . . . 6.3 A Wireless Two-Channel ExG Acquisition System . . . . . 6.4 A 1 cm3 Wireless Eight-Channel EEG Acquisition System . 6.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . .

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Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 7.1 Achievements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 7.2 Suggestions for Future Work . . . . . . . . . . . . . . . . . . . . 149

5.11 5.12 5.13 5.14

5.10.5 Test Results . . . . . . . . . . . . . . . Impedance Measurement and Calibration Modes Biological Test Results . . . . . . . . . . . . . Summary of the Biopotential Acquisition ASIC Conclusions . . . . . . . . . . . . . . . . . . .

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Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Symbols and Abbreviations

Symbols ACM Av BW Cbg Cbp Ciso Cin Cox Eg fc fc,1/f fchop fCSF fLP,IA gds gm go ID Ids Itot k KF F μp n q Rds Rel Rs S0 T VCM Velec-off ,max Vgs Vin,rms Vsg Vsd Vt

Common-mode gain of an amplifier Open-loop gain of an amplifier −3 dB bandwidth of an amplifier (Hz) Coupling capacitor between body and earth ground Coupling capacitor between body and mains Isolation capacitance between earth ground and battery Input capacitance Gate-oxide capacitance per unit area (F/cm2 ) Bandgap energy of silicon (≈1.12 eV) Low-pass cut-off frequency of an amplifier Corner frequency of the 1/f noise Chopping clock frequency Operating frequency of the CSF stage Low-pass cut-off frequency of the IA Output transconductance of a MOS transistor Transconductance of a MOS transistor Output transconductance of a current source Displacement current through human body Drain current of a MOS transistor Total supply current Boltzmann constant = 1.3806 × 10–23 m2 kg/s2 1/f noise constant of a MOS transistor (C2 /cm2 ) Mobility of pMOS transistors Weak inversion slope factor (= 1.45 in AMIS 0.5 µm technology) Unit charge = 1.6 × 10–19 C Drain-to-source resistance of a MOS transistor Electrode impedance Source resistance Thermal noise level of an amplifier Absolute temperature in Kelvin Common-mode voltage on the human body Maximum differential DC electrode offset voltage that can be filtered by ACCIA Gate-to-source voltage of a nMOS transistor Input-referred total RMS voltage noise Source-to-gate voltage of a pMOS transistor Source-to-drain voltage of a pMOS transistor Thermal voltage kT /q xiii

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Abbreviations ACM ACCIA ADC ADM CMFB CBIA CMRR CMRReq CMRRgds CMRRgo CMRRsys CMOS CGM CSF DAC DSP ECG EEG EMG EOG FGM HPF IA LPF NEF nMOS OTA pMOS PSG PSD RGC RMS S&H SAR SC SFDR SNDR SPI SPL STFT T&H TC THD

Common-mode gain of an amplifier AC Coupled Chopper Modulated Instrumentation Amplifier Analog-to-Digital Converter Differential-mode gain of an amplifier Common Mode Feedback Current Balancing (or Feedback) IA Common Mode Rejection Ratio Equivalent CMRR including all the limiting mechanisms CMRR limit due to gds mismatch of the input pair transistors CMRR limit due to go mismatch of current sources Systematic CMRR Complementary Metal Oxide Semiconductor Coarse Transconductance Chopping Spike Filter Digital-to-Analog Converter Digital Signal Processing Electrocardiogram Electroencephalogram Electromyogram Electrooculogram Fine Transconductance High-Pass Filter Instrumentation Amplifier Low-Pass Filter Noise-Efficiency Factor n-Channel Metal Oxide Semiconductor Operational Transconductance Amplifier p-Channel Metal Oxide Semiconductor Polysomnography Power Spectral Density Regulated Cascode Current Mirror Root-Mean-Square Sample-and-Hold Successive Approximation Switched-Capacitor Spurious Dynamic Range Signal-to-Noise Dynamic Range Serial Peripheral Interface Sound Pressure Level Short-Time Fourier Transform Track-and-Hold Temperature Coefficient Total Harmonic Distortion


VEMP VGA WHO WLAN

Vestibular Evoked Myogenic Potential Variable Gain Amplifier World Health Organization Wireless Local Area Network

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Chapter 1

Introduction

1.1 Ambulatory Health Care Systems Experts indicate that as many as 98,000 people die only in US each year at hospitals as a result of medical errors, such as diagnostics and treatment that could have been prevented. This is more than die from motor vehicle accidents, breast cancer, or AIDS. Therefore, the cost of faulty medical errors is actually higher than some causes that receive far more public attention. Interestingly, these medical errors are more commonly caused by faulty systems and conditions that lead people to make mistakes other than the people themselves [1]. A typical example for a faulty diagnostics can be the diagnosis of the epilepsy seizures that requires continuous monitoring of the patient at the hospital, which is a costly endeavor. Since it removes the patient from his or her routine, the diagnostics can be affected. A possible solution to this problem is the ambulatory monitoring of the patients. This can not only enable the patient to live his or her routine and improve the diagnostics, but also can reduce the medical cost [2]. However, the ambulatory monitoring of the patients’ requires an adequate technology platform for the support of the patient. The e-Health project, “The use, in the health sector, of digital data—transmitted, stored and retrieved electronically—in support of health care, both at the local site and at a distance.” as defined by WHO, can be the platform for the support and the diagnostics of the patients. E-health is claimed to offer the potential to reduce the medical cost, enable personalized health care, deliver remote health services, and increase the delivery efficiency in real-time. Therefore, the gathering of fast and reliable medical information from the patient lies in the center of the e-Health project, which can be achieved through implementation of biomedical sensors in Body Area Networks (BAN).

1.2 Body Area Networks Body Area Network [3] is a composition of miniaturized sensors and actuators that are attached to the human body, and capable of communicating with each other and/or with a central node worn on the body, Fig. 1.1 [4]. Each sensor node carries its own power source, and implements enough intelligence for standalone operation. The central node communicates with the outside world using a standard telecommunication infrastructure, such as WLAN or a cellular phone network, so that a medical personal can diagnose the results. Further improvement of the BAN system can add more intelligence to the nodes for the treatment of diseases and drug delivery. However, the realization of the BAN requires innovative solutions for the following technological problems: R.F. Yazıcıo˘glu et al., Biopotential Readout Circuits for Portable Acquisition Systems, © Springer Science + Business Media B.V. 2009

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Introduction

Fig. 1.1 The technology vision for the year 2010

• The power dissipation of the nodes must be improved for a better power autonomy. • The size and the weight of the sensor nodes must be reduced for invisibility and comfort. • New integration and packaging techniques must be developed to decrease the form factor and reconcile the sensor nodes with the human body. • Intelligence of the sensor nodes must be improved in order to shift from the treatment of the diseases towards the prevention of the diseases. • The sensor nodes should include its own energy source, which consists of energy generation and storage. • The cost of the system must be minimized. On the other hand, the nodes must be able to deal with the following implementation issues [5]: • • • •

Reliability, robustness, and durability. Look/unobtrusiveness. User identification. Zero maintenance and fault recovery.

So that the sensor nodes can be integrated in the every-day life of the human beings.

1.3 Scope of the Book A crucial and important part of a medical diagnostics system is the monitoring of the biopotential signals. These signals are recorded routinely in the modern clinical

1.3 Scope of the Book

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Fig. 1.2 A biopotential sensor node architecture indicating the scope of this Book

practice. Commonly, patients are connected to a bulky and mains-powered instrument, which reduces their mobility and creates discomfort. This limits the acquisition time, prevents the continuous monitoring of patients, and affects the diagnostics of the illness. Therefore, there is a growing demand for low-power, small-size, and ambulatory biopotential acquisition systems [2, 4, 6–9]. The ultimate goal is to implement a biopotential acquisition system that is comfortable and invisible to eye with long-term power autonomy, high signal quality, and configurability for different biopotential signals. The aim is not only to increase the patients’ quality of life, but also to extend device applications to sports, entertainment, comfort monitoring, etc. Therefore, intelligent and miniaturized biopotential acquisition sensor nodes can improve the functionality of a BAN system. The most critical demands for these sensor nodes are the ultra low power dissipation and minimal size for the improved autonomy. However, it should be noted that the signal quality must not be sacrificed for extending the power autonomy of the sensor nodes. Figure 1.2 shows the architecture of a typical biopotential acquisition sensor node. A crucial and power consuming building block of this sensor node is the readout front-end, which defines the quality of the extracted signals. However, long-term power autonomy dictates the need for low-power circuitry, putting strict design constraints on the readout front-end circuit. The challenges for designing a biopotential readout front-end circuit can be summarized as follows: Due to the low frequency behavior of the signals, in-band noise of the readout is dominated by 1/f noise. Moreover, the common-mode interference from the mains to the human body disturbs the biopotential signals [10], and there is the problem of electrode offset generated at the skin-electrode interface [11]. Therefore, in order to achieve signal extraction under these circumstances a readout front-end is needed with high CMRR, low-noise, and band-pass filter characteristics. Moreover, amplitude and bandwidth characteristics of biopotential signals vary

4

Introduction

for different biopotential signals, and different applications of these signals. Therefore, the front-end should have configurable gain and filter characteristics. As a consequence, this thesis describes the design and the implementation of lownoise and low-power ASICs convenient for the acquisition of different biopotential signals. This enables the implementation of miniaturized biopotential acquisition sensor nodes with long-term power autonomy. It should be noted that the circuits described in this thesis do not want to sacrifice performance for reducing power dissipation. Instead, the goal is to increase the performance of the readout circuits and decrease their power dissipation simultaneously.

Chapter 2

Introduction to Biopotential Acquisition

2.1 Introduction The biopotential readout circuits have to cope with various problems, while extracting the biopotential signals from the human body. These problems are not only due to the extremely weak characteristics of the biopotential signals but also due to the environment and the apparatus that are being used during the signal acquisition. Therefore, the design of a readout circuit for the biopotential acquisition systems requires a solid understanding of not only the analog circuit design techniques but also the origin and the characteristics of the biopotential signals. This Chapter gives a brief introduction to the challenges of extracting biopotential signals. Section 2.2 introduces the genesis of the biopotential signals, and presents the frequency and the amplitude characteristics of the EEG, ECG, and EMG signals. Section 2.3 explains the chemistry of the biopotential electrodes, which acts as a transducer between the human body and the readout circuit, and describes the non-ideal characteristics of the biopotential electrodes. Section 2.4 introduces the interference theory, i.e. the theory of the common-mode interference from the mains. This Section also presents the state-of-the-art in IA design, the building block that defines the quality of the extracted signals from the biopotential electrodes. Section 2.5 describes the chopper modulation technique, which is used in the literature to achieve low-noise and high-CMRR IAs. Finally, Sect. 2.6 states the conclusions of this Chapter.

2.2 Introduction to Biopotential Signals Biopotential signals are generated due to the electrochemical activity of certain class of cells that are components of the nervous, muscular or glandular tissue. Electrically, these cells exhibit a resting potential, and when they are stimulated they generate an action potential. The electrical activity of each cell is described by the ion exchange through the cell membrane. The membrane potential of an inactive cell is called the resting potential. At the rest state, the membrane of the cell is more permeable to K+ than Na+ , and K+ concentration of the interior of the cell is much higher than the exterior. Therefore, a diffusion gradient of K+ occurs towards the exterior of the cell making the interior more negative relative to the exterior, which results in an electrical field build up towards the interior of the cell. At steady state, the diffusion gradient of the K+ ions are balanced by the electrical field and the equilibrium is reached with a polarization voltage of nearly −70 mV. When the cell is electrically stimulated (through the central nervous system), the permeability of R.F. Yazıcıo˘glu et al., Biopotential Readout Circuits for Portable Acquisition Systems, © Springer Science + Business Media B.V. 2009

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6


Fig. 2.1 Frequency and amplitude characteristics of the biopotential signals, EEG, ECG, and EMG, and the correlating signals of the biopotential signals

the membrane to Na+ ions increases. Thus, Na+ ions diffuse toward the inside of the cell, resulting in a potential increase of the interior of the cell. As the potential reaches to +40 mV, the permeability of the membrane to Na+ ions decreases and to K+ increases, resulting in a sharp decrease in the membrane potential towards its rest state. This cycle of the cellular potential is called the action potential, and the biopotential signals, such as EEG, ECG, EMG, are the result of several action potentials produced by a combination of different cells [11]. EEG is the measure of the electrical activity of the brain created by a group of neurons. Electrodes are placed on the predefined locations of the scalp [12], and the voltage of the electrodes versus a reference is measured. Similarly, ECG is the measure of the electrical activity of the heart. It is extracted from the electrodes on the chest, and it is characterized by its three main features, the P-wave, the QRScomplex, and the T-wave [11]. Finally, EMG is the electrical potential of the skeletal muscle cells, which is generated during the contraction of the muscle. Figure 2.1 shows the frequency and amplitude characteristics of EEG, ECG, and EMG waves, when recorded by surface electrodes [11]. In order to extract the biopotential signals, the correlating signals, such as the 1/f noise of the CMOS transistors, the interference from the mains, and the DC differential electrode offset voltage between the biopotential electrodes, must be rejected or filtered by the readout circuit.

2.3 Introduction to Biopotential Electrodes Although readout circuits implemented in CMOS technology usually have very large input impedance, a non-zero current should flow from the body to the input

2.3 Introduction to Biopotential Electrodes

7

of the readout circuit. However, this current is carried by ions in the body, whereas it is carried by electrons on the wires connecting the electrodes to the readout circuit. Therefore, a transducer interface is necessary between the body and the readout circuit that converts the ionic current into electronic current, or vice versa. This interface is called a biopotential electrode. The operation principle of a biopotential electrode can be described by an electrode–electrolyte interface. In order to allow the current flow between the electrolyte, which has no free electrons, and the electrode, which has no free cations or anions, a chemical reaction has to occur at the interface that can be represented by the following general equations: C ↔ C+ + e− A− ↔ A + e −

(2.1)

In this equation, C and A stands for the cations and anions in the electrolyte, respectively, and it has been assumed that the electrode is made up of the cations of the electrolyte. Therefore, the cations in the electrode can oxidize at the interface, and the anions coming to the interface can be oxidized to a neutral atom, both resulting in a free electron in the electrode. Thus, current can pass from the electrode to the electrolyte. Similarly, the reduction reactions create current in the reverse direction. Therefore, if a metal is inserted in a solution, which has the ions of the same metal and some anions to preserve the neutrality of the solution, the reactions given in (2.1) starts to occur depending on the concentration of the cations in the solution. This disturbs the neutrality of the solution, and a charge gradient builds up at the electrode–electrolyte interface, resulting in a potential difference that is called the half-cell potential. The mismatch of the half-cell potential between the reference electrode and the recording electrode is responsible for the differential DC electrode offset voltage.

2.3.1 Equivalent Circuit Model Biopotential electrodes can be grouped as, polarizable and non-polarizable electrodes. The perfectly polarizable electrodes have no actual charge transfer between the electrode–electrolyte interface. Thus, such electrodes behave as capacitors and the current is due to the displacement current. On the other hand, the current passes freely across the electrode–electrolyte interface of the non-polarizable electrodes, thus these electrodes behave as a resistor. However, neither of the two types can be fabricated. Thus, practical electrodes are somewhere in between these two types. The equivalent circuit of an electrode can be described as shown in Fig. 2.2. CA and RA represents the impedance associated with the electrode–electrolyte interface, and RS is the resistance of the electrolyte solution. The half-cell potential of the interface is represented with a voltage source, Vhc .

8


Fig. 2.2 Equivalent circuit model of a biopotential electrode

In conventional electrodes, the electrolyte represents the gel that is used in between the tissue and the electrode. Since the biopotential signals are generally extracted differentially from two electrodes, there is always a mismatch between the half-cell potentials due to the difference in the gel–tissue interface (sweat glands and different epidermis effect the half-cell potentials of the electrodes [11]). Therefore, there appears a DC potential between the two electrodes, which is much larger than the µV level biopotential signals. This DC potential will be referred as differential DC electrode offset voltage in the rest of the text. Hence, the biopotential readout circuit should exhibit high-pass filter (HPF) characteristics to prevent the saturation of the readout circuit.

2.3.2 Types of Biopotential Electrodes Biopotential electrodes can also be classified as: wet, dry, and non-contact electrodes. Wet electrodes use a gel type electrolyte between the electrode and the surface of the skin. The most common type of a wet electrode is the Ag/AgCl electrode. Its characteristic approaches that of a perfectly non-polarizable electrode. The electrode metal is made up of Ag, which is coated with an AgCl layer. An electrolyte gel is used to establish the electrical contact between the electrode and the surface of the skin. The most important advantages of the Ag/AgCl electrodes are their low impedance and low artifact due to the motion of artifact. On the other hand, the use of the gel creates discomfort and increases the preparation time of the acquisition system. Dry electrodes, as their name imply, do not use any kind of gel to make contact between the electrode and the body. Thus, they are more comfortable and easy to prepare compared to the wet electrodes. However, due to the lack of the electrolyte, their characteristics are closer to a polarizable electrode, which can be characterized as a leaky capacitor. Therefore, the readout circuit for a dry electrode must have very high input impedance (1 G). Moreover, due to the very high impedance, the readout circuit must be placed very close to the electrode in order to prevent the electromagnetic interference. This can be achieved by using active electrodes [13]. However, the main disadvantage of the active electrodes is the necessity for matched components to achieve high CMRR, which is not straight forward in CMOS process. Alternatively, the characteristics of the dry electrodes can be improved by utilizing the advantages of MEMS processing technology to prevent the active electrode usage. Reference [14] proposes a dry electrode with micromachined spikes, where

2.4 Introduction to Biopotential Amplifiers

9

these spikes can penetrate through the stratum corneum of the skin, and bring the electrode directly in contact with the electrically conductive living epidermis. Test results shows that this dry electrode achieves 87 k at 0.6 Hz, and the arithmetic mean of the offset voltage between two electrodes is 11.8 mV, which is comparable to the performance of wet electrodes. Non-contact electrodes can be considered as a pure capacitor between the human body and the readout electronics, so they allow remote sensing of the biopotential signals [15]. They are intrinsically safe (no DC current drawn from the body) and biocompatible. However, the input impedance of the readout circuit must be extremely high for extracting the biopotential signals from non-contact electrodes. In addition, any motion of the electrode with respect to the body will create an artifact due to the change of capacitance. References [16] and [17] demonstrate ECG and EEG signals using non-contact electrodes.

2.4 Introduction to Biopotential Amplifiers The essential purpose of a biopotential amplifier is to amplify and filter the extremely weak biopotential signals. However, the design of this amplifier is not straight forward. Biopotential amplifiers must cope with various challenges in order to extract the biopotential signals. Meanwhile, the power dissipation of the amplifier must be minimized for long-term power autonomy. The challenges of designing a biopotential amplifier for portable biopotential acquisition systems can be summarized as follows: • • • • •

High CMRR to reject interference from mains. HPF characteristics for filtering differential DC electrode offset. Low-noise for high signal quality. Ultra-low power dissipation for long-term power autonomy. Configurable gain and filter characteristics that suit the needs of different biopotential signals and different applications.

Figure 2.1 shows the frequency characteristics of the correlating signals for the biopotential signals. The interference from the mains to the human body appears at the 50/60 Hz and at its harmonics. Thus, amplifier must have high CMRR in order to reject this common-mode signal. The differential DC electrode offset voltage, which is orders of magnitude larger than the biopotential signals, must be rejected to prevent the saturation of the amplifier. Therefore, the biopotential amplifier must have HPF characteristics. Meanwhile, the biopotential amplifier should minimize its power dissipation to improve the power autonomy. Subsection 2.4.1 will describe the theory of interference from the mains, and Sect. 2.4.2 will describe a parameter called NEF that can be used to compare the power-noise performance of the different amplifiers.

10


Fig. 2.3 Electrostatic interference to the human body

2.4.1 Interference Theory Biopotential acquisition systems are often disturbed by the interference from the mains. Two main types of interference are called the electromagnetic interference and the electrostatic interference. In the case of the electromagnetic interference, the magnetic field created by the alternating mains current cuts the loop enclosed by the human body, the leads of the circuit, and the biopotential amplifier. This induces an electromotive force (EMF), which creates an AC potential at the input of the circuit. The electromagnetic interference can be reduced by decreasing the area of the loop by twisting the cables [18]. Further reduction is possible by using miniaturized portable biomedical acquisition systems that can be placed much closer to the electrodes, which in turn reduces the cable length. Figure 2.3 shows the equivalent circuit for describing the electrostatic interference [10]. The human body is capacitively coupled to the mains via Cbp and also to the ground via Cbg . In addition to these two capacitances, there exists an isolation

2.4 Introduction to Biopotential Amplifiers

11

capacitance between the earth and the ground of the amplifier battery. As a result, the path through the coupling capacitors creates a displacement current, ID , passing through the human body and splitting equally between the Cbg and Ciso [19] (Cbg and Ciso have similar capacitance values and Rgnd is much smaller than the impedance of Ciso and Cbg at 50 Hz/60 Hz). Therefore, an AC voltage with magnitude: ID Rgnd VCM = (2.2) 2 is created on the human body. Unless there is a mismatch between Rel1 and Rel2 , this voltage appears as a common-mode input to the amplifier, and can be rejected by the amplifiers high CMRR. However, there is always a mismatch between the electrode impedances, due to this mismatch, a differential error signal is created with amplitude: |Rel1 − Rel2 | VIN = VCM (2.3) Zin where Zin stands for the input impedance of the amplifier [18]. As a conclusion, a high CMRR alone is not sufficient for an IA to completely reject the electrostatic interference. In addition, it should implement very high input impedance.

2.4.2 Noise-Efficiency Factor (NEF) of Biopotential Amplifiers Due to the small frequency bandwidth of the biopotential signals, it is the target noise level that defines the power dissipation of the biopotential amplifiers. As the type and the number of noise sources increase, the total noise of the amplifier also increases. Therefore, the amplifier requires more power to achieve the target noise level. The term called noise-efficiency factor (NEF) is first introduced by [20] in order to compare the power–noise performance of different amplifiers and can be expressed as: 2Itot NEF = Vin,rms (2.4) πVt 4kT BW where BW is the −3 dB bandwidth of the amplifier and Vin,rms is the total input referred voltage noise of the amplifier. The NEF of a single bipolar transistor having only thermal noise is 1, which is the theoretical limit for any practical circuit. NEF can be used to compare the power–noise performance of different amplifiers. The amplifier with lower NEF can achieve lower power dissipation for a given noise level.

12


Fig. 2.4 Simplified schematic of a current balancing IA

2.4.3 State-of-the-Art in Instrumentation Amplifier Design The IA is the most critical building block of the analog readout front-end in terms of the signal quality and clarity. It defines the noise level and the CMRR of the readout front-end, and filters the differential DC electrode offset. Hence, it is generally the most power consuming building block of an analog readout front-end. Therefore, the design effort focuses on implementing a low-power and low-noise IA. The most common and well-known IA architecture is called the three-opamp architecture [21–25]. However, it is very-well known that the CMRR of the threeopamp IA is highly dependent on the matching of the resistors [26]. This matching requires laser trimming in standard CMOS technology that increases the cost. In addition to that, the necessity for low output impedance opamps for driving the feedback resistors, results in excessive power dissipation. A second technique for implementing IAs uses switched-capacitor (SC) architectures [27, 28]. Although SC amplifiers are capable of eliminating the 1/f noise of the CMOS transistors, they suffer from the noise fold-over above Nyquist frequency (half of the sampling frequency) [29]. In order to compensate this increase in noise, the power dissipation of the SC amplifiers has to be increased. Therefore, SC architectures are not efficient for low-power and low-noise IAs. Another IA topology is called Current Balancing (Current Feedback) IA (CBIA) [20, 30–33]. Figure 2.4 shows the simplified block diagram of a CBIA. The input stage acts as a transconductance amplifier. The current passing through Rin is copied to the transresistance stage, and the voltage created on Rout is buffered to the output. Therefore, the voltage gain of the CBIA can be written as: (Vout+ − Vout− ) =

Rout (Vin+ − Vin− ) Rin

(2.5)

where the ratio of the two resistors defines the voltage gain of the CBIAs. Thus, the CBIA topology eliminates not only the need for matched resistors for achieving high CMRR but also the need for low output impedance amplifiers. Therefore, the CBIA topology is convenient for implementing low-power and low-noise IAs. Table 2.1 summarizes the properties of three-opamp, switched-capacitor, and CBIA architectures for biopotential readout applications. On the other hand, 1/f noise of the CMOS transistors limits the power reduction and process induced transistor mismatches degrades the CMRR of the CBIA.

2.5 Introduction to Chopper Modulation Technique

13

Table 2.1 Comparison of the three-opamp, switched-capacitor, and CBIA architectures for biopotential readout applications

Low Power Dissipation Free of Noise Fold-Over High Input Impedance

Three-Opamp IA

SC IA

x √

x

√

x x

CBIA √ √ √ √

CMRR Independent from Matching of Passives

x

x

CMRR Independent from Matching of Transistors

x

x

x

Negligible 1/f Noise in the Signal Bandwidth

x

x

x

The chopper modulation technique [29] can be used both for increasing the CMRR of the amplifiers and for eliminating the 1/f noise of the CMOS transistors (See Sect. 2.5 for further description of the chopper modulation technique). However, the main disadvantage of the chopper modulated amplifiers is the inherent DC coupling. Thus, they also amplify the differential DC electrode offset voltage between the biopotential electrodes. References [34–36] addresses the AC coupling issue in IAs using the chopper modulation technique. Reference [34] uses off-chip HPFs for filtering the electrode offset voltage. However, this technique not only results in large number of off-chip components for multi-channel biopotential readout frontends, but also implements a very low input-impedance amplifier and degrades the signal-to-noise ratio of the IA. Reference [35] uses a differential difference amplifier for introducing HPF characteristics to a chopper modulated IA. However, this technique consumes excessive power due to the resistive feedback topology. Finally, Ref. [36] implements a low-power chopper stabilized IA with monolithic HPF. Although, the circuit achieves 105 dB CMRR and eliminates majority of the 1/f noise, the input impedance of the amplifier is very low (7.5 M) especially for EEG acquisition systems, where a minimum of 100 M is required [37].

2.5 Introduction to Chopper Modulation Technique The operation principle of the chopper modulation technique is described in Fig. 2.5 [38]. The low frequency input signal (the bandwidth of the signal must be smaller than fchop /2 to prevent aliasing) is modulated with the square wave modulation signal, m(t). This shifts the frequency spectrum of the input signal, X(s), to the odd harmonics of fchop . Then, the modulated input signal is amplified by the amplifier with transfer function A(f ), and demodulated with m(t). This shifts the modulated spectrum back to its original location, leaving replicas at the odd harmonics of fchop . These replicas can be filtered by a LPF.

14


Fig. 2.5 Operation principle of chopper modulation technique. Input signal is modulated by m(t), amplified by A(f ), and demodulated by m(t)

Subsections 2.5.1 and 2.5.2 will present the necessary formulas for understanding the operation of the chopper modulation technique. More detailed analysis of the chopper modulated amplifiers can be found in [29, 39–41].

2.5.1 Noise Analysis of Chopper Modulation Technique Figure 2.5 describes the principle of how the chopper modulation technique eliminates the 1/f noise of the MOS transistors. The output noise and the offset of the core amplifier are indicated by vn and voff , which are only modulated by the output modulator. Therefore, the input referred noise of a chopper modulated amplifier is equivalent to vn , multiplied with a square wave with frequency fchop , when referred to the input of the chopper modulated amplifier. Hence, the double-sided inputreferred voltage noise power spectral density (PSD), Sin (f ), of the amplifier can be written as: 2 ∞ 1 2 Svn (f − nfchop ) (2.6) Sin (f ) = π n2 n=−∞,odd


15

This equation should be handled separately for the thermal noise and the 1/f noise. Considering first the thermal noise component, (2.6) can be approximated as (2.7), if the fc of the amplifier is much larger than fchop [29]. This equation is only valid for the region where |f | < 0.5fchop . Further approximation reduces (2.7) to (2.8) considering that fc fchop : fc tanh( π2 fchop ) 1 − S (f = 0) = S Sin,thermal (f ) ∼ = in,thermal 0 f π 2

Sin,thermal ∼ = S0

c fchop

≤ 0.5 and fc 1 fchop chop

f for f

(2.7)

(2.8)

As a result, the thermal noise of the chopper modulated amplifiers is not affected from the chopping operation as long as fc of the amplifier is much larger than fchop , which is due to the fact that the chopping operation only periodically changes the sign of the thermal noise. On the other hand, considering that the 1/f noise of an amplifier is in the form of (2.9), the PSD of the input referred 1/f noise can be approximated by inserting (2.9) to (2.6), which can be expressed as (2.10) and indicates that the input referred 1/f noise of chopper modulated amplifiers can be approximated by a white noise component in the baseband [29]. S1/f (f ) = S0

fc,1/f |f |

fc,1/f Sin,1/f (f ) ∼ = 0.8525S0 fchop

(2.9)

(2.10)

As a result, the total input referred noise of the amplifier in the baseband can be calculated by combining (2.8) and (2.10) as: f fc,1/f ∼ ≤ 0.5 and fc 1 (2.11) for Sin,total (f ) = S0 1 + 0.8525 fchop fchop fchop As a conclusion, the chopper modulation technique can effectively eliminate the 1/f noise of the MOS transistors without affecting the thermal noise, if fchop can be selected to be much higher than fc,1/f .

2.5.2 Charge Injection and Residual Offset of Chopper Modulated Amplifiers Theoretically chopping amplifiers can achieve zero input referred offset voltage, since the offset of the core amplifier is modulated by the output chopper and can

16


Fig. 2.6 Input modulator schematic of a chopper amplifier describing the charge injection from the nMOS switches to the input of the amplifier

be filtered. However, due to the non-ideality of the chopper switches, a residual offset remains. Figure 2.6 shows the schematic of a chopper modulator implemented with nMOS switches. Switches M1 , M2 and M3 , M4 are periodically toggled by the modulator signals m(t) and m(t), respectively. During the switching of the nMOS transistors a certain amount of charge is injected to the source and drain of the MOS switch [42]. Although, in an ideal situation the charge injection of the transistors M1 and M2 are equal and appears as common-mode at the input of the amplifier, there is always a small mismatch, q1 , which is injected to the input capacitance of the amplifier, Cin . Similarly, the mismatch between M3 and M4 results in an equivalent charge injection of q2 . As a result, the total equivalent charge that is injected to the input of the amplifier can be written as: q = |q1 − q2 |

(2.12)

which results in an equivalent differential input voltage of: Vinj =

q Cin

(2.13)

at the input of the amplifier with time constant: τinj = Rs Cin

(2.14)

as illustrated in Fig. 2.6. The input voltage, Vinj is amplified by the amplifier and then demodulated by the output chopper demodulator, creating an error output voltage, which has an average DC level of Voff . Assuming an amplifier with infinitely large bandwidth. The total input referred offset of the amplifier can be written as [40]: Voff = 2τ · fchop · Vinj

(2.15)


17

As a conclusion, the offset of the chopper modulated amplifiers depend on the source resistance and the amount of the charge injection to the input. On the other hand, it is independent of the input capacitance of the amplifier. Assuming that the source resistance is defined by the sensor, where the readout is connected to, the offset of the chopped amplifiers can be decreased by reducing the sizes of the chopper switches or decreasing the chopping frequency. More detailed analysis about the offset in chopper amplifiers can be found in [39–41]. Several techniques have been proposed in the literature for reducing the inherent DC offset problem of the chopper modulated amplifiers. Reference [38] uses a bandpass filter between the input and the output choppers. However, matching of the bandpass filter center frequency with the chopping frequency limits the efficiency of this technique. Reference [43] uses nested choppers, where in addition to the input and output modulators, another pair of slow chopping modulators are used to modulate the output spikes of the fast modulator. Although, this technique can be very efficient for slow signals, biopotential signals have too large bandwidth for this solution (1 kHz bandwidth is necessary for EMG signals). Another technique is proposed by [44]. It uses a SC notch filter with synchronous integration after the output modulator to filter both the chopping ripple and the modulated amplifier offset, however results in excess quiescent current and complexity in the signal path.

2.5.3 Signal Distortion in Chopper Modulated Amplifiers Signal distortion problem appears in chopper amplifiers due to the finite bandwidth of the core amplifier. Figure 2.7 describes the signal distortion in chopper modulated amplifiers. The differential input signal is modulated with the square wave modulation signal. However, due to the finite bandwidth of the core amplifier, high frequency components of the square wave is filtered by the core amplifier. When

Fig. 2.7 Signal distortion problem in a chopper modulated amplifier due to the finite bandwidth of the core amplifier

18


this signal is demodulated by the output chopper, signal distortion in the shape of spikes appears at the output with the time constant: τ=

1 2πfc

(2.16)

The main consequence of these spikes is the reduction in the gain of the chopper modulated amplifier, which can be derived by considering a DC input voltage and calculating the average value of the output voltage for half the period of the chopping signal: 4τ Achopped (f ) = A(f ) 1 − (2.17) T It should be noted that the techniques presented in the Sect. 2.5.2 are also effective for reducing the signal distortion in chopper modulated amplifiers.

2.5.4 CMRR of the Chopper Modulated Amplifiers Basically, there are two different mechanisms that define the CMRR of the conventional amplifiers: Systemic common-mode gain, which is due to the topology of the IA and mismatch induced common-mode gain, which is due to the process induced mismatches. Both of these CMRR reduction mechanisms can be eliminated by the chopper modulation technique. The chopper structure shown in Fig. 2.6 is transparent to common-mode signals. Therefore, the input common-mode signal passes through the input chopper without being modulated and appears as a common-mode input to the core amplifier. The common-mode gain of the core amplifier converts the common-mode input into differential output. However, this differential output voltage, which is due to the non-zero common-mode gain of the amplifier, is modulated by the output modulator. Thus, it can be eliminated in a similar way the 1/f noise and the offset of the IA are filtered.

2.6 Conclusions Biopotential readout circuits suffer from various problems for extracting biopotential signals. The extremely weak amplitudes of the biopotential signals make them susceptible to various correlating signals. Table 2.2 summarizes the requirements of a configurable readout front-end for biopotential acquisition systems. The first problem is the 1/f noise of the CMOS transistors that dominates the noise of the readout circuit in the frequency band of the biopotential signals. Moreover, there is the interference from the mains, thus the readout circuit must achieve high CMRR to reject the large common-mode signals, while amplifying the biopotential signals. Both the interference and the 1/f noise problem can be solved by

2.6 Conclusions

19

Table 2.2 Requirements of a configurable readout front-end for biopotential acquisition systems Problem Solution Technique 1/f Noise

1/f noise Filtering

Chopper Modulation

Common-Mode Interference

High CMRR

Chopper Modulation

Differential DC Electrode Offset

HPF Characteristics

?

Configurability for Different Biopotential Signals

Variable Gain

SC Resistive ?

Long Term Power Autonomy

Variable Bandwidth

?

Low-Power Design

?

using the chopper modulation technique. However, there is the problem of the differential DC offset between the electrodes. This DC voltage is orders of magnitude larger than the biopotential signals and can saturate the IA. Thus, the IA must have HPF characteristics for filtering the differential DC electrode offset voltage. Unfortunately, the chopper amplifiers are inherently DC coupled. Therefore, there is a need for a chopper modulated IA with HPF characteristics, so that the 1/f noise, the interference, and the differential DC offset problems can be solved and high quality biopotential signals can be extracted. In addition, configurable characteristics for different biopotential signals and ultra low power dissipation for long term power autonomy is a must for portable biopotential acquisition systems.

Chapter 3

24-Channel EEG Readout Front-End ASIC

3.1 Introduction The existing multi-channel EEG acquisition systems make use of off-the-shelf components for the implementation of the analog readout front-end. This not only consumes an excessive amount of power but also increases the size of the system that limits the autonomy of the patient. Therefore, there is a need for a multi-channel ASIC that is tailored towards the low-power and the small size needs of the biopotential acquisition systems. This Chapter describes a 24-channel EEG readout front-end ASIC that can circumvent the above mentioned problems of size and power for the EEG acquisition systems with large number of channels. It is capable of extracting biopotential signals from conventional Ag/AgCl biopotential electrodes. Section 3.2 describes the architecture of the 24-channel EEG readout front-end ASIC. Each channel of the ASIC uses a CBIA architecture that is described in Sect. 3.3 to filter the out of band signals and to reject the common-mode interference. Furthermore, Sect. 3.4 introduces a new CMRR reduction mechanism called electrode offset induced commonmode gain and demonstrates that this reduction mechanism is dominant for the IAs that are being used under large differential DC offset voltage between the biopotential electrodes. Later, Sect. 3.5 describes the gain stage of the channels that is for the further amplification of the output of the CBIA. Section 3.6 presents the test results of the ASIC, and Sect. 3.7 states the conclusions of this Chapter.

3.2 ASIC Architecture Figure 3.1 shows the simplified schematic of the 24-channel EEG readout front-end ASIC. It consists of 24 EEG readout channels and a single ECG readout channel that are multiplexed at the back-end and buffered to the output. The 24 EEG channels share a common reference input that is compatible with the applications using 10– 20 electrode placement systems [12]. On the other hand, the single ECG channel has a separate reference input so that ECG signals can be extracted independently from the EEG signals. Each channel consists of an IA and two cascaded gain stages. The front-end IA amplifies the biopotential signals and performs the differential-to-single ended conversion, while rejecting the common-mode signals. Then, two SC amplifiers further amplify the signal. The gain of the IA is 10 and the gain of the SC gain stage can be selected between 20 and 1000. This results in a programmable channel gain between 200 and 10000 that can be digitally configured by digitally selecting the gain R.F. Yazıcıo˘glu et al., Biopotential Readout Circuits for Portable Acquisition Systems, © Springer Science + Business Media B.V. 2009

21

22


Fig. 3.1 Architecture of the 24-channel EEG readout front-end ASIC

capacitors in the SC gain stage. On the other hand, the gain of the IA and the first amplification stage are 5 and 4 for the ECG channel, respectively, which translates into configurable gain between 20 and 1000. The IA of each channel uses off-chip passive components indicated by gray color in Fig. 3.1. These external components are used for setting the gain and the cut-off frequencies of the IA.

3.3 Current Balancing IA 3.3.1 Implementation Each channel of the 24-channel EEG readout front-end circuit uses the CBIA architecture as a preamplifier. Figure 3.2 shows the schematic of the CBIA architecture that consists of a transconductance stage and a transresistance stage [33]. The first stage is a transconductance amplifier, where the input voltage is converted into a current. Under steady state, this current equals the differential input voltage divided by R1 , which is mirrored to the transresistance stage and converted into voltage on the resistor R2 . Therefore, the gain of the IA can be defined as: Gain =

R2 R1

(3.1)

3.3 Current Balancing IA

23

Fig. 3.2 Schematic of the CBIA of each channel of the 24-channel EEG readout front-end ASIC. Off-chip components are indicated with gray color Table 3.1 Operating points of the transistors in Fig. 3.2 Transistors

W/L (µm/µm)

Ids (µA)

gm /Ids (1/V)

M1 , M2

800/20

12

12

M3 , M4

100/10

6

9.2

M5 , M6

300/200

12

5.1

M7 , M8

100/200

6

4.2

M9

14/20

2

8.5

M10

84/20

12

8.5

M11 , M12

300/3

6

21

Passives R1

10 k

Cc

50 pF

The bandwidth characteristics of the IA is set by R2 -CLPF and OTA1 -CHPF . The R2 -CLPF pair sets the LPF cut-off frequency of the IA as described in (3.2), and the HPF cut-off frequency is set by the OTA1 -CHPF according to (3.3). Therefore, the gain, the LPF cut-off frequency, and the HPF cut-off frequency can be precisely defined with three external passives. Table 3.1 shows the dimensions and the operating points of the implemented IA. fIA,LPF =

1 2πR2 CLPF

(3.2)

gm,OTA1 2πCHPF

(3.3)

fIA,HPF =

24


Fig. 3.3 Schematic of the OTA1 of Fig. 3.2

The resistor R1 is selected as 10 k and implemented using hipo resistors. If R2 is selected as 200 k the gain is set to 10. The LPF cut-off frequency of the IA can be set to 80 Hz by selecting CLPF as 10 nF. The size of the CHPF is defined by the transconductance of OTA1 . In order to reduce the size of the external capacitor, the transconductance of OTA1 must be as small as possible, which can be reduced using the series-parallel division of current as proposed in [45, 46]. Figure 3.3 shows the schematic of the OTA1 implementation. The equivalent transconductance of the architecture is 3.2 µS. Therefore, selecting CHPF as 1 µF sets the HPF cut-off frequency of the IA to 0.5 Hz. Different from the architecture of [33], the current mirrors I1 and I2 are implemented using the active current mirror architecture, shown in Fig. 3.4 [47], which increases their output resistance compared to a conventional cascode current mirror. This is necessary for the CMRR of the IA to be resistant to the increasing DC differential offset of the biopotential electrodes (This will be further described in Sect. 3.4). The output resistance of the active current mirror can be expressed as: Rout,Mirror = Av gm,MB1 Rds,MB1 Rds,MA1

(3.4)

which indicates that the active current mirror multiplies the output impedance of a conventional cascode current mirror by the open-loop gain of the opamp, Av .

3.3.2 Measurement of Performance The presented CBIA, see Fig. 3.2, is implemented in a 0.5 µm 3-metal double-poly CMOS process through AMIS and consumes 110 µA from a single 3 V supply. The implemented CBIA is capable of filtering ±50 mV differential DC electrode offset before the input transconductance stage saturates. Figure 3.5 shows the gain-

3.4 CMRR Model for Biopotential Instrumentation Amplifiers

25

Fig. 3.4 Current mirror architecture of I1 and I2 of Fig. 3.2

Fig. 3.5 Gain-bandwidth measurement of the CBIA

bandwidth plot of the IA without using the CLPF capacitor that sets the LPF cut-off frequency. The in-band gain of the IA is 10.5, and the HPF cut-off frequency appears at 0.5 Hz. Figure 3.6 shows the input referred voltage noise PSD of the IA. The total input referred voltage noise of the IA can be calculated as 0.64 µVrms between 0.5 Hz and 100 Hz.

3.4 CMRR Model for Biopotential Instrumentation Amplifiers The interference from the mains to the human body appears a common-mode signal at the input of the IA (see Sect. 2.4.1). Hence, the biopotential signals are correlated by the common-mode interference. The CMRR of the IA defines how good the IA rejects this common-mode interference and amplifies the biopotential signals. Basically, two different mechanisms define the CMRR of the conventional amplifiers: Systematic common-mode gain, which is due to the topology of the IA and

26


Fig. 3.6 Measured input referred voltage noise PSD of the CBIA

mismatch induced common-mode gain, which is due to the process induced mismatches. Unlike the conventional IAs, the IAs that are connected to the biopotential electrodes suffer from another type of common-mode gain mechanism called electrode offset induced common-mode gain. The differential electrode offset voltage at the input of the IA introduces operating point mismatches to the transistors of the IA. Unlike the other two mechanisms, the chopper modulation technique can not eliminate the electrode offset induced common-mode gain. This is due to the fact that the differential DC offset between the biopotential electrodes is also modulated by the input chopper. Therefore, any error signal at the output of the core amplifier appears to be modulated. Hence, it is demodulated to the baseband by the output chopper. Therefore, an IA for biopotential applications must preserve its CMRR under high differential DC offset voltages. The following subsection will describe a model for calculating the amount of CMRR reduction with changing electrode offset voltage. Although the model will be derived for a specific type of IA (a CBIA), its conclusions can be generalized for all types of IAs.

3.4.1 Systematic CMRR The systematic CMRR, CMRRsys , of an IA depends on the architecture. Unless the IA architecture is fully-differential, CMRRsys is finite. Figure 3.7(a) shows the simplified schematic of the CBIA of [33] and Fig. 3.7(b) shows the low-frequency small signal model of the same IA1 . Assuming that the symmetric transistors are 1 The small signal model is given for the flipped version of the circuit of Fig. 3.7(a), i.e., nMOS and pMOS transistors are interchanged.


27

(a)

(b) Fig. 3.7 (a) Simplified schematic of the CBIA, (b) low-frequency small-signal circuit of the CBIA

perfectly matched, the common-mode gain of the transconductance stage can be written as:

ACM =

I1 I2 gds,M5 go (2g1 + gm,M1 ) =− = vin vin 2gm,M1 gm,M5

(3.5)

where g1 = 1/R1 . Similarly, the differential gain of the transresistance stage can be written as: 1 vout = (I2 − I1 ) 2g2

(3.6)

28


where g2 = 1/R2 . Thus, CMRRsys of the CBIA of Fig. 3.7(a) can be expressed as: CMRRsys =

ADM 2g1 gm,M1 gm,M5 = ACM gds,M5 go (2g1 + gm,M1 )

(3.7)

Equation (3.7) indicates that CMRRsys of the IA can be increased by maximizing g1 and gm,M1 . Therefore, the input pair transistors should be operated in weak inversion for maximizing their transconductance [48]. Additionally, the output resistances of the current sources I1 and I2 can be increased in order to boost the CMRR, which is demonstrated by [49].

3.4.2 CMRR Limit due to Differential DC Electrode Offset Even though the transistors of a circuit are perfectly matching, the differential DC electrode offset voltage introduces operating point mismatches to the IA, which reduces its CMRR. These operating point mismatches can be divided into two. The first one is due to the mismatch of the drain-to-source voltages of the input pair transistors and the second one is due to the mismatch of the output transconductances of the current sources I1 and I2 . The effect of the drain-to-source voltage mismatch of the input pair transistors on the CMRR of the IA can be described as follows: The differential input voltage to the IA is copied to the terminals of R1 . If we assume that the gmi has infinite transconductance, the drain to source voltage of the input pair transistors will differ by the amount of the differential input voltage. Hence, there will be a gds mismatch between the input pair transistors. Figure 3.7(b) shows the introduced mismatch gds to the input pair transistors. Therefore, CMRR limit of the circuit due to the output transconductance mismatch of the input pair transistors can be written as: CMRRgds (vin ) =

gm gds (vin )

(3.8)

On the other hand, the effect of the output transconductance mismatch of the current sources can be described as follows: The differential DC input will create a DC current through R1 . This disturbs the matching of the quiescent current of the input pair transistors. However, the gmi stage compensates this mismatch by adjusting its output currents. Therefore, the differential DC input voltage does not disturb the DC quiescent current of the input pair transistors, but it affects the DC operating points of the transistors of I1 and I2 by changing the quiescent current. Figure 3.7(b) shows the added parameter, go , in order to represent the output transconductance mismatch of the current source I1 and I2 . Calculation of the CMRR considering this parameter results in: CMRRgo (vin ) =

2g1 go (vin )

(3.9)


29

After separately describing the three limitations for maximum achievable CMRR, the equivalent CMRR, CMRReq can be written as the superposition of the CMRRsys , CMRRgds , and CMRRgo as: 1 1 1 1 = + + CMRReq CMRRsys CMRRgds CMRRgo

(3.10)

assuming that the CMRR limiting factors are uncorrelated.

3.4.3 Verification of the CMRR Model In order to verify the presented CMRR model, the CBIA implementation of Sect. 3.3 is used. The main difference between the implemented IA and the IA of Fig. 3.7(a) is the structure of the current mirrors I1 and I2 . Instead of using the conventional current mirrors, the active current mirror structure shown in Fig. 3.4 is used. This structure boosts up the output impedance of the current mirrors, as shown in (3.11), compared to a normal current mirror. Thus, the CMRRgo limit is increased by a factor of (Av gm,Mc1 /gds,Mc1 ). go,active =

gds,M1 gds,Mc1 1 gm,Mc1 Av

(3.11)

Figure 3.8 shows the comparison of the simulated, the calculated, and the measured CMRR of the implemented IA at 50 Hz with changing differential DC input voltage, which represents the differential DC offset voltage of the biopotential electrodes. CMRRgds and CMRRgo of (3.10) are also shown in the same figure to

Fig. 3.8 Comparison of the calculated, the simulated, and the measured CMRR of the implemented CBIA

30


demonstrate their contribution to CMRReq . Under low differential DC input voltage, CMRReq is defined by the process related mismatches of the circuit. However, as the differential DC input increases, which is the operating region of a biopotential IA, CMRReq is reduced due to the reduction in CMRRgds . The simulated, calculated, and measured CMRR fits well in the large differential DC input voltage regions. Use of the active current mirrors increases CMRRgo , leaving CMRRgds as the dominant mechanism defining the CMRReq of the IA. The simulations and calculations show that if the active current mirror structure is replaced with a conventional current mirror, the CMRReq of the IA will be reduced down to 75 dB at 50 mV differential DC input voltage, which is purely due to CMRRgo .

3.5 Programmable Gain Stage 3.5.1 Finite-Gain Compensated SC Amplifier The programmable gain stage of each channel of the 24-channel EEG ASIC uses a SC amplifier architecture. Conventional SC amplifiers rely on high open-loop gain OTAs. These amplifiers can be implemented using cascaded or cascode architectures. However, the cascode implementations reduce the amplifier output voltage swing and the cascade architectures increase power dissipation. These two problems can be circumvented by using finite-gain compensated SC amplifiers as shown in Fig. 3.9 and described in [29]. The operation of the amplifier can be divided into two phases. φa is the amplification phase. During φa , C1 discharges into C2 and the output is created, which

Fig. 3.9 Schematic of the finite-gain compensated SC amplifier

3.5 Programmable Gain Stage

31

Fig. 3.10 Equivalent circuits of the SC amplifier in amplification (phase A) and sampling (phase B) phases

is stored by C3 . φb is the sampling phase. The voltage difference between the input and the negative input of the OTA is stored by C1 . Also, in this mode, C3 acts as a feedback capacitor and keeps the output voltage of the amplifier close to the value stored during the amplification phase. Therefore, due to the fact that the output of the amplifier is not reset, the slew-rate considerations of the OTA is relaxed. 3.5.1.1 Precision and Offset of the SC Amplifier The main drawback of the SC amplifiers is their dependency on the open-loop gain of the OTA. The transfer function of the finite-gain compensated SC amplifier can be extracted by dividing the operation of the circuit into two phases, phase A and phase B. Using the equivalent circuit models shown in Fig. 3.10, and assuming that the sampling frequency is high enough so that the input voltage can be assumed to be constant between two samples [50], the following equations can be written: 3 vB C1 3 out (n − 2 ) − vB n − + C1 + C2 in 2 Av,OTA 3 vB vA (n − 1) C2 out (n − 2 ) A vout (n − 1)− = − out (3.12) + C1 + C2 Av,OTA Av,OTA 1 vB 1 vA out (n − 2 ) out (n − 1) A n − = v vB (n − 1) − = out out 1 2 Av,OTA (1 + Av,OTA )

(3.13)

1 3 B n − n − ≈ v vB out out 2 2

(3.14)

32


Fig. 3.11 Small signal equivalent circuit of the amplification and the sampling phases of the SC amplifier

Using (3.12), (3.13), and (3.14), the transfer function of the SC amplifier can be given as in (3.15), which shows that the gain error of the finite-gain compensated SC amplifier is scaled by A2v,OTA instead of Av,OTA as in a conventional amplifier. As a result, the necessity for high open-loop gain is eliminated by the using the finite-gain compensated SC amplifier architecture. Similar to the gain analysis the output offset voltage of the SC amplifier can be calculated as in (3.16). 3 C1 /C2 a b vout (n − 1) = (3.15) v n− 1 C2 ) in 2 1 + (1+C 2 Av,OTA

vout,offset =

(1 + C1 C2 ) vOTA,offset Av,OTA

(3.16)

3.5.1.2 Speed of the SC Amplifier Figure 3.11 shows the small signal equivalent circuits of the finite-gain compensated SC amplifier for the amplification and the sampling phases. The time constant of the output voltage of each phase can be calculated from the small signal equivalent circuits and can be expressed as given in (3.17) and (3.18), where Ceq,amp = C1 + Cin , Ceq,samp = C1 + C2 + Cin , and CL,eq = C3 + CL . CL,eq Ceq,amp 1 τamp = (3.17) + CL,eq + Ceq gm,OTA C2 τsamp =

1 gm,OTA

CL Ceq,samp + CL + Ceq C3

(3.18)

3.5.2 Programmable Gain Stage Implementation Figure 3.12 shows the architecture of the programmable gain stage. It consists of two finite-gain compensated SC amplifiers operating in complementary clock phases.

3.5 Programmable Gain Stage

33

Fig. 3.12 Programmable gain stage architecture of the 24-channel EEG readout front-end Fig. 3.13 OTA structure of the finite-gain compensated SC amplifier stages

The first stage is implemented with a fixed gain of 20 for the EEG channels. The C2 capacitor of the second gain stage is digitally selectable that allows gain selection between 1 and 50 with 8 different settings. Therefore, the total gain of the channel can be selected between 200 and 10000. The OTA of the SC amplifier are implemented using the current mirror architecture shown in Fig. 3.13. The input pair transistors operate in weak inversion in order to maximize their transconductance and reduce the time constant of the amplification and sampling phases. The transconductance of the OTA is 21.5 µS, hence, the worst case time constant of the SC amplifier appears as 20 µs for the second SC am-

34


plifier stage with the gain setting of 50. The amplification time of the SC amplifier stages is selected as 140 µs, equivalent to 7τamp . Therefore, the operating frequency of the amplifiers is 3.125 kHz.

3.6 Test Results The presented 24-channel EEG readout front-end ASIC is implemented in 0.5 µm double-poly triple-metal CMOS process. Figure 3.14 shows the photo of the ASICs on 6-inch wafer. The total area of the ASIC measures 7.5 mm by 8.2 mm. In order to verify the operation of the 24-channel EEG readout front-end ASIC, a test setup has been prepared. Two Ag/AgCl cup electrodes are placed on the skull of a subject at the locations O1 and O2 (occipital cortex) in accordance with [12], Fig. 3.15. These electrode are connected to the inputs of the two channels of the 24-

Fig. 3.14 Photo of several 24-channel EEG readout front-end ASICs on 6-inch wafer. ASIC is implemented in 0.5 µm three-metal double-poly CMOS process through AMIS

Fig. 3.15 Extracted EEG signals and their STFT from the two electrodes connected to the occipital cortex of a subject (locations of the electrodes are indicated on the left)

3.6 Test Results 35

36


Table 3.2 Performance summary of the 24-channel EEG readout front-end ASIC Performance Summary Voltage Supply

3V

Current Consumption (24 EEG + ECG Channels)

3.42 mA

Number of Channels (EEG/ECG)

24/1

Input Clock Frequency

32 kHz

Input Common-Mode Range

0.5 V–1.8 V

Output Voltage Swing

0.3 V–2.0 V

Programmable Channel Gain Range (EEG)

200–10000

Programmable Channel Gain Range (ECG)

20–1000

CMRR (with 0 mV Differential Electrode Offset)

107 dB

CMRR (with 50 mV Differential Electrode Offset)

90 dB

Input Ref. Voltage Noise of IA (0.5 Hz–100 Hz)

0.64 µVrms

Input Ref. Voltage Noise of EEG Chn. (0.5 Hz–100 Hz)

120 dB

CMRR (50 mV Differential DC Input Voltage)

>110 dB

PSRR+, PSRR− (@ 50 Hz)

>80 dB, >78 dB

HPF Cut-Off Frequency (Cext2 = 1 µF, Cext2 = 22 nF)

0.30–0.34 Hz, 14.0–15.8 Hz

LPF Cut-Off Frequency Gain = 390

0.65, 0.88, 1.35, 1.85 kHz

Gain = 800

0.4, 0.65, 0.8, 1.2 kHz

Gain = 1550

0.25, 0.34, 0.5, 1 kHz

Gain = 2500 Input Impedance

0.15, 0.23, 0.33, 0.6 kHz >100 M

4.5.3 Biological Test Results Figure 4.17 shows the extracted biopotential signals from the ExG readout frontend ASIC using disposable Ag/AgCl electrodes for the ECG and the EMG signals, and using Ag/AgCl cup electrodes with conductive paste for EEG measurements. It is important to note that no digital signal processing is performed on the extracted biopotential signals. The EEG measurement has been performed on a subject with two electrodes connected to the backside of the head (occipital cortex) and when his eyes are closed. The gain of the front-end is set to 2500 with minimum bandwidth configuration (150 Hz), and the HPF cut-off frequency is set to 0.3 Hz by selecting Cext2 of 1 µF. Figure 4.18 demonstrates that the dominant rhythm of the EEG signal is in the alpha range (8–13 Hz) [10], and there is no sign of 50 Hz. Similarly, the ECG signal is extracted by connecting two electrodes to the chest of the subject and setting the gain of the front-end to 800 and the bandwidth to

Fig. 4.17 Extracted ExG signals from the ExG readout front-end using Ag/AgCl electrodes without digital signal processing. Signals amplitudes are referred to the circuit input

62 Biopotential Readout Front-End ASICs

4.6 Eight-Channel EEG Readout Front-End

63

Fig. 4.18 Spectrum of the extracted EEG signal of Fig. 4.17 from occipital cortex. Patients’ eyes are closed, thus dominant rhythm is in alpha range

400 Hz, and keeping the HPF cut-off frequency at 0.3 Hz. All the characteristics of an ECG signal, the P wave, the QRS complex, and the T wave, are clearly visible without any sign of 50 Hz. Finally, for the extraction of EMG waves, two electrodes are connected to the biceps muscles of the right arm, and gain is set to 400 with LPF cut-off frequency of 650 Hz, and Cext2 is changed by a 22 nF capacitor in order to set the HPF cut-off frequency to 14 Hz. The EMG signal appearing due to the contraction of the biceps muscle is clearly visible at the output.

4.6 Eight-Channel EEG Readout Front-End 4.6.1 Implementation A biopotential readout front-end circuit dedicated to EEG signal extraction is implemented. Figure 4.19 shows the architecture of the eight-channel EEG readout front-end ASIC. The channel architecture of the EEG readout front-end is similar to the architecture of the ExG readout front-end ASIC. Each channel consists of an ACCIA as the preamplifier, a CSF stage to filter the chopping spikes and distortion spikes, and a programmable gain stage to set the gain and the bandwidth of the channel for different applications of the EEG signal analysis. Each channel uses a channel buffer to prevent the kick-back effect of the output analog multiplexer. The analog multiplexer circuit time multiplexes the channels and an output buffer drives the multiplexed signal to the output, so that a single ADC can sample all the channels of the ASIC. The bias circuit of the ASIC not only generates the necessary bias currents for the building blocks of the ASIC, but also generates two reference current sources, from

Fig. 4.19 Architecture of the eight-channel EEG readout front-end ASIC

64 Biopotential Readout Front-End ASICs


65

Fig. 4.20 Die micrograph of the eight-channel EEG readout front-end ASIC implemented in 0.5 µm three-metal double-poly CMOS process through AMIS

which the patient bias (patient ground) and other DC bias voltages of the ASIC can be generated. The on-chip buffers with LPF characteristics are used to buffer and filter the excess noise on these DC voltage levels. All the digital signals of the chip are generated by the on-chip digital control circuit. This circuit accepts a 64 kHz external clock as an input and generates all the necessary timing signals from this single clock input. The presented ASIC has been implemented in 0.5 µm three-metal double-poly CMOS process. Figure 4.20 shows the die micrograph of the eight-channel EEG readout front-end ASIC. The noise and the CMRR performance of the readout channel is defined by the ACCIA, which has been implemented as shown in Fig. 4.2. A more detailed explanation of the design of ACCIA is given in Sect. 4.5.1 for the ACCIA of the ExG readout front-end ASIC, therefore in this section only a brief description will be presented. The voltage gain of the ACCIA is set to 10 by the CBIA architecture shown in Fig. 4.5 by selecting R1 as 100 k and implementing R2 with a nMOS transistor of size 2/255. If the common-mode output voltage level is set to 1.15 V, this transistor implements a 1 M resistor. Table 4.5 shows the dimensions and the operating points of the transistors of the CBIA implementation for the eight-channel EEG readout front-end ASIC. The simulated 1/f noise corner frequency is 60 Hz, thus the chopping frequency of the ACCIA is set to 1 kHz. The simulated bandwidth of the

66

Biopotential Readout Front-End ASICs

Table 4.5 Operating points of the transistors in Fig. 4.5, Fig. 4.6, and Fig. 4.3(b) for the eightchannel EEG readout ASIC Transistors

W/L (µm/µm)

Ids (nA)

gm /Ids (1/V)

Current Balancing IA (CBIA) MR2 , ML2

40/10

500

19.8

MR3 , ML3 , MR4 , ML4

50/4

50

23.7

MR5 , ML5

8/100

400

6.5

MR6 , ML6

12/2

400

21

MR7 , ML7 , CM1 , CM2

24/40

600

7.4

MR8 , ML8

100/2

600

22.3

MR9 , ML9

80/2

100

24.5

MI 1 , McI 1

24/40, 60/4

600

7.4, 19.7

MI 2 , McI 2

4/75, 4/2

200

7.5, 20.1

MI 3 , McI 3

10/75, 10/2

500

7.5, 20.1

MR2

2/255 CBIA Input Stage Transistors

MR1 , ML1

1120/7

600

23.8

MRC1 , MLC1

112/4

600

20.9

MRC2 , MLC2

16/128

100

8.2

GM Stages in the Offset Filter Loop of the ACCIA Mgm1

2.5/160

150

4.85

Mgm2

7.5/160

450

4.71

CBIA is 20 kHz. Similar to the ExG ASIC, the EEG ASIC can also filter ±50 mV differential DC electrode offset voltage. The CSF stage of the each channel operates at 2 kHz with selectable duty cycle of 3.125% or 6.25%. The programmable gain stage has 8 different gain settings between 2000 and 9000. The readout channels of the ASIC needs various bias voltages and bias currents. In battery powered systems, the supply voltage changes as the battery discharges. Therefore, the eight-channel EEG readout front-end ASIC includes a supply independent bias generator circuit, Fig. 4.21. The core of the bias circuit is the reference current generator circuit. The transistors M1 –M4 of the reference current generator operates in weak inversion, therefore the reference current can be expressed as: Iref = n × Vt ×

ln(a) R

(4.28)

where n is the weak inversion slope factor (1.45 for AMIS 0.5 µm CMOS technology [55]) and a is the ratio between the current mirrors. If a 63.4 k resistor is used and the mirroring ratio is 8, the generated reference current is set to 1.2 µA. The negative feedback nature of the reference current generator circuit is also stable while no current passes through its branches. Therefore, a start-up circuit


67

Fig. 4.21 Bias generator circuit of the eight-channel EEG readout front-end ASIC. The supply independent bias circuit generates the bias currents for the channels. The bias buffers filters and buffers the bias voltages

is included, which forces an initial current through the branches of the reference current generator during the start-up. The bias circuit generates eight bias currents for each readout channel of the ASIC. In addition to that, two reference current sources (1 µA source current and 1.2 µA sink current) are generated so that all the bias voltages of the ASIC can be generated from the two sets of external resistors. The voltages that needs to be constant with changing power supply voltage are generated from the source current, where as the voltages that need to be changing together with power supply voltage (e.g. the gate bias of the cascode transistor of the pMOS current sources) are generated from the current sink. Additionally, the bias circuit includes three low power buffer circuits (one of them is a dummy buffer circuit). One of the buffers is used for buffering the patient bias voltage, where as the other is used for filtering the excess noise on the ACCIA_ref voltage (this reference voltage is used in the servo-loop of the ACCIA as shown in Fig. 4.2). Finally, the last building block of the eight-channel EEG readout front-end ASIC is the digital control circuit that generates the necessary digital signals for the readout channels and the analog multiplexer. Figure 4.22 shows the architecture of the digital control circuit of the EEG ASIC. The main function of the digital control circuit can be summarized as follows; the non-overlapping clock generator circuit generates the complementary clock signals at 1 kHz for the chopper switches of the ACCIA. Based on the select chn sampling rate, the sampling frequency of each channel can be selected to be 1 kHz/chn or 2 kHz/chn. The sample signal of the first channel is also an output signal, so that an ADC that is connected to the output of the ASIC can use it to synchronize its sampling instant with the internal sampling of the ASIC. The combinational logic circuit generates the CSF stage clock from the output of the frequency divider. The frequency of the CSF clock is 2 kHz with externally selectable duty cycle of 3.125% or 6.25%. Finally, the digital control circuit controls the gain and the bandwidth switches of the readout channels depending upon 2-bit

68


Fig. 4.22 The architecture of the digital control circuit of the eight-channel EEG readout front-end ASIC

Select BW and 3-bit Select Gain digital input signals. Table 4.6 gives the current consumptions and the operating conditions of the each block of the eight-channel EEG readout front-end ASIC.

4.6.2 Measurement of Performance Figure 4.23 shows the gain and the bandwidth plot of the ACCIA. Measurement has been taken after the CSF stage. If neither the chopping nor the CSF stage is active, the gain of the ACCIA is 10 and the LPF cut-off frequency is 16 kHz. If only chopping is activated, the gain of the ACCIA is reduced due to the distortion spikes at the output of the ACCIA. This gain reduction can be calculated from (2.17) as 4% (τ = 1/(2π16 kHz) and fchop = 1 kHz), which matches perfectly with the measured reduction in the gain. After CSF stage is activated, this gain reduction is fully restored since the CSF stage filters the distortion spikes. If Cext2 is 1 µF, the HPF cut-off frequency appears at 0.2 Hz. Figure 4.24 shows the time-domain comparison of the output of the ACCIA, while the CSF stage is active with 3.125% duty-cycle, and while it is disabled. The distortion spikes are successfully filtered by the CSF stage. Similar to the distortion spikes, another test is performed to demonstrate the operation of the CSF stage on the chopping spikes by shorting the inputs of the ACCIA. Figure 4.25 demonstrates that CSF stage can also filter the chopping spikes generated due to the charge injection from the input chopper switches. Figure 4.25 also demonstrates the operation of the servo-loop implemented with OTA1 -Cext1 in Fig. 4.2, whose purpose is to filter the offset of the CBIA. The loop successfully filters the offset of the CBIA, the modulated output offset of the CBIA is only 300 µV, which states that the input referred


69

Table 4.6 Summary of the building blocks of the eight-channel EEG readout front-end ASIC Readout Channel BWACCIA fchop Av,ACCIA Current Consumption Input Ref. Noise Density NEF

AC Coupled Chopped IA (ACCIA) 20 kHz 1 kHz 10 6.25 µA√ 75 nV/ Hz 9.3

fCSF Duty Cycle (m) Current Consumption

Chopping Spike Filter (CSF) 2 kHz 3.125%, 6.25% 0.4 µA

Programmable Gain Current Consumption

Programmable Gain Stage 200, 300, . . . , 800, 900 0.7 µA and 0.38 µA

3 V gate bias

1-bit digital input

3-bit digital input Fixed Gain Stage and VGA

Channel Buffer Current Consumption

0.8 µA Buffers and Bias Circuit

Output Buffer Current Bias Buffers Bias Circuit

3.6 µA 3 × 0.6 µA 10.7 µA Digital Control Circuit

Clock Frequency

64 kHz Complete ASIC

Total Current Consumption Operating Voltage

92.6 µA 2.7–3.3 V

offset voltage of the CBIA is only 30 µV, thanks to the servo-loop implemented by the OTA1 -Cext1 . Figure 4.26 shows the input referred voltage noise PSD measurement of the ACCIA with and without chopping. The 1/f noise corner frequency of the ACCIA is reduced to 2 Hz, when chopping is activated, otherwise 1/f noise corner frequency is 60 Hz. √ The input referred voltage noise level of the ACCIA is measured to be 75 nV/ Hz. The residual 1/f noise is due to the OTA2 -Cext2 filter in Fig. 4.2, and has negligible effect to the total noise of the ACCIA. The total integrated input referred voltage noise is 0.78 µVrms between 0.5 Hz and 100 Hz, when chopping is

70


Fig. 4.23 Gain and bandwidth of the ACCIA of the eight-channel EEG ASIC. The gain of the ACCIA is reduced according to the (2.17) while chopping is active and CSF stage is disabled. After CSF stage is activated (3.125% duty cycle) the gain of the ACCIA is restored

Fig. 4.24 Comparison of the output of the ACCIA for a 20 mVpp sine wave input while CSF stage is active with 3.125% duty-cycle and while it is disabled

active, and 1.23 µVrms , when chopping is disabled. Therefore, the improvement of noise with chopping is more than 35%. All the bias voltages are generated from the reference source current and sink current outputs by using off-chip resistors. Figure 4.27 shows the test of the supply independent bias generator circuit. The supply voltage is changed from 2.7 V to 3.3 V. The voltages generated from the source current output are constant in the whole range of the supply voltage, where as the voltages generated from the sink current output follow the change in the supply voltage. The total supply current of


71

Fig. 4.25 Comparison of the output of the ACCIA while the inputs are shorted. The CSF stage can completely filter the chopping spikes due to the charge injection from the input chopper switches

Fig. 4.26 Comparison of the measured noise of the ACCIA with and without chopping. Chopping reduces the 1/f noise corner frequency from 60 Hz to 2 Hz

the ASIC is measured to be 95 µA, which only changes less than 2% in the specified supply voltage range. Figure 4.28 shows the output of the ASIC for a common-mode sine wave input of 750 mVpp at 50 Hz, where the channel gain is set to 9000. The CMRR of the readout channels of the ASIC is better than 130 dB at 50 Hz. Finally, Fig. 4.29 shows the variation of the output offset voltage for the each channel of the ASIC. The maximum deviation is less than 10 µV, when referred to the input of the channels. Table 4.7 summarizes the measured performance of the ASIC.

4.6.3 Biological Test Results In order to verify the operation of the EEG ASIC with real EEG signals, a test setup has been prepared. Eight Ag/AgCl cup electrodes are placed on the skull of a subject

72


Fig. 4.27 Total supply current of the ASIC, and change of supply current and bias voltages with changing supply voltage

Fig. 4.28 Output of the ASIC for a common-mode input sine wave of 750 mVpp at 50 Hz. Channel gain is 9000 during the measurement

at the locations O1, O2: occipital cortex, P3, P4: parietal cortex, C3, C4: central, F3, F4: frontal cortex in accordance with [12]. These electrodes are connected to the eight channel inputs of the ASIC. The patient bias voltage, which is generated from the on-chip source current and buffered by the on-chip buffer (see Fig. 4.21), is connected to the Gnd electrode located on the top of the subject’s skull aligned with the longitudinal fissure of the brain. The reference electrode is connected to


73

Fig. 4.29 Deviation of the output offset voltage of the channels of the eight-channel EEG readout front-end ASIC. Maximum deviation is less than 10 µV, when referred to the input of the channels Table 4.7 Performance summary of the eight-channel EEG readout front-end ASIC Performance Summary Voltage Supply

2.7 V–3.3 V

Current Consumption

95 µA

Input Common Mode Range

1.05 V–1.7 V

Electronics Gain Selection (ACCIA Gain = 10)

2000, 3000, . . . , 9000

Continuous Gain Adjustment

via R2

Input Referred Voltage Noise Density

75 nV/sqrt (Hz)

CMRR

>130 dB

HPF Cut-Off Frequency (Cext2 = 1 µF)

0.2 Hz

Input Impedance (signal input)

>500 M

Offset Deviation of the Channels (Input Referred)

86 dB

105 dB

>120 dB

>130 dB

Input Impedance

100 M

Larger

>7.5 M

>100 M

>500 M

HPF −3 dB Cut-Off

I1

(5.7)

Thus, the output of the differential amplifier is zero, as long as the output of the buffer is close to the input. Therefore, transistors M3 and M4 are OFF and no current is mirrored to increase tail current of the buffer. In this state, the circuit acts as a simple buffer with constant tail current source. If the difference between the input and the output exceeds the limit given by: I2 V = n × Vt × ln (5.8) I2 − I1

86

A Complete Biopotential Acquisition ASIC

where n is the weak inversion slope factor, then the gate voltage of either M3 or M4 increases, creating a large current that increases the tail current of the input transistors. Therefore, both the bandwidth and the output current drive capability of the buffer circuit increase. An important factor for the design of the tail current boost circuit is the ratio I2 /I1 . This ratio must be large enough so that the offset voltage of the buffer can not falsely activate the tail current boost circuit. On the other hand, increasing the ratio further makes the tail current boost circuit being turned off, while the buffer circuit is still slewing. Hence, the standard deviation of the input referred offset voltage of the buffer, σin,offset , is calculated as 4.3 mV. Therefore, the ratio I2 /I1 is set to 1.5, which sets the turn on voltage of the tail current boost circuit to 40 mV according to (5.8). The designed buffer circuit has a −3 dB cut-off frequency of 2.6 MHz and 230 kHz under no load and with 25.6 pF capacitive load (in addition to the 4 pF compensation capacitor), respectively. The positive and the negative slew rates of the class-AB buffer are 2.5 V/µs and 2.25 V/µs with 25.6 pF load, respectively. The input-output voltage swing of the buffer is between 0.3 V and 2.1 V. The class-AB buffer can settle from 0.3 V to 2.1 V in 2.2 µs with 0.1% precision and from 2.1 V to 0.3 V in 5.1 µs, with 25.6 pF load. The quiescent current consumption of the class-AB buffer circuit is 10 µA and 95% of this current consumption can be duty cycled by using the power switches. Under no load condition, the power-on time of the class-AB buffer is less than 1 µs. This class-AB buffer is used to buffer the ADC reference voltage and the multiplexed readout front-end output.

5.5 ACCIA with Coarse-Fine Servo-Loop 5.5.1 Structure of the ACCIA Defining the noise and the CMRR performance of the channel, and filtering the differential DC electrode offset, the ACCIA is the most important and power consuming building block of a readout front-end channel. The noise-power efficiency calculation of the ACCIA architecture of the previous Chapter is presented in Sect. 4.2.3. The calculation is based on the assumption that an input stage transistor of the CBIA is using only the 1/6 of the total current consumption of the ACCIA. Considering that the NEF of the ACCIA is proportional with the current passing through the input transistors, increasing the ratio of the current passing through the input transistors can improve the NEF of the ACCIA (due to the improved thermal noise). On the other hand, the maximum differential DC electrode offset filtering capability of the ACCIA, which is defined by (4.8), states that higher the current consumption of the transconductance stage, the higher the electrode offset filtering limit of the ACCIA. Therefore, there is a contradiction between the maximum allowed differential DC electrode offset voltage and the noise-power efficiency of the ACCIA architecture of Sect. 4.2.

5.5 ACCIA with Coarse-Fine Servo-Loop

87

Possible solutions for improving the NEF of the ACCIA can be: • Decreasing the current consumption of the gm1 and the gm2 stages of Fig. 4.2. • Increasing the current mirroring ratio of the current mirrors CM1 and CM2 . • Implementing the gm1 and the gm2 stages of Fig. 4.2 with pMOS transistors that replaces the current sources I1,1 and I1,2 in Fig. 4.2. The consequences of these solutions are: • The maximum allowed differential DC electrode offset voltage that can be filtered by the ACCIA decreases. • The contribution of the input pair transistors of the gm1 and the gm2 stages to the total noise of the amplifier increases, which increases NEF. • Input voltage swing of the ACCIA decreases considerably, and the sensitivity of the CMRR to the differential DC electrode offset voltage increases, due to the fact that under DC differential electrode offset, the transistors of the gm stages will be operating with different quiescent operating point. Hence, the CMRRgo term of (3.10) is reduced considerably. As a result, in an attempt to decrease the NEF of the ACCIA, the servo-loop that implements the HPF characteristics to the ACCIA is modified as shown in Fig. 5.5. The gm2 stage of Fig. 4.2 is decomposed into two parts, namely, the coarse transconductance (CGM) and the fine transconductance (FGM) stages. These two transconductance stages simulates the operation of the gm2 stage of Fig. 4.2. The operation of the FGM is same as the gm2 stage of Fig. 4.2, however, FGM stage consumes much less current. Therefore, the FGM can supply enough current difference between its output branches to filter only ±Vfilter,fine differential DC electrode offset voltage, which is defined by: Vfilter,fine =

|Ifine,L − Ifine,R | Ifine × M × R1 = R1 2 2

(5.9)

where M is the ratio of the current mirrors in the FGM. Meanwhile, the CGM checks whether the FGM has reached its limit by using two comparators. If the input of the FGM reaches to the top limit, VH , the thermometer code counter counts up. Else if the input of the FGM stage reaches to the bottom limit, VL , the thermometer code counter counts down. Therefore, in the former case, a current DAC bit is steered to increase IL by IDAC , and decrease IR by IDAC , whereas, in the latter case the opposite steering of the current DAC occurs. The steering of the single-bit current DAC from left to right or from right to left can create 2 × IDAC current difference between its output branches, which can filter ±Vfilter,DACbit differential DC electrode offset voltage that is defined by: Vfilter,DACbit = IDAC × R1

(5.10)

Therefore, the complete CGM can filter ±Vfilter,coarse that is defined by: Vfilter,coarse = mDAC × Vfilter,DACbit where mDAC is the number of bits of the current DAC.

(5.11)

88


Fig. 5.5 The operational principle of the ACCIA with coarse-fine servo-loops that implements HPF characteristics to the CBIA

As a result the maximum differential DC electrode offset that can be filtered by the ACCIA structure can be found by adding (5.9) with (5.11) assuming that the thermometer code counter has reached to its limit:


Velec-off ,max = Vfilter,fine + Vfilter,coarse Ifine × M + mDAC × IDAC × R1 = 2

89

(5.12)

An example behavior of the fine-coarse servo-loop under changing differential DC electrode offset voltage of the biopotential electrodes is described in Fig. 5.6. The main purpose of the servo-loop is to supply the current through R1 due to the differential DC electrode offset voltage, so that no current is supplied by the core CBIA and output is nulled. In the beginning, the CGM stage steers its current output such that the remaining necessary current difference can be adjusted by the FGM stage. As soon as, the remaining necessary current difference falls into this range, the VINT,OUT decreases from VH limit. Therefore, from this moment on the CGM stage sustains its output current difference. Meanwhile, the FGM stage adjusts its output such that (IL − IR ) equals to Velec-off /R1 . Therefore, at this instance, all the necessary current through R1 is supplied by the servo-loop, and the differential DC electrode offset is rejected by the ACCIA. As the electrode offset voltage of the biopotential electrodes drifts, the FGM stage adjusts its output till the point, where VINT,OUT reaches either VH or VL . At this instant, the CGM stage senses this and adjusts its output. Later, the FGM stage adjusts itself to the change in the CGM stage. As a result, all the necessary current through R1 due to the input differential DC electrode offset voltage can be supplied by the fine-coarse servo-loop. An important consideration of the fine-coarse servo-loop design is to prevent the saturation of the FGM stage. Therefore, VH and VL voltages must be selected such that the CGM stage should update its output before the FGM stage saturates. In such a situation, the HPF cut-off frequency of the ACCIA, fHP,ACCIA , is defined by the

Fig. 5.6 Illustration of the fine-coarse servo-loop operation with changing input differential DC electrode offset voltage of the biopotential electrodes

90


FGM stage. Therefore, fHP,ACCIA can be written using (4.4) as: fHP,ACCIA = [gm,fine · M · Av,INT ] × [R2 · A] × fLP,INT

(5.13)

where gm in (4.4) is replaced by Av,INT × gm,fine × M, and R2 is replaced by R2 × A. Av,INT and fLP,INT are the open-loop DC gain and the LPF cut-off frequency of the integrator stage. M and gm,fine are the current mirror ratio of the FGM stage and the transconductance of the input pair transistors, respectively. A is the gain of the second gain stage of the ACCIA.

5.5.2 Coarse Transconductance (CGM) Stage 5.5.2.1 Functional Block Diagram Figure 5.7 shows the implementation of the CGM stage. The counter of the CGM stage is reset after the power-on of the ASIC. This sets the output of the 4-bit binary counter to (1000)2 , which is the mid-level for the counter, and sets half of the current DAC bits to state 1 and other half to state 0. Therefore, IDAC,L equals to IDAC,R just after the reset. The operation of the CGM stage is controlled by three clock signals, compRST, compPOWER, and checkCLK. The comparators of the CGM stage are powered on

Fig. 5.7 Schematic and operation principle of the Coarse Transconductance (CGM) stage


91

with the compPOWER. A delay time is introduced between the compPOWER and compRST so that the transistors of the comparators settle to their quiescent operating points before the comparator decision. Together with the compRST, the two comparators check whether the output of the source follower is between VH and VL . If it is below VL or above VH then the output of the bottom or the top comparator goes high, respectively, which makes the counter to count. Meanwhile, a NAND gate and an OR gate check whether the counter has reached its limit, and prevent the transition of the counter from (0000)2 to (1111)2 or from (1111)2 to (0000)2 . The binary-to-thermometer code converter converts the output of the counter to thermometer code for the control of the current DAC bits. A 1-bit increase/decrease in the counter results in 2 × IDAC change for IDAC,L − IDAC,R . Therefore, each bit of the counter can steer enough current to cancel IDAC × R1 of the differential DC electrode offset of the biopotential electrodes. 5.5.2.2 Current DAC Architecture Figure 5.6 gives an example behavior of the fine-coarse servo-loop assuming that the current DAC is implemented using a conventional DAC architecture, where the steering of the DAC is instantaneous. Therefore, after the DAC steers its output, the total current (IL − IR ) is not equal to what is necessary to filter the input differential DC electrode offset voltage, since integrator output is at its limit prior to the steering. Hence, the integrator has to adjust its output so that (IL − IR ) will be set to what is necessary to filter the input differential DC electrode offset voltage. However, due to the large time constant of the integrator stage, an artifact will occur at the output of the ACCIA, when the integrator stage is adjusting its output. Therefore, a conventional DAC architecture is not convenient for the CGM stage. Figure 5.8 shows the proposed architecture of a single bit of the current DAC. The main difference between a conventional DAC and the implemented DAC is the change of the output current. On the contrary to a conventional DAC, the output current of this implementation steers slowly. This is due to the fact that the gates of the transistors, M1 and M2 , are connected to the output of a LPF that is implemented with pMOS transistors operating in OFF state and a load capacitor. Therefore, any fast voltage change at the input of this LPF will be filtered by the time constant of the LPF stage. The OFF state pMOS transistors can be modeled with two PNP bipolar transistors. When the input of the LPF filter switches from the supply voltage to Vcas the load capacitor is discharged by the base-emitter reverse bias leakage current of Q1 and the base-to-body leakage current. On the other hand, when the input switches from Vcas to VDD, the load capacitance is charged only by the base-emitter reverse bias leakage current of Q2 , and the base-to-body leakage is compensated by the base-emitter forward bias current of Q1 . Therefore, the rate of voltage change at the gates of the transistors M1 and M2 can be given as: Icharge /CnMOS ⇔ input(Vcasp to VDD) ∂Vg1,g2 (5.14) = ∂t (Idischarge + Ibase-to-body )/CnMOS ⇔ input(VDD to Vcasp )

92


Fig. 5.8 Architecture and operating principle of the current DAC that has slowly varying current output

where Icharge and Idischarge are defined by the BE reverse bias leakage of the bipolar transistors. Hence, the discharge of the load capacitance will be faster than the charging due to the fact that the total discharging current of the load capacitance is larger than the charging current by Ibase-to-body . The operation of this current DAC implementation can be described as follows: When Qn changes from 1 to 0, the input of the left LPF switches from Vcasp to supply voltage, and the input of the right LPF switches from supply voltage to Vcasp . Therefore, the gate voltage of the transistors M1 and M2 increases and decreases with slope given in (5.14), respectively. As a result, the current is steered slowly from left to right. The target is to make the time constant of the output current change much smaller than 1/(2πfHP,ACCIA ) so that the artifact of the current DAC is suppressed. Then, the operation of the fine-coarse servo-loop can be illustrated as in Fig. 5.9, which describes that fine-coarse servo-loop can continuously supply the necessary current to filter the DC differential electrode offset voltage of the biopotential electrodes.

5.5.2.3 Latched Comparator The CGM stage uses a static latched comparator as shown in Fig. 5.10 [72]. It consists of a differential input stage, a current mirror, and a regenerative active load.


93

Fig. 5.9 Illustration of the fine-coarse servo-loop operation, which uses a current DAC in the CGM stage having a large time-constant while steering its outputs

Fig. 5.10 Comparator schematic of the Coarse Transconductance stage

The signal compPOWER enables or disables the tail current of the input differential stage. Therefore, when compPOWER is low the comparator consumes no current. When compPOWER goes high the differential input voltage creates a current difference between the drain currents of the input pair transistors. This current difference is mirrored to the regenerative active load. During compRST is high, the comparator is in reset mode, and output is set to zero. When the compRST goes low, the active load creates virtually infinite gain, due to the regenerative process. This yields rapid amplification of the signals to the logic levels [72]. The main advantage of this comparator is its low kick-back noise. Since the input differential stage and the regenerative active load is isolated from each other with

94


Fig. 5.11 Schematic of the Fine Transconductance (FGM) stage

the current mirrors, the regeneration process has minimal effect on the inputs of the comparator [73]. The static power consumption of this architecture is not important since the tail current of the input differential stage is duty-cycled, and the power-on time is negligible (1 ms/300 s). Therefore, the average current consumption of this comparator is nearly zero, when it is used in the CGM stage. The implemented comparator consumes 500 nA when it is ON. The start-up time of the comparator is 2.5 µs, and it can resolve 1 mV differential input in less than 1 µs. Therefore, the delay of 62.5 µs between the clock signals of the CGM stage (see Fig. 5.7 for the clock signals of the comparator) is a very relaxed number that assures the proper operation.

5.5.3 Fine Transconductance (FGM) Stage The architecture of the FGM stage is very similar to the architecture of the gm2 stage of Fig. 4.2. Figure 5.11 shows the schematic of the FGM stage. The source follower of the FGM stage has the same size with the source follower of the CGM stage. Therefore, the output of the two source follower stages match. The nMOS differential pair transistors compare the output of the source follower with a reference voltage. Based on the source follower voltage, a current difference, (Ifine,L − Ifine,R ) is created and mirrored to the terminals of R1 of the CBIA. The tail current of the differential pair transistors is 100 nA and the current mirroring ratio between the current mirrors is 2. The differential pair transistors of the FGM stage is designed in deep strong inversion to minimize their noise contribution. The transconductance of the input differential pair transistors is 210 nS.

5.5.4 Integrator Stage The purpose of the integrator stage is to filter the output of the ACCIA such that only the signals below the cut-off frequency of the integrator, fLP,INT , are amplified.


95

Fig. 5.12 Schematic of the integrator stage

Therefore, both the CGM and the FGM stages can use the output of the integrator to set their outputs for filtering the differential DC electrode offset of the biopotential electrodes. Figure 5.12 shows the schematic of the integrator stage. The integrator characteristics are implemented using a differential amplifier, two resistors that are implemented with diode connected pMOS transistors operating in subthreshold region as in [74], and two capacitors. The transfer function of the integrator can be written as: Av,INT (s) =

Aopen-loop sRpMOS CLPF Aopen-loop + 1

(5.15)

where Aopen-loop is the open-loop DC gain of the differential amplifier. Hence, the integrator cut-off frequency can be given as: fLP,INT =

1 2πRpMOS CLPF Aopen-loop

(5.16)

The large time constant of the circuit can be reduced for the fast start-up of the circuit, which will be described in the later Sections. The implemented integrator stage has an open-loop DC gain of 77 dB and the total input referred noise is 50 µVrms . The total current consumption of the integrator stage is 50 nA.

5.5.5 Current Balancing IA (CBIA) Architecture The CBIA of the ACCIA is implemented as in Fig. 4.5 with some minor changes for decreasing the power dissipation and further improving the NEF of the ACCIA. Figure 5.13 shows the schematic of the CBIA. One of the main difference of this

96


Fig. 5.13 Schematic of the Current Balancing Instrumentation Amplifier (CBIA) of the ACCIA with fine-coarse servo-loop

CBIA implementation with the CBIA implementation of Fig. 4.5 is the elimination of the CMFB circuit for saving power. Instead, the second gain resistor is used for sensing the common-mode level of the output and this voltage is used to control the current through the transistors ML5 and MR5 . Similar to the previous implementation, the input stage of the CBIA uses the structure shown in Fig. 4.6 so that the CMRR of the ACCIA circuit will be resistant to increasing input DC differential electrode offset voltage of the biopotential electrodes. Table 5.1 shows the dimensions and the operating points of the transistors of the implemented CBIA circuit. The total current consumption of the CBIA circuit is 1.95 µA, and 1.8 µA of it is supplied by the FGM and CGM stages. Therefore, nearly all of the tail current of the CBIA stage can be used to filter the differential DC electrode offset voltage. Another important change of this CBIA implementation is the minimized current consumption of the transistors ML2 and MR2 , so that most of the current is utilized by the input pair transistors for decreasing the noise of the CBIA. The input transistors of the CBIA circuit consumes 1.5 µA of the total supply current. R1 of the CBIA is selected as 50 k so that 1/R1 is smaller than gm,M1 . Therefore, the noise of the CBIA can be minimized as explained in Sect. 4.2.3. R2 is implemented by four pMOS transistors of size 1.2/45. If the gate of the nMOS transistors are connected to 200 mV, the equivalent resistance is set to 2 M, setting the gain of the CBIA to 40. The compensation capacitance of the architecture is 0.7 pF, which sets fLP,CBIA to 40 kHz according to (4.13).


97

Table 5.1 Operating points of the transistors in CBIA implementation of Fig. 5.13 Transistors

W/L (µm/µm)

Ids (nA)

gm /Ids (1/V)

Current Balancing IA (CBIA) MR2 , ML2

10/2.5

MR3 , ML3 , MR4 , ML4 MR5 , ML5

150

22.1

8/4

25

21.9

6/200

750

2.8

MI 1 , Mcasp

2/100, 4/4

50

4.6, 18.9

MI 2

4.5/100

150

8.0

MILVL

2/200

25

4.6

MR2

1.2/45 CBIA Input Stage Transistors

MR1 , ML1

1120/7

750

23.4

MRC1 , MLC1

112/4

750

21.8

MRC2 , MLC2

16/128

50

11.1

5.5.6 Gain Stage A separate gain stage is implemented after the CBIA in order to increase the gain of the ACCIA architecture. The main reason behind dividing the gain of the ACCIA into two stages is to eliminate the servo-loop OTA1 -Cext1 and gm1 of Fig. 4.2 that filters the offset voltage of the CBIA. If the second gain stage can be AC coupled to the CBIA, then the offset voltage of the CBIA can be rejected. Since the differential input voltage is modulated by the input chopper, it will not be affected by this AC coupling. Figure 5.14 shows the schematic of the AC coupled gain stage. The voltage gain is defined by the transconductance of the input pair transistors multiplied by the drain-to-source resistance of the diode connected load transistors. Thanks to the minimum number of parallel branches, this architecture consumes minimum current and achieves the maximum bandwidth compared to the other differential gain architectures. The implemented gain stage has a differential gain of 5 and achieves 50 kHz cut-off frequency, while consuming 150 nA. The AC coupling of the gain stage is achieved by a RC filter, where the resistors are implemented with diode connected pMOS transistors operating in subthreshold region as in [74]. The start-up switches are also used in this stage in order to decrease the start-up time.

5.5.7 Implementation of the ACCIA The presented ACCIA architecture is implemented as the preamplifier of the analog readout channels of the EEG acquisition ASIC as shown in Fig. 5.1. fHP,ACCIA of

98


Fig. 5.14 Schematic of the gain stage of the ACCIA implementation

the ACCIA can be calculated by combining (5.13), (5.15) and (5.16) as: fHP,ACCIA =

Mgm,fine R2 A 4.2 = 2πRpMOS CLPF 2πRpMOS CLPF

(5.17)

Since it is not possible to reliably set the value of the RpMOS , on-chip digital trimming of the RpMOS is implemented via changing the number of series and/or parallel transistors. The aim is to set fHP,ACCIA lower than 0.5 Hz so that the back-end stages can effectively set it to the generally desired frequency 0.5 Hz for EEG applications. The chopping frequency of the ACCIA is selected considering the bandwidth of the CBIA and the differential gain stage. The bandwidth of the CBIA and the gain stage combination is simulated as 28 kHz, and the 1/f noise corner appears at 280 Hz. Therefore, the chopping frequency is selected as 2 kHz, so that Sin,total of the ACCIA will be only 1.1 × S0 according to (2.11), where S0 is the input referred thermal noise PSD of the ACCIA. This translates into only 6% increase of the input referred voltage noise from the thermal noise level of the ACCIA. Another important consideration is setting the VH and VL limits of the CGM stage, so that the FGM stage operates in its linear transconductance range, which is designed as ±4 mV. At 4 mV differential input, the current difference between the input pair transistors of the FGM stage is 80 nA. Since, the current mirror ratio is 2, 80 nA current difference in the differential pair, results in (Ifine,L − Ifine,R ) of 160 nA. Therefore, the output current difference of the FGM stage is sufficient to filter ±4 mV of the input DC differential electrode offset voltage of the biopotential electrodes (Refer to (5.9)). The reference voltage of the FGM stage is selected as 1.8 V, and VH and VL are set to 2.2 V and 1.4 V, respectively. This means that as soon as the FGM is set to filter ±4 mV differential electrode offset voltage, the CGM stage updates its output, which supplies enough current difference to filter ±5 mV differential electrode offset voltage (Refer to (5.10)). Therefore, as the CGM stage changes its output, the FGM stage is set to filter the remaining ∓1 mV of the differential DC electrode offset voltage.


99

Fig. 5.15 Circuit configuration for the fast start-up of the ACCIA

As a result, considering the fine-coarse operation of the servo-loop, the maximum allowed differential DC electrode offset voltage is set to ±45 mV, where ±40 mV can be filtered by the CGM and ±5 mV can be filtered by the FGM.

5.5.8 Fast Start-Up of the ACCIA An important concern for the ACCIA is the start-up. After the power-on of the ASIC, the counter of the CGM stage is set to the mid-range so that (IDAC,L − IDAC,R ) of the current DAC in Fig. 5.5 is zero. For a worst case scenario, the input DC differential offset voltage of the electrodes can be ±45 mV, which means the counter of the CGM stage has to count up/down to 1111/0000. Considering the timing of the CGM stage as shown in Fig. 5.7, this will take more than 40 minutes for the ACCIA to start extracting the EEG signals. In order to reduce the waiting time before starting to extract the biopotential signals, the ACCIA can be set to fast START UP mode after the power-on of the ASIC. Figure 5.15 describes the circuit configuration for the fast START UP of the ACCIA. In this mode, following changes occur in the architecture of the ACCIA: • The transition of the current DAC of the CGM stage is fast, since the pMOS OFF transistors in Fig. 5.8 are turned ON. • The subthreshold transistors of the integrator stage in Fig. 5.12 are bypassed by the switches, and the input of the integrator stage is disconnected from the output of the ACCIA and connected to the Voutp,START and Voutn,START outputs of the

100


CBIA. The CINT of the integrator stage and the output resistance of the nodes Voutp,START and Voutn,START set the dominant pole and ensures stability. • The subthreshold transistors of the gain stage in Fig. 5.14 are shorted by switches. Therefore, all the high impedance nodes of the ACCIA architecture are shorted to the low-impedance nodes by switches. As a consequence, the steering of the DAC can be fast, since the FGM stage can immediately adjust its output to the change of the CGM stage. Therefore, the TCGM of the CGM stage in Fig. 5.7 can be decreased down to 10 ms, which improves the worst case start-up time of the ACCIA from 40 minutes to less than 100 ms.

5.5.9 Power-Noise Performance of the ACCIA The main reason for splitting the servo-loop of the ACCIA as fine and coarse servoloops is to improve the power-noise performance. Figure 5.16 shows the equivalent circuit for the input referred noise calculation of the ACCIA with the coarse-fine servo-loop. Using this circuit the total input referred voltage noise PSD can be written as: v2in,ACCIA = v2in,CBIA + + v2in,FGM

v2in,GS A2v,CBIA

2 gm,I DAC + mDAC v2in,DACbit g12

(M × gm,fine )2 g12

+ v2in,LPF

A2v,CBIA

1 × A2v,GS

(5.18)

where mDAC is the number of bits of the current DAC of the CGM stage, gm,IDAC is the transconductance of the current source of the each bit of the current DAC, and gm,fine is the transconductance of the differential pair of the FGM stage. The values of Av,CBIA , Av,GS , M, mDAC , g1 , gm,IDAC , and gm,fine are 40, 5, 2, 16, 20 µS, 460 nS,

Fig. 5.16 Equivalent circuit for calculating the noise of the ACCIA with fine-coarse servo-loop


101

and 210 nS, respectively. Therefore, the total input referred voltage noise PSD of the ACCIA can be approximated as: v2in,ACCIA ∼ = v2in,CBIA,thermal

(5.19)

where v2in,CBIA,thermal is the thermal noise component of v2in,CBIA . It is important to note that although the FGM and the CGM stages are outside the choppers, i.e. their 1/f noise will not be eliminated by the chopper modulation technique, the noise components v2in,DACbit and v2in,FGM will be negligible, when they are referred to the input of the ACCIA. This is due to the fact that gm,fine and gm,DACbit are much smaller than g1 . In addition, the size of the current source transistors of the current DAC are maximized. The v2in,CBIA,thermal of the CBIA can be calculated from (4.15), which results a NEF of (4.21). Therefore, the NEF formula of the ACCIA with the coarse-fine servo-loop is same with the NEF formula of the ACCIA of Sect. 4.2 and can be expressed as: n 1 2Itot NEF = + (5.20) gm,M1 Vt 2 2 Up to this point everything looks similar to the ACCIA of Sect. 4.2. Knowing that M1 operates in weak inversion, the transconductance, gm,M1 , can be written as Ids /(nVt ) and Itot can be calculated by adding the current consumption of the building blocks. The current consumption of the FGM, CGM, gain stage, integrator, and CBIA are 137.5 nA, 37.5 nA, 150 nA, 50 nA and 1.95 µA, respectively. (The current consumption of the current DAC is included in the CBIA stage current consumption.) Considering that current passing through an input transistor of the CBIA is 750 nA, then Ids of the CBIA can be defined as 1/3 of the total ACCIA current. This yields: n 1 + = 3.25 (5.21) NEF = 6n 2 2 Hence the minimum achievable NEF of the ACCIA with coarse-fine servo-loop is improved compared to the ACCIA of Sect. 4.2, where the improvement is approximately equivalent to 2 times reduction in the current consumption at the same noise level. As a summary, the main advantage of the coarse-fine servo-loop of the ACCIA is that the tail current of the CBIA can be more efficiently used for filtering the electrode offset voltage. Therefore, less current is necessary for the building blocks that implements HPF characteristics to the CBIA. Hence, the NEF can be considerably improved compared to the NEF of the ACCIA of Sect. 4.2.

102


Fig. 5.17 Input referred voltage noise density measurement of the ACCIA with coarse-fine servo-loop

5.5.10 Measurement of Performance Figure 5.17 shows the measured input referred voltage noise density √ of the ACCIA with coarse-fine servo-loop. The thermal noise level is 55 nVrms / Hz and 1/f noise corner frequency appears at 4 Hz. The chopper modulation technique improves the corner frequency of the 1/f noise from 80 Hz down to 4 Hz. The residual 1/f noise is due to the unchopped FGM and CGM stages. Figure 5.18 shows the measured transfer function of the ACCIA. The gain of the IA is slightly higher than the design value of 200. This can be expected since the gain of the IA is defined by the ratio of a hipo resistor and the resistance implemented by pMOS transistors operating in linear region. The in-band gain of the ACCIA is 240 and the HPF cut-off frequency appears at 0.1 Hz which is set by the FGM stage. Figure 5.19 shows the CMRR measurement of the ACCIA. The CMRR is higher than 120 dB up to 1 kHz. Therefore, the chopping successfully increases the CMRR of the circuit. Figure 5.20 demonstrates the operation of the coarse-fine transconductance during the START UP mode as described in Sect. 5.5.8. A 20 mVpp triangular wave at 30 mHz is given as a differential input to the circuit, and the VINT,OUT node in Fig. 5.15 is monitored. As soon as the VINT,OUT reaches the upper or the lower limit, the current DAC updates its output setting VINT,OUT between VH and VL . Hence, the CGM stage can successfully adjust its output and prevent the saturation of the FGM stage. Although the DAC transition is FAST during the START UP mode of the ACCIA, it should be SLOW during the normal operation of the ACCIA so that the steering of the DAC does not create any artifact at the output. Figure 5.21 shows the measured


103

Fig. 5.18 The voltage gain measurement of the ACCIA with coarse-fine servo-loop

Fig. 5.19 CMRR measurement of the ACCIA with coarse-fine servo-loop

output current of a single current DAC bit, when it is steering from left to right. The steering of the output current is realized in two phases, phase1 and phase2 , as described in Sect. 5.5.2.2. Phase1 is due to the discharge of the gate M1 from VDD to Vcasp and phase2 is the due to the charging of the gate of M2 from Vcasp to VDD (refer to Fig. 5.8). Although, phase1 is faster than phase2 , it is still much lower than 1/(2πfHP,ACCIA ). Therefore, the artifacts of at the output of the ACCIA due to the steering of the DAC is minimized as it will be demonstrated in Sect. 5.8. An important consideration for the biopotential instrumentation amplifiers is the input impedance since the mismatch between the electrode impedances can reduce

104


Fig. 5.20 The operation of the fine-coarse transconductance stage during the START UP mode of the ACCIA. The differential input to the circuit is a 20 mVpp differential triangular wave at 30 mHz

Fig. 5.21 Steering of a single-bit of the current DAC


105

Fig. 5.22 Input impedance of the ACCIA with coarse-fine servo-loop and the input impedance of the reference input of the EEG acquisition ASIC

the CMRR (refer to (2.3) for detailed description). Figure 5.22 shows the input impedance measurement of the presented ACCIA with coarse-fine servo-loop. The measured input impedance is larger than 1 G indicating that even if there is a 10 k mismatch between the electrode impedances, the CMRR of the readout will be still larger than 100 dB. The same figure also shows the measurement of the input impedance, when eight ACCIA shares an input terminal as a reference input implementation for the eight channel acquisition system (refer to Fig. 5.1). The measured impedance of this input is close to 200 M, which is nearly eight times less than the impedance of a single input. The summary of the measured performance of the ACCIA with coarse-fine servo-loop is given in Table 5.2.

5.5.11 Comparison with State-of-the-Art Table 5.3 compares the performance of the proposed ACCIA with fine-coarse servo-loop with the state-of-the-art for EEG acquisition and with the IFCN standards. The proposed ACCIA is the only IA meeting the requirements of the IFCN standards, except for a slightly elevated total input referred noise. On the other hand, the total integrated input referred noise of the ACCIA is 0.57 µVrms between the frequencies 0.5 Hz and 100 Hz, while consuming 2.3 µA, which translates into the lowest NEF in the literature. It is important to note that the ACCIA with the modified

106


Table 5.2 Performance Summary of the ACCIA with coarse-fine servo-loop Performance Summary Voltage Supply Current Consumption CMRR Voltage Gain Input Referred Voltage Noise (0.5 Hz–100 Hz) HPF Cut-Off Frequency Input Impedance Input CM Range Maximum Allowed Electrode Offset Area Noise-Efficiency Factor (NEF)

2.7 V–3.3 V 2.3 µA >120 dB 240 0.57 µVrms 0.1 Hz 1 G 17 pF 0.85 V–1.8 V ±45 mV 0.45 mm2 4.1

Table 5.3 Comparison of the proposed ACCIA with fine-coarse servo-loop to the state-of-the-art for EEG acquisition. The equivalent −3 dB bandwidth for NEF calculation is 64 Hz (Denison: [36], Harrison: [57], IFCN Standards: [37]) IFCN Standard

Harrison

Denison

ACCIA (ExG)

ACCIA with CoarseFine Servo-Loop

Voltage

–

5V

1.8 V

3V

3V

Current

–

180 nA

1.2 µA

11.1 µA

2.3 µA

Input Ref. Noise (0.5–100 Hz)

110 dB

>86 dB

105 dB

>120 dB

>120 dB

Input Impedance

>100 M

Large

>7.5 M

>100 M

>1 G

HPF −3 dB Cut-Off

1 G

CMRR

>120 dB

HPF cut-off frequency

∼0.1 Hz

Current Consumption

2.3 µA

NEF

200 mV gate bias

4.1 Chopping Spike Filter (CSF)

fCSF

4 kHz

Duty Cycle (m)

6.25%

HPF Cut-Off Frequency

∼0.5 Hz

Current Consumption

0.2 µA

Total current of two CSF stages

Programmable Gain Stage Programmable Gain

16.7, 25, 50

SG1 SG0 = 00, 01(10), 11

Programmable BW (First Pole)

200, 300, 575

SG1 SG0 = 00, SBW1 SBW0 = 11, 01(10), 00

130, 190, 375

SG1 SG0 = 01(10), SBW1 SBW0 = 11, 01(10), 00

70, 105, 210

SG1 SG0 = 11, SBW1 SBW0 = 11, 01(10), 00

Programmable BW (Second Pole)

100, 125, 180, 320

Set by LPF (SBW1 SBW0 = 11, 10, 01, 00)

Current Consumption

0.5 µA

Total of the VGA and the LPF

5.14 Conclusions

133

Table 5.5 (continued) Specification

Value

BW

450 kHz

Current Consumption

0.6 µA

Description

Channel Buffer

Analog Readout Front-End Number of Channels

8

Cur. Consumption of a Readout Chn

3.6 µA

ACCIA + CSF + VGA + LPF + Chn. Buffer

Programmable Gain

4000, 6000, 12000

SG1 SG0 = 00, 01(10), 11

Programmable BW

see Programmable Gain Stage

THD

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