Electrostatic Discharge: Understand, Simulate, and Fix ESD Problems

Electrostatic Discharge

IEEE Press 445 Hoes Lane Piscataway, NJ 08854 IEEE Press Editorial Board Lajos Hanzo, Editor in Chief R. Abari J. Anderson S. Basu A. Chatterjee

T. Chen T. G. Croda S. Farshchi B. M. Hammerli

O. Malik S. Nahavandi M. S. Newman W. Reeve

Kenneth Moore, Director of IEEE Book and Information Services (BIS) Jeanne Audino, Project Editor

Electrostatic Discharge Understand, Simulate, and Fix ESD Problems Third Edition

Michel Mardiguian

A John Wiley & Sons, Inc., Publication

Copyright © 2009 by the Institute of Electrical and Electronics Engineers, Inc. Published by John Wiley & Sons, Inc., Hoboken, New Jersey. All rights reserved. Published simultaneously in Canada. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008, or online at www.wiley.com/go/permission. Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 762-2974, outside the United States at (317) 572-3993 or fax (317) 572-4002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic formats. For more information about Wiley products, visit our web site at www.wiley.com. Library of Congress Cataloging-in-Publication Data is available. ISBN: 978-0470-39704-6 Printed in the United States of America 10 9 8 7 6 5 4 3 2 1

Contents

Preface to the First Edition

ix

Preface to the Third Edition Acknowledgements

xi

xiii

1. The Electrostatic Discharge Phenomenon 1.1. 1.2. 1.3. 1.4.

Physics Involved 1 Influencing Parameters 6 Various Types of Electrostatic Charging with Humans and Objects 9 Statistics of Voltages and Currents Reached During ESD 1.4.1. Personnel ESD Statistics 15 1.4.2. Furniture and Objects ESD Statistics

1.5.

1

Waveforms of Electrostatic Discharges

13

18 23

1.5.1. Personal ESD Waveforms 23 1.5.2. Furniture ESD Waveforms 28 1.5.3. Summary: Comparison of Dynamic Parameters for Personnel and Furniture ESD 30 1.5.4. Actual versus Idealized ESD Waveforms 31 References 37

2. Effects of ESD on Electronics 2.1. 2.2. 2.3. 2.4.

Direct Discharge to an Electronic Component 39 Direct Discharge to Electronic Equipment Enclosure 50 Indirect Discharge 53 Coupling Mechanisms of ESD Pulse into the Victim’s Circuitry 2.4.1. Magnetic Field Coupling 55 2.4.2. Electric Field Coupling from Indirect ESD on Floating Parts 58 2.4.3. Measured E- and H -Field Values near an ESD to a Grounded Structure 60 2.4.4. Effect of Wave Impedance on Voltages Induced in Nearby PCBs and Small Circuits 64

39

54

vi

Contents

2.5.

2.4.5. Effect of a Typical Metallic Cabinet on ESD-Radiated Effects 2.4.6. Common Impedance Coupling with an ESD 69 Response of Victim Circuits and Type of Errors 70 2.5.1. Influence of Circuit Impedances 72 2.5.2. Specific Disturbance Created by the Hand/Metal Initial Spike 2.5.3. Errors/Malfunctions Induced in Analog Devices 74

67

74

2.6.

Prediction of Actual ESD-Induced Error, Fast Approximation Method 75 2.7. Remarks on the Actual Current Paths and Associated Radiation 2.8. Personnel or Furniture ESD: Which One is Worse? 78 References 79 3. Principal ESD Specifications ESD Test Specifications for Device Sensitivity 82 3.1.1. MIL-Std 883 82 3.1.2. EIA/JEDEC and ESD Association Test Methods 83 3.2. ESD Specifications for Equipment Immunity 84 3.2.1. International Standard IEC 61000-4-2 84 3.2.2. ANSI C.63-16, ESD Test Methods, and Criteria for Electronic Equipment 85 3.2.3. ESD Immunity for Automobile Electronics, SAE J1113-13 and ISO 10605 85 3.2.4. MIL-Std 1541, ESD Immunity Requirements for Space Systems 3.3. Antistatic Control Procedures 86 3.3.1. Military Domain: MIL-Std 1686 and MIL 263 Handbook 86 3.3.2. Industry Standards for Static Control Programs 87 References 88

78

80

3.1.

4. ESD Diagnostics and Testing 4.1.

4.2. 4.3. 4.4.

4.5.

ESD Simulators: How They Work 90 4.1.1. Arc or Direct Contact 92 4.1.2. Simulators for Equipment Test, Based on IEC 61000-4-2 Standard 95 4.1.3. Detailed Review of the IEC 61000-4-2 Simulator Definition 96 4.1.4. Generators with Different Networks, Very High Voltage and Field Enhancement Accessories 105 4.1.5. Special Relays Required for ESD Simulators 108 Furniture Versus Personnel ESD Simulation 109 Other Types of ESD Simulators for Component Testing 112 ESD Test Setup—Direct and Indirect ESD 114 4.4.1. Ground Reference 115 4.4.2. Direct versus Indirect ESD 115 4.4.3. Roles of the HCP and VCP 118 4.4.4. Grounding the Simulator and the EUT 120 4.4.5. External Cables and System Configuration 120 ESD Test Routine and Discharge Procedures 121

86

89

Contents 4.5.1. Preparation of EUT for Test Readiness 4.5.2. Application of the Discharges 122

4.6. 4.7.

121

No Error/No Damage Concept: The Several Layers of Severity The Error per Discharge Concept or Multiple-Trials Approach 4.7.1. Practical Application of the Error per Pulse Concept 4.7.2. ESD Test Plan with Cost-Effectiveness Constraints ESD Test During Design and Development 137

140 143

5. Design for ESD Immunity

5.2.

148

ESD Protection at Component Level 150 5.1.1. Integrated Circuits with Internal ESD Protection 150 5.1.2. Additional ESD Protection: When Is It Needed and How Much? 153 ESD Protection at the PCB Level (Internal Circuitry) 5.2.1. 5.2.2. 5.2.3. 5.2.4.

5.3. 5.4.

125 129

134 135

4.8. 4.9. ESD For Field Diagnostics and Forced Crash Method 4.10. Home-Made Investigation Tools and Diagnostic Hints References 146

5.1.

vii

Reducing the Field-to-PCB Coupling Mechanisms PCB Connectors Areas 159 Signal Ground versus Chassis Ground 160 PCB Hardening with Plastic Products 160

157 158

ESD Protection by Internal Wiring and Mechanical Packaging ESD Protection by Box Shielding and Envelope Design 169

161

5.4.1. 5.4.2. 5.4.3. 5.4.4. 5.4.5.

5.5.

Some Shielding Basics 170 How to Maintain Shield Integrity with Metal Housings 178 How to Make Shield Barriers for Plastic Housings 183 Treatment of Shield Openings 187 Nonmetallized Plastic Boxes 189 ESD Protection of External Cables and I/O Ports 191 5.5.1. External Cable Shielding 192 5.5.2. ESD Hardening of I/O Ports 200 5.5.3. I/O Cable Entries ESD Protection with Plastic Products 219

5.6. ESD Immunity by Software and Noise Inhibition Techniques 5.7. ESD Immunity with Miniature, Portable Devices 223 5.8. System ESD Immunity 225 5.9. ESD Control at Installation Level 226 References 228 6. ESD Cases Studies 6.1. 6.2. 6.3. 6.4. 6.5.

Case Case Case Case Case

1: 2: 3: 4: 5:

The Reradiating Ground Strap 231 ESD Hardening of a Printer 232 The Data Terminal with Floating Tray The Safety Wire “Antenna” 235 The Touchy Watchdog 236

221

230

233

viii

Contents

6.6. 6.7.

Case 6: The Trigger-Happy Air bag Initiator Conclusion: Troubleshooting Hints 237

236

Appendix A. ESD Protection by Design of Chips and Microcircuits

240

Appendix B. Prediction of ESD Damage Level for a Semiconductor Junction 252 Appendix C. Spark-Over Voltages

255

Appendix D. Fatigue Phenomena During Repeated ESD Testing

258

Appendix E. Prediction of ESD-Induced Noise by Fast FrequencyDomain Calculations 260 Appendix F. More Experiments on ESD Coupling to Boxes

269

Appendix G. Examples of Simple SPICE Modeling of ESD Coupling Effects 279 Appendix H. Time-to-Frequency Conversion for a Single Transient Index

295

293

Preface to the First Edition

Static electricity is the most ancient form of electricity known to humans. More than 2000 years ago, the Greeks recognized the attraction between certain materials when they were rubbed together; indeed, the word electricity comes from the Greek elektron, which means amber. During the seventeenth and eighteenth centuries, several key experiments were conducted to understand and measure static electricity. But the discovery of electromagnetism and its formidable breakthrough has rapidly outgrown interest in static electricity. Even today, where the industrial applications of static electricity are not insignificant, they cannot compare with those of electromagnetism and electrodynamics. Ironically, as much as static electricity was relegated to the attic of scientific evolution, she continuously occupied (I say “she” because electricity, in French, is feminine—don’t ask me why) the headlines with her undesirable effects. If we consider the thousands of lightning strikes hitting the terrestrial atmosphere every minute, we have to realize that our planet with its surrounding clouds is nothing more than a huge electrostatic machine constantly charging and discharging on itself. For decades, people have been learning the hard way that statics can cause explosions of fuels and ammunitions. In 1937, the German flying boat Hindenburg arriving in Lakehurst, New Jersey, caught fire while anchoring at its landing mast. What could have been a severe incident became a tragedy: Due to international tension, the United States had put an embargo on helium sales to Germany and the vessel was inflated with hydrogen instead. The resulting fire caused the death of 37 of its hundred or so passengers. Although the causes have not been completely understood, electrostatic discharge (ESD) is at the top of the list. More recently, during the 1970s in the United States, a spacecraft lauching rocket exploded during the fueling operation, killing three engineers. The cause was, beyond any doubt, identified as ESD. Satellites have paid a heavy toll because of ESD, from minor anomalies to severe malfunctions, as in the European Space Agency (ESA) MARECS satellite. In January 1985, during the assembly of a Pershing missile near Heilbronn, Germany, the motor case, made of Kevlar, was repeatedly rubbed against the cushioning in its container. The ensuing ESD caused the 4 tons of highly flammable propellant to catch fire and the motor exploded, blowing parts 125 meters away, killing three people and injuring nine. Although such catastrophes are terrible and spectacular, they are quite rare; but a more insidious aspect of ESD bloomed in the early 1970s, with the massive

x

Preface to the First Edition

arrival of integrated microelectronics. The plants producing integrated circuits (ICs) started to experience disappointing percentage yields. Once thoroughly investigated, the problem was found to be largely due to ESD during all fabrication steps and handling. Although the problem has been fully explained and drastic solutions adopted, ESD is still costing millions of dollars a year of pure losses. Considering the astronomical quantities of ICs manufactured each year, the mere fact that 3 to 30% of them die in infancy because of ESD represents an impressive amount of money. To quote G. C. Quinn, technical editor of Electronics Test Magazine (April 1984): “The volume range of ESD sensitive components is rising faster than the development and usage of ESD protections . . . Estimating costs of ESD failures not caught at manufacturing inspection is far more difficult. Many of the degraded, walking-wounded devices may not show up until after termination of the manufacturer’s guarantee.” Around 1980, Lockheed Corporation reported a one-year cost savings of $1.8 million through static protection measures, which reduced ESD-related failures by a 16 to 1 ratio. Arithmethic, then, tells us that Lockheed had endured losses of $1.92 million the previous year. Even with severe protection measures, some manufacturers still confess that ESD is causing 39 to 48% of their IC rejects. The only hope that the plague will ever be dominated is a progressive awareness of people and the growing use of robots on manufacturing lines. But the worst was yet to come: With the proliferation of microelectronics in all possible applications, an even bigger number of complaints flourished about ESD-related erratic bugs, transient malfunctions, erased memories, and the like. Although the economic losses resulting from erroneous transactions and corrupted data of all kinds are difficult to evaluate, it is probably an even larger figure than the one for chip damage during fabrication. It seems ironic that a physical fact, known for 2500 years as doing nothing but nasty things to us, has continued to defy electronics engineers. Solving the problem of transient errors induced by ESD has not been given the same concerted effort as the manufacturing aspect. Most early research was performed by isolated pioneers fighting with their own weapons. Initiating the research themselves, seldom supported by vast budgets, these men used their sagacity and all the resources they could find to investigate a problem for which no measuring techniques existed. They had to invent the tools they needed, and they had to be statisticians, chemists, and radio-frequency (RF) designers all at once. The names of Ted Madzy, W. Byrne, Michael King, Ralph Calcavecchio, Richard Simonic, and many others that I don’t know of are the people to whom all of us who followed are indebted. By mentioning their work, this book will try to render a piece of the recognition they deserve: They paved the road for bringing the understanding of ESD from black magic up to an analytic method. We hope this book will demystify ESD and give a step-by-step strategy for predicting, testing, and reducing its effects on electronic equipment. Gainesville, Virginia June 1985

Michel Mardiguian

Preface to the Third Edition

The two previous editions of this book had a very favorable reception from the EMC community. However, the first and second editions, published by the EMC consulting firm Interference Control Technologies, had a rather limited distribution and have been out of print since the year 2000. A new edition was sorely needed, incorporating current technological advances with the needs of the engineering community. Since the first edition of this book 22 years ago, the electrostatic discharge (ESD) phenomenon has continued to plague the electronic industry. In spite of undisputable progress in ESD awareness and protection measures, which are inforced by regular audits and accreditations, the “sleeping sentinel” syndrome takes its toll. Inspections often reveal that in an assumed static-free manufacturing chain, all but one of the workstations or handling/packing posts are adequately protected. This single defective link is enough to compromise the entire ESD line of defense. Sometimes it was the very apparatus intended to eliminate human influence, for example, automatic handling by robots, that created a new ESD problem, sometimes worse than the one it was supposed to cure. Once these pernicious problems are fixed, the return on investment of a flawless ESD control program is often spectacular, not forgetting that this is a constant battle because today’s problem is frequently the consequence of some unanticipated effect of yesterday’s solution. Nonetheless, once marketed and sold, some modern equipment, although it has undergone a compete EMC test program that includes ESD, is still experiencing malfunctions, a tangible share of which is traceable to ESD. Consider a recent example: This author, among other consultants, was asked to solve a problem on a certain model of car. Five percent of owners were experiencing a very unpleasant dashboard failure: During operation some displays would freeze up, eventually becoming totally dark without a possibility of reset, even after a stop-and-start action. The problem was a peculiar ESD configuration that had escaped the standard test program. In order to cope with such omnipresent threats, intensive research has continued worldwide, using instrumentation that is much more elaborate than that available in the 1970s and 1980s to the pionneers of ESD studies. Recent studies have covered arc formation, initial spike with the hand/metal scenario, fields radiated in the vicinity of the discharge, and the like. Among the engineers who

xii

Preface to the Third Edition

investigated these facets of ESD, one of the most prolific has certainly been D. Pommerenke of Missouri University. In the first few chapters of this new edition, we give an overview of these recent studies. The problem of poor repeatability has always also plagued ESD testing, as with many EMC tests in general. But, while other tests have gained significant improvements in accuracy and credibility, ESD remains the black sheep of the herd, raising sarcastic jokes among EMC practicioners and lab technicians, who are struggling constantly with these “ESD guns that don’t shoot right” or “ESD tests that make failing products pass and good products fail.” Therefore, a substantial share of the R&D effort has been aimed at reducing the uncertainty attached to ESD generators and test procedures. However, we have some reservations: While a tremendous amount of activity has been deployed toward ESD generator modeling, calibration, and error analysis that is basically “simulating the simulators,” it seems that the EMC community has lost sight of the actual fact we are trying to counteract: the real, everyday electrostatic discharge. To our knowledge, no organized, wide ranging statistical survey of ESD events has been conducted since the last outstanding work done by R. Simonic around 1973–1974. Things have changed: People’s habits are different: interior decoration, furniture, and clothing are different. Instrumentation that could capture and record ESD is now more accurate, with much greater bandwidth than in the early 1970s. As a result there is a danger that we may very well be trying to reproduce perfectly, with today’s advanced simulators, events as they were recorded 35 years ago. St. Remy les Chevreuse, France May 2009

Michel Mardiguian

Acknowledgments

After writing the word end , my gratitude goes to to those who provided their timely assistance and information: Etienne Sicard and Alain Charoy who gave me valuable details on IC protection, David Pommerenke who shed some light on his very specific series of measurements and modeling, Diethard Mohr and William Rhoades for bringing me up to date on some current ESD documents status. My thanks go also to Joel Raimbourg and Sebastien Bazzoli who provided invaluable support for some practical experiments. Last, but not the least, I am grateful to Mark Montrose and Michael King—the latter being a living memory of the pionneering era of ESD—who expressed their encouragement for the making of this third edition. Many thanks also to Jeanne Audino and Steve Welch of the IEEE Press team, for their very professionnal assistance that gave life to my crude manuscript, and again to Mark Montrose who did the technical review, adding some precious remarks. Very special thanks go to the editorial team at Wiley: Lisa Van Horn, Ernestine Franco, and Dean Gonzalez, respectively, senior production editor, copy editor, and illustration manager, who performed a meticulous editing and turned my crude sketches into fine drawings. I also thank my wife Corinne for her patience, not to mention that she has been the one who typed some of the chapters, as it is often the case with we engineers, who pretend to become writers. M. M.

Chapter

1

The Electrostatic Discharge Phenomenon Although a thorough description of the electrostatic phenomenon is beyond the scope of this book and has been covered by several authors (1–4), it might be useful to start by reviewing briefly how static electricity takes place, what are the contributing parameters, and why, eventually, it ends abruptly in its threatening consequence: the electrostatic discharge (ESD). The following section is an extremely simplified view of the electrostatic charging mechanisms. While clearly not a treatise on static electricity, it illustrate the physics involved, in a simple manner. Readers with a good basic knowledge of electrostatics can probably skip this preliminary portion.

1.1. PHYSICS INVOLVED Any material is made of atoms. Unless submitted to certain external influences (heating, rubbing, electrical stress, etc.), the atom is at equilibrum; that is, the amount of negative charges represented by the electrons orbiting around the nucleus is exactly balanced by an equal number of positive charges or protons aggregated in the nucleus. Therefore, the net electric charge seen from the ouside is zero. In good conductors, the mobility of electrons is such that the conditions of equilibrium will always exist; that is, no significant static field will exist between different zones of the same piece of metal. With nonconductive materials, however, the lesser mobility of electrons does not provide such a rapid recombination of charge unbalance. If heated, or rubbed strongly (which also creates heat), a nonconductor will free up electrons. Depending on the nature of its outer valence orbit, a nonconductive material may be likely to give up electrons or to capture wandering electrons. Electrostatic Discharge, Third Edition, by Michel Mardiguian Copyright © 2009 the Institute of Electrical and Electronics Engineers, Inc.

1

2

Chapter 1 The Electrostatic Discharge Phenomenon

− −

−

+ + + + + +

−

−

−

Figure 1.1 If by heating, rubbing, and the like, one electron is leaving the orbit, the material is left with six protons and only five electrons.

A nonconductive material that gives up an electron, as shown in Figure 1.1, will become positively charged. Such unbalanced atoms with a lack of electrons are called positive ions. A nonconductive material that takes extra electrons will become negatively charged, and its atoms with excess electrons are called negative ions. Charges with like sign repel while charges with opposite sign attract. Therefore, it seems that nature will rapidly take care of the unbalance by recombining the charges. Unfortunately, while this recombination is instantaneous in metals (i.e., indeed, how a current flows), the high resistance of nonconductive materials makes it unlikely to happen, until such a high gradient of field is reached that either an arc or a mechanical attraction will occur. Besides rubbing or heating, which is the common generation mechanism, an object can become charged by contact with another previously charged object. This ability of nonconductive materials to acquire electrostatic charges is known as triboelectricity. Once a nonconductive material has been subject to triboelectric charging, the charges trapped on its dielectric surface are not easily removed. Grounding the piece of material will do nothing since, on insulators, charges have no mobility. Only a flow of ionized air, hot steam, or conductive liquid can remove the charge unbalance. Static charging ability is frequently shown on triboelectric scale, such as the one in Table 1.1 Materials labeled “positive” will take on a positive charge every time they are frictionned against a material lower on the scale. Although this kind of scale is true overall, the precise ranking of each material within the scale should not be definitely relied upon in real-life situations. Many authors and practicians in the ESD community, such as A. Testone (3), have shown how deceptive such triboelectric tables can be.

1.1. Physics Involved

3

Table 1.1 Triboelectric Series More (+)

More (−)

Dry air Plexiglass Bakelite Cellulose acetate Silicon wax Glass, mica Nylon Wool Human hair Silk Paper, cotton, wood Amber, resins (natural or synthetic) Styrofoam, polyurethane Polyethylene Rubber Rayon, Dacron, Orlon PVC Silicon Teflon

For example, let us take a reel of ordinary office adhesive tape. If we quickly unwind some length of tape, everyone knows that this segment becomes charged and can attract small particles of dust, hairs etc and the like. But since both sides of the tape are the same material, they rank the same (e.g., positive for acetate) on the table, and this piece of film could not develop an electric field against itself. However, after unwinding this short segment (Fig. 1.2), we notice that it is strongly attracted by the rest of the reel, which indicates that there has been a charge transfer, whereas one side of the tape has acquired electrons that the other side has lost. How can the same material be at the same time a “taker” and a “giver” of electrons, thus contradicting the triboelectric scale? Furthermore, if we cut this piece of tape (using insulating gloves and scissors to prevent our conductive body from influencing the results), and approach it to the reel, some areas of the tape are attracted, while others may be repelled. The mechanisms coming into play in this apparently simple experiment are multiple and complex. For one, the materials involved are not just acetate against acetate; there is the adhesive layer and also the air itself, which is on the top (+) side of the scale. Then, the tape surfaces have changed their radii as they were separated, such as the “run-away” electrons do not face exactly the same region as when the contact was tight. Therefore, even two insulating materials of the same nature can eventually develop opposite charges if sufficient friction, shear, or bending is applied. This happens hundreds times a day in a photocopier when foil is slipped over the paper stack.

4

Chapter 1 The Electrostatic Discharge Phenomenon

−

+

+

+

+

+

−

−

−

−

Figure 1.2 Stripped end of acetate tape is attracted by the surface of the tape reel.

Thus, although triboelectric scale is a fair indication of the polarity of the charge acquired by materials, we must stay away from peremptory statements when facing an electrostatic charging situation. Static field meters are good instruments to get a true measure of the static voltage acquired by various materials. Now consider the classical example of a person walking on a synthetic carpet, rubbing his body on an insulated chair pad, or moving his nylon shirt sleeve over a polyvinyl chloride (PVC) surface: the farther apart the two materials are on the triboelectric scale and the faster the relative motion of the person, the more electrons will be freed by the givers and captured by the takers. This creates a charge unbalance—hence a latent electric field. Figure 1.3 suggests a scale of merit for the propensity of materials to create more or less ESD problems. It is based on the surface resistance in ohms per square (i.e., the resistance of a sample square, whether it is 1 cm2 or 1 m2 , yields the same results). Material with more than 109 /square are likely to develop electrostatic potentials that will not bleed-off by themselves due to the high insulation of

Ω /square 1014

Static generating materials

1012 1010 108 10

Insulators Anti-static, but Non-dissipative Anti-static, dissipative

6

104

Conductors Conductors

Figure 1.3 Propensity of materials to create ESD problems, based on surface resistance in ohms/square.

1.1. Physics Involved

5

the material. Materials with less than 109 /square, even if not real conductors, will not keep the charge unbalance very long because recombination will occur through the material itself. Aguet (5) relates the propensity to electrostatic charge to the dielectric constant of the materials that are rubbed. He indicates the surface charge density σs : σs = 15 × 10−6 (εr1 − εr2 ) Coulomb/m2

(1.1)

where εr1 , εr2 are the relative permittivity of the two materials. For instance, if one looks at a rubber shoe sole (εr1 = 2.5) representing 250 cm2 and a nylon carpet (εr = 5), the maximum total charge Q that can be acquired is Q = 15 × 10−6 (5−2.5)250 × 10−4 m2 = 0.93 × 10−6 Coulomb If the corresponding foot-to-ground capacitance C is about 100 pF, the static voltage is derived from Q = CV

(1.2)

Hence, V =

Q = 9300 V C

It might seem, therefore, that there is practically no upper limit to what voltage a person can attain. Why not 50 kV 100 kV? Richman, in his very illustrative pamphlet on ESD (6), explains that, hopefully, personnel electrostatic voltage cannot exceed 30 kV in the most extreme cases because: 1. The capacitance of the human body, no matter what we do, cannot drop below 30–40 pF, a value that Richman calls our “capacitance to infinity.” 2. Above approximately 25 kV, the corona will start to self-limit our voltage by bleeding off the charge, that is, the assumption of constant charge Q is no longer valid. So, in most practical situations, the upper range of human body static voltage is 20–25 kV. Summarizing this short description of electrostatic charging, we can say that static electrification is a complex phenomenon that one cannot solely characterize by any single parameter, such as the ranking of the material on a triboelectric scale, its surface resistivity, or dielectric constant. To the contrary, static dissipation can be dependably related to resistivity.

6

Chapter 1 The Electrostatic Discharge Phenomenon

1.2. INFLUENCING PARAMETERS Once the type of materials present is known, the most important parameter is relative humidity. It is well known that, during winter and spring seasons, all integrated circuit manufacturers have recorded an increased rate of “infant mortality” in their chips, and field engineers report an increasing number of service calls for computer failures. Several things happen when relative humidity is low: •

•

Normally, the moisture content in the air tends to decrease the surface resistance of floors, carpets, table mats, and the like by letting wet particles create a vaguely conductive (or say, less than 109 /square) film over an otherwise insulating surface. If the relative humidity decreases, this favorable phenomenon disappears. The air itself, being dry becomes a part of the electrostactic buildup mechanism every time there is an airflow (wind, air conditioning, blower) passing over an insulated surface.

Many evaluations have been made of the electrostatic voltages reached by a person walking on several types of floors. Generally, these tests are made using a kind of “standard walking procedure.” The person walks a given number of steps with a given type of shoes; then his (her) charging voltage is immediately measured with an electrostatic voltmeter having a quasi-infinite input impedance. The importance of measuring the voltage immediately after charging, and preferably having this same short time for all experiments, is seen in Figure 1.4. If the time elapsed between the end of the charging phase and the instant of the measurement is not kept constant, comparisons between materials, clothes, shoes, and the like become inaccurate. Figure 1.5 shows the range of acquired electrostatic voltages for several floor types and two values of the relative humidity (RH). On the left side, the voltages are shown for an RH of 50%. Even with a notoriously bad type of carpet such as nylon, the voltage stays within 1–3 kV. Note that this is already enough to kill some integrated circuits if the person touches directly a module or a printed circuit board (PCB). But the scale in the middle merely suggests the likely consequences when the charged person touches a typical electronic cabinet, without direct contact to a module or connector pin. What is shown as “likely consequences” assumes that the stressed equipment is of an ordinary design, not especially hardened against ESD. (Chapter 5 will explain how a system can be made reasonably immune to ESD.) The right side of the chart shows what happens with the same kind of floor coverings when RH goes down to 20%. Nylon jumps to 6–11 kV, and some other synthetic carpets cause people to charge up to 8 kV. The diagram in Figure 1.5 is restricted to the most current types of floors. With some specific materials, things can go even worse. The worst floor ever is probably a silicon waxed wooden floor where human ESD voltages over 20 kV

1.2. Influencing Parameters

7

Time in seconds 10

20

30

40 500

200

200

100

100

50

50

20

20

10 0

10

30

20

Operator potential in volts

Operator potential in volts

500

0

10 40

Time in seconds Legend Shoe sole Composition or leather Leather Composition Leather Composition Composition Conductive

Floor

RH

Vinyl

4%

Conductive (0.27 MΩ) Conductive (0.95 MΩ) Conductive (0.27 MΩ) Conductive (0.27 MΩ) Conductive (0.27 Ω) Conductive

5% 4% 45% 5% 45%

Figure 1.4 Electrostaticgenerated voltages will decay at a rate that is dependent on relative humidity, floor covering, and type of clothing worn by personnel. Decay times can take several minutes to reach safe levels (7).

have been commonly reported. A well-known, and often painful, static environment is that of an automobile interior (Fig. 1.6), since a car is a metallic envelope isolated by its tires and replete with plastic and synthetic textiles. It may seem that a relative humidity of 20% is a rather low. Indeed, as shown in Table 1.2 for relative humidity over the year in major U.S. cities, only a few locations have an RH less than 20%. But in absolute numbers, cities such as Albuquerque, Tucson, and Phoenix are industrial/business areas representing millions of people with hundreds of thousands of electronic devices installed, which must function correctly, even during the winter/spring months. In fact, the problem is more critical than Table 1.2 would have us believe: The recorded RH values are those found outdoors by the weather bureau. A significant difference may exist between the RH outdoors and its actual value in a heated building. This is due to the fact that, given the same quantity of water, warm air has a greater ability to absorb moisture; therefore, its relative humidity (compared to saturation) is lower. Equation (1.3) shows that in a restricted space whose temperature is T2 , the relative humidity is RH2(T2 ) = RH1(T1 )

T2 C(1/T2 −1/T1 ) e T1

(1.3)

8

Chapter 1 The Electrostatic Discharge Phenomenon 20 15

Static voltage in kV

10

× 5

Range for nylon and acrylic

3 2

ol

Wo

c” tati ) ti s ative n “A sip s (Di

×

1 0.6 60

50

30

20

15

10

Relative humidity in % 12

8

10 1

8

6

6 Poor

4

2

4

5 Marginal 1

3 2

2

3 4

4

5

6

Static voltage in kV

Static voltage in kV

10

12 Disastrous Material Code 1. Regular nylon 2. Com’l antistatic nylon Possible 3. Vinyl asbestos tile physical 4. High pressure laminate damage 5. Acrylic and polyester Very 6. Compu-Carpet poor

Safe

0

6

2 0

50% RH

Equipment reliability

20% RH

Figure 1.5 Typical range of static voltages generated by walking on common floor covering materials (adapted from Ref. 8).

where RH1 is the relative humidity of the outer ambient, at temperature T1 , and C a constant equal to 5370 between −20◦ C and +70◦ C; T1 and T2 in the formula are given in kelvins. The equation has been plotted in Figure 1.7 for a few typical situations. For instance, on a winter day where the outside temperature is 0◦ C (273◦ K) and the

1.3. Various Types of Electrostatic Charging with Humans and Objects

9

25

Charge voltage in kv

Polyester seat Nylon clothing

20

Vinyl seat Nylon clothing

15 Polyester seat Polyester clothing

10 Nylon/

5 Viscose

Nylon/ Viscose seat

seat Cotton Polyester clothing clothing

Leather seat Cotton clothing

Leather seat Nylon clothing

Vinyl seat Cotton clothing

Figure 1.6 Electrostatic charging voltages for various car driver/car seat combinations (9).

RH about 40%, the actual RH in a room heated at 22◦ C will be only 9%! Unless the heating, ventilation, or air-conditionning system (if there is one) compensates for this lack of water vapor, which it generally does rather poorly, or a humidifier is installed, the ESD risk is very high. Besides the type of material and the relative humidity, other factors play a role in the severity of the human electrostatic charge: Type of clothing and shoes Speed and manner of walking Sex and size of the person Body capacitance Body resistance The two last factors will be discussed in the next section because they strongly influence the dynamic characteristics of the discharge.

1.3. VARIOUS TYPES OF ELECTROSTATIC CHARGING WITH HUMANS AND OBJECTS Although an infinity of ESD cases have been reported, the ones that are plaguing the electronic industry belong to either the human body discharge or the charged object discharge. (9) So far, we have emphasized the electrostatic charges generated by human beings, as shown in the most common scenarios of Figure 1.8.

10

Chapter 1 The Electrostatic Discharge Phenomenon

Table 1.2

1.3. Various Types of Electrostatic Charging with Humans and Objects For :

11

θ2 = 20°C inside

100

80

θ1 = 30°C θ1 = 40°C

θ1 = 20°C

Inside

Hθ2 (%)

60

θ1 = 10°C

40

20

θ1 = 0°C Outside

0 0

20

40

60

80

100

Hθ1 (%) Hθ2 = Hθ1K·

θ2K 1 _ 1 · e 5400 ( θ1K θ2K) θ1K

Hθ : Relative humidity at temperature θ θ : Temperature in K (formula valid for −20 to + 60°C)

Figure 1.7 Actual vs. apparent relative humidity.

Notice that depending on the nature of the two materials being rubbed together, the person can exhibit positive or negative charging. Although humans tend to treat themselves as very special, physics does not care and treats us as a mere conglomerate of materials, vaguely conductive. There are thousands of occasions where the human body is not the electrostatic generator, but simply the carrier, or even is not involved at all (Fig. 1.9). An example of a human as a carrier occurs when a person gets out from a car after a ride on a bright, cold, and windy winter day. The moment he puts his foot on the ground while his hand is touching the door handle, he often feels a violent ESD zap. The body was not the electrostatic generator in this case, the car was.There have been reports of highway toll gate attendants who could not stand their job because of too many ESD zaps when drivers where handling them the money! Following is a list of some nonhuman ESD sources: • • • •

Wheelchairs, carts, rolling furniture Rubber or textile belts and conveyors and their pulleys/rollers Cooling fans with plastic rotor blades Helicopter rotor blades (generally made of composite material)

12

Chapter 1 The Electrostatic Discharge Phenomenon

+ −

− +

−

−

+

+

−

−

−

−

+

+

+

−

−

−

− +

+

+

+

+

+

+ −

+ −

+ −

Figure 1.8 Some of the classical ways a human can accumulate static charges.

+ + + + + +

− − − − − −

Figure 1.9 ESD with or without a human body involved.

1.4. Statistics of Voltages and Currents Reached During ESD • •

• •

13

Paper movement (printers, copiers) Rapid flow or friction of gas, liquid, or granule against an insulating material or unground conductor such as: • Cleaning with airgun • PVC “skin-packing” with hot air blast • Cleaning with solvent • Fuel lines (including filling-in or draining-off a fuel tank) • Loading or dumping grains in silos • Rocket exhaust nozzle • Radomes, fiberglass hoods, and tips • Thermal blankets (spacecrafts) Device-manipulating robots on manufacturing lines Electrostatic painting process (the spray nozzle being charged around 80–100 kV)

Also, we must remember that a nonconductive object can become charged by contact with another, previously charged, object. This static-contaminated object will, in turn, be a potential hazard for electronics. In all cases, whether a person is involved or not, the charged object will “seek” the first opportunity to recombine the unbalanced charges: This may occur smoothly by a progressive bleed of charges through a moderately conductive path, or may occur abruptly and generally accompanied by an arc. In the case of a “self”-recombination, a small amount of current will flow during a certain time, and the result will be generally harmless. To the contrary, with an abrupt recombination, the discharge will occur during a very short time due to the high-voltage gradients involved, and the corresponding current will be high. Since its average value is I (A) =

Q(Coulomb) t (s)

(1.4)

when a discharge of microcoulombs takes place within tens of nanoseconds, the average current amounts to several amperes, with peak values that can reach up to hundreds of amperes.

1.4. STATISTICS OF VOLTAGES AND CURRENTS REACHED DURING ESD Although the ESD phenomenon has been experienced and fought against for decades by electrical and electronics industries, it is only around the early 1970s that thorough studies were carried on its dynamic parameters. Measurements have been published of voltages and/or currents encountered during real or re-created ESD situations, sampled over a certain period of time or among a certain number of individuals. The statistics that have been gathered, to the knowledge of this author, can be classified as follows:

14

Chapter 1 The Electrostatic Discharge Phenomenon • • • •

Measured voltages of human ESD, depending on the materials involved (garments, type of shoes, type of floor covering) Measured voltages of human ESD, depending of the relative humidity (correlated or not with the time of the year) Measured voltage of objects and furniture ESD, against the type of objects and sometimes the type of environment (humidity and floor covering) Measured currents with furniture ESD, against type of environment and time of the year

Although they are more spectacular and seem to relate the most obviously with the severity of the discharge, the data collected on ESD voltages are not the most meaningful, neither are they the most crucial when trying to develop representative specifications for ESD simulation. The voltages at which the persons were charged during the measurement campaign can be an ambiguous or inaccurate database. Was the voltage measured at its peak, right after a static buildup? Or was it recorded at the moment of an actual discharge? What were the mean value and standard deviation of the voltage decay between its peak value (as generated) and its value at the exact moment of the discharge? Were the people in the study aware that ESD voltages were gathered? Every statistician knows that people in such surveys often tend to “sympathize” with the experimenter, helping him to find what he likes to find (in our case, for instance, by shuffling their shoes more conscienciously on the carpet). Statistics is a discipline requiring specific precautions. In some of the often mentionned experiments, it is not clear that these precautions were taken or were feasible. Doing a parallel between ESD and lightning, one could say that focusing on ESD voltages only is probably as irrelevant as would be concentrating on cloud-to-Earth voltages when studying lightning strikes: all sound statistics on lightning severity are based on lightning currents. Similarly, ESD statistics based on current seem the most dependable and usable. As for any transient, random events, statistical analysis is important for determining what is the risk that a certain value of electrostatic discharge will be reached (or the probability P that this value will be exceeded). Do we want to test the immunity of an electronic device or equipment to something that can happen once a day or once a year? How many failures per week or month do we risk by testing a machine only to a certain ESD level? A rough example of recording the number of electrostatic discharges is shown in Figure 1.10. During a particularly cold and dry spring (early April 1982) in Virginia, the author had taken a limited survey of the number of discharges (as they were felt by people) in a set of offices where about 12 people were using one copier, a telex, a desk-top computer, a postage meter, and a word processor. Discharges were recorded on Tuesdays, Wednesdays, and Thursdays for 3 weeks. These discharges did not necessarily cause equipment malfunction—in fact most of them did not—but the purpose of the survey was to count the

1.4. Statistics of Voltages and Currents Reached During ESD

15

29

18 16 13

Wed.

7

8

10

10 Thur.

Tues.

11

11

6

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Week 1 Week 2 Week 3 Day of the month

Figure 1.10 Number of discharges/day in a medium-size office area with copier, computer, word processor, telex, and mailing machine.

ESD events, not the eventual failures. It must be also noted that discharges of less than 1500–2000 V were generally not felt by a person and, therefore, were not recorded: They represent no risk for normal electronic equipment, but their absence in a sampling could skew the statistical analysis and produce overly pessimistic conclusions. A much more intensive survey was done by Simonic (10, 11). During two surveys spread over several years, he has compiled with an impeccable rigor thousands of measurements of both human and furniture ESD in quasi-real-life conditions. His work represents such an outstanding contribution to the subject that it deserves a detailed analysis, as shown hereafter.

1.4.1. Personnel ESD Statistics The first compilation made by Simonic covered personnel ESD events. The survey was run for 16 months, and its analysis allows one to predict, given a human contact discharge, the probability P of exceeding a peak discharge current I . The highlights of the analysis are the following: • • •

The rooms surveyed had a high human activity (terminal room with 16 operator-attended stations). The rooms had uncontrolled (or poorly controlled) RH and wool carpet. The purpose of the survey was to record the number of discharges, not the number of machine failures, which would have restricted the scope of the study.

16

Chapter 1 The Electrostatic Discharge Phenomenon

Therefore, to be sure that what was measured was the ESD current caused by people (and not furniture ESD), and to provide every person with the same calibrated discharge path, a special monitoring setup was devised: • • •

•

•

IESD was measured by a current probe (current transformer) placed on a specially equipped metal doorknob. Only the interior side of the door handle was equipped, so only personnel ESD from inside the room was recorded. The current probe was connected to a recorder with 9 separate channels, set to specific threshold levels. The probe had a 100-MHz bandwidth, but accounting for the whole instrumentation chain, the final 3-dB bandwidth was 30 MHz. Each channel was recording the number of occurrences its own threshold was exceeded [therefore it can be directly translated in a P (I > 1x) statistic]. The RH was constantly monitored.

The study collected data from 498 eight-hour shifts, with an average of 120 discharges per shift. Thus, about 60,000 ESD events were logged and arranged in 3800 data entries. Using sound statistical practices, a regression analysis weighted to the number of human contacts was performed. Over a more limited period, one type of antistatic carpet was also surveyed. Since some people had finger rings, wrist straps, and the like, it is likely that a certain percentage of human/metal discharge is included in the collected data. The 30-MHz bandwidth seems insufficient to measure ESD pulses with 1-ns rise time (which would need at the very least a 350-MHz bandwidth). But the system was calibrated by a reference ESD pulser delivering a waveform with a 2-ns rise time, 320-ns time constant, and a source impedance of 2000  (behaving like a current source). Thus, the correlation between the 30-MHz limited bandwidth and the actual pulse bandwidth was taken care of by the calibration. The analysis reveals, of course, a strong correlation between the RH and the peak currents reached. A convenient equation for predicting the current I , given a probability P , was derived from the analysis: I ≥ 10A P B (RH)C

(1.5)

with A = 4.12

B = −0.645

within the following range: 0.95 confidence RH% comprised between 15 and 55 Probability P (I ) = 0.001 < P < 1

C = −3.39

1.4. Statistics of Voltages and Currents Reached During ESD

17

Table 1.3 Peak Current (in Amperes) Having a Probability P (I ) of Being Exceeded by Personnel ESD P (I ) RH Percent 15 < 20 < 25 < 30 < 35 < 40 < 45 < 50
1 μA (indicating a damaged gate insulator) or an output not responding to input change, whichever failure came first. The graphs show ratios of 3 to 1 or 4 to 1 between the best part and the worst part of the sample. Also the deviation varies widely from one manufacturer to another. Another example showing that the ESD damage level is never a “green light/red light” situation is shown in Table 2.2. The product tested was a bipolar logic gate type 54L04 (TTL, low power). One hundred devices were tested for multiple pulses until a failure occurred. The criteria for failure was to monitor the deviation of two critical parameters from their normal value: Iinput

High

Voutput

Low

Normal = 10 μA max;

failure if I > 20 nA

Normal = 0.3 V max;

failure if V > 0.05 V

The results are shown in number of parts that did not survive to N pulses at level V . All the parts survived after the application of up to 175 pulses at 2000 V; then 10 died between 176 and 200 pulses. The survivors were stressed to 2750 V, where casualties are seen as soon at the first pulse. Finally, of the 15 survivors that came victoriously through the 200 pulses at 5000 V, 10 died at the first

48

Chapter 2 Effects of ESD on Electronics 4

8

12

20 30

Gate section D out of specification (inputs low)

20

20

Gate section C in specification (inputs low)

10

0

16

CD4001A ISS vs. VDD

0

4

8

10

12

Leakage current in mA

Leakage current in mA

30

0 20

16

Volts

Figure 2.5 Example of deteriorations in reverse breakdown (9).

Table 2.2 Failure Decision Is Never a Step Function (11) Pulse Level (V)

Number of Pulses to Cause Failure (N) 1

5750 5000 4250 3500 2750 2000

10 12 16 9 2

2

3

4

1 2 1

8 2 1 1 1

50

1

75

1

125

1

175

2

200

3 8 11 10

application of a 5750-V ESD. Can we then say that we have a product that can withstand ESD at 2000 V? or up to 5000 V? This is the case where all the usual methodology of stress tests and quality control (QC) have to be used to come up with a reliable number that will characterize the ESD immunity with a certain confidence level (12). In all these tests an unstressed sample lot should be verified to avoid the introduction of an uncontrolled variable not related to ESD. An interesting question arises: Would the 15 heroes that came through 5000 V have gone even further if they had not been inflicted, at lower levels, with 600-V discharges? Some test plans require that after every run at a given ESD voltage, the entire lot under test be replaced by a new one. This is a way to characterize the true ESD immunity of this product. However, the cumulative effect of multiple discharges, with increasing levels, is missed. Some technologies can be significantly more fragile than the previous example. The following relates to the ESD test results of an analog

2.1. Direct Discharge to an Electronic Component

100 99.9

300

Stress in volts 1000

49

99.9

In (time/stress) B

99 C,D

A

50 30

50 30

10

10

3

3

1

1

0.3

0.3

0.1

0.1

0.03

0.03

0.01 100

300

1000

Cumulative failutre in %

Cumulative failure in %

99

0.01

Stress in volts

Figure 2.6 ESD failure level for 4001 inverters from Manufacturers A, B, C, and D (10).

radio-frequency (RF) mixer IC, containing GaAs components, in a SOT (small outline technology) package: Sample size: 30 parts Type of test: human body, pass/fail treshold: 100/200 V Type of test: machine model, fail treshold: 100 V This is clearly a very ESD-sensitive device because of GaAs technology, requiring serious handling precautions and external protection components in its application. Another related problem is one of latent failures: a part which still appears undamaged after an ESD test may in fact have its lifetime affected. There are several confirmations that parts which have been subjected to ESD (either by fortuitous or intentional event) become “walking-wounded” that will exhibit abnormal failure rates in the field (12). But even this is not always true: some sample lots which were ESD stressed have exhibited, during accelerated life tests, better life-times than the sample lot, unstressed! This self-healing phenomena has been given several explanations, the description of which would be far beyond the scope of this book.

50

Chapter 2 Effects of ESD on Electronics

Since 1980, the U.S. Department of Defense (DOD) has issued a standard document, DOD-Std 1686, defining all the requirements for an ESD control program for electronic components and assemblies. Originally intended for suppliers and subcontractors of the DOD, it has become a commonly used reference for the industry in general. The DOD Standard (2006 Rev.) calls for: •

• • • •

Identification and tagging of ESD-sensitive items (Class 1 with sensitivity between 250 and 2000 V and Class 2 with sensitivity between 2000 and 4000 V); details of the corresponding test given in Chapter 3 Built-in circuit protection at chip and card level ESD-proof handling, shipping, and other procedures QC and audits Field maintenance precautions

The standard also requires that subcontractors rule out Class 1 devices when a Class 2 device is available that could perform identical functions. As a complement to DOD-Std 1686, the Department of Defense has issued Handbook 263, which gives ESD control guidelines and details of failure mechanisms. The document also contains classifications of ESD protection equipment, materials, manufacturing, and shipping procedures. (For an excerpt from Handbook 263, see Appendix A.) Other organizations such as the ESD Association or the IEC (International) also publish complete static control programs intended for manufacturers of electronic devices and equipment (see Chapter 3).

2.2. DIRECT DISCHARGE TO ELECTRONIC EQUIPMENT ENCLOSURE The direct discharge is the most classic case and the easiest to understand. The charged person or object (the “source”) touches a metal enclosure (the “load”). Most of the time [Fig. 2.7(a)] the discharge occurs on a purely mechanical part, which is touched intentionally (knob, key, switch, handle) or fortuitously (frame, covers, connector shell). Some more severe occurrences are shown in [Fig. 2.7(b)]: • • •

Finger approaching an unprotected input/output (I/O) connector Finger arcing through, or arc creeping around, a light-emitting diode (LED) or incandescent display Discharge on a PCB-mounted switch in which case a subsequent arc occurs internally between the toggle and the active contacts of the switch

In these latter cases, the ESD current can in fact reach directly the electronic components by a conducted path. Except for some damping caused by the wire or trace length, the situation is almost as severe as the direct discharge to a module pin, as was discussed in Section 2.1.

2.2. Direct Discharge to Electronic Equipment Enclosure

51

Metallic loudspeaker element

Wiring or PCB

to PBX ground

Plastic housing (a)

(b)

(c)

Figure 2.7 Personnel ESD coupling by direct contact.

Figure 2.7(c) shows another variation where the discharge occurs on a telephone set, via the earphone and its loudspeaker capsule. The consequences in this case are severe: The ESD transient is causing a hang-up of the conversation or loss of the memorized numbers. Whatever the scenario, the current then returns to ground by all possible routes, with amplitudes prorated to the impedances of these respective paths. This means that the bulk of the current will flow by the lowest impedance path, the remainder flowing through all other possible routes. For instance, Figure 2.8 illustrates what these routes can be for a single stand-alone machine. At this point in our discussion, let us briefly return to the actual waveform of a hand/metal (the most severe) type of personnel ESD, seen in Section 1.5 and Figure 1.29. The sharp peak of initial current caused by the local discharge of the forearm-to-target capacitance does not return by the machine-to-ground path. Instead, it remains confined in the loop formed by the hand and the machine cover. Only the main part of the current pulse, with rise time of 5–10 ns, is reclosing by the machine-to-ground impedance. In Figure 2.8(a), the discharge current path seems obvious, the machine being grounded by its safety wire and/or its neutral wire (neutral is generally grounded at the building level). However, the reality of this path does not resist a closer

52

Chapter 2 Effects of ESD on Electronics (a) Charged body

Grounded item IESD

(b) Charged body

Ungrounded item IESD

Several kV (c) Uncharged body

Charged item IESD

Figure 2.8 Personnel ESD coupling routes, showing return current paths.

look. The self-inductance of a round wire above ground is 1–1.5 μH/m, resulting in 3 μH of inductance for a typical 2-m power cord. For a current rise time of 5 ns, its dynamic impedance would be 3 × 10−6 L = = 600  dt 5 × 10−9 notwithstanding the additional length of building earth wire. Why would the entire ESD current choose to run across more than 600  while a lower impedance path exists in parallel? Figure 2.8(b) shows what this easier path can be. Any machine containing conductive parts has a capacitance to ground. In the case of a metallic casing, the capacitance to ground can reach 100 or even 1000 pF. For instance, a mainframe having a bottom area of 1 m2 , located 8–10 cm above ground, will have a parasitic capacitance of 100 pF. For a rise time of 5 ns, this corresponds to a dynamic impedance of about 50 . If the machine is lifted 0.80 m above ground, on a nonconductive table, this stray capacitance will decrease to approximately 40 pF, representing 120  of impedance, still less than what the ground wire can offer. Therefore a large proportion of the ESD current (specially during its rise, the most threatening one) will sink via the chassis-to-ground stray capacitance. This can be verified by the following, simple experiment: An ESD simulator is discharged on a grounded equipment. Then the power cord is removed completely

2.3. Indirect Discharge

53

and the test is repeated on the now floating frame. A discharge will occur with no difficulty and, if a current probe is inserted over the generator tip, it will read about the same peak current as with the grounded configuration. What will be affected is the discharge time constant of the pulse; in other words, the machine will stay charged for a longer time. Does this mean that for a normally grounded machine, no current is flowing into the ground wire? Certainly not: The same current probe, slipped over the power cord, would read a peak current that can be few percent to 10% of the total ESD current. In Figure 2.8(c) a third possibility is shown: the reverse discharge. In this case a machine has been charged by: • • •

Successive previous discharges from people and objects Internal static generations Laminar flow of air, specially dry or cold air or rubbing against a dry, isolated material

If the machine is floating versus ground (table-top equipment with power cord not connected, battery-powered device, and the like), the recombination of charges is not occurring or very slowly. When somebody approaches the machine, or takes the power cord to plug it in, a discharge will occur. If the machine is off, no harm is done to it, but the resulting surge creates locally a power line transient that may alter the operation of other machines nearby. Eventually, if the machine was in a stand-by, self-powered mode, a lock-up can occur that may necessitate a more or less elaborate restart.

2.3. INDIRECT DISCHARGE With an indirect discharge, the person does not (or even cannot) discharge directly on the equipment. For instance, if the machine is entirely housed in plastic with no or few accessible metal parts, nobody will discharge on it. In the early 1970s, with the massive arrival of plastic housings for electronic office products and electronic data processing (EDP) terminals, there was a general belief that they would mark the end of the electrostatic nightmare. “Bye-bye ESD” was the song, but people did not dance to it for very long: Field reports came in by legions to show that these products were experiencing even more ESD crashes than those with metal casings! Figure 2.9 shows what happens. A person discharges on any nearby metallic part: a door frame, a water pipe, a furniture, perhaps the very desk on which the machine is standing. Then, the ESD pulse radiates a strong local electromagnetic field, which couples into the nearby electronics since a plastic enclosure offers no shielding at all. With a desktop machine, for instance [Fig. 2.9(a)], if the motherboard lies flat on the bottom of the unit, the printed circuit is within 2 or 3 cm of the ESD current path. Figure 2.9(b) is a more diabolic variation of indirect ESD witnessed

54

Chapter 2 Effects of ESD on Electronics

IESD

IESD

(a) On metallic desk supporting a plastic product

(b) On a desk lamp

Figure 2.9 Indirect discharge.

by the author: A battery-operated calculator with a printer was being used by a draftman. During winter months, when the draftman switched his desk lamp on and off, the calculator would print a burst of erratic figures. At first a power-line transient was suspected but, besides the fact that the unit was not plugged into anything, the printer would turn on even when the lamp was simply touched. In fact, the ESD current was flowing via the lamp shade and the stem, coupling to the power cord via the large capacitance between the flexible tube and the wire inside and then to the ground. This long current path was radiating like an antenna on the plastic calculator circuit board. [Note: The author remembers a cocktail party where he experienced discharges on a large metal dish where the hors-d’oeuvres were arranged: The dish was on a cloth-covered wooden table, obviously grounded nowhere. But the charge transfer was enough to cause a violent ESD. Hopefully, sauteed chicken livers on toast and shrimps-a-la-creole are fairly ESD immune.]

2.4. COUPLING MECHANISMS OF ESD PULSE INTO THE VICTIM’S CIRCUITRY At the very instant of the discharge, a locally strong electromagnetic field excitation takes place: • •

The electric (E) field, which was established at a high value by the charged body, is collapsing abruptly. A magnetic (H ) field caused by the discharge current suddenly raises to a large value.

Both dE /dt and dH /dt field derivatives play a role, but all practical experience has confirmed that the severity of the threat is strongly related to the magnitude of

2.4. Coupling Mechanisms of ESD Pulse into the Victim’s Circuitry

55

the current. This is not to say that it could not be predicted from the initial voltage, but everything being equal—generator capacitance, discharging path dimensions, initial voltage, and arcing gap length—tests done with the least source resistance are generally causing the most machine malfunctions. The hypothesis that the arc length and the E field in its vicinity are predominant factors in the ESD susceptibility is usually contradicted by this fact: A machine withstanding 10 kV ESD with a generator having 2000  of internal resistance will almost certainly fail at a lower level with a tester having only 150 or 300  of internal resistance. In fact, a test condition considered as the most severe of all is one where the arc no longer exists, the discharge being done with direct contact of the probe tip. The role of the arc for air discharge is important in that it dictates the speed of ionization of the gap, hence contributing to the rise time, but the arc itself is not the predominant radiator. Instead, the radiating structure is made of: • • •

The human body (or charged furniture) The arm, terminated by the short arc The wall of the victim structure, with return by a more or less defined ground path

In the majority of cases [with the exception of Fig. 2.8(b) acknowledged], the electronic circuits of the victim equipment are not directly in the conducted path of the ESD current, which flows usually on housings and metallic structures. There is, therefore, a near-field coupling mechanism by which the localized field created by the discharge induces a voltage spike into the exposed circuit.

2.4.1. Magnetic Field Coupling Figure 2.10 shows a simplified model of this phenomenon, based on the discharge current only. A first thing to point out is that the dimensions of the ESD generating circuit are large compared to its distance to the receiving circuit. Therefore, it cannot be treated as a punctual source. Simple solutions of Maxwell’s equation for small electric or magnetic doublets with their resulting (1/d)2 and (1/d)3 field-to-distance dependency cannot be straightforwardly applied. A rigorous approach would be to apply the method of moments to the current path, broken down in small filaments. The much simpler model shown assimilates the ESD current path to a long radiating wire for which the resulting magnetic field is easily calculated from the Biot and Savart law. The ESD drain path to ground being long versus the distance of observation the magnetic field is given by: H (A/m) = I /(2πd) where I = ESD current in amperes d = distance from ESD path to victim circuit

(2.1)

56

Chapter 2 Effects of ESD on Electronics IESD

S

R

H

Simplified model: the H field is modeled from an infinite straight wire, carrying IESD

Ampère's law: H = I /2p R Example: IESD = 15 A (from a 4 kV simulated ESD) Distance R

H peak

Voltage induced in 1 cm2 loop Rise time 1 ns Rise time 5 ns

3 cm

80 A/m

10 V

2V

10 cm

24 A/m

3V

0.6 V

30 cm

8 A/m

1V

0.2 V

Figure 2.10 ESD coupling by radiation.

If the area of the circuit illuminated by the ESD field is known, a derivation of the field over the rise time gives an approximation of the open-loop voltage induced, generally sufficient for a quick prediction. Vi = −

dφ A dB = dt dt

(2.2)

where Vi = induced voltage, V A = victim circuit area, m2 B = induction in teslas, with 1 tesla = 104 gauss = 80 × 104 A/m Rearranging Eqs. (2.1) and (2.2) and using more convenient units, we end up with:   I A Vi = 2 (2.3) td

2.4. Coupling Mechanisms of ESD Pulse into the Victim’s Circuitry

where I A t d

= = = =

57

change in ESD current, A victim circuit loop area, cm2 rise time of the ESD current, ns distance from ESD path to victim circuit, cm

Figure 2.10 gives the results in voltages induced per centimeter squared of victim area, for three distances from the ESD path, assuming rise times of: • •

1 ns typical of the fast precursor peak with a hand/tool discharge ≤ 8 kV 5 ns more typical of simple hand discharge, or air discharge above 8 kV

Example Two printed traces 1 cm apart, with a 5-cm parallel run, located at 10 cm from the ESD flow will see a peak transient of 1 V/cm2 × 5 cm2 = 5 V. This is enough to create an erroneous bit in most logic technologies. Although very elementary, this method of predicting the ESD pulsed fields, hence the induced parasitic voltages, gives adequate approximation when compared to actual measurements. Even though the current flows more as a spread stream than as in a thin wire, the H field around its path can still be found by Eq. (2.3). This field from the ESD pulse has two effects: • •

It couples to the inner circuits of the machine: circuit boards, flat cables, discrete wiring It illuminates also the outside, all around the ESD source and discharge path (Fig. 2.11), where external signal and power cables behave as receiving antennas as well

1 2A Ipeak

−

+ 3

2B

Figure 2.11 ESD coupling mechanisms: (1) The discharge current flows over the equipment cabinet. (2A) Cabinet imperfections let the high-frequency component (near or above the λ/2 resonances) penetrate and shine inside. (2B) The discharge current radiates on the I/O cables. (3) Circuits inside intercept the high-frequency field. Note that these mechanisms are derivative, that is, frequency dependent.

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Chapter 2 Effects of ESD on Electronics

Another criticism could be raised against this overly simple model: Considering the frequencies involved, the current flow is supposed to stay confined on the outer skin of the metallic cabinet (assuming a direct discharge) because of the skin effect: At 100 MHz, for instance, the skin depth in steel is about 30 μm, therefore, a 1-mm steel cover would be 30 skin depths thick and, according to basic shielding theory, no ESD current should be found on the inner side. This would be true if the whole housing was a homogeneous shield, which is not the case: Slots, joints, vents, displays, cable entries create huge leakages especially at these high frequencies (this will be addressed in Chapter 5, under packaging aspects). As a result, the ESD current excites the many slot antennas formed by box discontinuities, cooling apertures, ungasketed seams, and the like. At the lower part of the frequency spectrum, these openings represent a minuscule fraction of wavelength, and their attenuation is significant. But for that part of the ESD spectrum that approaches or exceeds their λ/2 resonance, they shine inside with practically no attenuation. Therefore, in a device not specially hardened against ESD [or high-frequency electro magnetic interference (EMI), up to 1 GHz], the ESD current will flow on the inside of the cabinet as well as the outside. Now guess which part of the ESD-radiated field induces the largest voltages in the exposed PCB traces and in the cables? The high-frequency end, of course. However, knowing just the magnetic field may not be sufficient. A deeper knowledge of the nature of the electromagnetic field near the ESD path may be wished, as explained next.

2.4.2. Electric Field Coupling from Indirect ESD on Floating Parts Electrostatic discharge to an ungrounded, passive structure is a peculiar, although quite common, variation of indirect ESD. The basic coupling scenario is shown in Figure 2.12 and found in many practical situations such as in Figure 2.13. The charged person touches a floating, conductive object representing a sufficient surface—say more than a few tens of square centimeters. At the instant of contact, this object is acting as the armature of a capacitor that suddenly raises to the intruder’s voltage. In contrast with the previous cases with a grounded structure, where the ESD source was basically short-circuited by the target, what we have here is: • • •

A floating armature that is abruptly brought to kilovolts (+ or −) The local, narrow current spike i1 due to the small finger-to-target discharge, with the corresponding H field A strong E field impressed on the circuits of the victim equipment facing this armature

The effects of this E-field surge are generally less a problem than those caused by the H field in the previous examples. However, the circuits that are basically

2.4. Coupling Mechanisms of ESD Pulse into the Victim’s Circuitry i1

Floating armature A C1-G Victim circuit

59

1 to 2 kΩ A

VESD i2

C1-G

τ

ZGND

i2 Z(PCB-to-Ground) Impedance, wired or capacitive

Equivalent schematic

Example:

General scenario

VESD = 5 kV Rd = 1 kΩ

C1-G = 5 pF

ZC1−G 0.5 m

Insulating stand-off 10 cm thick GRP

Figure 4.23 Test installation for floor standing equipment (per IEC or ANSI). For I-ESD, notice the horizontal position of the gun at the edge of the VCP.

depending on the orientation of PCBs inside the unit, the points of entry and internal routing of the cables, one configuration may be more critical than the other. As a suggestion to save test time, one can run a first exploratory test with both configurations and find out which one gives the weakest ESD fail levels. Then retain this setup for the rest of the testing. For Equipment with Plastic Housing (Indirect ESD)

If floor standing, the EUT will be installed on a ground plane, as for the previous case. However, since there are no or very few accessible metal parts for direct discharge, the test following procedure will apply: • •

Direct discharges on all eventually accessible metal parts. Indirect discharge by discharging the probe on vertical coupling plates (VCP), grounded via high value resistances to the GRP. Discharges will be made at 10 cm from each side of the EUT. (This 10-cm distance is deemed to represent the closest reasonable worst case where people will actually discharge on nearby metallic objects. However, for some specific products, another distance can be selected.)

For table-top equipment, the EUT will be installed on a nonconductive table, covered with the HCP. The height of the EUT above this plane is simply dictated by its feet or stand-offs. No incidental contact to the HCP should occur by protruding screws or metallic parts on the bottom of the EUT. This is usually taken

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Chapter 4 ESD Diagnostics and Testing Simulator position for discharges to the EUT

Simulator position for discharges to the VCP Safety earth conductor

0.1 m >0.5 m to next structure and walls

VCP Insulation 0.1 m HCP Simulator position for discharges to the HCP

HCP discharging resistors (2 × 470 KΩ)

Ground reference plane (GRP)

Keep ground strap >0.2 m from the EUT and its cables

Figure 4.24 Test installation for table-top equipment. During the test, the EUT may need to be relocated on the HCP (or the HCP cut to size) to achieve the 0.1-m distance from the edges.

care of by putting an insulating foil on top of the HCP. A VCP will be installed on the HCP, via an insulating stand. The following test procedure will apply: •

•

Direct discharge on any accessible metal part (switches, keys, screws, conductive elements of an otherwise plastic cover, etc.). This includes contact or arc, whichever comes first. Indirect discharge by discharging the probe on a VCP (as done above), and on the table-top HCP, following a perimeter about 10 cm from the EUT sides.

4.4.3. Roles of the HCP and VCP With I-ESD, the test aims at reproducing the scenario where a charged person is touching a metallic structure (furniture, other equipment or appliance, door or window frame, etc.), very close to the nonmetallic EUT (see Chapter 2). For replicating the case where the EUT is resting on a metallic desktop, the gun will be discharged on the edge of a metal plate (the HCP). All the same, to simulate the case where the EUT would be close to a large vertical object, the gun will be discharged on the edge of a 0.50 × 0.50 m vertical coupling plate (VCP). Although this seems a sound approach, several issues are not clearly addressed or resolved in IEC and major testing standards:

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119

1. The connection of the HCP (or VCP) to the ground reference plane (GRP) is treated differently depending on the specification. The IEC demands that they be virtually isolated from the GRP via two 470-k resistors, acting only as a “soft” static sink for discharging the plate a few milliseconds after each discharge. At the moment of the discharge, this makes the VCP (or HCP) jump abruptly to the tip voltage, creating locally a strong E-field transient, hence a capacitive coupling to the EUT circuits (a plastic housing offers no Faraday shielding). But this is missing the large VCP-to-ground discharge current that would occur with a true grounded structure, radiating a correspondingly high magnetic field. A wise approach, at least during development time, is to arrange a test with the VCP (or HCP) alternatively floated via the 470 k, then directly grounded, and concentrate on the worst susceptible configuration. 2. How should the VCP be located with respect to the actual EUT target zone? Intuitively, and this is what the IEC document is suggesting, one would align the VCP center to face target zone. In fact, theory and experiments (14) have shown that the maximum current density, hence field concentration, is near the edges of the VCP. 3. The VCP and HCP are required regardless of nonmetallic or metallic type of EUT. There seems to be not much sense in discharging on a metal plate at 10 cm from an EUT, while this latter is already in a metallic housing, submitted to the much more threatening direct discharges. However, some rare situations (see Section 4.5.1) can justify this demand. 4. For EUTs with a very low height-to-perimeter form factor, such as 35 × 35 cm device only 5–6 cm high (e.g., a DVD player), there is no sense exciting the VCP since the E-field coupling from the HCP will be a much more severe threat. So, except for “going by the book,” ESD investigation and troubleshooting can be made with the HCP alone. 5. The E and H fields generated by the gun’s HV circuitry vary significantly with its tilt angle on the HCP (or VCP). With guns held vertically, Pommerenke and Frei (14) measured 2/1 H -field and up to 6/1 E-field variations between different guns. These ratios reduce to 1.25/1 if the gun is held co-planar with the HCP. On the other hand, the strongest coupling with the initial spike occurs with the gun held vertical. Thus, the dilemna was the following: •

•

The larger amplitude (vertical position) reproduces better the worst-case field near a human/metal discharge, but it aggravates the differences between various simulators. Differences are reduced with the gun held horizontally, but at the expense of a lesser field value.

Waiting for a better definition of simulator characterization, and at the risk of some undertesting, the second choice is retained in the IEC standard.

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4.4.4. Grounding the Simulator and the EUT The EUT should be grounded through its normal grounding conductor, to the ground terminal of the power outlet. If the EUT has no ground conductor (class II equipment) or is battery operated, it will then be ungrounded. In no circumstances should the EUT be directly grounded to the GRP, unless this is the way it would be normally installed in the field, as, for instance, airborne or automobile equipment. The return path for ESD pulse to the generator must be a large strap, its recommended length being 2 m (see discussion in Section 4.1.3 about how of this length can affect the rise time), bonded to the GRP via a “C” clamp or similar. This dimension is a trade-off between the need of a limited length with less inductance, and a sufficent slack for being able to move the gun around the EUT. This wire or strap must have an insulating jacket to prevent other uncontrolled ground loops. The simulator should not be grounded to the EUT frame or the table-top HCP, except for some exploratory diagnostics. Note This deviates from some older test methods, which showed in certain cases the simulator being grounded to the EUT itself. This is questionable since, in real life, charged people will have their feet on the ground, and not on the EUT cabinet. In addition, grounding the simulator to the EUT frame will decrease, or even nullify, the electric field gradient between the lower part of the EUT (especially the bottom plate) and the ground plane. This field change is important in the possible coupling to I/O cables near their entry points. When the EUT has no connection to ground (battery-operated system, completely floating power sytem, etc.), there must be a way to discharge the floating metal parts after each discharge. This can be made by touching them with a grounded wire loaded by a few 100-k resistors. Some ESD gun manufacturers provide a bleeder network attached to the discharge tip, which systematically remove the discharge after each shot.

4.4.5. External Cables and System Configuration Very often, the ESD test may have to replicate the conditions of a system configuration. There can be several reasons for this: For instance, the EUT may be one unit of a multiple box set in which case the vulnerability of the whole system must be evaluated by testing one box after the other. Alternatively, the EUT may be designed as stand-alone, “attachable” to several types of peripherals or ancillary equipment. In this case, the peripheral devices must be connected to the EUT, even if they are not themselves being tested. However, in the latter, it is necessary that the units not being tested have an ESD level consistent with the test objective (see Section 5.7).

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121

For a system configuration, the whole system must be installed over the GRP. If this is not practical, one ground plane per box can be used, provided that these planes are interconnected by wide straps. All the external cables that can be connected to the EUT in its maximum configuration should be in place and be laid out in a typical installation arrangement. To avoid too much variance in results due to different heights, they should be laid at a constant, repeatable height above the ground plane. Unless other heights are dictated by specific applications, a height of 10 cm, using wooden or plastic spacers, is a good average.

4.5. ESD TEST ROUTINE AND DISCHARGE PROCEDURES 4.5.1. Preparation of EUT for Test Readiness 1. Determine a clear, indisputable malfunction status that can be recognized without the need of an external oscilloscope, data-logger, and the like such as hard-error, wrong readout, inadvertent reset, alarm, on power down. This point is very important. No external ancillary equipment should be used to diagnose a fault condition because the very presence of additional probes and cables, and the monitoring device itself, can cause the EUT to fail at lower levels and give wrong test results. Very possibly, the oscillscope or data-logger can itself be disturbed by the ESD and give misleading information. The only exception would be by using a fiber-optic link to detect a change of state of some critical signals; but this assumes the EUT is already fitted with such diagnostic commodities. Therefore, if the EUT is a programmable device, it may be useful to develop a software routine that: • •

Exercises continuously all EUT operations, in closed loops without requiring an operator intervention. Indicates clearly by a printout, display message, alarm, buzzer, indicator light, dead display, locked keyboard, and the like that a fault has occurred.

With a large computer-based system, it would be sound to develop for all the transient immunity tests—not just ESD—a software that exercises every special-purpose routine, designed to operate in specific hardware areas. This will give a better efficiency for the hardware test program to approach a 100% probability of shooting in the worst sensitivity window, without running an excessively long test. It also facilitates the error diagnosis and faultly hardware location. It is not recommended to go to the extreme by trying to synchronize the ESD pulse rate with the EUT operation. Static discharges and machine cycles must remain two independent events (see Section 4.7).

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Chapter 4 ESD Diagnostics and Testing Type of equipment

YES

Metal covers on six sides ?

D-ESD only

NO

I-ESD (For instance : 4 – 16 kV for personnel ESD)

D-ESD • On all metallic touchable parts • On all arc-reachable parts

Figure 4.25 Decision chart for discharges mode. Notice that a D-ESD is practically always to be attempted on a plastic-covered product because of the possibility of a few metallic targets.

2. Make a zoning by dividing each side of the equipment into approximately 0.1-m2 (30 cm × 30 cm) areas. Mark/code each ESD target area. Include signal cables and power cord entry areas. Determine if the discharges will be entirely direct (D-ESD), indirect (I-ESD), or hybrid (Fig. 4.25). It may seem wasteful applying I-ESD on a 6-sided metallic housing and, indeed, it generally proves to be useless, whereas the worst suspeptibility is found by D-ESD. However, there are rare cases where an I-ESD test with a metallic EUT reveals a weaker failure level than a direct discharge on the envelope: This happens when the EUT has much smaller dimensions than the 0.50 m × 0.50 m of the VCP, and is equipped with unshielded (or poorly shielded) external cables. In this specific case, the cable exposure to ESD field is stronger with the VCP than with the direct discharge on the EUT.

4.5.2. Application of the Discharges 1. Set the ESD level at about 3 kV (for a personnel-type discharge) or other determined value, depending on whether it is an investigation or a quality control (QC) test.‡ ‡ Some standards (e.g., IEC) recommend that, with D-ESD, the test be started only at the required immunity level, without passing by the lower levels, but this is risky. Even with D-ESD, EUTs can exhibit the following response: Assume Vs is the specification level: For voltages Vi < Vs , the discharge current follows a certain path on the EUT, eventually inside. For levels > Vi , and up to Vn , internal arcings can take place, giving way to a different current path that can be more, but sometimes less, disturbing than with a test at Vi . By testing only at the highest level, one could miss this response. It is safer testing at ALL inferior levels.

4.5. ESD Test Routine and Discharge Procedures Metal spring

Conductive paint

Metallic name plate/logo

Magnetic head LCD module with metal rim

123

Metallic connector PC board

Metallic card frame Targets : • Accessible metal parts connected to internal conductive parts • Floating metal parts (no arc, but E-field coupling inside) • Internal parts reachable by arc

Figure 4.26 Fictitious plastic equipment showing potential D-ESD targets.

2. Zap each of the coded areas marked in the preliminary step. If this area includes switches, keys, indicators, connectors, screws, rivets, and the like, apply the discharge on those points. Apply also the discharge on the seams, slots, display edges, and any protruding shape, angle, or surface discontinuity existing in the area. Otherwise, simply apply the discharge in the middle of the coded area. If the EUT housing is plastic, perform indirect ESD, applied on the edge of the HCP and of the VCP, at 10 cm from the target face. However, a direct discharge should still be tried on screws, rivets, decorative trims, and the like as suggested in Figure 4.26. There can be EUT areas that are accessible only under specific circumstances, such as: • •

Parts touched by end user during service (batteries, cassettes, ink cartridges., etc) I/O connectors not equipped with their cables.

Since some of these service operations are performed “Power On”, the corresponding zones should be tested with a minimum requirement of no damage or no permanent change of conditions (loss of data, alarm, etc.).§ § Some

standards (IEC) recommend that these areas be exempted from the test. In our opinion, this exemption is not justified since these operations are often done with the equipment being simply in stand-by. For instance, metallic receptacles, even with recessed female contacts, can still be reached by a frontal air discharge before the finger even touches the peripheral shell.

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3. For those targets that cannot be touched by direct contact (pointed tip), use the air discharge. 4. Repeat the discharges until the prescribed number have been applied without unacceptable EUT response. If no minimum number of pulses is prescribed, use 50 as a default, in each polarity. However, the minimum number of pulses to guarantee the test depends on the complexity of the EUT operations (see Fig. 4.30). Section 4.7 discusses this problem of the number of trials more in detail. 5. Repeat step 4 for all coded areas and record which ones failed. If none failed, increase the level by 1 kV and rerun the test. Above 8 kV, most specifications recommend changing from contact discharge (pointed tip) to air discharge (round tip). 6. For each failed area, decrease the ESD level to find the go/no-go threshold, and record it. 7. Starting with the weakest spot, apply EMI-hardening methods, described in Chapter 5, to meet 8 kV, 15 kV, or other objective. Many simulators have a selectable repetition rate. This is a useful feature because manually applying 50 or more discharges times n points in a single-shot mode would be tedious. Also, for a first check with low ESD voltage, a quick sweep of all the target zones with accelerated pulse rate such as 20 or 50 pulses/second can give a rough estimate of the immunity, saving a lot of time. This first scan, intuitively thought of as a quick way to detect the weak spots, is in fact a way to eliminate the nonweak spots, by using an accelerated pulse rate. Within 1 min (at 50 pulses/second), 3000 discharges have been injected, giving a decent confidence that the selected area is fairly immune. Then, and only then, are the areas that did not pass this first exam candidates for a deeper search of the weakest spots (quite often, the designer assisted by an EMC engineer may have guessed where the weak spots are). These will be submitted to the number of specified discharges. As soon as a failure level seems to have been reached, the repetition rate must be slowed down sufficiently for allowing EUT software recoveries (if it has such features); otherwise, it could be stuck in a repetitive error mode, misrepresentative of real ESD situations where there are never several ESD events per second. Another phenomenon may occur that also fouls up the test if too fast a discharge rate is selected. Some circuits have very high input resistance; if, in addition, their 0-V reference is floating, the ESD bleed path to ground can be rather intricate, with an R,C discharge time constant that can reach tens of milliseconds. This means that the first ESD may induce a voltage pulse that is not sufficient to upset the device, but will leave a residual voltage that has not dissipated when the next pulse comes. A new residual voltage will add up to the previous one, and so on. After a certain number of pulses, the stack gradually reaches the upset level, causing a malfunction that is mistaken as a “true” ESD

4.6. No Error/No Damage Concept: The Several Layers of Severity

125

failure. The typical symptom in this case is an EUT that is insensitive to the first discharges, but will fail regularly after the same number of pulses. Therefore, because of the two possible EUT responses mentioned above, it is a safe practice to check, by slowing down the repetition rate, whether the ‘‘fail” level is correlated with the pulse rate. For the test validity, what is important is the minimum number of pulses to apply, not their repetition rate. To help document the test results in an orderly manner, a test log form is suggested in Figure 4.27. It will allow one to keep an accurate track of the failing zones, and record the fixes that worked and those that did not. Too often, this is neglected and people have to “reinvent the wheel” at every test. A dual indication “RUN/FAIL” is also recommended to show the level at which the EUT undoubtedly meets the criteria and the level at which it fails.

4.6. NO ERROR/NO DAMAGE CONCEPT: THE SEVERAL LAYERS OF SEVERITY Like any surge-type test, testing for ESD involves threshold criteria. Before testing, the designers of the EUT as well as the test people must clearly define what is to be considered a failure. Too often, statements are made like: Our system has been tested up to 8-kV ESD. Does this mean: 1. The system does not exhibit ANY malfunction up to and including 8 kV? 2. The system does exhibit malfunction starting 8 kV? And if so: a. Were these malfunctions only soft, self-recovered errors? b. Were they hard errors? c. Were they solid damages, requiring component replacement? To clarify the situation, Figure 4.28 shows a three-limit ESD criterion. No voltages have been put on the scale since they will depend on the type of product and the type of market (15). For instance, in selecting the actual ESD test voltages one should consider: • • •

The likelihood of high human activity around this product The type of environment (controlled or uncontrolled RH, antistatic floor carpeting, etc.) The sensitivity of the user to a temporary malfunction or error; that is, how often a week or a month can a malfunction occur and be considered “tolerable” by the user? This can depend on the price range of the product, the seriousness of a temporary loss of data for the customer, and, finally, the general EMI immunity claimed in the product specifications.

Up to V1 , the lower level, no malfunction at all (recoverable or not) is tolerated. Consider, for instance, an airline reservation terminal that exhibits

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Chapter 4 ESD Diagnostics and Testing

EUT:

Test Date: Prototype:

Test Type EUT

Pre production /Release test: Qc test:

Config. & Program Used:

Extern. Cables:

Simulator:

Checked:

Ω

R discharge: pF

C discharge:

Number of discharges / point: 5

Points of discharge 1

2

4 3

Point VESD Result +/− N° Direct/Ind. kV 1 to 4

Comments failure, mode, fixes...

EUT response: 1. Perform, not altered 2. Self-recoverable failure 3. No-recoverable failure, but no damage 4. Solid failure or permanent loss of data

Figure 4.27 Suggested ESD test log form.

Figure 4.28 Multilevel ESD test criteria.

4.6. No Error/No Damage Concept: The Several Layers of Severity

127

recoverable errors for 3-kV personnel ESD. The number of ESD events exceeding 3 kV in a counter type of environment is very high (Section 1.4). Even if the ESD-induced errors are automatically detected and the transaction is canceled, then retried, these operations take some time, and this terminal will spend too large a percentage of time recovering from errors, especially during the winter/spring season. From V1 to V2 , errors are permitted if they are “transparent” to the user, that is: They are self-corrected. They do not require a user intervention (halt–restart, data reentry, program reload, etc.) to restore normal operation. Above V2 and up to V3 “hard” errors are permitted; that is, this level is high enough to have a low probability of occurrence, which will not upset the user if an operator intervention is necessary to resume normal operation. However, it may be required that the error be visible to the user and not left unnoticed since it is not automatically corrected. No component damage is accepted, even those parts (like a fuse) that are replaceable by the client. No unsafe condition, leading to safety hazard, or expensive financial prejudice should result from this temporary upset. The IEC-suggested ESD test levels (see Chapter 3) are only indicative. In fact, each industry, government agency, or professional association decides the ESD immunity level for its respective products and applications. Examples of products/application categories are: Category A: Household Appliances and Entertaiment Devices

High human activity, uncontrolled environment. Aggravating factors (e.g., dust and friction with vacuum cleaners, cloth friction with dryers, etc.), but utilization is rather fault-tolerant as long as there is no solid damage. Category B: Office Products, Small Business and Point-of-Sale Equipment

High human activity, uncontrolled environment. RH can be as low as 15%, and any type of floor/carpet may be involved. Irritability factor quite high, but partial alteration of data not catastrophic because generally detectable by operator or user. Category C: Large Business Computers, Scientific or Medical Computing Centers, Large Systems Handling Critical Data (Banks, Government, etc.)

Such applications require high reliability, hence a low error rate (ER), but on the other hand the RH, floor treatment, and general environmental factors are fairly well controlled.

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Examples of coherent ESD test criteria, adapted from ANSI.C63-16 are given in Tables 4.2 and 4.3. These test levels correspond to discharges applied with a 330-/150-pF IEC or similar ESD simulator. Table 4.2 shows test levels for data processing equipment (officially designated as “information technology equipment,” or ITE). Two classes of severe environment are considered: Controlled environnement corresponds to: RH always> 20% and antistatic floor material Standard (but eventually severe) environment corresponds to RH being as low as 10% for some periods and synthetic carpet

Table 4.2 Suggested Personnel ESD Test Values for Information Technology Equipment Test Voltage

Criteria

Environment

Worst allowed EUT response at and above the indicated voltage

Controlled

Standard

2-kV contact

4-kV contact

Temporary loss of function or performance,

4-kV air 4-kV contact 8-kV air

8-kV air 8-kV contact 15-kV air

self-corrected Loss of function or performance, requiring operator intervention to be corrected. No permanent damage or loss of data

(Optional, Furniture Test) × (1 kV)

Self-corrected errors

×

Hard errors (no damage or loss of data)

(2 kV)

Table 4.3 Suggested Personnel ESD Test Values for Consumer Equipment Test Voltage Air Discharge (kV)

Criteria

Contact Discharge (kV)

5

3

10

6

15

7

(Worst allowed EUT response) Audible click, or visible short noise in video/audio No loss of function or performance, even self-corrected Momentary self-recoverable changes in user interface or equipment performance Operation suspended but can be restarted by normal user interface, without power OFF/ON

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129

Starting with the test levels, and doing a backward calculation based on the ESD current statistics, we can approximate that the corresponding accepted error rate (ER) for standard environment is: Less than 1.5 soft errors (autorecoverable) per shift for the worst-case periods of the year and in the worst possible installation Less than 0.3 hard error (no damage, but requiring operator action to be corrected) per shift Notice that no test levels are indicated for furniture discharge since this test is not widely practiced. If a furniture ESD test was also to be made, optional test levels are indicated that would guarantee an ER consistent with the accepted personnel ER of the standard environment. They are based on Simonic’s statistics (see Chapter 1) of furniture events, with a simulator having a 45- equivalent dynamic impedance. Another widely applied example of specific ESD test criteria is found in automobile electronic devices (Fig. 4.29). The influencing factors are multiple and may vary depending on manufacturers: 1. Environmental a. The device can be accessible only from inside the vehicle. b. The device can be accessible from outside as well. 2. Related to the condition of the vehicle: stopped with engine off, stopped with engine on, or running 3. Related to the benign to critical aspect of a malfunction a. Comfort equipment without direct impact on driveability b. Equipment providing information on driving and engine conditions c. Equipment influencing safety (steering, braking, air bag, driver seat control, etc.) In this latter case, the ESD test voltage can reach 25 kV.

4.7. THE ERROR PER DISCHARGE CONCEPT OR MULTIPLE-TRIALS APPROACH Not exclusive of, but rather complementary to, the severity layers, another concept, the error-per-discharge probability, has been recommended, although not widely used. Good rationales for this are explained in various studies (16–19). The basic principle is that the unwanted response (UR) of a machine is a probabilistic encounter between a randomly occurring event—the discharge—and the “sliding window” of the most vulnerable configurations of certain critical logic inputs (Fig. 4.30). The collision of these two random events cannot be predicted by a deterministic approach; therefore, any standard, such as IEC or others, requiring simply 10 discharges without errors is ill-fated. The unwritten, but implicit, statement that “if the EUT did not fail in 10 discharges,

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1. Test on vehicle, using car frame as reference

Device under test (DUT)

ESD gun

220 VAC/HV DC converter

DUT

ESD gun

Metal ground plane

2. Test on vehicle, using ground level reference

Figure 4.29 Example of ESD test setup for car on-board equipment (from ISO TC-22).

it will never fail” is about as sound as throwing a pair of dice 10 times and deciding that if you do not get two aces, you will never get two aces. Instead, the fail/no-fail decision must be based on a large enough number of independent trials, which the theory of probabilities helps us to define. The rationale is that the error sensitivity of a machine to ESD is almost never a step function. Figure 4.31 shows conceptually an “ideal” behavior (curve A), of a machine experiencing no error at all (regardless of how many pulses are applied) below a given ESD level, then making one error per pulse, that is, P (error/discharge) = 100% above that level.

4.7. The Error PER Discharge Concept or Multiple-Trials Approach

131

ESD Induced Glitches (a) 0

1

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1.5V VIL Threshold #2 for pulse width 1 ns VIL Threshold # 1 0.3V for pulse width ≥ 5 ns

1 ns 5 ns A

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C

D

E

No Error: Amplitude too low No Error: Logic is in “HIGH” state No Error: Duration is too short for VIL # 1, and amplitude does not exceed VIL # 2 Error: Duration is ∠ logic rise time, but amplitude exceeds VIL # 2 Error: Amplitude and duration are above VIL # 1 (b)

Figure 4.30 (a) The ESD-induced transient is a random event that occurs anywhere vs. the sequence of logic operations and message formats of the machine. A minimum number of discharges is necessasry to explore the worst-case coincidences of the ESD transient with certain patterns of logic transitions. (b) In addition, to cause a logic error, the glitch amplitude and duration must exceed certain values (fictitious example shown for a 3.5-ns logic pulse train).

By comparison, the behavior of an actual machine (curve B) is plotted as the number of errors per ESD event, which is less than, or equal to, unity since in fact: Number of errors per ESD pulse =

1 Number of pulses to cause an error

This number is recorded versus the ESD voltage applied by the simulator. Due to the random occurrence of the ESD event versus the operations of the

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Chapter 4 ESD Diagnostics and Testing Number of 1 discharges to cause one error

Errors/Discharge

1 10−1

101

10−2

B

102 A

10−3

103

10−4 2

4

6

8 10 VESD (kV)

12

14

16

104

Figure 4.31 Concept of error per pulse: the behavior of a machine during ESD test is not a step function (a), but a steep slope like (b) due to the random occurrence of ESD pulses vs. logic operations.

EUT, the error/pulse concept allows the replacement of the go/no-go concept with a better approach. The following assumptions are made: •

•

• •

The result of each trial (an ESD pulse) is independent from the previous one: Chances of hit-or-miss are the same for each trial, that is, the EUT has no “memory” of the former events. The stimulus of each event is received exactly the same way by the EUT: This assumption is not totally true since an ESD test carries substantial uncertainties, but we will accept it. The ocurrence of an UR to an ESD stimuli is of random nature for logic errors only. Component damage is practically never related to a “high” or “low” status of a logic input or to a byte pattern but to the coupled voltage and current exceeding the safe limits of the component. Therefore, the URs, which are addressed here, are exclusively logic errors.

A 100% confidence that no error will occur for a given ESD level would require an infinite number of trials. Hopefully, probability calculations for large sample sizes can help us, in several ways: •

It is generally sufficient, for ESD-related errors, to guarantee that the machine will not suffer more than Nr errors per day (or shift) or per week; such a figure is application-dependent and can be established by the product manager as being what the users can tolerate.

4.7. The Error PER Discharge Concept or Multiple-Trials Approach •

133

This number Nr will be confronted with the number of ESD events per shift exceeding a given voltage, such as in field conditions: Number of errors/shift

= P (Error, V ) × N (EventV ) per shift

(4.1)

with P (Error,V ) = Probability that the machine will make an error, given a discharge voltage V N (Event ≥ V ) = Number of ESD events/shift that will equal or exceed V One can derive such criteria that, for an ESD test, Error rate at given levelVESD =

Tolerable number of errors/shift Number of events/shift  V

(4.2)

The probability of ESD events decreases continuously with increasing voltages. Inversely, the percent probability of error per pulse increases with increasing voltages (Fig. 4.32). Unfortunately, the EUT error curve is not known by the designer and has to be approached by a sufficient number of trials. Probability theory tells us that to guarantee no default within N occurrences, the number of trials has to be much greater than N . How much greater depends on the degree of confidence that is desired. For instance, to guarantee less than one failure in 50 occurrences, with a 95% confidence level, a minimum of 150 trials without error is necessary. The residual risk, then, is twofold: 1. Accepting a machine that should have been rejected, that is, number of trials was too low (type 2 decision error) 2. Rejecting a machine that made one error but could have been accepted (type 1 decision error) In this case, the escalation strategy (given as informative annex in recent drafts of IEC and ANSI standards) allows for one error, provided an additional number of zero-error trials be performed. Rather than any arbitrary number of discharges imposed by a “fits-all” clause, this approach is personalized to the application, the market, and its environment. In addition, although a certain percentage of risk remains, a substantial margin is inherent to the method: •

•

The ESD event statistics (see Chapter 6) selected were for the worst case of a given class of the environment. Actually, the lower RH does not exist 100% of the time nor for 100% of the installed equipments. The IEC type of test systematically simulates a hand/metal type of discharge. Except for specific cases where the equipment is always touched first with a tool, a coin, or a key, the handheld sharp object represents only a fraction of the total number of ESD events.

Chapter 4 ESD Diagnostics and Testing

1

0.1

0.1 Confidence interval

0.01

0.01

Nevents

0.001

NER

2

0.001

Machine Response N Errors/pulse

Number of ESD events/shift (8 hr) busy office uncontrolled RH and floor-type worst season

134

4

6 8 10 12 Vi VESD (kV) expressed as simulator voltage For each given ESD level Vi, the probable machine error/shift is equal to : Nev × NER

Figure 4.32 Example of combined curves for ESD event rate and machine error curve.

4.7.1. Practical Application of the Error per Pulse Concept An example will describe how the error rate can be handled: Figure 4.33 shows a histogram of personnel ESD for the worst-case months (RH% = 15–20) compiled after Simonic data (see Section 1.4.1). Although the ESD events were given in amperes, they have been translated into an equivalent IEC simulator voltage assuming a uniform impedance of 300 . This will allow obtaining the results directly in the test levels. Assume that the objective is to have less than 1 error/shift (5 errors/week) during the worst-case months and for the worst-case installations (synthetic carpet). The EUT error profile, in its initial state, has been plotted on curve A. For 7 kV with an IEC simulator, there is one error per shot. Decreasing to 4 kV, it takes, on average, 30 pulses to cause one error. For each 2-kV interval of the histogram, the corresponding error/pulse figure is multiplied by the number of events per shift, to come up with the number of errors per shift. The total amounts to 2 errors/shift, which is excessive. By default, one can assume that the slope of the error curve has nothing to do with the fixes (shields, decouplings, etc.) existing in the machine, but rather with the nature of the operations and messages performed by the EUT. Therefore, hardware improvements will not change this slope but merely shift the curve. For instance, curve B shows the same unit after certain ESD fixes. The total is now 0.65 error/shift, which is below the one error objective.

4.7. The Error PER Discharge Concept or Multiple-Trials Approach

1

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8

10

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0.3

A

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12 10 VESD (kV)

Error/Pulse A before B after Improvement Improvement 0.015 0.1 1 1 1 1 1

Error rate of the EUT

Number of events per shift for RH = 15%–20 and worst environment

2

135

negligible 0.001 0.01 0.1 1 1 1

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0.1 14

0.001

16

Events/Shift for worstcase months 12 3 0.5 0.4 0.3 0.2 0.1 Total

Error/Shift A

B

0.18 0.3 0.5 0.4 0.3 0.3 0.1 2

neglig. 0.003 0.005 0.04 0.3 0.2 0.1 0.6

Figure 4.33 Application example of the error per pulse method.

Boxleitner (20, 21) has given very good examples of a comprehensive test plan, taking into account the increasing event rate with low-voltage ESD. A short excerpt of it is shown in Table 4.4.

4.7.2. ESD Test Plan with Cost-Effectiveness Constraints For mass production situations, it can be desirable optimizing the ESD test to avoid overtesting, hence unnecessary hardware costs. For instance, let us consider a low-cost personal computer, or similar microprocessor-based equipment, with manufacturing forecast of 100,000/ year over 3 years. Preliminary tests have shown that an additional $2 of hardware cost is needed to upgrade the ESD

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Table 4.4 Events

Example of Test Plan, Weighted by Increased Probabilty of Low-Voltage

Maximum Number of Test Voltage Number of Applied EUT Failures Corresponding (kV) Discharges Recoverable/Nonrecoverable Calculated Failure Rate 5 10 12.5 5

600 300 45 12

24/0 21/0 9/0 3/0

0.06/0.005 0.1/0.01 0.3/0.07 0.5/0.2

immunity from 6 to 7 kV and overcome a test uncertainty with the standard 10 discharges program. Therefore, the manufacturer is facing a potential expense (or savings) of $600,000 over 3 years. It is worthwhile to investigate an optimized test plan to decide what is really needed. A first approach for increasing the test efficiency consists in devising a deterministic—instead of random—test strategy (22). It appears generally that only very short time frames of the various program executions are actually vulnerable to ESD-induced glitches. For instance, more than 99% of the time the software-driven logic transactions inside the machine are in rather shake-proof states, with critical phases happening less than 1% of time. It seems interesting to develop a test software that would run repeatedly vulnerable program cycles, and a fast ESD repetition rate that would increase the chances to shoot in the worst susceptibility window. Some studies have even gone as far as suggesting to synchronize the ESD discharges with the principal clock frequencies of the EUT to reach a close to 10/10 “hit-the-mark” score. As attractive as they seem in theory, these approaches are confronted with some hard facts. It is true that creating a specific test software to emulate exclusively the vulnerable sequences is feasible, and this approach has been applied successfully with some products. But it has to be done over and over for each new product or new version of an existing one. This is upfront money to be spent before sales have actually started, which will only pay-off along the product life, so a financial analysis of the return-on-investment needs to be conducted. Next, synchronizing the ESD pulses with subnanosecond clock pulse edges is not an easy task, in practice: From the point of discharge to the susceptible circuit, there is a 30-ps/cm propagation delay of the field wavefront, that is, 0.3 ns for a 10-cm trip. Thus, for each discharge point the exact firing of the discharge should be adjusted for compensating this time lag. And finally, this technique is conflicting with the self-recovery routines: On one hand, forcing repetitive ESD pulses to reach the worst place at the worst moment is overkill, while at the same time a smart software in the machine is spending time correcting the errors. Another refinement, also described by Pratt and Davis (16) is more practical. It consists in assigning a weighting factor (0–100%) to each side or zone of the machine, to represent the percentage of ESD events that will occur at that position.

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137

The sum of all the weighting factors over all test points is 100%. Thus, parts of the machine that are less exposed than others will be given a lesser penalty. The merit of this method lies in the fact that it replaces the traditional single go/no-go voltage with a finer characterization of the EUT response. However, the search for machine error rate and position weighting can be delicate and is not the kind of iteration to be made during a manufacturing QC test. Therefore, the following is recommended: 1. At the end of the design stage, when the prototype is sufficiently representative of the final product, especially concerning the logic speeds, clock rates, architecture and sequence of the logic functions, interface protocols, and the like, a characterization of the EUT error curve will be made, taking into account: • Machine error rate over the complete voltage range, in 1- or 2-kV increments • Position weighting, if justified • ESD environmental weighting (controlled vs. uncontrolled RH, etc.) 2. Knowing the above, engineering tests will be pursued to see if the machine meets the maximum error/shift or error/month objective, and improvements will be made if necessary. 3. From then on, the routine QC test will not need to repeat the above but will simply check the average error rate at one voltage only. For instance, in our example of Fig. 4.33 if the simulator is set to 10 kV, the QC will ensure that it takes, on average, a minimum of 4 pulses to cause one error. As an added security, a sample check could be run to verify that, at 7 kV, the EUT makes less than1 error in 100 pulses (something that, relying on the IEC criteria, would have good chances to go undetected). This is acknowledging the fact that in real environments, there will be more 7-kV events than 10-kV ones, therefore, the machine exposure is greater. This also allows sample comparison and detects possible degradation after hardware changes. A clear effect of such a problem is that the slope of the error curve would not change, but its position will shift. The test procedure imposed by the QC must guarantee that the “average number of pulses to cause an error” is based on a sufficient number of trials (21). For instance, just doing 100 discharges without error is not enough to declare that the error rate is less than 1%. Such a 1% objective, with 95% confidence, requires a minimum of 300 discharges at the same point (Fig. 4.34).

4.8. ESD TEST DURING DESIGN AND DEVELOPMENT Given that ESD testing is very efficient and relatively easy to conduct, it can be applied to the machine as soon as an early prototype exists; and, furthermore, as soon as functional subassemblies exist. For instance, an early ESD test is easy to perform on a breadboard prototype using an indirect discharge setup.

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3 × 103

Number of test pulses

103

% 99 V: 95% V: 90% V:

300

100

30

10 10−3

3 × 10−3 0.01 0.03 0.1 0.3 Permissible failure rate (error/pulse)

Example:

1

To guarantee ≤ 0.03 error per discharge, with 95% confidence, a test program with a minimum of 100 discharges without failure is required

Figure 4.34 Required number of discharges to apply with zero faillure.

A most rewarding approach is to start an ESD immunity evalulation at the PCB level. Later on, when functional cards have been designed and the first run of prototype boards is available, the following is suggested: •

•

•

Identify the principal Printed Circuit Boards (PCBs) in the machine, that is, those that perform essential functions and constitute block diagrams in the machine architecture. Prepare each of those boards so they can be tested as stand-alone items. Identify few lines to be considered as “witnesses” of the card’s good condition (e.g., WATCHDOG, RESET, IRQ lines, etc.) and equip them with a LED soldered directly on the card, so that when everything is normal, the LED is ON (or OFF). Preferrably, provide a dc power source without the need of an external bench supply. The easiest way to do this is to merely attach an ordinary battery pack to the card with adhesive tape, and solder the terminals to the Vdc bus via ultrashort, twisted wires. Perform an I-ESD test of the board , as shown in Figure 4.35. The discharge is applied on a metal plane, the card being placed at a distance

4.8. ESD Test During Design and Development

Supply batteries

139

ESD gun ground strap

“C” clamp “Witness” LEDs

Insulating spacers Copper or aluminum foil 10 cm (4” ) typ.

Figure 4.35 Workbench mounting for early ESD testing of a PCB. The height h depends on the final configuration of the machine. It can be equaled to the average distance of the card from the bottom plate or the closest wall of the housing. By default, 5 cm (2 inches) can be used. The cable will be added later to check the immunity of the I/O interfaces. Discharges are made following a route around the card perimeter. One discharge point at each corner plus one midway is usually sufficient.

that is representative of the actual card-to-housing distance of the future machine. The test voltage depends on the criteria for the final product. If the product is planned with a plastic, nonconductive cabinet, the ESD voltage should be set as for the final product. If the machine will be a metal or metallized cabinet, a certain derating should be taken. This derating can be found by testing a similar machine or a mock-up (same size, identical card location) with and without covers, the difference in kilovolts between the two conditions is the derating. By default, a good rule of thumb is to test each stand-alone card for 6 kV. A machine equipped with cards that sustain that level will not be too difficult to harden up to 15 kV or more. This single card test probably represents some of the best invested time in the entire ESD strategy (perhaps even in the whole EMC strategy). It reveals PCB layout weaknesses (see Chapter 5) at a time when they are relatively easy to correct. Using the setup of Figure 4.35 makes it quite simple to identify weak spots and find the peculiarity of the layout in that area that causes such weakness. Nonetheless, by no means can we consider that zapping a bare PCB stripped of all its associated cables and surrounding hardware is a one-to-one anticipation of the actual machine behavior. •

Harden the I/O zones; this remains to be done when the card alone has been brought up to the desired level. A well-hardened card can still make

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errors if ESD-induced glitches enter by the connector pins (remember, the test done so far involved only the direct radiation pickup by the card). To this end, a typical length of flat cable, multipair cable, or any conductor that replicates the reality should be plugged on the card connector(s). Due to the localized nature of ESD, it is generally not necessary to put more than 1 or 2 m of cable (1 m of cable is already beyond the half-wave length for the typical ESD bandwidth). On its other end, the cable should be terminated with passive resistors simulating the actual impedance seen at this end. The test could be refined by connecting this cable to an exerciser that will actually reproduce the normal I/O transactions with the card. In that case, great caution must be taken to be sure that the part of the gear that is stressed is actually the card, and not the exerciser.

4.9. ESD FOR FIELD DIAGNOSTICS AND FORCED CRASH METHOD Transfer function theory states that any system can be viewed as a black box with input/output ports. To the degree that a system can be approximated as a two-port network, its transfer function can determined very conveniently by measuring its response to a step impulse. Just like there are many instances where one would use a small coin as a tool because no real screwdriver is available, the handy, easily carried ESD generator can be used as a quick, first check of the susceptibility of an equipment to almost any kind of EMI . A properly simulated ESD event can excite and reveal much more of the weaknesses of an equipment than its mere vulnerability to static discharges. Testing EMI susceptibility by traditional methods is a long and complex process. Although it cannot pretend to replace these conventional and mandatory compliance tests, the wideband field of an ESD flashes the equipment all at once, revealing many of the same weak spots that a true EMI test will explore. Furthermore, an ESD test is simple to run, hence ideally suited to on-site testing. Forced crash is a technique by which one decides that instead of waiting for a random, hard-to-catch problem to show up, he intentionally injects into the equipment a very fast transient pulse that broadly covers the frequency spectrum of any possible intermittent event, ESD or other. Very often, microprocessor-based devices experience random malfunctions once they are installed, even though they were tested compliant and declared good for shipment by the manufacturer QC department. These environmental problems quickly become exasperating because of their typically intermittent and inconsistent nature. Usually, after the first customer call, a field technician will check out the machine, run diagnostics, reinstall software programs, trim some settings, replace a couple of PCBs, and leave after a last, positive sanity check (needless to say, no malfuction occurred while the technician was there to see it). Back at the office, the technician in good faith will probably report an NTF (no trouble found). Of course, the problem recurs at the same unpredictable rate,

4.9. ESD For Field Diagnostics and Forced Crash Method

141

correlated to nothing, or to so many things that no explanation seems possible. The customer asks for a higher level of assistance and the district field engineer comes to the rescue, and so on, until someone eventually calls an EMC specialist. Is the problem an ESD one? Maybe or maybe not. In any case, forcing an EMI failure with an ESD test applied on site is a powerful diagnostic tool and a very localized stimulus. It will be merciless in pinpointing hardware EMC deficiencies. Since the pulse is calibrated, progress can be quantified, and a susceptibility map can be drawn. This on-site procedure is rather similar to the ESD test in the lab, but there are some differences: You are not testing a development or premanufacturing unit with diagnostic tools, but a machine actually in service. Make sure that the test does not lead to a risk of serious material damage or even safety hazard. Try to inhibit temporarily any peripheral that could create such risk. 1. Install a temporary ground plane (a double-fold of kitchen foil will do) underneath the machine. This will stabilize the RF reference and improve the test repeatability, so that the results can be compared to typical immunity objectives. Do not try to ground the EUT to this plane since it is normally grounded by its power cord. Connect this ground plane to the next safety earthing (e.g., a power outlet ground terminal). 2. Using chalk or water-soluble pen, make a zone/coding on the EUT housing, as described in Section 4.5. 3. Establish a clear, indisputable “fail” criteria of the system, preferrably with the same symptoms as the problem that was detected by the user. 4. Ground the ESD gun to the reference plane. Set a low level, such as 2 kV, and zap every coded area, including switches, keys, screw heads, front panel edges, display edges, and the like. Do not forget the areas around connectors and cable entry ports. Start with at least 50 pulses of each polarity, in a repetitive mode (5 or 10 pulses/second). If the product is mainly plastic, apply I-ESD by discharging on a metal plate located about 10 cm (4 inches) from each EUT face. 5. Increase the level by 1-kV steps until you reach a fail level, or the ESD immunity objective plus a 1-kV margin, whichever comes first. 6. If failures are detected, come back to the failed area with a single-shot mode to allow for possible automatic recoveries. 7. Record and map the confirmed pass and fail areas. 8. For each failed area, lower the test voltage until reaching a sure no-fail level and document the results as suggested in the log form shown in Figure 4.27. Once repeatable pass/fail levels have been confidently determined for all areas, what remains is to inspect and critique the hardware immediately behind each failing area, and especially nearby cables and I/O ports. Cables are privileged points of ESD entry because thay act as efficient pick-up antennas for the ESD field around the discharge area. Then the induced currents are carried inside

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by shield pigtails, unprotected wires, and the like. For I/O cables, a radical improvement is obtained when unshielded, or poorly shielded, cables are changed for homogeneous shields plus metallic connectors with integral grounding to the mainframe. If a weak spot exists, a close look will probably show one of these typical flaws, detrimental to high-frequency immunity: • • • • • • • •

Improper high-frequency bonding and grounding of the machine parts, high-frequency wise Deficient subsystems or OEMs (Other Equipment Manufacturers) attached to an otherwise healthy system Poorly shielded I/O cables or original manufacturer’s cables and connectors replaced by cheaper look-alike (but not perform-alike) items Deteriorated shields or housing integrity, missing RF gaskets Mediocre filtering hardware or improperly bonded to the chassis Filter located too far inside Input and output wires of the filter tangled or harnessed together Safety ground wire forming a loop extending inside the housing

After quickly installable field fixes have been applied (23), rerun a test to see if the ESD critera are now met. Be sure to rerun the test on all zones, even those that were previously okay: ESD and Murphy are old mates, and a local improvement may have caused a degradation in another place (especially any change implying rerouting of wires). Document your progress with a new pass/fail map. Never remove a fix that seems to bring no improvement: Add them up to the final success. The philosophy behind all this is that if a unit at its site, with all its external cables and peripherals in place, is fixed to 8-kV ESD, it will be vaccinated against any type of short, fast rising transients, even if the actual reason for the field problem is never found . There are, of course, exceptions to this rule. One is that if the trouble was due to a casual power line overvoltage or undervoltage, lasting a half-cycle or so, an ESD check will not detect it. But such troubles are generally traceable by putting a spy monitor on the power line. Another problem is that more and more systems are using automatic recovery software, which tends to make the error invisible to the user. Yet, with some specific customer applications, repeated errors could indirectly cause problems. If this is suspected, the ESD simulator should be used continuously with a nonperturbing monitoring device (e.g., a fiber-optic link), synchronized to the ESD pulse repetition rate, making it possible to capture erroneous data. Finally, certain civilian environments, and many military ones, are exposed, for short time periods, to very strong ambient RF fields, from nearby radio or radar transmitters. However (portable transmitters and cell phones excepted), such exposure is generally not random and usually is detectable by a field survey.

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143

Warning

An ESD gun delivers high voltages, which could be dangerous for devices whose vulnerability is not known. Always start the test at low levels since temporary malfunctions occur generally well below a possible damage level. This is not a survival test : Do not zap directly parts such as connector pins, membrane switches, and LEDs, if they are directly wired to sensitive components, Keep away all people who are not absolutely required to attend the test (especially bearers of cardiac pacemakers). Isolate the test zone with a colored strip or any kind of temporary barrier.

4.10. HOME-MADE INVESTIGATION TOOLS AND DIAGNOSTIC HINTS Investigating ESD susceptibility after a failed test or an actual field problem can be very frustrating for someone with no experience or preliminary knowledge of the ESD coupling mechanisms. On the contrary, with some background and a minimum set of appropriate diagnostic hardware, it will turn into a rewarding experience. Besides the ESD simulator, a few basic tools are needed [more on this subject can be found in (23) and (24)]: •

• • •

A fast digital memory oscilloscope, with an equivalent analog bandwidth of at least 500 MHz, corresponding to the 3-dB bandwidth for a 0.7-ns rise time An E-field injection adapter to mount on the gun tip An H -field injection adapter to mount on the gun tip A shielded EMI-type of passive current probe, with a minimum 500-MHz bandwidth and preferrably a flat response (transfer impedance) for the 5to 500-MHz range

Because of the limited area that they cover, the two field enhancement adaptors can help finger-pointing equipment weaknesses like shielding deficiencies of the housing, breeches in a PCB ground plane, or unfiltered (or poorly filtered) input ports. The E-field injection adapter is added to the tip of the ESD gun (Fig. 4.36). Some vendors of ESD simulators are offering this optional feature. It can also be homemade with any round metal plate. For a 8-cm diameter, the disk has an area of 50 cm2 , which approached at 1 cm from the target area will create 5 pF of coupling capacitance, which is about 200  of coupling impedance for a 1-ns rise time. A bracket is used to hold the disk against the pointed tip and to provide a smooth return path for the discharge current. Without it, the gun would probably not trigger, or display a “misfire” condition. The bracket can be screwed to the ground return threaded hole of the gun. To make sure that the disk will rise at the

144

Chapter 4 ESD Diagnostics and Testing er sh red a w lde ze , so ire n o Nylon or PVC rod br ead re w all w h ent drilled 12 mm m c e Nylon screw S scr the r o o t ld ESD gun ie d tip Sh ate flo

Shield soldered to center wire Det ail AWG 12 or 10 for ground connection back to generator

S = 20 cm2

Dia. 5 cm Semi-rigid coax RG405 (2 mm dia.) Ring terminal soldered to the shield Center wire, fold back and solder Self-tapping screw 2.5 or 3 mm dia.

H-field adapter

E-field disc 80 mm dia. (S = 50 cm2)

10 kΩ Insulating spacer (nylon or PVC) Steel bracket Generator ground screw E-field adapter

Figure 4.36 Homemade E-field and H -field adapters. For the E-field adapter, any round metal plate, like the cap of a preserves glass jar or the like, can be used.

tip voltage, a 10-k, 5-W resistor is inserted between the metal disk edge and the bracket end, through an insulating spacer for preventing the 10-k resistor from being shorted by the mounting bracket. A 1-cm plastic rod can be used as a distance gage to keep the disk-to-target interval. When the gun is switched on, the disk rises abruptly to the full tip voltage, re-creating approximately the conditions of the E-field coupling from an I-ESD (see Section 2.4.2 and Fig. 4.12). The capacitive current is injected in the

4.10. Home-Made Investigation Tools and Diagnostic Hints

145

victim’s target as a short spike of about 3 A/kV. By starting with a low level, like 1 kV, this method can be used for a detailed exploration of the failed areas (25). Typical examples of vulnerable PCB spots that can be detected by this “teaser” include microprocessor-related lines like clock traces, RESET, WATCHDOG, and CHIP-SELECT. E-field sensitivity can also be found on special connectors (J-TAG), test pads, or FLASH programming pads because they present large footprints, generally not screened by the PCB ground plane. The H -field injection adapter is also added to the tip of the ESD gun (Fig. 4.36) and available from some ESD simulator vendors. This H -field radiating loop can also be homemade from a piece of semirigid coaxial (RG405), forming a so-called Moebius loop. At the drive end of the loop, the copper shield is stripped and left floating. At the return end, the center conductor is soldered to the shield and extended via a piece of AWG 12 or 10 wire (2-mm diameter) back to the grounding post of the gun. This forms a perfect H -field antenna, with the single-end grounded shield acting as a Faraday screen against the E field. With the dimensions shown, this antenna generates, at a distance D = 0.1 m from its center, a magnetic field pulse with amplitude H per ampere of loop drive: H =

I (A)S(m2 ) = 1.6A/m 4πD 3

For instance, with an IEC-type gun set to 2 kV (i.e., 7 A for the first peak current), the field at 10 cm will be H = 11A/m This correspond to the field that the target zone would see for an actual 2-kV ESD. Note In the near-field region, the H field from a small loop is falling-off like 1/D 3 . For the frequency range of concern, the near-field region extends up to 10 cm from the loop. Therefore, the given field is very localized to tens of square centimeters and collapses strongly as one moves away, which provides this investigation tool with a good directivity. This method is used for a detailed exploration of the failed areas, which can be responsive to H -field excitation: shield leakages, nonscreened traces loops on a PCB, missing, or poorly bonded cable shields. The EMI passive current probe is associated with a fast sampling oscilloscope. This probe can be used as a sniffer to identify the ESD current paths on external cables and grounding wires. The point is to get an idea of the way the ESD current is spreading from the discharge point to the different parts of the system. While doing repetitive discharges (like 1 pulse/second), the current probe is successively slipped on the EUT cables, including the ground wires. For each cable, the probe must be placed close to the entry point. The shape and amplitude of these currents, seen on the oscilloscope (set to 50- input), is recorded and listed in order of magnitude. Then a last measurement is made of the total return current on the ground wire of the generator. This current does not necessarily

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amount to the summ I1 + I2 + I3 and so forth for the individual cable currents. The difference corresponds to the capacitive current, which flows directly from the EUT to the ground plane, via stray capacitance. Although this current tracing will not solve the ESD problem, it helps to understand the preferred current routes and what are the circuits or subassemblies in the machine that are crossed by the largest share of the total current (see also Chapter 5). One word of caution: Oscilloscopes are notoriously susceptible to the radiated field of an ESD. To prevent false triggering and misleading results, the oscilloscope should not be placed too close to the EUT; 1.50 m would be a minimum distance, the farther being the better. The mediocre common mode rejection of the oscilloscope input makes it also vulnerable to the outer shield current on the probe coaxial cable. To reduce this parasitic coupling, coil 2 or 3 turns of the probe cable (RG58 or else) in the window of a lossy ferrite: Select a ferrite toroid with at least 12.5 mm (0.5 inch) inner diameter, and a ferrite impedance  150  (for one through pass), from 30 to 300 MHz. A good check for this desensitization of the oscillope is to apply discharges on the EUT, with the current probe close to the EUT, but not clamped on any cable. If a significant signal is still displayed, this means that the oscilloscope is disturbed.

REFERENCES 1. Kocharian, V., and Tolman, D. Express Diagnostic for ESD Simulators. IEEE/EMC Symposium. Boston, 2003, p. 708– 712. 2. IEC 61000– 4-2 ElectroStatic Discharge Immunity Test (2001 + Amendments). 3. Hirata, T., Takahashi, T., and Shibuya, N. Evaluation of Fall Time Restriction of ESD Test Current. IEC Tech. Comm. 77 Report, 2007. 4. Smith, D., Barth, J., and Hyatt, H. Simulators Should Simulate. EOS/ESD Symposium, Orlando, FL, 1996, p. 211 5. Rhoades, W., and Maas, J. New ANSI ESD Standard Overcoming Deficiencies of Worldwide Standards. IEEE/EMC Symposium. Denver, 1998, p. 1078– 1081. 6. Pommerenke, D. Characteristics of Human/Metal ESD Ref. and Generators Parameters. IEEE/EMC Transactions, Nov., 2004, p. 498–511. 7. Caniggia, S. and Maradei, F. Circuit Modelling of ESD Generators. IEE Transactions on Industr. Appl., Nov., 2006. 8. Maas, J. S., and Pratt, D., Study of the Repeatability of ESD Simulators. IEEE/EMC Symposium. Washington, 1990, p. 265– 269. 9. ANSI C63-16 Standard for ESD Test Methodology and Criteria. Draft, 2005. 10. Mohr, D. How to Compare Old and New ESD Test Methods. EMC Expo, Washington, DC, 1989, p. B.3.9– B.3.14. 11. Honda, M. Characteristics of Low Voltage ESD. EOS/ESD Symposium, Las Vegas, 1991, p. 18. 12. Vrachnas, S. Testing Switches for ESD Simulators. Electronic Test, Feb. 1985, p. 44–52. 13. Calcavecchio, R. A Standard Test to Determine ESD Susceptibility. IEEE/EMC Symposium 1986, San Diego, p. 475– 480. 14. Pommerenke, D., and Frei, S. Analysis of Fields on Horizontal Coupling Plane in ESD Test. Journal of ElectroStatics, No. 44, 1998, p. 177– 190.

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15. Richman, P. A Realistic ESD Test Program. EMC Technology Magazine, July 1983, p. 50. 16. Pratt, D., and Davis, J. ESD Failure Rate Prediction. IEEE/EMC Symposium, San Antonio, 1984. 17. Habiger, E. F. ESD Immunity Testing Reproducibility from a Statistic Point of View. Zurich EMC Symposium. 1995, p. 645– 648. 18. Renninger, R. Improved Statistical Method for System Level ESD Test. IEEE/EMC Symposium, Dallas, 1993, p. 20–25. 19. Rittenour, T. J., and Gisin, F. Statistical ESD Test, Using New ANSI Guide. IEEE/EMC Symposium, 1992, Anaheim p. 464– 467. 20. Boxleitner, W. ESD and Electronic Equipment, IEEE Press, 1989. 21. Boxleitner, W. Design and Test for ESD Immunity, Based on Actual Equipment Use. EMC Expo, Washington, DC, 1989, P.B.3.15– 3.22. 22. Nick, H., Osborn, B., and Chang, Y. W. Diagnostic Effectiveness in Computers Using Deterministic ESD. IEEE/EMC Syposium Washington DC. 1990, p. 274– 279. 23. Mardiguian, M. EMI Troubleshooting Techniques. McGraw-Hill, New York, 2000. 24. Smith, D. Investigate System-Level ESD Problems. Test & Measurement World , 1999. 25. Pommerenke, D. Finding the Root Cause of an ESD Upset Event, Design Conference, 2006.

Chapter

5

Design for ESD Immunity E

lectrostatic discharge should not be fought with twelfth-hour fixes and costly retrofits. Rather, it must be treated as any potential environmental condition; that is, it should be dealt with during the equipment design. As for any organized EMI control, ESD protection consists in anticipating, or correcting, the unwanted effects of a hostile electromagnetic ambient. Like any EMI threat, ESD manifests through conducted and radiated phenomena, with the latest being often the predominant mode. But there is some unique aspect to ESD that is not found in ordinary EMI-radiated susceptibility: unlike classical Radio Frequency Interference (RFI) scenario where the victim equipment and its cables are illuminated by a uniform field, ESD generates locally a very strong field pulse, typically >1 kV/m near the discharge point, attenuating rapidly as one moves away toward other parts of the machine. Therefore, although ESD hardening should be part of a general EMI control strategy, and not handled as a separate constraint, some of the classical EMC solutions may not be sufficient and should be complemented by additional protections. Looking at Figure 5.1, we can expect ESD immunity to be considered at the following stages: • • • • • •

At component level At circuit board level By software and noise cancellation features At internal packaging and wiring level At housing/cabinet level At installation and environment level

A full ESD protection could be implemented at one of these levels only. Costwise, however, it is generally more efficient for ESD control to be shared between several levels. Like the skins of an onion, there are several layers, going from the physical envelope (metallic or not) of the machine down to the center core Electrostatic Discharge, Third Edition, by Michel Mardiguian Copyright © 2009 the Institute of Electrical and Electronics Engineers, Inc.

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149

Chip core I/O area: buffers and voltage translators

Software IC Module

External cables Components

Internal wiring

PCBs Discretes, electro-mechnical devices Physical envelope User's interface

Figure 5.1 Several layers to be considered for an ESD protection strategy.

of its electronic activity (the ICs that perform the essential functions). Each layer corresponds to a certain power level and frequency band of the signals being handled. For instance: Going from the external envelope where inputs/outputs can handle tens or, eventually, hundreds of volts if we think of power supply, levels as low as 1 V and few tens of milliamperes are reached after a few layers, when it comes to the chip core. In terms of frequency, the functional bandwidths can range from kilohertz, for low-speed analog, up to hundreds of megahertz, eventually gigahertz with high-speed digital processing. No single device, whatever it is deemed to protect from damage, or to prevent errors or signal alterations, or whether it is based on clamping, filtering, or shielding, can perform alone for all these different amplitudes and frequency domains. Instead, protection components are best installed at the boundary of

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these different layers, with current handling capacity, bandwidth, and physical size that are commensurate to the layer that is to be protected downstream.

5.1. ESD PROTECTION AT COMPONENT LEVEL A first degree of ESD immunity can be achieved by selecting components (logic or analog ICs, operational amplifiers, resistor networks, etc.) that already have built-in ESD protections. Appendix A gives some information on the type of embedded ESD damage protection incorporated by some vendors.

5.1.1. Integrated Circuits with Internal ESD Protection With the gigantic growth of the IC market, and the need for cost and volume reduction, a vast effort has been accomplished by manufacturers to incorporate ESD protection in the chip itself. However, as is often the case for technical progress, another trend is conflicting with the first one: Size reduction, or shrinking, by reducing the IC features size down to the submicron region, is causing such a squeeze in oxide thickness and metal trace width that even the protection devices such as diodes, crowbar transistors, and polysilicon resistors can no longer handle the required pulse energy. Several trade-offs are used to accommodate this conflict (1–4): 1. When scaling down by a k factor, for example, going down √ from 1- to 0.1-μm rule, it is possible to apply a lesser scaling factor, like k for the chip periphery where I/O pads and protection components are located. 2. While keeping the benefits of downscaling for the chip core, the I/O pads and protection components can be arranged in a double ring, with staggered pads such as the occupied real estate is optimized. 3. The effective dissipation area and contact area of the protections can be artificially improved by using slotted traces, multifingered shapes, and multiple contacts for diodes. Although the protection efficiency of these techniques can be tested through the standard HBM, MM, and CDM tests (see Chapter 3), a more recent design tool has been introduced: the TLP (transmission line pulse) where a calibrated square pulse is injected into the device via an RF-type jig, using precision-etched stripline. By varying the pulse amplitude and duration, more insight is obtained for critical failure parameters of each IC pin, including I ,V curves and mismatch. This technique is easily simulated by sofware tools such as SPICE, and results are correlatable to those of a real HBM or CDM pulse with equivalent (current–time) area. Another need that urged IC manufacturers into designing overvoltage suppression is the latch-up phenomenon, characteristic of CMOS, but also found

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151

with bipolar technologies. Caused by a parasitic bipolar (PNPN lateral thyristor), it manifests as a stable, low-resistance path, bridging Vdd with Vss if a transient current exceeding a few 100 mA is applied. It generally ends up in IC damage by overheating. Figure 5.2 shows some of the frequently used passive overvoltage protections that can be embedded in the chip. Their main features are summarized in Table 5.1. This table does not include subminiature protections incorporated by IC manufacturers in the chip core itself. Some other protection techniques have been devised that are not integrated in the chip but implemented in the module package, which does not suffer the same dimensional restrictions. One of them is shown in Figure 5.3. It consists in a ZnO varistor ring laid on the periphery of the chip carrier or substrate, such as all the module leads are 90◦ crossing with this varistor trace. The ZnO material, acting as a voltage-dependent resistor, is applied in the form of sinterable ink, whose width and thickness are adjusted for the desired capacitance and breakdown

INPUT

OUTPUT VCC

Bond pad

VSS DIE EDGE (a) Simple Diodes Protection

(b) CMOS Transistor (Crowbar) Protection Rwell

(c) Resistor and Transistor Protection

Figure 5.2 Few widely used ESD protection schemes, embedded in the IC itself.

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Table 5.1 Summary of Chip-Integrated ESD Protections Type of Embedded Protection

IC Technology CMOS

Unprotected (bare chip) Clamp diode + series resistance Input protected by Schottky diode (Vbr: 30 V) Crowbar transistor Thyristor Output, unprotected Diodes + resistance + low-pass filter

CMOS Bipolar

Low-speed drivers (RS 232)

ESD Withstanding, No-Damage Level (HBM test, 150-ns pulse) 50 V (for 0.50-μm rule) 2–4 kV

700 V 2 kV 5 kV 2 kV Up to 15 kV

8 5 7 6 4 e

5

3 4

Figure 5.3 Varistor “ring” for collective clamping of all the IC pins (6). The printed varistor ink trace (6) is crossing the chip leads (4, 5). On top of it, a grounding ring (7) collects the surge currents.

voltage (5, 6). For instance, with a 20-μm thickness and 0.25-mm2 crossover area, the following charateristics have been obtained: Breakdown voltage (Vbr) Vbr: 10 V Peak current for ESD-type pulse duration (100 ns): 50 A Energy handling: 1 mJ Clamping efficiency, α = 7, which translates into a clamping voltage ≈ 50V for I = 50A Capacitance to ground: 2–4 pF/pad In summary, efficient integrated protections, up to 15 kV, are achievable, but they are expensive and take chip real estate. Fast I/Os can be protected on

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the chip, but with some prejudice to their speed, because of the capacitance of the integrated diodes (typically 10 pF). Thus, if no technology or vendor can be found with built-in ESD protection that matches the objectives and constraints, application-specific protections are necessary. This is especially true for lines that are connected to “user-touchable” items, mostly connectors, as explained next.

5.1.2. Additional ESD Protection: When Is It Needed and How Much? It is, of course, cost-effective to purchase parts that are ESD immune (e.g., with a 2- to 4-kV ESD grade) rather than adding external transient protection devices to each component. Yet, in many cases, an additional protection is necessary, with performances selected to fulfill the expected ESD immunity of the equipment, because: 1. Integrated resistors, zeners, and crowbars are efficient against damage but cannot prevent errors if a few volt transient is induced by ESD. 2. The 2- or 4-kV vendor-specified ESD immunity is only granted against a human body (HBM) type of discharge, with a maximum current of 2.6 A (for a 4-kV grade). This covers the IC during handling, manufacturing, assembly, packing/unpacking, or maintenance. In actual machine life, and during ESD tests per IEC 61000-4-2 or automobile SAE J1113, ESD currents up to 30 A, for a 8-kV direct contact, and 45 A for an air discharge can be applied to the equipment. Although many circuits will never be directly exposed to such currents, but only to their radiated effects (Fig. 5.4), some others will. This is the case for ICs that connect directly to a user-touchable connector pin, a manual switch, or keyboard or that are arc-reachable by an air discharge, whereas the arc jumps from a discontinuity of the machine envelope to an internal component or trace. These added protections can be perform by: Decoupling (clamp diodes, crowbars, and capacitors): the pulse current is bypassed to Gnd or +Vcc Blocking (inductances): A high impedance is opposed to the ESD current. Absorbing (lossy ferrites and resistors): the ESD pulse is dissipated into heat. Depending on the selected components, their action can: Ensure a damage-free, but not an error-free operation. Filter the high-frequency components of ESD spectrum, that is, preventing errors with short pulses (less than 10 ns), but cannot attenuate long ESD pulses, typical of a direct injection. Ensure both survival and error-free protections. Following is the list of the commonly used ESD protection components, mounted close to the IC to be protected.

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ESD Gun

VDD

VSS

Figure 5.4 Voltage at the Vcc pin of a keyboard IC when a 1-kV indirect ESD is applied to the HCP at 10-cm distance. Although not destructive, the 130-V pulse causes a lockup of the keyboard in a frozzen state, requiring a power off/on action (7).

1. Transient protectors (in discrete or integrated packages) such as the ones shown in Figure 5.5. Leadless SMT devices, with 2–8 terminals (SO-8) are available, capable of handling the full current of a 15-kV IEC-type discharge. 2. Series resistances on the sensitive, high-impedance inputs, to limit the current below the damage level. 3. Capacitive decoupling next to critical signal pins. On signal inputs, 30 pF or more can be added, depending on what capacitive loading can be tolerated by this line, without affecting the performance. While transient protectors will not eliminate low-level glitches (those above the detection threshold, but not high enough to cause damage), decoupling capacitors will. 4. Capacitive filtering next to the power input pin. A 100-nF ceramic capacitor can be added, even if not considered necessary, at the initial circuit design (though less sensitive than signal inputs, some Vcc supply pins can cause a logic error if the parasitic pulse has enough amplitude. An interesting alternative, although not particularly developed for ESD, is shown in Figure 5.6), where the power supply buffer capacitor is integrated in the substrate of the IC. There is now a general trend among IC manufacturers

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155

Typical transmission line pulse response graph 360 Trigger voltage

PESD0603-140

320

Voltage response (40V/div)

280 240 200 160 Clamping voltage

120

1,000V TLP pulse 800V TLP pulse

80 40 500V TLP Pulse

0

0

D

20

60 40 Time (10 ns/div)

80

100

Dimensions in millimeters (inches)*

A

B

Length A Part Min. Max. 0402 0.95 (0.037) 1.05 (0.041) 0603 1.40 (0.055) 1.80 (0.071)

Height B Min. Max. 0.33 (0.010) 0.43 (0.017) 0.38 (0.015) 0.58 (0.023)

Figure 5.5 Transient voltage suppressors, with very low parasitic capacitance. (Source Tyco/Raychem.)

to incorporate such capacitors in the chip itself, using diffused junction capacitances. A final precaution must be taken when cascading external clamping devices with chip internal protection diodes. It relates to clamping coordination: If a fast acting diode exists already inside the chip, it parallels the external clamp, and one must make sure that the first one will not react faster. This would cause the full pulse current to cross the IC protection, with the external protection not even triggering. In other words, the faster but fragile device would prevent the triggering of the bigger one, and would be destroyed by an energy that it cannot handle. The solution is to always place some series impedance (a resistance or a small inductance) between the two (Fig. 5.7).

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.160"

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