Advanced CMOS Cell Design

Advanced CMOS Cell Design Authors’ Profiles Etienne Sicard is currently professor at National Institute of Applied Scie...

Author: Etienne Sicard | Sonia Delmas Bendhia

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Advanced CMOS Cell Design

Authors’ Profiles Etienne Sicard is currently professor at National Institute of Applied Sciences (INSA) of Toulouse, Department of Electrical and Computer Engineering. He has been a visiting professor at the Department of Electronics, Carleton University, Ottawa, Canada, since 2004. Prior to this, he was Professor of Electronics at the Department of Physics, University of Balearic Islands, Spain. Etienne received his BS (1984) and PhD (1987) in Electrical Engineering from the University of Toulouse while working in the laboratory LAAS of Toulouse. Upon being awarded the Monbusho scholarship he worked at Osaka University during 1988-89. His research interests include several aspects of CAD tools for the design of integrated circuits, including signal integrity in deep sub-micron CMOS ICs and electromagnetic compatibility. Etienne is the author of several books, and software of micro-electronics (Microwind, Dsch) and speech therapy (Vocalab). He also has to his credit several technical papers on electromagnetic compatibility of CMOS integrated circuits. A member of the French SEE and the IEEE EMC society, Etienne was elected, in 2006, the distinguished IEEE lecturer for EMC of IMCs. He can be reached at: [email protected] Sonia Delmas Bendhia is Assistant Professor at INSA-Toulouse, Department of Electrical and Computer Engineering, where she teaches digital electronics, IC testing and reliability, analog and RF CMOS design. She is on the INSA Studies Directorate Board that organizes transversal educational courses, and is also in charge of promoting IT in teaching. Sonia holds an engineering diploma (1995) and a PhD (1998) in Electronic Design from INSA, Toulouse, France. Her research interests include signal integrity in deep sub-micron CMOS ICs and electromagnetic compatibility of ICs. She has authored several technical papers on signal integrity and EMC, and has also contributed to three books. She can be reached at [email protected]

Copyright © 2007 by The McGraw-Hill Companies, Inc. Click here for terms of use.


Etienne Sicard Professor INSA Electronic Engineering School of Toulouse, France

Sonia Delmas Bendhia Assistant Professor INSA Electronic Engineering School of Toulouse, France

McGraw-Hill New York Chicago San Francisco Lisbon London Madrid Mexico City Milan New Delhi San Juan Seoul Singapore Sydney Toronto

To Vinay, Bhupesh, Brijesh and Tarun

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For more information about this title, click here

Contents Preface Acknowledgments Abbreviations and Symbols 1. Technology Scale-down 1.1 Recent Trends in CMOS Technology 1 1.2 Introducing the 90 nm Technology 5 References 12

xi xiii xv 1

2. Embedded Memories 2.1 The World of Memory 13 2.2 RAM Memory 15 2.3 RAM Array 18 2.4 Dynamic RAM Memory 23 2.5 EEPROM 24 2.6 Flash Memories 29 2.7 Ferroelectric RAM Memories 31 2.8 Memory Interface 34 References 34 Exercises 35

13

3. A Very-Simple-Microprocessor 3.1 Introduction 36 3.2 Instructions 38 3.3 Program Memory 39 3.4 Executing Instructions 40 3.5 Basic Block Design 45 3.6 Conclusion 65 References 66 Exercises 66

36

viii

Contents

4. Field-Programmable Gate Array 4.1 Introduction 67 4.2 Configurable Logic Circuits 69 4.3 Programmable Logic Block 77 4.4 Interconnection Between Blocks 79 4.5 Conclusion 90 References 90 Exercises 90

67

5. Radio-Frequency Circuits 5.1 Target Radio-Frequencies 93 5.2 Inductor 94 5.3 Power Amplifier 102 5.4 Oscillators 114 5.5 Phase-Lock Loop 125 5.6 Frequency Converter 137 5.7 Sub-sampling Frequency Converter 5.8 Conclusion 153 References 155 Exercises 155

93

153

6. Converters and Sensors 6.1 Introduction 157 6.2 Digital-Analog Converter Architectures 158 6.3 Sample and Hold Circuits 170 6.4 Analog-Digital Converter Architectures 176 6.5 Temperature Sensor 184 6.6 Image Sensors 186 6.7 Conclusion 191 References 191 Exercises 191

157

7. Input/Output Interfacing 7.1 Power Supply 192 7.2 The Bonding Pad 193 7.3 The Pad Ring 196 7.4 Input Structures 201

192

Contents

7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13

ix

Digital Output Structures 216 Pull-up, Pull-down 228 Low Voltage Differential Swing 230 Power Clamp 232 Core/Pad Limitation 232 I/O Pad Description Using IBIS 234 Connecting to the Package 236 Signal Propagation Between Integrated Circuits 239 Conclusion 241 References 242 Exercises 243

8. Silicon on Insulator 8.1 Introduction 244 8.2 SOI Technology Issues 251 8.3 SOI Device Model 253 8.4 SOI Design 254 8.5 The Tera-Hertz MOS Device 255 8.6 Conclusion 257 References 257 Exercices 257

244

9. Future and Conclusion 9.1 Predicting the Unpredictable 258 9.2 Conclusion 259 References 260

258

Appendix A: Design Rules Lambda Units 261 Layout Design Rules 262 Pads 266 Electrical Extraction Principles 266 Node Capacitance Extraction 267 Resistance Extraction 270 Simulation Parameters 272 Technology Files for DSCH 275

261

x

Contents

Appendix B: MICROWIND31 Program Operation and Commands Getting Started 277 List of Commands in MICROWIND31 277

277

Appendix C: DSCH31 Logic Editor Operation and Commands Getting Started 318 Commands 318

318

Appendix D: Quick Reference Sheet MICROWIND31 Menus 330 MICROWIND3.1 Simulation Menu 335 DSCH3.1 Menus 335 Silicon Tool 337 List of Files 339 File Organization 339

330

Appendix E: Interface to WinSpice About WinSpice3 340 SPICE Syntax 340 Generate a SPICE File with DSCH3.1 345 Generate a SPICE File with MICROWIND3.1 References 355

340

348

Glossary

356

Index

361

Preface Our first book, Basics of CMOS Cell Design, covered integrated circuit technology scale down, the MOS device model, layout and performance perspectives. It also included an extensive study of basic gates, interconnect and analog cells. We introduced basic cell design and simulation using user-friendly educational tools, Microwind and Dsch, developed by us. Advanced CMOS Cell Design takes the discussion further and illustrates how Microwind and Dsch versions 3.1 can be used to solve design problems. The book begins with an introduction to novel concepts in nano-scale technology, with a focus on 90 nm CMOS generation. In Chapter 2, various kinds of memories are discussed. Chapter 3 uses the medium of a project to explain microprocessor architecture, at the logic level. We would like to reiterate that this chapter would not have been possible without the able assistance and guidance of Dr Mafuz Aziz. The subject of Chapter 4 is field programmable gate arrays, from a switch level. In Chapter 5 RF analog cells are described, including extensive details of mixers, voltage-controlled oscillators, phase-lock-loop and power amplifiers. The focus of Chapter 6 is on principles of analog-to-digital, digital-to-analog converters; the chapter also introduces CMOS sensors. Input-output interfacing principles are detailed in Chapter 7, including an in-depth study of I/O structures and technology refinements. Silicon insulator technology is described in Chapter 8. Appendix A explains design rules, while details of all Microwind and Dsch commands are provided in Appendix B and C respectively. A quick reference sheet of the companion tools is provided in Appendix D. Students and practising electronic engineers will find this a useful reference to learn the practical aspects of CMOS cell design. We welcome feedback, suggestions for improvements, and comments on anything that could have been done better.

About Microwind and Dsch The exercises, samples in this book require extensive use of the software tools Microwind and Dsch versions 3.1. A lite version of these tools, all schematic and layout files of the examples in the book can be downloaded from: http://www.microwind.org The URL to download the latest version of these tools is http://www.microwind.net

ETIENNE SICARD [email protected] SONIA DELMAS BENDHIA [email protected]



Acknowledgments Our special thanks to Bhupesh Purohit, Vinay Sharma and Brijesh Shah—the team from ni2designs—for putting in their best effort to promote the tools, Microwind and Dsch, as well as our two books (Basics of CMOS Cell Design and the current book, Advanced CMOS Cell Design). We thank the many reviewers of the tools, especially Charles Wagner, Joao Paulo Teixeira, Mahfuz Aziz, Saeed Dubas, Fernando Moraes, Gert Voland, Gerald Huguenin, Javier Garcia Zubia, Mario della Ragione, Ndubuisi Ekekwe, and S Natarajan. Also, Marie-Agnes Detourbe for diligently reviewing the manuscript. Thanks are due to Salman Zaffar for introducing a discussion on microprocessors. The chapter Very Simple Microprocessor was significantly improved by Dr Mafuz Aziz, who strongly supported the project and provided valuable comments and suggestions. We would also like to thank R Chandra Sekhar and Vibhor Kataria of Tata McGraw-Hill, India, for publishing this book. Our acknowledgments would not be complete without thanking our parents, colleagues and friends for their constant support. ETIENNE SICARD SONIA DELMAS BENDHIA



Abbreviations and Symbols MULTIPLIERS Value 1018 1015 1012 109 106 103 100 10-3 10-6 10-9 10-12 10-15 10-18 10-21

Name PETA EXA TERA GIGA MEGA KILO – MILLI MICRO NANO PICO FEMTO ATTO ZEPTO

Standard Notation P E T G M (MEG in SPICE) K – m u n p f a z

PHYSICAL CONSTANTS AND PARAMETERS Name ε0 εr SiO2 εr Si εr ceramic k q µn µp γal γsi ni ρ al γ cu ρ cu ρ tungstène (W) ρ or (Ag) µ0 T

Value 8.85 e –12 Farad/m 3.9 – 4.2 11.8 12 1.381e–23 J/°K 1.6e-19 Coulomb 600 V.cm–2 270 V.cm–2 36.5 106 S/m 4 ⫻ 10–4 S/m 1.02 ⫻ 1010cm–3 0.0277 Ω.µm 58 ⫻ 106 S/m 0.0172 Ω.µm 0.0530 Ω.µm 0.0220 Ω.µm 1.257e–6 H/m 300°K (27°C)

Description Vacuum dielectric constant Relative dielectric constant of SiO2 Relative dielectric constant of silicon Relative dielectric constant of ceramic Bolztmann’s constant Electron charge Mobility of electrons in silicon Mobility of holes in silicon Aluminum conductivity Silicon conductivity Intrinsic carrier concentration in silicon at 300°K Aluminum resistivity Copper conductivity Copper resistivity Tungsten resistivity Gold resistivity Vacuum permeability Operating temperature


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1 Technology Scale-down This chapter describes the recent improvements in technology scale-down in terms of density and speed. It introduces the 90 nm technology.

1.1 Recent Trends in CMOS Technology In this chapter, we shall give an updated overview of the evolution of important parameters such as Integrated Circuit (IC) complexity, gate length, switching delay and supply voltage, with a prospective vision down to the 22 nm CMOS technology. The book Basic CMOS Design [1] was focused on 130 nm technology. Recognizing a trend in IC complexity, Intel co-founder Gordon Moore extrapolated it to predict an exponential growth in the available memory and calculation speed of microprocessors. This, he said in 1965, would double every year [2]. With a slight correction (i.e. doubling every 18 months, see Fig. 1.1), Moore’s Law has held up to the Itanium® 2 processor, which has around 400 million transistors. The trend of CMOS technology improvement continues to be driven by the need to integrate more functions into a given area of silicon. Table 1.1 gives an overview of the key parameters for technological nodes from 180 nm, introduced in 1999, down to 22 nm, which is expected to be in production by around 2011. The physical gate length is slightly smaller than the technological node, as illustrated in Fig. 1.2. The gate material has long been polysilicon, with silicon dioxide (SiO2) as the insulator between the gate and the channel. The atom is a convenient measuring stick for the insulating material transistor beneath the gate. In 90 nm technology, the gate oxide consisted of about five atomic layers, which were 1.2 nm in thickness. The thinner the gate oxide, the higher the transistor current and consequently the switching speed. The SiO2 oxide has been regularly scaled down over the last decade, but has reached a physical limit of five atoms with the 90 nm CMOS process. With the 45 nm technology, new materials such as metal gates together with high-permittivity oxide should be introduced. Copyright © 2007 by The McGraw-Hill Companies, Inc. Click here for terms of use.

2


Fig. 1.1 Moore’s law compared to Intel processor complexity from 1970 to 2005

At each lithography scaling, the linear dimensions are reduced by a factor of approximately 0.7 and the areas are reduced by a factor two. Smaller cell sizes lead to a higher integration density. This has thus risen from 100 kilogates per mm2 for the 130-nm technology to almost one million gates per mm2 in 45 nm technology. In parallel, the size of a six-transistor memory point, such as those used in static RAM memories, passed below the 1 µm2 limit after the 65-nm technology. The IC market has been growing steadily for many years, due to an ever-increasing demand for electronic devices. The production of ICs for various technologies over the years is illustrated in Fig. 1.3. Table 1.1 Technological evolution and forecast up to 2011 Technology node

180 nm

130 nm

90 nm

65 nm

45 nm

32 nm

22 nm

First production

1999

2001

2003

2005

2007

2009

2011

Gate length

130 nm

70 nm

50 nm

35 nm

25 nm

17 nm

12 nm

Gate material

Poly

Poly

Poly

Poly

Metal

Metal

Metal

SiO2

SiO2

SiO2

SiON

High K

High K

High K

Atoms stacked on the gate oxide

10

8

5

5

5–10

5–10

5–10

kgates/mm2

100

200

350

500

900

1500

3000

Memory point µ2

4.5

2.4

1.3

0.6

0.3

0.15

0.08

Technology Scale-down

3

Fig. 1.2 The technology scale-down towards nano-scale devices

Fig. 1.3 Technology ramping every two years [3]

It can be seen that a new technology has appeared regularly every two years, with a ramp-up close to three years. The production peak has constantly increased, and similar trends are likely to be observed for novel technologies such as 65 nm (forecast peak in 2009). One very important trend associated with lithography scaling is the decrease in gate switching delay, as illustrated in Fig. 1.4. The IC speed is improved thanks to stronger currents capable of charging and

4


discharging smaller parasitic capacitances. A constant increase in the device current is highly desirable but raises a number of important issues.

Fig. 1.4 The reduction in channel length leads to tremendous benefits in terms of gate switching delay

Let us recall a first-order approximation of the device current, given Eq. 1.1: Ids = k

VDD µ L tOX

Fig. 1.5 The continuous decrease in supply voltages

(1.1)


5

As may be deduced from the expression, there are at least three efficient ways of increasing the transistor current capabilities: • Increasing the supply voltage VDD (Fig. 1.5). Unfortunately, the supply voltage tends to follow the opposite trend, for low power consumption purposes. From 130 nm to 90 nm, the supply has been reduced from 1.5 to 1.2 V. • Reducing the distance L between the drain and the source. Fortunately, the channel length is automatically scaled with the technology. A scaling factor of 0.7 leads to a 33% increase in the absolute current. • Decreasing the oxide thickness tOX. The oxide thickness has been reduced from 1.8 nm (eight atoms) to 1.2 nm (five atoms). Unfortunately, the gate oxide leakage is exponentially increased, which affects the parasitic leakage currents and consequently the standby consumption. • Increasing the carrier mobility m. This parameter was kept unchanged up to the 90 nm generation, which was the first to exploit the concept of strained silicon to enhance the carrier mobility. Finding mobility enhancement techniques is mandatory, to maintain performance gain without deteriorating device leakage.

1.2 Introducing the 90 nm Technology A complete industrial 90 nm process was introduced by Intel in 2003 [3]. With transistor channels around 50 nm in size (50 billionths of a meter), comparable to the smallest micro-organisms, this technology is truly a nanotechnology. The main novelty related to the 90 nm technology is the introduction of strained silicon to speed up the carrier mobility. This boosts both the n-channel and p-channel transistor performances (Fig. 1.6). It has been known for decades that stretching the silicon lattice improves the carrier mobility, and consequently the device current.

Fig. 1.6 Strain generated by a silicon-nitride capping layer which increases the distance between atoms underneath the gate. This speeds up the electron mobility of n-channel MOS devices

6


Let us now focus on the silicon atoms forming a regular lattice structure inside which the electrons participating in the device current have to flow. In the case of electron carriers, stretching the lattice allows the charges to flow faster from the drain to the source, as depicted in Fig. 1.7. The mobility improvement exhibits a linear dependence with the tensile film thickness. An 80 nm film has resulted in a 10% saturation current improvement in Intel’s 90 nm technology [3]. The strain may also be applied from the bottom with a uniform layer of an alloy of silicon and germanium (SiGe).

Fig. 1.7

Compressive strain to reduce the distance between atoms underneath the gate, which speeds up the hole mobility of p-channel MOS devices

In a similar way, compressing the lattice slightly increases the speed of the p-type transistor for which the current carriers consist of holes. The combination of reduced channel length, decreased oxide thickness and strained silicon allows to achieve a substantial gain in drive current for both nMOS and pMOS devices. 1.2.1 N-channel MOS Device Characteristics Version 3.1 of the tool MICROWIND is configured in 90 nm technology by default. A cross-section of the n-channel and p-channel MOS devices is given in Fig. 1.8. The nMOS gate is capped with a specific silicon-nitride layer that induces lateral tensile channel strain for improved electron mobility. The I/V device characteristics of the low-leakage and high-speed MOS devices listed in Table 1.2 are obtained using the MOS model BSIM4 (See [1] for more information about this model). The device performances are close to those presented in [3]. The cross sections of the low-leakage and high-speed MOS devices (Fig. 1.8) do not reveal any major difference. Concerning the low-leakage MOS, the I/V characteristics reported in Fig. 1.9 demonstrate a drive current capability of around 0.6 mA for W = 0.5 µm, that is, 1.2 mA/µm at a voltage supply of 1.2 V. For the high-speed MOS, both the effective channel length and the threshold voltage are slightly reduced, to achieve an impressive drive current of around 1.5 mA/µm. The drawback of this astounding current drive is the leakage current, which rises from 60 nA/µm (low leakage) to 600 nA/µm (high speed), as seen in the Id/Vg curve for Vg = 0 V, Vb = 0 V (Fig. 1.10-b).


Table 1.2 nMOS parameters featured in the 90 nm CMOS technology provided in MICROWIND Parameter

nMOS Low leakage

nMOS High speed

Draw length

0.1 µm

0.1 µm

Effective length

60 nm

50 nm

Width

0.5 µm

0.5 µm

Threshold voltage

0.28 V

0.25 V

Ion (VDD = 1.2 V)

0.63 mA

0.74 mA

Ioff

30 nA

300 nA

Fig. 1.8 Bird’s eye view and cross section of nMOS devices

7

8


Fig. 1.9 Id /Vd characteristics of the low-leakage and high-speed nMOS devices (W = 0.5 µm, L = 0.1 µm)

Fig. 1.10

Id /Vd characteristics (low scale) of the low-leakage and high-speed nMOS devices (W = 0.5 µm, L = 0.1 µm)


9

1.2.2 P-channel MOS Device Characteristics Table 1.3 pMOS parameters featured in the 90 nm CMOS technology provided in MICROWIND Parameter

pMOS Low leakage

pMOS High speed

Drawn length

0.1 µm

0.1 µm

Effective length

60 nm

50 nm

Width

0.5 µm

0.5 µm

Ion (VDD = 1.2 V)

0.35 mA

0.39 mA

Ioff

21 nA

135 nA

Fig. 1.11 Cross section of the pMOS devices

The pMOS drive current in this 90 nm technology is as high as 700 µA/µm for low-leakage MOS and up to 800 µA/µm for high-speed MOS (Fig. 1.11). A novel Silicium-bermanium (Sibe) film induces compressive channel strain which boosts the pMOS hole mobility. These values are particularly high, as the target applications for this technology at Intel are high-speed digital circuits such as microprocessors. The leakage current is around 40 nA/µm for low-leakage MOS and near 300 nA/µm for high-speed devices.

10


1.2.3 High Speed, General Purpose and Low Power Process Variants The 90 nm process technology proposed in MICROWIND corresponds to the highest possible speed, at the cost of very important leakage current. This technology variant is called “high speed” as it is dedicated to applications for which high speed is the primary objective: fast microprocessors, fast DSP, etc. The second technological option is “general purpose” (Fig. 1.12). This targets standard products where the speed factor is not critical. The leakage current is one order of magnitude lower than in the high-speed option, and the gate delay is increased by 50%, as seen in the parameters listed in Table 1.4. The “low power” variant concerns ICs for which the leakage must remain as low as possible, a criterion that ranks first in applications such as embedded devices, mobile phones and personal organizers. The gate delay is multiplied by three as compared to the high-speed variant, mainly due to thicker oxides and a larger gate length.

Fig. 1.12 Introducing three variants of the 90 nm technology

1.2.4 High-permittivity Dielectrics The steady reduction in thickness of conventional oxides such as silicon dioxide (SiO2) results in reliability degradation and unacceptable current leakage. New dielectric materials (Table 1.5) with high permittivity (high-K) are needed to replace SiO2, both for the MOS device and the embedded capacitors. High-capacitance passive devices (known as Metal-Insulator-Metal, or MIM) are needed for various purposes including on-chip power supply decoupling, analog filtering for wireless applications and high-quality resonators for radio-frequency circuits. These capacitors should feature high reliability, low current leakage, low series resistance and low dielectric loss. They should also be fully compatible with the standard CMOS processes.


11

Table 1.4 The three classes of 90 nm CMOS technologies and comparative performances Technology

High Speed

General Purpose

Lower Power

Typical applications

Fast µP, fast DSP

ASIC, microcontrollers, FPGA

Mobiles, embedded devices

VCC

1.2

1.0

1.2

tox (nm)

1.2

1.6

2.2

Leff (nm)

50

65

80

VT (V)

0.28

0.35

0.50

Idsat_n (µA/µm)

1200

700

500

Idsat_p (µA/µm)

700

300

200

Ioff (A/µm)

50n

5n

50p

Delay (ps/stage)

7

12

25

Table 1.5 New dielectric materials that may replace SiO2 in future technologies Relative Permittivity (εεr )

Comments

Material

Description

HfO2

Fluor-oxide

20

Proposed for 45 nm gate oxide

Ta2O5

Tantalum pentoxide

25

High crystallization temperature. Reliability issues

NixTa2O5

Niobium tantalum pentoxide

28

Good candidate for MIM capacitor

SiOxNy

Silicon oxide nitride

5–7

Used for 65 nm gate oxide

SiO2

Silicon dioxide

4

Important ultra-thin film leakage

Both MOS devices and passives may benefit from high-K insulators. Concerning MOS devices, high-K dielectrics can be made thicker than SiO2 films to obtain the same equivalent channel effect, thereby reducing leakage. Concerning passives, the larger the permittivity, the larger the charge that can be stored in the memory capacitor, thus resulting in higher capacitance values. Alternatively, the same capacitance may require less silicon area with high-K insulators than with conventional SiO2. Typical values for the capacitance range from 2 to 20 fF/µm2.

12


References [1] E. Sicard and S. Bendhia, Basic CMOS Cell Design, Tata McGraw-Hill, 2005, ISBN 0-07-059933-5. [2] G.E. Moore, “Cramming more components onto integrated circuits”, Electronics, Volume 38, No. 8, 1965. [3] T. Ghani and Col, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors”, Proceedings of IEDM 2003.

2 Embedded Memories

2.1 The World of Memory Semiconductor memories are vital components in modern ICs. Stand-alone memories represent roughly 30% of the global IC market. In a system-on-chip, memory circuits usually represent more than 75% of the total number of transistors.

Fig. 2.1 Major classes of CMOS compatible memories


14


There are two main classes of memories: volatile and non-volatile memories. • In volatile circuits (Fig. 2.1 left), the data is stored as long as the power is applied. The Dynamic Random Access Memory (DRAM) is the most common volatile memory. • Non-volatile memories are capable of storing the information even if the power is turned off (Fig. 2.1 right). Read-only Memory (ROM) is the simplest type of non-volatile memory. One-time Programmable Memories (PROM) are an important family, but the most popular among non-volatile memories are erasable and programmable devices. These include the old Electrically Programmable ROM (EPROM), the more recent Electrically Erasable PROM (EEPROM, FLASH), and the new Magneto-resistive RAM (MRAM) and Ferroelectric RAM (FRAM) memories.

Fig. 2.2 Typical memory organization

Figure 2.2 shows a typical memory organization layout. It consists of a memory array, a row decoder, a column decoder and a read/write circuit. The row decoder selects one row from 2N, thanks to an N-bit row selection address. The column decoder selects one row from 2M, thanks to an M-bit column selection address. The memory array is based on 2N rows and 2M columns of a repeated pattern, the basic memory cell. A typical value for N and M is 10, resulting in 1024 rows and 1024 columns, which corresponds to 1048576 elementary memory cells (one Mega bit).

Embedded Memories

15

2.2 RAM Memory The basic cell for static memory design is based on six transistors, which two pass gates instead of one. The corresponding schematic diagram is given in Fig. 2.3. The circuit consists of the two cross-coupled inverters (see [1], Chapter 6), but uses two additional pass transistors. The cell has been designed to be duplicated in X and Y in order to create a large array of cells. Usual sizes for Megabit SRAM memories are 1024 column × 1024 rows, or higher. A modest arrangement of 4 × 4 RAM cells is proposed in Fig. 2.4. The selection line WL concerns all the cells of one row. The bit lines BL and ~BL concern all the cells of one column.

Fig. 2.3 The layout of the six-transistor static memory cell (RAM6T.SCH)

Fig. 2.4 An array of 6T memory cells, with four rows and four columns (RAM6T.SCH)

16


The RAM layout is given in Fig. 2.5. The BL and ~BL signals are made with metal2 and cross the cell from top to bottom. The supply lines are horizontal, made with metal3. This allows easy matrix-style duplication of the RAM cell.

Fig. 2.5 Layout of the SRAM cell (RAM6T.MSK)

WRITE CYCLE. Values one or zero must be placed on Bit Line, and the data’s inverted value on ~Bit Line. Then the selection Word Line goes to one. The two-inverter latch takes the Bit Line value. When the selection Word Line returns to zero, the RAM is in a memory state. READ CYCLE. The selection signal Word Line must be asserted, but no information should be imposed on the bit lines. In that case, the stored data value propagates to Bit Line, and its inverted value ~Data propagates to ~Bit Line. SIMULATION. The simulation parameters correspond to the read and write cycles in the RAM. The proposed simulation steps consist of writing a zero, writing a one, and then reading the one. In a second phase, we write a one, write a zero, and then read the zero. The Bit Line and ~Bit Line signals are controlled by pulses (Fig. 2.6). The floating state is obtained by inserting the letter “x” instead of one or zero in the description of the signal. The simulation of the RAM cell is proposed in Fig. 2.7. At time 0.0, Data reaches an unpredictable value of one, after an unstable period. Meanwhile, ~Data reaches zero. At time 0.5 ns, the memory cell is selected by a one on World Line. As the Bit Line information is zero, the memory cell information Data goes down to zero. At time 1.5 ns, the memory cell is selected again. As the Bit Line information is now one, the memory cell information Data goes to one. During the read cycle, in which Bit Line and ~Bit Line signals are floating, the memory sets these wires to one and zero respectively, corresponding to the stored values.

Embedded Memories

17

Fig. 2.6 Bit Line pulse uses the “x” floating state to enable reading of the memory cell (RamStatic6T.MSK)

Fig. 2.7 Write cycle for SRAM cell (RamStatic6T.MSK)

18


2.3 RAM Array You can duplicate the RAM cell into a 4 × 4 bit array using the command Edit→Duplicate XY. Select the whole RAM cell and a new window appears. Enter the value « 4 » for X and « 4 » for Y into the menu. Click on « Generate ». A very interesting approach to obtain a more compact memory cell consists of sharing all possible contacts: the supply contact, the ground contact and the bit line contacts. The consequence is that the effective cell size can be significantly reduced (Fig. 2.8).

Fig. 2.8 Sharing all possible contacts leads to a very compact cell design (Ram6Tcompact.MSK)

The layout is functionally identical to the previous layout. The only difference is in the placement of MOS devices and contacts. We duplicate the RAM cell into a 64-bit array. The multiplication cannot be done directly by the command Duplicate XY, as we need to flip one cell horizontally to share lateral contacts, and flip the resulting block vertically to share vertical contacts (Fig. 2.9). 2.3.1

Row Selection Circuit

The row selection circuit decodes the row address and activates one single row (Fig. 2.10). This row is shared by all word line signals of the row. The row selection circuit is based on a multiplexor circuit. One line is asserted while all the other lines are at zero.

Embedded Memories

Fig. 2.9 Compact 16 × 4 array of memory cells with shared contacts (Ram16 × 4Compact.MSK)

Fig. 2.10 Row selection circuit

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In the row selection circuit for the 16 × 4 array, we simply need to decode a two-bit address. Using AND gates is one simple solution. In Fig. 2.11, we present the schematic diagram of two-to-four and three-toeight decoders. In the case of a very large number of address lines, the decoder is split into sub-decoders, which handle a reduced number of address lines.

Fig. 2.11 Row selection circuit in two-bit and three-bit configuration (RamWordline.SCH)

2.3.2 Column Selection Circuit

Fig. 2.12 Column selection circuit principles

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The column decoder selects a particular column in the memory array to read the contents of the selected memory cell (Fig. 2.12) or to modify its contents. The column selector is based on the same principles as those of the row decoder. The major modification is that the data flows both ways, that is either from the memory cell to the DataOut signal (read cycle), or from the DataIn signal to the cell (write cycle). Figure 2.13 proposes an architecture based on n-channel MOS pass transistors. We consider here four columns of memory cells, which require two address signals Address_Col[0] and Address_Col[1]. The n-channel MOS device is used as a switch controlled by the column selection. When the nMOS is on and Write is asserted, (Fig. 2.13) the DataIn is amplified by the buffer, flows from the bottom to the top and reaches the memory through BL and ~BL. If Write is off, the three-state inverter is in high impedance, which allows the information to be read on DataOut.

Fig. 2.13 Row selection and read/write circuit (RamColumn.SCH)

2.3.3 A Complete 64-bit SRAM The 64-bit Static RAM (SRAM) memory interface is shown in Fig. 2.14. The 64 bits of memory are organized in words of four-bits, meaning that DataIn and DataOut have a four-bit width. Each data D0..D15 occupies four contiguous memory cells in the array. Four address lines are necessary to decode one address among 16. The memory structure shown in Fig. 2.14 requires two address lines A0 and A1 for the word lines WL[0]..WL[3] and two address lines A2 and A3 for the bit line selection. The final layout of the 64-bit SRAM is proposed in Fig. 2.15.

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Fig. 2.14 Architecture of the 64-bit RAM (RAM64.MSK)

Fig. 2.15 The complete RAM layout (RAM64.MSK)

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2.4 Dynamic RAM Memory The Dynamic RAM (DRAM) memory has only one transistor, in order to improve the memory matrix density by almost one order of magnitude. The storage element is no longer the stable inverter loop, as for the SRAM, but only a capacitor Cs, also called the storage capacitor. The DRAM cell architecture is shown in Fig. 2.16.

Fig. 2.16 Simulation of the write cycle for one-transistor DRAM cell (RAM1T.SCH)

The write and hold operation for ‘1’ is shown in Fig. 2.16. The data is set on the bit line, the word line is then activated, and Cs is charged. As the pass transistor is n-type, the analog value reaches VDD-Vt. When WL is inactive, the storage capacitor Cs holds one.

Fig. 2.17 Simulation of the read cycle for one-transistor DRAM cell (RAM1T.SCH)

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The read cycle is destructive for the stored information. Suppose that Cs holds a one (Fig. 2.17). The bit line is precharged to a voltage Vp (usually around VDD/2). When the word line is active, a communication is established between the bit line, loaded by capacitor CBL, and the memory, loaded by capacitor Cs. The charges are shared between these nodes, and the result is a small increase of the voltage Vp by ∆V, thanks to the injection of some charges from the memory. Commercial DRAM memories use storage capacitors with a value between 10 fF and 50 fF. This is done by creating a specific capacitor for the storage node appearing in Fig. 2.18 left, thanks to the following technological advances: the use of specific metal layers to create the lower plate and external walls of the RAM capacitor, an enlarged height between the substrate surface and metal1, and the use of highpermittivity dielectric oxide. SiO2 has a relative permittivity εr of 3.9. Other oxides compatible with the CMOS process have a higher permittivity (higher ‘K’); Si3N4 with εr close to 7.0, and Ta2O5 with εr equal to 23.

Fig. 2.18 Increasing the storage capacitance (left: junction capacitor, right: embedded capacitor)

A cross section of the DRAM layout is given in Fig. 2.19. The bit line is routed in metal2, and is connected to the cell through a metal1 and diffusion contact. The word line is the polysilicon gate. On the right side, the storage capacitor is a sandwich of conductor material connected to the diffusion contact, a thin oxide (SiO2 in this case) and a second conductor that fills the capacitor and is connected to the ground by a contact to the first level of metal. The capacitance is around 20 fF in this design. Higher capacitance values may be obtained using larger capacitor areas, at the price of a lower cell density.

2.5 EEPROM The basic element of an Electrically Erasable PROM (EEPROM) memory is the floating-gate transistor. The concept was introduced several years ago for the Erasable PROM (EPROM). It is based on the possibility of trapping electrons in an isolated polysilicon layer placed between the channel and the

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Fig. 2.19 The stacked capacitor cell and the diffusion capacitor cell (DramEdram.MSK)

controlled gate. The charges have a direct impact on the threshold voltage of a double-gate device. When there is no charge in the floating gate (Fig. 2.20, upper part), the threshold voltage is low. This means that a significant current may flow between the source and the drain if a high voltage is applied on the gate. However, the channel is small as compared to a regular MOS, and the ION current is three to five times lower, for the same channel size.

Fig. 2.20 The two states of double-gate MOS (EepromExplain.SCH)

When charges are trapped in the floating polysilicon layer (Fig. 2.20, lower part), the threshold voltage is high, and almost no current flows through the device, independent of the gate value. As a matter of

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fact, the electrons trapped in the floating gate prevent the creation of the channel by repelling channel electrons. Data retention is a key feature of EEPROM, as it must be guaranteed for a wide range of temperatures and operating conditions. Optimum electrical properties of the ultra-thin gate oxide and inter-gate oxide are critical for data retention. The typical data retention of an EEPROM is 10 years.

Fig. 2.21 The double-gate MOS generated by Microwind3 (Eeprom.MSK)

The double-gate MOS layout is shown in Fig. 2.21. The structure is very similar to the n-channel MOS device, except for the supplementary poly2 layer on top of the polysilicon. The lower polysilicon is unconnected, resulting in a floating node. Only the poly2 upper gate is connected to a metal layer through a poly2/metal contact situated at the top. The cross section of Fig. 2.21 reveals the stacked poly/ poly2 structure, with a thin oxide in between. 2.5.1 Double-gate MOS Charge The programming of a double-poly transistor involves the transfer of electrons from the source to the floating gate through the thin oxide (Fig. 2.22). Notice the high drain voltage (3 V) which is necessary to

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transfer enough temperature to some electrons to make them “hot”, and the very high gate control needed to attract some of these hot electrons to the floating poly through the ultra-thin gate oxide. The very high voltage varies from 7 V to 12 V, depending on the technology. In MICROWIND the “++” symbols attached to the signal properties indicates that a voltage higher than the nominal supply is used.

Fig. 2.22 Double-gate MOS characteristics (a) without and (b) with charges (EepromCharge.MSK)

At initialization (Fig. 2.22a) no charge exists in the floating gate, resulting in the possibility of current when the poly2 gate voltage is high. However, the device is much less efficient than the standard n-channel MOS, due to an indirect control of the channel. The maximum current is small but significant. The programming operation is performed using a very high gate voltage on poly2, here 8 V. The mechanism for electron transfer from the grounded source to the floating polysilicon gate, called tunneling, is a slow process. In MICROWIND3, around 1000 ns are required. With a sufficiently positive voltage on the poly2 gate, the voltage difference between poly and source is high enough to enable electrons to pass

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through the thin oxide. The electrons trapped on the floating gate increase the threshold voltage of the device, thus rapidly decreasing the channel current. When the gate is completely charged, no more current appears in the Id /Vd characteristics (Fig. 2.22b). 2.5.2 Double-gate MOS Discharge The floating gate may be discharged by ultra-violet light exposure or by electrical erasure. The UV technique is a heritage of the EPROM, which requires a specific package with a window to expose the memory bank to the specific light. The process is very slow (around 20 nm). After the UV exposure, the threshold voltage of the double-gate MOS returns to its low value, which enables the current to flow again. In MICROWIND3, the command Simulate → UV exposure to discharge floating gates simulates the exposure of all double-gate MOS to an ultra-violet light source. Alternatively, the charge can be accessed individually using the command Simulate → MOS characteristics. Changing the Charge cursor position dynamically modifies the MOS characteristics. For the electrical erase operation, the poly2 gate is grounded and high voltage (around 8 V) is applied to the source. Electrons are pulled off the floating gate, thanks to the high electrical field between the source and the floating gate. This charge transfer is called Fowler-Nordheim electron tunnelling (Fig. 2.23).

Fig. 2.23 Discharging the double-gate MOS device (EepromDischarge.MSK)

The basic structure for reading the EEPROM information is shown schematically in Fig. 2.24. After a precharge to VDD, and once WL is asserted, the bit line may either drop to VSS if the floating gate is empty of charges, or remain in a high voltage if the gate is charged. This disables the path between BL and the ground through the EEPROM device. In the case of Fig. 2.24 left, the floating gate has no charge, so BL is tied to ground after the precharge, meaning that DataOut is one. The write operation involves applying a very high voltage on the gate (8 V), and injecting a high or low state on BL. A zero on DataIn is equivalent to a high voltage on BL, which provokes the hot electron effect and charges the floating gate. In contrast, a one on DataIn keeps BL low, and no current flows on the EEPROM channel. In that case, the floating gate remains discharged.

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Fig. 2.24 Reading and writing in EEPROM (Eeprom.MSK)

2.6 Flash Memories Flash memories are a variation of EEPROM memories. Flash arrays can be programmed electrically bitby-bit but can only be erased by blocks. Flash memories are based on a single double-poly MOS device, without any selection transistor (Fig. 2.25).

Fig. 2.25 Flash memory point and principles for charge/discharge (FlashMemory.SCH)

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The immediate consequence of such a simple design is a more compact memory array and denser structures. Flash memories are commonly used in micro-controllers for the storage of application code, which gives the advantage of non-volatile memories and the possibility of reconfiguring and updating the code many times. The flash memory point usually has a ‘T-shape’, due to increased size of the source for optimum tunneling effect [1]. The horizontal polysilicon2 is the bit line, and the vertical metal2 is the word line, which links all drain regions together. The horizontal metal line links all sources together. It is common practice to violate usual design rules in order to achieve a more compact layout. In the case of Fig. 2.26, the poly extension is reduced from three lambda to two lambda.

Fig. 2.26 Flash memory point and associated cross section (Flash8x8.MSK)

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2.7 Ferroelectric RAM Memories Ferroelectric RAM (FRAM) memories are the most advanced of the flash memory challengers [2]. The FRAM is similar to the DRAM except that the FRAM memory point is based on a two-state ferroelectric insulator, while the DRAM relies on a silicon dioxide capacitor. Mega bit FRAM are already available as stand-alone products. However, FRAM embedded memories have been made compatible since the 90 nm CMOS technology. The MICROWIND3 software should first be configured in 90 nm to access the FRAM properties using the command File → Select Foundry. One FRAM cell layout example is shown in Fig. 2.27.

Fig. 2.27 Bird’s view of FRAM cells showing the distinction between two domains

The 2D cross section (Fig. 2.27) shows the ferroelectric crystalline material made from a compound of lead, zirconium and titanium (PZT). The chemical formulation of PZT is an exotic PbZr1-xTixO3. Adjusting the proportion of zirconium and titanium changes the electrical properties of the material. The PbZrTiO3 molecular structure is given in Fig. 2.29. It is equivalent to a cube, where each of the eight corners is an atom of lead (Pb). In the center of the cube is a titanium atom, which is a class IVb element, with oxygen atoms at its ends, shared with neighbors. The two stable states of the molecule are shown in Fig. 2.29. The titanium atom may be moved inside the cell applying an electrical field. The remarkable properties of this insulator material are: the stable state of the titanium atom even without any electrical field, the low electrical field required to move the atom, and its very high dielectric constant (around 100). The PZT capacitor behavior is usually represented by an hysteresis curve as shown in Fig. 2.30. In the X-axis, the electrical field applied to the electrodes is displayed. The Y-axis represents the dipole orientation for each molecule. It can be seen that if a minimum field is applied on the capacitor, the polarization changes. An inverted electrical field is required to change the state of the material.

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Fig. 2.28 Two domains of FRAM memory (FramCell.MSK)

Fig. 2.29 Two domains of the structure which change the orientation of the equivalent dipole

Consequently, the write cycle for a one simply consists of applying a large positive step which orients the dipoles north, and for a zero in applying a negative voltage step, which orients the dipoles south (Fig. 2.31).

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Fig. 2.30 Hysteresis curve of the PZT insulator

Fig. 2.31 FRAM circuit principles and architecture (Fram4 × 4.SCH)

To read the domain information, an electrical field is applied to the PZT capacitor, through a voltage pulse. If the electric field is oriented in the opposite direction of the elementary dipole and is strong enough, the inner atom orientation is changed. This creates a significant current, which is amplified and considered as a one. If the electric field is oriented in the same direction as the elementary dipole, only a small current pulse is observed. This is considered as a zero. Reading the logical information is equivalent to observing the current peak and deciding whether the current peak is small (zero) or large (one). Notice that the read operation destroys the data stored in the PZT material, as for the DRAM cell. Just after the memory information is read, the logical information must be written back to the memory cell.

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2.8 Memory Interface All inputs and outputs of the RAM are synchronized with the rise edge of the clock, and more than one word can be read or written in sequence. The typical chronograms of a synchronous RAM are shown in Fig. 2.32. The active edge of the clock is usually the rise edge. One read cycle includes three active clock edges in the example shown in Fig. 2.32. The row address selection is active at the first rise edge, followed by the column address selection. The data is valid at the third fall edge of the system clock.

Fig. 2.32 Synchronous RAM timing diagram

Double-data-rate memories involve both the rise and fall edge of the clock [1]. Furthermore, a series of data from adjacent memories may be sent on the data bus. Two contiguous data are sent, one on the rise edge of the clock, and the other on the fall edge of the clock. This technique is called “burst-of-two”. An example of double-data-rate and burst-of-two data in/out is proposed in Fig. 2.33. Notice that DataIn and DataOut work almost independently.

References [1] A. K. Sharma, Semiconductor Memories, Technology, Testing and Reliability, IEEE Press, 1997, ISBN 0-7803-1000-4. [2] L. Geppert, “The New Indelible Memories,” IEEE Spectrum, Mar. 2003, Vol. 40, No. 3, pp. 49–54.

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Fig. 2.33 Double-data-rate diagram

EXERCISES 1. Compare the leakage current on a DRAM cell for the following technologies: 0.35 µm, 0.12 µm and 90 nm. 2. Given a 4 × 4 EEPROM memory array, create the chronograms to write the words 0001, 0010, 0100 and 1000, and then to read these values. 3. Modify the ROM array proposed in file ROM8×8.SCH to write the word “Welcome”.

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3 A Very-Simple-Microprocessor (This chapter has been written in cooperation with Dr. Mahfuz Aziz, Senior Lecturer at the School of Electrical and Information Engineering, University of South Australia) This chapter gives an introduction to microprocessor architecture. The goal here is to build a four-bit processor at logic level and then simulate its internal structure step-by-step.

3.1 Introduction The Very-Simple-Microprocessor (VSM) is an updated version of the very popular Simple-As-Possible (SAP) computer architecture proposed by Albert P. Malvino [1] in 1993 in his famous book “Digital Computer Electronics”. The VSM computer introduces the basic concepts of microprocessor architecture in the simplest possible way. The VSM is very primitive, yet quite complex, as shown in Fig. 3.1.

Fig. 3.1 VSM basic architecture Copyright © 2007 by The McGraw-Hill Companies, Inc. Click here for terms of use.

A Very-Simple-Microprocessor

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The function of each block is described in Table 3.1. Table 3.1 Main blocks of VSM architecture Block

Block Description

Size

Program Counter

The program counter counts from 0000 to 1111. It monitors the address of the active instruction. Initially, the program counter is set to 0000, so the microprocessor starts with the instruction at the first memory location.

Program Memory

The program memory stores the program. Each program line has an 8 × 8 bits eight-bit format: the four most significant bits represent the instruction itself, and the four least significant bits represent the data attached to the instruction, if necessary.

Accumulator A

The accumulator is a four-bit register. It is used to store one of the operands for an arithmetic operation. It also stores the intermediate results computed by the microprocessor. Upon request (EnableA), the accumulator result is placed on the internal bus.

four bits

Accumulator B

The accumulator B is also a four-bit register. It is used to store the second operand for an arithmetic operation. For addition, this operand is added to accumulator A and for substraction accumulator A is subtracted from this operand.

four bits

Arithmetic Unit

The Arithmetic Unit performs the operation

four bits

four bits

S = A + B (Addition) Or S = B + ~A + 1 (Subtraction) Input Register

The Input Register gives the opportunity to transfer data from the outside world to the microprocessor.

four bits

Output Register

The Output Register transfers the contents of the internal bus to the outside world. Usually, this instruction is executed at the end of a program to display the final result. The output register stores the output data on the falling edge of the clock. The output register is usually connected to a circuit, which transfers or displays the result to the user.

four bits

The operation of the VSM is based on a bus called “Internal Bus” (IB). Each block shown in Fig. 3.2 may take control of the bus using a specific enable signal. For example, accumulator A uses an enable signal called EnableA. When EnableA is high, the content of accumulator A is placed on the internal bus.

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All the enable signals used in the VSM are shown in Fig. 3.2. Table 3.2 summarizes their functions. The control of these enable signals is provided by the MicroInstruction block, which plays a fundamental role in the operation of the microprocessor.

Fig. 3.2 Controller generates ‘Enable’ signals that allow one block to take control of the bus

Table 3.2 Four blocks may take control of the internal bus, thanks to Enable signals Enable Signal

Description

EnableA

Authorizes A to take control of the bus.

EnableAlu

Places the result of the arithmetic operation (ADD or SUB) on the bus.

EnableInstr

Places the data part of the instruction (four least significant bits) on the bus.

EnableIn

Transfers the contents of the external input to the internal bus.

3.2 Instructions Each instruction of the VSM is eight-bits long. However, only the four most significant bits represent the instruction itself. The remaining four bits contain the data. Therefore, only 16 different instructions are possible.


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3.2.1 No Operation (NOP = 0000) The No Operation instruction has no effect. It does not modify the content of any register. However, this instruction is very important to understand how the basic clock controls work. 3.2.2 Addition (ADD = 0001) The content of accumulator A is added to the data given as a parameter with the instruction. The result updates the accumulator A. The addition is performed on four bits. The carry is ignored. For example, considering that A = 2, the instruction “ADD 3” corresponds to A = A + 3, that is A = 2 + 3. The final value of A is 5. 3.2.3 Subtraction (SUB = 0010) The content of accumulator A is subtracted from the data given as a parameter, and the result updates the accumulator A. The subtraction is performed on four bits. The carry is ignored. 3.2.4 Get Input (In = 0100) The content of the input port is transferred to accumulator A. 3.2.5 Give Output (OUT = 0011) The content of accumulator A is stored on the output port. The output port is a four-bit register that memorizes the output value and makes it available to external devices until its content is refreshed by a new “Give Output” instruction. 3.2.6 Load Accumulator A (LDA = 0101) This instruction loads the accumulator A with the value given as a parameter. For example, the instruction LDA 9 transfers the value 9 (1001 in binary format) to accumulator A.

3.3 Program Memory The program memory contains up to eight bytes, where we store the instructions to be executed. Each instruction is eight-bits long. As shown in Fig. 3.3 each instruction is split into two parts: the four most significant bits represent the instruction code, while the four least significant bits represent the data. The program given in Table 3.3 loads accumulator A with the value ‘2’, then adds ‘1’, and places the result in the output register.

Fig. 3.3 Each instruction is split into four-bit microinstruction code and four-bit data fields

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Table 3.3 A simple program for adding two four-bit numbers Mnemonic

OpCode (binary)

OpCode (hexa)

LDA 2 ADD 1 OUT NOP

0101 | 0010 0001 | 0001 0011 | 0000 0000 | 0000

0 × 52 0 × 11 0 × 30 0 × 00

Figure 3.4 shows the memory symbol along with the corresponding schematic diagram depicting the contents of all the eight memory locations. The memory has eight registers, each register having eight elementary memory cells. You can change the contents of the memory by clicking on the desired memory cells. When you save the schematic diagram, you also save the memory contents. The memory symbol may be found in the basic symbol palette in DSCH.

Fig. 3.4 Storing program in memory (VSM-mem8×8macro.SCH)

3.4 Executing Instructions 3.4.1 Introducing Microinstructions Each VSM instruction is executed as a sequence of four internal micro-operations, also called microinstructions. Therefore the period of execution of each instruction can be divided into four time phases (T1–T4), each for one microinstruction, as shown in Fig. 3.5. The reader should note the distinction


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between the microprocessor instruction itself, such as “LDA 2” and the four internal microinstructions needed to complete the “LDA 2” instruction, called phase one, two, three and four. The first two phases are called the fetch sequence. The corresponding microinstructions are independent of the user’s instruction. The last two phases are called the execute sequence. Table 3.4 summarizes the microinstructions.

Fig. 3.5 Execution of one VSM instruction involves execution of four microinstructions in four separate time phases

Table 3.4 Execution of one instruction is based on four time phases Phase

Name

Description

Phase one

Address state

The content of the desired memory location is loaded into the instruction register.

Phase two

Increment state

The program counter address is incremented. The instruction register provides the microinstruction decoder with the instruction.

Phase three

Execute step one

Depending on the instruction, the microprocessor performs the first step of the execution phase.

Phase four

Execute step two

The microprocessor performs the second step of the execution phase.

3.4.2 No Operation (NOP = 0000) The control flow for the “No Operation” instruction is shown in Fig. 3.6. The Fetch sequence corresponds to access to the memory (ReadMem = 1), and the loading of the corresponding instruction (LoadInstr = 1) during phase one. During phase two, the stored instruction is sent to the microinstruction

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controller (EnableInstr = 1), while the counter is incremented (ProgCount = 1). As the ‘No Operation’ instruction does not affect any internal register, the execution phases (Phase three and phase four) do not correspond to any specific activity.

Fig. 3.6 Execution of microinstructions corresponding to NOP instruction

3.4.3 Addition (ADD = 0001) Addition is performed between the content of accumulator A and the four-bit data given as a parameter of the ADD instruction. Consequently, the addition is executed by storing the data in accumulator B


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(Phase three), then asking the arithmetic unit to produce the addition between accumulator A and accumulator B (Phase four), and finally by transferring the result back to accumulator A on the rising edge of the clock during phase four, as illustrated in Fig. 3.7.

Fig. 3.7 Execution of microinstructions corresponding to the ADD instruction

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3.4.4 Subtraction (SUB = 0010) The execution phase of the subtraction instruction is identical to that of the addition instruction. The only difference is that the AddSub signal is set to zero, which means “Subtract”. 3.4.5 Get Input (In = 0100) The content of the input port is transferred to accumulator A during phase three (Fig. 3.8). There is nothing to do in phase four, when all registers remain inactive.

Fig. 3.8 Execution of microinstructions corresponding to the IN instruction


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3.4.6 Give Output (OUT = 0011) The content of accumulator A is transferred to the output port via the internal bus during phase three. The output port memorizes the accumulator value and makes it available to external devices, thanks to its four registers. The processor is inactive during phase four.

Fig. 3.9 Execution of microinstructions corresponding to the OUT instruction

3.4.7 Load Instruction (LDA = 0101) The load instruction transfers the four-bit data given as a parameter of the LDA instruction to accumulator A. For example, the instruction “LDA 9” transfers the value 9 (1001 in binary format) to accumulator A. In Fig. 3.10, the four least significant bits of the instruction register are placed on the internal bus and then transferred to accumulator A. As a result, the updated value of A is 1001. There is no activity during phase four.

3.5 Basic Block Design The structure of each sub-block of the microprocessor is presented in detail here. 3.5.1 Accumulator A The accumulator is composed of four edge-sensitive D flip-flops as shown in Fig. 3.11. The register output is available through AluA0..AluA3 for the ADD and SUB operations. The content of A is transferred to the internal bus when EnableA is asserted. We use tri-state inverters to facilitate access to the internal bus. The latchA signal authorizes the transfer of input data (here, through a keyboard) to accumulator A at the falling edge of the main clock.

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Fig. 3.10 Microinstruction during phase three executes the load operation. During phase four, the processor is inactive


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Fig. 3.11 Structure of accumulator A showing its connections to the internal bus and arithmetic unit (VsmAccumulatorA.SCH)

3.5.2 Accumulator B Like accumulator A, the accumulator B is composed of four edge-sensitive D flip-flops as shown in Fig. 3.12. The register output is available through AluB0..AluB3 for the ADD and SUB operations. The

Fig. 3.12 Structure of accumulator B showing its connections to the arithmetic unit (Vsm-AccumulatorB.SCH)

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“latchB” signal authorizes the transfer of input data (here, through a keyboard) to accumulator B at the falling edge of the main clock. 3.5.3 Add/Subtract Block The addition is based on the full-adder sub-circuit that has been described in Chapter seven of the book “Basic CMOS cell design” by Sicard and Bendhia [2]. The full-adder consists of a set of XOR gates for generating the Sum output and a complex gate for generating the Carry output, as shown in Fig. 3.13.

Fig. 3.13 Internal structure of full-adder (Vsm-fullAdder.SCH)

Adding two four-bit numbers requires four cascaded full-adders as illustrated in Fig. 3.14. The carry signal propagates from the lower stage to the upper stage in order to perform the complete add operation. To subtract two numbers (B-A in this case) using the same full-adders, we need to build two supplementary things: • A circuit that produces the one’s complement of A • A small circuit that sets the initial carry to one. One approach consists of using multiplexer circuits, which may be found in Symbol palette → Advanced Symbol menu> sub-menu Switches. When Sel equals zero, the input i0 is transferred to the output. Otherwise, i1 is transferred to the output. Consequently, AddSub = 0 corresponds to the transfer of A to the adder chain (Add operation), while AddSub = 1 corresponds to the transfer of ~A to the adder chain (Subtract operation). At this point, it sounds very interesting to connect the accumulators and the arithmetic unit in order to perform manually what the microprocessor will later do with its internal sequencer. The circuit made of the accumulators A and B, and the arithmetic unit, is shown in Fig. 3.15. The two keyboards serve as inputs A and B. The displays are placed on the internal buses between the arithmetic units and the accumulators as well as on the output bus of the arithmetic unit.


Fig. 3.14

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Structure of the arithmetic unit, which performs the ADD and SUB operations (Vsm-ArithmeticUnit.SCH)

Trying to operate this simple circuit would be a very interesting introduction to the microprocessor’s operation. Below is the set of actions we need to perform sequentially in order to add two numbers: • De-active the main Reset. Initially the Reset pin is set to zero (default value at the start), which corresponds to an active Reset. Both registers A and B are cleared (A = 0, B = 0). Nothing will work until you set the button ~MainReset to one. • Load the desired value on A. Click on a digit on the lower keyboard named “A”, for example “3”. Click LatchA and wait for at least one complete cycle of the main clock. The accumulator A stores 3 at the falling edge of the clock. • Load the desired value on B. Click on a digit on the upper keyboard named “B”, for example “2”. Click LatchB and wait at least one complete cycle of the main clock. The accumulator B stores “2” at the falling edge of the clock. The arithmetic unit computes the sum A + B as AddSub is set to zero by default. This corresponds to the ADD instruction. However the result is not displayed, as EnableAlu is zero. • Set EnableAlu to one to display the result “5”, as shown in Fig. 3.15.

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Fig. 3.15

The connection between accumulators A and B, and the arithmetic unit to test ADD and SUB instructions (Vsm-RegARegBAlu.SCH)

3.5.4 The Input Register The input register is a simple set of three-state buffers as shown in Fig. 3.16. There is no need for D-registers as the input will be directly transferred to accumulator A.

Fig. 3.16 Input register (Vsm-InRegister.SCH)


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3.5.5 The Output Register The output register is composed of D-register cells as shown in Fig. 3.17. On the positive edge of the clock, the data is saved in the registers. It is very important that the data is stored on the positive edge of the clock during phase three, and not on the negative edge. The latter would give rise to synchronization conflicts. Therefore, a NAND gate is used to make the circuit sensitive to the rising edge of the main clock, as shown in Fig. 3.18.

Fig. 3.17 Internal structure of output register (Vsm-OutRegister.SCH)

Fig. 3.18 The output register must store data at the rising edge of the clock in phase three

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3.5.6 A Manual Microprocessor In this section, we propose to build a manually-controlled microprocessor which consists of accumulators A and B, and the input and output registers. The goal of the simulation reported in Fig. 3.19 is to transfer the input information (DataIn) to the output port (DataOut). To perform this transfer, we need to enable the input port (EnableIn = 1) and then enable the output port (EnableOut = 1). At the next rising edge of the main clock, the contents of the input keyboard (“5” in this case) will appear on the display connected to the output register. Several other transfers may be performed: • Input register to accumulator A • Input register to accumulator B • Result of the addition of A and B to the output port The arrow symbol (Symbol menu Advanced → Symbol → Arrow) is used to ease electrical connections for the clock and reset signals. In the example shown in Fig. 3.19, connections are made automatically among all arrows having the same name. Double click the Clk arrow symbol in Fig. 319 to access the arrow name which identifies the electrical net. In the example shown in Fig. 3.20, we build two different electrical connections, one called Clk and the other called Rst. Note that the electrical node names are not case sensitive.

Fig. 3.19 A manually-controlled microprocessor (Vsm-RegARegBAluInOut.SCH)


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Fig. 3.20 Building arrow connections to ease the electrical wiring of the main signals (Vsm_arrow.SCH)

3.5.7 The Phase Generator In order to transform the previous “manual” microprocessor into a fully-programmable microprocessor, we need to build several circuits to generate the appropriate control signals. First, the phase counter must produce the four phase signals Phase0 to Phase3 at the negative edge of the clock. The counter must be reset by an active low Clear signal. The design of the phase counter is based on edge-sensitive latches and XOR gates as shown in Fig. 3.21.

Fig. 3.21 Phase counter structure (Vsm-RingCounter4.SCH)

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Fig. 3.22 Simulation of phase counter (Vsm-RingCounter4.SCH)

When the Clear signal becomes inactive (logic high) the phases appear sequentially (Fig. 3.22). 3.5.8 Program Counter 0-to-15 The program counter plays a very important role in the microprocessor as it supplies the main program memory with the address of the active instruction (Fig. 3.23). At the start, the program counter is zero. At the end of each instruction the program counter is incremented in order to select the next instruction.

Fig. 3.23 The program counter supplies program memory with the address of active instruction


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One simple way to build a 0-to-15 counter is to use a cascaded chain of edge-sensitive D flip-flops, as shown in Fig. 3.24. The circuit is very simple, but works asynchronously. This means that due to propagation delays between stages, some intermediate results appear on the display for a very short period of time. These glitches have no impact on the microprocessor operation as the counter is incremented during phase two of the microinstruction sequence, and is only exploited during phase one of the next instruction to load the instruction register.

Fig. 3.24

Program counter at work. Counting is enabled only during phase two, at the falling edge of the main clock (Vsm-Counter16.SCH)

3.5.9 The Instruction Register The instruction register stores the instruction being executed. The eight-bit information is split into two parts: the most significant bits correspond to the instruction code, while the least significant bits are the data. The instruction code is stored in the four D-registers situated at the bottom of Fig. 3.25, in order to be available for the microinstruction decoder. The data is stored in four separate D-register cells and can be made available on the internal bus. The instruction register keeps a copy of the current instruction and releases the main memory, which can be accessed later for both read or write operation.

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Fig. 3.25

Instruction register stores contents of the memory and separates code part (lower registers) from data part (upper registers) (Vsm-InstructionReg.SCH)

3.5.10 The Microinstruction Controller The microinstruction controller is the ‘heart’ of the microprocessor. It generates the most important signals for controlling the operation of the processor, for example, the Enable and latch signals. The design of the microinstruction controller is shown in Fig. 3.26. The input to the microinstruction controller is the instruction code from the instruction register plus the phase information from the phase counter. The four-input AND gates serve as instruction decoders. For example, the instruction 0000 turns on the upper AND gate, which corresponds to the NOP instruction. Notice that phase0 and phase1 are not connected to the instruction decoder. This is because the first two phases are not dependent on the instruction itself. Then, depending on the type of instruction, the desired control signals are set to one if active, or kept at zero to be inactive.


Fig. 3.26

57

Control signals activated by the microinstruction controller during the first two time phases are same for all instructions and depend on instruction code during the last two phases

3.5.11 The Complete Microprocessor It is time now to connect all the sub-circuits together and test the entire microprocessor. Each of these sub-circuits has been embedded into a symbol where only the input and output pins appear. The complete circuit is shown in Fig. 3.27. We should keep in mind that this is only a very simple and very low complexity microprocessor. Before starting the simulation, we must load the program into the memory. The program shown in Table 3.5 has been written into the microprocessor’s memory.

Table 3.5 The code stored into program memory Mnemonic

OpCode (binary)

OpCode (hexa)

LDA 1 ADD 2 OUT

0101 | 0001 0001 | 0010 0011 | 0000

0 × 51 0 × 12 0 × 30

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Fig. 3.27 Microprocessor circuit ready for simulation (Vsm-Microprocessor.SCH)

Once simulation starts, there are several things to do in order to run the code: • De-active the reset signal MainClear (1) • Click on the main clock (2) • At each active edge of the clock, observe the phase counter shifting from phase0 to phase1, phase2, phase3 and back to phase0 (3). • Starting in phase two, the instruction is loaded into the microinstruction controller. The active instruction appears as shown in (4), which corresponds here to “Load (0101)”. • You can monitor the memory contents and the active memory location (5). • Also worth monitoring is the internal bus (6). • If required by the program, you can enter data through the keyboard named DataIn (7). • If the “OUT” instruction is running, the result should appear on the output display (8). At the end of the addition program, the screen appears as reported in Fig. 3.28. 3.5.12 Memory Move One important feature NOT handled by the very simple microprocessor is the memory move (MOVE). This instruction transfers the contents of a memory location to accumulator A or vice versa. Why did we not build this functionality into the first version of our processor? This is because the structure of the memory control and access must be deeply modified and would require a significant amount of supplementary hardware.


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Fig. 3.28 Final result of the addition of “1” and “2” using the program proposed in Table 3.5 (Vsm-Microprocessor.SCH)

Assuming that the MOVE operation transfers the contents of one memory location to A, we need to perform the following sequence of operations: during phase three, we need to have access to a new memory location, whose address is not the one currently stored in the program counter. This means that a new type of access must be provided in the processor from the internal bus to the memory, without altering the contents of the instruction register. The differences between the two structures are displayed in Fig. 3.29.

Fig. 3.29 Modifying the microprocessor to handle MOVE instruction

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In practice, the MOVE instruction can be incorporated by adding the following: • A direct path from memory to the internal bus (with its appropriate Enable control) • A four-bit address bus from the instruction register to the memory • A multiplexer for selecting a memory address either from the Program Counter or from the Instruction Register. 3.5.13 Physical Implementation

Description of the Design Flow The VSM processor has been described and simulated at logic level using DSCH, and saved under the name vsm-microprocessor.SCH. It can be converted automatically into layout using MICROWIND. The design flow is detailed in Fig. 3.30. First we create a VERILOG description of the VSM processor using the command File → Make Verilog File. The resulting text file vsm-microprocessor.TXT contains a VERILOG description of the processor. This file can be compiled in MICROWIND using the command Compile → Compile Verilog File in order to automatically generate the layout of the processor.

Fig. 3.30 Automatically generating the layout of VSM processor from logic circuit


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VERILOG Translation In its basic version, the microprocessor includes 312 primitives. This relatively small number of devices is due to the fact that the memory symbol is ignored during the translation to VERILOG. This is because the memory macro-cell used in the microprocessor design is not a real memory as it does not contain any real memory element such as flip-flops. The warning generated by DSCH during the VERILOG translation is shown in Fig. 3.31. A partial view of the VERILOG description of the VSM (vsmmicroprocessor.TXT) is shown in Fig. 3.32.

Fig. 3.31 Warning concerning the memory macro that has not been translated into a standard VERILOG description

Fig. 3.32 A partial view of VERILOG description of the four-bit microprocessor (vsm-microprocessor.TXT)

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3.5.14 Creating the Layout of the Complete Microprocessor To generate a complete layout of the microprocessor, we need to design a cell-based 8 × 8 bit memory that works exactly as the memory macro-cell. This can be done by constructing an array of 8 × 8 register cells based on very simple ring inverters as shown in Fig. 3.33. Data can be written to the memory cell via nMOS N1 when the Write control is high. Data is read from the cell when the Read control is high.

Fig. 3.33 Design of a very simple memory cell based on two ring inverters (Vsm-memorycell.SCH)

The design of an 8 × 8-bit memory array is shown in Fig. 3.34. There are eight memory cells in each row for storing the eight-bits of an instruction. At any one time only one memory location (one row) can be accessed by asserting one of the signals MemLocn0-MemLocn7. These eight signals are generated by the three-to-eight decoder shown in Fig. 3.35 using the three-bit address information (Addr2-Addr0). In Fig. 3.34, either the Read or the Write signal is asserted for a Read or a Write operation. The complete 8 × 8 memory including the address decoder is shown in Fig. 3.36. In order to generate a layout of the microprocessor we replace the memory macro (Vsm-Mem8×8 Macro.sch) used in the microprocessor of Fig. 3.27 with the real 8 × 8 memory block presented in Fig. 3.36. The new microprocessor containing this real memory block is shown in Fig. 3.37. Note that the three-bit address information can be supplied to the memory (VsmMem8×8) either from the top keypad titled Addr or from the program counter using a set of three multiplexers controlled by the WriteMem signal. During memory write operation (WriteMem is high) the address comes from the top keypad. Therefore the user is able to specify the memory addresses where to store instructions. When the processor executes instructions it reads the instructions from memory one after the other according to the addresses supplied from the program counter (WriteMem is low).


Fig. 3.34 An 8 × 8-bit memory array (Vsm-Mem8×8Array.SCH)

Fig. 3.35 A three-to-eight decoder for memory addressing (Vsm-3to8Decoder.SCH)

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64


Fig. 3.36 The complete 8 × 8 memory including address decoder (Vsm-Mem8×8.SCH)

Fig. 3.37 Complete microprocessor containing real memory (Vsm-ProcessorRealMem.SCH)


65

Follow the steps below for entering a program into the memory and then simulating the operation of the processor with the loaded program.

Program Entry Enter the program given in Table 3.5 into the processor memory as follows: • Start simulation in Dsch3. • The processor should be disabled by default. In any case it can be disabled by making sure that MainClear is active (low). • Assert the Memory Write signal by clicking the WriteMem button (high). • Enter address (0) using the top keypad titled Addr. The first memory location is now selected. • Enter the first instruction using the two bottom keypads titled Inst and Data. • Change addresses sequentially and enter the corresponding instructions. • No clocking is necessary for the program entry operation. • When all instructions are entered into the memory, click the WriteMem button in order to disable the memory write operation.

Program Execution • Enable the processor by deactivating the MainClear (high). • Cycle through various phases of processor operation by repeatedly clicking on the MainClock button until all instructions are executed by the processor. • At each active edge of the clock observe the phase counter shifting from phase0 to phase1, then phase2, then phase3, and back to phase0 for the next instruction. • You can observe the intermediate results in the top display (attached to the Arithmetic Unit) as each instruction is read and executed by the processor. • When the OUT instruction is executed, the final result appears on the output display (attached to the Output Register). Figure 3.38 shows the simulation results from execution of the program given in Table 3.5. More details about the implementation of the VSM microprocessor may be found on the web site of MICROWIND [3], and concern the interfacing of the microprocessor to the external world.

3.6 Conclusion In this chapter, the design of a very simple four-bit microprocessor has been presented. The basic processor implements five instructions. This gives the foundations for building more complex processors with extended instruction sets, more sophisticated exchanges between the main memory and the accumulators, and more powerful arithmetic units, in order to build a more attractive microprocessor.

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Fig. 3.38 Simulation results for addition of ‘1’ and ‘2’ by a processor using the program given in Table 3.5

References [1] A. P. Malvino, J.A. Brown, Digital computer electronics, Third Edition, Glenco-Macmillan, 1992, ISBN 0-02-800594-5, USA. [2] E. Sicard, S. Bendhia, Basics of CMOS Cell design, Tata McGraw-Hill, 2005, IBSN 0-07-059933-5. [MICROWIND] The MICROWIND web site is www.microwind.org

EXERCISES 1. Modify the microprocessor in order to handle the MOVE operation from the memory to the accumulator A, according to the recommendations of Fig. 3.29. The instruction code can be 0110, with the op-code MOVE. 2. List the necessary hardware and supplementary control signals in order to perform the STORE operation from accumulator A to a desired memory location. 3. Modify the arithmetic unit in order to perform the Shift Right one bit (SHR, coded 1000) and Shift Left one bit (SHL, coded 1001) operations. What new input do you need to add? In order to reduce the number of ALU controls, how can you handle the ADD, SUB, SHR and SHL signals? 4. Modify the microinstruction controller to handle the ADD, SUB, SHR and SHL operation. 5. Test the new microprocessor with these enhanced functions.

Field-Programmable Gate Array

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4 Field-Programmable Gate Array This chapter introduces the principles, implementation and programming of configurable logic circuits, from the point-of-view of cell design and interconnection strategy.

4.1 Introduction Field-Programmable Gate Arrays (FPGA) are specific ICs that can be user-programmed easily. The FPGA contains versatile functions, configurable interconnects and an input/output interface to adapt to the user specification. FPGAs allow rapid prototyping using custom logic structures, and are very popular for limited production products. Modern FPGAs are extremely dense, with a complexity of several millions of gates which enable the emulation of very complex hardware such as parallel microprocessors, mixture of processor and signal processing, and so on. One key advantage of FPGAs is their ability to be reprogrammed, in order to create a completely different hardware by modifying the logic gate array. The usual structure of FPGA is given in Fig. 4.1. One example of a very simple function (three-input XOR) implemented in a FPGA is given in Fig. 4.2. Three pads on the left are configured as inputs, one logic block is used to create the three-input XOR and one pad on the right is used as output. The propagation of signals is handled by interconnect lines, connected together at specific programmable interconnect points. Three pads are configured as inputs and represent the logical information A, B and C (Fig. 4.3). An internal routing path is created to establish an electrical link between the I/O region and the logic block. Internally, the logic block may be configured in any combination of sequential basic functions. Each logic block usually supports three to eight logic inputs. In our example, the block is configured as a three-input XOR. Then, other internal routing wires are configured in order to carry out the signal to an I/O pad configured as an output. The global propagation delay of such architecture is evidently very high, if compared to a three-input XOR gate that may be found in the cell library. This is usually the price to pay for configurable logic circuits. Copyright © 2007 by The McGraw-Hill Companies, Inc. Click here for terms of use.

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Configured I/O pads

Programmable logic blocks

Programmable interconnected points

Fig. 4.1 Basic structure of an FPGA

Fig. 4.2 Using an FPGA to build a three-input XOR gate

Notice that FPGAs not only exist as simple components, but also as macro-blocks in system-on-chip designs (Fig. 4.4). In the case of communication systems, the configurable logic may be dynamically changed to adapt to improved communication protocols. In the case of very-low-power systems, the configurable logic may handle several different tasks in series, rather than embedding all corresponding hardware that never works in parallel.


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Fig. 4.3 Equivalent circuit for FPGA configured in XOR3 gate

Fig. 4.4 FPGAs exist as stand-alone ICs or blocks within a system-on-chip

4.2 Configurable Logic Circuits The programmable logic block must be able to implement all basic logic functions, that is INV, AND, NAND, OR, NOR, XOR, XNOR, and so on. Several approaches are used in the FPGA industry to achieve this goal. The first approach consists in the use of multiplexors, the second one in the use of look-up tables.

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Multiplexors Surprisingly, a two-input multiplexor can be used as a programmable function generator, as illustrated in Table 4.1. Remember that the multiplexor output f is equal to i0 if en = 0, and i1 if en = 1. For example, the inverter is created if the multiplexor input i0 is equal to one, i1 is equal to zero, and enable is connected to A. In that case, the output f is the ~A. Figure 4.5 describes the use of multiplexors to produce the OR, AND, NOT and BUF functions. Table 4.1 Use of multiplexor to build logic functions Function

Boolean expression for output f

i0

i1

en

BUF(A)

f=A

0

A

1

NOT(A)

f=~(A)

1

0

A

AND(A,B)

f=A&B

0

B

A

OR(A,B)

f=A|B

B

1

A

Fig. 4.5 Use of multiplexors to build logic functions (fpgaMux.SCH)

Although NOT, AND and OR are directly available, other functions such as NAND, NOR and XOR cannot be built directly using a single two-input multiplexor, but need at least two multiplexor circuits. The XOR function is shown in Fig. 4.6. The four-input XOR gate would require six multiplexor cells. Remember that each multiplexor cell consists of a minimum of six transistors for a buffered output, and has three delay stages (two inverters and the pass transistor). The XOR4 implementation would comprise


71

Fig. 4.6 The XOR gate built from two multiplexor circuits (fpgaMux.SCH)

a total of 18 delay stages, which are far too important. Therefore, the multiplexor approach is not very efficient for many logical functions. Look-Up Table The Look-Up Table (LUT) is by far the most versatile circuit to create a configurable logic function [1]. The LUT shown in Table 4.2 has three main inputs F0, F1 and F2. The main output is Fout, which is a logical function of F0, F1 and F2. The output Fout is defined by the values given to Value[0]..Value[7]. The three values F0, F1, F2 create a three-bit address i between zero and seven, so that Fout gets the value of Value[i]. In the example given in Fig. 4.7, the input creates the number “5”, so Value[5] is routed to Fout. Table 4.2 gives Value[i] for the most common logical functions of F0, F1 and F2.

Fig. 4.7 The 3-bit address i selects one of the 8 values

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Table 4.2 Link between basic logic functions and the information stored in Value[0]..[7] Function

Value[0]

Value[1]

Value[2]

Value[3]

Value[4]

Value[5]

Value[6]

Value[7]

~F0

0

1

0

1

0

1

0

1

~F1

0

0

1

1

0

0

1

1

~F2

0

0

0

0

1

1

1

1

F0&F1

0

0

0

1

0

0

0

1

F0|F1|F2

0

1

1

1

1

1

1

1

F0^F1^F2

0

1

1

0

1

0

0

1

In the case of the three-input XOR, (F0^F1^F2) the set of values of Fout given in the truth-table of Table 4.3, must be assigned to Value[0]..Value[7]. In the schematic diagram shown in Fig. 4.8 we must assign manually the Fout truth-table to each of the eight buttons. Then Fout produces the XOR function of inputs F0, F1 and F2. Table 4.3 Truth-table of the three-input XOR gate for its implementation in an LUT F2

F1

F0

Fout= F0^F1^F2

Assigned to

0

0

0

0

Value[0]

0

0

1

1

Value[1]

0

1

0

1

Value[2]

0

1

1

0

Value[3]

1

0

0

1

Value[4]

1

0

1

0

Value[5]

1

1

0

0

Value[6]

1

1

1

1

Value[7]

Memory Points Memory points are essential components of the configurable logic blocks. The memory point is used to store one logical value, corresponding to the logic truth-table. For a three-input function (F0, F1, F2 in the previous LUT), we need an array of eight memory points to store the information Value[0]..Value[7]. There exist here also several approaches to store one single bit of information. The one that is illustrated in Fig. 4.9 consists of D-reg cells. Each register stores one logical information Value[i]. The Dreg cells are chained in order to limit the control signals to one clock ClockProg and one data signal DataProg. The logical data Value[i] is fully programmed by a word of eight bits sent in series to the signal DataProg.


Fig. 4.8

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The output f produces a logical function Fout according to an LUT stored in memory point Value[i] (FpgaLutStructure.SCH)

The configuration of the three-input LUT into a three-input XOR gate follows a strict protocol described in Fig. 4.10. A series of eight active edges is generated by the ClockProg signal (Dreg is active on fall edges). This is done by configuring a pulse-generator with series of zero and one as shown below. At each active edge, the shift register is fed by a new value presented sequentially at input DataProg (Fig. 4.11). As the D-reg is active on fall edge, data may be changed on each rise edge. Notice that the last register corresponds to Value[7]. Therefore, Value[7] must be inserted first, and Value[0] last. This means that the DataProg pulse must describe the truth-table in reverse order, as shown below. Most FPGA designs use D-reg cells to store the LUT configuration. Notice that the configuration is lost when the power supply is down. Fuse and Antifuse To retain the configuration even without power supply, non-volatile memories must be used. A one-time programmable non-volatile memory is the fuse [1][2]. Usually, a contact between metal layers is used as a fuse, as an over-current would blow its structure, as illustrated in Fig. 4.12. Although this technique induces severe damages close to the contact, no specific technological layer is required as it is a CMOS compatible approach.

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Fig. 4.9 The look-up information is given by a shift register based on D-reg cells (FpgaLutDreg.SCH)

Fig. 4.10 Programming the ClockProg pulse to generate eight active edges (FpgaLutDreg.SCH)


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Fig. 4.11 At the end of the eighth clock period, the LUT is configured as a three-input XOR (FpgaLutDreg.SCH)

Fig. 4.12 Contact fuse

A driver with large channel width (several µm), supplied by the highest available voltage (VDDH) generates a very strong current pulse. The schematic diagram of the fuse circuit is shown in Fig. 4.13. When the command BlowFuse is active, both nMOS and pMOS devices are on, leading to a short circuit current. This current must be higher than 15 mA to destroy the contact. In contrast to the fuse, the normal state of the antifuse is to be opened. In the example shown in Fig. 4.14, a thin insulator interrupts the contact between metal1 and metal2. A very high voltage applied between metal1 and metal2 (typically 10 V) breaks the oxide and provokes a conductive path between the metal layers. The use of very high voltage on the chip requires a careful use of high-voltage MOS, and of specific I/O pads, to ensure that no part of the circuit is damaged. Another popular structure, called ONO (Oxide, Nitride, Oxide) leads to a resistive path when programmed. The typical value of the resistance is 500 Ω. Statistically, the spread of the resistance is much larger for the SiO2 than for the ONO fuse [1]. This makes the ONO fuse more attractive, at the price of supplementary process steps.

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Fig. 4.13 Fuse circuit programming (FuseCircuits.SCH)

Fig. 4.14 The antifuse principles and the comparative resistance spread for ONO and SiO2

Other types of non-volatile memories are being used for hardware programming of FPGA arrays: EEPROM and FRAM memories. These memories are not altered when the power supply is down, and can be reprogrammed a large number of times. These types of memory cells are detailed in Chapter Nine. Implementation in DSCH In DSCH, an LUT symbol is proposed in the symbol menu (Fig. 4.15). It is equivalent to the schematic diagram of Fig. 4.8. An important property of the LUT symbol is its ability to retain the internal programming as a non-volatile memory would do. The user’s interface of the LUT symbol is given in Fig. 4.15. There are three ways of filling the LUT. One consists in defining each array element with a zero or a one. The number corresponds to the logic combination of inputs F2, F1, F0. For example n°4 is coded 100 in binary, corresponding to F2 = 1, F1 = 0 and F0 = 0. A second solution consists in choosing the function description in the list. The logic information Fout assigned to each combination


77

of inputs updates the LUT. A third solution is also proposed: enter a description based on inputs F0, F1 and F2, and the logic operators “~” (Not), “&” (And), “|” (Or) and “^” (Xor). Then click the button Fill LUT to transfer the result of the expression to the table.

Fig. 4.15 The LUT symbol

4.3 Programmable Logic Block The programmable logic block consists of a LUT, a D-register and some multiplexors. There exist numerous possible structures for logic blocks. We present in Fig. 4.16 a simple structure which has some similarities with the Xilinx XC5200 series (See [1] for detailed information on its internal structure). The configurable block contains two active structures, the LUT and the D-register, that may work independently or be mixed together. The output of the LUT is directly connected to the block output Fout. The output can also serve as the input data for the D-register, thanks to the multiplexor controlled by DataIn_Fout. The DataOut net can simply pass the signal DataIn. In that case the cell is transparent. The DataOut signal can also pass the signal nQ, depending on the multiplexor status controlled by DataIn_nQ

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Fig. 4.16 Simple configurable logic block including the LUT and a D-register (FpgaCell.SCH)

The block now consists of the LUT and the D-register. We chain the information DataIn_Fout and DataIn_nQ on the path of the shift register by adding two supplementary Dreg cells. Each Dreg still uses the same clock ClockProg and chained input data DataProg. The complete circuit is shown in Fig. 4.17.

Fig. 4.17

LUT, D-register and shift register, including the two multiplexor cells (FpgaBlockStructure.SCH)


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Configuring of the block is achieved thanks to 10 active clock edges on ClockProg, and 10 serial data bits on DataProg (Table 4.4). The chain of Dreg starts at Dreg0 (upper Dreg in Fig. 4.17, which produced Value[0]) and stops at Dreg9 (right side of Fig. 4.17 which produced DataIn/nQ). The information that flows at the far end of the register chain is defined at the first cycle, while the closest register is configured by the data present at the last active clock edge. Table 4.4 Serial data information used to program LUT memory points

Clock cycle DataProg

1

2

3

4

5

6

7

8

9

10

DataIn/ Nq

DataIn/ Fout

Val [7]

Val [6]

Val [5]

Val [4]

Val [3]

Val [2]

Val [1]

Val [0]

4.4 Interconnection Between Blocks The interconnection strategy between logic blocks is detailed in this paragraph. We shall focus on the programmable interconnect point and the programmable switching matrix. Then, we will discuss the global implementation of the structure. Programmable Interconnect Point The elementary programmable interconnect point (PIP) may be found in the Advanced set of Switches symbols (Fig. 4.18). It consists of a configurable bridge between two interconnects. The PIP may have two states: ‘On’ and ‘Off’. You may switch from ‘On’ to ‘Off’ by a double-click on the symbol (screen shown in Fig. 4.19) and a click on the button On/off. The bridge can be built from a transmission gate, controlled once again by a D-reg cell (Fig. 4.20). When the register information contains a zero, the transmission gate is off and no link exists between Interco1 and Interco2. When the information held by the register is one, the transmission gate establishes a resistive link between Interco1 and Interco2. The resistance value is around 100 Ω. The regrouping of programmable interconnect points into a matrix is of key importance to ensure the largest routing flexibility. Examples of three × three and three × two PIP matrices are shown in Fig. 4.21.

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Fig. 4.18 The PIP in the palette of symbols

Fig. 4.19 Changing the state of PIP (FpgaPip.SCH)


(a) Switch off

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(b) Switch on

Fig. 4.20 Internal structure of PIP and illustration of its behavior when (a) Off and (b) On (FpgaPip.SCH)

The link between In1 and Out1, In2 and Out2, In3 and Out3 is achieved by turning some PIP on. A specific routing tool usually handles this task, but the manual re-arrangement is not rare in some complex situations. In DSCH, just press the key “O” to switch the PIP On and Off.

Fig. 4.21 Matrix of PIPs (FpgaPip.SCH)

Switching Matrix The switching matrix is a sophisticated programmable interconnect point, which enables a wide range of routing combinations within a single interconnect crossing. The aspect of the switching matrix is given in Fig. 4.22. The matrix includes six configurable bridges between the two main interconnects. The switching matrix symbol may be found in Advanced set of Switches symbols. By a double-click on the matrix symbol, you can access the six On/Off switches. To ease the programming of the matrix, short-cuts exist in DSCH. You can change the state of the matrix by placing the cursor on the desired symbol and pressing the following keys: • To switch off the matrix, press the key “O”.

82


Fig. 4.22 Changing the state of matrix (FpgaMatrix.SCH)

• To switch on the matrix, press the key “O”. • To enable an horizontal link, press the key “-”. • To enable a vertical link, press the key “|”. Examples of three × two and three × three switching matrices are given in Fig. 4.23. The routing possibilities are numerous, which improves the configurability of the logic blocs. Implementation of the Switching Matrix From a practical point-of-view, the switching matrix can be built from a regrouping of six transmission gates (Fig. 4.24). Each transmission gate is controlled by an associated Dreg cell, which memorizes the desired configuration. The D-reg cells are chained so that one single input DataIn and one clock LoadClock are enough to configure the matrix. Array of Blocks The configurable blocks are associated with programmable interconnect points and switching matrix to create a complete configurable core. An example of a double configurable block and its associated configurable routing is proposed in Fig. 4.25.


83

Fig. 4.23 Three × two switching matrix and example of routing strategy between six inputs and outputs (fpgaMatrix.SCH)

Full-Adder Example The truth-table and logical expression for the full-adder are recalled in Table 4.5. The implementation of the CARRY and SUM functions is achieved by programming two LUTs according to the truth-tables reported in Table 4.4.

Fig. 4.24 Transmission gates placed on routing lines to build the matrix (FpgaMatrix3.SCH)

84


Fig. 4.25 Configurable blocks, switching matrix, configurable I/Os and arrays of PIP (fpga2blocks.SCH)

Table 4.5 Full-adder truth-table Full Adder A B

C

SUM

CARRY

RESULT

0

0

0

0

0

0

0

0

1

1

0

1

0

1

0

1

0

1

0

1

1

0

1

2

1

0

0

1

0

1

1

0

1

0

1

2

1

1

0

0

1

2

1

1

1

1

1

3

The general diagram of the full-adder implementation is given in Fig. 4.26. One programmable logic block Block1 supports the generation of the sum for given logic values of the inputs A, B and C. The information needed to configure Block1 as a SUM function (three-input XOR) is given in Table 4.6. Notice that we only use the LUT in this programmable logic block. The Dreg is not active, and we only exploit the output of the LUT Fout, which is configured as the SUM. The signal SUM propagates outside the block to the output interface region by exploiting the interconnect resources and switching matrix. The other programmable logic block Block2 supports the generation of


85

Fig. 4.26 SUM and CARRY functions to realize full-adder in FPGA (fpgaFullAdder.SCH)

the signal CARRY, from the same inputs A, B and C. The programming of Block2 is also given in Table 4.6. The result CARRY is exported to the output interface region as for the SUM signal. Again, in this block, only the LUT is active. Table 4.6 Serial data used to configure the logic blocks 1 & 2 as SUM and CARRY Block 1 (Sum of F0, F1 and F2) Cycle 1

2

3

4

5

6

7

8

9

10

DataIn Nq

Datain Fout

Val[7]

Val[6]

Val[5]

Val[4]

Val[3]

Val[2]

Val[1]

Val[0]

0

1

0

0

1

0

1

1

0

0

Block 2 (Carry of F0, F1 and F2) Cycle 1

2

3

4

5

6

7

8

9

10

DataIn Nq

Datain Fout

Val[7]

Val[6]

Val[5]

Val[4]

Val[3]

Val[2]

Val[1]

Val[0]

0

1

1

1

0

1

1

0

0

0

The programming sequence is contained in the piece-wise-linear symbols ProgBlock1 and ProgBlock2. As seen in the chronograms of Fig. 4.28, the program clock ClockPgm is only active at the initialization phase, to shift the logic information to the memory points inside the blocks which configure each multiplexor. The routing of the signals A, B and C as well as Sum and Carry has been done manually in the circuit shown in Fig. 4.27. In reality, specific placement/routing tools are provided to generate the electrical structure automatically from the initial schematic diagram, which avoids manual errors and limits conflicts or omissions.

86


Fig. 4.27 Simulation of the full-adder implemented in two configurable blocks (fpgaFullAdder.SCH)

Fig. 4.28 Chronograms of the full-adder FPGA (fpgaFullAdder.SCH)


87

Clock Divider Example A second example is proposed as an application of the FPGA circuits. It concerns clock division. We recall in Fig. 4.29 the general structure and the typical chronograms of the clock division by four, which requires two Dreg cells, with a feedback from the output ~Q to the input D.

Fig. 4.29 Diagram and typical simulation of the clock divider by four (ClockDiv4.SCH)

The general diagram of the clock divider implementation is given in Fig. 4.30. Each programmable logic block is configured as a single-stage clock divider. The information needed to configure Block1 as a simple Dreg function is given in Table 4.7. This serial data information creates a direct path from DataIn to input D of the Dreg cell, while nQ propagates to DataOut, as detailed in Fig. 4.31.

Fig. 4.30

Implementation of the clock divider in two configurable blocks (FpgaDiv4.SCH)

88


Fig. 4.31 Use of the configurable block as a DReg (FpgaDiv4.SCH)

Table 4.7 Serial data used to configure the logic blocks 1 & 2 as clock dividers (FpgaDiv4.SCH) Block 1 (DataOut=nQ, D=DataIn) Cycle 1

2

3

4

5

6

7

8

9

10

DataIn Nq

Datain Fout

Val[7]

Val[6]

Val[5]

Val[4]

Val[3]

Val[2]

Val[1]

Val[0]

0

0

0

0

0

0

0

0

0

1

Block 2 (DataOut=nQ, D=DataIn) Cycle 1

2

3

4

5

6

7

8

9

10

DataIn Nq

Datain Fout

Val[7]

Val[6]

Val[5]

Val[4]

Val[3]

Val[2]

Val[1]

Val[0]

0

0

0

0

0

0

0

0

0

1

Outside the programmable block, the signal nQ propagates to the input DataIn. Notice that the LUT is inactive in this configuration. The other programmable logic block Block2 is also programmed as a Dreg circuit with a feedback from nQ to DataIn (Fig. 4.31). The simulation of the counter is proposed in Fig. 4.33. The first nanoseconds are dedicated to the programming of the blocks. Once properly configured, the counter starts to work according to the


89

Fig. 4.32 Routing of the clock divider in two configurable blocks (FpgaDiv4.SCH)

Fig. 4.33 Chronograms of the clock divider circuit (ClockDiv4.SCH)

specifications of Fig. 4.29. Notice the very important delay in responding to the active edges. This is due to the intrinsic complexity of the configuration block, and to the long interconnect delay through the connection points and switching matrix.

90


4.5 Conclusion In this chapter, we have given a brief introduction to field programmable gate arrays, from the point of view of cell design. Firstly, the use of multiplexor and look-up-tables for building configurable logic circuits has been illustrated. Secondly, the programming of memory points using chained registers and fuse has been described. Thirdly, we have described the programmable interconnect points and switching matrix, with their implementation in DSCH. Finally, the implementation of a full adder and a clock divider have been performed using two configurable logic blocks, programmable interconnect points and switching matrix.

References [1] Michael. J.S. Smith, Application Specific Integrated Circuits, Addison Wesley, 0-201-50022-1. [2] A.K. Sharma, Semiconductor Memories, Technology, Testing and Reliability, IEEE Press, 1997, ISBN 0-7803-1000-4. [3] John P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and Simulation, 2006, ISBN 0-534-46629-X.

EXERCISES 4.1 Using DSCH, configure the 16 switching matrix in order to connect: switch1 to lights L3 and L5, switch2 to lights L1 and L6, switch3 to lights L2 and L4, switch4 to lights L7 and L8.

Fig. 4.34 Routing exercise

4.2 Store the following eight bits (01110111) (reading from left to right) in the LUT, as in Fig. 4.4. How many active edges on ClockProg do you need to configure the LUT? Which logical function have you realized?


Answer: (a) 8

91

(b) Fout = F 2 + F1 ⋅ F 0

4.3 Store the eight bits (00000111) (reading from left to right) in the LUT of Fig. 4.8. Demonstrate that you have realized the following logical function: F 2 + ( F1 ⋅ F 0) ) . Using two LUTs and one inverter, create the D_Latch shown below. Give the serial data sequence for DataProg.

Fig. 4.35 Implementing a D_latch in FPGA

Answer: (a) F 0 ⋅ F1 ⋅ F 2 + F 0 ⋅ F1 ⋅ F 2 + F 0 ⋅ F1 ⋅ F 2 = F 2 + ( F1 ⋅ F 0 ) (b) LUT N°1: F 0 = Data, F1 = Clock , F 2 = nQ , DataProg = 00000111, LUT N°2: F 0 = Data, F1 = Clock , F 2 = Q , DataProg = 00000111 4.4 How many programmable logic blocks do you need to create the following asynchronous counter (Fig. 4.36)? Give the programmable sequences for each block.

Fig. 4.36 Implementing an asynchronous counter in FPGA

Answer: Three blocks

92


4.5 Using programmable logic blocks create a one-bit comparator. The truth-table is given below. Table 4.8 The comparator A

B

A>B

A 2. fsignal

(Eq. 6.5)

Figure 6.30 shows the sampling of a 500 MHz sinusoidal input wave (fsignal) with a sampling frequency fsample of 2.5 GHz which complies largely with Shannon’s theorem. In Fig. 6.30 the sampling frequency fsample is too low (600 MHz), and consequently the sampled output Vin* is significantly different from Vin.

Fig. 6.30 The sampling frequency is too slow: Vin* differs from Vin (SampleHoldShannon.MSK)

6.4 Analog-Digital Converter Architectures The analog-to-digital converter is considered as an encoding device, where an analog sample is converted into a digital quantity with N number of bits. Figure 6.31 shows the complete chain from the analog signal to the digital data using a sampled-and-hold module and a four-bit ADC. ADCs can be implemented by employing a variety of architectures. In the following chapters, we describe the flash converter and successive-approach converters.

Fig. 6.31 A four-bit digital conversion of a sampled analog voltage

6.4.1 The Flash Converter Principles The two-bit analog-digital converter converts an analog value Vin into a two-bit digital value A coded on two bits A1, A0. The flash converter uses three amplifiers, which produce results C0, C1 and C2, connected

Converters and Sensors 177

to a coding logic to produce A1 and A0 in a very short delay (Fig. 6.32). The flash converters are widely used for very high sampling rates, at the cost of very important power dissipation. Table 6.3 The specifications for a two-bit flash ADC converter Analog Input Vin

C2

C1

C0

A1

A0

Vin

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Analog Design for CMOS VLSI Systems

Nano-CMOS Circuit and Physical Design

Design of Analog CMOS Integrated Circuits (Solutions)

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Analog design for CMOS VLSI systems

CMOS. Circuit Design, Layout, and Simulation

Design of Analog CMOS Integrated Circuits

Advanced Programming Language Design

Advanced programming language design

Advanced Programming Language Design

Advanced programming language design

Advanced CMOS Cell Design

Advanced Cmos Process Technology

Structured Analog CMOS Design

CMOS RFIC Design Principles

Cmos Logic Circuit Design

CMOS VLSI design

CMOS Logic Circuit Design

Cmos Logic Circuit Design

ESD Protection Device and Circuit Design for Advanced CMOS Technologies

Multi-voltage CMOS Circuit Design

wireless cmos frequency sythesizer design

AdvancED Flash Interface Design (Advanced Design)

AdvancED Flash Interface Design (Advanced Design)

AdvancED Flash Interface Design (Advanced Design)

Multi-voltage CMOS Circuit Design

CMOS Mixed-Signal Circuit Design

CMOS-MEMS: Advanced Micro and Nanosystems

CMOS-MEMS: Advanced Micro and Nanosystems

Tradeoffs and Optimization in Analog CMOS Design

CMOS Digital Integrated Circuits Analysis & Design

Analog Design for CMOS VLSI Systems

Nano-CMOS Circuit and Physical Design

Design of Analog CMOS Integrated Circuits (Solutions)

Low Power CMOS VLSI: Circuit Design

Analog design for CMOS VLSI systems

CMOS. Circuit Design, Layout, and Simulation

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