Demystifying Chipmaking

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Author: Richard F. Yanda | Michael Heynes | Anne Miller

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$EMYSTIFYING#HIPMAKING

BY2ICHARD&9ANDA -ICHAEL(EYNES AND!NNE+-ILLER

.EWNESISANIMPRINTOF%LSEVIER #ORPORATE$RIVE 3UITE "URLINGTON -! 53! ,INACRE(OUSE *ORDAN(ILL /XFORD/8$0 5+ #OPYRIGHTÚ %LSEVIER)NC!LLRIGHTSRESERVED .OPARTOFTHISPUBLICATIONMAYBEREPRODUCED STOREDINARETRIEVALSYSTEM OR TRANSMITTEDINANYFORMORBYANYMEANS ELECTRONIC MECHANICAL PHOTOCOPYING RECORDING OROTHERWISE WITHOUTTHEPRIORWRITTENPERMISSIONOFTHEPUBLISHER 0ERMISSIONSMAYBESOUGHTDIRECTLYFROM%LSEVIERS3CIENCE4ECHNOLOGY2IGHTS $EPARTMENTIN/XFORD 5+PHONE FAX E MAILPERMISSIONS ELSEVIERCOMUK9OUMAYALSOCOMPLETEYOURREQUESTON LINEVIA THE%LSEVIERHOMEPAGEHTTPELSEVIERCOM BYSELECTINGh#USTOMER3UPPORTvANDTHEN h/BTAINING0ERMISSIONSv 2ECOGNIZINGTHEIMPORTANCEOFPRESERVINGWHATHASBEENWRITTEN %LSEVIERPRINTSITSBOOKSONACID FREEPAPERWHENEVERPOSSIBLE ,IBRARYOF#ONGRESS#ATALOGING IN 0UBLICATION$ATA !PPLICATIONSUBMITTED "RITISH,IBRARY#ATALOGUING IN 0UBLICATION$ATA !CATALOGUERECORDFORTHISBOOKISAVAILABLEFROMTHE"RITISH,IBRARY )3". &ORINFORMATIONONALL.EWNESPUBLICATIONS VISITOUR7EBSITEATWWWBOOKSELSEVIERCOM 0RINTEDINTHE5NITED3TATESOF!MERICA

Contents Foreword

........................................................................................................... xi... ............................................................................................. xiii

Acknowledgments

.............................................................................................. .................................................................................. . . Chapter 1: IC Fabrication Overview....................................................................... Section 1 : Introduction ...........................................................................................

About the Authors What’s on the CD-ROM?

1.1 Integrated Circuits .............................................................. 1.2 The Semiconductor Industry ...................... Section 2: Support Technologies

............................... ...............................

.............................................................................

xv

..

XVII

1 3

3 6 7

2.1 Crystal Growth and Wafer Preparation ......................................... . . 2.2 Contamination Control ...................................................... ............................... 8 2.3 Circuit Design and Mask Making .............. ............................. 10 2.4 Process Diagnostics and Metrology ...................................................................... 12 Section 3: Integrated Circuit Fabrication

...............................................................

3.1 Layering ................................................................................................................ 3.2 Patterning .............................................................................................................. 3.3 Doping .................................................................................................................. 3.4 Process Control and In-line Monitoring ............................................................... Section 4: Test and Assembly

................................................................................

4.1 Electrical Tests ..................................................................................................... 4.2 Die Separation ....................................................................................................... 4.3 Die Attach and Wire Bonding ............................................................................... 4.4 Encapsulation ........................................................................................................ 4.5 Final Test ............................................................................................................... Section 5: Summary .............................................................................................. Chapter 2: Support Technologies .........................................................................

......................................................................................... .........................................................................

Section 1 : Introduction . . Section 2: Contamination Control

2.1 Why Control Contamination? ............................................ ............................. ........................................... 2.2 Contamination Sources ..............................

V

13

13 18 21 22 25

25 25 25 26 26 27

29 31 33

33 35

Contents

2.3 The Cleanroom .................. ....................................................... Section 3: Crystal Growth and Preparation ...................................................... ......................................... ion .................................... ......................................... 3.3 Czochralski Silicon Growth ...................................................... 3.4 Shaping, Grinding. Cutting Polishing ......................... 3.5 Final Inspection and Shipping ............................... ......................................... Section 4: Circuit Design 4.1 Introduction ........................ ....................................................... 4.2 Product Definition and Ne duct Plan ......................... ......................................... 4.3 The Design Team ...................................................

.............................

.............................................

.....................................

4.4 The Design Process ................................................ ......................................... 4.5 Design Verification and Tapeout ........................................................................... Section 5: Photomask and Reticle Preparation...................................................... 5.1 Introduction ........................................................................................................... 5.2 Reticle Substrate Preparation ................................................................................ 5.3 Pattern Transfer ..................................................................................................... 5.4 Inspection and Defect Repair ................................................................................

................................................................................... ......................................................................................... .................................................................................... ..................................................................................

Chapter 3: Forming Wells

Section 1 : Introduction Section 2: Initial Oxidation Section 3: Photolithography 3.1 Introduction ........................ ....................................................... 3.2 Coat (Spin) ............. ...................................................... ............................. 3.3 Exposure (Step) ...................................................... ......................................... 3.4 Develop ..................................................... ..................................................... 3.5 After Develop Inspect (ADI) .......................................................... Section 4: Ion Implantation

................................................................................... Chapter 4: Isolate Active Areas (Shallow Trench Isolation) ..................................... Section 1: Introduction to Shallow Trench Isolation............................................... Section 2: Pad Oxide Growth ................................................................................ Section 3: Silicon Nitride Deposition ................................................................... Section 4: Photolithography for Photo/Etch........................................................ Section 5: Hard Mask Formation Using Plasma Etch ...........................................

41 42

47 49 53 55 57 59 59 59 60 61 63 65 71 79

a3 a4 87

93 95 99 101 105 107 5.1 Hard Mask Overview .......................................................................................... 107 109 5.2 Plasma Etch Overview ........................................................................................ 5.3 Etch Chemistry: Silicon Dioxide and Silicon Nitride ......................................... 114 Section 6: Form Trenches in Silicon with Plasma Etch.......................................... 119 Section 7: Fill Trenches with Silicon Dioxide ........................................................ 121 Section 8: Chemical Mechanical Polishing (CMP) to Remove Excess Dioxide .......123

vi

Contents Section 9:W e t Etch Removal o f Silicon N i t r i d e and Pad Oxide

............................ Chapter 5: Building the Transistors.................................................................... Section 1 : Introduction ....................................................................................... Section 2:Thin Film Formation ...........................................................................

......................................... 2.1 Gate Dielectric Oxidation .. 2.2 Polycrystalline Silicon (Poly) Deposition .................................................. 2.3 Nitride Cap Deposition ...................................................... Section 3: Poly Gate Formation........................................................................... ......................................... 3.1 Photoresist Patterning ........ 3.2 Plasma Etch .........................................................................................................

127 129 131 137 137

143 143 144 Section 4: Source/Drain Formation ..................................................................... 147 4.1 Introduction ......................................................................................................... 147 4.2 Shallow Implant .................................................................................................. 149 4.3 Spacer Formation ................................................................................................ 149 4.4 High-Dose Implant ............................................................................................. 151 4.5 Anneal ................................................................................................................. 151 .. Section 5: Salicide Formation .............................................................................. 153 5.1 Sputter Cobalt .................................................................................................... 155 5.2 RTP Reaction Forming Silicide .......................................................................... 155 5.3 Strip Residual Cobalt .......................................................................................... 156 156 5.4 Anneal the Silicide ..............................................................................................

.................................................................. ....................................................................................... ............................................................

Chapter 6: First Level Metallization Section 1 : Introduction Section 2: N i t r i d e and Oxide Depositions . . .. 2.1 Nitride Deposition .............................................................. ......................................... 2.2 Oxide Deposition ........................... Section 3: C M P Planarization Section 4:Photo/Etch for Contact Holes 4.1 Contact Hole Photolithography ......................................... ......................................... 4.2 Contact Etch ................................... Section 5:Tungsten Plug Process 5.1 Deposit Ti/TiN Barrier/Glue Layers ..........................................................

................

........................................................ ............................................................

164 167 169

........................................................

170 173

..........

5.2 Tungsten CVD .................................................................................................... 5.3 Tungsten CMP .................................................................................................... Section 6 : Low-lc Dielectric Process

157 159 163

.....................................................................

6.1 Deposit Low-k Dielectric Film ........................................................................... 6.2 Trench Photolithography and Etch ..................................................................... Section 7: Copper First Level Interconnection Process ......................................... 7.1 TdTaN Barrier Layer Deposition ....................................................................... 7.2 Sputter Copper (Cu) ............................................................................................

vii

174 176 177 177 180 183 183 185

Contents

7.3 Electroplate Copper (Cu) ......................................... ........................... 7.4 Copper CMP .......................................................................................................

........................... Section 1 : Introduction ....................................................................................... Section 2: Deposit Barrier Layer and lntermetal Dielectric ................................... Section 3: Dual Damascene Process ....................................................................

Chapter 8: Multilevel M e t a l Interconnects and Dual Damascene

3.1 Introduction ......................................................................................................... 3.2 Via Photo/Etch .................................................................................................... 3.3 Trench Photo/Etch ............................................................................................... 3.4 Deposit Barrier Layers ........................................................................................ 3.5 Sputter Copper .................................................................................................... 3.6 Electroplate Copper ............................................................................................ 3.7 CMP to Remove Excess Copper ......................................................................... 3.8 Deposit S i c Barrier Layer .................................................................................. 3.9 Build Additional Layers ......................................................................................

............................................................................ ....................................................................

Section 4: Form Bonding Pads Section 5: Final Passivation Process

185 186

i89 191 195 197

197 198 199 200 200 200 201 202 202 203 205

5.1 Deposit Final Passivation .................................................................................... 205 5.2 Photo/Etch for Bonding Pads .............................................................................. 205 Chapter 8: Test and Assembly

...........................................................................

....................................................................................... ......................................................................

Section 1 : Introduction Section 2: Wafer and Chip Testing

2.1 In-line Parametric Test ........................................................................................ 2.2 Wafer Sort (Probe) .............................................................................................. 2.3 Final Functional Test ...........................................................................................

.....................................................................

Section 3: Assembly and Packaging

3.1 Die Separation ..................................................................................................... 3.2 Die Attach and Bond Pad Connection ................................................................ 3.3 Encapsulation ......................................................................................................

207 209 211

211 212 213 215

215 216 218

........................................................................... Introduction ....................................................................................................... Section 1 : Atoms and Molecules .........................................................................

219

1.1 The Atom ............................................................................................................ 1.2 Molecules ............................................................................................................ 1.3 Organic Molecules ..............................................................................................

223 226 227

Appendix A: Science Overview

Section 2: Gases

.................................................................................................

2.1 Facts about Gases ................................................................................................ 2.2 Ions ...................................................................................................................... 2.3 Plasma ................................................................................................................. 2.4 Free Radicals .......................................................................................................

...

Vlll

221 223

229

229 230 230 231

Contents

2.5 Excited States ...................................................................................................... Section 3: Chemistry

...........................................................................................

...............................................................

3.3 Plasma Etch Chemistry ....................................................................................... Section 4: Solids

.................................................................................................

231 233

233 235 237

4.1 Conductors and Insulators . 4.2 Semiconductors .................. ........................................................................... 238 4.3 pn Junctions ........................................................................................................ 239

...............................................

241

5.1 Electric Charges and Fields 5.2 Electric Current ................................................................................................... 5.3 Magnetic Field ....................................................................................................

242 243

Section 5: Electricity, Electric and Magnetic Fields

Appendix B: Plasma Etch Supplement to Chapter 4 .............................................

......................................................................... .....................................................

Section 1 : Plasma Etcher Theory Section 2: Plasma Etch Process Requirements

Bibliography

....................................................................................................

Index ..............................................................................................................

245 247 249

251 253


&OREWORD

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)TISINTERESTINGTONOTETHATTHEEASEWITHWHICHASILICONDIOXIDElLMCANBE FORMEDONSILICON ASWELLASITSELECTRICALPROPERTIESANDSTABILITYWEREIMPORTANT FACTORSINTHERAPIDTRANSITIONFROMGERMANIUMTOSILICONINTHEEARLYYEARSOFTHE SEMICONDUCTORINDUSTRY/XIDEALSOHASOTHERADVANTAGEOUSPROPERTIESLIKETHEABILITY TOBLOCKTHEIMPLANTATIONOFDOPANTS WHICHWILLBEDISCUSSEDLATER 3ILICONDIOXIDEISACTUALLYAVERYFAMILIARSUBSTANCEITISTHEPRINCIPALCOMPO NENTOFGLASSANDSEVERALOTHERITEMSMENTIONEDINTHENEXTSIDEBAR"OTHhOXIDEvAND hGLASSvAREINDUSTRYSLANGTERMSFORSILICONDIOXIDE !NOTHER&AMILIAR%XAMPLE 3ANDISPERHAPSTHEMOSTFAMILIAREXAMPLEOFNATURALLYOCCURRINGSILICONDIOX IDE-UCHOFTHESANDINTHEWORLDISPRINCIPALLYCOMPOSEDOFSILICONDIOXIDE SOMEOFQUITEHIGHPURITY!NOTHERCOMMON NATURALLYOCCURRINGFORMOF3I/ ISQUARTZ ASINGLECRYSTALFORM!NIMPORTANTINDUSTRIALPRODUCTIShQUARTZ GLASS vSOMETIMESMADEBYMELTINGHIGHPURITYQUARTZCRYSTALSBUTALSOCAN BEPRODUCEDTODAYFROMMELTINGVERYHIGHPURITYSYNTHETICSILICONDIOXIDE 1UARTZGLASSISWIDELYUSEDINHIGHTEMPERATUREENVIRONMENTSINCLUDINGMANY APPLICATIONSINTHESEMICONDUCTORINDUSTRY4HETHERMALOXIDElLMGROWNON SILICONWAFERSISCHEMICALLYSIMILARTOQUARTZGLASS 3EVERALGEMSTONES SUCHASOPALANDAMETHYST AREALSOFORMSOFSILICONDIOX IDE#OMMONBOTTLEANDWINDOWGLASSESAREABOUTSILICONDIOXIDE

$IELECTRICMATERIALSARETHECOMPLEMENTTOCONDUCTINGMATERIALSTHATALLOWTHE CREATIONOFELECTRICALCOMPONENTSINTHECIRCUIT3EVERALDIELECTRICMATERIALSARENEEDED TOMAKECHIPSANDEACHWILLBEEXPLAINEDASITISENCOUNTERED

#HAPTER&ORMING7ELLS 4HECRITICALVALUEOFOXIDEISTHATITISAHARD STABLEDIELECTRIC3INCEELECTRICAL CIRCUITSAREBEINGBUILTONTHECHIP ITWILLCERTAINLYBENECESSARYTOSEPARATECONDUCT INGMATERIALSFROMEACHOTHERWITHANINSULATORTOAVOIDANELECTRICALSHORT2ECALLTHAT THECHIPISBUILTINLAYERS ANDINSULATINGLAYERSSEPARATECONDUCTINGLAYERSASREQUIRED BYANYELECTRICALCIRCUIT$IELECTRICSALSOFORMTHESEPARATINGMEDIUMBETWEENTHE PLATESOFACAPACITORANDPLAYACRITICALROLEINTHEFUNCTIONOFTHETRANSISTORSANDOTHER COMPONENTSONTHECHIP 4HEELECTRICALPROPERTIESOFOXIDEAREIMPORTANT BUTITHASOTHERUSESTOO)TMAY SERVEASANIMPLANTMASK BLOCKINGTHEPATHOFDOPANTPARTICLESTHATARESHOTATTHE WAFERINANIONIMPLANTERDISCUSSEDLATERINTHISCHAPTER !NOTHERIMPORTANTUSEISAS ANETCHMASK PROTECTINGPORTIONSOFAlLMFROMATTACKBYETCHANTCHEMICALS 7HATFUNCTIONISTHEOXIDECOATINGPERFORMINGATTHISPOINTINTHEPROCESS $ElNITION4HE!CTIVE!REAISTHEREGIONONTHESURFACEOFTHEWAFERWHERETHETRAN SISTORSTHEhACTIVEDEVICESvWILLBEBUILT)TMUSTBEKEPTASFREEASPOSSIBLE FROMCONTAMINATIONANDDAMAGE +EY0OINT4HEINITIALOXIDEISAPROTECTIVECOATING!LTHOUGHTHElLMCOVERSTHE WHOLECHIP THEFOCUSOFITSUSEISINTHEhACTIVEAREAv $ElNITION3ACRIlCIAL/XIDEISTHECOMMONNAMEFORATHERMALOXIDETHATWILLBE REMOVEDLATERINTHEPROCESS3ACRIlCIALOXIDESAREUSEDASPROTECTIVELAYERSOR OCCASIONALLYTOREMOVECONTAMINANTSFROMTHESILICONSURFACE4HEINITIALOXIDA TIONSTEPPRODUCESASACRIlCIALOXIDETHATISETCHEDOFFAFTERTHEWELLSHAVEBEEN FORMED 4HEINITIALOXIDEALSOINmUENCESTHEAMOUNTOFDOPANTENTERINGTHEWAFERFROM THEIMPLANTER4HETHICKNESSISCAREFULLYCONTROLLEDSOTHATTHEDEGREEOFSCREENINGIS PREDICTABLEANDUNIFORM !NOTHERIMPORTANTFUNCTIONOFTHEINITIALOXIDEISTOPREVENThKNOCK ONvOFSURFACE CONTAMINANTS ANEFFECTWHERETHEIMPACTINGIONSFROMTHEIMPLANTERPUSHUNWANTED IMPURITIESINTOTHESILICONCRYSTALWHERETHEYCANMOVEAROUNDANDDAMAGETHE TRANSISTORS 4HE)MPLANTER &OR CLARIlCATION IT SHOULD BE MENTIONED THAT THE IMPLANTER IS A PARTICLE ACCELERATORTHATSHOOTSCHARGEDPARTICLESATTHEWAFER DRIVINGTHEMINTOTHE SURFACE4HEDETAILSOFIMPLANTATIONWILLBEDISCUSSEDIN3ECTION

)NITIAL/XIDATION 4HE/XIDATION0ROCESS $ElNITION4HERMAL/XIDATIONOF3ILICONISTHEHIGHTEMPERATUREREACTIONOFTHE SILICONWAFERWITHOXYGEN WATERVAPOR ANDORNITROGENOXIDES4HISISUSUALLYTHE lRSTOPERATIONTOBEPERFORMEDONTHEWAFERSINTHEFAB 0URPOSE4OFORMTHERMALOXIDE SILICONDIOXIDEPRODUCEDBYDIRECTOXIDATIONOF SILICONATHIGHTEMPERATURE 0ROCESSGASESFLOW DOWNOVERWAFERS

&IGURE /XIDATION&URNACE 6ERTICAL4UBE&URNACE

%LECTRICALLY HEATEDFURNACE

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1UARTZ'LASS CHAMBER

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"ANKSOF HIGH INTENSITYLAMPS

$ISCUSSION 4HISOXIDEMAYHAVEOTHERNAMES SUCHASSACRIlCIALOXIDEORPADOXIDE ANDCANDO SEVERALTHINGS DEPENDINGUPONTHEPROCESS3OMEOFTHESPECIlCSWILLBEDISCUSSEDIN THISANDSUBSEQUENTSECTIONS

#HAPTER&ORMING7ELLS )NITIAL/XIDATION0ROCESS&LOW &URNACEOXIDATION )NSPECTION !WETCLEANPRECEDESMOSTlLMGROWTHSORDEPOSITIONSTEPS5SINGVARIOUS COMBINATIONSOFACIDS BASES OXIDIZERSAND$)WATER SURFACECONTAMINANTS AREREMOVED 4HETEMPERATUREISVERYHIGHDURINGTHEMAJORITYOFTHEOXIDATIONOROTHERlLM DEPOSITIONOPERATIONSUNWANTEDCHEMICALIMPURITIESCANMOVEAROUNDINTHE WAFERTOPOINTSWHERETHEYWOULDRUINMANYTRANSISTORS4HEPHENOMENONIS CALLEDDIFFUSION WHICHISTHEENERGETICVIBRATIONOFTHEATOMSINTHECRYSTALAS WELLASTHEEXPANDEDDIMENSIONSOFTHECRYSTALATHIGHTEMPERATURECREATEAN ENVIRONMENTWHERESTRAYATOMSWILLBEMOVEDAROUNDINTHECRYSTALLATTICE

$ISCUSSION 4HERMALOXIDATIONINATUBEFURNACEISDONEBYPLACINGTHEWAFERSINTHEFURNACEWHILE ITISmUSHEDWITHGAS OFTENNITROGEN TODISPLACETHEAIR4HENOXYGENORWATERVAPOR ISINTRODUCEDWHILEHEATINGTHEWAFERSTO TYPICALLY SOMEWHEREINTHERANGEOF# TO# DEPENDINGONTHEPROCESSREQUIREMENTS!FURNACEOXIDATIONREQUIRESTHAT THEWAFERSBEPLACEDINSPECIALTEMPERATURE RESISTANTHOLDERSCALLEDBOATS WHICHARE SLOWLYINSERTEDINTOTHEFURNACE"ATCHESOFORMOREWAFERSAREPROCESSEDATTHE SAMETIME4HEFURNACEISHEATEDBYELECTRICALRESISTANCEHEATERS4HESLOWHEATING ANDCOOLINGOFTHEWAFERSTEMPERATURERAMPING ISCRITICALTOTHEPROCESSTOAVOID THERMALSHOCKWHICHWOULDWARPTHEWAFERSANDDAMAGETHECRYSTALSTRUCTURE3OME PROCESSINGCYCLESAREQUITELONGANDOFTENWAFERSATOPPOSITEENDSOFTHEFURNACEDIS PLAYSOMEVARIATIONINlLMCHARACTERISTICS !NOTHERTYPEOFHIGHTEMPERATURETOOLISCALLEDARAPIDTHERMALPROCESSOR240 4HE240ISAhSINGLE WAFERvSYSTEM MEANINGTHATITPROCESSESONLYONEWAFERATA TIME4HEWAFERISRAPIDLYHEATEDWITHHIGH INTENSITYLAMPS4HEPROCESSGASES INTHIS CASEOXYGENORWATERVAPOR AREINTRODUCEDWHENTHEWAFERREACHESTHEPRESCRIBED TEMPERATURE!FTERTHElLMISGROWN THELAMPSAREEXTINGUISHEDANDTHEPROCESSGASES ARETURNEDOFF7ATER COOLEDWAFERPLATENSORAmOODOFNITROGENGASMAYBEUSEDTO HELPRAPIDLYCARRYHEATAWAYFROMTHEWAFER!TYPICAL240SYSTEMWILLHEATTHEWAFER TO#ANDCOOLITBACKDOWNTOROOMTEMPERATUREINLESSTHANONEMINUTE 4HEISSUEOFTHROUGHPUTISVERYIMPORTANTINTHEMANUFACTURINGENVIRONMENT !LARGENUMBEROFWAFERSMUSTBEPROCESSEDINAGIVENAMOUNTOFTIMEINORDERTO

)NITIAL/XIDATION MINIMIZECOSTS4HECOMPETITIONBETWEENBATCHPROCESSORSANDSINGLE WAFERPROCES SORSHASALWAYSBEENlERCE NOTONLYBECAUSEOFTHROUGHPUTBUTALSOTHEMANYOTHER IMPORTANTPROCESSSPECIlCATIONS!NINTERESTINGVARIETYOFBOTHOFTHESETYPESOF PROCESSOR ASWELLASSOMEINNOVATIVECROSS BREEDSTHATCOMBINEASPECTSOFBOTH ARE FOUNDINFABSTODAY 4HERMAL"UDGET 4HERMALBUDGETISTHETERMTHATREFERSTOTHEAMOUNTOFHEATENERGYTHATTHE WAFERWILLTOLERATEDURINGTHEENTIREPROCESS4HEDEVICESBEINGBUILTONTHE WAFERWILLNOTTOLERATEHIGHTEMPERATURESLATERINTHEPROCESS&OREXAMPLE WHENMETALISDEPOSITEDONTHEWAFERLATERINTHEPROCESSTHATMETALWILL DEFORMORREACTWITHITSSURROUNDINGMATERIALSATONLYAFEWHUNDREDDEGREES #ELSIUS4HERMALOXIDEISGROWNATABOUT##LEARLY ITWILLNOTBEPOS SIBLETOGROWANOXIDEONTHEWAFERAFTERMETALHASBEENDEPOSITEDWITHOUT RUININGTHEDEVICES4EMPERATURELIMITATIONSWILLBEPOINTEDOUTTHROUGHOUT OURDISCUSSION

)NSPECTION $URINGTHEINSPECTIONPHASEOFTHEPROCESS MEASUREMENTSAREMADETOSEETHATTHE lLMTHICKNESSISCORRECTACCORDINGTOTHEDESIGNSPECIlCATIONSFORTHECHIP4HETERM hINSPEC vISINDUSTRYSLANGFORAPROPERLYDONEPROCESSINGSTEP4HEDEPOSITIONSTEPS REQUIREVERYCLOSEADHERENCETOlLMTHICKNESSANDCROSS WAFERTHICKNESSUNIFORMITY SPECIlCATIONS !NEXAMPLEOFTHEINITIALOXIDETHICKNESSUSEDFORSOMESTATE OF THEART#-/3 DEVICESISNANOMETERS WHICHMAYALSOBEEXPRESSEDAS!NGSTROMS $ElNITION/NE!NGSTROMª ALSOCALLEDTHE!NGSTROMUNIT IS¾nMETERSIN LENGTHONETEN BILLIONTHOFAMETER ORONETEN THOUSANDTHOFAMICRON)TMAY ALSOBEEXPRESSEDASONETENTHOFANANOMETER2ECALLTHATANANOMETERIS¾n METERSORONEBILLIONTHOFAMETER 4HE!NGSTROM5NIT 4HE!NGSTROMUNITISNAMEDAFTER!NDERS*!NGSTRM A3WEDISHPHYSICIST !TlRSTGLANCE ITSEEMSTOBEACUMBERSOMEANDANNOYINGUNITOFMEASURE BECAUSEITISINCONSISTENTWITHTHESTANDARDIZEDUNITSOFMEASURE LIKETHE MICRONANDNANOMETER ALLOFWHICHARESPACEDTHREEORDERSOFMAGNITUDE APARTTHATIS THENEXTSMALLERUNITISTHOFTHELARGERONEDIVIDETHE MILLIMETERINTOPARTSANDEACHONEISAMICRONINLENGTH

#HAPTER&ORMING7ELLS (OWEVER THE!NGSTROMUNITHASSPECIALPHYSICALMEANINGTHERADIIOFALL ATOMSAREAPPROXIMATELYONEORTWO!NGSTROMUNITS!CCORDINGTOTHE3AR GENT 7ELSH0ERIODIC4ABLE THELARGESTATOMICRADIUSIS&RANCIUMATª THE SMALLESTIS.EONATª)TISESPECIALLYMEANINGFULFORCHIPMAKINGSINCE THElLMSDEPOSITEDONTHEWAFERAREEXTREMELYTHIN4HISFACTISILLUSTRATEDIN THEDISCUSSIONOFTHE'ATE$IELECTRIClLMFOUNDIN#HAPTER

)MPORTANT&ILM#HARACTERISTICS 4HICKNESS4HEEXACTOXIDElLMTHICKNESSISSPECIlEDSOTHATTHEIMPLANTATION SCREENINGEFFECTOFTHEOXIDEISCONSISTENTFROMWAFER TO WAFERANDBATCH TO BATCH WHILESTILLPROVIDINGENOUGHPROTECTIONTOTHEUNDERLYINGSILICON 5NIFORMITY4HEWAFERWILLHAVEMANYINDIVIDUALCHIPSONITANDTHEGOALIS FOREACHONETOOPERATEIDENTICALLY&ORTHATTOHAPPEN THECROSS WAFERlLM THICKNESSMUSTBEKEPTWITHINTIGHTLIMITS !STHEREADERMIGHTEXPECT ALARGENUMBEROFPRODUCTWAFERSISNOTCOMMIT TEDTOAPROCESSINGTOOLWITHOUTDOUBLE CHECKINGTHATITISWORKINGPROPERLY 4HESETESTSAREPERFORMEDONATIMETABLETHATVARIESFROMFAB TO FAB BUT MONITORINGTHETOOLSISANECESSITY3OMEOFTHECOMMONNAMESFORTHESE WAFERSARETESTWAFERS PILOTWAFERSORMONITORWAFERS)TISNOTNECESSARYFORTHIS DISCUSSIONTOINCLUDETHEPROCEDURESINVOLVEDWITHTHESEWAFERS3UFlCETOSAY THATTHEYAREPROCESSEDINTHESTANDARDMANNER INSPECTED MEASUREDANDIF ALLISWELL THENLARGEBATCHESOFPRODUCTARECOMMITTEDTOTHETOOL

3%#4)/.

0HOTOLITHOGRAPHY )NTRODUCTION $ElNITION,ITHOGRAPHYISAPRINTINGPROCESS $ElNITION0HOTOLITHOGRAPHYISAPRINTINGPROCESSTHATUSESPHOTOGRAPHICTECHNIQUES TOTRANSFERAPATTERNFROMAPHOTOMASKORRETICLETOACOATINGOFPHOTOSENSITIVE MATERIAL CALLEDPHOTORESIST ONTHEWAFERSURFACE $ElNITION0HOTORESISTRESIST ISALIGHT SENSITIVEPLASTICMATERIALTHATISDISSOLVEDIN ASOLVENTTOFORMASOLUTION4HERESISTISDISPENSEDONTOTHEWAFERINTHEFORMOF ALIQUID THENSTABILIZEDSOLIDIlED BYABAKINGSTEPTHATALSOAFFECTSTHEPHOTOSEN SITIVITYANDSOLUBILITYINDEVELOPERSOLUTIONASDESCRIBEDLATERINTHISSECTION-OST PHOTORESISTISSENSITIVETOULTRAVIOLETLIGHT +EY0OINT4HEPROCESSOFWAFERPATTERNINGISNOWUNDERWAY"EFOREGETTINGINTOTHE DETAILSOFTHEPATTERNINGPROCESS TAKEALOOKAT&IGURE

&IGURE 0ATTERNED7AFER

#HAPTER&ORMING7ELLS 4OTHENAKEDEYE THEPATTERNEDWAFERLOOKSLIKEABUNCHOFSMALLSQUARESOR RECTANGLES(OWEVER WHENLOOKINGUNDERMAGNIlCATION THEREALDETAILSBECOMEVIS IBLE4HEPATTERNTHATISTRANSFERREDTOTHEWAFERISFOUNDONTHERETICLE2ECALLTHATTHE RETICLEMAYHAVETHEPATTERNFORONEDIEORMANYDIE DEPENDINGONTHEIRSIZEANDTHE SIZEOFTHEEXPOSURElELDOFTHEIMAGINGTOOLSTEPPER 4HETERMShDIEvANDhCHIPv AREUSEDINTERCHANGEABLYTHROUGHOUTTHISDISCUSSION/NERETICLEISREQUIREDFOREACH LAYERTHATNEEDSAMASKFORIMPLANTINGORETCHING4HEPATTERNFORMOSTLAYERSAPPEARS TOBEANUNCOMPLICATEDSETOFSQUARES LINESANDRECTANGLESONTHERETICLE)TISIMPRES SIVETHATTHESESIMPLEBITSCOMBINETOMAKESUCHASOPHISTICATEDDEVICE $IEVS$ICE 4HE PLURAL OF hDIEv IS hDICEv SEE ANY DICTIONARY (OWEVER USAGE IN THE INDUSTRYHASEVOLVEDAWAYFROMUSEOFTHEPLURALFORMANDhDIEvISCOMMONLY USEDFORBOTHSINGULARANDPLURAL

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#OAT3PIN A 3URFACE0REPARATION I 6ACUUMDEHYDRATIONBAKE II (-$3HEXAMETHYLDISILAZANE APPLICATION B 3PINRESISTAPPLICATION C 3OFTBAKE

%XPOSE3TEP $EVELOP A !PPLYDEVELOPERSOLUTION B 0OST DEVELOPRINSE !FTER$EVELOP)NSPECTION!$)

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$ElNITION!N)MPLANT-ASKISAPATTERNCREATEDINPHOTORESISTOROTHERMASKING MATERIAL 0URPOSE!NIMPLANTMASKALLOWSTHEINTRODUCTIONOFDOPANTSFROMANIMPLANTERTO ENTERONLYTHESPECIlEDAREASOFTHEWAFER4HERESISTFORMSACOMPARATIVELY THICKLAYEROFPLASTICTHATABSORBSTHESPEEDINGIONSORNEUTRALSSOTHATTHEYARE UNABLETOREACHTHESURFACEOFTHESILICON $OPANTSAREUSEDTOCREATETHETRANSISTORSANDSOMEOFTHEELECTRICALCOMPONENTS OFTHECHIP4HEDOPANTSMUSTBEPLACEDPRECISELYINTHECORRECTAREASFORTHECOM PONENTSTOWORK

#HAPTER&ORMING7ELLS

#OAT3PIN 3URFACE0REPARATION 7HENTHEWAFERSARRIVEATPHOTOLITHOGRAPHYPHOTO THEYENTERALOWPRESSUREBAKE OVENANDARETREATEDTOAhSAUNAvOFHOT DRYNITROGENGASTODRIVEOFFANYMOISTURE 4HENHEXAMETHYLDISILAZANE(-$3 ISDISPENSEDINTOTHECHAMBERINVAPORFORM WHEREITCOATSTHEWAFERS4HE(-$3FORMSANIMPORTANThGLUELAYERvTHATENSURES THEPHOTORESISTWILLSTICKTOTHEWAFERS 3URFACEPREPARATIONISALWAYSAMAJORISSUEINCHIPMAKING7EWOULDBEINREAL TROUBLEIFTHELAYERSDIDNTSTICKTOEACHOTHER 2ESIST!PPLICATION 4HEPROCESSOFCOATINGTHETOPOFTHEWAFERWITHPHOTORESISTISSOMETIMESCALLEDSPIN SIMPLYBECAUSETHETOOLTHATPUTSONTHERESISTSPINSTHEWAFERAROUND4HETOOLHOLDS THEWAFERONASPINNINGVACUUMCHUCK4HERESISTISDISPENSEDONTOTHECENTEROF THEWAFERTHROUGHATUBEANDISIMMEDIATELYmUNGOFFSIDEWAYSBECAUSETHEWAFERIS SPINNINGATARATHERHIGHSPEED"ELIEVEITORNOT THATISTHEIDEA4HESPINSPEEDISTHE PRINCIPLEDETERMINANTOFTHETHICKNESSOFTHERESISTTHATISLEFTONTHEWAFERRESISTVIS COSITYISALSOANIMPORTANTTHICKNESSFACTORITISOFTENTHETHICKNESSOFPANCAKESYRUP ORENGINEOIL &IGURE SHOWSASPINNER

&IGURE 0HOTORESIST#OATER3PINNER

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0HOTOLITHOGRAPHY

%XPOSURE3TEP $ElNITION%XPOSUREISTHEPROCESSOFSHININGULTRAVIOLETLIGHTONTOTHEWAFER4HE WAFERISEXPOSEDTOULTRAVIOLETLIGHTJUSTASTHElLMINACAMERAISEXPOSEDTOVIS IBLELIGHT 4HESTEPPERISANINCREDIBLYSOPHISTICATEDDEVICE4HENAMEhSTEPPERvCOMESFROM THEWAYTHEMACHINEPERFORMSITSJOBOFEXPOSINGTHEWAFERTO56LIGHT!SQUARE ORRECTANGULARREGIONOFAFEWSQUARECENTIMETERSISEXPOSEDATATIME4HESTEPPER PHYSICALLYMOVESORhSTEPSvTHEWAFERINPREPARATIONFORTHENEXTEXPOSURE 7ATCHINGTHEMACHINEINACTIONISFUN4HEWAFERISPOSITIONEDFORTHElRST EXPOSURE THESHUTTEROPENSFORASECONDORLESS ALLOWINGTHE56LIGHTTOSHINEONTHE WAFER4HENTHEWAFERISSUDDENLYMOVEDASHORTDISTANCEFOLLOWEDBYANOTHERmASH OFLIGHT4HEPROCESSCONTINUES STEPBYSTEP BACKANDFORTHACROSSTHEWAFERUNTILTHE ENTIRESURFACEISEXPOSED4HERECANBEAHUNDREDORMORESTEPSNEEDEDTOEXPOSEAN ENTIREWAFER 7HATISTRULYAMAZINGABOUTTHESTEPPERISTHEEXTREMEPRECISIONWITHWHICHIT MOVESTHEWAFERFOREACHEXPOSURE2EMEMBERTHATEACHLAYERREQUIREDTOMAKEA CHIPMUSTBEPLACEDEXACTLYONTOPOFTHELASTLAYEROREVERYTHINGWILLBEJUMBLEDUP ANDTHEDEVICESWILLNOTWORK4HETOLERANCEFORALIGNMENTOFTHEWAFERISMEASURED INNANOMETERSFORTODAYSDEVICES REQUIRINGTHEUSEOFLASERSTODETERMINETHEPOSITION OFTHEVACUUMCHUCKASSEMBLYTHATHOLDSTHEWAFER )NMOREFAMILIARTERMS THESTEPPERPOSITIONSTHEWAFERWITHATOLERANCEOFCLOSER THANOFTHETHICKNESSOFAHAIR4HATSPRECISION 4HESTEPPERISESSENTIALLYTAKINGAPICTUREOFTHERETICLE4HElLMINWHICHTHE PICTUREWILLBEDEVELOPEDISTHEPHOTORESISTONTOPOFTHEWAFER

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#ROPPER 7ILLIAM( 'REAT0HYSICISTS4HE,IFEAND4IMESOF,EADING0HYSICISTS FROM'ALILEOTO(AWKING .EW9ORK /XFORD5NIVERSITY0RESS 3ZE 3- 0HYSICSOF3EMICONDUCTOR$EVICES 3ECOND%DITION *OHN7ILEY 3ONS (ALLIDAY $AVID 2OBERT2ESNICK AND*EARL7ALKER &UNDAMENTALSOF0HYSICS %XTENDED &IFTH%DITION *OHN7ILEY3ONS "ROWN 4HEODORE, AND(%UGENE,E-AY *R #HEMISTRYTHE#ENTRAL3CIENCE 0RENTICE (ALL )NC 4HE/XFORD!MERICAN$ICTIONARYAND,ANGUAGE'UIDE /XFORD5NIVERSITY0RESS 7OLF 3 -ICROCHIP-ANUFACTURING ,ATTICE0RESS 3ZE 3- 6,3)4ECHNOLOGY "ELL4ELEPHONE,ABORATORIES )NCORPORATED 'HANDHI 3ORAB+ 6,3)&ABRICATION0RINCIPLES 3ILICONAND'ALLIUM!RSENIDE *OHN7ILEYSONS )NC 3EMICONDUCTOR)NTEGRATED#IRCUIT&ABRICATION4ECHNIQUES &AIRCHILD #ORPORATION -ANOS $ENNIS- AND$ANIEL,&LAMM 0LASMA%TCHING!N)NTRODUCTION !CADEMIC0RESS )NC ,IEBERMAN -ICHAEL! AND!LLAN*,ICHTENBERG 0RINCIPLESOF0LASMA$IS CHARGESAND-ATERIALS0ROCESSING *OHN7ILEY3ONS )NC

"IBLIOGRAPHY #HAPMAN "RIAN 'LOW$ISCHARGE0ROCESSES 3PUTTERINGAND0LASMA%TCHING *OHN7ILEY3ONS )NC 2OSSNAGEL 3TEPHEN- *EROME*#UOMO AND7ILLIAM$7ESTWOOD (ANDBOOK OF0LASMA0ROCESSING4ECHNOLOGY &UNDAMENTALS %TCHING $EPOSITION AND3UR FACE)NTERACTIONS .OYES0UBLICATIONS (EYNES -ICHAEL AND!NNE+-ILLER )NTEGRATED#IRCUIT3YNOPSIS 4HIRD%DITION 3EMICONDUCTOR3ERVICES (EYNES -ICHAEL AND!NNE+-ILLER 3EMICONDUCTOR4ERMINOLOGYn'RAPHIC 'LOSSARYOF4ERMS &OURTH%DITION 3EMICONDUCTOR3ERVICES -AKINGTHE-ICROCHIP!TTHE,IMITS)))6IDEO4RAINING#OURSE 3EMICONDUCTOR 3ERVICES %VANS + !-ILLERAND06AN:ANT #LEANROOM4ECHNOLOGY-ANUAL 3ECOND %DITION 3EMICONDUCTOR3ERVICES 6AN:ANT 0ETER -ICROCHIP&ABRICATION &IFTH%DITION -C'RAW (ILL 'ISE 0ETER% "LANCHARD 2ICHARD 3EMICONDUCTORAND)NTEGRATED#IRCUIT&ABRI CATION4ECHNIQUES 2ESTON0UBLISHING#OMPANY )NC 6AN.OSTRANDS3CIENTIlC%NCYCLOPEDIA &IFTH%D ,ITTON%DUCATIONAL0UBLISH ING )NC #2$(ANDBOOKOF#HEMISTRYAND0HYSICS TH%D n #2#0RESS )NC 0LUMMER *AMES$ $EAL -ICHAEL$ 'RIFlN 0ETER" 3ILICON6,3)4ECHNOL OGY 0RENTICE(ALL )NC 4HE3EMICONDUCTOR0ICTURE$ICTIONARY $-$ATA )NC

)NDEX

3YMBOLS

#

($0 #6$

CHEMICALCOMPOUND CHEMICALMECHANICALPOLISHING#-0 CHEMICALVAPORDEPOSITION#6$ CHEMISTRY CLEANROOM #-/3DEVICES COMPLEMENTARYMETALOXIDESEMICONDUCTOR #-/3 COMPOUNDSEMICONDUCTORS COMPUTER AIDEDDESIGN#!$ CONTACTHOLE

! ACTIVATED ACTIVEAREA ADHESIONLAYER ADSORBED AFTERDEVELOPINSPECTION!$) !NGSTROM !NGSTROMUNIT ANNEAL SPIKE ANNEALING ASHING ASPECTRATIO ATOMICLAYERDEPOSITION!,$ AUTOMATEDMATERIALHANDLINGSYSTEMS!-(3

" BACK GRINDING BACK LAPPING BARRIERLAYER BINNING BIT BONDINGPADS BUNNYSUIT BYTE

$ DEIONIZEDWATER$)WATER DELAMINATEPEELOFF DEPLETIONREGION DESIGNENGINEER DESIGNRULES DESIGNRULECHECKS$2# DESIGNRULESETS DESIGNVERIlCATION DIE ATTACH DIE BONDING DIELECTRICS HIGH K LOW K DIFFUSION DOPANTS ACTIVATED

)NDEX N TYPE P TYPE DRYETCHING DUALDAMASCENE$$ DYNAMICRANDOMACCESSMEMORY$2!-

% EFmUENT ELECTRICCHARGE ELECTRICCURRENT ELECTRIClELD ELECTROCHEMICALDEPOSITION%#$ ELECTROMAGNET ELECTROMIGRATION ELECTRONICSGRADESILICON%'3 ELECTROPLATING ENCAPSULATION EPITAXIALSILICONEPI EXCITEDSTATE EXPOSURE EXPOSURElELD

& FABRICATIONAREA lELDEFFECTTRANSISTOR lNALTEST mIP CHIPBONDING mUID FOUNDRY FUNCTIONTEST

' GAS GATEDIELECTRIC GERMANIUM'E GETTER GLUELAYER

( HALOGENS HARDMASK HIGH KDIELECTRICS HIGH KGATEDIELECTRICS HIGHASPECTRATIOCONTACT(!2#

) )))n6SEMICONDUCTORS IMPLANTMASK INERTGASES INGOT INLINEPACKAGE INTEGRATEDCIRCUIT)# INTERLEVELDIELECTRIC),$ INTERMETALDIELECTRIC)-$ INVERSESQUARELAW INSPEC ISOTROPIC

* JUNCTION SPIKING

+ KISTHEDIELECTRICCONSTANT

, LATCH UP LAYOUTDESIGNER LAYOUTENGINEER LAYOUTVERSUSSCHEMATIC,63 LIGHTLYDOPEDDRAIN,$$ LIGHTEMITTINGDIODES,%$S LITHOGRAPHY LOGICENGINEER LOW KDIELECTRICS LOW KDIELECTRICMATERIALS LOWPRESSURE#6$,0#6$

MAGNETIClELD METALINTERCONNECTS METALOXIDESEMICONDUCTORlELDEFFECTTRANSISTOR -/3&%4 MICRON MICROPROCESSORS MIL SPEC MILITARYAPPLICATIONS MOLECULE MONITORWAFERS -OORES,AW

)NDEX .

2

N TYPE NATIVEOXIDE NEWPRODUCTPLAN.00 NOBLEGASES

RAPIDTHERMALPROCESSOR240 REACTANTS RECTIlER REENTRANTPROlLESUNDERCUTTING RESISTTRIMMING RETICLE

0 P TYPE PADOXIDE PARALLEL PLATECAPACITOR PARASITICCAPACITANCE PASSIVATION PELLICLES PHASE SHIFTMASK PHASE SHIFTMASKCHECK PHOTOLITHOGRAPHY PHOTOMASK PHOTORESISTRESIST RETICLE PHOTOMASKRETICLE PHOTORESISTRESIST PHOTORESISTASHING PURPOSE PHOTORESISTSTRIPPING PHYSICALVAPORDEPOSITION06$ PILOTWAFERS PLANARIZATION PLASMA PLASMAENHANCED#6$0%#6$ PLASMAETCH PLUG PNJUNCTION POLYCIDE POLYCRYSTALLINEPOLY POTENTIALDIFFERENCE PRE METALDIELECTRIC0-$ PROBE PRODUCTDElNITION PROTECTIVEPASSIVATION

1 QUARTZ QUARTZGLASS

3 SACRIlCIALOXIDE SALICIDE SCANNINGELECTRONMICROSCOPES3%- SCHEMATIC SCRIBELINE SCRUBBERS SELF ALIGNEDGATE SEMICONDUCTOR SHALLOWTRENCH SHALLOWTRENCHISOLATION34) SHEARINGSTRESS SIDEWALLPASSIVATION SILICA SILICIDES SILICON3I POLYCRYSTALLINEPOLY SINGLECRYSTAL SILICONDIOXIDE SILICONNITRIDENITRIDE SILICONONINSULATOR3/) SIMULATIONS SINGLECRYSTAL SOFTWAREENGINEERS SOLIDSTATEDEVICE SOURCEANDDRAIN SPACER SPECIlCATIONS SPIKEANNEAL SPIN ONDIELECTRIC3/$ SPIN ONGLASS3/' SPUTTERING STANDARDMECHANICALINTERFACE3-)& STATICRANDOMACCESSMEMORY32!- STEP AND REPEATREDUCTION PROJECTIONPRINTING STEP AND SCAN STEPPER

)NDEX STREET SUBSTRATE SURFACTANTS

4 TAPEOUT TAPEAUTOMATEDBONDING4!" TESTWAFERS THERMALBUDGET THERMALOXIDATIONOFSILICON THERMALOXIDE THROUGHPUT TRENCHETCH TRENCHlLLPROCESS

5 UNDERCUTTING

6 VERTICALLAMINARmOW6,& VIA

7 WAFERSORT WELL WELLDIFFUSION WELLDRIVE IN WETETCH

9 YELLOWROOM

%,3%6)%23#)%.#%#$ 2/-,)#%.3%!'2%%-%.4 0,%!3%2%!$4(%&/,,/7).'!'2%%-%.4#!2%&5,,9"%&/2%53).'4()3#$ 2/-02/$5#44()3#$ 2/- 02/$5#4)3,)#%.3%$5.$%24(%4%2-3#/.4!).%$).4()3#$ 2/-,)#%.3%!'2%%-%.4h!GREEMENTv "953).'4()3#$ 2/-02/$5#4 9/5 !.).$)6)$5!,/2%.4)49).#,5$).'%-0,/9%%3 !'%.43!.$ 2%02%3%.4!4)6%3h9OUvORh9OURv !#+./7,%$'%4(!49/5(!6%2%!$4()3!'2%%-%.4 4(!49/55. $%234!.$)4 !.$4(!49/5!'2%%4/"%"/5.$"94(%4%2-3!.$#/.$)4)/.3/&4()3!'2%%-%.4 %,3%6)%23#)%.#%).#h%LSEVIER3CIENCEv %802%33,9$/%3./4!'2%%4/,)#%.3%4()3#$ 2/-02/$5#44/ 9/55.,%339/5!33%.44/4()3!'2%%-%.4)&9/5$/./4!'2%%7)4(!.9/&4(%&/,,/7).'4%2-3 9/5-!9 7)4().4()249 $!93!&4%29/522%#%)04/&4()3#$ 2/-02/$5#42%452.4(%5.53%$ #$ 2/-02/$5#4!.$!,,!##/-0!.9).'$/#5-%.4!4)/.4/%,3%6)%23#)%.#%&/2!&5,,2%&5.$ $%&).)4)/.3 !SUSEDINTHIS!GREEMENT THESETERMSSHALLHAVETHEFOLLOWINGMEANINGS h0ROPRIETARY-ATERIALvMEANSTHEVALUABLEANDPROPRIETARYINFORMATIONCONTENTOFTHIS#$ 2/-0RODUCTINCLUDINGALLINDEXES ANDGRAPHICMATERIALSANDSOFTWAREUSEDTOACCESS INDEX SEARCHANDRETRIEVETHEINFORMATIONCONTENTFROMTHIS#$ 2/-0RODUCT DEVELOPEDORLICENSEDBY%LSEVIER3CIENCEANDORITSAFlLIATES SUPPLIERSANDLICENSORS h#$ 2/-0RODUCTvMEANSTHECOPYOFTHE0ROPRIETARY-ATERIALANDANYOTHERMATERIALDELIVEREDON#$ 2/-ANDANYOTHERHU MAN READABLEORMACHINE READABLEMATERIALSENCLOSEDWITHTHIS!GREEMENT INCLUDINGWITHOUTLIMITATIONDOCUMENTATIONRELATING TOTHESAME /7.%23()0 4HIS#$ 2/-0RODUCTHASBEENSUPPLIEDBYANDISPROPRIETARYTO%LSEVIER3CIENCEANDORITSAFlLIATES SUPPLIERSANDLICENSORS 4HECOPYRIGHTINTHE#$ 2/-0RODUCTBELONGSTO%LSEVIER3CIENCEANDORITSAFlLIATES SUPPLIERSANDLICENSORSANDISPROTECTEDBY THENATIONALANDSTATECOPYRIGHT TRADEMARK TRADESECRETANDOTHERINTELLECTUALPROPERTYLAWSOFTHE5NITED3TATESANDINTERNATIONAL TREATYPROVISIONS INCLUDINGWITHOUTLIMITATIONTHE5NIVERSAL#OPYRIGHT#ONVENTIONANDTHE"ERNE#OPYRIGHT#ONVENTION9OUHAVE NOOWNERSHIPRIGHTSINTHIS#$ 2/-0RODUCT%XCEPTASEXPRESSLYSETFORTHHEREIN NOPARTOFTHIS#$ 2/-0RODUCT INCLUDING WITHOUTLIMITATIONTHE0ROPRIETARY-ATERIAL MAYBEMODIlED COPIEDORDISTRIBUTEDINHARDCOPYORMACHINE READABLEFORMWITHOUT PRIORWRITTENCONSENTFROM%LSEVIER3CIENCE!LLRIGHTSNOTEXPRESSLYGRANTEDTO9OUHEREINAREEXPRESSLYRESERVED!NYOTHERUSEOF THIS#$ 2/-0RODUCTBYANYPERSONORENTITYISSTRICTLYPROHIBITEDANDAVIOLATIONOFTHIS!GREEMENT 3#/0%/&2)'(43,)#%.3%$0%2-)44%$53%3 %LSEVIER3CIENCEISGRANTINGTO9OUALIMITED NON EXCLUSIVE NON TRANSFERABLELICENSETOUSETHIS#$ 2/-0RODUCTINACCORDANCE WITHTHETERMSOFTHIS!GREEMENT9OUMAYUSEORPROVIDEACCESSTOTHIS#$ 2/-0RODUCTONASINGLECOMPUTERORTERMINALPHYSI CALLYLOCATEDAT9OURPREMISESANDINASECURENETWORKORMOVETHIS#$ 2/-0RODUCTTOANDUSEITONANOTHERSINGLECOMPUTEROR TERMINALATTHESAMELOCATIONFORPERSONALUSEONLY BUTUNDERNOCIRCUMSTANCESMAY9OUUSEORPROVIDEACCESSTOANYPARTORPARTS OFTHIS#$ 2/-0RODUCTONMORETHANONECOMPUTERORTERMINALSIMULTANEOUSLY 9OUSHALLNOTA COPY DOWNLOAD OROTHERWISEREPRODUCETHE#$ 2/-0RODUCTINANYMEDIUM INCLUDING WITHOUTLIMITATION ONLINE TRANSMISSIONS LOCALAREANETWORKS WIDEAREANETWORKS INTRANETS EXTRANETSANDTHE)NTERNET ORINANYWAY INWHOLEORINPART EXCEPTTHAT9OUMAYPRINTORDOWNLOADLIMITEDPORTIONSOFTHE0ROPRIETARY-ATERIALTHATARETHERESULTSOFDISCRETESEARCHESB ALTER MODIFY ORADAPTTHE#$ 2/-0RODUCT INCLUDINGBUTNOTLIMITEDTODECOMPILING DISASSEMBLING REVERSEENGINEERING ORCREATING DERIVATIVEWORKS WITHOUTTHEPRIORWRITTENAPPROVALOF%LSEVIER3CIENCEC SELL LICENSEOROTHERWISEDISTRIBUTETOTHIRDPARTIESTHE #$ 2/-0RODUCTORANYPARTORPARTSTHEREOFORD ALTER REMOVE OBSCUREOROBSTRUCTTHEDISPLAYOFANYCOPYRIGHT TRADEMARKOR OTHERPROPRIETARYNOTICEONORINTHE#$ 2/-0RODUCTORONANYPRINTOUTORDOWNLOADOFPORTIONSOFTHE0ROPRIETARY-ATERIALS 2%342)#4)/.3/.42!.3&%2 4HIS,ICENSEISPERSONALTO9OU ANDNEITHER9OURRIGHTSHEREUNDERNORTHETANGIBLEEMBODIMENTSOFTHIS#$ 2/-0RODUCT INCLUDING WITHOUTLIMITATIONTHE0ROPRIETARY-ATERIAL MAYBESOLD ASSIGNED TRANSFERREDORSUB LICENSEDTOANYOTHERPERSON INCLUDINGWITHOUT LIMITATIONBYOPERATIONOFLAW WITHOUTTHEPRIORWRITTENCONSENTOF%LSEVIER3CIENCE!NYPURPORTEDSALE ASSIGNMENT TRANSFEROR SUBLICENSEWITHOUTTHEPRIORWRITTENCONSENTOF%LSEVIER3CIENCEWILLBEVOIDANDWILLAUTOMATICALLYTERMINATETHE,ICENSEGRANTED HEREUNDER

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Demystifying Six Sigma: A Company-Wide Approach to Continuous Improvement

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Demystifying Embedded Systems Middleware

Demystifying Business Celebrity

Demystifying ATM ADSL

Demystifying Organizational Learning

Demystifying the IPsec Puzzle

Demystifying Switching Power Supplies

Demystifying Six Sigma

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Demystifying Globalization (Globalization & Governance)

Demystifying Switched-capacitor Circuits Newnes

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The Miracle Tree: Demystifying the Qabalah

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Inside the Kaisha: Demystifying Japanese Business Behavior

Demystifying Postgraduate Research: From MA to PhD

The Accidental Zillionaire: Demystifying Paul Allen

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