Analog Circuits and Signal Processing
Series Editors Mohammed Ismail Mohamad Sawan
For further volumes: http://www.springer.com/series/7381
Juan Pablo Alegre Pérez€•Â€Santiago Celma Pueyo Belén Calvo López
Automatic Gain Control Techniques and Architectures for RF Receivers
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Juan Pablo Alegre Pérez LSI Corporation Madrid Spain
[email protected] Belén Calvo López University of Zaragoza Zaragoza Spain
[email protected] Santiago Celma Pueyo University of Zaragoza Zaragoza Spain
[email protected] ISBN 978-1-4614-0166-7â•…â•…â•…â•… e-ISBN 978-1-4614-0167-4 DOI 10.1007/978-1-4614-0167-4 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2011933911 © Springer Science+Business Media, LLC 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
Preface
Receivers have been a basic block in telecommunication systems since the invention of the radio in the late 19th century, acquiring an essential role in what has been called the third Communication Revolution where information is transferred via controlled waves and electronic signals. Their main function is to recover the information from the transmitted wave and convert it to electronic signals that can be understood by the succeeding electronic processing signal systems. Since the Internet revolution, new receivers appeared to connect computers one to another or to the World Wide Web, such as wireless systems, have been gaining more and more popularity over the last few years. Thus, great investments in time, effort and money from both academia and industry have been made in the development of these receivers in order to achieve fully integrated solutions in form of ASICs meeting the demand for ever increasing high performance with low cost, low voltage supply, low power consumption and reduced surface area. The design of one of these receivers include different blocks such as filters, low noise amplifiers, gain controlled amplifiers, mixers and analog to digital converters. This book is precisely focused on the analysis and design of automatic gain control, AGC, circuits with wireless receivers as the main target application. In this context, the general function of the AGC circuitry is to automatically adjust the output signal of a variable gain amplifier to an optimal rated level, for different input signal strengths. This function is essential to guarantee that the system dynamic range is neither saturated with large signals nor makes the system fall below a tolerable noise level. Specifically, some wireless applications, such as WLAN or Bluetooth, must be able to handle packets-based data transmission and orthogonal frequency division multiplexing which introduce stringent settling-time constraints. Thus, fast AGCs are primordial in those systems. It is under these conditions that feedforward AGCs present their greatest advantages as an alternative to conventional feedback AGCs. Thus, all through this book we offer a detailed study about feedforward AGCs design—both at basic AGC cells and system level—, their main characteristics and performances.
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Preface
The starting point is a complete review and theoretical analysis of both feedforward and feedback configurations and their behavioural modelling, issues addressed in Chap.€2. Next, basic components in gain control function, i.e., variable/programmable gain amplifiers, peak detectors and control voltage generation circuits are examined. These basic blocks must be carefully chosen as they will limit the full AGC performance, so their specifications have to guarantee those required by the corresponding application. Thus, the main challenges and solutions encountered during the design of such high performance cells are summarized in Chap.€3 and different high performance integrated proposals that will be next employed in specific AGCs are described and characterized considering low voltage low power constraints. To achieve low power consumption and ease any future scale to shorter transistor channel length technologies, low voltage power supplies have been employed: this requires greater effort in the design, but guarantees the validity of the achieved results in current submicron process technologies. To close, the work is focused on the complete characterization of few different gain control loops required to implement a complete AGC system making use of some previously studied cells. Three complete AGC proposals are fully designed and evaluated in Chap.€4: a general purpose digital feedforward CMOS AGC operating at 100€MHz, a fully analogue feedforward AGC for an 802.11a WLAN receiver in SiGe BiCMOS technology and a combined feedforward/feedback CMOS AGC for operating frequencies up to 250€MHz. These novel AGC contributions, more than competitive with those already presented in the literature, prove that feedforward AGCs are a fine alternative in wireless receiver applications, evidencing that this class of circuits will take an important role in upcoming applications where the stringent time constraints preclude the use of conventional closed-loop AGCs.
Contents
1╅Introduction ����������������������������������尓������������������������������������尓������������������������� ╇╅ 1 1.1╅AGC Design Strategies ����������������������������������尓������������������������������������尓 ╇╅ 3 1.2╅AGC Architectures for RF Receivers ����������������������������������尓��������������� ╇╅ 6 1.3╅Outline of the Work ����������������������������������尓������������������������������������尓������ ╇╅ 8 References ����������������������������������尓������������������������������������尓����������������������������� ╅ 10 2╅AGC Fundamentals ����������������������������������尓������������������������������������尓������������ ╅ 2.1╅AGC Loop Fundamentals ����������������������������������尓��������������������������������� ╅ 2.1.1╅AGC with Feedback Loop ����������������������������������尓�������������������� ╅ 2.1.2╅AGC with Feedforward Loop ����������������������������������尓��������������� ╅ 2.2╅Matlab Simulations ����������������������������������尓������������������������������������尓������ ╅ 2.2.1╅AGC with Feedback Loop ����������������������������������尓�������������������� ╅ 2.2.2╅AGC with Feedforward Loop ����������������������������������尓��������������� ╅ 2.3╅Conclusions ����������������������������������尓������������������������������������尓������������������ ╅ References ����������������������������������尓������������������������������������尓����������������������������� ╅
13 14 14 20 21 21 25 26 27
3╅Basic AGC Cells ����������������������������������尓������������������������������������尓������������������ ╅ 3.1╅Variable Gain Amplifiers ����������������������������������尓���������������������������������� ╅ 3.1.1╅Degeneration Based VGA Structures. Proposed VGA1 ��������� ╅ 3.1.2╅Multiplier-Based VGA Structures. Proposed VGA2 and VGA3 ����������������������������������尓������������������������������������尓��������� ╅ 3.1.3╅Complete VGA Architecture Design Considerations ������������� ╅ 3.1.4╅Conclusions ����������������������������������尓������������������������������������尓������ ╅ 3.2╅Peak Detectors ����������������������������������尓������������������������������������尓�������������� ╅ 3.2.1╅Basic Peak Detector Topologies ����������������������������������尓����������� ╅ 3.2.2╅Open-Loop Envelope Detectors. Proposed PD1 and PD2 ����������������������������������尓������������������������������������尓������������ ╅ 3.2.3╅Closed-Loop Envelope Detectors. Proposed PD3 and PD4 ����������������������������������尓������������������������������������尓������������ ╅ 3.2.4╅S/H Based Envelope Detector. Proposed PD5 ����������������������� ╅ 3.2.5╅Conclusions ����������������������������������尓������������������������������������尓������ ╅
29 29 32 35 51 52 54 55 57 66 70 76
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3.3╅Control Voltage Generation Circuit ����������������������������������尓���������������� ╇╅ 3.3.1╅Digital Control ����������������������������������尓������������������������������������尓 ╇╅ 3.3.2╅Analog Control ����������������������������������尓����������������������������������� ╇╅ 3.3.3╅Conclusions ����������������������������������尓������������������������������������尓���� ╇╅ References ����������������������������������尓������������������������������������尓��������������������������� ╇╅
78 78 79 82 82
4╅AGC Systems ����������������������������������尓������������������������������������尓��������������������� ╇╅ 87 4.1╅CMOS Feedforward Digital AGC Circuit ����������������������������������尓������ ╇╅ 87 4.1.1╅System Architecture ����������������������������������尓���������������������������� ╇╅ 88 4.1.2╅Performances ����������������������������������尓������������������������������������尓�� ╇╅ 91 4.2╅SiGe BiCMOS Analog AGC Circuit ����������������������������������尓�������������� ╇╅ 93 4.2.1╅System Architecture ����������������������������������尓���������������������������� ╇╅ 94 4.2.2╅Performances ����������������������������������尓������������������������������������尓�� ╇╅ 98 4.3╅CMOS Mixed Feedback/Feedforward AGC Circuit ������������������������ ╅ 101 4.3.1╅System Architecture ����������������������������������尓���������������������������� ╅ 102 4.3.2╅Performances ����������������������������������尓������������������������������������尓�� ╅ 109 4.4╅Conclusions ����������������������������������尓������������������������������������尓���������������� ╅ 112 References ����������������������������������尓������������������������������������尓��������������������������� ╅ 114 5╅Conclusions ����������������������������������尓������������������������������������尓������������������������ ╅ 117 5.1╅General Conclusions ����������������������������������尓������������������������������������尓�� ╅ 117 5.2╅Further Research Directions ����������������������������������尓��������������������������� ╅ 119 Appendix A: Layout and Experimental Techniques ����������������������������������尓 ╅ 121 Appendix B: Acronym List����������������������������������尓������������������������������������尓����� ╅ 127 Appendix C: Parameter Glossary����������������������������������尓������������������������������ ╅ 129 Appendix D: Process Parameters����������������������������������尓������������������������������� ╅ 131 Index ����������������������������������尓������������������������������������尓������������������������������������尓����� ╅ 133
List of Tables
Table 2.1↜渀̀ Summary of main AGC loop control characteristics������������������� â•… 14 Table 3.1↜渀̀ Summary of VGA1 performances����������������������������������尓�������������� â•… 35 Table 3.2↜渀̀ VGA2 transistors sizes����������������������������������尓������������������������������� â•… 41 Table 3.3↜渀̀ Simulation and measurement data of the VGA2�������������������������� â•… 44 Table 3.4↜渀̀ VGA3 transistor sizes����������������������������������尓��������������������������������� â•… 48 Table 3.5↜渀̀ Comparison of several VGAs����������������������������������尓��������������������� â•… 53 Table 3.6↜渀̀ PD1 devices sizes����������������������������������尓������������������������������������尓��� â•… 59 Table 3.7↜渀̀ Comparison of principal characteristics for simulation and measurements of the open-loop peak detector���������������������� â•… 61 Table 3.8↜渀̀ Comparison summary between PD1 and PD2 for 10 MHz��������� â•… 65 Table 3.9↜渀̀ PD5 transistor sizes����������������������������������尓������������������������������������尓 â•… 75 Table 3.10↜渀 Comparison of proposed envelope detectors������������������������������� â•… 77 Table 4.1↜渀̀ Comparison of literature and proposed AGCs����������������������������� ╇ 113 Table D.1↜渀̀ T echnology: AMS 0.35€μm CMOS P-Substrate, N-Well, 4-Metal, 2-Poly����������������������������������尓���������������������������� ╇ 131 Table D.2↜渀 Technology: IHP 0.25€μm SiGe:C BiCMOS with High-Voltage Devices, 5-metal����������������������������������尓������������������ ╇ 132
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List of Figures
Fig. 1.1↜渀̀ Estimated wireless subscribers from 1985 to 2009��������������������������� ╅ 2 Fig. 1.2↜渀̀ WLAN and Bluetooth receiver block diagram��������������������������������� ╅ 2 Fig. 1.3↜渀̀ Feedback (↜left) and feedforward (↜rigth) AGC architectures������������� ╅ 4 Fig. 1.4↜渀̀ IF strip example����������������������������������尓������������������������������������尓����������� ╅ 6 Fig. 1.5↜渀̀ OFDM preamble symbols transient response����������������������������������尓� ╅ 7 Fig. 1.6↜渀̀ Feedback closed-loop AGC block diagram����������������������������������尓����� ╅ 7 Fig. 1.7↜渀̀ Feedback open-loop AGC block diagram����������������������������������尓������� ╅ 8 Fig. 2.1↜渀̕܀ȕSimplified block diagrams of feedback (a) and feedforward (b) AGCs����������������������������������尓������������������������ ╇ 14 Fig. 2.2↜渀̀ Common block diagram of feedback AGC����������������������������������尓����� ╇ 15 Fig. 2.3↜渀̀ Model of generalized feedback AGC����������������������������������尓�������������� ╇ 16 Fig. 2.4↜渀̀ Equivalent AGC loop diagram����������������������������������尓������������������������ ╇ 19 Fig. 2.5↜渀̀ Common block diagram of feedforward AGC����������������������������������尓 ╇ 21 Fig. 2.6↜渀̀ AGC1: Simulink model����������������������������������尓����������������������������������� ╇ 22 Fig. 2.7↜渀̀ Convergence response of AGC1 for different stepwise changes������ ╇ 22 Fig. 2.8↜渀̀ AGC2: Simulink model����������������������������������尓����������������������������������� ╇ 23 Fig. 2.9↜渀̀ Convergence response of AGC2 for different stepwise changes������ ╇ 23 Fig. 2.10↜渀 AGC3: Simulink model����������������������������������尓����������������������������������� ╇ 24 Fig. 2.11↜渀̕Settling-time versus reference voltage for different input signal steps����������������������������������尓������������������������������������尓��������� ╇ 24 Fig. 2.12↜渀 AGC4: Simulink model����������������������������������尓����������������������������������� ╇ 25 Fig. 2.13↜渀 Convergence response of AGC4 for different stepwise changes������ ╇ 26 Fig. 2.14↜渀 AGC5: Simulink model����������������������������������尓����������������������������������� ╇ 26 Fig. 2.15↜渀 Convergence response of AGC5 for a stepwise change�������������������� ╇ 27 Fig. 3.1↜渀̀ȕa Programmable resistor and fixed gain amplifier based PGA and b high gain amplifier with resistor network feedback based PGA����������������������������������尓������������������������� ╇ 31 Fig. 3.2↜渀̀ Differential pair transconductor with degenerative resistor�������������� ╇ 32 Fig. 3.3↜渀̀ Schematic view of the PGA proposed in [10]����������������������������������尓� ╇ 34 Fig. 3.4↜渀̀ PGA frequency response����������������������������������尓��������������������������������� ╇ 36 Fig. 3.5↜渀̕܀ȕTHD levels at 10€MHz for all gain settings versus output voltage Vout����������������������������������尓�������������������������������� ╇ 36 xi
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List of Figures
Fig. 3.6↜渀̀ a Conceptual multiplier scheme. b Gilbert cell�������������������������������� ╇ 38 Fig. 3.7↜渀̀ Multiplier cell proposed in [14]����������������������������������尓���������������������� ╇ 39 Fig. 3.8↜渀̀ Complete scheme of the proposed VGA����������������������������������尓��������� ╇ 40 Fig. 3.9↜渀̀ VGA2 chip photograph (a) and measurement setup (b)������������������� ╇ 42 Fig. 3.10↜渀̕VGA gain frequency response: simulated (dashed) and measured (↜solid)����������������������������������尓������������������������������������尓��� ╇ 43 Fig. 3.11↜渀̕IM3 levels versus peak-to-peak differential input voltage (Vp-p) at 50€MHz for different gain settings����������������������������������尓���� ╇ 43 Fig. 3.12↜渀 VGA IM3 versus frequencies at 0.4 and 0.8 Vp-p output������������������� ╇ 43 Fig. 3.13↜渀 Measured HD3 for different gain settings at 100€kHz���������������������� ╇ 44 Fig. 3.14↜渀 Classical CMOS pseudo-differential transconductor������������������������ ╇ 45 Fig. 3.15↜渀̕CMOS pseudo-differential transconductor: a Core of the proposed topology and b Output DC current for different Vdâ•› = â•›VGâ•›−â•›VCM values����������������������������������尓������������������� ╇ 46 Fig. 3.16↜渀̕Proposed CMOS pseudo-differential VGA with 3-bit rough gain adjustment, CMFF (a) and selfbias common-mode feedback loop (b)����������������������������������尓������������������������������������尓�������� ╇ 47 Fig. 3.17↜渀 VGA cell photograph����������������������������������尓������������������������������������尓�� ╇ 49 Fig. 3.18↜渀̕Simulated (↜dashed) and measured (↜solid) VGA frequency response for different gain settings����������������������������������尓����������������� ╇ 50 Fig. 3.19↜渀̕PGA plus buffer simulated (↜black) and experimental (↜grey) IM3 for outputs signals of 0.4 and 0.8€Vp-p at 100€MHz������������������� ╇ 50 Fig. 3.20↜渀 Typical multiple cell VGA AGC structure����������������������������������尓������ ╇ 51 Fig. 3.21↜渀 Rough/fine gain based VGA structure����������������������������������尓������������ ╇ 52 Fig. 3.22↜渀̕Ideal charge/discharge behaviour in a peak detector with load capacitor, C, and resistor, R����������������������������������������������� ╇ 54 Fig. 3.23↜渀 Diode-RC peak detector topology����������������������������������尓������������������� ╇ 55 Fig. 3.24↜渀 Op-amp plus diode based peak detector topology���������������������������� ╇ 56 Fig. 3.25↜渀 Op-amp plus source follower based peak detector topology������������ ╇ 56 Fig. 3.26↜渀 Open-loop peak detector topology����������������������������������尓������������������ ╇ 57 Fig. 3.27↜渀 Schematic diagram of the full-wave precision rectifier block���������� ╇ 58 Fig. 3.28↜渀 Schematic diagram of the mirrored cascode OTA���������������������������� ╇ 58 Fig. 3.29↜渀 Schematic diagram of the peak detector block��������������������������������� ╇ 59 Fig. 3.30↜渀 Chip photograph of the peak detector PD1����������������������������������尓����� ╇ 60 Fig. 3.31↜渀 Measured and ideal linearity performance����������������������������������尓������ ╇ 60 Fig. 3.32↜渀̕Measured tracking (↜solid grey line) of the open-loop envelope detectors for a 500€kHz square signal (↜solid black line) and simulation results (↜dashed grey line) for a 71€MHz sinusoidal signal with a stepwise change (↜dashed black line)����������������������������������尓������������������������������������尓������ ╇ 60 Fig. 3.33↜渀 Fast-settling open-loop envelope detector block diagram���������������� ╇ 62 Fig. 3.34↜渀 Schematic of the peak hold block����������������������������������尓������������������� ╇ 62 Fig. 3.35↜渀̕Envelope detector operation. Peak holder both output signals (↜grey and black) and input signal (--) (↜up). Below VC1 control signal����������������������������������尓������������������������������������尓��������������� ╇ 63
List of Figures
xiii
Fig. 3.36↜渀 Schematic diagram of the control path����������������������������������尓������������ ╇ 63 Fig. 3.37↜渀̕Ripple of the conventional (--) and the proposed (―) envelope detectors for an input voltage of 300€mV at 10€MHz and a total capacitance of 3.2€pF����������������������������������尓��������������������� ╇ 64 Fig. 3.38↜渀̕Tracking of (--) ideal, (-.) conventional and (―) proposed envelope detectors for a step signal at 10€MHz and ripple of 1%����� ╇ 65 Fig. 3.39↜渀̕DC (o) and 10€MHz (-) transfer characteristic for the conventional and the proposed envelope detector����������������� ╇ 65 Fig. 3.40↜渀 OTA plus current mirror closed-loop topology��������������������������������� ╇ 66 Fig. 3.41↜渀 Schematic of a high-Gm OTA/current mirror based peak detector���� ╇ 67 Fig. 3.42↜渀 Peak detector input-output performance����������������������������������尓��������� ╇ 68 Fig. 3.43↜渀̕Peak detector convergence performance for an input sinusoidal 100€MHz stepwise signal����������������������������������尓�������������������������������� ╇ 68 Fig. 3.44↜渀 Schematic of the fast-settling OTA/current mirror PD��������������������� ╇ 69 Fig. 3.45↜渀 Chip photograph����������������������������������尓������������������������������������尓���������� ╇ 70 Fig. 3.46↜渀 Measured and ideal input-output performance��������������������������������� ╇ 70 Fig. 3.47↜渀̕Simulated (↜up) and measured (↜down) convergence performance with a 20€MHz input sinusoidal signal modulated by a 400€kHz square signal����������������������������������尓����������������������������� ╇ 71 Fig. 3.48↜渀 S/H based detector conceptual scheme����������������������������������尓����������� ╇ 72 Fig. 3.49↜渀 Schematic of the control block����������������������������������尓������������������������ ╇ 72 Fig. 3.50↜渀 Schematic diagram of the peak holder����������������������������������尓������������ ╇ 73 Fig. 3.51↜渀 Schematic diagram of the telescopic OTA����������������������������������尓������ ╇ 73 Fig. 3.52↜渀̕Tracking of ideal (–), conventional (-.) and proposed (–) envelope detectors for a step signal at 10€MHz and ripple of 1%����� ╇ 75 Fig. 3.53↜渀 Envelope detection of a frequency modulated input signal�������������� ╇ 76 Fig. 3.54↜渀̕10€MHz input output performance for different envelope detectors����������������������������������尓������������������������������������尓������� ╇ 76 Fig. 3.55↜渀 Comparator bank cell employed in [57]����������������������������������尓���������� ╇ 79 Fig. 3.56↜渀 Piece-wise linear approximation based logarithmic amplifier���������� ╇ 81 Fig. 3.57↜渀 Circuit to implement inverse of exponential function����������������������� ╇ 81 Fig. 3.58↜渀 Simple divider����������������������������������尓������������������������������������尓������������� ╇ 82 Fig. 4.1↜渀̀ IF 71€MHz strip����������������������������������尓������������������������������������尓����������� ╇ 88 Fig. 4.2↜渀̀ Programmable gain amplifier cell����������������������������������尓������������������� ╇ 89 Fig. 4.3↜渀̀ Comparator bank cell����������������������������������尓������������������������������������尓�� ╇ 90 Fig. 4.4↜渀̀ AGC1 chip photograph����������������������������������尓����������������������������������� ╇ 91 Fig. 4.5↜渀̀ȕMeasured PGA frequency response: solid line, Kâ•› = â•›1; dashed line, Kâ•› = â•›1.5����������������������������������尓������������������������������������尓����������������� ╇ 92 Fig. 4.6↜渀̕܀ȕSimulated THD levels at 71€MHz for the main gain settings versus output voltage Vout����������������������������������尓�������������������������������� ╇ 92 Fig. 4.7↜渀̀ Measured input-output linearity of the peak detector����������������������� ╇ 93 Fig. 4.8↜渀̕܀ȕMeasured peak detector convergence response for a 21 dB abrupt stepwise change����������������������������������尓������������������������������ ╇ 93 Fig. 4.9↜渀̀ Simulated worst case AGC output����������������������������������尓������������������ ╇ 94
xiv
List of Figures
Fig. 4.10↜渀 Complete AGC architecture����������������������������������尓�������������������������� â•… 95 Fig. 4.11↜渀 Schematic of the peak detector����������������������������������尓���������������������� â•… 98 Fig. 4.12↜渀 Die photo of the full AGC����������������������������������尓����������������������������� â•… 99 Fig. 4.13↜渀 Measurement test-bench PCB����������������������������������尓����������������������� â•… 99 Fig. 4.14↜渀̕Frequency response of the full VGA for several VC with fixed amplifiers VGA1 and VGA2 switched off (↜black) and for VCâ•› = â•›120€mV with VGA1 “on” (↜grey). Results are the mean value of 100 measurements����������������������������������尓����� ╇ 100 Fig. 4.15↜渀 Input-output linearity for the peak detector����������������������������������尓�� ╇ 100 Fig. 4.16↜渀 Control voltage (↜VC,diffâ•›) versus peak detector output Vpd���������������� ╇ 100 Fig. 4.17↜渀̕Measured peak detector settling-time with a 20€MHz sinusoidal wave modulated with a 400€kHz square signal�������������� ╇ 101 Fig. 4.18↜渀̕Simulated AGC output signal, Vout, with an OFDM input signal for highest gain adjustment (18€dB) from lowest input level����������������������������������尓������������������������������������尓������������������ ╇ 101 Fig. 4.19↜渀 AGC3 system schematic (↜down) and VGA3 (↜up)��������������������������� ╇ 104 Fig. 4.20↜渀 Block schematic of feedforward loop����������������������������������尓����������� ╇ 105 Fig. 4.21↜渀 Inverter based comparator schematic����������������������������������尓������������ ╇ 106 Fig. 4.22↜渀 Peak detector schematic����������������������������������尓�������������������������������� ╇ 107 Fig. 4.23↜渀 Peak detector comparator����������������������������������尓������������������������������ ╇ 107 Fig. 4.24↜渀̕Equation€(4.7) for arbitrary constants and fitting curve obtained by Matlab Curve Fitting Toolbox����������������������������������尓��� ╇ 108 Fig. 4.25↜渀 Chip photograph����������������������������������尓������������������������������������尓�������� ╇ 109 Fig. 4.26↜渀 Measurement test circuitry����������������������������������尓���������������������������� ╇ 109 Fig. 4.27↜渀 Gain vs. input amplitude for an input signal at 100€MHz��������������� ╇ 110 Fig. 4.28↜渀̕AGC convergence with a square modulation at 300€KHz and a carrier at 250€MHz for simulation (↜up) and 20€MHz for measurements (↜down) are offered����������������������������������尓����������� ╇ 111 Fig. A.1↜渀 Measurement scheme����������������������������������尓������������������������������������尓 ╇ 123 Fig. A.2â•… CMOS test-buffer schematic����������������������������������尓������������������������� ╇ 124 Fig. A.3â•… Test buffer chip photograph����������������������������������尓��������������������������� ╇ 124 Fig. A.4↜渀 PCBs for each chip����������������������������������尓������������������������������������尓���� ╇ 125
Chapter 1
Introduction
Receivers have been a basic block in telecommunication systems since the invention of the radio in the late nineteenth century, acquiring an essential role in what has been called the third Communication Revolution where information is transferred via controlled waves and electronic signals. Their main function is to recover the information from the transmitted wave and convert it to electronic signals that can be understood by the succeeding electronic processing signal systems. Following the Internet revolution which started in 1980s, new systems appeared designed either to connect computers one to another or to the World Wide Web. Among those new communication systems, wireless systems, such as wireless local area network (WLAN) and Bluetooth, have been gaining more and more popularity over the last few years. Figure€1.1 shows estimated wireless subscribers between 2006 and 2009. Thus, great investments in time, effort and money from both academia and industry have been made in the development of these receivers in order to achieve fully integrated systems meeting the demand for ever increasing high performance with low cost, low power consumption and reduced surface area. The design of one of these receivers is usually carried out by several specialists, as it is made up of different blocks such as filters, low noise amplifiers (LNA), gain controlled amplifiers, mixers and analog to digital converters (ADC), see Fig.€1.2. This book is precisely focused on the analysis and design of automatic gain control (AGC) circuits. Although the designed AGCs could serve other applications, the main target applications are wireless receivers. Therefore, the proposed AGCs must be able to handle a packets-based data transmission, orthogonal frequency division multiplexing (OFDM) and stringent settling-time constraints [1]. For the last two decades the expansion of ASICs (Application Specific Integrated Circuits) among many electronic applications has been spectacular. Wireless receivers are not an exception to this tendency. The main advantages of integrating mixed digital/analog functions into the same chip are the full system area reduction, improved operating speed, parasitic and contacts failure reduction, higher versatility of the design and reduced cost, etc. In the design of digital circuits, which make up over 90% of the whole electronic system, CMOS technology is very superior to the other technologies such as bipolar due to its lower power consumption, high performance, higher integration density J. P. Alegre Pérez et al., Automatic Gain Control, Analog Circuits and Signal Processing, DOI 10.1007/978-1-4614-0167-4_1, ©Â€Springer Science+Business Media, LLC 2011
1
1â•… Introduction
2
(VWLPDWHG:LUHOHVV6XEVFULEHUV
1XPEHURIVXEVFULEHUV
â•›21
PD5 CMOS 0.35€µm 3.3 2.98 + 1.37a 1â•›∼â•›10 Yes 3.3 0.4 0.3% 42
PD4 SiGe BiCMOS 2.5 0.55 0.3â•›∼â•›20 Yes 3.5 1 – >â•›20
3.2â•…Peak Detectors 77
78
3â•… Basic AGC Cells
for wireless LAN applications as will be shown in Chap.€4 for some of them. A wide range of performance frequencies has been considered, from 0.3 to 100€MHz. High linearity detectors have also been obtained, always above 20€dB, which is appropriate for feedforward AGC configuration. Moreover, new fast-settling configurations have been presented, which achieve very low release time and ripple at the same time, so a theoretical trade-off of these circuits has been overcome. Finally, the validity of one of the proposed topologies in a SiGe BiCMOS technology has been verified, so the range of applications has been extended to this technology market.
3.3╅Control Voltage Generation Circuit The control voltage generator must take the output signal from the peak detector and after comparing it with a reference signal, generate the control signal VC required to adjust the gain in the VGA. The way it was explained in Sect.€2.1, multiple choices exist to generate this control signal. Furthermore, feedforward and feedback AGCs require different solutions, the feedback loop being more restrictive in the VC generation function required, while in the feedforward loop, accuracy is mandatory. Therefore, the main objective of this circuit is to generate a signal function of a reference voltage VREF and the input (or output) amplitude, depending on which loop topology is employed), such as
VC = f (AI N/OU T , VREF ),
so
AOU T = g(AI N , VC ) = g(AI N , f (AI N/OU T , VREF )) ≈ constant,
(3.29) (3.30)
where f and g functions correspond to the VC generator block and VGA block respectively. As indicated in (3.29) and (3.30), functions f and g are correlated and thus, a different solution, f, will be required for each different VGA function g, so AOUT is constant. In this section, first, two main groups will be differentiated, namely digital and analog VC generators corresponding each one to one of the VGA main topologies: (i) programmable gain amplifiers and (ii) continuously variable gain amplifiers. In both digital and analog subsections, different solutions will be offered.
3.3.1 Digital Control Digital control approach groups mainly two options. First topology is that where the AGC loop is fully implemented inside the DSP [54]. This option requires a different type of work completely oriented to digital designers, so it will not be gone into here as we understand it is beyond the aims of this book. The second option,
3.3╅Control Voltage Generation Circuit Fig. 3.55↜渀 Comparator bank cell employed in [57]
79 Vref +VCM
Vpeak
+ Comp
a0
¯ + Comp
a1
¯ + Comp
a2
¯
VCM
however, takes the output of the peak detector and, making use of a simple digital block, generates the digital word required to manage the PGA [55]. Thus, the latter option inside mixed-signal design is considered in this book. Many different digital solutions are available to control more or less efficiently the PGA gain. However, usually PGAs of 10–20€dB gain range per stage are enough in wireless applications and 2–3€dB gain steps are also acceptable. Therefore, the most common solution is a simple comparator bank ADC [56, 57], as shown in Fig.€3.55.
3.3.2 Analog Control Analog control is much more complicated to implement than digital. However, some applications require smooth gain variation and thus, analog solutions can provide the key. The main solutions are those analytically presented in Sect.€2.1. Since, for each VGA case employed a different analog control is required and it is not possible to offer an implementation of all the possibilities in this work. However, several solutions will be considered which could fit the VGAs presented in Sect.€3.1. Then, the generalization will be analytically explained in Sect.€2.1. VGA1 is fully programmable and in spite of it being possible to obtain a continuous gain variation using active resistors, the gain dependency would again be linear in the best case, so it offers nothing new. VGA2 is the one which offers more control options, already presented in Sect.€3.1, due to its linear dependency of gain with the control voltage. Finally, VGA3, which proposes a mixed, analog/digital, gain adjustment, presents a complex gain variation response to its control voltage, which could be considered linear at first order. Thus, VGA2 is the best candidate of
80
3â•… Basic AGC Cells
all to make a study of different linear VC generation circuits for both feedforward and feedback. Other options exist in the literature, the most common being the linear in dB VGA. However, VGA2 can also be employed as a linear-in-dB VGA just by introducing an exponential block to generate VC and considering the input to this block the real control voltage. Finally, VGAs with general gain functions can also be considered [58, 59], but these cases require the generation of the opposite function, which usually involves another feedback loop inside the AGC loop. In feedback AGCs the use of another internal loop can greatly complicate the stability of the system or force making a considerable reduction in the bandwidth of the feedback loop in order to make it much slower than the internal loop. This goes against the aims of this book of studying AGCs with a fast convergence. Alternatively, in feedforward AGCs the introduction of a new feedback loop in the AGC loop does not cause more stability complications than those inherent to the loop itself. However, it does go against obtaining a fast convergence. Thus, the use of these general gain function VGAs has also been ruled out. The control voltage required by VGA2 to accomplish (3.30), is simply:
vC = k
Vref Vpd
.
(3.31)
where k is a constant, Vref is the desired output voltage and Vpd is the signal provided by the peak detector. The most common analog control voltage generation circuit is based on the exponential solution used to obtain a time-constant independent of bias signals in feedback loop AGCs. In these loops, it is the option of employing the exponential converter at the end of the loop alone or with a logarithmic converter just after the peak detector. The generation of both converters is feasible in BiCMOS technology due to the exponential behaviour of the bipolar transistors. However, in CMOS technology this task is much harder, since transistors present a quadratic current response (characteristics of both technologies are exposed in Appendix D). Several solutions exist in the literature for the CMOS exp-converter [60–64] or exponential VGAs [65, 66] employing pseudo-exponential functions that make the task easier. On the other hand, there are no simple solutions for the log-converter. Thus, for the latter case the need is to make use of a piece-wise linear approximation to the logarithm function, see Fig.€3.56. As explained in [67], this method consists of using many small linear functions combined together to approximate the logarithmic function. Another option is to try implementing it by using previously mentioned exponential solutions in a feedback loop as shown in Fig.€3.57. The logarithm function in the latter case is approximated when amplifier gain, A0, is much bigger than one only. From Fig.€ 3.57 we have: zâ•› = â•›A0(↜x╛╛−╛╛y), yâ•› = â•›ez. As mentioned if A0â•›>>â•›1, x╛╛≈╛╛y, x╛╛≈╛╛ez, and consequently z╛╛≈╛╛log(↜x). Both cases cause complications in the AGC loop so in feedback loop the approach is usually preferable where a log-converter is avoided. Unfortunately, feedforward loop has no possibility of avoiding the use of the log-converter without accepting the loss of accuracy, since the relation between
3.3â•…Control Voltage Generation Circuit
81 Lim(Vout)
Vpd
Log(Vpd)
Fig. 3.56↜渀 Piece-wise linear approximation based logarithmic amplifier Fig. 3.57↜渀 Circuit to implement inverse of exponential function
Vpd
x
+ Amp
y
¯
Log(Vpd)
z
Exp
the control voltage function and the VGA gain function must be exact. Thus, it is mandatory to generate a circuit with a logarithmic response, employing one of the solutions proposed in Figs€3.56 and 3.57. The latter solution would be preferable for small input dynamic range AGCs, while piece-wise linear approximation is a better option for a higher dynamic range. Apart from the exponential VC generator, feedforward AGC´s accept another straightforward solution. To achieve output amplitude as shown in (3.31), when using a linear multiplier, the logical solution would be to use a divider. Even if the implementation of an accurate divider in both CMOS and BiCMOS technologies can be as laborious as implementing an exponential circuit, when small dynamic range is required, simple dividers based on MOS transistors operating in triode region, as shown in Fig.€3.58, can be an acceptable solution. In this case, M2 operates in triode region so
Vout ≈
I0 , K(VX − VT H )
(3.32)
where K and VTH are M2 transistor transconductance constant and threshold voltage, respectively. Thus, a division relation is obtained between the two inputs, I0 and VXâ•›. Dividers based on this simple technique can be found in several works in the literature and they have been employed in the implementation of pseudo-exponential circuits [64] for example. Higher accuracy and dynamic range can be obtained em-
82
3â•… Basic AGC Cells
Fig. 3.58↜渀 Simple divider
9'' 0
0
,
, 9RXW
9;
0
*1'
ploying more complex circuits; however, the study of this possible solution is left for future work.
3.3.3 Conclusions In conclusion, each VGA can require a different solution, although, for example in feedback AGCs, the same exponential type solution is preferred among designers in the end, while in feedforward AGCs, PGAs and digital control are usually employed. The next chapter introduces some proposals of control voltage generators explained in this section in general terms as part of the full AGCs proposed in the book.
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Chapter 4
AGC Systems
Chapter€4 presents the final AGC circuits achieved as a result of the study and the blocks implementation carried in previous chapters. In total three novel AGC circuits are proposed. First is a CMOS feedforward digital AGC loop, AGC1. It is targeted for WLAN applications and its main strong points are its compactness and simplicity, together with its fast convergence time. The second AGC, AGC2, looks into the advantages of SiGe BiCMOS technology and offers solutions to an existing standard. Thus, a full AGC architecture is implemented to be integrated as a block of an IEEE 802.11a WLAN receiver. In this case a specific application is pursued, the main objective being to fulfil the standard requirements with a robust proposal offering minimum area and power consumption. The last AGC, AGC3, is designed to complete this chapter with a circuit capable of working at very high frequencies. The interesting field of the mixed loop AGC is also analyzed and novel unconventional level detection methods are proposed. Finally, at the end of the chapter conclusions are drawn and an interesting comparison is offered between the proposed AGC circuits and some other architectures already proposed in the literature.
4.1â•…CMOS Feedforward Digital AGC Circuit In applications such as WLAN or Bluetooth receivers, timing constraints preclude the use of closed-loop AGC schemes. Meanwhile, novel feedforward and open loop gain control techniques have proven to be adequate to shorten the settling time and reduce the acquisition time of AGCs [1–3]. Therefore, an automatic gain control circuit based on a feedforward approach to achieve very fast convergence will be presented in this section. It consists of a digitally programmable gain amplifier, a peak detector and a 4-bit flash ADC using thermometer code, offering low-voltage (1.8€V) low-power operation (1.6€mW), low-distortion (â•›VRefâ•›, since it must be remembered that for Aâ•›≤â•›VRef the comparator output is zero. If we plot (4.7) for arbitrary constants using Matlab and analyze it with Curve Fitting Toolbox, it is found that another very useful function approximately fits in our application dynamic range. As Fig.€4.24 shows, for VRefâ•› = â•›0.1€V and input amplitude, A, between 0.1 and 0.2€V, (4.7) is quite close to a logarithmic function. Thus, a peak detector with an approximate logarithmic function is obtained as long as input dynamic range is kept low enough. After the detector, the signal is simply filtered and shifted so that the required VGA control voltage is obtained. Filtration is by means of a simple RC filter which mainly reduces the ripple generated by the charge pump. The RC filter is implemented as a MOS/switch-capacitor configuration where the MOS operates in triode and its equivalent resistance is reduced by a switch in parallel, which is connected for a small time period each time the digital feedforward loop changes the digital word. Providing the time period is not too long, AGC settling-time is reduced by this technique, whereas a simple differential pair makes the function of the level shifter. As mentioned, once logarithmic conversion has been achieved by the peak detector, if an exponential converter was introduced into the loop, the dynamic response given by (2.13) would be obtained. In its place, the dynamic response given by (2.10) for linear control voltage is expected. Once again, power supply is 1.8€V, the same as for the VGA. To follow, simulation and measurement results for certain separated blocks and the full AGC are offered.
4.3â•…CMOS Mixed Feedback/Feedforward AGC Circuit
109
Fig. 4.25↜渀 Chip photograph
Fig. 4.26↜渀 Measurement test circuitry
4.3.2 Performances The AGC circuit was designed in 0.35€µm CMOS technology by Austria Microsystems (AMS). The chip photograph is shown in Fig.€4.25. The corresponding layout for this structure has been carefully realized taking into account matching between transistors and symmetry between sections in order to minimize second order distortion components due to mismatches. Figure€4.26 shows the chip and the PCB used during measurement tests. Further information on the instrumentation and test probes employed is offered in Appendix A. First, VGA frequency response was measured. Simulation results obtained an almost constant bandwidth around 700€MHz. Measurements however obtained a constant bandwidth of only 500€MHz though this bandwidth is more than enough for the target application, which was expected to be around 250€MHz. Bandwidth and
110 Fig. 4.27↜渀 Gain vs. input amplitude for an input signal at 100€MHz
4â•… AGC Systems 14
Measured response Ideal response
12 10 8 Gain (dB) 6 4 2 0 –2 100
150
200
250
300
350
400
450
500
Vin (mVp-p)
gain configuration measurement results are the same as those obtained by VGA3 and can be consulted in Fig.€3.18. Next, measurement results are offered for input signals though only at 100€MHz, as, due to instrumentation limitations, it was not possible to make measurements at higher frequencies. Target and achievable frequencies are not so far apart, consequently, the obtained results can give a close view of expected results for 250€MHz signals. Distortion levels at high frequencies are expected to be high. Simulation results predicted an IM3 for a Voutâ•› = â•›0.4 Vp-p at 100€MHz below −â•›42€dB. Measured IM3 is below −â•›40€dB for all gain settings. Both results, simulated and measured, were obtained for the combination of the VGA and the buffer together and can be checked, as well as bandwidth results, in Chap.€3 (see Fig.€3.19). As shown, worst case results for IM3 correspond quite closely to those expected by simulations, although 6 and 12€dB IM3 was underestimated by simulations. A first estimation for the VGA without buffer IM3 is given by simulations which offer an IM3 for an output of 0.4€Vp-p at 100€MHz below −â•›49.2€dB for all gain settings. To check AGC loop linearity response, the output amplitude was measured for different inputs at 100€MHz and thus, a graph with the gain vs. input amplitude was obtained. Figure€ 4.27 shows this graph where it can be compared with the ideal response and with ±â•›1€dB error curves. As shown, the obtained gain is below ±1€dB from the ideal response for a range above the input dynamic range of 12€dB (from 100 to 400€mVp-p). Finally, convergence was checked. Simulation results predicted a convergence time for a stepwise signal at 250€MHz below 50€ns. Again, instrumentation limitations prevented the use of such a high frequency modulation; instead, measurements were made with a square modulation of 300€KHz and a carrier frequency of 20€MHz. As shown in Fig.€4.28, the AGC response to this input signal is quite fast. Therefore, although it is not possible to verify whether predicted simulations are
4.3â•…CMOS Mixed Feedback/Feedforward AGC Circuit
111
1.5
0.3
Vc (V)
0.1
1.3
0
1.2
¯0.1 ¯0.2
1.1
0
0.5
1
1.5
2 t (s)
2.5
2 t (s)
2.5
3
AGC Input (V)
0.2
1.4
0.3
4¯
3.5
¯7
x 10
0.3 0.1 0 ¯0.1 ¯0.2 ¯0.3
0
0.5
1
1.5
3
3.5
4 x 10¯7
0.05
0.45
0.025
0.4 0.35
0 ¯0.025 ¯0.05
0.3 0
0.5
1
1.5
2
2.5 t (s)
3
2.5 t (s)
3
3.5
4
4.5
5
Vc (V)
AGC Input (V)
AGC Output (V)
0.2
0.25
x 10¯6
0.03 AGC Output (V)
0.02 0.01 0 ¯0.01 ¯0.02 ¯0.03 0
0.5
1
1.5
2
3.5
4
4.5
5
x 10¯6
Fig. 4.28↜渀 AGC convergence with a square modulation at 300€KHz and a carrier at 250€MHz for simulation (↜up) and 20€MHz for measurements (↜down) are offered
good, measurement results at least offer a maximum response time below 0.8€µs which is the maximum time required to vary VC between its maximum and minimum value with a 20€MHz signal.
112
4â•… AGC Systems
4.4â•…Conclusions Section€4.1 presented a 1.8€V─0.35€µm CMOS automatic gain control circuit based on a digital feedforward approach which converges to the desired level within 0.3€µs. The proposed architecture is very simple, compact and can be implemented with basic cells, obtaining at the same time high performance characteristics. Therefore, this AGC would prove very useful in applications such as WLAN or Bluetooth receivers where the use of traditional closed loop feedback amplifiers forms a boundary due to the stringent settling time constraints. The second proposition presented is a full analogue SiGe BiCMOS AGC circuitry embedded in an IEEE 802.11a WLAN direct conversion receiver. Based on an analog feedforward gain control technique, the circuit adjusts the gain rapidly and with high accuracy, maintaining at the same time a good trade-off between simplicity and power consumption. Therefore, this analog feedforward approach which provides very fast convergence and high enough linearity performance, classifies this architecture for WLAN receiver implementation. The third and final proposed AGC is a double loop AGC for application frequencies up to 250€ MHz. The fast feedforward loop is combined with a more linear feedback loop, so it is possible to offer a fast enough AGC without gain steps that not all applications can accept. Furthermore, a novel digital level detection method is proposed for the feedforward loop and another pseudo-logarithmic peak detector has been obtained for the feedback loop. Summarizing, 0.35€µm CMOS technology has been taken to its upper frequency limitation to offer a sufficiently linear AGC implemented with some simple but novel blocks. Next, a table (Table€4.1) is offered with main characteristics of three analyzed AGCs and some more AGC proposals from the literature: For WLAN applications, the AGC proposed by Dr. Jeon ET. Al in [1] is one of the most complete AGCs to be found in the literature. Therefore, it is a key reference in this book where WLAN receivers are the target application. AGC1 and AGC2 proposals aim to improve the performances obtained in this case. AGC2 is targeted specifically for the same IEEE standard as Jeon’s work. However, the circuit proposed here obtains a faster convergence-time thanks to its feedforward loop, while other performances are similar to those obtained in [1]. The strong points of AGC1 are its simplicity and very fast response. This AGC also offers considerably lower power consumption than other options; although, it would rise a little if gain range and precision were increased. [20] is another example from the literature of an AGC implemented in BiCMOS with high bandwidth and fast response. However, it has the usual drawback in BiCMOS technologies. A higher power supply voltage is used and consequently, consumption is much higher than in other AGCs. AGC2. In spite of using BiCMOS technology, it also makes use of low voltage blocks, so it can work with the right power supply for CMOS transistors. Finally, AGC3, the proposal for high frequency applications, achieves the 243€MHz standard with moderate power consumption, while other performances are below standard for these frequencies.
b
a
Attack-time THD
Supply voltage (V) Power (mW) Intrinsic bandwidth (MHz) AGC Gain range (dB) Gain setting AGC settling-time (μs) AGC output voltage (V) Distortion: IM3 (dB)
Tech process
0.25€μm BiCMOS 3–5.2 60–104 400 0â•›∼â•›45 Continuous 0.3a 0.11 — 0.18€μm CMOS 1.6–2 10.44 18 −8â•›∼â•›32 Continuous (±ldB) 4.2 0.5