Analog Integrated Circuits-Power management Signal conditioning and ASSP

DL128/D Rev. 7, Mar-2002 Analog Integrated Circuits Power Management, Signal Conditioning and ASSP Devices Literature ...

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DL128/D Rev. 7, Mar-2002

Analog Integrated Circuits Power Management, Signal Conditioning and ASSP Devices

Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected]

JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: [email protected]

N. American Technical Support: 800-282-9855 Toll Free USA/Canada

For additional information, please contact your local Sales Representative

ON Semiconductor Website: http://onsemi.com

DL128/D

Analog Integrated Circuits

PUBLICATION ORDERING INFORMATION

Power Management Devices Part 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

Volume I Pages 1-1263 VOLTAGE REF VOLTAGE REG AC/DC SWITCHING BATTERY MGMT 03/02 DL128 REV 7

Analog Integrated Circuits Power Management, Signal Conditioning and ASSP Devices

DL128/D Rev. 7, Mar–2002

 SCILLC, 2002 Previous Edition  1996 “All Rights Reserved”

NOCAP, POWERSENSE, SENSEFET, SMALLBLOCK and SWITCHMODE are trademarks of Semiconductor Components Industries, LLC (SCILLC). SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). GreenLine and SMARTMOS are trademarks of Motorola, Inc. Micro8 is a trademark of International Rectifier. POWERMITE is a registered trademark of and used under a license from Microsemi Corporation. V2 is a registered trademark of Switch Power, Inc. All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected]

JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.

N. American Technical Support: 800–282–9855 Toll Free USA/Canada

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Table of Contents

Page

Numeric Data Sheet Listing

INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Transistor Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Display Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Page Numeric Data Sheet Listing . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chapter 1: Family Tree and Selector Guide

SPECIAL FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . 75 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

APPLICATION SPECIFIC STANDARD PRODUCTS . . . . . . . . . . . . . . . . . . . . 76

SIGNAL CONDITIONING . . . . . . . . . . . . . . . . . . . . 15 Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Analog Switches and Multiplexers . . . . . . . . . . . . . . . . 24

Industrial/Appliances/Motor Control . . . . . . . . . . . . . . . Automotive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Networking/Computing . . . . . . . . . . . . . . . . . . . . . . . . . . Wireless & Portable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Smart Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . 25 Battery Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lithium Battery Protection ICs . . . . . . . . . . . . . . . . . Charge Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . Overvoltage Charge Protection . . . . . . . . . . . . . . . . DC/DC Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . . Switching Controllers . . . . . . . . . . . . . . . . . . . . . . . . . CPU DC–DC Controllers . . . . . . . . . . . . . . . . . . . . . . AC–DC Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Power Supply Controllers . . . . . . . . . . . . Off–Line Switching Controllers . . . . . . . . . . . . . . . . . Very High Voltage Off–Line Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . Power Factor Controllers . . . . . . . . . . . . . . . . . . . . . Voltage References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linear Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . General Purpose Linear Voltage Regulators . . . . . Low Dropout Linear Voltage Regulators . . . . . . . . . Application Specific Low Dropout Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . Supervisory ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOSFET/IGBT Drivers . . . . . . . . . . . . . . . . . . . . . . . Load/Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . Display Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Smart Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dedicated Power Management Controllers . . . . . . . . .

25 25 25 25 26 26 27 34 35 35 38

77 78 82 83 84

Chapter 2: Data Sheets Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Chapter 3: Case Outlines and Package Dimensions Case Outlines and Package Dimensions . . . . . . . . . . 3499

40 42 44 46 46 49

Chapter 4: Index Alphanumeric Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3535 Sales Office Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3541 Document Type Definitions . . . . . . . . . . . . . . . . . . . . . 3542

57 64 67 67 67 67 69 71

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Numeric Data Sheet Listing

Device Number

Function

Page

LM285, LM385, LM385B . . . . . . . .

Micropower Voltage Reference Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

86

NCP100 . . . . . . . . . . . . . . . . . . . . . . .

Sub 1.0 V Precision Adjustable Shunt Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

91

TLV431A . . . . . . . . . . . . . . . . . . . . . .

Low Voltage Precision Adjustable Shunt Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

100

TL431, TL431A, TL431B . . . . . . . .

Programmable Precision References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

111

CS1009 . . . . . . . . . . . . . . . . . . . . . . .

2.5 Volt Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

123

MC1403, MC1403B . . . . . . . . . . . . .

Low Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

128

MC78L00A Series . . . . . . . . . . . . . .

100 mA Positive Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

132

MC78M00, MC78M00A Series . . .

500 mA Positive Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

142

MC7800, MC7800A, LM340, LM340A Series . . . . . . . . . . . . . . . .

1.0 A Positive Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

152

MC78T00 Series . . . . . . . . . . . . . . .


170

LM323, LM323A . . . . . . . . . . . . . . .


179

MC79L00, MC79L00A Series . . . .

100 mA Negative Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

185

MC79M00 Series . . . . . . . . . . . . . . .

500 mA Negative Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

190

MC7900 Series . . . . . . . . . . . . . . . .

1.0 A Negative Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

194

LM317L . . . . . . . . . . . . . . . . . . . . . . .

100 mA Adjustable Output, Positive Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

206

LM317M . . . . . . . . . . . . . . . . . . . . . .

500 mA Adjustable Output, Positive Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

214

LM317 . . . . . . . . . . . . . . . . . . . . . . . .

1.5 A Adjustable Output, Positive Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

224

LM350 . . . . . . . . . . . . . . . . . . . . . . . .

3.0 A, Adjustable Output, Positive Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

233

LM337 . . . . . . . . . . . . . . . . . . . . . . . .

1.5 A, Adjustable Output, Negative Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

241

MC78LC00 Series . . . . . . . . . . . . . .

Micropower Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

248

MC33761 . . . . . . . . . . . . . . . . . . . . .

Ultra Low–Noise Low Dropout Voltage Regulator with 1.0 V ON/OFF Control . . . . . . . . . . .

254

NCP4561 . . . . . . . . . . . . . . . . . . . . .

Ultra Low–Noise Low Dropout Voltage Regulator with 1.0 V ON/OFF Control . . . . . . . . . . .

267

NCP502 . . . . . . . . . . . . . . . . . . . . . . .

80 mA CMOS Low Iq Voltage Regulator in an SC70–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

279

NCP512 . . . . . . . . . . . . . . . . . . . . . . .

80 mA CMOS Low Iq Voltage Regulator in an SC70–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

288

NCP552 . . . . . . . . . . . . . . . . . . . . . . .

80 mA CMOS Low Iq NOCAPt Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

295

NCP553 . . . . . . . . . . . . . . . . . . . . . . .

80 mA CMOS Low Iq NOCAPt Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

304

NCP562 . . . . . . . . . . . . . . . . . . . . . . .

80 mA CMOS Low Iq Low–Dropout Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

313

NCP563 . . . . . . . . . . . . . . . . . . . . . . .

80 mA CMOS Low Iq Low–Dropout Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

321

LM2931 Series . . . . . . . . . . . . . . . . .

100 mA, Adjustable Output, LDO Voltage Regulator with 60 V Load Dump Protection . . . .

329

LP2950, LP2951 . . . . . . . . . . . . . . .

100 mA, 3.0 V, Low Power Low Dropout Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . .

342

CS8221 . . . . . . . . . . . . . . . . . . . . . . .

Micropower 5.0 V, 100 mA Low Dropout Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . .

356

CS9201 . . . . . . . . . . . . . . . . . . . . . . .

Micropower 5.0 V, 100 mA Low Dropout Linear Regulator with NOCAPt . . . . . . . . . . . . . .

361

CS9202 . . . . . . . . . . . . . . . . . . . . . . .

Micropower 3.3 V, 100 mA Low Dropout Linear Regulator with NOCAPt . . . . . . . . . . . . . .

366

L4949 . . . . . . . . . . . . . . . . . . . . . . . . .

100 mA, 5.0 V, Low Dropout Voltage Regulator with Power–On Reset . . . . . . . . . . . . . . . . .

371

CS8311 . . . . . . . . . . . . . . . . . . . . . . .

Micropower 10 V, 100 mA Low Dropout Linear Regulator with RESET and ENABLE . . . . .

378 385

CS8101 . . . . . . . . . . . . . . . . . . . . . . .

Micropower 5.0 V, 100 mA Low Dropout Linear Regulator with RESET and ENABLE . . . .

CS8151 . . . . . . . . . . . . . . . . . . . . . . .

5.0 V, 100 mA Low Dropout Linear Regulator with Watchdog, RESET, and Wake Up . . . . .

394

MC78FC00 Series . . . . . . . . . . . . . .


403

CS8321 . . . . . . . . . . . . . . . . . . . . . . .

Micropower 5.0 V, 150 mA Low Dropout Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . .

407

MC33263 . . . . . . . . . . . . . . . . . . . . .

Ultra Low Noise 150 mA Low Dropout Voltage Regulator with ON/OFF Control . . . . . . . . . .

412

MC78PC00 Series . . . . . . . . . . . . . .

Low Noise 150 mA Low Drop Out (LDO) Linear Voltage Regulator . . . . . . . . . . . . . . . . . . . .

424

NCP551 . . . . . . . . . . . . . . . . . . . . . . .

150 mA CMOS Low Iq Low–Dropout Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

439

NCP561 . . . . . . . . . . . . . . . . . . . . . . .


449

NCP500 . . . . . . . . . . . . . . . . . . . . . . .

150 mA CMOS Low Noise Low–Dropout Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . .

459

NCP511 . . . . . . . . . . . . . . . . . . . . . . .


476

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Device Number

Function

Page

NCP5426 . . . . . . . . . . . . . . . . . . . . .

LDO Regulator/Vibration Motor Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

487

CS8182 . . . . . . . . . . . . . . . . . . . . . . .

Micropower 200 mA Low Dropout Tracking Regulator/Line Driver . . . . . . . . . . . . . . . . . . . . .

495

MC33565 . . . . . . . . . . . . . . . . . . . . .

Smart Voltage Regulator for Peripheral Card Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .

500

MC33275 . . . . . . . . . . . . . . . . . . . . .

300 mA, 2.5 V, Low Dropout Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

511

MC33375 . . . . . . . . . . . . . . . . . . . . .

300 mA, 2.5 V, Low Dropout Voltage Regulator with On/Off Control . . . . . . . . . . . . . . . . . . . .

520

CS8120 . . . . . . . . . . . . . . . . . . . . . . .

5.0 V, 300 mA Linear Regulator with RESET and ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . .

530

CS5231–3 . . . . . . . . . . . . . . . . . . . . .

500 mA, 3.3 V Linear Regulator with Auxiliary Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

540

CS5233–3 . . . . . . . . . . . . . . . . . . . . .

500 mA and 1.5 A, 3.3 V Dual Input Linear Regulator with Auxiliary Control . . . . . . . . . . . . .

552

CS8140, CS8141 . . . . . . . . . . . . . . .

5.0 V, 500 mA Linear Regulator with ENABLE, RESET, and Watchdog . . . . . . . . . . . . . . . . .

561

MC78BC00 Series . . . . . . . . . . . . . .


575

CS403 . . . . . . . . . . . . . . . . . . . . . . . .

5.0 V, 750 mA Linear Regulator with RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

581

CS8122 . . . . . . . . . . . . . . . . . . . . . . .

2.0% 5.0 V, 750 mA Low Dropout Linear Regulator with Delayed RESET . . . . . . . . . . . . . . .

587 595

CS8126 . . . . . . . . . . . . . . . . . . . . . . .

5.0 V, 750 mA Low Dropout Linear Regulator with Delayed RESET . . . . . . . . . . . . . . . . . . . .

CS8129 . . . . . . . . . . . . . . . . . . . . . . .

5.0 V, 750 mA Low Dropout Linear Regulator with Lower RESET Threshold . . . . . . . . . . . .

604

MC34268 . . . . . . . . . . . . . . . . . . . . .

800 mA, 2.85 V, SCSI–2 Active Terminator, Low Dropout Voltage Regulator . . . . . . . . . . . .

612

NCP1117 . . . . . . . . . . . . . . . . . . . . . .

1.0 A Low–Dropout Positive Fixed and Adjustable Voltage Regulators . . . . . . . . . . . . . . . . .

615

MC33269 . . . . . . . . . . . . . . . . . . . . .

800 mA, Adjustable Output, Low Dropout Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . .

627

CS5201–3 . . . . . . . . . . . . . . . . . . . . .

1.0 A, 3.3 V Fixed Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

635

CS5201–1 . . . . . . . . . . . . . . . . . . . . .

1.0 A Adjustable Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

641

CS52015–3 . . . . . . . . . . . . . . . . . . . .


648

CS52015–1 . . . . . . . . . . . . . . . . . . . .


654

CS5203–3 . . . . . . . . . . . . . . . . . . . . .


661

CS5203A–1, CS5203A–2, CS5203A–3, CS5203A–5 . . . . . . . .

3.0 A Adjustable, and Fixed 1.5 V, 3.3 V and 5.0 V Linear Regulators . . . . . . . . . . . . . . . . . .

667

CS5253B–8 . . . . . . . . . . . . . . . . . . .

3.0 A LDO 5–Pin 2.5 V Fixed Linear Regulator for Remote Sense Applications . . . . . . . . . .

675

CS5203–1 . . . . . . . . . . . . . . . . . . . . .


683

CS5253–1 . . . . . . . . . . . . . . . . . . . . .

3.0 A LDO 5–Pin Adjustable Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

691

CS5204–2 . . . . . . . . . . . . . . . . . . . . .


701

CS5204–1, CS5204–3, CS5204–5

4.0 A Adjustable, and 3.3 V and 5.0 V Fixed Linear Regulators . . . . . . . . . . . . . . . . . . . . . . .

707

CS5205–2 . . . . . . . . . . . . . . . . . . . . .


715

CS5205–1, CS5205–3, CS5205–5

5.0 A Adjustable, and 3.3 V and 5.0 V Fixed Linear Regulators . . . . . . . . . . . . . . . . . . . . . . .

721

CS5205A–1 . . . . . . . . . . . . . . . . . . .


729

CS5206–1, CS5206–3, CS5206–5

6.0 A Adjustable, and Fixed 3.3 V and 5.0 V Linear Regulators . . . . . . . . . . . . . . . . . . . . . . .

735

CS5207–2 . . . . . . . . . . . . . . . . . . . . .


743

CS5207–3 . . . . . . . . . . . . . . . . . . . . .


748

CS5207–1 . . . . . . . . . . . . . . . . . . . . .


753

CS5207A–1 . . . . . . . . . . . . . . . . . . .


759

CS5257A–1 . . . . . . . . . . . . . . . . . . .


766

CS5208–1 . . . . . . . . . . . . . . . . . . . . .


776

CS5258–1 . . . . . . . . . . . . . . . . . . . . .


783

NCP2860 . . . . . . . . . . . . . . . . . . . . .

300 mA Very Low Noise, Low Dropout Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

792

MC33765 . . . . . . . . . . . . . . . . . . . . .

Very Low Dropout/Ultra Low Noise 5 Outputs Voltage Regulator . . . . . . . . . . . . . . . . . . . . . .

800

MC33762 . . . . . . . . . . . . . . . . . . . . .

Dual Ultra Low–Noise Low Dropout Voltage Regulator with 1.0 V ON/OFF Control . . . . . . .

813

MC33566 . . . . . . . . . . . . . . . . . . . . .

Smart Voltage Regulator for Peripheral Card Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .

827

MC33567 . . . . . . . . . . . . . . . . . . . . .

Dual Linear Controller for High Current Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . .

832

MC34160, MC33160 . . . . . . . . . . . .

100 mA, 5.0 V Voltage Regulator and Supervisory Circuit for Microprocessors . . . . . . . . . .

841

CS8271 . . . . . . . . . . . . . . . . . . . . . . .

Adjustable Micropower Low Dropout Linear Regulator with ENABLE . . . . . . . . . . . . . . . . . . .

849

CS8183 . . . . . . . . . . . . . . . . . . . . . . .

Dual Micropower 200 mA Low Dropout Tracking Regulator/Line Driver . . . . . . . . . . . . . . . . .

855

CS8363 . . . . . . . . . . . . . . . . . . . . . . .

3.3 V Dual Micropower Low Dropout Regulator with ENABLE and RESET . . . . . . . . . . . . . .

860

CS8361 . . . . . . . . . . . . . . . . . . . . . . .

5.0 V Dual Micropower Low Dropout Regulator with ENABLE and RESET . . . . . . . . . . . . . .

866

CS8147 . . . . . . . . . . . . . . . . . . . . . . .

10 V/5.0 V Low Dropout Dual Regulator with ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

872

http://onsemi.com 6

Device Number

Function

Page

CS8156 . . . . . . . . . . . . . . . . . . . . . . .

12 V, 5.0 V Low Dropout Dual Regulator with ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

880

CS8161 . . . . . . . . . . . . . . . . . . . . . . .

12 V, 5.0 V Low Dropout Dual Regulator with ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

889

CS8281 . . . . . . . . . . . . . . . . . . . . . . .

5.0 V/250 mA, 5.0 V/100 mA Micropower Low Dropout Regulator with ENABLE . . . . . . . . .

898

CS8371 . . . . . . . . . . . . . . . . . . . . . . .

8.0 V/1.0 A, 5.0 V/250 mA Dual Regulator with Independent Output Enables and NOCAPt

904

CS8391 . . . . . . . . . . . . . . . . . . . . . . .


913

CS8481 . . . . . . . . . . . . . . . . . . . . . . .


919

NCV8501 Series . . . . . . . . . . . . . . .

Micropower 150 mA LDO Linear Regulators with ENABLE, Delay, RESET, and Monitor Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

925

NCV8502 Series . . . . . . . . . . . . . . .

Micropower 150 mA LDO Linear Regulators with Delay, Adjustable RESET, and Monitor Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

935

NCV8508 Series . . . . . . . . . . . . . . .

Low Dropout Linear Regulators with Watchdog, RESET, and Wake Up . . . . . . . . . . . . . . . . .

945

CS5101 . . . . . . . . . . . . . . . . . . . . . . .

Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters . . . . . .

955

NCP4300A . . . . . . . . . . . . . . . . . . . .

Dual Operational Amplifier and Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

963

MC44608 . . . . . . . . . . . . . . . . . . . . .

Few External Components Reliable and Flexible SMPS Controller . . . . . . . . . . . . . . . . . . . .

969

NCP1200 . . . . . . . . . . . . . . . . . . . . .

PWM Current–Mode Controller for Low–Power Universal Off–Line Supplies . . . . . . . . . . . .

983

NCP1203 . . . . . . . . . . . . . . . . . . . . .

PWM Current–Mode Controller for Universal Off–Line Supplies Featuring Standby and Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

996

MC33364 . . . . . . . . . . . . . . . . . . . . .

Critical Conduction GreenLine SMPS Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1006

MC33363 . . . . . . . . . . . . . . . . . . . . .

High Voltage Switching Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1020

MC33363A . . . . . . . . . . . . . . . . . . . .


1031

MC33363B . . . . . . . . . . . . . . . . . . . .


1043

MC33365 . . . . . . . . . . . . . . . . . . . . .


1053

MC33362 . . . . . . . . . . . . . . . . . . . . .


1063

NCP1000, NCP1001, NCP1002 . .

Integrated Off–Line Switching Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1075

NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055 . .

Monolithic High Voltage Gated Oscillator Power Switching Regulator . . . . . . . . . . . . . . . . . .

1089

MC33368 . . . . . . . . . . . . . . . . . . . . .

High Voltage GreenLine Power Factor Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1111

MC34262, MC33262 . . . . . . . . . . . .

Power Factor Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1126

MC33260 . . . . . . . . . . . . . . . . . . . . .

GreenLine Compact Power Factor Controller: Innovative Circuit for Cost Effective Solutions

1141

MC33349 . . . . . . . . . . . . . . . . . . . . .

Lithium Battery Protection Circuit for One Cell Battery Packs . . . . . . . . . . . . . . . . . . . . . . . . .

1160

NCP800 . . . . . . . . . . . . . . . . . . . . . . .

Lithium Battery Protection Circuit for One Cell Battery Packs . . . . . . . . . . . . . . . . . . . . . . . . .

1171

MC33351A . . . . . . . . . . . . . . . . . . . .

Lithium Battery Protection Circuit for Three Battery Packs . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1180

MC33340, MC33342 . . . . . . . . . . . .

Battery Fast Charge Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1193

MC33341 . . . . . . . . . . . . . . . . . . . . .

Power Supply Battery Charger Regulation Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1204

NCP1500 . . . . . . . . . . . . . . . . . . . . .

Dual Mode PWM/Linear BUCK Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1221

CS5361 . . . . . . . . . . . . . . . . . . . . . . .

Battery Charger Buck Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1231

NCP1800 . . . . . . . . . . . . . . . . . . . . .

Single–Cell Lithium Ion Battery Charge Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1246

NCP345 . . . . . . . . . . . . . . . . . . . . . . .

Over Voltage Protection IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1257

CS51411, CS51412, CS51413, CS51414 . . . . . . . . . . . . . . . . . . . . . .

1.5 A, 260 kHz and 520 kHz, Low Voltage Buck Regulators with External Bias or Synchronization Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1264

LM2574 . . . . . . . . . . . . . . . . . . . . . . .

0.5 A, Adjustable Output Voltage, Step–Down Switching Regulator . . . . . . . . . . . . . . . . . . . .

1278

LM2575 . . . . . . . . . . . . . . . . . . . . . . .

1.0 A, Adjustable Output Voltage, Step–Down Switching Regulator . . . . . . . . . . . . . . . . . . . .

1302

LM2576 . . . . . . . . . . . . . . . . . . . . . . .

3.0 A, 15 V, Step–Down Switching Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1326

CS2001 . . . . . . . . . . . . . . . . . . . . . . .

1.2 A Switching Regulator, and 5.0 V, 100 mA Linear Regulator with RESET . . . . . . . . . . . .

1350

CS5111 . . . . . . . . . . . . . . . . . . . . . . .

1.4 A Switching Regulator with 5.0 V, 100 mA Linear Regulator with Watchdog, RESET and ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1356

CS5112 . . . . . . . . . . . . . . . . . . . . . . .

1.4 A Switching Regulator with 5.0 V, 100 mA Linear Regulator with Watchdog, RESET and ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1369

CS5171, CS5172, CS5173, CS5174 . . . . . . . . . . . . . . . . . . . . . . .

1.5 A 280 kHz/560 kHz Boost Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1382

MC33463 . . . . . . . . . . . . . . . . . . . . .

Variable Frequency Micropower DC–to–DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1403

http://onsemi.com 7

Device Number

Function

Page

MC33466 . . . . . . . . . . . . . . . . . . . . .

Fixed Frequency PWM Micropower DC–to–DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1414

NCP1400A . . . . . . . . . . . . . . . . . . . .

100 mA, Fixed Frequency PWM Step–Up Micropower Switching Regulator . . . . . . . . . . . . .

1427

NCP1402 . . . . . . . . . . . . . . . . . . . . .

200 mA, PFM Step–Up Micropower Switching Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1441

NCP1410 . . . . . . . . . . . . . . . . . . . . .

250 mA Sync–Rect PFM Step–Up DC–DC Converter with Low–Battery Detector . . . . . . . .

1458

NCP1411 . . . . . . . . . . . . . . . . . . . . . .

Sync–Rect PFM Step–Up DC–DC Converter with Low–Battery Detector and Ring–Killer .

1470

NCP1450A . . . . . . . . . . . . . . . . . . . .

PWM Step–up DC–DC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1482

MC34063A, MC33063A . . . . . . . . .

1.5 A, Step–Up/Down/Inverting Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1504

MC34163, MC33163 . . . . . . . . . . . .


1515

MC34166, MC33166 . . . . . . . . . . . .


1529

MC34167, MC33167 . . . . . . . . . . . .

5.0 A, Step–Up/Down/inverting Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1546

CS51031 . . . . . . . . . . . . . . . . . . . . . .

Fast PFET Buck Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1563

CS51033 . . . . . . . . . . . . . . . . . . . . . .

Fast PFET Buck Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1572

CS5211 . . . . . . . . . . . . . . . . . . . . . . .

Low Voltage Synchronous Buck Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1581

NCP1570 . . . . . . . . . . . . . . . . . . . . .


1595

NCP1571 . . . . . . . . . . . . . . . . . . . . .


1608

NCP5162 . . . . . . . . . . . . . . . . . . . . .

General Purpose Synchronous Buck Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1622 1636

CS5421 . . . . . . . . . . . . . . . . . . . . . . .

Dual Out–of–Phase Synchronous Buck Controller with Remote Sense . . . . . . . . . . . . . . . . .

CS5422 . . . . . . . . . . . . . . . . . . . . . . .

Dual Out–of–Phase Synchronous Buck Controller with Current Limit . . . . . . . . . . . . . . . . . . .

1649

MC34060A, MC33060A . . . . . . . . .

Fixed Frequency, PWM, Voltage Mode Single Ended Controllers . . . . . . . . . . . . . . . . . . . . . .

1665

MC34023, MC33023 . . . . . . . . . . . .

High Speed Single–Ended PWM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1679

CS51220 . . . . . . . . . . . . . . . . . . . . . .

Feed Forward Voltage Mode PWM Controller with Programmable Synchronization . . . . . .

1695

NCP1560 . . . . . . . . . . . . . . . . . . . . .

Full Featured Voltage Mode PWM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1710

TL494 . . . . . . . . . . . . . . . . . . . . . . . .

SWITCHMODE Pulse Width Modulation Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1718

TL594 . . . . . . . . . . . . . . . . . . . . . . . .

Precision Switchmode Pulse Width Modulation Control Circuit . . . . . . . . . . . . . . . . . . . . . . . .

1728

SG3525A . . . . . . . . . . . . . . . . . . . . .

Pulse Width Modulator Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1738

CS3524A . . . . . . . . . . . . . . . . . . . . . .

Voltage Mode PWM Control Circuit with 200 mA Output Drivers . . . . . . . . . . . . . . . . . . . . . . .

1744

CS51221 . . . . . . . . . . . . . . . . . . . . . .

Enhanced Voltage Mode PWM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1750

CS51227 . . . . . . . . . . . . . . . . . . . . . .

Enhanced Voltage Mode PWM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1762

MC34025, MC33025 . . . . . . . . . . . .

High Speed Double–Ended PWM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1769

UC3842A, UC3843A, UC2842A, UC2843A . . . . . . . . . . . . . . . . . . . . .

High Performance Current Mode Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1786

UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV . . . . . . . . .


1802

UC3844B, UC3845B, UC2844B, UC2845B . . . . . . . . . . . . . . . . . . . . .


1819

CS2841B . . . . . . . . . . . . . . . . . . . . . .

Automotive Current Mode PWM Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1836

CS5124, CS5126 . . . . . . . . . . . . . . .

High Performance Integrated Current Mode PWM Controllers . . . . . . . . . . . . . . . . . . . . . . . .

1844

MC44603A . . . . . . . . . . . . . . . . . . . .

Enhanced Mixed Frequency Mode GreenLinet PWM Controller: Fixed Frequency, Variable Frequency, Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1855

MC44604 . . . . . . . . . . . . . . . . . . . . .

High Safety Pulsed Mode Standby GreenLine PWM Controller . . . . . . . . . . . . . . . . . . . . . . . .

1875

MC44605 . . . . . . . . . . . . . . . . . . . . .

High Safety, Latched Mode, GreenLine PWM Controller for (Multi) Synchronized Applications .

1896

CS51021A, CS51022A, CS51023A, CS51024A . . . . . . . . . .

Enhanced Current Mode PWM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1915

CS5106 . . . . . . . . . . . . . . . . . . . . . . .

Multi–Feature, Synchronous plus Auxiliary PWM Controller . . . . . . . . . . . . . . . . . . . . . . . . . .

1924

MC34067, MC33067 . . . . . . . . . . . .

High Performance Resonant Mode Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1938

MAX1720 . . . . . . . . . . . . . . . . . . . . .

Switched Capacitor Voltage Inverter with Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1951

MAX828, MAX829 . . . . . . . . . . . . . .

Switched Capacitor Voltage Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1973

CS5150H . . . . . . . . . . . . . . . . . . . . .

CPU 4–Bit Synchronous Buck Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1991

CS5151H . . . . . . . . . . . . . . . . . . . . .

CPU 4–Bit Nonsynchronous Buck Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2008

CS5155H . . . . . . . . . . . . . . . . . . . . .


2023

CS5156H . . . . . . . . . . . . . . . . . . . . .

CPU 5–Bit Nonsynchronous Buck Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2040

CS5161, CS5161H . . . . . . . . . . . . .


2055

http://onsemi.com 8

Device Number

Function

Page

CS5165H . . . . . . . . . . . . . . . . . . . . .

5–Bit Synchronous CPU Buck Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2072

CS5166H . . . . . . . . . . . . . . . . . . . . .

5–Bit Synchronous CPU Controller with Power Good and Current Limit . . . . . . . . . . . . . . . .

2093

CS51312 . . . . . . . . . . . . . . . . . . . . . .

Synchronous CPU Buck Controller for 12 V Only Applications . . . . . . . . . . . . . . . . . . . . . . . .

2119

CS5157H . . . . . . . . . . . . . . . . . . . . .


2140

CS5158 . . . . . . . . . . . . . . . . . . . . . . .


2156

CS5159 . . . . . . . . . . . . . . . . . . . . . . .


2171

CS5160 . . . . . . . . . . . . . . . . . . . . . . .


2187

CS51311 . . . . . . . . . . . . . . . . . . . . . .

Synchronous CPU Buck Controller for 12 V and 5.0 V Applications . . . . . . . . . . . . . . . . . . . .

2204

MC33470 . . . . . . . . . . . . . . . . . . . . .

Synchronous Rectification DC/DC Converter Programmable Integrated Controller . . . . . . .

2224

CS51313 . . . . . . . . . . . . . . . . . . . . . .

Synchronous CPU Buck Controller Capable of Implementing Multiple Linear Regulators . .

2238

CS5301 . . . . . . . . . . . . . . . . . . . . . . .

Three–Phase Buck Controller with Integrated Gate Drivers and Power Good . . . . . . . . . . .

2259

CS5302 . . . . . . . . . . . . . . . . . . . . . . .

Two–Phase Buck Controller with Integrated Gate Drivers and 4–Bit DAC . . . . . . . . . . . . . . .

2277

CS5303 . . . . . . . . . . . . . . . . . . . . . . .

Three–Phase Buck Controller with Integrated Gate Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . .

2293

CS5305 . . . . . . . . . . . . . . . . . . . . . . .

Three–Phase Synchronous Switching Step–Down Controller with Single Wire Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2311

CS5307 . . . . . . . . . . . . . . . . . . . . . . .

Four–Phase Buck CPU Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2342

CS5308 . . . . . . . . . . . . . . . . . . . . . . .

Two–Phase PWM Controller with Integrated Gate Drivers for VRM 8.5 . . . . . . . . . . . . . . . . .

2357

CS5322 . . . . . . . . . . . . . . . . . . . . . . .


2386

NCP5322A . . . . . . . . . . . . . . . . . . . .


2406

CS5323 . . . . . . . . . . . . . . . . . . . . . . .

Three–Phase Buck Controller with 5–Bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2435

CS5332 . . . . . . . . . . . . . . . . . . . . . . .

Two–Phase Buck Controller with Integrated Gate Drivers for VRM 9.0 . . . . . . . . . . . . . . . . .

2450

MC33501, MC33503 . . . . . . . . . . . .

1.0 V, Rail–to–Rail, Single Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2469

MC33502 . . . . . . . . . . . . . . . . . . . . .

1.0 V, Rail–to–Rail, Dual Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2485

MC33201, MC33202, MC33204 . .

Low Voltage, Rail–to–Rail Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2501

NCS2001 . . . . . . . . . . . . . . . . . . . . .

0.9 V, Rail–to–Rail Single Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2517

NCS7101 . . . . . . . . . . . . . . . . . . . . .

1.8 Volt Rail–to–Rail Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2537

MC33171, MC33172, MC33174 . .

Single Supply 3.0 V to 44 V, Low Power Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . .

2553

MC33178, MC33179 . . . . . . . . . . . .

Low Power, Low Noise Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2565

LM324, LM324A, LM224, LM2902, LM2902V, NCV2902 . . . . . . . . . . . .

Quad Differential Input, Low Power Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . .

2581

LM358, LM258, LM2904, LM2904A, LM2904V, NCV2904 . .

Single Supply Dual Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2593

MC3403, MC3303 . . . . . . . . . . . . . .

Single Supply Quad Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2609

LM301A, LM201A . . . . . . . . . . . . . .

Non Compensated Single Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2617

TCA0372, TCA0372B . . . . . . . . . . .

1.0 A Output Current, Dual Power Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2625

LM833 . . . . . . . . . . . . . . . . . . . . . . . .

Low Noise, Audio Dual Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2637

MC33077 . . . . . . . . . . . . . . . . . . . . .

Low Noise Dual Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2645

MC33078, MC33079 . . . . . . . . . . . .

Low Noise Dual/Quad Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2661

MC33272A, MC33274A . . . . . . . . .

Single Supply, High Slew Rate, Low Input Offset Voltage Operational Amplifiers . . . . . . . . .

2677

MC34071, MC34071A, MC34072, MC34072A, MC34074, MC34074A, MC33071, MC33071A, MC33072, MC33072A, MC33074, MC33074A

Single Supply 3.0 V to 44 V Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2693

LM211, LM311 . . . . . . . . . . . . . . . . .

Single Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2717

NCS2200, NCS2201, NCS2202, NCS2203 . . . . . . . . . . . . . . . . . . . . .

Low Voltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2729

NCS2300, NCS2301, NCS2302, NCS2303 . . . . . . . . . . . . . . . . . . . . .

High Voltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2741

LM393, LM293, LM2903, LM2903V, NCV2903 . . . . . . . . . . . .

Low Offset Voltage Dual Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2757

LM339, LM239, LM2901, LM2901V, NCV2901, MC3302 . . .

Single Supply Quad Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2765

http://onsemi.com 9

Device Number

Function

Page

MC3423 . . . . . . . . . . . . . . . . . . . . . . .

Overvoltage Crowbar Sensing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2773

NCP3712ASNT1 . . . . . . . . . . . . . . .

Over Voltage Protected High Side Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2781

MC34161, MC33161 . . . . . . . . . . . .

Universal Voltage Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2789

NCP300, NCP301 . . . . . . . . . . . . . .

Voltage Detector Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2805

NCP304, NCP305 . . . . . . . . . . . . . .

Voltage Detector Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2829

MC34064, MC33064 . . . . . . . . . . . .

Undervoltage Sensing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2853

MC34164, MC33164 . . . . . . . . . . . .

Micropower Undervoltage Sensing Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2861

NCP803 . . . . . . . . . . . . . . . . . . . . . . .

Very Low Supply Current 3–Pin Microprocessor Reset Monitor . . . . . . . . . . . . . . . . . . . . . . .

2873

MAX809 Series, MAX810 Series .

Very Low Supply Current 3–Pin Microprocessor Reset Monitors . . . . . . . . . . . . . . . . . . . . . .

2881

NCP302, NCP303 . . . . . . . . . . . . . .

Voltage Detector Series with Programmable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2893

MAX707, MAX708 . . . . . . . . . . . . . .

mP Supervisory Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2921

MDC3105LT1 . . . . . . . . . . . . . . . . . .

Integrated Relay/Inductive Load Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2933

MDC3205 . . . . . . . . . . . . . . . . . . . . .

Integrated Relay/Solenoid Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2945

MC1413, MC1413B, NCV1413B . .

High Voltage, High Current Darlington Transistor Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2953

MC34271 . . . . . . . . . . . . . . . . . . . . .

Liquid Crystal Display and Backlight Integrated Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2961

MC33441 . . . . . . . . . . . . . . . . . . . . .

Electroluminescent Lamp Driver IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2973

CS1087 . . . . . . . . . . . . . . . . . . . . . . .

Vacuum Fluorescent Display Tube Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2985

CS1088 . . . . . . . . . . . . . . . . . . . . . . .


2997

CS1089 . . . . . . . . . . . . . . . . . . . . . . .


3005

CS8312 . . . . . . . . . . . . . . . . . . . . . . .

IGBT Ignition Predriver with Dynamic Current Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3017

CS7054 . . . . . . . . . . . . . . . . . . . . . . .

Low Side PWM FET Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3025

CS4124 . . . . . . . . . . . . . . . . . . . . . . .

High Side PWM FET Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3033

MC34152, MC33152, NCV33152 .

High Speed Dual MOSFET Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3041

MC34151, MC33151 . . . . . . . . . . . .

High Speed Dual MOSFET Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3050

MC33153 . . . . . . . . . . . . . . . . . . . . .

Single IGBT Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3058

CS1112 . . . . . . . . . . . . . . . . . . . . . . .

Quad Power Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3069

CS1107 . . . . . . . . . . . . . . . . . . . . . . .

Single Relay Driver IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3079

CS1108 . . . . . . . . . . . . . . . . . . . . . . .

Single Lamp Driver IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3082

CS299 . . . . . . . . . . . . . . . . . . . . . . . .

Darlington Lamp Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3085

CS8240 . . . . . . . . . . . . . . . . . . . . . . .

500 mA High Side (PNP) Driver with On–Chip Flyback Diode . . . . . . . . . . . . . . . . . . . . . . . . .

3089

NCV7601 . . . . . . . . . . . . . . . . . . . . .

Quad Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3094

CS2082 . . . . . . . . . . . . . . . . . . . . . . .

Dual Airbag Deployment ASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3100

MC1489, MC1489A . . . . . . . . . . . . .

Quad Line EIA–232D Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3109

MC1488 . . . . . . . . . . . . . . . . . . . . . . .

Quad Line EIA–232D Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3118

MC3488A . . . . . . . . . . . . . . . . . . . . .

Dual EIA–423/EIA–232D Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3124

MC26LS30 . . . . . . . . . . . . . . . . . . . .

Dual Differential (EIA–422–A)/Quad Single–Ended (EIA–423–A) Line Drivers . . . . . . . . . . .

3128

MC75172B, MC75174B . . . . . . . . .

Quad EIA–485 Line Drivers with Three–State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3140

MC1455, MC1455B . . . . . . . . . . . . .

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3151

MC1496 . . . . . . . . . . . . . . . . . . . . . . .

Balanced Modulators/Demodulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3159

MC33033 . . . . . . . . . . . . . . . . . . . . .

Brushless DC Motor Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3170

MC33035 . . . . . . . . . . . . . . . . . . . . .

Brushless DC Motor Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3193

MC33039 . . . . . . . . . . . . . . . . . . . . .

Closed Loop Brushless Motor Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3219

MC33030 . . . . . . . . . . . . . . . . . . . . .

DC Servo Motor Controller/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3224

MC3479 . . . . . . . . . . . . . . . . . . . . . . .

Stepper Motor Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3238

CS8441 . . . . . . . . . . . . . . . . . . . . . . .

Stepper Motor Driver with Divide by Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3246

CS4161 . . . . . . . . . . . . . . . . . . . . . . .

85 mA Dual H–Bridge Odometer Driver with Divide by Select and UVLO . . . . . . . . . . . . . . .

3251

TDA1085C . . . . . . . . . . . . . . . . . . . .

Universal Motor Speed Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3257

CS4121 . . . . . . . . . . . . . . . . . . . . . . .

Low Voltage Precision Air–Core Tach/Speedo Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3267

CS4122 . . . . . . . . . . . . . . . . . . . . . . .

Triple Air–Core Gauge Driver with Serial Input Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3277

CS8190 . . . . . . . . . . . . . . . . . . . . . . .

Precision Air–Core Tach/Speedo Driver with Return to Zero . . . . . . . . . . . . . . . . . . . . . . . . . .

3285

CS8191 . . . . . . . . . . . . . . . . . . . . . . .

Precision Air–Core Tach/Speedo Driver with Short Circuit Protection . . . . . . . . . . . . . . . . . . .

3295

http://onsemi.com 10

Device Number

Function

Page

CS4192 . . . . . . . . . . . . . . . . . . . . . . .

Single Air–Core Gauge Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3305

UAA2016 . . . . . . . . . . . . . . . . . . . . . .

Zero Voltage Switch Power Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3312

CS3341, CS3351, CS387 . . . . . . .

Alternator Voltage Regulator Darlington Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3319

CS1124 . . . . . . . . . . . . . . . . . . . . . . .

Dual Variable–Reluctance Sensor Interface IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3326

NCP5351 . . . . . . . . . . . . . . . . . . . . .

Synchronous Power MOSFET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3332

CS3361 . . . . . . . . . . . . . . . . . . . . . . .

Alternator Voltage Regulator FET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3339

MC34280 . . . . . . . . . . . . . . . . . . . . .

Power Supply & Management IC for Handheld Electronic Products . . . . . . . . . . . . . . . . . . . .

3345 3361

MC33680 . . . . . . . . . . . . . . . . . . . . .

Dual DC–DC Regulator for Electronic Organizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC33560 . . . . . . . . . . . . . . . . . . . . .

Power Management and Interface IC for Smartcard Readers and Couplers . . . . . . . . . . . . .

3374

NCN6000 . . . . . . . . . . . . . . . . . . . . .

Compact Smart Card Interface IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3397

NCN6010 . . . . . . . . . . . . . . . . . . . . .

SIM Card Supply and Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3432

NCN6011 . . . . . . . . . . . . . . . . . . . . .

Low Power Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3447

MC33170 . . . . . . . . . . . . . . . . . . . . .

RF Amplifier Companion Chip for Dual–Band Cellular Subscriber Terminal . . . . . . . . . . . . .

3457

NCS5000 . . . . . . . . . . . . . . . . . . . . .

Integrated RF Schottky Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3472

MDC5100 . . . . . . . . . . . . . . . . . . . . .

Antenna Switch Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3477

MDC5101 . . . . . . . . . . . . . . . . . . . . .

Antenna Switch Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3482

MDC5001 . . . . . . . . . . . . . . . . . . . . .

Low Voltage Bias Stabilizer with Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3488



CHAPTER 1 Family Tree and Selector Guide


ON Semiconductor’s Analog Integrated Circuits Power Management

Signal Conditioning

Battery Management

Operational Amplifiers

Lithium Battery Protection ICs

Comparators

Analog Switches & Multiplexers

Charge Controllers

Overvoltage Charge Protection

Interfaces

Special Functions

ASSP* for . . .

DC–DC Switching Data Transmission

Switching Regulators Switching Controllers

Display Drivers

Charge Pump Converters

Timers

Balanced Modulator/ Demodulator

Transistor Arrays

CPU DC–DC Controllers

Industrial / Appliances / Motor Control

Automotive

Networking / Computing

AC–DC Switching Voltage References Supervisory ICs Drivers

Switching Power Supply Controllers

Wireless & Portable

Off–Line Switching Controllers (with High Voltage Startup Circuit) Very High Voltage Off–Line Switching Regulators

Smart Cards

MOSFET/IGBT Drivers Power Factor Controllers Load/Relay Drivers Linear Voltage Regulators

*ASSP: Application Specific Standard Products

Display Drivers General Purpose Linear Voltage Regulators Smart Drivers Low Dropout Linear Voltage Regulators Dedicated Power Management Controllers

Application Specific Low Dropout Voltage Regulators


Signal Conditioning

Operational Amplifiers

Low Voltage Rail–to–Rail

MC33501 MC33502 MC33503 MC33201

MC33202 MC33204 NCS2001 NCS7101

Low Power

MC33171 MC33172 MC33174

High Current

MC33178

TCA0372 MC33178 MC33179

MC33179

General Purpose

5.0 V

Fixed 72 kHz

–40 to +85

Voltage Mode

D2PAK


General Purpose Buck Converters (For Non–Isolated Step–Down Application) (continued) Iout

Part No.

Vin

Vout

Frequency

Temp. Range (_C)

Control Method

Package

3.0 A

MC33166T

7.5 to 40 V

> 5.0 V

Fixed 72 kHz

–40 to +85

Voltage Mode

TO–220

3.0 A

MC33166TH

7.5 to 40 V

> 5.0 V

Fixed 72 kHz

–40 to +85

Voltage Mode

TO–220

3.0 A

MC33166TV

7.5 to 40 V

> 5.0 V

Fixed 72 kHz

–40 to +85

Voltage Mode

TO–220

3.0 A

MC34166D2T

7.5 to 40 V

> 5.0 V

Fixed 72 kHz

0 to 70

Voltage Mode

D2PAK

3.0 A

MC34166T

7.5 to 40 V

> 5.0 V

Fixed 72 kHz

0 to 70

Voltage Mode

TO–220

3.0 A

MC34166TH

7.5 to 40 V

> 5.0 V

Fixed 72 kHz

0 to 70

Voltage Mode

TO–220

3.0 A

MC34166TV

7.5 to 40 V

> 5.0 V

Fixed 72 kHz

0 to 70

Voltage Mode

TO–220

3.0 A

LM2576D2T–12

15 to 40 V

Fixed 12 V

Fixed 52 kHz

–40 to +125

Voltage Mode

D2PAK

3.0 A

LM2576T–12

15 to 40 V

Fixed 12 V

Fixed 52 kHz

–40 to +125

Voltage Mode

TO–220

3.0 A

LM2576TV–12

15 to 40 V

Fixed 12 V

Fixed 52 kHz

–40 to +125

Voltage Mode

TO–220

3.0 A

LM2576D2T–15

18 to 40 V

Fixed 15 V

Fixed 52 kHz

–40 to +125

Voltage Mode

D2PAK

3.0 A

LM2576T–15

18 to 40 V

Fixed 15 V

Fixed 52 kHz

–40 to +125

Voltage Mode

TO–220

3.0 A

LM2576TV–15

18 to 40 V

Fixed 15 V

Fixed 52 kHz

–40 to +125

Voltage Mode

TO–220

5.0 A

MC33167D2T

7.5 to 40 V

> 5.0 V

Fixed 72 kHz

–40 to +85

Voltage Mode

D2PAK

5.0 A

MC33167T

7.5 to 40 V

> 5.0 V

Fixed 72 kHz

–40 to +85

Voltage Mode

TO–220

5.0 A

MC33167TH

7.5 to 40 V

> 5.0 V

Fixed 72 kHz

–40 to +85

Voltage Mode

TO–220

5.0 A

MC33167TV

7.5 to 40 V

> 5.0 V

Fixed 72 kHz

–40 to +85

Voltage Mode

TO–220

5.0 A

MC34167D2T

7.5 to 40 V

> 5.0 V

Fixed 72 kHz

0 to 70

Voltage Mode

D2PAK

5.0 A

MC34167T

7.5 to 40 V

> 5.0 V

Fixed 72 kHz

0 to 70

Voltage Mode

TO–220

5.0 A

MC34167TH

7.5 to 40 V

> 5.0 V

Fixed 72 kHz

0 to 70

Voltage Mode

TO–220

5.0 A

MC34167TV

7.5 to 40 V

> 5.0 V

Fixed 72 kHz

0 to 70

Voltage Mode

TO–220


General Purpose Buck Controllers (For Non–Isolated Step–Down Application) Peak output to MOSFET

Part No.

Vin

Vref

1.0 A

CS51031YD8

4.5 to 16 V

1.25 V

1.0 A

CS51031GD8

4.5 to 16 V

1.0 A

CS51033YD8

1.0 A

CS51033GD8

Output Current

Frequency

Temp. Range (_C)

Control Method

Package

by External P MOSFET

max 700 kHz

–40 to +125

Voltage Mode

SO–8

1.25 V


max 700 kHz

–40 to +125

Voltage Mode

SO–8

3.3 V

1.25 V


max 700 kHz

–40 to +125

Voltage Mode

SO–8

3.3 V

1.25 V


max 700 kHz

0 to 70

Voltage Mode

SO–8

11.4 V to 12.6 V

0.985 V

by External N MOSFET

200 kHz

0 to 70

V2 Control

SO–8

Remark

CS5211 1.5 A

NCP1570 NCP5162

–

CS51411E

4.5 V to 40 V

1.276 V

1.5 A

260 kHz

–40 to +85

V2 Control

SO–8

Synchronization Pin

–

CS51411G

4.5 V to 40 V

1.276 V

1.5 A

260 kHz

0 to 70

V2 Control

SO–8

Synchronization Pin

–40 to +85

V2

Control

SO–8

Bias Pin

V2

–

CS51412E

4.5 V to 40 V

1.276 V

1.5 A

260 kHz

–

CS51412G

4.5 V to 40 V

1.276 V

1.5 A

260 kHz

0 to 70

Control

SO–8

Bias Pin

–

CS51413E

4.5 V to 40 V

1.276 V

1.5 A

520 kHz

–40 to +85

V2 Control

SO–8

Synchronization Pin

–

CS51413G

4.5 V to 40 V

1.276 V

1.5 A

520 kHz

0 to 70

V2 Control

SO–8

Synchronization Pin

–

CS51414E

4.5 V to 40 V

1.276 V

1.5 A

520 kHz

–40 to +85

V2 Control

SO–8

Bias Pin

V2

SO–8

Bias Pin

–

CS51414G

4.5 V to 40 V

1.276 V

1.5 A

520 kHz


0 to 70

Control

General Purpose Boost Converters (For Non–Isolated Step–Up Applications) (Can also be configured for Boost, Flyback, Forward) Internal Switch

Part No.

Vin

Vout

Frequency

Temp. Range (_C)

Package

1.5 A

CS5171ED8

2.7 V to 30 V

Programmable

Fixed 280 kHz

–40 to +85

SO–8

1.5 A

CS5171GD8

2.7 V to 30 V

Programmable

Fixed 280 kHz

0 to 70

SO–8

1.5 A

CS5172ED8

2.7 V to 30 V

Programmable

Fixed 280 kHz

–40 to +85

SO–8

Negative Feedback of CS5171

1.5 A

CS5172GD8

2.7 V to 30 V

Programmable

Fixed 280 kHz

0 to 70

SO–8


1.5 A

CS5173ED8

2.7 V to 30 V

Programmable

Fixed 560 kHz

–40 to +85

SO–8

1.5 A

CS5173GD8

2.7 V to 30 V

Programmable

Fixed 560 kHz

0 to 70

SO–8

1.5 A

CS5174ED8

2.7 V to 30 V

Programmable

Fixed 560 kHz

–40 to +85

SO–8


1.5 A

CS5174GD8

2.7 V to 30 V

Programmable

Fixed 560 kHz

0 to 70

SO–8


Remark

DC–DC Boost Converters (For Non–Isolated Step–Up Applications) Vin

Part No.

Vout

Switch

MC33466H–30LT1 MC33463H–30LT1

Fixed 3 V

MC33466H–33LT1 Fixed 3.3 V

SOT–89

VFM around 100 kHz

VFM around 100 kHz Fixed 50 kHz

I t Internal l

MC33463H–33KT1 MC33466H–50LT1


E t External l Fixed 5 V

MC33466H–50JT1 MC33463H–50KT1

–30 to +80

VFM around 100 kHz

Fixed 100 kHz E t External l

MC33466H–33JT1

MC33463H–50LT1

Package

Fixed 50 kHz I t Internal l

MC33463H–30KT1

MC33463H–33LT1

Temp. Range (_C)

Fixed 100 kHz E t External l

MC33466H–30JT1

0 9 to 8 0.9 8.0 0V

Frequency


I t l Internal


VFM around 100 kHz

Power Management

DC–DC Switching

Charge Pumps Converters

Unregulated Output Voltage

Inverter with No Enable

Inverter w/Enable

MAX828 MAX829

MAX1720


Charge Pump Converters

Output Voltage

Input Voltage Range (V)

Oscillator Frequency (kHz)

MAX828

Vout = –Vin or Vout = 2 Vin

1.5 → 5.5

MAX829


1.5 → 5.5

MAX1720


1.5 → 5.5

Output Current (Typ mA)

Part No.

25 25 25

Quiescent Supply Current* (Max µA @ 25_C)

Package

10 / 35

90

SOT–23–5

12

260

SOT–23–5

35

90

TSOP–6

*Measured at VDD = 5.0 V at 25_C and no load.


Features

with Enable

Power Management

DC–DC Switching

CPU DC–DC Controllers

Single Phase w/ DAC for 12 V Only CS5150H CS5151H CS5155H CS5156H CS5161H CS5165H CS5166H CS51312

Single Phase w/ DAC

Single Phase w/ DAC & VRef

CS5150H CS5151H CS5155H CS5156H CS5157H CS5158 CS5159 CS5160 CS5161 CS5165H CS5166H CS51311 MC33470

CS51313


Multi–Phase

CS5301 CS5302 CS5303 CS5305 CS5307 CS5308 CS5322 NCP5322A CS5323 CS5332

Power Management PWM: Pulse Width Modulation PFM: Pulse Frequency Modulation VFM: Variable Frequency Modulation

AC–DC Switching

Switching Power Supply Controllers (Non–Monolithic)

Fixed Frequency, PWM, Current Mode

Fixed Frequency, PWM, Voltage Mode

Single Ended

Double Ended

Double Ended

Single Ended

Standard

MC33060A MC34060A

TL494 TL594 SG3525A CS3524A CS51221 CS51227

High Frequency MC33023 MC34023 Programmable Sync

High Frequency

CS51220

MC33025 MC34025

MC33067 MC34067

High Frequency Standard

Standard

Resonant Mode

MC33025 MC34025

UC3842/43A, UC2842/43A UC3842/43B, UC2842/43B UC3844/45B, UC2844/45B CS2841B CS5124 CS5126

High Frequency MC34023 Low Power Standby MC44603A MC44604 Enhanced Protection MC44605 CS51021/2/3/4 Dual PWM CS5106


Secondary Side Controllers CS5101 NCP4300A

Enhanced Current–Mode PWM Controller Part No.

Package

CS51021AED16

CS51022AED16 16L SO Narrow

CS51023AED16

CS51024AED16

Features

• • • • • • • • • • • • •

Application

75 uA Max. Startup Current (Comparing to 0.5 ∼ 1 mA in UC384X) Fixed Frequency Current–Mode Control up to 1 MHz (500 kHz in UC384X) Input Voltage Monitor (Under/Over) Programmable Dual Threshold Current Sense for OCP (Fast and Slow) LEB (55 ns) Current Sense Programmable Slope Compensation Adjustable Soft Start

More Programmable and Enhanced Features to Replace th General G l Market M k t off UC384X the

Programmable Maximum Duty Cycle Sleep (CS51022/51024)/Bi–directional Sync (CS51021/51023) Options UVLO Options: O tions: (8.25/7.7 V) for CS51021/22/(13/7.7 V) for CS51023/24 Operating Junction Temperature Range –40_C to +150_C 50 ns Shutdown Propagation Delay 1 A FET Driver

Enhanced Voltage–Mode PWM Controller Part No.

CS51227ED8

CS51221ED16

CS51221EN16

Package

8L SO Narrow

16L SO Narrow

16L DIP

Features

• • • • • • • • •

Application

Fixed Frequency Voltage Mode Control with Feedforward Programmable Volt–Second Clamp Programmable Frequency (up to 1 MHx) 1 A FET Driving Capability Thermal Shutdown

DC/DC Converter to have Simple Solution with Feedforward Control Function in a Small SO–8 Package

75 µA, Maximum Startup Current 150 ns LEB for Over Current Protection Operate from 5 V Supply – 4.6 V UVLO With Enhanced Features in Addition to CS51227

• • • • •

Bi–directional Synchronization 3.3 V Reference Voltage Output P Programmable bl U Under d and dO Overvoltage lt M Monitor it Programmable Soft Start Hiccup Mode Fault Timing


When more Control Features and Flexibility are wanted

Synchronous Rectification PWM Controller with Auxiliary Output Part No.

CS5106LSW24

Package

24 Lead SSOP

Features

• • • • • • • • • •

Application

Integrated Bootstrap Controller Synchronous Drivers with Programmable Non–Overlap Time for Main Output Input OVLO/UVLO Output Undervoltage Protection with Timer Under and Overvoltage Shutdown Enable Lead

Full–Featured High Power Isolated DC/DC Converter with 2 Outputs

Master/Slave Clock Synchronous Frequency Range Detect +25%, –35% 20 mA 5 V Reference Output –40_C to +85_C Operating Temperature Range Auxiliary Drive for Output

Highly Integrated PWM Current–Mode Controller Part No.

Package

CS5124XD8 8L SO Narrow

CS5126XD8

Features

• • • • • • • • •

Application

Input UVLO Direct Optocoupler Interface Soft–Start Capacitor Pin LEB (Leading Edge Blanking) for Current Sense (130 ns) –40_C to +125_C Operating Junction Temperature Range Thermal Shutdown Sleep Mode On/Off Pin CS5124 is 400 kHz with Bias Pin for Startup Circuitry, 195 mV First Current Sense Threshold for Resistor Current Sensing CS5126 is 200 kHz with Sync Pin, 330 mV First Current Sense Threshold for Current Sense Transformer


Compact Sub 50 W Isolated DC/DC Flyback

PWM: Pulse Width Modulation PFM: Pulse Frequency Modulation VFM: Variable Frequency Modulation

Power Management

AC–DC Switching

Off–Line Switching Controllers (with High Voltage Startup Circuit)

Critical Conduction Mode Variable Frequency

Fixed Frequency, PWM

MC33364

Voltage Mode, Single Ended MC44608 Current Mode, Single Ended NCP1200 NCP1203


Off–Line Controllers (with High Voltage Start–up Circuit) Part No.

MC33364DR

MC33364D1

MC33364D2

MC44608P40

MC44608P75

MC44608P100

NCP1200P40

NCP1200D40

Package

SO–16

SO–8

SO–8

DIP–8

DIP–8

DIP–8

DIP–8

SO–8

Features

• • •

• • • • • • • • • • • • • • • • •

Application

Critical Conduction Mode Operation to Minimize Inductor Size No Startup Resistor, Lossless Off–Line Startup Optional/Adjustable Frequency Clamp to Limit EMI MC33364D: The Internal Frequency Clam Clamp can either Lengthened, Shorted or Eliminated by Biasing the Appropriate Pin MC33364D1: The Internal Frequency Clamp is Fixed at 6.9 µs (Typ) MC33364D2: There is No Internal Frequency Clamp

General High–Density Low–Cost AC/DC Application

Leading Edge Blanking (LEB) for Noise Immunity and Prevent False Triggering Input Under Voltage Lockout with Hysteresis (7.6 V/15 V Typ) Over Current Limitation, Thermal Shutdown Ability Restart Delay after Fault 40 kHz, 75kHz, 100 kHz Fixed PWM Frequencies for Different Suffixes Programmable Sleep Mode during Stand–By Operation Resistor Lossless Off–Line Startup No Startup Resistor, Input Under Voltage Lockout with Hysteresis Maximum Duty Cycle Limitation

General Application Requires Sleep Mode Output Power as 1 W

O Over Current C t Li Limitation, it ti O Over VCC P Protection t ti Over Temperature Protection with Hysteresis (130_C/160_C) Requires fewer External Components 40 kHz, 60 kHz, 100 kHz Fixed PWM Frequency Current–Mode Sleep Capability with Adjustable Peak Skipping Current for Low Level of Audible Noise to Save Power at No Load Direct Optocoupler Connection for Saving External Components Direct Line Powered with No Auxiliary Winding and No Startup Resistor are Needed Internal Output Short–Circuit Protection and LEB


Very Small Power Application (about 10 W) and needs Sleep Mode Function such as Battery Charger

PWM: Pulse Width Modulation PFM: Pulse Frequency Modulation VFM: Variable Frequency Modulation

Power Management

AC–DC Switching

Very High Voltage Off–Line Switching Regulators (Monolithic) (with On–Board Power Switch)

Fixed Frequency, PWM, Voltage Mode MC33363/A/B MC33365 MC33362 NCP1000 NCP1001 NCP1002 NCP1050 NCP1051 NCP1052 NCP1053 NCP1054 NCP1055


Very High Voltage Off–Line Switching Regulators with On–Chip Power Switch

Active On–Chip 250 V FET

MC33363A

Yes

Yes

700 V

0.9 A

7.5 Ω

14 W


MC33363B

Yes

Yes

700 V

0.72 A

15 Ω

8.0 W


MC33365

Yes

Yes

700 V

0.72 A

15 Ω

8.0 W


•

PWM, Fixed Frequency

Adjustable up to 300 kHz

DIP–16 SO–16WB

–25 to +125_C

• •


DIP–16 SO–16WB

–25 to +125_C

• •


DIP–16 SO–16WB

–25 to +125_C

• •


DIP–16 SO–16WB

–25 to +125_C

•

Voltage Mode PWM, Fixed Frequency Voltage Mode PWM, Fixed Frequency Voltage Mode PWM, Fixed Frequency Voltage Mode

NOTE: Typical output power is dependent upon line voltage range, heatsinking and ambient temperature.


Additional Features

Temperature Range

20 W

Package

4.4 Ω

Oscillator Frequency

0.9 A

Control Scheme

RDS(on) (Typ @ TJ = 255C)

500 V

Start–Up

Peak Switch Current

Yes

to 265 VAC See Note

Max Drain Voltage

120 VAC Operation

Max Output Power @ V in = 92 V

Power Switch MOSFET Integrated

MC33362

Rectified 85 to 276 VAC Line

Device

This monolithic high voltage switching regulator is specifically designed to operate from a rectified ac line voltage source. Included are an on–chip high voltage power switch, active off–line startup circuitry and a full featured PWM controller with fault protection.

Bulk Capacitor Voltage Sensing Capability to Sense an AC Line Brown–Out

Power Management

AC–DC Switching

Power Factor Controllers

Variable Frequency, Critical Conduction Mode

With Integrated Start–Up Circuit MC33368

Without Integrated Start–Up Circuit MC33262 MC33260


Power Factor Controllers

Device MC33260

MC33262

MC34262

MC33368

Operating Modes

• • •

• • • • • • • • •

Voltage Mode Follower Boost or Fixed Output

Switching Frequency Free to 500 kHz Fixed Clamp

Critical Conduction Mode

Current Mode Fixed Output Voltage

Free, no Frequency Clamp


Current Mode Fixed Output Voltage

Free, no Frequency Clamp


Current Mode Fixed Output Voltage Critical Conduction Mode

Free, Programmable Frequency Clamp

Features

• • • • • • • • • • • • • • • • • •

Synchronization Capability

Voltage Reference

Maximum Input Voltage

Temp Range

Package

None

16 V

–40_C to 105_C

PDIP–8 SOIC–8

2.5 V +/– 1.4%

30 V

–40_C to 105_C

PDIP–8 SOIC–8

2.5 V +/– 1.4%

30 V

0_C to 85_C

PDIP–8 SOIC–8

5.0 V +/– 1.5%

500 V

–25_C to 125_C

SOIC–16

Output Current Sense Output Overvoltage Detect Input Undervoltage Lockout Maximum On time Limit Output Current Sense Output Overvoltage Detect Input Undervoltage Lockout Zero Current Detect Output Current Sense Output Overvoltage Detect Input Undervoltage Lockout Zero Current Detect True Off–line Start–Up Output Current Sense Output Overvoltage Detect Input Undervoltage Lockout Zero Current Detect


Power Management

Voltage References

Shunt

Series

Fixed Output Standard

Precision

2.5 V Fixed Output

Programmable Output

Fixed Output

1.235 V

0.9 to 6 V

1.235 V

LM285–1.2 LM385–1.2

NCP100

LM385B–1.2

1.24 to 16 V 2.5 V LM285–2.5 LM385–2.5

Programmable Output

2.5 V

2.5 to 36 V

LM385B–2.5 CS1009

TL431A TL431B

TLV431A

2.5 to 36 V TL431


MC1403/B

Series Voltage References Package PDIP

Typical Quiescent Current (mA)

Part Number

Reference Voltage (V)

SO–8

Typical Temperature Coefficient (ppm/_C)

Tolerance +/– (%)

MC1403

2.500

1.0

10

1.200

√

√

0 to +70

MC1403B

2.500

1.0

10

1.200

√

√

–40 to +85

Operating Temperature Range (_C)

Shunt Voltage References

TSOP–5

LM285–1.2

1.235

1.0

80

0.010

√

√

–40 to +85

LM385–1.2

1.235

2.0

80

0.015

√

√

0 to +70

LM285–2.5

2.500

1.5

80

0.020

√

√

0 to +70

PDIP


TO–92

Minimum Operating Current (mA)

Part Number

Tolerance +/– (%)

SO–8

Typical Temperature Coefficient (ppm/_C)

Micro8

Package

Operating Temperature Range (_C)

LM385–2.5

2.500

3.0

80

0.020

√

√

0 to +70

LM385B–1.2

1.235

1.0

80

0.020

√

√

0 to +70

LM385B–2.5

2.500

1.5

80

0.020

√

√

0 to +70

CS1009

2.500

0.2

–

–

√

√

–40 to +105

NCP100

Adjustable 0.9 to 6 V

1.0

25

0.100

TLV431A


1.0

–

0.050

TL431C


2.2

50

0.500

√

√

√

√

0 to +70

√ √

–40 to +85

√

–40 to +85

TL431I


2.2

50

0.500

√

√

√

√

–40 to +85

TL431AC


1.0

50

0.500

√

√

√

√

0 to +70

TL431AI


1.0

50

0.500

√

√

√

√

–40 to +85

TL431BC


0.4

50

0.500

√

√

√

√

0 to +70

TL431BI


0.4

50

0.500

√

√

√

√

–40 to +85


Power Management Linear Voltage Regulators

General Purpose Linear Voltage Regulators

Fixed Voltage

Negative

Positive

Standard 100 mA

MC78L05A MC78L09A MC78L15A MC78L24A

MC78L08A MC78L12A MC78L18A

Precision 500 mA

MC78M05 MC78M08 MC78M12 MC78M18 MC78M24 3A

1.5 A

MC7805 MC7806 MC7809 MC7815 MC7824 LM340–12

MC78M06 MC78M09 MC78M15 MC78M20

MC7805.2 MC7808 MC7812 MC7818 LM340–5 LM340–15

MC78T05 MC78T12 LM323

MC78T08 MC78T15

500 mA

MC78M05A MC78M12A

MC78M08A MC78M15A

Standard

Precision

100 mA

MC79L05A MC79L15A MC79L24A

1.5 A

MC79L12A MC7905A MC79L18A MC7912A

MC7908A MC7915A

1.5 A 500 mA MC7806A MC79M05 MC79M08 MC7809A MC79M12 MC79M15 MC7815A 1.5 A MC7824A MC7905 MC7905.2 LM340A–12 MC7906 MC7908 MC7912 MC7915 3A MC7918 MC7924 MC78T05A MC78T12A MC78T15A LM323A

MC7805A MC7808A MC7812A MC7818A LM340A–5 LM340A–15

Adjustable Voltage Positive

Negative

Standard

Standard

100 mA

LM317L 500 mA

LM317M 1.5 A

LM317 3A

LM350


1.5 A

LM337

General Purpose Linear Voltage Regulators

√ √ √

√

5.0

1.7 V @ 40 mA

–5.0 V Version = –30 V –12 to –18 V Version = –35 V –24 V Version = –40 V

√

√

√

100 mA

LM317Lxx Series

√

4.0

1.9 V @ 100 mA

VI – VO = 40 V

√

√

500 mA

MC78Mxx Series

√

√

4.0

1.9 V @ 500 mA

5.0 to 18 V Version = 35 V 20 to 24 V Version = 40 V

√

√

500 mA

MC78MxxA Series

√

√

√

√ √

2.0

1.9 V @ 500 mA

5.0 to 18 V Version = 35 V 20 to 24 V Version = 40 V

√

√

500 mA

MC79Mxx Series

√

√

√ √

4.0

1.1 V @ 500 mA

–35 V

√

√

500 mA

LM317Mxx Series

√

√

4.0

2.1 V @ 500 mA

VI – VO = 40 V

√

√

√ √

500 mA

LM317MxxA Series

√

√

2.0

2.1 V @ 500 mA

VI – VO = 40 V

√

√

√

1.5 A

MC78xx Series

√

√

√ √ √ √ √ √

√

4.0

2.0 V @ 500 mA

5.0 to 18 V Version = 35 V 24 V Version = 40 V

√

√

1.5 A

MC78xxA Series

√

√

√ √ √ √ √ √

√

2.0

2.0 V @ 500 mA


√ 2.

√

√

√

√ √ √ √ √ √ √ √

‘xx’ indicates nominal voltage

1. Available in select packages only; contact your local ON Semiconductor sales office for information. 2. Available for select voltage options only; contact your local ON Semiconductor sales office for information.


20.0 V 24.0 V

√

√

18.0 V

MC79LxxA Series

12.0 V 15.0 V

√

√ √ √ √ √ 1.

√

8.0 V 9.0 V

√

5.2V 6.0 V

√

5.0 V

5.0 to 18 V Version = 30V 12 to 18 V Version = 35 V 24 V Version = 40 V

Adjustable

1.7 V @ 40 mA

TO–92 TO–220

5.0

DPAK

√

D2PAK SOT–223

Tolerance (%)

100 mA

Maximum Input Voltage (Vdc)

SOP–8

20.0 V 24.0 V

√ √ √ √ √

12.0 V 15.0 V

√

√

8.0 V 9.0 V

MC78LxxA Series

5.2V 6.0 V

100 mA

5.0 V

Drop Out Voltage (Typical)

Adjustable

Part Number

Positive

Output Current

Negative

Automotive Temperature Rating Available (–40 to +125_C)

Package 18.0 V

Nominal Output Voltage

√ √

√ 1.

√ √

√ √ √ √ √ √ 1. 1. 1. 1.

√ 1.

√ √ √ √ √

√

√

√ √

√ √ √ √ √ √ 1. 1.

√

General Purpose Linear Voltage Regulators (continued)

4.0

2.0 V @ 1.0 A

–5.0 to –18 V Version = –35 V –24 V Version = –40 V

√

√

2.0

2.0 V @ 1.0 A

–5.0 to –18 V Version = –35 V –24 V Version = –40 V

√ 4.

√

√

4.0

2.25 V @ 1.5 A

VI – VO = 40 V

√

√ √

√ √

4.0

2.2 V @ 1.5 A

VI – VO = 40 V

√

√ √

1.5 A

MC79xx Series

√

√ √ √ √

√ √ √

1.5 A

MC79xxA Series

√

√

√ √

1.5 A

LM317

1.5 A

LM337

3.0 A

LM323

√

√

4.0

2.0 V @ 3.0 A

20 V

√

3.0 A

LM323A

√

√

2.0

2.0 V @ 3.0 A

20 V

√

3.0 A

LM350

√

4.0

2.7 V @ 3.0 A

VI – VO = 35 V

3.0 A

MC78Txx Series

√

√

√ √

4.0

2.2 V @ 3.0 A


3.0 A

MC78TxxA Series

√

√

√ √

2.0

2.2 V @ 3.0 A


√

√

√ √

‘xx’ indicates nominal voltage

3. Available in select packages only; contact your local ON Semiconductor sales office for information. 4. Available for select voltage options only; contact your local ON Semiconductor sales office for information.


√

√ √ 3.

√

√

√

√

√

√ √

√ √

20.0 V 24.0 V

√

18.0 V

35 V

12.0 V 15.0 V

1.75 V @ 1.0 A

8.0 V 9.0 V

2.0

5.2V 6.0 V

√ √

5.0 V

√

TO–92 TO–220 Adjustable

LM340A–xx √ Series

DPAK

√

D2PAK SOT–223

35 V

√

Maximum Input Voltage (Vdc) SOP–8

1.75 V @ 1.0 A

20.0 V 24.0 V

4.0

18.0 V

√ √

12.0 V 15.0 V

√

8.0 V 9.0 V

√

5.2V 6.0 V

LM340–xx Series

5.0 V

1.5 A 1.5 A

Drop Out Voltage (Typical)

Positive

Part Number

Negative Adjustable

Output Current

Automotive Temperature Rating Available (–40 to +125_C)

Package Tolerance (%)


√ 3.

Power Management Linear Voltage Regulators

Low Dropout Linear Voltage Regulators

Iout = 80 mA MC78LC30 MC78LC33 MC78LC40 MC78LC50 Fixed Vout MC33761 NCP4561 NCP502 NCP512 NCP552 NCP553 NCP562 NCP563

Iout = 120 mA

Iout = 100 mA Fixed Vout

Fixed Vout

LM2931 LP2950 CS8221 CS9201 CS9202

MC78FC

Iout = 150 mA Fixed Vout CS8321 MC33263 MC78PC NCP551 NCP561 NCP500 NCP511 NCP5426

w/ Reset L4949 w/ Shutdown & Reset CS8311 CS8101 w/ Watchdog & Reset CS8151

Iout = 200 mA

Iout = 500 mA

Adjustable Vout CS8182

w/ Watchdog, Reset, Delay, & Shutdown

w/ Auxiliary Control

MC33565

CS8140 CS8141


CS5231–3

CS5233–3

Iout = 300 mA

Fixed Vout MC33275

Adjustable Vout LM2931

w/ Shutdown

w/ Shutdown

MC33375

LM2931 w/Shutdown & Error Detection LP2951

w/ Shutdown & Reset CS8120


Fixed Vout

with External Pass Transistor Fixed Vout MC78BC

Power Management Linear Voltage Regulators Low Dropout Linear Voltage Regulators (continued)

Iout = 750 mA

Iout = 3.0 A

Iout = 1.0 A

Fixed Vout

Fixed Vout

Fixed Vout

CS5203–3 CS5203A–2 CS5203A–3 CS5203A–5 CS5253B–8

CS5201–3 w/ Reset CS403

Adjustable Vout

w/ Reset & Delay

Iout = 5.0 A

Adjustable Vout

Fixed Vout MC34268 NCP1117

MC33269 NCP1117

CS5205–2 CS5205–3 CS5205–5

CS5207–2 CS5207–3

Fixed Vout

Fixed Vout

CS52015–3

CS5204–2 CS5204–3 CS5204–5

CS52015–1 Adjustable Vout


CS5204–1

CS5233–3


Adjustable Vout CS5207–1 CS5207A–1 CS5257A–1 Iout = 6.0 A

Iout = 4.0 A

Iout = 1.5 A

Adjustable Vout Fixed or Adjustable Vout

Fixed Vout

CS5205–1 CS5205A–1

CS5203–1 CS5203A–1 CS5253–1 Iout = 800 mA

Fixed Vout

Adjustable Vout

CS5201–1

CS8122 CS8126 CS8129

Iout = 7.0 A

Fixed Vout CS5206–3 CS5206–5 Adjustable Vout CS5206–1

Iout = 8.0 A

Adjustable Vout CS5208–1 CS5258–1

Low Dropout Voltage Regulators Input Voltage

MC33761

80 mA

MC78LCxx

80 mA, 80 mA

MC33762

√, √

√, √

√, √

80 mA

NCP512*

√ √ √

√ √

√

√

80 mA

NCP552*

√ √ √

√ √

√

√

80 mA

NCP4561

100 mA

MC33160

100 mA

CS9201

100 mA

CS9202

100 mA

CS8221

100 mA

CS8311

√

√

Min.

Max.

√

√

2.5

0.1 V @ 100 mA

–

10

√

External Power Transistor

1.5

0.16 V @ 80 mA

–

12

√

w/ ENABLE, Ultra Low Noise

2.5

0.22 V @ 10 mA

–

10

√ √

–

0.16 V @ 80 mA, 0.16 V @ 80 mA

–

12

√

2.5

250 mV @ 80 mA

–

6.0

√

w/ ENABLE

√

2.5

100 mV @ 10 mA

–

12

√

w/ ENABLE, Low IQ

1.5

0.16 V @ 80 mA

–

12

√

–

–

–

40

√

2.0

0.4 V @ 100 mA

6.0

26

√

No Cap, 74 V Load Dump Protection

2.0

–

4.5

26

√

No Cap, 74 V Load Dump Protection

2.0

0.4 V @ 100 mA

6.0

26

√

2.0

0.4 V @ 100 mA

–

26

√

√

5.

√ √

√

√

√

5.

√

√ √ √

5. Output voltages from 2.0 V to 6.0 V, in 0.1 V increments, are available on request. *Q2, 2001


SC–70 SOT–23 SOT–89 SO–8 SOIC(W) DIP–8 Micro8 DPAK D2PAK SOT–223 TO–92 TO–220 TSOP–5 TSSOP16 PDIP

80 mA

√

Drop Out Voltage

3.2 V 3.3 V 3.8 V 4.0 V 4.75 V 5V 8V 10 V 12 V See Note

MC78BCxx

2.85 V 3.0 V

–

2.7 V 2.8 V

Part Number

Adjustable 1.5 V 1.8 V 2.5 V

Output Current

Package

Tolerance (%)

Output Voltage

Additional Features

Very Low Quiescent Current √

Dual, w/ ENABLE, Ultra Low Noise

√

w/ ENABLE, Ultra Low Noise Regulator and Supervisory Circuit in SOP–16L and DIP–16 Packages

√

– w/ RESET and ENABLE, 60 V Load Dump Protection

Low Dropout Voltage Regulators (continued) Input Voltage Min.

Max.

√

2.0

0.4 V @ 100 mA

6.0

26

100 mA

CS8151C

√

1.0

0.4 V @ 100 mA

6.0

26

100 mA

CS8101

√

2.0

0.4 V @ 100 mA

6.0

26

√ √

100 mA

CS8271

–

0.4 V @ 100 mA

–

30

√

100 mA

L4949

√

1.0

0.2 V @ 50 mA

5.0

28

√

100 mA

LM2931/A

√

3.8 5.0

0.16 V @ 100 mA

–

40

√

√ √

√ √

–

5.0, 2.0

0.16 V @ 100 mA

–

40

√

√

√ √

–

√

–

√

100 mA

LM2931C/AC √

100 mA

LP2950C/AC

100 mA

LP2951C/AC

120 mA

MC78FCxx

150 mA

MC78PCxx

150 mA

MC33263

√

√

√

√

w/ WATCHDOG, RESET, WAKE UP & DELAY, 74 V Load Dump Protection

√

w/ WATCHDOG, RESET, WAKE UP & DELAY, 60 V Load Dump Protection

√

w/ RESET and ENABLE, 60 V Load Dump Protection √

√

Additional Features

w/ ENABLE Power–On Reset, Input Voltage Sense

√

√

√

1.0/ 0.5

0.38 V @ 100 mA

–

30

√

√

√

1.0/ 0.5

0.38 V @ 100 mA

–

30

√

√

2.5

0.5 V @ 40 mA

2.0

10

√

√

√

2.0

0.2 V @ 100 mA

–

8.0

√

w/ ENABLE

√

√

–

0.18 V @ 150 mA

–

12

√

w/ ENABLE, Ultra Low Noise

√

√ √


Drop Out Voltage


CS8151

2.85 V 3.0 V

100 mA

2.7 V 2.8 V

Part Number


Output Current

Package

Tolerance (%)

Output Voltage

√

√ √

√ √ √ √ √ √

6.



√ √ √

√ √

– –

Low Dropout Voltage Regulators (continued) Input Voltage

150 mA

NCP500

√ √

√

√

150 mA

NCP511

√ √ √

√ √

150 mA

NCP551

√ √ √

√ √

200 mA

MC33565

300 mA

MC33275

√

√

√

2.0

0.3 V @ 150 mA

–

26

√

√

2.5

0.165 V @ 150 mA

–

6.0

√

w/ Shutdown

√

√

√

–

0.170 V @ 150 mA

–

6.0

√

w/ Shutdown

√

√

√

2.0

44 mV @ 10 mA

–

12

√

w/ Shutdown

√

√

2.0

–

4.3

5.5

√

2.0

0.26 V @ 300 mA

–

12

√

300 mA

MC33375

√ √

√

√

√

2.0

0.26 V @ 300 mA

–

12

√

300 mA

CS8120

√

4.0

1.0 V @ 200 mA

–

26

√

500 mA

CS8140/1

√

4.0

1.25 V @ 500 mA

–

26

√

500 mA

CS5231–3

√

2.0

–

–

6

√

500 mA

CS5233–3

√

2.0

–

–

6

√

√



Min.

Max.


CS8321


150 mA

2.85 V 3.0 V

Drop Out Voltage

2.7 V 2.8 V

Part Number


Output Current

Package

Tolerance (%)

Output Voltage

√

Y

Additional Features

45 V Load Dump Protection

w/ Auxiliary Control √

√

√

√

–

√

w/ ENABLE √

√

w/ RESET and ENABLE, 60 V Load Dump Protection

√

√

w/ ENABLE, RESET and WATCHDOG, 60 V Load Dump Protection w/ Auxiliary Control w/ Auxiliary Control and Standby Input


750 mA

CS8122

√

2.0

0.35 V @ 500 mA

6.0

26

750 mA

CS8126–X

√

3.0

0.35 V @ 500 mA

6.0

26

√

750 mA

CS8129

√

3.0

0.35 V @ 500 mA

6.0

26

√

750 mA

CS403

√

5.0

1.4 V @ 750 mA

–

18

800 mA

MC33269

1.0

1.1 V @ 800 mA

–

20

√

√

√

800 mA

MC34268

1.4

1.1 V @ 800 mA

–

15

√

√

√

1.0 A

CS5201–1

1.0

1.0 V @ 1.0 A

–

7.0

√ √

√

–

1.0 A

CS5201–3

1.5

1.0 V @ 1.0 A

–

7.0

√ √

√

–

1.5 A

CS52015–1

1.0

1.05 V @ 1.5 A

–

7.0

√ √

√

–

1.5 A

CS52015–3

√

1.5

1.05 V @ 1.5 A

–

7.0

√ √

√

–

1.5 A

CS5233–3

√

2.0

–

–

6.0

√

√

√ √

√ √ √

√

√




Max.


Min.

2.85 V 3.0 V

Drop Out Voltage

2.7 V 2.8 V

Part Number


Output Current

Package

Tolerance (%)

Output Voltage

√

Additional Features

√

w/ Delayed RESET, 60 V Load Dump Protection

√


√


√

w/ RESET

√

– For SCSI–2 Active Termination

w/ Auxiliary Control and Standby Input


CS5203–3

3.0 A

CS5203A–X

3.0 A

CS5253–1

3.0 A

CS5253B–8

4.0 A

CS5204–X

4.0 A

CS5204–2

5.0 A

CS5205–X

5.0 A

CS5205–2

5.0 A

CS5205A–1

√

6.0 A

CS5206–X

√

7.0 A

CS5207–1

√

7.0 A

CS5207–2

√ √ √

√

√

√ √ √

√

√

√ √

√

√

√

√

√

√

Drop Out Voltage

Min.

Max.

1.5

1.2 V @ 3.0 A

–

7.0

√

1.5

1.15 V @ 3.0 A

–

7.0

√

1.0

1.05 V @ 3.0 A

–

17

√

1.0

0.4 V @ 3.0 A

–

6.0

√

w/ Control and Sense

1.5

0.4 V @ 3.0 A

–

6.0

√

–

1.0

1.1 V @ 4.0 A

–

17

√

√

–

2.0

1.1 V @ 4.0 A

–

17

√

√

–

1.0

1.2 V @ 5.0 A

–

17

√

√

–

2.0

1.2 V @ 5.0 A

–

17

√

√

–

1.0

1.15 V @ 5.0 A

–

17

√

√

–

1.0

1.3 V @ 6.0 A

–

17

√

√

–

1.5

1.4 V @ 7.0 A

–

17

√

–

2.0

1.45 V @ 7.0 A

–

17

√

–




3.0 A

√

Package

Tolerance (%)

CS5203–1


3.0 A

2.85 V 3.0 V

Part Number


Output Current

2.7 V 2.8 V

Output Voltage

√

Additional Features

– –

√

–

Low Dropout Voltage Regulators (continued)

Tolerance (%)

Max.

7.0 A

CS5207–3

2.0

1.4 V @ 7.0 A

–

17

7.0 A

CS5207A–1

√

1.5

0.96 V @ 7.0 A

–

6.0

7.0 A

CS5257A–1

√

1.5

0.35 V @ 7.0 A

–

6.0

8.0 A

CS5208–1

√

1.5

0.96 V @ 8.0 A

–

8.0 A

CS5258–1

√

1.5

0.4 V @ 8.0 A

–


Min.

2.85 V 3.0 V

Drop Out Voltage

2.7 V 2.8 V

Part Number


Output Current

√



Package SC–70 SOT–23 SOT–89 SO–8 SOIC(W) DIP–8 Micro8 DPAK D2PAK SOT–223 TO–92 TO–220 TSOP–5 TSSOP16 PDIP

Input Voltage

Output Voltage

√

Additional Features

√

–

√

–

√


6.0

√

–

6.0

√


√

Power Management

Linear Voltage Regulators

Application Specific Low Dropout Voltage Regulators

Wireless & Portable

Network Interface Cards (NIC) & PCI Cards w/ Auxiliary Input

5 Outputs MC33765

Iout = 200 mA

Computing

Dual LDO Controller for Graphic Cards MC33567

Dual

MC33565 CS5231

MC33762 (80 mA, 80 mA) Iout = 500 mA Audio Amp NCP2860

SCSI Applications MC34268

CS5233–3 CS5231–3

Iout = 1.5 A MC33566 CS5233–3


Wireless Portable

Min.

Max.

–

0.16 V @ 80 mA, 0.16 V @ 80 mA

–

12

3.0

0.17 V @ 150 mA

3.0

5.3

√, √

√

DIP–8 Micro8 DPAK D2PAK SOT–223 TO–92 TO–220 TSSOP16 PDIP

Drop Out Voltage

Package SOT–23 SOT–89 SO–8 SOIC(W)

MC33765

√, √

Tolerance (%)

–

√, √

3.2 V 3.3 V

MC33762

Input Voltage

3.0 V

80 mA, 80 mA

2.8 V

Part Number

2.85 V

Output Current


Output Voltage

√

Additional Features

Dual, Ultra Low Noise, 1 V ON/OFF Control, No External Cap √

5 Outputs, Ultra Low Noise

NIC & PCI Cards

Drop Out Voltage

Min.

Max.

200 mA

MC33565

√

2.0

–

4.3

5.5

√

500 mA

CS5231–3

1.2 A

MC33566

√

2.0

–

–

6.0

√

√

–

–

4.35

5.5

1.5 A

CS5233–3

√

2.0

–

–

6.0

DIP–8 Micro8 DPAK D2PAK SOT–223 TO–92 TO–220 TSSOP16 PDIP

Part Number

Package SOT–23 SOT–89 SO–8 SOIC(W)

Output Current

Tolerance (%)

Input Voltage

Adjustable 1.5 V 1.8 V 2.5 V 2.8 V 2.85 V 3.0 V 3.2 V 3.3 V

Output Voltage

Additional Features


√

√


√


√


Computing

–

MC33567–1

–

MC33567–2

–

MC33567–3

√ √ √ √, √ √

√

Package SOT–23 SOT–89 SO–8 SOIC(W) DIP–8 Micro8 DPAK D2PAK SOT–223 TO–92 TO–220 TSSOP16 PDIP

MC34268

Input Voltage Tolerance (%)

800 mA

2.8 V 2.85 V 3.0 V 3.2 V 3.3 V

Part Number

2.525 V

Output Current

Adjustable 1.2 V 1.515 V 1.818 V 2.3 V

Output Voltage Drop Out Voltage

Min.

Max.

1.4

1.1 V @ 800 mA

–

15

√

2.5

–

–

12.5

√

Dual, External Pass Transistor

–

–

–

–

√


–

–

–

–

√



√

√

Additional Features

For SCSI–2 Active Termination

Power Management Application Specific Low Dropout Voltage Regulators Automotive

Iout = 100 mA

Iout = 150 mA

Iout = 300 mA

Fixed Vout

Fixed Vout

Fixed Vout

LM2931 CS9202

CS9201 CS8221

w/ Reset


CS8321

w/ Reset & Delay

NCV8501 NCV8502 NCV8508

L4949

CS8122 CS8126


Iout = 200 m A Fixed Vout

CS8151 Fixed Vout, w/ Reset, Power Warning

LM2931

Adjustable Vout CS8182

MC33160

Adjustable Vout

CS8129

CS8183 CS8363 CS8361

Duals Dual w/ Enable CS8147 (500 mA, 70 mA) CS8156 (750 mA, 100 mA) CS8161 (400 mA, 200 mA) CS8183 (200 mA, 200 mA) CS8281 (250 mA, 100 mA) CS8371 (1 A, 250 mA) CS8391 (250 mA, 100 mA) CS8481 (250 mA, 100mA)

Iout = 500 mA

CS8311

w/ Watchdog & Reset

MC34160

Dual

CS403

CS8120

Single CS8182

w/ Reset

w/ Shutdown & Reset

Reset & Monitors

Tracking

w/ Shutdown

w/ Watchdog, Reset, Delay, & Shutdown CS8140 CS8141

CS8271


Dual w/ Enable & Reset CS8361 (250 mA, 100 mA) CS8363 (250 mA, 100 mA)

Automotive Output Voltage

Input Voltage

√

–

–

–

40

100 mA

CS9201

√

2.0

0.4 V @ 100 mA

6.0

26

√

No Cap

100 mA

CS9202

2.0

0.4 V @ 100 mA

4.5

26

√

No Cap

100 mA

CS8221

2.0

0.4 V @ 100 mA

6.0

26

√

100 mA

CS8311

2.0

0.4 V @ 100 mA

–

26

√

100 mA

CS8151

√

2.0

0.4 V @ 100 mA

6.0

26

√

100 mA

CS8101

√

2.0

0.4 V @ 100 mA

6.0

26

√ √

100 mA

CS8271

–

0.4 V @ 100 mA

–

30

√

100 mA

L4949

1.0

0.2 V @ 50 mA

5.0

28

√

√ √ √

√ √


SOT–23 SOT–89 SO–8 SOIC(W) DIP–8 Micro8 DPAK D2PAK SOT–223 TO–92 TO–220 TSSOP16 PDIP

MC33160

Tolerance (%)

100 mA

14.0 V

Max.

12 V

Min.

8V 10 V

Drop Out Voltage

3.8 V 4.0 V 4.75 V 5V

Part Number


Output Current

Package Additional Features

Regulator and Supervisory Circuit in SOP–16L and DIP–16 Packages

√

– w/ RESET and ENABLE, 60 V Load Dump Protection

√

√

√

√

w/ WATCHDOG, RESET, WAKE UP and DELAY, 74 V Load Dump Protection uPower w/ RESET and ENABLE, 60 V Load Dump Protection

√ uPower with ENABLE √

Power–On Reset, Input Voltage Sense

Automotive (continued)

–

40

√

√ √

√ √


100 mA

LM2931C/AC

5.0, 2.0

0.16 V @ 100 mA

–

40

√

√

√ √


150 mA

CS8321

√

2.0

0.3 V @ 150 mA

–

26

√

√

uPower w/ 45 V Load Dump Protection

300 mA

CS8120

√

4.0

1.0 V @ 200 mA

–

26

√

√

√

√

w/ RESET and ENABLE, 60 V Load Dump Protection

500 mA

CS8140/1

√

4.0

1.25 V @ 500 mA

–

26

√

√

√

w/ ENABLE, RESET and WATCHDOG, 60 V Load Dump Protection

750 mA

CS8122

√

2.0

0.35 V @ 500 mA

6.0

26

750 mA

CS8126–1

√

3.0

0.35 V @ 500 mA

6.0

26

√

750 mA

CS8129

√

3.0

0.35 V @ 500 mA

6.0

26

√

√



0.16 V @ 100 mA

12 V

3.8, 5.0

√

See Note

LM2931/A

10 V

Max.

8V

Min.

3.3 V

100 mA

Package

Drop Out Voltage

3.8 V 4.0 V 4.75 V 5V

Part Number

Adjustable 1.5 V 1.8 V 2.5 V 2.8 V 2.85 V 3.0 V 3.2 V

Output Current

Input Voltage Tolerance (%)

Output Voltage

√

Additional Features

√


√


√



2.0

0.4 V @ 100 mA, 0.4 V @ 250 mA

6.0

26

100 mA, 250 mA

CS8363

√

2.0

0.4 V @ 100 mA, 0.4 V @ 250 mA

6.0

250 mA, 100 mA

CS8481

√

3.0

–, 0.4 V @ 100 mA

250 mA, 100 mA

CS8391

√, √

3.0

250 mA, 100 mA

CS8281

√, √

400 mA, 200 mA

CS8161

√

500 mA, 70 mA

CS8147

√

√

√

√

√

√

Tolerance (%)

√

12 V

CS8361

See Note

100 mA, 250 mA

10 V

Max.

8V

Min.

3.8 V 4.0 V 4.75 V 5V

Drop Out Voltage

2.85 V 3.0 V 3.2 V 3.3 V

Part Number

Adjustable 1.5 V 1.8 V 2.5 V 2.8 V

Output Current

Input Voltage

Package SOT–23 SOT–89 SO–8 SOIC(W) DIP–8 Micro8 DPAK D2PAK SOT–223 TO–92 TO–220 TSSOP16 PDIP

Output Voltage

√

Dual, uPower w/ RESET and ENABLE

26

√

Dual, uPower w/ RESET and ENABLE

–

30

√

Dual, w/ ENABLE

0.4 V @ 250 mA, 0.4 V @ 100 mA

–

45

√

Dual, w/ ENABLE

3.0

0.4 V @ 250 mA, 0.4 V @ 100 mA

6.0

26

√

Dual, w/ ENABLE

5.0, 2.0

0.35 V @ 400 mA, 0.35 V @ 200 mA

6.0

26

√

Dual, w/ ENABLE

5.0, 3.0

0.5 V @ 500 mA, 1.5 V @ 70 mA

6.0

26

√

Dual, w/ ENABLE


√

Additional Features


CS8371

√

√

Min.

Max.

5.0, 2.0

0.6 V @ 750 mA, 0.6 V @ 100 mA

6.0

26

√

Dual, w/ ENABLE

5.0, 5.0

1.5 V @ 1.0 A, 2.5 V @ 250 mA

–

16

√

Dual, Independent ENABLEs, NO CAP



1.0 A, 250 mA

√

Package

Drop Out Voltage

Tolerance (%)

√

12 V

CS8156

See Note

750 mA, 100 mA

3.8 V 4.0 V 4.75 V 5V

Part Number


Output Current

10 V

Input Voltage

8V

Output Voltage

Additional Features

Power Management

Supervisory ICs

Power Supply Protection

CPU Monitoring / Portable System Protection Undervoltage Sensing with Reset

Programmable Threshold

without Delay MC3423 NCP3712

NCP300/1 NCP304/5 MC33064 MC33164

Programmable Voltage Monitor (Over, Under, Window) MC33161

with Delay NCP302/3 MAX707 MAX708 Overvoltage Protection NCP345


NCP803 MAX809 MAX810

Supervisory

Typical Threshold Voltage (Vth) (V)

Supply Voltage Range (V)

Typical Supply Current (µA)

MAX809

4.63, 4.38, 4.00, 3.08, 2.93, 2.63 *

1.0 to 5.5

24

60

–

–40 to +85

SOT23

3–Pin Microprocessor Reset Monitors

240 msec

MAX810

4.63, 4.38, 3.08, 2.93, 2.63 *

1.0 to 5.5

24

60

–

–40 to +85

SOT23

3–Pin Microprocessor Reset Monitors

240 msec

MC33064

4.60

1.0 to 6.5

390

500

20

–40 to +85

SO–8, Micro8, TO–92

Undervoltage Sensing Circuit

Ext. Capacitor Dependent

MC34064

4.60

1.0 to 6.5

390

500

20

0 to +70


Undervoltage Sensing Circuit


MC33161

1.27

2.0 to 40 (Pos Sensing) 4.0 to 40 (Neg Sensing)

560

900

25

–40 to +85

SO–8, DIP–8

Universal Voltage Monitor


MC34161

1.27

2.0 to 40 (Pos Sensing) 4.0 to 40 (Neg Sensing)

560

900

25

0 to +70

SO–8, DIP–8

Universal Voltage Monitor


MC33164

2.71 (Vin Increasing) 2.65 (Vin Decreasing)

1.0 to 10

24

40

60

–40 to +125


Micropower Undervoltage Sensing Circuits


MC34164

2.71 (Vin Increasing) 2.65 (Vin Decreasing)

1.0 to 10

24

40

60

0 to +70


Micropower Undervoltage Sensing Circuits


MC3423

2.6

4.5 to 40

6.0 mA

10 mA

–

0 to +70

SO–8, DIP–8

Overvoltage Crowbar Sensing Circuit

0.5 µsec

NCP300/1

0.9, 1.8, 2.0, 2.7, 3.0, 4.5, 4.7

0.8 to 10

0.20 to 0.34*

1.2 to 1.4*

45 to 235 Depends on Threshold Voltage

–40 to +125

TSOP–5

Voltage Detector Series NCP300–CMOS, NCP301–Open Drain

High to Low 45–97* µsec Low to High 77–130* µsec

Description

Maximum Supply Current (µA)

Threshold Hysteresis (Typ) (mV)

Operating Temp. Range (°C)

Package

Description

*Voltages from 1.6 to 4.9 V by steps of 0.1 V are available upon request.


Time Delay (Typ)

Supervisory (continued) Typical Supply Current (µA)

Maximum Supply Current (µA)

Threshold Hysteresis (Typ) (mV)

Operating Temp. Range (°C)

Package

Description

1.2 to 1.4*


–40 to +125

TSOP–5

Voltage Detector Series with Programmable Delay NCP302–CMOS, NCP303–Open Drain


0.8 to 1.1*

3.0 to 3.9*


–40 to +125

SC–82AB

Voltage Detector Series NCP304–CMOS, NCP305–Open Drain

High to Low 10–18* µsec Low to High 6–21* µsec

750

1000

100

–40 to +85

TSOP–5

Overvoltage Protection IC

10 µsec

Typical Threshold Voltage (Vth) (V)

Supply Voltage Range (V)

NCP302/3

0.9, 1.8, 2.0, 2.7, 3.0, 4.5, 4.7

0.8 to 10

0.20 to 0.34*

NCP304/5

0.9, 1.8, 2.0, 2.7, 3.0, 4.5, 4.7

0.8 to 10

NCP345

6.85

3.0 to 25

Description

*Depends on the voltage threshold of the part


Time Delay (Typ)

Power Management

Drivers

Load / Relay Drivers MDC3105 MDC3205

Display Drivers

MC1413 LCD

EL Lamp Driver

MC34271 MOSFET / IGBT Drivers

IGBT Ignition Pre–driver with Current Regulation

1.5 A Peak Drive Current

2 A Peak Drive Current

CS8312 Dual Drivers Low Side PWM FET Controller CS7054

High Side PWM FET Controller CS4124

Non–Inverting Output MC33152 MC34152

Dedicated Drivers

Single Driver Inverting Output MC33153 (2 A Sink, 1 A Source)

Inverting Output MC33151 MC34151


MC33441

VFD Driver CS1087 CS1088 CS1089

Triac Controllers (Zero Voltage Switch Drivers) UAA2016

MOSFET/IGBT Drivers

Part No.

Configuration

Peak Output Current (A)

Output Resistance (RH/RL) (Max Ω @ 25_C)

Max Supply Voltage (V)

Input/Output Delay (tD1, tD2)* (nsec)

Package

CS4124

High–Side PWM FET Controller

0.300

–

30

1000/1000

DIP–16

CS7054

Low–Side PWM FET Controller

0.400

–

30

1000/1000

DIP–14

CS8312

IGBT Ignition Pre–Driver with Current Regulation

5 mA

–

12

30/30 (µs)

DIP–8, SO–8

MC33153

Single, Inverting Protection Circuits for IGBTs

1.0 A (source) 2.0 A (sink)

– –

20

300/300

DIP–8, SO–8

MC33151

Dual, Inverting Extended Operating Temp.

1.5

–

20

100/100

DIP–8, SO–8

MC34151

Dual, Inverting

1.5

–

20

100/100

DIP–8, SO–8

MC33152

Dual, Non–Inverting Extended Operating Temp.

1.5

–

20

120/120

DIP–8, SO–8

MC34152

Dual, Non–Inverting

1.5

–

20

120/120

DIP–8, SO–8

*tD1 = delay time from input low–to–high transition to output transition. tD2 = delay time from input high–to–low transition to output transition.


Power Management

Smart Drivers

Low Side Driver

High Side Driver

Dual H–Bridge Driver CS3701

CS8240 Quad w/ SPI CS1112

Hex w/ SPI CS76113 CS76114

Single w/o SPI CS1107 CS1108


SQUIB Driver CS2082

Smart Drivers (High–Side, Low–Side & H–Bridge)

CS76113/4

Low–Side Hex Power Output Driver

CS8240

High–Side Driver

√

√

√

500 mA 0.75 Ω

√

√

√

√

√

√ √

√

√

√

√

√

√

√

√

√

√

√

500 mA

√

√

√

√

√

√

√

√

Peak Transient

Configurable Dual H–Bridge Driver

√

√

√

Low Duty Cycle Over Current Mode

CS3701

√ 1.0 Ω

√

Over Temperature

350 mA

Low–Side Quad Power Output Driver

√

Over Voltage

Low–Side Single Lamp Driver

CS1112

√

Current Limit

CS1108

√

Power On Reset

350 mA

Open Load Detection

Low–Side Single Relay Driver

Protection

Undervoltage Lockout

CS1107

RDS(on) @ 25_C

Fault Reporting

Current

Serial Interface

Description

Parallel Inputs

Number

Features

Active Output Clamp

Output On–Chip Flyback Diode

Part

√

√

40 V

√

√

40 V

√

60 V

√

45 V

√

45 V

√ √

60 V

Squib Drivers

√

√

√

√

√

√

√

√

√

√


Peak Transient

Over Temperature

750 mΩ

Current Limit

Dual

Power On Reset

2

Serial Interface

CS2082

Safing Sensor Detection

RDS(on) @ 25_C

Short to Battery Monitor

Loop

Short to Ground Monitor

Number of Outputs

Squib Resistance Measurement

Part Number

Protection

Firing Potential Monitor

Features Battery Potential Monitor

Output

60 V

Power Management

Dedicated Power Management Controllers

DC–DC Converters for PDAs / Electronic Organizers

Power Management & Interface IC for Smart Card Systems MC33560 NCN6000

with Synchronous Rectification

Level Shifters for Smartcard & SIM Interface

RF Power Management

NCN6010 NCN6011

MC34280 MC33680 Power Management Controllers for RF Power Amplifiers

Antenna Switch Controller MDC5100 MDC5101

Multi–Output LDO Voltage Regulator for Cellular Phones Dual Band GaAs P.A.

MC33765 MC33762

Bias Stabilizer

MC33170

MDC5001 RF Signal Detection NCS5000


MC33035

10 – 40

10 – 30

√

√

√

60_/300_ and 120_/240_

Brake Input

√

Separate Drive VC

√

FAULT Output

√

Error Amplifier

–

6.25 V Referenc ce Output

10 – 30

Open Collector (Top)

Fwd/Rev Control

MC33033

Totem Pole (Bottom)

VC

Output Enable

VCC

Sensor Electrical Phasing

Device

Internal Therma mal Shutdown

Output Drivers


Operating Voltage Range (V)

Current Sense e put(s) Comparator Inp

Brushless DC Motor Controllers

Package

√

√

√

√

Noninv. Only

√

–

–

–

DIP–20, SO–20L

√

√

√

√

Noninv. and Inv.

√

√

√

√

DIP–24, SO–24L

Air Core Motor Drivers/Gauge Drivers Gauges Driven

Input

Part Number

Major

CS4121

1

CS4122

1

CS8190

1

√

CS8191

1

√

Minor

Freq.

PWM

Output SPI

√ √

2

√

Features

Current

Method

33 mA

Differential

80 mA

Differential

33 mA

Differential

55 mA

Differential

Return to Zero

UVLO

Protection Regulator Output

Current Limit

Over Voltage

√

√ √

√

Over Temp.

60 V

√

√ √

Peak Transient

√

18 V

√

60 V

√

60 V

Stepper Motor Drivers/Odometer Drivers Input

Modes

Output

Features

Part Number

Sine

Square

+1

+2

Current

Method

UVLO

CS4161

√

√

√

√

85 mA

Differential

√

CS8441

√

√

√

√

85 mA

Differential


Buffered Speed Output

Protection On–Chip Flyback Diodes

Current Limit

Over Voltage

Peak Transient

√

√

√

60 V

√

√

√

60 V

Interfaces

Transistor Arrays

Data Transmission

Display Drivers

MC1413 EL Lamp Driver MC33441 Receivers

Drivers

SCSI LCD

RS–232

RS–232

MC1489/A

MC1488 MC3488A

Voltage Regulator

MC34271

MC34268

VFD CS1087 CS1088 CS1089

RS–422/3 MC26LS30

RS–485 MC75172B MC75174B


Data Transmission Line Receivers – EIA Standard S = Single Ended D = Differential S

Type of Output

tprop Delay Time Max (ns)

Party Line Operation

Strobe or Enable

Power Supplies (V)

Device

Suffix/ Package

R (Note 11.)

85

–

–

+5.0

MC1489 MC1489A

DIP–16, SO–16

Receivers Per Package

Companion Drivers

4

MC1488 MC14C88B

Comments EIA–232–D

11. R = Resistor Pull–up, TP = Totem–pole output.

Line Drivers – EIA Standard Output Current Capability (mA)

tprop Delay Time Max (ns)

S = Single Ended D = Differential

Party Line Operation

Strobe or Enable

Power Supplies (V)

Device

85

35

D

√

√

+5.0

MC75174B MC75172B

SO–20L

10

350

S

–

±9.0 to ±12

MC1488

DIP–8, SO–8

60

300

S/D

±5.0

MC26LS30

SO–16

Input Capability

Propagation Delay Time Max (µs)

Output Clamp Diode

Off State Voltage Max (V)

Device

Drivers Per Package

1.0

√

50

MC1413B

7

EIA–422 √ EIA–423 –

Suffix/ Package

Receivers Per Package

Companion Drivers

4

–

EIA–485

MC1489 MC1489A

EIA–232–D

–

EIA–422 or EIA–423 Switchable

4 (423) 2 (422)

Comments

Peripheral Drivers Output Current Capability (mA) 500

TTL, 5.0 V CMOS


Suffix/ Package

Logic Function

DIP–16, SO–16

Invert

Special Functions

Balanced Modulator/Demodulator

Timers MC1455

MC1496


Application Specific Standard Product

Smart Cards

Industrial / Appliance / Motor Control



Wireless & Portable

Automotive

Application Specific Standard Products

Industrial / Appliance / Motor Control

Motor Control

Load / Relay Drivers MDC3105 MDC3205

MC1413 Industrial

Brushless DC Motor Control Brushless DC Motor Controllers MC33033 MC33035 Closed Loop Brushless Motor Adapter MC33039

Stepper Motor Driver

DC Brush Motor Control

Air Core Motor Driver CS4121 CS4122 CS8190 CS8191 CS4192

MC3479 CS8441 CS4161

w/ External MOSFET CS4124 CS7054 w/ Built–In H–Bridge Driver

DC Motor Driver AC Brush Triac Controller (Universal Motor)

CS3701

MC33030

TDA1085C


Triac Controllers (Zero Voltage Switch Drivers) UAA2016


Automotive

Smart Drivers

VFD Drivers

Sensor Interface

CS1087 CS1088 CS1089

Variable – Reluctance

Low Side Driver

Dual H–Bridge Driver

CS1124 CS3701 Gauge Drivers

Alternator Voltage Regulator FET Driver

CS4121 CS4122 CS8190 CS8191 CS4192

CS3341 CS3351 CS3361 CS387

Quad w/ SPI CS1112 Single w/o SPI Odometer Driver CS4161 CS8441

CS1107 CS1108 CS299 Hex w/ SPI

IGBT Ignition Predriver

CS76113 CS76114

CS8312 Quad Driver NCV7601


High Side Driver CS8240

SQUIB Driver CS2082

Smart Drivers (High–Side, Low–Side & H–Bridge)

CS76113/4

Low–Side Hex Power Output Driver

CS8240

High–Side Driver

√

√

√

500 mA 0.75 Ω

√

√

√

√

√

√ √

√

√

√

√

√

√

√

√

√

√

√

500 mA

√

√

√

√

√

√

√

√

Peak Transient

Configurable Dual H–Bridge Driver

√

√

√

Low Duty Cycle Over Current Mode

CS3701

√ 1.0 Ω

√

Over Temperature

350 mA

Low–Side Quad Power Output Driver

√

Over Voltage

Low–Side Single Lamp Driver

CS1112

√

Current Limit

CS1108

√

Power On Reset

350 mA

Open Load Detection

Low–Side Single Relay Driver

Protection


CS1107

RDS(on) @ 25_C

Fault Reporting

Current

Serial Interface

Description

Parallel Inputs

Number

Features

Active Output Clamp

Output On–Chip Flyback Diode

Part

√

√

40 V

√

√

40 V

√

60 V

√

45 V

√

45 V

√ √

60 V

Squib Drivers

√

√

√

√

√

√

√

√

√

√


Peak Transient

Over Temperature

750 mΩ

Current Limit

Dual

Power On Reset

2

Serial Interface

CS2082

Safing Sensor Detection

RDS(on) @ 25_C

Short to Battery Monitor

Loop

Short to Ground Monitor

Number of Outputs

Squib Resistance Measurement

Part Number

Protection

Firing Potential Monitor

Features Battery Potential Monitor

Output

60 V

Vacuum Fluorescent Drivers Outputs

Interface

Anodes Part Number

Features

Grids

Count

Current

Voltage (Typ)

CS1087/9

23 6

2 mA 20 mA

CS1088

25 6

2 mA 20 mA

Protection

Dimming

Count

Current

Voltage (Typ)

Type

SPI

Data Out

Power On Reset

Low Iq

PWM Input Pin

0.3 V 0.3 V

3

50 mA

0.5 V

Push–Pull Push–Pull

√

√

√

√

0.3 V 0.3 V

3

50 mA

0.5 V

Push–Pull Push–Pull

√

√

√

Serial Input Bits

Multiplex

Max Voltage

√

Triplex

18 V

√

Triplex

18 V

Sensor Interface Part

Features

Number

Description

Channels

Hysteresis

Programmable Trip Level

Trimming Method

Active Input Clamps

VCC Max

CS1124

Variable–Reluctance Sensor Interface IC

2

±160 mV

√

N/A

√

7.0 V

Air Core Motor Drivers/Gauge Drivers Gauges Driven

Input

Part Number

Major

CS4121

1

CS4122

1

CS8190

1

√

CS8191

1

√

Minor

Freq.

PWM

Output SPI

√ √

2

√

Features

Current

Method

33 mA

Differential

80 mA

Differential

33 mA

Differential

55 mA

Differential

Return to Zero

UVLO

Protection Regulator Output

Current Limit

Over Voltage

√

√ √

√

Over Temp.

60 V

√

√ √

Peak Transient

√

18 V

√

60 V

√

60 V

Stepper Motor Drivers/Odometer Drivers Input

Modes

Output

Features

Part Number

Sine

Square

+1

+2

Current

Method

UVLO

CS4161

√

√

√

√

85 mA

Differential

√

CS8441

√

√

√

√

85 mA

Differential


Buffered Speed Output

Protection On–Chip Flyback Diodes

Current Limit

Over Voltage

Peak Transient

√

√

√

60 V

√

√

√

60 V

Application Specific Standard Products Automotive (continued) Voltage Regulation

Iout = 100 mA

Iout = 150 mA

Iout = 300 mA

Fixed Vout

Fixed Vout

Fixed Vout

LM2931 CS9202

CS9201 CS8221


CS8321

w/ Reset

w/ Shutdown & Reset

w/ Reset

w/ Reset & Delay

L4949

CS8122 CS8126


Single CS8182 Dual

CS403

CS8120

Tracking

CS8129

CS8183 CS8363 CS8361

Duals

Dual w/ Enable CS8147 (500 mA, 70 mA) CS8156 (750 mA, 100 mA) CS8161 (400 mA, 200 mA) CS8183 (200 mA, 200 mA) CS8281 (250 mA, 100 mA) CS8371 (1 A, 250 mA) CS8391 (250 mA, 100 mA) CS8481 (250 mA, 100mA)

Iout = 500 mA

CS8311 Iout = 200 m A

w/ Watchdog & Reset

Fixed Vout Dual w/ Enable & Reset

CS8151 Fixed Vout, w/ Reset, Power Warning MC34160

CS8182

MC33160

Adjustable Vout LM2931

Adjustable Vout

w/ Shutdown

w/ Watchdog, Reset, Delay, & Shutdown CS8140 CS8141

CS8271


CS8361 (250 mA, 100 mA) CS8363 (250 mA, 100 mA)



Voltage Regulators

DC–DC Converters for Telecom Equipment NCP1560 CS51220 CS51021A CS51022A CS51023A CS51024A

Smart LDOs for NIC and PCI Cards

CS5106 CS5124 CS5126 CS51221 CS51227

Iout = 200 mA MC33565 DC–DC Converters for Microprocessors (VRM)

Iout = 500 mA CS5231–3 CS5233–3

Single Channel w/ DAC for 12 V Only CS5150H CS5151H CS5155H CS5156H CS5161H CS5165H CS5166H CS51312

Single Channel w/ DAC CS5150H CS5151H CS5155H CS5156H CS5157H CS5158 CS5159

CS5160 CS5161 CS5165H CS5166H CS51311 MC33470

Single Channel w/ DAC & VRef CS51313


Multi–Phase CS5301 CS5302 CS5303 CS5305 CS5307 CS5308 CS5322 NCP5322A CS5323 CS5332

Iout = 1.5 A MC33566 CS5233–3 Dual LDO Controller for Graphics Cards MC33567 SCSI Applications MC34268


Wireless & Portable

DC–DC Converters for PDAs, Electronic Organizers

LDO’s

Display Drivers

RF Power Management

Charge Control

EL Lamp Driver with Synchronous Rectification

MC33441

MC34280 MC33680

Dual Band GaAs P.A. MC33170

Multi–Output LDO Voltage Regulators

Motor Driver NCP5426

Antenna Switch Controller

Power Management Controllers for RF Power Amplifiers

MDC5100 MDC5101

LCD MC34271

MC33765 MC33762

Battery Management

Bias Stabilizer MDC5001

Audio Amp Driver

RF Signal Detection

NCP2860

NCS5000

MC33340 MC33342 Lithium Battery Protection MC33349 (1 cell) NCP800 (1 cell) MC33351A (3 cell) Voltage & Current Regulator MC33341 PWM Buck Controller for Li–ion CS5361 Single Cell Li–ion Battery Charge Controller



Smart Cards

Power Management & Interface IC

Level Shifters for SmartCard & SIM Interface

MC33560 NCN6000

NCN6010 NCN6011


CHAPTER 2 Data Sheets


t

The LM285/LM385 series are micropower two–terminal bandgap voltage regulator diodes. Designed to operate over a wide current range of 10 µA to 20 mA, these devices feature exceptionally low dynamic impedance, low noise and stable operation over time and temperature. Tight voltage tolerances are achieved by on–chip trimming. The large dynamic operating range enables these devices to be used in applications with widely varying supplies with excellent regulation. Extremely low operating current make these devices ideal for micropower circuitry like portable instrumentation, regulators and other analog circuitry where extended battery life is required. The LM285/LM385 series are packaged in a low cost TO–226AA plastic case and are available in two voltage versions of 1.235 and 2.500 V as denoted by the device suffix (see Ordering Information table). The LM285 is specified over a –40°C to +85°C temperature range while the LM385 is rated from 0°C to +70°C. The LM385 is also available in a surface mount plastic package in voltages of 1.235 and 2.500 V. • Operating Current from 10 µA to 20 mA • 1.0%, 1.5%, 2.0% and 3.0% Initial Tolerance Grades • Low Temperature Coefficient • 1.0 Ω Dynamic Impedance • Surface Mount Package Available

MICROPOWER VOLTAGE REFERENCE DIODES SEMICONDUCTOR TECHNICAL DATA Z SUFFIX PLASTIC PACKAGE CASE 29

N.C. Cathode Anode D SUFFIX PLASTIC PACKAGE CASE 751 !

(SO–8)

7 !

!

!

!

Standard Application

&

Representative Schematic Diagram

#

"

$% "

ORDERING INFORMATION

Device LM285D–1.2 LM285Z–1.2 LM285D–2.5 LM285Z–2.5

Ω

LM385D–1.2 LM385Z–1.2 LM385BD–2.5 LM385BZ–2.5

March, 2001 – Rev. 3

Reverse Break– Operating Temperature down Voltage Tolerance Range TA = –40° to +85°C

LM385BD–1.2 LM385BZ–1.2

 Semiconductor Components Industries, LLC, 2001

!

LM385D–2.5 LM385Z–2.5

86

TA = 0° to +70°C

1.235 V

±1.0%

2.500 V

±1.5%

1.235 V

±1.0%

1.235 V

±2.0%

2.500 V

±1.5%

2.500 V

±3.0%

Publication Order Number: LM285/D

LM285 LM385, B MAXIMUM RATINGS (TA = 25°C, unless otherwise noted) Symbol

Value

Unit

Reverse Current

IR

30

mA

Forward Current

IF

10

mA

Operating Ambient Temperature Range LM285 LM385

TA

Operating Junction Temperature

TJ

+ 150

°C

Storage Temperature Range

Tstg

– 65 to + 150

°C

Rating

°C – 40 to + 85 0 to +70

ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted) LM285–1.2 Characteristic Reverse Breakdown Voltage (IRmin IR 20 mA) LM285–1.2/LM385B–1.2 TA = Tlow to Thigh (Note 1) LM385–1.2 TA = Tlow to Thigh (Note 1) Minimum Operating Current TA = 25°C TA = Tlow to Thigh (Note 1) Reverse Breakdown Voltage Change with Current IRmin IR 1.0 mA, TA = +25°C TA = Tlow to Thigh (Note 1) 1.0 mA IR 20 mA, TA = +25°C TA = Tlow to Thigh (Note 1) Reverse Dynamic Impedance IR = 100 µA, TA = +25°C

Symbol

LM385–1.2/LM385B–1.2

Min

Typ

Max

Min

Typ

Max

1.223 1.200 – –

1.235 – – –

1.247 1.270 – –

1.223 1.210 1.205 1.192

1.235 – 1.235 –

1.247 1.260 1.260 1.273

– –

8.0 –

10 20

– –

8.0 –

15 20

– – – –

– – – –

1.0 1.5 10 20

– – – –

– – – –

1.0 1.5 20 25

0.6

–

–

0.6

–

W

V(BR)R

Unit V

µA

IRmin

∆V(BR)R

mV

Z ∆V(BR)/∆T

–

80

–

–

80

–

ppm/°C

Wideband Noise (RMS) IR = 100 µA, 10 Hz f 10 kHz

n

–

60

–

–

60

–

µV

Long Term Stability IR = 100 µA, TA = +25°C ± 0.1°C

S

–

20

–

–

20

–

ppm/ kHR

Average Temperature Coefficient 10 µA IR 20 mA, TA = Tlow to Thigh (Note 1)


LM285 LM385, B ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted) LM285–2.5 Characteristic Reverse Breakdown Voltage (IRmin IR 20 mA) LM285–2.5/LM385B–2.5 TA = Tlow to Thigh (Note 1) LM385–2.5 TA = Tlow to Thigh (Note 1) Minimum Operating Current TA = 25°C TA = Tlow to Thigh (Note 1) Reverse Breakdown Voltage Change with Current IRmin IR 1.0 mA, TA = +25°C TA = Tlow to Thigh (Note 1) 1.0 mA IR 20 mA, TA = +25°C TA = Tlow to Thigh (Note 1) Reverse Dynamic Impedance IR = 100 µA, TA = +25°C

Symbol

LM385–2.5/LM385B–2.5

Min

Typ

Max

Min

Typ

Max

2.462 2.415 – –

2.5 – – –

2.538 2.585 – –

2.462 2.436 2.425 2.400

2.5 – 2.5 –

2.538 2.564 2.575 2.600

– –

13 –

20 30

– –

13 –

20 30

– – – –

– – – –

1.0 1.5 10 20

– – – –

– – – –

2.0 2.5 20 25

0.6

–

–

0.6

–

W

V(BR)R

Unit V

µA

IRmin

∆V(BR)R

mV

Z ∆V(BR)/∆T

–

80

–

–

80

–

ppm/°C

Wideband Noise (RMS) IR = 100 µA, 10 Hz f 10 kHz

n

–

120

–

–

120

–

µV

Long Term Stability IR = 100 µA, TA = +25°C ± 0.1°C

S

–

20

–

–

20

–

ppm/ kHR

Average Temperature Coefficient 20 µA IR 20 mA, TA = Tlow to Thigh (Note 1)

NOTES: 1. Tlow = – 40°C for LM285–1.2, LM285–2.5 = 0°C for LM385–1.2, LM385B–1.2, LM385–2.5, LM385B–2.5

Thigh = +85°C for LM285–1.2, LM285–2.5 Thigh = +70°C for LM385–1.2, LM385B–1.2, LM385–2.5, LM385B–2.5


LM285 LM385, B TYPICAL PERFORMANCE CURVES FOR LM285–1.2/385–1.2/385B–1.2

Figure 1. Reverse Characteristics

Figure 2. Reverse Characteristics ∆5 5'/5**5:*/$(2 µ

( ? #@ ° #@ °

"@°

5 ' 5**5:* $( Vref

3

" " "

"

Figure 3. Test Circuit for Ioff

3 ? ( ? °

)0

" "

'/5*4*5*!*/)!.-(/$( 1 1> 1 > -

> -

> -

*4$ 40+*+ *'"'(*0(' ,°.

Figure 4. Dropout Voltage versus Junction Temperature

*$ /'+* *'"'(*0(' ,°.

1 > 1 > - *4 > °

1$ +"0* 1* ' ,1.

$

+ @69 :

(θ4 > °3& "#,-9A. ° > -& *$ /'+* *'"'(*0(' ,°.

ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ

9< 6 6:6 : :D--6

E98 89D

Figure 7. Maximum Average Power Dissipation versus Ambient Temperature – TO–92 Type Package

--

(θ4

$ '+ *@ ! ""'( ,--.

Figure 8. SOP–8 Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length


C 6

"#,-9A. 5 * > °

Figure 6. Input Bias Current versus Input Voltage

( θ 4$%*@'(%('))*+' 40+*+B*B(%,%%3&. °

Figure 5. Input Bias Current versus Ambient Temperature

"# $%"&'(%#))"*+%,-&.

> -

# 5 (67 89 : 656 9: ; ? 5 1

/ $%+"0*%/)%0(('+*%,-.

"#$%0%"&'(%#))"*+%,&.

1$%0*"0*%1* '%,1.

MC78L00A Series APPLICATIONS INFORMATION Design Considerations

input bypass capacitor should be selected to provide good high–frequency characteristics to insure stable operation under all load conditions. A 0.33 µF or larger tantalum, mylar, or other capacitor having low internal impedance at high frequencies should be chosen. The bypass capacitor should be mounted with the shortest possible leads directly across the regulators input terminals. Good construction techniques should be used to minimize ground loops and lead resistance drops since the regulator has no external sense lead. Bypassing the output is also recommended.

The MC78L00A Series of fixed voltage regulators are designed with Thermal Overload Protection that shuts down the circuit when subjected to an excessive power overload condition. Internal Short Circuit Protection limits the maximum current the circuit will pass. In many low current applications, compensation capacitors are not required. However, it is recommended that the regulator input be bypassed with a capacitor if the regulator is connected to the power supply filter with long wire lengths, or if the output load capacitance is large. The

K1

MC78L15A

µ!

(

: 9

6 6 9

K

µ! 1

*. 1& 1 7.B 9* ,7@ 8* *9@, D. @. *@ * 8 77. @, 78. ?>. 8,.8 . *@ *D,C. ,7.7 , )//)/;. /@@/* /, >. 1& 1& /@ 8>,@. / >/@ *9/8* /, .@/@ ,7 . .7)/.@

>. 8 77. *@ 0,99,?@H '

1& 1&

µ

G 6

* G

µ

1&

6 ' ) ,C.7 9/. * 9,* 8>*B.@ !>. */ /, ,0 * ,.7* /,*9 *)9/0/.7 *99,?@ *A @ ). , >/B>.7 ,7 / .7)./* . C*9 .@ ?>/9. 7. *//B 7.B 9* /, 8>*7*8 .7/@ /8@ !>. )//) ) C,9 *B. ,D */*D9. ?/ > >/@ *77*B.). /@ B7.* .7 >* >. 7.B 9* ,7 C,9 *B.

,7 .+*)9. * ) 8 77. @, 78. ?, 9 7.F /7. , D. * IΩ 7.@/@ ,7 * >. , C,9 *B. 8,)9/*8. ?, 9 D. >. / C,9 *B. 9.@@

Figure 10. Current Regulator

Figure 11. Adjustable Output Regulator

1% ,7 F /C

&

1& 155&

µ

µ

1% ,7 F /C

" ,7 F /C 1& 155& µ

55 ' /B/ @ ,0 :. )D.7 //8* /B C,9 *B.

55 ' /B/ @ ,0 :. )D.7 //8* /B C,9 *B.

!>. 1& 1 @.7/.@ 8* D. 8 77. D,,@ . ?/ > * "

7*@/@ ,7 !>. 1% 7,C/.@ 8 77. , .@/@ ,7 / 8,A 8 /, ?/ > >. 6 ,0 >. " . .7)/.@ ?>. >. *@@

7*@/@ ,7 D.B/@ 8, 8 /BE >/@ 8/78 / /@ , @>,7 8/78 /

7,,0 4, /00.7. /*9 C,9 *B. )//) ) /@ /87.*@. D: 6 ,0 >. *@@ 7*@/@ ,7

!>. 8/78 / ,0 /B 7. 8* D. ),/0/. , 7,C/. @ 9: 7, .8 /, *B*/@ @>,7 8/78 / @ D: */B * @>,7 8/78 / @.@. 7.@/@ ,7 @8 * * */ /,*9 " 7*@/@ ,7 !>. 8 77. @.@/B " ) @ D. *D9. , >*9. >. @>,7 8/78 / 8 77. ,0 >. >7..4 .7)/*9 7.B 9* ,7 !>.7.0,7. * 9*@ /8 ,?.7 7*@/@ ,7 /@ @.8/0/.

Figure 12. Current Boost Regulator

Figure 13. Current Boost with Short Circuit Protection


MC78M00, MC78M00A Series ORDERING INFORMATION Shipping Device

Output Voltage

Temperature Range

MC78M05CDT/RK MC78M05ACDT/RK

MC78M05ABDT/RK

50V 5.0

MC78M05ABT

40° to +125°C TJ = –40°

MC78M05BDT/RK MC78M05BT MC78M06CDT/RK MC78M06CT

6.0 V

TJ = 0° to +125°C TJ = –40° to +125°C

MC78M06BT MC78M08CDT/RK MC78M08ACDT/RK

MC78M08ABDT/RK

80V 8.0

MC78M08ABT

TJ = –40° 40° to +125°C

MC78M08BDT/RK MC78M08BT MC78M09CDT/RK MC78M09CT MC78M09BDT/RK

TJ = 0° to +125°C 90V 9.0 TJ = –40° 40° to +125°C

MC78M09BT MC78M12CDT/RK MC78M12ACDT/RK

MC78M12ABDT/RK

12 V

MC78M12ABT

TJ = –40° 40° to +125°C

MC78M12BDT/RK MC78M12BT MC78M15CDT/RK MC78M15ACDT/RK

MC78M15ABDT/RK

15 V

MC78M15ABT

TJ = –40° 40° to +125°C

MC78M15BDT/RK MC78M15BT MC78M18CDT MC78M18CT

18 V

TJ = 0° to +125°C

MC78M18BT

TJ = –40° to +125°C

MC78M20CT

TJ = 0° to +125°C

MC78M20BT MC78M24CT MC78M24BT

75 Units/Rail

2500 Units/Reel

TO 220 TO–220

50 Units/Rail

–

DPAK

75 Units/Rail

2500 Units/Reel

TO–220

50 Units/Rail

–

DPAK

75 Units/Rail

2500 Units/Reel

TO–220

50 Units/Rail

–

DPAK

75 Units/Rail

2500 Units/Reel

TO 220 TO–220

50 Units/Rail

–

DPAK

75 Units/Rail

2500 Units/Reel

TO 220 TO–220

50 Units/Rail

–

DPAK

75 Units/Rail

2500 Units/Reel

TO–220

50 Units/Rail

–

DPAK

75 Units/Rail

2500 Units/Reel

TO–220

50 Units/Rail

– 2500 Units/Reel

DPAK

75 Units/Rail

TO–220

50 Units/Rail

–

DPAK

75 Units/Rail

2500 Units/Reel

TO–220

50 Units/Rail

–

DPAK

75 Units/Rail

2500 Units/Reel

TO 220 TO–220

50 Units/Rail

– 2500 Units/Reel

DPAK

75 Units/Rail

TO–220

50 Units/Rail

–

DPAK

75 Units/Rail

2500 Units/Reel

TO–220

50 Units/Rail

–

DPAK

75 Units/Rail

2500 Units/Reel

TO 220 TO–220

50 Units/Rail

– 2500 Units/Reel

TJ = 0° to +125°C

MC78M15CT MC78M15ACT

DPAK

TJ = 0° to +125°C


Tape & Reel (RK Suffix)

TJ = 0° to +125°C


Rails (No Suffix)

TJ = 0° to +125°C


Package

20 V 24 V

TJ = –40° to +125°C TJ = 0° to +125°C TJ = –40° to +125°C


DPAK

75 Units/Rail

TO–220

50 Units/Rail

–

DPAK

75 Units/Rail

2500 Units/Reel

TO–220

50 Units/Rail

DPAK

75 Units/Rail

– TO 220 TO–220

50 Units/Rail

These voltage regulators are monolithic integrated circuits designed as fixed–voltage regulators for a wide variety of applications including local, on–card regulation. These regulators employ internal current limiting, thermal shutdown, and safe–area compensation. With adequate heatsinking they can deliver output currents in excess of 1.0 A. Although designed primarily as a fixed voltage regulator, these devices can be used with external components to obtain adjustable voltages and currents. • Output Current in Excess of 1.0 A • No External Components Required • Internal Thermal Overload Protection • Internal Short Circuit Current Limiting • Output Transistor Safe–Area Compensation • Output Voltage Offered in 2% and 4% Tolerance • Available in Surface Mount D2PAK, DPAK and Standard 3–Lead Transistor Packages

Input Voltage (5.0 – 18 V) Input Voltage (24 V)

Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case Case 936 (D2PAK) TA = 25°C

Value

Unit

VI

35 40

Vdc

PD RθJA RθJC

PD RθJA

Thermal Resistance, Junction–to–Case

RθJA

Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case

2

PD RθJA RθJC

Heatsink surface connected to Pin 2. 3 D2PAK D2T SUFFIX CASE 936

1

Pin 1. Input 2. Ground 3. Output

3 Heatsink surface (shown as terminal 4 in case outline drawing) is connected to Pin 2. DPAK DT SUFFIX CASE 369A

STANDARD APPLICATION

Thermal Resistance, Junction–to–Ambient

Case 369A (DPAK) TA = 25°C

1

3

Symbol

Power Dissipation Case 221A (TO–220) TA = 25°C

TO–220 T SUFFIX CASE 221A

1

MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.) Rating

http://onsemi.com

Internally Limited 65 5.0

Internally Limited See Figure 14 5.0


W °C/W °C/W

W °C/W

°C/W

W °C/W °C/W

Storage Junction Temperature Range

Tstg

–65 to +150

°C


TJ

+150

°C

&/J µ

MC78XX

&JJ

A common ground is required between the input and the output voltages. The input voltage must remain typically 2.0 V above the output voltage even during the low point on the input ripple voltage. XX, These two digits of the type number indicate nominal voltage. * Cin is required if regulator is located an appreciable distance from power supply filter. ** CO is not needed for stability; however, it does improve transient response. Values of less than 0.1 µF could cause instability.

ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 167 of this data sheet.

DEVICE MARKING INFORMATION

NOTE: ESD data available upon request.

See general marking information in the device marking section on page 169 of this data sheet.


January, 2002 – Rev. 9

152

Publication Order Number: MC7800/D

MC7800, MC7800A, LM340, LM340A Series /

1&

K..7

2 ! . 1& 7.B 9* ,7@ 8* *9@, D. @. *@ * 8 77. @, 78. ?>. 8,.8 . *@ *D,C. ,7.7 , )//)/;. /@@/* /, >. 1& & /@ 8>,@. / >/@ *9/8* /, .@/@ ,7 . .7)/.@ >. 8 77. *@ 0,99,?@H

+ I ) 6

µ

1&

' , " ' ≥

6 ^ ) ,C.7 9/. * 9,* 8>*B.@ ,7 .+*)9. * 8 77. @, 78. ?, 9 7.F /7. , D. * Ω 7.@/@ ,7 * >. , C,9 *B. 8,)9/*8. ?, 9 D. >. /

C,9 *B. 9.@@

!>. */ /, ,0 * ,.7* /,*9 *)9/0/.7 *99,?@ *A @ ). , >/B>.7 ,7 / .7)./* . C*9 .@ ?>/9. 7. *//B 7.B 9* /, 8>*7*8 .7/@ /8@ !>. )//) ) C,9 *B. ,D */*D9. ?/ > >/@ *77*B.). /@ B7.* .7 >* >. 7.B 9* ,7 C,9 *B.



, 78.

1% ,7 F /C

µ

&

, 78.

µ

MC78XX

≥ µ

µ

µ

≥ µ

1% ,7 F /C

" ,7 F /C MC78XX µ

55 ' /B/ @ ,0 :. )D.7 //8* /B C,9 *B.

55 ' /B/ @ ,0 :. )D.7 //8* /B C,9 *B. !>. 1& @.7/.@ 8* D. 8 77. D,,@ . ?/ > * " 7*@/@ ,7 !>. 1% 7,C/.@ 8 77. , .@/@ ,7 / 8,A 8 /, ?/ > >. 6 ,0 >. " . .7)/.@ ?>. >. *@@ 7*@/@ ,7 D.B/@ 8, 8 /BE >/@ 8/78 / /@ , @>,7 8/78 / 7,,0 (, /00.7. /*9 C,9 *B. )//) ) /@ /87.*@. D: 6 ,0 >. *@@ 7*@/@ ,7

!>. 8/78 / ,0 /B 7. 8* D. ),/0/. , 7,C/. @ 9: 7, .8 /, *B*/@ @>,7 8/78 / @ D: */B * @>,7 8/78 / @.@. 7.@/@ ,7 & * * */ /,*9 " 7*@/@ ,7 !>. 8 77. @.@/B " ) @ D. *D9. , >*9.

>. @>,7 8/78 / 8 77. ,0 >. >7..4 .7)/*9 7.B 9* ,7 !>.7.0,7. * 0, 74*).7. 9*@ /8 ,?.7 7*@/@ ,7 /@ @.8/0/.


Figure 11. Short Circuit Protection


MC7800, MC7800A, LM340, LM340A Series

/ 4, "3!43!3!2! "! 2#$

θ- ' °&(

θ- ' °&(

θ- ' °&(

", -.* @/

4

4

' ' )

' )

' ) ' )

∆ ' O ,0 + .. & 7C. 0,7 1& 556

4

4

4

!% %3"&!" !1 !3 #°&$

Figure 12. Worst Case Power Dissipation versus Ambient Temperature (Case 221A)

Figure 13. Input Output Differential as a Function of Junction Temperature (MC78XXC, AC, B)

%3"&!"P!P #&($ °

θ % !-1 2! "&

#)*+$ 0,7 ! ' °&

7.. /7 1, . .7 /8*99:

ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ,; &,.7 2

1//) ) /;. *

2

θ%

1 5131 !"#$

! 16"! !1 !3 #°&$

2 2"!- & #))$

%3"&!"4!4 #&($ °

7.. /7 1, . .7 /8*99:

ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ

1//) ) /;. *

,; &,.7 2

2

#)*+$ 0,7 ! ' °&

θ%

2 2"!- & #))$

Figure 15. DPAK Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length


1 5131 !"#$

Figure 14. D2PAK Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length

θ % !-1 2! "&

!"#$

θ%& ' °&( θ% ' °&( !%#)*+$ ' °&

MC7800, MC7800A, LM340, LM340A Series DEFINITIONS Quiescent Current – That part of the input current that is not delivered to the load. Output Noise Voltage – The rms ac voltage at the output, with constant load and no input ripple, measured over a specified frequency range. Long Term Stability – Output voltage stability under accelerated life test conditions with the maximum rated voltage listed in the devices’ electrical characteristics and maximum power dissipation.

Line Regulation – The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. Load Regulation – The change in output voltage for a change in load current at constant chip temperature. Maximum Power Dissipation – The maximum total device dissipation for which the regulator will operate within specifications.

ORDERING INFORMATION Shipping Device

Output Voltage

Temperature Range

Package TO–220

MC7805.2CT MC7805ACD2T/R4

D2PAK

MC7805ACT

TO–220

MC7805CD2T/R4

D2PAK

TJ = 0° to +125°C

MC7805CT 5.0 V

800 Units/Reel 50 Units/Rail

D2PAK

MC7805BD2T/R4

– 75 Units/Rail

TJ = *40° to +125°C

MC7805BDT/RK

DPAK

2500 Units/Reel –

50 Units/Rail

TO–220

MC7805BT

– 800 Units/Reel

TO 220 TO–220

LM340AT–5

Tape & Reel (R4 Suffix) –

TO–220 DPAK

MC7805CDT/RK LM340T–5

Rails (No Suffix)

800 Units/Reel –

75 Units/Rail

2500 Units/Reel

MC7805ABD2T/R4

D2PAK

800 Units/Reel

MC7805ABT

TO–220

–

MC7806ACT MC7806CT MC7806BD2T/R4

TJ = 0° to +125°C 60V 6.0 TJ = *40° 40° to +125°C

MC7806BT MC7808CD2T/R4

TJ = 0° to +125°C

MC7808CT

50 Units/Rail

–

TO–220

–

TO–220

MC7808BT TJ = *40° to +125°C

DPAK

MC7808ABD2T/R4

D2PAK

MC7808ABT

TO–220


– 800 Units/Reel

D2PAK

8.0 V

800 Units/Reel

D2PAK DPAK

MC7808CDT/RK/T5

MC7808BDT/RK

D2PAK

–

TO 220 TO–220

MC7808ACT

MC7808BD2T/R4

–

TO 220 TO–220

75 Units/Rail 50 Units/Rail 75 Units/Rail 50 Units/Rail

2500 Units/Reel 800 Units/Reel – 2500 Units/Reel 800 Units/Reel –

MC7800, MC7800A, LM340, LM340A Series ORDERING INFORMATION (continued) Shipping Device

Output Voltage

Temperature Range

MC7809ACT MC7809CD2T/R4 MC7809CT

90V 9.0

TJ = 0° to +125°C TJ = *40° to +125°C

MC7809BT

Package

Rails (No Suffix)

Tape & Reel (R4 Suffix)

TO–220

–

D2PAK

800 Units/Reel –

TO 220 TO–220 50 Units/Rail

–

MC7812ACD2T/R4

D2PAK

MC7812ACT

TO–220

–

MC7812CD2T/R4

D2PAK

800 Units/Reel

TO–220

–

MC7812CT

TJ = 0° to +125°C

DPAK

MC7812CDT/RK LM340T–12 LM340AT–12

12 V

TO 220 TO–220

MC7812BD2T/R4

D2PAK

MC7812BT

TO–220 TJ = *40° to +125°C

MC7812BDT/RK

75 Units/Rail

DPAK

800 Units/Reel

2500 Units/Reel –

50 Units/Rail

800 Units/Reel –

75 Units/Rail

2500 Units/Reel

MC7812ABD2T/R4

D2PAK

800 Units/Reel

MC7812ABT

TO–220

–

MC7815ACD2T/R4

D2PAK

800 Units/Reel

MC7815ACT

TO–220

MC7815CD2T/R4

D2PAK

MC7815CT

MC7815CDT/RK

– 800 Units/Reel

TJ = 0° to +125°C

LM340T–15 LM340AT–15

50 Units/Rail

TO–220 15 V

DPAK

MC7815BD2T/R4

D2PAK

MC7815BT

TO–220 TJ = *40° to +125°C

MC7815BDT/RK

DPAK

– 75 Units/Rail 50 Units/Rail 75 Units/Rail

2500 Units/Reel 800 Units/Reel – 2500 Units/Reel

MC7815ABD2T/R4

D2PAK

800 Units/Reel

MC7815ABT

TO–220

–

MC7818ACT

TO–220

–

TJ = 0° to +125°C

D2PAK

800 Units/Reel

TJ = *40° to +125°C

TO–220

MC7818CD2T/R4 MC7818CT

18 V

MC7818BT

–

MC7824CD2T MC7824BD2T/R4 MC7824BT

– –

MC7824ACT MC7824CT

50 Units/Rail

TJ = 0° to +125°C

D2PAK TO–220

24 V TJ = *40° 40° to +125°C


–

D2PAK

800 Units/Reel

TO–220

–

MC7800, MC7800A, LM340, LM340A Series MARKING DIAGRAMS TO–220 T SUFFIX CASE 221A MC7800, MC7800A Series

LM340, LM340A Series

MC 78xxXXT AWLYWW

LM 340XT–xx AWLYWW

D2PAK D2T SUFFIX CASE 936

DPAK DT SUFFIX CASE 369A

MC 78xxXXD2T AWLYWW

78xxX ALYWW

xx XX A WL, L Y WW

= Voltage Option = Appropriate Suffix Options = Assembly Location = Wafer Lot = Year = Work Week


t

This family of fixed voltage regulators are monolithic integrated circuits capable of driving loads in excess of 3.0 A. These three–terminal regulators employ internal current limiting, thermal shutdown, and safe–area compensation. Devices are available with improved specifications, including a 2% output voltage tolerance, on AC–suffix 5.0, 12 and 15 V device types. Although designed primarily as a fixed voltage regulator, these devices can be used with external components to obtain adjustable voltages and currents. This series of devices can be used with a series–pass transistor to supply up to 15 A at the nominal output voltage. • Output Current in Excess of 3.0 A • Power Dissipation: 25 W • No External Components Required • Output Voltage Offered in 2% and 4% Tolerance* • Thermal Regulation is Specified • Internal Thermal Overload Protection • Internal Short Circuit Current Limiting • Output Transistor Safe–Area Compensation

THREE–AMPERE POSITIVE FIXED VOLTAGE REGULATORS SEMICONDUCTOR TECHNICAL DATA

T SUFFIX PLASTIC PACKAGE CASE 221A

+ , " -

1 2 3

Heatsink surface is connected to Pin 2.

DEVICE TYPE/NOMINAL OUTPUT VOLTAGE MC78T05 MC78T08

5.0 V 8.0 V

MC78T12 MC78T15

12 V 15 V


Simplified Application

µ

Operating Temperature Package Range

Device

VO Tol.

MC78TXXCT MC78TXXACT

4% 2%*

TJ = 0° to +125°C

Plastic Power

MC78TXXBT# MC78TXXABT#

4% 2%*

TJ = –40° to +125°C

Plastic Power

XX Indicates nominal voltage.

* 2% regulators available in 5, 12 and 15 V devices. # Automotive temperature range selections are available with special test conditions and additional tests. Contact your local ON Semiconductor sales office for information.

!! "" # $$ % ! % % ! % &' % % ( % !) *



170

Publication Order Number: MC78T00/D

MC78T00 Series MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.) Symbol

Value

Unit

VI

35 40

Vdc

Power Dissipation and Thermal Characteristics Plastic Package (Note 1) TA = +25°C Thermal Resistance, Junction–to–Air TC = +25°C Thermal Resistance, Junction–to–Case

PD RθJA PD RθJC

Internally Limited 65 Internally Limited 2.5

Storage Junction Temperature

Tstg

+150

°C

Operating Junction Temperature Range (MC78T00C, AC)

TJ

0 to +125

°C

Rating Input Voltage (5.0 V – 12 V) Input Voltage (15 V)

°C/W °C/W

NOTES: 1. Although power dissipation is internally limited, specifications apply only for PO ≤ Pmax, Pmax = 25 W.

ELECTRICAL CHARACTERISTICS (Vin = 10 V, IO = 3.0 A, 0°C ≤ TJ ≤ 125°C, PO ≤ Pmax [Note 1], unless otherwise noted.) MC78T05AC Characteristics Output Voltage (5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) (5.0 mA ≤ IO ≤ 3.0 A; 5.0 mA ≤ IO ≤ 2.0 A, 7.3 Vdc ≤ Vin ≤ 20 Vdc)

Symbol

Min

Typ

Max

Min

Typ

Max

4.9 4.8

5.0 5.0

5.1 5.2

4.8 4.75

5.0 5.0

5.2 5.25

–

3.0

25

–

3.0

25

– –

10 15

30 80

– –

10 15

30 80

–

0.001

0.01

–

0.002

0.03

– –

3.5 4.0

5.0 6.0

– –

3.5 4.0

5.0 6.0

VO

Line Regulation (Note 2) (7.2 Vdc ≤ Vin ≤ 35 Vdc, IO = 5.0 mA, TJ = +25°C; 7.2 Vdc ≤ Vin ≤ 35 Vdc, IO = 1.0 A, TJ = +25°C; 8.0 Vdc ≤ Vin ≤ 12 Vdc, IO = 3.0 A, TJ = +25°C; 7.5 Vdc ≤ Vin ≤ 20 Vdc, IO = 1.0 A)

Regline

Load Regulation (Note 2) (5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) (5.0 mA ≤ IO ≤ 3.0 A)

Regload

Thermal Regulation (Pulse = 10 ms, P = 20 W, TA = +25°C)

Regtherm

Quiescent Current (5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) (5.0 mA ≤ IO ≤ 3.0 A)

MC78T05C Unit Vdc

mV

mV

IB

%VO/W mA

Quiescent Current Change (7.2 Vdc ≤ Vin ≤ 35 Vdc, IO = 5.0 mA, TJ = +25°C; 5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C; 7.5 Vdc ≤ Vin ≤ 20 Vdc, IO = 1.0 A)

∆IB

–

0.3

1.0

–

0.3

1.0

mA

Ripple Rejection (8.0 Vdc ≤ Vin ≤ 18 Vdc, f = 120 Hz, IO = 2.0 A, TJ = 25°C)

RR

62

75

–

62

75

–

dB

Vin–VO

–

2.2

2.5

–

2.2

2.5

Vdc

Output Noise Voltage (10 Hz ≤ f ≤ 100 kHz, TJ = +25°C)

Vn

–

10

–

–

10

–

µV/VO

Output Resistance (f = 1.0 kHz)

RO

–

2.0

–

–

20

–

mΩ

Short Circuit Current Limit (Vin = 35 Vdc, TJ = +25°C)

ISC

–

1.5

–

–

1.5

–

A

Peak Output Current (TJ = +25°C)

Imax

–

5.0

–

–

5.0

–

A

TCVO

–

0.2

–

–

0.2

–

mV/°C

Dropout Voltage (IO = 3.0 A, TJ = +25°C)

Average Temperature Coefficient of Output Voltage (IO = 5.0 mA)

NOTES: 1. Although power dissipation is internally limited, specifications apply only for PO ≤ Pmax, Pmax = 25 W. 2. Line and load regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.


MC78T00 Series ELECTRICAL CHARACTERISTICS (Vin = 13 V, IO = 3.0 A, 0°C ≤ TJ ≤ 125°C, PO ≤ Pmax [Note 1], unless otherwise noted.) MC78T08C Characteristics

Symbol

Output Voltage (5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) (5.0 mA ≤ IO ≤ 3.0 A; 5.0 mA ≤ IO ≤ 2.0 A, 10.4 Vdc ≤ Vin ≤ 23 Vdc)

Min

Typ

Max

7.7 7.6

8.0 8.0

8.3 8.4

–

4.0

35

– –

10 15

30 80

–

0.002

0.03

– –

3.5 4.0

5.0 6.0

VO

Line Regulation (Note 2) (10.3 Vdc ≤ Vin ≤ 35 Vdc, IO = 5.0 mA, TJ = +25°C 10.3 Vdc ≤ Vin ≤ 35 Vdc, IO = 1.0 A, TJ = +25°C 11 Vdc ≤ Vin ≤ 17 Vdc, IO = 3.0 A, TJ = +25°C 10.7 Vdc ≤ Vin ≤ 23 Vdc, IO = 1.0 A)

Regline


Regload


Regtherm


Unit Vdc

mV

mV

IB

%VO/W mA


∆IB

–

0.3

1.0

mA

Ripple Rejection (11 Vdc ≤ Vin ≤ 21 Vdc, f = 120 Hz, IO = 2.0 A, TJ = 25°C)

RR

60

71

–

dB

Vin–VO

–

2.2

2.5

Vdc

Vn

–

10

–

µV/VO


RO

–

2.0

–

mΩ


ISC

–

1.5

–

A


Imax

–

5.0

–

A

TCVO

–

0.3

–

mV/°C

Dropout Voltage (IO = 3.0 A, TJ = +25°C) Output Noise Voltage (10 Hz ≤ f ≤ 100 kHz, TJ = +25°C)




MC78T00 Series ELECTRICAL CHARACTERISTICS (Vin = 17 V, IO = 3.0 A, 0°C ≤ TJ ≤ 125°C, PO ≤ Pmax [Note 1], unless otherwise noted.) MC78T12AC Characteristics Output Voltage (5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) (5.0 mA ≤ IO ≤ 3.0 A, 5.0 mA ≤ IO ≤ 2.0 A, 14.5 Vdc ≤ Vin ≤ 27 Vdc)

Symbol

Typ

Max

Min

Typ

Max

11.75 11.5

12 12

12.25 12.5

11.5 11.4

12 12

12.5 12.6

–

6.0

45

–

6.0

45

– –

10 15

30 80

– –

10 15

30 80

–

0.001

0.01

–

0.002

0.03

– –

3.5 4.0

5.0 6.0

– –

3.5 4.0

5.0 6.0

VO

Line Regulation (Note 2) (14.5 Vdc ≤ Vin ≤ 35 Vdc, IO = 5.0 mA, TJ = +25°C; 14.5 Vdc ≤ Vin ≤ 35 Vdc, IO = 1.0 A, TJ = +25°C; 16 Vdc ≤ Vin ≤ 22 Vdc, IO = 3.0 A, TJ = +25°C; 14.9 Vdc ≤ Vin ≤ 27 Vdc, IO = 1.0 A)

Regline


Regload


Regtherm


MC78T12C

Min

Unit Vdc

mV

mV

IB

%VO/W mA


∆IB

–

0.3

1.0

–

0.3

1.0

mA

Ripple Rejection (15 Vdc ≤ Vin ≤ 25 Vdc, f = 120 Hz, IO = 2.0 A, TJ = 25°C)

RR

57

67

–

57

67

–

dB


Vin – VO

–

2.2

2.5

–

2.2

2.5

Vdc


Vn

–

10

–

–

10

–

µV/VO


RO

–

2.0

–

–

20

–

mΩ


ISC

–

1.5

–

–

1.5

–

A


Imax

–

5.0

–

–

5.0

–

A


TCVO

–

0.5

–

–

0.5

–

mV/°C



MC78T00 Series ELECTRICAL CHARACTERISTICS (Vin = 20 V, IO = 3.0 A, 0°C ≤ TJ ≤ 125°C, PO ≤ Pmax [Note 1], unless otherwise noted.) MC78T15AC Characteristics Output Voltage (5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C) (5.0 mA ≤ IO ≤ 3.0 A; 5.0 mA ≤ IO ≤ 2.0 A, 17.5 Vdc ≤ Vin ≤ 30 Vdc)

Symbol

MC78T15C

Min

Typ

Max

Min

Typ

Max

14.7 14.4

15 15

15.3 15.6

14.4 14.25

15 15

15.6 15.75

–

7.5

55

–

7.5

55

– –

10 15

30 80

– –

10 15

30 80

–

0.001

0.01

–

0.002

0.03

– –

3.5 4.0

5.0 6.0

– –

3.5 4.0

5.0 6.0

VO

Line Regulation (Note 2) (17.6 Vdc ≤ Vin ≤ 40 Vdc, IO = 5.0 mA, TJ = +25°C; 17.6 Vdc ≤ Vin ≤ 40 Vdc, IO = 1.0 A, TJ = +25°C; 20 Vdc ≤ Vin ≤ 26 Vdc, IO = 3.0 A, TJ = +25°C; 18 Vdc ≤ Vin ≤ 30 Vdc, IO = 1.0 A)

Regline


Regload


Regtherm

Unit Vdc

mV

mV

%VO/W


IB

mA

Quiescent Current Change (17.6 Vdc ≤ Vin ≤ 40 Vdc, IO = 5.0 mA, TJ = +25°C; 5.0 mA ≤ IO ≤ 3.0 A, TJ = +25°C; 18 Vdc ≤ Vin ≤ 30 Vdc, IO = 1.0 A)

∆IB

–

0.3

1.0

–

0.3

1.0

mA

Ripple Rejection (18.5 Vdc ≤ Vin ≤ 28.5 Vdc, f = 120 Hz, IO = 2.0 A, TJ = 25°C)

RR

55

65

–

55

65

–

dB


Vin–VO

–

2.2

2.5

–

2.2

2.5

Vdc


Vn

–

10

–

–

10

–

µV/VO


RO

–

2.0

–

–

20

–

mΩ


ISC

–

1.0

–

–

1.0

–

A


Imax

–

5.0

–

–

5.0

–

A

TCVO

–

0.6

–

–

0.6

–

mV/°C




MC78T00 Series

The performance of a voltage regulator is specified by its immunity to changes in load, input voltage, power dissipation, and temperature. Line and load regulation are tested with a pulse of short duration (< 100µs) and are strictly a function of electrical gain. However, pulse widths of longer duration (> 1.0 ms) are sufficient to affect temperature gradients across the die. These temperature gradients can cause a change in the output voltage, in addition to changes caused by line and load regulation. Longer pulse widths and thermal gradients make it desirable to specify thermal regulation. Thermal regulation is defined as the change in output voltage caused by a change in dissipated power for a specified time, and is expressed as a percentage output voltage change per watt. The change in dissipated power

can be caused by a change in either the input voltage or the load current. Thermal regulation is a function of IC layout and die attach techniques, and usually occurs within 10 ms of a change in power dissipation. After 10 ms, additional changes in the output voltage are due to the temperature coefficient of the device. Figure 1 shows the line and thermal regulation response of a typical MC78T05AC to a 20 W input pulse. The variation of the output voltage due to line regulation is labeled À and the thermal regulation component is labeled Á. Figure 2 shows the load and thermal regulation response of a typical MC78T05AC to a 20 W load pulse. The output voltage variation due to load regulation is labeled À and the thermal regulation component is labeled Á.

∆ # *74 +4 # *76+4 #8 -1731# 67&#( #8 -17&#(

∆ # *74 +4 #8 -1731# 67&#(

VOLTAGE REGULATOR PERFORMANCE

" ,

9

*74 +4 45516 7&(

&" 7#23#(

,9

"

, " "

* 01 &" 23#( # . / # # . 9 # → ,9 # → 9 # . "

* 01 &" 23#( # . / # # . ,/ . → " →

, . 5 . ": # " . 5 .

,/;#2

?A ?:A

=/

"

, A A =,>

/?A

, ="

/

/"

=,"

=?

=@

"?A 9 B,/C# / # >A

" A =,,

="/

="?

, "

="@

,"

:

? A

=,@

=,9 =,/

=, ? A

=,?

=,

,

=,:

-

"9A

Representative Schematic Diagram


MC78T00 Series ,

*74 +4 70+13617&7JC( Ω

6508F1374 +4 7#8 -1

, " # B # . , # . ,

,

>9 B>

B/

B,

@

,,

E* E46 6 10+15 451 &°(

,/

, B,

, B"

, B

, B: ,

,>

Figure 3. Temperature Stability

55*75++81751E1 67&D(

. /

9

. ,/ ?

# . / # # . , # .

E . "/°

:

,

,

, A

, A

,

A

, 0

, 0

, A , A ,

A %* 51=416G &HI(

, 0

, 0 ,

0

:

# . / # # . , # .

% . ," HI E . "/°

,

,

,

* 4 +4 45516 &(

Figure 5. Ripple Rejection versus Frequency

Figure 6. Ripple Rejection versus Output Current

/

E . ° E . "/°

E . ,"/°

"

E . °

E . "/°

E . ,"/°

?

%* 51=416G &HI(

:

,

9

,

,

0

D *7=41'16 745516 7&(

55*75++81751E1 67&D(

,

,

"

,

D *7=41'16 745516 7&(

,

Figure 4. Output Impedance

,

# . / # # . @/ # . , .

E . "/°

,

"

E . "/°

E . ,"/°

"

,

,

:

E . °

:

#B# . / #

,

,

#* 6+4 #8 -1 &#(

* 4 +4 45516 &(

Figure 7. Quiescent Current versus Input Voltage

Figure 8. Quiescent Current versus Output Current


,

MC78T00 Series 9

K*7+1L74 +4 745516 7&(

# B# *76+4 7 74 +4 #8 -173

1516 87&#(

"/ . "

. ,

,/

. /

,

∆# . / #

/ B>

B/

B,

@

,,

,/

?

:

"

E . "/°

,>

E . °

E . ,"/°

,

E* E46 6 10+15 451 &°(

∆ # *74 +4 7#8 -1 31# 67&#(

:

"

,

/

,

"

:

# . , # .

E . "/°

"

,

B , B " B ,/ ,

/

,

"

* 01 &µ(

* 01 &µ(

Figure 11. Line Transient Response

Figure 12. Load Transient Response

:

"

0K

θ' % HA

, °2
9 1

, µ

?

, A

∆D ^ @ * D ^ /

K* " 5 "/ Ω* , C< @ #

5

5

5

"6: >9 1

0E">// 1 , µ

,µ

$$ . " % ! 0@9

+6+ "6: >9 ,/ 5 5 O #D1 % +6+ ) % B %% ! #D1 %

$$ . " % ! % ,@ % ! ! * 5'* +6+ +6+ % B %* B %


Figure 17. Current Boost With Short Circuit Protection


t

!" !

The LM323,A are monolithic integrated circuits which supply a fixed positive 5.0 V output with a load driving capability in excess of 3.0 A. These three–terminal regulators employ internal current limiting, thermal shutdown, and safe–area compensation. The A–suffix is an improved device with superior electrical characteristics and a 2% output voltage tolerance. These regulators are offered with a 0° to +125°C temperature range in a low cost plastic power package. Although designed primarily as a fixed voltage regulator, these devices can be used with external components to obtain adjustable voltages and currents. These devices can be used with a series pass transistor to supply up to 15 A at 5.0 V. • Output Current in Excess of 3.0 A • Available with 2% Output Voltage Tolerance • No External Components Required • Internal Thermal Overload Protection • Internal Short Circuit Current Limiting • Output Transistor Safe–Area Compensation • Thermal Regulation and Ripple Rejection Have Specified Limits

3–AMPERE, 5 VOLT POSITIVE VOLTAGE REGULATORS SEMICONDUCTOR TECHNICAL DATA


+ , " -

1 2 3

Heatsink surface is connected to Pin 2.


Device

Output Voltage Tolerance

LM323T

4%

LM323AT

2%

Operating Temperature Range

Package

TJ = 0° to +125°C

Plastic Power

Simplified Application

µ

A common ground is required between the input and the output voltages. The input voltage must remain typically 2.5 V above the output voltage even during the low point on the input ripple voltage.

*Cin is required if regulator is located an appreciable *distance from power supply filter. (See Applications *Information for details.) **CO is not needed for stability; however, it does **improve transient response.  Semiconductor Components Industries, LLC, 2002


179


LM323, LM323A MAXIMUM RATINGS Symbol

Value

Unit

Input Voltage

Rating

Vin

20

Vdc

Power Dissipation

PD

Internally Limited

W

Operating Junction Temperature Range

TJ

0 to +125

°C


Tstg

–65 to +150

°C

Tsolder

300

°C

Lead Temperature (Soldering, 10 s)

ELECTRICAL CHARACTERISTICS (TJ = Tlow to Thigh [Note 1], unless otherwise noted.) LM323A Characteristics

LM323

Symbol

Min

Typ

Max

Min

Typ

Max

Unit

Output Voltage (Vin = 7.5 V, 0 ≤ Iout ≤ 3.0 A, TJ = 25°C)

VO

4.9

5.0

5.1

4.8

5.0

5.2

V

Output Voltage (7.5 V ≤ Vin ≤ 15 V, 0 ≤ Iout ≤ 3.0 A, P ≤ Pmax) (Note 2)

VO

4.8

5.0

5.2

4.75

5.0

5.25

V

Line Regulation (7.5 V ≤ Vin ≤ 15 V, TJ = 25°C) (Note 3)

Regline

–

1.0

15

–

1.0

25

mV

Load Regulation (Vin = 7.5 V, 0 ≤ Iout ≤ 3.0 A, TJ = 25°C) (Note 3)

Regload

–

10

50

–

10

100

mV

Thermal Regulation (Pulse = 10 ms, P = 20 W, TA = 25°C)

Regtherm

–

0.001

0.01

–

0.002

0.03

%VO/W

Quiescent Current (7.5 V ≤ Vin ≤ 15 V, 0 ≤ Iout ≤ 3.0 A)

IB

–

3.5

10

–

3.5

20

mA

Output Noise Voltage (10 Hz ≤ f ≤ 100 kHz, TJ = 25°C)

VN

–

40

–

–

40

–

µVrms

Ripple Rejection (8.0 V ≤ Vin ≤ 18 V, Iout = 2.0A, f = 120 Hz, TJ = 25°C)

RR

66

75

–

62

75

–

dB

Short Circuit Current Limit (Vin = 15 V, TJ = 25°C) (Vin = 7.5 V, TJ = 25°C)

ISC – –

4.5 5.5

– –

– –

4.5 5.5

– –

S

–

–

35

–

–

35

mV

RΘJC

–

2.0

–

–

2.0

–

°C/W

Long Term Stability Thermal Resistance, Junction–to–Case (Note 4)

A

NOTES: 1. Tlow to Thigh = 0° to +125°C 2. Although power dissipation is internally limited, specifications apply only for P ≤ Pmax = 25 W. 3. Load and line regulation are specified at constant junction temperature. Pulse testing is required with a pulse width ≤ 1.0 ms and a duty cycle ≤ 5%. 4. Without a heatsink, the thermal resistance (RθJA is 65°C/W). With a heatsink, the effective thermal resistance can approach the specified values of 2.0°C/W, depending on the efficiency of the heatsink.


LM323, LM323A Representative Schematic Diagram , A

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VOLTAGE REGULATOR PERFORMANCE

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voltage change per watt. The change in dissipated power can be caused by a change in either input voltage or the load current. Thermal regulation is a function of IC layout and die attach techniques, and usually occurs within 10 ms of a change in power dissipation. After 10 ms, additional changes in the output voltage are due to the temperature coefficient of the device. Figure 1 shows the line and thermal regulation response of a typical LM323A to a 20 W input pulse. The variation of the output voltage due to line regulation is labeled À and the thermal regulation component is labeled Á. Figure 2 shows the load and thermal regulation response of a typical LM323A to a 20 W load pulse. The output voltage variation due to load regulation is labeled À and the thermal regulation component is labeled Á.

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The performance of a voltage regulator is specified by its immunity to changes in load, input voltage, power dissipation, and temperature. Line and load regulation are tested with a pulse of short duration (< 100 µs) and are strictly a function of electrical gain. However, pulse widths of longer duration (> 1.0 ms) are sufficient to affect temperature gradients across the die. These temperature gradients can cause a change in the output voltage, in addition to changes by line and load regulation. Longer pulse widths and thermal gradients make it desirable to specify thermal regulation. Thermal regulation is defined as the change in output voltage caused by a change in dissipated power for a specified time, and is expressed as a percentage output

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Device No. 5%

Nominal Voltage

MC79L05C MC79L12C MC79L15C MC79L18C MC79L24C

MC79L05AC MC79L12AC MC79L15AC MC79L18AC MC79L24AC

–5.0 –12 –15 –18 –24

ORDERING INFORMATION Device

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Package

TJ = 0° to +125°C

Plastic Power

MC79LXXACD*

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Device No. ±10%

MC79LXXACP

SOP–8

MC79LXXCP

Plastic Power

MC79LXXABD* MC79LXXABP*

SOP–8 TJ = –40° to +125°C

Plastic Power

XX indicates nominal voltage  Semiconductor Components Industries, LLC, 2002


185

Publication Order Number: MC79L00/D

MC79L00, MC79L00A Series MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.) Rating

Symbol

Value

Unit

VI

–30 –35 –40

Vdc


Tstg

–65 to +150

°C

Junction Temperature

TJ

+150

°C

Input Voltage (–5 V) Input Voltage (–12, –15, –18 V) Input Voltage (–24 V)

ELECTRICAL CHARACTERISTICS (VI = –10 V, IO = 40 mA, CI = 0.33 µF, CO = 0.1 µF, –40°C < TJ +125°C (for MC79LXXAB), 0°C < TJ < +125°C (for MC79LXXAC)). MC79L05C, AB Characteristics Output Voltage (TJ = +25°C)

MC79L05AC, AB

Symbol

Min

Typ

Max

Min

Typ

Max

Unit

VO

–4.6

–5.0

–5.4

–4.8

–5.0

–5.2

Vdc

– –

– –

200 150

– –

– –

150 100

– –

– –

60 30

– –

– –

60 30

–4.5 –4.5

– –

–5.5 –5.5

–4.75 –4.75

– –

–5.25 –5.25

– –

– –

6.0 5.5

– –

– –

6.0 5.5

– –

– –

1.5 0.2

– –

– –

1.5 0.1

Input Regulation (TJ = +25°C) –7.0 Vdc ≥ VI ≥ –20 Vdc –8.0 Vdc ≥ VI ≥ –20 Vdc

Regline

Load Regulation TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA 1.0 mA ≤ IO ≤ 40 mA

Regload

mV

mV

Output Voltage –7.0 Vdc ≥ VI ≥ –20 Vdc, 1.0 mA ≤ IO ≤ 40 mA VI = –10 Vdc, 1.0 mA ≤ IO ≤ 70 mA

VO

Input Bias Current (TJ = +25°C) (TJ = +125°C)

IIB

Input Bias Current Change –8.0 Vdc ≥ VI ≥ –20 Vdc 1.0 mA ≤ IO ≤ 40 mA

IIB

Output Noise Voltage (TA = +25°C, 10 Hz ≤ f ≤ 100 kHz)

Vn

–

40

–

–

40

–

µV

Ripple Rejection (–8.0 ≥ VI ≥ –18 Vdc, f = 120 Hz, TJ = +25°C)

RR

40

49

–

41

49

–

dB

|VI–VO|

–

1.7

–

–

1.7

–

Vdc

Dropout Voltage (IO = 40 mA, TJ = +25°C)

Vdc

mA

mA

ELECTRICAL CHARACTERISTICS (VI = –19 V, IO = 40 mA, CI = 0.33 µF, CO = 0.1 µF, –40°C < TJ +125°C (for MC79LXXAC), 0°C < TJ < +125°C (for MC79LXXAB)). MC79L12C, AB Characteristics

MC79L12AC, AB

Symbol

Min

Typ

Max

Min

Typ

Max

Unit

Output Voltage (TJ = +25°C)

VO

–11.1

–12

–12.9

–11.5

–12

–12.5

Vdc

Input Regulation (TJ = +25°C) –14.5 Vdc ≥ VI ≥ –27 Vdc –16 Vdc ≥ VI ≥ –27 Vdc

Regline


Regload

mV – –

– –

250 200

– –

– –

250 200

– –

– –

100 50

– –

– –

100 50

–10.8 –10.8

– –

–13.2 –13.2

–11.4 –11.4

– –

–12.6 –12.6

– –

– –

6.5 6.0

– –

– –

6.5 6.0

– –

– –

1.5 0.2

– –

– –

1.5 0.2

mV

Output Voltage –14.5 Vdc ≥ VI ≥ –27 Vdc, 1.0 mA ≤ IO ≤ 40 mA VI = –19 Vdc, 1.0 mA ≤ IO ≤ 70 mA

VO


IIB

Input Bias Current Change –16 Vdc ≥ VI ≥ –27 Vdc 1.0 mA ≤ IO ≤ 40 mA

IIB


Vn

–

80

–

–

80

–

µV

Ripple Rejection (–15 ≤ VI ≤ –25 Vdc, f = 120 Hz, TJ = +25°C)

RR

36

42

–

37

42

–

dB

|VI–VO|

–

1.7

–

–

1.7

–

Vdc

Dropout Voltage (IO = 40 mA, TJ = +25°C)

Vdc

mA

mA


MC79L00, MC79L00A Series ELECTRICAL CHARACTERISTICS (VI = –23 V, IO = 40 mA, CI = 0.33 µF, CO = 0.1 µF, –40°C < TJ +125°C (for MC79LXXAB), 0°C < TJ < +125°C (for MC79LXXAC)). MC79L15C Characteristics

MC79L15AC, AB

Symbol

Min

Typ

Max

Min

Typ

Max

Unit


VO

–13.8

–15

–16.2

–14.4

–15

–15.6

Vdc

Input Regulation (TJ = +25°C) –17.5 Vdc ≥ VI ≥ –30 Vdc –20 Vdc ≥ VI ≥ –30 Vdc

Regline


Regload

mV – –

– –

300 250

– –

– –

300 250

– –

– –

150 75

– –

– –

150 75

–13.5 –13.5

– –

–16.5 –16.5

–14.25 –14.25

– –

–15.75 –15.75

– –

– –

6.5 6.0

– –

– –

6.5 6.0

– –

– –

1.5 0.2

– –

– –

1.5 0.1

mV

Output Voltage –17.5 Vdc ≥ VI ≥ –Vdc, 1.0 mA ≤ IO ≤ 40 mA VI = –23 Vdc, 1.0 mA ≤ IO ≤ 70 mA

VO


IIB


∆IIB


VN

–

90

–

–

90

–

µV

Ripple Rejection (–18.5 ≤ VI ≤ –28.5 Vdc, f = 120 Hz)

RR

33

39

–

34

39

–

dB

|VI–VO|

–

1.7

–

–

1.7

–

Vdc

Dropout Voltage IO = 40 mA, TJ = +25°C

Vdc

mA

mA

ELECTRICAL CHARACTERISTICS (VI = –27 V, IO = 40 mA, CI = 0.33 µF, CO = 0.1 µF, 0°C < TJ > +125°C, unless otherwise noted). MC79L18C Characteristics

MC79L18AC

Symbol

Min

Typ

Max

Min

Typ

Max

Unit


VO

–16.6

–18

–19.4

–17.3

–18

–18.7

Vdc

Input Regulation (TJ = +25°C) –20.7 Vdc ≥ VI ≥ –33 Vdc –21.4 Vdc ≥ VI ≥ –33 Vdc –22 Vdc ≥ VI ≥ –33 Vdc –21 Vdc ≥ VI ≥ –33 Vdc

Regline


Regload

mV – – – –

– – – –

– 325 275 –

– – – –

– – – –

325 – – 275

– –

– –

170 85

– –

– –

170 85

– – –

– –19.8 –19.8

–17.1 – –17.1

– – –

–18.9 – –18.9

– –

– –

6.5 6.0

– –

– –

6.5 6.0

– – –

– – –

– 1.5 0.2

– – –

– – –

1.5 – 0.1

mV

Output Voltage –20.7 Vdc ≥ VI ≥ –33 Vdc, 1.0 mA ≤ IO ≤ 40 mA –21.4 Vdc ≥ VI ≥ –33 Vdc, 1.0 mA ≤ IO ≤ 40 mA VI = –27 Vdc, 1.0 mA ≤ IO ≤ 70 mA

VO


IIB

Input Bias Current Change –21 Vdc ≥ VI ≥ –33 Vdc –27 Vdc ≥ VI ≥ –33 Vdc 1.0 mA ≤ IO ≤ 40 mA

IIB


Vn

–

150

–

–

150

–

µV


RR

32

46

–

33

48

–

dB

|VI–VO|

–

1.7

–

–

1.7

–

Vdc


Vdc – –16.2 –16.2

mA

mA


MC79L00, MC79L00A Series ELECTRICAL CHARACTERISTICS (VI = –33 V, IO = 40 mA, CI = 0.33 µF, CO = 0.1 µF, 0°C < TJ < +125°C, unless otherwise noted). MC79L24C Characteristics

MC79L24AC

Symbol

Min

Typ

Max

Min

Typ

Max

Unit


VO

–22.1

–24

–25.9

–23

–24

–25

Vdc

Input Regulation (TJ = +25°C) –27 Vdc ≥ VI ≥ –38 Vdc –27.5 Vdc ≥ VI ≥ –38 Vdc –28 Vdc ≥ VI ≥ –38 Vdc

Regline


Regload

mV – – –

– – –

– 350 300

– – –

– – –

350 – 300

– –

– –

200 100

– –

– –

200 100

– –21.4 –21.4

– – –

– –26.4 –26.4

–22.8 – –22.8

– – –

–25.2 – –25.2

– –

– –

6.5 6.0

– –

– –

6.5 6.0

– –

– –

1.5 0.2

– –

– –

1.5 0.1

mV

Output Voltage –27 Vdc ≥ VI ≥ –38 V, 1.0 mA ≤ IO ≤ 40 mA –28 Vdc ≥ VI ≥ –38 Vdc, 1.0 mA ≤ IO ≤ 40 mA VI = –33 Vdc, 1.0 mA ≤ IO ≤ 70 mA

VO


IIB


∆IIB


Vn

–

200

–

–

200

–

µV


RR

30

43

–

31

47

–

dB

|VI–VO|

–

1.7

–

–

1.7

–

Vdc


Vdc

mA

mA

APPLICATIONS INFORMATION Design Considerations

high–frequency characteristics to insure stable operation under all load conditions. A 0.33 µF or larger tantalum, mylar, or other capacitor having low internal impedance at high frequencies should be chosen. The bypass capacitor should be mounted with the shortest possible leads directly across the regulator’s input terminals. Normally good construction techniques should be used to minimize ground loops and lead resistance drops since the regulator has no external sense lead. Bypassing the output is also recommended.

The MC79L00, A Series of fixed voltage regulators are designed with Thermal Overload Protections that shuts down the circuit when subjected to an excessive power overload condition, Internal Short Circuit Protection that limits the maximum current the circuit will pass. In many low current applications, compensation capacitors are not required. However, it is recommended that the regulator input be bypassed with a capacitor if the regulator is connected to the power supply filter with long wire length, or if the output load capacitance is large. An input bypass capacitor should be selected to provide good

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NOTES: 1. Load and line regulation are specified at constant temperature. Change in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. 2. B = Tlow to Thigh, –40°C < TJ < 125°C C = Tlow to Thigh, 0°C < TJ < 125°C

The MC7900 series of fixed output negative voltage regulators are intended as complements to the popular MC7800 series devices. These negative regulators are available in the same seven–voltage options as the MC7800 devices. In addition, one extra voltage option commonly employed in MECL systems is also available in the negative MC7900 series. Available in fixed output voltage options from –5.0 V to –24 V, these regulators employ current limiting, thermal shutdown, and safe–area compensation – making them remarkably rugged under most operating conditions. With adequate heatsinking they can deliver output currents in excess of 1.0 A. • No External Components Required • Internal Thermal Overload Protection • Internal Short Circuit Current Limiting • Output Transistor Safe–Area Compensation • Available in 2% Voltage Tolerance (See Ordering Information)

http://onsemi.com

TO–220 T SUFFIX CASE 221A Heatsink surface connected to Pin 2.

1 2 3

Pin 1. Ground 2. Input 3. Output D2PAK D2T SUFFIX CASE 936

1

2 3

Heatsink surface (shown as terminal 4 in case outline drawing) is connected to Pin 2.

STANDARD APPLICATION

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A common ground is required between the input and the output voltages. The input voltage must remain typically 2.0 V above more negative even during the high point of the input ripple voltage.

ORDERING INFORMATION %

Figure 1. Representative Schematic Diagram

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XX, These two digits of the type number indicate nominal voltage. ** Cin is required if regulator is located an appreciable distance from power supply filter. ** CO improve stability and transient response.

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See detailed ordering and shipping information in the package dimensions section on page 204 of this data sheet.

DEVICE MARKING INFORMATION See general marking information in the device marking section on page 205 of this data sheet.



194


MC7900 Series MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.) Symbol

Value

Unit

VI

–35 –40

Vdc

PD θJA θJC


W °C/W °C/W

PD θJA θJC


W °C/W °C/W

Storage Junction Temperature Range

Tstg

–65 to +150

°C


TJ

+150

°C

Symbol

Max

Unit

Rating Input Voltage (–5.0 V ≥ VO ≥ –18 V) Input Voltage (24 V) Power Dissipation Case 221A TA = +25°C Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case Case 936 (D2PAK) TA = +25°C Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case

THERMAL CHARACTERISTICS Characteristics Thermal Resistance, Junction–to–Ambient

RθJA

65

°C/W

Thermal Resistance, Junction–to–Case

RθJC

5.0

°C/W

MC7905C ELECTRICAL CHARACTERISTICS (VI = –10 V, IO = 500 mA, 0°C < TJ < +125°C, unless otherwise noted.) Characteristics

Symbol

Min

Typ

Max

Unit


VO

–4.8

–5.0

–5.2

Vdc

Line Regulation (Note 1) (TJ = +25°C, IO = 100 mA) –7.0 Vdc ≥ VI ≥ –25 Vdc –8.0 Vdc ≥ VI ≥ –12 Vdc (TJ = +25°C, IO = 500 mA) –7.0 Vdc ≥ VI ≥ –25 Vdc –8.0 Vdc ≥ VI ≥ –12 Vdc

Regline

Load Regulation, TJ = +25°C (Note 1) 5.0 mA ≤ IO ≤ 1.5 A 250 mA ≤ IO ≤ 750 mA

Regload

Output Voltage –7.0 Vdc ≥ VI ≥ –20 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, P ≤ 15 W

VO

Input Bias Current (TJ = +25°C)

IIB

mV – –

7.0 2.0

50 25

– –

35 8.0

100 50

– –

11 4.0

100 50

–@4.75

–

–@5.25

–

4.3

8.0

– –

– –

1.3 0.5

mV

Vdc mA

Input Bias Current Change –7.0 Vdc ≥ VI ≥ –25 Vdc 5.0 mA ≤ IO ≤ 1.5 A

∆IIB


Vn

–

40

–

µV

Ripple Rejection (IO = 20 mA, f = 120 Hz)

RR

–

70

–

dB

–

2.0

–

–

–1.0

–

Dropout Voltage IO = 1.0 A, TJ = +25°C

mA

VI–VO

Vdc

∆VO/∆T

Average Temperature Coefficient of Output Voltage IO = 5.0 mA, 0°C ≤ TJ ≤ +125°C

mV/°C

1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used.


MC7900 Series MC7905AC ELECTRICAL CHARACTERISTICS (VI = –10 V, IO = 500 mA, 0°C < TJ < +125°C, unless otherwise noted.) Characteristics Output Voltage (TJ = +25°C)

Symbol

Min

Typ

Max

Unit

VO

–4.9

–5.0

–5.1

Vdc

– – – –

2.0 7.0 7.0 6.0

25 50 50 50

– – –

11 4.0 9.0

100 50 100

–4.80

–

–5.20

–

4.4

8.0

– – –

– – –

1.3 0.5 0.5

40

–

Line Regulation (Note 2) –8.0 Vdc ≥ VI ≥ –12 Vdc; IO = 1.0 A, TJ = +25°C –8.0 Vdc ≥ VI ≥ –12 Vdc; IO = 1.0 A –7.5 Vdc ≥ VI ≥ –25 Vdc; IO = 500 mA –7.0 Vdc ≥ VI ≥ –20 Vdc; IO = 1.0 A, TJ = +25°C

Regline

Load Regulation (Note 2) 5.0 mA ≤ IO ≤ 1.5 A, TJ = +25°C 250 mA ≤ IO ≤ 750 mA 5.0 mA ≤ IO ≤ 1.0 A

Regload


mV

mV

VO

Input Bias Current

IIB

Vdc mA

Input Bias Current Change –7.5 Vdc ≥ VI ≥ –25 Vdc 5.0 mA ≤ IO ≤ 1.0 A 5.0 mA ≤ IO ≤ 1.5 A, TJ = +25°C

∆IIB


Vn

–

RR

–

70

–

dB

VI–VO

–

2.0

–

Vdc

–

–1.0

–

Ripple Rejection (IO = mA, f = 120 Hz) Dropout Voltage (IO = 1.0 A. TJ = +25°C)

mA

∆VO/∆T

Average Temperature Coefficient of Output Voltage IO = 5.0 A, 0°C ≤ TJ ≤ +125°C

µV

mV/°C

MC7905.2C ELECTRICAL CHARACTERISTICS (VI = –10 V, IO = 500 mA, 0°C < TJ < +125°C, unless otherwise noted.) Characteristics

Symbol

Min

Typ

Max

Unit


VO

–5.0

–5.2

–5.4

Vdc


Regline


Regload


VO


IIB

mV – –

8.0 2.2

52 27

– –

37 8.5

105 52

– –

12 4.5

105 52

–4.95

–

–5.45

–

4.3

8.0

– –

– –

1.3 0.5

mV

Vdc mA


∆IIB


Vn

–

42

–

µV


RR

–

68

–

dB

VI–VO

–

2.0

–


mA

∆VO/∆T


Vdc mV/°C

–

–1.0

–



MC7900 Series MC7906C ELECTRICAL CHARACTERISTICS (VI = –11 V, IO = 500 mA, 0°C < TJ < +125°C, unless otherwise noted.) Characteristics

Symbol

Min

Typ

Max

Unit


VO

–5.75

–6.0

–6.25

Vdc


Regline


Regload


VO


IIB

mV – –

9.0 3.0

60 30

– –

43 10

120 60

– –

13 5.0

120 60

–5.7

–

–6.3

–

4.3

8.0

– –

– –

1.3 0.5

45

–

mV

Vdc mA


∆IIB


Vn

–


RR

–

65

–

dB


VI–VO

–

2.0

–

Vdc

–

–1.0

–

mA

∆VO/∆T


µV

mV/°C

MC7908C ELECTRICAL CHARACTERISTICS (VI = –14 V, IO = 500 mA, 0°C < TJ < +125°C, unless otherwise noted.) Characteristics Output Voltage (TJ = +25°C)

Symbol

Min

Typ

Max

Unit

VO

–7.7

–8.0

–8.3

Vdc

Line Regulation (Note 3) (TJ = +25°C, IO = 100 mA) –10.5 Vdc ≥ VI ≥ –25 Vdc –11 Vdc ≥ VI ≥ –17 Vdc (TJ = +25°C, IO = 500 mA) –10.5 Vdc ≥ VI ≥ –25 Vdc –11 Vdc ≥ VI ≥ –17 Vdc

Regline


Regload


VO


IIB

mV – –

12 5.0

80 40

– –

50 22

160 80

– –

26 9.0

160 80

–7.6

–

–8.4

–

4.3

8.0

– –

– –

1.0 0.5

mV

Vdc mA


∆IIB


Vn

–

52

–

µV


RR

–

62

–

dB

VI–VO

–

2.0

–


mA

∆VO/∆T


Vdc mV/°C

–

–1.0

–



MC7900 Series MC7912C ELECTRICAL CHARACTERISTICS (VI = –19 V, IO = 500 mA, 0°C < TJ < +125°C, unless otherwise noted.) Characteristics Output Voltage (TJ = +25°C)

Symbol

Min

Typ

Max

Unit

VO

–11.5

–12

–12.5

Vdc


Regline


Regload


VO


IIB

mV – –

13 6.0

120 60

– –

55 24

240 120

– –

46 17

240 120

–11.4

–

–12.6

–

4.4

8.0

– –

– –

1.0 0.5

75

–

mV

Vdc mA


∆IIB


Vn

–


RR

–

61

–

dB


VI–VO

–

2.0

–

Vdc

–

–1.0

–

mA

∆VO/∆T


µV

mV/°C

MC7912AC ELECTRICAL CHARACTERISTICS (VI = –19 V, IO = 500 mA, 0°C < TJ < +125°C, unless otherwise noted.) Characteristics Output Voltage (TJ = +25°C)

Symbol

Min

Typ

Max

Unit

VO

–11.75

–12

–12.25

Vdc

– – – –

6.0 24 24 13

60 120 120 120

– – –

46 17 35

150 75 150

–11.5

–

–12.5

–

4.4

8.0

– – –

– – –

0.8 0.5 0.5

Line Regulation (Note 4) –16 Vdc ≥ VI ≥ –22 Vdc; IO = 1.0 A, TJ = +25°C –16 Vdc ≥ VI ≥ –22 Vdc; IO = 1.0 A –14.8 Vdc ≥ VI ≥ –30 Vdc; IO = 500 mA –14.5 Vdc ≥ VI ≥ –27 Vdc; IO = 1.0 A, TJ = +25°C

Regline


Regload


VO

Input Bias Current

IIB

mV

mV

Vdc mA

Input Bias Current Change –15 Vdc ≥ VI ≥ –30 Vdc 5.0 mA ≤ IO ≤ 1.0 A 5.0 mA ≤ IO ≤ 1.5 A, TJ = +25°C

∆IIB


Vn

–

75

–

µV


RR

–

61

–

dB

VI–VO

–

2.0

–


mA

∆VO/∆T


Vdc mV/°C

–

–1.0

–



MC7900 Series MC7915C ELECTRICAL CHARACTERISTICS (VI = –23 V, IO = 500 mA, 0°C < TJ < +125°C, unless otherwise noted.) Characteristics Output Voltage (TJ = +25°C)

Symbol

Min

Typ

Max

Unit

VO

–14.4

–15

–15.6

Vdc


Regline


Regload


VO


IIB

mV – –

14 6.0

150 75

– –

57 27

300 150

– –

68 25

300 150

–14.25

–

–15.75

–

4.4

8.0

– –

– –

1.0 0.5

90

–

mV

Vdc mA


∆IIB


Vn

–


RR

–

60

–

dB


VI–VO

–

2.0

–

Vdc

–

–1.0

–

mA

∆VO/∆T


µV

mV/°C

MC7915AC ELECTRICAL CHARACTERISTICS (VI = –23 V, IO = 500 mA, 0°C < TJ < +125°C, unless otherwise noted.) Characteristics Output Voltage (TJ = +25°C)

Symbol

Min

Typ

Max

Unit

VO

–14.7

–15

–15.3

Vdc

– – – –

27 57 57 57

75 150 150 150

– – –

68 25 40

150 75 150

–14.4

–

–15.6

–

4.4

8.0

– – –

– – –

0.8 0.5 0.5

Line Regulation (Note 5) –20 Vdc ≥ VI ≥ –26 Vdc, IO = 1.0 A, TJ = +25°C –20 Vdc ≥ VI ≥ –26 Vdc, IO = 1.0 A, –17.9 Vdc ≥ VI ≥ –30 Vdc, IO = 500 mA –17.5 Vdc ≥ VI ≥ –30 Vdc, IO = 1.0 A, TJ = +25°C

Regline


Regload


VO

Input Bias Current

IIB

mV

mV

Vdc mA

Input Bias Current Change –17.5 Vdc ≥ VI ≥ –30 Vdc 5.0 mA ≤ IO ≤ 1.0 A 5.0 mA ≤ IO ≤ 1.5 A, TJ = +25°C

∆IIB


Vn

–

90

–

µV


RR

–

60

–

dB

VI–VO

–

2.0

–


mA

∆VO/∆T


Vdc mV/°C

–

–1.0

–



MC7900 Series MC7918C ELECTRICAL CHARACTERISTICS (VI = –27 V, IO = 500 mA, 0°C < TJ < +125°C, unless otherwise noted.) Characteristics

Symbol

Min

Typ

Max

Unit


VO

–17.3

–18

–18.7

Vdc

Line Regulation (Note 6) (TJ = +25°C, IO = 100 mA) –21 Vdc ≥ VI ≥ –33 Vdc –24 Vdc ≥ VI ≥ –30 Vdc (TJ = +25°C, IO = 500 mA) –21 Vdc ≥ VI ≥ –33 Vdc –24 Vdc ≥ VI ≥ –30 Vdc

Regline


Regload

Output Voltage –21 Vdc ≥ VI ≥ –33 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, P ≤ 15 W

VO


IIB

mV – –

25 10

180 90

– –

90 50

360 180

– –

110 55

360 180

–17.1

–

–18.9

–

4.5

8.0

– –

– –

1.0 0.5

110

–

mV

Vdc mA

Input Bias Current Change –21 Vdc ≥ VI ≥ –33 Vdc 5.0 mA ≤ IO ≤ 1.5 A

∆IIB


Vn

–


RR

–

59

–

dB


VI–VO

–

2.0

–

Vdc

–

–1.0

–

mA

∆VO/∆T


µV

mV/°C

MC7924C ELECTRICAL CHARACTERISTICS (VI = –33 V, IO = 500 mA, 0°C < TJ < +125°C, unless otherwise noted.) Characteristics

Symbol

Min

Typ

Max

Unit


VO

–23

–24

–25

Vdc

Line Regulation (Note 6) (TJ = +25°C, IO = 100 mA) –27 Vdc ≥ VI ≥ –38 Vdc –30 Vdc ≥ VI ≥ –36 Vdc (TJ = +25°C, IO = 500 mA) –27 Vdc ≥ VI ≥ –38 Vdc –30 Vdc ≥ VI ≥ –36 Vdc

Regline


Regload

Output Voltage –27 Vdc ≥ VI ≥ –38 Vdc, 5.0 mA ≤ IO ≤ 1.0 A, P ≤ 15 W

VO


IIB

mV – –

31 14

240 120

– –

118 70

470 240

– –

150 85

480 240

–22.8

–

–25.2

–

4.6

8.0

– –

– –

1.0 0.5

mV

Vdc mA

Input Bias Current Change –27 Vdc ≥ VI ≥ –38 Vdc 5.0 mA ≤ IO ≤ 1.5 A

∆IIB


Vn

–

170

–

µV


RR

–

56

–

dB

VI–VO

–

2.0

–


mA

∆VO/∆T


Vdc mV/°C

–

–1.0

–



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Figure 2. Worst Case Power Dissipation as a Function of Ambient Temperature

Figure 3. Peak Output Current as a Function of Input–Output Differential Voltage

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Figure 21. Slow Turn–On Regulator



$% !" # The LM317M is an adjustable three–terminal positive voltage regulator capable of supplying in excess of 500 mA over an output voltage range of 1.2 V to 37 V. This voltage regulator is exceptionally easy to use and requires only two external resistors to set the output voltage. Further, it employs internal current limiting, thermal shutdown and safe area compensation, making it essentially blow–out proof. The LM317M serves a wide variety of applications including local, on–card regulation. This device also makes an especially simple adjustable switching regulator, a programmable output regulator, or by connecting a fixed resistor between the adjustment and output, the LM317M can be used as a precision current regulator. • Output Current in Excess of 500 mA • Output Adjustable between 1.2 V and 37 V • Internal Thermal Overload Protection • Internal Short Circuit Current Limiting • Output Transistor Safe–Area Compensation • Floating Operation for High Voltage Applications • Eliminates Stocking Many Fixed Voltages

http://onsemi.com Heatsink surface connected to Pin 2

1

2

%

%

LM317M

0 M

µ

3

TO–220AB T SUFFIX CASE 221A

SOT–223 ST SUFFIX CASE 318E

1

%

2

3

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C µ

1

2 3

Heatsink Surface (shown as terminal 4 in case outline drawing) is connected to Pin 2.

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Vout

3

Vin


Figure 1. Simplified Application


1

214

Publication Order Number: LM317M/D

LM317M MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.) Rating

Symbol

Value

Unit

VI–VO

40

Vdc

PD θJA θJC


°C/W °C/W

PD θJA θJC


°C/W °C/W

PD θJA θJC

Internally Limited 245 15

°C/W °C/W


TJ

–40 to +125

°C


Tstg

–65 to +150

°C

Input–Output Voltage Differential Power Dissipation (Package Limitation) (Note 1) Plastic Package, T Suffix, Case 221A TA = 25°C Thermal Resistance, Junction–to–Air Thermal Resistance, Junction–to–Case Plastic Package, DT Suffix, Case 369A TA = 25°C Thermal Resistance, Junction–to–Air Thermal Resistance, Junction–to–Case Plastic Package, ST Suffix, Case 318E TA = 25°C Thermal Resistance, Junction–to–Air Thermal Resistance, Junction–to–Case

ELECTRICAL CHARACTERISTICS (VI–VO = 5.0 V; IO = 0.1 A, TJ = Tlow to Thigh [Note 2], unless otherwise noted.) Figure

Symbol

Min

Typ

Max

Unit

Line Regulation (Note 3) TA = 25°C, 3.0 V ≤ VI–VO ≤ 40 V

3

Regline

–

0.01

0.04

%/V

Load Regulation (Note 3) TA = 25°C, 10 mA ≤ IO ≤ 0.5 A VO ≤ 5.0 V VO ≥ 5.0 V

4

Regload – –

5.0 0.1

25 0.5

mV % VO

Adjustment Pin Current

5

IAdj

–

50

100

µA

Adjustment Pin Current Change 2.5 V ≤ VI–VO ≤ 40 V, 10 mA ≤ IL ≤ 0.5 A, PD ≤ Pmax

3,4

∆IAdj

–

0.2

5.0

µA

Reference Voltage 3.0 V ≤ VI–VO ≤ 40 V, 10 mA ≤ IO ≤ 0.5 A, PD ≤ Pmax:

5

Vref 1.200

1.250

1.300

Line Regulation (Note 3) 3.0 V ≤ VI–VO ≤ 40 V

3

Regline

–

0.02

0.07

%/V

Load Regulation (Note 3) 10 mA ≤ IO ≤ 0.5 A VO ≤ 5.0 V VO ≥ 5.0 V

4

Regload – –

20 0.3

70 1.5

mV % VO

Temperature Stability (Tlow ≤ TJ ≤ Thigh)

5

TS

–

0.7

–

% VO

Minimum Load Current to Maintain Regulation (VI–VO = 40 V)

5

ILmin

–

3.5

10

mA

Maximum Output Current VI–VO ≤ 15 V, PD ≤ Pmax VI–VO = 40 V, PD ≤ Pmax, TA = 25°C

5

Imax 0.5 0.15

0.9 0.25

– –

RMS Noise, % of VO TA= 25°C, 10 Hz ≤ f ≤ 10 kHz

–

N

–

0.003

–

Ripple Rejection, VO = 10 V, f = 120 Hz (Note 4) Without CAdj CAdj = 10 µF

6

RR – 66

65 80

– –

Long–Term Stability, TJ = Thigh (Note 5) TA= 25°C for Endpoint Measurements

5

–

0.3

1.0

Characteristics

S

V

A

% VO dB

%/1.0 k Hrs.

1. Figure 25 provides thermal resistance versus pc board pad size. Tlow to Thigh = –@40° to +125°C for LM317MB 2. Tlow to Thigh = 0° to +125°C for LM317M 3. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. 4. CAdj, when used, is connected between the adjustment pin and ground. 5. Since Long–Term Stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability from lot to lot.


LM317M %

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µ

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% 1 $ B % > 1 $ % 1 $

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Figure 4. Load Regulation and ∆IAdj/Load Test Circuit


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Figure 26. SOT–223 Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length


LM317M ORDERING INFORMATION Operating Temperature Range

Package

Shipping

LM317MT

Device

TJ = 0°C to 125°C

TO–220

50 units/rail

LM317MDT

TJ = 0°C to 125°C

DPAK

75 units/rail

LM317MDTRK

TJ = 0°C to 125°C

DPAK

2500 units/Tape & Reel

LM317MSTT3

TJ = 0°C to 125°C

SOT–223


LM317MBT

TJ = –40°C to 125°C

TO–220

50 units/rail

LM317MBDT

TJ = –40°C to 125°C

DPAK

75 units/rail

LM317MBDTRK

TJ = –40°C to 125°C

DPAK


LM317MBSTT3

TJ = –40°C to 125°C

SOT–223



t

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!" # The LM317 is an adjustable 3–terminal positive voltage regulator capable of supplying in excess of 1.5 A over an output voltage range of 1.2 V to 37 V. This voltage regulator is exceptionally easy to use and requires only two external resistors to set the output voltage. Further, it employs internal current limiting, thermal shutdown and safe area compensation, making it essentially blow–out proof. The LM317 serves a wide variety of applications including local, on card regulation. This device can also be used to make a programmable output regulator, or by connecting a fixed resistor between the adjustment and output, the LM317 can be used as a precision current regulator. • Output Current in Excess of 1.5 A • Output Adjustable between 1.2 V and 37 V • Internal Thermal Overload Protection • Internal Short Circuit Current Limiting Constant with Temperature • Output Transistor Safe–Area Compensation • Floating Operation for High Voltage Applications • Available in Surface Mount D2PAK, and Standard 3–Lead Transistor Package • Eliminates Stocking many Fixed Voltages

Standard Application %

SEMICONDUCTOR TECHNICAL DATA


2 3

0 M % %

+ "

0 M

0 M

µ

1

D2T SUFFIX PLASTIC PACKAGE CASE 936 (D2PAK)

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LM317

THREE–TERMINAL ADJUSTABLE POSITIVE VOLTAGE REGULATOR

1

2 3

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LM317BT

Operating Temperature Range TJ = –40° to +125°C

LM317D2T LM317T

Package Surface Mount Insertion Mount Surface Mount

TJ = 0° to +125°C

Insertion Mount

2 0 M !! ! µ0, #!#G!

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224


LM317 MAXIMUM RATINGS Rating

Symbol

Value

Unit

VI–VO

40

Vdc

PD θJA θJC


W °C/W °C/W

PD θJA θJC


W °C/W °C/W


TJ

–40 to +125

°C


Tstg

–65 to +150

°C

Input–Output Voltage Differential Power Dissipation Case 221A TA = +25°C Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case Case 936 (D2PAK) TA = +25°C Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case

ELECTRICAL CHARACTERISTICS (VI–VO = 5.0 V; IO = 0.5 A for D2T and T packages; TJ = Tlow to Thigh [Note 1]; Imax and Pmax [Note 2]; unless otherwise noted.) Characteristics

Figure

Symbol

Min

Typ

Max

Unit

Line Regulation (Note 3), TA = +25°C, 3.0 V ≤ VI–VO ≤ 40 V

1

Regline

–

0.01

0.04

%/V

Load Regulation (Note 3), TA = +25°C, 10 mA ≤ IO ≤ Imax VO ≤ 5.0 V VO ≥ 5.0 V

2

Regload – –

5.0 0.1

25 0.5

mV % VO

Thermal Regulation, TA = +25°C (Note 6), 20 ms Pulse

Regtherm

–

0.03

0.07

% VO/W

3

IAdj

–

50

100

µA

1, 2

∆IAdj

–

0.2

5.0

µA

Reference Voltage, 3.0 V ≤ VI–VO ≤ 40 V, 10 mA ≤ IO ≤ Imax, PD ≤ Pmax

3

Vref

1.2

1.25

1.3

V

Line Regulation (Note 3), 3.0 V ≤ VI–VO ≤ 40 V

1

Regline

–

0.02

0.07

%V

Load Regulation (Note 3), 10 mA ≤ IO ≤ Imax VO ≤ 5.0 V VO ≥ 5.0 V

2

Regload – –

20 0.3

70 1.5

mV % VO

Temperature Stability (Tlow ≤ TJ ≤ Thigh)

3

TS

–

0.7

–

% VO

Minimum Load Current to Maintain Regulation (VI–VO = 40 V)

3

ILmin

–

3.5

10

mA

Maximum Output Current VI–VO ≤ 15 V, PD ≤ Pmax, T Package VI–VO = 40 V, PD ≤ Pmax, TA = +25°C, T Package

3

Imax 1.5 0.15

2.2 0.4

– –

–

0.003

–

– 66

65 80

– –

S

–

0.3

1.0

%/1.0 k Hrs.

RθJC

–

5.0

–

°C/W

Adjustment Pin Current Adjustment Pin Current Change, 2.5 V ≤ VI–VO ≤ 40 V, 10 mA ≤ IL ≤ Imax, PD ≤ Pmax

RMS Noise, % of VO, TA = +25°C, 10 Hz ≤ f ≤ 10 kHz

N

Ripple Rejection, VO = 10 V, f = 120 Hz (Note 4) Without CAdj CAdj = 10 µF

4

Long–Term Stability, TJ = Thigh (Note 5), TA = +25°C for Endpoint Measurements

3

Thermal Resistance Junction to Case, T Package

A

RR

% VO dB

NOTES: 1. Tlow to Thigh = 0° to +125°C, for LM317T, D2T. Tlow to Thigh = –40° to +125°C, for LM317BT, BD2T. 2. Imax = 1.5 A, Pmax = 20 W 3. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. 4. CAdj, when used, is connected between the adjustment pin and ground. 5. Since Long–Term Stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability from lot to lot. 6. Power dissipation within an IC voltage regulator produces a temperature gradient on the die, affecting individual IC components on the die. These effects can be minimized by proper integrated circuit design and layout techniques. Thermal Regulation is the effect of these temperature gradients on the output voltage and is expressed in percentage of output change per watt of power change in a specified time.


LM317 Representative Schematic Diagram

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LM317 %

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# / # / B $:HD:@K 0.A1


Figure 14. Output Impedance

∆ BC%D>(D> %2>"):C ∆ BC%D>(D> %2>"):C."@):C01 %2>"):CE = ° 2 = # µ$

# +#

+# +

#

#

#

-#

B >'G: 0µ1

B >'G: 0µ1




# G

#

LM337 APPLICATIONS INFORMATION Basic Circuit Operation

The LM337 is a 3–terminal floating regulator. In operation, the LM337 develops and maintains a nominal –1.25 V reference (Vref) between its output and adjustment terminals. This reference voltage is converted to a programming current (IPROG) by R1 (see Figure 17), and this constant current flows through R2 from ground. The regulated output voltage is given by:

External Capacitors

A 1.0 µF tantalum input bypass capacitor (Cin) is recommended to reduce the sensitivity to input line impedance. The adjustment terminal may be bypassed to ground to improve ripple rejection. This capacitor (CAdj) prevents ripple from being amplified as the output voltage is increased. A 10 µF capacitor should improve ripple rejection about 15 dB at 120 Hz in a 10 V application. An output capacitance (CO) in the form of a 1.0 µF tantalum or 10 µF aluminum electrolytic capacitor is required for stability.

Ǔ

+ ) ) ' ",

Since the current into the adjustment terminal (IAdj) represents an error term in the equation, the LM337 was designed to control IAdj to less than 100 µA and keep it constant. To do this, all quiescent operating current is returned to the output terminal. This imposes the requirement for a minimum load current. If the load current is less than this minimum, the output voltage will rise. Since the LM337 is a floating regulator, it is only the voltage differential across the circuit which is important to performance, and operation at high voltages with respect to ground is possible.

Protection Diodes

When external capacitors are used with any IC regulator it is sometimes necessary to add protection diodes to prevent the capacitors from discharging through low current points into the regulator. Figure 18 shows the LM337 with the recommended protection diodes for output voltages in excess of –25 V or high capacitance values (CO > 25 µF, CAdj > 10 µF). Diode D1 prevents CO from discharging thru the IC during an input short circuit. Diode D2 protects against capacitor CAdj discharging through the IC during an output short circuit. The combination of diodes D1 and D2 prevents CAdj from the discharging through the IC during an input short circuit.

* '(%)

'", ",

LM337

*

%

+

= + >!

Figure 17. Basic Circuit Configuration

",

Load Regulation +

The LM337 is capable of providing extremely good load regulation, but a few precautions are needed to obtain maximum performance. For best performance, the programming resistor (R1) should be connected as close to the regulator as possible to minimize line drops which effectively appear in series with the reference, thereby

ED@>'%@N>%N"'C0CCOJ1 °

θ E"BC>.:G"2C:F'F>"@:

LM337

-#

$ " G !

6#

# A 2

G FA (

#

ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ

#

2

#

θE" #

#

%

< @##

*

+

Figure 18. Voltage Regulator with Protection Diodes (" = * #°

8#

*

*

" = °

-#

% BC%D>(D>C%2>"):C01

% BC%D>(D>C%2>"):C01

- '% = # "

7 '% = # "

6 '% = # "

8

G872-#@> 9

-

>" = °

7 8

G872-#@> #

>" = 7#° #

6#

7#

##

#

'%B %D>(D> D:@> 0"1

Figure 2. Output Voltage versus Input Voltage

Figure 3. Output Voltage versus Output Current

-#

6

% BC%D>(D>C%2>"):C01

+% BC<%(%D>C%2>"):C01

9

B '@(D> %2>"): 01

#

#7 # #

>" = +-#°

-#

# #

-

--

-

G872-#@> >" = ° #

#

#

-#

#

-#6

= # '%= # "

-# 97 9 G872-#@> 9# +#

#

'%B %D>(D> D:@> 0"1

+ #

#

#

#

6#

>"B "GI':@> >:G(:">D: 0°1

Figure 4. Dropout Voltage versus Output Current

Figure 5. Output Voltage versus Temperature


7#

MC78LC00 Series

-

>" = °

'BCHD':F:@>CD:@>C0CCC"1 µ

'BCHD':F:@>CD:@>C0CCC"1 µ

# #9 #7 -#

G872-#@> #

#

6#

8#

7#

9#

# #9 #7 #8

G872-#@>

#6 +#

#

+ #

#

#

#

6#

7#

B '@(D> %2>"): 01

>"B "GI':@> >:G(:">D: 0°1


Figure 7. Quiescent Current versus Temperature

'@(D>C%2>"):O%D>(D>C%2>"):C01

#7 +% BC<%(%D>C%2>"):C01

= #

#8 #6

'% = # "

#

# ## # # #

'% = # " #

#

-#

#

#

6#

7# 8

'

8# 6

6#

%

# % = # µ$ '% = # "

#

#

#

#

%B F:> %D>(D> %2>"): 01

B >'G: 01

Figure 8. Dropout Voltage versus Set Output Voltage



6#

MC78LC00 Series APPLICATIONS INFORMATION Introduction

electrolyte freezes, around –30°C, the capacitance will decrease and the equivalent series resistance (ESR) will increase drastically, causing the circuit to oscillate. Quality electrolytic capacitors with extended temperature ranges of –40° to +85°C are readily available. Solid tantalum capacitors may be the better choice if small size is a requirement. However, a maximum ESR limit of 3.0 Ω must be observed over temperature to maintain stability. In the Current Boost Circuit, shown in Figures 11 and 13, an output current of up to 600 mA can be delivered by the circuit. The circuit of Figure 11 has no current limit. In each case, the external transistor must be rated for the expected power dissipation. Figure 12 shows how a fixed output may be programmed, using R1 and R2, to provide a higher output voltage.

The MC78LC00 micropower voltage regulators are specifically designed with high accuracy output voltage and ultra low quiescent current by CMOS process making them ideal for battery powered applications and hand–held communication equipment. An input bypass capacitor is recommended if the regulator is located an appreciable distance (≥ 4 inches) from the input voltage source. These regulators require ≥ 0.1 µF capacitance between the output terminal and ground for stability. Most types of aluminum, tantalum or multilayer ceramic will perform adequately. Solid tantalums or other appropriate capacitors are recommended for operation below 25°C. The bypass capacitors should be mounted with the shortest possible leads or track lengths directly across the regulator input and output terminals. With economical electrolytic capacitors, cold temperature operation can pose a serious stability problem. As the

MJD32C

-

%

MC78LC00 # µ$

# µ$

)

##

)

#-- µ$

MC78LC00

-

%

# µ$

# µ$ )

)

Figure 10. Typical Application

MC78LC00

Figure 11. Current Boost Circuit

'

%

)

H

MJD32C H

MMBT2907 ALT1

#-- µ$

# µ$

MC78LC00

-

ǒ

Ǔ

'

Figure 12. Adjustable VO

) I: [ I: ) I: %0 1

Figure 13. Current Boost Circuit with Overcurrent Limit Circuit


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)

+ ) ) ' % %01

%

MC78LC00 Series ORDERING INFORMATION Nominal Output Voltage

Marking

Package

Shipping

MC78LC30NTR

3.0

0C

SOT–23

3000 Units/7″ Tape & Reel

MC78LC30HT1 MC78LC33HT1 MC78LC40HT1 MC78LC50HT1

3.0 3.3 4.0 5.0

0C 3C 0D 0E

SOT–89

1000 Units Tape & Reel

Device

Additional voltages in 100 mV steps are available upon request by contacting your ON Semiconductor representative.


"

!&

' %( % ) %* $ +,, " The MC33761 is an Low DropOut (LDO) regulator featuring excellent noise performances. Thanks to its innovative design, the circuit reaches an impressive 40 µVRMS noise level without an external bypass capacitor. Housed in a small SOT–23 5 leads–like package, it represents the ideal designer’s choice when space and noise are at premium. The absence of external bandgap capacitor accelerates the response time to a wake–up signal and keeps it within 40 µs (in repetitive mode), making the MC33761 as a natural candidate for portable applications. The MC33761 also hosts a novel architecture which prevents excessive undershoots in the presence of fast transient bursts, as in any bursting systems. Finally, with a static line regulation better than –75 dB, it naturally shields the downstream electronics against choppy lines.

http://onsemi.com

5 1 THIN SOT–23–5 SN SUFFIX CASE 483

PIN CONNECTIONS AND MARKING DIAGRAM

Features

• Ultra–Low Noise: 150 nV/√Hz @ 100 Hz, 40 µVRMS

• • • • • • • • •

1

GND

2

ON/OFF

3

5

Vout

4

NC

LxxYW

•

100 Hz–100 kHz Typical, Iout = 60 mA, Co = 1.0 µF Fast Response Time from OFF to ON: 40 µs Typical at a 200 Hz Repetition Rate Ready for 1.0 V Platforms: ON with a 900 mV High Level Nominal Output Current of 80 mA with a 100 mA Peak Capability Typical Dropout of 90 mV @ 30 mA, 160 mV @ 80 mA Ripple Rejection: 70 dB @ 1.0 kHz 1.5% Output Precision @ 25°C Thermal Shutdown Vout Available at 2.5 V, 2.8 V, 3.0 V Operating Range from –40 to +85°C Dual Version is Available as MC33762

Vin

(Top View) xx = Version Y = Year W = Work Week


Applications

• Noise Sensitive Circuits: VCOs RF Stages, etc. • Bursting Systems (TDMA Phones) • All Battery Operated Devices ON/ OFF

3

NC

4

GND

2

On/Off

1

Vin

5

Vout

Thermal Shutdown

Band Gap Reference

*Current Limit *Antisaturation Protection *Load Transient Improvement

Figure 1. Simplified Block Diagram  Semiconductor Components Industries, LLC, 2001

October, 2001 – Rev. 5

254


MC33761 PIN FUNCTION DESCRIPTIONS Pin #

Pin Name

1

Vin

2

GND

3

ON/OFF

4 5

Function Powers the IC

Description A positive voltage up to 12 V can be applied upon this pin.

The IC’s ground Shuts or wakes–up the IC

A 900 mV level on this pin is sufficient to start the IC. A 150 mV shuts it down.

NC

None

It makes no arm to connect the pin to a known potential, like in a pin–to–pin replacement case.

Vout

Delivers the output voltage

This pin requires a 1.0 µF output capacitor to be stable.

MAXIMUM RATINGS Value Rating

Pin #

Symbol

Min

Max

Unit

1

Vin

–

12

V

ESD Capability, HBM Model

All Pins

–

–

1.0

kV

ESD Capability, Machine Model

All Pins

–

–

200

V

Maximum Power Dissipation NW Suffix, Plastic Package Thermal Resistance Junction–to–Air

–

PD

–

Internally Limited

W

RJA

–

210

°C/W

Operating Ambient Temperature Maximum Junction Temperature (Note 1) Maximum Operating Junction Temperature (Note 2)

–

TA TJmax TJ

– – –

–40 to +85 150 125

°C °C °C


–

Tstg

–

–60 to +150

°C

Power Supply Voltage

ELECTRICAL CHARACTERISTICS (For typical values TA = 25°C, for min/max values TA = –40°C to +85°C, max TJ = 125°C unless otherwise noted) Pin #

Characteristics

Symbol

Min

Typ

Max

Unit

Logic Control Specifications Input Voltage Range

3

VON/OFF

0

–

Vin

V

ON/OFF Input Resistance (all versions)

3

RON/OFF

–

250

–

k

ON/OFF Control Voltages (Note 3) Logic Zero, OFF State, IO = 50 mA Logic One, ON State, IO = 50 mA

3

VON/OFF – 900

– –

150 –

mV

Currents Parameters Current Consumption in OFF State (all versions) OFF Mode Current: Vin = Vout + 1.0 V, IO = 0, VOFF = 150 mV

–

IQOFF

–

0.1

2.0

A

Current Consumption in ON State (all versions) ON Mode Current: Vin = Vout + 1.0 V, IO = 0, VON = 3.5 V

–

IQON

–

180

–

A

Current Consumption in ON State (all versions), ON Mode Saturation Current: Vin = Vout – 0.5 V, No Output Load

–

IQSAT

–

800

–

A

Current Limit Vin = Voutnom + 1.0 V, Output is brought to Voutnom – 0.3 V (all versions)

–

IMAX

100

180

–

mA

1. Internally limited by shutdown. 2. Specifications are guaranteed below this value. 3. Voltage slope should be greater than 2.0 mV/s.


MC33761 ELECTRICAL CHARACTERISTICS (continued) (For typical values TA = 25°C, for min/max values TA = –40°C to +85°C, max TJ = 125°C unless otherwise noted) Pin #

Symbol

Min

Typ

Max

Unit

5

Vout

2.462

2.5

2.537

V

2.8 V

5

Vout

2.758

2.8

2.842

V

3.0 V

5

Vout

2.955

3.0

3.045

V

5.0 V

5

Vout

4.925

5.0

5.075

V

Other Voltages up to 5.0 V Available in 50 mV Increment Steps

5

Vout

–1.5

X

+1.5

%

Vout + 1.0 V < Vin < 6.0 V, TA = –40°C to +85°C, 1.0 mA < Iout < 80 mA 2.5 V

5

Vout

2.425

2.5

2.575

V

2.8 V

5

Vout

2.716

2.8

2.884

V

3.0 V

5

Vout

2.91

3.0

3.090

V

5.0 V

5

Vout

4.850

5.0

5.150

V

5

Vout

–3.0

X

+3.0

%

5/1

Regline

–

–

20

mV

5

Regload

–

–

40

mV

5 5 5

Vin–Vout Vin–Vout Vin–Vout

– – –

90 140 160

150 200 250

5/1

Ripple

–

–70

–

dB

Output Noise Density @ 1.0 kHz

5

–

–

150

–

nV/ √Hz

RMS Output Noise Voltage (all versions) Cout = 1.0 F, Iout = 50 mA, F = 100 Hz to 1.0 MHz

5

Noise

–

35

–

V

Output Rise Time (all versions) Cout = 1.0 F, Iout = 50 mA, 10% of Rising ON Signal to 90% of Nominal Vout

5

trise

–

40

–

s

–

–

–

–

125

°C

Characteristics

Output Voltages Vout + 1.0 V < Vin < 6.0 V, TA = 25°C, 1.0 mA < Iout < 80 mA 2.5 V


Line and Load Regulation, Dropout Voltages Line Regulation (all versions) Vout + 1.0 V < Vin < 12 V, Iout = 80 mA Load Regulation (all versions) Vin = Vout + 1.0 V, Cout = 1.0 F, Iout = 1.0 to 80 mA Dropout Voltage (all versions) (Note 4) Iout = 30 mA Iout = 60 mA Iout = 80 mA

mV

Dynamic Parameters Ripple Rejection (all versions) Vin = Vout + 1.0 V + 1.0 kHz 100 mVpp Sinusoidal Signal

Thermal Shutdown Thermal Shutdown (all versions) 4. Vout is brought to Vout – 100 mV.


MC33761 DEFINITIONS Load Regulation

Line Regulation

The change in output voltage for a change in output current at a constant chip temperature.

The change in output voltage for a change in input voltage. The measurement is made under conditions of low dissipation or by using pulse technique such that the average chip temperature is not significantly affected. One usually distinguishes static line regulation or DC line regulation (a DC step in the input voltage generates a corresponding step in the output voltage) from ripple rejection or audio susceptibility where the input is combined with a frequency generator to sweep from a few hertz up to a defined boundary while the output amplitude is monitored.

Dropout Voltage

The input/output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. Measured when the output drops 100 mV below its nominal value (which is measured at 1.0 V differential value). The dropout level is affected by the chip temperature, load current and minimum input supply requirements.

Thermal Protection

Output Noise Voltage

This is the integrated value of the output noise over a specified frequency range. Input voltage and output current are kept constant during the measurement. Results are expressed in µVRMS.

Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated at typically 125°C, the regulator turns off. This feature is provided to prevent catastrophic failures from accidental overheating.

Maximum Power Dissipation

Maximum Package Power Dissipation

The maximum total dissipation for which the regulator will operate within its specs.

The maximum power package power dissipation is the power dissipation level at which the junction temperature reaches its maximum operating value, i.e. 125°C. Depending on the ambient temperature, it is possible to calculate the maximum power dissipation and thus the maximum available output current.

Quiescent Current

The quiescent current is the current which flows through the ground when the LDO operates without a load on its output: internal IC operation, bias etc. When the LDO becomes loaded, this term is called the Ground current. It is actually the difference between the input current (measured through the LDO input pin) and the output current.


MC33761 Characterization Curves All curves taken with Vin = Vout + 1.0 V, Vout = 2.8 V, Cout = 1.0 F 4.5

185

GROUND CURRENT (mA)

3.5

QUIESCENT CURRENT ( A)

–40°C 25°C 85°C

4.0

3.0 2.5 2.0 1.5 1.0

180

175

170

0.5 0 0

20

40 60 OUTPUT CURRENT (mA)

80

165 –60

100

Figure 2. Ground Current versus Output Current

–20 0 20 40 60 AMBIENT TEMPERATURE (°C)

80

100

Figure 3. Quiescent Current versus Temperature 2.805

200 85°C 25°C –40°C 100

50

85°C

2.800 OUTPUT VOLTAGE (V)

150

40°C 2.795 2.790 2.785

25°C 0°C

2.780

–20°C –40°C

0

2.775 0

20


80

100

0

20

Figure 4. Dropout versus Output Current


80 mA

160

60 mA

140 120

30 mA

100 80 60 40 20 0 –60

1.0 mA –40

–20

80


180 DROPOUT VOLTAGE (mV)

DROPOUT (mV)

–40

20 40 0 TEMPERATURE (°C)

60

80

Figure 6. Dropout versus Temperature


100

100

MC33761 APPLICATION HINTS Input Decoupling

Protections

As with any regulator, it is necessary to reduce the dynamic impedance of the supply rail that feeds the component. A 1.0 µF capacitor either ceramic or tantalum is recommended and should be connected close to the MC33761 package. Higher values will correspondingly improve the overall line transient response.

The MC33761 hosts several protections, giving natural ruggedness and reliability to the products implementing the component. The output current is internally limited to a maximum value of 180 mA typical while temperature shutdown occurs if the die heats up beyond 125°C. These values let you assess the maximum differential voltage the device can sustain at a given output current before its protections come into play. The maximum dissipation the package can handle is given by:

Output Decoupling

Thanks to a novel concept, the MC33761 is a stable component and does not require any specific Equivalent Series Resistance (ESR) neither a minimum output current. Capacitors exhibiting ESRs ranging from a few m up to 3.0 can thus safely be used. The minimum decoupling value is 1.0 µF and can be augmented to fulfill stringent load transient requirements. The regulator accepts ceramic chip capacitors as well as tantalum devices.

T *T A P max + Jmax R JA

If TJmax is limited to 125°C, then the MC33761 can dissipate up to 470 mW @ 25°C. The power dissipated by the MC33761 can be calculated from the following formula:

ǒ

Noise Decoupling

Ptot + V

Unlike other LDOs, the MC33761 is a true low–noise regulator. Without the need of an external bypass capacitor, it typically reaches the incredible level of 40 µVRMS overall noise between 100 Hz and 100 kHz. To give maximum insight on noise specifications, ON Semiconductor includes spectral density graphics. The classical bypass capacitor impacts the start–up phase of standard LDOs. However, thanks to its low–noise architecture, the MC33761 operates without a bypass element and thus offers a typical 40 µs start–up phase.

in

I

Ǔ

(I ) ) ǒV * V outǓ gnd out in

I out

or Vin max +

Ptot ) V out I

gnd

I out

) I out

If a 80 mA output current is needed, the ground current is extracted from the data–sheet curves: 4.0 mA @ 80 mA. For a MC33761SNT1–28 (2.8 V) delivering 80 mA and operating at 25°C, the maximum input voltage will then be 8.3 V. Typical Applications

The following picture portrays the typical application of the MC33761.


MC33761 Dropout

5

1

Input Permanently Enables the IC When Closed

Charge

Output

2 3

+ C3 1 F

4 MC33761

On/Off

+ C2 1.0 F

R1 100 k

Figure 7. A Typical Application Schematic

basis for the MC33761 performance evaluation board. The BNC connectors give the user an easy and quick evaluation mean.

As for any low noise designs, particular care has to be taken when tackling Printed Circuit Board (PCB) layout. The figure below gives an example of a layout where stray inductances/capacitances are minimized. This layout is the


MC33761 Understanding the Load Transient Improvement During this decreasing phase, the LDO stops the PNP bias and one can consider the LDO asleep (Figure 8). If by misfortune a current shot appears, the reaction time is incredibly lengthened and a strong undershoot takes place. This reaction is clearly not acceptable for line sensitive devices, such as VCOs or other Radio–Frequency parts. This problem is dramatically exacerbated when the output current drops to zero rather than a few mA. In this later case, the internal feedback network is the only discharge path, accordingly lengthening the output voltage decay period (Figure 9). The MC33761 cures this problem by implementing a clever design where the LDO detects the presence of the overshoot and forces the system to go back to steady–state as soon as possible, ready for the next shot. Figure 10 and 11 show how it positively improves the response time and decreases the negative peak voltage.

The MC33761 features a novel architecture which allows the user to easily implement the regulator in burst systems where the time between two current shots is kept very small. The quality of the transient response time is related to many parameters, among which the closed–loop bandwidth with the corresponding phase margin plays an important role. However, other characteristics also come into play like the series pass transistor saturation. When a current perturbation suddenly appears on the output, e.g. a load increase, the error amplifier reacts and actively biases the PNP transistor. During this reaction time, the LDO is in open–loop and the output impedance is rather high. As a result, the voltage brutally drops until the error amplifier effectively closes the loop and corrects the output error. When the load disappears, the opposite phenomenon takes place with a positive overshoot. The problem appears when this overshoot decays down to the LDO steady–state value.

Figure 8. A Standard LDO Behavior when the Load Current Disappears

Figure 9. A Standard LDO Behavior when the Load Current Appears in the Decay Zone

Figure 10. Without Load Transient Improvement

Figure 11. MC33761 with Load Transient Improvement


MC33761 MC33761 Has a Fast Start–Up Phase unacceptable level. MC33761 offers the best of both worlds since it no longer includes a bypass capacitor and starts in less than 40 µs typically (Repetitive at 200 Hz). It also ensures a low–noise level of 40 µVRMS 100 Hz–100 kHz. The following picture details the typical 33761 start–up phase.

Thanks to the lack of bypass capacitor the MC33761 is able to supply its downstream circuitry as soon as the OFF to ON signal appears. In a standard LDO, the charging time of the external bypass capacitor hampers the response time. A simple solution consists in suppressing this bypass element but, unfortunately, the noise rises to an

Figure 12. Repetitive Start–Up Waveforms


MC33761 TYPICAL TRANSIENT RESPONSES

Figure 13. Output is Pulsed from 2.0 mA to 80 mA

Figure 14. Discharge Effects from 0 to 40 mA

Figure 15. Load Transient Improvement Effect



MC33761 TYPICAL TRANSIENT RESPONSES 250

nV/sqrt Hz

200

Vin = Vout + 1 .0V TA = 25°C Cout = 1.0 F

RMS Noise, IO = 50 mA: 20 Hz – 100 kHz: 27 V 20 Hz – 1.0 MHz: 30 V

IO = 50 mA

150

10 mA 100

50

RMS Noise, IO = 10 mA: 20 Hz – 100 kHz: 29 V 20 Hz – 1.0 MHz: 31 V

0 100

1,000

10,000 100,000 f, FREQUENCY (Hz)

1,000,000

Figure 17. MC33761 Typical Noise Density Performance

3.5

0 –10

IO = 1.0 mA

3.0

–20 2.5

(dB)

–40

Z O (OHMS)

–30 IO = 50 mA

–50 –60 –70

10 mA

–90

1.5 80 mA

1.0 Vin = VO + 1.0 V TA = 25°C Cout = 1.0 F

–80

10 mA

2.0

0.5 20 mA

–100

0 100

1,000

10,000 100,000 f, FREQUENCY (Hz)

1,000,000

100

Figure 18. MC33761 Typical Ripple Rejection Performance

1,000

100,000 10,000 f, FREQUENCY (Hz)

1,000,000

Figure 19. Typical Output Impedance plot Cout = 1.0 µF, Vin = Vout + 1.0


MC33761 MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. ##9

##-8 #9

##8 9 ##-8 #9

## 7 #8 ##-9 #

THIN SOT–23–5


MC33761 ORDERING INFORMATION Device

Voltage Output

Package

Shipping

MC33761SNT1–25

2.5 V

Thin SOT–23–5

3000 Units / Tape & Reel

MC33761SNT1–28

2.8 V

Thin SOT–23–5


MC33761SNT1–30

3.0 V

Thin SOT–23–5


MC33761SNT1–50

5.0 V

Thin SOT–23–5



"-.& ' %( % ) %* $ +,, " The NCP4561 is a Low DropOut (LDO) regulator featuring excellent noise performances. Thanks to its innovative concept, the circuit reaches an incredible 40 µVRMS noise level without an external bypass capacitor. Housed in a small SOT–23 5 leads–like package, it represents the ideal designer’s choice when space and noise are at premium. The absence of external bandgap capacitor unleashes the response time to a wake–up signal and makes it stay within 40 µs (in repetitive mode), pushing the NCP4561 as a natural candidate in portable applications. The NCP4561 also hosts a novel architecture which prevents excessive undershoots when the regulator is the seat of fast transient bursts, as in any bursting systems. Finally, with a static line regulation better than –75 dB, it naturally shields the downstream electronics against choppy lines. Features

• Ultra Low–Noise: 150 nV/√Hz @ 100 Hz, 40 µVRMS 100 Hz –

• • • • • •

5 1 TSOP–5 SN SUFFIX CASE 483

PIN CONNECTIONS AND MARKING DIAGRAM ON/OFF

1

GND

2

NC

3

5

Vin

4

Vout

P28YW

•

100 kHz Typical, Iout = 60 mA, Co = 1.0 µF Fast Response Time from OFF to ON: 40 µs Typical at a 200 Hz Repetition Rate Ready for 1.0 V Platforms: ON with a 900 mV High Level Nominal Output Current of 80 mA with a 100 mA Peak Capability Typical Dropout of 90 mV @ 30 mA, 160 mV @ 80 mA Ripple Rejection: 70 dB @ 1.0 kHz 1.5% Output Precision @ 25°C Thermal Shutdown

http://onsemi.com

(Top View) P28 = Device Code Y = Year W = Work Week

Applications

• Noise Sensitive Circuits: VCOs RF Stages, etc. • Bursting Systems (TDMA Phones) • All Battery Operated Devices

ON/ OFF

1

NC

3

GND

2

On/Off


5

Vin

4

Vout

Device

Voltge Output*

Shipping

NCP4561SNT1–28

2.8 V

3000/Tape & Reel

* Contact your ON Semiconductor sales representative for other output voltage values.

Thermal Shutdown

Band Gap Reference


Figure 1. Simplified Block Diagram


June, 2001 – Rev. 1

267

Publication Order Number: NCP4561/D

NCP4561 PIN FUNCTION DESCRIPTIONS Pin #

Pin Name

Function

1

ON/OFF

Shuts or wakes–up the IC

Description

2

GND

The IC’s ground

3

NC

None

It makes no arm to connect the pin to a known potential, like in a pin–to–pin replacement case.

4

Vout



5

Vin

Powers the IC

A positive voltage up to 12 V can be applied upon this pin.

A 900 mV level on this pin is sufficient to start the IC. A 150 mV shuts it down.

MAXIMUM RATINGS Value Rating Power Supply Voltage

Pin #

Symbol

Min

Max

Unit

5

Vin

–

12

V


All Pins

–

1.0

kV


All Pins

–

200

V W


PD

–

RJ–A

–

Internally Limited 210


TA TJmax TJ

– – –

–40 to +85 150 125

°C

Tstg

–

–60 to +150

°C


°C/W

ELECTRICAL CHARACTERISTICS (For Typical Values TA = 25°C, for Min/Max values TA = –40°C to +85°C, Max TJ = 125°C unless otherwise noted) Pin #

Symbol

Min

Typ

Max

Unit

Input Voltage Range

1

VON/OFF

0

–

Vin

V

ON/OFF Input Resistance

1

RON/OFF

–

250

–

k


1

VON/OFF – 900

– –

150 –

Characteristics

Logic Control Specifications

mV

Currents Parameters Current Consumption in OFF State OFF Mode Current: Vin = Vout + 1.0 V, IO = 0, VOFF = 150 mV

IQOFF

–

0.1

2.0

A

Current Consumption in ON State ON Mode Current: Vin = Vout + 1.0 V, IO = 0, VON = 3.5 V

IQON

–

180

–

A

Current Consumption in ON State, ON Mode Saturation Current: Vin = Vout – 0.5 V, No Output Load

IQSAT

–

800

–

A

Current Limit Vin = Voutnom + 1.0 V, Output is brought to Voutnom – 0.3 V

IMAX

100

180

–

mA

1. Internally Limited by Shutdown. 2. Specifications are guaranteed below this value. 3. Voltage Slope should be Greater than 2.0 mV/s.


NCP4561 ELECTRICAL CHARACTERISTICS (continued) (For Typical Values TA = 25°C, for Min/Max values TA = –40°C to +85°C, Max TJ = 125°C unless otherwise noted) Pin #

Symbol

Min

Typ

Max

Unit

Vout + 1.0 V < Vin < 6.0 V, TA = 25°C, 1.0 mA < Iout < 80 mA

4

Vout

2.758

2.8

2.842

V

Vout + 1.0 V < Vin < 6.0 V, TA = –40°C to +85°C, 1.0 mA < Iout < 80 mA

4

Vout

2.716

2.8

2.884

V

4/5

Regline

–

–

20

mV

4

Regload

–

–

40

mV

4 4 4


– – –

90 140 160

150 200 250

4/5

Ripple

–

–70

–

dB

–

150

–

nV/ √Hz

Characteristics

Output Voltages

Line and Load Regulation, Dropout Voltages Line Regulation Vout + 1.0 V < Vin < 12 V, Iout = 80 mA Load Regulation Vin = Vout + 1.0 V, Cout = 1.0 F, Iout = 1.0 to 80 mA Dropout Voltage (Note 4) Iout = 30 mA Iout = 60 mA Iout = 80 mA

mV

Dynamic Parameters Ripple Rejection Vin = Vout + 1.0 V + 1.0 kHz 100 mVpp Sinusoidal Signal Output Noise Density @ 1.0 kHz

4

RMS Output Noise Voltage Cout = 1.0 F, Iout = 50 mA, F = 100 Hz to 1.0 MHz

4

Noise

–

35

–

V

Output Rise Time Cout = 1.0 F, Iout = 50 mA, 10% of Rising ON Signal to 90% of Nominal Vout

4

trise

–

40

–

s

–

–

125

°C

Thermal Shutdown Thermal Shutdown 4. Vout is brought to Vout – 100 mV.


NCP4561 DEFINITIONS Load Regulation

Line Regulation



Dropout Voltage


Thermal Protection








Quiescent Current

The quiescent current is the current which flows through the ground when the LDO operates without a load on its output: internal IC operation, bias, etc. When the LDO becomes loaded, this term is called the Ground current. It is actually the difference between the input current (measured through the LDO input pin) and the output current.


NCP4561 TYPICAL CHARACTERISTICS 6.000

210 QUIESCENT CURRENT (µA)

GROUND CURRENT (mA)

5.500 5.000 4.500 4.000

–40°C

25°C

3.500 3.000 2.500

85°C

2.000 1.500 1.000 0.500 0.000 0

20

40

80

60

100

205

200

195

190

185 –60

–40

–20

0

20

40

60

80

100

OUTPUT CURRENT (mA)

AMBIENT TEMPERATURE (°C)

Figure 2. Ground Current vs. Output Current

Figure 3. Quiescent Current vs. Temperature

2.810 200

2.805

150

OUTPUT VOLTAGE (V)

DROPOUT (mV)

85°C 25°C

100

–40°C

50

85°C

2.800 2.795 25°C

2.790 2.785 2.780

–40°C

2.775 2.770 2.765 2.760 2.755

00

–20

40

60

80

0

100

20

40

60

80

OUTPUT CURRENT (mA)

OUTPUT CURRENT (mA)

Figure 4. Dropout vs. Output Current

Figure 5. Output Voltage vs. Output Current

100

OUTPUT NOISE SPECTRAL DENSITY 180

1000

140 NOISE (nV/sqrt Hz)

DROPOUT VOLTAGE (mV)

Vin = Vout + 1 Cout = 1 µF IO = 10 & 50 mA

80 mA

160

120 60 mA

100 80

30 mA

60 40

100

10 RMS Noise 10 Hz to 100 kHz: 36 µV 10 Hz to 1 MHz: 47 µV

20 0 –60

–40

–20

0

20

40

60

80

100

1 0.01

0.1

1

10

100

1000

FREQUENCY (kHz)

TEMPERATURE (°C)

Figure 6. Dropout Voltage vs. Temperature

Figure 7. Typical Noise Density Performance


NCP4561 POWER SUPPLY REJECTION RATIO Mag (dB) Vin = Vout + 1 Cout = 1 µF Iload = 10 mA

–7.50 –15.00 PSSR (dB)

–22.50 –30.00 –37.50 –45.00 –52.50 –60.00 –67.50 10

100

1k

10 k

100 k

1M

FREQUENCY (Hz)

Figure 8. Typical Ripple Rejection Performance (Iload = 10 mA)

POWER SUPPLY REJECTION RATIO Mag (dB) Vin = Vout + 1 Cout = 1 µF Iload = 60 mA

–7.50 –15.00 PSSR (dB)

–22.50 –30.00 –37.50 –45.00 –52.50 –60.00 –67.50 10

100

1k

10 k

100 k

1M

FREQUENCY (Hz)

Figure 9. Typical Ripple Rejection Performance (Iload = 60 mA)


NCP4561 APPLICATION HINTS Input Decoupling

Protections

As with any regulator, it is necessary to reduce the dynamic impedance of the supply rail that feeds the component. A 1.0 µF capacitor either ceramic or tantalum is recommended and should be connected close to the NCP4561 package. Higher values will correspondingly improve the overall line transient response.

The NCP4561 hosts several protections, giving natural ruggedness and reliability to the products implementing the component. The output current is internally limited to a maximum value of 180 mA typical while temperature shutdown occurs if the die heats up beyond 125°C. These values let you assess the maximum differential voltage the device can sustain at a given output current before its protections come into play. The maximum dissipation the package can handle is given by:

Output Decoupling

Thanks to a novel concept, the NCP4561 is a stable component and does not require any specific Equivalent Series Resistance (ESR) neither a minimum output current. Capacitors exhibiting ESRs ranging from a few m up to 3.0 can thus safely be used. The minimum decoupling value is 1.0 µF and can be augmented to fulfill stringent load transient requirements. The regulator accepts ceramic chip capacitors as well as tantalum devices.

T *T A P max + Jmax R JA

If TJmax is limited to 125°C, then the NCP4561 can dissipate up to 470 mW @ 25°C. The power dissipated by the NCP4561 can be calculated from the following formula:

ǒ

Noise Decoupling

Ptot + V

Unlike other LDOs, the NCP4561 is a true low–noise regulator. Without the need of an external bypass capacitor, it typically reaches the incredible level of 40 µVRMS overall noise between 100 Hz and 100 kHz. To give maximum insight on noise specifications, ON Semiconductor includes spectral density graphics. The classical bypass capacitor impacts the start–up phase of standard LDOs. However, thanks to its low–noise architecture, the NCP4561 operates without a bypass element and thus offers a typical 40 µs start–up phase.

in

I

Ǔ


I out

or Vin max +

Ptot ) V out I

gnd

I out

) I out

If a 80 mA output current is needed, the ground current is extracted from the data–sheet curves: 4.0 mA @ 80 mA. For a NCP4561SNT1–28 (2.8 V) delivering 80 mA and operating at 25°C, the maximum input voltage will then be 8.3 V.


NCP4561 Typical Applications

The following figure portrays the typical application of the NCP4561. Dropout

Charge

SW*

4

Output 5

Input

3

1

+

2

NCP4561

C3 1.0 F

+ C2 1.0 F R1 100 k

On/Off

*Enables the IC When Closed

Figure 10. A Typical Application Schematic PCB Layout Considerations

inductances/capacitances are minimized. This layout is the basis for the NCP4561 performance evaluation board. The BNC connectors give the user an easy and quick evaluation mean.

As for any low noise designs, particular care has to be taken when tackling Printed Circuit Board (PCB) layout. The figure below gives an example of a layout where stray

ON SEMICONDUCTOR NCP4561 EVALUATION BOARD

DROPOUT

+ OUT _

+ IN _

ON Semiconductor NCP4561 EVALUATION BOARD

OUT

OFF ON

IN

ON/OFF

Figure 11. PCB Layout


NCP4561 Understanding the Load Transient Improvement During this decreasing phase, the LDO stops the PNP bias and one can consider the LDO asleep. If by misfortune a current shot appears, the reaction time is incredibly lengthened and a strong undershoot takes place. This reaction is clearly not acceptable for line sensitive devices, such as VCOs or other Radio–Frequency parts. This problem is dramatically exacerbated when the output current drops to zero rather than a few mA. In this later case, the internal feedback network is the only discharge path, accordingly lengthening the output voltage decay period. The NCP4561 cures this problem by implementing a clever design where the LDO detects the presence of the overshoot and forces the system to go back to steady–state as soon as possible, ready for the next shot, which positively improves the response time and decreases the negative peak voltage.

The NCP4561 features a novel architecture which allows the user to easily implement the regulator in burst systems where the time between two current shots is kept very small. The quality of the transient response time is related to many parameters, among which the closed–loop bandwidth with the corresponding phase margin plays an important role. However, other characteristics also come into play like the series pass transistor saturation. When a current perturbation suddenly appears on the output, e.g. a load increase, the error amplifier reacts and actively biases the PNP transistor. During this reaction time, the LDO is in open–loop and the output impedance is rather high. As a result, the voltage brutally drops until the error amplifier effectively closes the loop and corrects the output error. When the load disappears, the opposite phenomenon takes place with a positive overshoot. The problem appears when this overshoot decays down to the LDO steady–state value.

NCP4561 has a fast start–up phase unacceptable level. NCP4561 offers the best of both worlds since it no longer includes a bypass capacitor and starts in less than 40 µs typically (Repetitive at 200 Hz). It also ensures a low–noise level of 40 µVRMS 100 Hz–100 kHz. The following picture details the typical NCP4561 startup phase.

Thanks to the lack of bypass capacitor the NCP4561 is able to supply its downstream circuitry as soon as the OFF to ON signal appears. In a standard LDO, the charging time of the external bypass capacitor hampers the response time. A simple solution consists in suppressing this bypass element but, unfortunately, the noise rises to an Tek Run: 5.00 MS/s

Sample Vout 500 mV/div C4 High 2.78 V C4 Mean 2.426 V

ON/OFF Pin Voltage 1 V/div

Ch3 1.00 V

Ch4 500 mV

M 10.0 µs Ch3

1.82 V

(Conditions: Vin = 3.8 V, Iload = 10 mA, Cout = 1 µF)

Figure 12. Start–Up Waveform


NCP4561 TYPICAL TRANSIENT RESPONSES

Tek Run: 1.00 MS/s

Sample

Vout 200 mV/div

C4 Max 2.800 V C4 Mean 2.7840 V C4 Min 2.720 V

Iload 20 mA/div

Ch2 20.0 mVΩ M 50.0 µs Ch2 Ch4 200 mV

38.4 mV

(Conditions: Vin = 3.8 V, Cout = 1 mF)

Figure 13. Load Current is Pulsed from 0 to 40 mA

Sample

Tek Run: 1.00 MS/s Vout 200 mV/div

C4 Max 2.844 V C4 Mean 2.7852 V C4 Min 2.708 V Iload 20 mA/div

Ch1 20.0 mVΩ Ch4 200 mV

M 50.0 µs Ch1

78.8 mV


Figure 14. Load Current is Pulsed from 0 to 80 mA


NCP4561 TYPICAL TRANSIENT RESPONSES Tek Run: 1.00 MS/s

Sample

Vout 200 mV/div

C4 Max 2.824 V C4 Mean 2.7848 V C4 Mean 2.776 V

Iload 20 mA/div

Ch2 20.0 mVΩ M 50.0 µs Ch2 Ch4 200 mV

38.4 mV


Figure 15. Load Current is Switched from 40 to 0 mA

Tek Stop: 1.00 MS/s

1930 Acgs Vout 200 mV/div C4 Max 2.844 V C4 Mean 2.7848 V C4 Min 2.708 V Iload 20 mA/div

Ch1 20.0 mVΩ Ch4 200 mV

M 50.0 µs Ch1

0V


Figure 16. Load Current is Switched from 80 to 0 mA


NCP4561 MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection

interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. ##9

##-8 #9

##8 9 ##-8 #9

## 7 #8 ##-9 #

TSOP–5 (TSOP–5 is footprint compatible with SOT23–5)

ORDERING INFORMATION Device NCP4561SNT1–28

Voltage Output*

Package

Shipping

2.8 V

TSOP–5

3000 Units /Tape & Reel

*Contact your ON Semiconductor sales representative for other output voltage values.


"-$/ #$ " % 01 "!$( The NCP502 series of fixed output linear regulators are designed for handheld communication equipment and portable battery powered applications which require low quiescent. The NCP502 series features an ultra–low quiescent current of 40 µA. Each device contains a voltage reference unit, an error amplifier, a PMOS power transistor, resistors for setting output voltage, current limit, and temperature limit protection circuits. The NCP502 has been designed to be used with low cost ceramic capacitors. The device is housed in the micro–miniature SC70–5 surface mount package. Standard voltage versions are 1.5, 1.8, 2.5, 2.7, 2.8, 3.0, 3.3, and 5.0 V. Other voltages are available in 100 mV steps. Features

• • • • •

MARKING DIAGRAM

5

XXXd 1

SC–88A/SOT–353/SC70–5 DF SUFFIX CASE 419A XXX = Specific Device Code d = Date Code

Low Quiescent Current of 40 µA Typical Excellent Line and Load Regulation Low Output Voltage Option Output Voltage Accuracy of 2.0% Industrial Temperature Range of –40°C to 85°C

PIN CONNECTIONS

Typical Applications

• • • •

http://onsemi.com

Cellular Phones Battery Powered Consumer Products Hand–Held Instruments Camcorders and Cameras

Vin

1

Gnd

2

Enable

3

5

Vout

4

N/C

(Top View)

ORDERING INFORMATION Battery or Unregulated Voltage

Vout C1

*

1

5 *

2 ON

3


C2

4

OFF This device contains 86 active transistors

Figure 1. Typical Application Diagram


November, 2001 – Rev. 1

279


NCP502

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin No.

Pin Name

1

Gnd

Power supply ground.

Description

2

Vin

Positive power supply input voltage.

3

Vout

Regulated output voltage.

4

N/C

No internal connection.

5

Enable

This input is used to place the device into low–power standby. When this input is pulled low, the device is disabled. If this function is not used, Enable should be connected to Vin.

MAXIMUM RATINGS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating

Symbol

Value

Unit

Vin

12

V

Enable Voltage

Enable

–0.3 to Vin +0.3

V

Output Voltage

Vout

–0.3 to Vin +0.3

V

Power Dissipation and Thermal Characteristics Power Dissipation Thermal Resistance, Junction to Ambient

PD RθJA


W °C/W

Input Voltage


TJ

+125

°C

Operating Ambient Temperature

TA

–40 to +85

°C

Storage Temperature

Tstg

–55 to +150

°C

Tsolder

10

sec

Lead Soldering Temperature @ 260°C

1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL–STD–883, Method 3015 Machine Model Method 200 V 2. Latch up capability (85°C) "100 mA DC with trigger voltage.


NCP502 ELECTRICAL CHARACTERISTICS (Vin = Vout(nom.) + 2.0 V, Venable = Vin, Cin = 1.0 µF, Cout = 1.0 µF, TJ = 25°C, unless otherwise noted.) Characteristic

Symbol

Output Voltage (TA = 25°C, Iout = 10 mA) Vin = Vout (nom.) +1.0 V 1.5 V 1.8 V 2.5 V 2.7 V 2.8 V 3.0 V 3.3 V 5.0 V

Vout

Output Voltage (TA = –40°C to 85°C, Iout = 10 mA) Vin = Vout (nom.) +1.0 V 1.5 V 1.8 V 2.5 V 2.7 V 2.8 V 3.0 V 3.3 V 5.0 V

Vout

Min

Typ

Max

1.455 1.746 2.425 2.646 2.744 2.94 3.234 4.900

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

1.545 1.854 2.575 2.754 2.856 3.06 3.366 5.100

1.455 1.746 2.425 2.619 2.716 2.910 3.201 4.900

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

1.545 1.854 2.575 2.781 2.884 3.09 3.399 5.100

Unit V

V

Line Regulation (Vin = Vout + 1.0 V to 12 V, Iout = 10 mA)

Regline

–

0.4

3.0

mV/V

Load Regulation (Iout = 1.0 mA to 80 mA)

Regload

–

0.2

0.8

mV/mA

Output Current

Io(nom.)

80

–

–

mA

Dropout Voltage (TA = –40°C to 85°C, Iout = 80 mA, Measured at Vout –3.0%) 1.5 V – 1.7 V 1.8 V – 2.4 V 2.5 V – 2.6 V 2.7 V – 2.9 V 3.0 V – 4.9 V 5.0 V

Vin–Vout

Quiescent Current (Enable Input = 0 V) (Enable Input = Vin, Iout = 1.0 mA to Io(nom.))

mV – – – – – –

1500 1300 1000 850 850 600

1900 1700 1400 1300 1200 900

– –

0.1 40

1.0 90

Iout(max)

90

200

500

mA

RR

–

55

–

dB

Vn

–

180

–

µVrms

1.3 –

– –

– 0.3

–

100

–

µA

IQ

Output Short Circuit Current Ripple Rejection (f = 1.0 kHz, 15 mA) Output Voltage Noise (f = 100 Hz to 100 kHz) Enable Input Threshold Voltage (Voltage Increasing, Output Turns On, Logic High) (Voltage Decreasing, Output Turns Off, Logic Low)

Vth(en)

Output Voltage Temperature Coefficient

TC

V

3. Maximum package power dissipation limits must be observed. T *TA PD + J(max) RJA 4. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.


ppm/°C

NCP502 45 VOUT = 3.0 V

40

IQ, QUIESCENT CURRENT (A)


45

35 30 25 20 15 10 5

40 37.5 35 32.5 30 –60

0 1

IOUT, OUTPUT CURRENT (mA)

4

3

5

6

7

–40

–20

0

40

20

60

80

100

T, TEMPERATURE (_C)



6 VIN = 4.0 V to 5.0 V 5 4 60

ENABLE VOLTAGE (V)

VIN, INPUT VOLTAGE (V)

10 VIN = 4.0 V VENABLE = 0 to 4.0 V

5 0

COUT = 1.0 µF IOUT = 30 mA VOUT, OUTPUT VOLTAGE (V)

40 20 0 –20 –40 0

10

20

30

40

50

60

70

80

90

3.0 2.0

IOUT = 30 mA COUT = 1.0 µF

1.0 0 0

100

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

t, TIME (s)

t, TIME (ms)


Figure 5. Enable Response

60

0.9 1.0

70

30 0 100

OUTPUT VOLTAGE DEVIATION (mV)

2

RIPPLE REJECTION (dB)



0

VIN = 5.0 V VOUT = 3.0 V

42.5

COUT = 1.0 µF VOUT = 3.0 V VIN = 4.0 V

50 0 –50

–100 0

50

100

150

200

250

300

350

400

450

60

50

40

30 20 0.01

VIN = 4.5 V + 0.5 VP–P VOUT = 3.0 V IOUT = 30 mA COUT = 1.0 µF 0.1

1.0

10

t, TIME (s)

FREQUENCY (kHz)


Figure 7. Ripple Rejection/Frequency


100

NCP502 2.995

3.5 VOUT, OUTPUT VOLTAGE (V)

2.985 VIN = 4.0 V 2.98 2.975 2.97 2.965

3 2.5 2 1.5 1 0.5 0

–40

–20

0

20

40

80

60

100

0

2

1

3

4

5

T, TEMPERATURE (°C)




1200

VIN – VOUT, DROPOUT VOLTAGE (mV)

VOUT, OUTPUT VOLTAGE (V)

2.99

2.96 –60

CIN = 1.0 µF COUT = 1.0 µF VENABLE = VIN

VIN = 12 V

IOUT = 10 mA

1000 80 mA LOAD 800 600 40 mA LOAD

400 200

10 mA LOAD

0 –50

–25

0

50

25

75

100

125


Figure 10. Dropout Voltage versus Temperature


6


Line Regulation

The change in output voltage for a change in output current at a constant temperature.

The change in output voltage for a change in input voltage. The measurement is made under conditions of low dissipation or by using pulse technique such that the average chip temperature is not significantly affected.

Dropout Voltage

The input/output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. Measured when the output drops 3.0% below its nominal. The junction temperature, load current, and minimum input supply requirements affect the dropout level.

Line Transient Response

Typical over and undershoot response when input voltage is excited with a given slope. Thermal Protection

Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated at typically 160°C, the regulator turns off. This feature is provided to prevent failures from accidental overheating.


The maximum total dissipation for which the regulator will operate within its specifications. Quiescent Current



The maximum power package dissipation is the power dissipation level at which the junction temperature reaches its maximum operating value, i.e. 125°C. Depending on the ambient power dissipation and thus the maximum available output current.


NCP502 APPLICATIONS INFORMATION A typical application circuit for the NCP502 series is shown in Figure 1, front page.

Set external components, especially the output capacitor, as close as possible to the circuit, and make leads as short as possible.

Input Decoupling (C1)

A 1.0 µF capacitor either ceramic or tantalum is recommended and should be connected close to the NCP502 package. Higher values and lower ESR will improve the overall line transient response. If large line or load transients are not expected, then it is possible to operate the regulator without the use of a capaitor. TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K

Thermal

As power across the NCP502 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material and also the ambient temperature effect the rate of temperature rise for the part. This is stating that when the NCP502 has good thermal conductivity through the PCB, the junction temperature will be relatively low with high power dissipation applications. The maximum dissipation the package can handle is given by:

Output Decoupling (C2)

The NCP502 is a stable regulator and does not require any specific Equivalent Series Resistance (ESR) or a minimum output current. If load transients are not to be expected, then it is possible for the regulator to operate with no output capacitor. Otherwise, capacitors exhibiting ESRs ranging from a few mΩ up to 5.0 Ω can thus safely be used. The minimum decoupling value is 1.0 µF and can be augmented to fulfill stringent load transient requirements. The regulator accepts ceramic chip capacitors as well as tantalum devices. Larger values improve noise rejection and load regulation transient response. TDK capacitor: C2012X5R1C105K, C1608X5R1A105K, or C3216X7R1C105K

T *TA PD + J(max) RJA

If junction temperature is not allowed above the maximum 125°C, then the NCP502 can dissipate up to 250 mW @ 25°C. The power dissipated by the NCP502 can be calculated from the following equation: Ptot + [Vin * Ignd (Iout)] ) [Vin * Vout] * Iout

or P ) Vout * Iout VinMAX + tot Ignd ) Iout

Enable Operation

The enable pin will turn on the regulator when pulled high and turn off the regulator when pulled low. These limits of threshold are covered in the electrical specification section of this data sheet. If the enable is not used then the pin should be connected to Vin.

If an 80 mA output current is needed then the ground current from the data sheet is 40 µA. For an NCP502 (3.0 V), the maximum input voltage will then be 6.12 V.

Hints

Please be sure the Vin and Gnd lines are sufficiently wide. When the impedance of these lines is high, there is a chance to pick up noise or cause the regulator to malfunction.



interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.

ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ

ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ 1.9 mm

SC70–5 (SC–88A/SOT–353)


0.65 mm 0.65 mm

0.4 mm (min)

0.5 mm (min)

NCP502 ORDERING INFORMATION Device NCP502SQ15T1 NCP502SQ18T1 NCP502SQ25T1 NCP502SQ27T1 NCP502SQ28T1 NCP502SQ30T1 NCP502SQ33T1 NCP502SQ50T1


Marking

Package

Shipping

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

LCC LCD LCE LCF LCG LCH LCI LCJ

SC70–5

3000 Units/ 7″ Tape 7 Ta e & Reel



"-/ #$ " % 01 "!$( The NCP512 series of fixed output linear regulators are designed for handheld communication equipment and portable battery powered applications which require low quiescent. The NCP512 series features an ultra–low quiescent current of 40 µA. Each device contains a voltage reference unit, an error amplifier, a PMOS power transistor, resistors for setting output voltage, current limit, and temperature limit protection circuits. The NCP512 has been designed to be used with low cost ceramic capacitors. The device is housed in the micro–miniature SC70–5 surface mount package. Standard voltage versions are 1.5, 1.8, 2.5, 2.7, 2.8, 3.0, 3.3, and 5.0 V. Other voltages are available in 100 mV steps. Features

Low Quiescent Current of 40 µA Typical Low Dropout Voltage of 250 mV at 80 mA Excellent Line and Load Regulation Low Output Voltage Option Output Voltage Accuracy of 2.0% Industrial Temperature Range of –40°C to 85°C

5 1 SC–88A/SOT–353/SC–70 DF SUFFIX CASE 419A

PIN CONNECTIONS AND MARKING DIAGRAM Vin

1

Gnd

2

Enable

3

5

Vout

4

N/C

PP

• • • • • •

http://onsemi.com

XX = Specific Device Code d = Date Code


• • • •

(Top View)

Cellular Phones Battery Powered Consumer Products Hand–Held Instruments Camcorders and Cameras

Battery or Unregulated Voltage


Vout C1

*

1

5 *

2 ON

3

C2

4

OFF This device contains # active transistors


This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.


June, 2001 – Rev. 0

288


NCP512

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin No.

Pin Name

1

Gnd


Description

2

Vin


3

Vout


4

N/C


5

Enable


MAXIMUM RATINGS


Symbol

Value

Unit

Vin

0 to 6.0

V

Enable Voltage

Enable

–0.3 to Vin +0.3

V

Output Voltage

Vout

–0.3 to Vin +0.3

V


PD RθJA

Internally Limited –

W °C/W

Input Voltage


TJ

+125

°C


TA

–40 to +85

°C

Storage Temperature

Tstg

–55 to +150

°C

Tsolder

10

sec





Symbol

Output Voltage (TA = 25°C, Iout = 10 mA) 1.5 V 1.8 V 2.5 V 2.7 V 2.8 V 3.0 V 3.3 V 5.0 V

Vout

Output Voltage (TA = –40°C to 85°C, Iout = 10 mA) 1.5 V 1.8 V 2.5 V 2.7 V 2.8 V 3.0 V 3.3 V 5.0 V

Vout

Min

Typ

Max

1.455 1.746 2.425 2.646 2.744 2.94 3.234 4.900

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

1.545 1.854 2.575 2.754 2.856 3.06 3.366 5.100

1.455 1.746 2.425 2.619 2.716 2.910 3.201 4.900

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

1.545 1.854 2.575 2.781 2.884 3.09 3.399 5.100

Unit V

V

Line Regulation (Vin = Vout + 1.0 V to 6.0 V, Iout = 10 mA)

Regline

–

1.0

3.0

mV/V


Regload

–

0.3

0.8

mV/mA

Output Current 1.5 V, 1.8 V (Vin = 4.0 V) 2.5 V, 2.7 V, 2.8 V, 3.0 V (Vin = 5.0 V) 3.3 V, (Vin = 6.0 V) 5.0 V (Vin = 8.0 V)

Io(nom.) 80 80 80 80

200 200 200 200

– – – –

Dropout Voltage (TA = –40°C to 85°C, Iout = 80 mA, Measured at Vout –3.0%) 1.5 V 1.8 V 2.5 V 2.7 V 2.8 V 3.0 V 3.3 V 5.0 V

Vin–Vout


mA

mV – – – – – – – –

450 350 220 200 200 180 160 120

550 450 300 300 300 300 300 300

– –

0.1 40

1.0 90

TBD TBD TBD TBD

150 150 150 150

400 400 400 400

µA

IQ

Output Short Circuit Current 1.5 V, 1.8 V (Vin = 4.0 V) 2.5 V, 2.7 V, 2.8 V, 3.0 V (Vin = 5.0 V) 3.3 V, (Vin = 6.0 V) 5.0 V (Vin = 8.0 V)

Iout(max)

mA

Output Voltage Noise (f = 100 Hz to 100 kHz)

Vn

–

180

–

µVrms

Ripple Rejection (f = 1.0 kHz, 60 mA)

RR

–

50

–

dB

1.3 –

– –

– 0.3

–

"100

–

Enable Input Threshold Voltage (Voltage Increasing, Output Turns On, Logic High) (Voltage Decreasing, Output Turns Off, Logic Low)

Vth(en)


TC

V



ppm/°C


Line Regulation



Dropout Voltage














A 1.0 µF capacitor either ceramic or tantalum is recommended and should be connected close to the NCP512 package. Higher values and lower ESR will improve the overall line transient response. TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K

Thermal



The NCP512 is a stable regulator and does not require any specific Equivalent Series Resistance (ESR) or a minimum output current. Capacitors exhibiting ESRs ranging from a few mΩ up to 3.0 Ω can thus safely be used. The minimum decoupling value is 1.0 µF and can be augmented to fulfill stringent load transient requirements. The regulator accepts ceramic chip capacitors as well as tantalum devices. Larger values improve noise rejection and load regulation transient response. TDK capacitor: C2012X5R1C105K, C1608X5R1A105K, or C3216X7R1C105K


If junction temperature is not allowed above the maximum 125°C, then the NCP512 can dissipate up to xxx mW @ 25°C. The power dissipated by the NCP512 can be calculated from the following equation:

Enable Operation


Ptot + [Vin * Ignd (Iout)] ) [Vin * Vout] * Iout


If an 80 mA output current is needed then the ground current from the data sheet is 40 µA. For an NCP512 (3.0 V), the maximum input voltage will then be xx V.

Hints





FOOTPRINT TO COME


NCP512 ORDERING INFORMATION Device NCP512 NCP512 NCP512 NCP512 NCP512 NCP512 NCP512 NCP512


Marking

Package

Shipping

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

xxx xxx xxx xxx xxx xxx xxx xxx

SC70–5

xxxx Units/ xx″ Tape Ta e & Reel



"-/ #$ " % 01 "-E The NCP552 series of fixed output NOCAP linear regulators are designed for handheld communication equipment and portable battery powered applications which require low quiescent. The NCP552 series features an ultra–low quiescent current of 2.8 µA. Each device contains a voltage reference unit, an error amplifier, a PMOS power transistor, resistors for setting output voltage, current limit, and temperature limit protection circuits. The NCP552 has been designed to be used with low cost ceramic capacitors. This device has the ability to operate without an output capacitor. The device is housed in the micro–miniature SC82–AB surface mount package. Standard voltage versions are 1.5, 1.8, 2.5, 2.7, 2.8, 3.0, 3.3, and 5.0 V. Other voltages are available in 100 mV steps.

http://onsemi.com

4

1 SC82–AB (SC70–4) SQ SUFFIX CASE 419C

Features

• • • •

Low Quiescent Current of 2.8 µA Typical Low Output Voltage Option Output Voltage Accuracy of 2.0% Industrial Temperature Range of –40°C to 85°C


Gnd 1 xxxM


• Battery Powered Consumer Products • Hand–Held Instruments • Camcorders and Cameras

Vin 2

Enable

3 Vout (Top View)

xxx M

ON Gnd

4 Enable

= Device Code = Date Code

OFF

ORDERING INFORMATION Input

Output Vin

C1

Vout

*

*


C2

This device contains 32 active transistors



September, 2001 – Rev. 1

295


NCP552

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin No.

Pin Name

1

Gnd


Description

2

Vin


3

Vout


4

Enable


MAXIMUM RATINGS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating

Symbol

Value

Unit

Vin

12

V

Enable Voltage

Enable

–0.3 to Vin +0.3

V

Output Voltage

Vout

–0.3 to Vin +0.3

V


PD RθJA


W °C/W

TJ

+125

°C

Input Voltage

Operating Junction Temperature Operating Ambient Temperature

TA

–40 to +85

°C

Storage Temperature

Tstg

–55 to +150

°C

Tsolder

10

sec





Symbol


Vout


Vout

Min

Typ

Max

1.455 1.746 2.425 2.646 2.744 2.94 3.234 4.900

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

1.545 1.854 2.575 2.754 2.856 3.06 3.366 5.100

1.455 1.746 2.425 2.619 2.716 2.910 3.201 4.900

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

1.545 1.854 2.575 2.781 2.884 3.09 3.399 5.100

Unit V

V


Regline

–

2.0

4.5

mV/V

Load Regulation (Iout = 1.0 mA to 80 mA, Vin = Vout + 2.0 V)

Regload

–

0.3

0.8

mV/mA

Output Current (Vin = Vout + 2.0 V) 1.5 V, 1.8 V 2.5 V, 2.7 V, 2.8 V, 3.0 V 3.3 V, 5.0 V

Io(nom.) 80 80 80 80

180 180 180 180

– – – –


Vin–Vout

Quiescent Current (Enable Input = 0 V) (Enable Input = Vin, Iout = 1.0 mA to Io(nom.), Vin = Vout +2.0 V) Output Short Circuit Current (Vin = Vout + 2.0 V) 1.5 V, 1.8 V 2.5 V, 2.7 V, 2.8 V, 3.0 V 3.3 V, 5.0 V

mA

mV – – – – – – – –

1300 1100 800 750 730 680 650 470

1800 1600 1400 1200 1200 1000 1000 1000

– –

0.1 2.8

1.0 6.0

100 100 100 100

230 300 300 300

450 450 450 450

–

90

–

1.3 –

– –

– 0.3

–

"100

–

µA

IQ

Iout(max)

Output Voltage Noise (f = 20 Hz to 100 kHz, Iout = 10 mA) (Cout = 1.0 µF) Enable Input Threshold Voltage (Voltage Increasing, Output Turns On, Logic High) (Voltage Decreasing, Output Turns Off, Logic Low)

Vn

mA

Vth(en)


TC

V



µVrms

ppm/°C


Line Regulation



Dropout Voltage











1

3.03 Vout(nom.) = 3.0 V

0.9

Vout, OUTPUT VOLTAGE (VOLTS)

Vin – Vout, DROPOUT VOLTAGE (VOLTS)

NCP552

0.8 0.7

80 mA

0.6 0.5 0.4

40 mA

0.3 0.2 0.1 0 –50

–25

0

25

50

75

100

Vout(nom.) = 3.3 V 3.025 Iout = 5 mA 3.02

3.01 3.005 3 –60

125

–20

–40

40

20

0

80

60

TEMPERATURE (_C)

TEMPERATURE (_C)



3 2.75 2.5 2.25 2 1.75 –60

Vout(nom.) = 3 V Iout = 0 mA

4 3.5 3 2.5 2 1.5 1 0.5 0

–40

–20

0

20

40

60

80

100

0

2

TEMPERATURE (_C)

3.5 3 2.5


10 mA

1.5 50 mA

0.5 0 10

100

1000

10000

8

6

10

12


Vin, INPUT VOLTAGE (V)

4

2

4

Vin, INPUT VOLTAGE (VOLTS)


1

100

4.5 Iout = 0 mA Vin = 4 V

Iq, QUIESCENT CURRENT (µA)


Vin = 4 V

3.015

3.25

OUTPUT NOISE (V/ǰHz)

Vin = 12 V

100000

1000000

6 Iout = 1 mA Cout = 1 µF

5 4 200 100 0 –100

0

0.5

1

1.5

2

2.5

3

3.5

FREQUENCY (Hz)

TIME (s)

Figure 6. Output Noise Density



4

4.5

Vin = 4 V Cout = 10 F

400 200

ENABLE VOLTAGE (V)

200 0

–200

0


–400

Iout, OUTPUT CURRENT (V)

150 100 50 0

100 50 0 –50

0

OUTPUT VOLTAGE (V)


600

10

20

30

40

0

50

0.5

1

1.5

2

TIME (ms)

TIME (ms)



3.5 Vout, OUTPUT VOLTAGE (VOLTS)

Iout, OUTPUT CURRENT (mA)


NCP552

5 0

3 2 Iout = 10 mA Cin = 1 F Cout = 0.1 F Vin = 4 V

1 0 0

100

200

300

400

3 2.5 2 1.5 1

Cin = 1 F Cout = 1 F TA = 25 _C

0.5 0

500

600

700

0

2

4

6

8

10

12

TIME (s)


Figure 10. Turn–On Response






A 1.0 µF capacitor either ceramic or tantalum is recommended and should be connected close to the NCP552 package. Higher values and lower ESR will improve the overall line transient response. If large line or load transients are not expected, then it is possible to operate the regulator without the use of a capacitor. TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K

Thermal



The NCP552 is a stable regulator and does not require any specific Equivalent Series Resistance (ESR) or a minimum output current. If load transients are not to be expected, then it is possible for the regulator to operate with no output capacitor. Otherwise, capacitors exhibiting ESRs ranging from a few mΩ up to 10 Ω can thus safely be used. The minimum decoupling value is 0.1 µF and can be augmented to fulfill stringent load transient requirements. The regulator accepts ceramic chip capacitors as well as tantalum devices. Larger values improve noise rejection and load regulation transient response. TDK capacitor: C2012X5R1C105K, C1608X5R1A105K, or C3216X7R1C105K




Enable Operation


If an 80 mA output current is needed then the ground current from the data sheet is 2.8 µA. For an NCP552 (3.0 V), the maximum input voltage will then be 6.12 V.

Hints



NCP552 INFORMATION FOR USING THE SC–82AB SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection


#6#

#6#

#7#

#6#

#7#

9#

#7# -#

SC–82AB (SC70–4)




Marking

Package

Shipping

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

LAW LAX LAY LAZ LBA LBB LBC LBD

SC82 AB SC82–AB (SC70–4) (SC70 4)




"- #$ " % 01 "-E The NCP553 series of fixed output NOCAP linear regulators are designed for handheld communication equipment and portable battery powered applications which require low quiescent. The NCP553 series features an ultra–low quiescent current of 2.8 µA. Each device contains a voltage reference unit, an error amplifier, a PMOS power transistor, resistors for setting output voltage, current limit, and temperature limit protection circuits. The NCP553 has been designed to be used with low cost ceramic capacitors. This device has the ability to operate without an output capacitor. The device is housed in the micro–miniature SC82–AB surface mount package. Standard voltage versions are 1.5, 1.8, 2.5, 2.7, 2.8, 3.0, 3.3, and 5.0 V. Other voltages are available in 100 mV steps.

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4

1 SC82–AB (SC70–4) SQ SUFFIX CASE 419C

Features

• • • •

Low Quiescent Current of 2.8 µA Typical Low Output Voltage Option Output Voltage Accuracy of 2.0% Industrial Temperature Range of –40°C to 85°C


Gnd 1 xxxM


• Battery Powered Consumer Products • Hand–Held Instruments • Camcorders and Cameras

Vin 2

Output

C1

= Device Code = Date Code


N/C

Input Vin

3 Vout (Top View)

xxx M

Gnd

4 N/C


Vout

*

*

C2





304


NCP553

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin No.

Pin Name

1

Gnd


Description

2

Vin


3

Vout


4

N/C


MAXIMUM RATINGS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating

Symbol

Value

Unit

Input Voltage

Vin

12

V

Output Voltage

Vout

–0.3 to Vin +0.3

V


PD RθJA


W °C/W


TJ

+125

°C


TA

–40 to +85

°C

Storage Temperature

Tstg

–55 to +150

°C

Tsolder

10

sec




NCP553 ELECTRICAL CHARACTERISTICS (Vin = Vout(nom.) + 1.0 V, Cin = 1.0 µF, Cout = 1.0 µF, TJ = 25°C, unless otherwise noted.) Characteristic

Symbol


Vout


Vout

Min

Typ

Max

1.455 1.746 2.425 2.646 2.744 2.94 3.234 4.900

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

1.545 1.854 2.575 2.754 2.856 3.06 3.366 5.100

1.455 1.746 2.425 2.619 2.716 2.910 3.201 4.900

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

1.545 1.854 2.575 2.781 2.884 3.09 3.399 5.100

Unit V

V


Regline

–

2.0

4.5

mV/V

Load Regulation (Iout = 1.0 mA to 80 mA, Vin = Vout + 2.0 V)

Regload

–

0.3

0.8

mV/mA

Output Current (Vin = Vout + 2.0 V) 1.5 V, 1.8 V 2.5 V, 2.7 V, 2.8 V, 3.0 V 3.3 V, 5.0 V

Io(nom.) 80 80 80 80

180 180 180 180

– – – –


Vin–Vout

Quiescent Current (Iout = 1.0 mA to Io(nom.), Vin = Vout +2.0 V)

mA

mV – – – – – – – –

1300 1100 800 750 730 680 650 470

1800 1600 1400 1200 1200 1000 1000 1000

–

2.8

6.0

100 100 100 100

230 300 300 300

450 450 450 450

µA

IQ

Output Short Circuit Current (Vin = Vout + 2.0 V) 1.5 V, 1.8 V 2.5 V, 2.7 V, 2.8 V, 3.0 V 3.3 V, 5.0 V

Iout(max)

mA

Output Voltage Noise (f = 100 Hz to 100 kHz, Iout = 10 mA) Cout = 1 µF

Vn

–

90

–

µVrms


TC

–

"100

–

ppm/°C




Line Regulation



Dropout Voltage











1

3.03 Vout(nom.) = 3.0 V

0.9


Vin – Vout, DROPOUT VOLTAGE (VOLTS)

NCP553

0.8 0.7

80 mA

0.6 0.5 0.4

40 mA

0.3 0.2 0.1 0 –50

–25

0

25

50

75

Vout(nom.) = 3.3 V 3.025 Iout = 5 mA 3.02

3.01 3.005 3 –60

40

20

0

80

60

TEMPERATURE (_C)


Figure 3. Output Voltage vs. Temperature

100

4.5

3


Iout = 0 mA Vin = 4 V

2.75 2.5 2.25 2 1.75 –60

Vout(nom.) = 3 V Iout = 0 mA

4 3.5 3 2.5 2 1.5 1 0.5 0

–40

–20

0

20

40

60

80

100

0

2

TEMPERATURE (_C)

3.5 3 2.5


10 mA

1.5 1

50 mA

0.5 0 10

100

1000

10000

8

6

10

12

Figure 5. Quiescent Current vs. Input Voltage


4

2

4



OUTPUT NOISE (V/ǰHz)

–20

–40

TEMPERATURE (_C)

3.25 Iq, QUIESCENT CURRENT (µA)

Vin = 4 V

3.015

125

100

Vin = 12 V

100000

1000000

6 Iout = 1 mA Cout = 1 µF

5 4 200 100 0 –100

0

0.5

1

1.5

2

2.5

3

3.5

FREQUENCY (Hz)

TIME (s)




4

4.5


400 200


600

200 0

–200

0


–400

Iout, OUTPUT CURRENT (V)

150 100 50 0

100 50 0 –50

0

10

20

30

40

0

50

0.5

1

1.5

TIME (ms)

TIME (ms)






NCP553

3 2.5 2 1.5 1

Cin = 1 F Cout = 1 F TA = 25 _C

0.5 0 0

2

4

6

8

10


Figure 10. Output Voltage vs. Input Voltage


12

2

NCP553 APPLICATIONS INFORMATION Set external components, especially the output capacitor, as close as possible to the circuit, and make leads as short as possible.

A typical application circuit for the NCP553 series is shown in Figure 1, front page. Input Decoupling (C1)

A 0.1 µF capacitor either ceramic or tantalum is recommended and should be connected close to the NCP553 package. Higher values and lower ESR will improve the overall line transient response. If large line or load transients are not expected, then it is possible to operate the regulator without the use of a capacitor. TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K

Thermal



The NCP553 is a stable regulator and does not require any specific Equivalent Series Resistance (ESR) or a minimum output current. If load transients are not to be expected, then it is possible for the regulator to operate with no output capacitor. Otherwise, capacitors exhibiting ESRs ranging from a few mΩ up to 10 Ω can thus safely be used. The minimum decoupling value is 0.1 µF and can be augmented to fulfill stringent load transient requirements. The regulator accepts ceramic chip capacitors as well as tantalum devices. Larger values improve noise rejection and load regulation transient response. TDK capacitor: C2012X5R1C105K, C1608X5R1A105K, or C3216X7R1C105K




Hints


If an 80 mA output current is needed then the ground current from the data sheet is 2.8 µA. For an NCP553 (3.0 V), the maximum input voltage will then be 6.12 V.


NCP553 INFORMATION FOR USING THE SC–82AB SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection


#6#

#6#

#7#

#6#

#7#

9#

#7# -#

SC–82AB (SC70–4)




Marking

Package

Shipping

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

LBE LBF LBG LBH LBI LBJ LBK LBL

SC82 AB SC82–AB (SC70–4) (SC70 4)




"-&/ #$ " % 01 %() The NCP562 series of fixed output low–dropout linear regulators are designed for handheld communication equipment and portable battery powered applications which require low quiescent. The NCP562 series features an ultra–low quiescent current of 2.5 µA. Each device contains a voltage reference unit, an error amplifier, a PMOS power transistor, resistors for setting output voltage, current limit, and temperature limit protection circuits. The NCP562 has been designed to be used with low cost ceramic capacitors and requires a minimum output capacitor of 0.1 µF. The device is housed in the micro–miniature SC82–AB surface mount package. Standard voltage versions are 1.5, 1.8, 2.5, 2.7, 2.8, 3.0, 3.3, and 5.0 V. Features

• • • •

Low Quiescent Current of 2.5 µA Typical Low Output Voltage Option Output Voltage Accuracy of 2.0% Temperature Range of –40°C to 85°C

http://onsemi.com MARKING DIAGRAM SC82–AB (SC70–4) SQ SUFFIX CASE 419C

4

xxxM

1 xxx = Device Code M = Date Code

PIN CONNECTIONS Gnd 1

4 Enable


• Battery Powered Instruments • Hand–Held Instruments • Camcorders and Cameras

Vin 2 (Top View)


ON Gnd

3 Vout


Enable OFF Output

Input Vin C1

Vout

*

*

C2


Figure 1. Representative Block Diagram



313


NCP562

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin No.

Pin Name

1

Gnd


Description

2

Vin


3

Vout


4

Enable


MAXIMUM RATINGS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating

Symbol

Value

Unit

Vin

6.0

V

Enable Voltage

Enable

–0.3 to Vin +0.3

V

Output Voltage

Vout

–0.3 to Vin +0.3

V


PD RθJA


W °C/W

TJ

+125

°C

Input Voltage

Operating Junction Temperature Operating Ambient Temperature

TA

–40 to +85

°C

Storage Temperature

Tstg

–55 to +150

°C

Tsolder

10

sec




NCP562 ELECTRICAL CHARACTERISTICS (Vin = Vout(nom.) + 1.0 V, Venable = Vin, Cin = 1.0 µF, Cout = 1.0 µF, TJ = 25°C, unless otherwise noted.) Symbol

Characteristic Output Voltage (TA = 25°C, Iout = 1.0 mA) 1.5 V 1.8 V 2.5 V 2.7 V 2.8 V 3.0 V 3.3 V 5.0 V

Min

Typ

Max

1.455 1.746 2.425 2.646 2.744 2.940 3.234 4.9

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

1.545 1.854 2.575 2.754 2.856 3.060 3.366 5.1

– –

10 10

20 20

–

20

40

80 80

280 280

– –

Vout

Line Regulation 1.5 V–4.4 V (Vin = Vo(nom.) + 1.0 V to 6.0 V 4.5 V–5.0 V (Vin = 5.5 V to 6.0 V)

Regline

Load Regulation (Iout = 10 mA to 80 mA)

Regload

Output Current (Vout = (Vout at Iout = 80 mA) –3.0%) 1.5 V to 3.9 V (Vin = Vout(nom.) + 2.0 V) 4.0 V–5.0 V (Vin = 6.0 V)

Io(nom.)

Dropout Voltage (TA = –40°C to 85°C, Iout = 80 mA, Measured at Vout –3.0%) 1.5 V–1.7 V 1.8 V–2.4 V 2.5 V–2.6 V 2.7 V–2.9 V 3.0 V–3.2 V 3.3 V–4.9 V 5.0 V

Vin–Vout


V

mV

mV – – – – – – –

550 400 250 230 200 190 140

800 550 400 400 350 350 250

– –

0.1 2.5

1.0 6.0

600 150

300 300

600 600

–

100

–

1.3 –

– –

– 0.3

–

"100

–

µA

Iout(max)

Output Voltage Noise (f = 100 Hz to 100 kHz, Vout = 3.0 V) Enable Input Threshold Voltage (Voltage Increasing, Output Turns On, Logic High) (Voltage Decreasing, Output Turns Off, Logic Low)

Vn

mA

Vth(en)


TC

T *TA PD + J(max) RJA 4. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.

315

µVrms V

3. Maximum package power dissipation limits must be observed.

http://onsemi.com

mV mA

IQ

Output Short Circuit Current 1.5 V to 3.9 V (Vin = Vnom + 2.0 V) 4.0 V–5.0 V (Vin = 6.0 V)

Unit

ppm/°C

NCP562 3 VIN = 4.0 V VOUT = 3.0 V IOUT = 0 mA

2.7



2.9

2.5 2.3 2.1 1.9

VOUT = 3.0 V

2.5 2 1.5 1 0.5 0

1.7 –60

–40

–20

0

40

20

60

80

0

100

1


3

VIN = 6.0 V

6

3.010 3.005 3.000 VIN = 4.0 V

IOUT = 30 mA 2.5 2 1.5 1 0.5 0

–40

0

–20

20

40

60

80

100

0

1

2

3

4

5





6

4

300 VOUT(nom) = 3.0 V 250 80 mA LOAD 200

ENABLE VOLTAGE (V)



3.015

150

2 VIN = 4.0 V CIN = 1.0 F

0 3

40 mA LOAD

100 50

10 mA LOAD

0 –50

–25

0

25

50

75

100



3.5

2.990 –60

5

4


3.020

2.995

3



VOUT(nom) = 3.0 V IOUT = 10 mA

2

COUT = 0.1 F IOUT = 10 mA

2 1 0

125

0


50

100

150

200

250

300

t, TIME (s)




350 400


6 5 4 3


1 0.5 0

VOUT = 3.0 V COUT = 0.1 F IOUT = 10 mA

–0.5 –1 0

50

100 150 200 250 300 350 400

60 IOUT = 1 mA to 30 mA VIN = 4.0 V

30 0 –30 1 VOUT = 3.0 V COUT = 0.1 F

0.5 0 –0.5 –1

450 500

0

50

100 150 200 250 300 350 400

t, TIME (s)

t, TIME (s)


Vn, OUTPUT VOLTAGE NOISE (mV/√Hz)

OUTPUT VOLTAGE DEVIATION (V)


NCP562


3.5 VIN = 5.0 V VOUT = 3.0 V IOUT = 50 mA COUT = 0.1 F

3 2.5 2 1.5 1 0.5 0 0.01

0.1

1

10

100

f, FREQUENCY (kHz)

Figure 10. Output Voltage Noise


1000

450 500


Line Regulation



Dropout Voltage











NCP562 APPLICATIONS INFORMATION A typical application circuit for the NCP562 series is shown in Figure 1.




Thermal



The NCP562 is a stable regulator and does not require any specific Equivalent Series Resistance (ESR) or a minimum output current. Capacitors exhibiting ESRs ranging from a few mΩ up to 10 Ω can thus safely be used. The minimum decoupling value is 0.1 µF and can be augmented to fulfill stringent load transient requirements. The regulator accepts ceramic chip capacitors as well as tantalum devices. Larger values improve noise rejection and load regulation transient response. TDK capacitor: C2012X5R1C105K, C1608X5R1A105K, or C3216X7R1C105K


If junction temperature is not allowed above the maximum 125°C, then the NCP562 can dissipate up to 250 mW @ 25°C. The power dissipated by the NCP562 can be calculated from the following equation:

Enable Operation

The enable pin will turn on the regulator when pulled high and turn off the regulator when pulled low. These limits of threshold are covered in the electrical specification section of this data sheet. If the enable is not used, then the pin should be connected to Vin.



If an 80 mA output current is needed then the ground current from the data sheet is 2.5 µA. For an NCP562SQ30T1 (3.0 V), the maximum input voltage will then be 6.0 V.

Hints


MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection


#6#

#6#

#7#

#6#

#7#

9#

#7# -#

SC–82AB (SC70–4) http://onsemi.com 319



Marking

Package

Shipping

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

LDI LEY LDK LEZ LDL LDM LDN LDP

SC82–AB


Additional voltages are available upon request by contacting your ON Semiconductor representative.


"-& #$ " % 01 %() The NCP563 series of fixed output low–dropout linear regulators are designed for handheld communication equipment and portable battery powered applications which require low quiescent. The NCP563 series features an ultra–low quiescent current of 2.5 µA. Each device contains a voltage reference unit, an error amplifier, a PMOS power transistor, resistors for setting output voltage, current limit, and temperature limit protection circuits. The NCP563 has been designed to be used with low cost ceramic capacitors and requires a minimum output capacitor of 0.1 µF. The device is housed in the micro–miniature SC82–AB surface mount package. Standard voltage versions are 1.5, 1.8, 2.5, 2.7, 2.8, 3.0, 3.3, and 5.0 V. Features

• • • •

Low Quiescent Current of 2.5 µA Typical Low Output Voltage Option Output Voltage Accuracy of 2.0% Temperature Range of –40°C to 85°C

http://onsemi.com MARKING DIAGRAM SC82–AB (SC70–4) SQ SUFFIX CASE 419C

4

xxxM

1 xxx = Device Code M = Date Code

PIN CONNECTIONS Gnd 1

4 N/C

Vin 2

3 Vout



(Top View)

ORDERING INFORMATION Gnd

N/C

Vin

Vout


Output

Input

C1

*

*

C2





321


NCP563

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin No.

Pin Name

1

Gnd


Description

2

Vin


3

Vout


4

N/C


MAXIMUM RATINGS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating

Symbol

Value

Unit

Input Voltage

Vin

6.0

V

Output Voltage

Vout

–0.3 to Vin +0.3

V


PD RθJA


W °C/W


TJ

+125

°C


TA

–40 to +85

°C

Storage Temperature

Tstg

–55 to +150

°C

Tsolder

10

sec




NCP563 ELECTRICAL CHARACTERISTICS (Vin = Vout(nom.) + 1.0 V, Cin = 1.0 µF, Cout = 1.0 µF, TJ = 25°C, unless otherwise noted.) Characteristic

Symbol

Output Voltage (TA = 25°C, Iout = 1.0 mA) 1.5 V 1.8 V 2.5 V 2.7 V 2.8 V 3.0 V 3.3 V 5.0 V

Min

Typ

Max

1.455 1.746 2.425 2.646 2.744 2.940 3.234 4.9

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

1.545 1.854 2.575 2.754 2.856 3.060 3.366 5.1

– –

10 10

20 20

–

20

40

80 80

280 280

– –

Vout

Line Regulation 1.5 V–4.4 V (Vin = Vo(nom.) + 1.0 V to 6.0 V) 4.5 V–5.0 V (Vin = 5.5 V to 6.0 V)

Regline


Regload

Output Current (Vout = (Vout at Iout = 80 mA) –3.0%) 1.5 V to 3.9 V (Vin = Vout(nom.) + 2.0 V) 4.0 V–5.0 V (Vin = 6.0 V)

Io(nom.)

Dropout Voltage (TA = –40°C to 85°C, Iout = 80 mA, Measured at Vout –3.0%) 1.5 V–1.7 V 1.8 V–2.4 V 2.5 V–2.6 V 2.7 V–2.9 V 3.0 V–3.2 V 3.3 V–4.9 V 5.0 V

Vin–Vout

Quiescent Current (Iout = 1.0 mA to Iout(nom))

IQ

Output Short Circuit Current 1.5 V to 3.9 V (Vin = Vnom + 2.0 V) 4.0 V–5.0 V (Vin = 6.0 V)

Unit V

mV

mV mA

mV – – – – – – –

550 400 250 230 200 190 140

800 550 400 400 350 350 250

–

2.5

6.0

Iout(max)

µA mA

100 150

300 300

600 600

Output Voltage Noise (f = 100 Hz to 100 kHz, Vout = 3.0 V)

Vn

–

100

–

µVrms


TC

–

"100

–

ppm/°C



NCP563 3 VIN = 4.0 V VOUT = 3.0 V IOUT = 0 mA

2.7



2.9

2.5 2.3 2.1 1.9

VOUT = 3.0 V

2.5 2 1.5 1 0.5 0

1.7 –60

–40

–20

0

20

40

60

80

0

100

1


3


3.015 VIN = 6.0 V 3.010 3.005 3.000

5

6

VIN = 4.0 V

IOUT = 30 mA 2.5 2 1.5 1 0.5 0

–40

–20

0

20

40

80

60

100

0

1

2

3

4

5







3.5

2.990 –60

4


3.020

2.995

3



VOUT(nom) = 3.0 V IOUT = 10 mA

2

300 VOUT(nom) = 3.0 V 250 80 mA LOAD 200 150 40 mA LOAD

100 50

10 mA LOAD

0 –50

–25

0

25

50

75

100

125




6


6 5 4 3


1 0.5 0

VOUT = 3.0 V COUT = 0.1 F IOUT = 10 mA

–0.5 –1 0

50

100 150 200 250 300 350 400

60 IOUT = 1 mA to 30 mA VIN = 4.0 V

30 0 –30 1 VOUT = 3.0 V COUT = 0.1 F

0.5 0 –0.5 –1

450 500

0

50

100 150 200 250 300 350 400

t, TIME (s)

t, TIME (s)


Vn, OUTPUT VOLTAGE NOISE (mV/√Hz)



NCP563


3.5 VIN = 5.0 V VOUT = 3.0 V IOUT = 50 mA COUT = 0.1 F

3 2.5 2 1.5 1 0.5 0 0.01

0.1

1

10

100

f, FREQUENCY (kHz)

Figure 9. Output Voltage Noise


1000

450 500


Line Regulation



Dropout Voltage











NCP563 APPLICATIONS INFORMATION Thermal

A typical application circuit for the NCP563 series is shown in Figure 1.





The NCP563 is a stable regulator and does not require any specific Equivalent Series Resistance (ESR) or a minimum output current. Capacitors exhibiting ESRs ranging from a few mΩ up to 10 Ω can thus safely be used. The minimum decoupling value is 0.1 µF and can be augmented to fulfill stringent load transient requirements. The regulator accepts ceramic chip capacitors as well as tantalum devices. Larger values improve noise rejection and load regulation transient response. TDK capacitor: C2012X5R1C105K, C1608X5R1A105K, or C3216X7R1C105K




Hints

Please be sure the Vin and Gnd lines are sufficiently wide. When the impedance of these lines is high, there is a chance to pick up noise or cause the regulator to malfunction. Set external components, especially the output capacitor, as close as possible to the circuit, and make leads as short as possible.

If an 80 mA output current is needed then the ground current from the data sheet is 2.5 µA. For an NCP563SQ30T1 (3.0 V), the maximum input voltage will then be 6.0 V.



#6#

#6#

#7#

#6#

#7#

9#

#7# -#

SC–82AB (SC70–4)




Marking

Package

Shipping

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

LDQ LFA LDS LFB LDT LDU LDV LDX

SC82–AB




/2

$$ ) %* &$3 ) - The LM2931 series consists of positive fixed and adjustable output voltage regulators that are specifically designed to maintain proper regulation with an extremely low input–to–output voltage differential. These devices are capable of supplying output currents in excess of 100 mA and feature a low bias current of 0.4 mA at 10 mA output. Designed primarily to survive in the harsh automotive environment, these devices will protect all external load circuitry from input fault conditions caused by reverse battery connection, two battery jump starts, and excessive line transients during load dump. This series also includes internal current limiting, thermal shutdown, and additionally, is able to withstand temporary power–up with mirror–image insertion. Due to the low dropout voltage and bias current specifications, the LM2931 series is ideally suited for battery powered industrial and consumer equipment where an extension of useful battery life is desirable. The ‘C’ suffix adjustable output regulators feature an output inhibit pin which is extremely useful in microprocessor–based systems. • Input–to–Output Voltage Differential of < 0.6 V @ 100 mA • Output Current in Excess of 100 mA • Low Bias Current • 60 V Load Dump Protection • –50 V Reverse Transient Protection • Internal Current Limiting with Thermal Shutdown • Temporary Mirror–Image Protection • Ideally Suited for Battery Powered Equipment • Economical 5–Lead TO–220 Package with Two Optional Leadforms • Available in Surface Mount SOP–8, D2PAK and DPAK Packages • High Accuracy (±2%) Reference (LM2931AC) Available

http://onsemi.com FIXED OUTPUT VOLTAGE TO–92 Z SUFFIX CASE 29

Pin 1. Output 2. Ground 3. Input

1 2 3


1 2 3


1


Pin 1. Input 2. Ground 3. Output 3

1

3

ADJUSTABLE OUTPUT VOLTAGE TO–220 TH SUFFIX CASE 314A

1 5

TO–220 1 TV SUFFIX CASE 314B

TO–220 T SUFFIX CASE 314D

5

1

Pin 1. Adjust 2. Output Inhibit 3. Ground 4. Input 5. Output

5

SOIC–8 D SUFFIX CASE 751

D2PAK D2T SUFFIX 1 CASE 936A 1

FIXED @

7

) '

% '&

)

)

%

'

0> 1



ORDERING INFORMATION ADJUSTABLE

@

5

8

7

",


) %

0> 1

329

DEVICE MARKING INFORMATION See general marking and heatsink information in the device marking section on page 341 of this data sheet.


LM2931 Series Representative Schematic Diagram ' 6#

-# /

6# /

67

- #

##

% '&

% -# /

-# / -9 /

",

-# /

-# /

# / 7C/

7#C/

7C/

:(' I

9 7 / - C/

/ ) C%2>"):C01

## = ∆ = ## >E = °

6# # 7# # #

#

#

# 6# '%B %D>(D> D:@> 0"1

7#

= ∆ = ##

## '% = # " '% = # " #

##

#

#

8

##


6# >E = +#°

% BC%D>(D>C%2>"):C01

' % BC%D>(D>CD:@>C0"1

- #

>E = °

# >E = 7 °

# " = °

# # -# #

2 = # Ω

# #

-#

#

Figure 3. Peak Output Current versus Input Voltage

# -# # = # 2 = ## Ω >" = °

# # + #

+#

#

# # -# B '@(D> %2>"): 01

#

#

# -# # B '@(D> %2>"): 01

6#

#

6#


%BC%D>(D>C%2>"): 0 #CO:G(:">D: 0°1


#

'% = ## "

##

= # 2 = # Ω % = ## µ$ τ = # >" = ° #

#


B >'G: 0 # O %2>"): 01

#

#

#

#

#

6#

= = # >E = °

6#

#

#

6#

7#

##

'%B %D>(D> D:@> 0"1

Figure 8. Bias Current versus Output Current

Figure 7. Bias Current versus Input Voltage

#

7# = = #

'% = ## "

6#

'% BC%D>(D>C'G(:C0"1

#

# '% = # "

#

= = # '% = # " D: 0°1

##

#

#

Figure 9. Bias Current versus Junction Temperature

# G

# G

9

BC'((2:C:E:>'%@C">'%C0I1

BC'((2:C:E:>'%@C">'%C0I1

# / # / ## / B $:HD:@K 0.A1

Figure 10. Output Impedance versus Frequency

9

7

%0:F1 = # Ω >

= = # E = °

8

6

##

#

##

%0:F1 = #- Ω :! # /

# /

## /

# G

# G

7

= = # = # .A >E = °

8

6

#

B $:HD:@K 0.A1


#

# 6# '%B %D>(D> D:@> 0"1

7#

##



= # 2 = ## Ω % = ## µ$ %0:F1 = #- Ω >" = °

7

B >'G: 0# µO(D>C'@.'I'>N>.:F.%2'G: 0# µO(D> %2>"): 01

Figure 15. Reference Voltage versus Output Voltage

6#

9#

7 %B %D>(D> %2>"): 01

Figure 16. Output Inhibit–Thresholds versus Output Voltage

APPLICATIONS INFORMATION The LM2931 series regulators are designed with many protection features making them essentially blow–out proof. These features include internal current limiting, thermal shutdown, overvoltage and reverse polarity input protection, and the capability to withstand temporary power–up with mirror–image insertion. Typical application circuits for the fixed and adjustable output device are shown in Figures 17 and 18. The input bypass capacitor Cin is recommended if the regulator is located an appreciable distance (≥ 4″) from the supply input filter. This will reduce the circuit’s sensitivity to the input line impedance at high frequencies. This regulator series is not internally compensated and thus requires an external output capacitor for stability. The capacitance value required is dependent upon the load current, output voltage for the adjustable regulator, and the type of capacitor selected. The least stable condition is encountered at maximum load current and minimum output voltage. Figure 22 shows that for operation in the “Stable” region, under the conditions specified, the magnitude of the output capacitor impedance |ZO| must not exceed 0.4 Ω. This

limit must be observed over the entire operating temperature range of the regulator circuit. With economical electrolytic capacitors, cold temperature operation can pose a serious stability problem. As the electrolyte freezes, around –30°C, the capacitance will decrease and the equivalent series resistance (ESR) will increase drastically, causing the circuit to oscillate. Quality electrolytic capacitors with extended temperature ranges of –40° to +85°C and –55° to +105°C are readily available. Solid tantalum capacitors may be a better choice if small size is a requirement, however, the maximum ZO limit over temperature must be observed. Note that in the stable region, the output noise voltage is linearly proportional to ZO. In effect, CO dictates the high frequency roll–off point of the circuit. Operation in the area titled “Marginally Stable” will cause the output of the regulator to exhibit random bursts of oscillation that decay in an under–damped fashion. Continuous oscillation occurs when operating in the area titled “Unstable”. It is suggested that oven testing of the entire circuit be performed with maximum load, minimum input voltage, and minimum ambient temperature.


LM2931 Series '

/ #

LM2931C ",& %

% '&

%

LM2931+ # $5 %

'

#

%

)

ǒ

Ǔ

+ ) ) ' ",

/ w

)


> $ 9 & Q ! &! F (@( > (@( & & 2G 9- F & &

Figure 19. (5.0 A) Low Differential Voltage Regulator

Figure 20. Current Boost Regulator with Short Circuit Projection

LM2931C

BC%D>(D>C@%'F:C%2>"):C01

##

' 6 -#

*

# / ## 7 /

##

*

-- /

G U-

6 #

#

= 6 = # '% = ## " # .A # G.A 4M%4 T # /.A >" = °

#

#

## #

= .A

Figure 21. Constant Intensity Lamp Flasher

D& G! F&

F&

## # / 4M%4B G")@'>D"@:

8#

-

#

-# #

ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ

#

) ! !

9#

2

8#

6

# A 2

# -#

7

(" = #°

-#

#7

θE" #

#

#

-#

#

#

#

('%@C0J1

LM2931 Series

2B 2:@)>. %$ %((: 01

ED@>'%@+>%+"'C0CCOJ1 °

θ E"BC>.:G"2C:F'F>"@:

## 9#

#


7# G FA (

8# 6#

# A 2

6

2

#7

# #

(" = #°

$ " G !

#

θE" #

#

#

#

-#

#

('%@C0J1


2B 2:@)>. %$ %((: 01

ED@>'%@+>%+"'C0CCOJ1 °

θ E"BC>.:G"2C:F'F>"@:

7#

-

(" = #°

8#

-#

$ " G !

6#

G FA (

# # -#

ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ # A 2

#

#

#

2

θE" #

#

2B 2:@)>. %$ %((: 01

Figure 25. 3–Pin and 5–Pin D2PAK Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length


-#

#

('%@C0J1


LM2931 Series DEFINITIONS Maximum Power Dissipation – The maximum total device dissipation for which the regulator will operate within specifications. Bias Current – That part of the input current that is not delivered to the load. Output Noise Voltage – The rms AC voltage at the output, with constant load and no input ripple, measured over a specified frequency range. Long–Term Stability – Output voltage stability under accelerated life test conditions with the maximum rated voltage listed in the devices electrical characteristics and maximum power dissipation.

Dropout Voltage – The input/output voltage differential at which the regulator output no longer maintains regulation against further reductions in input voltage. Measured when the output decreases 100 mV from nominal value at 14 V input, dropout voltage is affected by junction temperature and load current. Line Regulation – The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. Load Regulation – The change in output voltage for a change in load current at constant chip temperature.


LM2931 Series ORDERING INFORMATION Output Device

Voltage

Tolerance

Package

Shipping

LM2931AD–5.0

SOIC–8

98 Units/Rail

LM2931AD–5.0R2

SOIC–8

2500 Tape & Reel

DPAK

75 Units/Rail

LM2931ADT–5.0RK

DPAK

2500 VacPk Reel

LM2931AD2T–5.0

D2PAK

50 Units/Rail

D2PAK

800 VacPk Reel

LM2931AT–5.0

TO–220

50 Units/Rail

LM2931AZ–5.0

TO–92

2000/Inner Bag

LM2931AZ–5.0RA

TO–92

2000 Tape & Reel

TO–92

2000/Ammo Pack

LM2931ADT–5.0

"3 8% "3.8%

LM2931AD2T–5.0R4

LM2931AZ–5.0RP

5.0 V

LM2931D–5.0

SOIC–8

98 Units/Rail

LM2931D–5.0R2

SOIC–8

2500 Tape & Reel

LM2931D2T–5.0

D2PAK

50 Units/Rail

LM2931D2T–5.0R4

D2PAK

800 VacPk Reel

LM2931DT–5.0

DPAK

75 Units/Rail

TO–220

50 Units/Rail

LM2931T–5.0 LM2931Z–5.0

TO–92

2000/Inner Bag

TO–92

2000 Tape & Reel

LM2931Z–5.0RP

TO–92

2000/Ammo Pack

LM2931CD

SOIC–8

98 Units/Rail

LM2931CDR2

SOIC–8

2500 Tape & Reel

LM2931CD2T

D2PAK

50 Units/Rail

LM2931CD2TR4

D2PAK

800 VacPk Reel

LM2931CT

TO–220

50 Units/Rail

SOIC–8

98 Units/Rail

SOIC–8

2500 Tape & Reel

D2PAK

800 VacPk Reel

TO–220

50 Units/Rail

"5 0% "5.0%

LM2931Z–5.0RA

Adjustable j

LM2931ACD LM2931ACDR2 LM2931ACD2TR4

"2 0% "2.0%

LM2931ACTV


LM2931 Series MARKING DIAGRAMS






931A5 ALYWW

2931 ALYWW

LM 2931AD2T–5 AWLYWW

LM 2931AD2T–5.0 AWLYWW

LM 2931D2T–5 AWLYWW



LM2931AT–5 AWLYWW



LM 2931T–5.0 AWLYWW

LM 2931ACTV AWLYWW

Heatsink surface connected to Pin 2.

SO–8 D SUFFIX CASE 751 8


2931A ALYW 1

Heatsink surface connected to Pin 3.


2931A ALYW5 1

1

LM 2931CT AWLYWW


TO–92 Z SUFFIX CASE 029

2931 ALYW5

2931A Z–5.0 YWW

2931Z –5.0 YWW

= Assembly Location = Wafer Lot = Year = Work Week


LM 2931ACD2T AWLYWW

TO–92 Z SUFFIX CASE 029

1

A WL, L YY, Y WW, W

D2PAK D2T SUFFIX CASE 936A


2931C ALYW


-/2$ -/2 $$ $ % -% % ) The LP2950 and LP2951 are micropower voltage regulators that are specifically designed to maintain proper regulation with an extremely low input–to–output voltage differential. These devices feature a very low quiescent bias current of 75 µA and are capable of supplying output currents in excess of 100 mA. Internal current and thermal limiting protection is provided. The LP2951 has three additional features. The first is the Error Output that can be used to signal external circuitry of an out of regulation condition, or as a microprocessor power–on reset. The second feature allows the output voltage to be preset to 5.0 V, 3.3 V or 3.0 V output (depending on the version) or programmed from 1.25 V to 29 V. It consists of a pinned out resistor divider along with direct access to the Error Amplifier feedback input. The third feature is a Shutdown input that allows a logic level signal to turn–off or turn–on the regulator output. Due to the low input–to–output voltage differential and bias current specifications, these devices are ideally suited for battery powered computer, consumer, and industrial equipment where an extension of useful battery life is desirable. The LP2950 is available in the three pin case 29 and DPAK packages, and the LP2951 is available in the eight pin dual–in–line, SO–8 and Micro–8 surface mount packages. The ‘A’ suffix devices feature an initial output voltage tolerance ±0.5%. LP2950 and LP2951 Features:

• Low Quiescent Bias Current of 75 µA • Low Input–to–Output Voltage Differential of 50 mV at 100 µA and • • • •

380 mV at 100 mA 5.0 V, 3.3 V or 3.0 V ±0.5% Allows Use as a Regulator or Reference Extremely Tight Line and Load Regulation Requires Only a 1.0 µF Output Capacitor for Stability Internal Current and Thermal Limiting

http://onsemi.com

TO–92 Z SUFFIX CASE 29 1

2

Pin: 1. Output 2. Ground 3. Input

3


1 3

PIN CONNECTIONS

1

2

Pin: 1. Input 2. Ground 3. Output

3

(Top View) Heatsink surface (shown as terminal 4 in case outline drawing) is connected to Pin 2. SO–8 D SUFFIX CASE 751

8 1

PDIP–8 N SUFFIX CASE 626

8 1

Micro–8 DM SUFFIX CASE 846A

LP2951 Additional Features:

• Error Output Signals an Out of Regulation Condition • Output Programmable from 1.25 V to 29 V • Logic Level Shutdown Input

8 1

PIN CONNECTIONS

(See Following Page for Device Information.)

Output 1

8

Input

Sense 2

7

Feedback

Shutdown 3

6

VO Tap

Gnd 4

5

Error Output

(Top View)

ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on pages 354 and 355 of this data sheet.



342

Publication Order Number: LP2950/D

LP2950, LP2951 DEVICE INFORMATION Output Voltage Package

3.0V

3.3V

5.0V

Adjustable


TO–92 Suffix Z

LP2950CZ–3.0 LP2950ACZ–3.0

LP2950CZ–3.3 LP2950ACZ–3.3

LP2950CZ–5.0 LP2950ACZ–5.0

Not Available

TJ = –40° to +125°C

DPAK Suffix DT

LP2950CDT–3.0 LP2950ACDT–3.0

LP2950CDT–3.3 LP2950ACDT–3.3

LP2950CDT–5.0 LP2950ACDT–5.0

Not Available

TJ = –40° to +125°C

SO–8 Suffix D

LP2951CD–3.0 LP2951ACD–3.0

LP2951CD–3.3 LP2951ACD–3.3

LP2951CD LP2951ACD

LP2951CD LP2951ACD

TJ = –40° to +125°C

Micro–8 Suffix DM

LP2951CDM–3.0 LP2951ACDM–3.0

LP2951CDM–3.3 LP2951ACDM–3.3

LP2951CDM LP2951ACDM

LP2951CDM LP2951ACDM

TJ = –40° to +125°C

DIP–8 Suffix N

LP2951CN–3.0 LP2951ACN–3.0

LP2951CN–3.3 LP2951ACN–3.3

LP2951CN LP2951ACN

LP2951CN LP2951ACN

TJ = –40° to +125°C

LP2950Cx–xx / LP2951Cxx–xx LP2950ACx–xx / LP2951ACxx–xx

1% Output Voltage Precision at TJ = 25°C 0.5% Output Voltage Precision at TJ = 25°C

'

%

-

I! D >2

LP2951CD or CN


Figure 1. Representative Block Diagrams


LP2950, LP2951 MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating

Symbol

Value

Unit

VCC

30

Vdc

PD

Internally Limited

W

RθJA RθJC

180 45

°C/W °C/W

RθJA RθJC

92 6.0

°C/W °C/W

RθJA RθJC

160 83

°C/W °C/W

RθJA

105

°C/W

RθJA

240

°C/W

Vfb

–1.5 to +30

Vdc

Shutdown Input Voltage

Vsd

–0.3 to +30

Vdc

Error Comparator Output Voltage

Verr

–0.3 to +30

Vdc


TJ

–40 to +125

°C


Tstg

–65 to +150

°C

Input Voltage

Power Dissipation and Thermal Characteristics Maximum Power Dissipation Case 751(SO–8) D Suffix Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case Case 369A (DPAK) DT Suffix (Note 1) Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case Case 29 (TO–226AA/TO–92) Z Suffix Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case Case 626 N Suffix Thermal Resistance, Junction–to–Ambient Case 846A (Micro–8) DM Suffix Thermal Resistance, Junction–to–Ambient

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Feedback Input Voltage

ELECTRICAL CHARACTERISTICS (Vin = VO + 1.0 V, IO = 100 µA, CO = 1.0 µF, TJ = 25°C [Note 3], unless otherwise noted.) Characteristic

Symbol

Output Voltage, 5.0 V Versions Vin = 6.0 V, IO = 100 µA, TJ = 25°C LP2950C–5.0/LP2951C LP2950AC–5.0/LP2951AC TJ = –40 to +125°C LP2950C–5.0/LP2951C LP2950AC–5.0/LP2951AC Vin = 6.0 to 30 V, IO = 100 µA to 100 mA, TJ = –40 to +125°C LP2950C–5.0/LP2951C LP2950AC–5.0/LP2951AC

VO

Output Voltage, 3.3 V Versions Vin = 4.3 V, IO = 100 µA, TJ = 25°C LP2950C–3.3/LP2951C–3.3 LP2950AC–3.3/LP2951AC–3.3 TJ = –40 to +125°C LP2950C–3.3/LP2951C–3.3 LP2950AC–3.3/LP2951AC–3.3 Vin = 4.3 to 30 V, IO = 100 µA to 100 mA, TJ = –40 to +125°C LP2950C–3.3/LP2951C–3.3 LP2950AC–3.3/LP2951AC–3.3

VO

Min

Typ

344

Unit V

4.950 4.975

5.000 5.000

5.050 5.025

4.900 4.940

– –

5.100 5.060

4.880 4.925

– –

5.120 5.075 V

3.267 3.284

3.300 3.300

3.333 3.317

3.234 3.260

– –

3.366 3.340

3.221 3.254

– –

3.379 3.346

Output Voltage, 3.0 V Versions VO Vin = 4.0 V, IO = 100 µA, TJ = 25°C LP2950C–3.0/LP2951C–3.0 2.970 3.000 LP2950AC–3.0/LP2951AC–3.0 2.985 3.000 TJ = –40 to +125°C LP2950C–3.0/LP2951C–3.0 2.940 – LP2950AC–3.0/LP2951AC–3.0 2.964 – Vin = 4.0 to 30 V, IO = 100 µA to 100 mA, TJ = –40 to +125°C LP2950C–3.0/LP2951C–3.0 2.928 – LP2950AC–3.0/LP2951AC–3.0 2.958 – 1. The Junction–to–Ambient Thermal Resistance is determined by PC board copper area per Figure 27. 2. ESD data available upon request. 3. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 4. VO(nom) is the part number voltage option. 5. Noise tests on the LP2951 are made with a 0.01 µF capacitor connected across Pins 7 and 1.

http://onsemi.com

Max

V 3.030 3.015 3.060 3.036 3.072 3.042

LP2950, LP2951 ELECTRICAL CHARACTERISTICS (continued) (Vin = VO + 1.0 V, IO = 100 µA, CO = 1.0 µF, TJ = 25°C [Note 8], unless otherwise noted.) Characteristic

Symbol

Min

Typ

Max

– –

0.08 0.04

0.20 0.10

– –

0.13 0.05

0.20 0.10

– –

30 350

80 450

– –

93 4.0

120 12

µA mA

ICCdropout

–

110

170

µA

ILimit

–

220

300

mA

Regthermal

–

0.05

0.20

%/W

– –

126 56

– –

1.210 1.220

1.235 1.235

1.260 1.250

1.200 1.200

– –

1.270 1.260

Line Regulation (Vin = VO(nom) +1.0 V to 30 V) (Note 9) LP2950C–XX/LP2951C/LP2951C–XX LP2950AC–XX/LP2951AC/LP2951AC–XX

Regline

Load Regulation (IO = 100 µA to 100 mA) LP2950C–XX/LP2951C/LP2951C–XX LP2950AC–XX/LP2951AC/LP2951AC–XX

Regload

Dropout Voltage IO = 100 µA IO = 100 mA

VI – VO

Supply Bias Current IO = 100 µA IO = 100 mA

%

%

mV

ICC

Dropout Supply Bias Current (Vin = VO(nom) – 0.5 V, IO = 100 µA) (Note 9) Current Limit (VO Shorted to Ground) Thermal Regulation Output Noise Voltage (10 Hz to 100 kHz) (Note 10) CL = 1.0 µF CL = 100 µF

Unit

µVrms

Vn

LP2951A/LP2951AC ONLY Reference Voltage (TJ = 25°C) LP2951C/LP2951C–XX LP2951AC/LP2951AC–XX

Vref

Reference Voltage (TJ = –40 to +125°C) LP2951C/LP2951C–XX LP2951AC/LP2951AC–XX

Vref

Reference Voltage (TJ = –40 to +125°C) IO = 100 µA to 100 mA, Vin = 23 to 30 V LP2951C/LP2951C–XX LP2951AC/LP2951AC–XX

Vref

Feedback Pin Bias Current

V

V

V 1.185 1.190

– –

1.285 1.270

IFB

–

15

40

nA

ERROR COMPARATOR Output Leakage Current (VOH = 30 V)

Ilkg

–

0.01

1.0

µA

Output Low Voltage (Vin = 4.5 V, IOL = 400 µA)

VOL

–

150

250

mV

Upper Threshold Voltage (Vin = 6.0 V)

Vthu

40

45

–

mV

Lower Threshold Voltage (Vin = 6.0 V)

Vthl

–

60

95

mV

Hysteresis (Vin = 6.0 V)

Vhy

–

15

–

mV

0 2.0

– –

0.7 30

– –

35 450

50 600

–

3.0

10

SHUTDOWN INPUT Input Logic Voltage Logic “0” (Regulator “On”) Logic “1” (Regulator “Off”)

Vshtdn

Shutdown Pin Input Current Vshtdn = 2.4 V Vshtdn = 30 V

Ishtdn

Regulator Output Current in Shutdown Mode (Vin = 30 V, Vshtdn = 2.0 V, VO = 0, Pin 6 Connected to Pin 7)

Ioff

V

µA

6. The Junction–to–Ambient Thermal Resistance is determined by PC board copper area per Figure 27. 7. ESD data available upon request. 8. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 9. VO(nom) is the part number voltage option. 10. Noise tests on the LP2951 are made with a 0.01 µF capacitor connected across Pins 7 and 1.


µA

LP2950, LP2951 DEFINITIONS Output Noise Voltage – The rms ac voltage at the output, with constant load and no input ripple, measured over a specified frequency range. Leakage Current – Current drawn through a bipolar transistor collector–base junction, under a specified collector voltage, when the transistor is “off”. Upper Threshold Voltage – Voltage applied to the comparator input terminal, below the reference voltage which is applied to the other comparator input terminal, which causes the comparator output to change state from a logic “0” to “1”. Lower Threshold Voltage – Voltage applied to the comparator input terminal, below the reference voltage which is applied to the other comparator input terminal, which causes the comparator output to change state from a logic “1” to “0”. Hysteresis – The difference between Lower Threshold voltage and Upper Threshold voltage.

Dropout Voltage – The input/output voltage differential at which the regulator output no longer maintains regulation against further reductions in input voltage. Measured when the output drops 100 mV below its nominal value (which is measured at 1.0 V differential), dropout voltage is affected by junction temperature, load current and minimum input supply requirements. Line Regulation – The change in output voltage for a change in input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that average chip temperature is not significantly affected. Load Regulation – The change in output voltage for a change in load current at constant chip temperature. Maximum Power Dissipation – The maximum total device dissipation for which the regulator will operate within specifications. Bias Current – Current which is used to operate the regulator chip and is not delivered to the load.

6#

#

#

## #

#

#

-# 2 = # Ω

# # #

#

#

-#

#

#

'2B 2%"< D:@> 0"1

B '@(D> %2>"): 01

Figure 2. Quiescent Current

Figure 3. Dropout Characteristics

6#

BC%D>(D>C%2>"):C01

##

##

# " 2

# ## @ 2

# #

2 = # /

#

#

##

#

I'"FCD:@>C0CCC"1 µ

2( 9 >" = °

# BC%D>(D>C%2>"):C01

2( 9 #O2( 9 CI'"FCD:@>C0"1

#

#

#

#

#

99 97 98 96 2( 9 9

+ #

#

#

##

#

B '@(D> %2>"): 01

>"B "GI':@> >:G(:">D: 0°1

Figure 4. Input Current



##

>" = °

# ## # ##

# # #

#

#

##

#

#

#

## - #

#

'%B %D>(D> D:@> 0"1

BC'@(D>C%2>"):C01

'G: 0µ1

Figure 8. Error Comparator Output


8#

2 = # µ$ = # '2 = ## " 8 " >" = °

#

# #

# #

F '

#

##

>" = ° '2 = # " = 7# = #

##

##

2 = # µ$

-#

+6# 7##

##

2 = # µ$

6#

+# +##

#

8

9#

2%"C0"1

BC%D>(D>C%2>"):C01 F.D>" = °

-#

-# #

##


#

# 8#

# >B >:G(:">D: 0°1


#

-

2 = # /

-## + #

##

2 = #

%D>(D>C%2>"):C."@):C01

-##

#

#

# + ##

'2

#

+## #

##

##

-##

##

+ #

#

#

-

-

B >'G: 0µ1

B >'G: 01

Figure 10. LP2951 Enable Transient



%D>(D>C%2>"):C."@):C01

<%(%D>C%2>"):C01

- #

<%(%D>C%2>"):C01 2=C #

##

<%(%D>C%2>"):C01 2=C #C/

LP2950, LP2951

LP2950, LP2951 # %2>"):C@%'F:C0CCCOCCC.A1 µ √

6# '2= # "

#

#

# #

>" = ° 2 = # µ$ = 6# = # #

#C/

##

#C/

2 = # µ$

-#

#

2 = ## µ$

#

# ##

##C/

#C/

B $:HD:@K 0.A1

#C/

##C/

B $:HD:@K 0.A1

Figure 12. Ripple Rejection

Figure 13. Output Noise

7

#

## BC%D>(D>CD:@>C0"1

F.D>.:F.%2"):C01

'2= ## " >" = ° % = # 2( 9

6 % R%S

% R%S

# #7 +# + #

#

#

#

6#

7#

##

#

#

#

#

+ #

#

+#

2( 9 @ #

#

#

#

-#

B >:G(:">D: 0°1

B '@(D> %2>"): 01

Figure 14. Shutdown Threshold Voltage versus Temperature

Figure 15. Maximum Rated Output Current


#

>" = 8 °

6#

#

6#

>" = °

7#

-

+6# #

%D>(D>C%2>"):C."@):C01

'((2:C:E:>'%@C0I1

7#

LP2950, LP2951 APPLICATIONS INFORMATION Introduction

to the LP2951 is ramped up and down. The ERROR signal becomes valid (low) at about 1.3 V input. It goes high when the input reaches about 5.0 V (Vout exceeds about 4.75 V). Since the LP2951’s dropout voltage is dependent upon the load current (refer to the curve in the Typical Performance Characteristics), the input voltage trip point will vary with load current. The output voltage trip point does not vary with load. The error comparator output is an open collector which requires an external pull–up resistor. This resistor may be returned to the output or some other voltage within the system. The resistance value should be chosen to be consistent with the 400 µA sink capability of the error comparator. A value between 100 k and 1.0 MΩ is suggested. No pull–up resistance is required if this output is unused. When operated in the shutdown mode, the error comparator output will go high if it has been pulled up to an external supply. To avoid this invalid response, the error comparator output should be pulled up to Vout (see Figure 16).

The LP2950/LP2951 regulators are designed with internal current limiting and thermal shutdown making them user–friendly. Typical application circuits for the LP2950 and LP2951 are shown in Figures 18 through 26. These regulators are not internally compensated and thus require a 1.0 µF (or greater) capacitance between the LP2950/LP2951 output terminal and ground for stability. Most types of aluminum, tantalum or multilayer ceramic will perform adequately. Solid tantalums or appropriate multilayer ceramic capacitors are recommended for operation below 25°C. At lower values of output current, less output capacitance is required for output stability. The capacitor can be reduced to 0.33 µF for currents less than 10 mA, or 0.1 µF for currents below 1.0 mA. Using the 8–pin versions at voltages less than 5.0 V operates the error amplifier at lower values of gain, so that more output capacitance is needed for stability. For the worst case operating condition of a 100 mA load at 1.23 V output (Output Pin 1 connected to the feedback Pin 7) a minimum capacitance of 3.3 µF is recommended. The LP2950 will remain stable and in regulation when operated with no output load. When setting the output voltage of the LP2951 with external resistors, the resistance values should be chosen to draw a minimum of 1.0 µA. A bypass capacitor is recommended across the LP2950/LP2951 input to ground if more than 4 inches of wire connects the input to either a battery or power supply filter capacitor. Input capacitance at the LP2951 Feedback Pin 7 can create a pole, causing instability if high value external resistors are used to set the output voltage. Adding a 100 pF capacitor between the Output Pin 1 and the Feedback Pin 7 and increasing the output filter capacitor to at least 3.3 µF will stabilize the feedback loop.

# 8

%

:%

@

@

8 * '

8#

-

(+D :5 (+D

8# * -

Error Detection Comparator

The comparator switches to a positive logic low whenever the LP2951 output voltage falls more than approximately 5.0% out of regulation. This value is the comparator’s designed–in offset voltage of 60 mV divided by the 1.235 V internal reference. As shown in the representative block diagram. This trip level remains 5.0% below normal regardless of the value of regulated output voltage. For example, the error flag trip level is 4.75 V for a normal 5.0 V regulated output, or 9.50 V for a 10 V output voltage. Figure 2 is a timing diagram which shows the ERROR signal and the regulated output voltage as the input voltage

Figure 16. ERROR Output Timing Programming the Output Voltage (LP2951)

The LP2951CX may be pin–strapped for the nominal fixed output voltage using its internal voltage divider by tying Pin 1 (output) to Pin 2 (sense) and Pin 7 (feedback) to Pin 6 (5.0 V tap). Alternatively, it may be programmed for any output voltage between its 1.235 reference voltage and its 30 V maximum rating. An external pair of resistors is required, as shown in Figure 17.


LP2950, LP2951

## / : %

7

:

F@F

F '

-

F

)

$I

for reducing noise on the 3 lead LP2950. However, increasing the capacitor from 1.0 µF to 220 µF only decreases the noise from 430 µV to 160 µVrms for a 100 kHz bandwidth at the 5.0 V output. Noise can be reduced fourfold by a bypass capacitor across R1, since it reduces the high frequency gain from 4 to unity. Pick

- -#

@

6 @

## µ$

C -- µ$

Bypass

[

1 2R1 x 200 Hz

or about 0.01 µF. When doing this, the output capacitor must be increased to 3.3 µF to maintain stability. These changes reduce the output noise from 430 µV to 126 µVrms for a 100 kHz bandwidth at 5.0 V output. With bypass capacitor added, noise no longer scales with output voltage so that improvements are more dramatic at higher output voltages.

8

Figure 17. Adjustable Regulator D '

The complete equation for the output voltage is: V + V (1 ) R1ńR2) ) I R1 out

ref

# µ$

FB

where Vref is the nominal 1.235 V reference voltage and IFB is the feedback pin bias current, nominally –20 nA. The minimum recommended load current of 1.0 µA forces an upper limit of 1.2 MΩ on the value of R2, if the regulator must work with no load. IFB will produce a 2% typical error in Vout which may be eliminated at room temperature by adjusting R1. For better accuracy, choosing R2 = 100 k reduces this error to 0.17% while increasing the resistor program current to 12 µA. Since the LP2951 typically draws 75 µA at no load with Pin 2 open circuited, the extra 12 µA of current drawn is often a worthwhile tradeoff for eliminating the need to set output voltage in test.

: %

F '

MTB23P06E

# /

:

-

## µ$

7

# ±#3 # # "

F@F LP2951CN F< )

% > $I

8

6

# µ$

### µ$ # G

# /

Output Noise

In many applications it is desirable to reduce the noise present at the output. Reducing the regulator bandwidth by increasing the size of the output capacitor is the only method

Figure 18. 1.0 A Regulator with 1.2 V Dropout


LP2950, LP2951 TYPICAL APPLICATIONS * = # -# '2

7 @

:

@##

@ F@F # µ$ LP2951CN 6 @ F< % > )

$I

--# $

µ$

8

: %

±## # G #3 7#6 / #3

F '

'2 = -O

2

D ' 6# #

:

7

# µ$

F@F LP2951CN 6 F< % > )

2 ' &

$I

# /

8 # µ$

)

Figure 19. Lithium Ion Battery Cell Charger

Figure 20. Low Drift Current Sink

* * 8# / @-9#6

8# / @!

:

7

F@F LP2951CN -

F< )

G%F )

F '

% > $I

@

6 @

: %

# µ$

8

7

8 /

:

8# /

F@F LP2951CN F '

-

F< )

Error flag occurs when Vin is too low to maintain Vout, or if Vout is reduced by excessive load current.

@

6 @ % > $I

@-9#6

## / -- µ$ ## / ## $

8 ## /

Figure 21. Latch Off When Error Flag Occurs

Figure 22. 5.0 V Regulator with 2.5 V Sleep Function


LP2950, LP2951 *

@

:

7

F@F LP2951CN #1 6 F< % > )

$I

<

%N"'C0CCOJ1 °

θ E"BC>.:G"2C:F'F>"@:

## $ " G !

9# 7#

G FA (

8# 6#

# #

(" = #°

ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ

6

2

θE" #

#

#

#

#

# A 2

-#

#7 # #

2B 2:@)>. %$ %((: 01

Figure 27. DPAK Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length http://onsemi.com 353

('%@C0J1

MC34164P–5

6# 2+" I!

@-9#6

LP2950, LP2951 ORDERING INFORMATION (LP2950) Output Voltage (Volts)

Tolerance (%)

Package

Shipping

LP2950CZ–3.0

3.0

1.0

TO–92

2000 Units / Bag

LP2950ACZ–3.0

3.0

0.5

TO–92

2000 Units / Bag

LP2950CZ–3.3

3.3

1.0

TO–92

2000 Units / Bag

LP2950ACZ–3.3

3.3

0.5

TO–92

2000 Units / Bag

LP2950CZ–3.3RA

3.3

1.0

TO–92


LP2950ACZ–3.3RA

3.3

0.5

TO–92


LP2950CZ–5.0

5.0

1.0

TO–92

2000 Units / Bag

LP2950ACZ–5.0

5.0

0.5

TO–92

2000 Units / Bag

LP2950CZ–5.0RA

5.0

1.0

TO–92


LP2950CZ–5.0RP

5.0

1.0

TO–92

2000 Units / Ammo Pack

LP2950ACZ–5.0RA

5.0

0.5

TO–92


LP2950CDT–3.0

3.0

1.0

DPAK

75 Units / Rail

LP2950CDT–3.0RK

3.0

1.0

DPAK


LP2950ACDT–3.0

3.0

0.5

DPAK

75 Units / Rail

LP2950CDT–3.3

3.3

1.0

DPAK

75 Units / Rail

LP2950CDT–3.3RK

3.3

1.0

DPAK


LP2950ACDT–3.3

3.3

0.5

DPAK

75 Units / Rail

LP2950CDT–5.0

5.0

1.0

DPAK

75 Units / Rail

LP2950CDT–5.0RK

5.0

1.0

DPAK


LP2950ACDT–5.0

5.0

0.5

DPAK

75 Units / Rail

LP2950ACDT–5.0RK

5.0

0.5

DPAK


Part Number


LP2950, LP2951 ORDERING INFORMATION (LP2951) Output Voltage (Volts)

Tolerance (%)

Package

Shipping

LP2951CD–3.0

3.0 or Adj.

1.0

SO–8

98 Units / Rail

LP2951CD–3.0R2

3.0 or Adj.

1.0

SO–8


LP2951ACD–3.0

3.0 or Adj.

0.5

SO–8

98 Units / Rail

LP2951ACD–3.0R2

3.0 or Adj.

0.5

SO–8


LP2951CD–3.3

3.3 or Adj.

1.0

SO–8

98 Units / Rail

LP2951CD–3.3R2

3.3 or Adj.

1.0

SO–8


LP2951ACD–3.3

3.3 or Adj.

0.5

SO–8

98 Units / Rail

LP2951ACD–3.3R2

3.3 or Adj.

0.5

SO–8


LP2951CD

5.0 or Adj.

2.0

SO–8

98 Units / Rail

LP2951CDR2

5.0 or Adj.

2.0

SO–8


LP2951ACD

5.0 or Adj.

1.2

SO–8

98 Units / Rail

LP2951ACDR2

5.0 or Adj.

1.2

SO–8


LP2951CDM–3.0R2

3.0 or Adj.

1.0

Micro–8


LP2951ACDM–3.0R2

3.0 or Adj.

0.5

Micro–8


LP2951CDM–3.3R2

3.3 or Adj.

1.0

Micro–8


LP2951ACDM–3.3R2

3.3 or Adj.

0.5

Micro–8


LP2951CDMR2

5.0 or Adj.

2.0

Micro–8


LP2951ACDMR2

5.0 or Adj.

1.2

Micro–8


LP2951CN–3.0

3.0 or Adj.

1.0

DIP–8

50 Units / Rail

LP2951ACN–3.0

3.0 or Adj.

0.5

DIP–8

50 Units / Rail

LP2951CN–3.3

3.3 or Adj.

1.0

DIP–8

50 Units / Rail

LP2951ACN–3.3

3.3 or Adj.

0.5

DIP–8

50 Units / Rail

LP2951CN

5.0 or Adj.

2.0

DIP–8

50 Units / Rail

LP2951ACN

5.0 or Adj.

1.2

DIP–8

50 Units / Rail

Part Number


"#// % $ $$ % ) The CS8221 is a precision 5.0 V, 100 mA micropower voltage regulator with very low quiescent current (60 µA typical at 100 µA load). The 5.0 V output is accurate within ±2.0% and supplies 100 mA of load current with a maximum dropout voltage of only 600 mV. The regulator is protected against reverse battery, short circuit, overvoltage, and over temperature conditions. The device can withstand 74 V peak transients making it suitable for use in automotive environments. The CS8221 is pin for pin compatible with the LM2931. Features • Low Quiescent Current (60 µA @ 100 µA Load) • 5.0 V ±2.0% Output • 100 mA Output Current Capability • Internally Fused Leads in SO–8 Package • Fault Protection – +74 V Peak Transient Voltage – –15 V Reverse Voltage – Short Circuit – Thermal Shutdown

http://onsemi.com

SO–8 DF SUFFIX CASE 751

8 1

12

D2PAK 3–PIN DP SUFFIX CASE 418E 3

PIN CONNECTIONS AND MARKING INDIAGRAM

VOUT

SO–8

1

8221 ALYW

GND GND

8

NC

VIN GND GND NC

D2PAK

CS8221 AWLYWW

Tab = GND Pin 1. VIN 2. GND 3. VOUT

1 A WL, L YY, Y WW, W


ORDERING INFORMATION* Device

Package

CS8221YDF8

SO–8

95 Units/Rail

CS8221YDFR8

SO–8

2500 Tape & Reel

D2PAK, 3–PIN

50 Units/Rail

CS8221YDP3

Shipping

CS8221YDPR3 D2PAK, 3–PIN 750 Tape & Reel *Contact your local sales representative for TO–92 package option.



356

Publication Order Number: CS8221/D

CS8221

VOUT VIN Current Source (Circuit Bias)

Over Voltage Shutdown

Current Limit Sense

+

–

Error Amplifier

Thermal Protection GND Bandgap Reference

Figure 1. Block Diagram ABSOLUTE MAXIMUM RATINGS* Rating

Value

Unit

Junction Temperature Range, TJ

–40 to +150

°C

Storage Temperature Range, TSTORAGE

–55 to +150

°C

Internally Limited

–

–15, 74

V

–0.5 to 26

V

Internally Limited

–

2.0

kV

230 peak

°C

Power Dissipation Peak Transient Voltage (60 V Load Dump @ VIN = 14 V) Input Operating Range Output Current Electrostatic Discharge (Human Body Model) Lead Temperature Soldering:

Reflow (Note 1)

1. 60 seconds maximum above 183°. *The maximum package power dissipation must be observed.


CS8221 ELECTRICAL CHARACTERISTICS (6.0 ≤ VIN ≤ 26 V, IOUT = 1.0 mA, –40°C ≤ TJ ≤ 125°C unless otherwise noted.) Characteristic

Test Conditions

Min

Typ

Max

Unit

Output Voltage, VOUT

9.0 V < VIN < 26 V, 100 µA ≤ IOUT ≤ 100 mA 6.0 V ≤ VIN ≤ 26 V, 100 µA ≤ IOUT ≤ 100 mA

4.9 4.85

5.0 5.0

5.1 5.15

V V

Dropout Voltage (VIN – VOUT)

IOUT = 100 mA IOUT = 100 µA

– –

400 100

600 150

mV mV

Load Regulation

VIN = 14 V, 100 µA ≤ IOUT ≤ 100 mA,

–

5.0

50

mV

Line Regulation

6.0 V < V < 26 V, IOUT = 1.0 mA

–

5.0

50

mV

Quiescent Current, (IQ)

IOUT = 100 µA, VIN = 6.0 V IOUT = 50 mA IOUT = 100 mA

– – –

60 4.0 12

120 6.0 20

µA mA mA

Ripple Rejection

7.0 ≤ VIN ≤ 17 V, IOUT = 100 mA, f = 120 Hz

60

75

–

dB

–

125

200

–

mA

40

125

–

µA

150

180

–

°C

30

34

38

V

Output Stage

Current Limit Short Circuit Output Current

VOUT = 0 V

Thermal Shutdown (Note 2) Overvoltage Shutdown

– VOUT ≤ 1.0 V

2. This parameter is guaranteed by design, but not parametrically tested in production.

PACKAGE LEAD DESCRIPTION PACKAGE LEAD # SO–8

D2PAK

LEAD SYMBOL

1

3

VOUT

5.0 V, ±2.0%, 100 mA Output.

2, 3, 6, 7

2

GND

Ground.

4

–

NC

No Connection.

5

–

NC

No Connection.

8

1

VIN

Input Voltage.

FUNCTION


CS8221 CIRCUIT DESCRIPTION VOLTAGE REFERENCE AND OUTPUT CIRCUITRY

Should the junction temperature of the power device exceed 180°C (typ) the power transistor is turned off. Thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the IC.

Output Stage Protection

The output stage is protected against overvoltage, short circuit and thermal runaway conditions (Figure 2). > 30 V

VOUT

VIN C1 * 0.1 µF

VIN

CS8221

C2** 10 µF

VOUT GND IOUT

Load Dump

Short Circuit

*C1 is required if regulator is far from the power source filter.

Thermal Shutdown

**C2 is required for stability.

Figure 2. Typical Circuit Waveforms for Output Stage Protection

Figure 3. Application and Test Diagram

If the input voltage rises above 30 V, the output shuts down. This response protects the internal circuitry and enables the IC to survive unexpected voltage transients. APPLICATION NOTES STABILITY CONSIDERATIONS

Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Increase the temperature to your highest operating temperature. Vary the load current as instructed in step 5 to test for any oscillations.

The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 3 should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for COUT for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible.


CS8221 HEAT SINKS

Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ± 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above.

A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RΘJA. RJA + RJC ) RCS ) RSA

where: RΘJC = the junction–to–case thermal resistance, RΘCS = the case–to–heatsink thermal resistance, and RΘSA = the heatsink–to–ambient thermal resistance. RΘJC appears in the package section of the data sheet. Like RΘJA, it too is a function of package type. RΘCS and RΘSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.

CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR

The maximum power dissipation for a single output regulator (Figure 4) is: PD(max) + ǊVIN(max) * VOUT(min)ǋIOUT(max) ) VIN(max)IQ

(1)

where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated: RJA +

150°C * TA PD

(2)

The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IIN

IOUT

VIN

(3)

VOUT

CS8221

IQ

Figure 4. Single Output Regulator With Key Performance Parameters Labeled PACKAGE THERMAL DATA SO–8 Parameter

D2PAK, 3–PIN

Unit

RΘJC

Typical

25

4.2

°C/W

RΘJA

Typical

110

10–50*

°C/W

* Depending on thermal properties of substrate. RθJA = RθJC = RθCA


"2/$ % $ $$ % ) %* "- The CS9201 is a precision 5.0 V, 100 mA voltage regulator with low quiescent current (450 µA typ. @ 100 µA load). The 5.0 V output is accurate within ±2% and supplies 100 mA of load current with a maximum dropout voltage of only 600 mV. The regulator is protected against reverse battery, short circuit, over voltage, and over temperature conditions. The device can withstand 74 V peak transients making it suitable for use in automotive environments. ON’s proprietary NOCAP solution is the first technology which allows the output to be stable without the use of an external capacitor. NOCAP is suitable for slow switching or steady loads.

1

PIN CONNECTIONS AND MARKING DIAGRAM VOUT GND GND NC

A WL, L YY, Y WW, W

1

8

VIN GND GND NC


ORDERING INFORMATION Device VOUT

VIN


8

CS920 ALYW1

Features NOCAP Low Quiescent Current (450 µΑ typ. @ 100 µA load) 5.0 V, ±2% Output 100 mA Output Current Capability Fault Protection – 74 V Peak Transient Voltage – –15 V Reverse Voltage – Short Circuit – Thermal Shutdown – Overvoltage Shutdown • Internally Fused Leads

• • • • •

http://onsemi.com

Package

Shipping

CS9201YDF8

SO–8

95 Units/Rail

CS9201YDFR8

SO–8

2500 Tape & Reel

Over Voltage Shutdown Current Source (Circuit Bias) NOCAP

+

Current Limit Sense

Sense(1)

– Error Amplifier

Thermal Shutdown

Bandgap Reference

(1)

GND

Contact factory for optional Sense lead.

Figure 1. Block Diagram



361


CS9201 MAXIMUM RATINGS* Parameter

Value

Unit

Internally Limited

–

–15 to 36 74

V V

Internally Limited

–

ESD Susceptibility (Human Body Model)

4.0

kV

Package Thermal Resistance: Junction–to–Case, RθJC Junction–to–Ambient, RθJA

25 110

°C/W °C/W


–40 to +150

°C

Storage Temperature

–55 to +150

°C

230 Peak

°C

Power Dissipation Input Voltage (VIN): DC Peak Transient Voltage (60 V Load Dump @ VIN = 14 V) Output Current

Lead Temperature Soldering:

Reflow (SMD styles only) Note 1

1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed.

ELECTRICAL CHARACTERISTICS (6.0 V ≤ VIN ≤ 26 V, IOUT = 1.0 mA, –40°C ≤ TJ ≤ 125°C; unless otherwise stated.) Parameter

Test Conditions

Min

Typ

Max

Unit

4.90 4.85

5.00 5.00

5.10 5.15

V V

Output Stage Output Voltage, VOUT

9.0 V < VIN < 16 V, 100 uA ≤ IOUT ≤ 100 mA 6.0 V < VIN < 26 V, 100 uA ≤ IOUT ≤ 100 mA

Dropout Voltage (VIN–VOUT)


–

400 100

600 150

mV mV

Load Regulation

VIN = 14 V, 100 µA ≤ IOUT ≤ 100 mA

–

5

50

mV

Line Regulation

6.0 V < V < 26 V, IOUT = 1.0 mA

–

5

50

mV


IOUT = 100 µA, VIN = 12 V IOUT ≤ 50 mA IOUT ≤ 100 mA

–

450 4 12

750 6 20

µA mA mA

Ripple Rejection

7.0 V ≤ VIN ≤ 17 V, IOUT = 100 mA, f = 120 Hz

60

75

–

dB

–

105

200

–

mA

25

125

–

mA

150

180

–

°C

28

32

36

V


VOUT = 0 V


– VOUT ≤ 1.0 V


PACKAGE LEAD DESCRIPTION Package Lead Number SO–8

Lead Symbol

1

VOUT

4, 5

NC

2, 3, 6, 7

GND

8

VIN

Function 5.0 V, ± 2%, 100 mA output. No connection. Ground. Input voltage.


CS9201

20 18 16 14 12

5.04

Output Voltage (V)

10 8 6

125°C 25°C

100 mA

5.02

100 µA

20 mA

5.01 5.00 4.99 4.98 4.97

0

10

20

30

40

50

60

70

80

90

4.96 –40 –20

100

0

20

Output Current (mA)

100

120 140

1 125°C

Quiescent Current (mA)

12 10 8 6 4 2 0 –2 –4 –6 –8 –10 –12

40 60 80 Temperature (°C)

Figure 3. Output Voltage vs. Temperature VIN = 14 V

Figure 2. Load Regulation vs. Output Current VIN = 14 V

Line Regulation (mV)

–40°C 25°C

125°C

0.9 0.8 0.7 –40°C

0.6 0.5

25°C

0.4 0.3

6

8

10

12

14

16

18

20

22

24

0

26

1

2

3

4

5

6

7

8

9

10

Output Current (mA)

Input Voltage (V)

Figure 4. Line Regulation vs. Input Voltage IOUT = 100 µA

Figure 5. Quiescent Current vs. Output Current (Lightly Loaded) VIN = 14 V

14

0.70 25°C

12


4 2 0 –2

5.03

–40°C


Load Regulation (mV)

TYPICAL PERFORMANCE CHARACTERISTICS

10 8 125°C

6 4

–40°C

2

0.60

0

10

20

30

40

50

60

70

80

90

25°C

125°C

0.55 0.50 0.45 0.40 0.35 0.30

0

–40°C

0.65

100

4

6

8

10

12 14 16 18 20

22

24 26

Input Voltage (V)

Output Current (mA)

Figure 6. Quiescent Current vs. Output Current VIN = 14 V

Figure 7. Quiescent Current vs. Input Voltage IOUT = 100 µA


CS9201 CIRCUIT DESCRIPTION > 32 V

VOLTAGE REFERENCE AND OUTPUT CIRCUITRY

VIN

Output Stage Protection VOUT

The output stage is protected against overvoltage, short circuit and thermal runaway conditions (Figure 8). If the input voltage rises above 32 V (typ), the output shuts down. This response protects the internal circuitry and enables the IC to survive unexpected voltage transients. Should the junction temperature of the power device exceed 180°C (typ) the power transistor is turned off. Thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the IC.

IOUT

Load Dump

Thermal Shutdown


VOUT

VIN C1 * 0.1 µF

Short Circuit

CS9201

GND

* C1 is required if regulator is distant from power source filter.


APPLICATION NOTES STABILITY CONSIDERATIONS / NOCAP

NOCAP is an ON Semiconductor exclusive output stage which internally compensates the LDO regulator over temperature, load and line variations without the need for an expensive external capacitor NOCAP is ideally suited for slow switching or steady loads. If the load is characterized by transient current events, an output storage capacitor may be needed. If this is the case, the capacitor should be no larger than 100 nF. With loads that require greater transient suppression, a regulator with a traditional output stage (such as the CS8221) may be better suited for proper operation.

Normally a low dropout or quasi–low dropout regulator (or any type requiring a slow lateral PNP in the control loop) necessitates a large external compensation capacitor at the output of the IC. The external capacitor is also used to curtail overshoot, determine startup delay time and load transient response. Traditional LDO regulators typically have low unity gain bandwidth, display overshoot and poor ripple rejection. Compensation is also an issue and depends on the external capacitor value, ESR (Equivalent Series Resistance) and board layout parasitics that all can create oscillations if not properly accounted for.


CS9201 CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR

The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with RΘJA ’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.

The maximum power dissipation for a single output regulator (Figure 10) is: PD(max) + {VIN(max) * VOUT(min)} IOUT(max) ) VIN(max)IQ

(1)

HEAT SINKS

where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max).

A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RΘJA:

Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated: RJA + 150°C * TA PD

IIN

RJA + RJC ) RCS ) RSA

where: RΘJC = the junction–to–case thermal resistance, RΘCS = the case–to–heatsink thermal resistance, and RΘSA = the heatsink–to–ambient thermal resistance.

(2)

IOUT

VIN

CS9201

(3)

RΘJC appears in the package section of the data sheet. Like RΘJA, it too is a function of package type. RΘCS and RΘSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.

VOUT

IQ

Figure 10. Single output regulator with key performance parameters labeled.


"2/$/ % $$ % ) %* "- The CS9202 is a precision 3.3 V, 100 mA voltage regulator with low quiescent current (450 µA typ. @ 100 µA load). The 3.3 V output is accurate within ±2% and supplies 100 mA of load current. The regulator is protected against reverse battery, short circuit, over voltage, and over temperature conditions. The device can withstand 74 V peak transients making it suitable for use in automotive environments. ON’s proprietary NOCAP solution is the first technology which allows the output to be stable without the use of an external capacitor. NOCAP is suitable for slow switching or steady loads.

http://onsemi.com


8 1

PIN CONNECTIONS AND MARKING DIAGRAM VOUT GND GND NC

A WL, L YY, Y WW, W

1

8 CS920 ALYW2

Features • NOCAP • Low Quiescent Current (450 µΑ typ. @ 100 µA load) • 3.3 V, ±2% Output • 100 mA Output Current Capability • Fault Protection – 74 V Peak Transient Voltage – –15 V Reverse Voltage – Short Circuit – Thermal Shutdown – Overvoltage Shutdown • Internally Fused Leads

VIN GND GND NC


ORDERING INFORMATION Device VOUT

VIN

Package

Shipping

CS9202YDF8

SO–8

95 Units/Rail

CS9202YDFR8

SO–8

2500 Tape & Reel

Over Voltage Shutdown Current Source (Circuit Bias) NOCAP

+

Current Limit Sense

Sense(1)

– Error Amplifier

Thermal Shutdown

Bandgap Reference

(1)

GND

Contact factory for optional Sense lead.




366


CS9202 MAXIMUM RATINGS* Parameter

Value

Unit

Internally Limited

–

–15 to 36 74

V V

Internally Limited

–


4.0

kV


25 110

°C/W °C/W


–40 to +150

°C

Storage Temperature

–55 to +150

°C

230 Peak

°C

Power Dissipation Input Voltage (VIN): DC Peak Transient Voltage (60 V Load Dump @ VIN = 14 V) Output Current




ELECTRICAL CHARACTERISTICS (4.5 V ≤ VIN ≤ 26 V, IOUT = 1.0 mA, –40°C ≤ TJ ≤ 125°C; unless otherwise stated.) Parameter

Test Conditions

Min

Typ

Max

Unit

3.234 3.201

3.300 3.300

3.366 3.399

V V


9.0 V < VIN < 16 V, 100 uA ≤ IOUT ≤ 100 mA 4.5 V < VIN < 26 V, 100 uA ≤ IOUT ≤ 100 mA

Load Regulation

VIN = 14 V, 100 µA ≤ IOUT ≤ 100 mA

–

5

50

mV

Line Regulation

4.5 V < V < 26 V, IOUT = 1.0 mA

–

5

50

mV


IOUT = 100 µA, VIN = 12 V IOUT ≤ 50 mA IOUT ≤ 100 mA

–

450 4 12

750 6 20

µA mA mA

Ripple Rejection

7.0 V ≤ VIN ≤ 17 V, IOUT = 100 mA, f = 120 Hz

60

75

–

dB

–

105

200

–

mA

25

125

–

mA

150

180

–

°C

28

32

36

V


VOUT = 0 V


– VOUT ≤ 1.0 V


PACKAGE LEAD DESCRIPTION Package Lead Number SO–8

Lead Symbol

1

VOUT

3.3 V, ± 2%, 100 mA output.

2, 3, 6, 7

GND

Ground.

4, 5

NC

No connection.

8

VIN

Input voltage.


Function

CS9202 TYPICAL PERFORMANCE CHARACTERISTICS 3.320

14

3.315

–40°C

10

Output Voltage (V)


12

8 6

125°C

4

25°C

2 0

100 mA

3.310 3.305 3.300 3.295

100 µA

20 mA

3.290 3.285 3.280 –40

–2 0

10

20

30

40

50

60

70

80

90

100

–20

0

20

8

100

120

140

0.9 Quiescent Current (mA)


80

1 125°C

6 4 2

–40°C

0

25°C

–2 –4

125°C

0.8 0.7 0.6

25°C

0.5 0.4

–6 –8 6

8

10

12

14

16

18

20

22

24

–40°C

0.3 0

26

1

2

3

4

5

6

7

8

9

10

Output Current (mA)

Input Voltage (V)

Figure 5. Quiescent Current vs. Output Current (Lightly Loaded) VIN = 14 V

Figure 4. Line Regulation vs. Input Voltage IOUT = 100 µA 0.70

12


10 Quiescent Current (mA)

60

Figure 3. Output Voltage vs. Temperature VIN = 14 V

Figure 2. Load Regulation vs. Output Current VIN = 14 V

125°C

8 6

25°C

4 –40°C

2 0

40

Temperature (°C)

Output Current (mA)

–40°C

0.60 0.55 125°C

0.50 0.45 0.40

25°C 0.35

0

10

20

30

40

50

60

70

80

0.30

90 100

4

6

8

10 12

14

16

18

20

22

Input Voltage (V)

Output Current (mA)

Figure 7. Quiescent Current vs. Input Voltage IOUT = 100 µA

Figure 6. Quiescent Current vs. Output Current VIN = 14 V


24 26

CS9202 CIRCUIT DESCRIPTION > 32 V

VOLTAGE REFERENCE AND OUTPUT CIRCUITRY

VIN

Output Stage Protection VOUT

The output stage is protected against overvoltage, short circuit and thermal runaway conditions (Figure 8). If the input voltage rises above 32 V (typ), the output shuts down. This response protects the internal circuitry and enables the IC to survive unexpected voltage transients. Should the junction temperature of the power device exceed 180°C (typ) the power transistor is turned off. Thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the IC.

IOUT

Load Dump

Thermal Shutdown


VOUT

VIN C1 * 0.1 µF

Short Circuit

CS9202

GND

* C1 is required if regulator is distant from power source filter.


APPLICATION NOTES STABILITY CONSIDERATIONS / NOCAP

NOCAP is an ON Semiconductor exclusive output stage which internally compensates the LDO regulator over temperature, load and line variations without the need for an expensive external capacitor NOCAP is ideally suited for slow switching or steady loads. If the load is characterized by transient current events, an output storage capacitor may be needed. If this is the case, the capacitor should be no larger than 100 nF. With loads that require greater transient suppression, a regulator with a traditional output stage (such as the CS8221) may be better suited for proper operation.

Normally a low dropout or quasi–low dropout regulator (or any type requiring a slow lateral PNP in the control loop) necessitates a large external compensation capacitor at the output of the IC. The external capacitor is also used to curtail offshoot, determine startup delay time and load transient response. Traditional LDO regulators typically have low unity gain bandwidth, display overshoot and poor ripple rejection. Compensation is also an issue and depends on the external capacitor value, ESR (Equivalent Series Resistance) and board layout parasitics that all can create oscillations if not properly accounted for.



The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with RΘJA ’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.

The maximum power dissipation for a single output regulator (Figure 10) is: PD(max) + {VIN(max) * VOUT(min)} IOUT(max) ) VIN(max)IQ

(1)

HEAT SINKS



Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated: RJA + 150°C * TA PD

IIN



(2)

IOUT

VIN

CS9202

(3)


VOUT

IQ

Figure 10. Single output regulator with key performance parameters labeled.


t

$$ $ % ) %* -%( The L4949 is a monolithic integrated 5.0 V voltage regulator with a very low dropout and additional functions such as power–on reset and input voltage sense. It is designed for supplying the micro–computer controlled systems especially in automotive applications. • Operating DC Supply Voltage Range 5.0 V to 28 V • Transient Supply Voltage Up to 40 V • Extremely Low Quiescent Current in Standby Mode • High Precision Standby Output Voltage 5.0 V ±1% • Output Current Capability Up to 100 mA • Very Low Dropout Voltage Less Than 0.4 V • Reset Circuit Sensing The Output Voltage • Programmable Reset Pulse Delay With External Capacitor • Voltage Sense Comparator • Thermal Shutdown and Short Circuit Protections

.2.2 MULTIFUNCTION VERY LOW DROPOUT VOLTAGE REGULATOR SILICON MONOLITHIC INTEGRATED CIRCUIT

8 1

N SUFFIX PLASTIC PACKAGE CASE 626

8 1

D SUFFIX PLASTIC PACKAGE CASE 751

Representative Block Diagram M F! 01

% 01 7

PIN CONNECTIONS >

( 6#

# µ"

F ' 0F1

* +

7

F

8

F

M

-

6

>

)

#

0> 1

F % 0F1

6

8

* +

-

F



ORDERING INFORMATION -

Device L4949N

)

L4949D

371

Operating Temperature Range TJ = –40° to +125°C

Package DIP–8 SO–8

Publication Order Number: L4949/D

L4949 ABSOLUTE MAXIMUM RATINGS (Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ Rating

Symbol

Value

Unit

VCC

28

V

VCC TR

40

V

Output Current

Iout

Internally Limited

–

Output Voltage

DC Operating Supply Voltage

Transient Supply Voltage (t < 1.0 s)

Vout

20

V

Sense Input Current

ISI

±1.0

mA

Sense Input Voltage

VSI

VCC

–

Output Voltages Reset Output Sense Output

VReset VSO

20 20

Output Currents Reset Output Sense Output

IReset ISO

5.0 5.0

Preregulator Output Voltage

VZ

7.0

V

Preregulator Output Current

IZ

5.0

mA

ESD Protection at any pin Human Body Model Machine Model

– –

2000 400

V

mA

V

Thermal Resistance, Junction–to–Air P Suffix, DIP–8 Plastic Package, Case 626 D Suffix, SO–8 Plastic Package, Case 751

°C/W

RθJA

100 200

Maximum Junction Temperature

TJ

150

°C


Tstg

–65 to +150

°C

NOTE:

ESD data available upon request.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ELECTRICAL CHARACTERISTICS (VCC = 14 V, –40°C < TJ < 125°C, unless otherwise specified.) Characteristic

Symbol

Min

Typ

Max

Unit

Output Voltage (TJ = 25°C, Iout = 1.0 mA)

Vout

4.95

5.0

5.05

V

Output Voltage (6.0 V < VCC < 28 V, 1.0 mA < Iout < 50 mA)

Vout

4.9

5.0

5.1

V

Output Voltage (VCC = 35 V, t < 1.0 s, 1.0 mA < Iout < 50 mA)

Vout

4.9

5.0

5.1

V

Dropout Voltage Iout = 10 mA Iout = 50 mA Iout = 100 mA

Vdrop

– – –

0.1 0.2 0.3

0.25 0.40 0.50

VIO

–

0.2

0.4

V

Line Regulation (6.0 V < VCC < 28 V, Iout = 1.0 mA)

Regline

–

1.0

20

mV

Load Regulation (1.0 mA < Iout < 100 mA)

Regload

–

8.0

30

mV

105 –

200 100

400 –

Input to Output Voltage Difference in Undervoltage Condition (VCC = 4.0 V, Iout = 35 mA)

V

Current Limit Vout = 4.5 V Vout = 0 V

ILim

Quiescent Current (Iout = 0.3 mA, TJ < 100°C)

IQSE

–

150

260

µA

IQ

–

–

5.0

mA

Quiescent Current (Iout = 100 mA)


mA

L4949 ELECTRICAL CHARACTERISTICS (continued) (VCC = 14 V, –40°C < TJ < 125°C, unless otherwise specified.) Characteristic

Symbol

Min

Typ

Max

Unit

VResth

–

Vout – 0.5

–

V

50 50

100 –

200 300

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RESET

Reset Threshold Voltage

Reset Threshold Hysteresis @ TJ = 25°C @ TJ = –40 to +125°C

VResth,hys

mV

Reset Pulse Delay (CT = 100 nF, tR ≥ 100 µs)

tResD

55

100

180

ms

Reset Reaction Time (CT = 100 nF)

tResR

–

5.0

30

µs

Reset Output Low Voltage (RReset = 10 kΩ to Vout, VCC ≥ 3.0 V)

VResL

–

–

0.4

V

Reset Output High Leakage Current (VReset = 5.0 V)

IResH

–

–

1.0

µA

Delay Comparator Threshold

VCTth

–

2.0

–

V

VCTth, hys

–

100

–

mV

VSOth

1.16

1.23

1.35

V

VSOth,hys

20

100

200

mV

Sense Output Low Voltage (VSI ≤ 1.16 V, VCC ≥ 3.0 V, RSO = 10 kΩ to Vout)

VSOL

–

–

0.4

V

Sense Output Leakage (VSO = 5.0 V, VSI ≥ 1.5 V)

ISOH

–

–

1.0

µA

ISI

–1.0

0.1

1.0

µA

VZ

–

6.3

–

V

Delay Comparator Threshold Hysteresis

SENSE

Sense Low Threshold (VSI Decreasing = 1.5 V to 1.0 V) Sense Threshold Hysteresis

Sense Input Current

PREREGULATOR

Preregulator Output Voltage (IZ = 10 µA)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION

Pin

Symbol

Description

1

VCC

Supply Voltage

2

Si

Input of Sense Comparator

3

VZ

Output of Preregulator

4

CT

Reset Delay Capacitor

5

Gnd

Ground

6

Reset

Output of Reset Comparator

7

SO

Output of Sense Comparator

8

Vout

Main Regulator Output

TYPICAL CHARACTERIZATION CURVES

#

6# = ' = # "

BC%D>(D>C%2>"):C01

BC%D>(D>C%2>"):C01

#

#

97

96 +#

+ #

#

#

#

6#

7#

##

#

>E = °

# #

2 = # / 2 = ## Ω

-# # # #

#

>EB ED@>'%@ >:G(:">D: 0°1

#

#

-#

#

#

6#

8#

7#

B FD((2K %2>"): 01

Figure 2. Output Voltage versus Supply Voltage

Figure 1. Output Voltage versus Junction Temperature http://onsemi.com 373

9#

#

L4949 TYPICAL CHARACTERIZATION CURVES (continued) ## >E = °

BC<%(%D>C%2>"):C01

BC<%(%D>C%2>"):C01

# ## # ##

# #

#

#

' = # "

# #

' = # " ##

# +#

##

#

' = ## "

#-#

+ #

#

'B %D>(D> D:@> 0"1


= >E = °

'HBCHD':F:@>CD:@>C0"1


6#

7#

##

#

-#

#

# #

#

#

#

# 2 = ## Ω

# #

#

##

>E = °

2 = # / #

#

#

'B %D>(D> D:@> 0"1

BC:F:>C>.:F.%2"):C01

>E = °

# # / % #

-# # # # #

-

6

8

#

-#

Figure 6. Quiescent Current versus Supply Voltage

6#

#

B FD((2K %2>"): 01

Figure 5. Quiescent Current versus Output Current

BC:F:>C%D>(D>C01

#


-#

#

#

>EB ED@>'%@ >:G(:">D: 0°1

7

9

#

8 66 6

D >

7

2 >

6 +#

+ #

#

#

#

6#

7#

##

>EB ED@>'%@ >:G(:">D: 0°1

B %D>(D> %2>"): 01

Figure 8. Reset Thresholds versus Junction Temperature

Figure 7. Reset Output versus Regulator Output Voltage


#

L4949 TYPICAL CHARACTERIZATION CURVES (continued)

#

>E = °

#

# / F % #

-#

F'BCF:@F:C'@(D>C%2>"):C01

F% BCF:@F:C%D>(D>C%2>"):C01

6#

# # # # #

-

-

-7 -6

D >

- - 7 6

2 >

+#

+ #

#

#

#

6#

7#

##

#

>EB ED@>'%@ >:G(:">D: 0°1

F'B F:@F: '@(D> %2>"): 01

Figure 9. Sense Output versus Sense Input Voltage

Figure 10. Sense Thresholds versus Junction Temperature

APPLICATION INFORMATION Supply Voltage Transient

less than 8.0 V supply transients of more than 0.4 V/µs can cause a reset signal perturbation. To improve the transient behavior for supply voltages less than 8.0 V a capacitor at Pin 3 can be used. A capacitor at Pin 3 (C3 ≤ 1.0 µF) reduces also the output noise.

High supply voltage transients can cause a reset output signal perturbation. For supply voltages greater than 8.0 V the circuit shows a high immunity of the reset output against supply transients of more than 100 V/µs. For supply voltages

M 01 &

-

%

7

>

( 6#

# µ"

6 # /Ω * +

#

F% # /Ω F

F

8

* + -

F

)

NOTES: 1. For stability: Cs ≥ 1.0 µF, CO ≥ 4.7 µF, ESR < 10 Ω at 10 kHz 2. Recommended for application: Cs = CO = 10 µF

Figure 11. Application Schematic


-

L4949 OPERATING DESCRIPTION

The L4949 is a monolithic integrated low dropout voltage regulator. Several outstanding features and auxiliary functions are implemented to meet the requirements of supplying microprocessor systems in automotive applications. Nevertheless, it is suitable also in other applications where the present functions are required. The modular approach of this device allows the use of other features and functions independently when required.

#

Voltage Regulator

The voltage regulator uses an isolated Collector Vertical PNP transistor as a regulating element. With this structure, very low dropout voltage at currents up to 100 mA is obtained. The dropout operation of the standby regulator is maintained down to 3.0 V input supply voltage. The output voltage is regulated up to the transient input supply voltage of 35 V. With this feature no functional interruption due to overvoltage pulses is generated. The typical curve showing the standby output voltage as a function of the input supply voltage is shown in Figure 13. The current consumption of the device (quiescent current) is less than 200 µA. To reduce the quiescent current peak in the undervoltage region and to improve the transient response in this region, the dropout voltage is controlled. The quiescent current as a function of the supply input voltage is shown in Figure 14.

#

#

#

-

Figure 13. Output Voltage versus Supply Voltage


-#

Short Circuit Protection:

The maximum output current is internally limited. In case of short circuit, the output current is foldback current limited as described in Figure 12.

>E = °

# 2 = ## Ω

# #

# #

2 = # /

#

#

#

-#

B FD((2K %2>"): 01

Figure 14. Quiescent Current versus Supply Voltage

#

01

Preregulator

To improve the transient immunity a preregulator stabilizes the internal supply voltage to 6.0 V. This internal voltage is present at Pin 3 (VZ). This voltage should not be used as an output because the output capability is very small (≤ 100 µA). This output may be used as an option when better transient behavior for supply voltages less than 8.0 V is required. In this case a capacitor (100 nF – 1.0 µF) must be connected between Pin 3 and Gnd. If this feature is not used Pin 3 must be left open.

#

#

#

##

##

' 0"1

Figure 12. Foldback Characteristic of Vout


L4949 Reset Circuit

Standby output voltage drops below the reset threshold only a bit longer than the reaction time results in a shorter reset delay time. The nominal reset delay time will be generated for standby output voltage drops longer than approximately 50 µs. The typical reset output waveforms are shown in Figure 16.

The block circuit diagram of the reset circuit is shown in Figure 15. The reset circuit supervises the output voltage. The reset threshold of 4.5 V is defined with the internal reference voltage and standby output divider. The reset pulse delay time tRD, is defined with the charge time of an external capacitor CT: t

RD

+

C x 2.0 V T 2.0 A

-#

%

- /

# > * # DW>

The reaction time of the reset circuit originates from the discharge time limitation of the reset capacitor CT and is proportional to the value of CT. The reaction time of the reset circuit increases the noise immunity.

#

30 V VIN

RESET Function

A RESET signal (low voltage) is generated as the IC powers up until VOUT is within 1.0 V of the regulated output voltage, or when VOUT drops out of regulation, and is lower than 1.1 V below the regulated output voltage. A hysteresis of 50 mV is included in the function to minimize oscillations. The RESET output is an open collector NPN transistor, controlled by a low voltage detection circuit. The circuit is functionally independent of the rest of the IC thereby guaranteeing that the RESET signal is valid for VOUT as low as 1.0 V.

VOUT

IOUT

Load Dump

Current Limit

Short Circuit


If the input voltage rises above 30 V (e.g. load dump), the output shuts down. This response protects the internal circuitry and enables the IC to survive unexpected voltage transients. Should the junction temperature of the power device exceed 180°C (typ) the load current capability is reduced thereby preventing thermal overload. This thermal management function is an effective means to prevent die overheating since the load current is the principle heat source in the IC.

CS8311

Figure 4. RC Network for RESET Delay

An external RC network on the lead (Figure 4) provides a sufficiently long delay for most microprocessor based applications. RC values can be chosen using the following formula:

For 11 V < VIN < 26 V

RTOTCRST +

VIN ENABLE

RESET

ƪ

–tDelay

lnǒV

VT*VOUT RST*VOUT

ƫ

Ǔ

where: RRST = RESET Delay resistor RIN = µP port impedance RTOT = RRST in parallel with RIN CRST = RESET Delay capacitor tDelay = desired delay time VRST = VSAT of RESET lead (0.7 V @ turn – ON) VT = RESET threshold.

VIN(H) VRH ON VRL OFF (1) (2)

to µP RESET Port CRST

The CS8311 contains two microprocessor compatible control functions: ENABLE and RESET (Figure 3).

VRPEAK

COUT

RRST

RESET

REGULATOR CONTROL FUNCTIONS

VOUT

5.0 V to µP and System Power

VOUT

VRPEAK

VRLO (1) = No Reset Delay Capacitor (2) = With Reset Delay Capacitor

Figure 3. Circuit Waveform


CS8311 APPLICATION NOTES 10 V, 100 mA VIN

VBAT

VOUT

To Load

0.1 µF

CS8311

500 kΩ

ENABLE

COUT

RRST

To µP

RESET GND CRST

To µP I/O

Q1 100 kΩ 500 kΩ

100 kΩ

SWITCH

Figure 5. Microprocessor Control of CS8311 Using External Switching Transistor Q1 STABILITY CONSIDERATIONS

The circuit depicted in Figure 5 lets the system control its power source, the CS8311 regulator. A SWITCH (potentially an I/O port on microprocessor) is used to drive the base of Q1. When Q1 is driven into saturation, the voltage on the ENABLE lead falls below its lower threshold. The regulator’s output is enabled. When the drive current is removed, the voltage on the ENABLE lead rises, the output is switched off and the IC moves into Sleep mode where it draws 50 µA (max). By coupling these two controls with the ENABLE lead, the system has added flexibility. Once the system is running, the state of the SWITCH is irrelevant as long as the I/O port continues to drive Q1. The microprocessor can turn off its own power by withdrawing drive current, once the SWITCH is open. This software control at the I/O port allows the microprocessor to finish key housekeeping functions before power is removed. The logic options are summarized in Table 1.

The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. VIN

Switch

ENABLE

Output

ON

Closed

LOW

ON

Open

LOW

ON

OFF

Closed

LOW

ON

Open

HIGH

OFF

CS8311

RRST

COUT** 10 µF

RESET ENABLE

*CIN required if regulator is located far from the power supply filter. *COUT required for stability. Capacitor must operate at minimum temperature expected.

Figure 6. Test and Application Circuit Showing Output Compensation

The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 6 should work for most applications, however it is not necessarily the optimized solution.

Table 1. Logic Control of CS8311 Output Microprocessor I/O Drive

VOUT

CIN* 0.1 µF

The I/O port of the microprocessor typically provides 50 µA to Q1. In automotive applications the SWITCH is connected to the ignition switch.


CS8311 To determine an acceptable value for COUT for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations.


(2)

The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IIN VIN

IOUT

SMART REGULATOR

VOUT

Control Features

IQ

Figure 7. Single Output Regulator With Key Performance Parameters Labeled

HEAT SINKS

A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RΘJA.



(3)




150°C * TA PD

(1)


CS8311

PACKAGE THERMAL DATA Parameter

SO–8

Unit

RΘJC

Typical

45

°C/W

RΘJA

Typical

165

°C/W


"#$ % $ $$ % ) %* 445 464 The CS8101 is a precision 5.0 V micropower voltage regulator with very low quiescent current (70 µA typ at 100 µA load). The 5.0 V output is accurate within ±2.0% and supplies 100 mA of load current with a typical dropout voltage of only 400 mV. Microprocessor control logic includes an ENABLE input and an active RESET. This combination of low quiescent current, outstanding regulator performance and control logic makes the CS8101 ideal for any battery operated, microprocessor controlled equipment. The active RESET circuit includes hysteresis, and operates correctly at an output voltage as low as 1.0 V. The RESET function is activated during the power up sequence or during normal operation if the output voltage drops outside the regulation limits by more than 200 mV typ. The logic level compatible ENABLE input allows the user to put the regulator into a shutdown mode where it draws only 20 µA typical of quiescent current. The regulator is protected against reverse battery, short circuit, over voltage, and thermal overload conditions. The device can withstand load dump transients making it suitable for use in automotive environments. The CS8101 is functionally equivalent to the National Semiconductor LP2951 series low current regulators. Features • 5.0 V ±2.0% Output • Low 70 µA Quiescent Current • Active RESET • ENABLE Input for ON/OFF and Active/Sleep Mode Control • 100 mA Output Current Capability • Fault Protection – +60 V Peak Transient Voltage – –15 V Reverse Voltage Short Circuit Thermal Overload • Low Reverse Current (Output to Input) • Internally Fused Leads Available in SO–20L Package

http://onsemi.com

TO–220 FIVE LEAD T SUFFIX CASE 314D 1

5 TO–220 FIVE LEAD TVA SUFFIX CASE 314K

1

TO–220 FIVE LEAD THA SUFFIX CASE 314A

1

5 SO–20L DWF SUFFIX CASE 751D

20 1

8 1

SO–8 D SUFFIX CASE 751




April, 2001 – Rev. 13

385


CS8101 PIN CONNECTIONS TO–220 5 LEAD Pin 1. VOUT 2. ENABLE 3. GND 4. RESET 5. VIN Tab = GND

VOUT

1

SO–8

VOUTSense ENABLE

8

ENABLE NC NC GND GND GND GND NC NC RESET

VIN NC NC

GND

RESET

1

1 SO–20L 20 VOUT VIN NC GND GND GND GND NC NC NC



Internally connected on 5 lead TO–220

ENABLE Current Limit Sense

+

–

Error Amplifier

VOUT Sense

Thermal Protection

Bandgap Reference

RESET + – Reset Comparator

GND



CS8101 ABSOLUTE MAXIMUM RATINGS* Rating

Value

Unit

Internally Limited

–

–15, 60

V

Internally Limited

–

2.0

kV

Operating Temperature

–40 to +125

°C

Junction Temperature Range

–40 to +150

°C


–55 to +150

°C

260 peak 230 peak

°C °C

Power Dissipation Peak Transient Voltage (46 V Load Dump @ VIN = 14 V) Output Current ESD Susceptibility (Human Body Model)


Wave Solder (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2)

1. 10 second maximum. 2. 60 second maximum above 183°C. *The maximum package power dissipation must be observed.

ELECTRICAL CHARACTERISTICS (6.0 V ≤ VIN ≤ 26 V; IOUT = 1.0 mA; –40 ≤ TA ≤ 125, –40°C ≤ TJ ≤ 150°C, unless otherwise noted.) Characteristic

Test Conditions

Min

Typ

Max

Unit


9.0 V < VIN < 16 V, 100 µA ≤ IOUT ≤ 100 mA 6.0 V < VIN < 26 V, 100 µA ≤ IOUT ≤ 100 mA

4.90 4.85

5.00 5.00

5.10 5.15

V V



– –

400 100

600 150

mV mV

Load Regulation

VIN = 14 V, 100 µA ≤ IOUT ≤ 100 mA

–

5.0

50

mV

Line Regulation

6.0 < V < 26 V, IOUT = 1.0 mA

–

5.0

50

mV

Quiescent Current, (IQ) Active Mode

IOUT = 100 µA, VIN = 6.0 V IOUT = 50 mA IOUT = 100 mA

– – –

70 4.0 12

140 6.0 20

µA mA mA

Quiescent Current, (IQ) Sleep Mode

VOUT = OFF, VIN = 6.0 V, VENABLE = 2.0 V

–

20

50

µA

Ripple Rejection

7.0 ≤ VIN ≤ 17 V, IOUT = 100 mA, f = 120 Hz

60

75

–

dB

–

105

200

–

mA

25

125

–

mA

150

180

–

°C

Output Stage


VOUT = 0 V

Thermal Shutdown

–

Overvoltage Shutdown

VOUT ≤ 1.0 V

30

34

38

V

Reverse Current

VOUT = 5.0 V, VIN = 0 V

–

100

200

µA

– 0.6

1.4 1.4

2.0 –

V V

–

30

100

µA

ENABLE Input (ENABLE) Threshold HIGH LOW

(VOUT OFF) (VOUT ON)

Input Current

VENABLE = 2.4 V


CS8101 ELECTRICAL CHARACTERISTICS (continued) (6.0 V ≤ VIN ≤ 26 V; IOUT = 1.0 mA; –40 ≤ TA ≤ 125, –40°C ≤ TJ ≤ 150°C, unless otherwise noted.) Characteristic

Test Conditions

Min

Typ

Max

Unit

4.525 4.500

4.75 4.70

VOUT – 0.05 VOUT – 0.075

V V

Reset Functions (RESET) RESET Threshold HIGH (VRH) LOW (VRL)

VOUT Increasing VOUT Decreasing

RESET Hysteresis

(HIGH – LOW)

25

50

100

mV

Reset Output Leakage RESET = HIGH

VOUT ≥ VRH

–

–

25

µA

1.0 V ≤ VOUT ≤ VRL, RRESET = 10 k VOUT, Power up, Power down, RRESET = 10 k

– –

0.1 0.6

0.4 1.0

V V

Output Voltage Low (VRLO) Low (VRPEAK)

PACKAGE LEAD DESCRIPTION PACKAGE LEAD # TO–220 5 LEAD

SO–20L

SO–8

LEAD SYMBOL

1

20

1

VOUT

–

–

2

VOUTSENSE

2

1

3

ENABLE

3

4, 5, 6, 7 14, 15, 16, 17

4

GND

4

10

5

RESET

–

2, 3, 8, 9, 11, 12, 13, 18

6,7

NC

No Connection.

5

19

8

VIN

Input voltage.

FUNCTION 5.0 V, ±2.0%, 100 mA output. Kelvin connection which allows remote sensing of output voltage for improved regulation. If remote sensing is not required, connect to VOUT. Logic level switches output off when toggled HIGH. Ground. All GND leads must be connected to Ground. Active reset (accurate to VOUT ≥ 1.0 V)


CS8101 TYPICAL PERFORMANCE CHARACTERISTICS 0.6 0.5 Dropout Voltage

125_C 0.4 25°C

0.3 –40°C

0.2 0.1 0 0

10

20

30

40

50

60

70

80

90

100

Load (mA)

Figure 2. CS8101 Dropout Voltage vs. Load Over Temperature

CIRCUIT DESCRIPTION VOLTAGE REFERENCE AND OUTPUT CIRCUITRY

For 7.0 V < VIN < 26 V


The output stage is protected against overvoltage, short circuit and thermal runaway conditions (Figure 3).

VIN ENABLE VIN(H)

> 30 V

VRH VIN

VOUT

VOUT

VRL (1) VRPEAK

(2)

VRPEAK

VRLO

RESET IOUT

(1) = No Reset Delay Capacitor (2) = With Reset Delay Capacitor Load Dump

Current Limit

Short Circuit

Figure 4. Circuit Waveform


ENABLE Function

The ENABLE function switches the output transistor ON and OFF. When the voltage on the ENABLE lead exceeds 1.4 V typ, the output pass transistor turns off, leaving a high impedance facing the load. The IC will remain in Sleep mode, drawing only 50 µA, until the voltage on this input drops below the ENABLE threshold.

If the input voltage rises above 30 V (e.g. load dump), the output shuts down. This response protects the internal circuitry and enables the IC to survive unexpected voltage transients. Should the junction temperature of the power device exceed 180°C (typ) the load current capability is reduced thereby preventing thermal overload. This thermal management function is an effective means to prevent die overheating since the load current is the principle heat source in the IC.

RESET Function

A RESET signal (low voltage) is generated as the IC powers up until VOUT is within 250 mV of the regulated output voltage, or when VOUT drops out of regulation, and is lower than 300 mV below the regulated output voltage. A hysteresis of 50 mV is included in the function to minimize oscillations.


The CS8101 contains two microprocessor compatible control functions: ENABLE and RESET (Figure 4).


CS8101 The RESET output is an open collector NPN transistor, controlled by a low voltage detection circuit. The circuit is functionally independent of the rest of the IC thereby guaranteeing that the RESET signal is valid for VOUT as low as 1.0 V.

VT = RESET threshold. The circuit depicted in Figure 6 lets the microprocessor control its power source, the CS8101 regulator. An I/O port on the µP and the SWITCH port are used to drive the base of Q1. When Q1 is driven into saturation, the voltage on the ENABLE lead falls below its lower threshold. The regulator’s output is enabled. When the drive current is removed, the voltage on the ENABLE lead rises, the output is switched off and the IC moves into Sleep mode where it draws 50 µA (max). By coupling these two controls with the ENABLE lead, the system has added flexibility. Once the system is running, the state of the SWITCH is irrelevant as long as the I/O port continues to drive Q1. The microprocessor can turn off its own power by withdrawing drive current, once the SWITCH is open. This software control at the I/O port allows the microprocessor to finish key housekeeping functions before power is removed. The logic options are summarized in Table 1.

5.0 V to µP and System Power

VOUT COUT

RRST

CS8101

to µP RESET Port

RESET CRST

Figure 5. RC Network for RESET Delay

An external RC network on the lead (Figure 5) provides a sufficiently long delay for most microprocessor based applications. RC values can be chosen using the following formula: RTOTCRST +

ƪ

–tDelay

lnǒV

VT*VOUT RST*VOUT

Table 1. Logic Control of CS8101 Output

ƫ

Ǔ

where: RRST = RESET Delay resistor RIN = µP port impedance RTOT = RRST in parallel with RIN CRST = RESET Delay capacitor tDelay = desired delay time VRST = VSAT of RESET lead (0.7 V @ turn – ON)

Microprocessor I/O Drive

Switch

ENABLE

Output

ON

Closed

LOW

ON

Open

LOW

ON

OFF

Closed

LOW

ON

Open

HIGH

OFF


APPLICATION NOTES

VIN

VBAT

VOUT

VCC

0.1 µF

CS8101

500 kΩ

ENABLE

GND

COUT

RRST

RESET

µP

RESET CRST

Q1 100 kΩ 500 kΩ

100 kΩ

SWITCH

Figure 6. Microprocessor Control of CS8101 Using External Switching Transistor Q1


I/O Port

CS8101 STABILITY CONSIDERATIONS

the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations.

The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. VIN

VOUT

CIN* 0.1 µF

CS8101

RRST

COUT** 10 µF

RESET ENABLE

*CIN required if regulator is located far from the power supply filter. *COUT required for stability. Capacitor must operate at minimum temperature expected.



The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 7 should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for COUT for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause



(1)


150°C * TA PD

(2)

The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C.


CS8101 HEAT SINKS

In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IIN VIN


IOUT VOUT

SMART REGULATOR


Control Features

(3)

where: RΘJC = the junction–to–case thermal resistance, RΘCS = the case–to–heatsink thermal resistance, and RΘSA = the heatsink–to–ambient thermal resistance. RΘJC appears in the package section of the data sheet. Like RΘJA, it is a function of package type. RΘCS and RΘSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.

IQ



CS8101 ORDERING INFORMATION† Device CS8101YD8 CS8101YDR8

Description

Shipping

SO–8

95 Units/Rail

SO–8

2500 Tape & Reel

CS8101YDWF20

SO–20L

37 Units/Rail

CS8101YDWFR20

SO–20L

1000 Tape & Reel

CS8101YT5

TO–220 FIVE LEAD STRAIGHT

50 Units/Rail

CS8101YTVA5

TO–220 FIVE LEAD VERTICAL

50 Units/Rail

CS8101YTHA5

TO–220 FIVE LEAD HORIZONTAL

50 Units/Rail

†Contact your local sales representative for D2PAK package option.

MARKING DIAGRAMS TO–220 FIVE LEAD TVA SUFFIX CASE 314K

TO–220 FIVE LEAD T SUFFIX CASE 314D


SO–20L DWF SUFFIX CASE 751D


20

8101 ALYW

CS8101 AWLYYWW CS8101 AWLYWW

CS8101 AWLYWW

CS8101 AWLYWW

1

1


1

1



TO–220 FIVE LEAD

SO–8

SO–20L

Unit

RΘJC

Typical

3.3

45

9.0

°C/W

RΘJA

Typical

50

165

55

°C/W


"# $ $$ % ) %* 7 * 445 7 8 ' The CS8151 is a precision 5.0 V, 100 mA micro–power voltage regulator with very low quiescent current (400 µA typical at 200 µA load). The 5.0 V output is accurate within ±2% and supplies 100 mA of load current with a typical dropout voltage of 400 mV. Microprocessor control logic includes Watchdog, Wake Up and RESET. This unique combination of low quiescent current and full microprocessor control makes the CS8151 ideal for use in battery operated, microprocessor controlled equipment. The CS8151 Wake Up function brings the microprocessor out of Sleep mode. The microprocessor in turn, signals its Wake Up status back to the CS8151 by issuing a Watchdog signal. The Watchdog logic function monitors an input signal (WDI) from the microprocessor. The CS8151 responds to the falling edge of the Watchdog signal which it expects at least once during each wake–up period. When the correct Watchdog signal is received, a falling edge is issued on the wake–up signal line. RESET is independent of VIN and operates correctly to an output voltage as low as 1.0 V. A RESET signal is issued in any of three situations. During power up the RESET is held low until the output voltage is in regulation. During operation if the output voltage shifts below the regulation limits, the RESET toggles low and remains low until proper output voltage regulation is restored. And finally, a RESET signal is issued if the regulator does not receive a Watchdog signal within the Wake Up period. The RESET pulse width, Wake Up signal frequency, and Wake Up delay time are all set by one external capacitor CDelay. The regulator is protected against short circuit, over voltage, and thermal runaway conditions. The device can withstand 74 volt peak transients, making it suitable for use in automotive environments. Features • 5.0 V ± 2%/100 mA Output Voltage • Micropower Compatible Control Functions – Wake Up – Watchdog – RESET • Low Dropout Voltage: 400 mV @ 100 mA • Low Sleep Mode Quiescent Current (400 µA Typ) • Protection Features – Thermal Shutdown – Short Circuit – 74 V Peak Transient Capability – Reverse Transient (–50 V) • Internally Fused Leads in DIP–16 and SO–16L Packages  Semiconductor Components Industries, LLC, 2002


http://onsemi.com TO–220 SEVEN LEAD T SUFFIX CASE 821E

1 7

TO–220 SEVEN LEAD TVA SUFFIX CASE 821J

1

D2PAK 7–PIN DPS SUFFIX CASE 936H

1 7

DIP–16 NF SUFFIX CASE 648

16 1

SO–16L DWF SUFFIX CASE 751G

16 1


Package

Shipping

CS8151YT7

TO–220* STRAIGHT

50 Units/Rail

CS8151YTVA7

TO–220* VERTICAL

50 Units/Rail

CS8151YDPS7

D2PAK*

50 Units/Rail

CS8151YDPSR7

D2PAK*

750 Tape & Reel

CS8151YNF16

DIP–16

25 Units/Rail

CS8151YDWF16

SO–16L

46 Units/Rail

CS8151YDWFR16

SO–16L

1000 Tape & Reel

*7 Lead/Pin.


394


CS8151 PIN CONNECTIONS TO–220 SEVEN LEAD

DIP–16 1

Tab = GND Pin 1. VOUT 2. VIN 3. WDI 4. GND 5. Wake Up 6. RESET 7. Delay

1 D2PAK 7–PIN

SO–16L 16

1

NC

Delay

NC

NC NC

RESET Wake Up

NC NC

16 Delay RESET Wake Up

GND GND

GND GND

GND GND

GND GND

NC Sense

WDI NC

GND Sense

WDI NC

VOUT

VIN

VOUT

VIN

1


Delay


VOUT Current Limit Sense

Timing Circuit

Wake Up Circuit

+ –

Watchdog Circuit

WDI

Internally connected on TO–220 and D2PAK

Wake Up

Sense

Error Amplifier

Thermal Shutdown

Falling Edge Detector Bandgap Reference

VOUT

RESET RESET Circuit

GND



CS8151 MAXIMUM RATINGS* Rating

Value

Unit

Power Dissipation

Internally Limited

–

Output Current (VOUT, RESET, Wake Up)

Internally Limited

–

Reverse Battery

–15

V

Peak Transient Voltage (60 V Load Dump @ VIN = 14 V)

+74

V

Maximum Negative Transient (t < 2.0 ms)

–50

V


2.0

kV

ESD Susceptibility (Machine Model)

200

V

Logic Inputs/Outputs

–0.3 to +6.0

V


–55 to +150

°C

260 peak 230 peak

°C °C

Lead Temperature Soldering

Wave Solder (through hole styles only) Note 1 Reflow (SMD styles only) Note 2

1. 10 seconds max. 2. 60 seconds max above 183°C *The maximum package power dissipation must be observed.

ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ 125°C, –40°C ≤ TJ ≤ 150°C, 6.0 V ≤ VIN ≤ 26 V, 100 µA ≤ IOUT ≤ 100 mA, C2 = 47 µF (ESR < 8.0 Ω), CDelay = 0.1 µF; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit


9.0 V < VIN < 16 V 6.0 V < VIN < 26 V, 0 < IOUT < 100 mA

4.90 4.85

5.0 5.0

5.10 5.15

V V



– –

400 100

600 150

mV mV

Load Regulation

VIN = 14 V, 100 µA < IOUT < 100 mA

–

10

50

mV

Line Regulation

IOUT = 1.0 mA, 6.0 V < VIN < 26 V

–

10

50

mV

Ripple Rejection

7.0 V < VIN < 17 V @ f = 120 Hz, IOUT = 100 mA

60

75

–

dB

Current Limit

VOUT = 4.5 V

100

250

–

mA

150

180

210

°C

Output Section

Thermal Shutdown

–


VOUT < 1.0 V

50

56

62

V

Quiescent Current

IOUT = 200 µA (Sleep) IOUT = 50 mA IOUT = 100 mA (Wake Up)

– – –

0.4 4.0 12

0.75 – 20

mA mA mA

Reverse Current

VOUT = 5.0 V, VIN = 0 V

–

1.0

1.5

mA

RESET Threshold High (RTH)

RTH VOUT Increasing

VOUT – 0.3

–

VOUT – 0.04

V

Threshold Low (RTL)

RTL VOUT Decreasing

4.5

4.7

4.91

V

Hysteresis

RTH – RTL

150

200

250

mV

Output Low

1.0 V < VOUT RTL, IOUT = 25 µA

–

0.2

0.8

V

Output High

IOUT = 25 µA, VOUT > RTH

3.8

4.2

5.1

V

Current Limit

RESET = 0 V, VOUT > VRTH (Sourcing) RESET = 5.0 V, VOUT > 1.0 V (Sinking)

0.025 0.1

0.5 12

1.30 80

mA mA

Delay Time

POR Mode

3.0

5.0

7.0

ms


CS8151 ELECTRICAL CHARACTERISTICS (continued) (–40°C ≤ TA ≤ 125°C, –40°C ≤ TJ ≤ 150°C, 6.0 V ≤ VIN ≤ 26 V, 100 µA ≤ IOUT ≤ 100 mA, C2 = 47 µF (ESR < 8.0 Ω), CDelay = 0.1 µF; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

Threshold High

–

–

1.4

2.0

V

Threshold Low

–

0.8

1.3

–

V

Hysteresis

–

25

100

–

mV

Watchdog Input

Input Current

0 < WDI < 6.0 V

–10

0

+10

µA

Pulse Width

50% WDI Falling Edge to 50% WDI Rising Edge and 50% WDI Rising Edge to 50% WDI Falling Edge (see Figures 2, 3, and 4)

5.0

–

–

µs

Wake Up Period

See Figure 2.

30

40

50

ms

Wake Up Duty Cycle Nominal

See Figure 4.

40

50

60

%

RESET High to Wake Up Rising Delay Time

50% RESET Rising Edge to 50% Wake Up Edge (see Figures 2, 3, and 4 )

15

20

25

ms

Wake Up Response to Watchdog Input

50% WDI Falling Edge to 50% Wake Up Falling Edge

–

2.0

10

µs

Wake Up Response to RESET

50% RESET Falling Edge to 50% Wake Up Falling Edge, VOUT = 5.0 V → 4.5 V

–

2.0

10

µs

Output Low

IOUT = 25 µA (Sinking)

–

0.2

0.8

V

Output High

IOUT = 25 µA (Sourcing)

3.8

4.2

5.1

V

Current Limit

Wake Up = 5.0 V Wake Up = 0 V

0.025 0.5

1.0 –

7.0 3.5

mA mA

Wake Up Output

PACKAGE PIN DESCRIPTION PACKAGE PIN # TO–220 &

D2PAK

DIP–16

SO–16L

PIN SYMBOL

1

8

8

VOUT

2

9

9

VIN

Supply voltage to the IC.

3

11

11

WDI

CMOS/TTL compatible input lead. The Watchdog function monitors the falling edge of the incoming signal.

4

4, 5, 12, 13

4, 5, 6, 12, 13*

GND

Ground connection.

5

14

14

Wake Up

6

15

15

RESET

7

16

16

Delay

Input lead from timing capacitor for RESET and Wake Up signal.

–

7

7

Sense

Kelvin connection which allows remote sensing of the output voltage for improved regulation. If remote sensing is not required, connect to VOUT.

FUNCTION Regulated output voltage 5.0 V ± 2%.

CMOS/TTL compatible output consisting of a continuously generated signal used to Wake Up the microprocessor from sleep mode. CMOS/TTL compatible output lead RESET goes low whenever VOUT drops by more than 6.0% from nominal, or during the absence of a correct watchdog signal.

*Pin 6 GND is not directly shorted to the fused paddle GND. The fused paddle GND (pins 4, 5, 12, 13) is connected through the substrate. Pin 6 must be electrically connected to at least one of the fused paddle GND’s on the PC board.


CS8151 TIMING DIAGRAMS VIN

RESET

Wake Up Duty Cycle = 50%

Wake Up

WDI

VOUT POR RESET High to Wake Up Delay Time Power Up

Sleep Mode

Normal Operation with Varying Watchdog Signal

Figure 2. Power Up, Sleep Mode and Normal Operation

VIN

RESET Delay Time

RESET Wake Up WDI

VOUT POR RESET High to Wake Up Delay Time

Wake Up Period

RESET High to Wake Up Delay Time

Figure 3. Error Condition: Watchdog Remains Low and a RESET Is Issued

RESET

Wake Up Period

Wake Up

WDI RTL VOUT

Watchdog Pulse Width

Power Down POR

POR Watchdog Pulse Width

Figure 4. Power Down and Restart Sequence


CS8151 DEFINITION OF TERMS techniques such that the average chip temperature is not significantly affected. Load Regulation: The change in output voltage for a change in load current at constant chip temperature. Quiescent Current: The part of the positive input current that does not contribute to the positive load current. The regulator ground lead current. Ripple Rejection: The ratio of the peak–to–peak input ripple voltage to the peak–to–peak output ripple voltage. Current Limit: Peak current that can be delivered to the output.

Dropout Voltage: The input–output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100mV from the nominal value obtained at 14V input, dropout voltage is dependent upon load current and junction temperature. Input Voltage: The DC voltage applied to the input terminals with respect to ground. Line Regulation: The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse

CIRCUIT DESCRIPTION Functional Description

The first falling edge of the watchdog signal causes the Wake Up to go low within 2.0 µs (typ) and remain low until the next Wake Up cycle (see Figure 5). Other watchdog pulses received within the same cycle are ignored (Figures 2, 3, and 4). During power up, RESET is held low until the output voltage is in regulation. During operation, if the output voltage shifts below the regulation limits, the RESET toggles low and remains low until proper output voltage regulation is restored. After the RESET delay, RESET returns high. The Watchdog circuitry continuously monitors the input watchdog signal (WDI) from the microprocessor. The absence of a falling edge on the Watchdog input during one Wake Up cycle will cause a RESET pulse to occur at the end of the Wake Up cycle (see Figure 3). The Wake Up output is pulled low during a RESET regardless of the cause of the RESET. After the RESET returns high, the Wake Up cycle begins again (see Figure 3). The RESET pulse width, Wake Up signal frequency and RESET high to Wake Up delay time are all set by one external capacitor CDelay. Wake Up Period = (4 × 105)CDelay RESET Delay Time = (5 × 104)CDelay RESET High to Wake Up Delay Time = (2 × 105)CDelay Capacitor temperature coefficient and tolerance as well as the tolerance of the CS8151 must be taken into account in order to get the correct system tolerance for each parameter.

To reduce the drain on the battery a system can go into a low current consumption mode when ever its not performing a main routine. The Wake Up signal is generated continuously and is used to interrupt a microcontroller that is in sleep mode. The nominal output is a 5.0 volt square wave with a duty cycle of 50% at a frequency that is determined by a timing capacitor, CDelay. When the microprocessor receives a rising edge from the Wake Up output, it must issue a watchdog pulse and check its inputs to decide if it should resume normal operations or remain in the sleep mode.

Wake Up WDI

Wake Up Response to WDI

Figure 5. Wake Up Response to WDI RESET

Wake Up


Figure 6. Wake Up Response to RESET (Low Voltage)


CS8151 APPLICATION NOTES Output Stage Protection

ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provide this information. The value for the output capacitor C2 shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for C2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ±20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low

The output stage is protected against overvoltage, short circuit and thermal runaway conditions (see Figure 7). If the input voltage rises above the overvoltage shutdown threshold (e.g. load dump), the output shuts down. This response protects the internal circuitry and enables the IC to survive unexpected voltage transients. Should the junction temperature of the power device exceed 180°C (typ) the power transistor is turned off. Thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the IC. > 50 V VIN VOUT

IOUT

Load Dump

Short Circuit

Thermal Shutdown

Figure 7. Typical Circuit Waveforms for Output Stage Protection Stability Considerations

The output or compensation capacitor C2 (see Figure 8) helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. VIN VOUT C1* 0.1 µF

CS8151

RRST

C2** 10 µF

RESET

*C1 required if regulator is located far from the power supply filter. **C2 required for stability.


The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or


CS8151 temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above.

In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air.

Calculating Power Dissipation In a Single Output Linear Regulator

The maximum power dissipation for a single output regulator (Figure 9) is: PD(max) + (VIN(max) * VOUT(min))IOUT(max) ) VIN(max)IQ

Heat Sinks

(1)

Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RΘJA:

where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated: RJA + 150°C * TA PD


where: RΘJC = the junction–to–case thermal resistance, RΘCS = the case–to–heatsink thermal resistance, and RΘSA = the heatsink–to–ambient thermal resistance. RΘJC appears in the package section of the data sheet. Like RΘJA, it too is a function of package type. RΘCS and RΘSA are functions of the package type, heatsink and the interface between them. These values appear in heatsink data sheets of heatsink manufacturers.

(2)

The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. IIN VIN

IOUT SMART REGULATOR

VOUT

} Control Features IQ

Figure 9. Single Output Regulator with Key Performance Parameters Labeled

Battery VIN

VOUT

C1

VCC C2 Microprocessor

CS8151 WDI

CDelay

RESET

I/O

RESET

CDelay GND

(3)

Wake Up I/O

Figure 10. Application Diagram


CS8151 MARKING DIAGRAMS TO–220 SEVEN LEAD T SUFFIX CASE 821E



16

16 CS8151 AWLYYWW

CS8151 AWLYWW CS8151 AWLYWW

CS8151 AWLYWW

CS8151 AWLYYWW

1 1

1 1

SO–16L DWF SUFFIX CASE 751G

DIP–16 NF SUFFIX CASE 648




TO–220 7 LEAD

D2PAK 7–Pin

DIP–16

SO–16L

Unit

RΘJC

Typical

1.8

1.8

15

18

°C/W

RΘJA

Typical

50

10–50*

50

75

°C/W

*Depending on thermal properties of substrate. RΘJA = RΘJC + RΘCA.


t

"!#,"$$

% The MC78FC00 series voltage regulators are specifically designed for use as a power source for video instruments, handheld communication equipment, and battery powered equipment. The MC78FC00 series voltage regulator ICs feature a high accuracy output voltage and ultra–low quiescent current. Each device contains a voltage reference unit, an error amplifier, a driver transistor, and resistors for setting output voltage, and a current limit circuit. These devices are available in SOT–89 surface mount packages, and allow construction of an efficient, constant voltage power supply circuit.

MICROPOWER ULTRA–LOW QUIESCENT CURRENT VOLTAGE REGULATORS SEMICONDUCTOR TECHNICAL DATA

MC78FC00 Series Features:

• • • • • • • •

TAB

Ultra–Low Quiescent Current of 1.1 µA Typical Ultra–Low Dropout Voltage (100 mV at 10 mA) Large Output Current (up to 120 mA) Excellent Line Regulation (0.1%) Wide Operating Voltage Range (2.0 V to 10 V) High Accuracy Output Voltage (±2.5%) Wide Output Voltage Range (2.0 V to 6.0 V) Surface Mount Package (SOT–89)

1

H SUFFIX PLASTIC PACKAGE CASE 1213 (SOT–89)

PIN CONNECTIONS

ORDERING INFORMATION Device MC78FC30HT1 MC78FC33HT1 MC78FC40HT1 MC78FC50HT1

Output Voltage


Package

3.0 3.3 4.0 5.0

TA = –30° to +80°C

SOT–89

'

%

-

>& 0>& ( 1 0> 1

Other voltages from 2.0 to 6.0 V, in 0.1 V increments, are available upon request. Consult factory for information.

Standard Application '

Representative Block Diagram

)

-

%

MC78FCXX -

%

%

)

This device contains 11 active transistors.  Semiconductor Components Industries, LLC, 2001

April, 2001 – Rev. 2

403

Publication Order Number: MC78FC00/D

MC78FC00 Series MAXIMUM RATINGS (TC = 25°C, unless otherwise noted.)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ Rating

Symbol

Value

Unit

Input Voltage

VCC

10

Vdc

Power Dissipation and Thermal Characteristics Maximum Power Dissipation Case 1213 (SOT–89) H Suffix Thermal Resistance, Junction–to–Ambient

PD RθJA

300 333

mW °C/W


TJ

125

°C


TA

–30 to +80

°C


Tstg

–40 to +125

°C

NOTE:

ESD data available upon request.

ELECTRICAL CHARACTERISTICS (Vin = VO + 1.0 V, IO = 10 mA, TJ = 25°C [Note 1], unless otherwise noted.)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Characteristic

Symbol

Output Voltage 30HT1 Suffix (Vin = 5.0 V) 33HT1 Suffix (Vin = 6.0 V) 40HT1 Suffix (Vin = 7.0 V) 50HT1 Suffix (Vin = 8.0 V)

Min

Typ

Max

2.925 3.218 3.900 4.875

3.0 3.3 4.0 5.0

3.075 3.382 4.100 5.125

VO

Unit V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Line Regulation Vin = [VO + 1.0] V to 10 V, IO = 10 mA

Regline

–

0.1

–

mV

Load Regulation Vin = [VO + 1.0], IO = 1.0 to 10 mA

Regload

–

40

80

mV

50 65 65 80

80 100 100 120

– – – –

–

0.5

0.7

– – – –

1.1 1.1 1.2 1.3

3.3 3.3 3.6 3.9

–

±100

–

Output Current 30HT1 Suffix (Vin = 5.0 V) 33HT1 Suffix (Vin = 6.0 V) 40HT1 Suffix (Vin = 7.0 V) 50HT1 Suffix (Vin = 8.0 V)

IO

Dropout Voltage IO = 40 mA

Vin – VO

Quiescent Current 30HT1 Suffix (Vin = 5.0 V) 33HT1 Suffix (Vin = 5.0 V) 40HT1 Suffix (Vin = 6.0 V) 50HT1 Suffix (Vin = 7.0 V)

ICC


TC

mA

V

µA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ NOTE:

ppm/°C

1. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

DEFINITIONS such that average chip temperature is not significantly affected. Load Regulation – The change in output voltage for a change in load current at constant chip temperature. Maximum Power Dissipation – The maximum total device dissipation for which the regulator will operate within specifications. Quiescent Bias Current – Current which is used to operate the regulator chip and is not delivered to the load.

Dropout Voltage – The input/output voltage differential at which the regulator output no longer maintains regulation against further reductions in input voltage. Measured when the output drops 100 mV below its nominal value (which is measured at 1.0 V differential), dropout voltage is affected by junction temperature, load current and minimum input supply requirements. Line Regulation – The change in output voltage for a change in input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques


MC78FC00 Series #7

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MC78FC00 Series APPLICATIONS INFORMATION Introduction

The MC78FC00 micropower voltage regulators are specifically designed with internal current limiting and low quiescent current making them ideal for battery powered applications. An input bypass capacitor is recommended if the regulator is located an appreciable distance (≥ 4 inches) from the input voltage source. These regulators require 0.1 µF capacitance between the output terminal and ground for stability. Most types of aluminum, tantalum or multilayer ceramic will perform adequately. Solid tantalums or other appropriate capacitors are recommended for operation below 25°C. The bypass capacitors should be mounted with the shortest possible leads or track lengths directly across the regulator input and output terminals. With economical electrolytic capacitors, cold temperature operation can pose a serious stability problem. As the electrolyte freezes, around –30°C, the capacitance will decrease and the equivalent series resistance (ESR) will increase drastically, causing the circuit to oscillate. Quality electrolytic capacitors with extended temperature ranges of –40° to +85°C are readily available. Solid tantalum capacitors may be the better choice if small size is a requirement. However, a maximum ESR limit of 3.0 Ω must be observed over temperature to maintain stability. Figure 6 is a typical circuit application. Figure 7 is a current boost circuit which can deliver more than 600 mA. The circuit has no current limiting and the external transistor must be rated for the expected power dissipation.

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406

%

##

"# / % $ $ % ) The CS8321 is a precision 5.0 V micropower voltage regulator with very low quiescent current (140 µA typ at 1.0 mA load). The 5.0 V output is accurate within ±2% and supplies 150 mA of load current with a typical dropout voltage of only 300 mV. This combination of low quiescent current and outstanding regulator performance makes the CS8321 ideal for any battery operated equipment. The regulator is protected against reverse battery and short circuit conditions. The device can withstand 45 V load dump transients making it suitable for use in automotive environments.

http://onsemi.com

TO–220 THREE LEAD T SUFFIX CASE 221A 1

Features • 5.0 V ± 2% Output • Low 140 µA (typ) Quiescent Current • 150 mA Output Current Capability • Fault Protection – –15 V Reverse Voltage Output Current Limit • Low Reverse Current (Output to Input)

12

2

Pin 1. VIN 2. GND 3. VOUT

3 D2PAK 3–PIN DP SUFFIX CASE 418E

3

MARKING DIAGRAMS VOUT

D2PAK

TO–220

VIN Current Source (Circuit Bias)

CS8321 AWLYWW

QP R CS8321 AWLYWW

QN

1 Current Limit Sense

1 VOUTSENSE*

A WL, L YY, Y WW, W

+ – Error Amplifier


R1

Bandgap Reference


R2 GND

*Lead Shorted to VOUT in 3–Pin Applications


Package

Shipping

CS8321YT3

TO–220 THREE LEAD

50 Units/Rail

CS8321YDP3

D2PAK, 3–PIN

50 Units/Rail

CS8321YDPR3

D2PAK, 3–PIN

750 Tape & Reel

*Contact your local sales representative for SO–16, DIP–16, SO–8, and DIP–8 package options.


February, 2002 – Rev. 4

407



Value

Unit

–15, 45

V

Internally Limited

–

2.0

kV


–40 to 150

°C

Storage Temperature

–65 to 150

°C

260 peak 230 peak

°C °C

Transient Input Voltage Output Current ESD Susceptibility (Human Body Model)




ELECTRICAL CHARACTERISTICS (6.0 V < VIN < 26 V, IOUT = 1.0 mA, –40°C ≤ TA ≤ 125°C, –40°C ≤ TJ ≤ 150°C; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

4.9

5.0

5.1

V


9.0 V < VIN 16 V, 100 mA ≤ IOUT ≤ 150 mA


IOUT = 150 mA, –40°C ≤ TA ≤ 85°C IOUT = 150 mA, TA = 125°C

– –

0.3 –

0.5 0.6

V V


IOUT = 1.0 mA @ VIN = 13 V IOUT < 50 mA @ VIN = 13 V IOUT < 150 mA @ VIN = 13 V

– – –

– 4.0 15

200 6.0 25

µA mA mA

Load Regulation

VIN = 14 V, 100 µA < IOUT < 150 mA

–

5.0

50

mV

Line Regulation

6.0 V ≤ V ≤ 26 V, IOUT = 1.0 mA

–

5.0

50

mV

Ripple Rejection

7.0 ≤ VIN ≤ 17 V, IOUT = 150 mA, f = 120 Hz

60

75

–

dB

175

250

–

mA

Current Limit

–

Short Circuit Output Current

VOUT = 0 V

60

200

–

mA

Reverse Current

VOUT = 5.0 V, VIN = 0 V

–

140

200

µA

PACKAGE PIN DESCRIPTION PACKAGE PIN # TO–220

D2PAK

PIN SYMBOL

1

1

VIN

2

2

GND

Ground. All GND leads must be connected to ground.

3

3

VOUT

5.0 V, ±2%, 150 mA Output.

FUNCTION Input voltage.


CS8321 CIRCUIT DESCRIPTION AND APPLICATION NOTES VOLTAGE REFERENCE AND OUTPUT CIRCUITRY

0.34257

The CS8321 is a series pass voltage regulator. It consists of an error amplifier, bandgap voltage reference, PNP pass transistor with antisaturation control, and current limit. As the voltage at the input, VIN, is increased (Figure 1), QN is forward biased via R. QN provides base drive for QP. As QP becomes forward biased, the output voltage, VOUT, begins to rise as QP’s output current charges the output capacitor. Once VOUT rises to a certain level, the error amplifier becomes biased and provides the appropriate amount of base current to QP. The error amplifier monitors the scaled output voltage via an internal voltage divider, R1 and R2, and compares it to the bandgap voltage reference. The error amplifier’s output is a current which is equal to the error amplifier’s differential input voltage times its transconductance. Therefore, the error amplifier varies the base drive current to QN, which provides bias to QP, based on the difference between the reference voltage and the scaled output voltage, VOUT.

0.30831 0.27405

Load Current

0.23980

0.17128 0.13703 0.10277 0.06851 0.03426

Curve will vary with temperature and process variation.

0.0 0.0 0.51 1.02 1.52 2.03 2.54 3.05 3.56 4.06 4.57 5.08

Output Voltage

Figure 3. Typical Current Limit and Fold Back Waveform

The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 4 should work for most applications, however it is not necessarily the best solution.

Antisaturation Protection

An antisaturation control circuit has also been added to prevent the pass transistor from going into deep saturation, which would cause excessive power dissipation due to large bias currents lost to the substrate via a parasitic PNP transistor, as shown in Figure 2. VIN QP

QParasitic

0.20554

VIN VOUT

VOUT CIN* 0.1 µF

Substrate

CS8321

COUT** 0.1 µF

VOUTSense†

Figure 2. The Parasitic PNP Transistor Which Is Part of the Pass Transistor (QP) Structure

Current Limit Limit

The output stage is protected against short circuit conditions. As shown in Figure 3, the output current will fold back when the faulted load is continually increased. This technique has been incorporated to limit the total power dissipation across the device during a short circuit condition, since the device does not contain overtemperature shutdown.

*CIN required if regulator is located far from the power supply filter. **COUT required for stability. Capacitor must operate at minimum temperature expected. †Pin internally shorted to VOUT in 3–pin applications.


STABILITY CONSIDERATIONS

To determine an acceptable value for COUT for a particular application, start with a tantalum capacitor of the

The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability.


CS8321 recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ±20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above.

VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated: RJA + 150°C * TA PD

The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IIN

VIN

IOUT

VOUT

CS8321

IQ


HEATSINKS

A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RΘJA: RJA + RJC ) RCS ) RSA

(3)

where: RΘJC = the junction–to–case thermal resistance, RΘCS = the case–to–heatsink thermal resistance, and RΘSA = the heatsink–to–ambient thermal resistance. RΘJC appears in the package section of the data sheet. Like RΘJA, it too is a function of package type. RΘCS and RΘSA are functions of the package type, heatsink and the interface between them. These values appear in heatsink data sheets of heatsink manufacturers.


The maximum power dissipation for a single output regulator (Figure 5) is: PD(max) + (VIN(max) * VOUT(min))IOUT(max) ) VIN(max)IQ

(2)

(1)

where:


CS8321 PACKAGE THERMAL DATA Parameter

TO–220

D2PAK

Unit

RΘJC

Typical

3.5

1.0*

°C/W

RΘJA

Typical

50

10–50†

°C/W

*Depending on die area. †Depending on thermal properties of substrate. RΘJA = RΘJC + RΘCA.


"

/&

' % $ % ) %* +,, " http://onsemi.com

6 1

PIN CONNECTIONS AND MARKING DIAGRAMS SOT–23L ON/OFF 1 GND 2 BYPASS 3

Features:

(OFF, no load)

• • • • • • • • • •

Current of 100 mA Very Low Noise with External Bypass Capacitor (10 nF), Typically 25 µVrms over 100 Hz to 100 kHz Internal Thermal Shutdown Extremely Tight Line Regulation Typically –90 dB Ripple Rejection –70 dB @ 1.0 kHz Line Transient Response: 1.0 mV for Vin = 3.0 V Extremely Tight Load Regulation, Typically 20 mV at Iout = 150 mA Multiple Output Voltages Available Logic Level ON/OFF Control (TTL–CMOS Compatible) ESR can vary from 0 to 3.0 Functionally and Pin Compatible with TK112xxA/B Series

6 VIN 5 GND 4 VOUT

(Top View)

• Very Low Quiescent Current 170 µA (ON, no load), 100 nA • Very Low Dropout Voltage, Typical Value is 137 mV at an Output

SOT–23L NW SUFFIX CASE 318J

xAYLW

Housed in a SOT23–L package, the MC33263 delivers up to 150 mA where it exhibits a typical 180 mV dropout. With an incredible noise level of 25 VRMS (over 100 Hz to 100 kHz, with a 10 nF bypass capacitor), the MC33263 represents the ideal choice for sensitive circuits, especially in portable applications where noise performance and space are premium. The MC33263 also excels in response time and reacts in less than 25 s when receiving an OFF to ON signal (with no bypass capacitor). Thanks to a novel concept, the MC33263 accepts output capacitors without any restrictions regarding their Equivalent Series Resistance (ESR) thus offering an obvious versatility for immediate implementation. With a typical DC ripple rejection better than –90 dB (–70 dB @ 1.0 kHz), it naturally shields the downstream electronics against choppy power lines. Additionally, thermal shutdown and short–circuit protection provide the final product with a high degree of ruggedness.

x A L Y W

= Voltage Option Code = Assembly Location = Wafer Lot = Year = Work Week

ORDERING INFORMATION See detailed ordering and shipping information on page 423 of this data sheet.

Applications:

• All Portable Systems, Battery Powered Systems, Cellular Telephones, Radio Control Systems, Toys and Low Voltage Systems



412


MC33263 6 Input Shutdown

1

Thermal Shutdown

ON/OFF

3 Bypass

2

4

Band Gap Reference

Output

* Current Limit * Antisaturation * Protection

5

GND

GND

Figure 1. MC33263 Block Diagram

MAXIMUM RATINGS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Rating


Symbol

Pin #

Value

Unit

Vin

6

12

V

Power Dissipation and Thermal Resistance Maximum Power Dissipation Thermal Resistance, Junction–to–Air

PD RJA


W °C/W

Operating Ambient Temperature Maximum Junction Temperature

TA TJmax

–40 to +85 150

°C °C

Tstg

–60 to +150

°C


ELECTRICAL CHARACTERISTICS (For typical values TA = 25°C, for min/max values TA = –40°C to +85°C, Max TJ = 150°C) Characteristics

Symbol

Pin #

Min

Typ

Max

Unit

CONTROL ELECTRICAL CHARACTERISTICS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Voltage Range

VON/OFF

1

ON/OFF Input Current (All versions) VON/OFF = 2.4 V

ION/OFF

1

ON/OFF Input Voltages (All versions) Logic “0”, i.e. OFF State Logic “1”, i.e. ON State

VON/OFF

0

–

Vin

–

2.5

–

– 2.2

– –

0.3 –

–

0.1

2.0

–

170

200

–

900

1400

175

210

–

V

A

1

V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CURRENTS PARAMETERS

Current Consumption in OFF State (All versions) OFF Mode Current: Vin = Vout + 1.0 V, Iout = 0 mA

IQOFF

Current Consumption in ON State (All versions) ON Mode Sat Current: Vin = Vout + 1.0 V, Iout = 0 mA

IQON

Current Consumption in Saturation ON State (All versions) ON Mode Sat Current: Vin = Vout – 0.5 V, Iout = 0 mA

IQSAT

Current Limit Vin = Vout + 1.0 V, (All versions) Output Short–circuited (Note 1)

IMAX

A A A

mA

1. Iout (Output Current) is the measured current when the output voltage drops below 0.3 V with respect to Vout at Iout = 30 mA.


MC33263 ELECTRICAL CHARACTERISTICS (For typical values TA = 25°C, for min/max values TA = –40°C to +85°C, Max TJ = 150°C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Characteristics

Symbol

Pin #

Vin = Vout + 1.0 V, TA = 25°C, 1.0 mA < Iout < 150 mA 2.8 Suffix 3.0 Suffix 3.2 Suffix 3.3 Suffix 3.8 Suffix 4.0 Suffix 4.75 Suffix 5.0 Suffix

Vout

4

Vin = Vout + 1.0 V, –40°C < TA < 80°C, 1.0 mA < Iout < 150 mA 2.8 Suffix 3.0 Suffix 3.2 Suffix 3.3 Suffix 3.8 Suffix 4.0 Suffix 4.75 Suffix 5.0 Suffix

Vout

Min

Typ

Max

2.74 2.94 3.13 3.23 3.72 3.92 4.66 4.90

2.8 3.0 3.2 3.3 3.8 4.0 4.75 5.0

2.86 3.06 3.27 3.37 3.88 4.08 4.85 5.1

Unit V

4

V 2.7 2.9 3.09 3.18 3.67 3.86 4.58 4.83

2.8 3.0 3.2 3.3 3.8 4.0 4.75 5.0

2.9 3.1 3.31 3.42 3.93 4.14 4.92 5.17

–

2.0

10

– – –

8.0 15 20

25 35 45

– – –

30 137 180

90 230 260

60

70

–

–

1.0

–

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ LINE AND LOAD REGULATION, DROPOUT VOLTAGES Line Regulation (All versions) Vout + 1.0 V < Vin < 12 V, Iout = 60 mA

Regline

Load Regulation (All versions)

Regload

Vin = Vout + 1.0 V Iout = 1.0 to 60 mA Iout = 1.0 to 100 mA Iout = 1.0 to 150 mA

Dropout Voltage (All versions)

Vin – Vout

4/6

mV

1

mV

4, 6

Iout = 10 mA Iout = 100 mA Iout = 150 mA

mV

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DYNAMIC PARAMETERS

Ripple Rejection (All versions) Vin = Vout + 1.0 V, Vpp = 1.0 V, f = 1.0 kHz, Iout = 60 mA

4, 6

Line Transient Response Vin = Vout + 1.0 V to Vout + 4.0 V, Iout = 60 mA, d(Vin)/dt = 15 mV/s

4, 6

Output Noise Voltage (All versions) Cout = 1.0 µF, Iout = 60 mA, f = 100 Hz to 100 kHz Cbypass = 10 nF Cbypass = 1.0 nF Cbypass = 0 nF

VRMS

dB

mV

µVrms

4, 6

– – –

25 40 65

– – –

–

230

–

– –

40 1.1

– –

µs ms

–

150

–

°C

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Output Noise Density

VN

Output Rise Time (All versions) Cout = 1.0 µF, Iout = 30 mA, VON/OFF = 0 to 2.4 V 1% of ON/OFF Signal to 99% of Nominal Output Voltage Without Bypass Capacitor With Cbypass = 10 nF

tr

nV/ √Hz

4

Cout = 1.0 µF, Iout = 60 mA, f = 1.0 kHz

4

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ THERMAL SHUTDOWN

Thermal Shutdown (All versions)


MC33263 DEFINITIONS This feature is provided to prevent catastrophic failures from accidental overheating. Maximum Package Power Dissipation – The maximum package power dissipation is the power dissipation level at which the junction temperature reaches its maximum value i.e. 125°C. The junction temperature is rising while the difference between the input power (VCC X ICC) and the output power (Vout X Iout) is increasing. Depending on ambient temperature, it is possible to calculate the maximum power dissipation, maximum load current or maximum input voltage (see Application Hints: Protection). The maximum power dissipation supported by the device is a lot increased when using appropriate application design. Mounting pad configuration on the PCB, the board material and also the ambient temperature are affected the rate of temperature rise. It means that when the IC has good thermal conductivity through PCB, the junction temperature will be “low” even if the power dissipation is great. The thermal resistance of the whole circuit can be evaluated by deliberately activating the thermal shutdown of the circuit (by increasing the output current or raising the input voltage for example). Then you can calculate the power dissipation by subtracting the output power from the input power. All variables are then well known: power dissipation, thermal shutdown temperature (150°C for MC33263) and ambient temperature.

Load Regulation – The change in output voltage for a change in load current at constant chip temperature. Dropout Voltage – The input/output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. Measured when the output drops 100 mV below its nominal value (which is measured at 1.0 V differential), dropout voltage is affected by junction temperature, load current and minimum input supply requirements. Output Noise Voltage – The RMS AC voltage at the output with a constant load and no input ripple, measured over a specified frequency range. Maximum Power Dissipation – The maximum total dissipation for which the regulator will operate within specifications. Quiescent Current – Current which is used to operate the regulator chip and is not delivered to the load. Line Regulation – The change in input voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. Line Transient Response – Typical over– and undershoot response when input voltage is excited with a given slope. Thermal Protection – Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated, typically 150°C, the regulator turns off.


MC33263 APPLICATION HINTS Input Decoupling – As with any regulator, it is necessary to reduce the dynamic impedance of the supply rail that feeds the component. A 1.0 F capacitor either ceramic or tantalum is recommended and should be connected close to the MC33263 package. Higher values will correspondingly improve the overall line transient response. Output Decoupling – Thanks to a novel concept, the MC33263 is a stable component and does not require any Equivalent Series Resistance (ESR) neither a minimum output current. Capacitors exhibiting ESRs ranging from a few m up to 3.0 can thus safely be used. The minimum decoupling value is 1.0 F and can be augmented to fulfill stringent load transient requirements. The regulator accepts ceramic chip capacitors as well as tantalum devices. Noise Performances – Unlike other LDOs, the MC33263 is a true low–noise regulator. With a 10 nF bypass capacitor, it typically reaches the incredible level of 25 VRMS overall noise between 100 Hz and 100 kHz. To give maximum insight on noise specifications, ON Semiconductor includes spectral density graphics as well as noise dependency versus bypass capacitor. The bypass capacitor impacts the start–up phase of the MC33263 as depicted by the data–sheet curves. A typical 1.0 ms settling time is achieved with a 10 nF bypass capacitor. However, thanks to its low–noise architecture, the MC33263 can operate without bypass and thus offers a typical 20 s start–up phase. In that case, the typical output noise stays lower than 65 VRMS between 100 Hz – 100 kHz. Protections – The MC33263 hosts several protections, conferring natural ruggedness and reliability to the products implementing the component. The output current is internally limited to a minimum of 175 mA while temperature shutdown occurs if the die heats up beyond 150°C. These value lets you assess the maximum differential voltage the device can sustain at a given output current before its protections come into play. The maximum dissipation the package can handle is given by:

If a 150 mA output current is needed, the ground current is extracted from the data–sheet curves: 6.5 mA @ 150 mA. For a MC33263NW28R2 (2.8 V), the maximum input voltage will then be 6.48 V, a rather comfortable margin. Typical Application – The following figure portraits the typical application for the MC33263 where both input/output decoupling capacitors appear. Input

Output

6 C3 1.0 F

4 C2 1.0 F

MC33263

1 On/Off

5

2

3 C1 10 nF

Figure 2. A Typical MC33263 Application with Recommended Capacitor Values

As for any low noise designs, particular care has to be taken when tackling Printed Circuit Board (PCB) layout. The following figure gives an example of a layout where stray inductances/capacitances are minimized.

T – T A P max + Jmax R JA

If TJmax is internally limited to 150°C, then the MC33263 can dissipate up to 595 mW @ 25°C. The power dissipated by the MC33263 can be calculated from the following formula:

Figure 3. Printed Circuit Board

Ptot + ǀ V @ I (I )ǁ ) ǀV * Vout ǁ @ I out in gnd out in

or Vin max +

Ptot ) Vout @ I out I ) I out gnd


MC33263 Differential (Vin–Vout)

Input

C3 MC33263 + +

C2

charge the bypass capacitor with the enable signal without degrading the noise response of the MC33263. At power–on, C4 is discharged. When the control logic sends its wake–up signal by going to a high level, the PNP base is momentarily tight to ground. The PNP switch closes and immediately charges the bypass capacitor C1 toward its operating value. After a few s, the PNP opens and becomes totally transparent to the regulator. This circuit improves the response time of the regulator which drops from 1.0 ms down to 30 s. The value of C4 needs to be tweaked in order to avoid any bypass capacitor overload during the wake–up transient.

Output

C1 Rpull–up

Input

Output

6 ON/OFF

+ C3 1.0 F

Figure 4. Copper Side Component Layout

This layout is the basis for an MC33263 performance evaluation board where the BNC connectors give the user an easy and quick evaluation mean. MC33263 Wake–up Improvement – In portable applications, an immediate response to an enable signal is vital. If noise is not of concern, the MC33263 without a bypass capacitor settles in nearly 20 s and typically delivers 65 VRMS between 100 Hz and 100 kHz. In ultra low–noise systems, the designer needs a 10 nF bypass capacitor to decrease the noise down to 25 VRMS between 100 Hz and 100 kHz. With the adjunction of the 10 nF capacitor, the wake–up time expands up to 1.0 ms as shown on the data–sheet curves. If an immediate response is wanted, following figure’s circuit gives a solution to

5

4 + C2 1.0 F

MC33263

1

2

3

On/Off R2 220 k

C4 470 pF

MMBT2902LT1 Q1

C1 10 nF

Figure 5. A PNP Transistor Drives the Bypass Pin when Enable Goes High


MC33263

MC33263 Without Wake–up Improvement (Typical Response)

1 ms

MC33263 With Wake–up Improvement (Typical Response) 30 s

Figure 6. MC33263 Wake–up Improvement with Small PNP Transistor

area which reaches a typical noise level of 26 VRMS (100 Hz to 100 kHz) at Iout = 60 mA.

The PNP being wired upon the bypass pin, it shall not degrade the noise response of the MC33263. Figure 7 confirms the good behavior of the integrated circuit in this 350

Vin = 3.8 V Vout = 2.8 V Co = 1.0 F Iout = 60 mA Tamb = 25°C

nV/sqrt (Hz)

300 250 200 Cbyp = 10 nF 150 100 50

Vin = 26 Vrms C = 10 nF @ 100 Hz – 100 kHz

0 100

1,000

10,000

100,000

1,000,000

Frequency (Hz)

Figure 7. Noise Density of the MC33263 with a 10 nF Bypass Capacitor and a Wake–up Improvement Network


MC33263 TYPICAL PERFORMANCE CHARACTERISTICS Ground Current Performances 2.1 GROUND CURRENT (mA)

GROUND CURRENT (mA)

7.0 Vin = 3.8 V Vout = 2.8 V CO = 1.0 mF Tamb = 25°C

6.0 5.0 4.0 3.0 2.0

2.05

Vin = 3.8 V Vout = 2.8 V CO = 1.0 F Iout = 60 mA

2.0 1.95 1.9 1.85

1.0 0 0

20

40

60

80

100 120 140 160 180 200

1.8 –40

–20

0

20

40

60

80

OUTPUT CURRENT (mA)

AMBIENT TEMPERATURE (°C)


Figure 9. Ground Current versus Ambient Temperature

QUIESCENT CURRENT ON MODE (A)

Line Transient Response and Output Voltage 200 190 Y1

180 170 160

Vin = 3.8 to 7.0 V Y1 = 1.0 mV/div Y2 = 1.0 V/div X = 1.0 ms Iout = 60 mA Tamb = 25°C

150 140 130 120 110 100 –40

–20

0

20

40

60

80

dVin = 3.2 V

100

TEMPERATURE (°C)




Y2

MC33263 TYPICAL PERFORMANCE CHARACTERISTICS Load Transient Response versus Load Current Slope

Y1 Y2 Vin = 3.8 V Y1 = 100 mV/div Y2 = 20 mV/div X = 200 s/div Tamb = 25°C

Vin = 3.8 V Y1 = 50 mA/div Y2 = 20 mV/div X = 20 s Tamb = 25°C

Y1

Y2

Y1: OUTPUT CURRENT, Y2: OUTPUT VOLTAGE


Figure 12. Iout = 3.0 mA to 150 mA

Figure 13. ISlope = 100 mA/ms (Large Scale) Iout = 3.0 mA to 150 mA

Y1

Y1


Y2


Y2



Figure 14. ISlope = 6.0 mA/ms (Large Scale) Iout = 3.0 mA to 150 mA

Figure 15. ISlope = 2.0 mA/ms (Large Scale) Iout = 3.0 mA to 150 mA


MC33263 TYPICAL PERFORMANCE CHARACTERISTICS Noise Performances 350

70

250

3.3 nF

200

60 RMS NOISE (A)

0 nF

300

O.A

Vin = 3.8 V Vout = 2.8 V CO = 1.0 F Iout = 60 mA Tamb = 23°C

Cbyp = 10 nF 150 100

Vn = 65 Vrms @ Cbypass = 0 Vn = 30 Vrms @ Cbypass = 3.3 nF Vn = 25 Vrms @ Cbypass = 10 nF 0 over 100 Hz to 100 kHz 100,000 100 1000 10,000 FREQUENCY (Hz)

50

50 40 30 Vin = 3.8 V Vout = 2.8 V CO = 1.0 F Iout = 60 mA Tamb = 25°C

20 10 0

1,000,000

Figure 16. Noise Density versus Bypass Capacitor

0

1.0

2.0

3.0 4.0 5.0 6.0 7.0 8.0 BYPASS CAPACITOR (nF)

9.0

10

Figure 17. RMS Noise versus Bypass Capacitor (100 Hz – 100 kHz)

Settling Time Performances 1200 Vin = 3.8 V Vout = 2.8 V CO = 1.0 F Iout = 60 mA Tamb = 25°C

SETTLINE TIME (A)

1000 800 600

200 s/div 500 mV/div Cbyp = 10 nF

400 200 0 0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

Vin = 3.8 V Vout = 2.8 V Cout = 1.0 F Iout = 50 mA Tamb = 25°C

10

BYPASS CAPACITOR (nF)

Figure 18. Output Voltage Settling Time versus Bypass Capacitor

100 s/div 500 mV/div Cbyp = 3.3 nF

Figure 19. Output Voltage Settling Shape Cbypass = 10 nF


10 s/div 500 mV/div Cbyp = 0 nF

Figure 20. Output Voltage Settling Shape Cbypass = 3.3 nF


Figure 21. Output Voltage Settling Shape without Bypass Capacitor


MC33263 TYPICAL PERFORMANCE CHARACTERISTICS

#

250

##

200

150 mA

85°C #

100 mA

<%(%D>C01

<%(%D>C01

Dropout Voltage

25°C –40°C

##

150 60 mA 100

# #

50

#

##

6#

10 mA

0 –40

#

–20

0

20

40

60

80

100

IO (mA)

TEMPERATURE (°C)

Figure 22. Dropout Voltage versus Iout


Output Voltage 2.860

2.805 1 mA

2.840 %D>(D>C%2>"):C01

%D>(D>C%2>"):C01

2.800 2.795

60 mA

2.790 100 mA

2.785 150 mA

2.780

2.820 2.800

–40°C

25°C 2.780 85°C 2.760

2.775 2.770 –40

2.740 –20

0

20

40

60

80

20

0

100

40

60

80

100

120

140

TEMPERATURE (°C)

OUTPUT CURRENT (mA)


Figure 25. Output Voltage versus Iout

160

Ripple Rejection Performances 0

0 –10


(dB)

–30 –40


–20 –40 (dB)

–20

–50

–60

–60 –80

–70 –80

–100

–90 –100

–120 100

1000

10,000

100,000

10

100

1000

10,000

100,000 1,000,000

FREQUENCY (Hz)

FREQUENCY (Hz)

Figure 26. Ripple Rejection versus Frequency with 10 nF Bypass Capacitor

Figure 27. Ripple Rejection versus Frequency without Bypass Capacitor


MC33263 ORDERING AND DEVICE MARKING INFORMATION

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Device

Marking

Version

MC33263NW–28R2

A

2.8 V

MC33263NW–30R2

B

3.0 V

MC33263NW–32R2

C

3.2 V

MC33263NW–33R2

D

3.3 V

MC33263NW–38R2

E

3.8 V

MC33263NW–40R2

F

4.0 V

MC33263NW–47R2

G

4.75 V

MC33263NW–50R2

H

5.0 V


Package

Shipping

SOT 23L SOT–23L

2500 Tape & Reel

"!#-"$$

% $ % ) 9): The MC78PC00 are a series of CMOS linear voltage regulators with high output voltage accuracy, low supply current, low dropout voltage, and high Ripple Rejection. Each of these voltage regulators consists of an internal voltage reference, an error amplifier, resistors, a current limiting circuit and a chip enable circuit. The dynamic Response to line and load is fast, which makes these products ideally suited for use in hand–held communication equipment. The MC78PC00 series are housed in the SOT–23 5 lead package, for maximum board space saving.

http://onsemi.com 5 1

SOT–23–5 N SUFFIX CASE 1212

MC78PC00 Features:

• • • • • • • • • • •

Ultra–Low Supply Current: typical 35 A in ON mode with no load. Standby Mode: typical 0.1 A. Low Dropout Voltage: typical 0.2 V @ IOUT = 100 mA. High Ripple Rejection: typical 70 dB @ f = 1 kHz. Low Temperature–Drift Coefficient of Output Voltage: typical ±100 ppm/°C. Excellent Line Regulation: typical 0.05%/V. High Accuracy Output Voltage: ±2.0%. Fast Dynamic Response to Line and Load. Small Package: SOT–23 5 leads. Built–in Chip Enable circuit (CE input pin). Identical Pinout to the LP2980/1/2.

PIN CONNECTIONS '@

•

:

-

%D>

-

@O

DEVICE MARKING

0 Q& Q /1

• Power source for cellular phones (GSM, CDMA, TDMA), Cordless •

)@
1

MC78PC00 Applications:

Phones (PHS, DECT) and 2–way radios. Power source for domestic appliances such as cameras, VCRs and camcorders. Power source for battery–powered equipment.

Marking

Voltage Version

W7

7

$

$7

7

)#

-#

)-

--

E# -

# 2 @&

Block Diagram PIN DESCRIPTION '@

MC78PCxx

:

%D>


Symbol

Description

'@

' (

)@

% (


D:@> 2'G'>

-


Pin #

424

)@

)@

%D>

'%D> $

)@
BC%D>(D>C%2>"):C0%2>F1

%D>BC%D>(D>C%2>"):C0%2>F1

#

7

-

# #7 #6

'@ =

# # #

>" = ° #

##

##

-##

##

#

>" = ° #

##

##

-##

##

##

Figure 6. MC78PC30 Output Voltage versus Output Current

6# 6#

-

%D>BC%D>(D>C%2>"):C0%2>F1

%D>BC%D>(D>C%2>"):C0%2>F1

#


#

-#

'@ = -

#

#

>" = °

#

##

#

##

-##

##

##

8#

#

6#

# -#

'@ = -

# # #

>" = ° ##

#

##

-##

##

'%D>B %D>(D> D:@> 0"1

'%D>B %D>(D> D:@> 0"1

Figure 7. MC78PC40 (4.0 V) Output Voltage versus Output Current


#

##

-

9

%D>BC%D>(D>C%2>"):C0%2>F1

%D>BC%D>(D>C%2>"):C0%2>F1

'@ = --

'%D>B %D>(D> D:@> 0"1

#

'%D> = "

7 8 6

-# "

-

#

'%D>B %D>(D> D:@> 0"1

#

#

#

##

#

-#

>" = °

# " #

#

-#

#

#

6#

8#

-# 9 7

-# "

6

7#

# "

8

'%D> = # " #

-#

>" = ° #

#

6#

8#

'@B '@(D> %2>"): 0%2>F1

'@B '@(D> %2>"): 0%2>F1

Figure 9. MC78PC18 Output Voltage versus Input Voltage



7#

MC78PC00 Series

-

'%D> = # "

-#

-# "

# "

# -#

>" = ° #

#

6#

8#

-#

# "

-# " #

-#

>" = ° #

#

6#

8#

7#


##

#6

°

#

+#°

#

#

##

>" = 7 °

#-

#-#

°

#

+#°

# # #

## ##

#

#

#

#

##

#

'%D>B %D>(D> D:@> 0"1

'%D>B %D>(D> D:@> 0"1

Figure 13. MC78PC18 Dropout Voltage versus Output Current


##

##

#-

C%2>"):C0%2>F1

'%D> = # "

-

Figure 11. MC78PC40 (4.0 V) Output Voltage versus Input Voltage

#7

>" = 7 °

#-#

°

#

# #

+#°

#

## ##

#

#

'@B '@(D> %2>"): 0%2>F1

>" = 7 °

#

7#

#

#

#

'@B '@(D> %2>"): 0%2>F1

C%2>"):C0%2>F1

%D>BC%D>(D>C%2>"):C0%2>F1

#

#

##

#-

#-#

>" = 7 °

#

°

# # #

## ##

#

#

+#°

#

#

##

#

'%D>B %D>(D> D:@> 0"1

'%D>B %D>(D> D:@> 0"1

Figure 15. MC78PC40 (4.0 V) Dropout Voltage versus Output Current



MC78PC00 Series -#7

77

'@ = 7 '%D> = -# "

76

%D>BC%D>(D>C%2>"):C0%2>F1

%D>BC%D>(D>C%2>"):C0%2>F1

9#

7 7 7# 87 86 8 8 8# + #

+

#

#

8

##

-# -## 97 96 9 9 9# + #

+

#

#

8

Figure 17. MPC78PC18 Output Voltage versus Temperature

Figure 18. MC78PC30 Output Voltage versus Temperature

##

#

#7

'@ = # '%D> = # "

#6

%D>BC%D>(D>C%2>"):C0%2>F1

%D>BC%D>(D>C%2>"):C0%2>F1

-#

>"B >:G(:">D: 0°1

# # ## -97 -96 -9 -9 -9# + #

+

#

#

8

##

#7

'@ = 6# '%D> = # "

#6

#

#

## 97 96 9 9 9# + #

+

#

#

8

>"B >:G(:">D: 0°1

>"B >:G(:">D: 0°1

Figure 19. MC78PC40 (4.0 V) Output Voltage versus Temperature

Figure 20. MC78PC50 Output Voltage versus Temperature

6#

##

#

#

'FF BCFD((2KCD:@>C0CCC"1


'@ = # '%D> = # "

-#

>"B >:G(:">D: 0°1

#

# -# # # #

-#6

# -# # #

>" = ° #

#

-#

#

#

6#

8#

>" = ° #

7#

#

-#

#

#

6#

8#

'@B '@(D> %2>"): 0%2>F1

'@B '@(D> %2>"): 0%2>F1

Figure 21. MC78PC18 Supply Current versus Input Voltage



7#

#

#

#

#



MC78PC00 Series

-# # #

-# # #

>" = ° #

-#

#

#

6#

8#

>" = ° #

7#

-#

#

#

6#

8#

'@B '@(D> %2>"): 0%2>F1

Figure 23. MC78PC40 (4.0 V) Supply Current versus Input Voltage


#

#

# -

-#

# + #

+

#

#

8

-#

+

#

#

8

>"B >:G(:">D: 0°1

Figure 25. MC78PC30 Supply Current versus Temperature

Figure 26. MC78PC40 (4.0 V) Supply Current versus Temperature

#8 = # "

# # " #

##

7#

#

# + #

##

# 'FF BCFD((2KCD:@>C0CCC"1

#

'@B '@(D> %2>"): 0%2>F1

'FFBCFD((2KCD:@>C0CCC"1

'FFBCFD((2KCD:@>C0CCC"1

#

6#

7#

8#

8#

6#

# # -# #

#

#

#

6#

# # -# #

6#

# # -# '%D> = # " '%D> = -# " '%D> = # "

'@ = # = 8 $ #

#

6#

# # -# # #

##

#

##

Figure 31. MC78PC30 Ripple Rejection versus Frequency


8#

6#

# # -# '%D> = # " '%D> = -# " '%D> = # "

'@ = # = 8 $ #

#

B $:HD:@K 0/.A1

8#

#

#

B $:HD:@K 0/.A1

7#

#

'%D> = # " '%D> = -# " '%D> = # "

'@ = # = # $

#

7#

#

##


8#

#

#


8#

#

#

B $:HD:@K 0/.A1

7#

#

#

B $:HD:@K 0/.A1

7#

#

'%D> = # " '%D> = -# " '%D> = # "

'@ = 7 = # $

# #

##

BC'((2:C:E:>'%@C0I1

BC'((2:C:E:>'%@C0I1

'%D> = # " '%D> = -# " '%D> = # "

'@ = 7 = # $

# #

BC'((2:C:E:>'%@C0I1

BC'((2:C:E:>'%@C0I1

7#

BC'((2:C:E:>'%@C0I1

BC'((2:C:E:>'%@C0I1

MC78PC00 Series

#

#

6#

# # -# # # #

##

'%D> = # " '%D> = -# " '%D> = # "

'@ = # = # $ #

#

#

B $:HD:@K 0/.A1

B $:HD:@K 0/.A1

Figure 33. MC78PC40 (4.0 V) Ripple Rejection versus Frequency

Figure 34. MC78PC40 (4.0 V) Ripple Rejection versus Frequency


##

MC78PC00 Series

BC'((2:C:E:>'%@C0I1

7# 8# 6#

# # -# # # #

'%D> = # " '%D> = -# " '%D> = # "

'@ = 6# = 8 $ #

#

#

##

B $:HD:@K 0/.A1

7#

7#

8#

8#

BC'((2:C:E:>'%@C0I1

BC'((2:C:E:>'%@C0I1


6#

# # -# # # #

'%D> = # " '%D> = -# " '%D> = # "

'@ = 6# = # $ #

#

#

# # -# = ## .A = # /.A = # /.A

#

#

##

-

-

-


Figure 37. MC78PC30 Ripple Rejection versus Input Voltage (DC Bias)

7#

6#

# # -# = ## .A = # /.A = # /.A

# # -

--

'@B '@(D> %2>"): 0%2>F1

'%D> = # " %D> = # $

8#

-

B $:HD:@K 0/.A1

BC'((2:C:E:>'%@C0I1

BC'((2:C:E:>'%@C0I1

6#

#

7#

#

'%D> = # " %D> = # $

-

--

-

'%D> = # " %D> = # $

8# 6#

# # -#

= ## .A = # /.A = # /.A

# # #

-

-

-

--

-

'@B '@(D> %2>"): 0%2>F1

'@B '@(D> %2>"): 0%2>F1




-

MC78PC00 Series

-

#

-

-# %D>(D> %2>"):

-#

= = # %D> = 8 $ 0>"@>"2DG1 '%D> = -# "

9 #

#

#

6#

7#

##

# #

# '@(D> %2>"):

-

#

-

-# %D>(D> %2>"):

-#

= = # %D> = 67 $ 0>"@>"2DG1 '%D> = -# "

9

7

#

#

#

6#

7#

##

# # # #

B >'G: 01

B >'G: 01

Figure 40. MC78PC30 Line Transient Response


-

'@(D> %2>"):

-

#

-

-# %D>(D> %2>"):

-#

#

= = # %D> = # $ 0>"@>"2DG1 '%D> = -# "

9 #

#

#

6#

7#

##

#

#

%D>BC%D>(D>C%2>"):C0%2>F1

'@BC'@(D>C%2>"):C0%2>F1

#

#

--

## %D>(D> D:@>

-

-

# %D>(D> %2>"): + #

-#

'@ = # 0>"@>"2DG1 %D> = 8 $ 0>"@>"2DG1 '@ = #

9

#

7

#

#

#

#

6#

7#

#

6

7

+## #

+ #

B >'G: 01

B >'G: 01


Figure 43. MC78PC30 Load Transient Response

-

-

%D>(D> D:@>

-

-

# #

%D>(D> %2>"): + #

-#

'@ = # 0>"@>"2DG1 %D> = 67 $ 0>"@>"2DG1 '@ = #

9 #

#

#

6#

7#

#

6

7

+## #

%D>BC%D>(D>C%2>"):C0%2>F1

##

#

+ #

--

## %D>(D> D:@>

- -

# %D>(D> %2>"): + #

-#

'@ = # 0>"@>"2DG1 %D> = # $ 0>"@>"2DG1 '@ = #

9 7

#

#

#

#

6#

7#

#

6

7

+## #

+ #

B >'G: 01

B >'G: 01




'%D>BC%D>(D>CD:@>C0"1

--

'%D>BC%D>(D>CD:@>C0"1

%D>BC%D>(D>C%2>"):C0%2>F1

#

'%D>BC%D>(D>CD:@>C0"1

%D>BC%D>(D>C%2>"):C0%2>F1

6#

--

7

--

# #

-

7

%D>BC%D>(D>C%2>"):C0%2>F1

# '@(D> %2>"):

6# '@BC'@(D>C%2>"):C0%2>F1

--

7

-

6# '@BC'@(D>C%2>"):C0%2>F1

%D>BC%D>(D>C%2>"):C0%2>F1

-

MC78PC00 Series APPLICATION HINTS When using these circuits, please be sure to observe the following points: • Phase compensation is made for securing stable operation even if the load current varies. For this reason, be sure to use a capacitor COUT with good frequency characteristics and ESR (Equivalent Series Resistance) as described in the graphs on page 434. On page 434, the relations between IOUT (Output

-

Current) and ESR of Output Capacitor are shown. The conditions where the white noise level is under 40 V (Avg.) are marked by the shaded area in the graph. (note: When additional ceramic capacitors are connected to the Output Pin with Output capacitor for phase compensation, there is a possibility that the operation will be unstable. Because of this, test these circuits with as same external components as ones to be used on the PCB).

:

'@

%D>

:"G' "("'>% # $

#

F"

:"G' "("'>%

)@< :F

F(:>DG "@"2KF:

'%D>

G:"FD'@) %@'%@F? 0 1 >:G(:">D:? °

Figure 46. Measuring Circuit for White Noise: MC78PC30

• Set external components, especially the Output Capacitor, as close as possible to the circuit, and make the wiring as short as possible.

• Please be sure the Vin and GND lines are sufficiently wide. When the impedance of these lines is high, there is a chance to pick up noise or to malfunction. • Connect the capacitor with a capacitance of 1.0 F or more between Vin and GND as close as possible to Vin or GND.

:

'@

'@

MC78PCxx

* "(

%D>

%D> *

)@
B %D>(D> D:@> 0"1

Figure 50. Ceramic Capacitor 10 mF


#

#

MC78PC00 Series TAPE AND REEL INFORMATION

Component Taping Orientation for 5L SOT–23 Devices

USER DIRECTION OF FEED DEVICE MARKING

PIN 1

Standard Reel Component Orientation for TR Suffix Device (Mark Right Side Up)

Tape & Reel Specifications Table Package

Tape Width (W)

Pitch (P)

Part Per Full Reel

5L SOT–23

8 mm

4 mm

3000

Reel Diameter 7 inches


Package

Shipping

SOT 23 SOT–23 5 Leads

3000 Units/Tape & Reel

MC78PC18NTR MC78PC25NTR MC78PC28NTR MC78PC30NTR MC78PC33NTR MC78PC50NTR Other voltages are available. Consult your ON Semiconductor representative.


MC78PC00 Series Recommended Footprint for SOT–23–5 Surface Mount Applications 0.7 MAX.

1.0

2.4

0.95

0.95 1.9

SOT–23–5


(Unit: mm)

"- $ " % 01 %() The NCP551 series of fixed output low dropout linear regulators are designed for handheld communication equipment and portable battery powered applications which require low quiescent. The NCP551 series features an ultra–low quiescent current of 4.0 µA. Each device contains a voltage reference unit, an error amplifier, a PMOS power transistor, resistors for setting output voltage, current limit, and temperature limit protection circuits. The NCP551 has been designed to be used with low cost ceramic capacitors and requires a minimum output capacitor of 0.1 µF. The device is housed in the micro–miniature TSOP–5 surface mount package. Standard voltage versions are 1.5, 1.8, 2.5, 2.7, 2.8, 3.0, 3.3, and 5.0 V. Other voltages are available in 100 mV steps.

5 1 TSOP–5 (SOT23–5, SC59–5) SN SUFFIX CASE 483


Features

Low Quiescent Current of 4.0 µA Typical Maximum Operating Voltage of 12 V Minimum Output Capacitance of 1.0 µF Low Output Voltage Option High Accuracy Output Voltage of 2.0% Industrial Temperature Range of –40°C to 85°C

Vin

1

Gnd

2

Enable

3

5

Vout

4

N/C

xxxYW

• • • • • •

http://onsemi.com

xxx = Version Y = Year W = Work Week



(Top View)

ORDERING INFORMATION Vin

1

5 Thermal Shutdown

Vout


Driver w/ Current Limit

Enable ON

3

OFF

Gnd

2




439


NCP551

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin No.

Pin Name

1

Vin

Positive power supply input voltage

Description

2

Gnd

Power supply ground

3

Enable


4

N/C

No Internal Connection

5

Vout

Regulated output voltage

MAXIMUM RATINGS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating

Symbol

Value

Unit

Input Voltage

Vin

0 to 12

V

Enable Voltage

VEN

–0.3 to Vin +0.3

V

Output Voltage

Vout

–0.3 to Vin +0.3

V

Power Dissipation and Thermal Characteristics Power Dissipation Thermal Resistance, Junction–to–Ambient

PD RθJA


W °C/W


TJ

+125

°C


TA

–40 to +85

°C

Storage Temperature

Tstg

–55 to +150

°C

Tsolder

10

sec


1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL–STD–883, Method 3015 Machine Model Method 200 V 2. Latch up capability (85°C) " 100 mA DC with trigger voltage.


NCP551 ELECTRICAL CHARACTERISTICS (Vin = Vout(nom.) + 1.0 V, VEN = Vin, Cin = 1.0 µF, Cout = 1.0 µF, TJ = 25°C, unless otherwise noted.) Symbol

Characteristic Output Voltage (TA = 25°C, Iout = 10 mA) 1.5 V 1.8 V 2.5 V 2.7 V 2.8 V 3.0 V 3.3 V 5.0 V

Vout


Vout

Min

Typ

Max

1.455 1.746 2.425 2.646 2.744 2.94 3.234 4.90

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

1.545 1.854 2.575 2.754 2.856 3.06 3.366 5.10

1.440 1.728 2.400 2.619 2.716 2.910 3.201 4.850

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

1.560 1.872 2.600 2.781 2.884 3.09 3.399 5.150

Unit V

V


Regline

–

10

30

mV


Regload

–

40

65

mV

Output Current 1.5 V, 1.8 V (Vin = 4.0 V) 2.5 V, 2.7 V, 2.8 V, 3.0 V (Vin = 5.0 V) 3.3 V (Vin = 6.0 V) 5.0 V (Vin = 8.0 V)

Io(nom.)

150 150 150 150

– – – –

– – – –

Dropout Voltage (Iout = 10 mA, Measured at Vout –3.0%) 1.5 V, 1.8 V, 2.5 V 2.7 V, 2.8 V, 3.0 V, 3.3 V, 5.0 V

Vin–Vout

– –

130 40

220 150

– –

0.1 4.0

1.0 8.0

–

"100

–

1.3 –

– –

– 0.3

160 160 160 160

350 350 350 350

600 600 600 600


IQ


Tc


mA

mV

µA

V

Vth(en)

Output Short Circuit Current 1.5 V, 1.8 V (Vin = 4.0 V) 2.5 V, 2.7 V, 2.8 V, 3.0 V (Vin = 5.0 V) 3.3 V (Vin = 6.0 V) 5.0 V (Vin = 8.0 V)

mA

Iout(max)

3. Maximum package power dissipation limits must be observed. TJ(max) * TA PD + RJA 4. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.


ppm/°C


Line Regulation



Dropout Voltage

The input/output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. Measured when the output drops 3% below its nominal. The junction temperature, load current, and minimum input supply requirements affect the dropout level.










NCP551 3.45

3.35

Vout = 3.3 V

3.3

GROUND CURRENT (A)

GROUND CURRENT (A)

Vout = 2.8 V

3.25 3.2 3.15 3.1 3.05

3.35 3.3 3.25 3.2 3.15

0

25

50

75

100

125

150

0

75

100

125

Figure 2. Ground Pin Current versus Output Current

Figure 3. Ground Pin Current versus Output Current

4

3.5

3.5

3 2.5 2 1.5 Vout(nom) = 2.8 V Iout = 25 mA

1 0.5

150

3 2.5 2 1.5 Vout(nom) = 3.3 V Iout = 25 mA

1 0.5 0

0 2

4

6

8

10

12

0

14

2

4

6

8

10

12



Figure 4. Ground Pin Current versus Input Voltage


8 6 4

Vin = 3.8 V to 4.8 V Vout = 2.8 V Cout = 1 F Iout = 10 mA

400 200



0


50


4


25


GROUND PIN CURRENT (A)

GROUND PIN CURRENT (A)

3.4

14

6 4


400 200 0

–200

0

–400

–200

–600

–400 0

200

400

600

800

1000

1200 1400

1600

0

200

400

600

800

1000 1200 1400

TIME (s)

TIME (s)




1600

4


400 200 0 –200


6

0

200

400

600

800

1000

1200 1400

0

1600

200

400

600

800

1000 1200 1400 1600

TIME (s)



6 4 800 Vin = 4.3 V to 5.3 V Vout = 3.3 V Cout = 1 F Iout = 100 mA

600 400 200 0 –200


TIME (s)



200

–600 0



400

–400

–600

6 4


600 400 200 0

–200

–400

–400

–600

–600 300

500 700

900 1100 1300 1500 1700 1900

800

1200

2000

1600




Vout = 2.8 V Cout = 10 mF

0

0 –500 –1000 0

400

TIME (s)

Iout = 3.0 mA – 150 mA 150

0

TIME (s)

1

2

3

4

5

6

7

8

9


100


4

–200

–400


6




NCP551

Iout = 3.0 mA – 150 mA Vout = 2.8 V Cout = 10 mF

150

0 1000 500 0 –500 0

1

2

3

4

5

6

7

8

9

TIME (ms)

TIME (ms)

Figure 12. Load Transient Response ON

Figure 13. Load Transient Response OFF




150

0




NCP551

1000 500 0 –500 0

1

2

3

4

5

6

7

8

9


150

0

–500 –1000

0

1

2

3

TIME (ms)

7

8

9

ENABLE VOLTAGE (V)

3

2 1 0

3

Co = 1 F

Vin = 4.3 V Vout = 3.3 V RO = 3.3 K VEN = 2.0 V

2 1

Vout, OUTPUT VOLTAGE (V)

ENABLE VOLTAGE (V)

6

Figure 15. Load Transient Response ON

3


5

TIME (ms)

Figure 14. Load Transient Response OFF

Co = 10 F

0 0

200 400 600 800 1000 1200 1400 1600 1800 2000

2 1 0

3

Co = 1 F

Vin = 3.8 V Vout = 2.8 V RO = 2.8 K VEN = 2.0 V

2 1

Co = 10 F

0 200 400 600 800 1000 1200 1400 1600 1800 2000

0

TIME (s)

TIME (s)



3



4

2.5 2 Vin = 0 V to 12 V Vout(nom) = 2.8 V Iout = 10 mA Cin = 1 F Cout = 1 F VEN = Vin

1.5 1 0.5 0

3 2.5 Vin = 0 V to 12 V Vout = 3.3 V Iout = 10 mA Cin = 1 F Cout = 1 F VEN = Vin

2 1.5 1 0.5 0

0

2

4

6

8

10

12

0

2

4

6

8

10






12



As power across the NCP551 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and also the ambient temperature effect the rate of temperature rise for the part. This is stating that when the NCP551 has good thermal conductivity through the PCB, the junction temperature will be relatively low with high power dissipation applications. The maximum dissipation the package can handle is given by:


A 0.1 µF capacitor either ceramic or tantalum is recommended and should be connected close to the NCP551 package. Higher values and lower ESR will improve the overall line transient response.


The NCP551 is a stable Regulator and does not require any specific Equivalent Series Resistance (ESR) or a minimum output current. Capacitors exhibiting ESRs ranging from a few mΩ up to 3.0 Ω can thus safely be used. The minimum decoupling value is 0.1 µF and can be augmented to fulfill stringent load transient requirements. The regulator accepts ceramic chip capacitors as well as tantalum devices. Larger values improve noise rejection and load regulation transient response.

PD +


Enable Operation


The enable pin will turn on or off the regulator. These limits of threshold are covered in the electrical specification section of this data sheet. If the enable is not used then the pin should be connected to Vin.


Hints

If a 150 mA output current is needed then the ground current from the data sheet is 4.0 µA. For an NCP551SN30T1 (3.0 V), the maximum input voltage will then be 5.6 V.



TJ(max) * TA RJA

Vout *

*

C1

ON OFF

Figure 20. Typical Application Circuit


C2

NCP551

Input

R1

Input

Q1

Q1

R2 R

Output 1 1.0 µF

R3

5

Output 1

1.0 µF

2 3

Q2

1.0 µF

4

5 1.0 µF

2 3


4

Figure 22. Current Boost Regulator with Short Circuit Limit

The NCP551 series can be current boosted with a PNP transistor. Resistor R in conjunction with VBE of the PNP determines when the pass transistor begins conducting; this circuit is not short circuit proof. Input/Output differential voltage minimum is increased by VBE of the pass resistor.

Short circuit current limit is essentially set by the VBE of Q2 and R1. ISC = ((VBEQ2 – ib * R2) / R1) + IO(max) Regulator

Output

Input 1

5

1.0 µF

1.0 µF

2 Enable 3

Input

4

R

Output 1

1.0 µF

1.0 µF

5 1.0 µF

2 3

4

11 V

2 3

1

5

1.0 µF

R

Output

Q1

4

C

Figure 24. Input Voltages Greater than 12 V

Figure 23. Delayed Turn–on

A regulated output can be achieved with input voltages that exceed the 12 V maximum rating of the NCP551 series with the addition of a simple pre–regulator circuit. Care must be taken to prevent Q1 from overheating when the regulated output (Vout) is shorted to Gnd.

If a delayed turn–on is needed during power up of several voltages then the above schematic can be used. Resistor R, and capacitor C, will delay the turn–on of the bottom regulator.




0.094 2.4

0.037 0.95 0.074 1.9 0.037 0.95 0.028 0.7 0.039 1.0

inches mm

TSOP–5 (Footprint Compatible with SOT23–5)

ORDERING INFORMATION Device NCP551SN15T1 NCP551SN18T1 NCP551SN25T1 NCP551SN27T1 NCP551SN28T1 NCP551SN30T1 NCP551SN33T1 NCP551SN50T1


Marking

Package

Shipping

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

LAO LAP LAQ LAR LAS LAT LAU LAV

TSOP–5

3000 Units/7″ Tape & Reel



"-& $ " % 01 %() The NCP561 series of fixed output low dropout linear regulators are designed for handheld communication equipment and portable battery powered applications which require low quiescent. The NCP561 series features an ultra–low quiescent current of 3.0 µA. Each device contains a voltage reference unit, an error amplifier, a PMOS power transistor, resistors for setting output voltage, current limit, and temperature limit protection circuits. The NCP561 has been designed to be used with low cost ceramic capacitors and requires a minimum output capacitor of 1.0 µF. The device is housed in the micro–miniature TSOP–5 surface mount package. Standard voltage versions are 1.5, 1.8, 2.5, 2.7, 2.8, 3.0, 3.3 and 5.0 V.



Features

Low Quiescent Current of 3.0 µA Typical Low Dropout Voltage of 170 mV at 150 mA Low Output Voltage Option Output Voltage Accuracy of 2.0% Industrial Temperature Range of –40°C to 85°C

Vin

1

Gnd

2

Enable

3

5

VOUT

4

N/C

555KJ

• • • • •

http://onsemi.com



xxx = Version Y = Year W = Work Week (Top View)

VIN

VOUT 1

5 Thermal Shutdown



Enable ON

3

OFF

Gnd

2





449


NCP561

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin No.

Pin Name

1

Vin


2

Gnd


3

Enable

4

N/C

5

VOUT

Description

This input is used to place the device into low–power standby. When this input is pulled low, the device is disabled. If this function is not used, Enable should be connected to Vin. No internal connection.


MAXIMUM RATINGS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating

Symbol

Value

Unit

VIN

6.0

V

Enable Voltage

Enable

–0.3 to VIN +0.3

V

Output Voltage

VOUT

–0.3 to VIN +0.3

V


PD RθJA


W °C/W

Input Voltage


TJ

+125

°C


TA

–40 to +85

°C

Storage Temperature

Tstg

–55 to +150

°C

Tsolder

10

sec




NCP561 ELECTRICAL CHARACTERISTICS (VIN = VOUT(nom.) + 1.0 V, Venable = VIN, CIN = 1.0 µF, COUT = 1.0 µF, TJ = 25°C, unless otherwise noted.) Characteristic

Symbol

Output Voltage (TA = 25°C, IOUT = 1.0 mA) 1.5 V 1.8 V 2.5 V 2.7 V 2.8 V 3.0 V 3.3 V 5.0 V

Min

Typ

Max

1.455 1.746 2.425 2.646 2.744 2.940 2.234 4.90

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

1.545 1.854 2.575 2.754 2.856 3.060 3.366 5.10

– –

10 10

20 20

–

30

60

150 150

– –

– –

VOUT

Line Regulation 1.5 V–4.4 V (Vin = Vo(nom.) + 1.0 V to 6.0 V) 4.5 V–5.0 V (Vin = 5.5 V to 6.0 V)

Regline

Load Regulation (IOUT = 10 mA to 150 mA)

Regload

Output Current (Vout = (Vout at Iout = 150 mA) –3.0%) 1.5 V to 3.9 V (VIN = Vo(nom.) + 2.0 V) 4.0 V to 5.0 V (VIN = 6.0 V)

Io(nom.)

Dropout Voltage (TA = –40°C to 85°C, IOUT = 150 mA, Measured at VOUT –3.0%) 1.5 V – 1.7 V 1.8 V – 2.4 V 2.5 V – 2.7 V 2.8 V – 3.2 V 3.3 V – 4.9 V 5.0 V

VIN–VOUT

Quiescent Current (Enable Input = 0 V) (Enable Input = VIN, IOUT = 1.0 mA to Io(nom.))

V

mV

mV – – – – – –

330 240 150 140 130 120

500 360 250 230 200 190

– –

0.1 4.0

1.0 8.0

160 160

400 400

800 800

–

60

–

1.3 –

– –

– 0.2

–

"100

–

µA

IOUT(max)

Output Voltage Noise (f = 20 Hz to 100 kHz, VOUT = 3.0, V IOUT = 1.0 V)

Vn


Vth(en)


TC

mA

T *TA PD + J(max) RJA 4. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.

451

µVrms V

3. Maximum package power dissipation limits must be observed.

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mV mA

IQ

Output Short Circuit Current 1.5 V to 3.9 V (VIN = Vo(nom.) + 2.0 V) 4.0 V to 5.0 V (VIN = 6.0 V)

Unit

ppm/°C

NCP561

180 160

3.015 VOUT = 3.0 V VOUT, OUTPUT VOLTAGE (V)


TYPICAL CHARACTERISTICS

140 150 mA Load

120 100

100 mA Load

80 60 40

50 mA Load

20 0 –50

–25

0

25

50

75

100

IOUT = 10 mA

3.010 3.005

VIN = 6.0 V

3.000 VIN = 4.0 V

2.995 2.990 2.985 2.980 2.975 –50

125

0


Figure 3. Output Voltages vs. Temperature 4.5

IOUT = 10 mA VIN = 4.0 V

4.50



4.75

4.25 4.00 3.75 3.50 3.25 3.00 –50

0

3.5 3.0 2.5 2.0 1.5

100

50

VOUT = 3.0 V IOUT = 0 mA TA = 25°C

4.0

1

0

2

TEMPERATURE (C°)

3

4

6

5

TEMPERATURE (C°)


Figure 5. Quiescent Current vs. Input Voltage 4.0 OUTPUT NOISE VOLTAGE (µV/ǰHz)

5.0 Ignd, GROUND PIN CURRENT (µA)

100

TEMPERATURE (C°)

TEMPERATURE (C°)

VOUT = 3.0 V IOUT = 50 mA TA = 25°C

4.5 4.0 3.5 3.0 2.5 2.0 1.5

50

0

1

2

3

4

6

5

3.5 3.0 2.5 2.0

1.0 mA

1.5 1.0

150 mA

0.5 0 10


100

1k

10 k

100 k

NOISE CHARACTERIZATION

Figure 7. Output Noise Voltage

Figure 6. Ground Current vs. Input Voltage


1000 k

NCP561

CHANGE IN OUTPUT VOLTAGE (mV)

60 50


40

IOUT = 10 mA COUT = 1.0 F

400

0

–200 –400 0.2

0.4 0.6

0.8 1.0 1.2 1.4 TIME (s)

1.6

VIN = 4.0 V VOUT = 3.0 V CIN = 1.0 F COUT = 10 F Al. Elec. Surface Mount

–50 –100 –150 –200 –250

200

0

0

1.8 2.0


VIN, INPUT VOLTAGE (mV)

TYPICAL CHARACTERISTICS

150 100 50 0 0

0 –50

VIN = 4.0 V VOUT = 3.0 V CIN = 1.0 F COUT = 10 F Tantalum

–100 –150


–200 –250 150 100 50 0

600 TIME (s)

800

1000

1200

4 2 0 3 CIN = 1.0 F COUT = 1.0 F IOUT = 10 mA

2 1 0

0

200

400

600 TIME (s)

800

1000

1200

0

200


400

3.0 2.5 CIN = 1.0 F COUT = 1.0 F TA = 25°C VENABLE = VIN

2.0 1.5 1.0 0.5 0 0

1

600 800 1000 1200 1400 1600 TIME (s)


3.5 VOUT, OUTPUT VOLTAGE (V)


400


ENABLE VOLTAGE (V)



200

4 2 3 VIN, INPUT VOLTAGE (V)

5



6


Line Regulation



Dropout Voltage











NCP561 APPLICATIONS INFORMATION Thermal A typical application circuit for the NCP561 series is shown in Figure 13. As power across the NCP561 increases, it might become necessary to provide some thermal relief. The maximum Input Decoupling (C1) power dissipation supported by the device is dependent A 1.0 µF capacitor either ceramic or tantalum is upon board design and layout. Mounting pad configuration recommended and should be connected close to the NCP561 on the PCB, the board material and also the ambient package. Higher values and lower ESR will improve the temperature effect the rate of temperature rise for the part. overall line transient response. This is stating that when the NCP561 has good thermal TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K conductivity through the PCB, the junction temperature will be relatively low with high power dissipation applications. Output Decoupling (C2) The maximum dissipation the package can handle is The NCP561 is a stable Regulator and does not require given by: any specific Equivalent Series Resistance (ESR) or a T *TA minimum output current. Capacitors exhibiting ESRs PD + J(max) RJA ranging from a few mΩ up to 3.0 Ω can thus safely be used. If junction temperature is not allowed above the The minimum decoupling value is 1.0 µF and can be maximum 125°C, then the NCP561 can dissipate up to augmented to fulfill stringent load transient requirements. 400 mW @ 25°C. The regulator accepts ceramic chip capacitors as well as The power dissipated by the NCP561 can be calculated tantalum devices. Larger values improve noise rejection and from the following equation: load regulation transient response. TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K, Ptot + [Vin * Ignd (Iout)] ) [Vin * Vout] * Iout or C3216X7R1C105K or ) VOUT * IOUT P VINMAX + TOT IGND ) IOUT

Enable Operation

The enable pin will turn on the regulator when pulled high and turn off the regulator when pulled low. These limits of threshold are covered in the electrical specification section of this data sheet. If the enable is not used then the pin should be connected to VIN.

If a 150 mA output current is needed then the ground current from the data sheet is 4.0 µA. For an NCP561SN30T1 (3.0 V), the maximum input voltage will then be 5.6 V.

Hints


Please be sure the Vin and Gnd lines are sufficiently wide. When the impedance of these lines is high, there is a chance to pick up noise or cause the regulator to malfunction. Set external components, especially the output capacitor, as close as possible to the circuit, and make leads a short as possible.

C1

*

1

* 2

ON

3

4

OFF



VOUT

5

C2

NCP561 APPLICATION CIRCUITS

Input

R1

Input

Q1

Q1

R2 R

Output

R3

5

1 1.0 µF

Q2

1.0 µF

2 3

Output 5

1 1.0 µF

4

1.0 µF

2 3




Input

4


Output 1

5

1.0 µF

1.0 µF

2 Enable 3

4 Input

1

5

1.0 µF

R

1.0 µF

Output

Q1

Output

1 1.0 µF

5 1.0 µF

2

2 3 3 R

4

5.6 V

4

C


Figure 17. Input Voltages Greater than 6.0 V

If a delayed turn–on is needed during power up of several voltages then the above schematic can be used. Resistor R, and capacitor C, will delay the turn–on of the bottom regulator.

A regulated output can be achieved with input voltages that exceed the 6.0 V maximum rating of the NCP561 series with the addition of a simple pre–regulator circuit. Care must be taken to prevent Q1 from overheating when the regulated output (VOUT) is shorted to Gnd.




0.094 2.4

0.037 0.95 0.074 1.9 0.037 0.95 0.028 0.7 0.039 1.0



inches mm

NCP561 ORDERING INFORMATION Device NCP561SN15T1 NCP561SN18T1 NCP561SN25T1 NCP561SN27T1 NCP561SN28T1 NCP561SN30T1 NCP561SN33T1 NCP561SN50T1


Marking

Package

Shipping

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

LDA LEV LDC LEX LDD LDE LDF LDH

TSOP–5




"-$$ $ " % %() The NCP500 series of fixed output low dropout linear regulators are designed for portable battery powered applications which require low noise operation, fast enable response time, and low dropout. The device achieves its low noise performance without the need of an external noise bypass capacitor. Each device contains a voltage reference unit, an error amplifier, a PMOS power transistor, and resistors for setting output voltage, and current limit and temperature limit protection circuits. The NCP500 has been designed to be used with low cost ceramic capacitors and requires a minimum output capacitor of 1.0 µF. Standard voltage versions are 1.8, 2.5, 2.7, 2.8, 3.0, 3.3, and 5.0 V.

1

QFN 2x2 SQL SUFFIX CASE 488 6

Ultra–Low Dropout Voltage of 170 mV at 150 mA Fast Enable Turn–On Time of 20 µsec Wide Operating Voltage Range of 1.8 V to 6.0 V Excellent Line and Load Regulation High Accuracy Output Voltage of 2.5% Enable Can Be Driven Directly by 1.0 V Logic Very Small QFN 2x2 Package

PIN CONNECTIONS AND MARKING DIAGRAMS TSOP–5

Noise Sensitive Circuits – VCO’s, RF Stages, etc. SMPS Post–Regulation Hand–Held Instrumentation Camcorders and Cameras

Vin

1

Gnd

2

Enable

3

5

Vout

4

N/C

6

N/C

5

Gnd

4

Vout

xxxYW


• • • •

TSOP–5 SN SUFFIX CASE 483

5

1

Features

• • • • • • •

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(Top View)

QFN 2x2

Vin 1 (3)

Vout 5 (4) Thermal Shutdown


Gnd

2

Vin

3

xxx Y W M

ON 3 (1)

Gnd

1 xxxM

(Top View)

Enable

OFF

Enable

= Version = Year = Work Week = Date Code


2 (2, 5)

NOTE: Pin numbers in parenthesis indicate QFN package.





459


NCP500

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION TSOP–5 Pin No.

QFN 2x2 Pin No.

Pin Name

1

3

Vin


2

2, 5

Gnd


3

1

Enable

4

6

N/C


5

4

Vout


Description

This input is used to place the device into low–power standby. When this input is pulled to a logic low, the device is disabled. If this function is not used, Enable should be connected to Vin.

MAXIMUM RATINGS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating

Symbol

Value

Unit

Vin

0 to 6.0

V

Enable Voltage

Von/off

–0.3 to Vin +0.3

V

Output Voltage

Vout

–0.3 to Vin +0.3

V

–

Infinite

–

Input Voltage

Output Short Circuit Duration

Thermal Resistance, Junction–to–Ambient TSOP–5 QFN

°C/W

RθJA

250 225


TJ

+125

°C

Storage Temperature

Tstg

–65 to +150

°C

Tsolder

10

sec


1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL–STD–883, Method 3015 Machine Model Method 200 V Latch up capability (85°C) "100 mA. 2. Device is internally limited to 160°C by thermal shutdown.

ELECTRICAL CHARACTERISTICS (Vin = 2.3 V, Cin = 1.0 µF, Cout = 1.0 µF, for typical value TA = 25°C, for min and max values TA = –40°C to 85°C, Tjmax = 125°C, unless otherwise noted) Characteristic

Symbol

Min

Typ

Max

Unit

–1.8 V Output Voltage (TA = –40°C to 85°C, Iout = 1.0 mA to 150 mA)

Vout

1.755

1.8

1.845

V

Line Regulation (Vin = 2.3 V to 6.0 V, Iout = 1.0 mA)

Regline

–

1.0

10

mV


Regload

–

15

45

mV

Dropout Voltage (Measured at Vout –2.0%, TA = –40°C to 85°C) (Iout = 1.0 mA) (Iout = 75 mA) (Iout = 150 mA)

Vin–Vout – – –

2.0 140 270

10 200 350

Output Short Circuit Current

Iout(max)

200

540

700

mA

RR

–

62

–

dB

– – –

0.01 175 175

1.0 300 300

0.9 –

– –

– 0.15

Ripple Rejection (Vin = Vout (nom.) + 1.0 V + 0.5 Vpp, f = 1.0 kHz, Io = 60 mA) Quiescent Current (Enable Input = 0 V) (Enable Input = 0.9 V, Iout = 1.0 mA) (Enable Input = 0.9 V, Iout = 150 mA)

mV

µA

IQ


Vth(EN)

Enable Input Bias Current

IIB(EN)

–

3.0

100

nA

–

–

20

100

µs

Output Turn On Time (Enable Input = 0 V to Vin)


V

NCP500 ELECTRICAL CHARACTERISTICS (Vin = 3.0 V, Cin = 1.0 µF, Cout = 1.0 µF, for typical value TA = 25°C, for min and max values TA = –40°C to 85°C, Tjmax = 125°C, unless otherwise noted) Symbol

Characteristic

Min

Typ

Max

2.438

2.5

2.563

Unit

–2.5 V Vout

Output Voltage (TA =–40°C to 85°C, Iout = 1.0 mA to 150 mA)

V


Regline

–

1.0

10

mV


Regload

–

15

45

mV



2.0 100 190

10 170 270


Iout(max)

200

540

700

mA

RR

–

62

–

dB

– – –

0.01 180 180

1.0 300 300

0.9 –

– –

– 0.15


mV

µA

IQ


Vth(EN)


IIB(EN)

–

3.0

100

nA

–

–

20

100

µs


V

ELECTRICAL CHARACTERISTICS (Vin = 3.2 V, Cin = 1.0 µF, Cout = 1.0 µF, for typical value TA = 25°C, for min and max values TA = –40°C to 85°C, Tjmax = 125°C, unless otherwise noted) Symbol

Characteristic

Min

Typ

Max

2.633

2.7

2.768

Unit

–2.7 V Vout


V


Regline

–

1.0

10

mV


Regload

–

15

45

mV



2.0 90 180

10 160 260


Iout(max)

200

540

700

mA

RR

–

62

–

dB

– – –

0.01 185 185

1.0 300 300

0.9 –

– –

– 0.15


mV

µA

IQ


Vth(EN)


IIB(EN)

–

3.0

100

nA

–

–

20

100

µs



V


Characteristic

Min

Typ

Max

2.730

2.8

2.870

Unit

–2.8 V Vout


V


Regline

–

1.0

10

mV


Regload

–

15

45

mV



2.0 90 170

10 150 250


Iout(max)

200

540

700

mA

RR

–

62

–

dB

– – –

0.01 185 185

1.0 300 300

0.9 –

– –

– 0.15


mV

µA

IQ


Vth(EN)


IIB(EN)

–

3.0

100

nA

–

–

20

100

µs


V

ELECTRICAL CHARACTERISTICS (Vin = 3.5 V, Cin = 1.0 µF, Cout = 1.0 µF, for typical value TA = 25°C, for min and max values TA = –40°C to 85°C, Tjmax = 125°C, unless otherwise noted) Symbol

Characteristic

Min

Typ

Max

2.925

3.0

3.075

Unit

–3.0 V Vout


V


Regline

–

1.0

10

mV


Regload

–

15

45

mV



2.0 85 165

10 130 240


Iout(max)

200

540

700

mA

RR

–

62

–

dB

– – –

0.01 190 190

1.0 300 300

0.9 –

– –

– 0.15


mV

µA

IQ


Vth(EN)


IIB(EN)

–

3.0

100

nA

–

–

20

100

µs



V


Characteristic

Min

Typ

Max

3.218

3.3

3.383

Unit

–3.3 V Vout


V


Regline

–

1.0

10

mV


Regload

–

15

45

mV



2.0 80 150

10 110 230


Iout(max)

200

540

700

mA

RR

–

62

–

dB

– – –

0.01 195 195

1.0 300 300

0.9 –

– –

– 0.15


mV

µA

IQ


Vth(EN)


IIB(EN)

–

3.0

100

nA

–

–

20

100

µs



V


Characteristic

Min

Typ

Max

4.875

5.0

5.125

Unit

–5.0 V Vout


V


Regline

–

1.0

10

mV


Regload

–

15

45

mV



2.0 60 120

10 100 180


Iout(max)

200

540

700

mA

RR

–

62

–

dB

– – –

0.01 210 210

1.0 300 300

0.9 –

– –

– 0.15


mV

µA

IQ


Vth(EN)


IIB(EN)

–

3.0

100

nA

–

–

20

100

µs


V



NCP500 200 Vout(nom.) = 3.3 V

Vin – Vout, Dropout Voltage (mV)


70 60 50 50 mA Load 40 30 20

10 mA Load

10 0 –50

1.0 mA Load –25

0

25

50

75

100

100 mA Load

100

–25

0

25

50

75

100


125

220 Vout(nom.) = 2.8 V Vin – Vout, Dropout Voltage (mV)


120 mA Load 120


50 mA Load

40 30 20

10 mA Load

10

1.0 mA Load –25

25

0

50

75

100

Vout(nom.) = 2.8 V 200 180 150 mA Load 160 140

120 mA Load

120 100 mA Load 100 80 –50

125

–25

0

25

50

75

100

Temperature (°C)

Temperature (°C)



125

350

120 Vout(nom.) = 1.8 V



150 mA Load 140

Temperature (°C)

50

100 50 mA Load 80 60 40 10 mA Load 20 1.0 mA Load 0 –50

160

Temperature (°C)

60

0 –50

180

80 –50

125

80 70

Vout(nom.) = 3.3 V

–25

0

25

50

75

100

125

330

Vout(nom.) = 1.8 V

310 290

150 mA Load

270 250 230 120 mA Load

210 190 170 150 –50

100 mA Load –25

0

25

50

75

100

Temperature (°C)

Temperature (°C)




125

NCP500 3.284

3.284 Vin = Vout(nom.) +0.5 V Vout(nom.) = 3.3 V IO = 1.0 mA

3.28 3.278 3.276 3.274 3.272

3.28 3.278 3.276 3.274 3.272

3.27 3.268 –50

–25

0

25

50

75

100

3.268 –50

125

25

50

75

100



125

210

IQ, Quiescent Current (µA)

1.803 1.8025 1.802 Vin = Vout(nom.) + 0.5 V Vout(nom.) = 1.8 V IO = 1.0 mA

1.8015 1.801 1.8005 –50

–25

0

25

50

75

100

Vout(nom.) = 3.3 V 190 180 Vout(nom.) = 1.8 V

170 160

–25

0

25

50

75

100

125

Temperature (°C)

Temperature (°C)



225

225

200

200

175 150 125 100 75 50

Vout(nom.) = 1.8 V Iout = 0 mA TA = 25°C

25 0

Vin = Vout(nom.) = + 0.5 V IO = 0 mA

200

150 –50

125


Vout, Output Voltage (V)

0

Temperature (°C)

1.8035


–25

Temperature (°C)

1.804

0

Vin = Vout(nom.) + 0.5 V Vout(nom.) = 2.8 V IO = 1.0 mA

3.282 Vout, Output Voltage (V)


3.282

1.0

2.0

3.0

4.0

5.0

175 150 125 100 75 Vout(nom.) = 3.3 V Iout = 0 mA TA = 25°C

50 25

6.0

0

0

1.0

2.0

3.0

4.0

5.0

6.0

Input Voltage (V)

Input Voltage (V)




225

225

200

200 Ground Pin Current (µA)

Ground Pin Current (µA)

NCP500

175 150 125 100 75 50


25 1.0

2.0

3.0

4.0

5.0

125 100 75 50


0 0

6.0

1.0

2.0

3.0

4.0

5.0

6.0

Input Voltage (V)

Input Voltage (V)

Figure 14. Ground Pin Current vs. Input Voltage


600

100

500

80

400 300 200 100

Vout(nom.) = 3.3 V

1.0

2.0

3.0

4.0

5.0

10 mA 60 mA

60 10 mA

40 Vout = 1.8 V Vin = 2.8 VDC + 0.5 Vp–p Cout = 1 µF

20

0 0.1

6.0

1.0

10

f, Frequency (kHz)

Figure 16. Current Limit vs. Input Voltage

Figure 17. Ripple Rejection vs. Frequency

1000 Vout = 1.8 V Vin = 2.8 V Iout = 1 mA Cout = 1 µF

800

600

5.0 4.0 3.0 200 Vin = 3.8 V to 4.8 V Vout = 3.3 V Cout = 1.0 µF Iout = 1.0 mA

150 Output Voltage Deviation (mV)

400 200

0 0.01

100

Input Voltage (V)

Vin, Input Voltage (V)

0 0

Vin,Voltage Noise (nV/ǠHZ)

150

25

RR, Ripple Rejection (dB)

Current Limit (mA)

0 0

175

0.1

1.0

10

100

1000

100 50 0 –50

0

20

40

60

80

100

120

140

f, Frequency (kHz)

Time (µs)




160

5.0

Iout, Output Current (mA)


NCP500

4.0 3.0

100 50 0 –50 20

40

60

80

100

120

140

Iout, Output Current (mA)

0

100 0 –100 –200 0

10

20

30

40

50

Time (µs)

Time (µs)



225 Vin = 3.8 V Vout = 3.3 V Cout = 10 µF Cin = 1 µF

150 75 0 50

60

3.0 Vin = 3.8 V Vout = 3.3 V TA = 25°C RL = 3.3 kΩ Cin = 1 µF

2.0 1.0 0 4.0

Output Voltage (V)

Output Voltage Deviation (mV)

75

–300

160

Enable Voltage (V)

0

Vin = 3.8 V Vout = 3.3 V Cout = 1.0 µF Cin = 1 µF

150

200

Vin = 3.8 V to 4.8 V Vout = 3.3 V Cout = 1.0 µF Iout = 10 mA

150



200

225

25 0 –25 –50 0

10

20

30

40

50

60

70

80

90

3.0 2.0

Cout = 10 µF

1.0

Cout = 1.0 µF

0 0

20

40

60

80

100

Time (µs)

Time (ms)


Figure 23. Turn–off Response


120

NCP500 2

3 2.5 Vout, Output Voltage (V)

1.6 1.4 1.2 1 0.8 Cin = 1 µF Cout = 1 µF TA = 25°C VEnable = Vin

0.6 0.4 0.2 0

2 1.5 Cin = 1 µF Cout = 1 µF TA = 25°C VEnable = Vin

1 0.5 0

0

1

2

3

5

4

6

0

1

2

3

4

5





3.5 3 Vout, Output Voltage (V)


1.8

2.5 2 1.5 Cin = 1 µF Cout = 1 µF TA = 25°C VEnable = Vin

1 0.5 0

0

1

2

3

4

5

6




7

6


Line Regulation

The change in output voltage for a change in output load current at a constant temperature.


Dropout Voltage

The input/output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. Measured when the output drops 2% below its nominal. The junction temperature, load current, and minimum input supply requirements affect the dropout level.



are expressed in VRMS or nV ǸHz.


Quiescent Current



This is the integrated value of the output noise over a specified frequency range. Input voltage and output load current are kept constant during the measurement. Results

The power dissipation level at which the junction temperature reaches its maximum operating value, i.e. 125°C.

The current which flows through the ground pin when the regulator operates without a load on its output: internal IC operation, bias, etc. When the LDO becomes loaded, this term is called the Ground current. It is actually the difference between the input current (measured through the LDO input pin) and the output current.


NCP500 APPLICATIONS INFORMATION The NCP500 series regulators are protected with internal thermal shutdown and internal current limit. A typical application circuit is shown in Figure 27.

If TJ is not recommended to exceed 125°C, then the NCP500 can dissipate up to 400 mW @ 25°C. The power dissipated by the NCP500 can be calculated from the following equation:





If a 150 mA output current is needed the ground current is extracted from the data sheet curves: 200 µA @ 150 mA. For a NCP500SN18T1 (1.8 V), the maximum input voltage will then be 4.4 V, good for a 1 Cell Li–ion battery.


The NCP500 is a stable component and does not require a minimum Equivalent Series Resistance (ESR) or a minimum output current. The minimum decoupling value is 1.0 µF and can be augmented to fulfill stringent load transient requirements. The regulator accepts ceramic chip capacitors as well as tantalum devices. Larger values improve noise rejection and load regulation transient response. Figure 29 shows the stability region for a range of operating conditions and ESR values.

Hints


Noise Decoupling

The NCP500 is a low noise regulator without the need of an external bypass capacitor. It typically reaches a noise level of 50 µVRMS overall noise between 10 Hz and 100 kHz. The classical bypass capacitor impacts the start up phase of standard LDOs. However, thanks to its low noise architecture, the NCP500 operates without a bypass element and thus offers a typical 20 µs start up phase.

Package Placement

QFN packages can be placed using standard pick and place equipment with an accuracy of "0.05 mm. Component pick and place systems are composed of a vision system that recognizes and positions the component and a mechanical system which physically performs the pick and place operation. Two commonly used types of vision systems are: (1) a vision system that locates a package silhouette and (2) a vision system that locates individual bumps on the interconnect pattern. The latter type renders more accurate place but tends to be more expensive and time consuming. Both methods are acceptable since the parts align due to a self–centering feature of the QFN solder joint during solder re–flow.

Enable Operation

The enable pin will turn on or off the regulator. These limits of threshold are covered in the electrical specification section of this data sheet. The turn–on/turn–off transient voltage being supplied to the enable pin should exceed a slew rate of 10 mV/µs to ensure correct operation. If the enable is not to be used then the pin should be connected to Vin.

Solder Paste

Type 3 or Type 4 solder paste is acceptable.

Thermal

As power across the NCP500 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and the ambient temperature effect the rate of junction temperature rise for the part. This is stating that when the NCP500 has good thermal conductivity through the PCB, the junction temperature will be relatively low with high power dissipation applications. The maximum dissipation the package can handle is given by:

Re–flow and Cleaning

The QFN may be assembled using standard IR/IR convection SMT re–flow processes without any special considerations. As with other packages, the thermal profile for specific board locations must be determined. Nitrogen purge is recommended during solder for no–clean fluxes. The QFN is qualified for up to three re–flow cycles at 235°C peak (J–STD–020). The actual temperature of the QFN is a function of: • Component density • Component location on the board • Size of surrounding components



NCP500 ON OFF Battery or Unregulated Voltage

1

6

2

5

3

4

Vout C1

1

*

5 *

2 ON

3


C2

4

Vout + C1

+ C2

OFF



10 Cout = 1 µF to 10 µF TA = 40°C to 125°C Vin = up to 6.0 V

Output Capacitor ESR (Ω)

UNSTABLE

1

STABLE 0.1

0.01

0

25

50

75

100

125

150

IO, Output Current (mA)

Figure 29. Stability

Input

Input

Q1

R1

Q1

R2 R

Output 1 1.0 µF

R3

5

Output 1

1.0 µF

2 3

Q2

1.0 µF

4

5 1.0 µF

2 3

4






Output 5

1 1.0 µF

1.0 µF

2 Enable 3

4

1

5

Output 1.0 µF

1.0 µF 2 3

R

4

C


Input

Enable Voltage (V)

NCP500 4 3 TA = 25°C Vin = 3.4 V Vout = 2.8 V

2 1 0 3 2.5

No Delay

2 1.5

R = 1.0 MΩ C = 1.0 µF

R = 1.0 MΩ C = 0.1 µF

1 0.5 0

10

0

20

30

40

50

60

70

80

90 100 110

Time (ms)



If a delayed turn–on is needed during power up of several voltages then the above schematic can be used. Resistor R, and capacitor C, will delay the turn–on of the bottom regulator. A few values were chosen and the resulting delay can be seen in Figure 33.

The graph shows the delay between the enable signal and output turn–on for various resistor and capacitor values.

Input

Output

Q1 R

1 1.0 µF

5 1.0 µF

2 3

4

5.6 V

Figure 34. Input Voltages Greater than 6.0 V A regulated output can be achieved with input voltages that exceed the 6.0 V maximum rating of the NCP500 series with the addition of a simple pre–regulator circuit. Care must be taken to prevent Q1 from overheating when the regulated output (Vout) is shorted to Gnd.




0.094 2.4

0.037 0.95 0.074 1.9 0.037 0.95 0.028 0.7 0.039 1.0

inches mm


0.4 mm (min)

0.65 mm

0.65 mm

0.5 mm (min)

1.9 mm

QFN 2x2


NCP500 ORDERING INFORMATION Nominal Output Voltage

Marking

Package

NCP500SN18T1 NCP500SN25T1 NCP500SN27T1 NCP500SN28T1 NCP500SN30T1 NCP500SN33T1 NCP500SN50T1

1.8 2.5 2.7 2.8 3.0 3.3 5.0

LCS LCT LCU LCV LCW LCX LCY

TSOP–5 TSOP 5

NCP500SQL18T1 NCP500SQL25T1 NCP500SQL27T1 NCP500SQL28T1 NCP500SQL30T1 NCP500SQL33T1 NCP500SQL50T1

1.8 2.5 2.7 2.8 3.0 3.3 5.0

LED LEE LEF LEG LEH LEJ LEK

QFN 2x2

Device

3000 Units/ 7″ Tape & Reel

For availability of other output voltages, please contact your local ON Semiconductor Sales Representative.


Shipping

"- $ " % 01 %() The NCP511 series of fixed output low dropout linear regulators are designed for handheld communication equipment and portable battery powered applications which require low quiescent current. The NCP511 series features an ultra–low quiescent current of 40 µA. Each device contains a voltage reference unit, an error amplifier, a PMOS power transistor, resistors for setting output voltage, current limit, and temperature limit protection circuits. The NCP511 has been designed to be used with low cost ceramic capacitors and requires a minimum output capacitor of 1.0 µF. The device is housed in the micro–miniature TSOP–5 surface mount package. Standard voltage versions are 1.5, 1.8, 2.5, 2.7, 2.8, 3.0, 3.3, and 5.0 V. Other voltages are available in 100 mV steps. Features

Low Quiescent Current of 40 µA Typical Low Dropout Voltage of 100 mV at 100 mA Excellent Line and Load Regulation Maximum Operating Voltage of 6.0 V Low Output Voltage Option High Accuracy Output Voltage of 2.0% Industrial Temperature Range of –40°C to 85°C

1 TSOP–5 SN SUFFIX CASE 483

PIN CONNECTIONS AND MARKING DIAGRAM Vin

1

Gnd

2

Enable

3

5

Vout

4

N/C

xxx = Version Y = Year W = Work Week


• • • •

5

555KJ

• • • • • • •

http://onsemi.com

Cellular Phones Battery Powered Instruments Hand–Held Instruments Camcorders and Cameras

(Top View)


Vin

Vout 1

5 Thermal Shutdown


Enable ON

3

OFF

Gnd

2




July, 2001 – Rev. 2

476


NCP511

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin No.

Pin Name

1

Vin


Description

2

Gnd


3

Enable


4

N/C


5

Vout


MAXIMUM RATINGS


Symbol

Value

Unit

Vin

0 to 6.0

V

Enable Voltage

Enable

–0.3 to Vin +0.3

V

Output Voltage

Vout

–0.3 to Vin +0.3

V


PD RθJA


W °C/W

Input Voltage


TJ

+125

°C


TA

–40 to +85

°C

Storage Temperature

Tstg

–55 to +150

°C

Tsolder

10

sec





Symbol

Output Voltage (TA = 25°C, Iout = 1.0 mA) 1.5 V 1.8 V 2.5 V 2.7 V 2.8 V 3.0 V 3.3 V 5.0 V

Vout

Output Voltage (TA = –40°C to 85°C, Iout = 1.0 mA) 1.5 V 1.8 V 2.5 V 2.7 V 2.8 V 3.0 V 3.3 V 5.0 V

Vout

Min

Typ

Max

1.455 1.746 2.425 2.646 2.744 2.94 3.234 4.900

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

1.545 1.854 2.575 2.754 2.856 3.06 3.366 5.100

1.455 1.746 2.425 2.619 2.716 2.910 3.201 4.900

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

1.545 1.854 2.575 2.781 2.884 3.09 3.399 5.100

Unit V

V

Line Regulation (Vin = Vout + 1.0 V to 6.0 V, Iout = 10 mA)

Regline

–

1.0

3.5

mV/V


Regload

–

0.3

0.8

mV/mA

Output Current (Vin = Vout + 1.0 V, Vout = Vout(nom) – 0.1 V)

Io(nom.)

150

–

–

mA

Dropout Voltage (Iout = 100 mA, Measured at Vout –3.0%) 1.5 V 1.8 V 2.5 V 2.7 V 2.8 V 3.0 V 3.3 V 5.0 V

Vin–Vout – – – – – – – –

245 160 110 100 100 100 90 75

350 200 200 200 200 200 200 200

– –

0.1 40

1.0 100

–

"100

–

1.3 –

– –

– 0.3

200

400

800


IQ


TC


mV

µA

Vth(en)

Output Short Circuit Current (Vin = Vout(nom) + 1.0 V, Vout = 0 V)

ppm/°C V

Iout(max)

mA

Ripple Rejection (f = 1.0 kHz, Io = 60 mA)

RR

–

50

–

dB

Output Noise Voltage (f = 20 Hz to 100 kHz, Iout = 60 mA)

Vn

–

110

–

µVrms



NCP511 3.5


180


Vout(nom.) = 3.0 V Iout = 150 mA

160 140 120

Iout = 100 mA

100 80 Iout = 50 mA

60 40

Iout = 1 mA

Iout = 10 mA

20 0 –60 –40 –20

20

40

60

80

2.0 Vout(nom.) = 3.0 V IO = 0 mA Cin = 1.0 µF Cout = 1.0 µF TA = 25°C Venable = Vin

1.5 1.0 0.5

100 120 140

0

1

2

3

4

5

6

TEMPERATURE (°C)




7

GROUND PIN CURRENT (µA)

45

45 40 35 30 Vin = Vout(nom.) + 0.5 V Vout(nom.) = 3.0 V IO = 0 mA

25 20 –50

43 41 39 37 35 33 31 Vout(nom.) = 3.0 V Vin = 5.0 V TA = 25°C

29 27 25

–25

0

25

50

75

100

0

125

25

50

75

100

125

TEMPERATURE (°C)



Figure 5. Ground Pin Current vs. Output Current

45

450

40

400

35

350

30 25 20 15 10


5

CURRENT LIMIT (mA)

IQ, QUIESCENT CURRENT (µA)

2.5

0 0

50

GROUND PIN CURRENT (µA)

3.0

300 250 200 150 100 Vout(nom.) = 3.0 V Cin = 1.0 µF

50

0

150

0 0

1

2

3

4

5

0

6

1

2

3

4

5




Figure 7. Current Limit vs. Input Voltage


6

NCP511 Vin, INPUT VOLTAGE (V)


5 4 3

4 3 100

Vin = 3.5 V to 4.5 V Vout = 3.0 V Cout = 1 µF Iout = 1 mA

40 20



60

5

0 –20 –40

50 0 –50 –100

20

100 200 300 400 500 600 700 800 900

40

60

100 120 140 160 180




80

TIME (µs)

TIME (µs)

5 4 3 150 Cout = 1 µF Iout = 150 mA

100 OUTPUT VOLTAGE DEVIATION (mV)

Cout = 1 F Iout = 100 mA

Vin = 3.5 V to 4.5 V Vout = 3.0 V

50 0 –50 –100

Vin = 3.5 V to 4.5 V Vout = 3.0 V

–150 –200 20

40

60

80 100 120 140 160 180 TIME (µs)

150 Vin = 3.5 V Vout = 3.0 V Cin = 1 µF Cout = 10 µF Iout = 1 mA to 150 mA




Vin = 3.5 V Vout = 3.0 V 0


0 OUTPUT VOLTAGE DEVIATION (mV)

150

20 10 0 –10 200 400 600

800 1000 1200 1400 1600 1800

200 100

Cin = 1 µF Cout = 1 µF IO = 1 mA to 150 mA

0 –100 –200

200 400 600 800 1000 1200 1400 1600 1800

TIME (µs)

TIME (µs)




ENABLE VOLTAGE (V)

NCP511

2 1 0

Vin = 3.5 V Vout = 3.0 V TA = 25°C Iout = 1 mA Cin = 1 µF


4 3 Cout = 10 µF

Cout = 1 µF

2 1 0 20

40

60

80

100 120 140 160 180

TIME (µs)


70 Vout = 1.5 V Vin = 2.5 V Iout = 60 mA Cout = 2.2 µF

1.4 1.2

RR, RIPPLE REJECTION (dB)

OUTPUT NOISE DENSITY (µV/ǠHZ)

1.6

1.0 0.8 0.6 0.4 0.2 0 0.01

0.1

1.0

10

100

1000

Vout = 3.0 V Vin = 3.5 VDC 0.25 V Iout = 60 mA Cout = 1.0 µF

60 50 40 30 20 10 0 100

1k

10 k

100 k

f, FREQUENCY (kHz)

f, FREQUENCY (Hz)




1M


Line Regulation



Dropout Voltage

















The NCP511 is a stable Regulator and does not require any specific Equivalent Series Resistance (ESR) or a minimum output current. Capacitors exhibiting ESRs ranging from a few mΩ up to 3.0 Ω can thus safely be used. The minimum decoupling value is 1.0 µF and can be augmented to fulfill stringent load transient requirements. The regulator accepts ceramic chip capacitors as well as tantalum devices. Larger values improve noise rejection and load regulation transient response.



Enable Operation


The enable pin will turn on or off the regulator. These limits of threshold are covered in the electrical specification section of this data sheet. If the enable is not used then the pin should be connected to Vin.


If a 150 mA output current is needed then the ground current from the data sheet is 40 µA. For an NCP511SN30T1 (3.0 V), the maximum input voltage will then be 5.6 V.

Hints

Please be sure the Vin and Gnd lines are sufficiently wide. When the impedance of these lines is high, there is a chance to pick up noise or cause the regulator to malfunction. Set external components, especially the output capacitor, as close as possible to the circuit, and make leads a short as possible.


Vout C1

*

1

5 *

2 ON

3

C2

ESR, OUTPUT CAPACITOR (Ω)

100 UNSTABLE 10

0.1

0.01

4

Cout = 1 µF to 10 µF TA = 25°C to 125°C Vin = up to 6.0 V

1

STABLE

0

OFF

25

50

75

100

125

IO, OUTPUT CURRENT (mA)


Figure 17. Output Capacitor vs. Output Current


150

NCP511 APPLICATION CIRCUITS

Input

R1

Input

Q1

Q1

R2 R

Output

R3

1.0 µF

3

1.0 µF

3


Output 5

1.0 µF

1.0 µF

2 Enable


Enable Voltage (V)

Input

4 3

1

1.0 µF 2 3

4

C


5

1 1.0 µF

TA = 25°C Vin = 3.5 V Vout = 3.0 V

2

4 Output

4



3

1.0 µF

2

4

1

5

1

2

R

Output

5

1 1.0 µF

Q2

0 3

R = 1.0 MΩ C = 0.1 µF

1 0

R = 1.0 MΩ C = 1.0 µF

No Delay

2

20

0

60

40

80

100

120

140

160

Time (ms)


Figure 21. Delayed Turn–on The graph shows the delay between the enable signal and output turn–on for various resistor and capacitor values.

If a delayed turn–on is needed during power up of several voltages then the above schematic can be used. Resistor R, and capacitor C, will delay the turn–on of the bottom regulator. A few values were chosen and the resulting delay can be seen in Figure 21. Input

Output

Q1 R

1 1.0 µF

5 1.0 µF

2 3

4

5.6 V

Figure 22. Input Voltages Greater than 6.0 V A regulated output can be achieved with input voltages that exceed the 6.0 V maximum rating of the NCP511 series with the addition of a simple pre–regulator circuit. Care must be taken to prevent Q1 from overheating when the regulated output (Vout) is shorted to Gnd.




0.094 2.4

0.037 0.95 0.074 1.9 0.037 0.95 0.028 0.7 0.039 1.0

TSOP–5 (Footprint Compatible with SOT–23–5)


inches mm

NCP511 ORDERING INFORMATION Device NCP511SN15T1 NCP511SN18T1 NCP511SN25T1 NCP511SN27T1 NCP511SN28T1 NCP511SN30T1 NCP511SN33T1 NCP511SN50T1


Marking

Package

Shipping

1.5 1.8 2.5 2.7 2.8 3.0 3.3 5.0

LBU LBV LBW LBX LBY LBZ LCA LCB

TSOP–5




"-./& ) + ) The NCP5426 series of fixed output, 150 mA low dropout linear regulators are designed to be an economical solution for a variety of applications. Each device contains a voltage reference unit, an error amplifier, a PNP power transistor, resistors for setting output voltage, an under voltage lockout on the input, an enable pin, and current limit and temperature limit protection circuits. The NCP5426 is designed for driving a vibration motor using ceramic capacitors on the output. The device is housed in the micro–miniature TSOP–5 surface mount package. The NCP5426 is available in output voltages of 1.2 to 2.0 volts in 0.1 volt increments.

http://onsemi.com


Features

• • • • • •

PIN CONNECTIONS AND MARKING DIAGRAM Enable

1

Gnd

2

N/C

3


• Vibration Motor Driver

5

Vin

4

Vout

555KJ

Wide Operating Voltage Range to 12 Volts Internally Set Output Voltages Enable Pin for On/Off Control UVLO on the Input Voltage with Hysteresis Current and Thermal Protection Compatible with Ceramic, Tantalum or Aluminum Electrolytic Capacitors

xxx = Version Y = Year W = Work Week Vin

Vout 4

5

(Top View)

UVLO Thermal Shutdown



Enable ON

1

OFF

Gnd

2


Figure 1. Internal Schematic



487


NCP5426

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DETAILED PIN DESCRIPTION Pin

Name

1

Enable

Description

2

GND

Ground pin.

3

N/C

This pin is not connected to the device.

4

Vout


5

Vin

Input voltage.

The enable pin allows the user to control the output. A low signal disables the output and places the device into a low current standby mode.

MAXIMUM RATINGS

Rating

Symbol

Value

Unit

VMAX

12

V

Power Dissipation to Air

PA

150

mW

Power Dissipation, Board Mounted

P

600

mW

Operating and Storage Temperature

TA

–40 to 85

°C

Thermal Resistance

TJA

300

°C/W


TJ

125

°C

Max Voltage, All Pins

ELECTRICAL CHARACTERISTICS (TA = 25°C, for min/max values TA is the operating junction temperature that applies, VCC = 3.5 V, unless otherwise noted.) Characteristic

Symbol

Min

Typ

Max

Unit

VCC

–

–

12

V

Operating Voltage Operating Voltage Turn On, Iout = 30 mA, Increasing VCC

VCCON

–

2.6

2.8

V

Operating Voltage Turn Off, Iout = 30 mA, Decreasing VCC

VCCOFF

2.0

2.1

2.2

V

Operating Voltage Hysteresis, Iout = 30 mA

VCC(hyst)

400

500

600

mV

ICC

–

120

240

µA

ICC(uvlo)

–

80

160

µA

ICC(off)

–

–

0.1

µA

Maximum Output Current, Vout = 0.95 *Vnom

Iout(max)

150

–

–

mA

Over Current Protection, Vout = 0 V

Iout(limit)

–

270

–

mA

Load Regulation, Vin = 3.5 V, Iout 1.0 to 100 mA

Regload

–

30

60

mV

Line Regulation, Iout = 30 mA, Vin 3.0 to 5.0 V

Regline

–

10

20

mV

Ripple Rejection, Vin 3.5 V, f 120 Hz, Vpp 1.0 V, Iout 30 mA

RR

55

70

–

dB

Temperature Shutdown

Tstd

–

150

–

°C

VCC H to L/T

–

200

–

ppm/°C

Vo/T

–

100

–

ppm/°C

Enable Pin High Threshold

Veh

1.6

–

–

V

Enable Pin Low Threshold

Vel

–

–

0.4

V

Enable Pin Current, Ve = 1.6 V

le

–

5.0

10

µA

Vout

1.261

1.3

1.339

V

Operating Current No Load Operating Current, VCC = 1.8 V, Enable High Operating Current, Enable Low

VCC Low Detector Temperature Coefficient, Iout = 30 mA, T = –40 to 85°C Vout Temperature Coefficient

–1.3 Volt Output Voltage, Iout = 30 mA


NCP5426 20

1.4 Vin = 3.5 V Ve = 2.5 V Vout = 1.3 V Cout = 1.0 F

12 8


LOAD REGULATION (mV)

16

4 0 –4 –8 –12

1.0 0.8 0.6 0.4 0.2

–16 –20 0

25

50

100

75

0

150

0

50

100

150

200

250

OUTPUT CURRENT (mA)

Figure 2. Load Regulation NCP5426

Figure 3. Current Limit NCP5426

136 134

300

2.7

Vin = 3.5 V Iout = 0 mA Vout(nom) = 1.3 V Ve = Vin

2.6 Vth ON 2.5

132 UVLO (V)

QUIESCENT CURRENT (A)

125

OUTPUT CURRENT (mA)

140 138

130 128 126 124

2.4 2.3 2.2

122 2.1

120

Vth OFF –25

0

25

75

50

100

125

2.0 –50

10

60

125

TEMPERATURE (°C)

TEMPERATURE (°C)


Figure 5. Undervoltage Lockout vs. Temperature

90 Vin = 3.5 V Vout = 1.3 V Iout = 1.0 mA Cout = 1.0 µF Ve = 2.5 V

80 70 60 50


118 –50

50

0 Iout = 1 mA to 150 mA

40 Iout, OUTPUT CURRENT (mA)

RIPPLE REJECTION (dB)

Vin = 3.5 V Ve = 2.5 V Vout(nom) = 1.3 V

30 20 10 0 100

1k

10 k

100 k

1M

150 Vin = 3.5 V Vout = 1.3 V Cin = 4.7 µF Cout = 4.7 µF 0 100 200 300 400 500 600

700 800 900 1000

FREQUENCY (Hz)

TIME (µs)




NCP5426 7.00

ENABLE CURRENT (µA)

ENABLE CURRENT (µA)

4.00

3.75

3.50

3.25

3.00 –50

Vin = 3.5 V Ve = 1.6 V Iout = 30 mA –25

0

50

100

75

125

6.75

6.50

6.25

Vin = 3.5 V Ve = 2.5 V Iout = 30 mA

6.00 –50

50

75

100

125

TEMPERATURE (°C)

TEMPERATURE (°C)

Figure 8. Enable Current vs. Temperature

Figure 9. Enable Current vs. Temperature

0.90

Vin = 3.5 V Vout = 1.3 V 50 s/div

0.80 LINE REGULATION (mV)

0

–25

0.70

1.3 V Vout

0.60 0.50

0

0.40

100 mA

0.30

Iout

0.20

Vout = 1.3 V Iout = 30 mA Cout = 1 µF

0.10

0

0 3

6

9

12 Cin = Cout = 4.7 F

Vin (V)

Figure 10. Line Regulation

Figure 11. Resistive Transient Response for Switching the Enable Pin, Rout – 13 Ohms

Vin = 3.5 V Vout = 1.3 V 100 ms/div

1.3 V Vout 0

50 mA Iout 0 mA

Cin = Cout = 4.7 F

Figure 12. Transient Response for Switching the Enable Pin, Vibration Motor Load



Line Regulation

The change in output voltage for a change in output load current at a constant temperature and input voltage.


Dropout Voltage




This is the integrated value of the output noise over a specified frequency range. Input voltage and output load current are kept constant during the measurement. Results are expressed in VRMS or nV√Hz.


Quiescent Current


The current which flows through the ground pin when the regulator operates without a load on its output: internal IC operation, bias, etc. When the LDO becomes loaded, this term is called the Ground current. It is actually the difference between the input current (measured through the LDO input pin) and the output current.

The power dissipation level at which the junction temperature reaches its maximum operating value, i.e. 125°C.



NCP5426 APPLICATIONS INFORMATION The maximum dissipation the package can handle is given by:

The following description will assist the system designer to correctly use the NCP5426 in an application. The NCP5426 is designed specifically for use with inductive loads, typically Vibration Motors. The LDO is capable of using ceramic and tantalum capacitors. Please refer to Figure 13 for a typical system schematic.


TJ is not recommended to exceed 125°C. The NCP5426 can dissipate up to 400 mW @ 25°C. The power dissipated by the NCP5426 can be calculated from the following equation:

Input Decoupling

A capacitor, C1, is necessary on the input for normal operation. A ceramic or tantalum capacitor with a minimum value of 1.0 µF is required. Higher values of capacitance and lower ESR will improve the overall line and load transient response.



Output Decoupling

If a 150 mA output current is needed then the ground current is extracted from the data sheet curves: 200 A @ 150 mA. For an NCP5426SN18T1 (1.8 V), the maximum input voltage will then be 4.4 V, good for a 1 Cell Li–ion battery.

A capacitor, C2, is required for the NCP5426 to operate normally. A ceramic or tantalum capacitor will suffice. The selection of the output capacitor is dependant upon several factors: output current, power up and down delays, inductive kickback during power up and down. It is recommended the output capacitor be as close to the output pin and ground pin for the best system response.

Hints


Enable Pin

The enable pin will turn on or off the regulator. The enable pin is active high. The internal input resistance of the enable pin is high which will keep the current very low when the pin is pulled high. A low threshold voltage permits the NCP5426 to operate directly from microprocessors or controllers.

ON OFF

Thermal

Enable

As power across the NCP5426 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material and the ambient temperature effect the rate of junction temperature rise for the part. This is stating that when the NCP5426 has good thermal conductivity through the PCB, the junction temperature will be relatively low with high power dissipation applications.

VCC

Vin

Gnd N/C

Vibration Motor

C1

Vout C2

Figure 13. Typical Applications Circuit for Driving a Vibration Motor

VCCON VCCOFF

Vout Resistive Load

Vout Motor Load

Figure 14. Timing Diagram


VCCHYST

VCC



0.094 2.4

0.037 0.95 0.074 1.9 0.037 0.95 0.028 0.7 0.039 1.0



inches mm

NCP5426 ORDERING INFORMATION Nominal Output Voltage*

Marking

Package

Shipping

NCP5426SN13T1

1.3

LDZ

TSOP–5

NCP5426SN13T2

1.3

LDZ

TSOP–5

3000 Units/ 7″ Tape & Reel

Device

*Contact your ON Semiconductor sales representative for other Output Voltage options.

TAPE DIMENSIONS mm

4.00 Ğ1.50 TYP

4.00 2.00

1.75

3.50 $0.50

8.00 $0.30

Ğ1.00 MIN

DIRECTION OF FEED

Figure 15. T1 Reel Configuration/Orientation

TAPE DIMENSIONS mm

4.00 Ğ1.50 TYP

4.00 2.00

1.75

3.50 $0.50

8.00 $0.30

Ğ1.00 MIN

DIRECTION OF FEED

Figure 16. T2 Reel Configuration/Orientation


"##/ % /$$ % ) 5 8 + ) The CS8182 is a monolithic integrated low dropout tracking regulator designed to provide adjustable buffered output voltage that closely tracks (±10 mV) the reference input. The output delivers up to 200 mA while being able to be configured higher, lower or equal to the reference voltages. The output has been designed to operate over a wide range (2.8 V to 45 V) while still maintaining excellent DC characteristics. The CS8182 is protected from reverse battery, short circuit and thermal runaway conditions. The device also can withstand 45 V load dump transients and –50 V reverse polarity input voltage transients. This makes it suitable for use in automotive environments. The VREF/ENABLE lead serves two purposes. It is used to provide the input voltage as a reference for the output and it also can be pulled low to place the device in sleep mode where it nominally draws less than 30 µA from the supply. Features • 200 mA Source Capability • Output Tracks within ±10 mV Worst Case • Low Dropout (0.35 V typ. @ 200 mA) • Low Quiescent Current • Thermal Shutdown • Short Circuit Protection • Wide Operating Range • Internally Fused Leads in SO–8 Package

http://onsemi.com

8 1 SO–8 DF SUFFIX CASE 751

1 5 D2PAK 5–PIN DPS SUFFIX CASE 936A

PIN CONNECTIONS AND MARKING DIAGRAMS 1 8182 ALYW

VOUT GND GND Adj

VIN GND GND VREF/ENABLE Tab GND Pin 1. VIN 2. VOUT 3. GND 4. Adj 5. VREF

CS8182 AWLYWW

VIN

VOUT ESD

1

Current Limit & SAT Sense Adj

– ENABLE

ESD

+


VREF/ENABLE

ORDERING INFORMATION*

ESD + GND Thermal Shutdown

A WL, L YY, Y WW, W

– 2.0 V

Device

Package

CS8182YDF8

SO–8

95 Units/Rail

CS8182YDFR8

SO–8

2500 Tape & Reel

CS8182YDPS5

D2PAK 5–PIN

50 Units/Rail

CS8182YDPSR5 D2PAK 5–PIN


750 Tape & Reel

* Consult your local sales representative for SO–8 with exposed pads package option.



Shipping

495



Value

Unit

Storage Temperature

–65 to 150

°C

Supply Voltage Range (continuous)

–15 to 45

V

Supply Voltage Range (normal, continuous)

3.4 to 45

V

45

V

–10 to 45

V


150

°C

Package Thermal Resistance, SO–8: Junction–to–Case, RθJC Junction–to–Ambient, RθJA

45 165

°C/W °C/W

4.0 10–50**

°C/W °C/W

2.0

kV

230 peak

°C

Peak Transient Voltage (VIN = 14 V, Load Dump Transient = 31 V) Voltage Range (Adj, VOUT, VREF/ENABLE)

Package Thermal Resistance, D2PAK, 5–Pin: Junction–to–Case, RθJC Junction–to–Ambient, RθJA ESD Capability (Human Body Model) Lead Temperature Soldering:

Reflow: (SMD styles only) (Note 1)

1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. **Depending on thermal properties of substrate. RθJA = RθJC + RθCA


CS8182 ELECTRICAL CHARACTERISTICS (VIN = 14 V; VREF/ENABLE > 2.75 V; –40°C < TJ < +125°C; COUT ≥ 10µF; 0.1 Ω < COUT–ESR < 1.0 Ω @ 10 kHz, unless otherwise specified.) Test Conditions

Parameter

Min

Typ

Max

Unit

–10 –5.0

– –

10 5

mV mV

Regular Output VREF – VOUT VOUT Tracking Error

4.5 V ≤ VIN ≤ 26 V, 100 µA ≤ IOUT ≤ 200 mA, Note 2 VIN = 12 V, IOUT = 30 mA, VREF = 5.0 V, Note 2


IOUT = 100 µA IOUT = 30 mA IOUT = 200 mA

– – –

100 – 350

150 500 600

mV mV mV

Line Regulation

4.5 V ≤ VIN ≤ 26 V, Note 2

–

–

10

mV

Load Regulation

100 µA ≤ IOUT ≤ 200 mA, Note 2

–

–

10

mV

Adj Lead Current

Loop in Regulation

–

0.2

1.0

µA

Current Limit

VIN = 14 V, VREF = 5.0 V, VOUT = 90% of VREF, Note 2

225

–

700

mA

Quiescent Current (IIN – IOUT)

VIN = 12 V, IOUT = 200 mA VIN = 12 V, IOUT = 100 µA VIN = 12 V, VREF/ENABLE = 0 V

– – –

15 75 30

25 150 55

mA µA µA

Reverse Current

VOUT = 5.0 V, VIN = 0 V

–

0.2

1.5

mA

Ripple Rejection

f = 120 Hz, IOUT = 200 mA, 4.5 V ≤ VIN ≤ 26 V

60

–

–

dB

Thermal Shutdown

GBD

150

180

210

°C

0.80

2.00

2.75

V

–

0.2

1.0

µA

VREF/ENABLE –

Enable Voltage Input Bias Current

VREF/ENABLE

2. VOUT connected to Adj lead.

PACKAGE PIN DESCRIPTION Package Lead Number SO–8

D2PAK 5–PIN

Lead Symbol

8

1

VIN

1

2

VOUT

Regulated output.

2, 3, 6, 7

3

GND

Ground.

4

4

Adj

5

5

VREF/ENABLE


Function Input voltage.

Adjust lead. Reference voltage and ENABLE input.

CS8182 CIRCUIT DESCRIPTION ENABLE Function

Output Voltage

By pulling the VREF/ENABLE lead below 2.0 V typically, (see Figure 5 or Figure 6), the IC is disabled and enters a sleep state where the device draws less than 55 µA from supply. When the VREF/ENABLE lead is greater than 2.75 V, VOUT tracks the VREF/ENABLE lead normally.

The output is capable of supplying 200 mA to the load while configured as a similiar (Figure 2), lower (Figure 4), or higher (Figure 3) voltage as the reference lead. The Adj lead acts as the inverting terminal of the op amp and the VREF lead as the non–inverting. The device can also be configured as a high–side driver as displayed in Figure 7.

GND GND

RA

Adj

VOUT, 200 mA B+

VIN CS8182

VREF

Figure 3. Tracking Regulator at Higher Voltages

Figure 2. Tracking Regulator at the Same Voltage

GND

GND

R VOUT + VREF(1 ) E) RA

VOUT + VREF

VOUT, 200 mA Loads VOUT C2** GND 10 µF

GND

C1* 1.0 µF

VREF/ ENABLE

Adj

5.0 V

VREF/ ENABLE

Adj

B+

VIN CS8182

C1* 1.0 µF

C2** 10 µF

C1* 1.0 µF

GND

VOUT GND GND

GND R1 R2

GND

C1* 1.0 µF

GND R

VREF/ ENABLE

Adj

VREF

VREF/ ENABLE

B+

VIN CS8182

GND

VOUT, 200 mA Loads VOUT C2** GND 10 µF RF GND

B+

VIN CS8182


VREF

from MCU

VOUT + VREF( R2 ) R1 ) R2

Figure 4. Tracking Regulator at Lower Voltages

CS8101

VREF (5.0 V)

200 mA

100 nF 5.0 V

GND

GND GND Adj

GND

VIN CS8182

VOUT

To Load 10 µF (e.g. sensor)

VOUT

GND

C1* 1.0 µF

µC

GND

VREF/ ENABLE

Adj

VIN CS8182

VIN

6.0 V–40 V

Figure 5. Tracking Regulator with ENABLE Circuit

GND GND

VREF/ ENABLE

VOUT + B ) * VSAT

I/O

Figure 6. Alternative ENABLE Circuit

Figure 7. High–Side Driver

* C1 is required if the regulator is far from the power source filter. ** C2 is required for stability.


B+

MCU

CS8182 APPLICATION NOTES Switched Application

where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current, for the application,and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated:

The CS8182 has been designed for use in systems where the reference voltage on the VREF/ENABLE pin is continuously on. Typically, the current into the VREF/ENABLE pin will be less than 1.0 µA when the voltage on the VIN pin (usually the ignition line) has been switched out (VIN can be at high impedance or at ground.) Reference Figure 8.

VOUT

VIN

GND

GND

GND Adj

CS8182

C2 10 µF

RJA + 150°C * TA PD

Ignition Switch

VOUT

The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heat sink will be required.

VBAT

C1 1.0 µF

GND

VREF/ ENABLE

< 1.0 µA

0 1

VREF 5.0 V

Figure 8.

IIN VIN

SMART REGULATOR

IOUT VOUT

External Capacitors

The output capacitor for the CS8182 is required for stability. Without it, the regulator output will oscillate. Actual size and type may vary depending upon the application load and temperature range. Capacitor effective series resistance (ESR) is also a factor in the IC stability. Worst–case is determined at the minimum ambient temperature and maximum load expected. The output capacitor can be increased in size to any desired value above the minimum. One possible purpose of this would be to maintain the output voltage during brief conditions of negative input transients that might be characteristic of a particular system. The capacitor must also be rated at all ambient temperatures expected in the system. To maintain regulator stability down to –40°C, a capacitor rated at that temperature must be used. More information on capacitor selection for SMART REGULATORs is available in the SMART REGULATOR application note, “Compensation for Linear Regulators,” document number SR003AN/D, available through the Literature Distribution Center or via our website at http://www.onsemi.com.

Control Features

IQ

Figure 9. Single Output Regulator with Key Performance Parameters Labeled Heatsinks



Calculating Power Dissipation in a Single Output Linear Regulator

The maximum power dissipation for a single output regulator (Figure 9) is:

RΘJC appears in the package section of the data sheet. Like RΘJA, it is a function of package type. RΘCS and RΘSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.

PD(max) + {VIN(max) * VOUT(min)} IOUT(max) ) VIN(max)IQ

0-1

01


"

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The MC33565 Low Drop Out Voltage Regulator is designed for computer peripheral card applications, allowing glitch–free transitions from “sleep” to “active” system modes. It has internal logic circuitry to detect whether there is a 5 V supply (“active” system mode) or an auxiliary 3.3 V supply (“sleep” system mode). A guaranteed 3.3 V regulated output voltage at 200 mA is always available even if the main 5 V supply drops out. The regulated 3.3 V output voltage is provided by either an internal dropout 5.0 V–to–3.3 V voltage regulator or an external P–channel MOSFET, depending on the system being in the “active” or “sleep” mode.

http://onsemi.com

200 mA INTELLIGENT LDO REGULATOR WITH SMART BYPASS CONTROL

Features

• • • • • •

Glitch–Free Transition from “Sleep” to “Active” Mode Compatible with Instantly Available PC Systems Output Current up to 200 mA Output Regulated to 2% over Temperature Excellent Line and Load Regulation (0.4%) Prevents Reverse Current Flow during Sleep Mode

MARKING DIAGRAM SOIC–8 D SUFFIX CASE 751

8 1

Applications

A L Y W

• Computer • Ethernet • PCI/NIC Cards Simplified Block Diagram

*--

X C2%JC%2>"):C0%2>F1

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4.35

4.25 4.20 4.15 4.10 4.05 4.00

–5

25 TA, TEMPERATURE (°C)

0.0152 0.0150 0.0148 0.0146 0.0144 0.0142 0.0140 0.0138 0.0136

140

+5 Vin = 5 V +3.3 Vin = 3.3 V IDrive out = 200 µA

0.0154

–5

Figure 10. Drive Out High Voltage (external P–channel MOSFET turned off) versus Ambient Temperature

39.5

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24.0 23.5 23.0 22.5 22.0

Drive out set to 1 V

21.5 21.0 20.5

–5


38.5 38.0 37.5 Drive out set to 2.3 V

37.0 36.5 36.0 35.5 35.0

140

+5 Vin = 4.3 V

39.0

–5

Figure 12. Drive Out Peak Sink Current versus Ambient Temperature

3.304 Vin = 4.3 V


140

Figure 13. Drive Out Peak Source Current versus Ambient Temperature

2.5

Iout = 200 µA

+5 Vin = 5.5 – 4.3 V Vout = 3.3 V Iout = 200 mA

3.302 2.0 2'@:C:)D2">'%@C01

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Figure 11. Drive Out Low Voltage (external P–channel MOSFET turned on) versus Ambient Temperature

24.5

20.0 19.5


3.300 Vin = 5.5 V 3.298 Vin = 5 V 3.296 3.294

1.5

1.0

0.5 3.292 3.290

–5


140

0

–5

Figure 14. Output Voltage versus Ambient Temperature


Figure 15. Line Regulation versus Ambient Temperature


140

MC33565 8.4 +5 Vin = 5 V Vout = 3.3 V Iout = 0 – 200 mA

2.0

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430 420 410 400 390 380 370

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140


140

Figure 19. Short Circuit Current versus Ambient Temperature

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PLASTIC D SUFFIX CASE 751




511


MC33275 MAXIMUM RATINGS (TA = 25°C, for min/max values TJ = –40°C to +125°C) Rating

Symbol

Value

Unit

VCC

13

Vdc

PD

Internally Limited

W

RθJA RθJC

160 25

°C/W °C/W

RθJA RθJC

92 6.0

°C/W °C/W

RθJA RθJC

245 15

°C/W °C/W

Output Current

IO

300

mA


TJ

150

°C


TJ

– 40 to +125

°C


Tstg

– 65 to +150

°C

Input Voltage Power Dissipation and Thermal Characteristics TA = 25°C Maximum Power Dissipation Case 751 (SOP–8) D Suffix Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case Case 369A (DPAK) DT Suffix Thermal Resistance, Junction–to–Air Thermal Resistance, Junction–to–Case Case 318E (SOT–223) ST Suffix Thermal Resistance, Junction–to–Air Thermal Resistance, Junction–to–Case

ELECTRICAL CHARACTERISTICS (CL = 1.0µF, TA = 25°C, for min/max values TJ = –40°C to +125°C, Note 1) Symbol

Characteristic Output Voltage 2.5 V Suffix 3.0 V Suffix 3.3 V Suffix 5.0 V Suffix

IO = 0 mA to 250 mA TA = 25°C, Vin = [VO + 1] V

Min

Typ

Max

2.475 2.970 3.267 4.950

2.50 3.00 3.30 5.00

2.525 3.030 3.333 5.05

2.450 2.940 3.234 4.900

— — — —

2.550 3.060 3.366 5.100

VO

Unit Vdc

2.5 V Suffix 3.0 V Suffix 3.3 V Suffix 5.0 V Suffix

Vin = [VO + 1] V, 0 < IO < 100 mA 2% Tolerance from TJ = –40 to +125°C

Line Regulation

Vin = [VO + 1] V to 12 V, IO = 250 mA, All Suffixes TA = 25°C

Regline

–

2.0

10

mV

Load Regulation

Vin = [VO + 1] V, IO = 0 mA to 250 mA, All Suffixes TA = 25°C

Regload

–

5.0

25

mV

— — — —

25 115 220 260

100 200 400 500

65

75

—

— —

160 46

— —

Symbol

Min

Typ

Max

Unit

—

125

200

A

— — — —

1100 1500 1500 1500

1500 2000 2000 2000

ILIMIT

—

450

—

mA

Symbol

Min

Typ

Max

Unit

—

—

150

—

°C

Dropout Voltage IO = 10 mA IO = 100 mA IO = 250 mA IO = 300 mA

Vin – VO TJ = –40°C to +125°C

Ripple Rejection (120 Hz)

Vin(peak–peak) = [VO + 1.5] V to [VO + 5.5] V

Output Noise Voltage CL = 1 F CL = 200 F

IO = 50 mA (10 Hz to 100 kHz)

—

mV

Vn

dB Vrm s

CURRENT PARAMETERS Characteristic Quiescent Current ON Mode

Vin = [VO + 1] V, IO = 0 mA

IQ

Quiescent Current ON Mode SAT 2.5 V Suffix 3.0 V Suffix 3.3 V Suffix 5.0 V Suffix

Vin = [VO – 0.5] V, IO = 0 mA, Note 2

IQ

Current Limit

Vin = [VO + 1] V, VO Shorted

A

THERMAL SHUTDOWN Characteristic Thermal Shutdown

NOTE: 1. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible. NOTE: 2. Quiescent Current is measured where the PNP pass transistor is in saturation. Vin = [VO – 0.5] V guarantees this condition.


MC33275 DEFINITIONS difference between the input power (VCC X ICC) and the output power (Vout X Iout) is increasing. Depending on ambient temperature, it is possible to calculate the maximum power dissipation and so the maximum current as following:

Load Regulation – The change in output voltage for a change in load current at constant chip temperature. Dropout Voltage – The input/output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. Measured when the output drops 100 mV below its nominal value (which is measured at 1.0 V differential), dropout voltage is affected by junction temperature, load current and minimum input supply requirements. Output Noise Voltage – The RMS AC voltage at the output with a constant load and no input ripple, measured over a specified frequency range. Maximum Power Dissipation – The maximum total dissipation for which the regulator will operate within specifications. Quiescent Current – Current which is used to operate the regulator chip and is not delivered to the load. Line Regulation – The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. Maximum Package Power Dissipation – The maximum package power dissipation is the power dissipation level at which the junction temperature reaches its maximum value i.e. 150°C. The junction temperature is rising while the

T –T Pd + J A R JA

The maximum operating junction temperature TJ is specified at 150°C, if TA = 25°C, then PD can be found. By neglecting the quiescent current, the maximum power dissipation can be expressed as: I out +

P D V – Vout CC

The thermal resistance of the whole circuit can be evaluated by deliberately activating the thermal shutdown of the circuit (by increasing the output current or raising the input voltage for example). Then you can calculate the power dissipation by subtracting the output power from the input power. All variables are then well known: power dissipation, thermal shutdown temperature (150°C for MC33275) and ambient temperature. R


T –T + J A JA P D

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MC33275–XX

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MC33275 ORDERING INFORMATION

Device

Operating Temperature Range, Tolerance

Type

MC33275DT–2.5RK 2.5 2 5V (Fixed Voltage)

MC33275ST–2.5T3 MC33275D–2.5R2 MC33275DT–3.0RK

3.0 3 0V (Fixed Voltage)

MC33275ST–3.0T3

1% T Tolerance l 25 C at TA = 25°C

MC33275D–3.0R2 MC33275DT–3.3RK 3.3 3 3V (Fixed Voltage)

MC33275ST–3.3T3

2% T Tolerance l att TJ from –40 to +125°C +125 C

MC33275D–3.3R2 MC33275DT–5.0RK 5.0 5 0V (Fixed Voltage)

MC33275ST–5.0T3 MC33275D–5.0R2

Case

Package

369A

DPAK

318E

SOT–223

751–5

SOP–8

369A

DPAK

318E

SOT–223

751–5

SOP–8

369A

DPAK

318E

SOT–223

751–5

SOP–8

369A

DPAK

318E

SOT–223

751–5

SOP–8

DEVICE MARKING Device

Version

Marking (1st line)

MC33275

2.5V

27525

MC33275

3.0V

27530

MC33275

3.3V

27533

MC33275

5.0V

27550

TAPE AND REEL SPECIFICATIONS Device

Reel Size

Tape Width

Quantity

MC33275DT

13”

16mm embossed tape

2500 units

MC33275D

13”

12mm embossed tape

2500 units

MC33275S

13”

8mm embossed tape

4000 units


"

!

$$ / % ) %* +;; " The MC33375 series are micropower low dropout voltage regulators available in a wide variety of output voltages as well as packages, SOT–223, and SOP–8 surface mount packages. These devices feature a very low quiescent current and are capable of supplying output currents up to 300 mA. Internal current and thermal limiting protection are provided by the presence of a short circuit at the output and an internal thermal shutdown circuit. The MC33375 has a control pin that allows a logic level signal to turn–off or turn–on the regulator output. Due to the low input–to–output voltage differential and bias current specifications, these devices are ideally suited for battery powered computer, consumer, and industrial equipment where an extension of useful battery life is desirable. Features: • Low Quiescent Current (0.3 A in OFF mode; 125 A in ON mode) • Low Input–to–Output Voltage Differential of 25 mV at IO = 10 mA, and 260 mV at IO = 300 mA • Extremely Tight Line and Load Regulation • Stable with Output Capacitance of only 0.33 F for 2.5 V Output Voltage • Internal Current and Thermal Limiting • Logic Level ON/OFF Control

http://onsemi.com

LOW DROPOUT MICROPOWER VOLTAGE REGULATOR ) 4

1

2

3

%@O%$$ 4 1 3

PLASTIC ST SUFFIX CASE 318E

' )

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Figure 20. Enable Response


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APPLICATIONS INFORMATION %@O%$$

MC33375–xx

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When this pin is pulled low, the MC33375 is off. This pin should not be left floating. The pin should be pulled high for the MC33375 to operate.

MC33375 ORDERING INFORMATION MC33375ST–1.8T3

1.8 V (Fixed V)

318E

SOT–223

MC33375ST–2.5T3

2.5 V (Fixed Voltage)

318E

SOT–223

751–5

SOP–8

318E

SOT–223

MC33375D–2.5R2 MC33375ST–3.0T3


MC33375D–3.0R2 MC33375ST–3.3T3

1% Tolerance at TA = 25°C


MC33375D–3.3R2 MC33375ST–5.0T3

2% Tolerance at TJ from –40 to +125°C


MC33375D–5.0R2

751–5

SOP–8

318E

SOT–223

751–5

SOP–8

318E

SOT–223

751–5

SOP–8

DEVICE MARKING Device

Version

Marking (1st line)

MC33375

1.8V

37518

MC33375

2.5V

37525

MC33375

3.0V

37530

MC33375

3.3V

37533

MC33375

5.0V

37550

TAPE AND REEL SPECIFICATIONS Device

Reel Size

Tape Width

Quantity

MC33375D

13”

12mm embossed tape

2500 units

MC33375ST

13”

8mm embossed tape

4000 units

MAXIMUM RATINGS (TA = 25°C, for min/max values TJ = –40°C to +125°C) Rating

Symbol

Value

Unit

VCC

13

Vdc

PD

Internally Limited

W

RθJA RθJC

160 25

°C/W °C/W

RθJA RθJC

245 15

°C/W °C/W

Output Current

IO

300

mA


TJ

150

°C


TJ

– 40 to +125

°C


Tstg

– 65 to +150

°C

Input Voltage Power Dissipation and Thermal Characteristics TA = 25°C Maximum Power Dissipation Case 751 (SOP–8) D Suffix Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case Case 318E (SOT–223) ST Suffix Thermal Resistance, Junction–to–Air Thermal Resistance, Junction–to–Case


"#/$ $ $$ %* 445 464 The CS8120 is a 5.0 V, 300 mA precision linear regulator with two microprocessor compatible control functions and protection circuitry included on chip. The composite NPN–PNP output pass transistor assures a lower dropout voltage (1.0 V @ 200 mA) without requiring excessive supply current (2.5 mA). The CS8120’s two logic control functions make this regulator well suited to applications requiring microprocessor–based control at the board or module level. ENABLE controls the output stage. A high voltage (> 2.9 V) on the ENABLE lead turns off the regulator’s pass transistor and sends the IC into Sleep mode where it draws only 250 µA. The RESET function sends a RESET signal when the IC is powering up or whenever the output voltage moves out of regulation. The RESET signal is valid down to VOUT = 1.0 V. The CS8120 design optimizes supply rejection by switching the internal bandgap reference from the supply input to the regulator output as soon as the nominal output voltage is achieved. Additional on chip filtering enhances rejection of high frequency transients on all external leads. The CS8120 is fault protected against short circuit, over voltage and thermal runaway conditions. Features • 5.0 V ±4.0% Output Voltage 300 mA • Low Dropout Voltage (1.0 V @ 150 mA) • Low Quiescent Current (2.5 mA @ IOUT = 150 mA) • µP Compatible Control Functions – RESET – ENABLE • Low Current Sleep Mode – IQ = 250 µA • Fault Protection – Thermal Shutdown – Short Circuit – 60 V Load Dump

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1


1

5 D2PAK 5–PIN DP SUFFIX CASE 936F

1 5

DIP–8 N SUFFIX CASE 626 8 1 SO–14 D SUFFIX CASE 751A

14 1





530


CS8120 PIN CONNECTIONS D2PAK 5–PIN

1 DIP–8 8

TO–220 5 LEAD Tab = GND Pin 1. VIN 2. ENABLE 3. GND 4. RESET 5. VOUT

1

GND

VOUT VIN

SENSE

NC

RESET

ENABLE

Pin 1. VIN 2. ENABLE 3. GND 4. RESET 5. VOUT

NC

1

SO–14

14 VOUT GND SENSE NC RESET NC NC

VIN NC NC NC ENABLE NC NC

1

VOUT VIN Over Voltage Shutdown

ENABLE

–

Output Current Limit

ENABLE Comparator – Bandgap Supply

+

Error Amplifier

Thermal Protection

VREF

Bandgap Reference

To VOUT

RESET

+

Reset Comparator + – GND

Figure 1. Block Diagram – TO–220 ABSOLUTE MAXIMUM RATINGS* Rating

Value

Unit

–0.7 to 26

V

60

V

Internally Limited

–

2.0

kV

Operating Temperature

–40 to +125

°C


–40 to +150

°C


–55 to +150

°C

260 peak 230 peak

°C °C

DC Input Voltage Load Dump Output Current Electrostatic Discharge (Human Body Model)





CS8120 ELECTRICAL CHARACTERISTICS (VIN = 14 V, IOUT = 5.0 mA; –40 ≤ TJ ≤ 150°C, –40°C ≤ TC ≤ 125°C, unless otherwise noted.) Note 3 Characteristic

Test Conditions

Min

Typ

Max

Unit


7.0 V ≤ VIN ≤ 26 V, 1.0 mA ≤ IOUT ≤ 300 mA

4.8

5.0

5.2

V

Line Regulation

7.0 V ≤ VIN ≤ 26 V, IOUT = 200 mA

–

–

50

mV

Load Regulation

1.0 mA ≤ IOUT ≤ 300 mA

–

–

50

mV

Supply Voltage Rejection

VIN = 14 VDC + 1.0 VRMS @ 120Hz LOAD = 25 Ω

40

70

–

dB

Dropout Voltage

IOUT = 200 mA

–

1.0

1.5

V

Quiescent Current

ENABLE = High, VIN = 12 V ENABLE = Low, IOUT = 200 mA

– –

0.25 2.5

0.65 15

mA mA

Output Stage

Protection Circuits Short Circuit Current

–

300

600

–

mA

Thermal Shutdown

–

150

190

–

°C


–

26

40

–

V

RESET RESET Saturation Voltage

1.0 V < VOUT < VRT(OFF), 3.1 kΩ Pull–Up to VOUT

–

0.1

0.4

V

RESET Output Leakage Current

ENABLE = Low, VOUT > VRT(ON), VRESET = VOUT

–

0

25

µA

Power ON/OFF RESET Peak Output Voltage

3.1 kΩ Pull–Up to VOUT

–

0.7

1.0

V

– 4.75

VOUT – 0.10 VOUT – 0.14

VOUT – 0.04 –

V V

10

40

–

mV

RESET Threshold HIGH (VRH) LOW (VRL)


RESET Threshold Hysteresis

–

ENABLE Input High Voltage

7.0 V < VIN < 26 V

–

2.9

3.9

V

Input Low Voltage

7.0 V < VIN < 26 V

1.1

2.1

–

V

Input Hysteresis

7.0 V < VIN < 26 V

0.4

0.8

2.8

V

Input Current

GND < VIN(HI) < VOUT

–10

0

+10

µA

3. To have safe operating junction temperatures, low duty cycle pulse testing is used on tests where applicable.


CS8120

PACKAGE LEAD DESCRIPTION PACKAGE LEAD # TO–220 5 LEAD–

DIP–8

SO–14

D2Pak 5 PIN

LEAD SYMBOL

1

2

1

1

VIN

2

4

5

2

ENABLE

3

8

13

3

GND

4

6

10

4

RESET

5

1

14

5

VOUT

N/A

7

12

–

SENSE

–

3, 5

2, 3, 4, 6, 7, 8, 9, 11

FUNCTION Supply voltage to IC, usually direct from the battery. CMOS compatible logical input. VOUT is disabled i.e. placed in a high impedance state when ENABLE is high. Ground Connection. CMOS compatible output lead. RESET goes low whenever VOUT falls out of regulation. The RESET delay is externally programmed. Regulated output voltage, 5.0 V (typ). Kelvin Connection which allows remote sensing of output voltage for improved regulation. If remote sensing is not desired, connect to VOUT.

NC

No Connection.

TYPICAL PERFORMANCE CHARACTERISTICS 5.02

0 IOUT = 100 mA 5.0 V @ 25°C

–10 Load Reg. (mV)

5.0 VOUT (V)

40°C

–5

5.01

4.99 4.98 4.97

125°C

–15

25°C

VIN = 14 V

–20 –25 –30 –35 –40

4.96

–45

4.95 –40

–50 –20

0

20

40

60

80

100

120

140

150

0

100

200

300

400

IOUT (mA)

Junction Temperature (°C)

Figure 3. Load Regulation vs. Output Current Over Temperature



500

CS8120 TYPICAL PERFORMANCE CHARACTERISTICS 50 1.4

VIN = 7 to 25 V

Dropout Voltage. (V)

Line Reg. (mV)

40 30 20

25°C 125°C

10 –40°C

0

1.2 1.0

–40°C

0.8 25°C

125°C

0.6 0.4 0.2

–10 0

50

100

150

200

250

300

350

400

450

0.0

500

0

50

100

IOUT (mA)

150

200

250

300

350

Output Current (mA)

Figure 4. Line Regulation vs. Output Current Over Temperature

Figure 5. Dropout Voltage vs. Output Current Over Temperature 5.5

3.5 VIN = 14 V

22 20

5 VOUT

4

16

VOUT (V)

25°C

2.0 125°C

1.5

3

12 IQ

2

8

1.0 4

1 0.5 0.0

0 0

50

100

150

200

300

250

350

0

2

4

Figure 7. Output Voltage and Supply Current vs. Input Voltage

Figure 6. Quiescent Current vs. Output Current Over Temperature 2000 1800 VIN = 5.0 V

1400 1200 1000 800 600 400 200 0

1

5

8

Supply Voltage (V)

Output Current (mA)

1600

6

10

15

20

25

30

35

Reset Output Current (mA)

Figure 8. RESET Output Voltage vs. Output Voltage


40

10

0

Supply Current (mA)

–40°C

2.5

Reset Output Voltage (mV)


3.0

CS8120 CIRCUIT DESCRIPTION VOLTAGE REFERENCE AND OUTPUT CIRCUITRY

circuitry and enables the IC to survive unexpected voltage transients. Using an emitter sense scheme, the amount of current through the NPN pass transistor is monitored. Feedback circuitry insures that the output current never exceeds a preset limit. Should the junction temperature of the power device exceed 180°C (typ) the power transistor is turned off. Thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the IC.

Precision Voltage Reference

The regulated output voltage depends on the precision band gap voltage reference in the IC. By adding an error amplifier into the feedback loop, the output voltage is maintained within ±4.0% over temperature and supply variation. Output Stage

The composite PNP–NPN output structure (Figure 9) provides 300 mA (typ) of output current while maintaining a low drop out voltage (1.00 V, typ) and drawing little quiescent current (2.5 mA). The NPN pass device prevents deep saturation of the output stage which in turn improves the IC’s efficiency by preventing excess current from being used and dissipated by the IC.


The CS8120 contains two microprocessor compatible control functions: ENABLE and RESET (Figure 11). ENABLE Function

VIN

The ENABLE function switches the output transistor. When the voltage on the ENABLE lead exceeds 2.9 V typ, the output pass transistor turns off, leaving a high impedance facing the load. The IC will remain in Sleep mode, drawing only 250 µA, until the voltage on the lead drops below 2.1 V typ. Hysteresis (800 mV) is built into the ENABLE function to provide good noise immunity. For 7.0 V < VIN < 26 V

VIN

VOUT

ENABLE

Figure 9. Composite Output Stage of the CS8120

VIN(H) VRH


The output stage is protected against overvoltage, short circuit and thermal runaway conditions (Figure 10).

VOUT

VRL (1) VRPEAK

> 26 V

(2)

VRPEAK

VRLO

RESET VIN

(1) = No Reset Delay Capacitor (2) = With Reset Delay Capacitor

VOUT

Figure 11. Circuit Waveform for CS8120 IOUT

RESET Function Load Dump

Short Circuit

A RESET signal (low voltage) is generated as the IC powers up (VOUT > VOUT – 100 mV) or when VOUT drops out of regulation (VOUT < VOUT – 140 mV, typ). 40 mV of hysteresis is included in the function to minimize oscillations. The RESET output is an open collector NPN transistor, controlled by a low voltage detection circuit. The circuit is

Thermal Shutdown


If the input voltage rises above 26 V (e.g. load dump), the output shuts down. This response protects the internal


CS8120 functionally independent of the rest of the IC, thereby guaranteeing that the RESET signal is valid for VOUT as low as 1.0 V. 5.0 V to µP and System Power

VOUT RRST

CS8120

An external RC network on the RESET lead (Figure 12) provides a sufficiently long delay for most microprocessor based applications. RC values can be chosen using the following formula: RTOT

C2 22 µF

ƪ

–tDelay

lnǒV

VT*VOUT RST*VOUT

Ǔ

ƫ

where: RTOT = RRST in parallel with RIN, RIN = µP port impedance, CRST = RESET delay capacitor, tDelay = desired delay time, VRST = VSAT of RESET lead (0.7 V @ turn – ON), and VT = µP logic threshold voltage.

to µP RESET Port

RESET

CRST +

CRST

Figure 12. RC Network for RESET Delay Circuitry

APPLICATION NOTES allows the microprocessor to finish key housekeeping functions before power is removed. The logic options are summarized in Table 1.

The circuit depicted in Figure 13 lets the microprocessor control its power source, the CS8120 regulator. An I/O port on the µP and the SWITCH port are used to drive the base of Q1. When Q1 is driven into saturation, the voltage on the ENABLE lead falls below its lower threshold. The regulator’s output is switched out. When the drive current is removed, the voltage on the ENABLE lead rises, the output is switched off and the IC moves into Sleep mode where it draws 250 µA. By coupling these two controls with the ENABLE, the system has added flexibility. Once the system is running, the state of the SWITCH is irrelevant as long as the I/O port continues to drive Q1. The microprocessor can turn off its own power by withdrawing drive current, once the SWITCH is open. This software control at the I/O port

Table 1. Logic Control of CS8120 Output Microprocessor I/O Drive

SWITCH

ENABLE

Output

ON

Closed

LOW

ON

Open

LOW

ON

Closed

LOW

ON

Open

HIGH

OFF

OFF


VIN

VBAT C1 0.1 µF

VOUT

CS8120

500 kΩ

ENABLE

GND

VCC C2 22µF

RRST

RESET

µP

RESET CRST

Q1 100 kΩ 500 kΩ

100 kΩ

SWITCH

Figure 13. Microprocessor Control of CS8120 Using External Switching Transistor Q1


I/O Port

CS8120 STABILITY CONSIDERATIONS

the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations.

The output or compensation capacitor, C2, helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor C2 shown in Figure 14 should work for most applications, however it is not necessarily the optimized solution. 5.0 V to µP and System Power

VIN C1 * 0.1 µF

VOUT CS8120 RESET ENABLE

RRST to µP RESET port


C2** 10 µF

CRST

*C1 is required if regulator is far from the power source filter.


**C2 is required for stability.

Figure 14. Circuit Showing Output Compensation Capacitor


To determine an acceptable value for C2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause

(1)


150°C * TA PD

(2)

The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.


CS8120 IIN VIN

IOUT

HEAT SINKS


VOUT

SMART REGULATOR Control Features

IQ


(3)




CS8120 ORDERING INFORMATION Description

Shipping


50 Units/Rail

CS8120YTVA5


50 Units/Rail

CS8120YTHA5


50 Units/Rail

DIP–8

50 Units/Rail

Device CS8120YT5

CS8120YN8 CS8120YDP5

D2PAK,

CS8120YDPR5

D2PAK, 5–Pin

5–Pin

50 Units/Rail 750 Tape & Reel

CS8120YD14

SO–14

55 Units/Rail

CS8120YDR14

SO–14

2500 Tape & Reel

MARKING DIAGRAMS TO–220 FIVE LEAD T SUFFIX CASE 314D

TO–220 FIVE LEAD TVA SUFFIX CASE 314K


DIP–8 N SUFFIX CASE 626 8

D2PAK 5–PIN DP SUFFIX CASE 936F

SO–14 D SUFFIX CASE 751A 14

CS8120

AWL YYWW CS8120 AWLYWW

CS8120 AWLYWW

CS8120 AWLYWW

CS8120

AWLYWW

CS8120

AWLYWW 1

1 1

1

1




TO–220 FIVE LEAD

D2PAK FIVE LEAD

DIP–8

SO–14

Unit

RΘJC

Typical

3.1

3.1

52

30

°C/W

RΘJA

Typical

50

10–50*

100

125

°C/W

* Depending on thermal properties of substrate. RΘJA = RΘJC + RΘCA


"/ ( $$ %* (D>C%2>"):C01

'% = # "

'% = ## "

7

'% = ## " 6 #

G87I-#@> >" = ° -#

#

8#

6#

#

7#

9 # G87I #@> X GE" = °

96

##

##

##

-##

##

6##

B '@(D> %2>"): 01

'%B %D>(D> D:@> 0"1



6#

##

BC'((2:C:E:>'%@C0I1

+%BC<%(%D>C%2>"):C01

=

9

9 #

9#

# # >" = 7#°

#-#

>" = °

# # >" = +-#°

## #

= 6#

9 7

G87I #@> X GE(D> D:@> 0"1

B $:HD:@K 0.A1


Figure 4. Ripple Rejection as a Function of Frequency


##CG

MC78BC00 Series 6#

97

96

9 +-#

G87I #@> X GED: 0°1

' % BC%D>(D>CD:@>C0"1

7#

# #

'

-# #

6#

# %

# 2 = # µ$ '% = ## " >" = ° G87I #@> X GE(D>C%2>"):C >:G(:">D: 0°1

##

##

##

%

-##

= 6# >" = ° 2 = # µ$ G87I #@> X GE'G: 0µ1

B >'G: 0µ1




%BC%D>(D>C%2>"):C $ !$ % ) %* ) = 445 The CS8122 is a precision 5.0 V linear regulator capable of sourcing in excess of 750 mA. The RESET’s delay time is externally programmed using a discrete RC network. During power up, or when the output goes out of regulation, the RESET lead remains in the low state for the duration of the delay. This function is independent of the input voltage and will function correctly as long as the output voltage remains at or above 1.0 V. Hysteresis is included in the Delay and the RESET comparators to improve noise immunity. A latching discharge circuit is used to discharge the delay capacitor when it is triggered by a brief fault condition. The regulator is protected against a variety of fault conditions: i.e. reverse battery, overvoltage, short circuit and thermal runaway conditions. The regulator is protected against voltage transients ranging from –50 V to +40 V. Short circuit current is limited to 1.2 A (typ). The CS8122 is an improved replacement for the CS8126 and features a tighter tolerance on its output voltage (2.0% vs. 4.0%). The CS8122 is packaged in a 5 lead TO–220 with copper tab. The copper tab can be connected to a heat sink if necessary.

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1

TO–220 FIVE LEAD THA SUFFIX CASE 314A 1

Features • 5.0 V ±2.0% Regulated Output • Low Dropout Voltage (0.6 V @ 0.5 A) • 750 mA Output Current Capability • Externally Programmed RESET Delay • Fault Protection – Reverse Battery – 60 V Load Dump – –50 V Reverse Transient – Short Circuit – Thermal Shutdown

5

5

PIN CONNECTIONS AND MARKING INDIAGRAM

CS8122 AWLYWW

Pin 1. VIN 2. VOUT 3. GND 4. Delay 5. RESET




Package

Shipping

CS8122YT5

TO–220* STRAIGHT

50 Units/Rail

CS8122YTVA5

TO–220* VERTICAL

50 Units/Rail

CS8122YTHA5

TO–220* HORIZONTAL

50 Units/Rail

*Five lead.  Semiconductor Components Industries, LLC, 2001


587


CS8122 VIN Over Voltage Shutdown VOUT Regulated Supply for Circuit Bias

Pre–Regulator

Bandgap Reference

– +

Charge Current Generator

Delay

Error Amplifier Anti–Saturation and Current Limit

VOUT (SENSE)

Thermal Shutdown

Latching Discharge – Q

S

+

R – + VDISC

RESET

Delay Comparator

+ –

GND

Figure 1. Block Diagram ABSOLUTE MAXIMUM RATINGS* Rating

Value

Unit

–0.5 to 26

V

Internally Limited

–

–50, 60

V

Internally Limited

–

4.0

kV


–55 to +150

°C


–55 to +150

°C

260 peak

°C

Input Operating Range Power Dissipation Peak Transient Voltage (46 V Load Dump @ VIN = 14 V) Output Current Electrostatic Discharge (Human Body Model)


Wave Solder (through hole styles only) (Note 1)

1. 10 second maximum. *The maximum package power dissipation must be observed.


CS8122 ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ 125°C, –40 ≤ TJ ≤ 150°C, 6.0 ≤ VIN ≤ 26 V, 5.0 mA ≤ IOUT ≤ 500 mA, RRESET = 4.7 kΩ to VCC unless otherwise noted.) Note 2 Characteristic

Test Conditions

Min

Typ

Max

Unit

–

4.9

5.0

5.1

V

Output Stage (VOUT) Output Voltage Dropout Voltage

IOUT = 500 mA

–

0.35

0.60

V

Supply Current

IOUT ≤ 10 mA IOUT ≤ 100 mA IOUT ≤ 500 mA

– – –

2.0 6.0 55

7.0 12 100

mA mA mA

Line Regulation

6.0 V ≤ VIN ≤ 26 V, IOUT = 50 mA

–

5.0

50

mV

Load Regulation

50 mA ≤ IOUT ≤ 500 mA, VIN = 14 V

–

10

50

mV

Ripple Rejection

f = 120 Hz, 7.0 ≤ VIN ≤ 17 V, IOUT = 250 mA

54

75

–

dB

Current Limit

–

0.75

1.20

–

A


–

32

–

40

V

Maximum Line Transient

VOUT ≤ 5.5 V

60

95

–

V

Reverse Polarity Input Voltage DC

VOUT ≥ –0.6 V, 10 Ω Load

–15

–30

–

V

Reverse Polarity Input Voltage Transient

1.0% Duty Cycle, T < 100 ms, 10 Ω Load

–50

–80

–

V

Thermal Shutdown

Guaranteed by Design

150

180

210

°C

Delay Charge Current

VDELAY = 2.0 V

5.0

10

15

µA

RESET Threshold

VOUT Increasing, VRT(ON) VOUT Decreasing, VRT(OFF)

4.65 4.50

4.90 4.70

VOUT – 0.01 VOUT – 0.16

V V

RESET Hysteresis

VRH = VRT(ON) – VRT(OFF)

150

200

250

mV

Delay Threshold

Charge, VDC(HI) Discharge, VDC(L)

3.25 2.85

3.50 3.10

3.75 3.35

V V

200

400

800

mV

RESET and Delay Functions

Delay Hysteresis

–

RESET Output Voltage Low

1.0 V < VOUT < VRT(L), 3.0 kΩ to VOUT

–

0.1

0.4

V

RESET Output Leakage

VOUT > VRT(H)

0

–

10

µA

Delay Capacitor Discharge Voltage

Discharge Latched “ON”, VOUT > VRT

–

0.2

0.5

V

Delay Time

CDELAY = 0.1 µF

16

32

48

ms

2. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable. CDelay VDelay Threshold Charge DelayTime + + CDelay 3 ICharge


CS8122


LEAD SYMBOL

1

VIN

2

VOUT

Regulated 5.0 V output.

3

GND

Ground Connection.

4

Delay

Timing capacitor for RESET function.

5

RESET

FUNCTION Unregulated supply voltage to IC.

CMOS/TTL compatible output lead. RESET goes low whenever VOUT drops below 6.0% of it’s regulated value.

TYPICAL PERFORMANCE CHARACTERISTICS 120

RLOAD = 25 Ω

45

Quiescent Current. (mA)


55 50 40 35 30

125°C

25 20 15

25°C

RLOAD = 6.67 Ω

100

10

80 60

RLOAD = 10 Ω

40 RLOAD = 25 Ω

20 –40°C

5 0

Room Temp

RLOAD = NO LOAD

0 0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

VIN (V)

4.5

4.5

4.0

4.0

3.5

3.5

3.0

125°C

2.5 2.0

8

9

10

RLOAD = 6.67 Ω

3.0

RLOAD = NO LOAD

2.5 2.0 1.5

1.5 1.0 25°C

0.5 0

7

Room Temp

5.0

VOUT (V)

VOUT (V)

5.5

RLOAD = 25 Ω

5.0

6

Figure 3. Quiescent Current vs. Input Voltage Over Load Resistance

Figure 2. Quiescent Current vs. Input Voltage Over Temperature 5.5

5

VIN (V)

0

1

2

3

1.0

–40°C

RLOAD = 10 Ω

0.5 4

5

6

7

8

9

0

10

0

1

2

3

4

5

6

7

8

9

VIN (V)

VIN (V)

Figure 4. Output Voltage vs. Input Voltage Over Temperature

Figure 5. VOUT vs. VIN Over RLOAD


10

CS8122 TYPICAL PERFORMANCE CHARACTERISTICS

100

6

80

4 VIN = 6–26 V

40 20

TEMP = 25°C TEMP = –40°C

0 –20 –40 TEMP = 125°C

–60

0 –2

–6 –8 –10 –12

–100

–14 100

200

300

400

TEMP = 25°C

–4

–80 0

TEMP = –40°C

2


Line Reg. (mV)

60

500

600

700

TEMP = 125°C VIN = 14 V 100

0

800

200

100

800

90

700

80


Dropout Voltage (mV)

900

25°C

600 500 125°C

300 –40°C

200 100 0

400

500

70

800

25°C

125°C

60 50 40 30 20

–40°C

10 0 0

100

200

300

400

500

600

700

800

0

100

200

300

800

CO = 47/68 µF

101 ESR (ohms)

60 50

Stable Region

100

10–1

COUT = 10 µF, ESR = 1.0 Ω

30

700

102

70

40

600

103

COUT = 10 µF, ESR = 1.0 & 0.1 µF, ESR = 0

80

500

Figure 9. Quiescent Current vs. Output Current

IOUT = 250 mA

90

400

Output Current (mA)

Figure 8. Dropout Voltage vs. Output Current

Rejection (dB)

700

VIN = 14 V

Output Current (mA)

CO = 47 µF

10–2

20 COUT = 10 µF, ESR = 1.0 Ω

10 0

600

Figure 7. Load Regulation vs. Output Current

Figure 6. Line Regulation vs. Output Current

400

300

Output Current (mA)

Output Current (mA)

100

101

102

103

104

105

106

CO = 68 µF

10–3

107

108

10–4

100

Frequency (Hz)

101

102

Output Current (mA)

Figure 11. Output Capacitor ESR



103

CS8122 VOUT

(1) = No Delay Capacitor (2) = With Delay Capacitor (3) = Max: RESET Voltage (1.0 V)

VRH

VRT(ON) VRT(OFF)

RESET

(1)

(3)

(2) VRL

tDELAY DELAY VDH VDC(HI) VDC(LO)

(2)

VDIS

Figure 12. RESET Circuit Waveform

CIRCUIT DESCRIPTION The CS8122 RESET function, has hysteresis on both the reset and delay comparators, a latching Delay capacitor discharge circuit, and operates down to 1.0 V. The RESET circuit output is an open collector type with ON and OFF parameters as specified. The RESET output NPN transistor is controlled by the two circuits described (see Block Diagram on page 588).

delay capacitor). The discharge current is latched ON when the output voltage is below VRT(OFF). The Delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. This feature ensures that a controlled RESET pulse is generated following detection of an error condition. The circuit allows the RESET output transistor to go to the OFF (open) state only when the voltage on the Delay lead is higher than VDC(HI).

Low Voltage Inhibit Circuit

The Low Voltage Inhibit Circuit monitors output voltage, and when output voltage is below the specified minimum, causes the RESET output transistor to be in the ON (saturation) state. When the output voltage is above the specified level, this circuit permits the RESET output transistor to go into the OFF state if allowed by the RESET Delay circuit.

VOUT

VIN CIN* 100 nF

CS8122

RRST 4.7 kΩ

RESET Delay

GND

CDelay 0.1 µF

Reset Delay Circuit

The Reset Delay Circuit provides a programmable (by external capacitor) delay on the RESET output lead. The Delay lead provides source current to the external delay capacitor only when the Low Voltage Inhibit circuit indicates that output voltage is above VRT(ON). Otherwise, the Delay lead sinks current to ground (used to discharge the

*CIN is required if regulator is far from the power source filter. **COUT is required for stability.

Figure 13. Test Circuit


COUT** 10 µF

CS8122 APPLICATION NOTES STABILITY CONSIDERATIONS


The output or compensation capacitor, COUT, helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 13 should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for COUT for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations.



(1)


150°C * TA PD

(2)


SMART REGULATOR

IOUT

Control Features IQ



VOUT

CS8122 HEAT SINKS



(3)


TO–220 FIVE LEAD

Unit

RΘJC

Typical

2.1

°C/W

RΘJA

Typical

50

°C/W


"#/& $ !$ % ) %* ) = 445 The CS8126 is a low dropout, high current 5.0 V linear regulator. It is an improved replacement for the CS8156. Improvements include higher accuracy, tighter saturation control, better supply rejection, and enhanced RESET circuitry. Familiar PNP regulator features such as reverse battery protection, overvoltage shutdown, thermal shutdown, and current limit make the CS8126 suitable for use in automotive and battery operated equipment. Additional on–chip filtering has been included to enhance rejection of high frequency transients on all external leads. An active microprocessor RESET function is included on–chip with externally programmable delay time. During power–up, or after detection of any error in the regulated output, the RESET lead will remain in the low state for the duration of the delay. Types of errors include short circuit, low input voltage, overvoltage shutdown, thermal shutdown, or others that cause the output to become unregulated. This function is independent of the input voltage and will function correctly with an output voltage as low as 1.0 V. Hysteresis is included in both the reset and Delay comparators for enhanced noise immunity. A latching discharge circuit is used to discharge the Delay capacitor, even when triggered by a relatively short fault condition. This circuit improves upon the commonly used SCR structure by providing full capacitor discharge (0.2 V type). Note: The CS8126 is lead compatible with the LM2927 and LM2926.

http://onsemi.com



1

1


Pin 1. VIN 2. VOUT 3. GND 4. Delay 5. RESET

5 TO–220 FIVE LEAD THE SUFFIX CASE 314J

1 5

Features • Low Dropout Voltage (0.6 V at 0.5 A) • 3.0% Output Accuracy • Active RESET • External RESET Delay for Reset • Protection Circuitry – Reverse Battery Protection – +60 V, –50 V Peak Transient Voltage – Short Circuit Protection – Internal Thermal Overload Protection


1 7

Pin 1. VIN 2. VOUT 3. VOUT(SENSE) 4. GND 5. Delay 6. RESET 7. NC





595


CS8126

VIN Over Voltage Shutdown

VOUT

Regulated Supply for Circuit Bias

Pre–Regulator

Bandgap Reference

Error Amp Anti–Saturation and Current Limit

– +

Internally connected on 5 Lead TO–220 VOUT(SENSE)


Thermal Shutdown

Delay


S R

–

+ Reset Comparator

+ Delay Comparator

VDischarge + – GND



RESET


Value

Unit

Internally Limited

–

–50, 60

V

Internally Limited

–


4.0

kV

Package Thermal Resistance, TO–220 5–Lead: Junction–to–Case, RθJC Junction–to–Ambient, RθJA

2.1 50

°C/W °C/W

2.1 10–50**

°C/W °C/W


–40 to +150

°C


–55 to +150

°C

260 peak 230 peak

°C °C

Power Dissipation Peak Transient Voltage (46 V Load Dump) Output Current

Package Thermal Resistance, D2PAK, 7–Pin: Junction–to–Case, RθJC Junction–to–Ambient, RθJA



1. 10 second maximum. 2. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. **Depending on thermal properties of substrate. RθJA = RθJC + RθCA.

ELECTRICAL CHARACTERISTICS (TA = –40°C to +125°C, TJ = –40°C to +150°C, VIN = 6.0 to 26 V, IO = 5.0 to 500 mA, RRESET = 4.7 kΩ to VCC, unless otherwise noted.) Characteristic

Test Conditions

Min

Typ

Max

Unit

–

4.85

5.00

5.15

V


IOUT1 = 500 mA

–

0.35

0.60

V

Supply Current

IOUT ≤ 10 mA IOUT ≤ 100 mA IOUT ≤ 500 mA

– – –

2.0 6.0 55

7.0 12 100

mA mA mA

Line Regulation

VIN = 6.0 to 26 V, IOUT = 50 mA

–

5.0

50

mV

Load Regulation

IOUT = 50 to 500 mA, VIN = 14 V

–

10

50

mV

Ripple Rejection

f = 120 Hz, VIN = 7.0 to 17 V, IOUT = 250 mA

54

75

–

dB

Current Limit

–

0.75

1.20

–

A


–

32

–

40

V

–

95

–

V

–15

–30

–

V

–

–80

–

V

150

180

210

°C

Maximum Line Transient

VOUT ≤ 5.5 V



Reverse Polarity Input Voltage Transient

1.0% Duty Cycle, T < 100 ms, 10 Ω Load

Thermal Shutdown

Note 3

3. Guaranteed By Design


CS8126

ELECTRICAL CHARACTERISTICS (continued) (TA = –40°C to +125°C, TJ = –40°C to +150°C, VIN = 6.0 to 26 V, IO = 5.0 to 500 mA, RRESET = 4.7 kΩ to VCC, unless otherwise noted.) Characteristic

Test Conditions

Min

Typ

Max

Unit

RESET and Delay Functions Delay Charge Current

VDelay = 2.0 V

5.0

10

15

µA

RESET Threshold


4.65 4.50

4.90 4.70

VOUT – 0.01 VOUT – 0.15

V V

RESET Hysteresis


150

200

250

mV

Delay Threshold

Charge, VDC(HI) Discharge, VDC(LO)

3.25 2.85

3.50 3.10

3.75 3.35

V V

200

400

800

mV

Delay Hysteresis

–


1.0 V < VOUT < VRTL, 3.0 kΩ to VOUT

–

0.1

0.4

V

RESET Output Leakage Current

VOUT > VRT(ON)

–

0

10

µA



–

0.2

0.5

V

Delay Time

CDelay = 0.1 µF*. Note 4

16

32

48

ms

* Delay Time +

CDelay

VDelayThreshold Charge + CDelay ICharge

3.2

4. Assumes Ideal Capacitor


D2PAK 7–PIN

LEAD SYMBOL

1

1

VIN

2

2

VOUT


3

4

GND

Ground connection.

4

5

Delay


5

6

RESET

–

3

VOUT(SENSE)

–

7

NC


CMOS/TTL compatible output lead. RESET goes low after detection of any error in the regulated output or during power up. Remote sensing of output voltage. No Connection.


CS8126 TYPICAL PERFORMANCE CHARACTERISTICS RLOAD = 25 Ω

Room Temp. 120 110

55 50 45 35

ICQ (mA)

ICQ (mA)

40 30

25°C

25 20 15

RLOAD = 6.67

100 90 80

125°C

70 60

RLOAD = 10

50 40 30 20

–40°C

10 5.0

RLOAD = 25

10 0

0 0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10

RLOAD = NO LOAD 0

1.0

2.0

3.0

4.0

7.0

8.0

Figure 2. ICQ vs. VIN Over Temperature

Figure 3. ICQ vs. VIN Over RLOAD

5.5

5.0

5.0

4.5

4.5

4.0

4.0

3.5

3.5

3.0

125°C

2.5 2.0

–40°C

1.5

10

9.0

10

RLOAD = NO LOAD RLOAD = 6.67

3.0 2.5 2.0 1.5

1.0

RLOAD = 10

1.0

0.5

9.0

Room Temp.

5.5

VOUT (V)

VOUT (V)

6.0

VIN (V)

RLOAD = 25 Ω

0.5

25°C

0

0 0

100

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10

0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

VIN (V)

VIN (V)

Figure 4. VOUT vs. VIN Over Temperature


6.0

VIN 6.0–26 V

80

TEMP = –40°C

4.0

40


60 Line Regulation (mV)

5.0

VIN (V)

TEMP = 25°C

20 TEMP = 40°C

0 –20 –40

TEMP = 125°C

2.0 0 –2.0 VIN = 14 V

–6.0

TEMP = 125°C

–8.0

–60

–10

–80

–12

–100

TEMP = 25°C

–4.0

–14 0

100

200

300

400

500

600

700

800

0

100

200

300

400

500

600

700

Output Current (mA)

Output Current (mA)

Figure 6. Line Regulation vs. Output Current Over Temperature

Figure 7. Load Regulation vs. Output Current Over Temperature http://onsemi.com 599

800

CS8126

900

100

800

90 25°C

700 600



TYPICAL PERFORMANCE CHARACTERISTICS (continued)

125°C

500 400 300 –40°C

200 100

80

25°C

VIN = 14 V

70

–40°C

60 50 40 30 20 10

0

0 0

100

200

300

400

500

600

700

800

0

100

200

300

600

700

Figure 8. Dropout Voltage vs. Output Current Over Temperature

Figure 9. Quiescent Current vs. Output Current Over Temperature

800

103 COUT C 10µF, mF,ESR = 1 OUT ==10 & ESR 0.1=µF, 1 &ESR 0.1 = mF, 0 ESR = 0

70

102 101 ESR (Ω)

60 50 40


30

COUT = 47/68 µF

100

Stable Region

10–1

COUT = 47 µF

10–2 20

COUT = 10 µF, ESR = 10 Ω

101

102

103

104

105

106

COUT = 68 µF

10–3

10 100

500

Output Current (mA)

80

0

400

Output Current (mA)

90

Rejection (dB)

125°C

107

10–4

108

100

101

102

Freq. (Hz)

Output Current (mA)



103

RESET CIRCUIT WAVEFORM VOUT VRT(ON) VRT(OFF)

(1) = No Delay Capacitor (2) = With Delay Capacitor (3) = Max:RESET Voltage (1.0 V)

VRH

(1)

RESET

(2)

(3)

VRL tDelay

Delay VDC(HI) VDC(LO)

VDH VDIS

(2)



CS8126 CIRCUIT DESCRIPTION The CS8126 RESET function, has hysteresis on both the Reset and Delay comparators, a latching Delay capacitor discharge circuit, and operates down to 1.0 V. The RESET circuit output is an open collector type with ON and OFF parameters as specified. The RESET output NPN transistor is controlled by the two circuits described (see Block Diagram).

voltage is above VRT(ON). Otherwise, the Delay lead sinks current to ground (used to discharge the delay capacitor). The discharge current is latched ON when the output voltage falls below VRT(OFF). The Delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. This feature ensures a controlled RESET pulse is generated following detection of an error condition. The circuit allows the RESET output transistor to go to the OFF (open) state only when the voltage on the Delay lead is higher than VDC(H1). The Delay time for the RESET function is calculated from the formula:


This circuit monitors output voltage, and when the output voltage falls below VRT(OFF), causes the RESET output transistor to be in the ON (saturation) state. When the output voltage rises above VRT(ON), this circuit permits the RESET output transistor to go into the OFF state if allowed by the RESET Delay circuit.

Delay time +

CDelay

VDelayThreshold ICharge

Delay time + CDelay

3.2

105

RESET Delay Circuit

If CDelay = 0.1 µF, Delay time (ms) = 32 ms ± 50%: i.e. 16 ms to 48 ms. The tolerance of the capacitor must be taken into account to calculate the total variation in the delay time.

This circuit provides a programmable (by external capacitor) delay on the RESET output lead. The Delay lead provides source current to the external delay capacitor only when the “Low Voltage Inhibit” circuit indicates that output

VOUT

VIN C1 * 100 nF

RRST 4.7 kΩ

CS8126 RESET

Delay Delay 0.1 µF

C2** 10 µF to 100 µF

GND



APPLICATION NOTES Stability Considerations

temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor C2 shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for C2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part.

The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR, can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low


CS8126 VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current, for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated:

Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations.

RJA +

(2)


IOUT

SMART REGULATOR

VOUT

Control Features

IQ


Heat Sinks




(3)

where: RΘJC = the junction–to–case thermal resistance, RΘCS = the case–to–heatsink thermal resistance, and RΘSA = the heatsink–to–ambient thermal resistance. RΘJC appears in the package section of the data sheet. Like RΘJA, it is a function of package type. RΘCS and RΘSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.

Calculating Power Dissipation in a Single Output Linear Regulator


150°C * TA PD

(1)

where:


CS8126 ORDERING INFORMATION Description

Shipping


50 Units/Rail

CS8126–1YTVA5


50 Units/Rail

CS8126–1YTHA5


50 Units/Rail

CS8126–1YTHE5

TO–220 FIVE LEAD SURFACE MOUNT

50 Units/Rail

CS8126–1YTHER5

Device CS8126–1YT5

TO–220 FIVE LEAD SURFACE MOUNT

750 Tape & Reel

CS8126–1YDPS7

D2PAK, 7–PIN

50 Units/Rail

CS8126–1YDPSR7

D2PAK,

7–PIN

750 Tape & Reel

MARKING DIAGRAMS TO–220 FIVE LEAD T SUFFIX CASE 314D



TO–220 FIVE LEAD THE SUFFIX CASE 314J


CS8126 AWLYWW CS8126 AWLYWW

CS8126 AWLYWW

CS8126 AWLYWW

CS8126 AWLYWW

1 1

1


1



"#/2 $ !$ % ) %* % 445 5* * The CS8129 is a precision 5.0 V linear regulator capable of sourcing 750 mA. The RESET threshold voltage has been lowered to 4.2 V so that the regulator can be used with 4.0 V microprocessors. The lower RESET threshold also permits operation under low battery conditions (5.5 V plus a diode). The RESET’s delay time is externally programmed using a discrete RC network. During power up, or when the output goes out of regulation, RESET remains in the low state for the duration of the delay. This function is independent of the input voltage and will function correctly as long as the output voltage remains at or above 1.0 V. Hysteresis is included in the Delay and the RESET comparators to improve noise immunity. A latching discharge circuit is used to discharge the delay capacitor when it is triggered by a brief fault condition. The regulator is protected against a variety of fault conditions: i.e. reverse battery, overvoltage, short circuit and thermal runaway conditions. The regulator is protected against voltage transients ranging from –50 V to +40 V. Short circuit current is limited to 1.2 A (typ). The CS8129 is packaged in a 5 lead TO–220 and a 16 lead surface mount package.

http://onsemi.com



1

1

Features • 5.0 V ±3.0% Regulated Output • Low Dropout Voltage (0.6 V @ 0.5 A) • 750 mA Output Current Capability • Reduced RESET Threshold for use with 4.0 V Microprocessors • Externally Programmed RESET Delay • Fault Protection – Reverse Battery – 60 V, –50 V Peak Transient Voltage – Short Circuit – Thermal Shutdown

5


SO–16L DW SUFFIX CASE 751G

16 1


Package

Shipping

CS8129YT5

TO–220* STRAIGHT

50 Units/Rail

CS8129YTHA5

TO–220* VERTICAL

50 Units/Rail

CS8129YTVA5


50 Units/Rail

CS8129YDW16

SO–16L

46 Units/Rail

CS8129YDWR16

SO–16L

1000 Tape & Reel

*Five lead.




604


CS8129 PIN CONNECTIONS

TO–220 5 LEAD

1

SO–16L

VIN NC NC GND GND RESET NC Delay

Pin 1. VIN 2. RESET 3. GND 4. Delay 5. VOUT

16 VOUT NC VOUT(SENSE) GND GND GND NC NC

1

VIN Over Voltage Shutdown VOUT Regulated Supply for Circuit Bias

Pre–Regulator

Bandgap Reference

– +


Delay

Error Amplifier Anti–Saturation and Current Limit

VOUT (SENSE)

Thermal Shutdown


S

+

R – + VDISCHARGE

RESET

Delay Comparator

+ –

GND

Figure 1. Block Diagram ABSOLUTE MAXIMUM RATINGS* Rating Input Operating Range Power Dissipation Peak Transient Voltage (46 V Load Dump @ 14 V VIN) Output Current

Value

Unit

–0.5 to 26

V

Internally Limited

–

–50, 60

V

Internally Limited

–

4.0

kV


–55 to +150

°C


–55 to +150

°C

260 peak 230 peak

°C

Electrostatic Discharge (Human Body Model)



1. 10 second maximum. 2. 60 seconds max above 183°C. *The maximum package power dissipation must be observed.


CS8129 ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ 125°C, –40 ≤ TJ ≤ 150°C, 6.0 ≤ VIN ≤ 26 V, 5.0 mA ≤ IOUT ≤ 500 mA, RRESET = 4.7 kΩ to VOUT unless otherwise noted.) Note 3 Characteristic

Test Conditions

Min

Typ

Max

Unit

–

4.85

5.0

5.15

V


IOUT = 500 mA

–

0.35

0.60

V

Supply Current

IOUT = 10 mA IOUT = 100 mA IOUT = 500 mA

– – –

2.0 6.0 55

7.0 12 100

mA mA mA

Line Regulation

6.0 V ≤ VIN ≤ 26 V, IOUT = 50 mA

–

5.0

50

mV

Load Regulation

50 mA ≤ IOUT ≤ 500 mA, VIN = 14 V

–

10

50

mV

Ripple Rejection

f = 120 Hz, VIN = 7.0 to 17 V, IOUT = 250 mA

54

75

–

dB

Current Limit

–

0.75

1.20

–

A


–

32

–

40

V



–15

–30

–

V

Thermal Shutdown


150

180

210

°C


VDELAY = 2.0 V

5.0

10

15

µA

RESET Threshold


4.05 4.00

4.35 4.20

4.50 4.45

V V

RESET Hysteresis


50

150

250

mV

Delay Threshold

Charge, VDC(HI) Discharge, VDC(LO)

3.25 2.85

3.50 3.10

3.75 3.35

V V

200

400

800

mV

RESET and Delay Functions

Delay Hysteresis

–


1.0 V < VOUT < VRT(L), 3.0 kΩ to VOUT

–

0.1

0.4

V

RESET Output Leakage

VOUT > VRT(H) Current

–

0

10

µA



–

0.2

0.5

V

Delay Time

CDELAY = 0.1 µF, Note 4

16

32

48

ms

3. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable. 4. Assuming ideal capacitor. DelayTime +

CDelay

VDelay Threshold Charge + CDelay ICharge

3


CS8129

PACKAGE LEAD DESCRIPTION PACKAGE LEAD # SO–16L

TO–220 5 LEAD

LEAD SYMBOL

1

1

VIN

16

5

VOUT


4, 5, 11, 12, 13

3

GND

Ground Connection.

8

4

Delay


6

2

RESET

14

N/A

VOUT(SENSE)


CMOS/TTL compatible output lead. RESET goes low whenever VOUT drops below 6.0% of it’s regulated value. Remote sensing of output voltage.

TYPICAL PERFORMANCE CHARACTERISTICS 55 50

120

RLOAD = 25 Ω

Room Temp RLOAD = 6.67 Ω

100

45 35 30

ICQ. (mA)

ICQ (mA)

40

125°C

25 20

60

RLOAD = 10 Ω

40

15

25°C

10

RLOAD = 25 Ω

20 –40°C

5 0

80

RLOAD = NO LOAD

0 0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

VIN (V)

4.5

4.5

4.0

4.0

3.5

3.5

3.0

125°C

2.5 2.0

8

9

10

RLOAD = 6.67 Ω

3.0

RLOAD = NO LOAD

2.5 2.0 1.5

1.5 1.0

1.0

–40°C 25°C

0.5 0

7

Room Temp

5.0

VOUT (V)

VOUT (V)

5.5

RLOAD = 25 Ω

5.0

6

Figure 3. Quiescent Current vs. Input Voltage Over Load Resistance

Figure 2. Quiescent Current vs. Input Voltage Over Temperature 5.5

5

VIN (V)

0

1

2

3

RLOAD = 10 Ω

0.5 4

5

6

7

8

9

0

10

0

1

2

3

4

5

6

7

8

VIN (V)

VIN (V)

Figure 4. Output Voltage vs. Input Voltage Over Temperature



9

10

CS8129 TYPICAL PERFORMANCE CHARACTERISTICS

100

100

VIN = 6–26 V

80

80

40


Line Reg. (mV)

60 TEMP = 25°C

20

TEMP = –40°C

0 –20 –40 TEMP = 125°C

–60

40 20

TEMP = 25°C

0 VIN = 14 V

–20 –40 –60

TEMP = 125°C

–80

–80

–100

–100 0

100

200

300

400

500

600

700

0

800

200

300

400

500

800


800

90

700

80

25°C

600 500 125°C

400 300

–40°C

200 100

VIN = 14 V

70

25°C

125°C

60 50 40 30 20

–40°C

10 0 0

100

200

300

400

500

600

700

800

0

100

200

300

IOUT = 250 mA

800

CO = 47/68 µF

101 ESR (ohms)

60 50

Stable Region

100

10–1


30

700

102

70

40

600

103

COUT = 10 µF, ESR = 1.0 & 0.1 µF, ESR = 0

80

500

Figure 9. Quiescent Current vs. Output Current

Figure 8. Dropout Voltage vs. Output Current 90

400

Output Current (mA)

Output Current (mA)

Rejection (dB)

700

Figure 6. Line Regulation vs. Output Current 100

CO = 47 µF

10–2

20 COUT = 10 µF, ESR = 1.0 Ω

10 0

600

Output Current (mA)

900

0

100

Output Current (mA)



TEMP = –40°C

60

100

101

102

103

104

105

106

CO = 68 µF

10–3

107

108

10–4

100

Frequency (Hz)

101

102

Output Current (mA)




103

CS8129 VOUT

(1) = No Delay Capacitor (2) = With Delay Capacitor (3) = Max: RESET Voltage (1.0 V)

VRH

VRT(ON) VRT(OFF)

RESET

(1)

(3)

(2) VRL

tDELAY DELAY VDH VDC(HI) VDC(LO)

(2)

VDIS


CIRCUIT DESCRIPTION The CS8129 RESET function has hysteresis on both the reset and delay comparators, a latching Delay capacitor discharge circuit, and operates down to 1.0 V. The RESET circuit output is an open collector type with ON and OFF parameters as specified. The RESET output NPN transistor is controlled by the two circuits described (see Block Diagram on page 605).

condition. The circuit allows the RESET output transistor to go to the OFF (open) state only when the voltage on the Delay lead is higher than VDC(HI). VOUT

VIN CIN* 100 nF

RRST 4.7 kΩ

CS8129

COUT** 10 µF to 100 µF

RESET


Delay

This circuit monitors output voltage, and when output voltage is below the specified minimum causes the RESET output transistor to be in the ON (saturation) state. When the output voltage is above the specified level, this circuit permits the RESET output transistor to go into the OFF state if allowed by the RESET Delay circuit.

GND

Delay 0.1 µF

*CIN is required if regulator is far from the power source filter. **COUT is required for stability.

Reset Delay Circuit

Figure 13. Test & Application Circuit

This circuit provides a programmable (by external capacitor) delay on the RESET output lead. The Delay lead provides source current to the external delay capacitor only when the “Low Voltage Inhibit” circuit indicates that output voltage is above VRT(ON). Otherwise, the Delay lead sinks current to ground (used to discharge the delay capacitor). The discharge current is latched ON when the output voltage is below VRT(OFF). The Delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. This feature ensures that a controlled RESET pulse is generated following detection of an error

The Delay time for the RESET function is calculated from the formula: Delay time +

CDelay

VDelay Threshold ICharge

Delay time + CDelay(F)

3.2

105

If CDelay = 0.1 µF, Delay time (ms) = 32 ms ±50%: i.e. 16 ms to 48 ms. The tolerance of the capacitor must be taken into account to calculate the total variation in the delay time.


CS8129 APPLICATION NOTES STABILITY CONSIDERATIONS


The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 13 should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for COUT for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations.



(1)


150°C * TA PD

(2)


SMART REGULATOR

IOUT

Control Features IQ



VOUT

CS8129 HEAT SINKS



(3)

MARKING DIAGRAMS

TO–220 FIVE LEAD

SO–16L 16 CS8129 AWLYYWW

CS8129 AWLYWW

1




TO–220 FIVE LEAD

SO–16L

Unit

RΘJC

Typical

2.1

23

°C/W

RΘJA

Typical

50

105

°C/W


!" #$ %$"# The MC34268 is a medium current, low dropout positive voltage regulator specifically designed for use in SCSI–2 active termination circuits. This device offers the circuit designer an economical solution for precision voltage regulation, while keeping power losses to a minimum. The regulator consists of a 1.0 V dropout composite PNP/NPN pass transistor, current limiting, and thermal limiting. These devices are packaged in the 8–pin SOP–8 and 3–pin DPAK and SOT–223 surface mount power packages. Applications include active SCSI–2 terminators and post regulation of switching power supplies.

• • • • • • • •

http://onsemi.com MARKING DIAGRAMS 8 SOP–8 D SUFFIX CASE 751

8 1

1 A L Y W

2.85 V Output Voltage for SCSI–2 Active Termination 1.0 V Dropout Output Current in Excess of 800 mA Thermal Protection Short Circuit Protection Output Trimmed to 1.4% Tolerance No Minimum Load Required Space Saving DPAK, SOT–223 and SOP–8 Surface Mount Power Packages


!"#


34268 ALYWW


AYW 268ST

1

Simplified Block Diagram

34268 ALYW

3

1 3

( ) ) ) )

!"# $%& % ' %" % % "# % ( )




612


MC34268 MAXIMUM RATINGS Rating Power Supply Input Voltage Power Dissipation and Thermal Characteristics DT Suffix, Plastic Package, Case 369A TA = 25°C, Derate Above TA = 25°C Thermal Resistance, Junction–to–Case Thermal Resistance, Junction–to–Air D Suffix, Plastic Package, Case 751 TA = 25°C, Derate Above TA = 25°C Thermal Resistance, Junction–to–Case Thermal Resistance, Junction–to–Air ST Suffix, Plastic Package, Case 318E TA = 25°C, Derate Above TA = 25°C Thermal Resistance, Junction–to–Case Thermal Resistance, Junction–to–Air Operating Junction Temperature Range Storage Temperature

Symbol

Value

Unit

Vin

15

V

PD RθJC RθJA

Internally Limted 5.0 87

W °C/W °C/W

PD RθJC RθJA


W °C/W °C/W

PD RθJC RθJA


W °C/W °C/W

TJ

0 to +150

°C

Tstg

– 55 to +150

°C

ELECTRICAL CHARACTERISTICS (Vin = 4.25 V, CO = 10 µF, for typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, unless otherwise noted.) Characteristic

Symbol

Min

Typ

Max

Unit

VO

2.81 2.76

2.85 2.85

2.89 2.93

V

Line Regulation (Vin = 4.25 V to 15 V, IO = 0 mA, TJ = 25°C)

Regline

—

—

0.3

%

Load Regulation (IO = 0 mA to 800 mA, TJ = 25°C)

Regload

—

—

0.5

%

Dropout Voltage (IO = 490 mA)

Vin – VO

—

0.95

1.1

V

Output Voltage (TJ = 25°C, IO = 0 mA) Output Voltage, over Line, Load, and Temperature (Vin = 3.9 V to 15 V, IO = 0 mA to 490 mA)

Ripple Rejection (f = 120 Hz)

RR

55

—

—

dB

Maximum Output Current (Vin = 5.0 V)

I(max)

800

—

—

mA

Bias Current (Vin = 4.25 V, IO = 0 mA)

IB

—

5.0 to 3.0

8.0

mA

IL(min)

—

—

0

mA

! 0! *3-.(+3! ,/3!#

) 4 5 ° ) ) 1)2 1) 1)

1

11

11

11

11

* +(+ ,- +../ ,#

111

*3+(+3+../ ∆ ! *3+(+3! ,/3-/!,

Minimum Load Current to maintain Regulation (Vin = 15 V)

Figure 1. Dropout Voltage versus Output Load Current

! 5 )1 ! 5 1 µ7 , 5 °

1 %6-!

Figure 2. Transient Load Regulation


MC34268 !

)1! 2

: 88 .

1

1Ω

!

1

88 9%

Figure 3. Typical SCSI Application

The MC34268 requires an external 10 µF capacitor with an ESR of less than 10 Ω for stability over temperature. With economical electrolytic capacitors, cold temperature operation can pose a stability problem. As temperature decreases, the capacitance also decreases and the ESR increases, which could cause the circuit to oscillate. Tantalum capacitors may be a better choice if small size is a requirement. Also, the capacitance and ESR of a tantalum capacitor is more stable over temperature.

1

θ 4, *3$/.:, 3./88,/34+;;,.3336

1

)1 =

1

1 1 1

1

Figure 4. SOP–8 Thermal Resistance versus P.C.B. Copper Length

1

1 1

* /$ 7 ((/.

#

Figure 5. DPAK Thermal Resistance versus P.C.B. Copper Length


Package

Shipping Information

MC34268D

SO–8

98 Units / Rail

MC34268DR2

SO–8


MC34268DT

DPAK

75 Units / Rail

MC34268DTRK

DPAK


MC34268STT3

SOT–223



1

! http://onsemi.com

The NCP1117 series are low dropout positive voltage regulators that are capable of providing an output current that is in excess of 1.0 A with a maximum dropout voltage of 1.2 V at 800 mA over temperature. This series contains eight fixed output voltages of 1.5 V, 1.8 V, 2.0 V, 2.5 V, 2.85 V, 3.3 V, 5.0 V, and 12 V that have no minimum load requirement to maintain regulation. Also included is an adjustable output version that can be programmed from 1.25 V to 18.8 V with two external resistors. On chip trimming adjusts the reference/output voltage to within ±1.0% accuracy. Internal protection features consist of output current limiting, safe operating area compensation, and thermal shutdown. The NCP1117 series can operate with up to 20 V input. Devices are available in SOT–223 and DPAK packages.

Tab

SOT–223 ST SUFFIX CASE 318H

1 123

3

(Top View) Pin: 1. Adjust/Ground 2. Output 3. Input Heatsink tab is connected to pin 2. Tab

Features

• Output Current in Excess of 1.0 A • 1.2 V Maximum Dropout Voltage at 800 mA Over Temperature • Fixed Output Voltages of 1.5 V, 1.8 V, 2.0 V, 2.5 V, 2.85 V, 3.3 V, • • • • •

1

5.0 V, and 12 V Adjustable Output Voltage Option No Minimum Load Requirement for Fixed Voltage Output Devices Reference/Output Voltage Trimmed to ±1.0% Current Limit, Safe Operating and Thermal Shutdown Protection Operation to 20 V Input



Applications

• • • • •

2 1 3 (Top View)

3


Consumer and Industrial Equipment Point of Regulation Active SCSI Termination for 2.85 V Version Switching Power Supply Post Regulation Hard Drive Controllers Battery Chargers TYPICAL APPLICATIONS 110 W

Input 10 mF

3 +

NCP1117 XTXX

Input

3

10 mF

+

2 Output + 10

1

NCP1117 XTA

10 mF

+ 10

mF

1

4.75 V to 5.25 V

mF

Figure 1. Fixed Output Regulator

3

2 Output


+

+

NCP1117 XT285 1

110 W

2 + 22

mF

110 W

18 to 27 Lines

110 W

Figure 3. Active SCSI Bus Terminator

This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.  Semiconductor Components Industries, LLC, 2001


615


NCP1117 MAXIMUM RATINGS Rating

Symbol

Value

Unit

Vin

20

V

–

Infinite

–

PD RqJA RqJC


W °C/W °C/W

PD RqJA RqJC


W °C/W °C/W


TJ

–55 to 150

°C


Tstg

–65 to 150

°C

Input Voltage (Note 1) Output Short Circuit Duration (Notes 2 and 3) Power Dissipation and Thermal Characteristics Case 318H (SOT–223) Power Dissipation (Note 2) Thermal Resistance, Junction–to–Ambient, Minimum Size Pad Thermal Resistance, Junction–to–Case Case 369A (DPAK) Power Dissipation (Note 2) Thermal Resistance, Junction–to–Ambient, Minimum Size Pad Thermal Resistance, Junction–to–Case

1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL–STD–883, Method 3015. Machine Model Method 200 V. 2. Internal thermal shutdown protection limits the die temperature to approximately 175°C. Proper heatsinking is required to prevent activation. The maximum package power dissipation is: PD +

TJ(max) * TA RqJA

3. The regulator output current must not exceed 1.0 A with Vin greater than 12 V.

ELECTRICAL CHARACTERISTICS (Cin = 10 µF, Cout = 10 µF, for typical value TJ = 25°C, for min and max values TJ = 0°C to 125°C unless otherwise noted.) Characteristic

Symbol

Reference Voltage, Adjustable Output Devices (Vin–Vout = 2.0 V, Iout = 10 mA, TJ = 25°C) (Vin–Vout = 1.4 V to 10 V, Iout = 10 mA to 800 mA, TJ = 0°C to 125°C)

Vref

Output Voltage, Fixed Output Devices

Vout

Min

Typ

Max

1.238 1.225

1.25 –

1.262 1.270

V

V

1.5 V

(Vin = 3.5 V, Iout = 10 mA, TJ = 25 °C) (Vin = 2.9 V to 11.5 V, Iout = 0 mA to 800 mA, TJ = 0°C to 125°C)

1.485 1.470

1.500 –

1.515 1.530

1.8 V

(Vin = 3.8 V, Iout = 10 mA, TJ = 25 °C) (Vin = 3.2 V to 11.8 V, Iout = 0 mA to 800 mA, TJ = 0°C to 125°C)

1.782 1.755

1.800 –

1.818 1.845

2.0 V

(Vin = 4.0 V, Iout = 10 mA, TJ = 25 °C) (Vin = 3.4 V to 12 V, Iout = 0 mA to 800 mA, TJ = 0°C to 125°C)

1.970 1.960

2.000 –

2.030 2.040

2.5 V


2.475 2.450

2.500 –

2.525 2.550

2.85 V (Vin = 4.85 V, Iout = 10 mA, TJ = 25 °C) (Vin = 4.25 V to 10 V, Iout = 0 mA to 800 mA, TJ = 0°C to 125°C) (Vin = 4.0 V, Iout = 0 mA to 500 mA, TJ = 0°C to 125°C)

2.821 2.790 2.790

2.850 – –

2.879 2.910 2.910

3.3 V


3.267 3.235

3.300 –

3.333 3.365

5.0 V


4.950 4.900

5.000 –

5.050 5.100

12 V

(Vin = 14 V, Iout = 10 mA, TJ = 25 °C) (Vin = 13.5 V to 20 V, Iout = 0 mA to 800 mA, TJ = 0°C to 125°C)

11.880 11.760

12.000 –

12.120 12.240


Unit

NCP1117 ELECTRICAL CHARACTERISTICS (Cin = 10 µF, Cout = 10 µF, for typical value TJ = 25°C, for min and max values TJ = 0°C to 125°C unless otherwise noted.) Characteristic

Symbol

Min

Typ

Max

Unit

– – – – – – – – –

0.04 0.3 0.4 0.5 0.5 0.8 0.8 0.9 1.0

0.1 1.0 1.0 2.5 2.5 3.0 4.5 6.0 7.5

%

– – – – – – – – –

0.2 2.3 2.6 3.0 3.3 3.8 4.3 6.7 16

0.4 5.5 6.0 6.0 7.5 8.0 10 15 28

– – –

0.95 1.01 1.07

1.10 1.15 1.20

Iout

1000

1500

2200

mA

IL(min)

–

0.8

5.0

mA

– – – – – – – –

3.6 4.2 4.5 5.2 5.5 6.0 6.0 6.0

10 10 10 10 10 10 10 10

–

0.01

0.1

67 66 64 64 62 62 60 57 50

73 72 70 70 68 68 64 61 54

– – – – – – – – –

Line Regulation (Note 4) Adjustable (Vin = 2.75 V to 16.25 V, Iout = 10 mA) 1.5 V (Vin = 2.9 V to 11.5 V, Iout = 0 mA) 1.8 V (Vin = 3.2 V to 11.8 V, Iout = 0 mA) 2.0 V (Vin = 3.4 V to 12 V, Iout = 0 mA) 2.5 V (Vin = 3.9 V to 10 V, Iout = 0 mA) 2.85 V (Vin = 4.25 V to 10 V, Iout = 0 mA) 3.3 V (Vin = 4.75 V to 15 V, Iout = 0 mA) 5.0 V (Vin = 6.5 V to 15 V, Iout = 0 mA) 12 V (Vin = 13.5 V to 20 V, Iout = 0 mA)

Regline

Load Regulation (Note 4) Adjustable (Iout = 10 mA to 800 mA, Vin = 4.25 V) 1.5 V (Iout = 0 mA to 800 mA, Vin = 2.9 V) 1.8 V (Iout = 0 mA to 800 mA, Vin = 3.2 V) 2.0 V (Iout = 0 mA to 800 mA, Vin = 3.4 V) 2.5 V (Iout = 0 mA to 800 mA, Vin = 3.9 V) 2.85 V (Iout = 0 mA to 800 mA, Vin = 4.25 V) 3.3 V (Iout = 0 mA to 800 mA, Vin = 4.75 V) 5.0 V (Iout = 0 mA to 800 mA, Vin = 6.5 V) 12 V (Iout = 0 mA to 800 mA, Vin = 13.5 V)

Regline

Dropout Voltage (Measured at Vout – 100 mV) (Iout = 100 mA) (Iout = 500 mA) (Iout = 800 mA)

Vin–Vout

Output Current Limit (Vin–Vout = 5.0 V, TJ = 25°C, Note 5) Minimum Required Load Current for Regulation, Adjustable Output Devices (Vin = 15 V) Quiescent Current 1.5 V (Vin = 11.5 V) 1.8 V (Vin = 11.8 V) 2.0 V (Vin = 12 V) 2.5 V (Vin = 10 V) 2.85 V (Vin = 10 V) 3.3 V (Vin = 15 V) 5.0 V (Vin = 15 V) 12 V (Vin = 20 V)

% mV

V

IQ

Thermal Regulation (TA = 25°C, 30 ms Pulse)

mV

mA

%/W

Ripple Rejection (Vin–Vout = 6.4 V, Iout = 500 mA, 10 Vpp 120 Hz Sinewave) Adjustable 1.5 V 1.8 V 2.0 V 2.5 V 2.85 V 3.3 V 5.0 V 12 V

RR

dB

Adjustment Pin Current (Vin = 11.25 V, Iout = 800 mA)

Iadj

–

52

120

mA

Adjust Pin Current Change (Vin–Vout = 1.4 V to 10 V, Iout = 10 mA to 800 mA)

DIadj

–

0.4

5.0

mA

Temperature Stability

ST

–

0.5

–

%

Long Term Stability (TA = 25°C, 1000 Hrs End Point Measurement)

St

–

0.3

–

%

RMS Output Noise (f = 10 Hz to 10 kHz)

N

–

0.003

–

%Vout

4. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 5. The regulator output current must not exceed 1.0 A with Vin greater than 12 V.


2.0

1.4 Vin = Vout + 3.0 V Iout = 10 mA

1.5

Vin – Vout, DROPOUT VOLTAGE (V)

Vout, OUTPUT VOLTAGE CHANGE (%)

NCP1117

Adj, 1.5 V, 1.8 V, 2.0 V, 2.5 V

1.0 0.5 0

–0.5 2.85 V, 3.3 V, 5.0 V, 12.0 V

–1.0 –1.5 –2.0 –50

–25

0

25

50

75

100

TJ = –40°C

1.0 0.8

TJ = 125°C

0.6 0.4 0.2 Load pulsed at 1.0% duty cycle 0

150

125

TJ = 25°C

1.2

0

200

400

600

800

TA, AMBIENT TEMPERATURE (°C)


Figure 4. Output Voltage Change vs. Temperature


1000

2.0

2.0 Iout, OUTPUT CURRENT (A)

Iout, OUTPUT CURRENT (A)

TJ = 25°C 1.5

1.0

0.5

1.8

1.6

1.4

1.2 Vin = 5.0 V Load pulsed at 1.0% duty cycle

Load pulsed at 1.0% duty cycle 0

2

4

6

8

10

12

14

16

18

–25

0

25

50

75

100

125

Vin – Vout, VOLTAGE DIFFERENTIAL (V)


Figure 6. Output Short Circuit Current vs. Differential Voltage

Figure 7. Output Short Circuit Current vs. Temperature

100 Iadj, ADJUST PIN CURRENT (mA)

1.0 –50

20

IQ, QUIESCENT CURRENT CHANGE (%)

0

80

60

150

10 5.0 0

–5.0

40

20

0 –50

Iout = 10 mA

–25

0

25

50

75

100

125

150

–10 –15 –20 –50

–25

0

25

50

75

100

125



Figure 8. Adjust Pin Current vs. Temperature

Figure 9. Quiescent Current Change vs. Temperature


150

NCP1117 100 fripple = 120 Hz Vripple v 3.0 VP–P

80

60



100

fripple = 20 kHz Vripple v 0.5 VP–P

40

Vout = 5.0 V Vin – Vout = 3.0 V Cout = 10 mF Cadj = 25 mF TA = 25°C

20

0

Vin – Vout w 3.0 V

80

60 Vout = 5.0 V Vin – Vout = 3.0 V Iout = 0.5 A Cout = 10 mF Cadj = 25 mF, f > 60 Hz Cadj = 200 mF, f v 60 Hz TA = 25°C

40

20

400

600

800

1000

Vin – Vout w Vdropout

100

1.0 k

10 k

100 k

fripple, RIPPLE FREQUENCY (Hz)

Figure 10. NCP1117XTA Ripple Rejection vs. Output Current

Figure 11. NCP1117XTA Ripple Rejection vs. Frequency OUTPUT VOLTAGE DEVIATION (V)


Cin = 1.0 mF Cout = 10 mF Iout = 0.1 A TA = 25°C

5.25

0.1 0

20 0 –20 80

120

160

0.5 0

200

0

40

80

120

t, TIME (ms)

Figure 12. NCP1117XT285 Line Transient Response

Figure 13. NCP1117XT285 Load Transient Response


7.5

20 0 –20 80

120

160

200

0 Cin = 10 mF Cout = 10 mF Vin = 6.5 V Preload = 0.1 A TA = 25°C

0.5 0 0

t, TIME (ms)

40

80

120

160

t, TIME (ms)




200

0.1

–0.1

6.5

40

160

t, TIME (ms)


40

Cin = 10 mF Cout = 10 mF Vin = 4.5 V Preload = 0.1 A TA = 25°C

–0.1

LOAD CURRENT CHANGE (A)

4.25

0

10


INPUT VOLTAGE (V) OUTPUT VOLTAGE DEVIATION (mV)

200

0

INPUT VOLTAGE (V)

Vripple v 0.5 VP–P

0 0


Vripple v 3.0 VP–P

200



14.5

0.1 0 Cin = 10 mF Cout = 10 mF Vin = 13.5 V Preload = 0.1 A TA = 25°C

–0.1


13.5

20 0 –20 120

160

200

0 0

40

80

t, TIME (ms)


180

1.6

160

1.4

PD(max) for TA = 50°C

140

ÎÎÎ ÎÎÎ ÎÎÎ

2.0 oz. Copper L

Minimum Size Pad

L

100 80

1.2 1.0 0.8 0.6

RθJA 60

0

5.0

10 15 20 25 L, LENGTH OF COPPER (mm)

0.4 30

Figure 18. SOT–223 Thermal Resistance and Maximum Power Dissipation vs. P.C.B. Copper Length

1.6

100

PD(max) for TA = 50°C 1.4

90


2.0 oz. Copper L

80 Minimum Size Pad

70

1.2 1.0

L

0.8

60 50

0.6

RθJA 40 0

160

t, TIME (ms)


120

120

PD, MAXIMUM POWER DISSIPATION (W)

80

0.5

5.0

10

15

20

25

0.4 30

L, LENGTH OF COPPER (mm)

Figure 19. DPAK Thermal Resistance and Maximum Power Dissipation vs. P.C.B. Copper Length http://onsemi.com 620

PD, MAXIMUM POWER DISSIPATION (W)

40

RqJA, THERMAL RESISTANCE, JUNCTION–TO–AIR (°CW)

0

RqJA, THERMAL RESISTANCE, JUNCTION–TO–AIR (°CW)


INPUT VOLTAGE (V)

NCP1117

200

NCP1117 APPLICATIONS INFORMATION Introduction

Frequency compensation for the regulator is provided by capacitor Cout and its use is mandatory to ensure output stability. A minimum capacitance value of 4.7 µF with an equivalent series resistance (ESR) that is within the limits of 0.25 W to 2.2 W is required. The capacitor type can be ceramic, tantalum, or aluminum electrolytic as long as it meets the minimum capacitance value and ESR limits over the circuit’s entire operating temperature range. Higher values of output capacitance can be used to enhance loop stability and transient response with the additional benefit of reducing output noise.

The NCP1117 features a significant reduction in dropout voltage along with enhanced output voltage accuracy and temperature stability when compared to older industry standard three–terminal adjustable regulators. These devices contain output current limiting, safe operating area compensation and thermal shutdown protection making them designer friendly for powering numerous consumer and industrial products. The NCP1117 series is pin compatible with the older LM317 and its derivative device types. Output Voltage

Input

The typical application circuits for the fixed and adjustable output regulators are shown in Figures 20 and 21. The adjustable devices are floating voltage regulators. They develop and maintain the nominal 1.25 V reference voltage between the output and adjust pins. The reference voltage is programmed to a constant current source by resistor R1, and this current flows through R2 to ground to set the output voltage. The programmed current level is usually selected to be greater than the specified 5.0 mA minimum that is required for regulation. Since the adjust pin current, Iadj, is significantly lower and constant with respect to the programmed load current, it generates a small output voltage error that can usually be ignored. For the fixed output devices R1 and R2 are included within the device and the ground current Ignd, ranges from 3.0 mA to 5.0 mA depending upon the output voltage.

Cin

Cin

+

NCP1117 XTXX 1

+

R1

Vref

1

+

ǒ

+

Cout

Cadj

Ǔ

Vout + Vref 1 ) R2 ) Iadj R2 R1


The output ripple will increase linearly for fixed and adjustable devices as the ratio of output voltage to the reference voltage increases. For example, with a 12 V regulator, the output ripple will increase by 12 V/1.25 V or 9.6 and the ripple rejection will decrease by 20 log of this ratio or 19.6 dB. The loss of ripple rejection can be restored to the values shown with the addition of bypass capacitor Cadj, shown in Figure 21. The reactance of Cadj at the ripple frequency must be less than the resistance of R1. The value of R1 can be selected to provide the minimum required load current to maintain regulation and is usually in the range of 100 W to 200 W. Cadj u

1 2 p fripple R1

The minimum required capacitance can be calculated from the above formula. When using the device in an application that is powered from the AC line via a transformer and a full wave bridge, the value for Cadj is:

Output

2

Output

2

R2

Input bypass capacitor Cin may be required for regulator stability if the device is located more than a few inches from the power source. This capacitor will reduce the circuit’s sensitivity when powered from a complex source impedance and significantly enhance the output transient response. The input bypass capacitor should be mounted with the shortest possible track length directly across the regulator’s input and ground terminals. A 10 µF ceramic or tantalum capacitor should be adequate for most applications.

3

+

NCP1117 XTA

Iadj

External Capacitors

Input

3

fripple + 120 Hz, R1 + 120 W, then Cadj u 11.1 mF

The value for Cadj is significantly reduced in applications where the input ripple frequency is high. If used as a post regulator in a switching converter under the following conditions:

Cout

Ignd

fripple + 50 kHz, R1 + 120 W, then Cadj u 0.027 mF Figure 20. Fixed Output Regulator

Figures 10 and 11 shows the level of ripple rejection that is obtainable with the adjust pin properly bypassed.


NCP1117 Protection Diodes

The second condition is that the ground end of R2 should be connected directly to the load. This allows true Kelvin sensing where the regulator compensates for the voltage drop caused by wiring resistance RW –.

The NCP1117 family has two internal low impedance diode paths that normally do not require protection when used in the typical regulator applications. The first path connects between Vout and Vin, and it can withstand a peak surge current of about 15 A. Normal cycling of Vin cannot generate a current surge of this magnitude. Only when Vin is shorted or crowbarred to ground and Cout is greater than 50 µF, it becomes possible for device damage to occur. Under these conditions, diode D1 is required to protect the device. The second path connects between Cadj and Vout, and it can withstand a peak surge current of about 150 mA. Protection diode D2 is required if the output is shorted or crowbarred to ground and Cadj is greater than 1.0 µF.

Input

Cin

3 +

NCP1117 XTA

RW+

2 +

R1

1

Cout

Output Remote Load

R2

RW–

Figure 23. Load Sensing D1

Thermal Considerations

1N4001 Input Cin

3 +

NCP1117 XTA 1

R1 +

R2

This series contains an internal thermal limiting circuit that is designed to protect the regulator in the event that the maximum junction temperature is exceeded. When activated, typically at 175°C, the regulator output switches off and then back on as the die cools. As a result, if the device is continuously operated in an overheated condition, the output will appear to be oscillating. This feature provides protection from a catastrophic device failure due to accidental overheating. It is not intended to be used as a substitute for proper heatsinking. The maximum device power dissipation can be calculated by:

Output

2 D2 1N4001

+

Cout

Cadj

Figure 22. Protection Diode Placement

A combination of protection diodes D1 and D2 may be required in the event that Vin is shorted to ground and Cadj is greater than 50 µF. The peak current capability stated for the internal diodes are for a time of 100 µs with a junction temperature of 25°C. These values may vary and are to be used as a general guide.

PD +

TJ(max) * TA RqJA

The devices are available in surface mount SOT–223 and DPAK packages. Each package has an exposed metal tab that is specifically designed to reduce the junction to air thermal resistance, RqJA, by utilizing the printed circuit board copper as a heat dissipater. Figures 18 and 19 show typical RqJA values that can be obtained from a square pattern using economical single sided 2.0 ounce copper board material. The final product thermal limits should be tested and quantified in order to insure acceptable performance and reliability. The actual RqJA can vary considerably from the graphs shown. This will be due to any changes made in the copper aspect ratio of the final layout, adjacent heat sources, and air flow.

Load Regulation

The NCP1117 series is capable of providing excellent load regulation; but since these are three terminal devices, only partial remote load sensing is possible. There are two conditions that must be met to achieve the maximum available load regulation performance. The first is that the top side of programming resistor R1 should be connected as close to the regulator case as practicable. This will minimize the voltage drop caused by wiring resistance RW + from appearing in series with reference voltage that is across R1.


NCP1117

Input

NCP1117 XTA

3 +

10 mF

Constant Current Output

R

2

+

1

Input

+

10 mF

10 mF

NCP1117 XTA

3

Output

2 +

R1

1

50 k

R2

2N2907

10 mF

V Iout + ref ) Iadj R

Figure 24. Constant Current Regulator


Input

3

10 mF

+

NCP1117 XTA

+

Output

2 +

R1

1

10 mF

Output

2

+ 10

120

1

NCP1117 XTA

3

10 mF Input

1N4001

10 mF

R2

mF 2N2222

360

1.0 k

Output Control

2N2222 On 1.0 k

Off

Output Voltage Control Resistor R2 sets the maximum output voltage. Each transistor reduces the output voltage when turned on.

Vout(Off) + Vref

Figure 26. Regulator with Shutdown

Input

3 10 mF

+

NCP1117 XT50

2

Figure 27. Digitally Controlled Regulator

Output + 10

mF

1 50 W

Input 5.3 V AC Line 5.0 V Battery

RCHG 3 +

6.6 V

–

10 mF

+

NCP1117 XT50

10 mF

2

3 +

NCP1117 XT50

Output 5.0 V to 12 V + 10

2

mF

1 + 10

2.0 k

1

mF

The 50 W resistor that is in series with the ground pin of the upper regulator level shifts its output 300 mV higher than the lower regulator. This keeps the lower regulator off until the input source is removed.

Figure 28. Battery Backed–Up Power Supply

Figure 29. Adjusting Output of Fixed Voltage Regulators


NCP1117 MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS The surface mount board layout is a critical portion of the total design. The footprint for the regulator package must be of correct size to insure a proper solder connection of the

package tab and pins to the printed circuit board copper. With proper footprint pad sizes, the packages will self align when subjected to a solder reflow process.

inches

inches mm mm

DPAK, Case 369A

SOT–223, Case 318H


NCP1117 ORDERING INFORMATION Nominal Output Voltage

Package

Shipping

NCP1117DTA

Adjustable

DPAK

75 Units/Rail

NCP1117DTARK

Adjustable

DPAK


NCP1117STAT3

Adjustable

SOT–223


NCP1117DT15

1.5

DPAK

75 Units/Rail

NCP1117DT15RK

1.5

DPAK


NCP1117ST15T3

1.5

SOT–223


NCP1117DT18

1.8

DPAK

75 Units/Rail

NCP1117DT18RK

1.8

DPAK


NCP1117ST18T3

1.8

SOT–223


NCP1117DT20

2.0

DPAK

75 Units/Rail

NCP1117DT20RK

2.0

DPAK


NCP1117ST20T3

2.0

SOT–223


NCP1117DT25

2.5

DPAK

75 Units/Rail

NCP1117DT25RK

2.5

DPAK


NCP1117ST25T3

2.5

SOT–223


NCP1117DT285

2.85

DPAK

75 Units/Rail

NCP1117DT285RK

2.85

DPAK


NCP1117ST285T3

2.85

SOT–223


NCP1117DT33

3.3

DPAK

75 Units/Rail

NCP1117DT33RK

3.3

DPAK


NCP1117ST33T3

3.3

SOT–223


NCP1117DT50

5.0

DPAK

75 Units/Rail

NCP1117DT50RK

5.0

DPAK


NCP1117ST50T3

5.0

SOT–223


NCP1117DT12

12

DPAK

75 Units/Rail

NCP1117DT12RK

12

DPAK


NCP1117ST12T3

12

SOT–223


Device


NCP1117 MARKING DIAGRAMS

SOT–223 ST SUFFIX CASE 318H

ALYW 117–A 1

2

ALYW 17–15 1

3

Adjustable

2

ALYW 17–18 1

3

1.5 V

2

1

3

1.8 V

1

3

2.85 V

2

2

ALYW 17–25 1

3

2.0 V

ALYW 17–33

ALYW 7–285 1

2

ALYW 117–2

1

3.3 V

2

3

2.5 V

ALYW 117–5 3

2

ALYW 17–12 1

3

5.0 V

2

3

12 V


117AJ ALYWW

17–15 ALYWW

2 1

17–18 ALYWW

2 3

1

Adjustable

2 3

1

1.5 V

17285 ALYWW

17–33 ALYWW

1

2.85 V

1

2 3

1

2.0 V

117–5 ALYWW

2 3

17–25 ALYWW

2 3

1.8 V

2 1

117–2 ALYWW

2.5 V

17–12 ALYWW

2 3

1

3.3 V

A L Y WW, W

2 3

5.0 V



3

1

3 12 V

"##$%& ' ( ) *)

! The MC33269 series are low dropout, medium current, fixed and adjustable, positive voltage regulators specifically designed for use in low input voltage applications. These devices offer the circuit designer an economical solution for precision voltage regulation, while keeping power losses to a minimum. The regulator consists of a 1.0 V dropout composite PNP–NPN pass transistor, current limiting, and thermal shutdown. • 3.3 V, 5.0 V, 12 V and Adjustable Versions. 2.85 V version available as MC34268. • Space Saving DPAK, SOP–8 and SOT–223 Power Packages • 1.0 V Dropout • Output Current in Excess of 800 mA • Thermal Protection • Short Circuit Protection • Output Trimmed to 1.0% Tolerance

http://onsemi.com SO–8 D SUFFIX CASE 751

8 1 Gnd/Adj 1

8

2

7

3

6

4

5

Vout Vin

DPAK DT SUFFIX CASE 369A 3

1. Gnd/Adj 2. Vout 3. Vin

DEVICE TYPE/NOMINAL OUTPUT VOLTAGE Adj Adj Adj 3.3 V 3.3 V 3.3 V 3.3 V

MC33269D–5.0 MC33269DT–5.0 MC33269T–5.0 MC33269D–12 MC33269DT–12 MC33269T–12

Vout NC

(Top View)

1

MC33269D MC33269DT MC33269T MC33269D–3.3 MC33269DT–3.3 MC33269T–3.3 MC33269ST–3.3

NC

5.0 V 5.0 V 5.0 V 12 V 12 V 12 V

1 3


1 2 3 (Top View)

1

2

3

(Top View) Heatsink surface (shown as terminal 4 in case outline drawing) is connected to Pin 2.


1

2

3

1. Gnd/Adj 2. Vout 3. Vin

12 3 (Top View)






627


MC33269 MAXIMUM RATINGS Rating

Symbol

Value

Unit

Vin

20

V

PD θJA θJC


W °C/W °C/W

PD θJA θJC


W °C/W °C/W

PD θJA θJC


W °C/W °C/W

PD θJA θJC


W °C/W °C/W


TJ

–40 to +150

°C

Storage Temperature

Tstg

–55 to +150

°C

Power Supply Input Voltage Power Dissipation Case 369A (DPAK) TA = 25°C Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case Case 751 (SOP–8) TA = 25°C Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case Case 221A TA = 25°C Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case Case 318E TA = 25°C Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case


ELECTRICAL CHARACTERISTICS (CO = 10 µF, TA = 25°C, for min/max values TJ = –40°C to +125°C, unless otherwise noted.) Characteristic

Symbol

Output Voltage (Iout = 10 mA, TJ = 25°C) 3.3 Suffix (VCC = 5.3 V) 5.0 Suffix (VCC = 7.0 V) 12 Suffix (VCC = 14 V)

VO

Output Voltage (Line, Load and Temperature) (Note 1) (1.25 V ≤ Vin – Vout ≤ 15 V, Iout = 500 mA) (1.35 V ≤ Vin – Vout ≤ 10 V, Iout = 800 mA) 3.3 Suffix 5.0 Suffix 12 Suffix

VO

Reference Voltage (Iout = 10 mA, Vin – Vout = 2.0 V, TJ = 25°C) for Adjustable Voltage Reference Voltage (Line, Load and Temperature) (Note 1) (1.25 V ≤ Vin – Vout ≤ 15 V, Iout = 500 mA) (1.35 V ≤ Vin – Vout ≤ 10 V, Iout = 800 mA) for Adjustable Voltage

Min

Typ

Max

3.27 4.95 11.88

3.3 5.0 12

3.33 5.05 12.12

Unit V

V

3.23 4.9 11.76

3.3 5.0 12

3.37 5.1 12.24

Vref

1.235

1.25

1.265

V

Vref

1.225

1.25

1.275

V

Line Regulation (Iout = 10 mA, Vin = [Vout + 1.5 V] to Vin = 20 V, TJ = 25°C)

Regline

–

–

0.3

%

Load Regulation (Vin = Vout + 3.0 V, Iout = 10 mA to 800 mA, TJ = 25°C)

Regload

–

–

0.5

%

– –

1.0 1.1

1.25 1.35

Dropout Voltage (Iout = 500 mA) (Iout = 800 mA)

Vin – Vout

V

Ripple Rejection (10 Vpp, 120 Hz Sinewave; Iout = 500 mA)

RR

55

–

–

dB

Current Limit (Vin – Vout = 10 V)

ILimit

800

–

–

mA

– –

5.5 –

8.0 20

Quiescent Current (Fixed Output) (1.5 V ≤ Vout ≤ 3.3 V) (5 V ≤ Vout ≤ 12 V)

IQ

mA

1. The MC33269–12, Vin – Vout is limited to 8.0 V maximum, because of the 20 V maximum rating applied to Vin.


MC33269 ELECTRICAL CHARACTERISTICS (continued) (CO = 10 µF, TA = 25°C, for min/max values TJ = –40°C to +125°C, unless otherwise noted.) Characteristic

Symbol

Minimum Required Load Current Fixed Output Voltage Adjustable Voltage

Min

Typ

Max

– 8.0

– –

0 –

–

–

120

ILoad


IAdj

Unit mA

µA


Figure 1. Internal Schematic


MC33269

∆ * ! %*"% &

, ) °#

, °#

, °#

+" 2 # , µ# , µ- ../ , 0 !1/. ,

* ! # $$%&

) *"$! * %*' (

-4' (* %$ %*&! *5$%65"*'7 *****( -4

Figure 2. Dropout Voltage versus Output Load Current

Figure 3. Transient Load Regulation

,

! *# $$%&*'(

)

)

&! ) ! % "--%$%& ' (


Figure 5. MC33269–XX Output DC Current versus Input–Output Differential Voltage

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$$*$!!%*$%:%#&*$*'4(

, °# 3#")88 , #991

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,

,

*

+"

! " # $$%& '(

*

, 0 , , °#

; -$%< %&#= '5>(

Figure 6. MC33269 Ripple Rejection versus Frequency

, , , # , µ , °#

; -$%< %&#= '5>(

Figure 7. MC33269–ADJ Ripple Rejection versus Frequency


ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏÏÏÏÏÏÏ

.9D 1911 C1 B./ /.C

> #991

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: &#&??$*'**#+@( °

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-11 31 1 B.//C

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MC33269

MC33269 APPLICATIONS INFORMATION supply input filter with long wire lengths. This will reduce the circuit’s sensitivity to the input line impedance at high frequencies. A 0.33 µF or larger tantalum, mylar, ceramic, or other capacitor having low internal impedance at high frequencies should be chosen. The bypass capacitor should be mounted with shortest possible lead or track length directly across the regulator’s input terminals. Applications should be tested over all operating conditions to insure stability. Internal thermal limiting circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated, typically at 170°C, the output is disabled. There is no hysteresis built into the thermal limiting circuit. As a result, if the device is overheating, the output will appear to be oscillating. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used as a substitute for proper heatsinking.

Figures 11 through 15 are typical application circuits. The output current capability of the regulator is in excess of 800 mA, with a typical dropout voltage of less than 1.0 V. Internal protective features include current and thermal limiting. * The MC33269 requires an external output capacitor for stability. The capacitor should be at least 10 µF with an equivalent series resistance (ESR) of less than 10 Ω but greater than 0.2 Ω over the anticipated operating temperature range. With economical electrolytic capacitors, cold temperature operation can pose a problem. As temperature decreases, the capacitance also decreases and the ESR increases, which could cause the circuit to oscillate. Also capacitance and ESR of a solid tantalum capacitor is more stable over temperature. The use of a low ESR ceramic capacitor placed within close proximity to the output of the device could cause instability. ** An input bypass capacitor is recommended to improve transient response or if the regulator is connected to the

MC33269-XX

EE #

# E µ-

EE #

#EEE

ǒ

Figure 11. Typical Fixed Output Application

MC33269

$6

***CAdj is optional, however it will improve the ripple rejection. The MC34269 develops a 1.25 V reference voltage between the output and the adjust terminal. Resistor R1, operates with constant current to flow through it and resistor R2. This current should be set such that the Adjust Pin current causes negligible drop across resistor R2. The total current with minimum load should be greater than 8.0 mA.

F +F $ 6


EE #

MC33269-XX

Ǔ

F + FFF ) $ F)F $ F $

# E µ-

# E µ-

$

An input capacitor is not necessary for stability, however it will improve the overall performance.

EE #

$

MC33269

Figure 12. Typical Adjustable Output Application

EE #

MC33269 $

MC33269-XX EE #

$

#E µ-

# E µ-

The Schottky diode in series with the ground leg of the upper regulator shifts its output voltage higher by the forward voltage drop of the diode. This will cause the lower device to remain off until the input voltage is removed.

R2 sets the maximum output voltage. Each transistor reduces the output voltage when turned on.

Figure 14. Battery Backed–Up Power Supply

Figure 15. Digitally Controlled Voltage Regulator



Package

Shipping Information

MC33269D

SO–8

98 Units / Rail

MC33269DR2

SO–8


MC33269DT

DPAK

75 Units / Rail

MC33269DTRK

DPAK


TO–220

50 Units / Rail

MC33269T MC33269D–3.3

SO–8

98 Units / Rail

MC33269DR2–3.3

SO–8


MC33269DT–3.3

DPAK

75 Units / Rail

MC33269DTRK–3.3

DPAK


MC33269ST–3.3T3

SOT–223


MC33269T–3.3

TO–220

50 Units / Rail

MC33269D–5.0

SO–8

98 Units / Rail

MC33269DR2–5.0

SO–8


MC33269DT–5.0

DPAK

75 Units / Rail

MC33269DTRK–5.0

DPAK


MC33269T–5.0

TO–220

50 Units / Rail

MC33269D–12

SO–8

98 Units / Rail

MC33269DR2–12

SO–8


MC33269DT–12

DPAK

75 Units / Rail

DPAK


TO–220

50 Units / Rail

MC33269DTRK–12 MC33269T–12


MC33269 MARKING DIAGRAMS SO–8 D SUFFIX CASE 751 8

8 269AJ ALYW

8 69–12 ALYW

1

8 269–3 ALYW

1

269–5 ALYW

1

1


269AJ ALYWW

69–12 ALYWW

2 1


269–3 ALYWW

2 3

1

269–5 ALYWW

2 3

1

ALYW 2693

2 3

1

1

3


MC 33269T AWLYWW

1

2

3

MC 33269T–12 AWLYWW

1

2

MC 33269T–3.3 AWLYWW

3

A WL, L Y WW, W

1

2



3

MC 33269T–5.0 AWLYWW

1

2

3

2

3

+,$ # ) ## ! The CS5201–3 linear regulator provides 1.0 A @ 3.3 V reference at 1.0 A with an output voltage accuracy of ±1.5 %. This regulator is intended for use as a post regulator and microprocessor supply. The fast loop response and low dropout voltage make this regulator ideal for applications where low voltage operation and good transient response are important. The circuit is designed to operate with dropout voltages less than 1.2 V at 1.0 A output current. The maximum quiescent current is only 10 mA at full load. Device protection includes over–current and thermal shutdown. The CS5201–3 is pin compatible with the LT1086 family of linear regulators. The regulator is available in TO–220, surface mount D2, and SOT–223 packages. Features • Output Current to 1.0 A • Output Accuracy to ±1.5% Over Temperature • Dropout Voltage (typical) 1.0 V @ 1.0 A • Fast Transient Response • Fault Protection – Current Limit – Thermal Shutdown

http://onsemi.com


12

2


Tab = VOUT Pin 1. GND 2. VOUT 3. VIN

3

1

23


ORDERING INFORMATION*† Device

VOUT

VIN

CS5201–3

3.3 V @ 1.0 A

GND 10 µF 5.0 V

22 µF 5.0 V

Package

Shipping

CS5201–3GT3

TO–220‡

50 Units/Rail

CS5201–3GDP3

D2PAK‡

50 Units/Rail

CS5201–3GDPR3

D2PAK‡

750 Tape & Reel

CS5201–3GST3

SOT–223‡

80 Units/Rail

CS5201–3GSTR3

SOT–223‡

2500 Tape & Reel

*Additional ordering information can be found on page 640 of this data sheet. †Consult your local sales representative for other fixed output voltage versions. ‡TO–220 are all 3–pin, straight leaded. D2PAK and SOT–223 are all 3–pin.

Figure 1. Applications Diagram




635

Publication Order Number: CS5201–3/D

CS5201–3 ABSOLUTE MAXIMUM RATINGS* Parameter Supply Voltage, VIN Operating Temperature Range Junction Temperature Storage Temperature Range Lead Temperature Soldering:


ESD Damage Threshold (Human Body Model)

Value

Unit

7.0

V

–40 to +70

°C

150

°C

–60 to +150

°C

260 Peak 230 Peak

°C °C

2.0

kV

1. 10 second maximum. 2. 60 second maximum above 183°C *The maximum package power dissipation must be observed.

ELECTRICAL CHARACTERISTICS (CIN = 10 µF, COUT = 22 µF Tantalum, VOUT + VDROPOUT < VIN < 7.0 V, 0°C ≤ TA ≤ 70°C, TJ ≤ +150°C, unless otherwise specified, Ifull load = 1.0 A)

Test Conditions

Characteristic

Min

Typ

Max

Unit

3.250 (–1.5%)

3.300

3.350 (+1.5%)

V

Fixed Output Voltage Reference Voltage (Notes 3 and 4)

VIN – VOUT = 1.5 V; 0 ≤ IOUT ≤ 1.0 A

Line Regulation

2.0 V ≤ VIN – VOUT ≤ 3.7 V; IOUT = 10 mA

–

0.02

0.20

%

Load Regulation (Notes 3 and 4)

VIN – VOUT = 2.0 V; 10 mA ≤ IOUT ≤ 1.0 A

–

0.04

0.4

%

Dropout Voltage (Note 5)

IOUT = 1.0 A

–

1.0

1.2

V

Current Limit

VIN – VOUT = 3.0 V

1.0

3.1

–

A

Quiescent Current

IOUT = 10 mA

–

5.0

10

mA

Thermal Regulation (Note 6)

30 ms Pulse, TA = 25°C

–

0.002

0.020

%/W

Ripple Rejection (Note 6)

f = 120 Hz; IOUT = 1.0 A; VIN – VOUT = 3.0 V; VRIPPLE = 1.0 VPP

–

80

–

dB

Thermal Shutdown (Note 7)

–

150

180

210

°C

Thermal Shutdown Hysteresis (Note 7)

–

–

25

–

°C

3. Load regulation and output voltage are measured at a constant junction temperature by low duty cycle pulse testing. Changes in output voltage due to temperature changes must be taken into account seperately. 4. Specifications apply for an external Kelvin sense connection at a point on the output pin 1/4” from the bottom of the package. 5. Dropout voltage is a measurement of the minimum input/output differential at full load. 6. Guaranteed by design, not 100% tested in production. 7. Thermal shutdown is 100% functionally tested in production. PACKAGE PIN DESCRIPTION Package Pin Number TO–220

D2PAK

SOT–223

Pin Symbol

1

1

1

GND

Ground connection.

2

2

2

VOUT

Regulated output voltage (case).

3

3

3

VIN

Function

Input voltage.


CS5201–3

VOUT VIN

Output Current Limit Thermal Shutdown

– +

Error Amplifier

Bandgap Reference GND



0.10 0.08 Output Voltage Deviation (%)

TCASE = 0°C

0.95 VDROPOUT (V)

TCASE = 25°C

0.90

0.85 TCASE = 125°C

0.80

0.06 0.04 0.02 0.00 –0.02 –0.04 –0.06 –0.08 –0.10

0.75

–0.12 0

200

400

600

800

1000

0

IOUT (mA)

TJ (°C)


Figure 4. Reference Voltage vs. Temperature 85

0.100

75 0.075

Ripple Rejection (dB)

Output Voltage Deviation (%)

10 20 30 40 50 60 70 80 90 100 110 120 130

0.050 TCASE = 25°C

0.025 TCASE = 125°C

0

55 TCASE = 25°C

45 35

IOUT = 1.0 A (VIN – VOUT) = 3.0 V VRIPPLE = 1.0 VPP

25 TCASE = 0°C

0.000

65

1

15

101

2

102

103

104

105

Output Current (A)

Frequency (Hz)




106

Load Step (mA)

300

3.5

200

3.3 3.1

100

2.9

0 ISC (A)

Voltage Deviation (mV)

CS5201–3

–100 –200

2.7 2.5 2.3 2.1

1000

1.9

500

1.7 1.5

0 0

1

2

3

4

5

6

7

8

9

10

1.0

1.5

2.0

2.5

3.0

3.5

Time (µS) COUT = CIN = 22 µF Tantalum

VIN – VOUT (V)

Figure 7. Transient Response

Figure 8. Short Circuit Current vs. VIN – VOUT

4.0

APPLICATIONS INFORMATION The CS5201–3 linear regulator provides a fixed 3.3 V output voltage at currents up to 1.0 A. The regulator is protected against overcurrent conditions and includes thermal shutdown. The CS5201–3 has a composite PNP–NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.

ceramic capacitors in parallel. This reduces the overall ESR and reduces the instantaneous output voltage drop under transient load conditions. The output capacitor network should be as close to the load as possible for the best results. Protection Diodes

When large external capacitors are used with a linear regulator it is sometimes necessary to add protection diodes. If the input voltage of the regulator gets shorted, the output capacitor will discharge into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage and the rate at which VIN drops. In the CS5201–3 linear regulator, the discharge path is through a large junction and protection diodes are not usually needed. If the regulator is used with large values of output capacitance and the input voltage is instantaneously shorted to ground, damage can occur. In this case, a diode connected as shown in Figure 9 is recommended.

Stability Considerations

The output compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response, and loop stability. The capacitor value and type is based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution. However, when the circuit operates at low temperatures, both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet provides this information. A 22 µF tantalum capacitor will work for most applications, but with high current regulators such as the CS5201–3 the transient response and stability improve with higher values of capacitance. The majority of applications for this regulator involve large changes in load current so the output capacitor must supply the instantaneous load current. The ESR of the output capacitor causes an immediate drop in output voltage given by: DV + DI

IN4002 (Optional) VIN

VOUT VIN

VOUT

CS5201–3 C1

C2 GND

Figure 9. Protection Diode Scheme for Large Output Capacitors

ESR

For microprocessor applications it is customary to use an output capacitor network consisting of several tantalum and


CS5201–3 Output Voltage Sensing

The maximum power dissipation for a regulator is:

Since the CS5201–3 is a three terminal regulator, it is not possible to provide true remote load sensing. Load regulation is limited by the resistance of the conductors connecting the regulator to the load. For best results the regulator should be connected as shown in Figure 10.

VIN

VIN

VOUT

RC

PD(max) + {VIN(max) * VOUT(min)}IOUT(max) ) VIN(max)IQ (5)

where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current, for the application IQ is the maximum quiescent current at IOUT(max).

Conductor Parasitic Resistance

CS5201–3 RLOAD

A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment has a thermal resistance. Like series electrical resistances, these resistances are summed to determine RΘJA, the total thermal resistance between the junction and the surrounding air. 1. Thermal Resistance of the junction to case, RΘJC (°C/W) 2. Thermal Resistance of the case to Heat Sink, RΘCS (°C/W) 3. Thermal Resistance of the Heat Sink to the ambient air, RΘSA (°C/W) These are connected by the equation:

Figure 10. Conductor Parasitic Resistance Effects Can Be Minimized With the Above Grounding Scheme For Fixed Output Regulators Calculating Power Dissipation and Heat Sink Requirements

The CS5201–3 linear regulator includes thermal shutdown and current limit circuitry to protect the device. High power regulators such as these usually operate at high junction temperatures so it is important to calculate the power dissipation and junction temperatures accurately to ensure that an adequate heat sink is used. The case is connected to VOUT on the CS5201–3, electrical isolation may be required for some applications. Thermal compound should always be used with high current regulators such as these. The thermal characteristics of an IC depend on the following four factors: 1. 2. 3. 4.

RQJA + RQJC ) RQCS ) RQSA

The value for RΘJA is calculated using equation (3) and the result can be substituted in equation (4). The value for RΘJC is 3.5°C/W for a given package type based on an average die size. For a high current regulator such as the CS5201–3 the majority of the heat is generated in the power transistor section. The value for RΘSA depends on the heat sink type, while RΘCS depends on factors such as package type, heat sink interface (is an insulator and thermal grease used?), and the contact area between the heat sink and the package. Once these calculations are complete, the maximum permissible value of RΘJA can be calculated and the proper heat sink selected. For further discussion on heat sink selection, see application note “Thermal Management for Linear Regulators,” document number SR006AN/D, available through the Literature Distribution Center or via our website at http://onsemi.com.

Maximum Ambient Temperature TA (°C) Power dissipation PD (Watts) Maximum junction temperature TJ (°C) Thermal resistance junction to ambient RΘJA (°C/W) These four are related by the equation TJ + TA ) PD

RQJA

(6)

(4)

The maximum ambient temperature and the power dissipation are determined by the design while the maximum junction temperature and the thermal resistance depend on the manufacturer and the package type.


CS5201–3

ADDITIONAL ORDERING INFORMATION Orderable Part Number

Type

Description

CS5201–3GT3

1.0 A, 3.3 V Output

TO–220 THREE LEAD, STRAIGHT

CS5201–3GDP3

1.0 A, 3.3 V Output

D2PAK 3–PIN

CS5201–3GDPR3

1.0 A, 3.3 V Output

D2PAK 3–PIN (Tape & Reel)

CS5201–3GST3

1.0 A, 3.3 V Output

SOT–223

CS5201–3GSTR3

1.0 A, 3.3 V Output

SOT–223 (Tape & Reel)

MARKING DIAGRAMS D2PAK 3–PIN DP SUFFIX CASE 418E

TO–220 THREE LEAD T SUFFIX CASE 221A

SOT–223 ST SUFFIX CASE 318E AYW 52013

CS5201–3 AWLYWW CS5201–3 AWLYWW

1 1




TO–220 THREE LEAD

D2PAK 3–PIN

SOT–223

Unit

RΘJC

Typical

3.5

3.5

15

°C/W

RΘJA

Typical

50

10–50*

156

°C/W



+,$ ! The CS5201–1 linear regulator provides 1.0 A with an output voltage accuracy of ±1.0 %. The device uses two external resistors to set the output voltage within a 1.25 V to 5.5 V range. This regulator is intended for use as a post regulator and microprocessor supply. The fast loop response and low dropout voltage make this regulator ideal for applications where low voltage operation and good transient response are important. The circuit is designed to operate with dropout voltages less than 1.2 V at 1.0 A output current. Device protection includes overcurrent and thermal shutdown. The CS5201 is pin compatible with the LT1086 family of linear regulators. The regulator is available in TO–220, surface mount D2, and SOT–223 packages. Features • Output Current to 1.0 A • Output Accuracy to ±1.0% Over Temperature • Dropout Voltage (typical) 1.0 V @ 1.0 A • Fast Transient Response • Fault Protection – Current Limit – Thermal Shutdown

http://onsemi.com


12

2


Tab = VOUT Pin 1. Adj 2. VOUT 3. VIN

3

1

23


ORDERING INFORMATION*† 5.0 V

Device

VOUT

VIN

3.3 V @ 1.0 A

CS5201–1 124 Ω 1.0%

Adj

10 µF 5.0 V

0.1 µF 5.0 V Tant

200 Ω 1.0%

22 µF 5.0 V

Package

Shipping

CS5201–1GT3

TO–220‡

50 Units/Rail

CS5201–1GDP3

D2PAK‡

50 Units/Rail

CS5201–1GDPR3

D2PAK‡

750 Tape & Reel

CS5201–1GST3

SOT–223‡

80 Units/Rail

CS5201–1GSTR3

SOT–223‡

2500 Tape & Reel

*Additional ordering information can be found on page 647 of this data sheet. †Consult your local sales representative for fixed output voltage versions. ‡TO–220 are all 3–pin, straight leaded. D2PAK and SOT–223 are all 3–pin.

Figure 1. Applications Diagram DEVICE MARKING INFORMATION See general marking information in the device marking section on page 647 of this data sheet.



641


CS5201–1 ABSOLUTE MAXIMUM RATINGS* Parameter Supply Voltage, VCC Operating Temperature Range Junction Temperature Storage Temperature Range Lead Temperature Soldering:



Value

Unit

7.0

V

–40 to +70

°C

150

°C

–60 to +150

°C

260 Peak 230 Peak

°C °C

2.0

kV



Test Conditions

Characteristic

Min

Typ

Max

Unit

1.241 (–1.0%)

1.254

1.266 (+1.0%)

V

Adjustable Output Voltage Reference Voltage (Notes 3 and 4)

VIN – VOUT = 1.5 V; VAdj = 0 V 10 mA ≤ IOUT ≤ 1.0 A

Line Regulation


–

0.02

0.20

%



–

0.04

0.40

%


IOUT = 1.0 A

–

1.0

1.2

V

Current Limit

VIN – VOUT = 3.0 V; TJ ≥ 25°C

1.1

3.1

–

A

Minimum Load Current (Note 6)

VIN = 7.0 V, VAdj = 0 V

–

0.6

2.0

mA

Adjust Pin Current

VIN – VOUT = 3.0 V; IOUT = 10 mA

–

50

100

µA



–

0.002

0.020

%/W



–

80

–

dB


–

150

180

210

°C


–

–

25

–

°C

3. Load regulation and output voltage are measured at a constant junction temperature by low duty cycle pulse testing. Changes in output voltage due to temperature changes must be taken into account seperately. 4. Specifications apply for an external Kelvin sense connection at a point on the output pin 1/4” from the bottom of the package. 5. Dropout voltage is a measurement of the minimum input/output differential at full load. 6. The minimum load current is the minimum current required to maintain regulation. Normally the current in the resistor divider used to set the output voltage is selected to meet the minimum load requirement. 7. Guaranteed by design, not 100% tested in production. 8. Thermal shutdown is 100% functionally tested in production. PACKAGE PIN DESCRIPTION Package Pin Number TO–220

D2PAK

SOT–223

Pin Symbol

1

1

1

Adj

2

2

2

VOUT

3

3

3

VIN

Function Adjust pin (low side of the internal reference). Regulated output voltage (case). Input voltage.


CS5201–1

VOUT VIN


– +

Error Amplifier

Bandgap Reference

Adj



0.10 0.08 Output Voltage Deviation (%)

TCASE = 0°C

0.95 VDROPOUT (V)

TCASE = 25°C

0.90

0.85 TCASE = 125°C

0.80

0.06 0.04 0.02 0.00 –0.02 –0.04 –0.06 –0.08 –0.10

0.75

–0.12 0

200

400

600

800

1000

0

TJ (°C)


Figure 4. Reference Voltage vs. Temperature 0.65 Minimum Load Current (mA)

0.100 Output Voltage Deviation (%)

10 20 30 40 50 60 70 80 90 100 110 120 130

IOUT (mA)

0.075

0.050 TCASE = 25°C

0.025 TCASE = 125°C

0

TCASE = 0°C

0.55

TCASE = 125°C

0.50

0.45 CIN = COUT = 22 µF Tantalum

TCASE = 0°C

0.000

TCASE = 25°C

0.60

1

0.40 2

1

2

3

4

5

6

Output Current (A)

VIN – VOUT (V)


Figure 6. Minimum Load Current vs. VIN – VOUT


7

CS5201–1 85

70 IO = 10 mA

75 Ripple Rejection (dB)

Adjust Pin Current (µA)

65 60 55 50 45

TCASE = 25°C

IOUT = 1.0 A (VIN – VOUT) = 3.0 V VRIPPLE = 1.0 VPP CAdj = 0.1 µF

45 35

15 0

101

10 20 30 40 50 60 70 80 90 100 110 120 130

102

103

104

105

Temperature (°C)

Frequency (Hz)



300

3.5

200

3.3

106

3.1

100

2.9

0 ISC (A)


55

25

40

Load Step (mA)

65

VOUT = 3.3 V

–100

COUT = CIN = 22 µF Tantalum CAdj = 0.1 µF

–200

2.7 2.5 2.3 2.1

1000

1.9

500

1.7 1.5

0 0

1

2

3

4

5

6

7

8

9

10

1.0

1.5

2.0

2.5

3.0

3.5

Time (µS)

VIN – VOUT (V)



4.0

APPLICATIONS INFORMATION A resistor divider network R1 and R2 causes a fixed current to flow to ground. This current creates a voltage across R2 that adds to the 1.25 V across R1 and sets the overall output voltage. The adjust pin current (typically 50 µA) also flows through R2 and adds a small error that should be taken into account if precise adjustment of VOUT is necessary. The output voltage is set according to the formula:

The CS5201–1 linear regulator provides adjustable voltages at currents up to 1.0 A. The regulator is protected against overcurrent conditions and includes thermal shutdown. The CS5201–1 has a composite PNP–NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section. Adjustable Operation

VOUT + VREF

The CS5201–1 has an output voltage range of 1.25 V to 5.5 V. An external resistor divider sets the output voltage as shown in Figure 11. The regulator maintains a fixed 1.25V (typical) reference between the output pin and the adjust pin.

) R2Ǔ ǒR1 R1 ) IAdj

R2

The term IAdj × R2 represents the error added by the adjust pin current.


CS5201–1 illustrated in Figure 12; however, the design of clamp circuitry must be done on an application by application basis. Care must be taken to ensure the clamp actually protects the design. Components used in the clamp design must be able to withstand the short circuit condition indefinitely while protecting the IC.

R1 is chosen so that the minimum load current is at least 2.0 mA. R1 and R2 should be the same type, e.g. metal film for best tracking over temperature. While not required, a bypass capacitor from the adjust pin to ground will improve ripple rejection and transient response. A 0.1 µF tantalum capacitor is recommended for “first cut” design. Type and value may be varied to obtain optimum performance vs. price. VIN

EXTERNAL SUPPLY

VOUT VIN

VOUT

CS5201–1 VREF

C1 Adj

C2 R1

VIN

VAdj

IAdj CAdj

VOUT

R2

VOUT

Figure 11. Resistor Divider Scheme Figure 12. Short Circuit Protection Circuit for High Voltage Application.

Short Circuit Protection

The CS5201–1 linear regulator has an absolute maximum specification of 7.0 V for the voltage difference between VIN and VOUT. However, the IC may be used to regulate voltages in excess of 7.0 V. The main considerations in such a design are power–up and short circuit capability. In most applications, ramp–up of the power supply to VIN is fairly slow, typically on the order of several tens of milliseconds, while the regulator responds in less than one microsecond. In this case, the linear regulator begins charging the load as soon as the VIN to VOUT differential is large enough that the pass transistor conducts current. The load at this point is essentially at ground, and the supply voltage is on the order of several hundred millivolts, with the result that the pass transistor is in dropout. As the supply to VIN increases, the pass transistor will remain in dropout, and current is passed to the load until VOUT reaches the point at which the IC is in regulation. Further increase in the supply voltage brings the pass transistor out of dropout. The result is that the output voltage follows the power supply ramp–up, staying in dropout until the regulation point is reached. In this manner, any output voltage may be regulated. There is no theoretical limit to the regulated voltage as long as the VIN to VOUT differential of 7.0 V is not exceeded. However, the possibility of destroying the IC in a short circuit condition is very real for this type of design. Short circuit conditions will result in the immediate operation of the pass transistor outside of its safe operating area. Over–voltage stresses will then cause destruction of the pass transistor before overcurrent or thermal shutdown circuitry can become active. Additional circuitry may be required to clamp the VIN to VOUT differential to less than 7.0 V if failsafe operation is required. One possible clamp circuit is



ESR

For microprocessor applications it is customary to use an output capacitor network consisting of several tantalum and ceramic capacitors in parallel. This reduces the overall ESR and reduces the instantaneous output voltage drop under transient load conditions. The output capacitor network should be as close to the load as possible for the best results.


CS5201–1 Protection Diodes

Calculating Power Dissipation and Heat Sink Requirements




VOUT VIN

VOUT

CS5201–1 C1

C2 Adj

These four are related by the equation

R1

TJ + TA ) PD

R2

CAdj

Output Voltage Sensing

(8)


) R2Ǔ ǒR1 R1


where RC = conductor parasitic resistance.

VIN

VIN

VOUT


CS5201–1 R1 Adj

(7)

PD(max) + {VIN(max) * VOUT(min)}IOUT(max) ) VIN(max)IQ

Since the CS5201–1 is a three terminal regulator, it is not possible to provide true remote load sensing. Load regulation is limited by the resistance of the conductors connecting the regulator to the load. For the adjustable regulator, the best load regulation occurs when R1 is connected directly to the output pin of the regulator as shown in Figure 14. If R1 is connected to the load, RC is multiplied by the divider ratio and the effective resistance between the regulator and the load becomes.

RC

RQJA

The maximum ambient temperature and the power dissipation are determined by the design while the maximum junction temperature and the thermal resistance depend on the manufacturer and the package type. The maximum power dissipation for a regulator is:

Figure 13. Protection Diode for Large Output Capacitors

RC

Maximum Ambient Temperature TA (°C) Power dissipation PD (Watts) Maximum junction temperature TJ (°C) Thermal resistance junction to ambient RΘJA (°C/W)

RLOAD

R2

Figure 14. Grounding Scheme for Adjustable Output Regulator to Minimize Parasitic Resistance Effects



(9)

CS5201–1 The value for RΘJA is calculated using equation (3) and the result can be substituted in equation (7). The value for RΘJC is 3.5°C/W for a given package type based on an average die size. For a high current regulator such as the CS5201–1 the majority of the heat is generated in the power transistor section. The value for RΘSA depends on the heat sink type, while RΘCS depends on factors such as package type, heat sink interface (is an insulator and

thermal grease used?), and the contact area between the heat sink and the package. Once these calculations are complete, the maximum permissible value of RΘJA can be calculated and the proper heat sink selected. For further discussion on heat sink selection, see application note “Thermal Management for Linear Regulators,” document number SR006AN/D, available through the Literature Distribution Center or via our website at http://onsemi.com.


Type

Description

CS5201–1GT3

1.0 A, Adj. Output


CS5201–1GDP3

1.0 A, Adj. Output

D2PAK 3–PIN

CS5201–1GDPR3

1.0 A, Adj. Output


CS5201–1GST3

1.0 A, Adj. Output

SOT–223

CS5201–1GSTR3

1.0 A, Adj. Output






1 1




TO–220 THREE LEAD

D2PAK 3–PIN

SOT–223

Unit

RΘJC

Typical

3.5

3.5

15

°C/W

RΘJA

Typical

50

10–50*

156

°C/W



+,$, # , ) ## ! The CS52015–3 linear regulator provides 1.5 A @ 3.3 V reference at 1.0 A with an output voltage accuracy of ±1.5 %. The regulator is intended for use as a post regulator and microprocessor supply. The fast loop response and low dropout voltage make this regulator ideal for applications where low voltage operation and good transient response are important. The circuit is designed to operate with dropout voltages less than 1.4 V at 1.5 A output current. The maximum quiescent current is only 10 mA at full load. Device protection includes over–current and thermal shutdown. The CS52015–3 is pin compatible with the LT1086 family of linear regulators but has lower dropout voltage. The regulator is available in TO–220, surface mount D2, and SOT–223 packages. Features • Output Current to 1.5 A • Output Accuracy to ±1.5% Over Temperature • Dropout Voltage (typical) 1.05 V @ 1.5 A • Fast Transient Response • Fault Protection – Current Limit – Thermal Shutdown

http://onsemi.com


12

2



3

1

23



VOUT

VIN

CS52015–3

3.3 V @ 1.5 A

GND 10 µF 5.0 V

22 µF 5.0 V

Package

Shipping

CS52015–3GT3

TO–220‡

50 Units/Rail

CS52015–3GDP3

D2PAK‡

50 Units/Rail

CS52015–3GDPR3

D2PAK‡

750 Tape & Reel

CS52015–3GST3

SOT–223‡

80 Units/Rail

CS52015–3GSTR3

SOT–223‡ 2500 Tape & Reel

*Additional ordering information can be found on page 653 of this data sheet. †Consult your local sales representative for other fixed output voltage versions. ‡TO–220 are all 3–pin, straight leaded. D2PAK and SOT–223 are all 3–pin.





648




ESD Damage Threshold

Value

Unit

7.0

V

–40 to +70

°C

150

°C

–60 to +150

°C

260 Peak 230 Peak

°C °C

2.0

kV



Test Conditions

Characteristic

Min

Typ

Max

Unit

3.250 (–1.5%)

3.300

3.350 (+1.5%)

V

Fixed Output Voltage Output Voltage (Notes 3 and 4)

VIN – VOUT = 1.5 V; 0 ≤ IOUT ≤ 1.5 A

Line Regulation


–

0.02

0.20

%



–

0.04

0.4

%


IOUT = 1.5 A

–

1.05

1.4

V

Current Limit


1.6

3.1

–

A

Quiescent Current

IOUT = 10 mA

–

5.0

10

mA



–

0.002

0.020

%/W



–

80

–

dB


–

150

180

210

°C


–

–

25

–

°C

3. Load regulation and output voltage are measured at a constant junction temperature by low duty cycle pulse testing. Changes in output voltage due to temperature changes must be taken into account seperately. 4. Specifications apply for an external Kelvin sense connection at a point on the output pin 1/4” from the bottom of the package. 5. Dropout voltage is a measurement of the minimum input/output differential at full load. 6. Guaranteed by design, not 100% tested in production. 7. Thermal shutdown is 100% functionally tested in production. PACKAGE PIN DESCRIPTION Package Pin Number TO–220

D2PAK

SOT–223

Pin Symbol

1

1

1

GND

Ground connection.

2

2

2

VOUT


3

3

3

VIN

Function

Input voltage.


CS52015–3

VOUT VIN


– +

Error Amplifier

Bandgap GND




0.08 1.00 VDROPOUT (V)

TCASE = 0°C

0.95

TCASE = 25°C

0.90 0.85 TCASE = 125°C

0.80

0.06 0.04 0.02 0.00 –0.02 –0.04 –0.06 –0.08 –0.10

0.75

–0.12 0

300

600

900

1200

1500

0

10 20 30 40 50 60 70 80 90 100 110 120 130

IOUT (mA)

TJ (°C)



3.5

85

3.3

75

2.9

55

ISC (A)


3.1 65

TCASE = 25°C

45 35


2.7 2.5 2.3 2.1 1.9

25 15

101

1.7 102

103

104

105

1.5

106

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

Frequency (Hz)

VIN – VOUT (V)




0.100

300 200


Load Step (mA)


CS52015–3

100 0

COUT = CIN = 22 µF Tantalum

–100 –200 1500

0.075

0.050 TCASE = 25°C

0.025 TCASE = 125°C

750 0 0

1

2

3

4

5

6

7

8

9

TCASE = 0°C

0.000

10

0

1

2

Time (µS)

Output Current (A)



APPLICATIONS INFORMATION The CS52015–3 linear regulator provides a 3.3 V output voltage at currents up to 1.5 A. The regulator is protected against overcurrent conditions and includes thermal shutdown. The CS52015–3 has a composite PNP–NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.

For microprocessor applications it is customary to use an output capacitor network consisting of several tantalum and ceramic capacitors in parallel. This reduces the overall ESR and reduces the instantaneous output voltage drop under transient load conditions. The output capacitor network should be as close to the load as possible for the best results. Protection Diodes





VOUT VIN

VOUT

CS52015–3 C1

C2 GND

ESR Figure 9. Protection Diode Scheme for Large Output Capacitors





VIN

VIN

VOUT

RC




CS52015–3 RLOAD







RQJA

(12)

(10)



CS52015–3


Type

Description

CS52015–3GT3

1.5 A, 3.3 V Output


CS52015–3GDP3

1.5 A, 3.3 V Output

D2PAK 3–PIN

CS52015–3GDPR3

1.5 A, 3.3 V Output


CS52015–3GST3

1.5 A, 3.3 V Output

SOT–223

CS52015–3GSTR3

1.5 A, 3.3 V Output





CS 52015–3 AWLYWW CS52015–3 AWLYWW

1 1




TO–220 THREE LEAD

D2PAK 3–PIN

SOT–223

Unit

RΘJC

Typical

3.5

3.5

15

°C/W

RΘJA

Typical

50

10–50*

156

°C/W



+,$, , ! The CS52015–1 linear regulator provides 1.5 A with an accuracy of ±1.0 %. The device uses two external resistors to set the output voltage within a 1.25 V to 5.5 V range. The regulator is intended for use as a post regulator and microprocessor supply. The fast loop response and low dropout voltage make this regulator ideal for applications where low voltage operation and good transient response are important. The circuit is designed to operate with dropout voltages less than 1.4 V at 1.5 A output current. Device protection includes overcurrent and thermal shutdown. The CS52015–1 is pin compatible with the LT1086 family of linear regulators but has lower dropout voltage. The regulator is available in TO–220, surface mount D2, and SOT–223 packages. Features • Output Current to 1.5 A • Output Accuracy to ±1.0% Over Temperature • Dropout Voltage (typical) 1.05 V @ 1.5 A • Fast Transient Response • Fault Protection – Current Limit – Thermal Shutdown

http://onsemi.com


12

2



3

1

23


ORDERING INFORMATION*† 5.0 V

Device

VOUT

VIN

3.3 V @ 1.5 A

CS52015–1 124 Ω 1.0%

Adj

10 µF 5.0 V

0.1 µF 5.0 V Tantalum

200 Ω 1.0%

Package

Shipping

CS52015–1GT3

TO–220‡

50 Units/Rail

CS52015–1GDP3

D2PAK‡

50 Units/Rail

CS52015–1GDPR3

D2PAK‡

750 Tape & Reel

SOT–223‡

80 Units/Rail

CS52015–1GST3

22 µF 5.0 V

CS52015–1GSTR3 SOT–223‡

2500 Tape & Reel

*Additional ordering information can be found on page 660 of this data sheet. †Consult your local sales representative for fixed output voltage versions. ‡TO–220 are all 3–pin, straight leaded. D2PAK and SOT–223 are all 3–pin.

Figure 1. Application Diagram DEVICE MARKING INFORMATION See general marking information in the device marking section on page 660 of this data sheet.



654





Value

Unit

7.0

V

–40 to +70

°C

150

°C

–60 to +150

°C

260 Peak 230 Peak

°C °C

2.0

kV



Test Conditions

Characteristic

Min

Typ

Max

Unit

1.241 (–1.0%)

1.254

1.266 (+1.0%)

V



Line Regulation


–

0.02

0.20

%



–

0.04

0.4

%


IOUT = 1.5 A

–

1.05

1.4

V

Current Limit

VIN – VOUT = 3.0 V; TJ ≥ 25°C

1.6

3.1

–

A


VIN = 7.0 V, VAdj = 0 V

–

0.6

2.0

mA

Adjust Pin Current


–

50

100

µA



–

0.002

0.020

%/W



–

80

–

dB


–

150

180

210

°C


–

–

25

–

°C

3. Load regulation and output voltage are measured at a constant junction temperature by low duty cycle pulse testing. Changes in output voltage due to temperature changes must be taken into account seperately. 4. Specifications apply for an external Kelvin sense connection at a point on the output pin 1/4” from the bottom of the package. 5. Dropout voltage is a measurement of the minimum input/output differential at full load. 6. The minimum load current is the minimum current required to maintain regulation. Normally the current in the resistor divider used to set the output voltage is selected to meet the minimum requirement. 7. Guaranteed by design, not 100% tested in production. 8. Thermal shutdown is 100% functionally tested in production. PACKAGE PIN DESCRIPTION Package Pin Number TO–220

D2PAK

SOT–223

Pin Symbol

1

1

1

Adj

2

2

2

VOUT

3

3

3

VIN



CS52015–1

VOUT VIN


– +

Error Amplifier Adj

Bandgap




0.08 1.00 VDROPOUT (V)

TCASE = 0°C

TCASE = 25°C

0.95 0.90 0.85

TCASE = 125°C

0.80

0.06 0.04 0.02 0.00 –0.02 –0.04 –0.06 –0.08 –0.10

0.75

–0.12 300

0

600

900

1200

1500

0

TJ (°C)




10 20 30 40 50 60 70 80 90 100 110 120 130

IOUT (mA)

0.075

0.050 TCASE = 25°C

0.025 TCASE = 125°C

0

TCASE = 0°C

0.55

TCASE = 125°C

0.50

0.45 CIN = COUT = 22 µF Tantalum

TCASE = 0°C

0.000

TCASE = 25°C

0.60

1

0.40 2

1

2

3

4

5

6

Output Current (A)

VIN – VOUT (V)




7

CS52015–1 85

70 IO = 10 mA



65 60 55 50 45

TCASE = 25°C

IOUT = 1.5 A (VIN – VOUT) = 3.0 V VRIPPLE = 1.0 VPP CAdj = 0.1 µF

45 35

15 0

101

10 20 30 40 50 60 70 80 90 100 110 120 130

102

103

104

105

Temperature (°C)

Frequency (Hz)



300

3.5

200

3.3

106

3.1

100

2.9

0 ISC (A)


55

25

40

Load Step (mA)

65

VOUT = 3.3 V

–100

COUT = CIN = 22 µF Tantalum CAdj = 0.1 µF

–200

2.7 2.5 2.3 2.1

1500

1.9

750

1.7 1.5

0 0

1

2

3

4

5

6

7

8

9

10

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

Time (µS)

VIN – VOUT (V)



APPLICATIONS INFORMATION A resistor divider network R1 and R2 causes a fixed current to flow to ground. This current creates a voltage across R2 that adds to the 1.25 V across R1 and sets the overall output voltage. The adjust pin current (typically 50 µA) also flows through R2 and adds a small error that should be taken into account if precise adjustment of VOUT is necessary. The output voltage is set according to the formula:

The CS52015–1 linear regulator provides adjustable voltages at currents up to 1.5 A. The regulator is protected against overcurrent conditions and includes thermal shutdown. The CS52015–1 has a composite PNP–NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.

VOUT + VREF

Adjustable Operation

) R2Ǔ ǒR1 R1 ) IAdj

R2

The term IAdj × R2 represents the error added by the adjust pin current.

The CS52015–1 has an output voltage range of 1.25 V to 5.5 V. An external resistor divider sets the output voltage as shown in Figure 11. The regulator maintains a fixed 1.25V (typical) reference between the output pin and the adjust pin.


CS52015–1 illustrated in Figure 12; however, the design of clamp circuitry must be done on an application by application basis. Care must be taken to ensure the clamp actually protects the design. Components used in the clamp design must be able to withstand the short circuit condition indefinitely while protecting the IC.

R1 is chosen so that the minimum load current is at least 2.0 mA. R1 and R2 should be the same type, e.g. metal film for best tracking over temperature. While not required, a bypass capacitor from the adjust pin to ground will improve ripple rejection and transient response. A 0.1 µF tantalum capacitor is recommended for “first cut” design. Type and value may be varied to obtain optimum performance vs. price. VIN

EXTERNAL SUPPLY

VOUT VIN

VOUT

CS52015–1 VREF

C1 Adj

C2 R1

VIN

VAdj

IAdj CAdj

VOUT

R2

VOUT

Figure 11. Resistor Divider Scheme Short Circuit Protection

Figure 12. Short Circuit Protection Circuit for High Voltage Application.

The CS52015–1 linear regulator has an absolute maximum specification of 7.0 V for the voltage difference between VIN and VOUT. However, the IC may be used to regulate voltages in excess of 7.0 V. The main considerations in such a design are power–up and short circuit capability. In most applications, ramp–up of the power supply to VIN is fairly slow, typically on the order of several tens of milliseconds, while the regulator responds in less than one microsecond. In this case, the linear regulator begins charging the load as soon as the VIN to VOUT differential is large enough that the pass transistor conducts current. The load at this point is essentially at ground, and the supply voltage is on the order of several hundred millivolts, with the result that the pass transistor is in dropout. As the supply to VIN increases, the pass transistor will remain in dropout, and current is passed to the load until VOUT reaches the point at which the IC is in regulation. Further increase in the supply voltage brings the pass transistor out of dropout. The result is that the output voltage follows the power supply ramp–up, staying in dropout until the regulation point is reached. In this manner, any output voltage may be regulated. There is no theoretical limit to the regulated voltage as long as the VIN to VOUT differential of 7.0 V is not exceeded. However, the possibility of destroying the IC in a short circuit condition is very real for this type of design. Short circuit conditions will result in the immediate operation of the pass transistor outside of its safe operating area. Over–voltage stresses will then cause destruction of the pass transistor before overcurrent or thermal shutdown circuitry can become active. Additional circuitry may be required to clamp the VIN to VOUT differential to less than 7.0 V if failsafe operation is required. One possible clamp circuit is



ESR

For microprocessor applications it is customary to use an output capacitor network consisting of several tantalum and ceramic capacitors in parallel. This reduces the overall ESR and reduces the instantaneous output voltage drop under transient load conditions. The output capacitor network should be as close as possible to the load for the best results.


CS52015–1 Protection Diodes





VOUT VIN

VOUT

CS52015–1 C1

C2 Adj

These four are related by the equation

R1

TJ + TA ) PD

R2

CAdj


(14)


) R2Ǔ ǒR1 R1



VIN

VIN

VOUT


CS52015–1 R1 Adj

(13)



RC

RQJA


Figure 13. Protection Diode for Large Output Capacitors

RC


RLOAD

R2




(15)

CS52015–1 The value for RΘJA is calculated using equation (3) and the result can be substituted in equation (13). The value for RΘJC is 3.5°C/W for a given package type based on an average die size. For a high current regulator such as the CS52015–1 the majority of the heat is generated in the power transistor section. The value for RΘSA depends on the heat sink type, while RΘCS depends on factors such as package type, heat sink interface (is an insulator and

thermal grease used?), and the contact area between the heat sink and the package. Once these calculations are complete, the maximum permissible value of RΘJA can be calculated and the proper heat sink selected. For further discussion on heat sink selection, see application note “Thermal Management for Linear Regulators,” document number SR006AN/D, available through the Literature Distribution Center or via our website at http://onsemi.com.


Type

Description

CS52015–1GT3

1.5 A, Adj. Output


CS52015–1GDP3

1.5 A, Adj. Output

D2PAK 3–PIN

CS52015–1GDPR3

1.5 A, Adj. Output


CS52015–1GST3

1.5 A, Adj. Output

SOT–223

CS52015–1GSTR3

1.5 A, Adj. Output





CS 52015–1 AWLYWW CS52015–1 AWLYWW

1 1




TO–220 THREE LEAD

D2PAK 3–PIN

SOT–223

Unit

RΘJC

Typical

3.5

3.5

15

°C/W

RΘJA

Typical

50

10–50*

156

°C/W



+,$# # # ) ## ! The CS5203–3 linear regulator provides 3.3 V reference at 3.0 A with an output voltage accuracy of ±1.5 %. This regulator is intended for use as a post regulator and microprocessor supply. The fast loop response and low dropout voltage make this regulator ideal for applications where low voltage operation and good transient response are important. The circuit is designed to provide 3.0 A of output current with dropout voltages of less than 1.15 V. The maximum quiescent current is only 10 mA at full load. Device protection includes over–current and thermal shutdown. The CS5203–3 is pin compatible with the LT1085 family of linear regulators. The regulator is available in a surface mount D2 package. Features Output Current to 3.0 A Output Accuracy to ±1.5% Over Temperature Dropout Voltage (typical) 1.15 V @ 3.0 A Fast Transient Response Fault Protection – Current Limit – Thermal Shutdown

• • • • •

http://onsemi.com

12


3

D2PAK 3–PIN DP SUFFIX CASE 418E

MARKING DIAGRAM

CS5203–3 AWLYWW

1 VOUT

VIN 5.0 V

CS5203–3

A WL, L YY, Y WW, W

3.3 V @ 3.0 A

GND 100 µF 5.0 V

10 µF 5.0 V




Package

Shipping

CS5203–3GDP3

D2PAK‡

50 Units/Rail

CS5203–3GDPR3

D2PAK‡

750 Tape & Reel

*Additional ordering information can be found on page 665 of this data sheet. †Consult your local sales representative for other package options. ‡D2PAK are all 3–pin.



661





Value

Unit

7.0

V

–40 to +70

°C

150

°C

–60 to +150

°C

230 Peak

°C

2.0

kV

1. 60 second maximum above 183°C *The maximum package power dissipation must be observed.

ELECTRICAL CHARACTERISTICS (CIN = 10 µF, COUT = 22 µF Tantalum, VOUT + VDROPOUT < VIN < 7.0 V, 0°C ≤ TA ≤ 70°C, TJ ≤ +150°C, unless otherwise specified, Ifull load = 3.0 A) Characteristic

Test Conditions

Min

Typ

Max

Unit

3.250 (–1.5%)

3.300

3.350 (+1.5%)

V


VIN – VOUT = 1.5 V; 0 ≤ IOUT ≤ 3.0 A

Line Regulation


–

0.02

0.20

%



–

0.04

0.4

%


IOUT = 3.0 A

–

1.15

1.4

V

Current Limit


3.1

4.6

–

A

Quiescent Current

IOUT = 10 mA

–

6.0

10

mA



–

0.002

0.020

%/W



–

80

–

dB


–

150

180

210

°C


–

–

25

–

°C

2. Load regulation and output voltage are measured at a constant junction temperature by low duty cycle pulse testing. Changes in output voltage due to temperature changes must be taken into account seperately. 3. Specifications apply for an external Kelvin sense connection at a point on the output pin 1/4” from the bottom of the package. 4. Dropout voltage is a measurement of the minimum input/output differential at full load. 5. Guaranteed by design, not tested in production. 6. Thermal shutdown is 100% functionally tested in production. PACKAGE PIN DESCRIPTION Package Pin Number D2PAK

Pin Symbol

1

GND

Ground connection.

2

VOUT


3

VIN

Function

Input voltage.


CS5203–3

VOUT VIN


– +

Error Amplifier

Bandgap Reference GND


TYPICAL PERFORMANCE CHARACTERISTICS +0.3

1.20

1.10

Reference Voltage Deviation (%)

Dropout Voltage (V)

1.15 TCASE = 0°C

1.05 1.00 0.95 0.90

TCASE = 125°C

TCASE = 25°C

0.85 0.80 0.75

+0.1 0 –0.1 –0.2 –0.3

0

0.30 0.60 0.90 1.20 1.50 1.80 2.10 2.40 2.70 3.00

0

30

60

90

120

Output Current (A)

TJ (°C)


Figure 4. Output Voltage Deviation vs. Temperature

0.16

85 75

0.12



+0.2

0.08 TCASE = 25°C

0.04 TCASE = 125°C

0

55 TCASE = 25°C

45 35


25 TCASE = 0°C

0.00

65

1.5

15

101

3

102

103

104

105

Output Current (A)

Frequency (Hz)




106

CS5203–3

+200

5

0 4

–200 ISC (A)

∆VOUT (mV)

6

VIN = 5.0 V

VOUT = 3.3 V CIN = 100 µF COUT = 10 mF Tantalum

I (A)

3

3 2

2 1

1 0 0

5

0

1.0

10

1.5

2.0

2.5

3.0

Time (µs)

VIN – VOUT (V)



3.5

APPLICATIONS INFORMATION The CS5203–3 linear regulator provides a fixed 3.3 V output voltage at currents up to 3.0 A. The regulator is protected against overcurrent conditions and includes thermal shutdown. The CS5203–3 has a composite PNP–NPN output transistor and requires an output capacitor for stability.



Protection Diodes

The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response, and loop stability. The capacitor value and type is based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution. However, when the circuit operates at low temperatures, both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet provides this information. A 22 µF tantalum capacitor will work for most applications, but with high current regulators such as the CS5203–3 the transient response and stability improve with higher values of capacitance. The majority of applications for this regulator involve large changes in load current so the output capacitor must supply the instantaneous load current. The ESR of the output capacitor causes an immediate drop in output voltage given by:


DV + DI


VOUT VIN

VOUT

CS5203–3 C1

C2 GND

ESR

Figure 9. Protection Diode Scheme for Large Output Capacitors





VIN

VIN

VOUT

RC




CS5203–3 RLOAD







RQJA

(16)


ADDITIONAL ORDERING INFORMATION Orderable Part Number CS5203–3GDP3 CS5203–3GDPR3

(18)

Type

Description

3.0 A, 3.3 V Output

D2PAK

3–PIN

3.0 A, 3.3 V Output

D2PAK

3–PIN (Tape & Reel)


CS5203–3


D2PAK, 3–PIN

Unit

RΘJC

Typical

3.5

°C/W

RΘJA

Typical

10–50*

°C/W



+,$# ) +,$# $) +,$# #) +,$# , # ) , ) ## ,

! The CS5203A series of linear regulators provides 3.0 A at adjustable and fixed voltages with an accuracy of ±1.0% and ±2.0% respectively. The adjustable version uses two external resistors to set the output voltage within a 1.25 V to 13 V range. The regulators are intended for use as post regulators and microprocessor supplies. The fast loop response and low dropout voltage make these regulators ideal for applications where low voltage operation and good transient response are important. The circuit is designed to operate with dropout voltages as low as 1.0 V depending on the output current level. The maximum quiescent current is only 10 mA at full load. The regulators are fully protected against overload conditions with protection circuitry for Safe Operating Area (SOA), overcurrent and thermal shutdown. The CS5203A is pin compatible with the LT1085 family of linear regulators but has lower dropout voltage. The regulators are available in TO–220 and surface mount D2PAK packages.

12

2


3 D2PAK 3–PIN DPS SUFFIX CASE 418F

3

Device

VOUT

Output Current Limit – +

Error Amplifier

Bandgap

Adj

Tab = VOUT Pin 1. Adj 2. VOUT 3. VIN Fixed Output Tab = VOUT Pin 1. GND 2. VOUT 3. VIN

Package

Shipping

CS5203A–1GT3

TO–220†

50 Units/Rail

CS5203A–1GDP3

D2PAK†

50 Units/Rail

CS5203A–1GDPR3

D2PAK†

750 Tape & Reel

CS5203A–2GT3

TO–220†

50 Units/Rail

CS5203A–2GDP3

D2PAK†

50 Units/Rail

CS5203A–2GDPR3

D2PAK†

750 Tape & Reel

CS5203A–2GDPSR3

D2PAK†

750 Tape & Reel

CS5203A–3GT3

TO–220†

50 Units/Rail

CS5203A–3GDP3

D2PAK†

50 Units/Rail

CS5203A–3GDPR3

D2PAK†

750 Tape & Reel

CS5203A–3GDPSR3

D2PAK†

750 Tape & Reel

CS5203A–5GT3

TO–220†

50 Units/Rail

*Additional ordering information can be found on page 674 of this data sheet. †TO–220 is 3–pin, straight leaded. D2PAK are all 3–pin.

DEVICE MARKING INFORMATION

Figure 1. Block Diagram – CS5203A–1


1

Adjustable Output


VIN



12

Features • Output Current to 3.0 A • Output Trimmed to ±1.0% • Dropout Voltage 1.05 V @ 3.0 A • Fast Transient Response • Fault Protection Circuitry – Thermal Shutdown – Overcurrent Protection – Safe Area Protection

Thermal Shutdown

http://onsemi.com


667

Publication Order Number: CS5203A/D

CS5203A–1, CS5203A–2, CS5203A–3, CS5203A–5

VOUT VIN


– + Error Amplifier

Bandgap GND

Figure 2. Block Diagram – CS5203A–2, –3, –5 ABSOLUTE MAXIMUM RATINGS* Parameter Supply Voltage, VCC Operating Temperature Range Junction Temperature Storage Temperature Range Lead Temperature Soldering:


Value

Unit

17

V

–40 to +70

°C

150

°C

–60 to +150

°C

260 Peak 230 Peak

°C


ELECTRICAL CHARACTERISTICS (CIN = 10 µF, COUT = 22 µF Tantalum, VIN – VOUT = 3.0 V, VIN ≤ 15 V, 0°C ≤ TA ≤ 70°C, TJ ≤ +150°C, unless otherwise specified, Ifull load = 3.0 A.) Characteristic

Test Conditions

Min

Typ

Max

Unit

1.241 (–1%)

1.254

1.266 (+1%)

V

Adjustable Output Voltage (CS5203A–1) Reference Voltage (Notes 3 and 4)

VIN – VOUT = 1.5 V; VAdj = 0 V, 10 mA ≤ IOUT ≤ 3.0 A

Line Regulation


–

0.04

0.20

%



–

0.03

0.4

%


IOUT = 3.0 A

–

1.05

1.15

V

Current Limit

VIN – VOUT = 3.0 V; TJ ≥ 25°C VIN – VOUT = 15 V

3.2 –

5.5 2.5

– –

A A

Minimum Load Current


–

1.2

6.0

mA

–

50

100

µA

Adjust Pin Current

–

Adjust Pin Current Change

1.5 V ≤ VIN – VOUT ≤ 4.0 V; 10 mA ≤ IOUT ≤ 3.0 A

–

0.2

5.0

µA

Thermal Regulation

30 ms pulse; TA = 25°C

–

0.003

–

%/W

3. Load regulation and output voltage are measured at a constant junction temperature by low duty cycle pulse testing. Changes in output voltage due to thermal gradients or temperature changes must be taken into account separately. 4. Specifictions apply for an external Kelvin sense connection at a point on the output pin 1/4” from the bottom of the package. 5. Dropout voltage is a measurement of the minimum input/output differentail at full load.


CS5203A–1, CS5203A–2, CS5203A–3, CS5203A–5 ELECTRICAL CHARACTERISTICS (continued) (CIN = 10 µF, COUT = 22 µF Tantalum, VIN – VOUT = 3.0 V, VIN ≤ 15 V, 0°C ≤ TA ≤ 70°C, TJ ≤ +150°C, unless otherwise specified, Ifull load = 3.0 A.)

Test Conditions

Characteristic

Min

Typ

Max

Unit

–

85

–

dB

–

0.5

–

%

–

0.003

–

%VOUT

Adjustable Output Voltage (CS5203A–1) (continued) f = 120 Hz; CAdj = 25 µF; IOUT = 3.0 A

Ripple Rejection Temperature Stability

– 10 Hz ≤ f ≤ 10 kHz; TA = 25°C

RMS Output Noise Thermal Shutdown

–

150

180

–

°C

Thermal Shutdown Hysteresis

–

–

25

–

°C

ELECTRICAL CHARACTERISTICS (CIN = 10 µF, COUT = 22 µF Tantalum, VIN – VOUT = 3.0 V, VIN ≤ 15 V, 0°C ≤ TA ≤ 70°C, TJ ≤ +150°C, unless otherwise specified, Ifull load = 3.0 A.) Test Conditions

Characteristic

Min

Typ

Max

Unit

4.9 (–2%) 3.234 (–2%) 1.47 (–2%)

5.0 3.3 1.5

5.1 (+2%) 3.366 (+2%) 1.53 (+2%)

V V V

Fixed Output Voltage (CS5203A–2, CS5203A–3, CS5203A–5) Reference Voltage (Notes 6 and 7) CS5203A–5 CS5203A–3 CS5203A–2

VIN – VOUT = 1.5 V; 0 ≤ IOUT ≤ 3.0A VIN – VOUT = 1.5 V; 0 ≤ IOUT ≤ 3.0A VIN – VOUT = 1.5 V; 0 ≤ IOUT ≤ 3.0A

Line Regulation


–

0.04

0.20

%



–

0.03

0.4

%


IOUT = 3.0 A

–

1.05

1.15

V

Current Limit


3.2 –

5.5 2.5

– –

A A

Quiescent Current

VIN ≤ 9.0 V; IOUT = 10 mA

–

5.0

10

mA

Thermal Regulation


–

0.003

–

%/W

Ripple Rejection

f = 120 Hz; IOUT = 3.0 A

–

78

–

dB

–

0.5

–

%

–

0.003

–

%VOUT


–

RMS Output Noise (%VOUT)

10 Hz ≤ f ≤ 10 kHz

Thermal Shutdown

–

150

180

–

°C


–

–

25

–

°C

6. Load regulation and output voltage are measured at a constant junction temperature by low duty cycle pulse testing. Changes in output voltage due to thermal gradients or temperature changes must be taken into account separately. 7. Specifictions apply for an external Kelvin sense connection atr a point on the output pin 1/4” from the bottom of the package. 8. Dropout voltage is a measurement of the minimum input/output differentail at full load. PACKAGE PIN DESCRIPTION Package Pin Number CS5203A–1 D2PAK

CS5203A–2, –3, –5

TO–220

D2PAK

TO–220

Pin Symbol

Function

1

1

N/A

N/A

Adj

Adjust pin (low side of the internal reference).

2

2

2

2

VOUT

3

3

3

3

VIN

N/A

N/A

1

1

GND


Regulated output voltage (case). Input voltage. Ground connection.

CS5203A–1, CS5203A–2, CS5203A–3, CS5203A–5

1.15

0.10

1.10

0.08

1.05


Dropout Voltage (V)


TCASE = 0°C

1.00 0.95 0.90 TCASE = 25°C

0.85

TCASE = 125°C

0.80 0.75 0.70

0.06 0.04 0.02 0.00 –0.02 –0.04 –0.06 –0.08 –0.10 –0.12

0

1

2

3

0

Output Current (A)

TJ (°C)




10 20 30 40 50 60 70 80 90 100 110 120 130

0.075

0.050 TCASE = 125°C TCASE = 25°C

0.025

2.175 TCASE = 0°C

1.850 1.525 TCASE = 25°C

1.200 0.875 TCASE = 125°C

TCASE = 0°C

0.550

0.000 0

1

2

3

1

3

4

5

6

7

Output Current (A)

VIN – VOUT (V)


Figure 6. Minimum Load Current

8

9

100

70 IO = 10 mA

90

65



2

60 55 50

70 60 50 40 30 20

45

TCASE = 25°C


10 40

0

0

101

10 20 30 40 50 60 70 80 90 100 110 120 130

102

103

104

Temperature (°C)

Frequency (Hz)


Figure 8. Ripple Rejection vs. Frequency (Fixed Versions)


105

CS5203A–1, CS5203A–2, CS5203A–3, CS5203A–5 100 90 Ripple Rejection (dB)

80 70 60 50 40 30 20 10

TCASE = 25°C

IOUT = 3.0 A (VIN – VOUT) = 3.0 V VRIPPLE = 1.6 VPP CAdj = 25 µF

0

101

102

103

104

105

Frequency (Hz)

Figure 9. Ripple Rejection vs. Frequency (Adjustable Versions)

APPLICATIONS INFORMATION The CS5203A family of linear regulators provides fixed or adjustable voltages at currents up to 3.0 A. The regulators are protected against short circuit, and include thermal shutdown and safe area protection (SOA) circuitry. The SOA protection circuitry decreases the maximum available output current as the input–output differential voltage increases. The CS5203A has a composite PNP–NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.

VIN C1

VREF R1

C2

IAdj CAdj

R2

Figure 10. Resistor Divider Scheme for the Adjustable Version

The adjustable regulator (CS5203A–1) has an output voltage range of 1.25 V to 13 V. An external resistor divider sets the output voltage as shown in Figure 10. The regulator maintains a fixed 1.25 V (typical) reference between the output pin and the adjust pin. A resistor divider network R1 and R2 causes a fixed current to flow to ground. This current creates a voltage across R2 that adds to the 1.25 V across R1 and sets the overall output voltage. The adjust pin current (typically 50 µA) also flows through R2 and adds a small error that should be taken into account if precise adjustment of VOUT is necessary. The output voltage is set according to the formula: ) R2Ǔ ) I ǒR1 R1 Adj

VOUT

CS5203A–1 Adj


VOUT + VREF

VOUT

VIN


The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type is based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR, can cause instability. The aluminum electrolytic capacitor is the least expensive solution. However, when the circuit operates at low temperatures, both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet provides this information. A 22 µF tantalum capacitor will work for most applications, but with high current regulators such as the CS5203A the transient response and stability improve with higher values of capacitor. The majority of applications for this regulator involve large changes in load current so the output capacitor must supply the instantaneous load current.

R2

The term IAdj × R2 represents the error added by the adjust pin current. R1 is chosen so that the minimum load current is at least 10 mA. R1 and R2 should be the same type, e.g. metal film for best tracking over temperature. The adjust pin is bypassed to improve the transient response and ripple rejection of the regulator.


CS5203A–1, CS5203A–2, CS5203A–3, CS5203A–5 Output Voltage Sensing

The ESR of the output capacitor causes an immediate drop in output voltage given by: DV + DI

Since the CS5203A is a three terminal regulator, it is not possible to provide true remote load sensing. Load regulation is limited by the resistance of the conductors connecting the regulator to the load. For best results the fixed regulators should be connected as shown in Figure 13.

ESR

For microprocessor applications it is customary to use an output capacitor network consisting of several tantalum and ceramic capacitors in parallel. This reduces the overall ESR and reduces the instantaneous output voltage drop under load transient conditions. The output capacitor network should be as close as possible to the load for the best results.


VIN

VIN

VOUT

RC

CS5203A–X

RLOAD

Protection Diodes

When large external capacitors are used with a linear regulator it is sometimes necessary to add protection diodes. If the input voltage of the regulator gets shorted, the output capacitor will discharge into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage and the rate at which VIN drops. In the CS5203A–X family of linear regulators, the discharge path is through a large junction and protection diodes are not usually needed. If the regulator is used with large values of output capacitance and the input voltage is instantaneously shorted to ground, damage can occur. In this case, a diode connected as shown in Figures 11 and 12 is recommended.

Gnd

Figure 13. Conductor Parasitic Resistance can be Minimized with the Above Grounding Scheme for Fixed Output Regulators

For the adjustable regulator, the best load regulation occurs when R1 is connected directly to the output pin of the regulator as shown in Figure 14. If R1 is connected to the load, RC is multiplied by the divider ratio and the effective resistance between the regulator and the load becomes

IN4002 (optional) VIN

VIN C1

VOUT CS5203A–1

RC

VOUT

) R2Ǔ ǒR1 R1


Adj

R1

CAdj

C2 VIN

R2

VIN

RC

VOUT


CS5203A–1 R1 Adj

RLOAD

Figure 11. Protection Diode Scheme for Adjustable Output Regulator R2 IN4002 (optional) VIN

VOUT

VIN

VOUT

CS5203A–X C1 Gnd

Figure 14. Grounding Scheme for Adjustable Output Regulator to Minimize Parasitics

C2

Figure 12. Protection Diode Scheme for Fixed Output Regulators


CS5203A–1, CS5203A–2, CS5203A–3, CS5203A–5 Calculating Power Dissipation and Heat Sink Requirements


The CS5203A series of linear regulators includes thermal shutdown and current limit circuitry to protect the device. High power regulators such as these usually operate at high junction temperatures so it is important to calculate the power dissipation and junction temperatures accurately to ensure that an adequate heat sink is used. The case is connected to VOUT on the CS5203A, electrical isolation may be required for some applications. Thermal compound should always be used with high current regulators such as these. The thermal characteristics of an IC depend on the following four factors: 1. 2. 3. 4.



The value for RΘJA is calculated using equation (3) and the result can be substituted in equation (19). The value for RΘJC is normally quoted as a single figure for a given package type based on an average die size. For a high current regulator such as the CS5203A the majority of the heat is generated in the power transistor section. The value for RΘSA depends on the heat sink type, while RΘCS depends on factors such as package type, heat sink interface (is an insulator and thermal grease used?), and the contact area between the heat sink and the package. Once these calculations are complete, the maximum permissible value of RΘJA can be calculated and the proper heat sink selected. For further discussion on heat sink selection, see application note “Thermal Management for Linear Regulators,” document number SR006AN/D, available through the Literature Distribution Center or via our website at http://onsemi.com.

These four are related by the equation TJ + TA ) PD

RQJA

(21)

(19)

The maximum ambient temperature and the power dissipation are determined by the design while the maximum junction temperature and the thermal resistance depend on the manufacturer and the package type. The maximum power dissipation for a regulator is: PD(max) + {VIN(max) * VOUT(min)}IOUT(max) ) VIN(max)IQ (20)



CS5203A–1, CS5203A–2, CS5203A–3, CS5203A–5


Type

Description

CS5203A–1GT3

3.0 A, Adj. Output


CS5203A–1GDP3

3.0 A, Adj. Output

D2PAK 3–PIN

CS5203A–1GDPR3

3.0 A, Adj. Output


CS5203A–2GT3

3.0 A, 1.5 V Output


CS5203A–2GDP3

3.0 A, 1.5 V Output

D2PAK 3–PIN

CS5203A–2GDPR3

3.0 A, 1.5 V Output


CS5203A–2GDPSR3

3.0 A, 1.5 V Output


CS5203A–3GT3

3.0 A, 3.3 V Output


CS5203A–3GDP3

3.0 A, 3.3 V Output

D2PAK 3–PIN

CS5203A–3GDPR3

3.0 A, 3.3 V Output


CS5203A–3GDPSR3

3.0 A, 3.3 V Output


CS5203A–5GT3

3.0 A, 5.0 V Output




D2PAK 3–PIN DPS SUFFIX CASE 418F

CS 5203A–x AWLYWW

CS 5203A–x AWLYYWW

5203A–x AWLYWW

1 1 1

x A WL, L YY, Y WW, W

= 1, 2, 3, or 5 = Assembly Location = Wafer Lot = Year = Work Week


TO–220 THREE LEAD

D2PAK 3–PIN

Unit

RΘJC

Typical

1.6

1.6

°C/W

RΘJA

Typical

50

10–50*

°C/W



+,$,#- ' # * , $,

! . !( + / This new very low dropout linear regulator reduces total power dissipation in the application. To achieve very low dropout, the internal pass transistor is powered separately from the control circuitry. Furthermore, with the control and power inputs tied together, this device can be used in single supply configuration and still offer a better dropout voltage than conventional PNP–NPN based LDO regulators. In this mode the dropout is determined by the minimum control voltage. The CS5253B–8 is offered in a five–terminal D2PAK package, which allows for the implementation of a remote–sense pin permitting very accurate regulation of output voltage directly at the load, where it counts, rather than at the regulator. This remote sensing feature virtually eliminates output voltage variations due to load changes and resistive voltage drops. Typical load regulation measured at the sense pin is less than 1.0 mV for an output voltage of 2.5 V with a load step of 10 mA to 3.0 A. The CS5253B–8 has a very fast transient loop response. Internal protection circuitry provides for “bust–proof” operation, similar to three–terminal regulators. This circuitry, which includes overcurrent, short circuit, and overtemperature protection will self protect the regulator under all fault conditions. The CS5253B–8 is ideal for generating a 2.5 V supply to power graphics controllers used on VGA cards. Its remote sense and low value capacitance requirements make this a low cost high performance solution. The CS5253B–8 is optimized from the CS5253–1 to allow a lower value of output capacitor to be used at the expense of a slower transient response. Features VOUT Fixed @ 2.5 V ± 1.5% VPOWER Dropout < 0.40 V @ 3.0 A VCONTROL Dropout < 1.05 V @ 3.0 A 1.5% Trimmed Reference Fast Transient Response Remote Voltage Sensing Thermal Shutdown Current Limit Short Circuit Protection Drop–In Replacement for EZ1582 Backwards Compatible with 3–Pin Regulators Very Low Dropout Reduces Total Power Consumption

• • • • • • • • • • • •



http://onsemi.com

1 5 D2PAK 5–PIN DP SUFFIX CASE 936F

Tab = VOUT Pin 1. VSENSE 2. GND 3. VOUT 4. VCONTROL 5. VPOWER

MARKING DIAGRAM

CS 5253B–8 AWLYWW




Package

Shipping

CS5253B–8GDP5

D2PAK*

50 Units/Rail

CS5253B–8GDPR5

D2PAK*

750 Tape & Reel

*5–Pin.

675

Publication Order Number: CS5253B–8/D

CS5253B–8 RDIS +5.0 V

VCONTROL

2.5 V @ 3.0 A

VOUT VSENSE

CS5253B–8 +3.3 V 10 µF 10 V

VPOWER

GND

33 µF 5.0 V

CLOAD (Optional)

100 µF 5.0 V

GND

GND RDIS


ABSOLUTE MAXIMUM RATINGS* Rating

Value

Unit

VPOWER Input Voltage

6.0

V

VCONTROL Input Voltage

13

V

0 to 150

°C

–65 to +150

°C

2.0

kV

230 peak

°C

Operating Junction Temperature Range, TJ Storage Temperature Range ESD Damage Threshold Lead Temperature Soldering:



ELECTRICAL CHARACTERISTICS (0°C ≤ TA ≤ 70°C; 0°C ≤ TJ ≤ 150°C; VSENSE = VOUT and GND = 0 V; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

Output Voltage

VCONTROL = 3.9 V to 12 V, VPOWER = 3.13 V to 5.5 V, IOUT = 10 mA to 3.0 A

2.463 (–1.5%)

2.5

2.538 (+1.5%)

V

Line Regulation

VCONTROL = 3.9 V to 12 V, VPOWER = 3.13 V to 5.5 V, IOUT = 10 mA

–

0.02

0.2

%

Load Regulation

VCONTROL = 3.9 V, VPOWER = 3.13 V, IOUT = 10 mA to 3.0 A, with Remote Sense

–

0.04

0.3

%


VCONTROL = 5.0 V, VPOWER = 3.3 V, ∆VOUT = +1.0%

–

0

0

mA

Control Pin Current (Note 3)

VCONTROL = 3.9 V, VPOWER = 3.13 V, IOUT = 100 mA VCONTROL = 3.9 V, VPOWER = 3.13 V, IOUT = 3.0 A

– –

6.0 35

10 120

mA mA

Ground Pin Current

VCONTROL = 3.9 V, VPOWER = 3.13 V, IOUT = 10 mA

–

7

10

mA

Current Limit

VCONTROL = 3.9 V, VPOWER = 3.13 V, ∆VOUT = –4.0%

3.1

4.0

–

A

Short Circuit Current

VCONTROL = 3.9 V, VPOWER = 3.13 V, VOUT = 0 V

2.0

3.5

–

A

CS5253B–8

2. The minimum load current is the minimum current required to maintain regulation. 3. The VCONTROL pin current is the drive current required for the output transistor. This current will track output current with roughly a 1:100 ratio. The minimum value is equal to the quiescent current of the device.


CS5253B–8 ELECTRICAL CHARACTERISTICS (continued) (0°C ≤ TA ≤ 70°C; 0°C ≤ TJ ≤ 150°C; VSENSE = VOUT and GND = 0 V; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

CS5253B–8 Ripple Rejection (Note 4)

VCONTROL = VPOWER = 3.9 V, VRIPPLE = 1.0 VP–P @ 120 Hz, IOUT = 3.0 A

60

80

–

dB

Thermal Regulation


–

0.002

–

%/W

VCONTROL Dropout Voltage (Minimum VCONTROL – VOUT) (Note 5)

VPOWER = 3.13 V, IOUT = 100 mA VPOWER = 3.13 V, IOUT = 1.0 A VPOWER = 3.13 V, IOUT = 3.0 A

– – –

0.90 1.00 1.05

1.15 1.15 1.30

V V V

VPOWER Dropout Voltage (Minimum VPOWER – VOUT) (Note 5)

VCONTROL = 3.9 V, IOUT = 100 mA VCONTROL = 3.9 V, IOUT = 1.0 A VCONTROL = 3.9 V, IOUT = 3.0 A

– – –

0.05 0.15 0.40

0.15 0.25 0.60

V V V

RMS Output Noise

Freq = 10 Hz to 10 kHz, TA = 25°C

–

0.003

–

%VOUT


–

0.5

–

–

%


–

150

180

210

°C


–

–

25

–

°C

VCONTROL Supply Only Output Current

VCONTROL = 13 V, VPOWER Not Connected, GND = VOUT = VSENSE = 0 V

–

–

50

mA

VPOWER Supply Only Output Current

VPOWER = 6.0 V, VCONTROL Not Connected, GND = VOUT = VSENSE = 0 V

–

0.1

1.0

mA

4. This parameter is guaranteed by design and is not 100% production tested. 5. Dropout is defined as either the minimum control voltage (VCONTROL) or minimum power voltage (VPOWER) to output voltage differential required to maintain 1.5% regulation at a particular load current. 6. This parameter is guaranteed by design, but not parametrically tested in production. However, a 100% thermal shutdown functional test is performed on each part.

PACKAGE PIN DESCRIPTION PACKAGE PIN # D2PAK

PIN SYMBOL

1

VSENSE

2

GND

This pin is connected to system ground.

3

VOUT

This pin is connected to the emitter of the power pass transistor and provides a regulated voltage capable of sourcing 3.0 A of current.

4

VCONTROL

5

VPOWER

FUNCTION This Kelvin sense pin allows for remote sensing of the output voltage at the load for improved regulation. It is internally connected to the positive input of the voltage sensing error amplifier.

This is the supply voltage for the regulator control circuitry. For the device to regulate, this voltage should be between 0.9 V and 1.3 V (depending on the output current) greater than the output voltage. The control pin current will be about 1.0% of the output current. This is the power input voltage. This pin is physically connected to the collector of the power pass transistor. For the device to regulate, this voltage should be between 0.1 V and 0.6 V greater than the output voltage depending on the output current. The output load current of 3.0 A is supplied through this pin.


CS5253B–8

VPOWER VCONTROL

BIAS and TSD

– +

VREF

EA

IA

+ – VOUT VSENSE

GND



5.0

4.0 2.499

Output Current (A)


Measured at ∆VOUT = –1.5%

4.5

2.500

2.498 2.497 2.496

3.0 2.5 2.0 1.5 1.0

2.495 2.494

3.5

0.5 0

20

40

60

80

100

120

0

0


1

2

3

4

5

VPOWER – VOUT (V)

Figure 3. Output Voltage vs Junction Temperature

Figure 4. Output Current vs VPOWER – VOUT


6

CS5253B–8 3.9

15 A/µs

Short Circuit Output current Limit (A)

VCONTROL = 5.0 V VPOWER = 3.3 V VOUT = 2.5 V CCONTROL = 10 µF CADJ = 0.1 µF

VOUT CS5253–1 COUT = 330 µF

VOUT CS5253B–8 COUT = 33 µF

80 A/µs ILOAD 10 mA to 3.0 A

3.7 3.6 3.5 3.4 3.3

0

20

60

80

100

120

140

Figure 6. Short Circuit Output Current vs Junction Temperature

0.12

12

0.10

10

VCONTROL = 13 V VOUT = 0 V VPOWER Not Connected

TJ = 120°C 8

0.08 0.06 TJ = 20°C

6 4

0.04 TJ = 0°C

2

0.02 0

0

0.5

1.0

1.5

2.0

2.5

0

3.0

0

20

Output Current (A)

40

60

80

100

120

140


Figure 7. Load Regulation vs Output Current

Figure 8. VCONTROL Only Output Current vs Junction Temperature 30

500

VPOWER = 6.0 V VOUT = 0 V VCONTROL Not Connected

450 25

400 TJ = 120°C

350

20 IOUT (µA)

VPOWER Dropout Voltage (V)

40


IOUT (mA)

Load Regulation (%)

Figure 5. Transient Response Comparison between CS5253–1 and CS5253B–8

VCONTROL = 5.0 V VPOWER = 3.3 V

3.8

300 TJ = 0°C

250 200

TJ = 20°C

150

15 10

100

5

50 0

0 0

0.5

1.0

1.5

2.0

2.5

3.0

0

20

40

60

80

100

120

140


Output Current (A)

Figure 10. VPOWER Only Output Current vs Junction Temperature

Figure 9. VPOWER Dropout Voltage vs Output Current


CS5253B–8 90

5.0 VPOWER = 3.3 V VCONTROL = 5.0 V VOUT = 2.5 V TA = 25°C

70 Current Limit (A)


80

60 50 VIN – VOUT = 2.0 V IOUT = 3.0 A VRIPPLE = 1.0 VP–P COUT = 22 µF CADJ = 0.1 µF

40 30 20 10 101

102

103

104

105

4.5

4.0

3.5

106

0

0.5

1.0

Frequency (Hz)

2.0

1100

3.0

40 VPOWER = 2.05 V


35 TJ = 0°C

IOUT = 3.0 A

ICONTROL (mA)

30

1000

TJ = 20°C 900

25 20 15

IOUT = 1.0 A

10

TJ = 120°C

IOUT = 100 mA

5 800

2.5

Figure 12. Current Limit vs VOUT

Figure 11. Ripple Rejection vs Frequency

0

0.5

1.0

1.5

2.0

0

3.0

2.5

0

20

40

Output Current (A)

VPOWER = 3.3 V VCONTROL = 5.0 V ILOAD = 0 to 3.0 A

VOUT = 2.5 V VOUT Shorted to VSENSE TJ = 0°C to 150°C

4 Unstable 3 2 Stable Region 1 0

0

10

80

100

120

Figure 14. VCONTROL Supply Current vs Junction Temperature

6 5

60


Figure 13. VCONTROL Dropout Voltage vs Output Current

ESR (Ω)

VCONTROL Dropout Voltage (mV)

1.5 VOUT (V)

20

30

40

50

60

70

Capacitance (µF)

Figure 15. Stability vs ESR


80

90

100

140

CS5253B–8 APPLICATIONS NOTES THEORY OF OPERATION

DESIGN GUIDELINES

The CS5253B–8 linear regulator is fixed at 2.5 V at currents up to 3.0 A. The regulator is protected against short circuits, and includes a thermal shutdown circuit with hysteresis. The output, which is current limited, consists of a PNP–NPN transistor pair and requires an output capacitor for stability.

Remote Sense

Remote sense operation can be easily obtained with the CS5253B–8 but some care must be paid to the layout and positioning of the filter capacitors around the part. The ground side of the input capacitors on the +5.0 V and +3.3 V lines and the local VOUT–to–ground output capacitor on the IC must be tied close to the ground pin of the regulator. This will establish the stability of the part. The IC ground may then be connected to ground remotely at the load, giving the ground portion remote sense operation. The VSENSE line can then be tied remotely at the positive load connection, giving the feedback remote sense operation. The remote sense lines should be Kelvin connected so as to eliminate the effect of load current voltage drop. An optional bypass capacitor may be used at the load to reduce the effect of load variations and spikes.

VPOWER Function

The CS5253B–8 utilizes a two supply approach to maximize efficiency. The collector of the power device is brought out to the VPOWER pin to minimize internal power dissipation under high current loads. VCONTROL provides for the control circuitry and the drive for the output NPN transistor. VCONTROL should be at least 1.0 V greater than the output voltage. Special care has been taken to ensure that there are no supply sequencing problems. The output voltage will not turn on until both supplies are operating. If the control voltage comes up first, the output current will be limited to about three milliamperes until the power input voltage comes up. If the power input voltage comes up first, the output will not turn on at all until the control voltage comes up. The output can never come up unregulated. The CS5253B–8 can also be used as a single supply device with the control and power inputs tied together. In this mode, the dropout will be determined by the minimum control voltage.

Current Limit

The internal current limit circuit limits the output current under excessive load conditions. Short Circuit Protection

The device includes short circuit protection circuitry that clamps the output current at approximately 500mA less than its current limit value. This provides for a current foldback function, which reduces power dissipation under a direct shorted load.


The CS5253B–8 five terminal linear regulator includes a dedicated VSENSE function. This allows for true Kelvin sensing of the output voltage. This feature can virtually eliminate errors in the output voltage due to load regulation. Regulation will be optimized at the point where the sense pin is tied to the output.

Thermal Shutdown

The thermal shutdown circuitry is guaranteed by design to activate above a die junction temperature of approximately 150°C and to shut down the regulator output. This circuitry has 25°C of typical hysteresis, thereby allowing the regulator to recover from a thermal fault automatically.

RDIS +5.0 V

VCONTROL

+3.3 V

VPOWER

+Load

VOUT VSENSE

CS5253B–8 +

10 µF

+

GND 100 µF

+

33 µF

Remote Connections

+

Optional

Local Connections

–Load

GND RDIS

Figure 16. Remote Sense


CS5253B–8 Calculating Power Dissipation and Heat Sink Requirements

A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment has a thermal resistance which is measured in degrees per watt. Like series electrical resistances, these thermal resistances are summed to determine the total thermal resistance between the die junction and the surrounding air, RΘJA. This total thermal resistance is comprised of three components. These resistive terms are measured from junction to case (RΘJC), case to heat sink (RΘCS), and heat sink to ambient air (RΘSA). The equation is:

High power regulators such as the CS5253B–8 usually operate at high junction temperatures. Therefore, it is important to calculate the power dissipation and junction temperatures accurately to ensure that an adequate heat sink is used. Since the package tab is connected to VOUT on the CS5253B–8, electrical isolation may be required for some applications. Also, as with all high power packages, thermal compound in necessary to ensure proper heat flow. For added safety, this high current LDO includes an internal thermal shutdown circuit The thermal characteristics of an IC depend on the following four factors: junction temperature, ambient temperature, die power dissipation, and the thermal resistance from the die junction to ambient air. The maximum junction temperature can be determined by: TJ(max) + TA(max) ) PD(max)


The value for RΘJC is 2.5°C/watt for the CS5253B–8 in the D2PAK package. For a high current regulator such as the CS5253B–8 the majority of heat is generated in the power transistor section. The value for RΘSA depends on the heat sink type, while the RΘCS depends on factors such as package type, heat sink interface (is an insulator and thermal grease used?), and the contact area between the heat sink and the package. Once these calculations are complete, the maximum permissible value of RΘJA can be calculated and the proper heat sink selected. For further discussion on heat sink selection, see our application note “Thermal Management for Linear Regulators,” document number SR006AN/D, available through the Literature Distribution Center or via our website at http://www.onsemi.com.

RQJA

The maximum ambient temperature and the power dissipation are determined by the design while the maximum junction temperature and the thermal resistance depend on the manufacturer and the package type. The maximum power dissipation for a regulator is: PD(max) + (VIN(max) * VOUT(min))IOUT(max) ) VIN(max) IIN(max)


D2PAK, 5–Pin

Unit

RΘJC

Typical

2.5

°C/W

RΘJA

Typical

10–50*

°C/W



+,$# # ! The CS5203–1 linear regulator provides 3.0 A at adjustable output voltages with an accuracy of ±1.5 %. The device uses two external resistors to set the output voltage within a 1.25 V to 5.5 V range. The regulator is intended for use as a post regulator and microprocessor supply. The fast loop response and low dropout voltage make this regulator ideal for applications where low voltage operation and good transient response are important. The circuit is designed to operate with dropout voltages less than 1.4 V at 3.0 A output current. Device protection includes overcurrent and thermal shutdown. The CS5203–1 is pin compatible with the LT1085 family of linear regulators but has lower dropout voltage. The regulator is available in TO–220 and surface mount D2 packages.

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Features • Output Current to 3.0 A • Output Accuracy to ±1.5% Over Temperature • Dropout Voltage (typical) 1.2 V @ 3.0 A • Fast Transient Response • Fault Protection – Current Limit – Thermal Shutdown

12

5.0 V

124 Ω 1.0%

Adj

10 µF 5.0 V

0.1 µF 5.0 V

200 Ω 1.0%

D2PAK 3–PIN DP SUFFIX CASE 418E 3

Device

3.3 V @ 3.0 A

CS5203–1

3

ORDERING INFORMATION*†

VOUT

VIN

2


Package

Shipping

CS5203–1GT3

TO–220‡

50 Units/Rail

CS5203–1GDP3

D2PAK‡

50 Units/Rail

CS5203–1GDPR3

D2PAK‡

750 Tape & Reel

*Additional ordering information can be found on page 690 of this data sheet. †Consult your local sales representative for fixed output voltage versions. ‡TO–220 is 3–pin, straight leaded. D2PAK is a 3–pin.

22 µF 5.0 V





683


CS5203–1 ABSOLUTE MAXIMUM RATINGS* Parameter Supply Voltage, VIN Operating Temperature Range Junction Temperature Storage Temperature Range ESD Damage Threshold Lead Temperature Soldering:


Value

Unit

7.0

V

–40 to +70

°C

150

°C

–60 to +150

°C

2.0

kV

260 Peak 230 Peak

°C °C



Test Conditions

Characteristic

Min

Typ

Max

Unit

1.235 (–1.5%)

1.254

1.273 (+1.5%)

V



Line Regulation


–

0.02

0.20

%



–

0.04

0.4

%


IOUT = 3.0 A

–

1.15

1.40

V

Current Limit

VIN – VOUT = 3.0 V; TJ ≥ 25°C

3.1

4.6

–

A


VIN = 7.0 V, VAdj = 0 V

–

0.6

2.0

mA

Adjust Pin Current


–

50

100

µA



–

0.002

0.020

%/W



–

80

–

dB


–

150

180

210

°C


–

–

–

25

°C

3. Load regulation and output voltage are measured at a constant junction temperature by low duty cycle pulse testing. Changes in output voltage due to temperature changes must be taken into account seperately. 4. Specifications apply for an external Kelvin sense connection at a point on the output pin 1/4” from the bottom of the package. 5. Dropout voltage is a measurement of the minimum input/output differential at full load. 6. Minimum load current is defined as the minimum output current required to maintain regulation. The reference resistor in the output divider is usually sized to fulfill the minimum load current requirement. 7. Guaranteed by design, not 100% functionally tested in production. 8. Guaranteed by design, not 100% parametrically tested in production. However, every part is subject to functional testing for thermal shutdown. PACKAGE PIN DESCRIPTION Package Pin Number TO–220

D2PAK

Pin Symbol

1

1

Adj

2

2

VOUT

3

3

VIN



CS5203–1

VOUT VIN


– +

Error Amplifier

Bandgap Reference

Adj


TYPICAL PERFORMANCE CHARACTERISTICS +0.3

1.20

1.10

Reference Voltage Deviation (%)

Dropout Voltage (V)

1.15 TCASE = 0°C

1.05 1.00 0.95 0.90

TCASE = 125°C

TCASE = 25°C

0.85 0.80 0.75

+0.1 0 –0.1 –0.2 –0.3

0

0.30 0.60 0.90 1.20 1.50 1.80 2.10 2.40 2.70 3.00

0

30

60

90

120

Output Current (A)

TJ (°C)


Figure 4. Bandgap Reference Voltage Deviation vs. Temperature 0.65

90 Minimum Load Current (mA)


+0.2

70 60 50 40 30

0.60

0.55

TCASE = 25°C TCASE = 125°C

0.50 TCASE = 0°C

0.45

20 10

101

102

103

104

105

0.40

106

1

2

3

4

5

6

7

Frequency (Hz)

VIN – VOUT (V)




8

CS5203–1 68 TCASE = 125°C

66 Adjust Pin Current (µA)

Adjust Pin Current, IAdj (µA)

75

65

55

64 62 60 TCASE = 25°C

58 56 TCASE = 0°C

54

45 0

30

60

90

120

1

2

3

4

5

6

7

TA (°C)

VIN – VOUT (V)


Figure 8. Adjust Pin Current vs. VIN – VOUT

8

70.00 ∆VOUT (mV)

67.00 65.50 64.00

+200 0 –200 VIN = 5.0 V

62.50 61.00

VOUT = 3.3 V CIN = 100 µF COUT = 10 mF Tantalum

3 I (A)

59.50 58.00

2 1

56.50 55.00

0 0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.0

0

5

IOUT (A)

Time (µs)

Figure 9. Adjust Pin Current vs. Output Current


6 5 4 ISC (A)


68.50

3 2 1 0

1

2

3

4

5

6

VIN – VOUT (V)



7

10

CS5203–1 APPLICATIONS INFORMATION The CS5203–1 linear regulator provides adjustable voltages at currents up to 3.0 A. The regulator is protected against overcurrent conditions and includes thermal shutdown. The CS5203–1 has a composite PNP–NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.

In most applications, ramp–up of the power supply to VIN is fairly slow, typically on the order of several tens of milliseconds, while the regulator responds in less than one microsecond. In this case, the linear regulator begins charging the load as soon as the VIN to VOUT differential is large enough that the pass transistor conducts current. The load at this point is essentially at ground, and the supply voltage is on the order of several hundred millivolts, with the result that the pass transistor is in dropout. As the supply to VIN increases, the pass transistor will remain in dropout, and current is passed to the load until VOUT reaches the point at which the IC is in regulation. Further increase in the supply voltage brings the pass transistor out of dropout. The result is that the output voltage follows the power supply ramp–up, staying in dropout until the regulation point is reached. In this manner, any output voltage may be regulated. There is no theoretical limit to the regulated voltage as long as the VIN to VOUT differential of 7.0 V is not exceeded. However, the possibility of destroying the IC in a short circuit condition is very real for this type of design. Short circuit conditions will result in the immediate operation of the pass transistor outside of its safe operating area. Over–voltage stresses will then cause destruction of the pass transistor before overcurrent or thermal shutdown circuitry can become active. Additional circuitry may be required to clamp the VIN to VOUT differential to less than 7.0 V if failsafe operation is required. One possible clamp circuit is illustrated in Figure 13; however, the design of clamp circuitry must be done on an application by application basis. Care must be taken to ensure the clamp actually protects the design. Components used in the clamp design must be able to withstand the short circuit condition indefinitely while protecting the IC.


The CS5203–1 has an output voltage range of 1.25 V to 5.5 V. An external resistor divider sets the output voltage as shown in Figure 12. The regulator maintains a fixed 1.25V (typical) reference between the output pin and the adjust pin. A resistor divider network R1 and R2 causes a fixed current to flow to ground. This current creates a voltage across R2 that adds to the 1.25 V across R1 and sets the overall output voltage. The adjust pin current (typically 50 µA) also flows through R2 and adds a small error that should be taken into account if precise adjustment of VOUT is necessary. The output voltage is set according to the formula: ) R2Ǔ ǒR1 R1 ) IAdj

VOUT + VREF

R2

The term IAdj × R2 represents the error added by the adjust pin current. R1 is chosen so that the minimum load current is at least 2.0 mA. R1 and R2 should be the same type, e.g. metal film for best tracking over temperature. While not required, a bypass capacitor from the adjust pin to ground will improve ripple rejection and transient response. A 0.1 µF tantalum capacitor is recommended for “first cut” design. Type and value may be varied to obtain optimum performance vs. price. VIN

VOUT VIN

EXTERNAL SUPPLY

VOUT

CS5203–1 VREF

C1 Adj

C2 R1

IAdj CAdj

VIN

R2

VOUT VAdj

Figure 12. Resistor Divider Scheme VOUT

The CS5201–1 linear regulator has an absolute maximum specification of 7.0 V for the voltage difference between VIN and VOUT. However, the IC may be used to regulate voltages in excess of 7.0 V. The main considerations in such a design are power–up and short circuit capability.

Figure 13. Short Circuit Protection Circuit for High Voltage Application.


CS5203–1 Stability Considerations

The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response, and loop stability. The capacitor value and type is based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution. However, when the circuit operates at low temperatures, both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet provides this information. A 22 µF tantalum capacitor will work for most applications, but with high current regulators such as the CS5203–1 the transient response and stability improve with higher values of capacitor. The majority of applications for this regulator involve large changes in load current so the output capacitor must supply the instantaneous load current. The ESR of the output capacitor causes an immediate drop in output voltage given by: DV + DI


VOUT VIN

VOUT

CS5203–1 C1

C2 Adj

R1

R2

CAdj

Figure 14. Protection Diode Scheme for Large Output Capacitors Output Voltage Sensing


ESR


RC

) R2Ǔ ǒR1 R1


Protection Diodes


VIN

VIN

RC

VOUT


CS5203–1 R1 Adj

RLOAD

R2



CS5203–1 Calculating Power Dissipation and Heat Sink Requirements







RQJA

(24)

(22)




CS5203–1


Type

Description

CS5203–1GT3

3.0 A, Adj. Output


CS5203–1GDP3

3.0 A, Adj. Output

D2PAK 3–PIN

CS5203–1GDPR3

3.0 A, Adj. Output





1 1

A WL, L YY, Y WW, W



TO–220 THREE LEAD

D2PAK 3–PIN

Unit

RΘJC

Typical

3.5

3.5

°C/W

RΘJA

Typical

50

10–50*

°C/W



+,$,# # * ,

! This new very low dropout linear regulator reduces total power dissipation in the application. To achieve very low dropout, the internal pass transistor is powered separately from the control circuitry. Furthermore, with the control and power inputs tied together, this device can be used in single supply configuration and still offer a better dropout voltage than conventional PNP–NPN based LDO regulators. In this mode the dropout is determined by the minimum control voltage. The CS5253–1 is offered in a five–terminal D2PAK package, which allows for the implementation of a remote–sense pin permitting very accurate regulation of output voltage directly at the load, where it counts, rather than at the regulator. This remote sensing feature virtually eliminates output voltage variations due to load changes and resistive voltage drops. Typical load regulation measured at the sense pin is less than 1.0 mV for an output voltage of 2.5 V with a load step of 10 mA to 3.0 A. The CS5253–1 has a very fast transient loop response which can be adjusted using a small capacitor on the Adjust pin. Internal protection circuitry provides for “bust–proof” operation, similar to three–terminal regulators. This circuitry, which includes overcurrent, short circuit, and overtemperature protection will self protect the regulator under all fault conditions. The CS5253–1 is ideal for generating a 2.5 V supply to power graphics controllers used on VGA cards.

http://onsemi.com

1 5 D2PAK 5–PIN DP SUFFIX CASE 936F

Tab = VOUT Pin 1. VSENSE 2. Adjust 3. VOUT 4. VCONTROL 5. VPOWER

MARKING DIAGRAM

CS5253–1 AWLYWW

1

Features • VOUT Range Is 1.25 V to 5.0 V @ 3.0 A • VPOWER Dropout < 0.40 V @ 3.0 A • VCONTROL Dropout < 1.05 V @ 3.0 A • 1.0% Trimmed Reference • Fast Transient Response • Remote Voltage Sensing • Thermal Shutdown • Current Limit • Short Circuit Protection • Drop–In Replacement for EZ1582 • Backwards Compatible with 3–Pin Regulators • Very Low Dropout Reduces Total Power Consumption



A WL, L YY, Y WW, W



Package

Shipping

CS5253–1GDP5

D2PAK*

50 Units/Rail

CS5253–1GDPR5

D2PAK*

750 Tape & Reel

*5–Pin.

691


CS5253–1 5.0 V VCONTROL

VOUT

CS5253–1 2.5 V @ 3.0 A 3.3 V

VPOWER

VSENSE 124 1.0%

Adjust 10 µF 10 V

100 µF 5.0 V

124 1.0%

300 µF 5.0 V

Load



Value

Unit


6.0

V


13

V

0 to 150

°C

–65 to +150

°C

2.0

kV

230 peak

°C




ELECTRICAL CHARACTERISTICS (0°C ≤ TA ≤ 70°C; 0°C ≤ TJ ≤ 150°C; VSENSE = VOUT and VADJ = 0 V; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

Reference Voltage

VCONTROL = 2.75 V to 12 V, VPOWER = 2.05 V to 5.5 V, IOUT = 10 mA to 3.0 A

1.237 (–1.0%)

1.250

1.263 (+1.0%)

V

Line Regulation


–

0.02

0.2

%

Load Regulation


–

0.04

0.3

%



–

5.0

10

mA


VCONTROL = 2.75 V, VPOWER = 2.05 V, IOUT = 100 mA VCONTROL = 2.75 V, VPOWER = 2.05 V, IOUT = 3.0 A

– –

6.0 35

10 120

mA mA

Adjust Pin Current


–

60

120

µA

Current Limit


3.1

4.0

–

A



2.0

3.5

–

A


VCONTROL = VPOWER = 3.25 V, VRIPPLE = 1.0 VP–P @ 120 Hz, IOUT = 4.0 A, CADJ = 0.1 µF

60

80

–

dB

CS5253–1

2. The minimum load current is the minimum current required to maintain regulation. Normally the current in the resistor divider used to set the output voltage is selected to meet the minimum load current requirement. 3. The VCONTROL pin current is the drive current required for the output transistor. This current will track output current with roughly a 1:100 ratio. The minimum value is equal to the quiescent current of the device. 4. This parameter is guaranteed by design and is not 100% production tested.


CS5253–1 ELECTRICAL CHARACTERISTICS (continued) (0°C ≤ TA ≤ 70°C; 0°C ≤ TJ ≤ 150°C; VSENSE = VOUT and VADJ = 0 V; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

CS5253–1 Thermal Regulation


–

0.002

–

%/W


VPOWER = 2.05 V, IOUT = 100 mA VPOWER = 2.05 V, IOUT = 1.0 A VPOWER = 2.05 V, IOUT = 3.0 A

– – –

0.90 1.00 1.05

1.15 1.15 1.30

V V V


VCONTROL = 2.75 V, IOUT = 100 mA VCONTROL = 2.75 V, IOUT = 1.0 A VCONTROL = 2.75 V, IOUT = 3.0 A

– – –

0.05 0.15 0.40

0.15 0.25 0.60

V V V

RMS Output Noise


–

0.003

–

%VOUT


–

0.5

–

–

%


–

150

180

210

°C


–

–

25

–

°C


VCONTROL = 13 V, VPOWER Not Connected, VADJ = VOUT = VSENSE = 0 V

–

–

50

mA


VPOWER = 6.0 V, VCONTROL Not Connected, VADJ = VOUT = VSENSE = 0 V

–

0.1

1.0

mA

5. Dropout is defined as either the minimum control voltage (VCONTROL) or minimum power voltage (VPOWER) to output voltage differential required to maintain 1.0% regulation at a particular load current. 6. This parameter is guaranteed by design, but not parametrically tested in production. However, a 100% thermal shutdown functional test is performed on each part.

PACKAGE PIN DESCRIPTION PACKAGE PIN # D2PAK

PIN SYMBOL

1

VSENSE

This Kelvin sense pin allows for remote sensing of the output voltage at the load for improved regulation. It is internally connected to the positive input of the voltage sensing error amplifier.

2

Adjust

This pin is connected to the low side of the internally trimmed 1.0% bandgap reference voltage and carries a bias current of about 50 µA. A resistor divider from Adjust to VOUT and from Adjust to ground sets the output voltage. Also, transient response can be improved by adding a small bypass capacitor from this pin to ground.

3

VOUT


4

VCONTROL

5

VPOWER

FUNCTION

This is the supply voltage for the regulator control circuitry. For the device to regulate, this voltage should be between 0.9 V and 1.3 V (depending on the output current) greater than the output voltage. The control pin current will be about 1.0% of the output current. This is the power input voltage. This pin is physically connected to the collector of the power pass transistor. For the device to regulate, this voltage should be between 0.1 V and 0.6 V greater than the output voltage depending on the output current. The output load current of 3.0 A is supplied through this pin.


CS5253–1

VPOWER VCONTROL

BIAS and TSD

– +

VREF

EA

IA

+ – VOUT VSENSE Adjust


0.12

1.252

0.10 Load Regulation (%)

1.253

1.251 1.250 1.249 1.248 1.247

TJ = 120°C 0.08 0.06 TJ = 20°C 0.04 TJ = 0°C 0.02

0

20

40

60

80

100

0

120

0

0.5


1.0

1.5

2.0

2.5

3.0

Output Current (A)

Figure 3. Reference Voltage vs Junction Temperature


5.0 VCONTROL = 5.0 V VPOWER = 3.3 V VOUT = 2.5 V CCONTROL = 10 µF CPOWER = 100 µF CADJ = 0.1 µF COUT = 300 µF

Measured at ∆VOUT = –1.0%

4.5 4.0 Output Current (A)



VOUT

3.5 3.0 2.5 2.0 1.5 1.0

ILOAD, 10 mA to 3.0 A

0.5 0

0

1

2

3

4

5

VPOWER – VOUT (V)


Figure 6. Output Current vs VPOWER – VOUT


6

CS5253–1 85 Minimum Load Current (µA)

1200

IADJ (µA)

80

75

70

65

VPOWER = 3.3 V ∆VOUT = +1.0%

1150 1100 1050 1000 950 900 850

60

0

20

40

60

80

100

120

800 1.0

140

2.0

3.0



8.0

9.0

10

11


80

3.7 3.6 3.5 3.4

70 60 50 VIN – VOUT = 2.0 V IOUT = 4.0 A VRIPPLE = 1.0 VP–P COUT = 22 µF CADJ = 0.1 µF

40 30 20

0

20

40

60

80

100

120

10 101

140

102

103

104

105

106

Frequency (Hz)


Figure 9. Short Circuit Output Current vs Junction Temperature


1100

12 VCONTROL Dropout Voltage (mV)

VCONTROL = 13 V VOUT = 0 V VPOWER Not Connected

10 8 IOUT (mA)

7.0

90

3.8

6 4 2 0

6.0

Figure 8. Minimum Load Current vs VCONTROL – VOUT

3.9 Short Circuit Output current Limit (A)

5.0

VCONTROL – VOUT (V)

Figure 7. Adjust Pin Current vs Junction Temperature

3.3

4.0

0

20

40

60

80

100

120

140

VPOWER = 2.05 V TJ = 0°C 1000

TJ = 20°C 900 TJ = 120°C

800

0

0.5

1.0

1.5

2.0

2.5

Output Current (A)


Figure 11. VCONTROL Only Output Current vs Junction Temperature

Figure 12. VCONTROL Dropout Voltage vs Output Current


3.0

500

916.4

450

916.3 Minimum Load Current (µA)


CS5253–1

400 TJ = 120°C

350 300

TJ = 0°C

250 200

TJ = 20°C

150 100 50 0

VCONTROL = 5.0 V ∆VOUT = +1.0%

916.2 916.1 916.0 915.9 915.8 915.7 915.6 915.5

0

0.5

1.0

1.5

2.0

2.5

915.4 0.5

3.0

1.5

2.5 VPOWER – VOUT (V)

Output Current (A)

Figure 13. VPOWER Dropout Voltage vs Output Current

4.5

Figure 14. Minimum Load Current vs VPOWER – VOUT

30

40 VPOWER = 6.0 V VOUT = 0 V VCONTROL Not Connected ICONTROL (mA)

25 20 IOUT (µA)

3.5

15 10

35


30

IOUT = 3.0 A

25 20 15

IOUT = 1.0 A

10 5 0

IOUT = 100 mA

5 0

20

40

80

60

100

120

0

140

0

20


80

60

100

120

140


Figure 15. VPOWER Only Output Current vs Junction Temperature

Figure 16. VCONTROL Supply Current vs Junction Temperature

5.0

6 VPOWER = 3.3 V VCONTROL = 5.0 V VOUT = 2.5 V TA = 25°C

VPOWER = 3.3 V VCONTROL = 5.0 V ILOAD = 0 to 3.0 A

5

VOUT = 2.5 V VOUT Shorted to VSENSE TJ = 0°C to 150°C

4

4.5 ESR (Ω)

Current Limit (A)

40

Unstable 3 2

4.0

Stable Region 1 3.5

0

0.5

1.0

1.5

2.0

2.5

3.0

0

0

10

20

30

40

50

60

70

Capacitance (µF)

VOUT (V)

Figure 17. Current Limit vs VOUT

Figure 18. Stability vs ESR


80

90

100

CS5253–1 APPLICATIONS NOTES THEORY OF OPERATION

5.0 V

The CS5253–1 linear regulator provides adjustable voltages from 1.26 V to 5.0 V at currents up to 3.0 A. The regulator is protected against short circuits, and includes a thermal shutdown circuit with hysteresis. The output, which is current limited, consists of a PNP–NPN transistor pair and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.

VCONTROL

VOUT 2.5 V @ 3.0 A

CS5253–1 3.3 V VPOWER

VSENSE Adjust

R1

R2

VPOWER Function

The CS5253–1 utilizes a two supply approach to maximize efficiency. The collector of the power device is brought out to the VPOWER pin to minimize internal power dissipation under high current loads. VCONTROL provides for the control circuitry and the drive for the output NPN transistor. VCONTROL should be at least 1.0 V greater than the output voltage. Special care has been taken to ensure that there are no supply sequencing problems. The output voltage will not turn on until both supplies are operating. If the control voltage comes up first, the output current will be limited to about three milliamperes until the power input voltage comes up. If the power input voltage comes up first, the output will not turn on at all until the control voltage comes up. The output can never come up unregulated. The CS5253–1 can also be used as a single supply device with the control and power inputs tied together. In this mode, the dropout will be determined by the minimum control voltage.

Figure 19. Typical Application Schematic. The Resistor Divider Sets VOUT, With the Internal 1.260 V Reference Dropped Across R1.

A resistor divider network R1 and R2 causes a fixed current to flow to ground. This current creates a voltage across R2 that adds to the 1.260 V across R1 and sets the overall output voltage. The adjust pin current (typically 50 µA) also flows through R2 and adds a small error that should be taken into account if precise adjustment of VOUT is necessary. The output voltage is set according to the formula: VOUT + 1.260 V

R1 ) R2 ) R2 R1

IADJ

The term IADJ × R2 represents the error added by the adjust pin current. R1 is chosen so that the minimum load current is at least 10 mA. R1 and R2 should be of the same composition for best tracking over temperature. The divider resistors should be placed physically as close to the load as possible. While not required, a bypass capacitor connected between the adjust pin and ground will improve transient response and ripple rejection. A 0.1 µF tantalum capacitor is recommended for “first cut” design. Value and type may be varied to optimize performance vs. price.


The CS5253–1 five terminal linear regulator includes a dedicated VSENSE function. This allows for true Kelvin sensing of the output voltage. This feature can virtually eliminate errors in the output voltage due to load regulation. Regulation will be optimized at the point where the sense pin is tied to the output. DESIGN GUIDELINES Adjustable Operation

Other Adjustable Operation Considerations

This LDO adjustable regulator has an output voltage range of 1.26 V to 5.0 V. An external resistor divider sets the output voltage as shown in Figure 19. The regulator’s voltage sensing error amplifier maintains a fixed 1.260 V reference between the output pin and the adjust pin.

The CS5253–1 linear regulator has an absolute maximum specification of 6.0 V for the voltage difference between VPOWER and VOUT. However, the IC may be used to regulate voltages in excess of 6.0 V. The two main


CS5253–1 series resistance), ESL (equivalent series inductance), and variation over temperature. Tantalum and aluminum electrolytic capacitors work best, with electrolytic capacitors being less expensive in general, but varying more in capacitor value and ESR over temperature. The CS5253–1 requires an output capacitor to guarantee loop stability. The Stability vs ESR graph in the typical performance section shows the minimum ESR needed to guarantee stability, but under ideal conditions. These include: having VOUT connected to VSENSE directly at the IC pins; the compensation capacitor located right at the pins with a minimum lead length; the adjust feedback resistor divider ground, (bottom of R2 in Figure 19), connected right at the capacitor ground; and with power supply decoupling capacitors located close to the IC pins. The actual performance will vary greatly with board layout for each application. In particular, the use of the remote sensing feature will require a larger capacitor with less ESR. For most applications, a minimum of 33 µF tantalum or 150 µF aluminum electrolytic, with an ESR less than 1.0 Ω over temperature, is recommended. Larger capacitors and lower ESR will improve stability. The load transient response, during the time it takes the regulator to respond, is also determined by the output capacitor. For large changes in load current, the ESR of the output capacitor causes an immediate drop in output voltage given by:

considerations in such a design are the sequencing of power supplies and short circuit capability. Power supply sequencing should be such that the VCONTROL supply is brought up coincidentally with or before the VPOWER supply. This allows the IC to begin charging the output capacitor as soon as the VPOWER to VOUT differential is large enough that the pass transistor conducts. As VPOWER increases, the pass transistor will remain in dropout, and current is passed to the load until VOUT is in regulation. Further increase in the supply voltage brings the pass transistor out of dropout. In this manner, any output voltage less than 13 V may be regulated, provided the VPOWER to VOUT differential is less than 6.0 V. In the case where VCONTROL and VPOWER are shorted, there is no theoretical limit to the regulated voltage as long as the VPOWER to VOUT differential of 6.0 V is not exceeded. There is a possibility of damaging the IC when VPOWER – VOUT is greater than 6.0 V if a short circuit occurs. Short circuit conditions will result in the immediate operation of the pass transistor outside of its safe operating area. Overvoltage stresses will then cause destruction of the pass transistor before overcurrent or thermal shutdown circuitry can become active. Additional circuitry may be required to clamp the VPOWER to VOUT differential to less than 6.0 V if fail safe operation is required. One possible clamp circuit is illustrated in Figure 20; however, the design of clamp circuitry must be done on an application by application basis. Care must be taken to ensure the clamp actually protects the design. Components used in the clamp design must be able to withstand the short circuit condition indefinitely while protecting the IC.

DV + DI

DV + DI External Supply

TńC

where T is the time for the regulation loop to begin to respond. The very fast transient response time of the CS5253–1 allows the ESR effect to dominate. For microprocessor applications, it is customary to use an output capacitor network consisting of several tantalum and ceramic capacitors in parallel. This reduces the overall ESR and reduces the instantaneous output voltage drop under transient load conditions. The output capacitor network should be as close to the load as possible for the best transient response.

External Supply VCONTROL

ESR

There is then an additional drop in output voltage given by:

VSENSE

CS5253–1 VPOWER VOUT VADJ

Protection Diodes

When large external capacitors are used with a linear regulator, it is sometimes necessary to add protection diodes. If the input voltage of the regulator gets shorted, the output capacitor will discharge into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage, and the rate at which VCONTROL drops. In the CS5253–1 regulator, the discharge path is through a large junction and protection diodes are not usually needed. If the regulator is used with large values of output capacitance and the input voltage is instantaneously shorted to ground, damage can occur. In this case, a diode connected as shown in Figure 21 is recommended.

Figure 20. This Circuit Is an Example of How the CS5253–1 Can Be Short–Circuit Protected When Operating With VOUT > 6.0 V Stability Considerations

The output compensation capacitor helps determine three main characteristics of a linear regulator: loop stability, start–up delay, and load transient response. Different capacitor types vary widely in tolerance, ESR (equivalent


CS5253–1

VCONTROL

important to calculate the power dissipation and junction temperatures accurately to ensure that an adequate heat sink is used. Since the package tab is connected to VOUT on the CS5253–1, electrical isolation may be required for some applications. Also, as with all high power packages, thermal compound in necessary to ensure proper heat flow. For added safety, this high current LDO includes an internal thermal shutdown circuit The thermal characteristics of an IC depend on the following four factors: junction temperature, ambient temperature, die power dissipation, and the thermal resistance from the die junction to ambient air. The maximum junction temperature can be determined by:

VOUT

CS5253–1 VPOWER

VSENSE Adjust

TJ(max) + TA(max) ) PD(max)

Figure 21. Diode Protection Circuit


A rule of thumb useful in determining if a protection diode is required is to solve for current: I+C

RQJA

V T

where: I is the current flow out of the load capacitance when VCONTROL is shorted, C is the value of load capacitance V is the output voltage, and T is the time duration required for VCONTROL to transition from high to being shorted. If the calculated current is greater than or equal to the typical short circuit current value provided in the specifications, serious thought should be given to the use of a protection diode.

PD(max) + (VIN(max) * VOUT(min))IOUT(max) ) VIN(max) IIN(max)


Current Limit



The device includes short circuit protection circuitry that clamps the output current at approximately 500 mA less than its current limit value. This provides for a current foldback function, which reduces power dissipation under a direct shorted load.

The value for RQJC is 2.5°C/watt for the CS5253–1 in the D2PAK package. For a high current regulator such as the CS5253–1 the majority of heat is generated in the power transistor section. The value for RΘSA depends on the heat sink type, while the RΘCS depends on factors such as package type, heat sink interface (is an insulator and thermal grease used?), and the contact area between the heat sink and the package. Once these calculations are complete, the maximum permissible value of RΘJA can be calculated and the proper heat sink selected. For further discussion on heat sink selection, see our application note “Thermal Management for Linear Regulators,” document number SR006AN/D, available through the Literature Distribution Center or via our website at http://www.onsemi.com.

Thermal Shutdown

The thermal shutdown circuitry is guaranteed by design to activate above a die junction temperature of approximately 150°C and to shut down the regulator output. This circuitry has 25°C of typical hysteresis, thereby allowing the regulator to recover from a thermal fault automatically. Calculating Power Dissipation and Heat Sink Requirements

High power regulators such as the CS5253–1 usually operate at high junction temperatures. Therefore, it is


CS5253–1 PACKAGE THERMAL DATA Parameter

D2PAK, 5–Pin

Unit

RΘJC

Typical

2.5

°C/W

RΘJA

Typical

10–50*

°C/W



+,$0 $ 0 ) , ! The CS5204–2 linear regulator provides 4.0 A @ 1.5 V with an accuracy of ±2.0 %. The fast loop response and low dropout voltage make this regulator ideal for GTL bus termination where low voltage operation and good transient response are important. The circuit is designed to operate with dropout voltages as low as 1.0 V depending on the output current level. The maximum quiescent current is only 10 mA at full load. The regulator is fully protected against overload conditions with protection circuitry for Safe Operating Area (SOA), overcurrent and thermal shutdown. The regulator is available in TO–220 and surface mount D2 packages.

http://onsemi.com


Features • Output Current to 4.0 A • Output Voltage Trimmed to ±2.0% • Dropout Voltage (typical) 1.10 V @ 4.0 A • Fast Transient Response • Fault Protection Circuitry – Thermal Shutdown – Overcurrent Protection – Safe Area Protection

12

2


3 D2PAK 3–PIN D2T SUFFIX CASE 418E

3

MARKING DIAGRAMS D2PAK

TO–220


VOUT VIN

1 1 A WL, L YY, Y WW, W





Bandgap GND


Package

Shipping

CS5204–2GT3

TO–220†

50 Units/Rail

CS5204–2GDP3

D2PAK†

50 Units/Rail

CS5204–2GDPR3

D2PAK†

750 Tape & Reel

*Additional ordering information can be found on page 705 of this data sheet. † TO–220 are all 3–pin, straight leaded. D2PAK are all 3–pin.



701




Value

Unit

17

V

–40 to +70

°C

150

°C

–60 to +150

°C

260 Peak 230 Peak

°C °C


ELECTRICAL CHARACTERISTICS (CIN = 10 µF, COUT = 22 µF Tantalum, VIN – VOUT = 3.0 V, VIN ≤ 10 V, 0°C ≤ TA ≤ 70°C, TJ ≤ +150°C, unless otherwise specified, Ifull load = 4.0 A) Characteristic

Test Conditions

Min

Typ

Max

Unit

1.47 (–2.0%)

1.50

1.53 (+2.0%)

V

CS5204–2 Output Voltage (Notes 3 and 4)

VIN – VOUT = 1.5 V; 0 ≤ IOUT ≤ 4.0 A

Line Regulation


–

0.04

0.20

%



–

0.05

0.4

%


IOUT = 4.0 A

–

1.1

1.2

V

Current Limit


4.5 –

8.5 2.5

– –

A A

Quiescent Current


–

5.0

10

mA

Thermal Regulation


–

0.003

–

%/W

Ripple Rejection

f = 120 Hz; IOUT = 4.0 A

–

75

–

dB

–

–

0.5

–

%

–

0.003

–

%/VOUT

Temperature Stability RMS Output Noise (%VOUT)

10 Hz ≤ f ≤ 10 kHz

Thermal Shutdown

–

150

180

–

°C


–

–

25

–

°C

3. Load regulation and output voltage are measured at a constant junction temperature by low duty cycle pulse testing. Changes in output voltage due to thermal gradients or temperature changes must be taken into account seperately. 4. Specifications apply for an external Kelvin sense connection at a point on the output pin 1/4” from the bottom of the package. 5. Dropout voltage is a measurement of the minimum input/output differential at full load. PACKAGE PIN DESCRIPTION Package Pin Number TO–220

D2PAK

Pin Symbol

1

1

GND

Ground connection.

2

2

VOUT


3

3

VIN

Function

Input voltage.


CS5204–2 TYPICAL PERFORMANCE CHARACTERISTICS 0.10

1.15


1.20

Dropout Voltage (V)

1.10 TCASE = 0°C

1.05 1.00 0.95 0.90

TCASE = 125°C

TCASE = 25°C

0.85 0.80 0.75

0.06 0.04 0.02 0.00 –0.02 –0.04 –0.06 –0.08 –0.10 –0.12

0.70 0

1

2

3

0

4

TJ (°C)


Figure 3. Reference Voltage vs. Temperature 2.500

0.200 Minimum Load Current (mA)

0.175 0.150 0.125 0.100 TCASE = 25°C

0.075 0.050 TCASE = 125°C

0.025

2.175 TCASE = 0°C

1.850 1.525 TCASE = 25°C

1.200 0.875 TCASE = 125°C

TCASE = 0°C

0.550

0.000 0

1

2

3

4

1

2

3

4

5

6

7

VIN – VOUT (V)

Output Current (A)



100 90 80 Ripple Rejection (dB)


10 20 30 40 50 60 70 80 90 100 110 120 130

Output Current (A)

70 60 50 40 30 20

TCASE = 25°C


10 0

101

102

103

104

Frequency (Hz)



105

8

9

CS5204–2 APPLICATIONS INFORMATION Protection Diodes

The CS5204–2 linear regulator provides fixed 1.5 V voltage at currents up to 4.0 A. The regulator is protected against short circuit, and includes thermal shutdown and safe area protection (SOA) circuitry. The SOA protection circuitry decreases the maximum available output current as the input–output differential voltage increase. The CS5204–2 has a composite PNP–NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.





VOUT VIN

VOUT

CS5204–2 C1

C2 GND

Figure 7. Protection Diode Scheme Output Voltage Sensing


ESR

VIN


VIN

VOUT

RC


CS5204–2 GND

RLOAD

Figure 8. Conductor Parasitic Resistance Effects Can Be Minimized With the Above Grounding Scheme




The CS5204–2 linear regulator includes thermal shutdown and safe operating area circuitry to protect the device. High power regulators such as these usually operate at high junction temperatures so it is important to calculate the power dissipation and junction temperatures accurately to ensure that an adequate heat sink is used. The case is connected to VOUT on the CS5204–2, electrical isolation may be required for some applications. Thermal compound should always be used with high current regulators such as these. The thermal characteristics of an IC depend on the following four factors: 1. 2. 3. 4.



The value for RΘJA is calculated using equation (3) and the result can be substituted in equation (25). RΘJC is 1.6°C/Watt for the CS5204–2. For a high current regulator such as the CS5204–2 the majority of the heat is generated in the power transistor section. The value for RΘSA depends on the heat sink type, while RΘCS depends on factors such as package type, heat sink interface (is an insulator and thermal grease used?), and the contact area between the heat sink and the package. Once these calculations are complete, the maximum permissible value of RΘJA can be calculated and the proper heat sink selected. For further discussion on heat sink selection, see application note “Thermal Management for Linear Regulators,” document number SR006AN/D, available through the Literature Distribution Center or via our website at http://onsemi.com.


RQJA

(25)




(27)

Type

Description

CS5204–2GT3

4.0 A, 1.5 V Output


CS5204–2GDP3

4.0 A, 1.5 V Output

D2PAK 3–PIN

CS5204–2GDPR3

4.0 A, 1.5 V Output



CS5204–2


TO–220 THREE LEAD

D2PAK 3–PIN

Unit

RΘJC

Typical

1.6

1.6

°C/W

RΘJA

Typical

50

10–50*

°C/W



+,$0 ) +,$0 #) +,$0 , 0 ) ## ,

! The CS5204–x series of linear regulators provides 4.0 A at adjustable and fixed voltages with an accuracy of ±1.0% and ±2.0% respectively. The adjustable version uses two external resistors to set the output voltage within a 1.25 V to 13 V range. The regulators are intended for use as post regulators and microprocessor supplies. The fast loop response and low dropout voltage make these regulators ideal for applications where low voltage operation and good transient response are important. The circuit is designed to operate with dropout voltages as low as 1.0 V depending on the output current level. The maximum quiescent current is only 10 mA at full load. The regulators are fully protected against overload conditions with protection circuitry for Safe Operating Area (SOA), overcurrent and thermal shutdown. The regulators are available in TO–220 and surface mount D2PAK packages.

http://onsemi.com

Adjustable Output TO–220 THREE LEAD T SUFFIX CASE 221A 1

12

2

Fixed Output



3


TO–220

Features • Output Current to 4.0 A • Output Trimmed to ±1.0% • Dropout Voltage 1.10 V @ 4.0 A • Fast Transient Response • Fault Protection Circuitry – Thermal Shutdown – Overcurrent Protection – Safe Area Protection


CS5204–X AWLYWW CS5204–X AWLYWW

1 1 A WL, L YY, Y WW, W VOUT



VIN Device


– +

Error Amplifier

Bandgap


Shipping

CS5204–1GT3

TO–220†

50 Units/Rail

CS5204–1GDP3

D2PAK†

50 Units/Rail

CS5204–1GDPR3

D2PAK†

750 Tape & Reel

CS5204–3GT3

TO–220†

50 Units/Rail

CS5204–3GDP3

D2PAK†

50 Units/Rail

CS5204–3GDPR3

D2PAK†

750 Tape & Reel

CS5204–5GT3

TO–220†

50 Units/Rail

Adj

Figure 1. Block Diagram – CS5204–1


Package


707


CS5204–1, CS5204–3, CS5204–5

VOUT VIN



Bandgap GND

Figure 2. Block Diagram – CS5204–3, –5 ABSOLUTE MAXIMUM RATINGS* Parameter Supply Voltage, VCC Operating Temperature Range Junction Temperature Storage Temperature Range Lead Temperature Soldering:


Value

Unit

17

V

–40 to +70

°C

150

°C

–60 to +150

°C

260 Peak 230 Peak

°C



Test Conditions

Min

Typ

Max

Unit

1.241 (–1%)

1.254

1.266 (+1%)

V

Adjustable Output Voltage (CS5204–1) Reference Voltage (Notes 3 and 4)


Line Regulation


–

0.04

0.20

%



–

0.05

0.4

%


IOUT = 4.0 A

–

1.1

1.2

V

Current Limit

VIN – VOUT = 3.0 V; TJ ≥ 25°C VIN – VOUT = 9.0 V

4.5 –

8.5 1.0

– –

A A



–

1.2

6.0

mA

–

50

100

µA

Adjust Pin Current

–



–

0.2

5.0

µA

Thermal Regulation


–

0.003

–

%/W



CS5204–1, CS5204–3, CS5204–5 ELECTRICAL CHARACTERISTICS (continued) (CIN = 10 µF, COUT = 22 µF Tantalum, VIN – VOUT = 3.0 V, VIN ≤ 15 V, 0°C ≤ TA ≤ 70°C, TJ ≤ +150°C, unless otherwise specified, Ifull load = 4.0 A.)

Test Conditions

Characteristic

Min

Typ

Max

Unit

–

82

–

dB

–

0.5

–

%

–

0.003

–

%VOUT

Adjustable Output Voltage (CS5204–1) (continued) f = 120 Hz; CAdj = 25 µF; IOUT = 4.0 A


– 10 Hz ≤ f ≤ 10 kHz; TA = 25°C


–

150

180

–

°C


–

–

25

–

°C


Characteristic

Min

Typ

Max

Unit

4.9 (–2%) 3.234 (–2%)

5.0 3.3

5.1 (+2%) 3.366 (+2%)

V V

Fixed Output Voltage (CS5204–3, CS5204–5) Reference Voltage (Notes 6 and 7) CS5204–5 CS5204–3

VIN – VOUT = 1.5 V; 0 ≤ IOUT ≤ 4.0 A VIN – VOUT = 1.5 V; 0 ≤ IOUT ≤ 4.0 A

Line Regulation


–

0.04

0.20

%



–

0.05

0.4

%


IOUT = 4.0 A

–

1.1

1.2

V

Current Limit


4.5 –

8.5 1.0

– –

A A

Quiescent Current


–

5.0

10

mA

Thermal Regulation


–

0.003

–

%/W

Ripple Rejection

f = 120 Hz; IOUT = 4.0 A

–

75

–

dB

–

0.5

–

%

–

0.003

–

%VOUT


–


10 Hz ≤ f ≤ 10 kHz

Thermal Shutdown

–

150

180

–

°C


–

–

25

–

°C

6. Load regulation and output voltage are measured at a constant junction temperature by low duty cycle pulse testing. Changes in output voltage due to thermal gradients or temperature changes must be taken into account separately. 7. Specifictions apply for an external Kelvin sense connection atr a point on the output pin 1/4” from the bottom of the package. 8. Dropout voltage is a measurement of the minimum input/output differentail at full load. PACKAGE PIN DESCRIPTION Package Pin Number CS5204–1 D2PAK

CS5204–3, –5

TO–220

D2PAK

TO–220

Pin Symbol

Function

1

1

N/A

N/A

Adj


2

2

2

2

VOUT

3

3

3

3

VIN

N/A

N/A

1

1

GND



CS5204–1, CS5204–3, CS5204–5 TYPICAL PERFORMANCE CHARACTERISTICS 0.10

1.15


1.20

Dropout Voltage (V)

1.10 1.05

TCASE = 0°C

1.00 0.95 0.90

TCASE = 125°C

TCASE = 25°C

0.85 0.80 0.75

0.06 0.04 0.02 0.00 –0.02 –0.04 –0.06 –0.08 –0.10 –0.12

0.70 0

1

2

3

4

0

Output Current (A)

TJ (°C)


Figure 4. Reference Voltage vs. Temperature

0.200

2.500

0.175

Minimum Load Current (mA)


10 20 30 40 50 60 70 80 90 100 110 120 130

0.150 0.125 0.100 0.075

TCASE = 25°C

0.050 TCASE = 125°C

0.025

2.175 TCASE = 0°C

1.850 1.525 TCASE = 25°C

1.200 0.875 TCASE = 125°C

TCASE = 0°C

0.550

0 0

1

2

3

4

1

3

4

5

6

7

Output Current (A)

VIN – VOUT (V)



8

9

100

70 IO = 10 mA

90

65



2

60 55 50

70 60 50 40 30 20

45

TCASE = 25°C


10 40

0

0

101

10 20 30 40 50 60 70 80 90 100 110 120 130

102

103

104

Temperature (°C)

Frequency (Hz)




105

CS5204–1, CS5204–3, CS5204–5 100 90 Ripple Rejection (dB)

80 70 60 50 40 30 20 10

TCASE = 25°C


0

101

102

103

104

105

Frequency (Hz)


APPLICATIONS INFORMATION The CS5204–x family of linear regulators provides fixed or adjustable voltages at currents up to 4.0 A. The regulators are protected against short circuit, and include thermal shutdown and safe area protection (SOA) circuitry. The SOA protection circuitry decreases the maximum available output current as the input–output differential voltage increases. The CS5204–x has a composite PNP–NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.

VIN C1

VREF R1

C2

IAdj CAdj

R2


The adjustable regulator (CS5204–1) has an output voltage range of 1.25 V to 13 V. An external resistor divider sets the output voltage as shown in Figure 10. The regulator maintains a fixed 1.25 V (typical) reference between the output pin and the adjust pin. A resistor divider network R1 and R2 causes a fixed current to flow to ground. This current creates a voltage across R2 that adds to the 1.25 V across R1 and sets the overall output voltage. The adjust pin current (typically 50 µA) also flows through R2 and adds a small error that should be taken into account if precise adjustment of VOUT is necessary. The output voltage is set according to the formula: ) R2Ǔ ) I ǒR1 R1 Adj

VOUT

CS5204–1 Adj


VOUT + VREF

VOUT

VIN


The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type is based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR, can cause instability. The aluminum electrolytic capacitor is the least expensive solution. However, when the circuit operates at low temperatures, both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet provides this information. A 22 µF tantalum capacitor will work for most applications, but with high current regulators such as the CS5204–x the transient response and stability improve with higher values of capacitor. The majority of applications for this regulator involve large changes in load current so the output capacitor must supply the instantaneous load current.

R2



CS5204–1, CS5204–3, CS5204–5 Output Voltage Sensing


Since the CS5204–x is a three terminal regulator, it is not possible to provide true remote load sensing. Load regulation is limited by the resistance of the conductors connecting the regulator to the load. For best results the fixed regulators should be connected as shown in Figure 13.

ESR



VIN

VIN

VOUT

RC

CS5204–x

RLOAD

Protection Diodes

When large external capacitors are used with a linear regulator it is sometimes necessary to add protection diodes. If the input voltage of the regulator gets shorted, the output capacitor will discharge into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage and the rate at which VIN drops. In the CS5204–x family of linear regulators, the discharge path is through a large junction and protection diodes are not usually needed. If the regulator is used with large values of output capacitance and the input voltage is instantaneously shorted to ground, damage can occur. In this case, a diode connected as shown in Figures 11 and 12 is recommended.

Gnd




VIN C1

VOUT CS5204–1

RC

VOUT

) R2Ǔ ǒR1 R1


Adj

R1

CAdj

C2 VIN

R2

VIN

RC

VOUT


CS5204–1 R1 Adj

RLOAD


VOUT

VIN

VOUT

CS5204–x C1 Gnd


C2



CS5204–1, CS5204–3, CS5204–5 Calculating Power Dissipation and Heat Sink Requirements


The CS5204–x series of linear regulators includes thermal shutdown and current limit circuitry to protect the device. High power regulators such as these usually operate at high junction temperatures so it is important to calculate the power dissipation and junction temperatures accurately to ensure that an adequate heat sink is used. The case is connected to VOUT on the CS5204–x, electrical isolation may be required for some applications. Thermal compound should always be used with high current regulators such as these. The thermal characteristics of an IC depend on the following four factors: 1. 2. 3. 4.



The value for RΘJA is calculated using equation (3) and the result can be substituted in equation (28). The value for RΘJC is 3.5°C/W for a given package type based on an average die size. For a high current regulator such as the CS5204–x the majority of the heat is generated in the power transistor section. The value for RΘSA depends on the heat sink type, while RΘCS depends on factors such as package type, heat sink interface (is an insulator and thermal grease used?), and the contact area between the heat sink and the package. Once these calculations are complete, the maximum permissible value of RΘJA can be calculated and the proper heat sink selected. For further discussion on heat sink selection, see application note “Thermal Management for Linear Regulators,” document number SR006AN/D, available through the Literature Distribution Center or via our website at http://onsemi.com.


RQJA

(28)




(30)

Type

Description

CS5204–1GT3

4.0 A, Adj. Output


CS5204–1GDP3

4.0 A, Adj. Output

D2PAK 3–PIN

CS5204–1GDPR3

4.0 A, Adj. Output


CS5204–3GT3

4.0 A, 3.3 V Output


CS5204–3GDP3

4.0 A, 3.3 V Output

D2PAK 3–PIN

CS5204–3GDPR3

4.0 A, 3.3 V Output


CS5204–5GT3

4.0 A, 5.0 V Output



CS5204–1, CS5204–3, CS5204–5


TO–220 THREE LEAD

D2PAK 3–PIN

Unit

RΘJC

Typical

1.6

1.6

°C/W

RΘJA

Typical

50

10–50*

°C/W



+,$, $ , ) , ! The CS5205–2 linear regulator provides 5.0 A @ 1.5 V with an accuracy of ±2.0 %. The regulator is intended for use as an active termination for the GTL bus on Intel based motherboards. The fast loop response and low dropout voltage make these regulators ideal for applications where low voltage operation and good transient response are important. The circuit is designed to operate with dropout voltages as low as 1.0 V depending on the output current level. The maximum quiescent current is only 10 mA at full load. The regulator is fully protected against overload conditions with protection circuitry for Safe Operating Area (SOA), overcurrent and thermal shutdown. The CS5205–2 is available in TO–220 and surface mount D2 packages. Features • Output Current to 5.0 A • Output Voltage Trimmed to ±2.0% • Dropout Voltage 1.2 V @ 5.0 A • Fast Transient Response • Fault Protection Circuitry – Thermal Shutdown – Overcurrent Protection – Safe Area Protection

http://onsemi.com


12

2



3


TO–220


VOUT

1

VIN 1 A WL, L YY, Y WW, W




Device

Bandgap GND





Package

Shipping

CS5205–2GT3

TO–220†

50 Units/Rail

CS5205–2GDP3

D2PAK†

50 Units/Rail

CS5205–2GDPR3

D2PAK†

750 Tape & Reel

*Additional ordering information can be found on page 719 of this data sheet. † TO–220 are all 3–pin, straight leaded. D2PAK are all 3–pin.

715


CS5205–2 MAXIMUM RATINGS* Parameter Supply Voltage, VCC Operating Temperature Range Junction Temperature Storage Temperature Range Lead Temperature Soldering:


Value

Unit

17

V

–40 to +70

°C

150

°C

–60 to +150

°C

260 Peak 230 Peak

°C °C



Test Conditions

Min

Typ

Max

Unit

1.47 (–2.0%)

1.50

1.53 (+2.0%)

V


VIN – VOUT = 1.5 V; 0 ≤ IOUT ≤ 5.0 A

Line Regulation


–

0.04

0.20

%



–

0.08

0.40

%


IOUT = 5.0 A

–

1.2

1.3

V

Current Limit


5.5 –

8.5 1.0

– –

A A

Quiescent Current


–

5.0

10

mA

Thermal Regulation


–

0.003

–

%/W

Ripple Rejection

f = 120 Hz; IOUT = 5.0 A

–

75

–

dB

–

–

0.5

–

%

–

0.003

–

%/VOUT


10 Hz ≤ f ≤ 10 kHz

Thermal Shutdown

–

150

180

–

°C


–

–

25

–

°C


D2PAK

Pin Symbol

1

1

GND

Ground connection.

2

2

VOUT


3

3

VIN

Function

Input voltage.


CS5205–2 TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.08 Output Voltage Deviation (%)

Dropout Voltage (V)

1.30 1.25 1.20 1.15 1.10 1.05

TCASE = 0°C

1.00 0.95 TCASE = 125°C

0.90 0.85

TCASE = 25°C

0.80

0.06 0.04 0.02 0.00 –0.02 –0.04 –0.06 –0.08 –0.10

0.75 0.70

–0.12 0

1

2

3

4

5

0

TJ (°C)



0.200


0.175 0.150 0.125 0.100

TCASE = 25°C

0.075 0.050 TCASE = 125°C

0.025

TCASE = 0°C 0

1

2

3

4

2.175 TCASE = 0°C

1.850 1.525 TCASE = 25°C

1.200 0.875 TCASE = 125°C

0.000

0.550

5

1

2

Output Current (A)

3

4

5

6

7

VIN – VOUT (V)





10 20 30 40 50 60 70 80 90 100 110 120 130

Output Current (A)

70 60 50 40 30 20

TCASE = 25°C


10 0

101

102

103

104

Frequency (Hz)



105

8

9


The regulator is protected against short circuit, and includes thermal shutdown and safe area protection (SOA) circuitry. The SOA protection circuitry decreases the maximum available output current as the input–output differential voltage increase. The CS5205–2 has a composite PNP–NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.



The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response, and loop stability. The capacitor value and type is based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution. However, when the circuit operates at low temperatures, both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet provides this information. A 22 µF tantalum capacitor will work for most applications, but with high current regulators such as the CS5205–2 the transient response and stability improve with higher values of capacitance. The majority of applications for this regulator involve large changes in load current so the output capacitor must supply the instantaneous load current. The ESR of the output capacitor causes an immediate drop in output voltage given by: DV + DI


VOUT VIN

VOUT

CS5205–2 C1

C2 GND

Figure 7. Protection Diode Scheme for Fixed Output Regulators Output Voltage Sensing


ESR


VIN

VIN

VOUT

RC


CS5205–2 RLOAD

Figure 8. Conductor Parasitic Resistance Effects Can Be Minimized With the Above Grounding Scheme for Fixed Output Regulators




The CS5205–2 includes thermal shutdown and safe operating area circuitry to protect the device. High power regulators such as these usually operate at high junction temperatures so it is important to calculate the power dissipation and junction temperatures accurately to ensure that an adequate heat sink is used. The case is connected to VOUT on the CS5205–2, electrical isolation may be required for some applications. Thermal compound should always be used with high current regulators such as these. The thermal characteristics of an IC depend on the following four factors: 1. 2. 3. 4.





RQJA

(31)




(33)

Type

Description

CS5205–2GT3

5.0 A, 1.5 V Output


CS5205–2GDP3

5.0 A, 1.5 V Output

D2PAK 3–PIN

CS5205–2GDPR3

5.0 A, 1.5 V Output



CS5205–2


TO–220 THREE LEAD

D2PAK 3–PIN

Unit

RΘJC

Typical

1.6

1.6

°C/W

RΘJA

Typical

50

10–50*

°C/W



+,$, ) +,$, #) +,$, , , ) ## ,

! The CS5205–x series of linear regulators provides 5.0 A at adjustable and fixed voltages with an accuracy of ±1.0% and ±2.0% respectively. The adjustable version uses two external resistors to set the output voltage within a 1.25 V to 13 V range. The regulators are intended for use as post regulators and microprocessor supplies. The fast loop response and low dropout voltage make these regulators ideal for applications where low voltage operation and good transient response are important. The circuit is designed to operate with dropout voltages as low as 1.0 V depending on the output current level. The maximum quiescent current is only 10 mA at full load. The regulators are fully protected against overload conditions with protection circuitry for Safe Operating Area (SOA), overcurrent and thermal shutdown. The CS5205–x is pin compatible with the LT1084 family of linear regulators but has lower dropout voltage. The regulators are available in TO–220 and surface mount D2PAK packages. Features • Output Current to 5.0 A • Output Trimmed to ±1.0% • Dropout Voltage 1.2 V @ 5.0 A • Fast Transient Response • Fault Protection Circuitry – Thermal Shutdown – Overcurrent Protection – Safe Area Protection

http://onsemi.com

Adjustable Output TO–220 THREE LEAD T SUFFIX CASE 221A 1

12

2

Tab = VOUT Pin 1. Adj 2. VOUT 3. VIN Fixed Output



3


TO–220

CS5205–X AWLYWW CS5205–X AWLYWW



ORDERING INFORMATION* VOUT VIN


– +

Error Amplifier

Bandgap

Adj


Package

Shipping

CS5205–1GT3

TO–220†

50 Units/Rail

CS5205–1GDP3

D2PAK†

50 Units/Rail

CS5205–1GDPR3

D2PAK†

750 Tape & Reel

CS5205–3GT3

TO–220†

50 Units/Rail

CS5205–3GDP3

D2PAK†

50 Units/Rail

CS5205–3GDPR3

D2PAK†

750 Tape & Reel

CS5205–5GT3

TO–220†

50 Units/Rail




Device

721


CS5205–1, CS5205–3, CS5205–5

VOUT VIN



Bandgap GND

Figure 2. Block Diagram – CS5205–3, –5 ABSOLUTE MAXIMUM RATINGS* Parameter Supply Voltage, VCC Operating Temperature Range Junction Temperature Storage Temperature Range Lead Temperature Soldering:


Value

Unit

17

V

–40 to +70

°C

150

°C

–60 to +150

°C

260 Peak 230 Peak

°C °C



Test Conditions

Min

Typ

Max

Unit

1.241 (–1%)

1.254

1.266 (+1%)

V



Line Regulation


–

0.04

0.20

%



–

0.08

0.4

%


IOUT = 5.0 A

–

1.2

1.3

V

Current Limit


5.5 –

8.5 1.0

– –

A A



–

1.2

6.0

mA

–

50

100

µA

Adjust Pin Current

–



–

0.2

5.0

µA

Thermal Regulation


–

0.003

–

%W



CS5205–1, CS5205–3, CS5205–5 ELECTRICAL CHARACTERISTICS (continued) (CIN = 10 µF, COUT = 22 µF Tantalum, VIN – VOUT = 3.0 V, VIN ≤ 15 V, 0°C ≤ TA ≤ 70°C, TJ ≤ +150°C, unless otherwise specified, Ifull load = 5.0 A.)

Test Conditions

Characteristic

Min

Typ

Max

Unit

–

82

–

dB

–

0.5

–

%

–

0.003

–

%VOUT

Adjustable Output Voltage (CS5205–1) (continued) f = 120 Hz; CAdj = 25 µF; IOUT = 5.0 A


– 10 Hz ≤ f ≤ 10 kHz; TA = 25°C


–

150

180

–

°C


–

–

25

–

°C


Characteristic

Min

Typ

Max

Unit

4.9 (–2%) 3.234 (–2%)

5.0 3.3

5.1 (+2%) 3.366 (+2%)

V V

Fixed Output Voltage (CS5205–3, CS5205–5) Reference Voltage (Notes 6 and 7) CS5205–5 CS5205–3

VIN – VOUT = 1.5 V; 0 ≤ IOUT ≤ 5.0 A VIN – VOUT = 1.5 V; 0 ≤ IOUT ≤ 5.0 A

Line Regulation


–

0.04

0.20

%



–

0.08

0.40

%


IOUT = 5.0 A

–

1.2

1.3

V

Current Limit


5.5 –

8.5 1.0

– –

A A

Quiescent Current


–

5.0

10

mA

Thermal Regulation


–

0.003

–

%W

Ripple Rejection

f = 120 Hz; IOUT = 5.0 A

–

75

–

dB

–

0.5

–

%

–

0.003

–

%VOUT


–


10 Hz ≤ f ≤ 10 kHz

Thermal Shutdown

–

150

180

–

°C


–

–

25

–

°C

6. Load regulation and output voltage are measured at a constant junction temperature by low duty cycle pulse testing. Changes in output voltage due to thermal gradients or temperature changes must be taken into account separately. 7. Specifictions apply for an external Kelvin sense connection atr a point on the output pin 1/4” from the bottom of the package. 8. Dropout voltage is a measurement of the minimum input/output differentail at full load. PACKAGE PIN DESCRIPTION Package Pin Number CS5205–1 D2PAK

CS5205–3, –5

TO–220

D2PAK

TO–220

Pin Symbol

Function

1

1

N/A

N/A

Adj


2

2

2

2

VOUT

3

3

3

3

VIN

N/A

N/A

1

1

GND



CS5205–1, CS5205–3, CS5205–5 TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.08 Output Voltage Deviation (%)

Dropout Voltage (V)

1.30 1.25 1.20 1.15 TCASE = 0°C

1.10 1.05 1.00 0.95 0.90 0.85

TCASE = 125°C

TCASE = 25°C

0.80

0.06 0.04 0.02 0.00 –0.02 –0.04 –0.06 –0.08 –0.10

0.75 0.70

–0.12 0

1

2

3

4

5

0

Output Current (A)

TJ (°C)



0.175



0.200

0.150 0.125 0.100

TCASE = 25°C

0.075 0.050 TCASE = 125°C

0.025

2.175 TCASE = 0°C

1.850 1.525 TCASE = 25°C

1.200 0.875

TCASE = 0°C

TCASE = 125°C

0.550

0.000 0

1

2

3

4

5

1

2

3

4

5

6

7

Output Current (A)

VIN – VOUT (V)



8

9

100

70 IO = 10 mA

90

65



10 20 30 40 50 60 70 80 90 100 110 120 130

60 55 50

70 60 50 40 30 20

45

TCASE = 25°C


10 40

0

0

101

10 20 30 40 50 60 70 80 90 100 110 120 130

102

103

104

Temperature (°C)

Frequency (Hz)




105

CS5205–1, CS5205–3, CS5205–5 100 90 Ripple Rejection (dB)

80 70 60 50 40 30 20 10

TCASE = 25°C


0

101

102

103

104

105

Frequency (Hz)


APPLICATIONS INFORMATION The CS5205–x family of linear regulators provide fixed or adjustable voltages at currents up to 5.0 A. The regulators are protected against short circuit, and include thermal shutdown and safe area protection (SOA) circuitry. The SOA protection circuitry decreases the maximum available output current as the input–output differential voltage increases. The CS5205–x has a composite PNP–NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.

VIN C1

VREF R1

C2

IAdj CAdj

R2



VOUT

CS5205–1 Adj


VOUT + VREF

VOUT

VIN


The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type is based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR, can cause instability. The aluminum electrolytic capacitor is the least expensive solution. However, when the circuit operates at low temperatures, both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet provides this information. A 22 µF tantalum capacitor will work for most applications, but with high current regulators such as the CS5205–x the transient response and stability improve with higher values of capacitor. The majority of applications for this regulator involve large changes in load current so the output capacitor must supply the instantaneous load current.

R2





Since the CS5205–x is a three terminal regulator, it is not possible to provide true remote load sensing. Load regulation is limited by the resistance of the conductors connecting the regulator to the load. For best results the fixed regulators should be connected as shown in Figure 13.

ESR



VIN

VIN

VOUT

RC

CS5205–x

RLOAD

Protection Diodes

When large external capacitors are used with a linear regulator it is sometimes necessary to add protection diodes. If the input voltage of the regulator gets shorted, the output capacitor will discharge into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage and the rate at which VIN drops. In the CS5205–x family of linear regulators, the discharge path is through a large junction and protection diodes are not usually needed. If the regulator is used with large values of output capacitance and the input voltage is instantaneously shorted to ground, damage can occur. In this case, a diode connected as shown in Figures 11 and 12 is recommended.

Gnd




VIN C1

VOUT CS5205–1

RC

VOUT

) R2Ǔ ǒR1 R1


Adj

R1

CAdj

C2 VIN

R2

VIN

RC

VOUT


CS5205–1 R1 Adj

RLOAD


VOUT

VIN

VOUT

CS5205–x C1 Gnd


C2



CS5205–1, CS5205–3, CS5205–5 Calculating Power Dissipation and Heat Sink Requirements


The CS5205–x series of linear regulators includes thermal shutdown and current limit circuitry to protect the device. High power regulators such as these usually operate at high junction temperatures so it is important to calculate the power dissipation and junction temperatures accurately to ensure that an adequate heat sink is used. The case is connected to VOUT on the CS5205–x, electrical isolation may be required for some applications. Thermal compound should always be used with high current regulators such as these. The thermal characteristics of an IC depend on the following four factors: 1. 2. 3. 4.



The value for RΘJA is calculated using equation (3) and the result can be substituted in equation (34). The value for RΘJC is 3.5°C/W for a given package type based on an average die size. For a high current regulator such as the CS5205–x the majority of the heat is generated in the power transistor section. The value for RΘSA depends on the heat sink type, while RΘCS depends on factors such as package type, heat sink interface (is an insulator and thermal grease used?), and the contact area between the heat sink and the package. Once these calculations are complete, the maximum permissible value of RΘJA can be calculated and the proper heat sink selected. For further discussion on heat sink selection, see application note “Thermal Management for Linear Regulators,” document number SR006AN/D, available through the Literature Distribution Center or via our website at http://onsemi.com.


RQJA

(34)




(36)

Type

Description

CS5205–1GT3

5.0 A, Adj. Output


CS5205–1GDP3

5.0 A, Adj. Output

D2PAK 3–PIN

CS5205–1GDPR3

5.0 A, Adj. Output


CS5205–3GT3

5.0 A, 3.3 V Output


CS5205–3GDP3

5.0 A, 3.3 V Output

D2PAK 3–PIN

CS5205–3GDPR3

5.0 A, 3.3 V Output


CS5205–5GT3

5.0 A, 5.0 V Output



CS5205–1, CS5205–3, CS5205–5


TO–220 THREE LEAD

D2PAK 3–PIN

Unit

RΘJC

Typical

1.6

1.6

°C/W

RΘJA

Typical

50

10–50*

°C/W



+,$, , ! The CS5205A–1 linear regulator provides 5.0 A at an adjustable voltage with an accuracy of ±1%. Two external resistors are used to set the output voltage within a 1.25 V to 13 V range. The regulator is intended for use as a post regulator and microprocessor supply. The fast loop response and low dropout voltage make this regulator ideal for applications where low voltage operation and good transient response are important. The circuit is designed to operate with dropout voltages as low as 1.0 V depending on the output current level. The maximum quiescent current is only 10 mA at full load. The regulator is fully protected against overload conditions with protection circuitry for Safe Operating Area (SOA), overcurrent and thermal shutdown. The CS5205A–1 is pin compatible with the LT1084 family of linear regulators but has lower dropout voltage. The regulator is available in TO–220 and surface mount D2 packages. Features • Output Current to 5.0 A • Output Trimmed to ±1% • Dropout Voltage 1.15 V @ 5.0 A • Fast Transient Response • Fault Protection Circuitry – Thermal Shutdown – Overcurrent Protection – Safe Area Protection

http://onsemi.com


12

2



3


TO–220

CS5205A–1 AWLYWW CS5205A–1 AWLYWW

1 1

VOUT VIN

A WL, L YY, Y WW, W


ORDERING INFORMATION† Device


– +

Error Amplifier

Bandgap

Adj

Package

Shipping

CS5205A–1GT3

TO–220*

50 Units/Rail

CS5205A–1GDP3

D2PAK*

50 Units/Rail

CS5205A–1GDPR3

D2PAK*

750 Tape & Reel

* TO–220 is 3–pin, straight leaded, D2PAK is 3–pin. †Additional ordering information can be found on page 734 of this data sheet.




729

Publication Order Number: CS5205A–1/D

CS5205A–1 ABSOLUTE MAXIMUM RATINGS* Parameter Supply Voltage, VCC Operating Temperature Range Junction Temperature Storage Temperature Range Lead Temperature Soldering:


Value

Unit

17

V

–40 to +70

°C

150

°C

–60 to +150

°C

260 Peak 230 Peak

°C


ELECTRICAL CHARACTERISTICS (CIN = 10 µF, COUT = 22 µF Tantalum, VIN – VOUT = 3.0 V, VIN ≤ 15 V, 0°C ≤ TA ≤ 70°C, TJ ≤ +150°C, unless otherwise specified, Ifull load = 5.0 A.)

Test Conditions

Characteristic

Min

Typ

Max

Unit

1.241 (–1%)

1.254

1.266 (+1%)

V



Line Regulation


–

0.04

0.20

%



–

0.08

0.4

%


IOUT = 5.0 A; TJ ≥ 25°C

–

1.15

1.25

V

Current Limit


5.5 –

8.5 1.0

– –

A A



–

1.2

6.0

mA

–

50

100

µA

Adjust Pin Current Adjust Pin Current Change


–

0.2

5.0

µA

Thermal Regulation


–

0.003

–

%W

Ripple Rejection

f = 120 Hz; CAdj = 25 µF; IOUT = 5.0 A

–

82

–

dB

–

0.5

–

%

–

0.003

–

%VOUT


– 10 Hz ≤ f ≤ 10 kHz; TA = 25°C


–

150

180

–

°C


–

–

25

–

°C

3. Load regulation and output voltage are measured at a constant junction temperature by low duty cycle pulse testing. Changes in output voltage due to thermal gradients or temperature changes must be taken into account separately. 4. Specifictions apply for an external Kelvin sense connection at a point on the output pin 1/4” from the bottom of the package. 5. Dropout voltage is a measurement of the minimum input/output differentail at full load. PACKAGE PIN DESCRIPTION Package Pin Number TO–220

D2PAK

Pin Symbol

1

1

Adj

2

2

VOUT

3

3

VIN



CS5205A–1 TYPICAL PERFORMANCE CHARACTERISTICS 0.10

1.20


1.25

Dropout Voltage (V)

1.15 1.10

TCASE = 25°C

1.05 1.00

TCASE = 0°C

0.95

TCASE = 125°C

0.90 0.85 0.80

0.04 0.02 0.00 –0.02 –0.04 –0.06 –0.08 –0.10

0.75 0.70

0.06

–0.12 0

1

2

3

4

5

0

TJ (°C)




0.175 0.150 0.125 0.100

TCASE = 25°C

0.075 0.050

TCASE = 125°C

0.025

2.175 1.850

TCASE = 0°C

1.525 1.200 TCASE = 25°C

0.875

TCASE = 125°C

TCASE = 0°C

0.000

0.550 0

1

2

3

4

5

1

2

3

4

5

6

7

Output Current (A)

VIN – VOUT (V)





10 20 30 40 50 60 70 80 90 100 110 120 130

Output Current (A)

70 60 50 40 30 20

TCASE = 25°C


10 0

101

102

103

104

Frequency (Hz)



105

8

9

CS5205A–1 APPLICATIONS INFORMATION Stability Considerations

The CS5205A–1 linear regulator provides an adjustable voltage at currents up to 5.0 A. The regulator is protected against short circuit, and include thermal shutdown and safe area protection (SOA) circuitry. The SOA protection circuitry decreases the maximum available output current as the input–output differential voltage increases. The CS5205A–1 has a composite PNP–NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.

The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type is based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR, can cause instability. The aluminum electrolytic capacitor is the least expensive solution. However, when the circuit operates at low temperatures, both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet provides this information. A 22 µF tantalum capacitor will work for most applications, but with high current regulators such as the CS5205A–1 the transient response and stability improve with higher values of capacitor. The majority of applications for this regulator involve large changes in load current so the output capacitor must supply the instantaneous load current. The ESR of the output capacitor causes an immediate drop in output voltage given by:


The adjustable regulator (CS5205A–1) has an output voltage range of 1.25 V to 13 V. An external resistor divider sets the output voltage as shown in Figure 7. The regulator maintains a fixed 1.25 V (typical) reference between the output pin and the adjust pin. A resistor divider network R1 and R2 causes a fixed current to flow to ground. This current creates a voltage across R2 that adds to the 1.25 V across R1 and sets the overall output voltage. The adjust pin current (typically 50 µA) also flows through R2 and adds a small error that should be taken into account if precise adjustment of VOUT is necessary. The output voltage is set according to the formula: VOUT + VREF

) R2Ǔ ) I ǒR1 R1 Adj

DV + DI


R2

The term IAdj × R2 represents the error added by the adjust pin current. R1 is chosen so that the minimum load current is at least 10 mA. R1 and R2 should be the same type, e.g. metal film for best tracking over temperature. The adjust pin is bypassed to improve the transient response and ripple rejection of the regulator. VIN

VOUT

VIN C1

Protection Diodes

When large external capacitors are used with a linear regulator it is sometimes necessary to add protection diodes. If the input voltage of the regulator gets shorted, the output capacitor will discharge into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage and the rate at which VIN drops. In the CS5205A–1 linear regulator, the discharge path is through a large junction and protection diodes are not usually needed. If the regulator is used with large values of output capacitance and the input voltage is instantaneously shorted to ground, damage can occur. In this case, a diode connected as shown in Figure 8 is recommended.

VOUT

CS5205A–1 VREF

Adj

R1

C2

IAdj CAdj

ESR

R2



CS5205A–1 Calculating Power Dissipation and Heat Sink Requirements


VIN C1

VOUT CS5205A–1

The CS5205A–1 linear regulator includes thermal shutdown and safe operating area circuitry to protect the device. High power regulators such as these usually operate at high junction temperatures so it is important to calculate the power dissipation and junction temperatures accurately to ensure that an adequate heat sink is used. The case is connected to VOUT on the CS5205A–1, electrical isolation may be required for some applications. Thermal compound should always be used with high current regulators such as these. The thermal characteristics of an IC depend on the following four factors:

VOUT

Adj

R1

CAdj

C2

R2

Figure 8. Protection Diode Scheme for Adjustable Output Regulator Output Voltage Sensing

1. 2. 3. 4.

Since the CS5205A–1 is a three terminal regulator, it is not possible to provide true remote load sensing. Load regulation is limited by the resistance of the conductors connecting the regulator to the load. Best load regulation occurs when R1 is connected directly to the output pin of the regulator as shown in Figure 9. If R1 is connected to the load, RC is multiplied by the divider ratio and the effective resistance between the regulator and the load becomes RC


VIN

) R2Ǔ ǒR1 R1

RC

VOUT R1

(37)



(38)


CS5205A–1 Adj

RQJA



VIN


RLOAD

R2





(39)

CS5205A–1 area between the heat sink and the package. Once these calculations are complete, the maximum permissible value of RΘJA can be calculated and the proper heat sink selected. For further discussion on heat sink selection, see application note “Thermal Management for Linear Regulators,” document number SR006AN/D, available through the Literature Distribution Center or via our website at http://onsemi.com.

The value for RΘJA is calculated using equation (3) and the result can be substituted in equation (37). The value for RΘJC is normally quoted as a single figure for a given package type based on an average die size. For a high current regulator such as the CS5205A–1 the majority of the heat is generated in the power transistor section. The value for RΘSA depends on the heat sink type, while RΘCS depends on factors such as package type, heat sink interface (is an insulator and thermal grease used?), and the contact


Type

Description

CS5205A–1GT3

5.0 A, Adj. Output


CS5205A–1GDP3

5.0 A, Adj. Output

D2PAK 3–PIN

CS5205A–1GDPR3

5.0 A, Adj. Output



TO–220 THREE LEAD

D2PAK 3–PIN

Unit

RΘJC

Typical

1.6

1.6

°C/W

RΘJA

Typical

50

10–50*

°C/W



+,$% ) +,$% #) +,$% , % ) ## ,

! The CS5206–X series of linear regulators provides 6.0 A at adjustable and fixed voltages of 3.3 V and 5.0 V with an accuracy of ±1% and ±2% respectively. The adjustable version uses two external resistors to set the output voltage within a 1.25 V to 13 V range. The regulators are intended for use as post regulators and microprocessor supplies. The fast loop response and low dropout voltage make these regulators ideal for applications where low voltage operation and good transient response are important. The circuit is designed to operate with dropout voltages as low as 1.0 V depending on the output current level. The maximum quiescent current is only 10 mA at full load. The regulators are fully protected against overload conditions with protection circuitry for Safe Operating Area (SOA), overcurrent and thermal shutdown. The regulators are available in TO–220 and surface mount D2PAK packages.

http://onsemi.com

Adjustable Output

1

2

12

Fixed Output

3


D2PAK 3–PIN D2T SUFFIX CASE 418E 3


TO–220

Features • Output Current to 6.0 A • Output Trimmed to ±1% • Dropout Voltage 1.3 V @ 6.0 A • Fast Transient Response • Fault Protection Circuitry – Thermal Shutdown – Overcurrent Protection – Safe Area Protection



CS5206–x AWLYWW CS5206–x AWLYWW

1 1 x A WL, L YY, Y WW, W

= 1, 3, or 5 = Assembly Location = Wafer Lot = Year = Work Week

VOUT VIN

ORDERING INFORMATION† Device Output Current Limit Thermal Shutdown

– +

Error Amplifier

Bandgap

Adj




Package

Shipping

CS5206–1GT3

TO–220*

50 Units/Rail

CS5206–1GDP3

D2PAK*

50 Units/Rail

CS5206–1GDPR3

D2PAK

750 Tape & Reel

CS5206–3GT3

TO–220

50 Units/Rail

CS5206–3GDP3

D2PAK

50 Units/Rail

CS5206–3GDPR3

D2PAK

750 Tape & Reel

CS5206–5GT3

TO–220

50 Units/Rail

* TO–220 are all 3–pin, straight leaded. D2PAK are all 3–pin. †Additional ordering information can be found on page 742 of this data sheet. 735


CS5206–1, CS5206–3, CS5206–5

VOUT VIN



Bandgap Gnd

Figure 2. Block Diagram – CS5206–2, –3 MAXIMUM RATINGS* Parameter Supply Voltage, VCC Operating Temperature Range Junction Temperature Storage Temperature Range Lead Temperature Soldering:


Value

Unit

17

V

–40 to +70

°C

150

°C

–60 to +150

°C

260 Peak 230 Peak

°C


ELECTRICAL CHARACTERISTICS (CIN = 10 µF, COUT = 22 µF, Tantalum, VIN – VOUT = 3.0 V, VIN ≤ 15 V, 0°C ≤ TA ≤ 70°C, TJ = +150°C, unless otherwise specified, Ifull load = 6.0 A.) Test Conditions

Characteristic

Min

Typ

Max

Unit

1.241 (–1%)

1.254

1.266 (+1%)

V



Line Regulation


0.04

0.20

%



0.1

0.4

%


IOUT = 6.0 A

1.3

1.4

V

Current Limit


8.5 1.0

6.0

A A



1.2

100

mA

50

5.0

µA

Adjust Pin Current Adjust Pin Current Change


Thermal Regulation


6.5

0.2

µA

0.003

%/W

3. Load regulation and output voltage are measured at a constant junction temperature by low duty cycle pulse testing. Changes in output voltage due to thermal gradients or temperature changes must be taken into account separately. 4. Specifictions apply for an external Kelvin sense connection atr a point on the output pin 1/4” from the bottom of the package. 5. Dropout voltage is a measurement of the minimum input/output differentail at full load.


CS5206–1, CS5206–3, CS5206–5 ELECTRICAL CHARACTERISTICS continued (CIN = 10 µF, COUT = 22 µF, Tantalum, VIN – VOUT = 3.0 V, VIN ≤ 15 V, 0°C ≤ TA ≤ 70°C, TJ = +150°C, unless otherwise specified, Ifull load = 6.0 A.)

Test Conditions

Characteristic

Min

Typ

Max

Unit

Adjustable Output Voltage (CS5206–1) continued f = 120 Hz; CAdj = 25 µF; IOUT = 6.0 A


10 Hz ≤ f ≤ 10 kHz; TA = 25°C


150


82

dB

0.5

%

0.003

%VOUT

180

°C

25

°C

ELECTRICAL CHARACTERISTICS (CIN = 10 µF, COUT = 22 µF, Tantalum, VIN – VOUT = 3.0 V, VIN ≤ 10 V, 0°C ≤ TA ≤ 70°C, TJ = +150°C, unless otherwise specified, Ifull load = 6.0 A.) Test Conditions

Characteristic

Min

Typ

Max

4.9 (–2%) 3.234 (–2%)

5.0 3.3

5.1 (+2%) 3.366 (+2%)

Unit

Fixed Output Voltage (CS5206–3, CS5206–5) V

Reference Voltage (Notes 6 and 7) CS5206–5 CS5206–3


Line Regulation


0.04

0.20

%



0.1

0.4

%


IOUT = 6.0 A

1.3

1.4

V

Current Limit


8.5 1.0

6.0

A A

Quiescent Current


5.0

10

mA

Thermal Regulation


Ripple Rejection

f = 120 Hz; CAdj = 25 µF; IOUT = 6.0 A

6.5


10 Hz ≤ f ≤ 10 kHz

Thermal Shutdown

150


0.003

%/W

75

dB

0.5

%

0.003

%VOUT

180

°C

25

°C

6. Load regulation and output voltage are measured at a constant junction temperature by low duty cycle pulse testing. Changes in output voltage due to thermal gradients or temperature changes must be taken into account separately. 7. Specifictions apply for an external Kelvin sense connection atr a point on the output pin 1/4” from the bottom of the package. 8. Dropout voltage is a measurement of the minimum input/output differentail at full load. PACKAGE PIN DESCRIPTION Package Pin Number CS5206–1

CS5206–3, CS5206–5

D2PAK

TO–220

D2PAK

TO–220

Pin Symbol

Function

1

1

N/A

N/A

Adj

Adjust pin (low side of the internal reference)

2

2

2

2

VOUT

3

3

3

3

VIN

Input voltage

N/A

N/A

1

1

Gnd

Ground connection


Regulated output voltage (case)

CS5206–1, CS5206–3, CS5206–5 TYPICAL PERFORMANCE CHARACTERISTICS

0.10

1.4


Dropout Voltage (V)

1.3 TCASE = 0°C

1.2 1.1

TCASE = 25°C

1.0 TCASE = 125°C

0.9 0.8 0.7

0

1

2

3

4

5

0.04 0.00 –0.04 –0.08 –0.12 0

6

TJ (°C)



0.200


0.175 0.150 TCASE = 125°C 0.125 0.100

TCASE = 25°C

0.075 0.050 0.025

2.175 TCASE = 0°C 1.850 1.525 1.200 0.875

TCASE = 25°C

TCASE = 125°C

TCASE = 0°C

0.000 0

1

2 3 4 Output Current (A)

5

6

0.550 1


3

4 5 6 VIN – VOUT (V)

7

8

9

100

65


IO = 10 mA 60 55 50

60

40

20

45 40 0

2


70


Output Voltage Deviation, (%)

10 20 30 40 50 60 70 80 90 100 110 120 130

Output Current (A)

20

40

60 80 Temperature (°C)

100

0 101

120

TCASE = 25°C IOUT = 6.0 A (VIN – VOUT = 3.0 V) VRIPPLE = 1.6 VPP

102

103 Frequency (Hz)

104




105

CS5206–1, CS5206–3, CS5206–5 100


80

60

40

20

TCASE = 25°C IOUT = 6.0 A (VIN – VOUT = 3.0 V) VRIPPLE = 1.6 VPP CAdj = 25 µF

0 101

102

103 Frequency (Hz)

104

105

Figure 9. Ripple Rejection vs. Frequency (Adjustable Version)

APPLICATIONS INFORMATION bypassed to improve the transient response and ripple rejection of the regulator.

The CS5206–X family of linear regulators provide fixed or adjustable voltages at currents up to 6.0 A. The regulators are protected against short circuit, and include thermal shutdown and safe area protection (SOA) circuitry. The SOA protection circuitry decreases the maximum available output current as the input–output differential voltage increases. The CS5206–X has a composite PNP–NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.

VIN

VOUT

VIN C1

CS5206–1 VREF

Adj

R1

CAdj


C2

IAdj


VOUT + VREF

VOUT

R2



The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type is based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR, can cause instability. The aluminum electrolytic capacitor is the least expensive solution. However, when the circuit operates at low temperatures, both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet provides this information. A 22 µF tantalum capacitor will work for most applications, but with high current regulators such as the

R2

The term IAdj × R2 represents the error added by the adjust pin current. R1 is chosen so that the minimum load current is at least 10 mA. R1 and R2 should be the same type, e.g. metal film for best tracking over temperature. The adjust pin is



CS5206–X the transient response and stability improve with higher values of capacitor. The majority of applications for this regulator involve large changes in load current so the output capacitor must supply the instantaneous load current. The ESR of the output capacitor causes an immediate drop in output voltage given by: DV + DI

Since the CS5206–X is a three terminal regulator, it is not possible to provide true remote load sensing. Load regulation is limited by the resistance of the conductors connecting the regulator to the load. For best results the fixed regulators should be connected as shown in Figure 13. Conductor Parasitic Resistance

ESR VIN


VIN

VOUT

RC

CS5206–X

RLOAD

Gnd

Protection Diodes

When large external capacitors are used with a linear regulator it is sometimes necessary to add protection diodes. If the input voltage of the regulator gets shorted, the output capacitor will discharge into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage and the rate at which VIN drops. In the CS5206–X family of linear regulators, the discharge path is through a large junction and protection diodes are not usually needed. If the regulator is used with large values of output capacitance and the input voltage is instantaneously shorted to ground, damage can occur. In this case, a diode connected as shown in Figures 11 and 12 is recommended.


For the adjustable regulator, the best load regulation occurs when R1 is connected directly to the output pin of the regulator as shown in Figure 14. If R1 is connected to the load, RC is multiplied by the divider ratio and the effective resistance between the regulator and the load becomes RC

) R2Ǔ ǒR1 R1



VIN C1

VOUT CS5206–1

VIN

VOUT

VIN

RC

VOUT


CS5206–1

Adj

R1

CAdj

R1 Adj

C2

RLOAD

R2

R2

Figure 11. Protection Diode Scheme for Adjustable Output Regulator Figure 14. Grounding Scheme for Adjustable Output Regulator to Minimize Parasitics


VOUT

VIN

VOUT


CS5206–1 C1 Gnd

The CS5206–X series of linear regulators includes thermal shutdown and safe operating area circuitry to protect the device. High power regulators such as these usually operate at high junction temperatures so it is important to calculate the power dissipation and junction

C2



CS5206–1, CS5206–3, CS5206–5 Each material in the heat flow path between the IC and the outside environment has a thermal resistance. Like series electrical resistances, these resistances are summed to determine RΘJA, the total thermal resistance between the junction and the surrounding air. 1. Thermal Resistance of the junction to case, RΘJC (°C/W) 2. Thermal Resistance of the case to Heat Sink, RΘCS (°C/W) 3. Thermal Resistance of the Heat Sink to the ambient air, RΘSA (°C/W) These are connected by the equation:

temperatures accurately to ensure that an adequate heat sink is used. The case is connected to VOUT on the CS5206–X, electrical isolation may be required for some applications. Thermal compound should always be used with high current regulators such as these. The thermal characteristics of an IC depend on the following four factors: 1. 2. 3. 4.


RQJA


(42)

The value for RΘJA is calculated using equation (3) and the result can be substituted in equation (40). The value for RΘJC is normally quoted as a single figure for a given package type based on an average die size. For a high current regulator such as the CS5206–X the majority of the heat is generated in the power transistor section. The value for RΘJSA depends on the heat sink type, while RΘJCS depends on factors such as package type, heat sink interface (is an insulator and thermal grease used?), and the contact area between the heat sink and the package. Once these calculations are complete, the maximum permissible value of RΘJA can be calculated and the proper heat sink selected. For further discussion on heat sink selection, see application note “Thermal Management for Linear Regulators,” document number SR006AN/D, available through the Literature Distribution Center or via our website at http://onsemi.com.

(40)


where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current, for the application IQ is the maximum quiescent current at IOUT(max). A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air.


CS5206–1, CS5206–3, CS5206–5 ADDITIONAL ORDERING INFORMATION Orderable Part Number

Type

Description

CS5206–1GT3

6A, Adj. Output

3–Pin TO–220 Straight

CS5206–1GDP3

6A, Adj. Output

3–Pin D2PAK

CS5206–1GDPR3

6A, Adj. Output

3–Pin D2PAK (Tape & Reel)

CS5206–3GT3

6A, 3.3V Output


CS5206–3GDP3

6A, 3.3V Output

3–Pin D2PAK

CS5206–3GDPR3

6A, 3.3V Output

3–Pin D2PAK (Tape & Reel)

CS5206–5GT3

6A, 5V Output



TO–220

D2PAK

Unit

RΘJC

Typical

1.6

1.6

°C/W

RΘJA

Typical

50

10–50*

°C/W



+,$ $ ) , ! The CS5207–2 provides 7.0 A at 1.5 V with an accuracy of ±2.0 %. The regulator is intended for use as an active termination for the GTL bus on Intel based motherboards. The fast loop response and low dropout voltage make these regulators ideal for applications where low voltage operation and good transient response are important. The circuit is designed to operate with dropout voltages as low as 1.0 V depending on the output current level. The maximum quiescent current is only 10 mA at full load. The regulators are fully protected against overload conditions with protection circuitry for Safe Operating Area (SOA), overcurrent and thermal shutdown. The CS5207–2 is available in TO–220 packages.


Features • Output Current to 7.0 A • Output Voltage Trimmed to ±2.0% • Dropout Voltage 1.45 V @ 7.0 A • Fast Transient Response • Fault Protection Circuitry – Thermal Shutdown – Overcurrent Protection – Safe Area Protection

2

3

PIN CONNECTIONS AND MARKING DIAGRAMS

CS5207–2 AWLYWW

VOUT VIN




http://onsemi.com




Device CS5207–2GT3

Bandgap GND

Package

Shipping

TO–220†

50 Units/Rail

*Additional ordering information can be found on page 747 of this data sheet. † TO–220 is 3–pin, straight leaded.




743



Wave Solder (through hole styles only) Note 1


Value

Unit

17

V

–40 to +70

°C

150

°C

–60 to +150

°C

260 Peak

°C

2.0

kV



Test Conditions

Min

Typ

Max

Unit

1.47 (–2.0%)

1.50

1.53 (+2.0%)

V


VIN – VOUT = 1.65 V; 0 ≤ IOUT ≤ 7.0 A

Line Regulation


–

0.04

0.20

%



–

0.08

0.40

%


IOUT = 7.0 A

–

1.42

1.65

V

Current Limit


7.1 –

8.5 1.0

– –

A A

Quiescent Current


–

5.0

10

mA

Thermal Regulation


–

0.003

–

%/W

Ripple Rejection

f = 120 Hz; IOUT = 7.0 A

–

80

–

dB

–

–

0.5

–

%

–

0.003

–

%/VOUT


10 Hz ≤ f ≤ 10 kHz

Thermal Shutdown

–

150

180

–

°C


–

–

25

–

°C


Pin Symbol

1

GND

Ground connection.

2

VOUT


3

VIN

Function

Input voltage.


CS5207–2

0.10

1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70


Dropout Voltage (V)



TCASE = 125°C

0.06 0.04 0.02 0.00 –0.02 –0.04 –0.06 –0.08 –0.10 –0.12

0

1

2

3

4

5

6

7

0

TJ (°C)



100

0.200

90

0.175

TCASE = 125°C

80

0.150



10 20 30 40 50 60 70 80 90 100 110 120 130

Output Current (A)

0.125 TCASE = 25°C

0.100 0.075 0.050

70 60 50 40 30 20

TCASE = 0°C

0.025

TCASE = 25°C


10

0.000 0

1

2

3

4

5

6

0

101

7

102

103

104

Frequency (Hz)

Output Current (A)




105


The CS5207–2 linear regulator provides a fixed 1.5 V output at currents up to 7.0 A. The regulator is protected against short circuit, and includes thermal shutdown and safe area protection (SOA) circuitry. The SOA protection circuitry decreases the maximum available output current as the input–output differential voltage increase. The CS5207–2 has a composite PNP–NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.





VOUT VIN

VOUT

CS5207–2 C1

C2 GND

Figure 6. Protection Diode Scheme for Fixed Output Regulators Output Voltage Sensing


ESR


VIN

VIN

VOUT

RC


CS5207–2 RLOAD

Figure 7. Conductor Parasitic Resistance Effects Can Be Minimized With the Above Grounding Scheme for Fixed Output Regulators




The CS5207–2 includes thermal shutdown and safe operating area circuitry to protect the device. High power regulators such as these usually operate at high junction temperatures so it is important to calculate the power dissipation and junction temperatures accurately to ensure that an adequate heat sink is used. The case is connected to VOUT on the CS5207–2, electrical isolation may be required for some applications. Thermal compound should always be used with high current regulators such as these. The thermal characteristics of an IC depend on the following four factors: 1. 2. 3. 4.





RQJA

(43)



ADDITIONAL ORDERING INFORMATION Orderable Part Number CS5207–2GT3

(45)

Type

Description

7.0 A, 1.5 V Output



TO–220 THREE LEAD

Unit

RΘJC

Typical

1.6

°C/W

RΘJA

Typical

50

°C/W


+,$ # ) ## ! The CS5207–3 linear regulator provides 7.0 A @ 3.3 V with an accuracy of ±2.0 %. The regulator is intended for use as post regulator and microprocessor supply. The fast loop response and low dropout voltage make these regulators ideal for applications where low voltage operation and good transient response are important. The circuit is designed to operate with dropout voltages as low as 1.0 V depending on the output current level. The maximum quiescent current is only 10 mA at full load. The regulator is fully protected against overload conditions with protection circuitry for Safe Operating Area (SOA), overcurrent and thermal shutdown. The CS5207–3 is available in TO–220 and surface mount D2 packages. Features • Output Current to 7.0 A • Output Voltage Trimmed to ±2.0% • Dropout Voltage 1.4 V @ 7.0 A • Fast Transient Response • Fault Protection Circuitry – Thermal Shutdown – Overcurrent Protection – Safe Area Protection

http://onsemi.com


12

2



3


TO–220


VOUT

1

VIN 1 A WL, L YY, Y WW, W




Device

Bandgap GND





Package

Shipping

CS5207–3GT3

TO–220*

50 Units/Rail

CS5207–3GDP3

D2PAK*

50 Units/Rail

CS5207–3GDPR3

D2PAK*

750 Tape & Reel

*TO–220 are all 3–pin, straight leaded. D2PAK are all 3–pin.

748




Value

Unit

17

V

–40 to +70

°C

150

°C

–60 to +150

°C

260 Peak 230 Peak

°C °C



Test Conditions

Min

Typ

Max

Unit

3.234 (–2.0%)

3.300

3.366 (+2.0%)

V

3.3 V Fixed Output Voltage Output Voltage (Notes 3 and 4)


Line Regulation


–

0.04

0.20

%



–

0.13

0.5

%


IOUT = 7.0 A

–

1.4

1.55

V

Current Limit


7.1 –

8.5 1.0

– –

A A

Quiescent Current


–

5.0

10

mA

Thermal Regulation


–

0.003

–

%W

Ripple Rejection

f = 120 Hz; IOUT = 7.0 A

–

80

–

dB

–

–

0.5

–

%

–

0.003

–

%VOUT


10 Hz ≤ f ≤ 10 kHz; TA = 25°C

Thermal Shutdown

–

150

180

–

°C


–

–

25

–

°C


D2PAK

Pin Symbol

1

1

GND

Ground connection.

2

2

VOUT


3

3

VIN

Function

Input voltage.


CS5207–3

0.10

1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70


Dropout Voltage (V)



TCASE = 125°C

0.06 0.04 0.02 0.00 –0.02 –0.04 –0.06 –0.08 –0.10 –0.12

0

1

2

3

4

5

6

7

0

TJ (°C)



100

0.200

90

0.175

TCASE = 125°C

80

0.150



10 20 30 40 50 60 70 80 90 100 110 120 130

Output Current (A)

0.125 TCASE = 25°C

0.100 0.075 0.050

70 60 50 40 30 20

TCASE = 0°C

0.025

TCASE = 25°C


10

0.000 0

1

2

3

4

5

6

0

101

7

102

103

104

Frequency (Hz)

Output Current (A)




105


The CS5207–3 linear regulator provides a fixed 3.3 V output currents up to 7.0 A. The regulator is protected against short circuit, and includes thermal shutdown and safe area protection (SOA) circuitry. The SOA protection circuitry decreases the maximum available output current as the input–output differential voltage increase. The CS5207–3 has a composite PNP–NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.

When large external capacitors are used with a linear regulator it is sometimes necessary to add protection diodes. If the input voltage of the regulator gets shorted, the output capacitor will discharge into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage and the rate at which VIN drops. In the CS5207–3 regulator, the discharge path is through a large junction and protection diodes are not usually needed. If the regulator is used with large values of output capacitance and the input voltage is instantaneously shorted to ground, damage can occur. In this case, a diode connected as shown in Figure 6 is recommended.




VOUT VIN

VOUT

CS5207–3 C1

C2 GND

Figure 6. Protection Diode Scheme for Fixed Output Regulator Output Voltage Sensing

Since the CS5207–3 is a three terminal regulator, it is not possible to provide true remote load sensing. Load regulation is limited by the resistance of the conductors connecting the regulator to the load. Best load regulation occurs when the regulator is connected to the load as shown in Figure 7.

ESR


VIN

VIN

VOUT

RC


CS5207–3 RLOAD

Figure 7. Grounding Scheme for the Output Regulator to Minimize Parasitics









RQJA

(46)




(48)

TO–220 THREE LEAD

D2PAK 3–PIN

Unit

RΘJC

Typical

1.6

1.6

°C/W

RΘJA

Typical

50

10–50*

°C/W



+,$ ! The CS5207–1 linear regulator provides 7.0 A adjustable voltages with an accuracy of ±1.5 %. Two external resistors are used to set the output voltage within a 1.25 V to 13 V range. The regulator is intended for use as post regulator and microprocessor supply. The fast loop response and low dropout voltage make this regulator ideal for applications where low voltage operation and good transient response are important. The circuit is designed to operate with dropout voltages as low as 1.0 V depending on the output current. The maximum quiescent current is only 10 mA at full load. The regulator is fully protected against overload conditions with protection circuitry for Safe Operating Area (SOA), overcurrent and thermal shutdown. The regulator is available in TO–220 package. A 3.3 V, fixed version is also available. Please consult your local sales representative for more information. Features Output Current to 7.0 A Output Trimmed to ±1.5% Dropout Voltage 1.4 V @ 7.0 A Fast Transient Response Fault Protection Circuitry – Thermal Shutdown – Overcurrent Protection – Safe Area Protection

• • • • •

http://onsemi.com


2

3


CS5207–1 AWLYWW


1

VOUT

A WL, L YY, Y WW, W


VIN

ORDERING INFORMATION*† Device Output Current Limit Thermal Shutdown

– +

CS5207–1GT3

Shipping

TO–220‡

50 Units/Rail

*Additional ordering information can be found on page 758 of this data sheet. †Consult your local sales representative for fixed output voltage versions. ‡TO–220 is 3–pin, straight leaded.

Error Amplifier

Bandgap

Package

Adj




753




Value

Unit

17

V

–40 to +70

°C

150

°C

–60 to +150

°C

260 Peak

°C



Test Conditions

Min

Typ

Max

Unit

1.235 (–1.5%)

1.254

1.272 (+1.5%)

V



Line Regulation


–

0.04

0.20

%



–

0.13

0.5

%


IOUT = 7.0 A

–

1.4

1.55

V

Current Limit


7.1 –

8.5 1.0

– –

A A



–

1.2

6.0

mA

–

–

50

100

µA



–

0.2

5.0

µA

Thermal Regulation


–

0.003

–

%W

Ripple Rejection

f = 120 Hz; CAdj = 25 µF; IOUT = 7.0 A

–

80

–

dB

–

0.5

–

%

–

0.003

–

%VOUT

Adjust Pin Current

Temperature Stability RMS Output Noise

– 10 Hz ≤ f ≤ 10 kHz; TA = 25°C

Thermal Shutdown

–

150

180

–

°C


–

–

25

–

°C


Pin Symbol

1

Adj

2

VOUT

3

VIN



CS5207–1

0.10

1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70


Dropout Voltage (V)



TCASE = 125°C

0.06 0.04 0.02 0.00 –0.02 –0.04 –0.06 –0.08 –0.10 –0.12

0

1

2

3

4

5

6

7

0

TJ (°C)



0.175


0.200 TCASE = 125°C

0.150 0.125 TCASE = 25°C

0.100 0.075 0.050

TCASE = 0°C

0.025

2.175 TCASE = 0°C

1.850 1.525 TCASE = 25°C

1.200 0.875 TCASE = 125°C

0.550

0.000 0

1

2

3

4

5

6

7

1

2

3

4

5

6

7

Output Current (A)

VIN – VOUT (V)





10 20 30 40 50 60 70 80 90 100 110 120 130

Output Current (A)

70 60 50 40 30 20 10 0

101

TCASE = 25°C

IOUT = 7.0 A (VIN – VOUT) = 3.0 V VRIPPLE = 1.6 VPP CAdj = 25 µF 102

103

104

Frequency (Hz)



105

8

9

CS5207–1 APPLICATIONS INFORMATION The capacitor value and type is based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution. However, when the circuit operates at low temperatures, both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet provides this information. A 22 µF tantalum capacitor will work for most applications, but with high current regulators such as the CS5207–1 the transient response and stability improve with higher values of capacitor. The majority of applications for this regulator involve large changes in load current so the output capacitor must supply the instantaneous load current. The ESR of the output capacitor causes an immediate drop in output voltage given by:

The CS5207–1 linear regulator provides adjustable voltages at currents up to 7.0 A. The regulator is protected against short circuit, and includes thermal shutdown and safe area protection (SOA) circuitry. The SOA protection circuitry decreases the maximum available output current as the input–output differential voltage increases. The CS5207–1 has a composite PNP–NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section. Adjustable Operation

The adjustable regulator has an output voltage range of 1.25 V to 13 V. An external resistor divider sets the output voltage as shown in Figure 7. The regulator maintains a fixed 1.25V (typical) reference between the output pin and the adjust pin. A resistor divider network R1 and R2 causes a fixed current to flow to ground. This current creates a voltage across R2 that adds to the 1.25 V across R1 and sets the overall output voltage. The adjust pin current (typically 50 µA) also flows through R2 and adds a small error that should be taken into account if precise adjustment of VOUT is necessary. The output voltage is set according to the formula: ) R2Ǔ ǒR1 R1 ) IAdj

VOUT + VREF

DV + DI


R2 Protection Diodes

The term IAdj × R2 represents the error added by the adjust pin current. R1 is chosen so that the minimum load current is at least 10 mA. R1 and R2 should be the same type, e.g. metal film for best tracking over temperature. The adjust pin is bypassed to improve the transient response and ripple rejection of the regulator. VIN


VOUT VIN

VOUT

CS5207–1 VREF

C1 Adj

C2 R1

IN4002 (Optional)

IAdj CAdj

ESR

VIN

R2

VOUT VIN

VOUT

CS5207–1 C1

C2 Adj


R1

CAdj


The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response, and loop stability.

R2

Figure 8. Protection Diode Scheme for Adjustable Output Regulator




Since the CS5207–1 is a three terminal regulator, it is not possible to provide true remote load sensing. Load regulation is limited by the resistance of the conductors connecting the regulator to the load. Best load regulation occurs when R1 is connected directly to the output pin of the regulator as shown in Figure 9. If R1 is connected to the load, RC is multiplied by the divider ratio and the effective resistance between the regulator and the load becomes. RC



) R2Ǔ ǒR1 R1


VIN

VIN

RC

VOUT



CS5207–1 R1 Adj

RLOAD

R2

Figure 9. Grounding Scheme for Adjustable Output Regulator to Minimize Parasitic Resistance Effects Calculating Power Dissipation and Heat Sink Requirements



The value for RΘJA is calculated using equation (3) and the result can be substituted in equation (49). The value for RΘJC is normally quoted as a single figure for a given package type based on average die size. For a high current regulator such as the CS5207–1 the majority of the heat is generated in the power transistor section. The value for RΘSA depends on the heat sink type, while RΘCS depends on factors such as package type, heat sink interface (is an insulator and thermal grease used?), and the contact area between the heat sink and the package. Once these calculations are complete, the maximum permissible value of RΘJA can be calculated and the proper heat sink selected. For further discussion on heat sink selection, see application note “Thermal Management for Linear Regulators,” document number SR006AN/D, available through the Literature Distribution Center or via our website at http://onsemi.com.


RQJA

(51)

(49)


CS5207–1


Type

CS5207–1GT3

Description

7.0 A, Adj. Output



TO–220 THREE LEAD

Unit

RΘJC

Typical

1.6

°C/W

RΘJA

Typical

50

°C/W


+,$ * #

! The CS5207A–1 linear regulator provides 7.0 A at adjustable voltages from 1.25 V to 5.0 V. This adjustable device requires two external resistors to set the output voltage and provide the minimum load current for proper regulation. This regulator is intended for use as a post regulator and microprocessor supply. The fast loop response and low dropout voltage make this regulator ideal for applications where low voltage operation and good transient response are important. The circuit is designed to operate with dropout voltages as low as 1.0 V at 7.0 A. This regulator is protected against overload conditions with overcurrent and thermal shutdown protection circuitry. The CS5207A–1 is pin compatible with the LT1584 family of linear regulators but has lower dropout voltage and faster transient response. This regulator is available in a TO–220 package.

1

2

3

CS5207A–1 AWLYWW

3.3 V @ 7.0 A

VOUT

CS5207A–1

A WL, L YY, Y WW, W

Device

100 µF



124 Load 0.1 µF

Tab = VOUT Pin 1. Adjust 2. VOUT 3. VIN

1

5.0 V

Adj



Features • 1.25 V to 5.0 V VOUT @ 7.0 A • Dropout Voltage < 1.0 V @ 7.0 A • 1.5% Trimmed Reference • Fast Transient Response • Thermal Shutdown • Current Limit • Short Circuit Protection • Drop–In Replacement for LT1584

VIN

http://onsemi.com

200

CS5207A–1GT3 300 µF

Package

Shipping

TO–220*

50 Units/Rail

*TO–220 is 3–pin, straight leaded.




759


CS5207A–1 ABSOLUTE MAXIMUM RATINGS* Parameter

Value

Unit

6.0

V


0 ≤ TJ ≤ 150

°C


–60 to +150

°C

260 Peak

°C

2.0

kV

Input Voltage



ESD Damage Threshold 1. 10 second maximum. *The maximum package power dissipation must be observed.

ELECTRICAL CHARACTERISTICS ( 0°C ≤ TA ≤ 70°C, 0°C ≤ TJ ≤ 150°C, VAdj = 0 V, unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

1.234 (–1.5%)

1.253

1.271 (+1.5%)

V

Adjustable Output Voltage Reference Voltage

VIN = 2.75 V to 5.5 V, IOUT = 10 mA to 7.0 A

Line Regulation

VIN = 2.75 V to 5.5 V, IOUT = 10 mA

–

0.02

0.20

%

Load Regulation

VIN = 2.75 V, IOUT = 10 mA to 7.0 A

–

0.04

0.50

%


VIN = 5.0 V, ∆VOUT = +1.5%

–

5.0

10

mA

Adjust Pin Current

VIN = 2.75 V, IOUT = 10 mA

–

70

120

µA

Current Limit

VIN = 2.75 V, ∆VOUT = –1.5%

7.1

8.0

–

A


VIN = 2.75 V, VOUT = 0 V

5.0

9.0

–

A


VIN = 3.25 V, VRIPPLE = 1.0 VP–P @ 120 Hz, IOUT = 4.0 A, CAdj = 0.1 µF; COUT = 22 µF

60

80

–

dB



–

0.002

–

%/W

Dropout Voltage (Minimum VIN–VOUT) (Note 4)

IOUT = 100 mA IOUT = 1.0 A IOUT = 2.75 A IOUT = 4.0 A IOUT = 7.0 A

– – – – –

0.92 0.93 0.94 0.95 0.96

1.15 1.15 1.15 1.15 1.25

V V V V V

RMS Output Noise


–

0.003

–

%VOUT


–

–

0.5

–

%


–

150

180

210

°C


–

–

25

–

°C

2. The minimum load current is the minimum current required to maintain regulation. Normally the current in the resistor divider used to set the output voltage is selected to meet the minimum load current requirement. 3. This parameter is guaranteed by design and is not 100% production tested. 4. Dropout voltage is defined as the minimum input/output voltage differential required to maintain 1.5% regulation. 5. This parameter is guaranteed by design, but not parametrically tested in production. However, a 100% thermal shutdown functional test is performed on each part.


CS5207A–1 PACKAGE PIN DESCRIPTION Package Pin Number TO–220

Pin Symbol

Function

1

Adjust

This pin is connected to the low side of the internally trimmed 1.5% bandgap reference voltage and carries a bias current of about 70 µA. A resistor divider from Adj to VOUT and from Adj to ground sets the output voltage. Also, transient response can be improved by adding a small bypass capacitor from this pin to ground.

2

VOUT


3

VIN

This is the supply voltage for the regulator. For the device to regulate, this voltage should be between 1.0 V and 1.25 V (depending on the output current) greater than the output voltage.

VIN

BIAS and TSD

VREF

– EA +

+ IA –

VOUT

Adj



0.200 IO = 10 mA

VIN = 2.75 V



0.075 0.050 0.025 0 –0.025 –0.050 –0.075 –0.100

0.175 TCASE = 125°C

0.150 0.125 TCASE = 25°C

0.100 0.075

TCASE = 0°C

0.050 0.025

–0.125 –0.150

0 0

10 20 30 40 50 60 70 80 90 100 110 120 130

0

1

2

3

4

5

6

TJ (°C)

Output Current (A)




7

CS5207A–1 90

72.4 72.2

IO = 10 mA



85 80 75 70 65 60

72.0 71.8 71.6 71.4 71.2 71.0 70.8 70.6 70.4 70.2 70.0

0

10 20 30 40 50 60 70 80 90 100 110 120 130

0

1

2

3

4

5

6

TCase (°C)

IOUT (A)


Figure 6. Adjust Pin vs. IOUT

7

20

1.25

18 16 Output Current (A)

Dropout Voltage (V)

1.00

0.75

0.50

0.25

14 12 10 8 6 4 2

0

0 1

2

3

4

5

6

7

0.0

Figure 8. Short Circuit vs. VIN – VOUT

0.98

80

0.96 TCASE = 25°C

TCASE = 125°C

0.92 0.90 0.88 0.86 TCASE = 0°C

0.80 2

70 60 50 VIN – VOUT = 2.0 V

40

VRIPPLE = 1.0 VPP IOUT = 4.0 A CAdj = 0.1 µF COUT = 22 µF

30 20

0.82 1

5.0 5.5


0.84

2.5 3.0 3.5 4.0 4.5

VIN – VOUT (V)

1.00

0.94

0.5 1.0 1.5 2.0

Output Current (A)



0

3

4

10

5

101

102

103

104

105

VIN – VOUT (V)

Frequency (Hz)




106

CS5207A–1 APPLICATION NOTES THEORY OF OPERATION

OTHER ADJUSTABLE OPERATION CONSIDERATIONS

The CS5207A–1 linear regulator has a composite PNP–NPN output stage that requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.

The CS5207A–1 linear regulator has an absolute maximum specification of 6.0 V for the voltage difference between VIN and VOUT. However, the IC may be used to regulate voltages in excess of 6.0 V. The main considerations in such a design are power–up and short circuit capability. In most applications, ramp–up of the power supply to VIN is fairly slow, typically on the order of several tens of milliseconds, while the regulator responds in less than one microsecond. In this case, the linear regulator begins charging the output capacitor as soon as the VIN to VOUT differential is large enough that the pass transistor conducts current. VOUT is essentially at ground, and VIN is on the order of several hundred millivolts, so the pass transistor is in dropout. As VIN increases, the pass transistor will remain in dropout, and current is passed to the load until VOUT is in regulation. Further increase in VIN brings the pass transistor out of dropout. The result is that the output voltage follows the power supply ramp–up, staying in dropout until the regulation point is reached. In this manner, any output voltage may be regulated. There is no theoretical limit to the regulated voltage as long as the VIN to VOUT differential of 6.0 V is not exceeded. However, maximum ratings of the IC will be exceeded in a short circuit condition. Short circuit conditions will result in the immediate operation of the pass transistor outside of its safe operating area. Over–voltage stresses will then cause destruction of the pass transistor before overcurrent or thermal shutdown circuitry can become active. Additional circuitry may be required to clamp VIN to VOUT differential to less than 6.0 V if failsafe operation is required. One possible clamp circuit is illustrated in Figure 12; however, the design of clamp circuitry must be done on an application by application basis. Care must be taken to ensure the clamp actually protects the design. Components used in the clamp design must be able to withstand the short circuit conditions indefinitely while protecting the IC.

ADJUSTABLE OPERATION Design Guidelines

This LDO adjustable regulator has an output voltage range of 1.25 V to 5.0 V. An external resistor divider sets the output voltage as shown in Figure 11. The regulator’s voltage sensing error amplifier maintains a fixed 1.25 V reference between the output pin and the adjust pin. A resistor divider network R1 and R2 causes a fixed current to flow to ground. This current creates a voltage across R2 that adds to the 1.25 V across R1 and sets the overall output voltage. The adjust pin current (typically 50 µA) also flows through R2 and adds a small error that should be taken into account if precise adjustment of VOUT is necessary. The output voltage is set according to the formula:

ǒR1 R) R2Ǔ ) R2

VOUT + VREF

1

IAdj

The term IAdj × R2 represents the error added by the adjust pin current. R1 is chosen so that the minimum load current is at least 10 mA. R1 and R2 should be of the same composition for best tracking over temperature. For best results, the divider resistor should be placed near the regulator with a seperate metal trace connecting them to output.. VIN

VOUT

CS5207A–1 Adj

R1

R2

EXTERNAL SUPPLY

Figure 11.

While not required, a bypass capacitor connected between the adjust pin and ground will improve transient response and ripple rejection. A 0.1 µF tantalum capacitor is recommended for “first cut” design. Value and type may be varied to optimize performance vs price.

VIN

VOUT VAdj

Figure 12.


CS5207A–1 STABILITY CONSIDERATIONS

If the calculated current is greater than or equal to the typical short circuit current value provided in the specifications, serious thought should be given to including a protection diode.

The output compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response, and loop stability. The capacitor value and type is based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution. However, when the circuit operates at low temperatures, both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet provides this information. A 300 µF tantalum capacitor will work for most applications, but with high current regulators such as the CS5207A–1 the transient response and stability improve with higher values of capacitance. The majority of applications for this regulator involve large changes in load current so the output capacitor must supply the instantaneous load current. The ESR of the output capacitor causes an immediate drop in output voltage given by: DV + DI

VIN

CS5207A–1 Adj

Figure 13. Current Limit

The internal current limit circuit limits the output current under excessive load conditions and protects the regulator.

ESR



The device includes foldback short circuit current limit that clamps the output current at approximately two amperes less than its current limit value. Thermal Shutdown

The thermal shutdown circuitry is guaranteed by design to become activated above a die junction temperature of 150°C and to shut down the regulator output. This circuitry includes a thermal hysteresis circuit with 25°C of typical hysteresis, thereby allowing the regulator to recover from a thermal fault automatically.

Protection Diodes

When large external capacitors are used with a linear regulator it is sometimes necessary to add protection diodes. If the input voltage of the regulator gets shorted, the output capacitor will discharge into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage and the rate at which VIN drops. In the CS5207A–1 regulator, the discharge path is through a large junction and protection diodes are not usually needed. If the regulator is used with large values of output capacitance and the input voltage is instantaneously shorted to ground, damage can occur. In this case, a diode connected as shown in Figure 13 is recommended. A rule of thumb useful in determining if a protection diode is required is to solve for current I+

C

VOUT


High power regulators such as the CS5207A–1 usually operate at high junction temperatures. Therefore, it is important to calculate the power dissipation and junction temperatures accurately to ensure that an adequate heat sink is used. Since the package tab is connected to VOUT on the CS5207A–1, electrical isolation may be required for some applications. Also, as with all high power packages, thermal compound is necessary to ensure proper heat flow. For added safety, this high current LDO includes an internal thermal shutdown circuit The thermal characteristics of an IC depend on the following four factors. Junction temperature, ambient temperature, die power dissipation, and the thermal resistance from the die junction to ambient air. The maximum junction temperature can be determined by:

V T

where: I is the current flow out of the load capacitance when VIN is shorted, C is the value of the load capacitance, V is the output voltage, and T is the time duaration required for VIN to transition from high to being shorted.



RQJA

CS5207A–1 RQJA + RQJC ) RQCS ) RQSA

The maximum ambient temperature and the power dissipation are determined by the design while the maximum junction temperature and the thermal resistance depend on the manufacturer and the package type. The maximum power dissipation for a regulator is: PD(max) + (VIN(max) * VOUT(min))IOUT(max) ) VIN(max)

RΘJC is rated @ 1.4°C/W for the CS5207A–1. For a high current regulator such as the CS5207A–1 the majority of heat is generated in the power transistor section. The value for RΘSA depends on the heat sink type, while the RΘCS depends on factors such as package type, heat sink interface (is an insulator and thermal grease used?), and the contact area between the heat sink and the package. Once these calculations are complete, the maximum permissible value of RΘJA can be calculated and the proper heat sink selected. For further discussion on heat sink selection, see application note “Thermal Management for Linear Regulators,” document number SR006AN/D, available through the Literature Distribution Center or via our website at http://onsemi.com.

IIN(max)

A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment has a thermal resistance. Like series electrical resistances, these resistances are summed to determine the total thermal resistance between the die junction and the surrounding air, RΘJC. This total thermal resistance is comprised of three components. These resistive terms are measured from junction to case (RΘJC), case to heat sink (RΘCS), and heat sink to ambient air (RΘSA). The equation is: PACKAGE THERMAL DATA Parameter

TO–220 THREE LEAD

Unit

RΘJC

Typical

1.4

°C/W

RΘJA

Typical

50

°C/W


+,$, * ,

! This new very low dropout regulator is designed to power the next generation of advanced microprocessors. To achieve very low dropout, the internal pass transistor is powered separately from the control circuitry. Furthermore, with the control and power inputs tied together, this device can be used in single supply configuration and still offer a better dropout voltage than conventional PNP–NPN based LDO regulators. In this mode the dropout is determined by the minimum control voltage. It is supplied in five–terminal TO–220 and D2PAK packages, allowing for the implementation of a remote–sense pin permitting very accurate regulation of output voltage directly at the load, where it counts, rather than at the regulator. This remote sensing feature virtually eliminates output voltage variations due to load changes and resistive voltage drops. Typical load regulation measured at the sense pin is 1.0 mV for an output voltage of 2.5 V with a load step of 10 mA to 7.0 A. The very fast transient loop response easily meets the needs of the latest microprocessors. In addition, a small capacitor on the Adjust pin will further improve the transient capabilities. Internal protection circuitry provides for “bust–proof” operation, similar to three–terminal regulators. This circuitry, which includes overcurrent, short circuit, supply sequencing and overtemperature protection will self protect the regulator under all fault conditions. The CS5257A–1 is ideal for generating a secondary 2.0–2.5 V low voltage supply on a motherboard where both 5.0 V and 3.3 V are already available.

http://onsemi.com

TO–220 FIVE LEAD T SUFFIX CASE 314D


1 5


1 5


TO–220

CS 5257A–1 AWLYWW

Features • 1.25 V to 5.0 V VOUT at 7.0 A • VPOWER Dropout < 0.35 V @ 7.0 A • VCONTROL Dropout < 1.1 V @ 7.0 A • 1.5% Trimmed Reference • Fast Transient Response • Remote Voltage Sensing • Thermal Shutdown • Current Limit • Short Circuit Protection • Drop–In Replacement for LT1580 • Backwards Compatible with 3–Pin Regulators

CS5257A–1 AWLYWW




Package

Shipping

CS5257A–1GT5

TO–220 FIVE LEAD

50 Units/Rail

CS5257A–1GDP5

D2PAK*

50 Units/Rail

CS5257A–1GDPR5

D2PAK*

750 Tape & Reel

*5–Pin.



766


CS5257A–1 5.0 V VCONTROL

VOUT

CS5257A–1 2.5 V @ 7.0 A 3.3 V

VPOWER

VSENSE Adjust

10 µF 10 V

100 µF 5.0 V

0.1 µF 5.0 V

124 1.0% 124 1.0%

300 µF 5.0 V

Load



Value

Unit


6.0

V


13

V

0 to 150

°C

–65 to +150

°C

2.0

kV

260 peak 230 peak

°C °C





Test Conditions

Min

Typ

Max

Unit

Reference Voltage

VCONTROL = 2.75 V to 12 V, VPOWER = 2.05 V to 5.5 V, 10 mA ≤ IOUT ≤ 7.0 A

1.234 (–1.5%)

1.253

1.272 (+1.5%)

V

Line Regulation


–

0.02

0.2

%

Load Regulation (Note 3)


–

0.04

0.2

%



–

5.0

10

mA


VCONTROL = 2.75 V, VPOWER = 2.05 V, IOUT = 100 mA VCONTROL = 2.75 V, VPOWER = 2.05 V, IOUT = 4.0 A VCONTROL = 2.75 V, VPOWER = 1.75 V, IOUT = 4.0 A VCONTROL = 2.75 V, VPOWER = 2.05 V, IOUT = 7.0 A

– – – –

6.0 30 33 60

10 60 70 180

mA mA mA mA

Adjust Pin Current


–

60

120

µA

Current Limit


7.1

10

–

A

CS5257A–1

3. This parameter is guaranteed by design and is not 100% production tested. 4. The minimum load current is the minimum current required to maintain regulation. Normally the current in the resistor divider used to set the output voltage is selected to meet the minimum load current requirement. 5. The VCONTROL pin current is the drive current required for the output transistor. This current will track output current with roughly a 1:100 ratio. The minimum value is equal to the quiescent current of the device.


CS5257A–1 ELECTRICAL CHARACTERISTICS (continued) (0°C ≤ TA ≤ 70°C; 0°C ≤ TJ ≤ 150°C; VSENSE = VOUT and VADJ = 0 V; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

CS5257A–1 Short Circuit Current


5.0

9.0

–

A


VCONTROL = VPOWER = 3.25 V VRIPPLE = 1.0 VP–P @ 120 Hz, IOUT = 4.0 A, CADJ = 0.1 µF

60

80

–

dB

Thermal Regulation


–

0.002

–

%/W


VPOWER = 2.05 V, IOUT = 100 mA VPOWER = 2.05 V, IOUT = 1.0 A VPOWER = 2.05 V, IOUT = 2.75 A VPOWER = 2.05 V, IOUT = 4.0 mA VPOWER = 2.05 V, IOUT = 7.0 A

– – – – –

1.00 1.00 1.00 1.00 1.10

1.15 1.15 1.15 1.15 1.25

V V V V V


VCONTROL = 2.75 V, IOUT = 100 mA VCONTROL = 2.75 V, IOUT = 1.0 A VCONTROL = 2.75 V, IOUT = 2.75 A VCONTROL = 2.75 V, IOUT = 4.0 mA VCONTROL = 2.75 V, IOUT = 7.0 A

– – – – –

0.10 0.15 0.20 0.26 0.35

0.15 0.20 0.30 0.40 0.65

V V V V V

RMS Output Noise


–

0.003

–

%VOUT


–

–

0.5

–

%


–

150

180

210

°C


–

–

–

25

°C



–

–

50

mA



–

0.1

1.0

mA

6. This parameter is guaranteed by design and is not 100% production tested. 7. Dropout is defined as either minimum control voltage (VCONTROL) or minimum power voltage (VPOWER) to output voltage differential required to maintain 1.5% regulation at a particular load. 8. This parameter is guaranteed by design, but not parametrically tested in production. However, a 100% thermal shutdown functional test is performed on each part.


D2PAK

PIN SYMBOL

FUNCTION

1

1

VSENSE


2

2

Adjust


3

3

VOUT


4

4

VCONTROL

This is the supply voltage for the regulator control circuitry. For the device to regulate, this voltage should be between 1.0 V and 1.25 V (depending on the output current) greater than the output voltage. The control pin current will be about 1.0% of the power pin output current.

5

5

VPOWER

This is the power input voltage. This pin is physically connected to the collector of the power pass transistor. For the device to regulate, this voltage should be between 0.1 V and 0.65 V greater than the output voltage depending on the output current. The output load current of 7.0 A is supplied through this pin.


CS5257A–1

VPOWER VCONTROL

BIAS and TSD

– +

VREF

EA

IA



0.100

0.10

0.075

0.09




0.050 0.025 0 –0.025 –0.050 –0.075 IO = 10 mA VCONTROL = 2.75 V VPOWER = 2.05 V

–0.100 –0.125 –0.150

0

VPOWER = 2.05 V VCONTROL = 2.75 V

0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0

10 20 30 40 50 60 70 80 90 100 110 120 130

0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

Output Current (A)

TJ (°C)

Figure 3. Reference Voltage vs Temperature


14.0 12.0 0 COUT = 330 µF CPOWER = 110 µF CCONTROL = 10 µF CADJ = 0.1 µF VCONTROL = 5.0 V VPOWER = 3.3 V VOUT = 2.5 V

–50

–100

Current (A)

VCONTROL = 2.75 V

50 Output Current (A)


100

7.0

8.0 6.0 4.0 2.0

0 0

10.0

0 0

1

2

3

4

5

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5

4.0 4.5

5.0 5.5

VPOWER – VOUT (V)

Time (µs)


Figure 6. Short Circuit Current vs VPOWER – VOUT


83

1200

81

1150

Minimum Load Current (µA)


CS5257A–1

79 77 75 73 71 69

1100 1050 1000 950 900 850

67 65

VPOWER = 3.3 V ∆VOUT = +1.0%

0

20

40

60

80

120

100

140

800 1.0

160

2.0

3.0

Temperature (°C)

VPOWER = 2.05 V IL = 10 mA

9.0

10

11


72

71

70 60 50 VIN – VOUT = 2.0 V IOUT = 4.0 A VRIPPLE = 1.0 VP–P COUT = 22 µF CADJ = 0.1 µF

40 30 20

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10

10 1 10

11

102

103

104

105

106

Frequency (Hz)


Figure 9. Adjust Pin Current vs VCONTROL – VOUT


1.25

75 VCONTROL = 2.75 V IL = 10 mA

VCONTROL Dropout Voltage (V)


8.0

80

73

73

72

71

70 0.5

7.0

90

74

74

6.0


75


5.0


Figure 7. Adjust Pin Current vs Temperature

70 1.0

4.0

1.5

2.5

3.5

4.5

VPOWER = 2.05 V 1.00

0.75

0.50

0.25

0

0

VPOWER – VOUT (V)

1.0

2.0

3.0

4.0

5.0

6.0

Output Current (A)

Figure 11. Adjust Pin Current vs VPOWER – VOUT

Figure 12. VCONTROL Dropout Voltage vs IOUT


7.0

CS5257A–1 1.0

916.4 916.3

VCONTROL = 2.75 V



0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2

916.2 916.1 916.0 915.9 915.8 915.7 915.6 915.5

0.1 0


0

1.0

2.0

3.0

4.0

5.0

6.0

915.4 0.5

7.0

1.5

2.5

3.5

4.5

VPOWER – VOUT (V)

Output Current (A)

Figure 13. VPOWER Dropout Voltage vs IOUT


77


VPOWER = 2.05 V VCONTROL = 2.75 V 76

75

74

73

72

0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

Output Current (A)

Figure 15. Adjust Pin Current vs Output Current

APPLICATIONS NOTES THEORY OF OPERATION The CS5257A–1 linear regulator provides adjustable voltages from 1.25 V to 5.0 V at currents up to 7.0 A. The regulator is protected against short circuits, and includes a thermal shutdown circuit with hysteresis. The output, which is current limited, consists of a PNP–NPN transistor pair and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.

that there are no supply sequencing problems. The output voltage will not turn on until both supplies are operating. If the control voltage comes up first, the output current will be typically limited to about 3.0 mA until the power input voltage comes up. If the power input voltage comes up first the output will not turn on at all until the control voltage comes up. The output can never come up unregulated. The CS5257A–1 can also be used as a single supply device with the control and power inputs tied together. In this mode, the dropout will be determined by the minimum control voltage.

VPOWER Function

The CS5257A–1 utilizes a two supply approach to maximize efficiency. The collector of the power device is brought out to the VPOWER pin to minimize internal power dissipation under high current loads. VCONTROL provides power for the control circuitry and the drive for the output NPN transistor. VCONTROL should be at least 1.0 V greater than the output voltage. Special care has been taken to ensure


The CS5257A–1 five terminal linear regulator includes a dedicated VSENSE function. This allows for true Kelvin sensing of the output voltage. This feature can virtually eliminate errors in the output voltage due to load regulation.


CS5257A–1 Power supply sequencing should be such that the VCONTROL supply is brought up coincidentally with or before the VPOWER supply. This allows the IC to begin charging the output capacitor as soon as the VPOWER to VOUT differential is large enough that the pass transistor conducts. As VPOWER increases, the pass transistor will remain in dropout, and current is passed to the load until VOUT is in regulation. Further increase in the supply voltage brings the pass transistor out of dropout. In this manner, any output voltage less than 13 V may be regulated, provided the VPOWER to VOUT differential is less than 6.0 V. In the case where VCONTROL and VPOWER are shorted, there is no theoretical limit to the regulated voltage as long as the VPOWER to VOUT differential of 6.0 V is not exceeded. There is a possibility of damaging the IC when VPOWER – VIN is greater than 6.0 V if a short circuit occurs. Short circuit conditions will result in the immediate operation of the pass transistor outside of its safe operating area. Overvoltage stresses will then cause destruction of the pass transistor before overcurrent or thermal shutdown circuitry can become active. Additional circuitry may be required to clamp the VPOWER to VOUT differential to less than 6.0 V if fail safe operation is required. One possible clamp circuit is illustrated in Figure 17; however, the design of clamp circuitry must be done on an application by application basis. Care must be taken to ensure the clamp actually protects the design. Components used in the clamp design must be able to withstand the short circuit condition indefinitely while protecting the IC.

Regulation will be optimized at the point where the sense pin is tied to the output. DESIGN GUIDELINES Adjustable Operation

This LDO adjustable regulator has an output voltage range of 1.25 V to 5.0 V. An external resistor divider sets the output voltage as shown in Figure 16. The regulator’s voltage sensing error amplifier maintains a fixed 1.253 V reference between the output pin and the adjust pin. VCONTROL

VOUT

CS5257A–1 VPOWER

VSENSE Adjust

R1

R2

Figure 16. An External Resistor Divider Sets the Value of VOUT. The 1.253 V Reference Voltage Drops Across R1.


R1 ) R2 ) R2 R1

External Supply

VCONTROL

IADJ

The term IADJ × R2 represents the error added by the adjust pin current. R1 is chosen so that the minimum load current is a least 10 mA. R1 and R2 should be of the same composition for best tracking over temperature. The divider resistors should be placed physically as close to the load as possible. While not required, a bypass capacitor connected between the adjust pin and ground will improve transient response and ripple rejection. A 0.1 µF tantalum capacitor is recommended for “first cut” design. Value and type may be varied to optimize performance vs. price.

VSENSE

VPOWER

VOUT

VADJ

Figure 17. Example Clamp Circuitry for VPOWER – VOUT > 6.0 V Stability Considerations

The output compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response, and loop stability. The capacitor value and type is based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The


The CS5257A–1 linear regulator has an absolute maximum specification of 6.0 V for the voltage difference between VIN and VOUT. However, the IC may be used to regulate voltages in excess of 6.0 V. The two main considerations in such a design are the sequencing of power supplies and short circuit capability.


CS5257A–1 aluminum electrolytic capacitor is the least expensive solution. However, when the circuit operates at low temperatures, both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet provides this information. A 300 µF tantalum capacitor will work for most applications, but with high current regulators such as the CS5257A–1 the transient response and stability improve with higher values of capacitor. The majority of applications for this regulator involve large changes in load current so the output capacitor must supply the instantaneous load current. The ESR of the output capacitor causes an immediate drop in output voltage given by: DV + DI

A rule of thumb useful in determining if a protection diode is required is to solve for current I+C

where: I is the current flow out of the load capacitance when VCONTROL is shorted, C is the value of load capacitance, V is the output voltage, and T is the time duration required for VCONTROL to transition from high to being shorted. If the calculated current is greater than or equal to the typical short circuit current value provided in the specifications, serious thought should be given to the use of a protection diode.

ESR


Current Limit


The device includes short circuit protection circuitry that clamps the output current at approximately two amperes less than its current limit value. This provides for a current foldback function, which reduces power dissipation under a direct shorted load.

Protection Diodes

When large external capacitors are used with a linear regulator it is sometimes necessary to add protection diodes. If the input voltage of the regulator gets shorted, the output capacitor will discharge into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage, and the rate at which VCONTROL drops. In the CS5257A–1 regulator, the discharge path is through a large junction and protection diodes are not usually needed. If the regulator is used with large values of output capacitance and the input voltage is instantaneously shorted to ground, damage can occur. In this case, a diode connected as shown in Figure 18 is recommended.

VCONTROL

Thermal Shutdown


High power regulators such as the CS5257A–1 usually operate at high junction temperatures. Therefore, it is important to calculate the power dissipation and junction temperatures accurately to ensure that an adequate heat sink is used. Since the package tab is connected to VOUT on the CS5257A–1, electrical isolation may be required for some applications. Also, as with all high power packages, thermal compound in necessary to ensure proper heat flow. For added safety, this high current LDO includes an internal thermal shutdown circuit. The thermal characteristics of an IC depend on the following four factors: junction temperature, ambient temperature, die power dissipation, and the thermal resistance from the die junction to ambient air. The maximum junction temperature can be determined by:

VOUT

CS5257A–1 VPOWER

V T

VSENSE Adjust

Figure 18. Diode Protection Against VCONTROL Short Circuit Conditions


Use of the diode has the added benefit of bleeding VOUT to ground if VCONTROL is shorted. This prevents an unregulated output from causing system damage.

RQJA

The maximum ambient temperature and the power dissipation are determined by the design while the


CS5257A–1 RQJA + RQJC ) RQCS ) RQSA

maximum junction temperature and the thermal resistance depend on the manufacturer and the package type. The maximum power dissipation for a regulator is:

The value for RΘJC is 1.4°C/watt for the CS5257A–1 in both the TO–220 and D2PAK packages. For a high current regulator such as the CS5257A–1 the majority of heat is generated in the power transistor section. The value for RΘSA depends on the heat sink type, while the RΘCS depends on factors such as package type, heat sink interface (is an insulator and thermal grease used?), and the contact area between the heat sink and the package. Once these calculations are complete, the maximum permissible value of RΘJA can be calculated and the proper heat sink selected. For further discussion on heat sink selection, see our application note “Thermal Management for Linear Regulators,” document number SR006AN/D, available through the Literature Distribution Center or via our website at http://www.onsemi.com.




CS5257A–1 PACKAGE THERMAL DATA Parameter

TO–220 Five Lead

D2PAK, 5–Pin

Unit

RΘJC

Typical

1.4

1.4

°C/W

RΘJA

Typical

50

10–50*

°C/W



+,$' ' * #

! The CS5208–1 linear regulator provides 8.0 A at adjustable voltages from 1.25 V to 4.5 V. This adjustable device requires two external resistors to set the output voltage and provide the minimum load current for proper regulation. This regulator is intended for use as a post regulator and microprocessor supply. The fast loop response and low dropout voltage make this regulator ideal for applications where low voltage operation and good transient response are important. The circuit is designed to operate with dropout voltages as low as 1.0 V at 8.0 A. The regulator is protected against overload conditions with overcurrent and thermal shutdown protection circuitry. The regulator is available in a TO–220 package. Features • 1.25 V to 4.5 V VOUT at 8.0 A • Dropout Voltage < 1.0 V @ 8.0 A • 1.5% Trimmed Reference • Fast Transient Response • Thermal Shutdown • Current Limit • Short Circuit Protection

2

3

Tab = VOUT Pin 1. Adjust 2. VOUT 3. VIN

3.3 V @ 8.0 A 1

CS5208–1

A WL, L YY, Y WW, W

124

100 µF

Load 0.1 µF

1

CS5208–1 AWLYWW

VOUT

Adj



5.0 V VIN

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200

300 µF


ORDERING INFORMATION Device CS5208–1GT3

Package

Shipping

TO–220*

50 Units/Rail

*TO–220 is 3–pin, straight leaded.




776


CS5208–1 ABSOLUTE MAXIMUM RATINGS* Parameter

Value

Unit

6.0

V


0 ≤ TJ ≤ 150

°C


–60 to +150

°C

260 Peak

°C

2.0

kV

Input Voltage



ESD Damage Threshold 1. 10 second maximum. *The maximum package power dissipation must be observed.

ELECTRICAL CHARACTERISTICS ( 0°C ≤ TA ≤ 70°C, 0°C ≤ TJ ≤ 150°C, VAdj = 0 V, unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

1.234 (–1.5%)

1.253

1.271 (+1.5%)

V

Adjustable Output Voltage Reference Voltage

VIN = 2.75 V to 5.5 V, IOUT = 10 mA to 8.0 A

Line Regulation

VIN = 2.75 V to 5.5 V, IOUT = 10 mA

–

0.02

0.20

%

Load Regulation

VIN = 2.75 V, IOUT = 10 mA to 8.0 A

–

0.04

0.50

%


VIN = 5.0 V, ∆VOUT = +1.5%

–

5.0

10

mA

Adjust Pin Current

VIN = 2.75 V, IOUT = 10 mA

–

70

120

µA

Current Limit

VIN = 2.75 V, ∆VOUT = –1.5%

8.1

9.0

–

A


VIN = 2.75 V, VOUT = 0 V

6.0

8.5

–

A


VIN = 3.25 V Avg, VRIPPLE = 1.0 VP–P @ 120 Hz, IOUT = 4.0 A, CAdj = 0.1 µF; COUT = 22 µF

60

80

–

dB



–

0.002

–

%/W

Dropout Voltage (Minimum VIN–VOUT) (Note 4)

IOUT = 100 mA IOUT = 1.0 A IOUT = 2.75 A IOUT = 4.0 A IOUT = 8.0 A

– – – – –

0.92 0.93 0.94 0.95 0.96

1.15 1.15 1.15 1.15 1.30

V V V V V

RMS Output Noise


–

0.003

–

%VOUT


–

–

0.5

–

%


–

150

180

210

°C


–

–

25

–

°C

2. The minimum load current is the minimum current required to maintain regulation. Normally the current in the resistor divider used to set the output voltage is selected to meet the minimum load current requirement. 3. This parameter is guaranteed by design and is not 100% production tested. 4. Dropout voltage is defined as the minimum input/output voltage differential required to maintain 1.5% regulation. 5. This parameter is guaranteed by design, but not parametrically tested in production. However, a 100% thermal shutdown functional test is performed on each part.


CS5208–1 PACKAGE PIN DESCRIPTION Package Pin Number TO–220

Pin Symbol

Function

1

Adjust

This pin is connected to the low side of the internally trimmed 1.5% bandgap reference voltage and carries a bias current of about 70 µA. A resistor divider from Adj to VOUT and from Adj to ground sets the output voltage. Also, transient response can be improved by adding a small bypass capacitor from this pin to ground.

2

VOUT


3

VIN

This is the supply voltage for the regulator. For the device to regulate, this voltage should be between 1.1 V and 1.30 V (depending on the output current) greater than the output voltage.

VIN

BIAS and TSD

VREF

– EA +

+ IA –

VOUT

Adj



0.250 IO = 10 mA

0.225

VIN = 2.75 V



0.075 0.050 0.025 0 –0.025 –0.050 –0.075 –0.100 –0.125

TCASE = 125°C

0.200 0.175 0.150

TCASE = 25°C

0.125 0.100 0.075

TCASE = 0°C

0.050 0.025

–0.150

0 0

10 20 30 40 50 60 70 80 90 100 110 120 130

0

1

2

3

4

5

6

7

TJ (°C)

Output Current (A)




8

CS5208–1 90 IO = 10 mA



85 80 75 70 65 60

0

72.6 72.4 72.2 72.0 71.8 71.6 71.4 71.2 71.0 70.8 70.6 70.4 70.2 70

10 20 30 40 50 60 70 80 90 100 110 120 130

0.0

0.8

1.6

2.4

3.2

4.0

4.8

5.6

6.4

TCase (°C)

IOUT (A)


Figure 6. Adjust Pin vs. IOUT

7.2

8.0

20

1.25

18 16 Output Current (A)

Dropout Voltage (V)

1.00

0.75

0.50

0.25

14 12 10 8 6 4 2

0

0 1

2

3

4

5

6

7

8

0.0

Figure 8. Short Circuit vs. VIN – VOUT

0.98

80

0.96 TCASE = 25°C

TCASE = 125°C

0.92 0.90 0.88 0.86 TCASE = 0°C

0.80 2

70 60 50 VIN – VOUT = 2.0 V

40

VRIPPLE = 1.0 VPP IOUT = 4.0 A CAdj = 0.1 µF COUT = 22 µF

30 20

0.82 1

5.0 5.5


0.84

2.5 3.0 3.5 4.0 4.5

VIN – VOUT (V)

1.00

0.94

0.5 1.0 1.5 2.0

Output Current (A)



0

3

4

10

5

101

102

103

104

105

VIN – VOUT (V)

Frequency (Hz)




106

CS5208–1 APPLICATION NOTES THEORY OF OPERATION

OTHER ADJUSTABLE OPERATION CONSIDERATIONS

The CS5208–1 linear regulator has a composite PNP–NPN output stage that requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.

The CS5208–1 linear regulator has an absolute maximum specification of 6.0 V for the voltage difference between VIN and VOUT. However, the IC may be used to regulate voltages in excess of 6.0 V. The main considerations in such a design are power–up and short circuit capability. In most applications, ramp–up of the power supply to VIN is fairly slow, typically on the order of several tens of milliseconds, while the regulator responds in less than one microsecond. In this case, the linear regulator begins charging the output capacitor as soon as the VIN to VOUT differential is large enough that the pass transistor conducts current. VOUT is essentially at ground, and VIN is on the order of several hundred millivolts, so the pass transistor is in dropout. As VIN increases, the pass transistor will remain in dropout, and current is passed to the load until VOUT is in regulation. Further increase in VIN brings the pass transistor out of dropout. The result is that the output voltage follows the power supply ramp–up, staying in dropout until the regulation point is reached. In this manner, any output voltage may be regulated. There is no theoretical limit to the regulated voltage as long as the VIN to VOUT differential of 6.0 V is not exceeded. However, the maximum ratings of the IC will be exceeded in a short circuit condition. Short circuit conditions will result in the immediate operation of the pass transistor outside of its safe operating area. Over–voltage stresses will then cause destruction of the pass transistor before overcurrent or thermal shutdown circuitry can become active. Additional circuitry may be required to clamp VIN to VOUT differential to less than 6.0 V if failsafe operation is required. One possible clamp circuit is illustrated in Figure 12; however, the design of clamp circuitry must be done on an application by application basis. Care must be taken to ensure the clamp actually protects the design. Components used in the clamp design must be able to withstand the short circuit conditions indefinitely while protecting the IC.

ADJUSTABLE OPERATION Design Guidelines

This LDO adjustable regulator has an output voltage range of 1.25 V to 4.5 V. An external resistor divider sets the output voltage as shown in Figure 11. The regulator’s voltage sensing error amplifier maintains a fixed 1.25 V reference between the output pin and the adjust pin. A resistor divider network R1 and R2 causes a fixed current to flow to ground. This current creates a voltage across R2 that adds to the 1.25 V across R1 and sets the overall output voltage. The adjust pin current (typically 50 µA) also flows through R2 and adds a small error that should be taken into account if precise adjustment of VOUT is necessary. The output voltage is set according to the formula:

ǒR1 R) R2Ǔ ) R2

VOUT + VREF

1

IAdj

The term IAdj × R2 represents the error added by the adjust pin current. R1 is chosen so that the minimum load current is at least 10 mA. R1 and R2 should be of the same composition for best tracking over temperature. The divider resistors should be placed as close to the IC as possible and connected to the output with a seperate metal trace. VIN

VOUT

CS5208–1 Adj

R1

R2

EXTERNAL SUPPLY

Figure 11.

While not required, a bypass capacitor connected between the adjust pin and ground will improve transient response and ripple rejection. A 0.1 µF tantalum capacitor is recommended for “first cut” design. Value and type may be varied to optimize performance vs price.

VIN

VOUT VAdj

Figure 12.


CS5208–1 STABILITY CONSIDERATIONS

If the calculated current is greater than or equal to the typical short circuit current value provided in the specifications, serious thought should be given to including a protection diode.


VIN

CS5208–1 Adj


The internal current limit circuit limits the output current under excessive load conditions and protects the regulator.

ESR



The device includes foldback short circuit current limit that clamps the output current at approximately two amperes less than its current limit value. Thermal Shutdown

The thermal shutdown circuitry is guaranteed by design to become activated above a die junction temperature of 150°C and to shut down the regulator output. This circuitry includes a thermal hysteresis circuit with 25°C of typical hysteresis, thereby allowing the regulator to recover from a thermal fault automatically.

Protection Diodes

When large external capacitors are used with a linear regulator it is sometimes necessary to add protection diodes. If the input voltage of the regulator gets shorted, the output capacitor will discharge into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage and the rate at which VIN drops. In the CS5208–1 regulator, the discharge path is through a large junction and protection diodes are not usually needed. If the regulator is used with large values of output capacitance and the input voltage is instantaneously shorted to ground, damage can occur. In this case, a diode connected as shown in Figure 13 is recommended. A rule of thumb useful in determining if a protection diode is required is to solve for current I+

C

VOUT


High power regulators such as the CS5208–1 usually operate at high junction temperatures. Therefore, it is important to calculate the power dissipation and junction temperatures accurately to ensure that an adequate heat sink is used. Since the package tab is connected to VOUT on the CS5208–1, electrical isolation may be required for some applications. Also, as with all high power packages, thermal compound is necessary to ensure proper heat flow. For added safety, this high current LDO includes an internal thermal shutdown circuit The thermal characteristics of an IC depend on the following four factors. Junction temperature, ambient temperature, die power dissipation, and the thermal resistance from the die junction to ambient air. The maximum junction temperature can be determined by:

V T

where: I is the current flow out of the load capacitance when VIN is shorted, C is the value of the load capacitance, V is the output voltage, and T is the time duaration required for VIN to transition from high to being shorted.



RQJA

CS5208–1 RQJA + RQJC ) RQCS ) RQSA

The maximum ambient temperature and the power dissipation are determined by the design while the maximum junction temperature and the thermal resistance depend on the manufacturer and the package type. The maximum power dissipation for a regulator is: PD(max) + (VIN(max) * VOUT(min))IOUT(max) ) VIN(max)

RΘJC is rated @ 1.4°C/W for the CS5208–1. For a high current regulator such as the CS5208–1 the majority of heat is generated in the power transistor section. The value for RΘSA depends on the heat sink type, while the RΘCS depends on factors such as package type, heat sink interface (is an insulator and thermal grease used?), and the contact area between the heat sink and the package. Once these calculations are complete, the maximum permissible value of RΘJA can be calculated and the proper heat sink selected. For further discussion on heat sink selection, see application note “Thermal Management for Linear Regulators,” document number SR006AN/D, available through the Literature Distribution Center or via our website at http://onsemi.com.

IIN(max)

A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment has a thermal resistance. Like series electrical resistances, these resistances are summed to determine the total thermal resistance between the die junction and the surrounding air, RΘJC. This total thermal resistance is comprised of three components. These resistive terms are measured from junction to case (RΘJC), case to heat sink (RΘCS), and heat sink to ambient air (RΘSA). The equation is: PACKAGE THERMAL DATA Parameter

TO–220 THREE LEAD

Unit

RΘJC

Typical

1.4

°C/W

RΘJA

Typical

50

°C/W


+,$,' ' * ,

! This new very low dropout regulator is designed to power the next generation of advanced microprocessors. To achieve very low dropout, the internal pass transistor is powered separately from the control circuitry. Furthermore, with the control and power inputs tied together, this device can be used in single supply configuration and still offer a better dropout voltage than conventional PNP–NPN based LDO regulators. In this mode the dropout is determined by the minimum control voltage. It is supplied in a five–terminal TO–220 package, which allows for the implementation of a remote–sense pin permitting very accurate regulation of output voltage directly at the load, where it counts, rather than at the regulator. This remote sensing feature virtually eliminates output voltage variations due to load changes and resistive voltage drops. Typical load regulation measured at the sense pin is 1.0 mV for an output voltage of 2.5 V with a load step of 10 mA to 8.0 A. The very fast transient loop response easily meets the needs of the latest microprocessors. In addition, a small capacitor on the Adjust pin will further improve the transient capabilities. Internal protection circuitry provides for “bust–proof” operation, similar to three–terminal regulators. This circuitry, which includes overcurrent, short circuit, supply sequencing and overtemperature protection, will self protect the regulator under all fault conditions. The CS5258–1 is ideal for generating a secondary 2.0–2.5 V low voltage supply on a motherboard where both 5.0 V and 3.3 V are already available. Features • 1.25 V to 5.0 V VOUT at 8.0 A • VPOWER Dropout < 0.4 V @ 8.0 A • VCONTROL Dropout < 1.15 V @ 8.0 A • 1.5% Trimmed Reference • Fast Transient Response • Remote Voltage Sensing • Thermal Shutdown • Current Limit • Short Circuit Protection • Backwards Compatible with 3–Pin Regulators



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1 5 TO–220 FIVE LEAD T SUFFIX CASE 314D

MARKING DIAGRAM

CS5258–1 AWLYWW




783

Device

Package

Shipping

CS5258–1GT5

TO–220 FIVE LEAD

50 Units/Rail


CS5258–1 5.0 V VCONTROL

VOUT

CS5258–1 2.5 V @ 8.0 A 3.3 V

VPOWER

VSENSE Adjust

10 µF 10 V

100 µF 5.0 V

0.1 µF 5.0 V

124 1.0% 124 1.0%

300 µF 5.0 V

Load



Value

Unit


6.0

V


13

V

0 to 150

°C

–65 to +150

°C

2.0

kV

260 peak

°C





Test Conditions

Min

Typ

Max

Unit

Reference Voltage

VCONTROL = 2.75 V to 12 V, VPOWER = 2.15 V to 5.5 V, 10 mA ≤ IOUT ≤ 8.0 A

1.234 (–1.5%)

1.253

1.272 (+1.5%)

V

Line Regulation


–

0.02

0.2

%

Load Regulation (Note 2)


–

0.04

0.2

%



–

5.0

10

mA


VCONTROL = 2.75 V, VPOWER = 2.15 V, IOUT = 100 mA VCONTROL = 2.75 V, VPOWER = 2.15 V, IOUT = 4.0 A VCONTROL = 2.75 V, VPOWER = 1.75 V, IOUT = 4.0 A VCONTROL = 2.75 V, VPOWER = 2.15 V, IOUT = 8.0 A

– – – –

6.0 30 33 80

10 60 70 180

mA mA mA mA

Adjust Pin Current


–

60

120

µA

Current Limit


8.1

10

–

A



6.0

9.0

–

A

CS5258–1

2. This parameter is guaranteed by design and is not 100% production tested. 3. The minimum load current is the minimum current required to maintain regulation. Normally the current in the resistor divider used to set the output voltage is selected to meet the minimum load current requirement. 4. The VCONTROL pin current is the drive current required for the output transistor. This current will track output current with roughly a 1:100 ratio. The minimum value is equal to the quiescent current of the device.


CS5258–1 ELECTRICAL CHARACTERISTICS (continued) (0°C ≤ TA ≤ 70°C; 0°C ≤ TJ ≤ 150°C; VSENSE = VOUT and VADJ = 0 V; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

CS5258–1 Ripple Rejection (Note 5)

VCONTROL = VPOWER = 3.25 V Avg VRIPPLE = 1.0 VP–P @ 120 Hz, IOUT = 4.0 A, CADJ = 0.1 µF

60

80

–

dB

Thermal Regulation


–

0.002

–

%/W


VPOWER = 2.15 V, IOUT = 100 mA VPOWER = 2.15 V, IOUT = 1.0 A VPOWER = 2.15 V, IOUT = 2.75 A VPOWER = 2.15 V, IOUT = 4.0 mA VPOWER = 2.15 V, IOUT = 8.0 A

– – – – –

1.00 1.00 1.00 1.00 1.15

1.15 1.15 1.15 1.15 1.30

V V V V V


VCONTROL = 2.75 V, IOUT = 100 mA VCONTROL = 2.75 V, IOUT = 1.0 A VCONTROL = 2.75 V, IOUT = 2.75 A VCONTROL = 2.75 V, IOUT = 4.0 mA VCONTROL = 2.75 V, IOUT = 8.0 A

– – – – –

0.10 0.15 0.20 0.26 0.40

0.15 0.20 0.30 0.40 0.70

V V V V V

RMS Output Noise


–

0.003

–

%VOUT


–

–

0.5

–

%


–

150

180

210

°C


–

–

25

–

°C



–

–

50

mA



–

0.1

1.0

mA

5. This parameter is guaranteed by design and is not 100% production tested. 6. Dropout is defined as either minimum control voltage (VCONTROL) or minimum power voltage (VPOWER) to output voltage differential required to maintain 1.5% regulation at a particular load. 7. This parameter is guaranteed by design, but not parametrically tested in production. However, a 100% thermal shutdown functional test is performed on each part.


PIN SYMBOL

1

VSENSE


2

Adjust


3

VOUT


4

VCONTROL

This is the supply voltage for the regulator control circuitry. For the device to regulate, this voltage should be between 1.0 V and 1.3 V (depending on the output current) greater than the output voltage. The control pin current will be about 1.0% of the power pin output current.

5

VPOWER

FUNCTION

This is the power input voltage. This pin is physically connected to the collector of the power pass transistor. For the device to regulate, this voltage should be between 0.1 V and 0.7 V greater than the output voltage depending on the output current. The output load current of 8.0 A is supplied through this pin.


CS5258–1

VPOWER VCONTROL

BIAS and TSD

– +

VREF

EA

IA



0.100

0.10

0.075

0.09




0.050 0.025 0 –0.025 –0.050 –0.075 IO = 10 mA VCONTROL = 2.75 V VPOWER = 2.15 V

–0.100 –0.125 –0.150

0

VPOWER = 2.15 V VCONTROL = 2.75 V

0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0

10 20 30 40 50 60 70 80 90 100 110 120 130

0

1.0

2.0

TJ (°C)

81

80

79

70



90

77 75 73 71 69

40

60

80

100

6.0

7.0

8.0

60 50 40 30 20

67 20

5.0


83

0

4.0

Output Current (A)


65

3.0

120

140

160

10 1 10

VIN – VOUT = 2.0 V IOUT = 4.0 A VRIPPLE = 1.0 VP–P COUT = 22 µF CADJ = 0.1 µF 102

103

104

105

Frequency (Hz)

Temperature (°C)


Figure 5. Adjust Pin Current vs Temperature


106

CS5258–1 1.0

1.25 VCONTROL = 2.75 V VCONTROL Dropout Voltage (V)


0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2

VPOWER = 2.15 V 1.00

0.75

0.50

0.25

0.1 0

0 0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

0

1.0

2.0

4.0

5.0

6.0

7.0

8.0

Output Current (A)

Output Current (A)

Figure 7. VPOWER Dropout Voltage vs IOUT

Figure 8. VCONTROL Dropout vs IOUT

1200

100

1150


VPOWER = 3.3 V ∆VOUT = +1.0%

1100 1050

50 0 COUT = 330 µF CPOWER = 110 µF CCONTROL = 10 µF CADJ = 0.1 µF VCONTROL = 5.0 V VPOWER = 3.3 V VOUT = 2.5 V

–50

–100

1000 950

Current (A)


3.0

900 850 800 1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10

11

8.0 0 0

0

1

2


3

4

5

Time (µs)


Figure 10. Current Step Transient Response

77 14.0

VCONTROL = 2.75 V

VPOWER = 2.15 V VCONTROL = 2.75 V Adjust Pin Current (µA)

Output Current (A)

12.0 10.0 8.0 6.0 4.0

76

75

74

73 2.0 0

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5

4.0 4.5

5.0 5.5

72

0

VPOWER – VOUT (V)

1.0

2.0

3.0

4.0

5.0

6.0

7.0

Output Current (A)

Figure 11. Short Circuit Current vs VPOWER – VOUT

Figure 12. Adjust Pin Current vs Output Current


8.0

CS5258–1 75 VPOWER = 2.15 V IL = 10 mA

74



75

73

72

71

70 1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10

74

VCONTROL = 2.75 V IL = 10 mA

73

72

71

70 0.5

11

1.5

2.5

3.5

4.5

VPOWER – VOUT (V)


Figure 13. Adjust Pin Current vs VCONTROL – VOUT

Figure 14. Adjust Pin Current vs VPOWER – VOUT

916.4 Minimum Load Current (µA)

916.3 916.2


916.1 916.0 915.9 915.8 915.7 915.6 915.5 915.4 0.5

1.5

2.5

3.5

4.5

VPOWER – VOUT (V)


APPLICATIONS NOTES THEORY OF OPERATION The CS5258–1 linear regulator provides adjustable voltages from 1.25 V to 5.0 V at currents up to 8.0 A. The regulator is protected against short circuits, and includes a thermal shutdown circuit with hysteresis. The output, which is current limited, consists of a PNP–NPN transistor pair and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.

that there are no supply sequencing problems. The output voltage will not turn on until both supplies are operating. If the control voltage comes up first, the output current will be typically limited to about 3.0 mA until the power input voltage comes up. If the power input voltage comes up first the output will not turn on at all until the control voltage comes up. The output can never come up unregulated. The CS5258–1 can also be used as a single supply device with the control and power inputs tied together. In this mode, the dropout will be determined by the minimum control voltage.

VPOWER Function

The CS5258–1 utilizes a two supply approach to maximize efficiency. The collector of the power device is brought out to the VPOWER pin to minimize internal power dissipation under high current loads. VCONTROL provides power for the control circuitry and the drive for the output NPN transistor. VCONTROL should be at least 1.0 V greater than the output voltage. Special care has been taken to ensure


The CS5258–1 five terminal linear regulator includes a dedicated VSENSE function. This allows for true Kelvin sensing of the output voltage. This feature can virtually eliminate errors in the output voltage due to load regulation. Regulation will be optimized at the point where the sense pin is tied to the output.


CS5258–1 DESIGN GUIDELINES

before the VPOWER supply. This allows the IC to begin charging the output capacitor as soon as the VPOWER to VOUT differential is large enough that the pass transistor conducts. As VPOWER increases, the pass transistor will remain in dropout, and current is passed to the load until VOUT is in regulation. Further increase in the supply voltage brings the pass transistor out of dropout. In this manner, any output voltage less than 13 V may be regulated, provided the VPOWER to VOUT differential is less than 6.0 V. In the case where VCONTROL and VPOWER are shorted, there is no theoretical limit to the regulated voltage as long as the VPOWER to VOUT differential of 6.0 V is not exceeded. There is a possibility of damaging the IC when VPOWER – VIN is greater than 6.0 V if a short circuit occurs. Short circuit conditions will result in the immediate operation of the pass transistor outside of its safe operating area. Overvoltage stresses will then cause destruction of the pass transistor before overcurrent or thermal shutdown circuitry can become active. Additional circuitry may be required to clamp the VPOWER to VOUT differential to less than 6.0 V if fail safe operation is required. One possible clamp circuit is illustrated in Figure 17; however, the design of clamp circuitry must be done on an application by application basis. Care must be taken to ensure the clamp actually protects the design. Components used in the clamp design must be able to withstand the short circuit condition indefinitely while protecting the IC.


This LDO adjustable regulator has an output voltage range of 1.25 V to 5.0 V. An external resistor divider sets the output voltage as shown in Figure 16. The regulator’s voltage sensing error amplifier maintains a fixed 1.253V reference between the output pin and the adjust pin. VCONTROL

VOUT

CS5258–1 VPOWER

VSENSE Adjust

R1

R2

Figure 16. An External Resistor Divider Sets the Value of VOUT. The 1.253 V Reference Voltage Drops Across R1.


R1 ) R2 ) R2 R1

External Supply

IADJ

VCONTROL

The term IADJ × R2 represents the error added by the adjust pin current. R1 is chosen so that the minimum load current is a least 10 mA. R1 and R2 should be of the same composition for best tracking over temperature. The divider resistors should be located as close to the load as possible. While not required, a bypass capacitor connected between the adjust pin and ground will improve transient response and ripple rejection. A 0.1 µF tantalum capacitor is recommended for “first cut” design. Value and type may be varied to optimize performance vs. price.

VSENSE

VPOWER

VOUT

VADJ

Figure 17. Example Clamp Circuitry for VPOWER – VOUT > 6.0 V Stability Considerations


The output compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response, and loop stability. The capacitor value and type is based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive

The CS5258–1 linear regulator has an absolute maximum specification of 6.0 V for the voltage difference between VIN and VOUT. However, the IC may be used to regulate voltages in excess of 6.0 V. The two main considerations in such a design are the sequencing of power supplies and short circuit capability. Power supply sequencing should be such that the VCONTROL supply is brought up coincidentally with or


CS5258–1 I+C

solution. However, when the circuit operates at low temperatures, both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet provides this information. A 300 µF tantalum capacitor will work for most applications, but with high current regulators such as the CS5258–1 the transient response and stability improve with higher values of capacitor. The majority of applications for this regulator involve large changes in load current so the output capacitor must supply the instantaneous load current. The ESR of the output capacitor causes an immediate drop in output voltage given by: DV + DI

where: I is the current flow out of the load capacitance when VCONTROL is shorted, C is the value of load capacitance, V is the output voltage, and T is the time duration required for VCONTROL to transition from high to being shorted. If the calculated current is greater than or equal to the typical short circuit current value provided in the specifications, serious thought should be given to the use of a protection diode.

ESR


Current Limit


The device includes short circuit protection circuitry that clamps the output current at approximately two amperes less than its current limit value. This provides for a current foldback function, which reduces power dissipation even further under a direct shorted load.

Protection Diodes

When large external capacitors are used with a linear regulator it is sometimes necessary to add protection diodes. If the input voltage of the regulator gets shorted, the output capacitor will discharge into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage, and the rate at which VCONTROL drops. In the CS5258–1 regulator, the discharge path is through a large junction and protection diodes are not usually needed. If the regulator is used with large values of output capacitance and the input voltage is instantaneously shorted to ground, damage can occur. In this case, a diode connected as shown in Figure 18 is recommended. Use of the diode has the added benefit of bleeding VOUT to ground if VCONTROL is shorted. This prevents an unregulated output from causing system damage.

VCONTROL

Thermal Shutdown


High power regulators such as the CS5258–1 family usually operate at high junction temperatures. Therefore, it is important to calculate the power dissipation and junction temperatures accurately to ensure that an adequate heat sink is used. Since the package tab is connected to VOUT on the CS5258–1, electrical isolation may be required for some applications. Also, as with all high power packages, thermal compound is necessary to ensure proper heat flow. For added safety, this high current LDO includes an internal thermal shutdown circuit. The thermal characteristics of an IC depend on the following four factors: junction temperature, ambient temperature, die power dissipation, and the thermal resistance from the die junction to ambient air. The maximum junction temperature can be determined by:

VOUT

CS5257A–1 VPOWER

V T

VSENSE Adjust


RQJA


Figure 18. Diode Protection Against VCONTROL Short Circuit Conditions

A rule of thumb useful in determining if a protection diode is required is to solve for current


CS5258–1 RQJA + RQJC ) RQCS ) RQSA


The value for RΘJC is 1.4°C watt for the CS5258–1 in the TO–220 package. For a high current regulator such as the CS5258–1 the majority of heat is generated in the power transistor section. The value for RΘSA depends on the heat sink type, while the RΘCS depends on factors such as package type, heat sink interface (is an insulator and thermal grease used?), and the contact area between the heat sink and the package. Once these calculations are complete, the maximum permissible value of RΘJA can be calculated and the proper heat sink selected. For further discussion on heat sink selection, see our application note “Thermal Management for Linear Regulators,” document number SR006AN/D, available through the Literature Distribution Center or via our website at http://www.onsemi.com.

A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment has a thermal resistance which is measured in degrees per watt. Like series electrical resistances, these thermal resistances are summed to determine the total thermal resistance between the die junction and the surrounding air, RΘJA. This total thermal resistance is comprised of three components. These resistive terms are measured from junction to case (RΘJC), case to heat sink RΘCS), and heat sink to ambient air (RΘSA). The equation is: PACKAGE THERMAL DATA Parameter

TO–220 Five Lead

Unit

RΘJC

Typical

1.4

°C/W

RΘJA

Typical

50

°C/W


$'% # ( 1 ) ! The NCP2860 is a low noise, low dropout linear regulator that has been designed to supply 2.77 V/300 mA from 3.0 V to 6.0 V input. If wished, the “SET’’ pin enables to adjust the output voltage level that then depends on the voltage applied to this pin. The excellent performances the NCP2860 features in terms of transient responses, PSRR and noise, make it an ideal solution for audio applications (e.g. audio amplifier drivers).

http://onsemi.com MARKING DIAGRAM

Features

• • • • • • • • •

8

High Output Current (300 mA Max) Low Output Voltage Noise: 60 µVrms Low Dropout (150 mV @ Iout = 300 mA) Thermal Overload and Short Circuit Protections Very Low Consumption in Shutdown Mode (10 nA) High Power Supply Rejection Ratio (60 dB @ 1.0 kHz) FAULT Indicator Programmable Output Voltage Soft Start

Micro8t DM SUFFIX CASE 846A

8

LCZ AYW

1

1

A = Assembly Location Y = Year W = Work Week

PIN CONNECTIONS


• Cellular Phone • Handheld Instruments

IN

OUT

1

8

FAULT

IN

2

7

STDWN

GND

3

6

N.C.

OUT

4

5

SET

FAULT (Top View)

ORDERING INFORMATION Fault Detect

Device NCP2860DM277R2

Error Amplifier Bandgap

STDWN

– +

Shipping

Micro8

4000 Units/Reel

Drive and Current Limiting OUTPUT BUFFER

SHUTDOWN

Thermal Sensor

Package

Feedback Selection

OUT

Rint1

Rint2

GND



SET

792


NCP2860 PIN DESCRIPTION Pin

Name

Description

1, 4

OUT

2

IN

3

GND

Ground

5

SET

Ground the “SET’’ pin to set the output voltage to 2.77 V. Refer to the “output voltage setting’’ paragraph if you need to program another value.

6

N.C.

This pin is non–connected.

7

STDWN

8

FAULT

“OUT’’ is the regulator output. A low ESR, bypass capacitor should be connected for stable operation. “IN’’ is the supply input that is connected to the power source (up to 6.0 V). Bypass with a 2.2 µF capacitor.

If the “STDWN’’ pin is low, the circuit enters the shutdown mode. The “FAULT’’ terminal is a high impedance, open drain output. If the circuit is out of regulation, the voltage pin goes low. Otherwise (normal operation or shutdown mode), this pin is high impedance. Connect the pin to ground, if unused.

MAXIMUM RATINGS Rating

Symbol

Value

Vinmax

–0.3, +6.0

V

–

230

°C/W


TJmax

150

°C


TSmax

– 65 to +150

°C

Lead Temperature (Soldering, 10s)

TLmax

300

°C

ESD Capability Human Body Model Machine Model

– –

2.0 200

kV V

Latch–up Capability @ 85°C

–

+/–100

mA

Input Voltage, Shutdown Pin, Voltage Range (Note 1) Thermal Resistance (Note 2)

Unit

1. The recommended input voltage range for NCP2860 proper operation is 2.7 V to 6.0 V. 2. Circuit being mounted on a board that has no metal oxide traces attached to the leads. The addition of plated copper can lower the thermal resistance.


NCP2860 TYPICAL ELECTRICAL CHARACTERISTICS* (Vin = 3.6 V, SET = GND, TA from –25°C to +85°C, unless otherwise noted.) Symbol

Min

Typ

Max

Unit

Output Voltage @ Iout = 100 µA, 300 mA, Vin = 3.2 V and TA = 25°C TA from –25°C to +85°C

Vout

2.73 2.70

2.77 2.77

2.81 2.84

V

Supply Current @ Iout = 0, Vin = 3.2 V

Icc–0

–

355

700

µA

Supply Current @ Iout = 300 mA, Vin = 3.2 V

Icc–300

–

1.1

–

mA

Supply Current in Shutdown Mode (STDWN Pin Grounded) @ TA = 25°C

Istdwn

–

0.01

1.0

µA

Dropout Voltage @ Iout = 1.0 mA (Note 3)

Vdrop–1

–

0.6

–

mV

Dropout Voltage @ Iout = 150 mA (Note 3)

Vdrop–150

–

75

150

mV

Dropout Voltage @ Iout = 300 mA (Note 3)

Vdrop–300

–

150

–

mV

SET Threshold (SET = OUT) @ Iout = 1.0 mA and Vin = 3.6 V or 6.0 V, TA = 25°C TA from –25°C to +85°C

Vref

1.226 1.220

1.244 1.244

1.262 1.270

V

SET Input Leakage Current @ VSET = 1.25 V and TA = 25°C

Ileak

–

10

200

nA

Short Circuit Output Current Limitation @ Vin = 3.2 V and Vout = 2.2 V

Imax_cc

310

465

700

mA

Start–Up Current Limitation @ TA = 25°C, Vin = 3.2 V and Vout = 2.2 V

Imax_stup

–

220

–

mA

Line Regulation, Vin varying between 3.0 V and 6.0 V @ Iout = 1.0 mA

LineReg1

–0.1

0.01

0.1

%/V

Line Regulation, Vin varying between 3.0 V and 6.0 V @ Iout = 10 mA

LineReg2

–0.1

0.01

0.1

%/V

Line Regulation, Vin varying between 3.0 V and 6.0 V @ Iout = 1.0 mA and (SET = OUT)

LineReg3

–0.1

0.03

0.1

%/V

Line Regulation, Vin varying between 3.0 V and 6.0 V @ Iout = 10 mA and (SET = OUT)

LineReg4

–0.1

0.03

0.1

%/V

Load Regulation, Iout varying from 0.1 mA to 300 mA, SET = OUT, @ Vin = 3.2 V

LoadReg1

–

0.0002

–

%/mA

Load Regulation, Iout varying from 0.1 mA to 300 mA, SET Grounded, @ Vin = 3.2 V

LoadReg2

–

0.001

–

%/mA

– –

15 35

– –

– –

35 60

– –

Characteristic

Output Voltage Noise @ SET = OUT, Cout = 22 µF (Note 4) 10 Hz t f t 10 kHz 10 Hz t f t 100 kHz

–

µVrms

Output Voltage Noise @ SET = GND, Cout = 22 µF (Note 4) 10 Hz t f t 10 kHz 10 Hz t f t 100 kHz

–

Output Voltage Noise Density @ SET = GND, Cout = 22 µF, 10 Hz t f t 100 kHz (Note 4)

–

–

400

–

nV(Hz)–1/2

Power Supply Rejection Ratio @ 1.0 kHz and Iout = 100 mA

PSRR

–

60

–

dB

Shutdown Threshold (with hysteresis) @ Vin = 3.2 V

Vstdwn

0.4

–

2.0

V

Shutdown Pin Bias Current @ STDWN = IN or GND and TA = 25°C

lstdwn

–

–

100

nA

FAULT Detection Voltage @ Iout = 200 mA

Vfault–th

–

120

280

mV

FAULT Output Low Voltage @ Isink = 2.0 mA

Vfault–out

–

0.15

0.4

V

FAULT Output OFF Leakage Current @ TA = 25°C

Ifault

–

0.1

100

nA

Start–Up Time @ Cout = 10 µF, Vout = 2.7 V (Note 4)

Tstup

–

135

–

µs

Thermal Shutdown Threshold

Tlimit

–

170

–

°C


Htemp

–

30

–

°C

µVrms

*The specification gives the targeted values. This specification may have to be slightly adjusted after the temperature characterization of the die. 3. The dropout voltage is defined as (Vin–Vout) when Vout is 100 mV below the value of Vout when Vin = 3.1 V. 4. Refer to characterization curves for more details.


NCP2860 TYPICAL ELECTRICAL CHARACTERISTICS (Vin = Vout + 0.5 V, Cin = Cout = 2.2 mF, SET = GND, TA = 25°C, unless otherwise noted.) 0.80

0.4 Iout = 100 mA

0.2 OUTPUT VOLTAGE (%)

OUTPUT VOLTAGE (%)

Vout Normalized at Iout = 0 0.40

0.00

–0.40

Iout = 0 mA

0.0 –0.2

Iout = 200 mA

–0.4 –0.6 –0.8 –1.0

–0.80 60

120

180

240

–1.2

300

7

30

53

100

77

Figure 1. Normalized Output Voltage vs. Load Current

Figure 2. Normalized Output Voltage vs. Temperature 600

1000

500

800 TA = –40°C

TA = 85°C 600 TA = 25°C

400 200 0 40

80

120

160

200

TA = 25°C TA = +85°C

400 300

TA = –40°C 200 100 0 0.00

280

240

0.90

1.75

2.60

3.45

4.30

5.15 6.00

LOAD CURRENT (mA)

INPUT VOLTAGE (V)

Figure 3. Supply Current vs. Load Current

Figure 4. No Load Supply Current vs. Input Voltage 250 FAULT DETECT THRESHOLD (mV)

180 160 DROPOUT VOLTAGE (mV)

–17

TEMPERATURE (°C)

1200

0

–40

LOAD CURRENT (mA)

SUPPLY CURRENT (µA)

SUPPLY CURRENT (µA)

0

Vout Normalized at 30°C, Iout = 0

140

TA = 25°C

120 TA = 85°C

100 80

TA = –40°C

60 40 20 0 0

50

100

150

200

250

300

200

150

FAULT = HIGH

100

50

FAULT = LOW

0 0

50

100

150

200

250

LOAD CURRENT (mA)

LOAD CURRENT (mA)

Figure 5. Dropout Voltage vs. Load Current

Figure 6. Fault Detect Threshold vs. Load Current


300

NCP2860 TYPICAL ELECTRICAL CHARACTERISTICS (Vin = Vout + 0.5 V, Cin = Cout = 2.2 mF, SET = GND, TA = 25°C, unless otherwise noted.) 0

–20

Cout = 2.2 µF

PSSR (dB)

–30

RMS Noise 10 Hz to 100 kHz: 59 µVrms

1000

–40 Cout = 22 µF

–50

NOISE (nV/sqrt Hz)

–10

10000 Vin = 3.26 V SET = GND Iload = 10 mA

–60

100

–70

Vin = Vout + 1 V Cout = 22 µF Iload = 10 mA

–80 –90 0.01

0.1

1

10

100

1000

10 0.01

Figure 7. Power Supply Rejection Ratio

1

10

100

4.3 V Vin

3.3 V

C4 Mean 2.7612 V Vin = Vout + 200 mV

1000

Figure 8. Output Noise Spectral Density

C4 Max 2.780 V

Vout (200 mV/div)

0.10

FREQUENCY (kHz)

FREQUENCY (kHz)

ILoad = 200 mA

C4 Min 2.716 V

200 mA Iload Vout

0 mA

10 mV/div


Figure 10. Line Transient


NCP2860 TYPICAL ELECTRICAL CHARACTERISTICS (Vin = Vout + 0.5 V, Cin = Cout = 2.2 mF, SET = GND, TA = 25°C, unless otherwise noted.)

Vin (0.5 V/div)

C4 Max 2.77 V

C4 Max 2.79 V C4 Mean 712 mV

Vin (0.5 V/div)

Vout (0.5 V/div)

C4 Mean 711 mV C4 Min –30 mV

C4 Min –30 mV FAULT (2 V/div)

FAULT (2 V/div) Vout (0.5 V/div)

Figure 12. Power–Up Response (Iload = 100 mA)

Figure 11. Power–Down Response (Iload = 100 mA)

C4 Max 2.84 V

C4 Max 2.84 V Vout (1 V/div)

C4 Mean 1.496 V

Vout (1 V/div)

C4 Min –40 mV

C4 Mean 1.374 V C4 Min 0V

STDWN (2 V/div)

STDWN (2 V/div)

Figure 13. Shutdown/Power–Up (Vin = Vout + 0.5 V, Iload = 50 mA)

Figure 14. Shutdown/Power–Up (Vin = Vout + 0.5 V, Iload = 0 mA)


NCP2860 DETAILED OPERATING DESCRIPTION Internal Pass Transistor The NCP2860 incorporates a 0.5 Ω typical P–channel MOSFET pass transistor. The P–channel MOSFET requires no drive current and then compared to the PNP based regulators, this solution drastically reduces the quiescent current and associated losses.

If the output voltage is directly applied to the “SET’’ pin, Vout = Vref = 1.244 V. Vout OUT

Shutdown Block The circuit turns into shutdown mode when the shutdown pin is in low state. In this mode, the internal biasing current sources are disconnected so that the pass transistor is off and the consumption reduced to a minimum value. Practically, the shutdown consumption is in the range of 10 nA. When this function is unused, “IN’’ is generally applied to the shutdown pin.

R1 SET R2

NCP2860

Regulation The circuit incorporates a transconductance error amplifier. The error amplifier output varies in response to load and input voltage variations to control the pass transistor current so that the “OUT’’ pin delivers the wished voltage. No compensation capacitor is required.

Current Limitation The NCP2860 incorporates a short circuit protection that prevents the pass transistor current from exceeding 465 mA typically. The current limit is set to 220 mA during the start–up phase. Thermal Protection The thermal protection protects the die against excessive overheating. Practically, when the junction temperature exceeds 170°C, an internal thermal sensor sends a logical signal to the shutdown block so that the circuit enters the shutdown mode. Once the die has cooled enough (typically 30°C), the circuit enters a new working phase.

Fault Detection Circuitry The circuit detects when the input–output differential voltage is too low to ensure a correct load and line regulation at the output. The input–output differential threshold scales proportionally with the load current to be always just higher than the dropout. When the circuit detects a fault condition, an internal switch connects “FAULT’’ to ground. In normal operation, the “FAULT’’ terminal is an open–drain–N–channel MOSFET and if a pull–up resistor is connected between “OUT’’ and “FAULT’’, “FAULT’’ goes high. The pull–up resistor is generally selected in the range of 100 kΩ to minimize the current consumption.

Output Voltage Setting The output voltage is set to 2.77 V if the “SET’’ pin is grounded. It can also be programmed to a different value. To do so, a portion of the output voltage must be applied to the “SET’’ pin. If a (R1, R2) resistors divider is used, then: Vout = (1 + R1/R2) * Vref Therefore, as Vref typically equals 1.244 V: Vout = 1.244 * (1 + R1/R2).

Application Information It is recommended to use 2.2 mF capacitors on the input and on the output of the NCP2860. Capacitor type is not very critical. Simply the ESR should be lower than 0.5 Ω to ensure a stable operation over the temperature and output current ranges. It could be convenient to increase the capacitor size and its quality (lower ESR) only if it was necessary to further improve the noise performances, the Power Supply Rejection Ratio or the fast transient response.

Now if R1 and R2 are high impedance resistors, the leakage current that is absorbed by the “SET’’ pin, may have to be taken into account as follows: Vout = [1.244 * (1 + R1/R2)] + (R1*Ilk) where Ilk is the “SET’’ pin leakage current.


NCP2860

IN

(2)

(8)

FAULT

R3 100 k

Fault Detect Error Amplifier BANDGAP

STDWN

– +

Drive and Current Limiting

SHUTDOWN

Rint1

(7)

Feedback Selection

BATTERY Thermal Sensor

C1 2.2 µF

OUT

OUTPUT BUFFER

(1,4) R1

Rint2

SET

C2 2.2 µF

(5) R2 (3)

GND

Figure 15. With External Output Voltage Adjustment

IN

(2)

FAULT

(8)

R3 100 k

Fault Detect Error Amplifier BANDGAP

STDWN

– +

Drive and Current Limiting

SHUTDOWN

Rint1

(7) Thermal Sensor

Rint2

GND

(3)

Figure 16. Application for 2.77 V Output Voltage


(1,4) C2 2.2 µF

Feedback Selection

BATTERY C1 2.2 µF

OUT

OUTPUT BUFFER

SET

(5)

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http://onsemi.com MARKING DIAGRAMS 16 MC33 765 ALYW

TSSOP–16 DTB SUFFIX CASE 948F

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PIN CONNECTIONS 4C9.

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MC33765

The MC33765 is an ultra low noise, very low dropout voltage regulator with five independent outputs which is available in TSSOP 16 surface mount package. The MC33765 is available in 2.8 V. The output voltage is the same for all five outputs but each output is capable of supplying different currents up to 150 mA for output 4. The device features a very low dropout voltage (0.11 V typical for maximum output current), very low quiescent current (5.0 mA maximum in OFF mode, 130 mA typical in ON mode) and one of the output (output 3) exhibits a very low noise level which allows the driving of noise sensitive circuitry. Internal current and thermal limiting protections are provided. Additionally, the MC33765 has an independent Enable input pin for each output. It includes also a common Enable pin to shutdown the complete circuit when not used. The Common Enable pin has the highest priority over the five independent Enable input pins. The voltage regulators VR1, VR2 and VR3 have a common input voltage pin VCC1. The other voltage regulators VR4 and VR5 have a common input voltage pin VCC2. • Five Independent Outputs at 2.8V Typical, based upon voltage version • Internal Trimmed Voltage Reference • Vout Tolerance ±3.0% over the Temperature Range –40°C to +85°C • Enable Input Pin (Logic–Controlled Shutdown) for Each of the Five Outputs • Common Enable Pin to Shutdown the Whole Circuit • Very Low Dropout Voltage (0.11 V Typical for Output 1, 2, 3 and 5; 0.17 V Typical for Output 4 at Maximum Current) • Very Low Quiescent Current (Maximum 5.0 µA in OFF Mode, 130 µA Typical in ON Mode) • Ultra Low Noise for VR3 (30 µV RMS Max, 100 Hz < f < 100 kHz) • Internal Current and Thermal Limit • 100 nF for VR1, VR2, VR4 and VR5 and 1.0 µF for VR3 for Stability • Supply Voltage Rejection: 60 dB (Typical) @ f = 1.0 kHz

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MC33765DTB

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96 Units/Rail

MC33765DTBR2

TSSOP16

2500 Units/Reel


MC33765 Simplified Block Diagram ##

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MC33765 MAXIMUM RATINGS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating

Symbol

Pin #

Value

Unit


VCC

5.3

V

Thermal Resistance Junction–to–Air

RqJA

140

°C/W


TA

–40 to +85

°C

Maximum Operating Junction Temperature

TJ

125

°C

TJmax

150

°C

Tstg

–60 to +150

°C

Maximum Junction Temperature Storage Temperature Range

CONTROL ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS (For typical values TA = 25°C, for min/max values TA = –40°C to +85°C/ Max TJ = 125°C) Characteristics

Symbol

Pin #

Min

Typ

Max

Unit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Independent Enable Pins Input Voltage Range

VON/OFF(1–5)

Control Input Impedance

Logic “0”, i.e. OFF State Logic “1”, i.e. ON State

VON/OFF(1–5)

0

–

VCC

V

100

–

–

kW

– 2.0

– –

0.5 –

V

Common Enable Pin

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Voltage Range

VCE

Control Input Impedance

Logic “0”, i.e. OFF State Logic “1”, i.e. ON State

VCE

2

0

–

VCC

V

2

100

–

–

kW

2

– 2.0

– –

0.3 –

V

ELECTRICAL CHARACTERISTICS (For typical values TA = 25°C, for min/max values TA = –40°C to +85°C/ Max TJ = 125°C) Symbol

Characteristics

Min

Typ

Max

–

–

5.0

–

470

–

–

130

–

Unit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CURRENT CONSUMPTION with NO LOAD

Current Consumption at Logic “0” for the complete device, i.e. Common Enable and All Independent Enable pins at OFF State

IQOFF

Current Consumption at Logic “1” for the complete device, i.e. Common Enable and All Independents Enable pins at ON State

IQON1

Current Consumption at Logic “1”, Common Enable at ON State and All Independents Enable pins at OFF State

IQON2


mA mA mA

MC33765 REGULATOR ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS (For typical values TA = 25°C, for min/max values TA = –40°C to +85°C/ Max TJ = 125°C) Characteristics

Symbol

Pin #

Min

Typ

Max

Unit

VCC1, VCC2

15, 10

3.0

3.6

5.3

V

Regulator Output Voltage for VR1, VR2, VR3, VR4 and VR5 MC33765 (2.8V)

VOUT(1–5)

14, 13, 12, 11, 9

2.7

2.8

2.85

Dropout Voltage for VR1, VR2, VR3, VR5 (Note 1)

VCC–VOUT

14, 13, 12, 9

–

0.11

0.17

V

Dropout Voltage for VR4 (Note 1)

VCC–VOUT4

11

–

0.17

0.30

V

Load Regulation (TA = 25°C)

Regload(1–5)

9, 11, 12,

–

–

0.5

mV/ mA

Supply and Output Voltages, Dropout and Load Regulation Supply Voltage VCC

MC33765 (2.8V)

V

13, 14

Max Power Dissipation and Total DC Output Current (VR1 + VR2 + VR3 + VR4 + VR5) (Note 2) Max Power Dissipation at VCC = 5.3 V (TA = 85°C) Max. Total RMS Output Current at VCC = 5.3 V (TA = 85°C)

Pdmax IRMS

– –

– –

285 130

mW mA

Max Power Dissipation at VCC = 5.3 V (TA = 25°C) Max. Total RMS Output Current at VCC = 5.3 V (TA = 25°C)

Pdmax IRMS

– –

– –

700 250

mW mA

Output Currents (Note 3) Regulator VR1 Output Current

IOUT1

14

10

–

30

mA

Regulator VR2 Output Current

IOUT2

13

10

–

40

mA


IOUT3

12

0

–

50

mA


IOUT4

11

10

–

150

mA


IOUT5

9

10

–

60

mA

Current Limit for VR1, VR2, VR3, VR4, VR5 [Twice the max Output Current for each output]

IMAX

14, 13, 12, 11, 9

–

2 X IOUT (1–5)

–

mA

C(1–2, 4–5)

14, 13, 11, 9

0.10

–

1.0

mF

C4

12

1.0

–

–

mF

0.05

1.0

3.0

W

50

60

–

dB

40

45

–

dB

External Capacitors External Compensation Capacitors for VR1, VR2, VR4, VR5 External Compensation Capacitors for VR3 External Compensation Capacitors ESR

Ripple Rejections Ripple Rejection VR1, VR2, VR4, VR5 (at Max. Current, 1.0 kHz, C = 100 nF) Ripple Rejection VR1, VR2, VR4, VR5 (at Max. Current, f = 10 kHz, C = 100 nF) Ripple Rejection of VR3 (at Max. Current, f = 1.0 kHz, C = 1.0 mF) Ripple Rejection of VR3 (at Max. Current, f = 10 kHz, C = 1.0 mF) Ripple Rejection of VR3 (at Max. Current, f = 100 kHz, C = 1.0 mF)

)

14, 13,

)

11, 9

(DV

OUT

(DV

CC

)

14, 13,

)

11, 9

)

12

50

60

–

dB

12

40

45

–

dB

12

18

22

–

dB

(DV

OUT

(DV

CC

(DV

OUT

(DV

CC

)

(DV

OUT

(DV

CC

(DV

OUT

(DV

CC

)

) )

)

1. Typical dropout voltages have been measured at currents: Output1: 25 mA, Output2: 35 mA, Output3: 40 mA, Output4: 140 mA, Output5: 40 mA Maximum value of dropout voltages are measured at maximum specified current. 2. See package power dissipation and thermal protection. 3. Maximum Output Currents are peak values. Total DC current have to be set upon maximum power dissipation specification. Only Output 3 has been designed to be stable at minimum current of 0 mA.


MC33765 REGULATOR ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS (For typical values TA = 25°C, for min/max values TA = –40°C to +85°C/Max TJ = 125°C) Symbol

Min

Typ

Max

Unit

VR1, VR2, VR4, VR5 with COUT = 100 nF, TA = 25°C VR3 with COUT = 1.0 mF, TA = 25°C

ton

– –

– –

30 150

ms ms

Fall Time (99% → 1%) [COUT = 100 nF, IOUT = 30 mA] (Note 4)

toff

–

100

–

ms

–

5

8

%

–

95

–

ms

VR1, VR2, VR4, VR5 with COUT = 100 nF

–

40

–

VR3 with COUT = 1.0 mF

–

25

30

Static crosstalk (DC shift) between the Regulator Output, TA = 25°C (Note 5)

–

150

200

mV

Dynamic CrossTalk Attenuation between the Regulator Outputs (f = 10 kHz), TA = 25°C (Note 6)

30

35

–

dB

–

160

–

°C

Characteristics

Dynamic Parameters Rise Time (1% → 99%) Common Enable at ON state, Cbypass = 10 nF, Iout at max. current

Overshoot (COUT = 100 nF for VR1, VR2, VR4, VR5 and COUT = 1.0 mF for VR3) at TA = 25°C Common Enable at ON state, independent enable from OFF to ON state Settling Time (to ±0.1% of nominal) at TA = 25°C Common Enable at ON state, independent enable from OFF to ON state

Noise and Crosstalks mV RMS

Noise Voltage (100 Hz < f < 100 kHz) with Cbypass = 100 nF

Thermal Shutdown Thermal Shutdown

4. The Fall time is highly dependent on the load conditions, i.e. load current for a specified value of COUT. 5. Static Crosstalk is a DC shift caused by switching ON one of the outputs through independent enable to all other outputs. This parameter is highly dependent on overall PCB layout and requires the implementation of low–noise GROUND rules (e.g. Ground plane). 6. Dynamic crosstalk is the ratio between a forced output signal to signal transferred to other outputs. This requires special device configuration to be measured.


MC33765 MC33765 TYPICAL OSCILLOSCOPE SHOTS 8J µ+ 2 =J + 2 =J + 2 , . , °#

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8J + 2 =J + 2 =J µ + 2 , . , °#

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Figure 1. Crosstalk response of MC33765 showing extremely weak interaction between outputs Output 4 is banged from 0 to 150mA

8J µ+ 2 =J + 2 =J + 2 , . , °#

Figure 2. Repetitive Common Enable response time

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Figure 3. Single Common Enable response time (Cbypass discharged)

Figure 4. Output response from seperate Enable


MC33765

=

=

8J µ+ 2 =J + 2 , . , °#

8J µ+ 2 =J + 2 , . , °#

Figure 5. Output 4 is banged from 3mA to 150mA

Figure 6. Output 5 is banged from 3mA to 50mA

=

= =

=

8J µ+ 2 =J + 2 =J + 2 , 2. .H/1 . , °#

8J µ+ 2 =J + 2 =J + 2 , 2. .H/1 . , °#

Figure 7. Typical input voltage rejection (Cout = 100nF)

Figure 8. Typical input voltage rejection (Cout = 1µF)


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Figure 11. Maximum Output Current versus Temperature

Figure 12. Dropout Voltage versus Operating Temperature: OUT1

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MC33765 DEFINITIONS Load Regulation – The change in output voltage for a change in load current at constant chip temperature. Dropout Voltage – The input/output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. Measured when the output drops 100 mV below its nominal value (which is measured at 1.0 V differential input/output), dropout voltage is affected by junction temperature, load current and minimum input supply requirements. Output Noise Voltage – The RMS AC voltage at the output with a constant load and no input ripple, measured over a specified frequency range.

As the device can be switched ON/OFF through independent Enable (ON/OFF pin) or Common Enable, the output signal could be, for example, a square wave. Let’s assume that the device is ON during TON on a signal period T. The RMS current will be given by: I

out RMS

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T D + ON T

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Depending on ambient temperature, it is possible to calculate the maximum power dissipation and so the maximum RMS current as following:

T –T Pd + J A R qJA

-1K1BC '5>(

The maximum operating junction temperature TJ is specified at 125°C, if TA = 25°C, then PD = 700 mW. By neglecting the quiescent current, the maximum power dissipation can be expressed as:

Maximum Power Dissipation – The maximum total dissipation for which the regulator will operate within specifications. Quiescent Current – Current which is used to operate the regulator chip with no load current. Line Regulation – The change in input voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. Thermal Protection – Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated, typically 160°C, the regulator turns off. This feature is provided to prevent catastrophic failures from accidental overheating. Maximum Package Power Dissipation and RMS Current – The maximum package power dissipation is the power dissipation level at which the junction temperature reaches its maximum value i.e. 125°C. The junction temperature is rising while the difference between the input power (VCC X ICC) and the output power (Vout X Iout) is increasing. As MC33765 device exhibits five independent outputs Iout is specified as the maximum RMS current combination of the five output currents.

I out +

P D V – Vout CC

So that in the more drastic conditions: VCC = 5.3 V, Vout = 2.7 V then the maximum RMS value of Iout is 269 mA. The maximum power dissipation supported by the device is a lot increased when using appropriate application design. Mounting pad configuration on the PCB, the board material and also the ambient temperature are affected the rate of temperature rise. It means that when the IC has good thermal conductivity through PCB, the junction temperature will be “low” even if the power dissipation is great. The thermal resistance of the whole circuit can be evaluated by deliberately activating the thermal shutdown of the circuit (by increasing the output current or raising the input voltage for example). Then you can calculate the power dissipation by subtracting the output power from the input power. All variables are then well known: power dissipation, thermal shutdown temperature (160°C for MC33765) and ambient temperature. R


qJA

T –T + J A P D

MC33765 DESIGN HINTS Reducing the cross–talk between the MC33765 outputs One of the origin of the DC shift finds its seat in the layout surrounding the integrated circuit. Particular care has to be taken when routing the output ground paths. Star grounding

or a ground plane are the absolute conditions to reduce the noise or shift associated to common impedance situations, as depicted by Figure 17.

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Figure 17. Star Cabling Avoids Coupling by Common Ground Impedance

The first left cabling will generate a voltage shift which will superimpose on the output voltages, thus creating an undesirable offset. By routing the return grounds to a single

low impedance point, you naturally shield the circuit against common impedance disturbances. Figure 18 portraits the text fixture implemented to test the response of the MC33765. ##

-

MC33765

-

0

9

µ-

9

-

Figure 18. DC Shift Text Fixture


MC33765 DESIGN HINTS (cont.) Output 4 was banged from 0 to 150mA via its dedicated control pin, while output 3 fixed at 50mA was monitored. The circuit has been implemented on a PCB equipped with a

ground plane and routed with short copper traces. The results are shown hereafter, revealing the excellent behavior of the MC33765 when crosstalks outputs is at utmost importance.

= 9

= 9

Figure 19. Vin = 4V, Y1 = 62.5µV/div, F = 200Hz

Figure 20. Vin = 5V, Y1 = 1mV/div


MC33765 TECHNICAL TERMS Overshoot, Settling Time – As regulators are based on regulation loop through an error amplifier, this type of device requires a certain time to stabilize and reach its nominal value. The overshoot is defined as the voltage difference between the peak voltage and steady state when switching ON the regulator. The settling time is equal to the time required by the regulator to stabilize to its nominal value (±0.5%) after peak value when switching ON the regulator.

Rise Time – Common Enable being in ON state, the device is switched on by ON/OFF pin control. Let’s call t1 the time when ON/OFF signal reaches 1% of its nominal value. Let’s call t2 the time when output signal reaches 99% of its nominal value. The rise time for this device is specified as: t

ON

+ t1 * t2

Fall Time – The fall time is highly dependent on the output capacitor and so device design is not impacting at all this parameter.

61/ I 1

$ 1 1

21D

9 /.I1

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"##%$ 3 ! 4 *2* The MC33762 is a dual Low DropOut (LDO) regulator featuring excellent noise performances. Thanks to its innovative design, the circuit reaches an impressive 40 µVRMS noise level without an external bypass capacitor. Housed in a small µ8 package, it represents the ideal designer’s choice when space and noise are at premium. The absence of external bandgap capacitor accelerates the response time to a wake–up signal and keeps it within 40 µs, making the MC33762 as a natural candidate for portable applications. The MC33762 also hosts a novel architecture which prevents excessive undershoots in the presence of fast transient bursts, as in any bursting systems. Finally, with a static line regulation better than –75 dB, it naturally shields the downstream electronics from choppy lines.

http://onsemi.com

8 1 Micro8t DM SUFFIX CASE 846A

Features

• Nominal Output Current of 80 mA with a 100 mA Peak Capability • Ultra–Low Noise: 150 nV/√Hz @ 100 Hz, 40 µVRMS

•

100 Hz–100 kHz Typical, Iout = 60 mA, Co = 1.0 µF Fast Response Time from OFF to ON: 40 µs Typical Ready for 1.0 V Platforms: ON with a 900 mV High Level Typical Dropout of 90 mV @ 30 mA, 160 mV @ 80 mA Ripple Rejection: 70 dB @ 1.0 kHz 1.5% Output Precision @ 25°C Thermal Shutdown Vout Available at 2.5 V, 2.8 V, and 3.0 V Separate Dice for Each Regulator Provides Maximum Isolation Between Regulators Operating Range from –40 to +85°C

Gnd1 1 En1 2 Gnd2 3

8 Vout1

762 YWW

• • • • • • • •

PIN CONFIGURATION AND MARKING DIAGRAM

7 VCC1 6 Vout2 5 VCC2

En2 4 (Top View)

Y = Year WW = Work Week


Applications

• Noise Sensitive Circuits: VCOs RF Stages, etc. • Bursting Systems (TDMA Phones) • All Battery Operated Devices



813


MC33762

EN1

On/Off

2

7

VCC1

8

Vout

5

VCC2

6

Vout

Thermal Shutdown

Band Gap Reference

GND1 EN2

1


On/Off

4

Thermal Shutdown

Band Gap Reference

GND2

3



PIN FUNCTION DESCRIPTIONS Pin #

Pin Name

1

Gnd1

Function

Description

2

En1

3

Gnd2

4

En2

Enables the 2nd LDO

A 900 mV level on this pin is sufficient to start this LDO. A 150 mV shuts it down.

5

Vcc2

2nd LDO Vcc pin

This pin brings the power to the 1st LDO and requires adequate decoupling.

6

Vout2

Shuts or wakes–up the IC


7

Vcc1

1st LDO Vcc pin

This pin brings the power to the 1st LDO and requires adequate decoupling.

8

Vout1



Ground of the 1st LDO Enables the 1st LDO

A 900 mV level on this pin is sufficient to start this LDO. A 150 mV shuts it down.

Ground of the 2nd LDO

MAXIMUM RATINGS Value Rating

Pin #

Symbol

Min

Max

Unit

1

Vin

–

12

V


All Pins

–

–

1.0

kV


All Pins

–

–

200

V


–

PD

–

Internally Limited

W

–

RqJ–A

–

240

°C/W


– – –

TA TJmax TJ

– – –

–40 to +85 150 125

°C °C °C


–

Tstg

–

–60 to +150

°C


1. Internally limited by shutdown. 2. Specifications are guaranteed below this value.


MC33762 ELECTRICAL CHARACTERISTICS (For typical values TA = 25°C, for min/max values TA = –40°C to +85°C, max TJ = 125°C unless otherwise noted) Pin #

Symbol

Min

Typ

Max

Unit

Input Voltage Range

2–4

VON/OFF

0

–

Vin

V

ON/OFF Input Resistance (all versions)

2–4

RON/OFF

–

250

–

kW


2–4

VON/OFF – 900

– –

150 –

Characteristics

Logic Control Specifications

mV

Currents Parameters Current Consumption in OFF State (all versions) OFF Mode Current: Vin = Vout + 1.0 V, IO = 0, VOFF = 150 mV

–

IQOFF

–

0.1

2.0

mA

Current Consumption in ON State (all versions) ON Mode Current: Vin = Vout + 1.0 V, IO = 0, VON = 3.5 V

–

IQON

–

180

–

mA

Current Consumption in ON State (all versions), ON Mode Saturation Current: Vin = Vout – 0.5 V, No Output Load

–

IQSAT

–

800

–

mA

Current Limit Vin = Voutnom + 1.0 V, Output is brought to Voutnom – 0.3 V (all versions)

–

IMAX

100

180

–

mA

5–7

Vout

2.462

2.5

2.537

V

2.8 V

5–7

Vout

2.758

2.8

2.842

V

3.0 V

5–7

Vout

2.955

3.0

3.045

V

3.3 V

5–7

Vout

3.250

3.3

3.349

V

3.6 V

5–7

Vout

3.546

3.6

3.654

V


5–7

Vout

–1.5

X

+1.5

%

Vout + 1.0 V < Vin < 6.0 V, TA = –40°C to +85°C, 1.0 mA < Iout < 80 mA 2.5 V

5–7

Vout

2.425

2.5

2.575

V

2.8 V

5–7

Vout

2.716

2.8

2.884

V

3.0 V

5–7

Vout

2.91

3.0

3.090

V

3.3 V

5–7

Vout

3.201

3.3

3.399

V

3.6 V

5–7

Vout

3.492

3.6

3.708

V

5–7

Vout

–3.0

X

+3.0

%

Line Regulation (all versions) Vout + 1.0 V < Vin < 12 V, Iout = 80 mA

5–7

Regline

–

–

20

mV

Load Regulation (all versions) Vin = Vout + 1.0 V, Cout = 1.0 mF, Iout = 1.0 to 80 mA

5–7

Regload

–

–

40

mV

5–7 5–7 5–7


– – –

90 140 160

150 200 250

Output Voltages Vout + 1.0 V < Vin < 6.0 V, TA = 25°C, 1.0 mA < Iout < 80 mA 2.5 V


Line and Load Regulation, Dropout Voltages

Dropout Voltage (all versions) (Note 3) Iout = 30 mA Iout = 60 mA Iout = 80 mA

mV

3. Voltage slope should be greater than 2.0 mV/ms


MC33762 ELECTRICAL CHARACTERISTICS (continued) (For typical values TA = 25°C, for min/max values TA = –40°C to +85°C, max TJ = 125°C unless otherwise noted) Pin #

Symbol

Min

Typ

Max

Unit

Ripple Rejection (all versions) Vin = Vout + 1.0 V + 1.0 kHz 100 mVpp Sinusoidal Signal

5–7

Ripple

–

–70

–

dB

Output Noise Density @ 1.0 kHz

5–7

–

–

150

–

nV/ √Hz

RMS Output Noise Voltage (all versions) Cout = 1.0 mF, Iout = 50 mA, F = 100 Hz to 1.0 MHz

5–7

Noise

–

35

–

mV

Output Rise Time (all versions) Cout = 1.0 mF, Iout = 50 mA, 10% of Rising ON Signal to 90% of Nominal Vout

5–7

trise

–

40

–

ms

–

–

–

–

125

°C

Characteristics

Dynamic Parameters

Thermal Shutdown Thermal Shutdown (all versions)


MC33762 DEFINITIONS Load Regulation

Line Regulation



Dropout Voltage


Thermal Protection








Quiescent Current

The quiescent current is the current which flows through the ground when the LDO operates without a load on its output: internal IC operation, bias etc. When the LDO becomes loaded, this term is called the Ground current. It is actually the difference between the input current (measured through the LDO input pin) and the output current.


MC33762 Characterization Curves Curves are Common to Both Regulators

4.5

185

GROUND CURRENT (mA)

3.5

QUIESCENT CURRENT (m A)

–40°C 25°C 85°C

4.0

3.0 2.5 2.0 1.5 1.0

180

175

170

0.5 0 0

20


80

165 –60

100


–20 0 20 40 60 AMBIENT TEMPERATURE (°C)

80

100

Figure 3. Quiescent Current versus Temperature 2.805

200 85°C 25°C –40°C 100

50

85°C


150

40°C 2.795 2.790 2.785

25°C 0°C

2.780

–20°C –40°C

0

2.775 0

20


80

100

0

20

Figure 4. Dropout versus Output Current


80 mA

160

60 mA

140 120

30 mA

100 80 60 40 20 0 –60

1.0 mA –40

–20

80



DROPOUT (mV)

–40

20 40 0 TEMPERATURE (°C)

60

80

Figure 6. Dropout versus Temperature


100

100

MC33762 APPLICATION HINTS Input Decoupling

Protections

As with any regulator, it is necessary to reduce the dynamic impedance of the supply rail that feeds the component. A 1.0 µF capacitor either ceramic or tantalum is recommended and should be connected close to the MC33762 package. Higher values will correspondingly improve the overall line transient response.

The MC33762 hosts several protections, giving natural ruggedness and reliability to the products implementing the component. The output current is internally limited to a maximum value of 180 mA typical while temperature shutdown occurs if the die heats up beyond 125°C. These values let you assess the maximum differential voltage the device can sustain at a given output current before its protections come into play. The maximum dissipation the package can handle is given by:

Output Decoupling

Thanks to a novel concept, the MC33762 is a stable component and does not require any specific Equivalent Series Resistance (ESR) neither a minimum output current. Capacitors exhibiting ESRs ranging from a few mW up to 3.0 W can thus safely be used. The minimum decoupling value is 1.0 µF and can be augmented to fulfill stringent load transient requirements. The regulator accepts ceramic chip capacitors as well as tantalum devices.

T *T A P max + Jmax R qJA

If TJmax is limited to 125°C, then the MC33762 can dissipate up to 395 mW @ 25°C. The power dissipated by the MC33762 can be calculated from the following formula:

ǒ

Noise Performances

Ptot + V

Unlike other LDOs, the MC33762 is a true low–noise regulator. Without the need of an external bypass capacitor, it typically reaches the incredible level of 40 µVRMS overall noise between 100 Hz and 100 kHz. To give maximum insight on noise specifications, ON Semiconductor includes spectral density graphics. The classical bypass capacitor impacts the start–up phase of standard LDOs. However, thanks to its low–noise architecture, the MC33762 operates without a bypass element and thus offers a typical 40 µs start–up phase.

in

I

Ǔ


I out

or Vin max +

Ptot ) V out I

gnd

I out

) I out

If a 80 mA output current is needed, the ground current is extracted from the data–sheet curves: 4.0 mA @ 80 mA. For a half 2.8 V MC33762 (2.8 V) operating at 25°C, the maximum input voltage will then be 7.3 V. Typical Applications

The following picture portrays the typical application of the MC33762.


MC33762 Input 1

8

2

7

3

6

4

5

Output 1 Output 2

MC33762 + C3 1.0 mF

Regulator 1

On/Off

+ + C1 C2 1.0 mF 1.0 mF

Regulator 2 R1 100 k

On/Off

R2 100 k

Figure 7. A Typical Application Schematic

As for any low noise designs, particular care has to be taken when tackling Printed Circuit Board (PCB) layout. Connections shall be kept short and wide. Layout example

as given in the MC33761 application hints can be used as a starting basis.


MC33762 Understanding the Load Transient Improvement During this decreasing phase, the LDO stops the PNP bias and one can consider the LDO asleep (Figure 8). If by misfortune a current shot appears, the reaction time is incredibly lengthened and a strong undershoot takes place. This reaction is clearly not acceptable for line sensitive devices, such as VCOs or other Radio–Frequency parts. This problem is dramatically exacerbated when the output current drops to zero rather than a few mA. In this later case, the internal feedback network is the only discharge path, accordingly lengthening the output voltage decay period (Figure 9). The MC33762 cures this problem by implementing a clever design where the LDO detects the presence of the overshoot and forces the system to go back to steady–state as soon as possible, ready for the next shot. Figure 10 and 11 show how it positively improves the response time and decreases the negative peak voltage.

The MC33762 features a novel architecture which allows the user to easily implement the regulator in burst systems where the time between two current shots is kept very small. The quality of the transient response time is related to many parameters, among which the closed–loop bandwidth with the corresponding phase margin plays an important role. However, other characteristics also come into play like the series pass transistor saturation. When a current perturbation suddenly appears on the output, e.g. a load increase, the error amplifier reacts and actively biases the PNP transistor. During this reaction time, the LDO is in open–loop and the output impedance is rather high. As a result, the voltage brutally drops until the error amplifier effectively closes the loop and corrects the output error. When the load disappears, the opposite phenomenon takes place with a positive overshoot. The problem appears when this overshoot decays down to the LDO steady–state value.

Figure 8. A Standard LDO Behavior when the Load Current Disappears

Figure 9. A Standard LDO Behavior when the Load Current Appears in the Decay Zone

Figure 10. Without Load Transient Improvement

Figure 11. MC33762 with Load Transient Improvement


MC33762 MC33762 Has a Fast Start–Up Phase unacceptable level. MC33762 offers the best of both worlds since it no longer includes a bypass capacitor and starts in less than 40 µs typically (Repetitive at 200 Hz). It also ensures an incredible low–noise level of 40 µVRMS 100 Hz–100 kHz. The following picture details the typical 33762 startup phase.

Thanks to the lack of bypass capacitor the MC33762 is able to supply its downstream circuitry as soon as the OFF to ON signal appears. In a standard LDO, the charging time of the external bypass capacitor hampers the response time. A simple solution consists in suppressing this bypass element but, unfortunately, the noise rises to an

Figure 12. Repetitive Start–Up Waveforms


MC33762 TYPICAL TRANSIENT RESPONSES

Figure 13. Output is Pulsed from 2.0 mA to 80 mA

Figure 14. Discharge Effects from 0 to 40 mA




MC33762 TYPICAL TRANSIENT RESPONSES 250

nV/sqrt Hz

200

Vin = Vout + 1.0 V TA = 25°C Cout = 1.0 mF

RMS Noise, IO = 50 mA: 20 Hz – 100 kHz: 27 mV 20 Hz – 1.0 MHz: 30 mV

IO = 50 mA

150

10 mA 100

50

RMS Noise, IO = 10 mA: 20 Hz – 100 kHz: 29 mV 20 Hz – 1.0 MHz: 31 mV

0 100

1,000

10,000 100,000 f, FREQUENCY (Hz)

1,000,000

Figure 17. MC33762 Typical Noise Density Performance

0

3.5

–10

IO = 1.0 mA

3.0

–20 2.5

(dB)

–40

Z O (OHMS)

–30 IO = 50 mA

–50 –60 –70

10 mA

–90

1.5 80 mA

1.0 Vin = VO + 1.0 V TA = 25°C Cout = 1.0 mF

–80

10 mA

2.0

0.5 20 mA

–100

0 100

1,000

100,000 10,000 f, FREQUENCY (Hz)

1,000,000

100

Figure 18. MC33762 Typical Ripple Rejection Performance

1,000

100,000 10,000 f, FREQUENCY (Hz)

Figure 19. Output Impedance Plot Cout = 1.0 mF, Vin = Vout + 1.0 V


1,000,000

MC33762 MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface

between the board and the package. With the correct pad geometry, the packages will self–align when subjected to a solder reflow process. 0.041 1.04

0.208 5.28

0.126 3.20

0.015 0.38

0.0256 0.65 inches mm


MC33762 ORDERING INFORMATION Part Number

Voltage Output

Package

Shipping

MC33762DM–2525R2

2.5 V & 2.5 V

Micro8


MC33762DM–2828R2

2.8 V & 2.8 V

Micro8


MC33762DM–3030R2

3.0 V & 3.0 V

Micro8



"##,%% +( ! . 4 / The MC33566 Low Dropout Regulator is designed for computer peripheral card applications complying with the instantly available requirements as specified by ACPI objectives. The MC33566 permits glitch–free transitions from “sleep” to “active” system modes and has internal logic circuitry to detect whether the system is being powered from the motherboard main 5.0 V power supply or the 3.3 V aux supply. The MC33566 provides a regulated output voltage of 3.3 V via either an internal low dropout 5.0 V–to–3.3 V voltage regulator or an external P–channel MOSFET, depending on the operating status of the system in which the card is installed. During normal operating mode (5.0 V main supply available) the 3.3 V output is provided from the internal low dropout regulator at an output current of 0.4 A. When the motherboard enters sleep mode, the MC33566 operates from the 3.3 V aux supply and routes the aux current to the output via the external P–channel MOSFET bypass transistor controlled by the drive out pin. As a result, the output voltage provided to the peripheral card remains constant at 3.3 V even during host systems transitions to and from sleep mode.



1 5 Pin

Output Current up to 0.4 A Excellent Line and Load Regulation Low Dropout Voltage Prevents Reverse Current Flow During Sleep Mode Glitch–Free Transfer from Sleep Mode to Active Mode Compatible with Instantly Available PC Systems

A WL Y WW

1

Vaux Vin Gnd Vout Drv

5

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5C G #9 " 21 " 21

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1. 2. 3. 4. 5.

Note: Tab is ground

MC33566 Features:

• • • • • •

M5 661 AWLYWW

Device

Package

Shipping

MC33566D2T–1

D2PAK

50 Units/Rail

MC33566D2T–1RK

D2PAK

2500 Tape & Reel

0

11B 1;

0 0 %A1./

µB.9

"




827


MC33566 PIN ASSIGNMENTS AND FUNCTIONS Pin #

Pin Name

Pin Description

1

+3.3 Vaux

2

+5.0 Vin

3

Gnd

4

+3.3 Vout

3.3 V output provided to the application circuit (output current is sourced to this pin from the 5.0 V input.)

5

Drive out

This output drives a P–channel MOSFET with up to 2000 pF of “effective” gate capacitance. Recommended devices are the MMFT5P03HD and MTSF1P02HD. Drive out has active internal pull–up and pull–down circuitry to guarantee fast transitions.

Auxiliary input. Typical voltage 3.3 V. This is the input supply for the IC. Typical voltage 5.0 V. (Notes 1 and 2) Logic and power ground.

MAXIMUM RATINGS (TC = 25°C, unless otherwise noted) Symbol

Value

Unit

Vin

7.0

Vdc

Vin

–0.5 (Note 3)

Vdc


Ta

–5.0 to +85

°C


TJ

– 5.0 to +150

°C

Lead Temperature (Soldering, 10 seconds)

TL

300

°C

Storage Temperature

Tstg

– 55 to +150

°C

RθJA (Note 4)

65

°C/W

Rating +5.0 Vin Supply Voltage

Package Thermal Resistance

AC ELECTRICAL SPECIFICATIONS (Notes 5, 6, and 7) Symbol

Min

Typ

Max

Unit

Drive High Delay (Vin ramping up) Cdrive = 1.2 nF, measured from +5.0 Vin = VthresHi to VDrive = 2.0 V

tDH

–

0.5

3.5

µS

Drive Low Delay (Vin ramping down) Cdrive = 1.2 nF, measured from +5.0 Vin = VthresLo to VDrive = 2.0 V

tDL

–

0.5

3.5

µS

Characteristic

1. See 5.0 V Detect Thresholds Diagram. 2. Recommended source impedance for 5.0 V supply: ≤ 0.12 W. This will ensure that Io x Rsource < Vhyst, thus avoiding driveout toggling during 5.0 V detect threshold transitions. 3. Vin should not be allowed to go negative relative to ground. 4. Mounted on recommended minimum PCB pad on FR4, 2–oz. copper circuit board. 5. AC specs are guaranteed by characterization, but not production tested after characterization. 6. See Figure 3. Application Block Diagram. 7. See Timing Diagram.


MC33566 DC ELECTRICAL CHARACTERISTICS (Note 8) Symbol

Min

Typ

Max

Unit

+5.0 Vin Supply Voltage Range

+5.0 Vin

4.35

5.0

5.5

Vdc

Reverse Leakage Current from Output

Ireverse

–

–

25

µA

Vaux Quiescent Current

Iqaux

–

–

2.0

mA

+5.0 Vin Quiescent Current, Operating

Iqvin

–

–

10

mA

Load Capacitance (Note 9)

Cload

4.7

22

–

mF

3.267 3.234

3.30 3.30

3.333 3.366

Vd

3.0

–

–

Vdc

Voltage Out at Max Voltage In (Vin = 7.0 V)

Voutmax

3.1

3.3

3.5

Vdc

Line Regulation (Io = 400 mA)

Linereg

–

–

0.4

%

Load Regulation (Io = 0 to 400 mA)

Loadreg

–

–

0.8

%

Low Threshold Voltage (+5.0 Vin Falling, Io = 400 mA)

VthresLo

3.9

4.05

–

Vdc

High Threshold Voltage (+5.0 Vin Rising, Io = 400 mA)

VthresHi

–

4.2

4.35

Vdc

Vhyst

0.05

–

–

Vdc

Output Peak Source Current (+5.0 Vin > VthresHi)

Ipeak

15

–

–

mA

Output Peak Sink Current (+5.0 Vin < VthresLo)

Ipeak

15

–

–

mA

Low Output Voltage (IoL = 200 µA, Vin < VthresLo)

VoL

–

100

200

mVdc

High Output Voltage (IoH = 200 µA)

VoH

3.4

–

–

Vdc

Characteristic

REGULATOR OUTPUT +3.3 Vout

Output Voltage (4.35 V ≤ Vin ≤ 5.5 V, 0 mA ≤ Io ≤ 400 mA) TA = 25°C (TJ = –5°C to 150°C) In–to–Out Voltage (3.9 V ≤ Vin ≤ 4.35 V, Vaux = 3.3 V)

Vdc

5.0 V DETECT

Hysteresis DRIVE OUTPUT

8. –5°C < Ta < 70°C, 4.35 V < Vin < 5.5 V, Cload ≥ 4.7 µF unless otherwise noted. 9. 4.7 µF minimum over temperature; 22 µF recommended; 500 mW ESR maximum.


MC33566 0 .A

$1; L "11B

%A1./ !)BD.1/ 36-%

5C G #9 " 21 " 21

#91. L 5C11

0

11B 1;

0 0

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Figure 2. Functional Block Diagram

FUNCTIONAL DESCRIPTION Glitch–free Transfer – The design of the 5.0 V detect Input Blocking – The internal NPN pass transistor of the circuitry and drive out control circuitry guarantees that the LDO regulator ensures that no significant reverse current +3.3 Vout will not exceed the output voltage specification will flow from +3.3 Vout back to the +5.0 Vin input when the 5.0 V input is not powered and the 3.3 Vin supply is present. listed in the table of DC Operating Specifications even with +5.0 Vin ramping up and down at the extremes of the slew 5.0 Volt Detect – Internal circuitry detects the presence of rates in the table of AC Operating Specifications. the 5.0 V input supply. When the 5.0 V supply drops below Offset Voltage Performance – To ensure performance a given threshold, the +3.3 Vin bypass transistor (an external P–channel MOSFET) is enabled. The 5.0 V detect logic is when external offsets are present on the +5.0 Vin and +3.3 Vin power inputs, the device has been designed to be active throughout the entire range of ramp–up from 0 to capable of operating with either one or both of these inputs 5.5 V. Additionally, the drive out signal is never turned ON rising from or falling to zero volts, or with offsets of 0.05 V or OFF inappropriately during ramp–up of the +5.0 Vin supply. Also, +3.3 Vout never drops below 3.0 V while to 0.9 V as the inputs ramp up and down. +5.0 Vin is above the 5.0 V detect minimum threshold. .A

3D1H.+ 3. H. !# 6/

!# #. # B C

µ5 4 3 2 1 " $ & " & 8

Figure 3. Application Block Diagram


µ-

MC33566

5'5(

&

5=6

&

5'(

"$

"$

NOTE: '( 1 . ;.// 1 '7 7( H1 ≥ µ

NOTE: '( 1 . ;.// 1 '7 7( H1 ≤


B.9.B µW %6$ !D.1*3.I ° *. *'4(

B.9.B µW %6$ !D.1*3.I ° *. *'4(

"

Figure 4. 5.0 V Detect Thresholds Diagram

"5

!D.1 3.I °

!D.1 3.I °

. 4

. 4

-1K1BC '5>(

-1K1BC '5>(

NOTE: B.9.B ≥ µ- 21 91. I 191.1 .I1 3.A %6$ 91 .H/1 , W 21 91. I 191.1 .I1

Figure 6. Predicted Gain and Phase at Zero Load Current

Figure 7. Predicted Gain and Phase at Full Load Current


"##,% . 5 4 ! The MC33567 Dual Linear Power Supply Controller is designed to facilitate power management for motherboard applications where reliable regulation of high current supply planes is required. It provides the Drive, Sense and Control signals to interface two external, N–channel MOSFETs for regulating two different supply planes. Undervoltage, short circuit detection places the operation of the system into a protected mode pending removal of the short.


Features

• MC33567–1: Two, Independent Regulated Supplies

• • • •


8 1

1.515 V – Supply for GTL and AGP Planes 1.818 V – Supply for I/O Plane and Memory Termination MC33567–2: Dual 2.525 V Supplies for Clock and Memory Undervoltage Detection and Protection Mode Drive Capability for SOT–223, DPAK, and D2PAK MOSFETs Bypass Function for 3.3 V AGP Card Detection

x A L Y W

MC567x ALYW

= 1 or 2 = Assembly Location = Wafer Lot = Year = Work Week

PIN CONNECTIONS

Applications

• Motherboards • Dual Power Supplies

Gate1 drv 1 Sense1 2 Shutdown1 3 Gnd 4

8 VCC 7 Gate2 drv 6 Sense2 5 Shutdown2

Simplified Functional Block Diagram ORDERING INFORMATION +3.3 Vin

Vin Bypass On 8 +12 V

UVLO

REF

3.3 V


1 DRV1

+12 V

4 GND

66 k Startup & Undervoltage Shutdown

3 SHDN1

Control 2 SNS1

Vout1

REF +3.3 Vin

Vin Bypass On REF

3.3 V

7 DRV2

+12 V 66 k Startup & Undervoltage Shutdown

5 SHDN2

Control 6 SNS2

Vout2

REF



832


MC33567 MAXIMUM RATINGS* Symbol

Value

Unit

Supply Voltage

Rating

Vcc

12.5

Vdc


Ta

0 to +80

°C


TJ

– 5 to +125

°C


TL

300

°C


Tstg

– 55 to +150

°C

RθJA Note 1

159

°C/W

RθJC

28

°C/W

Package Thermal Resistance, Junction to Ambient Thermal Resistance, Junction to Case

1. Minimum pad test board with 5 MIL wide and 2.8 MIL thick copper traces1 inch long. *All characterizing done with MTD3055VL N–Channel MOSFETs.

DC ELECTRICAL CHARACTERISTICS Characteristic

Symbol

Min

Typ

Max

Unit

Supply Voltage

Vcc

9.0

12

12.5

V

Quiescent Current

IqL IqH

– –

6.0 7.0

9.0 10

mA

UVLO

7.0

8.5

9.0

V

Vhys

0.2

0.5

0.9

V

Drive Voltage (Gate to Ground)

Vdrv

–

–

10.5

V

Gate Drive Source Output Current (Pin 1, Pin 7)

Ipkdrv

10

20

30

mA

Gate Drive Sink Current (Steady State)

Isink

5.0

7.0

10

mA

Shutdown Threshold

SHDN

0.8

1.13

1.3

V

Shutdown Hysteresis

SHDNhys

–

130

–

mV

Shutdown Disable Time

SHDNtdis

–

0.5

2.0

ms

ISHDN

–

37

–

mA

Short Circuit Response Time

SCtd

–

250

–

ms

Short Circuit On Time

SCton

0.5

0.8

1.5

ms

Short Circuit Off Time

SCtoff

20

40

60

ms

Short Circuit/Undervoltage Detect (Load current increased until output drops)

SCuvd

70

–

80

%Vout

MC33567–1 Regulator 1 Regulator 2 MC33567–2

Vreg1 Vreg2 –

– – –

1.818 1.515 2.525

– – –

Output Voltage Regulation (Full–Load to No–Load @ 25–70°C)

Vreg%

–2.5

–

+2.5

UNDER VOLTAGE LOCKOUT Undervoltage Lockout Hysteresis

DRIVE

SHUTDOWN

Shutdown Current Threshold

SHORT CIRCUIT

OUTPUT REGULATION V


%

MC33567 VCC

+3.3 Vin

8

Vref

5 Vreg

REF

5V

Vref

UVLO Vref UVLO

Vref 75% 1 2 SNS1 3 SHDN1

Vfb

COMP HYS SHDN1

BYPASS ON

5V

A1 +

5V

1.818 V

OUT

GLITCH FILTER IN OUT Vref 5V 5V

Out

FAULT LOGIC FAULT UVLO SHDN1 Vref FAULT 5V

In1 In2 In3

OR

7 6 SNS2 5 SHDN2

COMP HYS

Vfb

SHDN2

BYPASS ON

5V

Out A2

+

5V

4

REG 1.515 V SNS2 DRV2 OFF ON

Q2 DRV2

1.515 V

To SNS2

Vref

Vref

–

To SNS1

Vref

Vref

–

*

Q1 DRV1

REG 1.818 V SNS1 DRV1 OFF ON

OUT

GLITCH FILTER IN OUT Vref 5V 5V

FAULT LOGIC FAULT UVLO SHDN2 Vref FAULT

In1 In2 In3

OR

5V

* Internal ground disables bypass on function on the 1.818 V regulator in the MC33567–1 and on the 2.525 V regulators in the MC33567–2. A1 and A2 are undervoltage comparators.


PIN ASSIGNMENTS AND FUNCTIONS PIN #

PIN NAME

1

Gate 1 drive

Drives MOSFET into linear region. Is internally clamped to ground in power down mode.

PIN DESCRIPTION

2

Sense 1 line

Returns regulated output from MOSFET.

3

Shutdown 1

At TTL high level turns off regulation for gate 1. Effectively grounds gate 1. (Internal pull–up to 3.3 V)

4

Ground

5

Shutdown 2

At TTL high level turns off regulation for gate 2. Effectively grounds gate 2. (Internal pull–up to 3.3 V)

6

Sense 2 line

Returns regulated output from MOSFET.

7

Gate 2 drive

Drives MOSFET into linear region for 1.515 V operation. Saturates external FET in bypass mode. Is internally clamped to ground in power down mode.

8

12 volt input

Supply voltage for operation and gate drive output.


MC33567 OPERATING DESCRIPTION The MC33567 Dual Linear Controller is designed for power management applications where high current, voltage regulation is needed. Some computer applications include: • 1.515 V – AGP (Advanced Graphic Port) and GTL+ (Gunning Transistor Logic – Intel’s electrical bus technology) • 1.818 V – I/O planes on motherboard • 2.525 V – Clock and memory

The way in which the external board is wired to the shutdown pin will determine the output of the MC33567. Listed are the conditions the external board is wired and the corresponding output voltages: 1. If there is no connection on the external board, there is an open and the output will be the regulated output voltage. 2. If there is a ground on the external board which will cause the SHUTDOWN pin to be less than 0.8 V, the MOSFET turns off and there is no output voltage. 3. If there is a resistor on the external board pulling the SHUTDOWN pin above 4.1 V, the output will be in the bypass mode. In this mode, the MOSFET is fully on, or fully enhanced, and the output will be whatever voltage is supplied to the input voltage of the MOSFET, Vin. 4. If the SHUTDOWN pin is between 1.3 V and 4.1 V, the output will be the regulated voltage.

Hiccup Mode

If the output drops below 75% of the regulated threshold for greater than 250 µs or a short circuit condition exists, that output will go into hiccup mode. This means that the output is turned ON for 1.0 ms and OFF for 40 ms for a duty cycle of 1:40. Please refer to Figure 2. Each transition from low to high of the input restarts the hiccup mode holdoff period. Once the short circuit is removed or the output comes back to the regulated threshold, it will operate under normal operating conditions.

Tables 1 and 2 are the logic tables for the SHUTDOWN pins. Note that the logic tables are not the same for the 1.515 V regulator and the 1.818 V regulator. The MC33567–2 does not have the Full–On Bypass feature.

1 ms 40 ms

Table 1. Logic Table for Shutdown (Pin 5) on the 1.515 V Regulator

Figure 2. Hiccup Mode Duty Cycle

SHUTDOWN Pin

1.515 V Regulator Output

No Connect

1.515 V

t0.8 V

Shutdown

1.3 VtSHDNt4.1 V

1.515 V

u4.2 V

Vin = Bypass

Shutdown

The SHUTDOWN pin is connected to the external board (AGP or GTL+). Please refer to Figure 3. 3.3 Vin AGP Card Type Detection

12 Vin

AGP Card Voltage 1.5 V / 3.3 V

Table 2. Logic Table for Shutdown (Pin 3) on the 1.818 V Regulator

3.3 Vin R7 10 k

SHUTDOWN Pin

1.818 V Regulator Output

No Connect

1.818 V

8

t0.8 V

Shutdown

2 1.8 V/1.5 V 7

u 1.3 V

1.818 V

1

3

MC33567 6

4

5

Gate 2 drv Sense2 Shutoff2

PIN 5 TRUTH TABLE Pin 5 No connect = 1.515 V LDO drive out active Pin 5 < 0.8V = shutdown (drive out 0 V) 1.3 V < pin 5 < 4.1 V = 1.515 V LDO drive out active Pin 5 > 4.2 V = 3.3 V bypass mode (drive out = Vin for FET)

Figure 3. 1.5 V/3.3 V AGP Card Detection


MC33567 Sense

PCB Layout Guidelines

The SENSE pins provide tight regulation of the load voltages with varying load currents. When the load is located at a distance, there will be a voltage drop due to the resistance loss of the trace. If the load is not near the MC33567, it is recommended that the SENSE pins be used. Connect the SENSE pins as close to the load as possible. Use a separate trace to connect the source of the N–Channel MOSFET to the load. Refer to Figure 4.

It is recommended that the MC33567 be placed as physically close as possible to the external series pass MOSFET transistors. Use short traces to minimize extraneous signals from being magnetically or electrostatically induced on the sense or drive lines. Place the sense trace and power trace in the same plane and same direction. The power trace is to be placed from the series pass transistor source lead to the load. Avoid routing the sense lead near the load current return path. Also avoid unterminated runs of the sense leads. If it is desired to have options where the sense lead is placed on the board, use 0 Ω resistor jumpers to make the alternate sense lead connection near the sense pin.

Vin

7

N–Channel MOSFET Selection 6

The ON Semiconductor MTD3055VL N–Channel MOSFET was used in the characterization of the MC33567. To select a N–Channel MOSFET the drain–source on–resistance, RDS(on), must be considered. For best results, RDS(on) needs to be low. Below is the calculation for RDS(on). The 0.5 in the equation is to prevent saturation and to account for tolerance build–up.

RL

Sense

Figure 4. Capacitor Selection

RDS(on) v 0.5

Stable operation is achieved by preserving an adequate phase margin. A rule of thumb for preserving an adequate phase margin is: C · R w 10 R w 10

Vin * Vout ILoad

Where:

10*6

Vin = 3.3 V typically Vout = 1.515 V, 1.818 V, or 2.525 V ILoad = Current at load

10*6 C

Select a N–channel MOSFET that has a RDS(on) lower than the calculated value.

Where: C = load capacitance R = equivalent series resistance (ESR) of the capacitor For example, if the load capacitor is 400 µF, then the ESR of the capacitor would need to be no less than 25 mΩ. 25 mW w 10

10*6 400 mF

This rule of thumb assumes that all capacitors across the load are the same type and value. If different types and values are used in parallel across the load, then each individual capacitor must meet the requirements of the given equation.


MC33567

Vin Vin

+ 3.3 V

C1 100 µF

Power Supply VCC

+ 12 V

DRV1 Q1

1

8

2

7

DRV2

SNS1

C2 100 µF

C3 100 µF

MC33567

SHDN1

Q2 SNS2

3

6

4

5

SNS2

SHDN2

SHDN2

C4 100 µF

SHDN1 SNS1

AGP Card

Figure 5. Application Block Diagram

Parts List Qty

Reference

Part/Description

Vendor

Notes

4

C1, C2, C3, C4

100 µF Electrolytic Capacitor

Various

1

U1

MC33567

ON Semiconductor

2

Q1, Q2

MTD3055VL

ON Semiconductor

N–Channel MOSFET

MC33567 TYPICAL CHARACTERISTICS 200

200 PHASE °

PHASE MARGIN = 48° @ 8 kHz

PHASE °


100


100

GAIN dB

GAIN dB

0

0 ILOAD = 2 A C = 200 mF Resr = 50 mW

–100

*PHASE MARGIN = 85° @ 8 kHz

ILOAD = 2 A C = 200 mF Resr = 200 mW –100

101

102

103 104 f, FREQUENCY

105

106

101

102

103 104 f, FREQUENCY

105

Figure 7. Gain–Phase Plot @ 200 mW

Figure 6. Gain–Phase Plot @ 50 mW


106

MC33567 1.515

1.83 1.828

1.514 1.513

1.824

1.512

VOLTAGE (V)

VOLTAGE (V)

1.3 A Load 1.826

1.822 1.82 1.818

5 mA Load

1.816

0

10

20

30

40

50

60

70

80

1.509

1.506 –10

90

10

20

30

40

50

60

70

80

TA,TEMPERATURE (°C)

Figure 8. Regulator 1 Load Regulation vs. Temperature Gate Drive 2 Open

Figure 9. Regulator 2 Load Regulation vs. Temperature Gate Drive 1 is Open

8

6.6

7.8

6.5

90

Quiescent Current with both SHDNs High

6.4

7.4

QUIESCENT

7.6 Regulator 1

7.2

Regulator 2

7

6.3 6.2 6.1

5.9 5.8

6.6

5.7 0

10

20

30

40

50

60

70

80

5.6 –10

90

Quiescent Current with Regulator 2 SHDN High

6

6.8

Quiescent Current with both SHDNs Low

0

10

20

30

40

50

60

70

80



Figure 10. Gate Drive Sink Current vs. Temperature

Figure 11. SHDN Quiescent Current vs. Temperature 50 mA Load

1.817

1.514

1.816

1.513

1.815 1.814 1.813 1.812 1.811 –10

0


VOLTAGE (V)

SINK CURRENT (MA) VOLTAGE (V)

1.51

1.507

1.812

6.4 –10

1.3 A Load

1.511

1.508

1.814 1.81 –10

5 mA Load

90

1.512 1.511 1.51 1.509

0

10

20

30

40

50

60

70

80

90

1.508 –10

0

10

20

30

40

50

60

70

80



Figure 12. Regulator 1 Line Regulation vs. Temperature 50 mA Load (3.0 V to 3.6 V)

Figure 13. Regulator 2 Line Regulation vs. Temperature 50 mA Load (3.0 V to 3.6 V)


90

MC33567 8.6

570

8.5

560 550 VOLTAGE (V)

VOLTAGE (V)

8.4 8.3 8.2 8.1

540 530 520 510 500 490

8

480

7.9 –10

0

10

20

30

40

50

60

70

80

470 –10

90

10

20

30

40

50

60

70

80


Figure 14. Under Voltage Lock Out Threshold vs. Temperature

Figure 15. Under Voltage Hysteresis vs. Temperature

10.8

42.5

10.75

42

10.7

90

41.5 TIME (ms)

Series 1

10.65 10.6 10.55

41 40.5

Regulator 1

40

10.5

Regulator 2 39.5

10.45 10.4 –10

0

10

20

30

40

50

60

70

80

39 –10

90

0

10

20

30

40

50

60

70

80



Figure 16. Regulator 2 Maximum Gate Voltage with SHDN = 4.2 V vs. Temperature VCC = 12 V

Figure 17. Hiccup Off Time Temperature

0.9 0.88

TIME (ms)

VOLTAGE (V)

0


0.86 Regulator 2

0.84 Regulator 1

0.82 0.8 0.78 –10

0

10

20

30

40

50

60

70

80


Figure 18. Hiccup On Time vs. Temperature


90

90

MC33567 ORDERING INFORMATION Output Voltage (Vout1)

Regulated/Bypass (Vout2)

Package

Shipping

MC33567D–1

1.8 V

1.5 V/3.3 V

SO–8

98 Units/Rail

MC33567D–1R2

1.8 V

1.5 V/3.3 V

SO–8

2500 Tape & Reel

MC33567D–2

2.5 V

2.5 V

SO–8

98 Units/Rail

MC33567D–2R2

2.5 V

2.5 V

SO–8

2500 Tape & Reel

Device


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The MC34160 Series is a voltage regulator and supervisory circuit containing many of the necessary monitoring functions required in microprocessor based systems. It is specifically designed for appliance and industrial applications, offering the designer a cost effective solution with minimal external components. These integrated circuits feature a 5.0 V/100 mA regulator with short circuit current limiting, pinned out 2.6 V bandgap reference, low voltage reset comparator, power warning comparator with programmable hysteresis, and an uncommitted comparator ideally suited for microprocessor line synchronization. Additional features include a chip disable input for low standby current, and internal thermal shutdown for over temperature protection. These devices are contained in a 16 pin dual–in–line heat tab plastic package for improved thermal conduction. • 5.0 V Regulator Output Current in Excess of 100 mA • Internal Short Circuit Current Limiting • Pinned Out 2.6 V Reference • Low Voltage Reset Comparator • Power Warning Comparator with Programmable Hysteresis • Uncommitted Comparator • Low Standby Current • Internal Thermal Shutdown Protection • Heat Tab Power Package Representative Block Diagram

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P SUFFIX PLASTIC PACKAGE CASE 648C (DIP–16)

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MICROPROCESSOR VOLTAGE REGULATOR/ SUPERVISORY CIRCUIT

MC34160P

Operating Temperature Range TA = 0° to +70°C

MC33160DW MC33160P

Package SOP–16L DIP–16 SOP–16L

TA = – 40° to +85°C

DIP–16

1 1 !1 .



841


MC34160 MC33160 MAXIMUM RATINGS Rating

Symbol

Value

Unit


VCC

40

V

Chip Disable Input Voltage (Pin 15, Note 1)

VCD

–0.3 to VCC

V

Comparator Input Current (Pins 1, 2, 9)

Iin

–2.0 to +2.0

mA

Comparator Output Voltage (Pins 6, 7, 8)

VO

40

V

ISink

10

mA

Comparator Output Sink Current (Pins 6, 7, 8)

°C/W

Power Dissipation and Thermal Characteristics P Suffix, Dual–In–Line Case 648C Thermal Resistance, Junction–to–Air Thermal Resistance, Junction–to–Case (Pins 4, 5, 12, 13) DW Suffix, Surface Mount Case 751G Thermal Resistance, Junction–to–Air Thermal Resistance, Junction–to–Case (Pins 4, 5, 12, 13)

RθJA RθJC

80 15

RθJA RθJC

94 18


TJ

+150

Operating Ambient Temperature MC34160 MC33160

TA


Tstg

°C °C

0 to +70 –40 to +85 –65 to +150

°C

ELECTRICAL CHARACTERISTICS (VCC = 30 V, IO = 10 mA, Iref = 100 µA) For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Notes 2 and 3], unless otherwise noted.) Characteristics

Symbol

Min

Typ

Max

Unit

VO

4.75

5.0

5.25

V

Line Regulation (VCC = 7.0 V to 40 V, TA = 25°C)

Regline

–

5.0

40

mV

Load Regulation (IO = 1.0 V to 100 mA, TA = 25°C)

Regload

–

20

50

mV

RR

50

6.5

–

dB

Vref

2.47

2.6

2.73

V

Line Regulation (VCC = 5.0 V to 40 V, TA = 25°C)

Regline

–

2.0

20

mV

Load Regulation (IO = 0.1 mA to 2.0 mA, TA = 25°C)

Regload

–

4.0

30

mV

Threshold Voltage High State Output (Pin 11 Increasing) Low State Output (Pin 11 Decreasing) Hysteresis

VIH VIL VH

– 4.55 0.02

(VO–0.11) (VO–0.18) 0.07

(VO–0.05) – –

Output Sink Saturation (VCC = 4.5 V, ISink = 2.0 mA)

VOL

–

–

0.4

V

Output Off–State Leakage (VOH = 40 V)

IOH

–

–

4.0

µA

REGULATOR SECTION Total Output Variation (VCC = 7.0 V to 40 V, IO = 1.0 mA to 100 mA, TA = Tlow to Thigh)

Ripple Rejection (VCC = 25 V to 35 V, IO = 40 mA, f = 120 Hz, TA = 25°C) REFERENCE SECTION Total Output Variation (VCC = 7.0 to 40 V, IO = 0.1 mA to 2.0 mA, TA = Tlow to Thigh)

RESET COMPARATOR V

NOTES: 1. The maximum voltage range is –0.3 V to VCC or +35 V, whichever is less. 2. Tlow = 0°C for MC34160 Thigh = 70°C for MC34160 –40°C for MC33160 85°C for MC33160 3. Low duty cycle pulse testing techniques are used during test to maintain junction temperature as close to ambient as possible.


MC34160 MC33160 ELECTRICAL CHARACTERISTICS (continued) (VCC = 30 V, IO = 10 mA, Iref = 100 µA) For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Notes 2 and 3], unless otherwise noted.) Characteristics

Symbol

Min

Typ

Max

Unit

Input Offset Voltage

VIO

–

Input Bias Current (VPin 9 = 3.0 V)

IIB

–

1.2

10

mV

–

0.5

µA

Input Hysteresis Current (VPin 9 = Vref – 100 mV) RPin 10 = 24 k RPin 10 = ∞

IH 40 4.5

50 7.5

60 11

POWER WARNING COMPARATOR

µA

Output Sink Saturation (ISink = 2.0 mA)

VOL

–

0.13

0.4

V


IOH

–

–

4.0

µA

VIO

–

–

20

mV

Input Hysteresis Voltage (Output Transition High to Low)

IH

140

200

260

mV

Input Bias Current (VPin 1, 2 = 2.6 V)

IIB

–

–

–1.0

µA

Input Common Mode Voltage Range

VICR

0.6 to 5.0

–

–

V

Output Sink Saturation (ISink = 2.0 mA)

VOL

–

0.13

0.4

V


IOH

–

–

4.0

µA

Chip Disable Threshold Voltage (Pin 15) High State (Chip Disabled) Low State (Chip Enabled)

VIH VIL

2.5 –

– –

– 0.8

Chip Disable Input Current (Pin 15) High State (Vin = 2.5 V) Low State (Vin = 0.8 V)

IIH IIL

– –

– –

100 30

Chip Disable Input Resistance (Pin 15)

Rin

50

100

–

Operating Voltage Range VO (Pin 11) Regulated Vref (Pin 16) Regulated

VCC 7.0 to 40 5.0 to 40

– –

– –

Power Supply Current Standby (Chip Disable High State) Operating (Chip Disable Low State)

ICC – –

0.18 1.5

0.35 3.0

UNCOMMITTED COMPARATOR Input Offset Voltage (Output Transition Low to High)

TOTAL DEVICE V

µA

kΩ V

mA

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Figure 2. Reference and Regulator Output versus Supply Voltage


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Figure 9. DW Suffix (SOP–16L) Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length

PIN FUNCTION DESCRIPTION Pin

Function

Description

1

Comparator Inverting Input

This is the Uncommitted Comparator Inverting input. It is typically connected to a resistor divider to monitor a voltage.

2

Comparator Noninverting Input

This is the Uncommitted Comparator Noninverting input. It is typically connected to a reference voltage.

3

N.C.

No connection. This pin is not internally connected.

4, 5, 12, 13

Gnd

These pins are the control circuit grounds and are connected to the source and load ground returns. They are part of the IC lead frame and can be used for heatsinking.

6

Comparator Output

This is the Uncommitted Comparator output. It is an open collector sink–only output requiring a pull–up resistor.

7

Reset

This is the Reset Comparator output. It is an open collector sink–only output requiring a pull–up resistor.

8

Power Warning

This is the Power Warning Comparator output. It is an open collector sink–only output requiring a pull–up resistor.

9

Power Sense

This is the Power Warning Comparator noninverting input. It is typically connected to a resistor divider to monitor the input power source voltage.

10

Hysteresis Adjust

The Power Warning Comparator hysteresis is programmed by a resistor connected from this pin to ground.

11

Regulator Output

This is the 5.0 V Regulator output.

14

VCC

This pin is the positive supply input of the control IC.

15

Chip Disable

This input is used to switch the IC into a standby mode turning off all outputs.

16

Vref

This is the 2.6 V Reference output. It is intended to be used in conjunction with the Power Warning and Uncommitted comparators.


MC34160 MC33160 OPERATING DESCRIPTION information to the microprocessor, preventing system malfunctions. The Reset Comparator Inverting Input is internally connected to the 2.6 V reference while the Noninverting Input monitors VO. The Reset Output is active low when VO falls approximately 180 mV below its regulated voltage. To prevent erratic operation when crossing the comparator threshold, 70 mV of hysteresis is provided. The Power Warning Comparator is typically used to detect an impending loss of system power. The Inverting Input is internally connected to the reference, fixing the threshold at 2.6 V. The input power source Vin is monitored by the Noninverting Input through the R1/R2 divider (Figure 10). This input features an adjustable 10 µA to 50 µA current sink IH that is programmed by the value selected for resistor RH. A default current of 6.5 µA is provided if RH is omitted. When the comparator input falls below 2.6 V, the current sink is activated. This produces hysteresis if Vin is monitored through a series resistor (R1). The comparator thresholds are defined as follows:

The MC34160 series is a monolithic voltage regulator and supervisory circuit containing many of the necessary monitoring functions required in microprocessor based systems. It is specifically designed for appliance and industrial applications, offering the designer a cost effective solution with minimal external components. These devices are specified for operation over an input voltage of 7.0 V to 40 V, and with a junction temperature of –40° to +150°C. A typical microprocessor application is shown in Figure 10. Regulator

The 5.0 V regulator is designed to source in excess of 100 mA output current and is short circuit protected. The output has a guaranteed tolerance of ±5.0% over line, load, and temperature. Internal thermal shutdown circuitry is included to limit the maximum junction temperature to a safe level. When activated, typically at 170°C, the regulator output turns off. In specific situations a combination of input and output bypass capacitors may be required for regulator stability. If the regulator is located an appreciable distance (≥ 4″) from the supply filter, an input bypass capacitor (Cin) of 0.33 µF or greater is suggested. Output capacitance values of less than 5.0 nF may cause regulator instability at light load (≤ 1.0 mA) and cold temperature. An output bypass capacitor of 0.1 µF or greater is recommended to ensure stability under all load conditions. The capacitors selected must provide good high frequency characteristics. Good construction techniques should be used to minimize ground loops and lead resistance drops since the regulator does not have external sense inputs.

Vth(lower) = Vref Vth(upper) = Vref

R1 R2 R1 1+ R2

1+

– IIB R1 + IH R1

The nominal hysteresis current IH equals 1.2 V/RH (Figure 4). The Uncommitted Comparator can be used to synchronize the microprocessor with the ac line signal for timing functions, or for synchronous load switching. It can also be connected as a line loss detector as shown in Figure 11. The comparator contains 200 mV of hysteresis preventing erratic output behavior when crossing the input threshold. The Power Warning and Uncommitted Comparators each have a transistor base–emitter connected across their inputs. The base input normally connects to a voltage reference while the emitter input connects to the voltage to be monitored. The transistor limits the negative excursion on the emitter input to – 0.7 V below the base input by supply current from VCC. This clamp current will prevent forward biasing the IC substrate. Zener diodes are connected to the comparator inputs to enhance the ICs electrostatic discharge capability. Resistors R1 and Rin must limit the input current to a maximum of ±2.0 mA. Each comparator output consists of an open collector NPN transistor capable of sinking 2.0 mA with a saturation voltage less than 0.4 V, and standing off 40 V with minimal leakage. Internal bias for the Reset and Power Warning Comparators is derived from either VCC or the regulator output to ensure functionality when either is below nominal.

Reference

The 2.6 V bandgap reference is short circuit protected and has a guaranteed output tolerance of ±5.0% over line, load, and temperature. It is intended to be used in conjunction with the Power Warning and Uncommitted comparator. The reference can source in excess of 2.0 mA and sink a maximum of 10 µA. For additional current sinking capability, an external load resistor to ground must be used. Reference biasing is internally derived from either VCC or VO, allowing proper operation if either drops below nominal. Chip Disable

This input is used to switch the IC into a standby mode. When activated, internal biasing for the entire die is removed causing all outputs to turn off. This reduces the power supply current (ICC) to less than 0.3 mA. Comparators

Three separate comparators are incorporated for voltage monitoring. Their outputs can provide diagnostic


MC34160 MC33160 Heat Tab Package

medium as a heat dissipator by soldering these tabs to an adequate area of copper foil. This permits the use of standard board layout and mounting practices while having the ability to more than halve the junction to air thermal resistance. The example and graph are for a symmetrical layout on a single sided board with one ounce per square foot copper.

The MC34160 is contained in a 16 lead plastic dual–in–line package in which the die is mounted on a special Heat Tab copper alloy lead frame. This tab consists of the four center ground pins that are specifically designed to improve thermal conduction from the die to the surrounding air. The pictorial in Figure 8 shows a simple but effective method of utilizing the printed circuit board

2

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1 1 !1 .

2 3

Figure 10. Typical Microprocessor Application


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Figure 12. Time Delayed Microprocessor Reset


! The CS8271 is an adjustable micropower voltage regulator with very low quiescent current (60 µA typical at 100 µA load). The output supplies 100 mA of load current with a maximum dropout voltage of only 600 mV. Control logic includes ENABLE. The combination of low quiescent current, outstanding regulator performance and control logic makes the CS8271 ideal for any battery operated equipment. The logic level ENABLE compatible pin allows the user to put the regulator into a shutdown mode where it draws only 50 µA of quiescent current. The regulator is protected against reverse battery, short circuit, over voltage, and over temperature conditions. The device can withstand 60 V load dump transients making it suitable for use in automotive environments. The CS8271 is pin compatible with the National Semiconductor LM2931.

http://onsemi.com SO–8 D SUFFIX CASE 751

8 1

DIP–8 N SUFFIX CASE 626

8 1


Features Low Quiescent Current Adjustable Output: 5.0 V to 12 V ENABLE for Sleep Mode Control 100 mA Output Current Capability Fault Protection – +60 V Load Dump – –15 V Reverse Voltage Short Circuit – Thermal Shutdown • Low Reverse Current (Output to Input)

SO–8

• • • • •

VOUT

1

8

ENABLE

Adj 1

DIP–8

VOUT NC Adj A WL, L YY, Y WW, W

8 VIN

CS8271 AWL YYWW

GND

VIN NC NC

8271 ALYW

GND NC

NC NC ENABLE



Package

Shipping

CS8271YD8

SO–8

95 Units/Rail

CS8271YDR8

SO–8

2500 Tape & Reel

CS8271YN8

DIP–8

50 Units/Rail

*Consult your local sales representative for other package options.



849


CS8271 VOUT VIN Current Source (Circuit Bias)


ENABLE Input Current Limit Sense

Adj +

–

Error Amplifier

Thermal Shutdown

Bandgap Reference

GND

Figure 1. Block Diagram MAXIMUM RATINGS* Rating

Value

Unit

Internally Limited

–

–50, 60

V

Reverse Battery

–15

V

Output Current

Internally Limited

–

2.0

kV


–40 to +150

°C

Storage Temperature

–55 to +150

°C

260 peak 230 peak

°C °C

Adj, ENABLE

–0.3, 10

V

VOUT

–0.3, 20

V

Power Dissipation Peak Transient Voltage (46 V Load Dump @ VIN = 14 V)






CS8271 ELECTRICAL CHARACTERISTICS (VOUT + 1.0 V ≤ VIN ≤ 30 V, 5.0 V ≤ VOUT ≤ 12 V, IOUT = 10 mA, –40°C ≤ TA ≤ 125°C, –40°C ≤ TJ ≤ 150°C, VENABLE = 0 V; unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit

Output Voltage Dropout Voltage

IOUT = 100 µA, VDROP = (VIN – VOUT) IOUT = 100 mA, VDROP = (VIN – VOUT)

– –

100 400

150 600

mV mV

Load Regulation

Measure VOUT when IOUT = 100 µA, 100 mA. LDREG = ABS (∆VOUT)

–

0.1

1.0

%VOUT

Line Regulation

IOUT = 1.0 mA. Measure VOUT when VIN = VOUT + 1.0 V, 30 V, LNREG = ABS (∆VOUT)

–

0.1

0.5

%VOUT


VIN = 6.0 V, IOUT = 100 µA, VOUT setup for 5.0 V, IQ = IVIN – IOUT VIN = 13 V, IOUT = 100 µA, VOUT setup for 12 V, IQ = IVIN – 100 µA VIN = 30 V, IOUT = 100 µA, VOUT setup for 5.0 V. IQ = IVIN – 100 µA VIN = 30 V, IOUT = 100 µA, VOUT setup for 12 V. IQ = IVIN – 100 µA IOUT = 50 mA, IQ = IVIN – 50 mA IOUT = 100 mA, IQ = IVIN – 100 mA

–

55

120

µA

–

130

200

µA

–

150

450

µA

–

20

500

µA

– –

4.0 12

7.0 21

mA mA


VIN = 6.0 V, ENABLE = 2.5 V, IQSLEEP = IVIN VIN = 30 V, ENABLE = 2.5 V, IQSLEEP = IVIN

– –

20 75

50 350

µA µA

Ripple Rejection

f = 120 Hz, Note 3

60

75

–

dB

Current Limit

VOUT = VOUT – 500 mV, ILIM = IVOUT

105

200

300

mA

Short Circuit Output Current

VOUT = 0 V, ISHRT = IVOUT

15

100

215

mA

Thermal Limit

Note 3

150

180

210

°C


Adjust VIN from 28 V to 40 V until VOUT ≤ 1.0 V

30

34

38

V

Reverse Current

VIN = 0 V, IREV = IVOUT, VOUT = 13.2 V

–

100

200

µA

1.15

2.0

2.6

V

– –

10 35

20 50

µA µA

ENABLE Enable Threshold

–

Enable Input Current

VENABLE = 2.6 V VENABLE = 5.0 V

Adjustment Pin

R1: Feedback resistor between VOUT and Adjust, R2: Adjust resistor to ground.

Reference Voltage

100 µA ≤ IOUT ≤ 100 mA


IADJ = (VREF/R2) – ((VOUT – VREF)/R1)

1.246

1.272

1.297

V

–

20

500

nA

3. Guaranteed by design, not 100% tested in production.

PACKAGE LEAD DESCRIPTION PACKAGE LEAD # SO–8

DIP–8

LEAD SYMBOL

1

1

VOUT

100 mA output; adjustable from 5.0 V to 12 V.

2

2

GND

Ground.

3, 6, 7

3, 6, 7

NC

No connection.

4

4

Adj

Resistor divider from VOUT to Adj, sets output voltage.

5

5

ENABLE

8

8

VIN

FUNCTION

Logic level switch, when High, regulator is in sleep mode. Input voltage.


CS8271 CIRCUIT DESCRIPTION OUTPUT VOLTAGE ADJUSTMENT

Short circuit protection limits the amount of current the output transistor can supply. In the case of a CS8271 under a short circuit condition, the output transistor current is limited to 100 mA. Should the junction temperature of the power device exceed 180°C (typ) the power transistor is turned off. Thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the IC.

The output voltage of the CS8271 is adjustable to any value between 5.0 V and the maximum input voltage minus the dropout voltage. To adjust the output voltage, a pair of external resistors R1 and R2 are connected as shown in Figure 2. The equation for the output voltage is VOUT + VREF


R1

where VREF is the typical reference voltage and IAdj is the adjust pin bias current. This is usually 500 nA maximum.

> 30 V VIN

VOUT

VOUT

VOUT

CS8271 R1 IOUT Adj

VREF Load Dump

R2

Short Circuit

Thermal Shutdown


Figure 2. Output Voltage Adjustment

ENABLE

OUTPUT STAGE PROTECTION

The ENABLE function switches the output transistor. When the voltage on the ENABLE pin exceeds 2.0 V typ, the output pass transistor turns off, leaving a high impedance facing the load. The IC will remain in Sleep mode, drawing only 20 µA (typ), until the voltage on this input drops below the ENABLE threshold.

The output stage is protected against overvoltage, short circuit and thermal runaway conditions (Figure 3). If the input voltage rises above 30 V (e.g. load dump), the output shuts down. This response protects the internal circuitry and enables the IC to survive unexpected voltage transients up to 60 V in magnitude.


CS8271 APPLICATION NOTES SELECTING THE RIGHT CAPACITOR VALUE

Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. (A smaller capacitor will usually cost less and occupy less board space.) If the capacitor oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real work environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations.

The output compensation capacitor COUT, determines three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The selection of a capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR, can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provide this information. The value for the output compensation capacitor COUT shown in Figure 4 should work for most applications, but it is not necessarily the least expensive or the optimal solution. VIN

VOUT

CIN 0.1 µF

CS8271 Adj ENABLE

COUT 10 µF

RRST

RL

CAdj (optional)

Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ± 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. Capacitance on the Adjust pin combined with the feedback resistors R1 and R2 can affect loop stability and should also be considered. The CS8271 internal circuitry produces about 5.0 pF to Ground on the Adjust pin. This capacitance, plus any additional external capacitance on the Adjust pin will create a pole when combined with the resistive feedback network. The effect can be significant when using large values for the feedback resistors to minimize quiescent current. A capacitor connected from the Adjust pin to Ground provides additional means to compensate the regulator by creating a pole. Alternately, a capacitor can be connected from the Adjust pin to VOUT to create a zero.

Figure 4. Test and Application Circuit Showing An Output Compensation Capacitor

To determine an acceptable value for COUT for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. (Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible). Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions.



RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.


(1)


150°C * TA PD

IIN

IOUT

VIN

VOUT

SMART REGULATOR Control Features

IQ

(2)


The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with

VIN

VOUT

VOUT R1

CS8271 C1 * 0.1 µF

ENABLE

Adj

C2** 10 µF

VREF

GND R2

C1* Required if regulator is away from power supply filter. C2** Required for output stability.

VOUT + VREF


Figure 6. Application Diagram PACKAGE THERMAL DATA Parameter

SO–8

DIP–8

Unit

RΘJC

Typical

45

52

°C/W

RΘJA

Typical

165

100

°C/W


R1

"

## $ % & ' ( The CS8183 is a dual low dropout tracking regulator designed to provide adjustable buffered output voltages that closely track (±10 mV) the reference inputs. The outputs deliver up to 200 mA while being able to be configured higher, lower or equal to the reference voltages. The outputs have been designed to operate over a wide range (2.8 V to 45 V) while still maintaining excellent DC characteristics. The CS8183 is protected from reverse battery, short circuit and thermal runaway conditions. The device also can withstand 45 V load dump transients and –50 V reverse polarity input voltage transients. This makes it suitable for use in automotive environments. The VREF/ENABLE leads serve two purposes. They are used to provide the input voltage as a reference for the output and they also can be pulled low to place the device in sleep mode where it nominally draws less than 30 µA from the supply.

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20 1 SO–20L DWF SUFFIX CASE 751D

PIN CONNECTIONS AND MARKING DIAGRAM 1 VIN VOUT1 NC NC GND GND NC NC VADJ1 VREF/ENABLE1 A WL, L YY, Y WW, W

CS8183 AWLYYWW

Features • Two Regulated Outputs 200 mA, ±10 mV Track Worst Case • Low Dropout (0.35 V typ. @ 200 mA) • Low Quiescent Current • Independent Thermal Shutdown • Short Circuit Protection • Wide Operating Range • Internally Fused Leads in the SO–20L Package

20 VOUT2 VIN2 NC NC GND GND NC NC VREF/ENABLE2 VADJ2





855

Package

Shipping

CS8183YDWF20

SO–20L

37 Units/Rail

CS8183YDWFR20

SO–20L

1000 Tape & Reel


CS8183

VIN1

VOUT1 ESD Current Limit & VSAT Sense Adj1

– ESD

ENABLE

+

VREF/ENABLE1 ESD + GND

Independent Thermal Shutdown

– 2.0 V

VIN2

VOUT2 ESD Current Limit & VSAT Sense Adj2

– ESD

ENABLE

+

VREF/ENABLE2 ESD +

Independent Thermal Shutdown

– 2.0 V


MAXIMUM RATINGS* Rating

Value

Unit

–65 to 150

°C

Supply Voltage Range (continuous)

15 to 45

V

Supply Voltage Range (normal, continuous)

3.4 to 45

V

45

V

–10 to 45

V


150

°C


18 73

°C/W °C/W

ESD Capability (Human Body Model)

2.0

kV

230 peak

°C

Storage Temperature

Peak Transient Voltage (VIN = 14 V, Load Dump Transient = 31 V) Voltage Range (Adj, VREF/ENABLE, VOUT)





CS8183 ELECTRICAL CHARACTERISTICS (VIN = 14 V; VREF/ENABLE > 2.75 V; –40°C ≤ TJ ≤ +125°C; COUT ≥ 10 µF; 0.1 Ω < COUT – ESR < 1.0 Ω @ 10 kHz; unless otherwise stated.)

Test Conditions

Parameter

Min

Typ

Max

Unit

–10

–

10

mV

Regular Output 1, 2 VREF – VOUT VOUT Tracking Error

4.5 V ≤ VIN ≤ 26 V, 100 µA ≤ IOUT ≤ 200 mA, Note 2


IOUT = 100 µA IOUT = 200 mA

– –

100 350

150 600

mV mV

Line Regulation

4.5 V ≤ VIN ≤ 26 V, Note 2

–

–

10

mV

Load Regulation

100 µA ≤ IOUT ≤ 200 mA, Note 2

–

–

10

mV

Adj Lead Current

Loop in Regulation

–

0.2

1.0

µA

Current Limit

VIN = 14 V, VREF = 5.0 V, VOUT = 90% of VREF, Note 2

225

–

700

mA

Quiescent Current (IIN – IOUT)

VIN = 12 V, IOUT = 200 mA VIN = 12 V, IOUT = 100 µA VIN = 12 V, VREF/ENABLE = 0 V

– – –

15 75 30

25 150 55

mA µA µA

Reverse Current

VOUT = 5.0 V, VIN = 0 V

–

0.2

1.5

mA

Ripple Rejection

f = 120 Hz, IOUT = 200 mA, 4.5 V ≤ VIN ≤ 26 V

60

–

–

dB

–

150

180

210

°C

–

0.80

2.00

2.75

V

–

0.2

1.0

µA

Thermal Shutdown VREF/ENABLE 1, 2 Enable Voltage Input Bias Current

VREF/ENABLE 1, 2 > 2.0 V

2. VOUT connected to Adj lead.

PACKAGE PIN DESCRIPTION Package Lead Number SO–20L

Lead Symbol

1

VIN1

2

VOUT1

3, 4, 7, 8, 13, 14, 17, 18

NC

5, 6, 15, 16

GND

Ground (4 leads fused)

9

VADJ1

Adjust lead for VOUT1.

10

VREF/ENABLE1

11

VADJ2

12

VREF/ENABLE2

19

VIN2

20

VOUT2

Function Input voltage for VOUT1. Regulated output voltage 1. No connection.

Reference voltage and ENABLE input for VOUT1. Adjust lead for VOUT2. Reference voltage and ENABLE input for VOUT2. Input voltage for VOUT2. Regulated output voltage 2.


CS8183 CIRCUIT DESCRIPTION ENABLE Function

The outputs are capable of supplying 200 mA to the load while configured as a similiar (Figure 2), lower (Figure 4), or higher (Figure 3) voltage as the reference lead. The Adj lead acts as the inverting terminal of the op amp and the VREF lead as the non–inverting. The device can also be configured as a high–side driver as displayed in Figure 7.

By pulling the VREF/ENABLE 1, 2 lead below 2.0 V typically, (see Figure 5 or Figure 6), the IC is disabled and enters a sleep state where the device draws less than 30 µA from supply. When the VREF/ENABLE lead is greater than 2.75 V, VOUT tracks the VREF/ENABLE lead normally. Output Voltage

Figures 2 through 7 only display one channel of the device for simplicity. The configurations shown apply for both channels. VOUT, 200 mA Loads VOUT C2** GND 10 µF

GND

GND

GND

C1* 1.0 µF

RA

VOUT, 200 mA

GND

GND

B+

VIN

C2** 10 µF

C1* 1.0 µF

VOUT

B+

VIN

GND

GND

GND

GND

VREF/ ENABLE

Adj

VREF

VREF/ ENABLE

VREF

C1* 1.0 µF R

R1 Adj

GND

Figure 3. Tracking Regulator at Higher Voltages

Figure 2. Tracking Regulator at the Same Voltage

GND

GND

C1* 1.0 µF

R VOUT + VREF(1 ) E) RA

VOUT + VREF


B+

VIN

VREF/ ENABLE

Adj

5.0 V

VREF/ ENABLE

Adj

VOUT, 200 mA Loads VOUT C2** GND 10 µF RF GND

B+

VIN

R2

VREF

from MCU

VOUT + VREF( R2 ) R1 ) R2

Figure 4. Tracking Regulator at Lower Voltages VOUT, 200 mA C2** 10 µF

VOUT

GND

GND

GND

Adj

B+

VIN

GND

VREF/ ENABLE

Figure 5. Tracking Regulator with ENABLE Circuit

200 mA

C1* 1.0 µF

VREF

VOUT

VIN

GND

GND

GND

GND

Adj

100 k from MCU

VREF/ ENABLE

VOUT + B ) * VSAT

Figure 6. Alternative ENABLE Circuit

Figure 7. High–Side Driver



B+

MCU

CS8183 APPLICATION NOTES Switched Application

VOUT2(min) is the minimum output voltage from VOUT2, IOUT1(max) is the maximum output current, for the application, IOUT2(max) is the maximum output current, for the application, IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated:

The CS8183 has been designed for use in systems where the reference voltage on the VREF/ENABLE pin is continuously on. Typically, the current into the VREF/ENABLE pin will be less than 1.0 µA when the voltage on the VIN pin (usually the ignition line) has been switched out (VIN can be at high impedance or at ground.) Reference Figure 8.

VOUT

VIN

GND

GND

GND Adj

CS8183

C2 10 µF

RJA + 150°C * TA PD

Ignition Switch

VOUT

C1 1.0 µF

The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heat sink will be required.

VBAT

GND

VREF/ ENABLE

< 1.0 µA

VREF 5.0 V

Figure 8.

IIN VIN

SMART REGULATOR

IOUT VOUT

External Capacitors

Output capacitors for the CS8183 are required for stability. Without them, the regulator outputs will oscillate. Actual size and type may vary depending upon the application load and temperature range. Capacitor effective series resistance (ESR) is also a factor in the IC stability. Worst–case is determined at the minimum ambient temperature and maximum load expected. The output capacitors can be increased in size to any desired value above the minimum. One possible purpose of this would be to maintain the output voltage during brief conditions of negative input transients that might be characteristic of a particular system. The capacitors must also be rated at all ambient temperatures expected in the system. To maintain regulator stability down to –40°C, a capacitor rated at that temperature must be used. More information on capacitor selection for SMART REGULATORs is available in the SMART REGULATOR application note, “Compensation for Linear Regulators.”

Control Features

IQ

Figure 9. Dual Output Regulator with Key Performance Parameters Labeled Heatsinks


Calculating Power Dissipation in a Dual Output Linear Regulator


The maximum power dissipation for a dual output regulator (Figure 9) is: PD(max) + {VIN(max) * VOUT1(min)} IOUT1(max) ) {VIN(max) * VOUT2(min)}IOUT2(max2) ) VIN(max)IQ

RΘJC appears in the package section of the data sheet. Like RΘJA, it is a function of package type. RΘCS and RΘSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.

where: VIN(max) is the maximum input voltage, VOUT1(min) is the minimum output voltage from VOUT1,


")" "*" +

! % The CS8363 is a precision micropower dual voltage regulator with ENABLE and RESET. The 3.3 V standby output is accurate within ±2% while supplying loads of 100 mA. Quiescent current is low, typically 140 µA with a 300 µA load. The active RESET output monitors the 3.3 V standby output and is low during power–up and regulator dropout conditions. The RESET circuit includes hysteresis and is guaranteed to operate correctly with 1.0 V on the standby output. The second output tracks the 3.3 V standby output through an external adjust lead, and can supply loads of 250 mA with a typical dropout voltage of 400 mV. The logic level lead ENABLE is used to control this tracking regulator output. Both outputs are protected against overvoltage, short circuit, reverse battery and overtemperature conditions. The robustness and low quiescent current of the CS8363 makes it not only well suited for automotive microprocessor applications, but for any battery powered microprocessor applications.

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1 7 D2PAK 7–PIN DPS SUFFIX CASE 936H

MARKING DIAGRAM

CS8363 AWLYWW

Features

• 2 Regulated Outputs – Standby Output 3.3 V ± 2%; 100 mA – Adjustable Tracking Output; 250 mA • Low Dropout Voltage • RESET for VSTBY • ENABLE for VTRK • Low Quiescent Current • Protection Features – Independent Thermal Shutdown – Short Circuit – 60 V Load Dump – Reverse Battery



Pin 1. VSTBY 2. VIN 3. VTRK 4. GND 5. Adj 6. ENABLE 7. RESET

A WL, L YY, Y WW, W

1 = Assembly Location = Wafer Lot = Year = Work Week


Package

Shipping

CS8363YDPS7

D2PAK, 7–PIN

50 Units/Rail

CS8363YDPSR7 D2PAK, 7–PIN 750 Tape & Reel *Contact your local sales representative for SO–16L package option.

860


CS8363

VSTBY 3.3 V, 100 mA, 2.0%

VIN Overvoltage Shutdown

Current Limit

Bandgap RESET BG

+

OVSD

BG

–

TSD OVSD VIN

VTRK 250 mA Current Limit Thermal Shutdown

TSD

–

Adj

+ ENABLE

VSTBY

– +

TSD OVSD BG RESET +

GND

RESET

–

Figure 1. Block Diagram. Consult Your Local Sales Representative for Positive ENABLE Option


Value

Unit

–16 to 26

V

Positive Transient Input Voltage, tr > 1.0 ms

60

V

Negative Transient Invput Voltage, T < 100 ms, 1.0 % Duty Cycle

–50

V

–0.3 to 10

V


–40 to +150

°C


–55 to +150

°C

2.0

kV

260 peak 230 peak

°C °C

Supply Voltage, VIN

Input Voltage Range (ENABLE, RESET)

ESD Susceptibility (Human Body Model) Lead Temperature Soldering




CS8363 ELECTRICAL CHARACTERISTICS (6.0 V ≤ VIN ≤ 26 V, IOUT1 = IOUT2 = 100 µA, –40°C ≤ TA ≤ +125°C; unless otherwise stated.) Test Conditions

Characteristic

Min

Typ

Max

Unit

–25

–

+25

mV

Tracking Output (VTRK) VTRK Tracking Error (VSTBY – VTRK)

6.0 V ≤ VIN ≤ 26 V, 100 µA ≤ ITRK ≤ 250 mA. Note 3

Adjust Pin Current, IAdj

Loop in Regulation

–

1.5

5.0

µA

Line Regulation

6.0 V ≤ VIN ≤ 26 V. Note 3

–

5.0

50

mV

Load Regulation

100 µA ≤ ITRK ≤ 250 mA. Note 3

–

5.0

50

mV

Dropout Voltage (VIN – VTRK)

ITRK = 100 µA. ITRK = 250 mA

– –

100 400

150 700

mV mV

Current Limit

VIN = 12 V, VTRK = 3.0 V

275

500

–

mA

Quiescent Current

VIN = 12 V, ITRK = 250 mA, No Load on VSTBY VIN = 12 V, ITRK = 500 µA, ISTBY = 100 µA

– –

25 145

50 220

mA µA

Reverse Current

VTRK = 3.3 V, VIN = 0 V

–

200

1500

µA

Ripple Rejection

f = 120 Hz, ITRK = 250 mA, 7.0 V ≤ VIN ≤ 17 V

60

70

–

dB

Output Voltage, VSTBY

4.5 V ≤ VIN ≤ 26 V, 100 µA ≤ ISTBY ≤ 100 mA.

3.234

3.3

3.366

V

Line Regulation

6.0 V ≤ VIN ≤ 26 V.

–

5.0

50

mV

Load Regulation

100 µA ≤ ISTBY ≤ 100 mA.

–

5.0

50

mV

Dropout Voltage (VIN – VSTBY)

ISTBY = 100 µA, VIN = 4.2 V ISTBY = 100 mA, VIN = 4.2 V

– –

– –

1.0 1.0

V V

Current Limit

VIN = 12 V, VSTBY = 3.0 V

125

200

–

mA


VIN = 12 V, VSTBY = 0 V

10

100

–

mA

Quiescent Current

VIN = 12 V, ISTBY = 100 mA, ITRK = 0 mA VIN = 12 V, ISTBY = 300 µA, ITRK = 0 mA

– –

10 140

20 200

mA µA

Reverse Current

VSTBY = 3.3 V, VIN = 0 V

–

100

200

µA

Ripple Rejection

f = 120 Hz, ISTBY = 100 mA, 7.0 V ≤ VIN ≤ 17 V

60

70

–

dB

–

0.8

1.2

2.0

V

–10

0

10

µA

10

50

100

mV

92.5

95

97.5

%VSTBY

–

–

25

µA

Standby Output (VSTBY)

RESET ENABLE Functions ENABLE Input Threshold ENABLE Input Bias Current

VENABLE = 0 V to 10 V

RESET Hysteresis RESET Threshold Low (VRL)

– VSTBY Decreasing, VIN > 4.5 V

RESET Leakage

–

Output Voltage, Low (VRLO)

1.0 V ≤ VSTBY ≤ VRL, RRST = 10 kΩ

–

0.1

0.4

V

Output Voltage, Low (VRPEAK)

VSTBY, Power Up, Power Down

–

0.6

1.0

V

VIN (VRST Low)

VSTBY = 3.3 V

–

4.0

4.5

V

150 150

180 165

– –

°C °C

30

34

38

V

Protection Circuitry (Both Outputs) Independent Thermal Shutdown Overvoltage Shutdown

VSTBY VTRK –

3. VTRK connected to Adj lead. VTRK can be set to higher values by using an external resistor divider.


CS8363 PACKAGE PIN DESCRIPTION PACKAGE PIN # D2PAK

PIN SYMBOL

1

VSTBY

2

VIN

3

VTRK

Tracking output voltage controlled by ENABLE delivering 250 mA.

4

GND

Reference ground connection.

5

Adj

6

ENABLE

7

RESET

FUNCTION Standby output voltage delivering 100 mA. Input voltage.

Resistor divider from VTRK to Adj. Sets the output voltage on VTRK. If tied to VTRK, VTRK will track VSTBY. Provides on/off control of the tracking output, active LOW. CMOS compatible output lead that goes low whenever VSTBY falls out of regulation.

CIRCUIT DESCRIPTION ENABLE Function

VTRK Output Voltage

The ENABLE function switches the output transistor for VTRK on and off. When the ENABLE lead voltage exceeds 1.4 V (typ), VTRK turns off. This input has several hundred millivolts of hysteresis to prevent spurious output activity during power–up or power–down.

This output uses the same type of output device as VSTBY, but is rated for 250 mA. The output is configured as a tracking regulator of the standby output. By using the standby output as a voltage reference, giving the user an external programming lead (Adj lead), output voltages from 3.3 V to 20 V are easily realized. The programming is done with a simple resistor divider, and following the formula:

RESET Function

The RESET is an open collector NPN transistor, controlled by a low voltage detection circuit sensing the VSTBY (3.3 V) output voltage. This circuit guarantees the RESET output stays below 1.0 V (0.1 V typ) when VSTBY is as low as 1.0 V to ensure reliable operation of microprocessor–based systems.

VTRK + VSTBY

(1 ) R1ńR2) ) IAdj

If another 3.3 V output is needed, simply connect the Adj lead to the VTRK output lead.

3.3 V, 100 mA B+

C1* 0.1 µF

VSTBY

VIN CS8363

C2** 10 µF ESR < 8.0 Ω

R3

RESET

VDD MCU RESET I/O

ENABLE R2 Adj R1 GND

R1

SW 5.0 V, 250 mA C3** 10 µF ESR < 8.0 Ω

VTRK

VTRK ∼ VSTBY(1 + R1/R2) For VTRK ∼ 5.0 V, R1/R2 ∼ 0.5 *C1 is required if regulator is located far from power supply filter. **C2 and C3 are required for stability.

Figure 2. Test and Application Circuit, 3.3 V, 5.0 V Regulator


GND

CS8363 3.3 V, 100 mA B+

C1* 0.1 µF

VSTBY

VIN CS8363

VDD

C2** 10 µF ESR < 8.0 Ω

R3

RESET

MCU RESET I/O

ENABLE Adj

GND

SW 3.3 V, 250 mA C3** 10 µF ESR < 8.0 Ω

VTRK

GND

*C1 is required if regulator is located far from power supply filter. **C2 and C3 are required for stability.

Figure 3. Test and Application Circuit, Dual 3.3 V Regulator

APPLICATION NOTES External Capacitors

IOUT2(max) is the maximum output current, for the application, and IQ is the quiescent current the regulator consumes at both IOUT1(max) and IOUT2(max). Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated:

Output capacitors for the CS8363 are required for stability. Without them, the regulator outputs will oscillate. Actual size and type may vary depending upon the application load and temperature range. Capacitor effective series resistance (ESR) is also a factor in the IC stability. Worst–case is determined at the minimum ambient temperature and maximum load expected. Output capacitors can be increased in size to any desired value above the minimum. One possible purpose of this would be to maintain the output voltages during brief conditions of negative input transients that might be characteristic of a particular system. Capacitors must also be rated at all ambient temperatures expected in the system. To maintain regulator stability down to –40°C, capacitors rated at that temperature must be used. More information on capacitor selection for SMART REGULATORs is available in the SMART REGULATOR application note, “Compensation for Linear Regulators,” document number SR003AN/D, available through the Literature Distribution Center or via our website at http://www.onsemi.com.

RJA +

150°C * TA PD

(2)

The value of RΘJA can be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IIN VIN

SMART REGULATOR

Control Features


The maximum power dissipation for a dual output regulator (Figure 4) is

IOUT1 VOUT1

IOUT2 VOUT2

IQ

PD(max) + ǊVIN(max) * VOUT1(min)ǋIOUT1(max) ) ǊVIN(max) * VOUT2(min)ǋIOUT2(max) ) VIN(max)IQ (1)

Figure 4. Dual Output Regulator With Key Performance Parameters Labeled.

where: VIN(max) is the maximum input voltage, VOUT1(min) is the minimum output voltage from VOUT1, VOUT2(min) is the minimum output voltage from VOUT2, IOUT1(max) is the maximum output current, for the application,

Heat Sinks

A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air.


CS8363 RΘCS = the case–to–heatsink thermal resistance, and RΘSA = the heatsink–to–ambient thermal resistance.

Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RΘJA: RJA + RJC ) RCS ) RSA


(3)

where: RΘJC = the junction–to–case thermal resistance, PACKAGE THERMAL DATA Parameter

D2PAK, 7–Pin

Unit

RΘJC

Typical

3.5

°C/W

RΘJA

Typical

10–50*

°C/W



") ,*# +

! %


16 1


1 7

PIN CONNECTIONS AND MARKING DIAGRAM 1 VIN NC VTRK GND GND Adj NC ENABLE

CS8361

Features

• 2 Regulated Outputs – Standby Output 5.0 V ± 2%; 100 mA – Tracking Output 5.0 V; 250 mA • Low Dropout Voltage (0.4 V at Rated Current) • RESET Option • ENABLE Option • Low Quiescent Current • Protection Features – Independent Thermal Shutdown – Short Circuit – 60 V Load Dump – Reverse Battery • Internally Fused Leads in SO–16L Package

http://onsemi.com

AWLYYWW

The CS8361 is a precision micropower dual voltage regulator with ENABLE and RESET. The 5.0 V standby output is accurate within ±2% while supplying loads of 100mA and has a typical dropout voltage of 400 mV. Quiescent current is low, typically 140 µA with a 300 µA load. The active RESET output monitors the 5.0 V standby output and is low during power–up and regulator dropout conditions. The RESET circuit includes hysteresis and is guaranteed to operate correctly with 1.0 V on the standby output. The second output tracks the 5.0 V standby output through an external adjust lead, and can supply loads of 250 mA with a typical dropout voltage of 400 mV. The logic level ENABLE lead is used to control this tracking regulator output. Both outputs are protected against overvoltage, short circuit, reverse battery and overtemperature conditions. The robustness and low quiescent current of the CS8361 makes it not only well suited for automotive microprocessor applications, but for any battery powered microprocessor applications.

16 VSTBY NC NC GND GND NC NC RESET

SO–16L

CS8361 AWLYWW


Pin 1. VSTBY 2. VIN 3. VTRK 4. GND 5. Adj 6. ENABLE 7. RESET D2PAK



Package

Shipping

CS8361YDPS7

D2PAK†

50 Units/Rail

CS8361YDPSR7

D2PAK†

750 Tape & Reel

CS8361YDWF16

SO–16L

46 Units/Rail

CS8361YDWFR16

SO–16L

1000 Tape & Reel

*Contact your local sales representative for other package options including PSOP–20, TO–220 Seven Lead, DIP–16, and SO–20L. †7–Pin.


March, 2001 – Rev. 11

866


CS8361

VSTBY 5.0 V, 100 mA, 2.0%

VIN Overvoltage Shutdown

Current Limit

Bandgap RESET BG

+

OVSD

BG

–

TSD OVSD VIN

VTRK 250 mA Current Limit Thermal Shutdown

TSD

–

Adj

+ ENABLE

VSTBY

– +

TSD OVSD BG RESET +

GND

RESET

–

Figure 1. Block Diagram. Consult Your Local Sales Representative for Positive ENABLE Option


Value

Unit

–16 to 26

V

Positive Transient Input Voltage, tr > 1.0 ms

60

V

Negative Transient Invput Voltage, T < 100 ms, 1.0 % Duty Cycle

–50

V

–0.3 to 10

V

20

V


–40 to +150

°C


–55 to +150

°C

2.0

kV

260 peak 230 peak

°C °C

Supply Voltage, VIN

Input Voltage Range (ENABLE, RESET) Tracking Regulator (VTRK, Adj)

ESD Susceptibility (Human Body Model) Lead Temperature Soldering




CS8361 ELECTRICAL CHARACTERISTICS (6.0 V ≤ VIN ≤ 26 V, IOUT1 = IOUT2 = 100 µA, –40°C ≤ TA ≤ +125°C, –40°C ≤ TJ ≤ +150°C; unless otherwise stated.)

Test Conditions

Characteristic

Min

Typ

Max

Unit

–25

–

+25

mV

Tracking Output (VTRK) VTRK Tracking Error (VSTBY – VTRK)

6.0 V ≤ VIN ≤ 26 V, 100 µA ≤ ITRK ≤ 250 mA. Note 3

Adjust Pin Current, IAdj

Loop in Regulation

–

1.5

5.0

µA

Line Regulation

6.0 V ≤ VIN ≤ 26 V. Note 3

–

5.0

50

mV

Load Regulation

100 µA ≤ ITRK ≤ 250 mA. Note 3

–

5.0

50

mV

Dropout Voltage (VIN – VTRK)

ITRK = 100 µA. ITRK = 250 mA

– –

100 400

150 700

mV mV

Current Limit

VIN = 12 V, VTRK = 4.5 V

275

500

–

mA

Quiescent Current

VIN = 12 V, ITRK = 250 mA, No Load on VSTBY

–

25

50

mA

Reverse Current

VTRK = 5.0 V, VIN = 0 V

–

200

1500

µA

Ripple Rejection

f = 120 Hz, ITRK = 250 mA, 7.0 V ≤ VIN ≤ 17 V

60

70

–

dB

Output Voltage, VSTBY

6.0 V ≤ VIN ≤ 26 V, 100 µA ≤ ISTBY ≤ 100 mA.

4.9

5.0

5.1

V

Line Regulation

6.0 V ≤ VIN ≤ 26 V.

–

5.0

50

mV

Load Regulation

100 µA ≤ ISTBY ≤ 100 mA.

–

5.0

50

mV

Dropout Voltage (VIN – VSTBY)

ISTBY = 100 µA. ISTBY = 100 mA

– –

100 400

150 600

mV mV

Current Limit

VIN = 12 V, VSTBY = 4.5 V

125

200

–

mA


VIN = 12 V, VSTBY = 0 V

10

100

–

mA

Quiescent Current

VIN = 12 V, ISTBY = 100 mA, ITRK = 0 mA VIN = 12 V, ISTBY = 300 µA, ITRK = 0 mA

– –

10 140

20 200

mA µA

Reverse Current

VSTBY = 5.0 V, VIN = 0 V

–

100

200

µA

Ripple Rejection

f = 120 Hz, ISTBY = 100 mA, 7.0 V ≤ VIN ≤ 17 V

60

70

–

dB

–

0.8

1.2

2.0

V

Standby Output (VSTBY)

RESET ENABLE Functions ENABLE Input Threshold ENABLE Input Bias Current

VENABLE = 0 V to 10 V

–10

0

10

µA

RESET Threshold High (VRH)

VSTBY Increasing

4.59

4.87

VSTBY – 0.02

V

60

120

180

mV

4.53

4.75

VSTBY – 0.08

V

–

–

25

µA

RESET Hysteresis RESET Threshold Low (VRL)

– VSTBY Decreasing

RESET Leakage

–

Output Voltage, Low (VRLO)

1.0 V ≤ VSTBY ≤ VRL, RRST = 10 kΩ

–

0.1

0.4

V

Output Voltage, Low (VRPEAK)

VSTBY, Power Up, Power Down

–

0.6

1.0

V

150 150

180 165

– –

°C °C

30

34

38

V

Protection Circuitry (Both Outputs) Independent Thermal Shutdown Overvoltage Shutdown

VSTBY VTRK –

3. VTRK connected to Adj lead. VTRK can be set to higher values by using an external resistor divider.


CS8361 PACKAGE PIN DESCRIPTION PACKAGE PIN # D2PAK, 7 Pin

SO–16L

PIN SYMBOL

1

16

VSTBY

2

1

VIN

3

3

VTRK

Tracking output voltage controlled by ENABLE delivering 250 mA.

4

4, 5, 12, 13

GND

Reference ground connection.

5

6

Adj

6

8

ENABLE

7

9

RESET

2, 7, 10, 11, 14, 15

NC

FUNCTION Standby output voltage delivering 100 mA. Input voltage.

Resistor divider from VTRK to Adj. Sets the output voltage on VTRK. If tied to VTRK, VTRK will track VSTBY. Provides on/off control of the tracking output, active LOW. CMOS compatible output lead that goes low whenever VSTBY falls out of regulation. No connection.

CIRCUIT DESCRIPTION ENABLE Function

VTRK Output Voltage

The ENABLE function switches the output transistor for VTRK on and off. When the ENABLE lead voltage exceeds 1.4 V (typ), VTRK turns off. This input has several hundred millivolts of hysteresis to prevent spurious output activity during power–up or power–down.

This output uses the same type of output device as VSTBY, but is rated for 250 mA. The output is configured as a tracking regulator of the standby output. By using the standby output as a voltage reference, giving the user an external programming lead (Adj lead), output voltages from 5.0 V to 20 V are easily realized. The programming is done with a simple resistor divider (Figure 2), and following the formula:

RESET Function

The RESET is an open collector NPN transistor, controlled by a low voltage detection circuit sensing the VSTBY (5.0 V) output voltage. This circuit guarantees the RESET output stays below 1.0 V (0.1 V typ) when VSTBY is as low as 1.0 V to ensure reliable operation of microprocessor– based systems.

VTRK + VSTBY

(1 ) R1ńR2) ) IAdj

5.0 V, 100 mA B+

C1* 0.1 µF

VSTBY

VIN CS8361

C2** 10 µF ESR < 8.0 Ω

R3

RESET

VDD MCU RESET I/O

ENABLE R2 Adj R1 GND

R1

If another 5.0 V output is needed, simply connect the Adj lead to the VTRK output lead.

SW 8.0 V, 250 mA C3** 10 µF ESR < 8.0 Ω

VTRK

VTRK ∼ VSTBY(1 + R1/R2) For VTRK ∼ 8.0 V, R1/R2 ∼ 0.6 *C1 is required if regulator is located far from power supply filter. **C2 and C3 are required for stability.

Figure 2. Test and Application Circuit, 5.0 V, 8.0 V Regulator


GND

CS8361 5.0 V, 100 mA B+

C1* 0.1 µF

VSTBY

VIN CS8361

VDD

C2** 10 µF ESR < 8.0 Ω

R3

RESET

MCU RESET I/O

ENABLE Adj

GND

SW 5.0 V, 250 mA C3** 10 µF ESR < 8.0 Ω

VTRK

GND

*C1 is required if regulator is located far from power supply filter. **C2 and C3 are required for stability.

Figure 3. Test and Application Circuit, Dual 5.0 V Regulator

APPLICATION NOTES External Capacitors

IOUT2(max) is the maximum output current, for the application, and IQ is the quiescent current the regulator consumes at both IOUT1(max) and IOUT2(max).

Output capacitors for the CS8361 are required for stability. Without them, the regulator outputs will oscillate. Actual size and type may vary depending upon the application load and temperature range. Capacitor effective series resistance (ESR) is also a factor in the IC stability. Worst–case is determined at the minimum ambient temperature and maximum load expected. Output capacitors can be increased in size to any desired value above the minimum. One possible purpose of this would be to maintain the output voltages during brief conditions of negative input transients that might be characteristic of a particular system. Capacitors must also be rated at all ambient temperatures expected in the system. To maintain regulator stability down to –40°C, capacitors rated at that temperature must be used. More information on capacitor selection for SMART REGULATORs is available in the SMART REGULATOR application note, “Compensation for Linear Regulators,” document number SR003AN/D, available through the Literature Distribution Center or via our website at http://www.onsemi.com.

Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated: RJA +

(2)

The value of RΘJA can be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IIN VIN

SMART REGULATOR

Control Features


The maximum power dissipation for a dual output regulator (Figure 4) is PD(max)

150°C * TA PD

IOUT1 VOUT1

IOUT2 VOUT2

IQ

+ ǊVIN(max) * VOUT1(min)ǋIOUT1(max) )

ǊVIN(max) * VOUT2(min)ǋIOUT2(max) ) VIN(max)IQ (1)



Heat Sinks

A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air.


CS8361 RΘCS = the case–to–heatsink thermal resistance, and RΘSA = the heatsink–to–ambient thermal resistance.

Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RΘJA: RJA + RJC ) RCS ) RSA


(3)

where: RΘJC = the junction–to–case thermal resistance, PACKAGE THERMAL DATA Parameter

SO–16L

D2PAK, 7–Pin

Unit

RΘJC

Typical

18

3.5

°C/W

RΘJA

Typical

75

10–50*

°C/W



- # +',*# +

! The CS8147 is a 10 V/5.0 V dual output linear regulator. The 10V ±5.0% output sources 500 mA and the 5.0 V ±3% output sources 70 mA. The secondary output is inherently stable and does not require an external capacitor. The on board ENABLE function controls the regulator’s two outputs. When ENABLE is high, the regulator is placed in SLEEP mode. Both outputs are disabled and the regulator draws only 70 µA of quiescent current. The regulator is protected against overvoltage conditions. Both outputs are protected against short circuit and thermal runaway conditions. The CS8147 is packaged in a 5 lead TO–220 with copper tab. The copper tab can be connected to a heat sink if necessary.

http://onsemi.com



1

Features • Two Regulated Outputs – 10 V ±5.0%; 500 mA – 5.0 V ±3.0%; 70 mA • 70 µA SLEEP Mode Current • Inherently Stable Secondary Output (No Output Capacitor Required) • Fault Protection – Overvoltage Shutdown – Reverse Battery – 60 V Peak Transient – –50 V Reverse Transient – Short Circuit – Thermal Shutdown • CMOS Compatible ENABLE Input with Low (IOUT(max)) Input Current

1



CS8147 AWLYWW

Tab = GND Pin 1. ENABLE 2. VIN 3. GND 4. VOUT1 (10 V) 5. VOUT2 (5.0 V)




Package

Shipping

CS8147YT5

TO–220* STRAIGHT

50 Units/Rail

CS8147YTVA5

TO–220* VERTICAL

50 Units/Rail

CS8147YTHA5


50 Units/Rail

*Five lead.



872


CS8147 Primary Output

VOUT1

VIN Overvoltage Shutdown Anti–saturation and Current Limit

ENABLE

– +

Pre–Regulator

+ –

Secondary Output

Bandgap Reference

– +

VOUT2 GND

Thermal Shutdown

Current Limit



Value

Unit

–18 to 26 60 –50

V V V

2.0

kV

–0.3 to 10

V

Internally Limited

–


–40 to +150

°C


–65 to +150

°C

260 peak

°C

Input Voltage:

DC Positive Peak Transient Voltage (Note 1) Negative Peak Transient Voltage

ESD (Human Body Model) ENABLE Input Internal Power Dissipation



1. 46 V Load Dump @ VIN = 14 V 2. 10 second maximum. *The maximum package power dissipation must be observed.


CS8147 ELECTRICAL CHARACTERISTICS for VOUT: (VIN = 14 V, IOUT1 = IOUT2 = 5.0 mA, –40°C < TJ < 150°C, –40°C ≤ TA ≤ 125°C, ENABLE = LOW; unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit

9.50

10.00

10.5

V

Primary Output (VOUT1) Output Voltage

13 V ≤ VIN ≤ 26 V, IOUT1 ≤ 500 mA

Dropout Voltage

IOUT1 = 500 mA

–

0.5

0.7

V

Line Regulation

11 V ≤ VIN ≤ 18 V, IOUT1 = 250 mA

–

45

90

mV

Load Regulation

5.0 mA ≤ IOUT1 ≤ 500 mA

–

15

75

mV

Quiescent Current

IOUT1 ≤ 1.0 mA, No Load on VOUT2, VIN = 18 V IOUT1 = 500 mA, No Load on VOUT2, VIN = 11 V

– –

3.0 60

7.0 120

mA mA

Quiescent Current

ENABLE = HIGH, VOUT1, VOUT2 = OFF

–

70

200

µA

Current Limit

–

0.55

0.80

–

A

Long Term Stability

–

–

50

–

mV/khr

32

36

40

V

4.85

5.00

5.15

V


VOUT1 and VOUT2

Secondary Output (VOUT2) Output Voltage

6.0 V ≤ VIN ≤ 26 V, 1.0 mA ≤ IOUT2 ≤ 70 mA

Dropout Voltage

IOUT2 ≤ 70 mA

–

1.5

2.5

V

Line Regulation

11 ≤ VIN ≤ 18 V, IOUT = 70 µA

–

4.0

50

mV

Load Regulation

1.0 mA ≤ IOUT2 ≤ 70 mA, VIN = 14 V

–

10

50

mV

–

150

–

mA

Current Limit

–

ENABLE Function (ENABLE) Input ENABLE Threshold

VOUT2(ON) VOUT1(OFF)

– 0.8

1.40 1.40

2.50 –

V V

Input ENABLE Current

Input Voltage Range 0 to 5.0 V

–10

–

10

µA

PACKAGE PIN DESCRIPTION PACKAGE LEAD # 5 Lead TO–220

LEAD SYMBOL

1

ENABLE

2

VIN

3

GND

4

VOUT1

Regulated output 10 V, 500 mA (typ).

5

VOUT2

Secondary output 5.0 V, 70 mA (typ).

FUNCTION CMOS compatible input lead; switches VOUT1 and VOUT2 on and off. When ENABLE is low, VOUT1 and VOUT2 are active. Supply voltage, usually direct from battery. Ground connection.


CS8147

2.00

600 550 500 450 400

125°C

350

25°C

300 250

–40°C

200 150 100

1.60

25°C

1.40 1.20

125°C

1.00 0.80 0.60

VIN = 6.00 V

0.40 0.20

50 0

0 0

0

50 100 150 200 250 300 350 400 450 500 550 600

20

30

40

50

60

70

80

Output Current (mA), VOUT2 (5.0 V)

Figure 2. Dropout Voltage vs. Output Current (VOUT1)

Figure 3. Dropout Voltage vs. Output Current (VOUT2)

90 100

7.0

90

25°C

125°C

70 60 –40°C

50


80

VIN = 14 V

40 30 20

5.0 –40°C

4.0 25°C

3.0

125°C

2.0 1.0

10

VIN = 14 V

0

0 0

0

50 100 150 200 250 300 350 400 450 500 550 600

20

30

40

50

60

70

80


Figure 4. Quiescent Current vs. Output Current (VOUT1)

Figure 5. Quiescent Current vs. Output Current (VOUT2)

90 100

120 110 100 Line Regulation (mV)

5.01

5.00

4.99

125°C VIN = 11 V – 26 V

90 80

25°C

70

–40°C

60 50 40 30 20 10 0

4.98 –50

10

Output Current (mA)

5.02

VOUT (Volts)

10

Output Current (mA)

100


–40°C

1.80 Dropout Voltage (V), VOUT2

Dropout Voltage (mV), VOUT1


–30

–10

10

30

50

70

90

110

130

0

50 100 150 200 250 300 350 400 450 500 550 600

Output Current (mA), VOUT1 (10 V)

Temp (C°) PART1 VIN = 14 V, No Load

Figure 7. Line Regulation vs. Output Current (VOUT1)

Figure 6. VOUT2 vs. Temperature


30

10

26

9.0

22

8.0

125°C



CS8147

VIN = 14 V

18

25°C

14 –40°C

10 6 2 125°C

VIN = 14 V

7.0 6.0

25°C

5.0 4.0 –40°C

3.0

–2

2.0

–6

1.0 0

–10 0

0

50 100 150 200 250 300 350 400 450 500 550 600

10

20

30

40

50

60

70

80

Output Current (mA), VOUT1 (10 V)


Figure 8. Load Regulation vs. Output Current (VOUT1)

Figure 9. Load Regulation vs. Output Current (VOUT2)

90 100

350 –40°C

100.0

300

V10 = 500 mA Load V5 = 70 mA Load

IENABLE (µA)

250 ICQ (mA)

20.00 /div

0

25°C

200 150 125°C

100 50 0

–100.0 –1.000

0

0

9.000

2

3

4

5

6

7

8

9 10 11 12 13 14 15

VIN (V)

Figure 10. ENABLE Input Current vs. Input Voltage

Figure 11. Quiescent Current (ICQ) vs. VIN Overtemperature

300

10.025

VOUT1 = 500 mA Load

VIN = 14 V IO = 30 mA

10.020

VOUT2 = 100 mA Load

250

10.015 10.010

150

VOUT (V)

200 ICQ (mA)

1

VENABLE 1.000/div (V)

VOUT1 = 500 mA Load VOUT2 = No Load

100

10.005 10.000 9.995 9.990 9.985

50

VOUT1 = No Load

9.980

VOUT2 = No Load

0

9.975 0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

–50 –30 –10

10

30

50

70

90

110 130 150

VIN (V)

TEMP (°C)

Figure 12. Quiescent Current (ICQ) vs. VIN Over RLOAD



CS8147 DEFINITION OF TERMS Load Regulation – The change in output voltage for a change in load current at constant chip temperature. Long Term Stability – Output voltage stability under accelerated life–test conditions after 1000 hours with maximum rated voltage and junction temperature. Output Noise Voltage – The rms AC voltage at the output, with constant load and no input ripple, measured over a specified frequency range. Quiescent Current – The part of the positive input current that does not contribute to the positive load current. The regulator ground lead current. Ripple Rejection – The ratio of the peak–to–peak input ripple voltage to the peak–to–peak output ripple voltage. Temperature Stability of VOUT – The percentage change in output voltage for a thermal variation from room temperature to either temperature extreme.

Dropout Voltage – The input–output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100 mV from the nominal value obtained at 14 V input, dropout voltage is dependent upon load current and junction temperature. Current Limit – Peak current that can be delivered to the output. Input Voltage – The DC voltage applied to the input terminals with respect to ground. Input Output Differential – The voltage difference between the unregulated input voltage and the regulated output voltage for which the regulator will operate. Line Regulation – The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. 60 V VIN

14 V

ENABLE

2.0 V 0.8 V

31 V

26 V

14V

5.0 V

10 V

10 V

10 V

VOUT1

0V

0V

0V 5.0 V

VOUT2

5.0 V

5.0 V

3.0 V

0V

0V

Load Dump

Low VIN

Line Noise, Etc.

0V 5.0 V

5.0 V

0V Turn On

10 V

10 V

5.0 V

VOUT Short Circuit

Thermal Shutdown

Figure 14. Typical Circuit Waveform

C1 * 0.1 µF

ENABLE

10V

VOUT1

CS8147

Control

VIN

C2** 10 µF 5.0V VOUT2

GND

* C1 is required if the regulator is located away from the power source filter. ** C2 is required for stability.

Figure 15. Test & Applications Circuit


Tuner IC

0V

Turn Off

CS8147 APPLICATION NOTES Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found for each output, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ±20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitors should be less than 50% of the maximum allowable ESR found in step 3 above.

Since both outputs are controlled by the same ENABLE, the CS8147 is ideal for applications where a sleep mode is required. Using the CS8147, a section of circuitry such as a display and nonessential 5.0 V circuits can be shut down under microprocessor control to conserve energy. The test applications circuit diagram shows an automotive radio application where the display is powered by 10 V from VOUT1 and the Tuner IC is powered by 5.0 V from VOUT2. Neither output is required unless both the ignition and the Radio On/OFF switch are on. Stability Considerations

The secondary output VOUT2 is inherently stable and does not require a compensation capacitor. However a compensation capacitor connected between VOUT1 and ground is required for stability in most applications. The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor C2 shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. To determine acceptable value for C2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature.


The maximum power dissipation for a dual output regulator (Figure 16) is PD(max) + ǊVIN(max) * VOUT1(min)ǋIOUT1(max) ) ǊVIN(max) * VOUT2(min)ǋIOUT2(max) ) VIN(max)IQ (1)

where: VIN(max) is the maximum input voltage, VOUT1(min) is the minimum output voltage from VOUT1, VOUT2(min) is the minimum output voltage from VOUT2, IOUT1(max) is the maximum output current, for the application, IOUT2(max) is the maximum output current, for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated: RJA +

150°C * TA PD

(2)

The value of RΘJA can be compared with those in the package section of the data sheet. Those packages with


CS8147 Heat Sinks

RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IIN VIN

Smart Regulator

Control Features


IOUT1 VOUT1


(3)


IOUT2 VOUT2


IQ

Figure 16. Dual Output Regulator With Key Performance Parameters Labeled. PACKAGE THERMAL DATA Parameter

TO–220

Unit

RΘJC

Typical

2.4

°C/W

RΘJA

Typical

50

°C/W


,) +. ,*# +

! The CS8156 is a low dropout 12 V/5.0 V dual output linear regulator. The 12 V ±5.0% output sources 750 mA and the 5.0 V ±2.0% output sources 100 mA. The on board ENABLE function controls the regulator’s two outputs. When the ENABLE lead is low, the regulator is placed in SLEEP mode. Both outputs are disabled and the regulator draws only 200 nA of quiescent current. The regulator is protected against overvoltage conditions. Both outputs are protected against short circuit and thermal runaway conditions. The CS8156 is packaged in a 5 lead TO–220 with copper tab. The copper tab can be connected to a heat sink if necessary.

http://onsemi.com



1

Features • Two Regulated Outputs – 12 V ±5.0%; 750 mA – 5.0 V ±2.0%; 100 mA • Very Low SLEEP Mode Current Drain 200 nA • Fault Protection – Reverse Battery – +60 V, –50 V Peak Transient Voltage – Short Circuit – Thermal Shutdown • CMOS Compatible ENABLE

1



CS8156 AWLYWW

Tab = GND Pin 1. VIN 2. VOUT1 3. GND 4. ENABLE 5. VOUT2




Package

Shipping

CS8156YT5

TO–220* STRAIGHT

50 Units/Rail

CS8156YTVA5

TO–220* VERTICAL

50 Units/Rail

CS8156YTHA5


50 Units/Rail

*Five lead.



880


CS8156 VOUT2, 5.0 V

VIN

Anti–saturation and Current Limit

ENABLE

– +

Pre–Regulator

+ –

VOUT1, 12 V

Overvoltage Shutdown Anti–saturation and Current Limit

Bandgap Reference

+ –

GND Thermal Shutdown



Value

Unit

–0.5 to 26 60

V V

Internally Limited

–


–40 to +125

°C


–40 to +150

°C


–65 to +150

°C

260 peak

°C

Input Voltage:

Operating Range Peak Transient Voltage (Note 1)

Internal Power Dissipation



1. Load Dump = 46 V 2. 10 second maximum. *The maximum package power dissipation must be observed.


CS8156 ELECTRICAL CHARACTERISTICS for VOUT: (VIN = 14.5 V, IOUT1 = 5.0 mA, IOUT2 = 5.0 mA, –40°C ≤ TJ ≤ +150°C, –40°C ≤ TC ≤ +125°C; unless otherwise specified.)

Test Conditions

Min

Typ

Max

Unit

Output Voltage, (VOUT1)

13 V ≤ VIN ≤ 16 V, IOUT1 ≤ 750 mA

11.2

12.0

12.8

V

Dropout Voltage

IOUT1 = 500 mA IOUT1 = 750 mA

–

0.4 0.6

0.6 1.0

V V

Line Regulation

13 V ≤ VIN ≤ 16 V, 5.0 mA ≤ IOUT1 < 100 mA

–

15

80

mV

Load Regulation

5.0 mA ≤ IOUT1 ≤ 500 mA

–

15

80

mV

Quiescent Current

IOUT1 ≤ 500 mA, No Load on Standby IOUT1 ≤ 750 mA, No Load on Standby

– –

45 100

125 250

mA mA

Quiescent Current (Sleep Mode)

ENABLE = Low

–

0.2

50

µA

Ripple Rejection

f = 120 Hz, IOUT = 5.0 mA, VIN = 1.5 VPP at 15.5 VDC

42

70

–

dB

–

0.75

1.20

2.50

A

Characteristic Output Stage (VOUT1)

Current Limit Maximum Line Transient

VOUT1 ≤ 13 V

60

90

–

V

Reverse Polarity Input Voltage, DC

VOUT1 ≥ –0.6 V, 10 Ω Load

–18

–30

–

V

Reverse Polarity Input Voltage, Transient

1.0% Duty Cycle, t = 100 ms, VOUT ≥ –6.0 V, 10 Ω Load

–50

–80

–

V


10 Hz – 100 kHz

–

–

500

µVrms

Output Impedance

500 mA DC and 10 mA rms, 100Hz

–

0.2

1.0

Ω

28

34

45

V

4.90

5.00

5.10

V


–

Standby Output (VOUT2) Output Voltage, (VOUT2)

9.0 V ≤ VIN ≤ 16 V, 1.0 mA ≤ IOUT2 ≤ 100 mA

Dropout Voltage

IOUT2 ≤ 100 mA

–

–

0.60

V

Line Regulation

6.0 V ≤ VIN ≤ 26 V, 1.0 mA ≤ IOUT ≤ 100 mA

–

5.0

50

mV

Load Regulation

1.0 mA ≤ IOUT2 ≤ 100 mA; 9.0 V ≤ VIN ≤ 16 V

–

5.0

50

mV

Ripple Rejection

f = 120 Hz; IOUT = 100 mA, VIN = 1.5 VPP at 14.5 VDC

42

70

–

dB

–

100

200

–

mA

Current Limit ENABLE Function (ENABLE) Input ENABLE Threshold

VOUT1 Off VOUT1 On

– 2.00

1.25 1.25

0.80 –

V V


VENABLE ≤ VTHRESHOLD

–10

0

10

µA

PACKAGE PIN DESCRIPTION PACKAGE LEAD # 5 Lead TO–220

LEAD SYMBOL

1

VIN

2

VOUT1

3

GND

4

ENABLE

5

VOUT2

FUNCTION Supply voltage, usually direct from battery. Regulated output 12 V, 750 mA (typ). Ground connection. CMOS compatible input lead; switches outputs on and off. When ENABLE is high VOUT1 and VOUT2 are active. Regulated output 5.0 V, 100 mA (typ).


CS8156 TYPICAL PERFORMANCE CHARACTERISTICS 2000

1600 Output Voltage (V)


1800

1400 1200 1000 800 600 400 200 0 0

50

100

150

13 12 11 10 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 –1.0 –2.0

RL = 10 Ω

200

–40

–20

0

20

40

IOUT (mA)

Input Voltage (V)

Figure 2. Dropout Voltage vs. IOUT2

Figure 3. VOUT1 vs. Input Voltage

12.15

60

5.030

12.10

5.020 5.010

12.00

VOUT2 (V)

VOUT1 (V)

12.05

11.95 11.90

5.000 4.990

11.85 4.980

11.80 11.75 0

20

40

60

80

4.970

100 120 140 160

–40 –20

20

40

60

80

100 120 140 160

Temp (°C)



100

5.0

80

4.0

60 40

3.0 2.0 1.0

20 0

0

Temp (°C)

IENABLE (mA)

IENABLE (µA)

–40 –20

0

1.0

2.0

3.0

4.0

0

5.0

VENABLE (V)

0

5.0

10

15

20

VENABLE (V)

Figure 6. ENABLE Current vs. ENABLE Voltage



25

CS8156 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 10

10 0 –10 –20 3.0 2.0 1.0 0 0

10

20

30

40

50

–5.0 –10

3.0 2.0 1.0 0

60

0

20

30

40

50

60

Figure 8. Line Transient Response (VOUT1)

Figure 9. Line Transient Response (VOUT2)

150

100

100

50 0 –50 –100

Standby Load Current (mA)

0.8 0.6 0.4 0.2

50 0 –50 –100 –150 20 15 10 5.0 0

0 0

10

20

30

40

50

60

0

10

20

30

40

50

Time (µs)

Time (µs)

Figure 10. Load Transient Response (VOUT1)

Figure 11. Load Transient Response (VOUT2)

20 18 Infinite Heat Sink

16


Power Dissipation (W)

10

Time (µs)

–150 Load Current (A)

0

150

14 12 10 8.0

10°C/W Heat Sink

6.0 4.0

No Heat Sink

2.0 0 0

IOUT2 = 100 mA

5.0

Time (µs)

Standby Output Voltage Deviation (mV)



IOUT1 = 500 mA

Input Voltage Chnage (V)

Input Voltage Change (V)


20

10

20

30

40

50

60

70

80

90

150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0

60

No Load on 5.0 V 125°C VIN = 14 V 25°C

–40°C

0

100

200

300

400

500

600

700

Ambient Temperature (°C)

Output Current (mA)

Figure 12. Maximum Power Dissipation (TO–220)

Figure 13. Quiescent Current vs. Output Current for VOUT2


800

CS8156 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 22

2.0

18 16



3.0

No Load on 5.0 V

20

VIN = 14 V

14 12 10 8.0

–40°C

6.0 4.0

–40°C

–1.0

125°C

–2.0 –3.0 VIN = 6.0–26 V

–5.0

125°C

0

–6.0 0

20

40

60

80

100

120

140

0

80

100

120

140

Figure 15. Line Regulation vs. Output Current for VOUT2

25°C Line Regulation (mV)

–4.0 –6.0 –8.0 –10 –12 125°C VIN = 14 V

–18 20

40

60

80

100

120

25 20 15 10 5.0 0 –5.0 –10 –15 –20 –25 –30 –35 –40

140

125°C

25°C

VIN = 13–26V –40°C

0

100

200

300

400

500

600

700

Output Current (mA)

Output Current (mA)

Figure 16. Load Regulation vs. Output Current fo VOUT2

Figure 17. Line Regulation vs. Output Current for VOUT1

0 –5.0 Load Regulation (mV)

0

60


–2.0

–16

40

Output Current (mA)

–40°C

–14

20

Output Current (mA)

0


25°C

0

–4.0

25°C

2.0

1.0

–40°C

–10

25°C

–15 –20

125°C

–25 –30 VIN = 14 V –35 –40 0

100

200

300

400

500

600

700

Output Current (mA)

Figure 18. Load Regulation vs. Output Current for VOUT1


800

800

CS8156 DEFINITION OF TERMS Load Regulation – The change in output voltage for a change in load current at constant chip temperature. Long Term Stability – Output voltage stability under accelerated life–test conditions after 1000 hours with maximum rated voltage and junction temperature. Output Noise Voltage – The rms AC voltage at the output, with constant load and no input ripple, measured over a specified frequency range. Quiescent Current – The part of the positive input current that does not contribute to the positive load current, i.e., the regulator ground lead current. Ripple Rejection – The ratio of the peak–to–peak input ripple voltage to the peak–to–peak output ripple voltage. Temperature Stability of VOUT – The percentage change in output voltage for a thermal variation from room temperature to either temperature extreme.

Dropout Voltage – The input–output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100 mV from the nominal value obtained at 14 V input, dropout voltage is dependent upon load current and junction temperature. Input Voltage – The DC voltage applied to the input terminals with respect to ground. Input Output Differential – The voltage difference between the unregulated input voltage and the regulated output voltage for which the regulator will operate. Line Regulation – The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. 60 V VIN

14 V

ENABLE

2.0 V 0.8 V

34 V

26 V

14V

3.0 V

12 V

12 V

12 V

12 V

12 V

2.4 V VOUT1

0V

0V

0V

5.0 V VOUT2

5.0 V 2.4 V

0V Turn On

Load Dump

Low VIN

Line Noise, Etc.

VOUT1 Short Circuit

VOUT2 Short Circuit

VOUT1 Thermal Shutdown

Turn Off


APPLICATION NOTES Stability Considerations

To determine acceptable values for C2 and C3 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part for each output. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor C2 will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations

The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the cheapest solution, but, if the circuit operates at low temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitors C2 and C3 shown in the test and applications circuit should work for most applications, however it is not necessarily the best solution.


CS8156 IOUT2(max) is the maximum output current, for the application, and IQ is the quiescent current the regulator consumes at IOUT(max).

are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found for each output, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ±20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitors should be less than 50% of the maximum allowable ESR found in step 3 above. Repeat steps 1 through 7 with C3, the capacitor on the other output.


(2)

The value of RΘJA can be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IIN

Smart Regulator

VIN

Control Features

IOUT1 VOUT1

IOUT2 VOUT2

IQ

Figure 20. Dual Output Regulator With Key Performance Parameters Labeled. Heat Sinks



The maximum power dissipation for a dual output regulator (Figure 20) is PD(max)

150°C * TA PD


+ ǊVIN(max) * VOUT1(min)ǋIOUT1(max) )

(3)


ǊVIN(max) * VOUT2(min)ǋIOUT2(max) ) VIN(max)IQ (1)




CS8156

C1 * 0.1 µF VIN CS8156

VOUT1

+

C2** 22 µF

+

C3** 22 µF

ENABLE VOUT2

GND

* C1 is required if the regulator is far from power supply filter. ** C2, C3 required for stability.



TO–220 FIVE LEAD

Unit

RΘJC

Typical

2.0

°C/W

RΘJA

Typical

50

°C/W


) +. ,*# +

! The CS8161 is a 12 V/5.0 V dual output linear regulator. The 12V ±5.0% output sources 400 mA and the 5.0 V ±2.0% output sources 200 mA. The on board ENABLE function controls the regulator’s two outputs. When the ENABLE pin is low, the regulator is placed in SLEEP mode. Both outputs are disabled and the regulator draws only 200 nA of quiescent current. The primary output, VOUT1 is protected against overvoltage conditions. Both outputs are protected against short circuit and thermal runaway conditions. The CS8161 is packaged in a 5 lead TO–220 with copper tab. The copper tab can be connected to a heat sink if necessary. Features • Two Regulated Outputs – 12 V ±5.0%; 400 mA – 5.0 V ±2.0%; 200 mA • Very Low SLEEP Mode Current Drain 200 nA • Fault Protection – Reverse Battery (–15 V) – 74 V Load Dump – –100 V Reverse Transient – Short Circuit – Thermal Shutdown

http://onsemi.com



1

1



CS8161 AWLYWW

Tab = GND Pin 1. VIN 2. VOUT1 3. GND 4. ENABLE 5. VOUT2




Package

Shipping

CS8161YT5

TO–220** STRAIGHT

50 Units/Rail

CS8161YTVA5

TO–220** VERTICAL

50 Units/Rail

CS8161YTHA5

TO–220** HORIZONTAL

50 Units/Rail

*Consult your local sales representative for SO–16L package option. **Five lead.



889


CS8161 VOUT2

VIN

Anti–saturation and Current Limit

ENABLE

+ –

Pre–Regulator

+ –

VOUT1

Overvoltage Shutdown Anti–saturation and Current Limit

Bandgap Reference

+ –

GND Thermal Shutdown



Value

Unit

–15 to 26 74

V V

Internally Limited

–


–40 to +150

°C


–65 to +150

°C

260 peak 230 peak

°C °C

2.0

kV

Input Voltage:

Operating Range Overvoltage Protection

Internal Power Dissipation



ESD (Human Body Model) 1. 10 second maximum. 2. 60 second maximum above 183°C *The maximum package power dissipation must be observed.


CS8161 ELECTRICAL CHARACTERISTICS for VOUT: (6.0 V ≤ VIN ≤ 26 V; IOUT1 = 5.0 mA; IOUT2 = 5.0 mA; –40°C ≤ TJ ≤ +150°C; –40°C ≤ TA ≤ +125°C; unless otherwise specified.) Test Conditions

Min

Typ

Max

Unit

Output Voltage, VOUT1

13 V ≤ VIN ≤ 26 V, IOUT1 ≤ 400 mA

11.4

12.0

12.6

V

Dropout Voltage

IOUT1 = 400 mA

–

0.35

0.6

V

Line Regulation

13 V ≤ VIN ≤ 20 V, 5.0 mA ≤ IOUT < 400 mA

–

–

80

mV

Load Regulation

5.0 mA ≤ IOUT1 ≤ 400 mA, VIN = 14 V

–

–

80

mV

Quiescent Current

IOUT1 ≤ 100 mA, No Load on VOUT2 IOUT1 ≤ 400 mA, No Load on VOUT2

– –

8.0 50

12 75

mA mA

Ripple Rejection

f = 120 Hz, IOUT = 300 µA, VIN = 15.0 VDC, 2.0 VRMS

42

–

–

dB

–

0.40

–

1.0

A

Characteristic Primary Output Stage (VOUT1)

Current Limit Reverse Polarity Input Voltage, DC

VOUT1 ≥ –0.6 V, 10 Ω Load

–

–30

–18

V

Reverse Polarity Input Voltage, Transient

1.0% Duty Cycle, t = 100 ms, VOUT ≥ –6.0 V, 10 Ω Load

–

–80

–50

V


–

28

34

45

V


–

–

–

700

mA

4.90

–

5.10

V

Secondary Output (VOUT2) Output Voltage, (VOUT2)

6.0 V ≤ VIN ≤ 26 V, IOUT2 ≤ 200 mA

Dropout Voltage

IOUT2 ≤ 200 mA

–

0.35

0.60

V

Line Regulation

6.0 V ≤ VIN ≤ 26 V, 1.0 mA ≤ IOUT ≤ 200 mA

–

–

50

mV

Load Regulation

1.0 mA ≤ IOUT2 ≤ 200 mA; VIN =14 V

–

–

50

mV

Quiescent Current

IOUT2 = 50 mA IOUT2 = 200 mA

– –

5.0 20

10 35

mA mA

Ripple Rejection

f = 120 Hz; IOUT = 10 mA, VIN = 15 V, 2.0 VRMS

42

–

–

dB

Current Limit

–

200

–

600

mA


–

–

–

400

mA

ENABLE Function (ENABLE) Input ENABLE Threshold

VOUT1 Off VOUT1 On

– 2.00

1.30 1.30

0.80 –

V V


VENABLE = 5.5 V VENABLE < 0.8 V

80 –10

– –

500 10

µA µA

VENABLE < 0.4 V

–

0.2

50

µA

150

–

210

°C

–

–

60

mA

Other Features Sleep Mode Thermal Shutdown Quiescent Current in Dropout

– IOUT1 = 100 mA, IOUT2 = 50 mA


CS8161 PACKAGE PIN DESCRIPTION PACKAGE LEAD # 5 Lead TO–220

LEAD SYMBOL

1

VIN

2

VOUT1

3

GND

4

ENABLE

5

VOUT2

FUNCTION Supply voltage, usually direct from battery. Regulated output 12 V, 400 mA (typ). Ground connection. CMOS compatible input lead; switches outputs on and off. When ENABLE is high VOUT1 and VOUT2 are active. Regulated output 5.0 V, 200 mA (typ).

TYPICAL PERFORMANCE CHARACTERISTICS 12.150 12.110

10 VIN = 14 V IOUT1 = 5.0 A

12.070 Line Regulation (mV)

0

Volt 1

12.030 11.990 11.950 11.910 11.870

125°C

–20 –25

11.790

–35

–40°C

–40

–40 –20

15

25°C

–15

–30

11.750 0

20

40

60

80

100 120 140 160

0

50

100 150 200 250

300 350 400 450 500

Temperature (°C)

Output Current (mA)

Figure 2. Output Voltage vs. Temperature for VOUT1

Figure 3. Line Regulation vs. Output Current for VOUT1 100

–40°C

VIN = 14 V

VIN = 14 V No Load on VOUT2

90

0


5 Load Regulation (mV)

–5 –10

11.830

10

VIN = 13–26V

5

25°C

5 10 15 20 25

125°C

30

80

125°C

70 –40°C

60 50 40

25°C

30 20 10

35 40 0

50

100 150 200 250

0

300 350 400 450 500

0

50

100 150 200 250

300 350 400 450 500

Output Current (mA)

Output Current (mA)




CS8161 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 600 550

VIN = 11 V

450



500 25°C

400 350

125°C

300

–40°C

250 200 150 100 50 0 0

50

100 150 200 250 300 350 400 450 500

125°C

50

100

150 200 250 300

350 400 450

Output Current (mA)

Figure 6. Dropout Voltage vs. Output Voltage for VOUT1

Figure 7. Quiescent Current vs. Output Current @ Dropout for VOUT1

500

3 VIN = 11 V IOUT = 5.0 mA

VIN = 6.0–26V

2 1 Load Regulation (mV)

Output Voltage

–40°C 25°C

0

5.015 5.010 5.005 5.000 4.995 4.990

0 –1

–40°C

125°C

–2 –3 –4 –5

4.985

–6

4.980

–7

25°C

–8

4.975

–40 –20

0

20

40

60

80

100 120 140 160

0

25

50

75

100 125 150 175 200 225 250

Temperature (°C)

Output Current (mA)

Figure 8. Output Voltage vs. Temperature for VOUT2

Figure 9. Line Regulation vs. Output Current for VOUT2 50

8 6 4 2 0 –2

VIN = 14 V

–40°C

25°C

–4 –6 –8 –10 –12 –14 –16 –18


45 Quiescent Current (mA)



Output Current (mA)

5.025 5.020

150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0

125°C

40 –40°C

35 30

125°C

25 20

25°C

15 10 5

0

25

50

75

0

100 125 150 175 200 225 250

0

25

50

75

100 125 150 175 200 225 250

Output Current (mA)

Output Current (mA)




CS8161

60

800 750 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0

VIN = 4.0 V No Load on VOUT1

VIN = 4.0 V

55 50

125°C Quiescent Current (mA)


TYPICAL PERFORMANCE CHARACTERISTICS (continued)

–40°C 25°C

–40°C

45 40 35

125°C

25°C

30 25 20 15 10 5 0

0

25

50

75

100 125 150 175 200 225 250

0

25

50

75

100 125 150

175 200

225 250

Output Current (mA)

Output Current (mA)

Figure 12. Dropout Voltage vs. Output Current for VOUT2

Figure 13. Quiescent Current vs. Output Current @ Dropout for VOUT2

1.305

(1.8500 V, 253.9 nA.) VIN = 14 V

100

IENABLE

80 1.295

60 40

1.290 20 1.285 –40

–20

0

20

40

60

80

100

120

0

140

0

1

2

3

4

Temperature (°C)

VENABLE (V)

Figure 14. Enable Threshold Voltage vs. Temperature


5 4 IENABLE

ENABLE Voltage

1.300

3 2 1 0 0

5

10

15

20

VENABLE

Figure 16. 12 mA ENABLE Current vs. ENABLE Voltage


25

5

CS8161 DEFINITION OF TERMS Load Regulation – The change in output voltage for a change in load current at constant chip temperature. Long Term Stability – Output voltage stability under accelerated life–test conditions after 1000 hours with maximum rated voltage and junction temperature. Output Noise Voltage – The rms AC voltage at the output, with constant load and no input ripple, measured over a specified frequency range. Quiescent Current – The part of the positive input current that does not contribute to the positive load current, i.e., the regulator ground lead current. Ripple Rejection – The ratio of the peak–to–peak input ripple voltage to the peak–to–peak output ripple voltage. Temperature Stability of VOUT – The percentage change in output voltage for a thermal variation from room temperature to either temperature extreme.

Dropout Voltage – The input–output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100 mV from the nominal value obtained at 14 V input, dropout voltage is dependent upon load current and junction temperature. Input Voltage – The DC voltage applied to the input terminals with respect to ground. Input Output Differential – The voltage difference between the unregulated input voltage and the regulated output voltage for which the regulator will operate. Line Regulation – The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. 60 V VIN

14 V

ENABLE

2.0 V 0.8 V

34 V

26 V

14V

3.0 V

12 V

12 V

12 V

12 V

12 V

2.4 V VOUT1

0V

0V

0V 5.0 V

5.0 V

VOUT2

0V

5.0 V

2.4 V

0V

0V

0V Turn On

Load Dump

Low VIN

Line Noise, Etc.

VOUT1 Short Circuit

VOUT2 Short Circuit

VOUT1 Thermal Shutdown


APPLICATION DIAGRAM

C1 * 0.1 µF

Display VIN CS8161

VOUT1

+

C2 * 22 µF

+

C3 * 22 µF

ENABLE

GND

VOUT2

Tuner

* C1 required if regulator is located far from power supply filter. ** C2, C3 required for stability, value may be increased. Capacitor must operate at minimum temperature expected.



Turn Off

CS8161 APPLICATION NOTES This point represents the worst case input voltage conditions. Step 5: If the capacitor C2 is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. (A smaller capacitor will usually cost less and occupy less board space.) If the capacitor oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real work environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ±20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitors should be less than 50% of the maximum allowable ESR found in step 3 above. Once the value for C2 is determined, repeat the steps to determine the appropriate value for C3.

Since both outputs are controlled by the same ENABLE, the CS8161 is ideal for applications where a sleep mode is required. Using the CS8161, a section of circuitry such as a display and nonessential 5.0 V circuits can be shut down under microprocessor control to conserve energy. The example in the Applications Diagram (Figure 18) shows an automotive radio application where the display is powered by the 12 V on VOUT1 and the Tuner IC is powered by the 5.0 V on VOUT2. Neither output is required unless both the ignition and the Radio On/Off switch are on. Stability Considerations

The output or compensation capacitor (Application diagram C2 and C3) helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the cheapest solution, but, if the circuit operates at low temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The values for the output capacitors C2 and C3 shown in the test and applications circuit should work for most applications, however it is not necessarily the best solution. To determine acceptable values for C2 and C3 for a particular application, start with tantalum capacitors of the recommended value on each output and work towards less expensive alternative parts for each output in turn. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs on the oscilloscope. A decade box connected in series with the capacitor C2 will simulate the higher ESR of an aluminum capacitor.(Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible) Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase.


The maximum power dissipation for a dual output regulator (Figure 19) is PD(max) + ǊVIN(max) * VOUT1(min)ǋIOUT1(max) ) ǊVIN(max) * VOUT2(min)ǋIOUT2(max) ) VIN(max)IQ (1)

where: VIN(max) is the maximum input voltage, VOUT1(min) is the minimum output voltage from VOUT1, VOUT2(min) is the minimum output voltage from VOUT2, IOUT1(max) is the maximum output current, for the application, IOUT2(max) is the maximum output current, for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated: RJA +

150°C * TA PD

(2)

The value of RΘJA can be compared with those in the package section of the data sheet. Those packages with


CS8161 Heat Sinks

RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IIN VIN

Smart Regulator

Control Features


IOUT1 VOUT1


(3)


IOUT2 VOUT2


IQ

Figure 19. Dual Output Regulator With Key Performance Parameters Labeled. PACKAGE THERMAL DATA Parameter

TO–220 FIVE LEAD

Unit

RΘJC

Typical

2.0

°C/W

RΘJA

Typical

50

°C/W


,*# +',# $. ,*# +'## $ ! The CS8281 is a precision, dual 5.0 V micropower linear voltage regulator. The switched primary output (VOUT1) supplies up to 250 mA while the secondary (VOUT2) is capable of supplying 100 mA. Both outputs have a maximum dropout voltage of 600 mV and low reverse current. Quiescent current drain is typically 150 µA when supplying 100 µA from each output. The ENABLE input provides logic level control of the primary output. With the primary output disabled, quiescent current drain is typically 100 µA when supplying 100 µA from the secondary output. The CS8281 is extremely robust with protection provided for reverse battery, short circuit, overvoltage, and overtemperature on both outputs. The CS8281 is available in a 5–lead D2PAK. Features • 5.0 V/250 mA Primary Output • 5.0 V/100 mA Secondary Output • 3.0% Tolerance, Both Outputs • ON/OFF Control for Primary Output • Low Quiescent Current Drain (100 µA VOUT2) • Low Reverse Current • Protection Features – Reverse Battery (–15 V) – 74 V Load Dump – Short Circuit – Overtemperature – Overvoltage (34 V)

http://onsemi.com


1 5


Tab = GND Pin 1. VIN 2. VOUT1 3. GND 4. VOUT2 5. ENABLE

CS8281 AWLYWW




Package

Shipping

CS8281YDP5

D2PAK, 5–PIN

50 Units/Rail

CS8281YDPR5

D2PAK, 5–PIN

750 Tape & Reel

*Consult your local sales representative for SO–8, SO–16, DIP–8, DIP–16, TO–220 FIVE LEAD, and D2PAK 7–PIN packaging options.



898


CS8281

Primary Output

VOUT1

VIN

ENABLE

+ –

VOUT1SENSE

Current Limit + –

Bandgap Reference

Overvoltage Shutdown Thermal Shutdown Secondary Output

VOUT2

VOUT2SENSE

Current Limit + –

Pwr GND

GND



Value

Unit

–15 to 74

V

Internally Limited

–


–40 to +125

°C


–40 to +150

°C


–55 to +150

°C

4.0

kV

230 peak

°C

Input Voltage Power Dissipation

Electrostatic Discharge (Human Body Model) Lead Temperature Soldering

Reflow (SMD styles only) (Note 1)



CS8281 ELECTRICAL CHARACTERISTICS: (6.0 V ≤ VIN ≤ 26 V, IOUT1 = IOUT2 = 100 µA, –40°C ≤ TC ≤ 125°C; unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit

4.85

5.00

5.15

V

Primary Output Stage (VOUT1) Output Voltage, VOUT1

100 µA ≤ IOUT1 ≤ 250 mA

Dropout Voltage

IOUT1 = 250 mA IOUT1 = 100 µA

– –

400 100

600 150

mV mV

Line Regulation

6.0 V ≤ VIN ≤ 26 V

–

5.0

50

mV

Load Regulation

1.0 mA ≤ IOUT1 ≤ 250 mA, VIN = 14 V

–

5.0

50

mV

Quiescent Current

ENABLE = HIGH, VIN = 16V, IOUT1 = 250 mA

–

22

50

mA

Ripple Rejection

f = 120 Hz, IOUT1 = 125 mA, 7.0 V ≤ VIN ≤ 17 V

60

70

–

dB

260

400

–

mA

Current Limit

–

Short Circuit Current Limit

VOUT1 = 0 V, VIN = 16 V

25

–

–

mA

Reverse Current

VOUT1 = 5.0 V, VIN = 0 V

–

100

1500

µA


100 µA ≤ IOUT1 ≤ 100 mA

4.85

5.00

5.15

V

Dropout Voltage


–

400 100

600 150

mV mV

Line Regulation

6.0 V ≤ VIN ≤ 26 V

–

5.0

50

mV

Load Regulation

100 µA ≤ IOUT2 ≤ 100 mA, VIN = 14 V

–

5.0

50

mV

Quiescent Current

ENABLE = LOW, VIN = 12.8 V ENABLE = HIGH, VIN = 16 V

– –

100 8.0

150 25

µA mA

Ripple Rejection

f = 120 Hz; IOUT2 = 50 mA, 7.0 V ≤ VIN ≤ 17 V

60

70

–

dB

105

200

–

mA

Secondary Output (VOUT2)

Current Limit

–


VOUT2 = 0 V, VIN = 16 V, IOUT1 = 0 A

25

–

–

mA

Reverse Current

VOUT2 = 5.0 V, VIN = 0 V

–

100

250

µA

ENABLE Function (ENABLE) Input Threshold

ENABLE = LOW, 7.0 V ≤ VIN ≤ 26 V ENABLE = HIGH, 7.0 V ≤ VIN ≤ 26 V

– 2.0

1.2 1.2

0.8 –

V V

Input Bias Current

0 V ≤ VENABLE ≤ 5.0 V

–2.0

0

2.0

µA

Protection Circuits Overtemperature Threshold

–

150

180

–

°C


–

30

34

38

V

PACKAGE PIN DESCRIPTION PACKAGE LEAD # D2PAK, 5–PIN

LEAD SYMBOL

1

VIN

2

VOUT1

3

GND

4

VOUT2

5

ENABLE

FUNCTION Supply voltage to IC, usually direct from battery. 5.0 V regulated output which is activated by ENABLE input. Ground connection. Standby output 5.0 V, 100 mA capability; always on. CMOS compatible input lead; switches VOUT1. When ENABLE is high, VOUT1 is active.


CS8281 DEFINITION OF TERMS Load Regulation – The change in output voltage for a change in load current at constant chip temperature. Long Term Stability – Output voltage stability under accelerated life–test conditions after 1000 hours with maximum rated voltage and junction temperature. Quiescent Current – The part of the positive input current that does not contribute to the positive load current, i.e., the regulator ground lead current. Ripple Rejection – The ratio of the peak–to–peak input ripple voltage to the peak–to–peak output ripple voltage. Short Circuit Current Limit – Peak current that can be delivered by the outout when forced to 0 V. Temperature Stability of VOUT – The percentage change in output voltage for a thermal variation from room temperature to either temperature extreme.

Current Limit – Peak current that can be delivered to the output. Dropout Voltage – The input–output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100 mV from the nominal value obtained at 14 V input, dropout voltage is dependent upon load current and junction temperature. Input Output Differential – The voltage difference between the unregulated input voltage and the regulated output voltage for which the regulator will operate. Input Voltage – The DC voltage applied to the input terminals with respect to ground. Line Regulation – The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. 60 V VIN

14 V

ENABLE

2.0 V 0.8 V

26 V

34 V

5.0 V

14 V

3.0 V

5.0 V

5.0 V

5.0 V

5.0 V

5.0 V

2.4 V VOUT1

0V

VOUT2

0V

System Condition

0V 5.0 V

5.0 V

5.0 V

0V 5.0 V

0V 5.0 V

5.0 V

2.4 V 0V

Turn On

Load Dump

Low VIN

Line VOUT1 Noise, Etc. Short Circuit

VOUT2 Short Circuit

Thermal Shutdown

Turn Off


APPLICATION NOTES General

Worst–case is determined at the minimum ambient temperature and maximum load expected. Output capacitors can be increased in size to any desired value above the minimum. One possible purpose of this would be to maintain the output voltages during brief conditions of negative input transients that might be characteristic of a particular system. Capacitors must also be rated at all ambient temperatures expected in the system. To maintain regulator stability down to –40°C, capacitors rated at that temperature must be used. More information on capacitor selection for SMART REGULATORs is available in the SMART REGULATOR application note, “Compensation for Linear Regulators,” document number SR003AN/D, available through the Literature Distribution Center or via our website at http://www.onsemi.com.

The CS8281 is a micropower dual 5.0 V regulator. All bias required to operate the internal circuitry is derived from the standby output, VOUT2. If this output experiences an over current situation and collapses, then VOUT1 will also collapse (see Figure 2). If there is critical circuitry that must remain active under most conditions it should be connected to VOUT2. Any circuitry that is likely to be subjected to a short circuit, e.g., circuitry outside the module, should be connected to VOUT1. External Capacitors

Output capacitors are required for stability with the CS8281. Without them, the regulator outputs will oscillate. Actual size and type may vary depending upon the application load and temperature range. Capacitor effective series resistance (ESR) is also a factor in the IC stability.


CS8281 ENABLE

IIN

The ENABLE function controls VOUT1. When ENABLE is high, VOUT1 is on. When ENABLE is low, VOUT1 is off. Calculating Power Dissipation in a Dual Output Linear Regulator


IOUT2 VOUT2

IQ

where: VIN(max) is the maximum input voltage, VOUT1(min) is the minimum output voltage from VOUT1, VOUT2(min) is the minimum output voltage from VOUT2, IOUT1(max) is the maximum output current, for the application, IOUT2(max) is the maximum output current, for the application, and IQ is the quiescent current the regulator consumes at both IOUT1(max) and IOUT2(max).

Figure 3. Dual Output Regulator With Key Performance Parameters Labeled. Heat Sinks


Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated: 150°C * TA PD

VOUT1

Control Features


RJA +

IOUT1

SMART REGULATOR

VIN



(2)

The value of RΘJA can be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.


TEST & APPLICATION DIAGRAM

VCC

VOUT2

VIN 0.1 µF

C2**

C1 * CS8281

VBATT

22 µF ESR < 8 Ω

mP

VOUT1 22 µF ESR < 8 Ω

C3**

Load

(3)

ENABLE

I/O GND

GND

* C1 required if regulator is located far from power supply filter. ** C2 and C3 required for stability. Capacitor must operate at minimum temperature expected during system operations.




D2PAK, 5–PIN

Unit

RΘJC

Typical

2.4

°C/W

RΘJA

Typical

10–50*

°C/W



" *# +'*# . ,*# +',# $

/ 0 01t The CS8371 is an 8.0 V/5.0 V dual output linear regulator. The 8.0 V ±5.0% output sources 1.0 A, while the 5.0 V ±5.0% output sources 250 mA. Each output is controlled by its own ENABLE lead. Setting the ENABLE input high turns on the associated regulator output. Holding both ENABLE inputs low puts the IC into sleep mode where current consumption is less than 10 µA. The regulator is protected against overvoltage, short–circuit and thermal runaway conditions. The device can withstand 45 V load dump transients making suitable for use in automotive environments. ON’s proprietary NOCAP solution is the first technology which allows the output to be stable without the use of an external capacitor. The CS8371 is available in a 7 lead TO–220 package with copper tab. The tab can be connected to a heatsink if necessary.

http://onsemi.com

TO–220 SEVEN LEAD T SUFFIX CASE 821E

1 7


1

TO–220 SEVEN LEAD THA SUFFIX CASE 821H

Features

• Two Regulated Outputs – 8.0 V ±5.0%; 1.0 A – 5.0 V ±5.0%; 250 mA • Independent ENABLE for Each Output • Seperate Sense Feedback Lead for 8.0 V Output • < 10 µA Sleep Mode Current • Fault Protection – Overvoltage Shutdown – +45 V Peak Transient Voltage – Short Circuit – Thermal Shutdown • CMOS Compatible, Low Current ENABLE Inputs

1 7


CS8371 AWLYWW

Tab = GND Pin 1. ENABLE1 2. ENABLE2 3. VOUT2 4. GND 5. Sense 6. VCC 7. VOUT1




Package

Shipping

CS8371ET7

TO–220* STRAIGHT

50 Units/Rail

CS8371ETVA7

TO–220* VERTICAL

50 Units/Rail

CS8371ETHA7


50 Units/Rail

*Seven lead.



904


CS8371 VCC Overvoltage Shutdown

ENABLE1

VOUT1

– +

1.2 V

Current Limit Pre–Regulator Bias Generator

+ –

Sense NOCAP

Trimmed Bandgap Voltage Reference

Thermal Shutdown

ENABLE2

– +

1.2 V

– +

VOUT2 Current Limit

GND



Value

Unit

Internally Limited

–

ENABLE Input Voltage Range

–0.6 to +10

V

Load Current (8.0 V Regulator)

Internally Limited

–

Load Current (5.0 V Regulator)

Internally Limited

–

45

V


–65 to +150

°C


–40 to +150

°C

260 peak

°C

Power Dissipation

Transient Peak Voltage (31 V Load Dump @ 14 V VCC)





CS8371 ELECTRICAL CHARACTERISTICS: (–40°C ≤ TA ≤ +85°C, 10.5 V ≤ VCC ≤ 16 V, ENABLE1 = ENABLE2 = 5.0 V, IOUT1 = IOUT2 = 5.0 mA, unless otherwise stated.) Test Conditions

Characteristic

Min

Typ

Max

Unit

7.60

8.00

8.40

V

Primary Output (VOUT1) Output Voltage

IOUT1 = 1.0 A

Line Regulation

10.5 V ≤ VCC ≤ 26 V

–

–

50

mV

Load Regulation

5.0 mA ≤ IOUT1 ≤ 1.0 A

–

–

150

mV

Sleep Mode Quiescent Current

VCC = 14 V, ENABLE1 = ENABLE2 = 0 V

0

0.2

10.0

µA

Quiescent Current

VCC = 14 V, IOUT1 = 1.0 A, IOUT2 = 250 mA

–

–

30

mA

Dropout Voltage

IOUT1 = 250 mA IOUT1 = 1.0 A

–

– –

1.2 1.5

V V

Quiescent Bias Current

IOUT1 = 5.0 mA, ENABLE2 = 0 V, VCC = 14 V, IQ = ICC – IOUT1 IOUT1 = 1.0 A, ENABLE2 = 0 V, VCC = 14 V, IQ = ICC – IOUT1

–

–

10

mA

–

–

22

mA

Ripple Rejection

f = 120 Hz, VCC = 14 V with 1.0 VPP AC, COUT = 0 µF f = 10 kHz, VCC = 14 V with 1.0 VPP AC, COUT = 0 µF f = 20 kHz, VCC = 14 V with 1.0 VPP AC, COUT = 0 µF

– – –

90 74 68

– – –

dB dB dB

Current Limit

VCC = 16 V

1.1

–

2.5

A

Overshoot Voltage

5.0 mA ≤ IREG1 ≤ 1.0 A

–

–

6.0

V

Output Noise

10 Hz – 100 kHz

–

300

–

µVrms

Output Voltage

IOUT2 = 250 mA

4.75

5.00

5.25

V

Line Regulation

7.0 V ≤ VCC ≤ 26 V

–

–

40

mV

Load Regulation

5.0 mA ≤ IOUT2 ≤ 250 mA

–

–

100

mV

Dropout Voltage

IOUT2 = 5.0 mA IOUT2 = 250 mA

–

– –

2.2 2.5

V V

Quiescent Bias Current

IOUT2 = 5.0 mA, ENABLE1 = 0 V, VCC = 14 V, IQ = ICC – IOUT2 IOUT2 = 250 mA, ENABLE1 = 0 V, VCC = 14 V, IQ = ICC – IOUT2

–

–

7.0

mA

–

–

8.0

mA

Ripple Rejection

f = 120 Hz, VCC = 14 V with 1.0 VPP AC, COUT = 0 µF f = 10 kHz, VCC = 14 V with 1.0 VPP AC, COUT = 0 µF f = 20 kHz, VCC = 14 V with 1.0 VPP AC, COUT = 0 µF

– – –

90 75 67

– – –

dB dB dB

Current Limit

VCC = 16 V

270

–

600

mA

Overshoot Voltage

5.0 mA ≤ IREG2 ≤ 250 mA

–

–

4.3

V

Output Noise

10 Hz – 100 kHz

–

170

–

µVrms

–150

–

150

µA


ENABLE Function (ENABLE) Input Current

VCC = 14 V, 0 V ≤ ENABLE ≤ 5.5 V

Input Voltage

Low High

0 2.0

– –

0.8 5.0

V V

Human Body Model

±2.0

±4.0

–

kV

24

–

30

V

150

180

–

°C

–

30

–

°C

Protection Circuitry ESD Threshold Overvoltage Shutdown Thermal Shutdown Thermal Hysteresis

– Guaranteed by Design –


CS8371 PACKAGE PIN DESCRIPTION PACKAGE LEAD # 7 Lead TO–220

LEAD SYMBOL

1

ENABLE1

ENABLE control for the 8.0 V, 1.0 A output.

2

ENABLE2

ENABLE control for the 5.0 V, 250 mA output.

3

VOUT2

4

GND

5

Sense

6

VCC

Supply voltage, usually from battery.

7

VOUT1

8.0 V ±5.0%, 1.0 A regulated output.

FUNCTION

5.0 V ±5.0%, 250 mA regulated output. Ground. Sense feedback for the primary 8.0 V output.

TYPICAL PERFORMANCE CHARACTERISTICS 8.05 8.04

5.00 VIN = 14 V IOUT = 1.0 A

Output Voltage (V)

Output Voltage (V)

8.03 8.02 8.01 8.00 7.99 7.98

4.95 VIN = 14 V IOUT = 250 A

4.90

7.97 7.96 7.95

4.85

–40 –20

0

20

40

60

80

100

120

140

–40 –20

0

20

40

60

80

100 120



Figure 2. Regulator 1 Output Voltage

Figure 3. Regulator 2 Output Voltage

2.0

140

2.5

1.8 2.0 Dropout Voltage (V)

Dropout Voltage (V)

1.6 1.4 1.2

–40°C

1.0

85°C

0.8 0.6

25°C

–40°C

1.5

85°C 25°C

1.0

0.5

0.4 0.2 0

0 0

100 200 300 400 500 600

0

700 800 900 1000

50

100

150

200

Output Current (mA)

Output Current (mA)

Figure 4. Regulator 1 Dropout Voltage

Figure 5. Regulator 2 Dropout Voltage


250

CS8371 10

10 VIN = 14 V TA = 25°C

8 7 6 5 4 3 2

0

7 6 5 4 3 2

0 0

1

2

3

0

300

400

Figure 6. Regulator 1 Current Limit

Figure 7. Regulator 2 Current Limit

500

1.0 Enable 1 = 5.0 V Enable 2 = 5.0 V VIN = 14 V IOUT1 = 1.0 A IOUT2 = 250 mA

7.5

0.9 Quiescent Current (µA)

8.0

7.0 6.5 6.0 5.5 5.0

0.8

Enable 1 = 0 V Enable 2 = 0 V VIN = 14 V

0.7 0.6 0.5 0.4 0.3 0.2 0.1

4.5

0

4.0 –20

0

20

40

60

80

–40

–20

0

20

40

60





80

4.0

6.0 Enable 1 = 5.0 V Enable 2 = 0 V VIN = 14 V

Enable 1 = 0 V Enable 2 = 5.0 V VIN = 14 V


5.5

200

Reg 2 Output Current (mA)

8.5

–40

100

Reg 1 Output Current (A)

9.0

Quiescent Current (mA0

8

1

1


VIN = 14 V TA = 25°C

9 Reg 2 Output Voltage (V)

Reg 1 Output Voltage (V)

9

5.0 4.5 IOUT = 5.0 mA

IOUT = 1.0 A

4.0 3.5

3.6 3.4 3.2

IOUT = 250 mA

IOUT = 5.0 mA

3.0 2.8 2.6 2.4 2.2

3.0

–40

–20

0

20

40

60

2.0

80

–40

–20

0

20

40

60

80



Figure 10. Regulator 1 Quiescent Current

Figure 11. Regulator 2 Quiescent Current


CS8371 8.020

5.02 VIN = 14 V

8.015

5.01

8.010

5.00

8.005

Output Voltage (V)

Output Voltage (V)

VIN = 14 V

–40°C 85°C

8.000 25°C

7.995

4.97

7.985

4.95 0

200

250

1

2

3

4

5

6

7

8

9

10

11


Figure 13. Regulator 2 Load Regulation

8 7 6 5 4 3 2 1 0 5 4 3 2 1 0

12

COUT = 0 µF TA = 25°C IOUT = 5.0 mA

0

1

2

3

4

5

6

7

8

9

10

Time (µs)

Time (µs)

Figure 14. Regulator 1 Startup

Figure 15. Regulator 2 Startup

16 14 12 10 0

150

Figure 12. Regulator 1 Load Regulation

COUT = 0 µF TA = 25°C

2 1 0 –1 –2

100

Output Current (mA)

COUT = 0 µF TA = 25°C IOUT = 5.0 mA

0

50

Output Current (mA)

Enable 2 (V)

Enable 1 (V)

5 4 3 2 1 0

–40°C

4.94 100 200 300 400 500 600 700 800 900 1000

Input Voltage (V) Output Voltage Deviation (V)


8 7 6 5 4 3 2 1 0

85°C

4.98

4.96

0

Input Voltage (V) Output Voltage Deviation (V)

4.99

7.990

7.980

25°C

100

200

300

400

500

600

11

COUT = 0 µF TA = 25°C

0.6 0.4 0.2 0 –0.2 –0.4 –0.6

16 14 12 10 0

100

200

300

400

500

Time (ns)

Time (ns)

Figure 16. Regulator 1 Line Transient Response

Figure 17. Regulator 2 Line Transient Response


12

600

VIN = 14 V COUT = 0 µF TA = 25°C

3 2 1 0 –1 –2 –3

1000 5 0

5

10

15

20

25

30

VIN = 14 V COUT = 0 µF TA = 25°C

+500

0 –500

250 5 0

5

10

15

20

25

Time (µs)

Time (µs)

Figure 18. Regulator 1 Load Transient Response

Figure 19. Regulator 2 Load Transient Response

TA = 25°C VIN = 14 V COUT = 0 µF

80

60

30

TA = 25°C VIN = 14 V COUT = 0 µF


100

80

60

40

40

20

20 1

10

100

1k

10k

100k

1M

1

10

100

1k

10k

100k

Frequency (Hz)

Frequency (Hz)

Figure 20. Regulator 1 Ripple Rejection

Figure 21. Regulator 2 Ripple Rejection

5

Output Capacitor ESR (Ω)


Load Current (mA) Output Voltage Deviation (mV)

Load Current (mA) Output Voltage Deviation (V)

CS8371

TA = 25°C VIN = 14 V RESR ≤ 1.6 Ω IOUT = 5.0 mA to 1.0 A

1 Unstable Region

0 .01

0.1

1

10

100

1000

Output Capacitor Size (µF)

Figure 22. Regulator 1 Stability


1M

CS8371 DEFINITION OF TERMS Load Regulation – The change in output voltage for a change in load current at constant chip temperature. Long Term Stability – Output voltage stability under accelerated life–test conditions after 1000 hours with maximum rated voltage and junction temperature. Output Noise Voltage – The rms AC voltage at the output, with constant load and no input ripple, measured over a specified frequency range. Quiescent Current – The part of the positive input current that does not contribute to the positive load current. The regulator ground lead current. Ripple Rejection – The ratio of the peak–to–peak input ripple voltage to the peak–to–peak output ripple voltage. Temperature Stability of VOUT – The percentage change in output voltage for a thermal variation from room temperature to either temperature extreme.

Dropout Voltage – The input–output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100 mV from the nominal value obtained at 14 V input, dropout voltage is dependent upon load current and junction temperature. Current Limit – Peak current that can be delivered to the output. Input Voltage – The DC voltage applied to the input terminals with respect to ground. Input Output Differential – The voltage difference between the unregulated input voltage and the regulated output voltage for which the regulator will operate. Line Regulation – The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected.

C1 * 0.1 µF

ENABLE1

VOUT1

8.0 V

CS8371

Control

VIN

5.0 V

ENABLE2

VOUT2

Tuner IC

GND

* C1 is required if the regulator is far from the power source filter.

Figure 23. Applications Circuit

APPLICATION NOTES load capacitor value, ESR (Equivalent Series Resistance) and board layout parasitics all can create oscillations if not properly accounted for. NOCAP is an ON Semiconductor exclusive output stage which internally compensates the LDO regulator over temperature, load and line variations without the need for an expensive external capacitor. It incorporates high gain (>80 dB) and large unity gain bandwidth (>100 kHz) while maintaining many of the characteristics of a single–pole amplifier (large phase margin and no overshoot). NOCAP is ideally suited for slow switching or steady loads. If the load displays large transient current requirements, such as with high frequency microprocessors, an output storage capacitor may be needed. Some large capacitor and small capacitor ESR values at the output may

With seperate control of each output channel, the CS8371 is ideal for applications where each load must be switched independently. In an automotive radio, the 8.0 V output drives the displays and tape drive motors while the 5.0 V output supplies the Tuner IC and memory. Stability Considerations/NOCAP

Normally a low dropout or quasi–low dropout regulator (or any type requiring a slow lateral PNP in the control loop) necessitates a large external compensation capacitor at the output of the IC. The external capacitor is also used to curtail overshoot, determine startup delay time and load transient response. Traditional LDO regulators typically have low unity gain bandwidth, display overshoot and poor ripple rejection. Compensation is also an issue because the high frequency


CS8371 cause small signal oscillations at the output. This will depend on the load conditions. With these types of loads, a traditional output stage may be better suited for proper operation. Output 1 employs NOCAP. Refer to the plots in the Typical Performance Characteristics section for appropriate output capacitor selections for stability if an external capacitor is required by the switching characteristics of the load. Output 2 has a Darlington NPN–type output structure and is inherently stable with any type of capacitive load or no capacitor at all.

In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IIN

SMART REGULATOR

VIN

Control Features


IOUT1 VOUT1

IOUT2 VOUT2

IQ

The maximum power dissipation for a dual output regulator (Figure 24) is Figure 24. Dual Output Regulator With Key Performance Parameters Labeled.


Heat Sinks

where: VIN(max) is the maximum input voltage, VOUT1(min) is the minimum output voltage from VOUT1, VOUT2(min) is the minimum output voltage from VOUT2, IOUT1(max) is the maximum output current, for the application, IOUT2(max) is the maximum output current, for the application, and IQ is the quiescent current the regulator consumes at IOUT(max).

A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RΘJA: RJA + RJC ) RCS ) RSA



150°C * TA PD

(3)


(2)

The value of RΘJA can be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. PACKAGE THERMAL DATA Parameter

TO–220 SEVEN LEAD

Unit

RΘJC

Typical

2.4

°C/W

RΘJA

Typical

50

°C/W


"2 ,*# +',# $. ,*# +'## $ ! The CS8391 is a precision, dual 5.0 V micropower linear voltage regulator. The switched primary output (VOUT1) supplies up to 250 mA while the secondary (VOUT2) is capable of supplying 100 mA. Both outputs have a maximum dropout voltage of 600 mV and low reverse current. Quiescent current drain is typically 150 µA when supplying 100 µA from each output. The ENABLE input provides logic level control of the primary output. With the primary output disabled, quiescent current drain is typically 100 µA when supplying 100 µA from the secondary output. The CS8391 is extremely robust with protection provided for reverse battery, short circuit, and overtemperature on both outputs. The CS8391 is available in a 5–lead D2PAK. Features • 5.0 V/250 mA Primary Output • 5.0 V/100 mA Secondary Output • 3.0% Tolerance, Both Outputs • ON/OFF Control for Primary Output • Low Quiescent Current Drain (100 µA VOUT2) • Low Reverse Current • Protection Features – Reverse Battery (–15 V) – Short Circuit – Overtemperature

http://onsemi.com


1 5



CS8391 AWLYWW




Package

Shipping

CS8391YDP5

D2PAK, 5–PIN

50 Units/Rail

CS8391YDPR5

D2PAK, 5–PIN

750 Tape & Reel




913


CS8391

Primary Output

VOUT1 (250 mA)

VIN * ENABLE

+ –

VOUT1SENSE

Current Limit

1.2 V

+ –

*Note: Internally connected on 5 leaded package.

Bandgap Reference

Thermal Shutdown Secondary Output

VOUT2 (100 mA) *

Current Limit

VOUT2SENSE

+ –

GND



Value

Unit

–15 to 45

V

Internally Limited

–


–40 to +125

°C


–40 to +150

°C


–55 to +150

°C

4.0

kV

260 peak 230 peak

°C °C

Input Voltage Power Dissipation


Wave Solder (through hole styles only)(Note 1) Reflow (SMD styles only) (Note 2)

1. 10 second maximum 2. 60 second maximum above 183°C *The maximum package power dissipation must be observed.


CS8391 ELECTRICAL CHARACTERISTICS: (6.0 V ≤ VIN ≤ 26 V, IOUT1 = IOUT2 = 100 µA, –40°C ≤ TC ≤ 125°C, –40°C ≤ TJ ≤ 150°C; unless otherwise specified.)

Test Conditions

Characteristic

Min

Typ

Max

Unit

4.85

5.00

5.15

V


100 µA ≤ IOUT1 ≤ 250 mA

Dropout Voltage


– –

400 100

600 150

mV mV

Line Regulation

6.0 V ≤ VIN ≤ 26 V

–

5.0

50

mV

Load Regulation

1.0 mA ≤ IOUT1 ≤ 250 mA, VIN = 14 V

–

5.0

50

mV

Quiescent Current


–

22

50

mA

Ripple Rejection

f = 120 Hz, IOUT1 = 125 mA, 7.0 V ≤ VIN ≤ 17 V

60

70

–

dB

260

400

–

mA

Current Limit

–


VOUT1 = 0 V, VIN = 16 V

25

–

–

mA

Reverse Current

VOUT1 = 5.0 V, VIN = 0 V

–

100

1500

µA


100 µA ≤ IOUT1 ≤ 100 mA

4.85

5.00

5.15

V

Dropout Voltage


–

400 100

600 150

mV mV

Line Regulation

6.0 V ≤ VIN ≤ 26 V

–

5.0

50

mV

Load Regulation

100 µA ≤ IOUT2 ≤ 100 mA, VIN = 14 V

–

5.0

50

mV

Quiescent Current

ENABLE = LOW, VIN = 12.8 V ENABLE = HIGH, VIN = 16 V, IOUT2 = 100 mA

– –

100 8.0

150 25

µA mA

Ripple Rejection

f = 120 Hz; IOUT2 = 50 mA, 7.0 V ≤ VIN ≤ 17 V

60

70

–

dB

105

200

–

mA


Current Limit

–


VOUT2 = 0 V, VIN = 16 V, IOUT1 = 0 A

25

–

–

mA

Reverse Current

VOUT2 = 5.0 V, VIN = 0 V

–

100

250

µA



– 2.0

1.2 1.2

0.8 –

V V

Input Bias Current


–2.0

0

2.0

µA

Note 3

150

180

–

°C

Protection Circuits Overtemperature Threshold 3. Guaranteed by design.


LEAD SYMBOL

1

VIN

2

VOUT1

3

GND

4

VOUT2

5

ENABLE





14 V

ENABLE

2.0 V 0.8 V

26 V

14 V

3.0 V

5.0 V

5.0 V

5.0 V

5.0 V

5.0 V

5.0 V

2.4 V VOUT1

0V

0V 5.0 V

VOUT2 5.0 V

System Condition

5.0 V

5.0 V

0V 5.0 V

0V 5.0 V

5.0 V

2.4 V 0V

Turn On

Load Dump

Low VIN


VOUT2 Short Circuit

Thermal Shutdown

Turn Off




The CS8391 is a micropower dual 5.0 V regulator. All bias required to operate the internal circuitry is derived from the standby output, VOUT2. If this output experiences an over current situation and collapses, then VOUT1 will also collapse (see Figure 2). If there is critical circuitry that must remain active under most conditions it should be connected to VOUT2. Any circuitry that is likely to be subjected to a short circuit, e.g., circuitry outside the module, should be connected to VOUT1. External Capacitors



CS8391 ENABLE

IIN



Heat Sinks


The value of RΘJA can be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heat sink will be required.


VCC

VOUT2

VIN

C2**

C1 * CS8391

22 µF ESR < 8 Ω

mP


C3**

Load

(3)

where: RΘJC = the junction–to–case thermal resistance, RΘCS = the case–to–heat sink thermal resistance, and RΘSA = the heat sink–to–ambient thermal resistance.

(2)

VBATT

VOUT2


Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated:

0.1 µF

IOUT2

IQ


150°C * TA PD

VOUT1

Control Features


RJA +

IOUT1

SMART REGULATOR

VIN

ENABLE

I/O GND

GND





D2PAK, 5–PIN

Unit

RΘJC

Typical

2.4

°C/W

RΘJA

Typical

10–50*

°C/W



- "*" +',# $. ,*# +'## $ ! The CS8481 is a precision, dual micropower linear voltage regulator. The switched 3.3 V primary output (VOUT1) supplies up to 250 mA while the secondary 5.0 V (VOUT2) is capable of supplying 100 mA. Both outputs have a maximum dropout voltage of 600 mV and low reverse current. Quiescent current drain is typically 150 µA when supplying 100 µA from each output. The ENABLE input provides logic level control of the primary output. With the primary output disabled, quiescent current drain is typically 100 µA when supplying 100 µA from the secondary output. The CS8481 is extremely robust with protection provided for reverse battery, short circuit, overvoltage, and overtemperature on both outputs. The CS8481 is available in a 5–lead D2PAK. Features • 3.3 V/250 mA Primary Output • 5.0 V/100 mA Secondary Output • 3.0% Tolerance, Both Outputs • ON/OFF Control for Primary Output • Low Quiescent Current Drain (100 µA VOUT2) • Low Reverse Current • Protection Features – Reverse Battery (–15 V) – 74 V Peak Transient Voltage – Short Circuit – Overtemperature – Overvoltage (34 V)

http://onsemi.com


1 5



CS8481 AWLYWW




Package

Shipping

CS8481YDP5

D2PAK, 5–PIN

50 Units/Rail

CS8481YDPR5

D2PAK, 5–PIN

750 Tape & Reel




919


CS8481

Primary Output

VOUT1 (3.3 V)

VIN

ENABLE

+ –

VOUT1SENSE

Current Limit + –

Bandgap Reference

Overvoltage Shutdown Thermal Shutdown Secondary Output

VOUT2 (5.0 V)

VOUT2SENSE

Current Limit + –

Pwr GND

GND



Value

Unit

30 –15 74

V V V

10

V

Internally Limited

–


–40 to +150

°C


–55 to +150

°C

4.0

kV

230 peak

°C

Input Voltage (VIN)

Operating Range Reverse Battery Peak Transient Voltage (60 V Load Dump @ 14 V VIN)

ENABLE Power Dissipation


Reflow (SMD styles only) (Note 1)



CS8481 ELECTRICAL CHARACTERISTICS: (6.0 V ≤ VIN ≤ 26 V, IOUT1 = IOUT2 = 100 µA, –40°C ≤ TA ≤ 125°C, –40°C ≤ TC ≤ 125°C; unless otherwise specified.)

Test Conditions

Characteristic

Min

Typ

Max

Unit

3.2

3.3

3.4

V


100 µA ≤ IOUT1 ≤ 250 mA

Line Regulation

6.0 V ≤ VIN ≤ 26 V

–

5.0

50

mV

Load Regulation

1.0 mA ≤ IOUT1 ≤ 250 mA, VIN = 14 V

–

5.0

50

mV

Quiescent Current


–

22

50

mA

Ripple Rejection

f = 120 Hz, IOUT1 = 125 mA, 7.0 V ≤ VIN ≤ 17 V

60

70

–

dB

Current Limit

9.0 V ≤ VIN ≤ 26 V

260

400

–

mA


VOUT1 = 0 V, VIN = 16 V

25

–

–

mA

Reverse Current

VOUT1 = 3.3 V, VIN = 0 V

–

100

1500

µA


100 µA ≤ IOUT2 ≤ 100 mA

4.85

5.00

5.15

V

Dropout Voltage


–

400 100

600 150

mV mV

Line Regulation

6.0 V ≤ VIN ≤ 26 V

–

5.0

50

mV

Load Regulation

100 µA ≤ IOUT2 ≤ 100 mA, VIN = 14 V

–

5.0

50

mV

Quiescent Current

ENABLE = LOW, VIN = 12.8 V ENABLE = HIGH, VIN = 16 V, IOUT2 = 100 mA

– –

100 8.0

150 30

µA mA

Ripple Rejection

f = 120 Hz; IOUT2 = 10 mA, 7.0 V ≤ VIN ≤ 17 V

60

70

–

dB

Current Limit

9.0 V ≤ VIN ≤ 26 V

105

200

–

mA


VOUT2 = 0 V, VIN = 16 V, IOUT1 = 0 A

25

–

–

mA

Reverse Current

VOUT2 = 5.0 V, VIN = 0 V

–

100

250

µA




– 2.0

1.2 1.2

0.8 –

V V

Input Bias Current


–2.0

0

2.0

µA

Note 2

150

180

–

°C

30

34

38

V

Protection Circuits Overtemperature Threshold Overvoltage Shutdown

–

2. Guaranteed by Design.


LEAD SYMBOL

1

VIN

2

VOUT1

3

GND

4

VOUT2

5

ENABLE





14 V

ENABLE

2.0 V 0.8 V

30 V

34 V

3.3 V

14 V

3.0 V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

2.4 V VOUT1

0V

0V 5.0 V

VOUT2 5.0 V

System Condition

5.0 V

5.0 V

0V 5.0 V

0V 5.0 V

5.0 V

2.4 V 0V

Turn On

Load Dump

Low VIN


VOUT2 Short Circuit

Thermal Shutdown

Turn Off




The CS8481 is a micropower dual regulator. All bias required to operate the internal circuitry is derived from the standby output, VOUT2. If this output experiences an over current situation and collapses, then VOUT1 will also collapse (see Figure 2). If there is critical circuitry that must remain active under most conditions it should be connected to VOUT2. Any circuitry that is likely to be subjected to a short circuit, e.g., circuitry outside the module, should be connected to VOUT1. External Capacitors



CS8481 ENABLE

IIN



Heat Sinks


The value of RΘJA can be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.


VCC

VOUT2

VIN

C2**

C1 * CS8281

22 µF ESR < 8 Ω

mP


C3**

Load

(3)


(2)

VBATT

VOUT2


Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated:

0.1 µF

IOUT2

IQ


150°C * TA PD

VOUT1

Control Features


RJA +

IOUT1

SMART REGULATOR

VIN

ENABLE

I/O GND

GND





D2PAK, 5–PIN

Unit

RΘJC

Typical

2.4

°C/W

RΘJA

Typical

10–50*

°C/W



+,# ,# $ 0 !. 3. %. 4 The NCV8501 is a family of precision micropower voltage regulators. Their output current capability is 150 mA. The family has output voltage options for adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, and 10 V. The output voltage is accurate within ± 2.0% with a maximum dropout voltage of 0.6 V at 150 mA. Low quiescent current is a feature drawing only 70 µA with a 100 µA load. This part is ideal for any and all battery operated microprocessor equipment. Microprocessor control logic includes an active RESET (with DELAY), and a flag monitor which can be used to provide an early warning signal to the microprocessor of a potential impending RESET signal. The use of the flag monitor allows the microprocessor to finish any signal processing before the RESET shuts the microprocessor down. The active RESET circuit includes hysteresis, and operates correctly at an output voltage as low as 1.0 V. The RESET function is activated during the power up sequence or during normal operation if the output voltage drops outside the regulation limits. The regulator is protected against reverse battery, short circuit, and thermal overload conditions. The device can withstand load dump transients making it suitable for use in automotive environments. The device has also been optimized for EMC conditions.

http://onsemi.com

8 1


SO–14 PD SUFFIX CASE 751A

14 1

16 1

SOIC 16 LEAD WIDE BODY EXPOSED PAD PDW SUFFIX CASE 751R



Features Output Voltage Options: Adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, 10 V ± 2.0% Output Low 70 µA Quiescent Current Fixed or Adjustable Output Voltage Active RESET ENABLE 150 mA Output Current Capability Fault Protection – +60 V Peak Transient Voltage – –15 V Reverse Voltage – Short Circuit – Thermal Overload • Early Warning through FLAG/MON Leads

• • • • • • • •

This document contains information on a new product. Specifications and information herein are subject to change without notice.  Semiconductor Components Industries, LLC, 2002


925

Publication Order Number: NCV8501/D

NCV8501 Series PIN CONNECTIONS, ADJUSTABLE OUTPUT SO–8 VIN

1

8

MON ENABLE

VOUT

VADJ VOUT NC NC NC NC VIN NC

VADJ FLAG

NC

GND

SOW–16 E PAD 1 16 FLAG MON NC GND NC NC NC ENABLE

PIN CONNECTIONS, FIXED OUTPUT SO–8

SO–14 8

MON ENABLE

VOUT

GND

VIN

14

NC DELAY NC NC NC ENABLE RESET

FLAG RESET

DELAY

VBAT

1

MON VIN NC GND NC VOUT FLAG

FLAG VOUT NC NC NC NC VIN MON

SOW–16 E PAD 1 16 RESET NC NC GND NC NC DELAY ENABLE

VOUT

VDD 10 µF

10 µF

NCV8501 Delay

RFLG 10 k

Microprocessor

VIN

1

RRST 10 k

MON

CDELAY

ENABLE

VADJ (Adjustable Output Only) RESET

FLAG

I/O

GND



I/O

NCV8501 Series MAXIMUM RATINGS*{ Rating

Value

Unit

–15 to 45

V


60

V

Operating Voltage

45

V

Input Voltage Range (RESET, FLAG)

–0.3 to 10

V

Input Voltage Range (MON)

–0.3 to 45

V

Input Voltage Range (ENABLE)

60

V


2.0

kV

Junction Temperature, TJ

–40 to +150

°C

Storage Temperature, TS

–55 to 150

°C


45 165

°C/W °C/W


30 115

°C/W °C/W

Package Thermal Resistance, SOW–16 E PAD: Junction–to–Case, RθJC Junction–to–Ambient, RθJA

1.0 36

°C/W °C/W

230 peak

°C

VIN (DC)



1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. †During the voltage range which exceeds the maximum tested voltage of VIN, operation is assured, but not specified. Wider limits may apply. Thermal dissipation must be observed closely.

ELECTRICAL CHARACTERISTICS (IOUT = 1.0 mA, ENABLE = TBD, –40°C ≤ TA ≤ 125°C; –40°C ≤ TJ ≤ 150°C; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

Output Stage Output Voltage for 2.5 V Option (4.5 V ≤ VIN ≤ 26 V)


2.450 2.425

2.5 2.5

2.550 2.575

V V

Output Voltage for 3.3 V Option (4.5 V ≤ VIN ≤ 26 V)


3.234 3.201

3.3 3.3

3.366 3.399

V V



4.90 4.85

5.0 5.0

5.10 5.15

V V


12 V < VIN < 16 V, 100 µA ≤ IOUT ≤ 150 mA 9.0 V < VIN < 16 V, 100 µA ≤ IOUT ≤ 150 mA

7.84 7.76

8.0 8.0

8.16 8.24

V V

Output Voltage for 10 V Option (11 V ≤ VIN ≤ 26 V)

14 V < VIN < 16 V, 100 µA ≤ IOUT ≤ 150 mA 11 V < VIN < 16 V, 100 µA ≤ IOUT ≤ 150 mA

9.8 9.7

10 10

10.2 10.3

V V

Dropout Voltage (VIN – VOUT) (5.0 V, 8.0 V, 10 V Options Only)


– –

400 100

600 150

mV mV

Load Regulation

VIN = 14 V, 5.0 mA ≤ IOUT ≤ 150 mA

–

5.0

30

mV

Line Regulation

[VOUT(typ) + 1.0] < V < 26 V, IOUT = 1.0 mA

–

5.0

40

mV


IOUT = 100 µA, VIN = 12 V, Delay = 3.0 V, MON = 3.0 V IOUT = 75 mA, Delay = 3.0 V, MON = 3.0 V IOUT ≤ 150 mA, Delay = 3.0 V, MON = 3.0 V

– – –

70 6.0 12

TBD 9.0 19

µA mA mA


ENABLE = 0 V

–

12

25

µA


NCV8501 Series ELECTRICAL CHARACTERISTICS (continued) (IOUT = 1.0 mA, ENABLE = TBD, –40°C ≤ TA ≤ 125°C; –40°C ≤ TJ ≤ 150°C; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

–

160

300

–

mA

Output Stage Current Limit Short Circuit Output Current

VOUT = 0 V

40

190

–

mA

Thermal Shutdown

(Guaranteed by Design)

150

180

–

°C

Reset Function (RESET) RESET Threshold for 2.5 V Option HIGH (VRH) LOW (VRL)

4.5 V ≤ VIN ≤ 26 V (Note 2) VOUT Increasing VOUT Decreasing

2.225 2.200

2.350 2.300

2.475 2.400

V V

RESET Threshold for 3.3 V Option HIGH (VRH) LOW (VRL)


2.937 2.904

3.102 3.036

3.267 3.168

V V



4.45 4.40

4.70 4.60

4.95 4.80

V V



7.12 7.04

7.52 7.36

7.92 7.68

V V

RESET Threshold for 10 V Option HIGH (VRH) LOW (VRL)


8.90 8.80

9.40 9.20

9.90 9.60

V V

RESET Hysteresis

(HIGH – LOW)

–

100

–

mV

Output Voltage Low (VRLO) Low (VR(PEAK))

1.0 V ≤ VOUT ≤ VRL, RRESET = 10 k VOUT, Power up, Power down

– –

0.1 0.6

0.4 1.0

V V

1.4

1.8

2.2

V

–

–

0.1

V

Delay Switching Threshold (VDT)

–

Reset Delay Low Voltage

VOUT < RESET Threshold Low(min)


Delay = 1.0 V, VOUT > VRH

2.0

3.0

5.0

µA

Delay Discharge Current

Delay = 1.0 V, VOUT = 1.5 V

10

–

–

mA

FLAG/Monitor Monitor Threshold

–

TBD

1.28

TBD

V

Hysteresis

–

20

100

200

mV

–1.0

0.1

1.0

µA

–

0.1

0.4

V

TBD

1.28

TBD

V

–

–20

TBD

µA

– TBD

– –

TBD –

V V

–

–

TBD

µA

Input Current

VMON = 2.0 V

Output Saturation Voltage

VMON = 0 V, IFLAG = 1.0 mA

Voltage Adjust (Adjustable Output only) Threshold Input Current

– SENSE = 0 V

ENABLE Input Threshold

Low High

Input Current

ENABLE = 14 V

2. For VIN ≤ 4.5 V, a RESET = Low may occur with the output in regulation.


NCV8501 Series PACKAGE PIN DESCRIPTION, ADJUSTABLE OUTPUT Package Pin Number SO–8

SOW–16 E PAD

Pin Symbol

1

7

VIN

2

15

MON

3

9

ENABLE

4

3–6, 8, 10–12, 14

NC

5

13

GND

Ground. All GND leads must be connected to Ground.

6

16

FLAG

Open collector output from early warning comparator.

7

1

VADJ

Voltage Adjust. A resistor divider from VOUT to this lead sets the output voltage.

8

2

VOUT

±2.0%, 150 mA output.

NOTE:

Function Input Voltage. Monitor. Input for early warning comparator. If not needed connect to VOUT. ENABLE control for the IC. A high powers the device up. No connection.

Tentative pinout for SOW–16 E Pad.

PACKAGE PIN DESCRIPTION, FIXED OUTPUT Package Pin Number SO–8

SO–14

SOW–16 E PAD

Pin Symbol

1

13

7

VIN

2

14

8

MON

3

6

9

ENABLE

4

2

10

DELAY

5

11

13

GND

6

7

16

RESET

7

8

1

FLAG


8

9

2

VOUT

±2.0%, 150 mA output.

–

1, 3–5, 10, 12

3–6, 11, 12, 14, 15

NC

NOTE:

Function Input Voltage. Monitor. Input for early warning comparator. If not needed connect to VOUT. ENABLE control for the IC. A high powers the device up. Timing capacitor for RESET function. Ground. All GND leads must be connected to Ground. Active reset (accurate to VOUT ≥ 1.0 V)

No connection.

Tentative pinouts for SO–14 and SOW–16 E Pad. 5.0 V option only for SO–14.


NCV8501 Series VOUT

VIN Current Source (Circuit Bias)

ENABLE

IBIAS Current Limit Sense

+ + –

IBIAS + –

VBG

Error Amplifier RESET

VBG

+ –

2.0 V

Fixed Voltage only

Thermal Protection 3.0 µA Delay

IBIAS

Bandgap Reference VBG

VADJ VBG

20 k Adjustable Version only

GND

IBIAS +

FLAG

–

MON


CIRCUIT DESCRIPTION RESET Function

REGULATOR CONTROL FUNCTIONS The NCV8501 contains the microprocessor compatible control function RESET (Figure 3).

A RESET signal (low voltage) is generated as the IC powers up until VOUT is within 6.0% of the regulated output voltage, or when VOUT drops out of regulation,and is lower than 8.0% below the regulated output voltage. Hysteresis is included in the function to minimize oscillations. The RESET output is an open collector NPN transistor, controlled by a low voltage detection circuit. The circuit is functionally independent of the rest of the IC thereby guaranteeing that the RESET signal is valid for VOUT as low as 1.0 V.

VIN RESET Threshold

VOUT

Delay

Delay Threshold (VDT)

RESET Td

Td

Figure 3. Reset and Delay Circuit Wave Forms


NCV8501 Series ENABLE Function

will allow the microprocessor time to complete its present task before shutting down. This function is performed by a comparator referenced to the bandgap reference. The actual trip point can be programmed externally using a resistor divider to the input monitor (MON) (Figure 5).

The part stays in a low IQ sleep mode when the ENABLE pin is held low. The part has an internal pull down if the pin is left floating. This is intended for failure modes only. An external connection (active pulldown, resistor, or switch) for normal operation is recommended. The integrity of the ENABLE pin allows it to be tied directly to the battery line. It will withstand load dump potentials. VBAT

VBAT

VCC

NCV8501

VOUT

VIN

VOUT

VIN

NCV8501

MON

FLAG

RADJ

RESET

Delay

GND

µP

COUT I/O

RESET

ENABLE GND

Figure 5. Flag/Monitor Function Voltage Adjust

Figure 4. ENABLE Function

Figure 6 shows the device setup for a user configurable output voltage. The feedback to the VADJ pin is taken from a voltage divider referenced to the output voltage. The loop is balanced around the SENSE threshold (1.28 V typical).

Delay Function

The reset delay circuit provides a programmable (by an external capacitor) delay on the RESET output lead. The delay lead provides source current (typically 3.0 µA) to the external delay capacitor only when the output voltage, VOUT, has dropped below the reset threshold. Otherwise, the delay pin is always grounded through an internal NPN. If reset delay is not needed, this pin should be left open.

≈5.0 V

VOUT NCV8501

15 k

COUT

VADJ 5.1 k

FLAG/Monitor Function

An on–chip comparator is provided to perform an early warning to the microprocessor of a possible reset signal. The reset signal typically turns the microprocessor off instantaneously. This can cause unpredictable results with the microprocessor. The signal received from the FLAG pin

Figure 6. Adjustable Output Voltage

APPLICATION NOTES VIN

FLAG MONITOR Figure 7 shows the FLAG Monitor waveforms as a result of the circuit depicted in Figure 5. As the input voltage falls (VIN), the Monitor threshold is crossed. This causes the voltage on the FLAG output to go low sending a warning signal to the microprocessor that a RESET signal may occur in a short period of time. TWARNING is the time the microprocessor has to complete the function it is currently working on and get ready for the RESET shutdown signal.

MON Flag Monitor Ref. Voltage

RESET

FLAG

TWARNING

Figure 7. FLAG Monitor Circuit Waveform


NCV8501 Series SETTING THE DELAY TIME The delay time is controlled by the Reset Delay Low Voltage, Delay Switching Threshold, and the Delay Charge Current. The delay follows the equation: tDELAY +

CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR The maximum power dissipation for a single output regulator (Figure 9) is:

[CDELAY(Vdt * Reset Delay Low Voltage)] Delay Charge Current

PD(max) + [VIN(max) * VOUT(min)]IOUT(max) ) VIN(max)IQ

Example: Using CDELAY = 33 nF. Assume reset Delay Low Voltage = 0. Use the typical value for Vdt = 1.8 V. Use the typical value for Delay Charge Current = 3.0 µA. tDELAY +

where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated:

[33 nF(1.8 * 0)] + 19.8 ms 3.0 A

STABILITY CONSIDERATIONS The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 8 should work for most applications, however it is not necessarily the optimized solution. VIN

T RJA + 150°C * A PD

NCV8501

(2)

The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IOUT

IIN VIN

SMART REGULATOR

VOUT


VOUT

CIN* 0.1 µF

(1)

RRST

COUT** 10 µF


RESET

HEAT SINKS A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RΘJA:

*CIN required if regulator is located far from the power supply filter **COUT required for stability. Capacitor must operate at minimum temperature expected



(3)

where: RΘJC = the junction–to–case thermal resistance, RΘCS = the case–to–heatsink thermal resistance, and RΘSA = the heatsink–to–ambient thermal resistance. RΘJC appears in the package section of the data sheet. Like RΘJA, it too is a function of package type. RΘCS and RΘSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. http://onsemi.com 932

NCV8501 Series ORDERING INFORMATION Device

Output Voltage

NCV8501DADJ NCV8501DADJR2 NCV8501PDWADJ

Adjustable

NCV8501PDWADJR2 NCV8501D25 NCV8501D25R2 NCV8501PDW25

25V 2.5

NCV8501PDW25R2 NCV8501D33 NCV8501D33R2 NCV8501PDW33

33V 3.3

NCV8501PDW33R2

Package

Shipping

SO–8

95 Units/Rail

SO–8

2500 Tape & Reel

SOW–16 Exposed Pad

46 Units/Rail


1000 Tape & Reel

SO–8

95 Units/Rail

SO–8

2500 Tape & Reel


46 Units/Rail


1000 Tape & Reel

SO–8

95 Units/Rail

SO–8

2500 Tape & Reel


46 Units/Rail


1000 Tape & Reel

NCV8501D50

SO–8

95 Units/Rail

NCV8501D50R2

SO–8

2500 Tape & Reel


46 Units/Rail


1000 Tape & Reel

NCV8501PD50

SO–14

55 Units/Rail

NCV8501PD50R2

SO–14

2500 Tape & Reel

NCV8501D80

SO–8

95 Units/Rail

NCV8501D80R2

SO–8

2500 Tape & Reel


46 Units/Rail


1000 Tape & Reel

SO–8

95 Units/Rail

SO–8

2500 Tape & Reel

NCV8501PDW50 NCV8501PDW50R2

NCV8501PDW80

50V 5.0

80V 8.0

NCV8501PDW80R2 NCV8501D100 NCV8501D100R2 10 V NCV8501PDW100


46 Units/Rail

NCV8501PDW100R2


1000 Tape & Reel


NCV8501 Series MARKING DIAGRAMS SO–8

SO–14

8

14 8501x ALYW

SOW–16 E PAD 16

NCV8501x AWLYWW

1

NCV8501x

1

AWLYYWW 1

x

= Voltage Ratings as Indicated Below: A = Adjustable 2 = 2.5 V 3 = 3.3 V 5 = 5.0 V 8 = 8.0 V 0 = 10 V A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week


+,# ,# $ 0 3. %.

4 The NCV8502 is a family of precision micropower voltage regulators. Their output current capability is 150 mA. The family has output voltage options for adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, and 10 V. The output voltage is accurate within ± 2.0% with a maximum dropout voltage of 0.6 V at 150 mA. Low quiescent current is a feature drawing only 70 µA with a 100 µA load. This part is ideal for any and all battery operated microprocessor equipment. Microprocessor control logic includes an active RESET (with DELAY), and a flag monitor which can be used to provide an early warning signal to the microprocessor of a potential impending RESET signal. The use of the flag monitor allows the microprocessor to finish any signal processing before the RESET shuts the microprocessor down. The active RESET circuit includes hysteresis, and operates correctly at an output voltage as low as 1.0 V. The RESET function is activated during the power up sequence or during normal operation if the output voltage drops outside the regulation limits. The reset threshold voltage can be decreased by the connection of external resistor divider to RADJ lead. The regulator is protected against reverse battery, short circuit, and thermal overload conditions. The device can withstand load dump transients making it suitable for use in automotive environments. The device has also been optimized for EMC conditions.

http://onsemi.com

8 1


SO–14 PD SUFFIX CASE 751A

14 1

16 1




Features • Output Voltage Options: Adjustable, 2.5 V, 3.3 V, 5.0 V, 8.0 V, 10 V • ± 2.0% Output • Low 70 µA Quiescent Current • Fixed or Adjustable Output Voltage • Active RESET • Adjustable Reset • 150 mA Output Current Capability • Fault Protection – +60 V Peak Transient Voltage – –15 V Reverse Voltage – Short Circuit – Thermal Overload • Early Warning through FLAG/MON Leads This document contains information on a new product. Specifications and information herein are subject to change without notice.



935


NCV8502 Series PIN CONNECTIONS, ADJUSTABLE OUTPUT SO–8 VIN

1

8

MON NC

VOUT

VADJ VOUT NC NC NC NC VIN NC

VADJ FLAG

NC

GND

SOW–16 E PAD 1 16 FLAG MON NC GND NC NC NC NC

PIN CONNECTIONS, FIXED OUTPUT SO–8

MON RADJ

1

VOUT

GND

VIN

14

RADJ DELAY NC NC NC NC RESET

FLAG RESET

DELAY

VBAT

SO–14 8

MON VIN NC GND NC VOUT FLAG

FLAG VOUT NC NC NC NC VIN MON

SOW–16 E PAD 1 16 RESET NC NC GND NC NC DELAY RADJ

VOUT

VDD 10 µF

10 µF

RADJ

NCV8502 Delay

RFLG 10 k

Microprocessor

VIN

1

RRST 10 k

MON

CDELAY VADJ (Adjustable Output Only) RESET

FLAG

I/O

GND



I/O

NCV8502 Series MAXIMUM RATINGS*{ Rating

Value

Unit

–15 to 45

V


60

V

Operating Voltage

45

V

Input Voltage Range (RESET, FLAG)

–0.3 to 10

V

Input Voltage Range (MON, VADJ)

–0.3 to 45

V

2.0

kV

Junction Temperature, TJ

–40 to +150

°C

Storage Temperature, TS

–55 to 150

°C


45 165

°C/W °C/W


30 115

°C/W °C/W


1.0 36

°C/W °C/W

230 peak

°C

VIN (DC)




1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. †During the voltage range which exceeds the maximum tested voltage of VIN, operation is assured, but not specified. Wider limits may apply. Thermal dissipation must be observed closely.

ELECTRICAL CHARACTERISTICS (IOUT = 1.0 mA, –40°C ≤ TA ≤ 125°C; –40°C ≤ TJ ≤ 150°C; unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit

Output Stage Output Voltage for 2.5 V Option (4.5 V ≤ VIN ≤ 26 V)


2.450 2.425

2.5 2.5

2.550 2.575

V V



3.234 3.201

3.3 3.3

3.366 3.399

V V



4.90 4.85

5.0 5.0

5.10 5.15

V V


12 V < VIN < 16 V, 100 µA ≤ IOUT ≤ 150 mA 9.0 V < VIN < 16 V, 100 µA ≤ IOUT ≤ 150 mA

7.84 7.76

8.0 8.0

8.16 8.24

V V

Output Voltage for 10 V Option (11 V ≤ VIN ≤ 26 V)

14 V < VIN < 16 V, 100 µA ≤ IOUT ≤ 150 mA 11 V < VIN < 16 V, 100 µA ≤ IOUT ≤ 150 mA

9.8 9.7

10 10

10.2 10.3

V V

Dropout Voltage (VIN – VOUT) (5.0 V, 8.0 V, 10 V Options Only)


– –

400 100

600 150

mV mV

Load Regulation

VIN = 14 V, 5.0 mA ≤ IOUT ≤ 150 mA

–

5.0

30

mV

Line Regulation

[VOUT(typ) + 1.0] < V < 26 V, IOUT = 1.0 mA

–

5.0

40

mV


IOUT = 100 µA, VIN = 12 V, Delay = 3.0 V, MON = 3.0 V IOUT = 75 mA, Delay = 3.0 V, MON = 3.0 V IOUT ≤ 150 mA, Delay = 3.0 V, MON = 3.0 V

– – –

70 6.0 12

TBD 9.0 19

µA mA mA


NCV8502 Series ELECTRICAL CHARACTERISTICS (continued) (IOUT = 1.0 mA, –40°C ≤ TA ≤ 125°C; –40°C ≤ TJ ≤ 150°C; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

–

160

300

–

mA

Output Stage Current Limit Short Circuit Output Current

VOUT = 0 V

40

190

–

mA

Thermal Shutdown

(Guaranteed by Design)

150

180

–

°C

Reset Function (RESET) RESET Threshold for 2.5 V Option HIGH (VRH) LOW (VRL)


2.225 2.200

2.350 2.300

2.475 2.400

V V



2.937 2.904

3.102 3.036

3.267 3.168

V V



4.45 4.40

4.70 4.60

4.95 4.80

V V



7.12 7.04

7.52 7.36

7.92 7.68

V V

RESET Threshold for 10 V Option HIGH (VRH) LOW (VRL)


8.90 8.80

9.40 9.20

9.90 9.60

V V

RESET Hysteresis

(HIGH – LOW)

–

100

–

mV

Output Voltage Low (VRLO) Low (VR(PEAK))

1.0 V ≤ VOUT ≤ VRL, RRESET = 10 k VOUT, Power up, Power down

– –

0.1 0.6

0.4 1.0

V V

1.4

1.8

2.2

V

–

–

0.1

V

2.0

3.0

5.0

µA

TBD

1.28

TBD

V

10

–

–

mA

Delay Switching Threshold (VDT)

–

Reset Delay Low Voltage

VOUT < RESET Threshold Low(min)


Delay = 1.0 V, VOUT > VRH

Reset Adjust Switching Voltage (VR(ADJ)) Delay Discharge Current

– Delay = 1.0 V, VOUT = 1.5 V

FLAG/Monitor Monitor Threshold

–

TBD

1.28

TBD

V

Hysteresis

–

20

100

200

mV

–1.0

0.1

1.0

µA

–

0.1

0.4

V

TBD

1.28

TBD

V

–

–20

TBD

µA

Input Current

VMON = 2.0 V

Output Saturation Voltage

VMON = 0 V, IFLAG = 1.0 mA

Voltage Adjust (Adjustable Output only) –

Threshold Input Current

SENSE = 0 V

2. For VIN ≤ 4.5 V, a RESET = Low may occur with the output in regulation.


NCV8502 Series PACKAGE PIN DESCRIPTION, ADJUSTABLE OUTPUT Package Pin Number SO–8

SOW–16 E PAD

Pin Symbol

1

7

VIN

2

15

MON

3, 4

3–6, 8–12, 14

NC

5

13

GND

Ground. All GND leads must be connected to Ground.

6

16

FLAG


7

1

VADJ

Voltage Adjust. A resistor divider from VOUT to this lead sets the output voltage.

8

2

VOUT

±2.0%, 150 mA output.

NOTE:

Function Input Voltage. Monitor. Input for early warning comparator. If not needed connect to VOUT. No connection.

Tentative pinout for SOW–16 E Pad.

PACKAGE PIN DESCRIPTION, FIXED OUTPUT Package Pin Number SO–8

SO–14

SOW–16 E PAD

Pin Symbol

1

13

7

VIN

2

14

8

MON

Monitor. Input for early warning comparator. If not needed connect to VOUT.

3

1

9

RADJ

Reset Adjust. If not needed connect to ground.

4

2

10

DELAY

5

11

13

GND

6

7

16

RESET

7

8

1

FLAG


8

9

2

VOUT

±2.0%, 150 mA output.

–

3–6, 10, 12

3–6, 11, 12, 14, 15

NC

NOTE:

Function Input Voltage.

Timing capacitor for RESET function. Ground. All GND leads must be connected to Ground. Active reset (accurate to VOUT ≥ 1.0 V)

No connection.

Tentative pinouts for SO–14 and SOW–16 E Pad. 5.0 V option only for SO–14.


NCV8502 Series VOUT

VIN Current Source (Circuit Bias) IBIAS Current Limit Sense

+ + –

RADJ

IBIAS + –

VBG

Error Amplifier RESET

VBG

+ –

2.0 V

Fixed Voltage only

Thermal Protection 3.0 µA Delay

IBIAS

Bandgap Reference VBG

VADJ VBG

20 k Adjustable Version only

GND

IBIAS +

FLAG

–

MON


CIRCUIT DESCRIPTION RESET Function

REGULATOR CONTROL FUNCTIONS The NCV8502 contains the microprocessor compatible control function RESET (Figure 3).

A RESET signal (low voltage) is generated as the IC powers up until VOUT is within 6.0% of the regulated output voltage, or when VOUT drops out of regulation,and is lower than 8.0% below the regulated output voltage. Hysteresis is included in the function to minimize oscillations. The RESET output is an open collector NPN transistor, controlled by a low voltage detection circuit. The circuit is functionally independent of the rest of the IC thereby guaranteeing that the RESET signal is valid for VOUT as low as 1.0 V.

VIN RESET Threshold

VOUT

Delay

Delay Threshold (VDT)

RESET Td

Td

Figure 3. Reset and Delay Circuit Wave Forms


NCV8502 Series Adjustable Reset Function

the microprocessor. The signal received from the FLAG pin will allow the microprocessor time to complete its present task before shutting down. This function is performed by a comparator referenced to the bandgap reference. The actual trip point can be programmed externally using a resistor divider to the input monitor (MON) (Figure 5).

The reset threshold can be made lower by connecting an external resistor divided to the RADJ lead from the VOUT lead, as displayed in Figure 4. This lead is grounded to select the default value of 4.6 V. to µP and System Power

VOUT

RADJ

VBAT

NCV8502

VCC

NCV8502 RRST

Delay

VOUT

VIN

RESET

COUT

to µP and RESET Port

CDELAY

MON

FLAG

RADJ

RESET

Delay

GND

µP

COUT I/O

RESET

Figure 5. Flag/Monitor Function Voltage Adjust

Figure 4. Adjustable RESET

Figure 6 shows the device setup for a user configurable output voltage. The feedback to the VADJ pin is taken from a voltage divider referenced to the output voltage. The loop is balanced around the SENSE threshold (1.28 V typical).

Delay Function

The reset delay circuit provides a programmable (by an external capacitor) delay on the RESET output lead. The delay lead provides source current (typically 3.0 µA) to the external delay capacitor only when the output voltage, VOUT, has dropped below the reset threshold. Otherwise, the delay pin is always grounded through an internal NPN. If reset delay is not needed, this pin should be left open.

≈5.0 V

VOUT NCV8502

15 k

COUT

VADJ 5.1 k

FLAG/Monitor Function

An on–chip comparator is provided to perform an early warning to the microprocessor of a possible reset signal. The reset signal typically turns the microprocessor off instantaneously. This can cause unpredictable results with

Figure 6. Adjustable Output Voltage

APPLICATION NOTES VIN

FLAG MONITOR Figure 7 shows the FLAG Monitor waveforms as a result of the circuit depicted in Figure 5. As the input voltage falls (VIN), the Monitor threshold is crossed. This causes the voltage on the FLAG output to go low sending a warning signal to the microprocessor that a RESET signal may occur in a short period of time. TWARNING is the time the microprocessor has to complete the function it is currently working on and get ready for the RESET shutdown signal.

MON Flag Monitor Ref. Voltage

RESET

FLAG

TWARNING

Figure 7. FLAG Monitor Circuit Waveform


NCV8502 Series SETTING THE DELAY TIME The delay time is controlled by the Reset Delay Low Voltage, Delay Switching Threshold, and the Delay Charge Current. The delay follows the equation: tDELAY +

CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR The maximum power dissipation for a single output regulator (Figure 9) is:

[CDELAY(Vdt * Reset Delay Low Voltage)] Delay Charge Current

PD(max) + [VIN(max) * VOUT(min)]IOUT(max) ) VIN(max)IQ

Example: Using CDELAY = 33 nF. Assume reset Delay Low Voltage = 0. Use the typical value for Vdt = 1.8 V. Use the typical value for Delay Charge Current = 3.0 µA. tDELAY +

where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated:

[33 nF(1.8 * 0)] + 19.8 ms 3.0 A

STABILITY CONSIDERATIONS The output or compensation capacitor helps determine three main characteristics of a linear regulator: start–up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (–25°C to –40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 8 should work for most applications, however it is not necessarily the optimized solution. VIN

T RJA + 150°C * A PD

NCV8502

(2)

The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. IOUT

IIN VIN

SMART REGULATOR

VOUT


VOUT

CIN* 0.1 µF

(1)

RRST

COUT** 10 µF


RESET

HEAT SINKS A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RΘJA:

*CIN required if regulator is located far from the power supply filter **COUT required for stability. Capacitor must operate at minimum temperature expected



(3)

where: RΘJC = the junction–to–case thermal resistance, RΘCS = the case–to–heatsink thermal resistance, and RΘSA = the heatsink–to–ambient thermal resistance. RΘJC appears in the package section of the data sheet. Like RΘJA, it too is a function of package type. RΘCS and RΘSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers. http://onsemi.com 942

NCV8502 Series ORDERING INFORMATION Device

Output Voltage

NCV8502DADJ NCV8502DADJR2 NCV8502PDWADJ

Adjustable

NCV8502PDWADJR2 NCV8502D25 NCV8502D25R2 NCV8502PDW25

25V 2.5


33V 3.3

NCV8502PDW33R2

Package

Shipping

SO–8

95 Units/Rail

SO–8

2500 Tape & Reel


46 Units/Rail


1000 Tape & Reel

SO–8

95 Units/Rail

SO–8

2500 Tape & Reel


46 Units/Rail


1000 Tape & Reel

SO–8

95 Units/Rail

SO–8

2500 Tape & Reel


46 Units/Rail


1000 Tape & Reel

NCV8502D50

SO–8

95 Units/Rail

NCV8502D50R2

SO–8

2500 Tape & Reel


46 Units/Rail


1000 Tape & Reel

NCV8502PD50

SO–14

55 Units/Rail

NCV8502PD50R2

SO–14

2500 Tape & Reel

NCV8502D80

SO–8

95 Units/Rail

NCV8502D80R2

SO–8

2500 Tape & Reel


46 Units/Rail


1000 Tape & Reel

SO–8

95 Units/Rail

SO–8

2500 Tape & Reel

NCV8502PDW50 NCV8502PDW50R2

NCV8502PDW80

50V 5.0

80V 8.0


10 V

NCV8502PDW100R2


46 Units/Rail


1000 Tape & Reel


NCV8502 Series MARKING DIAGRAMS SO–8

SO–14

8

14 8502x ALYW

SOW–16 E PAD 16

NCV8502x AWLYWW

NCV8502x AWLYYWW

1

1

1

x

= Voltage Ratings as Indicated Below: A = Adjustable 2 = 2.5 V 3 = 3.3 V 5 = 5.0 V 8 = 8.0 V 0 = 10 V A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week


+,# 5 . %. 5 & 6 http://onsemi.com

The NCV8508 is a precision micropower voltage regulator family. The part contains many of the required operational requirements for powering microprocessors. Its robustness makes it suitable for severe automotive environments. The devices low dropout voltage ensures operation of loads (i.e. microprocessors) when the battery voltage is low such as during the cranking cycle of an automobile. In addition to being a good fit for the automotive environment, the NCV8508 is ideal for use in battery operated, microprocessor controlled equipment because of its extremely low quiescent current.

MARKING DIAGRAMS 8 8 1


8508x ALYW 1 16

Features Output Voltage Options: 3.3 V or 5.0 V ±3.0% Output Voltage IOUT Up to 250 mA Quiescent Current Independent of Load Micropower Compatible Control Functions: – Wake Up – Watchdog – RESET • Low Dropout Voltage • Low Quiescent Current (100 µA typ) • Protection Features: – Thermal Shutdown – Short Circuit – 45 V Operation • Internally Fused Leads in SO–16L Package

• • • • •

16 1

NCV8508x


AWLYYWW

1 16 16 1


NCV8508x AWLYYWW 1

x

= Voltage Ratings as Indicated Below: 3 = 3.3 V 5 = 5.0 V A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week


This document contains information on a new product. Specifications and information herein are subject to change without notice.



945


NCV8508 Series PIN CONNECTIONS Delay

1

SO–16L 8

GND Sense

1

RESET

NC NC NC GND GND NC Sense VOUT

WAKE UP WDI

VOUT

VIN

VBAT

C1* 0.1 µF

16 Delay RESET WAKE UP GND GND WDI NC VIN

VOUT

VIN

C2 1.0 µF WDI

SOW–16 E PAD 1

VDD I/O

NCV8508 Delay

GND

RESET

RESET

WAKE UP

I/O

RDelay 120 k

16 Delay RESET WAKE UP NC NC WDI NC VIN

NC NC NC NC GND NC Sense VOUT

Microprocessor

SO–8

*C1 * required if regulator is located far from power supply filter.

.

Figure 1. Application Circuit


Value

Unit

Input Voltage, VIN

–0.3 to 45

V


–0.3 to 18

V

2.0

kV

–0.3 to +7.0

V

–40 to150

°C

–55 to +150

°C


45 165

°C/W °C/W

Package Thermal Resistance, SO–16L: Junction–to–Case, RθJC Junction–to–Ambient, RθJA

18 75

°C/W °C/W


1.0 36

°C/W °C/W

260 peak 230 peak

°C

ESD Susceptibility (Human Body Model) Logic Inputs/Outputs (Reset, WDI, Wakeup) Operating Junction Temperature, TJ Storage Temperature Range, TS


Wave Solder (through hole styles only) (Note 1) Reflow: (SMD styles only) (Note 2)



NCV8508 Series ELECTRICAL CHARACTERISTICS (–40°C ≤ TJ ≤ 125°C; 6.0 V ≤ VIN ≤ 28 V, 100 µA ≤ IOUT ≤ 150 mA, C2 = 1.0 µF, RDelay = 60 k; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

Output Voltage, VOUT for 3.3 V Option

–

3.201

3.300

3.399

V

Output Voltage, VOUT for 5.0 V Option

–

4.85

5.00

5.15

V

Output


IOUT = 150 mA. Note 3

–

425

800

mV

Load Regulation

VIN = 14 V, 100 µA ≤ IOUT ≤ 150 mA

–

5.0

30

mV

Line Regulation

6.0 V ≤ VIN ≤ 28 V, IOUT = 5.0 mA

–

5.0

20

mV

–

250

400

–

mA

Thermal Shutdown


150

180

210

°C

Quiescent Current

VIN = 12 V, IOUT = 150 mA

–

100

150

µA

Current Limit

RESET Threshold for 3.3 V Option

–

2.970

3.069

3.168

V

Threshold for 5.0 V Option

–

4.50

4.65

4.80

V

–

0.2

0.4

V

VOUT – 0.5

VOUT – 0.25

–

V

2.0 –

3.0 6.0

4.0 –

ms ms

Output Low

RLOAD = 10 k to VOUT, VOUT ≥ 1.0 V

Output High

RLOAD = 10 k to GND

Delay Time

VIN = 14 V, RDelay = 60 k, IOUT = 5.0 mA VIN = 14 V, RDelay = 120 k, IOUT = 5.0 mA

Watchdog Input Threshold High

–

70

–

–

%VOUT

Threshold Low

–

–

–

30

%VOUT

Hysteresis

–

25

100

–

mV

–

0.1

+10

µA

5.0

–

–

µs

Input Current

WDI = 6.0 V

Pulse Width

50% WDI falling edge to 50% WDI rising edge and 50% WDI rising edge to 50% WDI falling edge, (see Figure 5)

Wake Up Output (VIN = 14 V, IOUT = 5.0 mA) Wake Up Period

See Figures 4 and 5, RDELAY = 60 k See Figures 4 and 5, RDELAY = 120 k

19 –

25 50

31 –

ms ms

Wake Up Duty Cycle Nominal

See Figure 3.

45

50

55

%

RESET HIGH to Wake Up Rising Delay Time

RDELAY = 60 k 50% RESET rising edge to 50% Wake Up edge, RDELAY = 120 k (see Figures 3 and 4)

10 –

12.5 25

15 –

ms ms

Wake Up Response to Watchdog Input

50% WDI falling edge to 50% Wake Up falling edge

–

0.1

5.0

µs


50% RESET falling edge to 50% Wake Up falling edge. VOUT = 5.0 V→ 4.5 V

–

0.1

5.0

µs

Output Low

RLOAD = 10 k

–

0.2

0.4

V

Output High

RLOAD = 10 k

VOUT – 0.5

VOUT – 0.25

–

V

3. Measured when the output voltage has dropped 100 mV from the nominal value


NCV8508 Series ELECTRICAL CHARACTERISTICS (continued) (–40°C ≤ TJ ≤ 125°C; 6.0 V ≤ VIN ≤ 28 V, 100 µA ≤ IOUT ≤ 150 mA, C2 = 1.0 µF, RDelay = 60 k; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

–

1.25

–

V

Delay IDELAY = 50 µA. Note 4

Output Voltage

4. Current drain on the Delay pin directly affects the Delay Time, Wake Up Period, and the RESET to Wake Up Delay Time..

PACKAGE PIN DESCRIPTION PACKAGE PIN # SO–8

SO–16L

SOW–16 E PAD

PIN SYMBOL

4

8

8

VOUT

5

9

9

VIN

Supply Voltage to the IC.

6

11

11

WDI

CMOS compatible input lead. The watchdog function monitors the falling edge of the incoming signal.

2

4, 5, 12, 13

5

GND

Ground connection.

7

14

14

WAKE UP

CMOS compatible output consisting of a continuously generated signal used to Wake Up the microprocessor from sleep mode.

8

15

15

RESET

CMOS compatible output lead RESET goes low whenever VOUT drops by more than 7.0% from nominal, or during the absence of a correct watchdog signal.

1

16

16

Delay

–

1–3, 6, 10

1–4, 6, 10, 12, 13

NC

3

7

7

Sense

FUNCTION Regulated output voltage ± 3.0%.

Buffered bandgap voltage used to create timing current for RESET and Wake Up from RDelay. No Connection. Kelvin connection which allows remote sensing of the output voltage for improved regulation. Connect to VOUT if remote sensing is not required.


NCV8508 Series

VIN

VOUT Charge Pump

Current Limit +

Bandgap Reference

Thermal Shutdown

−

−

RESET

+

Watchdog Circuit

WDI Falling Edge Detect

Delay

Timing Circuit

WAKE UP Circuit



Wake Up

NCV8508 Series TIMING DIAGRAMS VIN

RESET

Wake Up Duty Cycle = 50%

Wake Up

WDI

VOUT

WDI Pulse Must Occur with Wake Up in Low State for 50% Duty Cycle. Reference Figure 15 for Occurance of WDI with Wake Up in High State.

POR RESET High to Wake Up Delay Time Power Up

Microprocessor Sleep Mode

Normal Operation with Varying Watchdog Signal

Figure 3. Power Up, Sleep Mode and Normal Operation

VIN

RESET Delay Time

RESET Wake Up WDI

VOUT POR RESET High to Wake Up Delay Time

Wake Up Period

RESET High to Wake Up Delay Time

Figure 4. Error Condition: Watchdog Remains Low and a RESET Is Issued

RESET

Wake Up Period

Wake Up

WDI RESET Threshold VOUT

Watchdog Pulse Width

Power Down POR

POR Watchdog Pulse Width

Figure 5. Power Down and Restart Sequence


NCV8508 Series TYPICAL PERFORMANCE CHARACTERISTICS –500

120 –40°C

–450 VOUT Transient, mV

–400

IQ, µA

110 +25°C

100

1.0 µF

–350 –300

10 µF

–250 –200 –150

100 µF

–100 +125°C 90

0

30

60

–50 90

120

0

150

0

30

IOUT, mA

Figure 6. Quiescent Current vs Output Current

120

150


3.7

14

3.6

12

3.5 3.4

10

POR Delay, ms

POR Delay, ms

60 90 Switching Current, mA

3.3 3.2 3.1 3.0

8 6 4

2.9 2

2.8 2.7 –40

–20

0

20

40 60 80 Temperature, °C

100

120

0 15

140

Figure 8. POR Delay vs Temp, RDELAY = 60 kW

60

105 150 RDELAY, kΩ

195

240

Figure 9. POR Delay vs RDELAY

27.0

100 90

26.5

70 RDELAY, ms

Wakeup Period, ms

80 26.0 25.5 25.0 24.5

60 50 40 30

24.0

20

23.5 23.0 –40

10 –20

0

20 40 60 80 Temperature (°C)

100

120

140

0 15

Figure 10. Wakeup Period vs Temp, RDELAY = 60 kW

60

105 150 RDELAY, kΩ

195

Figure 11. Wake Up Period vs RDELAY


240

NCV8508 Series TYPICAL PERFORMANCE CHARACTERISTICS 5.10

700

+125°C

500 400

Output Voltage (V)


600

+25°C

300

–40°C

200

5.05

5.00 VIN = 14 V IOUT = 5.0 mA 4.95

RL = 33 Ω 100 0

0

25

50 75 100 Output Current (mA)

125

4.90 –40 –25 –10

150

Figure 12. Dropout Voltage vs Output Current

5

20 35 50 65 Temperature (°C)

80

95 110 125

Figure 13. Output Voltage vs Temperature

160 140

IOUT (mA)

120 100 80 60 40

RL = 33 Ω

20 0 1.0

1.5

2.0

2.5

3.0

3.5 4.0 VIN (V)

4.5

5.0

5.5

6.0

Figure 14. Output Current vs Input Voltage

DEFINITION OF TERMS such that the average chip temperature is not significantly affected. Load Regulation: The change in output voltage for a change in load current at constant chip temperature. Quiescent Current: The part of the positive input current that does not contribute to the positive load current. The regulator ground lead current. Ripple Rejection: The ratio of the peak–to–peak input ripple voltage to the peak–to–peak output ripple voltage. Current Limit: Peak current that can be delivered to the output.

Dropout Voltage: The input–output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100 mV from the nominal value obtained at 14 V input, dropout voltage is dependent upon load current and junction temperature. Input Voltage: The DC voltage applied to the input terminals with respect to ground. Line Regulation: The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques

DETAILED OPERATING DESCRIPTION Wake Up and RESET. This unique combination of extremely low quiescent current and full microprocessor control makes the NCV8508 ideal for use in battery

The NCV8508 is a precision micro–power voltage regulator with very low quiescent current (100 µA typical at 250 mA load). A typical dropout voltage is 425 mV at 150 mA. Microprocessor control logic includes Watchdog,


NCV8508 Series the output voltage shifts below the regulation limits, the RESET toggles low and remains low until proper output voltage regulation is restored. And finally, a RESET signal is issued if the regulator does not receive a Watchdog signal within the Wake Up period. The RESET pulse width, Wake Up signal frequency, and Wake Up delay time are all set by one external resistor, RDelay. The Delay pin is a buffered bandgap voltage (1.25 V). It can be used as a reference for an external tracking regulator like the CS8182. The regulator is protected against short circuit and thermal runaway conditions. The device runs through 45 volt transients, making it suitable for use in automotive environments.

operated, microprocessor controlled equipment in addition to being a good fit in the automotive environment. The NCV8508 Wake Up function brings the microprocessor out of Sleep mode. The microprocessor in turn, signals its Wake Up status back to the NCV8508 by issuing a Watchdog signal. The Watchdog logic function monitors an input signal (WDI) from the microprocessor. The NCV8508 responds to the falling edge of the Watchdog signal which it expects at least once during each wake–up period. When the correct Watchdog signal is received, a falling edge is issued on the wake–up signal line. RESET is independent of VIN and operates correctly to an output voltage as low as 1.0 V. A signal is issued in any of three situations. During power up the RESET is held low until the output voltage is in regulation. During operation if

CIRCUIT DESCRIPTION Functional Description

Capacitor temperature coefficient and tolerance as well as the tolerance of the NCV8508 must be taken into account in order to get the correct system tolerance for each parameter.

To reduce the drain on the battery a system can go into a low current consumption mode when ever its not performing a main routine. The Wake Up signal is generated continuously and is used to interrupt a microcontroller that is in sleep mode. The nominal output is a 5.0 volt square wave with a duty cycle of 50% at a frequency that is determined by a timing resistor, RDelay. When the microprocessor receives a rising edge from the Wake Up output, it must issue a watchdog pulse and check its inputs to decide if it should resume normal operations or remain in the sleep mode. The first falling edge of the watchdog signal causes the Wake Up to go low within 2.0 µs (typ) and remain low until the next Wake Up cycle (see Figure 15). Other watchdog pulses received within the same cycle are ignored (Figure 3). During power up, RESET is held low until the output voltage is in regulation. During operation, if the output voltage shifts below the regulation limits, the RESET toggles low and remains low until proper output voltage regulation is restored. After the RESET delay, RESET returns high. The Watchdog circuitry continuously monitors the input watchdog signal (WDI) from the microprocessor. The absence of a falling edge on the Watchdog input during one Wake Up cycle will cause a RESET pulse to occur at the end of the Wake Up cycle. (see Figure 4). The Wake Up output is pulled low during a RESET regardless of the cause of the RESET. After the RESET returns high, the Wake Up cycle begins again (see Figure 4). The RESET Delay Time, Wake Up signal frequency and RESET high to Wake Up delay time are all set by one external resistor RDelay. Wake Up period = (4.17 × 10–7)RDelay RESET Delay Time = (5.21 × 10–8)RDelay RESET HIGH to Wake Up Delay Time = (2.08 × 10–7)RDelay

WDI

WAKE UP

WAKE UP Response to WDI

Figure 15. Wake Up Response to WDI RESET

WAKE UP

WAKE UP Response to RESET

Figure 16. Wake Up Response to RESET (Low Voltage)


NCV8508 Series APPLICATION NOTES Calculating Power Dissipation in a Single Output Linear Regulator

The value of RΘJA can then be compared with those in the package section of the data sheet. Those packages with RΘJA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.

The maximum power dissipation for a single output regulator (Figure 17) is: PD(max) + [VIN(max) * VOUT(min)]IOUT(max)

(1)

) VIN(max)IQ


Heat Sinks


IOUT

IIN

SMART REGULATOR

VIN

}


VOUT


Control Features IQ


Once the value of PD(max) is known, the maximum permissible value of RΘJA can be calculated: T RJA + 150°C * A PD

(2)


Output Voltage

Package

Shipping

NCV8508D50

SO–8

95 Units/Rail

NCV8508D50R2

SO–8

2500 Tape & Reel

SO–16L

46 Units/Rail

SO–16L

1000 Tape & Reel

NCV8508PDW50


46 Units/Rail

NCV8508PDW50R2


1000 Tape & Reel

NCV8508DW50 NCV8508DW50R2

(3)

50V 5.0

*Consult your local sales representative for 3.3 V option.


,# 3 1 7 ' ' 0 ( The CS5101 is a bipolar monolithic secondary side post regulator (SSPR) which provides tight regulation of multiple output voltages in AC–DC or DC–DC converters. Leading edge pulse width modulation is used with the CS5101. The CS5101 is designed to operate over an 8.0 V to 45 V supply voltage (VCC) range and up to a 75 V drive voltage (VC). The CS5101 features include a totem pole output with 1.5 A peak output current capability, externally programmable overcurrent protection, an on chip 2.0% precision 5.0 V reference, internally compensated error amplifier, externally synchronized switching frequency, and a power switch drain voltage monitor. It is available in a 14 lead plastic DIP or a 16 lead wide body SO package. Features 1.5 A Peak Output (Grounded Totem Pole) 8.0 V to 75 V Gate Drive Voltage 8.0 V to 45 V Supply Voltage 300 ns Propagation Delay 1.0% Error Amplifier Reference Voltage Lossless Turn On and Turn Off Sleep Mode: < 100 µA Overcurrent Protection with Dedicated Differential Amp Synchronization to External Clock External Power Switch Drain Voltage Monitor

http://onsemi.com DIP–14 N SUFFIX CASE 646

14 1


16 1

PIN CONNECTIONS AND MARKING DIAGRAMS 1 SYNC VCC VREF LGND VFB COMP

CS5101 AWLYYWW

• • • • • • • • • •

14 VD VC VG PGND IS COMP IS–

RAMP

IS+ DIP–14

1

CS5101

AWLYYWW

SYNC VCC VREF DGND AGND VFB COMP RAMP

16 VD VC VG PGND PGND IS COMP IS– IS+

SO–16L A WL, L YY, Y WW, W





955

Package

Shipping

CS5101EN14

DIP–14

25 Units/Rail

CS5101EDW16

SO–16L

46 Units/Rail

CS5101EDWR16

SO–16L 1000 Tape & Reel


CS5101 VSY

L1 CR4

1

3

4

Q1

VOUT

R10

TR

5 R8

6

R11

R13 + C6

CR5 R5

R6

R9

R12

R14

GND CR1

C5 +

R1

R2

CR3 R7

VD

VSYNC VCC R3

VREF

CR2

CS5101 SSPR

LGND VFB + C1

C2

R4

VC VG

PGND

C4

IS COMP

COMP

IS–

RAMP

IS+

2 C3

CR

Figure 1. Application Diagram ABSOLUTE MAXIMUM RATINGS* Rating

Value

Unit

Power Supply Voltage, VCC

–0.3 to 45

V

VSYNC and Output Supply Voltages, VC, VG, VSYNC, VD

–0.3 to 75

V

VIS+, VIS– (VCC – 4.0 V, up to 24 V)

–0.3 to 24

V

VREF, VFB, VCOMP, VRAMP, VISCOMP

–0.3 to 10

V

Operating Junction Temperature, TJ

–40 to +150

°C


–40 to +85

°C


–65 to +150

°C

Output Energy (Capacitive Load Per Cycle)

5.0

µJ

ESD Human Body

2.0

kV

260 peak 230 peak

°C °C


Wave Solder (through hole styles only)(Note 1) Reflow (SMD styles only) (Note 2)

1. 10 second maximum 2. 60 second maximum above 183°C *The maximum package power dissipation must be observed.


CS5101 ELECTRICAL CHARACTERISTICS: (–40°C ≤ TA ≤ 85°C, –40°C ≤ TJ ≤ 150°C, 10 V < VCC < 45 V, 8.0 V < VC < 75 V; unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit

Error Amplifier Input Voltage Initial Accuracy

VFB = VCOMP, VCC = 15 V, T = 25°C, Note 3

1.98

2.00

2.02

V

Input Voltage

VFB = VCOMP, includes line and temp

1.94

2.00

2.06

V

Input Bias Current

VFB = 0 V, IVFB flows out of pin

–

–

500

nA

Open Loop Gain

1.5 V < VCOMP < 3.0 V

60

70

–

dB

Unity Gain Bandwidth

1.5 V < VCOMP < 3.0 V, Note 3

0.7

1.0

–

MHz

Output Sink Current

VCOMP = 2.0 V, VFB = 2.2 V

2.0

8.0

–

mA

Output Source Current

VCOMP = 2.0 V, VFB = 1.8 V

2.0

6.0

–

mA

VCOMP High

VFB = 1.8 V

3.3

3.5

3.7

V

VCOMP Low

VFB = 2.2 V

0.85

1.0

1.15

V

PSRR

10 V < VCC < 45 V, VFB = VCOMP, Note 3

60

70

–

dB

Output Voltage Initial Accuracy

VCC = 15 V, T = 25°C, Note 3

4.9

5.0

5.1

V

Output Voltage

0 A < IREF < 8.0 mA

4.8

5.0

5.2

V

Line Regulation

10 V < VCC < 45 V, IREF = 0 A

–

10

60

mV

Load Regulation

0 A < IREF < 8.0 mA

–

20

60

mV

Current Limit

VREF = 4.8 V

10

50

–

mA

VREF–OK FAULT V

VSYNC = 5.0 V, VREF = VLOAD

4.10

4.40

4.60

V

VREF–OK V

VSYNC = 5.0 V, VREF = VLOAD

4.30

4.50

4.80

V

40

100

250

mV

Voltage Reference

VREF–OK Hysteresis

–

Current Sense Amplifier IS COMP High V

IS+ = 5.0 V, IS– = IS COMP

4.7

5.0

5.3

V

IS COMP Low V

IS+ = 0 V, IS– = IS COMP

0.5

1.0

1.3

V

Source Current

IS+ = 5.0 V, IS– = 0 V

2.0

10

–

mA

Sink Current

IS– = 5.0 V, IS+ = 0 V

10

20

–

mA

Open Loop Gain

1.5 V ≤ VCOMP ≤ 4.5 V, RL = 4.0 kΩ

60

80

–

dB

CMRR

Note 3

60

80

–

dB

PSRR

10 V < VCC < 45 V, Note 3

60

80

–

dB


1.5 V ≤ VCOMP ≤ 4.5 V, RL = 4.0 kΩ, Note 3

0.5

0.8

–

MHz

Input Offset Voltage

VIS+ = 2.5 V, VIS– = VISCOMP

–8.0

0

8.0

mV

Input Bias Currents

VIS+ = VIS– = 0 V, IIS flows out of pins

–

20

250

nA

–250

0

250

nA

–0.3

–

VCC – 4.0

V

Input Offset Current (IS+, IS–) Input Signal Voltage Range

– Note 3

3. Guaranteed by design. Not 100% tested in production.


CS5101 ELECTRICAL CHARACTERISTICS: (continued) (–40°C ≤ TA ≤ 85°C, –40°C ≤ TJ ≤ 150°C, 10 V < VCC < 45 V, 8.0 V < VC < 75 V; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

RAMP/SYNC Generator RAMP Source Current Initial Accuracy

VSYNC = 5.0 V, VRAMP = 2.5 V, T = 25°C, Note 4

0.18

0.20

0.22

mA

RAMP Source Current

VSYNC = 5.0 V, VRAMP = 2.5 V

0.16

0.20

0.24

mA

RAMP Sink Current

VSYNC = 0 V, VRAMP = 2.5 V

1.0

4.0

–

mA

RAMP Peak Voltage

VSYNC = 5.0 V

3.3

3.5

3.7

V

RAMP Valley Voltage

VSYNC = 0 V

1.4

1.5

1.6

V

RAMP Dynamic Range

VRAMPDR = VRAMPPK – VRAMPVY

1.7

2.0

2.3

V

RAMP Sleep Threshold Voltage

VRAMP @ VREF < 2.0 V

0.3

0.6

1.0

V

SYNC Threshold

VSYNC @ VRAMP > 2.5 V

2.3

2.5

2.7

V

SYNC Input Bias Current

VSYNC = 0 V, ISYNC flows out of pin

–

1.0

20

µA

VG, High

VSYNC = 5.0 V, IVG = 200 mA, VC – VG

–

1.6

2.5

V

VG, Low

VSYNC = 0 V, IVG = 200 mA

–

0.9

1.5

V

VG Rise Time

Switch VSYNC High, CG = 1.0 nF, VCC = 15 V, measure 2.0 V to 8.0 V

–

30

75

ns

VG Fall Time

Switch VSYNC Low, CG = 1.0 nF, VCC = 15 V, measure 8.0 V to 2.0 V

–

40

100

ns

VG Resistance to GND

Remove supplies, VG = 10 V

–

50

100

kΩ

VD Resistance to GND

Remove supplies, VD = 10 V

500

1500

–

Ω

Output Stage

General ICC, Operating

VSYNC = 5.0 V

–

12

18

mA

ICC in UVL

VCC = 6.0 V

–

300

500

µA

ICC in Sleep Mode High

VRAMP = 0 V, VCC = 45 V

–

80

200

µA

ICC in Sleep Mode Low

VRAMP = 0 V, VCC = 10 V

–

20

50

µA

IC, Operating High

VSYNC = 5.0 V, VFB = VIS– = 0 V, VC = 75 V

–

4.0

8.0

mA

IC, Operating Low

VSYNC = 5.0 V, VFB = VIS– = 0 V, VC = 8.0 V

–

3.0

6.0

mA

UVLO Start Voltage

–

7.4

8.0

9.2

V

UVLO Stop Voltage

–

6.4

7.0

8.3

V

UVLO Hysteresis

–

0.8

1.0

1.2

V

Leading Edge, tDELAY

VSYNC = 2.5 V to VG = 8.0 V

–

280

–

ns

Trailing Edge, tDELAY

VSYNC = 2.5 V to VG = 2.0 V

–

750

–

ns

4. Guaranteed by design. Not 100% tested in production.


CS5101 PACKAGE PIN DESCRIPTION PACKAGE LEAD # DIP–14

SO–16L

LEAD SYMBOL

1

1

SYNC

2

2

VCC

Logic supply (10 V to 45 V).

3

3

VREF

5.0 V voltage reference.

4

–

LGND

Logic level ground (analog and digital ground tied).

5

6

VFB

6

7

COMP

Error amplifier output and compensation.

7

8

RAMP

RAMP programmable with the external capacitor.

8

9

IS+

Current sense amplifier non–inverting input.

9

10

IS–

Current sense amplifier inverting input.

10

11

IS COMP

11

12, 13

PGND

12

14

VG

External power switch gate drive.

13

15

VC

Output power stage supply voltage (8.0 V to 75 V).

14

16

VD

External FET DRAIN voltage monitor.

–

5

AGND

Analog ground.

–

4

DGND

Digital ground.

FUNCTION Synchronization input.

Error amplifier inverting input.

Current sense amplifier compensation and output. Power ground.


CS5101 CIRCUIT DESCRIPTION

VCC

VD VCC

VC

REF VREF

5.0 V

OK

+ SLEEP –

+ UVL + – + – 8.0 V/7.0 V

LGND

Q1

VG Q2

0.7 V +–

PGND IS COMP

VCC 5.0 V

5.0 V

24.6 k

–

VFB

EA

10 k

+

– BUF +

10 k

+ – 2.0 V

VC

+

IS+

I = 200 µA 5.0 V

+ – 1.65 V

Q3

S

5.0 V

LATCH Q

+ – 1.5 V

+ RAMP –

5.0 V

– – + PWM +

Q

SYNC

IS–

+ 2.4 V –

5.0 V

COMP

RAMP

– IS

R

0.7 V +– – VCC–OK

5.0 V

+

+ Q4

G1

REF_OK

–

5.0 V

+ – 4.5 V/4.4 V

+ SYNC –

VCC

G2

+ – 2.5 V

Figure 2. Block Diagram Theory of Operation

SYNC Function

The CS5101 is designed to regulate voltages in multiple output power supplies. Functionally, it is similar to a magnetic amplifier, operating as a switch with a delayed turn–on. It can be used with both single ended and dual ended topologies. The VFB voltage is monitored by the error amplifier EA. It is compared to an internal reference voltage and the amplified differential signal is fed through an inverting amplifier into the buffer, BUF. The buffered signal is compared at the PWM comparator with the ramp voltage generated by capacitor CR. When the ramp voltage VR, exceeds the control voltage VC, the output of the PWM comparator goes high, latching its state through the LATCH, the output stage transistor Q1 turns on, and the external power switch, usually an N–FET, turns on.

The SYNC circuit is activated at time t1 (Figure 3) when the voltage at the SYNC pin exceeds the threshold level (2.5V) of the SYNC comparator. The external ramp capacitor CR is allowed to charge through the internal current source I (200 µA). At time t2, the ramp voltage intersects with the control voltage VC and the output of the PWM comparator goes high, turning on the output stage and the external power switch. At the same time, the PWM comparator is latched by the RS latch, LATCH.


CS5101 1

RAMP Function

VSY

VSY

The value of the ramp capacitor CR is based on the switching frequency of the regulator and the maximum duty cycle of the secondary pulse VSY. If the RAMP pin is pulled externally to 0.3 V or below, the SSPR is disabled. Current drawn by the IC is reduced to less than 100 µA, and the IC is in SLEEP mode.

0V

VC

2

VRAMP VSY + VD VDS

3

VSY

4

VD

VS

VL1

0V

VOUT + VD

VSY + VC

6

The voltage at the VCC pin is monitored by the undervoltage lockout comparator with hysteresis. When VCC falls below the UVL threshold, the 5.0 V reference and all the circuitry running off of it is disabled. Under this condition the supply current is reduced to less than 500 µA. The VCC supply voltage is further monitored by the VCC_OK comparator. When VCC is reduced below VREF – 0.7 V, a fault signal is sent to gate G1. This fault signal, which determines if VCC is absent, works in conjunction with the ramp signal to disable the output, but only after the current cycle has finished and the RS latch is reset. Therefore this fault will not cause the output to turn off during the middle of an on pulse, but rather will utilize lossless turn–off. This feature protects the FET from overvoltage stress. This is accomplished through gate G1 by driving transistor Q4 on. An additional fault signal is derived from the REF_OK comparator. VREF is monitored so to disable the output through gate G1 when the VREF voltage falls below the OK threshold. As in the VCC_OK fault, the REF_OK fault disables the output after the current cycle has been completed. The fault logic will operate normally only when VREF voltage is within the specification limits of REF_OK.

0V

VSY – VOUT

5

FAULT Function

0V

VD

VG

0V

Ground Level (Gate doesn’t go below GND)

t1 t2 t3

t4 t1

Figure 3. Waveforms for CS5101. The Number to the Left of Each Curve Refers to a Node On the Application Diagram on Page 956.

The logic state of the LATCH can be changed only when both the voltage level of the trailing edge of the power pulse at the SYNC pin is less than the threshold voltage of the SYNC comparator (2.5 V) and the RAMP voltage is less than the threshold voltage of the RAMP comparator (1.65 V). On the negative going transition of the secondary side pulse VSY, gate G2 output goes high, resetting the latch at time t3. Capacitor CR is discharged through transistor Q4. CR’s output goes low disabling the output stage, and the external power switch (an N–FET) is turned off.

DRAIN Function

The drain pin, VD monitors the voltage on the drain of the power switch and derives energy from it to keep the output stage in an off state when VC or VCC is below the minimum specified voltage.


CS5101 S1 8.0 V – 45 V C1 1.0 µF

R1 100 k

R2 100 k

V1 100 kHz 0 V to 5.0 V Square Wave

VSYNC VCC VREF

C2 0.1 µF

SW SPST

CS5101

LGND VFB

R3 5.0 k

VD VC C3 1.0 nF

VG

PGND IS COMP

COMP

IS–

RAMP

IS+ R4 2.2 k

R6 10 k

C4 0.1 µF

R7 10 k

R5 10 k

C5 680 pF

Figure 4. CS5101 Bench Test on DIP–14 Package


DIP–14

SO–16L

Unit

RΘJC

Typical

23

48

°C/W

RΘJA

Typical

105

85

°C/W


1-"##

0 $7

+ 7 The NCP4300A is a monolithic integrated circuit specifically designed to control the output current and voltage levels of switch mode battery chargers and power supplies. This device contains a precision 2.6 V shunt reference and two operational amplifiers. Op–Amp 1 is designed to perform voltage control and has its non–inverting input internally connected to the reference. Op–Amp 2 is designed for current control and has both inputs uncommitted. The NCP4300A offers the power converter designer a control solution that features increased precision with a corresponding reduction in system complexity and cost. This device is available in an 8–lead surface mount package.

http://onsemi.com MARKING DIAGRAM 8 SO–8 D SUFFIX CASE 751

8 1

N4300 ALYWX 1

Features A L Y W X

Operational Amplifier

• • • • • •

Low Input Offset Voltage: 0.5 mV Input Common Mode Voltage Range Includes Ground Low Supply Current: 210 µA/Op–Amp (@VCC = 5.0 V) Medium Unity Gain Bandwidth: 0.7 MHz Large Output Voltage Swing: 0 V to VCC – 1.5 V Wide Power Supply Voltage Range: 3.0 V to 35 V

= Assembly Location = Wafer Lot = Year = Work Week = Option Code = A

PIN CONNECTIONS

Voltage Reference

• Fixed Output Voltage Reference: 2.60 V • High Precision Over Temperature: 1.0% • Wide Sink Current Range: 80 µA to 80 mA

Out 1 1

8

VCC

In 1– 2

7

Out 2

In 1+ 3

6

In 2–

GND 4

5

In 2+

Typical Applications • Battery Charger • Switch Mode Power Supply

(Top View)


Output 1

VCC

Output 2

Shipping

SO–8

2500/Tape & Reel

+

2.6 V

GND

NCP4300ADR2

Package

+

Inputs 1

Inputs 2




963

Publication Order Number: NCP4300A/D

NCP4300A ABSOLUTE MAXIMUM RATINGS Symbol

Value

Unit

Supply Voltage (VCC to GND)

Rating

VCC

36

V

ESD Protection Voltage at any Pin (Human Body Model)

VESD

2.0 K (min)

V

Op–Amp 1 and 2 Input Voltage Range (Pins 2, 5, 6)

VIR

–0.6 to VCC +0.6

V

Op–Amp 2 Input Differential Voltage Range (Pins 5, 6)

VIDR

VCC to GND

V

Voltage Reference Cathode Current (Pin 3)

IK

100

mA


TJ

150

°C

Operating Ambient Temperature Range

TA

0 to 105

°C


Tstg

–55 to 150

°C

Symbol

Value

Unit

Thermal Resistance, Junction to Ambient

RJA

155

°C/W

Thermal Resistance, Junction to Case

RJC

45

°C/W

THERMAL CHARACTERISTICS Rating

TYPICAL ELECTRICAL CHARACTERISTICS Characteristic Total Supply Current, excluding Current in the Voltage Reference VCC = 5.0 V, no load; 0°C v TA v 105°C

Symbol

Min

Typ

Max

Unit

ICC

–

0.42

0.8

mA

– –

0.5 –

2.0 3.0

–

7.0

–

– –

–50 –

–150 –150

50 25

100 –

– –

Op–Amp 1 (Op–amp with non–inverting input connected to the internal Vref) (VCC = 5.0 V, Vout = 1.4 V, TA = 25°C, unless otherwise noted) Input Offset Voltage TA = 25°C TA = 0°C to 105°C

VIO

VIO/T

Input Offset Voltage Temperature Coefficient TA = 0°C to 105°C Input Bias Current (Inverting input only) TA = 25°C TA = 0°C to 105°C

mV

IIB

Large Signal Voltage Gain (VCC = 15 V, RL = 2.0 kΩ, Vout = 1.4 V to 11.4 V) TA = 25°C TA = 0°C to 105°C

AVOL

Power Supply Rejection (VCC = 5.0 V to 30 V)

µV/°C nA

V/mV

PSRR

40

90

–

dB

Output Source Current (VCC = 15 V, Vout = 2.0 V, VID = +1.0 V)

IO+

10

16

–

mA

Output Sink Current (VCC = 15 V, Vout = 2.0 V, VID = –1.0 V)

IO–

10

25

–

mA

Output Voltage Swing, High (VCC = 30 V, RL = 10 kΩ, VID = +1.0 V) TA = 25°C TA = 0°C to 105°C

VOH 27 27

28 –

– –

Output Voltage Swing, Low (RL = 10 kΩ, VID = –1.0 V) TA = 25°C TA = 0°C to 105°C

VOL – –

17 –

100 100

Slew Rate (Vin = 0.5 to 2.0 V, VCC = 15 V, RL = 2.0 kΩ, Av = 1.0, CL = 100 pF)

SR

0.3

0.5

–

V/µs

Unity Gain Bandwidth (VCC = 30 V, RL = 2.0 kΩ, CL = 100 pF, Vin = 0.5 Vpp @ f = 70 kHz)

BW

0.3

0.7

–

MHz

Total Harmonic Distortion (f = 1.0 kHz, AV = 10, RL = 2.0 kΩ, VCC = 30 V, Vout = 2.0 VPP)

THD

–

0.02

–

%


V

mV

NCP4300A TYPICAL ELECTRICAL CHARACTERISTICS (continued) Characteristic

Symbol

Min

Typ

Max

– –

0.5 –

2.0 3.0

–

7.0

–

– –

2.0 –

30 30

– –

–50 –

–150 –150

–

0 to VCC –1.5

–

50 25

100 –

– –

40

90

–

40 30

60 –

– –

Unit

Op–Amp 2 (Independent op–amp) (VCC = 5.0 V, Vout = 1.4 V, TA = 25°C, unless otherwise noted) VIO

Input Offset Voltage TA = 25°C TA = 0°C to 105°C

VIO/T

Input Offset Voltage Temperature Coefficient TA = 0°C to 105°C Input Offset Current TA = 25°C TA = 0°C to 105°C

IIO

Input Bias Current TA = 25°C TA = 0°C to 105°C

IIB

Input Common Mode Voltage Range (VCC = 0 V to 35 V)

VICR

Large Signal Voltage Gain (VCC = 15 V, RL = 2.0 kΩ, Vout = 1.4 V to 11.4 V) TA = 25°C TA = 0°C to 105°C

AVOL

Power Supply Rejection (VCC = 5.0 V to 30 V)

PSRR

Common Mode Rejection (VCM = 0 V to 3.5 V) TA = 25°C TA = 0°C to 105°C

CMRR

mV

µV/°C nA

nA

V V/mV

dB dB

Output Source Current (VCC = 15 V, Vout = 2.0 V, VID = +1.0 V)

IO+

10

16

–

mA

Output Sink Current (VCC = 15 V, Vout = 2.0 V, VID = –1.0 V)

IO–

10

25

–

mA

Output Voltage Swing, High (VCC = 30 V, RL = 10 kΩ, VID = +1.0 V) TA = 25°C TA = 0°C to 105°C

VOH 27 27

28 –

– –

Output Voltage Swing, Low (RL = 10 kΩ, VID = –1.0 V) TA = 25°C TA = 0°C to 105°C

VOL – –

17 –

100 100

V

mV

Slew Rate (Vin = 0.5 to 3.0 V, VCC = 15 V, RL = 2.0 kΩ, Av = 1.0, CL = 100 pF)

SR

0.3

0.5

–

V/µs

Unity Gain Bandwidth (VCC = 30 V, RL = 2.0 kΩ, CL = 100 pF, Vin = 0.5 Vpp @ f = 70 kHz)

BW

0.3

0.7

–

MHz

Total Harmonic Distortion (f = 1.0 KHz, AV = 10, RL = 2.0 kΩ, VCC = 30 V, Vout = 2.0 VPP)

THD

–

0.02

–

%

– 2.574

2.60 2.60

– 2.626

Voltage Reference Reference Voltage (IK = 10 mA) TA = 25°C TA = 0°C to 105°C

Vref

V

Reference Input Voltage Deviation Over Full Temperature Range (IK = 10 mA, TA = 0°C to 105°C)

Vref

–

5.0

22

mV

Minimum Cathode Current for Regulation

IK(min)

–

55

80

µA

Dynamic Impedance TA = 25°C, IK = 1.0 to 80 mA, f t 1.0 KHz TA = 0°C to 125°C, IK = 1.0 mA to 60 mA, f t 1.0 KHz

|ZKA| – –

0.3 –

0.5 0.6


Ω

TA = 25°C

60

Vref, REFERENCE VOLTAGE (V)

IK, CATHODE CURRENT (mA)

NCP4300A

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20

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0

1.0

2.0

2.620

2.610

2.600

2.590

2.580

3.0

20

0

80

100


Figure 2. Reference Cathode Current vs. Cathode Voltage

Figure 3. Reference Voltage vs. Ambient Temperature

10 IK, CATHODE CURRENT (mA)

IK = 1.0 mA to 60 mA 0.35

0.3

0.25

0.2 0

50

TA = 25°C

8.0

Stable 6.0 Unstable

4.0 Stable 2.0

0 100 pF

100

1.0 F

1000 pF

10 F

100 F

CL, LOAD CAPACITANCE


Figure 5. Reference Stability vs. Load Capacitance

Figure 4. Reference Dynamic Impedance vs. Ambient Temperature 0 VCC = 5.0 V Op–Amp 2

0.5

0

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–0.5

IIB, INPUT BIAS CURRENT (nA)

1.0 VO, INPUT OFFSET VOLTAGE (mV)

60

40

VKA, CATHODE VOLTAGE (V)

0.4 |ZKA|, DYNAMIC IMPEDANCE (Ω)

IK = 10 mA

VCC = 5.0 V –5.0

–10

–15

Op–Amp 2 Op–Amp 1

–20

–25

–1.0 0

20

40

60

80

0

100

20

40

60

80



Figure 6. Input Offset Voltage vs. Ambient Temperature

Figure 7. Input Bias Current vs. Ambient Temperature


100

CMRR, COMMON MODE REJECTION RATIO (dB)

NCP4300A

65 VCC = 3.0 V to 35 V

60 105°C 55 25°C

0°C

50 0

10

20

30

40

VCC, SUPPLY VOLTAGE (V)

Figure 8. Common Mode Rejection Ratio vs. Supply Voltage

DETAILED OPERATING DESCRIPTION reference is initially trimmed to a ±0.5% tolerance at TA = 25_C and is guaranteed to be within ±1.0% over an ambient temperature range of 0_C to 105_C.

INTRODUCTION Power supplies and battery chargers require precise control of output voltage and current in order to prevent catastrophic damage to the system connected. Many present day power sources contain a wide assortment of building blocks and glue devices to perform the required sensing for proper regulation. Typical feedback loop circuits may consist of a voltage and current amplifier, summing circuitry and a reference. The NCP4300A contains all of these basic functions in a manner that is easily adaptable to many of the various power source–load configurations.

Voltage Sensing Operational Amplifier (Op–Amp 1)

The internal Op–Amp 1 is designed to perform the voltage control function. The non–inverting input of the op–amp is connected to the precision voltage reference internally. The inverting input of the op–amp monitors the voltage information derived from the system output. As the control threshold is internally connected to the voltage reference, the voltage regulation threshold is fixed at 2.6 V. For any output voltage from 2.6 V up to the maximum limit can be configurated with an external resistor divider. The output terminal of Op–Amp 1 (pin 1) provides the error signal for output voltage control. The output pin also provides a means for external compensation.

OPERATING DESCRIPTION The NCP4300A is an analog regulation control circuit that is designed to simultaneously close the voltage and current feedback loops in power supply and battery charger applications. This device can control the feedback loop in either constant–voltage (CV) or constant–current (CC) mode with smooth crossover. A concise description of the integrated circuit blocks is given in below. The functional block diagram of the IC is shown in Figure 1.

Independent Operational Amplifier (Op–Amp 2)

The internal Op–Amp 2 is configurated as a general purpose op–amp with all terminals available for the user. With the low offset voltage provided, 0.5 mV, this op–amp can be used for current sensing in a constant current regulator.

Internal Reference

An internal precision band gap reference is used to set the 2.6 V voltage threshold and current threshold setting. The


NCP4300A

Opto Isolator

AC Line

SMPS

Iout

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Vout

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R3 R2 R4 R5 Current Sense

The above circuit demonstrates the use of the NCP4300A in a constant–current constant–voltage switch mode battery charger application. The charging current level is set by resistors R3, R4, and R5. The reference voltage is divided down by resistors R3 and R4 to create an offset voltage at pin 6. This results in a high state at the op amp output, pin 7. As the battery pack charge current increases, a proportional increasing voltage is developed across R5 that will eventually cancel out the pin 6 offset voltage. This will cause the op amp output to sink current from the opto isolator diode, and control the SMPS block in a constant–current mode. Resistors R1 and R2 divide the battery pack voltage down to the 2.6 V reference level. As the battery pack voltage exceeds the desired programmed level, the voltage at pin 2 will become slightly greater than pin 3. This will cause the op amp output to sink current from the opto isolator diode, and control the SMPS block in a constant–voltage mode. The formulas for programming the output current and voltage are given below.

Iout +

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With : R1 + 4.7 k R2 + 3.6 k Vout + 6.0 V

Figure 9. Constant–Current Constant–Voltage Switch Mode Battery Charger


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General Features

• • • • •

Flexibility Duty Cycle Control Undervoltage Lockout with Hysteresis On Chip Oscillator Switching Frequency 40, 75, or 100 kHz Secondary Control with Few External Components

•


Demag 1 Isense

2

Control Input

3

8

4

Vi

7 6

VCC

5

Driver

AWL = Manufacturing Code YYWW = Date Code


Low Power Mode Lossless Startup Low dV/dT for Low EMI Radiations


PDIP–8 P SUFFIX CASE 626

(Top View)

• Pulsed Mode Techniques for a Very High Efficiency


1

GND

Maximum Duty Cycle Limitation Cycle by Cycle Current Limitation Demagnetization (Zero Current Detection) Protection “Over VCC Protection” Against Open Loop Programmable Low Inertia Over Voltage Protection Against Open Loop Internal Thermal Protection

SMPS Controller

• •

8

(Top View)

Protections

• • • • •

http://onsemi.com

44608Pxxx AWL YYWW

The MC44608 is a high performance voltage mode controller designed for off–line converters. This high voltage circuit that integrates the start–up current source and the oscillator capacitor, requires few external components while offering a high flexibility and reliability. The device also features a very high efficiency stand–by management consisting of an effective Pulsed Mode operation. This technique enables the reduction of the stand–by power consumption to approximately 1.0 W while delivering 300 mW in a 150 W SMPS. • Integrated Start–Up Current Source • Lossless Off–Line Start–Up • Direct Off–Line Operation • Fast Start–Up

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Switching Frequency Package Shipping

MC44608P40

40 kHz

Plastic DIP–8

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MC44608P75

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The MC44608 demagnetization detection consists of a comparator designed to compare the VCC winding voltage to a reference that is typically equal to 50 mV. This reference is chosen low to increase effectiveness of the demagnetization detection even during start–up. A latch is incorporated to turn the demagnetization block output into a low level as soon as a voltage less than 50 mV is detected, and to keep it in this state until a new pulse is generated on the output. This avoids any ringing on the input signal which may alter the demagnetization detection. For a higher safety, the demagnetization block output is also directly connected to the output, which is disabled during the demagnetization phase. The demagnetization pin is also used for the quick, programmable OVP. In fact, the demagnetization input current is sensed so that the circuit output is latched off when this current is detected as higher than 120 µA.

Figure 5. Oscillator Block

The complete demagnetization status DMG is used to inhibit the recharge of the CT capacitor. Thus in case of incomplete transformer demagnetization the next switching cycle is postpone until the DMG signal appears. The oscillator remains at 2.4 V corresponding to the sawtooth valley voltage. In this way the SMPS is working in the so called SOPS mode (Self Oscillating Power Supply). In that case the effective switching frequency is variable and no longer depends on the oscillator timing but on the external working conditions (Refer to DMG signal in the Figure 6).


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Figure 7. Hiccup Mode Figure 6.

In case of the hiccup mode, the duty cycle of the switching phase is in the range of 10%.

The OSC and Clock signals are provided according to the Figure 6. The Clock signals correspond to the CT capacitor discharge. The bottom curve represents the current flowing in the sense resistor Rcs. It starts from zero and stops when the sawtooth value is equal to the control voltage Vcont. In this way the SMPS is regulated with a voltage mode control.

Mode Transition

The LW latch Figure 8 is the memory of the working status at the end of every switching sequence. Two different cases must be considered for the logic at the termination of the SWITCHING PHASE: 1. No Over Current was observed 2. An Over Current was observed These 2 cases are corresponding to the signal labelled NOC in case of “No Over Current” and “OC” in case of Over Current. So the effective working status at the end of the ON time memorized in LW corresponds to Q=1 for no over current and Q=0 for over current. This sequence is repeated during the Switching phase. Several events can occur: 1. SMPS switch OFF 2. SMPS output overload 3. Transition from Normal to Pulsed Mode 4. Transition from Pulsed Mode to Normal Mode

Overvoltage Protection

The MC44608 offers two OVP functions: – a fixed function that detects when VCC is higher than 15.4 V – a programmable function that uses the demag pin. The current flowing into the demag pin is mirrored and compared to the reference current Iovp (120 µA). Thus this OVP is quicker as it is not impacted by the VCC inertia and is called QOVP. In both cases, once an OVP condition is detected, the output is latched off until a new circuit START–UP. Start–up Management

The Vi pin 8 is directly connected to the HV DC rail Vin. This high voltage current source is internally connected to the VCC pin and thus is used to charge the VCC capacitor. The VCC capacitor charge period corresponds to the Start–up phase. When the VCC voltage reaches 13 V, the high voltage 9.0 mA current source is disabled and the device starts working. The device enters into the switching phase. It is to be noticed that the maximum rating of the Vi pin 8 is 500 V. ESD protection circuitry is not currently added to this pin due to size limitations and technology constraints. Protection is limited by the drain–substrate junction in avalanche breakdown. To help increase the application safety against high voltage spike on that pin it is possible to insert a small wattage 1.0 k series resistor between the Vin rail and pin 8. The Figure 7 shows the VCC voltage evolution in case of no external current source providing current into the VCC pin during the switching phase. This case can be encountered in SMPS when the self supply through an auxiliary winding is not present (strong overload on the SMPS output for example). The Figure 17 also depicts this working configuration.

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MC44608 The Figure 19 represents a complete power supply using the secondary reconfiguration. The specification is as follows: Input source: 85 Vac to 265 Vac 3 Outputs 112 V/0.45 A 16 V/1.5 A 8.0 V/1.0 A Output power 80 W Stand–by mode @ Pout = 300 mW, 1.3 W ,$*

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MC33364 FUNCTIONAL DESCRIPTION INTRODUCTION

directly from the ac line. This data sheet describes a monolithic control IC that was specifically designed for power supply control with a minimal number of external components. It offers the designer a simple cost effective solution to obtain the benefits of off–line power regulation.

With the goal of reducing the size and cost of off–line power supplies, there is an ever increasing demand for an economical method of obtaining a regulated galvanically isolated dc output voltage using a control which operates

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Conditions

Results

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Vin = 120VAC to 240VAC, Iout = 0.8A

V = 50mV

Load

Vin = 120VAC, Iout = 0.2A to 0.8A

V = 40mV

Vin = 240VAC, Iout = 0.2A to 0.8A

V = 40mV

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V = 290mV


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Power Factor

Vout

Vout

Iout

Iout

Ch1: 2.0V/div Ch2: 200mA/div

2.0 msec/div

Ch1: 2.0V/div Ch2: 200mV/div

Figure 11. Load Regulation 120V

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Figure 12. Load Regulation 240V


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Figure 8. Error Amplifier Large Signal Transient Response


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The pulse width modulator consists of a comparator with the oscillator ramp voltage applied to the non–inverting input, while the error amplifier output is applied into the inverting input. The Oscillator applies a set pulse to the PWM Latch while CT is discharging, and upon reaching the valley voltage, Power Switch conduction is initiated. When CT charges to a voltage that exceeds the error amplifier output, the PWM Latch is reset, thus terminating Power Switch conduction for the duration of the oscillator ramp–up period. This PWM Comparator/Latch combination prevents multiple output pulses during a given oscillator clock cycle. The timing diagram shown in Figure 18 illustrates the Power Switch duty cycle behavior versus the Compensation voltage.

The oscillator frequency is controlled by the values selected for the timing components RT and CT. Resistor RT programs the oscillator charge/discharge current via the Current Mirror 4 I output, Figure 3. Capacitor CT is charged and discharged by an equal magnitude internal current source and sink. This generates a symmetrical 50 percent duty cycle waveform at Pin 7, with a peak and valley threshold of 2.6 V and 0.6 V respectively. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the inverting input of the AND gate Driver high. This causes the Power Switch gate drive to be held in a low state, thus producing a well controlled amount of output deadtime. The amount of deadtime is relatively constant with respect to the oscillator frequency when operating below 1.0 MHz. The maximum Power Switch duty cycle at Pin 16 can be modified from the internal 50% limit by providing an additional charge or discharge current path to CT, Figure 19. In order to increase the maximum duty cycle, a discharge current resistor RD is connected from Pin 7 to ground. To decrease the maximum duty cycle, a charge current resistor RC is connected from Pin 7 to the Regulator Output. Figure 4 shows an obtainable range of maximum output duty cycle versus the ratio of either RC or RD with respect to RT.

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MC33363 Startup Control

The Power Switch is designed to directly drive the converter transformer and is capable of switching a maximum of 700 V and 1.0 A. Proper device voltage snubbing and heatsinking are required for reliable operation. A Leading Edge Blanking circuit was placed in the current sensing signal path. This circuit prevents a premature reset of the PWM Latch. The premature reset is generated each time the Power Switch is driven into conduction. It appears as a narrow voltage spike across the current sense resistor, and is due to the MOSFET gate to source capacitance, transformer interwinding capacitance, and output rectifier recovery time. The Leading Edge Blanking circuit has a dynamic behavior in that it masks the current signal until the Power Switch turn–on transition is completed. The current limit propagation delay time is typically 233 ns. This time is measured from when an overcurrent appears at the Power Switch drain, to the beginning of turn–off.

An internal Startup Control circuit with a high voltage enhancement mode MOSFET is included within the MC33363. This circuitry allows for increased converter efficiency by eliminating the external startup resistor, and its associated power dissipation, commonly used in most off–line converters that utilize a UC3842 type of controller. Rectified ac line voltage is applied to the Startup Input, Pin 1. This causes the MOSFET to enhance and supply internal bias as well as charge current to the VCC bypass capacitor that connects from Pin 3 to ground. When VCC reaches the UVLO upper threshold of 15.2 V, the IC commences operation and the startup MOSFET is turned off. Operating bias is now derived from the auxiliary transformer winding, and all of the device power is efficiently converted down from the rectified ac line. The startup MOSFET will provide an initial peak current of 20 mA, Figure 10, which decreases rapidly as VCC and the die temperature rise. The steady state current will self limit in the range of 8.0 mA with VCC shorted to ground. The startup MOSFET is rated at a maximum of 400 V with VCC shorted to ground, and 500 V when charging a VCC capacitor of 1000 µF or less.

Error Amplifier

An fully compensated Error Amplifier with access to the inverting input and output is provided for primary side voltage sensing, Figure 17. It features a typical dc voltage gain of 82 dB, and a unity gain bandwidth of 1.0 MHz with 78 degrees of phase margin, Figure 5. The noninverting input is internally biased at 2.6 V ±3.1% and is not pinned out. The Error Amplifier output is pinned out for external loop compensation and as a means for directly driving the PWM Comparator. The output was designed with a limited sink current capability of 270 µA, allowing it to be easily overridden with a pull–up resistor. This is desirable in applications that require secondary side voltage sensing, Figure 20. In this application, the Voltage Feedback Input is connected to the Regulator Output. This disables the Error Amplifier by placing its output into the sink state, allowing the optocoupler transistor to directly control the PWM Comparator.

Regulator

A low current 6.5 V regulated output is available for biasing the Error Amplifier and any additional control system circuitry. It is capable of up to 10 mA and has short–circuit protection. This output requires an external bypass capacitor of at least 1.0 µF for stability. Thermal Shutdown and Package

Internal thermal circuitry is provided to protect the Power Switch in the event that the maximum junction temperature is exceeded. When activated, typically at 155°C, the Latch is forced into a ‘reset’ state, disabling the Power Switch. The Latch is allowed to ‘set’ when the Power Switch temperature falls below 145°C. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used as a substitute for proper heatsinking. The MC33363 is contained in a heatsinkable plastic dual–in–line package in which the die is mounted on a special heat tab copper alloy lead frame. This tab consists of the four center ground pins that are specifically designed to improve thermal conduction from the die to the circuit board. Figures 15 and 17 show a simple and effective method of utilizing the printed circuit board medium as a heat dissipater by soldering these pins to an adequate area of copper foil. This permits the use of standard layout and mounting practices while having the ability to halve the junction to air thermal resistance. The examples are for a symmetrical layout on a single–sided board with two ounce per square foot of copper. Figure 22 shows a practical example of a printed circuit board layout that utilizes the copper foil as a heat dissipater. Note that a jumper was added to the layout from Pins 8 to 10 in order to enhance the copper area near the device for improved thermal conductivity. The application circuit requires two ounce copper foil in order to obtain 8.0 watts of continuous output power at room temperature.


An Overvoltage Protection Comparator is included to eliminate the possibility of runaway output voltage. This condition can occur if the control loop feedback signal path is broken due to an external component or connection failure. The comparator is normally used to monitor the primary side VCC voltage. When the 2.6 V threshold is exceeded, it will immediately turn off the Power Switch, and protect the load from a severe overvoltage condition. This input can also be driven from external circuitry to inhibit converter operation. Undervoltage Lockout

An Undervoltage Lockout comparator has been incorporated to guarantee that the integrated circuit has sufficient voltage to be fully functional before the output stage is enabled. The UVLO comparator monitors the VCC voltage at Pin 3 and when it exceeds 14.5 V, the reset signal is removed from the PWM Latch allowing operation of the Power Switch. To prevent erratic switching as the threshold is crossed, 5.0 V of hysteresis is provided.


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Figure 20. 8.0 W Off–Line Converter

Test

Conditions

Results

Line Regulation

Vin = 92 Vac to 276 Vac, IO 1.6 A

∆ = 1.0 mV

Load Regulation g

Vin = 115 Vac, IO = 0.4 A to 1.6 A

∆ = 4.0 mV

Vin = 230 Vac, IO = 0.4 A to 1.6 A

∆ = 4.0 mV

Vin = 115 Vac, IO = 1.6 A

Triangular = 2.0 mVpp, Spike = 12 mVpp

Vin = 230 Vac, IO = 1.6 A


Vin = 115 Vac, IO = 1.6 A

78.6%*

Vin = 230 Vac, IO = 1.6 A

75.6%

Output Ripple

Efficiencyy

This data was taken with the components listed below mounted on the printed circuit board shown in Figure 22. * With MBR2535CTL, 79.8% efficiency. PCB layout modification is required to use this rectifier. For high efficiency and small circuit board size, the Sanyo Os–Con capacitors are recommended for C8, C9, C10 and C11. C8, C9, C10 = Sanyo Os–Con #6SA330M, 330 µF 6.3 V. C11 = Sanyo Os–Con #10SA220M, 220 µF 10 V. L1 = Coilcraft S5088–A, 5.0 µH, 0.11 Ω. T1 = Coilcraft S5502–A Primary: 77 turns of # 28 AWG, Pin 1 = start, Pin 8 = finish. Two layers 0.002″ Mylar tape. Secondary: 5 turns of # 22 AWG, 2 strands bifiliar wound, Pin 5 = start, Pin 4 = finish. Two layers 0.002″ Mylar tape. Auxiliary: 13 turns of # 28 AWG wound in center of bobbin, Pin 2 = start, Pin 7 = finish. Two layers 0.002″ Mylar tape. Gap: 0.006″ total for a primary inductance (LP) of 1.0 mH. Core and Bobbin: Coilcraft PT1950, E187, 3F3 material.

Figure 21. Converter Test Data


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Figure 22. Printed Circuit Board and Component Layout (Circuit of Figure 20) http://onsemi.com 1030

""")" ; + The MC33363A is a monolithic high voltage switching regulator that is specifically designed to operate from a rectified 240 Vac line source. This integrated circuit features an on–chip 700 V/1.5 A SenseFET power switch, 500 V active off–line startup FET, duty cycle controlled oscillator, current limiting comparator with a programmable threshold and leading edge blanking, latching pulse width modulator for double pulse suppression, high gain error amplifier, and a trimmed internal bandgap reference. Protective features include cycle–by–cycle current limiting, input undervoltage lockout with hysteresis, output overvoltage protection, and thermal shutdown. This device is available in a 16–lead dual–in–line and wide body surface mount packages. • Enhanced Power Capability Over MC33363 • On–Chip 700 V, 1.5 A SenseFET Power Switch • Rectified 240 Vac Line Source Operation • On–Chip 500 V Active Off–Line Startup FET • Latching PWM for Double Pulse Suppression • Cycle–By–Cycle Current Limiting • Input Undervoltage Lockout with Hysteresis • Output Overvoltage Protection Comparator • Trimmed Internal Bandgap Reference • Internal Thermal Shutdown

http://onsemi.com MARKING DIAGRAMS

PDIP–16 P SUFFIX CASE 648E

MC33363AP AWLYYWW

SO–16W DW SUFFIX CASE 751N

MC33363ADW AWLYYWW

16 1

16 1

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Figure 1. Simplified Application  Semiconductor Components Industries, LLC, 2001


1031

Publication Order Number: MC33363A/D

MC33363A MAXIMUM RATINGS (Note 1)

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Power Switch (Pin 16) Drain Voltage Drain Current

Symbol

Value

Unit

VDS IDS

700 1.5

V A

Startup Input Voltage (Pin 1, Note 2) Pin 3 = Gnd Pin 3 ≤ 1000 µF to ground

Vin

V

Power Supply Voltage (Pin 3)

VCC

40

V

Input Voltage Range Voltage Feedback Input (Pin 10) Compensation (Pin 9) Overvoltage Protection Input (Pin 11) RT (Pin 6) CT (Pin 7)

VIR

–1.0 to Vreg

V

400 500

°C/W

Thermal Characteristics P Suffix, Dual–In–Line Case 648E Thermal Resistance, Junction–to–Air Thermal Resistance, Junction–to–Case (Pins 4, 5, 12, 13) DW Suffix, Surface Mount Case 751N Thermal Resistance, Junction–to–Air Thermal Resistance, Junction–to–Case (Pins 4, 5, 12, 13) Refer to Figures 16 and 17 for additional thermal information.

RθJA RθJC

80 15

RθJA RθJC

95 15


TJ

–25 to +150

°C

Storage Temperature

Tstg

–55 to +150

°C

ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 µF, for typical values TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies (Note 3), unless otherwise noted.)

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Symbol

Min

Typ

Max

Unit

Output Voltage (IO = 0 mA, TJ = 25°C)

Vreg

5.5

6.5

7.5

V

Line Regulation (VCC = 20 V to 40 V)

Regline

–

30

500

mV

Load Regulation (IO = 0 mA to 10 mA)

Regload

–

44

200

mV

Vreg

5.3

–

8.0

V

REGULATOR (Pin 8)

Total Output Variation over Line, Load, and Temperature

OSCILLATOR (Pin 7)

Frequency CT = 390 pF TJ = 25°C (VCC = 20 V) TJ = Tlow to Thigh (VCC = 20 V to 40 V) CT = 2.0 nF TJ = 25°C (VCC = 20 V) TJ = Tlow to Thigh (VCC = 20 V to 40 V)

fOSC

∆fOSC/∆V

Frequency Change with Voltage (VCC = 20 V to 40 V)

1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL–STD–883, Method 3015. Machine Model Method 200 V. 2. Maximum power dissipation limits must be observed. 3. Tested junction temperature range for the MC33363A: Thigh = +125°C Tlow = –25°C


kHz

260 255

285 –

310 315

60 59

67.5 –

75 76

–

0.1

2.0

kHz

MC33363A ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 µF, for typical values TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies (Note 4), unless otherwise noted.)

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Symbol

Min

Typ

Max

Unit

VFB

2.52

2.6

2.68

V

Regline

–

0.6

5.0

mV

IIB

–

20

500

nA

Open Loop Voltage Gain (TJ = 25°C)

AVOL

–

82

–

dB

Gain Bandwidth Product (f = 100 kHz, TJ = 25°C)

GBW

–

1.0

–

MHz

Output Voltage Swing High State (ISource = 100 µA, VFB < 2.0 V) Low State (ISink = 100 µA, VFB > 3.0 V)

VOH VOL

4.0 –

5.3 0.2

– 0.35

Input Threshold Voltage

Vth

2.47

2.6

2.73

V

Input Bias Current (Vin = 2.6 V)

IIB

–

100

500

nA

DC(max) DC(min)

48 –

50 0

52 0

– –

7.5 –

9.0 20

– –

0.2 0.2

100 100

ERROR AMPLIFIER (Pins 9, 10)

Voltage Feedback Input Threshold

Line Regulation (VCC = 20 V to 40 V, TJ = 25°C) Input Bias Current (VFB = 2.6 V)

V

OVERVOLTAGE DETECTION (Pin 11)

PWM COMPARATOR (Pins 7, 9) Duty Cycle Maximum (VFB = 0 V) Minimum (VFB = 2.7 V)

%

POWER SWITCH (Pin 16)

Drain–Source On–State Resistance (ID = 200 mA) TJ = 25°C TJ = Tlow to Thigh

Ω

RDS(on)

Drain–Source Off–State Leakage Current TJ = 25°C to 125°C, VDS = 700 V TJ = –25°C, VDS = 650 V

µA

ID(off)

Rise Time

tr

–

50

–

ns

Fall Time

tf

–

50

–

ns

Ilim

0.7

0.9

1.1

A

– –

22 6.0

– –

OVERCURRENT COMPARATOR (Pin 16) Current Limit Threshold (RT = 13 k)

STARTUP CONTROL (Pin 1)

Peak Startup Current (Vin = 400 V) VCC = 0 V VCC = (Vth(on) – 0.2 V)

Istart

mA

Off–State Leakage Current (Vin = 50 V, VCC = 20 V)

ID(off)

–

40

200

µA

Vth(on)

11

14.9

18

V

VCC(min)

7.5

9.5

11.5

V

– –

0.27 3.4

0.5 5.0

UNDERVOLTAGE LOCKOUT (Pin 3) Startup Threshold (VCC Increasing)

Minimum Operating Voltage After Turn–On

TOTAL DEVICE (Pin 3)

Power Supply Current Startup (VCC = 10 V, Pin 1 Open) Operating

ICC

4. Tested junction temperature range for the MC33363A: Thigh = +125°C Tlow = –25°C


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Current Limit Comparator and Power Switch The MC33363A uses cycle–by–cycle current limiting as a means of protecting the output switch transistor from overstress. Each on–cycle is treated as a separate situation. Current limiting is implemented by monitoring the output switch current buildup during conduction, and upon sensing an overcurrent condition, immediately turning off the switch for the duration of the oscillator ramp–up period. The Power Switch is constructed as a SenseFET allowing a virtually lossless method of monitoring the drain current. It consists of a total of 2819 cells, of which 65 are connected to a 6.0 Ω ground–referenced sense resistor. The Current Sense Comparator detects if the voltage across the sense resistor exceeds the reference level that is present at the inverting input. If exceeded, the comparator quickly resets the PWM Latch, thus protecting the Power Switch. The current limit reference level is generated by the 2.25 I output of the Current Mirror. This current causes a reference voltage to appear across the 450 Ω resistor. This voltage level, as well as the Oscillator charge/discharge current are both set by resistor RT. Therefore when selecting the values for RT and CT, RT must be chosen first to set the Power Switch peak drain current, while CT is chosen second to set the desired Oscillator frequency. A graph of the Power Switch peak drain current versus RT is shown in Figure 3 with the related formula below.

5"

f [

PWM Comparator and Latch The pulse width modulator consists of a comparator with the oscillator ramp voltage applied to the non–inverting input, while the error amplifier output is applied into the inverting input. The Oscillator applies a set pulse to the PWM Latch while CT is discharging, and upon reaching the valley voltage, Power Switch conduction is initiated. When CT charges to a voltage that exceeds the error amplifier output, the PWM Latch is reset, thus terminating Power Switch conduction for the duration of the oscillator ramp–up period. This PWM Comparator/Latch combination prevents multiple output pulses during a given oscillator clock cycle. The timing diagram shown in Figure 19 illustrates the Power Switch duty cycle behavior versus the Compensation voltage.

Oscillator and Current Mirror The oscillator frequency is controlled by the values selected for the timing components RT and CT. Resistor RT programs the oscillator charge/discharge current via the Current Mirror 4 I output, Figure 4. Capacitor CT is charged and discharged by an equal magnitude internal current source and sink. This generates a symmetrical 50 percent duty cycle waveform at Pin 7, with a peak and valley threshold of 2.6 V and 0.6 V respectively. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the inverting input of the AND gate Driver high. This causes the Power Switch gate drive to be held in a low state, thus producing a well controlled amount of output deadtime. The amount of deadtime is relatively constant with respect to the oscillator frequency when operating below 1.0 MHz. The maximum Power Switch duty cycle at Pin 16 can be modified from the internal 50% limit by providing an additional charge or discharge current path to CT, Figure 20. In order to increase the maximum duty cycle, a discharge current resistor RD is connected from Pin 7 to ground. To decrease the maximum duty cycle, a charge current resistor RC is connected from Pin 7 to the Regulator Output. Figure 5 shows an obtainable range of maximum output duty cycle versus the ratio of either RC or RD with respect to RT. ,+$

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MC33363A The Power Switch is designed to directly drive the converter transformer and is capable of switching a maximum of 700 V and 1.0 A. Proper device voltage snubbing and heatsinking are required for reliable operation. A Leading Edge Blanking circuit was placed in the current sensing signal path. This circuit prevents a premature reset of the PWM Latch. The premature reset is generated each time the Power Switch is driven into conduction. It appears as a narrow voltage spike across the current sense resistor, and is due to the MOSFET gate to source capacitance, transformer interwinding capacitance, and output rectifier recovery time. The Leading Edge Blanking circuit has a dynamic behavior in that it masks the current signal until the Power Switch turn–on transition is completed. The current limit propagation delay time is typically 300 ns. This time is measured from when an overcurrent appears at the Power Switch drain, to the beginning of turn–off.

Power Switch. To prevent erratic switching as the threshold is crossed, 5.0 V of hysteresis is provided. Startup Control An internal Startup Control circuit with a high voltage enhancement mode MOSFET is included within the MC33363A. This circuitry allows for increased converter efficiency by eliminating the external startup resistor, and its associated power dissipation, commonly used in most off–line converters that utilize a UC3842 type of controller. Rectified ac line voltage is applied to the Startup Input, Pin 1. This causes the MOSFET to enhance and supply internal bias as well as charge current to the VCC bypass capacitor that connects from Pin 3 to ground. When VCC reaches the UVLO upper threshold of 15.2 V, the IC commences operation and the startup MOSFET is turned off. Operating bias is now derived from the auxiliary transformer winding, and all of the device power is efficiently converted down from the rectified ac line. The startup MOSFET will provide an initial peak current of 20 mA, Figure 11, which decreases rapidly as VCC and the die temperature rise. The steady state current will self limit in the range of 8.0 mA with VCC shorted to ground. The startup MOSFET is rated at a maximum of 400 V with VCC shorted to ground, and 500 V when charging a VCC capacitor of 1000 µF or less.

Error Amplifier An fully compensated Error Amplifier with access to the inverting input and output is provided for primary side voltage sensing, Figure 18. It features a typical dc voltage gain of 82 dB, and a unity gain bandwidth of 1.0 MHz with 78 degrees of phase margin, Figure 6. The noninverting input is internally biased at 2.6 V ±3.1% and is not pinned out. The Error Amplifier output is pinned out for external loop compensation and as a means for directly driving the PWM Comparator. The output was designed with a limited sink current capability of 270 µA, allowing it to be easily overridden with a pull–up resistor. This is desirable in applications that require secondary side voltage sensing, Figure 21. In this application, the Voltage Feedback Input is connected to the Regulator Output. This disables the Error Amplifier by placing its output into the sink state, allowing the optocoupler transistor to directly control the PWM Comparator.

Regulator A low current 6.5 V regulated output is available for biasing the Error Amplifier and any additional control system circuitry. It is capable of up to 10 mA and has short–circuit protection. This output requires an external bypass capacitor of at least 1.0 µF for stability. Thermal Shutdown and Package Internal thermal circuitry is provided to protect the Power Switch in the event that the maximum junction temperature is exceeded. When activated, typically at 155°C, the Latch is forced into a ‘reset’ state, disabling the Power Switch. The Latch is allowed to ‘set’ when the Power Switch temperature falls below 145°C. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used as a substitute for proper heatsinking. The MC33363A is contained in a heatsinkable plastic dual–in–line package in which the die is mounted on a special heat tab copper alloy lead frame. This tab consists of the four center ground pins that are specifically designed to improve thermal conduction from the die to the circuit board. Figures 16 and 17 show a simple and effective method of utilizing the printed circuit board medium as a heat dissipater by soldering these pins to an adequate area of copper foil. This permits the use of standard layout and mounting practices while having the ability to halve the junction to air thermal resistance. The examples are for a symmetrical layout on a single–sided board with two ounce per square foot of copper. Figure 23 shows a practical example of a printed circuit board layout

Overvoltage Protection An Overvoltage Protection Comparator is included to eliminate the possibility of runaway output voltage. This condition can occur if the control loop feedback signal path is broken due to an external component or connection failure. The comparator is normally used to monitor the primary side VCC voltage. When the 2.6 V threshold is exceeded, it will immediately turn off the Power Switch, and protect the load from a severe overvoltage condition. This input can also be driven from external circuitry to inhibit converter operation. Undervoltage Lockout An Undervoltage Lockout comparator has been incorporated to guarantee that the integrated circuit has sufficient voltage to be fully functional before the output stage is enabled. The UVLO comparator monitors the VCC voltage at Pin 3 and when it exceeds 14.5 V, the reset signal is removed from the PWM Latch allowing operation of the


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Figure 21. 15 W Off–Line Converter Test

Conditions

Results

Line Regulation


∆ = 1.0 mV

Load Regulation g

Vin = 115 Vac, IO = 0.75 A to 3.0 A

∆ = 5.0 mV

Vin = 230 Vac, IO = 0.75 A to 3.0 A

∆ = 5.0 mV

Vin = 115 Vac, IO = 3.0 A


Vin = 230 Vac, IO = 3.0 A


Vin = 115 Vac, IO = 3.0 A

76.8%*

Vin = 230 Vac, IO = 3.0 A

76.8%

Output Ripple

Efficiencyy

This data was taken with the components listed below mounted on the printed circuit board shown in Figure 23. * With MBR2535CTL, 78.8% efficiency. PCB layout modification is required to use this rectifier. For high efficiency and small circuit board size, the Sanyo Os–Con capacitors are recommended for C8, C9, C10 and C11. C8, C9, C10 = Sanyo Os–Con #6SA330M, 330 µF 6.3 V. C11 = Sanyo Os–Con #10SA220M, 220 µF 10 V. L1 = Coilcraft S5088–A, 5.0 µH, 0.11 Ω. T1 = Coilcraft U6875–A Primary: 77 turns of # 28 AWG, Pin 1 = start, Pin 8 = finish. Two layers 0.002″ Mylar tape. Secondary: 5 turns of # 22 AWG, 2 strands bifiliar wound, Pin 5 = start, Pin 4 = finish. Two layers 0.002″ Mylar tape. Auxiliary: 13 turns of # 28 AWG wound in center of bobbin, Pin 2 = start, Pin 7 = finish. Two layers 0.002″ Mylar tape. Gap: 0.011″ total for a primary inductance (LP) of 620 µH. Core and Bobbin: Coilcraft PT1950, E187, 3F3 material.

Figure 22. Converter Test Data http://onsemi.com 1041

>9 $&;>9$4

5$

5 9 5 >9

MC33363A Caution! High Voltages

5 5

, ,

,

,3

H

,

=5

=5

,9

5

5 5

5 =5

* 45 " ="

,

, 5

,

59

53

, 1

5

,

5

5

5

1 &! > R

> R

MC33363A

- &!


""")"! ; + The MC33363B is a monolithic high voltage switching regulator that is specifically designed to operate from a rectified 240 Vac line source. This integrated circuit features an on–chip 700 V/1.0 A SENSEFET power switch, 450 V active off–line startup FET, duty cycle controlled oscillator, current limiting comparator with a programmable threshold and leading edge blanking, latching pulse width modulator for double pulse suppression, high gain error amplifier, and a trimmed internal bandgap reference. Protective features include cycle–by–cycle current limiting, input undervoltage lockout with hysteresis, overvoltage protection, and thermal shutdown. This device is available in a 16–lead dual–in–line and wide body surface mount packages. • On–Chip 700 V, 1.0 A SENSEFET Power Switch • Rectified 240 Vac Line Source Operation • On–Chip 450 V Active Off–Line Startup FET • Latching PWM for Double Pulse Suppression • Cycle–By–Cycle Current Limiting • Input Undervoltage Lockout with Hysteresis • Over–Voltage Protection • Trimmed Internal Bandgap Reference • Internal Thermal Shutdown



MC33363BP AWLYYWW

16 1 SO–16W DW SUFFIX CASE 751N

16

MC33363BDW AWLYYWW

1 A WL YY WW


PIN CONNECTIONS ="

&55

45 =" =" ,+

,

2&

&

,1 51

6

@

7

@@+ " ="

,1

51

9

,+

3

5

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"

"# @@+ " =" &+ *#/' =" 5" "

1 &!

,

6

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85" "

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3 84 "#

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G G G

9 &+ *#/' ="

Device

Package

Shipping

MC33363BDW

SO–16W

47 Units/Rail

MC33363BDWR2

SO–16W

1000 Tape & Reel

MC33363BP

PDIP–16

25 Units/Rail




1043

Publication Order Number: MC33363B/D

MC33363B MAXIMUM RATINGS (Note 1)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating


Symbol

Value

Unit

VDS IDS

700 1.0

V A


Vin

V


VCC

40

V


VIR

–1.0 to Vreg

V

400 500

°C/W

Thermal Characteristics P Suffix, Dual–In–Line Case 648E Thermal Resistance, Junction–to–Air Thermal Resistance, Junction–to–Case DW Suffix, Surface Mount Case 751G Thermal Resistance, Junction–to–Air Thermal Resistance, Junction–to–Case

RθJA RθJC

80 15

RθJA RθJC

95 15


TJ

–25 to +150

°C

Storage Temperature

Tstg

–55 to +150

°C

8 = 1.0 µF, for typical values TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies (Note 3), unless otherwise noted.)

ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Characteristic

Symbol

Min

Typ

Max

Unit


Vreg

5.5

6.5

7.5

V


Regline

–

30

500

mV


Regload

–

44

200

mV

Vreg

5.3

–

8.0

V

REGULATOR (Pin 8)


OSCILLATOR (Pin 7)


fOSC

∆fOSC/∆V


1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL–STD–883, Method 3015. Machine Model Method 200 V. 2. Maximum power dissipation limits must be observed. 3. Tested junction temperature range for the MC33363B: Thigh = +125°C Tlow = –25°C


kHz

260 255

285 –

310 315

60 59

67.5 –

75 76

–

0.1

2.0

kHz

MC33363B 8 = 1.0 µF, for typical values TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies (Note 4), unless otherwise noted.)


ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Characteristic

Symbol

Min

Typ

Max

Unit

VFB

2.52

2.6

2.68

V

Line Regulation (VCC = 20 V to 40 V, TJ = 25°C)

Regline

–

0.6

5.0

mV

Input Bias Current (VFB = 2.6 V, TJ = 0 – 125°C)

IIB

–

20

500

nA


AVOL

70

82

94

dB


GBW

0.85

1.0

1.15

MHz


VOH VOL

4.0 –

5.3 0.2

– 0.35


Vth

2.47

2.6

2.73

V

Input Bias Current (Vin = 2.6 V, TJ = –25 – 125°C)

IIB

–

100

500

nA

DC(max) DC(min)

48 –

50 0

52 0

– –

15 –

17 39

–

0.2

100



V



%



Ω

RDS(on)

Drain–Source Off–State Leakage Current VDS = 650 V

µA

ID(off)

Rise Time

tr

–

50

–

ns

Fall Time

tf

–

50

–

ns

Ilim

0.5

0.72

0.9

A

– –

2.0 2.0

4.0 4.0



Peak Startup Current (Vin = 400 V) (Note 5) VCC = 0 V VCC = (Vth(on) – 0.2 V)

Istart

mA


ID(off)

–

40

200

µA

Vth(on)

11

15.2

18

V

VCC(min)

7.5

9.5

11.5

V

– –

0.25 3.2

0.5 5.0





ICC

4. Tested junction temperature range for the MC33363B: Thigh = +125°C Tlow = –25°C 5. The device can only guarantee to start up at high temperature below +115°C.


mA

% 5G$5=41,$*,87289$ 99$'

51 F 99 *

= JG$68,$6=15($84J$ ,4=9 "* 51 F 9 "*

9$' >9

9

9

9

9

9

,1G 1==9 "* 14 F °5

, ;,1 ,

, " "#

1==

="# +0 @+ "# "#" @+ #E # =' "%% @# >9 µ >

9 " # "#

>9

&%

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Current Limit Comparator and Power Switch The MC33363B uses cycle–by–cycle current limiting as a means of protecting the output switch transistor from overstress. Each on–cycle is treated as a separate situation. Current limiting is implemented by monitoring the output switch current buildup during conduction, and upon sensing an overcurrent condition, immediately turning off the switch for the duration of the oscillator ramp–up period. The Power Switch is constructed as a SENSEFET allowing a virtually lossless method of monitoring the drain current. It consists of a total of 1462 cells, of which 36 are connected to a 8.1 Ω ground–referenced sense resistor. The Current Sense Comparator detects if the voltage across the sense resistor exceeds the reference level that is present at the inverting input. If exceeded, the comparator quickly resets the PWM Latch, thus protecting the Power Switch. The current limit reference level is generated by the 2.25 I output of the Current Mirror. This current causes a reference voltage to appear across the 405 Ω resistor. This voltage level, as well as the Oscillator charge/discharge current are both set by resistor RT. Therefore when selecting the values for RT and CT, RT must be chosen first to set the Power Switch peak drain current, while CT is chosen second to set the desired Oscillator frequency. A graph of the Power Switch peak drain current versus RT is shown in Figure 3 with the related formula below.

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Oscillator and Current Mirror The oscillator frequency is controlled by the values selected for the timing components RT and CT. Resistor RT programs the oscillator charge/discharge current via the Current Mirror 4 I output, Figure 4. Capacitor CT is charged and discharged by an equal magnitude internal current source and sink. This generates a symmetrical 50 percent duty cycle waveform at Pin 7, with a peak and valley threshold of 2.6 V and 0.6 V respectively. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the inverting input of the AND gate Driver high. This causes the Power Switch gate drive to be held in a low state, thus producing a well controlled amount of output deadtime. The amount of deadtime is relatively constant with respect to the oscillator frequency when operating below 1.0 MHz. The maximum Power Switch duty cycle at Pin 16 can be modified from the internal 50% limit by providing an additional charge or discharge current path to CT, Figure 20. In order to increase the maximum duty cycle, a discharge current resistor RD is connected from Pin 7 to ground. To decrease the maximum duty cycle, a charge current resistor RC is connected from Pin 7 to the Regulator Output. Figure 5 shows an obtainable range of maximum output duty cycle versus the ratio of either RC or RD with respect to RT.

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MC33363B Startup Control An internal Startup Control circuit with a high voltage enhancement mode MOSFET is included within the MC33363B. This circuitry allows for increased converter efficiency by eliminating the external startup resistor, and its associated power dissipation, commonly used in most off–line converters that utilize a UC3842 type of controller. Rectified ac line voltage is applied to the Startup Input, Pin 1. This causes the MOSFET to enhance and supply internal bias as well as charge current to the VCC bypass capacitor that connects from Pin 3 to ground. When VCC reaches the UVLO upper threshold of 15.2 V, the IC commences operation and the startup MOSFET is turned off. Operating bias is now derived from the auxiliary transformer winding, and all of the device power is efficiently converted down from the rectified ac line. The startup MOSFET will provide a steady current of 1.7 mA, Figure 11, as VCC increases or shorted to ground. The startup MOSFET is rated at a maximum of 400 V with VCC shorted to ground, and 500 V when charging a VCC capacitor of 1000 µF or less.

The Power Switch is designed to directly drive the converter transformer and is capable of switching a maximum of 700 V and 1.0 A. Proper device voltage snubbing and heatsinking are required for reliable operation. A Leading Edge Blanking circuit was placed in the current sensing signal path. This circuit prevents a premature reset of the PWM Latch. The premature reset is generated each time the Power Switch is driven into conduction. It appears as a narrow voltage spike across the current sense resistor, and is due to the MOSFET gate to source capacitance, transformer interwinding capacitance, and output rectifier recovery time. The Leading Edge Blanking circuit has a dynamic behavior in that it masks the current signal until the Power Switch turn–on transition is completed. The current limit propagation delay time is typically 262 ns. This time is measured from when an overcurrent appears at the Power Switch drain, to the beginning of turn–off. Error Amplifier An fully compensated Error Amplifier with access to the inverting input and output is provided for primary side voltage sensing, Figure 18. It features a typical dc voltage gain of 82 dB, and a unity gain bandwidth of 1.0 MHz with 78 degrees of phase margin, Figure 6. The noninverting input is internally biased at 2.6 V ±3.1% and is not pinned out. The Error Amplifier output is pinned out for external loop compensation and as a means for directly driving the PWM Comparator. The output was designed with a limited sink current capability of 270 µA, allowing it to be easily overridden with a pull–up resistor. This is desirable in applications that require secondary side voltage sensing.

Regulator A low current 6.5 V regulated output is available for biasing the Error Amplifier and any additional control system circuitry. It is capable of up to 10 mA and has short–circuit protection. This output requires an external bypass capacitor of at least 1.0 µF for stability. Thermal Shutdown and Package Internal thermal circuitry is provided to protect the Power Switch in the event that the maximum junction temperature is exceeded. When activated, typically at 150°C, the Latch is forced into a ‘reset’ state, disabling the Power Switch. The Latch is allowed to ‘set’ when the Power Switch temperature falls below 140°C. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used as a substitute for proper heatsinking. The MC33363B is contained in a heatsinkable plastic dual–in–line package in which the die is mounted on a special heat tab copper alloy lead frame. This tab consists of the four center ground pins that are specifically designed to improve thermal conduction from the die to the circuit board. Figures 16 and 17 show a simple and effective method of utilizing the printed circuit board medium as a heat dissipater by soldering these pins to an adequate area of copper foil. This permits the use of standard layout and mounting practices while having the ability to halve the junction to air thermal resistance. The examples are for a symmetrical layout on a single–sided board with two ounce per square foot of copper.

Overvoltage Protection An Overvoltage Protection Comparator is included to eliminate the possibility of runaway output voltage. This condition can occur if the control loop feedback signal path is broken due to an external component or connection failure. The comparator is normally used to monitor the primary side VCC voltage. When the 2.6 V threshold is exceeded, it will immediately turn off the Power Switch, and protect the load from a severe overvoltage condition. This input can also be driven from external circuitry to inhibit converter operation. Undervoltage Lockout An Undervoltage Lockout comparator has been incorporated to guarantee that the integrated circuit has sufficient voltage to be fully functional before the output stage is enabled. The UVLO comparator monitors the VCC voltage at Pin 3 and when it exceeds 14.5 V, the reset signal is removed from the PWM Latch allowing operation of the Power Switch. To prevent erratic switching as the threshold is crossed, 5.0 V of hysteresis is provided.


"""), ; + The MC33365 is a monolithic high voltage switching regulator that is specifically designed to operate from a rectified 240 Vac line source. This integrated circuit features an on–chip 700 V/1.0 A SENSEFETt power switch, 450 V active off–line startup FET, duty cycle controlled oscillator, current limiting comparator with a programmable threshold and leading edge blanking, latching pulse width modulator for double pulse suppression, high gain error amplifier, and a trimmed internal bandgap reference. Protective features include cycle–by–cycle current limiting, input undervoltage lockout with hysteresis, bulk capacitor voltage sensing, and thermal shutdown. This device is available in a 16–lead dual–in–line package. • On–Chip 700 V, 1.0 A SENSEFET Power Switch • Rectified 240 Vac Line Source Operation • On–Chip 450 V Active Off–Line Startup FET • Latching PWM for Double Pulse Suppression • Cycle–By–Cycle Current Limiting • Input Undervoltage Lockout with Hysteresis • Bulk Capacitor Voltage Comparator • Trimmed Internal Bandgap Reference • Internal Thermal Shutdown

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October, 2001– Rev. 2

1053



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Symbol

Value

Unit

VDS IDS

700 1.0

V A


Vin

V


VCC

40

V

Input Voltage Range Voltage Feedback Input (Pin 10) Compensation (Pin 9) Bulk OK Input (Pin 11) RT (Pin 6) CT (Pin 7)

VIR

–1.0 to Vreg

V

400 500

°C/W

Thermal Characteristics P Suffix, Dual–In–Line Case 648E Thermal Resistance, Junction–to–Air Thermal Resistance, Junction–to–Case

RθJA RθJC

80 15


TJ

–25 to +125

°C

Storage Temperature

Tstg

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°C


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Symbol

Min

Typ

Max

Unit


Vreg

5.5

6.5

7.5

V


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–

30

500

mV


Regload

–

44

200

mV

Vreg

5.3

–

8.0

V

REGULATOR (Pin 8)


OSCILLATOR (Pin 7)


fOSC

kHz

260 255

285 –

310 315

60 59

67.5 –

75 76

∆fOSC/∆V

–

0.1

2.0

kHz

VFB

2.52

2.6

2.68

V

Line Regulation (VCC = 20 V to 40 V, TJ = 25°C)

Regline

–

0.6

5.0

mV

Input Bias Current (VFB = 2.6 V, TJ = 0 – 125°C)

IIB

–

20

500

nA


AVOL

70

82

94

dB


GBW

0.85

1.0

1.15

MHz


VOH VOL

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– 0.35




V

1. Maximum power dissipation limits must be observed.


MC33365 8 = 1.0 µF, for typical values TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies, unless otherwise noted.)

ELECTRICAL CHARACTERISTICS (continued) (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Characteristic

Symbol

Min

Typ

Max

Unit


Vth

1.18

1.25

1.32

V

Input Bias Current (VBK < Vth, TJ = 0 – 125°C)

IIB

–

100

500

nA

Source Current (Turn on after VBK > Vth, TJ = 25°C – 125°C)

ISC

39

–

53

µA

DC(max) DC(min)

48 –

50 0

52 0

– –

15 –

17 39

–

0.2

100

BULK OK (Pin 11)


%


Drain–Source On–State Resistance (ID = 200 mA) TJ = 25°C TJ = –25°C to +125°C

Ω

RDS(on)

Drain–Source Off–State Leakage Current VDS = 650 V

µA

ID(off)

Rise Time

tr

–

50

–

ns

Fall Time

tf

–

50

–

ns

Ilim

0.5

0.72

0.9

A

– –

2.0 2.0

4.0 4.0



Peak Startup Current (Vin = 400 V) (Note 2) VCC = 0 V VCC = (Vth(on) – 0.2 V)

Istart

mA


ID(off)

–

40

200

µA

Vth(on)

11

15.2

18

V

VCC(min)

7.5

9.5

11.5

V

– –

0.25 3.2

0.5 5.0





ICC

mA

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Figure 11. Peak Startup Current versus Power Supply Voltage

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Figure 13. Power Switch Drain–Source Capacitance versus Voltage

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The MC33365 uses cycle–by–cycle current limiting as a means of protecting the output power switch from overstress. Each on–cycle is treated as a separate situation. Current limiting is implemented by monitoring the output switch current buildup during conduction, and upon sensing an overcurrent condition, immediately turning off the switch for the duration of the oscillator ramp–up period. The Power Switch is constructed as a SENSEFET allowing a virtually lossless method of monitoring the drain current. It consists of a total of 1462 cells, of which 36 are connected to a 8.1 Ω ground–referenced sense resistor. The Current Sense Comparator detects if the voltage across the sense resistor exceeds the reference level that is present at the inverting input. If exceeded, the comparator quickly resets the PWM Latch, thus protecting the Power Switch. The current limit reference level is generated by the 2.25 I output of the Current Mirror. This current causes a reference voltage to appear across the 405 Ω resistor. This voltage level, as well as the Oscillator charge/discharge current are both set by resistor RT. Therefore when selecting the values for RT and CT, RT must be chosen first to set the Power Switch peak drain current, while CT is chosen second to set the desired Oscillator frequency. A graph of the Power Switch peak drain current versus RT is shown in Figure 3 with the related formula below.

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pk

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T – 1.077 1000

MC33365 The Power Switch is designed to directly drive the converter transformer and is capable of switching a maximum of 700 V and 1.0 A. Proper device voltage snubbing and heatsinking are required for reliable operation. A Leading Edge Blanking circuit was placed in the current sensing signal path. This circuit prevents a premature reset of the PWM Latch. The premature reset is generated each time the Power Switch is driven into conduction. It appears as a narrow voltage spike across the current sense resistor, and is due to the MOSFET gate to source capacitance, transformer interwinding capacitance, and output rectifier recovery time. The Leading Edge Blanking circuit has a dynamic behavior in that it masks the current signal until the Power Switch turn–on transition is completed. The current limit propagation delay time is typically 262 ns. This time is measured from when an overcurrent appears at the Power Switch drain, to the beginning of turn–off.

VBULK Vref

RUpper

BOK 11


An Undervoltage Lockout comparator has been incorporated to guarantee that the integrated circuit has sufficient voltage to be fully functional before the output stage is enabled. The UVLO comparator monitors the VCC voltage at Pin 3 and when it exceeds 14.5 V, the reset signal is removed from the PWM Latch allowing operation of the Power Switch. To prevent erratic switching as the threshold is crossed, 5.0 V of hysteresis is provided. Startup Control

An internal Startup Control circuit with a high voltage enhancement mode MOSFET is included within the MC33365. This circuitry allows for increased converter efficiency by eliminating the external startup resistor, and its associated power dissipation, commonly used in most off–line converters that utilize a UC3842 type of controller. Rectified ac line voltage is applied to the Startup Input, Pin 1. This causes the MOSFET to enhance and supply internal bias as well as charge current to the VCC bypass capacitor that connects from Pin 3 to ground. When VCC reaches the UVLO upper threshold of 15.2 V, the IC commences operation and the startup MOSFET is turned off. Operating bias is now derived from the auxiliary transformer winding, and all of the device power is efficiently converted down from the rectified ac line. The startup MOSFET will provide a steady current of 1.7 mA, Figure 11, as VCC increases or shorted to ground. The startup MOSFET is rated at a maximum of 400 V with VCC shorted to ground, and 500 V when charging a VCC capacitor of 1000 µF or less.

Bulk Capacitor Voltage Comparator

In order to avoid output voltage bouncing during electricity brownout condition, a Bulk Capacitor Voltage Comparator with programmable hysteresis is included in this device. The non–inverting input, pin 11, is connected to the voltage divider comprised of RUpper and RLower as shown in Figure 20 monitoring the bulk capacitor voltage level. The inverting input is connected to a threshold voltage of 1.25 V internally. As bulk capacitor voltage drops below the pre–programmed level, (Pin 11 drops below 1.25 V), a reset signal will be generated via internal protection logic to the PWM Latch so turning off the Power Switch immediately. An internal current source controlled by the state of the comparator provides a means to program the voltage hysteresis. The following equation shows the relationship between VBULK levels and the voltage divider network resistors. in K Ohm

25

[ VBulk_H * VBulk_L ] VBulk_H * 1.25

in K Ohm

RLower +

Protection Logic

Figure 20. Bulk OK Functional Operation

An fully compensated Error Amplifier with access to the inverting input and output is provided for primary side voltage sensing, Figure 17. It features a typical dc voltage gain of 82 dB, and a unity gain bandwidth of 1.0 MHz with 78 degrees of phase margin, Figure 6. The noninverting input is internally biased at 2.6 V ±3.1% and is not pinned out. The Error Amplifier output is pinned out for external loop compensation and as a means for directly driving the PWM Comparator. The output was designed with a limited sink current capability of 270 µA, allowing it to be easily overridden with a pull–up resistor. This is desirable in applications that require secondary side voltage sensing.

[ VBulk_H * VBulk_L ]

1.25 V

RLower

Error Amplifier

RUpper + 20

50 A

Regulator

A low current 6.5 V regulated output is available for biasing the Error Amplifier and any additional control system circuitry. It is capable of up to 10 mA and has


MC33365 The MC33365 is contained in a heatsinkable plastic dual–in–line package in which the die is mounted on a special heat tab copper alloy lead frame. This tab consists of the four center ground pins that are specifically designed to improve thermal conduction from the die to the circuit board. Figure 16 shows a simple and effective method of utilizing the printed circuit board medium as a heat dissipater by soldering these pins to an adequate area of copper foil. This permits the use of standard layout and mounting practices while having the ability to halve the junction to air thermal resistance. The examples are for a symmetrical layout on a single–sided board with two ounce per square foot of copper.

short–circuit protection. This output requires an external bypass capacitor of at least 1.0 µF for stability. Thermal Shutdown and Package

Internal thermal circuitry is provided to protect the Power Switch in the event that the maximum junction temperature is exceeded. When activated, typically at 150°C, the Latch is forced into a ‘reset’ state, disabling the Power Switch. The Latch is allowed to ‘set’ when the Power Switch temperature falls below 140°C. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used as a substitute for proper heatsinking.


""") ; + The MC33362 is a monolithic high voltage switching regulator that is specifically designed to operate from a rectified 120 VAC line source. This integrated circuit features an on–chip 500 V/2.0 A SenseFET power switch, 250 V active off–line startup FET, duty cycle controlled oscillator, current limiting comparator with a programmable threshold and leading edge blanking, latching pulse width modulator for double pulse suppression, high gain error amplifier, and a trimmed internal bandgap reference. Protective features include cycle–by–cycle current limiting, input undervoltage lockout with hysteresis, output overvoltage protection, and thermal shutdown. This device is available in a 16–lead dual–in–line and wide body surface mount packages. • On–Chip 500 V, 2.0 A SenseFET Power Switch • Rectified 120 VAC Line Source Operation • On–Chip 250 V Active Off–Line Startup FET • Latching PWM for Double Pulse Suppression • Cycle–By–Cycle Current Limiting • Input Undervoltage Lockout with Hysteresis • Output Overvoltage Protection Comparator • Trimmed Internal Bandgap Reference • Internal Thermal Shutdown



MC33362P AWLYYWW

SO–16W DW SUFFIX CASE 751N

MC33362DW AWLYYWW

16 1

16 1

A WL YY WW


PIN CONNECTIONS 45 =" =" ,+

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6

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Device

Package

Shipping

MC33362DW

SO–16W

47 Units/Rail

MC33362DWR2

SO–16W

1000 Tape & Reel

MC33362P

PDIP–16

25 Units/Rail




May, 2001 – Rev. 4

1063


MC33362 MAXIMUM RATINGS (Note 1)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating


Symbol

Value

Unit

VDS IDS

500 2.0

V A


Vin

V


VCC

40

V


VIR

–1.0 to Vreg

V

250 400

°C/W

Thermal Characteristics P Suffix, Dual–In–Line Case 648E Thermal Resistance, Junction–to–Air Thermal Resistance, Junction–to–Case (Pins 4, 5, 12, 13) DW Suffix, Surface Mount Case 751N Thermal Resistance, Junction–to–Air Thermal Resistance, Junction–to–Case (Pins 4, 5, 12, 13) Refer to Figures 16 and 17 for additional thermal information.

RθJA RθJC

80 15

RθJA RθJC

95 15


TJ

– 25 to +150

°C

Storage Temperature

Tstg

– 55 to +150

°C

ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 µF, for typical values TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies (Note 3), unless otherwise noted.)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Characteristic

Symbol

Min

Typ

Max

Unit


Vreg

5.5

6.5

7.5

V


Regline

–

30

500

mV


Regload

–

44

200

mV

Vreg

5.3

–

8.0

V

REGULATOR (Pin 8)


OSCILLATOR (Pin 7)


fOSC

∆fOSC/∆V


1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL–STD–883, Method 3015. Machine Model Method 200 V. 2. Maximum power dissipation limits must be observed. 3. Tested junction temperature range for the MC33362: Thigh = +125°C Tlow = –25°C


kHz

260 255

285 –

310 315

60 59

67.5 –

75 76

–

0.1

2.0

kHz

MC33362 ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 µF, for typical values TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies (Note 4), unless otherwise noted.)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Characteristic

Symbol

Min

Typ

Max

Unit

VFB

2.52

2.6

2.68

V

Regline

–

0.6

5.0

mV

IIB

–

20

500

nA

Open Loop Voltage Gain (TJ= 25°C)

AVOL

–

82

–

dB

Gain Bandwidth Product (f = 100 kHz, TJ= 25°C)

GBW

–

1.0

–

MHz


VOH VOL

4.0 –

5.3 0.2

– 0.35


Vth

2.47

2.6

2.73

V

Input Bias Current (Vin = 2.6 V)

IIB

–

100

500

nA

DC(max) DC(min)

48 –

50 0

52 0

– –

4.4 –

6.0 12



Line Regulation (VCC = 20 V to 40 V, TJ = 25°C) Input Bias Current (VFB = 2.6 V)

V



%



Ω

RDS(on)

ID(off)

–

0.2

50

µA

Rise Time

tr

–

50

–

ns

Fall Time

tf

–

50

–

ns

Ilim

0.7

0.9

1.1

A

– –

55 26

– –

Drain–Source Off–State Leakage Current (VDS = 500 V)



Peak Startup Current (Vin = 200 V) VCC = 0 V VCC = (Vth(on) – 0.2 V)

Istart

mA


ID(off)

–

40

200

µA

Vth(on)

11

14.5

18

V

VCC(min)

7.5

9.5

11.5

V

– –

0.3 3.6

0.5 5.0





ICC

4. Tested junction temperature range for the MC33362: Thigh = +125°C Tlow = –25°C


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Current Limit Comparator and Power Switch The MC33362 uses cycle–by–cycle current limiting as a means of protecting the output switch transistor from overstress. Each on–cycle is treated as a separate situation. Current limiting is implemented by monitoring the output switch current buildup during conduction, and upon sensing an overcurrent condition, immediately turning off the switch for the duration of the oscillator ramp–up period. The Power Switch is constructed as a SenseFET allowing a virtually lossless method of monitoring the drain current. It consists of a total of 3770 cells, of which 50 are connected to a 9.0 Ω ground–referenced sense resistor. The Current Sense Comparator detects if the voltage across the sense resistor exceeds the reference level that is present at the inverting input. If exceeded, the comparator quickly resets the PWM Latch, thus protecting the Power Switch. The current limit reference level is generated by the 2.25 I output of the Current Mirror. This current causes a reference voltage to appear across the 450 Ω resistor. This voltage level, as well as the Oscillator charge/discharge current are both set by resistor RT. Therefore when selecting the values for RT and CT, RT must be chosen first to set the Power Switch peak drain current, while CT is chosen second to set the desired Oscillator frequency. A graph of the Power Switch peak drain current versus RT is shown in Figure 3 with the related formula below.

5"

f [


Oscillator and Current Mirror The oscillator frequency is controlled by the values selected for the timing components RT and CT. Resistor RT programs the oscillator charge/discharge current via the Current Mirror 4 I output, Figure 4. Capacitor CT is charged and discharged by an equal magnitude internal current source and sink. This generates a symmetrical 50 percent duty cycle waveform at Pin 7, with a peak and valley threshold of 2.6 V and 0.6 V respectively. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the inverting input of the AND gate Driver high. This causes the Power Switch gate drive to be held in a low state, thus producing a well controlled amount of output deadtime. The amount of deadtime is relatively constant with respect to the oscillator frequency when operating below 1.0 MHz. The maximum Power Switch duty cycle at Pin 16 can be modified from the internal 50% limit by providing an additional charge or discharge current path to CT, Figure 20. In order to increase the maximum duty cycle, a discharge current resistor RD is connected from Pin 7 to ground. To decrease the maximum duty cycle, a charge current resistor RC is connected from Pin 7 to the Regulator Output. Figure 5 shows an obtainable range of maximum output duty cycle versus the ratio of either RC or RD with respect to RT.

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MC33362 The Power Switch is designed to directly drive the converter transformer and is capable of switching a maximum of 500 V and 2.0 A. Proper device voltage snubbing and heatsinking are required for reliable operation. A Leading Edge Blanking circuit was placed in the current sensing signal path. This circuit prevents a premature reset of the PWM Latch. The premature reset is generated each time the Power Switch is driven into conduction. It appears as a narrow voltage spike across the current sense resistor, and is due to the MOSFET gate to source capacitance, transformer interwinding capacitance, and output rectifier recovery time. The Leading Edge Blanking circuit has a dynamic behavior in that it masks the current signal until the Power Switch turn–on transition is completed. The current limit propagation delay time is typically 233 ns. This time is measured from when an overcurrent appears at the Power Switch drain, to the beginning of turn–off.

Power Switch. To prevent erratic switching as the threshold is crossed, 5.0 V of hysteresis is provided. Startup Control An internal Startup Control circuit with a high voltage enhancement mode MOSFET is included within the MC33362. This circuitry allows for increased converter efficiency by eliminating the external startup resistor, and its associated power dissipation, commonly used in most off–line converters that utilize a UC3842 type of controller. Rectified ac line voltage is applied to the Startup Input, Pin 1. This causes the MOSFET to enhance and supply internal bias as well as charge current to the VCC bypass capacitor that connects from Pin 3 to ground. When VCC reaches the UVLO upper threshold of 14.5 V, the IC commences operation and the startup MOSFET is turned off. Operating bias is now derived from the auxiliary transformer winding, and all of the device power is efficiently converted down from the rectified ac line. The startup MOSFET will provide an initial peak current of 55 mA, Figure 11, which decreases rapidly as VCC and the die temperature rise. The steady state current will self limit in the range of 12 mA with VCC shorted to ground. The startup MOSFET is rated at a maximum of 250 V with VCC shorted to ground, and 400 V when charging a VCC capacitor of 1000 µF or less.

Error Amplifier An fully compensated Error Amplifier with access to the inverting input and output is provided for primary side voltage sensing, Figure 18. It features a typical dc voltage gain of 82 dB, and a unity gain bandwidth of 1.0 MHz with 78 degrees of phase margin, Figure 6. The noninverting input is internally biased at 2.6 V ±3.1% and is not pinned out. The Error Amplifier output is pinned out for external loop compensation and as a means for directly driving the PWM Comparator. The output was designed with a limited sink current capability of 270 µA, allowing it to be easily overridden with a pull–up resistor. This is desirable in applications that require secondary side voltage sensing, Figure 21. In this application, the Voltage Feedback Input is connected to the Regulator Output. This disables the Error Amplifier by placing its output into the sink state, allowing the optocoupler transistor to directly control the PWM Comparator.

Regulator A low current 6.5 V regulated output is available for biasing the Error Amplifier and any additional control system circuitry. It is capable of up to 10 mA and has short–circuit protection. This output requires an external bypass capacitor of at least 1.0 µF for stability. Thermal Shutdown and Package Internal thermal circuitry is provided to protect the Power Switch in the event that the maximum junction temperature is exceeded. When activated, typically at 155°C, the Latch is forced into a ‘reset’ state, disabling the Power Switch. The Latch is allowed to ‘set’ when the Power Switch temperature falls below 145°C. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used as a substitute for proper heatsinking. The MC33362 is contained in a heatsinkable plastic dual–in–line package in which the die is mounted on a special heat tab copper alloy lead frame. This tab consists of the four center ground pins that are specifically designed to improve thermal conduction from the die to the circuit board. Figures 16 and 17 show a simple and effective method of utilizing the printed circuit board medium as a heat dissipater by soldering these pins to an adequate area of copper foil. This permits the use of standard layout and mounting practices while having the ability to halve the junction to air thermal resistance. The examples are for a symmetrical layout on a single–sided board with two ounce per square foot of copper. Figure 23 shows a practical example of a printed circuit board layout

Overvoltage Protection An Overvoltage Protection Comparator is included to eliminate the possibility of runaway output voltage. This condition can occur if the control loop feedback signal path is broken due to an external component or connection failure. The comparator is normally used to monitor the primary side VCC voltage. When the 2.6 V threshold is exceeded, it will immediately turn off the Power Switch, and protect the load from a severe overvoltage condition. This input can also be driven from external circuitry to inhibit converter operation. Undervoltage Lockout An Undervoltage Lockout comparator has been incorporated to guarantee that the integrated circuit has sufficient voltage to be fully functional before the output stage is enabled. The UVLO comparator monitors the VCC voltage at Pin 3 and when it exceeds 14.5 V, the reset signal is removed from the PWM Latch allowing operation of the


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conductivity. The application circuit requires two ounce copper foil in order to obtain 20 watts of continuous output power at room temperature.

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Figure 21. 20 W Off–Line Converter

Test

Conditions

Results

Line Regulation


∆ = 1.0 mV

Load Regulation

Vin = 115 Vac, IO = 1.0 A to 4.0 A

∆ = 9.0 mV

Output Ripple

Vin = 115 Vac, IO = 4.0 A

Triangular = 10 mVpp Spike = 60 mVpp

Efficiency

Vin = 115 Vac, IO = 4.0 A

78.4%

This data was taken with the components listed below mounted on the printed circuit board shown in Figure 23. For high efficiency and small circuit board size, the Sanyo Os–Con capacitors are recommended for C8, C9, C10 and C11. C8, C9, C10 = Sanyo Os–Con #6SA330M, 330 µF 6.3 V. C11 = Sanyo Os–Con #10SA220M, 220 µF 10 V. D7 = MBR2515L mounted on Aavid #592502B03400 heatsink. L1 = Coilcraft S5088–A, 5.0 µH, 0.11 Ω. T1 = Coilcraft S5069–A Primary: 58 turns of # 26 AWG, Pin 1 = start, Pin 8 = finish. Two layers 0.002″ Mylar tape. Secondary: 4 turns of # 18 AWG, 2 strands bifiliar wound, Pin 5 = start, Pin 4 = finish. Two layers 0.002″ Mylar tape. Auxiliary: 10 turns of # 26 AWG wound in center of bobbin, Pin 2 = start, Pin 7 = finish. Two layers 0.002″ Mylar tape. Gap: 0.014″ total for a primary inductance (LP) of 330 µH. Core and Bobbin: Coilcraft PT1950, E187, 3F3 material.

Figure 22. Converter Test Data


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MC33362 Caution! High Voltages

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1###. 1##. 1## / 0779 The NCP1000 through NCP1002 series of integrated switching regulators, combine a fixed frequency PWM controller with an integrated high voltage power switch circuit. This chip allows for simple design and minimal parts count for very low cost applications which utilize an ac input. This chip is designed to power a single ended topology, typically a discontinuous mode flyback, with secondary side sensing. The internal high voltage switch circuit and start–up circuit can function in continuous operation over a wide range of inputs, from 85 Vac to 265 Vac, and thus can be used in any existing power system in the world. Though inexpensive, these devices include a number of features such as undervoltage lockout, over–temperature protection, bandgap reference and leading edge blanking that make them an excellent value.

http://onsemi.com MARKING DIAGRAMS TO–220 T SUFFIX CASE 314D

12

NCP100xT AWLYWW 34

5 Pin:

Features

• • • • • • • •

Highly Integrated Solution Operates Over Universal Input Voltage Range (85 Vac to 265 Vac) On–board 700 Volt Power Switch Circuit Minimal External Parts Required Input Undervoltage Lockout with Hysteresis Very Low Standby Current No Minimum Load Requirement Opto Fail–safe Shutdown Circuit

1. 2. 3. 4. 5.

1

1 Pin:

1. 2. 3, 6–8 4. 5.

PWM COMPARATOR

GND

x A WL YY, Y WW

START–UP

START–UP CIRCUIT

FEEDBACK INPUT PWM CONTROL & POWER SWITCH CIRCUIT

POWER SWITCH CIRCUIT

OSCILLATOR


NCP100xP AWL YYWW

DIP–8 P SUFFIX CASE 626

• Cell Phone Chargers • Wall Adapters • On–board AC–DC Converters

INTERNAL BIAS UVLO & OPTO FAIL–SAFE

5

8 8


VCC

VCC Feedback Input Ground 1 Startup Power Switch Circuit

VCC Feedback Input Ground Startup Power Switch Circuit

= Device Number 0, 1, or 2 = Assembly Location = Wafer Lot = Year = Work Week

ORDERING INFORMATION* Ipk Ron Typ Max (A) (W)

Device

Package

Shipping

NCP1000P

DIP–8

50 Units/Rail

0.5

18

NCP1001P

DIP–8

50 Units/Rail

1.0

9

NCP1002P

DIP–8

50 Units/Rail

1.5

6

NCP1000T

TO–220

50 Units/Rail

0.5

18

NCP1001T

TO–220

50 Units/Rail

1.0

9

NCP1002T

TO–220

50 Units/Rail

1.5

6

*Consult factory for additional optocoupler fail–safe latching, frequency, and current limit options.



1075


NCP1000, NCP1001, NCP1002 Functional Pin Description Pin (DIP–8)

Pin (TO–220)

Function

Description

1

1

VCC

Positive input supply voltage. This pin is connected to an external capacitor for energy storage. The start–up circuit sources current out of this pin to initially charge the capacitor. When the voltage reaches the upper threshold limit of the undervoltage lockout circuit, the start–up circuit will turn off, and the power supply will begin operation. Power is then supplied to the chip via this pin, by virtue of the auxiliary winding.

2

2

Feedback Input

The error signal from the optocoupler is fed into this input. It is loaded with a 2.7 kOhm resistor which converts the opto current into a voltage. There is a 7.0 kHz, single pole, low pass filter between this pin and the error amp input. A 10 volt clamp is also connected to this pin to protect the device from ESD damage or overvoltage conditions.

3, 6, 7, 8

3

Ground

Ground reference pin for the circuit. This pin is part of the integrated circuit leadframe and is electrically common with the tab on the TO–220, and is an integral part of the heat flow path on the DIP–8 package.

4

4

Start–up

This pin is connected to the bulk DC input voltage supply. It feeds an internal current source that initially charges up the VCC capacitor on power up.

5

5

Power Switch Circuit

The internal power switch circuit is connected between this pin and ground. This pin connects directly to one end of the transformer primary winding.

MAXIMUM RATINGS (Notes 1 and 2) Symbol

Value

Unit

VDS IDS(pk)

*0.3 to 700 2.0 Ilim Max

V A

Power Supply Voltage Range (Pin 1)

Vclp

*0.3 to 10

V

Feedback Input (Pin 2) Voltage Range Current

VI(fb) lfb

*0.3 to 10 100

V mA

Rating Power Switch Circuit (Pin 5) Drain Voltage Range Drain Current Peak During Transformer Saturation

°C/W

Thermal Resistance P Suffix, Plastic Package Case 626 Junction to Lead Junction to Air, 2.0 Oz. Printed Circuit Copper Clad 0.36 Sq. Inch 1.0 Sq. Inch T Suffix, Plastic Package Case 314D Junction to Case Junction to Air

RθJL RθJA

5.0 45 35

RθJC RθJA

2.0 65


TJ

*40 to 125

°C

Storage Temperature

Tstg

*65 to +150

°C

1. This device series contains ESD protection and exceeds the following tests: Pins 1–3: Human Body Model 4000 V per MIL–STD–883, Method 3015. Machine Model Method 400 V. Pins 4, 5: Human Body Model 1000 V per MIL–STD–883, Method 3015. Machine Model Method 400 V. Pins 4 and 5 are the HV start–up and the drain of the LDMOS device, rated only to the max rating of the part , or 700 V. 2. This device contains Latch–up protection and exceeds $200 mA per JEDEC Standard JESD78.


NCP1000, NCP1001, NCP1002 ELECTRICAL CHARACTERISTICS (VCC = 8.6 volts, pin 2 grounded, TJ = 25°C for typical values. For min/max values, TJ is the operating junction temperature that applies.) Characteristics

Symbol

Min

Typ

Max

Unit

90 85 75

100 – –

110 115 115

Av ∆Av

–110 –

*136 0.2

–170 –

%/mA (%/mA)/°C

D(max) Ifb

68 1.8

72 –

74 –

% mA

Vrpk Vrvly

– –

4.1 2.7

– –

Vclp

8.3 8.2 7.2 –

8.55 8.5 7.5 1.0

8.9 8.8 8.0 –

2.0 1.5

3.4 2.6

4.2 4.2

Drst frst

4.0 –

5.0 1.2

6.0 –

% Hz

VBR(st)

700

–

–

V

– –

20 30

40 75

OSCILLATOR Frequency (lfb = 1.5 mA) (Note 4) (Figure 7) TJ = 25°C TJ = 0°C to 125°C TJ = –40°C to 125°C

fOSC

kHz

PWM COMPARATOR Feedback Input PWM Gain (TJ = 25°C) (lfb = 1.10 mA to 1.20 mA) (Figure 2) Gain Temperature Coefficient (TJ = –40°C to TJ = 125°C) (Note 4) PWM Duty Cycle (Pin 2) Maximum (lfb = 0 mA) Zero Duty Cycle Current PWM Ramp Peak Valley

V

START–UP CONTROL AND VCC LIMITER Undervoltage Lockout (Figure 8) VCC Clamp Voltage (ICC = 4.0 mA) Start–Up Threshold (Vclp Increasing) Minimum Operating Voltage After Turn–On Hysteresis

V Vclp(on) Vclp(min) VH

Start–Up Circuit, Pin 1 Output Current (Pin 4 = 50 V) VCC = 0 V VCC = 8.0 V

Istart

Auto Restart (CPin 1 = 47 µF, Pin 4 = 50 V) (Note 5) Duty Cycle Frequency Start–Up Circuit Breakdown Voltage (I = 2 µA) (Note 5) Start–Up Circuit Leakage Current (Pin 4 = 700 VDC) TJ = 25°C TJ = –40°C to 125°C

mA

µA

Ileak

3. Maximum package power dissipation limits must be observed. 4. Tested junction temperature range for this device series: Tlow = –40°C, Thigh = +125°C 5. Guaranteed by design only.


NCP1000, NCP1001, NCP1002 ELECTRICAL CHARACTERISTICS Characteristics

Symbol

Min

Typ

Max

Unit

POWER SWITCH CIRCUIT Power Switch Circuit On–State Resistance NCP1000 (ID = 50 mA) TJ = 25°C TJ = 125°C (Note 8) NCP1001 (ID = 100 mA) TJ = 25°C TJ = 125°C (Note 8) NCP1002 (ID = 150 mA) TJ = 25°C TJ = 125°C (Note 8)

R(on)

Power Switch Circuit Breakdown Voltage (ID(off) = 100 µA, TJ = 25°C)

V(BR)

Power Switch Circuit Off–State Leakage Current (VDS = 700 V) TJ = 25°C TJ = –40°C to 125°C

Ω – –

13 24

18 36

– –

7.0 14

9.0 18

– –

4.0 8.0

6.0 12

700

–

–

– –

0.25 –

1.0 100

– –

50 50

– –

0.42 0.84 1.26

0.48 0.96 1.43

0.54 1.08 1.6

– – –

0.500 1.000 1.500

– – –

– 10

18 –

25 35

µA

I(off)

Switching Characteristics (VDS = 50 V, RL set for ID = 0.7 IIim) Turn–on Time (90% to 10%) Turn–off Time (10% to 90%)

V

ns ton toff

CURRENT LIMIT AND THERMAL PROTECTION Current Limit Threshold (TJ = 25°C) (Note 9) NCP1000 NCP1001 NCP1002

Ilim

Current Limit, Peak Switch Current NCP1000 (di/dt = 100 mA/µs) NCP1001 (di/dt = 200 mA/µs) NCP1002 (di/dt = 300 mA/µs)

Ipk

A

A

Opto Fail–safe Protection (Figure 12) TJ = 25°C TJ = 0°C to 125°C

IOfail

mA

Propagation Delay, Current Limit Threshold to Power Switch Circuit Output (Leading Edge Blanking plus Current Limit Delay)

tPLH

–

220

–

tsd tH

125 –

140 30

– –

ns °C

Thermal Protection (Note 6, 8) Shutdown (Junction Temperature Increasing) Hysteresis (Junction Temperature Decreasing) TOTAL DEVICE (Pin 1)

mA

Power Supply Current After UVLO Turn–On Power Switch Circuit Enabled NCP1000 NCP1001 NCP1002 Power Switch Circuit Disabled

ICC1

ICC2

– – – 0.6

6. Maximum package power dissipation limits must be observed. 7. Tested junction temperature range for this device series: Thigh = +125°C Tlow = –40°C 8. Guaranteed by design only. 9. Actual peak switch current is increased due to the propagation delay time and the di/dt (see Figure 16).


1.2 1.4 1.6 1.0

1.6 1.8 2.0 1.25

NCP1000, NCP1001, NCP1002 2

0.800 0.700

1.5

0.600 ICC (mA)

DC (%)

0.500 0.400 0.300

1

0.5

0.200 0.100 0.000 0.8

1

1.2

1.4

1.6

0

1.8

0

1

2

3

4

5

7

6

lfb (mA)

VCC (V)

Figure 2. Duty Cycle vs. FB Input Current

Figure 3. ICC vs. VCC

1000

8

9

4.00

Start–up Current (mA)

VCC Charge Time (ms)

3.50

100

10

3.00 2.50 2.00 1.50 1.00

VCC = 4.0 V

0.50 1

0.00 1

10

100

1

10

100

1000

Capacitance (µF)

Start–up Voltage (V) (Pin 4)

Figure 4. Charge Time vs. VCC Capacitance

Figure 5. Startup Current vs. Startup Voltage

1000

104.0 102.0

98.0

NCP1001

fOSC, (kHz)

Capacitance (pF)

100.0 NCP1002

100 NCP1000

96.0 94.0 92.0 90.0 88.0

10

1

10

100

1000

86.0 –40

–25

0

25

50

75

Switch Voltage (V)

Temperature (°C)

Figure 6. Power Switch Circuit Capacitance vs. Voltage

Figure 7. Oscillator Frequency vs. Temperature


100

125

NCP1000, NCP1001, NCP1002 8.60

VCC/UVLO Threshold (V)

8.40

Peak Current Limit Threshold (A)

1.80 VCC Turn On

8.20 8.00 7.80 7.60

VCC Turn Off

7.40 7.20 –40 –25

0

25

50

75

100

1.40 1.20

NCP1001

1.00 0.80 NCP1000

0.60 0.40 0.20 0.00 –40

125

–25

0

25

50

75

100

Temperature (°C)

Temperature (°C)

Figure 8. VCC/UVLO Threshold vs. Temperature

Figure 9. Peak Current Limit Threshold vs. Temperature

25.0

125

250

200 Leakage Current (µA)

20.0 On Resistance (Ω)

NCP1002

1.60

NCP1000 15.0 NCP1001 10.0

125°C

150

100 25°C

–40°C 50

5.0 NCP1002 0.0 –40

–25

0

25

50

75

100

0

125

0

400

600

800

1000

Voltage (V)

Figure 10. Power Switch Circuit On Resistance vs. Temperature

Figure 11. Power Switch Circuit Leakage Current vs. Pin 5 Voltage

24.0

1.75

22.0

ZDC Feedback Current (mA)

Fail–safe Trigger Current (mA)

200

Temperature (°C)

20.0 18.0 16.0 14.0 12.0 10.0 8.0 –40

–25

0

25

50

75

100

125

1.70 1.65 1.60 1.55 1.50 1.45 –40

–25

0

25

50

75

100

Temperature (°C)

Temperature (°C)

Figure 12. Opto Fail–safe Trigger Current vs. Temperature

Figure 13. Zero Duty Cycle Feedback Current vs. Temperature


125

NCP1000, NCP1001, NCP1002 1.100

14.0 12.0 On Resistance (Ω)

1.060 1.040 1.020 1.000

0.960 –40

10.0 NCP1001 8.0 6.0 NCP1002 4.0

0.980

–25

0

25

50

75

100

125

2.0

0

0.5

1

Temperature (°C)

Power Switch Circuit Current (A)

Figure 14. Maximum Duty Cycle Feedback Current vs. Temperature

Figure 15. On Resistance vs. Current

1600 1400 1200 di/dt (mA/µs)

MDC Feedback Current (mA)

NCP1000 1.080

1000 800 600 400 200 0 0

50

100

150

200

250

300

∆Ipk (mA)

Figure 16. Power Switch Circuit di/dt vs. DIpk


350

1.5

NCP1000, NCP1001, NCP1002 OPERATING DESCRIPTION Introduction

consumption while in the stand–by operation mode. For operation at no load, the output may skip cycles. This is a common occurrence for this type of control circuit. The converter will switch for several cycles, and due to delays in the output filter and feedback loop, the duty cycle will not be reduced until the output has exceeded it’s regulation limit. The unit will then shut down for several cycles until the voltage is below the regulation limit, and then it will switch again. During the time that switching cycles are not present the output voltage will decay according to it’s RC time constant, which is based on the output capacitance and internal loading from the regulation circuitry. During this interval, the voltage on the VCC supply will also decay. If it decays below the lower hysteretic turn off threshold, the unit will shut down and recycle. This mode of operation is not normally desirable. In order to avoid it, the time constant for the VCC cap and load should be equal to, or greater than the time constant of the output. If no load operation is not required, a relatively small value (t10 µF) for the VCC capacitor is acceptable.

The NCP1000 thru NCP1002 represent a new higher level of integration by providing on a single monolithic chip all of the active power, control, logic, and protection circuitry required to implement a high voltage flyback or forward converter. This device series is designed for direct operation from a rectified 240 VAC line source and requires minimal external components for a complete cost sensitive converter solution. Potential markets include office automation, industrial, residential, personal computer, and consumer. A description of each of the functional blocks is given below, and the representative block diagram is shown in Figure 17. Oscillator

The Oscillator block consists of two comparators that alternately gate on and off a trimmed current source and current sink which are used to respectively charge and discharge an on–chip timing capacitor between two voltage levels. This configuration generates a precise linear sawtooth ramp signal that is used to pulse width modulate the MOSFET of the Power Switch circuit. During the charge of the timing capacitor, the Oscillator duty cycle output holds one input of the Driver low. This action keeps the MOSFET of the Power Switch Circuit off, thus limiting the maximum duty cycle. The Oscillator frequency is internally programmed for 100 kHz operation with a controlled charge to discharge current ratio that yields a maximum Power Switch Circuit duty cycle of 72%. The Oscillator temperature characteristics are shown in Figure 7.

Feedback Input

The feedback input, pin 2, accepts the DC error signal that feeds the non–inverting input to the PWM. Pin 2 has a nominal 2.7 kOhm internal resistor to ground, which converts the optocoupler current into a voltage. Its’ signal is filtered by a 7.0 kHz low pass filter which reduces high frequency noise to the input of the PWM comparator. Typically, the photo transistor of the optocoupler is connected between VCC (pin 1) and the Feedback input (pin 2). The photo transistor is effectively a current source which is driven by the LED, which is connected to the output regulation circuit of the power supply. An external capacitor may be connected from pin 2 to ground for additional noise filtering if necessary. When the feedback input is below the lower threshold of the ramp signal, the output of the power converter will be operating at full duty cycle. The input current vs. duty cycle transfer function is shown in Figure 2. As the voltage increases, the duty cycle will vary linearly with the change in voltage at the feedback input, between the upper and lower extremes of the ramp waveform 2.7 V to 4.1 volts. Above the upper extreme point of the ramp, the duty cycle will be zero and no power will be transmitted to the output. The circuit should be designed such that when the output is low, the optocoupler will be off, leaving the voltage at pin 2 at ground (full duty cycle). As the output voltage increases, the optocoupler will begin to conduct, such that the voltage at pin 2 increases until the proper duty cycle is reached to maintain regulation. Pin 2 is protected from ESD transients by a 10 volt zener diode to ground.


The pulse width modulator (PWM) consists of a comparator with the Oscillator ramp output applied to the inverting input. The Oscillator clock output applies a set pulse to the PWM Latch when the timing capacitor reaches its peak voltage, initiating Power Switch Circuit conduction. As the timing capacitor discharges, the ramp voltage decreases to a level that is less than the Error Amplifier output, causing the PWM Comparator to reset the latch and terminate Power Switch Circuit conduction for the duration of the ramp–down period. This method of having the Oscillator set and the PWM Comparator reset the Latch prevents the possibility of multiple output pulses during a given Oscillator clock cycle. This circuit configuration is commonly referred to as double pulse suppression logic. A timing diagram is shown in Figure 18 that illustrates the behavior of the pulse width modulator. No load operation. The pulse width modulator is designed to operate between 73% and 0% duty cycle. The ability to operate down to zero duty cycle allows for no load operation without the burden of preloads. This feature is consistent with the Blue Angle requirements, as it minimizes power


NCP1000, NCP1001, NCP1002 Current Limit Comparator and Power Switch Circuit

High Voltage Start–Up

The NCP1000 series uses cycle–by–cycle current limiting as a means of protecting the output switch transistor from overstress. Current limiting is implemented by monitoring the instantaneous output switch current during conduction, and upon sensing an overcurrent condition, immediately turning off the switch for the duration of the Oscillator ramp–down period. The Power Switch Circuit is constructed using a SenseFET allowing a virtually lossless method of monitoring the drain current. A small number of the power MOSFET cells are used for current sensing by connecting their individual sources to a single ground referenced sense resistor, Rpk. The current limit comparator detects if the voltage across Rpk exceeds the reference level that is present at the noninverting input. If exceeded, the comparator quickly resets the PWM Latch, thus protecting the Power Switch Circuit. Figure 9 shows that this detection method yields a relatively constant current limit threshold over temperature. The high voltage Power Switch Circuit is integrated with the control logic circuitry and is designed to directly drive the converter transformer. The Power Switch Circuit is capable of switching 700 V with an associated drain current that ranges from 0.5 A to 1.5 A. Proper drain voltage snubbing during converter start–up and overload is mandatory for reliable device operation. A Leading Edge Blanking circuit was placed in the current sensing signal path to prevent a premature reset of the PWM Latch. A potential premature reset signal is generated each time the Power Switch Circuit is driven into conduction and appears as a narrow voltage spike across current sense resistor Rpk. The spike is due to the MOSFET gate to source capacitance, transformer interwinding capacitance, and output rectifier recovery time. The Leading Edge Blanking circuit has a dynamic behavior that masks the current signal until the Power Switch Circuit turn–on transition is completed. The current limit propagation delay time is typically 220 ns. This time is measured from when an overcurrent appears at the Power Switch Circuit drain, to the beginning of turn–off. Care must be taken during transformer saturation so that the maximum device current limit rating is not exceeded. To determine the peak Power Switch Circuit current at turn off, the effect of the propagation delay must be taken into account. To do this, use the appropriate Current Limit Threshold value from the electrical tables, and then add the Ipk based on the di/dt from Figure 16. The di/dt of the circuit can be calculated by the following formula:

The NCP1000–1002 contain an internal start–up circuit that eliminates the need for external start–up components. In addition, this circuit increases the efficiency of the supply as it uses no power when in the normal mode of operation, but instead uses the power supplied by the auxiliary winding. Rectified, filtered ac line voltage is connected to pin 4. An internal JFET allows current to flow from the start–up pin, to the VCC pin at a current of approximately 3.0 mA. Figure 5 shows the startup current out of pin 1 which charges the capacitor(s) connected to this pin. The start circuit will be enhanced (conducting) when the voltage at Pin 1 (VCC) is less than 7.5 volts. It will remain enhanced until the VCC voltage reaches 8.5 volts. At this point the Power Switch Circuit will be disabled, and the unit will generate voltage via the auxiliary winding to maintain proper operation of the device. Figure 4 shows the charge time for turn–on vs. VCC capacitance when the unit is initially energized. If the VCC voltage drops below 7.5 volts (e.g. current limit mode), the start circuit will again begin conducting, and will charge up the VCC cap until the 8.5 volt limit is reached. VCC Limiter and Undervoltage Lockout

The undervoltage lockout (UVLO) is designed to guarantee that the integrated circuit has sufficient voltage to be fully functional before the output stage is enabled. It inhibits operation of the major functions of the device by disabling the Internal Bias circuitry, and assures that the Power Switch Circuit remains in its “off’’ state as the bias voltage is initially brought up from zero volts. When the NCP100x is in the “off’’ state, the High Voltage Start–up circuit is operational. The UVLO is a hysteretic switch and will hold the device in its “off’’ state any time that the VCC voltage is less than 7.5 volts. As the VCC increases past 7.5 volts, the NCP100x will remain off until the upper threshold of 8.6 volts is reached. At this time the power converter is enabled and will commence operation. The UVLO will allow the unit to continue to operate as long as the VCC voltage exceeds 7.5 volts. The temperature characteristics of the UVLO circuit are shown in Figure 8. If the converter output is overloaded or shorted, the device will enter the auto restart mode. This happens when the auxiliary winding of the power transformer does not have sufficient voltage to support the VCC requirements of the chip. Once the chip is operational, if the VCC voltage falls below 7.5 volts the unit will shut down, and the High Voltage Start–up circuit will be enabled. This will charge the VCC cap up to 8.5 volts, which will clock the divide by eight counter. The divide by eight counter holds the Power Switch Circuit off. This causes the VCC cap to discharge. It will continue to discharge and recharge for eight consecutive cycles. After the eighth cycle, the unit will turn on again. If the fault remains, the unit will again cycle through the auto restart mode; if the fault has cleared the unit will begin normal operation. The auto restart mode greatly reduces the power dissipation of the power devices in the circuit and

dińdt (Ańs) + VńL

where: V is the rectified, filtered input voltage (volts) L is the primary inductance of the flyback transformer (Henries)


NCP1000, NCP1001, NCP1002 improves reliability in overload conditions. Figure 20 shows the timing waveforms in auto restart mode. The VCC pin receives its start–up power from the high voltage start–up circuit. Once the undervoltage lockout trip point is exceeded, the high voltage start–up circuit turns off, and the VCC pin receives its power from the auxiliary winding of the power transformer. Once the converter is enabled, the VCC voltage will be clamped by the 8.6 volt limiter. Since the voltage limiter will regulate the VCC voltage at 8.6 volts, it must shunt all excess current based on the input impedance to this pin. A resistor is required between the auxiliary winding filter capacitor and the VCC pin to limit the current.

where: VAUXmin is the minimum expected DC voltage from the auxiliary winding. Typically, this voltage will vary between "5% to "10% from it’s nominal value. ICC1max is the maximum rated bias current for the device used. This value can found in the tables on the data sheet. For the best optocoupler fail–safe response: Rs

(V * 7.2 volts) AUX max 1.0mA ) I trip

where: VAUXmax is the maximum expected DC voltage from the auxiliary winding. Itrip is the minimum trip current for the optocoupler fail–safe. This information can be found in the tables under Current Limit and Thermal Protection, as well as in Figure 12. The value of RS that is used in the circuit must be between the two extreme values calculated. Setting it closer to RSmin will optimize the optocoupler fail–safe feature, while setting it closer to the RSmax value will minimize the bias current

Optocoupler Fail–safe Circuit

The NCP100x has the ability to sense an open optocoupler and protect the load in the event of a failure. This circuit operates by sensing the current in the VCC limiter, and detecting a high current which is an indication of an open optocoupler. The VCC pin receives the output of a current source which is created by the voltage drop between the auxiliary winding and the VCC limiter across the shunt resistor. The Vcc limiter will clamp the VCC voltage to approximately 8.6 volts. Any current that is available at this pin, that is not needed for either the chip bias current, or the opto current is shunted through this limiter. The opto fail–safe circuit operates on the premise that under an open opto condition, the opto current will all be shunted through the VCC limiter, and the output voltage (and therefore the auxiliary winding voltage) will increase. The increase in auxiliary winding voltage will cause an amplified increase in the current into the VCC pin. To detect an open opto condition, the current in the limiter is measured and if it exceeds 10 milliamps, the chip will shut down and go into burst mode operation. After a shutdown signal, the optocoupler fail–safe circuit will enable the divide–by–eight counter and attempt to restart the unit after every eight VCC cycles. For this circuit to operate properly, the shunt resistor must be chosen prudently. There is a range of values for RS that will determine the operation of this circuit. On one extreme, a large value of RS will minimize the bias current, which will have the effect of maximizing efficiency, while reducing the response to an open optocoupler. The other extreme is the minimum value of RS, which will maximize the bias current into the chip and minimize the voltage overshoot in the event of an open optocoupler. For minimum bias current: Rs max +

min

+

Thermal Shutdown and Package

The internal Thermal Shutdown block protects the device in the event that the maximum junction temperature is exceeded. When activated, typically at 140°C, one input of the Driver is held low to disable the Power Switch Circuit. Thermal shutdown activation is non–latching and the Power Switch Circuit is allowed resume operation when the junction temperature falls below 110°C. The thermal shutdown feature is provided to prevent catastrophic device failures from accidental overheating. It is not intended to be used as a substitute for proper heatsinking. The die in the 8–pin dual–in–line package is mounted on a special heat tab copper alloy lead frame. The tab consists of pins 3, 6, 7, 8 is specifically designed to improve the thermal conduction from the die to the printed circuit board. This permits the use of standard layout and mounting practices while having the ability to halve the junction to air thermal resistance. The die in the 5–pin TO–220 style package is mounted directly on a copper alloy heat tab. This metal tab is exposed on the backside of the package for heatsink attachment and is electrically common to the device ground, Pin 3. A wide variety of TO–220 style heatsinks are commercially available for enhancing the thermal performance and converter output power capability.

(V * 8.8 volts) AUX min I CC1max


NCP1000, NCP1001, NCP1002 Applications

to the printed circuit ground plane and should not be bent or offset by the board layout. The Power Switch Circuit pin can be offset if additional layout creepage distance is required. Due to the potentially high rate of change in switch current, a capacitor (if used), at pin 2, should have traces as short as possible, from pin 2 and ground. This will significantly reduce the level of switching noise that can be imposed upon the feedback control signal.

The TO–220 devices have a single Ground, pin 3, that serves the high current return path for the Power Switch Circuit. Do not attempt to construct a converter circuit on a wire–wrap or plug–in prototype board. In order to ensure proper device operation and stability, it is important to minimize the lead length and the associated inductance of the ground pin. This pin must connect as directly as possible

45 " ="

"//

-0

4L+0

2

4 , 1"

! ! 5

&55

2

9 & &55 > &

*#/' ="

*+ %

9 &

9 4

=""+ -

5"+ !

2"#@+

> &; ' > &

5' ,

@# /0

7

1+ #!"

5" " ++

0 50+

6 7 ,

5+' ,

> '

>9 '() *+

@

6 5

#" 8# -+"'"

5" 5 "#

,'



5"@

5

NCP1000, NCP1001, NCP1002 *#/' =" ,%/ &+ ++ , ++

0 50+

++ 5+' 6 5 6 7

5" "

+0

! ! 5 @

5" 1 +#

#" 8# -+"'" =" ! ! 5 5" I 0 50+

& > &

,+" 1 +#

&55 " 9& *+0/' &+

! ! 5 &+ "

,%# " &+ !" /+#

!"

& > &

9& *+0/' &+ ,%# " &+ 9&

!" /+#

!"

!" /+#

!"

!" /+#

4 , " ! @+## #

Figure 20. Auto Restart Operation Timing Diagram


!"

NCP1000, NCP1001, NCP1002 APPLICATIONS INFORMATION Converter Test Data

APPLICATION #1: Offline Converter Provides 5.0 Volt, 1.0 Amp Output for Small Electronic Equipment

Parameter

ON Semiconductor’s NCP1000 series of offline converters offers a low cost, high efficiency power source for low power, electronic equipment. It serves the same function as small, line frequency transformers, but with the added benefits of line and load regulation, transient suppression, reduction in weight, and operation across the universal input voltage range. This kit provides a 5.0 volt, 1.0 amp output, which is derived from an input source of 85 to 265 vac, and 50 Hz to 60 Hz. This range of input voltages will allow this circuit to function virtually anywhere in the world without modification. The output is regulated and current limited, and EMI filters are included on both the input and output.

RS

F1

85 v v Vin v 265 v

Vo = 6.0 mV

Load Regulation

0 A v lo v 1.0 A

Vo = 8.0 mV

Combined Line/ Load Regulation

85 v v Vin v 265 v .09 A v lo v 1.0 A

Vo = 10 mV

Output Ripple

lo = 1.0 A

100 mVpp

Input Power

Vin = 115 v, lo = 1.0 A Vin = 220 v, lo = 1.0 A

7.75 watts 7.88 watts

Power Factor

Vin = 115 v, lo = 1.0 A Vin = 220 v, lo = 1.0 A

–.57 –.49

Efficiency

Vin = 115 v, lo = 1.0 A Vin = 220 v, lo = 1.0 A

= 66% = 64%

L2

C1

D5

5 V, 1 A

C6

R2 +

V in

Data

Line Regulation

D1 – D4

6.8

Conditions

C7

+

R3

C3

R4

p/o U2

C2a C2b R7 6.8

p/o U2

C10

D6

R1

U3

C8

1

R5 NCP 1000

C5

RETURN C9

C4

Figure 21. Wall Adapter Schematic

For additional information on this application, please order application note AND8019/D from the Literature Distribution Center or download from our website at http://onsemi.com.


1#,#. 1#,. 1#,-.

1#,. 1#,". 1#,,

; + : 0 1

http://onsemi.com

The NCP1050 through NCP1055 are monolithic high voltage regulators that enable end product equipment to be compliant with low standby power requirements. This device series combines the required converter functions allowing a simple and economical power system solution for office automation, consumer, and industrial products. These devices are designed to operate directly from a rectified AC line source. In flyback converter applications they are capable of providing an output power that ranges from 6.0 W to 40 W with a fixed AC input of 100 V, 115 V, or 230 V, and 3.0 W to 20 W with a variable AC input that ranges from 85 V to 265 V. This device series features an active startup regulator circuit that eliminates the need for an auxiliary bias winding on the converter transformer, fault logic with a programmable timer for converter overload protection, unique gated oscillator configuration for extremely fast loop response with double pulse suppression, power switch current limiting, input undervoltage lockout with hysteresis, thermal shutdown, and auto restart fault detection. These devices are available in an economical 8–pin dual–in–line package.

8 1 DIP–8 CASE 626 P SUFFIX Pin: 1. 2. 3, 6–8. 4. 5.

MARKING DIAGRAM 8

Features

NCP105XZ AWL YYWW

• Startup Circuit Eliminates the Need for Transformer Auxiliary Bias Winding

• Optional Auxiliary Bias Winding Override for Lowest Standby • • • • • • • • • •

Power Applications Converter Output Overload and Open Loop Protection Auto Restart Fault Protection IC Thermal Fault Protection Unique, Dual Edge, Gated Oscillator Configuration for Extremely Fast Loop Response Oscillator Frequency Dithering with Controlled Slew Rate Driver for Reduced EMI Low Power Consumption Allowing European Blue Angel Compliance On–Chip 700 V Power Switch Circuit and Active Startup Circuit Rectified AC Line Source Operation from 85 V to 265 V Input Undervoltage Lockout with Hysteresis Oscillator Frequency Options of 44 kHz, 100 kHz, 136 kHz

VCC Control Input Ground No Connection Power Switch Circuit Drain

1 X Z A WL YY WW

= Current Limit (0, 1, 2, 3, 4, 5) = Oscillator Frequency (A, B, C) = Assembly Location = Wafer Lot = Year = Work Week

ORDERING INFORMATION See detailed ordering and shipping information on page 1110 of this data sheet.


• • • •

AC–DC Converters Wall Adapters Portable Electronic Chargers Low Power Standby and Keep–Alive Supplies



1089


NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055 + AC Line Input

+

Snubber

+

Converter DC Output –

Power Switch Circuit Output VCC +

1

Startup & VCC Regulator Circuit Power Switch Circuit

Fault Logic Control Input 2

5

Oscillator & Gating Logic

Ground

3, 6–8

Figure 1. Typical Application Pin Function Description Pin #

Function

Description

1

VCC

This is the positive supply voltage input. During startup, power is supplied to this input from Pin 5. When VCC reaches VCC(on), the Startup Circuit turns off and the output is allowed to begin switching with 1.0 V hysteresis on the VCC pin. The capacitance connected to this pin programs fault timing and frequency modulation rate.

2

Control Input

3, 6, 7, 8

Ground

4

No Connection

5


The Power Switch Circuit is turned off when a current greater than approximately 50 µA is drawn out of or applied to this pin. A 10 V clamp is built onto the chip to protect the device from ESD damage or overvoltage conditions. This pin is the control circuit and Power Switch Circuit ground. It is part of the integrated circuit lead frame.

This pin is designed to directly drive the converter transformer primary, and internally connects to Power Switch Circuit and Startup Circuit.


NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055

+ AC Line Input

Snubber

+

+

Converter DC Output –

Power Switch Circuit Output VCC +

Startup/VCC Reg

10 V

+ –

+ VCC Bypass/ Fault Timing/ VCO Sweep Control

Startup Circuit

7.6/8.6 V

Fault Logic & Timer

Internal Bias Fault Latch

S Undervoltage Lockout

Thermal Shutdown

– +

+


Q R

Driver

4.6 V

VCC

Oscillator IH = 9.0 µA

47 µA

Turn On Latch Turn Off Latch

R Q

+ 2.6 V

Ck

S

Control Input

Q R

10 V

+ – Current Limit Comparator

+ 3.3 V

47 µA

Leading Edge Blanking +

RSENSE

IH = 10 µA

Ground



NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055 fOSC (high) 8.6 V fOSC (low)

VCC 7.6 V

Oscillator Duty Cycle

Oscillator Clock 47 µA 38 µA ICONTROL, SINK

0 µA

Leading Edge On Duty Cycle Off

Leading Edge On Feedback Off Delay On Duty Cycle Off

Leading Edge On Duty Cycle Off No Second Pulse

Leading Edge On Current Limit Off

Power Switch Circuit Gate Drive

Current Limit Threshold

Primary Current

Current Limit Propagation Delay

Figure 3. Timing Diagram for Gated Oscillator with Dual Edge PWM


NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055 ICC1, Current Measurement ICC2, Current Measurement VCC(on) Hysteretic Regulation VCC(off) VCC VCC(reset) ICC3, Current Measurement 0V 6.2 mA I(start) 0 mA ICC1 ICC

ICC2 ICC3

0 mA

I(start) 47 µA 38 µA ICONTROL, SINK 0 µA

V(pin 5)

Fault Removed

Fault Applied

Figure 4. Non–Latching Fault Condition Timing Diagram


NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055 MAXIMUM RATINGS (Note 1) Rating Power Switch and Startup Circuit Drain Voltage Range Drain Current Peak During Transformer Saturation Power Supply/VCC Bypass and Control Input Voltage Range Current

Symbol

Value

Unit

VDS IDS(pk)

*0.3 to 700 2.0 Ilim Max

V A

VIR Imax

*0.3 to 10 100

V mA °C/W

Thermal Characteristics P Suffix, Plastic Package Case 626 Junction to Lead Junction to Air, 2.0 Oz. Printed Circuit Copper Clad 0.36 Sq. Inch 1.0 Sq. Inch

RθJC RθJA

2.0 45 35


TJ

*40 to +150

°C

Storage Temperature

Tstg

*65 to +150

°C

1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. A. This device series contains ESD protection and exceeds the following tests: Pins 1–3: Human Body Model 2000 V per MIL–STD–883, Method 3015. Machine Model Method 400 V. Pin 5: Human Body Model 1000 V per MIL–STD–883, Method 3015. Machine Model Method 400 V. Pin 5 is connected to the power switch and start–up circuits, and is rated only to the max voltage of the part, or 700 V. B. This device contains Latch–up protection and exceeds $100 mA per JEDEC Standard JESD78.


NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055 ELECTRICAL CHARACTERISTICS (VCC = 8.0 V, for typical values TJ = 25°C, for min/max values, TJ is the operating junction temperature range that applies (Note 2), unless otherwise noted.) Characteristics

Symbol

Min

Typ

Max

Unit

OSCILLATOR Frequency (VCC = 7.6 V) TJ = 25°C: A Suffix Device B Suffix Device C Suffix Device TJ = Tlow to Thigh A Suffix Device B Suffix Device C Suffix Device

fOSC(low)

Frequency (VCC = 8.6 V) TJ = 25°C: A Suffix Device B Suffix Device C Suffix Device TJ = Tlow to Thigh A Suffix Device B Suffix Device C Suffix Device

fOSC(high)

kHz 38 87 119

43 97 132

47 107 145

37 84 113

– – –

47 107 145 kHz

41 93 126

46 103 140

50 113 154

39 90 120

– – –

50 113 154

Frequency Sweep (VCC = 7.6 V to 8.6 V, TJ = 25°C)

%fOSC

–

6.0

–

%

Maximum Duty Cycle

D(max)

74

77

80

%

Ioff(low) Ion(low)

–58 –50

–47 –38

–37 –25

Ioff(high) Ion(high)

37 25

47 37

58 50

Vlow Vhigh

1.15 4.2

1.3 4.6

1.45 5.0

CONTROL INPUT µA

Lower Window Input Current Threshold Switching Enabled, Sink Current Increasing Switching Disabled, Sink Current Decreasing Upper Window Input Current Threshold Switching Enabled, Source Current Increasing Switching Disabled, Source Current Decreasing Control Window Input Voltage Lower (Isink = 25 µA) Upper (Isource = 25 µA)

V

2. Tested junction temperature range for the NCP105X series: Thigh = +125°C Tlow = –40°C



Symbol

Power Switch Circuit On–State Resistance NCP1050, NCP1051, NCP1052 (ID = 50 mA) TJ = 25°C TJ = 125°C NCP1053, NCP1054, NCP1055 (ID = 100 mA) TJ = 25°C TJ = 125°C

RDS(on)

Power Switch Circuit & Startup Breakdown Voltage (ID(off) = 100 µA, TA = 25°C)

V(BR)DS

Min

Typ

Max

Unit

POWER SWITCH CIRCUIT

Power Switch Circuit & Startup Circuit Off–State Leakage Current (VDS = 700 V) TJ = 25°C TJ = 125°C

Ω – –

26 48

30 55

– –

13 24

15 28

700

–

–

µA

IDS(off) – –

25 15

40 80

– –

45 25

– –

93 186 279 372 493 632

100 200 300 400 530 680

107 214 321 428 567 728

–

0

10

– –

125 250

– –

Tsd TH

140 –

160 75

– –

Startup/VCC Regulation Startup Threshold/VCC Regulation Peak (VCC Increasing) Minimum Operating/VCC Valley Voltage After Turn–On Hysteresis

VCC(on) VCC(off) VH

8.2 7.2 –

8.6 7.6 1.0

9.0 8.0 –

Undervoltage Lockout Threshold Voltage, VCC Decreasing

VCC(reset)

4.2

4.6

5.0

Switching Characteristics (RL = 50 Ω, VDS set for ID = 0.7 IIim) Turn–on Time (90% to 10%) Turn–off Time (10% to 90%)

V

ns ton toff

CURRENT LIMIT AND THERMAL PROTECTION Current Limit Threshold (TJ = 25°C) (Note 6) NCP1050 NCP1051 NCP1052 NCP1053 NCP1054 NCP1055

Ilim

I2fOSC

Conversion Power Deviation (TJ = 25°C) (Note 7) Propagation Delay, Current Limit Threshold to Power Switch Circuit Output NCP1050, NCP1051, NCP1052 NCP1053, NCP1054, NCP1055

mA

tPLH

%A2Hz ns

°C

Thermal Protection (VCC = 8.6 V) (Note 3, 4, 5) Shutdown (Junction Temperature Increasing) Hysteresis (Junction Temperature Decreasing) STARTUP CONTROL

V

Startup Circuit Output Current (Power Switch Circuit Output = 40 V) VCC = 0 V TJ = 25°C TJ = –40 to 125°C VCC = VCC(on) – 0.2 V TJ = 25°C TJ = –40 to 125°C Output Fault Condition Auto Restart (VCC Capacitor = 10 µF, Power Switch Circuit Output = 40 V) Average Switching Duty Cycle Frequency

Istart

Drst frst

3. Tested junction temperature range for the NCP105X series: Thigh = +125°C Tlow = –40°C 4. Maximum package power dissipation limits must be observed. 5. Guaranteed by design only. 6. Adjust di/dt to reach Ilim in 4.0 sec. 7. Consult factory for additional options including trim for output power accuracy.


V mA

5.4 4.5

6.2 –

7.0 8.0

4.6 3.5

5.4 –

6.2 7.0

– –

8.0 5.0

– –

% Hz


Symbol

Min

Typ

Max

Unit

TOTAL DEVICE Power Supply Current After UVLO Turn–On (Note 9) Power Switch Circuit Enabled NCP1050, NCP1051, NCP1052 A Suffix Device B Suffix Device C Suffix Device NCP1053, NCP1054, NCP1055 A Suffix Device B Suffix Device C Suffix Device Power Switch Circuit Disabled Non–Fault Condition Fault Condition

mA ICC1

ICC2 ICC3

8. Tested junction temperature range for the NCP105X series: Thigh = +125°C Tlow = –40°C 9. See Non–Latching Fault Condition Timing Diagram in Figure 4.


0.35 0.40 0.45

0.47 0.52 0.56

0.55 0.60 0.65

0.40 0.45 0.50

0.53 0.61 0.67

0.60 0.70 0.80

0.35 0.10

0.45 0.16

0.55 0.25

NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055 105 OSCILLATOR FREQUENCY (kHz)

OSCILLATOR FREQUENCY (kHz)

48 47 VCC = 8.6 V 46 45 VCC = 7.6 V

44 43 42 41 40 –50

–25

0

25

50

75

100

125

103 VCC = 8.6 V

101 99 97

93 91 89 87 –50

150

VCC = 7.6 V

95

–25

0

TEMPERATURE (°C)

Figure 5. Oscillator Frequency (A Suffix) versus Temperature

FREQUENCY SWEEP (kHz)

OSCILLATOR FREQUENCY (kHz)

VCC = 8.6 V

140

100

125

150

138 136 134

VCC = 7.6 V

132 130 128

–25

0

25

50

75

100

125

8 7 C SUFFIX 6 5 B SUFFIX 4 3 2 –50

150

A SUFFIX –25

0

TEMPERATURE (°C)

77.1 77.0 76.9 76.8 76.7 76.6 25

50

75

100

125

150

SINK CONTROL CURRENT THRESHOLD (A)

77.2

0

50

75

100

125

150

125

150

Figure 8. Frequency Sweep versus Temperature

77.3

–25

25

TEMPERATURE (°C)

Figure 7. Oscillator Frequency (C Suffix) versus Temperature

MAXIMUM DUTY CYCLE (%)

75

9

142

76.5 –50

50

Figure 6. Oscillator Frequency (B Suffix) versus Temperature

144

126 124 –50

25

TEMPERATURE (°C)

52 50 CURRENT RISING

48 46 44 42 40

CURRENT FALLING

38 36 34 32 –50

–25

0

25

50

75

100

TEMPERATURE (°C)

TEMPERATURE (°C)

Figure 9. Maximum Duty Cycle versus Temperature

Figure 10. Lower Window Control Input Current Thresholds versus Temperature


1.34

48 CURRENT RISING

46

1.32

44

CLAMP VOLTAGE (V)

SOURCE CONTROL CURRENT THRESHOLD (A)


42 40 38 36

CURRENT FALLING

34

1.30 1.28 1.26

ISINK = 25 A

1.24 1.22 1.20

32 30 –50

–25

0

25

50

75

100

125

150

1.18 –50

–25

0

25

TEMPERATURE (°C)

50

75

100

125

150

TEMPERATURE (°C)

Figure 11. Upper Window Control Input Current Thresholds versus Temperature

Figure 12. Control Input Lower Window Clamp Voltage versus Temperature

4.67

50

4.65

ON RESISTANCE ()

CLAMP VOLTAGE (V)

4.66

4.64 4.63 ISOURCE = 25 A

4.62 4.61 4.60

NCP1050,1,2 (ID = 50 mA)

40

30 NCP1053,4,5 (ID = 100 mA) 20

10

4.59 4.58 –50

–25

0

25

50

75

100

125

0 –50

150

–25

0

TEMPERATURE (°C)

25

50

75

100

125

150

TEMPERATURE (°C)

Figure 13. Control Input Upper Window Clamp Voltage versus Temperature

Figure 14. On Resistance versus Temperature

120

100

CAPACITANCE (pF)

LEAKAGE CURRENT (A)

TJ = 25°C 100 80 60 TJ = –40°C

40

TJ = 25°C

NCP1053,4,5 10

NCP1050,1,2

20 TJ = 125°C 0

1 0

200

400

600

800

1000

0

APPLIED VOLTAGE (V)

100

200

300

400

500

600

APPLIED VOLTAGE (V)

Figure 15. Power Switch and Startup Circuit Leakage Current versus Voltage

Figure 16. Power Switch and Startup Circuit Output Capacitance versus Applied Voltage


700

NORMALIZED CURRENT LIMIT

1.02 1.00 0.98 0.96 0.94 0.92 0.90 0.88 –50

–25

0

25

50

75

100

125

150

PEAK CURRENT LIMIT DEVIATION (mA)

NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055 140 TJ = 25°C 120 100 NCP1053,4,5 80 60 NCP1050,1,2 40 20 0 0

100

TEMPERATURE (°C)

Figure 17. Normalized Peak Current Limit versus Temperature

400

500

600

4.70 UNDERVOLTAGE THRESHOLD (V)

8.6

STARTUP THRESHOLD

8.4 8.2 8.0 7.8 7.6

MINIMUM OPERATING THRESHOLD

7.4 7.2 7.0 6.8 –50

–25

0

25

50

75

100

125

150

4.65 4.60 4.55 4.50 4.45 4.40 4.35 4.30 –50

–25

0

TEMPERATURE (°C)

25

50

75

100

125

150

TEMPERATURE (°C)

Figure 19. Supply Voltage Thresholds versus Temperature

Figure 20. Undervoltage Lockout Threshold versus Temperature

7.0

7

6.0

STARTUP CURRENT (mA)

6.5 START CURRENT (mA)

300

Figure 18. Peak Current Limit Deviation versus Current Slew Rate

8.8 SUPPLY THRESHOLD (V)

200

CURRENT SLEW RATE (mA/sec)

VCC = 0 V

5.5 5.0 4.5

VCC = 8.4 V

4.0 VPIN 5 = 40 V

5 4 3 TJ = 25°C VPIN 5 = 40 V

2 1

3.5 3.0 –50

6

0 –25

0

25

50

75

100

125

150

0

TEMPERATURE (°C)

1

2

3

4

5

6

7

8

SUPPLY VOLTAGE (V)

Figure 21. Start Current versus Temperature

Figure 22. Startup Current versus Supply Voltage


9

NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055 0.60 C SUFFIX, SWITCHING ENABLED

6 SUPPLY CURRENT (mA)

STARTUP CURRENT (mA)

7

VCC = 0 V 5 VCC = 8 V 4 3 2 TJ = 25°C

0.55

0.50

B SUFFIX, SWITCHING ENABLED A SUFFIX, SWITCHING ENABLED

0.45 SWITCHING DISABLED 0.40

1 0 1

10

100

0.35 –50

1000

–25

0

PIN 5 VOLTAGE (V)

Figure 23. Startup Current versus Pin 5 Voltage

75

100

125

150

0.20 C SUFFIX, SWITCHING ENABLED

0.65

0.19 SUPPLY CURRENT (mA)

SUPPLY CURRENT (mA)

50

Figure 24. Supply Current versus Temperature (NCP1050/1/2)

0.70

0.60

25

TEMPERATURE (°C)

B SUFFIX, SWITCHING ENABLED

0.55

0.50 0.45 –50

A SUFFIX, SWITCHING ENABLED –25

0

25

50

75

100

125

0.18 0.17 0.16 0.15 0.14 0.13

150

0.12 –50

TEMPERATURE (°C)

–25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 25. Supply Current versus Temperature (NCP1053/4/5)

Figure 26. Supply Current in Fault Condition versus Temperature


150

NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055 OPERATING DESCRIPTION approximately 47 µA with 10 µA hysteresis. When a source or sink current in excess of this value is applied to this input, a logic signal generated internally changes state to block power switch conduction. Since the output of the Control Input sense is sampled continuously during ton (77% duty cycle), it is possible to turn the Power Switch Circuit on or off at any time within ton. Because it does not have to wait for the next cycle (rising edge of the clock signal) to switch on, and because it does not have to wait for current limit to turn off, the circuit has a very fast transient response as shown in Figure 3. In a typical converter application the control input current is drawn by an optocoupler. The collector of the optocoupler is connected to the Control Input pin and the emitter is connected to ground. The optocoupler LED is mounted in series with a shunt regulator (typically a TL431) at the DC output of the converter. When the power supply output is greater than the reference voltage (shunt regulator voltage plus optocoupler diode voltage drop), the optocoupler turns on, pulling down on the Control Input. The control input logic is configured for line input sensing as well.

Introduction

The NCP105X series represents a new higher level of integration by providing on a single monolithic chip all of the active power, control, logic, and protection circuitry required to implement a high voltage flyback converter and compliance with very low standby power requirements for modern consumer electronic power supplies. This device series is designed for direct operation from a rectified 240 VAC line source and requires minimal external components for a complete cost sensitive converter solution. Potential markets include cellular phone chargers, standby power supplies for personal computers, secondary bias supplies for microprocessor keep–alive supplies and IR detectors. A description of each of the functional blocks is given below, and the representative block diagram is shown in Figure 2. This device series features an active startup regulator circuit that eliminates the need for an auxiliary bias winding on the converter transformer, fault logic with a programmable timer for converter overload protection, unique gated oscillator configuration for extremely fast loop response with double pulse suppression, oscillator frequency dithering with a controlled slew rate driver for reduced EMI, cycle–by–cycle current limiting, input undervoltage lockout with hysteresis, thermal shutdown, and auto restart or latched off fault detect device options. These devices are available in an economical 8–pin PDIP package.

Turn On Latch

The Oscillator output is typically a 77% positive duty cycle square waveform. This waveform is inverted and applied to the reset input of the turn–on latch to prevent any power switch conduction during the guaranteed off time. This square wave is also gated by the output of the control section and applied to the set input of the same latch. Because of this gating action, the power switch can be activated when the control input is not asserted and the oscillator output is high. The use of this unique gated Turn On Latch over an ordinary Gated Oscillator allows a faster load transient response. The power switch is allowed to turn on immediately, within the maximum duty cycle time period, when the control input signals a necessary change in state.

Oscillator

The Oscillator is a unique fixed–frequency, duty–cycle– controlled oscillator. It charges and discharges an on chip timing capacitor to generate a precise square wave signal used to pulse width modulate the Power Switch Circuit. During the discharge of the timing capacitor, the Oscillator duty cycle output holds one input of the Driver low. This action keeps the Power Switch Circuit off, thus limiting the maximum duty cycle. A frequency modulation feature is incorporated into the IC in order to aide in EMI reduction. Figure 3 illustrates this frequency modulation feature. The power supply voltage, VCC, acts as the input to the built–in voltage controlled oscillator. As the VCC voltage is swept across its nominal operating range of 7.6 to 8.6 V, the oscillator frequency is swept across its corresponding range. The center oscillator frequency is internally programmed for 44 kHz, 100 kHz, or 136 kHz operation with a controlled charge to discharge current ratio that yields a maximum Power Switch duty cycle of 77%. The Oscillator temperature characteristics are shown in Figures 5 through 9. Contact an ON Semiconductor sales representative for further information regarding frequency options.

Turn Off Latch

A Turn Off Latch feature has been incorporated into this device series to protect the power switch circuit from excessive current, and to reduce the possibility of output overshoot in reaction to a sudden load removal. If the Power Switch current reaches the specified maximum current limit, the Current Limit Comparator resets the Turn Off Latch and turns the Power Switch Circuit off. The turn off latch is also reset when the Oscillator output signal goes low or the Control Input is asserted, thus terminating output MOSFET conduction. Because of this response to control input signals, it provides a very fast transient response and very tight load regulation. The turn off latch has an edge triggered set input which ensures that the switch can only be activated once during any oscillator period. This is commonly referred to as double pulse suppression.

Control Input

The Control Input pin circuit has parallel source follower input stages with voltage clamps set at 1.3 and 4.6 V. Current sources clamp the input current through the followers at


NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055 Current Limit Comparator and Power Switch Circuit


The Power Switch Circuit is constructed with a SENSEFETt in order to monitor the drain current. A portion of the current flowing through the circuit goes into a sense element, Rsense. The current limit comparator detects if the voltage across Rsense exceeds the reference level that is present at its inverting input. If this level is exceeded, the comparator quickly resets the Turn Off Latch, thus protecting the Power Switch Circuit. A Leading Edge Blanking circuit was placed in the current sensing signal path to prevent a premature reset of the Turn Off Latch. A potential premature reset signal is generated each time the Power Switch Circuit is driven into conduction and appears as a narrow voltage spike across current sense resistor Rsense. The spike is due to the Power Switch Circuit gate to source capacitance, transformer interwinding capacitance, and output rectifier recovery time. The Leading Edge Blanking circuit has a dynamic behavior that masks the current signal until the Power Switch Circuit turn–on transition is completed. The current limit propagation delay time is typically 125 to 250 nanoseconds. This time is measured from when an overcurrent appears at the Power Switch Circuit drain, to the beginning of turn–off. Care must be taken during transformer saturation so that the maximum device current limit rating is not exceeded. The high voltage Power Switch Circuit is monolithically integrated with the control logic circuitry and is designed to directly drive the converter transformer. Because the characteristics of the power switch circuit are well known, the gate drive has been tailored to control switching transitions to help limit electromagnetic interference (EMI). The Power Switch Circuit is capable of switching 700 V with an associated drain current that ranges nominally from 0.10 to 0.68 Amps.

An Undervoltage Lockout (UVLO) comparator is included to guarantee that the integrated circuit has sufficient voltage to be fully functional. The UVLO comparator monitors the supply capacitor input voltage at Pin 1 and disables the Power Switch Circuit whenever the capacitor voltage drops below the undervoltage lockout threshold. When this level is crossed, the controller enters a new startup phase by turning the current source on. The supply voltage will then have to exceed the startup threshold in order to turn off the startup current source. Startup and normal operation of the converter are shown in Figure 3. Fault Logic and Timer Control

The NCP105X series has integrated Fault Logic and Timer Control circuitry for detecting application fault conditions such as open loop, overload or a short circuited output. A timer is generated by driving the supply capacitor with a known current and hysteretically regulating the supply voltage between set thresholds. The timer period starts when the supply voltage reaches the nominal upper threshold of 8.6 V and stops when the drain current of the integrated circuit draws the supply capacitor voltage down to the undervoltage lockout threshold of 7.6 V. If, during this timer period, no feedback has been applied to the control input, the fault logic is set to indicate an abnormal condition. This may occur, for example, when the optocoupler fails or the output of the application is overloaded or completely shorted. In this case, the part will stop switching, go into a low power mode, and begin to draw down the supply capacitor to the reset threshold voltage of 4.6 V. At that time, the startup circuit will turn on again to drive the supply to the turn on threshold. Then the part will begin the cycle again, effectively sampling the control input to determine if the fault condition has been removed. This mode is commonly referred to as burst mode operation and is shown is Figure 4. Proper selection of the supply capacitor allows successful startup with monotonically increasing output voltage, without falsely sensing a fault condition. Figure 4 shows successful startup and the evolution of the signals involved in the presence of a fault.

Startup Circuit

Rectified AC line voltage is applied to the Startup Circuit on Pin 5, through the primary winding. The circuit is self–biasing and acts as a constant current source, gated by control logic. Upon application of the AC line voltage, this circuit routes current into the supply capacitor typically connected to Pin 1. During normal operation, this capacitor is hysteretically regulated from 7.6 to 8.6 V by monitoring the supply voltage with a comparator and controlling the startup current source accordingly. This Dynamic Self–Supply (DSS) functionality offers a great deal of applications flexibility as well. The startup circuit is rated at a maximum 700 V (maximum power dissipation limits must be observed).

Thermal Shutdown

The internal Thermal Shutdown block protects the device in the event that the maximum junction temperature is exceeded. When activated, typically at 160_C, one input of the Driver is held low to disable the Power Switch Circuit. The Power Switch is allowed to resume operation when the junction temperature falls below 85_C. The thermal shutdown feature is provided to prevent catastrophic device failures from accidental overheating. It is not intended to be used as a substitute for proper heatsinking.


NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055 APPLICATIONS to provide a tightly regulated DC output. IC3 is a shunt regulator that samples the output voltage by virtue of R5 and R6 to provide drive to the optocoupler, IC2, Light Emitting Diode (LED). C10 is used to compensate the shunt regulator. When the application is configured as a Charger, Q1 delivers additional drive to the optocoupler LED when in constant current operation by sampling the output current through R7 and R8.

Two application examples have been provided in this document, and they are described in detail in this section. Figure 27 shows a Universal Input, 10 Watt Converter Application as well as a 5.5 Watt Charger Application using the NCP1053B. The Charger consists of the additional components Q1, C13, and R7 through R10, as shown. These were constructed and tested using the printed circuit board layout shown in Figure 39. The board consists of a fiberglass epoxy material (FR4) with a single side of two ounce per square foot (70 m thick) copper foil. Test data from the two applications is given in Figures 28 through 38. Both applications generate a well–regulated output voltage over a wide range of line input voltage and load current values. The charger application transitions to a constant current output if the load current is increased beyond a preset range. This can be very effective for battery charger application for portable products such as cellular telephones, personal digital assistants, and pagers. Using the NCP105X series in applications such as these offers a wide range of flexibility for the system designer. The NCP105X application offers a low cost alternative to other applications. It uses a Dynamic Self–Supply (DSS) function to generate its own operating supply voltage such that an auxiliary transformer winding is not needed. (It also offers the flexibility to override this function with an auxiliary winding if ultra–low standby power is the designer’s main concern.) This product also provides for automatic output overload, short circuit, and open loop protection by entering a programmable duty cycle burst mode of operation. This eliminates the need for expensive devices overrated for power dissipation or maximum current, or for redundant feedback loops. The application shown in Figure 27 can be broken down into sections for the purpose of operating description. Components C1, L1 and C6 provide EMI filtering for the design, although this is very dependent upon board layout, component type, etc. D1 through D4 along with C2 provide the AC to bulk DC rectification. The NCP1053 drives the primary side of the transformer, and the capacitor, C5, is an integral part of the Dynamic Self–Supply. R1, C3, and D5 comprise an RCD snubber and R2 and C4 comprise a ringing damper both acting together to protect the IC from voltage transients greater than 700 volts and reduce radiated noise from the converter. Diode D6 along with C7–9, L2, C11, and C12 rectify the transformer secondary and filter the output

Component Selection Guidelines

Choose snubber components R1, C3, and D5 such that the voltage on pin 5 is limited to the range from 0 to 700 volts. These components protect the IC from substrate injection if the voltage was to go below zero volts, and from avalanche if the voltage was to go above 700 volts, at the cost of slightly reduced efficiency. For lower power design, a simple RC snubber as shown, or connected to ground, can be sufficient. Ensure that these component values are chosen based upon the worst–case transformer leakage inductance and worst–case applied voltage. Choose R2 and C4 for best performance radiated switching noise. Capacitor C5 serves multiple purposes. It is used along with the internal startup circuitry to provide power to the IC in lieu of a separate auxiliary winding. It also serves to provide timing for the oscillator frequency sweep for limiting the conducted EMI emissions. The value of C5 will also determine the response during an output fault (overload or short circuit) or open loop condition as shown in Figure 4, along with the total output capacitance. Resistors R5 and R6 will determine the regulated output voltage along with the reference voltage chosen with IC3. The base to emitter voltage drop of Q1 along with the value of R7 will set the fixed current limit value of the Charger application. R9 is used to limit the base current of Q1. Component R8 can be selected to keep the current limit fixed with very low values of output voltage or to provide current limit foldback with results as shown in Figures 28 and 32. A relatively large value of R8 allows for enough output voltage to effectively drive the optocoupler LED for fixed current limit. A low value of R8, along with resistor R10, provides for a low average output power using the fault protection feature when the output voltage is very low. C13 provides for output voltage stability when the Charger application is in current limit.


D1 1N4006

D6 1N5822

T1

L2 5 H

1105

http://onsemi.com

Figure 27. Universal Input 10/5.5 Watt Converter/Charger Application

C4 50 p

Vin 85 – 265 VAC C1 0.1

L1 10 mH

R1 91 k

D2 1N4006

C3 220 p

C8 330

R2 2.2 k

D3 1N4006

D4 1N4006

C7 330

C2 33

C9 330

R3 47

R6 2.20 k

IC2 SFH 615A–4

D5 MUR160

R4* 1.0 k C13* 1.0

R10* 220

C10 0.22

R9* 22 Ω

NCP1053B Q1*

IC3 TL431

2N3904 C5 10

5.25 V 1.91 A

C6 100 p

R7* 0.5 Ω/1 W

R8* 1.2 Ω/1 W

T1: COOPER ELECTRONIC TECHNOLOGIES PART # CTX22–15348 PRIMARY: 97 turns of #29 AWG, Pin 4 = start, Pin 5 = finish SECONDARY: 5 turns of 0.40 mm, Pins 2 and 1 = start, Pins 7 and 8 = finish GAP: Designed for Total 1.24 mH Primary Inductance CORE: TSF–7070 BOBBIN: Pins 3 and 6 Removed, EE19

* Add Q1, C13, and R7–R10, and Change R4 to 2.0 k for Charger Output

R5 2.00 k

C11 220

C12 1.0


F1 2.0 A

NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055 Test Line Regulation

Conditions

Converter Results

Vin = 85 – 265 VAC; Iout = 190 mA Vin = 85 – 265 VAC; Iout = 950 mA Vin = 85 – 265 VAC; Iout = 1.91 A

1 mV 1 mV 2 mV

Vin = 85 – 265 VAC; Iout = 100 mA Vin = 85 – 265 VAC; Iout = 500 mA Vin = 85 – 265 VAC; Iout = 1.00 A Load Regulation

Vin = 85 VAC; Iout = 190 mA – 1.91 A Vin = 110 VAC; Iout = 190 mA – 1.91 A Vin = 230 VAC; Iout = 190 mA – 1.91 A Vin = 265 VAC; Iout = 190 mA – 1.91 A

2 mV 3 mV 7 mV 1 mV 2 mV 3 mV 3 mV

Vin = 85 VAC; Iout = 100 mA – 1.00 A Vin = 110 VAC; Iout = 100 mA – 1.00 A Vin = 230 VAC; Iout = 100 mA – 1.00 A Vin = 265 VAC; Iout = 100 mA – 1.00 A Output Ripple

Vin = 110 VAC; Iout = 1.91 A Vin = 230 VAC; Iout = 1.91 A

8 mV 9 mV 9 mV 12 mV 40 mVp–p 50 mVp–p

Vin = 110 VAC; Iout = 1.00 A Vin = 230 VAC; Iout = 1.00 A Efficiency

Charger Results

40 mVp–p 50 mVp–p

Vin = 110 VAC; Iout = 1.91 A Vin = 230 VAC; Iout = 1.91 A

72.0% 71.2%

Vin = 110 VAC; R8 = 1.2 , Iout = 1.00 A Vin = 230 VAC; R8 = 1.2 , Iout = 1.00 A

52.2% 52.8%

Vin = 110 VAC; R8 = 0 , Iout = 1.00 A Vin = 230 VAC; R8 = 0 , Iout = 1.00 A

65.0% 62.4%

No Load Input Power

Vin = 110 VAC; Iout = 0 A Vin = 230 VAC; Iout = 0 A

110 mW 240 mW

110 mW 190 mW

Standby Output Power

Vin = 110 VAC; Pin = 1 W Vin = 230 VAC; Pin = 1 W

675 mW 570 mW

635 mW 570 mW

Short Circuit Load Input Power

Vin = 110 VAC; Vout = 0 V (Shorted) Vin = 230 VAC; Vout = 0 V (Shorted)

500 mW 750 mW

Vin = 110 VAC; R8 = 1.2 , Vout = 0 V (Shorted) Vin = 230 VAC; R8 = 1.2 , Vout = 0 V (Shorted)

1.05 W 1.40 W

Vin = 110 VAC; R8 = 0 , Vout = 0 V (Shorted) Vin = 230 VAC; R8 = 0 , Vout = 0 V (Shorted)

900 mW 1.25 W

Figure 28. Converter and Charger Test Data Summary


NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055 5.250

5.250

5.245

OUTPUT VOLTAGE (VDC)


Iout = 190 mA

5.240 Iout = 950 mA

5.235 Iout = 1.91 A

5.230 5.225

5.220

5.240 Iout = 100 mA 5.230 Iout = 500 mA 5.220 Iout = 1.00 A

5.210 5.200

R8 = 1.2

5.190 80

130

180

230

280

80

130

LINE INPUT VOLTAGE (VAC)

5.244

6

5.242

5

Vin = 85 VAC Vin = 110 VAC

5.238 Vin = 265 VAC

5.236

230

280

Figure 30. Charger Line Regulation



Figure 29. Converter Line Regulation

5.240

180

LINE INPUT VOLTAGE (VAC)

Vin = 230 VAC 5.234 5.232 5.230

R8 = 0 4 3 R8 = 1.2 2 1 0

0

0.5

1.0

1.5

2.0

0

0.2

0.4

LOAD CURRENT (A)

[

0.8

1.0

1.2

1.4

Figure 32. Charger Load Regulation

Figure 31. Converter Load Regulation

Tek Stop: Single Seq 50.0 kS/s

0.6

LOAD CURRENT (A)

Tek Stop: Single Seq 25.0 kS/s

]

[

]

Vout Vout

ILOAD (500 mA/div)

0 V, 0 A

Ch 1

1.00 V

Ch 2 10.0 mV M1.00 ms Ch 2

ILOAD (200 mA/div)

0V

5.8 mV

Figure 33. Converter Load Transient Response

0A

Ch 1 1.00 V Ch 3 10.0 mV

R8 = 1.2

M2.00 ms Ch 1

–40 mV

Figure 34. Charger Load Transient Response


NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055 62

80

Vin = 85 VAC Vin = 110 VAC

Vin = 85 VAC

70

EFFICIENCY (%)

EFFICIENCY (%)

60

Vin = 110 VAC

75

Vin = 230 VAC 65 Vin = 265 VAC 60

58 Vin = 230 VAC 56 54 Vin = 265 VAC 52

55

50

50

48 0

0.5

1.0

1.5

2.0

R8 = 1.2 0

0.25

0.50

LOAD CURRENT (A)

Figure 35. Converter Efficiency

Tek Stop: Single Seq 500 S/s

[

0.75

Tek Stop: Single Seq 500 S/s

]

[

]

ILOAD = 500 mA R8 = 1.2 Vout

Vout

VLINE, RECTIFIED

Ch 1

1.00 V

1.25

Figure 36. Charger Efficiency

ILOAD = 1.0 A

0V

1.00

LOAD CURRENT (A)

Ch 2 50.0 V

VLINE, RECTIFIED

M 100 ms Ch 2

17 V

0V

Ch 1

Figure 37. Converter On/Off Line Transient Response

1.00 V

Ch 2

50.0 V

M 100 ms Ch 2

Figure 38. Charger On/Off Line Transient Response


28 V

NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055 Board Graphics

DC Output

AC Input

R5

R6

R4

C5

–

+

IC3

F1

C12

C1

–

IC2

+

C10 R9 +

R8 L1

C11

–

IC1

Q1

L2

R7

D4

C6

D2

R3 +

C9

–

D3 D5

D1

T1

R2

D6 +

–

C2

C8

–

R1 +

C3 C4

+

C7

Top View 2.75″

2.25″

NCP1050 Series

Bottom View

Figure 39. Printed Circuit Board and Component Layout


–

NCP1050, NCP1051, NCP1052, NCP1053, NCP1054, NCP1055 DEVICE ORDERING INFORMATION (Note 10) Device (Note 11)

Package

Shipping

RDS(on) (W)

NCP1050PZZZ

100

NCP1051PZZZ

30

NCP1052PZZZ NCP1053PZZZ

Ipk (mA)

200 300

DIP 8 DIP–8

50 Units/Rail

NCP1054PZZZ

400 15

NCP1055PZZZ

530 680

10. Consult factory for additional optocoupler fail–safe latching, frequency, current limit and line input options. 11. ZZZ = Oscillator Frequency in kHz (44, 100 or 136)


""") ; + : 1 4 http://onsemi.com MARKING DIAGRAMS 16 DIP–16 P SUFFIX CASE 648

16

MC33368P AWLYYWW 1 16

1 SO–16 D SUFFIX CASE 751K

16 1 A WL YY, Y WW

MC33368D AWLYWW

1 = Assembly Location = Wafer Lot = Year = Work Week

PIN CONNECTIONS >9 &%

"

, +0

9 &% , +0

*C"0 5+ &55

1 &!



August, 2000 – Rev. 5

1111

Package

Shipping

MC33368D

SO–16

48 Units/Rail

MC33368DR2

SO–16

2500 Tape & Reel

MC33368P

DIP–16

25 Units/Rail


MC33368 Representative Block Diagram " , +0

, +0

&55

@@+ *5 + 85" " I5

2&

++; 8 4+%

6

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&% 4"#

,

5" "

7

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*C"0 5+


MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating

Power Supply Voltage (Transient)

Symbol

Value

Unit

VCC

20

V

Power Supply Voltage (Operating)

VCC

16

V

Line Voltage

VLine

500

V

Current Sense, Multiplier, Compensation, Voltage Feedback, Restart Delay and Zero Current Input Voltage

Vin1

–1.0 to +10

V

LEB Input, Frequency Clamp Input

Vin2

–1.0 to +20

V

Zero Current Detect Input

Iin

±5.0

mA

Restart Diode Current

Iin

5.0

mA

Power Dissipation and Thermal Characteristics P Suffix, Plastic Package Case 648 Maximum Power Dissipation @ TA = 25°C Thermal Resistance, Junction–to–Air

PD RθJA

1.25 100

W °C/W

Power Dissipation and Thermal Characteristics D Suffix, Plastic Package Case 751K Maximum Power Dissipation @ TA = 70°C Thermal Resistance, Junction–to–Air

PD RθJA

450 178

mW °C/W


TJ

150

°C


TA

–25 to +125

°C


Tstg

–55 to +150

°C



MC33368 ELECTRICAL CHARACTERISTICS (VCC = 14.5 V, for typical values TA = 25°C, for min/max values TJ = –25 to +125°C) Characteristic

Symbol

Min

Typ

Max

Input Bias Current (VFB = 5.0 V)

IIB

Input Offset Voltage (VComp = 3.0 V)

VIO

Transconductance (VComp = 3.0 V)

Output Source (VFB = 4.6 V, VComp = 3.0 V) Output Sink (VFB = 5.4 V, VComp = 3.0 V)

Unit

–

0

1.0

µA

–

2.0

50

mV

gm

30

51

80

µmho

IO IO

9.0 9.0

17.5 17.5

30 30

µA

VFB(OV)

1.07 VFB

1.084 VFB

1.1 VFB

V

TP

–

705

–

ns

IIB

–

–0.2

–1.0

µA

Input Threshold, VComp

Vth(M)

1.8

2.1

2.4

V

Dynamic Input Voltage Range Multiplier Input Compensation

VMult VComp

0 to 2.5 Vth(M) to (Vth(M) + 1.0)

0 to 3.5 Vth(M) to (Vth(M) + 2.0)

– –

K

0.25

0.51

0.75

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ERROR AMPLIFIER

OVERVOLTAGE COMPARATOR

Voltage Feedback Input Threshold Propagation Time to Output

MULTIPLIER

Input Bias Current, VMult (VFB = 0 V)

V

ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ȡ ȣ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ȧ ȧ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ǒ ǓȤ Ȣ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Multiplier Gain (VMult = 0.5 V, VComp = Vth(M) + 1.0 V) V

K+

V

CS

Mult

V

1/V

Threshold

–V th(M) Comp

VOLTAGE REFERENCE

Voltage Reference (IO = 0 mA, TJ = 25°C)

Vref

4.95

5.0

5.05

V


Regline

–

5.0

100

mV

Load Regulation (IO = 0 – 5.0 mA)

Regload

–

5.0

100

mV

Vref

4.8

–

5.2

V

Maximum Output Current

IO

5.0

10

–

mA

Reference Undervoltage Lockout Threshold

Vth

–

4.5

–

V

Input Threshold Voltage (Vin Increasing)

Vth

1.0

1.2

1.4

V

Hysteresis (Vin Decreasing)

VH

100

200

300

mV

Delay to Output

Tpd

–

127

–

ns

Input Bias Current (VCS = 0 to 2.0 V)

IIB

–

0.2

1.0

µA

Input Offset Voltage (VMult = –0.2 V)

VIO

–

4.0

50

mV

Vth(max)

1.3

1.5

1.8

V

tPHL(in/out)

50

270

425

ns

Vth(FC)

1.9

2.0

2.1

V

Frequency Clamp Capacitor Reset Current (VFC = 0.5 V)

Ireset

0.5

1.7

4.0

mA

Frequency Clamp Disable Voltage

VDFC

–

7.3

8.0

V

Total Output Variation Over Line, Load and Temperature

ZERO CURRENT DETECTOR

CURRENT SENSE COMPARATOR

Maximum Current Sense Input Threshold (VComp = 5.0 V, VMult = 5.0 V)

Delay to Output (VLEB = 12 V, VComp = 5.0 V, VMult = 5.0 V) (VCS = 0 to 5.0 V Step, CL = 1.0 nF)

FREQUENCY CLAMP

Frequency Clamp Input Threshold


MC33368 ELECTRICAL CHARACTERISTICS (continued) (VCC = 14.5 V, for typical values TA = 25°C, for min/max values TJ = –25 to +125°C)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Characteristic

Symbol

Min

Typ

Max

Unit

Source Resistance (Current Sense = 0 V, VGate = VCC – 1.0 V) Sink Resistance (Current Sense = 3.0 V, VGate = 1.0 V)

ROH ROL

4.0 4.0

8.6 7.2

20 20

Ω

Output Voltage Rise Time (25% – 75%) (CL = 1.0 nF)

tr

–

55

200

ns

Output Voltage Fall Time (75% – 25%) (CL = 1.0 nF)

tf

–

70

200

ns

VO(UV)

–

0.01

0.25

V

Input Bias Current

Ibias

–

0.1

0.5

µA

Threshold (as Offset from VCC) (VLEB Increasing)

VLEB

1.0

2.25

2.75

V

VH

100

270

500

mV

Vth(on)

11.5

13

14.5

V

VShutdown

7.0

8.5

10

V

VH

–

4.5

–

V

tDLY

180

385

800

µs

Vth(restart)

1.5

2.3

3.0

V

Irestart

3.1

5.2

7.1

mA

Line Startup Current (VCC = 0 V, VLine = 50 V)

ISU

5.0

16

25

mA

Line Operating Current (VCC = Vth(on), VLine = 50 V)

IOP

3.0

12.9

20

mA

VCC Dynamic Operating Current (50 kHz, CL = 1.0 nF) VCC Static Operating Current (IO = 0)

ICC

– –

5.3 3.0

8.5 –

mA

Line Pin Leakage (VLine = 500 V)

ILine

–

30

80

µA

DRIVE OUTPUT

Output Voltage in Undervoltage (VCC = 7.0 V, ISink = 1.0 mA)

LEADING EDGE BLANKING

Hysteresis (VLEB Decreasing)

UNDERVOLTAGE LOCKOUT

Startup Threshold (VCC Increasing)

Minimum Operating Voltage After Turn–On (VCC Decreasing) Hysteresis

TIMER

Watchdog Timer

Restart Timer Threshold

Restart Pin Output Current (Vrestart = 0 V, Vref = 5.0 V)

TOTAL DEVICE


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MC33368 FUNCTIONAL DESCRIPTION INTRODUCTION

of the ac line, they are smaller, lighter in weight, and more efficient than a passive circuit that yields similar results. With proper control of the preconverter, almost any complex load can be made to appear resistive to the ac line, thus significantly reducing the harmonic current content.

With the goal of exceeding the requirements of legislation on line current harmonic content, there is an ever increasing demand for an economical method of obtaining a unity power factor. This data sheet describes a monolithic control IC that was specifically designed for power factor control with minimal external components. It offers the designer a simple cost effective solution to obtain the benefits of active power factor correction. Most electronic ballasts and switching power supplies use a bridge rectifier and a bulk storage capacitor to derive raw dc voltage from the utility ac line, Figure 13.

Operating Description

The MC33368 contains many of the building blocks and protection features that are employed in modern high performance current mode power supply controllers. Referring to the block diagram in Figure 15, note that a multiplier has been added to the current sense loop and that this device does not contain an oscillator. A description of each of the functional blocks is given below.

5"@

,% -+' 5

45 "

Error Amplifier

#

An Error Amplifier with access to the inverting input and output is provided. The amplifier is a transconductance type, meaning that it has high output impedance with controlled voltage–to–current gain (gm 50 µmhos). The noninverting input is internally biased at 5.0 V ±2.0%. The output voltage of the power factor converter is typically divided down and monitored by the inverting input. The maximum input bias current is –1.0 µA which can cause an output voltage error that is equal to the product of the input bias current and the value of the upper divider resistor R2. The Error Amplifier output is internally connected to the Multiplier and is pinned out (Pin 4) for external loop compensation. Typically, the bandwidth is set below 20 Hz so that the amplifier’s output voltage is relatively constant over a given ac line cycle. In effect, the error amplifier monitors the average output voltage of the converter over several line cycles resulting in a fixed Drive Output on–time. The amplifier output stage can sink and source 11.5 µA of current and is capable of swinging from 1.7 to 5.0 V, assuring that the Multiplier can be driven over its entire dynamic range. Note that by using a transconductance type amplifier, the input is allowed to move independently with respect to the output, since the compensation capacitor is connected to ground. This allows dual usage of the Voltage Feedback pin by the Error Amplifier and Overvoltage Comparator.

Figure 13. Uncorrected Power Factor Circuit

This simple rectifying circuit draws power from the line when the instantaneous ac voltage exceeds the capacitor voltage. This occurs near the line voltage peak and results in a high charge current spike, Figure 14. Since power is only taken near the line voltage peaks, the resulting spikes of current are extremely nonsinusoidal with a high content of harmonics. This results in a poor power factor condition where the apparent input power is much higher than the real power. Power factor ratios of 0.5 to 0.7 are common. &' ,%#

5 9

"

45 " &+ 9 45 " 5"

Overvoltage Comparator

An Overvoltage Comparator is incorporated to eliminate the possibility of runaway output voltage. This condition can occur during initial startup, sudden load removal, or during output arcing and is the result of the low bandwidth that must be used in the Error Amplifier control loop. The Overvoltage Comparator monitors the peak output voltage of the converter, and when exceeded, immediately terminates MOSFET switching. The comparator threshold is internally set to 1.08 Vref. In order to prevent false tripping during normal operation, the value of the output filter capacitor C3 must be large enough to keep the peak–to–peak ripple less than 16% of the average dc output.

Figure 14. Uncorrected Power Factor Input Waveforms

Power factor correction can be achieved with the use of either a passive or active input circuit. Passive circuits usually contain a combination of large capacitors, inductors, and rectifiers that operate at the ac line frequency. Active circuits incorporate some form of a high frequency switching converter for the power processing with the boost converter being the most popular topology. Since active input circuits operate at a frequency much higher than that


MC33368 Multiplier

Sense Comparator threshold will be internally clamped to 1.5 V. Therefore, the maximum peak switch current is:

A single quadrant, two input multiplier is the critical element that enables this device to control power factor. The ac haversines are monitored at Pin 5 with respect to ground while the Error Amplifier output at Pin 4 is monitored with respect to the Voltage Feedback Input threshold. A graph of the Multiplier transfer curve is shown in Figure 1. Note that both inputs are extremely linear over a wide dynamic range, 0 to 3.2 V for Pin 5 and 2.5 to 4.0 V for Pin 4. The Multiplier output controls the Current Sense Comparator threshold as the ac voltage traverses sinusoidally from zero to peak line. This has the effect of forcing the MOSFET on–time to track the input line voltage, thus making the preconverter load appear to be resistive.

ǒ

Pin 6 Threshold [ 0.55 V

Pin 4

–V

I

A watchdog timer function was added to the IC to eliminate the need for an external oscillator when used in stand alone applications. The Timer provides a means to automatically start or restart the preconverter if the Drive Output has been off for more than 385 µs after the inductor current reaches zero.

Ǔ VPin 5

Pin 3

Undervoltage Lockout and Quickstart

The MC33368 has a 5.0 V internal reference brought out to Pin 1 and capable of sourcing 10 mA typically. It also contains an Undervoltage Lockout (UVLO) circuit which suppresses the Gate output at Pin 11 if the VCC supply voltage drops below 8.5 V typical. A Quickstart circuit has been incorporated to optimize converter startup. During initial startup, compensation capacitor C1 will be discharged, holding the Error Amplifier output below the Multiplier’s threshold. This will prevent Drive Output switching and delay bootstraping of capacitor C4 by diode D6. If Pin 4 does not reach the multiplier threshold before C4 discharges below the lower SMPS UVLO threshold, the converter will hiccup and experience a significant startup delay. The Quickstart circuit is designed to precharge C1 to 1.7 V. This level is slightly below the Pin 4 Multiplier threshold, allowing immediate Drive Output switching. Restart Delay

A restart delay pin is provided to allow hiccup mode fault protection in case of a short circuit condition and to prevent the SMPS from repeatedly trying to restart after the input line voltage has been removed. When power is first applied, there is no startup delay, but subsequent cycling of the VCC voltage will result in delay times that are programmed by an external resistor and capacitor. The Restart Delay, Pin 2, is a high impedance, so that an external capacitor can provide delay times as long as several seconds. If the SMPS output is short circuited, the transformer winding, which provides the VCC voltage to the control IC and the MC33368, will be unable to sustain VCC to the control circuits. The restart delay capacitor at Pin 2 of the MC33368 prevents the high voltage startup transistor within the IC from maintaining the voltage on C4. After VCC drops below the UVLO threshold in the SMPS, the SMPS switching transistors are held off for the time programmed by the values of the restart capacitor (C9) and resistor (R8). In this manner, the SMPS switching transistors are operated

Current Sense Comparator and RS Latch

The Current Sense Comparator RS Latch configuration used ensures that only a single pulse appears at the Drive Output during a given cycle. The inductor current is converted to a voltage by inserting a ground–referenced sense resistor R7 in series with the source of output switch. This voltage is monitored by the Current Sense Input and compared to a level derived from the Multiplier output. The peak inductor current under normal operating conditions is controlled by the threshold voltage of Pin 6 where: +

1.5 V R7

Timer

The MC33368 operates as a critical conduction current mode controller, whereby output switch conduction is initiated by the Zero Current Detector and terminated when the peak inductor current reaches the threshold level established by the Multiplier output. The Zero Current Detector initiates the next on–time by setting the RS Latch at the instant the inductor current reaches zero. This critical conduction mode of operation has two significant benefits. First, since the MOSFET cannot turn–on until the inductor current reaches zero, the output rectifier’s reverse recovery time becomes less critical allowing the use of an inexpensive rectifier. Second, since there are no deadtime gaps between cycles, the ac line current is continuous thus limiting the peak switch to twice the average input current The Zero Current Detector indirectly senses the inductor current by monitoring when the auxiliary winding voltage falls below 1.2 V. To prevent false tripping, 200 mV of hysteresis is provided. The Zero Current Detector input is internally protected by two clamps. The upper 10 V clamp prevents input overvoltage breakdown while the lower –0.7 V clamp prevents substrate injection. An external resistor must be used in series with the auxiliary winding to limit the current through the clamps to 5.0 mA or less.

pk

+

With the component values shown in Figure 15, the Current Sense Comparator threshold, at the peak of the haversine, varies from 110 mV at 90 Vac to 100 mV at 268 Vac. The Current Sense Input to Drive Output propagation delay is typically 200 ns.

Zero Current Detector

I

pk(max)

Pin 6 Threshold R7

Abnormal operating conditions occur when the preconverter is running at extremely low line or if output voltage sensing is lost. Under these conditions, the Current


MC33368 at very low duty cycles, preventing their destruction. If the short circuit fault is removed, the power supply system will turn on by itself in a normal startup mode after the restart delay has timed out.

For best results, the minimum off–time, determined by the values of R10 and C7, should be chosen so that ts(min) = t(on) + t(off)fc. Output drive is inhibited when the voltage at the frequency clamp input is less than 2.0 V. When the output drive is high, C7 is discharged through an internal 100 µA current source. When the output drive switches low, C7 is charged through R10. The drive output is inhibited until the voltage across C7 reaches 2.0 V, establishing a minimum off–time where:

Output Switching Frequency Clamp

In normal operation, the MC33368 operates the boost inductor in the critical mode. That is, the inductor current ramps to a peak value, ramps down to zero, then immediately begins ramping positive again. The peak current is programmed by the multiplier output within the IC. As the input voltage haversine declines to near zero, the output switch on–time becomes constant, rather than going to zero because of the small integrated dc voltage at Pin 5 caused by C2, R3 and R5. Because of this, the average line current does not exactly follow the line voltage near the zero crossings. The Output Switching Frequency Clamp remedies this situation to improve power factor and minimize EMI generated in this operating region. The values of R10 and C7, as shown in Figure 15, program a minimum off–time in the frequency clamp which overrides the zero current detect signal, forcing a minimum off–time. This allows discontinuous conduction operation of the boost inductor in the zero crossing region, and the average line current more nearly follows the voltage. The Output Switching Frequency Clamp function can be disabled by connecting the FC input, Pin 13, to the VCC supply Pin 12.

t

(off)fc

+ * R10 C7 log e

ƪ ǒ Ǔƫ 1 *

2

V

CC

Output

The IC contains a CMOS output driver that was specifically designed for direct drive of power MOSFETs. The Gate Output is capable of up to ±1500 mA peak current with a typical rise and fall time of 50 ns with a 1.0 nF load. Additional internal circuitry has been added to keep the Gate Output in a sinking mode whenever the Undervoltage Lockout is active. This characteristic eliminates the need for an external gate pull–down resistor. The totem–pole output has been optimized to minimize cross–conduction current during high speed operation.


MC33368 Table 1. Design Equations Calculation

Formula

Converter Output Power

+ V

P

O

L(pk)

ǒ

Inductance t L + P

+

Vac

O –Vac Ǹ2 (LL) Ǹ2 V

t

(on)

Minimum Switch Off–Time

t

min

In theory, the on–time t(on) is constant. In practice, t(on) tends to increase at the ac line zero crossings due to the charge on capacitor C5. Let Vac = Vac(LL) for initial t(on) and t(off) calculations. The off–time t(off) is greatest at the peak of the ac line voltage and approaches zero at the ac line zero crossings. Theta (θ) represents the angle of the ac line voltage.

(on) –1

The off–time is at a minimum at ac line crossings. This equation is used to calculate t(off) as Theta approaches zero.

L I P L(pk)

+

V

Delay Time t + – R10 C7 ln d

ǒ

O

Ǔ

V

–2 CC V CC

Switching Frequency f+

t

(on)

Peak Switch Current

Multiplier Input Voltage V

Converter Output Voltage Converter Output Peak–to–Peak Ripple Voltage

Error Amplifier Bandwidth

V

V

O(pp)

O

+ V

+I

M

+

ref

L(pk)

1 )t

V

R7 +

I

(off)

Set the current sense threshold VCS to 1.0 V for universal input (85 to 265 Vac) operation and to 0.5 V for fixed input (92 to 138 Vac, or 184 to 276 Vac) operation. Note that VCS must be less than 1.4 V.

CS

L(pk)

Set the multiplier input voltage VM to 3.0 V at high line. Empirically adjust VM for the lowest distortion over the ac line voltage range while guaranteeing startup at minimum line.

ǒR5 ) 1Ǔ R3

ǒR2 ) 1Ǔ – I IB R1 R1

BW +

The delay time is used to override the minimum off–time at the ac line zero crossings by programming the Frequency Clamp with C7 and R10. The minimum switching frequency occurs at the peak of the ac line voltage. As the ac line voltage traverses from peak to zero, t(off) approaches zero producing an increase in switching frequency.

Vac Ǹ 2

Ǹǒ

Let the switching cycle t = 40 µs for universal input (85 to 265 Vac) operation and 20 µs for fixed input (92 to 138 Vac, or 184 to 276 Vac) operation.

P O O

V O Ǹ 2 Vac ŤSin Ť

(off)

(LL)

2

L O P Vac 2 t

+

Vac

2P

+

Switch Off–Time (off)

Calculated at the minimum required ac line voltage for output regulation. Let the efficiency η = 0.92 for low line operation.

O

(LL)

Ǔ

V

Switch On–Time

t

I O O

2 Ǹ2 P

Peak Indicator Current I

Notes Calculate the maximum required output power.

Ǔ

1 2 f ac C3

2 ) ESR 2

The IIB R1 error term can be minimized with a divider current in excess of 100 µA. The calculated peak–to–peak ripple must be less than 16% of the average dc output voltage to prevent false tripping of the Overvoltage Comparator. Refer to the Overvoltage Comparator Text. ESR is the equivalent series resistance of C3. The bandwidth is typically set to 20 Hz. When operating at high ac line, the value of C1 may need to be increased.

gm 2 C1

NOTE: The following converter characteristics must be chosen: VO = Desired output voltage. Vac(LL) = AC RMS minimum required operating line voltage for output regulation. IO = Desired output current. ∆VO = Converter output peak–to–peak ripple voltage. Vac = AC RMS operating line voltage.


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An RFI filter is required for best performance when connecting the preconverter directly to the ac line. The filter attenuates the level of high frequency switching that appears on the ac line current waveform. Figures 15 and 16 work well with commercially available two stage filters such as the Delta Electronics 03DPCG6. Shown above is a single stage test filter that can easily be constructed with four ac line rated capacitors and a common–mode transformer. Coilcraft CMT3–28–2 was used to test Figures 15 and 16. It has a minimum inductance of 28 mH and a maximum current rating of 2.0 A. Coilcraft CMT4–17–9 was used to test Figure 19. It has a minimum inductance of 17 mH and a maximum current rating of 9.0 A. Circuit conversion efficiency η (%) was calculated without the power loss of the RFI filter.

Figure 17. Power Factor Test Setup

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The MC34262/MC33262 are active power factor controllers specifically designed for use as a preconverter in electronic ballast and in off–line power converter applications. These integrated circuits feature an internal startup timer for stand–alone applications, a one quadrant multiplier for near unity power factor, zero current detector to ensure critical conduction operation, transconductance error amplifier, quickstart circuit for enhanced startup, trimmed internal bandgap reference, current sensing comparator, and a totem pole output ideally suited for driving a power MOSFET. Also included are protective features consisting of an overvoltage comparator to eliminate runaway output voltage due to load removal, input undervoltage lockout with hysteresis, cycle–by–cycle current limiting, multiplier output clamp that limits maximum peak switch current, an RS latch for single pulse metering, and a drive output high state clamp for MOSFET gate protection. These devices are available in dual–in–line and surface mount plastic packages. • Overvoltage Comparator Eliminates Runaway Output Voltage • Internal Startup Timer • One Quadrant Multiplier • Zero Current Detector • Trimmed 2% Internal Bandgap Reference • Totem Pole Output with High State Clamp • Undervoltage Lockout with 6.0 V of Hysteresis • Low Startup and Operating Current • Supersedes Functionality of SG3561 and TDA4817

POWER FACTOR CONTROLLERS SEMICONDUCTOR TECHNICAL DATA

P SUFFIX PLASTIC PACKAGE CASE 626

8 1

D SUFFIX PLASTIC PACKAGE CASE 751 (SO–8)

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ORDERING INFORMATION Device MC34262D

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MC34262P MC33262D MC33262P

Operating Temperature Range TA = 0° to +85°C

TA = –40° to +105°C

Package SO–8 Plastic DIP SO–8 Plastic DIP

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1126


MC34262 MC33262 MAXIMUM RATINGS Rating

Symbol

Value

Unit

(ICC + IZ)

30

mA

Output Current, Source or Sink (Note 1)

IO

500

mA

Current Sense, Multiplier, and Voltage Feedback Inputs

Vin

–1.0 to +10

V

Zero Current Detect Input High State Forward Current Low State Reverse Current

Iin

Total Power Supply and Zener Current

mA 50 –10

Power Dissipation and Thermal Characteristics P Suffix, Plastic Package, Case 626 Maximum Power Dissipation @ TA = 70°C Thermal Resistance, Junction–to–Air D Suffix, Plastic Package, Case 751 Maximum Power Dissipation @ TA = 70°C Thermal Resistance, Junction–to–Air

PD RθJA

800 100

mW °C/W

PD RθJA

450 178

mW °C/W


TJ

+150

°C

Operating Ambient Temperature (Note 3) MC34262 MC33262

TA

Storage Temperature

Tstg

°C 0 to + 85 – 40 to +105 – 65 to +150

°C

ELECTRICAL CHARACTERISTICS (VCC = 12 V (Note 2), for typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 3], unless otherwise noted.) Characteristic

Symbol

Min

Typ

Max

2.465 2.44

2.5 —

2.535 2.54

—

1.0

10

Unit

ERROR AMPLIFIER Voltage Feedback Input Threshold TA = 25°C TA = Tlow to Thigh (VCC = 12 V to 28 V)

VFB

Line Regulation (VCC = 12 V to 28 V, TA = 25°C)

Regline

V

mV

Input Bias Current (VFB = 0 V)

IIB

—

– 0.1

– 0.5

µA

Transconductance (TA = 25°C)

gm

80

100

130

µmho

Output Current Source (VFB = 2.3 V) Sink (VFB = 2.7 V)

IO — —

10 10

— —

VOH(ea) VOL(ea)

5.8 —

6.4 1.7

— 2.4

VFB(OV)

1.065 VFB

1.08 VFB

1.095 VFB

V

IIB

—

– 0.1

– 0.5

µA

Input Threshold, Pin 2

Vth(M)

1.05 VOL(EA)

1.2 VOL(EA)

—

V

Dynamic Input Voltage Range Multiplier Input (Pin 3) Compensation (Pin 2)

VPin 3 VPin 2

0 to 2.5 Vth(M) to (Vth(M) + 1.0)

0 to 3.5 Vth(M) to (Vth(M) + 1.5)

— —

K

0.43

0.65

0.87

1/V

Input Threshold Voltage (Vin Increasing)

Vth

1.33

1.6

1.87

V

Hysteresis (Vin Decreasing)

VH

100

200

300

mV

Input Clamp Voltage High State (IDET = + 3.0 mA) Low State (IDET = – 3.0 mA)

VIH VIL

6.1 0.3

6.7 0.7

— 1.0

Output Voltage Swing High State (VFB = 2.3 V) Low State (VFB = 2.7 V)

µA

V

OVERVOLTAGE COMPARATOR Voltage Feedback Input Threshold MULTIPLIER Input Bias Current, Pin 3 (VFB = 0 V)

V

Multiplier Gain (VPin 3 = 0.5 V, VPin 2 = Vth(M) + 1.0 V) (Note 4) ZERO CURRENT DETECTOR

V


MC34262 MC33262 ELECTRICAL CHARACTERISTICS (VCC = 12 V (Note 2), for typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies (Note 3), unless otherwise noted.) Symbol

Min

Typ

Max

Unit

Input Bias Current (VPin 4 = 0 V)

IIB

—

– 0.15

–1.0

µA

Input Offset Voltage (VPin 2 = 1.1 V, VPin 3 = 0 V)

VIO

—

9.0

25

mV

Vth(max)

1.3

1.5

1.8

V

tPHL(in/out)

—

200

400

ns

VOL

— — 9.8 7.8

0.3 2.4 10.3 8.4

0.8 3.3 — —

14

16

18

50

120

ns

Characteristic CURRENT SENSE COMPARATOR

Maximum Current Sense Input Threshold (Note 5) Delay to Output DRIVE OUTPUT Output Voltage (VCC = 12 V) Low State (ISink = 20 mA) Low State (ISink = 200 mA) High State (ISource = 20 mA) High State (ISource = 200 mA)

V

VOH

Output Voltage (VCC = 30 V) High State (ISource = 20 mA, CL = 15 pF)

VO(max)

Output Voltage Rise Time (CL = 1.0 nF)

tr

—

Output Voltage Fall Time (CL = 1.0 nF) Output Voltage with UVLO Activated (VCC = 7.0 V, ISink = 1.0 mA)

V

tf

—

50

120

ns

VO(UVLO)

—

0.1

0.5

V

tDLY

200

620

—

µs

RESTART TIMER Restart Time Delay UNDERVOLTAGE LOCKOUT Startup Threshold (VCC Increasing) Minimum Operating Voltage After Turn–On (VCC Decreasing)

Vth(on)

11.5

13

14.5

V

VShutdown

7.0

8.0

9.0

V

VH

3.8

5.0

6.2

V

— — —

0.25 6.5 9.0

0.4 12 20

30

36

—

Hysteresis TOTAL DEVICE Power Supply Current Startup (VCC = 7.0 V) Operating Dynamic Operating (50 kHz, CL = 1.0 nF)

ICC

Power Supply Zener Voltage (ICC = 25 mA)

VZ

mA

NOTES: 1. Maximum package power dissipation limits must be observed. 2. Adjust VCC above the startup threshold before setting to 12 V. 3. Tlow = 0°C for MC34262 3. Tlow = – 40°C for MC33262

4. K =

Thigh = + 85°C for MC34262 Thigh = +105°C for MC33262

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Figure 22. Current Sense Input Threshold versus Multiplier Input, Expanded View

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Figure 47. Negative Current Waveform Spike Suppression

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The MC33260 is a controller for Power Factor Correction preconverters meeting international standard requirements in electronic ballast and off–line power conversion applications. Designed to drive a free frequency discontinuous mode, it can also be synchronized and in any case, it features very effective protections that ensure a safe and reliable operation. This circuit is also optimized to offer extremely compact and cost effective PFC solutions. While it requires a minimum number of external components, the MC33260 can control the follower boost operation that is an innovative mode allowing a drastic size reduction of both the inductor and the power switch. Ultimately, the solution system cost is significantly lowered. Also able to function in a traditional way (constant output voltage regulation level), any intermediary solutions can be easily implemented. This flexibility makes it ideal to optimally cope with a wide range of applications. Standard Constant Output Voltage or “Follower Boost” Mode Switch Mode Operation: Voltage Mode Latching PWM for Cycle–by–Cycle On–Time Control Constant On–Time Operation That Saves the Use of an Extra Multiplier Totem Pole Output Gate Drive Undervoltage Lockout with Hysteresis Low Start–Up and Operating Current Improved Regulation Block Dynamic Behavior Synchronization Capability Internally Trimmed Reference Current Source

Safety Features

• • • • • •

Overvoltage Protection: Output Overvoltage Detection Undervoltage Protection: Protection Against Open Loop Effective Zero Current Detection Accurate and Adjustable Maximum On–Time Limitation Overcurrent Protection ESD Protection on Each Pin TYPICAL APPLICATION

8 1

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MC33260P AWL YYWW 1 8


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MC33260D ALYW

1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week

PIN CONNECTIONS 23 4 * 6

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Package

Shipping

MC33260P

Plastic DIP–8

50 Units/Rail

MC33260D

SO–8

98 Units/Rail

MC33260DR2

SO–8

2500 Tape & Reel

*+& ,*-.#*,&/0,

June, 2001 – Rev. 4

8 DIP–8 P SUFFIX CASE 626

MC33260

MARKING DIAGRAMS

1

General Features

• • • • • • • • • •

http://onsemi.com

1141


MC33260 BLOCK DIAGRAM

6 * + 7 B

! C * C * *:

*

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1

6

*:

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MC33260 MAXIMUM RATINGS Pin # DIP–8

Pin # SO–8

Gate Drive Current* Source Sink

7

5

VCC Maximum Voltage

8

Rating

Symbol

Value

Unit

IO(Source) IO(Sink)

–500 500

(Vcc)max

16

V

Vin

–0.3 to +10

V

PD RθJA

600 100

mW °C/W


TJ

150

°C


TA

–40 to +105

°C

mA

6

Input Voltage Power Dissipation and Thermal Characteristics P Suffix, DIP Package Maximum Power Dissipation @ TA = 85°C Thermal Resistance Junction to Air

*The maximum package power dissipation must be observed.

ELECTRICAL CHARACTERISTICS (VCC = 13 V, TJ = 25°C for typical values, TJ = –40 to 105°C for min/max values unless otherwise noted.) Characteristic

Pin # DIP–8

Pin # SO–8

7

5

Symbol

Min

Typ

Max

ROL ROH

10 5

20 10

35 25

Unit

GATE DRIVE SECTION Gate Drive Resistor Source Resistor @ IDrive = 100 mA Sink Resistor @ IDrive = 100 mA

Ω

Gate Drive Voltage Rise Time (From 3.0 V Up to 9.0 V) (Note 1)

7

5

tr

–

50

–

ns

Output Voltage Falling Time (From 9.0 V Down to 3.0 V) (Note 1)

7

5

tf

–

50

–

ns

Maximum Oscillator Swing

3

1

∆VT

1.4

1.5

1.6

V

Charge Current @ IFB = 100 µA

3

1

Icharge

87.5

100

112.5

µA

Charge Current @ IFB = 200 µA

3

1

Icharge

350

400

450

µA

Ratio Multiplier Gain Over Maximum Swing @ IFB = 100 µA

3

1

Kosc

5600

6400

7200

1/(V.A)

Ratio Multiplier Gain Over Maximum Swing @ IFB = 200 µA

3

1

Kosc

5600

6400

7200

1/(V.A)

Average Internal Oscillator Pin Capacitance Over Oscillator Maximum Swing (CT Voltage Varying From 0 Up to 1.5 V) (Note 2)

3

1

Cint

10

15

20

pF

Discharge Time (CT = 1.0 nF)

3

1

Tdisch

–

0.5

1.0

µs

Regulation High Current Reference

1

7

Ireg–H

192

200

208

µA

Ratio (Regulation Low Current Reference)/Ireg–H

1

7

Ireg–L/Ireg–H

0.965

0.97

0.98

–

Vcontrol Impedance

1

7

ZVcontrol

–

300

–

kΩ

Feedback Pin Clamp Voltage @ IFB = 100 µA

1

7

VFB–100

1.5

2.1

2.5

V

Feedback Pin Clamp Voltage @ IFB = 200 µA

1

7

VFB–200

2.0

2.6

3.0

V

OSCILLATOR SECTION

REGULATION SECTION

NOTE: IFB is the current that is drawn by the Feedback Input pin. 1. 1.0 nF being connected between the pin 7 and ground for DIP–8, between Pin 5 and ground for SO–8. 2. Guaranteed by design.


MC33260 ELECTRICAL CHARACTERISTICS (VCC = 13 V, TJ = 25°C for typical values, TJ = –40 to 105°C for min/max values unless otherwise noted.) Pin # DIP–8

Pin # SO–8

Symbol

Min

Typ

Max

Unit

Zero Current Detection Comparator Threshold

4

2

VZCD–th

–90

–60

–30

mV

Negative Clamp Level (ICS–pin = –1.0 mA)

4

2

Cl–neg

–

–0.7

–

V

Bias Current @ Vcs = VZCD–th

4

2

Ib–cs

–0.2

–

–

µA

Propagation Delay (Vcs > VZCD–th) to Gate Drive High

7

5

TZCD

–

500

–

ns

Current Sense Pin Internal Current Source

4

2

IOCP

192

205

218

µA

τLEB

–

400

–

ns

Characteristic CURRENT SENSE SECTION

Leading Edge Blanking Duration OverCurrent Protection Propagation Delay (Vcs < VZCD–th to Gate Drive Low)

7

5

TOCP

100

160

240

ns

Synchronization Threshold DIP–8 SO–8

5 –

– 3

Vsync–th Vsync–th

0.8 0.8

1.0 1.0

1.2 1.4

V V

Negative Clamp Level (Isync = –1.0 mA)

5

3

Cl–neg

–

–0.7

–

V

Minimum Off–Time

7

5

Toff

1.5

2.1

2.7

µs

Minimum Required Synchronization Pulse Duration

5

3

Tsync

–

–

0.5

µs

OverVoltage Protection High Current Threshold and Ireg–H Difference

1

7

IOVP–H–Ireg–H

8.0

13

18

µA

OverVoltage Protection Low Current Threshold and Ireg–H Difference

1

7

IOVP–L–Ireg–H

0

–

–

–

Ratio (IOVP–H/IOVP–L)

1

7

IOVP–H/IOVP–L

1.02

–

–

–

Propagation Delay (IFB > 110% Iref to Gate Drive Low)

7

5

TOVP

–

500

–

ns

Ratio (UnderVoltage Protection Current Threshold)/Ireg–H

1

7

IUVP/Ireg–H

12

14

16

%

Propagation Delay (IFB < 12% Iref to Gate Drive Low)

7

5

TUVP

–

500

–

ns

Thermal Shutdown Threshold

7

5

Tstdwn

—

150

–

°C

Hysteresis

7

5

∆Tstdwn

–

30

–

°C

Start–Up Threshold

8

6

Vstup–th

9.7

11

12.3

V

Disable Voltage After Threshold Turn–On

8

6

Vdisable

7.4

8.5

9.6

V

8

6

ICC – –

0.1 4.0

0.25 8.0

SYNCHRONIZATION SECTION

OVERVOLTAGE PROTECTION SECTION

UNDERVOLTAGE PROTECTION SECTION

THERMAL SHUTDOWN SECTION

VCC UNDERVOLTAGE LOCKOUT SECTION

TOTAL DEVICE Power Supply Current Start–Up (VCC = 5 V with VCC Increasing) Operating @ IFB = 200 µA

Vcs is the Current Sense Pin Voltage and IFB is the Feedback Pin Current


mA

MC33260

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Pin Numbers are Relevant to the DIP–8 Version

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1

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1

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1

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1

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1

1 °

1

11

1

!1

1

" 1

1 °

"11 ! 1 !11 1 11 1 1

1

!1

1

1

1 11 !1 1 1 1 !11 !!1 !1

Figure 4. Feedback Input Voltage versus Feedback Current

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!1

Figure 3. Maximum Oscillator Swing versus Temperature

1

!1

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!11

Figure 2. Regulation Block Output versus Feedback Current

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Figure 1. Regulation Block Output versus Feedback Current

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1

1

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Figure 5. Oscillator Charge Current versus Feedback Current

Figure 6. Oscillator Charge Current versus Temperature


11

MC33260 Pin Numbers are Relevant to the DIP–8 Version !1

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11

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1

1

1

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+1°

1 °

!1

1

1

@1

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!1 !1 !1" !1!

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1

!1

1

1

1

11

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Figure 9. On–Time versus Feedback Current

Figure 10. Internal Current Sources versus Temperature

1

1 1

1

$*9 / LBM - 9 > )

Figure 25. Current Sense Block '

Overcurrent Protection

&

During the power switch conduction (i.e. when the Gate Drive pin voltage is high), a current source is applied to the pin 4. A voltage drop VOCP is then generated across the resistor ROCP that is connected between the sense resistor and the Current Sense pin (refer to Figure 25). So, instead of Vcs, the sum (Vcs + VOCP) is compared to (–60 mV) and the maximum permissible current is the solution of the following equation: * ǂR cs

OCP

+ * 60 mV

where: Ipkmax is maximum allowed current, Rcs is the sensing resistor. The overcurrent threshold is then:

&&

Ipk maxǃ ) V

+1 '

Ipk max +

K 6

ǂROCP

I

ǃ

) 60 OCP R cs

10 *3

where: ROCP is the resistor connected between the pin and the sensing resistor (Rcs), IOCP is the current supplied by the Current Sense pin when the gate drive signal is high (power switch conduction phase). IOCP equals 205 µA typically. Practically, the VOCP offset is high compared to 60 mV and the precedent equation can be simplified. The maximum current is then given by the following equation:

B * # 9 6 2 2 : 7 772 $+1 ') 26 7 > > 7

Figure 24. Current Sensing

The negative signal Vcs is applied to the current sense through a resistor ROCP. The pin is internally protected by a negative clamp (–0.7 V) that prevents substrate injection. As long as the pin 4 voltage is lower than (–60 mV), the Current Sense comparator resets the PWM latch to force the gate drive signal low state. In that condition, the power MOSFET cannot be on. During the on–time, the pin 4 information is used for the overcurrent limitation while it serves the zero current detection during the off time.

Ipk max [

R

< > k OCP < > R cs

< > 0.205 A

Consequently, the ROCP resistor can program the OCP level whatever the Rcs value is. This gives a high freedom in the choice of Rcs. In particular, the inrush resistor can be utilized.

Zero Current Detection

The Zero Current Detection function guarantees that the MOSFET cannot turn on as long as the inductor current hasn’t reached zero (discontinuous mode). http://onsemi.com 1151

MC33260 Pin Numbers are Relevant to the DIP–8 Version

7+2> 78 # '

% .

6

' +

K N

N

+

0 7

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Figure 26. PWM Latch

A LEB (Leading Edge Blanking) has been implemented. This circuitry disconnects the Current Sense comparator from pin 4 and disables it during the 400 first ns of the power switch conduction. This prevents the block from reacting on the current spikes that generally occur at power switch turn on. Consequently, proper operation does not require any filtering capacitor on pin 4.

Practically, Vpin1 that is in the range of 2.5 V, can be neglected. The equation can then be simplified: V

V

Refer to Current Sense Block.

V

OVP (Overvoltage Protection)

I

< ovpH

A

>< > V

ovpL

+V

pin1

ǒ

) Ro

I

Ǔ

ovpL

* * * / *9 *9 /

V uvp [ V

Figure 27. Internal Current Thresholds

ǒ

I

ovpH

I

< >< > A V ovpL

This function detects when the feedback current is lower than 14% of Iref. In this case, the PWM latch is reset and the power switch is kept off. This protection is useful to: • Protect the preregulator from working in too low mains conditions. • To detect the feedback current absence (in case of a nonproper connection for instance). The UVP threshold is:

) Ro

< > + R o M

UVP (Undervoltage Protection)

- 9 ;3

So, the OVP upper threshold is:

ovpL

The OVP hysteresis prevents erratic behavior. IovpL is guaranteed to be higher than IregH (refer to parameters specification). This ensures that the OVP function doesn’t interfere with the regulation one.

The feedback current (Io) is compared to a threshold current (IovpH). If it exceeds this value, the gate drive signal is maintained low until this current gets lower than a second level (IovpL).

pin1

< > + R o M

where Iovp–L is the internal low OVP current threshold. Consequently, Vpin1 being neglected:

OCP (Overcurrent Protection)

+V

ovpH

On the other hand, the OVP low threshold is:

PROTECTIONS

ovpH

=

6 6?

+1 '

V

0 7

*69

6 6 (6::

=

pin1

ǒ

< > ) R o M

Ǔ

< > I uvp A (V)

Practically (Vpin1 being neglected),

Ǔ

< > V uvp + R o M

< >< > I uvp A V

Maximum On–Time Limitation

where: Ro is the feedback resistor that is connected between pin 1 and the output voltage, Iovp–H is the internal upper OVP current threshold, Vpin1 is the pin 1 clamp voltage.

As explained in PWM Latch, the maximum on–time is accurately controlled. Pin Protection

All the pins are ESD protected.



In particular, a 11 V zener diode is internally connected between the terminal and ground on the following pins:

Feedback, Vcontrol, Oscillator, Current Sense, and Synchronization.

+

.

=

= / 7 LBM 78 2

!

!

N

!

0 7

=!

! 6 6?

Figure 28. Synchronization Arrangement SYNCHRONIZATION BLOCK

operation. The gate drive is kept in a sinking mode whenever the Undervoltage Lockout is active. The rise and fall times have been controlled to typically equal 50 ns while loaded by 1 nF.

The MC33260 features two modes of operation: • Free Running Discontinuous Mode: The power switch is turned on as soon as there is no current left in the inductor (Zero Current Detection). This mode is simply obtained by grounding the synchronization terminal (pin 5). • Synchronization Mode: This mode is set as soon as a signal crossing the 1 V threshold, is applied to the pin 5. In this case, operation in free running can only be recovered after a new circuit start–up. In this mode, the power switch cannot turn on before the two following conditions are fulfilled. – Still, the zero current must have been detected. – The precedent turn on must have been followed by (at least) one synchronization raising edge crossing the 1 V threshold. In other words, the synchronization acts to prolong the power switch off time. Consequently, a proper synchronized operation requires that the current cycle (on–time + inductor demagnetization) is shorter than the synchronization period. Practically, the inductor must be chosen accordingly. Otherwise, the system will keep working in free running discontinuous mode. Figure 33 illustrates this behavior. It must be noticed that whatever the mode is, a 2 µs minimum off–time is forced. This delay limits the switching frequency in light load conditions.

REFERENCE SECTION

An internal reference current source (Iref) is trimmed to be ±4% accurate over the temperature range (the typical value is 200 µA). Iref is the reference used for the regulation (IregH = Iref). UNDERVOLTAGE LOCKOUT SECTION

An Undervoltage Lockout comparator has been implemented to guarantee that the integrated circuit is operating only if its supply voltage (VCC) is high enough to enable a proper working. The UVLO comparator monitors the pin 8 voltage and when it exceeds 11 V, the device gets active. To prevent erratic operation as the threshold is crossed, 2.5 V of hysteresis is provided. The circuit off state consumption is very low: in the range of 100 µA @ VCC = 5 V. This consumption varies versus VCC as the circuit presents a resistive load in this mode. THERMAL SHUTDOWN

An internal thermal circuitry is provided to disable the circuit gate drive and then to prevent it from oscillating, if the junction temperature exceeds 150°C typically. The output stage is again enabled when the temperature drops below 120°C typically (30°C hysteresis).

OUTPUT SECTION

The output stage contains a totem pole optimized to minimize the cross conduction current during high speed


MC33260 Pin Numbers are Relevant to the DIP–8 Version FOLLOWER BOOST

of the follower boost: it allows the use of smaller, lighter and cheaper inductors compared to traditional systems. Finally, this technique utilization brings a drastic system cost reduction by lowering the size and then the cost of both the inductor and the power switch.

Traditional PFC preconverters provide the load with a fixed and regulated voltage that generally equals 230 V or 400 V according to the mains type (U.S., European, or universal). In the “Follower Boost” operation, the preconverter output regulation level is not fixed but varies linearly versus the ac line amplitude at a given input power.

IL

traditional preconverter follower boost preconverter

Ipk

2 6 6

$> ()

time Vin

Vin

Vin

Vout

Vin

IL

IL

2

the power switch is on

the power switch is off

Figure 30. Off–Time Duration Increase

Figure 29. Follower Boost Characteristics

This technique aims at reducing the gap between the output and the input voltages to minimize the boost efficiency degradation.

Follower Boost Implementation

In the MC33260, the on–time is differently controlled according to the feedback current level. Two areas can be defined: • When the feedback current is higher than IregL (refer to regulation section), the regulation block output (Vcontrol) is modulated to force the output voltage to a desired value. • On the other hand, when the feedback current is lower than IregL, the regulation block output and therefore, the on–time are maximum. As explained in PWM Latch Section, the on–time is then inversely proportional to the output voltage square. The Follower Boost is active in these conditions in which the on–time is simply limited by the output voltage level. Note: In this equation, the feedback pin voltage (Vpin1) is neglected compared to the output voltage (refer to the PWM Latch Section).

Follower Boost Benefits

The boost presents two phases: • The on–time during which the power switch is on. The inductor current grows up linearly according to a slope (Vin/Lp), where Vin is the instantaneous input voltage and Lp the inductor value. • The off–time during which the power switch is off. The inductor current decreases linearly according the slope (Vo – Vin)/Lp, where Vo is the output voltage. This sequence that terminates when the current equals zero, has a duration that is inversely proportional to the gap between the output and input voltages. Consequently, the off–time duration becomes longer in follower boost. Consequently, for a given peak inductor current, the longer the off time, the smaller power switch duty cycle and then its conduction dissipation. This is the first benefit of this technique: the MOSFET on–time losses are reduced. The increase of the off time duration also results in a switching frequency diminution (for a given inductor value). Given that in practise, the boost inductor is selected big enough to limit the switching frequency down to an acceptable level, one can immediately see the second benefit

t on + ǂt onǃmax +

pin3

R2 o

K osc

V2 o

C

where: Cpin3 is the total oscillator capacitor (sum of the internal and external capacitors – Cint + CT), Kosc is the ratio (oscillator swing over oscillator gain), Vo is the output voltage, Ro is the feedback resistor.



On the other hand, the boost topology has its own rule that dictates the on–time necessary to deliver the required power: t on +

4

Lp

P

6 ( 4 # 9

$)'

in

V2 pk

where: Vpk is the peak ac line voltage, Lp is the inductor value, Pin is the input power. Combining the two equations, one can obtain the Follower Boost equation: Vo +

Ro 2

B 4

Ǹ

C

K osc

pin3 Lp

P

V in

$)'C 63

pk

Consequently, a linear dependency links the output voltage to the ac line amplitude at a given input power.

/

Figure 32. Follower Boost Output Voltage $ )'C

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7 6 ( 4 # 9

Mode Selection

The operation mode is simply selected by adjusting the oscillator capacitor value. As shown in Figure 32, the output voltage first has an increasing linear characteristic versus the ac line magnitude and then is clamped down to the regulation value. In the traditional mode, the linear area must be rejected. This is achieved by dimensioning the oscillator capacitor so that the boost can deliver the maximum power while the output voltage equals its regulation level and this, whatever the given input voltage. Practically, that means that whatever the power and input voltage conditions are, the follower boost would generate output voltages values higher than the regulation level, if there was no regulation block. In other words, if (Vo)regL is the low output regulation level:

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MC33351A Smart Battery Pack with High–Side Discharge Current Sensing 7 > 7 =!

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- # $ ". The MC33340 and MC33342 are monolithic control IC’s that are specifically designed as fast charge controllers for Nickel Cadmium (NiCd) and Nickel Metal Hydride (NiMH) batteries. These devices feature negative slope voltage detection as the primary means for fast charge termination. Accurate detection is ensured by an output that momentarily interrupts the charge current for precise voltage sampling. An additional secondary backup termination method can be selected that consists of either a programmable time or temperature limit. Protective features include battery over and undervoltage detection, latched over temperature detection, and power supply input undervoltage lockout with hysteresis. Fast charge holdoff time is the only difference between the MC33340 and the MC33342. The MC33340 has a typical holdoff time of 177 seconds and the MC33342 has a typical holdoff time of 708 seconds. • Negative Slope Voltage Detection with 4.0 mV Sensitivity • Accurate Zero Current Battery Voltage Sensing • High Noise Immunity with Synchronous VFC/Logic • Programmable 1 to 4 Hour Fast Charge Time Limit • Programmable Over/Under Temperature Detection • Battery Over and Undervoltage Fast Charge Protection • Power Supply Input Undervoltage Lockout with Hysteresis • Operating Voltage Range of 3.25 V to 18 V • 177 seconds Fast Change Hold–off Time (MC33340) • 708 seconds Fast Change Hold–off Time (MC33342)

http://onsemi.com MARKING DIAGRAMS 8 PDIP–8 P SUFFIX CASE 626

8

MC3334xP AWL YYWW

1

1 8 SO–8 D SUFFIX CASE 751

8 1

3334x ALYW 1

x = 0 or 2 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week

* 6

6

PIN CONNECTIONS

.29 46

* ( J6

9

4 / 7

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=

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7 !

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Device MC33341D MC33341P

Operating Temperature Range TA = –25° to +85°C

Package SO–8 Plastic DIP



1204



ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Symbol

Value

Unit


Rating

VCC

16

V

Voltage Range Current Sense Input A (Pin 1) Current Threshold Adjust (Pin 2) Compensation (Pin 3) Voltage Sense Input (Pin 5) Current Sense Input B/Voltage Threshold Adjust (Pin 6) Drive Output (Pin 8)

VIR

–1.0 to VCC

V

ISource

50

mA

Drive Output Source Current (Pin 8)

Thermal Resistance, Junction–to–Air P Suffix, DIP Plastic Package, Case 626 D Suffix, SO–8 Plastic Package, Case 751

°C/W

RθJA

100 178

Operating Junction Temperature (Note 1)

TJ

–25 to +150

°C

Storage Temperature

Tstg

–55 to +150

°C


ELECTRICAL CHARACTERISTICS (VCC = 6.0 V, TA = 25°C, for min/max values TA is the operating junction temperature range that applies (Note 1), unless otherwise noted.)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Characteristic

Symbol

Min

Typ

Max

Unit

CURRENT SENSING (Pins 1, 2, 6)

High–Side Source and Load Sensing Pin 1 to Pin 6 (Pin 1 >1.6 V) Internally Fixed Threshold Voltage (Pin 2 = VCC) TA = 25°C TA = Tlow to Thigh Externally Adjusted Threshold Voltage (Pin 2 = 0 V) Externally Adjusted Threshold Voltage (Pin 2 = 200 mV)

Vth(I HS)

Low–Side Load Sensing Pin 1 to Pin 4 (Pin 1 = 0 V to 0.8 V) Internally Fixed Threshold Voltage (Pin 2 = VCC) TA = 25°C TA = Tlow to Thigh Externally Adjusted Threshold Voltage (Pin 2 = 0 V) Externally Adjusted Threshold Voltage (Pin 2 = 200 mV)

Vth(I LS+)

Low–Side Source Return Sensing Pin 1 to 4 (Pin 1 = 0 V to –0.2 V) Internally Fixed Threshold Voltage (Pin 2 = VCC) TA = 25°C TA = Tlow to Thigh Externally Adjusted Threshold Voltage (Pin 2 = 0 V) Externally Adjusted Threshold Voltage (Pin 2 = 200 mV)

Vth(I LS–)

mV

187 183 – –

197 – 10 180

207 211 – –

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ mV

194 192 – –

200 – 10 180

206 208 – –

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ mV

–195 –193 – –

–201 – –10 –180

–207 –209 – –

IIB(A HS)

–

40

–

µA

IIB(A LS+)

–

10

–

nA

Rin(A LS–)

–

10

–

kΩ

– –

20 100

– –

µA nA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Current Sense Input A (Pin 1) Input Bias Current, High–Side Source and Load Sensing (Pin 2 = 0 V to VPin 6 V) Input Bias Current, Low–Side Load Sensing (Pin 2 = 0 V to 0.8 V) Input Resistance, Low–Side Source Return Sensing (Pin 2 = –0.6 V to 0 V)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Current Sense Input B/Voltage Threshold Adjust (Pin 6) Input Bias Current High–Side Source and Load Current Sensing (Pin 6 > 2.0 V) Voltage Threshold Adjust (Pin 6 < 1.2 V)

IIB(B)

Current Sense Threshold Adjust (Pin 2) Input Bias Current

IIB(I th)

–

10

–

nA

gm(I)

–

6.0

–

mhos

Transconductance, Current Sensing Inputs to Drive Output

NOTE: 1. Tested ambient temperature range for the MC33341: Tlow = –25°C, Thigh = +85°C.


MC33341 ELECTRICAL CHARACTERISTICS (continued) (VCC = 6.0 V, TA = 25°C, for min/max values TA is the operating junction temperature range that applies (Note 1), unless otherwise noted.)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Characteristic

Symbol

Min

Typ

Max

Unit

Vth(I HS) Vth(I LS)

– –

≥1.7 ≤1.3

– –

1.186 1.174 – –

1.210 – 40 1.175

1.234 1.246 – –

V V mV V

DIFFERENTIAL AMPLIFIER DISABLE LOGIC (Pins 1, 6)

Logic Threshold Voltage Pin 1 (Pin 6 = 0 V) Enabled, High–Side Source and Load Current Sensing Disabled, Low–Side Load and Source Return Current Sensing

V

VOLTAGE SENSING (Pins 5, 6)

Positive Sensing Pin 5 to Pin 4 Internally Fixed Threshold Voltage TA = 25°C TA = Tlow to Thigh Externally Adjusted Threshold Voltage (Pin 6 = 0 V) Externally Adjusted Threshold Voltage (Pin 6 = 1.2 V)

Vth(V)

Voltage Sense, Input Bias Current (Pin 5)

IIB(V)

–

10

–

nA

Transconductance, Voltage Sensing Inputs to Drive Output

gm(V)

–

7.0

–

mhos

VOH

–

VCC – 0.8

–

V

ISource

15

20

–

mA

Operating Voltage Range

VCC

2.5 to 15

2.3 to 15

–

V

Power Supply Current (VCC = 6.0 V)

ICC

–

300

600

µA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DRIVE OUTPUT (Pin 8)

High State Source Voltage (ISource = 10 mA) High State Source Current (Pin 8 = 0 V)


NOTE: 1. Tested ambient temperature range for the MC33341: Tlow = –25°C, Thigh = +85°C.

PIN FUNCTION DESCRIPTION

ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Pin

Name

Description

1

Current Sense Input A

This multi–mode current sensing input can be used for either source high–side, load high–side, source–return low–side, or load low–side sensing. It is common to a Differential Amplifier, Inverting Amplifier, and a Noninverting input path. Each of these sensing paths indirectly connect to the current sense input of the Transconductance Amplifier. This input is connected to the high potential side of a current sense resistor when used in source high–side, load high–side, or load low–side current sensing modes. In source return low–side current sensing mode, this pin connects to the low potential side of a current sense resistor.

2

Current Threshold Adjust

The current sense threshold can be externally adjusted over a range of 0 V to 200 mV with respect to Pin 4, or internally fixed at 200 mV by connecting Pin 2 to VCC.

3

Compensation

This pin is connected to a high impedance node within the transconductance amplifier and is made available for loop compensation. It can also be used as an input to directly control the Drive Output. An active low at this pin will force the Drive Output into a high state.

4

Ground

This pin is the regulation control IC ground. The control threshold voltages are with respect to this pin.

5

Voltage Sense Input

This is the voltage sensing input of the Transconductance Amplifier. It is normally connected to the power supply/battery charger output through a resistor divider. The input threshold is controlled by Pin 6.

6

Current Sense Input B/ Voltage Threshold Adjust

This is a dual function input that is used for either high–side current sensing, or as a voltage threshold adjustment for Pin 5. This input is connected to the low potential side of a current sense resistor when used in source high–side or load high–side current sensing modes. In all low–side current sensing modes, Pin 6 is available as a voltage threshold adjustment for Pin 5. The threshold can be externally adjusted over a range of 0 V to 1.2 V with respect to Pin 4, or internally fixed at 1.2 V by connecting Pin 6 to VCC.

7

VCC

This is the positive supply voltage for the regulation control IC. The typical operating voltage range is 2.3 V to 15 V with respect to Pin 4.

8

Drive Output

This is a source–only output that normally connects to a linear or switching regulator control circuit. This output is capable of 15 mA, allowing it to directly drive an optoisolator in primary side control applications where galvanic isolation is required.


+1

+1

+!

1

!

1

11

!

1

1

1

1

1

1

1!

+ 1!

1

1

1

!1 1

!

1

1

!

1

11

!

1

1

+1

+

+1

+!1 +1 +!11

!1

B 1 B 1 * B 1 '# B

# B ! °

1 1 1 1

:: #' : 9 : 6 7 7+2 2 2 7 7+2

6 (7 9 C C 2 '9 2>

+!1 +!1 1

1

1

!1

! 1

!11

!1

!1

Figure 3. Closed–Loop Voltage Sensing Input versus Voltage Threshold Adjust

Figure 4. Closed–Loop Current Sense Input B versus Current Threshold Adjust

!1

! 1 1 1

1

1

!+

1

!1

-2 1

1

!1

1

!11

!1

1 !1

&%& .;,&;,;&*,.&#&$')

!% .;, /;/ #D. $)

,9 6 7 9 : 2 >+2 6

B 1 B 1 * B 1 '# # B ! °

1

+!

% #-; /;/ #D. $)

!1

1

& %& .;,&;,;&*,.&(&$')

1

1

+ 6 / 7+2 2 2 / 7+2 ! + 6 6 >+2 " + 2 >+2 #% #(*;, ;;#.; $° )

1

!11

!

+!1

Figure 2. Current Sensing Threshold Change versus Temperature

!1

"

#% #(*;, ;;#.; $° )

B 1 B 1 * B 1 '# # B ! °

!

+1

Figure 1. Voltage Sensing Threshold Change versus Temperature

1

+"1 + 1

!

& + & %&*,.&*;;, ;&#-;&$')

+! + 1

B 1

1

B 1 B 1 * B 1 '# # B ! °

-2

+1

+1

1

+!1

1

+1

1

+!11

!+P P

+!1 +!1 1

1

1

!1

1 *9 #' : !1 9 : 6 6 >+2 6 1 1 !11 !1 !1

!% .;, /;/ #D. $')

!% .;, /;/ #D. $')

Figure 5. Closed–Loop Current Sensing Input A versus Current Threshold Adjust

Figure 6. Closed–Loop Current Sensing Input A versus Current Threshold Adjust


!

& + & %&*,.&*;;, ;&#-;&$')

∆ 7$*&/)%& .;,&;,*,/;/& /#,-;&$')

1

1 1

&%& .;,&;,;&*,.&#&$')

1

B 1

&! +P & P%&*,.&*;;, ;&#-;&$')

1

&! + &%&*,.&*;;, ;&#-;&$')

& %&#-;&;,*,-&*,.&$)

∆ 7$9) %&#-;&;,*,-&/;/& /#,-;&$')

MC33341

1

7

φ%&;G ;&/#;&$°)

11

1

!1 1 1 1&4

!1

-

"1

1

B 1 B 1 B 1 4 " B 1 # B ! °

1 1 1&4

11&4

1&

1

!1 1

-

1

B 1 B 1 B 1 4 " B # B ! °

1 1&4

1 1 1&4

11&4

1&

Figure 7. Bode Plot Voltage Sensing Inputs to Drive Output

Figure 8. Bode Plot Current Sensing Inputs to Drive Output

B 1 B 1 # B ! °

1

!1

1!

1"

1

1

!1

"1

1

1

*% *; .. # .;, $'#)

1

B 1 # B ! °

+1 +1 +! +

1

1

!

B 1 B 1 # B ! °

1

1

!1

1 1

1!

1"

1

1

!1

"1

1

1

*% *; .. # .;, $'#)

Figure 10. Transconductance Current Sensing Inputs to Drive Output *

%&.H& .;,%&*;&..&0&#;&$'#)

1

11 !1

"1

Figure 9. Transconductance Voltage Sensing Inputs to Drive Output

/ %&..&. ;&#.#*,&#-;&$)

7 / 7+2

:% ;=.;, H $/8)

1

+!1 1

1

7 >+2

1

:% ;=.;, H $/8)

1

1 1

1

!1

*% .. # .;, $'#)

1 9 6 6 / 7 1 * B 1 '# # B ! °

1 1

9 6 6 >

1! 1 1

Figure 11. Drive Output High State Source Saturation versus Load Current

1

1

!

% .H #-; $)



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MC33341

MC33341 INTRODUCTION Power supplies and battery chargers require precise control of output voltage and current in order to prevent catastrophic damage to the system load. Many present day power sources contain a wide assortment of building blocks and glue devices to perform the required sensing for proper regulation. Typical feedback loop circuits may consist of a voltage and current amplifier, level shifting circuitry, summing circuitry and a reference. The MC33341 contains all of these basic functions in a manner that is easily adaptable to many of the various power source–load configurations.

current sensing modes, Pin 6 is available, and can be used to lower the regulation threshold of Pin 5. This threshold can be externally adjusted over a range of 0 V to 1.2 V with respect to the IC ground at Pin 4. Current Sensing

Current sensing is accomplished by monitoring the voltage that appears across sense resistor RS, level shifting it with respect to Pin 4 if required, and applying it to the noninverting Isen input of the transconductance amplifier. In order to allow for maximum circuit flexibility, there are three methods of current sensing, each with different internal paths. In source high–side (Figures 13 and 14) and load high–side (Figures 17 and 18) current sensing, the Differential Amplifier is active with a gain of 1.0. Pin 1 connects to the high potential side of current sense resistor RS while Pin 6 connects to the low side. Logic circuitry is provided to disable the Differential Amplifier output whenever low–side current sensing is required. This circuit clamps the Differential Amplifier output high which disconnects it from the Isen input of the Transconductance Amplifier. This happens if Pin 1 is less than 1.2 V or if Pin 1 is less than Pin 6. With source return low–side current sensing (Figures 15 and 16), the Inverting Amplifier is active with a gain of –1.0. Pin 1 connects to the low potential side of current sense resistor RS while Pin 4 connects to the high side. Note that a negative voltage appears across RS with respect to Pin 4. In load low–side current sensing (Figures 19 and 20) a Noninverting input path is active with a gain of 1.0. Pin 1 connects to the high potential side of current sense resistor RS while Pin 4 connects to the low side. The Noninverting input path lies from Pin 1, through the Inverting Amplifier input and feedback resistors R, to the cathode of the output diode. With load low–side current sensing, Pin 1 will be more positive than Pin 4, forcing the Inverting Amplifier output low. This causes the diode to be reverse biased, thus preventing the output stage of the amplifier from loading the input signal that is flowing through the feedback resistors. The regulation threshold in all of the current sensing modes is internally fixed at 200 mV with Pin 2 connected to VCC. Pin 2 can be used to externally adjust the threshold over a range of 0 to 200 mV with respect to the IC ground at Pin 4.

OPERATING DESCRIPTION The MC33341 is an analog regulation control circuit that is specifically designed to simultaneously close the voltage and current feedback loops in power supply and battery charger applications. This device can control the feedback loop in either constant–voltage or constant–current mode with automatic crossover. A concise description of the integrated circuit blocks is given below. Refer to the block diagram in Figure 13. Transconductance Amplifier

A quad input transconductance amplifier is used to control the feedback loop. This amplifier has separate voltage and current channels, each with a sense and a threshold input. Within a given channel, if the sense input level exceeds that of the threshold input, the amplifier output is driven high. The channel with the largest difference between the sense and threshold inputs will set the output source current of the amplifier and thus dominate control of the feedback loop. The amplifier output appears at Pin 8 and is a source–only type that is capable of 15 mA. A high impedance node within the transconductance amplifier is made available at Pin 3 for loop compensation. This pin can sink and source up to 10 µA of current. System stability is achieved by connecting a capacitor from Pin 3 to ground. The Compensation Pin signal is out of phase with respect to the Drive Output. By actively clamping Pin 3 low, the Drive Output is forced into a high state. This, in effect, will shutdown the power supply or battery charger, by forcing the output voltage and current regulation threshold down towards zero. Voltage Sensing

Reference

The voltage that appears across the load is monitored by the noninverting Vsen input of the transconductance amplifier. This voltage is resistively scaled down and connected to Pin 5. The threshold at which voltage regulation occurs is set by the level present at the inverting Vth input of the transconductance amplifier. This level is controlled by Pin 6. In source high–side and load high–side current sensing modes, Pin 6 must be connected to the low potential side of current sense resistor RS. Under these conditions, the voltage regulation threshold is internally fixed at 1.2 V. In source return low–side and load low–side

An internal band gap reference is used to set the 1.2 V voltage threshold and 200 mV current threshold. The reference is initially trimmed to a ±1.0% tolerance at TA = 25°C and is guaranteed to be within ±2.0% over an ambient operating temperature range of –25° to 85°C. Applications

Each of the application circuits illustrate the flexibility of this device. The circuits shown in Figures 13 through 20 contain an optoisolator connected from the Drive Output at


MC33341 drop across RS could exceed 1.6 V. Depending upon the current sensing configuration used, this will result in forward biasing of either the internal VCC clamp diode, Pin 6, or the device substrate, Pin 1. Under these conditions, input series resistor R3 is required. The peak input current should be limited to 20 mA. Excessively large values for R3 will degrade the current sensing accuracy. Figure 21 shows a method of bounding the voltage drop across RS without sacrificing current sensing accuracy.

Pin 8 to ground. This configuration is shown for ease of understanding and would normally be used to provide an isolated control signal to a primary side switching regulator controller. In non–isolated, primary or secondary side applications, a load resistor can be placed from Pin 8 to ground. This resistor will convert the Drive Output current to a voltage for direct control of a regulator. In applications where excessively high peak currents are possible from the source or load, the load induced voltage

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The above figure shows the MC33341 configured for source high–side current sensing allowing a common ground path between Load – and Source Return –. The Differential Amplifier inputs, Pins 1 and 6, are used to sense the load induced voltage drop that appears across resistor RS. The internal voltage and current regulation thresholds are selected by the respective external connections of Pins 2 and 6. Resistor R3 is required in applications where a high peak level of reverse current is possible if the source inputs are shorted. The resistor value should be chosen to limit the input current of the internal VCC clamp diode to less than 20 mA. Excessively large values for R3 will degrade the current sensing accuracy. +

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The above figure shows the MC33341 configured for source high–side current sensing with an externally adjustable current threshold. Operation of this circuit is similar to that of Figure 13. The current regulation threshold can be adjusted over a range of 0 V to 200 mV with respect to Pin 4. +

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The above figure shows the MC33341 configured for source return low–side current sensing allowing a common power path between Source + and Load +. This configuration is especially suited for negative output applications where a common ground path, Source + to Load +, is desired. The Inverting Amplifier inputs, Pins 1 and 4, are used to sense the load induced voltage drop that appears across resistor RS. The internal voltage and current regulation thresholds are selected by the respective external connections of Pins 2 and 6. Resistor R3 is required in applications where high peak levels of inrush current are possible. The resistor value should be chosen to limit the negative substrate current to less than 20 mA. Excessively large values for R3 will degrade the current sensing accuracy.

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The above figure shows the MC33341 configured for source return low–side current sensing with externally adjustable voltage and current thresholds. Operation of this circuit is similar to that of Figure 15. The respective voltage and current regulation threshold can be adjusted over a range of 0 to 1.6 V and 0 V to 200 mV with respect to Pin 4. +

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Figure 16. Source Return Low–Side Current Sensing with Externally Adjustable Current and Voltage Thresholds


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The above figure shows the MC33341 configured for load high–side current sensing allowing common paths for both power and ground, between the source and load. The Differential Amplifier inputs, Pins 1 and 6, are used to sense the load induced voltage drop that appears across resistor RS. The internal voltage and current regulation thresholds are selected by the respective external connections of Pins 2 and 6. Resistor R3 is required in applications where high peak levels of load current are possible from the battery or load bypass capacitor. The resistor value should be chosen to limit the input current of the internal VCC clamp diode to less than 20 mA. Excessively large values for R3 ill degrade the current sensing accuracy. +

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Figure 17. Load High–Side Current Sensing with Internally Fixed Current and Voltage Thresholds


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The above figure shows the MC33341 configured for load high–side current sensing with an externally adjustable current threshold. Operation of this circuit is similar to that of Figure 17. The current regulation threshold can be adjusted over a range of 0 V to 200 mV with respect to Pin 4. +

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Figure 18. Load High–Side Current Sensing with Externally Adjustable Current and Internally Fixed Voltage Thresholds


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The above figure shows the MC33341 configured for load low–side current sensing allowing common paths for both power and ground, between the source and load. The Noninverting input paths, Pins 1 and 4, are used to sense the load induced voltage drop that appears across resistor RS. The internal voltage and current regulation thresholds are selected by the respective external connections of Pins 2 and 6. Resistor R3 is required in applications where high peak levels of load current are possible from the battery or load bypass capacitor. The resistor value should be chosen to limit the negative substratecurrent to less than 20 mA. Excessively large values for R3 will degrade the current sensing accuracy. +

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The above figure shows the MC33341 configured for load low–side current sensing with an externally adjustable voltage and current threshold. Operation of this circuit is similar to that of Figure 19. The respective voltage and current regulation threshold can be adjusted over a range of 0 to 1.2 V and 0 V to 200 mV, with respect to Pin 4. +

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NOTE: An excessive load induced voltage across RS can occur if either the source input or load output is shorted. This voltage can easily be bounded with the addition of the diodes shown without degrading the current sensing accuracy. This bounding technique can be used in any of the MC33341 applications where high peak currents are anticipated.

Figure 21. Current Sense Resistor Bounding

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Figure 22. Multiple Output Current and Voltage Regulation


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Figure 1. Block Diagram and Typical Application

ABSOLUTE MAXIMUM RATINGS (Absolute Maximum Ratings indicate limits beyond which damage to the device may occur). Symbol

Value

Unit

Maximum Supply Voltage

Vin

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ON/OFF Pin Input Voltage

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Minimum ESD Rating (Human Body Model: C = 100 pF, R = 1.5 kΩ)



LM2574 OPERATING RATINGS (Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics). Rating

Symbol

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TJ

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SYSTEM PARAMETERS ([Note 1] Test Circuit Figure 16) ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Vin = 12 V for the 3.3 V, 5.0 V, and Adjustable version, Vin = 25 V for the 12 V version, Vin = 30 V for the 15 V version. ILoad = 100 mA. For typical values TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies [Note 2], unless otherwise noted). Symbol

Min

Typ

Max

Unit

Output Voltage (Vin = 12 V, ILoad = 100 mA, TJ = 25°C)

Vout

3.234

3.3

3.366

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Feedback Voltage Vin = 12 V, ILoad = 100 mA, Vout = 5.0 V, TJ = 25°C

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Feedback Voltage 7.0 V ≤ Vin ≤ 40 V, 0.1 A ≤ ILoad ≤ 0.5 A, Vout = 5.0 V TJ = 25°C TJ = –40 to +125°C

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Characteristic LM2574–3.3 ([Note 1] Test Circuit Figure 16)

Efficiency (Vin = 12 V, ILoad = 0.5 A)

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LM2574–5 ([Note 1] Test Circuit Figure 16)


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LM2574 ADJUSTABLE VERSION ([Note 1] Test Circuit Figure 16)

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1. External components such as the catch diode, inductor, input and output capacitors can affect the switching regulator system performance. When the LM2574 is used as shown in the Figure 16 test circuit, the system performance will be as shown in the system parameters section of the Electrical Characteristics. 2. Tested junction temperature range for the LM2574: Tlow = –40°C Thigh = +125°C.


LM2574 SYSTEM PARAMETERS ([Note 1] Test Circuit Figure 16) ELECTRICAL CHARACTERISTICS (continued) (Unless otherwise specified, Vin = 12 V for the 3.3 V, 5.0 V, and Adjustable version, Vin = 25 V for the 12 V version, Vin = 30 V for the 15 V version. ILoad = 100 mA. For typical values TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies [Note 2], unless otherwise noted). Characteristic

Symbol

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Typ

Max

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98

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ALL OUTPUT VOLTAGE VERSIONS Feedback Bias Current Vout = 5.0 V (Adjustable Version Only) TJ = 25°C TJ = –40 to +125°C

Ib

Oscillator Frequency (Note 3) TJ = 25°C TJ = 0 to +125°C TJ = –40 to +125°C

fO

Saturation Voltage (Iout = 0.5 A, [Note 4]) TJ = 25°C TJ = –40 to +125°C

Vsat

Max Duty Cycle (“on”) (Note 5)

DC

Current Limit Peak Current (Notes 3 and 4) TJ = 25°C TJ = –40 to +125°C

ICL

Output Leakage Current (Notes 6 and 7), TJ = 25°C Output = 0 V Output = – 1.0 V

IL

Quiescent Current (Note 6) TJ = 25°C TJ = –40 to +125°C

IQ

Standby Quiescent Current (ON/OFF Pin = 5.0 V (“off”)) TJ = 25°C TJ = –40 to +125°C

nA

kHz

V

A

mA

mA

µA

Istby

ON/OFF Pin Logic Input Level Vout = 0 V TJ = 25°C TJ = –40 to +125°C Nominal Output Voltage TJ = 25°C TJ = –40 to +125°C

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ON/OFF Pin Input Current ON/OFF Pin = 5.0 V (“off”), TJ = 25°C ON/OFF Pin = 0 V (“on”), TJ = 25°C

IIH IIL

1. External components such as the catch diode, inductor, input and output capacitors can affect the switching regulator system performance. When the LM2574 is used as shown in the Figure 16 test circuit, the system performance will be as shown in the system parameters section of the Electrical Characteristics. 2. Tested junction temperature range for the LM2574: Tlow = –40°C Thigh = +125°C. 3. The oscillator frequency reduces to approximately 18 kHz in the event of an output short or an overload which causes the regulated output voltage to drop approximately 40% from the nominal output voltage. This self protection feature lowers the average power dissipation of the IC by lowering the minimum duty cycle from 5% down to approximately 2%. 4. Output (Pin 2) sourcing current. No diode, inductor or capacitor connected to the output pin. 5. Feedback (Pin 4) removed from output and connected to 0 V. 6. Feedback (Pin 4) removed from output and connected to 12 V for the Adjustable, 3.3 V, and 5.0 V versions, and 25 V for the 12 V and 15 V versions, to force the output transistor OFF. 7. Vin = 40 V.


LM2574 TYPICAL PERFORMANCE CHARACTERISTICS (Circuit of Figure 16) $" ! ?A&&A,;:A*-;:AE

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LM2574 TYPICAL PERFORMANCE CHARACTERISTICS (Circuit of Figure 16) (continued) $#

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Figure 10. Minimum Operating Voltage

Figure 11. Feedback Pin Current

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A: Output Pin Voltage, 10 V/DIV. B: Inductor Current, 0.2 A/DIV. C: Output Ripple Voltage, 20 mV/DIV, AC–Coupled

Figure 12. Continuous Mode Switching Waveforms Vout = 5.0 V, 500 mA Load Current, L = 330 µH

Figure 13. Discontinuous Mode Switching Waveforms Vout = 5.0 V, 100 mA Load Current, L = 100 µH


LM2574 TYPICAL PERFORMANCE CHARACTERISTICS (Circuit of Figure 16) (continued)

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A: Output Voltage, 50 mV/DIV, AC Coupled B: 100 mA to 500 mA Load Pulse

A: Output Voltage, 50 mV/DIV, AC Coupled B: 50 mA to 250 mA Load Pulse

Figure 14. 500 mA Load Transient Response for Continuous Mode Operation, L = 330 µH, Cout = 300 µF

Figure 15. 250 mA Load Transient Response for Discontinuous Mode Operation, L = 68 µH, Cout = 470 µF


LM2574 Fixed Output Voltage Versions /(01

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Figure 16. Test Circuit and Layout Guidelines

PCB LAYOUT GUIDELINES On the other hand, the PCB area connected to the Pin 7 (emitter of the internal switch) of the LM2574 should be kept to a minimum in order to minimize coupling to sensitive circuitry. Another sensitive part of the circuit is the feedback. It is important to keep the sensitive feedback wiring short. To assure this, physically locate the programming resistors near to the regulator, when using the adjustable version of the LM2574 regulator.

As in any switching regulator, the layout of the printed circuit board is very important. Rapidly switching currents associated with wiring inductance, stray capacitance and parasitic inductance of the printed circuit board traces can generate voltage transients which can generate electromagnetic interferences (EMI) and affect the desired operation. As indicated in the Figure 16, to minimize inductance and ground loops, the length of the leads indicated by heavy lines should be kept as short as possible. For best results, single–point grounding (as indicated) or ground plane construction should be used.


LM2574 PIN FUNCTION DESCRIPTION Pin SO–16W

PDIP–8

Symbol

12

5

Vin

14

7

Output

4

2

Sig Gnd

Circuit signal ground pin. See the information about the printed circuit board layout.

6

4

Pwr Gnd

Circuit power ground pin. See the information about the printed circuit board layout.

3

1

Feedback

This pin senses regulated output voltage to complete the feedback loop. The signal is divided by the internal resistor divider network R2, R1 and applied to the non–inverting input of the internal error amplifier. In the Adjustable version of the LM2574 switching regulator, this pin is the direct input of the error amplifier and the resistor network R2, R1 is connected externally to allow programming of the output voltage.

5

3

ON/OFF

Description (Refer to Figure 1) This pin is the positive input supply for the LM2574 step–down switching regulator. In order to minimize voltage transients and to supply the switching currents needed by the regulator, a suitable input bypass capacitor must be present (Cin in Figure 1). This is the emitter of the internal switch. The saturation voltage Vsat of this output switch is typically 1.0 V. It should be kept in mind that the PCB area connected to this pin should be kept to a minimum in order to minimize coupling to sensitive circuitry.

It allows the switching regulator circuit to be shut down using logic level signals, thus dropping the total input supply current to approximately 80 µA. The input threshold voltage is typically 1.5 V. Applying a voltage above this value (up to +Vin) shuts the regulator off. If the voltage applied to this pin is lower than 1.5 V or if this pin is left open, the regulator will be in the “on” condition.

DESIGN PROCEDURE Buck Converter Basics

current loop. This removes the stored energy from the inductor. The inductor current during this time is:

The LM2574 is a “Buck” or Step–Down Converter which is the most elementary forward–mode converter. Its basic schematic can be seen in Figure 17. The operation of this regulator topology has two distinct time periods. The first one occurs when the series switch is on, the input voltage is connected to the input of the inductor. The output of the inductor is the output voltage, and the rectifier (or catch diode) is reverse biased. During this period, since there is a constant voltage source connected across the inductor, the inductor current begins to linearly ramp upwards, as described by the following equation: I

L(on)

+

I

For the buck converter with ideal components, the duty cycle can also be described as: V d + out V in

L

Figure 18 shows the buck converter idealized waveforms of the catch diode voltage and the inductor current. I

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) A'!(

,

)

L

t d + on , where T is the period of switching. T

During this “on” period, energy is stored within the core material in the form of magnetic flux. If the inductor is properly designed, there is sufficient energy stored to carry the requirements of the load during the “off” period.

ǒVout – VDǓ toff

This period ends when the power switch is once again turned on. Regulation of the converter is accomplished by varying the duty cycle of the power switch. It is possible to describe the duty cycle as follows:

ǒVin – VoutǓ ton

!04

L(off)

+

2,(

!04 77 )I)

!04

!04 77

!04 5

+ 0!A* !

Figure 17. Basic Buck Converter

The next period is the “off” period of the power switch. When the power switch turns off, the voltage across the inductor reverses its polarity and is clamped at one diode voltage drop below ground by the catch diode. Current now flows through the catch diode thus maintaining the load

+1 +5 )

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+,(; !04 5

Figure 18. Buck Converter Idealized Waveforms http://onsemi.com 1286

LM2574 Procedure (Fixed Output Voltage Version) In order to simplify the switching regulator design, a step–by–step design procedure and example is provided. Procedure

Example

Given Parameters: Vout = Regulated Output Voltage (3.3 V, 5.0 V, 12 V or 15 V) Vin(max) = Maximum Input Voltage ILoad(max) = Maximum Load Current

Given Parameters: Vout = 5.0 V Vin(max) = 15 V ILoad(max) = 0.4 A

1. Controller IC Selection According to the required input voltage, output voltage and current, select the appropriate type of the controller IC output voltage version.

1. Controller IC Selection According to the required input voltage, output voltage, current polarity and current value, use the LM2574–5 controller IC.

2. Input Capacitor Selection (Cin) To prevent large voltage transients from appearing at the input and for stable operation of the converter, an aluminium or tantalum electrolytic bypass capacitor is needed between the input pin +Vin and ground pin Gnd. This capacitor should be located close to the IC using short leads. This capacitor should have a low ESR (Equivalent Series Resistance) value.

2. Input Capacitor Selection (Cin) A 22 µF, 25 V aluminium electrolytic capacitor located near to the input and ground pins provides sufficient bypassing.

3. Catch Diode Selection (D1) A. Since the diode maximum peak current exceeds the regulator maximum load current, the catch diode current rating must be at least 1.2 times greater than the maximum load current. For a robust design the diode should have a current rating equal to the maximum current limit of the LM2574 to be able to withstand a continuous output short. B. The reverse voltage rating of the diode should be at least 1.25 times the maximum input voltage.

3. Catch Diode Selection (D1) A. For this example the current rating of the diode is 1.0 A.

4. Inductor Selection (L1) A. According to the required working conditions, select the correct inductor value using the selection guide from Figures 19 to 23. B. From the appropriate inductor selection guide, identify the inductance region intersected by the Maximum Input Voltage line and the Maximum Load Current line. Each region is identified by an inductance value and an inductor code. C. Select an appropriate inductor from the several different manufacturers part numbers listed in Table 2. The designer must realize that the inductor current rating must be higher than the maximum peak current flowing through the inductor. This maximum peak current can be calculated as follows:

I p(max) + I Load(max) )

B. Use a 20 V 1N5817 Schottky diode, or any of the suggested fast recovery diodes shown in Table 1. 4. Inductor Selection (L1) A. Use the inductor selection guide shown in Figure 20.

B. From the selection guide, the inductance area intersected by the 15 V line and 0.4 A line is 330. C. Inductor value required is 330 µH. From Table 2, choose an inductor from any of the listed manufacturers.

ǒV in * V outǓton 2L

where ton is the “on” time of the power switch and

V t on + out x 1.0 V in f osc For additional information about the inductor, see the inductor section in the “EXTERNAL COMPONENTS” section of this data sheet.


LM2574 Procedure (Fixed Output Voltage Version) (continued) In order to simplify the switching regulator design, a step–by–step design procedure and example is provided. Procedure

Example

5. Output Capacitor Selection (Cout) A. Since the LM2574 is a forward–mode switching regulator with voltage mode control, its open loop 2–pole–1–zero frequency characteristic has the dominant pole–pair determined by the output capacitor and inductor values. For stable operation and an acceptable ripple voltage, (approximately 1% of the output voltage) a value between 100 µF and 470 µF is recommended. B. Due to the fact that the higher voltage electrolytic capacitors generally have lower ESR (Equivalent Series Resistance) numbers, the output capacitor’s voltage rating should be at least 1.5 times greater than the output voltage. For a 5.0 V regulator, a rating at least 8.0 V is appropriate, and a 10 V or 16 V rating is recommended.

5. Output Capacitor Selection (Cout) A. Cout = 100 µF to 470 µF standard aluminium electrolytic.

B. Capacitor voltage rating = 20 V.

Procedure (Adjustable Output Version: LM2574–ADJ) Procedure

Example

Given Parameters: Vout = Regulated Output Voltage Vin(max) = Maximum DC Input Voltage ILoad(max) = Maximum Load Current

Given Parameters: Vout = 24 V Vin(max) = 40 V ILoad(max) = 0.4 A

1. Programming Output Voltage To select the right programming resistor R1 and R2 value (see Figure 2) use the following formula:

1. Programming Output Voltage (selecting R1 and R2) Select R1 and R2 :

ǒ

Ǔ

R2 1.0 ) V out + V ref R1

where Vref = 1.23 V

ǒ

Resistor R1 can be between 1.0 kΩ and 5.0 kΩ. (For best temperature coefficient and stability with time, use 1% metal film resistors).

ǒ

R2 + R1

V out V

ref

ǒ

Vout = 1.23 1.0 )

R2 + R1

Ǔ

V out V

ref

Ǔ

R2 R1

Ǔ

* 1.0

Select R1 = 1.0 kΩ

+ 1.0 k

10 V ǒ1.23 * 1.0Ǔ V

R2 = 18.51 kΩ, choose a 18.7 kΩ metal film resistor.

* 1.0

2. Input Capacitor Selection (Cin) To prevent large voltage transients from appearing at the input and for stable operation of the converter, an aluminium or tantalum electrolytic bypass capacitor is needed between the input pin +Vin and ground pin Gnd. This capacitor should be located close to the IC using short leads. This capacitor should have a low ESR (Equivalent Series Resistance) value. For additional information see input capacitor section in the “EXTERNAL COMPONENTS” section of this data sheet.

2. Input Capacitor Selection (Cin) A 22 µF aluminium electrolytic capacitor located near the input and ground pin provides sufficient bypassing.

3. Catch Diode Selection (D1) A. Since the diode maximum peak current exceeds the regulator maximum load current the catch diode current rating must be at least 1.2 times greater than the maximum load current. For a robust design, the diode should have a current rating equal to the maximum current limit of the LM2574 to be able to withstand a continuous output short. B. The reverse voltage rating of the diode should be at least 1.25 times the maximum input voltage.

3. Catch Diode Selection (D1) A. For this example, a 1.0 A current rating is adequate.

B. Use a 50 V MBR150 Schottky diode or any suggested fast recovery diodes in Table 1.


LM2574 Procedure (Adjustable Output Version: LM2574–ADJ) Procedure

Example

4. Inductor Selection (L1) A. Use the following formula to calculate the inductor Volt x microsecond [V x µs] constant:

4. Inductor Selection (L1) A. Calculate E x T ƪV x sƫ constant : E x T + (40 * 24) x 24 x 1000 + 105ƪV x sƫ 52 40

V out

6 E x T + (V * V out) x 10 ƪV x sƫ in V F[Hz] in B. Match the calculated E x T value with the corresponding number on the vertical axis of the Inductor Value Selection Guide shown in Figure 23. This E x T constant is a measure of the energy handling capability of an inductor and is dependent upon the type of core, the core area, the number of turns, and the duty cycle. C. Next step is to identify the inductance region intersected by the E x T value and the maximum load current value on the horizontal axis shown in Figure 27. D. From the inductor code, identify the inductor value. Then select an appropriate inductor from Table 2. The inductor chosen must be rated for a switching frequency of 52 kHz and for a current rating of 1.15 x ILoad. The inductor current rating can also be determined by calculating the inductor peak current:

I p(max) + I Load(max) )

B. E x T + 185ƪV x sƫ

C. ILoad(max) = 0.4 A Inductance Region = 1000 D. Proper inductor value = 1000 µH Choose the inductor from Table 2.

ǒV in * V outǓton 2L

where ton is the “on” time of the power switch and

V t on + out x 1.0 V in f osc For additional information about the inductor, see the inductor section in the “External Components” section of this data sheet. 5. Output Capacitor Selection (Cout) A. Since the LM2574 is a forward–mode switching regulator with voltage mode control, its open loop 2–pole–1–zero frequency characteristic has the dominant pole–pair determined by the output capacitor and inductor values. For stable operation, the capacitor must satisfy the following requirement: V in (max) ƪFƫ C out w 13, 300 V out x LƪHƫ

5. Output Capacitor Selection (Cout) A. 40 C out w 13, 300 x + 22.2 F 24 x 1000 To achieve an acceptable ripple voltage, select Cout = 100 µF electrolytic capacitor.

B. Capacitor values between 10 µF and 2000 µF will satisfy the loop requirements for stable operation. To achieve an acceptable output ripple voltage and transient response, the output capacitor may need to be several times larger than the above formula yields. C. Due to the fact that the higher voltage electrolytic capacitors generally have lower ESR (Equivalent Series Resistance) numbers, the output capacitor’s voltage rating should be at least 1.5 times greater than the output voltage. For a 5.0 V regulator, a rating of at least 8.0 V is appropriate, and a 10 V or 16V rating is recommended.


LM2574 LM2574 Series Buck Regulator Design Procedures (continued)

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Figure 20. LM2574–5

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Indicator Value Selection Guide (For Continuous Mode Operation)

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LM2574 Table 1. Diode Selection Guide gives an overview about through–hole diodes for an effective design. Device listed in bold are available from ON Semiconductor 1.0 Amp Diodes VR

Schottky

20 V

1N5817 MBR120P

30 V

1N5818 MBR130P

40 V

1N5819 MBR140P

50 V

MBR150

60 V

MBR160

Fast Recovery

MUR110 (rated to 100 V)

Table 2. Inductor Selection Guide Inductor Value

Pulse Engineering

Tech 39

Renco

NPI

68 µH

*

55 258 SN

RL–1284–68

NP5915

100 µH

*

55 308 SN

RL–1284–100

NP5916

150 µH

52625

55 356 SN

RL–1284–150

NP5917

220 µH

52626

55 406 SN

RL–1284–220

NP5918/5919

330 µH

52627

55 454 SN

RL–1284–330

NP5920/5921

470 µH

52628

*

RL–1284–470

NP5922

680 µH

52629

55 504 SN

RL–1284–680

NP5923

1000 µH

52631

55 554 SN

RL–1284–1000

*

1500 µH

*

*

RL–1284–1500

*

2200 µH

*

*

RL–1284–2200

*

* : Contact Manufacturer

Table 3. Example of Several Inductor Manufacturers Phone/Fax Numbers Pulse Engineering Inc.

Phone Fax

+ 1–619–674–8100 + 1–619–674–8262

Pulse Engineering Inc. Europe

Phone Fax

+ 353–9324–107 + 353–9324–459

Renco Electronics Inc.

Phone Fax

+ 1–516–645–5828 + 1–516–586–5562

Tech 39

Phone Fax

+ 33–1–4115–1681 + 33–1–4709–5051

NPI/APC

Phone Fax

+ 44–634–290–588


LM2574 EXTERNAL COMPONENTS Input Capacitor (Cin) The Input Capacitor Should Have a Low ESR

voltage ratings may be needed to provide low ESR values, that are required for low output ripple voltage.

For stable operation of the switch mode converter a low ESR (Equivalent Series Resistance) aluminium or solid tantalum bypass capacitor is needed between the input pin and the ground pin, to prevent large voltage transients from appearing at the input. It must be located near the regulator and use short leads. With most electrolytic capacitors, the capacitance value decreases and the ESR increases with lower temperatures. For reliable operation in temperatures below –25°C larger values of the input capacitor may be needed. Also paralleling a ceramic or solid tantalum capacitor will increase the regulator stability at cold temperatures.

The Output Capacitor Requires an ESR Value that has an Upper and Lower Limit

As mentioned above, a low ESR value is needed for low output ripple voltage, typically 1% to 2% of the output voltage. But if the selected capacitor’s ESR is extremely low (below 0.03 Ω), there is a possibility of an unstable feedback loop, resulting in oscillation at the output. This situation can occur when a tantalum capacitor, that can have a very low ESR, is used as the only output capacitor. At Low Temperatures, Put in Parallel Aluminium Electrolytic Capacitors with Tantalum Capacitors

Electrolytic capacitors are not recommended for temperatures below –25°C. The ESR rises dramatically at cold temperatures and typically rises 3 times at –25°C and as much as 10 times at –40°C. Solid tantalum capacitors have much better ESR spec at cold temperatures and are recommended for temperatures below –25°C. They can be also used in parallel with aluminium electrolytics. The value of the tantalum capacitor should be about 10% or 20% of the total capacitance. The output capacitor should have at least 50% higher RMS ripple current rating at 52 kHz than the peak–to–peak inductor ripple current.

RMS Current Rating of Cin

The important parameter of the input capacitor is the RMS current rating. Capacitors that are physically large and have large surface area will typically have higher RMS current ratings. For a given capacitor value, a higher voltage electrolytic capacitor will be physically larger than a lower voltage capacitor, and thus be able to dissipate more heat to the surrounding air, and therefore will have a higher RMS current rating. The consequences of operating an electrolytic capacitor beyond the RMS current rating is a shortened operating life. In order to assure maximum capacitor operating lifetime, the capacitor’s RMS ripple current rating should be: I rms u 1.2 x d x I

Catch Diode Locate the Catch Diode Close to the LM2574

The LM2574 is a step–down buck converter, it requires a fast diode to provide a return path for the inductor current when the switch turns off. This diode must be located close to the LM2574 using short leads and short printed circuit traces to avoid EMI problems.

Load

where d is the duty cycle, for a continuous mode buck regulator V t d + on + out V T in

and

|V out| t d + on + |V out| ) V T

Use a Schottky or a Soft Switching Ultra–Fast Recovery Diode

for a buck–boost regulator.

Since the rectifier diodes are very significant source of losses within switching power supplies, choosing the rectifier that best fits into the converter design is an important process. Schottky diodes provide the best performance because of their fast switching speed and low forward voltage drop. They provide the best efficiency especially in low output voltage applications (5.0 V and lower). Another choice could be Fast–Recovery, or Ultra–Fast Recovery diodes. It has to be noted, that some types of these diodes with an abrupt turnoff characteristic may cause instability or EMI troubles. A fast–recovery diode with soft recovery characteristics can better fulfill some quality, low noise design requirements. Table 1 provides a list of suitable diodes for the LM2574 regulator. Standard 50/60 Hz rectifier diodes, such as the 1N4001 series or 1N5400 series are NOT suitable.

in

Output Capacitor (Cout)

For low output ripple voltage and good stability, low ESR output capacitors are recommended. An output capacitor has two main functions: it filters the output and provides regulator loop stability. The ESR of the output capacitor and the peak–to–peak value of the inductor ripple current are the main factors contributing to the output ripple voltage value. Standard aluminium electrolytics could be adequate for some applications but for quality design, low ESR types are recommended. An aluminium electrolytic capacitor’s ESR value is related to many factors, such as the capacitance value, the voltage rating, the physical size and the type of construction. In most cases, the higher voltage electrolytic capacitors have lower ESR value. Often capacitors with much higher


LM2574 Inductor

current increases. This discontinuous mode of operation is perfectly acceptable for this type of switching converter. Any buck regulator will be forced to enter discontinuous mode if the load current is light enough.

The magnetic components are the cornerstone of all switching power supply designs. The style of the core and the winding technique used in the magnetic component’s design have a great influence on the reliability of the overall power supply. Using an improper or poorly designed inductor can cause high voltage spikes generated by the rate of transitions in current within the switching power supply, and the possibility of core saturation can arise during an abnormal operational mode. Voltage spikes can cause the semiconductors to enter avalanche breakdown and the part can instantly fail if enough energy is applied. It can also cause significant RFI (Radio Frequency Interference) and EMI (Electro–Magnetic Interference) problems.

Selecting the Right Inductor Style

Some important considerations when selecting a core type are core material, cost, the output power of the power supply, the physical volume the inductor must fit within, and the amount of EMI (Electro–Magnetic Interference) shielding that the core must provide. There are many different styles of inductors available, such as pot core, E–core, toroid and bobbin core, as well as different core materials such as ferrites and powdered iron from different manufacturers. For high quality design regulators the toroid core seems to be the best choice. Since the magnetic flux is contained within the core, it generates less EMI, reducing noise problems in sensitive circuits. The least expensive is the bobbin core type, which consists of wire wound on a ferrite rod core. This type of inductor generates more EMI due to the fact that its core is open, and the magnetic flux is not contained within the core. When multiple switching regulators are located on the same printed circuit board, open core magnetics can cause interference between two or more of the regulator circuits, especially at high currents due to mutual coupling. A toroid, pot core or E–core (closed magnetic structure) should be used in such applications.

Continuous and Discontinuous Mode of Operation

The LM2574 step–down converter can operate in both the continuous and the discontinuous modes of operation. The regulator works in the continuous mode when loads are relatively heavy, the current flows through the inductor continuously and never falls to zero. Under light load conditions, the circuit will be forced to the discontinuous mode when inductor current falls to zero for certain period of time (see Figure 24 and Figure 25). Each mode has distinctively different operating characteristics, which can affect the regulator performance and requirements. In many cases the preferred mode of operation is the continuous mode. It offers greater output power, lower peak currents in the switch, inductor and diode, and can have a lower output ripple voltage. On the other hand it does require larger inductor values to keep the inductor current flowing continuously, especially at low output load currents and/or high input voltages. To simplify the inductor selection process, an inductor selection guide for the LM2574 regulator was added to this data sheet (Figures 19 through 23). This guide assumes that the regulator is operating in the continuous mode, and selects an inductor that will allow a peak–to–peak inductor ripple current to be a certain percentage of the maximum design load current. This percentage is allowed to change as different design load currents are selected. For light loads (less than approximately 0.2 A) it may be desirable to operate the regulator in the discontinuous mode, because the inductor value and size can be kept relatively low. Consequently, the percentage of inductor peak–to–peak

Do Not Operate an Inductor Beyond its Maximum Rated Current

Exceeding an inductor’s maximum current rating may cause the inductor to overheat because of the copper wire losses, or the core may saturate. Core saturation occurs when the flux density is too high and consequently the cross sectional area of the core can no longer support additional lines of magnetic flux. This causes the permeability of the core to drop, the inductance value decreases rapidly and the inductor begins to look mainly resistive. It has only the dc resistance of the winding. This can cause the switch current to rise very rapidly and force the LM2574 internal switch into cycle–by–cycle current limit, thus reducing the dc output load current. This can also result in overheating of the inductor and/or the LM2574. Different inductor types have different saturation characteristics, and this should be kept in mind when selecting an inductor.


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GENERAL RECOMMENDATIONS Output Voltage Ripple and Transients Source of the Output Ripple

Minimizing the Output Ripple

In order to minimize the output ripple voltage it is possible to enlarge the inductance value of the inductor L1 and/or to use a larger value output capacitor. There is also another way to smooth the output by means of an additional LC filter (20 µH, 100 µF), that can be added to the output (see Figure 35) to further reduce the amount of output ripple and transients. With such a filter it is possible to reduce the output ripple voltage transients 10 times or more. Figure 26 shows the difference between filtered and unfiltered output waveforms of the regulator shown in Figure 34. The upper waveform is from the normal unfiltered output of the converter, while the lower waveform shows the output ripple voltage filtered by an additional LC filter.

Since the LM2574 is a switch mode power supply regulator, its output voltage, if left unfiltered, will contain a sawtooth ripple voltage at the switching frequency. The output ripple voltage value ranges from 0.5% to 3% of the output voltage. It is caused mainly by the inductor sawtooth ripple current multiplied by the ESR of the output capacitor. Short Voltage Spikes and How to Reduce Them

The regulator output voltage may also contain short voltage spikes at the peaks of the sawtooth waveform (see Figure 26). These voltage spikes are present because of the fast switching action of the output switch, and the parasitic inductance of the output filter capacitor. There are some other important factors such as wiring inductance, stray capacitance, as well as the scope probe used to evaluate these transients, all these contribute to the amplitude of these spikes. To minimize these voltage spikes, low inductance capacitors should be used, and their lead lengths must be kept short. The importance of quality printed circuit board layout design should also be highlighted.

Heatsinking and Thermal Considerations

The LM2574 is available in both 8–pin DIP and SO–16L packages. When used in the typical application the copper lead frame conducts the majority of the heat from the die, through the leads, to the printed circuit copper. The copper and the board are the heatsink for this package and the other heat producing components, such as the catch diode and inductor. For the best thermal performance, wide copper traces should be used and all ground and unused pins should be soldered to generous amounts of printed circuit board copper, such as a ground plane. Large areas of copper provide the best transfer of heat to the surrounding air. One exception to this is the output (switch) pin, which should not have large areas of copper in order to minimize coupling to sensitive circuitry. Additional improvement in heat dissipation can be achieved even by using of double sided or multilayer boards which can provide even better heat path to the ambient. Using a socket for the 8–pin DIP package is not recommended because socket represents an additional thermal resistance, and as a result the junction temperature will be higher.

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LM2574 TJ = (RθJA)(PD) + TA

Since the current rating of the LM2574 is only 0.5 A, the total package power dissipation for this switcher is quite low, ranging from approximately 0.1 W up to 0.75 W under varying conditions. In a carefully engineered printed circuit board, the through–hole DIP package can easily dissipate up to 0.75 W, even at ambient temperatures of 60°C, and still keep the maximum junction temperature below 125°C.

where (RθJA)(PD) represents the junction temperature rise caused by the dissipated power and TA is the maximum ambient temperature. Some Aspects That can Influence Thermal Design

It should be noted that the package thermal resistance and the junction temperature rise numbers are all approximate, and there are many factors that will affect these numbers, such as PC board size, shape, thickness, physical position, location, board temperature, as well as whether the surrounding air is moving or still. At higher power levels the thermal resistance decreases due to the increased air current activity. Other factors are trace width, total printed circuit copper area, copper thickness, single– or double–sided, multilayer board, the amount of solder on the board or even color of the traces. The size, quantity and spacing of other components on the board can also influence its effectiveness to dissipate the heat. Some of them, like the catch diode or the inductor will generate some additional heat.

Thermal Analysis and Design

The following procedure must be performed to determine the operating junction temperature. First determine: 1. PD(max) – maximum regulator power dissipation in the application. 2. TA(max) – maximum ambient temperature in the application. 3. TJ(max) – maximum allowed junction temperature (125°C for the LM2574). For a conservative design, the maximum junction temperature should not exceed 110°C to assure safe operation. For every additional +10°C temperature rise that the junction must withstand, the estimated operating lifetime of the component is halved. 4. RθJC – package thermal resistance junction–case. 5. RθJA – package thermal resistance junction–ambient. (Refer to Absolute Maximum Ratings on page 1279 of this data sheet or RθJC and RθJA values).

ADDITIONAL APPLICATIONS Inverting Regulator

An inverting buck–boost regulator using the LM2574–12 is shown in Figure 27. This circuit converts a positive input voltage to a negative output voltage with a common ground by bootstrapping the regulators ground to the negative output voltage. By grounding the feedback pin, the regulator senses the inverted output voltage and regulates it. In this example the LM2574–12 is used to generate a –12 V output. The maximum input voltage in this case cannot exceed 28 V because the maximum voltage appearing across the regulator is the absolute sum of the input and output voltages and this must be limited to a maximum of 40 V. This circuit configuration is able to deliver approximately 0.1 A to the output when the input voltage is 8.0 V or higher. At lighter loads the minimum input voltage required drops to approximately 4.7 V, because the buck–boost regulator topology can produce an output voltage that, in its absolute value, is either greater or less than the input voltage. Since the switch currents in this buck–boost configuration are higher than in the standard buck converter topology, the available output current is lower. This type of buck–boost inverting regulator can also require a larger amount of startup input current, even for light loads. This may overload an input power source with a current limit less than 0.6 A. Because of the relatively high startup currents required by this inverting regulator topology, the use of a delayed startup or an undervoltage lockout circuit is recommended. While using a delayed startup arrangement, the input capacitor can charge up to a higher voltage before the switch–mode regulator begins to operate.

The following formula is to calculate the approximate total power dissipated by the LM2574: PD = (Vin x IQ) + d x ILoad x Vsat

where d is the duty cycle and for buck converter V t d + on + O , V T in

IQ (quiescent current) and Vsat can be found in the LM2574 data sheet, Vin is minimum input voltage applied, VO is the regulator output voltage, ILoad is the load current. $ ! & '(! )* + ! . *

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Figure 27. Inverting Buck–Boost Develops –12 V

The dynamic switching losses during turn–on and turn–off can be neglected if a proper type catch diode is used. The junction temperature can be determined by the following expression:


LM2574 The high input current needed for startup is now partially supplied by the input capacitor Cin.

by the fact, that the ground pin of the converter IC is no longer at ground. Now, the ON/OFF pin threshold voltage (1.3 V approximately) has to be related to the negative output voltage level. There are many different possible shutdown methods, two of them are shown in Figures 29 and 30.

Design Recommendations:

The inverting regulator operates in a different manner than the buck converter and so a different design procedure has to be used to select the inductor L1 or the output capacitor Cout. The output capacitor values must be larger than what is normally required for buck converter designs. Low input voltages or high output currents require a large value output capacitor (in the range of thousands of µF). The recommended range of inductor values for the inverting converter design is between 68 µH and 220 µH. To select an inductor with an appropriate current rating, the inductor peak current has to be calculated. ! & '(! )* + !

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Under normal continuous inductor current operating conditions, the worst case occurs when Vin is minimal. It has been already mentioned above, that in some situations, the delayed startup or the undervoltage lockout features could be very useful. A delayed startup circuit applied to a buck–boost converter is shown in Figure 28. Figure 34 in the “Undervoltage Lockout” section describes an undervoltage lockout feature for the same converter topology. With the inverting configuration, the use of the ON/OFF pin requires some level shifting techniques. This is caused

Figure 30. Inverting Buck–Boost Regulator Shutdown Circuit Using a PNP Transistor Negative Boost Regulator

This example is a variation of the buck–boost topology and it is called negative boost regulator. This regulator experiences relatively high switch current, especially at low input voltages. The internal switch current limiting results in lower output load current capability.


LM2574 When a high 50 Hz or 60 Hz (100 Hz or 120 Hz respectively) ripple voltage exists, a long delay time can cause some problems by coupling the ripple into the ON/OFF pin, the regulator could be switched periodically on and off with the line (or double) frequency.

The circuit in Figure 31 shows the negative boost configuration. The input voltage in this application ranges from –5.0 to –12 V and provides a regulated –12 V output. If the input voltage is greater than –12 V, the output will rise above –12 V accordingly, but will not damage the regulator.

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Figure 32. Delayed Startup Circuitry



The same design rules as for the previous inverting buck–boost converter can be applied. The output capacitor Cout must be chosen larger than what would be required for a standard buck converter. Low input voltages or high output currents require a large value output capacitor (in the range of thousands of µF). The recommended range of inductor values for the negative boost regulator is the same as for inverting converter design. Another important point is that these negative boost converters cannot provide any current limiting load protection in the event of a short in the output so some other means, such as a fuse, may be necessary to provide the load protection.

Some applications require the regulator to remain off until the input voltage reaches a certain threshold level. Figure 33 shows an undervoltage lockout circuit applied to a buck regulator. A version of this circuit for buck–boost converter is shown in Figure 34. Resistor R3 pulls the ON/OFF pin high and keeps the regulator off until the input voltage reaches a predetermined threshold level, which is determined by the following expression: V

th

[V

Z1

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There are some applications, like the inverting regulator already mentioned above, which require a higher amount of startup current. In such cases, if the input power source is limited, this delayed startup feature becomes very useful. To provide a time delay between the time when the input voltage is applied and the time when the output voltage comes up, the circuit in Figure 32 can be used. As the input voltage is applied, the capacitor C1 charges up, and the voltage across the resistor R2 falls down. When the voltage on the ON/OFF pin falls below the threshold value 1.3 V, the regulator starts up. Resistor R1 is included to limit the maximum voltage applied to the ON/OFF pin. It reduces the power supply noise sensitivity, and also limits the capacitor C1 discharge current, but its use is not mandatory.

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LM2574 Adjustable Output, Low–Ripple Power Supply

2 1

A 0.5 A output current capability power supply that features an adjustable output voltage is shown in Figure 35. This regulator delivers 0.5 A into 1.2 to 35 V output. The input voltage ranges from roughly 3.0 to 40 V. In order to achieve a 10 or more times reduction of output ripple, an additional L–C filter is included in this circuit.

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LM2574 The LM2574–5 Step–Down Voltage Regulator with 5.0 V @ 0.5 A Output Power Capability. Typical Application With Through–Hole PC Board Layout # .

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Figure 36. Schematic Diagram of the LM2574–5 Step–Down Converter

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Figure 38. PC Board Layout Copper Side


LM2574 The LM2574–ADJ Step–Down Voltage Regulator with 5.0 V @ 0.5 A Output Power Capability Typical Application With Through–Hole PC Board Layout #

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References • Marty Brown “Practical Switching Power Supply Design”, Academic Press, Inc., San Diego 1990 • Ray Ridley “High Frequency Magnetics Design”, Ridley Engineering, Inc. 1995


LM2574 ORDERING INFORMATION Device



LM2574DW–ADJ LM2574DW–ADJR2

1.23 V to 37 V

LM2574N–ADJ

Package

Shipping

SO–16W

47 Units/Rail

SO–16W


PDIP–8

50 Units/Rail

PDIP–8

50 Units/Rail

LM2574N–3.3

3.3 V

LM2574N–5

5.0 V

PDIP–8

50 Units/Rail

LM2574N–12

12 V

PDIP–8

50 Units/Rail

LM2574N–15

15 V

PDIP–8

50 Units/Rail

TA= –40° to +125°C

MARKING DIAGRAMS

SO–16W DW SUFFIX CASE 751G 16 2574DW–ADJ AWL YYWW 1

PDIP–8 N SUFFIX CASE 626 8

8 2574–ADJ AWL YYWW

1

8 2574–3.3 AWL YYWW

8 LM2574N–5 AWL YYWW

1

1

A WL YY WW

2574–12 AWL YYWW 1



8 2574–15 AWL YYWW 1

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+!( ,' '-. "#" The LM2575 series of regulators are monolithic integrated circuits ideally suited for easy and convenient design of a step–down switching regulator (buck converter). All circuits of this series are capable of driving a 1.0 A load with excellent line and load regulation. These devices are available in fixed output voltages of 3.3 V, 5.0 V, 12 V, 15 V, and an adjustable output version. These regulators were designed to minimize the number of external components to simplify the power supply design. Standard series of inductors optimized for use with the LM2575 are offered by several different inductor manufacturers. Since the LM2575 converter is a switch–mode power supply, its efficiency is significantly higher in comparison with popular three–terminal linear regulators, especially with higher input voltages. In many cases, the power dissipated by the LM2575 regulator is so low, that no heatsink is required or its size could be reduced dramatically. The LM2575 features include a guaranteed ±4% tolerance on output voltage within specified input voltages and output load conditions, and ±10% on the oscillator frequency (±2% over 0°C to 125°C). External shutdown is included, featuring 80 µA typical standby current. The output switch includes cycle–by–cycle current limiting, as well as thermal shutdown for full protection under fault conditions.

http://onsemi.com

TO–220 TV SUFFIX CASE 314B

1 5

Heatsink surface connected to Pin 3

TO–220 T SUFFIX CASE 314D 1 5 Pin

1. 2. 3. 4. 5.

Vin Output Ground Feedback ON/OFF

Features

• 3.3 V, 5.0 V, 12 V, 15 V, and Adjustable Output Versions • Adjustable Version Output Voltage Range of 1.23 V to 37 V ±4% • • • • • • • • •

Maximum Over Line and Load Conditions Guaranteed 1.0 A Output Current Wide Input Voltage Range: 4.75 V to 40 V Requires Only 4 External Components 52 kHz Fixed Frequency Internal Oscillator TTL Shutdown Capability, Low Power Standby Mode High Efficiency Uses Readily Available Standard Inductors Thermal Shutdown and Current Limit Protection Moisture Sensitivity Level (MSL) Equals 1

1 5

Heatsink surface (shown as terminal 6 in case outline drawing) is connected to Pin 3



Applications

• • • • • •


Simple and High–Efficiency Step–Down (Buck) Regulators Efficient Pre–Regulator for Linear Regulators On–Card Switching Regulators Positive to Negative Converters (Buck–Boost) Negative Step–Up Converters Power Supply for Battery Chargers



1302


LM2575 Typical Application (Fixed Output Voltage Versions) /(01 $ % " & '(! )* + !

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ABSOLUTE MAXIMUM RATINGS (Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.) Symbol

Value

Unit


Vin

45

V


–

–0.3 V ≤ V ≤ +Vin

V

Output Voltage to Ground (Steady–State)

–

–1.0

V

Power Dissipation Case 314B and 314D (TO–220, 5–Lead) Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case Case 936A (D2PAK) Thermal Resistance, Junction–to–Ambient (Figure 34) Thermal Resistance, Junction–to–Case

PD RθJA RθJC PD RθJA RθJC

Internally Limited 65 5.0 Internally Limited 70 5.0

W °C/W °C/W W °C/W °C/W


Tstg

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°C


–

3.0

kV

Lead Temperature (Soldering, 10 s)

–

260

°C


TJ

150

°C

Rating


LM2575 OPERATING RATINGS (Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.) Rating

Symbol

Value

Unit


TJ

–40 to +125

°C

Supply Voltage

Vin

40

V

SYSTEM PARAMETERS ([Note 1] Test Circuit Figure 14) ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Vin = 12 V for the 3.3 V, 5.0 V, and Adjustable version, Vin = 25 V for the 12 V version, and Vin = 30 V for the 15 V version. ILoad = 200 mA. For typical values TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies [Note 2], unless otherwise noted.) Symbol

Min

Typ

Max

Unit

Output Voltage (Vin = 12 V, ILoad = 0.2 A, TJ = 25°C)

Vout

3.234

3.3

3.366

V


Vout 3.168 3.135

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3.432 3.465

η

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–

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4.9

5.0

5.1

V


Vout 4.8 4.75

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11.76

12

12.24

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Vout

14.7

15

15.3

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Vout 14.4 14.25

15 –

15.6 15.75

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Feedback Voltage (Vin = 12 V, ILoad = 0.2 A, Vout = 5.0 V, TJ = 25°C)

VFB

1.217

1.23

1.243

V

Feedback Voltage (8.0 V ≤ Vin ≤ 40 V, 0.2 A ≤ ILoad ≤ 1.0 A, Vout = 5.0 V) TJ = 25°C TJ = –40 to +125°C

VFB 1.193 1.18

1.23 –

1.267 1.28

–

77

–

Characteristics LM2575–3.3 ([Note 1] Test Circuit Figure 14)


V



V


Efficiency (Vin = 15V, ILoad = 1.0 A)

V



V


η


V

%

1. External components such as the catch diode, inductor, input and output capacitors can affect switching regulator system performance. When the LM2575 is used as shown in the Figure 14 test circuit, system performance will be as shown in system parameters section. Thigh = +125°C 2. Tested junction temperature range for the LM2575: Tlow = –40°C


LM2575 DEVICE PARAMETERS ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Vin = 12 V for the 3.3 V, 5.0 V, and Adjustable version, Vin = 25 V for the 12 V version, and Vin = 30 V for the 15 V version. ILoad = 200 mA. For typical values TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies [Note 2], unless otherwise noted.) Symbol

Characteristics

Min

Typ

Max

– –

25 –

100 200

– 47 42

52 – –

– 58 63

– –

1.0 –

1.2 1.3

94

98

–

1.7 1.4

2.3 –

3.0 3.2

– –

0.8 6.0

2.0 20

– –

5.0 –

9.0 11

– –

80 –

200 400

Unit

ALL OUTPUT VOLTAGE VERSIONS Feedback Bias Current (Vout = 5.0 V [Adjustable Version Only]) TJ = 25°C TJ = –40 to +125°C

Ib

Oscillator Frequency [Note 3] TJ = 25°C TJ = 0 to +125°C TJ = –40 to +125°C

fosc

Saturation Voltage (Iout = 1.0 A [Note 4]) TJ = 25°C TJ = –40 to +125°C

Vsat

Max Duty Cycle (“on”) [Note 5]

DC

Current Limit (Peak Current [Notes 4 and 3]) TJ = 25°C TJ = –40 to +125°C

ICL

Output Leakage Current [Notes 6 and 7], TJ = 25°C Output = 0 V Output = –1.0 V

IL

Quiescent Current [Note 6] TJ = 25°C TJ = –40 to +125°C

IQ


nA

kHz

V

A

mA

mA

µA

Istby

ON/OFF Pin Logic Input Level (Test Circuit Figure 14) Vout = 0 V TJ = 25°C TJ = –40 to +125°C Vout = Nominal Output Voltage TJ = 25°C TJ = –40 to +125°C

%

V VIH 2.2 2.4

1.4 –

– –

– –

1.2 –

1.0 0.8

– –

15 0

30 5.0

VIL

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ON/OFF Pin Input Current (Test Circuit Figure 14) ON/OFF Pin = 5.0 V (“off”), TJ = 25°C ON/OFF Pin = 0 V (“on”), TJ = 25°C

IIH IIL

3. The oscillator frequency reduces to approximately 18 kHz in the event of an output short or an overload which causes the regulated output voltage to drop approximately 40% from the nominal output voltage. This self protection feature lowers the average dissipation of the IC by lowering the minimum duty cycle from 5% down to approximately 2%. 4. Output (Pin 2) sourcing current. No diode, inductor or capacitor connected to output pin. 5. Feedback (Pin 4) removed from output and connected to 0 V. 6. Feedback (Pin 4) removed from output and connected to +12 V for the Adjustable, 3.3 V, and 5.0 V versions, and +25 V for the 12 V and 15 V versions, to force the output transistor “off”. 7. Vin = 40 V.


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LM2575 PIN FUNCTION DESCRIPTION Pin

Symbol

1

Vin

2

Output

3

Gnd

4

Feedback

This pin senses regulated output voltage to complete the feedback loop. The signal is divided by the internal resistor divider network R2, R1 and applied to the non–inverting input of the internal error amplifier. In the Adjustable version of the LM2575 switching regulator this pin is the direct input of the error amplifier and the resistor network R2, R1 is connected externally to allow programming of the output voltage.

5

ON/OFF

It allows the switching regulator circuit to be shut down using logic level signals, thus dropping the total input supply current to approximately 80 µA. The input threshold voltage is typically 1.4 V. Applying a voltage above this value (up to +Vin) shuts the regulator off. If the voltage applied to this pin is lower than 1.4 V or if this pin is connected to ground, the regulator will be in the “on” condition.

Description (Refer to Figure 1) This pin is the positive input supply for the LM2575 step–down switching regulator. In order to minimize voltage transients and to supply the switching currents needed by the regulator, a suitable input bypass capacitor must be present (Cin in Figure 1). This is the emitter of the internal switch. The saturation voltage Vsat of this output switch is typically 1.0 V. It should be kept in mind that the PCB area connected to this pin should be kept to a minimum in order to minimize coupling to sensitive circuitry. Circuit ground pin. See the information about the printed circuit board layout.



L(on)

+

I


L

Figure 16 shows the buck converter idealized waveforms of the catch diode voltage and the inductor current.

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During this “on” period, energy is stored within the core material in the form of magnetic flux. If the inductor is properly designed, there is sufficient energy stored to carry the requirements of the load during the “off” period.

L(off)

+


The next period is the “off” period of the power switch. When the power switch turns off, the voltage across the inductor reverses its polarity and is clamped at one diode voltage drop below ground by catch dioded. Current now flows through the catch diode thus maintaining the load current loop. This removes the stored energy from the inductor. The inductor current during this time is:

+1 +5 )

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+,(; !04 5

Figure 16. Buck Converter Idealized Waveforms


LM2575 Procedure (Fixed Output Voltage Version) In order to simplify the switching regulator design, a step–by–step design procedure and example is provided. Procedure

Example

Given Parameters: Vout = Regulated Output Voltage (3.3 V, 5.0 V, 12 V or 15 V) Vin(max) = Maximum DC Input Voltage ILoad(max) = Maximum Load Current



1. Controller IC Selection According to the required input voltage, output voltage, current polarity and current value, use the LM2575–5 controller IC



3. Catch Diode Selection (D1) A. Since the diode maximum peak current exceeds the regulator maximum load current the catch diode current rating must be at least 1.2 times greater than the maximum load current. For a robust design the diode should have a current rating equal to the maximum current limit of the LM2575 to be able to withstand a continuous output short B. The reverse voltage rating of the diode should be at least 1.25 times the maximum input voltage. 4. Inductor Selection (L1) A. According to the required working conditions, select the correct inductor value using the selection guide from Figures 17 to 21. B. From the appropriate inductor selection guide, identify the inductance region intersected by the Maximum Input Voltage line and the Maximum Load Current line. Each region is identified by an inductance value and an inductor code. C. Select an appropriate inductor from the several different manufacturers part numbers listed in Table 1 or Table 2. When using Table 2 for selecting the right inductor the designer must realize that the inductor current rating must be higher than the maximum peak current flowing through the inductor. This maximum peak current can be calculated as follows: ǒVin–VoutǓ ton +I ) I p(max) Load(max) 2L


B. Use a 30 V 1N5818 Schottky diode, or any of the suggested fast recovery diodes shown in the Table 4. 4. Inductor Selection (L1) A. Use the inductor selection guide shown in Figures 17 to 21. B. From the selection guide, the inductance area intersected by the 20 V line and 0.8 A line is L330.

C. Inductor value required is 330 µH. From the Table 1 or Table 2, choose an inductor from any of the listed manufacturers.

where ton is the “on” time of the power switch and V ton + out x 1 fosc V in For additional information about the inductor, see the inductor section in the “External Components” section of this data sheet.


LM2575 Procedure (Fixed Output Voltage Version) (continued)In order to simplify the switching regulator design, a step–by–step design procedure and example is provided. Procedure

Example

5. Output Capacitor Selection (Cout) A. Since the LM2575 is a forward–mode switching regulator with voltage mode control, its open loop 2–pole–2–zero frequency characteristic has the dominant pole–pair determined by the output capacitor and inductor values. For stable operation and an acceptable ripple voltage, (approximately 1% of the output voltage) a value between 100 µF and 470 µF is recommended. B. Due to the fact that the higher voltage electrolytic capacitors generally have lower ESR (Equivalent Series Resistance) numbers, the output capacitor’s voltage rating should be at least 1.5 times greater than the output voltage. For a 5.0 V regulator, a rating at least 8V is appropriate, and a 10 V or 16 V rating is recommended.



Procedure (Adjustable Output Version: LM2575–Adj) Procedure

Example




1. Programming Output Voltage (selecting R1 and R2) Select R1 and R2:

ǒ

ǒ

V out + 1.23 1 )

Ǔ

R2 1) V out + V ref R1 where Vref = 1.23 V

ǒ

R2 + R1

Resistor R1 can be between 1.0 k and 5.0 kΩ. (For best temperature coefficient and stability with time, use 1% metal film resistors). V out R2 + R1 –1 V ref

ǒ

Ǔ

V out V

ref

Ǔ

R2 R1 Select R1 = 1.8 kΩ

Ǔ

*1

+ 1.8 k

8.0 V ǒ1.23 * 1Ǔ V

R2 = 9.91 kΩ, choose a 9.88 k metal film resistor.

2. Input Capacitor Selection (Cin) To prevent large voltage transients from appearing at the input and for stable operation of the converter, an aluminium or tantalum electrolytic bypass capacitor is needed between the input pin +Vin and ground pin Gnd This capacitor should be located close to the IC using short leads. This capacitor should have a low ESR (Equivalent Series Resistance) value.

2. Input Capacitor Selection (Cin) A 100 µF aluminium electrolytic capacitor located near the input and ground pin provides sufficient bypassing.

For additional information see input capacitor section in the “External Components” section of this data sheet. 3. Catch Diode Selection (D1) A. Since the diode maximum peak current exceeds the regulator maximum load current the catch diode current rating must be at least 1.2 times greater than the maximum load current. For a robust design, the diode should have a current rating equal to the maximum current limit of the LM2575 to be able to withstand a continuous output short. B. The reverse voltage rating of the diode should be at least 1.25 times the maximum input voltage.


B. Use a 20 V 1N5820 or MBR320 Schottky diode or any suggested fast recovery diode in the Table 4.


LM2575 Procedure (Adjustable Output Version: LM2575–Adj) (continued) Procedure

Example

4. Inductor Selection (L1) A. Use the following formula to calculate the inductor Volt x microsecond [V x µs] constant: V out 6 x 10 [V x s] E x T + V – V out in F[Hz] V on

ǒ

4. Inductor Selection (L1) A. Calculate E x T [V x µs] constant:

Ǔ

E x T + (12 – 8.0) x 8.0 x 1000 + 51 [V x s] 52 12

B. Match the calculated E x T value with the corresponding number on the vertical axis of the Inductor Value Selection Guide shown in Figure 21. This E x T constant is a measure of the energy handling capability of an inductor and is dependent upon the type of core, the core area, the number of turns, and the duty cycle. C. Next step is to identify the inductance region intersected by the E x T value and the maximum load current value on the horizontal axis shown in Figure 21. D. From the inductor code, identify the inductor value. Then select an appropriate inductor from the Table 1 or Table 2. The inductor chosen must be rated for a switching frequency of 52 kHz and for a current rating of 1.15 x IIoad. The inductor current rating can also be determined by calculating the inductor peak current: I

p(max)

+I

Load(max)

)

B. E x T = 51 [V x µs]

C. ILoad(max) = 1.0 A Inductance Region = L220 D. Proper inductor value = 220 µH Choose the inductor from the Table 1 or Table 2.

ǒVin – VoutǓ ton 2L

where ton is the “on” time of the power switch and V out

x 1 f osc in For additional information about the inductor, see the inductor section in the “External Components” section of this data sheet. t on +

V

5. Output Capacitor Selection (Cout) A. Since the LM2575 is a forward–mode switching regulator with voltage mode control, its open loop 2–pole–2–zero frequency characteristic has the dominant pole–pair determined by the output capacitor and inductor values.

5. Output Capacitor Selection (Cout) A. Cout w 7.785 12 + 53 µF 8.220 To achieve an acceptable ripple voltage, select Cout = 100 µF electrolytic capacitor.

For stable operation, the capacitor must satisfy the following requirement: V in(max) [µF] Cout w 7.785 V out x L [µH] B. Capacitor values between 10 µF and 2000 µF will satisfy the loop requirements for stable operation. To achieve an acceptable output ripple voltage and transient response, the output capacitor may need to be several times larger than the above formula yields. C. Due to the fact that the higher voltage electrolytic capacitors generally have lower ESR (Equivalent Series Resistance) numbers, the output capacitor’s voltage rating should be at least 1.5 times greater than the output voltage. For a 5.0 V regulator, a rating of at least 8V is appropriate, and a 10 V or 16 V rating is recommended.


LM2575 INDUCTOR VALUE SELECTION GUIDE

-

?AG;L+G&GA+&A,;:A

?AG;L+G&GA+&A,;:A

, ,"

$

,##

$

,

,

$

, $ $

$#

$"

$

$

$

,

,"

,##

$

,

$

, $#

$"

$

$

$ $ $ $

+,? G;L+G&G ,;) *&22: ;

Figure 17. LM2575–3.3

Figure 18. LM2575–5.0

-

?AG;L+G&GA+&A,;:A

?AG;L+G&GA+&A,;:A

-

+,? G;L+G&G ,;) *&22: ;

- - - -"

,

,"

" $

-

$ $

$

" #

"

,## ,

$#

$"

$

$

-

" # #

- -

-

,

,## ,

$

$ $ $ $

,"

$#

$"

$

$

+,? G;L+G&G ,;) *&22: ;

+,? G;L+G&G ,;) *&22: ;



:?A,;:A+G:AAAA3 µ

-

-

-

-"

," ,##

#

$

-

,

"

,

, ,

$#

$"

$

$

$ $ $ $

+,? G;L+G&G ,;) *&22: ;

Figure 21. LM2575–Adj

NOTE: This Inductor Value Selection Guide is applicable for continuous mode only.


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$ $ $ $

LM2575 Table 1. Inductor Selection Guide Inductor Code

Inductor Value

Pulse Eng

Renco

AIE

Tech 39

L100

100 µH

PE–92108

RL2444

415–0930

77 308 BV

L150

150 µH

PE–53113

RL1954

415–0953

77 358 BV

L220

220 µH

PE–52626

RL1953

415–0922

77 408 BV

L330

330 µH

PE–52627

RL1952

415–0926

77 458 BV

L470

470 µH

PE–53114

RL1951

415–0927

–

L680

680 µH

PE–52629

RL1950

415–0928

77 508 BV

H150

150 µH

PE–53115

RL2445

415–0936

77 368 BV

H220

220 µH

PE–53116

RL2446

430–0636

77 410 BV

H330

330 µH

PE–53117

RL2447

430–0635

77 460 BV

H470

470 µH

PE–53118

RL1961

430–0634

–

H680

680 µH

PE–53119

RL1960

415–0935

77 510 BV

H1000

1000 µH

PE–53120

RL1959

415–0934

77 558 BV

H1500

1500 µH

PE–53121

RL1958

415–0933

–

H2200

2200 µH

PE–53122

RL2448

415–0945

77 610 BV

Table 2. Inductor Selection Guide Inductance

Current

(µH)

(A)

THT

SMT

THT

SMT

THT

SMT

SMT

0.32

67143940

67144310

RL–1284–68–43

RL1500–68

PE–53804

PE–53804–S

DO1608–68

0.58

67143990

67144360

RL–5470–6

RL1500–68

PE–53812

PE–53812–S

DO3308–683

0.99

67144070

67144450

RL–5471–5

RL1500–68

PE–53821

PE–53821–S

DO3316–683

1.78

67144140

67144520

RL–5471–5

–

PE–53830

PE–53830–S

DO5022P–683

0.48

67143980

67144350

RL–5470–5

RL1500–100

PE–53811

PE–53811–S

DO3308–104

0.82

67144060

67144440

RL–5471–4

RL1500–100

PE–53820

PE–53820–S

DO3316–104

1.47

67144130

67144510

RL–5471–4

–

PE–53829

PE–53829–S

DO5022P–104

0.39

–

67144340

RL–5470–4

RL1500–150

PE–53810

PE–53810–S

DO3308–154

0.66

67144050

67144430

RL–5471–3

RL1500–150

PE–53819

PE–53819–S

DO3316–154

1.20

67144120

67144500

RL–5471–3

–

PE–53828

PE–53828–S

DO5022P–154

0.32

67143960

67144330

RL–5470–3

RL1500–220

PE–53809

PE–53809–S

DO3308–224

0.55

67144040

67144420

RL–5471–2

RL1500–220

PE–53818

PE–53818–S

DO3316–224

1.00

67144110

67144490

RL–5471–2

–

PE–53827

PE–53827–S

DO5022P–224

0.42

67144030

67144410

RL–5471–1

RL1500–330

PE–53817

PE–53817–S

DO3316–334

0.80

67144100

67144480

RL–5471–1

–

PE–53826

PE–53826–S

DO5022P–334

68

100

150

220

330

Schott

Renco

Pulse Engineering

Coilcraft

NOTE: Table 1 and Table 2 of this Indicator Selection Guide shows some examples of different manufacturer products suitable for design with the LM2575.


LM2575 Table 3. Example of Several Inductor Manufacturers Phone/Fax Numbers Pulse Engineering Inc.

Phone Fax

+ 1–619–674–8100 + 1–619–674–8262

Pulse Engineering Inc. Europe

Phone Fax

+ 353 93 24 107 + 353 93 24 459

Renco Electronics Inc.

Phone Fax

+ 1–516–645–5828 + 1–516–586–5562

AIE Magnetics

Phone Fax

+ 1–813–347–2181

Coilcraft Inc.

Phone Fax

+ 1–708–322–2645 + 1–708–639–1469

Coilcraft Inc., Europe

Phone Fax

+ 44 1236 730 595 + 44 1236 730 627

Tech 39

Phone Fax

+ 33 8425 2626 + 33 8425 2610

Schott Corp.

Phone Fax

+ 1–612–475–1173 + 1–612–475–1786

Table 4. Diode Selection Guide gives an overview about both surface–mount and through–hole diodes for an effective design. Device listed in bold are available from ON Semiconductor. Schottky

Ultra–Fast Recovery

1.0 A

3.0 A

1.0 A

VR

SMT

THT

SMT

THT

20 V

SK12

1N5817 SR102

SK32 MBRD320

1N5820 MBR320 SR302

30 V

MBRS130LT3 SK13

1N5818 SR103 11DQ03

SK33 MBRD330

1N5821 MBR330 SR303 31DQ03

40 V

MBRS140T3 SK14 10BQ040 10MQ040

1N5819 SR104 11DQ04

MBRS340T3 MBRD340 30WQ04 SK34

1N5822 MBR340 SR304 31DQ04

50 V

MBRS150 10BQ050

MBR150 SR105 11DQ05

MBRD350 SK35 30WQ05

MBR350 SR305 11DQ05

SMT

THT

MURS120T3

MUR120 11DF1 HER102

SMT

THT

MURS320T3


3.0 A

10BF10

MURD320

31DF1 HER302

MUR320 30WF10 MUR420

LM2575 EXTERNAL COMPONENTS Input Capacitor (Cin) The Input Capacitor Should Have a Low ESR

loop, resulting in oscillation at the output. This situation can occur when a tantalum capacitor, that can have a very low ESR, is used as the only output capacitor.

For stable operation of the switch mode converter a low ESR (Equivalent Series Resistance) aluminium or solid tantalum bypass capacitor is needed between the input pin and the ground pin to prevent large voltage transients from appearing at the input. It must be located near the regulator and use short leads. With most electrolytic capacitors, the capacitance value decreases and the ESR increases with lower temperatures. For reliable operation in temperatures below –25°C larger values of the input capacitor may be needed. Also paralleling a ceramic or solid tantalum capacitor will increase the regulator stability at cold temperatures.

At Low Temperatures, Put in Parallel Aluminium Electrolytic Capacitors with Tantalum Capacitors


RMS Current Rating of Cin

The important parameter of the input capacitor is the RMS current rating. Capacitors that are physically large and have large surface area will typically have higher RMS current ratings. For a given capacitor value, a higher voltage electrolytic capacitor will be physically larger than a lower voltage capacitor, and thus be able to dissipate more heat to the surrounding air, and therefore will have a higher RMS current rating. The consequence of operating an electrolytic capacitor above the RMS current rating is a shortened operating life. In order to assure maximum capacitor operating lifetime, the capacitor’s RMS ripple current rating should be:

Catch Diode Locate the Catch Diode Close to the LM2575

The LM2575 is a step–down buck converter; it requires a fast diode to provide a return path for the inductor current when the switch turns off. This diode must be located close to the LM2575 using short leads and short printed circuit traces to avoid EMI problems. Use a Schottky or a Soft Switching Ultra–Fast Recovery Diode

Since the rectifier diodes are very significant source of losses within switching power supplies, choosing the rectifier that best fits into the converter design is an important process. Schottky diodes provide the best performance because of their fast switching speed and low forward voltage drop. They provide the best efficiency especially in low output voltage applications (5.0 V and lower). Another choice could be Fast–Recovery, or Ultra–Fast Recovery diodes. It has to be noted, that some types of these diodes with an abrupt turnoff characteristic may cause instability or EMI troubles. A fast–recovery diode with soft recovery characteristics can better fulfill a quality, low noise design requirements. Table 4 provides a list of suitable diodes for the LM2575 regulator. Standard 50/60 Hz rectifier diodes such as the 1N4001 series or 1N5400 series are NOT suitable.

Irms > 1.2 x d x ILoad

where d is the duty cycle, for a buck regulator V t d + on + out V T in |V out| t on and d + + for a buck*boost regulator. |V out| ) V T in Output Capacitor (Cout)

For low output ripple voltage and good stability, low ESR output capacitors are recommended. An output capacitor has two main functions: it filters the output and provides regulator loop stability. The ESR of the output capacitor and the peak–to–peak value of the inductor ripple current are the main factors contributing to the output ripple voltage value. Standard aluminium electrolytics could be adequate for some applications but for quality design low ESR types are recommended. An aluminium electrolytic capacitor’s ESR value is related to many factors such as the capacitance value, the voltage rating, the physical size and the type of construction. In most cases, the higher voltage electrolytic capacitors have lower ESR value. Often capacitors with much higher voltage ratings may be needed to provide low ESR values that are required for low output ripple voltage.

Inductor

The magnetic components are the cornerstone of all switching power supply designs. The style of the core and the winding technique used in the magnetic component’s design has a great influence on the reliability of the overall power supply. Using an improper or poorly designed inductor can cause high voltage spikes generated by the rate of transitions in current within the switching power supply, and the possibility of core saturation can arise during an abnormal operational mode. Voltage spikes can cause the semiconductors to enter avalanche breakdown and the part can instantly fail if enough energy is applied. It can also cause significant RFI (Radio Frequency Interference) and EMI (Electro–Magnetic Interference) problems.

The Output Capacitor Requires an ESR Value That Has an Upper and Lower Limit

As mentioned above, a low ESR value is needed for low output ripple voltage, typically 1% to 2% of the output voltage. But if the selected capacitor’s ESR is extremely low (below 0.05 Ω), there is a possibility of an unstable feedback


LM2575 Continuous and Discontinuous Mode of Operation

amount of EMI (Electro–Magnetic Interference) shielding that the core must provide. The inductor selection guide covers different styles of inductors, such as pot core, E–core, toroid and bobbin core, as well as different core materials such as ferrites and powdered iron from different manufacturers. For high quality design regulators the toroid core seems to be the best choice. Since the magnetic flux is completely contained within the core, it generates less EMI, reducing noise problems in sensitive circuits. The least expensive is the bobbin core type, which consists of wire wound on a ferrite rod core. This type of inductor generates more EMI due to the fact that its core is open, and the magnetic flux is not completely contained within the core. When multiple switching regulators are located on the same printed circuit board, open core magnetics can cause interference between two or more of the regulator circuits, especially at high currents due to mutual coupling. A toroid, pot core or E–core (closed magnetic structure) should be used in such applications. Do Not Operate an Inductor Beyond its Maximum Rated Current

Exceeding an inductor’s maximum current rating may cause the inductor to overheat because of the copper wire losses, or the core may saturate. Core saturation occurs when the flux density is too high and consequently the cross sectional area of the core can no longer support additional lines of magnetic flux. This causes the permeability of the core to drop, the inductance value decreases rapidly and the inductor begins to look mainly resistive. It has only the dc resistance of the winding. This can cause the switch current to rise very rapidly and force the LM2575 internal switch into cycle–by–cycle current limit, thus reducing the dc output load current. This can also result in overheating of the inductor and/or the LM2575. Different inductor types have different saturation characteristics, and this should be kept in mind when selecting an inductor.

$

I:2AI+**&22:A;

+)&*2 *&22:A;

I:2AI+**&22:A;

The LM2575 step–down converter can operate in both the continuous and the discontinuous modes of operation. The regulator works in the continuous mode when loads are relatively heavy, the current flows through the inductor continuously and never falls to zero. Under light load conditions, the circuit will be forced to the discontinuous mode when inductor current falls to zero for certain period of time (see Figure 22 and Figure 23). Each mode has distinctively different operating characteristics, which can affect the regulator performance and requirements. In many cases the preferred mode of operation is the continuous mode. It offers greater output power, lower peak currents in the switch, inductor and diode, and can have a lower output ripple voltage. On the other hand it does require larger inductor values to keep the inductor current flowing continuously, especially at low output load currents and/or high input voltages. To simplify the inductor selection process, an inductor selection guide for the LM2575 regulator was added to this data sheet (Figures 17 through 21). This guide assumes that the regulator is operating in the continuous mode, and selects an inductor that will allow a peak–to–peak inductor ripple current to be a certain percentage of the maximum design load current. This percentage is allowed to change as different design load currents are selected. For light loads (less than approximately 200 mA) it may be desirable to operate the regulator in the discontinuous mode, because the inductor value and size can be kept relatively low. Consequently, the percentage of inductor peak–to–peak current increases. This discontinuous mode of operation is perfectly acceptable for this type of switching converter. Any buck regulator will be forced to enter discontinuous mode if the load current is light enough.

$

$ A

+)&*2 *&22:A;

-2+J;, +G: ;:M $ µ3)+

$ A


-2+J;, +G: ;:M $ µ3)+

Selecting the Right Inductor Style

Some important considerations when selecting a core type are core material, cost, the output power of the power supply, the physical volume the inductor must fit within, and the

Figure 23. Discontinuous Mode Switching Current Waveforms


LM2575 GENERAL RECOMMENDATIONS Output Voltage Ripple and Transients Source of the Output Ripple

Heatsinking and Thermal Considerations The Through–Hole Package TO–220

Since the LM2575 is a switch mode power supply regulator, its output voltage, if left unfiltered, will contain a sawtooth ripple voltage at the switching frequency. The output ripple voltage value ranges from 0.5% to 3% of the output voltage. It is caused mainly by the inductor sawtooth ripple current multiplied by the ESR of the output capacitor.

The LM2575 is available in two packages, a 5–pin TO–220(T, TV) and a 5–pin surface mount D2PAK(D2T). There are many applications that require no heatsink to keep the LM2575 junction temperature within the allowed operating range. The TO–220 package can be used without a heatsink for ambient temperatures up to approximately 50°C (depending on the output voltage and load current). Higher ambient temperatures require some heatsinking, either to the printed circuit (PC) board or an external heatsink.

Short Voltage Spikes and How to Reduce Them


The Surface Mount Package D 2PAK and its Heatsinking

The other type of package, the surface mount D2PAK, is designed to be soldered to the copper on the PC board. The copper and the board are the heatsink for this package and the other heat producing components, such as the catch diode and inductor. The PC board copper area that the package is soldered to should be at least 0.4 in2 (or 100 mm2) and ideally should have 2 or more square inches (1300 mm2) of 0.0028 inch copper. Additional increasing of copper area beyond approximately 3.0 in2 (2000 mm2) will not improve heat dissipation significantly. If further thermal improvements are needed, double sided or multilayer PC boards with large copper areas should be considered.

'!( 31 3 0( 3 /@ 3 !04 (0! 7 !4 ! ! 3 !04 ( !4 ((3!0 0!(0 7 !4 ! ! 0((0!

&+,:2:) && ,;:


The following procedure must be performed to determine whether or not a heatsink will be required. First determine: 1. PD(max) maximum regulator power dissipation in the application. 2. TA(max) maximum ambient temperature in the application. 3. TJ(max) maximum allowed junction temperature (125°C for the LM2575). For a conservative design, the maximum junction temperature should not exceed 110°C to assure safe operation. For every additional 10°C temperature rise that the junction must withstand, the estimated operating lifetime of the component is halved. 4. RθJC package thermal resistance junction–case. 5. RθJA package thermal resistance junction–ambient. (Refer to Absolute Maximum Ratings in this data sheet or RθJC and RθJA values).

:2+*;, 2:,&+M

5)+ +,:2:) && ,;:

-2+J;, +G: ;:M µ3)+

Figure 24. Output Ripple Voltage Waveforms Minimizing the Output Ripple

In order to minimize the output ripple voltage it is possible to enlarge the inductance value of the inductor L1 and/or to use a larger value output capacitor. There is also another way to smooth the output by means of an additional LC filter (20 µH, 100 µF), that can be added to the output (see Figure 33) to further reduce the amount of output ripple and transients. With such a filter it is possible to reduce the output ripple voltage transients 10 times or more. Figure 24 shows the difference between filtered and unfiltered output waveforms of the regulator shown in Figure 33. The upper waveform is from the normal unfiltered output of the converter, while the lower waveform shows the output ripple voltage filtered by an additional LC filter.

The following formula is to calculate the total power dissipated by the LM2575: PD = (Vin x IQ) + d x ILoad x Vsat

where d is the duty cycle and for buck converter


LM2575 & '(! )* + ! !

V t d + on + O , V T in

IQ Vin VO ILoad

* µ

(quiescent current) and Vsat can be found in the LM2575 data sheet, is minimum input voltage applied, is the regulator output voltage, is the load current.

/(01 .

LM2575–12

#

" ! !

)

* ! µ 2 '(! ! ! % N $# ;

The dynamic switching losses during turn–on and turn–off can be neglected if proper type catch diode is used.

Figure 25. Inverting Buck–Boost Regulator Using the LM2575–12 Develops –12 V @ 0.35 A

Packages Not on a Heatsink (Free–Standing)

For a free–standing application when no heatsink is used, the junction temperature can be determined by the following expression:


TJ = (RθJA) (PD) + TA

An inverting buck–boost regulator using the LM2575–12 is shown in Figure 25. This circuit converts a positive input voltage to a negative output voltage with a common ground by bootstrapping the regulators ground to the negative output voltage. By grounding the feedback pin, the regulator senses the inverted output voltage and regulates it. In this example the LM2575–12 is used to generate a –12 V output. The maximum input voltage in this case cannot exceed +28 V because the maximum voltage appearing across the regulator is the absolute sum of the input and output voltages and this must be limited to a maximum of 40 V. This circuit configuration is able to deliver approximately 0.35 A to the output when the input voltage is 12 V or higher. At lighter loads the minimum input voltage required drops to approximately 4.7 V, because the buck–boost regulator topology can produce an output voltage that, in its absolute value, is either greater or less than the input voltage. Since the switch currents in this buck–boost configuration are higher than in the standard buck converter topology, the available output current is lower. This type of buck–boost inverting regulator can also require a larger amount of startup input current, even for light loads. This may overload an input power source with a current limit less than 1.5 A. Such an amount of input startup current is needed for at least 2.0 ms or more. The actual time depends on the output voltage and size of the output capacitor. Because of the relatively high startup currents required by this inverting regulator topology, the use of a delayed startup or an undervoltage lockout circuit is recommended.

where (RθJA)(PD) represents the junction temperature rise caused by the dissipated power and TA is the maximum ambient temperature. Packages on a Heatsink

If the actual operating junction temperature is greater than the selected safe operating junction temperature determined in step 3, than a heatsink is required. The junction temperature will be calculated as follows: TJ = PD (RθJA + RθCS + RθSA) + TA

where

, µ-

RθJC is the thermal resistance junction–case, RθCS is the thermal resistance case–heatsink, RθSA is the thermal resistance heatsink–ambient.

If the actual operating temperature is greater than the selected safe operating junction temperature, then a larger heatsink is required. Some Aspects That can Influence Thermal Design

It should be noted that the package thermal resistance and the junction temperature rise numbers are all approximate, and there are many factors that will affect these numbers, such as PC board size, shape, thickness, physical position, location, board temperature, as well as whether the surrounding air is moving or still. Other factors are trace width, total printed circuit copper area, copper thickness, single– or double–sided, multilayer board, the amount of solder on the board or even color of the traces. The size, quantity and spacing of other components on the board can also influence its effectiveness to dissipate the heat.


LM2575 Using a delayed startup arrangement, the input capacitor can charge up to a higher voltage before the switch–mode regulator begins to operate. The high input current needed for startup is now partially supplied by the input capacitor Cin.

.

4 ! + !

$

The inverting regulator operates in a different manner than the buck converter and so a different design procedure has to be used to select the inductor L1 or the output capacitor Cout. The output capacitor values must be larger than is normally required for buck converter designs. Low input voltages or high output currents require a large value output capacitor (in the range of thousands of µF). The recommended range of inductor values for the inverting converter design is between 68 µH and 220 µH. To select an inductor with an appropriate current rating, the inductor peak current has to be calculated. The following formula is used to obtain the peak inductor current:

77

LM2575–12

2 " 1

# 2 " 1

" ! !

Figure 27. Inverting Buck–Boost Regulator Shut Down Circuit Using an Optocoupler

With the inverting configuration, the use of the ON/OFF pin requires some level shifting techniques. This is caused by the fact, that the ground pin of the converter IC is no longer at ground. Now, the ON/OFF pin threshold voltage (1.4 V approximately) has to be related to the negative output voltage level. There are many different possible shut down methods, two of them are shown in Figures 27 and 28. .

.

77

4 ! + !

2 $ 1

.

, µ-

C

# * ! µ

)

2 " 1

LM2575–XX

* µ

#


/(01

2# "

Under normal continuous inductor current operating conditions, the worst case occurs when Vin is minimal. Note that the voltage appearing across the regulator is the absolute sum of the input and output voltage, and must not exceed 40 V.

* * µ $ µ

G*

I (V ) |V |) O ) V in x t on [ Load in 2L 1 V in |V | O where t on + x 1 , and f osc + 52 kHz. V ) |V | f osc in O

.

* 2 µ " 1

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Figure 28. Inverting Buck–Boost Regulator Shut Down Circuit Using a PNP Transistor

Figure 26. Inverting Buck–Boost Regulator with Delayed Startup

Negative Boost Regulator

This example is a variation of the buck–boost topology and is called a negative boost regulator. This regulator experiences relatively high switch current, especially at low input voltages. The internal switch current limiting results in lower output load current capability. The circuit in Figure 29 shows the negative boost configuration. The input voltage in this application ranges from –5.0 V to –12 V and provides a regulated –12 V output.

It has been already mentioned above, that in some situations, the delayed startup or the undervoltage lockout features could be very useful. A delayed startup circuit applied to a buck–boost converter is shown in Figure 26. Figure 32 in the “Undervoltage Lockout” section describes an undervoltage lockout feature for the same converter topology.


LM2575 cause some problems by coupling the ripple into the ON/OFF pin, the regulator could be switched periodically on and off with the line (or double) frequency.

If the input voltage is greater than –12 V, the output will rise above –12 V accordingly, but will not damage the regulator.

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Figure 30. Delayed Startup Circuitry

Figure 29. Negative Boost Regulator Undervoltage Lockout Design Recommendations:

Some applications require the regulator to remain off until the input voltage reaches a certain threshold level. Figure 31 shows an undervoltage lockout circuit applied to a buck regulator. A version of this circuit for buck–boost converter is shown in Figure 32. Resistor R3 pulls the ON/OFF pin high and keeps the regulator off until the input voltage reaches a predetermined threshold level, which is determined by the following expression:

The same design rules as for the previous inverting buck–boost converter can be applied. The output capacitor Cout must be chosen larger than would be required for a standard buck converter. Low input voltages or high output currents require a large value output capacitor (in the range of thousands of µF). The recommended range of inductor values for the negative boost regulator is the same as for inverting converter design. Another important point is that these negative boost converters cannot provide current limiting load protection in the event of a short in the output so some other means, such as a fuse, may be necessary to provide the load protection.

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There are some applications, like the inverting regulator already mentioned above, which require a higher amount of startup current. In such cases, if the input power source is limited, this delayed startup feature becomes very useful. To provide a time delay between the time the input voltage is applied and the time when the output voltage comes up, the circuit in Figure 30 can be used. As the input voltage is applied, the capacitor C1 charges up, and the voltage across the resistor R2 falls down. When the voltage on the ON/OFF pin falls below the threshold value 1.4 V, the regulator starts up. Resistor R1 is included to limit the maximum voltage applied to the ON/OFF pin, reduces the power supply noise sensitivity, and also limits the capacitor C1 discharge current, but its use is not mandatory. When a high 50 Hz or 60 Hz (100 Hz or 120 Hz respectively) ripple voltage exists, a long delay time can

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LM2575 Adjustable Output, Low–Ripple Power Supply .

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A 1.0 A output current capability power supply that features an adjustable output voltage is shown in Figure 33. This regulator delivers 1.0 A into 1.2 V to 35 V output. The input voltage ranges from roughly 8.0 V to 40 V. In order to achieve a 10 or more times reduction of output ripple, an additional L–C filter is included in this circuit.

LM2575–5.0

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LM2575 THE LM2575–5.0 STEP–DOWN VOLTAGE REGULATOR WITH 5.0 V @ 1.0 A OUTPUT POWER CAPABILITY. TYPICAL APPLICATION WITH THROUGH–HOLE PC BOARD LAYOUT /(01 "

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Figure 35. Schematic Diagram of the LM2575–5.0 Step–Down Converter

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LM2575 THE LM2575–ADJ STEP–DOWN VOLTAGE REGULATOR WITH 8.0 V @ 1.0 A OUTPUT POWER CAPABILITY. TYPICAL APPLICATION WITH THROUGH–HOLE PC BOARD LAYOUT 2 '(! ! ! &7'! ! > $ N $ ; " & '(! )* + !

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Figure 38. Schematic Diagram of the 8.0 V @ 1.0 V Step–Down Converter Using the LM2575–Adj (An additional LC filter is included to achieve low output ripple voltage)

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References

• • • •

National Semiconductor LM2575 Data Sheet and Application Note National Semiconductor LM2595 Data Sheet and Application Note Marty Brown “Practical Switching Power Supply Design”, Academic Press, Inc., San Diego 1990 Ray Ridley “High Frequency Magnetics Design”, Ridley Engineering, Inc. 1995


LM2575 ORDERING INFORMATION Device



LM2575TV–ADJ

TO–220 (Straight Lead) 1 23 V to 37 V 1.23

D2PAK (Surface Mount)

LM2575D2T–ADJR4


LM2575TV–3.3

TO–220 (Vertical Mount)

LM2575T–3.3

TO–220 (Straight Lead) 33V 3.3

D2PAK

(Surface Mount)

LM2575D2T–3.3R4

D2PAK

(Surface Mount)

LM2575TV–5


LM2575D2T–3.3

LM2575T–5 LM2575D2T–5

TJ = –40° 40° to +125°C

D2PAK (Surface Mount) D2PAK (Surface Mount)

LM2575TV–12


LM2575T–12

800 Tape & Reel

TO–220 (Straight Lead) 12 V


LM2575D2T–12R4


LM2575TV–15


LM2575T–15 LM2575D2T–15

50 Units/Rail


LM2575D2T–5R4

LM2575D2T–12

Shipping


LM2575T–ADJ LM2575D2T–ADJ

Package

TO–220 (Straight Lead) 15 V

D2PAK (Surface Mount) D2PAK (Surface Mount)

LM2575D2T–15R4

MARKING DIAGRAMS TO–220 TV SUFFIX CASE 314B


LM 2575T–xxx AWLYWW



LM 2575–xxx AWLYWW

1 1

5

1

xxx A WL Y WW

5

= 3.3, 5.0, 12, 15, or ADJ = Assembly Location = Wafer Lot = Year = Work Week


5

50 Units/Rail

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'-. "#" The LM2576 series of regulators are monolithic integrated circuits ideally suited for easy and convenient design of a step–down switching regulator (buck converter). All circuits of this series are capable of driving a 3.0 A load with excellent line and load regulation. These devices are available in fixed output voltages of 3.3 V, 5.0 V, 12 V, 15 V, and an adjustable output version. These regulators were designed to minimize the number of external components to simplify the power supply design. Standard series of inductors optimized for use with the LM2576 are offered by several different inductor manufacturers. Since the LM2576 converter is a switch–mode power supply, its efficiency is significantly higher in comparison with popular three–terminal linear regulators, especially with higher input voltages. In many cases, the power dissipated is so low that no heatsink is required or its size could be reduced dramatically. A standard series of inductors optimized for use with the LM2576 are available from several different manufacturers. This feature greatly simplifies the design of switch–mode power supplies. The LM2576 features include a guaranteed ±4% tolerance on output voltage within specified input voltages and output load conditions, and ±10% on the oscillator frequency (±2% over 0°C to 125°C). External shutdown is included, featuring 80 µA (typical) standby current. The output switch includes cycle–by–cycle current limiting, as well as thermal shutdown for full protection under fault conditions.

http://onsemi.com


1 5


TO–220 T SUFFIX CASE 314D 1 5 Pin

Features

• 3.3 V, 5.0 V, 12 V, 15 V, and Adjustable Output Versions • Adjustable Version Output Voltage Range, 1.23 to 37 V ±4% • • • • • • • • •

Maximum Over Line and Load Conditions Guaranteed 3.0 A Output Current Wide Input Voltage Range Requires Only 4 External Components 52 kHz Fixed Frequency Internal Oscillator TTL Shutdown Capability, Low Power Standby Mode High Efficiency Uses Readily Available Standard Inductors Thermal Shutdown and Current Limit Protection Moisture Sensitivity Level (MSL) Equals 1

5 Heatsink surface (shown as terminal 6 in case outline drawing) is connected to Pin 3



Simple High–Efficiency Step–Down (Buck) Regulator Efficient Pre–Regulator for Linear Regulators On–Card Switching Regulators Positive to Negative Converter (Buck–Boost) Negative Step–Up Converters Power Supply for Battery Chargers



Vin Output Ground Feedback ON/OFF


1

Applications

• • • • • •

1. 2. 3. 4. 5.

1326


LM2576 Typical Application (Fixed Output Voltage Versions) /(01 $ % " & '(! )* + !

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ABSOLUTE MAXIMUM RATINGS (Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.) Rating

Symbol

Value

Unit


Vin

45

V


–

–0.3 V ≤ V ≤ +Vin

V

Output Voltage to Ground (Steady–State)

–

–1.0

V

Power Dissipation Case 314B and 314D (TO–220, 5–Lead) Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case Case 936A (D2PAK) Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case

PD RθJA RθJC PD RθJA RθJC




Tstg

–65 to +150

°C


–

2.0

kV


–

260

°C


TJ

150

°C


LM2576 OPERATING RATINGS (Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.) Rating

Symbol

Value

Unit


TJ

–40 to +125

°C

Supply Voltage

Vin

40

V

SYSTEM PARAMETERS ([Note 1] Test Circuit Figure 15) ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Vin = 12 V for the 3.3 V, 5.0 V, and Adjustable version, Vin = 25 V for the 12 V version, and Vin = 30 V for the 15 V version. ILoad = 500 mA. For typical values TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies [Note 2], unless otherwise noted.) Symbol

Min

Typ

Max

Unit


Vout

3.234

3.3

3.366

V


Vout 3.168 3.135

3.3 –

3.432 3.465

η

–

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–

%


Vout

4.9

5.0

5.1

V


Vout 4.8 4.75

5.0 –

5.2 5.25

η

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Vout

11.76

12

12.24

V


Vout 11.52 11.4

12 –

12.48 12.6

η

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Vout

14.7

15

15.3

V


Vout 14.4 14.25

15 –

15.6 15.75

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Feedback Voltage (Vin = 12 V, ILoad = 0.5 A, Vout = 5.0 V, TJ = 25°C)

Vout

1.217

1.23

1.243

V

Feedback Voltage (8.0 V ≤ Vin ≤ 40 V, 0.5 A ≤ ILoad ≤ 3.0 A, Vout = 5.0 V) TJ = 25°C TJ = –40 to +125°C

Vout 1.193 1.18

1.23 –

1.267 1.28

–

77

–

Characteristics LM2576–3.3 ([Note 1] Test Circuit Figure 15)


V



V



V



V


η


V

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1. External components such as the catch diode, inductor, input and output capacitors can affect switching regulator system performance. When the LM2576 is used as shown in the Figure 15 test circuit, system performance will be as shown in system parameters section. Thigh = +125°C 2. Tested junction temperature range for the LM2576: Tlow = –40°C


LM2576 DEVICE PARAMETERS ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Vin = 12 V for the 3.3 V, 5.0 V, and Adjustable version, Vin = 25 V for the 12 V version, and Vin = 30 V for the 15 V version. ILoad = 500 mA. For typical values TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies [Note 2], unless otherwise noted.) Symbol

Characteristics

Min

Typ

Max

– –

25 –

100 200

– 47 42

52 – –

– 58 63

– –

1.5 –

1.8 2.0

94

98

–

4.2 3.5

5.8 –

6.9 7.5

– –

0.8 6.0

2.0 20

– –

5.0 –

9.0 11

– –

80 –

200 400

Unit

ALL OUTPUT VOLTAGE VERSIONS Feedback Bias Current (Vout = 5.0 V [Adjustable Version Only]) TJ = 25°C TJ = –40 to +125°C

Ib

Oscillator Frequency [Note 3] TJ = 25°C TJ = 0 to +125°C TJ = –40 to +125°C

fosc

Saturation Voltage (Iout = 3.0 A [Note 4]) TJ = 25°C TJ = –40 to +125°C

Vsat

Max Duty Cycle (“on”) [Note 5]

DC

Current Limit (Peak Current [Notes 3 and 4]) TJ = 25°C TJ = –40 to +125°C

ICL

Output Leakage Current [Notes 6 and 7], TJ = 25°C Output = 0 V Output = –1.0 V

IL

Quiescent Current [Note 6] TJ = 25°C TJ = –40 to +125°C

IQ


nA

kHz

V

A

mA

mA

µA

Istby

ON/OFF Pin Logic Input Level (Test Circuit Figure 15) Vout = 0 V TJ = 25°C TJ = –40 to +125°C Vout = Nominal Output Voltage TJ = 25°C TJ = –40 to +125°C

%

V VIH 2.2 2.4

1.4 –

– –

– –

1.2 –

1.0 0.8

– –

15 0

30 5.0

VIL

µA

ON/OFF Pin Input Current (Test Circuit Figure 15) ON/OFF Pin = 5.0 V (“off”), TJ = 25°C ON/OFF Pin = 0 V (“on”), TJ = 25°C

IIH IIL

3. The oscillator frequency reduces to approximately 18 kHz in the event of an output short or an overload which causes the regulated output voltage to drop approximately 40% from the nominal output voltage. This self protection feature lowers the average dissipation of the IC by lowering the minimum duty cycle from 5% down to approximately 2%. 4. Output (Pin 2) sourcing current. No diode, inductor or capacitor connected to output pin. 5. Feedback (Pin 4) removed from output and connected to 0 V. 6. Feedback (Pin 4) removed from output and connected to +12 V for the Adjustable, 3.3 V, and 5.0 V versions, and +25 V for the 12 V and 15 V versions, to force the output transistor “off”. 7. Vin = 40 V.


LM2576 TYPICAL PERFORMANCE CHARACTERISTICS (Circuit of Figure 15) $" ! ?A&&A,;:A*-;:AE

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LM2576 TYPICAL PERFORMANCE CHARACTERISTICS (Circuit of Figure 15) ;

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Vout = 15 V A: Output Pin Voltage, 10 V/DIV B: Inductor Current, 2.0 A/DIV C: Inductor Current, 2.0 A/DIV, AC–Coupled D: Output Ripple Voltage, 50 mV/dDIV, AC–Coupled Horizontal Time Base: 5.0 µs/DIV


LM2576 Fixed Output Voltage Versions /(01

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100 µF, 75 V, Aluminium Electrolytic 1000 µF, 25 V, Aluminium Electrolytic Schottky, MBR360 100 µH, Pulse Eng. PE–92108 2.0 k, 0.1% 6.12 k, 0.1%

Adjustable Output Voltage Versions /(01

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LM2576 PIN FUNCTION DESCRIPTION Pin

Symbol

1

Vin

This pin is the positive input supply for the LM2576 step–down switching regulator. In order to minimize voltage transients and to supply the switching currents needed by the regulator, a suitable input bypass capacitor must be present (Cin in Figure 1).

2

Output

This is the emitter of the internal switch. The saturation voltage Vsat of this output switch is typically 1.5 V. It should be kept in mind that the PCB area connected to this pin should be kept to a minimum in order to minimize coupling to sensitive circuitry.

3

Gnd

4

Feedback

This pin senses regulated output voltage to complete the feedback loop. The signal is divided by the internal resistor divider network R2, R1 and applied to the non–inverting input of the internal error amplifier. In the Adjustable version of the LM2576 switching regulator this pin is the direct input of the error amplifier and the resistor network R2, R1 is connected externally to allow programming of the output voltage.

5

ON/OFF

It allows the switching regulator circuit to be shut down using logic level signals, thus dropping the total input supply current to approximately 80 µA. The threshold voltage is typically 1.4 V. Applying a voltage above this value (up to +Vin) shuts the regulator off. If the voltage applied to this pin is lower than 1.4 V or if this pin is left open, the regulator will be in the “on” condition.

Description (Refer to Figure 1)

Circuit ground pin. See the information about the printed circuit board layout.




L(on)

+



Figure 17 shows the buck converter, idealized waveforms of the catch diode voltage and the inductor current.


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During this “on” period, energy is stored within the core material in the form of magnetic flux. If the inductor is properly designed, there is sufficient energy stored to carry the requirements of the load during the “off” period. ,

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The next period is the “off” period of the power switch. When the power switch turns off, the voltage across the inductor reverses its polarity and is clamped at one diode voltage drop below ground by the catch diode. The current now flows through the catch diode thus maintaining the load current loop. This removes the stored energy from the inductor. The inductor current during this time is: L(off)

+

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Figure 17. Buck Converter Idealized Waveforms

ǒVout – VDǓ toff L


LM2576 Procedure (Fixed Output Voltage Version) In order to simplify the switching regulator design, a step–by–step design procedure and some examples are provided. Procedure

Example

Given Parameters: Vout = Regulated Output Voltage (3.3 V, 5.0 V, 12 V or 15 V) Vin(max) = Maximum Input Voltage ILoad(max) = Maximum Load Current



1. Controller IC Selection According to the required input voltage, output voltage, current polarity and current value, use the LM2576–5 controller IC



3. Catch Diode Selection (D1) A. Since the diode maximum peak current exceeds the regulator maximum load current the catch diode current rating must be at least 1.2 times greater than the maximum load current. For a robust design the diode should have a current rating equal to the maximum current limit of the LM2576 to be able to withstand a continuous output short B. The reverse voltage rating of the diode should be at least 1.25 times the maximum input voltage.


4. Inductor Selection (L1) A. According to the required working conditions, select the correct inductor value using the selection guide from Figures 18 to 22. B. From the appropriate inductor selection guide, identify the inductance region intersected by the Maximum Input Voltage line and the Maximum Load Current line. Each region is identified by an inductance value and an inductor code. C. Select an appropriate inductor from the several different manufacturers part numbers listed in Table 2. The designer must realize that the inductor current rating must be higher than the maximum peak current flowing through the inductor. This maximum peak current can be calculated as follows:

4. Inductor Selection (L1) A. Use the inductor selection guide shown in Figures 19.

I

p(max)

+I

Load(max)

)

B. Use a 20 V 1N5820 Schottky diode, or any of the suggested fast recovery diodes shown in Table 1.

B. From the selection guide, the inductance area intersected by the 15 V line and 3.0 A line is L100.

C. Inductor value required is 100 µH. From Table 2, choose an inductor from any of the listed manufacturers.

ǒVin–VoutǓ ton 2L

where ton is the “on” time of the power switch and V ton + out x 1.0 fosc V in For additional information about the inductor, see the inductor section in the “Application Hints” section of this data sheet.


LM2576 Procedure (Fixed Output Voltage Version) (continued)In order to simplify the switching regulator design, a step–by–step design procedure and some examples are provided. Procedure

Example

5. Output Capacitor Selection (Cout) A. Since the LM2576 is a forward–mode switching regulator with voltage mode control, its open loop 2–pole–1–zero frequency characteristic has the dominant pole–pair determined by the output capacitor and inductor values. For stable operation and an acceptable ripple voltage, (approximately 1% of the output voltage) a value between 680 µF and 2000 µF is recommended. B. Due to the fact that the higher voltage electrolytic capacitors generally have lower ESR (Equivalent Series Resistance) numbers, the output capacitor’s voltage rating should be at least 1.5 times greater than the output voltage. For a 5.0 V regulator, a rating at least 8.0 V is appropriate, and a 10 V or 16 V rating is recommended.



Procedure (Adjustable Output Version: LM2576–ADJ) Procedure

Example




1. Programming Output Voltage (selecting R1 and R2) Select R1 and R2:

ǒ

Ǔ

R2 1.0 ) V out + V ref R1

ǒ

where Vref = 1.23 V

R2 + R1

Resistor R1 can be between 1.0 k and 5.0 kΩ. (For best temperature coefficient and stability with time, use 1% metal film resistors). V out R2 + R1 – 1.0 V ref

ǒ

ǒ

V out + 1.23 1.0 )

Ǔ

V out V

ref

Ǔ

R2 R1

Ǔ

* 1.0

Select R1 = 1.8 kΩ + 1.8 k

8.0 V ǒ1.23 * 1.0Ǔ V

R2 = 9.91 kΩ, choose a 9.88 k metal film resistor.

2. Input Capacitor Selection (Cin) To prevent large voltage transients from appearing at the input and for stable operation of the converter, an aluminium or tantalum electrolytic bypass capacitor is needed between the input pin +Vin and ground pin Gnd This capacitor should be located close to the IC using short leads. This capacitor should have a low ESR (Equivalent Series Resistance) value.

2. Input Capacitor Selection (Cin) A 100 µF, 150 V aluminium electrolytic capacitor located near the input and ground pin provides sufficient bypassing.

For additional information see input capacitor section in the “Application Hints” section of this data sheet. 3. Catch Diode Selection (D1) A. Since the diode maximum peak current exceeds the regulator maximum load current the catch diode current rating must be at least 1.2 times greater than the maximum load current. For a robust design, the diode should have a current rating equal to the maximum current limit of the LM2576 to be able to withstand a continuous output short. B. The reverse voltage rating of the diode should be at least 1.25 times the maximum input voltage.


B. Use a 30 V 1N5821 Schottky diode or any suggested fast recovery diode in the Table 1.


LM2576 Procedure (Adjustable Output Version: LM2576–ADJ) (continued) Procedure

Example

4. Inductor Selection (L1) A. Use the following formula to calculate the inductor Volt x microsecond [V x µs] constant: V out 6 x 10 [V x s] E x T + V – V out in F[Hz] V in B. Match the calculated E x T value with the corresponding number on the vertical axis of the Inductor Value Selection Guide shown in Figure 22. This E x T constant is a measure of the energy handling capability of an inductor and is dependent upon the type of core, the core area, the number of turns, and the duty cycle. C. Next step is to identify the inductance region intersected by the E x T value and the maximum load current value on the horizontal axis shown in Figure 25. D. From the inductor code, identify the inductor value. Then select an appropriate inductor from Table 2. The inductor chosen must be rated for a switching frequency of 52 kHz and for a current rating of 1.15 x ILoad. The inductor current rating can also be determined by calculating the inductor peak current:

ǒ

I

p(max)

4. Inductor Selection (L1) A. Calculate E x T [V x µs] constant:

Ǔ

+I

Load(max)

)

E x T + (25 – 8.0) x 8.0 x 1000 + 80 [V x s] 52 25 B. E x T = 80 [V x µs]

C. ILoad(max) = 2.5 A Inductance Region = H150 D. Proper inductor value = 150 µH Choose the inductor from Table 2.

ǒVin – VoutǓ ton 2L

where ton is the “on” time of the power switch and V out

x 1.0 f osc in For additional information about the inductor, see the inductor section in the “External Components” section of this data sheet. t on +

V

5. Output Capacitor Selection (Cout) A. Since the LM2576 is a forward–mode switching regulator with voltage mode control, its open loop 2–pole–1–zero frequency characteristic has the dominant pole–pair determined by the output capacitor and inductor values.

5. Output Capacitor Selection (Cout) A. Cout w 13, 300 x 25 + 332.5 µF 8 x 150 To achieve an acceptable ripple voltage, select Cout = 680 µF electrolytic capacitor.

For stable operation, the capacitor must satisfy the following requirement: V in(max) [µF] Cout w 13, 300 V out x L [µH] B. Capacitor values between 10 µF and 2000 µF will satisfy the loop requirements for stable operation. To achieve an acceptable output ripple voltage and transient response, the output capacitor may need to be several times larger than the above formula yields. C. Due to the fact that the higher voltage electrolytic capacitors generally have lower ESR (Equivalent Series Resistance) numbers, the output capacitor’s voltage rating should be at least 1.5 times greater than the output voltage. For a 5.0 V regulator, a rating of at least 8.0 V is appropriate, and a 10 V or 16 V rating is recommended.


LM2576 LM2576 Series Buck Regulator Design Procedures (continued)

"

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G;L+G&GA+&A,;:A

G;L+G&GA+&A,;:A

Indicator Value Selection Guide (For Continuous Mode Operation)

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Figure 18. LM2576–3.3

,

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+,? G;L+G&G ,;) *&22: ;

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+,? G;L+G&G ,;) *&22: ;

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Figure 22. LM2576–ADJ


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LM2576 Table 1. Diode Selection Guide Schottky 3.0 A

Fast Recovery 4.0 – 6.0 A

3.0 A

Through Hole

Surface Mount

Through Hole

20 V

1N5820 MBR320P SR302

SK32

1N5823 SR502 SB520

30 V

1N5821 MBR330 SR303 31DQ03

SK33 30WQ03

1N5824 SR503 SB530

50WQ03

1N5822 MBR340 SR304 31DQ04

SK34 30WQ04 MBRS340T3 MBRD340

1N5825 SR504 SB540

MBRD640CT 50WQ04

50 V

MBR350 31DQ05 SR305

SK35 30WQ05

SB550

50WQ05

60 V

MBR360 DQ06 SR306

MBRS360T3 MBRD360

50SQ080

MBRD660CT

VR

40 V

Surface Mount

4.0 – 6.0 A

Through Hole

Surface Mount

Through Hole

Surface Mount

MUR320 31DF1 HER302

MURS320T3 MURD320 30WF10

MUR420 HER602

MURD620CT 50WF10

(all diodes rated to at least 100 V)




NOTE: Diodes listed in bold are available from ON Semiconductor.

Table 2. Inductor Selection by Manufacturer’s Part Number Inductor Code

Inductor Value

Tech 39

Schott Corp.

Pulse Eng.

Renco

L47

47 µH

77 212

671 26980

PE–53112

RL2442

L68

68 µH

77 262

671 26990

PE–92114

RL2443

L100

100 µH

77 312

671 27000

PE–92108

RL2444

L150

150 µH

77 360

671 27010

PE–53113

RL1954

L220

220 µH

77 408

671 27020

PE–52626

RL1953

L330

330 µH

77 456

671 27030

PE–52627

RL1952

L470

470 µH

*

671 27040

PE–53114

RL1951

L680

680 µH

77 506

671 27050

PE–52629

RL1950

H150

150 µH

77 362

671 27060

PE–53115

RL2445

H220

220 µH

77 412

671 27070

PE–53116

RL2446

H330

330 µH

77 462

671 27080

PE–53117

RL2447

H470

470 µH

*

671 27090

PE–53118

RL1961

H680

680 µH

77 508

671 27100

PE–53119

RL1960

H1000

1000 µH

77 556

671 27110

PE–53120

RL1959

H1500

1500 µH

*

671 27120

PE–53121

RL1958

H2200

2200 µH

*

671 27130

PE–53122

RL2448

NOTE: *Contact Manufacturer


LM2576 Table 3. Example of Several Inductor Manufacturers Phone/Fax Numbers Pulse Engineering, Inc.

Phone Fax

+ 1–619–674–8100 + 1–619–674–8262

Pulse Engineering, Inc. Europe

Phone Fax

+ 353–9324–107 + 353–9324–459

Renco Electronics, Inc.

Phone Fax

+ 1–516–645–5828 + 1–516–586–5562

Tech 39

Phone Fax

+ 33–1–4115–1681 + 33–1–4709–5051

Schott Corporation

Phone Fax

+ 1–612–475–1173 + 1–612–475–1786

EXTERNAL COMPONENTS Input Capacitor (Cin) The Input Capacitor Should Have a Low ESR

Output Capacitor (Cout)

For low output ripple voltage and good stability, low ESR output capacitors are recommended. An output capacitor has two main functions: it filters the output and provides regulator loop stability. The ESR of the output capacitor and the peak–to–peak value of the inductor ripple current are the main factors contributing to the output ripple voltage value. Standard aluminium electrolytics could be adequate for some applications but for quality design, low ESR types are recommended. An aluminium electrolytic capacitor’s ESR value is related to many factors such as the capacitance value, the voltage rating, the physical size and the type of construction. In most cases, the higher voltage electrolytic capacitors have lower ESR value. Often capacitors with much higher voltage ratings may be needed to provide low ESR values that, are required for low output ripple voltage.

For stable operation of the switch mode converter a low ESR (Equivalent Series Resistance) aluminium or solid tantalum bypass capacitor is needed between the input pin and the ground pin, to prevent large voltage transients from appearing at the input. It must be located near the regulator and use short leads. With most electrolytic capacitors, the capacitance value decreases and the ESR increases with lower temperatures. For reliable operation in temperatures below –25°C larger values of the input capacitor may be needed. Also paralleling a ceramic or solid tantalum capacitor will increase the regulator stability at cold temperatures. RMS Current Rating of Cin

The important parameter of the input capacitor is the RMS current rating. Capacitors that are physically large and have large surface area will typically have higher RMS current ratings. For a given capacitor value, a higher voltage electrolytic capacitor will be physically larger than a lower voltage capacitor, and thus be able to dissipate more heat to the surrounding air, and therefore will have a higher RMS current rating. The consequence of operating an electrolytic capacitor beyond the RMS current rating is a shortened operating life. In order to assure maximum capacitor operating lifetime, the capacitor’s RMS ripple current rating should be:

The Output Capacitor Requires an ESR Value That Has an Upper and Lower Limit

As mentioned above, a low ESR value is needed for low output ripple voltage, typically 1% to 2% of the output voltage. But if the selected capacitor’s ESR is extremely low (below 0.05 Ω), there is a possibility of an unstable feedback loop, resulting in oscillation at the output. This situation can occur when a tantalum capacitor, that can have a very low ESR, is used as the only output capacitor. At Low Temperatures, Put in Parallel Aluminium Electrolytic Capacitors with Tantalum Capacitors

Irms > 1.2 x d x ILoad


where d is the duty cycle, for a buck regulator V t d + on + out V T in |V out| t on and d + + for a buck*boost regulator. |V out| ) V T in


LM2576 Catch Diode Locate the Catch Diode Close to the LM2576

The LM2576 is a step–down buck converter; it requires a fast diode to provide a return path for the inductor current when the switch turns off. This diode must be located close to the LM2576 using short leads and short printed circuit traces to avoid EMI problems. Use a Schottky or a Soft Switching Ultra–Fast Recovery Diode

Since the rectifier diodes are very significant sources of losses within switching power supplies, choosing the rectifier that best fits into the converter design is an important process. Schottky diodes provide the best performance because of their fast switching speed and low forward voltage drop. They provide the best efficiency especially in low output voltage applications (5.0 V and lower). Another choice could be Fast–Recovery, or Ultra–Fast Recovery diodes. It has to be noted, that some types of these diodes with an abrupt turnoff characteristic may cause instability or EMI troubles. A fast–recovery diode with soft recovery characteristics can better fulfill some quality, low noise design requirements. Table 1 provides a list of suitable diodes for the LM2576 regulator. Standard 50/60 Hz rectifier diodes, such as the 1N4001 series or 1N5400 series are NOT suitable.

:22+*;,A2:,&+A $A;)+

ripple voltage. On the other hand it does require larger inductor values to keep the inductor current flowing continuously, especially at low output load currents and/or high input voltages. To simplify the inductor selection process, an inductor selection guide for the LM2576 regulator was added to this data sheet (Figures 18 through 22). This guide assumes that the regulator is operating in the continuous mode, and selects an inductor that will allow a peak–to–peak inductor ripple current to be a certain percentage of the maximum design load current. This percentage is allowed to change as different design load currents are selected. For light loads (less than approximately 300 mA) it may be desirable to operate the regulator in the discontinuous mode, because the inductor value and size can be kept relatively low. Consequently, the percentage of inductor peak–to–peak current increases. This discontinuous mode of operation is perfectly acceptable for this type of switching converter. Any buck regulator will be forced to enter discontinuous mode if the load current is light enough.

$ ; + 0! * ! I(< 75 ;

Inductor

$ ; !04 * ! I(< 75 ;

The magnetic components are the cornerstone of all switching power supply designs. The style of the core and the winding technique used in the magnetic component’s design has a great influence on the reliability of the overall power supply. Using an improper or poorly designed inductor can cause high voltage spikes generated by the rate of transitions in current within the switching power supply, and the possibility of core saturation can arise during an abnormal operational mode. Voltage spikes can cause the semiconductors to enter avalanche breakdown and the part can instantly fail if enough energy is applied. It can also cause significant RFI (Radio Frequency Interference) and EMI (Electro–Magnetic Interference) problems.

-2+J;, +G: ;:M $ µ3)+

Figure 23. Continuous Mode Switching Current Waveforms Selecting the Right Inductor Style

Some important considerations when selecting a core type are core material, cost, the output power of the power supply, the physical volume the inductor must fit within, and the amount of EMI (Electro–Magnetic Interference) shielding that the core must provide. The inductor selection guide covers different styles of inductors, such as pot core, E–core, toroid and bobbin core, as well as different core materials such as ferrites and powdered iron from different manufacturers. For high quality design regulators the toroid core seems to be the best choice. Since the magnetic flux is contained within the core, it generates less EMI, reducing noise problems in sensitive circuits. The least expensive is the bobbin core type, which consists of wire wound on a ferrite rod core. This type of inductor generates more EMI due to the fact that its core is open, and the magnetic flux is not contained within the core.

Continuous and Discontinuous Mode of Operation

The LM2576 step–down converter can operate in both the continuous and the discontinuous modes of operation. The regulator works in the continuous mode when loads are relatively heavy, the current flows through the inductor continuously and never falls to zero. Under light load conditions, the circuit will be forced to the discontinuous mode when inductor current falls to zero for certain period of time (see Figure 23 and Figure 24). Each mode has distinctively different operating characteristics, which can affect the regulator performance and requirements. In many cases the preferred mode of operation is the continuous mode. It offers greater output power, lower peak currents in the switch, inductor and diode, and can have a lower output


LM2576 inductor and/or the LM2576. Different inductor types have different saturation characteristics, and this should be kept in mind when selecting an inductor.

Do Not Operate an Inductor Beyond its Maximum Rated Current

$" ; + 0! * ! I(< 75 ;

Exceeding an inductor’s maximum current rating may cause the inductor to overheat because of the copper wire losses, or the core may saturate. Core saturation occurs when the flux density is too high and consequently the cross sectional area of the core can no longer support additional lines of magnetic flux. This causes the permeability of the core to drop, the inductance value decreases rapidly and the inductor begins to look mainly resistive. It has only the DC resistance of the winding. This can cause the switch current to rise very rapidly and force the LM2576 internal switch into cycle–by–cycle current limit, thus reducing the DC output load current. This can also result in overheating of the

:2+*;,A2:,&+A A5;)+

When multiple switching regulators are located on the same printed circuit board, open core magnetics can cause interference between two or more of the regulator circuits, especially at high currents due to mutual coupling. A toroid, pot core or E–core (closed magnetic structure) should be used in such applications.

$" ; !04 * ! I(< 75 ; -2+J;, +G: ;:M $ µ3)+

Figure 24. Discontinuous Mode Switching Current Waveforms

GENERAL RECOMMENDATIONS Output Voltage Ripple and Transients Source of the Output Ripple

Minimizing the Output Ripple

In order to minimize the output ripple voltage it is possible to enlarge the inductance value of the inductor L1 and/or to use a larger value output capacitor. There is also another way to smooth the output by means of an additional LC filter (20 µH, 100 µF), that can be added to the output (see Figure 34) to further reduce the amount of output ripple and transients. With such a filter it is possible to reduce the output ripple voltage transients 10 times or more. Figure 25 shows the difference between filtered and unfiltered output waveforms of the regulator shown in Figure 34. The lower waveform is from the normal unfiltered output of the converter, while the upper waveform shows the output ripple voltage filtered by an additional LC filter.

Since the LM2576 is a switch mode power supply regulator, its output voltage, if left unfiltered, will contain a sawtooth ripple voltage at the switching frequency. The output ripple voltage value ranges from 0.5% to 3% of the output voltage. It is caused mainly by the inductor sawtooth ripple current multiplied by the ESR of the output capacitor. Short Voltage Spikes and How to Reduce Them


Heatsinking and Thermal Considerations The Through–Hole Package TO–220

The LM2576 is available in two packages, a 5–pin TO–220(T, TV) and a 5–pin surface mount D2PAK(D2T). Although the TO–220(T) package needs a heatsink under most conditions, there are some applications that require no heatsink to keep the LM2576 junction temperature within the allowed operating range. Higher ambient temperatures require some heat sinking, either to the printed circuit (PC) board or an external heatsink.

'!( 31 3 0( 3 /@ 3 !04 (0! 7 !4 ! ! 3 !04 ( !4 ((3!0 0!(0 7 !4 ! ! 0((0!

The Surface Mount Package D 2PAK and its Heatsinking

The other type of package, the surface mount D2PAK, is designed to be soldered to the copper on the PC board. The copper and the board are the heatsink for this package and the other heat producing components, such as the catch diode and inductor. The PC board copper area that the package is soldered to should be at least 0.4 in2 (or 260 mm2) and ideally should have 2 or more square inches (1300 mm2) of 0.0028 inch copper. Additional increases of copper area

:22+*;, 2:,&+

A5)+

'! ! ! '!(

&7'! ! ! '!( -2+J;, +G: ;:M $ µ3)+

Figure 25. Output Ripple Voltage Waveforms


LM2576 beyond approximately 6.0 in2 (4000 mm2) will not improve heat dissipation significantly. If further thermal improvements are needed, double sided or multilayer PC boards with large copper areas should be considered. In order to achieve the best thermal performance, it is highly recommended to use wide copper traces as well as large areas of copper in the printed circuit board layout. The only exception to this is the OUTPUT (switch) pin, which should not have large areas of copper (see page 1333 ‘PCB Layout Guideline’).

Packages on a Heatsink

If the actual operating junction temperature is greater than the selected safe operating junction temperature determined in step 3, than a heatsink is required. The junction temperature will be calculated as follows: TJ = PD (RθJA + RθCS + RθSA) + TA

where

RθJC is the thermal resistance junction–case, RθCS is the thermal resistance case–heatsink, RθSA is the thermal resistance heatsink–ambient.

If the actual operating temperature is greater than the selected safe operating junction temperature, then a larger heatsink is required.


The following procedure must be performed to determine whether or not a heatsink will be required. First determine: 1. PD(max) maximum regulator power dissipation in the application. 2. TA(max) maximum ambient temperature in the application. 3. TJ(max) maximum allowed junction temperature (125°C for the LM2576). For a conservative design, the maximum junction temperature should not exceed 110°C to assure safe operation. For every additional +10°C temperature rise that the junction must withstand, the estimated operating lifetime of the component is halved. 4. RθJC package thermal resistance junction–case. 5. RθJA package thermal resistance junction–ambient. (Refer to Absolute Maximum Ratings on page 1327 of this data sheet or RθJC and RθJA values).

Some Aspects That can Influence Thermal Design

It should be noted that the package thermal resistance and the junction temperature rise numbers are all approximate, and there are many factors that will affect these numbers, such as PC board size, shape, thickness, physical position, location, board temperature, as well as whether the surrounding air is moving or still. Other factors are trace width, total printed circuit copper area, copper thickness, single– or double–sided, multilayer board, the amount of solder on the board or even color of the traces. The size, quantity and spacing of other components on the board can also influence its effectiveness to dissipate the heat. ! " & '(! )* + !

The following formula is to calculate the approximate total power dissipated by the LM2576:

* µ

PD = (Vin x IQ) + d x ILoad x Vsat

/(01 .

LM2576–12

#

" ! !

where d is the duty cycle and for buck converter

, µ)

* !

µ % N $ ; 2 '(! ! !

V t d + on + O , V T in

Figure 26. Inverting Buck–Boost Develops –12 V

IQ

(quiescent current) and Vsat can be found in the LM2576 data sheet, Vin is minimum input voltage applied, VO is the regulator output voltage, ILoad is the load current. The dynamic switching losses during turn–on and turn–off can be neglected if proper type catch diode is used.


An inverting buck–boost regulator using the LM2576–12 is shown in Figure 26. This circuit converts a positive input voltage to a negative output voltage with a common ground by bootstrapping the regulators ground to the negative output voltage. By grounding the feedback pin, the regulator senses the inverted output voltage and regulates it. In this example the LM2576–12 is used to generate a –12 V output. The maximum input voltage in this case cannot exceed +28 V because the maximum voltage appearing across the regulator is the absolute sum of the input and output voltages and this must be limited to a maximum of 40 V.

Packages Not on a Heatsink (Free–Standing)

For a free–standing application when no heatsink is used, the junction temperature can be determined by the following expression: TJ = (RθJA) (PD) + TA

where (RθJA)(PD) represents the junction temperature rise caused by the dissipated power and TA is the maximum ambient temperature.


LM2576 I (V ) |V |) O ) V in x t on [ Load in 2L 1 V in |V | O where t on + x 1.0 , and f osc + 52 kHz. V ) |V | f osc in O

This circuit configuration is able to deliver approximately 0.7 A to the output when the input voltage is 12 V or higher. At lighter loads the minimum input voltage required drops to approximately 4.7 V, because the buck–boost regulator topology can produce an output voltage that, in its absolute value, is either greater or less than the input voltage. Since the switch currents in this buck–boost configuration are higher than in the standard buck converter topology, the available output current is lower. This type of buck–boost inverting regulator can also require a larger amount of start–up input current, even for light loads. This may overload an input power source with a current limit less than 5.0 A. Such an amount of input start–up current is needed for at least 2.0 ms or more. The actual time depends on the output voltage and size of the output capacitor. Because of the relatively high start–up currents required by this inverting regulator topology, the use of a delayed start–up or an undervoltage lockout circuit is recommended. Using a delayed start–up arrangement, the input capacitor can charge up to a higher voltage before the switch–mode regulator begins to operate. The high input current needed for start–up is now partially supplied by the input capacitor Cin. It has been already mentioned above, that in some situations, the delayed start–up or the undervoltage lockout features could be very useful. A delayed start–up circuit applied to a buck–boost converter is shown in Figure 27, Figure 33 in the “Undervoltage Lockout” section describes an undervoltage lockout feature for the same converter topology.

I

peak

Under normal continuous inductor current operating conditions, the worst case occurs when Vin is minimal. ! & '(! )* + ! * µ

/(01 .

* $ µ

LM2576–12

2 " 1

#

" ! !

, µ-

* !

µ

)

2 " 1

% N 5 ; 2 '(! ! !

Figure 27. Inverting Buck–Boost Regulator with Delayed start–up

.

. LM2576–XX

4 ! + !

$


The inverting regulator operates in a different manner than the buck converter and so a different design procedure has to be used to select the inductor L1 or the output capacitor Cout. The output capacitor values must be larger than what is normally required for buck converter designs. Low input voltages or high output currents require a large value output capacitor (in the range of thousands of µF). The recommended range of inductor values for the inverting converter design is between 68 µH and 220 µH. To select an inductor with an appropriate current rating, the inductor peak current has to be calculated. The following formula is used to obtain the peak inductor current:

77

* 2 µ " 1

2# "

#

2 " 1 % ! G*


Figure 28. Inverting Buck–Boost Regulator Shutdown Circuit Using an Optocoupler

With the inverting configuration, the use of the ON/OFF pin requires some level shifting techniques. This is caused by the fact, that the ground pin of the converter IC is no longer at ground. Now, the ON/OFF pin threshold voltage (1.3 V approximately) has to be related to the negative output voltage level. There are many different possible shut down methods, two of them are shown in Figures 28 and 29.


LM2576 .

4 ! + !

77

2 $ 1

.

Another important point is that these negative boost converters cannot provide current limiting load protection in the event of a short in the output so some other means, such as a fuse, may be necessary to provide the load protection.

.

Delayed Start–up

C

#

There are some applications, like the inverting regulator already mentioned above, which require a higher amount of start–up current. In such cases, if the input power source is limited, this delayed start–up feature becomes very useful. To provide a time delay between the time when the input voltage is applied and the time when the output voltage comes up, the circuit in Figure 31 can be used. As the input voltage is applied, the capacitor C1 charges up, and the voltage across the resistor R2 falls down. When the voltage on the ON/OFF pin falls below the threshold value 1.3 V, the regulator starts up. Resistor R1 is included to limit the maximum voltage applied to the ON/OFF pin. It reduces the power supply noise sensitivity, and also limits the capacitor C1 discharge current, but its use is not mandatory. When a high 50 Hz or 60 Hz (100 Hz or 120 Hz respectively) ripple voltage exists, a long delay time can cause some problems by coupling the ripple into the ON/OFF pin, the regulator could be switched periodically on and off with the line (or double) frequency.

LM2576–XX

* µ

#

2 1

% !


Figure 29. Inverting Buck–Boost Regulator Shutdown Circuit Using a PNP Transistor Negative Boost Regulator

This example is a variation of the buck–boost topology and it is called negative boost regulator. This regulator experiences relatively high switch current, especially at low input voltages. The internal switch current limiting results in lower output load current capability. The circuit in Figure 30 shows the negative boost configuration. The input voltage in this application ranges from –5.0 V to –12 V and provides a regulated –12 V output. If the input voltage is greater than –12 V, the output will rise above –12 V accordingly, but will not damage the regulator.

.

.

* $ µ

LM2576–12

* µ

* µ

* !

µ , :3

"

/(01

µ-

#

2 " 1

NOTE: This picture does not show the complete circuit. ! > %

2 " 1

! ! #

LM2576–XX

Figure 31. Delayed Start–up Circuitry

@0(' ,( * ! " 5; 7 > %$ 5; 7 > %$


Some applications require the regulator to remain off until the input voltage reaches a certain threshold level. Figure 32 shows an undervoltage lockout circuit applied to a buck regulator. A version of this circuit for buck–boost converter is shown in Figure 33. Resistor R3 pulls the ON/OFF pin high and keeps the regulator off until the input voltage reaches a predetermined threshold level with respect to the ground Pin 3, which is determined by the following expression:

%$ ! %

Figure 30. Negative Boost Regulator Design Recommendations:

The same design rules as for the previous inverting buck–boost converter can be applied. The output capacitor Cout must be chosen larger than would be required for a what standard buck converter. Low input voltages or high output currents require a large value output capacitor (in the range of thousands of µF). The recommended range of inductor values for the negative boost regulator is the same as for inverting converter design.

V


th

[V

Z1

ǒ

Ǔ

(Q1) ) 1.0 ) R2 V R1 BE

LM2576

.

Under normal continuous inductor current operating conditions, the worst case occurs when Vin is minimal.

.

LM2576–XX

2 1

* µ

2# " 1

#

2 1

J " C

#" 2 1

.

.

* µ

2# " 1

LM2576–XX

#

J "

!4 ≈ #

!4 ≈ #

C

#" 2 1


!



The following formula is used to obtain the peak inductor current:


I (V ) |V |) O ) V in x t on [ Load in peak 2L 1 V in |V | O where t on + x 1.0 , and f osc + 52 kHz. V ) |V | f osc in O I

" G(9 & '(! )* + !

A 3.0 A output current capability power supply that features an adjustable output voltage is shown in Figure 34. This regulator delivers 3.0 A into 1.2 V to 35 V output. The input voltage ranges from roughly 3.0 V to 40 V. In order to achieve a 10 or more times reduction of output ripple, an additional L–C filter is included in this circuit.

/(01 "

.

LM2574–Adj

* µ

Adjustable Output, Low–Ripple Power Supply

! ! #

, µ-

,

µ-

$ ! # N #$ ;

2 1 )

* !

µ

2 $ 1

* µ

!(' ! ! 2' '!

Figure 34. 1.2 to 35 V Adjustable 3.0 A Power Supply with Low Output Ripple


! ! '!(

LM2576 THE LM2576–5 STEP–DOWN VOLTAGE REGULATOR WITH 5.0 V @ 3.0 A OUTPUT POWER CAPABILITY. TYPICAL APPLICATION WITH THROUGH–HOLE PC BOARD LAYOUT /(01 "

.

& '(! )* + ! . > $ ! "

, µ-

LM2576–5

! ! #

* µ

2 '(! ! ! ! > $ N #$ ;

)

* ! µ !

C1 C2 D1 L1

– – – –

100 µF, 50 V, Aluminium Electrolytic 1000 µF, 16 V, Aluminium Electrolytic 3.0 A, 40 V, Schottky Rectifier, 1N5822 150 µH, RL2444, Renco Electronics

Figure 35. Schematic Diagram of the LM2576–5 Step–Down Converter

P

,G

& )

. *

*

!

.

.

,

! NOTE: Not to scale.

NOTE: Not to scale.

Figure 36. Printed Circuit Board Layout Component Side

Figure 37. Printed Circuit Board Layout Copper Side


LM2576 THE LM2576–ADJ STEP–DOWN VOLTAGE REGULATOR WITH 8.0 V @ 1.0 A OUTPUT POWER CAPABILITY. TYPICAL APPLICATION WITH THROUGH–HOLE PC BOARD LAYOUT " & '(! )* + !

.

. > ! "

/(01

LM2576–ADJ ! ! #

, µ-

2 '(! ! ! '!

2 1

* µ

)

* µ

2 $ 1

C1 C2 D1 L1 R1 R2

– – – – – –

100 µF, 50 V, Aluminium Electrolytic 1000 µF, 16 V, Aluminium Electrolytic 3.0 A, 40 V, Schottky Rectifier, 1N5822 150 µH, RL2444, Renco Electronics 1.8 kΩ, 0.25 W 10 kΩ, 0.25 W

! > $ N #$ ;

ǒ

Ǔ

2 ! + 7 ) $ ) 2

7 > $ # 2 3 / ! $ 1 ( $ 1

P

Figure 38. Schematic Diagram of the 8.0 V @ 3.0 A Step–Down Converter Using the LM2576–ADJ

,G & )

2 2

* .

. *

! . ,

! NOTE: Not to scale.

NOTE: Not to scale.

Figure 39. Printed Circuit Board Layout Component Side

Figure 40. Printed Circuit Board Layout Copper Side

References

• • • •

National Semiconductor LM2576 Data Sheet and Application Note National Semiconductor LM2595 Data Sheet and Application Note Marty Brown “Practical Switching Power Supply Design”, Academic Press, Inc., San Diego 1990 Ray Ridley “High Frequency Magnetics Design”, Ridley Engineering, Inc. 1995 http://onsemi.com 1348

LM2576 ORDERING INFORMATION Nominal Output Voltage

Device


Package

LM2576TV–ADJ

Shipping


LM2576T–ADJ

TO–220 (Straight Lead) 1 23 V to 37 V 1.23

LM2576D2T–ADJ

D2PAK

(Surface Mount)

LM2576D2T–ADJR4


LM2576TV–3.3


LM2576T–3.3

50 Units/Rail

2500 Tape & Reel


LM2576D2T–3.3 LM2576D2TR4–3.3 LM2576TV–5

D2PAK

(Surface Mount)

D2PAK

(Surface Mount)

50 Units/Rail

2500 Tape & Reel

TO–220 (Vertical Mount) TJ = –40° 40° to +125°C

LM2576T–5

TO–220 (Straight Lead)

50V 5.0

LM2576D2T–5 LM2576D2TR4–5


LM2576TV–12


LM2576T–12

2500 Tape & Reel


12 V

LM2576D2T–12

D2PAK

LM2576TV–15


LM2576T–15

50 Units/Rail


50 Units/Rail

(Surface Mount)


15 V

50 Units/Rail


LM2576D2T–15

MARKING DIAGRAMS TO–220 TV SUFFIX CASE 314B





LM 2576–xxx AWLYWW

1 1

5

1

5

xxx A WL Y WW

= 3.3, 5.0, 12, 15, or ADJ = Assembly Location = Wafer Lot = Year = Work Week


5

LM 2576D2T–xxx AWLYWW

1

5

"#"

/ " "# $$0 The CS2001 is a smart power supply ASIC utilized in automotive airbag systems. It contains a current–mode switching regulator with a 1.2 A on–chip switch and a 5.0 V, 100 mA linear regulator. The linear output capacitor must be 3.3 µF or greater with an ESR in the range of 100 mΩ to 1.0 Ω. If the ESR of the cap is less than 100 mΩ, a series resistor must be used. The switcher can be configured in either a boost or flyback topology. The boost topology produces energy reserve voltage VER which is externally adjustable (25 V maximum) through the resistor divider connected to the VFB pin. In the event of fault conditions that produce VFB either open or shorted, the switcher is shut down. Under normal operating conditions (VBAT > 8.0 V), the current loading on the linear regulator is directed through VBAT. A low battery or loss of battery condition switches the supply for the linear regulator from VBAT to VER and shuts down the switcher using the ASIC’s internal “smartswitch.” This switchover feature minimizes the power dissipation in both the linear and switcher output devices and saves the cost of using a larger inductor. The NERD (No Energy Reserve Detected) pin is a dual function output. If VOUT is not in regulation, it provides a Power On Reset function whose time interval is externally adjustable with the capacitor. This interval can be seen on the RESETB pin, which allows for clean power–up and power–down of the microprocessor. Once VOUT is in regulation, the logic level of the NERD output (usually low) indicates to the microprocessor whether or not the VER pin is connected. A switched–capacitor voltage tripler accepts input voltage VER and produces output voltage VCHG (typically VER + 8.0 V). This voltage is used in the system to drive high–side FETs. This part is capable of withstanding a 50 V peak transient voltage. The linear regulator will not shut down during this event. Features Linear Regulator 5.0 V ±2% @ 100 mA Switching Regulator 1.2 A Peak Internal Switch Voltage Tripler Smart Functions – Smartswitch – RESET – Energy Reserve Status • Protection – Overtemperature – Current Limit – 50 V Peak Transient Capability • Internally Fused Leads in SO–20L Package

• • • •


December, 2000 – Rev. 5

http://onsemi.com

SO–20L DWF SUFFIX CASE 751D

20 1

MARKING DIAGRAM 20 CS2001 AWLYYWW 1 A WL, L YY, Y WW, W


PIN CONNECTIONS 1

20 VOUT RESETB NERD GND8 GND7 GND6 GND5 VCHG IBIAS CPUMP

VER VBAT VFB GND1 GND2 GND3 GND4 VSW SWSD COMP


1350

Package

Shipping

CS2001YDWF20

SO–20L

37 Units/Rail

CS2001YDWFR20

SO–20L

1000 Tape & Reel


CS2001

Microprocessor

100 µF 68 µH

VOUT RESETB NERD

VER VBAT VFB GND1 1.0 k

95.3 k

GND8

GND4

GND5

VSW

Reserve Firing Voltage

VCHG

SWSD

IBIAS

COMP

CPUMP

11 k VIGN

1000 µF

Tripler Firing Voltage 30.1 k

5.1 k 1000 µF

ESR

GND2 GND7 CS2001 GND3 GND6

270 pF 1.0 µF

0.1 µF

1.0 µF

0.47 µF

10 µF



Value

Unit

VBAT

–0.5 to 25

V

VER

–0.5 to 25

V

VOUT

–0.5 to 7.0

V

Digital Input/Output Voltage

–0.5 to 7.0

V

50

V

–55 to 150

°C

Junction to Free Air Thermal Impedance

55

°C/W


4.0

kV

230 peak

°C

TA

–40 to 85

°C

TJ

–40 to 150

°C

Peak Transient Voltage (36 V Load Dump @ 14 V Battery Voltage) Storage Temperature Range





CS2001 ELECTRICAL CHARACTERISTICS (8.0 V ≤ VBAT ≤ 16 V, 8.0 V ≤ VER ≤ 25 V, 1.0 mA ≤ IV(OUT) ≤ 100 mA, TTEST = –40°C to 125°C; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

4.9 4.9

– –

5.1 5.1

V V

Linear Regulator Output Voltage

Output Driven from VBAT, VER = 25 V Output Driven from VER, VBAT = 0 V

Regulator Bias Current (from VBAT)

IV(BAT) @ IV(OUT) = –100 mA, SWSD = 4.0 V, VBAT = 16 V, VER = 25 V T = –40°C T = 25°C T = 125°C

– – –

– – –

8.0 7.0 6.0

mA mA mA

IVER @ IV(OUT) = –100 mA, SWSD = 4.0 V, VBAT = 0 V, VER = 25 V T = –40°C T = 25°C T = 125°C

– – –

– – –

11 9.0 8.0

mA mA mA

Dropout Voltage VBAT – VOUT

VER = 25 V, IV(OUT) = –100 mA (Probe Only)

–

–

1.5

V

Dropout Voltage VER – VOUT

VBAT = 0 V, IV(OUT) = –100 mA

–

–

1.5

V

Smart Switch Threshold VBAT to VER

VER = 25 V, IV(OUT) = –50 mA

6.5

–

8.0

V

Smart Switch Threshold Hysteresis

VER = 25 V, IV(OUT) = –50 mA

0.5

–

1.0

V

VOUT Output Noise

VBAT = 16 V, VER = 25 V, IV(OUT) = – 1.0 mA, C = 10 µF, ESR = 0.5 Ω

–

–

0.05

V

Line Regulation

–

–

–

0.025

V

Load Regulation

–

–

–

0.025

V


–

120

–

–

mA

135

150

165

kHz

Regulator Bias Current (from VER)

Switching Regulator

VER = 25V, IV(OUT) = –1.0 mA

Switching Frequency

CPUMP 270 pF, RI(BIAS) = 30.1 kΩ

Pump Drive Current

∆IV(BAT) for 0 A ≤ IV(SW) ≤ 1.2 A

–

–

50

mA

Switch Saturation Voltage

IV(SW) = 1.2 A

–

–

1.6

V


–

1.2

–

2.4

A

VFB Regulation

–

1.238

1.27

1.303

V

–

–

1.0

µA

VFB Input Current

VFB Above Short Low Detection Level

VFB Input Shorted Low Detection Level

–

200

250

300

mV

CPUMP Short Detection Threshold

–

200

250

300

mV

Maximum Duty Cycle

–

80

–

95

%

–

–

100

µA

VSW Leakage Current Voltage Tripler

IV(SW) @ VSW = 50 V, SWSD = VOUT VBAT = 16 V, IV(OUT) = –1.0 mA, CCHG = 1.5 mF

Output Voltage Clamp VCHG – VER

VER = 8.0 V, IV(CHG) = –30 µA VER = 12 V, IV(CHG) = –90 µA

6.25 6.25

8.0 8.0

13 13

V V

Initial Charge Time

CCHG = 0.15 µF, VER = 8.0 V, VCHG = 14.25 V

–

–

30

ms

25

32.5

40

V

25

32.5

40

V

–

–

3.0

mA

Maximum Output Voltage Clamp VCHG Output Voltage Clamp VCHG Short Circuit Path Current Limit VER to VCHG

– VER = 28 V, IV(CHG) = 0 µA –


CS2001 ELECTRICAL CHARACTERISTICS (continued) (8.0 V ≤ VBAT ≤ 16 V, 8.0 V ≤ VER ≤ 25 V, 1.0 mA ≤ IV(OUT) ≤ 100 mA, TTEST = –40°C to 125°C; unless otherwise specified.) Characteristic RESETB OUTPUT

Test Conditions

Min

Typ

Max

Unit

VBAT = 0 V

High Threshold

VOUT Increasing

4.525

4.75

4.85

V

Low Threshold

VOUT Decreasing

4.5

4.65

4.825

V

25

100

200

mV

Hysteresis

–

Output Low Voltage

VOUT = 1.0 V, IRESETB = 100 µA IRESETB = 1.0 mA, VOUT = 4.5 V

– –

– –

0.5 0.5

V V

Pull–Up Resistor

RESETB = 1.0 V

25

50

100

kΩ

SWSD Input

VBAT = 16 V, VER = 25 V, IV(OUT) = –1.0 mA

High Threshold

–

–

–

0.7 × VOUT

V

Low Threshold

–

0.3 × VOUT

–

–

V

10

20

40

kΩ

1.5

–

6.5

V

Input Impedance NERD OUTPUT

Referenced to Ground VBAT = 16 V, IV(OUT) = –1.0 mA, CNERD = 0.47 mF –

VER Detection Voltage Output Low Voltage

INERD = 1.0 mA, VOUT = 4.5 V

–

–

0.5

V

Pull–Up Current

NERD = 0.5 V

30

40

50

µA

6.25

8.5

11

ms

Power On Delay

–

Clamping Voltage (Low)

VER Present

1.0

1.25

1.5

V

Clamping Voltage (High)

VER Not Present

3.5

3.75

4.0

V

– – –

– – –

5.0 5.0 4.0

mA mA mA

160

–

210

°C

General VER Load Current

Thermal Shutdown

VER = 25 V, VBAT = 16 V, IV(OUT) = –100 mA T = –40°C T = 25°C T = 125°C (Guaranteed by Design)

PACKAGE PIN DESCRIPTION PACKAGE PIN # SO–20L

PIN SYMBOL

1

VER

Energy reserve input.

2

VBAT

Battery input.

3

VFB

Charge PUMP control voltage input.

4

GND1

Ground.

5

GND2

Ground.

6

GND3

Ground.

7

GND4

Ground.

8

VSW

Charge PUMP switch collector.

9

SWSD

Charge PUMP shutdown input.

10

COMP

Charge PUMP compensation pin.

11

CPUMP

Charge PUMP timing cap input.

12

IBIAS

Reference current resistor pin.

FUNCTION


CS2001 PACKAGE PIN DESCRIPTION (continued) PACKAGE PIN # SO–20L

PIN SYMBOL

13

VCHG

Switched cap voltage tripler output.

14

GND5

Ground.

15

GND6

Ground.

16

GND7

Ground.

17

GND8

Ground.

18

NERD

No energy reserve detected output.

19

RESETB

20

VOUT

VER

FUNCTION

Reset output. Linear regulator output.

VREF V /C FB PUMP Short Detect

0.25 V – +

VFB

VCC Switcher – Error Amp + COMP

VCC + –

VSW Base Drive

Logic

VREF Bandgap 1.25 V Reference

VREF Over Temperature

NERD

GND

Switcher VCC Shutdown Comp – 0.5 × V CC +

Oscillator

VBAT

1.2 A

Current VCC Sense Amp + –

VCC

CPUMP

VCHG

Switcher V Comp REF

VREF IBIAS

Voltage Tripler

Preregulator

VREF Low Battery – Detect 7.25 V +

VREF

Linear VREF Error Amp + –

Logic

SWSD

No Battery Drive 100 mA

Current Limit

VOUT VER Detect

VCC VCC

RESETB Reset

Figure 2. Block Diagram http://onsemi.com 1354

CS2001 CIRCUIT DESCRIPTION Figure 3 is an oscilloscope waveform showing the charge pump collector voltage, collector current and the charge pump timing capacitor during normal operation with IVER = 30mA.

Figure 4 is an oscilloscope waveform showing the voltage tripler output and the energy reserve input during power up.

Figure 4. Startup with RV(CHG) = 510 k Figure 3. Typical Operation with IVER = 30 mA PACKAGE THERMAL DATA Parameter

SO–20L

Unit

RΘJC

Typical

9

°C/W

RΘJA

Typical

55

°C/W


"#" "#

/ " "# 1# $$0 $2$ The CS5111 is a dual output power supply integrated circuit. It contains a 5.0 V ± 2%, 100 mA linear regulator, a watchdog timer, a linear output voltage monitor to provide a Power On Reset (POR) and a 1.4 A current mode PWM switching regulator. The 5.0 V linear regulator is comprised of an error amplifier, reference, and supervisory functions. It has low internal supply current consumption and provides 1.2 V (typical) dropout voltage at maximum load current. The watchdog timer circuitry monitors an input signal (WDI) from the microprocessor. It responds to the falling edge of this watchdog signal. If a correct watchdog signal is not received within the externally programmable time, a reset signal is issued. The externally programmable active reset circuit operates correctly for an output voltage (VLIN) as low as 1.0 V. During power up, or if the output voltage shifts below the regulation limit, RESET toggles low and remains low for the duration of the delay after proper output voltage regulation is restored. Additionally a reset pulse is issued if the correct watchdog is not received within the programmed time. Reset pulses continue until the correct watchdog signal is received. The reset pulse width and frequency, as well as the Power On Reset delay, are set by one external RC network. The current mode PWM switching regulator is comprised of an error amplifier with selectable feedback inputs, a current sense amplifier, an adjustable oscillator, and a 1.4 A output power switch with anti–saturation control. The switching regulator can be configured in a variety of topologies. The CS5111 is load dump capable and has protection circuitry which includes overvoltage shutdown, current limit on the linear and switcher outputs, and an overtemperature limiter. Features • Linear Regulator – 5.0 V ± 2% @ 100 mA • Switching Regulator – 1.4 A Peak Internal Switch – 120 kHz Maximum Switching Frequency – 5.0 V to 26 V Operating Supply Range • Smart Functions – Watchdog – RESET – ENABLE • Protection – Overvoltage – Overtemperature – Current Limit • 54 V Peak Transient Capability • Internally Fused Leads in SO–24L Package  Semiconductor Components Industries, LLC, 2001


1356

http://onsemi.com SO–24L DWF SUFFIX CASE 751E

24 1



PIN CONNECTIONS VIN NC NC VSW GND GND GND GND VFB1 VFB2 SELECT COMP

1

24

ENABLE VREG VLIN IBIAS GND GND GND GND RESET CDelay WDI COSC


Package

Shipping

CS5111YDWF24

SO–24L

31 Units/Rail

CS5111YDWFR24

SO–24L

1000 Tape & Reel


CS5111 VIN

Switcher Error Amplifier

VFB1 VFB2 SELECT

Multiplexer

– +

VSW COMP

Base Drive

Logic

COMP Current Sense Amplifier

IBIAS

1.4 A

+ –

GND

Oscillator

COSC

+ –

Switcher Shutdown

ENABLE

VREG Overvoltage + –

Linear Error Amplifier

VLIN Current Limit

Bandgap Reference

Over Temperature

1.25 V

RESET RESET & Watchdog Timer

CDELAY WDI


ABSOLUTE MAXIMUM RATINGS* Rating Logic Inputs/Outputs (ENABLE, SELECT, WDI, RESET) VLIN VIN, VREG:

Value

Unit

–0.3 to VLIN

V

–0.3 to 10 DC Input Voltage Peak Transient Voltage (40 V Load Dump @ 14 V VIN)

–0.3 to 26 –0.3 to 54

V V

54

V

–0.3 to VLIM

V

Power Dissipation

Internally Limited

–

VLIN Output Current

Internally Limited

–

VSW Output Current

Internally Limited

–

RESET Output Sink Current

5.0

mA


2.0

kV


200

V

–65 to 150

°C

230 peak

°C

VSW Peak Transient Voltage COSC, CDelay, COMP, VFB1, VFB2

Storage Temperature Lead Temperature Soldering:




CS5111 ELECTRICAL CHARACTERISTICS (5.0 V ≤ VIN ≤ 26 V and –40°C ≤ TJ ≤ 150°C, COUT = 100 µF (ESR ≤ 8.0 Ω), CDelay = 0.1 µF, RBIAS = 64.9 kΩ, COSC = 390 pF, CCOMP = 0.1 µF; unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit

General IIN Off Current

6.6 V ≤ VIN ≤ 26 V, ISW = 0 A

–

–

2.0

mA

IIN On Current

6.6 V ≤ VIN ≤ 26 V, ISW = 1.4 A

–

30

70

mA

IREG Current

ILIN = 100 mA, 6.6 V ≤ VIN ≤ 26 V

–

–

6.0

mA

Thermal Limit


160

–

210

°C

VLIN Output Voltage

6.6 V ≤ VREG ≤ 26 V, 1.0 mA ≤ ILIN ≤ 100 mA

4.9

5.0

5.1

V

Dropout Voltage

(VREG – VLIN) @ ILIN = 100 mA

–

1.2

1.5

V

30

34

38

V

5.0 V Regulator Section


–

Line Regulation

6.6 V ≤ VREG ≤ 26 V, ILIN = 5.0 mA

–

5.0

25

mV

Load Regulation

VREG = 19 V, 1.0 mA ≤ ILIN ≤ 100 mA

–

5.0

25

mV

Current Limit

6.6 V ≤ VREG ≤ 26 V

120

–

–

mA

DC Ripple Rejection

14 V ≤ VREG ≤ 24 V

60

75

–

dB

RESET Section Low Threshold (VRTL)

VLIN Decreasing

4.05

4.25

4.45

V

High Threshold (VRTH)

VLIN Increasing

4.2

4.45

4.7

V

Hysteresis

VRTH – VRTL

140

190

240

mV

Active High

VLIN > VRTH, IRESET = –25 µA

VLIN – 0.5

–

–

V

Active Low

VLIN = 1.0 V, 10 kΩ Pull–Up from RESET to VLIN VLIN = 4.0 V, IRESET = 1.0 mA

–

–

0.4

V

–

–

0.7

V

Delay

Invalid WDI

6.25

8.78

11

ms

Power On Delay

VLIN Crossing VRTH

6.25

–

–

ms

–

–

2.0

V

0.8

–

–

V

Watchdog Input (WDI) VIH

Peak WDI Needed to Activate RESET

VIL

–

Hysteresis

Note 2

25

50

–

mV

Pull–Up Resistor

WDI = 0 V

20

50

100

kΩ

Low Threshold

–

6.25

8.78

11

ms

Floating Input Voltage

–

3.5

–

–

V

WDI Pulse Width

–

–

–

5.0

µs

–

–

–

5.0

V

Switcher Section Minimum Operating Input Voltage Switching Frequency

Refer to Figure 5

80

95

110

kHz


ISW = 1.4 A

0.7

1.1

1.6

V

1.4

–

2.5

A

120

–

–

kHz

Output Current Limit Max Switching Frequency

– VSW = 7.5 V with 50 Ω Load, Refer to Figure 5

2. Guaranteed by design, not 100% tested in productions.


CS5111 ELECTRICAL CHARACTERISTICS (continued) (5.0 V ≤ VIN ≤ 26 V and –40°C ≤ TJ ≤ 150°C, COUT = 100 µF (ESR ≤ 8.0 Ω), CDelay = 0.1 µF, RBIAS = 64.9 kΩ, COSC = 390 pF, CCOMP = 0.1 µF; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

VFB1 Regulation Voltage

–

1.206

1.25

1.294

V

VFB2 Regulation Voltage

–

1.206

1.25

1.294

V

Switcher Section (continued)

VFB1, VFB2 Input Current

VFB1 = VFB2 = 5.0 V

–

–

1.0

µA

Oscillator Charge Current

COSC = 0 V

35

40

45

µA

Oscillator Discharge Current

COSC = V40

270

320

370

µA

CDelay Charge Current

CDelay = 0 V

35

40

45

µA

Switcher Max Duty Cycle

VSW = 5.0 V with 50 Ω Load, VFB1 = VFB2 = 1.0 V

72

85

95

%

Current Sense Amp Gain

ISW = 2.3 A

–

7.0

–

V/V

Error Amp DC Gain

–

–

67

–

dB

Error Amp Transconductance

–

–

2700

–

µA/V

VIL

–

0.8

1.24

–

V

VIH

–

–

1.3

2.0

V

Hysteresis

–

–

60

–

mV

Input Impedance

–

10

20

40

kΩ

ENABLE Input

Select Input VIL (Selects VFB1)

4.9 ≤ VLIN ≤ 5.1

0.8

1.25

–

V

VIH (Selects VFB2)

4.9 ≤ VLIN ≤ 5.1

–

1.25

2.0

V

SELECT Pull–Up

SELECT = 0 V

10

24

50

kΩ

3.5

4.5

–

V


–

PIN FUNCTION DESCRIPTION PACKAGE PIN # SO–24L

PIN SYMBOL

1

VIN

Supply voltage.

2, 3

NC

No connection.

4

VSW

Collector of NPN power switch for switching regulator section.

5, 6, 7, 8, 17, 18, 19, 20

GND

Connected to the heat removing leads.

9

VFB1

Feedback input voltage 1 (referenced to 1.25 V).

10

VFB2


11

SELECT

12

COMP

Output of the transconductance error amplifier.

13

COSC

A capacitor connected to GND sets the switching frequency. Refer to Figure 5.

14

WDI

Watchdog input. Active on falling edge.

15

CDelay

A capacitor connected to GND sets the Power On Reset and Watchdog time.

16

RESET

RESET output. Active low if VLIN is below the regulation limit. If watchdog timeout is reached, a reset pulse train is issued.

FUNCTION

Logic level input that selects either VFB1 or VFB2. An open selects VFB2. Connect to GND to select VFB1.


CS5111 PIN FUNCTION DESCRIPTION (continued) PACKAGE PIN # SO–24L

PIN SYMBOL

21

IBIAS

A resistor connected to GND sets internal bias currents as well as the COSC and CDelay charge currents.

22

VLIN

Regulated 5.0 V output from the linear regulator section.

23

VREG

Input voltage to the linear regulator and the internal supply circuitry.

24

ENABLE

FUNCTION

Logic level input to shut down the switching regulator.


–10 IIN (mA)

IREG – ILIN (mA)

4.5

4.0

–20

–30

3.5

0

20

60

40

80

–40

100

0

0.5

1.5

1.0

ILIN (mA)

2.0

ISW (A)

Figure 2. 5.0 V Regulator Bias Current vs. Load Current

Figure 3. Supply Current vs. Switch Current

1.4

180 160

1.2

140 Frequency (kHz)

VSW (V)

1.0 0.8 0.6 0.4

120 100 80 60 40

0.2 0

20 0

0.5

1.0

1.5

2.0

0

0

ISW (A)

500

1000

1500

2000

2500

COSC (pF)


Figure 5. Oscillator Frequency (kHz) vs. COSC (pF), Assuming RBIAS = 64.9 kW


3000

CS5111 CIRCUIT DESCRIPTION VREG Overvoltage + –

R1 Linear Error Amplifier

Q2 Q3

Q1

VLIN COUT = 100 µF ESR < 8.0 Ω

R2

Current Limit

R3 IBIAS

Bandgap Reference

RBIAS 64.9 kΩ

1.25 V

Over Temperature

R4 R5

CDelay

RESET & Watchdog Timer

RESET

WDI

Figure 6. Block Diagram of 5.0 V Linear Regulator Portion of the CS5111 5.0 V LINEAR REGULATOR

CONTROL FUNCTIONS

The 5.0 V linear regulator consists of an error amplifier, bandgap voltage reference, and a composite pass transistor. The 5.0 V linear regulator circuitry is shown in Figure 6. When an unregulated voltage greater than 6.6 V is applied to the VREG input, a 5.0 V regulated DC voltage will be present at VLIN. For proper operation of the 5.0 V linear regulator, the IBIAS lead must have a 64.9 kΩ pull down resistor to ground. A 100 µF or larger capacitor with an ESR < 8.0 Ω must be connected between VLIN and ground. To operate the 5.0 V linear regulator as an independent regulator (i.e. separate from the switching supply), the input voltage must be tied to the VREG lead. As the voltage at the VREG input is increased, Q1 is turned on. Q1 provides base drive for Q2 which in turn provides base current for Q3. As Q3 is turned on, the output voltage, VLIN, begins to rise as Q3’s output current charges the output capacitor, COUT. Once VLIN rises to a certain level, the error amplifier becomes biased and provides the appropriate amount of base current to Q1. The error amplifier monitors the scaled output voltage via an internal voltage divider, R2 through R5, and compares it to the bandgap voltage reference. The error amplifier output or error signal is an output current equal to the error amplifier’s input differential voltage times the transconductance of the amplifier. Therefore, the error amplifier varies the base current to Q1, which provides bias to Q2 and Q3, based on the difference between the reference voltage and the scaled VLIN output voltage.

The watchdog timer circuitry monitors an input signal (WDI) from the microprocessor. It responds to the falling edge of this watchdog signal which it expects to see within an externally programmable time (see Figure 7). The watchdog time is given by: tWDI + 1.353

CDelayRBIAS

Using CDelay = 0.1 µF and RBIAS = 64.9 kΩ gives a time ranging from 6.25 ms to 11 ms assuming ideal components. Based on this, the software must be written so that the watchdog arrives at least every 6.25 ms. In practice, the tolerance of CDelay and RBIAS must be taken into account when calculating the minimum watchdog time (tWDI).

VREG

RESET

WDI

VLIN tPOR

Normal Operation

Figure 7. Timing Diagram for Normal Regulator Operation


CS5111 VLIN

If a correct watchdog signal is not received within the specified time a reset pulse train is issued until the correct watchdog signal is received. The nominal reset signal in this case is a 5 volt square wave with a 50% duty cycle as shown in Figure 8.

5.0 V 4.25 V

RESET

50% Duty Cycle

VREG

5.0 V

RESET tPOR

WDI

Figure 10. RESET Signal Is Issued Whenever VLIN Falls Below 4.25 V (Typical)

VLIN

The POR delay (tPOR) is given by: tPOR

A

tPOR + 1.353

B

A: Watchdog waiting for low–going transition on WDI B: RESET stays low for tWDI time

CDelayRBIAS

CURRENT MODE PWM SWITCHING CIRCUITRY

The current mode PWM switching voltage regulator contains an error amplifier with selectable feedback inputs, a current sense amplifier, an adjustable oscillator and a 1.4 A output power switch with antisaturation control. The switching regulator and external components, connected in a boost configuration, are shown in Figure 11. The switching regulator begins operation when VREG and VIN are raised above 5 volts. VREG is required since the switching supply’s control circuitry is powered through VLIN. VIN supplies the base drive to the switcher output transistor. The output transistor turns on when the oscillator starts to charge the capacitor on COSC. The output current will develop a voltage drop across the internal sense resistor (RS). This voltage drop produces a proportional voltage at the output of the current sense amplifier, which is compared to the output of the error amplifier. The error amplifier generates an output voltage which is proportional to the difference between the scaled down output boost voltage (VFB1 or VFB2) and the internal bandgap voltage reference. Once the current sense amplifier output exceeds the error amplifier’s output voltage, the output transistor is turned off. The energy stored in the inductor during the output transistor on time is transferred to the load when the output transistor is turned off. The output transistor is turned back

Figure 8. Timing Diagram When WDI Fails to Appear Within the Preset Time Interval, tWDI

The RESET signal frequency is given by: 1 fRESET + 2(tWDI)

The Power On Reset (POR) and low voltage RESET use the same circuitry and issue a reset when the linear output voltage is below the regulation limit. After VLIN rises above the minimum specified value, RESET remains low for a fixed period tPOR as shown in Figures 9 and 10. VLIN 4.45 V 4.25 V

RESET VR(LO) VR(PEAK) tPOR

Figure 9. The Power On Reset Time Interval (tPOR) Begins When VLIN Rises Above 4.45 V (Typical)


CS5111 on at the next rising edge of the oscillator. On a cycle by cycle basis, the current mode controller in a discontinuous mode of operation charges the inductor to the appropriate amount of energy, based on the energy demand of the load. Figure 12 shows the typical current and voltage waveforms for a boost supply operating in the discontinuous mode.

2. The switching regulator can be disabled by providing a logic high at the ENABLE input. 3. The boost output voltage can be controlled dynamically by the feedback select input. If select is open, VFB2 is selected. If select is low, then VFB1 is selected.

Notes:

1. Refer to Figure 5 to determine oscillator frequency. VIN VLIN VOUT VSW

COMP

IBIAS RBIAS 64.9 kΩ

Base Drive

Logic

Current Sense Amplifier

COSC Oscillator ENABLE VREG

+ –

RS

COMP


Bandgap Reference R1

VFB1 – +

GND

+ – Switcher Shutdown 1.25 V

Overvoltage

COUT

1.4 A

Multiplexer

R2

VFB2

R3 SELECT

Figure 11. Block Diagram of the 1.4 A Current Mode Control Switching Regulator Portion of the CS5111 in a Boost Configuration


CS5111 PROTECTION CIRCUITRY

VSW

If the input voltage at VREG is increased above the overvoltage threshold, the drive to the linear and switcher output transistors is shut off. Therefore, VLIN is disabled and VSW can not be pulled low. The current out of VLIN is sensed in order to limit excessive power dissipation in the linear output transistor over the output range of 0 V to regulation. Also, the current into VSW is sensed in order to provide the current limit function in the switcher output transistor. If the die temperature is increased above 160°C, either due to excessive ambient temperature or excessive power dissipation, the drive to the linear output transistor is reduced proportionally with increasing die temperature. Therefore, VLIN will decrease with increasing die temperature above 160°C. Since the switcher control circuitry is powered through VLIN, the switcher performance, including current limit, will be affected by the decrease in VLIN.

VOUT

VIN

VSAT 0

t

ISW IPeak

t

0 ID IPeak

t

0

Figure 12. Voltage and Current Waveforms for Boost Topology in CS5111


CS5111 APPLICATION NOTES VINtON + (VOUT * VIN)tOFF

DESIGN PROCEDURE FOR BOOST TOPOLOGY

This section outlines a procedure for designing a boost switching power supply operating in the discontinuous mode.

where the maximum on time is:

ƪ

VIN(MIN) tON(MAX) [ 1 * VOUT(MAX)

Step 1

Determine the output power required by the load. POUT + IOUTVOUT

1 ƫƪfSW(MIN) ƫ

(7)

Step 5

(1)

Calculate the maximum inductance allowed for discontinuous operation:

Step 2

Choose COSC based on the target oscillator frequency with an external resistor value, RBIAS = 64.9 kΩ. (See Figure 5).

2 f V 2 t L(MAX) + SW(MIN) IN (MIN) ON (MAX) 2POUTń

Step 3

(8)

where η = efficiency. Usually η = 0.75 is a good starting point. The IC’s power dissipation should be calculated after the peak current has been determined in Step 6. If the efficiency is less than originally assumed, decrease the efficiency and recalculate the maximum inductance and peak current.

Next select the output voltage feedback sense resistor divider as follows (Figure 13). For VFB1 active, choose a value for R1 and then solve for REQ where: R REQ + VOUT 1 *1 V

(6)

(2)

FB1

Step 6

For VFB2 active, find:

ǒ

REQ VFB1 + VOUT R1 ) REQ

Ǔ

Determine the peak inductor current at the minimum inductance, minimum VIN and maximum on time to make sure the inductor current doesn’t exceed 1.4 A.

(3)

and then calculate R2 where: V V * VFB2 R2 + R2 + FB1 IR2 VFB1ńREQ

V t IPK + IN(MIN) ON(MAX) L(MIN)

(4)

Step 7

Then find R3, where: R3 + REQ * R2

Determine the minimum output capacitance and maximum ESR based on the allowable output voltage ripple.

(5)

COUT(MIN) +

VOUT

ESR(MIN) +

R1 VFB1 VR2

IPK 8fVRIPPLE

(10)

VRIPPLE IPK

(11)

In practice, it is normally necessary to use a larger capacitance value to obtain a low ESR. By placing capacitors in parallel, the equivalent ESR can be reduced.

R2 VFB2

REQ

(9)

Step 8

Compensate the feedback loop to guarantee stability under all operating conditions. To do this, we calculate the modulator gain and the feedback resistor network attenuation and set the gain of the error amplifier so that the overall loop gain is 0 dB at the crossover frequency, fCO. In addition, the gain slope should be –20 dB/decade at the crossover frequency. The low frequency gain of the modulator (i.e. error amplifier output to output voltage) is:

R3

Figure 13. Feedback Sense Resistor Divider Connected Between VOUT and Ground Step 4

Determine the maximum on time at the minimum oscillator frequency and VIN. For discontinuous operation, all of the stored energy in the inductor is transferred to the load prior to the next cycle. Since the current through the inductor cannot change instantaneously and the inductance is constant, a volt–second balance exists between the on time and off time. The voltage across the inductor during the on cycle is VIN and the voltage across the inductor during the off cycle is VOUT – VIN. Therefore:

IPK(MAX) VOUT + VEA(MAX) VEA

Lf ǸRLOAD 2

(12)

where: V ńG 2.4 Vń7 IPK(MAX) + EA(MAX) CSA + + 2.3 A (13) 150 m RS

The VOUT/VEA transfer function has a pole at:


CS5111 fp + 1ń(RLOADCOUT)

VOUT

(14)

and a zero due to the output capacitor’s ESR at:

R1

fz + 1ń(2ESR(COUT))

Since the error amplifier reference voltage is 1.25 V, the output voltage must be divided down or attenuated before being applied to the input of the error amplifier. The feedback resistor divider attenuation is:

1.25 V

VFB1

(15) R2

M U X

VFB2

– Error Amplifier

R3

1.25 V VOUT

+ C1

C2

R4

The error amplifier in the CS5111 is an operational transconductance amplifier (OTA), with a gain given by: GOTA + gmZOUT

SELECT

(16)

Figure 14. RC Network Used to Compensate the Error Amplifier (OTA)

where: gm +

IOUT VIN

(17)

A pole at point C:

For the CS5111, gm = 2700 µA/V typical. One possible error amplifier compensation scheme is shown in Figure 14. This gives the error amplifier a gain plot as shown in Figure 15. For the error amplifier gain shown in Figure 15, a low frequency pole is generated by the error amplifier output impedance and C1 . This is shown by the line AB with a –20 dB/decade slope in Figure 15. The slope changes to zero at point B due to the zero at: fz + 1ń(2R4C1)

fp + 1ń(R4C2)

offsets the zero set by the ESR of the output capacitors. An alternative scheme uses a single capacitor as shown in Figure 16, to roll the gain off at a relatively low frequency. Step 9

Finally the watchdog timer period and Power on Reset time is determined by: tDelay + 1.353

(18)

CDelayRBIAS

Pole due to error amplifier output impedance and C1 G A

fz = 1/(2πR4C1)

fp = 1/(πR4C2) +G

C

B error amplifier gain Gain (dB)

(19)

–20 dB/dec

fp = 1/(πRLOADCOUT) fCO 0 modulator gain + feedback resistor divider attenuation –G

fz = 1/(2πESR(COUT))

Figure 15. Bode Plot of Error Amplifier (OTA) Gain and Modulator Gain Added to the Feedback Resistor Divider Attenuation


(20)

CS5111 VIN

VOUT = 18 V, Select > 2.0 V VOUT = 16 V, Select < 0.8 V

L = 33 µH

COUT 88 µF

VIN

ENABLE

NC

VREG

NC

VLIN

VSW

IBIAS

GND

GND

(2)

GND

5.0 V 100 µF ESR < 8.0 Ω RBIAS 64.9 kΩ

GND CS5111

R1 100 kΩ

R2 946 Ω

GND

GND

GND

GND

VFB1

RESET

VFB2

CDelay

Microprocessor

(1)

R3 7.5 kΩ

SELECT COMP

CDelay 0.1 µF

WDI COSC COSC 390 pF

CCOMP 0.33 µF

Figure 16. A Typical Application Diagram with External Components Configured in a Boost Topology


CS5111 LINEAR REGULATOR OUTPUT CURRENT VS. INPUT VOLTAGE

100 ILIN (mA)

ILIN (mA)

100

75 ΘJA = 55°C/W VIN = 14 V Max Total Power = 1.18 W

50

25

0


50

25

0

5

10

15

20

25

0

30

0

5

10

VREG (V)

15

20

25

30

VREG (V)

Figure 17. The Shaded Area Shows the Safe Operating Area of the CS5111 as a Function of ILIN, VREG, and QJA. Refer to Table 4 for Typical Loads and Voltages.

Table 4. Worst Case Switcher Power Available (ΘJA = 55°C/W) (W)

Worst Case Switcher Power Available (ΘJA = 35°C/W) (W)

VREG (V)

VIN (V)

ILIN (mA)

Linear Power Dissipation (W)

20

14

25

0.44

0.74

1.42

20

14

50

0.83

0.35

1.03

20

14

75

1.22

*

0.64

20

14

100

1.60

*

0.26

25

14

25

0.60

0.58

1.26

25

14

50

1.11

0.07

0.75

25

14

75

1.62

*

0.24

25

14

100

2.14

*

*

*Subjecting the CS5111 to these conditions will exceed the maximum total power that the part can handle, thereby forcing it into thermal limit. PACKAGE THERMAL DATA Parameter

SO–24L

Unit

RΘJC

Typical

9

°C/W

RΘJA

Typical

55

°C/W


"#" "#

/ " "# 1# $$0 $2$ The CS5112 is a dual output power supply integrated circuit. It contains a 5.0 V ± 2%, 100 mA linear regulator, a watchdog timer, a linear output voltage monitor to provide a Power On Reset (POR) and a 1.4 A current mode PWM switching regulator. The 5.0 V linear regulator is comprised of an error amplifier, reference, and supervisory functions. It has low internal supply current consumption and provides 1.2 V (typical) dropout voltage at maximum load current. The watchdog timer circuitry monitors an input signal (WDI) from the microprocessor. It responds to the falling edge of this watchdog signal. If a correct watchdog signal is not received within the externally programmable time, a reset signal is issued. The externally programmable active reset circuit operates correctly for an output voltage (VLIN) as low as 1.0 V. During power up, or if the output voltage shifts below the regulation limit, RESET toggles low and remains low for the duration of the delay after proper output voltage regulation is restored. Additionally a reset pulse is issued if the correct watchdog is not received within the programmed time. Reset pulses continue until the correct watchdog signal is received. The reset pulse width and frequency, as well as the Power On Reset delay, are set by one external RC network. The current mode PWM switching regulator is comprised of an error amplifier with selectable feedback inputs, a current sense amplifier, an adjustable oscillator, and a 1.4 A output power switch with anti–saturation control. The switching regulator can be configured in a variety of topologies. The CS5112 is load dump capable and has protection circuitry which includes current limit on the linear and switcher outputs, and an overtemperature limiter. Features • Linear Regulator – 5.0 V ± 2% @ 100 mA • Switching Regulator – 1.4 A Peak Internal Switch – 120 kHz Maximum Switching Frequency – 5.0 V to 26 V Operating Supply Range • Smart Functions – Watchdog – RESET – ENABLE • Protection – Overtemperature – Current Limit • Internally Fused Leads in SO–24L Package



http://onsemi.com SO–24L DWF SUFFIX CASE 751E

24 1



PIN CONNECTIONS VIN NC NC VSW GND GND GND GND VFB1 VFB2 SELECT COMP

1

24

ENABLE VREG VLIN IBIAS GND GND GND GND RESET CDelay WDI COSC


1369

Package

Shipping

CS5112YDWF24

SO–24L

31 Units/Rail

CS5112YDWFR24

SO–24L

1000 Tape & Reel


CS5112 VIN


VFB1 VFB2 SELECT

Multiplexer

– +

VSW COMP

Base Drive

Logic

COMP Current Sense Amplifier

IBIAS

1.4 A

+ –

GND

Oscillator

COSC

+ –

Switcher Shutdown

ENABLE

VREG

+ –

Linear Error Amplifier

VLIN Current Limit

Bandgap Reference

Over Temperature

1.25 V

RESET RESET & Watchdog Timer

CDELAY WDI


ABSOLUTE MAXIMUM RATINGS* Rating Logic Inputs/Outputs (ENABLE, SELECT, WDI, RESET) VLIN VIN, VREG:

Value

Unit

–0.3 to VLIN

V

–0.3 to 10 DC Input Voltage Peak Transient Voltage (26 V Load Dump @ 14 V VIN)

–0.3 to 26 –0.3 to 40

V V

54

V

–0.3 to VLIM

V

Power Dissipation

Internally Limited

–

VLIN Output Current

Internally Limited

–

VSW Output Current

Internally Limited

–

RESET Output Sink Current

5.0

mA


2.0

kV


200

V

–65 to 150

°C

230 peak

°C

VSW Peak Transient Voltage COSC, CDelay, COMP, VFB1, VFB2

Storage Temperature Lead Temperature Soldering:




CS5112 ELECTRICAL CHARACTERISTICS (5.0 V ≤ VIN ≤ 26 V and –40°C ≤ TJ ≤ 150°C, COUT = 100 µF (ESR ≤ 8.0 Ω), CDelay = 0.1 µF, RBIAS = 64.9 kΩ, COSC = 390 pF, CCOMP = 0.1 µF; unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit

General IIN Off Current

6.6 V ≤ VIN ≤ 26 V, ISW = 0 A

–

–

2.0

mA

IIN On Current

6.6 V ≤ VIN ≤ 26 V, ISW = 1.4 A

–

30

70

mA

IREG Current

ILIN = 100 mA, 6.6 V ≤ VIN ≤ 26 V

–

–

6.0

mA

Thermal Limit


160

–

210

°C

VLIN Output Voltage

6.6 V ≤ VREG ≤ 26 V, 1.0 mA ≤ ILIN ≤ 100 mA

4.9

5.0

5.1

V

Dropout Voltage

(VREG – VLIN) @ ILIN = 100 mA

–

1.2

1.5

V

Line Regulation

6.6 V ≤ VREG ≤ 26 V, ILIN = 5.0 mA

–

5.0

25

mV

Load Regulation

VREG = 19 V, 1.0 mA ≤ ILIN ≤ 100 mA

–

5.0

25

mV

Current Limit

6.6 V ≤ VREG ≤ 26 V

120

–

–

mA

DC Ripple Rejection

14 V ≤ VREG ≤ 24 V

60

75

–

dB

5.0 V Regulator Section

RESET Section Low Threshold (VRTL)

VLIN Decreasing

4.05

4.25

4.45

V

High Threshold (VRTH)

VLIN Increasing

4.2

4.45

4.7

V

Hysteresis

VRTH – VRTL

140

190

240

mV

Active High

VLIN > VRTH, IRESET = –25 µA

VLIN – 0.5

–

–

V

Active Low

VLIN = 1.0 V, 10 kΩ Pull–Up from RESET to VLIN VLIN = 4.0 V, IRESET = 1.0 mA

–

–

0.4

V

–

–

0.7

V

Delay

Invalid WDI

6.25

8.78

11

ms

Power On Delay

VLIN Crossing VRTH

6.25

–

–

ms

–

–

2.0

V

0.8

–

–

V

Watchdog Input (WDI) VIH

Peak WDI Needed to Activate RESET

VIL

–

Hysteresis

Note 2

25

50

–

mV

Pull–Up Resistor

WDI = 0 V

20

50

100

kΩ

Low Threshold

–

6.25

8.78

11

ms


–

3.5

–

–

V

WDI Pulse Width

–

–

–

5.0

µs

–

–

–

5.0

V

Switcher Section Minimum Operating Input Voltage Switching Frequency

Refer to Figure 5

80

95

110

kHz


ISW = 1.4 A

0.7

1.1

1.6

V

1.4

–

2.5

A

120

–

–

kHz

1.206

1.25

1.294

V

Output Current Limit Max Switching Frequency VFB1 Regulation Voltage

– VSW = 7.5 V with 50 Ω Load, Refer to Figure 5 –

2. Guaranteed by design, not 100% tested in productions.


CS5112 ELECTRICAL CHARACTERISTICS (continued) (5.0 V ≤ VIN ≤ 26 V and –40°C ≤ TJ ≤ 150°C, COUT = 100 µF (ESR ≤ 8.0 Ω), CDelay = 0.1 µF, RBIAS = 64.9 kΩ, COSC = 390 pF, CCOMP = 0.1 µF; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

–

1.206

1.25

1.294

V

Switcher Section (continued) VFB2 Regulation Voltage VFB1, VFB2 Input Current

VFB1 = VFB2 = 5.0 V

–

–

1.0

µA

Oscillator Charge Current

COSC = 0 V

35

40

45

µA

Oscillator Discharge Current

COSC = V40

270

320

370

µA

CDelay Charge Current

CDelay = 0 V

35

40

45

µA

Switcher Max Duty Cycle

VSW = 5.0 V with 50 Ω Load, VFB1 = VFB2 = 1.0 V

72

85

95

%

Current Sense Amp Gain

ISW = 2.3 A

–

7.0

–

V/V

Error Amp DC Gain

–

–

67

–

dB

Error Amp Transconductance

–

–

2700

–

µA/V

VIL

–

0.8

1.24

–

V

VIH

–

–

1.3

2.0

V

Hysteresis

–

–

60

–

mV

Input Impedance

–

10

20

40

kΩ

ENABLE Input

Select Input VIL (Selects VFB1)

4.9 ≤ VLIN ≤ 5.1

0.8

1.25

–

V

VIH (Selects VFB2)

4.9 ≤ VLIN ≤ 5.1

–

1.25

2.0

V

SELECT Pull–Up

SELECT = 0 V

10

24

50

kΩ

3.5

4.5

–

V


–

PIN FUNCTION DESCRIPTION PACKAGE PIN # SO–24L

PIN SYMBOL

1

VIN

Supply voltage.

2, 3

NC

No connection.

4

VSW

Collector of NPN power switch for switching regulator section.

5, 6, 7, 8, 17, 18, 19, 20

GND

Connected to the heat removing leads.

9

VFB1


10

VFB2


11

SELECT

12

COMP

Output of the transconductance error amplifier.

13

COSC

A capacitor connected to GND sets the switching frequency. Refer to Figure 5.

14

WDI

Watchdog input. Active on falling edge.

15

CDelay

A capacitor connected to GND sets the Power On Reset and Watchdog time.

16

RESET

RESET output. Active low if VLIN is below the regulation limit. If watchdog timeout is reached, a reset pulse train is issued.

21

IBIAS

FUNCTION

Logic level input that selects either VFB1 or VFB2. An open selects VFB2. Connect to GND to select VFB1.

A resistor connected to GND sets internal bias currents as well as the COSC and CDelay charge currents.


CS5112 PIN FUNCTION DESCRIPTION (continued) PACKAGE PIN # SO–24L

PIN SYMBOL

22

VLIN

Regulated 5.0 V output from the linear regulator section.

23

VREG

Input voltage to the linear regulator and the internal supply circuitry.

24

ENABLE

FUNCTION

Logic level input to shut down the switching regulator.


–10 IIN (mA)

IREG – ILIN (mA)

4.5

4.0

–20

–30

3.5

0

20

60

40

80

–40

100

0

0.5

1.5

1.0

ILIN (mA)

2.0

ISW (A)

Figure 2. 5.0 V Regulator Bias Current vs. Load Current

Figure 3. Supply Current vs. Switch Current

1.4

180 160

1.2

140 Frequency (kHz)

VSW (V)

1.0 0.8 0.6 0.4

120 100 80 60 40

0.2 0

20 0

0.5

1.0

1.5

2.0

0

0

ISW (A)

500

1000

1500

2000

2500

COSC (pF)


Figure 5. Oscillator Frequency (kHz) vs. COSC (pF), Assuming RBIAS = 64.9 kW


3000

CS5112 CIRCUIT DESCRIPTION VREG

+ –

R1 Linear Error Amplifier

Q2 Q3

Q1

VLIN COUT = 100 µF ESR < 8.0 Ω

R2

Current Limit

R3 IBIAS

Bandgap Reference

RBIAS 64.9 kΩ

1.25 V

Over Temperature

R4 R5

CDelay

RESET & Watchdog Timer

RESET

WDI

Figure 6. Block Diagram of 5.0 V Linear Regulator Portion of the CS5112 5.0 V LINEAR REGULATOR

CONTROL FUNCTIONS

The 5.0 V linear regulator consists of an error amplifier, bandgap voltage reference, and a composite pass transistor. The 5.0 V linear regulator circuitry is shown in Figure 6. When an unregulated voltage greater than 6.6 V is applied to the VREG input, a 5.0 V regulated DC voltage will be present at VLIN. For proper operation of the 5.0 V linear regulator, the IBIAS lead must have a 64.9 kΩ pull down resistor to ground. A 100 µF or larger capacitor with an ESR < 8.0 Ω must be connected between VLIN and ground. To operate the 5.0 V linear regulator as an independent regulator (i.e. separate from the switching supply), the input voltage must be tied to the VREG lead. As the voltage at the VREG input is increased, Q1 is turned on. Q1 provides base drive for Q2 which in turn provides base current for Q3. As Q3 is turned on, the output voltage, VLIN, begins to rise as Q3’s output current charges the output capacitor, COUT. Once VLIN rises to a certain level, the error amplifier becomes biased and provides the appropriate amount of base current to Q1. The error amplifier monitors the scaled output voltage via an internal voltage divider, R2 through R5, and compares it to the bandgap voltage reference. The error amplifier output or error signal is an output current equal to the error amplifier’s input differential voltage times the transconductance of the amplifier. Therefore, the error amplifier varies the base current to Q1, which provides bias to Q2 and Q3, based on the difference between the reference voltage and the scaled VLIN output voltage.

The watchdog timer circuitry monitors an input signal (WDI) from the microprocessor. It responds to the falling edge of this watchdog signal which it expects to see within an externally programmable time (see Figure 7). The watchdog time is given by: tWDI + 1.353

CDelayRBIAS

Using CDelay = 0.1 µF and RBIAS = 64.9 kΩ gives a time ranging from 6.25 ms to 11 ms assuming ideal components. Based on this, the software must be written so that the watchdog arrives at least every 6.25 ms. In practice, the tolerance of CDelay and RBIAS must be taken into account when calculating the minimum watchdog time (tWDI).

VREG

RESET

WDI

VLIN tPOR

Normal Operation

Figure 7. Timing Diagram for Normal Regulator Operation


CS5112 VLIN

If a correct watchdog signal is not received within the specified time a reset pulse train is issued until the correct watchdog signal is received. The nominal reset signal in this case is a 5 volt square wave with a 50% duty cycle as shown in Figure 8.

5.0 V 4.25 V

RESET

50% Duty Cycle

VREG

5.0 V

RESET tPOR

WDI

Figure 10. RESET Signal Is Issued Whenever VLIN Falls Below 4.25 V (Typical)

VLIN

The POR delay (tPOR) is given by: tPOR

A

tPOR + 1.353

B

A: Watchdog waiting for low–going transition on WDI B: RESET stays low for tWDI time

CDelayRBIAS

CURRENT MODE PWM SWITCHING CIRCUITRY

The current mode PWM switching voltage regulator contains an error amplifier with selectable feedback inputs, a current sense amplifier, an adjustable oscillator and a 1.4 A output power switch with antisaturation control. The switching regulator and external components, connected in a boost configuration, are shown in Figure 11. The switching regulator begins operation when VREG and VIN are raised above 5 volts. VREG is required since the switching supply’s control circuitry is powered through VLIN. VIN supplies the base drive to the switcher output transistor. The output transistor turns on when the oscillator starts to charge the capacitor on COSC. The output current will develop a voltage drop across the internal sense resistor (RS). This voltage drop produces a proportional voltage at the output of the current sense amplifier, which is compared to the output of the error amplifier. The error amplifier generates an output voltage which is proportional to the difference between the scaled down output boost voltage (VFB1 or VFB2) and the internal bandgap voltage reference. Once the current sense amplifier output exceeds the error amplifier’s output voltage, the output transistor is turned off. The energy stored in the inductor during the output transistor on time is transferred to the load when the output transistor is turned off. The output transistor is turned back

Figure 8. Timing Diagram When WDI Fails to Appear Within the Preset Time Interval, tWDI

The RESET signal frequency is given by: 1 fRESET + 2(tWDI)

The Power On Reset (POR) and low voltage RESET use the same circuitry and issue a reset when the linear output voltage is below the regulation limit. After VLIN rises above the minimum specified value, RESET remains low for a fixed period tPOR as shown in Figures 9 and 10. VLIN 4.45 V 4.25 V

RESET VR(LO) VR(PEAK) tPOR

Figure 9. The Power On Reset Time Interval (tPOR) Begins When VLIN Rises Above 4.45 V (Typical)


CS5112 on at the next rising edge of the oscillator. On a cycle by cycle basis, the current mode controller in a discontinuous mode of operation charges the inductor to the appropriate amount of energy, based on the energy demand of the load. Figure 12 shows the typical current and voltage waveforms for a boost supply operating in the discontinuous mode.

2. The switching regulator can be disabled by providing a logic high at the ENABLE input. 3. The boost output voltage can be controlled dynamically by the feedback select input. If select is open, VFB2 is selected. If select is low, then VFB1 is selected.

Notes:

1. Refer to Figure 5 to determine oscillator frequency. VIN VLIN VOUT VSW

COMP

IBIAS RBIAS 64.9 kΩ

Base Drive

Logic

Current Sense Amplifier

COSC Oscillator ENABLE

+ –

RS

COMP

Bandgap Reference R1

VFB1 – +

GND

+ – Switcher Shutdown 1.25 V


COUT

1.4 A

Multiplexer

R2

VFB2

R3 SELECT

Figure 11. Block Diagram of the 1.4 A Current Mode Control Switching Regulator Portion of the CS5112 in a Boost Configuration


CS5112 PROTECTION CIRCUITRY

VSW

The current out of VLIN is sensed in order to limit excessive power dissipation in the linear output transistor over the output range of 0 V to regulation. Also, the current into VSW is sensed in order to provide the current limit function in the switcher output transistor. If the die temperature is increased above 160°C, either due to excessive ambient temperature or excessive power dissipation, the drive to the linear output transistor is reduced proportionally with increasing die temperature. Therefore, VLIN will decrease with increasing die temperature above 160°C. Since the switcher control circuitry is powered through VLIN, the switcher performance, including current limit, will be affected by the decrease in VLIN.

VOUT

VIN

VSAT 0

t

ISW IPeak

t

0 ID IPeak

t

0

Figure 12. Voltage and Current Waveforms for Boost Topology in CS5112


CS5112 APPLICATION NOTES VINtON + (VOUT * VIN)tOFF

DESIGN PROCEDURE FOR BOOST TOPOLOGY

This section outlines a procedure for designing a boost switching power supply operating in the discontinuous mode.

where the maximum on time is:

ƪ

VIN(MIN) tON(MAX) [ 1 * VOUT(MAX)

Step 1

Determine the output power required by the load. POUT + IOUTVOUT

1 ƫƪfSW(MIN) ƫ

(7)

Step 5

(1)

Calculate the maximum inductance allowed for discontinuous operation:

Step 2

Choose COSC based on the target oscillator frequency with an external resistor value, RBIAS = 64.9 kΩ. (See Figure 5).

2 f V 2 t L(MAX) + SW(MIN) IN (MIN) ON (MAX) 2POUTń

Step 3

(8)

where η = efficiency. Usually η = 0.75 is a good starting point. The IC’s power dissipation should be calculated after the peak current has been determined in Step 6. If the efficiency is less than originally assumed, decrease the efficiency and recalculate the maximum inductance and peak current.

Next select the output voltage feedback sense resistor divider as follows (Figure 13). For VFB1 active, choose a value for R1 and then solve for REQ where: R REQ + VOUT 1 *1 V

(6)

(2)

FB1

Step 6

For VFB2 active, find:

ǒ

REQ VFB1 + VOUT R1 ) REQ

Ǔ

Determine the peak inductor current at the minimum inductance, minimum VIN and maximum on time to make sure the inductor current doesn’t exceed 1.4 A.

(3)

and then calculate R2 where: V V * VFB2 R2 + R2 + FB1 IR2 VFB1ńREQ

V t IPK + IN(MIN) ON(MAX) L(MIN)

(4)

Step 7

Then find R3, where: R3 + REQ * R2

Determine the minimum output capacitance and maximum ESR based on the allowable output voltage ripple.

(5)

COUT(MIN) +

VOUT

ESR(MIN) +

R1 VFB1 VR2

IPK 8fVRIPPLE

(10)

VRIPPLE IPK

(11)

In practice, it is normally necessary to use a larger capacitance value to obtain a low ESR. By placing capacitors in parallel, the equivalent ESR can be reduced.

R2 VFB2

REQ

(9)

Step 8

Compensate the feedback loop to guarantee stability under all operating conditions. To do this, we calculate the modulator gain and the feedback resistor network attenuation and set the gain of the error amplifier so that the overall loop gain is 0 dB at the crossover frequency, fCO. In addition, the gain slope should be –20 dB/decade at the crossover frequency. The low frequency gain of the modulator (i.e. error amplifier output to output voltage) is:

R3

Figure 13. Feedback Sense Resistor Divider Connected Between VOUT and Ground Step 4

Determine the maximum on time at the minimum oscillator frequency and VIN. For discontinuous operation, all of the stored energy in the inductor is transferred to the load prior to the next cycle. Since the current through the inductor cannot change instantaneously and the inductance is constant, a volt–second balance exists between the on time and off time. The voltage across the inductor during the on cycle is VIN and the voltage across the inductor during the off cycle is VOUT – VIN. Therefore:

IPK(MAX) VOUT + VEA(MAX) VEA

Lf ǸRLOAD 2

(12)

where: V ńG 2.4 Vń7 IPK(MAX) + EA(MAX) CSA + + 2.3 A (13) 150 m RS

The VOUT/VEA transfer function has a pole at:


CS5112 fp + 1ń(RLOADCOUT)

VOUT

(14)

and a zero due to the output capacitor’s ESR at:

R1

fz + 1ń(2ESR(COUT))

Since the error amplifier reference voltage is 1.25 V, the output voltage must be divided down or attenuated before being applied to the input of the error amplifier. The feedback resistor divider attenuation is:

1.25 V

VFB1

(15) R2

M U X

VFB2

– Error Amplifier

R3

1.25 V VOUT

+ C1

C2

R4

The error amplifier in the CS5112 is an operational transconductance amplifier (OTA), with a gain given by: GOTA + gmZOUT

SELECT

(16)

Figure 14. RC Network Used to Compensate the Error Amplifier (OTA)

where: gm +

IOUT VIN

(17)

A pole at point C:

For the CS5112, gm = 2700 µA/V typical. One possible error amplifier compensation scheme is shown in Figure 14. This gives the error amplifier a gain plot as shown in Figure 15. For the error amplifier gain shown in Figure 15, a low frequency pole is generated by the error amplifier output impedance and C1 . This is shown by the line AB with a –20 dB/decade slope in Figure 15. The slope changes to zero at point B due to the zero at: fz + 1ń(2R4C1)

fp + 1ń(R4C2)

offsets the zero set by the ESR of the output capacitors. An alternative scheme uses a single capacitor as shown in Figure 16, to roll the gain off at a relatively low frequency. Step 9

Finally the watchdog timer period and Power on Reset time is determined by: tDelay + 1.353

(18)

CDelayRBIAS

Pole due to error amplifier output impedance and C1 G A

fz = 1/(2πR4C1)

fp = 1/(πR4C2) +G

C

B error amplifier gain Gain (dB)

(19)

–20 dB/dec

fp = 1/(πRLOADCOUT) fCO 0 modulator gain + feedback resistor divider attenuation –G

fz = 1/(2πESR(COUT))

Figure 15. Bode Plot of Error Amplifier (OTA) Gain and Modulator Gain Added to the Feedback Resistor Divider Attenuation


(20)

CS5112 VIN

VOUT = 18 V, Select > 2.0 V VOUT = 16 V, Select < 0.8 V

L = 33 µH

COUT 88 µF

VIN

ENABLE

NC

VREG

NC

VLIN

VSW

IBIAS

GND

GND

(2)

GND

5.0 V 100 µF ESR < 8.0 Ω RBIAS 64.9 kΩ

GND CS5112

R1 100 kΩ

R2 946 Ω

GND

GND

GND

GND

VFB1

RESET

VFB2

CDelay

Microprocessor

(1)

R3 7.5 kΩ

SELECT COMP

CDelay 0.1 µF

WDI COSC COSC 390 pF

CCOMP 0.33 µF

Figure 16. A Typical Application Diagram with External Components Configured in a Boost Topology


CS5112 LINEAR REGULATOR OUTPUT CURRENT VS. INPUT VOLTAGE

100 ILIN (mA)

ILIN (mA)

100


50

25

0


50

25

0

5

10

15

20

25

0

30

0

5

10

VREG (V)

15

20

25

30

VREG (V)

Figure 17. The Shaded Area Shows the Safe Operating Area of the CS5112 as a Function of ILIN, VREG, and QJA. Refer to Table 5 for Typical Loads and Voltages.

Table 5. Worst Case Switcher Power Available (ΘJA = 55°C/W) (W)

Worst Case Switcher Power Available (ΘJA = 35°C/W) (W)

VREG (V)

VIN (V)

ILIN (mA)

Linear Power Dissipation (W)

20

14

25

0.44

0.74

1.42

20

14

50

0.83

0.35

1.03

20

14

75

1.22

*

0.64

20

14

100

1.60

*

0.26

25

14

25

0.60

0.58

1.26

25

14

50

1.11

0.07

0.75

25

14

75

1.62

*

0.24

25

14

100

2.14

*

*

*Subjecting the CS5112 to these conditions will exceed the maximum total power that the part can handle, thereby forcing it into thermal limit. PACKAGE THERMAL DATA Parameter

SO–24L

Unit

RΘJC

Typical

9

°C/W

RΘJA

Typical

55

°C/W


* * * * 3 4 ! ! The CS5171/2/3/4 products are 280 kHz/560 kHz switching regulators with a high efficiency, 1.5 A integrated switch. These parts operate over a wide input voltage range, from 2.7 V to 30 V. The flexibility of the design allows the chips to operate in most power supply configurations, including boost, flyback, forward, inverting, and SEPIC. The ICs utilize current mode architecture, which allows excellent load and line regulation, as well as a practical means for limiting current. Combining high frequency operation with a highly integrated regulator circuit results in an extremely compact power supply solution. The circuit design includes provisions for features such as frequency synchronization, shutdown, and feedback controls for either positive or negative voltage regulation. These parts are pin–to–pin compatible with LT1372/1373.

http://onsemi.com


PIN CONNECTIONS AND MARKING DIAGRAM VC

Frequency

Feedback Voltage Polarity

CS5171

280 kHz

positive

CS5172

280 kHz

negative

CS5173

560 kHz

positive

CS5174

560 kHz

negative

FB Test SS

Features • Integrated Power Switch: 1.5 A Guaranteed • Wide Input Range: 2.7 V to 30 V • High Frequency Allows for Small Components • Minimum External Components • Easy External Synchronization • Built in Overcurrent Protection • Frequency Foldback Reduces Component Stress During an Overcurrent Condition • Thermal Shutdown with Hysteresis • Regulates Either Positive or Negative Output Voltages • Shut Down Current: 50 µA Maximum • Pin–to–Pin Compatible with LT1372/1373 • Wide Ambient Temperature Range – Industrial Grade: –40°C to 85°C – Commercial Grade: 0°C to 70°C


June, 2001 – Rev. 13

1382

Test NFB SS

1

CS5172/4 CS517x ALYW

VC

CS5171/3

8

CS517x ALYW

Part Number

1

VSW PGND AGND VCC

8

VSW PGND AGND VCC

x = 1, 2, 3, or 4 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week



CS5171, CS5172, CS5173, CS5174 R2 3.72 k

2

C1 0.01 µF

3

D1 VSW

VC FB Test

PGND

CS5171/3

1

AGND

VOUT

8

5V MBRS120T3

7

6

L1 4

SS

VCC

SS

5

+

22 µH

C3 22 µF

3.3 V R3

R1 5k

+

C2 22 µF

1.28 k

Figure 1. Applications Diagram ABSOLUTE MAXIMUM RATINGS* Rating

Value

Unit

Junction Temperature Range, TJ

–40 to +150

°C

Storage Temperature Range, TSTORAGE

–65 to +150

°C

230 Peak

°C

1.2

kV


Reflow (Note 1)

ESD, Human Body Model 1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed.

ABSOLUTE MAXIMUM RATINGS Pin Name

Pin Symbol

VMAX

VMIN

ISOURCE

ISINK

IC Power Input

VCC

30 V

–0.3 V

N/A

200 mA

Shutdown/Sync

SS

30 V

–0.3 V

1.0 mA

1.0 mA

Loop Compensation

VC

6.0 V

–0.3 V

10 mA

10 mA

Voltage Feedback Input

FB (CS5171/3 only)

10 V

–0.3 V

1.0 mA

1.0 mA

Negative Feedback Input (transient, 10 ms)

NFB (CS5172/4 only)

–10 V

10 V

1.0 mA

1.0 mA

Test Pin

Test

6.0 V

–0.3 V

1.0 mA

1.0 mA

Power Ground

PGND

0.3 V

–0.3 V

4A

10 mA

Analog Ground

AGND

0V

0V

N/A

10 mA

Switch Input

VSW

40 V

–0.3 V

10 mA

3.0 A


CS5171, CS5172, CS5173, CS5174 ELECTRICAL CHARACTERISTICS (2.7 V< VCC < 30 V; Industrial Grade: –40°C < TA < 85°C; –40°C < TJ < 125°C; Commercial Grade: 0°C < TA < 70°C; 0°C < TJ < 125°C; For all CS5171/2/3/4 specifications unless otherwise stated.) Test Conditions

Characteristic

Min

Typ

Max

Unit

Positive and Negative Error Amplifiers FB Reference Voltage (CS5171/3 only)

VC tied to FB; measure at FB

1.246

1.276

1.300

V

NFB Reference Voltage (CS5172/4 only)

VC = 1.25 V

–2.55

–2.45

–2.35

V

FB Input Current (CS5171/3 only)

FB = VREF

–1.0

0.1

1.0

µA

NFB Input Current (CS5172/4 only)

NFB = NVREF

–16

–10

–5.0

µA

FB Reference Voltage Line Regulation (CS5171/3 only)

VC = FB

–

0.01

0.03

%/V

NFB Reference Voltage Line Regulation (CS5172/4 only)

VC = 1.25 V

–

0.01

0.05

%/V

Positive Error Amp Transconductance

IVC = ± 25 µA

300

550

800

µMho

Negative Error Amp Transconductance

IVC = ± 5 µA

115

160

225

µMho

Positive Error Amp Gain

Note 2

200

500

–

V/V

Negative Error Amp Gain

Note 2

100

180

320

V/V

VC Source Current

FB = 1.0 V or NFB = –1.9 V, VC = 1.25 V

25

50

90

µA

VC Sink Current

FB = 1.5 V or NFB = –3.1 V, VC = 1.25 V

200

625

1500

µA

VC High Clamp Voltage

FB = 1.0 V or NFB = –1.9 V; VC sources 25 µA

1.5

1.7

1.9

V

VC Low Clamp Voltage

FB = 1.5 V or NFB = –3.1 V, VC sinks 25 µA

0.25

0.50

0.65

V

VC Threshold

Reduce VC from 1.5 V until switching stops

0.75

1.05

1.30

V

Base Operating Frequency

CS5171/2, FB = 1 V or NFB = –1.9 V

230

280

310

kHz

Reduced Operating Frequency

CS5171/2, FB = 0 V or NFB = 0 V

30

52

120

kHz

Maximum Duty Cycle

CS5171/2

90

94

–

%

Base Operating Frequency

CS5173/4, FB = 1 V or NFB = –1.9 V

460

560

620

kHz

Reduced Operating Frequency

CS5173/4, FB = 0 V or NFB = 0 V

60

104

160

kHz

Maximum Duty Cycle

CS5173/4

82

90

–

%

NFB Frequency Shift Threshold

Frequency drops to reduced operating frequency

–0.80

–0.65

–0.50

V

FB Frequency Shift Threshold

Frequency drops to reduced operating frequency

0.36

0.40

0.44

V

Sync Range

CS5171/2

320

–

500

kHz

Sync Range

CS5173/4

640

–

1000

kHz

Sync Pulse Transition Threshold

Rise time = 20 ns

2.5

–

–

V

SS Bias Current

SS = 0 V SS = 3.0 V

–15 –

–3.0 3.0

– 8.0

µA µA

0.50

0.85

1.20

V

12 12

80 36

350 200

µs µs

Oscillator

Sync/ Shutdown

Shutdown Threshold Shutdown Delay

– 2.7 V ≤ VCC ≤ 12 V 12 V < VCC ≤ 30 V



CS5171, CS5172, CS5173, CS5174 ELECTRICAL CHARACTERISTICS (continued) (2.7 V< VCC < 30 V; Industrial Grade: –40°C < TA < 85°C; –40°C < TJ < 125°C; Commercial Grade: 0°C < TA < 70°C; 0°C < TJ < 125°C; For all CS5171/2/3/4 specifications unless otherwise stated.) Characteristic

Test Conditions

Min

Typ

Max

Unit

– – – –

0.8 0.55 0.75 0.09

1.4 1.00 1.30 0.45

V V V V

Power Switch Switch Saturation Voltage

ISWITCH = 1.5 A, Note 3 ISWITCH = 1.0 A, 0 ≤ TA ≤ 85°C ISWITCH = 1.0 A, –40 ≤ TA ≤ 0°C, Note 3 ISWITCH = 10 mA

Switch Current Limit

50% duty cycle, Note 3 80% duty cycle, Note 3

1.6 1.5

1.9 1.7

2.4 2.2

A A

Minimum Pulse Width

FB = 0 V or NFB = 0 V, ISW = 4.0 A, Note 3

200

250

300

ns

∆ICC/ ∆IVSW

2.7 V ≤ VCC ≤ 12 V, 10 mA ≤ ISW ≤ 1.0 A 12 V < VCC ≤ 30 V, 10 mA ≤ ISW ≤ 1.0 A 2.7 V ≤ VCC ≤ 12 V, 10 mA ≤ ISW ≤ 1.5 A, Note 3 12 V < VCC ≤ 30 V, 10 mA ≤ ISW ≤ 1.5 A, Note 3

– – –

10 – 17

30 100 30

mA/A mA/A mA/A

–

–

100

mA/A

VSW = 40 V, VCC = 0V

–

2.0

100

µA

Operating Current

ISW = 0

–

5.5

8.0

mA

Shutdown Mode Current

VC < 0.8 V, SS = 0 V, 2.7 V ≤ VCC ≤ 12 V VC < 0.8 V, SS = 0 V, 12 V ≤ VCC ≤ 30 V

– –

12 –

60 100

µA

Minimum Operation Input Voltage

VSW switching, maximum ISW = 10 mA

–

2.45

2.70

V

Thermal Shutdown

Note 3

150

180

210

°C

Thermal Hysteresis

Note 3

–

25

–

°C

Switch Leakage General


PACKAGE PIN DESCRIPTION Package Pin Number 8 LEAD SO NARROW

Pin Symbol

Function

1

VC

Loop compensation pin. The VC pin is the output of the error amplifier and is used for loop compensation, current limit and soft start. Loop compensation can be implemented by a simple RC network as shown in the application diagram on page 1383 as R1 and C1.

2 (CS5171/3 only)

FB

Positive regulator feedback pin. This pin senses a positive output voltage and is referenced to 1.276 V. When the voltage at this pin falls below 0.4 V, chip switching frequency reduces to 20% of the nominal frequency.

2 (CS5172/4 only) 3 (CS5171/3 only)

Test

These pins are connected to internal test logic and should either be left floating or tied to ground. Connection to a voltage between 2 V and 6 V shuts down the internal oscillator and leaves the power switch running.

3 (CS5172/4 only)

NFB

Negative feedback pin. This pin senses a negative output voltage and is referenced to –2.5 V. When the voltage at this pin goes above –0.65 V, chip switching frequency reduces to 20% of the nominal frequency.

4

SS

Synchronization and shutdown pin. This pin may be used to synchronize the part to nearly twice the base frequency. A TTL low will shut the part down and put it into low current mode. If synchronization is not used, this pin should be either tied high or left floating for normal operation.


CS5171, CS5172, CS5173, CS5174 PACKAGE PIN DESCRIPTION Package Pin Number 8 LEAD SO NARROW (continued)

Pin Symbol

5

VCC

6

AGND

Analog ground. This pin provides a clean ground for the controller circuitry and should not be in the path of large currents. The output voltage sensing resistors should be connected to this ground pin. This pin is connected to the IC substrate.

7

PGND

Power ground. This pin is the ground connection for the emitter of the power switching transistor. Connection to a good ground plane is essential.

8

VSW

VCC

Function Input power supply pin. This pin supplies power to the part and should have a bypass capacitor connected to AGND.

High current switch pin. This pin connects internally to the collector of the power switch. The open voltage across the power switch can be as high as 40 V. To minimize radiation, use a trace as short as practical.

Thermal Shutdown Shutdown

2.0 V Regulator

VSW Oscillator

Delay Timer

S PWM Latch R

Q

Switch

Driver

Sync

SS

Frequency Shift 5:1 ×5 200 k 2.0 V

NFB CS5172/4 only

250 k

Slope Compensation

Negative Error Amp

63 mΩ

+

Ramp Summer

–

PWM Comparator

–0.65 V Detector

+

0.4 V Detector FB

–

CS5171/3 only

+

1.276 V

Positive Error Amp

AGND

VC



–

PGND

CS5171, CS5172, CS5173, CS5174 TYPICAL PERFORMANCE CHARACTERISTICS 7.2

70

7.0

VCC = 12 V

50

(mA/A)

Current (mA)

6.6 6.4

ISW = 1.5 A

40 30

6.2

VCC = 12 V

20

6.0 5.8 5.6

VCC = 30 V

60

VCC = 30 V

6.8

0

50

VCC = 2.7 V

10

VCC = 2.7 V

0

100

0

TA (°C)

100

Figure 4. ∆ICC/ ∆IVSW vs. TA

Figure 3. ICC (No Switching) vs. TA

1.9

1200 1000

TA = –40 °C

800

TA = 85 °C

1.8 VIN (V)

VCE(SAT) (mV)

50 TA (°C)

1.7

600 TA = 25 °C

400

1.6 200 0

500

1.5

1000

0

ISW (mA)

285

fOSC (kHz)

280 fOSC (kHz)

275 270

265

260 0

100

Figure 6. Minimum Input Voltage vs. TA

Figure 5. VCE(SAT) vs. ISW

255

50 TA (°C)

50

570 565 560 555 550 545 540 535 530 525 520

100

0

50

100

TA (°C)

TA (°C)

Figure 8. Switching Frequency vs. TA (CS5173/4 only)

Figure 7. Switching Frequency vs. TA (CS5171/2 only)


CS5171, CS5172, CS5173, CS5174 TYPICAL PERFORMANCE CHARACTERISTICS

VCC = (12 V)

VCC = (12 V)

100

fOSC (% of Typical)

fOSC (% of Typical)

100

TA = –40°C 75 TA = 85°C

50 TA = 25°C 25 0 350

380

400 VFB (mV)

420

TA = 85°C 75

25 0

450

TA = –40°C

50

TA = 25°C –550

–660 VNFB (mV)

–725

Figure 10. Switching Frequency vs. VNFB (CS5172/4 only)

Figure 9. Switching Frequency vs. VFB (CS5171/3 only)

1.280 VCC = 12 V

–2.42 VCC = 30 V

–2.43

1.276

Voltage (V)

Voltage (V)

1.278

–2.44

1.274

–2.45

VCC = 2.7 V

1.272

VCC = 30 V

1.270

VCC = 12 V

–2.46

–2.47

1.268 0

50 TA (°C)

100

–2.48

VCC = 2.7 V 0

100

Figure 12. Reference Voltage vs. TA (CS5172/4 only)

Figure 11. Reference Voltage vs. TA (CS5171/3 only)

–7

0.20 0.18

–8

0.16

–9 INFB (µA)

IFB (µA)

50 TA (°C)

VCC = 12 V

0.14

–10

0.12

–11

–12 0.10 0.08

VCC = 2.7 V 0

50

–13 –14

100

TA (°C)

Figure 13. IFB vs. TA (CS5171/3 only)

0

50 TA (°C)

100

Figure 14. INFB vs. TA (CS5172/ 4 only)


CS5171, CS5172, CS5173, CS5174

99

2.60

VCC = 30 V

Current (A)

2.50 2.40 VCC = 2.7 V

2.30

0

VCC = 12 V

97 96

VCC = 2.7 V

95 94

VCC = 12 V 2.20

Duty Cycle (%)

98

VCC = 30 V

TA (°C)

93

50

0

100

50

100

TA (°C)

Figure 17. Maximum Duty Cycle vs. TA

Figure 16. Current Limit vs. TA

1.1 1.7

1.0 VC High Clamp Voltage Voltage (V)

Voltage (V)

1.5 1.3 1.1 0.9 0.7

VC Threshold

0.9 0.8 0.7 0.6 0.5 0.4

0

50 TA (°C)

0

100

Figure 19. Shutdown Threshold vs. TA

Figure 18. VC Threshold and High Clamp Voltage vs. TA

40

160 140

100

50 TA (°C)

VCC = 2.7 V

TA = 25°C

30

100

ISS (µA)

Delay (µs)

120 VCC = 12 V

80 VCC = 30 V

60 50

TA = –40°C

10 0

40 0

TA = 85°C

20

–10

100

TA (°C)

1

3

5 VSS (V)

Figure 21. ISS vs. VSS

Figure 20. Shutdown Delay vs. TA


7

9

CS5171, CS5172, CS5173, CS5174

30 TA = 25°C 20

TA = 85°C

gm (µmho)

ICC (µA)

600

TA = –40°C

40

550

500

10 450

0

10 VIN (V)

50

100

TA (°C)

Figure 23. Error Amplifier Transconductance vs. TA (CS5171/3 only)

Figure 22. ICC vs. VIN During Shutdown

100

190 180 170 160 150 140 130 120 110 100

60 IOUT (µA)

gm (µmho)

0

20

–20 –60 0

50 TA (°C)

100

–255 –175 –125 –75 –25 VREF – VFB (mV)

0

25

Figure 25. Error Amplifier IOUT vs. VFB (CS5171/3 only)

Figure 24. Negative Error Amplifier Transconductance vs. TA (CS5172/4 only)

2.6 100 80 60 40 20 0 –20 –40

IOUT (µA)

Current (µA)

2.5

–60

2.4 2.3 2.2 2.1

–200

–150

–100 –50 VREF – VNFB (mV)

2.0

50

0

0

TA (°C)

50

Figure 27. Switch Leakage vs. TA

Figure 26. Error Amplifier IOUT vs. VNFB (CS5172/4 only)


100

CS5171, CS5172, CS5173, CS5174 APPLICATIONS INFORMATION THEORY OF OPERATION

The oscillator is trimmed to guarantee an 18% frequency accuracy. The output of the oscillator turns on the power switch at a frequency of 280 kHz (CS5171/2) or 560 kHz (CS5173/4), as shown in Figure 28. The power switch is turned off by the output of the PWM Comparator. A TTL–compatible sync input at the SS pin is capable of syncing up to 1.8 times the base oscillator frequency. As shown in Figure 29, in order to sync to a higher frequency, a positive transition turns on the power switch before the output of the oscillator goes high, thereby resetting the oscillator. The sync operation allows multiple power supplies to operate at the same frequency. A sustained logic low at the SS pin will shut down the IC and reduce the supply current. An additional feature includes frequency shift to 20% of the nominal frequency when either the NFB or FB pins trigger the threshold. During power up, overload, or short circuit conditions, the minimum switch on–time is limited by the PWM comparator minimum pulse width. Extra switch off–time reduces the minimum duty cycle to protect external components and the IC itself. As previously mentioned, this block also produces a ramp for the slope compensation to improve regulator stability.

Current Mode Control VCC Oscillator

S VC

– +

Q

L

R D1

Power Switch

VSW

PWM Comparator

In Out X5

CO

Driver

RLOAD

SUMMER Slope Compensation

63 mΩ

Figure 28. Current Mode Control Scheme

The CS517x family incorporates a current mode control scheme, in which the PWM ramp signal is derived from the power switch current. This ramp signal is compared to the output of the error amplifier to control the on–time of the power switch. The oscillator is used as a fixed–frequency clock to ensure a constant operational frequency. The resulting control scheme features several advantages over conventional voltage mode control. First, derived directly from the inductor, the ramp signal responds immediately to line voltage changes. This eliminates the delay caused by the output filter and error amplifier, which is commonly found in voltage mode controllers. The second benefit comes from inherent pulse–by–pulse current limiting by merely clamping the peak switching current. Finally, since current mode commands an output current rather than voltage, the filter offers only a single pole to the feedback loop. This allows both a simpler compensation and a higher gain–bandwidth over a comparable voltage mode circuit. Without discrediting its apparent merits, current mode control comes with its own peculiar problems, mainly, subharmonic oscillation at duty cycles over 50%. The CS517x family solves this problem by adopting a slope compensation scheme in which a fixed ramp generated by the oscillator is added to the current ramp. A proper slope rate is provided to improve circuit stability without sacrificing the advantages of current mode control.

Error Amplifier

200 k NFB

250 k

2.0 V

+ CS5172/4

–

negative error–amp

FB

1.276 V + – CS5171/3

VC 1MΩ

120 pF

Voltage Clamp

C1 0.01 µF R1 5 kΩ

positive error–amp

Figure 30. Error Amplifier Equivalent Circuit

For CS5172/4, the NFB pin is internally referenced to –2.5 V with approximately a 250 kΩ input impedance. For CS5171/3, the FB pin is directly connected to the inverting input of the positive error amplifier, whose non–inverting input is fed by the 1.276 V reference. Both amplifiers are transconductance amplifiers with a high output impedance of approximately 1 MΩ, as shown in Figure 30. The VC pin is connected to the output of the error amplifiers and is internally clamped between 0.5 V and 1.7 V. A typical connection at the VC pin includes a capacitor in series with a resistor to ground, forming a pole/zero for loop compensation. An external shunt can be connected between the VC pin and ground to reduce its clamp voltage. Consequently, the current limit of the internal power transistor current is reduced from its nominal value.

Oscillator and Shutdown Sync Current Ramp VSW

Figure 29. Timing Diagram of Sync and Shutdown


CS5171, CS5172, CS5173, CS5174 Switch Driver and Power Switch

output through the inductor and diode. Once VCC reaches approximately 1.5 V, the internal power switch briefly turns on. This is a part of the CS517x’s normal operation. The turn–on of the power switch accounts for the initial current swing. When the VC pin voltage rises above the threshold, the internal power switch starts to switch and a voltage pulse can be seen at the VSW pin. Detecting a low output voltage at the FB pin, the built–in frequency shift feature reduces the switching frequency to a fraction of its nominal value, reducing the minimum duty cycle, which is otherwise limited by the minimum on–time of the switch. The peak current during this phase is clamped by the internal current limit. When the FB pin voltage rises above 0.4 V, the frequency increases to its nominal value, and the peak current begins to decrease as the output approaches the regulation voltage. The overshoot of the output voltage is prevented by the active pull–on, by which the sink current of the error amplifier is increased once an overvoltage condition is detected. The overvoltage condition is defined as when the FB pin voltage is 50 mV greater than the reference voltage.

The switch driver receives a control signal from the logic section to drive the output power switch. The switch is grounded through emitter resistors (63 mΩ total) to the PGND pin. PGND is not connected to the IC substrate so that switching noise can be isolated from the analog ground. The peak switching current is clamped by an internal circuit. The clamp current is guaranteed to be greater than 1.5 A and varies with duty cycle due to slope compensation. The power switch can withstand a maximum voltage of 40 V on the collector (VSW pin). The saturation voltage of the switch is typically less than 1 V to minimize power dissipation. Short Circuit Condition

When a short circuit condition happens in a boost circuit, the inductor current will increase during the whole switching cycle, causing excessive current to be drawn from the input power supply. Since control ICs don’t have the means to limit load current, an external current limit circuit (such as a fuse or relay) has to be implemented to protect the load, power supply and ICs. In other topologies, the frequency shift built into the IC prevents damage to the chip and external components. This feature reduces the minimum duty cycle and allows the transformer secondary to absorb excess energy before the switch turns back on.

COMPONENT SELECTION Frequency Compensation

The goal of frequency compensation is to achieve desirable transient response and DC regulation while ensuring the stability of the system. A typical compensation network, as shown in Figure 32, provides a frequency response of two poles and one zero. This frequency response is further illustrated in the Bode plot shown in Figure 33.

IL

VOUT VCC

VC R1

VC CS5171

C2 C1 GND

Figure 31. Startup Waveforms of Circuit Shown in the Application Diagram. Load = 400 mA.

Figure 32. A Typical Compensation Network

The CS517x can be activated by either connecting the VCC pin to a voltage source or by enabling the SS pin. Startup waveforms shown in Figure 31 are measured in the boost converter demonstrated in the Application Diagram on the page 1383 of this document. Recorded after the input voltage is turned on, this waveform shows the various phases during the power up transition. When the VCC voltage is below the minimum supply voltage, the VSW pin is in high impedance. Therefore, current conducts directly from the input power source to the

The high DC gain in Figure 33 is desirable for achieving DC accuracy over line and load variations. The DC gain of a transconductance error amplifier can be calculated as follows: GainDC + GM

RO

where: GM = error amplifier transconductance; RO = error amplifier output resistance ≈ 1 MΩ.


CS5171, CS5172, CS5173, CS5174 The low frequency pole, fP1, is determined by the error amplifier output resistance and C1 as: 1 fP1 + 2C1R

–VOUT

2V

NFB

The first zero generated by C1 and R1 is:

RIN

+

250 kΩ

1 fZ1 + 2C1R1

R2

The phase lead provided by this zero ensures that the loop has at least a 45° phase margin at the crossover frequency. Therefore, this zero should be placed close to the pole generated in the power stage which can be identified at frequency:

– Negative Error–Amp

Figure 34. Negative Error Amplifier and NFB Pin

It is shown that if R1 is less than 10 k, the deviation from the design target will be less than 0.1 V. If the tolerances of the negative voltage reference and NFB pin input current are considered, the possible offset of the output VOFFSET varies in the range of:

1 fP + 2CORLOAD

where: CO = equivalent output capacitance of the error amplifier ≈120pF; RLOAD= load resistance. The high frequency pole, fP2, can be placed at the output filter’s ESR zero or at half the switching frequency. Placing the pole at this frequency will cut down on switching noise. The frequency of this pole is determined by the value of C2 and R1:

(R1 ) R2) ǒ*0.0.5 R2 Ǔ * (15 A R1) v VOFFSET 0.0.5 (R1 ) R2) Ǔ * (5 A vǒ R2

In the boost topology, VSW pin maximum voltage is set by the maximum output voltage plus the output diode forward voltage. The diode forward voltage is typically 0.5 V for Schottky diodes and 0.8 V for ultrafast recovery diodes

One simple method to ensure adequate phase margin is to design the frequency response with a –20 dB per decade slope, until unity–gain crossover. The crossover frequency should be selected at the midpoint between fZ1 and fP2 where the phase margin is maximized.

VSW(MAX) + VOUT(MAX))VF

where: VF = output diode forward voltage. In the flyback topology, peak VSW voltage is governed by: VSW(MAX) + VCC(MAX))(VOUT)VF)

fP1

Gain (dB)

fP2

Frequency (LOG)

Figure 33. Bode Plot of the Compensation Network Shown in Figure 32 Negative Voltage Feedback

Magnetic Component Selection

Since the negative error amplifier has finite input impedance as shown in Figure 34, its induced error has to be considered. If a voltage divider is used to scale down the negative output voltage for the NFB pin, the equation for calculating output voltage is: ) R2) ǒ*2.5 (R1 Ǔ*10 A R2

N

where: N = transformer turns ratio, primary over secondary. When the power switch turns off, there exists a voltage spike superimposed on top of the steady–state voltage. Usually this voltage spike is caused by transformer leakage inductance charging stray capacitance between the VSW and PGND pins. To prevent the voltage at the VSW pin from exceeding the maximum rating, a transient voltage suppressor in series with a diode is paralleled with the primary windings. Another method of clamping switch voltage is to connect a transient voltage suppressor between the VSW pin and ground.

fZ1

*VOUT +

R1)

VSW Voltage Limit

1 fP2 + 2C2R1

DC Gain

RP 200 kΩ

R1

O

When choosing a magnetic component, one must consider factors such as peak current, core and ferrite material, output voltage ripple, EMI, temperature range, physical size and cost. In boost circuits, the average inductor current is the product of output current and voltage gain (VOUT/VCC),

R1


CS5171, CS5172, CS5173, CS5174 assuming 100% energy transfer efficiency. In continuous conduction mode, inductor ripple current is

IL

IIN

V (V * VCC) IRIPPLE + CC OUT (f)(L)(VOUT) VCC

where: f = 280 kHz for CS5171/2 and 560 kHz for CS5173/4. The peak inductor current is equal to average current plus half of the ripple current, which should not cause inductor saturation. The above equation can also be referenced when selecting the value of the inductor based on the tolerance of the ripple current in the circuits. Small ripple current provides the benefits of small input capacitors and greater output current capability. A core geometry like a rod or barrel is prone to generating high magnetic field radiation, but is relatively cheap and small. Other core geometries, such as toroids, provide a closed magnetic loop to prevent EMI.

+ –

CIN

RESR

Figure 36. Boost Circuit Effective Input Filter

The situation is different in a flyback circuit. The input current is discontinuous and a significant pulsed current is seen by the input capacitors. Therefore, there are two requirements for capacitors in a flyback regulator: energy storage and filtering. To maintain a stable voltage supply to the chip, a storage capacitor larger than 20 µF with low ESR is required. To reduce the noise generated by the inductor, insert a 1.0 µF ceramic capacitor between VCC and ground as close as possible to the chip.

Input Capacitor Selection

In boost circuits, the inductor becomes part of the input filter, as shown in Figure 36. In continuous mode, the input current waveform is triangular and does not contain a large pulsed current, as shown in Figure 35. This reduces the requirements imposed on the input capacitor selection. During continuous conduction mode, the peak to peak inductor ripple current is given in the previous section. As we can see from Figure 35, the product of the inductor current ripple and the input capacitor’s effective series resistance (ESR) determine the VCC ripple. In most applications, input capacitors in the range of 10 µF to 100 µF with an ESR less than 0.3 Ω work well up to a full 1.5 A switch current.

Output Capacitor Selection

VOUT ripple

IL

VCC ripple

IIN

Figure 37. Typical Output Voltage Ripple

By examining the waveforms shown in Figure 37, we can see that the output voltage ripple comes from two major sources, namely capacitor ESR and the charging/discharging of the output capacitor. In boost circuits, when the power switch turns off, IL flows into the output capacitor causing an instant ∆V = IIN × ESR. At the same time, current IL – IOUT charges the capacitor and

IL

Figure 35. Boost Input Voltage and Current Ripple Waveforms


CS5171, CS5172, CS5173, CS5174 increases the output voltage gradually. When the power switch is turned on, IL is shunted to ground and IOUT discharges the output capacitor. When the IL ripple is small enough, IL can be treated as a constant and is equal to input current IIN. Summing up, the output voltage peak–peak ripple can be calculated by:

VIN VCC R2

)

IOUTD ) IIN (COUT)(f)

VC

D1

(I * IOUT)(1 * D) VOUT(RIPPLE) + IN (COUT)(f) ESR

R3

The equation can be expressed more conveniently in terms of VCC, VOUT and IOUT for design purposes as follows: I (V * VCC) VOUT(RIPPLE) + OUT OUT (COUT)(f)

R1 C1 C2

1 (COUT)(f)

(I )(V )(ESR) ) OUT OUT VCC

Figure 38. Current Limiting using a Diode Clamp

The capacitor RMS ripple current is:

Another solution to the current limiting problem is to externally measure the current through the switch using a sense resistor. Such a circuit is illustrated in Figure 39.

IRIPPLE + Ǹ(IIN * IOUT)2(1 * D))(IOUT)2(D) * VCC ǸVOUTVCC

VCC

Although the above equations apply only for boost circuits, similar equations can be derived for flyback circuits.

PGND AGND VIN

VC

− +

+ IOUT

Reducing the Current Limit

In some applications, the designer may prefer a lower limit on the switch current than 1.5 A. An external shunt can be connected between the VC pin and ground to reduce its clamp voltage. Consequently, the current limit of the internal power transistor current is reduced from its nominal value. The voltage on the VC pin can be evaluated with the equation

R1 Q1

R2

C1 C2

C3 RSENSE

Output Ground

Figure 39. Current Limiting using a Current Sense Resistor

The switch current is limited to

VC + ISWREAV

VBE(Q1) ISWITCH(PEAK) + RSENSE

where: RE = .063Ω, the value of the internal emitter resistor; AV = 5 V/V, the gain of the current sense amplifier. Since RE and AV cannot be changed by the end user, the only available method for limiting switch current below 1.5 A is to clamp the VC pin at a lower voltage. If the maximum switch or inductor current is substituted into the equation above, the desired clamp voltage will result. A simple diode clamp, as shown in Figure 38, clamps the VC voltage to a diode drop above the voltage on resistor R3. Unfortunately, such a simple circuit is not generally acceptable if VIN is loosely regulated.

where: VBE(Q1) = the base–emitter voltage drop of Q1, typically 0.65 V. The improved circuit does not require a regulated voltage to operate properly. Unfortunately, a price must be paid for this convenience in the overall efficiency of the circuit. The designer should note that the input and output grounds are no longer common. Also, the addition of the current sense resistor, RSENSE, results in a considerable power loss which


CS5171, CS5172, CS5173, CS5174 increases with the duty cycle. Resistor R2 and capacitor C3 form a low–pass filter to remove noise.

pin. In normal operation, VSW looks similar to a square wave, and is dependent on the converter topology. Formulas for calculating VSW in the boost and flyback topologies are given in the section “VSW Voltage Limit.” The voltage on VSW charges capacitor C3 when the switch is off, causing the voltage at the VC pin to shift upwards. When the switch turns on, C3 discharges through R3, producing a negative slope at the VC pin. This negative slope provides the slope compensation. The amount of slope compensation added by this circuit is

Subharmonic Oscillation

Subharmonic oscillation (SHM) is a problem found in current–mode control systems, where instability results when duty cycle exceeds 50%. SHM only occurs in switching regulators with a continuous inductor current. This instability is not harmful to the converter and usually does not affect the output voltage regulation. SHM will increase the radiated EM noise from the converter and can cause, under certain circumstances, the inductor to emit high–frequency audible noise. SHM is an easily remedied problem. The rising slope of the inductor current is supplemented with internal “slope compensation” to prevent any duty cycle instability from carrying through to the next switching cycle. In the CS517x family, slope compensation is added during the entire switch on–time, typically in the amount of 180 mA/µs. In some cases, SHM can rear its ugly head despite the presence of the onboard slope compensation. The simple cure to this problem is more slope compensation to avoid the unwanted oscillation. In that case, an external circuit, shown in Figure 40, can be added to increase the amount of slope compensation used. This circuit requires only a few components and is “tacked on” to the compensation network. VSW

ǒ

VSW

SW Ǔǒ(1 *fD)R Ǔ EAV

R3C3 t 1 * D fSW

R2

Finally, it is worth mentioning that the added slope compensation is a trade–off between duty cycle stability and transient response. The more slope compensation a designer adds, the slower the transient response will be, due to the external circuitry interfering with the proper operation of the error amplifier.

C1 C2

C3

*(1*D) R3C3fSW

where: ∆I/∆T = the amount of slope compensation added (A/s); VSW = the voltage at the switch node when the transistor is turned off (V); fSW = the switching frequency, typically 280 kHz (CS5171/3) or 560 kHz (CS5172/4) (Hz); D = the duty cycle; RE = 0.063 Ω, the value of the internal emitter resistor; AV = 5 V/V, the gain of the current sense amplifier. In selecting appropriate values for the slope compensation network, the designer is advised to choose a convenient capacitor, then select values for R2 and R3 such that the amount of slope compensation added is 100 mA/µs. Then R2 may be increased or decreased as necessary. Of course, the series combination of R2 and R3 should be large enough to avoid drawing excessive current from VSW. Additionally, to ensure that the control loop stability is improved, the time constant formed by the additional components should be chosen such that

VC

R1

Ǔ ǒ1 * e

R3 I + V SW R )R T 2 3

Soft Start

R3

Through the addition of an external circuit, a soft–start function can be added to the CS5171/2/3/4 family of components. Soft–start circuitry prevents the VC pin from slamming high during startup, thereby inhibiting the inductor current from rising at a high slope.

Figure 40. Technique for Increasing Slope Compensation

The dashed box contains the normal compensation circuitry to limit the bandwidth of the error amplifier. Resistors R2 and R3 form a voltage divider off of the VSW


CS5171, CS5172, CS5173, CS5174 This circuit, shown in Figure 41, requires a minimum number of components and allows the soft–start circuitry to activate any time the SS pin is used to restart the converter.

due to this circuitry is 5.5 mA. Additional guidance can be found in the graph of operating current vs. temperature. This graph shows that IQ is strongly dependent on input voltage, VIN, and the ambient temperature, TA. Then

VIN

PBIAS + VINIQ

Since the onboard switch is an NPN transistor, the base drive current must be factored in as well. This current is drawn from the VIN pin, in addition to the control circuitry current. The base drive current is listed in the specifications as ∆ICC/∆ISW, or switch transconductance. As before, the designer will find additional guidance in the graphs. With that information, the designer can calculate

VCC SS

SS VC

D2

D1

C1 C3

ICC ISW

PDRIVER + VINISW

R1

D

where: ISW = the current through the switch; D = the duty cycle or percentage of switch on–time. ISW and D are dependent on the type of converter. In a boost converter,

C2

ISW(AVG) ^ ILOAD Figure 41. Soft Start

D

1 Efficiency

V * VIN D ^ OUT VOUT

Resistor R1 and capacitors C1 and C2 form the compensation network. At turn on, the voltage at the VC pin starts to come up, charging capacitor C3 through Schottky diode D2, clamping the voltage at the VC pin such that switching begins when VC reaches the VC threshold, typically 1.05 V (refer to graphs for detail over temperature).

In a flyback converter, V I ISW(AVG) ^ OUT LOAD VIN VOUT D^ N VOUT ) NSP VIN

VC + VF(D2))VC3

1 Efficiency

The switch saturation voltage, V(CE)SAT, is the last major source of on–chip power loss. V(CE)SAT is the collector–emitter voltage of the internal NPN transistor when it is driven into saturation by its base drive current. The value for V(CE)SAT can be obtained from the specifications or from the graphs, as “Switch Saturation Voltage.” Thus,

Therefore, C3 slows the startup of the circuit by limiting the voltage on the VC pin. The soft–start time increases with the size of C3. Diode D1 discharges C3 when SS is low. If the shutdown function is not used with this part, the cathode of D1 should be connected to VIN.

PSAT ^ V(CE)SATISW

Calculating Junction Temperature

To ensure safe operation of the CS5171/2/3/4, the designer must calculate the on–chip power dissipation and determine its expected junction temperature. Internal thermal protection circuitry will turn the part off once the junction temperature exceeds 180°C ± 30°. However, repeated operation at such high temperatures will ensure a reduced operating life. Calculation of the junction temperature is an imprecise but simple task. First, the power losses must be quantified. There are three major sources of power loss on the CS517x: • biasing of internal control circuitry, PBIAS • switch driver, PDRIVER • switch saturation, PSAT The internal control circuitry, including the oscillator and linear regulator, requires a small amount of power even when the switch is turned off. The specifications section of this datasheet reveals that the typical operating current, IQ,

D

Finally, the total on–chip power losses are PD + PBIAS)PDRIVER)PSAT

Power dissipation in a semiconductor device results in the generation of heat in the junctions at the surface of the chip. This heat is transferred to the surface of the IC package, but a thermal gradient exists due to the resistive properties of the package molding compound. The magnitude of the thermal gradient is expressed in manufacturers’ data sheets as ΘJA, or junction–to–ambient thermal resistance. The on–chip junction temperature can be calculated if ΘJA, the air temperature near the surface of the IC, and the on–chip power dissipation are known. TJ + TA)(PDJA)

where: TJ = IC or FET junction temperature (°C);


CS5171, CS5172, CS5173, CS5174 TA = ambient temperature (°C); PD = power dissipated by part in question (W); ΘJA = junction–to–ambient thermal resistance (°C/W).

combined with trace inductance generates voltage transitions that can cause problems. Therefore the following guidelines should be followed in the layout.

For ON Semiconductor components, the value for ΘJA can be found on page 1402 of the datasheet, under “Package Thermal Data.” Note that this value is different for every package style and every manufacturer. For the CS517x, ΘJA=165°C/W. Once the designer has calculated TJ, the question of whether the CS517x can be used in an application is settled. If TJ exceeds 150°C, the absolute maximum allowable junction temperature, the CS517x is not suitable for that application. If TJ approaches 150°C, the designer should consider possible means of reducing the junction temperature. Perhaps another converter topology could be selected to reduce the switch current. Increasing the airflow across the surface of the chip might be considered to reduce TA. A copper “landing pad” can be connected to the ground or VIN pins – designers are referred to ON Semiconductor applications note SR–006 for more information on properly sizing a copper area.

1. In boost circuits, high AC current circulates within the loop composed of the diode, output capacitor, and on–chip power transistor. The length of associated traces and leads should be kept as short as possible. In the flyback circuit, high AC current loops exist on both sides of the transformer. On the primary side, the loop consists of the input capacitor, transformer, and on–chip power transistor, while the transformer, rectifier diodes, and output capacitors form another loop on the secondary side. Just as in the boost circuit, all traces and leads containing large AC currents should be kept short. 2. Separate the low current signal grounds from the power grounds. Use single point grounding or ground plane construction for the best results. 3. Locate the voltage feedback resistors as near the IC as possible to keep the sensitive feedback wiring short. Connect feedback resistors to the low current analog ground.

Circuit Layout Guidelines

In any switching power supply, circuit layout is very important for proper operation. Rapidly switching currents


CS5171, CS5172, CS5173, CS5174 R2 4.87 k

2 C1 0.01 µF

C4 VC

VSW CS5172/4

1

Test

3 NFB

PGND AGND

D1

+

22 µF

7

MBRS120T3

6 +

L1 4

SS

VCC

SS

VOUT –12 V

8

5

22 µH

C3 22 µF

D2 MBRS120T3

VCC 5.0 V R1 5.0 k

R3 1.27 k

+

C2 22 µF

Figure 42. Additional Application Diagram, 5.0 V to –12 V Inverting Converter

22 µH 3.3 VIN

MBRS120T3 5.0 VO

10 µF 3.6 k

VCC (5) PGND (7)

GND

AGND (6)

22 µF GND

VSW (8)

CS5171/3 0.1 µF 5.0 k

VC (1 )

FB (2) 1.3 k

200 pF

Figure 43. Additional Application Diagram, 3.3 V Input, 5 V/ 400 mA Output Boost Converter


CS5171, CS5172, CS5173, CS5174 MBRS140T3 VCC

P6KE–15A +

22 µF

–12 V T1

1.0 µF

+

47 µF GND

VCC (5) GND

1N4148

+

1:2

47 µF

PGND (7)

VSW (8) AGND (6) CS5171/3 VC (1 )

+12 V MBRS140T3

FB (2)

47 nF

10.72 k

1.28 k

4.7 nF 2.0 k

Figure 44. Additional Application Diagram,2.7 to 13 V Input, +12 V/ 200 mA Output Flyback Converter

GND VCC (5)

VC (1 )

GND

5.0 k

2.2 µF

22 µF CS5171/3

200 pF .01 µF VIN

15 µH

VSW (8)

300

Low ESR

–5.0 VOUT

FB (2)

AGND (6) PGND (7)

1.1 k

Figure 45. Additional Application Diagram, –9.0 V to –28 V Input, –5.0 V/700 mA Output Inverted Buck Converter

22 µH VCC 2.2 µF

VCC (5) PGND (7)

GND

AGND (6)

VSW (8)

5.0 V

+

22 µF

+

CS5171/3 VC (1 ) 200 pF

22 µH FB (2)

22 µF

37.24 k

Low ESR

.01 µF 5.0 k

12.76 k

Figure 46. Additional Application Diagram,2.7 V to 28 V Input, 5.0 V Output SEPIC Converter


GND

CS5171, CS5172, CS5173, CS5174 R1

R2

1.245 k/0.1 W, 1%

99.755 k/0.1 W, 1%

GND C1

D1 C10 .1 µ C11 .01 µ

VSW 8 PGND 7

3 Test

R3 2.0 k

4 SS

CS5171/3

1 V C 2 FB

AGND VCC

.1 µ 50 V D1

C3

.1 µ 50 V D1

D1

.1 µ 50 V D1

D1

D1 100 VO

1N4148 1N4148

6 5

C2

C8 10 µ

C9 .1 µ

C7 .1 µ 50 V

1N4148 1N4148 1N4148 1N4148 1N4148

C4 .1 µ 50 V

C5 .1 µ 50 V

C6 .1 µ 50 V GND

4.0 V

Figure 47. Additional Application Diagram, 4.0 V Input, 100 V/ 10 mA Output Boost Converter with Output Voltage Multiplier

200 pF D1

C6 C1 0.01 µF

2 3

SS

FB Test

VSW 8 CS5171

5.0 k

1 V C

+

R1

4 SS

PGND

22 µF

7

L1 15 µH

AGND 6 VCC

+5.0 V

–12 V

5

D2

D3

+

C3 22 µF

+

C5 22 µF

C4 0.1 µF

GND

GND

R2

R3

1.28 k

10.72 k

+12 V

Figure 48. Additional Application Diagram, 5.0 V Input, ± 12 V Output Dual Boost Converter


CS5171, CS5172, CS5173, CS5174 ORDERING INFORMATION Operating Temperature Range

Package

Shipping

CS5171ED8

–40°C < TA < 85°C

SO–8

95 Units/Rail

CS5171EDR8

–40°C < TA < 85°C

SO–8

2500 Tape & Reel

CS5172ED8

–40°C < TA < 85°C

SO–8

95 Units/Rail

CS5172EDR8

–40°C < TA < 85°C

SO–8

2500 Tape & Reel

CS5173ED8

–40°C < TA < 85°C

SO–8

95 Units/Rail

CS5173EDR8

–40°C < TA < 85°C

SO–8

2500 Tape & Reel

CS5174ED8

–40°C < TA < 85°C

SO–8

95 Units/Rail

CS5174EDR8

2500 Tape & Reel

Device

–40°C < TA < 85°C

SO–8

CS5171GD8

0°C < TA < 70°C

SO–8

95 Units/Rail

CS5171GDR8

0°C < TA < 70°C

SO–8

2500 Tape & Reel

CS5172GD8

0°C < TA < 70°C

SO–8

95 Units/Rail

CS5172GDR8

0°C < TA < 70°C

SO–8

2500 Tape & Reel

CS5173GD8

0°C < TA < 70°C

SO–8

95 Units/Rail

CS5173GDR8

0°C < TA < 70°C

SO–8

2500 Tape & Reel

CS5174GD8

0°C < TA < 70°C

SO–8

95 Units/Rail

CS5174GDR8

0°C < TA < 70°C

SO–8

2500 Tape & Reel


8 Lead SO Narrow

Unit

RΘJC

Typical

45

°C/W

RΘJA

Typical

165

°C/W


) "( 5 6& )" ' .--. 7 The MC33463 series are micropower step–up switching voltage regulators, specifically designed for handheld and laptop applications, to provide regulated output voltages using a minimum of external parts. A wide choice of output voltages are available. These devices feature a very low quiescent bias current of 4.0 µA typical. The MC33463H–XXKT1 series features a highly accurate voltage reference, an oscillator, a variable frequency modulation (VFM) controller, a driver transistor (Lx), a comparator and feedback resistive divider. The MC33463H–XXLT1 is identical to the MC33463H–XXKT1, except that a drive pin (EXT) for an external transistor is provided. Due to the low bias current specifications, these devices are ideally suited for battery powered computer, consumer, and industrial equipment where an extension of useful battery life is desirable.

http://onsemi.com MARKING DIAGRAM xxy TAB 1

xx y zz B

SOT–89 H SUFFIX CASE 1213

zzB

= Voltage Option (30, 33, 50) = 1 = KT1, 2= LT1 = Lot Code = Lot

MC33463 Series Features:

• • • • • •

Low Quiescent Bias Current of 4.0 µA High Output Voltage Accuracy of ±2.5% Low Startup Voltage of 0.9 V at 1.0 mA Wide Output Voltage Range of 2.5 V to 7.5 V Available High Efficiency of 80% Typical Surface Mount Package

PIN CONNECTIONS MC33463H–XXKT1

! !

,9

#

(/ (/ 3 0 0! !

MC33463H–XXLT1

MC33463H–XXKT1

# ,9

! !

:L

#

(/ (/ 3 0 0! !


MC33463H–XXLT1

#

:L

Figure 1. Typical Circuit Configurations for the MC33463H



1403


MC33463 MC33463H–XXKT1 ) , #

,9

,9 ,5!

! !

*

*

)< G *!'' 1-6 30''(!

7

,

MC33463H–XXLT1

) * C

2/

#

! !

)<

:L

*

G *!''

*/

1-6 30''(!

7

XX Denotes Output Voltage This device contains 100 active transistors.

Figure 2. Representative Block Diagrams MAXIMUM RATINGS (TC = 25°C, unless otherwise noted.)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Symbol

Value

Unit


VCC

12

V


VCC

8.0

V

External Pin Voltage

VEXT

–0.3 to VO

V

Rating

Lx Pin Voltage

VLx

12

V

EXT Pin Source/Sink Current

IEXT

"50

mA

ILx

250

mA

PD RθJA

500 200

mW °C/W


TJ

125

°C


TA

–30 to +80

°C


Tstg

–40 to +125

°C

Lx Pin Sink Current

Power Dissipation and Thermal Characteristics H Suffix, Plastic Package Case 1213 (SOT–89) Maximum Power Dissipation @ TA = 25°C Thermal Resistance, Junction–to–Air


MC33463 ELECTRICAL CHARACTERISTICS (VCC = 2.0 V, IO = 10 mA and TA = 25°C, unless otherwise noted.) Characteristic

Symbol

Min

Typ

Max

Unit

Maximum Oscillator Frequency

fosc

80

100

120

kHz

Oscillator Minimum Supply Voltage (IO = 1.0 mA) KT1 Suffix

VCC

0.7

–

–

Oscillator Startup Voltage (IO = 1.0 mA) KT1 Suffix

VCC

–

0.8

0.9

Oscillator Startup Voltage (IO = 0 mA) LT1 Suffix

VCC

–

0.7

0.8

Maximum Oscillator Duty Cycle

Dmax

65

75

85

60 63 80

– – –

– – –

VLxLim

0.65

0.8

1.0

V

ILKG

–

–

0.5

µA

1.5 1.575 2.0

– – –

– – –

1.5 1.575 2.0

– – –

– – –

2.925 3.218 4.875

3.0 3.3 5.0

3.075 3.383 5.125

– – –

4.0 4.3 6.0

8.0 8.6 12

– – –

2.0 2.0 2.0

5.0 5.0 5.0

– – –

30 34.5 60

50 56 90

– – –

2.0 2.0 2.0

5.0 5.0 5.0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ OSCILLATOR

V V V

%

Lx OUTPUT (KT1 SUFFIX)

ON State Sink Current (VLx = 0.4 V) 30KT1 Suffix 33KT1 Suffix 50KT1 Suffix

ILx

mA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ VLx Voltage Limit (Note 1)

OFF State Leakage Current (VLx = 6.0 V)

EXT OUTPUT (LT1 SUFFIX)

ON State Source Current (VEXT = VO – 0.4 V) 30LT1 Suffix 33LT1 Suffix 50LT1 Suffix

Isource

mA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ OFF State Sink Current (VEXT = 0.4 V) 30LT1 Suffix 33LT1 Suffix 50LT1 Suffix

Isink

mA

TOTAL DEVICE

Output Voltage 30KT1 or 30LT1 Suffix 33KT1 or 33LT1 Suffix 50KT1 or 50LT1 Suffix

VO

Quiescent Bias Current (IO = 0 mA) 30KT1 Suffix (Vin = 1.8 V) 33KT1 Suffix 50KT1 Suffix (Vin = 3.0 V) Quiescent Bias Current (Vin = VO + 0.5 V, IO = 0 mA) 30KT1 Suffix 33KT1 Suffix 50KT1 Suffix

IQ

Quiescent Bias Current (IO = 0 mA) 30LT1 Suffix (Vin = 1.8 V) 33LT1 Suffix 50LT1 Suffix (Vin = 3.0 V) Quiescent Bias Current (Vin = VO + 0.5 V, IO = 0 mA) 30LT1 Suffix 33LT1 Suffix 50LT1 Suffix

IQ

V

µA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ µA

1. When the Lx switch is turned on, ILx carried through the RDS(on) of the Lx switch results in VLx. When VLx reaches VLxLim, the Lx switch is turned off by the Lx switch protection circuit.


1.8 1.6 1.4

IQ, QUIESCENT BIAS CURRENT (µA)


MC33463

MC33463H–50KT1 Vin = 5.5 V IO = 0 mA

1.2 1.0 0.8 0.6 0.4 0.2 0 –40

–20

0

20

40

60

60 MC33463H–50LT1 Vin = 3.0 V IO = 0 mA

50 40 30 20 10 0 –40

80

TA, AMBIENT TEMPERATURE (C)

40

D, DUTY RATIO (%)

120

80

–20

0

20

40

60

90

80

70

60 –40

80

–20

0

20

40


Figure 5. Oscillator Frequency versus Temperature

Figure 6. Oscillator Duty Ratio versus Temperature

200

60

80

60

80

0.9

160

120

40 –40

80

MC33463H–50KT1 Vin = 3.0 V IO = 10 mA


80

60

100 MC33463H–50KT1 Vin = 3.0 V IO = 10 mA

VLxLim, Lx VOLTAGE LIMIT (V)

fOSC, OSCILLATOR FREQUENCY (kHz) ILx, Lx SWITCHING CURRENT (mA)

20


180

40 –40

0



160

–20

MC33463H–50KT1 Vin = 3.0 V IO = 10 mA –20

0

20

40

60

80

0.8

0.7

0.6

MC33463H–50KT1 Vin = 3.0 V IO = 10 mA

0.5 –40

–20

0

20

40



Figure 7. Lx Switching Current versus Temperature

Figure 8. VLx Voltage Limit versus Temperature


MC33463

6

6.0

Vin = 4.0 V VO, OUTPUT VOLTAGE (V)

VO, OUTPUT VOLTAGE (V)

Vin = 4.0 V 5.0 Vin = 1.5 V

4.0

Vin = 3.0 V Vin = 2.0 V

3.0 Vin = 0.9 V

MC33463H–50KT1 L = 120 µH TA = 25°C

2.0

1.0 0

20

40

60

80

100

5 Vin = 3.0 V

Vin = 1.5 V

3 2

MC33463H–50LT1 L = 28 µH TA = 25°C

1 0

120

Vin = 2.0 V

Vin = 0.9 V

4

0

200

400

600





100

100 Vin = 4.0 V

60 Vin = 0.9 V Vin = 1.5 V

Vin = 2.0 V

40 MC33463H–50KT1 L = 120 µH TA = 25°C

0 0

Vstart/Vhold, STARTUP/HOLD VOLTAGE (V)

EFFICIENCY (%)

Vin = 3.0 V

20

20

Vin = 3.0 V 60

40

20

40

60

80

Vin = 1.5 V

Vin = 2.0 V

Vin = 0.9 V MC33463H–50LT1 L = 28 µH TA = 25°C

0 0

100

200

400

600



Figure 11. Efficiency versus Output Current


2.0

1.6

1.2 Vstart 0.8

0.4

0 0

Vin = 4.0 V

80

Vstart/Vhold, VOLTAGE LIMIT (V)

EFFICIENCY (%)

80

MC33463H–50KT1 L = 82 µH TA = 25°C

Vhold

2.0

4.0

6.0

8.0

12

10

1.5

1.0

Vstart

Vhold

MC33463H–50KT1 L = 28 µH TA = 25°C

0.5

0 0

20

40

60

80

100



Figure 13. Startup/Hold Voltage versus Output Current



120


MC33463


6.1

5.0

4.9 MC33463H–50KT1 L = 120 µH 4.8 –40

–20

0

20

40

60

80

1.0

Vstart

0.8

0.6 Vhold 0.4

0.2 –40

MC33463H–50KT1 L = 120 µH IO = 1.0 mA –20

0

20

40

60




Figure 16. Startup/Hold Voltage versus Temperature

DEFINITIONS

80

discrete components, as shown in Figure 19, or a micropower undervoltage sensor, as shown in Figure 20.

Quiescent Bias Current – Current which is used to operate the switching regulator chip and is not delivered to the load. Leakage Current – Current drawn through a transistor junction, under a specified collector voltage, when the transistor is off.

Oscillator

The maximum oscillator frequency, is internally programmed to 100 kHz. The duty ratio of the oscillator is designed for a constant value of 0.75 nominal. Hence the nominal on–time of the power switch is:

FUNCTIONAL DESCRIPTION

ton + D + 0.75 + 7.5 µs f osc (100 kHz)

Introduction

The MC33463 series are monolithic power switching regulators optimized for dc–to–dc converter applications where power drain must be minimized. The combination of features in this series allows the system designer to directly implement step–up, step–down or flyback converters with a small number of external components. Potential applications include low power consumer products and battery powered portable products. Typical application circuits are shown in Figure 17 and Figure 18.

Feedback Comparator

The output voltage is sensed and fed to a high speed comparator noninverting input through an internal resistive divider. The comparator inverting input is connected to an internally trimmed to 0.7 V reference. With a voltage mode ripple converter operating under normal conditions, output switch conduction is initiated and terminated by the oscillator, off–time is controlled by the high speed voltage feedback comparator.


Driver and Output Switch

The MC33463 series converters each operate as a fixed on–time, variable off–time voltage mode ripple regulator. Operation is intended to be in the discontinuous mode, where the inductor current ramps up to a peak value which is greater than or equal to twice the value of the dc input current during the on–time of the transistor switch. During the off–time of the transistor switch, the inductor current ramps down to zero and remains at zero until another switching cycle begins. Because the output voltage pin is also used as the supply voltage for powering internal circuitry, an external startup circuit is needed in step–down and flyback converter designs to provide initial power to the integrated circuit to begin switching. The startup circuit needed can be three

To aid in system design flexibility and conversion efficiency, two output driver options are provided. The MC33463H–XXKT1 converters have an internal drive transistor which is capable of sinking currents greater than 60 mA into the Lx pin. An internal VLx limiter circuit senses if the Lx pin voltage exceeds 1.0 V during ton and turns off the drive transistor. The MC33463H–XXLT1 provides output drive for an external transistor. Applications

The following converter applications show the simplicity and flexibility of the converter architecture. Three main converter topologies are demonstrated in Figures 17 through 21.


MC33463 G2) , µ

MC33463H–XXKT1

# ,9

µ

Figure 17. MC33463H–50KT1 Typical Step–Up Application

G2) ,

µMC33463H–XXLT1

GG

;,

#

#

µ

:L

$ µ

Figure 18. MC33463H–50LT1 Typical Step–Up Application


MC33463 !(! *0 ! GG

;, $ 1 JL"*##, #$#

" µH GG ;,

#$# G2) ,

$ 1 µF

MC33463H–33KT1 # ,9

,9 ,5!

! ! µF

)< G *!'' 1-6 30''(!

7

Figure 19. MC33463H–33KT1 Step–Down Application

Test

Conditions

Results

Line Regulation

Vin = 5.0 V to 8.0 V, IO = 100 mA

18.5 mV = ±0.3%

Load Regulation

Vin = 5.0 V, IO = 1.0 mA to 100 mA

5.7 mV = ±0.1%

Output Ripple

Vin = 5.0 V, IO = 100 mA

40 mVpp

Efficiency

Vin = 5.0 V, IO = 100 mA

60.3%


MC33463 !(! *0 ! G*##""%#;2

GG ;,

+ #

!

1

1

" µH GG ;,

#$# G2) ,

$ 1 µF

MC33463H–33KT1 # ,9

,9 ,5!

! !

µF

)< G *!''

1-6 30''(!

7

Figure 20. Micropower Step–Down Application


MC33463 GG

;, $ 1

!(! *0 !

#$#

GG ;,

$ 1 µF

MC33463H–33KT1 #

,9 ,5!

,9

! !

)<

µF

G *!'' 1-6 30''(!

7

Figure 21. Flyback Application

Calculation

Step–Down

Step–Up

Flyback

ton

D f osc

D f osc

D f osc

L t t on

ƪ

IL(avg)

(V

in

* V sat * V ) O (2I ) O

ƫ

(n)(V )2(ton) in P O

t

IO

IL(pk)

(V

Vripple(pp) I

in

(n)(V )2(ton) in P O

Iin

* V sat * V )(t on) O L

ȱǒ 1 Ǔ Lȧ 16f oscC O Ȳ

t

(V

in

* V sat)(t on) L

1 2

2 ) (ESR)

ȳ ȧ ȴ

[

2

(t on)(I ) O (C ) O

Iin (V

in

* V sat)(t on) L

[

(t on)(I ) O (C ) O

The following converter design characteristics must be chosen: Vin – Nominal Operating dc input voltage VO – Desired dc output voltage IO – Desired dc output current Vripple(pp) – Desired peak–to–peak output ripple voltage. For best performance the ripple voltage should be kept to a low value since it will directly affect line and load regulation. Capacitor CO should be a low equivalent series resistance (ESR) electrolytic designed for switching regulator applications. 1. Vsat – Saturation voltage of the switching transistor. n – Estimated circuit efficiency.

Figure 22. Design Equations



Output Voltage

MC33463H–30KT1

3.0

MC33463H–33KT1

3.3

MC33463H–50KT1

5.0

MC33463H–30LT1

3.0

MC33463H–33LT1

3.3

MC33463H–50LT1

5.0

Type


Package

Shipping

TA = –30° 30° to +80°C

SOT 89 SOT–89

1000 Tape & Reel

I t Int. Switch

Ext. Switch Di Drive

Other voltages from 2.5 V to 7.5 V, in 0.1 V increments are available. Consult factory for information.


) 5"% 5 6& 81) )" ' .--. 7 The MC33466 series are micropower switching voltage regulators, specifically designed for handheld and laptop applications, to provide regulated output voltages using a minimum of external parts. A wide choice of output voltages are available. These devices feature a very low quiescent bias current of 15 µA typical. The MC33466H–XXJT1 series features a highly accurate voltage reference, an oscillator, a pulse width modulation (PWM) controller, a driver transistor (Lx), an error amplifier and feedback resistive divider. The MC33466H–XXLT1 is identical to the MC33466H–XXJT1, except that a drive pin (EXT) for an external transistor is provided. Due to the low bias current specifications, these devices are ideally suited for battery powered computer, consumer, and industrial equipment where an extension of useful battery life is desirable.

http://onsemi.com MARKING DIAGRAM TAB 1

xxy SOT–89 H SUFFIX CASE 1213 yzz

xx yy zz

= Voltage Option (30, 33, 50) = 1A = JT1, 2B= LT1 = Lot Code

MC33466 Series Features:

• • • • •

Low Quiescent Bias Current of 15 µA High Output Voltage Accuracy of ±2.5% Low Startup Voltage of 0.9 V at 1.0 mA Soft–Start = 500 µs Surface Mount Package

PIN CONNECTIONS MC33466H–XXJT1

! !

,9

#

(/ (/ 3 0 0! !

MC33466H–XXLT1

! !

:L

#

(/ (/ 3 0 0! !




1414


MC33466 MC33466H–XXJT1 )

, #

,9 ,5!

,9

*

! ! '!( /(01

)<

*

IG *!'' 4(3 *5

1-6 30''(!

7

7!%!(!

MC33466H–XXLT1

,

)

*

2/ C

# :L

*/

! ! '!( /(01

)<

*

IG *!'' 1-6 30''(!

4(3 *5 7!%!(!

7

LL ) ! 3 ! ! '!( This device contains 100 active transistors.

Figure 1. Representative Block Diagrams

MAXIMUM RATINGS (TC = 25°C, unless otherwise noted.)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating

Symbol

Value

Unit


VO

12

V


VO

8.0

V

External Pin Voltage

VEXT

–0.3 to VO

V

Lx Pin Voltage

VLx

12

V

EXT Pin Source/Sink Current

IEXT

"50

mA

ILx

250

mA

PD RθJA

500 200

mW °C/W


TJ

125

°C


TA

–30 to +80

°C


Tstg

–40 to +125

°C

Lx Pin Sink Current

Power Dissipation and Thermal Characteristics H Suffix, Plastic Package Case 1213 (SOT–89) Maximum Power Dissipation @ TA = 25°C Thermal Resistance, Junction–to–Air



MC33466 ELECTRICAL CHARACTERISTICS (VCC = 2.0 V, IO = 10 mA and TA = 25°C, unless otherwise noted.) Characteristic

Symbol

Min

Typ

Max

Unit

40 80

50 100

60 120

–

0.8

0.9

0.7

–

–

–

0.7

0.8

60 63 80

– – –

– – –

VLxLim

0.65

0.8

1.0

V

ILKG

–

–

0.5

µA

1.5 1.575 2.0

– – –

– – –

1.5 1.575 2.0

– – –

– – –

70

80

90

2.925 3.218 4.875

3.0 3.3 5.0

3.075 3.383 5.125

0.5

2.0

–

– – –

15 17 30

25 27 45

– – –

2.0 2.0 2.0

5.0 5.0 5.0

– – –

30 34.5 60

50 56 90

– – –

2.0 2.0 2.0

5.0 5.0 5.0

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ OSCILLATOR Frequency JT1 Suffix LT1 Suffix

fosc

Oscillator Minimum Startup Voltage (IO = 1.0 mA) JT1 Suffix

Vstart

Oscillator Minimum Supply Voltage (IO = 1.0 mA) JT1 Suffix

VCC

Oscillator Startup Voltage (IO = 0 mA) LT1 Suffix

Vstart

kHz

V V V

LX OUTPUT (JT1 SUFFIX)

ON State Sink Current (VLx = 0.4 V) 30JT1 Suffix 33JT1 Suffix 50JT1 Suffix

ILx

mA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ VLx Voltage Limit (Note 1)

OFF State Leakage Current (VLx = 6.0 V)

EXT OUTPUT (LT1 SUFFIX)

ON State Source Current (VEXT = VO – 0.4 V) 30LT1 Suffix 33LT1 Suffix 50LT1 Suffix

Isource

mA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ OFF State Sink Current (VEXT = 0.4 V) 30LT1 Suffix 33LT1 Suffix 50LT1 Suffix

Isink

mA

TOTAL DEVICE

Maximum Duty Ratio Each Cycle

D

Output Voltage 30JT1 or 30LT1 Suffix 33JT1 or 33LT1 Suffix 50JT1 or 50LT1 Suffix

VO

Soft–Start Time (Note 2)

Tss

Quiescent Bias Current (IO = 0 mA) 30JT1 Suffix (Vin = 1.8 V) 33JT1 Suffix 50JT1 Suffix (Vin = 3.0 V) Quiescent Bias Current (Vin = VO + 0.5 V, IO = 0 mA) 30JT1 Suffix 33JT1 Suffix 50JT1 Suffix

IQ

Quiescent Bias Current (IO = 0 mA) 30LT1 Suffix (Vin = 1.8 V) 33LT1 Suffix 50LT1 Suffix (Vin = 3.0 V) Quiescent Bias Current (Vin = VO + 0.5 V, IO = 0 mA) 30LT1 Suffix 33LT1 Suffix 50LT1 Suffix

IQ

% V

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ms µA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ µA

1. When the Lx switch is turned on, ILx current carried through the RDS(on) of the Lx switch results in VLx. When VLx reaches VLxLim, the Lx switch is turned off by the Lx switch protection circuit. 2. The soft–start circuit turn–on sequence is as follows: a) Vin is applied. b) The internal IC Vref is held at zero for 200 µs. During this time, the error amplifier output voltage ramps up to the positive voltage rail. c) The internal reference steps up to 0.7 V after 200 µs delay has timed out. d) The error amplifier output voltage integrates down to its steady state value. As the error amplifier output integrates down, the output Lx pin of EXT pin pulse width gradually widens to its steady operating value.


MC33466

MC33466H–50JT1 IO = 0 mA 80 Vin = 3.0 V

60

40

20

0 –40

fOSC, OSCILLATOR FREQUENCY (kHz)


100

20

0

20

40

60

MC33466H–50JT1 IO = 0 mA Vin = 5.5 V

4

3

2

1

20

0

20

40

60

80





100

100 MC33466H–50JT1 L = 120 µH IO = 10 mA Vin = 3.0 V

80

60

40

20 –40

20

0

20

40

60

MC33466H–50JT1 L = 120 µH IO = 10 mA 90 Vin = 3.0 V

80

70

60 –40

80

20

0

20

40




Figure 5. Maximum Duty Ratio versus Temperature

200

160

120

80

40

60

80

60

80

1.0 VLxLim, VLx VOLTAGE LIMIT (V)

ILx, Lx SWITCHING CURRENT (mA)

5

0 –40

80

Dmax, MAXIMUM DUTY RATIO (%)


TYPICAL APPLICATIONS

MC33466H–50JT1 IO = 10 mA Vin = 3.0 V

0 –40

20

0

20

40

60

80

0.9

0.8

0.7

0.6

MC33466H–50JT1 IO = 10 mA Vin = 3.0 V

0.5 –40


20

0

20

40


Figure 6. Lx Switching Current versus Temperature


Figure 7. VLx Voltage Limit versus Temperature

MC33466 TYPICAL APPLICATIONS 6.0 VO, OUTPUT VOLTAGE (V)


6.0

5.0

4.0

Vin = 2.0 V

3.0

Vin = 4.0 V

Vin = 3.0 V

Vin = 1.0 V MC33466H–50JT1 L = 120 µH TA = 25°C

2.0

1.0 0

20

40

60

80

100

Vin = 4.0 V

5.0 Vin = 2.0 V 4.0

Vin = 1.5 V

3.0 MC33466H–50LT1 L = 28 µH TA = 25°C

2.0

1.0 0

120

100


300

400

500

600


3.1

3.1 MC33466H–30JT1 L = 120 µH TA = 25°C

3.0



200



2.9 2.8 Vin = 1.5 V

2.7 2.6 Vin = 1.0 V 2.5 0

Vin = 1.5 V

2.8 0

60

Vin = 2.5 V

2.9 MC33466H–30LT1 L = 28 µH TA = 25°C

Vin = 0.9 V

40

20

Vin = 2.0 V

3.0

Vin = 2.0 V

200

400

600





100

100

90

80

80

EFFICIENCY (%)

EFFICIENCY (%)

Vin = 3.0 V

Vin = 4.0 V

Vin = 3.0 V

70 Vin = 2.0 V 60 Vin = 1.0 V

MC33466H–50JT1 L = 120 µH TA = 25°C

40 0

50

100

60

40

Vin = 2.0 V

Vin = 1.5 V

MC33466H–50LT1 L = 28 µH TA = 25°C

20

50

150

Vin = 4.0 V

Vin = 3.0 V

0 0

500 IO, OUTPUT CURRENT (mA)



Figure 13. Effciency versus Output Current


1000

MC33466 TYPICAL APPLICATIONS 100

100 Vin = 2.0 V

80 EFFICIENCY (%)

EFFICIENCY (%)

80

Vin = 1.5 V 60

Vin = 1.0 V

40

MC33466H–30JT1 L = 120 µH TA = 25°C Figure 22

20

MC33466H–30LT1 L = 28 µH TA = 25°C Figure 23

40 Vin = 0.9 V 20

5.0

10

15

20

25

0

30

100

200

300

400

500

600





1.6 Vstart/Vhold, VOLTAGE LIMIT (V)

1.6 Vstart/Vhold, VOLTAGE LIMIT (V)

Vin = 1.5 V

0

0 0

1.2 Vstart 0.8 Vhold

MC33466H–50JT1 L = 120 µH TA = 25°C Figure 22

0.4

0 0

10

20

1.4

1.2 Vstart 1.0

0.8

0.6 0

30

20

4.9

4.8 –20

0

20

40

60

80


5.0

–40

60

80

100

120


MC33466H–50JT1 L = 120 µH IO = 10 mA Vin = 3.0 V Figure 22

5.1

40



5.2

MC33466H–50LT1 L = 28 µH TA = 25°C Figure 23

Vhold



Vin = 2.5 V

Vin = 2.0 V 60

1.0

0.8

Vstart

0.6 Vhold MC33466H–50JT1 L = 120 µH IO = 3.0 mA Figure 22

0.4

0.2 –40

–20

0

20

40

60




Figure 19. Startup/Hold Voltage versus Temperature


80

MC33466 TYPICAL APPLICATIONS

200

5.4

150

100

50

5.2

MC33466H–50JT1 L = 120 µH IO = 1.0 to 30 mA Vin = 3.0 V Figure 22

200

150 5.0 100 4.8 50 4.6

0 0

1.0

2.0

3.0

4.0

5.0

0

6.0

10

20

30

40

50

t, TIME (ms)


Figure 20. Supply Current versus Input Voltage



0 60


250 MC33466H–50JT1 L = 120 µH IO = 0 mA Figure 22


ICC, SUPPLY CURRENT (µA)

250

MC33466 Error Amplifier and Reference

DEFINITIONS Quiescent Bias Current – Current which is used to operate the switching regulator chip and is not delivered to the load. Leakage Current – Current drawn through a transistor junction, under a specified collector voltage, when the transistor is off.

An Error Amplifier is provided which has a nominal 80 dB of voltage gain at dc. Internal compensation components provide poles at 0.25 Hz, 30 kHz and 33 kHz. Two zeros are provided at 1.0 kHz and at 2.5 kHz. The output voltage value is set by the internal voltage divider and a 0.7 V reference which is trimmed to an accuracy of ±2.5%. Because the loop compensation components are located within the IC, discontinuous mode operation is recommended for most applications.

FUNCTIONAL DESCRIPTION Introduction

The MC33466 series are monolithic power switching regulators optimized for dc–to–dc converter applications where power drain must be minimized. The combination of features in this series allows the system designer to directly implement step–up, step–down or flyback converters with a small number of external components. Potential applications include low power consumer products and battery powered portable products. Typical application circuits are shown in Figures 22 through 26.


To aid in system design flexibility and conversion efficiency, two output driver options are provided. The MC33466H–XXJT1 converters have an internal drive transistor which is capable of sinking currents greater than 60 mA into the Lx pin. An internal VLx limiter circuit senses if the Lx pin voltage exceeds 1.0 V during ton and turns off the drive transistor. The MC33466H–XXLT1 provides output drive for an external transistor.


Applications

The MC33466 series converters operate as a fixed frequency voltage mode regulator. Operation is intended to be in the discontinuous mode, where the inductor current ramps up to a peak value which is greater than or equal to twice the value of the dc input current during the on–time of the transistor switch. During the off–time of the transistor switch, the inductor current ramps down to zero and remains at zero until another switching cycle begins. Because the output voltage pin is also used as the supply voltage for powering internal circuitry, an external startup circuit is needed in step–down converter and flyback designs to provide initial power to the integrated circuit to begin switching. The startup circuit needed can be three discrete components, as shown in Figure 24, or a micropower undervoltage sensor, as shown in Figure 25.

The following converter applications show the simplicity and flexibility of the converter architecture. Three main converter topologies are demonstrated in Figures 22 through 26. G2) , µ

MC33466H–50JT1

# ,9

µ

µ

Oscillator

The oscillator frequency, is internally programmed to 50 kHz for the JT1 suffix and 100 kHz for the LT1 suffix. The timing capacitor (CT) discharge to charge ratio of the oscillator is designed for a maximum duty cycle of 80% at the Lx or EXT output. During the charge of CT, the oscillator generates an internal blanking pulse that holds the PWM control off, disabling the output transistor drive. The oscillator peak and valley thresholds are 0.5 V and ground, respectively.

Figure 22. MC33466H–50JT1 Typical Step–Up Application G2) ,

µ

MC33466H–50LT1

µ

Pulse Width Modulator

The Pulse Width Modulator consists of a comparator with the oscillator ramp voltage applied to the inverting input, while the error amplifier output is applied to the noninverting input. Output switch conduction is initiated when the timing capacitor is charged to its peak voltage value. When the timing capacitor ramp discharges to a voltage below the error amplifier output, the comparator resets a latch terminating output transistor drive for the duration of the oscillator ramp period.

GG

;,

#

$ µ

#

µ

:L

Figure 23. MC33466H–50LT1 Typical Step–Up Application


$

MC33466 !(! *0 ! GG

;, $ 1 JL"*##, #$# " µH GG ;,

G2) ,

$ 1

## µF

#$# # 5;

MC33466H–33JT1 # ,9

,9 ,5!

! !

)< IG *!'' 1-6 30''(!

## µF 4(3 *5 7!%!(!

7

Figure 24. MC33466H–33JT1 Step–Down Application

Test

Condition

Results

Line Regulation

Vin = 5.0 V to 10 V, IO = 320 mA

7.0 mV = ±0.1%

Load Regulation

Vin = 7.0 V, IO = 3.3 mA to 320 mA

3.0 mV = ±0.04%

Output Ripple

Vin = 7.0 V, IO = 320 mA

70 mVpp

Efficiency

Vin = 7.0 V, IO = 320 mA

63.8%


## µF

MC33466 !(! *0 ! G*##""%#;2

GG

;,

+ #

!

1 1 " µH

GG ;,

$ µF

#$# # 5;

G2) ,

$ 1

MC33466H–33JT1 # ,9

,9 ,5!

! ! µF

)< IG *!'' 1-6 30''(!

4(3 *5 7!%!(!

7

NOTE: Using the MC33464N–30ATR reduces current drawn in the startup circuit to 1 mA during normal operation.

Figure 25. Micropower Step–Down Application


MC33466 !(! *0 !

$ 1 GG

;, #$#

GG ;,

µF

#$#

$ 1

MC33466H–33JT1

# ,9

,9 ,5!

! ! µF

)< IG *!'' 1-6 30''(!

4(3 *5 7!%!(!

7

Figure 26. Flyback Application


MC33466 Step–Down

Calculation L

t

(V

ton

in

Step–Up

– V )(t on) O 2I O

t

(V )(ton) in 2I in

D fs (V ) O t (V ) in

t

(V

IO

IL(pk)

(V

in

t

D fs

D

IL(avg)

Flyback

D fs

* V ) in O (V ) O

t

V

ƪǒ Ǔ

(V

Vripple(pp)

in

O

Ns (V ) ) V in O Np

Iin

* V )(t on) O L

(V )(ton) in 2I in

ƫ

Iin

* V sat)(t on) L

(V

in

* V sat)(t on) L

1

ȱǒ 1 Ǔ2 ) (ESR)2ȳ2 I ȧ L(pk)ȧ 8fsC Ȳ O ȴ

The following converter design characteristics must be chosen: Vin – Nominal Operating dc input voltage VO – Desired dc output voltage IO – Desired dc output current Vripple(pp) – Desired peak–to–peak output ripple voltage. For best performance the ripple voltage should be kept to a low value since it will directly affect line and load regulation. Capacitor CO should be a low equivalent series resistance (ESR) electrolytic designed for switching regulator applications. D – Operating duty cycle = ton(fs). This parameter must be chosen to be IPK Reverse voltage larger than output voltage, Vreverse > VOUT

(Vin * Vs)ton

toff

Vripple

Diode

(IL * IO)toff [

Q ) (IL * IO)ESR COUT

Peak inductor current Minimum inductor current Desired dc output current Desired maximum dc output current Average inductor current Nominal operating dc input voltage Desired dc output voltage Diode forward voltage Saturation voltage of the internal FET switch Charge stores in the COUT during charging up Output ripple voltage Equivalent series resistance of the output capacitor An empirical factor, when VOUT ≥ 3.0 V, M = 8 x 10–6, otherwise M = 5.3 x 10–6.

Input Capacitor

EXTERNAL COMPONENT SELECTION

The input capacitor can stabilize the input voltage and minimize peak current ripple from the source. The value of the capacitor depends on the impedance of the input source used. Small ESR (Equivalent Series Resistance) Tantalum or ceramic capacitor with value of 10 F should be suitable.

Inductor

The NCP1402 is designed to work well with a 47 H inductor in most applications. 47 H is a sufficiently low value to allow the use of a small surface mount coil, but large


NCP1402 Output Capacitor

An evaluation board of NCP1402 has been made in the size of 23 mm x 20 mm only, as shown in Figures 60 and 61. Please contact your ON Semiconductor representative for availability. The evaluation board schematic diagram, the artwork and the silkscreen of the surface–mount PCB are shown below:

The output capacitor is used for sustaining the output voltage when the internal MOSFET is switched on and smoothing the ripple voltage. Low ESR capacitor should be used to reduce output ripple voltage. In general, a 47 uF to 68 uF low ESR (0.15 to 0.30 ) Tantalum capacitor should be appropriate. For applications where space is a critical factor, two parallel 22 uF low profile SMD ceramic capacitors can be used.

20 mm

23 mm

Figure 60. NCP1402 PFM Step–Up DC–DC Converter Evaluation Board Silkscreen

20 mm

23 mm

Figure 61. NCP1402 PFM Step–Up DC–DC Converter Evaluation Board Artwork (Component Side)


NCP1402 Components Supplier Supplier

Part Number

Inductor, L1

Parts

Sumida Electric Co. Ltd.

CD54–470L

Schottky Diode, D1

ON Semiconductor Corp.

MBR0520LT1

Description

Phone

Inductor 47 H / 0.72 A

(852)–2880–6688

Schottky Power Rectifier

(852)–2689–0088 (852)–2305–1168 (852)–2305–1168

Output Capacitor, C2

KEMET Electronics Corp.

T494D686K010AS

Low ESR Tantalum Capacitor 68 F / 10 V

Input Capacitor, C1


T491C106K016AS

Low Profile Tantalum Capacitor 10 F / 16 V

PCB Layout Hints Grounding

efficiency (short and thick traces for connecting the inductor L can also reduce stray inductance), e.g. : short and thick traces listed below are used in the evaluation board: 1. Trace from TP1 to L1 2. Trace from L1 to Lx pin of U1 3. Trace from L1 to anode pin of D1 4. Trace from cathode pin of D1 to TP2

One point grounding should be used for the output power return ground, the input power return ground, and the device switch ground to reduce noise as shown in Figure 62, e.g. : C2 GND, C1 GND, and U1 GND are connected at one point in the evaluation board. The input ground and output ground traces must be thick enough for current to flow through and for reducing ground bounce.

Output Capacitor Power Signal Traces

The output capacitor should be placed close to the output terminals to obtain better smoothing effect on the output ripple.

Low resistance conducting paths should be used for the power carrying traces to reduce power loss so as to improve

L1

TP1 Vin

47 µH

C1 10 µF/16 V

TP4 GND

TP2

+

JP1 Enable

On Off

LX

CE 1 OUT NCP1402 2 NC

Vout

D1 MBR0520LT1 +

5

GND 6

3

Figure 62. NCP1402 Evaluation Board Schematic Diagram


C2 68 µF/10 V TP3 GND

28 / &- 85) '-9' .-. 7 "# - & . NCP1410 is a monolithic micropower high frequency Boost (step–up) voltage switching converter IC specially designed for battery operated hand–held electronic products up to 250 mA loading. It integrates Synchronous Rectifier for improving efficiency as well as eliminating the external Schottky Diode. High switching frequency (up to 600 kHz) allows low profile inductor and output capacitor being used. Low–Battery Detector, Logic–Controlled Shutdown and Cycle–by–Cycle Current Limit provide value–added features for various battery–operated applications. With all these functions ON, the device quiescent supply current is only 9.0 µA typical. This device is available in space saving compact Micro8 package.

http://onsemi.com MARKING DIAGRAM 8 Micro8 DM SUFFIX CASE 846A

8

A1 AYW

1 1

Features

• • • • • • • • • • • • • •

High Efficiency up to 92% Very Low Device Quiescent Supply Current of 9.0 A Typical Allows use of Small Size Inductor and Capacitor Built–in Synchronous Rectifier (PFET) Eliminates One External Schottky Diode High Switching Frequency (up to 600 kHz) Allows Use of Small Size Inductor and Capacitor High Accuracy Reference Output, 1.19 V ± 0.6% @ 25°C, can supply more than 2.5 mA when VOUT ≥ 3.3 V 1.0 V Startup at No Load Guaranteed Output Voltage from 1.5 V to 5.5 V Adjustable Output Current up to 250 mA @ Vin = 2.5 V, Vout = 3.3 V Logic–Controlled Shutdown Open Drain Low–Battery Detector Output 1.0 A Cycle–by–Cycle Current Limit Low Profile and Minimum External Parts Compact Micro8 Package


• • • • •

A1 = Device Marking A = Assembly Location Y = Year W = Work Week

PIN CONNECTIONS FB 1

8 OUT

LBI 2

7 LX

LBO 3

6 GND

REF 4

5 SHDN (Top View)

ORDERING INFORMATION Device NCP1410DMR2

Package

Shipping

Micro8

4000 Tape & Reel

Personal Digital Assistant (PDA) Handheld Digital Audio Product Camcorders and Digital Still Camera Hand–held Instrument Conversion from One or Two NiMH or NiCd, or One Li–ion Cell to 3.3 V/5.0 V



1458


NCP1410 Input 1.0 V to VOUT 10 µF

150 pF

22 µF

500 k

360 k +

200 k Low Battery Sense Input

LBI

Low Battery Open Drain Output

Output 1.5 V to 5.5 V IOUT typical up to 33 µF 250 mA at 3.3 V Output and 2.5 V Input

VOUT

FB NCP1410

LX

LBO

GND

REF

SHDN

150 nF

56 nF

Shutdown Open Drain Input

Figure 1. Typical Operating Circuit

MAXIMUM RATINGS (Note 1) Rating

Symbol

Value

Unit

VOUT

–0.3 to 6.0

V

VIO

–0.3 to 6.0

V

PD RθJA

520 240

mW °C/W


TJ

–40 to +150

°C


TA

–40 to +85

°C


Tstg

–55 to +150

°C

Device Power Supply (Pin 8) Input/Output Pins Pin 1–5, Pin 7 Thermal Characteristics Micro8 Plastic Package Maximum Power Dissipation @ TA = 25°C Thermal Resistance Junction to Air

1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) $2.0 kV per JEDEC standard: JESD22–A114. Machine Model Method (MM) $200 V per JEDEC standard: JESD22–A115. 2. The maximum package power dissipation limit must not be exceeded. TJ(max) * TA PD + RJA 3. Latch–up Current Maximum Rating: $150 mA per JEDEC standard: JESD78. 4. Moisture Sensitivity Level: MSL 1 per IPC/JEDEC standard: J–STD–020A.


NCP1410 ELECTRICAL CHARACTERISTICS (VOUT = 3.3 V, TA = 25°C for typical value, –40°C ≤ TA ≤ 85°C for min/max values unless otherwise noted.) Characteristics

Symbol

Min

Typ

Max

Unit

VIN

1.0

–

5.5

V

VOUT

VIN

–

5.5

V

VREF_NL

1.183

1.190

1.197

V

VREF_NL_A

1.178

–

1.202

V

TCVREF

–

0.03

–

mV/°C

Reference Voltage Load Current (VOUT = 3.3 V, VREF = VREF_NL ±1.5%, CREF = 1.0 F) (Note 5)

IREF

2.5

–

–

mA

Reference Voltage Load Regulation (VOUT = 3.3 V, IREF = 0 to 100 A, CREF = 1.0 F)

VREF_LOAD

–

0.015

1.0

mV

Reference Voltage Line Regulation (VOUT from 1.5 V to 5.5 V, CREF = 1.0 F)

VREF_LINE

–

0.03

1.0

mV/V

FB, LBI Input Threshold (ILOAD = 0 mA)

VFB, VLBI

1.174

1.190

1.200

V

N–FET ON Resistance

RDS(ON)–N

0.6

P–FET ON Resistance

RDS(ON)–P

0.9

Operating Voltage Output Voltage Range (Adjusted by external feedback) Reference Voltage (CREF = 150 nF, under no loading, TA = 25°C) Reference Voltage (CREF = 150 nF, under no loading, –40°C ≤ TA ≤ 85°C) Reference Voltage Temperature Coefficient

LX Switch Current Limit (NFET)

ILIM

–

1.0

–

A

Operating Current into OUT (VFB = 1.4 V, i.e. No switching, VOUT = 3.3 V)

IQ

–

9.0

14

A

Shutdown Current into OUT (SHDN = GND)

ISD

–

0.05

1.0

A

LX Switch MAX. ON–Time (VFB = 1.0 V, VOUT = 3.3 V)

tON

1.2

1.4

1.8

S

LX Switch MIN. OFF–Time (VFB = 1.0 V, VOUT = 3.3 V)

tOFF

0.25

0.31

0.37

S

FB Input Current

IFB

–

1.5

9.0

nA

LBI Input Current

ILBI

–

1.5

8.0

nA

VLBO_L

–

–

0.05

V

ISHDN

–

1.5

8.0

nA

SHDN Input Threshold, Low

VSHDN_L

–

–

0.3

V

SHDN Input Threshold, High

VSHDN_H

0.6

–

–

V

LBO Low Output Voltage (VLBI = 0, ISINK = 1.0 mA) SHDN Input Current

5. Loading capability increases with VOUT.


NCP1410 PIN FUNCTION DESCRIPTIONS Pin #

Symbol

Pin Description

1

FB

Output Voltage Feedback Input.

2

LBI

Low–Battery Detector Input.

3

LBO

Open–Drain Low–Battery Detector Output. Output is LOW when VLBI is t1.178 V. LBO is high impedance during shutdown.

4

REF

1.190 V Reference Voltage Output, bypass with 150 nF capacitor if this pin is not loaded, bypass with 1.0 F if this pin is loaded up to 2.5 mA @ VOUT = 3.3 V.

5

SHDN

6

GND

7

LX

8

OUT

Shutdown Input. HIGH (u 0.6 V) = operating; LOW (t 0.3 V) = shutdown. Ground. N–Channel and P–Channel Power MOSFET Drain Connection. Power Output. OUT provides bootstrap power to the IC.

Vbat

L ZLC + –

Vbat 5 RSHDN SHDN

_ZCUR

PFM + –

OUT CONTROL LOGIC

VDD

CFB1 RFB1 SENSEFET

_MAINSW2ON

_CEN GND

_PFM

REF CREF

Voltage Reference

COUT

6

M1

RFB2

VDD

_MAINSWOFD

GND

_SYNSW2ON 4

GND

_VREFOK _SYNSWOFD _ILIM

+ –

+

ILIM

RSENSE 3 GND

2

VOUT

8

M2

Chip Enable _PWGONCE

FB

VDD LX

20 mV

CSHDN

1

7 +

LBO

+ –

LBI GND

Figure 2. Simplified Functional Diagram


NCP1410 TYPICAL OPERATING CHARACTERISTICS 1.195 VOUT = 3.3 V L = 22 µH CIN = 10 µF COUT = 33 µF CREF = 1.0 µF TA = 25°C

1.208 1.204

REFERENCE VOLTAGE, VREF/V


1.212

VIN = 2.2 V VIN = 1.8 V

1.2 1.196 VIN = 3.0 V 1.192 1.188 1.0

1000

10 100 OUTPUT CURRENT, ILOAD/mA

1.193 IREF = 0 mA 1.190 1.188 IREF = 2.5 mA 1.185 CREF = 1.0 F TA = 25°C

1.183 1.180 1.5

Figure 3. Reference Voltage vs. Output Current

SWITCH ON RESISTANCE, RDS(ON)/


1.192

1.190

1.188 VOUT = 3.3 V CREF = 150 nF IREF = 0 mA –20

0

20

40

60

80

100

5.5

1.8 1.6 1.4 1.2

P–FET (M2)

1.0 0.8 0.6

N–FET (M1)

0.4 0.2 0 –40

–20

0

20

40

60

80

100

AMBIENT TEMPERATURE, TA/°C



Figure 6. Switch ON Resistance vs. Temperature

1.8

2.0

1.7

1.8

MINIMUM STARTUP BATTERY VOLTAGE, VBATT/V

LX SWITCH MAXIMUM ON TIME, tON/S

1.184 –40

5.0 2.5 3.0 3.5 4.0 4.5 INPUT VOLTAGE AT OUT PIN, VOUT,/V

Figure 4. Reference Voltage vs. Input Voltage at OUT pin

1.194

1.186

2.0

1.6 1.5 1.4 1.3 1.2 –40

–20

0

20

40

60

80

100

Without Schottky Diode

1.6 1.4 1.2

With Schottky Diode (MBR0502)

1.0 0.8 0.6

0

20

40

60

80

100

120


OUTPUT LOADING CURRENT, ILOAD/mA

Figure 7. LX Switch Maximum ON Time vs. Temperature

Figure 8. Minimum Startup Battery Voltage vs. Loading Current


NCP1410 TYPICAL OPERATING CHARACTERISTICS 100

80

L = 22 µH

90 EFFICIENCY (%)

EFFICIENCY (%)

90

100

L = 15 µH

L = 10 µH

70 60

VIN = 1.8 V VOUT = 3.3 V CIN = 10 µF COUT = 33 µF

50 1.0

L = 22 µH 80

70 60

10

100

Figure 9. Efficiency vs. Load Current


L = 27 µH EFFICIENCY (%)

EFFICIENCY (%)

90

L = 15 µH

L = 10 µH


50 1.0

L = 22 µH 80

70 60

10

100

10

100





100 L = 22 µH

1000

L = 27 µH

90 EFFICIENCY (%)

90 EFFICIENCY (%)


50 1.0

1000

100

L = 15 µH

L = 10 µH

70

50 1.0

1000

100

70

60

100


L = 22 µH

80

10


90

60


50 1.0

1000

100

80

L = 27 µH


L = 22 µH 80

70 60

10

100

1000

50 1.0


VIN = 4.5 V VOUT = 5.0 V CIN = 10 µF COUT = 33 µF 10

100





1000

NCP1410 TYPICAL OPERATING CHARACTERISTICS 3 OUTPUT VOLTAGE CHANGE (%)

OUTPUT VOLTAGE CHANGE (%)

3 2 1 3.0 V 0 2.2 V –1

VIN = 1.8 V

L = 22 mH VOUT = 3.3 V CIN = 10 µF COUT = 33 µF

–2 –3 1.0

10

100

3.0 V 0 2.2 V –1

VIN = 1.8 V

L = 15 mH VOUT = 3.3 V CIN = 10 µF COUT = 33 µF

–2

10

100

1000



Figure 15. Output Voltage Change vs. Load Current

Figure 16. Output Voltage Change vs. Load Current 200

VOUT = 3.3 V CIN = 10 µF COUT = 33 µF L = 22 mH

180 160 140

RIPPLE VOLTAGE, VRIPPLE/mVp–p

RIPPLE VOLTAGE, VRIPPLE/mVp–p

1

–3 1.0

1000

200

120 100 200 mA

80 100 mA

60 40 20 0 1.0

NO LOAD OPERATING CURRENT, IBATT/µA

2

1.5

2.0

3.0

2.5

VOUT = 3.3 V CIN = 10 µF COUT = 33 µF L = 15 mH

180 160 140 120 100 80 200 mA

60 40 20

100 mA

0 1.0

1.5

2.0

2.5

BATTERY INPUT VOLTAGE, VBATT/V

BATTERY INPUT VOLTAGE, VBATT/V

Figure 17. Output Ripple Voltage vs. Battery Input Voltage

Figure 18. Output Ripple Voltage vs. Battery Input Voltage

14 12 10 8.0 6.0 4.0 2.0 (VIN = 2.2 V, VOUT = 3.3 V, ILOAD = 100 mA; L = 22 µH, COUT = 33 µF)

0 0

1.0 3.0 5.0 2.0 4.0 INPUT VOLTAGE AT OUT PIN, VOUT/V

6.0

Upper Trace: Output Voltage Waveform, 2.0 V/Division Lower Trace: Shutdown Pin Waveform, 1.0 V/Division

Figure 19. No Load Operating Current vs. Input Voltage at OUT Pin

Figure 20. Startup Transient Response


3.0

NCP1410 TYPICAL OPERATING CHARACTERISTICS

(VIN = 2.2 V, VOUT = 3.3 V, ILOAD = 10 mA; L = 22 µH, COUT = 33 µF)


Upper Trace: Voltage at LX pin, 2.0 V/Division MiddleTrace Otuput Voltage Ripple, 50 mV/Division Lower Trace: Inductor Current, IL, 100 mA/Division

Upper Trace: Voltage at LX pin, 2.0 V/Division MiddleTrace Otuput Voltage Ripple, 50 mV/Division Lower Trace: Inductor Current, IL, 100 mA/Division

Figure 21. Continuous Conduction Mode Switching Waveform

Figure 22. Discontinuous Conduction Mode Switching Waveform

(VIN = 1.8 V, to 3.0 V, L = 22 µH, COUT = 33 µF)

(VOUT = 3.3 V, ILOAD = 10 mA to 100 mA; L = 22 µH, COUT = 33 µF)

Upper Trace: Battery Voltage, VIN, 1.0 V/Division Lower Trace: Output Voltage Ripple, 100 mV/Division

Upper Trace: Output Voltage Ripple, 100 mV/Division Lower Trace: Load Current, ILOAD, 50 mA/Division

Figure 23. Line Transient Response for VOUT = 3.3 V

Figure 24. Load Transient Response for VIN = 1.8 V








NCP1410 DETAILED OPERATION DESCRIPTIONS

When the main regulator is operating in CCM, as M2 is being turned OFF, and M1 is just turned ON with M2 not being completed OFF, the above mentioned situation will occur. So dead time is introduced to make sure M2 is completed OFF before M1 is being turned ON. When the regulator is operating in DCM, as coil current is dropped to zero, M2 is supposed to be OFF. Fail to do so, reverse current will flow from the output bulk capacitor through M2 and then the inductor to the battery input. It causes damage to the battery. So the ZLC comparator comes with fixed offset voltage to switch M2 OFF before any reverse current builds up. However, if M2 is switch OFF too early, large residue coil current flows through the body diode of M2 and increases conduction loss. Therefore, determination on the offset voltage is essential for optimum performance. With the implementation of synchronous rectification, efficiency can be as high as 92%. For single cell input voltage, use an external Schottky diode such as MBR0520 connected from pin 7 to pin 8 to ensure start–up.

NCP1410 is a monolithic micropower high frequency step–up voltage switching converter IC specially designed for battery operated hand–held electronic products up to 250 mA loading. It integrates Synchronous Rectifier for improving efficiency as well as eliminating the external Schottky Diode. High switching frequency (up to 600 kHz) allows low profile inductor and output capacitor being used. Low–Battery Detector, Logic–Controlled Shutdown and Cycle–by–Cycle Current Limit provide value–added features for various battery–operated application. With all these functions ON, the quiescent supply current is only 9.0 µA typical. This device is available in a compact Micro8 package. PFM Regulation Scheme

From the simplified Functional Diagram (Figure 2), the output voltage is divided down and fed back to pin 1 (FB). This voltage goes to the non–inverting input of the PFM comparator whereas the comparator’s inverting input is connected to REF. A switching cycle is initiated by the falling edge of the comparator, at the moment, the main switch (M1) is turned ON. After the maximum ON–time (typical 1.4 µS) elapses or the current limit is reached, M1 is turned OFF, and the synchronous switch (M2) is turned ON. The M1 OFF time is not less than the minimum OFF–time (typical 0.31 µS), this is to ensure energy transfer from the inductor to the output capacitor. If the regulator is operating at continuous conduction mode (CCM), M2 is turned OFF just before M1 is supposed to be ON again. If the regulator is operating at discontinuous conduction mode (DCM), which means the coil current will decrease to zero before the next cycle, M1 is turned OFF as the coil current is almost reaching zero. The comparator (ZLC) with fixed offset is dedicated to sense the voltage drop across M2 as it is conducting, when the voltage drop is below the offset, the ZLC comparator output goes HIGH, and M2 is turned OFF. Negative feedback of closed loop operation regulates voltage at pin 1 (FB) equal to the internal voltage reference (1.190 V).

Cycle–by–Cycle Current Limit

From Figure 2, SENSEFET is applied to sample the coil current as M1 is ON. With that sample current flowing through a sense resistor, sense–voltage is developed. Threshold detector (ILIM) detects whether the sense–voltage is higher than preset level. If it happens, detector output signifies the CONTROL LOGIC to switch OFF M1, and M1 can only be switched ON as next cycle starts after the minimum OFF–time (typical 0.31 µS). With properly sizing of SENSEFET and sense resistor, the peak coil current limit is set at 1.0 A typically. Voltage Reference

The voltage at REF is set typically at +1.190 V. It can output up to 2.5 mA with load regulation ±1.5%, at VOUT equal to 3.3 V. If VOUT is increased, the REF load capability can also be increased. A bypass capacitor of 0.15 µF is required for proper operation when REF is not loaded. If REF is loaded, 1.0 F capacitor at REF is needed. Shutdown

Synchronous Rectification

The IC is shutdown when the voltage at pin 5 (SHDN) is pulled lower than 0.3 V. During shutdown, M1 and M2 are both switched OFF, however, the body diode of M2 allows current flow from battery to the output, the IC internal circuit will consume less than 0.05 µA current typically. If the pin 5 voltage is pull higher than 0.6 V, for example, by a resistor connected to VIN, the IC is enabled, and the internal circuit will only consume 9.0 µA current typically from the OUT pin. Refer to Figure 2, the product of RSHDN and CSHDN must be larger than (500 k • 56 nF, i.e. 28 msec). This is to provide reset pulse for startup as battery is plugged in.

Synchronous Rectifier is used to replace Schottky Diode for eliminating the conduction loss contributed by forward voltage of the latter. Synchronous Rectifier is normally realized by powerFET with gate control circuitry which, however, involved relative complicated timing concerns. As main switch M1 is being turned OFF, if the synchronous switch M2 is just turned ON with M1 not being completed turned OFF, current will be shunt from the output bulk capacitor through M2 and M1 to ground. This power loss lowers overall efficiency. So a certain amount of dead time is introduced to make sure M1 is completely OFF before M2 is being turned ON.


NCP1410 Low–Battery Detection

Capacitors Selection

A comparator with 30 mV hysteresis is applied to perform the low–battery detection function. When pin 2 (LBI) is at a voltage, which can be defined by a resistor divider from the battery voltage, lower than the internal reference voltage, 1.190 V, the comparator output will cause a 50 Ohm low side switch to be turned ON. It will pull down the voltage at pin 3 (LBO) which has a hundreds kilo–Ohm of pull–high resistance. If the pin 2 voltage is higher than 1.190 V + 30 mV, the comparator output will cause the 50 Ohm low side switch to be turned OFF, pin 3 will become high impedance, and its voltage will be pulled high by the external resistor.

In all switching mode boost converter applications, both the input and output terminals sees pulsating voltage/current waveforms. The currents flowing into and out of the capacitors multiplying with the Equivalent Series Resistance (ESR) of the capacitor producing ripple voltage at the terminals. During the syn–rect switch off cycle, the charges stored in the output capacitor is used to sustain the output load current. Load current at this period and the ESR combined and reflected as ripple at the output terminals. For all cases, the lower the capacitor ESR, the lower the ripple voltage at output. As a general guide line, low ESR capacitors should be used. Ceramic capacitors have the lowest ESR, but low ESR tantalum capacitors can also be used as a cost effective substitute.

APPLICATIONS INFORMATION Output Voltage Setting

The output voltage of the converter is determined by the external feedback network comprised of RFB1 and RFB2 and the relationship is given by: VOUT + 1.190 V

ǒ

Optional Startup Schottky Diode for Low Battery Voltage

In general operation, no external Schottky diode is required, however, in case you are intended to operate the device close to 1 V level, a Schottky diode connected between the LX and OUT pins as shown in Figure 27 can help during startup of the converter. The effect of the additional Schottky was shown in Figure 8.

Ǔ

R 1 ) FB1 RFB2

where RF2 and RF1 are the upper and lower feedback resistors respectively. Low Battery Detect Level Setting

The Low Battery Detect Voltage of the converter is determined by the external divider network comprised of RLB1 and RLB2 and the relationship is given by: VLB + 1.190 V

L

MBR0502 VOUT

ǒ1 ) RRLB1Ǔ

OUT

LB2

where RLB1 and RLB2 are the upper and lower divider resistors respectively.

NCP1410

LX COUT

Inductor Selection

The NCP1410 is tested to produce optimum performance with a 22 µH inductor at VIN = 3 V, VOUT = 3.3 V supplying output current up to 250 mA. For other input/output requirements, inductance in the range 10 µH to 47 µH can be used according to end application specifications. Selecting an inductor is a compromise between output current capability and tolerable output voltage ripple. Of course, the first thing we need to obey is to keep the peak inductor current below its saturation limit at maximum current and the ILIM of the device. In NCP1410, ILIM is set at 1 A. As a rule of thumb, low inductance values supply higher output current, but also increase the ripple at output and reducing efficiency, on the other hand, high inductance values can improve output ripple and efficiency, however it also limit the output current capability at the same time. One other parameter of the inductor is its DC resistance, this resistance can introduce unwanted power loss and hence reduce overall efficiency, the basic rule is selecting an inductor with lowest DC resistance within the board space limitation of the end application.

Figure 27. Schottky Device Between LX and OUT Pins PCB Layout Recommendations

Good PCB layout plays an important role in switching mode power conversion. Careful PCB layout can help to minimize ground bounce, EMI noise and unwanted feedback that can affect the performance of the converter. Hints in the following paragraphs, can be used as guidelines in most situations. Grounding

Star–ground connection should be used to connect the output power return ground, the input power return ground and the device power ground together at one point. All high current running paths must be thick enough for current flowing through and producing insignificant voltage drop along the path. Feedback signal path must be separated with the main current path and sensing directly at the anode of the output capacitor.


NCP1410 Components Placement

Feedback Network

Power components, i.e. input capacitor, inductor and output capacitor, must be placed as close together as possible. All connecting traces must be short, direct and thick. High current flowing and switching paths must be kept away from the feedback (FB, pin 1) terminal to avoid unwanted injection of noise into the feedback path.

Feedback of the output voltage must be a separate trace detached from the power path. External feedback network must be placed very close to the feedback (FB, pin 1) pin and sensing the output voltage directly at the anode of the output capacitor.

TYPICAL APPLICATION CIRCUIT

RFB1 355 K

VIN = 1.8 V to 3.0 V

CFB 150 pF

L

22 µH

VBATT

VOUT = 3.3 V/250 mA max. VOUT

+ CIN 10 µF/ 10 V

GND

RLB1 225 K

1 FB 2 LBI

RLB2 330 K

RFB2 200 K

VOUT 8 LX 7

NCP1410

3 LBO

GND 6

4 REF

SHDN 5

RSHDN 560 K

+ COUT 33 µF/ 10 V

CSHDN 56 nF

CREF 150 nF

Figure 28. Typical Application Schematic for 2 Alkaline Cells Supply


GND

NCP1410 GENERAL DESIGN PROCEDURES Switching mode converter design is considered as black magic to most engineers, some complicate empirical formulae are available for reference usage. Those formulae are derived form the assumption that the key components, i.e. power inductor and capacitors are available with no tolerance. Practically, its not true, the result is not a matter of how accurate the equations you are using to calculate the component values, the outcome is still somehow away from the optimum point. In below a simple method base on the most basic first order equations to estimate the inductor and capacitor values for NCP1410 operate in Continuous Conduction Mode is introduced. The component value set can be used as a starting point to fine tune the circuit operation. By all means, detail bench testing is needed to get the best performance out of the circuit.

Determine the Steady State Duty Ratio, D for typical VIN, operation will be optimized around this point: VOUT 1 + 1*D VIN D+1*

VIN + 1 * 2.4 V + 0.273 3.3 V VOUT

Determine the average inductor current, ILAVG at maximum IOUT: I 250 mA ILAVG + OUT + + 344 mA 1 * 0.273 1*D

Determine the peak inductor ripple current, IRIPPLE–P and calculate the inductor value: Assume IRIPPLE–P is 20% of ILAVG, the inductance of the power inductor can be calculated as in below:

Design Parameters:

IRIPPLE–P = 0.20 x 344 mA = 68.8 mA

VIN = 1.8 V to 3.0 V, Typical 2.4 V VOUT = 3.3 V IOUT = 200 mA (250 mA max) VLB = 2.0 V VOUT–RIPPLE = 40 mVP–P at IOUT = 250 mA

L+

Standard value of 22 µH is selected for initial trial. Determine the output voltage ripple, VOUT–RIPPLE and calculate the output capacitor value: VOUT–RIPPLE = 40 mVP–P at IOUT = 250 mA

Calculate the feedback network: Select RFB2 = 200 K RFB1 + RFB2

ǒVVOUT * 1Ǔ REF

RFB1 + 200 K

3.3 V * 1Ǔ + 355 K ǒ1.19 V

COUT u

ǒVVLB

RLB1 + 330 K

2.0 V * 1Ǔ + 225 K ǒ1.19 V

REF

IOUT tON VOUT–RIPPLE * IOUT ESRCOUT

where tON = 1.4 µS and ESRCOUT = 0.1 Ω, COUT u

Calculate the Low Battery Detect divider: VLB = 2.0 V Select RLB2 = 330 K RLB1 + RLB2

VIN tON 2.4 V 0.4 S + + 24.4 H 2(68.8 mA) 2 IRIPPLE * P

250 mA 0.4 S + 23.33 F 40 mV * 250 mA 0.1

From above calculation, you need at least 23.33 F in order to achieve the specified ripple level at conditions stated. Practically, a one level larger capacitor will be used to accommodate factors not take into account in the calculation, therefore a capacitor value of 33 F is selected.

Ǔ

*1


28 &- 85) '-9' .-. 7 "# - & . "-:" NCP1411 is a monolithic micropower high frequency Boost (step–up) voltage switching converter IC specially designed for battery operated hand–held electronic products up to 250 mA loading. It integrates Synchronous Rectifier for improving efficiency as well as eliminating the external Schottky Diode. High switching frequency (up to 600 kHz) allows low profile inductor and output capacitor being used. Low–Battery Detector, Logic–Controlled Shutdown and Cycle–by–Cycle Current Limit provide value–added features for various battery–operated applications. The innovative Ring–Killer circuitry guarantees quiet operation in discontinuous conduction mode. With all these functions ON, the device quiescent supply current is only 9.0 A typical. This device is available in the space saving compact Micro8 package.


Micro8 DM SUFFIX CASE 846A

8 1 A2 A Y W

A2 AYW

= Device Marking = Assembly Location = Year = Wafer Lot

Features

• High Efficiency, up to 92% • Very Low Device Quiescent Supply Current of 9.0 A Typical • Built–in Synchronous Rectifier (P–FET) Eliminates One External • • • • • • • • • • •

Schottky Diode High Switching Frequency (up to 600 kHz) Allows use of Small Size Inductor High Accuracy Reference Output, 1.19 V $ 0.6% @ 25°C, can supply more than 2.5 mA when VOUT ≥ 3.3 V Ring–Killer for Quiet Operation in Discontinuous Conduction Mode 1.0 V Startup at No Load Guaranteed Output Voltage from 1.5 V to 5.5 V Adjustable Output Current up to 250 mA @ VIN = 2.5 V, VOUT = 3.3 V Logic–Controlled Shutdown Open Drain Low–Battery Detector Output 1.0 A Cycle by Cycle Current Limit Low Profile and Minimum External Parts Compact Micro8 Package

PIN CONNECTIONS FB 1

8 OUT

LBI/EN 2

7 LX

LBO 3

6 GND

REF 4

5 BAT (Top View)

ORDERING INFORMATION Device NCP1411DMR2

Package

Shipping

Micro8

4000 Tape & Reel


• • • • •

Personal Digital Assistant (PDA) Handheld Digital Audio Product Camcorder and Digital Still Camera Handheld Instrument Conversion from One or Two NiMH or NiCd, or One Li–ion Cell to 3.3 V/5.0 V



1470


NCP1411 Input 1 V to VOUT

10 F

220 pF

150 pF

350 k

200 k

1 2

Low Battery Sense Input

RLB2

RLB1

3 4

Shutdown Open Drain Input

CEN 120 nF

22 H

NCP1411 FB

OUT

LBI/EN

LX

LBO

GND

REF

BAT

8 7

33 F +

6 5

Output 1.5 to 5.5 V IOUT Typical Up to 250 mA at 3.3 V Output and 2.5 V Input

150 nF

Low Battery Open Drain Output

Figure 1. Typical Operating Circuit

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin #

Symbol

Pin Description

1

FB

2

LBI/EN

3

LBO

Open–Drain Low–Battery Detector Output. Output is LOW when VLBI is < 1.178 V. LBO is high impedance during shutdown.

4

REF

1.190 V Reference Voltage Output, bypassing with 150 nF capacitor if this pin is not loaded, bypassing with 1.0 F if this pin is loaded up to 2.5 mA @ VOUT = 3.3 V.

5

BAT

Battery input connection for internal Ring–Killer.

6

GND

Ground.

7

LX

8

OUT

Output Voltage Feedback Input.

Low–Battery Detector Input and IC Enable.

N–Channel and P–Channel Power MOSFET Drain Connection. Power Output. OUT also provides bootstrapped power to the device.

MAXIMUM RATINGS Rating

Symbol

Value

Unit

VOUT

–0.3 to 6.0

V

VIO

–0.3 to 6.0

V

PD RθJA

520 240

mW °C/W


TJ

–40 to +150

°C


TA

–40 to +85

°C


Tstg

–55 to +150

°C

Device Power Supply (Pin 8) Input/Output Pins Pins 1–5, Pin 7 Thermal Characteristics Micro8 Plastic Package Maximum Power Dissipation @ TA = 25C Thermal Resistance, Junction–to–Air

1. This device contains ESD protection and exceeds the following tests: Human Body Model (HBM) "2.0 kV per JEDEC standard: JESD22–A114. Machine Model (MM) "200 V per JEDEC standard: JESD22–A115. 2. The maximum package power dissipation limit must not be exceeded. PD +

TJ(max) * TA RJA

3. Latch–up Current Maximum Rating: "150 mA per JEDEC standard: JESD78. 4. Moisture Sensitivity Level: MSL 1 per IPC/JEDEC standard: J–STD–020A.


NCP1411 ELECTRICAL CHARACTERISTICS (VOUT = 3.3 V, TA = 25°C for typical value, –40°C ≤ TA ≤ 85°C for min/max values unless otherwise noted.) Characteristic

Symbol

Min

Typ

Max

Unit

VIN

1.0

–

5.5

V

VOUT

VIN

–

5.5

V

VREF_NL

1.183

1.190

1.197

V

VREF_NL_A

1.178

–

1.202

V

TCVREF

–

0.03

–

mV/°C

IREF

2.5

–

–

mA

Reference Voltage Load Regulation (VOUT = 3.3 V, ILOAD = 0 to 100 A, CREF = 1.0 F)

VREF_LOAD

–

0.015

1.0

mV

Reference Voltage Line Regulation (VOUT from 1.5 V to 5.5 V, CREF = 1.0 F)

VREF_LINE

–

0.03

1.0

mV/V

FB, LBI Input Threshold (ILOAD = 0 mA)

VFB, VLBI

1.174

1.190

1.200

V

N–FET ON Resistance

RDS(ON)–N

–

0.6

–

Ω

P–FET ON Resistance

RDS(ON)–P

–

0.9

–

Ω

ILIM

–

1.0

–

A

Operating Current into OUT (VFB = 1.4 V, i.e. no switching, VOUT = 3.3 V)

IQ

–

9.0

14

A

Shutdown Current into OUT (LBI/EN = GND)

ISD

–

0.05

1.0

A

LX Switch MAX. ON–Time (VFB = 1.0 V, VOUT = 3.3 V)

tON

1.2

1.4

1.8

S

LX Switch MIN. OFF–Time (VFB = 1.0 V, VOUT = 3.3 V)

tOFF

0.25

0.31

0.37

S

FB Input Current

IFB

–

1.5

9.0

nA

Shutdown Current into BAT (LBI/EN = 0 V, VOUT = VBAT = 3.0 V)

ILBT

–

50

–

nA

RLBT_LX

–

100

–

Ω

LBI/EN Input Current

ILBI/EN

–

1.5

8.0

nA

LBO Low Output Voltage (VLBI = 0 V, ISINK = 1.0 mA)

VLBO_L

–

–

0.05

V

ENABLE (Pin 2) Input threshold, Low

VEN

–

–

0.3

V

ENABLE (Pin 2) Input threshold, High

VEN

0.6

–

–

V

Operating Input Voltage Output Voltage Range (Adjusted by external feedback) Reference Voltage (CREF = 150 nF, under no loading, TA = 25°C) Reference Voltage (CREF = 150 nF, under no loading, –40°C ≤ TA ≤ 85°C) Reference Voltage Temperature Coefficient Reference Voltage Load Current (VOUT = 3.3 V, VREF = VREF_NL ±1.5%, CREF = 1.0 F) (Note 5)

LX Switch Current Limit (N–FET)

BAT to LX resistance (VFB = 1.4 V, VOUT = 3.3 V)

5. Loading capability increases with VOUT.


NCP1411 VBAT M3

ZLC Chip Enable

. %

+ 20 mV

VDD M2

CONTROL LOGIC VDD

SenseFET

_MAINSW2ON

1

PFM

REF 4

M1

_PWQONCE _CEN _PFM _MAINSWOFD _SYNSW2ON

. %

Voltage Reference

LX 7 OUT 8

_ZCUR _MSON

FB

BAT 5

6

GND

GND

VDD

GND

_SYNSWOFD _VREFOK _ILIM ILIM

. %

RSENSE +

LBO 3

LBI/EN 2

. %

GND

GND

Figure 2. Simplified Functional Diagram


VOUT

NCP1411 TYPICAL OPERATING CHARACTERISTICS 1.195 VOUT = 3.3 V L = 22 H CIN = 10 F COUT = 33 F CREF = 1 F TA = 25°C

1.215 1.210

VREF, REFERENCE VOLTAGE (V)


1.220

VIN = 1.8 V

1.205 VIN = 2.2 V 1.200 1.195 VIN = 3.0 V 1.190

1.192 IREF = 0 mA 1.189

1.186

IREF = 2.5 mA CREF = 1 F TA = 25°C

1.183 1.180

1

10 100 ILOAD, OUTPUT CURRENT (mA)

1000

1

2 3 4 5 VOUT, INPUT VOLTAGE AT OUT PIN (V)

Figure 3. Reference Voltage versus Output Current

Figure 4. Reference Voltage versus Input Voltage at OUT Pin

RDS(on), SWITCH ON RESISTANCE ()


1.194

1.192

1.190

1.188 VOUT = 3.3 V CREF = 150 nF IREF = 0 mA

1.186 1.184 –40

–20

0 20 40 60 80 TA, AMBIENT TEMPERATURE (°C)

100

1.5

1.2 P–FET (M2) 0.9 N–FET (M1)

0.6

0.3 VOUT = 3.3 V 0 –40

LX, SWITCH MAX. ON TIME (ton/S)

1.8 1.7 1.6 1.5 1.4 1.3

–20


–20


100

Figure 6. Switch ON Resistance versus Temperature

100

VBATT, MIN. STARTUP BATTERY VOLTAGE (V)

Figure 5. Reference Voltage versus Temperature

1.2 –40

6

1.9 WITHOUT SCHOTTKY DIODE 1.6

1.4

1.1

WITH SCHOTTKY DIODE (MBR0502)

0.9 0.6 0

Figure 7. LX Switch Max. ON Time versus

20 100 40 60 80 ILOAD, OUTPUT LOADING CURRENT (mA)

120

Figure 8. Min. Startup Battery Voltage versus Loading Current

Temperature


NCP1411 100

90

L = 22 H

80

L = 10 H

L = 15 H

70 VIN = 1.8 V VOUT = 3.3 V CIN = 10 F COUT = 33 F

60

L = 27 H

90 EFFICIENCY (%)

EFFICIENCY (%)

100

L = 22 H 80

70 VIN = 2.2 V VOUT = 5 V CIN = 10 F COUT = 33 F

60

50

50 1

10 100 ILOAD, OUTPUT LOADING CURRENT (mA)

1000

1

Figure 9. Efficiency versus Load Current

100

90

L = 22 H

80

L = 10 H L = 15 H


60

L = 27 H

90 EFFICIENCY (%)

EFFICIENCY (%)

1000


100

L = 22 H 80


60 50

50 1


1000

1



1000


100

100 L = 27 H

L = 22 H 90 EFFICIENCY (%)

90 EFFICIENCY (%)


L = 10 H

80

L = 15 H

70 VIN = 3 V VOUT = 3.3 V CIN = 10 F COUT = 33 F

60

L = 22 H 80

70 VIN = 4.5 V VOUT = 5 V CIN = 10 F COUT = 33 F

60 50

50 1


1000

1



1000



NCP1411 3.0 OUTPUT VOLTAGE CHANGE (%)

OUTPUT VOLTAGE CHANGE (%)

3.0 2.0 1.0 3V 0 2.2 V

–1.0

L = 22 H VOUT = 3.3 V CIN = 10 F COUT = 33 F

–2.0 –3.0 1

VIN = 1.8 V

2.0 1.0 3V

0 –1.0 –2.0 –3.0


1000

1

Figure 15. Output Voltage Change versus Load Current


1000

200 VRIPPLE, RIPPLE VOLTAGE (mVp–p)

VRIPPLE, RIPPLE VOLTAGE (mVp–p)

VIN = 1.8 V

Figure 16. Output Voltage Change versus Load Current

200 VOUT = 3.3 V CIN = 10 F COUT = 33 F L = 22 H

160

120 200 mA

80 100 mA 40 0

160

200 mA

VOUT = 3.3 V CIN = 10 F COUT = 33 F L = 15 H

120 100 mA

80

40 0

1

1.5 2 2.5 VBATT, BATTERY INPUT VOLTAGE (V)

3

1

Figure 17. Battery Input Voltage vesus Output Ripple Voltage IBATT, NO LOAD OPERATING CURRENT (A)

2.2 V

L = 15 H VOUT = 3.3 V CIN = 10 F COUT = 33 F

1.5 2 2.5 VBATT, BATTERY INPUT VOLTAGE (V)

Figure 18. Battery Input Voltage versus Output Ripple Voltage

20

16

12

8

4 0 0

1 4 5 6 2 3 VOUT, INPUT VOLTAGE AT OUT PIN (V)

3


7

Upper Trace: Output Voltage Waveform, 2.0 V/Division Lower Trace: Shutdown Pin Waveform, 1.0 V/Division

Figure 19. No Load Operating Current versus Input Voltage at OUT Pin

Figure 20. Startup Transient Response


NCP1411



Upper Trace: Voltage at LX pin, 2.0 V/Division MiddleTrace: Output Voltage Ripple, 50 mV/Division Lower Trace: Inductor Current, IL, 100 mA/Division

Upper Trace: Voltage at LX pin, 2.0 V/Division MiddleTrace: Output Voltage Ripple, 50 mV/Division Lower Trace: Inductor Current, IL, 100 mA/Division

Figure 21. Continuous Conduction Mode Switching Waveform

Figure 22. Discontinuous Conduction Mode Switching Waveform

(VIN = 1.8 V to 3.0 V, L = 22 µH, COUT = 33 µF)


Upper Trace: Output Voltage Ripple, 100 mV/Division Lower Trace: Battery Voltage, VIN, 1.0 V/Division


Figure 23. Line Transient Response for VOUT = 3.3 V







Figure 25. Load Transient Response for VIN = 2.4 V http://onsemi.com 1477

NCP1411 DETAILED OPERATION DESCRIPTIONS

situation will occur. So dead time is introduced to make sure M2 is completely turned OFF before M1 is being turned ON. When the regulator is operating in DCM, as coil current is dropped to zero, M2 is supposed to be OFF. Fail to do so, reverse current will flow from the output bulk capacitor through M2 and then the inductor to the battery input. It causes damage to the battery. So the ZLC comparator comes with fixed offset voltage to switch M2 OFF before any reverse current builds up. However, if M2 is switch OFF too early, large residue coil current flows through the body diode of M2 and increases conduction loss. Therefore, determination on the offset voltage is essential for optimum performance. With the implementation of synchronous rectification, efficiency can be as high as 92%. For single cell input voltage, use an external schottky diode such as MBR0520 connected from pin 7 to pin 8 to ensure quick start–up.

NCP1411 is a monolithic micropower high frequency step–up voltage switching converter IC specially designed for battery operated hand–held electronic products up to 250 mA loading. It integrates Synchronous Rectifier for improving efficiency as well as eliminating the external Schottky Diode. High switching frequency (up to 600 kHz) allows low profile inductor and output capacitor being used. Low–Battery Detector, Logic–Controlled Shutdown and Cycle–by–Cycle Current Limit provide value–added features for various battery–operated application. With all these functions ON, the quiescent supply current is only 9.0 A typical. This device is available in a compact Micro8 package. PFM Regulation Scheme

From the simplified Functional Diagram (Figure 2), the output voltage is divided down and fed back to pin 1 (FB). This voltage goes to the non–inverting input of the PFM comparator whereas the comparator’s inverting input is connected to REF. A switching cycle is initiated by the falling edge of the comparator, at the moment, the main switch (M1) is turned ON. After the maximum ON–time (typical 1.4 S) elapses or the current limit is reached, M1 is turned OFF, and the synchronous switch (M2) is turned ON. The M1 OFF time is not less than the minimum OFF–time (typical 0.31 S), this is to ensure energy transfer from the inductor to the output capacitor. If the regulator is operating at continuous conduction mode (CCM), M2 is turned OFF just before M1 is supposed to be ON again. If the regulator is operating at discontinuous conduction mode (DCM), which means the coil current will decrease to zero before the next cycle, M1 is turned OFF as the coil current is almost reaching zero. The comparator (ZLC) with fixed offset is dedicated to sense the voltage drop across M2 as it is conducting, when the voltage drop is below the offset, the ZLC comparator output goes HIGH, and M2 is turned OFF. Negative feedback of closed loop operation regulates voltage at pin 1 (FB) equal to the internal voltage reference (1.190 V).

Ring–Killer

When the device entered Discontinuous Conduction Mode operation, a typical ringing at LX pin will start while the inductor current just ceased. This ringing is caused primarily by the capacitance and inductance at LX node and the result can produce unwanted EMI problem to the system. In order to eliminate this ringing, an internal damping switch (M3) is implemented to provide a low impedance path to dissipate the residue energy stored in the inductor once the operation entered the Discontinuous Conduction Mode. This feature can improve the EMI problem. The performance of the Ring–Killer switch is shown in Figure 22. Cycle–by–Cycle Current Limit

From Figure 2, SenseFET is applied to sample the coil current as M1 is ON. With that sample current flowing through a sense resistor, sense–voltage is developed. Threshold detector (ILIM) detects whether the sense–voltage is higher than preset level. If it happens, detector output signifies the CONTROL LOGIC to switch OFF M1, and M1 can only be switched ON as next cycle starts after the minimum OFF–time (typical 0.31 S). With properly sizing of SenseFET and sense resistor, the peak coil current limit is set at 1.0 A typically.

Synchronous Rectification

Synchronous Rectifier is used to replace Schottky Diode for eliminating the conduction loss contributed by forward voltage of the latter. Synchronous Rectifier is normally realized by powerFET with gate control circuitry which, however, involved relative complicated timing concerns. As main switch M1 is being turned OFF, if the synchronous switch M2 is just turned ON with M1 not being completed turned OFF, current will be shunt from the output bulk capacitor through M2 and M1 to ground. This power loss lowers overall efficiency. So a certain amount of dead time is introduced to make sure M1 is completely OFF before M2 is being turned ON. When the main regulator is operating in CCM, as M2 is being turned OFF, and M1 is just turned ON with M2 not being completely turned OFF, the above mentioned

Voltage Reference

The voltage at REF is set typically at +1.190 V. It can deliver up to 2.5 mA with load regulation ±1.5%, at VOUT equal to 3.3 V. If VOUT is increased, the REF load capability can also be increased. A bypass capacitor of 0.15 F is required for proper operation when REF is not loaded. If REF is loaded, 1.0 F capacitor at REF is needed. Shutdown

The IC will shutdown when the voltage at pin 2 (LBI/EN) is pulled lower than 0.3 V. During shutdown, M1 and M2 are both switched OFF, however, the body diode of M2 allows current flow from battery to the output, the IC internal circuit will consume less than 0.05 A current typically. If the pin


NCP1411 however it also limit the output current capability at the same time. One other parameter of the inductor is its DC resistance, this resistance can introduce unwanted power loss and hence reduce overall efficiency, the basic rule is selecting an inductor with lowest DC resistance within the board space limitation of the end application.

1 voltage raised higher than 0.6 V, the IC will be enabled. The internal circuit will only consume 9.0 A current typically from the OUT pin. In order to ensure proper startup, a timing capacitor CEN as shown in Figure 1 is required to provide the reset pulse during batteries are plugged in. The product of RLB1 and CEN must be larger than 28 msec.

Capacitors Selection

In all switching mode boost converter applications, both the input and output terminals sees impulsive voltage/current waveforms. The currents flowing into and out of the capacitors multiplying with the Equivalent Series Resistance (ESR) of the capacitor producing ripple voltage at the terminals. During the syn–rect switch off cycle, the charges stored in the output capacitor is used to sustain the output load current. Load current at this period and the ESR combined and reflected as ripple at the output terminal. For all cases, the lower the capacitor ESR, the lower the ripple voltage at output. As a general guide line, low ESR capacitors should be used. Ceramic capacitors have the lowest ESR, but low ESR tantalum capacitors can also be used as a cost effective substitute.

Low–Battery Detection

A comparator with 30 mV hysteresis is applied to perform the low–battery detection function. When pin 2 (LBI/EN) is at a voltage, which can be defined by a resistor divider from the battery voltage, lower than the internal reference voltage, 1.190 V, the comparator output will cause a 50 Ohm low side switch to be turned ON. It will pull down the voltage at pin 3 (LBO) which has a hundreds kilo–Ohm of pull–high resistance. If the pin 2 voltage is higher than 1.190 V +30 mV, the comparator output will cause the 50 Ohm low side switch to be turned OFF, pin 3 will become high impedance, and its voltage will be pulled high. APPLICATIONS INFORMATION Output Voltage Setting

Optional Startup Schottky Diode for Low Battery Voltage

The output voltage of the converter is determined by the external feedback network comprised of RFB1 and RFB2 and the relationship is given by: VOUT + 1.190 V

In general operation, no external schottky diode is required, however, in case you are intended to operate the device close to 1.0 V level, a schottky diode connected between the LX and OUT pins as shown in Figure 27 can help during startup of the converter. The effect of the additional schottky was shown in Figure 8.

ǒ1 ) RRFB1 Ǔ FB2

where RFB1 and RFB2 are the upper and lower feedback resistors respectively. Low Battery Detect Level Setting

L

MBR0502 VOUT

The Low Battery Detect Voltage of the converter is determined by the external divider network comprised of RLB1 and RLB2 and the relationship is given by: VLB + 1.190 V

ǒ1 ) RRLB1 Ǔ

OUT

LB2

NCP1411

where RLB1 and RLB2 are the upper and lower divider resistors respectively.

COUT LX

Inductor Selection

Figure 27. PCB Layout Recommendations

The NCP1411 is tested to produce optimum performance with a 22 H inductor at VIN = 3.0 V, VOUT = 3.3 V supplying output current up to 250 mA. For other input/output requirements, inductance in the range 10 H to 47 H can be used according to end application specifications. Selecting an inductor is a compromise between output current capability and tolerable output voltage ripple. Of course, the first thing we need to obey is to keep the peak inductor current below its saturation limit at maximum current and the ILIM of the device. In NCP1411, ILIM is set at 1.0 A. As a rule of thumb, low inductance values supply higher output current, but also increase the ripple at output and reducing efficiency, on the other hand, high inductance values can improve output ripple and efficiency,

PCB Layout Recommendations

Good PCB layout plays an important role in switching mode power conversion. Careful PCB layout can help to minimize ground bounce, EMI noise and unwanted feedback that can affect the performance of the converter. Hints suggested in below can be used as a guide line in most situations. Grounding

Star–ground connection should be used to connect the output power return ground, the input power return ground and the device power ground together at one point. All high


NCP1411 thick. High current flowing and switching paths must be kept away from the feedback (FB, pin 1) terminal to avoid unwanted injection of noise into the feedback path.

current running paths must be thick enough for current flowing through and producing insignificant voltage drop along the path. Feedback signal path must be separated with the main current path and sensing directly at the anode of the output capacitor.

Feedback Network

Feedback of the output voltage must be a separate trace detached from the power path. External feedback network must be placed very close to the feedback (FB, pin 1) pin and sensing the output voltage directly at the anode of the output capacitor.

Components Placement

Power components, i.e. input capacitor, inductor and output capacitor, must be placed as close together as possible. All connecting traces must be short, direct and

RFB1 335 k

CFB1 150 pF

L 22 H

VBATT NCP1411

RLB1 225 k CIN 10 F/10 V

1 2

+ CEN 120 nF RLB2 330 k

VOUT

CFB2 220 pF RFB2 200 k

3 4

FB LBI/EN

OUT LX

LBO

GND

REF

BAT

8 7 6 5

+ COUT 33 F/10 V

CREF 150 nF

GND

GND

Figure 28. Typical Application Schematic for 2 Alkaline Cells Supply


NCP1411 GENERAL DESIGN PROCEDURES

RLB1 + RLB2

Switching mode converter design is considered as black magic to most engineers, some complicate empirical formulae are available for reference usage. Those formulae are derived from the assumption that the key components, i.e. power inductor and capacitors are available with no tolerance. Practically, its not true, the result is not a matter of how accurate the equations you are using to calculate the component values, the outcome is still somehow away from the optimum point. In below a simple method base on the most basic first order equations to estimate the inductor and capacitor values for NCP1411 operate in Continuous Conduction Mode is introduced. The component value set can be used as a starting point to fine tune the circuit operation. By all means, detail bench testing is needed to get the best performance out of the circuit.

RLB1 + 330 K

Ǔ

*1

2.0 V * 1Ǔ + 225 K ǒ1.19 V

Determine the Steady State Duty Ratio, D for typical VIN, operation will be optimized around this point: VOUT + 1 VIN 1*D D+1*

VIN + 1 * 2.4 V + 0.273 3.3 V VOUT

Determine the average inductor current, ILAVG at maximum IOUT: I ILAVG + OUT + 250 mA + 344 mA 1 * 0.273 1*D

Determine the peak inductor ripple current, IRIPPLE–P and calculate the inductor value: Assume IRIPPLE–P is 20% of ILAVG, the inductance of the power inductor can be calculated as in below: IRIPPLE–P = 0.20 x 344 mA = 68.8 mA

Calculate the feedback network: Select RFB2 = 200 K

RFB1 + 200 K

REF

CEN + 28 msec + 120 nF 225 K

Design Parameters: VIN = 1.8 V to 3.0 V, Typical 2.4 V VOUT = 3.3 V IOUT = 200 mA (250 mA max) VLB = 2.0 V VOUT–RIPPLE = 40 mVP–P at IOUT = 250 mA

RFB1 + RFB2

ǒVVLB

ǒVVOUT * 1Ǔ REF

L+

VIN tON 2.4 V 1.4 S + + 24.4 H 2(68.8 mA) 2IRIPPLE–P

Standard value of 22 H is selected for initial trial.

3.3 V * 1Ǔ + 355 K ǒ1.19 V

Determine the output voltage ripple, VOUT–RIPPLE and calculate the output capacitor value: VOUT–RIPPLE = 40 mVP–P at IOUT = 250 mA

With the feedback resistor divider, additional small capacitor, CFB1 in parallel with RFB1 is required to ensure stability. The value can be in between 68 pF to 220 pF, the rule is to select the lowest capacitance to ensure stability. Also a small capacitor, CFB2 in parallel with RFB2 may also be needed to lower the feedback ripple hence improve output regulation. The use of CFB2 is a compromise between output ripple level and regulation, so careful selection of the value according to end application requirement is needed. In this example, values for CFB1 and CFB2 are 150 pF and 220 pF respectively.

COUT w

IOUT tON VOUT * RIPPLE * IOUT

ESRCOUT

where tON = 1.4 S and ESRCOUT = 0.1 Ω, COUT w

250 mA 1.4 S + 23.33 F 40 mV * 250 mA 0.1

From above calculation, we need at least 23.33 F in order to achieve the specified ripple level at conditions stated. Practically, a one level larger capacitor will be used to accommodate factors not take into account in the calculation. So a capacitor value of 33 F is selected.

Calculate the Low Battery Detect divider: VLB = 2.0 V Select RLB2 = 330 K


28 81) '-' .-. The NCP1450A series are PWM step–up DC–DC switching controller that are specially designed for powering portable equipment from one or two cells battery packs. The NCP1450A series have a driver pin, EXT pin, for connecting to an external transistor. Large output currents can be obtained by connecting a low ON–resistance external power transistor to the EXT pin. With only five external components, this series allows a simple means to implement highly efficient converter for large output current applications. Each device consists of an on–chip PWM (Pulse Width Modulation) oscillator, PWM controller, phase–compensated error amplifier, soft–start, voltage reference, and driver for driving external power transistor. Additionally, a chip enable feature is provided to power down the converter for extended battery life. The NCP1450A device series are available in the TSOP–5 package with five standard regulated output voltages. Additional voltages that range from 1.8 V to 5.0 V in 100 mV steps can be manufactured. Features

http://onsemi.com

5 1 TSOP–5 SN SUFFIX CASE 483


• High Efficiency 86% at IO = 200 mA, VIN = 2.0 V, VOUT = 3.0 V

• • • • •

Personal Digital Assistant (PDA) Electronic Games Portable Audio (MP3) Digital Still Cameras Handheld Instruments



1

OUT

2

NC

3

5

EXT

4

GND

xxx = Marking Y = Year W = Work Week (Top View)

ORDERING INFORMATION See detailed ordering and shipping information in the ordering information section on page 1484 of this data sheet.


• • • • •

CE

xxxYW

• • •

88% at IO = 400 mA, VIN = 3.0 V, VOUT = 5.0 V Low Start–up Voltage of 0.9 V typical at IO = 1.0 mA Operation Down to 0.6 V Five Standard Voltages: 1.9 V, 2.7 V, 3.0 V, 3.3 V, 5.0 V with High Accuracy ± 2.5% Low Conversion Ripple High Output Current up to 1000 mA (3.0 V version at VIN = 2.0 V, L = 10 H, COUT = 220 F) Fixed Frequency Pulse Width Modulation (PWM) at 180 kHz Chip Enable Pin with On–chip Pull–up Resistor Low Profile and Micro Miniature TSOP–5 Package

1482

Publication Order Number: NCP1450A/D

NCP1450A

VIN

VOUT

OUT 2 NC 3

EXT 5

NCP1450A

CE 1

GND 4

Figure 1. Typical Step–up Converter Application

OUT 2

+ –

NC 3

Error Amplifier

PWM Controller

Phase Compensation Voltage Reference

Driver

EXT 5

180 kHz Oscillator

Soft–Start

GND 4

1 CE

Figure 2. Representative Block Diagram PIN FUNCTION DESCRIPTION

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Pin #

Symbol

Pin Description

1

CE

2

OUT

3

NC

4

GND

Ground pin.

5

EXT

External transistor drive pin.

Chip Enable Pin (1) The chip is enabled if a voltage equal to or greater than 0.9 V is applied. (2) The chip is disabled if a voltage less than 0.3 V is applied. (3) The chip is enabled if this pin is left floating. Output voltage monitor pin and also the power supply pin for the device. No internal connection to this pin.


NCP1450A ORDERING INFORMATION (Note 1) Device

Output Voltage

Switching Frequency

Marking

NCP1450ASN19T1

1.9 V

DAY

NCP1450ASN27T1

2.7 V

DAZ

NCP1450ASN30T1

3.0 V

NCP1450ASN33T1

3.3 V

DBC

NCP1450ASN50T1

5.0 V

DBD

DBA

180 KHz

Package

Shipping

TSOP–5

3000 Units U it on 7 Inch Reel

1. The ordering information lists five standard output voltage device options. Additional devices with output voltage ranging from 1.8 V to 5.0 V in 100 mV increments can be manufactured. Contact your ON Semiconductor representative for availability.

MAXIMUM RATINGS

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Rating

Symbol

Value

Unit


VOUT

6.0

V

Input/Output Pins EXT (Pin 5) EXT Sink/Source Current

VEXT IEXT

–0.3 to 6.0 –150 to 150

V mA

CE (Pin 1) Input Voltage Range Input Current Range

VCE ICE

–0.3 to 6.0 –150 to 150

V mA

Power Dissipation and Thermal Characteristics Maximum Power Dissipation @ TA = 25°C Thermal Resistance Junction to Air

PD RθJA

500 250

mW °C/W


TA

–40 to +85

°C


TJ

–40 to +150

°C


Tstg

–55 to +150

°C

2. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) $2.0 kV per JEDEC standard: JESD22–A114. Machine Model (MM) $200 V per JEDEC standard: JESD22–A115. 3. Latch–up Current Maximum Rating: $150 mA per JEDEC standard: JESD78. 4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J–STD–020A.


NCP1450A ELECTRICAL CHARACTERISTICS (For all values TA = 25°C, unless otherwise noted.) Characteristic

Symbol

Min

Typ

Max

fOSC f

Unit

144

180

216

kHz

–

0.11

–

%/°C

DMAX

70

80

90

%

OSCILLATOR Frequency (VOUT = VSET

0.96, Note 5)

Frequency Temperature Coefficient (TA = –40°C to 85°C) Maximum PWM Duty Cycle (VOUT = VSET

0.96)

Minimum Start–up Voltage (IO = 0 mA) Minimum Start–up Voltage Temperature Coefficient (TA = –40°C to 85°C) Minimum Operation Hold Voltage (IO = 0 mA) Soft–Start Time (VOUT u 0.8 V)

Vstart

–

0.8

0.9

V

Vstart

–

–1.6

–

mV/°C

Vhold

–

0.6

0.7

V

tSS

0.5

2.0

–

ms

VCE(high) VCE(low)

0.9 –

– –

– 0.3

ICE(high) ICE(low)

–0.5 0

0 0.15

0.5 0.5

CE (PIN 1) CE Input Voltage (VOUT = VSET High State, Device Enabled Low State, Device Disabled

0.96)

V

µA

CE Input Current (Note 6) High State, Device Enabled (VOUT = VCE = 5.0 V) Low State, Device Disabled (VOUT = 5.0 V, VCE = 0 V) EXT (PIN 5) EXT “H” Output Current (VEXT = VOUT –0.4 V) Device Suffix: 19T1 27T1 30T1 33T1 50T1

IEXTH

EXT “L” Output Current(VEXT = 0.4 V) Device Suffix: 19T1 27T1 30T1 33T1 50T1

IEXTL

mA – – – – –

–25.0 –35.0 –37.7 –40.0 –53.7

–20.0 –30.0 –30.0 –30.0 –35.0 mA

20.0 30.0 30.0 30.0 35.0

38.3 48.0 50.8 52.0 58.2

– – – – –

TOTAL DEVICE VOUT

Output Voltage Device Suffix: 19T1 27T1 30T1 33T1 50T1

VOUT

Output Voltage Temperature Coefficient (TA = –40 to +85°C) Operating Current (VOUT = VCE = VSET Device Suffix: 19T1 27T1 30T1 33T1 50T1

0.96, Note 5)

V 1.853 2.633 2.925 3.218 4.875

1.9 2.7 3.0 3.3 5.0

1.948 2.768 3.075 3.383 5.125

–

150

–

ppm/°C µA

IDD – – – – –

55 93 98 103 136

90 140 150 160 220

Stand–by Current (VOUT = VCE = VSET +0.5 V)

ISTB

–

15

20

µA

Off–State Current (VOUT = 5.0 V, VCE = 0 V, TA = –40 to +85°C, Note 6)

IOFF

–

0.6

1.5

µA

5. VSET means setting of output voltage. 6. CE pin is integrated with an internal 10 MΩ pull–up resistor.


NCP1450A 3.2 VOUT, OUTPUT VOLTAGE (V)


2.1

2.0

1.9 VIN = 0.9 V

VIN = 1.2 V

VIN = 1.5 V

1.8 NCP1450ASN19T1 L = 10 µH Q = MGSF3442VT1 COUT = 220 µF TA = 25°C

1.7

0

200

400

800

600

3.0 VIN = 0.9 V

VIN = 1.2 V

2.9

VIN = 2.0 V

VIN = 1.5 V

NCP1450ASN30T1 L = 10 µH Q = MGSF3442VT1 COUT = 220 µF TA = 25°C

2.8

1000

0

200

400

600

800

1000



Figure 3. NCP1450ASN19T1 Output Voltage vs. Output Current


100

5.2

VIN = 1.5 V

VIN = 4.5 V

5.1 VIN = 1.2 V

VIN = 2.0 V

80

VIN = 4.0 V

EFFICIENCY (%)


VIN = 2.5 V

2.7

1.6

5.0 VIN = 2.5 V

VIN = 1.5 V

VIN = 3.0 V

4.9 NCP1450ASN50T1 L = 10 µH Q = MGSF3442VT1 COUT = 220 µF TA = 25°C

VIN = 0.9 V 4.8

0

200

400

600

800

VIN = 0.9 V 40 NCP1450ASN19T1 L = 10 µH Q = MGSF3442VT1 COUT = 220 µF TA = 25°C 0.1

1

10

100




Figure 6. NCP1450ASN19T1 Efficiency vs. Output Current

100 VIN = 2.5 V

VIN = 2.0 V

EFFICIENCY (%)

VIN = 1.5 V

60

40

20

VIN = 1.2 V VIN = 0.9 V

0 0.01

60

0 0.01

1000

100

80

VIN = 1.2 V

20

4.7

EFFICIENCY (%)

3.1

0.1

1

NCP1450ASN30T1 L = 10 µH Q = MGSF3442VT1 COUT = 220 µF TA = 25°C 10

100

VIN = 4.0 V VIN = 3.0 V 80 VIN = 2.5 V VIN = 2.0 V

VIN = 4.5 V

VIN = 1.2 V 60 VIN = 0.9 V

VIN = 1.5 V

40 NCP1450ASN50T1 L = 10 µH Q = MGSF3442VT1 COUT = 220 µF TA = 25°C

20

1000

0 0.01

0.1

1

10

100






1000

1000



2.1

2.0

1.9

1.8

1.7

1.6 –50

NCP1450ASN19T1 L = 22 µH IO = 0 mA VIN = 1.2 V –25

0

25

50

75

0

25

50

75

100

100 IDD, OPERATING CURRENT (µA)


–25

Figure 10. NCP1450ASN30T1 Output Voltage vs. Temperature

NCP1450ASN50T1 L = 22 µH IO = 0 mA VIN = 1.2 V –25

0

25

50

75

80

60

40

20

0 –50

100

NCP1450ASN19T1 VOUT = 1.9 V x 0.96 Open–Loop Test –25

0

25

50

75

TEMPERATURE (°C)

TEMPERATURE (°C)


Figure 12. NCP1450ASN19T1 Operating Current vs. Temperature

100



NCP1450ASN30T1 L = 22 µH IO = 0 mA VIN = 1.2 V


4.9

120

100

80

40 –50

2.8

TEMPERATURE (°C)

5.0

60

2.9

TEMPERATURE (°C)

5.1

4.7 –50

3.0

2.7 –50

100

5.2

4.8

3.1


0

25

50

75

100

180

160

140

120

100 –50


0

25

50

75

TEMPERATURE (°C)

TEMPERATURE (°C)




100

NCP1450A 25 ISTD, STANDBY CURRENT (µA)

ISTD, STANDBY CURRENT (µA)

25

20

15

10 NCP1450ASN19T1 VOUT = 1.9 V + 0.5 V Open–Loop Test

5

0 –50

–25

0

25

50

75


5

–25

0

25

50

75

100

TEMPERATURE (°C)

TEMPERATURE (°C)

Figure 15. NCP1450ASN19T1 Standby Current vs. Temperature


1.0 IOFF, OFF–STATE CURRENT (µA)

ISTD, STANDBY CURRENT (µA)

15

0 –50

100

25

20

15


5

0 –50

–25

0

25

50

75

NCP1450ASN19T1 VOUT = 5.0 V VCE = 0 V Open–Loop Test

0.8

0.6

0.4

0.2

0.0 –50

100

–25

0

25

50

75

100

TEMPERATURE (°C)

TEMPERATURE (°C)


Figure 18. NCP1450ASN19T1 Off–State Current vs. Temperature

1.0

1.2 NCP1450ASN30T1 VOUT = 5.0 V VCE = 0 V Open–Loop Test

0.8

IOFF, OFF–STATE CURRENT (µA)

IOFF, OFF–STATE CURRENT (µA)

20

0.6

0.4

0.2

0.0 –50

–25

0

25

50

75

100

NCP1450ASN50T1 VOUT = 5.0 V VCE = 0 V Open–Loop Test

1.0

0.8

0.6

0.4

0.2 –50

–25

0

25

50

75

100

TEMPERATURE (°C)

TEMPERATURE (°C)





300 250 200 150 100 NCP1450ASN19T1 VOUT = 1.9 V x 0.96 Open–Loop Test

50 0 –50

–25

0

25

50

75

100

250 200 150 100 NCP1450ASN30T1 VOUT = 3.0 V x 0.96 Open–Loop Test

50 0 –50

–25

0

25

50

75

TEMPERATURE (°C)

Figure 21. NCP1450ASN19T1 Oscillator Frequency vs. Temperature


300

100

100


50 0 –50

–25

0

25

50

75


50 40 –50

100

–25

0

25

50

75

TEMPERATURE (°C)

TEMPERATURE (°C)


Figure 24. NCP1450ASN19T1 Maximum Duty Cycle vs. Temperature

100

100 DMAX, MAXIMUM DUTY CYCLE (%)

100 DMAX, MAXIMUM DUTY CYCLE (%)

300

TEMPERATURE (°C)

DMAX, MAXIMUM DUTY CYCLE (%)



NCP1450A


50 40 –50

–25

0

25

50

75

100


50 40 –50

–25

0

25

50

75

TEMPERATURE (°C)

TEMPERATURE (°C)




100

IEXTH, EXT “H” OUTPUT CURRENT (mA)

0

–10

–20

–30 NCP1450ASN19T1 VOUT = 1.9 V x 0.96 VEXT = VOUT – 0.4 V Open–Loop Test

–40

–50 –50

–25

0

25

50

75

100

–20

–30

–40


–60

–70 –50

–25

0

25

50

75

TEMPERATURE (°C)

TEMPERATURE (°C)

Figure 27. NCP1450ASN19T1 EXT “H” Output Current vs. Temperature


IEXTL, EXT “L” OUTPUT CURRENT (mA)

–40

–50

–60


–80

–90 –50

–25

0

25

50

75

100

40

30

20 NCP1450ASN19T1 VOUT = 1.9 V x 0.96 VEXT = 0.4 V Open–Loop Test

10

0 –50

–25

0

25

50

75

TEMPERATURE (°C)


Figure 30. NCP1450ASN19T1 EXT “L” Output Current vs. Temperature

80

70

60


40

30 –50

–25

0

25

50

75

100

100

90

80

70


50 40 –50

–25

0

25

50

75

TEMPERATURE (°C)

TEMPERATURE (°C)




100

50

TEMPERATURE (°C)





NCP1450A

100

20

15

10

5

0 –50

NCP1450ASN19T1 VOUT = 1.9 V x 0.96 VEXT = VOUT – 0.4 V Open–Loop Test –25

0

25

50

75

100

10

5

0 –50

NCP1450ASN30T1 VOUT = 3.0 V x 0.96 VEXT = VOUT – 0.4 V Open–Loop Test –25

0

25

50

75

Figure 34. NCP1450ASN30T1 EXT “H” ON–Resistance vs. Temperature

NCP1450ASN50T1 VOUT = 5.0 V x 0.96 VEXT = VOUT – 0.4 V Open–Loop Test

10

5

–25

0

25

50

75

20

NCP1450ASN19T1 VOUT = 1.9 V x 0.96 VEXT = 0.4 V Open–Loop Test

15

10

5

–25

0

25

50

75

TEMPERATURE (°C)

TEMPERATURE (°C)


Figure 36. NCP1450ASN19T1 EXT “L” ON–Resistance vs. Temperature


15

10

5

–25

0

25

50

75

100

100

25

20


15

10

5

0 –50

–25

0

25

50

75

TEMPERATURE (°C)

TEMPERATURE (°C)




100

25

0 –50

100

25

0 –50

15


15

20

20

TEMPERATURE (°C)

REXTL, EXT “L” ON–RESISTANCE (Ω)

20

25

TEMPERATURE (°C)

25

0 –50


REXTH, EXT “H” ON–RESISTANCE (Ω)

25




NCP1450A

100

0.8 Vstart 0.6

0.4

NCP1450ASN19T1 L = 22 µH COUT = 0.1 µF IO = 0 mA

Vhold

0.2

0.0 –50

–25

0

25

50

75

100


1.0

NCP1450ASN30T1 L = 22 µH COUT = 0.1 µF IO = 0 mA

0.6

0.4

Vhold 0.2

0.0 –50

–25

0

25

50

75

Figure 40. NCP1450ASN30T1 Startup/Hold Voltage vs. Temperature

100

200

Vstart

0.6

0.4

Vhold NCP1450ASN50T1 L = 22 µH COUT = 0.1 µF IO = 0 mA –25

0


180 160 140 120 100

VIN = 1.5 V VIN = 1.2 V

VIN = 0.9 V

80 60 40 20 0

25

50

75

100

0

200

400

600

800

1000

TEMPERATURE (°C)



Figure 42. NCP1450ASN19T1 Ripple Voltage vs. Output Current

200

200 NCP1450ASN30T1 L = 10 µH Q = MGSF3442VT1 COUT = 220 µF TA = 25°C

180 160 140

VIN = 1.2 V

VRIPPLE, RIPPLE VOLTAGE (mV)


Vstart


0.8

0.0 –50

0.8

TEMPERATURE (°C)

1.0

0.2

1.0

TEMPERATURE (°C)




NCP1450A

VIN = 1.5 V

120 100

VIN = 0.9 V

80 VIN = 2.5 V

60 40

VIN = 2.0 V

20 0

180

VIN = 2.0 V

160 VIN = 2.5 V

VIN = 0.9 V

140 120

VIN = 1.2 V

100


VIN = 3.0 V

VIN = 1.5 V

80 60

VIN = 4.5 V

40 VIN = 4.0 V

20 0

0

200

400

600

800

1000

0

200

400

600

800

1000






Vstart

1.6

1.2

0.8 Vhold


0.4

0.0 20

40

60

80

100

1.6

Vstart

1.2

0.8 Vhold

0.4

0.0 0

20

40

60

80

Figure 45. NCP1450ASN19T1 Startup/Hold Voltage vs. Output Current (Using MOSFET)

Figure 46. NCP1450ASN19T1 Startup/Hold Voltage vs. Output Current (Using BJT)

Vstart

1.6


1.2

0.8 Vhold 0.4

0.0 20

40

60

80

100

Vstart

1.6

1.2 Vhold 0.8 NCP1450ASN30T1 L = 10 µH Q = MMJT9410 COUT = 220 µF TA = 25°C

0.4

0.0 0

20

40

60

80




1.6

Vstart

1.2

Vhold

0.8


0.4

0.0 20

40

60

80

100

100

2.0 Vstart

1.6

1.2 Vhold 0.8

NCP1450ASN50T1 L = 10 µH Q = MMJT9410 COUT = 220 µF TA = 25°C

0.4

0.0 0

20

40

60

80






100

2.0


2.0

0

NCP1450ASN19T1 L = 10 µH Q = MMJT9410 COUT = 220 µF TA = 25°C


2.0

0

2.0



0


2.0





NCP1450A

100

NCP1450A

2 µs/div VOUT = 1.9 V, VIN = 1.2 V, IO = 500 mA, L = 10 µH, COUT = 220 µF 1. VL, 1.0 V/div 2. IL, 500 mA/div 3. VOUT, 50 mV/div, AC coupled


Figure 51. NCP1450ASN19T1 Operating Waveforms (Medium Load)

Figure 52. NCP1450ASN19T1 Operating Waveforms (Heavy Load)










NCP1450A

VIN = 1.5 V, L = 4.7 µH, COUT = 220 µF 1. VOUT, 1.9 V (AC coupled), 200 mV/div 2. IO, 1.0 mA to 100 mA

VIN = 1.5 V, L = 4.7 µH, COUT = 220 µF 1. VOUT, 1.9 V (AC coupled), 200 mV/div 2. IO, 100 mA to 1.0 mA

Figure 57. NCP1450ASN19T1 Load Transient Response













2.1

VIN = 1.5 V

2.0

1.9

1.8

VIN = 0.9 V

NCP1450ASN19T1 L = 10 µH Q = MMJT9410 Rb = 560 Ω Cb = 0.003 µF COUT = 220 µF TA = 25°C

VIN = 1.2 V

1.7

1.6 0

200

400

600

800

VIN = 2.5 V


VIN = 1.5 V 2.9

VIN = 1.2 V VIN = 0.9 V

2.8

0

200

400

600

800

1000



Figure 63. NCP1450ASN19T1 Output Voltage vs. Output Current (Ext. BJT)


100 VIN = 4.5 V VIN = 4.0 V

5.1 VIN = 1.5 V

VIN = 2.5 V

VIN = 3.0 V

5.0

4.9


VIN = 2.0 V VIN = 1.2 V

4.8

VIN = 0.9 V

200

400

600

800


40

0 0.01

1000

0.1

1

10

100




Figure 66. NCP1450ASN19T1 Efficiency vs. Output Current (Ext. BJT)

1000

100 VIN = 2.5 V VIN = 2.0 V VIN = 1.5 V VIN = 1.2 V VIN = 0.9 V


40

20

0 0.01

EFFICIENCY (%)

60

60

VIN = 0.9 V

100

80

VIN = 1.2 V

20

4.7 0

VIN = 1.5 V

80 EFFICIENCY (%)


VIN = 2.0 V

3.0

2.7

1000

5.2

EFFICIENCY (%)

3.1

0.1

1

10

100

VIN = 4.0 V VIN = 3.0 V 80 VIN = 2.5 V VIN = 2.0 V VIN = 0.9 V 60

VIN = 4.5 V

40


VIN = 1.5 V VIN = 1.2 V

20

1000

0 0.01

0.1

1

10

100






1000

100

10 IIN, NO LOAD INPUT CURRENT (mA)

IIN, NO LOAD INPUT CURRENT (mA)

NCP1450A NCP1450ASNXXT1 L = 10 µH Q = MGSF3442VT1 COUT = 220 µF TA = 25°C

1

VOUT = 5.0 V 0.1

VOUT = 3.0 V VOUT = 1.9 V 0.01 1

2

3

5

4

A. VOUT = 1.9 V, Rb = 1 kΩ B. VOUT = 3.0 V, Rb = 1 kΩ C. VOUT = 5.0 V, Rb = 1 kΩ D. VOUT = 1.9 V, Rb = 560 Ω E. VOUT = 3.0 V, Rb = 560 Ω F. VOUT = 5.0 V, Rb = 560 Ω

F C 10

E B

NCP1450ASNXXT1 L = 10 µH Q = MMJT9410 COUT = 220 µF TA = 25°C

1 D 0.1

A

0.01 0

1

2

3

4



Figure 69. NCP1450ASNXXT1 No Load Input Current vs. Input Voltage (Using MOSFET)

Figure 70. NCP1450ASNXXT1 No Load Input Current vs. Input Voltage (Using BJT)


5

NCP1450A DETAILED OPERATING DESCRIPTION Operation

Soft Start

The NCP1450A series are monolithic power switching controllers optimized for battery powered portable products where large output current is required. The NCP1450A series are low noise fixed frequency voltage–mode PWM DC–DC controllers, and consist of start–up circuit, feedback resistor divider, reference voltage, oscillator, loop compensation network, PWM control circuit, and low ON resistance driver. Due to the on–chip feedback resistor and loop compensation network, the system designer can get the regulated output voltage from 1.8 V to 5.0 V with 0.1 V stepwise with a small number of external components. The quiescent current is typically 93 µA (VOUT = 2.7 V, fOSC = 180 kHz), and can be further reduced to about 1.5 µA when the chip is disabled (VCE t 0.3 V). The NCP1450A operation can be best understood by referring to the block diagram in Figure 2. The error amplifier monitors the output voltage via the feedback resistor divider by comparing the feedback voltage with the reference voltage. When the feedback voltage is lower than the reference voltage, the error amplifier output will decrease. The error amplifier output is then compared with the oscillator ramp voltage at the PWM controller. When the ramp voltage is higher than the error amplifier output, the high–side driver is turned on and the low–side driver is turned off which will then switch on the external transistor; and vice versa. As the error amplifier output decreases, the high–side driver turn–on time increases and duty cycle increases. When the feedback voltage is higher than the reference voltage, the error amplifier output increases and the duty cycle decreases. When the external power switch is on, the current ramps up in the inductor, storing energy in the magnetic field. When the external power switch is off, the energy stored in the magnetic field is transferred to the output filter capacitor and the load. The output filter capacitor stores the charge while the inductor current is higher than the output current, then sustains the output voltage until the next switching cycle. As the load current is decreased, the switch transistor turns on for a shorter duty cycle. Under the light load condition, the controller will skip cycles to maintain the output voltage regulation.

There is a soft start circuit in NCP1450A. When power is applied to the device, the soft start circuit pumps up the output voltage to approximately 1.5 V at a fixed duty cycle, the level at which the controller can operate normally. In addition to that, the start–up capability with heavy loads is also improved. Oscillator

The oscillator frequency is internally set to 180 kHz at an accuracy of "20% and with low temperature coefficient of 0.11%/°C. Regulated Converter Voltage (VOUT)

The VOUT is set by an integrated feedback resistor network. This is trimmed to a selected voltage from 1.8 V to 5.0 V range in 100 mV steps with an accuracy of "2.5%. Compensation

The device is designed to operate in continuous conduction mode. An internal compensation circuit was designed to guarantee stability over the full input/output voltage and full output load range. Enable/Disable Operation

The NCP1400A series offer IC shut–down mode by chip enable pin (CE pin) to reduce current consumption. An internal pull–up resistor tied the CE pin to OUT pin by default, i.e., user can float the pin CE for permanent “ON’’. When voltage at pin CE is equal or greater than 0.9 V, the chip will be enabled, which means the controller is in normal operation. When voltage at pin CE is less than 0.3 V, the chip is disabled, which means IC is shutdown. Important: DO NOT apply a voltage between 0.3 V to 0.9 V to pin CE as this is the CE pin’s hysteresis voltage range. Clearly defined output states can only be obtained by applying voltage out of this range.


NCP1450A APPLICATION CIRCUIT INFORMATION Step–up Converter Design Equations

Higher inductor values reduce ripple and improve efficiency, but also limit output current. The inductor should have small DCR, usually less than 1 , to minimize loss. It is necessary to choose an inductor with a saturation current greater than the peak current which the inductor will encounter in the application.

The NCP1450A PWM step–up DC–DC controller is designed to operate in continuous conduction mode and can be defined by the following equations. External components values can be calculated from these equations, however, the optimized value should obtained through experimental results.

Diode

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Calculation

Equation

D

V ) VD * VIN v OUT VOUT ) VD * VS

IL

IO 1*D

L

(VIN * VS)D 2f ( IL * I min)

IPK

IL )

Q

VPP

(VIN * VS)D 2Lf

( IL * IO)(1 * D) f

[

Q ) ( IL * IO)ESR COUT

NOTES: D – On–time duty cycle IL – Average inductor current IPK – Peak inductor current Imin – Minimum inductor current IO – Desired dc output current VIN – Nominal operating dc input voltage VOUT – Desired dc output voltage VD – Diode forward voltage VS – Saturation voltage of the external transistor switch – Charge stores in the COUT during charging up Q ESR – Equivalent series resistance of the output capacitor

The diode is the largest source of loss in DC–DC converters. The most importance parameters which affect their efficiency are the forward voltage drop, VD , and the reverse recovery time, trr. The forward voltage drop creates a loss just by having a voltage across the device while a current flowing through it. The reverse recovery time generates a loss when the diode is reverse biased, and the current appears to actually flow backwards through the diode due to the minority carriers being swept from the P–N junction. A Schottky diode with the following characteristics is recommended: Small forward voltage, VF t 0.3 V Small reverse leakage current Fast reverse recovery time/switching speed Rated current larger than peak inductor current, Irated u IPK Reverse voltage larger than output voltage, Vreverse u VOUT Input Capacitor

The input capacitor can stabilize the input voltage and minimize peak current ripple from the source. The value of the capacitor depends on the impedance of the input source used. Small ESR (Equivalent Series Resistance) Tantalum or ceramic capacitor with a value of 10 µF should be suitable.

External Component Selection Inductor Selection

Output Capacitor

The NCP1450A is designed to work well with a 6.8 to 12 H inductors in most applications 10 H is a sufficiently low value to allow the use of a small surface mount coil, but large enough to maintain low ripple. Lower inductance values supply higher output current, but also increase the ripple and reduce efficiency.

The output capacitor is used for sustaining the output voltage when the external MOSFET or bipolar transistor is switched on and smoothing the ripple voltage. Low ESR capacitor should be used to reduce output ripple voltage. In general, a 100 µF to 220 µF low ESR (0.10 Ω to 0.30 Ω) Tantalum capacitor should be appropriate.


NCP1450A External Switch Transistor

Rb can be calculated by the following equation:

An enhancement N–channel MOSFET or a bipolar NPN transistor can be used as the external switch transistor. For enhancement N–channel MOSFET, since enhancement MOSFET is a voltage driven device, it is a more efficient switch than a BJT transistor. However, the MOSFET requires a higher voltage to turn on as compared with BJT transistors. An enhancement N–channel MOSFET can be selected by the following guidelines: 1. Low ON–resistance, RDS(on), typically < 0.1 . 2. Low gate threshold voltage, VGS(th), must be < VOUT, typically < 1.5 V, it is especially important for the low VOUT device, like VOUT = 1.9 V. 3. Rated continuous drain current, ID, should be larger than the peak inductor current, i.e. ID > IPK. 4. Gate capacitance should be 1200 pF or less. For bipolar NPN transistor, medium power transistor with continuous collector current typically 1 A to 5 A and VCE(sat) < 0.2 V should be employed. The driving capability is determined by the DC current gain, HFE, of the transistor and the base resistor, Rb; and the controller’s EXT pin must be able to supply the necessary driving current.

V 0.7 0.4 Rb + OUT * * | IEXTH| Ib I Ib + PK HFE

Since the pulse current flows through the transistor, the exact Rb value should be finely tuned by the experiment. Generally, a small Rb value can increase the output current capability, but the efficiency will decrease due to more energy is used to drive the transistor. Moreover, a speed–up capacitor, Cb, should be connected in parallel with Rb to reduce switching loss and improve efficiency. Cb can be calculated by the equation below: Cb v

2

Rb

1 fOSC

0.7

It is due to the variation in the characteristics of the transistor used. The calculated value should be used as the initial test value and the optimized value should be obtained by the experiment.

External Component Reference Data VOUT

Inductor Model

Inductor Value

External Transistor

Diode

Output Capacitor

NCP1450ASN19T1

1.9 V

CD54

12 H

MGSF3442VT

MBRM120LT3

220 F

NCP1450ASN30T1

3.0 V

CD54

10 H

MGSF3442VT

MBRM120LT3

220 F

NCP1450ASN50T1

5.0 V

CD54

10 H

MGSF3442VT

MBRM120LT3

220 F

NCP1450ASN19T1

1.9 V

CD54

12 H

MMJT9410

MBRM120LT3

220 F

NCP1450ASN30T1

3.0 V

CD54

10 H

MMJT9410

MBRM120LT3

220 F

NCP1450ASN50T1

5.0 V

CD54

10 H

MMJT9410

MBRM120LT3

220 F

Device


NCP1450A Semiconductor representative for availability. The evaluation board schematic diagrams are shown in Figures 73 and 74.

An evaluation board of NCP1450A has been made in the small size of 89 mm x 51 mm. The artwork and the silk screen of the surface–mount evaluation board PCB are shown in Figures 71 and 72. Please contact your ON

51 mm

89 mm

Figure 71. NCP1450A PWM Step–up DC–DC Controller Evaluation Board Silkscreen

51 mm

89 mm

Figure 72. NCP1450A PWM Step–up DC–DC Controller Evaluation Board Artwork (Component Side)


NCP1450A L1 10 µH

D1 MBRM120LT3

JP1

TP1 VIN

TP2 VOUT MGSF3442VT1

ON CE OFF

NCP1450A

C2 10 µF

CE 1 OUT 2 NC 3

TP4 GND

EXT 5

Q1

C1 220 µF

IC1 GND 4

TP3 GND

Figure 73. NCP1450A Evaluation Board Schematic Diagram 1 (Step–up DC–DC Converter Using External MOSFET Switch)

L2 10 µH

D2 MBRM120LT3

JP2

C4 10 µF

TP8 GND

ON CE OFF

TP6 VOUT CE 1 OUT 2 NC 3

NCP1450A

TP5 VIN

EXT 5

Rb 560

Q2 MMJT9410

C3 220 µF

IC2 GND 4

Cb 3000 pF

TP7 GND

Figure 74. NCP1450A Evaluation Board Schematic Diagram 2 (Step–up DC–DC Converter Using External Bipolar Transistor Switch)

PCB Layout Hints Grounding

efficiency (short and thick traces for connecting the inductor L can also reduce stray inductance), e.g.: short and thick traces listed below are used in the evaluation board: 1. Trace from TP1 to L1 2. Trace from L1 to anode pin of D1 3. Trace from cathode pin of D1 to TP2

One point grounding should be used for the output power return ground, the input power return ground, and the device switch ground to reduce noise. In Figure 73, e.g.: C2 GND, C1 GND, and IC1 GND are connected at one point in the evaluation board. The input ground and output ground traces must be thick enough for current to flow through and for reducing ground bounce.

Output Capacitor

The output capacitor should be placed close to the output terminals to obtain better smoothing effect on the output ripple.

Power Signal Traces

Low resistance conducting paths should be used for the power carrying traces to reduce power loss so as to improve


NCP1450A Components Supplier

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Parts

Supplier

Part Number

Description

Phone

Inductor: L1, L2

Sumida Electric Co. Ltd.

CD54–100MC

Inductor 10 µH/1.44 A

(852) 2880–6688

Schottky Diode: D1, D2

ON Semiconductor

MBRM120LT3

Schottky Power Rectifier

(852) 2689–0088

MOSFET: Q1

ON Semiconductor

MGSF3442VT1

Power MOSFET N–Channel

(852) 2689–0088

BJT: Q2

ON Semiconductor

MMJT9410

Bipolar Power Transistor

(852) 2689–0088

Output Capacitor: C1, C3


T495D227K006AS

Low ESR Tantalum Capacitor 220 µF/6.0 V

(852) 2305–1168

Input Capacitor: C2, C4


T491C106K016AS

Low Profile Tantalum Capacitor 10 µF/16 V

(852) 2305–1168



0.094 2.4

0.037 0.95 0.074 1.9 0.037 0.95 0.028 0.7 0.039 1.0


TSOP–5 T1 ORIENTATION 8 mm


inches mm

) ) '-9'4.4 ;7 " "#" ! The MC34063A Series is a monolithic control circuit containing the primary functions required for DC–to–DC converters. These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch. This series was specifically designed to be incorporated in Step–Down and Step–Up and Voltage–Inverting applications with a minimum number of external components. Refer to Application Notes AN920A/D and AN954/D for additional design information.

• • • • • • •

Operation from 3.0 V to 40 V Input Low Standby Current Current Limiting Output Switch Current to 1.5 A Output Voltage Adjustable Frequency Operation to 100 kHz Precision 2% Reference

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PIN CONNECTIONS

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1504

Publication Order Number: MC34063A/D

MC34063A, MC33063A MAXIMUM RATINGS Symbol

Value

Unit


Rating

VCC

40

Vdc

Comparator Input Voltage Range

VIR

–0.3 to +40

Vdc

Switch Collector Voltage

VC(switch)

40

Vdc

Switch Emitter Voltage (VPin 1 = 40 V)

VE(switch)

40

Vdc

Switch Collector to Emitter Voltage

VCE(switch)

40

Vdc

Driver Collector Voltage

VC(driver)

40

Vdc

Driver Collector Current (Note 1)

IC(driver)

100

mA

ISW

1.5

A

PD RθJA

1.25 100

W °C/W

PD RθJA

625 160

mW °C/W


TJ

+150

°C

Operating Ambient Temperature Range MC34063A MC33063AV MC33063A

TA


Tstg

Switch Current Power Dissipation and Thermal Characteristics Plastic Package, P, P1 Suffix TA = 25°C Thermal Resistance SOIC Package, D Suffix TA = 25°C Thermal Resistance

°C 0 to +70 –40 to +125 –40 to +85

1. Maximum package power dissipation limits must be observed. 2. ESD data available upon request.


–65 to +150

°C

MC34063A, MC33063A ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = Tlow to Thigh [Note 3], unless otherwise specified.) Characteristics

Symbol

Min

Typ

Max

Unit

fosc

24

33

42

kHz

OSCILLATOR Frequency (VPin 5 = 0 V, CT = 1.0 nF, TA = 25°C)

Ichg

24

35

42

µA

Idischg

140

220

260

µA

Discharge to Charge Current Ratio (Pin 7 to VCC, TA = 25°C)

Idischg/Ichg

5.2

6.5

7.5

–

Current Limit Sense Voltage (Ichg = Idischg, TA = 25°C)

Vipk(sense)

250

300

350

mV

Saturation Voltage, Darlington Connection ( ISW = 1.0 A, Pins 1, 8 connected)

VCE(sat)

–

1.0

1.3

V

Saturation Voltage (Note 5) (ISW = 1.0 A, RPin 8 = 82 Ω to VCC, Forced β ] 20)

VCE(sat)

–

0.45

0.7

V

hFE

50

75

–

–

IC(off)

–

0.01

100

µA

1.225 1.21

1.25 –

1.275 1.29

– –

1.4 1.4

5.0 6.0

IIB

–

–20

–400

nA

ICC

–

–

4.0

mA

Charge Current (VCC = 5.0 V to 40 V, TA = 25°C) Discharge Current (VCC = 5.0 V to 40 V, TA = 25°C)

OUTPUT SWITCH (Note 4)

DC Current Gain (ISW = 1.0 A, VCE = 5.0 V, TA = 25°C) Collector Off–State Current (VCE = 40 V) COMPARATOR Threshold Voltage TA = 25°C TA = Tlow to Thigh

Vth

Threshold Voltage Line Regulation (VCC = 3.0 V to 40 V) MC33063A, MC34063A MC33363AV

V

Regline

Input Bias Current (Vin = 0 V)

mV

TOTAL DEVICE Supply Current (VCC = 5.0 V to 40 V, CT = 1.0 nF, Pin 7 = VCC, VPin 5 > Vth, Pin 2 = Gnd, remaining pins open)

3. Tlow = 0°C for MC34063A, –40°C for MC33063A, AV Thigh = +70°C for MC34063A, +85°C for MC33063A, +125°C for MC33063AV 4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible. 5. If the output switch is driven into hard saturation (non–Darlington configuration) at low switch currents (≤ 300 mA) and high driver currents (≥ 30 mA), it may take up to 2.0 µs for it to come out of saturation. This condition will shorten the off time at frequencies ≥ 30 kHz, and is magnified at high temperatures. This condition does not occur with a Darlington configuration, since the output switch cannot saturate. If a non–Darlington configuration is used, the following output drive condition is recommended: IC output w 10 Forced of output switch : IC driver – 7.0 mA * * The 100 Ω resistor in the emitter of the driver device requires about 7.0 mA before the output switch conducts.


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Figure 2. Output Switch On–Off Time versus Oscillator Timing Capacitor

Figure 3. Timing Capacitor Waveform

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Figure 5. Common Emitter Configuration Output Switch Saturation Voltage versus Collector Current

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Figure 4. Emitter Follower Configuration Output Saturation Voltage versus Emitter Current

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Figure 6. Current Limit Sense Voltage versus Temperature

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Figure 7. Standby Supply Current versus Supply Voltage

6. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible.


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Test

Conditions

Results

Line Regulation

Vin = 8.0 V to 16 V, IO = 175 mA

30 mV = ±0.05%

Load Regulation

Vin = 12 V, IO = 75 mA to 175 mA

10 mV = ±0.017%

Output Ripple

Vin = 12 V, IO = 175 mA

400 mVpp

Efficiency

Vin = 12 V, IO = 175 mA

87.7%

Output Ripple With Optional Filter

Vin = 12 V, IO = 175 mA

40 mVpp

Figure 8. Step–Up Converter


MC34063A, MC33063A

!

230

2

!

230

2 ³ 7 03!(!

Figure 9. External Current Boost Connections for IC Peak Greater than 1.5 A 9a. External NPN Switch

9b. External NPN Saturated Switch (See Note 7)

7. If the output switch is driven into hard saturation (non–Darlington configuration) at low switch currents (≤ 300 mA) and high driver currents (≥ 30 mA), it may take up to 2.0 µs to come out of saturation. This condition will shorten the off time at frequencies ≥ 30 kHz, and is magnified at high temperatures. This condition does not occur with a Darlington configuration, since the output switch cannot saturate. If a non–Darlington configuration is used, the following output drive condition is recommended.


MC34063A, MC33063A

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Conditions

Results

Line Regulation

Vin = 15 V to 25 V, IO = 500 mA

12 mV = ±0.12%

Load Regulation

Vin = 25 V, IO = 50 mA to 500 mA

3.0 mV = ±0.03%

Output Ripple

Vin = 25 V, IO = 500 mA

120 mVpp


Vin = 25 V, RL = 0.1 Ω

1.1 A

Efficiency

Vin = 25 V, IO = 500 mA

83.7%


Vin = 25 V, IO = 500 mA

40 mVpp

Figure 10. Step–Down Converter

!

230

230


11b. External PNP Saturated Switch


MC34063A, MC33063A

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Test

Conditions

Results

Line Regulation

Vin = 4.5 V to 6.0 V, IO = 100 mA

3.0 mV = ±0.012%

Load Regulation

Vin = 5.0 V, IO = 10 mA to 100 mA

0.022 V = ±0.09%

Output Ripple

Vin = 5.0 V, IO = 100 mA

500 mVpp


Vin = 5.0 V, RL = 0.1 Ω

910 mA

Efficiency

Vin = 5.0 V, IO = 100 mA

62.2%


Vin = 5.0 V, IO = 100 mA

70 mVpp

Figure 12. Voltage Inverting Converter

!

!


13b. External PNP Saturated Switch


MC34063A, MC33063A $"′′

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*:A3(!?A+HA;&2;+A

*:A3(!?A&2*:A;&2;+A

%D

Figure 5. Feedback Comparator 2 Threshold Voltage versus Temperature

Figure 6. Bootstrap Input Current Source versus Temperature

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Figure 8. Output Switch Source Saturation versus Emitter Current

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Figure 9. Output Switch Sink Saturation versus Collector Current


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Figure 11. Low Voltage Indicator Output Sink Saturation Voltage versus Sink Current

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Figure 10. Output Switch Negative Emitter Voltage versus Temperature

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Figure 13. Current Limit Comparator Input Bias Current versus Temperature

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Figure 12. Current Limit Comparator Threshold Voltage versus Temperature

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Figure 15. Standby Supply Current versus Temperature


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Figure 17. P Suffix (DIP–16) Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length

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MC34163, MC33163

MC34163, MC33163

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Figure 20. Typical Operating Waveforms


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MC34163, MC33163 INTRODUCTION

of an external deadtime resistor (RDT) placed across CT. The resistor increases the discharge current which reduces the on–time of the output switch. A graph of the Output Switch On–Off Time versus Oscillator Timing Capacitance for various values of RDT is shown in Figure 2. Note that the maximum output duty cycle, ton/ton + toff, remains constant for values of CT greater than 0.2 nF. The converter output can be inhibited by clamping CT to ground with an external NPN small–signal transistor.

The MC34163 series are monolithic power switching regulators optimized for dc–to–dc converter applications. The combination of features in this series enables the system designer to directly implement step–up, step–down, and voltage–inverting converters with a minimum number of external components. Potential applications include cost sensitive consumer products as well as equipment for the automotive, computer, and industrial markets. A Representative Block Diagram is shown in Figure 19.

Feedback and Low Voltage Indicator Comparators

Output voltage control is established by the Feedback comparator. The inverting input is internally biased at 1.25 V and is not pinned out. The converter output voltage is typically divided down with two external resistors and monitored by the high impedance noninverting input at Pin 2. The maximum input bias current is ±0.4 µA, which can cause an output voltage error that is equal to the product of the input bias current and the upper divider resistance value. For applications that require 5.0 V, the converter output can be directly connected to the noninverting input at Pin 3. The high impedance input, Pin 2, must be grounded to prevent noise pickup. The internal resistor divider is set for a nominal voltage of 5.05 V. The additional 50 mV compensates for a 1.0% voltage drop in the cable and connector from the converter output to the load. The Feedback comparator’s output state is controlled by the highest voltage applied to either of the two noninverting inputs. The Low Voltage Indicator (LVI) comparator is designed for use as a reset controller in microprocessor–based systems. The inverting input is internally biased at 1.125 V, which sets the noninverting input thresholds to 90% of nominal. The LVI comparator has 15 mV of hysteresis to prevent erratic reset operation. The Open Collector output is capable of sinking in excess of 6.0 mA (see Figure 11). An external resistor (RLVI) and capacitor (CDLY) can be used to program a reset delay time (tDLY) by the formula shown below, where Vth(MPU) is the microprocessor reset input threshold. Refer to Figure 21.

OPERATING DESCRIPTION The MC34163 operates as a fixed on–time, variable off–time voltage mode ripple regulator. In general, this mode of operation is somewhat analogous to a capacitor charge pump and does not require dominant pole loop compensation for converter stability. The Typical Operating Waveforms are shown in Figure 20. The output voltage waveform shown is for a step–down converter with the ripple and phasing exaggerated for clarity. During initial converter startup, the feedback comparator senses that the output voltage level is below nominal. This causes the output switch to turn on and off at a frequency and duty cycle controlled by the oscillator, thus pumping up the output filter capacitor. When the output voltage level reaches nominal, the feedback comparator sets the latch, immediately terminating switch conduction. The feedback comparator will inhibit the switch until the load current causes the output voltage to fall below nominal. Under these conditions, output switch conduction can be inhibited for a partial oscillator cycle, a partial cycle plus a complete cycle, multiple cycles, or a partial cycle plus multiple cycles. Oscillator

The oscillator frequency and on–time of the output switch are programmed by the value selected for timing capacitor CT. Capacitor CT is charged and discharged by a 9 to 1 ratio internal current source and sink, generating a negative going sawtooth waveform at Pin 6. As CT charges, an internal pulse is generated at the oscillator output. This pulse is connected to the NOR gate center input, preventing output switch conduction, and to the AND gate upper input, allowing the latch to be reset if the comparator output is low. Thus, the output switch is always disabled during ramp–up and can be enabled by the comparator output only at the start of ramp–down. The oscillator peak and valley thresholds are 1.25 V and 0.55 V, respectively, with a charge current of 225 µA and a discharge current of 25 µA, yielding a maximum on–time duty cycle of 90%. A reduction of the maximum duty cycle may be required for specific converter configurations. This can be accomplished with the addition

tDLY = RLVI CDLY In

ǒ

1 Vth(MPU) 1– Vout

Ǔ

Current Limit Comparator, Latch and Thermal Shutdown

With a voltage mode ripple converter operating under normal conditions, output switch conduction is initiated by the oscillator and terminated by the Voltage Feedback comparator. Abnormal operating conditions occur when the converter output is overloaded or when feedback voltage sensing is lost. Under these conditions, the Current Limit comparator will protect the Output Switch.


MC34163, MC33163 additional device heating and reduced conversion efficiency. Figure 10 shows that by clamping the emitter to 0.5 V, the collector current will be in the range 10 µA over temperature. A 1N5822 or equivalent Schottky barrier rectifier is recommended to fulfill these requirements. A bootstrap input is provided to reduce the output switch saturation voltage in step–down and voltage–inverting converter applications. This input is connected through a series resistor and capacitor to the switch emitter and is used to raise the internal 2.0 mA bias current source above VCC. An internal zener limits the bootstrap input voltage to VCC +7.0 V. The capacitor’s equivalent series resistance must limit the zener current to less than 100 mA. An additional series resistor may be required when using tantalum or other low ESR capacitors. The equation below is used to calculate a minimum value bootstrap capacitor based on a minimum zener voltage and an upper limit current source.

The switch current is converted to a voltage by inserting a fractional ohm resistor, RSC, in series with VCC and output switch transistor Q2. The voltage drop across RSC is monitored by the Current Sense comparator. If the voltage drop exceeds 250 mV with respect to VCC, the comparator will set the latch and terminate output switch conduction on a cycle–by–cycle basis. This Comparator/Latch configuration ensures that the Output Switch has only a single on–time during a given oscillator cycle. The calculation for a value of RSC is: RSC +

0.25 V Ipk (Switch)

Figures 12 and 13 show that the Current Sense comparator threshold is tightly controlled over temperature and has a typical input bias current of 1.0 µA. The propagation delay from the comparator input to the Output Switch is typically 200 ns. The parasitic inductance associated with RSC and the circuit layout should be minimized. This will prevent unwanted voltage spikes that may falsely trip the Current Limit comparator. Internal thermal shutdown circuitry is provided to protect the IC in the event that the maximum junction temperature is exceeded. When activated, typically at 170°C, the Latch is forced into the “Set” state, disabling the Output Switch. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used as a replacement for proper heatsinking.

CB(min) + I t + 4.0 mA ton + 0.001 ton V 4.0 V

Parametric operation of the MC34163 is guaranteed over a supply voltage range of 2.5 V to 40 V. When operating below 3.0 V, the Bootstrap Input should be connected to VCC. Figure 16 shows that functional operation down to 1.7 V at room temperature is possible. Package

The MC34163 is contained in a heatsinkable 16–lead plastic dual–in–line package in which the die is mounted on a special heat tab copper alloy lead frame. This tab consists of the four center ground pins that are specifically designed to improve thermal conduction from the die to the circuit board. Figures 17 and 18 show a simple and effective method of utilizing the printed circuit board medium as a heat dissipater by soldering these pins to an adequate area of copper foil. This permits the use of standard layout and mounting practices while having the ability to halve the junction–to–air thermal resistance. These examples are for a symmetrical layout on a single–sided board with two ounce per square foot of copper.


To aid in system design flexibility and conversion efficiency, the driver current source and collector, and output switch collector and emitter are pinned out separately. This allows the designer the option of driving the output switch into saturation with a selected force gain or driving it near saturation when connected as a Darlington. The output switch has a typical current gain of 70 at 2.5 A and is designed to switch a maximum of 40 V collector to emitter, with up to 3.4 A peak collector current. The minimum value for RSC is: RSC(min) + 0.25 V + 0.0735 3.4 A

APPLICATIONS

When configured for step–down or voltage–inverting applications, as in Figures 21 and 25, the inductor will forward bias the output rectifier when the switch turns off. Rectifiers with a high forward voltage drop or long turn–on delay time should not be used. If the emitter is allowed to go sufficiently negative, collector current will flow, causing

The following converter applications show the simplicity and flexibility of this circuit architecture. Three main converter topologies are demonstrated with actual test data shown below each of the circuit diagrams.


MC34163, MC33163

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Results

Line Regulation

Vin = 8.0 V to 24 V, IO = 3.0 A

6.0 mV = ± 0.06%

Load Regulation

Vin = 12 V, IO = 0.6 A to 3.0 A

2.0 mV = ± 0.02%

Output Ripple

Vin = 12 V, IO = 3.0 A

36 mVpp


Vin = 12 V, RL = 0.1 Ω

3.3 A

Efficiency, Without Bootstrap

Vin = 12 V, IO = 3.0 A

76.7%

Efficiency, With Bootstrap

Vin = 12 V, IO = 3.0 A

81.2%

Figure 21. Step–Down Converter

+

C C

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#

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C

C

#

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+

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#

#

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!!5

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Figure 22A. External NPN Switch

Figure 22B. External PNP Saturated Switch

Figure 22. External Current Boost Connections for Ipk (Switch) Greater Than 3.4 A


MC34163, MC33163

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Condition

Results

Line Regulation

Vin = 9.0 V to 16 V, IO = 0.6 A

30 mV = ± 0.05%

Load Regulation

Vin = 12 V, IO = 0.1 A to 0.6 A

50 mV = ± 0.09%

Output Ripple

Vin = 12 V, IO = 0.6 A

140 mVpp

Efficiency

Vin = 12 V, IO = 0.6 A

88.1%


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Condition

Results

Line Regulation

Vin = 9.0 V to 16 V, IO = 1.0 A

5.0 mV = ± 0.02%

Load Regulation

Vin = 12 V, IO = 0.6 A to 1.0 A

2.0 mV = ± 0.01%

Output Ripple

Vin = 12 V, IO = 1.0 A

130 mVpp


Vin = 12 V, RL = 0.1 Ω

3.2 A

Efficiency, Without Bootstrap

Vin = 12 V, IO = 1.0 A

73.1%

Efficiency, With Bootstrap

Vin = 12 V, IO = 1.0 A

77.5%

Figure 25. Voltage–Inverting Converter

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Figure 27. Printed Circuit Board and Component Layout (Circuits of Figures 21, 23, 25)


+

MC34163, MC33163 Step–Down

Calculation ton (Notestoff 1, 2, 3)

V

V out ) V F * V sat * V out in

ǒ

ton ƒ

t on t off

Voltage–Inverting

V out ) V – V F in V – V sat in

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Step–Up

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R2

ref

R1

Ǔ

t on ) 1 t off

ǒ

Ǔ

t on ) 1 t off

IL(avg) )

t on

ǒ

V

t on I out C

t on t off

I

L 2

0.25 Ipk (Switch)

Ǔ

L

ǒ

I out

I

* V sat

in

F * V sat

in

32.143 · 10 –6 ƒ

t on ) 1 t off

2

Vripple(pp)

ƒ

0.25 Ipk (Switch)

* V sat * V out I L

ǒ8 ƒ1COǓ

ǒ

IL(avg) )

0.25 Ipk (Switch)

L

Ǔ

t on ) 1 t off

32.143 · 10 –6 ƒ I out

IL(avg) )

RSC

ǒ

t on t off

V

in

C

O

Ǔ

V

L

ǒ

R2

ref

t on

t on I out

[

) 1

Ǔ

* V sat I

R1

O

Ǔ

) 1

The following Converter Characteristics must be chosen: Nominal operating input voltage. Desired output voltage. Desired output current. Desired peak–to–peak inductor ripple current. For maximum output current it is suggested that ∆IL be chosen to be less than 10% of the average inductor current IL(avg). This will help prevent Ipk (Switch) from reaching the current limit threshold set by RSC. If the design goal is to use a minimum inductance value, let ∆IL = 2(IL(avg)). This will proportionally reduce converter output current capability. – Maximum output switch frequency. Vripple(pp) – Desired peak–to–peak output ripple voltage. For best performance the ripple voltage should be kept to a low value since it will directly affect line and load regulation. Capacitor CO should be a low equivalent series resistance (ESR) electrolytic designed for switching regulator applications. Vin – Vout – Iout – ∆IL –

NOTES: NOTES: NOTES: NOTES:

1. 2. 3. 3.

Vsat – Saturation voltage of the output switch, refer to Figures 8 and 9. VF – Output rectifier forward voltage drop. Typical value for 1N5822 Schottky barrier rectifier is 0.5 V. The calculated ton/toff must not exceed the minimum guaranteed oscillator charge to discharge ratio of 8, at the minimum operating input voltage.

Figure 28. Design Equations


) )

'-9'4.4 ;7 " "#" ! The MC34166, MC33166 series are high performance fixed frequency power switching regulators that contain the primary functions required for dc–to–dc converters. This series was specifically designed to be incorporated in step–down and voltage–inverting configurations with a minimum number of external components and can also be used cost effectively in step–up applications. These devices consist of an internal temperature compensated reference, fixed frequency oscillator with on–chip timing components, latching pulse width modulator for single pulse metering, high gain error amplifier, and a high current output switch. Protective features consist of cycle–by–cycle current limiting, undervoltage lockout, and thermal shutdown. Also included is a low power standby mode that reduces power supply current to 36 µA. • Output Switch Current in Excess of 3.0 A • Fixed Frequency Oscillator (72 kHz) with On–Chip Timing • Provides 5.05 V Output without External Resistor Divider • Precision 2% Reference • 0% to 95% Output Duty Cycle • Cycle–by–Cycle Current Limiting • Undervoltage Lockout with Hysteresis • Internal Thermal Shutdown • Operation from 7.5 V to 40 V • Standby Mode Reduces Power Supply Current to 36 µA • Economical 5–Lead TO–220 Package with Two Optional Leadforms • Also Available in Surface Mount D2PAK Package • Moisture Sensitivity Level (MSL) Equals 1

http://onsemi.com x A WL Y WW

= 3 or 4 = Assembly Location = Wafer Lot = Year = Work Week TO–220 TH SUFFIX CASE 314A

MARKING DIAGRAMS

MC 3x166T AWLYWW

1 5


1

MC 3x166T AWLYWW

5


MC 3x166T AWLYWW


"

+,+G+

1

30''(!

C

5

2

Pin

IG &, 4 5('

,

1. 2. 3. 4. 5.

Voltage Feedback Input Switch Output Ground Input Voltage/VCC Compensation/Standby

2 7 0 :;

$ #$ ;

#


1 5


MC 3x166T AWLYWW

1

5



Figure 1. Simplified Block Diagram (Step Down Application)




1529


MC34166, MC33166 MAXIMUM RATINGS (Note 2) Symbol

Rating Power Supply Input Voltage Switch Output Voltage Range Voltage Feedback and Compensation Input Voltage Range

Value

Unit

VCC

40

V

VO(switch)

–1.5 to + Vin

V

VFB, VComp

–1.0 to + 7.0

V

Power Dissipation Case 314A, 314B and 314D (TA = +25°C) Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case Case 936A (D2PAK) (TA = +25°C) Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case

PD θJA θJC PD θJA θJC




TJ

+150

°C


TA


Tstg

°C 0 to + 70 – 40 to + 85

1. Maximum package power dissipation limits must be observed to prevent thermal shutdown activation. 2. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL–STD–883, Method 3015. Machine Model Method 200 V. Thigh = + 70°C for MC34166 3. Tlow = 0°C for MC34166 = – 40°C for MC33166 = + 85°C for MC33166


– 65 to +150

°C

MC34166, MC33166 ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TA = +25°C, for min/max values TA is the operating ambient temperature range that applies [Notes 4, 5], unless otherwise noted.) Symbol

Min

Typ

Max

Unit

TA = +25°C TA = Tlow to Thigh

fOSC

65 62

72 –

79 81

kHz


VFB(th)

4.95 4.85

5.05 –

5.15 5.2

V

Regline

–

0.03

0.078

%/V

Characteristic OSCILLATOR Frequency (VCC = 7.5 V to 40 V) ERROR AMPLIFIER Voltage Feedback Input Threshold

Line Regulation (VCC = 7.5 V to 40 V, TA = +25°C)

IIB

–

0.15

1.0

µA

PSRR

60

80

–

dB

VOH VOL

4.2 –

4.9 1.6

– 1.9

DC(max) DC(min)

92 0

95 0

100 0

Vsat

–

(VCC –1.5)

(VCC –1.8)

V

Isw(off)

–

0

100

µA

Ipk(switch)

3.3

4.3

6.0

Input Bias Current (VFB = VFB(th) + 0.15 V) Power Supply Rejection Ratio (VCC = 10 V to 20 V, f = 120 Hz) Output Voltage Swing High State (ISource = 75 µA, VFB = 4.5 V) Low State (ISink = 0.4 mA, VFB = 5.5 V)

V

PWM COMPARATOR Duty Cycle Maximum (VFB = 0 V) Minimum (VComp = 1.9 V)

%

SWITCH OUTPUT Output Voltage Source Saturation (VCC = 7.5 V, ISource = 3.0 A) Off–State Leakage (VCC = 40 V, Pin 2 = Gnd) Current Limit Threshold Switching Times (VCC = 40 V, Ipk = 3.0 A, L = 375 µH, TA = +25°C) Output Voltage Rise Time Output Voltage Fall Time

A ns

tr tf

– –

100 50

200 100

Startup Threshold (VCC Increasing, TA = +25°C)

Vth(UVLO)

5.5

5.9

6.3

V

Hysteresis (VCC Decreasing, TA = +25°C)

VH(UVLO)

0.6

0.9

1.2

V

– –

36 31

100 55

µA mA


TOTAL DEVICE Power Supply Current (TA = +25°C ) Standby (VCC = 12 V, VComp < 0.15 V) Operating (VCC = 40 V, Pin 1 = Gnd for maximum duty cycle)

ICC

4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Thigh = + 70°C for MC34166 5. Tlow = 0°C for MC34166 = – 40°C for MC33166 = + 85°C for MC33166


MC34166, MC33166 ** >

!4 G(9 > $

$ $

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!4?A,;:A::);*HA+&A-2:-,)A

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$ $ $

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$ $ $ +1? && +H *&22: 5;

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Figure 5. Error Amp Output Saturation versus Sink Current

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%D %D

$

Figure 4. Error Amp Open Loop Gain and Phase versus Frequency

;? ;G+: :G:2;&2: °*

Figure 3. Voltage Feedback Input Bias Current versus Temperature

3(! ?A&&A;&2;+A,;:A

Figure 2. Voltage Feedback Input Threshold versus Temperature

%D

** > ; > . °*

"

$

Figure 6. Oscillator Frequency Change versus Temperature

$

$ #$ #$ "$ *5? *G:;+ ,;:

Figure 7. Switch Output Duty Cycle versus Compensation Voltage


"$

**

%D$

3 ?AI+*-A&&A,;:A

3(! ?AI+*-A&&A&2*:A;&2;+A

MC34166, MC33166

; > . °*

% $ % $ %D $ %D $ %D#$

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** > 3 ? ? # >

"$

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;? ;G+: :G:2;&2: °*

" > ** 3 ? #? > ; > . °*

"

Figure 10. Switch Output Current Limit Threshold versus Temperature

# **? &,B ,;:

"


$

" !(! 4 34' ** +0 (3

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+ **?A&,BA*&22:A5;

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;? ;G+: :G:2;&2: °*

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$ "$ "$ %D

%D

Figure 9. Negative Switch Output Voltage versus Temperature

+ **?A&,BA*&22:A µ ;

+ 13 !04 ?A*&22:A,+G+A-2:-,)A;

Figure 8. Switch Output Source Saturation versus Source Current

#$ %D

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;? ;G+: :G:2;&2: °*

#

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Figure 12. Undervoltage Lockout Threshold versus Temperature

# **? &,B ,;:

Figure 13. Operating Supply Current versus Supply Voltage


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MC34166, MC33166 * ! 3

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The MC34166 can be used cost effectively in off–line applications even though it is limited to a maximum input voltage of 40 V. Figure 28 shows a simple and efficient method for converting the AC line voltage down to 24 V. This preconverter has a total power rating of 125 W with a conversion efficiency of 90%. Transformer T1 provides output isolation from the AC line and isolation between each of the secondaries. The circuit self–oscillates at 50 kHz and is controlled by the saturation characteristics of T2. Multiple MC34166 post regulators can be used to provide accurate independently regulated outputs for a distributed power system.

F&*+OO;+2AAA*I °

2 θ F;?A-:2G;,A2:+;*:

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#

$

,? ,:- *:2 55




Figure 28. Off–Line Preconverter

MC34166, MC33166

Table 1. Design Equations Calculation

Step–Down

Step–Up/Down

Voltage–Inverting

ton toff (Notes 1, 2)

Vout ) VF Vin * Vsat * Vout

Vout ) VF1 ) VF2 Vin * VsatQ1 * VsatQ2

|Vout| ) VF Vin * Vsat

!

ton toff ton fosc )1 toff



Duty Cycle (Note 3)

ton fosc

ton fosc

ton fosc

IL avg

Iout

t Iout on ) 1 toff

t Iout on ) 1 toff

Ipk(switch)

I IL avg ) L 2

I IL avg ) L 2

I IL avg ) L 2

L

ǒVin * VIsatL * VoutǓton

* VsatQ2 ǒVin * VsatQ1 Ǔton IL

ǒVin *ILVsatǓton

Vripple(pp)

ǒ

IL

Ǹǒ

Ǔ

ǒ

Ǔ

1 2 ) (ESR)2 8foscCo

ǒ

ǒ

Ǔ

Ǔ

ǒtton ) 1Ǔ Ǹǒ 1 Ǔ2 ) (ESR)2 foscCo off

Ǔ

ǒ

Ǔ

ǒ

ǒ

Ǔ

Ǔ

ǒtton ) 1Ǔ Ǹǒ 1 Ǔ2 ) (ESR)2 foscCo off ǒ

Ǔ

R R R Vref 2 ) 1 Vref 2 ) 1 Vref 2 ) 1 R1 R1 R1 1. Vsat – Switch Output source saturation voltage, refer to Figure 8. 2. VF – Output rectifier forward voltage drop. Typical value for 1N5822 Schottky barrier rectifier is 0.5 V. 3. Duty cycle is calculated at the minimum operating input voltage and must not exceed the guaranteed minimum DC(max) specification of 0.92. Vout

The following converter characteristics must be chosen: Vout – Desired output voltage. Iout – Desired output current. ∆IL – Desired peak–to–peak inductor ripple current. For maximum output current especially when the duty cycle is greater than 0.5, it is suggested that ∆IL be chosen to be less than 10% of the average inductor current IL avg. This will help prevent Ipk(switch) from reaching the guaranteed minimum current limit threshold of 3.3 A. If the design goal is to use a minimum inductance value, let ∆IL = 2 (IL avg). This will proportionally reduce the converter’s output current capability. Vripple(pp) – Desired peak–to–peak output ripple voltage. For best performance, the ripple voltage should be kept to less than 2% of Vout. Capacitor CO should be a low equivalent series resistance (ESR) electrolytic designed for switching regulator applications.


MC34166, MC33166 ORDERING INFORMATION Device


Package

MC33166D2T

D2PAK

(Surface Mount)

MC33166D2TR4

D2PAK

(Surface Mount)

MC33166T


TA= –40° to +85°C

MC33166TH

TO–220 (Horizontal Mount)

MC33166TV


MC34166D2T


MC34166D2TR4


MC34166T

Shipping


TA= 0° to +70°C

MC34166TH


MC34166TV



50 Units/Rail

) * ) *

'-9'4.4 ;7 " "#" ! The MC34167, MC33167 series are high performance fixed frequency power switching regulators that contain the primary functions required for dc–to–dc converters. This series was specifically designed to be incorporated in step–down and voltage–inverting configurations with a minimum number of external components and can also be used cost effectively in step–up applications. These devices consist of an internal temperature compensated reference, fixed frequency oscillator with on–chip timing components, latching pulse width modulator for single pulse metering, high gain error amplifier, and a high current output switch. Protective features consist of cycle–by–cycle current limiting, undervoltage lockout, and thermal shutdown. Also included is a low power standby mode that reduces power supply current to 36 µA. • Output Switch Current in Excess of 5.0 A • Fixed Frequency Oscillator (72 kHz) with On–Chip Timing • Provides 5.05 V Output without External Resistor Divider • Precision 2% Reference • 0% to 95% Output Duty Cycle • Cycle–by–Cycle Current Limiting • Undervoltage Lockout with Hysteresis • Internal Thermal Shutdown • Operation from 7.5 V to 40 V • Standby Mode Reduces Power Supply Current to 36 µA • Economical 5–Lead TO–220 Package with Two Optional Leadforms • Also Available in Surface Mount D2PAK Package • Moisture Sensitivity Level (MSL) Equals 1

http://onsemi.com x A WL Y WW

= 3 or 4 = Assembly Location = Wafer Lot = Year = Work Week

MARKING DIAGRAMS

TO–220 TH SUFFIX CASE 314A

MC 3x167T AWLYWW


MC 3x167T AWLYWW

1 5

1 5



"

+,+G+

1

30''(!

MC 3x167T AWLYWW

C

5

2

Pin

IG &, 4 5('

,

1. 2. 3. 4. 5.

Voltage Feedback Input Switch Output Ground Input Voltage/VCC Compensation/Standby

2 7 0 :;

$ $ ;

#



1 5


MC 3x167T AWLYWW

1

5


Figure 1. Simplified Block Diagram (Step Down Application)  Semiconductor Components Industries, LLC, 2002



1546


MC34167, MC33167 MAXIMUM RATINGS (Note 2) Rating Power Supply Input Voltage Switch Output Voltage Range

Symbol

Value

Unit

VCC

40

V

VO(switch)

–2.0 to + Vin

V

VFB, VComp

–1.0 to + 7.0

V

Power Dissipation Case 314A, 314B and 314D (TA = +25°C) Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case Case 936A (D2PAK) (TA = +25°C) Thermal Resistance, Junction–to–Ambient Thermal Resistance, Junction–to–Case

PD θJA θJC PD θJA θJC




TJ

+150

°C


TA


Tstg

Voltage Feedback and Compensation Input Voltage Range

°C 0 to + 70 – 40 to + 85

1. Maximum package power dissipation limits must be observed to prevent thermal shutdown activation. 2. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL–STD–883, Method 3015. Machine Model Method 200 V. Thigh = + 70°C for MC34167 3. Tlow = 0°C for MC34167 = – 40°C for MC33167 = + 85°C for MC33167


– 65 to +150

°C

MC34167, MC33167 ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TA = +25°C, for min/max values TA is the operating ambient temperature range that applies [Notes 4, 5], unless otherwise noted.) Symbol

Min

Typ

Max

Unit


fOSC

65 62

72 –

79 81

kHz

TA =+ 25°C TA = Tlow to Thigh

VFB(th)

4.95 4.85

5.05 –

5.15 5.20

V

Regline

–

0.03

0.078

%/V

Characteristic OSCILLATOR Frequency (VCC = 7.5 V to 40 V) ERROR AMPLIFIER Voltage Feedback Input Threshold

Line Regulation (VCC = 7.5 V to 40 V, TA = +25°C) Input Bias Current (VFB = VFB(th) + 0.15 V) Power Supply Rejection Ratio (VCC = 10 V to 20 V, f = 120 Hz) Output Voltage Swing

High State (ISource = 75 µA, VFB = 4.5 V) Low State (ISink = 0.4 mA, VFB = 5.5 V)

IIB

–

0.15

1.0

µA

PSRR

60

80

–

dB

VOH VOL

4.2 –

4.9 1.6

– 1.9

V

DC(max) DC(min)

92 0

95 0

100 0

%

Vsat

–

(VCC –1.5)

(VCC –1.8)

V

PWM COMPARATOR Duty Cycle (VCC = 20 V)

Maximum (VFB = 0 V) Minimum (VComp = 1.9 V)

SWITCH OUTPUT Output Voltage Source Saturation (VCC = 7.5 V, ISource = 5.0 A)

Isw(off)

–

0

100

µA

Ipk(switch)

5.5

6.5

8.0

A

tr tf

– –

100 50

200 100

Startup Threshold (VCC Increasing, TA = +25°C)

Vth(UVLO)

5.5

5.9

6.3

V

Hysteresis (VCC Decreasing, TA = +25°C)

VH(UVLO)

0.6

0.9

1.2

V

– –

36 40

100 60

µA mA

Off–State Leakage (VCC = 40 V, Pin 2 = Gnd) Current Limit Threshold (VCC = 7.5 V) Switching Times (VCC = 40 V, Ipk = 5.0 A, L = 225 µH, TA = +25°C) Output Voltage Rise Time Output Voltage Fall Time

ns


TOTAL DEVICE Power Supply Current (TA = +25°C ) Standby (VCC = 12 V, VComp < 0.15 V) Operating (VCC = 40 V, Pin 1 = Gnd for maximum duty cycle)

ICC

4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Thigh = + 70°C for MC34167 5. Tlow = 0°C for MC34167 = – 40°C for MC33167 = + 85°C for MC33167


$

** >

$ $

!4 @ > $

$ !4 G > "$ "$# "$ %D

%D

;? ;G+: :G:2;&2: °*

** > > !4

"

%D

Figure 2. Voltage Feedback Input Threshold versus Temperature

(

** > *5 > #$ 2, > 1 ; > . °*

"

4(3

#

%D

$ 1 1 1 7? 2:C&:*B -6

G

$ G

)*?AI+*-A&&A)&BA*B*,:AE

∆ 7 *?A*+,,;2A2:C&:*BA*-;:AE

** >

%D"$

%D$

%D

;? ;G+: :G:2;&2: °*

$ $ $

** > > $ ; > . °*

$"

$"

$ $ $ +1? && +H *&22: 5;

$

Figure 5. Error Amp Output Saturation versus Sink Current

"$

%D %D

;? ;G+: :G:2;&2: °*

$


%D

Figure 3. Voltage Feedback Input Bias Current versus Temperature

φ?A:L*:A-;:A):2::

; , ?A:A,A,;:A;+A

+ +?A+&A+;A*&22:A;

!4 G(9 > $

3(! ?A&&A;&2;+A,;:A

!4?A,;:A::);*HA+&A-2:-,)A

MC34167, MC33167

** > ; > . °*

"

$

Figure 6. Oscillator Frequency Change versus Temperature

$

$ #$ #$ "$ *5? *G:;+ ,;:

Figure 7. Switch Output Duty Cycle versus Compensation Voltage


"$

**

%D$

3 ?AI+*-A&&A,;:A

3(!?AI+*-A&&A&2*:A;&2;+A

MC34167, MC33167

; > . °*

% $ % $

%D $

%D $ %D#$

$ "$ $ + 0 ? I+*- && &2*: *&22: ;

%D$

** > > $ 3 ? # > )< (!<

%D$" %D$ %D$

+3 > 5;

% $ % $ %D

$

$ ** > 3 ? ? # > $

$"

$

%D

;? ;G+: :G:2;&2: °*

"

# **? &,B ,;:

"


$

!(! 4 34' ** +0 (3

$

+ **?A&,BA*&22:A5;

!4&, ?A&):2,;:A,*H&A-2:-,)A

;? ;G+: :G:2;&2: °*

" > ** 3 ? #? > ; > . °*

Figure 10. Switch Output Current Limit Threshold versus Temperature

$ %77 4 34' ** ) 0 (3

$ "$ "$ %D

%D

Figure 9. Negative Switch Output Voltage versus Temperature

+ ** ?A&,BA*&22:A µ ;

+ 13 !04?A*&22:A,+G+A-2:-,)A;

Figure 8. Switch Output Source Saturation versus Source Current

$ %D

+3 > µ;

%D

;? ;G+: :G:2;&2: °*

" #

" > ** 3 ? # > 3 ? ; > . °*

Figure 12. Undervoltage Lockout Thresholds versus Temperature

# **? &,B ,;:

Figure 13. Operating Supply Current versus Supply Voltage


"

MC34167, MC33167 * ! 3

.

*

"

*

30''(!

!04 ! !

C 2 '3 I!4 G '(!

,

$ 2 7 0

.

.

: ;5

µ;

*5 3(!

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#

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.

! !A#

> * % )H 9 $ 9 # -* > " ! 3 0 ! !( S# ;I > - (!31 > ;;+) : +0$ > G*#" ( GF: # % # > G2 * %

The MC34167 can be used cost effectively in off–line applications even though it is limited to a maximum input voltage of 40 V. Figure 28 shows a simple and efficient method for converting the AC line voltage down to 24 V. This preconverter has a total power rating of 125 W with a conversion efficiency of 90%. Transformer T1 provides output isolation from the AC line and isolation between each of the secondaries. The circuit self–oscillates at 50 kHz and is controlled by the saturation characteristics of T2. Multiple MC34167 post regulators can be used to provide accurate independently regulated outputs for a distributed power system.

F&*+OO;+2AAA*I °

2 θ F;?A-:2G;,A2:+;*:

#$

; G ! !0(''@


$ 6$ * ,

G5 5 6 (

$

$

,

"

$

2θF; #

#$

)5(9 7 ; > .°*

$

#

$

,? ,:- *:2 55




Figure 28. Off–Line Preconverter

MC34167, MC33167 Table 1. Design Equations Calculation

Step–Down

Step–Up/Down

Voltage–Inverting

ton toff (Notes 1, 2)

Vout ) VF Vin * Vsat * Vout

Vout ) VF1 ) VF2 Vin * VsatQ1 * VsatQ2

|Vout| ) VF Vin * Vsat

ton




Duty Cycle (Note 3)

ton fosc

ton fosc

ton fosc

IL avg

Iout

t Iout on ) 1 toff

t Iout on ) 1 toff

Ipk(switch)

I IL avg ) L 2

I IL avg ) L 2

I IL avg ) L 2

L

ǒVin * VIsatL * VoutǓton

* VsatQ2 ǒVin * VsatQ1 Ǔton IL

ǒVin *ILVsatǓton

Vripple(pp)

ǒ

IL

Ǹǒ

Ǔ

ǒ

Ǔ

1 2 ) (ESR)2 8foscCo

ǒ

ǒ

Ǔ

Ǔ

ǒtton ) 1Ǔ Ǹǒ 1 Ǔ2 ) (ESR)2 foscCo off

Ǔ

ǒ

Ǔ

ǒ

ǒ

Ǔ

Ǔ

ǒtton ) 1Ǔ Ǹǒ 1 Ǔ2 ) (ESR)2 foscCo off ǒ

Ǔ

R R R Vref 2 ) 1 Vref 2 ) 1 Vref 2 ) 1 R1 R1 R1 1. Vsat – Switch Output source saturation voltage, refer to Figure 8. 2. VF – Output rectifier forward voltage drop. Typical value for 1N5822 Schottky barrier rectifier is 0.35 V. 3. Duty cycle is calculated at the minimum operating input voltage and must not exceed the guaranteed minimum DC(max) specification of 0.92. Vout

The following converter characteristics must be chosen: Vout – Desired output voltage. Iout – Desired output current. ∆IL – Desired peak–to–peak inductor ripple current. For maximum output current especially when the duty cycle is greater than 0.5, it is suggested that ∆IL be chosen minimum current limit threshold of 5.5 A. If the design goal is to use a minimum inductance value, let ∆IL = 2 (IL avg). This will proportionally reduce the converter’s output current capability. Vripple(pp) – Desired peak–to–peak output ripple voltage. For best performance, the ripple voltage should be kept to less than 2% of Vout. Capacitor CO should be a low equivalent series resistance (ESR) electrolytic designed for switching regulator applications.


MC34167, MC33167 ORDERING INFORMATION Device


Package D2PAK

MC33167D2T MC33167T MC33167TH

(Surface Mount)

TO–220 (Straight Lead) TA= –40° 40° to +85°C


MC33167TV


MC34167D2T


MC34167T MC34167TH

Shipping

TO–220 (Straight Lead) TA= 0° to +70°C


MC34167TV



50 Units/Rail

5! 85$0 The CS51031 is a switching controller for use in DC–DC converters. It can be used in the buck topology with a minimum number of external components. The CS51031 consists of a VCC monitor for controlling the state of the device, 1.0 A power driver for controlling the gate of a discrete P–channel transistor, fixed frequency oscillator, short circuit protection timer, programmable soft start, precision reference, fast output voltage monitoring comparator, and output stage driver logic with latch. The high frequency oscillator allows the use of small inductors and output capacitors, minimizing PC board area and systems cost. The programmable soft start reduces current surges at start up. The short circuit protection timer significantly reduces the duty cycle to approximately 1/30 of its cycle during short circuit conditions. The CS51031 is available in 8 Lead SO and 8 Lead PDIP plastic packages. Features • 1.0 A Totem Pole Output Driver • High Speed Oscillator (700 kHz max) • No Stability Compensation Required • Lossless Short Circuit Protection • VCC Monitor • 2.0% Precision Reference • Programmable Soft Start • Wide Ambient Temperature Range: – Industrial Grade: –40°C to 85°C – Commercial Grade: 0°C to 70°C 5.0 V–12 V

http://onsemi.com MARKING DIAGRAMS 8 SO–8 D SUFFIX CASE 751

8 1

1 8 DIP–8 N SUFFIX CASE 626

8

20 Ω MP1 IRF7416

VGATE VGATE

MBRS360

VC

CS51031 AWL YYWW



PIN CONNECTIONS VGATE

CIN 47 µF

51031 ALYW

1

VC

PGND

CS

COSC GND

VCC VFB


D1

COSC 100 pF

COSC

CS51031

Device PGND

CS RVCC 10 Ω VCC

CS 0.1 µF

CVCC 100 µF 100

GND

VFB

.01 µF

L 4.7 µH

RB 2.5 kΩ

VO 3.3 V @ 3 A

CRR 0.1 µF RA 1.5 kΩ

CO 100 µF × 2

Package

Shipping

CS51031YD8

SO–8

95 Units/Rail

CS51031YDR8

SO–8

2500 Tape & Reel

CS51031YN8

DIP–8

50 Units/Rail

CS51031GD8

SO–8

95 Units/Rail

CS51031GDR8

SO–8

2500 Tape & Reel

*Additional ordering information can be found on page 1571 of this data sheet.



May, 2001 – Rev. 8

1563



Value

Unit


20

V

Driver Supply Voltage, VC

20

V

Driver Output Voltage, VGATE

20

V

COSC, CS, VFB (Logic Pins)

6.0

V

Peak Output Current

1.0

A

Steady State Output Current

200

mA


150

°C

Operating Temperature Range, TA

–40 to 85

°C

Storage Temperature Range, TS

–65 to 150

°C

2.0

kV

260 peak 230 peak

°C °C

ESD (Human Body Model) Lead Temperature Soldering:

Wave Solder: (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2)

1. 10 sec. maximum. 2. 60 sec. max above 183°C. *The maximum package power dissipation must be observed.

ELECTRICAL CHARACTERISTICS (Specifications apply for 4.5 ≤ VCC ≤ 16 V, 3.0 V ≤ VC ≤ 16 V; Industrial Grade: –40°C < TA < 85°C; –40°C < TJ < 125°C: Commercial Grade: 0°C < TA < 70°C; 0°C < TJ < 125°C, unless otherwise specified.) Characteristic Oscillator

Test Conditions

Min

Typ

Max

Unit

160

200

240

kHz

VFB = 1.2 V

Frequency

COSC = 470 pF

Charge Current

1.4 V < VCOSC < 2.0 V

–

110

–

µA

Discharge Current

2.7 V > VCOSC > 2.0 V

–

660

–

µA

Maximum Duty Cycle

1 – (tOFF/tON)

80.0

83.3

–

%

Short Circuit Timer

VFB = 1.0 V; CS = 0.1 mF; VCOSC = 2.0 V

Charge Current

1.0 V < VCS < 2.0 V

175

264

325

µA

Fast Discharge Current

2.55 V > VCS > 2.4 V

40

66

80

µA

Slow Discharge Current

2.4 V > VCS > 1.5 V

4.0

6.0

10

µA

Start Fault Inhibit Time

0 V < VCS < 2.5 V

0.70

0.85

1.40

ms

Valid Fault Time

2.6 V > VCS > 2.4 V

0.2

0.3

0.45

ms

GATE Inhibit Time

2.4 V > VCS > 1.5 V

9.0

15

23

ms

–

2.5

3.1

4.6

%

–

–

2.5

–

V

Fault Duty Cycle CS Comparator

VFB = 1.0 V

Fault Enable CS Voltage Max. CS Voltage

VFB = 1.5 V

–

2.6

–

V

Fault Detect Voltage

VCS when GATE goes high

–

2.4

–

V

Fault Inhibit Voltage

Minimum VCS

–

1.5

–

V

Hold Off Release Voltage

VFB = 0 V

0.4

0.7

1.0

V

Regulator Threshold Voltage Clamp

VCS = 1.5 V

0.725

0.866

1.035

V


CS51031 ELECTRICAL CHARACTERISTICS (continued) (Specifications apply for 4.5 ≤ VCC ≤ 16 V, 3.0 V ≤ VC ≤ 16 V; Industrial Grade: –40°C < TA < 85°C; –40°C < TJ < 125°C: Commercial Grade: 0°C < TA < 70°C; 0°C < TJ < 125°C, unless otherwise specified.) Characteristic VFB Comparators

Test Conditions

Min

Typ

Max

Unit

VCOSC = VCS = 2.0 V

Regulator Threshold Voltage

TJ = 25°C (Note 3) TJ = –40 to 125°C

1.225 1.210

1.250 1.250

1.275 1.290

V V

Fault Threshold Voltage

TJ = 25°C (Note 3) TJ = –40 to 125°C

1.12 1.10

1.15 1.15

1.17 1.19

V V

Threshold Line Regulation

4.5 V ≤ VCC ≤ 16 V

–

6.0

15

mV

Input Bias Current

VFB = 0 V

–

1.0

4.0

µA

Voltage Tracking

(Regulator Threshold – Fault Threshold Voltage)

70

100

120

mV

–

–

4.0

20

mV

Input Hysteresis Voltage Power Stage

VCC = VC = 10 V; VFB = 1.2 V

GATE DC Low Saturation Voltage

VCOSC = 1.0 V; 200 mA Sink

–

1.2

1.5

V

GATE DC High Saturation Voltage

VCOSC = 2.7 V; 200 mA Source; VC = VGATE

–

1.5

2.1

V

Rise Time

CGATE = 1.0 nF; 1.5 V < VGATE < 9.0 V

–

25

60

ns

Fall Time

CGATE = 1.0 nF; 9.0 V > VGATE > 1.5 V

–

25

60

ns

VCC Monitor Turn On Threshold

–

4.200

4.400

4.600

V

Turn Off Threshold

–

4.085

4.300

4.515

V

Hysteresis

–

65

130

200

mV

Current Drain ICC

4.5 V < VCC < 16 V, Gate switching

–

4.5

6.0

mA

IC

3.0 V < VC < 16 V, Gate non–switching

–

2.7

4.0

mA

Shutdown ICC

VCC = 4.0

–

500

900

µA


PACKAGE LEAD DESCRIPTION PACKAGE PIN NUMBER SO–8

DIP–8

PIN SYMBOL

1

1

VGATE

Driver pin to gate of external PFET.

2

2

PGND

Output power stage ground connection.

3

3

COSC

Oscillator frequency programming capacitor.

4

4

GND

Logic ground.

5

5

VFB

Feedback voltage input.

6

6

VCC

Logic supply voltage.

7

7

CS

Soft start and fault timing capacitor.

8

8

VC

Driver supply voltage.

FUNCTION


CS51031

VC

VREF RG IC

Oscillator

7IC

VGATE

VGATE Flip–Flop

+ Comparator A1 –

COSC

G1

R

Q F2 Q

2.5 V

–

VFB Comparator

– +

A6 + 0.7 V – +

+ –

VREF 3.3 V

– Fault Comp

+

G4

VREF = 3.3 V

1.15 V CS Charge Sense Comparator

– +

VCCOK

VCC

– +

Hold Off Comp

VCC

G3 +

A4

IT

CS Comparator

– +

+ A2 –

1.5 V

R

2.3 V

Q F1

G5 2.5 V

2.4 V

– +

IT 5

– +

IT 55

– +

CS

VFB

1.25 V

–

– +

1.5 V

PGND

S

G2

– A3 + Slow Discharge Comparator

S

Q

Slow Discharge Flip–Flop

GND


CIRCUIT DESCRIPTION THEORY OF OPERATION

duration of the charge time. The PFET gets turned off and remains off during the oscillator’s discharge time with the maximum duty cycle to 80%. It requires 7.0 mV typical, and 20 mV maximum ripple on the VFB pin is required to operate. This method of control does not require any loop stability compensation.

Control Scheme

The CS51031 monitors and the output voltage to determine when to turn on the PFET. If VFB falls below the internal reference voltage of 1.25 V during the oscillator’s charge cycle, the PFET is turned on and remains on for the


CS51031 Startup

Lossless Short Circuit Protection

The CS51031 has an externally programmable soft start feature that allows the output voltage to come up slowly, preventing voltage overshoot on the output. At startup, the voltage on all pins is zero. As VCC rises, the VC voltage along with the internal resistor RG keeps the PFET off. As VCC and VC continue to rise, the oscillator capacitor (COSC ) and the Soft Start/Fault Timing capacitor (CS) charges via internal current sources. COSC gets charged by the current source IC and CS gets charged by the IT source combination described by:

The CS51031 has “lossless” short circuit protection since there is no current sense resistor required. When the voltage at the CS pin (the fault timing capacitor voltage ) reaches 2.5 V during startup, the fault timing circuitry is enabled. During normal operation the CS voltage is 2.6 V. During a short circuit or a transient condition, the output voltage moves lower and the voltage at VFB drops. If VFB drops below 1.15 V, the output of the fault comparator goes high and the CS51031 goes into a fast discharge mode. The fault timing capacitor, CS, discharges to 2.4 V. If the VFB voltage is still below 1.15 V when the CS pin reaches 2.4 V, a valid fault condition has been detected. The slow discharge comparator output goes high and enables gate G5 which sets the slow discharge flip flop. The VGATE flip flop resets and the output switch is turned off. The fault timing capacitor is slowly discharged to 1.5 V. The CS51031 then enters a normal startup routine. If the fault is still present when the fault timing capacitor voltage reaches 2.5 V, the fast and slow discharge cycles repeat as shown in figure 3. If the VFB voltage is above 1.15 V when CS reaches 2.4 V a fault condition is not detected, normal operation resumes and CS charges back to 2.6 V. This reduces the chance of erroneously detecting a load transient as a fault condition.

ǒ

I I ICS + IT * T ) T 55 5

Ǔ

The internal Holdoff Comparator ensures that the external PFET is off until VCS > 0.7 V, preventing the GATE flip–flop (F2) from being set. This allows the oscillator to reach its operating frequency before enabling the drive output. Soft start is obtained by clamping the VFB comparator’s (A6) reference input to approximately 1/2 of the voltage at the CS pin during startup, permitting the control loop and the output voltage to slowly increase. Once the CS pin charges above the Holdoff Comparator trip point of 0.7 V, the low feedback to the VFB Comparator sets the GATE flip–flop during COSC ’s charge cycle. Once the GATE flip–flop is set, VGATE goes low and turns on the PFET. When VCS exceeds 2.4 V, the CS charge sense comparator (A4) sets the VFB comparator reference to 1.25 V completing the startup cycle.

2.6 V VCS

S2

2.4 V

S2

S1

S3

S3

S1

2.5 V

S2 S3

S1

S3

1.5 V 0V

0V TSTART START

td1 NORMAL OPERATION

tFAULT

tRESTART

td2

FAULT

VGATE 1.25 V 1.15 V VFB

Figure 3. Voltage on Start Capacitor (VGS), the Gate (VGATE), and in the Feedback Loop (VFB), During Startup, Normal and Fault Conditions.


tFAULT

CS51031 Buck Regulator Operation

and R2 and the reference voltage VREF, the power transistor Q1 switches on and current flows through the inductor to the output. The inductor current rises at a rate determined by (VIN – VOUT)/L. The duty cycle (or “on” time) for the CS51031 is limited to 80%. If output voltage remains higher than nominal during the entire COSC change time, the Q1 does not turn on, skipping the pulse.

A block diagram of a typical buck regulator is shown in Figure 4. If we assume that the output transistor is initially off, and the system is in discontinuous operation, the inductor current IL is zero and the output voltage is at its nominal value. The current drawn by the load is supplied by the output capacitor CO. When the voltage across CO drops below the threshold established by the feedback resistors R1

L

Q1

VIN

R1

CIN

CO

D1

RLOAD

R2 Control

Feedback

Figure 4. Buck Regulator Block Diagram.

APPLICATIONS INFORMATION CS51031 DESIGN EXAMPLE

If VF = 0.60 V and VSAT = 0.60 V then the above equation becomes:

Specifications 12 V to 5.0 V, 3.0 A Buck Controller

DMAX + 5.6 + 0.62 9.0

• VIN = 12 V ±20% (i.e. 14.4 V max., 12 V nom., 9.6 V • • • • •

min.) VOUT = 5.0 V ±2% IOUT = 0.3 A to 3.0 A Output ripple voltage < 50 mV max. Efficiency > 80% fSW = 200 kHz

DMIN + 5.6 + 0.40 13.8 2) Switching Frequency and On and Off Time Calculations

Given that fSW = 200 kHz and DMAX = 0.80 T + 1.0 + 5.0 s fSW

1) Duty Cycle Estimates

Since the maximum duty cycle D, of the CS51031 is limited to 80% min., it is necessary to estimate the duty cycle for the various input conditions over the complete operating range. The duty cycle for a buck regulator operating in a continuous conduction mode is given by: D+

TON(max) + T

DMAX + 5.0 s

TON(min) + T

DMIN + 5.0 s

0.62 ^ 3.0 s 0.40 ^ 2.0 s

TOFF(max) + TON(min) + 5.0 s * 2.0 s + 3.0 s

VOUT ) VF VIN * VSAT

3) Oscillator Capacitor Selection

The switching frequency is set by COSC, whose value is given by:

where: VSAT = Rds(on) × IOUT max. and Rds(on) is the value at TJ 100°C.

COSC in pF +

ǒ

10*6

95

FSW 106

FSW 1 ) 3


* ǒ30F

103 SW

Ǔ

2

Ǔ

CS51031 6) VFB Divider

4) Inductor Selection

ǒ

The inductor value is chosen for continuous mode operation down to 0.3 Amps. The ripple current ∆I = 2 × IOUTmin = 2 × 0.3 A = 0.6 A. L min +

(VOUT ) VD)

TOFF(max)

I

I +

TOFF(min)

LMIN

Let R2 = 1.0 K Rearranging the divider equation gives: OUT * 1.0Ǔ + 1.0 kǒ5.0 V * 1.0Ǔ + 3.0 k ǒV1.25 1.25

R1 + R2

IMAX + IOUT ) Iń2 + 3.0 A ) 0.4 Ań2 + 3.2 A

7) Divider Bypass Capacitor CRR

5) Output Capacitor

Since the feedback resistors divide the output voltage by a factor of 4.0, i.e. 5.0 V/1.25 V= 4.0, it follows that the output ripple is also divided by four. This would require that the output ripple be at least 60 mV (4.0 × 15 mV) to trip the feedback comparator. We use a capacitor CRR to act as an AC short. The ripple voltage frequency is equal to the switching frequency so we choose CRR = 1.0 nF.

The output capacitor and the inductor form a low pass filter. The output capacitor should have a low ESL and ESR. Low impedance aluminum electrolytic, tantalum or organic semiconductor capacitors are a good choice for an output capacitor. Low impedance aluminum are less expensive. Solid tantalum chip capacitors are available from a number of suppliers and are the best choice for surface mount applications. The output capacitor limits the output ripple voltage. The CS51031 needs a maximum of 20 mV of output ripple for the feedback comparator to change state. If we assume that all the inductor ripple current flows through the output capacitor and that it is an ideal capacitor (i.e. zero ESR), the minimum capacitance needed to limit the output ripple to 50 mV peak to peak is given by: 8.0

I fSW

V

+

8.0

(200

0.6 A 103Hz) (50

10*3 V)

8) Soft Start and Fault Timing Capacitor CS

CS performs several important functions. First it provides a delay time for load transients so that the IC does not enter a fault mode every time the load changes abruptly. Secondly it disables the fault circuitry during startup, it also provides soft start by clamping the reference voltage during startup, allowing it to rise slowly, and, finally it controls the hiccup short circuit protection circuitry. This reduces the duty cycle to approximately 0.035 during short circuit conditions. An important consideration in calculating CS is that it’s voltage does not reach 2.5 V (the voltage at which the fault detect circuitry is enabled) before VFB reaches 1.15 V otherwise the power supply will never start. If the VFB pin reaches 1.15 V, the fault timing comparator will discharge CS and the supply will not start. For the VFB voltage to reach 1.15 V the output voltage must be at least 4 × 1.15 = 4.6 V. If we choose an arbitrary startup time of 900 µs, the value of CS is:

+ 7.5F

The minimum ESR needed to limit the output voltage ripple to 50 mV peak to peak is: *3 ESR + V + 50 10 + 83 m 0.6 A I

The output capacitor should be chosen so that its ESR is less than 83 mΩ. During the minimum off time, the ripple current is 0.4 A and the output voltage ripple will be: V + ESR

Ǔ

5.0 V + R1 ) R2 + 5.0 K 1.0 mA

5.6 V 2.0 s + + 0.4 A 28 H

The core must not saturate with the maximum expected current, here given by:

C+

ǒ

The input bias current to the comparator is 4.0 µA. The resistor divider current should be considerably higher than this to ensure that there is sufficient bias current. If we choose the divider current to be at least 250 times the bias current this permits a divider current of 1mA and simplifies the calculations.

5.6 V 3.0 s + + 28 H 0.6 A

This is the minimum value of inductor to keep the ripple current < 0.6 A during normal operation. A smaller inductor will result in larger ripple current. Ripple current at a minimum off time is (VOUT ) VF)

Ǔ

VOUT + 1.25 V R1 ) R2 + 1.25 V R1 ) 1.0 R2 R2

I + 83m

0.4 + 33 mV

tStartup + CS 2.5 V ICharge CS min +


900 s 264 A + 950 nF ^ 0.1 F 2.5 V

CS51031 the VCC and VC pins. This capacitor must also ensure that the VCC remains above the UVLO voltage in the event of an output short circuit. A low ESR capacitor of at least 100 µF is good. A ceramic surface mount capacitor should also be connected between VCC and ground to filter high frequency noise.

The fault time is the sum of the slow discharge time the fast discharge time and the recharge time. It is dominated by the slow discharge time. The first parameter is the slow discharge time, it is the time for the CS capacitor to discharge from 2.4 V to 1.5 V and is given by: tSlowDischarge(t) +

CS

(2.4 V * 1.5 V) IDischarge

10) MOSFET Selection

The CS51031 drives a P–channel MOSFET. The VGATE pin swings from GND to VC. The type of PFET used depends on the operating conditions but for input voltages below 7.0 V a logic level FET should be used. A PFET with a continuous drain current (ID) rating greater than the maximum output current is required. The Gate–to–Source voltage VGS and the Drain–to Source Breakdown Voltage should be chosen based on the input supply voltage. The power dissipation due to the conduction losses is given by:

where IDischarge is 6.0 µA typical. tSlowDischarge(t) + CS

1.5

105

The fast discharge time occurs when a fault is first detected. The CS capacitor is discharged from 2.5 V to 2.4 V. tFastDischarge(t) +

CS

(2.5 V * 2.4 V) IFastDischarge

where IFastDischarge is 66 µA typical. tFastDischarge(t) + CS

1515

PD + IOUT2

The recharge time is the time for CS to charge from 1.5 V to 2.5 V. tCharge(t) +

CS

RDS(ON) is the value at TJ + 100°C

The power dissipation of the PFET due to the switching losses is given by:

where ICharge is 264 µA typical.

PD + 0.5

3787

(3787 ) 1515 ) 1.5

tFault + CS

(1.55

105)

10*6

IOUT

(tr)

fSW

11) Diode Selection

The flyback or catch diode should be a Schottky diode because of it’s fast switching ability and low forward voltage drop. The current rating must be at least equal to the maximum output current. The breakdown voltage should be at least 20 V for this 12 V application. The diode power dissipation is given by:

105)

For this circuit tFault + 0.1

VIN

where tr = Rise Time.

The fault time is given by: tFault + CS

D

where

(2.5 V * 1.5 V) ICharge

tCharge(t) + CS

RDS(ON)

1.55

105 + 15.5 s

A larger value of CS will increase the fault time out time but will also increase the soft start time.

PD + IOUT

9) Input Capacitor

The input capacitor reduces the peak currents drawn from the input supply and reduces the noise and ripple voltage on


VD

(1.0 * D min)

CS51031 ORDERING INFORMATION Operating Temperature Range

Package

Shipping

CS51031YD8

–40°C < TA < 85°C

SO–8

95 Units/Rail

CS51031YDR8

–40°C < TA < 85°C

SO–8

2500 Tape & Reel

CS51031YN8

–40°C < TA < 85°C

DIP–8

50 Units/Rail

CS51031GD8

0°C < TA < 70°C

SO–8

95 Units/Rail

CS51031GDR8

0°C < TA < 70°C

SO–8

2500 Tape & Reel

Device


SO–8

DIP–8

Unit

RΘJC

Typical

45

52

°C/W

RΘJA

Typical

165

100

°C/W


5! 85$0 The CS51033 is a switching controller for use in DC–DC converters. It can be used in the buck topology with a minimum number of external components. The CS51033 consists of a 1.0 A power driver for controlling the gate of a discrete P–channel transistor, fixed frequency oscillator, short circuit protection timer, programmable Soft Start, precision reference, fast output voltage monitoring comparator, and output stage driver logic with latch. The high frequency oscillator allows the use of small inductors and output capacitors, minimizing PC board area and systems cost. The programmable Soft Start reduces current surges at start up. The short circuit protection timer significantly reduces the PFET duty cycle to approximately 1/30 of its normal cycle during short circuit conditions. The CS51033 is available in 8 Lead SO and 8 Lead PDIP plastic packages.

http://onsemi.com MARKING DIAGRAMS 8 SO–8 D SUFFIX CASE 751

8 1

51033 ALYW 1 8

Features • 1.0 A Totem Pole Output Driver • High Speed Oscillator (700 kHz max) • No Stability Compensation Required • Lossless Short Circuit Protection • 2.0% Precision Reference • Programmable Soft Start • Wide Ambient Temperature Range: – Industrial Grade: –40°C to 85°C – Commercial Grade: 0°C to 70°C

DIP–8 N SUFFIX CASE 626

8

CS51033 AWL YYWW



PIN CONNECTIONS VGATE

1

VC

PGND

CS

COSC GND

VCC VFB


Package

Shipping

CS51033ED8

SO–8

95 Units/Rail

CS51033EDR8

SO–8

2500 Tape & Reel

CS51033EN8

DIP–8

50 Units/Rail

CS51033GD8

SO–8

95 Units/Rail

CS51033GDR8

SO–8

2500 Tape & Reel

CS51033GN8

DIP–8

50 Units/Rail

*Additional ordering information can be found on page 1580 of this data sheet.



1572


CS51033 3.3VIN CIN 100 µF

D2 1N4148

RC 10 Ω D4 1N5818

C1

D3 1N4148

0.1 µF RG

VC V GATE VCC

COSC

U1 CS51033

10 Ω

IRF7404

0.1 µF

VFB

4.7 µH 1.5VOUT @ 3.0 Amp 100

C2 1.0 µF

C3 100 µF

COSC 150 pF

GND PGND CS

0.1 µF CS

C0 100 µF

0.1 µF

100 µF

C4 0.1 µF

D1

1N5821 GND

GND RA 1.5 k

RB 300

Note: Capacitors C2, C3, and C4, are low ESR tantalum caps used for noise reduction.



Value

Unit


5.0

V

Driver Supply Voltage, VC

20

V

Driver Output Voltage, VGATE

20

V

COSC, CS, VFB (Logic Pins)

5.0

V

Peak Output Current

1.0

A

Steady State Output Current

200

mA


150

°C

–65 to 150

°C

2.0

kV

260 peak 230 peak

°C °C

Storage Temperature Range, TS ESD (Human Body Model) Lead Temperature Soldering:

Wave Solder: (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2)

1. 10 sec. maximum. 2. 60 sec. max above 183°C. *The maximum package power dissipation must be observed.


CS51033 ELECTRICAL CHARACTERISTICS (Specifications apply for 3.135 ≤ VCC ≤ 3.465, 3.0 V ≤ VC ≤ 16 V; Industrial Grade: –40°C < TA < 85°C; –40°C < TJ < 125°C: Commercial Grade: 0°C < TA < 70°C; 0°C < TJ < 125°C, unless otherwise specified.) Test Conditions

Characteristic Oscillator

Min

Typ

Max

Unit

160

200

240

kHz

VFB = 1.2 V

Frequency

COSC = 470 pF

Charge Current

1.4 V < VCOSC < 2.0 V

–

110

–

µA

Discharge Current

2.7 V > VCOSC > 2.0 V

–

660

–

µA

Maximum Duty Cycle

1 – (tOFF/tON)

80.0

83.3

–

%

Short Circuit Timer

VFB = 1.0 V; CS = 0.1 mF; VCOSC = 2.0 V

Charge Current

1.0 V < VCS < 2.0 V

175

264

325

µA

Fast Discharge Current

2.55 V > VCS > 2.4 V

40

66

80

µA

Slow Discharge Current

2.4 V > VCS > 1.5 V

4.0

6.0

10

µA

0.70

0.85

1.40

ms

Start Fault Inhibit Time

–

Valid Fault Time

2.6 V > VCS > 2.4 V

0.2

0.3

0.45

ms

GATE Inhibit Time

2.4 V > VCS > 1.5 V

9.0

15

23

ms

–

2.5

3.1

4.6

%

–

–

2.5

–

V

Duty Cycle CS Comparator

VFB = 1.0 V

Fault Enable CS Voltage Max. CS Voltage

VFB = 1.5 V

–

2.6

–

V

Fault Detect Voltage

VCS when GATE goes high

–

2.4

–

V

Fault Inhibit Voltage

Minimum VCS

–

1.5

–

V

Hold Off Release Voltage

VFB = 0 V

0.4

0.7

1.0

V

Regulator Threshold Voltage Clamp

VCS = 1.5 V

0.725

0.866

1.035

V

VFB Comparators

VCOSC = VCS = 2.0 V

Regulator Threshold Voltage

TJ = 25°C (Note 3) TJ = –40 to 125°C

1.225 1.210

1.250 1.250

1.275 1.290

V V

Fault Threshold Voltage

TJ = 25°C (Note 3) TJ = –40 to 125°C

1.12 1.10

1.15 1.15

1.17 1.19

V V

Threshold Line Regulation

3.135 V ≤ VCC ≤ 3.465

–

6.0

15

mV

Input Bias Current

VFB = 0 V

–

1.0

4.0

µA

Voltage Tracking

(Regulator Threshold – Fault Threshold Voltage)

70

100

120

mV

–

–

4.0

20

mV

Input Hysteresis Voltage Power Stage

VC = 10 V; VFB = 1.2 V

GATE DC Low Saturation Voltage

VCOSC = 1.0 V; 200 mA Sink

–

1.2

1.5

V

GATE DC High Saturation Voltage

VCOSC = 2.7 V; 200 mA Source; VC = VGATE

–

1.5

2.1

V

Rise Time

CGATE = 1.0 nF; 1.5 V < VGATE < 9.0 V

–

25

60

ns

Fall Time

CGATE = 1.0 nF; 9.0 V > VGATE > 1.5 V

–

25

60

ns

ICC

3.135 V < VCC < 3.465 V, Gate switching

–

3.5

6.0

mA

IC

3.0 V < VC < 16 V, Gate non–switching

–

2.7

4.0

mA

Current Drain



CS51033 PACKAGE LEAD DESCRIPTION PACKAGE PIN NUMBER SO–8

DIP–8

PIN SYMBOL

1

1

VGATE

Driver pin to gate of external PFET.

2

2

PGND

Output power stage ground connection.

3

3

COSC

Oscillator frequency programming capacitor.

4

4

GND

Logic ground.

5

5

VFB

Feedback voltage input.

6

6

VCC

Logic supply voltage.

7

7

CS

Soft Start and fault timing capacitor.

8

8

VC

Driver supply voltage.

FUNCTION

VC

VCC RG IC

Oscillator

7IC

VGATE

VGATE Flip–Flop

+ Comparator A1 –

COSC

G1

R

Q F2 Q

2.5 V

–

– +

– +

1.5 V

PGND

S

G2

VFB Comparator

A6 + 0.7 V – +

+ VCC

– +

Hold Off Comp

VFB

1.25 V

–

VCC – 1.15 V

CS Charge Sense Comparator

G3 +

A4

IT

CS Comparator + A2 –

R

G5

2.4 V

2.3 V

Q F1

2.5 V

– +

1.5 V

– +

IT 5

– +

IT 55

– +

CS

–

+

G4

– +

Fault Comp

– A3 + Slow Discharge Comparator

S

Q

Slow Discharge Flip–Flop

GND



CS51033 CIRCUIT DESCRIPTION THEORY OF OPERATION

pin during startup, permitting the control loop and the output voltage to slowly increase. Once the CS pin charges above the Holdoff Comparator trip point of 0.7 V, the low feedback to the VFB Comparator sets the GATE flip–flop during COSC’s charge cycle. Once the GATE flip–flop is set, VGATE goes low and turns on the PFET. When VCS exceeds 2.4 V, the CS charge sense comparator (A4) sets the VFB comparator reference to 1.25 V completing the startup cycle.

Control Scheme

The CS51033 monitors the output voltage to determine when to turn on the PFET. If VFB falls below the internal reference voltage of 1.25 V during the oscillator’s charge cycle, the PFET is turned on and remains on for the duration of the charge time. The PFET gets turned off and remains off during the oscillator’s discharge cycle time with the maximum duty cycle to 80%. It requires 7.0 mV typical, and 20 mV maximum ripple on the VFB pin to operate. This method of control does not require any loop stability compensation.

Lossless Short Circuit Protection

The CS51033 has “lossless” short circuit protection since there is no current sense resistor required. When the voltage at the CS pin (the fault timing capacitor voltage ) reaches 2.5 V, the fault timing circuitry is enabled. During normal operation the CS voltage is 2.6 V. During a short circuit or a transient condition, the output voltage moves lower and the voltage at VFB drops. If VFB drops below 1.15 V, the output of the fault comparator goes high and the CS51033 goes into a fast discharge mode. The fault timing capacitor, CS, discharges to 2.4 V. If the VFB voltage is still below 1.15 V when the CS pin reaches 2.4 V, a valid fault condition has been detected. The slow discharge comparator output goes high and enables gate G5 which sets the slow discharge flip flop. The VGATE flip flop resets and the output switch is turned off. The fault timing capacitor is slowly discharged to 1.5 V. The CS51033 then enters a normal startup routine. If the fault is still present when the fault timing capacitor voltage reaches 2.5 V, the fast and slow discharge cycles repeat as shown in Figure 3. If the VFB voltage is above 1.15 V when CS reaches 2.4 V a fault condition is not detected, normal operation resumes and CS charges back to 2.6 V. This reduces the chance of erroneously detecting a load transient as a fault condition.

Startup

The CS51033 has an externally programmable Soft Start feature that allows the output voltage to come up slowly, preventing voltage overshoot on the output. At startup, the voltage on all pins is zero. As VCC rises, the VC voltage along with the internal resistor RG keeps the PFET off. As VCC and VC continue to rise, the oscillator capacitor (COSC ) and the Soft Start/Fault Timing capacitor (CS) charges via internal current sources. COSC gets charged by the current source IC and CS gets charged by the IT source combination described by:

ǒ

I I ICS + IT * T ) T 55 5

Ǔ

The internal Holdoff Comparator ensures that the external PFET is off until VCS > 0.7 V, preventing the GATE flip–flop (F2) from being set. This allows the oscillator to reach its operating frequency before enabling the drive output. Soft Start is obtained by clamping the VFB comparator’s (A6) reference input to approximately 1/2 of the voltage at the CS

2.6 V VCS

S2

2.4 V

S2

S1

S3

S3

S1

2.5 V

S2 S3

S1

S3

1.5 V 0V

0V TSTART START

td1 NORMAL OPERATION

tFAULT

tRESTART

td2

FAULT

VGATE 1.25 V 1.15 V VFB

Figure 3. Voltage on Start Capacitor (VGS), the Gate (VGATE), and in the Feedback Loop (VFB), During Startup, Normal and Fault Conditions.


tFAULT

CS51033 Buck Regulator Operation

and R2 and the reference voltage VREF, the power transistor Q1 switches on and current flows through the inductor to the output. The inductor current rises at a rate determined by (VIN – VOUT)/Load. The duty cycle (or “on” time) for the CS51033 is limited to 80%. If output voltage remains higher than nominal during the entire COSC change time, the Q1 does not turn on, skipping the pulse.

A block diagram of a typical buck regulator is shown in Figure 4. If we assume that the output transistor is initially off, and the system is in discontinuous operation, the inductor current IL is zero and the output voltage is at its nominal value. The current drawn by the load is supplied by the output capacitor CO. When the voltage across CO drops below the threshold established by the feedback resistors R1

L

Q1

VIN

R1

CIN

CO

D1

RLOAD

R2 Control

Feedback

Figure 4. Buck Regulator Block Diagram. Charge Pump Circuit

turns on, it’s drain voltage will be approximately equal to VIN. Since the voltage across C1 can not change instantaneously, D2 is reverse biased and the anode voltage rises to approximately 2.0 × 3.3 V – VD2. C1 transfers some of its stored charge C2 via D3. After several cycles there is sufficient gate drive voltage.

(Refer to the CS51033 Application Diagram on page 1573). An external charge pump circuit is necessary when the VC input voltage is below 5.0 V to ensure that there is suffifient gate drive voltage for the external FET. When VIN is applied, capacitors C1 and C2 will be charged to a diodes drop below VIN via diodes D2 and D4, respectively. When the PFET

APPLICATIONS INFORMATION DESIGNING A POWER SUPPLY WITH THE CS51033

In this case we can assume that VD = 0.6 V and VSAT = 0.6 V so the equation reduces to:

Specifications

• • • • •

V D + OUT VIN

VIN = 3.3 V ±10% (i.e. 3.63 V max., 2.97 V min.) VOUT = 1.5 V ±2.0% IOUT = 0.3 A to 3.0 A Output ripple voltage < 33 mV. FSW = 200 kHz

From this, the maximum duty cycle DMAX is 53%, this occurs when VIN is at it’s minimum while the minimum duty cycle DMIN is 0.35%. 2) Switching Frequency and On and Off Time Calculations

1) Duty Cycle Estimates

Since the maximum duty cycle D, of the CS51033 is limited to 80% min., it is best to estimate the duty cycle for the various input conditions to see that the design will work over the complete operating range. The duty cycle for a buck regulator operating in a continuous conduction mode is given by:

FSW = 200 kHz. The switching frequency is determined by COSC, whose value is determined by:

V ) VD D + OUT VIN * VSAT

T + 1.0 + 5.0 s FSW

COSC + FSW

ǒ1 * ǒ

95

FSW 3 106

TON(MAX) + 5.0 s

where: VSAT = RDS(ON) × IOUT Max. http://onsemi.com 1577

Ǔ * ǒ30F

103 SW

Ǔ

2

Ǔ

^ 470 pF

0.53 + 2.65 s

CS51033 TON(MIN) + 5.0 s

0.35 + 1.75 s

this to ensure that there is sufficient bias current. If we choose the divider current to be at least 250 times the bias current this gives a divider current of 1.0 mA and simplifies the calculations.

TOFF(MAX) + 5.0 s * 0.7 s + 4.3 s 3) Inductor Selection

1.5 V + R1 ) R2 + 1.5 k 1.0 mA

Pick the inductor value to maintain continuous mode operation down to 0.3 Amps. The ripple current ∆I = 2 × IOUT(MIN) = 2 × 0.3 A = 0.6 A.

Let R2 = 1.0 k Rearranging the divider equation gives: OUT * 1.0Ǔ + 1.0 kǒ1.5 VǓ + 200 ǒV1.25 1.25

2.1 V 4.3 s V ) VD TOFF(MAX) LMIN + OUT + ^ 15 H I 0.6 A

R1 + R2

The CS51033 will operate with almost any value of inductor. With larger inductors the ripple current is reduced and the regulator will remain in a continuous conduction mode for lower values of load current. A smaller inductor will result in larger ripple current. The core must not saturate with the maximum expected current, here given by:

6) Divider Bypass Capacitor CRR

Since the feedback resistors divide the output voltage by a factor of 4.0, i.e. 5.0 V/1.25 V= 4.0, it follows that the output ripple is also divided by four. This would require that the output ripple be at least 60 mV (4.0 × 15 mV) to trip the feedback comparator. We use a capacitor CRR to act as an AC short so that the output ripple is not attenuated by the divider network. The ripple voltage frequency is equal to the switching frequency so we choose CRR so that:

I ) I IMAX + OUT + 3.0 A ) 0.6 Ań2.0 + 3.3 A 2.0 4) Output Capacitor

The output capacitor limits the output ripple voltage. The CS51033 needs a maximum of 15 mV of output ripple for the feedback comparator to change state. If we assume that all the inductor ripple current flows through the output capacitor and that it is an ideal capacitor (i.e. zero ESR), the minimum capacitance needed to limit the output ripple to 50 mV peak to peak is given by: CO + +

8.0 8.0

I FSW

V

(200

0.6 A 103 Hz)

XC + 1.0 2fC

is negligible at the switching frequency. In this case FSW is 200 kHz if we allow XC = 3.0 Ω then: C + 1.0 ^ 0.265 F 2f3 7) Soft Start and Fault Timing Capacitor CS

(33

10*3 V)

CS performs several important functions. First it provides a dead time for load transients so that the IC does not enter a fault mode every time the load changes abruptly. Secondly it disables the fault circuitry during startup, it also provides Soft Start by clamping the reference voltage during startup to rise slowly and finally it controls the hiccup short circuit protection circuitry. This function reduces the PFET’s duty cycle to 2.0% of the CS period. The most important consideration in calculating CS is that it’s voltage does not reach 2.5 V (the voltage at which the fault detect circuitry is enabled) before VFB reaches 1.15 V otherwise the power supply will never start. If the VFB pin reaches 1.15 V, the fault timing comparator will discharge CS and the supply will not start. For the VFB voltage to reach 1.15 V the output voltage must be at least 4 × 1.15 = 4.6 V. If we choose an arbitrary startup time of 200 µs, we calculate the value of CS from:

^ 11.4 F

The minimum ESR needed to limit the output voltage ripple to 50 mV peak to peak is: *3 ESR + V + 50 10 + 55 m 0.6 A I

The output capacitor should be chosen so that its ESR is at least half of the calculated value and the capacitance is at least ten times the calculated value. It is often advisable to use several capacitors in parallel to reduce ESR. Low impedance aluminum electrolytic, tantalum or organic semiconductor capacitors are a good choice for an output capacitor. Low impedance aluminum are the cheapest but are not available in surface mount at present. Solid tantalum chip capacitors are available from a number of suppliers and offer the best choice for surface mount applications. The capacitor working voltage should be greater than the output voltage in all cases. 5) VFB Divider

ǒ

Ǔ

ǒ

T + CS 2.5 V ICHARGE CS(MIN) +

Ǔ

VOUT + 1.25 V R1 ) R2 + 1.25 V R1 ) 1.0 R2 R2

Use 0.1 µf.

The input bias current to the comparator is 4.0 µA. The resistor divider current should be considerably higher than


200 s 264 A + 0.02 F 2.5 V

CS51033 the VCC and VC pins. This capacitor must also ensure that the VCC remains above the UVLO voltage in the event of an output short circuit. CIN should be a low ESR capacitor of at least 100 µF. A ceramic surface mount capacitor should also be connected between VCC and ground to prevent spikes.

The fault time out time is the sum of the slow discharge time the fast discharge time and the recharge time and is obviously dominated by the slow discharge time. The first parameter is the slow discharge time, it is the time for the CS capacitor to discharge from 2.4 V to 1.5 V and is given by: TSLOWDISCHARGE +

CS

(2.4 V * 1.5 V) IDISCHARGE

9) MOSFET Selection

The CS51033 drives a P–channel MOSFET. The VGATE pin swings from GND to VC. The type of PFET used depends on the operating conditions but for input voltages below 7.0 V a logic level FET should be used. Choose a PFET with a continuous drain current (ID) rating greater than the maximum output current. RDS(ON) should be less than

where IDISCHARGE is 6.0 µA typical. TSLOWDISCHARGE + CS

1.5 V

105

The fast discharge time occurs when a fault is first detected. The CS capacitor is discharged from 2.5 V to 2.4 V. TFASTDISCHARGE +

CS (2.5 V * 2.4 V) IFASTDISCHARGE

RDS t+

where IFASTDISCHARGE is 66 µA typical. TFASTDISCHARGE + CS

The Gate–to–Source voltage VGS and the Drain–to Source Breakdown Voltage should be chosen based on the input supply voltage. The power dissipation due to the conduction losses is given by:

1515

The recharge time is the time for CS to charge from 1.5 V to 2.5 V. TCHARGE +

CS

(2.5 V * 1.5 V) ICHARGE

PD + IOUT2

3787

PD + 0.5

The fault time out time is given by: TFAULT + CS

(3787 ) 1515 ) 1.5

TFAULT + CS

(1.55

10*6

1.55

D

VIN

IOUT

(TRr ) TF)

FSW

where TR = Rise Time and TF = Fall Time.

105)

10) Diode Selection

105)

The flyback or catch diode should be a Schottky diode because of it’s fast switching ability and low forward voltage drop. The current rating must be at least equal to the maximum output current. The breakdown voltage should be at least 20 V for this 12 V application. The diode power dissipation is given by:

For this circuit TFAULT + 0.1

RDS(ON)

The power dissipation due to the switching losses is given by:

where ICHARGE is 264 µA typical. TCHARGE + CS

0.6 V 167 m IOUT(MAX)

105 + 0.0155

A larger value of CS will increase the fault time out time but will also increase the Soft Start time.

PD + IOUT

8) Input Capacitor

The input capacitor reduces the peak currents drawn from the input supply and reduces the noise and ripple voltage on


VD

(1.0 * DMIN)

CS51033 ORDERING INFORMATION Operating Temperature Range

Package

Shipping

CS51033ED8

–40°C < TA < 85°C

SO–8

95 Units/Rail

CS51033EDR8

–40°C < TA < 85°C

SO–8

2500 Tape & Reel

CS51033EN8

–40°C < TA < 85°C

DIP–8

50 Units/Rail

CS51033GD8

0°C < TA < 70°C

SO–8

95 Units/Rail

CS51033GDR8

0°C < TA < 70°C

SO–8

2500 Tape & Reel

CS51033GN8

0°C < TA < 70°C

DIP–8

50 Units/Rail

Device


SO–8

DIP–8

Unit

RΘJC

Typical

45

52

°C/W

RΘJA

Typical

165

100

°C/W


&# ! The CS5211 is a low voltage synchronous buck controller. It contains all required circuitry for a synchronous buck converter using external N–Channel MOSFETs. High current internal gate drivers are capable of driving high gate capacitance of low RDS(on) NFETs for better efficiency. The V2 control architecture is used to achieve unmatched transient response, the best overall regulation and the simplest loop compensation. The CS5211 is in a 14–pin package to allow the designer added flexibility. The CS5211 provides overcurrent protection, undervoltage lockout, Soft Start and built in adaptive nonoverlap. The CS5211 also provides adjustable fixed frequency range of 150 kHz to 750 kHz. This gives the designer more flexibility to make efficiency and component size compromises. The CS5211 will operate over a 4.5 V to 14 V range using either single of dual input voltage. Features

• Switching Regulator Controller – N–Channel Synchronous Buck Design – V2 Control Topology – 200 ns Transient Response – Programmable Fixed Frequency of 150 kHz–750 kHz – 1.0 V 1.5% Internal Reference – Lossless Inductor Sensing Overcurrent Protection – Hiccup Mode Short Circuit Protection – Programmable Soft Start – 40 ns GATE Rise and Fall Times (3.3 nF Load) – 70 ns Adaptive FET Nonoverlap Time – Differential Remote Sense Capability • System Power Management – 5.0 V or 12 V Operation – Undervoltage Lockout – On/Off Control Through Use of the COMP Pin



1581

http://onsemi.com MARKING DIAGRAM 14 SOIC–14 D SUFFIX CASE 751A

CS5211x AWLYWW 1

x A WL, L YY, Y WW, W

= E or G = Assembly Location = Wafer Lot = Year = Work Week

PIN CONNECTIONS 1

GATE(H) BST LGND VFFB VFB COMP SGND

PGND GATE(L) VC IS+ IS– VCC ROSC



CS5211 5.0 V

+

+VOUT

BST

VC

100 µF/10 V × 2

GATE(L)

COMP

PGND

0.1 µF

ROSC IS+

CS5211

0.1 µF

IS– 0.1 µF

+

4.7 k

GATE(H)

VCC

51 k

2.5 V/8.0 A

2.9 µH

0.1 µF

0.1 µF

100 µF/10 V × 3

SGND

VFFB

LGND

VFB

10

–VOUT Return

4.7 k

1.0% SENSE+ 1.5 k 1.0 k 1.0%

10

680 pF SENSE–

Figure 1. Application Diagram, 5.0 V to 2.5 V/8.0 A Converter with Differential Remote Sense MAXIMUM RATINGS* Rating

Value

Unit

150

°C

230 peak

°C

–65 to +150

°C


30 125

°C/W °C/W


2.0

kV

JEDEC Moisture Sensitivity

1.0

–

Operating Junction Temperature, TJ Lead Temperature Soldering:


Storage Temperature Range, TS


MAXIMUM RATINGS Pin Name

Pin Symbol

VMAX

VMIN

ISOURCE

ISINK

IC Power Input

VCC

16 V

–0.3 V

N/A

50 mA DC

Power input for the low side driver

VC

16 V

–0.3 V

N/A

1.5 A Peak, 200 mA DC

Power Supply input for the high side driver

BST

20 V

–0.3 V

N/A


Compensation Capacitor

COMP

6.0 V

–0.3 V

1.0 mA

1.0 mA


VFB

6.0 V

–0.3 V

1.0 mA

1.0 mA

Oscillator Resistor

ROSC

6.0 V

–0.3 V

1.0 mA

1.0 mA


CS5211 MAXIMUM RATINGS (continued) Pin Name

Pin Symbol

VMAX

VMIN

ISOURCE

ISINK

Fast Feedback Input

VFFB

6.0 V

–0.3 V

1.0 mA

1.0 mA

High–Side FET Driver

GATE(H)

20 V

–0.3 V –2.0 V for 50 ns

1.5 A Peak 200 mA DC


Low–Side FET Driver

GATE(L)

16 V

–0.3 V –2.0 V for 50 ns



Positive Current Sense

IS+

6.0 V

–0.3 V

1.0 mA

1.0 mA

Negative Current Sense

IS–

6.0 V

–0.3 V

1.0 mA

1.0 mA

Power Ground

PGND

0.3 V

–0.3 V


N/A

Logic Ground

LGND

0V

0V

100 mA

N/A

Sense Ground

SGND

0.3 V

–0.3 V

1.0 mA

1.0 mA

ELECTRICAL CHARACTERISTICS (–40°C < TA < 85°C; –40°C < TJ < 125°C; 4.5 V < VCC, VC < 14 V; 7.0 V < BST < 20 V; CGATE(H) = CGATE(L) = 3.3 nF; ROSC = 51 k; CCOMP = 0.1 µF, unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit

Error Amplifier VFB Bias Current

VFB = 0 V

–

0.1

1.0

µA

COMP Source Current

VFB = 0.8 V

15

30

60

µA

COMP SINK Current

VFB = 1.2 V

15

30

60

µA

–

98

–

dB

–

50

–

kHz

Open Loop Gain Unity Gain Bandwidth

– C = 0.1 µF

PSRR @ 1.0 kHz

–

–

70

–

dB

Output Transconductance

–

–

32

–

mmho

Output Impedance

–

–

2.5

–

MΩ

0.977

0.992

1.007

V

Reference Voltage

–0.1 V < SGND < 0.1 V, COMP = VFB, Measure VFB to SGND

COMP Max Voltage

VFB = 0.8 V

2.5

3.0

–

V

COMP Min Voltage

VFB = 1.2 V

–

0.1

0.2

V

VC – 0.5 BST – 0.5

–

–

V

GATE(H) and GATE(L) High Voltage (AC)

GATE(L), GATE(H) 0.5 nF < CGATE(H) = CGATE(L) < 10 nF

Low Voltage (AC)

GATE(L) or GATE(H) 0.5 nF < CGATE(H); CGATE(L) < 10 nF

–

–

0.5

V

Rise Time

VC = BST = 10 V, Measure: 1.0 V < GATE(L) < 9.0 V, 1.0 V < GATE(H) < 9.0 V

–

40

80

ns

Fall Time

VC = BST = 10 V, Measure: 1.0 V < GATE(L) < 9.0 V, 1.0 V < GATE(H) < 9.0 V

–

40

80

ns

GATE(H) to GATE(L) Delay

GATE(H) < 2.0 V, GATE(L) > 2.0 V

40

70

110

ns

GATE(L) to GATE(H) Delay

GATE(L) < 2.0 V, GATE(H) > 2.0 V

40

70

110

ns

GATE(H)/(L) Pull–Down

Resistance to PGND

20

50

115

KΩ

2. Guaranteed by design. Not tested in production.


CS5211 ELECTRICAL CHARACTERISTICS (continued) (–40°C < TA < 85°C; –40°C < TJ < 125°C; 4.5 V < VCC, VC < 14 V; 7.0 V < BST < 20 V; CGATE(H) = CGATE(L) = 3.3 nF; ROSC = 51 k; CCOMP = 0.1 µF, unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

54

60

66

mV

Overcurrent Protection OVC Comparator Offset Voltage

0 V < IS+ < VCC, 0 V < IS– < VCC

IS+ Bias Current

0 V < IS+ < VCC

–1.0

0.1

1.0

µA

IS– Bias Current

0 V < IS– < VCC

–1.0

0.1

1.0

µA

0.20

0.25

0.30

V

2.0

5.0

8.0

µA

–

100

200

ns

0.425

0.475

0.525

V

COMP Discharge Threshold COMP Discharge Current in OVC Fault Mode

– COMP = 1.0 V

PWM Comparator Transient Response

COMP = 0 – 1.5 V, VFFB, 20 mV overdrive

PWM Comparator Offset

VFB = VFFB = 0 V; Increase COMP until GATE(H) starts switching

Artificial Ramp

Duty Cycle = 90%

40

70

100

mV

VFFB Bias Current

VFFB = 0 V

–

0.1

1.0

µA

VFFB Input Range

Note 3.

–

–

1.1

V

–

–

200

ns

Minimum Pulse Width

–

Oscillator Switching Frequency

ROSC = 18 k

600

750

900

kHz

Switching Frequency

ROSC = 51 k

240

300

360

kHz

Switching Frequency

ROSC = 96 k

120

150

180

kHz

1.21

1.25

1.29

V

ROSC Voltage

–

General Electrical Specifications VCC Supply Current

COMP = 0 V (no switching)

–

5.0

8.0

mA

BST/VC Supply Current

COMP = 0 V (no switching)

–

2.0

3.0

mA

Start Threshold

GATE(H) Switching, COMP Charging

3.90

4.05

4.20

V

Stop Threshold

GATE(H) Not Switching, COMP Not Charging

3.75

3.90

4.05

V

Hysteresis

Start–Stop

100

150

200

mV

Sense Ground Current

Note 3.

–

0.15

1.00

mA

3. Recommended maximum operating voltage between the three grounds is 200 mV.


CS5211 PACKAGE PIN DESCRIPTION PIN NO.

PIN SYMBOL

FUNCTION

1

GATE(H)

2

BST

3

LGND

Reference ground. All control circuits are referenced to this pin. IC substrate connection.

4

VFFB

Input for the PWM comparator.

5

VFB

Error amplifier input.

6

COMP

Error Amp output. PWM Comparator reference input. A capacitor to LGND provides error amp compensation.

7

SGND

Internal reference is connected to this ground. Connect directly at the load for ground remote sensing.

8

ROSC

A resistor from this pin to SGND sets switching frequency.

9

VCC

Input Power Supply Pin. It supplies power to control circuitry. A 0.1 µF Decoupling cap is recommended.

10

IS–

Negative input for overcurrent comparator.

11

IS+

Positive input for overcurrent comparator.

12

VC

Power supply input for the low side driver.

13

GATE(L)

14

PGND

High Side Switch FET driver pin. Capable of delivering peak currents of 1.0 A. Power supply input for the high side driver.

Low Side Synchronous FET driver pin. Capable of delivering peak currents of 1.0 A. High Current ground for the GATE(H) and GATE(L) pins.

0.5 V

Σ

−

+

Reset Dominant

PWM Comparator

+

VFFB

R

Q

S

Q

−

COMP

ART Ramp

VFB

OSC ROSC

Error Amp

−

PWM FF

+

Fault

1.0 V

BST GATE(H)

VC GATE(L)

− +

SGND −

VSTART

Set Dominant

UVLO

−

+

OC Comparator

S

Q

R

Q

−

0.25 V

+

−

60 mV

+

IS+

LGND

ROSC UVLO Comparator

−

VCC

IS–

PGND

+

+

0.8 V

100 % DC Comparator

5.0 µA

COMP Discharge COMP



Fault

CS5211 THEORY OF OPERATION V2 Control Method

Line and load regulations are drastically improved because there are two independent voltage loops. A voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. The V2 method of control maintains a fixed error signal for both line and load variations, since both line and load affect the ramp signal.

The V2 method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the value of the DC output voltage. This control scheme inherently compensates for variations in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current. PWM Comparator +

GATE(H)

−

GATE(L)

Constant Frequency Operation

Ramp Signal Error Amplifier

+

COMP

Output Voltage Feedback

−

Error Signal

The CS5211 uses a constant frequency, trailing edge modulation architecture for generating PWM signal. During normal operation, the oscillator generates a narrow pulse at the beginning of each switching cycle to turn on the main switch. The main switch will be turned off when the ramp signal intersects with the output of the error amplifier (COMP pin voltage). Therefore, the switch duty cycle can be modified to regulate the output voltage to the desired value as line and load conditions change. The major advantage of constant frequency operation is that the component selections, especially the magnetic component design, become very easy. The oscillator frequency of CS5211 is programmable from 150 kHz to 750 kHz using an external resistor connected from the ROSC pin to ground.

Reference Voltage

Figure 3. V2 Control Block Diagram

V2

The control method is illustrated in Figure 3. The output voltage is used to generate both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of the change. The ramp signal also contains the DC portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. A change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the V2 control scheme to compensate the duty cycle. Since the change in the inductor current modifies the ramp signal, as in current mode control, the V2 control scheme has the same advantages in line transient response. A change in load current will have an effect on the output voltage, altering the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. Load transient response is determined only by the comparator response time and the transition speed of the main switch. The reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. The error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. The main purpose of this “slow” feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered.

Start–Up

If there are no fault conditions and the fault latch is reset, the error amplifier will start charging the COMP pin capacitor after the CS5211 is powered up. The output of the error amplifier (COMP voltage) will ramp up linearly. The COMP capacitance and the source current of the error amplifier determine the slew rate of COMP voltage. The output of the error amplifier is connected internally to the inverting input of the PWM comparator and it is compared with the VFFB pin voltage plus 0.5 V offset at the non–inverting input of the PWM comparator. Since VFFB voltage is zero before the start–up, the PWM comparator output will stay high until the COMP pin voltage hits 0.5 V. There is no switching action while the PWM comparator output is high. After the COMP voltage exceeds the 0.5 V offset, the output of PWM comparator toggles and releases the PWM latch. The narrow pulse generated by the oscillator at the beginning of the next oscillator cycle will set the latch so that the main switch can be turned on and the regulator output voltage ramps up. When the output voltage achieves a level set by the COMP voltage, the main switch will be turned off. The V2 control loop will adjust the main switch duty cycle as required to ensure the regulator output voltage tracks the


CS5211 COMP voltage. Since the COMP voltage increases gradually, the Soft–Start can be achieved. The start–up period ends when the output voltage reaches the level set by the external resistor divider.

If the values of R and C are chosen such that: L + RC RL

Then the voltage across the capacitor C will be: VC + RLIL

Output Enable

Since there can be no switching until the COMP pin exceeds the 0.5 V offset built into the PWM comparator, the COMP pin can also be used for an enable function. Hold the COMP pin below 0.4 V with an open collector circuit to disable the output. When the COMP pin is released to enable start–up, the user must ensure there is no leakage current from the enable circuit into COMP. During normal operation the COMP output is driven with only 5.0 µA to 30 µA internally.

Therefore, if the time constant of the RC network is equal to that of the inductor, the voltage across the capacitor is proportional to the inductor current by a factor of the inductor ESR. In practice, the user should ensure that under all component tolerances, the RC time constant is larger than the L/R time constant. This will keep the high frequency gain for VC(s)/IL(s) less than the low frequency gain, and avoid unnecessary OCP tripping during short duration overcurrent situations. Compared with conventional resistor sensing, the inductor ESR current sensing technique is lossless, but is not as accurate due to variation in the ESR from inductor to inductor and over temperature. For typical inductor ESR, the 0.39%/°C positive temperature coefficient will reduce the current limit at high temperature, and will help prevent thermal runaway, but will force an increased design target at room temperature. This technique can be more accurate than using a PCB trace, since PCB copper thickness can vary 10–20%, compared to 1% variation in wire diameter thickness typical of inductors.

Hiccup Mode Overcurrent Protection

Under normal load conditions, the voltage across the IS+ and IS– pins is less than the 60 mV overcurrent threshold. If the threshold is exceeded, the overcurrent fault latch is set, the high side gate driver is forced low, and the COMP pin is discharged with 5.0 µA. There is no switching until the COMP voltage drops below a 0.25 V threshold. Then, the fault latch is cleared and a soft–start is initiated. The low effective duty cycle during hiccup overcurrent greatly reduces component stress for an extended fault. Inductor Current Sensing

Remote Voltage Sensing

Besides using a current sense resistor to sense inductor current, CS5211 provides the users with the possibility of using loss–less inductor sensing technique. This sensing technique utilizes the Equivalent Series Resistance (ESR) of the inductor to sense the current. The output current is sensed through an RC network in parallel with the inductor as shown in Figure 4. The voltage across the small capacitor is then fed to the OC comparator. IS+ VIN

The CS5211 has the capability to sense the voltage when the load is located far away from the regulator. The SGND pin is dedicated to the differential remote sensing. The negative remote sense line is connected to SGND pin directly, while the positive remote sense line is usually connected to the top of the feedback voltage divider. To prevent over–voltage condition caused by open remote sense lines, the divider should also be locally connected to the output of the regulator through a low value resistor. That resistor is used to compensate for the voltage drop across the output power cables.

IS– C

R

Q1 L

RL

Q2

CO

Figure 4. Inductor Current Sensing


CS5211 APPLICATIONS INFORMATION P + IRMS2

APPLICATIONS AND COMPONENT SELECTION

RL

Inductor Component Selection

Input Capacitor Selection and Considerations

The output inductor may be the most critical component in the converter because it will directly effect the choice of other components and dictate both the steady–state and transient performance of the converter. When selecting an inductor the designer must consider factors such as DC current, peak current, output voltage ripple, core material, magnetic saturation, temperature, physical size, and cost (usually the primary concern). In general, the output inductance value should be as low and physically small as possible to provide the best transient response and minimum cost. If a large inductance value is used, the converter will not respond quickly to rapid changes in the load current. On the other hand, too low an inductance value will result in very large ripple currents in the power components (MOSFETs, capacitors, etc) resulting in increased dissipation and lower converter efficiency. Also, increased ripple currents will force the designer to use higher rated MOSFETs, oversize the thermal solution, and use more, higher rated input and output capacitors – the converter cost will be adversely effected. One method of calculating an output inductor value is to size the inductor to produce a specified maximum ripple current in the inductor. Lower ripple currents will result in less core and MOSFET losses and higher converter efficiency. The following equation may be used to calculate the minimum inductor value to produce a given maximum ripple current (α • IO,MAX). The inductor value calculated by this equation is a minimum because values less than this will produce more ripple current than desired. Conversely, higher inductor values will result in less than the maximum ripple current.

The input capacitor is used to reduce the current surges caused by conduction of current of the top pass transistor charging the PWM inductor. The input current is pulsing at the switching frequency going from 0 to peak current in the inductor. The duty factor will be a function of the ratio of the input to output voltage and of the efficiency. V DF + O VI

1 Eff

The RMS value of the ripple into the input capacitors can now be calculated: IIN(RMS) + IOUT ǸDF * DF2

The input RMS is maximum at 50% DF, so selection of the possible duty factor closest to 50% will give the worst case dissipation in the capacitors. The power dissipation of the input capacitors can be calculated by multiplying the square of the RMS current by the ESR of the capacitor. Output Capacitor

The output capacitor filters output inductor ripple current and provides low impedance for load current changes. The effect of the capacitance for handling the power supply induced ripple will be discussed here. Effects of load transient behavior can be considered separately. The principle consideration for the output capacitor is the ripple current induced by the switches through the inductor. This ripple current was calculated as IAC in the above discussion of the inductor. This ripple component will induce heating in the capacitor by a factor of the RMS current squared multiplied by the ESR of the output capacitor section. It will also create output ripple voltage. The ripple voltage will be a vector summation of the ripple current times the ESR of the capacitor, plus the ripple current integrating in the capacitor, and the rate of change in current times the total series inductance of the capacitor and connections. The inductor ripple current acting against the ESR of the output capacitor is the major contributor to the output ripple voltage. This fact can be used as a criterion to select the output capacitor.

LoMIN + (Vin * Vout) @ Voutń( @ IO,MAX @ Vin @ fSW)

α is the ripple current as a percentage of the maximum output current (α = 0.15 for ±15%, α = 0.25 for ±25%, etc) and fsw is the switching frequency. If the minimum inductor value is used, the inductor current will swing ± α/2% about Iout. Therefore, the inductor must be designed or selected such that it will not saturate with a peak current of (1 + α/2) • IO,MAX. Power dissipation in the inductor can now be calculated from the RMS current level. The RMS of the AC component of the inductor is given by the following relationship:

VPP + IPP

I IAC + PP Ǹ12

CESR

The power dissipation in the output capacitor can be calculated from:

where IPP = α • IO,MAX. The total IRMS of the current will be calculated from:

P + IAC2

CESR

where: IAC = AC RMS of the inductor CESR = Effective series resistance of the output capacitor network.

IRMS + Ǹ IOUT2 ) IAC2

The power dissipation for the inductor can be determined from:


CS5211 MOSFET & Heatsink Selection

may be specified in the data sheet or approximated from the gate–charge curve as shown in the Figure 5.

Power dissipation, package size, and thermal solution drive MOSFET selection. To adequately size the heat sink, the design must first predict the MOSFET power dissipation. Once the dissipation is known, the heat sink thermal impedance can be calculated to prevent the specified maximum case or junction temperatures from being exceeded at the highest ambient temperature. Power dissipation has two primary contributors: conduction losses and switching losses. The control or upper MOSFET will display both switching and conduction losses. The synchronous or lower MOSFET will exhibit only conduction losses because it switches into nearly zero voltage. However, the body diode in the synchronous MOSFET will suffer diode losses during the non–overlap time of the gate drivers. For the upper or control MOSFET, the power dissipation can be approximated from:

Qswitch + Qgs2 ) Qgd

ID

VGATE

VGS_TH

QGS1

QGS2

QGD

VDRAIN

PD,CONTROL + (IRMS,CNTL2 @ RDS(on)) Figure 5. MOSFET Switching Characteristics

) (ILo,MAX @ QswitchńIg @ VIN @ fSW) ) (Qossń2 @ VIN @ fSW) ) (VIN @ QRR @ fSW)

Ig is the output current from the gate driver IC. VIN is the input voltage to the converter. fsw is the switching frequency of the converter. QG is the MOSFET total gate charge to obtain RDS(on). Commonly specified in the data sheet. Vg is the gate drive voltage. QRR is the reverse recovery charge of the lower MOSFET. Qoss is the MOSFET output charge specified in the data sheet. For the lower or synchronous MOSFET, the power dissipation can be approximated from:

The first term represents the conduction or IR losses when the MOSFET is ON while the second term represents the switching losses. The third term is the losses associated with the control and synchronous MOSFET output charge when the control MOSFET turns ON. The output losses are caused by both the control and synchronous MOSFET but are dissipated only in the control FET. The fourth term is the loss due to the reverse recovery time of the body diode in the synchronous MOSFET. The first two terms are usually adequate to predict the majority of the losses. Where IRMS,CNTL is the RMS value of the trapezoidal current in the control MOSFET:

PD,SYNCH + (IRMS,SYNCH2 @ RDS(on)) ) (Vfdiode @ IO,MAXń2 @ t_nonoverlap @ fSW)

IRMS,CNTL + ǸD @ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN

The first term represents the conduction or IR losses when the MOSFET is ON and the second term represents the diode losses that occur during the gate non–overlap time. All terms were defined in the previous discussion for the control MOSFET with the exception of:

) ILo,MIN2)ń3]1ń2

ILo,MAX is the maximum output inductor current: ILo,MAX + IO,MAXń2 ) ILoń2

IRMS,SYNCH + Ǹ1 * D @ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2)ń3]1ń2

ILo,MIN is the minimum output inductor current: ILo,MIN + IO,MAXń2 * ILoń2

IO,MAX is the maximum converter output current. D is the duty cycle of the converter:

where: Vfdiode is the forward voltage of the MOSFET’s intrinsic diode at the converter output current. t_nonoverlap is the non–overlap time between the upper and lower gate drivers to prevent cross conduction. This time is usually specified in the data sheet for the control IC. When the MOSFET power dissipations are known, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case ambient operating temperature

D + VOUTńVIN

∆ILo is the peak–to–peak ripple current in the output inductor of value Lo: ILo + (VIN * VOUT) @ Dń(Lo @ fSW)

RDS(on) is the ON resistance of the MOSFET at the applied gate drive voltage. Qswitch is the post gate threshold portion of the gate–to–source charge plus the gate–to–drain charge. This


CS5211 T t (TJ * TA)ńPD

The COMP output current range is given in the data sheet and will affect the ramp–up time. The value of the capacitor on the COMP pin will have an effect on the loop response and the transient response of the converter. Transient response can be enhanced by the addition of a parallel combination of a resistor and capacitor between the COMP pin and the comp capacitor.

where; θT is the total thermal impedance (θJC + θSA). θJC is the junction–to–case thermal impedance of the MOSFET. θSA is the sink–to–ambient thermal impedance of the heatsink assuming direct mounting of the MOSFET (no thermal “pad” is used). TJ is the specified maximum allowed junction temperature. TA is the worst case ambient operating temperature. For TO–220 and TO–263 packages, standard FR–4 copper clad circuit boards will have approximate thermal resistances (θSA) as shown below: Single–Sided 1 oz. Copper

0.5/323

60–65°C/W

0.75/484

55–60°C/W

1.0/645

50–55°C/W

1.5/968

45–50°C/W

2.0/1290

38–42°C/W

2.5/1612

33–37°C/W

The switching frequency is programmed by selecting the resistor connected between the ROSC pin and SGND (pin 7). The grounded side of this resistor should be directly connected to the SGND pin, without any other currents flowing between the bottom of the resistor and the pin. Also, avoid running any noisy signals under the resistor, since injected noise could cause frequency jitter. The graph in Figure 6 shows the required resistance to program the frequency. Below 500 kHz, the following formula is accurate: R + 13500ńfSW ) 6 k

where fSW is the switching frequency in kHz. 800 700 Frequency (kHz)

Pad Size (in2/mm2)

ROSC Selection

As with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. Variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e. worst case MOSFET RDS(on)). Also, the inductors and capacitors share the MOSFET’s heatsinks and will add heat and raise the temperature of the circuit board and MOSFET. For any new design, its advisable to have as much heatsink area as possible – all too often new designs are found to be too hot and require re–design to add heatsinking.

500 400 300 200 100 0 10

20

30

40

50 60 70 80 Resistance (kΩ)

90

100 110

Figure 6. Frequency vs. ROSC Differential Remote Sense Operation

Compensation Capacitor Selection

The ability to implement fully differential remote sense is provided by the CS5211. The positive remote sense is implemented by bringing the output remote sense connection to the positive load connection. A low value resistor is connected from Vout to the feedback point at the regulator to provide feedback in the instance when the remote sense point is not connected. The negative remote sense connection is provided by connecting the SGND of the CS5211 to the negative of the load return. Again, a low value resistor should be connected between SGND and LGND at the regulator to provide feedback in the instance when the remote sense point is not connected. The maximum voltage differential between the three grounds for this part is 200 mV.

The nominal output current capability of the error amp is 30 µA. This current charging the capacitor on the COMP pin is used as soft start for the converter. The COMP pin is going to ramp up to a voltage level that is within 70 mV of what VFFB is going to be when in regulation. This is the voltage that will determine the soft start. Therefore, the COMP capacitor can be established by the following relationship: C + 30 A

600

soft start VFFB(REG)

where: soft start = output ramp–up time VFFB(REG) = VFFB voltage when in regulation 30 µA = COMP output current, typ.


CS5211 Feedback Divider Selection

Maximum Frequency Operation

The feedback voltage measured at VFB during normal regulation will be 1.0 V. This voltage is compared to an internal 1.0 V reference and is used to regulate the output voltage. The bias current into the error amplifier is 1.0 µA max, so select the resistor values so that this current does not add an excessive offset voltage.

The minimum pulse width may limit the maximum operating frequency. The duty factor, given by the output/input voltage ratio, multiplied by the period determines the pulse width during normal operation. This pulse width must be greater than 200 ns, or duty cycle jitter could become excessive. For low pulse widths below 300 ns, external slope compensation should be added to the VFFB pin to increase the PWM ramp signal and improve stability. 50 mV of added ramp at the VFFB pin is typically enough.

VFFB Feedback Selection

To take full advantage of the V2 control scheme, a small amount of output ripple must be fed back to the VFFB pin, typically 50 mV. For most application, this requirement is simple to achieve and the VFFB can be connected directly to the VFB pin. There are some application that have to meet stringent load transient requirements. One of the key factor in achieving tight dynamic voltage regulation is low ESR. Low ESR at the regulator output results in low output voltage ripple. This situation could result in increase noise sensitivity and a potential for loop instability. In applications where the output ripple is not sufficient, the performance of the CS5211 can be improved by adding a fixed amount external ramp compensation to the VFFB pin. Refer to Figure 7, the amount of ramp at the VFFB pin depends on the switch node Voltage, Feedback Voltage, R1 and C2. Vramp + (Vsw * VFB)

tonń(R1

Current Sense Component Selection

The current limit threshold is set by sensing a 60 mV voltage differential between the IS+ and IS– pins. Referring to Figure 8, the time constant of the R2,C1 filter should be set larger than the L/R1 time constant under worst case tolerances, to prevent overshoot in the sensed voltage and tripping the current limit too low. Resistor R3 of value equal to R2 is added for bias current cancellation. R2 and R3 should not be made too large, to reduce errors from bias current offsets. For typical L/R time constants, a 0.1 µF capacitor for C1 will allow R2 to be between 1.0 k and 10 kΩ. The current limit without R4 and R5, which are optional, is given by 60 mV/R1, where R1 is the internal resistance of the inductor, obtained from the manufacturer. The addition of R5 can be used to decrease the current limit to a value given by:

C2)

where: Vramp = amount of ramp needed; Vsw = switch note voltage; VFB = voltage feedback, 1 V; ton = switch on–time. To minimize the lost in efficiency R1 resistance should be large, typically 100 k or larger. With R1 chosen, C2 can be determined by the following; C2 + (Vsw * VFB)

tonń(R1

ILIM + (60 mV * (VOUT

R3ń(R3 ) R5))ńR1

where VOUT is the output voltage. Similiarly, omitting R5 and adding R4 will increase the current limit to a value given by: ILIM + 60 mVńR1

(1 ) R2ńR4)

Essentially, R4 or R5 are used to increase or decrease the inductor voltage drop which corresponds to 60 mV at the IS+ and IS– pins.

Vramp)

C1 is used as a bypass capacitor and its value should be equal to or greater than C2.

IS– Vsw

R3 R5 60 mV Trip

R1 IS+

C1 VFFB C2

R2

R2 1.0 k

C1 R4

Switching Node

VFB

VOUT L1

Figure 7. Small RC Filter Providing the Proper Voltage Ramp at the Beginning of Each On–Time Cycle

R1 L



CS5211 Boost Component Selection for Upper FET Gate Drive

the summation of the voltage from the charging diode and the output voltage swing. Care must be taken to keep the peak voltage with respect to ground less than 20 V peak. The capacitor should be large enough to drive the capacitance of the top FET.

The boost (BST) pin provides for application of a higher voltage to drive the upper FET. This voltage may be provided by a fixed higher voltage or it may be generated with a boost capacitor and charging diode, as shown in Figure 10. The voltage in the boost configuration would be

12 V

12 V

33 +

33 µF/25 V × 3

0.1 µF 18 V

2.9 µH BST

VC

0.1 µF 4.7 k

GATE(H)

VCC

5.0 V/8.0 A

PGND

0.1 µF

ROSC 51 k 0.1 µF

100 µF/10 V × 2

GATE(L)

COMP 0.1 µF

+

CS5211

10

IS+

4.7 k

IS– SGND LGND

SENSE+

VFFB

4.02 k 1.0%

VFB 1.0 k 1.0%

SENSE–

10

Figure 9. Additional Application Diagram, 12 V to 5.0 V/8.0 A Converter with Differential Remote Sense


CS5211 12 V

5.0 V

+

33 µF/25 V × 3

2.9 µH

0.22 µF

3.3 V/8.0 A

BST

VC

4.7 k

GATE(H)

VCC COMP

51 k 0.1 µF

100 µF/10 V × 2

GATE(L) PGND

0.1 µF

ROSC 0.1 µF

+

CS5211

10

IS+

4.7 k

IS– SGND LGND

SENSE+

VFFB

2.32 k 1.0%

VFB 1.0 k 1.0%

SENSE–

10

Figure 10. Additional Application Diagram, 12 V to 5.0 V Bias to 3.3 V/8.0 A Converter with Differential Remote Sense


CS5211 ORDERING INFORMATION Device


CS5211ED14 CS5211EDR14

–40°C 40°C < TA < 85°C

CS5211GD14 CS5211GDR14

0°C < TA < 70°C


Package

Shipping

SO–14

55 Units/Rail

SO–14

2500 Tape & Reel

SO–14

55 Units/Rail

SO–14

2500 Tape & Reel

28* &# ! The NCP1570 is a low voltage buck controller. It provides the control for a DC–DC power solution producing an output voltage as low as 0.985 V over a wide current range. The NCP1570–based solution is powered from 12 V with the output derived from a 5 V supply. It contains all required circuitry for a synchronous NFET buck regulator using the V2 control method to achieve the fastest possible transient response and best overall regulation. The NCP1570 operates at a fixed internal 200 kHz frequency and is packaged in an SO–8. The NCP1570 provides undervoltage lockout protection, Soft Start, Power Good with delay, and built–in adaptive non–overlap. Features • 0.985 V ± 1.0% Reference • V2 Control Topology • 200 ns Transient Response • Programmable Soft Start • Power Good • Programmable Power Good Delay • 40 ns Gate Rise and Fall Times (3.3 nF Load) • 50 ns Adaptive FET Non–Overlap Time • Fixed 200 kHz Oscillator Frequency • Undervoltage Lockout • On/Off Control Through Use of the COMP Pin • Overvoltage Protection through Synchronous MOSFETs • Synchronous N–Channel Buck Design • Dual Supply, 12 V Control, 5 V Power Source


8 1 SO–8 D SUFFIX CASE 751

PIN CONNECTIONS AND MARKING DIAGRAM VCC PWRGD PGDELAY COMP A WL, L YY, Y WW, W

1

8 1570 ALYWX


http://onsemi.com

GND VFB GATE(L) GATE(H)



1595

Package

Shipping

NCP1570D

SO–8

95 Units/Rail

NCP1570DR2

SO–8

2500 Tape & Reel

Publication Order Number NCP1570/D

NCP1570 12 V PWRGD VLOGIC

GND

5.0 V 33 µF/8.0 V/1.6 Arms × 4

R1 50 k

C1 C4

1.2 µH GND

PWRGD NCP1570

C12 0.01 µF

C2

+

C3

NTD4302 Q1

0.1 µF VCC

+

+

PGDELAY

GATE(L)

COMP

GATE(H)

L1

100 pF C6

VFB

1.2 V

1.2 V/10 A +

2.0 k R3

NTD4302 Q2

+

C8

+

C9

+

C10

C11 GND

56 µF/4.0 V/1.6 Arms SP–CAP 40 mΩ

R5 10 k

C13 0.1 µF

Figure 1. Applications Circuit MAXIMUM RATINGS* Rating

Value

Unit

150

°C

–65 to 150

°C


2.0

kV


200

V

230 peak

°C

2

–

48 165

°C/W °C/W

Operating Junction Temperature Storage Temperature Range


Reflow: (Note 1)

Moisture Sensitivity Level Package Thermal Resistance, SO–8 Junction–to–Case, RθJC Junction–to–Ambient, RθJA 1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed.


Pin Symbol

VMAX

VMIN

ISOURCE

ISINK

IC Power Input

VCC

15 V

–0.5 V

N/A



COMP

6.0 V

–0.5 V

10 mA

10 mA


VFB

6.0 V

–0.5 V

1.0 mA

1.0 mA

Power Good Output

PWRGD

15 V

–0.5 V

1.0 mA

20 mA

Power Good Delay

PGDELAY

6.0 V

–0.5 V

1.0 mA

10 mA


GATE(H)

15 V

–0.5 V –2.0 V for 50 ns




GATE(L)

15 V

–0.5 V –2.0 V for 50 ns



Ground

GND

0.5 V

–0.5 V


N/A


NCP1570 ELECTRICAL CHARACTERISTICS (0°C < TJ < 125°C, 11.4 V < VCC < 12.6 V, CGATE(H) = CGATE(L) = 3.3 nF, CPGDELAY = 0.01 µF, CCOMP = 0.1 µF; unless otherwise specified.)

Test Conditions

Characteristic

Min

Typ

Max

Unit


VFB = 0 V

–

0.2

2.0

µA

COMP Source Current

COMP = 1.5 V, VFB = 0.8 V

15

30

60

µA

COMP Sink Current

COMP = 1.5 V, VFB = 1.2 V

15

30

60

µA

Reference Voltage

COMP = VFB

0.975

0.985

0.995

V

COMP Max Voltage

VFB = 0.8

2.4

2.7

–

V

COMP Min Voltage

VFB = 1.2

–

0.1

0.2

V

COMP Fault Discharge Current at UVLO

COMP = 1.2 V, VCC = 6.9 V

0.5

1.7

–

mA

COMP Fault Discharge Threshold to Reset UVLO

COMP = 0.5 V, VCC = 12 V – 6.9 V – 12 V. Ramp COMP to 0.1 V. Monitor I (COMP)

0.1

0.25

0.3

V

Open Loop Gain

–

–

98

–

dB


–

–

20

–

kHz

PSRR @ 1.0 kHz

–

–

70

–

dB


–

–

32

–

mmho

Output Impedance

–

–

2.5

–

MΩ

GATE(H) and GATE(L) Rise Time

1.0 V < GATE(L) & GATE(H) < VCC – 2.0

–

40

80

ns

Fall Time

VCC – 2.0 < GATE(L) & GATE(H) < 1.0 V

–

40

80

ns


GATE(H) < 2.0 V, GATE(L) > 2.0 V

25

50

75

ns


GATE(L) < 2.0 V, GATE(H) > 2.0 V

25

50

75

ns

Minimum Pulse Width

GATE(X) = 4.0 V

–

250

–

ns

High Voltage (AC)

Measure GATE(L) or GATE(H) 0.5 nF < CGATE(H) = CGATE(L) < 10 nF Note 2

VCC – 0.5

VCC

–

V

Low Voltage (AC)

Measure GATE(L) or GATE(H) 0.5 nF < CGATE(H) = CGATE(L) < 10 nF Note 2

–

0

0.5

V


Resistance to GND. Note 2

20

50

115

kΩ

Power Good Lower Threshold, VO Rising

–

0.856

0.887

0.917

V

Lower Threshold, VO Falling

–

0.666

0.690

0.713

V

–

0.15

0.4

V

7.0

12

18

µA

3.45

4.0

4.3

V

PWRGD Low Voltage

ISINK = 1.0 mA, VFB = 0


PGDELAY = 2.0 V

Delay Clamp Voltage

–

Delay Charge Threshold

Ramp PGDELAY, Monitor PWRGD

3.1

3.3

3.5

V

Delay Discharge Current at UVLO

PGDELAY = 0.5 V, VCC = 6.9 V

0.5

2.0

–

mA

Delay Discharge Threshold to Reset UVLO

PGDELAY = 0.5 V, VCC = 12 V to 6.9 to 12 V, Ramp PGDELAY to 0.1 V, Monitor I (PGDELAY)

0.1

0.25

0.3

V

“Good” Signal Delay

With 0.01 µF. Note 2

1.0

3.0

5.0

ms



NCP1570 ELECTRICAL CHARACTERISTICS (continued) (0°C < TJ < 125°C, 11.4 V < VCC < 12.6 V, CGATE(H) = CGATE(L) = 3.3 nF, CPGDELAY = 0.01 µF, CCOMP = 0.1 µF; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

0.475

0.525

0.575

V

–

80

–

%

PWM Comparator PWM Comparator Offset

VFB = 0 V, Increase COMP Until GATE(H) Starts Switching

Ramp Max Duty Cycle

–

Artificial Ramp

Duty Cycle = 50%

18

25

35

mV

Transient Response

COMP = 1.5 V, VFB 20 mV Overdrive. Note 3

–

200

300

ns

VFB Input Range

Note 3

0

–

1.4

V

150

200

250

kHz

–

10

15

mA

Oscillator –

Switching Frequency General Electrical Specifications VCC Supply Current

COMP = 0 V (No Switching)

Start Threshold


8.0

8.5

9.0

V

Stop Threshold

GATE(H) Not Switching, COMP Discharging

7.0

7.5

8.0

V

Hysteresis

Start – Stop

0.75

1.0

1.25

V



PIN SYMBOL

1

VCC

2

PWRGD

Open collector output goes low when VFB is out of regulation. User must externally limit current into this pin to less than 20 mA.

3

PGDELAY

External capacitor programs PWRGD low–to–high transition delay.

4

COMP

Error amp output. PWM comparator reference input. A capacitor to LGND provides error amp compensation and Soft Start. Pulling pin < 0.45 locks gate outputs to a zero percent duty cycle state.

5

GATE(H)

High–side switch FET driver pin. Capable of delivering peak currents of 1.5 A.

6

GATE(L)

Low–side synchronous FET driver pin. Capable of delivering peak currents of 1.5 A.

7

VFB

Error amplifier and PWM comparator input.

8

GND

Power supply return.

FUNCTION Power supply input.


NCP1570

VCC

Fault Latch

UVLO COMP

–

S

Q

+ + –

– 8.5 V/7.5 V + + –

R Set Dominant

0.25 V

GND VCC

–

VFB

Error Amp

PWM COMP

+

PWM Latch

+

R

GATE(H)

Q

– + –

Non Overlap

0.985 V S Reset Dominant

GATE(L)

COMP 0.525 V Σ

– +

OSC

Art Ramp 80%, 200 kHz

+

0.25 V

12 µA

–

+ –

PGDELAY –

PGDELAY Latch S

–

Q

+

+ + –

+ –

0.89 V/0.69 V R Set Dominant



3.3 V

PWRGD

NCP1570 TYPICAL PERFORMANCE CHARACTERISTICS 11

205 204


ICC (mA)

10

9

8

7

203 202 201 200 199

6

0

20


100

198

120

Figure 3. Supply Current vs. Temperature

Ramp Amplitude (mV)

VREF (mV) 984

0

20


100

100

120

25

24

23

22

120


0

20


100

120

Figure 6. Artificial Ramp Amplitude vs. Temperature (50% Duty Cycle)

520

8.4 Start/Stop Threshold Voltages (V)

PWM Offset Voltage (mV)


26

986

516

512

508

504

20


988

982

0

0

20


100

120

Figure 7. PWM Offset Voltage vs. Temperature

8.2 Turn–On Threshold

8.0 7.8 7.6

Turn–Off Threshold

7.4 7.2 7.0

0

20


100

Figure 8. Undervoltage Lockout Thresholds vs. Temperature


120

NCP1570 TYPICAL PERFORMANCE CHARACTERISTICS 34 Error Amp Source/Sink Currents (µA)

0.55

VFB Bias Current (µA)

0.50 0.45 0.40 0.35 0.30 0.25 0.20

0

20


100

3.0

29

0

20


100

120

1.30 Discharge Current (mA)

COMP Minimum Voltage (mV)

Sink Current

30

1.34

COMP Maximum Voltage

2.5 2.0 1.5

COMP Fault Threshold Voltage

1.0

COMP Minimum Voltage

0

20


100

1.26 1.22 1.18 1.14

0.5 120

Figure 11. COMP Voltages vs. Temperature

1.10

0

20


100

120

Figure 12. COMP Fault Mode Discharge Current vs. Temperature

55

38 GATEH Fall Time

36

GATEH Rise Time

Gate Non–Overlap Time (ns)

GATE Rise/Fall Times (ns)

31

Figure 10. Error Amp Output Currents vs. Temperature

3.5

0

Source Current

32

28

120

Figure 9. VFB Bias Current vs. Temperature

33

34 32 30 28 GATEL Rise Time 26

GATEL Fall Time

24

50 GATEH to GATEL Delay Time 45 GATEL to GATEH Delay Time

40

35

22 20

0

20


100

120

Figure 13. GATE Output Rise and Fall Times vs. Temperature

30

0

20


100

120

Figure 14. GATE Non–Overlap Times vs. Temperature


NCP1570 TYPICAL PERFORMANCE CHARACTERISTICS 70 Turn–On Threshold, VFB Rising

900

PGOOD Low Voltage (mV)

Power Good Threshold Voltage (mV)

1000

800

700 Turn–Off Threshold, VFB Falling 600

0

20


100

65 60 55 50 45 40

120

11.9

1.65

11.8

1.60

11.7 11.6 11.5 11.4 11.3


100

120

1.55 1.50 1.45 1.40

0

20


100

1.35

120

Figure 17. PGOOD Delay Charge Current vs. Temperature

0

20


100

120

Figure 18. PGDELAY Discharge Current vs. Temperature

263

4.00 3.90 PGDELAY Voltages (V)

Discharge Threshold Voltage (mV)

20

Figure 16. PGOOD Output Low Voltage vs. Temperature

Discharge Current (mA)

GOOD Delay Charge Current (µA)

Figure 15. Power Good Thresholds vs. Temperature

0

262

261

260

PGDELAY Max Voltage

3.80 3.70 3.60 3.50 3.40

PGDELAY Upper Threshold Voltage

3.30 259

0

20


100

120

Figure 19. Power Good Discharge Threshold Voltage vs. Temperature

3.20

0

20


100

Figure 20. PGDELAY Voltages vs. Temperature


120

NCP1570 APPLICATION INFORMATION THEORY OF OPERATION

time to the output load step is not related to the crossover frequency of the error signal loop. The error signal loop can have a low crossover frequency, since the transient response is handled by the ramp signal loop. The main purpose of this ‘slow’ feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. Line and load regulation are drastically improved because there are two independent control loops. A voltage mode controller relies on the change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains a fixed error signal during line transients, since the slope of the ramp signal changes in this case. However, regulation of load transients still requires a change in the error signal. The V2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load. The stringent load transient requirements of modern microprocessors require the output capacitors to have very low ESR. The resulting shallow slope in the output ripple can lead to pulse width jitter and variation caused by both random and synchronous noise. A ramp waveform generated in the oscillator is added to the ramp signal from the output voltage to provide the proper voltage ramp at the beginning of each switching cycle. This slope compensation increases the noise immunity, particularly at duty cycles above 50%.

The NCP1570 is a simple, synchronous, fixed–frequency, low–voltage buck controller using the V2 control method. It provides a programmable–delay Power Good function to indicate when the output voltage is out of regulation. V2 Control Method

The V2 control method uses a ramp signal generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. The V2 method differs from traditional techniques such as voltage mode control, which generates an artificial ramp, and current mode control, which generates a ramp using the inductor current.

–

GATE(H)

PWM +

GATE(L)

RAMP

Slope Compensation

Output Voltage Error Amplifier

VFB

–

COMP

Error Signal

+

Reference Voltage

Figure 21. V2 Control with Slope Compensation

Start Up

The V2 control method is illustrated in Figure 21. The output voltage generates both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output, regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, allowing the control circuit to drive the main switch to 0% or 100% duty cycle as required. A variation in line voltage changes the current ramp in the inductor, which causes the V2 control scheme to compensate the duty cycle. Since any variation in inductor current modifies the ramp signal, as in current mode control, the V2 control scheme offers the same advantages in line transient response. A variation in load current will affect the output voltage, modifying the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. The comparator response time and the transition speed of the main switch determine the load transient response. Unlike traditional control methods, the reaction

The NCP1570 features a programmable Soft Start function, which is implemented through the error amplifier and the external compensation capacitor. This feature prevents stress to the power components and limits output voltage overshoot during start–up. As power is applied to the regulator, the NCP1570 undervoltage lockout circuit (UVL) monitors the IC’s supply voltage (VCC). The UVL circuit prevents the MOSFET gates from switching until VCC exceeds the 8.5 V threshold. A hysteresis function of 1.0 V improves noise immunity. The compensation capacitor connected to the COMP pin is charged by a 30 µA current source. When the capacitor voltage exceeds the 0.5 V offset of the PWM comparator, the PWM control loop will allow switching to occur. The upper gate driver GATE(H) is activated turning on the upper MOSFET. The current then ramps up through the main inductor and linearly powers the output capacitors and load. When the regulator output voltage exceeds the COMP pin voltage minus the 0.5 V


NCP1570 low at 70% of the designed output voltage. PWRGD is an open–collector output and should be externally pulled to logic high through a resistor to limit current to no more than 20mA. Figure 23 shows the hysteretic nature of the PWRGD pin’s operation.

PWM comparator offset threshold and the artificial ramp, the PWM comparator terminates the initial pulse. VIN

8.5 V

VCOMP

PWRGD

0.5 V

High

VFB

GATE(H)

Low UVLO

STARTUP

tS

NORMAL OPERATION

VOUT

Figure 22. Idealized Waveforms

70% 90% Percent of Designed VOUT

Normal Operation

During normal operation, the duty cycle of the gate drivers remains approximately constant as the V2 control loop maintains the regulated output voltage under steady state conditions. Variations in supply line or output load conditions will result in changes in duty cycle to maintain regulation.

Figure 23. PWRGD Assertion Selection of the Output Capacitors

These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to provide acceptable ripple on the regulator output voltage. Key specifications for output capacitors are their ESR (Equivalent Series Resistance), and ESL (Equivalent Series Inductance). For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. In order to determine the number of output capacitors the maximum voltage transient allowed during load transitions has to be specified. The output capacitors must hold the output voltage within these limits since the inductor current can not change with the required slew rate. The output capacitors must therefore have a very low ESL and ESR. The voltage change during the load current transient is:

Gate Charge Effect on Switching Times

When using the onboard gate drivers, the gate charge has an important effect on the switching times of the FETs. A finite amount of time is required to charge the effective capacitor seen at the gate of the FET. Therefore, the rise and fall times rise linearly with increased capacitive loading. Transient Response

The 200 ns reaction time of the control loop provides fast transient response to any variations in input voltage and output current. Pulse–by–pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitors during the time required to slew the inductor current. For better transient response, several high frequency and bulk output capacitors are usually used.

VOUT + IOUT

t ǒESL ) ESR ) TR Ǔ t COUT

where: ∆IOUT / ∆t = load current slew rate; ∆IOUT = load transient; ∆t = load transient duration time; ESL = Maximum allowable ESL including capacitors, circuit traces, and vias; ESR = Maximum allowable ESR including capacitors and circuit traces; tTR = output voltage transient response time. The designer has to independently assign values for the change in output voltage due to ESR, ESL, and output capacitor discharging or charging. Empirical data indicates that most of the output voltage change (droop or spike depending on the load current transition) results from the total output capacitor ESR. The maximum allowable ESR can then be determined according to the formula:


Overvoltage protection is provided as a result of the normal operation of the V2 control method and requires no additional external components. The control loop responds to an overvoltage condition within 200 ns, turning off the upper MOSFET and disconnecting the regulator from its input voltage. This results in a crowbar action to clamp the output voltage, preventing damage to the load. The regulator remains in this state until the overvoltage condition ceases. Power Good

The PWRGD pin is asserted when the output voltage is within regulation limits. Sensing for the PWRGD pin is achieved through the VFB pin. When the output voltage is rising, PWRGD goes high at 90% of the designed output voltage. When the output voltage is falling, PWRGD goes


NCP1570 ESRMAX +

VESR IOUT

fC +

where: ∆VESR = change in output voltage due to ESR (assigned by the designer) Once the maximum allowable ESR is determined, the number of output capacitors can be found by using the formula: Number of capacitors +

Selection of the Output Inductor

There are many factors to consider when choosing the output inductor. Maximum load current, core and winding losses, ripple current, short circuit current, saturation characteristics, component height and cost are all variables that the designer should consider. However, the most important consideration may be the effect inductor value has on transient response. The amount of overshoot or undershoot exhibited during a current transient is defined as the product of the current step and the output filter capacitor ESR. Choosing the inductor value appropriately can minimize the amount of energy that must be transferred from the inductor to the capacitor or vice–versa. In the subsequent paragraphs, we will determine the minimum value of inductance required for our system and consider the trade–off of ripple current vs. transient response. In order to choose the minimum value of inductance, input voltage, output voltage and output current must be known. Most computer applications use reasonably well regulated bulk power supplies so that, while the equations below specify VIN(MAX) or VIN(MIN), it is possible to use the nominal value of VIN in these calculations with little error. Current in the inductor while operating in the continuous current mode is defined as the load current plus ripple current.

ESRCAP ESRMAX

ESRMAX

Similarly, the maximum allowable ESL is calculated from the following formula: ESLMAX +

VESL I

ǸLC

where: L = input inductor; C = input capacitor(s).

where: ESRCAP = maximum ESR per capacitor (specified in manufacturer’s data sheet). ESRMAX = maximum allowable ESR. The actual output voltage deviation due to ESR can then be verified and compared to the value assigned by the designer: VESR + IOUT

1 2

t

Selection of the Input Inductor

A common requirement is that the buck controller must not disturb the input voltage. One method of achieving this is by using an input inductor and a bypass capacitor. The input inductor isolates the supply from the noise generated in the switching portion of the buck regulator and also limits the inrush current into the input capacitors upon power up. The inductor’s limiting effect on the input current slew rate becomes increasingly beneficial during load transients. The worst case is when the load changes from no load to full load (load step), a condition under which the highest voltage change across the input capacitors is also seen by the input inductor. The inductor successfully blocks the ripple current while placing the transient current requirements on the input bypass capacitor bank, which has to initially support the sudden load change. The minimum inductance value for the input inductor is therefore:

IL + ILOAD ) IRIPPLE

The ripple current waveform is triangular, and the current is a function of voltage across the inductor, switch FET on–time and the inductor value. FET on–time can be defined as the product of duty cycle and switch frequency, and duty cycle can be defined as a ratio of VOUT to VIN. Thus, IRIPPLE +

(VIN * VOUT)VOUT (fOSC)(L)(VIN)

Peak inductor current is defined as the load current plus half of the peak current. Peak current must be less than the maximum rated FET switch current, and must also be less than the inductor saturation current. Thus, the maximum output current can be defined as:

V LIN + (dIńdt)MAX

where: LIN = input inductor value; ∆V = voltage seen by the input inductor during a full load swing; (dI/dt)MAX = maximum allowable input current slew rate. The designer must select the LC filter pole frequency so that at least 40 dB attenuation is obtained at the regulator switching frequency. The LC filter is a double–pole network with a slope of –2.0, a roll–off rate of –40 dB/dec, and a corner frequency:

IOUT(MAX) + ISWITCH(MAX) *

ǒVIN(MAX) * VOUTǓVOUT ǒ2ǓǒfOSCǓǒLǓǒVIN(MAX)Ǔ

Since the maximum output current must be less than the maximum switch current, the minimum inductance required can be determined. (VIN(MIN) * VOUT)VOUT L(MIN) + (fOSC)(ISWITCH(MAX))(VIN(MIN))


NCP1570 LIN

This equation identifies the value of inductor that will provide the full rated switch current as inductor ripple current, and will usually result in inefficient system operation. The system will sink current away from the load during some portion of the duty cycle unless load current is greater than half of the rated switch current. Some value larger than the minimum inductance must be used to ensure the converter does not sink current. Choosing larger values of inductor will reduce the ripple current, and inductor value can be designed to accommodate a particular value of ripple current by replacing ISWITCH(MAX) with a desired value of IRIPPLE:

COUT

CONTROL INPUT

Figure 24.

Consider the schematic shown in Figure 24. The average current flowing in the input inductor LIN for any given output current is: IIN(AVE) + IOUT

VOUT VIN

Input capacitor current is positive into the capacitor when the switch FETs are off, and negative out of the capacitor when the switch FETs are on. When the switches are off, IIN(AVE) flows into the capacitor. When the switches are on, capacitor current is equal to the per–phase output current minus IIN(AVE). If we ignore the small current variation due to the output ripple current, we can approximate the input capacitor current waveform as a square wave. We can then calculate the RMS input capacitor ripple current:

(L)(IOUT) (VIN * VOUT) (L)(IOUT) (VOUT)

Ǹ

Inductor value selection also depends on how much output ripple voltage the system can tolerate. Output ripple voltage is defined as the product of the output ripple current and the output filter capacitor ESR. Thus, output ripple voltage can be calculated as: VRIPPLE + ǒESRCǓǒIRIPPLEǓ +

CIN

IRMS(CIN)

However, reducing the ripple current will cause transient response times to increase. The response times for both increasing and decreasing current steps are shown below.

TRESPONSE(DECREASING) +

VOUT IIN(AVE)

(VIN(MIN) * VOUT)VOUT L(RIPPLE) + (fOSC)(IRIPPLE)(VIN(MIN))

TRESPONSE(INCREASING) +

LOUT

VIN

V I 2IN(AVE) ) OUT VIN ǒIOUT per phase * IIN(AVE)Ǔ2 * I 2 IN(AVE)

IRMS(CIN) +

ƪ

ƫ

The input capacitance must be designed to conduct the worst case input ripple current. This will require several capacitors in parallel. In addition to the worst case current, attention must be paid to the capacitor manufacturer’s derating for operation over temperature. As an example, let us define the input capacitance for a 5 V to 3.3 V conversion at 10 A at an ambient temperature of 60°C. A droop voltage of 90 mV to 1.61 V and efficiency of 80% is assumed. Average input current in the input filter inductor is:

ǒESRCǓǒVIN * VOUTǓVOUT ǒfOSCǓǒLǓǒVINǓ

Finally, we should consider power dissipation in the output inductors. Power dissipation is proportional to the square of inductor current: PD + (I 2L)(ESRL)

The temperature rise of the inductor relative to the air surrounding it is defined as the product of power dissipation and thermal resistance to ambient:

IIN(AVE) + (10 A)(3.3 Vń5 V) + 6.6 A

T(inductor) + (Ra)(PD)

Input capacitor RMS ripple current is then

Ǹ

Ra for an inductor designed to conduct 20 A to 30 A is approximately 45°C/W. The inductor temperature is given as:

IIN(RMS) +

T(inductor) + T(inductor) ) Tambient VCC Bypass Filtering

6.62 ) 3.3 V 5V [(10 A * 6.6 A)2 * 6.6 A2]

+ 4.74 A

A small RC filter should be added between module VCC and the VCC input to the IC. A 10 Ω resistor and a 0.1 µF capacitor should be sufficient to ensure the controller IC does not operate erratically due to injected noise.

If we consider a Rubycon MBZ series capacitor, the ripple current rating for a 6.3 V, 1800 nF capacitor is 2000 mA at 100 kHz and 105°C. We determine the number of input capacitors by dividing the ripple current by the per–capacitor current rating:

Input Filter Capacitors

Number of capacitors + 4.74 Ań2.0 A + 2.3

The input filter capacitors provide a charge reservoir that minimizes supply voltage variations due to changes in current flowing through the switch FETs. These capacitors must be chosen primarily for ripple current rating.

A total of at least 3 capacitors in parallel must be used to meet the input capacitor ripple current requirements.


NCP1570 Output Switch FETs

I I I IPEAK + ILOAD ) RIPPLE + OUT ) RIPPLE 2 3 2

Output switch FETs must be chosen carefully, since their properties vary widely from manufacturer to manufacturer. The NCP1570 system is designed assuming that n–channel FETs will be used. The FET characteristics of most concern are the gate charge/gate–source threshold voltage, gate capacitance, on–resistance, current rating and the thermal capability of the package. The onboard FET driver has a limited drive capability. If the switch FET has a high gate charge, the amount of time the FET stays in its ohmic region during the turn–on and turn–off transitions is larger than that of a low gate charge FET, with the result that the high gate charge FET will consume more power. Similarly, a low on–resistance FET will dissipate less power than will a higher on–resistance FET at a given current. Thus, low gate charge and low RDS(ON) will result in higher efficiency and will reduce generated heat. It can be advantageous to use multiple switch FETs to reduce power consumption. By placing a number of FETs in parallel, the effective RDS(ON) is reduced, thus reducing the ohmic power loss. However, placing FETs in parallel increases the gate capacitance so that switching losses increase. As long as adding another parallel FET reduces the ohmic power loss more than the switching losses increase, there is some advantage to doing so. However, at some point the law of diminishing returns will take hold, and a marginal increase in efficiency may not be worth the board area required to add the extra FET. Additionally, as more FETs are used, the limited drive capability of the FET driver will have to charge a larger gate capacitance, resulting in increased gate voltage rise and fall times. This will affect the amount of time the FET operates in its ohmic region and will increase power dissipation. The following equations can be used to calculate power dissipation in the switch FETs. For ohmic power losses due to RDS(ON): PON(TOP) +

PON(BOTTOM) +

where: D = Duty cycle. For switching power losses: PD + nCV2(fOSC)

where: n = number of switch FETs (either top or bottom), C = FET gate capacitance, V = maximum gate drive voltage (usually VCC), fOSC = switching frequency. Layout Considerations

1. The fast response time of V2 technology increases the IC’s sensitivity to noise on the VFB line. Fortunately, a simple RC filter, formed by the feedback network and a small capacitor (100 pF works well, shown below as C6) placed between VFB and GND, filters out most noise and provides a system practically immune to jitter. This capacitor should be located as close as possible to the IC. 2. The COMP capacitor (shown below as C13) should be connected via its own path to the IC ground. The COMP capacitor is sensitive to the intermittent ground drops caused by switching currents. A separate ground path will reduce the potential for jitter. 3. The VCC bypass capacitor (0.1 µF or greater, shown below as C4) should be located as close as possible to the IC. This capacitor’s connection to GND must be as short as possible. The 10 Ω resistor (shown below as R3) should be placed close to the VCC pin. 4. The IC should not be placed in the path of switching currents. If a ground plane is used, care should be taken by the designer to ensure that the IC is not located over a ground or other current return path.

(RDS(ON)(TOP))(IRMS(TOP))2 (number of topside FETs)

ǒRDS(ON)(BOTTOM)ǓǒIRMS(BOTTOM)Ǔ2

R4

ǒnumber of bottom–side FETsǓ

C6

VOUT R6

where: n = number of phases. Note that RDS(ON) increases with temperature. It is good practice to use the value of RDS(ON) at the FET’s maximum junction temperature in the calculations shown above. IRMS(TOP) +

ǸI

C4

C12

R3 U1

2 PK

* (IPK)(IRIPPLE) ) D I 2RIPPLE 3

IRMS(BOTTOM) + I 2PK * (IPKIRIPPLE) ) IRIPPLE +

C13 R1 5V

GND

(1 * D) 2 I RIPPLE 3

12 V PWRGD

Figure 25.

(VIN * VOUT)(VOUT) (fOSC)(L)(VIN)


28* &# ! The NCP1571 is a low voltage buck controller. It provides the control for a DC–DC power solution producing an output voltage as low as 0.980 V over a wide current range. The NCP1571–based solution is powered from 12 V with the output derived from a 2–7 V supply. It contains all required circuitry for a synchronous NFET buck regulator using the V2 control method to achieve the fastest possible transient response and best overall regulation. NCP1571 operates at a fixed internal 200 kHz frequency and is packaged in an SO–8. This device provides undervoltage lockout protection, Soft Start, Power Good with delay, and built–in adaptive non–overlap. During undervoltage lockout, the NCP1571 controller allows the power supply output to drift down, allowing the load time to shut off. This operation distinguishes the NCP1571 from other parts in its family.

1 SO–8 D SUFFIX CASE 751


PWRGD PGDELAY

1

8 1571 ALYW


8

VCC

Features • 0.980 V ± 1.0% Reference Voltage • V2 Control Topology • 200 ns Transient Response • Programmable Soft Start • Power Good • Programmable Power Good Delay • 40 ns Gate Rise and Fall Times (3.3 nF Load) • Adaptive FET Non–Overlap Time • Fixed 200 kHz Oscillator Frequency • Undervoltage Lockout Holds Both Gate Outputs Low • On/Off Control Through Use of the COMP Pin • Overvoltage Protection through Synchronous MOSFETs • Synchronous N–Channel Buck Design • Dual Supply, 12 V Control, 2–7 V Power Source


http://onsemi.com

COMP A WL, L YY, Y WW, W

GND VFB GATE(L) GATE(H)



1608

Package

Shipping

NCP1571D

SO–8

95 Units/Rail

NCP1571DR2

SO–8

2500 Tape & Reel


NCP1571 12 V PWRGD VLOGIC

GND

5.0 V 33 µF/8.0 V/1.6 Arms × 4

R1 50 k

C1 C4

VCC

2.7 µH GND

+

C3

PWRGD NCP1571

VFB

PGDELAY

GATE(L)

COMP

GATE(H)

2.5 V

1.2 V/10 A

L1

100 pF C6

10

C12 0.01 µF

C2

NTD4302 Q1

0.1 µF R4

+

+

+

5.1 k R3

NTD4302 Q2

+

C8

+

C9

+

C10

C11 GND

56 µF/4.0 V/1.6 Arms SP–CAP 40 mΩ

R5 3.3 k

C13 0.1 µF

Figure 1. Applications Circuit MAXIMUM RATINGS* Rating

Value

Unit

150

°C

–65 to 150

°C

2.0

kV

230 peak

°C

1

–

48 165

°C/W °C/W

Operating Junction Temperature Storage Temperature Range ESD Susceptibility (Human Body Model) Lead Temperature Soldering:

Reflow: (Note 1)

Moisture Sensitivity Level Package Thermal Resistance, SO–8 Junction–to–Case, RθJC Junction–to–Ambient, RθJA 1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed.


Pin Symbol

VMAX

VMIN

ISOURCE

ISINK

IC Power Input

VCC

15 V

–0.5 V

N/A



COMP

6.0 V

–0.5 V

10 mA

10 mA


VFB

6.0 V

–0.5 V

1.0 mA

1.0 mA

Power Good Output

PWRGD

15 V

–0.5 V

1.0 mA

20 mA

Power Good Delay

PGDELAY

6.0 V

–0.5 V

1.0 mA

10 mA


GATE(H)

15 V

–0.5 V –2.0 V for 50 ns




GATE(L)

15 V

–0.5 V –2.0 V for 50 ns



Ground

GND

0.5 V

–0.5 V


N/A


NCP1571 ELECTRICAL CHARACTERISTICS (0°C < TJ < 125°C, 11.4 V < VCC < 12.6 V, CGATE(H) = CGATE(L) = 3.3 nF, CPGDELAY = 0.01 µF, CCOMP = 0.1 µF; unless otherwise specified.)

Test Conditions

Characteristic

Min

Typ

Max

Unit


VFB = 0 V

–

0.2

2.0

µA

COMP Source Current

COMP = 1.5 V, VFB = 0.8 V

15

30

60

µA

COMP Sink Current

COMP = 1.5 V, VFB = 1.2 V

15

30

60

µA

Reference Voltage

COMP = VFB TJ < 25°C

0.970 0.965

0.980 0.980

0.990 0.995

V V

COMP Max Voltage

VFB = 0.8

2.4

2.7

–

V

COMP Min Voltage

VFB = 1.2

–

0.1

0.2

V

COMP Fault Discharge Current at UVLO

COMP = 1.2 V, VCC = 6.9 V

0.5

1.7

–

mA

COMP Fault Discharge Threshold to Reset UVLO

COMP = 0.5 V, VCC = 12 V – 6.9 V – 12 V. Ramp COMP to 0.1 V. Monitor I (COMP)

0.1

0.25

0.3

V

Open Loop Gain

–

–

98

–

dB


–

–

20

–

kHz

PSRR @ 1.0 kHz

–

–

70

–

dB


–

–

32

–

mmho

Output Impedance

–

–

2.5

–

MΩ

GATE(H) and GATE(L) Rise Time

1.0 V < GATE(L) & GATE(H) < VCC – 2.0

–

40

80

ns

Fall Time

VCC – 2.0 < GATE(L) & GATE(H) < 1.0 V

–

40

80

ns


GATE(H) < 2.0 V, GATE(L) > 2.0 V

40

60

100

ns


GATE(L) < 2.0 V, GATE(H) > 2.0 V

40

60

100

ns

Minimum Pulse Width

GATE(X) = 4.0 V

–

250

–

ns

High Voltage (AC)

Measure GATE(L) or GATE(H) 0.5 nF < CGATE(H) = CGATE(L) < 10 nF Note 2.

VCC – 0.5

VCC

–

V

Low Voltage (AC)

Measure GATE(L) or GATE(H) 0.5 nF < CGATE(H) = CGATE(L) < 10 nF Note 2.

–

0

0.5

V


Resistance to GND. Note 2.

20

50

115

kΩ

TJ < 25°C

0.852 0.847

0.882 0.882

0.912 0.917

V V

TJ < 25°C

0.663 0.658

0.685 0.685

0.709 0.714

V V

–

0.15

0.4

V

7.0

12

18

µA

3.45

4.0

4.3

V

Power Good Lower Threshold, VO Rising Lower Threshold, VO Falling PWRGD Low Voltage

ISINK = 1.0 mA, VFB = 0


PGDELAY = 2.0 V

Delay Clamp Voltage

–

Delay Charge Threshold

Ramp PGDELAY, Monitor PWRGD

3.1

3.3

3.5

V

Delay Discharge Current at UVLO

PGDELAY = 0.5 V, VCC = 6.9 V

0.5

2.0

–

mA



NCP1571 ELECTRICAL CHARACTERISTICS (continued) (0°C < TJ < 125°C, 11.4 V < VCC < 12.6 V, CGATE(H) = CGATE(L) = 3.3 nF, CPGDELAY = 0.01 µF, CCOMP = 0.1 µF; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

Delay Discharge Threshold to Reset UVLO

PGDELAY = 0.5 V, VCC = 12 V to 6.9 to 12 V, Ramp PGDELAY to 0.1 V, Monitor I (PGDELAY)

0.1

0.25

0.3

V

“Good” Signal Delay

With 0.01 µF. Note 3.

1.0

3.0

5.0

ms

0.475

0.525

0.575

V

–

80

–

%

Power Good

PWM Comparator PWM Comparator Offset

VFB = 0 V, Increase COMP Until GATE(H) Starts Switching

Ramp Max Duty Cycle

–

Artificial Ramp

Duty Cycle = 50%

18

25

35

mV

Transient Response

COMP = 1.5 V, VFB 20 mV Overdrive. Note 3

–

200

300

ns

VFB Input Range

Note 3

0

–

1.4

V

150

200

250

kHz

–

10

15

mA

Oscillator –

Switching Frequency General Electrical Specifications VCC Supply Current

COMP = 0 V (No Switching)

Start Threshold


8.0

8.5

9.0

V

Stop Threshold

GATE(H) Not Switching, COMP Discharging

7.0

7.5

8.0

V

Hysteresis

Start – Stop

0.75

1.0

1.25

V



PIN SYMBOL

1

VCC

2

PWRGD

Open collector output goes low when VFB is out of regulation. User must externally limit current into this pin to less than 20 mA.

3

PGDELAY

External capacitor programs PWRGD low–to–high transition delay.

4

COMP

Error amp output. PWM comparator reference input. A capacitor to LGND provides error amp compensation and Soft Start. Pulling pin < 0.475 V locks gate outputs to a zero percent duty cycle state.

5

GATE(H)

High–side switch FET driver pin. Capable of delivering peak currents of 1.5 A.

6

GATE(L)

Low–side synchronous FET driver pin. Capable of delivering peak currents of 1.5 A.

7

VFB

Error amplifier and PWM comparator input.

8

GND

Power supply return.

FUNCTION Power supply input.


NCP1571

VCC

Fault Latch

UVLO COMP

–

S

Q

+ + –

– 8.5 V/7.5 V + + –

R Set Dominant

0.25 V

GND VCC

–

VFB

Error Amp

PWM COMP

–

PWM Latch

+

R

GATE(H)

Q

+ + –

Non Overlap

0.980 V S Reset Dominant

GATE(L)

COMP 0.525 V Σ

– +

OSC

Art Ramp 80%, 200 kHz

+

0.25 V

12 µA

–

+ –

PGDELAY –

PGDELAY Latch S

–

Q

+

+ + –

+ –

0.88 V/0.69 V R Set Dominant



3.3 V

PWRGD

NCP1571 TYPICAL PERFORMANCE CHARACTERISTICS 10

216 214


ICC (mA)

9

8

7

6

212 210 208 206 204

5

0

20


100

202

120

0.984

27

0.983

26

0.982 0.981 0.980 0.979 0.978

0

20

40


100

120

24 23 22

0

20

40


100

120

Figure 6. Artificial Ramp Amplitude vs. Temperature (50% Duty Cycle)

540

8.6 Start/Stop Threshold Voltages (V)

PWM Offset Voltage (mV)

100

25

20

120


535

530

525

520


21

0.977 0.976

20


Ramp Amplitude (mV)


Figure 3. Supply Current vs. Temperature

0

0

20


100

120

Figure 7. PWM Offset Voltage vs. Temperature

8.4 Turn–On Threshold

8.2 8.0 7.8

Turn–Off Threshold

7.6 7.4 7.2

0

20


100

Figure 8. Undervoltage Lockout Thresholds vs. Temperature


120

NCP1571 TYPICAL PERFORMANCE CHARACTERISTICS 0.60

31 30 Output Current (µA)

Bias Current (µA)

0.55

0.50

0.45

29 Sink Current 28 27 Source Current 26 25

0.40

0

20

40


100

24

120

Figure 9. VFB Bias Current vs. Temperature


100

120


1.15

2.5 2.0 COMP Minimum Voltage

1.5 1.0

COMP Fault Threshold Voltage

0.5 0

20

40


100

1.10 1.05 1.00 0.95 0.90

120

Figure 11. COMP Voltages vs. Temperature

0

20


100

120

Figure 12. COMP Fault Mode Discharge Current vs. Temperature

55

38 GATEH Fall Time

36

GATEH Rise Time

Gate Non–Overlap Time (ns)

COMP Voltages (V)

40

1.20 COMP Maximum Voltage

3.0

GATE Rise/Fall Times (ns)

20

Figure 10. Error Amp Output Currents vs. Temperature

3.5

0

0

34 32 30 28 GATEL Rise Time 26

GATEL Fall Time

24

50 GATEH to GATEL Delay Time 45 GATEL to GATEH Delay Time

40

35

22 20

0

20


100

120

Figure 13. GATE Output Rise and Fall Times vs. Temperature

30

0

20


100

120

Figure 14. GATE Non–Overlap Times vs. Temperature


NCP1571 TYPICAL PERFORMANCE CHARACTERISTICS 70 Turn–On Threshold, VFB Rising

900

PWRGD Low Voltage (mV)

PWRGD Threshold Voltages (mV)

1000

800

700 Turn–Off Threshold, VFB Falling 600

0

20


100

65 60 55 50 45 40

120

13.4

1.45

13.1

1.40

12.8 12.5 12.2 11.9 11.6


100

120

1.35 1.30 1.25 1.20

0

20


100

1.15

120

Figure 17. PGDELAY Charge Current vs. Temperature

0

20


100

120

Figure 18. PGDELAY Discharge Current vs. Temperature

259

4.00 3.90 PGDELAY Voltages (V)

Discharge Threshold Voltage (mV)

20

Figure 16. PWRGD Output Low Voltage vs. Temperature


PGDELAY Charge Current (µA)

Figure 15. PWRGD Thresholds vs. Temperature

0

257

255

253

PGDELAY Max Voltage

3.80 3.70 3.60 3.50 3.40

PGDELAY Upper Threshold Voltage

3.30 251

0

20


100

120

Figure 19. PGDELAY Discharge Threshold Voltage vs. Temperature

3.20

0

20


100

Figure 20. PGDELAY Voltages vs. Temperature


120

NCP1571 APPLICATION INFORMATION THEORY OF OPERATION

time to the output load step is not related to the crossover frequency of the error signal loop. The error signal loop can have a low crossover frequency, since the transient response is handled by the ramp signal loop. The main purpose of this ‘slow’ feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. Line and load regulation are drastically improved because there are two independent control loops. A voltage mode controller relies on the change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains a fixed error signal during line transients, since the slope of the ramp signal changes in this case. However, regulation of load transients still requires a change in the error signal. The V2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load. The stringent load transient requirements of modern microprocessors require the output capacitors to have very low ESR. The resulting shallow slope in the output ripple can lead to pulse width jitter and variation caused by both random and synchronous noise. A ramp waveform generated in the oscillator is added to the ramp signal from the output voltage to provide the proper voltage ramp at the beginning of each switching cycle. This slope compensation increases the noise immunity, particularly at duty cycles above 50%.

The NCP1571 is a simple, synchronous, fixed–frequency, low–voltage buck controller using the V2 control method. It provides a programmable–delay Power Good function to indicate when the output voltage is out of regulation. V2 Control Method

The V2 control method uses a ramp signal generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. The V2 method differs from traditional techniques such as voltage mode control, which generates an artificial ramp, and current mode control, which generates a ramp using the inductor current.

–

GATE(H)

PWM +

GATE(L)

RAMP

Slope Compensation

Output Voltage Error Amplifier

VFB

–

COMP

Error Signal

+

Reference Voltage

Figure 21. V2 Control with Slope Compensation

Start Up

The V2 control method is illustrated in Figure 21. The output voltage generates both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output, regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, allowing the control circuit to drive the main switch to 0% or 100% duty cycle as required. A variation in line voltage changes the current ramp in the inductor, which causes the V2 control scheme to compensate the duty cycle. Since any variation in inductor current modifies the ramp signal, as in current mode control, the V2 control scheme offers the same advantages in line transient response. A variation in load current will affect the output voltage, modifying the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. The comparator response time and the transition speed of the main switch determine the load transient response. Unlike traditional control methods, the reaction

The NCP1571 features a programmable Soft Start function, which is implemented through the error amplifier and the external compensation capacitor. This feature prevents stress to the power components and limits output voltage overshoot during start–up. As power is applied to the regulator, the NCP1571 undervoltage lockout circuit (UVL) monitors the IC’s supply voltage (VCC). The UVL circuit holds both gate outputs low until VCC exceeds the 8.5 V threshold. A hysteresis function of 1.0 V improves noise immunity. The compensation capacitor connected to the COMP pin is charged by a 30 µA current source. When the capacitor voltage exceeds the 0.5 V offset of the PWM comparator, the PWM control loop will allow switching to occur. The upper gate driver GATE(H) is activated, turning on the upper MOSFET. The current ramps up through the main inductor and linearly powers the output capacitors and load. When the regulator output voltage exceeds the COMP pin voltage minus the 0.5 V PWM comparator offset


NCP1571 to an overvoltage condition within 200 ns, turning off the upper MOSFET and disconnecting the regulator from its input voltage. This results in a crowbar action to clamp the output voltage, preventing damage to the load. The regulator remains in this state until the overvoltage condition ceases.

threshold and the artificial ramp, the PWM comparator terminates the initial pulse. VIN

8.5 V

Power Good

VCOMP

The PWRGD pin is asserted when the output voltage is within regulation limits. Sensing for the PWRGD pin is achieved through the VFB pin. When the output voltage is rising, PWRGD goes high at 90% of the designed output voltage. When the output voltage is falling, PWRGD goes low at 70% of the designed output voltage. PWRGD is an open–collector output and should be externally pulled to logic high through a resistor to limit current to no more than 20 mA. Figure 23 shows the hysteretic nature of the PWRGD pin’s operation.

0.5 V VFB

GATE(H)

UVLO

STARTUP

tS

NORMAL OPERATION

Figure 22. Idealized Waveforms Normal Operation

During normal operation, the duty cycle of the gate drivers remains approximately constant as the V2 control loop maintains the regulated output voltage under steady state conditions. Variations in supply line or output load conditions will result in changes in duty cycle to maintain regulation.

PWRGD High

Input Supplies

The NCP1571 can be used in applications where a 12 V supply is available along with a lower voltage supply. Often the lower voltage supply is 5 V, but it can be any voltage less than the 12 V supply minus the required gate drive voltage of the top MOSFET. The greater the difference between the two voltages, the better the efficiency due to increasing VGS available to turn on the upper MOSFET. In order to maintain power supply stability, the lower supply voltage should be at least 1.5 times the desired voltage. A lower supply voltage between 2–7 V is recommended.

Low VOUT 70% 90% Percent of Designed VOUT

Figure 23. PWRGD Assertion Shutdown

When the input voltage connected to VCC falls through the lower threshold of the UVLO comparator, a fault latch is set. The fault latch provides a signal that forces both GATE(H) and GATE(L) into their logic low state, producing a high–impedance output at the converter switch node. At the same time, the latch also turns on two transistors which pull down on the COMP and PGDELAY pins, quickly discharging their external capacitors, and allowing PWRGD to fall.

Gate Charge Effect on Switching Times

When using the onboard gate drivers, the gate charge has an important effect on the switching times of the FETs. A finite amount of time is required to charge the effective capacitor seen at the gate of the FET. Therefore, the rise and fall times rise linearly with increased capacitive loading. Transient Response

The 200 ns reaction time of the control loop provides fast transient response to any variations in input voltage and output current. Pulse–by–pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitors during the time required to slew the inductor current. For better transient response, several high frequency and bulk output capacitors are usually used.

CONVERTER DESIGN Selection of the Output Capacitors

These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to provide acceptable ripple on the regulator output voltage. Key specifications for output capacitors are their ESR (Equivalent Series Resistance), and ESL (Equivalent Series Inductance). For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. In order to determine the number of output capacitors the maximum voltage transient allowed during load transitions has to be specified. The output capacitors must hold the


Overvoltage protection is provided as a result of the normal operation of the V2 control method and requires no additional external components. The control loop responds


NCP1571 The inductor’s limiting effect on the input current slew rate becomes increasingly beneficial during load transients. The worst case is when the load changes from no load to full load (load step), a condition under which the highest voltage change across the input capacitors is also seen by the input inductor. The inductor successfully blocks the ripple current while placing the transient current requirements on the input bypass capacitor bank, which has to initially support the sudden load change. The minimum inductance value for the input inductor is therefore:

output voltage within these limits since the inductor current can not change with the required slew rate. The output capacitors must therefore have a very low ESL and ESR. The voltage change during the load current transient is: VOUT + IOUT

t ǒESL ) ESR ) TR Ǔ t COUT

where: ∆IOUT / ∆t = load current slew rate; ∆IOUT = load transient; ∆t = load transient duration time; ESL = Maximum allowable ESL including capacitors, circuit traces, and vias; ESR = Maximum allowable ESR including capacitors and circuit traces; tTR = output voltage transient response time. The designer has to independently assign values for the change in output voltage due to ESR, ESL, and output capacitor discharging or charging. Empirical data indicates that most of the output voltage change (droop or spike depending on the load current transition) results from the total output capacitor ESR. The maximum allowable ESR can then be determined according to the formula: ESRMAX +

V LIN + (dIńdt)MAX

where: LIN = input inductor value; ∆V = voltage seen by the input inductor during a full load swing; (dI/dt)MAX = maximum allowable input current slew rate. The designer must select the LC filter pole frequency so that at least 40 dB attenuation is obtained at the regulator switching frequency. The LC filter is a double–pole network with a slope of –2.0, a roll–off rate of –40 dB/dec, and a corner frequency:

VESR IOUT

fC +

Selection of the Output Inductor

There are many factors to consider when choosing the output inductor. Maximum load current, core and winding losses, ripple current, short circuit current, saturation characteristics, component height and cost are all variables that the designer should consider. However, the most important consideration may be the effect inductor value has on transient response. The amount of overshoot or undershoot exhibited during a current transient is defined as the product of the current step and the output filter capacitor ESR. Choosing the inductor value appropriately can minimize the amount of energy that must be transferred from the inductor to the capacitor or vice–versa. In the subsequent paragraphs, we will determine the minimum value of inductance required for our system and consider the trade–off of ripple current vs. transient response. In order to choose the minimum value of inductance, input voltage, output voltage and output current must be known. Most computer applications use reasonably well regulated bulk power supplies so that, while the equations below specify VIN(MAX) or VIN(MIN), it is possible to use the nominal value of VIN in these calculations with little error. Current in the inductor while operating in the continuous current mode is defined as the load current plus ripple current.

ESRCAP ESRMAX

where: ESRCAP = maximum ESR per capacitor (specified in manufacturer’s data sheet). ESRMAX = maximum allowable ESR. The actual output voltage deviation due to ESR can then be verified and compared to the value assigned by the designer: VESR + IOUT

ESRMAX

Similarly, the maximum allowable ESL is calculated from the following formula: ESLMAX +

VESL I

ǸLC

where: L = input inductor; C = input capacitor(s).

where: ∆VESR = change in output voltage due to ESR (assigned by the designer) Once the maximum allowable ESR is determined, the number of output capacitors can be found by using the formula: Number of capacitors +

1 2

t

Selection of the Input Inductor

A common requirement is that the buck controller must not disturb the input voltage. One method of achieving this is by using an input inductor and a bypass capacitor. The input inductor isolates the supply from the noise generated in the switching portion of the buck regulator and also limits the inrush current into the input capacitors upon power up.


NCP1571 IL + ILOAD ) IRIPPLE

Finally, we should consider power dissipation in the output inductors. Power dissipation is proportional to the square of inductor current:

The ripple current waveform is triangular, and the current is a function of voltage across the inductor, switch FET on–time and the inductor value. FET on–time can be defined as the product of duty cycle and switch frequency, and duty cycle can be defined as a ratio of VOUT to VIN. Thus, IRIPPLE +

PD + (I 2L)(ESRL)

The temperature rise of the inductor relative to the air surrounding it is defined as the product of power dissipation and thermal resistance to ambient:

(VIN * VOUT)VOUT (fOSC)(L)(VIN)

T(inductor) + (Ra)(PD)

Peak inductor current is defined as the load current plus half of the peak current. Peak current must be less than the maximum rated FET switch current, and must also be less than the inductor saturation current. Thus, the maximum output current can be defined as: IOUT(MAX) + ISWITCH(MAX) *

Ra for an inductor designed to conduct 20 A to 30 A is approximately 45°C/W. The inductor temperature is given as: T(inductor) + T(inductor) ) Tambient VCC Bypass Filtering

ǒVIN(MAX) * VOUTǓVOUT

A small RC filter should be added between module VCC and the VCC input to the IC. A 10 Ω resistor and a 0.47 µF capacitor should be sufficient to ensure the controller IC does not operate erratically due to injected noise, and will also supply reserve charge for the onboard gate drivers.

ǒ2ǓǒfOSCǓǒLǓǒVIN(MAX)Ǔ

Since the maximum output current must be less than the maximum switch current, the minimum inductance required can be determined. (VIN(MIN) * VOUT)VOUT L(MIN) + (fOSC)(ISWITCH(MAX))(VIN(MIN))

Input Filter Capacitors

The input filter capacitors provide a charge reservoir that minimizes supply voltage variations due to changes in current flowing through the switch FETs. These capacitors must be chosen primarily for ripple current rating.

This equation identifies the value of inductor that will provide the full rated switch current as inductor ripple current, and will usually result in inefficient system operation. The system will sink current away from the load during some portion of the duty cycle unless load current is greater than half of the rated switch current. Some value larger than the minimum inductance must be used to ensure the converter does not sink current. Choosing larger values of inductor will reduce the ripple current, and inductor value can be designed to accommodate a particular value of ripple current by replacing ISWITCH(MAX) with a desired value of IRIPPLE:

LIN

IRMS(CIN)

COUT

CONTROL INPUT

Consider the schematic shown in Figure 24. The average current flowing in the input inductor LIN for any given output current is: IIN(AVE) + IOUT

(L)(IOUT) (VIN * VOUT)

VOUT VIN

Input capacitor current is positive into the capacitor when the switch FETs are off, and negative out of the capacitor when the switch FETs are on. When the switches are off, IIN(AVE) flows into the capacitor. When the switches are on, capacitor current is equal to the per–phase output current minus IIN(AVE). If we ignore the small current variation due to the output ripple current, we can approximate the input capacitor current waveform as a square wave. We can then calculate the RMS input capacitor ripple current:

(L)(IOUT) (VOUT)

Inductor value selection also depends on how much output ripple voltage the system can tolerate. Output ripple voltage is defined as the product of the output ripple current and the output filter capacitor ESR. Thus, output ripple voltage can be calculated as: VRIPPLE + ǒESRCǓǒIRIPPLEǓ +

CIN

Figure 24.

However, reducing the ripple current will cause transient response times to increase. The response times for both increasing and decreasing current steps are shown below.

TRESPONSE(DECREASING) +

VOUT IIN(AVE)

(VIN(MIN) * VOUT)VOUT L(RIPPLE) + (fOSC)(IRIPPLE)(VIN(MIN))

TRESPONSE(INCREASING) +

LOUT

VIN

ǒESRCǓǒVIN * VOUTǓVOUT ǒfOSCǓǒLǓǒVINǓ


NCP1571

Ǹ

there is some advantage to doing so. However, at some point the law of diminishing returns will take hold, and a marginal increase in efficiency may not be worth the board area required to add the extra FET. Additionally, as more FETs are used, the limited drive capability of the FET driver will have to charge a larger gate capacitance, resulting in increased gate voltage rise and fall times. This will affect the amount of time the FET operates in its ohmic region and will increase power dissipation. The following equations can be used to calculate power dissipation in the switch FETs. For ohmic power losses due to RDS(ON):

V I 2IN(AVE) ) OUT VIN ǒIOUT per phase * IIN(AVE)Ǔ2 * I 2 IN(AVE)

IRMS(CIN) +

ƪ

ƫ

The input capacitance must be designed to conduct the worst case input ripple current. This will require several capacitors in parallel. In addition to the worst case current, attention must be paid to the capacitor manufacturer’s derating for operation over temperature. As an example, let us define the input capacitance for a 5 V to 3.3 V conversion at 10 A at an ambient temperature of 60°C. Efficiency of 80% is assumed. Average input current in the input filter inductor is:

PON(TOP) +

IIN(AVE) + (10 A)(3.3 Vń5 V) + 6.6 A

Input capacitor RMS ripple current is then

Ǹ

IIN(RMS) +

PON(BOTTOM) +

6.62 ) 3.3 V 5V [(10 A * 6.6 A)2 * 6.6 A2]

(RDS(ON)(TOP))(IRMS(TOP))2 (number of topside FETs)

ǒRDS(ON)(BOTTOM)ǓǒIRMS(BOTTOM)Ǔ2 ǒnumber of bottom–side FETsǓ

where: n = number of phases. Note that RDS(ON) increases with temperature. It is good practice to use the value of RDS(ON) at the FET’s maximum junction temperature in the calculations shown above.

+ 4.74 A

If we consider a Rubycon MBZ series capacitor, the ripple current rating for a 6.3 V, 1800 nF capacitor is 2000 mA at 100 kHz and 105°C. We determine the number of input capacitors by dividing the ripple current by the per–capacitor current rating:

IRMS(TOP) +

ǸI

2 PK

* (IPK)(IRIPPLE) ) D I 2RIPPLE 3

IRMS(BOTTOM) + I 2PK * (IPKIRIPPLE) )

Number of capacitors + 4.74 Ań2.0 A + 2.3

A total of at least 3 capacitors in parallel must be used to meet the input capacitor ripple current requirements.

IRIPPLE +

Output Switch FETs

(1 * D) 2 I RIPPLE 3

(VIN * VOUT)(VOUT) (fOSC)(L)(VIN)

I I I IPEAK + ILOAD ) RIPPLE + OUT ) RIPPLE 2 3 2

Output switch FETs must be chosen carefully, since their properties vary widely from manufacturer to manufacturer. The NCP1571 system is designed assuming that n–channel FETs will be used. The FET characteristics of most concern are the gate charge/gate–source threshold voltage, gate capacitance, on–resistance, current rating and the thermal capability of the package. The onboard FET driver has a limited drive capability. If the switch FET has a high gate charge, the amount of time the FET stays in its ohmic region during the turn–on and turn–off transitions is larger than that of a low gate charge FET, with the result that the high gate charge FET will consume more power. Similarly, a low on–resistance FET will dissipate less power than will a higher on–resistance FET at a given current. Thus, low gate charge and low RDS(ON) will result in higher efficiency and will reduce generated heat. It can be advantageous to use multiple switch FETs to reduce power consumption. By placing a number of FETs in parallel, the effective RDS(ON) is reduced, thus reducing the ohmic power loss. However, placing FETs in parallel increases the gate capacitance so that switching losses increase. As long as adding another parallel FET reduces the ohmic power loss more than the switching losses increase,

where: D = Duty cycle. For switching power losses: PD + nCV2(fOSC)

where: n = number of switch FETs (either top or bottom), C = FET gate capacitance, V = maximum gate drive voltage (usually VCC), fOSC = switching frequency. Layout Considerations

1. The fast response time of V2 technology increases the IC’s sensitivity to noise on the VFB line. Fortunately, a simple RC filter, formed by the feedback network and a small capacitor (100 pF works well, shown below as C6) placed between VFB and GND, filters out most noise and provides a system practically immune to jitter. This capacitor should be located as close as possible to the IC. 2. The COMP capacitor (shown below as C13) should be connected via its own path to the IC ground. The COMP capacitor is sensitive to the


NCP1571 intermittent ground drops caused by switching currents. A separate ground path will reduce the potential for jitter. 3. The VCC bypass capacitor (0.1 µF or greater, shown below as C4) should be located as close as possible to the IC. This capacitor’s connection to GND must be as short as possible. The 10 Ω resistor (shown below as R3) should be placed close to the VCC pin. 4. The IC should not be placed in the path of switching currents. If a ground plane is used, care should be taken by the designer to ensure that the IC is not located over a ground or other current return path.

R4 C6

VOUT R6

C4

C12

R3 U1

C13 R1 5V

GND 12 V PWRGD

Figure 25.


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Conditions

Results

Line Regulation

Vin = 8.0 V to 26 V, IO = 0.5 A

40 mV 0.14%

Load Regulation

Vin = 12 V, IO = 1.0 mA to 0.5 A

5.0 mV 0.18%

Output Ripple

Vin = 12 V, IO = 0.5 A

24 mV p–p P.A.R.D.

Efficiency

Vin = 12 V, IO = 0.5 A

75%

*Optional circuit to minimize output ripple



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Conditions

Results

Line Regulation

Vin = 8.0 V to 40 V, IO = 250 mA

52 mV

0.35%

Load Regulation

Vin = 12 V, IO = 1.0 to 250 mA

47 mV

0.32%

Output Ripple

Vin = 12 V, IO = 250 mA


Vin = 12 V, RL = 0.1 Ω

Efficiency

Vin = 12 V, IO = 250 mA

10 mV p–p P.A.R.D. 330 mA 86%

*Optional circuit to minimize output ripple

Figure 21. Step–Up/Down Voltage Inverting Converter with Soft–Start and Current Limiting


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Line Regulation 5.0 V

V in = 95 Vac to 135 Vac, IO = 3.0 A

20 mV 0.40%

Line Regulation ±12 V

V in = 95 Vac to 135 Vac, IO = ±0.75 A

52 mV 0.26%

Load Regulation 5.0 V

V in = 115 Vac, IO = 1.0 A to 4.0 A

476 mV 9.5%

Load Regulation ±12 V

V in = 115 Vac, IO = ±0.4 A to ±0.9 A

Output Ripple 5.0 V

V in = 115 Vac, IO = 3.0 A


Output Ripple ±12 V

V in = 115 Vac, IO = ±0.75 A


Efficiency

V in = 115 Vac, IO 5.0 V = 3.0 A IO ±12 V = ±0.75 A

300 mV 2.5%

74%

T1 – Coilcraft W2961 T2 – Core: Coilcraft 11–464–16, 0.025″ gap in each leg. Bobbin: Coilcraft 37–573 Windings: Primary, 2 each, 75 turns #25 Awg Bifilar wound Feedback: 15 turns #26 Awg Secondary, 5.0 V, 6 turns @33 Awg Bifilar wound Secondary, 2 each, 14 turns #24 Awg Bifilar wound L1 – Coilcraft Z7156, 15 µH @ 5.0 A L2, L3 – Coilcraft Z7157, 25 µH @ 1.0 A

Figure 22. 33 W Off–Line Flyback Converter with Soft–Start and Primary Power Limiting

MC34060A, MC33060A

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MC34060A, MC33060A ORDERING INFORMATION Device


Package

Shipping

SO–14

55 Units/Rail

SO–14

2500 Tape & Reel

MC34060AP

PDIP–14

25 Units/Rail

MC33060AD

SO–14

55 Units/Rail

SO–14

2500 Tape & Reel

PDIP–14

25 Units/Rail

MC34060AD MC34060ADR2

MC33060ADR2

TA= 0° to +70°C

TA= –40° to +85°C

MC33060AP


) ) "# ' "-$ 81) The MC34023 series are high speed, fixed frequency, single–ended pulse width modulator controllers optimized for high frequency operation. They are specifically designed for Off–Line and DC–to–DC converter applications offering the designer a cost–effective solution with minimal external components. These integrated circuits feature an oscillator, a temperature compensated reference, a wide bandwidth error amplifier, a high speed current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET. Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle–by–cycle current limiting, and a latch for single pulse metering. The flexibility of this series allows it to be easily configured for either current mode or voltage mode control. • 50 ns Propagation Delay to Output • High Current Totem Pole Output • Wide Bandwidth Error Amplifier • Fully–Latched Logic with Double Pulse Suppression • Latching PWM for Cycle–By–Cycle Current Limiting • Soft–Start Control with Latched Overcurrent Reset • Input Undervoltage Lockout with Hysteresis • Low Start–Up Current (500 µA Typ) • Internally Trimmed Reference with Undervoltage Lockout • 90% Maximum Duty Cycle (Externally Adjustable) • Precision Trimmed Oscillator • Voltage or Current Mode Operation to 1.0 MHz • Functionally Similar to the UC3823

7 *'01 2 *

16 PDIP–16 P SUFFIX CASE 648 1 1

16 SO–16W DW SUFFIX CASE 751G

16 1 A WL YY WW


PIN CONNECTIONS : ;5 +< ! + ! : ;5 < ! + ! : ;5 ! ! #

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MC33023DW

SO–16W

47 Units/Rail

MC33023DWR2

SO–16W

1000 Tape & Reel

MC34023P

PDIP–16

25 Units/Rail


Figure 1. Simplified Application  Semiconductor Components Industries, LLC, 2001

May, 2001 – Rev. 3

1679


MC34023, MC33023 MAXIMUM RATINGS Rating

Symbol

Value

Unit


VCC

30

V

Output Driver Supply Voltage

VC

20

V

Output Current, Source or Sink (Note 1) DC Pulsed (0.5 µs)

IO

Current Sense, Soft–Start, Ramp, and Error Amp Inputs

Vin

–0.3 to +7.0

V

Error Amp Output and Soft–Start Sink Current

IO

10

mA

Clock and RT Output Current

ICO

5.0

mA

PD RθJA

862 145

mW °C/W

PD RθJA

1.25 100

W °C/W


TJ

+150

°C


TA

0 to +70 –40 to +105


Tstg

–55 to +150

A 0.5 2.0

Power Dissipation and Thermal Characteristics SO–16L Package (Case 751G) Maximum Power Dissipation @ TA = +25°C Thermal Resistance, Junction–to–Air DIP Package (Case 648) Maximum Power Dissipation @ TA = +25°C Thermal Resistance, Junction–to–Air

°C

°C

ELECTRICAL CHARACTERISTICS (VCC = 15 V, RT = 3.65 kΩ, CT = 1.0 nF, for typical values TA = +25°C, for min/max values TA is the operating ambient temperature range that applies [Note 2], unless otherwise noted.) Characteristic

Symbol

Min

Typ

Max

Unit

REFERENCE SECTION Vref

5.05

5.1

5.15

V


Reference Output Voltage (IO = 1.0 mA, TJ = +25°C)

Regline

–

2.0

15

mV

Load Regulation (IO = 1.0 mA to 10 mA)

Regload

–

2.0

15

mV


TS

–

0.2

–

mV/°C


Vref

4.95

–

5.25

V

Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = +25°C)

Vn

–

50

–

µV

Long Term Stability (TA = +125°C for 1000 Hours)

S

–

5.0

–

mV

ISC

– 30

– 65

–100

mA

fosc

380 370

400 400

420 430


∆fosc/∆V

–

0.2

1.0

%

Frequency Change with Temperature (TA = Tlow to Thigh)

∆fosc/∆T

–

2.0

–

%

Sawtooth Peak Voltage

VOSC(P)

2.6

2.8

3.0

V

Sawtooth Valley Voltage

VOSC(V)

0.7

1.0

1.25

V

VOH VOL

3.9 –

4.5 2.3

– 2.9

Output Short Circuit Current OSCILLATOR SECTION Frequency TJ = +25°C Line (VCC = 10 V to 30 V) and Temperature (TA = Tlow to Thigh)

kHz

Clock Output Voltage High State Low State

V

1. Maximum package power dissipation limits must be observed. 2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Thigh = +70°C for MC34023 Tlow = 0°C for MC34023 = –40°C for MC33023 = +105°C for MC33023


MC34023, MC33023 ELECTRICAL CHARACTERISTICS (VCC = 15 V, RT = 3.65 kΩ, CT = 1.0 nF, for typical values TA = +25°C, for min/max values TA is the operating ambient temperature range that applies [Note 3], unless otherwise noted.) Characteristic

Symbol

Min

Typ

Max

Unit

ERROR AMPLIFIER SECTION Input Offset Voltage

VIO

–

–

15

mV

Input Bias Current

IIB

–

0.6

3.0

µA

Input Offset Current

IIO

–

0.1

1.0

µA

Open–Loop Voltage Gain (VO = 1.0 V to 4.0 V)

AVOL

60

95

–

dB

Gain Bandwidth Product (TJ = +25°C)

GBW

4.0

8.3

–

MHz

Common Mode Rejection Ratio (VCM = 1.5 V to 5.5 V)

CMRR

75

95

–

dB

Power Supply Rejection Ratio (VCC = 10 V to 30 V)

PSRR

85

110

–

dB

Output Current, Source (VO = 4.0 V) Output Current, Sink (VO = 1.0 V)

ISource ISink

0.5 1.0

3.0 3.6

– –

mA

Output Voltage Swing, High State (IO = –0.5 mA) Output Voltage Swing, Low State (IO = 1 mA)

VOH VOL

4.5 0

4.75 0.4

5.0 1.0

V

Slew Rate

SR

6.0

12

–

V/µs

PWM COMPARATOR SECTION Ramp Input Bias Current Duty Cycle, Maximum Duty Cycle, Minimum Zero Duty Cycle Threshold Voltage Pin 3(4) (Pin 7(9) = 0 V) Propagation Delay (Ramp Input to Output, TJ = +25°C)

IIB

–

–0.5

–5.0

µA

DC(max) DC(min)

80 –

90 –

– 0

%

Vth

1.1

1.25

1.4

V

tPLH(in/out)

–

60

100

ns

SOFT–START SECTION Charge Current (VSoft–Start = 0.5 V) Discharge Current (VSoft–Start = 1.5 V)

Ichg

3.0

9.0

20

µA

Idischg

1.0

4.0

–

mA

IIB

–

–

15

µA

CURRENT SENSE SECTION Input Bias Current (Pin 9(12) = 0 V to 4.0 V) Current Limit Comparator Input Offset Voltage (Pin 11(14) = 1.1 V)

VIO

–

–

45

mV

Current Limit Reference Input Common Mode Range (Pin 11(14))

VCMR

1.0

–

1.25

V

Shutdown Comparator Threshold Propagation Delay (Current Limit/Shutdown to Output, TJ = +25°C)

Vth

1.25

1.40

1.55

V

tPLH(in/out)

–

50

80

ns

VOL

– – 13 12

0.25 1.2 13.5 13

0.4 2.2 – –

OUTPUT SECTION Output Voltage Low State (ISink = 20 mA) (ISink = 200 mA) High State (ISource = 20 mA) (ISource = 200 mA)

V

VOH

Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 0.5 mA)

VOL(UVLO)

–

0.25

1.0

V

Output Leakage Current (VC = 20 V)

IL

–

100

500

µA

Output Voltage Rise Time (CL = 1.0 nF, TJ = +25°C)

tr

–

30

60

ns

Output Voltage Fall Time (CL = 1.0 nF, TJ = +25°C)

tf

–

30

60

ns

Vth(on)

8.8

9.2

9.6

V

VH

0.4

0.8

1.2

V

– –

0.5 20

1.2 30

UNDERVOLTAGE LOCKOUT SECTION Start–Up Threshold (VCC Increasing) UVLO Hysteresis Voltage (VCC Decreasing After Turn–On) TOTAL DEVICE ICC

Power Supply Current Start–Up (VCC = 8.0 V) Operating

mA

3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Thigh = +70°C for MC34023 Tlow = 0°C for MC34023 = –40°C for MC33023 = +105°C for MC33023


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Figure 6. Error Amp Small Signal Transient Response

Figure 7. Error Amp Large Signal Transient Response


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Figure 10. Reference Line Regulation

Figure 11. Reference Load Regulation

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Figure 13. Shutdown Comparator Threshold Voltage versus Temperature


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Figure 14. Soft–Start Charge Current versus Temperature

Figure 15. Output Saturation Voltage versus Load Current

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Figure 16. Drive Output Rise and Fall Time


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Figure 18. Supply Voltage versus Supply Current


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MC34023, MC33023 OPERATING DESCRIPTION The MC33023 and MC34023 series are high speed, fixed frequency, single–ended pulse width modulator controllers optimized for high frequency operation. They are specifically designed for Off–Line and DC–to–DC converter applications offering the designer a cost effective solution with minimal external components. A representative block diagram is shown in Figure 19.

output of the error amplifier to less than its normal output voltage, thus limiting the duty cycle. The time it takes for a capacitor to reach full charge is given by: t [ (4.5 • 10 5) C Soft-Start

A Soft–Start latch is incorporated to prevent erratic operation of this circuitry. Two conditions can cause the Soft–Start circuit to latch so that the Soft–Start capacitor stays discharged. The first condition is activation of an undervoltage lockout of either VCC or Vref. The second condition is when current sense input exceeds 1.4 V. Since this latch is “set dominant”, it cannot be reset until either of these signals is removed and, the voltage at CSoft–Start is less than 0.5 V.

Oscillator

The oscillator frequency is programmed by the values selected for the timing components RT and CT. The RT pin is set to a temperature compensated 3.0 V. By selecting the value of RT, the charge current is set through a current mirror for the timing capacitor CT. This charge current runs continuously through CT. The discharge current is ratioed to be 10 times the charge current, which yields the maximum duty cycle of 90%. CT is charged to 2.8 V and discharged to 1.0 V. During the discharge of CT, the oscillator generates an internal blanking pulse that resets the PWM Latch and, inhibits the outputs. The threshold voltage on the oscillator comparator is trimmed to guarantee an oscillator accuracy of 5.0% at 25°C. Additional dead time can be added by externally increasing the charge current to CT as shown in Figure 24. This changes the charge to discharge ratio of CT which is set internally to Icharge/10 Icharge. The new charge to discharge ratio will be: % Deadtime +


A PWM circuit typically compares an error voltage with a ramp signal. The outcome of this comparison determines the state of the output. In voltage mode operation the ramp signal is the voltage ramp of the timing capacitor. In current mode operation the ramp signal is the voltage ramp induced in a current sensing element. The ramp input of the PWM comparator is pinned out so that the user can decide which mode of operation best suits the application requirements. The ramp input has a 1.25 V offset such that whenever the voltage at this pin exceeds the error amplifier output voltage minus 1.25 V, the PWM comparator will cause the PWM latch to set, disabling the outputs. Once the PWM latch is set, only a blanking pulse by the oscillator can reset it, thus initiating the next cycle.

I additional ) I charge 10 (I charge)

A bidirectional clock pin is provided for synchronization or for master/slave operation. As a master, the clock pin provides a positive output pulse during the discharge of CT. As a slave, the clock pin is an input that resets the PWM latch and blanks the drive output, but does not discharge CT. Therefore, the oscillator is not synchronized by driving the clock pin alone. Figures 28, 29 and 30 provide suggested synchronization.

Current Limiting and Shutdown

A pin is provided to perform current limiting and shutdown operations. Two comparators are connected to the input of this pin. The reference voltage for the current limit comparator is not set internally. A pin is provided so the user can set the voltage. When the voltage at the current limit input pin exceeds the externally set voltage, the PWM latch is set, disabling the output. In this way cycle–by–cycle current limiting is accomplished. If a current limit resistor is used in series with the power devices, the value of the resistor is found by:

Error Amplifier

A fully compensated Error Amplifier is provided. It features a typical DC voltage gain of 95 dB and a gain bandwidth product of 8.3 MHz with 75 degrees of phase margin (Figure 4). Typical application circuits will have the noninverting input tied to the reference. The inverting input will typically be connected to a feedback voltage generated from the output of the switching power supply. Both inputs have a common mode voltage (VCM) input range of 1.5 V to 5.5 V. The Error Amplifier Output is provided for external loop compensation.

R Sense +

I Limit Reference Voltage I pk (switch)

If the voltage at this pin exceeds 1.4 V, the second comparator is activated. This comparator sets a latch which, in turn, causes the soft start capacitor to be discharged. In this way a “hiccup” mode of recovery is possible in the case of output short circuits. If a current limit resistor is used in series with the output devices, the peak current at which the controller will enter a “hiccup” mode is given by:

Soft–Start Latch

Soft–Start is accomplished in conjunction with an external capacitor. The Soft–Start capacitor is charged by an internal 9.0 µA current source. This capacitor clamps the

I shutdown +


1.4 V R Sense

MC34023, MC33023 Undervoltage Lockout

current feedback loop. It has been shown that the instability is caused by a double pole at half the switching frequency. If an external ramp (Se) is added to the on–time ramp (Sn) of the current–sense waveform, stability can be achieved. One must be careful not to add too much ramp compensation. If too much is added the system will start to perform like a voltage mode regulator. All benefits of current mode control will be lost. Figure 26 is an example of one way in which external ramp compensation can be implemented.

There are two undervoltage lockout circuits within the IC. The first senses VCC and the second Vref. During power–up, VCC must exceed 9.2 V and Vref must exceed 4.2 V before the outputs can be enabled and the Soft–Start latch released. If VCC falls below 8.4 V or Vref falls below 3.6 V, the outputs are disabled and the Soft–Start latch is activated. When the UVLO is active, the part is in a low current standby mode allowing the IC to have an off–line bootstrap start–up circuit. Typical start–up current is 500 µA. Output

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The MC34023 has a high current totem pole output specifically designed for direct drive of power MOSFETs. It is capable of up to ± 2.0 A peak drive current with a typical rise and fall time of 30 ns driving a 1.0 nF load. Separate pins for VC and Power Ground are provided. With proper implementation, a significant reduction of switching transient noise imposed on the control circuitry is possible. The separate VC supply input also allows the designer added flexibility in tailoring the drive voltage independent of VCC.

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Figure 21. Ramp Compensation

A simple equation can be used to calculate the amount of external ramp slope necessary to add that will achieve stability in the current loop. For the following equations, the calculated values for the application circuit in Figure 35 are also shown.

Reference

A 5.1 V bandgap reference is pinned out and is trimmed to an initial accuracy of ±1.0% at 25°C. This reference has short circuit protection and can source in excess of 10 mA for powering additional control system circuitry.

Se +

Design Considerations

Do not attempt to construct the converter on wire–wrap or plug–in prototype boards. With high frequency, high power, switching power supplies it is imperative to have separate current loops for the signal paths and for the power paths. The printed circuit layout should contain a ground plane with low current signal and high current switch and output grounds returning on separate paths back to the input filter capacitor. Shown in Figure 36 is a printed circuit layout of the application circuit. Note how the power and ground traces are run. All bypass capacitors and snubbers should be connected as close as possible to the specific part in question. The PC board lead lengths must be less than 0.5 inches for effective bypassing for snubbing.

where:

VO = NP, NS = = Ai = = L= RS =

VO L

ǒ Ǔ NS NP

(R S)A i

DC output voltage number of power transformer primary or secondary turns gain of the current sense network (see Figures 24 and 25) output inductor current sense resistance

For the application circuit: S e +

ǒǓ

5 2 (0.3)(0.55) 1.8 µ 8

= 0.115 V/ms

Instabilities

In current mode control, an instability can be encountered at any given duty cycle. The instability is caused by the


MC34023, MC33023 PIN FUNCTION DESCRIPTION Pin DIP/SOIC

Function

1

Error Amp Inverting Input

2

Error Amp Noninverting Input

3

Error Amp Output

4

Clock

5

RT

The value of RT sets the charge current through timing Capacitor, CT.

6

CT

In conjunction with RT, the timing Capacitor sets the switching frequency.

7

Ramp Input

8

Soft–Start

9

Current Limit/ Shutdown

Description This pin is usually used for feedback from the output of the power supply. This pin is used to provide a reference in which an error signal can be produced on the output of the error amp. Usually this is connected to Vref, however an external reference can also be used. This pin is provided for compensating the error amp for poles and zeros encountered in the power supply system, mostly the output LC filter. This is a bidirectional pin used for synchronization.

For voltage mode operation this pin is connected to CT. For current mode operation this pin is connected through a filter to the current sensing element. A capacitor at this pin sets the Soft–Start time. This pin has two functions. First, it provides cycle–by–cycle current limiting. Second, if the current is excessive, this pin will reinitiate a Soft–Start cycle.

10

Ground

11

Current Limit Reference Input

This pin is the ground for the control circuitry.

12

Power Ground

13

VC

14

Output

15

VCC

This pin is the positive supply of the control IC.

16

Vref

This is a 5.1 V reference. It is usually connected to the noninverting input of the error amplifier.

This pin voltage sets the threshold for cycle–by–cycle current limiting. This is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. This is a separate power source connection for the outputs that is connected back to the power source input. With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. This is a high current totem pole output.

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In voltage mode operation, the control range on the output of the Error Amplifier from 0% to 90% duty cycle is from 2.25 V to 4.05 V.

7

In current mode control, an RC filter should be placed at the ramp input to filter the leading edge spike caused by turn–on of a power MOSFET.

Figure 22. Voltage Mode Operation

Figure 23. Current Mode Operation


MC34023, MC33023

The addition of an RC filter will eliminate instability caused by the leading edge spike on the current waveform. This sense signal can also be used at the ramp input pin for current mode control. For ramp compensation it is necessary to know the gain of the current feedback loop. If a transformer is used, the gain can be calculated by:

A

i

+

2

+ 3

+ 3

The addition of an RC filter will eliminate instability caused by the leading edge spike on the current waveform. This sense signal can also be used at the ramp input pin for current mode control. For ramp compensation it is necessary to know the gain of the current feedback loop. The gain can be calculated by:

R Sense turns ratio

A

Figure 24. Resistive Current Sensing

i

Rw turns ratio

+

Figure 25. Primary Side Current Sensing

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This method of slope compensation is easy to implement, however, it is noise sensitive. Capacitor C1 provides AC coupling. The oscillator signal is added to the current signal by a voltage divider consisting of resistors R1 and R2.

Figure 26A. Slope Compensation (Noise Sensitive)

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When only one output is used, this method of slope compensation can be used and it is relatively noise immune. Resistor RM and capacitor CM provide the added slope necessary. By choosing RM and CM with a larger time constant than the switching frequency, you can assume that its charge is linear. First choose CM, then RM can be adjusted to achieve the required slope. The diode provides a reset pulse at the ramp input at the end of every cycle. The charge current IM can be calculated by IM = CMSe. Then RM can be calculated by RM = VCC/IM.

Figure 26B. Slope Compensation (Noise Immune)


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Additional dead time can be added by the addition of a dead time resistor from Vref to CT. See text on Oscillator section for more information.

The sync pulse fed into the clock pin must be at least 3.9 V. RT and CT need to be set 10% slower than the sync frequency. This circuit is also used in Voltage Mode operation for master/slave operation. The clock signal would be coming from the master which is set at the desired operating frequency, while the slave is set 10% slower.

Figure 27. Dead Time Addition

Figure 28. External Clock Synchronization

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Condition

Result

Line Regulation

V in = 40 V to 56 V, I O = 7.5A

14 mV = ± 0.275%

Load Regulation

V in = 48 V, IO = 4.0 A to 7.5 A

54 mV = ± 1.0%

Output Ripple

V in = 48 V, IO = 7.5 A

10 mVp–p

Efficiency

V in = 48 V, IO = 7.5 A

69.8%

MC34023, MC33023

MBR 2535CTI

1N5819

1N5819

+10

1000 pF

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100 pF

100 pF

1500 pF

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MBR 2535CTI

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CS51220 is a single output PWM Controller with switching frequency up to 500 kHz. The feed forward voltage mode control provides excellent line regulation for wide input range. This PWM controller has a synchronization output allowing programmable phase delay. For overcurrent protection, the “soft hiccup” technique effectively limits the output current with maximum flexibility. In addition, this device includes such features as: soft start, pulse–by–pulse current limit, programmable foldback current limit, volt–second clamping, maximum duty cycle, overvoltage and undervoltage protection, and synchronization input. The CS51220 is available in 16 SO narrow surface mount package.

1 SO–16 D SUFFIX CASE 751B

PIN CONNECTIONS AND MARKING DIAGRAM 1 VO GND VCC VREF ISET ISENSE OV UV

A WL, L YY, Y WW, W

16 CS51220 AWLYWW

Features Constant Frequency Feed Forward Voltage Mode Control Programmable Pulse by Pulse Overcurrent Limit Programmable Foldback Overcurrent Limit with Delay Soft Hiccup Overcurrent Protection with Programmable Foldback Frequency Synchronization Output with Programmable Phase Delay Synchronization Input to Higher or Lower Frequency Direct Connection to External Opto Isolators Logic Gate Output Signal Accurate Volt–Second Clamping Programmable Soft Start Logic Input to Disable IC Line Overvoltage and Undervoltage Monitoring 3.3 V 3% Reference Voltage Output

• • • • • • • • • • • • •

16

SYNCO VSD SS COMP FF DISABLE SYNCI CT





1695

Package

Shipping

CS51220ED16

SO–16

48 Units/Rail

CS51220EDR16

SO–16

2500 Tape & Reel


36–72 V

1.0 µH

C3 1.5 µF 100 V

C1 0.2 µF 100 V

C5

C12

C6 0.1 µF

R8 64.9 k

CT VSD

OV

6.8 µH

T2 R23 10

C17 330 µF

20:5

ISENSE CS51220

VREF

C8 390 pF

70:1

VCC

ISET UV

R6 7.5 k

D5B MBRB2535CTL

U1

FF R7 150 k

L1

R14 R15 36 10 k

VO GND

D5A MBRB2535CTL C18 330 µF

C12 680 pF

VORTN

SS SYNCI U4

SYNCO C10 0.1 µF

COMP DISABLE

C7 1000 pF

VDD INA NC GND

ENABLE SYNC OUT SYNC IN

R16 10

VDD OUT OUT GND

Q1 MTB20N20E

R21 40.2 k C13 100 pF 200 V

R9 R11 510 k 510 k

C15

R20 2.21 k

R10 15 k

R17 182

R12 11.8 k

C9 1000 pF

2.0 k

R23 220

R19 3.92 k

0.022 µF C14

100 pF

C11 1.0 µF

R14

VOUT 3.3 V @ 5.0 A

R24 3.3 k

U2 MOC213

R18 1.0 K

U3 TLV431ASNT1

R22 24.3 k

CS51220

1696

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Figure 1. Application Diagram, 48 V to 3.3 V Converter

0.1 µF

T1

D4

100 pF

D1 9.1 V MMSZ5239B

R5 10 k

R13 100

D2 15 V MMSZ5245B

C4 470 pF

10

MMSD4148T1

Q2 MMFT1N10E C2 0.1 µF 500 V

MMSD4148T1

R1 100 k

R2 174 k

GND

R4

NCP4414

L2 VIN

R3 10

D3


Value

Unit

150

°C

–65 to +150

°C


2.0

kV

Thermal Resistance, Junction–to–Case, RΘJC

28

°C/W

Thermal Resistance, Junction–to–Ambient, RΘJA

115

°C/W

230 peak

°C

Operating Junction Temperature, TJ Storage Temperature Range, TS

Lead Temperature Soldering: 1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed.



Pin Symbol

VMAX

VMIN

ISOURCE

ISINK

Gate Logic Output

VO

20 V

–0.3 V

100 mA

100 mA

Current Sense Input

ISENSE

6.0 V

–0.3 V

10 mA

10 mA

Timing Capacitor

CT

6.0 V

–0.3 V

10 mA

10 mA

Feed Forward

FF

6.0 V

–0.3 V

10 mA

100 mA

Error Amp Output

COMP

6.0 V

–0.3 V

10 mA

10 mA

Feedback Voltage

VFB

6.0 V

–0.3 V

10 mA

10 mA

Sync Input

SYNCI

20 V

–0.3 V

10 mA

10 mA

Power Down Input

DISABLE

20 V

–0.3 V

10 mA

10 mA

Undervoltage

UV

6.0 V

–0.3 V

10 mA

10 mA

Overvoltage

OV

6.0 V

–0.3 V

10 mA

10 mA

Current Set

ISET

6.0 V

–0.3 V

10 mA

10 mA

Soft Start

SS

6.0 V

–0.3 V

10 mA

10 mA

Power Supply

VCC

20 V

–0.3 V

10 mA

50 mA

Sync Output

SYNCO

20 V

–0.3 V

100 mA

100 mA

Reference Voltage

VREF

6.0 V

–0.3 V

Internally Limited

10 mA

Sync Delay

VSD

6.0 V

–0.3 V

1.0 mA

1.0 mA

Ground

GND

N/A

N/A

50 mA

N/A


CS51220 ELECTRICAL CHARACTERISTICS (–40°C < TA < 85°C; –40°C < TJ < 125°C; 4.7 V < VCC < 16 V; CT = 390 pF; unless otherwise specified.) Test Conditions

Min

Typ

Max

Unit

Start Threshold

–

4.0

4.4

4.7

V

Stop Threshold

–

3.3

3.8

4.1

V

400

600

1000

mV

Characteristic Supply Voltage/Current

Hysteresis

Start – Stop

ICC @ Startup

VCC < UVL Start Threshold

–

–

500

µA

ICC Operating, Low VCC

4.7 V < VCC < 10 V

–

–

7.5

mA

ICC Operating, High VCC

10 V < VCC < 16 V

–

–

9.0

mA

3.2

3.3

3.4

V

Reference Voltage Total Accuracy

0 mA < IREF < 2.0 mA

Line Regulation

IREF = 2.0 mA

–

6.0

20

mV

Load Regulation

0 mA < IREF < 2.0 mA, VCC = 8.0 V

–

6.0

15

mV

Operating Life Shift

T = 1000 Hrs., Note 2

–

4.0

20

mV

Fault Voltage

–

2.8

2.95

3.1

V

VREF OK Voltage

–

2.9

3.05

3.2

V

VREF OK Hysteresis

–

50

100

150

mV

2.0

25

65

mA

223

266

309

kHz

Current Limit

VREF = 2.5 V

Oscillator Frequency Accuracy

–


Note 2

–

8.0

–

%

Max Frequency

Note 2

500

–

–

kHz

80

85

90

%

Duty Cycle

–

Peak Voltage

Note 2

1.9

2.0

2.1

V

Valley Voltage

Note 2

0.85

0.90

0.98

V

Discharge Current

VCT = 1.5 V

0.70

0.85

1.05

mA

Charge Current

VCT = 1.5 V

127

150

183

µA

Synchronization SYNCI Input Threshold

fSYNC = 500 kHz

1.0

2.0

3.0

V

SYNCI Input Resistance

VSYNC = 0.5

50

150

250

kΩ

Minimum Sync Frequency

Reduction of nominal frequency.

25

–

–

%

–

–

200

ns

5.0

6.5

7.5

V

Minimum Input Sync Pulse Width

–

SYNCO Output High

RSYNCO = 5.0 k, VCC = 8.0 V

SYNCO Output Low

Sink 1.0 mA, VSD = 2.5 V

–

0.2

0.4

V

SYNCO Delay Time

VCT = 1.5 V, Toggle VSD

100

200

300

ns



CS51220 ELECTRICAL CHARACTERISTICS (continued) (–40°C < TA < 85°C; –40°C < TJ < 125°C; 4.7 V < VCC < 16 V; CT = 390 pF; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

Output (continued) High Saturation Voltage

VCC – VO, VCC = 10 V, ISOURCE = 100 µA

–

1.4

2.0

V

Low Saturation Voltage

VO – GND, ISINK = 100 µA

–

0.7

1.0

V

Pull Down Resistance

ISINK = 100 µA

25

50

75

kΩ

Rise Time

VCC = 10 V, 1.0 V < VO < 6.0 V; 50 pF load

–

35

80

ns

Fall Time

VCC = 10 V, 1.0 V < VO < 6.0 V; 50 pF load

–

25

50

ns

Feed Forward Discharge Voltage

IFF = 2.0 mA

0.25

0.35

0.45

V

Discharge Current

FF = 1.0 V

2.0

10

30

mA

FF to VO Delay

Connect VO to FF, Measure min. pulse width.

50

75

150

ns

–

1.15

1.3

1.45

V

0.8 1.4

1.4 1.6

1.7 1.7

V V

180

200

215

mV

FF Clamp Voltage COMP Switch Off Voltage

VFF = 0.2 V, Ramp down VCOMP VFF = 0.2 V, Ramp down VCOMP –40°C

Overcurrent Protection –

Overcurrent Comparator DC Offset ISENSE Attenuation

∆VISET/∆VISENSE

0.9

0.94

0.98

V/V

ISENSE Input Resistance

∆VISENSE = 0 V

40

82

150

kΩ

ISENSE to GATE Delay

VISET = 0.5 V

50

100

175

ns

ISET Foldback Sink Current

ISET = 0.5 V, SS = 1.5 V and ISENSE = 0.5 V

12

15

18

µA

Overvoltage Threshold

OV pin increasing

1.9

2.0

2.1

V

OV Hysteresis Current

OV = 2.15 V

10

12.5

15

µA

Undervoltage Threshold

UV pin decreasing

0.95

1.00

1.05

V

25

75

125

mV

External Voltage Monitors

UV Hysteresis

–

Soft Start Charge Current

SS = 1.5 V

35

50

65

µA

Discharge Current

SS = 1.5 V, UV = 1.5 V

4.0

5.0

7.0

µA

OC Delay Discharge Current

SS = 2.85 V, ISET = 0.5, ISENSE = 0.5 V

35

50

65

µA

SS Clamp Voltage

–

2.7

2.9

3.1

V

Discharge Voltage

–

0.25

0.3

0.35

V

–

0.1

0.2

V

–

0.08

0.1

0.12

V

–

1.0

2.0

3.0

V

Soft Start Fault Voltage

OV = 2.5 V or UV = 0.85 V

Hiccup Delay Discharge Voltage Disable DISABLE Input Threshold DISABLE Input Resistance

VDISABLE = 0.5 V

50

150

250

kΩ

DISABLE Operation Current, Low VCC

4.7 V < VCC < 10 V

–

–

800

µA

DISABLE Operation Current, High VCC

10 V < VCC < 16 V

–

–

1600

µA


CS51220 PACKAGE PIN DESCRIPTION PACKAGE PIN # 16 Lead SO Narrow

PIN SYMBOL

1

VO

2

GND

Ground.

3

VCC

Supply Voltage.

4

VREF

3.3 V reference voltage output.

5

ISET

Voltage at this pin sets pulse–by–pulse overcurrent threshold. When the ISENSE exceeds ISET for a sustained period of time, a sink current is generated at this pin. Along with external resistors, this current provides a foldback overcurrent threshold. The sink current is disabled periodically for restart.

6

ISENSE

7

OV

Overvoltage protection monitor.

8

UV

Undervoltage protection monitor.

9

CT

Timing capacitor CT determines oscillator frequency.

10

SYNCI

11

DISABLE

12

FF

13

COMP

14

SS

A capacitor is connected to this pin for Soft Start and soft hiccup timing.

15

VSD

The voltage at this pin programs the delay of the SYNCO output in reference to the internal oscillator.

16

SYNCO

FUNCTION Logic output connecting to external gate driver.

Current sense input for overcurrent protection.

By applying sync pulses to this pin, the IC can be synchronized to frequencies ranging from 25% slower to several times faster than the internal oscillator frequency. Disable mode input pin. A voltage greater than 3.0 V turns off the whole IC. Feed forward input for PWM ramp. This pin allows external connection to make the ramp adjustable to the input line. This pin carries feedback error signal from an external amplifier. Internally, it connects to the PWM controller.

Sync output.


CS51220 . %

VCC

UVL Comparator VREF = 3.3 V

VREF

+ –

. VREF COMP

DISABLE X0.94 ISENSE

. ILIM %

–+

200 mV ISET

Ifoldback COMP

Charge

%

SS SS

SS Clamp

Soft Hiccup

SS low

Discharge

SS low

SS CLK

R Q Fault Latch Q S SET DOMINANT

GND % .

FF

Off

SS Discharge

OC

1.3 V SS

MIN

3.1 V

PWM COMP

% .

0.3 V

SS COMP

%

2.0 V

.

OV

OV COMP % .

SYNCO

UV 1.0 V

UV COMP

VSD S Q

SYNCI OSC CT

R RESET DOMINANT



VO

CS51220 APPLICATIONS INFORMATION THEORY OF OPERATION VOUT

Feed Forward Voltage Mode Control

COMP

Conventional voltage mode control uses a fixed ramp signal for pulse width modulation, typically utilizing the oscillator output as the ramp signal. Since the only feedback signal comes from the output, this results in inferior line regulation and audio susceptibility. A significant improvement in line regulation and line transient response can be achieved using Feed Forward Voltage Mode Control, implemented using the CS51220 controller. The enhancement comes from generating the ramp signal using a pull–up resistor from the FF pin to the line voltage and a capacitor to ground. The slope of the ramp then depends on the line voltage. At the start of each switch cycle, the capacitor connected to the FF pin is charged through the resistor connected to the input voltage. Meanwhile, the VO pin goes high to turn on a power mosfet through an external gate driver. When the rising FF pin exceeds the COMP input pin, as driven through the regulation feedback loop, VO goes low and turns off the external switch. Simultaneously, the FF capacitor is quickly discharged and set for the next switching cycle. Overall, both input and output voltages control the dynamics of the duty cycle. As illustrated in Figure 3, with a fixed input voltage the output voltage is regulated solely by the error amplifier. For example, an elevated output voltage pulls down the COMP pin through an external error amplifier. This in turn causes duty cycle to decrease. On the another hand, if the input voltage varies, the slope of the FF pin ramp reacts correspondingly and immediately. As an example shown in Figure 4, when the input voltage goes up, the slope of the ramp signal increases, which reduces duty cycle and counteracts the change. For line variations, feed forward control requires less response from the error amplifier, which improves the transient speed and DC regulation.

FF VIN CT VO

Figure 3. Pulse Width Modulated by the Output Voltage with a Constant Input Voltage

VIN COMP

FF VOUT CT VO

Figure 4. Pulse Width Modulated by the Input Voltage with a Constant Output Voltage

The feed forward feature can also be employed for volt–second clamp, which limits the maximum product of input voltage and switch on time. This clamp is used in circuits, such as forward and flyback converters, to prevent the transformer from saturating. Calculations used in the design of the volt–second clamp are presented in the Design Guidelines section on page 1706.


CS51220 VCC Power Up and Fault Conditions

resistance to the ISET pin. However with normal pulse–by–pulse current limit, the secondary currents during short circuits may be several times the maximum output current. Soft hiccup limit can be obtained by setting the ISET resistor values for a higher thevenin resistance. During overcurrent conditions, the ISET level will fold back, after a short delay, to reduce the pulse by pulse threshold. If desired, the short circuit current can be chosen to be equal to or even less than the maximum output current. During soft hiccup the circuit will periodically disable the foldback and attempt to restart. Hard hiccup limit can be obtained by setting the ISET resistor values so that the ISET pin is held below 200 mV during foldback. During overcurrent conditions, the ISET level will fold back, after a short delay, preventing any gate pulses. When the SS capacitor is completely discharged, the circuit will attempt restart. This configuration provides the lowest power dissipation during short outputs. The circuit functions can be best described by discussing the block diagram and illustrations of expected waveforms. Actual waveforms, values and circuit configurations from a design will be used. The design is from the 5.0 V supply of a dual synchronized converter. The current is monitored with a voltage at the ISENSE pin. The ISENSE signal is slightly attenuated DC shifted by 200 mV, and is compared with the threshold voltage programmed by the voltage at the ISET pin. If the current signal reaches the threshold voltage, the overcurrent comparator resets the VO latch and terminates the VO pulse. The overcurrent comparator has a maximum common mode input voltage of 1.8 V. However, an ISET voltage below 1.0 V is desirable for reducing the comparator’s propagation delay. During initial turnon of the power supply, normal pulse–by–pulse overcurrent control is used to protect the power supply switches. This is accomplished by comparing the voltage at the ISENSE input to the voltage at the ISET pin and using this to limit the duty factor of VO, the gate drive signal. This current limit control is maintained until the SS voltage reaches 2.9 V.

During power up, an undervoltage lockout comparator monitors VCC and disables VREF, (which in turn disables the entire IC), until the VCC voltage reaches its start threshold. Hysteresis prevents “chattering” caused by the source impedance of the VCC supply. VREF can also be disabled using the Disable input pin, which is active high. An internal pull–down resistor ensures the IC will start up if the Disable pin is allowed to float. In VCC or Disable lockout mode, the output stage is held low by the output pull–down resistance. After VREF turns on, there are three conditions that can cause fault mode: 10. The 3.3 V VREF is below regulation, 11. The OV pin rises above overvoltage threshold, or 12. The UV pin falls below undervoltage threshold. Fault detection will cause the VO output to go low and the SS pin to discharge. The UV and OV inputs are typically used to monitor the input line voltage. The undervoltage comparator has a built–in hysteresis voltage, while the hysteresis for the OV comparator is programmable through a current sourced from the pin when above the threshold, and the equivalent external resistance. The fault condition can only be reset after the SS pin has been completely discharged and all faults have been removed. After a fault is removed or upon initial startup, the SS pin charges at a rate determined by an internal charge current and an external capacitor. The rising voltage on the SS pin will override the regulation feedback voltage on the COMP pin and clamp the duty cycle, helping to reduce any in–rush current during startup. The duration of the Soft Start is typically set with a capacitor from 0.01 µF to 0.1 µF. Overcurrent Protection

The CS51220 uses the “soft hiccup” technique to provide an adjustable and predictable overcurrent limit. By choosing external component values the designer can select pulse–by–pulse current limit, soft hiccup current limit or hard hiccup limit. Normal pulse–by–pulse current limit can be obtained by selecting the ISET resistor values for a low Thevenin


CS51220 The block diagram of the soft hiccup circuit is shown in Figure 5. When overcurrent occurs and the SS is above 2.9 V, the OC pulses set the OC latch. The output of the OC latch turns on the OC delay discharge current to ramp down the SS voltage. This SS discharge ramp down is at a rate of 50 µA while the SS voltage is above 2.8 V. The level between 2.9 V and 2.8 V is called the hiccup delay discharge voltage. The time to cross this voltage creates a short delay. This delay is useful so that a quick transient overcurrent condition can be controlled and still allow the supply to return immediately to normal operation. After reaching the hiccup delay discharge voltage, the SS current is reduced to 5.0 µA and the ISET foldback current is turned on at 15 µA. It is the ISET foldback current that adjusts the ISET level to establish a new lower ISENSE current limit level. See Figure 6 for details.

The NOOC or SS low (VSS < 0.3 V) signal can reset OC latch at any time. This event turns off ISET foldback and allows the recharging of the SS capacitor. Therefore, the IC allows the power supply to restart periodically or after the overcurrent condition is cleared. The OC latch can not be set until the SS capacitor is fully charged. To implement “hard hiccup” which disables the VO completely when the SS voltage is ramping down, select a resistor value greater than 3.3 V/ISET for R1 in Figure 6, and saturate the internal ISET current source. Since the saturation voltage is less than the DC shift applied to the ISENSE signal, the OC comparator output is always high and in turn keeps the VO low. Figure 7 demonstrates the interactions among the voltage of SS, ISET and internal signal OC. Figure 8 further describes the specifications associated with the soft hiccup. The ratio among the charge time, delay time and discharge time is given at the bottom of Figure 8.

SS + 2.9 V

– Peak COMP

OC

S

2.9 V 2.8 V

SS

SS Discharge Q

CLK

Reset Trig

SS low

N00C

0.3 V

R OC Latch

One Shot

Foldback ON

– 2.8 V

ISET

+ Delay COMP

Figure 5. The Block Diagram of the Soft Hiccup Operation OC

A circuit monitors the OC pulses. If the OC pulses cease for 50 µs, the NOt–OverCurrent (NOOC) signal is generated. This NOOC signal resets the OC Latch and allows the SS capacitor to charge back up allowing the output to reestablish regulation. For an equivalent circuit shown in Figure 6, the ISET current reduces the overcurrent threshold and sets the new threshold at VI(SET) + (3.3 * ISET

R1)

50µs

Figure 7. Illustrative Waveforms of the Soft Hiccup Operation

Charge Voltage

R2 (R1 ) R2)

Charge Current

Hiccup Delay Discharge Voltage OC Delay Dischage Current Dischage Current

VREF

Discharge Voltage R1 ISET Pin

26

1

250

Figure 8. The SS Pin Voltage Under Ramp Up and Overcurrent Condition and Associated Specifications.

R2 ISET

Figure 6. The Voltage Divider Used at the ISET Pin Allows the ISET Foldback Current to Reduce the Overcurrent Threshold


CS51220 The effect of the soft hiccup can be observed in Figure 9, which shows the output voltage as load increases. The output is maintained at the regulation value of 5.0 V until it goes into current limit. At the point of overcurrent inception (A), the current limit level changes to a lower level (B). The switchback to a lower current limit level can be seen as the bottom curve in Figure 9.

The middle trace is a digitizing ‘scope trace of the current sense line. The scope interprets the voltages as an average voltage. This voltage is actually a narrow duty cycle peak voltage representing the peak current level in the switching transistor. The actual peak voltages can be seen in the Figure 11. The peaks are 0.85 V at full load, reducing to 0.6 V peak at the reduced short circuit level. The 1.1 V peak is the full short circuit current while SS ramps back up. The 0.32 V level is the normal load resistance, while ISET is still on. The 1.0 V surge is created by ramp up into a normal 5.0 A load and followed by the 0.85 V at normal load.

6 A

Output Voltage (V)

5

Peak Detect Setting

4 3 2 1

B

0 0

2

4

6

Load Current (A)

Figure 9. Overcurrent In a 5.0 V Output Converter Using Soft Hiccup

A typical overload scenario is shown in Figure 10. The top trace is the voltage on the Soft Start (SS) pin. The initial high discharge rate can be seen transitioning to a 40 ms discharge period. During this period the ISET establishes a lower current limit level. The bottom trace shows the output current. The initial current spike is the output capacitors discharging. The next level around 4.0 A is the short circuit current level set by the ISET current. The output then turns off allowing the current to reduce to a level that does not cause overcurrent pulses. This releases the SS pin to ramp back up. During ramp up, the output is still shorted as noted by the 8.0 A current level. When SS reaches the 2.9 V level, the short is again recognized and ISET is turned back on shifting the short circuit current level.

Figure 11. Over–Load Current and ISENSE Voltage Oscillator and Synchronization

The switching frequency is programmable through a capacitor connected to the CT pin. When the CT pin voltage reaches peak voltage (2.0 V), the internal discharge current discharges the CT capacitor and VO stays low. When the CT voltage declines to valley voltage (0.9 V), the current source toggles to charge current and ramps up the CT pin. This starts a new switching cycle. The duty cycle of the oscillator determines the maximum PWM duty cycle. The switching frequency of the IC can be synchronized to an external frequency presented to the SYNCI pin. When pulses with amplitude over SYNCI input threshold are detected, the CT pin immediately ramps down the external capacitor and the VO pin is forced low. A new switching cycle begins when the CT pin reaches valley voltage. During synchronization, the oscillator charge current is reduced by 80 µA, while discharge current is increased by 80 µA. This effectively slows down the internal oscillator to avoid any race condition with the sync frequency. As a result, the sync frequency can be either higher or lower than the internal oscillator frequency. CS51220 is able to synchronize up to 500 kHz and down to 25% below CT frequency. The maximum duty cycle clamp is raised to 92% in synchronization mode. The original oscillator frequency is restored upon the removal of sync pulses.

Figure 10. Over–Load Current and Soft Start Waveforms


CS51220 The desired effect on the input ripple is illustrated in Figure 14. This is the input current for two power converters operating from a 36 V line.

Figure 12. Synchronization Input Timing

Figure 12 shows the sync input from one CS51220 into another. The delay between receiving the sync input and the start of the next switching cycle is 423 ns. This delay must be taken into account when establishing the total delay between two regulators. The SYNCO pin provides outgoing synchronization pulses whose delay can be programmed by setting the voltage on the VSD pin. The feature allows two converters to run at interleaved phases. This implementation significantly reduces the input ripple, and thus the number of input capacitors. The phase delay is achieved by turning on SYNCO output only after the CT pin voltage reaches the VSD voltage. Therefore, the phase delay varies linearly with the VSD voltage. The SYNCO output is reset during the falling edge of the CT pin. For minimum phase delay (~ 240 ns), tie the VSD pin to the ground. To entirely disable the SYNCO output, connect the VSD pin to VREF. The waveform in Figure 13 shows the CT ramp crossing the VSD voltage set at 1.41 V.

Figure 14. Input Current Ripple with Different Overlap Conditions

The top waveform in Figure 14 is the input current with the two supplies operating out of phase. The next down shows the same supplies but with both conduction times occurring simultaneously. The greatly increased ripple current can be observed. The last two waveforms are the two converters shown individually when operating out of phase. DESIGN GUIDELINES Program Volt–Second Clamp

Feed forward voltage mode control provides the volt–second clamp which clamps the product of the line voltage and switch on time. For the circuit shown in Figure 15, the charging current of the CFF can be considered as a constant current equal to VIN/RFF , provided VIN is much greater than the FF pin voltage. Then the volt–second clamp provided by CS51220 is given by VINTON(MAX) + 1.0RFFCFF VIN

RFF

FF Pin

CFF

Figure 13. Synchronization Output Timing

Figure 15. An RC Network Provides Both Volt–Second Clamp and Feed Forward Control

The delay from the point of crossing to the output of the sync signal is 240 ns. The time for the sync out voltage is measured at the +2.0 V level, which is the level that triggers the next CS51220.

Select the time constant of the FF pin RC network to provide desirable volt–second clamp.


CS51220 Program Oscillator Frequency

Synchronized Dual Converters with Soft Hiccup and Feed Forward

CS51220 requires an external capacitor to program the oscillator frequency. The internally trimmed charge/discharge current determines the maximum duty cycle. The capacitor for a required switching frequency fS can be calculated by:

The circuits shown in Figures 17 and 18 illustrate typical applications for a dual output supply using independent but synchronized converters. These circuits demonstrate the use of the soft hiccup, feed forward, volt–second control and synchronization features of the CS51220. In Figure 17, the feed forward circuit has a volt–second constant of 82 V/µs. This would limit the duty factor to 0.51 at 48 V input. With a turns ratio of 4:1 on the power transformer and 48 V input, a duty factor of 0.46 is required for 5.0 V output. This converter serves as the master synchronization generator. The voltage on the VSD pin establishes the delay as it is compared to the ramp generated on the CT pin. Adjustable synchronization allows the conduction time for the two converters to be adjusted so that they are not on at the same time. This greatly reduces the ripple current from the 48 V source. In Figure 18, the feed forward circuit has a volt–second constant of 63 V/µs. This would limit the duty factor to 0.39 at 48 V input. With a turns ratio of 4:1 on the power transformer and 48 V input, a duty factor of 0.33 is required for 3.3V output.

CT + 13400 * 95 fS

where: CT = Timing capacitance is in pF fS = Switching frequency is in kHz Figure 16 shows the relationship of CT and fS. 600 550

Frequency (kHz)

500 450 400 350 300 250 200 150 100

100

200

300

400

500

600

CT (pF)

Figure 16. Operating Frequency


VIN

TP1 GND L2 VIN

D2

R23

MMSD4148T1

10

BST1 R22 10

36–72 V

1.0 µH

R1 100 k MMSD4148T1

R6 174 k C2

Q1 MMFT1N10E C37 0.1 µF 500 V

T1

D1

0.1 µF

D3 15 V MMSZ5245BT1

C5 470 pF

R11 100

L1

R12 R10 36 10 k

C6

D5B MBRB2535CTL

70:1

100 pF

D4 9.1 V MMSZ5239BT1

R15 10

U1 FF

VCC

CT VSD ISET

C3 0.1 µF

R3 7.5 k R5 64.9 k

C4 390 pF

UV OV

TP2

ISENSE

VORTN

SYNCI SYNCO

COMP DISABLE

U4 C7 0.1 µF

VDD INA NC GND

R13 10

VDD OUT

Q2 IRF634S

OUT GND TP3

SYNC R21 511 k

R16 182

R48 3.92 k

C35 1000 pF

R14 2.0 k

C10 100 pF 200 V

10 k

TP4 R9 11.8 k

R19 40.2 k

R18

SYNC IN R8 15 k

C9 330 µF

SS

C38 1000 pF

C36 C14

0.022 µF C13 1.25 V

100 pF C18 1000 pF

VOUT 5.0 V @ 5.0 A

D5A MBRB2535CTL C12 680 pF

ENABLE1

R7 511 k

C11 330 µF

20:5

VO GND

NCP4414

VREF

R4 150 k

CS51220

R2 10 k

6.8 µH

T2

U2 MOC213

R17 1.0 K

U3 TLV431ASNT1

1000 pF

R20 13.3 k

CS51220

1708

http://onsemi.com

Figure 17. Additional Application Diagram, 5.0 V Output Converter Used As Sync Master for the Dual Converter

C1 1.5 µF 100 V

C16 0.2 µF 100 V

TP5 D6

R38

MMSD4148T1

10

BST1 36–72 V

VIN GND

C32 1.5 µF 100 V

R37 10 MMSD4148T1

R24 137 k C22

L3

R35 R36 36 10 k

0.1 µF C31 470 pF

T3

D7

C23

D8B MBRB2535CTL

70:1

100 pF

R39 10

U5

CT VSD ISET

C19 0.1 µF

UV

R26 5.11 k R28 64.9 k

C20 390 pF

VCC ISENSE

TP6

GND SS

C27 330 µF

VORTN

SYNCI U4

OV SYNCO COMP DISABLE

C21 0.1 µF

C39 1000 pF

VDD INA NC GND

SYNC OUT

R40 10

VDD OUT

Q3 MTB20N20E

R44 40.2 k

OUT GND TP7

SYNC

R31 511 k

C28 100 pF 200 V

C29

R43 2.21 k

R30 15 k

R41 182

R32 11.8 k C33 1000 pF

C24 1.0 µF

R33 TP8 2.0 k

R49 3.3 k

VOUT 3.3 V @ 5.0 A

D8A MBRB2535CTL C25 680 pF

ENABLE2

R29 511 k

C26 330 µF

20:5

VO

NCP4414

FF VREF

R27 150 k

CS51220

R25 10 k

6.8 µH

T4

R48 220

R47 2.21 k

0.022 µF C30

100 pF U6 MOC213

R42 1.0 K

U7 TLV431ASNT1

R45 24.3 k

CS51220

1709

http://onsemi.com

Figure 18. Additional Application Diagram, 3.3 V Output Converter Synchronized to the 5.0 V Converter

R34 100

28 5 5 ) 81) The NCP1560 PWM controller contains all of the features and flexibility needed to implement voltage–mode control for modern high performance power converters. This device cost effectively reduces system part count with the inclusion of a high–voltage start–up regulator that operates over a wide input range of 33 V to 150 V. The NCP1560 provides two control outputs, OUT1 which controls the main PWM switch and OUT2 with adjustable over–lap delay, which can control a synchronous rectifier. Other distinctive features include: two mode over–current protection, line under/over voltage lockout, fast line feed–forward, soft–start and a maximum duty cycle clamp. Features

• • • • • • • • • •

http://onsemi.com MARKING DIAGRAM 16 SO–16 D SUFFIX CASE 751B

16 1

1 A WL Y WW

Internal High Voltage Start–up Regulator Dual Control Outputs with Adjustable Over–Lap Delay Single Resistor Oscillator Frequency Setting Fast Line Feed–Forward Line Under/Over Voltage Lockout Dual Mode Over–Current Protection Programmable Maximum Duty Cycle Control Maximum Duty Cycle Proportional to Line Voltage Programmable Soft–Start Precision Reference

NCP1560DR2 AWLYWW


ORDERING INFORMATION Device NCP1560DR2

Package

Shipping

SO–16

2500 Units/Reel


• • • • •

Telecommunication Power Converters Industrial Power Converters High Voltage Power Modules +42 V Automotive Systems Control Driven Synchronous Rectifier Power Converters

This document contains information on a new product. Specifications and information herein are subject to change without notice.



1710


NCP1560

Vin Vaux

Start–up Regulator

REF

5 V REF

Thermal Shutdown

GND

UV_OV Protection CS C_SKIP_SET RT OSC FF_SET TP_Ramp

Td Set

Vea Modulator SS

DELAY LOGIC

Max Duty Set



OUT1 OUT2

NCP1560 1 Vin Disable

12 mA AUX 16

+

Vout

OUT

7 11

CAUX 11 V/7 V 14

–

Disable_Vref

I

Vaux

DIS

Voltage Reference

11

One Shot Pulse O (250 ns)

5 V_Ref

RD

GND Thermal Shutdown Vin

Set

1.49 V Disable_Vref

+ –

UV_OV 2

15

S Dominant Reset Q Latch

Td_Set

R STOP

+ – Level Shift

3.60 V

C_Skip_Set 6

Disable_ss

Cycle Skip Timer

S Dominant Reset Q Latch

CSKIP Clock 5 + –

CS

DIS Delay Logic

R

0.6 V + – 0.5 V

SS

9

6 µA

Disable_ss

Soft Start – +

CSS

Td

STOP

OUT1 Vin RFF FF_Set

4

RT

7

RT

OUT2

Clock OSC_Ramp Oscillator

FF_Ramp

3 TP_Ramp

Buffer

VEA 10

+ – 2V

20 K

VREF RMDP

+ – 8

Max_Duty Set RP

PWM

RP

RMDP

Max Duty %

0 Open Open

Open Open 100 K

60 80 X100

Max Duty 60 – 80%

Figure 2. NCP1560 Block Diagram


Td

OUT1 OUT2

NCP1560 PIN DESCRIPTION Pin

Name

1

Vin

2

UV_OV

3

TP_Ramp

4

FF_SET

5

CS

6

C_SKIP_SET

7

RT

8

MAX_DUTY_SET

9

Description

Application Information

Source Input Voltage

Input range: 33 V to 150 V.

Input Undervoltage and Overvoltage shutdown.

An external divider from the power converter source input must be scaled >1.49 volts and < 3.60 volts over the operational range.

Test point provided for the Feed Forward Ramp signal.

Internally this signal is compared to Vea.

An external resistor between Vin and this pin adjusts the amplitude of the FF_Ramp in proportion to Vin and R.

By varying the PWM ramp amplitude in proportion to the line voltage changes in loop bandwidth resulting from line voltage changes are eliminated.

Current Sense input

If CS exceeds 0.5 volt the outputs will go into a Cycle by Cycle current limit. If CS exceeds 0.6 volts the outputs will be disabled for a period determined by the Current Sense Fault Timer. A softstart will follow at the conclusion of the fault timer.

An external capacitor sets the shutdown period after 0.6 V CS event.

An external capacitor sets the shutdown period. Range: 68 pF = 12 s, 6800 pF = 1.2 ms

A single external resistor between this pin and GND sets the fixed oscillator frequency.

Resistance Range 68 K = 500 KHz 390 K = 100 KHz

An external resistor between this pin and GND sets the maximum allowable Duty cycle.

Resistance Range 0 Ohms = 60% Open = 80% given the FF_Ramp of 2.0 V peak (low line).

SS

Softstart control

An external capacitor and the internal 6.0 A current source, set the softstart ramp. The capacitor voltage sets a maximum duty cycle clamp from 0 to 2.0 volts (0 to 100% Duty).

10

Vea

Input from an external error amplifier.

There is no error amplifier included within this controller. The error amplifier is typically secondary side referenced while the controller is primary side referenced.

11

5.0 V_REF

Precision 5.0 volt reference output.

Maximum output current: 10 mA.

12

Td_Set

An external resistor between Vref and this pin sets the leading edge and trailing edge time delay between OUT1 and OUT2.

Time delay (Td) Rd open = 250 nS (Max Delay) Rd (60 K) = 25 nS (Min Delay)

13

OUT2

Output of the PWM controller with leading edge and a trailing edge time delay of (Td).

OUT2 can be used to drive a synchronous rectifier.

14

GND

Return

15

OUT1

Output of the PWM controller.

OUT1 main PWM output.

16

AUX

Auxiliary bias power. Upon turn–on an internal current source supplies bias power. An external slave winding then continues supplying bias power.

An internal current source supplies 12 mA until Vaux reaches 11 volts. An external capacitor is required to holdup Vaux above 7.0 volts while the converter starts. Typically an external slave winding then provides power to the control circuits.


NCP1560 MAXIMUM RATINGS (Notes 1 & 2) Rating

Symbol

Value

Unit

Vin

150

V

Vaux

16

V

–

–

V

IREF

10

mA

IOUT1, IOUT2

20

mA


TJ

–40 to +140

C


Tstg

–55 to +150

C

Power Dissipation at TA = 25°C

PD

0.88

W

RθJA

130

C/W

Vin to GND Vaux to GND All Other Inputs to GND 5.0 V Reference Output Current OUT1, OUT2 Output Current

Thermal Resistance, Junction to Case

1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. 2. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL–STD–883, Method 3015. Machine Model Method 200 V.

ELECTRICAL CHARACTERISTICS (TA = Tlow to Thigh, Vin = 48 V, Vaux = 12 V, RT = 100 K, Cft = 6800 pF, Rd = 60 K, RFF = 464 K) Min

Typ

Max

Unit

4.9

5.0

5.1

V

Iref = 0 to 10 mA

–

50

–

mV

Vaux t 11 V*

11

12

–

mA

Vaux Current Source Disable

–

11

–

V

Vaux Undervoltage Lockout Voltage

–

7.0

–

V

Characteristic

Symbol

Conditions

Reference REF Output Voltage REF Voltage Regulation

VREF

Iref = 0 mA

Vaux Supply Vaux Current Source

Startup Regulator Leakage

TA = 25°C, Vin = 150 V

–

–

50

A

Supply Current (laux)

Vea = 0 V

–

–

5.0

mA

Shutdown Current (laux)

Vuv/ov = 0 V

–

–

2.5

mA

Undervoltage Shutdown (increasing)

1.43

1.49

1.55

V

Undervoltage Shutdown Hysteresis

–

0.16

–

V

Overvoltage Shutdown (increasing)

3.46

3.60

3.74

V

Overvoltage Shutdown Hysteresis

–

0.16

–

V

–

–

150

nS

Cycle–by–Cycle Threshold Voltage

0.47

0.5

0.53

V

Cycle Skip Threshold Voltage

0.57

0.6

0.63

V

–

1.2

–

mS

Input UV/OV Shutdown

Current Limit ILIM Delay to Output (TA = 25C)

Cycle Skip Program Time Delay

*Non–continuous rating. Vaux current source will supply 12 mA over the input voltage range of 33 V to 150 V. However package thermal restrictions apply.


NCP1560 ELECTRICAL CHARACTERISTICS (continued) (TA = Tlow to Thigh, Vin = 48 V, Vaux = 12 V, RT = 100 K, Cft = 6800 pF, Rd = 60 K, RFF = 464 K) Min

Typ

Max

Unit

5.0

6.0

7.0

A

–

10

–

mA

285

300

315

KHz

Input Bias Current

–

1.0

–

nA

Delay to Output (TA = 25C)

–

–

200

nS

–

2.7

–

V

Characteristic

Symbol

Conditions

Softstart Charge Current Discharge Current Oscillator Frequency PWM Comparator

Feedforward FF Ramp Amplitude Max Duty Program Max Duty 60%

Rp = 0 Ohms, Vin = 36 V

57

60

63

%

Max Duty 80%

Rp = open, Vin = 36 V

76

80

84

%

Output High Saturation

Iout = 10 mA

–

11.4

–

V

Output Low Saturation

Iout = –10 mA

–

0.25

–

V

Rise Time

CL = 100 pF

–

20

–

nS

Fall Time

CL = 100 pF

–

12

–

nS

Output Section

Time Delay Set Time Delay Max

Td(max)

Rd = open, TA = 25°C

225

250

275

nS

Time Delay Min

Td(min)

Rd = 60 K, TA = 25°C

20

25

30

nS

–

150

–

°C

Thermal Shutdown Thermal Shutdown Temperature

Tsd


NCP1560 DETAILED OPERATING DESCRIPTION Reference The NCP1560 provides a precision reference output of 5 volts. This output should be locally bypassed with a 0.1 F ceramic capacitor. The maximum current available from this output is 10 mA.

The NCP1560 PWM controller contains all of the features and flexibility needed for implementation of voltage–mode control for modern high performance power converters. This device cost effectively reduces system part count with the inclusion of a high–voltage start–up regulator. The NCP1560 provides two control outputs, OUT1 which controls the main PWM switch and OUT2 with adjustable over–lap delay, which can control a synchronous rectifier switch. Other distinctive features include: two mode over–current protection, line under/over voltage lockout, fast line feed–forward, soft–start and a maximum duty cycle clamp. The Functional Block Diagram is shown in Figure 1. The NCP1560 is designed for Voltage–Mode Control converters. The features included in the NCP1560 enable all of the advantages of Current–Mode Control, fast line feed–forward, and cycle by cycle current limit. It eliminates the disadvantages of low power jitter, slope compensation and noise susceptibility. Finally the dual outputs of the NCP1560 allow for optimum control of a synchronous rectifier switch.

Current Limit The NCP1560 contains two levels of over current protection. If the voltage on the CS pin exceeds 0.5 volt the present cycle is terminated and the outputs are disabled. If the voltage on the CS pin exceeds 0.6 volts, the controller will disable the outputs, enable the Cycle Skip Timer and discharge the softstart capacitor. The outputs will remain disabled until the Cycle Skip Timer completes, then a softstart will commence. The duration of the Current Sense Fault Timer is set by an external capacitor. The range of capacitor (time set) is 68 pF (12 s) to 6800 pF (1.2 mS). A complete softstart will commence after the current sense fault timer completes. Oscillator and Ramp Feed–Forward The NCP1560 oscillator is set by a single external resistor connected between the RT pin and return. Internally there are two ramp voltages generated by the oscillator. The OSC_Ramp is a fixed amplitude ramp of 0 to 1.5 volts. This ramp is used for the softstart comparator and as a basis for the Feed Forward ramp (FF_Ramp). The amplitude of the FF ramp varies in proportion to the voltage on the FF_SET pin. The FF_Ramp is used for the PWM comparator and the Max Duty Cycle comparator. The amplitude of the FF_Ramp is normally set to vary from 1.5 to 3.0 volts for a corresponding 2:1 change in line voltage. An external resistor between the FF_SET pin and the line sets the proportion to which the ramp amplitude changes with line voltage.

High Voltage Start–up Regulator The NCP1560 contains an internal high voltage current source. This current source is set to 12 mA. When the line voltage is in range, the current source is enabled and sources current into an external capacitor connected to the Vaux pin. When the voltage on the Vaux pin reaches 11 V the controller outputs are enabled and the internal current source is disabled. The Vaux voltage will then transition to the converter self bias voltage. The start–up regulator will remain off until the Vaux voltage falls below 7.0 V. At that time the outputs will be disabled until the Vaux pin again reaches 11 V. The external Vaux capacitor must be sized such that the self–bias will maintain a Vaux voltage greater than 7.0 V during initial start–up. During a fault mode when the converter self bias is inactive, external current draw on the Vaux line should be limited as to not exceed the maximum power dissipation of the controller.

Maximum Duty Cycle A dedicated internal comparator limits the maximum output duty cycle. The Feedforward ramp is compared to a fixed voltage configured by the Max Duty Cycle pin. Since the amplitude of the Feedforward ramp increases with increasing line voltage the maximum duty cycle will then decrease with increasing line voltage, which is a desirable feature. If the Max Duty Cycle pin is left open the voltage present at the Max Duty Cycle comparator will be 1.6 volts, which will correspond to a maximum duty cycle of 80% when the FF_Ramp amplitude is at 2.0 volts. If the Max Duty Cycle pin is shorted to return the voltage present at the Max Duty Cycle comparator will be 1.2 volts, which will correspond to a maximum duty cycle of 60% when the FF_Ramp amplitude is 2.0 volts. If the Max Duty Cycle pin is connected to Vref, the maximum duty cycle feature will be disabled and the maximum duty cycle will approach 100%. If the FF_Ramp amplitude increases to 4.0 volts as a result of the line increasing the maximum duty cycle will

Input Under/Over Voltage Shutdown The NCP1560 contains a line under/over voltage shut down circuit. An external voltage divider sets the operational range of the converter. The divider must be set for a voltage at the under/over voltage pin to be greater than 1.49 V and less than 3.60 V. If the Under voltage threshold is not met, all functions of the controller are disabled except the bias (Vaux) regulator and the controller will be in a low power state, < 500 A. If the Over voltage threshold is exceeded, OUT1 and OUT2 will be disabled and the softstart capacitor will be discharged. The under/over voltage pin can also be used to implement a remote enable/disable function. By shorting the over/under pin to ground, the converter can be disabled. The internal bias regulator will continue to operate varying between 7.0 and 11 volts. All other functions will be disabled.


NCP1560 OUT1, OUT2 and Time Delay The NCP1560 provides two in–phase outputs, OUT1 and OUT2. However, OUT2 always precedes OUT1 at any low to high transition and OUT1 always precedes OUT2 at any high to low transition. The leading and trailing time delays are equal and set by the Time Delay pin. An open circuit on the Time Delay pin will cause the maximum delay of 500 nS. A 60 K resistor between the Time Delay pin and 5.0 V_REF will cause the minimum delay of 50 nS. Generally, OUT1 controls the main switching element. OUT2 once inverted can drive the free–wheeling synchronous rectifier switching element.

then decrease to 40% or 30%, respectively, depending upon the Maximum Duty Set pin configuration. PWM Comparator The PWM comparator compares the Feedforward ramp to the voltage presented at the Vea pin. There is a 0.65 V (diode) offset between the Vea pin and the PWM comparator. The output of an external error amplifier generally drives the Vea pin. The comparator polarity is such that 0.65 volts or less on the Vea pin will cause a Zero duty cycle. Softstart The softstart feature allows the converter to gradually reach the initial steady state operating point, thus reducing start–up stresses and surges. Upon power on, a 6.0 A current is sourced out of the softstart pin into an external capacitor. The capacitor voltage will begin to ramp up. The voltage on the softstart pin is compared to a 2.0 V Oscillator Ramp signal and will act to reduce the maximum duty cycle until the capacitor voltage ramps up. In the event of a fault, line under/over voltage or current cycle skip, the softstart pin will discharge the external capacitor and disable the output drivers. When the fault condition is no longer present a softstart will be exercised again.

Thermal Protection Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction temperature is exceeded. When activated, typically at 150 degrees Celsius, the controller is forced into a low power reset state, disabling the output drivers and the bias regulator. This feature is provided to prevent catastrophic failures from accidental device overheating.


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• • • • • • • •

Complete Pulse Width Modulation Control Circuitry On–Chip Oscillator with Master or Slave Operation On–Chip Error Amplifiers On–Chip 5.0 V Reference Adjustable Deadtime Control Uncommitted Output Transistors Rated to 500 mA Source or Sink Output Control for Push–Pull or Single–Ended Operation Undervoltage Lockout

http://onsemi.com MARKING DIAGRAMS 16 SO–16 D SUFFIX CASE 751B

16 1

MAXIMUM RATINGS (Full operating ambient temperature range applies,

1

unless otherwise noted.) Rating

Symbol

TL494C

TL494I

Unit


VCC

42

V

Collector Output Voltage

VC1, VC2

42

V

Collector Output Current (Each transistor) (Note 1)

IC1, IC2

500

mA

Amplifier Input Voltage Range

VIR

–0.3 to +42

PD

1000

mW

RθJA

80

°C/W

Power Dissipation @ TA ≤ 45°C Thermal Resistance, Junction–to–Ambient

TJ

125

°C

Tstg

–55 to +125

°C

Operating Ambient Temperature Range TL494C TL494I

TA

Derating Ambient Temperature

TA

°C

45

PIN CONNECTIONS

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ORDERING INFORMATION Package

Shipping

TL494CD

SO–16

48 Units/Rail

TL494CDR2

SO–16

2500 Tape & Reel

TL494CN

PDIP–16

500 Units/Rail

TL494IN

PDIP–16

500 Units/Rail

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30''(!

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x = C or I A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week

Device

1. Maximum thermal limits must be observed.

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July, 2000 – Rev. 2

1718

Publication Order Number: TL494/D

TL494 RECOMMENDED OPERATING CONDITIONS Characteristics

Symbol

Min

Typ

Max

Unit

VCC

7.0

15

40

V

VC1, VC2

–

30

40

V

IC1, IC2

–

–

200

mA

Amplified Input Voltage

Vin

–0.3

–

VCC – 2.0

V

Current Into Feedback Terminal

lfb

–

–

0.3

mA

Reference Output Current

lref

–

–

10

mA

Power Supply Voltage Collector Output Voltage Collector Output Current (Each transistor)

Timing Resistor

RT

1.8

30

500

kΩ

Timing Capacitor

CT

0.0047

0.001

10

µF


fosc

1.0

40

200

kHz

ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 µF, RT = 12 kΩ, unless otherwise noted.) For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted. Characteristics

Symbol

Min

Typ

Max

Unit

Vref

4.75

5.0

5.25

V

Line Regulation (VCC = 7.0 V to 40 V)

Regline

–

2.0

25

mV


Regload

–

3.0

15

mV

Short Circuit Output Current (Vref = 0 V)

ISC

15

35

75

mA

Collector Off–State Current (VCC = 40 V, VCE = 40 V)

IC(off)

–

2.0

100

µA

Emitter Off–State Current VCC = 40 V, VC = 40 V, VE = 0 V)

IE(off)

–

–

–100

µA

Vsat(C) Vsat(E)

– –

1.1 1.5

1.3 2.5

IOCL IOCH

– –

10 0.2

– 3.5

– –

100 100

200 200

– –

25 40

100 100

REFERENCE SECTION Reference Voltage (IO = 1.0 mA)

OUTPUT SECTION

Collector–Emitter Saturation Voltage (Note 2) Common–Emitter (VE = 0 V, IC = 200 mA) Emitter–Follower (VC = 15 V, IE = –200 mA)

V

Output Control Pin Current Low State (VOC ≤ 0.4 V) High State (VOC = Vref) Output Voltage Rise Time Common–Emitter (See Figure 12) Emitter–Follower (See Figure 13)

tr

Output Voltage Fall Time Common–Emitter (See Figure 12) Emitter–Follower (See Figure 13)

tf

µA mA ns

ns



TL494 ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 µF, RT = 12 kΩ, unless otherwise noted.) For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted. Characteristics

Symbol

Min

Typ

Max

Unit

Input Offset Voltage (VO (Pin 3) = 2.5 V)

VIO

–

2.0

10

mV

Input Offset Current (VO (Pin 3) = 2.5 V)

IIO

–

5.0

250

nA

Input Bias Current (VO (Pin 3) = 2.5 V)

IIB

–

–0.1

–1.0

µA

ERROR AMPLIFIER SECTION

Input Common Mode Voltage Range (VCC = 40 V, TA = 25°C)

VICR

–0.3 to VCC–2.0

V

Open Loop Voltage Gain (∆VO = 3.0 V, VO = 0.5 V to 3.5 V, RL = 2.0 kΩ)

AVOL

70

95

–

dB

Unity–Gain Crossover Frequency (VO = 0.5 V to 3.5 V, RL = 2.0 kΩ)

fC–

–

350

–

kHz

Phase Margin at Unity–Gain (VO = 0.5 V to 3.5 V, RL = 2.0 kΩ)

φm

–

65

–

deg.

Common Mode Rejection Ratio (VCC = 40 V)

CMRR

65

90

–

dB

Power Supply Rejection Ratio (∆VCC = 33 V, VO = 2.5 V, RL = 2.0 kΩ)

PSRR

–

100

–

dB

Output Sink Current (VO (Pin 3) = 0.7 V)

IO–

0.3

0.7

–

mA

Output Source Current (VO (Pin 3) = 3.5 V)

IO+

2.0

–4.0

–

mA

VTH

–

2.5

4.5

V

II–

0.3

0.7

–

mA

Input Bias Current (Pin 4) (VPin 4 = 0 V to 5.25 V)

IIB (DT)

–

–2.0

–10

µA

Maximum Duty Cycle, Each Output, Push–Pull Mode (VPin 4 = 0 V, CT = 0.01 µF, RT = 12 kΩ) (VPin 4 = 0 V, CT = 0.001 µF, RT = 30 kΩ)

DCmax 45 –

48 45

50 50

– 0

2.8 –

3.3 –

fosc

–

40

–

kHz

PWM COMPARATOR SECTION (Test Circuit Figure 11) Input Threshold Voltage (Zero Duty Cycle) Input Sink Current (V(Pin 3) = 0.7 V) DEADTIME CONTROL SECTION (Test Circuit Figure 11)

Input Threshold Voltage (Pin 4) (Zero Duty Cycle) (Maximum Duty Cycle)

%

Vth

V

OSCILLATOR SECTION Frequency (CT = 0.001 µF, RT = 30 kΩ) Standard Deviation of Frequency* (CT = 0.001 µF, RT = 30 kΩ)

σfosc

–

3.0

–

%

Frequency Change with Voltage (VCC = 7.0 V to 40 V, TA = 25°C)

∆fosc (∆V)

–

0.1

–

%

Frequency Change with Temperature (∆TA = Tlow to Thigh) (CT = 0.01 µF, RT = 12 kΩ)

∆fosc (∆T)

–

–

12

%

Vth

5.5

6.43

7.0

V

– –

5.5 7.0

10 15

–

7.0

–

UNDERVOLTAGE LOCKOUT SECTION Turn–On Threshold (VCC increasing, Iref = 1.0 mA) TOTAL DEVICE Standby Supply Current (Pin 6 at Vref, All other inputs and outputs open) (VCC = 15 V) (VCC = 40 V) Average Supply Current (CT = 0.01 µF, RT = 12 kΩ, V(Pin 4) = 2.0 V) (VCC = 15 V) (See Figure 12)

ICC

mA

mA

* Standard deviation is a measure of the statistical distribution about the mean as derived from the formula, σ


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TL494 APPLICATIONS INFORMATION Description

common mode input range from –0.3 V to (VCC – 2V), and may be used to sense power–supply output voltage and current. The error–amplifier outputs are active high and are ORed together at the noninverting input of the pulse–width modulator comparator. With this configuration, the amplifier that demands minimum output on time, dominates control of the loop. When capacitor CT is discharged, a positive pulse is generated on the output of the deadtime comparator, which clocks the pulse–steering flip–flop and inhibits the output transistors, Q1 and Q2. With the output–control connected to the reference line, the pulse–steering flip–flop directs the modulated pulses to each of the two output transistors alternately for push–pull operation. The output frequency is equal to half that of the oscillator. Output drive can also be taken from Q1 or Q2, when single–ended operation with a maximum on–time of less than 50% is required. This is desirable when the output transformer has a ringback winding with a catch diode used for snubbing. When higher output–drive currents are required for single–ended operation, Q1 and Q2 may be connected in parallel, and the output–mode pin must be tied to ground to disable the flip–flop. The output frequency will now be equal to that of the oscillator. The TL494 has an internal 5.0 V reference capable of sourcing up to 10 mA of load current for external bias circuits. The reference has an internal accuracy of ±5.0% with a typical thermal drift of less than 50 mV over an operating temperature range of 0° to 70°C.

The TL494 is a fixed–frequency pulse width modulation control circuit, incorporating the primary building blocks required for the control of a switching power supply. (See Figure 1.) An internal–linear sawtooth oscillator is frequency– programmable by two external components, RT and CT. The approximate oscillator frequency is determined by: fosc ≈

1.1 RT • CT

For more information refer to Figure 3.

Output pulse width modulation is accomplished by comparison of the positive sawtooth waveform across capacitor CT to either of two control signals. The NOR gates, which drive output transistors Q1 and Q2, are enabled only when the flip–flop clock–input line is in its low state. This happens only during that portion of time when the sawtooth voltage is greater than the control signals. Therefore, an increase in control–signal amplitude causes a corresponding linear decrease of output pulse width. (Refer to the Timing Diagram shown in Figure 2.) The control signals are external inputs that can be fed into the deadtime control, the error amplifier inputs, or the feedback input. The deadtime control comparator has an effective 120 mV input offset which limits the minimum output deadtime to approximately the first 4% of the sawtooth–cycle time. This would result in a maximum duty cycle on a given output of 96% with the output control grounded, and 48% with it connected to the reference line. Additional deadtime may be imposed on the output by setting the deadtime–control input to a fixed voltage, ranging between 0 V to 3.3 V.

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Output Function

fout fosc =

Grounded

Single–ended PWM @ Q1 and Q2

1.0

Push–pull Operation

0.5

@ Vref

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Figure 12. Common–Emitter Configuration Test Circuit and Waveform


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Figure 20. Pulse Width Modulated Push–Pull Converter Test

Conditions

Results

Line Regulation

Vin = 10 V to 40 V

14 mV 0.28%

Load Regulation

Vin = 28 V, IO = 1.0 mA to 1.0 A

3.0 mV 0.06%

Output Ripple

Vin = 28 V, IO = 1.0 A

65 mV pp P.A.R.D.


Vin = 28 V, RL = 0.1 Ω

1.6 A

Efficiency

Vin = 28 V, IO = 1.0 A

71%


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Figure 21. Pulse Width Modulated Step–Down Converter

Test

.

Conditions

Line Regulation

Vin = 8.0 V to 40 V

Load Regulation

Vin = 12.6 V, IO = 0.2 mA to 200 mA

Output Ripple

Vin = 12.6 V, IO = 200 mA


Vin = 12.6 V, RL = 0.1 Ω

Efficiency

Vin = 12.6 V, IO = 200 mA


Results 3.0 mV

0.01%

5.0 mV

0.02%

40 mV pp

P.A.R.D.

250 mA 72%

0> 8 "!" "#/ 8! 1"# )" " " The TL594 is a fixed frequency, pulse width modulation control circuit designed primarily for Switchmode power supply control.

• • • • • • • •

Complete Pulse Width Modulation Control Circuitry On–Chip Oscillator with Master or Slave Operation On–Chip Error Amplifiers On–Chip 5.0 V Reference, 1.5% Accuracy Adjustable Deadtime Control Uncommitted Output Transistors Rated to 500 mA Source or Sink Output Control for Push–Pull or Single–Ended Operation Undervoltage Lockout

http://onsemi.com MARKING DIAGRAMS 16 PDIP–16 N SUFFIX CASE 648

16

TL594CN AWLYWW

1

1 16 SO–16 D SUFFIX CASE 751B

16

TL594CD AWLYWW

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1 16 TL59 4DTB ALYW

TSSOP–16 DTB SUFFIX CASE 948F

16 1

1

MAXIMUM RATINGS (Full operating ambient temperature range applies,

A WL, L Y WW, W


unless otherwise noted.) Rating

Symbol

Value

Unit


VCC

42

V

Collector Output Voltage

VC1, VC2

42

V

IC1, IC2

500

mA

Collector Output Current (Each Transistor) (Note 1) Amplifier Input Voltage Range

VIR

–0.3 to +42

V

Power Dissipation @ TA ≤ 45°C

PD

1000

mW

Thermal Resistance Junction–to–Ambient (PDIP) Junction–to–Air (TSSOP) Junction–to–Ambient (SOIC)

RθJA


TJ

125

°C


Tstg

–55 to +125

°C

Operating Ambient Temperature Range TL594CD, CN, CDTB

TA

Derating Ambient Temperature

TA

°C/W 80 140 135


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PIN CONNECTIONS

1728

Publication Order Number: TL594/D

TL594 RECOMMENDED OPERATING CONDITIONS Characteristics

Symbol

Min

Typ

Max

Unit

VCC

7.0

15

40

V

VC1, VC2

–

30

40

V

IC1, IC2

–

–

200

mA

Amplified Input Voltage

Vin

0.3

–

VCC – 2.0

V

Current Into Feedback Terminal

lfb

–

–

0.3

mA

Reference Output Current

lref

–

–

10

mA kΩ

Power Supply Voltage Collector Output Voltage Collector Output Current (Each transistor)

Timing Resistor

RT

1.8

30

500

Timing Capacitor

CT

0.0047

0.001

10

µF


fosc

1.0

40

200

kHz

–

0.3

–

5.3

V

PWM Input Voltage (Pins 3, 4, 13)

ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 µF, RT = 12 kΩ, unless otherwise noted.) For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted. Characteristics

Symbol

Min

Typ

Max

4.925 4.9

5.0 –

5.075 5.1

Unit

REFERENCE SECTION Reference Voltage (IO = 1.0 mA, TA = 25°C) (IO = 1.0 mA)

Vref

V

Line Regulation (VCC = 7.0 V to 40 V)

Regline

–

2.0

25

mV


Regload

–

2.0

15

mV

Short Circuit Output Current (Vref = 0 V)

ISC

15

40

75

mA

Collector Off–State Current (VCC = 40 V, VCE = 40 V)

IC(off)

–

2.0

100

µA

Emitter Off–State Current (VCC = 40 V, VC = 40 V, VE = 0 V)

IE(off)

–

–

–100

µA

VSAT(C) VSAT(E)

– –

1.1 1.5

1.3 2.5

IOCL IOCH

– –

0.1 2.0

– 20

– –

100 100

200 200

– –

40 40

100 100

2.0

10

OUTPUT SECTION

Collector–Emitter Saturation Voltage (Note 2) Common–Emitter (VE = 0 V, IC = 200 mA) Emitter–Follower (VC = 15 V, IE = –200 mA)

V

µA

Output Control Pin Current Low State (VOC ≤ 0.4 V) High State (VOC = Vref) Output Voltage Rise Time Common–Emitter (See Figure 13) Emitter–Follower (See Figure 14)

tr

Output Voltage Fall Time Common–Emitter (See Figure 13) Emitter–Follower (See Figure 14)

tf

ns

ns

ERROR AMPLIFIER SECTION Input Offset Voltage (VO (Pin 3) = 2.5 V)

VIO

–

Input Offset Current (VO (Pin 3) = 2.5 V)

IIO

–

5.0

250

nA

Input Bias Current (VO (Pin 3) = 2.5 V)

IIB

–

–0.1

–1.0

µA

Input Common Mode Voltage Range (VCC = 40 V, TA = 25°C) Inverting Input Voltage Range

VICR

0 to VCC–2.0

VIR(INV)

–0.3 to VCC–2.0

Open Loop Voltage Gain (∆VO = 3.0 V, VO = 0.5 V to 3.5 V, RL = 2.0 kΩ)

mV

V V

AVOL

70

95

–

dB

Unity–Gain Crossover Frequency (VO = 0.5 V to 3.5 V, RL = 2.0 kΩ)

fC

–

700

–

kHz

Phase Margin at Unity–Gain (VO = 0.5 V to 3.5 V, RL = 2.0 kΩ)

φm

–

65

–

deg.

Common Mode Rejection Ratio (VCC = 40 V)

CMRR

65

90

–

dB

Power Supply Rejection Ratio (∆VCC = 33 V, VO = 2.5 V, RL = 2.0 kΩ)

PSRR

–

100

–

dB

Output Sink Current (VO (Pin 3) = 0.7 V)

IO–

0.3

0.7

–

mA

Output Source Current (VO (Pin 3) = 3.5 V)

IO+

–2.0

–4.0

–

mA



TL594 ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 µF, RT = 12 kΩ, unless otherwise noted.) For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted. Characteristics

Symbol

Min

Typ

Max

Unit

VTH

–

3.6

4.5

V

II–

0.3

0.7

–

mA

Input Bias Current (Pin 4) (VPin 4 = 0 V to 5.25 V)

IIB (DT)

–

–2.0

–10

µA

Maximum Duty Cycle, Each Output, Push–Pull Mode (VPin 4 = 0 V, CT = 0.01 µF, RT = 12 kΩ) (VPin 4 = 0 V, CT = 0.001 µF, RT = 30 kΩ)

DCmax 45 –

48 45

50 –

– 0

2.8 –

3.3 –

– 9.2 9.0

40 10 –

– 10.8 12

σfosc

–

1.5

–

%

Frequency Change with Voltage (VCC = 7.0 V to 40 V, TA = 25°C)

∆fosc (∆V)

–

0.2

1.0

%

Frequency Change with Temperature (∆TA = Tlow to Thigh, CT = 0.01 µF, RT = 12 kΩ)

∆fosc (∆T)

–

4.0

–

%

4.0 3.5

5.2 –

6.0 6.5

100 50

150 150

300 300

– –

8.0 8.0

15 18

–

11

–

PWM COMPARATOR SECTION (Test Circuit Figure 11) Input Threshold Voltage (Zero Duty Cycle) Input Sink Current (VPin 3 = 0.7 V) DEADTIME CONTROL SECTION (Test Circuit Figure 11)

Input Threshold Voltage (Pin 4) (Zero Duty Cycle) (Maximum Duty Cycle)

%

VTH

V

OSCILLATOR SECTION Frequency (CT = 0.001 µF, RT = 30 kΩ) (CT = 0.01 µF, RT = 12 kΩ, TA = 25°C) (CT = 0.01 µF, RT = 12 kΩ, TA = Tlow to Thigh)

fosc

Standard Deviation of Frequency* (CT = 0.001 µF, RT = 30 kΩ)

kHz

UNDERVOLTAGE LOCKOUT SECTION Turn–On Threshold (VCC Increasing, Iref = 1.0 mA) TA = 25°C TA = Tlow to Thigh

Vth

Hysteresis TL594C,I TL594M

VH

V

mV

TOTAL DEVICE Standby Supply Current (Pin 6 at Vref, All other inputs and outputs open) (VCC = 15 V) (VCC = 40 V)

ICC

Average Supply Current (VPin 4 = 2.0 V, CT = 0.01 µF, RT = 12 kΩ, VCC = 15 V, See Figure 11)

mA

mA

*Standard deviation is a measure of the statistical distribution about the mean as derived from the formula, σ


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TL594 APPLICATIONS INFORMATION Description

pin varies from 0.5 V to 3.5 V. Both error amplifiers have a common–mode input range from –0.3 V to (VCC – 2 V), and may be used to sense power–supply output voltage and current. The error–amplifier outputs are active high and are ORed together at the noninverting input of the pulse–width modulator comparator. With this configuration, the amplifier that demands minimum output on time, dominates control of the loop.

The TL594 is a fixed–frequency pulse width modulation control circuit, incorporating the primary building blocks required for the control of a switching power supply. (See Figure 1.) An internal–linear sawtooth oscillator is frequency– programmable by two external components, RT and CT. The approximate oscillator frequency is determined by: 1.1 RT • CT

Functional Table Input/Output Controls

For more information refer to Figure 3.

Grounded

Output pulse width modulation is accomplished by comparison of the positive sawtooth waveform across capacitor CT to either of two control signals. The NOR gates, which drive output transistors Q1 and Q2, are enabled only when the flip–flop clock–input line is in its low state. This happens only during that portion of time when the sawtooth voltage is greater than the control signals. Therefore, an increase in control–signal amplitude causes a corresponding linear decrease of output pulse width. (Refer to the Timing Diagram shown in Figure 2.) The control signals are external inputs that can be fed into the deadtime control, the error amplifier inputs, or the feedback input. The deadtime control comparator has an effective 120 mV input offset which limits the minimum output deadtime to approximately the first 4% of the sawtooth–cycle time. This would result in a maximum duty cycle on a given output of 96% with the output control grounded, and 48% with it connected to the reference line. Additional deadtime may be imposed on the output by setting the deadtime–control input to a fixed voltage, ranging between 0 V to 3.3 V. The pulse width modulator comparator provides a means for the error amplifiers to adjust the output pulse width from the maximum percent on–time, established by the deadtime control input, down to zero, as the voltage at the feedback

@ Vref

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Single–ended PWM @ Q1 and Q2

1.0

Push–pull Operation

0.5

When capacitor CT is discharged, a positive pulse is generated on the output of the deadtime comparator, which clocks the pulse–steering flip–flop and inhibits the output transistors, Q1 and Q2. With the output–control connected to the reference line, the pulse–steering flip–flop directs the modulated pulses to each of the two output transistors alternately for push–pull operation. The output frequency is equal to half that of the oscillator. Output drive can also be taken from Q1 or Q2, when single–ended operation with a maximum on–time of less than 50% is required. This is desirable when the output transformer has a ringback winding with a catch diode used for snubbing. When higher output–drive currents are required for single–ended operation, Q1 and Q2 may be connected in parallel, and the output–mode pin must be tied to ground to disable the flip–flop. The output frequency will now be equal to that of the oscillator. The TL594 has an internal 5.0 V reference capable of sourcing up to 10 mA of load current for external bias circuits. The reference has an internal accuracy of ±1.5% with a typical thermal drift of less than 50 mV over an operating temperature range of 0° to 70°C.

1

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fout fosc =

Output Function

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Figure 6. Percent Duty Cycle versus Deadtime Control Voltage

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Figure 8. Common–Emitter Configuration Output Saturation Voltage versus Collector Current

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Figure 10. Undervoltage Lockout Thresholds versus Reference Load Current


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Figure 12. Deadtime and Feedback Control Circuit

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Figure 13. Common–Emitter Configuration Test Circuit and Waveform

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Figure 14. Emitter–Follower Configuration Test Circuit and Waveform


TL594

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Figure 19. Slaving Two or More Control Circuits

Figure 20. Operation with Vin > 40 V Using External Zener

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Test

Conditions

Results

Line Regulation

Vin = 10 V to 40 V

14 mV 0.28%

Load Regulation

Vin = 28 V, IO = 1.0 mA to 1.0 A

3.0 mV 0.06%

Output Ripple

Vin = 28 V, IO = 1.0 A

65 mVpp P.A.R.D.


Vin = 28 V, RL = 0.1 Ω

1.6 A

Efficiency

Vin = 28 V, IO = 1.0 A

71%

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Figure 21. Pulse Width Modulated Push–Pull Converter


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Conditions

Results

Line Regulation

Vin = 8.0 V to 40 V

3.0 mV

0.01%

Load Regulation

Vin = 12.6 V, IO = 0.2 mA to 200 mA

5.0 mV

0.02%

Output Ripple

Vin = 12.6 V, IO = 200 mA


Vin = 12.6 V, RL = 0.1 Ω

Efficiency

Vin = 12.6 V, IO = 200 mA

40 mVpp

P.A.R.D.

250 mA 72%

Figure 22. Pulse Width Modulated Step–Down Converter

ORDERING INFORMATION Operating Temperature Range

Package

Shipping

TL594CD

–25 to 85°C

SOIC–16

48 Units/Rail

TL594CDR2

–25 to 85°C

SOIC–16

2400 Tape & Reel

TL594CN

–25 to 85°C

PDIP–16

25 Units/Rail

TL594CDTB

–25 to 85°C

TSSOP–16

96 Units/Rail

TL594CDTBR2

–25 to 85°C

TSSOP–16

2500 Tape & Reel

Device


< 8! 1"# ) " " The SG3525A pulse width modulator control circuit offers improved performance and lower external parts count when implemented for controlling all types of switching power supplies. The on–chip +5.1 V reference is trimmed to ±1% and the error amplifier has an input common–mode voltage range that includes the reference voltage, thus eliminating the need for external divider resistors. A sync input to the oscillator enables multiple units to be slaved or a single unit to be synchronized to an external system clock. A wide range of deadtime can be programmed by a single resistor connected between the CT and Discharge pins. This device also features built–in soft–start circuitry, requiring only an external timing capacitor. A shutdown pin controls both the soft–start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft–start recycle with longer shutdown commands. The under voltage lockout inhibits the outputs and the changing of the soft–start capacitor when VCC is below nominal. The output stages are totem–pole design capable of sinking and sourcing in excess of 200 mA. The output stage of the SG3525A features NOR logic resulting in a low output for an off–state.

• • • • • • • • •

8.0 V to 35 V Operation 5.1 V ± 1.0% Trimmed Reference 100 Hz to 400 kHz Oscillator Range Separate Oscillator Sync Pin Adjustable Deadtime Control Input Undervoltage Lockout Latching PWM to Prevent Multiple Pulses Pulse–by–Pulse Shutdown Dual Source/Sink Outputs: ±400 mA Peak

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MC34025, MC33025 OPERATING DESCRIPTION Soft–Start Latch

The MC33025 and MC34025 series are high speed, fixed frequency, double–ended pulse width modulator controllers optimized for high frequency operation. They are specifically designed for Off–Line and DC–to–DC converter applications offering the designer a cost effective solution with minimal external components. A representative block diagram is shown in Figure 19.

Soft–Start is accomplished in conjunction with an external capacitor. The soft start capacitor is charged by an internal 9.0 µA current source. This capacitor clamps the output of the error amplifier to less than its normal output voltage, thus limiting the duty cycle. The time it takes for a capacitor to reach full charge is given by:

Oscillator

t [ (4.5 • 10 5) C Soft-Start

The oscillator frequency is programmed by the values selected for the timing components RT and CT. The RT pin is set to a temperature compensated 3.0 V. By selecting the value of RT, the charge current is set through a current mirror for the timing capacitor CT. This charge current runs continuously through CT. The discharge current is ratioed to be 10 times the charge current, which yields the maximum duty cycle of 90%. CT is charged to 2.8 V and discharged to 1.0 V. During the discharge of CT, the oscillator generates an internal blanking pulse that resets the PWM Latch, inhibits the outputs, and toggles the steering flip–flop. The threshold voltages on the oscillator comparator is trimmed to guarantee an oscillator accuracy of 5.0% at 25°C. Additional dead time can be added by externally increasing the charge current to CT as shown in Figure 24. This changes the charge to discharge ratio of CT which is set internally to Icharge/10 Icharge. The new charge to discharge ratio will be: % Deadtime +

A Soft–Start latch is incorporated to prevent erratic operation of this circuitry. Two conditions can cause the Soft–Start circuit to latch so that the Soft–Start capacitor stays discharged. The first condition is activation of an undervoltage lockout of either VCC or Vref. The second condition is when current sense input exceeds 1.4 V. Since this latch is “set dominant”, it cannot be reset until either of these signals is removed, and the voltage at CSoft–Start is less than 0.5 V. PWM Comparator and Latch

A PWM circuit typically compares an error voltage with a ramp signal. The outcome of this comparison determines the state of the output. In voltage mode operation the ramp signal is the voltage ramp of the timing capacitor. In current mode operation the ramp signal is the voltage ramp induced in a current sensing element. The ramp input of the PWM comparator is pinned out so that the user can decide which mode of operation best suits the application requirements. The ramp input has a 1.25 V offset such that whenever the voltage at this pin exceeds the Error Amplifier Output voltage minus 1.25 V, the PWM comparator will cause the PWM latch to set, disabling the outputs. Once the PWM latch is set, only a blanking pulse by the oscillator can reset it, thus initiating the next cycle. A toggle flip flop connected to the output of the PWM latch controls which output is active. The flip flop is pulsed by an OR gate that gets its inputs from the oscillator clock and the output of the PWM latch. A pulse from either one will cause the flip flop to enable the other output.

I additional ) I charge 10 (I charge)

A bidirectional clock pin is provided for synchronization or for master/slave operation. As a master, the clock pin provides a positive output pulse during the discharge of CT. As a slave, the clock pin is an input that resets the PWM latch and blanks the drive output, but does not discharge CT. Therefore, the oscillator is not synchronized by driving the clock pin alone. Figures 30 and 31 provide suggested synchronization. Error Amplifier

A fully compensated Error Amplifier is provided. It features a typical DC voltage gain of 95 dB and a gain bandwidth product of 8.3 MHz with 75 degrees of phase margin (Figure 4). Typical application circuits will have the noninverting input tied to the reference. The inverting input will typically be connected to a feedback voltage generated from the output of the switching power supply. Both inputs have a Common Mode Voltage (VCM) input range of 1.5 V to 5.5 V. The Error Amplifier Output is provided for external loop compensation.

Current Limiting and Shutdown

A pin is provided to perform current limiting and shutdown operations. Two comparators are connected to the input of this pin. When the voltage at this pin exceeds 1.0 V, one of the comparators is activated. The output of this comparator sets the PWM latch, which disables the output. In this way cycle–by–cycle current limiting is accomplished. If a current limit resistor is used in series with the power devices, the value of the resistor is found by: R Sense +


1.0 V I pk (switch)

MC34025, MC33025 and snubbers should be connected as close as possible to the specific part in question. The PC board lead lengths must be less than 0.5 inches for effective bypassing or snubbing.

If the voltage at this pin exceeds 1.4 V, the second comparator is activated. This comparator sets a latch which, in turn, causes the Soft–Start capacitor to be discharged. In this way a “hiccup” mode of recovery is possible in the case of output short circuits. If a current limit resistor is used in series with the output devices, the peak current at which the controller will enter a “hiccup” mode is given by: I shutdown +

Instabilities

In current mode control, an instability can be encountered at any given duty cycle. The instability is caused by the current feedback loop. It has been shown that the instability is caused by a double pole at half the switching frequency. If an external ramp (Se) is added to the on–time ramp (Sn) of the current–sense waveform, stability can be achieved (see Figure 21). One must be careful not to add too much ramp compensation. If too much is added, the system will start to perform like a voltage mode regulator. All benefits of current mode control will be lost. Figures 29A and 29B show examples of two different ways in which external ramp compensation can be implemented.

1.4 V R Sense


There are two undervoltage lockout circuits within the IC. The first senses VCC and the second Vref. During power–up, VCC must exceed 9.2 V and Vref must exceed 4.2 V before the outputs can be enabled and the Soft–Start latch released. If VCC falls below 8.4 V or Vref falls below 3.6 V, the outputs are disabled and the Soft–Start latch is activated. When the UVLO is active, the part is in a low current standby mode allowing the IC to have an off–line bootstrap start–up circuit. Typical start–up current is 500 µA.

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The MC34025 has two high current totem pole outputs specifically designed for direct drive of power MOSFETs. They are capable of up to ±2.0 A peak drive current with a typical rise and fall time of 30 ns driving a 1.0 nF load. Separate pins for VC and Power Ground are provided. With proper implementation, a significant reduction of switching transient noise imposed on the control circuitry is possible. The separate VC supply input also allows the designer added flexibility in tailoring the drive voltage independent of VCC.

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A simple equation can be used to calculate the amount of external ramp necessary to add that will achieve stability in the current loop. For the following equations, the calculated values for the application circuit in Figure 37 are also shown.

Reference

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where:


Do not attempt to construct the converter on wire–wrap or plug–in prototype boards. With high frequency, high power, switching power supplies it is imperative to have separate current loops for the signal paths and for the power paths. The printed circuit layout should contain a ground plane with low current signal and high current switch and output grounds returning on separate paths back to the input filter capacitor. All bypass capacitors

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MC34025, MC33025 PIN FUNCTION DESCRIPTION Pin No. DIP/SOIC

Function

Description

1

Error Amp Inverting Input

This pin is usually used for feedback from the output of the power supply.

2

Error Amp Noninverting Input

This pin is used to provide a reference in which an error signal can be produced on the output of the error amp. Usually this is connected to Vref, however an external reference can also be used.

3

Error Amp Output

This pin is provided for compensating the error amp for poles and zeros encountered in the power supply system, mostly the output LC filter.

4

Clock

This is a bidirectional pin used for synchronization.

5

RT

The value of RT sets the charge current through timing Capacitor, CT.

6

CT

In conjunction with RT, the timing Capacitor sets the switching frequency. Because this part is a push–pull output, each output runs at one–half the frequency set at this pin.

7

Ramp Input

For voltage mode operation this pin is connected to CT. For current mode operation this pin is connected through a filter to the current sensing element.

8

Soft–Start

A capacitor at this pin sets the Soft–Start time.

9

Current Limit/Shutdown

This pin has two functions. First, it provides cycle–by–cycle current limiting. Second, if the current is excessive, this pin will reinitiate a Soft–Start cycle.

10

Ground

This pin is the ground for the control circuitry.

11

Output A

This is a high current totem pole output.

12

Power Ground

This is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry.

13

VC

This is a separate power source connection for the outputs that is connected back to the power source input. With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry.

14

Output B

This is a high current totem pole output.

15

VCC


16

Vref

This is a 5.1 V reference. It is usually connected to the noninverting input of the error amplifier.

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7

In current mode control, an RC filter should be placed at the ramp input to filter the leading edge spike caused by turn–on of a power MOSFET.

Figure 22. Voltage Mode Operation

Figure 23. Current Mode Operation


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Additional dead time can be added by the addition of a dead time resistor from Vref to CT. See text on oscillator section for more information. The sync pulse fed into the clock pin must be at least 3.9 V. RT and CT need to be set 10% slower than the sync frequency. This circuit is also used in voltage mode operation for master/slave operation. The clock signal would be coming from the master which is set at the desired operating frequency, while the slave is set 10% slower.

Figure 24. Dead Time Addition


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The addition of an RC filter will eliminate instability caused by the leading edge spike on the current waveform. This sense signal can also be used at the ramp input pin for current mode control. For ramp compensation it is necessary to know the gain of the current feedback loop. If a transformer is used, the gain can be calculated by: A

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Figure 26. Resistive Current Sensing

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The addition of an RC filter will eliminate instability caused by the leading edge spike on the current waveform. This sense signal can also be used at the ramp input pin for current mode control. For ramp compensation it is necessary to know the gain of the current feedback loop. The gain can be calculated by: A

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This method of slope compensation is easy to implement, however, it is noise sensitive. Capacitor C1 provides AC coupling. The oscillator signal is added to the current signal by a voltage divider consisting of resistors R1 and R2.

Figure 29A. Slope Compensation (Noise Sensitive)

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When only one output is used, this method of slope compensation can be used and it is relatively noise immune. Resistor RM and capacitor CM provide the added slope necessary. By choosing RM and CM with a larger time constant than the switching frequency, you can assume that its charge is linear. First choose CM, then RM can be adjusted to achieve the required slope. The diode provides a reset pulse at the ramp input at the end of every cycle. The charge current IM can be calculated by IM = CMSe. Then RM can be calculated by RM = VCC/IM.

Figure 29B. Slope Compensation (Noise Immune)

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Figure 30. Current Mode Master/Slave Operation Over Short Distances


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UC3842A, UC3843A, UC2842A, UC2843A OPERATING DESCRIPTION The UC3842A, UC3843A series are high performance, fixed frequency, current mode controllers. They are specifically designed for Off–Line and dc–to–dc converter applications offering the designer a cost effective solution with minimal external components. A representative block diagram is shown in Figure 18.

is removed, or at the beginning of a soft–start interval (Figures 24, 25). The Error Amp minimum feedback resistance is limited by the amplifier’s source current (0.5 mA) and the required output voltage (VOH) to reach the comparator’s 1.0 V clamp level: Rf(min) ≈

Oscillator

The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor CT is charged from the 5.0 V reference through resistor RT to approximately 2.8 V and discharged to 1.2 V by an internal current sink. During the discharge of CT, the oscillator generates and internal blanking pulse that holds the center input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. Figure 2 shows RT versus Oscillator Frequency and Figure 3, Output Deadtime versus Frequency, both for given values of CT. Note that many values of RT and CT will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. The oscillator thresholds are temperature compensated, and the discharge current is trimmed and guaranteed to within ±10% at TJ = 25°C. These internal circuit refinements minimize variations of oscillator frequency and maximum output duty cycle. The results are shown in Figures 4 and 5. In many noise sensitive applications it may be desirable to frequency–lock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 21. For reliable locking, the free–running oscillator frequency should be set about 10% less than the clock frequency. A method for multi unit synchronization is shown in Figure 22. By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved.

3.0 (1.0 V) + 1.4 V = 8800 Ω 0.5 mA

Current Sense Comparator and PWM Latch

The UC3842A, UC3843A operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin1). Thus the error signal controls the peak inductor current on a cycle–by–cycle basis. The current Sense Comparator PWM Latch configuration used ensures that only a single pulse appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground referenced sense resistor RS in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where: Ipk =

V(Pin 1) – 1.4 V 3 RS

Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0 V. Therefore the maximum peak switch current is: Ipk(max) =

1.0 V RS

When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 23. The two external diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the Ipk(max) clamp voltage. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability; refer to Figure 27.

Error Amplifier

A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical dc voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz with 57 degrees of phase margin (Figure 8). The noninverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is –2.0 µA which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. The Error Amp Output (Pin 1) is provide for external loop compensation (Figure 31). The output voltage is offset by two diode drops (≈ 1.4 V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when Pin 1 is at its lowest state (VOL). This occurs when the power supply is operating and the load


UC3842A, UC3843A, UC2842A, UC2843A PIN FUNCTION DESCRIPTION Pin 8–Pin

14–Pin

Function

1

1

Compensation

2

3

Voltage Feedback

This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider.

3

5

Current Sense

A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction.

4

7

RT/CT

5

–

Gnd

6

10

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7

12

VCC


8

14

Vref

This is the reference output. It provides charging current for capacitor CT through resistor RT.

–

8

Power Ground

–

11

VC

–

9

Gnd

This pin is the control circuitry ground return (14–pin package only) and is connected back to the power source ground.

–

2,4,6,13

NC

No connection (14–pin package only). These pins are not internally connected.

Description This pin is Error Amplifier output and is made available for loop compensation.

The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and capacitor CT to ground. Operation to 500 kHz is possible. This pin is the combined control circuitry and power ground (8–pin package only). This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced and sunk by this pin.

This pin is a separate power ground return (14–pin package only) that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. The Output high state (VOH) is set by the voltage applied to this pin (14–pin package only). With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry.


and has a typical rise and fall time of 50 ns with a 1.0 nF load. Additional internal circuitry has been added to keep the Output in a sinking mode whenever an undervoltage lockout is active. This characteristic eliminates the need for an external pull–down resistor. The SO–14 surface mount package provides separate pins for VC (output supply) and Power Ground. Proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the Ipk(max) clamp level. The separate VC supply input allows the designer added flexibility in tailoring the drive voltage independent of VCC. A zener clamp is typically connected to this input when driving power MOSFETs in systems where VCC is greater than 20 V. Figure 26 shows proper power and control ground connections in a current sensing power MOSFET application.

Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stage is enabled. The positive power supply terminal (VCC) and the reference output (Vref) are each monitored by separate comparators. Each has built–in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The VCC comparator upper and lower thresholds are 16 V/10 V for the UCX842A, and 8.4 V/7.6 V for the UCX843A. The Vref comparator upper and lower thresholds are 3.6V/3.4 V. The large hysteresis and low startup current of the UCX842A makes it ideally suited in off–line converter applications where efficient bootstrap startup techniques are required (Figure 34). The UCX843A is intended for lower voltage dc to dc converter applications. A 36 V zener is connected as a shunt regulator form VCC to ground. Its purpose is to protect the IC from excessive voltage that can occur during system startup. The minimum operating voltage for the UCX842A is 11 V and 8.2 V for the UCX843A.

Reference

The 5.0 V bandgap reference is trimmed to ±1.0% tolerance at TJ = 25°C on the UC284XA, and ± 2.0% on the UC384XA. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has short circuit protection and is capable of providing in excess of 20 mA for powering additional control system circuitry.

Output

These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFETs. It is capable of up to ±1.0 A peak drive current


UC3842A, UC3843A, UC2842A, UC2843A DESIGN CONSIDERATIONS Do not attempt to construct the converter on wire–wrap or plug–in prototype boards. High Frequency circuit layout techniques are imperative to prevent pulsewidth jitter. This is usually caused by excessive noise pick–up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low–current signal and high–current switch and output grounds returning on separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1 µF) connected directly to VCC, VC, and Vref may be required depending upon circuit layout. This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise generating components. Current mode converters can exhibit subharmonic oscillations when operating at a duty cycle greater than 50% with continuous inductor current. This instability is independent of the regulators closed–loop characteristics and is caused by the simultaneous operating conditions of fixed frequency and peak current detecting. Figure 20A shows the phenomenon graphically. At t0, switch conduction begins, causing the inductor current to rise at a slope of m1. This slope is a function of the input voltage divided by the inductance. At t1, the Current Sense Input reaches the threshold established by the control voltage. This causes the switch to turn off and the current to decay at a slope of m2 until the next oscillator cycle. The unstable condition can be shown if a pertubation is added to the control voltage, resulting in a small ∆I (dashed line). With a fixed oscillator period, the current decay time is reduced, and the minimum current at switch turn–on (t2) is increased by ∆I + ∆I m2/m1. The minimum current at the next cycle

(t3) decreases to (∆I + ∆I m2/m1) (m2/m1). This pertubation is multiplied by m2.m1 on each succeeding cycle, alternately increasing and decreasing the inductor current at switch turn–on. Several oscillator cycles may be required before the inductor current reaches zero causing the process to commence again. If m2/m1 is greater than 1, the converter will be unstable. Figure 20B shows that by adding an artificial ramp that is synchronized with the PWM clock to the control voltage, the ∆I pertubation will decrease to zero on succeeding cycles. This compensation ramp (m3) must have a slope equal to or slightly greater than m2/2 for stability. With m2/2 slope compensation, the average inductor current follows the control voltage yielding true current mode operation. The compensating ramp can be derived from the oscillator and added to either the Voltage Feedback or Current Sense inputs (Figure 33).

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UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV PIN FUNCTION DESCRIPTION Pin 8–Pin

14–Pin

Function

1

1

Compensation

2

3

Voltage Feedback


3

5

Current Sense


4

7

RT/CT

5

Gnd

Description This pin is the Error Amplifier output and is made available for loop compensation.

The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and capacitor CT to ground. Operation to 500 kHz is possible. This pin is the combined control circuitry and power ground.

6

10

Output

This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced and sunk by this pin.

7

12

VCC


8

14

Vref


8

Power Ground

11

VC

9

Gnd

This pin is the control circuitry ground return and is connected back to the power source ground.

2,4,6,13

NC

No connection. These pins are not internally connected.

This pin is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. The Output high state (VOH) is set by the voltage applied to this pin. With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry.


UC3842B, UC3843B, UC2842B, UC2843B, NCV3843BV OPERATING DESCRIPTION The UC3842B, UC3843B series are high performance, fixed frequency, current mode controllers. They are specifically designed for Off–Line and dc–to–dc converter applications offering the designer a cost–effective solution with minimal external components. A representative block diagram is shown in Figure 18.

This occurs when the power supply is operating and the load is removed, or at the beginning of a soft–start interval (Figures 24, 25). The Error Amp minimum feedback resistance is limited by the amplifier’s source current (0.5 mA) and the required output voltage (VOH) to reach the comparator’s 1.0 V clamp level: Rf(min) ≈

Oscillator

The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor CT is charged from the 5.0 V reference through resistor RT to approximately 2.8 V and discharged to 1.2 V by an internal current sink. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the center input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. Figure 2 shows RT versus Oscillator Frequency and Figure 3, Output Deadtime versus Frequency, both for given values of CT. Note that many values of RT and CT will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. The oscillator thresholds are temperature compensated to within ±6% at 50 kHz. Also because of industry trends moving the UC384X into higher and higher frequency applications, the UC384XB is guaranteed to within ±10% at 250 kHz. These internal circuit refinements minimize variations of oscillator frequency and maximum output duty cycle. The results are shown in Figures 4 and 5. In many noise–sensitive applications it may be desirable to frequency–lock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 21. For reliable locking, the free–running oscillator frequency should be set about 10% less than the clock frequency. A method for multi–unit synchronization is shown in Figure 22. By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved.

3.0 (1.0 V) + 1.4 V = 8800 Ω 0.5 mA


The UC3842B, UC3843B operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin 1). Thus the error signal controls the peak inductor current on a cycle–by–cycle basis. The Current Sense Comparator PWM Latch configuration used ensures that only a single pulse appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground–referenced sense resistor RS in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where: Ipk =

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1.0 V RS

When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 23. The two external diodes are used to compensate the internal diodes, yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the Ipk(max) clamp voltage. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability (refer to Figure 27).

Error Amplifier

A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical dc voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz with 57 degrees of phase margin (Figure 8). The non–inverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is –2.0 µA which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. The Error Amp Output (Pin 1) is provided for external loop compensation (Figure 32). The output voltage is offset by two diode drops (≈1.4 V) and divided by three before it connects to the non–inverting input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when pin 1 is at its lowest state (VOL).


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Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stage is enabled. The positive power supply terminal (VCC) and the reference output (Vref) are each monitored by separate comparators. Each has built–in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The VCC comparator upper and lower thresholds are 16 V/10 V for the UCX842B, and 8.4 V/7.6 V for the UCX843B. The Vref comparator upper and lower thresholds are 3.6 V/3.4 V. The large hysteresis and low startup current of the UCX842B makes it ideally suited in off–line converter applications where efficient bootstrap startup techniques are required (Figure 34). The UCX843B is intended for lower voltage dc–to–dc converter applications. A 36 V zener is connected as a shunt regulator from VCC to ground. Its purpose is to protect the IC from excessive voltage that can occur during system startup. The minimum operating voltage (VCC) for the UCX842B is 11 V and 8.2 V for the UCX843B. These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFETs. It is capable of up to ±1.0 A peak drive current and has a typical rise and fall time of 50 ns with a 1.0 nF load. Additional internal circuitry has been added to keep the Output in a sinking mode whenever an undervoltage lockout is active. This characteristic eliminates the need for an external pull–down resistor. The SO–14 surface mount package provides separate pins for VC (output supply) and Power Ground. Proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the Ipk(max) clamp level. The separate VC supply input allows the designer added flexibility in tailoring the drive voltage independent of VCC. A zener clamp is typically connected to this input when driving power MOSFETs in systems where VCC is greater than 20 V. Figure 26 shows proper power and control ground connections in a current–sensing power MOSFET application.

Do not attempt to construct the converter on wire–wrap or plug–in prototype boards. High frequency circuit layout techniques are imperative to prevent pulse–width jitter. This is usually caused by excessive noise pick–up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low–current signal and high–current switch and output grounds returning on separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1 µF) connected directly to VCC, VC, and Vref may be required depending upon circuit layout. This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise–generating components. Current mode converters can exhibit subharmonic oscillations when operating at a duty cycle greater than 50% with continuous inductor current. This instability is independent of the regulator’s closed loop characteristics and is caused by the simultaneous operating conditions of fixed frequency and peak current detecting. Figure 20A shows the phenomenon graphically. At t0, switch conduction begins, causing the inductor current to rise at a slope of m1. This slope is a function of the input voltage divided by the inductance. At t1, the Current Sense Input reaches the threshold established by the control voltage. This causes the switch to turn off and the current to decay at a slope of m2, until the next oscillator cycle. The unstable condition can be shown if a perturbation is added to the control voltage, resulting in a small ∆I (dashed line). With a fixed oscillator period, the current decay time is reduced, and the minimum current at switch turn–on (t2) is increased by ∆I + ∆I m2/m1. The minimum current at the next cycle (t3) decreases to (∆I + ∆I m2/m1) (m2/m1). This perturbation is multiplied by m2/m1 on each succeeding cycle, alternately increasing and decreasing the inductor current at switch turn–on. Several oscillator cycles may be required before the inductor current reaches zero causing the process to commence again. If m2/m1 is greater than 1, the converter will be unstable. Figure 20B shows that by adding an artificial ramp that is synchronized with the PWM clock to the control voltage, the ∆I perturbation will decrease to zero on succeeding cycles. This compensating ramp (m3) must have a slope equal to or slightly greater than m2/2 for stability. With m2/2 slope compensation, the average inductor current follows the control voltage, yielding true current mode operation. The compensating ramp can be derived from the oscillator and added to either the Voltage Feedback or Current Sense inputs (Figure 33).

Reference

The 5.0 V bandgap reference is trimmed to ±1.0% tolerance at TJ = 25°C on the UC284XB, and ±2.0% on the UC384XB. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has short– circuit protection and is capable of providing in excess of 20 mA for powering additional control system circuitry.


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UC3844B, UC3845B, UC2844B, UC2845B PIN FUNCTION DESCRIPTION Pin 8–Pin

14–Pin

Function

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2

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3

5

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4

7

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The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and capacitor CT to ground. Oscillator operation to 1.0 kHz is possible.

5

Gnd

Description This pin is the Error Amplifier output and is made available for loop compensation.

This pin is the combined control circuitry and power ground.

6

10

Output

This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced and sunk by this pin. The output switches at one–half the oscillator frequency.

7

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8

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8

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11

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9

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2,4,6,13

NC

No connection. These pins are not internally connected.

This pin is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. The Output high state (VOH) is set by the voltage applied to this pin. With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry.


UC3844B, UC3845B, UC2844B, UC2845B OPERATING DESCRIPTION Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when Pin 1 is at its lowest state (VOL). This occurs when the power supply is operating and the load is removed, or at the beginning of a soft–start interval (Figures 21, 22). The Error Amp minimum feedback resistance is limited by the amplifier’s source current (0.5 mA) and the required output voltage (VOH) to reach the comparator’s 1.0 V clamp level:

The UC3844B, UC3845B series are high performance, fixed frequency, current mode controllers. They are specifically designed for Off–Line and dc–to–dc converter applications offering the designer a cost–effective solution with minimal external components. A representative block diagram is shown in Figure 16. Oscillator

The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor CT is charged from the 5.0 V reference through resistor RT to approximately 2.8 V and discharged to 1.2 V by an internal current sink. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the center input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. An internal flip–flop has been incorporated in the UCX844/5B which blanks the output off every other clock cycle by holding one of the inputs of the NOR gate high. This in combination with the CT discharge period yields output deadtimes programmable from 50% to 70%. Figure 2 shows RT versus Oscillator Frequency and Figure 3, Output Deadtime versus Frequency, both for given values of CT. Note that many values of RT and CT will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. The oscillator thresholds are temperature compensated to within ±6% at 50 kHz. Also, because of industry trends moving the UC384X into higher and higher frequency applications, the UC384XB is guaranteed to within ±10% at 250 kHz. In many noise–sensitive applications it may be desirable to frequency–lock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 18. For reliable locking, the free–running oscillator frequency should be set about 10% less than the clock frequency. A method for multi–unit synchronization is shown in Figure 19. By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved to realize output deadtimes of greater than 70%.

Rf(min) ≈

3.0 (1.0 V) + 1.4 V = 8800 Ω 0.5 mA


The UC3844B, UC3845B operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin 1). Thus the error signal controls the peak inductor current on a cycle–by–cycle basis. The Current Sense Comparator PWM Latch configuration used ensures that only a single pulse appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground–referenced sense resistor RS in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at Pin 1 where: Ipk =

V(Pin 1) – 1.4 V 3 RS


1.0 V RS

When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 20. The two external diodes are used to compensate the internal diodes, yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the Ipk(max) clamp voltage. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability (refer to Figure 24).

Error Amplifier

A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical dc voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz with 57 degrees of phase margin (Figure 6). The non–inverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is –2.0 µA which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. The Error Amp Output (Pin 1) is provided for external loop compensation (Figure 29). The output voltage is offset by two diode drops (≈1.4 V) and divided by three before it connects to the inverting input of the Current Sense


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designer added flexibility in tailoring the drive voltage independent of VCC. A zener clamp is typically connected to this input when driving power MOSFETs in systems where VCC is greater than 20 V. Figure 23 shows proper power and control ground connections in a current–sensing power MOSFET application.

Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stage is enabled. The positive power supply terminal (VCC) and the reference output (Vref) are each monitored by separate comparators. Each has built–in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The VCC comparator upper and lower thresholds are 16 V/10 V for the UCX844B, and 8.4 V/7.6 V for the UCX845B. The Vref comparator upper and lower thresholds are 3.6 V/3.4 V. The large hysteresis and low startup current of the UCX844B makes it ideally suited in off–line converter applications where efficient bootstrap startup techniques are required (Figure 30). The UCX845B is intended for lower voltage dc–to–dc converter applications. A 36 V zener is connected as a shunt regulator from VCC to ground. Its purpose is to protect the IC from excessive voltage that can occur during system startup. The minimum operating voltage for the UCX844B is 11 V and 8.2 V for the UCX845B.

Reference

The 5.0 V bandgap reference is trimmed to ±1.0% tolerance at TJ = 25°C on the UC284XB, and ±2.0% on the UC384XB. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has short–circuit protection and is capable of providing in excess of 20 mA for powering additional control system circuitry. Design Considerations

Do not attempt to construct the converter on wire–wrap or plug–in prototype boards. High frequency circuit layout techniques are imperative to prevent pulse–width jitter. This is usually caused by excessive noise pick–up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low–current signal and high–current switch and output grounds returning on separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1 µF) connected directly to VCC, VC, and Vref may be required depending upon circuit layout. This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise–generating components.

Output

These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFETs. It is capable of up to ±1.0 A peak drive current and has a typical rise and fall time of 50 ns with a 1.0 nF load. Additional internal circuitry has been added to keep the Output in a sinking mode whenever an undervoltage lockout is active. This characteristic eliminates the need for an external pull–down resistor. The SO–14 surface mount package provides separate pins for VC (output supply) and Power Ground. Proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the Ipk(max) clamp level. The separate VC supply input allows the

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Figure 10. Error Amplifier Gain and Phase versus Frequency

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Figure 12. Demag Comparator Threshold versus Temperature


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Figure 22. Protection Threshold Level on VOVP versus Temperature

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Figure 24. Propagation Delay (VOVP > 2.58 V to Vout Low) versus Temperature


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Figure 26. Current Sense Voltage Threshold Standby Mode versus Temperature

PIN FUNCTION DESCRIPTION Pin

Name

Description

1

VCC

This pin is the positive supply of the IC. The operating voltage range after startup is 9.0 to 14.5 V.

2

VC

The output high state (VOH) is set by the voltage applied to this pin. With a separate connection to the power source, it can reduce the effects of switching noise on the control circuitry.

3

Output

Peak currents up to 750 mA can be sourced or sunk, suitable for driving either MOSFET or Bipolar transistors. This output pin must be shunted by a Schottky diode, 1N5819 or equivalent.

4

Gnd

The ground pin is a single return, typically connected back to the power source; it is used as control and power ground.

5

Foldback Input

The foldback function provides overload protection. Feeding the foldback input with a portion of the VCC voltage (1.0 V max) establishes on the system control loop a foldback characteristic allowing a smoother startup and sharper overload protection. Above 1.0 V the foldback input is inactive.

6


When the overvoltage protection pin receives a voltage greater than 17 V, the device is disabled and requires a complete restart sequence. The overvoltage level is programmable.

7

Current Sense Input

A voltage proportional to the current flowing into the power switch is connected to this input. The PWM latch uses this information to terminate the conduction of the output buffer when working in a current mode of operation. A maximum level of 1.0 V allows either current or voltage mode operation.

8

Demagnetization Detection

A voltage delivered by an auxiliary transformer winding provides to the demagnetization pin an indication of the magnetization state of the flyback transformer. A zero voltage detection corresponds to complete core saturation. The demagnetization detection ensures a discontinuous mode of operation. This function can be inhibited by connecting Pin 8 to Gnd.

9

Synchronization Input

The synchronization input pin can be activated with either a negative pulse going from a level between 0.7 V and 3.7 V to Gnd or a positive pulse going from a level between 0.7 V and 3.7 V up to a level higher than 3.7 V. The oscillator runs free when Pin 9 is connected to Gnd.

10

CT

The normal mode oscillator frequency is programmed by the capacitor CT choice together with the Rref resistance value. CT, connected between Pin 10 and Gnd, generates the oscillator sawtooth.

11

Soft–Start/Dmax/ Voltage–Mode

A capacitor, resistor or a voltage source connected to this pin limits the switching duty–cycle. This pin can be used as a voltage mode control input. By connecting Pin 11 to Ground, the MC44603A can be shut down.

12

RP Standby

A voltage level applied to the RP Standby pin determines the output power level at which the oscillator will turn into the reduced frequency mode of operation (i.e. standby mode). An internal hysteresis comparator allows to return in the normal mode at a higher output power level.

13

E/A Out

The error amplifier output is made available for loop compensation.

14

Voltage Feedback

This is the inverting input of the Error Amplifier. It can be connected to the switching power supply output through an optical (or other) feedback loop.

15

RF Standby

The reduced frequency or standby frequency programming is made by the RF Standby resistance choice.

16

Rref

Rref sets the internal reference current. The internal reference current ranges from 100 µA to 500 µA. This requires that 5.0 kΩ ≤ Rref ≤ 25 kΩ.


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OPERATING DESCRIPTION .

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A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical dc voltage gain of 70 dB. The noninverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current with the inverting input at 2.5 V is –2.0 µA. This can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. The Error Amp output (Pin 13) is provided for external loop compensation. The output voltage is offset by two diode drops (≈ 1.4 V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Output (Pin 3) when Pin 13 is at its lowest state (VOL). The Error Amp minimum feedback resistance is limited by the amplifier’s minimum source current (0.2 mA) and the required output voltage (VOH) to reach the current sense comparator’s 1.0 V clamp level:

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The MC44603A can operate as a current mode controller or as a voltage mode controller. In current mode operation, the MC44603A uses the current sense comparator. The output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier output

3.0 (1.0 V) ) 1.4 V + 22 k 0.2 mA


MC44603A (Pin 13). Thus, the error signal controls the peak inductor current on a cycle–by–cycle basis. The Current Sense Comparator PWM Latch ensures that only a single pulse appears at the Source Output during the appropriate oscillator cycle. The inductor current is converted to a voltage by inserting the ground referenced sense resistor RS in series with the power switch Q1. This voltage is monitored by the Current Sense Input (Pin 7) and compared to a level derived from the Error Amp output. The peak inductor current under normal operating conditions is controlled by the voltage at Pin 13 where: Ipk [

the discharge current source has to be higher than the charge current to be able to decrease the CT voltage (refer to Figure 35). This condition is performed, its value being (2.0 Iref) in normal working and (0.4 Iref + 0.5 IF Stby in standby mode). 7 $" + 7 * !

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Figure 33. Output Totem Pole Series gate resistor, R2, will dampen any high frequency oscillations caused by the MOSFET input capacitance and any series wiring inductance in the gate–source circuit. Diode D is required if the negative current into the output drive pin exceeds 15 mA.

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Two comparators are used to generate the sawtooth. They compare the CT voltage to the oscillator valley (1.6 V) and peak reference (3.6 V) values. A latch (Ldisch) memorizes the oscillator state. In addition to the charge and discharge cycles, a third state can exist. This phase can be produced when, at the end of the discharge phase, the oscillator has to wait for a synchronization or demagnetization pulse before restarting. During this delay, the CT voltage must remain equal to the oscillator valley value (]1.6 V). So, a third regulated current source IRegul controlled by COSC Regul, is connected to CT in order to perfectly compensate the (0.4 Iref) current source that permanently supplies CT. The maximum duty cycle is 80%. Indeed, the on–time is allowed only during the oscillator capacitor charge.

Oscillator

The oscillator is a very accurate sawtooth generator that can work either in free mode or in synchronization mode. In this second mode, the oscillator stops in the low state and waits for a demagnetization or a synchronization pulse to start a new charging cycle. • The Sawtooth Generation:

In the steady state, the oscillator voltage varies between about 1.6 V and 3.6 V. The sawtooth is obtained by charging and discharging an external capacitor CT (Pin 10), using two distinct current sources = Icharge and Idischarge. In fact, CT is permanently connected to the charging current source (0.4 Iref) and so,


MC44603A – equal to zero for the dead–time with generally some – ringing (refer to Figure 37).

Consequently: Tcharge = CT x ∆V/Icharge Tdischarge = CT x ∆V/Idischarge where: Tcharge is the oscillator charge time ∆V is the oscillator peak–to–peak value Icharge is the oscillator charge current and Tdischarge is the oscillator discharge time Idischarge is the oscillator discharge current

That is why, the MC44603A demagnetization detection consists of a comparator that can compare the auxiliary winding voltage to a reference that is typically equal to 65 mV.

So, as fS = 1 /(Tcharge + Tdischarge) when the Regul arrangement is not activated, the operating frequency can be obtained from the graph in Figure 1. NOTE: The output is disabled by the signal VOSC prot when VCT is lower than 1.0 V (refer to Figure 30).

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To enable the output, the LOSC latch complementary output must be low. Reset is activated by the Ldisch output during the discharge phase. To restart, the LOSC has to be set (refer to Figure 34). To perform this, the demagnetization signal and the synchronization must be low.

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Figure 37. Demagnetization Detection

A diode D has been incorporated to clamp the positive applied voltages while an active clamping system limits the negative voltages to typically –0.33 V. This negative clamp level is sufficient to avoid the substrate diode switching on. In addition to the comparator, a latch system has been incorporated in order to keep the demagnetization block output level low as soon as a voltage lower than 65 mV is detected and as long as a new restart is produced (high level on the output) (refer to Figure 38). This process prevents ringing on the signal at Pin 8 from disrupting the demagnetization detection. This results in a very accurate demagnetization detection. The demagnetization block output is also directly connected to the output, disabling it during the demagnetization phase (refer to Figure 33). NOTE: The demagnetization detection can be inhibited by connecting Pin 8 to the ground.

• Synchronization:

The synchronization block consists of two comparators that compare the synchronization signal (external) to 0.7 and 3.7 V (typical values). The comparators’ outputs are connected to the input of an AND gate so that the final output of the block should be: – high when 0.7 < SYNC < 3.7 V – low in the other cases. As a low level is necessary to enable the output, synchronized low level pulses have to be generated on the output of the synchronization block. If synchronization is not required, the Pin 9 must be connected to the ground. #$ 30''(!

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• Demagnetization:

In flyback applications, a good means to detect magnetic saturation of the transformer core, or demagnetization, consists in using the auxiliary winding voltage. This voltage is:

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MC44603A Standby

where fS is the normal working switching frequency.

• Power Losses in a Classical Flyback Structure

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where RS is the resistor used to measure the power switch current. Thus, the input power is proportional to VCS2 (VCS being the internal current sense comparator input). That is why the standby detection is performed by creating a VCS threshold. An internal current source (0.4 x Iref) sets the threshold level by connecting a resistor to Pin 12. As depicted in Figure 40, the standby comparator noninverting input voltage is typically equal to (3.0 x VCS + VF) while the inverter input value is (VR P Stby + VF).

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Figure 39. Power Losses in a Classical Flyback Structure

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In a classical flyback (as depicted in Figure 39), the standby losses mainly consist of the energy waste due to: – the startup resistor Rstartup – the consumption of the IC and the power – switch control – the inrush current limitation resistor RICL – the switching losses in the power switch – the snubber and clamping network

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The VCS threshold level is typically equal to [(VR P Stby)/3] and if the corresponding power threshold is labelled PthL:

PICL only depends on the current drawn from the mains. Losses can be considered constant. This waste of energy decreases when the standby losses are reduced. Pcontrol increases when the oscillator frequency is increased (each switching requires some energy to turn on the power switch). PSW and PSN–CLN are proportional to the switching frequency. Consequently, standby losses can be minimized by decreasing the switching frequency as much as possible. The MC44603A was designed to operate at a standby frequency lower than the normal working one.

PthL + 0.5 x L x

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• Standby Power Calculations with MC44603A

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Thus, when the power drawn by the converter decreases, VCS decreases and when VCS becomes lower than [VCS–th x (VR P Stby)/3], the standby mode is activated. This results in an oscillator discharge current reduction in order to increase the oscillator period and to diminish the switching frequency. As it is represented in Figure 40, the (0.8 x Iref) current source is disconnected and is replaced by a lower value one (0.25 x IF Stby). Where: IF Stby = Vref/RF Stby

During a switching period, the energy drawn by the transformer during the on–time to be transferred to the output during the off–time, is equal to: E + 1 x L x Ipk2 2

where: – L is the transformer primary inductor, – lpk is the inductor peak current. Input power is labelled Pin:

In order to prevent undesired mode switching when power is close to the threshold value, a hysteresis that is

Pin + 0.5 x L x Ipk2 x fS


MC44603A proportional to VR P Stby is incorporated creating a second VCS threshold level that is equal to [2.5 x (VR P Stby)/3]. When the standby comparator output is high, a second current source (0.6 x Iref) is connected to Pin 12. Finally, the standby mode function can be shown graphically in Figure 41.

Using the internal current source (0.4 Iref), the Pin 11 voltage can easily be set by connecting a resistor to this pin. If a capacitor is connected to Pin 11, the voltage increases from 0 to its maximum value progressively (refer to Figure 44), thereby, implementing a soft–start. The soft–start capacitor is discharged internally when the VCC (Pin 1) voltage drops below 9.0 V.

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If no external component is connected to Pin 11, an internal zener diode clamps the Pin 11 voltage to a value VZ that is higher than the oscillator peak value, disabling soft–start and maximum duty cycle limitation.

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Figure 41. Dynamic Mode Change

Foldback

As depicted in Figures 32 and 48, the foldback input (Pin 5) can be used to reduce the maximum VCS value, providing foldback protection. The foldback arrangement is a programmable peak current limitation. If the output load is increased, the required converter peak current becomes higher and VCS increases until it reaches its maximum value (normally, VCS max = 1.0 V). Then, if the output load keeps on increasing, the system is unable to supply enough energy to maintain the output voltages in regulation. Consequently, the decreasing output can be applied to Pin 5, in order to limit the maximum peak current. In this way, the well known foldback characteristic can be obtained (refer to Figure 45).

This curve shows that there are two power threshold levels: – the low one: PthL fixed by VR P Stby

– the high one: PthH + (2.5)2 x PthL x PthH + 6.25 x PthL x

fStby fS

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Maximum Duty Cycle and Soft–Start Control

Maximum duty cycle can be limited to values less than 80% by utilizing the Dmax and soft–start control. As depicted in Figure 42, the Pin 11 voltage is compared to the oscillator sawtooth. 7

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Figure 43. Maximum Duty Cycle Control


MC44603A Undervoltage Lockout Section

If no external component is connected to Pin 6, the comparator noninverting input voltage is nearly equal to: 2.0 k ǒ11.6 k Ǔ x VCC ) 2.0 k

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Figure 47. VCC Management

As depicted in Figure 47, an undervoltage lockout has been incorporated to garantee that the IC is fully functional before allowing system operation. This block particularly, produces Vref (Pin 16 voltage) and Iref that is determined by the resistor Rref connected between Pin 16 and the ground: V Iref + ref where Vref + 2.5 V (typically) Rref

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Another resistor is connected to the Reference Block: RF Stby that is used to fix the standby frequency. In addition to this, VCC is compared to a second threshold level that is nearly equal to 9.0 V (Vdisable1). UVLO1 is generated to reset the maximum duty cycle and soft–start block disabling the output stage as soon as VCC becomes lower than Vdisable1. In this way, the circuit is reset and made ready for the next startup, before the reference block is disabled (refer to Figure 29). Finally, the upper limit for the minimum normal operating voltage is 9.4 V (maximum value of Vdisable1) and so the minimum hysteresis is 4.2 V. ((Vstup–th) min = 13.6 V). The large hysteresis and the low startup current of the MC44603A make it ideally suited for off–line converter applications where efficient bootstrap startup techniques are required.

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A delay latch (2.0 µs) is incorporated in order to sense overvoltages that last at least 2.0 µs. If this condition is achieved, VOVP out, the delay latch output, becomes high. As this level is brought back to the input through an OR gate, VOVP out remains high (disabling the IC output) until Vref is disabled. Consequently, when an overvoltage longer than 2.0 µs is detected, the output is disabled until VCC is removed and then re–applied. The VCC is connected after Vref has reached steady state in order to limit the circuit startup consumption. The overvoltage section is enabled 5.0 µs after the regulator has started to allow the reference Vref to stabilize. By connecting an external resistor to Pin 6, the threshold VCC level can be changed. **

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Figure 48. 250 W Input Power Off–Line Flyback Converter with MOSFET Switch

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MC44603A 250 W Input Power Fly–Back Converter 185 V – 270 V Mains Range MC44603AP & MTP6N60E Tests Line Regulation

Conditions

Results

Vin = 185 Vac to 270 Vac Fmains = 50 Hz Iout = 0.6 A Iout = 2.0 A Iout = 2.0 A Iout = 2.0 A

10 mV 10 mV 10 mV 20 mV

Load Regulation 150 V

Vin = 220 Vac Iout = 0.3 A to 0.6 A

50 mV

Cross Regulation

Vin = 220 Vac Iout (150 V) = 0.6 A Iout (30 V) = 0 A to 2.0 A Iout (14 V) = 2.0 A Iout (7.0 V) = 2.0 A

150 V 130 V 114 V 7.0 V

150 V

< 1.0 mV

Efficiency

Vin = 220 Vac, Pin = 250 W

81%

Standby Mode P input

Vin = 220 Vac, Pout = 0 W

3.3 W

Switching Frequency

20 kHz fully stable

Output Short Circuit

Pout (max) = 270 W

Safe on all outputs

Startup

Pin = 250 W

Vac = 160 V


) "# =& 8! ) (& < " 81) The MC44604 is an enhanced high performance controller that is specifically designed for off–line and dc–to–dc converter applications. Its high current totem pole output is ideally suited for driving a power MOSFET. The MC44604 is an evolution of the MC44603A. Like the MC44603A, the MC44604 has been optimized to operate with universal ac mains voltage from 80 V to 280 V. It also offers enhanced safety and reliable power management thanks to its protection features (foldback, overvoltage detection, soft–start, accurate demagnetization detection). In addition, the MC44604 offers a new efficient way to reduce the standby operating power by means of a so–called pulsed mode standby operation of the converter, significantly reducing the converter consumption in standby mode.

http://onsemi.com MARKING DIAGRAM 16 PDIP–16 P SUFFIX CASE 648

16

1

1


Current Mode Controller

• • • •

Operation Up to 250 kHz Output Switching Frequency Inherent Feed Forward Compensation Latching PWM for Cycle–by–Cycle Current Limiting Oscillator with Precise Frequency Control

PIN CONNECTIONS **

2 7

*

!(/@ G(( 5 !

! !

#

" : ;5 + !

"

# : ;5 ! !

'/(01 + !

*'(5 : ;5 + !

< 2.58 V to Vout Low) Protection Level on VCC TA = 0° to +70°C TA = –25° to +85°C

VCC prot

Input Resistance TA = 0° to +70°C TA = –25° to +85°C

V

–

kΩ

FOLDBACK SECTION (Note 3) Current Sense Voltage Threshold (Vfoldback (pin5) = 0.9 V)

5

Vcs–th

0.84

0.88

0.89

V

Foldback Input Bias Current (Vfoldback (pin5) = 0 V)

5

Ifoldback–lb

–6.0

–2.0

–

µA

12

Vcl

4.5

4.7

4.9

V

15

Iinit/Iref

126

140

154

–

Tinit

–

–

1.0

µs

CLAMP ERROR AMPLIFIER INPUT Clamp Level (@ l = 30 mA) STANDBY PULSED MODE SECTION Standby Initialization Current Ratio (S1 closed) Minimum Initialization Current Pulse Width* Standby On Detection Current Ratio

15

Idet/Iref

0.34

0.38

0.42

–

Standby Regulation Current Ratio

15

Ireg/Iref

18

20.5

23

–

Standby Bias Current (S1 and S2 open; 0 V t Vpin15 t Vstup–th)**

15

Istby–ib

–1.0

–

2.0

µA

* This is the minimum time during which the pin 15 current must be higher than Iinit to enable the detection of the transition normal to standby mode. **Tested using VCC = 6.0 V, 9.0 V, 13.5 V, the MC44604 being off. STANDBY CURRENT SET 9

Peak Standby Current Setting Ratio TA = 0° to +70°C TA = –25° to +85°C Standby Current Sense Threshold Ratio* *Tested using Vpin9 = 0.2 V, 0.4 V, 0.6 V, 0.8 V, 1.0 V.

7

– Ipk–stby/Iref –

0.37 0.36

0.4 0.4

0.43 0.44

Vpin9/Vcs–st

2.4

2.6

2.9

– 16

0.3 20

0.45 24

–

TOTAL DEVICE Power Supply Current Startup* Operating TA = –25° to +85°C (Note 2)

ICC

Power Supply Zener Voltage (ICC = 25 mA)

VZ

18.5

–

–

V

–

–

155

–

°C

Thermal Shutdown

mA

*Tested using VCC = 6.0 V, 9.0 V, 13.5 V, the MC44604 being off. 1. Adjust VCC above the start–up threshold before setting to 12 V. 2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 3. This function can be inhibited by connecting pin 5 to VCC.


120

120

115

115

PROPAGATION DELAY ( s )


MC44604

110 105 100 95 90 85 80 –50

–25

0

25

50

75

105 100 95 90 85 80 –50

100

0

25

50

75


Figure 1. Propagation Delay Current Sense Input vs. Temperature

Figure 2. Propagation Delay Current Sense Input in Standby vs. Temperature

100


3.0

3.1

3.0

2.9

2.8 –50

–25

0

25

50

75

2.5

2.0

1.5

1.0 –50

100

–25

0

25

50

75



Figure 3. Current Sense Gain vs. Temperature

Figure 4. Propagation Delay Current (Vovp > 2.58 V to Vout Low) vs. Temperature

2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 –50

100

80

V , DEMAG COMPARATOR demag–th THRESHOLD (mV)

Vstup–th –Vdisable2 , DELTA VCCDURING STAND–BY (V)

–25


3.2 A VCS,CURRENT SENSE GAIN

110

–25

0

25

50

75

100

75 70 65 60 55 50 –50


–25

0

25

50

75


Figure 5. Delta VCC During Standby

Figure 6. Demag Comparator Threshold vs. Temperature


100

MC44604 160

70

0.890 0.885 V cs–th,CURRENT SENSE THRESHOLD (V), Vph 9 = Q9V

60 50 GAIN (dB)

40 30 – 60 20 10 0 –10

0.875 0.870 0.865 0.860 0.855 0.850 0.845

–40 10000

–20 1

10

100

1000

0.840 –50

F, FREQUENCY (kHz)

–25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C)

100

Figure 8. Current Sense Voltage Threshold vs. Temperature 0.42

49000

I /I det ref (Standby On Detection Current Ratio)

FOSC, OSCILLATOR FREQUENCY (Hz)

Figure 7. Error Amplifier Gain and Phase vs. Frequency

48000 47000 46000 45000 44000 43000 42000 41000 40000 –50

–25

0 25 50 75 TA, AMBIENT TEMPERATURE (°C)

100

0.41 0.40 0.39 0.38 0.37 0.36 0.35 0.34 –50



100

Figure 10. Standby On Detection Current Ratio vs. Temperature 2.9

156 V ph 9/ V cs–st,STANDBY CURRENT SENSE THRESHOLD RATIO

I /I init ref (Standby Initialization Current Ratio)

Vpin5 = 0.9 V

0.880

151 146 141 136 131 126 –50

2.8

2.7

2.6 2.5

2.4 –25

0

25

50

75

100

0


0.5

1

1.5

2

Vpin9, STANDBY CURRENT SET (V)

Figure 11. Standby Initialization Current Ratio vs. Temperature


Figure 12. Standby Current Sense Threshold Ratio

2.5

MC44604 23.0

IPK–STBY /I ref , PEAK STANBY CURRENT SETTING RATIO

Ireg /I ref , STANDBY REGULATION CURRENT RATIO

0.44 0.43 0.42 0.41 0.40 0.39 0.38 0.37 0.36 –50

–25

0

25

50

75

100

22.5 22.0 21.5 21.0 20.5 20.0 19.5 19.0 18.5 18.0 –50

0

25

50

75


Figure 13. Peak Standby Current Setting Ratio vs. Temperature

Figure 14. Standby Regulation Current Ratio vs. Temperature

1.2

100

1.8 V OH , SOURCE OUTPUT SATURATION VOLTAGE (V)

Vol , SINK OUTPUT SATURATION VOLTAGE (V)

–25


1.0 0.8 0.6 0.4 0.2

1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2

0

0

100

200

300

400

0

500

0

100

Isink, SINK OUTPUT CURRENT (mA)

Figure 15. Sink Output Saturation Voltage vs. Sink Current

300

400

500

Figure 16. Source Output Saturation Voltage vs. Source Current

0.45

24

0.40

ICC , SUPPLY CURRENT (mA)

START UP CURRENT (mA)

200

Isource, OUTPUT SOURCE CURRENT (mA)

0.35 0.30 0.25 0.20 0.15 0.10 0.05 0

20 16 12 8 4 0

0

2

4

6 8 10 VCC, SUPPLY VOLTAGE (V)

12

14

Figure 17. Start–up Current vs. VCC

0

2

4 6 8 10 12 VCC, SUPPLY VOLTAGE (V)

14

Figure 18. Supply Current vs. Supply Voltage


16

MC44604 15.5 V CC, OVERVOLTAGE THRESHOLD (Vcc_prot )

18.0

14.5

VOLTAGE (V)

13.5

Vstup, STARTUP THRESHOLD VOLTAGE

12.5 11.5 10.5 Vdisable1, UVLO1

9.5 8.5

Vdisable2, UVLO2

7.5 6.5 –50

–25

0

25

50

75

17.5

17.0

16.5

16.0 –50

100

–25

Figure 19. Start–up Threshold, UVLO1, UVLO2 Voltage vs. Temperature

50

75

100

2.60 V ref , REFERENCE VOLTAGE (V)

4.85 4.80

2.55

4.75 4.70

2.50

4.65 4.60

2.45

4.55 –25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C)

2.40 –50

100

Figure 21. Clamp Error Amplifier Input vs. Temperature


21.5 21.0 20.5 20.0 19.5 18.0 –50

–25

0

100


22.0

Y 2 , ZENER VOLTAGE (V)

V , PIN 12 CLAMP LEVEL cl

25

Figure 20. Protection Level on VCC vs. Temperature

4.90

4.50 –50

0



25

50

75


Figure 23. Power Supply Zener Voltage vs. Temperature


100

MC44604 Name

Pin

Pin Description

1

VCC

This pin is the positive supply of the IC.

2

VC

The output high state, VOH, is set by the voltage applied to this pin. With a separate connection to the power source, it gives the possibility to set by means of an external resistor the output source current at a different value than the sink current.

3

Output

The output current capability is suited for driving a power MOSFET. A Bipolar transistor can also be driven for low power applications. The maximum on–time of the duty cycle can last up to 80% of the switching period.

4

Gnd

The ground pin is a single return typically connected back to the power source, it is used as control and power ground.

5

Foldback Input

The foldback function ensures an overload protection. Feeding the foldback input with a portion of the VCC voltage (1 V max) establishes on the system control loop a foldback characteristic allowing a smoother start–up and a sharper overload protection. The foldback action performs an active current sense clamping reduction. Above 1 V the foldback input is no more active.

6


When the overvoltage protection pin receives a voltage greater than 17 V the device gets disabled and requires a complete restart sequence. The overvoltage level is programmable.

7

Current Sense Input

A voltage proportional to the current flowing into the power switch is connected to this input. The PWM latch uses this information to terminate the conduction of the output buffer when operating in current mode. A maximum level of 1 V allows to limit the inductor current either in current or voltage mode of operation.

8


A voltage delivered by an auxiliary transformer winding provides to the demagnetization pin an indication of the magnetization state of the flyback energy reservoir. A zero voltage detection corresponds to a complete core demagnetization. The demagnetization detection ensures a discontinuous mode of operation. This function can be inhibited by connecting Pin 8 to GND.

9

Standby Current Set

Using an external resistor connected to this pin, the standby burst mode peak current can be adjusted.

10

CT

The normal mode oscillator frequency is programmed by the capacitor CT choice together with the Rref resistance value. CT, connected between pin 10 and GND, generates the oscillator sawtooth.

11

Soft–Start/Dmax/Voltage–Mode

A capacitor or a resistor or a voltage source connected to this pin can temporary or permanently control the effective switching duty–cycle. This pin can be used as a voltage mode control input. By connecting pin 11 to Ground, the MC44604 can be shut down.

12

Clamp Error Amplifier Input

In normal mode, the current drawn from this pin, is used by the Error Amplifier to perform the regulation. A 4.7 V zener diode clamps the voltage of this pin.

13

E/A Out


14

Voltage Feedback

This is the inverting input of the Error Amplifier. It uses a voltage that is built up using the current drawn from the pin 12.

15

Standby Management

This block is designed to detect the standby mode. It particularly determines if the circuit must work in standby or in normal mode at each start–up. For that, it uses an information given by an external arrangement consisting of an opto–coupler. In standby mode, this block makes the circuit work in the standby configuration, and the current injected in the pin 15 is used to perform the regulation. In normal mode, this pin is internally connected to the pin 12.

16

RREF

The RREF values fixes the internal reference current which is used to perform the precise oscillator waveform. The current range goes from 100 µA up to 500 µA.


MC44604 Operating Description Schematics

V CC V stup–th V disable1 V disable2

V ref

UVLO1

V Pin 11 (Soft–Start)

ÎÎÎ ÎÎÎ

Output (Pin 3)

I CC 17 mA 0.3 mA

Figure 24. Switching Off Behavior



V CC

Loop Failure

No–Take Over Startup

>2.0 s

Restart

V CC prot V stup–th

Normal Mode

Vdisable1 V disable2

V ref

UVLO1

V Pin 11 (Soft–Start)

V OVP Out

Output

I CC 17 mA

ÎÎ ÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ

0.3 mA

Figure 25. Starting Behavior and Overvoltage


ÎÎÎ ÎÎÎ ÎÎÎ


Vref

VCSS + 1.6 V

Soft–Start

Internal Clamp

External Clamp

VCT 3.6 V VCT low 1.6 V

VOSC

Output (Pin 3)

Figure 26. Soft–Start and Dmax

V demag in

Output (Pin 3)

Vdemag out

V demag in

Demagnetization Management

V demag out Oscillator

Buffer

Figure 27. Demagnetization


Output

MC44604 Error Amplifier


A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical DC voltage gain of 70 dB. The non–inverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current with the inverting input at 2.5 V is –2.0 µA. This can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. The Error Amp Output (Pin 13) is provided for external loop compensation. The output voltage is offset by two diodes drops ([ 1.4 V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Source Output (Pin 3) when Pin 13 is at its lowest state (VOL). This occurs when the power supply is operating and the load is removed, or at the beginning of a soft–start interval. The Error Amp minimum feedback resistance is limited by the amplifier’s minimum source current (0.2 mA) and the required output voltage (VOH) to reach the current sense comparator’s 1.0 V clamp level:

The MC44604 can operate as a current mode controller and/or as a voltage mode controller. In current mode operation, the MC44604 uses the current sense comparator, where the output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier output (Pin 13). Thus the error signal controls the peak inductor current on a cycle–by–cycle basis. The Current Sense Comparator PWM Latch configuration used ensures that only a single pulse appears at the Source Output during the appropriate oscillator cycle. The inductor current is converted to a voltage by inserting the ground referenced sense resistor RS in series with the power switch Q1. In normal mode, this voltage is monitored by the Current Sense Input (Pin 7) and compared to a level derived from the Error Amp output. The peak inductor current under normal operating conditions is controlled by the voltage at Pin 13 where:

R [ f (min)

V I

pk

+

RFB C1

Rf

I

1.0 mA

pk(max)

[

1·0 V R S

Error Amplifier

13

Vin

2R

14 2.5 V

VC

R

Voltage Feedback Input R1

* 1·4 V (pin13) 3R S

The Current Sense Comparator threshold is internally clamped to 1.0 V. Therefore the maximum peak switch current is:

3·0(1·0 V) ) 1·4 V + 22 kΩ 0·2 mA

Compensation

[

Foldback 5 Input +

VOSCPROT R2 Q1

Vdemag out

1.0 V

3

VOSC (from Oscillator) Thermal Protection

4.7 W Pin 12 R2

Gnd

14

UVLO

Current Sense Comparator

R Q R

4

R3

S PWM Latch Substrate

MC44604 Current Sense Comparator

Figure 28. Error Amplifier Compensation

Current Sense 7

In a preferred embodiment, the feedback signal (current) is drawn from the pin 12 that is connected to the pin 15 in normal mode (Note 1). Using a resistor connected on pin 12, this current generates a voltage that is the input signal of the error amplifier arrangement.

C

R RS

Figure 29. Output Totem Pole

Oscillator Note 1. The error amplifier is not used in the standby mode regulation.

The oscillator is a very accurate sawtooth generator.


MC44604 The Sawtooth Generation

order to perfectly compensate the (0.4 Iref) current source that permanently supplies CT. On–time is only allowed during the oscillator capacitor charge. So, the maximum duty cycle is 80%. (Note 1) The demagnetization condition is taken into account by a second latch (Losc). (Refer to demagnetization § for further details.)

In the steady state, the oscillator voltage varies between about 1.6 V and 3.6 V. Indeed, the sawtooth is obtained by charging and discharging an external capacitor CT (Pin 10), using two distinct current sources = Icharge and Idischarge. In fact, CT is permanently connected to the charging current source (0.4 Iref) and so, the discharge current source has to be higher than the charge one to be able to decrease the CT voltage. This condition is performed, its value being (2 Iref). Two comparators are used to generate the sawtooth. They compare the CT voltage to the oscillator valley and peak values. The comparison to the low value enables to detect the end of the discharge phase while the comparison to the high value determines when the charge cycle must be stopped. A latch (LDISCH) memorizes the oscillator state.


The oscillator frequency can be deducted using the following equations: .

T + C • Vń I charge T charge T + C • Vń I discharge T discharge

where: Tcharge is the oscillator charge time V is the oscillator peak to peak value Icharge is the oscillator charge current and Tdischarge is the oscillator discharge time Idischarge is the oscillator discharge current So, as: fosc = 1 /(Tcharge + Tdischarge) if the REGUL arrangement is not activated, the following equation can be obtained:

Vref 0.4 IREF CVOS PROT

Vosc prot

1V

Vosc CT< 1.6 V

COSC LOW

DISCHARGE

1.6 V

R COSC HIGH 10 CT

S

Q

Q

LOSC

DISCH

f osc X

R Vdemag out

S

0·395 R •C T ref

Demagnetization Block (Note 2)

3.6 V

COSC REGUL 0

1

To enable the output, the Losc latch complementary output must be low. Now, this latch reset is activated by the LDISCH output during the discharge phase. So, to restart, the Losc has to be set (refer to Figure 30). To perform this, the demagnetization signal must be low. In a fly–back, a good means to detect the demagnetization consists in using the VCC winding voltage. Indeed this voltage is: — negative during the on–time, — positive during the off–time, — equal to zero for the dead–time with generally a ringing (refer to Figure 31). That is why, the MC44604 demagnetization detection consists of a comparator that can compare the VCC winding voltage to a reference that is typically equal to 65 mV.

1

0 IREGUL

IDISCHARGE MC44604

Figure 30. Oscillator

Now, in addition to the charge and discharge cycles, a third state can exist. This phase can be produced when at the end of the discharge phase, the oscillator has to wait for a demagnetization pulse before re–starting. During this delay, the CT voltage must remain equal to the oscillator valley value (X1.6 V). So, a third regulated current source IREGUL controlled by COSC REGUL, is connected to CT in

Note 1. The output is disabled by the signal Vosc prot when VCT is lower than 1 V. (Refer to Figure 29 and Figure 30.) Note 2. The demagnetization detection can be inhibited by connecting pin 8 to the ground.


MC44604 Output Control

Vref 0.75 V VPin 8

0.4 Iref

Pin 11

Zero Current Detection

DZ 65 mV

Soft Start Capacitor

–0.33 V

2.4 V

Dmax

Output Buffer

VOSC Oscillator MC44604

On–Time

Off–Time Dead–Time

Figure 33. Dmax and Soft–Start Block Diagram Figure 31. Demagnetization Detection

Maximum Duty Cycle and Soft–Start Control A diode D has been incorporated to clamp the positive applied voltages while an active clamping system limits the negative voltages to typically –0.33 V. This negative clamp level is sufficient to avoid the substrate diode switching on. In addition to the comparator, a latch system has been incorporated in order to keep the demagnetization block output level low as soon as a voltage lower than 65 mV is detected and as long as a new restart is produced (high level on the output) (refer to Figure 33). This process avoids that any ringing on the signal used on the pin 8, disrupts the demagnetization detection. Finally, this method results in a very accurate demagnetization detection. For a higher safety, the demagnetization block output is also directly connected to the output, disabling it during the demagnetization phase (refer to Figure 29).

As explained in the paragraph “oscillator”, the duty cycle cannot be more than 80%. Now, using the Dmax and soft–start control, this duty cycle can be limited to a lower value. Indeed as depicted in Figure 34, the pin 11 voltage is compared to the oscillator sawtooth, so that the MC44604 output should be disabled as soon as the pin 11 level becomes lower than the oscillator voltage (refer to Figure 27 and to Figure 25). Pin 11

Voltage

VCT (Pin 10) Dmax

Figure 34. Maximum Duty Cycle Control Oscillator

Output

Now, using the internal current source (0,4 Iref), the pin 11 voltage can easily be fixed by connecting a resistor to this pin. If a capacitor is connected to pin 11 (without any resistor or in parallel to a resistor for instance), the pin 11 voltage increases from 0 to its maximum value progressively (refer to Figure 26). Thus, the allowed maximum duty cycle grows for a delay depending on the capacitor value (and the resistor value when a resistor is connected). So, this pin can be used to limit the duty cycle during the start–up phase and thus, to perform a soft–start.

Buffer R Q Demag S

VCC Negative Active Clamping System

Vdemag out

Pin 8

65 mV C DEM

D

Figure 32. Demagnetization Block


MC44604 Pin 11 RI

R Connected to VZ Pin 11 I = 0.4 Iref

C

VCS grows up till it reaches its maximum value (normally, VCS max = 1 V). Then if the output load keeps on increasing, the system is not able to supply enough energy to maintain the output regulation. Consequently, the decreasing output can be used to apply a voltage that diminishes to a value lower than 1 V, to pin 5, in order to limit the maximum peak current. In this way, the well known foldback characteristic is obtained (refer to Figure 36). The foldback action can be inhibited by connecting the pin 5 to VCC.

C // R VZ RI τ = RC

Figure 35. Different Possible Uses of Pin 11

In any case (particularly if no external component is connected to pin 11), an internal zener diode (DZ, refer to Figure 34) is able to clamp the pin 11 voltage to a value VZ that is higher than the oscillator value and so, that results in no max duty cycle limitation. As soon as Vdisable1 is detected, a signal UVLO1 is generated until the VCC voltage falls down to Vdisable2 (refer to the undervoltage lockout section paragraph). During the delay between the disable 1 and the disable 2, using a transistor controlled by UVLO1, the pin 11 voltage is made equal to zero in order to make the max duty cycle and soft–start arrangement ready to work for the next restart. In standby mode, this block is inhibited in order not to interfere with the Standby Current Set.


The overvoltage arrangement consists of a comparator that compares the pin 6 voltage to Vref (2,5 V) (refer to Figure 37). Vref VCC In

0 VOVP Pin 6

Protection The MC44604 can ensure a high converter reliability thanks to the protection it offers.

Out

2.5 V 11.6 K

Enable In

2K

COVLO 2.5 V (Vref)

Demagnetization Detection (Refer to Demag §) Foldback

As depicted in Figure 28, the foldback input (pin 5) enables to reduce the maximum VCS value that would be equal to 1 typically, if there was no foldback action. Finally, the foldback arrangement is a programmable peak current limitation. Vout

Delay τ 5.0 µs

T

τ

VOVP out

Out Delay 2.0 µs

(If VOVP out = 1.0, the Output is Disabled)

Figure 37. Overvoltage Protection

If no external component is connected to pin 6, the comparator non inverting input voltage is nearly equal to:

ǒ11, 6 kΩ2 kΩ) 2 kΩǓ VCC

Ipk max

•

VO Nominal

So, the comparator output is high when:

ǒ11, 6 kΩ2 kΩ) 2 kΩǓ

New Startup Sequence Initiated

•

V w 2, 5 V CC

V w 17 V CC

VCC Vdisable2

A delay latch (2 µs) is incorporated in order to only take into account the overvoltages that last at least 2 µs. If this condition is achieved, VOVPout the delay latch output becomes high and as this level is brought back to the input through an OR gate, VOVPout remains high (and so, the IC output is disabled) until Vref is disabled. Consequently when an overvoltage longer than 2 µs is detected, the output is disabled until a new circuit restart. The VCC is connected when once the circuit has started–up in order to limit the circuit start–up consumption (T is switched on when once Vref has been generated).

Iout Overload

Figure 36. Foldback Characteristic

It could be used as a soft–start (by connecting to pin 5, a gradually increasing voltage) but in fact, it has been designed to provide the system with an effective overload protection. Indeed, as the output load gradually increases, the required converter peak current becomes higher and so,


MC44604 The overvoltage section is enabled 5 µs after the regulator has started to allow the reference Vref to stabilize. By connecting external resistors to pin 6, the threshold VCC level can be changed.

Thus, finally in normal mode, the upper Vcc limit that enables the output to be active, is 9.4 V (maximum value of Vdisable1) and so the minimum hysteresis is 4.2 V. [(Vstup–th)min = 13.6 V]. The large hysteresis and the low start–up current of the MC44604 make it ideally suited for off–line converter applications where efficient bootstrap start–up techniques are required.

Rref Pin 16

Vref enable

VCC (Pin 1)

Standby Management

CSTART–UP 1 0 1

0

Vdisable 7.5 V or 12.5 V

START–UP 14.5 V

The MC44604 has been designed to detect the transitions between the standby and normal mode and to manage each mode in an optimal way. In standby, the device monitors a pulsed mode that enables to drastically reduce the power consumption.

Reference Block: Voltage and Current Sources Generator (Vref, Iref, ...)

Pulsed Mode

UVLO1 CUVLO1 (to SOFTSTART)

Vdisable1 9.0 V

The MC44604 standby is preferably associated to a flyback configuration as depicted in Figure 39. MC44604

Figure 38. VCC Management

Input Voltage VCC

Undervoltage Lockout Section As depicted in Figure 39, an undervoltage lockout has been incorporated to guarantee that the IC is fully functional before allowing operation of the system. Indeed, the VCC is connected to the non inverting input of a comparator that has an upper threshold equal to 14,5 V (Vstup–th) and a lower one equal to 7.5 V (Vdisable2) in normal mode and 14.5 V and 12.5 V in Standby mode (typical values) (Note 1). This hysteresis comparator enables or disables the reference block that generates the voltage and current sources required by the system. This block particularly, produces Vref (pin 16 voltage) and Iref that is determined by the resistor Rref connected between pin 16 and the ground:

1 = Standby 0 = Normal Mode 1 0

Lp

P Vstby

MC44604

Regulator

Figure 39. Standby Flyback Configuration

In effect, by this means, all the output regulation levels are divided by the ratio: V V

V I + ref where V + 2.5 V (typically) ref ref R ref

HV

stby

where VHV is the normal mode high voltage regulation level, Vstby is the standby µP supply voltage. For instance, in the case of TV or monitors applications, the output levels (except the µP supply voltage, Vstby) are drastically reduced by a ratio in the range of 10. Consequently, as the output voltages are reduced, the losses due to the output leakage consumption, are practically eliminated, without having to disconnect the loads.

In addition to this, VCC is compared to a second threshold level that is nearly equal to 9 V (Vdisable1) so that in normal mode, a signal UVLO1 is generated to reset the maximum duty cycle and soft–start block and so, to disable the output stage (refer to Max. Duty Cycle and Soft–Start §) as soon as VCC becomes lower than Vdisable1. In this way, the circuit is reset and made ready for a next start–up, before the reference block is disabled (refer to Figure 26). In standby, UVLO1 is not active (there is no need to discharge the soft–start capacitor as the soft–start pin is maintained short circuited).

Start–up Operations

The choice of the right configuration (normal or standby) is performed at each start–up.

Note 1. In standby the difference between V disable2 and Vstup–th is decreased not to have too low pulsed mode frequencies.


MC44604 Standby Management

That is why, as explained in the transitions §, at each change of mode, the MC44604 is first turned off so that a new start–up should be performed.

The standby operation consists of two main phases: — the off phase during which the MC44604 is off. During this sequence, the circuit Vcc is being charged and no energy is transferred to the output. — the active phase during which the MC44604 is on. At this moment, some power can be drawn from the mains. During the active phase, the power conversion is controlled so that: — the normal mode regulation means (error amplifier) and the soft–start are inhibited — the Vcc undervoltage lockout (Vdisable2) level is increased from 9 V up to 12.5 V. This limitation of the Vcc hysteresis enables to increase the pulsed mode frequency — the peak inductor current is forced to be constant and equal to the level programmable by the external resistor RIpmax connected to the pin 9 so that:

Vcc gets higher than Vstup–th Start–up

YES

Ipin 15 > Idet*

NO

STAND–BY

NORMAL MODE

– Pin 15 and pin 12 are kept disconnected and so, the E/A input receives no feedback (the regulation is performed by comparing Ipin 15 to Ireg – refer to stand–by regulation ) – the soft–start is inhibited and its capacitor is discharged – the lpmax limitation block is activated (clamp of the peak current) – the level Vdisable2 is increased (refer to undervoltage lockout section)

– The pin 15 is connected to pin 12 to provide the E/A input with a feedback – the stand–by block is inhibited

0, 4 I pmax +

— when the pin 15 current gets higher than the threshold Ireg (20.5 Iref), this operating mode stops and the circuit output is latched off. So, in fact, the active phase is split into two distinct sequences and finally three phases can be defined (refer to Figure 32): — the off phase: the MC44604 is off and the Vcc capacitor is being charged. When the Vcc gets higher than Vstup–th, the circuit turns on and the switching sequence starts — the switching phase: the circuit is on and forces a constant peak inductor current. This sequence lasts until Ipin15 gets higher than Ireg — the latched phase: the circuit is on but the output is disabled. This sequence lasts until the standby Vcc undervoltage lockout voltage (12.5 V) is reached. A new off phase is then initialized.

* this test is performed during the first 5 s of circuit operation

At each start–up, the circuit detects if it must work in standby or in normal mode configuration. To do that, the circuit compares the current Ipin15 to Idet so that, if: — Ipin15 > Idet: Standby mode — Ipin15 < Idet: Normal mode According to the detected mode, the circuit configuration is set (refer to Figure 40). This detection phase takes place during the first 5 µs of circuit operation in order to have the internal signals well stabilized before the decision is taken. Vstby

VCC

Opto Coupler Rinit

TL431

R

Rdet Z P

R lpmax ref 2, 6 R S

where: Ipmax is the standby inductor peak current, RS is the current sense resistor.

Figure 40. Start–up Operation

Rreg

I

Pin 15

C T

MC44604

Figure 41. Standby Pin 15 Arrangement


MC44604 detect a sequence during which Ipin15 lower than Ireg before being able to latch gets higher than Vz).

Vstup (14.5 V)

V CC

Transitions Between Normal Mode and Standby Mode (Refer to Figure 43)

Stby Vdisable 2 (12.5 V) V stby P supply voltage

The MC44604 detects a transition by comparing the pin 15 current to: — Idet (transition standby to normal mode) — Iinit (transition normal mode to standby) Each transition detection results in the circuit turning off, so that the device can work in the new mode after the following restart.

V pin 15

I zener

• transition normal mode to standby:

I reg

I pin 15

I det

output

ÎÎÎÎ ÎÎÎÎ

The output is latched off until the next re–start

This transition is detected by comparing the Ipin15 current to the threshold current (Iinit). Iinit is high enough so that the opto coupler current used for the regulation, never exceeds this value. The arrangement in Figure 41 is well adapted to this mode of operation. The µP initializes the standby mode by turning on the switch T. This results in the C capacitor charge that produces a peak current in the primary side of the opto coupler. C and Rinit must be dimensioned so that the opto coupler primary side generates a pin 15 current higher than Iinit during more than 1 µs.

time

Figure 42. Standby Regulation

As a consequence, Vstby varies between a peak value (obtained at the end of the switching phase) and a valley level (reached at the end of the off phase). The level of the peak value is controlled by forcing a current higher than Ireg in pin 15 when this level has reached the desired value. The arrangement in Figure 41 allows to obtain this operation. A zener diode Z is connected so that a current limited by Rreg, is drawn by this device, when the µP supply voltage gets higher than Vz. By this way, the current injected in the pin 15 increases and when this current is detected as higher than Ireg, the output gets disabled until the next start–up (Note 1). Practically, the pin 15 current can be expressed as follows (when the zener is activated): I

pin15

+ CTR

• transition standby to normal mode:

If the circuit detects that (Ipin15 < Idet) during standby operation, the circuit is turned off. So, if the normal mode is maintained at the following start–up, the circuit will re–start in a normal mode configuration. The arrangement in Figure 41 allows to perform this detection. When the µP detects the end of the standby, it turns off the switch T and the opto coupler stops supplying current to the circuit. V CC

V * Vopto * V z stby R reg

14.5 V 12.5 V Normal Mode

(....)

Normal Mode

Stand–by

where: CTR is the opto coupler gain, Vopto is opto coupler voltage drop.

R reg

time

The transition stand–by to normal mode occurs while the circuit is off (VCC charge phase)

So, as the Vstby peak value is obtained when (Ipin15 = Ireg), it can be calculated using the following equation: V + V z ) Vopto ) stby pk

Normal Mode

Stand–by Burst Mode

I reg

V CC

CTR

Practically, Rreg is chosen very low (in the range of 10 Ω, low resistance just to limit the current when Vstby pk gets higher than Vz):

14.5 V 12.5 V Normal Mode

(....)

Stand–by

V ^ V z ) Vopto stby pk

Normal Mode

Stand–by Burst Mode Normal Mode

time

The transition stand–by to normal mode occurs while the circuit is on (working phase)

Note 1. If the pin 15 current is higher than Ireg at start–up, the output is just shutdown but not latched. The circuit must

Figure 43. Transitions Between Modes


MC44604 Application Schematic 185 Vac to 270 Vac

RFI Filter

CS 1nF11kV 1 Ω 15 W

C4....C7 1 nF/1000 V

RS 4.7 MΩ 220 pF 120/0.5 A

D1 ... D4 1N4007

C1 100 F

R19 10 k

9

8

10

7

C2 100 F

11

13

MC44604P

R15 22 k 1 k C11 1F R16 22 k

12

6

100 nF 1N4937

R4 C16 100 pF 27 k

47 nF 1N4148

R9 180 k

C14 4.7 nF

R8 15 k

Lp

R6 150 Ω

4 R26 20 3

15

2

16 R19 10 k

1

28V/1A

MR856 100 F

MR856 1.2 k

5

14

220 pF

1 kΩ

MCR22–6 1N4148

Laux

1 nF

C10 1F

47 k 120 pF

VCC

1 k

C9 1 nF

0.1 F

100 pF

1 H

1N4148

R2 68 K (2W)

MR856

22 k (5W)

MTP6N60E

MR856 R14 0.47 (1W)

220 pF

15V/1A

MR852 1000 F

C18 2.2 nF

R11 100

C13 100 nF

0.1 F

R13 1 k (5W)

0.1 F

220 pF 8V/1A BC237B

MR852 4700 F

0.1 F

VCC MOC8104 117.5 kΩ 100 nF 220 kΩ

4.7 kΩ 8.2 k 22 Ω

47 Ω

4.7 kΩ

270 Ω

4.7 k

TL431 12 V BC237B 4.7 kΩ

BC237B


P

2.5 kΩ

) "# =& # ) < " 81) = @)"A&# " ''""! The MC44605 is a high performance current mode controller that is specifically designed for off–line converters. This circuit has several distinguishing features that make it particularly suitable for multisynchronized monitor applications. The MC44605 synchronization arrangement enables operation from 16 kHz up to 130 kHz. This product was optimized to operate with universal mains voltage, i.e., from 80 V to 280 V, and its high current totem pole output makes it ideally suited for driving a power MOSFET. The MC44605 protections enable a well–controlled and safe power management. Four major faults while detected, activate the analogic counter of a disabling block designed to perform a latched circuit output inhibition.

http://onsemi.com MARKING DIAGRAM 16 PDIP–16 P SUFFIX CASE 648

16

1

1


Current Mode Controller

• • • • • • • • • • •

Current Mode Operation up to 250 kHz Output Switching Frequency Inherent Feed Forward Compensation Latching PWM for Cycle–by–Cycle Current Limiting Oscillator with Precise Frequency Control Externally Programmable Reference Current Secondary or Primary Sensing (Availability of Error Amplifier Output) Synchronization Facility High Current Totem Pole Output Vcc Undervoltage Lockout with Hysteresis Low Output dV/dT for Low EMI Radiations Low Start–Up and Operating Current

Safety/Protection Features

• • • • • • •

Soft–Start Feature Demagnetization (Zero Current Detection) Protection Overvoltage Protection Facility against Open Loop EHT Overvoltage Protection (E.H.T.OVP): Detection of too High Synchronization Pulses Winding Short Circuit Detection (W.S.C.D.) Limitation of the Maximum Input Power (M.P.L.): Calculation of Input Power for Overload Protection Overheating Detection (O.H.D.): to Prevent the Power Switch from an Excessive Heating

Latched Disabling Mode

• When one of the following faults is detected: EHT overvoltage, •

MC44605P AWLYYWW

PIN CONNECTIONS **

2 7

*

I*) (5

! !

#

" '!( /(01 + !

"

# : ;5 ! !

G(9 ,5!(!

)3(/' '01 * 9!

< 4 (! ) ! 0! * ! 3 + !

7!%!(! + !

30 *((0! *

) 5( !6(! ) ! 0! + !

@0 (

:- + !

* Winding Short Circuit Detection


Package

Shipping

MC44605P

PDIP–16

25 Units/Rail

Winding Short Circuit (WSCD), a too high input power (M.P.L.), power switch overheating (O.H.D.), an analogic counter is activated If the counter is activated for a time that is long enough, the circuit gets definitively disabled. The latch can only be reset by making decrease the Vcc down to about 3 V, i.e., practically by unplugging or turning off the SMPS.



1896


MC44605 Block Diagram R ref

V CC

16

1 i ref

V ref Demagnetization Detection Input 8

Demagnetization Management

C T 10 Synchronization and EHTOVP 9 Input

2 VC

W.S.C.D* Comparator

–

V ref

V shift Level Programmation

Vcs

dis MPL

UVLO2

V CC enable 15

dis OHD Disout

Error AMP

V CC

Over Voltage Management

V WSCD

Sf dis MPL I sense

Voltage Feedback 14 Input

+

4 Gnd

Thermal Shutdown

V shift

Disabling Block

V ref

Current Sense

3 Output

Buffer

Set Q PWM Latch Reset

Vcs I sense

C ext 12

Disout

VS

Sf

E.H.T.OVP Block

18 V

UVLO1 UVLO2

I ref Oscillator

V CC

Supply Initialization Block

Reference Block

V DT

Output

V cc enable

V demag out

I ref

dis OHD

V cs 2

MPL block

O.H.D. block

5

6

Soft–Start

UVLO1 V CC enable

E/A Output 13 7

11

Current Maximum Over Soft–Start Heating Input Power Sense Input Limitation Detection *W.S.C.D. = Winding Short Circuit Detection


MC44605

WSCD Programmation

MC44605 MAXIMUM RATINGS Rating

Pin #

Symbol

Value

Unit

(ICC + IZ)

40

mA

VC VCC

18

V

IO(Source) IO(Sink)

–750 750

W

5.0

µJ

Soft–Start

VSS

–0.3 to 2.2 V

V

Current Sense, Voltage Feedback, E/A Output, CT, Rref, MPL, OHD, Cext, WSCD

Vin

–0.3 to 5.5 V

V

Total Power Supply and Zener Current Output Supply Voltage with Respect to Ground

2 1

Output Current* Source Sink

3

mA

Output Energy (Capacitive Load per Cycle)

E.H.T.OVP, Sync Input Current Source

mA 9 6 9 6

Sink Demagnetization Detection Input Current Source Sink

8

Error Amplifier Output Sink Current

13

Isync (Source) IEHT (Source) Isync (Sink) IEHT (Sink)

–4.0 10 mA

Idemag–ib (Source) Idemag–ib (Sink)

–4.0 10

IE/A (Sink)

20

mA

PD RθJA

0.6 100

W °C/W


TJ

150

°C


TA

–25 to +85

°C

Power Dissipation and Thermal Characteristics Maximum Power Dissipation at TA = 85°C Thermal Resistance, Junction–to–Air

*Maximum package power dissipation must be observed.

ELECTRICAL CHARACTERISTICS (VCC and VC = 12 V, Rref = 10 kΩ, CT = 2.2 nF, for typical values TA = 25°C, for min/max values TA = –25° to +85°C unless otherwise noted.) (Note 1) Pin #

Characteristic

Symbol

Min

Typ

Max

VOL

– – – –

1.0 1.4 1.5 2.0

1.2 2.0 2.0 2.7

– – –

– 0.1 0.1 01

1.0 1.0 1.0 10

Unit

OUTPUT SECTION (Note 2) Output Voltage* Low Level Drop Voltage (ISink = 100 mA) (ISink = 500 mA) High Level Drop Voltage (ISource = 200 mA) (ISource = 500 mA)

3

Out ut Voltage During Initialization Phase Output VCC = 0 to 1.0 V, ISink = 10 µA µ VCC = 1.0 to 5.0 V, ISink = 100 µA VCC = 5 5.0 V, ISink = 1.0 0 tto 13 V 1 0 mA A

3

V

VOH VOL

V

Output Voltage Rising Edge Slew–Rate (CL = 1.0 nF, TJ = 25°C)

dVo/dT

–

300

–

V/µs

Output Voltage Falling Edge Slew–Rate (CL = 1.0 nF, TJ = 25°C)

dVo/dT

–

–300

–

V/µs

*VC must be greater than 5.0 V. 1. Adjust VCC above the start–up threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 2. No output signal when the Error Amplifier output is in Low State, i.e., when for instance, VFB = 2.7 V.


MC44605 ELECTRICAL CHARACTERISTICS (VCC and VC = 12 V, Rref = 10 kΩ, CT = 2.2 nF, for typical values TA = 25°C, for min/max values TA = –25° to +85°C unless otherwise noted.) (Note 1) Pin #

Symbol

Min

Typ

Max

Unit

Voltage Feedback Input (VE/A out = 2.5 V)

14

VFB

2.4

2.5

2.6

V

Input Bias Current (VFB = 2.5 V)

14

IFB–ib

–2.0

–0.6

–

µA

AVOL

65

70

–

dB

– –

– –

– 5.5

–10

–

10

Characteristic ERROR AMPLIFIER SECTION

Open Loop Voltage Gain (VE/A out = 2.0 V to 4.0 V) Unity Gain Bandwidth TJ = 25°C TA = –25° to +85°C

BW

Voltage Feedback Input Line Regulation (VCC = 10 V to 15 V)

VFBline–reg

Output Current Sink (VE/A out = 1.5 V, VFB = 2.7 V) TA = –25° to +85°C Source (VE/A out = 5.0 V, VFB = 2.3 V) TA = –25° to +85°C

13

Output Voltage Swing High State (IE/A out (source) = 0.5 mA, VFB = 2.3 V) Low State (IE/A out (sink) = 0.33 mA, VFB = 2.7 V)

13

MHz

mV mA

ISink 2.0

12

–

–2.0

–

–0.2

VOH VOL

5.5 –

6.5 1.0

7.5 1.1

Vcs–th

0.96

1.0

1.04

V

ISource V

CURRENT SENSE SECTION Maximum Current Sense Input Threshold (VFeedback (pin14) = 2.3 V and VSoft–Start (pin11) = 1.2 V)

7

Input Bias Current

7

Ics–ib

–10

–2.0

–

µA

tPLH(In/Out)

–

120

200

ns

FOSC

16

–

20

kHz


∆FOSC/∆V

–

0.05

–

%/V

Frequency Change with Temperature (TA = –25° to +85°C)

∆FOSC/∆T

–

0.05

–

%/°C

Ratio Charge Current/Reference Current (TA = –25° to +85°C)

Icharge/Iref

0.39

–

0.48

–

Propagation Delay (Current Sense Input to Output at VTH of MOS transistor = 3.0 V) OSCILLATOR AND SYNCHRONIZATION SECTION Frequency (TA = –25° to +85°C)

Free Mode Oscillator Ratio = Idischarge/(Idischarge + Icharge) Synchronization Input Threshold Voltage

9

Negative Clamp Level (Isyncth–in = 2.0 mA)

D

72

75

78

%

Vsyncth

–250

–200

–150

mV

NEG–SYNC

–0.65

–0.5

–0.34

V

UNDERVOLTAGE LOCKOUT SECTION Start–up Threshold

1

Vstup–th

13.6

14.5

15.4

V

Disable Voltage After Threshold Turn–On (UVLO 1) (TA = –25° to +85°C)

1

Vdisable1

8.3

–

9.6

V

Disable Voltage After Threshold Turn–On (UVLO 2) (TA = –25° to +85°C)

1

Vdisable2

7.0

7.5

8.0

V

1. Adjust VCC above the start–up threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.



Symbol

Min

Typ

Max

Unit

Reference Output Voltage (VCC = 10 V to 15 V)

16

Vref

2.4

2.5

2.6

V

Reference Current Range (Iref = Vref/Rref, R = 5.0 k to 25 kΩ)

16

Characteristic REFERENCE SECTION

Reference Voltage Over Iref Range

Iref

–500

–

–100

µA

∆Vref

–40

–

40

mV

Vdemag–th tPLH(In/Out) Idemag–lb

50 – –0.5

65 0.5 –

80 – –

mV µs µA

DEMAGNETIZATION DETECTION SECTION (Note 2) 8

Demagnetization Detect Input Demagnetization Comparator Threshold (Vpin9 Decreasing) Propagation Delay (Input to Output, Low to High) Input Bias Current (Vdemag = 65 mV) Minimum Off–Time when the pin 8 is grounded

TDEM–GND

1.5

3.0

4.5

µs

Negative Clamp Level (Idemag = –2.0 mA)

CLVL–neg

–0.50

–0.38

–0.25

V

Positive Clamp Level (Idemag = +2.0 mA)

CLVL–pos

0.50

0.72

0.85

V

SOFT–START SECTION (Note 3) Ratio Charge Current/Iref (TA = –25° to +85°C)

Iss–ch/Iref

0.37

–

0.43

–

Discharge Current (Vsoft–start = 1.0 V)

Idischarge

1.5

5.0

–

mA

Clamp Level

VSS–CLVL

2.2

2.4

2.6

V

VSSinhi

30

–

150

mV

VCSsoft–start

0.45

0.5

0.55

V

Circuit Inhibition Threshold* VCS Soft–Start Clamp Level (Rsoft–start = 5 kΩ)

*The circuit is shutdown if the Soft–Start pin voltage is lower than this level. 1. Adjust VCC above the start–up threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 2. This function can be inhibited by connecting pin 8 to GND. In this case, there is a minimum off–time equal to TDEM–GND. 3. The MC44605 can be shut down by connecting Soft–Start pin (pin 11) to Ground.



Symbol

Min

Typ

Max

Unit

Propagation Delay (VCC > 18.1 V to Vout Low)

TPHL(In/Out)

1.0

–

4.0

µs

Protection Level on VCC (TA = –25° to +85°C)

VCC prot

15.9

–

18.1

V

NEG–SYNC

–0.65

–0.5

–0.35

V

Characteristic OVERVOLTAGE SECTION

EHT OVP SECTION (Note 2) Negative Clamp Level (Isynch–in = –2.0 mA) EHT OVP Input Threshold EHT OVP Input Bias Current (VEHT OVP(pin 9) = 0 V)

9

Vref

7.0

7.4

7.8

V

IEHTOVP

–5.0

–

0

µA

Vshift

70

100

120

mV

ΓMPL

0.185

0.240

0.295

V–1

WINDING SHORT CIRCUIT DETECTION SECTION WSCD Threshold with Ipin15 = 200 µA MPL & OHD SECTION MPL Parameter* MPL Comparator Threshold** OHD Parameter*** OHD Comparator Threshold****

VMPL–th

2.4

2.5

2.6

V

ΓOHD

1.15

1.50

1.85

V–1

VOHD–th

2.4

2.5

2.6

V

*This parameter is defined in the MPL §. This parameter is obtained by measuring the MPL pin average current and dividing this result by the corresponding squared VCS, the measured frequency value and the CT value deducted from the measured frequency value. Measurement conditions: VFeedback(pin 14) = 2.3 V, Vsoft–start(pin 11) = 0.5 V and pins 7, 8, and 9 connected to GND (the working frequency is typically equal to 18 kHz – Rref = 10 kΩ "1%, CT = 2.2 nF). **The MPL comparator output is DisMPL. ***This parameter is defined in the OHD §. This parameter is obtained by measuring the OHD pin average current and dividing this result by the corresponding squared VCS value and multiplying it by the Rref value. Measurement conditions: VFeedback(pin 14) = 2.3 V, Vsoft–start(pin 11) = 0.5 V and pins 7, 8, and 9 connected to GND (the working frequency is typically equal to 18 kHz – Rref = 10 kΩ "1%, CT = 2.2 nF). ****The OHD comparator output is DisOHD. DISABLING BLOCK SECTION TWSCD

–

4.0

–

µs

Ratio (EHTOVP and WSCD Disabling Capacitor Charge Current)Iref

IDis–H/Iref

90

100

110

%

Ratio (MPL and OHD Disabling Capacitor Charge Current)Iref

IDis–L/Iref

2.7

3.1

3.5

%

5.0

V

Delay Pulse Width

Minimum VCC Value Enabling the Disabling Block Latch* VCCDis 1.0 – *Once a fault detection activated it, the Disabling Block Latch gets reset when the VCC becomes lower than this threshold. TOTAL DEVICE Power Supply Current Startup–Up (VCC = 5.0 V with VCC increasing) Startup–Up (VCC = 9.0 V with VCC increasing) Startup–Up (VCC = 12 V with VCC increasing) Operating TA = –25°C to +85°C* Disabling Mode (VCC = 6.0 V)**

ICC

Power Supply Zener Voltage (ICC = 35 mA) Thermal Shutdown

mA – – – – –

0.35 0.35 0.35 20 –

0.55 0.55 0.55 25 0.55

VZ

18.5

–

–

V

–

–

155

–

°C

*Refer to Note 1. **This consumption is measured while the circuit is inhibited by the Definitive Latch. 1. Adjust VCC above the start–up threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 2. This function can be inhibited by connecting pin 9 to GND. In this case, the synchronization block is inhibited too and the MC44605 works in free mode.


MC44605 Name

Pin

Pin Description

1

VCC

This pin is the positive supply of the IC.

2

VC

The output high state, VOH, is set by the voltage applied to this pin. With a separate connection to the power source, it gives the possibility to set by means of an external resistor the output source current at a different value than the sink current.

3

Output

The output current capability is suited for driving a power MOSFET.

4

GND

The ground pin is a single return typically connected back to the power source. It is used as control and power ground.

5

Maximum Power Limitation

This block enables to estimate the input power. When this calculated power is detected as too high, a fault information is sent to the disabling block in order to definitively disable the circuit.

6

Over–Heating Detection

This block estimates the MOSFET heating. When this calculated heating is too high, the device gets definitively disabled (disabling block action).

7

Current Sense Input

A voltage proportional to the current flowing into the power switch is connected to this input. The PWM latch uses this information to terminate the conduction of the output buffer. A maximum level of 1 V allows to limit the inductor current.

8


A voltage delivered by an auxiliary transformer winding provides to the demagnetization pin an indication of the magnetization state of the flyback energy reservoir. A zero voltage detection corresponds to a complete core demagnetization. The demagnetization detection prevents the oscillator from a re–start and so the circuit from a new conduction phase, if the fly–back is not in a dead–time state. This function can be inhibited by connecting Pin 8 to GND but in this case, there is a minimum off–time typically equal to 3 µs.

9

Synchronization and E.H.T.OVP Input

Activating the synchronization input pin with a pulse higher or equal to the negative threshold (typically –200 mV) allows the next switching period to be reinitialized. The oscillator is free when connecting Pin 9 to GND. When the E.H.T.OVP pin receives a voltage that is greater than 7.5 V, the disabling block Cext capacitor is charged so that the circuit gets definitively disabled if the Cext voltage becomes higher than Vref. This block is incorporated to detect and disable the device when the synchronization pulses are too high.

10

Oscillator Capacitor CT

The free mode oscillator frequency is programmed by the capacitor CT choice together with the Rref resistance value. CT, connected between pin 10 and GND, generates the oscillator sawtooth.

11

Soft–Start

A capacitor connected to this pin can temporary reduce the maximum inductor peak current. By this way, a soft–start can be performed. By connecting pin 11 to Ground, the MC44605 is shut down.

12

Cext (Disabling Block)

When a too high synchronization pulse voltage (E.H.T.OVP) or a winding short circuit (WSCD) is detected, the capacitor Cext is charged using a current source IDis– H. In the case of a MPL or OHD fault detection, Cext is charged using IDis–L. If the Cext capacitor voltage gets higher than Vref, the circuit is definitively disabled. Then, to restart, the converter must be switched off in order to make VCC decrease down to about 0 V.

13

E/A Output


14

Voltage Feedback

This is the inverting input of the Error Amplifier. It can be connected to the Switching Mode Power Supply output through an optical (or else) feedback loop or to the subdivided VCC voltage in case of primary sensing technic.

15

Winding Short Circuit Detection Programmation

The W.S.C.D. block is incorporated to detect the transformer Winding Short Circuits. This function is performed by detecting the inductor overcurrents thanks to a comparator which threshold is programmable to be well adapted to any application.

16

Rref

The Rref value fixes the internal reference current that is particularly used to perform the precise oscillator waveform. The current range goes from 100 µA up to 500 µA.


MC44605 Summary of the Main Design Equations The following table consists of equations enabling to dimension a multisynchronized SMPS operating in discontinuous mode. Poutmax is the maximum power the load may draw in normal working.

Pout max

Pin max +

ƪ Lp max +

2

d max +

Ǹ2·Vac Ǹ2·Vac

Pon max + 1 3

min

Ǹ

2 L

ǸPin max

ƫ

NVo 2

min

Pin max

Ipk max +

The maximum input power Pinmax is easily deducted by dividing Poutmax by the efficiency (η). In this kind of application, the efficiency is generally taken equal to 80%.

η

)NVo

fsync max

Vac

fsync max

min

Ipk max2

Rds on

In effect, if Lp was higher than Lpmax, a synchronized and discontinuous working could not be guaranteed (in some cases, the demagnetization phase would not be finished while a new conduction phase should start to follow the synchronization). Ipkmax is the maximum inductor peak current. This current is obtained when the power to transfer is maximum at the minimum synchronization frequency (60 W output, 30 kHz in the proposed application).

Pin max fsync min Lp

The inductor value Lp must be chosen lower than Lpmax or ideally equal to this value (to optimize the application design–in).

d max

dmax is the maximum duty cycle. The duty cycle is maximum at the lowest input voltage when the power demand is maximum while the synchronization frequency also is maximum. Ponmax is the maximum Mosfet on–time losses that are proportional to Ipkmax, dmax and Rdson (on–time Mosfet resistor). This conduction losses estimation enables to dimension the power Mosfet.

(V ) max + ǒǸ2 DS

Vac maxǓ ) (N

ǒ

Ǔ

Vout)

Vac max ) Vout N

(V ) max + Ǹ2 D

(VDS)max is the maximum voltage the power switch must be able to face. In fact, this calculation does not take into account the turnings off spikes. So, it is necessary to take a margin of at least about 50 V. (VD)max is the maximum voltage the high voltage secondary diode must be able to face. Because of the turning off spikes, a margin must also be taken. (AL) and (ni) are the magnetic parameters.

(ni) max + N

A + L (N

n

Vout L

Ipk max

P n )2 Vout

(ni)max must not exceed the ferrite (ni). Otherwise, the transformer may get saturated when the peak current is high. (AL) is the ferrite constant that links the primary inductor value to the squared number of primary turns: Lp = AL x np2.

+

Error Amplifier

1.0 mA

Compensation

A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical DC voltage gain of 70 dB. The non inverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current with the inverting input at 2.5 V is –2.0 µA. This can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance.

RFB

Rf

Error Amplifier

13 14 2.5 V

Cf

2R R


1.0 V


MC44605 Gnd

4

From Power Supply Output R1

R2

Figure 1. Error Amplifier Compensation


MC44605 The Error Amp Output (Pin 13) is provided for external loop compensation. The output voltage is offset by two diodes drops ([1.4 V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Source Output (Pin 3) when Pin 13 is at its lowest state (VOL). This occurs when the power supply is operating and the load is removed, or at the beginning of a soft–start interval. The Error Amp minimum feedback resistance is limited by the amplifier’s minimum source current (0.2 mA) and the required output voltage (VOH) to reach the current sense comparator’s 1.0 V clamp level: (3

R1(min) +

V I

pk

I

I

ref

+

V R

ref where V + 2.5 V (typically) ref ref

VCC (Pin 1)

Vin

Rref Pin 16

Vref enable

VC

CSTART–UP

14 R2

1 0 Q1

Vdemag out

3

1

S

R3

Q Thermal Protection

+1V R S

As depicted in Figure 3, an undervoltage lockout has been incorporated to guarantee that the IC is fully functional before allowing the system working. In effect, the VCC is connected to the non inverting input of a comparator that has an upper threshold equal to 14,5 V (typical Vstup–th) and a lower one equal to 7.5 V (typical Vdisable 2). This hysteresis comparator enables or disables the reference block that generates the voltage and current sources required by the system. This block particularly, produces Vref (pin 16 voltage) and Iref that is determined by the resistor Rref connected between pin 16 and the ground:

The MC44605 operates as a current mode controller. The circuit uses a current sense comparator to compare the inductor current to the threshold level established by the Error Amplifier output (Pin 13). When the current reaches the threshold, the current sense comparator terminates the output switch conduction that has been initiated by the oscillator, by resetting the PWM Latch. Thus the error signal controls the peak inductor current on a cycle–by–cycle basis. This configuration ensures that only one single pulse appears at the Source Output during the appropriate oscillator cycle.

VS

pk(max)

Undervoltage Lockout Section


Disout

* 1.4 V (pin13) 3 R S

The Current Sense Comparator threshold is internally clamped to 1.0 V. Therefore the maximum peak switch current is:

1 V) ) 1.4 V + 22 kΩ 0.2 mA

UVLO

[

Vdisable 7.5 V

R

START–UP 14.5 V

CUVLO1

PWM Latch Substrate


0

Current Sense 7

C

Vdisable1 9.0 V

R

Reference Block: Voltage and Current Sources Generator (Vref, Iref, ...)

UVLO1 (to SOFTSTART) MC44605

RS

Figure 3. VCC Management Figure 2. Output Totem Pole

In addition to this, VCC is compared to a second threshold level that is nearly equal to 9 V (Vdisable1) so that a signal UVLO1 is generated to reset the soft start block and so, to disable the output stage (refer to the Soft–Start §) as soon as VCC becomes lower than Vdisable 1. In this way, the circuit is reset and made ready for a next start–up, before the reference block is disabled (refer to Figure 3). Thus, finally the upper limit for the minimum normal operating voltage

The inductor current is converted to a voltage by inserting the ground referenced sense resistor RS in series with the power switch Q1. This voltage is monitored by the Current Sense Input (Pin 7) and compared to a level derived from the Error Amp output. The peak inductor current under normal operating conditions is controlled by the voltage at Pin 13 where:


MC44605 The MC44605 oscillator achieves four functions: — it fixes the free mode frequency — it takes into account the synchronization signal — it does not allow a new power switch conduction if the flyback is not in a dead–time state when the circuit works in demagnetization mode (pin 8 connected) — it builds the Sf pulse required by the MPL block During the operating mode, the oscillator sawtooth can vary between a valley value (1.6 V typically) and a peak one (3.6 V typically) and presents three distinct phases: — the CT charge — the CT discharge — the phase during which the oscillator voltage is maintained equal to its valley value. This happens at the end of a discharge cycle when the synchronization or demagnetization condition does not allow a new CT charge phase. During this sequence, IREGUL compensates the charge current Icharge. The oscillator has two working modes: — a free one when there is no synchronization — a synchronized one. In the free working, the oscillator grows up from its valley value to its peak one for the charge phase and when once the peak value is reached, a discharge sequence makes the CT voltage decrease down to its valley value. When the decrease phase is finished, a new charge cycle occurs if the demagnetization condition is achieved (VDT high). Otherwise there is a REGUL phase until VDT gets high. In the synchronized mode, the charge cycle is only allowed when the synchronization signal gets high while a dead time has been detected (VDT high). This charge phase is stopped when the synchronization signal has got low and when the oscillator voltage is higher than Vint, the intermediary voltage level used to generate the calibrated pulse Sf by comparing the CT voltage to this threshold. So, when these two conditions are performed, a discharge sequence is set until the oscillator voltage is equal to its valley value. Then, the CT voltage is maintained constant thanks to the “REGUL” arrangement until the next synchronization pulse. In both cases, during the charge phase, a signal VS is generated. When Sf becomes high. VS gets high and remains in this state until the PWN latch is set of Sf is low. Then, VS keeps low until the next Sf high level. This oscillator behavior is obtained using the process described in Figure 5b.

is 9.4 V (maximum value of Vdisable 1) and so the minimum hysteresis is 4.2 V. [(Vstup–th)min = 13.6 V]. The large hysteresis and the low start–up current of the MC44605 make it ideally suited for off–line converter applications where efficient bootstrap start–up techniques are required. Soft–Start Control Section The Vcs value is clamped down to the pin 11 voltage. So, if a capacitor is connected to this pin, its voltage increases slowly at the start–up (the capacitor is charged by an internal current source 0.4 Iref). So, Vcs is limited during the start–up and then a soft–start is performed. This pin can be used to inhibit the circuit by applying a voltage that is lower than VSSinhi (refer to page 4). Particularly, the MC44605 can be shutdown by connecting the soft–start pin to ground. As soon as Vdis1 is detected (that is Vcc lower than Vdisable1), a signal UVLO1 is generated until the Vcc falls down to Vdis2 (refer to the undervoltage lockout section §). During the delay between the disable1 and the disable2, using a transistor controlled by UVLO1, the pin 11 voltage is made equal to zero in order to make the soft–start arrangement ready to work for the next re–start. Vref Vcs

0.4 Iref Pin 11 Soft Start Capacitor

DZ

Output Inhibition

2.4 V UVLO1

VSSlnhi MC44605

Figure 4. Soft–Start

Oscillator Section (Figures 5 & 5b) The oscillator and synchronization represented in Figure 5b.

behavior

is


MC44605 a – Free mode

Inductor current

V DT

Oscillator

Vint

Sf

Output

b – Synchronized mode

Synchro input

Inductor current

V DT Oscillator Vint

Sf

Output

Figure 5b. Oscillator Behavior


MC44605 In effect, the output of the latch L1 is: — high during the oscillator capacitor charge and during the REGUL phase — low for the oscillator capacitor discharge Now, the latch L2 is set when the L1 output is high and the synchronization condition is performed (that is: sync = 1 – free mode or synchro signal high state) and during the dead–time (VDT high). So, this latch is set for the CT charge. On the other hand, this latch is reset by the signal used to reset L1. Consequently, it is reset at the end of the charge phase. So, in any case, QL2 is: — high during the CT charge cycle — low in the other cases Thus, this latch enables to obtain a signal that is high for the charge phase and low in the other cases, whatever the mode (synchronized or free) and whatever the synchronization pulses width (higher than the delay necessary for the oscillator to reach its intermediary value or lower than this delay) in the synchronized mode. That is why: — the discharge current source must be connected to the oscillator capacitor when QL1 is low. The condition (CT voltage higher than the valley value) is added to stop the discharge phase as soon as the oscillator voltage is detected as lower than the valley value (without any delay due to the L1 latch propagation time). — the REGUL current source must be connected when: • QL1 is high (charge or REGUL phase) • QL2 is low (the oscillator is not in a charge phase) On the other hand, the oscillator charge is stopped when: — the oscillator voltage reaches the peak value in the free mode — the oscillator voltage is higher than the intermediary value (Vint) and the synchronization signal is negative, in the synchronized mode. Consequently, in any case, QL2 that is high during the oscillator charge phase, is high for the delay during which the oscillator voltage grows from the valley value up to the intermediary one. That is why the signal Sf (refer to the MPL block) that must be high when the oscillator voltage is between the valley value and the intermediary one during the charge phase (QL2 high), is obtained using an AND gate with the following inputs: — QL2 (QL2 high charge phase) — COSCINT (COSCINT high the CT voltage is lower than the intermediary value). So, using the output of this AND gate, Sf is obtained. This signal Sf is connected to a logic block consisting of two AND gates and an OR one. This block aims at supplying a signal VS that: — gets high as soon as Sf becomes high if the PWM latch output is low — gets low as soon as the PWM latch is set and then remains low until the next cycle.

Vref Icharge COSCINT Vint

&

sync

DISCH PWM Latch Output

COSC HIGH 3.6 V

& Sf

COSCINT

PWM VS Latch Set

&

&

COSC LOW QL2

1.6 V

VDT (from demag CT %D"°*


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MC34067, MC33067

Figure 12. Operating Frequency versus Supply Current

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Error Amp output high, minimum IOSC current occurring at minimum input voltage, maximum load.

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MC34067, MC33067 OPERATING DESCRIPTION Introduction

frequencies exceeding 1.0 MHz. The Error Amplifier can control the oscillator frequency over a 1000:1 frequency range, and both the minimum and maximum frequencies are easily and accurately programmed by the proper selection of external components. The functional diagram of the Oscillator and One–Shot timer is shown in Figure 16. The oscillator capacitor (COSC) is initially charged by transistor Q1. When COSC exceeds the 4.9 V upper threshold of the oscillator comparator, the base of Q1 is pulled low allowing COSC to discharge through the external resistor, (ROSC), and the oscillator control current, (IOSC). When the voltage on COSC falls below the comparator’s 3.6 V lower threshold, Q1 turns on and again charges COSC. COSC charges from 3.6 V to 5.1 V in less than 50 ns. The high slew rate of COSC and the propagation delay of the comparator make it difficult to control the peak voltage. This accuracy issue is overcome by clamping the base of Q1 through a diode to a voltage reference. The peak voltage of the oscillator waveform is thereby precisely set at 5.1 V.

As power supply designers have strived to increase power conversion efficiency and reduce passive component size, high frequency resonant mode power converters have emerged as attractive alternatives to conventional pulse–width modulated control. When compared to pulse–width modulated converters, resonant mode control offers several benefits including lower switching losses, higher efficiency, lower EMI emission, and smaller size. A new integrated circuit has been developed to support this trend in power supply design. The MC34067 Resonant Mode Controller is a high performance bipolar IC dedicated to variable frequency power control at frequencies exceeding 1.0 MHz. This integrated circuit provides the features and performance specifically for zero voltage switching resonant mode power supply applications. The primary purpose of the control chip is to provide a fixed off–time to the gates of external power MOSFETs at a repetition rate regulated by a feedback control loop. Additional features of the IC ensure that system startup and fault conditions are administered in a safe, controlled manner. A simplified block diagram of the IC is shown on the front page, which identifies the main functional blocks and the block–to–block interconnects. Figure 14 is a detailed functional diagram which accurately represents the internal circuitry. The various functions can be divided into two sections. The first section includes the primary control path which produces precise output pulses at the desired frequency. Included in this section are a variable frequency Oscillator, a One–Shot, a pulse Steering Flip–Flop, a pair of power MOSFET Drivers, and a wide bandwidth Error Amplifier. The second section provides several peripheral support functions including a voltage reference, undervoltage lockout, Soft–Start circuit, and a fault detector.

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Figure 16. Oscillator and One–Shot Timer

Primary Control Path

The output pulse width and repetition rate are regulated through the interaction of the variable frequency Oscillator, One–Shot timer and Error Amplifier. The Oscillator triggers the One–Shot which generates a pulse that is alternately steered to a pair of totem pole output drivers by a toggle Flip–Flop. The Error Amplifier monitors the output of the regulator and modulates the frequency of the Oscillator. High speed Schottky logic is used throughout the primary control channel to minimize delays and enhance high frequency characteristics.

The frequency of the Oscillator is modulated by varying the current flowing out of the Oscillator Control Current (IOSC) pin. The IOSC pin is the output of a voltage regulator. The input of the voltage regulator is tied to the variable frequency oscillator. The discharge current of the Oscillator increases by increasing the current out of the IOSC pin. Resistor RVFO is used in conjunction with the Error Amp output to change the IOSC current. Maximum frequency occurs when the Error Amplifier output is at its low state with a saturation voltage of 0.1 V at 1.0 mA. The minimum oscillator frequency will result when the IOSC current is zero, and COSC is discharged through the external resistor (ROSC). This occurs when the Error Amplifier output is at its high state of 2.5 V. The minimum and maximum oscillator frequencies are programmed by the proper selection of resistor ROSC and RVFO. The minimum frequency is programmed by ROSC using Equation 1:

Oscillator

The characteristics of the variable frequency Oscillator are crucial for precise controller performance at high operating frequencies. In addition to triggering the One–Shot timer and initiating the output deadtime, the oscillator also determines the initial voltage for the one–shot capacitor. The Oscillator is designed to operate at


MC34067, MC33067 1 – t PD t (max) – 70 ns ƒ(min) R OSC = = 0.348 C OSC C OSC ȏ n 5.1 3.6 where tPD is the internal propagation delay.

Error Amplifier

A fully accessible high performance Error Amplifier is provided for feedback control of the power supply system. The Error Amplifier is internally compensated and features dc open loop gain greater than 70 dB, input offset voltage of less than 10 mV and a guaranteed minimum gain–bandwidth product of 2.5 MHz. The input common mode range extends from 1.5 V to 5.1 V, which includes the reference voltage.

(1)

ǒ Ǔ

The maximum oscillator frequency is set by the current through resistor RVFO. The current required to discharge COSC at the maximum oscillator frequency can be calculated by Equation 2: I (max) = C OSC

5.1 – 3.6 1 ƒ(max)

= 1.5COSC ƒ(max)

30''(! *!' * !

(2) +*

The discharge current through ROSC must also be known and can be calculated by Equation 3:

ǒ

–

5.1 – 3.6 = IR ε OSC ROSC

ǒ

–

=

1.5 R OSC

ε

1

ƒ (min) R OSC COSC

< ! + ! +< ! + !

Ǔ

(3)

ƒ(min) R OSC COSC

: ;5 *4(

: ;5

Figure 17. Error Amplifier and Clamp

When the Error Amplifier output is coupled to the IOSC pin by RVFO, as illustrated in Figure 17, it provides the Oscillator Control Current, IOSC. The output swing of the Error Amplifier is restricted by a clamp circuit to improve its transient recovery time.

Resistor RVFO can now be calculated by Equation 4: 2.5 – V EAsat RVFO = I(max) – I R OSC

2

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1

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(4)

One–Shot Timer

Output Section

The One–Shot is designed to disable both outputs simultaneously providing a deadtime before either output is enabled. The One–Shot capacitor (CT) is charged concurrently with the oscillator capacitor by transistor Q1, as shown in Figure 16. The one–shot period begins when the oscillator comparator turns off Q1, allowing CT to discharge. The period ends when resistor RT discharges CT to the threshold of the One–Shot comparator. The lower threshold of the One–Shot is 3.6 V. By choosing CT, RT can by solved by Equation 5:

The pulse(tOS), generated by the Oscillator and One–Shot timer is gated to dual totem–pole output drives by the Steering Flip–Flop shown in Figure 18. Positive transitions of tOS toggle the Flip–Flop, which causes the pulses to alternate between Output A and Output B. The flip–flop is reset by the undervoltage lockout circuit during startup to guarantee that the first pulse appears at Output A.

RT =

t OS

ǒ Ǔ

C T ȏn 5.1 3.6

=

: ±

t OS 0.348 C T

(5)

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Errors in the threshold voltage and propagation delays through the output drivers will affect the One–Shot period. To guarantee accuracy, the output pulse of the control chip is trimmed to within 5% of 250 ns with nominal values of RT and CT. The outputs of the Oscillator and One–Shot comparators are OR’d together to produce the pulse tOS, which drives the Flip–Flop and output drivers. The output pulse (tOS) is initiated by the Oscillator and terminated by the One–Shot comparator. With zero–voltage resonant mode converters, the oscillator discharge time should never be set less than the one–shot period.

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Figure 18. Steering Flip–Flop and Output Drivers


MC34067, MC33067 current during output transitions. The MC34067 utilizes a unique design that virtually eliminates cross conduction, thus controlling the chip power dissipation at high frequencies. A separate power ground pin is provided to isolate the sensitive analog circuitry from large transient currents.

The totem–pole output drivers are ideally suited for driving power MOSFETs and are capable of sourcing and sinking 1.5 A. Rise and fall times are typically 20 ns when driving a 1.0 nF load. High source/sink capability in a totem–pole driver normally increases the risk of high cross conduction **

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Figure 19. Undervoltage Lockout and Reference

PERIPHERAL SUPPORT FUNCTIONS Fault Detector

The MC34067 Resonant Controller provides a number of support and protection functions including a precision voltage reference, undervoltage lockout comparators, soft–start circuitry, and a fault detector. These peripheral circuits ensure that the power supply can be turned on and off in a controlled manner and that the system will be quickly disabled when a fault condition occurs.

The high speed Fault Comparator illustrated in Figure 20 can protect a power supply from destruction under fault conditions. The Fault Input pin connects to the input of the Fault Comparator. The Fault Comparator output connects to the output drivers. This direct path reduces the propagation delay from the Fault Input to the A and B outputs to typically 70 ns. The Fault Comparator output is also OR’d with the UVLO output from the Vref UVLO comparator to produce the logic output labeled “UVLO+Fault”. This signal disables the Oscillator and One–Shot by forcing both the COSC and CT capacitors to be continually charged.

Undervoltage Lockout and Voltage Reference

Separate undervoltage lockout comparators sense the input VCC voltage and the regulated reference voltage as illustrated in Figure 19. When VCC increases to the upper threshold voltage, the VCC UVLO comparator enables the Reference Regulator. After the Vref output of the Reference Regulator rises to 4.2 V, the Vref UVLO comparator switches the UVLO signal to a logic zero state enabling the primary control path. Reducing VCC to the lower threshold voltage causes the VCC UVLO comparator to disable the Reference Regulator. The Vref UVLO comparator then switches the UVLO output to a logic one state disabling the controller. The Enable/UVLO Adjust pin allows the power supply designer to select the VCC UVLO threshold voltages. When this pin is open, the comparator switches the controller on at 16 V and off at 9.0 V. If this pin is connected to the VCC terminal, the upper and lower thresholds are reduced to 9.0 V and 8.6 V, respectively. Forcing the Enable/UVLO Adjust pin low will pull the VCC UVLO comparator input low (through an internal diode) turning off the controller. The Reference Regulator provides a precise 5.1 V reference to internal circuitry and can deliver up to 10 mA to external loads. The reference is trimmed to better than 2% initial accuracy and includes active short circuit protection.

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Figure 20. Fault Detector and Soft–Start


MC34067, MC33067 Soft–Start Circuit

Amplifier output low. After UVLO+Fault switches to a logic zero, the soft–start capacitor is charged by a 9.0 µA current source. The buffer allows the Error Amplifier output to follow the soft–start capacitor until it is regulated by the Error Amplifier inputs. The soft–start function is generally applicable to controllers operating below resonance and can be disabled by simply opening the CSoft–Start terminal.

The Soft–Start circuit shown in Figure 20 forces the variable frequency Oscillator to start at the maximum frequency and ramp downward until regulated by the feedback control loop. The external capacitor at the CSoft–Start terminal is initially discharged by the UVLO+Fault signal. The low voltage on the capacitor passes through the Soft–Start Buffer to hold the Error

APPLICATIONS INFORMATION The MC34067 is specifically designed for zero voltage switching (ZVS) quasi–resonant converter (QRC) applications. The IC is optimized for double–ended push–pull or bridge type converters operating in continuous conduction mode. Operation of this type of ZVS with resonant properties is similar to standard push–pull or bridge circuits in that the energy is transferred during the transistor on–time. The difference is that a series resonant tank is usually introduced to shape the voltage across the power transistor prior to turn–on. The resonant tank in this topology is not used to deliver energy to the output as is the case with zero current switch topologies. When the power transistor is enabled the voltage across it should already be zero, yielding minimal switching loss. Figure 21 shows a timing diagram for a half–bridge ZVS QRC. An application circuit is shown in Figure 22. The circuit built is a dc to dc half–bridge converter delivering 75 W to the output from a 48 V source. When building a zero voltage switch (ZVS) circuit, the objective is to waveshape the power transistor’s voltage waveform so that the voltage across the transistor is zero when the device is turned on. The purpose of the control IC is to allow a resonant tank to waveshape the voltage across the power transistor while still maintaining regulation. This is accomplished by maintaining a fixed deadtime and by varying the frequency; thus the effective duty cycle is changed. Primary side resonance can be used with ZVS circuits. In the application circuit, the elements that make the resonant tank are the primary leakage inductance of the transformer (LL) and the average output capacitance (COSS) of a power MOSFET (CR). The desired resonant frequency for the application circuit is calculated by Equation 6: ƒr =

In the application circuit, the operating voltage is low and the value of COSS versus Drain Voltage is known. Because the COSS of a MOSFET changes with drain voltage, the value of the CR is approximated as the average COSS of the MOSFET. For the application circuit the average COSS can be calculated by Equation 7: CR =

L L 2C R

1 V 2 in

(7)

The MOSFET chosen fixes CR and that LL is adjusted to achieve the desired resonant frequency. However, the desired resonant frequency is less critical than the leakage inductance. Figure 21 shows the primary current ramping toward its peak value during the resonant transition. During this time, there is circulating current flowing through the secondary inductance, which effectively makes the primary inductance appear shorted. Therefore, the current through the primary will ramp to its peak value at a rate controlled by the leakage inductance and the applied voltage. Energy is not transferred to the secondary during this stage, because the primary current has not overcome the circulating current in the secondary. The larger the leakage inductance, the longer it takes for the primary current to slew. The practical effect of this is to lower the duty cycle, thus reducing the operating range. The maximum duty cycle is controlled by the leakage inductance, not by the MC34067. The One–Shot in the MC34067 only assures that the power switch is turned on under a zero voltage condition. Adjust the one–shot period so that the output switch is activated while the primary current is slewing but before the current changes polarity. The resonant stage should then be designed to be as long as the time for the primary current to go to zero amps.

1 2π

2 * C OSS measured at

(6)


MC34067, MC33067 $ ** #$ %4!

$ #$

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. +5(@

;

% +5(@ 3 2(!

! ! ) '!(

Figure 21. Application Timing Diagram


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##

1

$ 1 1 $1 ##

*,

$1

#

$1

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, A> 3

#

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#$1

1949

http://onsemi.com

"

1

$

"

T1 = Primary: 12 turns #48 AWG (1300 strands litz wire) Secondary: 6 turns center tapped #48 AWG (1300 strands litz wire) Core: Philips 3F3 4312 020 4124 Bobbin: Philips 4322 021 3525 Primary Leakage Inductance = 1.0 µH

Test

! >A$

Conditions

Results

Line Regulation

V in = 40 V to 56 V, IO =15 A

20 mV = ±0.198%

Load Regulation

V in = 48 V, IO = 10 A to 15 A

4.0 mV = ±0.039%

Output Ripple

V in = 48 V, I O = 15 A, fswitch = 1.0 MHz

25 mVp–p

Efficiency

V in = 48 V, I O = 10 A, fswitch = 1.7 MHz V in = 48 V, I O = 15 A, fswitch = 1.0 MHz

83.5% 84.2%

T2 = All windings: 8 turns #36 AWG Core: Philips 3F3 EP7–3F3 Bobbin: Philips EP7PCB1–6 T3 = Coilcraft D1870 (100 turns) L1 = 2 turns #48 AWG (1300 strands litz wire) Core: Philips 3F3 EP10–3F3 Bobbin: Philips EP10PCB1–8 Inductance = 1.8 µH L2 = 5 turns #48 AWG (1300 strands litz wire) Core: 0.5″ diameter air code Inductance = 100 nH Heatsinks = AAVID Engineering Inc. 533402B02552 with clip MC34067–5803 Insulators = Berquist Sil–Pad 1500


MC34067, MC33067

$1

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Figure 23. Printed Circuit Board and Component Layout http://onsemi.com 1950

)B* "# '" ;7 "# # The MAX1720 is a CMOS charge pump voltage inverter that is designed for operation over an input voltage range of 1.15 V to 5.5 V with an output current capability in excess of 50 mA. The operating current consumption is only 67 A, and a power saving shutdown input is provided to further reduce the current to a mere 0.4 A. The device contains a 12 kHz oscillator that drives four low resistance MOSFET switches, yielding a low output resistance of 26 and a voltage conversion efficiency of 99%. This device requires only two external 10 F capacitors for a complete inverter making it an ideal solution for numerous battery powered and board level applications. The MAX1720 is available in the space saving TSOP–6 (SOT–23–6) package.

http://onsemi.com MARKING DIAGRAM 6 TSOP–6 SN SUFFIX CASE 318G

6

EACYW 1

1

Features

• • • • • • •

EAC = Device Code Y = Year W = Work Week

Operating Voltage Range of 1.15 V to 5.5 V Output Current Capability in Excess of 50 mA Low Current Consumption of 67 A Power Saving Shutdown Input for a Reduced Current of 0.4 A Operation at 12 kHz Low Output Resistance of 26 Space Saving TSOP–6 (SOT–23–6) Package

PIN CONNECTIONS


• • • • • • • •

LCD Panel Bias Cellular Telephones Pagers Personal Digital Assistants Electronic Games Digital Cameras Camcorders Hand Held Instruments

Vout

1

6

C+

Vin

2

5

SHDN

C–

3

4

GND

(Top View)


Package

Shipping

MAX1720EUT

TSOP–6

3000 Tape & Reel

–Vout

Vin

1

6

2

5

3

4





1951

Publication Order Number: MAX1720/D

MAX1720 MAXIMUM RATINGS*

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Symbol

Value

Unit

Input Voltage Range (Vin to GND)

Rating

Vin

–0.3 to 6.0

V

Output Voltage Range (Vout to GND)

Vout

–6.0 to 0.3

V

Output Current (Note 1)

Iout

100

mA

Output Short Circuit Duration (Vout to GND, Note 1)

tSC

Indefinite

sec


TJ

150

°C

Power Dissipation and Thermal Characteristics Thermal Resistance, Junction to Air Maximum Power Dissipation @ TA = 70°C

RθJA PD

256 313

°C/W mW

Storage Temperature

Tstg

–55 to 150

°C

*ESD Ratings ESD Machine Model Protection up to 200 V, Class B ESD Human Body Model Protection up to 2000 V, Class 2

ELECTRICAL CHARACTERISTICS (Vin = 5.0 V, C1 = 10 µF, C2 = 10 µF, TA = –40°C to 85°C, typical values shown are for TA = 25°C unless otherwise noted. See Figure 14 for Test Setup.) Characteristic

Symbol

Min

Typ

Max

Unit

Operating Supply Voltage Range (SHDN = Vin, RL = 10 k)

Vin

1.5 to 5.5

1.15 to 6.0

–

V

Supply Current Device Operating (SHDN = 5.0 V, RL = R) TA = 25°C TA = 85°C

Iin – –

67 72

90 100

– –

0.4 1.6

– –

8.4 6.0

12 –

15.6 21

µA

µA

Supply Current Device Shutdown (SHDN = 0 V) TA = 25°C TA = 85°C

ISHDN

Oscillator Frequency TA = 25°C TA = –40°C to 85°C

fOSC

Output Resistance (Iout = 25 mA, Note 2)

Rout

–

26

50

Ω

Voltage Conversion Efficiency (RL = R)

VEFF

99

99.9

–

%

Power Conversion Efficiency (RL = 1.0 k)

PEFF

–

96

–

%

– –

0.6 Vin 0.5 Vin

– –

Shutdown Input Threshold Voltage (Vin = 1.5 V to 5.5 V) High State, Device Operating Low State, Device Shutdown Shutdown Input Bias Current High State, Device Operating, SHDN = 5.0 V TA = 25°C TA = 85°C Low State, Device Shutdown, SHDN = 0 V TA = 25°C TA = 85°C Wake–Up Time from Shutdown (RL = 1.0 k)

kHz

Vth(SHDN)

V

pA IIH – –

5.0 100

– –

– –

5.0 100

– –

–

1.2

–

IIL

tWKUP

ms

1. Maximum Package power dissipation limits must be observed to ensure that the maximum junction temperature is not exceeded. TJ + TA ) (PD RJA) 2. Capacitors C1 and C2 contribution is approximately 20% of the total output resistance.


MAX1720 90 Figure 14 Test Setup TA = 25°C

90

Rout, OUTPUT RESISTANCE (Ω)


100

80 70 60 50 40 30 20

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Figure 14 Test Setup 80 Vin = 1.5 V

70

Vin = 2.0 V 60 50 Vin = 3.3 V 40 30 Vin = 5.0 V 20 –50

5.5

Vin, SUPPLY VOLTAGE (V)

Vout, OUTPUT VOLTAGE RIPPLE (mVp–p)


30 Vin = 4.75 V Vout = –4.00 V

20 Vin = 3.15 V Vout = –2.50 V

10 Vin = 1.90 V Vout = –1.50 V

5

Figure 14 Test Setup TA = 25°C

0 10

0

20

40

30

Vin = 4.75 V Vout = –4.00 V

300 250 200

Vin = 3.15 V Vout = –2.50 V

150

Vin = 1.90 V Vout = –1.50 V

100 50 0 10

20

30

40

C1, C2, C3, CAPACITANCE (µF)


Figure 4. Output Current vs. Capacitance

Figure 5. Output Voltage Ripple vs. Capacitance

Figure 14 Test Setup RL = ∞ 70 TA = 85°C 60 TA = 25°C 50

TA = –40°C

40

2.0

2.5

3.0

3.5

4.0

100


350

0


Iin, SUPPLY CURRENT (µA)

75

400

50

80

30 1.5

50

25

Figure 3. Output Resistance vs. Ambient Temperature

35

15

0


Figure 2. Output Resistance vs. Supply Voltage

25

–25

4.5

5.0

13.0 Figure 14 Test Setup 12.5 Vin = 5.0 V

12.0 11.5 11.0

Vin = 1.5 V

10.5 10.0 –50

Vin = 3.3 V

–25

0

25

50

75



Figure 6. Supply Current vs. Supply Voltage

Figure 7. Oscillator Frequency vs. Ambient Temperature


50

100


0.0

, POWER CONVERSION EFFICIENCY (%)

MAX1720 100


Vin = 2.0 V

–1.0

Vin = 3.3 V

–2.0 –3.0

Vin = 5.0 V –4.0 –5.0 –6.0 10

20

30

40

50

90 80 70 60

Vin = 2.0 V

50 40

0

10

20

30

40

Figure 8. Output Voltage vs. Output Current

Figure 9. Power Conversion Efficiency vs. Output Current ISHDN, SHUTDOWN SUPPLY CURRENT (µA)


Figure 14 Test Setup Vin = 3.3 V Iout = 5.0 mA TA = 25°C

1.50

Vin = 5.0 V

RL = 10 kΩ SHDN = GND Vin = 3.3 V

1.25 1.00 0.75

Vin = 1.5 V

0.50 0.25 –50

–25

0

25

50

75

TIME = 25 µs / Div.


Figure 10. Output Voltage Ripple and Noise

Figure 11. Shutdown Supply Current vs. Ambient Temperature SHDN = 5.0V/Div. WAKEUP TIME FROM SHUTDOWN

TA = 25°C 4.5 4.0 Low State, Device Shutdown

3.5 3.0

High State, Device Operating

2.5 2.0 1.5 0.5

1.0

1.5

2.0

2.5

Vin = 5.0 V RL = 1.0 k TA = 25°C

Vout = 1.0 V/Div.

3.0

Vth(SHND), SHUTDOWN INPUT VOLTAGE THRESHOLD (V)

Figure 12. Supply Voltage vs. Shutdown Input Voltage Threshold

TIME = 500 µs / Div.

Figure 13. Wakeup Time From Shutdown


50

1.75

5.0 Vin, SUPPLY VOLTAGE (V)

Vin = 5.0 V

Vin = 3.3 V

Vin = 1.5 V


OUTPUT VOLTAGE RIPPLE AND NOISE = 10 mV / Div. AC COUPLED

0


100

MAX1720 Charge Pump Efficiency

–Vout C + 2

6

1

The overall power conversion efficiency of the charge pump is affected by four factors: 1. Losses from power consumed by the internal oscillator, switch drive, etc. (which vary with input voltage, temperature and oscillator frequency). 2. I2R losses due to the on–resistance of the MOSFET switches on–board the charge pump. 3. Charge pump capacitor losses due to Equivalent Series Resistance (ESR). 4. Losses that occur during charge transfer from the commutation capacitor to the output capacitor when a voltage difference between the two capacitors exists. Most of the conversion losses are due to factors 2, 3 and 4. These losses are given by Equation 1.

RL

OSC Vin

+ C3

2

5

3

4

+ C1

C1 = C2 = C3 = 10 F

Figure 14. Test Setup/Voltage Inverter

DETAILED OPERATING DESCRIPTION The MAX1720 charge pump converter inverts the voltage applied to the Vin pin. Conversion consists of a two–phase operation (Figure 15). During the first phase, switches S2 and S4 are open and S1 and S3 are closed. During this time, C1 charges to the voltage on Vin and load current is supplied from C2. During the second phase, S2 and S4 are closed, and S1 and S3 are open. This action connects C1 across C2, restoring charge to C2. S1

ƪ

P + I out 2 LOSS(2,3,4) 1

(f

OSC

)C1

) 8R

SWITCH

R out ^ I out 2 ) 4ESR

C1

) ESR

ƫ

C2

(eq. 1)

The 1/(fOSC)(C1) term in Equation 1 is the effective output resistance of an ideal switched capacitor circuit (Figures 16 and 17). The losses due to charge transfer above are also shown in Equation 2. The output voltage ripple is given by Equation 3.

S2

Vin

PLOSS + [ 0.5C1 (Vin 2 * Vout 2)

C1

) 0.5C2 (VRIPPLE 2 * 2VoutVRIPPLE)]

fOSC (eq. 2)

C2

V S3

S4

RIPPLE

+

I out (f

OSC

)(C 2)

) 2(I out)(ESR ) C2

–Vout

(eq. 3)

f

From Osc Vin

Vout

C1

Figure 15. Ideal Switched Capacitor Charge Pump

C2

RL

APPLICATIONS INFORMATION Output Voltage Considerations

Figure 16. Ideal Switched Capacitor Model

The MAX1720 performs voltage conversion but does not provide regulation. The output voltage will drop in a linear manner with respect to load current. The value of this equivalent output resistance is approximately 26 Ω nominal at 25°C with Vin = 5.0 V. Vout is approximately –5.0 V at light loads, and drops according to the equation below: VDROP + Iout

REQUIV Vin

Vout R

Rout

EQUIV

+

f

1 C1

C2

RL

Vout + * (Vin * VDROP) Figure 17. Equivalent Output Resistance


MAX1720 Capacitor Selection

switching internals in the device. If the device is loaded from Vout to GND, it is recommended that a large value capacitor (at least equal to C1) be connected from Vin to GND. If the device is loaded from Vin to Vout, a small (0.7 µF) capacitor between the pins is sufficient.

In order to maintain the lowest output resistance and output ripple voltage, it is recommended that low ESR capacitors be used. Additionally, larger values of C1 will lower the output resistance and larger values of C2 will reduce output voltage ripple. (See Equation 3). Table 1 shows various values of C1, C2 and C3 with the corresponding output resistance values at 25°C. Table 2 shows the output voltage ripple for various values of C1, C2 and C3. The data in Tables 1 and 2 was measured not calculated.

Voltage Inverter

C1 = C2 = C3 (mF)

Rout (W)

The most common application for a charge pump is the voltage inverter (Figure 14). This application uses two or three external capacitors. The C1 (pump capacitor) and C2 (output capacitor) are required. The input bypass capacitor, C3, may be necessary depending on the application. The output is equal to –Vin plus any voltage drops due to loading. Refer to Tables 1 and 2 for capacitor selection. The test setup used for the majority of the characterization is shown in Figure 14.

0.7

129.1

Layout Considerations

1.4

69.5

3.3

37.0

7.3

26.5

10

25.9

As with any switching power supply circuit, good layout practice is recommended. Mount components as close together as possible to minimize stray inductance and capacitance. Also, use a large ground plane to minimize noise leakage into other circuitry.

24

24.1

50

24

Table 1. Output Resistance vs. Capacitance (C1 = C2 = C3), Vin = 4.75 V and Vout = –4.0 V

Capacitor Resources

Selecting the proper type of capacitor can reduce switching loss. Low ESR capacitors are recommended. The MAX1720 was characterized using the capacitors listed in Table 3. This list identifies low ESR capacitors for the voltage inverter application.

Table 2. Output Voltage Ripple vs. Capacitance (C1 = C2 = C3), Vin = 4.75 V and Vout = –4.0 V C1 = C2 = C3 (mF)

Output Voltage Ripple (mV)

0.7

382

Manufacturer/Contact

1.4

342

3.3

255

AVX 843–448–9411 www.avxcorp.com

7.3

164

10

132

24

59

50

38

Table 3. Capacitor Types

Cornell Dubilier 508–996–8561 www.cornell–dubilier.com ll d bili

Input Supply Bypassing

The input voltage, Vin should be capacitively bypassed to reduce AC impedance and minimize noise effects due to the

TPS

ESRD

Sanyo/Os–con Sanyo/Os con 619–661–6835 www.sanyovideo.com/oscon.htm id / ht

SN SVP

Vishay 603–224–1961 www.vishay.com i h

593D 594


Part Types/Series

MAX1720

–Vout

6

1 OSC

+ Vin

2

+

5 +

3

4

Capacitors = 10 µF

Figure 18. Voltage Inverter

The MAX1720 primary function is a voltage inverter. The device will convert 5.0 V into –5.0 V with light loads. Two capacitors are required for the inverter to function. A third capacitor, the input bypass capacitor, may be required depending on the power source for the inverter. The performance for this device is illustrated below. 0 Vout, OUTPUT VOLTAGE (V)

TA = 25°C –1.0 Vin = 3.3 V

–2.0 –3.0

Vin = 5.0 V

–4.0 –5.0 –6.0 0

10

20

30

40


Figure 19. Inverter Load Regulation, Output Voltage vs. Output Current


50

MAX1720 Vin

–Vout

6

1 + +

OSC

+

2

6

1

OSC 5

+

2

5

3

4

+ 3

4

Capacitors = 10 µF

Figure 20. Cascaded Devices for Increased Negative Output Voltage

Two or more devices can be cascaded for increased output voltage. Under light load conditions, the output voltage is approximately equal to –Vin times the number of stages. The converter output resistance increases dramatically with each additional stage. This is due to a reduction of input voltage to each successive stage as the converter output is loaded. Note that the ground connection for each successive stage must connect to the negative output of the previous stage. The performance characteristics for a converter consisting of two cascaded devices are shown below. 0 Vout, OUTPUT VOLTAGE (V)

TA = 25°C –2.0 B –4.0

A

–6.0

–8.0

–10.0

0

10

20

30

40


Figure 21. Cascade Load Regulation, Output Voltage vs. Output Current


Curve

Vin (V)

Rout (Ω)

A

5.0

140

B

3.0

174

MAX1720

6

1 OSC Vin

+

2

–Vout

5 + +

3

+

+

4

Capacitors = 10 µF

Figure 22. Negative Output Voltage Doubler

A single device can be used to construct a negative voltage doubler. The output voltage is approximately equal to –2Vin minus the forward voltage drop of each external diode. The performance characteristics for the above converter are shown below. Note that curves A and C show the circuit performance with economical 1N4148 diodes, while curves B and D are with lower loss MBRA120E Schottky diodes.


0 TA = 25°C –2.0 A –4.0 B

Curve

Vin (V)

All Diodes

Rout (W)

A

3.0

1N4148

124

B

3.0

MBRA120E

115

C

5.0

1N4148

96

D

5.0

MBRA120E

94

C

–6.0

–8.0

D

–10.0 0

10

20

30

40


Figure 23. Doubler Load Regulation, Output Voltage vs. Output Current


MAX1720

6

1 OSC Vin

2

+

–Vout

5 + +

3

+

+

+

+

4

Capacitors = 10 µF

Figure 24. Negative Output Voltage Tripler

A single device can be used to construct a negative voltage tripler. The output voltage is approximately equal to –3Vin minus the forward voltage drop of each external diode. The performance characteristics for the above converter are shown below. Note that curves A and C show the circuit performance with economical 1N4148 diodes, while curves B and D are with lower loss MBRA120E Schottky diodes. 0

Vout, OUTPUT VOLTAGE

–2.0

A B

–4.0 –6.0 C

–8.0

D

–10.0 –12.0 –14.0

TA = 25°C

–16.0 0

10

20

30

40

50

Iout, OUTPUT CURRENT

Figure 25. Tripler Load Regulation, Output Voltage vs. Output Current


Curve

Vin (V)

All Diodes

Rout (W)

A

3.0

1N4148

267

B

3.0

MBRA120E

250

C

5.0

1N4148

205

D

5.0

MBRA120E

195

MAX1720

6

1 OSC

+ Vin

+

2

5

3

4

+

Vout

Capacitors = 10 µF

Figure 26. Positive Output Voltage Doubler

A single device can be used to construct a positive voltage doubler. The output voltage is approximately equal to 2Vin minus the forward voltage drop of each external diode. The performance characteristics for the above converter are shown below. Note that curves A and C show the circuit performance with economical 1N4148 diodes, while curves B and D are with lower loss MBRA120E Schottky diodes. 10.0 Vout, OUTPUT VOLTAGE (V)

D 8.0 C 6.0

Curve

Vin (V)

All Diodes

Rout (W)

A

3.0

1N4148

32

B

3.0

MBRA120E

26

C

5.0

1N4148

26

D

5.0

MBRA120E

21

B

4.0 A 2.0 TA = 25°C 0 0

10

20

30

40


Figure 27. Doubler Load Regulation, Output Voltage vs. Output Current


MAX1720

6

1 OSC

+ Vin

2

+

+ Vout

5 +

3

+

4

Capacitors = 10 µF

Figure 28. Positive Output Voltage Tripler

A single device can be used to construct a positive voltage tripler. The output voltage is approximately equal to 3Vin minus the forward voltage drop of each external diode. The performance characteristics for the above converter are shown below. Note that curves A and C show the circuit performance with economical 1N4148 diodes, while curves B and D are with lower loss MBRA120E Schottky diodes. 14.0 Vout, OUTPUT VOLTAGE (V)

D 12.0 10.0 C

Curve

Vin (V)

All Diodes

Rout (W)

A

3.0

1N4148

111

B

3.0

MBRA120E

97

C

5.0

1N4148

85

D

5.0

MBRA120E

75

8.0 6.0

B

4.0 2.0

A

TA = 25°C 0 0

10

20

30

40


Figure 29. Tripler Load Regulation, Output Voltage vs. Output Current


MAX1720 –Vout + 6

1 OSC Vin

2

+

5

+

100 k 3

4

Capacitors = 10 µF

Figure 30. Load Regulated Negative Output Voltage

A zener diode can be used with the shutdown input to provide closed loop regulation performance. This significantly reduces the converter’s output resistance and dramatically enhances the load regulation. For closed loop operation, the desired regulated output voltage must be lower in magnitude than –Vin. The output will regulate at a level of –VZ + Vth(SHDN). Note that the shutdown input voltage threshold is typically 0.5 Vin and therefore, the regulated output voltage will change proportional to the converter’s input. This characteristic will not present a problem when used in applications with constant input voltage. In this case the zener breakdown was measured at 25 A. The performance characteristics for the above converter are shown below. Note that the dashed curve sections represent the converter’s open loop performance.


–1.0 TA = 25°C –2.0 A –3.0 B –4.0

–5.0 0

10

20

30

40

50

60


Figure 31. Load Regulation, Output Voltage vs. Output Current


Curve

Vin (V)

Vz (V)

Vout (V)

A

3.3 V

4.5

–2.8

B

5.0 V

6.5

–3.8

MAX1720 –Vout R1

6

1

+

OSC Vin

+

2

5

3

4

+

R2

10 k Capacitors = 10 µF

Figure 32. Line and Load Regulated Negative Output Voltage

An adjustable shunt regulator can be used with the shutdown input to give excellent closed loop regulation performance. The shunt regulator acts as a comparator with a precise input offset voltage which significantly reduces the converter’s output resistance and dramatically enhances the line and load regulation. For closed loop operation, the desired regulated output voltage must be lower in magnitude than –Vin. The output will regulate at a level of –Vref (R2/R1 + 1). The adjustable shunt regulator can be from either the TLV431 or TL431 families. The comparator offset or reference voltage is 1.25 V or 2.5 V respectively. The performance characteristics for the converter are shown below. Note that the dashed curve sections represent the converter’s open loop performance. 0 Iout = 25 mA R1 = 10 k R2 = 20 k TA = 25°C



–1.0 A –2.0

–3.0

B

–4.0

–1.0

–2.0

–3.0

TA = 25°C –5.0

0

10

20

30

40

50

60

70

–4.0 1.0

2.0

3.0

4.0

5.0

6.0




Figure 34. Line Regulation, Output Voltage vs. Input Current

Curve

Vin (V)

R1 (W)

R2 (W)

Vout (V)

A

3.0

10 k

5.0 k

–1.8

B

5.0

10 k

20 k

–3.6


MAX1720 –Vout + 6

1 OSC Vin

+

6

1 OSC

2

5

2

5

3

4

3

4

+

+ Capacitors = 10 µF

Figure 35. Paralleling Devices for Increased Negative Output Current

An increase in converter output current capability with a reduction in output resistance can be obtained by paralleling two or more devices. The output current capability is approximately equal to the number of devices paralleled. A single shared output capacitor is sufficient for proper operation but each device does require it’s own pump capacitor. Note that the output ripple frequency will be complex since the oscillators are not synchronized. The performance characteristics for a converter consisting of two paralleled devices is shown below.


0 TA = 25°C –1.0 B

–2.0

–3.0 A

–4.0

–5.0 0

10

20

30

40

50

60

70

80

90

100


Figure 36. Parallel Load Regulation, Output Voltage vs. Output Current


Curve

Vin (V)

Rout (Ω)

A

5.0

14.5

B

3.0

17

MAX1720

Q2 6

1

+

–Vout

+

OSC Vin

C1

Q1

2

5

3

4

C3

+

C2

C1 = C2 = 470 µF C3 = 220 µF Q1 = PZT751 Q2 = PZT651

–Vout = Vin –VBE(Q1) – VBE(Q2) –2 VF

Figure 37. External Switch for Increased Negative Output Current

The output current capability of the MAX1720 can be extended beyond 600 mA with the addition of two external switch transistors and two Schottky diodes. The output voltage is approximately equal to –Vin minus the sum of the base emitter drops of both transistors and the forward voltage of both diodes. The performance characteristics for the converter are shown below. Note that the output resistance is reduced to 0.9 ohms.


–2.2

–2.4

–2.6

–2.8 Vin = 5.0 V Rout = 0.9 Ω TA = 25°C

–3.0

–3.2

0

0.1

0.2

0.3

0.4

0.5


Figure 38. Current Boosted Load Regulation, Output Voltage vs. Output Current


0.6

MAX1720 10 k

R2 Q2 R1

C1

–Vout

6

1

+

OSC Vin

+

Q1 +

2

5

3

4

C3

C2


Figure 39. Line and Load Regulated Negative Output Voltage with High Current Capability

This converter is a combination of Figures 37 and 32. It provides a line and load regulated output of –2.36 V at up to 450 mA with an input voltage of 5.0 V. The output will regulate at a level of –Vref (R2/R1 + 1). The performance characteristics are shown below. Note, the dashed line is the open loop and the solid line is the closed loop performance. –1.0 Vout, OUTPUT VOLTAGE (V)


–2.2

–2.4

–2.6

–2.8 Vin = 5.0 V Rout = 0.9 Ω R1 = 10 kΩ R2 = 9.0 kΩ TA = 25°C

–3.0

–3.2

0

0.1

0.2

0.3

0.4

0.5

0.6

Iout = 100 mA R1 = 10 k R2 = 9 kΩ TA = 25°C

–1.2 –1.4 –1.6 –1.8 –2.0 –2.2 –2.4 3.0

3.5

4.0

4.5

5.0

5.5



Figure 40. Current Boosted Load Regulation, Output Voltage vs. Output Current

Figure 41. Current Boosted Line Regulation, Output Voltage vs. Input Voltage


6.0

MAX1720 50 Q2

C1 Vout

6

1

+

50

OSC

+

Q1 Vin

+

2

5

3

4

C2

C3 Capacitors = 220 µF Q1 = PZT751 Q2 = PZT651

Figure 42. Positive Output Voltage Doubler with High Current Capability

The MAX1720 can be configured to produce a positive output voltage doubler with current capability in excess of 500 mA. This is accomplished with the addition of two external switch transistors and two Schottky diodes. The output voltage is approximately equal to 2Vin minus the sum of the base emitter drops of both transistors and the forward voltage of both diodes. The performance characteristics for the converter is shown below. Note that the output resistance is reduced to 1.9 ohms.


8.8 Vin = 5.0 V Rout = 1.9 Ω TA = 25°C

8.4

8.0

7.6

7.2

6.8

0

0.1

0.2

0.3

0.4

0.5

0.6


Figure 43. Positive Doubler with Current Boosted Load Regulation, Output Voltage vs. Output Current


MAX1720

R1 50

10 k

Q2 6

1

50

OSC

Q1 Vin

+

2

5

3

4

R2

+

C3

Vout +

C1

C2

Capacitors = 220 µF Q1 = PZT751 Q2 = PZT651

Figure 44. Line and Load Regulated Positive Output Voltage Doubler with High Current Capability

This converter is a combination of Figures 42 and the shunt regulator to close the loop. In this case the anode of the regulator is connected to ground. This convert provides a line and load regulated output of 7.6 V at up to 300 mA with an input voltage of 5.0 V. The output will regulate at a level of Vref (R2/R1 + 1). The open loop configuration is the dashed line and the closed loop is the solid line. The performance characteristics are shown below. 8.0 Vin = 5.0 V Rout = 1.9 Ω Open Loop Rout = 0.5 Ω Closed Loop R1 = 10 k R2 = 51.3 kΩ TA = 25°C

8.4

8.0



8.8

7.6

7.2

6.8

0

0.1

0.2

0.3

0.4

0.5

0.6

7.0 6.0 5.0 4.0 Iout = 100 mA R1 = 10 k R2 = 51.3 kΩ TA = 25°C

3.0 2.0 1.0 1.0

2.0

3.0

4.0

5.0


Vin, INPUT VOLTGE (V)

Figure 45. Current Boosted Close Loop Load Regulation, Output Voltage vs. Output Current

Figure 46. Current Boosted Close Loop Line Regulation, Output Voltage vs. Input Voltage


6.0

MAX1720 Vin = –5.0 V

+

+

OSC

C

C

+

6

1

C

2

5

3

4

Vout = –2.5 V C

+ Capacitors = 10 µF

Figure 47. Negative Input Voltage Splitter

A single device can be used to split a negative input voltage. The output voltage is approximately equal to –Vin/2. The performance characteristics are shown below. Note that the converter has an output resistance of 10 ohms.


–1.5 TA = 25°C Rout = 10 Ω

–1.7

–1.9

–2.1

–2.3

–2.5 0

10

20

30

40

50

60

70


Figure 48. Negative Voltage Splitter Load Regulation, Output Voltage vs. Output Current


80

MAX1720 –Vout +

R1

R2

6

1 OSC Vin

+

2

5 10 k

3

4

+

+ +

+Vout

Capacitors = 10 µF

Figure 49. Combination of a Closed Loop Negative Inverter with a Positive Output Voltage Doubler

All of the previously shown converter circuits have only single outputs. Applications requiring multiple outputs can be constructed by incorporating combinations of the former circuits. The converter shown above combines Figures 26 and 32 to form a regulated negative output inverter with a non–regulated positive output doubler. The magnitude of –Vout is controlled by the resistor values and follows the relationship –Vref (R2/R1 + 1). Since the positive output is not within the feedback loop, its output voltage will increase as the negative output load increases. This cross regulation characteristic is shown in the upper portion of Figure 50. The dashed line is the open loop and the solid line is the closed loop configuration for the load regulation. The load regulation for the positive doubler with a constant load on the –Vout is shown in Figure 51. 10.0 Vout, OUTPUT VOLTAGE (V)


9.0 Positive Doubler Iout = 15 mA

8.0 –3.0 Negative Inverter

–4.0

Rout = 45 Ω – Open Loop Rout = 2 Ω – Closed Loop R1 = 10 k, R2 = 20 k TA = 25°C

–5.0 0

10

20

9.0

8.0

Negative Inverter Iout = 15 mA R1 = 10 k R2 = 20 k TA = 25°C

7.0 30

0

10

20

30

40

50

Iout, NEGATIVE INVERTER OUTPUT CURRENT (mA)

Iout, POSITIVE DOUBLER OUTPUT CURRENT (mA)




MAX1720 +

IC1

C1

C2

Vin

–Vout

SHDN

GND

C3

+

GND

+

0.5″ Inverter Size = 0.5 in x 0.2 in Area = 0.10 in2, 64.5 mm2

Figure 52. Inverter Circuit Board Layout, Top View Copper Side

TAPING FORM Component Taping Orientation for TSOP–6 Devices


PIN 1

Standard Reel Component Orientation (Mark Right Side Up)


Tape Width (W)

Pitch (P)

Part Per Full Reel

Diameter

TSOP–6

8 mm

4 mm

3000

7 inches


)B33 )B3> "# '" 7 The MAX828 and MAX829 are CMOS charge pump voltage inverters that are designed for operation over an input voltage range of 1.15 V to 5.5 V with an output current capability in excess of 50 mA. The operating current consumption is only 68 A for the MAX828 and 118 A for the MAX829. The devices contain an internal oscillator that operates at 12 kHz for the MAX828 and 35 kHz for the MAX829. The oscillator drives four low resistance MOSFET switches, yielding a low output resistance of 26 and a voltage conversion efficiency of 99.9%. These devices require only two external capacitors, 10 F for the MAX828 and 3.3 F for the MAX829, for a complete inverter making it an ideal solution for numerous battery powered and board level applications. The MAX828 and MAX829 are available in the space saving Thin SOT–23–5 package.

http://onsemi.com MARKING DIAGRAM 5 THIN SOT–23–5 EUK SUFFIX CASE 483

5 1

xxxYW 1

Features

xxx = Device Code MAX828 is EAA MAX829 is EAB Y = Year W = Work Week

• Operating Voltage Range of 1.15 V to 5.5 V • Output Current Capability in Excess of 50 mA • Low Current Consumption of 68 A (MAX828) or 118 A (MAX829)

• Operation at 12 kHz (MAX828) or 35 kHz (MAX829) • Low Output Resistance of 26 • Space Saving Thin SOT–23–5 Package

PIN CONFIGURATION


• • • • • • • •

Vout

1

Vin

2

C–

3

LCD Panel Bias Cellular Telephones Pagers Personal Digital Assistants Electronic Games Digital Cameras Camcorders Hand Held Instruments

GND


5

2 3

4

(Top View)

Device

Vin

C+

Thin SOT–23–5*

–Vout 1

5

Package

Shipping

MAX828EUK

Thin SOT–23–5

3000 Tape/Reel

MAX829EUK

Thin SOT–23–5

3000 Tape/Reel

4





1973

Publication Order Number: MAX828/D

MAX828, MAX829 MAXIMUM RATINGS*

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Symbol

Value

Unit

Input Voltage Range (Vin to GND)

Rating

Vin

–0.3 to 6.0

V

Output Voltage Range (Vout to GND)

Vout

–6.0 to 0.3

V

Output Current (Note 1)

Iout

100

mA

Output Short Circuit Duration (Vout to GND, Note 1)

tSC

Indefinite

sec


TJ

150

°C

Power Dissipation and Thermal Characteristics Thermal Resistance, Junction to Air Maximum Power Dissipation @ TA = 70°C

RθJA PD

256 313

°C/W mW

Storage Temperature

Tstg

–55 to 150

°C

*ESD Ratings ESD Machine Model Protection up to 200 V, Class B ESD Human Body Model Protection up to 2000 V, Class 2

ELECTRICAL CHARACTERISTICS (Vin = 5.0 V for MAX828 C1 = C2 = 10 µF, for MAX829 C1 = C2 = 3.3 µF, TA = –40°C to 85°C, typical values shown are for TA = 25°C unless otherwise noted. See Figure 20 for test setup.) Symbol

Min

Typ

Max

Unit

Operating Supply Voltage Range (RL = 10 k)

Vin

1.5 to 5.5

1.15 to 6.0

–

V

Supply Current Device Operating (RL = R) TA = 25°C MAX828 MAX829 TA = 85°C MAX828 MAX829

Iin

Characteristic

Oscillator Frequency TA = 25°C MAX828 MAX829 TA = –40°C to 85°C MAX828 MAX829

fOSC

Output Resistance (Iout = 25 mA, Note 2) MAX828 MAX829

Rout

Voltage Conversion Efficiency (RL = R) Power Conversion Efficiency (RL = 1.0 k)

µA – –

68 118

90 200

– –

73 128

100 200 kHz

8.4 24.5

12 35

15.6 45.6

6.0 19

– –

21 54

– –

26 26

50 50

VEFF

99

99.9

–

%

PEFF

–

96

–

%

Ω

1. Maximum Package power dissipation limits must be observed to ensure that the maximum junction temperature is not exceeded. TJ + TA ) (PD RJA) 2. Capacitors C1 and C2 contribution is approximately 20% of the total output resistance.


MAX828, MAX829

100 Figure 20 Test Setup

TA = 25°C



100 90 80 70 60 50 40 30 20 1.0

1.5

2.0

2.5

3.5

3.0

4.0

5.0

4.5

Figure 20 Test Setup 80 70 60 50 40 30 20 1.0

5.5

1.5

2.0


3.0

3.5

4.0

4.5

5.0

5.5

Figure 3. Output Resistance vs. Supply Voltage MAX829 100


Vin = 1.5 V



2.5


Figure 2. Output Resistance vs. Supply Voltage MAX828

80 70 Vin = 2.0 V

60 50

Vin = 3.3 V

40 30 20 –50

Vin = 5.0 V –25

0

25

50

Figure 20 Test Setup 90

Vin = 1.5 V

80 70 60

Vin = 2.0 V

50 Vin = 5.0 V

40 Vin = 3.3 V 30 20 –50

100

75

–25

0

25

50

75



Figure 4. Output Resistance vs. Ambient Temperature MAX828

Figure 5. Output Resistance vs. Ambient Temperature MAX829

35

100


Figure 20 Test Setup

TA = 25°C

30



TA = 25°C

90

Vin = 4.75 V Vout = –4.0 V

25 20

Vin = 3.15 V Vout = –2.5 V

15 10

Vin = 1.9 V Vout = –1.5 V

5 0

TA = 25°C

30 Vin = 4.75 V Vout = –4.0 V

25 20

Vin = 3.15 V Vout = –2.5 V

15 10

Vin = 1.9 V Vout = –1.5 V

5 0

0

10

20

30

40

50

0

10

20

30

40

50



Figure 6. Output Current vs. Capacitance MAX828

Figure 7. Output Current vs. Capacitance MAX829



TA = 25°C

350 Vin = 4.75 V Vout = –4.0 V

300 250

Vin = 3.15 V Vout = –2.5 V

200 150

Vin = 1.9 V Vout = –1.5 V

100 50 0 0

20

10

40

30


TA = 25°C

300 Vin = 4.75 V Vout = –4.0 V

250 200

Vin = 3.15 V Vout = –2.5 V

150 100

Vin = 1.9 V Vout = –1.5 V

50 0 0

10

20

30

50

40


Figure 8. Output Voltage Ripple vs. Capacitance MAX828

Figure 9. Output Voltage Ripple vs. Capacitance MAX829 130

RL = ∞


70 TA = 85°C TA = 25°C

60 50

TA = –40°C

40

RL = ∞

Figure 20 Test Setup 120

80



50

350


90

30

110 TA = 85°C

100 90

TA = 25°C

80 70

TA = –40°C

60 50

20 1.5


Vout, OUTPUT VOLTAGE RIPPLE (mVpp)

400

2.0

2.5

3.0

3.5

4.0

4.5

40 1.5

5.0

2.0

2.5

3.0

3.5

4.0

4.5



Figure 10. Supply Current vs. Supply Voltage MAX828

Figure 11. Supply Current vs. Supply Voltage MAX829

13.0


Vout, OUTPUT VOLTAGE RIPPLE (mVpp)

MAX828, MAX829

Figure 20 Test Setup 12.5 Vin = 5.0 V 12.0 Vin = 3.3 V

11.5 11.0 Vin = 1.5 V 10.5 10.0 –50

–25

0

25

50

75

100

40 Figure 20 Test Setup 39 Vin = 3.3 V

38 37 Vin = 1.5 V

36 35

Vin = 5.0 V

34 33 32 –50

–25

0

25

50

75



Figure 12. Oscillator Frequency vs. Ambient Temperature MAX828

Figure 13. Oscillator Frequency vs. Ambient Temperature MAX829


5.0

100

MAX828, MAX829

0

0

Figure 20 Test Setup Vout, OUTPUT VOLTAGE (V)

–1.0

Vin = 2.0 V

–2.0 Vin = 3.3 V

–3.0 –4.0

Vin = 5.0 V

–5.0

10

20

30

40

–2.0 Vin = 3.3 V

–3.0 –4.0

Vin = 5.0 V

–5.0

10

20

30

40

50

Figure 14. Output Voltage vs. Output Current MAX828

Figure 15. Output Voltage vs. Output Current MAX829

90 Vin = 5.0 V

80 70

Vin = 3.3 V

Vin = 1.5 V Vin = 2.0 V

50

TA = 25°C

OUTPUT VOLTAGE RIPPLE & NOISE = 10 mV/Div. AC COUPLED

Vin = 2.0 V



40 0

TA = 25°C


100

60

–1.0

–6.0 0

50

10

20

30

40

50

η, POWER CONVERSION EFFICIENCY (%)

–6.0 0

η, POWER CONVERSION EFFICIENCY (%)

TA = 25°C

100 Figure 20 Test Setup 90 Vin = 5.0 V

80 70 60

Vin = 3.3 V

Vin = 1.5 V Vin = 2.0 V

50

TA = 25°C 40 0

10

20

30

40



Figure 16. Power Conversion Efficiency vs. Output Current MAX828

Figure 17. Power Conversion Efficiency vs. Output Current MAX829


Vin = 3.3 V Iout = 5.0 mA TA = 25°C

TIME = 25 µs/div

OUTPUT VOLTAGE RIPPLE & NOISE = 10 mV/Div. AC COUPLED



Figure 18. Output Voltage Ripple and Noise MAX828


Vin = 3.3 V Iout = 5.0 mA TA = 25°C

TIME = 10 µs/div

Figure 19. Output Voltage Ripple and Noise MAX829


50

MAX828, MAX829 Charge Pump Efficiency

–Vout

C + 2

6

1

The overall power efficiency of the charge pump is affected by four factors: 1. Losses from power consumed by the internal oscillator, switch drive, etc. (which vary with input voltage, temperature and oscillator frequency). 2. I2R losses due to the on–resistance of the MOSFET switches on–board the charge pump. 3. Charge pump capacitor losses due to Equivalent Series Resistance (ESR). 4. Losses that occur during charge transfer from the commutation capacitor to the output capacitor when a voltage difference between the two capacitors exists. Most of the conversion losses are due to factors 2, 3 and 4. These losses are given by Equation 1.

RL

OSC Vin

+

+

2

C1

C3 3

4

MAX828: C1 = C2 = C3 = 10 F MAX829: C1 = C2 = C3 = 3.3 F

Figure 20. Test Setup/Voltage Inverter

DETAILED OPERATING DESCRIPTION

ƪ

The MAX828/829 charge pump converters inverts the voltage applied to the Vin pin. Conversion consists of a two–phase operation (Figure 21). During the first phase, switches S2 and S4 are open and S1 and S3 are closed. During this time, C1 charges to the voltage on Vin and load current is supplied from C2. During the second phase, S2 and S4 are closed, and S1 and S3 are open. This action connects C1 across C2, restoring charge to C2. S1

P + I out 2 LOSS(2,3,4) 1

(f

OSC

)C1

) 8R

SWITCH

R out ^ I out 2 ) 4ESR

C1

) ESR

ƫ

C2

(eq. 1)

The 1/(fOSC)(C1) term in Equation 1 is the effective output resistance of an ideal switched capacitor circuit (Figures 22 and 23). The losses due to charge transfer above are also shown in Equation 2. The output voltage ripple is given by Equation 3.

S2

PLOSS + [ 0.5C1 (Vin 2 * Vout 2)

Vin

) 0.5C2 (VRIPPLE 2 * 2VoutVRIPPLE)]

C1

fOSC (eq. 2)

V

C2 S3

RIPPLE

+

I out (f

OSC

)(C 2)

) 2(I out)(ESR ) C2

(eq. 3)

S4 –Vout

f Vin

From Osc

Vout

C1

C2

RL

Figure 21. Ideal Switched Capacitor Charge Pump Figure 22. Ideal Switched Capacitor Model

APPLICATIONS INFORMATION Output Voltage Considerations

REQUIV

The MAX828/829 performs voltage conversion but does not provide regulation. The output voltage will drop in a linear manner with respect to load current. The value of this equivalent output resistance is approximately 26 Ω nominal at 25°C and Vin = 5.0 V. Vout is approximately –5.0 V at light loads, and drops according to the equation below: VDROP + Iout

Vin

Vout R

Rout

EQUIV

+

f

1 C1

C2

RL

Figure 23. Equivalent Output Resistance

Vout + * (Vin * VDROP)


MAX828, MAX829 Capacitor Selection

Voltage Inverter

In order to maintain the lowest output resistance and output ripple voltage, it is recommended that low ESR capacitors be used. Additionally, larger values of C1 will lower the output resistance and larger values of C2 will reduce output voltage ripple. (See Equation 3). Table 1 shows various values of C1, C2 and C3 with the corresponding output resistance values at 25°C. Table 2 shows the output voltage ripple for various values of C1, C2 and C3. The data in Tables 1 and 2 was measured not calculated.

The most common application for a charge pump is the voltage inverter (Figure 20). This application uses two or three external capacitors. The capacitors C1 (pump capacitor) and C2 (output capacitor) are required. The input bypass capacitor C3, may be necessary depending on the application. The output is equal to –Vin plus any voltage drops due to loading. Refer to Tables 1 and 2 for capacitor selection. The test setup used for the majority of the characterization is shown in Figure 20.

Table 1. Output Resistance vs. Capacitance (C1 = C2 = C3), Vin = 4.75 V and Vout = –4.0 V

As with any switching power supply circuit, good layout practice is recommended. Mount components as close together as possible to minimize stray inductance and capacitance. Also use a large ground plane to minimize noise leakage into other circuitry.

C1 = C2 = C3 (mF)

MAX828 Rout (W)

MAX829 Rout (W)

0.7

127.2

55.7

1.4

67.7

36.8

3.3

36

26.0

7.3

26.7

24.9

10

25.9

25.1

24

24.3

25.2

50

24

24

Layout Considerations

Capacitor Resources

Selecting the proper type of capacitor can reduce switching loss. Low ESR capacitors are recommended. The MAX828 and MAX829 were characterized using the capacitors listed in Table 3. This list identifies low ESR capacitors for the voltage inverter application. Table 3. Capacitor Types Manufacturer/Contact

Table 2. Output Voltage Ripple vs. Capacitance (C1 = C2 = C3), Vin = 4.75 V and Vout = –4.0 V C1 = C2 = C3 (mF)

MAX828 Ripple (mV)

MAX829 Ripple (mV)

0.7

377.5

320

1.4

360.5

234

3.3

262

121

7.3

155

62.1

10

126

51.25

24

55.1

25.2

50

36.6

27.85

AVX 843–448–9411 www.avxcorp.com Cornell Dubilier 508–996–8561 ll d bili www.cornell–dubilier.com

TPS

ESRD

Sanyo/Os con Sanyo/Os–con 619–661–6835 id / ht www.sanyovideo.com/oscon.htm

SN SVP

Vishay 603–224–1961 i h www.vishay.com

593D 594

Input Supply Bypassing

The input voltage, Vin should be capacitively bypassed to reduce AC impedance and minimize noise effects due to the switching internals in the device. If the device is loaded from Vout to GND, it is recommended that a large value capacitor (at least equal to C1) be connected from Vin to GND. If the device is loaded from Vin to Vout a small (0.7 µF) capacitor between the pins is sufficient.


Part Types/Series

MAX828, MAX829

–Vout

5

1 OSC

+ Vin

+

2

+

3

4

MAX828: Capacitors = 10 µF MAX829: Capacitors = 3.3 µF

Figure 24. Voltage Inverter

The MAX828 / 829 primary function is a voltage inverter. The device will convert 5.0 V into –5.0 V with light loads. Two capacitors are required for the inverter to function. A third capacitor, the input bypass capacitor, may be required depending on the power source for the inverter. The performance for this device is illustrated below. 0.0

0.0

TA = 25°C Vout, OUTPUT VOLTAGE (V)


TA = 25°C –1.0 –2.0 Vin = 3.3 V –3.0 Vin = 5.0 V

–4.0 –5.0

–1.0 –2.0 Vin = 3.3 V –3.0 Vin = 5.0 V

–4.0 –5.0 –6.0

–6.0 0

10

20

30

40

50

0

10

20

30

40



Figure 25. Voltage Inverter Load Regulation Output Voltage vs. Output Current MAX828

Figure 26. Voltage Inverter Load Regulation Output Voltage vs. Output Current MAX829


50

MAX828, MAX829 –Vout

5

1 + Vin

OSC

+

2

+

5

1

OSC

2

3

4

3

4 +

+ MAX828 Capacitors = 10 µF MAX829 Capacitors = 3.3 µF

Figure 27. Cascade Devices for Increased Negative Output Voltage

–1.0

–1.0

–2.0

–2.0

–3.0



Two or more devices can be cascaded for increased output voltage. Under light load conditions, the output voltage is approximately equal to –Vin times the number of stages. The converter output resistance increases dramatically with each additional stage. This is due to a reduction of input voltage to each successive stage as the converter output is loaded. Note that the ground connection for each successive stage must connect to the negative output of the previous stage. The performance characteristics for a converter consisting of two cascaded devices are shown below.

A

–4.0 –5.0 B

–6.0 –7.0 –8.0 –9.0

–3.0

C

–4.0 –5.0 –6.0

D

–7.0 –8.0 –9.0

–10.0

–10.0 0

10

20

30

40

0

10

20

30



Figure 28. Cascade Load Regulation, Output Voltage vs. Output Current MAX828

Figure 29. Cascade Load Regulation, Output Voltage vs. Output Current MAX829

Curve

Vin (V)

Rout (W)

A

3.0

173

B

5.0

141

C

3.0

179

D

5.0

147


40

MAX828, MAX829

5

1 OSC Vin

2

+

–Vout

+ +

3

+

+

4 MAX828: Capacitors = 10 µF MAX829: Capacitors = 3.3 µF

Figure 30. Negative Output Voltage Doubler

A single device can be used to construct a negative voltage doubler. The output voltage is approximately equal to –2Vin minus the forward voltage drop of each external diode. The performance characteristics for the above converter are shown below. Note that curves A and C show the circuit performance with economical 1N4148 diodes, while curves B and D are with lower loss MBRA120E Schottky diodes. –2.0 Vout, OUTPUT VOLTAGE (V)


0.0

–2.0 A –4.0 C

B –6.0

D –8.0 TA = 25°C

–10.0 0

10

20

30

A –4.0 B –6.0

C

–8.0 D TA = 25°C

–10.0 40

0

10

20

30



Figure 31. Doubler Load Regulation, Output Voltage vs. Output Current MAX828


Curve

Vin (V)

Diodes

MAX828 Rout (W)

MAX829 Rout (W)

A

3.0

1N4148

122

118

B

3.0

MBRA120E

114

106

C

5.0

1N4148

96

90

D

5.0

MBRA120E

91

87


40

MAX828, MAX829

5

1 OSC Vin

+

–Vout

+

2

+

3

+

+

+

+


Figure 33. Negative Output Voltage Tripler

A single device can be used to construct a negative voltage tripler. The output voltage is approximately equal to –3Vin minus the forward voltage drop of each external diode. The performance characteristics for the above converter are shown below. Note that curves A and C show the circuit performance with economical 1N4148 diodes, while curves B and D are with lower loss MBRA120E Schottky diodes. 0.0

–2.0



0.0

A –4.0 C

–6.0

B

–8.0 D

–2.0 A –4.0 –6.0 B –8.0

C

–10.0

–10.0

D

–12.0

–12.0 TA = 25°C

TA = 25°C –14.0

–14.0 0

10

20

30

40

0

10

20

30



Figure 34. Tripler Load Regulation, Output Voltage vs. Output Current MAX828


Curve

Vin (V)

Diodes

MAX828 Rout (W)

MAX829 Rout (W)

A

3.0

1N4148

259

246

B

3.0

MBRA120E

251

237

C

5.0

1N4148

209

198

D

5.0

MBRA120E

192

185


40

MAX828, MAX829

5

1 OSC

+ Vin

2

+

+

3

Vout

4


Figure 36. Positive Output Voltage Doubler

A single device can be used to construct a positive voltage doubler. The output voltage is approximately equal to 2Vin minus the forward voltage drop of each external diode. The performance characteristics for the above converter are shown below. Note that curves A and C show the circuit performance with economical 1N4148 diodes, while curves B and D are with lower loss MBRA120E Schottky diodes. 10.0

10.0

D Vout, OUTPUT VOLTAGE (V)


D 8.0 C 6.0 B

4.0 A

8.0 C 6.0 B 4.0 A

TA = 25°C

TA = 25°C 2.0

2.0 0

10

20

30

40

0

10

20

30





Curve

Vin (V)

Diodes

MAX828 Rout (W)

MAX829 Rout (W)

A

3.0

1N4148

32.5

32.2

B

3.0

MBRA120E

27.1

25.7

C

5.0

1N4148

26.0

25.1

D

5.0

MBRA120E

21.2

19.0


40

MAX828, MAX829

5

1 OSC

+ Vin

+

2

+

+

3

Vout

+


Figure 39. Positive Output Voltage Tripler

A single device can be used to construct a positive voltage tripler. The output voltage is approximately equal to 3Vin minus the forward voltage drop of each external diode. The performance characteristics for the above converter are shown below. Note that curves A and C show the circuit performance with economical 1N4148 diodes, while curves B and D are with lower loss MBRA120E Schottky diodes. 14.0

14.0

D Vout, OUTPUT VOLTAGE (V)


D 12.0 10.0 C 8.0 B 6.0 4.0

12.0 10.0 C 8.0 B 6.0 4.0

A

TA = 25°C

A

TA = 25°C 2.0

2.0 0

10

20

30

40

0

10

20

30





Curve

Vin (V)

Diodes

MAX828 Rout (W)

MAX829 Rout (W)

A

3.0

1N4148

110

111

B

3.0

MBRA120E

96.5

96.7

C

5.0

1N4148

84.5

87.3

D

5.0

MBRA120E

78.2

77.1


40

MAX828, MAX829 –Vout + 5

1

5

1

OSC Vin

OSC

2

+

2

3

4

3

4

+

+ MAX828 Capacitors = 10 µF MAX829 Capacitors = 3.3 µF

Figure 42. Paralleling Devices for Increased Negative Output Current

An increase in converter output current capability with a reduction in output resistance can be obtained by paralleling two or more devices. The output current capability is approximately equal to the number of devices paralleled. A single shared output capacitor is sufficient for proper operation but each device does require it’s own pump capacitor. Note that the output ripple frequency will be complex since the oscillators are not synchronized. The output resistance is approximately equal to the output resistance of one device divided by the total number of devices paralleled. The performance characteristics for a converter consisting of two paralleled devices is shown below. –1.0

–1.0 TA = 25°C Vout, OUTPUT VOLTAGE (V)


TA = 25°C B

–2.0

–3.0

A

–4.0

–5.0

–2.0

D

–3.0

C

–4.0

–5.0 0

20

40

60

80

100

0

20

40

60

80



Figure 43. Parallel Load Regulation, Output Voltage vs. Output Current MAX828

Figure 44. Parallel Load Regulation, Output Voltage vs. Output Current MAX829

Curve

Vin (V)

Rout (Ω)

A

5.0

13.3

B

3.0

17.3

C

5.0

14.4

D

3.0

17.3


100

MAX828, MAX829

Q2 5

1

–Vout

+

OSC Vin

C1

Q1

C2

+

2

+ C3

3


4

–Vout = Vin –VBE(Q1) – VBE(Q2) –2 VF

Figure 45. External Switch for Increased Negative Output Current

The output current capability of the MAX828 and MAX829 can be extended beyond 600 mA with the addition of two external switch transistors and two Schottky diodes. The output voltage is approximately equal to –Vin minus the sum of the base emitter drops of both transistors and the forward voltage of both diodes. The performance characteristics for the converter are shown below. Note that the output resistance is reduced to 0.9 and 1.0 ohms for the 828 and 829 respectively. –2.0 Vout, OUTPUT VOLTAGE (V)


–2.2

–2.4

–2.6

–2.8 Vin = 5.0 V Rout = 0.9 Ω TA = 25°C

–3.0

–3.2

0

0.1

0.2

0.3

0.4

0.5

0.6

–2.2 –2.4 –2.6 –2.8 Vin = 5.0 V Rout = 1.0 Ω TA = 25°C

–3.0 –3.2

0

0.1

0.2

0.3

0.4

0.5



Figure 46. Current Boosted Load Regulation, Output Voltage vs. Output Current MAX828

Figure 47. Current Boosted Load Regulation, Output Voltage vs. Output Current MAX829


0.6

MAX828, MAX829 50 Q2

C1 Vout

5

1

+

50

OSC

+

Q1 Vin

C2

2

+ C3

3

Capacitors = 220 µF Q1 = PZT751 Q2 = PZT651

4

Figure 48. Positive Output Voltage Doubler with High Current Capability

The MAX828 / 829 can be configured to produce a positive output voltage doubler with current capability in excess of 500 mA. This is accomplished with the addition of two external switch transistors and two Schottky diodes. The output voltage is approximately equal to 2Vin minus the sum of the base emitter drops of both transistors and the forward voltage of both diodes. The performance characteristics for the converter are shown below. Note that the output resistance is reduced to 1.8 ohms. 9.0 Vin = 5.0 V Rout = 1.8 Ω TA = 25°C

8.4



8.8

8.0

7.6

7.2

6.8

0

0.1

0.2

0.3

0.4

0.5

0.6

Vin = 5.0 V Rout = 1.8 Ω TA = 25°C

8.6

8.2

7.8

7.4

7.0

0

0.1

0.2

0.3

0.4

0.5



Figure 49. Positive Doubler with Current Boosted Load Regulation, Output Voltage vs. Output Current, MAX828

Figure 50. Positive Doubler with Current Boosted Load Regulation, Output Voltage vs. Output Current, MAX829


0.6

MAX828, MAX829 –Vout

5

1

+

OSC Vin


2

+

+ +

3

4

+

+Vout

Figure 51. A Positive Doubler, with a Negative Inverter

All of the previously shown converter circuits have only single outputs. Applications requiring multiple outputs can be constructed by incorporating combinations of the former circuits. The converter shown above combines Figures 24 and 36 to form a negative output inverter with a positive output doubler. Different combinations of load regulation are shown below. In Figures 52 and 53 the positive doubler has a constant Iout = 15 mA while the negative inverter has the variable load. In Figures 54 and 55 the negative inverter has the constant Iout = 15 mA and the positive doubler has the variable load. 9.5 Positive Doubler Iout = 15 mA

9.0



9.5

8.5

–4.0 Negative Inverter –4.5

–5.0

Negative Inverter Rout = 28.8 Ω TA = 25°C 0

10

20

8.5

–4.0 Negative Inverter –4.5

Negative Inverter Rout = 28 Ω TA = 25°C 0

10

20



Figure 52. Negative Inverter Load Regulation, Output Voltage vs. Output Current, MAX828

Figure 53. Negative Inverter Load Regulation, Output Voltage vs. Output Current, MAX829

30

9.5

9.5 Positive Doubler Rout = 21.4 Ω

9.0



9.0

–5.0

30

Positive Doubler Iout = 15 mA

8.5

–4.0 Negative Inverter –4.5 Negative Inverter Iout = 15 mA TA = 25°C

9.0

8.5

–4.0 Negative Inverter –4.5 Negative Inverter Iout = 15 mA TA = 25°C –5.0

–5.0 0

Positive Doubler Rout = 20 Ω

10 20 30 Iout, POSITIVE DOUBLER OUTPUT CURRENT (mA)

0

10 20 30 Iout, POSITIVE DOUBLER OUTPUT CURRENT (mA)

Figure 55. Positive Doubler Load Regulation, Output Voltage vs. Output Current, MAX829

Figure 54. Positive Doubler Load Regulation, Output Voltage vs. Output Current, MAX828 http://onsemi.com 1989

MAX828, MAX829

IC1

+

C1

C2

Vin

–Vout

GND

+

C3

GND

+

0.5 ″ Inverter Size = 0.5 in x 0.2 in Area = 0.10 in2, 64.5 mm2

Figure 56. Inverter Circuit Board Layout, Top View Copper Side

TAPING FORM Component Taping Orientation for Thin SOT–23–5 Devices


PIN 1

Standard Reel Component Orientation (Mark Right Side Up)


Tape Width (W)

Pitch (P)

Part Per Full Reel

Diameter

Thin SOT–23–5

8 mm

4 mm

3000

7 inches


89 -" &# ! The CS5150H is a 4–bit synchronous dual N–Channel buck controller. It is designed to provide unprecedented transient response for today’s demanding high–density, high–speed logic. The regulator operates using a proprietary control method, which allows a 100 ns response time to load transients. The CS5150H is designed to operate over a 4.25–20 V range (VCC) using 12 V to power the IC and 5.0 V or 12 V as the main supply for conversion. The CS5150H is specifically designed to power Pentium Pro processors and other high performance core logic. It includes the following features: on board, 4–bit DAC, short circuit protection, 1.0% output tolerance, VCC monitor, and programmable Soft Start capability. The CS5150H is upward compatible with the 5–bit CS5155H, allowing the mother board designer the capability of using either the CS5150H or the CS5155H with no change in layout. The CS5150H is available in 16 pin surface mount. Features Dual N–Channel Design Excess of 1.0 MHz Operation 100 ns Transient Response 4–Bit DAC Upward Compatible with 5–Bit CS5155H/CS5156H 30 ns Gate Rise/Fall Times 1.0% DAC Accuracy 5.0 V & 12 V Operation Remote Sense Programmable Soft Start Lossless Short Circuit Protection VCC Monitor 25 ns FET Nonoverlap Time Adaptive Voltage Positioning V2 Control Topology Current Sharing Overvoltage Protection

• • • • • • • • • • • • • • • • •



http://onsemi.com MARKING DIAGRAM 16

16 SOIC–16 D SUFFIX CASE 751B

1

CS5150H AWLYWW 1

A WL, L YY, Y WW, W


PIN CONNECTIONS 1

16

VID0 VID1 VID2 VID3 SS NC COFF VFFB

VFB COMP LGND VCC1 VGATE(L) PGND VGATE(H) VCC2


1991

Package

Shipping

CS5150HGD16

SO–16

48 Units/Rail

CS5150HGDR16

SO–16

2500 Tape & Reel

Publication Order Number: CS5150H/D

CS5150H 5.0 V

12 V

0.1 µF VCC1

VCC2

1200 µF/16 V × 6 AIEI

IRL3103 VGATE(H)

VID0

VID0

VID1

VID1

VID2

VID2

VID3

VID3 COFF

2.0 µH

2.1 V to 3.5 V @ 13 A

IRL3103 VGATE(L)

CS5150H

330 pF

PGND SS

0.1 µF

COMP

VFB 3.3 k

0.33 µF

LGND

VFFB

1200 µF/16 V × 5 AIEI

100 pF

Figure 1. Application Diagram, Switching Power Supply for Core Logic – Pentium) Pro Processor


Value

Unit

0 to 150

°C

230 peak

°C

–65 to +150

°C

2.0

kV



Storage Temperature Range, TS ESD Susceptibility (Human Body Model) 1. 60 second maximum above 183°C. *The maximum package power dissipation must be observed.


Max Operating Voltage

Max Current

VCC1

16 V/–0.3 V

25 mA DC/1.5 A peak

VCC2

20 V/–0.3 V

20 mA DC/1.5 A peak

SS

6.0 V/–0.3 V

–100 µA

COMP

6.0 V/–0.3 V

200 µA

VFB

6.0 V/–0.3 V

–0.2 µA

COFF

6.0 V/–0.3 V

–0.2 µA

VFFB

6.0 V/–0.3 V

–0.2 µA

VID0 – VID3

6.0 V/–0.3 V

–50 µA

VGATE(H)

20 V/–0.3 V

100 mA DC/1.5 A peak

VGATE(L)

16 V/–0.3 V


LGND

0V

25 mA

PGND

0V



CS5150H ELECTRICAL CHARACTERISTICS (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 20 V; DAC Code: VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit


VFB = 0 V

–

0.3

1.0

µA

Open Loop Gain

1.25 V < VCOMP < 4.0 V; Note 2

50

60

–

dB


Note 2

500

3000

–

kHz

COMP SINK Current

VCOMP = 1.5 V; VFB = 3.0 V; VSS > 2.0 V

0.4

2.5

8.0

mA

COMP SOURCE Current

VCOMP = 1.2 V; VFB = 2.7 V; VSS = 5.0 V

30

50

80

µA

COMP CLAMP Current

VCOMP = 0 V; VFB = 2.7 V

0.4

1.0

1.6

mA

COMP High Voltage

VFB = 2.7 V; VSS = 5.0 V

4.0

4.3

5.0

V

COMP Low Voltage

VFB = 3.0 V

–

160

600

mV

PSRR

8.0 V < VCC1 < 14 V @ 1.0 kHz; Note 2

60

85

–

dB

VCC1 Monitor Start Threshold

Output switching

3.75

3.90

4.05

V

Stop Threshold

Output not switching

3.70

3.85

4.00

V

Hysteresis

Start–Stop

–

50

–

mV

DAC Input Threshold

VID0, VID1, VID2, VID3

1.00

1.25

2.40

V

Input Pull Up Resistance


25

50

110

kΩ

4.85

5.00

5.15

V

–

–

1.0

%

Pull Up Voltage

–

Accuracy (all codes except 11111)

Measure VFB = COMP, 25°C ≤ TJ ≤ 125°C

VID3

VID2

VID1

VID0

1

1

1

1

–

1.2191

1.2440

1.2689

V

1

1

1

0

–

2.1186

2.1400

2.1614

V

1

1

0

1

–

2.2176

2.2400

2.2624

V

1

1

0

0

–

2.3166

2.3400

2.3634

V

1

0

1

1

–

2.4156

2.4400

2.4644

V

1

0

1

0

–

2.5146

2.5400

2.5654

V

1

0

0

1

–

2.6136

2.6400

2.6664

V

1

0

0

0

–

2.7126

2.7400

2.7674

V

0

1

1

1

–

2.8116

2.8400

2.8684

V

0

1

1

0

–

2.9106

2.9400

2.9694

V

0

1

0

1

–

3.0096

3.0400

3.0704

V

0

1

0

0

–

3.1086

3.1400

3.1714

V

0

0

1

1

–

3.2076

3.2400

3.2724

V

0

0

1

0

–

3.3066

3.3400

3.3734

V

0

0

0

1

–

3.4056

3.4400

3.4744

V

0

0

0

0

–

3.5046

3.5400

3.5754

V



CS5150H ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 20 V; DAC Code: VID2 = VID1 = VID0 =1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit

VGATE(H) and VGATE(L) Out SOURCE Sat at 100 mA

Measure VCC1 – VGATE(L); VCC2 – VGATE(H)

–

1.2

2.0

V

Out SINK Sat at 100 mA

Measure VGATE(H) – VPGND; VGATE(L) – VPGND

–

1.0

1.5

V

Out Rise Time

1.0 V < VGATE(H) < 9.0 V; 1.0 V < VGATE(L) < 9.0 V; VCC1 = VCC2 = 12 V

–

30

50

ns

Out Fall Time

9.0 V > VGATE(H) > 1.0 V; 9.0 V > VGATE(L) > 1.0 V; VCC1 = VCC2 = 12 V

–

30

50

ns

Shoot–Through Current

Note 3

–

–

50

mA

Delay VGATE(H) to VGATE(L)

VGATE(H) falling to 2.0 V; VCC1 = VCC2 = 8.0 V VGATE(L) rising to 2.0 V

–

25

50

ns

Delay VGATE(L) to VGATE(H)

VGATE(L) falling to 2.0 V; VCC1 = VCC2 = 8.0 V VGATE(H) rising to 2.0 V

–

25

50

ns

VGATE(H), VGATE(L) Resistance

Resistor to LGND. Note 3

20

50

100

kΩ

VGATE(H), VGATE(L) Schottky

LGND to VGATE(H) @ 10 mA; LGND to VGATE(L) @ 10 mA

–

600

800

mV

Soft Start (SS) Charge Time

–

1.6

3.3

5.0

ms

Pulse Period

–

25

100

200

ms

Duty Cycle

(Charge Time /Pulse Period) × 100

1.0

3.3

6.0

%

COMP Clamp Voltage

VFB = 0 V; VSS = 0

0.50

0.95

1.10

V

VFFB SS Fault Disable

VGATE(H) = Low; VGATE(L) = Low

0.9

1.0

1.1

V

–

–

2.5

3.0

V

Transient Response

VFFB = 0 to 5.0 V to VGATE(H) = 9.0 V to 1.0 V; VCC1 = VCC2 = 12 V

–

100

125

ns

VFFB Bias Current

VFFB = 0 V

–

0.3

–

µA

ICC1

No Switching

–

8.5

13.5

mA

ICC2

No Switching

–

1.6

3.0

mA

Operating ICC1

VFB = COMP = VFFB

–

8.0

13

mA

Operating ICC2

VFB = COMP = VFFB

–

2.0

5.0

mA

High Threshold PWM Comparator

Supply Current

COFF Normal Charge Time

VFFB = 1.5 V; VSS = 5.0 V

1.0

1.6

2.2

µs

Extension Charge Time

VSS = VFFB = 0

5.0

8.0

11.0

µs

Discharge Current

COFF to 5.0 V; VFB > 1.0 V

5.0

–

–

mA

Time Out Time

VFB = VCOMP; VFFB = 2.0 V; Record VGATE(H) Pulse High Duration

10

30

65

µs

Fault Mode Duty Cycle

VFFB = 0V

35

50

70

%

Time Out Timer



CS5150H PACKAGE PIN DESCRIPTION PACKAGE PIN # 16 Lead SO Narrow

PIN SYMBOL

FUNCTION

1, 2, 3, 4

VID0–VID3

Voltage ID DAC input pins. These pins are internally pulled up to 5.0 V providing logic ones if left open. The DAC range is 2.14 V to 3.54 V with 100 mV increments. VID0 – VID3 select the desired DAC output voltage. Leaving all 4 DAC input pins open results in a DAC output voltage of 1.244 V, allowing for adjustable output voltage, using a traditional resistor divider.

5

SS

Soft Start Pin. A capacitor from this pin to LGND in conjunction with internal 60 µA current source provides Soft Start function for the controller. This pin disables fault detect function during Soft Start. When a fault is detected, the Soft Start capacitor is slowly discharged by internal 2.0 µA current source setting the time out before trying to restart the IC. Charge/discharge current ratio of 30 sets the duty cycle for the IC when the regulator output is shorted.

6

NC

No Connection.

7

COFF

A capacitor from this pin to ground sets the time duration for the on board one shot, which is used for the constant off time architecture.

8

VFFB

Fast feedback connection to the PWM comparator. This pin is connected to the regulator output. The inner feedback loop terminates on time.

9

VCC2

Boosted power for the high side gate driver.

10

VGATE(H)

High FET driver pin capable of 1.5 A peak switching current. Internal circuit prevents VGATE(H) and VGATE(L) from being in high state simultaneously.

11

PGND

High current ground for the IC. The MOSFET drivers are referenced to this pin. Input capacitor ground and the source of lower FET should be tied to this pin.

12

VGATE(L)

Low FET driver pin capable of 1.5 A peak switching current.

13

VCC1

Input power for the IC and low side gate driver.

14

LGND

Signal ground for the IC. All control circuits are referenced to this pin.

15

COMP

Error amplifier compensation pin. A capacitor to ground should be provided externally to compensate the amplifier.

16

VFB

Error amplifier DC feedback input. This is the master voltage feedback which sets the output voltage. This pin can be connected directly to the output or a remote sense trace.


CS5150H VCC2 VCC1

–

VCC1 Monitor Comparator 5.0 V

+

–

3.90 V 3.85V

VGATE(H)

SS Low Comparator R

60 µA

SS +

2.0 µA

Q S FAULT Latch

VID2

SS High Comparator

FAULT

PGND

VCC1

–

VID0 VID1

Q

+ 0.7 V

FAULT

4 BIT DAC

Error Amplifier

VGATE(L)

2.5 V

+ –

PGND

PWM Comparator

VID3

– VFB

Maximum On–Time Timeout

+

Slow Feedback

Normal Off–Time Timeout Extended Off–Time Timeout

COMP

VFFB

Fast Feedback

– +

LGND

1.0 V

R

Q

S

Q PMW Latch

GATE(H) = ON GATE(H) = OFF COFF One Shot R

Off–Time Timeout

COFF Q

S

VFFB Low Comparator

Time–Out Timer (30 µs)

PWM COMP

Edge Triggered


APPLICATIONS INFORMATION THEORY OF OPERATION

PWM Comparator + VGATE(H) C VGATE(L)

V2 Control Method

The V2 method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the value of the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current.

–

Ramp Signal

VFFB

VFB

Error Amplifier COMP

Error Signal


–

E +

Figure 3. V2 Control Diagram


Reference Voltage

CS5150H The V2 control method is illustrated in Figure 3. The output voltage is used to generate both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. A change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the V2 control scheme to compensate the duty cycle. Since the change in inductor current modifies the ramp signal, as in current mode control, the V2 control scheme has the same advantages in line transient response. A change in load current will have an affect on the output voltage, altering the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. Load transient response is determined only by the comparator response time and the transition speed of the main switch. The reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. The error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. The main purpose of this ‘slow’ feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. Line and load regulation are drastically improved because there are two independent voltage loops. A voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. The V2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load.

Constant off time provides a number of advantages. Switch duty cycle can be adjusted from 0 to 100% on a pulse by pulse basis when responding to transient conditions. Both 0% and 100% duty cycle operation can be maintained for extended periods of time in response to load or line transients. PWM slope compensation to avoid sub–harmonic oscillations at high duty cycles is avoided. Switch on time is limited by an internal 30 µs timer, minimizing stress to the power components. Programmable Output

The CS5150H is designed to provide two methods for programming the output voltage of the power supply. A four bit on board digital to analog converter (DAC) is used to program the output voltage from 2.14 V to 3.54 V in 100 mV steps, depending on the digital input code. If all four bits are left open, the CS5150H enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feedback to the VFB and VFFB pins, as in traditional controllers. The CS5150H is specifically designed to be upwards compatible with the CS5155H, which uses a five bit DAC code. Start Up

Until the voltage on the VCC1 supply pin exceeds the 3.9 V monitor threshold, the Soft Start and gate pins are held low. The FAULT latch is reset (no Fault condition). The output of the error amplifier (COMP) is pulled up to 1.0 V by the comparator clamp. When the VCC1 pin exceeds the monitor threshold, the GATE(H) output is activated, and the Soft Start capacitor begins charging. The GATE(H) output will remain on, enabling the NFET switch, until terminated by either the PWM comparator, or the maximum on time timer. If the maximum on time is exceeded before the regulator output voltage achieves the 1.0 V level, the pulse is terminated. The GATE(H) pin drives low, and the GATE(L) pin drives high for the duration of the extended off time. This time is set by the time out timer and is approximately equal to the maximum on time, resulting in a 50% duty cycle. The GATE(L) pin will then drive low, the GATE(H) pin will drive high, and the cycle repeats. When regulator output voltage achieves the 1.0 V level present at the COMP pin, regulation has been achieved and normal off time will ensue. The PWM comparator terminates the switch on time, with off time set by the COFF capacitor. The V2 control loop will adjust switch duty cycle as required to ensure the regulator output voltage tracks the output of the error amplifier. The Soft Start and COMP capacitors will charge to their final levels, providing a controlled turn on of the regulator output. Regulator turn on time is determined by the COMP

Constant Off Time

To maximize transient response, the CS5150H uses a constant off time method to control the rate of output pulses. During normal operation, the off time of the high side switch is terminated after a fixed period, set by the COFF capacitor. To maintain regulation, the V2 control loop varies switch on time. The PWM comparator monitors the output voltage ramp, and terminates the switch on time.


CS5150H capacitor charging to its final value. Its voltage is limited by the Soft Start COMP clamp and the voltage on the Soft Start pin (see Figures 4 and 5).

M 10.0 µs Trace 1– Regulator Output Voltage (5.0 V/div.) Trace 2– Inductor Switching Node (5.0 V/div.)

M 250 µs

Figure 6. CS5150H Demonstration Board Enable Startup Waveforms

Trace 1– Regulator Output Voltage (1.0 V/div.) Trace 2– Inductor Switching Node (2.0 V/div.) Trace 3– 12 V Input (VCC1 and VCC2) (5.0 V/div.) Trace 4– 5.0 V Input (1.0 V/div.)

Normal Operation

Figure 4. CS5150H Demonstration Board Startup in Response to Increasing 12 V and 5.0 V Input Voltages. Extended Off Time is Followed by Normal Off Time Operation when Output Voltage Achieves Regulation to the Error Amplifier Output.

During normal operation, switch off time is constant and set by the COFF capacitor. Switch on time is adjusted by the V2 control loop to maintain regulation. This results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. Output voltage ripple will be determined by inductor ripple current working into the ESR of the output capacitors (see Figures 7 and 8).

M 2.50 ms Trace 1– Regulator Output Voltage (1.0 V/div.) Trace 3– COMP PIn (error amplifier output) (1.0 V/div.) Trace 4– Soft Start Pin (2.0 V/div.)

M 1.00 µs

Figure 5. CS5150H Demonstration Board Startup Waveforms

Trace 1– Regulator Output Voltage (10 mV/div.)

If the input voltage rises quickly, or the regulator output is enabled externally, output voltage will increase to the level set by the error amplifier output more rapidly, usually within a couple of cycles (see Figure 6).

Trace 2– Inductor Switching Node (5.0 V/div.)

Figure 7. Peak–to–Peak Ripple on VOUT = 2.8 V, IOUT = 0.5 A (Light Load)


CS5150H level, the output capacitor is pre–positioned –40 mV (see Figures 9, 10, and 11). For best transient response, a combination of a number of high frequency and bulk output capacitors are usually used. If the maximum on time is exceeded while responding to a sudden increase in load current, a normal off time occurs to prevent saturation of the output inductor.

M 1.00 µs Trace 1– Regulator Output Voltage (10 mV/div.) Trace 2– Inductor Switching Node (5.0 V/div.)

Figure 8. Peak–to–Peak Ripple on VOUT = 2.8 V, IOUT = 13 A (Heavy Load) Transient Response

The CS5150H V2 control loop’s 100 ns reaction time provides unprecedented transient response to changes in input voltage or output current. Pulse by pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. Overall load transient response is further improved through a feature called “adaptive voltage positioning”. This technique pre–positions the output capacitor’s voltage to reduce total output voltage excursions during changes in load. Holding tolerance to 1.0% allows the error amplifier’s reference voltage to be targeted +40 mV high without compromising DC accuracy. A “droop resistor”, implemented through a PC board trace, connects the error amplifier’s feedback pin (VFB) to the output capacitors and load and carries the output current. With no load, there is no DC drop across this resistor, producing an output voltage tracking the error amplifier’s, including the +40 mV offset. When the full load current is delivered, an 80 mV drop is developed across this resistor. This results in output voltage being offset –40 mV low. The result of adaptive voltage positioning is that additional margin is provided for a load transient before reaching the output voltage specification limits. When load current suddenly increases from its minimum level, the output capacitor is pre–positioned +40 mV. Conversely, when load current suddenly decreases from its maximum

Trace 1– Regulator Output Voltage (1.0 V/div.) Trace 2– Regulator Output Voltage (20 V/div.)

Figure 9. CS5150H Demonstration Board Response to a 0.5 to 13 A Load Pulse (Output Set for 2.8 V)

Trace 1– Regulator Output Voltage (1.0 V/div.) Trace 2– Inductor Switching Node (5.0 V/div.) Trace 3– Output Current (0.5 to 13 Amps) (20 V/div.)

Figure 10. CS5150H Demonstration Board Response to 13 A Load Turn On (Output Set for 2.8 V). Upon Completing a Normal Off Time, The V2 Control Loop Immediately Connects the Inductor to the Input Voltage, Providing 100% Duty Cycle. Regulation is Achieved in Less Than 20 ms


CS5150H traces than occurs with constant NO TAGcurrent limit protection (see Figures 12 and 13). If the short circuit condition is removed, output voltage will rise above the 1.0 V level, preventing the FAULT latch from being set, allowing normal operation to resume.

Trace 1– Regulator Output Voltage (1.0 V/div.) Trace 2– Inductor Switching Node (5.0 V/div.) Trace 3– Output Current (13 to 0,5 Amps) (20 mV/div.)

Figure 11. CS5150H Demonstration Board Response to 13 A Load Turn Off (Output Set for 2.8 V). V2 Control Topology Immediately Connects Inductor to Ground, Providing 0% Duty Cycle. Regulation is Achieved in Less Than 10 ms

M 25.0 ms Trace 4– 5.0 V Supply Voltage (2.0 V/div.) Trace 3– Soft Start Timing Capacitor (1.0 V/div.) Trace 2– Inductor Switching Node (2.0 V/div.)

Figure 12. CS5150H Demonstration Board Hiccup Mode Short Circuit Protection. Gate Pulses are Delivered While the Soft Start Capacitor Charges, and Cease During Discharge

PROTECTION AND MONITORING FEATURES VCC1 Monitor

To maintain predictable startup and shutdown characteristics an internal VCC1 monitor circuit is used to prevent the part from operating below 3.75 V minimum startup. The VCC1 monitor comparator provides hysteresis and guarantees a 3.70 V minimum shutdown threshold. Short Circuit Protection

A lossless hiccup mode short circuit protection feature is provided, requiring only the Soft Start capacitor to implement. If a short circuit condition occurs (VFFB < 1.0 V), the VFFB low comparator sets the FAULT latch. This causes the top MOSFET to shut off, disconnecting the regulator from it’s input voltage. The Soft Start capacitor is then slowly discharged by a 2.0 µA current source until it reaches it’s lower 0.7 V threshold. The regulator will then attempt to restart normally, operating in it’s extended off time mode with a 50% duty cycle, while the Soft Start capacitor is charged with a 60 µA charge current. If the short circuit condition persists, the regulator output will not achieve the 1.0 V low VFFB comparator threshold before the Soft Start capacitor is charged to it’s upper 2.5 V threshold. If this happens the cycle will repeat itself until the short is removed. The Soft Start charge/discharge current ratio sets the duty cycle for the pulses (2.0 µA/60 µA = 3.3%), while actual duty cycle is half that due to the extended off time mode (1.65%). This protection feature results in less stress to the regulator components, input power supply, and PC board

M 50.0 µs Trace 4– 5.0 V from PC Power Supply (2.0 V/div.) Trace 2– Inductor Switching Node (2.0 V/div.)

Figure 13. Startup with Regulator Output Shorted Overvoltage Protection

Overvoltage protection (OVP) is provided as result of the normal operation of the V2 control topology and requires no additional external components. The control loop responds to an overvoltage condition within 100 ns, causing the top MOSFET to shut off, disconnecting the regulator from it’s input voltage. The bottom MOSFET is then activated, resulting in a “crowbar” action to clamp the output voltage and prevent damage to the load (see Figures 14 and 15). The regulator will remain in this state until the overvoltage


CS5150H 5.0 V

condition ceases or the input voltage is pulled low. The bottom FET and board trace must be properly designed to implement the OVP function.

MMUN2111T1 (SOT–23) 5 SS

CS5150H 8 V FFB IN4148 Shutdown Input

M 10.0 µs

Figure 16. Implementing Shutdown with the CS5150H

Trace 4– 5.0 V from PC Power Supply (5.0 V/div.) Trace 1– Regulator Output Voltage (1.0 V/div.)

External Power Good Circuit

Trace 2– Inductor Switching Node 5.0 V/div.)

An optional Power Good signal can be generated through the use of four additional external components (see Figure 17). The threshold voltage of the Power Good signal can be adjusted per the following equation:

Figure 14. OVP Response to an Input–to–Output Short Circuit by Immediately Providing 0% Duty Cycle, Crow–Barring the Input Voltage to Ground

VPower Good +

(R1 ) R2) 0.65 V R2

This circuit provides an open collector output that drives the Power Good output to ground for regulator voltages less than VPower Good. 5.0 V R3 10 k VOUT

CS5150H M 5.00 ms

R1 10 k

PN3904

Power Good

PN3904

R2 6.2 k


Figure 15. OVP Response to an Input–to–Output Short Circuit by Pulling the Input Voltage to Ground

Figure 17. Implementing Power Good with the CS5150H

External Output Enable Circuit

On/off control of the regulator can be implemented through the addition of two additional discrete components (see Figure 16). This circuit operates by pulling the Soft Start pin high, and the VFFB pin low, emulating a short circuit condition.


CS5150H

M 1.00 µs

M 2.50 ms Trace 3 – 12 V Input (VCC1) and (VCC2) (10 V/div.)

Trace 3 = VGATE(H) (10 V/div.)

Trace 4– 5.0 V Input (2.0 V/div.)

Math 1 = VGATE(H) – 5.0 VIN

Trace 1– Regulator Output Voltage (1.0 V/div.)

Trace 4 = VGATE(L) (10 V/div.)

Trace 2– Power Good Signal (2.0 V/div.)

Trace 2– Inductor Switching Nodes (5.0 V/div.)

Figure 18. CS5150H Demonstration Board During Power Up. Power Good Signal is Activated when Output Voltage Reaches 1.70 V.

Figure 19. CS5150H Gate Drive Waveforms Depicting Rail to Rail Swing

The most important aspect of MOSFET performance is RDSON, which effects regulator efficiency and MOSFET thermal management requirements. The power dissipated by the MOSFETs may be estimated as follows; Switching MOSFET:

Selecting External Components

The CS5150H can be used with a wide range of external power components to optimize the cost and performance of a particular design. The following information can be used as general guidelines to assist in their selection.

Power + ILOAD2

NFET Power Transistors

RDSON

duty cycle

Synchronous MOSFET:

Both logic level and standard MOSFETs can be used. The reference designs derive gate drive from the 12 V supply which is generally available in most computer systems and utilize logic level MOSFETs. A charge pump may be easily implemented to permit use of standard MOSFETs or support 5.0 V or 12 V only systems (maximum of 20 V). Multiple MOSFETs may be paralleled to reduce losses and improve efficiency and thermal management. Voltage applied to the MOSFET gates depends on the application circuit used. Both upper and lower gate driver outputs are specified to drive to within 1.5 V of ground when in the low state and to within 2.0 V of their respective bias supplies when in the high state. In practice, the MOSFET gates will be driven rail to rail due to overshoot caused by the capacitive load they present to the controller IC. For the typical application where VCC1 = VCC2 = 12 V and 5.0 V is used as the source for the regulator output current, the following gate drive is provided;

Power + ILOAD2

RDSON

(1 * duty cycle)

Duty Cycle = VOUT ) (ILOAD

ƪ

RDSON OF SYNCH FET)

VIN)(ILOAD RDSON OF SYNCH FET) * (ILOAD RDSON OF SWITCH FET)

ƫ

Off Time Capacitor (COFF)

The COFF timing capacitor sets the regulator off time: TOFF + COFF

4848.5

When the VFFB pin is less than 1.0 V, the current charging the COFF capacitor is reduced. The extended off time can be calculated as follows: TOFF + COFF

24, 242.5

Off time will be determined by either the TOFF time, or the time out timer, whichever is longer.

VGATE(H) + 12 V * 5.0 V + 7.0 V, VGATE(L) + 12 V

(see Figure 19.)


CS5150H provide acceptable ripple on the input supply lines and regulator output voltage. Key specifications for input capacitors are their ripple rating, while ESR is important for output capacitors. For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required.

The preceding equations for duty cycle can also be used to calculate the regulator switching frequency and select the COFF timing capacitor: COFF +

Perioid

(1 * duty cycle) 4848.5

where: Period +

Output Inductor

1 switching frequency

The inductor should be selected based on its inductance, current capability, and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response.

Schottky Diode for Synchronous MOSFET

A Schottky diode may be placed in parallel with the synchronous MOSFET to conduct the inductor current upon turn off of the switching MOSFET to improve efficiency. The CS5150H reference circuit does not use this device due to its excellent design. Instead, the body diode of the synchronous MOSFET is utilized to reduce cost and conducts the inductor current. For a design operating at 200 kHz or so, the low non–overlap time combined with Schottky forward recovery time may make the benefits of this device not worth the additional expense (see Figure 8, channel 2). The power dissipation in the synchronous MOSFET due to body diode conduction can be estimated by the following equation: Power + VBD

ILOAD

conduction time

THERMAL MANAGEMENT Thermal Considerations for Power MOSFETs and Diodes

In order to maintain good reliability, the junction temperature of the semiconductor components should be kept to a maximum of 150°C or lower. The thermal impedance (junction to ambient) required to meet this requirement can be calculated as follows: Thermal Impedance +

A heatsink may be added to TO–220 components to reduce their thermal impedance. A number of PC board layout techniques such as thermal vias and additional copper foil area can be used to improve the power handling capability of surface mount components.

switching frequency

Where VBD = the forward drop of the MOSFET body diode. For the CS5150H demonstration board as shown in Figure 8; Power + 1.6 V

13 A

100 ns

TJUNCTION(MAX) * TAMBIENT Power

233 kHz + 0.48 W

This is only 1.3% of the 36.4 W being delivered to the load.

EMI Management

As a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. When designing for compliance with EMI/EMC regulations, additional components may be added to reduce noise emissions. These components are not required for regulator operation and experimental results may allow them to be eliminated. The input filter inductor may not be required because bulk filter and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the circuit board and input power supply. Placement of the power component to minimize routing distance will also help to reduce emissions.

“Droop” Resistor for Adaptive Voltage Positioning

Adaptive voltage positioning is used to reduce output voltage excursions during abrupt changes in load current. Regulator output voltage is offset +40 mV when the regulator is unloaded, and –40 mV at full load. This results in increased margin before encountering minimum and maximum transient voltage limits, allowing use of less capacitance on the regulator output (see Figure 9). To implement adaptive voltage positioning, a “droop” resistor must be connected between the output inductor and output capacitors and load. This is normally implemented by a PC board trace of the following value: RDROOP + 80 mV IMAX

Adaptive voltage positioning can be disabled for improved DC regulation by connecting the VFB pin directly to the load using a separate, non–load current carrying circuit trace. Input and Output Capacitors

These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to


CS5150H RTRACE + 80 mV IMAX

This causes the output voltage to be +40 mV with no load, and –40 mV with a full load, improving regulator transient response. This trace must be wide enough to carry the full output current. (Typical trace is 1.0 inch long, 0.17 inch wide). Care should be taken to minimize any additional losses after the feedback connection point to maximize regulation. 7. If DC regulation is to be optimized (at the expense of degraded transient regulation), adaptive voltage positioning can be disabled by connecting to VFB pin directly to the load with a separate trace (remote sense). 8. Place 5.0 V input capacitors close to the switching MOSFET and synchronous MOSFET. Route gate drive signals VGATE(H) (pin 10) and VGATE(L) (pin 12 when used) with traces that are a minimum of 0.025 inches wide.

2.0 µH

33 Ω 1000 pF

Figure 20. Filter Components 2.0 µH + 1200 pF × 3.0/16 V

Figure 21. Input Filter To the negative terminal of the input capacitors

VCC 0.1 µF

Layout Guidelines

1. Place 12 V filter capacitor next to the IC and connect capacitor ground to pin 11 (PGND). 2. Connect pin 11 (PGND) with a separate trace to the ground terminals of the 5.0 V input capacitors. 3. Place fast feedback filter capacitor next to pin 8 (VFFB) and connect it’s ground terminal with a separate, wide trace directly to pin 14 (LGND). 4. Connect the ground terminals of the Compensation capacitor directly to the ground of the fast feedback filter capacitor to prevent common mode noise from effecting the PWM comparator. 5. Place the output filter capacitor(s) as close to the load as possible and connect the ground terminal to pin 14 (LGND). 6. To implement adaptive voltage positioning, connect both slow and fast feedback pins 16 (VFB) and 8 (VFFB) to the regulator output right at the inductor terminal. Connect inductor to the output capacitors via a trace with the following resistance:

15

11

1.0 µF VCOMP

8 5

100 pF VFFB

SOFT START

OFF TIME To the negative terminal of the output capacitors

Figure 22. Layout Guidelines


CS5150H 5.0V

0.1 µF MBRS 120

MBRS120 1.0 µF

MBRS120 1.0 µF

VCC2

VCC1

+

100 µF/10 V × 3 Tantalum

Si4410DY

VGATE(H)

3.0 µH

3.3 V/10 A

VID0 VID1 VID2 VID3

CS5150H Si9410DY

VGATE(L) COFF PGND

330 pF SS

VFB

COMP

0.1 µF

3.3 k LGND

VFFB + 100 µF/10 V × 3 Tantalum

100 pF

0.33 µF

Figure 23. Additional Application Diagram, 5.0 V to 3.3 V/10 A Converter 12 V

1N5818 +12 V

1N5818 22 Ω 1/4 W

+ 1N4746 18 V 1.0 W

1.0 µF

1.0 µF

VCC1

VCC2 VGATE(H)

VID0 VID1

0.1 µF FY10AJJ03

820 µF/16 V × 4 Aluminum Electrolytic

1.1 µH

VFB

VID2 VID3

+

CS5150H VGATE(L)

FY10AJJ03

COFF

330 pF

PGND

COMP

3.3 k LGND

0.33 µF


FY10AJJ03

SS 0.1 µF

3.5 V/5.0 A

VFFB 100 pF

Figure 24. Additional Application Diagram, 12 V to 3.3 V/5.0 V Converter with Remote Sense http://onsemi.com 2005

CS5150H 5.0V MBRS 120

0.1 µF

MBRS120 +

1.0 µF

MBRS120

100 µF/10 V × 3 Tantalum Remote Sense

1.0 µF

VCC2

VCC1

Si4410

VGATE(H)

3.0 µH

3.3 V/10 A

VID0 VID1

VFB

VID2

10 Ω

VID3

CS5150H


+

Si9410

VGATE(L) COFF 330 pF SS 0.1 µF

PGND

COMP

3.3 k LGND

VFFB

0.33 µF

Connect to other circuits for current sharing

100 pF

Figure 26. Additional Application Diagram, 5.0 V to 3.3 V/10 A Converter with Current Sharing 12 V

3.3 V

1.0 µF + VCC1

VCC2

Si9410

VGATE(H) VID0

33 µF/25 V × 3 Tantalum 5.0 µH

2.5 V/7.0 A

VID1 VID2 VID3

VFB

CS5150H

+

COFF 330 pF

Si9410

VGATE(L) SS


PGND

0.1 µF COMP

3.3 k LGND

0.33 µF

VFFB 100 pF

Figure 25. Additional Application Diagram, 3.3 V to 2.5 V/7.0 A Converter with 12 V Bias


CS5150H PACKAGE THERMAL DATA Parameter

16–SO

Unit

RΘJC

Typical

28

°C/W

RΘJA

Typical

115

°C/W


89 -" 2!&# ! The CS5151H is a 4–bit nonsynchronous N–Channel buck controller. It is designed to provide unprecedented transient response for today’s demanding high–density, high–speed logic. The regulator operates using a proprietary control method, which allows a 100 ns response time to load transients. The CS5151H is designed to operate over a 4.25–20 V range (VCC) using 12 V to power the IC and 5.0 V or 12 V as the main supply for conversion. The CS5151H is specifically designed to power Pentium processors with MMX Technology and other high performance core logic. It includes the following features: on board, 4–bit DAC, short circuit protection, 1.0% output tolerance, VCC monitor, and programmable Soft Start capability. The CS5151H is upwards compatible with the 5–bit CS5156H, allowing the mother board designer the capability of using either the CS5151H or the CS5156H with no change in layout. The CS5151H is available in 16 pin surface mount package. Features N–Channel Design Excess of 1.0 MHz Operation 100 ns Transient Response 4–Bit DAC Upward Compatible with 5–Bit CS5155H/CS5156H 30 ns Gate Rise/Fall Times 1.0% DAC Accuracy 5.0 V & 12 V Operation Remote Sense Programmable Soft Start Lossless Short Circuit Protection VCC Monitor Adaptive Voltage Positioning V2 Control Topology Current Sharing Overvoltage Protection

• • • • • • • • • • • • • • • •




16 1

CS5151H AWLYWW

SOIC–16 D SUFFIX CASE 751B

A WL, L YY, Y WW, W

1


PIN CONNECTIONS 1

16

VID0 VID1 VID2 VID3 SS NC COFF VFFB

VFB COMP LGND VCC1 NC PGND VGATE VCC2


2008

Package

Shipping

CS5151HGD16

SO–16

48 Units/Rail

CS5151HGDR16

SO–16

2500 Tape & Reel


CS5151H 5.0 V

12 V

0.1 µF VCC1

VCC2

1200 µF/16 V × 3 AIEI

IRL3103 VGATE

VID0

VID0

VID1

VID1

VID2

VID2

VID3

VID3

2.0 µH

2.1 V to 3.5 V @ 13 A

3 MBR735

CS5151H

1,2

COFF 330 pF

PGND SS

0.1 µF

COMP

VFB 3.3 k LGND

0.33 µF

VFFB

1200 µF/16 V × 5 AIEI

100 pF

Figure 1. Application Diagram, Switching Power Supply for Core Logic – Pentium) Processor with MMX Technology


Value

Unit

0 to 150

°C

230 peak

°C

–65 to +150

°C

2.0

kV






Max Current

VCC1

16 V/–0.3 V

25 mA DC/1.5 A peak

VCC2

20 V/–0.3 V

20 mA DC/1.5 A peak

SS

6.0 V/–0.3 V

–100 µA

COMP

6.0 V/–0.3 V

200 µA

VFB

6.0 V/–0.3 V

–0.2 µA

COFF

6.0 V/–0.3 V

–0.2 µA

VFFB

6.0 V/–0.3 V

–0.2 µA

VID0 – VID3

6.0 V/–0.3 V

–50 µA

VGATE

20 V/–0.3 V


LGND

0V

25 mA

PGND

0V



CS5151H ELECTRICAL CHARACTERISTICS (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 20 V; DAC Code: VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit


VFB = 0 V

–

0.3

1.0

µA

Open Loop Gain

1.25 V < VCOMP < 4.0 V; Note 2

50

60

–

dB


Note 2

500

3000

–

kHz

COMP SINK Current

VCOMP = 1.5 V; VFB = 3.0 V; VSS > 2.0 V

0.4

2.5

8.0

mA

COMP SOURCE Current

VCOMP = 1.2 V; VFB = 2.7 V; VSS = 5.0 V

30

50

80

µA

COMP CLAMP Current


0.4

1.0

1.6

mA

COMP High Voltage

VFB = 2.7 V; VSS = 5.0 V

4.0

4.3

5.0

V

COMP Low Voltage

VFB = 3.0 V

–

160

600

mV

PSRR

8.0 V < VCC1 < 14 V @ 1.0 kHz; Note 2

60

85

–

dB


Output switching

3.75

3.90

4.05

V

Stop Threshold


3.70

3.85

4.00

V

Hysteresis

Start–Stop

–

50

–

mV

DAC Input Threshold


1.00

1.25

2.40

V



25

50

100

kΩ

4.85

5.00

5.15

V

–

–

1.0

%

Pull Up Voltage

–


Measure VFB = VCOMP, 25°C ≤ TJ ≤ 125°C

VID3

VID2

VID1

VID0

1

1

1

1

–

1.2191

1.2440

1.2689

V

1

1

1

0

–

2.1186

2.1400

2.1614

V

1

1

0

1

–

2.2176

2.2400

2.2624

V

1

1

0

0

–

2.3166

2.3400

2.3634

V

1

0

1

1

–

2.4156

2.4400

2.4644

V

1

0

1

0

–

2.5146

2.5400

2.5654

V

1

0

0

1

–

2.6136

2.6400

2.6664

V

1

0

0

0

–

2.7126

2.7400

2.7674

V

0

1

1

1

–

2.8116

2.8400

2.8684

V

0

1

1

0

–

2.9106

2.9400

2.9694

V

0

1

0

1

–

3.0096

3.0400

3.0704

V

0

1

0

0

–

3.1086

3.1400

3.1714

V

0

0

1

1

–

3.2076

3.2400

3.2724

V

0

0

1

0

–

3.3066

3.3400

3.3734

V

0

0

0

1

–

3.4056

3.4400

3.4744

V

0

0

0

0

–

3.5046

3.5400

3.5754

V



CS5151H ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 20 V; DAC Code: VID2 = VID1 = VID0 =1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit

VGATE Out SOURCE Sat at 100 mA

Measure VCC2 – VGATE

–

1.2

2.0

V


Measure VGATE – VPGND

–

1.0

1.5

V

Out Rise Time

1.0 V < VGATE < 9.0 V; VCC1 = VCC2 = 12 V

–

30

50

ns

Out Fall Time

9.0 V > VGATE > 1.0 V; VCC1 = VCC2 = 12 V

–

30

50

ns


Note 3

–

–

50

mA

VGATE Resistance


20

50

100

kΩ

VGATE Schottky

LGND to VGATE @ 10 mA

–

600

800

mV


–

1.6

3.3

5.0

ms

Pulse Period

–

25

100

200

ms

Duty Cycle


1.0

3.3

6.0

%

COMP Clamp Voltage

VFB = 0 V; VSS = 0

0.50

0.95

1.10

V


VGATE = Low

0.9

1.0

1.1

V

–

2.5

3.0

V

High Threshold

–


VFFB = 0 to 5.0 V to VGATE = 9.0 V to 1.0 V; VCC1 = VCC2 = 12 V

–

100

125

ns

VFFB Bias Current

VFFB = 0 V

–

0.3

–

µA

ICC1

No Switching

–

8.5

13.5

mA

ICC2

No Switching

–

1.6

3.0

mA

Operating ICC1

VFB = COMP = VFFB

–

8.0

13

mA

Operating ICC2

VFB = COMP = VFFB

–

2.0

5.0

mA

Supply Current


VFFB = 1.5 V; VSS = 5.0 V

1.0

1.6

2.2

µs


VSS = VFFB = 0

5.0

8.0

11.0

µs

Discharge Current


5.0

–

–

mA

Time Out Time

VFB = VCOMP; VFFB = 2.0 V; Record VGATE Pulse High Duration

10

30

65

µs


VFFB = 0V

35

50

70

%

Time Out Timer



CS5151H PACKAGE PIN DESCRIPTION PACKAGE PIN # 16 Lead SO Narrow

PIN SYMBOL

FUNCTION

1, 2, 3, 4

VID0–VID3

Voltage ID DAC input pins. These pins are internally pulled up to 5.0 V providing logic ones if left open. The DAC range is 2.14 V to 3.54 V with 100 mV increments. VID0 – VID3 select the desired DAC output voltage. Leaving all 4 DAC input pins open results in a DAC output voltage of 1.244 V, allowing for adjustable output voltage, using a traditional resistor divider.

5

SS


6, 12

NC

No Connection.

7

COFF


8

VFFB


9

VCC2

Boosted power for the gate driver.

10

VGATE

MOSFET driver pin capable of 1.5 A peak switching current.

11

PGND

High current ground for the IC. The MOSFET driver is referenced to this pin. Input capacitor ground and the anode of the Schottky diode should be tied to this pin.

13

VCC1

Input power for the IC.

14

LGND


15

COMP


16

VFB



CS5151H VCC2 VCC1

–


+

–

3.90 V 3.85V

VGATE

SS Low Comparator R

60 µA

SS +

2.0 µA

Q S FAULT Latch

VID2

SS High Comparator

PGND

FAULT

–

VID0 VID1

Q

+ 0.7 V

FAULT

4 BIT DAC

Error Amplifier

2.5 V

+ –

PWM Comparator

VID3

– VFB


+

Slow Feedback


COMP

VFFB

Fast Feedback

– +

LGND

1.0 V

GATE = ON

R

Q

S

Q PMW Latch

GATE = OFF COFF One Shot R

Off–Time Timeout

COFF Q

S

VFFB Low Comparator


PWM COMP

Edge Triggered



PWM Comparator + VGATE C

V2 Control Method


–

Ramp Signal

VFFB

VFB


Error Signal


–

E +



Reference Voltage



The CS5151H is designed to provide two methods for programming the output voltage of the power supply. A four bit on board digital to analog converter (DAC) is used to program the output voltage from 2.14 V to 3.54 V in 100 mV steps, depending on the digital input code. If all four bits are left open, the CS5151H enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feedback to the VFB and VFFB pins, as in traditional controllers. The CS5151H is specifically designed to be upwards compatible with the CS5156H, which uses a five bit DAC code. Start Up

Until the voltage on the VCC1 supply pin exceeds the 3.9 V monitor threshold, the Soft Start and gate pins are held low. The FAULT latch is reset (no Fault condition). The output of the error amplifier (COMP) is pulled up to 1.0 V by the comparator clamp. When the VCC1 pin exceeds the monitor threshold, the GATE output is activated, and the Soft Start capacitor begins charging. The GATE output will remain on, enabling the NFET switch, until terminated by either the PWM comparator, or the maximum on time timer. If the maximum on time is exceeded before the regulator output voltage achieves the 1.0 V level, the pulse is terminated. The GATE pin drives low for the duration of the extended off time. This time is set by the time out timer and is approximately equal to the maximum on time, resulting in a 50% duty cycle. Then, the GATE pin will drive high, and the cycle repeats. When regulator output voltage achieves the 1.0 V level present at the COMP pin, regulation has been achieved and normal off time will ensue. The PWM comparator terminates the switch on time, with off time set by the COFF capacitor. The V2 control loop will adjust switch duty cycle as required to ensure the regulator output voltage tracks the output of the error amplifier. The Soft Start and COMP capacitors will charge to their final levels, providing a controlled turn on of the regulator output. Regulator turn on time is determined by the COMP capacitor charging to its final value. Its voltage is limited by

Constant Off Time



CS5151H the Soft Start COMP clamp and the voltage on the Soft Start pin (see Figures 4 and 5).

M 10.0 µs Trace 1– Regulator Output Voltage (5.0 V/div.)

M 250 µs


Trace 1– Regulator Output Voltage (1.0 V/div.) Trace 2– Inductor Switching Node (2.0 V/div.) Trace 3– 12 V Input (VCC1 and VCC2) (5.0 V/div.)




Normal Operation




M 1.00 µs


Trace 1– Regulator Output Voltage (10 mV/div.) Trace 2– Inductor Switching Node (5.0 V/div.)




M 1.00 µs Trace 1– Regulator Output Voltage (10 V/div.) Trace 2– Inductor Switching Node (5.0 V/div.)








CS5151H traces than occurs with constant current limit protection (see Figures 12 and 13). If the short circuit condition is removed, output voltage will rise above the 1.0 V level, preventing the FAULT latch from being set, allowing normal operation to resume.







A lossless hiccup mode short circuit protection feature is provided, requiring only the Soft Start capacitor to implement. If a short circuit condition occurs (VFFB < 1.0 V), the VFFB low comparator sets the FAULT latch. This causes the MOSFET to shut off, disconnecting the regulator from it’s input voltage. The Soft Start capacitor is then slowly discharged by a 2.0 µA current source until it reaches it’s lower 0.7 V threshold. The regulator will then attempt to restart normally, operating in it’s extended off time mode with a 50% duty cycle, while the Soft Start capacitor is charged with a 60 µA charge current. If the short circuit condition persists, the regulator output will not achieve the 1.0 V low VFFB comparator threshold before the Soft Start capacitor is charged to it’s upper 2.5 V threshold. If this happens the cycle will repeat itself until the short is removed. The Soft Start charge/discharge current ratio sets the duty cycle for the pulses (2.0 µA/60 µA = 3.3%), while actual duty cycle is half that due to the extended off time mode (1.65%). This protection feature results in less stress to the regulator components, input power supply, and PC board



Overvoltage protection (OVP) is provided as result of the normal operation of the V2 control topology and requires no additional external components. The control loop responds to an overvoltage condition within 100 ns, causing the MOSFET to shut off, disconnecting the regulator from it’s input voltage. External Output Enable Circuit

On/off control of the regulator can be implemented through two additional discrete components (see Figure 14).


CS5151H This circuit operates by pulling the Soft Start pin high, and the VFFB pin low, emulating a short circuit condition. 5.0 V


CS5151H M 2.50 ms

8 V FFB

Trace 3 – 12 V Input (VCC1) and (VCC2) (10 V/div.)

IN4148


Shutdown Input

Trace 1– Regulator Output Voltage (1.0 V/div.) Trace 2– Power Good Signal (2.0 V/div.)


Figure 14. Implementing Shutdown with the CS5151H External Power Good Circuit


An optional Power Good signal can be generated through the use of four additional external components (see Figure 15). The threshold voltage of the Power Good signal can be adjusted per the following equation: VPower Good +


(R1 ) R2) 0.65 V R2


Both logic level and standard MOSFETs can be used. The reference designs derive gate drive from the 12 V supply which is generally available in most computer systems and use logic level MOSFETs. A charge pump may be easily implemented to permit use of standard MOSFETs or support 5.0 V or 12 V only systems (maximum of 20 V). Multiple MOSFETs may be paralleled to reduce losses and improve efficiency and thermal management. Voltage applied to the MOSFET gates depends on the application circuit used. The gate driver output is specified to drive to within 1.5 V of ground when in the low state and to within 2.0 V of its bias supply when in the high state. In practice, the MOSFET gate will be driven rail to rail due to overshoot caused by the capacitive load it presents to the controller IC. For the typical application where VCC1 = VCC2 = 12 V and 5.0 V is used as the source for the regulator output current, the following gate drive is provided;


CS5151H

R1 10 k

PN3904

Power Good

PN3904

R2 6.2 k


VGATE + 12 V * 5.0 V + 7.0 V

(see Figure 17.)


CS5151H “Droop” Resistor for Adaptive Voltage Positioning


M 1.00 µs

Adaptive voltage positioning can be disabled for improved DC regulation by connecting the VFB pin directly to the load using a separate, non–load current carrying circuit trace.

Channel 3 = VGATE M1 = VGATE – 5.0 VIN Channel 2– Inductor Switching Node


Input and Output Capacitors

The most important aspect of MOSFET performance is RDSON, which effects regulator efficiency and MOSFET thermal management requirements. The power dissipated by the MOSFET and the Schottky diode may be estimated as follows; Switching MOSFET: Power + ILOAD2

RDSON

These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to provide acceptable ripple on the input supply lines and regulator output voltage. Key specifications for input capacitors are their ripple rating, while ESR is important for output capacitors. For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required.

duty cycle

Schottky diode: Power + VFORWARD

ILOAD

(1 * duty cycle)

Output Inductor


Duty Cycle = VOUT ) VFORWARD VIN ) VFORWARD * (ILOAD RDSON OF SYNCH FET)


THERMAL MANAGEMENT


Thermal Considerations for Power MOSFETs and Diodes

4848.5


In order to maintain good reliability, the junction temperature of the semiconductor components should be kept to a maximum of 150°C or lower. The thermal impedance (junction to ambient) required to meet this requirement can be calculated as follows:

24, 242.5

Off time will be determined by either the TOFF time, or the time out timer, whichever is longer. The preceding equations for duty cycle can also be used to calculate the regulator switching frequency and select the COFF timing capacitor: COFF +

Perioid

Thermal Impedance +


(1 * duty cycle) 4848.5

where: Period +




CS5151H EMI Management

RTRACE + 80 mV IMAX


This causes the output voltage to be +40 mV with no load, and –40 mV with a full load, improving regulator transient response. This trace must be wide enough to carry the full output current. (Typical trace is 1.0 inch long, 0.17 inch wide). Care should be taken to minimize any additional losses after the feedback connection point to maximize regulation. 7. If DC regulation is to be optimized (at the expense of degraded transient regulation), adaptive voltage positioning can be disabled by connecting to VFB pin directly to the load with a separate trace (remote sense). 8. Place 5.0 V input capacitors close to the switching MOSFET. Route gate drive signals VGATE (pin 10) with a trace that is a minimum of 0.025 inches wide.

2.0 µH

To the negative terminal of the input capacitors

VCC 0.1 µF

33 Ω 1000 pF

15

11

1.0 µF VCOMP

Figure 18. Filter Components 2.0 µH

8 +

5

1200 pF × 3.0/16 V

100 pF VFFB

SOFT START

OFF TIME

Figure 19. Input Filter

To the negative terminal of the output capacitors

Layout Guidelines




CS5151H 5.0V

0.1 µF MBRS 120

MBRS120 1.0 µF

MBRS120 1.0 µF

VCC2

VCC1

+


Si4410DY

VGATE

3.0 µH

3.3 V/10 A

VID0 VID1 2

VID2

MBR1535CT

VID3

1,3

CS5151H

COFF PGND

330 pF SS

VFB

COMP

0.1 µF

3.3 k LGND


100 pF

0.33 µF

Figure 21. Additional Application Diagram, 5.0 V to 3.3 V/10 A Converter 12 V

3.3 V

1.0 µF + VCC1

VCC2

Si9410

VGATE


VID0

2.5 V/7.0 A

VID1 VID2 VID3

VFB

2

CS5151H MBR1535CT COFF

1,3

+


330 pF

SS

PGND

0.1 µF COMP

3.3 k LGND

0.33 µF

VFFB 100 pF



CS5151H 5.0V MBRS 120

0.1 µF

MBRS120

1.0 µF

+

1.0 µF

MBRS120


VCC1

VCC2

Si4410

VGATE

3.0 µH

3.3 V/10 A

VID0 VID1

VFB

VID2 VID3

10 Ω 2

CS5151H

MBR1535CT

+


1,3

COFF 330 pF SS 0.1 µF

PGND

COMP

3.3 k LGND

VFFB

0.33 µF


100 pF

Figure 23. Additional Application Diagram, 5.0 V to 3.3 V/10 A Converter with Current Sharing PACKAGE THERMAL DATA Parameter

16–SO

Unit

RΘJC

Typical

28

°C/W

RΘJA

Typical

115

°C/W


89 -" &# ! The CS5155H is a 5–bit synchronous dual N–Channel buck controller. It is designed to provide unprecedented transient response for today’s demanding high–density, high–speed logic. The regulator operates using a proprietary control method, which allows a 100 ns response time to load transients. The CS5155H is designed to operate over a 4.25–20 V range (VCC) using 12 V to power the IC and 5.0 V or 12 V as the main supply for conversion. The CS5155H is specifically designed to power Pentium II processors and other high performance core logic. It includes the following features: on board, 5–bit DAC, short circuit protection, 1.0% output tolerance, VCC monitor, and programmable Soft Start capability. The CS5155H is backwards compatible with the 4–bit CS5150, allowing the mother board designer the capability of using either the CS5150 or the CS5155H with no change in layout. The CS5155H is available in 16 pin surface mount packages. Features Dual N–Channel Design Excess of 1.0 MHz Operation 100 ns Transient Response 5–Bit DAC Backward Compatible with 4–Bit CS5150H/CS5151H 30 ns Gate Rise/Fall Times 1.0% DAC Accuracy 5.0 V & 12 V Operation Remote Sense Programmable Soft Start Lossless Short Circuit Protection VCC Monitor 25 ns FET Nonoverlap Time Adaptive Voltage Positioning V2 Control Topology Current Sharing Overvoltage Protection

• • • • • • • • • • • • • • • • •




16 1

CS5155H AWLYWW


A WL, L YY, Y WW, W

1


PIN CONNECTIONS 1

16

VID0 VID1 VID2 VID3 SS VID4 COFF VFFB



2023

Package

Shipping

CS5155HGD16

SO–16

48 Units/Rail

CS5155HGDR16

SO–16

2500 Tape & Reel


CS5155H 5.0 V

12 V

0.1 µF VCC1

VCC2

1200 µF/16 V × 3 AIEI

IRL3103 VGATE(H)

VID0

VID0

VID1

VID1

VID2

VID2

VID3

VID3

VID4

VID4

2.0 µH

IRL3103

VGATE(L)

CS5155H

COFF

330 pF

1.3 V to 3.5 V @ 13 A

PGND

SS 0.1 µF

COMP

VFB 3.3 k

0.33 µF

LGND

VFFB

1200 µF/16 V × 5 AIEI

100 pF

Figure 1. Application Diagram, Switching Power Supply for Core Logic – Pentium) II Processor


Value

Unit

0 to 150

°C

260 peak 230 peak

°C

–65 to +150

°C

2.0

kV


Wave Solder (through hole styles only) (Note 1) Reflow: (SMD styles only) (Note 2)

Storage Temperature Range, TS ESD Susceptibility (Human Body Model) 1. 10 second maximum. 2. 60 second maximum above 183°C. *The maximum package power dissipation must be observed.



Max Current

VCC1

16 V/–0.3 V

25 mA DC/1.5 A peak

VCC2

20 V/–0.3 V

20 mA DC/1.5 A peak

SS

6.0 V/–0.3 V

–100 µA

COMP

6.0 V/–0.3 V

200 µA

VFB

6.0 V/–0.3 V

–0.2 µA

COFF

6.0 V/–0.3 V

–0.2 µA

VFFB

6.0 V/–0.3 V

–0.2 µA

VID0 – VID4

6.0 V/–0.3 V

–50 µA

VGATE(H)

20 V/–0.3 V


VGATE(L)

16 V/–0.3 V


LGND

0V

25 mA

PGND

0V



CS5155H ELECTRICAL CHARACTERISTICS (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 20 V;DAC Code: VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit


VFB = 0 V

–

0.3

1.0

µA

Open Loop Gain

1.25 V < VCOMP < 4.0 V; Note 3

50

60

–

dB


Note 3

500

3000

–

kHz

COMP SINK Current

VCOMP = 1.5 V; VFB = 3.0 V; VSS > 2.0 V

0.4

2.5

8.0

mA

COMP SOURCE Current

VCOMP = 1.2 V; VFB = 2.7 V; VSS = 5.0 V

30

50

80

µA

COMP CLAMP Current


0.4

1.0

1.6

mA

COMP High Voltage

VFB = 2.7 V; VSS = 5.0 V

4.0

4.3

5.0

V

COMP Low Voltage

VFB = 3.0 V

–

160

600

mV

PSRR

8.0 V < VCC1 < 14 V @ 1.0 kHz; Note 3

60

85

–

dB


Output switching

3.75

3.90

4.05

V

Stop Threshold


3.70

3.85

4.00

V

Hysteresis

Start–Stop

–

50

–

mV

Out SOURCE Sat at 100 mA


–

1.2

2.0

V



–

1.0

1.5

V

Out Rise Time


–

30

50

ns

Out Fall Time


–

30

50

ns


Note 3

–

–

50

mA


VGATE(H) falling to 2.0 V; VCC1 = VCC2 = 8.0 V; VGATE(L) rising to 2.0 V

–

25

50

ns


VGATE(L) falling to 2.0 V; VCC1 = VCC2 = 8.0 V; VGATE(H) rising to 2.0 V

–

25

50

ns



20

50

100

kΩ


LGND to VGATE(H) @ 10 mA LGND to VGATE(L) @ 10 mA

–

600

800

mV

VGATE(H) and VGATE(L)


–

1.6

3.3

5.0

ms

Pulse Period

–

25

100

200

ms

Duty Cycle


1.0

3.3

6.0

%

COMP Clamp Voltage

VFB = 0 V; VSS = 0

0.50

0.95

1.10

V



0.9

1.0

1.1

V

–

2.5

3.0

V

High Threshold

–



–

100

125

ns

VFFB Bias Current

VFFB = 0 V

–

0.3

–

µA



CS5155H ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 20 V;DAC Code: VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

DAC Input Threshold

VID0, VID1, VID2, VID3, VID4

1.00

1.25

2.40

V



25

50

100

kΩ

4.85

5.00

5.15

V

–

–

1.0

%

Pull Up Voltage

–



VID4

VID3

VID2

VID1

VID0

0

1

1

1

1

–

1.3266

1.3400

1.3534

V

0

1

1

1

0

–

1.3761

1.3900

1.4039

V

0

1

1

0

1

–

1.4256

1.4400

1.4544

V

0

1

1

0

0

–

1.4751

1.4900

1.5049

V

0

1

0

1

1

–

1.5246

1.5400

1.5554

V

0

1

0

1

0

–

1.5741

1.5900

1.6059

V

0

1

0

0

1

–

1.6236

1.6400

1.6564

V

0

1

0

0

0

–

1.6731

1.6900

1.7069

V

0

0

1

1

1

–

1.7226

1.7400

1.7574

V

0

0

1

1

0

–

1.7721

1.7900

1.8079

V

0

0

1

0

1

–

1.8216

1.8400

1.8584

V

0

0

1

0

0

–

1.8711

1.8900

1.9089

V

0

0

0

1

1

–

1.9206

1.9400

1.9594

V

0

0

0

1

0

–

1.9701

1.9900

2.0099

V

0

0

0

0

1

–

2.0196

2.0400

2.0604

V

0

0

0

0

0

–

2.0691

2.0900

2.1109

V

1

1

1

1

1

–

1.2191

1.2440

1.2689

V

1

1

1

1

0

–

2.1186

2.1400

2.1614

V

1

1

1

0

1

–

2.2176

2.2400

2.2624

V

1

1

1

0

0

–

2.3166

2.3400

2.3634

V

1

1

0

1

1

–

2.4156

2.4400

2.4644

V

1

1

0

1

0

–

2.5146

2.5400

2.5654

V

1

1

0

0

1

–

2.6136

2.6400

2.6664

V

1

1

0

0

0

–

2.7126

2.7400

2.7674

V

1

0

1

1

1

–

2.8116

2.8400

2.8684

V

1

0

1

1

0

–

2.9106

2.9400

2.9694

V

1

0

1

0

1

–

3.0096

3.0400

3.0704

V

1

0

1

0

0

–

3.1086

3.1400

3.1714

V

1

0

0

1

1

–

3.2076

3.2400

3.2724

V

1

0

0

1

0

–

3.3066

3.3400

3.3734

V

1

0

0

0

1

–

3.4056

3.4400

3.4744

V

1

0

0

0

0

–

3.5046

3.5400

3.5754

V



Test Conditions

Min

Typ

Max

Unit

Supply Current ICC1

No Switching

–

8.5

13.5

mA

ICC2

No Switching

–

1.6

3.0

mA

Operating ICC1

VFB = COMP = VFFB

–

8.0

13

mA

Operating ICC2

VFB = COMP = VFFB

–

2.0

5.0

mA


VFFB = 1.5 V; VSS = 5.0 V

1.0

1.6

2.2

µs


VSS = VFFB = 0

5.0

8.0

11.0

µs

Discharge Current


5.0

–

–

mA

Time Out Time


10

30

65

µs


VFFB = 0V

35

50

70

%

Time Out Timer


PIN SYMBOL

FUNCTION

1, 2, 3, 4, 6

VID0–VID4

Voltage ID DAC input pins. These pins are internally pulled up to 5.0 V providing logic ones if left open. VID4 selects the DAC range. When VID4 is High (logic one), the DAC range is 2.14 V to 3.54 V with 100 mV increments. When VID4 is Low (logic zero), the DAC range is 1.34 V to 2.09 V with 50 mV increments. VID0 – VID4 select the desired DAC output voltage. Leaving all 5 DAC input pins open results in a DAC output voltage of 1.244 V, allowing for adjustable output voltage, using a traditional resistor divider.

5

SS


7

COFF


8

VFFB


9

VCC2


10

VGATE(H)

11

PGND

12

VGATE(L)

13

VCC1


14

LGND


15

COMP


16

VFB


High FET driver pin capable of 1.5 A peak switching current. Internal circuit prevents VGATE(H) and VGATE(L) from being in high state simultaneously. High current ground for the IC. The MOSFET driver is referenced to this pin. Input capacitor ground and the source of lower FET should be tied to this pin. Low FET driver pin capable of 1.5 A peak switching current.


CS5155H VCC2 VCC1

–


+

–

3.90 V 3.85V

VGATE(H)

SS Low Comparator R

60 µA

Q S FAULT Latch

0.7 V SS +

2.0 µA

VID2

PGnd

FAULT

VCC1

–

VID0 VID1

SS High Comparator

FAULT

Q

+

5 BIT DAC

VID3

Error Amplifier + –

VGATE(L)

2.5 V

PGnd

PWM Comparator

VID4

– VFB


+

Slow Feedback

Fast Feedback

– +

LGnd

1.0 V

S


COMP

VFFB

R

Q

Q PMW Latch


Off–Time Timeout

COFF Q

S

VFFB Low Comparator


PWM COMP

Edge Triggered



PWM Comparator + VGATE(H) C VGATE(L) –

V2 Control Method

The V2 method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the value of the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current.

Ramp Signal

VFFB

VFB


Error Signal


–

E +



Reference Voltage



The CS5155H is designed to provide two methods for programming the output voltage of the power supply. A five bit on board digital to analog converter (DAC) is used to program the output voltage within two different ranges. The first range is 2.14 V to 3.54 V in 100 mV steps, the second is 1.34 V to 2.09 V in 50 mV steps, depending on the digital input code. If all five bits are left open, the CS5155H enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feedback to the VFB and VFFB pins, as in traditional controllers. The CS5155H is specifically designed to be backwards compatible with the CS5150, which uses a four bit DAC code. Start Up


Constant Off Time



CS5155H capacitor charging to its final value. Its voltage is limited by the Soft Start COMP clamp and the voltage on the Soft Start pin (see Figures 4 and 5).


M 250 µs


Trace 1– Regulator Output Voltage (1.0 V/div.) Trace 2– Inductor Switching Node (2.0 V/div.) Trace 3– 12 V Input (VCC1 and VCC2) (5.0 V/div.) Trace 4– 5.0 V Input (1.0 V/div.)

Normal Operation




M 1.00 µs


























Overvoltage protection (OVP) is provided as result of the normal operation of the V2 control topology and requires no additional external components. The control loop responds to an overvoltage condition within 100 ns, causing the top MOSFET to shut off, disconnecting the regulator from it’s input voltage. The bottom MOSFET is then activated, resulting in a “crowbar” action to clamp the output voltage and prevent damage to the load (see Figures 14 and 15 ). The regulator will remain in this state until the overvoltage


CS5155H 5.0 V

condition ceases or the input voltage is pulled low. The bottom FET and board trace must be properly designed to implement the OVP function.


CS5155H 8 V FFB IN4148 Shutdown Input

M 10.0 µs




Trace 2– Inductor Switching Node 5.0 V/div.)

An optional Power Good signal can be generated through the use of four additional external components (see Figure 17). The threshold voltage of the Power Good signal can be adjusted per the following equation:


VPower Good +

(R1 ) R2) 0.65 V R2


CS5155H M 5.00 ms

R1 10 k

PN3904

Power Good

PN3904

R2 6.2 k




External Output Enable Circuit

On/off control of the regulator can be implemented through the addition of two additional discrete components (see Figure 16). This circuit operates by pulling the Soft Start pin high, and the VFFB pin low, emulating a short circuit condition.


CS5155H

M 1.00 µs

M 2.50 ms Trace 3 – 12 V Input (VCC1) and (VCC2) (10 V/div.)

Trace 3 = VGATE(H) (10 V/div.)


Math 1 = VGATE(H) – 5.0 VIN


Trace 4 = VGATE(L) (10 V/div.)








Power + ILOAD2


RDSON

duty cycle

Synchronous MOSFET:

Both logic level and standard MOSFETs can be used. The reference designs derive gate drive from the 12 V supply which is generally available in most computer systems and use logic level MOSFETs. A charge pump may be easily implemented to support 5.0 V or 12 V only systems (maximum of 20 V). Multiple MOSFETs may be paralleled to reduce losses and improve efficiency and thermal management. Voltage applied to the MOSFET gates depends on the application circuit used. Both upper and lower gate driver outputs are specified to drive to within 1.5 V of ground when in the low state and to within 2.0 V of their respective bias supplies when in the high state. In practice, the MOSFET gates will be driven rail to rail due to overshoot caused by the capacitive load they present to the controller IC. For the typical application where VCC1 = VCC2 = 12 V and 5.0 V is used as the source for the regulator output current, the following gate drive is provided;

Power + ILOAD2

RDSON

(1 * duty cycle)


ƪ

RDSON OF SYNCH FET)


ƫ



4848.5


24, 242.5



(see Figure 19.)


CS5155H provide acceptable ripple on the input supply lines and regulator output voltage. Key specifications for input capacitors are their ripple rating, while ESR is important for output capacitors. For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required.


Perioid

(1 * duty cycle) 4848.5

where: Period +

Output Inductor




A Schottky diode may be placed in parallel with the synchronous MOSFET to conduct the inductor current upon turn off of the switching MOSFET to improve efficiency. The CS5155H reference circuit does not use this device due to it’s excellent design. Instead, the body diode of the synchronous MOSFET is utilized to reduce cost and conducts the inductor current. For a design operating at 200 kHz or so, the low non–overlap time combined with Schottky forward recovery time may make the benefits of this device not worth the additional expense (see Figure 8, channel 2). The power dissipation in the synchronous MOSFET due to body diode conduction can be estimated by the following equation: Power + VBD

ILOAD

conduction time

THERMAL MANAGEMENT Thermal Considerations for Power MOSFETs and Diodes



switching frequency

Where VBD = the forward drop of the MOSFET body diode. For the CS5155H demonstration board as shown in Figure 8; Power + 1.6 V

13 A

100 ns


233 kHz + 0.48 W


EMI Management


“Droop” Resistor for Adaptive Voltage Positioning


Adaptive voltage positioning can be disabled for improved DC regulation by connecting the VFB pin directly to the load using a separate, non–load current carrying circuit trace. Input and Output Capacitors

These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to


CS5155H RTRACE + 80 mV IMAX

This causes the output voltage to be +40 mV with no load, and –40 mV with a full load, improving regulator transient response. This trace must be wide enough to carry the full output current. (Typical trace is 1.0 inch long, 0.17 inch wide). Care should be taken to minimize any additional losses after the feedback connection point to maximize regulation. 7. If DC regulation is to be optimized (at the expense of degraded transient regulation), adaptive voltage positioning can be disabled by connecting to VFB pin directly to the load with a separate trace (remote sense). 8. Place 5.0 V input capacitors close to the switching MOSFET and synchronous MOSFET. Route gate drive signals VGATE(H) (pin 10) and VGATE(L) (pin 12 when used) with a trace that are a minimum of 0.025 inches wide.

2.0 µH

33 Ω 1000 pF

Figure 20. Filter Components 2.0 µH + 1200 pF × 3.0/16 V

Figure 21. Input Filter To the negative terminal of the input capacitors

VCC 0.1 µF

Layout Guidelines


15

11

1.0 µF VCOMP

8 5

100 pF VFFB

SOFT START




CS5155H 5.0V MBRS 120

0.1 µF

MBRS120 1.0 µF

MBRS120 1.0 µF

VCC2

VCC1

+


Si4410DY

VGATE(H)

3.0 µH

3.3 V/10 A

VID0 VID1 VID2

Si9410DY

VGATE(L)

VID3

CS5155H

VID4

PGND COFF 330 pF SS 0.1 µF

VFB

COMP

3.3 k VFFB

LGND

+

0.33 µF

100 pF


Figure 23. Additional Application Diagram, 5.0 V to 3.3 V/10 A Converter 3.3 V

12 V

+

1.0 µF VCC1

VCC2

5.0 µH

Si9410

VGATE(H)


2.5 V/7.0 A

VID0 VID1

VFB

VID2

+

VID3 VID4

CS5155H


Si9410

VGATE(L)

COFF

330 pF

SS 0.1 µF

PGND 3.3 k

COMP LGND 0.33 µF

VFFB 100 pF



CS5155H 5.0V MBRS 120

0.1 µF

MBRS120 1.0 µF

MBRS120 1.0 µF

+


VCC1

VCC2

Si4410

VGATE(H)

3.0 µH

3.3 V/10 A

VID0 VID1

VFB

VID2 VID3

10 Ω

100 µF/10 V × 3

+

Tantalum

CS5155H Si9410

VID4

VGATE(L)


PGND

COMP

3.3 k VFFB

LGND


100 pF

0.33 µF

Figure 25. Additional Application Diagram, 5.0 V to 3.3 V/10 A Converter with Current Sharing 12 V 1N5818

12 V 1N5818

22 Ω 1/4 W 1.0 µF

+ 1N4746 18 V 1.0 W

1.0 µF VCC1

VCC2

VID0


0.1 µF FY10AAJ03

VGATE(H)

1.1 µH

3.3 V/5.0 A

VID1 VID2

VFB

VID3 VID4 330 pF

CS5155H

+

COFF

FY10AAJ03

SS 0.1 µF

FY10AAJ03

VGATE(L)

PGND 3.3 k

COMP LGND 0.33 µF


VFFB 100 pF

Figure 26. Additional Application Diagram, 12 V to 3.3 V/5.0 A Converter with Remote Sense



16–SO

Unit

RΘJC

Typical

28

°C/W

RΘJA

Typical

115

°C/W


89 -" 2!&# ! The CS5156H is a 5–bit nonsynchronous N–Channel buck controller. It is designed to provide unprecedented transient response for today’s demanding high–density, high–speed logic. The regulator operates using a proprietary control method, which allows a 100 ns response time to load transients. The CS5156H is designed to operate over a 4.25–20 V range (VCC) using 12 V to power the IC and 5.0 V or 12 V as the main supply for conversion. The CS5156H is specifically designed to power Pentium II processors and other high performance core logic. It includes the following features: on board, 5–bit DAC, short circuit protection, 1.0% output tolerance, VCC monitor, and programmable Soft Start capability. The CS5156H is backwards compatible with the 4–bit CS5151, allowing the mother board designer the capability of using either the CS5151 or the CS5156H with no change in layout. The CS5156H is available in 16 pin surface mount packages. Features N–Channel Design Excess of 1.0 MHz Operation 100 ns Transient Response 5–Bit DAC Backward Compatible with 4–Bit CS5150H/CS5151H 30 ns Gate Rise/Fall Times 1.0% DAC Accuracy 5.0 V & 12 V Operation Remote Sense Programmable Soft Start Lossless Short Circuit Protection VCC Monitor Adaptive Voltage Positioning V2 Control Topology Current Sharing Overvoltage Protection

• • • • • • • • • • • • • • • •




16 1

CS5156H AWLYWW


A WL, L YY, Y WW, W

1


PIN CONNECTIONS 1

16


VFB COMP LGND VCC1 NC PGND VGATE VCC2


2040

Package

Shipping

CS5156HGD16

SO–16

48 Units/Rail

CS5156HGDR16

SO–16

2500 Tape & Reel


CS5156H 5.0 V

12 V

0.1 µF VCC1

VCC2

1200 µF/16 V × 3 AIEI

IRL3103 VGATE

VID0

VID0

VID1

VID1

VID2

VID2

VID3

VID3

VID4

VID4

2.0 µH

2 MBR1535CT

1,3

CS5156H

COFF

330 pF

1.3 V to 3.5 V @ 13 A

PGND

SS 0.1 µF

COMP

VFB 3.3 k

0.33 µF

LGND

VFFB

1200 µF/16 V × 5 AIEI

100 pF



Value

Unit

0 to 150

°C

230 peak

°C

–65 to +150

°C

2.0

kV






Max Current

VCC1

16 V/–0.3 V

25 mA DC/1.5 A peak

VCC2

20 V/–0.3 V

20 mA DC/1.5 A peak

SS

6.0 V/–0.3 V

–100 µA

COMP

6.0 V/–0.3 V

200 µA

VFB

6.0 V/–0.3 V

–0.2 µA

COFF

6.0 V/–0.3 V

–0.2 µA

VFFB

6.0 V/–0.3 V

–0.2 µA

VID0 – VID4

6.0 V/–0.3 V

–50 µA

VGATE

20 V/–0.3 V


LGND

0V

25 mA

PGND

0V



CS5156H ELECTRICAL CHARACTERISTICS (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 20 V; DAC Code: VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit


VFB = 0 V

–

0.3

1.0

µA

Open Loop Gain

1.25 V < VCOMP < 4.0 V; Note 2

50

60

–

dB


Note 2

500

3000

–

kHz

COMP SINK Current

VCOMP = 1.5 V; VFB = 3.0 V; VSS > 2.0 V

0.4

2.5

8.0

mA

COMP SOURCE Current

VCOMP = 1.2 V; VFB = 2.7 V; VSS = 5.0 V

30

50

80

µA

COMP CLAMP Current


0.4

1.0

1.6

mA

COMP High Voltage

VFB = 2.7 V; VSS = 5.0 V

4.0

4.3

5.0

V

COMP Low Voltage

VFB = 3.0 V

–

160

600

mV

PSRR

8.0 V < VCC1 < 14 V @ 1.0 kHz; Note 2

60

85

–

dB


Output switching

3.75

3.90

4.05

V

Stop Threshold


3.70

3.85

4.00

V

Hysteresis

Start–Stop

–

50

–

mV


Measure VCC2 – VGATE

–

1.2

2.0

V


Measure VGATE – VPGND

–

1.0

1.5

V

Out Rise Time

1.0 V < VGATE < 9.0 V; VCC1 = VCC2 = 12 V

–

30

50

ns

Out Fall Time

9.0 V > VGATE > 1.0 V; VCC1 = VCC2 = 12 V

–

30

50

ns


Note 2

–

–

50

mA

VGATE Resistance


20

50

100

kΩ

VGATE Schottky

LGND to VGATE @ 10 mA

–

600

800

mV

VGATE


–

1.6

3.3

5.0

ms

Pulse Period

–

25

100

200

ms

Duty Cycle


1.0

3.3

6.0

%

COMP Clamp Voltage

VFB = 0 V; VSS = 0

0.50

0.95

1.10

V


VGATE = Low

0.9

1.0

1.1

V

–

2.5

3.0

V

High Threshold

–


VFFB = 0 to 5.0 V to VGATE = 9.0 V to 1.0 V; VCC1 = VCC2 = 12 V

–

100

125

ns

VFFB Bias Current

VFFB = 0 V

–

0.3

–

µA



CS5156H ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 20 V; DAC Code: VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

DAC Input Threshold


1.00

1.25

2.40

V



25

50

100

kΩ

4.85

5.00

5.15

V

–

–

1.0

%

Pull Up Voltage

–


Measure VFB = COMP, 25°C ≤ TJ ≤ 125°C

VID4

VID3

VID2

VID1

VID0

0

1

1

1

1

–

1.3266

1.3400

1.3534

V

0

1

1

1

0

–

1.3761

1.3900

1.4039

V

0

1

1

0

1

–

1.4256

1.4400

1.4544

V

0

1

1

0

0

–

1.4751

1.4900

1.5049

V

0

1

0

1

1

–

1.5246

1.5400

1.5554

V

0

1

0

1

0

–

1.5741

1.5900

1.6059

V

0

1

0

0

1

–

1.6236

1.6400

1.6564

V

0

1

0

0

0

–

1.6731

1.6900

1.7069

V

0

0

1

1

1

–

1.7226

1.7400

1.7574

V

0

0

1

1

0

–

1.7721

1.7900

1.8079

V

0

0

1

0

1

–

1.8216

1.8400

1.8584

V

0

0

1

0

0

–

1.8711

1.8900

1.9089

V

0

0

0

1

1

–

1.9206

1.9400

1.9594

V

0

0

0

1

0

–

1.9701

1.9900

2.0099

V

0

0

0

0

1

–

2.0196

2.0400

2.0604

V

0

0

0

0

0

–

2.0691

2.0900

2.1109

V

1

1

1

1

1

–

1.2191

1.2440

1.2689

V

1

1

1

1

0

–

2.1186

2.1400

2.1614

V

1

1

1

0

1

–

2.2176

2.2400

2.2624

V

1

1

1

0

0

–

2.3166

2.3400

2.3634

V

1

1

0

1

1

–

2.4156

2.4400

2.4644

V

1

1

0

1

0

–

2.5146

2.5400

2.5654

V

1

1

0

0

1

–

2.6136

2.6400

2.6664

V

1

1

0

0

0

–

2.7126

2.7400

2.7674

V

1

0

1

1

1

–

2.8116

2.8400

2.8684

V

1

0

1

1

0

–

2.9106

2.9400

2.9694

V

1

0

1

0

1

–

3.0096

3.0400

3.0704

V

1

0

1

0

0

–

3.1086

3.1400

3.1714

V

1

0

0

1

1

–

3.2076

3.2400

3.2724

V

1

0

0

1

0

–

3.3066

3.3400

3.3734

V

1

0

0

0

1

–

3.4056

3.4400

3.4744

V

1

0

0

0

0

–

3.5046

3.5400

3.5754

V


CS5156H ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 20 V; DAC Code: VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

Supply Current ICC1

No Switching

–

8.5

13.5

mA

ICC2

No Switching

–

1.6

3.0

mA

Operating ICC1

VFB = COMP = VFFB

–

8.0

13

mA

Operating ICC2

VFB = COMP = VFFB

–

2.0

5.0

mA


VFFB = 1.5 V; VSS = 5.0 V

1.0

1.6

2.2

µs


VSS = VFFB = 0

5.0

8.0

11.0

µs

Discharge Current


5.0

–

–

mA

Time Out Time

VFB = VCOMP; VFFB = 2.0 V; Record VGATE Pulse High Duration

10

30

65

µs


VFFB = 0V

35

50

70

%

Time Out Timer


PIN SYMBOL

FUNCTION

1, 2, 3, 4, 6

VID0–VID4


5

SS


7

COFF


8

VFFB


9

VCC2

Boosted power for the gate driver.

10

VGATE

MOSFET driver pin capable of 1.5 A peak switching current.

11

PGND

High current ground for the IC. The MOSFET driver is referenced to this pin. Input capacitor ground and the anode of the Schottky diode should be tied to this pin.

12

NC

13

VCC1

Input power for the IC.

14

LGND


15

COMP


16

VFB

No connection.



CS5156H VCC2 VCC1

–


+

–

3.90 V 3.85V

VGATE

SS Low Comparator R

60 µA

SS +

2.0 µA VID0

Q S FAULT Latch

5 BIT DAC

Error Amplifier

2.5 V

PWM Comparator

VID4

– Maximum On–Time Timeout

+

Slow Feedback


COMP

VFFB

PGND

+ –

VID3

VFB

SS High Comparator

FAULT

–

VID1 VID2

Q

+ 0.7 V

FAULT

Fast Feedback

– +

LGND

1.0 V

R

Q

S

Q PMW Latch

GATE = ON GATE = OFF COFF One Shot R

Off–Time Timeout

COFF Q

S

VFFB Low Comparator


PWM COMP

Edge Triggered



PWM Comparator +

V2 Control Method

C


–

Ramp Signal

VGATE

VFFB

VFB


Error Signal


–

E +



Reference Voltage



The CS5156H is designed to provide two methods for programming the output voltage of the power supply. A five bit on board digital to analog converter (DAC) is used to program the output voltage within two different ranges. The first range is 2.14 V to 3.54 V in 100 mV steps, the second is 1.34 V to 2.09 V in 50 mV steps, depending on the digital input code. If all five bits are left open, the CS5156H enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feedback to the VFB and VFFB pins, as in traditional controllers. The CS5156H is specifically designed to be backwards compatible with the CS5151H, which uses a four bit DAC code. Start Up

Until the voltage on the VCC1 supply pin exceeds the 3.9 V monitor threshold, the Soft Start and gate pins are held low. The FAULT latch is reset (no Fault condition). The output of the error amplifier (COMP) is pulled up to 1.0 V by the comparator clamp. When the VCC1 pin exceeds the monitor threshold, the GATE output is activated, and the Soft Start capacitor begins charging. The GATE output will remain on, enabling the NFET switch, until terminated by either the PWM comparator, or the maximum on time timer. If the maximum on time is exceeded before the regulator output voltage achieves the 1.0 V level, the pulse is terminated. The GATE pin drives low for the duration of the extended off time. This time is set by the time out timer and is approximately equal to the maximum on time, resulting in a 50% duty cycle. Then, the GATE pin will drive high, and the cycle repeats. When regulator output voltage achieves the 1.0 V level present at the COMP pin, regulation has been achieved and normal off time will ensue. The PWM comparator terminates the switch on time, with off time set by the COFF capacitor. The V2 control loop will adjust switch duty cycle as required to ensure the regulator output voltage tracks the output of the error amplifier. The Soft Start and COMP capacitors will charge to their final levels, providing a controlled turn on of the regulator output. Regulator turn on time is determined by the COMP capacitor charging to its final value. Its voltage is limited by

Constant Off Time





M 250 µs






Normal Operation




M 1.00 µs
























Overvoltage protection (OVP) is provided as result of the normal operation of the V2 control topology and requires no additional external components. The control loop responds to an overvoltage condition within 100 ns, causing the top MOSFET to shut off, disconnecting the regulator from it’s input voltage. External Output Enable Circuit

On/off control of the regulator can be implemented through the addition of two additional discrete components


CS5156H (see Figure 14). This circuit operates by pulling the Soft Start pin high, and the VFFB pin low, emulating a short circuit condition. 5.0 V

MMUN2111T1 (SOT–23) 5 SS M 2.50 ms

CS5156H 8 V FFB

Trace 3 – 12 V Input (VCC1) and (VCC2) (10 V/div.) Trace 4– 5.0 V Input (2.0 V/div.)

IN4148


Shutdown Input








(R1 ) R2) 0.65 V R2


Both logic level and standard MOSFETs can be used. The reference designs derive gate drive from the 12 V supply which is generally available in most computer systems and use logic level MOSFETs. A charge pump may be easily implemented to permit use of standard MOSFETs or support 5.0 V or 12 V only systems (maximum of 20 V). Multiple MOSFETs may be paralleled to reduce losses and improve efficiency and thermal management. Voltage applied to the MOSFET gates depends on the application circuit used. The gate driver output is specified to drive to within 1.5 V of ground when in the low state and to within 2.0 V of its bias supply when in the high state. In practice, the MOSFET gates will be driven rail to rail due to overshoot caused by the capacitive load they present to the controller IC. For the typical application where VCC1 = VCC2 = 12 V and 5.0 V is used as the source for the regulator output current, the following gate drive is provided;


CS5156H

R1 10 k

PN3904

Power Good

PN3904

R2 6.2 k


VGATE + 12 V * 5.0 V + 7.0 V

(see Figure 17.)


CS5156H “Droop” Resistor for Adaptive Voltage Positioning


M 1.00 µs

Adaptive voltage positioning can be disabled for improved DC regulation by connecting the VFB pin directly to the load using a separate, non–load current carrying circuit trace.

Channel 3 = VGATE M1 = VGATE – 5.0 VIN Channel 2– Inductor Switching Node



The most important aspect of MOSFET performance is RDSON, which effects regulator efficiency and MOSFET thermal management requirements. The power dissipated by the MOSFETs and the Schottky diode may be estimated as follows; Switching MOSFET: Power + ILOAD2

RDSON


duty cycle

Schottky diode: Power + VFORWARD

ILOAD

(1 * duty cycle)

Output Inductor


Duty Cycle = VOUT ) VFORWARD VIN ) VFORWARD * (ILOAD RDSON OF SYNCH FET)


THERMAL MANAGEMENT



4848.5



24, 242.5

Off time will be determined by either the TOFF time, or the time out timer, whichever is longer. The preceding equations for duty cycle can also be used to calculate the regulator switching frequency and select the COFF timing capacitor: COFF +

Perioid

Thermal Impedance +


(1 * duty cycle) 4848.5

where: Period +




CS5156H EMI Management

RTRACE + 80 mV IMAX


This causes the output voltage to be +40 mV with no load, and –40 mV with a full load, improving regulator transient response. This trace must be wide enough to carry the full output current. (Typical trace is 1.0 inch long, 0.17 inch wide). Care should be taken to minimize any additional losses after the feedback connection point to maximize regulation. 7. If DC regulation is to be optimized (at the expense of degraded transient regulation), adaptive voltage positioning can be disabled by connecting to VFB pin directly to the load with a separate trace (remote sense). 8. Place 5.0 V input capacitors close to the switching MOSFET. Route gate drive signals VGATE (pin 10) with a trace that is a minimum of 0.025 inches wide.

2.0 µH


VCC 0.1 µF

33 Ω 1000 pF

15

11

1.0 µF VCOMP


8 +

5

1200 pF × 3.0/16 V

100 pF VFFB

SOFT START

OFF TIME


To the negative terminal of the output capacitors

Layout Guidelines




CS5156H 5.0V

0.1 µF

MBRS120

MBRS 120

1.0 µF

MBRS120 1.0 µF

VCC1

VCC2

+


Si4410DY

VGATE

3.0 µH

3.3 V/10 A

VID0 VID1 VID2 VID3 VID4

2 MBR1535CT

1,3

CS5156H

COFF PGND

330 pF SS

VFB

COMP

0.1 µF

3.3 k LGND


100 pF

0.33 µF

Figure 21. Additional Application Diagram, 5.0 V to 3.3 V/10 A Converter

12 V

3.3 V

1.0 µF + VCC1

VCC2

Si9410

VGATE


VID0

2.5 V/7.0 A

VID1 VID2 VID3 VID4

VFB

CS5156H MBR1535CT

COFF

2 1,3

+


330 pF

SS

PGND

0.1 µF COMP

3.3 k LGND

0.33 µF

VFFB 100 pF



CS5156H 5.0V MBRS 120

0.1 µF

MBRS120

1.0 µF

+

1.0 µF

MBRS120


VCC1

VCC2

Si4410

VGATE

3.0 µH

3.3 V/10 A

VID0 VID1

VFB

VID2 VID3 VID4

2 MBR1535CT

CS5156H

10 Ω

+


1,3

COFF 330 pF

PGND 3.3 k

SS 0.1 µF

VFFB

COMP LGND


100 pF

0.33 µF

Figure 23. Additional Application Diagram, 5.0 V to 3.3 V/10 A Converter with Current Sharing PACKAGE THERMAL DATA Parameter

SO–16

Unit

RΘJC

Typical

28

°C/W

RΘJA

Typical

115

°C/W


89 -" &# ! The CS5161/5161H are 5–bit synchronous dual N–Channel buck controllers designed to provide unprecedented transient response for today’s demanding high–density, high–speed logic. They operate using a proprietary control method which allows a 100 ns response time to load transients. The CS5161 is designed to operate over a 9–16 V range (VCC) using 12 V to power the IC and 5.0 V as the main supply for conversion. The CS5161H operates from a 12 V input as the main supply for conversion using a discrete charge pump circuit to provide up to 20 V for VCC2 and high side gate drive. The CS5161/5161H are specifically designed to power Pentium III processors and other high performance core logic. They include the following features: on board 5–bit DAC, short circuit protection, 1.0% output tolerance, VCC monitor, and programmable Soft Start capability. The CS5161/5161H are available in 16 pin surface mount packages.


MARKING DIAGRAMS 16 SO–16 D SUFFIX CASE 751B

CS5161 AWLYWW 1

A WL, L YY, Y WW, W


PIN CONNECTIONS

Features • Dual N–Channel Design • Excess of 1.0 MHz Operation • 100 ns Transient Response • 5–Bit DAC • Backward Compatible with CS515X Family • 30 ns Gate Rise/Fall Times • 1.0% DAC Accuracy • 5.0 V & 12 V Operation • Remote Sense • Programmable Soft Start • Lossless Short Circuit Protection • VCC Monitor • 50 ns FET Nonoverlap Time • V2 Control Topology • Current Sharing • Overvoltage Protection


http://onsemi.com


VFB COMP LGnd VCC1 VGATE(L) PGnd VGATE(H) VCC2

1


2055

Package

Shipping

CS5161GD16

SO–16

48 Units/Rail

CS5161GDR16

SO–16

2500 Tape & Reel

CS5161HGD16

SO–16

48 Units/Rail

CS5161HGDR16

SO–16

2500 Tape & Reel


CS5161, CS5161H 5V

12 V 1.0 µH

1200 µF/10 V × 6.0 Sanyo GX

0.1 µF

VCC1

SILICONIX SUD50NO3–10P

VCC2 VGATE(H)

1.8 µH

VID0

VID0

VID1

VID1

VID2

VID2

VID3

VID3

VID4

VID4

VOUT

SILICONIX SUD50NO3–07

VGATE(L)

CS5161 MBRS140T3

COFF PGnd

680 pF

SS

VFB

0.1 µF COMP LGnd

1200 µF/10 V × 8.0 Sanyo GX

VFFB

0.33 µF

1.3 k

Figure 1. Application Diagram,5.0 V to 1.5 V/15 A Core Logic Converter with 12 V Bias


Value

Unit

0 to 150

°C

230 peak

°C

–65 to +150

°C

2.0

kV






Max Current

VCC1

16 V/–0.3 V


VCC2 (CS5161)

18 V/–0.3 V


VCC2 (CS5161H)

20 V/–0.3 V


SS

6.0 V/–0.3 V

–100 µA


CS5161, CS5161H MAXIMUM RATINGS (continued) Pin Name


Max Current

COMP

6.0 V/–0.3 V

200 µA

VFB

6.0 V/–0.3 V

–0.2 µA

COFF

6.0 V/–0.3 V

–0.2 µA

VFFB

6.0 V/–0.3 V

–0.2 µA

VID0 – VID4

6.0 V/–0.3 V

–50 µA

VGATE(H) (CS5161)

18 V/–0.3 V


VGATE(H) (CS5161H)

20 V/–0.3 V


VGATE(L)

16 V/–0.3 V


LGnd

0V

25 mA

PGnd

0V


ELECTRICAL CHARACTERISTICS (0°C < TA < +70°C; CS5161: 0°C < TJ < +85°C; CS5161H: 0°C < TJ < +125°C; 9.5 V < VCC1 < 14 V; CS5161: 5.0 V < VCC2 < 16 V; CS5161H: 5.0 V < VCC2 < 20 V; DAC Code: VID4 = VID2 = VID1 = VID0 =1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit


VFB = 0 V

–

0.3

1.0

µA

Open Loop Gain

1.25 V < VCOMP , 4.0 V; CCOMP = 0.1 µF; Note 2

–

80

–

dB


CCOMP = 0.1 µF; Note 2

–

50

–

kHz

COMP SINK Current

VCOMP = 1.5 V; VFB = 3.0 V; VSS > 2.0 V

30

60

120

µA

COMP SOURCE Current

VCOMP = 1.2 V; VFB = 2.7 V; VSS = 5.0 V

15

30

60

µA

COMP CLAMP Current


0.4

1.0

1.6

mA

COMP High Voltage

VFB = 2.7 V; VSS = 5.0 V

4.0

4.3

5.0

V

COMP Low Voltage

VFB = 3.0 V

–

1.0

1.15

V

PSRR

8.0 V < VCC1 < 14 V @ 1.0 kHz; CCOMP = 0.1 µF; Note 2

–

70

–

dB

–

33

–

mmho

Transconductance

–


Output switching

8.70

9.05

9.40

V

Stop Threshold


8.55

8.90

9.25

V

Hysteresis

Start–Stop

–

150

–

mV


–

1.6

3.3

5.0

ms

Pulse Period

–

25

100

200

ms

Duty Cycle


1.0

3.3

6.0

%

COMP Clamp Voltage

VFB = 0 V; VSS = 0

0.50

0.95

1.10

V



0.9

1.0

1.1

V

–

2.5

3.0

V

High Threshold

–



CS5161, CS5161H ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < +70°C; CS5161: 0°C < TJ < +85°C; CS5161H: 0°C < TJ < +125°C; 9.5 V < VCC1 < 14 V; CS5161: 5.0 V < VCC2 < 16 V; CS5161H: 5.0 V < VCC2 < 20 V; DAC Code: VID4 = VID2 = VID1 = VID0 =1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

Transient Response


–

100

125

ns

VFFB Bias Current

VFFB = 0 V

–

0.3

–

µA

PWM Comparator

DAC Input Threshold


1.00

1.25

2.40

V



25

50

110

kΩ

4.85

5.00

5.15

V

–

–

± 1.0

%

Pull Up Voltage

–

Accuracy (all codes except 11111, 10110, 10101, 10100, 10011, 10010, 10001, 10000)

Measure VFB = COMP, CS5161: 25°C ≤ TJ ≤ 85°C CS5161H: 25°C ≤ TJ ≤ 125°C

VID4

VID3

VID2

VID1

VID0

0

1

1

1

1

–

1.2870

1.3000

1.3130

V

0

1

1

1

0

–

1.3365

1.3500

1.3635

V

0

1

1

0

1

–

1.3860

1.4000

1.4140

V

0

1

1

0

0

–

1.4355

1.4500

1.4645

V

0

1

0

1

1

–

1.4850

1.5000

1.5150

V

0

1

0

1

0

–

1.5345

1.5500

1.5655

V

0

1

0

0

1

–

1.5840

1.6000

1.6160

V

0

1

0

0

0

–

1.6335

1.6500

1.6665

V

0

0

1

1

1

–

1.6830

1.7000

1.7170

V

0

0

1

1

0

–

1.7325

1.7500

1.7675

V

0

0

1

0

1

–

1.7820

1.8000

1.8180

V

0

0

1

0

0

–

1.8315

1.8500

1.8685

V

0

0

0

1

1

–

1.8810

1.9000

1.9190

V

0

0

0

1

0

–

1.9305

1.9500

1.9695

V

0

0

0

0

1

–

1.9800

2.0000

2.0200

V

0

0

0

0

0

–

2.0295

2.0500

2.0705

V

1

1

1

1

1

–

1.2191

1.2440

1.2689

V

1

1

1

1

0

–

2.0790

2.1000

2.1210

V

1

1

1

0

1

–

2.1780

2.2000

2.2220

V

1

1

1

0

0

–

2.2770

2.3000

2.3230

V

1

1

0

1

1

–

2.3760

2.4000

2.4240

V

1

1

0

1

0

–

2.4750

2.5000

2.5250

V

1

1

0

0

1

–

2.5740

2.6000

2.6260

V

1

1

0

0

0

–

2.6730

2.7000

2.7270

V

1

0

1

1

1

–

2.7720

2.8000

2.8280

V

1

0

1

1

0

–

2.8420

2.9000

2.9580

V

1

0

1

0

1

–

2.9400

3.0000

3.0600

V


CS5161, CS5161H ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < +70°C; CS5161: 0°C < TJ < +85°C; CS5161H: 0°C < TJ < +125°C; 9.5 V < VCC1 < 14 V; CS5161: 5.0 V < VCC2 < 16 V; CS5161H: 5.0 V < VCC2 < 20 V; DAC Code: VID4 = VID2 = VID1 = VID0 =1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

DAC 1

0

1

0

0

–

3.0380

3.1000

3.1620

V

1

0

0

1

1

–

3.1360

3.2000

3.2640

V

1

0

0

1

0

–

3.2340

3.3000

3.3660

V

1

0

0

0

1

–

3.3320

3.4000

3.4680

V

1

0

0

0

0

–

3.4300

3.5000

3.5700

V

VGATE(H) and VGATE(L) Out SOURCE Sat at 100 mA


–

1.2

2.0

V


Measure VGATE(H) – VPGnd; VGATE(L) – VPGnd

–

1.0

1.5

V

Out Rise Time


–

30

50

ns

Out Fall Time

9.0 V < VGATE(H) > 1.0 V; 9.0 V > VGATE(L) > 1.0 V; VCC1 = VCC2 = 12 V

–

30

50

ns


VGATE(H) falling to 2.0 V; VCC1 = VCC2 = 8.0 V VGATE(L) rising to 2.0 V

20

50

90

ns


VGATE(L) falling to 2.0 V; VCC1 = VCC2 = 8.0 V VGATE(H) rising to 2.0 V

20

50

90

ns


Resistor to LGnd. Note 3

20

50

100

kΩ


LGnd to VGATE(H) @ 10 mA; LGnd to VGATE(L) @ 10 mA

–

600

800

mV

Supply Current ICC1 No Switching

–

–

9.5

14.5

mA

ICC2 No Switching

–

–

2.0

3.5

mA

Operating ICC1

VFB = COMP = VFFB

–

9.0

14

mA

Operating ICC2

VFB = COMP = VFFB

–

2.5

5.5

mA


VFFB = 1.5 V; VSS = 5.0 V

1.0

1.6

2.2

µs

Discharge Current


5.0

–

–

mA

Time Out Time


10

30

65

µs


VFFB = 0V

35

50

70

%

Time Out Timer



CS5161, CS5161H PACKAGE PIN DESCRIPTION PACKAGE PIN #

PIN SYMBOL

FUNCTION

1, 2, 3, 4, 6

VID0–VID4


5

SS

Soft Start Pin. A capacitor from this pin to LGnd in conjunction with internal 60 µA current source provides Soft Start function for the controller. This pin disables fault detect function during Soft Start. When a fault is detected, the Soft Start capacitor is slowly discharged by internal 2.0 µA current source setting the time out before trying to restart the IC. Charge/discharge current ratio of 30 sets the duty cycle for the IC when the regulator output is shorted.

7

COFF


8

VFFB


9

VCC2


10

VGATE(H)

High FET driver pin capable of 1.5 A peak switching current. Internal circuit prevents VGATE(H) and VGATE(L) from being in high state simultaneously.

11

PGnd

High current ground for the IC. The MOSFET drivers are referenced to this pin. Input capacitor ground and the source of lower FET should be tied to this pin.

12

VGATE(L)

Low FET driver pin capable of 1.5 A peak switching current.

13

VCC1


14

LGnd


15

COMP


16

VFB

16 Lead SO Narrow



CS5161, CS5161H VCC2 VCC1

–


+

–

9.05 V 8.90V

VGATE(H)

SS Low Comparator R

60 µA

Q S FAULT Latch

0.7 V SS +

2.0 µA

VID2

PGnd

FAULT

VCC1

–

VID0 VID1

SS High Comparator

FAULT

Q

+

5 BIT DAC

VID3


VGATE(L)

2.5 V

PGnd

PWM Comparator

VID4

– VFB


+

Slow Feedback


COMP

VFFB

Fast Feedback

– +

LGnd

1.0 V

R

Q

S

Q PMW Latch


Off–Time Timeout

COFF Q

S

VFFB Low Comparator


Edge Triggered



PWM Comparator + VGATE(H) C VGATE(L)

V2 Control Method


–

Ramp Signal

VFFB

VFB


Error Signal


–

E +



Reference Voltage

CS5161, CS5161H The V2 control method is illustrated in Figure 3. The output voltage is used to generate both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. A change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the V2 control scheme to compensate the duty cycle. Since the change in inductor current modifies the ramp signal, as in current mode control, the V2 control scheme has the same advantages in line transient response. A change in load current will have an affect on the output voltage, altering the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. Load transient response is determined only by the comparator response time and the transition speed of the main switch. The reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. The error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. The main purpose of this ‘slow’ feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. Line and load regulation are drastically improved because there are two independent voltage loops. A voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. The V2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load.


The CS5161/5161H is designed to provide two methods for programming the output voltage of the power supply. A five bit on board digital to analog converter (DAC) is used to program the output voltage within two different ranges. The first range is 2.10 V to 3.50 V in 100 mV steps, the second is 1.30 V to 2.05 V in 50 mV steps, depending on the digital input code. If all five bits are left open, the CS5161/5161H enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feedback to the VFB and VFFB pins, as in traditional controllers. Start Up


Constant Off Time

To maximize transient response, the CS5161/5161H uses a constant off time method to control the rate of output pulses. During normal operation, the off time of the high side switch is terminated after a fixed period, set by the COFF capacitor. To maintain regulation, the V2 control loop varies switch on time. The PWM comparator monitors the output voltage ramp, and terminates the switch on time.


CS5161, CS5161H capacitor charging to its final value. Its voltage is limited by the Soft Start COMP clamp and the voltage on the Soft Start pin (see Figures 4 and 5).


M 250 µs

Figure 6. CS5161/5161H Enable Startup Waveforms


Normal Operation



Figure 4. CS5161/5161H Startup in Response to Increasing 12 V and 5.0 V Input Voltages. Extended Off Time is Followed by Normal Off Time Operation when Output Voltage Achieves Regulation to the Error Amplifier Output.

M 2.50 ms Trace 1– Regulator Output Voltage (1.0 V/div.) Trace 3– COMP PIn (error amplifier output) (1.0 V/div.)

M 1.00 µs

Trace 4– Soft Start Pin (2.0 V/div.)

Figure 5. CS5161/5161H Startup Waveforms




Figure 7. CS5161/5161H Peak–to–Peak Ripple on VOUT = 2.8 V, IOUT = 0.5 A (Light Load)


CS5161, CS5161H

10 µs/div.

M 1.00 µs

Trace 1– Inductor Switching Node (5.0 V/div.) Trace 2– Regulator Output Voltage (output set for 1.55 V, 20 mV/div.)


Figure 10. CS5161/5161H Pentium III Converter Output Voltage Response to a 0 to 12 A Load Increase


Figure 8. CS5161/5161H Peak–to–Peak Ripple on VOUT = 2.8 V, IOUT = 13 A (Heavy Load) Transient Response

The CS5161/5161H V2 control loop’s 100 ns reaction time provides unprecedented transient response to changes in input voltage or output current. Pulse by pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. For best transient response, a combination of a number of high frequency and bulk output capacitors are usually used. If the maximum on time is exceeded while responding to a sudden increase in load current, a normal off time occurs to prevent saturation of the output inductor.

Trace 1– Inductor Switching Node (5 V/div.)

10 µs/div.

Trace 2– Regulator Output Voltage (output set for 1.55 V, 20 mV/div.)

Figure 11. CS5161/5161H Pentium III Converter Output Voltage Response to a 12 to 0 A Load Decrease


To maintain predictable startup and shutdown characteristics an internal VCC1 monitor circuit is used to prevent the part from operating below 8.70 V minimum startup. The VCC1 monitor comparator provides hysteresis and guarantees a 8.55 V minimum shutdown threshold. Short Circuit Protection 100 µs/div.

A lossless hiccup mode short circuit protection feature is provided, requiring only the Soft Start capacitor to implement. If a short circuit condition occurs (VFFB < 1.0 V), the VFFB low comparator sets the FAULT

Trace 2– Regulator Output Voltage (output set for 1.55 V, 20 mV/div.)

Figure 9. CS5161/5161H Pentium III Converter Output Voltage Response to a 12 A Load Pulse.


CS5161, CS5161H latch. This causes the top MOSFET to shut off, disconnecting the regulator from it’s input voltage. The Soft Start capacitor is then slowly discharged by a 2.0 µA current source until it reaches it’s lower 0.7 V threshold. The regulator will then attempt to restart normally, operating in it’s extended off time mode with a 50% duty cycle, while the Soft Start capacitor is charged with a 60 µA charge current. If the short circuit condition persists, the regulator output will not achieve the 1.0 V low VFFB comparator threshold before the Soft Start capacitor is charged to it’s upper 2.5 V threshold. If this happens the cycle will repeat itself until the short is removed. The Soft Start charge/discharge current ratio sets the duty cycle for the pulses (2.0 µA/60 µA = 3.3%), while actual duty cycle is half that due to the extended off time mode (1.65%). This protection feature results in less stress to the regulator components, input power supply, and PC board traces than occurs with constant current limit protection (see Figures 12 and 13). If the short circuit condition is removed, output voltage will rise above the 1.0 V level, preventing the FAULT latch from being set, allowing normal operation to resume.


Figure 13. CS5161/5161H Startup with Regulator Output Shorted Overvoltage Protection

Overvoltage protection (OVP) is provided as result of the normal operation of the V2 control topology and requires no additional external components. The control loop responds to an overvoltage condition within 100 ns, causing the top MOSFET to shut off, disconnecting the regulator from it’s input voltage. The bottom MOSFET is then activated, resulting in a “crowbar” action to clamp the output voltage and prevent damage to the load (see Figures 14 and 15). The regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. The bottom FET and board trace must be properly designed to implement the OVP function.


Figure 12. CS5161/5161H Hiccup Mode Short Circuit Protection. Gate Pulses are Delivered While the Soft Start Capacitor Charges, and Cease During Discharge M 10.0 µs Trace 4– 5.0 V from PC Power Supply (5.0 V/div.) Trace 1– Regulator Output Voltage (1.0 V/div.) Trace 2– Inductor Switching Node 5.0 V/div.)

Figure 14. CS5161/5161H OVP Response to an Input–to–Output Short Circuit by Immediately Providing 0% Duty Cycle, Crow–Barring the Input Voltage to Ground


CS5161, CS5161H 5.0 V R3 10 k VOUT

R1 10 k

CS5161

PN3904

Power Good

PN3904

R2 6.2 k

Figure 17. Implementing Power Good with the CS5161/5161H M 5.00 ms Trace 4– 5.0 V from PC Power Supply (5.0 V/div.) Trace 1– Regulator Output Voltage (1.0 V/div.)

Figure 15. CS5161/5161H OVP Response to an Input–to–Output Short Circuit by Pulling the Input Voltage to Ground External Output Enable Circuit

On/off control of the regulator can be implemented through the addition of two additional discrete components (see Figure 16). This circuit operates by pulling the Soft Start pin high, and the VFFB pin low, emulating a short circuit condition. M 2.50 ms 5.0 V

Trace 3 – 12 V Input (VCC1) and (VCC2) (10 V/div.) Trace 4– 5.0 V Input (2.0 V/div.) Trace 1– Regulator Output Voltage (1.0 V/div.) Trace 2– Power Good Signal (2.0 V/div.)

Figure 18. CS5161/5161H During Power Up. Power Good Signal is Activated when Output Voltage Reaches 1.70 V.


Slope Compensation

The V2 control method uses a ramp signal, generated by the ESR of the output capacitors, that is proportional to the ripple current through the inductor. To maintain regulation, the V2 control loop monitors this ramp signal, through the PWM comparator, and terminates the switch on–time. The stringent load transient requirements of modern microprocessors require the output capacitors to have very low ESR. The resulting shallow slope presented to the PWM comparator, due to the very low ESR, can lead to pulse width jitter and variation caused by both random or synchronous noise. Adding slope compensation to the control loop, avoids erratic operation of the PWM circuit, particularly at lower duty cycles and higher frequencies, where there is not enough ramp signal, and provides a more stable switchpoint. The scheme that prevents that switching noise prematurely triggers the PWM circuit consists of adding a positive voltage slope to the output of the Error Amplifier (COMP pin) during an off–time cycle.

CS5161 8 V FFB IN4148 Shutdown Input

Figure 16. Implementing Shutdown with the CS5161/5161H External Power Good Circuit


(R1 ) R2) 0.65 V R2

This circuit provides an open collector output that drives the Power Good output to ground for regulator voltages less than VPower Good.


CS5161, CS5161H The circuit that implements this function is shown in Figure 19. 16 COMP CCOMP

CS5161 VOUT

R2

C1

R1

12 GATE(L)

To Synchronous FET M 1.00 µs

Figure 19. Small RC Filter Provides the Proper Voltage Ramp at the Beginning of each On–Time Cycle

Trace 3 = VGATE(H) (10 V/div.) Math 1 = VGATE(H) – 5.0 VIN Trace 4 = VGATE(L) (10 V/div.)

The ramp waveform is generated through a small RC filter that provides the proper voltage ramp at the beginning of each on–time cycle. The resistors R1 and R2 in the circuit of Figure 14 form a voltage divider from the GATE(L) output, superimposing a small artificial ramp on the output of the error amplifier. It is important that the series combination R1/R2 is high enough in resistance not to load down and negatively affect the slew rate on the GATE(L) pin.


Figure 20. CS5161/5161H Gate Drive Waveforms Depicting Rail to Rail Swing



The CS5161/5161H can be used with a wide range of external power components to optimize the cost and performance of a particular design. The following information can be used as general guidelines to assist in their selection.

Power + ILOAD2

RDSON

duty cycle

Synchronous MOSFET: Power + ILOAD2

RDSON

(1 * duty cycle)

Duty Cycle = NFET Power Transistors

VOUT ) (ILOAD

Both logic level and standard MOSFETs can be used. The reference designs derive gate drive from the 12 V supply which is generally available in most computer systems and utilize logic level MOSFETs. Multiple MOSFETs may be paralleled to reduce losses and improve efficiency and thermal management. Voltage applied to the MOSFET gates depends on the application circuit used. Both upper and lower gate driver outputs are specified to drive to within 1.5 V of ground when in the low state and to within 2.0 V of their respective bias supplies when in the high state. In practice, the MOSFET gates will be driven rail to rail due to overshoot caused by the capacitive load they present to the controller IC. For the typical application where VCC1 = VCC2 = 12 V and 5.0 V is used as the source for the regulator output current, the following gate drive is provided;

ƪ

RDSON OF SYNCH FET)


ƫ



4848.5


Perioid

(1 * duty cycle) 4848.5

where: Period +


(see Figure 20.)



CS5161, CS5161H Schottky Diode for Synchronous MOSFET


A Schottky diode may be placed in parallel with the synchronous MOSFET to conduct the inductor current upon turn off of the switching MOSFET to improve efficiency. For a design operating at 200 kHz or so, the low non–overlap time combined with Schottky forward recovery time may make the benefits of this device not worth the additional expense (see Figure 8, channel 2). The power dissipation in the synchronous MOSFET due to body diode conduction can be estimated by the following equation: Power + VBD

ILOAD

conduction time

EMI Management


switching frequency

Where VBD = the forward drop of the MOSFET body diode. For the CS5161/5161H demonstration board as shown in Figure 8; Power + 1.6 V

13 A

100 ns

233 kHz + 0.48 W

This is only 1.3% of the 36.4 W being delivered to the load. Input and Output Capacitors


2.0 µH

33 Ω 1000 pF

Output Inductor



THERMAL MANAGEMENT +


1200 pF × 3.0/16 V





CS5161, CS5161H Layout Guidelines


VCC 0.1 µF

1. Place 12 V filter capacitor next to the IC and connect capacitor ground to pin 11 (PGnd). 2. Connect pin 11 (PGnd) with a separate trace to the ground terminals of the 5.0 V input capacitors. 3. Place fast feedback filter capacitor next to pin 8 (VFFB) and connect it’s ground terminal with a separate, wide trace directly to pin 14 (LGnd). 4. Connect the ground terminals of the Compensation capacitor directly to the ground of the fast feedback filter capacitor to prevent common mode noise from effecting the PWM comparator. 5. Place the output filter capacitor(s) as close to the load as possible and connect the ground terminal to pin 14 (LGnd). 6. Connect the VFB pin directly to the load with a separate trace (remote sense). 7. Place 5.0 V input capacitors close to the switching MOSFET and synchronous MOSFET. Route gate drive signals VGATE(H) (pin 10) and VGATE(L) (pin 12 when used) with traces that are a minimum of 0.025 inches wide.

15

11

1.0 µF VCOMP

8 5

100 pF VFFB

SOFT START




CS5161, CS5161H ADDITIONAL APPLICATION DIAGRAMS 12 V MBRS 120

0.1 µF

MBRS120 1.0 µF

MBRS120

+

100 µF/10 V × 3.0 Tantalum Remote Sense

1.0 µF

VCC1

VCC2

Si4410

VGATE(H)

3.0 µH

3.3 V/10 A

VID0 VID1

VFB

VID2

+ 100 µF/10 V × 3.0 Tantalum

10 Ω

VID3

CS5161

VID4

Si9410 VGATE(L)

COFF MBRS140T3

300 pF SS 0.1 µF

PGnd

COMP

3.3 k LGnd

VFFB

033 µF


100 pF

Figure 24. 12 V to 3.3 V/10 A Converter with Remote Sense and Current Sharing

3.3 V

12 V

33 µF/25 V × 3.0 Tantalum

1.0 µF VCC1

VCC2

5.0 µH

Si9410

VGATE(H)

2.5 V/7.0 A

VID0 VID1

VGATE(L)

VID2

100 µF/10 V × 2.0 Tantalum

VID3 VID4

CS5161

Si9410 PGnd

COFF

330 pF

MBRS140T3 SS

0.1 µF

VFB 3.3 k

COMP LGnd 0.33 µF

VFFB 100 pF

Figure 25. 3.3 V to 2.5 V/7.0 A Converter with 12 V Bias. http://onsemi.com 2070

CS5161, CS5161H ADDITIONAL APPLICATION DIAGRAMS 5.0 V 1.0 µH

12 V

0.1 µF VCC1

VCC2 VGATE(H)

VID0

VID0

VID1

VID1

VID2

VID2

VID3

VID3

VID4

VID4

1200 µF/10 V × 6.0 Sanyo GX

SILICONIX SUD50NO3–10P

1.8 µH

SILICONIX SUD50NO3–07

VGATE(L)

10 k

CS5161

VOUT

30 nF

MBRS140T3

COFF 680 pF

PGnd

SS

VFB

0.1 µF COMP LGnd

500 k

VFFB

1200 µF/10 V × 8.0 Sanyo GX

1.0 µF

00.1 µF

10 k 100

Figure 26. PentiumIII Converter with Slope Compensation and Adaptive Voltage Positioning PACKAGE THERMAL DATA 16 Lead SO Narrow

Unit

RΘJC

Typical

28

°C/W

RΘJA

Typical

115

°C/W

Parameter


-" &# ! 89 The CS5156H synchronous 5–bit NFET buck controller is optimized to manage the power of the next generation Pentium II processors. It’s V2 control architecture delivers the fastest transient response (100 ns), and best overall voltage regulation in the industry today. It’s feature rich design gives end users the maximum flexibility to implement the best price/performance solutions for their end products. The CS5156H has been carefully crafted to maximize performance and protect the processor during operation. It has a 5–bit DAC on board that holds a ±1.0% tolerance over temperature. Its on board programmable Soft Start insures a control start up, and the FET nonoverlap circuitry ensures that both FETs do not conduct simultaneously. The on board oscillator can be programmed up to 1.0 MHz to give the designer maximum flexibility in choosing external components and setting systems costs. The CS5156H protects the processor during potentially catastrophic events like overvoltage (OVP) and short circuit. The OVP feature is part of the V2 architecture and does not require any additional components. During short circuit, the controller pulses the MOSFETs in a “hiccup” mode (3.0% duty cycle) until the fault is removed. With this method, the MOSFETs do not overheat or self destruct. The CS5156H is designed for use in both single processor desktop and multiprocessor workstation and server applications. The IC can be powered from either single or dual 5.0 V, 12 V power supplies. The CS5156H’s current sharing capability allows the designer to build multiple parallel and redundant power solutions for multiprocessor systems. The CS5156H contains other control and protection features such as Power Good, ENABLE, and adaptive voltage positioning. It is available in a 16 lead SOIC wide body package. Features • V2 Control Topology • 100 ns Controller Transient Response • Excess of 1.0 MHz Operation • 5–Bit DAC with 1.0% Tolerance • Power Good Output With Internal Delay • Enable Input Provides Micropower Shutdown Mode • 5.0 V & 12 V Operation Using Either Dual or Single Supplies • Adaptive Voltage Positioning • Remote Sense Capability • Current Sharing Capability • VCC Monitor • Hiccup Mode Short Circuit Protection • Overvoltage Protection (OVP) • Programmable Soft Start • 150 ns PWM Blanking • 65 ns FET Nonoverlap Time • 40 ns Gate Rise and Fall Times (3.3 nF Load)  Semiconductor Components Industries, LLC, 2001


2072


16 1

CS5165H


AWLYYWW



PIN CONNECTIONS 1

16 VFB COMP LGND PWRGD GATE(L) PGND GATE(H) VCC

VID0 VID1 VID2 VID3 SS VID4 COFF ENABLE


Package

Shipping

CS5165HGDW16

SO–16L

46 Units/Rail

CS5165HGDWR16

SO–16L

1000 Tape & Reel


CS5165H 12 V

5.0 V 1200 µF/10 V × 3

1.0 µF

IRL3103 0.1 µF

0.1 µF

330 pF

VCC

SS COMP COFF

1.2 µH

VCC

GATE(H)

1200 µF/10 V × 5

GATE(L)

VSS

VID4

IRL3103

PWRGD

PGND

VID3

ENABLE

LGND

VID2

CS5156H

VID1 VID0

PCB trace 6.0 mΩ

VID0

3.3 k

VID1

VFB 1000 pF

Pentium II System

VID2

PWRGD

VID3

ENABLE

VID4

Figure 1. Application Diagram, 5.0 V to 2.8 V @ 14.2 A for 300 MHz Pentium II

ABSOLUTE MAXIMUM RATINGS* Rating Operating Junction Temperature, TJ Lead Temperature Soldering:




Value

Unit

0 to 150

°C

230 peak

°C

–65 to +150

°C

2.0

kV

CS5165H ABSOLUTE MAXIMUM RATINGS Pin Name

Pin Symbol

VMAX

VMIN

ISOURCE

ISINK

IC Power Input

VCC

20 V

–0.3 V

N/A

1.5 A peak, 200 mA DC

Soft Start Capacitor

SS

6.0 V

–0.3 V

200 µA

10 µA


COMP

6.0 V

–0.3 V

10 mA

1.0 mA


VFB

6.0 V

–0.3 V

10 µA

10 µA

Off–Time Capacitor

COFF

6.0 V

–0.3 V

1.0 mA

50 mA

Voltage ID DAC Inputs

VID0–VID4

6.0 V

–0.3 V

1.0 mA

10 µA


GATE(H)

20 V

–0.3 V




GATE(L)

20 V

–0.3 V



Enable Input

ENABLE

6.0 V

–0.3 V

100 µA

1.0 mA

Power Good Output

PWRGD

6.0 V

–0.3 V

10 µA

30 mA

Power Ground

PGND

0V

0V


N/A

Logic Ground

LGND

0V

0V

100 mA

N/A

ELECTRICAL CHARACTERISTICS (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC < 20 V; 2.8 DAC Code: (VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0); CGATE(H) and CGATE(L) = 3.3 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit

–

12

20

mA

VCC Supply Current Operating

1.0 V < VFB < VDAC (max on–time) No Loads on GATE(H) and GATE(L)

VCC Monitor Start Threshold

GATE(H) switching

3.75

3.95

4.15

V

Stop Threshold

GATE(H) not switching

3.65

3.87

4.05

V

Hysteresis

Start–Stop

–

80

–

mV

VFB Bias Current

VFB = 0 V

–

0.1

1.0

µA

COMP Source Current

COMP = 1.2 V to 3.6 V; VFB = 2.7 V

15

30

60

µA

COMP CLAMP Voltage

VFB = 2.7 V, Adjust COMP voltage for Comp current = 50 µA

0.85

1.0

1.15

V

COMP Clamp Current

COMP = 0 V

0.4

1.0

1.6

mA

COMP Sink Current

VCOMP = 1.2 V; VFB = 3.0 V; VSS > 2.5 V

180

400

800

µA

Open Loop Gain

Note 2

50

60

–

dB


Note 2

0.5

2.0

–

MHz

PSRR @ 1.0 kHz

Note 2

60

85

–

dB

Error Amplifier



CS5165H ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC < 20 V; 2.8 DAC Code: (VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0); CGATE(H) and CGATE(L) = 3.3 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

GATE(H) and GATE(L) High Voltage at 100 mA

Measure VCC – GATE

–

1.2

2.0

V

Low Voltage at 100 mA

Measure GATE

–

1.0

1.5

V

Rise Time

1.6 V < GATE < (VCC – 2.5 V), 8 V < VCC < 14 V

–

40

80

ns

Fall Time

(VCC – 2.5 V) > GATE > 1.6 V, 8 V < VCC < 14 V

–

40

80

ns


GATE(H) < 2.0 V; GATE(L) > 2.0 V, 8.0 V < VCC < 14 V

30

65

100

ns


GATE(L) < 2.0 V; GATE(H) > 2.0 V, 8.0 V < VCC < 14 V

30

65

100

ns

GATE pull–down

Resistor to PGND, Note 3

20

50

115

kΩ

SS Charge Time

VFB = 0 V

1.6

3.3

5.0

ms

SS Pulse Period

VFB = 0 V

25

100

200

ms

SS Duty Cycle

(Charge Time/Period) × 100

1.0

3.3

6.0

%

SS COMP Clamp Voltage

VFB = 2.7 V; VSS = 0 V

0.50

0.95

1.10

V

VFB Low Comparator

Increase VFB till no SS pulsing and normal Off–time

0.9

1.0

1.1

V

Transient Response

VFB = 1.2 to 5.0 V. 500 ns after GATE(H) (after Blanking time) to GATE(H) = (VCC –1.0 V) to 1.0 V, 8.0 V < VCC < 14 V

–

100

150

ns

Minimum Pulse Width (Blanking Time)

Drive VFB. 1.2 to 5.0 V upon GATE(H) rising edge (> VCC – 1.0 V), measure GATE(H) pulse width, 8.0 V < VCC < 14 V

50

150

250

ns

Normal Off–Time

VFB = 2.7 V

1.0

1.6

2.3

µs

Extended Off–Time

VSS = VFB = 0 V

5.0

8.0

12.0

µs

Time–Out Time

VFB = 2.7 V, Measure GATE(H) Pulse Width

10

30

50

µs

Fault Duty Cycle

VFB = 0V

30

50

70

%

ENABLE Threshold

GATE(H) Switching

0.8

1.15

1.30

V

Shutdown delay (Note 3)

ENABLE–to–GATE(H) < 2.0 V

–

3.0

–

µs

Pull–up Current

ENABLE = 0 V

3.0

7.0

15

µA

Pull–up Voltage

No load on ENABLE pin

1.30

1.8

3.0

V

Input Resistance

ENABLE = 5.0 V, R = (5.0 V – VPULLUP)/IENABLE

10

20

50

kΩ

Low to High Delay

VFB = (0.8 × VDAC) to VDAC

30

65

110

µs

High to Low Delay

VFB = VDAC to (0.8 × VDAC)

30

75

120

µs

Output Low Voltage

VFB = 2.4 V, IPWRGD = 500 µA

–

0.2

0.3

V

Sink Current Limit

VFB = 2.4 V, PWRGD = 1.0 V

0.5

4.0

15.0

mA

Fault Protection

PWM Comparator

COFF

Time–Out Timer

Enable Input

Power Good Output



CS5165H ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC < 20 V; 2.8 DAC Code: (VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0); CGATE(H) and CGATE(L) = 3.3 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

–1.0

–

+1.0

%

Voltage Identification DAC Accuracy (all codes except 11111)

Measure VFB = COMP (COFF = 0 V) 25°C ≤ TJ ≤ 125°C; VCC = 12 V

VID4

VID3

VID2

VID1

VID0

1

0

0

0

0

–

3.505

3.540

3.575

V

1

0

0

0

1

–

3.406

3.440

3.474

V

1

0

0

1

0

–

3.307

3.340

3.373

V

1

0

0

1

1

–

3.208

3.240

3.272

V

1

0

1

0

0

–

3.109

3.140

3.171

V

1

0

1

0

1

–

3.010

3.040

3.070

V

1

0

1

1

0

–

2.911

2.940

2.969

V

1

0

1

1

1

–

2.812

2.840

2.868

V

1

1

0

0

0

–

2.713

2.740

2.767

V

1

1

0

0

1

–

2.614

2.640

2.666

V

1

1

0

1

0

–

2.515

2.540

2.565

V

1

1

0

1

1

–

2.416

2.440

2.464

V

1

1

1

0

0

–

2.317

2.340

2.363

V

1

1

1

0

1

–

2.218

2.240

2.262

V

1

1

1

1

0

–

2.119

2.140

2.161

V

0

0

0

0

0

–

2.069

2.090

2.111

V

0

0

0

0

1

–

2.020

2.040

2.060

V

0

0

0

1

0

–

1.970

1.990

2.010

V

0

0

0

1

1

–

1.921

1.940

1.959

V

0

0

1

0

0

–

1.871

1.890

1.909

V

0

0

1

0

1

–

1.822

1.840

1.858

V

0

0

1

1

0

–

1.772

1.790

1.808

V

0

0

1

1

1

–

1.723

1.740

1.757

V

0

1

0

0

0

–

1.673

1.690

1.707

V

0

1

0

0

1

–

1.624

1.640

1.656

V

0

1

0

1

0

–

1.574

1.590

1.606

V

0

1

0

1

1

–

1.525

1.540

1.555

V

0

1

1

0

0

–

1.475

1.490

1.505

V

0

1

1

0

1

–

1.426

1.440

1.455

V

0

1

1

1

0

–

1.376

1.390

1.405

V

0

1

1

1

1

–

1.327

1.340

1.353

V

1

1

1

1

1

–

1.223

1.247

1.273

V

Input Threshold


1.000

1.250

2.400

V

Input Pull–up Resistance


25

50

100

kΩ

4.85

5.00

5.15

V

Input Pull–up Voltage


CS5165H ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC < 14 V; 2.8 DAC Code: (VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0); CGATE(H) and CGATE(L) = 3.3 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Lower Threshold Threshold Accuracy Acc racy

Min

Typ

–12

–8.5

Upper Threshold Max

Min

Typ

Max

Unit

–5.0

5.0

8.5

12

%

DAC CODE % of Nominal DAC Output VID4

VID3

VID2

VID1

VID0

1

0

0

0

0

3.115

3.239

3.363

3.717

3.841

3.965

V

1

0

0

0

1

3.027

3.148

3.268

3.612

3.732

3.853

V

1

0

0

1

0

2.939

3.056

3.173

3.507

3.624

3.741

V

1

0

0

1

1

2.851

2.965

3.078

3.402

3.515

3.629

V

1

0

1

0

0

2.763

2.873

2.983

3.297

3.407

3.517

V

1

0

1

0

1

2.675

2.782

2.888

3.192

3.298

3.405

V

1

0

1

1

0

2.587

2.690

2.793

3.087

3.190

3.293

V

1

0

1

1

1

2.499

2.599

2.698

2.982

3.081

3.181

V

1

1

0

0

0

2.411

2.507

2.603

2.877

2.973

3.069

V

1

1

0

0

1

2.323

2.416

2.508

2.772

2.864

2.957

V

1

1

0

1

0

2.235

2.324

2.413

2.667

2.756

2.845

V

1

1

0

1

1

2.147

2.233

2.318

2.562

2.647

2.733

V

1

1

1

0

0

2.059

2.141

2.223

2.457

2.539

2.621

V

1

1

1

0

1

1.971

2.050

2.128

2.352

2.430

2.509

V

1

1

1

1

0

1.883

1.958

2.033

2.250

2.322

2.397

V

0

0

0

0

0

1.839

1.912

1.986

2.195

2.268

2.341

V

0

0

0

0

1

1.795

1.867

1.938

2.142

2.213

2.285

V

0

0

0

1

0

1.751

1.821

1.810

2.090

2.159

2.229

V

0

0

0

1

1

1.707

1.775

1.843

2.037

2.105

2.173

V

0

0

1

0

0

1.663

1.729

1.796

1.985

2.051

2.117

V

0

0

1

0

1

1.619

1.684

1.748

1.932

1.996

2.061

V

0

0

1

1

0

1.575

1.638

1.701

1.880

1.942

2.005

V

0

0

1

1

1

1.531

1.592

1.653

1.827

1.888

1.949

V

0

1

0

0

0

1.487

1.546

1.606

1.775

1.834

1.893

V

0

1

0

0

1

1.443

1.501

1.558

1.722

1.779

1.837

V

0

1

0

1

0

1.399

1.455

1.511

1.670

1.725

1.781

V

0

1

0

1

1

1.355

1.409

1.463

1.617

1.671

1.724

V

0

1

1

0

0

1.311

1.363

1.416

1.565

1.617

1.669

V

0

1

1

0

1

1.267

1.318

1.368

1.512

1.562

1.613

V

0

1

1

1

0

1.223

1.272

1.321

1.460

1.508

1.557

V

0

1

1

1

1

1.179

1.226

1.273

1.407

1.454

1.501

V

1

1

1

1

1

1.097

1.141

1.185

1.309

1.353

1.397

V


CS5165H PACKAGE PIN DESCRIPTION PACKAGE PIN # SO–16L

PIN SYMBOL

FUNCTION

1, 2, 3, 4, 6

VID0–VID4

Voltage ID DAC input pins. These pins are internally pulled up to 5.0 V if left open. VID4 selects the DAC range. When VID4 is high (logic one), the Error Amp reference range is 2.14 V to 3.45 V with 100 mV increments. When VID4 is low (logic zero), the Error Amp reference voltage 1.34 V to 2.09 V with 50 mV increments.

5

SS

Soft Start Pin. A capacitor from this pin to LGND sets the Soft Start and fault timing.

7

COFF

Off–Time Capacitor Pin. A capacitor from this pin to LGND sets both the normal and extended off time.

8

ENABLE

9

VCC

10

GATE(H)

11

PGND

12

GATE(L)

Low Side Synchronous FET driver pin.

13

PWRGD

Power Good Output. Open collector output drives low when VFB is out of regulation. Active when ENABLE input is low.

14

LGND

Reference ground. All control circuits are referenced to this pin.

15

COMP

Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error Amp compensation.

16

VFB

Output Enable Input. This pin is internally pulled up to 1.8 V. A logic Low (< 0.8 V) on this pin disables operation and places the CS5156H into a low current sleep mode. Input Power Supply Pin. High Side Switch FET driver pin. High current ground for the GATE(H) and GATE(L) pins.

Error Amp, PWM Comparator, and Low VFB Comparator feedback input.


CS5165H VCC 7.0 µA

–

VCC Monitor

20 k

ENABLE

–

VCC

+

3.95 V 3.87V

Circuit Bias

+ 1.25 V

VGATE(H)

Enable Comparator

5.0 V

–

SS Low Comparator

R

Q

S

Q

+

60 µA 0.7 V SS

+

2.0 µA

FAULT FAULT

PGND

FAULT Latch

SS High Comparator

VCC

–

VCC1

VGATE(L)

2.5 V COMP VID0

Error Amplifier

PGND

+

VID1

5 BIT DAC

VID2

–

VID3 VID4 –8.5%

–

PWM COMP Blanking

PWM Comparator

+8.5% +

– +

–


Q

S

Q

Normal Off–Time Timeout

+

Extended Off–Time Timeout

PWRGD

R

PWM Latch Off–Time Timeout

GATE(H) = ON GATE(H) = OFF COFF One Shot R S

65 µs Delay

VFB


– +

1.0 V

VFB Low Comparator

LGND



Edge Triggered

COFF Q

CS5165H

200

200

180

180

160

160

140

140

Risetime (ns)

Risetime (ns)


120 100 80 60

0

0

2000 4000

80 VCC = 12 V

40

TA = 25°C

20

100

60

VCC = 12 V

40

120

TA = 25°C

20 0

6000 8000 10000 12000 14000 16000

0

2000 4000

Load Capacitance (pF)

Figure 3. GATE(L) Risetime vs. Load Capacitance

Figure 4. GATE(H) Risetime vs. Load Capacitance

0.04 DAC Output Voltage Deviation (%)

200 180 160 Falltime (ns)

140 120 100 80 60 40

VCC = 12 V

20

TA = 25°C

0

0

2000 4000

0.02 0 –0.02 –0.04 –0.06 –0.08 –0.1

6000 8000 10000 12000 14000 16000

0

20

40


60

80

100

120


Figure 5. GATE(H) & GATE(L) Falltime vs. Load Capacitance

Figure 6. DAC Output Voltage vs. Temperature, DAC Code = 10111, VCC = 12 V

0.04

0.05

0.02

0

0

Output Error (%)

Output Error (%)

6000 8000 10000 12000 14000 16000 Load Capacitance (pF)

–0.02 –0.04

–0.05

–0.10

–0.15

DAC Output Voltage Setting (V)


Figure 7. Percent Output Error vs. DAC Voltage Setting, VCC = 12 V, TA = 25°C, VID4 = 0

Figure 8. Percent Output Error vs. DAC Output Voltage Setting VCC = 12 V, TA = 25°C, VID4 = 1


3.54

3.44

3.34

3.24

3.14

3.04

2.94

2.84

2.74

2.64

2.54

2.44

2.34

2.14

2.09

2.04

1.94

1.99

1.84

1.89

1.79

1.69

1.74

1.59

1.64

1.54

1.49

–0.25

1.39

–0.10 1.44

–0.20

1.34

–0.08

2.24

–0.06

CS5165H APPLICATIONS INFORMATION THEORY OF OPERATION

The main purpose of this ‘slow’ feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. Line and load regulation are drastically improved because there are two independent voltage loops. A voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. The V2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load.

V2 Control Method

The V2 method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the value of the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current. PWM Comparator + GATE(H) C GATE(L) –

Constant Off Time

Ramp Signal


Error Signal

To maximize transient response, the CS5156H uses a constant off time method to control the rate of output pulses. During normal operation, the off time of the high side switch is terminated after a fixed period, set by the COFF capacitor. To maintain regulation, the V2 control loop varies switch on time. The PWM comparator monitors the output voltage ramp, and terminates the switch on time. Constant off time provides a number of advantages. Switch duty cycle can be adjusted from 0 to 100% on a pulse by pulse basis when responding to transient conditions. Both 0% and 100% duty cycle operation can be maintained for extended periods of time in response to load or line transients. PWM slope compensation to avoid sub–harmonic oscillations at high duty cycles is avoided. Switch on time is limited by an internal 30 µs (typical) timer, minimizing stress to the power components.

Output Voltage Feedback –

E +

Reference Voltage


V2

The control method is illustrated in Figure 9. The output voltage is used to generate both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. A change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the V2 control scheme to compensate the duty cycle. Since the change in inductor current modifies the ramp signal, as in current mode control, the V2 control scheme has the same advantages in line transient response. A change in load current will have an affect on the output voltage, altering the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. Load transient response is determined only by the comparator response time and the transition speed of the main switch. The reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. The error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop.

Programmable Output

The CS5156H is designed to provide two methods for programming the output voltage of the power supply. A five bit on board digital to analog converter (DAC) is used to program the output voltage within two different ranges. The first range is 2.14 V to 3.54 V in 100 mV steps, the second is 1.34 V to 2.09 V in 50 mV steps, depending on the digital input code. If all five bits are left open, the CS5156H enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feedback to the VFB pin, as in traditional controllers. The CS5156H is specifically designed to meet or exceed Intel’s Pentium II specifications.


CS5165H Start Up

Until the voltage on the VCC supply pin exceeds the 3.95 V monitor threshold, the Soft Start and GATE pins are held low. The FAULT latch is reset (no Fault condition). The output of the error amplifier (COMP) is pulled up to 1.0 V by the comparator clamp. When the VCC pin exceeds the monitor threshold, the GATE(H) output is activated, and the Soft Start capacitor begins charging. The GATE(H) output will remain on, enabling the NFET switch, until terminated by either the PWM comparator, or the maximum on time timer. If the maximum on time is exceeded before the regulator output voltage achieves the 1.0 V level, the pulse is terminated. The GATE(H) pin drives low, and the GATE(L) pin drives high for the duration of the extended off time. This time is set by the time out timer and is approximately equal to the maximum on time, resulting in a 50% duty cycle. The GATE(L) pin will then drive low, the GATE(H) pin will drive high, and the cycle repeats. When regulator output voltage achieves the 1.0 V level present at the COMP pin, regulation has been achieved and normal off time will ensue. The PWM comparator terminates the switch on time, with off time set by the COFF capacitor. The V2 control loop will adjust switch duty cycle as required to ensure the regulator output voltage tracks the output of the error amplifier. The Soft Start and COMP capacitors will charge to their final levels, providing a controlled turn on of the regulator output. Regulator turn on time is determined by the COMP capacitor charging to its final value. Its voltage is limited by the Soft Start COMP clamp and the voltage on the Soft Start pin.

M 250 µs Trace 1– Regulator Output Voltage (1.0 V/div.) Trace 2– Inductor Switching Node (2.0 V/div.) Trace 3– 12 V Input (VCC) (5.0 V/div.) Trace 4– 5.0 V Input (1.0 V/div.)

Figure 10. Demonstration Board Startup in Response to Increasing 12 V and 5.0 V Input Voltages. Extended Off Time is Followed by Normal Off Time Operation when Output Voltage Achieves Regulation to the Error Amplifier Output.

Power Supply Sequencing

Trace 1– Soft Start Pin (2.0 V/div.)

The CS5156H offers inherent protection from undefined start up conditions, regardless of the 12 V and 5.0 V supply power up sequencing. The turn on slew rates of the 12 V and 5.0 V power supplies can be varied over wide ranges without affecting the output voltage or causing detrimental effects to the buck regulator.

Trace 2– COMP PIn (error amplifier output) (1.0 V/div.) Trace 4– Regulator Output Voltage (1.0 V/div.)

Figure 11. Demonstration Board Startup Waveforms


CS5165H

M 10.0 µs Trace 1– GATE(H) (10 V/div.) Trace 2– Inductor Switching Node (5.0 V/div.) Trace 3– Output Inductor Ripple Current (2.0 A/div.) Trace 4– VOUT ripple (20 mV/div.)

Trace 1– Regulator Output Voltage (1.0 V/div.) Trace 2– Inductor Switching Node (5.0 V/div.)

Figure 12. Demonstration Board Enable Startup Waveforms

Figure 14. Normal Operation Showing Output Inductor Ripple Current and Output Voltage Ripple, ILOAD = 14 A, VOUT = +2.84 V (DAC = 10111)

Normal Operation

During normal operation, switch off time is constant and set by the COFF capacitor. Switch on time is adjusted by the V2 control loop to maintain regulation. This results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. Output voltage ripple will be determined by inductor ripple current working and the ESR of the output capacitors (see Figures 13 and 14).

Transient Response

The CS5156H V2 control loop’s 100 ns reaction time provides unprecedented transient response to changes in input voltage or output current. Pulse by pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. Overall load transient response is further improved through a feature called “Adaptive Voltage Positioning”. This technique pre–positions the output capacitors voltage to reduce total output voltage excursions during changes in load. Holding tolerance to 1.0% allows the error amplifiers reference voltage to be targeted +40 mV high without compromising DC accuracy. A “Droop Resistor”, implemented through a PC board trace, connects the Error Amps feedback pin (VFB) to the output capacitors and load and carries the output current. With no load, there is no DC drop across this resistor, producing an output voltage tracking the Error amps, including the +40 mV offset. When the full load current is delivered, an 80 mV drop is developed across this resistor. This results in output voltage being offset –40 mV low. The result of Adaptive Voltage Positioning is that additional margin is provided for a load transient before reaching the output voltage specification limits. When load

Trace 1– GATE(H) (10 V/div.) Trace 2– Inductor Switching Node (5.0 V/div.) Trace 3– Output Inductor Ripple Current (2.0 A/div.) Trace 4– VOUT ripple (20 mV/div.)

Figure 13. Normal Operation Showing Output Inductor Ripple Current and Output Voltage Ripple, 0.5 A Load, VOUT = +2.84 V (DAC = 10111)


CS5165H current suddenly increases from its minimum level, the output capacitor is pre–positioned +40 mV. Conversely, when load current suddenly decreases from its maximum level, the output capacitor is pre–positioned –40 mV (see Figures 15, 16, and 17). For best Transient Response, a combination of a number of high frequency and bulk output capacitors are usually used. If the Maximum On–Time is exceeded while responding to a sudden increase in Load current, a normal off–time occurs to prevent saturation of the output inductor.

Trace 1– GATE(H) (10 V/div.) Trace 2– Inductor Switching Node (5.0 V/div.) Trace 3– Load Current (5.0 A/div) Trace 4– VOUT (100 mV/div.)

Figure 17. Output Voltage Transient Response to a 14 A Load Turn–Off, VOUT = +2.84 V (DAC = 10111)

PROTECTION AND MONITORING FEATURES Short Circuit Protection

A lossless hiccup mode short circuit protection feature is provided, requiring only the Soft Start capacitor to implement. If a short circuit condition occurs the VFB low comparator sets the FAULT latch. This causes the top FET to shut off, disconnecting the regulator from it’s input voltage. The Soft Start capacitor is then slowly discharged by a 2.0 µA current source until it reaches it’s lower 0.7 V threshold. The regulator will then attempt to restart normally, operating in it’s extended off time mode with a 50% duty cycle, while the Soft Start capacitor is charged with a 60 µA charge current. If the short circuit condition persists, the regulator output will not achieve the 1.0 V low VFB comparator threshold before the Soft Start capacitor is charged to it’s upper 2.5 V threshold. If this happens the cycle will repeat itself until the short is removed. The Soft Start charge/discharge current ratio sets the duty cycle for the pulses (2.0 µA/60 µA = 3.3%), while actual duty cycle is half that due to the extended off time mode (1.65%). This protection feature results in less stress to the regulator components, input power supply, and PC board traces than occurs with constant current limit protection (see Figures 18 and 19). If the short circuit condition is removed, output voltage will rise above the 1.0 V level, preventing the FAULT latch from being set, allowing normal operation to resume.

Trace 3– Load Current (5.0 A/10 mV/div.) Trace 4– VOUT (100 mV/div.)

Figure 15. Output Voltage Transient Response to a 14 A Load Pulse, VOUT = +2.84 V (DAC = 10111)


Figure 16. Output Voltage Transient Response to a 14 A Load Step, VOUT = +2.84 V (DAC = 10111)


CS5165H implement the OVP function. If a dedicated OVP output is required, it can be implemented using the circuit in Figure 22. In this figure the OVP signal will go high (overvoltage condition), if the output voltage (VCORE) exceeds 20% of the voltage set by the particular DAC code and provided that PWRGD is low. It is also required that the overvoltage condition be present for at least the PWRGD delay time for the OVP signal to be activated. The resistor values shown in Figure 22 are for VDAC = +2.8 V (DAC = 10111). The VOVP (overvoltage trip–point) can be set using the following equation:

ǒ

Ǔ

VOVP + VBEQ3 1 ) R2 R1


Figure 18. Demonstration Board Hiccup Mode Short Circuit Protection. Gate Pulses are Delivered While the Soft Start Capacitor Charges, and Cease During Discharge

M 10.0 µs Trace 4– 5.0 V from PC Power Supply (5.0 V/div.) Trace 1– Regulator Output Voltage (1.0 V/div.) Trace 2– Inductor Switching Node 5.0 V/div.)



Figure 19. Demonstration Board Startup with Regulator Output Shorted To Ground Overvoltage Protection

Overvoltage protection (OVP) is provided as result of the normal operation of the V2 control topology and requires no additional external components. The control loop responds to an overvoltage condition within 100 ns, causing the top MOSFET to shut off, disconnecting the regulator from it’s input voltage. The bottom MOSFET is then activated, resulting in a “crowbar” action to clamp the output voltage and prevent damage to the load (see Figures 20 and 21 ). The regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. The bottom FET and board trace must be properly designed to


CS5165H nominal output voltage. Maximum output voltage deviation before Power Good is pulled low is ± 12%.

M 5.00 ms Trace 4– 5.0 V from PC Power Supply (2.0 V/div.) Trace 1– Regulator Output Voltage (1.0 V/div.)


Trace 2– PWRGD (2.0 V/div.) Trace 4– VOUT (1.0 V/div.)

Figure 23. PWRGD Signal Becomes Logic High as VOUT Enters –8.5% of Lower PWRGD Threshold, VOUT = +2.84 V (DAC = 10111)

VCORE 15 k

R1 Q3 2N3906

+5.0 V 56 k

R2

5.0 k OVP 20 k

+5.0 V

CS5156H

10 k

PWRGD

10 k

Q2 2N3904

10 K

Q1 2N3906

Figure 22. Circuit To Implement A Dedicated OVP Output Using The CS5156H Output Enable Circuit

The Enable pin (pin 8) is used to enable or disable the regulator output voltage, and is consistent with TTL DC specifications. It is internally pulled–up. If pulled low (below 0.8 V), the output voltage is disabled. At the same time the Power Good and Soft Start pins are pulled low, so that when normal operation resumes power–up of the CS5156H goes through the Soft Start sequence. Upon pulling the Enable pin low, the internal IC bias is completely shut off, resulting in total shutdown of the Controller IC.

Trace 2– PWRGD (2.0 V/div.) Trace 4– VFB (1.0 V/div.)

Figure 24. Power Good Response to an Out of Regulation Condition

Figure 24 shows the relationship between the regulated output voltage VFB and the Power Good signal. To prevent Power Good from interrupting the CPU unnecessarily, the CS5156H has a built–in delay to prevent noise at the VFB pin from toggling Power Good. The internal time delay is designed to take about 75 µs for Power Good to go low and 65 µs for it to recover. This allows the Power Good signal to be completely insensitive to out of regulation conditions that are present for a duration less than the built in delay (see Figure 25).

Power Good Circuit

The Power Good pin (pin 13) is an open–collector signal consistent with TTL DC specifications. It is externally pulled–up, and is pulled low (below 0.3 V) when the regulator output voltage typically exceeds ± 8.5% of the


CS5165H It is therefore required that the output voltage attains an out of regulation or in regulation level for at least the built–in delay time duration before the Power Good signal can change state.

Trace 3– GATE(H) (10 V/div.) Trace 1– GATE(H) – 5.0 VIN Trace 4– GATE(L) (10 V/div.) Trace 2– Inductor Switching Node (5.0 V/div.)

Figure 26. Gate Drive Waveforms Depicting Rail to Rail Swing


Figure 25. Power Good is Insensitive to Out of Regulation Conditions that are Present for a Duration Less Than the Built In Delay

@:2.2 V


The CS5156H buck regulator can be used with a wide range of external power components to optimize the cost and performance of a particular design. The following information can be used as general guidelines to assist in their selection. NFET Power Transistors

Both logic level and standard FETs can be used. The reference designs derive gate drive from the 12 V supply which is generally available in most computer systems and utilize logic level FETs. A charge pump may be easily implemented to permit use of standard FET’s or support 5.0 V or 12 V only systems (maximum of 20 V). Multiple FET’s may be paralleled to reduce losses and improve efficiency and thermal management. Voltage applied to the FET gates depends on the application circuit used. Both upper and lower gate driver outputs are specified to drive to within 1.5 V of ground when in the low state and to within 2.0 V of their respective bias supplies when in the high state. In practice, the FET gates will be driven rail to rail due to overshoot caused by the capacitive load they present to the controller IC. For the typical application where VCC = 12 V and 5.0 V is used as the source for the regulator output current, the following gate drive is provided:

Trace 1 = GATE(H) (5.0 V/div.) Trace 2 = GATE(L) (5.0 V/div.)

Figure 27. Normal Operation Showing the Guaranteed Non–Overlap Time Between the High and Low–Side MOSFET Gate Drives, ILOAD = 14 A

The CS5156H provides adaptive control of the external NFET conduction times by guaranteeing a typical 65 ns non–overlap between the upper and lower MOSFET gate drive pulses. This feature eliminates the potentially catastrophic effect of “shoot–through current”, a condition during which both FETs conduct causing them to overheat, self–destruct, and possibly inflict irreversible damage to the processor. The most important aspect of FET performance is RDSON, which effects regulator efficiency and FET thermal management requirements. The power dissipated by the MOSFETs may be estimated as follows: Switching MOSFET:

VGS(TOP) + 12 V * 5.0 V + 7.0 V VGS(BOTTOM) + 12 V

Power + ILOAD2

(see Figure 26)


RDSON

duty cycle

CS5165H 1. Sheet Resistivity for one ounce copper, the thickness variation typically 1.15 mil to 1.35 mil. Therefore the error due to sheet resistivity is:


(1 * duty cycle)

RDSON


ƪ

1.35 * 1.15 + 16% 1.25

RDSON OF SYNCH FET)


ƫ

2. Mismatch due to L/W. The variation in L/W is governed by variations due to the PCB manufacturing process that affect the geometry and the power dissipation capability of the droop resistor. The error due to L/W mismatch is typically 1.0%. 3. Thermal Considerations. Due to I2 × R power losses the surface temperature of the droop resistor will increase causing the resistance to increase. Also, the ambient temperature variation will contribute to the increase of the resistance, according to the formula:



4848.5


Perioid

R + R20[1 ) 20(T * 20)]

(1 * duty cycle) 4848.5

where: R20 = resistance at 20°C

where: Period +

+ 0.00393 °C


T = operating temperature R = desired droop resistor value For temperature T = 50°C, the % R change = 12%

Schottky Diode for Synchronous FET

For synchronous operation, a Schottky diode may be placed in parallel with the synchronous FET to conduct the inductor current upon turn off of the switching FET to improve efficiency. The CS5156H reference circuit does not use this device due to it’s excellent design. Instead, the body diode of the synchronous FET is utilized to reduce cost and conducts the inductor current. For a design operating at 200 kHz or so, the low non–overlap time combined with Schottky forward recovery time may make the benefits of this device not worth the additional expense. The power dissipation in the synchronous MOSFET due to body diode conduction can be estimated by the following equation: Power + VBD

ILOAD

conduction time

Droop Resistor Tolerance

Tolerance due to sheet resistivity variation Tolerance due to L/W error Tolerance due to temperature variation Total tolerance for droop resistor

In order to determine the droop resistor value the nominal voltage drop across it at full load has to be calculated. This voltage drop has to be such that the output voltage full load is above the minimum DC tolerance spec. VDROOP(TYP) +

14.2 A

100 ns

[VDAC(MIN) * VDC(MIN)] 1 ) RDROOP(TOLERANCE)

switching frequency

Example: for a 300 MHz PentiumII, the DC accuracy spec is 2.74 < VCC(CORE) < 2.9 V, and the AC accuracy spec is 2.67 V < VCC(CORE) < 2.9 3V. The CS5156H DAC output voltage is +2.812 V < VDAC < +2.868 V. In order not to exceed the DC accuracy spec, the voltage drop developed across the resistor must be calculated as follows:

Where VBD = the forward drop of the MOSFET body diode. For the CS5156H demonstration board: Power + 1.6 V

16% 1.0% 12% 29%

200 kHz + 0.45 W

This is only 1.1% of the 40 W being delivered to the load. “Droop” Resistor for Adaptive Voltage Positioning

Adaptive voltage positioning is used to help keep the output voltage within specification during load transients. To implement adaptive voltage positioning a “Droop Resistor” must be connected between the output inductor and output capacitors and load. This resistor carries the full load current and should be chosen so that both DC and AC tolerance limits are met. An embedded PC trace resistor has the distinct advantage of near zero cost implementation. However, this droop resistor can vary due to three reasons: 1) the sheet resistivity variation causes the thickness of the PCB layer to vary. 2) the mismatch of L/W, and 3) temperature variation.

VDROOP(TYP) +

[VDAC(MIN) * VDC PENTIUMII(MIN)] 1 ) RDROOP(TOLERANCE)

+ 2.812 V * 2.74 V + 56 mV 1.3

With the CS5156H DAC accuracy being 1.0%, the internal error amplifier’s reference voltage is trimmed so that the output voltage will be 40 mV high at no load. With no load, there is no DC drop across the resistor, producing an output voltage tracking the error amplifier output voltage, including the offset. When the full load current is delivered, a drop of –56 mV is developed across the resistor. Therefore,


CS5165H the regulator output is pre–positioned at 40 mV above the nominal output voltage before a load turn–on. The total voltage drop due to a load step is ∆V–40 mV and the deviation from the nominal output voltage is 40 mV smaller than it would be if there was no droop resistor. Similarly at full load the regulator output is pre–positioned at 16 mV below the nominal voltage before a load turn–off. The total voltage increase due to a load turn–off is ∆V–16 mV and the deviation from the nominal output voltage is 16 mV smaller than it would be if there was no droop resistor. This is because the output capacitors are pre–charged to value that is either 40 mV above the nominal output voltage before a load turn–on or, 16 mV below the nominal output voltage before a load turn–off (see Figure 15). Obviously, the larger the voltage drop across the droop resistor ( the larger the resistance), the worse the DC and load regulation, but the better the AC transient response.

L+

RDROOP

+ 0.0039

W

284 717.86

t 1.37 + 2113 mil + 5.36 cm

Output Inductor

The inductor should be selected based on its inductance, current capability, and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response. Inductor Ripple Current Ripple Current +

[(VIN * VOUT) VOUT] (Switching Frequency L VIN)

Example: VIN = +5.0 V, VOUT = +2.8 V, ILOAD = 14.2 A, L = 1.2 µH, Freq = 200 kHz Ripple Current +

Design Rules for Using a Droop Resistor

[(5.0 V * 2.8 V) 2.8 V] + 5.1 A [200 kHz 1.2 H 5.0 V]

The basic equation for laying an embedded resistor is: RAR +

L or R + A

Output Ripple Voltage

L (W

t)

VRIPPLE + Inductor Ripple Current

where: A = W × t = cross–sectional area ρ = the copper resistivity (µΩ – mil) L = length (mils) W = width (mils) t = thickness (mils)

Output Capacitor ESR

Example: VIN = +5.0 V, VOUT = +2.8 V, ILOAD = 14.2 A, L = 1.2 µH, Switching Frequency = 200 kHz Output Ripple Voltage = 5.1 A × Output Capacitor ESR (from manufacturer’s specs) ESR of Output Capacitors to limit Output Voltage Spikes

For most PCBs the copper thickness, t, is 35 µm (1.37 mils) for one ounce copper. ρ = 717.86 µΩ–mil For a Pentium II load of 14.2 A the resistance needed to create a 56 mV drop at full load is:

ESR +

VOUT IOUT

This applies for current spikes that are faster than regulator response time. Printed Circuit Board resistance will add to the ESR of the output capacitors. In order to limit spikes to 100 mV for a 14.2 A Load Step, ESR = 0.1/14.2 = 0.007 Ω

Response Droop + 56 mV + 56 mV + 3.9 m 14.2 A IOUT

The resistivity of the copper will drift with the temperature according to the following guidelines:

Inductor Peak Current

R + 12% @ TA + ) 50°C

Peak Current + Maximum Load Current )

R + 34% @ TA + ) 100°C

ǒRipple 2CurrentǓ

Example: VIN = +5.0 V, VOUT = +2.8 V, ILOAD = 14.2 A, L = 1.2 µH, Freq = 200 kHz

Droop Resistor Width Calculations

The droop resistor must have the ability to handle the load current and therefore requires a minimum width which is calculated as follows (assume one ounce copper thickness):

Peak Current + 14.2 A ) (5.1ń2) + 16.75 A

A key consideration is that the inductor must be able to deliver the Peak Current at the switching frequency without saturating.

I W + LOAD 0.05

Response Time to Load Increase

where: W = minimum width (in mils) required for proper power dissipation, and ILOAD Load Current Amps. The PentiumII maximum load current is 14.2 A. Therefore:

(limited by Inductor value unless Maximum On–Time is exceeded) Response Time +

L IOUT (VIN * VOUT)

Example: VIN = +5.0 V, VOUT = +2.8 V, L = 1.2 µH, 14.2 A change in Load Current

W + 14.2 A + 284 mils + 0.7213 cm 0.05

Droop Resistor Length Calculation http://onsemi.com 2089

CS5165H Response Time +

1.2 H 14.2 A + 7.7 s (5.0 V * 2.8 V)

and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the circuit board and input power supply. Placement of the power component to minimize routing distance will also help to reduce emissions.

Response Time to Load Decrease

(limited by Inductor value) Response Time +

L

Change in IOUT VOUT

Layout Guidelines

When laying out the CPU buck regulator on a printed circuit board, the following checklist should be used to ensure proper operation of the CS5156H. 1. Rapid changes in voltage across parasitic capacitors and abrupt changes in current in parasitic inductors are major concerns for a good layout. 2. Keep high currents out of logic grounds. 3. Avoid ground loops as they pick up noise. Use star or single point grounding. The source of the lower (synchronous FET) is an ideal point where the input and output GND planes can be connected. 4. For double–sided PCBs a single large ground plane is not recommended, since there is little control of where currents flow and the large surface area can act as an antenna. 5. Even though double sided PCBs are usually sufficient for a good layout, four–layer PCBs are the optimum approach to reducing susceptibility to noise. Use the two internal layers as the +5.0 V and GND planes, and the top and bottom layers for the vias. 6. Keep the inductor switching node small by placing the output inductor, switching and synchronous FETs close together. 7. The FET gate traces to the IC must be as short, straight, and wide as possible. Ideally, the IC has to be placed right next to the FETs. 8. Use fewer, but larger output capacitors, keep the capacitors clustered, and use multiple layer traces with heavy copper to keep the parasitic resistance low. 9. Place the switching FET as close to the +5.0 V input capacitors as possible. 10. Place the output capacitors as close to the load as possible. 11. Place the VFB filter resistor in series with theVFB pin (pin 16) right at the pin. 12. Place the VFB filter capacitor right at the VFB pin (pin 16). 13. The “Droop” Resistor (embedded PCB trace) has to be wide enough to carry the full load current. 14. Place the VCC bypass capacitor as close as possible to the VCC pin.

Example: VOUT = +2.8 V, 14.2 A change in Load Current, L = 1.2 µH Response Time +

1.2 H 14.2 A + 6.1 s 2.8 V


These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to provide acceptable ripple on the input supply lines and regulator output voltage. Key specifications for input capacitors are their ripple rating, while ESR is important for output capacitors. For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. THERMAL MANAGEMENT Thermal Considerations for Power MOSFETs and Diodes


TJ(MAX) * TAMBIENT Power

A heatsink may be added to TO–220 components to reduce their thermal impedance. A number of PC board layout techniques such as thermal vias and additional copper foil area can be used to improve the power handling capability of surface mount components. EMI Management

As a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. When designing for compliance with EMI/EMC regulations, additional components may be added to reduce noise emissions. These components are not required for regulator operation and experimental results may allow them to be eliminated. The input filter inductor may not be required because bulk filter


CS5165H 12 V +12 V

1N5818

1200 µF/10 V × 3

1N5818 0.1 µF

18 Ω 18 V 1N4746 1.0 µF COFF

1000 pF

VCC

IRL3103

GATE(H) SS

1.2 µH

CS5156H

0.1 µF

GATE(L)


1200 µF/10 V × 5

1000 pF

COMP

VCC

3.3 k

VFB

0.1 µF

Droop Resistor (Embedded PCB trace) 6.0 Ω

IRL3103

VSS

PGND PWRGD LGND

ENABLE

ENABLE PWRGD PENTIUM II SYSTEM VID4 VID3 VID2 VID1 VID0

Figure 28. Additional Application Diagram, +12 V to +2.8 V @ 14.2 A for 300 MHz Pentium II 5.0 V MBRS120 1.0 µF

MBRS120

1200 µF/10 V × 3

MBRS120 1.0 µF VCC VID0

VGATE(H)

Si4410DY

VID1 CS5156H VID2 VGATE(L)

VID3 VID4 330 pF

+ 1200 µF/10 V × 5

Si9410DY

COFF SS

ENABLE PWRGD 3.3 k

VFB LGND

0.1 µF

VCC

VSS

PGND

COMP 0.1 µF

Droop Resistor (Embedded PCB trace) 6.0 mΩ 1.2 µH

ENABLE PWRGD PENTIUM II SYSTEM

1000 pF


Figure 29. Additional Application Diagram, +5.0 V to +2.8 V @ 14.2 A for 300 MHz Pentium II



SO–16L

Unit

RΘJC

Typical

23

°C/W

RΘJA

Typical

105

°C/W


-" &# ! 89 "# 8 2.5 V

180

400

800

µA

Open Loop Gain

Note 2

50

60

–

dB


Note 2

0.5

2.0

–

MHz

PSRR @ 1.0 kHz

Note 2

60

85

–

dB

Current Limit Voltage

VFB = 0 V to 3.5 V, 8.0 V < VCC < 12 V + 10%

55

76

130

mV

ISENSE Bias Current

ISENSE = 2.8 V

13

30

50

µA

Error Amplifier

Overcurrent Detection



CS5166H ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 8.0 V < VCC < 20 V; 2.0 DAC Code: (VID4 = VID3 = VID2 = VID1 = 0, VID0 = 1), CGATE(H) = CGATE(L) = 3.3 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit


Measure VCC – GATE

–

1.2

2.0

V


Measure GATE

–

1.0

1.5

V

Rise Time

1.6 V < GATE < (VCC – 2.5 V), 8.0 V < VCC < 14 V

–

40

80

ns

Fall Time

(VCC – 2.5 V) > GATE > 1.6 V, 8.0 V < VCC < 14 V

–

40

80

ns


GATE(H) < 2.0 V; GATE(L) > 2.0 V, 8.0 V < VCC < 14 V

30

65

100

ns


GATE(L) < 2.0 V; GATE(H) > 2.0 V, 8.0 V < VCC < 14 V

30

65

100

ns

GATE pull–down

Resistor to PGND, Note 3

20

50

115

kΩ

SS Charge Time

VFB = 3.0 V, VISENSE = 2.8 V

1.6

3.3

5.0

ms

SS Pulse Period

VFB = 3.0 V, VISENSE = 2.8 V

25

100

200

ms

SS Duty Cycle

(Charge Time/Period) × 100

1.0

3.3

6.0

%

SS COMP Clamp Voltage

VFB = 2.7 V; VSS = 0 V

0.50

0.95

1.10

V

VFB Low Comparator

Increase VFB till normal off–time

0.9

1.0

1.1

V

Fault Protection


VFB = 1.2 to 5.0 V. 500 ns after GATE(H) (after Blanking time) to GATE(H) = (VCC –1.0 V) to 1.0 V, 8.0 V < VCC < 14 V

–

115

175

ns

Minimum Pulse Width (Blanking Time)

Drive VFB 1.2 V to 5.0 V upon GATE(H) rising edge (> VCC – 1.0 V), measure GATE(H) pulse width, 8.0 V < VCC < 14 V

100

200

300

ns

Normal Off–Time

VFB = 2.7 V

1.0

1.6

2.3

µs

Extended Off–Time

VSS = VFB = 0 V

5.0

8.0

12.0

µs

Time–Out Time

VFB = 2.7 V, Measure GATE(H) Pulse Width

10

30

50

µs

Fault Duty Cycle

VFB = 0V

30

50

70

%

Low to High Delay

VFB = (0.8 × VDAC) to VDAC

30

65

110

µs

High to Low Delay

VFB = VDAC to (0.8 × VDAC)

30

75

120

µs

Output Low Voltage


–

0.2

0.3

V

Sink Current Limit

VFB = 2.4 V, PWRGD = 1.0 V

0.5

4.0

15.0

mA

COFF

Time–Out Timer

Power Good Output



CS5166H ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 8.0 V < VCC < 20 V; 2.0 DAC Code: (VID4 = VID3 = VID2 = VID1 = 0, VID0 = 1), CGATE(H) = CGATE(L) = 3.3 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

–1.0

–

+1.0

%

Voltage Identification DAC Accuracy (all codes except 11111)

Measure VFB = COMP (COFF = GND) 25°C ≤ TJ ≤ 125°C; VCC = 12 V

VID4

VID3

VID2

VID1

VID0

1

0

0

0

0

–

3.489

3.525

3.560

V

1

0

0

0

1

–

3.390

3.425

3.459

V

1

0

0

1

0

–

3.291

3.325

3.358

V

1

0

0

1

1

–

3.192

3.225

3.257

V

1

0

1

0

0

–

3.093

3.125

3.156

V

1

0

1

0

1

–

2.994

3.025

3.055

V

1

0

1

1

0

–

2.895

2.925

2.954

V

1

0

1

1

1

–

2.796

2.825

2.853

V

1

1

0

0

0

–

2.697

2.725

2.752

V

1

1

0

0

1

–

2.598

2.625

2.651

V

1

1

0

1

0

–

2.499

2.525

2.550

V

1

1

0

1

1

–

2.400

2.425

2.449

V

1

1

1

0

0

–

2.301

2.325

2.348

V

1

1

1

0

1

–

2.202

2.225

2.247

V

1

1

1

1

0

–

2.103

2.125

2.146

V

0

0

0

0

0

–

2.054

2.075

2.095

V

0

0

0

0

1

–

2.004

2.025

2.045

V

0

0

0

1

0

–

1.955

1.975

1.994

V

0

0

0

1

1

–

1.905

1.925

1.944

V

0

0

1

0

0

–

1.856

1.875

1.893

V

0

0

1

0

1

–

1.806

1.825

1.843

V

0

0

1

1

0

–

1.757

1.775

1.792

V

0

0

1

1

1

–

1.707

1.725

1.742

V

0

1

0

0

0

–

1.658

1.675

1.691

V

0

1

0

0

1

–

1.608

1.625

1.641

V

0

1

0

1

0

–

1.559

1.575

1.590

V

0

1

0

1

1

–

1.509

1.525

1.540

V

0

1

1

0

0

–

1.460

1.475

1.489

V

0

1

1

0

1

–

1.410

1.425

1.439

V

0

1

1

1

0

–

1.361

1.375

1.388

V

0

1

1

1

1

–

1.311

1.325

1.338

V

1

1

1

1

1

–

1.219

1.247

1.269

V

Input Threshold


1.000

1.250

2.400

V

Input Pull–up Resistance


25

50

100

kΩ

4.85

5.00

5.15

V

Input Pull–up Voltage


CS5166H ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 8.0 V < VCC < 20 V; 2.0 DAC Code: (VID4 = VID3 = VID2 = VID1 = 0, VID0 = 1); CGATE(H) = CGATE(L) = 3.3 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Lower Threshold Threshold Accuracy Acc racy

Min

Typ

–12

–8.5

Upper Threshold Max

Min

Typ

Max

Unit

–5.0

5.0

8.5

12

%

DAC CODE % of Nominal DAC Output VID4

VID3

VID2

VID1

VID0

1

0

0

0

0

3.102

3.225

3.348

3.701

3.824

3.948

V

1

0

0

0

1

3.014

3.133

3.253

3.596

3.716

3.836

V

1

0

0

1

0

2.926

3.042

3.158

3.491

3.607

3.724

V

1

0

0

1

1

2.838

2.950

3.063

3.386

3.499

3.612

V

1

0

1

0

0

2.750

2.859

2.968

3.281

3.390

3.500

V

1

0

1

0

1

2.662

2.767

2.873

3.176

3.282

3.388

V

1

0

1

1

0

2.574

2.676

2.778

3.071

3.173

3.276

V

1

0

1

1

1

2.486

2.584

2.683

2.966

3.065

3.164

V

1

1

0

0

0

2.398

2.493

2.588

2.861

2.956

3.052

V

1

1

0

0

1

2.310

2.401

2.493

2.756

2.848

2.940

V

1

1

0

1

0

2.222

2.310

2.398

2.651

2.739

2.828

V

1

1

0

1

1

2.134

2.218

2.303

2.546

2.631

2.716

V

1

1

1

0

0

2.046

2.127

2.208

2.441

2.522

2.604

V

1

1

1

0

1

1.958

2.035

2.113

2.336

2.414

2.492

V

1

1

1

1

0

1.870

1.944

2.018

2.231

2.305

2.380

V

0

0

0

0

0

1.826

1.898

1.971

2.178

2.251

2.324

V

0

0

0

0

1

1.782

1.8520

1.923

2.126

2.197

2.268

V

0

0

0

1

0

1.738

1.807

1.876

2.073

2.142

2.212

V

0

0

0

1

1

1.694

1.761

1.828

2.021

2.088

2.156

V

0

0

1

0

0

1.650

1.715

1.781

1.968

2.034

2.100

V

0

0

1

0

1

1.606

1.669

1.733

1.916

1.980

2.044

V

0

0

1

1

0

1.562

1.624

1.686

1.863

1.925

1.988

V

0

0

1

1

1

1.518

1.578

1.638

1.811

1.871

1.932

V

0

1

0

0

0

1.474

1.532

1.591

1.758

1.817

1.876

V

0

1

0

0

1

1.430

1.486

1.543

1.706

1.763

1.820

V

0

1

0

1

0

1.386

1.441

1.496

1.653

1.708

1.764

V

0

1

0

1

1

1.342

1.395

1.448

1.601

1.654

1.708

V

0

1

1

0

0

1.298

1.349

1.401

1.548

1.600

1.652

V

0

1

1

0

1

1.254

1.303

1.353

1.496

1.546

1.596

V

0

1

1

1

0

1.210

1.258

1.306

1.443

1.491

1.540

V

0

1

1

1

1

1.166

1.212

1.258

1.391

1.437

1.484

V

1

1

1

1

1

1.094

1.138

1.181

1.306

1.349

1.393

V


CS5166H PACKAGE PIN DESCRIPTION PACKAGE PIN # SO–16L

PIN SYMBOL

FUNCTION

1, 2, 3, 4, 6

VID0–VID4

Voltage ID DAC input pins. These pins are internally pulled up to 5.0 V if left open. VID4 selects the DAC range. When VID4 is high (logic one), the Error Amp reference range is 2.125 V to 3.525 V with 100 mV increments. When VID4 is low (logic zero), the Error Amp reference voltage is 1.325 V to 2.075 V with 50 mV increments.

5

SS

Soft Start Pin. A capacitor from this pin to LGND sets the Soft Start and fault timing.

7

COFF

Off–Time Capacitor Pin. A capacitor from this pin to LGND sets both the normal and extended off time.

8

ISENSE

9

VCC

10

GATE(H)

11

PGND

12

GATE(L)

Low Side Synchronous FET driver pin.

13

PWRGD

Power Good Output. Open collector output drives low when VFB is out of regulation.

14

LGND

Reference ground. All control circuits are referenced to this pin.

15

COMP

Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error Amp compensation.

16

VFB

Error Amp, PWM Comparator feedback input, Current Sense Comparator Non–Inverting input, and PWRGD Comparator input.

Current Sense Comparator Inverting Input. Input Power Supply Pin. High Side Switch FET driver pin. High current ground for the GATE(H) and GATE(L) pins.


CS5166H

–

VCC Monitor

VCC

+

3.95 V 3.87V VGATE(H) 5.0 V

–

SS Low Comparator

R

Q

S

Q

+

60 µA 0.7 V SS

+

2.0 µA

FAULT FAULT

PGND

FAULT Latch

SS High Comparator

VCC

–

VCC1

VGATE(L)

2.5 V COMP VID0

Error Amplifier 5 BIT DAC

VID2

PGND

PWM Comparator

+

VID1

–

VID3 VID4

–

PWM COMP

+

Blanking

VCC –8.5%

+8.5% +

–

–

+

76 mV

30 µA

Extended Off–Time Timeout

+ 65 µs Delay

R

Q

S

Q

PWM Latch

Normal Off–Time

– PWRGD

GATE(H) = ON Maximum On–Time Timeout

Off–Time Timeout

GATE(H) = OFF COFF One Shot R S

ISENSE Comparator

VFB

Time–Out Timer

– +

ISENSE 1.0 V

VFB Low Comparator

LGND



Edge Triggered

COFF Q

CS5166H

200

200

180

180

160

160

140

140

Risetime (ns)

Risetime (ns)


120 100 80 60

0

0

2000 4000

80 VCC = 12 V

40

TA = 25°C

20

100

60

VCC = 12 V

40

120

TA = 25°C

20 0

6000 8000 10000 12000 14000 16000

0

2000 4000


Figure 3. GATE(L) Risetime vs. Load Capacitance

Figure 4. GATE(H) Risetime vs. Load Capacitance

0.04 DAC Output Voltage Deviation (%)

200 180 160 Falltime (ns)

140 120 100 80 60 40

VCC = 12 V

20

TA = 25°C

0

0

2000 4000

0.02 0 –0.02 –0.04 –0.06 –0.08 –0.1

6000 8000 10000 12000 14000 16000

0

20

40


60

80

100

120


Figure 5. GATE(H) & GATE(L) Falltime vs. Load Capacitance

Figure 6. DAC Output Voltage vs. Temperature, DAC Code = 10111, VCC = 12 V

0.04

0.05

0.02

0

0

Output Error (%)

Output Error (%)

6000 8000 10000 12000 14000 16000 Load Capacitance (pF)

–0.02 –0.04

–0.05

–0.10

–0.15



Figure 7. Percent Output Error vs. DAC Voltage Setting, VCC = 12 V, TA = 25°C, VID4 = 0

Figure 8. Percent Output Error vs. DAC Output Voltage Setting VCC = 12 V, TA = 25°C, VID4 = 1


3.525

3.425

3.325

3.225

3.125

3.025

2.925

2.825

2.725

2.625

2.525

2.425

2.325

2.125

2.075

2.025

1.975

1.925

1.875

1.825

1.775

1.675

1.725

1.625

1.575

1.525

1.475

–0.25 1.425

–0.10 1.325

–0.20

1.375

–0.08

2.225

–0.06

CS5166H APPLICATIONS INFORMATION THEORY OF OPERATION

since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. The Bode plot in Figure 10 shows the gain and phase margin of the CS5166H single pole feedback loop and demonstrates the overall stability of the CS5166H–based regulator.

V2 Control Method

The V2 method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the value of the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current. PWM Comparator + GATE(H) C GATE(L) –

Ramp Signal

VFB Error Amplifier

COMP

Error Signal

Figure 10. Feedback Loop Bode Plot –

E +

Line and load regulation are drastically improved because there are two independent voltage loops. A voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. The V2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load.

Reference Voltage


V2

The control method is illustrated in Figure 9. The output voltage is used to generate both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. A change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the V2 control scheme to compensate the duty cycle. Since the change in inductor current modifies the ramp signal, as in current mode control, the V2 control scheme has the same advantages in line transient response. A change in load current will have an affect on the output voltage, altering the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. Load transient response is determined only by the comparator response time and the transition speed of the main switch. The reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. The error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. The main purpose of this ‘slow’ feedback loop is to provide DC accuracy. Noise immunity is significantly improved,

Constant Off Time

To maximize transient response, the CS5166H uses a constant off time method to control the rate of output pulses. During normal operation, the off time of the high side switch is terminated after a fixed period, set by the COFF capacitor. To maintain regulation, the V2 control loop varies switch on time. The PWM comparator monitors the output voltage ramp, and terminates the switch on time. Constant off time provides a number of advantages. Switch duty cycle can be adjusted from 0 to 100% on a pulse by pulse basis when responding to transient conditions. Both 0% and 100% duty cycle operation can be maintained for extended periods of time in response to load or line transients. PWM slope compensation to avoid sub–harmonic oscillations at high duty cycles is avoided.


CS5166H Switch on time is limited by an internal 30 µs (typical) timer, minimizing stress to the power components. Programmable Output

The CS5166H is designed to provide two methods for programming the output voltage of the power supply. A five bit on board digital to analog converter (DAC) is used to program the output voltage within two different ranges. The first range is 2.125 V to 3.525 V in 100 mV steps, the second is 1.325 V to 2.075 V in 50 mV steps, depending on the digital input code. If all five bits are left open, the CS5166H enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feedback to the VFB pin, as in traditional controllers. The CS5166H is specifically designed to meet or exceed Intel’s Pentium II specifications.

M 250 µs Trace 1– Regulator Output Voltage (1.0 V/div.) Trace 2– Inductor Switching Node (2.0 V/div.) Trace 3– 12 V Input (VCC) (5.0 V/div.) Trace 4– 5.0 V Input (1.0 V/div.)

Figure 11. Demonstration Board Startup in Response to Increasing 12 V and 5.0 V Input Voltages. Extended Off Time is Followed by Normal Off Time Operation when Output Voltage Achieves Regulation to the Error Amplifier Output.

Start Up

Until the voltage on the VCC supply pin exceeds the 3.95 V monitor threshold, the Soft Start and GATE pins are held low. The FAULT latch is reset (no Fault condition). The output of the error amplifier (COMP) is pulled up to 1.0 V by the comparator clamp. When the VCC pin exceeds the monitor threshold, the GATE(H) output is activated, and the Soft Start capacitor begins charging. The GATE(H) output will remain on, enabling the NFET switch, until terminated by either the PWM comparator, or the maximum on time timer. If the maximum on time is exceeded before the regulator output voltage achieves the 1.0 V level, the pulse is terminated. The GATE(H) pin drives low, and the GATE(L) pin drives high for the duration of the extended off time. This time is set by the time out timer and is approximately equal to the maximum on time, resulting in a 50% duty cycle. The GATE(L) pin will then drive low, the GATE(H) pin will drive high, and the cycle repeats. When regulator output voltage achieves the 1.0 V level present at the COMP pin, regulation has been achieved and normal off time will ensue. The PWM comparator terminates the switch on time, with off time set by the COFF capacitor. The V2 control loop will adjust switch duty cycle as required to ensure the regulator output voltage tracks the output of the error amplifier. The Soft Start and COMP capacitors will charge to their final levels, providing a controlled turn on of the regulator output. Regulator turn on time is determined by the COMP capacitor charging to its final value. Its voltage is limited by the Soft Start COMP clamp and the voltage on the Soft Start pin.

Trace 1– Regulator Output Voltage (1.0 V/div.). Trace 3– COMP PIn (error amplifier output) (1.0 V/div.). Trace 4– Soft Start Pin (2.0 V/div.).

Figure 12. Demonstration Board Startup Waveforms


CS5166H

M 10.0 µs Trace 1– GATE(H) (10 V/div.) Trace 2– Inductor Switching Node (5.0 V/div.) Trace 3– Output Inductor Ripple Current (2.0 A/div.) Trace 4– VOUT ripple (20 mV/div.)


Figure 13. Demonstration Board Enable Startup Waveforms

Figure 15. Normal Operation Showing Output Inductor Ripple Current and Output Voltage Ripple, ILOAD = 14 A, VOUT = +2.825 V (DAC = 10111)

Normal Operation

During normal operation, switch off time is constant and set by the COFF capacitor. Switch on time is adjusted by the V2 control loop to maintain regulation. This results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. Output voltage ripple will be determined by inductor ripple current working and the ESR of the output capacitors (see Figures 14 and 15).

Transient Response

The CS5166H V2 control loop’s 150 ns reaction time provides unprecedented transient response to changes in input voltage or output current. Pulse by pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. Overall load transient response is further improved through a feature called “Adaptive Voltage Positioning”. This technique pre–positions the output capacitors voltage to reduce total output voltage excursions during changes in load. Holding tolerance to 1.0% allows the error amplifiers reference voltage to be targeted +25 mV high without compromising DC accuracy. A “Droop Resistor”, implemented through a PC board trace, connects the Error Amps feedback pin (VFB) to the output capacitors and load and carries the output current. With no load, there is no DC drop across this resistor, producing an output voltage tracking the Error amps, including the +25 mV offset. When the full load current is delivered, an 50 mV drop is developed across this resistor. This results in output voltage being offset –25 mV low. The result of Adaptive Voltage Positioning is that additional margin is provided for a load transient before

Trace 1– GATE(H) (10 V/div.) Trace 2– Inductor Switching Node (5.0 V/div.) Trace 3– Output Inductor Ripple Current (2.0 A/div.) Trace 4– VOUT ripple (20 mV/div.)

Figure 14. Normal Operation Showing Output Inductor Ripple Current and Output Voltage Ripple, 0.5 A Load, VOUT = +2.825 V (DAC = 10111)


CS5166H reaching the output voltage specification limits. When load current suddenly increases from its minimum level, the output capacitor is pre–positioned +25 mV. Conversely, when load current suddenly decreases from its maximum level, the output capacitor is pre–positioned –25 mV (see Figures 16, 17, and 18). For best Transient Response, a combination of a number of high frequency and bulk output capacitors are usually used. If the Maximum On–Time is exceeded while responding to a sudden increase in Load current, a normal off–time occurs to prevent saturation of the output inductor.


Figure 18. Output Voltage Transient Response to a 14 A Load Turn–Off, VOUT = +2.825 V (DAC = 10111) Power Supply Sequencing

The CS5166H offers inherent protection from undefined start up conditions, regardless of the 12 V and 5.0 V supply power up sequencing. The turn on slew rates of the 12 V and 5.0 V power supplies can be varied over wide ranges without affecting the output voltage or causing detrimental effects to the buck regulator.

Trace 3– Load Current (5.0 A/10 mV/div.) Trace 4– VOUT (100 mV/div.)

PROTECTION AND MONITORING FEATURES

Figure 16. Output Voltage Transient Response to a 14 A Load Pulse, VOUT = +2.825 V (DAC = 10111)

Overcurrent Protection

A loss–less hiccup mode current limit protection feature is provided, requiring only the Soft Start capacitor to implement. The CS5166H provides overcurrent protection by sensing the current through a “Droop” resistor, using an internal current sense comparator. The comparator compares this voltage drop to an internal reference voltage of 76 mV (typical). If the voltage drop across the “Droop” resistor exceeds this threshold, the current sense comparator allows the fault latch to be set. This causes the regulator to stop switching. During this overcurrent condition, the CS5166H stays off for the time it takes the Soft Start capacitor to slowly discharge by a 2.0 µA current source until it reaches its lower 0.7 V threshold. At that time the regulator attempts to restart normally by delivering short gate pulses to both FET’s. The CS5166H will operate initially in its extended off time mode with a 50% duty cycle, while the Soft Start capacitor is charged with a 60 mA charge current. The gates will switch on while


Figure 17. Output Voltage Transient Response to a 14 A Load Step, VOUT = +2.825 V (DAC = 10111)


CS5166H MOSFET to shut off, disconnecting the regulator from it’s input voltage. The bottom MOSFET is then activated, resulting in a “crowbar” action to clamp the output voltage and prevent damage to the load (see Figures 21 and 22 ). The regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. The bottom FET and board trace must be properly designed to implement the OVP function. If a dedicated OVP output is required, it can be implemented using the circuit in Figure 23. In this figure the OVP signal will go high (overvoltage condition), if the output voltage (VCORE) exceeds 20% of the voltage set by the particular DAC code and provided that PWRGD is low. It is also required that the overvoltage condition be present for at least the PWRGD delay time for the OVP signal to be activated. The resistor values shown in Figure 23 are for VDAC = +2.8 V (DAC = 10111). The VOVP (overvoltage trip–point) can be set using the following equation:

the Soft Start capacitor is charged to its upper 2.7 V threshold. During an overload condition the Soft Start charge/discharge current ratio sets the duty cycle for the pulses (2.0 µA/60 µA = 3.3%), while actual duty cycle is half that due to the extended off time mode (1.65%) when VFB is less than 1.0 V. The Soft Start hiccup pulses last for a 3.0 ms period at the end of which the duty cycle repeats if a fault is detected, otherwise normal operation resumes. The protection scheme minimizes thermal stress to the regulator components, input power supply, and PC board traces, as the overcurrent condition persists. Upon removal of the overload, the fault latch is cleared, allowing normal operation to resume. The current limit trip point can be adjusted through an external resistor, providing the user with the current limit set–point flexibility.

ǒ

Ǔ

VOVP + VBEQ3 1 ) R2 R1


Figure 19. Demonstration Board Hiccup Mode Short Circuit Protection. Gate Pulses are Delivered While the Soft Start Capacitor Charges, and Cease During Discharge

M 10.0 µs Trace 4– 5.0 V from PC Power Supply (5.0 V/div.) Trace 1– Regulator Output Voltage (1.0 V/div.) Trace 2– Inductor Switching Node 5.0 V/div.)



Figure 20. Demonstration Board Startup with Regulator Output Shorted To Ground Overvoltage Protection

M 5.00 ms

Overvoltage protection (OVP) is provided as result of the normal operation of the V2 control topology and requires no additional external components. The control loop responds to an overvoltage condition within 100 ns, causing the top




CS5166H VCORE 15 k

R1 Q3 2N3906

+5.0 V 56 k

R2

5.0 k OVP 20 k

+5.0 V

CS5166H

10 k

PWRGD

10 k

Q2 2N3904

10 K

Q1 2N3906

Figure 23. Circuit To Implement A Dedicated OVP Output Using The CS5166H


Figure 25. Power Good Response to an Out of Regulation Condition

Power Good Circuit

The Power Good pin (pin 13) is an open–collector signal consistent with TTL DC specifications. It is externally pulled–up, and is pulled low (below 0.3 V) when the regulator output voltage typically exceeds ± 8.5% of the nominal output voltage. Maximum output voltage deviation before Power Good is pulled low is ± 12%.

Figure 25 shows the relationship between the regulated output voltage VFB and the Power Good signal. To prevent Power Good from interrupting the CPU unnecessarily, the CS5166H has a built–in delay to prevent noise at the VFB pin from toggling Power Good. The internal time delay is designed to take about 75 µs for Power Good to go low and 65 µs for it to recover. This allows the Power Good signal to be completely insensitive to out of regulation conditions that are present for a duration less than the built in delay (see Figure 26). It is therefore required that the output voltage attains an out of regulation or in regulation level for at least the built–in delay time duration before the Power Good signal can change state.

Trace 2– PWRGD (2.0 V/div.) Trace 4– VOUT (1.0 V/div.)

Figure 24. PWRGD Signal Becomes Logic High as VOUT Enters –8.5% of Lower PWRGD Threshold, VOUT = +2.825 V (DAC = 10111)


Figure 26. Power Good is Insensitive to Out of Regulation Conditions that are Present for a Duration Less Than the Built In Delay External Output Enable Circuit

On/off control of the regulator can be implemented through the addition of two additional discrete components (see Figure ). This circuit operates by pulling the Soft Start pin high, and the ISENSE pin low, emulating a current limit condition.


CS5166H 5.0 V

MMUN2111T1 (SOT–23) 5

8

SS CS5166H ISENSE

IN4148 Shutdown Input Trace 3– GATE(H) (10 V/div.) Trace 1– GATE(H) – 5.0 VIN


Trace 4– GATE(L) (10 V/div.) Trace 2– Inductor Switching Node (5.0 V/div.)


Figure 28. Gate Drive Waveforms Depicting Rail to Rail Swing

The CS5166H buck regulator can be used with a wide range of external power components to optimize the cost and performance of a particular design. The following information can be used as general guidelines to assist in their selection. NFET Power Transistors

Both logic level and standard FETs can be used. The reference designs derive gate drive from the 12 V supply which is generally available in most computer systems and utilize logic level FETs. A charge pump may be easily implemented to permit use of standard FET’s or support 5.0 V or 12 V only systems (maximum of 20 V). Multiple FET’s may be paralleled to reduce losses and improve efficiency and thermal management. Voltage applied to the FET gates depends on the application circuit used. Both upper and lower gate driver outputs are specified to drive to within 1.5 V of ground when in the low state and to within 2.0 V of their respective bias supplies when in the high state. In practice, the FET gates will be driven rail to rail due to overshoot caused by the capacitive load they present to the controller IC. For the typical application where VCC = 12 V and 5.0 V is used as the source for the regulator output current, the following gate drive is provided:

Trace 1 = GATE(H) (5.0 V/div.) Trace 2 = GATE(L) (5.0 V/div.)

Figure 29. Normal Operation Showing the Guaranteed Non–Overlap Time Between the High and Low–Side MOSFET Gate Drives, ILOAD = 14 A

The CS5166H provides adaptive control of the external NFET conduction times by guaranteeing a typical 65 ns non–overlap (as seen in Figure 29) between the upper and lower MOSFET gate drive pulses. This feature eliminates the potentially catastrophic effect of “shoot–through current”, a condition during which both FETs conduct causing them to overheat, self–destruct, and possibly inflict irreversible damage to the processor.

VGS(TOP) + 12 V * 5.0 V + 7.0 V VGS(BOTTOM) + 12 V

(see Figure 28)


CS5166H and output capacitors and load. This resistor carries the full load current and should be chosen so that both DC and AC tolerance limits are met. An embedded PC trace resistor has the distinct advantage of near zero cost implementation. However, this droop resistor can vary due to three reasons: 1) the sheet resistivity variation causes the thickness of the PCB layer to vary. 2) the mismatch of L/W, and 3) temperature variation. 1. Sheet Resistivity for one ounce copper, the thickness variation typically 1.15 mil to 1.35 mil. Therefore the error due to sheet resistivity is:

The most important aspect of FET performance is RDSON, which effects regulator efficiency and FET thermal management requirements. The power dissipated by the MOSFETs may be estimated as follows: Switching MOSFET: Power + ILOAD2

RDSON

duty cycle


(1 * duty cycle)

RDSON


ƪ

1.35 * 1.15 + 16% 1.25

RDSON OF SYNCH FET)


ƫ

2. Mismatch due to L/W. The variation in L/W is governed by variations due to the PCB manufacturing process that affect the geometry and the power dissipation capability of the droop resistor. The error due to L/W mismatch is typically 1.0%. 3. Thermal Considerations. Due to I2 × R power losses the surface temperature of the droop resistor will increase causing the resistance to increase. Also, the ambient temperature variation will contribute to the increase of the resistance, according to the formula:



4848.5


Perioid

R + R20[1 ) 20(T * 20)]

(1 * duty cycle) 4848.5

where: R20 = resistance at 20°C

where: Period +

+ 0.00393 °C


T = operating temperature R = desired droop resistor value For temperature T = 50°C, the % R change = 12%

Schottky Diode for Synchronous FET

For synchronous operation, a Schottky diode may be placed in parallel with the synchronous FET to conduct the inductor current upon turn off of the switching FET to improve efficiency. The CS5166H reference circuit does not use this device due to it’s excellent design. Instead, the body diode of the synchronous FET is utilized to reduce cost and conducts the inductor current. For a design operating at 200 kHz or so, the low non–overlap time combined with Schottky forward recovery time may make the benefits of this device not worth the additional expense. The power dissipation in the synchronous MOSFET due to body diode conduction can be estimated by the following equation: Power + VBD

ILOAD

conduction time



In order to determine the droop resistor value the nominal voltage drop across it at full load has to be calculated. This voltage drop has to be such that the output voltage full load is above the minimum DC tolerance spec. VDROOP(TYP) +

switching frequency

14.2 A

100 ns

[VDAC(MIN) * VDC(MIN)] 1 ) RDROOP(TOLERANCE)

Example: for a 300 MHz PentiumII, the DC accuracy spec is 2.74 < VCC(CORE) < 2.9 V, and the AC accuracy spec is 2.67 V < VCC(CORE) < 2.93 V. The CS5166H DAC output voltage is +2.796 V < VDAC < +2.853 V. In order not to exceed the DC accuracy spec, the voltage drop developed across the resistor must be calculated as follows:

Where VBD = the forward drop of the MOSFET body diode. For the CS5166H demonstration board: Power + 1.6 V

16% 1.0% 12% 29%

200 kHz + 0.45 W

This is only 1.1% of the 40 W being delivered to the load. “Droop” Resistor for Adaptive Voltage Positioning

Adaptive voltage positioning is used to help keep the output voltage within specification during load transients. To implement adaptive voltage positioning a “Droop Resistor” must be connected between the output inductor


CS5166H VDROOP(TYP) +

[VDAC(MIN) * VDC PENTIUMII(MIN)] 1 ) RDROOP(TOLERANCE)

deviation from the nominal output voltage is 25 mV smaller than it would be if there was no droop resistor. Similarly at full load the regulator output is pre–positioned at 18 mV below the nominal voltage before a load turn–off. The total voltage increase due to a load turn–off is ∆V–18 mV and the deviation from the nominal output voltage is 18 mV smaller than it would be if there was no droop resistor. This is because the output capacitors are pre–charged to value that is either 25 mV above the nominal output voltage before a load turn–on or, 18 mV below the nominal output voltage before a load turn–off (see Figure 16). Obviously, the larger the voltage drop across the droop resistor (the larger the resistance), the worse the DC and load regulation, but the better the AC transient response.

+ 2.796 V * 2.74 V + 43 mV 1.3

With the CS5166H DAC accuracy being 1.0%, the internal error amplifier’s reference voltage is trimmed so that the output voltage will be 25 mV high at no load. With no load, there is no DC drop across the resistor, producing an output voltage tracking the error amplifier output voltage, including the offset. When the full load current is delivered, a drop of –43 mV is developed across the resistor. Therefore, the regulator output is pre–positioned at 25 mV above the nominal output voltage before a load turn–on. The total voltage drop due to a load step is ∆V–25 mV and the

VIN

CS5166H IFB

RFB

Current Limit Comparator VFB

+

Q1 L

RDROOP

Q2

ISENSE

–

VOUT COUT

VTH ISENSE

RISENSE ISENSE

Figure 30. Circuit Used to Determine the Voltage Across the Droop Resistor that will Trip the Internal Current Sense Comparator Current Limit Setpoint Calculations

limits are: 55 mV < VTH < 130 mV. Also, there is a 29% total variation in RSENSE as discussed in the previous section. We select the value of the current sensing element (embedded PCB trace) for the minimum current limit setpoint:

The following is the design equations used to set the current limit trip point by determining the value of the embedded PCB trace used as a current sensing element. The current limit setpoint has to be higher than the normal full load current. Attention has to be paid to the current rating of the external power components as these are the first to fail during an overload condition. The MOSFET continuous and pulsed drain current rating at a given case temperature has to be accounted for when setting the current limit trip point. For example the IRL 3103S (D2 PAK) MOSFET has a continuous drain current rating of 45 A at VGS = 10 V and TC = 100°C. Temperature curves on MOSFET manufacturers’ data sheets allow the designer to determine the MOSFET drain current at a particular VGS and TJ (junction temperature). This, in turn, will assist the designer to set a proper current limit, without causing device breakdown during an overload condition. For 300 MHz Pentium II CPU the full load is 14.2 A. The internal current sense comparator current limit voltage

RSENSE(MAX) + RSENSE

VTH(MIN) å RSENSE ICL(MIN)

1.29 + 55 mV å 14.2 A

1.29 + 3.87 m å RSENSE + 3.0 m

We calculate the range of load currents that will cause the internal current sense comparator to detect and overload condition. From the overcurrent detection data section on page 2095. Nominal Current Limit Setpoint VTH(TYP) + 76 mV ICL(NOM) + R

VTH(TYP) SENSE(NOM)

Maximum Current Limit Setpoint


CS5166H Therefore, ICL(NOM) + 76 mV + 25.3 3.0 m

RSENSE(MAX) + 58.3 mV + 4.1 m 14.2 A

VTH(MAX) + 110 mV

RSENSE(NOM) +

Therefore,

The range of load currents that will cause the internal current sense comparator to detect an overload condition is as follows: Nominal Current Limit Setpoint

ICL(MAX) + 110 mV 110 mV 110 mV + + + 51.6 A 3.0 m 0.71 RSENSE(MIN) RSENSE 0.71

VTRIP(NOM) ICL(NOM) + RSENSE(NOM)

Therefore, the range of load currents that will cause the internal current sense comparator to detect an overload condition through a 3.0 mΩ embedded PCB trace is: 14.2 A < ICL < 51.6 A, with 25.3 A being the nominal overload condition. There may be applications whose layout will require the use of two extra filter components, a 510 Ω resistor in series with the ISENSE pin, and a 0.1 µF capacitor between the ISENSE and VFB pins. These are needed for proper current limit operation and the resistor value is layout dependent. This series resistor affects the calculation of the current limit setpoint, and has to be taken into account when determining an effective current limit. The calculations below show how the current limit setpoint is determined when this 510 Ω is taken into consideration. VTRIP + VTH ) (ISENSE

RISENSE) * (RFB

Therefore, ICL(NOM) + 90.97 mV + 28.6 A 3.18 m

Maximum Current Limit Setpoint VTRIP(MAX) ICL(MAX) + RSENSE(MAX)

Therefore, 135 mV ICL(MAX) + + 60 A 3.18 m 0.71

Therefore, the range of load currents that will cause the internal current sense comparator to detect an overload condition through a 3.0 mΩ embedded PCB trace is: 14.2 A < ICL 60 A, with 28.6 A being the nominal overload condition.

IFB)

Where: VTRIP = voltage across the droop resistor that trips the ISENSE comparator. VTH = internal ISENSE comparator threshold ISENSE = ISENSE bias current RISENSE = ISENSE pin 510 Ω filter resistor RFB = VFB pin 3.3 k filter resistor IFB = VFB bias current Minimum current sense resistor (droop resistor) voltage drop required for current limit when RISENSE is used VTRIP(MIN) + 55 mV ) (13 A

510) * (3.3 k



1.0 A)

0.1 A)

+ 76 mV ) 15.3 mV * 0.33 mV + 90.97 mV

t)

Response Droop + 43 mV + 43 mV + 3.0 m 14.2 A IOUT

Maximum current sense resistor (droop resistor) voltage drop required for current limit when RISENSE is used VTRIP(NOM) + 110 mV ) (50 A

L (W

For most PCBs the copper thickness, t, is 35 µm (1.37 mils) for one ounce copper. ρ = 717.86 µΩ–mil For a Pentium II load of 14.2 A the resistance needed to create a 43 mV drop at full load is:

Nominal current sense resistor (droop resistor) voltage drop required for current limit when RISENSE is used 510) * (3.3 k

L or R + A

where: A = W × t = cross–sectional area ρ = the copper resistivity (µΩ – mil) L = length (mils) W = width (mils) t = thickness (mils)

+ 55 mV ) 6.6 mV * 3.3 mV + 58.3 mV

VTRIP(NOM) + 76 mV ) (30 A

RSENSE(MAX) + 4.1 mm + 3.18 m 1.29 1.29

The resistivity of the copper will drift with the temperature according to the following guidelines:

510)

+ 110 mV ) 25.5 mV + 135.5 mV

R + 12% @ TA + ) 50°C

The value of RSENSE (current sense PCB trace) is then calculated:

R + 34% @ TA + ) 100°C


CS5166H 5.0 V 1200 µF/10 V × 3

12 V IRL3103S

1.0 µF COFF SS 0.1 µF

COMP VID0

0.1 µF

CS5166H

330 pF

VCC GATE(H)

1.2 µH

3.0 mΩ 510

ISENSE

1200 µF/ 10 V × 5

0.1 µF

IRL3103S

GATE(L)

VID1 VID2

PGND

VID3

LGND

2.8 V/30 A Power Supply

PWRGD

3.3 k

VID4 PWRGD VFB

VID4 VID3

1000 pF

VID2 VID1 VID0

5.0 V 1200 µF/ 10 V × 3

12 V

1.0 µF

IRL3103S

330 pF 0.1 µF

COMP VID0 VID1 VID2

CS5166H

VCC GATE(H) COFF SS

1.2 µH

3.0 mΩ 510

ISENSE 0.1 µF IRL3103S

GATE(L) PGND

VID3

LGND

VID4

VFB

3.3 k

1000 pF

Figure 31. Current Sharing of a 2.8 V/30 A Power Supply Using Two CS5166H Synchronous Buck Regulators Droop Resistor Width Calculations

Droop Resistor Length Calculation

The droop resistor must have the ability to handle the load current and therefore requires a minimum width which is calculated as follows (assume one ounce copper thickness):

L+

RDROOP

+ 0.0030

I W + LOAD 0.05

W

284 717.86

t 1.37 + 1626 mil + 4.13 cm

Implementing Current Sharing Using the “Droop Resistor”

where: W = minimum width (in mils) required for proper power dissipation, and ILOAD Load Current Amps. The Pentium II maximum load current is 14.2 A. Therefore:

In addition to improving load transient performance, the CS5166H V2 control method allows the droop resistor to provide the additional capability to easily implement current sharing. Figure 31 shows a simplified schematic of two current sharing synchronous buck regulators. Each buck

W + 14.2 A + 284 mils + 0.7213 cm 0.05


CS5166H necessary to obtain perfect matching. Keeping output currents within ± 10% is usually acceptable. For microprocessor applications, the value of the droop resistor must be selected to optimize adaptive voltage positioning, current sharing, current limit and efficiency. Current sharing is realized by simply connecting the COMP pins of the respective buck regulators, as shown in Figure 31. Figure 32 shows operation with no load. In this case, there is insufficient output voltage ripple across the droop resistor to produce complete synchronization. Duty Cycle is close to the theoretical 56% (VOUT/VIN) resulting in a switching frequency of approximately 275 kHz. Figure 34 shows operation with a 30 Amp load. Synchronization between the two regulators is now obtained due to increased ripple voltage. Increases losses cause the V2 control loop to increase on–time to compensate. This results in a larger duty cycle and a corresponding decrease in switching frequency to 233 kHz.

regulator’s droop resistor is terminated at the load. The PWM control signal from each Error Amp is connected together, causing the inner PWM loop to regulate to a common voltage. Since the voltage at each resistor terminal is the same, this configuration results in equal voltage being applied across each matched droop resistor. The result is equal current flowing through each buck regulator. An additional benefit is that synchronization to a common switching frequency tends to be achieved because each regulator shares a common PWM ramp signal. In practice, each buck regulator will regulate to a slightly different output voltage due to mismatching of the PWM comparators, slope of the PWM ramp (output voltage ripple), and propagation delays. At light loads, the results can be very poor current sharing. With zero output current, some regulators may be sourcing current while others may be sinking current. This results in additional power dissipation and lower efficiency than would be obtained by a single regulator. This is usually not an issue since efficiency is most important when a supply is fully loaded. This effect is similar to the difference in efficiency between synchronous and non–synchronous buck regulators. Synchronous buck regulators have lower efficiency at light loads because inductor current is always continuous, flowing from the load to ground during switch off–time through the synchronous rectifier. Under full load conditions, the synchronous design is more efficient due to the lower voltage drop across the synchronous rectifier. Likewise, the efficiency of droop sharing regulators will be lower at light loads due to the continuous current flow in the droop resistors. Efficiency at heavy loads tends to be higher due to reduced I2R losses. The output current of each regulator can be calculated from:

Trace 1 = Output voltage ripple. Trace 2 = Buck regulator #1 inductor switching node. Trace 3 = Buck regulator #2 inductor switching node.

(V * VOUT) IN + OUT(N) RDROOP(N)

Figure 32. No Load Waveforms

where: VOUT(N) and RDROOP(N) are the output voltage and droop resistance of a particular regulator and VOUT is the system output voltage. Output current is the sum of each regulator’s current: IOUT + I1 ) I2 ) AAA ) IN

Current sharing improves with increasing load current. The increasing voltage drop across the droop resistor due to increasing load current eventually swamps out the differences in regulator output voltages. If a large enough voltage can be developed across the droop resistors, current sharing accuracy will be determined solely by their matching. To realize the benefits of current sharing, it is not


CS5166H Inductor Ripple Current Ripple Current +

[(VIN * VOUT) VOUT] (Switching Frequency L VIN)

Example: VIN = +5.0 V, VOUT = +2.8 V, ILOAD = 14.2 A, L = 1.2 µH, Freq = 200 kHz Ripple Current +

[(5.0 V * 2.8 V) 2.8 V] + 5.1 A [200 kHz 1.2 H 5.0 V]

Output Ripple Voltage VRIPPLE + Inductor Ripple Current

Output Capacitor ESR

Example: VIN = +5.0 V, VOUT = +2.8 V, ILOAD = 14.2 A, L = 1.2 µH, Switching Frequency = 200 kHz Output Ripple Voltage = 5.1 A × Output Capacitor ESR (from manufacturer’s specs) ESR of Output Capacitors to limit Output Voltage Spikes


Figure 33. 15 A Load Transient Waveforms

ESR +

VOUT IOUT

This applies for current spikes that are faster than regulator response time. Printed Circuit Board resistance will add to the ESR of the output capacitors. In order to limit spikes to 100 mV for a 14.2 A Load Step, ESR = 0.1/14.2 = 0.007 Ω Inductor Peak Current Peak Current + Maximum Load Current )

ǒRipple 2CurrentǓ

Example: VIN = +5.0 V, VOUT = +2.8 V, ILOAD = 14.2 A, L = 1.2 µH, Freq = 200 kHz


Figure 34. 30 A Load Waveforms

Peak Current + 14.2 A ) (5.1ń2) + 16.75 A

Figure 33 shows supply response to a 15 A load step with a 30 A/µs slew rate. The V2 control loop immediately forces the duty cycle to 100%, ramping the current in both inductors up. A voltage spike of 136 mV due to output capacitor impedance occurs. The inductive component of the spike due to ESL recovers within several microseconds. The resistive component due to ESR decreases as inductor current replaces capacitor current. The benefit of adaptive voltage positioning in reducing the voltage spike can readily be seen. The difference in DC voltage and duty cycle can also be observed. This particular transient occurred near the beginning of regulator off time, resulting in a longer recovery time and increased voltage spike.

A key consideration is that the inductor must be able to deliver the Peak Current at the switching frequency without saturating. Response Time to Load Increase

(limited by Inductor value unless Maximum On–Time is exceeded) Response Time +

L IOUT (VIN * VOUT)

Example: VIN = +5.0 V, VOUT = +2.8 V, L = 1.2 µH, 14.2 A change in Load Current Response Time +

Output Inductor

1.2 H 14.2 A + 7.7 s (5.0 V * 2.8 V)

Response Time to Load Decrease


(limited by Inductor value) Response Time +


L

Change in IOUT VOUT

CS5166H Example: VOUT = +2.8 V, 14.2 A change in Load Current, L = 1.2 µH Response Time +

1.2 H 14.2 A + 6.1 s 2.8 V

2.0 µH


33 Ω


1000 pF

Figure 35. Filter Components 2.0 µH +

THERMAL MANAGEMENT

1200 µF × 3.0/16 V



Figure 36. Input Filter Layout Guidelines

When laying out the CPU buck regulator on a printed circuit board, the following checklist should be used to ensure proper operation of the CS5166H. 1. Rapid changes in voltage across parasitic capacitors and abrupt changes in current in parasitic inductors are major concerns for a good layout. 2. Keep high currents out of sensitive ground connections. Avoid connecting the IC GND (LGND) between the source of the lower FET and the input capacitor GND. 3. Avoid ground loops as they pick up noise. Use star or single point grounding. 4. For high power buck regulators on double–sided PCBs a single large ground plane (usually the bottom) is recommended. 5. Even though double sided PCBs are usually sufficient for a good layout, four–layer PCBs are the optimum approach to reducing susceptibility to noise. Use the two internal layers as the +5.0 V and GND planes, the top layer for the power connections and component vias, and the bottom layer for the noise sensitive traces.

TJ(MAX) * TA Power




CS5166H 12. Place the VFB filter capacitor right at the VFB pin (pin 16). 13. The “Droop” Resistor (embedded PCB trace) has to be wide enough to carry the full load current. 14. Place the VCC bypass capacitor as close as possible to the VCC pin and connect it to the PGND pin of the IC. Connect the PGND pin directly to the GND plane. 15. Create a subground (local GND) plane preferably on the PCB top layer and under the IC controller. Connect all logic capacitor returns and the LGND pin of the IC to this place. Connect the subground plane to the main GND plane using a minimum of four (4) vias.

6. Keep the inductor switching node small by placing the output inductor, switching and synchronous FETs close together. 7. The FET gate traces to the IC must be as short, straight, and wide as possible. Ideally, the IC has to be placed right next to the FETs. 8. Use fewer, but larger output capacitors, keep the capacitors clustered, and use multiple layer traces with heavy copper to keep the parasitic resistance low. 9. Place the switching FET as close to the +5.0 V input capacitors as possible. 10. Place the output capacitors as close to the load as possible. 11. Place the VFB filter resistor in series with theVFB pin (pin 16) right at the pin.


CS5166H +12 V +12 V

1N5818

1200 µF/16 V × 3

1N5818 0.1 µF

18 Ω 18 V 1N4746 1.0 µF

Droop Resistor IRL3103S (Embedded PCB trace)

VCC

COFF

1000 pF

GATE(H) SS CS5166H VFB COMP

0.1 µF 0.1 µF

1.2 µH

3.0 mΩ VCC

3.3 k

1000 pF

IRL3103S

GATE(L)

VID0 VID1 PGND VID2 VID3 LGND VID4 ISENSE PWRGD

1200 µF/10 V ×5

VSS PWRGD

0.1 µF

PENTIUM II SYSTEM

510


Figure 37. Additional Application Diagram, +12 V to +2.8 V @ 14.2 A for 300 MHz Pentium II +5.0 V

MBRS120 1.0 µF

MBRS120

1200 µF/10 V × 3

MBRS120 1.0 µF VCC VID0 VID1

VGATE(L)

VID3 VID4

3.0 mΩ VCC

COFF SS

VSS

510

ISENSE PWRGD

0.1 µF

VFB LGND

0.1 µF

1200 µF/10 V ×5

IRL3103S

PGND

COMP 0.1 µF

1.2 µH

CS5166H

VID2

330 pF

VGATE(H)

Droop Resistor (Embedded PCB trace)

IRL3103S

3.3 k

PWRGD PENTIUM II SYSTEM

1000 pF


Figure 38. Additional Application Diagram, +5.0 V to +2.8 V @ 14.2 A for 300 MHz Pentium II



SO–16L

Unit

RΘJC

Typical

23

°C/W

RΘJA

Typical

105

°C/W


&# ! 89 = ,& ''""! The CS51312 is a synchronous dual NFET Buck Regulator Controller. It is designed to power the core logic of the latest high performance CPUs and ASICs from a single 12 V input. It uses the V2 control method to achieve the fastest possible transient response and best overall regulation. It incorporates many additional features required to ensure the proper operation and protection of the CPU and Power system. The CS51312 provides the industry’s most highly integrated solution, minimizing external component count, total solution size, and cost. The CS51312 is specifically designed to power Intel’s Pentium II processor and includes the following features: 5–bit DAC with 1.2% tolerance, Power–Good output, overcurrent hiccup mode protection, overvoltage protection, VCC monitor, Soft Start, adaptive voltage positioning, adaptive FET non–overlap time, and remote sense. The CS51312 will operate over a 9.0 V to 20 V (VCC2) range using either single or dual input voltage and is available in 16 lead narrow body surface mount package. Features Synchronous Switching Regulator Controller for CPU VCORE Dual N–Channel MOSFET Synchronous Buck Design V2 Control Topology 200 ns Transient Loop Response 5–Bit DAC with 1.2% Tolerance Hiccup Mode Overcurrent Protection 40 ns Gate Rise and Fall Times (3.3 nF Load) 65 ns Adaptive FET Non–Overlap Time Adaptive Voltage Positioning Power Good Output Monitors Regulator Output 5.0 V/12 V or 12 V–Only Operation VCC Monitor Provides Undervoltage Lockout OVP Output Monitors Regulator Output Multifunctional COMP Pin Provides ENABLE, Soft Start, and Hiccup Timing in Addition to Control Loop Compensation

• • • • • • • • • • • • • •



2119

http://onsemi.com

SO–16 D SUFFIX CASE 751B

16 1

MARKING DIAGRAM 16 CS51312 AWLYWW 1 A WL, L YY, Y WW, W


PIN CONNECTIONS 1

16

VID0 VID1 VID2 VID3 VID4 VFB VOUT VCC1

COMP COFF PWRGD OVP GATE(L) GND GATE(H) VCC2


Package

Shipping

CS51312GD16

SO–16

48 Units/Rail

CS51312GDR16

SO–16

2500 Tape & Reel


CS51312 12 V

C1 1.0 µF

D1 SS16GICT–ND

12 V C2 C3 C4 220 µF

R1 22 Ω

+

+

+

16SV220

C6 0.01 µF

FY10AAJ–03A D2 ZM4746ACT–ND

Q1

FY10AAJ–03A

C10 1.0 µF

VCC2

VCC1

COFF

C19 1000 pF

R4 0.004 Ω

+

VFB

COMP

GATE(H)

VID0 VID1

C11 C12 C13 L1 1.2 µH

+

Q2

+

R3 10 k

FY10AAJ–03A

C14

+

C9 0.01 µF

R2 200

+

CS51312

VID2

GND

VID3

OVP

VID4

PWRGD

FY10AAJ–03A Q4

VOUT

DAC ENABLE

D3 SS12GICT–ND 1 OVP 1 PWRGD

Figure 1. Application Diagram, 12 V to 16 A High Performance Converter


1.25 V to 3.5 V

470 µF T510X477K006AS4394 C15

Q3

GATE(L)

470 µF

CS51312 ABSOLUTE MAXIMUM RATINGS* Rating Operating Junction Temperature, TJ Lead Temperature Soldering:


Storage Temperature Range, TS ESD Susceptibility

Value

Unit

150

°C

230 peak

°C

–65 to +150

°C

2.0

kV



Pin Symbol

VMAX

VMIN

ISOURCE

ISINK

IC Bias and Low Side Driver Power Input

VCC1

16

–0.3

N/A


IC High Side Driver Power Input

VCC2

20 V

–0.3 V

N/A


Compensation Pin

COMP

6.0 V

–0.3 V

1.0 mA

5.0 mA

Voltage Feedback Input, Output Voltage Sense Pin, Voltage ID DAC Inputs

VFB, VOUT, VID0–4

6.0 V

–0.3 V

1.0 mA

1.0 mA

Off–Time Pin

COFF

6.0 V

–0.3 V

1.0 mA

50 mA


GATE(H)

20 V

–0.3 V DC




GATE(L)

16 V

–0.3 V DC



Power Good Output

PWRGD

6.0 V

–0.3 V

1.0 mA

30 mA


OVP

15 V

–0.3 V

30 mA

1.0 mA

Ground

GND

0V

0V


N/A


CS51312 ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCC1 < 14 V; 9.0 V ≤ VCC2 ≤ 20 V; 2.0 V DAC Code (VID4 = VID3 = VID2 = VID1 = 0, VID0 = 1.0) CGATE(H) = CGATE(L) = 3.3 nF, COFF = 390 pF; unless otherwise specified.) Characteristic

Test Conditions

Voltage Identification DAC Measure VFB = VCOMP, VCC = 12 V. Note 2 755C 3 TJ 3 1255C

255C 3 TJ 3 755C

VID4

VID3

VID2

VID1

VID0

Min

Typ

Max

±Tol

Min

Typ

Max

±Tol

Unit

1

0

0

0

0

3.483

3.525

3.567

1.2%

3.455

3.525

3.596

2.0%

V

1

0

0

0

1

3.384

3.425

3.466

1.2%

3.357

3.425

3.494

2.0%

V

1

0

0

1

0

3.285

3.325

3.365

1.2%

3.259

3.325

3.392

2.0%

V

1

0

0

1

1

3.186

3.225

3.264

1.2%

3.161

3.225

3.290

2.0%

V

1

0

1

0

0

3.087

3.125

3.163

1.2%

3.063

3.125

3.188

2.0%

V

1

0

1

0

1

2.989

3.025

3.061

1.2%

2.965

3.025

3.086

2.0%

V

1

0

1

1

0

2.890

2.925

2.960

1.2%

2.875

2.925

2.975

1.7%

V

1

0

1

1

1

2.791

2.825

2.859

1.2%

2.777

2.825

2.873

1.7%

V

1

1

0

0

0

2.692

2.725

2.758

1.2%

2.679

2.725

2.771

1.7%

V

1

1

0

0

1

2.594

2.625

2.657

1.2%

2.580

2.625

2.670

1.7%

V

1

1

0

1

0

2.495

2.525

2.555

1.2%

2.482

2.525

2.568

1.7%

V

1

1

0

1

1

2.396

2.425

2.454

1.2%

2.389

2.425

2.461

1.5%

V

1

1

1

0

0

2.297

2.325

2.353

1.2%

2.290

2.325

2.360

1.5%

V

1

1

1

0

1

2.198

2.225

2.252

1.2%

2.192

2.225

2.258

1.5%

V

1

1

1

1

0

2.099

2.125

2.151

1.2%

2.093

2.125

2.157

1.5%

V

0

0

0

0

0

2.050

2.075

2.100

1.2%

2.044

2.075

2.106

1.5%

V

0

0

0

0

1

2.001

2.025

2.049

1.2%

1.995

2.025

2.055

1.5%

V

0

0

0

1

0

1.953

1.975

1.997

1.1%

1.945

1.975

2.005

1.5%

V

0

0

0

1

1

1.904

1.925

1.946

1.1%

1.896

1.925

1.954

1.5%

V

0

0

1

0

0

1.854

1.875

1.896

1.1%

1.847

1.875

1.903

1.5%

V

0

0

1

0

1

1.805

1.825

1.845

1.1%

1.798

1.825

1.852

1.5%

V

0

0

1

1

0

1.755

1.775

1.795

1.1%

1.748

1.775

1.802

1.5%

V

0

0

1

1

1

1.706

1.725

1.744

1.1%

1.699

1.725

1.751

1.5%

V

0

1

0

0

0

1.656

1.675

1.694

1.1%

1.650

1.675

1.700

1.5%

V

0

1

0

0

1

1.607

1.625

1.643

1.1%

1.601

1.625

1.649

1.5%

V

0

1

0

1

0

1.558

1.575

1.593

1.1%

1.551

1.575

1.599

1.5%

V

0

1

0

1

1

1.508

1.525

1.542

1.1%

1.502

1.525

1.548

1.5%

V

0

1

1

0

0

1.459

1.475

1.491

1.1%

1.453

1.475

1.497

1.5%

V

0

1

1

0

1

1.409

1.425

1.441

1.1%

1.404

1.425

1.446

1.5%

V

0

1

1

1

0

1.360

1.375

1.390

1.1%

1.354

1.375

1.396

1.5%

V

0

1

1

1

1

1.310

1.325

1.340

1.1%

1.305

1.325

1.345

1.5%

V

1

1

1

1

1

1.225

1.250

1.275

2.0%

1.225

1.250

1.275

2.0%

V

2. The IC power dissipation in a typical application with VCC = 12 V, switching frequency fSW = 250 kHz, 50 nc MOSFETs and RθJA = 115°C/W yields an operating junction temperature rise of approximately 52°C, and a junction temperature of 77°C with an ambient temperature of 25°C.


CS51312 ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCC1 < 14 V; 9.0 V ≤ VCC2 ≤ 20 V; 2.0 V DAC Code (VID4 = VID3 = VID2 = VID1 = 0, VID0 = 1.0) CGATE(H) = CGATE(L) = 3.3 nF, COFF = 390 pF; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

–

0.01

–

%/V

Voltage Identification DAC (continued) Line Regulation

9.0 V ≤ VCC ≤ 14 V

Input Threshold


1.0

1.25

2.4

V

Input Pull–Up Resistance


25

50

100

kΩ

5.48

5.65

5.82

V

–7.0

0.1

7.0

µA

Pull–Up Voltage

–


0.2 V ≤ VFB ≤ 3.5 V

COMP Source Current

VCOMP = 1.2 V to 3.6 V, VFB = 1.9 V

15

30

60

µA

COMP Sink Current

VCOMP = 1.2 V, VFB = 2.1 V

30

60

120

µA

Open Loop Gain

CCOMP = 0.1 µF

–

80

–

dB


CCOMP = 0.1 µF

–

50

–

kHz

PSRR @ 1.0 kHz

CCOMP = 0.1 µF

–

70

–

dB

Transconductance

–

–

32

–

mmho

Output Impedance

–

–

0.5

–

MΩ


Measure VCC1/2 – GATE(L)/(H)

–

1.2

2.1

V


Measure GATE(L)/(H)

–

1.0

1.5

V

Rise Time

1.6 V < GATE(H)/(L) < (VCC1/2 – 2.5 V)

–

40

80

ns

Fall Time

(VCC1/2 – 2.5 V) > GATE(L)/(H) > 1.6 V

–

40

80

ns


GATE(H) < 2.0 V, GATE(L) > 2.0 V, VCC1/2 = 12 V

30

65

110

ns


GATE(L) < 2.0 V, GATE(H) > 2.0 V, VCC1/2 = 12 V

30

65

110

ns

GATE Pull–Down

Resistance to GND. Note 3

20

50

115

kΩ

0 V ≤ VOUT ≤ 3.5 V

77

86

101

mV

0.2

0.25

0.3

V

Overcurrent Protection OVC Comparator Offset Voltage Discharge Threshold Voltage

–

VOUT Bias Current

0.2 V ≤ VOUT ≤ 3.5 V

–7.0

0.1

7.0

µA

OVC Latch Discharge Current

VCOMP = 1.0 V

100

800

2500

µA

PWM Comparator Offset Voltage

0 V ≤ VFB ≤ 3.5 V

0.99

1.1

1.23

V

Transient Response

VFB = 0 to 3.5 V

–

200

300

ns

1.0

1.6

2.3

µs

PWM Comparator

COFF Off–Time

–

Charge Current

VCOFF = 1.5 V

–

550

–

µA

Discharge Current

VCOFF = 1.5 V

–

25

–

mA



CS51312 ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCC1 < 14 V; 9.0 V ≤ VCC2 ≤ 20 V; 2.0 V DAC Code (VID4 = VID3 = VID2 = VID1 = 0, VID0 = 1.0) CGATE(H) = CGATE(L) = 3.3 nF, COFF = 390 pF; unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

Power Good Output PWRGD Sink Current

VFB = 1.7 V, VPWRGD = 1.0 V

0.5

4.0

15

mA

PWRGD Upper Threshold

% of Nominal DAC Code

5.0

8.5

12

%

PWRGD Lower Threshold


–12

–8.5

–5.0

%

PWRGD Output Low Voltage


–

0.2

0.3

V

Overvoltage Protection (OVP) Output OVP Source Current

OVP = 1.0 V

1.0

10

25

mA

OVP Threshold


5.0

8.5

12

%

OVP Pull–Up Voltage

IOVP = 1.0 mA, VCC1 – VOVP

–

1.1

1.5

V

General Electrical Specifications VCC1 Monitor Start Threshold

–

7.9

8.4

8.9

V

VCC1 Monitor Stop Threshold

–

7.6

8.1

8.6

V

0.15

0.3

0.6

V

Hysteresis

Start–Stop

VCC1 Supply Current

No Load on GATE(H), GATE(L)

–

9.5

16

mA

VCC2 Supply Current

No Load on GATE(H), GATE(L)

–

2.5

4.5

mA


PIN SYMBOL

FUNCTION

1, 2, 3, 4, 5

VID0–VID4

Voltage ID DAC inputs. These pins are internally pulled up to 5.65 V if left open. VID4 selects the DAC range. When VID4 is high (logic one), the Error Amp reference range is 2.125 V to 3.525 V with 100 mV increments. When VID4 is low (logic zero), the Error Amp reference voltage is 1.325 V to 2.075 V with 50 mV increments.

6

VFB

7

VOUT

Current limit comparator inverting input.

8

VCC1

Input power supply pin for the internal circuitry and low side gate driver. Decouple with filter capacitor to GND.

9

VCC2

Input power supply pin for the high side gate driver. Decouple with filter capacitor to GND.

10

GATE(H)

11

GND

12

GATE(L)

13

OVP

Overvoltage protection pin. Drives high when overvoltage condition is detected on VFB.

14

PWRGD

Power Good Output. Open collector output drives low when VFB is out of regulation.

15

COFF

16

COMP

Error amp inverting input, PWM comparator non–inverting input, current limit comparator non–inverting input, PWRGD and OVP comparator input.

High side switch FET driver pin. Ground pin and IC substrate connection. Low side synchronous FET driver pin.

Off–Time Capacitor pin. A capacitor from this pin to GND sets the off time for the regulator. Error amp output. PWM comparator inverting input. A capacitor on this pin provides error amp compensation, and determines the Soft Start and hiccup timing. Pulling COMP below 1.1 V (typ) turns off both GATE drivers and shuts down the regulator.


CS51312 COMP

VFB 1.1 V + –

COFF PWM COMP + –

EA

Off Time

– +

Discharge COMP

Current Limit VOUT

86 mV + –

+ –

– +

R Q

+ –

Fault Latch

0.25 V

S

VID0 UVLO

VID1

VCC1

DAC

VID2 VID3

VCC2

VID4

GATE(H)

Nonoverlap Logic

+ –

GATE(L)

+ – VCC

OVP

PWRGD



GND

CS51312 TYPICAL PERFORMANCE CHARACTERISTICS 150

150 VCC = 12 V TA = 25°C

100 75 50

100 75 50

25 0

VCC = 12 V TA = 25°C

125

Risetime (ns)

25

0

2000 4000

0

6000 8000 10000 12000 14000 16000

0

2000 4000



Figure 3. GATE(H) and GATE(L) Falltime vs. Load Capacitance

Figure 4. GATE(H) and GATE(L) Risetime vs. Load Capacitance

0.10

0.10 VCC = 12 V 0.05 Output Error (%)

0.05

0

0

–0.05

–0.05

VCC = 12 V TA = 25°C VID4 = 0

–0.10

–0.10


Figure 5. DAC Output Voltage vs. Temperature, DAC Code = 00001

Figure 6. Percent Output Error vs. DAC Output Voltage Setting, VID4 = 0

Output Error (%)

0.35 0.30 0.25 0.20 0.15 0.10 0.05

0 –0.05


Figure 7. Percent Output Error vs. DAC Output Voltage Setting, VID4 = 1


3.525

3.425

3.225

3.025

2.925

2.725

2.625

2.525

2.425

2.325

2.225

–0.25

2.125

–0.20

3.125

VCC = 12 V TA = 25°C VID4 = 1

–0.10 –0.15

2.075

2.025

1.975

1.925

1.875

1.825

1.775


1.725

–0.20

1.625

120

1.675

100

1.575

80

1.525

60

1.475

40

1.425

20

1.375

0

1.325

–0.15

–0.15

2.825

DAC Output Voltage Deviation (%)

6000 8000 10000 12000 14000 16000

3.325

Falltime (ns)

125

CS51312 APPLICATIONS INFORMATION THEORY OF OPERATION

The main purpose of this ‘slow’ feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. Line and load regulation are drastically improved because there are two independent voltage loops. A voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. The V2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load.

V2 Control Method

The V2 method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the value of the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current. The V2 control method is illustrated in Figure 8. The output voltage is used to generate both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required.

Constant Off–Time

To minimize transient response, the CS51312 uses a Constant Off–Time method to control the rate of output pulses. During normal operation, the Off–Time of the high side switch is terminated after a fixed period, set by the COFF capacitor. Every time the VFB pin exceeds the COMP pin voltage an Off–Time is initiated. To maintain regulation, the V2 Control Loop varies switch On–Time. The PWM comparator monitors the output voltage ramp, and terminates the switch On–Time. Constant Off–Time provides a number of advantages. Switch Duty Cycle can be adjusted from 0 to 100% on a pulse–by pulse basis when responding to transient conditions. Both 0% and 100% Duty Cycle operation can be maintained for extended periods of time in response to Load or Line transients.

PWM Comparator GATE(H) – C + GATE(L) Output Voltage Feedback VFB

Ramp Signal


E Error Signal

– +

Reference Voltage


Programmable Output

The CS51312 is designed to provide two methods for programming the output voltage of the power supply. A five bit on board digital to analog converter (DAC) is used to program the output voltage within two different ranges. The first range is 2.125 V to 3.525 V in 100 mV steps, the second is 1.325 V to 2.075 V in 50 mV steps, depending on the digital input code. If all five bits are left open, the CS51312 enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feedback to the VFB pin, as in traditional controllers. The CS51312 is specifically designed to meet or exceed Intel’s Pentium II specifications.

A change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the V2 control scheme to compensate the duty cycle. Since the change in inductor current modifies the ramp signal, as in current mode control, the V2 control scheme has the same advantages in line transient response. A change in load current will have an affect on the output voltage, altering the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. Load transient response is determined only by the comparator response time and the transition speed of the main switch. The reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. The error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop.

Error Amplifier

The COMP pin is the output of the error amplifier. A capacitor to GND compensates the error amplifier loop.


CS51312 The Error Amp Capacitor connected to the COMP pin is charged by a 30 µA current source. This capacitor must be charged to 1.1 V (typ) so that it exceeds the PWM comparator’s offset before the V2 PWM control loop permits switching to occur. When VCC1 has exceeded 8.4 V and COMP has charged to 1.1 V, the upper Gate driver (GATE(H)) is activated, turning on the upper FET. This causes current to flow through the output inductor and into the output capacitors and load according to the following equation:

Additionally, the built in offset on the PWM Comparator non–inverting input provides the hiccup timing for the Overcurrent Protection, Soft Start function, and regulator output enable. VCC2 Charge Pump

In order to fully turn on the high side NFET, a voltage greater than the input voltage must be applied to VCC2 to bias the GATE(H) driver. Referring to the application diagram on page 2120; a simple charge pump circuit can be implemented for this purpose through capacitor C6, resistor R1, and diodes D1 and D2. The input voltage, less the drop in D1 is stored in C6 during the off–time period. When the high–side FET turns on, it drives the inductor switching node and C6 high causing Schottky diode D1 to reverse bias. The charge stored in C6 is transferred to VCC2 through R1. Zener diode D2 clamps the VCC2 voltage to 18 V to prevent the VCC2 from exceeding its 20 V Max rating (see Figure 9).

I + (VIN * VOUT)

T L

GATE(H) and the upper NFET remain on and inductor current ramps up until the initial pulse is terminated by either the PWM control loop or the overcurrent protection. This initial surge of in–rush current minimizes startup time, but avoids overstressing of the regulator’s power components. The PWM comparator will terminate the initial pulse if the regulator output exceeds the voltage on the COMP pin plus the 1.1 V PWM comparator offset prior to the drop across the current sense resistor exceeding the current limit threshold. In this case, the PWM control loop has achieved regulation and the initial pulse is then followed by a constant off time as programmed by the COFF capacitor. The COMP capacitor will continue to slowly charge and the regulator output voltage will follow it, less the 1.1 V PWM offset, until it achieves the voltage programmed by the DAC’s VID input. The Error Amp will then source or sink current to the COMP cap as required to maintain the correct regulator DC output voltage. Since the rate of increase of the COMP pin voltage is typically set much slower than the regulator’s slew capability, inrush current, output voltage, and duty cycle all gradually increase from zero. (See Figures 10 and 11).

Channel 1 – Charge Pump Switching Node (10 V/div) Channel 2 – VCC2 (10 V/div) Channel 3 – GATE(H) (10 V/div) Channel 4 – Inductor Switching Node (10 V/div)

Figure 9. VCC2 Charge Pump Operation (1.0 ms/div)

Startup

The CS51312 provides a controlled startup of regulator output voltage and features Programmable Soft Start implemented through the Error Amp and external Compensation Capacitor. This feature, combined with overcurrent protection, prevents stress to the regulator power components and overshoot of the output voltage during startup. As Power is applied to the regulator, the CS51312 Undervoltage Lockout circuit (UVL) monitors the ICs supply voltage (VCC1) which is typically connected to the +12 V input. The UVL circuit prevents the NFET gates from being activated until VCC1 exceeds the 8.4 V (typ) threshold. Hysteresis of 300 mV (typ) is provided for noise immunity.

Channel 1 – Regulator Input Voltage and VCC1 (10 V/div) Channel 2 – COMP (2.0 V/div) Channel 3 – Regulator Output Voltage (1.0 V/div)

Figure 10. Normal Startup (5.0 ms/div)


CS51312 When driving large capacitive loads, the COMP must charge slowly enough to avoid tripping the CS51312 overcurrent protection. The following equation can be used to ensure unconditional startup: ICHG I * ILOAD t LIM CCOMP COUT

where: ICHG = COMP Source Current (30 µA typical); CCOMP = COMP Capacitor value (0.1 µF typical); ILIM = Current Limit Threshold; ILOAD = Load Current during startup; COUT = Total Output Capacitance. Channel 1 – VCC2 (10 V/div) Channel 2 – GATE(H) (10 V/div) Channel 3 – Inductor Switching Node (10 V/div) Channel 4 – Regulator Output Voltage (2.0 V/div)

Normal Operation

During normal operation, Switch Off–Time is constant and set by the COFF capacitor. Switch On–Time is adjusted by the V2 Control loop to maintain regulation. This results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. Output voltage ripple will be determined by inductor ripple current and the ESR of the output capacitors

Figure 11. Normal Startup Showing Initial Pulse Followed by Soft Start (5.0 ms/div)

If the voltage across the Current Sense resistor generates a voltage difference between the VFB and VOUT pins that exceeds the OVC Comparator Offset Voltage (86 mV typical), the Fault latch is set. This causes the COMP pin to be quickly discharged, turning off GATE(H) and the upper NFET since the voltage on the COMP pin is now less than the 1.1 V PWM comparator offset. The Fault latch is reset when the voltage on the COMP decreases below the discharge threshold voltage (0.25 V typical). The COMP capacitor will again begin to charge, and when it exceeds the 1.1 V PWM comparator offset, the regulator output will Soft Start normally (see Figure 12).

Transient Response

The CS51312 V2 Control Loop’s 200 ns reaction time provides unprecedented transient response to changes in input voltage or output current. Pulse–by–pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. Overall load transient response is further improved through a feature called “Adaptive Voltage Positioning”. This technique pre–positions the output capacitors voltage to reduce total output voltage excursions during changes in load. Holding tolerance to 1.0% allows the error amplifiers reference voltage to be targeted +25 mV high without compromising DC accuracy. A “Droop Resistor” connects the Error Amps feedback pin (VFB) to the output capacitors and load and carries the output current. With no load, there is no DC drop across this resistor, producing an output voltage tracking the Error amps, including the +25 mV offset. When the full load current is delivered, a 50 mV drop is developed across this resistor. This results in output voltage being offset –25 mV low. The benefit of Adaptive Voltage Positioning is that additional margin is provided for a load transient before reaching the output voltage specification limits. When load current suddenly increases from its minimum level, the output capacitor is pre–positioned +25 mV. Conversely, when load current suddenly decreases from its maximum level, the output capacitor is pre–positioned –25 mV. For

Channel 1 – Regulator Output Voltage (1.0 V/div) Channel 2 – COMP Pin (1.0 V/div) Channel 3 – VCC (10 V/div)

Figure 12. Startup with COMP Pre–Charged to 2.0 V (2.0 ms/div)


CS51312 Output Enable

best Transient Response, a combination of a number of high frequency and bulk output capacitors are usually used.

On/off control of the regulator outputs can be implemented by pulling the COMP pins low. It is required to pull the COMP pins below the 1.1 V PWM comparator offset voltage in order to disable switching on the GATE drivers.

PROTECTION AND MONITORING FEATURES Overcurrent Protection

A hiccup mode current limit protection feature is provided, requiring only the COMP capacitor to implement. The CS51312 provides overcurrent protection by sensing the current through a “Droop” resistor, using an internal current sense comparator. The comparator compares the voltage drop through the “Droop” resistor to an internal reference voltage of 86 mV (typical). If the voltage drop across the “Droop” resistor exceeds this threshold, the current sense comparator allows the fault latch to be set. This causes the regulator to stop switching. During this over current condition, the CS51312 stays off for the time it takes the COMP pin capacitor to discharge to its lower 0.25 V threshold. As soon as the COMP pin reaches 0.25 V, the Fault latch is reset (no overcurrent condition present) and the COMP pin is charged with a 30 µA current source to a voltage 1.1 V greater than the VFB voltage. Only at this point the regulator attempts to restart normally by delivering short gate pulses to both FETs. This protection scheme minimizes thermal stress to the regulator components, input power supply, and PC board traces, as the over current condition persists. Upon removal of the overload, the fault latch is cleared, allowing normal operation to resume.

Adaptive FET Non–Overlap

The CS51312 includes circuitry to prevent the simultaneous conduction of both the high and low side NFETs. This is necessary to prevent efficiency reducing “shoot–through” current from flowing from the input voltage to ground through the two NFETs. Prior to either GATE(H) or GATE(L) driving high, the other GATE must reach its low state. Since GATE rise and fall times vary with loading, this results in a variable delay from the start of turn–off until the start of turn–on (see Figure 13).


Overvoltage protection (OVP) is provided as result of the normal operation of the V2 control topology and requires no additional external components. The control loop responds to an overvoltage condition within 200 ns, causing the top MOSFET to shut off, disconnecting the regulator from its input voltage. This results in a “crowbar” action to clamp the output voltage and prevents damage to the load. The regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. Additionally, a dedicated Overvoltage protection (OVP) output pin (pin 13) is provided in the CS51312. The OVP signal will go high (overvoltage condition), if the output voltage (VCC(CORE)) exceeds the regulation voltage by 8.5% of the voltage set by the particular DAC code. The OVP pin can source up to 25 mA of current that can be used to drive an SCR to crowbar the power supply.

Channel 1 – GATE(H) (5.0 V/div) Channel 2 – GATE(L) (5.0 V/div) Channel 3 – Inductor Switching Node (10 V/div)

Figure 13. Adaptive FET Non–Overlap (100 ns/div)

CS51312–BASED VCC(CORE) BUCK REGULATOR DESIGN EXAMPLE Step 1: Definition of the Design Specifications

The output voltage tolerance can be affected by any or all of the following reasons: 1. buck regulator output voltage setpoint accuracy; 2. output voltage change due to discharging or charging of the bulk decoupling capacitors during a load current transient; 3. output voltage change due to the ESR and ESL of the bulk and high frequency decoupling capacitors, circuit traces, and vias; 4. output voltage ripple and noise. Budgeting the tolerance is left up to the designer who must take into account all of the above effects and provide an output voltage that will meet the specified tolerance at the load.

Power Good Circuit

The Power Good pin (pin 14) is an open–collector signal consistent with TTL DC specifications. It is externally pulled up, and is pulled low (below 0.3 V) when the regulator output voltage typically exceeds ±8.5% of the nominal output voltage. Maximum output voltage deviation before Power Good is pulled low is ±12%.


CS51312 The designer must also ensure that the regulator component temperatures are kept within the manufacturer’s specified ratings at full load and maximum ambient temperature..

The actual output voltage deviation due to ESR can then be verified and compared to the value assigned by the designer:

Step 2: Selection of the Output Capacitors

Similarly, the maximum allowable ESL is calculated from the following formula:

VESR + IOUT

These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to provide acceptable ripple on the regulator output voltage. Key specifications for output capacitors are their ESR (Equivalent Series Resistance), and ESL (Equivalent Series Inductance). For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. In order to determine the number of output capacitors the maximum voltage transient allowed during load transitions has to be specified. The output capacitors must hold the output voltage within these limits since the inductor current can not change with the required slew rate. The output capacitors must therefore have a very low ESL and ESR. The voltage change during the load current transient is: VOUT + IOUT

ESLMAX +

t

ESLCAP ESLMAX + Number of output capacitors

where ESLCAP = maximum ESL per capacitor (it is estimated that a 10 × 12 mm Aluminum Electrolytic capacitor has approximately 4.0 nH of package inductance). The actual output voltage deviation due to the actual maximum ESL can then be verified: VESL +

where: ∆IOUT / ∆t = load current slew rate; ∆IOUT = load transient; ∆t = load transient duration time; ESL = Maximum allowable ESL including capacitors, circuit traces, and vias; ESR = Maximum allowable ESR including capacitors and circuit traces; tTR = output voltage transient response time. The designer has to independently assign values for the change in output voltage due to ESR, ESL, and output capacitor discharging or charging. Empirical data indicates that most of the output voltage change (droop or spike depending on the load current transition) results from the total output capacitor ESR. The maximum allowable ESR can then be determined according to the formula

ESLMAX t

I

The designer now must determine the change in output voltage due to output capacitor discharge during the transient: VCAP +

I tTR COUT

where: ∆tTR = the output voltage transient response time (assigned by the designer); ∆VCAP = output voltage deviation due to output capacitor discharge; ∆I = Load step. The total change in output voltage as a result of a load current transient can be verified by the following formula: VOUT + VESR ) VESL ) VCAP

VESR IOUT

Step 3: Selection of the Duty Cycle, Switching Frequency, Switch On–Time (TON) and Switch Off–Time (TOFF)

where ∆VESR = change in output voltage due to ESR (assigned by the designer). Once the maximum allowable ESR is determined, the number of output capacitors can be found by using the formula Number of capacitors +

VESL I

where: ∆I/∆T = load current slew rate (as high as 20 A/µs); ∆VESL = change in output voltage due to ESL. The actual maximum allowable ESL can be determined by using the equation:

ǒESL ) ESR ) tTR Ǔ t COUT

ESRMAX +

ESRMAX

The duty cycle of a buck converter (including parasitic losses) is given by the formula: V ) (VHFET ) VL ) VDROOP) Duty Cycle + D + OUT VIN ) VLFET * VHFET * VL

where: VOUT = buck regulator output voltage; VHFET = high side FET voltage drop due to RDS(ON); VL = output inductor voltage drop due to inductor wire DC resistance; VDROOP = droop (current sense) resistor voltage drop;

ESRCAP ESRMAX

where: ESRCAP = maximum ESR per capacitor (specified in manufacturer’s data sheet); ESRMAX = maximum allowable ESR.


CS51312 VIN = buck regulator input voltage; VLFET = low side FET voltage drop due to RDS(ON).

VOUT = output voltage; tTR = output voltage transient response time (assigned by the designer); ∆I = load transient. The inductor ripple current can then be determined:

Step3a: Calculation of Switch On–Time

The Switch On–Time (time during which the switching MOSFET in a synchronous buck topology is conducting) is determined by: TON +

V TOFF IL + OUT L

Duty Cycle FSW

where: ∆IL = inductor ripple current; VOUT = output voltage; TOFF = switch Off–Time; L = inductor value. The designer can now verify if the number of output capacitors from Step 2 will provide an acceptable output voltage ripple (1.0% of output voltage is common). The formula below is used:

where FSW = regulator switching frequency selected by the designer. Higher operating frequencies allow the use of smaller inductor and capacitor values. Nevertheless, it is common to select lower frequency operation because a higher frequency results in lower efficiency due to MOSFET gate charge losses. Additionally, the use of smaller inductors at higher frequencies results in higher ripple current, higher output voltage ripple, and lower efficiency at light load currents.

VOUT IL + ESRMAX

Rearranging we have:

Step 3b: Calculation of Switch Off–Time

The Switch Off–Time (time during which the switching MOSFET is not conducting) can be determined by:

ESRMAX +

TOFF + 1.0 * TON FSW

where ESRMAX = maximum allowable ESR; ∆VOUT = 1.0% × VOUT = maximum allowable output voltage ripple ( budgeted by the designer ); ∆IL = inductor ripple current; VOUT = output voltage. The number of output capacitors is determined by:

The COFF capacitor value has to be selected in order to set the Off–Time, TOFF, above: COFF +

Period

(1.0 * D) 3980

where: 3980 is a characteristic factor of the CS51312; D = Duty Cycle.

Number of capacitors +

The inductor should be selected based on its inductance, current capability, and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response. There are many factors to consider in selecting the inductor including cost, efficiency, EMI and ease of manufacture. The inductor must be able to handle the peak current at the switching frequency without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. There are a variety of materials and types of magnetic cores that could be used for this application. Among them are ferrites, molypermalloy cores (MPP), amorphous and powdered iron cores. Powdered iron cores are very commonly used. Powdered iron cores are very suitable due to their high saturation flux density and have low loss at high frequencies, a distributed gap and exhibit very low EMI. The inductor value can be determined by: (VIN * VOUT) I

ESRCAP ESRMAX

where ESRCAP = maximum ESR per capacitor (specified in manufacturer’s data sheet). The designer must also verify that the inductor value yields reasonable inductor peak and valley currents (the inductor current is a triangular waveform):

Step 4: Selection of the Output Inductor

L+

VOUT IL

I IL(PEAK) + IOUT ) L 2.0

where: IL(PEAK) = inductor peak current; IOUT = load current; ∆IL = inductor ripple current. I IL(VALLEY) + IOUT * L 2.0

where IL(VALLEY) = inductor valley current. Step 5: Selection of the Input Capacitors

These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to provide acceptable ripple on the input supply lines. A key specification for input capacitors is their ripple current rating. The input capacitor should also be able to handle the input RMS current IIN(RMS).

tTR

where: VIN = input voltage;


CS51312 ICIN(RMS) = total input RMS current; ESRCIN = total input capacitor ESR. The designer must determine the input capacitor power loss in order to ensure there isn’t excessive power dissipation through these components. The following formula is used:

The combination of the input capacitors CIN discharges during the on–time. The input capacitor discharge current is given by: ICINDIS(RMS) +

Ǹ

2 ȡ)IL(PEAK) ȣ (IL(PEAK) IL(VALLEY)) ȧ) I ȧ Ȣ L(VALLEY)2 Ȥ

PCIN(RMS) + ICIN(RMS)2

D

where: PCIN(RMS) = input capacitor RMS power dissipation; ICIN(RMS) = total input RMS current; ESRCIN = total input capacitor ESR.

3.0

where: ICINDIS(RMS) = input capacitor discharge current; IL(PEAK) = inductor peak current; IL(VALLEY) = inductor valley current. CIN charges during the off–time, the average current through the capacitor over one switching cycle is zero: ICIN(CH) + ICIN(DIS)

Step 6: Selection of the Input Inductor

A common requirement is that the buck controller must not disturb the input voltage. One method of achieving this is by using an input inductor and a bypass capacitor. The input inductor isolates the supply from the noise generated in the switching portion of the buck regulator and also limits the inrush current into the input capacitors upon power up. The inductor’s limiting effect on the input current slew rate becomes increasingly beneficial during load transients. The worst case is when the load changes from no load to full load (load step), a condition under which the highest voltage change across the input capacitors is also seen by the input inductor. The inductor successfully blocks the ripple current while placing the transient current requirements on the input bypass capacitor bank, which has to initially support the sudden load change. The minimum inductance value for the input inductor is therefore:

D 1.0 * D

where: ICIN(CH) = input capacitor charge current; ICIN(DIS) = input capacitor discharge current; D = Duty Cycle. The total Input RMS current is: ICIN(RMS) +

Ǹ

(ICIN(DIS)2 D) ) (ICIN(CH)2 (1.0 * D))

The number of input capacitors required is then determined by: I NCIN + CIN(RMS) IRIPPLE

V LIN + (dIńdt)MAX

where: NCIN = number of input capacitors; ICIN(RMS) = total input RMS current; IRIPPLE = input capacitor ripple current rating (specified in manufacturer’s data sheets). The total input capacitor ESR needs to be determined in order to calculate the power dissipation of the input capacitors: ESRCIN +

where: LIN = input inductor value; ∆V = voltage seen by the input inductor during a full load swing; (dI/dt)MAX = maximum allowable input current slew rate. The designer must select the LC filter pole frequency so that at least 40 dB attenuation is obtained at the regulator switching frequency. The LC filter is a double–pole network with a slope of –2.0, a roll–off rate of —40 dB/dec, and a corner frequency:

ESRCAP NCIN

where: ESRCIN = total input capacitor ESR; ESRCAP = maximum ESR per capacitor (specified in manufacturer’s data sheets); NCIN = number of input capacitors. Once the total ESR of the input capacitors is known, the input capacitor ripple voltage can be determined using the formula: VCIN(RMS) + ICIN(RMS)

ESRCIN

fC +

1.0 2.0 ǸLC

where: L = input inductor; C = input capacitor(s). Step 7: Selection of the Switching FET FET Basics

The use of the MOSFET as a power switch is propelled by two reasons: 1) Its very high input impedance; and 2) Its very fast switching times. The electrical characteristics of a MOSFET are considered to be those of a perfect switch.

ESRCIN

where: VCIN(RMS) = input capacitor RMS voltage;


CS51312 Control and drive circuitry power is therefore reduced. Because the input impedance is so high, it is voltage driven. The input of the MOSFET acts as if it were a small capacitor, which the driving circuit must charge at turn on. The lower the drive impedance, the higher the rate of rise of VGS, and the faster the turn–on time. Power dissipation in the switching MOSFET consists of 1) conduction losses, 2) leakage losses, 3) turn–on switching losses, 4) turn–off switching losses, and 5) gate–transitions losses. The latter three losses are proportional to frequency. For the conducting power dissipation rms values of current and resistance are used for true power calculations. The fast switching speed of the MOSFET makes it indispensable for high–frequency power supply applications. Not only are switching power losses minimized, but also the maximum usable switching frequency is considerably higher. Switching time is independent of temperature. Also, at higher frequencies, the use of smaller and lighter components (transformer, filter choke, filter capacitor) reduces overall component cost while using less space for more efficient packaging at lower weight. The MOSFET has purely capacitive input impedance. No DC current is required. It is important to keep in mind the drain current of the FET has a negative temperature coefficient. Increase in temperature causes higher on–resistance and greater leakage current. VDS(ON) should be low to minimize power dissipation at a given ID, and VGS should be high to accomplish this. MOSFET switching times are determined by device capacitance, stray capacitance, and the impedance of the gate drive circuit. Thus the gate driving circuit must have high momentary peak current sourcing and sinking capability for switching the MOSFET. The input capacitance, output capacitance and reverse–transfer capacitance also increase with increased device current rating. Two considerations complicate the task of estimating switching times. First, since the magnitude of the input capacitance, CISS, varies with VDS, the RC time constant determined by the gate–drive impedance and CISS changes during the switching cycle. Consequently, computation of the rise time of the gate voltage by using a specific gate–drive impedance and input capacitance yields only a rough estimate. The second consideration is the effect of the “Miller” capacitance, CRSS, which is referred to as CDG in the following discussion. For example, when a device is on, VDS(ON) is fairly small and VGS is about 12 V. CDG is charged to VDS(ON) – VGS, which is a negative potential if the drain is considered the positive electrode. When the drain is “off”, CDG is charged to quite a different potential. In this case the voltage across CDG is a positive value since the potential from gate–to–source is near zero volts and VDS is essentially the drain supply voltage. During turn–on and turn–off, these large swings in gate–to–drain voltage tax the current sourcing and sinking capabilities of the gate drive. In addition to charging and discharging CGS, the gate drive must also supply the displacement current required by

CDG(IGATE = CDG dVDG/dt). Unless the gate–drive impedance is very low, the VGS waveform commonly plateaus during rapid changes in the drain–to–source voltage. The most important aspect of FET performance is the Static Drain–To–Source On–Resistance (RDS(ON)), which effects regulator efficiency and FET thermal management requirements. The On–Resistance determines the amount of current a FET can handle without excessive power dissipation that may cause overheating and potentially catastrophic failure. As the drain current rises, especially above the continuous rating, the On–Resistance also increases. Its positive temperature coefficient is between +0.6%/C and +0.85%/C. The higher the On–Resistance the larger the conduction loss is. Additionally, the FET gate charge should be low in order to minimize switching losses and reduce power dissipation. Both logic level and standard FETs can be used. Voltage applied to the FET gates depends on the application circuit used. Both upper and lower gate driver outputs are specified to drive to within 1.5 V of ground when in the low state and to within 2.0 V of their respective bias supplies when in the high state. In practice, the FET gates will be driven rail–to–rail due to overshoot caused by the capacitive load they present to the controller IC. Step 7a: Selection of the Switching (Upper) FET

The designer must ensure that the total power dissipation in the FET switch does not cause the power component’s junction temperature to exceed 150°C. The maximum RMS current through the switch can be determined by the following formula: IRMS(H) +

Ǹ

2 ȡI)L(PEAK) ȣ ȧ) (IIL(PEAK) 2 IL(VALLEY))ȧ Ȣ L(VALLEY) Ȥ

D

3.0

where: IRMS(H) = maximum switching MOSFET RMS current; IL(PEAK) = inductor peak current; IL(VALLEY) = inductor valley current; D = Duty Cycle. Once the RMS current through the switch is known, the switching MOSFET conduction losses can be calculated: PRMS(H) + IRMS(H)2

RDS(ON)

where: PRMS(H) = switching MOSFET conduction losses; IRMS(H) = maximum switching MOSFET RMS current; RDS(ON) = FET drain–to–source on–resistance The upper MOSFET switching losses are caused during MOSFET switch–on and switch–off and can be determined by using the following formula:


CS51312 PSWH + PSWH(ON) ) PSWH(OFF) V + IN

IOUT

ILOAD = load current Non–overlap time = GATE(L)–to–GATE(H) or GATE(H)–to–GATE(L) delay (from CS51312 data sheet Electrical Characteristics section); FSW = switching frequency. The total power dissipation in the synchronous (lower) MOSFET can then be calculated as:

(tRISE ) tFALL) 6.0T

where: PSWH(ON) = upper MOSFET switch–on losses; PSWH(OFF) = upper MOSFET switch–off losses; VIN = input voltage; IOUT = load current; tRISE = MOSFET rise time (from FET manufacturer’s switching characteristics performance curve); tFALL = MOSFET fall time (from FET manufacturer’s switching characteristics performance curve); T = 1/FSW = period. The total power dissipation in the switching MOSFET can then be calculated as:

PLFET(TOTAL) + PRMSL ) PSWL

where: PLFET(TOTAL) = Synchronous (lower) FET total losses; PRMSL = Switch Conduction Losses; PSWL = Switching losses. Once the total power dissipation in the synchronous FET is known the maximum FET switch junction temperature can be calculated:

PHFET(TOTAL) + PRMSH ) PSWH(ON) ) PSWH(OFF)

TJ + TA ) (PLFET(TOTAL)

where: PHFET(TOTAL) = total switching (upper) MOSFET losses; PRMSH = upper MOSFET switch conduction Losses; PSWH(ON) = upper MOSFET switch–on losses; PSWH(OFF) = upper MOSFET switch–off losses. Once the total power dissipation in the switching FET is known, the maximum FET switch junction temperature can be calculated: TJ + TA ) (PHFET(TOTAL)

where: TJ = MOSFET junction temperature; TA = ambient temperature; PLFET(TOTAL) = total synchronous (lower) FET losses; RθJA = lower FET junction–to–ambient thermal resistance. Step 8: Control IC Power Dissipation

The power dissipation of the IC varies with the MOSFETs used, VCC, and the CS51312 operating frequency. The average MOSFET gate charge current typically dominates the control IC power dissipation. The IC power dissipation is determined by the formula:

RJA)

where: TJ = FET junction temperature; TA = ambient temperature; PHFET(TOTAL) = total switching (upper) FET losses; RθJA = upper FET junction–to–ambient thermal resistance.

PCONTROLIC + ICC1VCC1 ) PGATE(H) ) PGATE(L)

where: PCONTROLIC = control IC power dissipation; ICC1 = IC quiescent supply current; VCC1 = IC supply voltage; PGATE(H) = upper MOSFET gate driver (IC) losses; PGATE(L) = lower MOSFET gate driver (IC) losses.

Step 7b: Selection of the Synchronous (Lower) FET

The switch conduction losses for the lower FET can be calculated as follows: PRMSL + IRMS2 + ǒIOUT

RDS(ON)

Ǹ(1.0 * D)Ǔ2

RDS(ON)

where: PRMSL = lower MOSFET conduction losses; IOUT = load current; D = Duty Cycle; RDS(ON) = lower FET drain–to–source on–resistance. The synchronous MOSFET has no switching losses, except for losses in the internal body diode, because it turns on into near zero voltage conditions. The MOSFET body diode will conduct during the non–overlap time and the resulting power dissipation (neglecting reverse recovery losses) can be calculated as follows: PSWL + VSD

ILOAD

non–overlap time

RJA)

FSW

where: PSWL = lower FET switching losses; VSD = lower FET source–to–drain voltage; http://onsemi.com 2135

CS51312 16

The upper (switching) MOSFET gate driver (IC) losses are: PGATE(H) + QGATE(H)

FSW

COMP

FSW

C1 R1

12 GATE(L)

To Synchronous FET

Figure 14. Small RC Filter Provides the Proper Voltage Ramp at the Beginning of Each On–Time Cycle

VGATE(L)

The artificial voltage ramp created by the slope compensation scheme results in improved control loop stability provided that the RC filter time constant is smaller than the off–time cycle duration (time during which the lower MOSFET is conducting). It is important that the series combination of R1 and R2 is high enough in resistance to avoid loading the GATE(L) pin.

where: PGATE(L) = lower MOSFET gate driver (IC) losses; QGATE(L) = total lower MOSFET gate charge; FSW = switching frequency; VGATE(L) = lower MOSFET gate voltage. The junction temperature of the control IC is primarily a function of the PCB layout, since most of the heat is removed through the traces connected to the pins of the IC.

Step 10: Selection of Current Limit Filter Components

In some applications, the current limit comparator may falsely trigger due to noise, load transients, or high inductor ripple currents. A filter circuit such as the one shown in Figure 15 can be added to prevent this. The RC time constant of this filter is equal to (RFB + ROUT) × CSENSE. Increasing the RC time constant will reduce the sensitivity of the circuit, but increase the time required to detect an overcurrent condition. The value of RFB + ROUT should be kept to 510 Ω or lower to avoid significant DC offsets due to the VFB and VOUT bias currents.

Step 9: Slope Compensation

Voltage regulators for today’s advanced processors are expected to meet very stringent load transient requirements. One of the key factors in achieving tight dynamic voltage regulation is low ESR at the CPU input supply pins. Low ESR at the regulator output results in low output voltage ripple. The consequence is, however, that there’s very little voltage ramp at the control IC feedback pin (VFB) and regulator sensitivity to noise and loop instability are two undesirable effects that can surface. The performance of the CS51312–based CPU VCC(CORE) regulator is improved when a fixed amount of slope compensation is added to the output of the PWM Error Amplifier (COMP pin) during the regulator Off–Time. Referring to Figure 14, the amount of voltage ramp at the COMP pin is dependent on the gate voltage of the lower (synchronous) FET and the value of resistor divider formed by R1and R2. VSLOPECOMP + VGATE(L)

R2

CS51312

where: PGATE(H) = upper MOSFET gate driver (IC) losses; QGATE(H) = total upper MOSFET gate charge; FSW = switching frequency; VGATE(H) = upper MOSFET gate voltage. The lower (synchronous) MOSFET gate driver (IC) losses are: PGATE(L) + QGATE(L)

CCOMP

VGATE(H)

VIN

GATE(H)

VOUT

RSENSE

ǒR1 R2 Ǔ ǒ1.0 * e *t Ǔ ) R2

+

GATE(L)

where: VSLOPECOMP = amount of slope added; VGATE(L) = lower MOSFET gate voltage; R1, R2 = voltage divider resistors; t = tOFF (switch off–time); τ = RC constant determined by C1 and the parallel combination of R1, R2 (Figure 14), neglecting the low driver output impedance.

RFB

ROUT

VFB CSENSE VOUT

Figure 15. Current Limit Filter Circuit


CS51312 2) Mismatch Due to L/W

“DROOP” RESISTOR FOR ADAPTIVE VOLTAGE POSITIONING AND CURRENT LIMIT Adaptive voltage positioning is used to help keep the output voltage within specification during load transients. To implement adaptive voltage positioning a “Droop Resistor” must be connected between the output inductor and output capacitors and load. This resistor carries the full load current and should be chosen so that both DC and AC tolerance limits are met. In order to determine the droop resistor value the nominal voltage drop across it at full load has to be calculated. This voltage drop has to be such that the output voltage at full load is above the minimum DC tolerance spec:

The variation in L/W is governed by variations due to the PCB manufacturing process. The error due to L/W mismatch is typically 1.0%. 3) Thermal Considerations

Due to I2 × R power losses the surface temperature of the droop resistor will increase causing the resistance to increase. Also, the ambient temperature variation will contribute to the increase of the resistance, according to the formula: R + R20[1.0 ) 20(T * 20)]

where: R20 = resistance at 20°C; α = 0.00393/°C T= operating temperature; R = desired droop resistor value. For temperature T = 50°C, the % R change = 12%.

VDAC(MIN) * VDC(MIN) VDROOP(TYP) + 1.0 ) RDROOP(TOLERANCE) Current Limit

The current limit setpoint has to be higher than the normal full load current. Attention has to be paid to the current rating of the external power components as these are the first to fail during an overload condition. The MOSFET continuous and pulsed drain current rating at a given case temperature has to be accounted for when setting the current limit trip point.



±8.0% 1.0% 12% 21%

Nominal Current Limit Setpoint Droop Resistor Length, Width, and Thickness

From the overcurrent detection data in the electrical characteristics table:

The minimum width and thickness of the droop resistor should primarily be determined on the basis of the current–carrying capacity required, and the maximum permissible droop resistor temperature rise. PCB manufacturer design charts can be used in determining current–carrying capacity and sizes of etched copper conductors for various temperature rises above ambient.

VTH(TYP) + 86 mV ICL(NOM) + R

VTH(TYP) SENSE(NOM)



L or R + A

THERMAL MANAGEMENT

L (W

Thermal Considerations for Power MOSFETs

t)


where: A = W × t = cross–sectional area; ρ = the copper resistivity (µΩ–mil); L = length (mils); W = width (mils); t = thickness (mils). An embedded PC trace resistor has the distinct advantage of near zero cost implementation. However, this droop resistor can vary due to three reasons: 1) the sheet resistivity variation caused by variation in the thickness of the PCB layer; 2) the mismatch of L/W; and 3) temperature variation.

T * TA Thermal Impedance + J(MAX) Power


1) Sheet Resistivity

For one ounce copper, the thickness variation is typically 1.26 mil to 1.48 mil. Therefore the error due to sheet resistivity is:

EMI MANAGEMENT As a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. When designing for

1.48 * 1.26 +" 8.0% 1.37


CS51312 6. Keep the inductor switching node small by placing the output inductor, switching and synchronous FETs close together. 7. The MOSFET gate traces to the IC must be as short, straight, and wide as possible. 8. Use fewer, but larger output capacitors, keep the capacitors clustered, and use multiple layer traces with heavy copper to keep the parasitic resistance low. 9. Place the switching MOSFET as close to the +5.0 V input capacitors as possible. 10. Place the output capacitors as close to the load as possible. 11. Place the VFB, VOUT filter resistors (510 Ω) in series with the VFB and VOUT pins as close as possible to the pins. 12. Place the COFF and COMP capacitors as close as possible to the COFF and COMP pins. 13. Place the current limit filter capacitor between the VFB and VOUT pins, as close as possible to the pins. 14. Connect the filter components of the following pins: VFB, VOUT, COFF, and COMP to the GND pin with a single trace, and connect this local GND trace to the output capacitor GND. 15. The “Droop” Resistor (embedded PCB trace) has to be wide enough to carry the full load current. 16. Place the VCC bypass capacitor as close as possible to the IC.

compliance with EMI/EMC regulations, additional components may be added to reduce noise emissions. These components are not required for regulator operation and experimental results may allow them to be eliminated. The input filter inductor may not be required because bulk filter and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the circuit board and input power supply. Placement of the power component to minimize routing distance will also help to reduce emissions. LAYOUT GUIDELINES When laying out the CPU buck regulator on a printed circuit board, the following checklist should be used to ensure proper operation of the CS51312. 1. Rapid changes in voltage across parasitic capacitors and abrupt changes in current in parasitic inductors are major concerns for a good layout. 2. Keep high currents out of sensitive ground connections. 3. Avoid ground loops as they pick up noise. Use star or single point grounding. 4. For high power buck regulators on double–sided PCBs a single ground plane (usually the bottom) is recommended. 5. Even though double sided PCBs are usually sufficient for a good layout, four–layer PCBs are the optimum approach to reducing susceptibility to noise. Use the two internal layers as the power and GND planes, the top layer for power connections and component vias, and the bottom layer for the noise sensitive traces.


CS51312 +5.0 V

+12 V

1.0 µF

1200 µF/10 V × 3

680 pF

10 k

0.01 µF

100 Ω

COFF

0.1 µF

VCC1

VCC2

COMP

GATE(H)

VID0

GATE(L)

VID1

FS70VSJ–03 1.2 µH

3.3 mΩ

FS70VSJ–03 1200 µF/10 V × 5

CS51312

VID2

VFB

VID3

VOUT

VID4 GND

VCC(CORE) 2.0 V @ 19 A

510 Ω

OVP PWRGD

0.1 µF 510 Ω

OVP PWRGD

Figure 16. Additional Application Circuit, 5.0 V/12 V to 2.0 V/19 A Converter


SO–16

Unit

RΘJC

Typical

28

°C/W

RΘJA

Typical

115

°C/W


* 89 -" &# ! The CS5157H is a 5–bit synchronous dual N–Channel buck controller. It is designed to provide unprecedented transient response for today’s demanding high–density, high–speed logic. The regulator operates using a proprietary control method, which allows a 100 ns response time to load transients. The CS5157H is designed to operate over a 4.25–20 V range (VCC) using 12 V to power the IC and 5.0 V or 12 V as the main supply for conversion. The CS5157H is specifically designed to power Pentium II processors and other high performance core logic. It includes the following features: on board, 5–bit DAC, short circuit protection, 1.0% output tolerance, VCC monitor, and programmable Soft Start capability. The CS5157H is available in 16 pin surface mount. Features Dual N–Channel Design Excess of 1.0 MHz Operation 100 ns Transient Response 5–Bit DAC 30 ns Gate Rise/Fall Times 1.0% DAC Accuracy 5.0 V & 12 V Operation Remote Sense Programmable Soft Start Lossless Short Circuit Protection VCC Monitor 25 ns FET Nonoverlap Time V2 Control Topology Current Sharing Overvoltage Protection

• • • • • • • • • • • • • • •


16 1

CS5157H AWLYWW


XXX A WL, L YY, Y WW, W

1

= Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week

PIN CONNECTIONS 1

16






2140

Package

Shipping

CS5157HGD16

SO–16

48 Units/Rail

CS5157HGDR16

SO–16

2500 Tape & Reel


CS5157H 5.0 V

12 V

0.1 µF VCC1

VCC2

1200 µF/10 V × 3 AIEI

IRL3103 VGATE(H)

VID0

VID0

VID1

VID1

VID2

VID2

VID3

VID3

VID4

VID4

2.0 µH

IRL3103

VGATE(L)

CS5157H

COFF

330 pF

1.3 V to 3.5 V @ 13 A

PGND

SS 0.1 µF

COMP

VFB 3.3 k

0.33 µF

LGND

VFFB

1200 µF/10 V × 5 AIEI

100 pF



Value

Unit

0 to 150

°C

230 peak

°C

–65 to +150

°C

2.0

kV






Max Current

VCC1

16 V/–0.3 V

25 mA DC/1.5 A peak

VCC2

20 V/–0.3 V

20 mA DC/1.5 A peak

SS

6.0 V/–0.3 V

–100 µA

COMP

6.0 V/–0.3 V

200 µA

VFB

6.0 V/–0.3 V

–0.2 µA

COFF

6.0 V/–0.3 V

–0.2 µA

VFFB

6.0 V/–0.3 V

–0.2 µA

VID0 – VID4

6.0 V/–0.3 V

–50 µA

VGATE(H)

20 V/–0.3 V


VGATE(L)

16 V/–0.3 V


LGND

0V

25 mA

PGND

0V



CS5157H ELECTRICAL CHARACTERISTICS (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 20 V;DAC Code: VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit


VFB = 0 V

–

0.3

1.0

µA

Open Loop Gain

1.25 V < VCOMP < 4.0 V; Note 2

50

60

–

dB


Note 2

500

3000

–

kHz

COMP SINK Current

VCOMP = 1.5 V; VFB = 3.0 V; VSS > 2.0 V

0.4

2.5

8.0

mA

COMP SOURCE Current

VCOMP = 1.2 V; VFB = 2.7 V; VSS = 5.0 V

30

50

80

µA

COMP CLAMP Current


0.4

1.0

1.6

mA

COMP High Voltage

VFB = 2.7 V; VSS = 5.0 V

4.0

4.3

5.0

V

COMP Low Voltage

VFB = 3.0 V

–

160

600

mV

PSRR

8.0 V < VCC1 < 14 V @ 1.0 kHz; Note 2

60

85

–

dB


Output switching

3.75

3.90

4.05

V

Stop Threshold


3.70

3.85

4.00

V

Hysteresis

Start–Stop

–

50

–

mV



–

1.2

2.0

V



–

1.0

1.5

V

Out Rise Time


–

30

50

ns

Out Fall Time


–

30

50

ns



–

25

50

ns



–

25

50

ns



20

50

100

kΩ



–

600

800

mV



–

1.6

3.3

5.0

ms

Pulse Period

–

25

100

200

ms

Duty Cycle


1.0

3.3

6.0

%

COMP Clamp Voltage

VFB = 0 V; VSS = 0

0.50

0.95

1.10

V



0.9

1.0

1.1

V

–

2.5

3.0

V

High Threshold

–



–

100

125

ns

VFFB Bias Current

VFFB = 0 V

–

0.3

–

µA




Test Conditions

Min

Typ

Max

Unit

DAC Input Threshold


1.00

1.25

2.40

V



25

50

100

kΩ

4.85

5.00

5.15

V

–

–

1.0

%

Pull Up Voltage

–



VID4

VID3

VID2

VID1

VID0

0

1

1

1

1

–

1.2870

1.3000

1.3130

V

0

1

1

1

0

–

1.3365

1.3500

1.3635

V

0

1

1

0

1

–

1.3860

1.4000

1.4140

V

0

1

1

0

0

–

1.4355

1.4500

1.4645

V

0

1

0

1

1

–

1.4850

1.5000

1.5150

V

0

1

0

1

0

–

1.5345

1.5500

1.5655

V

0

1

0

0

1

–

1.5840

1.6000

1.6160

V

0

1

0

0

0

–

1.6335

1.6500

1.6665

V

0

0

1

1

1

–

1.6830

1.7000

1.7170

V

0

0

1

1

0

–

1.7325

1.7500

1.7675

V

0

0

1

0

1

–

1.7820

1.8000

1.8180

V

0

0

1

0

0

–

1.8315

1.8500

1.8685

V

0

0

0

1

1

–

1.8810

1.9000

1.9190

V

0

0

0

1

0

–

1.9305

1.9500

1.9695

V

0

0

0

0

1

–

1.9800

2.0000

2.0200

V

0

0

0

0

0

–

2.0295

2.0500

2.0705

V

1

1

1

1

1

–

1.2191

1.2440

1.2689

V

1

1

1

1

0

–

2.0790

2.1000

2.1210

V

1

1

1

0

1

–

2.1780

2.2000

2.2220

V

1

1

1

0

0

–

2.2770

2.3000

2.3230

V

1

1

0

1

1

–

2.3760

2.4000

2.4240

V

1

1

0

1

0

–

2.4750

2.5000

2.5250

V

1

1

0

0

1

–

2.5740

2.6000

2.6260

V

1

1

0

0

0

–

2.6730

2.7000

2.7270

V

1

0

1

1

1

–

2.7720

2.8000

2.8280

V

1

0

1

1

0

–

2.8710

2.9000

2.9290

V

1

0

1

0

1

–

2.9700

3.0000

3.0300

V

1

0

1

0

0

–

3.0690

3.1000

3.1310

V

1

0

0

1

1

–

3.1680

3.2000

3.2320

V

1

0

0

1

0

–

3.2670

3.3000

3.3330

V

1

0

0

0

1

–

3.3660

3.4000

3.4340

V

1

0

0

0

0

–

3.4650

3.5000

3.5350

V



Test Conditions

Min

Typ

Max

Unit

Supply Current ICC1

No Switching

–

8.5

13.5

mA

ICC2

No Switching

–

1.6

3.0

mA

Operating ICC1

VFB = COMP = VFFB

–

8.0

13

mA

Operating ICC2

VFB = COMP = VFFB

–

2.0

5.0

mA


VFFB = 1.5 V; VSS = 5.0 V

1.0

1.6

2.2

µs


VSS = VFFB = 0

5.0

8.0

11.0

µs

Discharge Current


5.0

–

–

mA

Time Out Time


10

30

65

µs


VFFB = 0V

35

50

70

%

Time Out Timer


PIN SYMBOL

FUNCTION

1, 2, 3, 4, 6

VID0–VID4


5

SS


7

COFF


8

VFFB


9

VCC2


10

VGATE(H)

11

PGND

12

VGATE(L)

13

VCC1


14

LGND


15

COMP


16

VFB


High FET driver pin capable of 1.5 A peak switching current. Internal circuit prevents VGATE(H) and VGATE(L) from being in high state simultaneously. High current ground for the IC. The MOSFET driver is referenced to this pin. Input capacitor ground and the source of lower FET should be tied to this pin. Low FET driver pin capable of 1.5 A peak switching current.


CS5157H VCC2 VCC1

–


+

–

3.90 V 3.85V

VGATE(H)

SS Low Comparator R

60 µA

Q S FAULT Latch

0.7 V SS +

2.0 µA

VID2

PGnd

FAULT

VCC1

–

VID0 VID1

SS High Comparator

FAULT

Q

+

5 BIT DAC

VID3


VGATE(L)

2.5 V

PGnd

PWM Comparator

VID4

– VFB


+

Slow Feedback


COMP

VFFB

Fast Feedback

– +

LGnd

1.0 V

R

Q

S

Q PMW Latch


Off–Time Timeout

COFF Q

S

VFFB Low Comparator


PWM COMP

Edge Triggered



PWM Comparator + VGATE(H) C VGATE(L) –

V2 Control Method


Ramp Signal

VFFB

VFB


Error Signal


–

E +



Reference Voltage



The CS5157H is designed to provide two methods for programming the output voltage of the power supply. A five bit on board digital to analog converter (DAC) is used to program the output voltage within two different ranges. The first range is 2.10 V to 3.50 V in 100 mV steps, the second is 1.30 V to 2.05 V in 50 mV steps, depending on the digital input code. If all five bits are left open, the CS5157H enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feedback to the VFB and VFFB pins, as in traditional controllers. Start Up

Until the voltage on the VCC1 supply pin exceeds the 3.9 V monitor threshold, the Soft Start and gate pins are held low. The FAULT latch is reset (no Fault condition). The output of the error amplifier (COMP) is pulled up to 1.0 V by the comparator clamp. When the VCC1 pin exceeds the monitor threshold, the GATE(H) output is activated, and the Soft Start capacitor begins charging. The GATE(H) output will remain on, enabling the NFET switch, until terminated by either the PWM comparator, or the maximum on time timer. If the maximum on time is exceeded before the regulator output voltage achieves the 1.0 V level, the pulse is terminated. The GATE(H) pin drives low, and the GATE(L) pin drives high for the duration of the extended off time. This time is set by the time out timer and is approximately equal to the maximum on time, resulting in a 50% duty cycle. The GATE(L) pin will then drive low, the GATE(H) pin will drive high, and the cycle repeats. When regulator output voltage achieves the 1.0 V level present at the COMP pin, regulation has been achieved and normal off time will ensue. The PWM comparator terminates the switch on time, with off time set by the COFF capacitor. The V2 control loop will adjust switch duty cycle as required to ensure the regulator output voltage tracks the output of the error amplifier. The Soft Start and COMP capacitors will charge to their final levels, providing a controlled turn on of the regulator output. Regulator turn on time is determined by the COMP capacitor charging to its final value. Its voltage is limited by

Constant Off Time





M 250 µs






Normal Operation




M 1.00 µs





CS5157H

M 1.00 µs Trace 1– Regulator Output Voltage (10 mV/div.)



Trace 2– Inductor Switching Node (5.0 V/div.) Trace 3– Output Current (0.5 to 13 Amps) (10 A/div.)

Figure 8. Peak–to–Peak Ripple on VOUT = 2.8 V, IOUT = 13 A (Heavy Load)


Transient Response

The CS5157H V2 control loop’s 100 ns reaction time provides unprecedented transient response to changes in input voltage or output current. Pulse by pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. For best transient response, a combination of a number of high frequency and bulk output capacitors are usually used. If the maximum on time is exceeded while responding to a sudden increase in load current, a normal off time occurs to prevent saturation of the output inductor.

Trace 1– Regulator Output Voltage (100 mV/div.) Trace 2– Inductor Switching Node (5.0 V/div.) Trace 3– Output Current (13 to 0,5 Amps) (10 A/div.)



To maintain predictable startup and shutdown characteristics an internal VCC1 monitor circuit is used to prevent the part from operating below 3.75 V minimum startup. The VCC1 monitor comparator provides hysteresis and guarantees a 3.70 V minimum shutdown threshold.

Trace 1– Regulator Output Voltage (100 mV/div.) Trace 2– Regulator Output Voltage (10 A/div.)



CS5157H Short Circuit Protection

A lossless hiccup mode short circuit protection feature is provided, requiring only the Soft Start capacitor to implement. If a short circuit condition occurs (VFFB < 1.0 V), the VFFB low comparator sets the FAULT latch. This causes the MOSFET to shut off, disconnecting the regulator from it’s input voltage. The Soft Start capacitor is then slowly discharged by a 2.0 µA current source until it reaches it’s lower 0.7 V threshold. The regulator will then attempt to restart normally, operating in it’s extended off time mode with a 50% duty cycle, while the Soft Start capacitor is charged with a 60 µA charge current. If the short circuit condition persists, the regulator output will not achieve the 1.0 V low VFFB comparator threshold before the Soft Start capacitor is charged to it’s upper 2.5 V threshold. If this happens the cycle will repeat itself until the short is removed. The Soft Start charge/discharge current ratio sets the duty cycle for the pulses (2.0 µA/60 µA = 3.3%), while actual duty cycle is half that due to the extended off time mode (1.65%). This protection feature results in less stress to the regulator components, input power supply, and PC board traces than occurs with constant current limit protection (see Figures 12 and 13). If the short circuit condition is removed, output voltage will rise above the 1.0 V level, preventing the FAULT latch from being set, allowing normal operation to resume.



Overvoltage protection (OVP) is provided as result of the normal operation of the V2 control topology and requires no additional external components. The control loop responds to an overvoltage condition within 100 ns, causing the top MOSFET to shut off, disconnecting the regulator from it’s input voltage. The bottom MOSFET is then activated, resulting in a “crowbar” action to clamp the output voltage and prevent damage to the load (see Figures 14 and 15 ). The regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. The bottom FET and board trace must be properly designed to implement the OVP function.

M 25.0 ms M 10.0 µs

Trace 4– 5.0 V Supply Voltage (2.0 V/div.) Trace 3– Soft Start Timing Capacitor (1.0 V/div.)

Trace 4– 5.0 V from PC Power Supply (5.0 V/div.)






CS5157H 5.0 V R3 10 k VOUT

R1 10 k

CS5157H

PN3904

Power Good

PN3904

R2 6.2 k

Figure 17. Implementing Power Good with the CS5157H M 5.00 ms Trace 4– 5.0 V from PC Power Supply (2.0 V/div.) Trace 1– Regulator Output Voltage (1.0 V/div.)

Figure 15. OVP Response to an Input–to–Output Short Circuit by Pulling the Input Voltage to Ground External Output Enable Circuit

On/off control of the regulator can be implemented through the addition of two additional discrete components (see Figure 16). This circuit operates by pulling the Soft Start pin high, and the VFFB pin low, emulating a short circuit condition. 5.0 V

M 2.50 ms Trace 3 – 12 V Input (VCC1) and (VCC2) (10 V/div.) Trace 4– 5.0 V Input (2.0 V/div.) Trace 1– Regulator Output Voltage (1.0 V/div.) Trace 2– Power Good Signal (2.0 V/div.)

MMUN2111T1 (SOT–23)


5 SS


CS5157H


8 V FFB IN4148 Shutdown Input


Both logic level and standard MOSFETs can be used. The reference designs derive gate drive from the 12 V supply which is generally available in most computer systems and utilize logic level MOSFETs. Multiple MOSFETs may be paralleled to reduce losses and improve efficiency and thermal management. Voltage applied to the MOSFET gates depends on the application circuit used. Both upper and lower gate driver outputs are specified to drive to within 1.5 V of ground when in the low state and to within 2.0 V of their respective bias supplies when in the high state. In practice, the MOSFET gates will be driven rail to rail due to overshoot caused by the

Figure 16. Implementing Shutdown with the CS5157H External Power Good Circuit


(R1 ) R2) 0.65 V R2

This circuit provides an open collector output that drives the Power Good output to ground for regulator voltages less than VPower Good.


CS5157H capacitive load they present to the controller IC. For the typical application where VCC1 = VCC2 = 12 V and 5.0 V is used as the source for the regulator output current, the following gate drive is provided;



Perioid

(1 * duty cycle) 4848.5

where:

(see Figure 19.)

Period +



A Schottky diode may be placed in parallel with the synchronous MOSFET to conduct the inductor current upon turn off of the switching MOSFET to improve efficiency. The CS5157H reference circuit does not use this device due to it’s excellent design. Instead, the body diode of the synchronous MOSFET is utilized to reduce cost and conducts the inductor current. For a design operating at 200 kHz or so, the low non–overlap time combined with Schottky forward recovery time may make the benefits of this device not worth the additional expense (see Figure 8, channel 2). The power dissipation in the synchronous MOSFET due to body diode conduction can be estimated by the following equation:

M 1.00 µs Trace 3 = VGATE(H) (10 V/div.) Math 1 = VGATE(H) – 5.0 VIN Trace 4 = VGATE(L) (10 V/div.)

Power + VBD


The most important aspect of MOSFET performance is RDSON, which effects regulator efficiency and MOSFET thermal management requirements. The power dissipated by the MOSFETs may be estimated as follows; Switching MOSFET: Power + ILOAD2

RDSON

Power + 1.6 V

RDSON

ƪ

(1 * duty cycle)

RDSON OF SYNCH FET)

ƫ

233 kHz + 0.48 W


The COFF timing capacitor sets the regulator off time: 4848.5

THERMAL MANAGEMENT


100 ns

Output Inductor

Off Time Capacitor (COFF) TOFF + COFF

13 A


duty cycle


switching frequency



conduction time



ILOAD

Where VBD = the forward drop of the MOSFET body diode. For the CS5157H demonstration board as shown in Figure 8;



24, 242.5

In order to maintain good reliability, the junction temperature of the semiconductor components should be kept to a maximum of 150°C or lower. The thermal



CS5157H Layout Guidelines

impedance (junction to ambient) required to meet this requirement can be calculated as follows: Thermal Impedance +

1. Place 12 V filter capacitor next to the IC and connect capacitor ground to pin 11 (PGND). 2. Connect pin 11 (PGND) with a separate trace to the ground terminals of the 5.0 V input capacitors. 3. Place fast feedback filter capacitor next to pin 8 (VFFB) and connect it’s ground terminal with a separate, wide trace directly to pin 14 (LGND). 4. Connect the ground terminals of the Compensation capacitor directly to the ground of the fast feedback filter capacitor to prevent common mode noise from effecting the PWM comparator. 5. Place the output filter capacitor(s) as close to the load as possible and connect the ground terminal to pin 14 (LGND). 6. Connect the VFB pin directly to the load with a separate trace (remote sense). 7. Place 5.0 V input capacitors close to the switching MOSFET and synchronous MOSFET. Route gate drive signals VGATE(H) (pin 10) and VGATE(L) (pin 12 when used) with traces that are a minimum of 0.025 inches wide.





VCC 0.1 µF 15

11

1.0 µF VCOMP

2.0 µH

33 Ω 8 1000 pF

5

100 pF VFFB

SOFT START Figure 20. Filter Components OFF TIME

2.0 µH

To the negative terminal of the output capacitors +


1200 pF × 3.0/16 V



CS5157H 5.0V MBRS 120

0.1 µF

MBRS120 1.0 µF

MBRS120 1.0 µF

VCC2

VCC1

+


Si4410DY

VGATE(H)

3.0 µH

3.3 V/10 A

VID0 VID1 VID2

Si9410DY

VGATE(L)

VID3

CS5157H

VID4

PGND COFF 330 pF SS 0.1 µF

VFB

COMP

3.3 k VFFB

LGND

+

0.33 µF

100 pF


Figure 23. Additional Application Diagram, 5.0 V to 3.3 V/10 A Converter 3.3 V

12 V

+

1.0 µF VCC1

VCC2

5.0 µH

Si9410

VGATE(H)


2.5 V/7.0 A

VID0 VID1

VFB

VID2

+

VID3 VID4

CS5157H


Si9410

VGATE(L)

COFF

330 pF

SS 0.1 µF

PGND 3.3 k

COMP LGND 0.33 µF

VFFB 100 pF



CS5157H 5.0V MBRS 120

0.1 µF

MBRS120 1.0 µF

MBRS120 1.0 µF

+


VCC1

VCC2

Si4410

VGATE(H)

3.0 µH

3.3 V/10 A

VID0 VID1

VFB

VID2 VID3

10 Ω

100 µF/10 V × 3

+

Tantalum

CS5157H Si9410

VID4

VGATE(L)


PGND

COMP

3.3 k VFFB

LGND


100 pF

0.33 µF

Figure 25. Additional Application Diagram, 5.0 V to 3.3 V/10 A Converter with Current Sharing 12 V 1N5818

12 V 1N5818

22 Ω 1/4 W 1.0 µF

+ 1N4746 18 V 1.0 W

1.0 µF VCC1

VCC2

VID0


0.1 µF FY10AAJ03

VGATE(H)

1.1 µH

3.3 V/5.0 A

VID1 VID2

VFB

VID3 VID4 330 pF

CS5157H

+

COFF

FY10AAJ03

SS 0.1 µF

FY10AAJ03

VGATE(L)

PGND 3.3 k

COMP LGND 0.33 µF


VFFB 100 pF

Figure 26. Additional Application Diagram, 12 V to 3.3 V/5.0 A Converter with Remote Sense



16–SO

Unit

RΘJC

Typical

28

°C/W

RΘJA

Typical

115

°C/W


3 89 -" &# ! The CS5158 is a 5–bit synchronous dual N–Channel buck controller. It is designed to provide unprecedented transient response for today’s demanding high–density, high–speed logic. The regulator operates using a proprietary control method, which allows a 100 ns response time to load transients. The CS5158 is designed to operate over a 4.25–16 V range (VCC) using 12 V to power the IC and 5.0 V as the main supply for conversion. The CS5158 is specifically designed to power Pentium II processors and other high performance core logic. It includes the following features: on board, 5–bit DAC, short circuit protection, 0.8% output tolerance for the 01111 DAC code (1.3 V) and 1.0% for the remaining DAC codes, VCC monitor, and programmable Soft Start capability. The CS5158 is available in 16 pin surface mount. Features Dual N–Channel Design Excess of 1.0 MHz Operation 100 ns Transient Response 5–Bit DAC 30 ns Gate Rise/Fall Times 0.8% Accuracy for the 01111 DAC Code and 1.0% for the Remaining DAC Codes • 5.0 V & 12 V Operation • Remote Sense • Programmable Soft Start • Lossless Short Circuit Protection • VCC Monitor • 25 ns FET Nonoverlap Time • V2 Control Topology • Current Sharing • Overvoltage Protection

• • • • • •


16 1

A WL, L YY, Y WW, W


2156

1


PIN CONNECTIONS 1

16





CS5158 AWLYWW


Package

Shipping

CS5158GD16

SO–16

48 Units/Rail

CS5158GDR16

SO–16

2500 Tape & Reel


CS5158 5.0 V

12 V

0.1 µF VCC1

VCC2

1200 µF/10 V × 3 AIEI

IRL3103 VGATE(H)

VID0

VID0

VID1

VID1

VID2

VID2

VID3

VID3

VID4

VID4

2.0 µH

IRL3103

VGATE(L)

CS5158

COFF

330 pF

1.3 V to 3.5 V @ 13 A

PGND

SS 0.1 µF

COMP

VFB 3.3 k

0.33 µF

LGND

VFFB

1200 µF/10 V × 5 AIEI

100 pF



Value

Unit

0 to 150

°C

230 peak

°C

–65 to +150

°C

2.0

kV






Max Current

VCC1

16 V/–0.3 V

25 mA DC/1.5 A peak

VCC2

16 V/–0.3 V

20 mA DC/1.5 A peak

SS

6.0 V/–0.3 V

–100 µA

COMP

6.0 V/–0.3 V

200 µA

VFB

6.0 V/–0.3 V

–0.2 µA

COFF

6.0 V/–0.3 V

–0.2 µA

VFFB

6.0 V/–0.3 V

–0.2 µA

VID0 – VID4

6.0 V/–0.3 V

–50 µA

VGATE(H)

16 V/–0.3 V


VGATE(L)

16 V/–0.3 V


LGND

0V

25 mA

PGND

0V



CS5158 ELECTRICAL CHARACTERISTICS (0°C < TA < +70°C; 0°C < TJ < +85°C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 14 V;DAC Code: VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Test Conditions

Characteristic

Min

Typ

Max

Unit


VFB = 0 V

–

0.3

1.0

µA

Open Loop Gain

1.25 V < VCOMP < 4.0 V; Note 2

50

60

–

dB


Note 2

500

3000

–

kHz

COMP SINK Current

VCOMP = 1.5 V; VFB = 3.0 V; VSS > 2.0 V

0.4

2.5

8.0

mA

COMP SOURCE Current

VCOMP = 1.2 V; VFB = 2.7 V; VSS = 5.0 V

30

50

70

µA

COMP CLAMP Current


0.4

1.0

1.6

mA

COMP High Voltage

VFB = 2.7 V; VSS = 5.0 V

4.0

4.3

5.0

V

COMP Low Voltage

VFB = 3.0 V

–

160

600

mV

PSRR

8.0 V < VCC1 < 14 V @ 1.0 kHz; Note 2

60

85

–

dB


Output switching

3.75

3.90

4.05

V

Stop Threshold


3.70

3.85

4.00

V

Hysteresis

Start–Stop

–

50

–

mV



–

1.2

2.0

V



–

1.0

1.5

V

Out Rise Time


–

30

50

ns

Out Fall Time


–

30

50

ns



–

25

50

ns



–

25

50

ns


Resistor to LGND

20

50

100

kΩ



–

600

800

mV



–

1.6

3.3

5.0

ms

Pulse Period

–

25

100

200

ms

Duty Cycle


1.0

3.3

6.0

%

COMP Clamp Voltage

VFB = 0 V; VSS = 0

0.50

0.95

1.10

V



0.9

1.0

1.1

V

–

2.5

3.0

V

High Threshold

–



–

100

125

ns

VFFB Bias Current

VFFB = 0 V

–

0.3

–

µA



CS5158 ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < +70°C; 0°C < TJ < +85°C; 8.0 V < VCC1 < 14 V; 5.0 V < VCC2 < 14 V;DAC Code: VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1.0 nF; COFF = 330 pF; CSS = 0.1 µF, unless otherwise specified.) Characteristic

Test Conditions

Min

Typ

Max

Unit

DAC Input Threshold


1.00

1.25

2.40

V



25

50

100

kΩ

4.85

5.00

5.15

V

–

–

1.0

%

Pull Up Voltage

–

Accuracy (all codes except 01111 at 0.8%)


VID4

VID3

VID2

VID1

VID0

0

1

1

1

1

–

1.2896

1.3000

1.3104

V

0

1

1

1

0

–

1.3365

1.3500

1.3635

V

0

1

1

0

1

–

1.3860

1.4000

1.4140

V

0

1

1

0

0

–

1.4355

1.4500

1.4645

V

0

1

0

1

1

–

1.4850

1.5000

1.5150

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Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits

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Practical Design Techniques for Sensor Signal Conditioning

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Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits

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High-Frequency Analog Integrated Circuit Design

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Design of Analog CMOS Integrated Circuits

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Fault Diagnosis of Analog Integrated Circuits

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Design of Analog CMOS Integrated Circuits (Solutions)

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Integrated Project Management

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Integrated Project Management

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Distortion Analysis of Analog Integrated Circuits

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Smart AD and DA Conversion (Analog Circuits and Signal Processing)

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CMOS Processors and Memories (Analog Circuits and Signal Processing)

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Reuse-Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits

Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits

Practical Design Techniques for Sensor Signal Conditioning

Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits

High-Frequency Analog Integrated Circuit Design

Design of Analog CMOS Integrated Circuits

Fault Diagnosis of Analog Integrated Circuits

Design of Analog CMOS Integrated Circuits (Solutions)

Design of Analog CMOS Integrated Circuits

Integrated Project Management

Integrated Project Management

Design of Analog CMOS Integrated Circuits

Distortion Analysis of Analog Integrated Circuits

Design of Analog CMOS Integrated Circuits

Smart AD and DA Conversion (Analog Circuits and Signal Processing)

CMOS Processors and Memories (Analog Circuits and Signal Processing)

Air-conditioning and refrigeration

Mixed-signal and DSP Design Techniques (Analog Devices)

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