Advances in Electronics and Electron Physics, Volume 86 (Advances in Imaging and Electron Physics)

ADVANCES IN ELECTRONICS AND ELECTRON PHYSICS VOLUME 86 EDITOR-IN-CHIEF PETER W. HAWKES Centre National de la Recher...

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ADVANCES IN ELECTRONICS AND ELECTRON PHYSICS

VOLUME 86

EDITOR-IN-CHIEF

PETER W. HAWKES Centre National de la Recherche Scient$que Toulouse. France

ASSOCIATE EDITOR

BENJAMIN KAZAN Xerox Corporation Palo Alto Research Center Palo Alto, California

Advances in

Electronics and Electron Physics EDITEDBY PETER W. HAWKES CEMESILaboratoire d’Optique Electronique du Centre National de la Recherche Scientijique Toulouse, France

VOLUME 86

ACADEMIC PRESS, INC. Harcourt Brace Jovanovich, Publishers

Boston San Diego New York London Sydney Tokyo Toronto

This book is printed on acid-free paper. @ COPYRIGHT 0 1993 BY ACADEMIC PRESS,INC. ALL RIGHTS RESERVED. NO PART OF THIS PUBLICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS, ELECTRONIC OR MECHANICAL, INCLUDING PHOTOCOPY, RECORDING, OR ANY INFORMATION STORAGE AND RETRIEVAL SYSTEM, WITHOUT PERMISSION IN WRITING FROM THE PUBLISHER.

ACADEMIC PRESS,

INC. 1250 Sixth Avenue, San Diego. CA 92101-4311

United Kingdom Edition published by

ACADEMIC PRESS LIMITED 24-28 Oval Road, London NWI 7DX

LIBRARY OF CONGRESS ISSN 0065-2539 ISBN 0-12-014728-9

CATALOG C A R D

NUMBER: 49-7504

PRINTED IN THt UNITED STATES OF AMERICA

93

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BC 9 8 7 6 5 4 3 2

1

CONTENTS CONTRIBUTORS . . . . . . . . . . . . . . . . . . . . . . . PREFACE. . . . . . . . . . . . . . . . . . . . . . . . . .

Recent Advances in GaAs Dynamic Memories JAMESA . COOPER. JR. I . Introduction. Motivation. and Potential Applications . . . IT. pn-Junction Storage Capacitors . . . . . . . . . . . . I11. JFET and MESFET DRAM Cells . . . . . . . . . . . IV . Heterostructure DRAM Cells . . . . . . . . . . . . . V . Bipolar DRAMS. . . . . . . . . . . . . . . . . . . . VI . Future Directions . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . .

vii ix

. . . . .

Expert Systems for Image Processing. Analysis. and Recognition TAKASHI MATSUYAMA I . Introduction . . . . . . . . . . . . . . . . . . . . . I1. Expert Systems for Image Processing and Analysis (ESIPAs) 111. Representing Knowledge about Image Analysis Strategies . . IV . Representing Spatial Relations and Spatial Reasoning for Image Understanding . . . . . . . . . . . . . . . . . . Concluding Remarks . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . .

1 6 32 44 59 64 77

81 87 124 143 163 168

n-beam Dynamical Calculations KAZUTO WATANABE I. I1. I11. IV . V.

Introduction . . . . . . . . . . . . . n-beam Dynamical Calculation Methods Bethe Method . . . . . . . . . . . . . Multislice Method . . . . . . . . . . Coupled Differential Equations . . . . V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

173 176 178 187 199

vi

CONTENTS

VI. Summary. . . . . Acknowledgments . Appendix A: Crystal References . . . .

. .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

218 2 19 219 22 1

Methods for Calculation of Parasitic Aberrations and Machining- Tolerances in Electron Optical Systems M. I. YAVOR 225 I. Introduction . . . . . . . . . . . . . . . . . . . . . 11. Parasitic Aberrations caused by Electron Optical Element 227 Misalignment . . . . . . . . . . . . . . . . . . . . . 111. Effects of Electromagnetic Field Disturbances on Charged Particle Trajectories . . . . . . . . . . . . . . . . . . 235 IV. General Methods for Calculation of Electromagnetic Field Disturbances due to Electrode or Pole Face Distortions. . . 245 V. Field Disturbance in Electrostatic and Magnetic Sector Analyzers . . . . . . . . . . . . . . . . . . . . . . . 26 1 VI. Application of Approximate Conformal Mappings . . , . . 269 VII. Conclusion . . . . . . . . . . . . . . . . . . . . . . 277 References . . . . . . . . . . . . . . . . . . . . . . 279

INDEX. . . . . . . . . . . . . . . . . . . . . . . . . .

28 3

CONTRIBUTORS Numbers in parentheses indicate the pages on which the authors’ contributions begin.

JAMES A. COOPER, JR. (l), School of Electrical Engineering, Purdue University, West Lafayette, IN 47907- 1285 (8 l), Department of Information Technology, Faculty TAKASHI MATSUYAMA of Engineering, Okayama University, 3- 1 - 1 Tsushima-Naka, Okayama, Okayama 700, Japan

KAZUTO WATANABE (173), Tokyo Metropolitan Technical College, 1-10-40 Higashiohi, Shinagawa-Ku, Tokyo 140, Japan M. I. YAVOR(225), Institute of Analytical Instrumentation, Pr Ogorodnikova 26, 198103 St. Petersburg, Russia

vii

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PREFACE

Computer memory, expert systems in image processing, and image simulation and tolerances, are the themes of this volume. All of them are of considerable importance today. We begin with an account by James A. Cooper on the use of gallium arsenide for dynamic RAM technology. Attractive though GaAs is, there are problems to be overcome and James Cooper examines these critically, notably the limitations to long-term charge storage on p n junctions. He then examines the various one-transistor dynamic RAM cells, notably junction field-effect transistors, metal-semiconductor FETs, modulationdoped FETs, heterojunction, quantum well and bipolar cells. His chapter ends with a critical examination of future possibilities. The chapter has numerous illustrations to help make this material accessible to a wide readership. The second chapter deals with expert systems for image processing, analysis and recognition. This is a rapidly developing field of great commercial as well as intellectual importance. Takashi Matsuyama subtitles his account “Declarative Knowledge Representation for Computer Vision,” which reminds us that in these expert systems we have to distinguish between procedural and declarative knowledge. After an introductory analysis of the problem and a brief recapitulation of the associated vocabulary, the author explores in detail expert systems in the field of image processing and analysis. A section is then devoted to the representation of strategic knowledge and a further section deals with the important topic of spatial relations in image understanding. Here too, the many examples should help the reader through this difficult but important material. The third chapter is concerned with the simulation of images by the n-beam method, which is a topic of major importance for the electron microscopist. Although this is a subject that is found in textbooks on high-resolution microscopy, new ideas and fresh developments continue to appear in the specialized journals. This survey by an expert, Kazuto Watanabe, is therefore very welcome. Simulation is an essential step in the interpretation of electron images when the detail is close to the limit of resolution of the instrument since direct interpretation is impossible or at best risky. The volume ends with a chapter by Michael Yavor on a remarkably unpleasant topic in particle optics, the calculation of parasitic aberrations. These aberrations arise as a result of imperfect machining of polepieces and electrodes, and are almost inevitable owing to the extremely high tolerances ix

X

PREFACE

that have to be maintained not only in machining but also in alignment. They are not easy to calculate because they require either the application of a sophisticated perturbation calculation to a system of relatively high symmetry (typically two planes of symmetry or rotational symmetry) or the development of a fully three-dimensional approach. Although the theory of such aberrations has been known for several decades, the practical implications have not yet been fully explored. This is hence a valuable, and bold, addition to the subject. In conclusion, I thank all the authors for taking so much time to work on their chapters, and I append a list of those anticipated in forthcoming volumes of the series.

FORTHCOMING ARTICLES Neural networks and image processing Image processing with signal-dependent noise Parallel detection Microscopic imaging with mass-selected secondary ions Magnetic reconnection Sampling theory ODE methods Interference effects in mesoscopic structures Integer sinusoidal transforms The artificial visual system concept Minimax algebra and its applications Corrected lenses for charged particles Data structures for image processing in C The development of electron microscopy in Italy Electron crystallography of organic compounds The study of dynamic phenomena in solids using field emission Gabor filters and texture analysis Amorphous semiconductors Median filters

J. B. Abbiss and M. A. Fiddy H. H. Arsenault P. E. Batson M. T. Bernius

A. Bratenahl and P. J. Baum J. L. Brown J. C. Butcher M. Cahay W. K. Cham J. M. Coggins R. A. CuninghameGreen R. L. Dalglish M. R. Dobie and P. H. Lewis G. Donelli D. L. Dorset M. Drechsler J. M. H. Du Buf W. Fuhs N. C. Gallagher and E. Coyle

xi

PREFACE

Bayesian image analysis Non-contact scanning force microscopy with applications to magnetic imaging Theory of morphological operators Noise as an indicator of reliability in electronic devices Applications of speech recognition technology Spin-polarized SEM Fractal signal analysis using mathematical morphology Electronic tools in parapsychology Image formation in STEM Phase-space treatment of photon beams Fuzzy tools for image analysis Z-contrast in materials science Electron scattering and nuclear structure Edge detection The wave-particle dualism Electrostatic lenses Scientific work of Reinhold Rudenberg Metaplectic methods and image processing X-ray microscopy Accelerator mass spectroscopy Applications of mathematical morphology Focus-deflection systems and their applications The suprenum project Knowledge-based vision Electron gun optics Spin-polarized SEM Cathode-ray tube projection TV systems

Parallel imaging processing methodologies Signal description The Aharonov-Casher effect

S. and D. Geman U. Hartmann

H. J. A. M. Heijmans B. K. Jones H. R. Kirby K. Koike P. Maragos R. L. Morris C. Mory and C. Colliex G. Nemes S. K. Pal S . J. Pennycook G . A. Peterson M. Petrou H. Rauch F. H. Read and I. W. Drummond H. G . Rudenberg W. Schempp G. Schmahl J. P. F. Sellschop J. Serra T. Soma 0. Trottenberg J. K. Tsotsos Y. Uchikawa T. R. van Zandt and R. Browning L. Vriens, T. G . Spanjer and R. Raue S. Yalamanchili A. Zayezdny and I. Druckmann A. Zeilinger, E. Rase1 and H. Weinfurter


.

ADVANCES IN ELECTRONICS AND ELECTRON PHYSICS VOL . 86

Recent Advances in GaAs Dynamic Memories JAMES A . COOPER. JR . School of Electrical Engineering. Purdue University. West Lafayette. IN

I . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . A . Introduction and Background . . . . . . . . . . . . . . . . . B. Motivations for the Development of DRAM Technology in GaAs . I1. pn-Junction Storage Capacitors . . . . . . . . . . . . . . . . . . . A . General Description . . . . . . . . . . . . . . . . . . . . B. Charge Storage on pn Junctions . . . . . . . . . . . . . . . . C . Theory of pnp Storage Capacitors . . . . . . . . . . . . . . . D . Experimental Results . . . . . . . . . . . . . . . . . . . . . I11. JFET and MESFET DRAM Cells. . . . . . . . . . . . . . . . . A . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . B. Implementations of JFET and MESFET DRAM Cells . . . . . . C . Effect of Transistor Gate Leakage . . . . . . . . . . . . . . . D . A 4-Bit JFET Dynamic Content-Addressable Memory . . . . . . IV . Heterostructure DRAM Cells . . . . . . . . . . . . . . . . . . . . A . Introduction . . . . . . . . . . . . . . . . . . . . . . . . B . Undoped Heterostructure DRAMs . . . . . . . . . . . . . . . C . Quantum-Well Floating-Gate DRAMs . . . . . . . . . . . . . D . Modulation-Doped Heterostructure DRAMs . . . . . . . . . . . V . Bipolar DRAMs . . . . . . . . . . . . . . . . . . . . . . . . A . Introduction . . . . . . . . . . . . . . . . . . . . . . . . B. Concept of the Bipolar DRAM Cell . . . . . . . . . . . . . . . C . Experimental Results . . . . . . . . . . . . . . . . . . . . . VI . Future Directions . . . . . . . . . . . . . . . . . . . . . . . . A . Introduction . . . . . . . . . . . . . . . . . . . . . . . . B. Trench Capacitors and Stacked Capacitors in GaAs . . . . . . . C . Nondestructive Readout Cells . . . . . . . . . . . . . . . . . D . Ultra-Long Storage Times: Quasi-Static and Nonvolatile DRAMs . E . Nonconventional Applications . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . .

. . . .

. . . .

. . . .

. . . . . . . . .

. . . . . . . . .

. . . . . . . . .

. . . . . . . . .

. . . . . . . . . . . .

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1 1

4 6 6 8 16 23 32 32 32 37 40

44 44 44 49 54 59 59 59 62

64 64 65 69 71

74 17

1. INTRODUCTION. MOTIVATION. AND POTENTIAL APPLICATIONS A . Introduction and Background

The evolution of electronic systems inevitably creates demand for integrated circuits with higher integration densities. higher speeds. and lower power consumption. Often the performance of a system is limited by a relatively 1

Copyright 0 1993 by Academic Press. Inc . All rights of reproduction in any form reserved . ISBN 0-12-014728-9

2

JAMES A. COOPER, JR.

small number of components in certain critical paths, so that improvements in the speed of these components reflect directly in enhanced performance of the system as a whole. The desire for high-speed integrated circuits for such applications has led to the investigation of GaAs as a host semiconductor for high-performance systems. The trend toward programmable digital systems has intensified the need for large quantities of high-speed digital memory. To date, most of the memory development in GaAs has been based on simple adaptations of existing GaAs circuit technology in the form of six-transistor static storage cells (Fiedler, Chun, and Kang, 1988; Makino et al., 1988, 1990; Vogelsang et al., 1988; Terrell, Ho, and Hinds, 1988; Maysue et al., 1989; Nakano et al., 1990), as shown in Fig. l(a). These cells are organized in a two-dimensional array to form a random-access memory (RAM). Circuits of up to 16 kilobit complexity have been demonstrated, with access times in the 3-7 nsec range. While straightforward to design and build, these static RAM (SRAM) cells are inefficient in two respects: they occupy considerable chip area, and they dissipate static power in the storage state. In silicon integrated circuit technology, the majority of large-scale RAM circuits are one-transistor dynamic RAMS (DRAMs) of the type shown in Fig. l(b). The one-transistor DRAM cell is much smaller than the six-transistor SRAM cell and dissipates negligible standby power, thus permitting large arrays to be incorporated on a single chip. The one-transistor cell consists of a storage capacitor and a single access transistor. In operation, the access transistor is turned on by the word line, electrically connecting the storage capacitor to the bit line. The storage capacitor is then charged to the potential of the bit line, representing either a logic 0 or a logic 1. When the access transistor is turned off by the word line, the storage capacitor is isolated from the bit line and remains charged to the former bit-line potential until leakage currents eventually destroy the stored information. This gradual degradation of the stored potential requires that the storage cell be periodically read and refreshed. The refreshing period must be substantially shorter than the storage time of the weakest cell in the array at the highest operating temperature. In silicon DRAM systems, refresh rates in the neighborhood of 1 kHz are commonly used, and therefore the weakest DRAM cell must have a storage time greater than about 20msec at the highest temperature. The storage capacitor in most silicon DRAMs is a metal-oxide-semiconductor (MOS) capacitor, made possible by the high-quality SiO, insulator formed by thermal oxidation of silicon. One of the obstacles to the development of DRAM cells in GaAs has been the lack of a high-quality native oxide. However, it has been found that charge storage in GaAs can be successfully accomplished using the capacitance of properly designed reversebiased p n junctions. As evidence of progress in this area, Fig. 2 shows the

RECENT ADVANCES IN GaAs DYNAMIC MEMORIES Bit Line

VDD

VDD

3

Bit Line

+ Bit Line

Word Line

(b) FIGURE 1. Six-transistor static RAM cell (a), and one-transistor dynamic RAM cell (b). Static RAM cells in GaAs usually use MESFETs or JFETs.

evolution in room temperature storage time of GaAs homojunction capacitors over the past four years. Note that storage times have increased about one order-of-magnitude every two years and are now over 10 hours at room temperature. These results are far superior to those observed in silicon MOS capacitors. Several types of access transistors are possible in GaAs. These include metal-semiconductor field-effect transistors (MESFETs), junction field-effect transistors (JFETs), modulation-doped field-effect transistors (MODFETs), and heterojunction bipolar transistors (HBTs). All have been investigated

4


loo I

,

1986

,

'

'

' ' ' ,

1987

'

1988

' ' ,

'

1989

' ' '

'

'

1990

' ' '

'

, ' ' ,

1991

I

1992

Year FIGURE 2. Room temperature storage time of GaAspn homojunction storage capacitors as a function of year since development began in 1987. The trend line indicates one order-ofmagnitude increase every two years.

and will be discussed and compared in Sections 111-V. At this point, however, it is appropriate to consider possible applications for GaAs DRAMS. B. Motivations for the Development of DRAM Technology in GaAs As mentioned previously, digital systems in GaAs will require digital memory, and in order to preserve the speed advantage of GaAs systems, this memory must be fast. As a specific example, consider a GaAs microprocessor operating at a clock rate of 200MHz (5nsec cycle time). Such a processor would be similar to the 32-bit GaAs RISC microprocessor designed by Texas Instruments as part of the VSHIC program (Whitmire, Garcia, and Evans, 1988). A typical instruction requires several accesses to external memory. The simple instruction shown in Fig. 3(a) consists of four cycles: fetch instruction, decode instruction, fetch data, operate on data. Each cycle requires 5 nsec, for a total of 20 nsec for the entire instruction. However, if the program and data are stored off-chip in a silicon memory, operation is slowed considerably. For example, assume a 20nsec silicon SRAM is used. Then each external memory access requires the insertion of three "wait states," bringing the total instruction time to 50 nsec, as shown in the bottom half of Fig. 3(a). Now suppose instead we place a high-speed GaAs cache memory on the same chip as the microprocessor. Assuming a good ratio of cache "hits," the wait states can be eliminated and the instruction execution time decreases by a factor of 2.5. Figure 3(b) shows system throughput as a function of CPU cycle time for two cases: (i) when each memory access must be directed to a 20 ns off-chip RAM, and (ii) when each access can be handled by a 0.5 ns

RECENT ADVANCES I N GaAs DYNAMIC MEMORIES

5

Simple 4-Cycle Instruction Format

Decode

Fetch Instruction

-

I Instruction 1 I +t

Fetch Data

Operate on Data

I I

I

cycle

Introduction of Wait States to Accomodate Slow Memory (5 ns cycle time, 20 ns memory access time)

Fetch

Decode Fetch Data

Wait Wait Wait

I

I

I

I

I

I

Operate

Wait Wait Wait

I

D~~

I

CPU Clock Rate (MHz) 1oooo

1000

100

1

10

1000

100

10

0.1

Cycle Time (ns)

FIGURE 3. Part (a) shows a basic four-cycle CPU instruction. Assuming a 5 nsec CPU cycle time, each access to a 20 nsec external memory would require the introduction of four wait states, increasing the execution time to 10 CPU cycles. In part (b) we illustrate the impact that a 0.5 nsec on-chip cache memory would have on system performance as a function of cycle time, assuming a unity cache hit ratio.

on-chip cache memory. It is apparent that the benefits of cache memory increase significantly as the CPU cycle time decreases. In order to be useful, a cache memory must be sufficiently large to ensure a good ratio of cache “hits.” A typical size would be 16 kilobytes (131,072

6


bits). If such a memory were constructed with six-transistor static RAM cells, it would probably be too large to be included on a GaAs microprocessor chip. However, such a cache memory could be implemented using one-transistor dynamic RAM cells without excessive area penalty. There are other motivations for the development of dynamic memory technology in GaAs. A dynamic memory is inherently an analog device, and several specialized applications exist for analog storage. Examples include switched capacitor filters and electronic neural networks (see Section VI). In addition, the basic information obtained in the course of DRAM development is applicable to any device or circuit that requires low leakage, such as GaAs dynamic logic or low-dark-current imagers. As an example, GaAs DRAM research has led to a technique for reducing the subthreshold current in GaAs MESFETs by three orders of magnitude (see Section 111). In the sections that follow we will consider the factors limiting long-term charge storage on pn junctions in GaAs. We will then describe several types of one-transistor DRAM cells, including JFET, MESFET, MODFET, heterojunction, quantum well, and bipolar cells. We will conclude with a discussion of future directions, applications, and opportunities. 11. PN-Junction Storage Capacitors

A . General Description

Dynamic charge storage in GaAs can be accomplished quite efficiently using the capacitance of a properly designed reverse-biased p n junction. In this section we will first discuss the operating principles and design considerations for pn junction storage capacitors. We will then present experimental data on the performance of GaAs p n junction capacitors as a function of doping, geometry, and temperature. To begin, let us consider the pnp test structure shown in Fig. 4. Here the central n-layer is floating, and forms two back-to-back pn junctions with the surrounding p-type layers. The storage time of these back-to-back p n junctions is tested as follows: A bias Vpof either polarity is applied across the structure. This forward biases one p n junction and reverse biases the other. In the process, electrons are removed from the floating n-region across the forward-biased junction, leaving the n-layer at a positive potential. In steady state, the potential of the n-layer is essentially equal to V,, since the steady-state current will be negligible unless the reverse-biased junction is driven into breakdown. When the applied bias is returned to 0, the charge on the n-region redistributes between the two junctions in such a way that both are reverse biased. The n-region is now floating at a positive potential

RECENT ADVANCES IN GaAs DYNAMIC MEMORIES

P GaAs Substrate

FIGURE 4. Schematic of a pnp charge storage capacitor, with junction voltages defined for further analysis. Note that the voltage polarities are chosen so that positive values indicate reverse bias.

somewhat less than V,, as determined by the capacitance divider formed by the two junctions. The storage capacitor will gradually discharge as thermal generation supplies electrons to the positive n-region. This discharge can be monitored by observing the capacitance of the two back-to-back junctions, as illustrated in Fig. 5. Immediately following the bias pulse, this capacitance is small due to the large depletion regions of the reverse-biased junctions. As thermal generation returns the structure to equilibrium, the capacitance gradually rises to the value determined by the zero-bias depletion widths of the two junctions. For discussion purposes, we define the storage time as the time required for the capacitance to return to within l/e (36.8%) of its equilibrium value. In designingpn junction storage capacitors, two objectives must be kept in mind. First, we wish to maximize the charge storage density at a given voltage; i.e., the capacitance per unit area of the junction. Second, we wish to minimize the generation current that discharges the capacitor. Up to a certain point, both these objectives may be met by increasing the doping on both sides of the junction. There is, however, a limit beyond which increasing the doping will actually increase the generation current per unit area and reduce the storage time. These effects will be discussed later in this section. Before moving to a more detailed discussion of charge storage in the pn junction capacitor, however, we will anticipate the final results of this chapter by

8


FIGURE 5 . Capacitance transient observed on a symmetrically-doped pnp storage capacitor. For t < 0 the bias is 0 and the structure is in equilibrium. A bias pulse V, is applied at I = 0 and removed at I = to. During the bias pulse, one junction is forward biased while the other is reverse biased. Electrons are removed from the n-region by the forward-biased junction, leaving that region positive charged. The capacitance decreases due to the increased depletion width of the reverse-biased junction. At t = to the bias is returned to 0. The n-region remains positively charged and both junctions are now reverse biased. Thermal generation gradually returns the structure to equilibrium. The capacitance recovery is approximately exponential in time, with time constant T ~ .

revealing that, by proper design, it has proven possible to achieve both high-charge storage densities (1.85 fC/pm2for a single junction or 3.7 fC/pm2 for a pnp structure at 1 V reverse bias [Dungan, 1989; Dungan et al., 19901) and long storage times ( 2 10 hours at room temperature [Stellwag, Melloch, and Cooper, 1991b]) using pn-junction storage capacitors. B. Charge Storage on pn Junctions 1. Steady-State Relationships

In order to examine the most important features of charge storage on p n junctions, we will make a number of simplifying assumptions. We assume an abrupt (step) junction having uniform nondegenerate doping on each side, as shown in Fig. 6 . We also assume that all dopant atoms are ionized at the temperatures of interest. Employing the depletion approximation, it is easy to show that the maximum electric field, which occurs at the metallurgical


9

Mx -X

0

FIGURE 6 . Cross section of an abrupt pn junction. The voltage polarity is defined so that a positive value represents a reverse bias.

junction, is given by

where E, is the semiconductor permittivity, NA and No are the doping on the p and n sides, respectively, and xp and x, are the depletion widths on thep and n sides. These depletion widths can be expressed in terms of the total potential drop across the junction as

Here VAis the applied voltage, taken to be positive under reverse bias, and V,, is the built-in potential of the junction, given by (4)

where q is the electronic charge, k is Boltzmann’s constant, T is absolute temperature, and niis the intrinsic carrier concentration at temperature T. The capacitance of the junction serves as a useful indicator of the electrostatic state at any given time and is given by

where A is the junction area. Finally, we will calculate the charge storage density of a pn junction. The charge per unit area removed from the junction under reverse bias VAis given

10


where xpoand xn0are the equilibrium values of xpand x,. Making use of either (2) or (3), the charge stored per unit area at reverse voltage V, is

Here we see that the charge storage density increases as the square root of doping and also as the square root of (VB,+ 5 ) .The maximum charge storage density is limited by junction breakdown. In GaAs, to achieve breakdown fields requires charge densities in excess of 5 fC/pm2.However, a more reasonable value for maximum charge storage density is in the range of 1-2 fC/pmz. This is comparable to the planar charge storage densities presently achieved in silicon dynamic RAMS. 2 . Generation Mechanisms In describing the operation of a pnp storage capacitor, we indicated that if the voltage is quickly swept back toward 0, the charge removed from the n-region will not change appreciably. The rate at which charge “leaks back” onto the n-region is a central issue in DRAM cell operation. Working toward an understanding of the charge recovery transient in a pnp structure, we first need to consider the generation mechanisms responsible for leakage in reverse-biased pn junctions. Electron-hole pairs can be created by thermal generation, photogeneration, or impact ionization. Assuming the capacitor is kept in the dark and that internal fields are low enough that impact ionization can be neglected, the primary leakage mechanism is thermal generation (Dungan, 1989). Thermal generation can occur within the depletion region itself or in the neutral bulk within a diffusion length of the depletion region. We will show that generation in the neutral bulk can be neglected compared to generation in the depletion region. Finally, thermal generation may occur along the periphery of the device, where thepn junction is exposed by a mesa etch. This “edge” generation will prove to be important and must be included in calculation of the charge recovery transient. Thermal generation may involve either direct band-to-band transitions or transitions through defect centers in the forbidden band-gap (ShockleyRead-Hall generation). Because of the greater energy required for each transition, band-to-band generation is much less likely than generation by means of defect centers (SRH generation). Therefore, we will neglect bandto-band generation in the discussions which follow.


11

a. Generation in the Depletion Region. The bulk generation rate per unit volume due to a single-level defect center at energy ETis given by (Shockley and Read, 1952)

n: - np (8) zp(n + n1) + TAP +PI) Here n and p are the electron and hole densities, z, and 7p are electron and hole lifetimes, and n, and p , are constants that depend on the energy E T of the defect center. Since we have assumed nondegenerate material, the carrier densities can be written

G=

n = niexp( F,, T - Ei

)

(9)

where F, and Fp are the quasi-Fermi levels for electrons and holes, and E, is the intrinsic Fermi level, usually taken to lie approximately at midgap. The constants n, and p, are the carrier densities that would be present if the respective Fermi levels lay at the energy ET. Therefore, we can write

PI =.PI(

T)

- ET

The np product in the numerator of (8) can be obtained by multiplying (9) and (10): np = n:exp( F" -7;T-) -Fp It is commonly assumed that the quasi-Fermi levels can be extended across the depletion region of a pn junction with essentially zero slope. Under this assumption, the splitting of the quasi-Fermi levels within the depletion region is equal to the applied voltage, and (13) may be written np

= n:exp(

%)

Combining (8)-(12) and (14), we can write

Equation (15) gives the generation rate per unit volume at any point within

12

JAMES A. COOPER, JR. 1.5

,

,

,

,

,

,

,

,

,

N A = N D = l x l O ” cmm3

-

V*=5V

. c

1.0

-

0.5

-

i

1

0

u b‘

,

0.0

I

,

t i , ;

FIGURE 7. Generation rate per unit volume as a function of position in the depletion region, calculated using (15). Here we have assumed a symmetrical junction with midgap generation centers.

the depletion region. To calculate the total leakage current per unit area arising from generation within the depletion region, we need to integrate (15) with respect to position from one edge of the depletion region to the other: + XP

Jdepl

=4

G ( 4&

(16)

The integration in (16) is complicated by the fact that the terms (F, - E,) and ( E , - F,) in (15) are strong functions of position. The simplest way to evaluate the integral in (16) is to recognize that the integrand is very nearly a rectangular function of position. Figure 7 shows the generation rate given by (15) as a function of position for a typicalpnjunction. Note that G(x) goes exponentially to 0 wherever either (F,, - E T ) or ( E , - 4 ) is positive. When both (F,, - E T ) and (ET - F,) are negative, the exponential terms may be


13

neglected and (15 ) reduces to G=“[l %

-exp(s)]

where z, is a generation lifetime given by %=

e(E~-EOIkT p

e(E,--Er)IkT

+

n

(18)

In the typical case, V, 9 kT/q, so that (17) becomes simply G = ni/zc. The leakage current can then be expressed as

where W, is the generation width, defined as the region within which (Fn- E,) and (E, - F,) are negative; i.e., the region where F, < E, < Fp.

b. Generation in the Neutral Regions. Hole-electron pairs that are thermally generated withln one diffusion length of the edge of the depletion region can also contribute a leakage current that will discharge the capacitor. This diffusion current is described by the Shockley diode equation:

where D,and Dpare diffusion coefficients, L, and Lpare diffusion lengths, and npo and pnoare equilibrium minority carrier concentrations for electrons and holes, respectively. This diffusion current arises as a result of the concentration gradient of minority carriers in the neutral regions adjacent to the edge of the depletion region. Under sufficiently large reverse bias (V, > 0), the minority carrier concentrations at the edge of the depletion regions are essentially 0, while deep within the neutral regions they are at their equilibrium values: npo= n f / N Aand pno= $IND. This concentration gradient gives rise to a steady diffusion current in the reverse direction. In GaAs pn junction storage capacitors, however, this diffusion current is negligible compared to generation within the depletion region (Dungan, 1989). This can be seen by the following calculation: At room temperature, n: in GaAs is approximately 4 x 10l2cm-6 while the doping densities N, and ND for typical storage capacitors are in the range lO”-lO’*~m-~.Thus the equilibrium minority concentrations npoand p,,,, are typically on the order of lo-’ ~ r n at - ~room temperature. Assuming reasonable values for diffusion coefficients and diffusion lengths, we estimate a total diffusion current of about 2000 carriers/(cm2s). If the capacitor has an area of 10 x 10 pm’, the Carrie&, or total diffusion current discharging the capacitor is only 2 x one carrier returned to the storage capacitor every eight minutes. Since the

14


minimum charge stored on the capacitor is at least lo6 carriers, this leakage rate is totally negligible. c. Generation at the Junction Perimeter. Leakage current arising from generation at the perimeter of the storage capacitor must also be considered. Experimental measurements on real storage capacitors indicate that a substantial portion of the leakage current is due to such generation. At etched surfaces the termination of the crystal lattice gives rise to a continuum of generation-recombination centers distributed across the bandgap in energy. The total generation rate per unit area at the perimeter can be calculated by summing the contributions from generation centers at various energy levels across the band-gap. Thus, in analogy to (8), we may write (Schroder, 1987)

where n, and p , are the carrier densities at the surface, ,c, and c,, are capture coefficients of surface centers for holes and electrons, and D,T(E) is the density of surface centers at energy E measured per unit area per eV. The terms nls and pisare functions of energy E and are analogous to the n, and p i terms defined for bulk centers in (11) and (12) earlier. As in the case of bulk generation, we regard (21) as representing the surface generation rate at one point within the depletion region and integrate (21) with respect to position within the depletion region. Thus, by analogy to (16), the surface generation contribution to current in the depletion region is given by

j

+X P

J W P

=4

GP(x)dx

(22)

- Xn

In order to calculate this integral, we recognize that n, and p s are functions of x,and that the G, in the integrand will be negligible except in the region WGpwhere both n, and p s are small compared to ni. Since n, and p , are negligible within W,,, the integrand GPis independent of position and can be taken outside the integral in (22). Thus, combining (21) and (22) using these considerations leads to

where s, is identified as the surface generation velocity. Equation (24) for surface generation in the depletion region is the direct counterpart to (19) for bulk generation in the depletion region.


15

3. Charge Recovery Transient

Combining (19) and (24) and taking into account the area and perimeter of the junction leads to an expression for the total generation current discharging the p n junction storage capacitor

z = ( ~ c e p )l A +

( ~ d e p 1 . P )= ~

qni

[(3) + w,,s)P] 7,

A

(

(25)

Using (6), the total charge stored on the capacitor can be written

Q = qNA(xp - x p ~ ) A (26) where xp is the depletion width on the p side of the junction and x is the 40 value of xp in equilibrium. To maintain charge neutrality, we require that NA ( x p - x p O ) = ND ( x n - xnO) (27) where x, and xd are the actual and equilibrium values of depletion width on the n-side of the junction. Denoting (x, + x , ) by Wand (xpO xd) by Wo,we can write

+

In order to write the differential equation governing charge decay in a p n junction charge storage capacitor, we must obtain expressions for the effective generation widths W, and W, in (25). The generation width W, was introduced in (19) and defined as the width of the region where F, < E, < F,. For the most general situation where NA # No and E , # E,, the expressions for W, as a function of bias are cumbersome (Dungan, 1989). However, if the generation centers lie very close to midgap ( E , x E,) and the junction is symmetrically doped (NA= ND = NB),then the expression for the generation width W, is simplified considerably. Under these assumptions, one can show that W,

-+

(W - W,). . .if NA = ND and E,

= E,

(29) where W is the depletion width at reverse bias and W, is the equilibrium depletion width ( VA= 0). If we further assume that the generation width at the perimeter is the same as the generation width in the bulk, we can write (Dungan, 1989) that

w,=

W,,=(W-

Inserting (30) into (25) yields

W,)=- 2Q qAN,

16

JAMES A . COOPER. JR

Equation (31) has the solution

Q(r)

=

Q(0)eKf’7s

where tS is the storage time constant defined by

Equation (33) is extremely important to understanding the capabilities of pn junction storage capacitors in GaAs. As will be confirmed by experimental measurements in Section II.C, (33) tells us that the storage time should be a strong function of temperature, since the intrinsic carrier concentration ni increases exponentially with temperature according to

where N, and Nvare the effective density of states in the conduction band and valence band, respectively, and EGis the band-gap energy. Although N,, N,, and E G are weak functions of temperature, the dominant temperature dependence arises because of the kT factor in the exponent. Thus, if (34) is inserted into (33), one expects that a plot of In (tS)versus l/Twould be linear with a slope approximately equal to EG/(2k).In other words, the storage time of a pn junction storage capacitor decreases exponentially with temperature. A second point that is apparent from an examination of (33) is that a plot of 1 / t S versus ( P / A ) should be linear, with slope 2nis,/NB and intercept 2n,/NBt,. From such a plot, it should be possible to estimate both the surface generation velocity and the generation lifetime at a given temperature. A final point should be made with regard to (30)-(33). In developing these equations we have assumed a symmetrically doped junction with generation centers at midgap. If either of these assumptions fail, our equations have to be modified. In the general case where ND# NAor E , # E,, WGis larger than ( W - W,) and the ratio of WG/(W - W,) is bias dependent (Dungan, 1989). As a result, the charge recovery transient in (32) is no longer exactly exponential, and the storage time in (33) loses its special significance. A recovery time can still be defined, however, but it becomes bias dependent. We will touch on this matter again in Section II.C.2. C. Theory of pnp Storage Capacitors Having considered the generation mechanisms and charge recovery transient in pn junctions, we now return to the pnp storage capacitor structure shown


17

in Fig. 4. The behaviour of this structure was described qualitatively in Section 1I.A. 1. Steady-State Capacitance- Voltage Relationship At this point we wish to calculate the capacitance-voltage relation of the pnp structure shown in Fig. 4.We assume that, in general, the two pn junctions are not doped symmetrically, and we designate the doping of the top layer NAl and the bottom layer NA2.When a bias is applied across the pnp structure, negligible current will flow in steady state, since one of the pn junctions is reverse biased. Consequently, the voltage drop across the forward-biased junction is also negligible, and virtually all the applied voltage develops across the reverse-biased junction. Thus, the total capacitance of the structure is that of two capacitors in series, one at essentially zero bias and the other reverse biased by an amount V,. Assume that V, > 0, so that the top junction is forward biased and the bottom junction is reverse biased. Under these conditions (and assuming the dopings NAIand NA2are within about two orders of magnitude of each other) the capacitance of the top junction CJ,(0) will be larger than the capacitance of the bottom junction cJ2( V,). Equation ( 5 ) can be used to calculate both these capacitances. The total capacitance of the pnp structure measured in steady state is then

The total charge stored is given by (7) evaluated for the reverse-biased junction (junction 2):

The steady-state capacitance-voltage relationship (V, swept away from 0 ) is illustrated for two values of NA2in Fig. 8. Note that if the doping is not symmetrical (i.e., NA2# NAI), the capacitance-voltage relationship will not be symmetrical about VA= 0. Figure 8 shows a decreasing capacitance when the voltage is swept away from 0 in either direction (assuming quasi-steady-state conditions), and a different, almost flat, capacitance if the voltage is swept rapidly back toward 0. The capacitance remains nearly constant when the voltage is swept toward 0 because the charge Qlotal removed from the n-region during the outward sweep cannot be quickly restored when the voltage is reduced. Again, assume that V, > 0, so that the top junction is forward biased and the bottom junction is reverse biased. When the applied bias is swept toward 0, the charge Q,,,,, , which originally resided entirely on the bottom junction, must

18

JAMES A. COOPER, JR. 4.0 10 N -

3.5 10

. E

3.0 10

8 .-0

2.510

c)

p

2.0 10

0 -5

-4

-3 -2

-1

0

1

2

3

4

5

Applied Voltage (V)

FIGURE8. Capacitance-voltage curves of a pnp storage capacitor for two different values of doping in the second pf region.

now redistribute between the two junctions in such a manner that the total voltage drop across both junctions adds up to V, . Thus, the voltages V, and V, must satisfy

where Qto,,, is given by (36) when V, reaches its maximum value on the outward sweep. At the same time, we can write

-v,+v,=V,

(38)

Substituting ( 3 8 ) into (37) yields

Equation (39) can be solved for V, as a function of VA.The capacitance of the pnp structure as VAis swept back toward 0 is then given by

where V, is obtained from the solution of (39). Depending on the relative dopings N,, and N A 2 ,the capacitance may increase or decrease as VAis swept toward 0. An example of C-V relationships for both symmetrical and asymmetrical doping is shown in Fig. 8. The value of V, that satisfies (39) when V, = 0 is of particular importance, since this is the voltage across each of thepn junctions at the end of the "write pulse." It is this voltage that determines the generation widths W, and W,, at the start of the charge recovery transient.


19

2. Capacitance Recovery Transient (Dungan, 1989) Assume that the pnp structure has been ,pulsed to a specific voltage V, = Vp, resulting in a stored charge QtOmi, where Qtotai is given by (36).If the structure is symmetrically doped ( N A i= NA2),the charge Qtota, divides equally between junctions 1 and 2. If we further assume that each junction individually is symmetrically doped (N,, = NA2= N,, call this value of doping NB)and that the dominant generation centers lie at midgap (E, = Ei),the charge recovery transient of each junction is given by (32), with Q(0) set equal to Qtota,/2.The instantaneous charge on each junction given by (32) can be related to an instantaneous value of depletion width using (28). Thus, combining (32) and (28), we can write for each junction that Q(t)

Qtotai

= -exp 2

(- t/z,)

=qANB 2 ( W ( t )-

6)

(41)

Solving for W(t), W ( t ) = W,+-exp(-t/z,) Qtotai qANB Since the capacitance of the pnp structure is that of two junctions in series, we can write

As can be seen from (43), the capacitance transient that occurs due to generation within the pn junction is not exponential, but rather the reciprocal of a constant plus an exponential. Plots of (43) for NB = 5 x 10’7cmp3and pulse voltages of 1,2, and 5 V are shown in Fig. 9 as symbols. One is tempted to view the curves in Fig. 9, as truely exponential; i.e., as represented by an equation of the form C(t) = C,, - [C,,- C(O)]exp ( - t / z c )

(44)

In fact, the lines in the figure (barely visible beneath the symbols) are least-squares fits of (44)to the “data” represented by the symbols. The agreement would appear to be excellent, but the time constants zc obtained by the fit are approximately 9, 16, and 32% longer than z, for the 1, 2, and 5 V curves, respectively. Under the assumed conditions of symmetrical doping and midgap generation centers, we can derive an expression relating the measured capacitance recovery time constant zc to the actual charge recovery time constant z, by

20


h

2 610.’

8 a C .-8

c)

510-8

P 0 4 10 -

1

0

1

2

3

4

5

t l zs

FIGURE 9. Capacitance recovery transients (symbols) calculated from (43) for a symmetricalpnp storage capacitor with NA = ND = 5 x lO”cm-’ and pulse voltages of 1,2, and 5 V. The solid lines (almost obscured by the symbols) are least-squares fits to (44).Although the fits appear to be quite good, the time constants T~ obtained by the fitting are longer than T~ by 9, 16, and 32%, as shown on the figure.

equating (43)and (44).As shown by Dungan (1989), this ratio can be written

Here e is the base of natural logarithms (e = 2.7182). The time constant ratio in (45)is typically between 1 and 2. In particular, since Qtota, increases as the square root of pulse voltage V, through (36), the capacitance recovery times observed in experiments will be voltage dependent, increasing as pulse voltage is increased. This is consistent with the trends in Fig. 9. As stated, such variations are typically less than a factor of 2 over the normal range of pulse voltages used (1 V < I V,l < 5 V). Note that the charge recovery time constant ss is not voltage dependent (see eq. 33) - rather it is our approximation of zs by zc that is voltage dependent. The preceding discussion required the rather restrictive assumptions that both junctions are symmetrically doped ( N A ,= ND = N A 2 ) and that the dominant generation centers lie at midgap (ET = Ei). These restrictions may be removed through a more careful calculation of the generation volume, the region where FN < ET < F,. The mathematics involved are straightforward but tedious (Dungan, 1989) and will not be reproduced here. However, an example of such a calculation is shown in Fig. 10. Here we plot the normalized capacitance recovery transient for two pulse voltages and three generation center positions. All six curves are calculated assuming that the (A/ effective generation current per unit volume in the depletion region, Jeff cm’), is equal to unity. The “time” axis actually represents the time integral of the charge density generated per unit volume in the depletion region during


21

1.o

0.8 0.6 0.4

0.2 0.0 0.00

0.01

0.02

0.04

0.03

JEFFt (C/cm

0.05

3,

FIGURE10. Normalized capacitance recovery transients for a nonsymmetrical pnp capacitor ( N A ,= NA2= 1 x 10’8cm-3,ND = 1 x l O ” ~ m - ~for ) two pulse voltages and three generation center energies. The horizontal axis is “time” multiplied by the effective generation current per unit volume Jeff= qn,(l/s, + s,P/A).

the recovery. Actual times can be computed by dividing the normalized = qn,(l/tG s G P / A ) . “time” axis by Jeff One observes that the capacitance recovery time constants in Fig. 10 (the point where the normalized capacitance is 0.632) are dependent both on initial bias and on the energy of the generation center. Again, higher pulse voltages lead to longer capacitance recovery times. However, as stated earlier, the variations are typically less than a factor of 2. We shall see that these corrections are small compared to the range of storage times that arise due to variations in the design of the storage capacitors and the procedures used to fabricate them. In the sections that follow, we will make no particular distinction between the capacitance recovery time constant tC and the charge recovery time constant tS and will simply refer to the measured capacitance recovery time constant as the “storage time” ts.

+

3 . Charge Removal Transient

In the development in Section II.C.1, we made the tacit assumption that charge is removed instantaneously from the n-region whenever a bias V, is applied across the pnp structure. This is not the case, and in fact the charge removal transient that occurs on the application of bias can be extremely slow in a higher band-gap semiconductor material such as AlGaAs or Sic. To obtain closed-form expressions for the charge removal transient, we will consider the simple circuit consisting of a forward-biased diode charging a capacitor, as shown in Fig. 11. For this development, we assume the capacitor has a fixed value independent of voltage. The capacitor is initially at zero voltage, and a bias 6 is applied across the diode-capacitor combination at t = 0. We wish to obtain an expression for the voltage V , across the

22

JAMES A. COOPER. JR

I +

t=O

VA

T

7i7T FIGURE11. Simple circuit model for visualizing the charge removal transient in a pnp capacitor structure.

capacitor as a function of time. The current flowing through the forwardbiased diode may be written 1 = lo ( e q ' ~ ' ~ ' - 1) = C dQ

dt

(46)

where Qc is the charge on the capacitor and I, is the saturation current density of the diode given by I,

=

ya.i(0" + L~NA

--)

0,

(47)

LpND

It is significant to note that I, varies as the square of n,. Since n, decreases exponentially with band-gap energy, as shown by (34), I, may be extremely small in high-band-gap semiconductors at room temperature. The charge on the capacitor can be written Qc = cvc = C ( ~-A VD)

(48)

and its derivative is

Combining (46) and (49) gives a differential equation that may be solved for Vo(t).After algebra, we find that

where

T,,

given by


10.1510-1310-11

l o - O 10-7 .,0-5

23

lo-3

t IT,

FIGURE 12. Diode voltage drop as a function of time for several values of applied voltage

6 during the charge removal transient. The write time can be made arbitrarily short if the write process is terminated before the diode voltage reaches 0. For example, if we are willing to provide a write voltage V, that is 0.25 V greater than the final value of capacitor voltage (allowing VD to be 0.25V % 10kT/q at the end of the write process), then the write time can be reduced to 10-~~,.

is the time for a steady current I, to charge the capacitor C to a potential kT/q. Equation (50) is plotted for several values of V, in Fig. 12. If V, b kT/q and t -g q,, (50) can be simplified to

This relationship explains the linear dependence of the V, = co curve in Fig. 12. It is perhaps more enlightening to plot the capacitor voltage as a function of time, as shown in Fig. 13. The point to note from both figures is that the capacitor charges to within VD(t)of the pulse voltage V, in a specific time t , regardless of the value of VA. Therefore, if we wish to charge the capacitor to a voltage V,, in time t , , this can be accomplished by applying a pulse , V D ( t lis ) obtained from (50) or voltage V, given by V, = V,, + V D ( t l )where Fig. 12. These arguments can be refined by including the specific voltage dependence of the capacitance using (5). This is left as an exercise for the reader.

D . Experimental Results 1. Eflect of Temperature

Consider a large-area storage capacitor in which bulk generation dominates

24


lo-’

10.5

10’

t IT,

FIGURE13 Capacitor voltage as a function of time for several values of applied voltage VA the capacitor dunng the charge removal transient. Note that at a specific time, say t/ro = voltage falls short of the applied voltage VAby the same amount, regardless of the value of VA. This “shortfall” is, of course, the diode voltage drop.

(A/PS

sGtG) so

that the storage time constant given by (33) can be written

Inserting (18) and (34) into (53) and assuming that (i) the dominant generation center is above midgap (this assumption is arbitrary, and equally valid equations would result if the opposite assumption were made), and (ii) z, is of the same order of magnitude as r P ,leads to

where AET = IE, - E l / .Equation (54) suggests that the storage time will be thermally activated with an activation energy EAgreater than or equal to half the band-gap. (Note that we would have reached the same conclusion if we had assumed the generation center to be below midgap, except that t pwould be replaced by 7,). To further appreciate the temperature dependence of (54), note that N , and N y are proportional to T3I2and that T~ is inversely proportional to the thermal velocity vth, which increases as TIi2.Thus, the prefactor is proportional to (1 / T)’. This dependence, however, is overshadowed by the temperature dependence of the exponential factor. In the exponent, the band-gap energy EG is a weak function of temperature and can be approximated by a firstorder Taylor expansion as EG(T) % E G O

-

UT

(55)


25

Temperature ("C) 181

144

111

2.4

2.6

84

60

40

21

3.0

3.2

3.4

F8

d

I"

2.2

2.8

1000/T

(1IK)

FIGURE14. Measured capacitance recovery time constants as a function of temperature for pnp capacitors in GaAs and Al,Ga,_,As (x x 0.2). The recovery process is thermally activated, with activation energies very close to half the band-gap.

where EGO is the extrapolated zero-temperature band-gap and ci is a parameter. For GaAs in the neighborhood of room temperature (Thurmond, 1975), EGO z 1.56eV and ci = 4.17 x 10-4eV/K. Inserting (55) into (54) yields

The first exponential term is now explicitly temperature independent. From the second exponential term, we see that the activation energy should be greater than or equal to half the extrapolated zero-temperature band-gap, which for GaAs is about 0.78 eV. Figure 14 shows measured storage times (Dungan, 1989) forpnp capacitors fabricated in GaAs and Al,Ga,-,As (x z 0.2). These capacitors were grown by molecular beam epitaxy (MBE) and were mesa isolated by chemical etching. The doping and thickness of the layers are the same. The storage times in Fig. 14 are indeed thermally activated, as required by (56), and the activation energies are consistent with generation sites at or very close to midgap (AETz 0). In considering the magnitudes of the storage times, we note that dynamic memories in silicon are typically refreshed at a 1 kHz rate, so that the storage times of individual cells must be longer than the refresh period of 1 msec. To take a conservative view, we shall require a storage time of at least 100msec

26

JAMES A. COOPER, JR Temperature (“C) 182 l0000

144

111

2.4

2.6

84

60

40

21

5

2.8

3.0

3.2

3.4

3.6

1000 100 10 1 0.1 0.01 2.2

lOOO/T(1/K)

FIGUREIS. Capacitance recovery time constants for three GaAs pnp capacitors having different doping concentrations. The doping on the lightly doped side is given in the legend. The ~ ~ Note the reduction longest storage times are obtained for dopings in the low l O ’ ’ ~ n -range. in activation energy for the most highly doped sample (0 1990 IEEE).

for GaAs-based memories. By this criterion, Fig. 14 indicates that both these (unoptimized) pnp storage capacitors would be capable of satisfactory operation to over 100°C. 2. Effect of Doping

Equation (33) indicates that the charge storage time constant T~ is expected to scale directly with doping. This is because higher dopings result in smaller depletion regions, and generation within the depletion region determines the storage time. Also, (7) tells us that the charge storage density, i.e., the charge stored per unit area at a given voltage, increases as the square root of doping. Since long storage times and high-charge storage densities are both desirable, it would appear that high doping levels on both sides of the junction are called for. Figure 15 shows measured time constants for three pnp storage capacitors grown by MBE and mesa isolated by chemical etching (Dungan, 1989; Dungan ef al., 1990). All growth and processing conditions were the same except for the doping of the layers. In all three structures the n-layer is doped 1 x l O ” ~ m - ~The . p-layer dopings are 7 x 1015cm-3,1 x 1017cm-3,and 1 x 1019cm-3.All three capacitors are effectively one-sided step junctions, with the generation occurring primarily on the lightly doped side. The doping of the lightly doped side is shown in the figure. (Note that for the sample with NA = 10’9cm-3,the lightly doped side is the n-region, ND = l O ” ~ m - ~ ) . Equation ( 3 3 ) suggests that the charge recovery time constant should scale linearly with the doping of the lightly doped side. Figure 15 shows that


27

recovery time indeed increases with doping up to about 1 x 1017cm-3. However, the sample with dopings of 1 x 1018cm-3exhibits a reduced time constant at all temperatures and a reduced activation energy. Thus it appears that there is a practical limit above which further increases in doping actually reduce the storage time. The reduced storage time of the most highly doped sample can be explained by the phenomenon of field-induced barrier lowering. This effect occurs when electric fields within the depletion region become high enough to modify the escape energy of carriers confined on a generation center. This can occur when the potential drop over a distance comparable to the radius of the electron orbit is significant compared to the ground-state energy of the center. Frenkel(l938) showed that the change in escape energy AEA is given by -

AEA = 2q/$

(57)

where F is the electric field in V/cm. Thus, AEA calculated by (57) can be viewed as the reduction in activation energy resulting from field-induced barrier lowering. Applying this correction to the data of Fig. 15, we obtain AE, values of 90, 180, and 330meV, respectively, for the three curves of increasing doping density. These values correspond approximately to the differences between activation energies seen in the figure. It has been found experimentally (Dungan, 1989; Dungan et al., 1990) that higher doping levels can be used successfully if a small undoped (or lightly doped) i layer is inserted between the p and n-type regions in each junction, resulting in a p-i-n-i-p structure such as shown in Fig. 16. The i layer has the effect of reducing the maximum electric field in the depletion region, thereby avoiding the barrier lowering phenomenon, while maintaining a very highcharge storage density (high capacitance per unit area). The storage times of two p-i-n-i-p storage capacitors are compared to a pnp storage capacitor of similar doping in Fig. 17. 3. Eflect of Device Area and Device Scaling In order to construct a high-density memory array using p n junction storage capacitors, it is important that the size of the capacitor be reduced as much as possible. Two issues arise immediately: (i) charge storage capacity and (ii) storage time. Clearly, as the area of the capacitor is reduced, the amount of stored charge is reduced proportionally. What is perhaps not immediately apparent is that the storage time is also reduced. We shall consider both of these limitations in this section. First, we consider the charge storage capacity. To permit reliable detection

28

JAMES A. COOPER. JR.

i (undoped) 30nm

N+ 10’’ cmJ i (undoped) 30nm

FIGURE16. Storage capacitor having p-i-n-i-p structure. The presence of the undoped i layers reduces the maximum electric field in the junction, minimizing field-induced barrier lowering, while still providing a high capacitance per unit area.

of the signal charge during readout and to minimize soft errors due to alpha particle strikes, a dynamic memory must store a certain minimum charge in each cell. In silicon dynamic memories, this minimum is typically on the order of lo6 electrons. To understand how this restriction affects the GaAs storage cell, let us consider the p-i-n-i-p capacitor of Fig. 16. For this capacitor, the Temperature (“C) 182 10000

144

111

84

60

40

21

5

2.4

2.6

2.8

3.0

3.2

3.4

3.6

1000

100

sE H

10 1

0.1 0.01 2.2

10001T(IIK)

FIGURE17. Capacitance recovery times for pnp and p-i-n-i-p storage capacitors. By introducing an i layer, we are able to avoid the reduction in room temperature storage time caused by field-enhanced generation.


29

Square Edge Length (pm) 198

98

78

62

5.0 6.25

.-cE

0.16

a,

0.12

8.33

8

0.08

12.5

f

0.04

25.0

P

-

3 v

$

C

0 0 100 200 300 400 500 600 700 800

Perimeter / Area (Ilcm)

FIGURE18. Inverse storage time of square pnp capacitors as a function of P / A ratio at several temperatures. At each temperature, the generation lifetime T~ is calculated from the intercept and the surface generation velocity sc from the slope.

charge storage density of each junction is about 1.85fC/pm2 at a reverse voltage of 1 V. Accounting for both junctions, the area required to store lo6 electrons would be 43 pm2 or 6.6pm on a side. This area would be reduced if a higher signal voltage were used. A reasonable lower limit would appear to be around 25 pm2 or 5 pm per side.’ Next we consider the effect of scaling on storage time. One obvious geometrical consequence of reducing the capacitor area is the fact that the perimeter-to-area ratio P / A increases. Taking the inverse of (33),

(-+

1 =2ni 1 TS

NB

sG;)

TG

This implies that a plot of inverse time constant versus P / A should produce a straight line whose slope is determined by the surface generation velocity and whose intercept is determined by the bulk generation lifetime. This is illustrated by the data (Sheppard, 1991) in Fig. 18 for four different temperatures. The inverse storage time increases linearly with P / A , in good agreement with (58). From the slopes and intercepts, we can calculate values of T~ and sG at each temperature using (58). These data are shown in Fig. 19. Here we see that both T~ and sG are relatively weak functions of temperature I As an aside, we note that one wishes to retain lo6 electrons at the end of one refreshing period. We have defined storage time as the time for the electron density to be reduced to l/e of its initial value. Thus, we should store 2.7 x lo6 charges at the beginning of the transient, requiring 2.7 times the quoted area. However, in practice one never allows the charge to decay to lie of its initial value before refreshing. In fact, if we require the storage time to be at least IOOmsec, but refresh at a 1 kHz rate, the initial charge will only decay to 0.99 of its initial value at the end of one refreshing period.

30

JAMES A. COOPER, JR Temperature (“C)

-

111

104

97

91

84

-‘E In

78

In

Y

r”

C

.-0

c)

e

al c

8 0 Q

lo4 3 2.60

h

2.65

2.70

2.75

2.80

2.85

lOOO/l(lIK)

FIGURE19. Bulk lifetime tG and surface generation velocity sG deduced from the plot of Fig. 18.

(at least compared to the temperature dependence of n,). This slight temperature dependence indicates that the dominant generation centers are not precisely at midgap. The generation lifetime is in the vicinity of 200 ns, which is an excellent value for GaAs. We note that the precise values of T~ are somewhat uncertain, since the intercepts in Fig. 18 are estimated by extrapolation and are sensitive to small errors in fitting the data. Of more practical interest is the time constant to be expected if the area of the storage capacitor is reduced below the 62pm per side of the smallest capacitor shown. If we extrapolate the data in Fig. 18 to a side length of 5 pm, we find a storage time of 1.5 sec at 101OC. This is still comfortably above our criterion of 100msec. Therefore it appears that adequate charge storage densities and acceptable storage times can be achieved with storage capacitors down to 5pm on a side.

4. Metal Evaporation Technique Since storage time is determined by extremely small generation currents, it is to be expected that it should be sensitive to certain details of the processing. One of the most important aspects of the processing in this regard is the method of metal deposition. In fact, the storage time of well-made identically prepared samples is reduced by about three orders of magnitude if the ohmic metal is deposited in an electron-beam evaporator as compared to a thermally heated evaporator (Stellwag et al., 1992a). Figure 20 shows storage time versus temperature for four 100 x 100pm2 p-i-n-i-p storage capacitors (Stellwag et al., 1992a). These capacitors are taken from two wafers whose epitaxial layers were grown by MBE using As, and As, flux, respectively. Both p+ layers are doped 1 x 1019cm-3,the n-layer is


/

lo5

5

Thermally lo3

Evaporated

i! i=

$

// / AS2

z

d

/

10'

lo-'

10"

E-Beam Evaporated

,

1

I

,

1

,

1

,

1

,

1

1

,

I

,

31

32

JAMES A. COOPER, JR

on the flux conditions during MBE growth. This suggests that, rather than creating new centers, the electron-beam environment is simply activating preexisting centers present in the As-grown film, the density of which depends on the growth conditions.

111. JFET

AND

MESFET DRAM CELLS

A . Introduction

In Section I1 we considered the design and performance of pn junction storage capacitors in some detail. However, the storage capacitor is only half the story. In order to construct a complete DRAM cell, it is necessary to provide an access transistor that will connect the storage capacitor to the bit line for reading and writing and isolate the storage capacitor from the bit line during storage. In this section we will consider two means of implementing this access transistor in GaAs: (i) using junction field-effect transistors (JFETs), and (ii) using metal-semiconductor field-effect transistors (MESFETs). Figure 21 shows how one might implement a one-transistor DRAM cell utilizing a JFET access transistor and a MESFET access transistor. In the following sections we will present experimental results on early versions of both JFET and MESFET DRAM cells, with special attention to the effects of transistor leakage on storage time.

B. Implementations of JFET and MESFET DRAM Cells The first demonstration of a complete JFET-accessed GaAs DRAM cell was reported by Neudeck et al. (1989). The structure, shown in Fig. 22, consists of two large-area p + n storage capacitors surrounded by a ring-gate JFET. Two storage capacitors are used in this implementation so that the charge can be monitored by observing the capacitance between the two p+ plates. This is necessary since the structure is fabricated on a 1 pm undoped buffer layer. The layers are grown by MBE, and the p + gates are patterned by wet etch. The 50nm p-type GaAs layer under the channel is included to improve subthreshold performance of the access transistor, and it is fully depleted during normal operation (Yamasaki, Kato, and Hirayama, 1985). Figure 23 shows waveforms obtained during electrical writing of the cell. The top waveform is the capacitance between the twop+ capacitor plates, the middle waveform is the bit line voltage applied to the source of the JFET, and the lower waveform is a series of 1 msec write pulses applied to the gate of the access transistor (the word line). The word line is held at a negative

33


Word Line

PorS.1. GaAs

JFET DRAM Cell

Bit Line

Word Line

ohmic contac

PorS.1. GaAs I

I

MESFET DRAM Cell

FIGURE21. Two examples of FET-accessed DRAM cells in GaAs. Each cell consists of a pn junction storage capacitor and an access transistor. The top drawing depicts a JFET DRAM cell, while the bottom drawing illustrates a MESFET DRAM cell.

potential to keep the JFET biased off. When the word line is pulsed to 0, the JFET is turned on and the potential of the bit line is connected to the storage capacitor. During the first pulse the bit line is positive, and electrons are removed from the n-side of the p n junction storage capacitors. This reverse biases the p n junctions, widening the depletion regions and reducing the capacitance signal. When the second word line pulse occurs, the bit line has returned to 0. This allows electrons from the bit line to flow to the storage capacitors, returning them to their equilibrium conditions. The capacitance is thus increased. One notes that the capacitance signal changes only when the word line is pulsed to 0. This proves that the storage capacitor is effectively isolated by the access transistor: changes in bit line potential have no effect on capacitance while the access transistor is off. The high-capacitance condition occurs when the storage capacitors are in equilibrium, so this state will not decay

34

JAMES A. COOPER, JR. JFET Source (Bit Line)

JFET Drain

JFET Ring Gate (Word Line)

PN Junction Charge Storage Capacitors

50 nm P+ GaAs

FIGURE 22. A prototype JFET DRAM cell implemented in GaAs by Neudeck et al. The cell consists of two storage capacitors surrounded by a ring-gate JFET. Two storage capacitors are used to allow the charge recovery to be monitored by observing the capacitance between the storage gates. A second JFET is included for evaluation purposes (01990 IEEE).

with time. The low-capacitance state represents a reverse bias on the storage capacitor. This is a temporary condition, and the capacitance will gradually return to its equilibrium value as thermal generation discharges the storage capacitor. This can be seen in the waveforms of Fig. 23, where the storage

r

CPII

Capacitance Signal

-

1 -

0

1 msec Write pulse

--)-

-1

-

A L

-2 -

4

wPiue I

4 WPite 0

Bit Line Voltage

4 wuiue I

Word Line Voltage

Time (s)

FIGURE23. Writing waveforms for the JFET DRAM cell of Fig. 22. The upper trace is the cell capacitance, the middle trace is the bit line voltage, and the lower trace is the write pulse train applied to the word line. Note that the cell capacitance changes only at the moments when write pulses are applied to the word line. The stored 1 state gradually decays due to gate leakage in 1990 IEEE). the JFET access transistor and generation in the substrate depletion region (0


-

Storage Node Write Pulse

-

0

>

35

-1 -

r

;

:

?

,

:

:

;

:

-

;

;

Word Line Voltage

time is estimated to be on the order of 1 s. This low storage time is due to two factors. First, the gate-to-drain leakage current in the access transistor flows directly to the storage capacitor. In this prototype geometry, the access transistor is a ring-gate configuration that actually maximizes the leakage current supplied to the storage capacitor. Second, the large undoped buffer layer below the storage capacitor provides a large generation volume for leakage currents discharging the storage capacitor. During normal operation of a GaAs DRAM cell, the cell capacitance would not be monitored. Instead, the charge state of the cell would be detected by a change in potential of the bit line when the access transistor is turned on. This mode of operation is demonstrated in Fig. 24. Here the bit line is connected directly to a high-impedance active oscilloscope probe. The top waveform in the figure is the potential of the probe, the middle waveform is a write pulse applied to the p + terminal of the storage capacitor, and the bottom waveform is the pulse train applied to the word line. The write pulse (middle waveform) momentarily forward biases the pn junction storage capacitor, removing electrons from the n-region. During the first word line pulse, the JFET is turned on and electrons flow from the bit line to the storage capacitor to restore the missing electrons. This causes the bit line to jump to a positive potential. The rapid decay of the bit line signal is caused by the RC time constant of the active probe. By the end of the first word line pulse, the bit line potential has essentially returned to ground, and as a result the storage capacitor is also essentially at ground, The second word line pulse produces almost no response on the bit line, since the storage capacitor is

36


Alloyed Ohm (Bit Line) Contact

E, 0

10pm x 200 p n Au MESFET Ga (Word Line)

0

i Storage Node Connection

50 nm

P-

NA = 1 x 10" cm-3

Undoped GaAs

FIGURE25. Top view and cross section of a MESFET DRAM cell implemented by Neudeck et al. This cell employs a linear gate rather than a ring gate, in order to minimize gate leakage current discharging the storage capacitor.

now at ground potential. Thus the charge state of the cell can be determined by detecting the bit line potential when the access transistor is turned on. Similar results have also been achieved using MESFET access transistors (Dungan et al., 1990). Figure 25 shows the top view and cross section of an experimental MESFET DRAM cell (Neudeck, 1991). Notice that in this structure the ring gate has been replaced by a linear gate. Writing waveforms for the MESFET cell are shown in Fig. 26. These waveforms are very similar to those of the JFET DRAM cell in Fig. 23. In order to eliminate the need for a negative supply voltage, the cell is operated with bit line potentials that vary from 1.3V for a logic 0 to 2.45 V for a logic 1. (A thorough discussion of operating voltage considerations for FET-accessed GaAs DRAM cells can be found in Dungan, 1989, and in Dungan et al., 1990). As expected, the cell capacitance changes only when the access transistor is turned on. In spite of the reduced gate width exposed to the storage capacitors, the storage time for this cell is only about 25 msec at room temperature. The drastic reduction in storage time is the result of increased gate leakage in the MESFET as compared to JFET. This effect will be discussed next.

RECENT ADVANCES IN GaAs DYNAMIC MEMORIES L

-

P5

Cell Capacitance Signal

4 :

1

-

Q

c

,

3-5

5

-0

’

37

r

Bit Line Voltage

2 -

-_

s”

1 psec Pulse

-

1 -

*-Write

MESFET Gate (Word Line) Voltage

0 I

I

I

I

I

I

I

I

FIGURE 26. Writing waveforms for the MESFET DRAM cell of Fig. 25. The top trace is the cell capacitance, the middle trace is the bit line voltage, and the lower trace is the write pulse train applied to the word line. The access transistor threshold voltage is + 0.8 V, and positively 1990 IEEE). shifted logic levels are employed (0

C . Eflect of Transistor Gate Leakage When an access transistor is connected to the storage capacitor, additional leakage mechanisms are introduced that reduce the storage time of the cell, even when the access transistor is deliberately biased into the off state. These leakage mechanisms are illustrated in Fig. 27. The primary leakage mechanisms are subthreshold leakage of electrons from the source to the drain and leakage of electrons from the gate (or gate depletion region) to the drain. Since the drain is connected directly to the storage capacitor, these leakage paths tend to prematurely discharge the capacitor. Subthreshold leakage from the source can be described by (Conger, (Word Line)

t

4 -

Source

Drain

IDG

(Storage Node)

(Bit Line)

ov

++I++

4

IDS

--r-

FIGURE 27. Drain current components in a GaAs field-effect access transistor. The primary mechanisms affecting DRAM storage time are drain-to-source current I,,, and drain-to-gate current I,.

38

JAMES A. COOPER, JR. 10

10 -5

- VDs = + 0.5V

Transistor

ON

0..

c p! L

a

-1 .o

\

/,

10 -10

-0.5

0.0

. 0.5

Gate Voltage (V)

FIGURE28. Drain current as a function of gate voltage in a GaAs field-effect transistor. I,, is the drain-to-source current and IDG is the drain-to-gate current. I,, decreases exponentially with gate voltage below threshold, but eventually I,, dominates. This gate current is not present in silicon MOS transistors, but it is the dominant leakage mechanism in most FET-accessed GaAs DRAM cells.

Peezalski, and Shur, 1988)

Here ZDs, is the current measured at threshold (VGs= VT), V,, is gate-tosource voltage, VTis the threshold voltage, VDs is drain-to-source voltage, and n is a subthreshold ideality factor. If V,, is greater than a few kT, the term in square brackets approaches unity. In any event, the last factor shows that the current decreases exponentially as V,, is reduced below threshold. Unfortunately, one encounters a fundamental difficulty in taking advantage of this exponential reduction in subthreshold current. This is because GaAs, unlike silicon, does not possess a true insulator that can be placed between the gate and channel. As a result, a significant gate-to-drain current can flow whenever the gate becomes too strongly reverse biased with respect to the channel. This is illustrated in Fig. 28, where we show the measured drain current for a GaAs MESFET as a function of gate voltage (Neudeck, 1991). As gate voltage is reduced below threshold, the drain current in Fig. 28 drops exponentially with gate voltage, in agreement with (59). However, a minimum is reached at a gate voltage of about -0.2V; below - 0.2 V the drain current increases. This increase is due to electrons flowing from gate to drain, and the I-V characteristic in this region is that of the reverse-biased gate-to-channel junction. If the transistor of Fig. 28 were used in a p n junction DRAM cell, the storage time would be reduced to a few hundred milliseconds at room temperature. Obviously, there is considerable motivation for minimizing this effect.


39

o3

1

10-4

*

=: 3

j

105

104 107

lo4 lov 10-10 10 -11

-2.0

-1.o

-1.5

-0.5

0.0

Gate Voltage (V)

FIGURE29. Drain current vs. gate voltage for a 5 x 350pm ring-gate JFET.

For comparable devices, gate leakage is considerably lower in a JFET than a MESFET (Dungan et al., 1990; Neudeck, 1991). Figure 29 shows drain current versus gate voltage for a 5 x 350pm ring-gate JFET, while Fig. 30 shows drain current in a 10 x 350pm ring-gate MESFET. At room temperature, the gate-to-drain leakage in the JFET is more than two orders of magnitude smaller than in the MESFET. Thus, one expects superior storage time performance from a JFET-based memory. It has been found that the gate-to-drain leakage of MESFETs can be reduced significantly by treating the GaAs surface with ammonium sulfide (NH,),S just prior to thermal evaporation of Schottky metal (Neudeck et al., 1991a). (It is important in this procedure that the metal not be deposited in an electron-beam evaporator). Figure 31 shows drain and gate currents at room temperature for treated and untreated 10 x 350pm ring-gate

10.~ 10’~ 10.~

10.’

10.’ 10.10

-1.4

-1.2

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

Gate Voltage (V)

FIGURE30. Drain current vs. gate voltage for a 10 x 350 pm ring-gate MESFET. Note that at room temperature the gate-to-drain leakage in the MESFET is more than two orders of magnitude higher than in the JFET of Fig. 29.

40

JAMES A. COOPER, JR

10.~ 10.6 10” 10-8

10.”

lo-’* -1.o

-0.5

0.0

0.5

Gate Voltage (V)

FIGURE31. Drain and gate currents for a 10 x 350pn ring-gate MESFET with and without (NH,),S surface treatment prior to gate metal deposition. In the treated device the gate current exceeds the drain current for Vc < - 0.3 V because the gate depletion region is punching through to the substrate, causing substrate holes to flow to the gate. This phenomenon has no effect on DRAM storage (01991 IEEE).

MESFETs. The drain current in the treated device is reduced by about three orders of magnitude compared to the untreated device. (In the treated device, the gate current exceeds the drain current below about - 0.3 eV. This excess gate current is due to gate-to-substrate punchthrough, and has no effect on the storage time of the DRAM cell, since it does not flow to the storage capacitor .) The reduction in gate-to-drain current in the treated devices is attributed to an increase in Schottky barrier height that results from an unpinning of the Fermi level (Carpenter, Melloch, and Dungan, 1988). The (NH,)2S layer is thought to passivate most of the surface states that otherwise would exist at the metal-semiconductor interface. Although (NH,),S-treated surfaces degrade within a few hours if exposed to air, the presence of the metal gate protects the (NH,),S layer in these MESFETs. No changes in I-V characteristics could be detected after over a year of undessicated storage at room temperature.

D. A 4-Bit JFET Dynamic Content-Addressable Memory As a final example of demonstration circuits involving GaAs DRAM technology, we consider the four-bit dynamic content addressable memory (DCAM) constructed by Neudeck and coworkers (Neudeck, 1991). In a content-addressable memory, each storage cell contains logic to compare the bit of information stored in the cell with a binary signal presented on the bit line. The organization of a typical content addressable memory is depicted in Fig. 32. Each word in the memory array contains many bits of data stored


41

Bit Line

Word Line

Match Line

Word Line

Match Line

FIGURE 32. Schematic diagram of a content-addressable memory. Each memory cell contains logic elements that compare the contents of the cell to the information on the bit lines. If a bit fails to match, the cell pulls its match line to ground. Only if all cells in a word match the input pattern will the match line for that word remain high.

in individual cells connected to a common word line. In addition, the storage cells in each word of a content addressable memory are also connected to a second horizontal line called the match line. To select a stored word based on content, a binary pattern is impressed on the bit lines. Each cell in the memory compares its stored bit to the bit on its bit line. If any cell finds a mismatch, it pulls its associated match line to ground. Only if every bit in a word matches the input pattern will the associated match line remain high. Content addressable memories are useful in situations where large data bases are to be searched rapidly for specific patterns. The GaAs DCAM cell (Neudeck, 1991) is shown in Fig. 33. This cell consists of two JFET DRAM cells and four additional n-channel JFETs used to implement an exclusive-nor (XNOR) function. A unique feature of this design is the fact that an ohmic contact is established to the n-type region of the storage capacitor in each DRAM cell. This contact is connected to the gate of an n-channel JFET in the XNOR logic so that the contents of the cell can be compared with the new data on the bit lines. Altogether, six transistors and two storage capacitors are required per cell. The cell of Fig. 33 is implemented in a 2 x 2 DCAM array, complete with peripheral circuitry to load the memory with initial data, read the stored data using the bit lines, select the word lines, and read the match lines. In all, 40 JFETs and 8 storage capacitors are involved. Figure 34 shows operating waveforms of the 2 x 2 DCAM array. During the first six cycles a distinctive binary pattern (all 0s) is loaded into the

42

JAMES A. COOPER, JR. Word Line I

-

. Bit

Bit Line

Line

Match Line

5 0,

L

m

B L

Storage Node Contact

Storage Capicitor (Gate Metal)

v)

>m

‘DRAM Access JFET

FIGURE33. Schematic of one cell of the JFET DCAM cell (top) and layout of the cell (bottom). Each cell consists of two one-transistor DRAM cells and four n-channel JFET XNOR transistors. A two-level metal process is employed, with the top interconnect metal placed on polyimide for isolation.


43

Keyword Input (81 & 82) and Match Line Output (M1 & M2)

MI M2

81

881

82

882

Stored Memory Contents

FIGURE 34. Operating waveforms of the 2 x 2 JFET DCAM array. The two match line and four bit line waveforms are shown for six cycles. During each cycle, the memory is loaded with a four-bit data pattern and then presented with nine interrogation patterns. The boxes at the bottom indicate the data pattern written into each word of the memory. The boxes at the top indicate the nine interrogation patterns and the match line responses. A d represents a “don’t care” condition, implemented by taking both bit and bit-bar lines low; d bits always match the stored bit.

memory. In the next nine cycles, all possible binary input patterns (including “don’t care” inputs) are presented and the match line outputs tabulated at the top of the figure. Beginning with the sixteenth cycle, a new data pattern (all 1s) is loaded into the memory and the interrogation pattern repeated. This cycle continues until all stored data patterns are verified with all possible input combinations. In all cases, the DCAM produced the correct outputs. The array was also tested as an eight-bit DRAM. In this mode, the match lines are ignored and the individual DRAM cells in each DCAM cell are written and read out using the bit lines. The array was fully functional in this mode as well.

44


This DCAM array is far too small to be useful, it does not contain all the necessary peripheral logic such as sense amplifiers and address decoders, and it has not been optimized for minimum cell size or maximum speed of operation. Nevertheless, it does demonstrate that GaAs JFET DRAM cells can be combined into a working memory array, that they can be read and written electrically without interference between adjacent cells or excessive cross talk, and that they can be combined with logic within each cell to operate as a content-addressable memory.

IV. HETEROSTRUCTURE DRAM CELLS A . Introduction

Heterostructure DRAM cells have been investigated by several groups. These cells can be classified into two types: (i) generation-limited cells, similar to the pn junction JFET and MESFET DRAM cells already discussed, in which the nonequilibrium state is a deficit of carriers and the cell returns to equilibrium by thermal generation, and (ii) leakage-limited cells, in which the nonequilibrium state is an excess of carriers and the cell returns to equilibrium by leakage of excess carriers over a potential barrier. As we shall see, the generation-limited DRAM designs have been more successful, since generation is characterized by activation energies of at least half the semiconductor band-gap. To create a comparable leakage-limited memory would require a heterojunction band discontinuity of comparable magnitude. Such band discontinuities are difficult to achieve in 111-V material systems. In the following sections we shall first review the results obtained with leakage-limited devices (undoped heterojunction cells and quantum-well floating-gate cells). We will conclude with a discussion of generation-limited devices (modulation-doped heterojunction cells). B. Undoped Heterostructure DRAMS

A storage capacitor employing an undoped heterojunction (Cooper, Qian, and Melloch, 1986) is shown in Fig. 35(a). The barrier layer is undoped Al,Ga,-.As (x = 0.38), and excess electrons are confined in a two-dimensional electron gas (2DEG) in the GaAs adjacent to the heterojunction, as shown in part (b). Figure 36 shows C-V and I-V characteristics of the structure at 77 K in the dark and under white light (Kleine et al., 1989b). In the dark no measurable current flows, and the capacitance is that of an MOS structure in deep


45

FIGURE 35. A leakage-limited heterojunction storage capacitor formed by undoped AlGaAs on GaAs. A cross section of the structure is shown in (a) and the band diagram for the interface region is shown in (b). The top Al,Ga,-,As layer has a mole fraction x of 0.38, while the Al,Ga,_,As layers in the five-period superlattice have a mole fraction of 0.30. The superlattice buffer layer is included to improve material quality of the subsequently grown layers. Electrons in the 2DEG tend to escape. over the heterojunction to the GaAs gate. This leakage process limits the storage time of this capacitor.

46


-

I . r L , , , , I , , , ,

I

,

,

, ,

,,

, , ,

,

, , ,

,

,

, , , ,,

1n-‘

10-7

Gate Voltage [V]

FIGURE36. Capacitance- and current-voltage characteristics of the heterojunction storage capacitor of Fig. 35 at 77 K. The current and the upper capacitance curves were taken under white light illumination, and the lower capacitance curve was taken in the dark. The dark current was too small to be measured. The ledge in the light-on capacitance curve indicates that electrons 1989 IEEE). are being stored in the 2DEG (0

depletion - the capacitance decreases as voltage is swept positive due to the expanding depletion region in the p-type GaAs. Under illumination, photogeneration occurs in the depletion region. Holes are swept into the substrate, while electrons drift to the GaAs/AIGaAs interface, where they are trapped in the potential well. As voltage is swept positive under illumination, a capacitance ledge is observed. This ledge is caused by the screening effect of electrons in the 2DEG at the GaAs/AlGaAs interface. The leakage current also increases. This can be explained as follows: At any bias, a steady state exists between electrons supplied to the 2DEG by photogeneration and electrons escaping the 2DEG to the gate or to the substrate. In the ledge region, not all of the photogenerated electrons flow from the 2DEG to the gate. Some are injected to the substrate, where they recombine with holes, producing no current. As the gate voltage increases, field emission and thermionic field emission of electrons from the 2DEG to the gate increase, and an increasing fraction of photogenerated electrons flow to the gate. The capacitance remains almost constant for a range of gate voltages (the “ledge”) because additional charges added to the gate by the increasing gate voltage are imaged by additional electrons in the 2DEG; the depletion region is shielded from the additional charges and does not expand. Eventually, the 2DEG contains the maximum electron density that can be contained behind the finite potential barrier (AEc = 0.3eV). Beyond this point no more electrons can be added to the 2DEG, and the depletion region is no longer shielded from increases in the gate charge. As a result, the capacitance again


-1 .o

0.0

47

1.0

Voltage (Volts)

FIGURE37. Transient capacitance decay at several gate voltages at 55K.When light is extinguished, electrons in the 2DEG leak over the heterojunction barrier to the gate, and the capacitance decreases to the dark value. The lack of hysteresis in the C-V curves in depletion (V, < - 0.4V) proves that all the stored electrons have been expelled from the ZDEG, and none 1989 IEEE). are held in traps (0

decreases with gate voltage. The gate current saturates, since now essentially all of the photogenerated electrons are flowing from the 2DEG to the gate. The various processes by which electrons escape the 2DEG are illustrated in part (b) of Fig. 35. These include thermionic emission over the potential barrier to the gate, thermionic-field emission through the top of the barrier, tunneling from quantized energy levels at E, and E , , diffusion into the substrate, and black-body photoemission over the barrier to the gate (Kleine et al., 198913). The rate at which electrons escape determines the storage time. This escape rate can be determined from a capacitance-time (C-t) transient at any voltage in the capacitance ledge region. An example of a series of such C-t transients is shown in Fig. 37. By a careful analysis of the rate of change of capacitance during each transient, the leakage current can be determined as a function of electric field in the AlGaAs and the quasi-Fermi level splitting in the 2DEG. From these analyses it is possible to distinguish which of the several leakage mechanisms in Fig. 35(b) is dominant in each bias region and to determine relevant constants in the mathematical expressions for each leakage mechanism. We shall not go into such detail here; the interested reader is referred to the literature (Kleine et al., 1989b). The major conclusion to be drawn from the work on leakage-limited undoped heterostructure DRAM cells is that storage times are too short to be useful except at cryogenic temperatures. This is illustrated by Fig. 38, where electron density in the 2DEG is plotted as a function of time following extinction of the light (Kleine et al., 1989b). Symbols represent experimental data obtained from capacitance transients, and lines are theoretical predictions based on the known emission mechanisms. One observes that storage

48

I

10'

10'

102

Time [s]

FIGURE38. Stored electron density as a function of time at 50 and 80K. The points represent experimental data at several values of gate voltage, while the lines are predictions of the emission theory of Kleine et al. (1989b). Storage times are on the order of a few seconds at 80 K (0 1989 IEEE).

times of around 1000 seconds are obtained at 50K. However, at 80K the storage times have dropped to the order of a few seconds. Measurements at higher temperatures are not practical due to the short time constant of the C-t transient. Figure 39 shows the heterojunction barriers in the GaAs/AlGaAs system as a function of AlAs mole fraction (Batey and Wright, 1986). The largest conduction band discontinuity, about 0.35 eV, occurs around x = 0.4, where the AlGaAs bandgap becomes indirect. This is very close to the mole fraction of the samples presented in Figs. 35-38. However the valence band discon0.6 0.5

0.4

I5 '0

w" U

0.3 0.2 0.1

0 0.0

0.2

0.4

0.6

0.8

1.0

AlAs Mole Fraction

FIGURE39. Conduction and valence band discontinuities in the AlGaAs ternary system as a function of AlAs mole fraction. The largest discontinuity in the conduction band occurs around x = 0.4,where the AlGaAs becomes indirect. In the valence band, however, the discontinuity increases monotonically as x approaches unity.


49

0

I

Barrier

Potential Well

AuZn

-

f

N GaAs 1 ~ 1 0 cm3 '~

\

3 N+ GaAs Substrate

FIGURE 40. A heterojunctioncapacitor for storing holes at the interface between undoped AlAs and n-type GaAs. The valence band discontinuity at this interface is about 0.55 eV.

tinuity increases monotonically, reaching a maximum value of about 0.55 eV at x = 1. Perhaps an advantage can be gained by storing holes in a twodimensional gas at the GaAs/AlAs interface! Figure 40 shows a heterostructure storage capacitor formed by undoped AlAs and n-type GaAs. This capacitor was also studied by the method of C-t transients (Qian, Melloch, and Cooper, 1986, 1989), and the results for a gate voltage of - 3 V are shown in Fig. 41. Here we see that storage times of tens of seconds are obtained at 100 K, and measurable charge storage persists to almost 200 K. Again, however, room temperature operation is not feasible. In addition to questions of storage time, we must also consider the charge storage density of heterojunction DRAM cells. The hole memory capacitor of Fig. 41 can retain about 8 x 10" holes per cm2at 150 K, while the electron capacitor of Fig. 38 retains only about 1 x 10" electrons per cm2at 80 K. In order to store lo6 carriers, the hole capacitor would need to be at least 1 1 x 11pm2, while the electron capacitor would need to be at least 32 x 32 pm2. In Section I1 we found that pnp homojunction capacitors could be made as small as 5 x 5pmZ. C. Quantum- Well Floating-Gate DRAMS

Two groups have investigated charge storage in quantum wells formed by heterojunctions. The first such structure was reported by Capasso and co-workers (Capasso et al., 1988; Beltram et al., 1988), and is shown in Fig. 42. In this structure a GaAs quantum well, formed between two AlAs barriers, serves as a floating gate for an underlying field-effect transistor. Electrons are injected into the quantum well from the gate by a negative pulse. This injection is aided by grading the band-gap of the barrier layer between the gate and the quantum well. Once stored, the electrons cause a positive shift in the threshold voltage of the underlying transistor. This

50


90 K

vg = -3.0 v

10

.---.

3

N

I

b!

E

L

rl

0

4

x

5

h

Y

v

a

..

A

0

lo-'

I

10"

I

10'

I

102

lo3

t [sec]

FIGURE 41. Hole density in the capacitor of Fig. 40 as a function of time at several temperatures. Hole densities in the low 10" cm-' range can be retained for several seconds at temperatures up to 190K, but room temperature operation is not feasible.

threshold shift can be detected by observing the current in the transistor, providing a form of nondestructive readout. In the GaAs/AlAs version, the room temperature storage time was about 2 sec, increasing to about 4 hr at 77 K. Figure 43 shows drain current transients at 140 K and at room temperature following filling pulses from the gate. From measurements of effective threshold voltage shift, a sheet charge density of about 10l2cm-2 was inferred for the quantum well. A similar structure was investigated by Lott, Klein, and Weaver (1989b). This structure differed from the structure of Fig. 42 in that a variable-period superlattice was used to produce the graded-band-gap effect in the injector region. Storage times of around 1 sec were reported at room temperature, with sheet charge densities above 10''cm-2. The latter workers have also reported similar devices using InAs (wells)/ AlAsSb (barriers) on InAs substrates (Lott et al., 1989a), and using InGaAs (wells)/InAlAs (barriers) on InP substrates (Lott et al., 1990). The InAs/ AlAsSb structures exhibited a l / e storage time of only 50 sec at 77 K. Storage time data was not reported at higher temperatures. The InGaAs/InAlAs devices had storage times of around lOsec at 200K, decreasing to less than 1 s at 250 K. In the latter devices, the dominant mechanism of charge loss was


N+Gah 500nm

graded undoped

"raped

AlGaAs 180 nm

1

200 nm

U AlAs 100

nm

51

N SI GaAs OeAS 75 Substrate nm

Equlllbrlum

Du~Ing WRITE phase

FIGURE 42. A floating-gate DRAM cell in which electrons are stored in a GaAs quantum well between two AlAs barrier regions. Electrons are injected from the top gate over a compositionally graded AlGaAs barrier. The presence of electrons on the floating gate modulates the 1988 IEEE). current in the GaAs channel below, providing nondestructive readout (0

identified as horizontal leakage over a lateral potential barrier, rather than vertical emission over the heterojunction discontinuity. The quantum-well DRAM structures described previously are qualitatively similar to the single-heterojunction storage capacitors discussed in Section 1V.B. In both cases electrons are retained behind the potential barrier created by the conduction band discontinuity at a heterojunction. The storage time is determined by the rate at which electrons are emitted over the heterojunction. In comparing the storage times reported for these two types of structures, a striking difference in storage time is apparent: The capacitors of Section IV.B, which were based on the heterojunction between GaAs and Al,Ga,_,As

52


-a -E

2 c5-)/-vw

atp= loops

Atp=1 ms

(z

(b)

3

za

4T=300K

a

n

3

I

I

9

5-

T= 140K

-

I WRITE

4-

0

WRITE

ERASE (SHORT LIGHT PULSE)

2

4 TIME

6

(c)

8

10

(5)

FIGURE 43. Channel current in the floating-gate DRAM of Fig. 42 as a function of time at (a) 140K and (b) room temperature. The current transients have time constants of 4 hours at 140 K and 2 seconds at room temperature. Part (c) illustrates the write-erase operation at 140 K (erase is accomplished by shining light on the sample) (01988 IEEE).

(x = 0.38), had measurable storage times only below 100 K. In contrast, the quantum-well capacitors of Section C, based on the heterojunction between GaAs and AlAs, had storage times of 1-2 sec at room temperature and 4 hr at 140K. What can account for such a dramatic difference? One possible explanation is that the GaAs/AlAs and InAs/AlAsSb systems are heterojunctions between direct band-gap and indirect band-gap semiconductors. Thus, electrons residing in the r valley in the quantum well must be emitted into the X valley in the barrier. The thermionic emission rate of


53

electrons over a potential barrier decreases exponentially with the barrier height. However, Solomon, Wright, and Lanza (1986) have argued that when the heterojunction is indirect, the prefactor before the exponential term is diminished, owing to reflections caused by wave function mismatch. A similar argument applies to thermionic-field emission (tunneling). Solomon et af. (1986) have calculated these prefactors from measurements of dc current through n+ in- n+ structures, where the i layers were undoped Al,Ga, -,As (0.3 < x < 0.8) and the doped layers were GaAs. They conclude that the prefactor for thermionic emission decreases by about a factor of 200 at x = 0.8 as compared to the value when x < 0.4. For thermionic-field emission, the prefactor decreases by about a factor of 2500 at x = 0.8. However, Kleine, Melloch, and Cooper (1989a) have pointed out that these decreases are insufficient to explain the reported room temperature storage times of the quantum-well storage capacitors. Kleine et al. measured the transient decay of electron density at the heterojunction between GaAs and Al,Ga,-,As at 55K for mole fractions of 0.4, 0.6, 0.8, and 1. The optimum mole fraction for electron storage at this temperature was found to be between 0.4 and 0.6, and the storage time decreased markedly as the mole fraction approached unity (Kleine et al., 1989a). Moreover, they showed that the storage time of a GaAs/AlAs barrier at room temperature, based on the parameters of Solomon et al., would be less than 1psec. Another possible explanation for the long storage times reported for quantum-well capacitors is charge trapping (Kleine et af., 1989a). It is not possible to determine from capacitance or threshold voltage transients whether the stored charges are mobile or confined in deep traps in the material. Certainly, if charges were confined in traps, the storage times would be much greater than predicted by thermionic emission or thermionic field emission theories. If charge trapping were taking place, the cell would also be highly resistant to electrical erasure, and could not function effectively as a random-access (read-write) memory. Indeed, the floating-gate cells of Capasso et al. (1988) and Beltram et af. (1988) could not be electrically erased, and instead were erased with light. Moreover, evidence of charge trapping in the AlAs was specifically mentioned by the groups investigating GaAs/AlAs quantum-well capacitors (Capasso et al., 1988; Beltram et al., 1988; Lott et al., 1989b). In the single-heterojunction results reported in Section B and in the emission study of Kleine et al. (1989a), charge trapping could be ruled out by the fact that no hysteresis was observed when C-V curves were swept rapidly in both directions (electrical removal of stored electrons). To summarize this rather confusing section, quantum-well storage capacitors have exhibited storage times up to 1-2 sec at room temperature, although some controversy exists regarding the explanation for the storage

54


I

2DEG

P+ GaAs

....................

I

N AlGaAs

P GaAs P+ GaAs Substrate

FIGURE44. Cross-section and band diagram of a modulation-doped heterostructure storage capacitor. Because of the band banding in the AlGaAs layer, the Fermi level at the interface lies above the conduction band in the GaAs. As a result, a 2DEG will be present at the GaAs/AlGaAs interface in equilibrium.

phenomenon. The issue is made moot, to some extent, by the results obtained with simple pn junction storage capacitors in Section I1 and the results to be reported in the next section. D . Modulation-Doped Heterostructure DRAMS

A heterostructure capacitor employing modulation doping is illustrated in Fig. 44. This type of structure has a distinct advantage over both the undoped heterostructure capacitors considered in Section B and the quantum-well capacitors discussed in the last section. This is because the modulation-doped structure of Fig. 44 is generation limited, in the sense that it retains a two-dimensional electron gas as the equilibrium state. The non equilibrium


55

Access

P+ substrate

L--

Storage Capacitor

, Word Ly,

FIGURE45. Cross section of a MODFET DRAM cell. This cell consists of a rnodulationdoped heterostructure capacitor and a MODFET access transistor.

state is achieved by removing electrons, and the structure returns to equilibrium by thermal generation, just as the pn homojunction capacitors of Section 11. Thus one expects storage times in modulation-doped heterostructure capacitors to be comparable to those in p n homojunction capacitors. Figure 45 illustrates a complete one-transistor DRAM cell using a modulation-doped heterostructure (Kleine, Cooper, and Melloch, 1991). A p + GaAs layer is used as the gate of the access transistor and the top electrode of the storage capacitor. This p + layer has a higher barrier to the AlGaAs than a metallic gate, thus reducing gate leakage current in the access transistor (Priddy et al., 1987). The AlGaAs layers have an AlAs mole fraction x = 0.3. The storage capacitor is 187 x 190pmZ,while the access transistor has a gate length of 5Spm and width of 54pm. Storage times of an isolated modulation-doped storage capacitor and a complete DRAM cell are shown as a function of temperature in Fig. 46. As was the case with JFET and MESFET DRAM cells, addition of the access transistor reduces storage times by several orders of magnitude. This is due to gate leakage current flowing when the transistor is biased off. At room

56

JAMES A. COOPER, JR. Temperature ("C) 105f,'

144 .

,

111 '

'

60

84 '

'

'

39 ,.

21 ,

1OOO/T (1/K)

FIGURE46. Storage times of an isolated modulation-doped storage capacitor and a complete MODFET DRAM cell as a function of temperature. The isolated capacitor has a storage time of 4.3 hr at room temperature. The storage time of the complete cell is reduced to about 2 min at room temperature because of leakage currents in the MODFET access transistor.

temperature, the storage time of an isolated modulation-doped storage capacitor is about 4.3 hr. In the complete DRAM cell, gate leakage in the access transistor reduces the storage time to about 2min at room temperature. The storage capacitor exhibits two activation energies, indicating two independent generation processes are occurring. The fact that both of these activation energies are greater than half-band-gap suggests generation through centers some distance from the middle of the band-gap. The results shown in Fig. 46 were obtained on cells that had thermally evaporated metal. The use of electron-beam metallization reduces the storage time of isolated capacitors to around 15min at room temperature. This is consistent with the results reported for pn junction storage capacitors in Section II.D.4. Figure 47 illustrates electrical writing of the MODFET DRAM cell. The charge state of the storage capacitor is monitored by measuring the capacitance between the storage gate and the substrate. A gate bias of - 2.9 V was applied to the access transistor during storage, and the gate was pulsed to 0 to write information into the cell. The arrows indicate the points where the MODFET access transistor was momentarily pulsed on. Write pulses as short as 20nsec were effective in writing the cell. Shorter pulses were not investigated due to equipment limitations. It can be seen that for this particular device the room temperature l/e capacitance recovery time is about 3 min. The bit line waveforms during reading are shown in Fig. 48. Here the potential of the bit line is monitored by a high-impedance FET probe. The 2DEG in the storage capacitor is first partially removed by pulsing the

RECENT ADVANCES IN GaAs DYNAMIC MEMORIES 11

0.5

10

0.4

9

0.3

a 0 8 c m c

0.2

E: a v

-k 0

-

’ 0

.-O

7

0.1

Q

6

0.0

al

=-

m

B -

8

57

C

2

-0.1

5 4

-0.2 0

200

100

300

500

400

600

Time (s)

FIGURE 47. Writing waveforms for the MODFET DRAM cell of Fig. 45. Note that the cell capacitance changes only at the instants when write pulses are applied to the word line (indicated by arrows). The storage time of this cell can be estimated from the capacitance transient to be about 3 min at room temperature.

storage gate to a negative bias for sufficient time for the electrons to recombine with substrate holes. The pulse voltage magnitude is indicated on the figure. Note that for the largest pulse voltage shown here (- 1.5V), the 2DEG is still not totally removed, since the threshold voltage for this device is - 2.08 V. The access transistor is turned on at t = 0, which is 50 msec after the end of the emptying pulse. For r > 0, charge sharing occurs between the storage capacitor and the combined capacitance of the bit line and FET probe, resulting in a voltage output proportional to the charge required to refill the storage capacitor. The decay of the output signal for r > 0 is due primarily to the conductance of the FET probe. 0.5

E

-.-m

,

,

I

,

,

,

,

,

,

,

,

,

,

,

,

. , ,

,

,

,

,

300 K

0.4

E: 0.3 al w

tc

0.2

.=

0.1

0

.4 m

0 -10

0

20 Time (ps)

10

30

40

FIGURE48. Bit line waveforms during reading of the MODFET DRAM of Fig. 45 as a function of the write pulse voltage used to empty the storage capacitor. The access transistor is turned on at time t = 0, which occurs 50msec after a I is written to the cell. The storage capacitor contains a partial 2DEG even for the - 1.5 V case, since the threshold voltage for total removal of the 2DEG is - 2.08 V.

58


output

Memory Cel I S

F1

MODFET F3

F2

s

F4

D

500 nm undoped AlGaAa

-

950 nm p AlGaAs

-

360 nm p GaAs

seml-InsulatingG a b substrate

FIGURE49. A modulation-doped heterostructure DRAM cell reported by Chen et al. Electrons are stored in the 2DEG under gate F2, while gates F1 and F3 are used for isolation. The transistor formed by gate F4 is used to buffer the output. During testing, gate F3 was left on permanently. In an actual DRAM, transistors FI and F3 would be replaced by a single MODFET (reprinted with permission of Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts).

A similar modulation-doped heterostructure DRAM cell has been reported by Chen, Goodhue, and Mahoney (1991). This cell, shown in Fig. 49, utilizes a 20 nm undoped GaAs quantum-well channel grown on a fourperiod AlGaAs/GaAs superlattice buffer layer. An undoped AlGaAs layer and a p + AlGaAs barrier are placed under the superlattice to prevent electron emission to the semiinsulating substrate, and a modulation-doped barrier is grown on top of the GaAs channel. All AlGaAs layers have mole fraction x = 0.23. The primary storage gate is labeled F2, and two separate transistors, labeled Fl and F3, are used for writing and reading the cell. An output MODFET, F4, is also included to amplify the signal resulting from charge transfer when F3 is turned on. In functionality demonstrations, however, Chen et al. kept F3 biased on to avoid capacitive coupling between the read pulse and the cell and placed a 1 MQ resistor in series with the gate of F2 to minimize coupling of the write pulse applied to F1. The circuit of Fig. 49 has a storage time of only 250msec at room temperature, probably due to leakage through transistor F3, which is always left on. However, large-area isolated storage capacitors exhibit storage times as long as 5.4sec at room temperature and up to 40 sec at 77 K. The charge storage density is 4.5 x 10" electrons per cm'.


59

V. BIPOLARDRAMs A . Introduction

In Section I1 we found that the storage time ofpn junction storage capacitors is limited by thermal generation of hole-electron pairs. This process is slow in higher band-gap materials such as GaAs, and well-made storage capacitors can have storage times of several hours at room temperature. In Sections I11 and IV we learned that the addition of a field-effect access transistor (either JFET, MESFET, or MODFET) reduced the overall storage time of the complete cell to the order of 0.1-100sec. This drastic reduction in storage time is due to unavoidable gate leakage when the access transistor is in the off state. We note that silicon DRAM cells avoid this problem because MOS transistors have essentially no gate leakage. The most straightforward way to eliminate gate leakage in the access transistor is to eliminate the gate! This can be done if, instead of a field-effect access transistor, we employ a bipolar access transistor. We should point out that bipolar DRAM cells are really not new, since DRAMs based on integrated injection logic were introduced in silicon in the early 1970s (Sander and Early, 1976; Quinn et al., 1978). These cells worked well, but they offered no particular operational advantage over MOS DRAM cells, since MOS cells in silicon are not limited by gate leakage. However, in GaAs the advantage over FET-accessed cells is enormous. In this section we will discuss the operation of a bipolar DRAM cell in GaAs. B. Concept of the Bipolar DRAM Cell A bipolar DRAM cell in GaAs (Stellwag, Cooper, and Melloch, 1991, 1992) is illustrated schematically in Fig. 50. This cell can be recognized as the basic pnp storage capacitor of Fig. 4 with an additional n-type layer on top. This n-type layer, together with the p - and n-type layers immediately beneath it, form an npn bipolar transistor. This bipolar transistor is merged with the pnp storage capacitor, as indicated in the figure. The base of the bipolar transistor is connected to the word line and the emitter to the bit line. The collector is floating and forms a p n junction with the substrate. The capacitance of this latter pn junction, together with the capacitance of the base-collector junction, stores the charge. Operation of the bipolar DRAM cell is illustrated in Fig. 51. In equilibrium, the n-type collector is at ground potential, corresponding to a stored logic 0 (part a). A logic 1 is written by removing electrons from the collector. This is done by taking both bit line and word line positive, thereby forward

60

JAMES A. COOPER. JR

Bit Line NPN Bipolar Access Transistor

Word Line

t ...........

%

.......

P GaAs N GaAs

Floating Collector

PNP

Storage Capacitor

P+ GaAs substrate

*

FIGURE50. Cross section of a bipolar DRAM cell in GaAs. An npn bipolar transistor is merged with a pnp storage capacitor to form the cell. Alternatively, the cell may be viewed as an npn bipolar transistor with a floating collector, with the collector specially constructed to have a large capacitance to ground.

biasing the collector-base junction (part b). Electrons will flow from the collector to the emitter until the collector-base voltage has been reduced to 0. The collector is now at the potential of the word line. If both bit line and word line are returned to ground, part (c), the collector remains positively charged due to the loss of electrons. The structure is now storing a logic 1. Note that all potentials applied to the cell are now at ground. As a result, the only currents that will discharge the collector are those due to generation in the depletion regions of the two reverse biased junctions. This is the same situation as the pnp storage capacitors of Section 11, where storage times of several hours were obtained at room temperature. Also, note that, since storage takes place with all terminals at ground potential, no power is dissipated in the storage state. Indeed, the memory can be considered nonvolatile, in the sense that all external power can be removed without loss of stored data, at least for times short compared to the normal storage time of the cell. The cell can be written to a logic 0 state by keeping the bit line at ground and taking the word line slightly positive, as shown in part (d). Electrons then flow from the emitter to the collector until the collector-toemitter voltage is 0. In examining the sequence of band diagrams in Fig. 5 1, we note a conflict. To empty the cell, the word line and bit line are taken several volts positive. To fill the cell, however, the bit line is kept at ground and the word line is taken only slightly positive. Since we have no way of knowing whether the bit line will be positive or at ground during a particular writing operation, how can we know to what potential to take the word line? The answer is that the writing operation must be a two-step procedure: First all cells in a word

RECENT ADVANCES IN GaAs DYNAMIC MEMORIES Substrate

61

Floating coiiector

%?* \....

0

.

(a)

Store Zero (Equilibrlurn)

0

....

(b) Read -or-

Write One

0

0

0

(c) Store One

FIGURE 51. Band diagrams illustrating the operation of the bipolar DRAM of Fig. 50. Data consists of the presence or absence of electrons in the floating collector. Electrons are removed by taking both the word line and bit line positive, as shown in part (b). Data is stored when both the word line and bit line are at ground potential, as in parts (a) and (c). Electrons are inserted by taking the word line slightly positive while the bit line is held at ground, part (d).

must be emptied (word line and all bit lines taken several volts positive), then the cells must be selectively refilled, based on the bias state of their particular bit lines (word line taken only slightly positive). From the schematic drawing in Fig. 50, two other advantages of the bipolar cell can be seen. First, the cell conserves area, since the access transistor is vertically integrated on top of the storage capacitor. Second, the cell is inherently fast, since charge transport during reading and writing is vertical rather than horizontal. This latter point deserves further explanation. In FET-accessed cells such as shown in Fig. 21, charge transport occurs laterally along the FET channel. During reading and writing, the storage capacitor in these structures functions essentially as a long-channel FET, and the channel can pinch off, limiting current flow. This pinch-off effect is avoided in the bipolar structure.

62


The bipolar DRAM of Fig. 50 can also be realized as a heterojunction bipolar transistor, or HBT. In the HBT the emitter is formed from AlGaAs, and the base and collector from GaAs. HBTs are widely used in GaAs bipolar circuits because the valence band offset at the emitter-base junction drastically reduces hole injection from the base into the emitter, improving the emitter injection efficiency. This improvement is so great that it is no longer necessary to keep the base doping lower than the emitter doping. The increase in base doping has the added advantage of reducing the base spreading resistance. To apply these ideas to the bipolar DRAM cell, we must consider the requirements on the bipolar access transistor. As illustrated in Fig. 51, the operation of the bipolar DRAM dictates that the access transistor operate in both the forward and inverse modes. When electrons are removed from the floating collector (Fig. 51(b)), the transistor is in the inverse mode, with the collector functioning as an emitter and the emitter functioning as a collector. If we construct the cell using HBT technology, it will be desirable to fabricate both the collector and emitter in AlGaAs to enhance both forward and inverse operations. Therefore, we envision a double-heterojunction bipolar transistor in which the n-type emitter and n-type collector are both AIGaAs. The presence of a heterojunction in the reverse-biased collector-base junction would have minimal effect on forward operation. A further extension would be to make all layers (except the base) AlGaAs, since this would reduce generation in the depletion region of the collectorsubstrate junction. C . Experimental Results A prototype homojunction bipolar DRAM cell is shown in cross section in Fig. 52. This cell was grown by MBE, and metalized using a thermal evaporator (Stellwag et al., 1991a, 1992b). The storage time of the cell is measured by observing the transient recovery of the base capacitance following writing a logic 1. The capacitance transient of a 36 x 48 ,urn2cell at room temperature is shown in Fig. 53. The l/e recovery time is 16,200 sec, or 4 . 5 hr. This storage time is of the same magnitude as storage times of isolated pnp capacitors reported in Section 11, indicating that the presence of the bipolar access transistor has no negative effects on storage time. Figure 54 shows storage time as a function of temperature for several bipolar DRAM cells. An activation energy of 0.88 eV is common to all cells, and larger cells have slightly longer storage times, consistent with the scaling arguments presented in Section II.D.3. The cell is electrically written in Fig. 55. The 3 V, 1 msec word line pulses are not shown, but occur at the points indicated by arrows. Note that the capacitance increases when the bit line is at ground (store 0 state), since this

63


p+ GaAs I I

1x10 19cm-3

Access Transistor

100 nm

I GaAs

30 nm 5x10 "cni3

p+ GaAs

I I

200 nm

1x10 '9cmi3 1000 nm

p+ GaAs Substrate

FIGURE 52. Cross section of the experimental device used to verify the operation of the 1992 IEEE). bipolar DRAM (0

returns the cell to equilibrium. When the bit line is positive (store I state), the capacitance decreases. This is because electrons have been removed from the floating collector, widening the depletion regions. The capacitance transient in the store 0 state is due to the turn-off time of the forward-biased emitterbase junction, as excess carriers are removed by recombination. This transient has no effect on operation of the memory. We should emphasize that in the high-capacitance store 0 state, the cell is actually in equilibrium, Time (hours) 0

2

4

6

1.10

G'

e 8c

1

105

-

.

,

0

10

mj. I '

.

-

m

0

10,000

20,000

30,000

40,000

Time (sec) FIGURE 53 Capacitance recovery transient measured at the base contact of the bipolar DRAM cell of Fig 52 at room temperature A recovery time constant of 4 5 hr is observed (01992 IEEE)

64

JAMES A. COOPER, JR. Temperature ( "C ) 144

111

84

60

40

21

1

105

2.4

2.6

2.8

3.0

1000 / T (1/

3.2

3.4

K)

FIGURE54. Storage time as a function of temperature for several bipolar DRAM cells. All cells have an activation energy of about 0.88 eV. Storage time decreases slightly as the cell is 1992 scaled to smaller dimensions, as expected from the scaling discussion in Section I1 (0 IEEE).

and no further decay of capacitance will occur. The nonequilibrium condition actually corresponds to the low-capacitance store 1 state. Thus, the capacitance in the store 1 state will gradually rise (with a time constant of 4.5 hr at room temperature). No such rise is perceptible on the short time scale of this figure.

VI. FUTURE DIRECTIONS A . Introduction

In the five previous sections we have described experimental work that has led to the present state of the art in GaAs one-transistor DRAM cells. Over the past years, storage times in GaAs capacitors have increased dramatically - from about 3 min at room temperature in 1987 to over lOhr in 1991, and the trend seems likely to continue. Moreover, the use of bipolar access transistors, as described in Section V, makes it possible to construct complete DRAM cells having storage times on the same order of magnitude as the capacitors alone. The charge storage density of p n junction capacitors in GaAs is comparable to that achieved in planar storage capacitors in silicon. What next? What directions should GaAs DRAM development take from this point? What applications can be identified that would lead to commercialization of these devices? We will address some of these questions in this final section.


65

-

L

c m

Equilibrium Capacitance

I

---

m

c)

Store 0

0

8 0

Store 1

m

iL------1

0

200

400

600

800

1000

Time (sec)

FIGURE 55. Electrical writing of the bipolar DRAM cell. For this test, the charge state of the cell is monitored by observing the base capacitance. To write the cell, 3 V, 1msec write pulses are applied to the word line at the times indicated by arrows. The capacitance decay in the store 0 state is due to the turn-off transient of the forward-biased emitter-base junction, and it has no effect on operation. The store-0 state is in fact the equilibrium condition and will never decay. The low-capacitance store 1 state is the nonequilibrium condition. This capacitance will gradually increase with a time constant of 4.5 hr at room temperature. This increase is imperceptible on the time scale of this plot (0 1992 IEEE).

B. Trench Capacitors and Stacked Capacitors in GaAs One of the dramatic developments in the evolution of silicon DRAMs was the introduction of vertical structures to increase the effective charge storage density (Sunami, 1985; Lu, 1989; Sunouchi et al., 1990). These vertical structures take the form of trench capacitors and stacked capacitors, as illustrated in Fig. 56. A large number of variations on these basic ideas have been proposed, but we will not attempt to review them here. The main point is that vertical structures have become absolutely necessary in silicon DRAMs at the integration levels prevalent today. On first glance it would appear that GaAs would be unable to emulate these vertical structures, and so would be totally unable to compete for high-density DRAM applications. However, that may not be the case at all. In this section, we will describe early efforts to develop a trench capacitor

66

JAMES A. COOPER, JR. Bit Line

Word

Line

Plate Voltage

SIO,

P Silicon

Trench Capacitor Cell

Plate Voltage Bit Line

Word Line

P Silicon

P Stacked Capacitor Cell

FIGURE56. Two types of vertical-geometry DRAM cells in silicon. The trench capacitor cell conserves area by placing the storage capacitor on the sidewalls of a vertical trench. The trench aspect ratio can be as high as 30: 1. The stacked capacitor cell utilizes a multilayer sandwich of insulating and conducting layers formed on top of the semiconductor surface.

technology in GaAs. We will also speculate on the use of stacked capacitors in conjunction with GaAs DRAM cells. Trench capacitors and complete trench DRAM cells can be grown in GaAs using a technique known as atomic layer epitaxy (ALE) (Bedair et al., 1985). ALE is a gas-phase epitaxial growth technique similar to metal-organic chemical vapor deposition (MOCVD) except that special precautions are taken to expose the growth surface to only one species of adatom at a time. Epitaxy is carried out in a temperature range where growth is self-limiting, so that a single monolayer of either Ga or As is formed during one cycle. The growth surface is alternately exposed to ambients containing Ga and As source gases, resulting in layer-by-layer growth. This leads to unprecedented control of the growing film on an atomic level. One very useful property of this growth technique is the ability to grow high-quality layers conformally on vertical sidewalls of etched trenches. This property is exploited to build trench DRAMS in GaAs. Figure 57 is a scanning electron micrograph of four 100 x 100pm’ mesaisolated GaAs p n diodes grown by ALE over a substrate in which several square 2pm deep trenches were etched prior to growth (Neudeck et al.,


67

FIGURE 57. SEM photograph of four 100 x 1oOpm2mesa-isolated pn diodes grown by ALE conformally over a substrate in which 2 pm deep trenches were etched prior to growth. Two of the mesas have a single 30 x 30pm2trench each, one mesa has nine 10 x 10pm2trenches. and one is planar (no trenches). The planar mesa is at the upper right. The light-colored square regon near the center of this device is the metal ohmic contact. An SEM cross section of one of the trenches is shown at the bottom.

68

JAMES A. COOPER, JR. Area = 100 x 100 pm

-1

0

-0.5

0.5

Voltage (V)

FIGURE58. Current-voltage characteristics at 1 4 4 O C for three ALE-grown pn diodes (symbols) with and without trenches. The nine-trench diode has 360pm of trench sidewall, while the one-trench diode has 120pm of trench sidewall. The line represents one of the best MBEgrown planar diodes.

1991b). Three types of diodes are shown: the diode on the upper right has no trenches (planar diode), the diodes on the upper left and the lower right each have one 30 x 30pm’ trench, and the diode on the lower left has nine 10 x 10pm2 trenches. The surface morphology is smooth, and conformal growth of epitaxial layers over the trench sidewalls is observed. Figure 58 shows the current-voltage characteristics of these three types of structures at 144OC. Also shown for comparison is one of the best planar diodes grown by MBE. Both forward and reverse currents are larger for the diodes containing trenches, but the reverse characteristics are not significantly degraded. Figure 59 shows the dependence of reverse current on trench perimeter for the three structures at a reverse voltage of 1V. Note that the one-trench and the nine-trench diodes each have the same trench area and same total diode area,

0

100

200

300

400

Trench Perimeter (pm)

FIGURE59. Leakage current at 144°C and 1 V reverse bias for the three ALE diodes of Fig. 5 8 . The reverse leakage increases linearly with trench perimeter.


69

but the trench perimeter differs by a factor of three. From this plot it is apparent that the reverse leakage scales with trench perimeter. It is not possible to determine from this measurement whether the leakage is due to the sidewalls themselves or to generation at the edges where the vertical sidewalls meet the horizontal top and bottom surfaces. This question can be resolved by a study of the dependence of leakage current on trench depth. Measurements of leakage current as a function of temperature indicate that the leakage is thermally activated. The planar diodes have an activation energy of 0.713 eV while both the trenched samples have an activation energy of 0.844 eV. These samples were metalized by electron-beam evaporation. Further work is needed to determine the dependence of leakage current on trench depth and sidewall orientation. In addition, both pnp storage capacitors and bipolar DRAM cells need to be built using this technique, and storage times need to be measured as a function of trench depth and orientation. Preliminary evidence based on the diode leakage measurements suggests that the degradation of storage time caused by the trenches would be within acceptable limits. The advantages of increased charge storage in the same amount of horizontal chip area would probably far outweigh the negative effects on storage time, particularly when storage times of planar devices are now measured in terms of hours at room temperature. Another approach to achieve higher charge storage densities with nonplanar capacitor structures is the use of stacked capacitors, similar to those illustrated in Fig. 56. In silicon DRAMS these stacked capacitors are formed by alternating layers of polysilicon conductors and SiO, insulators fabricated by a complex and ingenious sequence of deposition and selective etching. There is no fundamental reason why these steps cannot be performed on GaAs substrates. In effect, we are proposing that the storage capacitor need not be integral to the GaAs substrate, but could simply be deposited on the top surface after all the GaAs active devices are fabricated. This would open the possibility for a number of different structures, including metaloxide-metal capacitors, stacked capacitors such as shown in Fig. 56, and capacitors having a ferroelectric material as dielectric. C . Nondestructive Readout Cells

Another direction that shows great promise are GaAs DRAM cells that provide nondestructive readout with internal gain. Two types of structures are known to be under investigation (Cooper, 1989; Hetherington, Klein, and Weaver, 1991). One such structure, the bipolar/field-effect (BiFET) cell (Cooper, 1989), is shown in Fig. 60. Here the basic bipolar cell of Section V has been modified by the addition of a second base contact. This second contact allows the base layer to function as the channel of a lateral JFET,

70

JAMES A. COOPER, JR Gate / Emitter Source / Base

P I 30 nm undoped

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-

Y

Drain / Base

P

N GaAs P+ GaAs

I

N+ GaAs

l

FIGURE 60. A proposed bipolar-field-effect (BiFET) DRAM cell. The cell operates as a bipolar storage cell as described in Section V. Once a potential is stored on the floating collector, the depletion region of the collector-base junction modulates the lateral conductivity of the base layer. By establishing two ohmic contacts to the base, it is possible to detect the charge state of the floating collector by measuring the current between the two base contacts. In effect, the base forms a lateral JFET, gated from above by the emitter and from below by the floating collector.

gated from the top by the emitter and from the bottom by the floating collector. As a result, the current in the JFET is controlled by the potential of the floating collector, providing nondestructive readout. Because the cell now has gain, a robust signal can be placed on the bit lines during readout. Data is written to the cell in the conventional way using the bipolar access transistor (see Section V). The additional requirements on the base layer place new constraints on the design of the cell. In particular, the base layer thickness and doping must be adjusted to allow significant modulation by the floating collector. This must be accomplished without sacrificing the operation of the bipolar access transistor, both in the forward and inverse modes. Work is proceeding on these design issues, but no insurmountable problems are foreseen. The design problem is made more tractable by the several degrees of freedom inherent in the structure. Adjustable parameters include the base doping and thickness, the logic voltages on the floating collector, and the bias voltage on the emitter during readout. In addition, the use of heterojunctions at the emitter-base and collector-base junctions would improve bipolar operation, further relaxing the design constraints. In addition to providing nondestructive readout for digital (binary) memories, the BiFET cell can also be used as an analog memory. This mode of operation opens the possibility for several new applications, one of which is in the field of artificial neural networks. This will be discussed in Section


71

D. Ultra-Long Storage Times: Quasi-Static and Nonvolatile DRAMs As pointed out in the introduction to this section, storage times in GaAs memories have increased dramatically in recent years. In simple GaAs bipolar DRAM cells, storage times in excess of 4 hr at room temperature are now routinely obtained. For many applications such as cache memory, in which paging occurs at predictable intervals, storage times of this magnitude allow the cell to be operated essentially as a static memory, without the need for refreshing of any kind. Moreover, the bipolar DRAM has the unique feature that storage is accomplished with no external bias applied to the cell. This is because the bipolar access transistor is a current-controlled device and is off when the base current is 0. Thus, bipolar DRAMs can be used in applications where data is to be retained during temporary power losses, provided such interruptions are short compared to the normal storage time of the memory. In this mode, the memory is considered “nonvolatile,” at least for limited periods of time. What if the storage time could be extended to the order of days, months, or even years? In a moment, we will show experimental evidence that such storage times may indeed be possible. But first, we should point out the potential advantages that this type of nonvolatile memory would have in comparison to nonvolatile memories available today. In present-day nonvolatile memories in silicon, a charge is injected onto a floating gate by tunneling through a thin tunnel oxide or by avalanche injection over the potential barrier of a thicker oxide (Kahng and Sze, 1967; Frohman-Bentchkowsky, 1974; Nishi and Iizuka, 1981). Storage times are measured in years, but writing operation is quite slow, typically on the order of 100psec per bit, and writing requires pulse voltages much larger than the normal 5 V supply voltage. Therefore, operation is effectively restricted to read-only memory (ROM) applications, and the devices are variously referred to as programmable ROMs (PROMS), electrically alterable ROMs (EA-XOMs or E-PROMS), or “flash” E-PROMS. The bipolar DRAM, on the other hand, achieves nonvolatile storage from its inherently long charge recovery time and does not depend on tunneling or avalanche injection across an oxide barrier. As a result, electrical writing is expected to be very fast, typically on the order of nanoseconds or less per bit, and operation as a high-speed read-write memory is not compromised. Silicon E-PROMS also suffer from a wearout mechanism that limits the number of times the memory can be reprogrammed to around 106-107times. Although this is not a limitation when the memory is used as a ROM, it does preclude use of these devices in RAM applications, where lo6 writing operations can occur in a few seconds of real time. The bipolar DRAM suffers from no comparable wearout mechanism.

72

JAMES A. COOPER, JR

As stated earlier, storage times on the order of months to years may be possible using the basic bipolar DRAM structure of Section V, provided a suitable semiconductor material is utilized. One particularly attractive material for such applications is silicon carbide (Sic) (Davis et al., 1988). This is because S i c has a band-gap almost three times as large as silicon and twice as large as GaAs. S i c occurs in both cubic and hexagonal forms. Cubic (“beta”) S i c has a lattice constant of 4.359A and a band-gap of 2.3eV. Hexagonal (“alpha”) S i c occurs in a variety of polytypes, each having a hexagonal basal plane but with different stacking sequences in the vertical direction. The most useful polytype is “6H,” with a band-gap of 2.9 eV. Both beta and 6H material have been used to fabricate electronic devices (Kong et al., 1987; Palmour et al., 1991), including MESFETs, JFETs, MOSFETs, and bipolar transistors. 6H-Sic wafers are available commercially from Cree Research, Inc., Durham, NC, and are now grown at a number of research laboratories in the United States, Europe, Japan, and the states constituting the former Soviet Union. S i c is physically robust, being one of the hardest and most chemically inert materials known to humankind. It is thermally stable, and electronic devices retain good electrical characteristics to very high temperatures. MOSFET operation has been demonstrated (Palmour, Kong, and Davis, 1987) to 65OoC, and packaged devices operate reliably for extended periods at temperatures up to 35OoC, limited by the thermal stability of the package. Therefore, a major application for S i c is high-temperature and high-power electronic devices. For further information on S i c crystal growth, fabrication techniques, and electrical properties, the reader is referred to the literature. In order to evaluate S i c for use in long-term dynamic memory applications, we have investigated the storage time of npn storage capacitors in 6H-Sic (Gardner et al., 1991). A cross section of the experimental device is shown in Fig. 61. All layers are doped in situ during epitaxy. Circular npn diodes are isolated by reactive ion etching and passivated with S O z formed by wet thermal oxidation. Ohmic contacts are annealed Ni. Capacitance recovery times are measured on various devices using the techniques described in Section 11. Referring to equations (33) and (34) of Section 11, we are reminded that the recovery time of a pn junction storage capacitor is expected to increase exponentially with band-gap energy as exp (EG/2kT), assuming that generation lifetimes in the materials are comparable. Since the band-gap energy of 6H-Sic is 1.48eV greater than the band-gap of GaAs, one expects the storage time at room temperature to be larger by a factor of exp(28.6) or approximately 12 orders of magnitude. Alternatively, we expect to observe the same storage time as GaAs at an absolute temperature that is higher by the ratio of the band-gaps, or approximately a factor of 2. This means that S i c devices should exhibit


73

Ni Ohmic Contact

30 nm undoped

-

N 6H Sic Substrate (Siface)

FIGURE 61. Prototype n-i-p-i-nstorage capacitor fabricated in 6H-Sic for storage time measurements. The etched surfaces are passivated by thermal SiO, grown by wet oxidation.

storage times at 600 K (3OOOC) that are comparable to those of GaAs at room temperature. Figure 62 shows storage time versus temperature for several Sic diodes (Cooper et al., 1991). As predicted, storage times on the order of 10 min are observed at 300°C. All diodes have an activation energy around 1.48 eV, close to half the band-gap. If we extrapolate these data to room temperature, we would predict a storage time of about loi3sec, or about 300,000 years! Of course, such an extrapolation is not realistic - other mechanisms having lower activation

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FIGURE62. Recovery time versus temperature for storage capacitors fabricated in GaAs and in 6H-Sic. The activation energy of the Sic capacitors is about 1.48 eV, close to half the band-gap. Data on the S i c samples had to be taken above 300°C because at lower temperatures the storage times are too long to be conveniently measured.

74


energies (or not thermally activated at all) will become dominant before room temperature is reached. The point, however, is that thermal generation is not likely to limit storage times in these devices. How long will room temperature storage times be? That question is difficult to answer with any confidence, since it will require actual room temperature measurements over extended periods of time. Such measurements have not yet been attempted. To summarize, we have shown the possibility of one-transistor memories having exceedingly long storage times at room temperature. For practical purposes, such memories can be regarded as static. In addition, since the bipolar cell requires no external bias to retain data, these memories are also nonvolatile. Because they can be written in nanoseconds, these devices can be used in high-speed RAM applications. E. Nonconventional Applications

TOconclude this chapter, we wish to suggest some nonconventional applications for these compact storage devices. Dynamic memory is usually associated with digital electronics. However, the applications we will describe in this section use the fact that the dynamic memory is inherently an analog device. The basic elements of the dynamic memory cell, storage capacitors and access transistors, are utilized in a number of analog applications such as switched capacitor filters. In addition, the basic capacitor structure, which has been optimized for exceedingly low dark current, is ideal for use in low-light-level imagers. Perhaps the most novel application, one that has arisen only in the last few years, is in the emerging field of electronic neural networks. We will describe this particular application next. Artificial neural networks are electronic circuits that embody many of the features of biological neural systems (Hopfield, 1988; Lippmann, 1987). In particular, they are highly interconnected networks composed of a large number of very simple identical elements. The basic elements of neural networks are neurons and synapses. In electronic neural networks, neurons are simple amplifiers having saturating (or sigmoidlike) input-output characteristics. The input to each neuron is a summing node connected to a large number of surrounding neurons by resistive connections called synapses. An example of a simple electronic neural network is shown in Fig. 63. Here the network consists of a row of amplifiers (neurons) whose outputs are brought around to a matrix of resistive connections (synapses). The synapse matrix forms the interconnections between neurons. One simple way to visualize the operation of a neural network is to define an energy function for the network. This energy function depends on the output voltages of the neurons in the array. If there are n neurons, the energy function is defined on an n-dimensional space. The exact dependence of the


I

75

I

FIGURE63. Illustration of a simple Hopfield neural network. The network consists of a row of amplifiers (neurons) whose outputs are brought around to a matrix of resistive connections (synapses). The synapse matrix forms the interconnections between neurons. Programming is accomplished by specifying the strengths of the resistive connections in the synapse matrix.

network energy on the individual neuron voltages is determined by the resistive weights of the synapse elements in the interconnection matrix. Thus, the information content of the network, in effect its programming, is contained in the resistive weights of the synapse connections. One use of such a neural network is in pattern recognition. Suppose that an input pattern (which could be an optical image, a fragment of speech, a radar signature, etc.) is to be classified based on a number of predetermined “example” patterns, To be specific, let us assume that the network is to identify a two-dimensional image as belonging to one of 26 possible classes: the letters of the alphabet. The weights in the synapse matrix of the neural network are selected so that the energy function of the network exhibits local minima. Each local minimum corresponds to one of the “example” patterns that are acceptable answers to the identification problem. The inputs to the neurons are then preset to potentials that correspond to the input image to be identified. This, in effect, places the network in an initial condition at some point in the n-dimensional parameter space corresponding to the input pattern. The network is then allowed to settle into the local energy minimum that is “nearest” the starting point. This minimum corresponds to one of the 26 possible “answers” - the 26 letters of the alphabet. In this way, the network performs a natural minimization function, determining which “example” pattern is the minimum distance from the input pattern.

76

JAMES A. COOPER, JR

The question of how to specify the weights in the synapse matrix so that the local minima in the energy function are efficiently placed is a subject of current research. However, for our purposes it suffices to understand that the network is “programmed” by specifying these synapse weights. To perform a meaningful pattern recognition task, the electronic neural network must be of sufficient size. In particular, the number of local minima in the energy function grows approximately as the square root of the number of neurons. Unfortunately, the number of synapse connections grows as the square of the number of neurons. It is easy to see that simply identifying the letters of the alphabet would require perhaps a few thousand neurons and a few million synapses. How does all this relate to dynamic memories? In Section C , we described a combination bipolar-field-effect (BiFET) cell capable of nondestructive readout of stored information. We now suggest that this BiFET cell can be used to implement a very compact synapse connection for electronic neural networks. As discussed earlier, the potential on the floating collector in this device serves to back-gate the channel of the lateral JFET formed by the base layer. Thus, the conductance of this lateral JFET can be programmed to an analog value by storing the proper voltage on the floating collector. The JFET is then used to provide the desired resistive connection required of the synapse element. An illustration of the use of the BiFET cell in a synapse array is shown in Fig. 64. We assume that the weighting information is stored off-line in a conventional semiconductor memory. This weighting information is then loaded into the BiFET array using the data lines shown. Once initialized, the BiFET array is ready to provide weighted synapse connections for the neural network. Since it is important that the analog voltage in each cell does not change appreciably, the array will need to be refreshed in a time that is much shorter than the l/e storage times previously quoted for our DRAM cells. However, considering the long room-temperature storage times of GaAs bipolar cells (not to mention the storage times of S ic cells), such periodic refreshing should not be a significant problem, particularly since the normal settling time of the neural network is on the order of a few microseconds. The use of dynamic storage for the synapse weights allows the network to be reprogrammed on-the-fly to solve different classification problems, in effect becoming a general-purpose neural computer. In conclusion, we have pointed out a number of nonconventional applications for dynamic storage devices. The ultra-long storage times now being realized make possible a number of novel applications, as diverse as nonvolatile digital memory and high-density neural networks. The evolution of nonsilicon dynamic memory devices has been rapid, and a number of exciting directions are opening for future development.


-

I,

11

l2

77

12

FIGURE 64. Realization of a Hopfield network using the BiFET storage cell of Fig. 60 as a programmable analog synapse element. Synapse weights are entered using the horizontal “data” lines.

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ADVANCES IN ELECTRONICS A N D ELECTRON PHYSICS. VOL. 86

Expert Systems for Image Processing. Analysis. and Recognition: Declarative Knowledge Representation for Computer Vision TAKASHI MATSUYAMA Department o$ Information Technology. Faculty of Engineering. Okayama University. Okayama. Japan

I . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A . Declarative Knowledge Representation . . . . . . . . . . . . . . . . . B. Knowledge Representation in Computer Vision . . . . . . . . . . . . . C. Organization of the Chapter . . . . . . . . . . . . . . . . . . . . . . I1. Expert Systems for Image Processing and Analysis (ESIPAs) . . . . . . . . . A . Problems in Image Processing and Analysis . . . . . . . . . . . . . . . B. Characteristics of ESIPAs . . . . . . . . . . . . . . . . . . . . . . . C . General Architecture of ESIPAs . . . . . . . . . . . . . . . . . . . . D . Consultation System for Image Processing . . . . . . . . . . . . . . . . E . Knowledge-Based Program Composition System . . . . . . . . . . . . . F. Rule-Based Design System for Bottom-up Image Segmentation Algorithms . G . Goal-Directed Top-down Image Segmentation System. . . . . . . . . . . I11. Representing Knowledge about Image Analysis Strategies . . . . . . . . . . A . Heterogeneous Combination of Image Processing Operators . . . . . . . . B. Cooperative Integration of Multiple Stereo Vision Algorithms . . . . . . . IV. Representing Spatial Relations and Spatial Reasoning for Image Understanding A . Knowledge Representation in Logic Based on Topological Relations . . . . B. Structural Representation of Geometric Relations . . . . . . . . . . . . C . Algebraic Representation of Geometric Information and Geometric Theorem Proving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D . Reasoning Based on PART-OF Relations . . . . . . . . . . . . . . . . V. Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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I . INTRODUCTION A . Declarative Knowledge Representation

Expert systems are computer software systems capable of intelligent problem solving. which usually requires sophisticated knowledge of human experts. In the 1980s expert systems in various task domains were developed and their practical utilities have been widely recognized: medical diagnosis. chemical 81

Copyright 0 1993 by Academic Press. Inc. All rights of reproduction in any form reserved. ISBN 0-12-0 14728-9

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substance analysis, geological investigation, computer system configuration, and so on. Generally speaking, any meaningful computer software or program can be considered as an embodiment of human knowledge; it is designed and implemented using knowledge in a specific task domain. In other words, without knowledge no useful software or program can be realized. For example, the following function in C programming language is a realization of the mathematical knowledge about absolute values of integer numbers:

absolute (n) int n;

c if (n)=o) return (n); else return (-n);

1 The most distinguishing characteristic of expert systems is the use of declarative knowledge. That is, knowledge in expert systems is explicitly represented as symbolic data, independent of the control of problem solving, while that in ordinary programs is implicitly encoded in and spread over various types of program statements. The knowledge represented by procedures like the preceeding absolute function is called procedural knowledge. A FORTRAN or C program for the fast Fourier transform (FFT) is a typical example of procedural knowledge. Although the program embodies the knowledge about FFT (i.e., when executed, it transforms an input data correctly based on the knowledge), the knowledge is implicitly encoded in the sequence of primitive operations like assignment and IF-THEN-ELSE control statements. Thus it is almost impossible to identify (and separate) the knowledge itself in (from) the program code. On the other hand, formulae in the first-order predicate calculus like Vx[MAN(x) + MORTAL(x)] [For all x,M A N ( x ) implies MORTAL(x). MAN and MORTAL are predicates and x a variable.] and so-called production rules like I F (condition for activation) THEN (action) (If the condition is satisfied, execute the action.) are typical examples of declarative knowledge, where knowledge is explicitly described in terms of symbols in a predefined vocabularly. Note that declara-

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tive knowledge does not include any control information about how and in which order it is used. Thus we can freely design the control structure of reasoning and problem solving independent of the knowledge. Moreover, flexible modification and augmentation of knowledge can be easily realized by symbol manipulations, since the embodiment of knowledge is just a collection of well-formed symbolic data. The clear separation of knowledge from control leads to the natural decomposition of an expert system into knowledge base and reasoning engine.' The knowledge base is a collection of symbolic data representing knowledge and the reasoning engine is a control program that conducts reasoning based on the knowledge base. Merits and demerits of the declarative knowledge representation can be summarized as follows: Merit 1 : High Modularity and Easy Modijication. The declarative knowledge representation enables highly modular description of knowledge; knowledge is represented by a set of mutually independent descriptions (e.g., rules and axioms). Thus knowledge can be added, deleted, and modified easily by editing related portions of symbolic data in the knowledge base, while even a small change in procedural knowledge can lead to extensive modification of an entire program. Merit 2: High Transportability and Knowledge Sharing. Once knowledge in a specific task domain is described declaratively, it can be used in or transported to other expert systems even if it is not originally intended to be used in such systems. In other words, declarative knowledge can be shared by different expert systems. Merit 3: High-Level Reasoning. New knowledge can be automatically generated by reasoning and learning mechanisms since the addition of knowledge can be easily realized by inserting new symbolic descriptions into the knowledge base. Moreover, meta knowledge about how to use knowledge in a task domain can also be described declaratively to realize flexible control of reasoning processes. Merit 4: Introspective Explanation. Since the reasoning engine can memorize which knowledge is used in a specific reasoning process, it can present to a user an introspective explanation of the executed reasoning process. Demerit 1 : Limited Descriptive Vocabulary. Knowledge used in expert systems is often called shallow knowledge; declarative knowledge used in them is described in terms of naive qualitative vocabularies. Such naive descriptions limit the level of reasoning and analysis. Demerit 2: Low Eficiency. Declarative knowledge should be interpreted to be

'

Although the term inference engine is more popular than reasoning engine, we reserve inference for that in the formal mathematical logic and use reasoning in a general context.

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used in a reasoning process, so that many complicated symbolic processings (e.g., symbolic pattern matching) are inevitable. This lowers execution speed considerably. In short, it is the essence of the declarative knowledge representation that knowledge itself is described as independent objective data to be processed. With the declarative knowledge representation, we can gain much flexibility and versatility despite loose efficiency. The problem described in Demerit 1 is a crucial point in developing an expert system in a specific task domain. That is, how well we can symbolically describe the knowledge in that task domain determines the performance and utility of the developed expert system. On the other hand, Demerit 2 can be resolved by compiling the knowledge base. That is, although during the development we should use the declarative knowledge representation for its modifiability, we can encode the knowledge into procedures for efficiency once the entire set of knowledge required for problem solving is fixed. B. Knowledge Representation in Computer Vision

In general computer vision’ refers to visual information processing by computer. It includes image processing, analysis, and recognition. Image processing denotes transformation of an input image to another. Filtering operations like smoothing and edge enhancement are its typical examples. On the other hand, image analysis refers to image segmentation to extract meaningful image features such as lines and regions.’ In image processing, analysis, and recognition and modern computer vision for three-dimensional object recognition, most of the knowledge has been described procedurally. Reasons for this are as follows: 1. Digital filtering is a fundamental scientific discipline of image processing, and photometry and geometry in the three-dimensional world provide major knowledge sources for three-dimensional computer vision. All these scientific disciplines have been established based on quantitative analysis of physical phenomena, where mathematical formulae such as differential equations are used as general representational schemes. Thus it is natural to use numerical computation procedures as the embodiment of such physical knowledge.

’

Computer vision sometimes refers specifically to three-dimensional information analysis and object recognition from two-dimensional images. When necessary, we will refer to it explicitly as three-dimensional computer vision or computer vision for three-dimensional object recognition. In this chapter we will sometimes use image processing in a general sense, including both filtering and feature extraction.

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2. For human beings, the identification of various visual properties - i.e., brightness, color, size, and shape - is so natural and immediate that no conscious thought or logical reasoning is required for their characterization. Consequently, only limited descriptive vocabularies for such visual properties have been developed and few efforts for their declarative description have been made until quite recently. 3. In ordinary statistical pattern recognition, patterns and objects to be analyzed are represented by n-dimensional vectors. This also leads to the development of numerical computation procedures in realizing the knowledge about various recognition methods. 4. Since the size of image data is large and its processing should often be done quickly in practical applications, the speed of execution has been an important factor to design computer systems for image processing, analysis, and recognition. Thus the efficiency of the procedural knowledge representation has been preferred to the flexibility of the declarative knowledge representation. Several years ago, Rosenfeld (1986) proposed the term expert vision systems to denote computer vision systems using declarative knowledge and had open discussions with several computer vision researchers on possibilities and utilities of the declarative knowledge representation for computer vision. Unfortunately, the discussions were not developed extensively, nor did they produce any creative concrete ideas at that time. Since then, however, many research efforts have been put to prove the feasibilities of expert vision systems. Especially in Japan, we organized a special interest group on expert vision and have developed various types of expert systems for image processing and analysis. On the other hand, several formal approaches to the declarative knowledge representation for computer vision were proposed to clarify the knowledge and reasoning mechanism required for image recognition and understanding. Moreover, a major focus of recent multimedia communication and database research is on the integration of textual, verbal, and visual information; and many methods for declarative characterization of visual information have been proposed for multimedia information processing. From an engineering point of view, since the speed and memory space of computers increased dramatically in the past few years and this increase is expected to continue, system designers for practical applications gradually shifted their attention from efficiency to the flexibility and versatility of implemented systems. Therefore we believe that by exploring the declarative knowledge representation for computer vision new scientific findings and technological

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successes will be obtained and many new-featured vision systems can be developed.

C. Organization of the Chapter In this chapter we will describe various approaches to the declarative representation of visual information and knowledge for image processing, analysis, and recognition. We will not survey or discuss that for multimedia information processing. First Section I1 gives an extensive survey of expert systems for image processing and analysis. They use the knowledge about image processing techniques to compose complex image analysis processes from primitive image processing operators. We classify the expert systems into the following four categories and discuss their objectives, knowledge representation, and reasoning methods: 1. Consultation system for image processing, 2 . Knowledge-based program composition system, 3. Rule-based design system for bottom-up image segmentation algorithms, 4. Goal-directed top-down image segmentation system. In order to realize flexible and reliable image analysis, ordinary sequential reasoning mechanisms such as backward-forward chaining in expert systems and linear resolution in PROLOG are not enough. In Section I11 we discuss the following sophisticated strategies (i.e., control mechanisms) for image analysis with practical examples: 1. Heterogeneous combinations of image processing operators. 2 . Cooperative integration of multiple stereo vision algorithms. The success of the declarative knowledge representation for computer vision rests wholy on how well we can symbolically describe various types of visual properties. In Section IV we first discuss the declarative representation of spatial relations for image recognition and understanding. During the discussion, we introduce two formal declarative knowledge representation methods for computer vision: 1. Knowledge representation in terms of the first-order predicate calculus, 2 . Algebraic knowledge representation and geometric theorem proving.

Then we describe expert vision systems for recognizing complex objects with internal structures; that is, reasoning based on PART-OF relations.

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In Section V, we conclude the article by discussing future problems of the declarative knowledge representation for computer vision.4

FOR IMAGE PROCESSING AND ANALYSIS (ESIPAs) 11. EXPERTSYSTEMS

A . Problems in Image Processing and Analysis

A variety of image processing algorithms have been devised in the history of digital image processing. Although they do not work perfectly for complex natural images, their utilities have been proven in various application areas such as remote sensing, medical engineering, office and factory automation, and so on. In order to facilitate a wider use of digital image processing techniques, various software packages have been developed: FORTRAN subroutine libraries (Tamura e f al., 1983) and command libraries in image processing systems. As is well known, however, it is not so easy to make full use of such libraries; various forms of knowledge and know-how about image processing techniques are required to realize effective image analysis. In other words, the requirement for such knowledge limits utilities of the libraries and increases the cost of developing image processing systems for various applications. From a knowledge representation viewpoint, each subroutine or command in a library is a procedural embodiment of the knowledge about a primitive image processing operator, and the library is a simple collection of such procedural knowledge. Although the procedural knowledge representation for primitive image-processing operators is natural and effective, no systematic description about syntactic and semantic relations among subroutines and commands is supported in ordinary libraries. This makes it difficult for their users, especially those with little knowledge of and experience in image processing, to compose effective image analysis processes5 by selecting and combining primitive operators in the libraries. Note that even to read manuals of the libraries requires knowledge about image processing, for example, meanings of specialized terminology in image processing. Thus what we mean by knowledge and know-how about image processing techniques includes syntactic and semantic relations among subroutines and commands in image processing operator libraries. To investigate the knowledge about image processing techniques further, first we should examine popular problems encountered in designing image An earlier version of Sections I1 and 1II.A was published in Matsuyama (1989). By an image unalysisprocess we mean an executableprogram composed of various combinations of primitive operators. Types of combinations will be discussed in Section I11 in detail.

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analysis processes by using an image processing operator library. The following are typical problems in development image analysis processes: 1. Assessment of Image Quality. To assess the quality of an image is the first step in image analysis. Although one should design an image analysis process based on the assessment, how to measure and describe the image quality is a difficult problem. In the analysis of complex natural images, moreover, we encounter a more difficult problem; since the image quality often changes depending on its location in an image, we need to analyze the image and determine its structure to make the image quality assessment. This leads to a chicken-and-egg problem between image quality assessment and image structure analysis. When physical models of objects and imaging devices are available, we can assess the image quality based on such models. 2 . Selection of Appropriate Operators. There are many different operators (algorithms) for a specific image processing task. For edge detection, for example, several tens or more of operators have been developed. They are designed based on different image models and computation schemes, so that one has to select an appropriate operator considering the image quality, the purpose of image analysis, and characteristics of the operators. 3. Determination of Optimal Parameters. Many operators have adjustable parameters and their performance is heavily dependent on the values of the parameters (e.g., threshold in binarization). How to determine optimal parameter values is another difficult problem. 4. Combination of Primitive Operators. It is often necessary to combine many primitive operators to perform a meaningful task. For example, a popular way of extracting regions from an image is to apply smoothing edge detection +-edge linking sclosed boundary detection. To attain an effective combination of operators, the knowledge about syntactic and semantic relations between operators is required. 5. Trial-and-Error Experiments. Usually it is very hard to estimate a priori the performance of an operator for a given image, so that one has to repeat trial-and-error experiments by modifying parameters (and sometimes operators). To control such trial-and-error analysis, sophisticated knowledge about and rich experience in image processing are required. 6. Evaluation of Analysis Result. The process of evaluation is very important in realizing flexible image analysis. For example, the feedback analysis (Nagao, 1984) evaluates the difference between a processing result and the ideal output (i.e., the model of an object) and adjusts parameters for the analysis. How to evaluate the analysis result


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and how to adjust parameters based on the evaluation is an important problem in designing image analysis processes with feedback loops. Vogt (1986) pointed out 10 major problems in developing image analysis programs, which are almost the same as the preceding, and analyzed their causes extensively. Among others he claimed that many intuitive, ad hoc, nonsystematic, and sometimes ambiguous factors are involved in the image analysis program development and that well-defined formal systems like mathematical morphology are required to facilitate the development. From the knowledge representation viewpoint discussed in Section I, his claim can be put as follows. When we develop a complex image analysis process, we usually write a main program that calls many primitive operators (subroutines) in a library. Such main program is really a procedural embodiment of the knowledge to solve the problems listed earlier. However, since this procedural knowledge is not systematically designed, no one, not even the programmer who wrote the main program, can understand clearly what knowledge is incorporated and how some portions of the program are related to others. Even worse, meaningless and incorrect knowledge can sneak into the program because there is no way of verifying the correctness of the procedural knowledge except by reading the program intensively. Due to these problems, it is very hard to improve an image analysis (main) program and modify it for other applications. This increases the time and cost of the image analysis program development. In other words, the procedural knowledge representation is efficient once correctly implemented, but its development and verification processes are far from efficient and usually require much time, cost, and moreover human expertise because no mechanical development and proof system is available. In short, while the procedural knowledge representation is useful for primitive image processing operators, its use in developing complex image analysis processes causes many problems. Therefore, we should study the declarative knowledge representation to examine its practical utilities in the development of complex image analysis processes.

B. Characteristics of ESIPAs Recently, several expert systems for image processing and analysis (ESIPAs, in short) were developed to facilitate the development of image analysis processes. They incorporated declarative knowledge representation and symbolic reasoning methods in artificial intelligence to solve the problems discussed in the previous section. The knowledge used by these systems is about how to effectively use and combine primitive image processing operators for image analysis. That is, the expertise stored in the systems is

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what we, computer vision researchers, have acquired and accumulated through the development of image analysis techniques. Before proceeding to technical discussions of ESIPAs we will discuss general characteristics of ESIPAs by comparing them to ordinary expert systems and image understanding systems. Expert systems have been developed for various tasks: signal interpretation, medical diagnosis, circuit design and trouble shooting, plant control, and so on (Hayes-Roth, Waterman, and Lenat, 1983). In general, the task of ESIPAs is to compose effective image analysis processes based on primitive image processing operators. In this sense, ESIPAs can be considered as expert design systems. The most successful system of this type would be R1 /XCON (McDermott, 1980b), which configures computer systems suitable for customer’s requirements by combining available functional components. The critical differences between ESIPAs and such expert design systems are 1. Although we can symbolically describe characteristics and behaviors of electronic circuits and computer hardware in terms of logical and mathematical expressions, it is very hard to describe the visual information included in an image and specify characteristics of image processing operators. 2. Since ESIPAs are given the input information in the form of raw image data (signal data), they have to analyze it to extract meaningful information and verify the effectiveness of composed image analysis processes.

Difference 1 implies that a major objective of developing ESIPAs is to investigate methods of formulating and describing the visual information in a declarative way: what types of image features we can extract from images, what properties they have, and how they are related to each other. Difference 2 means that ESIPA is not only an expert design system for symbolic reasoning but also an image analysis system for signal processing. Therefore, ESIPAs should have capabilities of both qualitative symbolic reasoning and quantitative signal processing. The integration of both qualitative (symbolic) and quantitative (numeric) information processing is also an important problem in image understanding and multimedia information processing. A primary objective of image understanding systems (IUSs in short) is to construct the symbolic description of the scene depicted in an image, while image processing transforms an image to another and pattern recognition classifies and labels objects represented by feature vectors. IUSs analyze an image(s) to interpret the scene in terms of object models given to IUSs as the knowledge about the world. Here interpretation refers to the correspondence


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(i.e., mapping) between the description of the scene and the structure of the image. It associates objects in the scene (e.g., houses, roads) with image features in the image (e.g., points, lines, regions). Once the description of the scene is constructed, computer systems can answer various queries about the scene (e.g., how many houses exist in the scene?), perform physical operations by controlling robot manipulators (e.g., pick up and move physical objects), and if needed, generate explanations of the scene in natural languages. It is in this sense that we can say IUSs understand the scene. IUSs require diverse sources of knowledge to interpret visual scenes. In general, the knowledge they use can be classified into the following three types: 1. Scene Domain Knowledge. This type of knowledge includes intrinsic properties of and mutual relations between objects in the world. It is described in terms of the terminology defined in the scene: names of scene objects and their constituent parts, geometric coordinate systems to specify locations and spatial relations, physical scale systems to measure various size properties (e.g., length in meters) and so on. 2. Image Domain Knowledge. This type of knowledge is used to extract image features from an image and to group them to construct the structural description of the image. It is described in terms of the terminology defined in the image domain. This terminology must not be confused with that for describing the scene. For example, a word adjacent in the scene domain knowledge must be clearly discriminated from that in the image domain knowledge; adjacent image features need not correspond to adjacent objects in the scene. 3. Knowledge About the Mapping Between the Scene and the Image. This type of knowledge is used to transform image features to scene features and vice versa. It defines translation rules between the two terminologies used to describe the scene and the image domain knowledge. The knowledge about photogeometry is a typical knowledge source for the translation rules: viewing angle and focal length of a camera, color spectral properties, resolution, and so on. Although IUSs often use the declarative knowledge representation as ESIPAs, there are several differences between these two systems: Objective: A major purpose of ESIPAs is to realize effective image analysis processes by combining primitive image processing operators in a program library, while that of IUSs is to interpret a scene. In other words, ESIPAs are developed to make full use of available image processing techniques, while IUSs to realize new versatile visual recognition capability. Knowledge Sources: The knowledge used by ESIPAs is about how to use image processing techniques as well as the image domain knowledge. That

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is, no knowledge about the scene is used in ESIPAs, while IUSs require all three types of knowledge listed previously. Goal Specification: “Find roads” is a typical goal given to IUSs. Since goals for IUSs are described in terms of the scene domain terminology, IUSs require models of objects in the scene and the knowledge about the mapping in order to establish correspondence between the object models and image features extracted from the image. On the other hand, “find rectangles” is a typical goal given to ESIPAs. Since there are many possible methods to extract rectangles from an image, ESIPAs require the knowledge about primitive image processing operators in order to select promising ones and know-how about image processing techniques so as to combine them effectively. As will be described in detail in the following subsections, we can develop ESIPAs for various different tasks. Among them, one view of ESIPAs is to consider them as image segmentation modules in IUSs. Most of IUSs so far developed emphasized the importance of the knowledge of types 1 (scene domain knowledge) and 3 (knowledge for mapping), and many reasoning and computational methods have been developed based on such knowledge (Ballard and Brown, 1982; Binford, 1982; Brooks, 1981). However, we also need a lot of knowledge to analyze image data. The knowledge of type 2 (i.e., image domain knowledge) has been usually encoded in programs, so that it is very hard to see what knowledge is used for the image analysis in IUSs. Moreover, fixed processes of image analysis (i.e., image analysis procedures) reduce the flexibility of image segmentation capability of IUSs. For example, the poor capability of the ribbon detection (i.e., image segmentation) in the ACRONYM image understanding system (Brooks, 1981) limits its overall performance in object recognition. Selfridge (1 982) incorporated the knowledge about image processing techniques to realize the adaptive operation and parameter selection in his aerial image understanding system. The appropriate image processing operator and its optimal parameters were automatically selected through several iterations of trial-and-error image segmentation. This allowed flexible image segmentation and increased the reliability. Although his idea is very similar to ESIPAs, the knowledge for the operator and parameter selection in his system was still represented procedurally, and consequently, its reasoning capability was limited. In ESIPAs we describe the image domain knowledge and the know-how about image processing techniques explicitly (i.e., declaratively) and make it clear what knowledge is important and how we can use it effectively. Replacing a group of image analysis programs in IUSs by ESIPAs, we can

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.

Library of Image

Request I Goal

Processing Operators

e r

Database of Characteristics of

n

imagedata specification

I

Image data

Analysis Result Reasoning Engine

composedprocess

a

knowledge about

C

Image Processing Techniques Knowledge about Knowledge about Image Processing Standard operators Image Analysis Processes

Selector

e -

increase the flexibility of image analysis in IUSs. Especially, the reliability of top-down image segmentation6can be greatly improved by incorporating an ESIPA as an image analysis module; since the model of a target image feature to be extracted and its approximate location are given in the top-down image segmentation, the ESIPA can accurately reason about the most reliable image segmentation tehnique (i.e., operators and parameters) using such information. C . General Architecture of ESIPAs

Figure 1 illustrates the general architecture of ESIPAs. It consists of the following modules: User Interface: A user of ESIPA interacts with the system through this

module. Its basic functions are to get a user’s request or analysis goal and image data to be analyzed and to return the analysis or reasoning result. Besides these primary functions, it supports various man-machine interface facilities such as displaying intermediate analysis results and reasoning histories graphically and sometimes asking the user for the evaluation of analysis results. Library of Image Processing Operators: This library is a major knowledge source of ESIPAs and contains a collection of procedures for primitive image processing operators, which can be called by the analysis executor. Note that the knowledge in this library is represented procedurally. Knowledge About Image Processing Techniques: This module is another major Later in this section we will discuss bottom-up and top-down image segmentation and describe ESIPAs for these two types of image segmentation.

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knowledge source of ESIPAs and includes various types of declarative knowledge about image processing: knowledge about standard image analysis processes, declarative characterization of individual image processing operators, rules for parameter selection, and so on. Database of Characteristics of Image Data: While the preceding two knowledge sources are usually built-in static information, this database stores all input and intermediate image data and their characteristics. They are dynamically created during the analysis and reasoning process. Analysis Executor: This module takes the full responsibility of executing image processing operators in the library and image analysis processes composed by the reasoning engine. All analysis results by this module are stored in the database for later use by the reasoning engine. Reasoning Engine: This is the central reasoning module in ESIPAs. It uses the knowledge about image processing techniques and characteristics of image data to reason about analysis plan generation, operator and parameter selection, and so on. Usually, reasoning in ESIPAs is done at two levels: 1. Analysis Plan Generation. First, ESIPAs reason about an appropriate

global plan to guide the analysis of a given image. The reasoning engine uses characteristics of the image and the knowledge about standard image analysis processes to generate the plan. The generated analysis plan can be considered as an abstract analysis process. 2 . Operator Selection and Parameter Adjustment. The reasoning at this level instantiates the generated analysis plan into an executable image analysis process: specific operators are selected from the library and values for their parameters are determined. These selections are done through the trial-and-error analysis of the input image: first ESIPAs perform image analysis by applying a promising operator and then evaluate the result to replace the operator or adjust parameter values. Here we classify ESIPAs into the following four categories: 1. Consultation system for image processing to improve user interface of image processing systems, 2. Knowledge-based program composition system to automatically generate complex image analysis programs, 3. Rule-based design system for image segmentation algorithms to realize flexible bottom-up image segmentation, 4. Goal-directed top-down image segmentation system for detecting specified image features. In the following subsections, we present an overview of these four types of


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ESIPAs and discuss their objectives, knowledge representation, and reasoning methods.

D . Consultation System for Image Processing

A user of an interactive image processing system is usually required to select a command from a command library and specify appropriate parameters for the command. Although several HELP facilities are available, one has to refer to a manual to see the detailed usage of commands and the meanings of their parameters. In other words, syntax and semantics of commands are described only verbally in the manual, which forces users to read and understand documents written in specialized terminologies in image processing. Moreover, the information about how to select an appropriate command from a group of commands with similar functions and how to combine different commands to realize a meaningful image analysis process is rarely described in the manual. These problems implicitly prevent inexperienced users from using the system and limit its utility. Expert consultation systems for image processing (Sueda and Hoshi, 1986; Toriu, Iwase, and Yoshida, 1987) use such manual information as their knowledge source and help a user to select an appropriate command and parameters and to combine primitive commands to realize meaningful image analysis processes. Since the command and parameter selection is done under the system guidance, the man-machine interface of the systems can be greatly improved. This facility is useful especially for those with little experience in image processing. In Sueda and Hoshi (1986) a prototype of such a consultation system, EXPLAIN, was proposed. Figure 2 shows the general flow of the consultation. First a user specifies the purpose of image processing in terms of predefined abstract functional specifications (e.g., image quality enhancement, image segmentation). Then he or she inputs an image to be processed and describes its rough characteristics (e.g., color or B&W, noise level, contrast) via a terminal. The system first reasons about a global processing plan based on both the given goal specification and the stored knowledge about standard image analysis processes. The plan is described as an ordered sequence of abstract image processing algorithms (functions) such as noise elimination, edge detection, thresholding, region segmentation, and so on. The knowledge about standard image analysis processes includes a set of such abstract plans and rules to select an appropriate plan satisfying the user’s request and suitable to the given image data. This knowledge is the embodiment of know-how about how to combine primitive image processing operators to

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Global Procassi

Evaluation of the Result

G All Procassing Finished?

No

FIGURE2 . General flow of consultation (from Sueda and Hoshi, 1986).

realize meaningful image analysis processes. Such knowledge rarely has been written explicitly in ordinary manuals. After selecting an appropriate global processing plan, the system instantiates each abstract algorithm in the selected plan one by one from the beginning (Figure 3): a promising practical command and its appropriate parameters are determined for each abstract algorithm. The instantiation is done through conversations on the detailed user’s objective and image quality guided by the knowledge about commands. The knowledge in this system is described by a set of production rules, which control the search process to find an appropriate command sequence. In Figure 3, for example, the global plan consists of two abstract algorithms:


I

F I OK

Evaluation

I

97

OK

pi55-l

FIGURE3. Search process for the instantiation of abstract algorithms (from Sueda and Hoshi, 1986).

and NOISE-ELIMINATION. At the first stage, rule 20 for the instantiation of BACKGROUND-ELIMINATION was applied but failed; a user did not satisfy the analysis result by the selected command. Then, the system activates an alternative rule, rule 21, for the same abstract algorithm, BACKGROUND-ELIMINATION. The following is an illustrative example of a rule for instantiating BACKGROUND-ELIMINATION: BACKGROUND-ELIMINATION

*rule 21*

FOR INPUT OUTPUT EFFECT IF

BACKGROUND-ELIMINATION BINARY- IMAGE LABELED-IMAGE the background region i s eliminated the size o f the background i s larger than

objects

THEN

execute LABELING and LARGE-REGION-ELIMINATION

When this rule is activated, it instantiates into an abstract algorithm sequence,

BACKGROUND-ELIMINATION LABELING

followed

by

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As the next step of reasoning, rule 81 for instanis activated but fails. And finally, rule 82 instantiates LABELING to generate an executable command. The selected command is applied to the input image, and the result is immediately displayed on the monitor screen. Then, the system asks the user for its evaluation. Depending on the user’s evaluation, the system replaces the operator or modifies parameters by activating other rules and retries the analysis. If the selected command successfully analyzes the image, the system proceeds to the instantiation of the next abstract algorithm in the plan. Note that even if the intermediate analysis result by the selected command is satisfactory, the selection is cancelled and another rule for instantiation is activated if the user does not satisfy the analysis result at some later stage. This backtracking capability realizes the trial-and-error analysis to select commands and adjust parameters. The system performs a large backtrack to try another global processing plan when no new command can be applied to satisfy the user. In addition to the knowledge about standard image analysis processes and commands, EXPLAIN contains rules describing the information about hardware and software architectures of the image processing system such as the number of image memories and special registers. This information is useful to hide specific architectural features of the system from the user and enables him or her to think about image processing at the logical level. LARGE-REGION-ELIMINATION.

tiating

LABELING

E. Knowledge-Based Program Composition System Currently, many software libraries for image processing are available. For example, SPIDER (Tamura et al., 1983) is a FORTRAN subroutine library for image processing containing over 300 subroutines, and many image processing systems are equipped with command libraries. Syntactic and semantic characteristics of program modules (subroutines and commands) in a library, such as data types of arguments of a subroutine, are usually written in a manual. Using such software characteristics of program modules as the knowledge source, we can develop an automatic programming system, which composes complex programs by combining program modules in the library. A user of the system has only to write an abstract program specification without knowing about details of program codes. Although we usually have to improve the composed program in its analysis capability and efficiency, expert systems of this type are useful to quickly develop image analysis programs for various applications. Automatic programming has long been a dream in software engineering and artificial intelligence (Barr and Feigenbaum, 1982), but no general-purpose practical system has been developed. However, if we confine ourselves to a


99

specific application domain, there may be a good possibility to realize usable systems; we can employ much domain specific knowledge and heuristics. One of the most critical problems in automatic programming is how to describe the program specification. ESIPAs proposed so far use the following specification methods: 1. Specification through conversation, 2. Specification by abstract command and language, 3. Specification by example. Although these specification methods themselves are not very new, there is a big difference between ordinary automatic programming systems and ESIPAs for program composition. That is, besides the symbolic reasoning engine, ESIPAs contain the analysis executor (see Figure l), which executes partially composed programs so as to verify their utilities during the program composition. This capability is necessary because (a) specifications given to ESIPAs are often informal and ambiguous, so that they have to repeat trial-and-error experiments; and (b) usually specifications given to ESIPAs describe only image features to be extracted. Therefore, in order to verify if composed programs are satisfactory, ESIPAs have to apply them to real images and to examine whether or not extracted image features satisfy the specifications. 1. Program Specification Through Conversation Those systems that obtain program specifications through conversation (Tamura et al., 1988; Sato, Kitamura, and Tamura, 1988; Bailey, 1988, Clement and Thonnat, 1989; Bunke and Grimm, 1990) are very similar to the consultation systems described in Section 1I.D. That is, the reasoning and conversation with a user are performed just in the same way as the consultation systems; and when the user is satisfied with the final analysis result, the system composes a program based on the analysis history stored in the system. Figure 4 illustrates a search tree representing the reasoning history. Each node in this tree represents a practical operator (subroutine) selected by the system during the reasoning process, and arcs between nodes specify orders of execution. In the figure some sequences of operators could not generate the satisfactory result, and the sequence illustrated by bold lines denotes a successful image analysis process. The system generates an executable program corresponding to the successful path in the tree. For this program generation, the knowledge about practical programming languages is required in addition to that about image processing techniques: declaration of variables and their types, syntactic forms for procedure or subroutine calls and argument specification and so on. Since the trial-and-error analysis is required to find appropriate operators

100

TAKASHI MATSUYAMA

n

Y

successful analysis process n

FAIL

FAIL

b

\

FAIL

0

:operator SUCCESS

FIGURE 4. Search tree representing the reasoning history.

and parameters, the flexibility of a system is heavily dependent on the modification process of an instantiated plan. EXPLAIN, described earlier, uses an ordinary tree search algorithm with backtracking to find alternatives. It should be noted that the tree in Figure 3 illustrates a history of the search and that the system instantiates abstract algorithms one by one in a sequential fashion. Such a sequential search prevents the system from reasoning about image analysis processes from a global viewpoint. DIA-Expert (Tamura et al., 1988; Sato et al., 1988) uses the operation tree to explicitly describe an image analysis process at various levels of abstraction (Figure 5(a)). The level of the operation tree means the level of abstraction. That is, vertical arcs in the tree represent abstraction and instantiation relations between image analysis algorithms. At each level a sequence of image analysis algorithms is described. In the figure, such sequence is shown as a group of rectangular nodes connected by dashed arrows. The sequence at the bottom of the tree represents the sequence of executable software modules in the program library, names of subroutines in SPIDER. In DIA-Expert all reasoning processes for the plan generation, instantiation, and modification are considered as symbolic manipulations of operation trees (Figure 5(b)). Besides rules for these reasoning processes, the system contains additional rules to avoid artifacts caused by image processing operators and to enhance effects of the operators. When these rules are activated, auxiliary nodes representing various pre- and postprocessing operations are added to the operation tree (see the right side of Figure S(b)). These rules are useful to improve the capability and robustness of composed image analysis programs.

101

IMAGE PROCESSING, ANALYSIS, AND RECOGNITION abstract algorithm abstract

binarization

noise elimination

-

single threshold

-

small reglon elimination

shape smoothing

-

shrink

expand

concrete executable command

order of execution

(a)An operation tree for segmentation.

iNSTANTlATE

L

I

small region elimination

I

I

AUGMENT

noise elimination

hole filling

FHL1

INSTANTiATE

small region elimination

- - - - _ _ - _ - ESAR

(b)Instantiationand augmentation of operation trees.

FIGURE5. Operation tree (from Tamura et al., 1988): (a) an operation tree for segmentation; (b) instantiation and augmentation of operation trees.

In short, the operation tree provides a uniform common data structure and enables the system to take a global view for program composition and modification. A similar tree representation of image analysis processes was used in Clement and Thonnat (1989). 2. Program SpecEfication by Abstract Command and Language

When we write a program for image processing, we have to write many codes

102

TAKASHI MATSUYAMA

besides those for essential processing: declaration and initialization of image data arrays, allocation of working memories, and so on. Especially, when we develop a complex image analysis program using a program module library, we want to devote ourselves to the function of each module without caring about such programming details. Expert systems that generate executable programs from abstract commands facilitate the development of complex image analysis programs. With such systems, we have to only specify combinations of modules in the library without knowing about their detailed syntactic and semantic structures. Sakaue and Tamura (1985) proposed an automatic program generation system using SPIDER. The system generates a complete RATFOR (structured FORTRAN) main program from a given abstract command sequence. Figure 6(a) shows an input command sequence, whose meaning is as follows: 1. For an image in the standard format (SFDI), G, compute its histogram (HISTl), 2. Find a threshold value from the histogram (THDS2), 3. Apply binarization to G using the threshold (SLTHl), 4. Apply connected component labeling (CLAB), 5. Remove tiny regions (ERSR3), 6. Compute a compactness measure of each region (CRCLI).

Each command denotes the name of a subroutine in SPIDER. The system stores the syntactic and semantic information about each argument of every subroutine in SPIDER, such as input-output discrimination, data type, and semantic usage (e.g., image data, histogram, property table, etc.). For example, Figure 6(b) shows the syntactic and semantic constraints of HISTl. The second line reads “the first argument ($1) is an input argument and its data type is Gray Picture” and the third line “the second argument ($2) is an output argument and its data type is Histogram.” The last three lines specify the semantic constraint on the first and second arguments: the third attribute of the first argument (i.e., $1-3, the number of gray levels of the input picture) must be equal to the first attribute of the second argument (i.e., $2-1, the size of an array for the output histogram). Based on this information, the system determines real arguments for each subroutine, if necessary, asks a user to specify missing parameters, and generates a complete main program consisting of a set of necessary data declarations and a sequence of subroutine calls (Figure 6(c)). By comparing the length of the input command sequence with that of the generated program, the effectiveness of the system can be clearly understood. Specifications used by this system describe abstract image analysis processes in terms of names of subroutines. In this sense, the level of abstrac-

IMAGE PROCESSING, ANALYSIS, AND RECOGNITION SFDl

103

HIST1 $1 In GRYN $2 out HlST

G HlSTl in G THDS2 SLTHl in G CIAB ERSR3 CRCLl

I

$19 $2-1

(%)Syntactic and semantic consIraints.

(a)Command sequence. I program

PARTICLE

I

GRYU: GRAY PICluRE (O"+b* 4; = CC&* 4; - ( M " ) *

*

1

I

=

8

1(1bh* g

'

4;)

* (Mn)hg

= (Mn)hO.

(17)

l

Applying the boundary condition (10) gives

I& 4; = 6,. * *

I

Using Eq. (17), Eq. (13) can be rewritten as

where the scattering matrix is defined as S

= exp {(iz/2ic)M).

Applying Eq. (18) to a thin crystal of thickness z and assuming the incident wave amplitude, i.e., O,,, the amplitude q$, at the exit surface is D O

= e x p (2K kM)

0

(19) 0

Although this method has been known since 1959, it has received little use (Self et al., 1983). B. Inelastic Scattering

Incident electrons impinging on a crystal are elastically scattered by the crystal potential and inelastically scattered by the polarization field of the crystal structure. The polarization process is divided into two parts, a real process in which the definite energy is transferred and a virtual process that occurs before the energy transfer. The real process corresponds to the

184

KAZUTO WATANABE

complex potential, with this complex potential being called the optical potential in the field of atomic collisions and in nuclear physics for homogeneous scattering distributions. A theoretical justification for treating the crystal potential as complex was given by Yoshioka (1957), when inelastic scattering is small compared with the elastic scattering. The Schrodinger equation representing an incident electron’s interaction with a crystal is

where - h2/2mAis the electron’s kinetic energy, H, is crystal’s energy and H‘ is the interaction energy between the electron and crystal. Neglecting the exchange effect, the wave function of this system, Y, is expanded as Y{r, r l , . . . , T N ) =

c *,(r>

*

afl(r1>

. . . ,r N ) ,

(21)

n

where a, is the wave function representing the nth excited state of the crystal and satisfying H,a, = Enan. Function $o in (21) is the elastic scattering and $n is the inelastic scattering that causes excitation to the nth state. Substituting function (21) into Eq. (20),Yoshioka’s coupled equations are obtained as

where ki

= ( 2 m / h 2 ) ( E- E n )

s

Hni= a,*H’amdrl. . . dr,v.

The right-hand side of Eqs. (22) and (23) gives the effect of inelastic waves. Since is small compared with $o, and 12rnHLm/h’*I6 1, Eq. (23) reduces to

+,,

+

(A k f ) G = ( 2 m / h 2 ) H ~ o t j o , (n 2 1 ) Eq. (24) is easily solved as *n(r) = -

exp {ik,(r - r’l} Hio(r’)$o(r’) dr‘. )r - r‘l

(24)

(25)

185

n-BEAM DYNAMICAL CALCULATIONS

Substituting solution (25) into Eq. (22) enables the elastic scattering equation to be obtained as A(r, r’)+hodr‘ = 0, where A(r, r’) is written by A(r, r’) =

-

m exp {iknlr- r’l} H&,Hio 2nh2n + O Ir - r’l

1

-

The wave function of Eq. (26) and crystal potential HA can then be respectively expressed as $o(r> = 1

h

4 h ’ exp (ikh

HA = - 1 h

*

r),

(kh

=k

(27)

bh)

- exp (ib, - r).

(28)

-

By substituting (27) and (28) into Eq. (26),multiplying by exp (- ik, r), and integrating over the entire volume, a generalized fundamental equation of the dynamical theory that takes into account inelastic waves is obtained as

where

Using the identity relation of 1 1 - Px+id x --

+ inij(x)

enables qgto be rewritten as V,g=vg+i-Kg. Inelastic scattering effects can be accounted for by adding a complex potential to the Fourier coefficient of the crystal potential. The matrix M of (8a) is then expressed as

+ + ic V, + K + ir5: V, + v,‘+ i
=

s

4@0

7

zo)p(b

-

bo z 2

-

zo) dbo

194

KAZUTO WATANABE

-4

lDll l+., -2

V(b’, z’)#(b’, z’)P(b - b’, z - z’) dz’db’, (50) in‘ where n’ = (l/hv) and v is velocity. This integral equation of Volterra’s type (Margenau and Murphy, 1943) can be solved by expanding 4(b, z) in an infinite series off,(b, z): -

Substituting the trial forms of (51) into (50), zero-order part and nth order one are obtained as

I

f,(b, z ) = #@o, zo)p(b - bo, z - zo)dbo,

(524

L(b, z ) = j ‘ = ‘ j V ( b ’ , z’)f,_,(b’, z’)p(b - b’, z - z’)dz’db’.

(52b)

I =zo

With the successive application of the stationary-phase approximation method, f, reduces to

f,(h z ) = ~ ( 1 / n ! ) { V(bo, ~ ~ ~ z’ldz’ ‘ -_

r

4(bo, zo)p(b - bo, z

-

zO)dbo.

(53) When relations of (52) and (53) are substituted into (51), the final relationship for the n-beam dynamical calculation before and after passing the slice is given by z =z

4(b, z)

= lexp{ - io’l

V(bo, z’)dz’

:=zo

1

4(bo, zo)p(b - bo, z - zo)dbo

(54) Equation (54) can also be transformed into the familiar convolution form:

4n+,(b) = [#n(b), qn(b)l*.p(b,

Zn+I - Z n h

(55)

where

4%(b) = #(b3

zn

)3

.-- ‘ “ +_I

{ jz ~

q n = exp - 10’

=:”

I

V(b, z’)dz’ .

The sequence of the wave propagator and the phase grating function in Eq. (55) is in the reverse order to that in Eq. (40). This difference is caused by the manner of the projection potential in a slice. The projection on front surface is carried out in Eq. ( 5 5 ) , while the back one is in Eq. (40).

195


D . Extended Multislice Method An extended multislice theory succeeded in including multiple inelastic scattering as well as the multiple elastic one by solving Yoshioka's coupled Eqs. (22) and (23) (Wang, 1989; 1990). Equations (22) and (23) are expressed in a matrix form as

The following basic procedure is similar to that introduced by Ishizuka and Uyeda (1977) for finding multislice formula. The wave function for a highenergy electron may be represented by the modulated wave function: The integral equation for

4,

$, = e x p ( W 4 , can be written in the form (57):

F(r - r', ko)

0

0

...

0

F(r - r', k , ) . . .

0

0

... ... ... . . . F(r - r', k,)

0

where function I is

and the function F is defined as

-

F(r - r', k,) = exp[i{k,Ir - r'l - k, (r - r')}l/lr - r'l. Using a small angle approximation, the stationary-phase approximation, and relations of propagation functions (49a, b), the extended multislice equation for multiple elastic and multiple inelastic scattering before and after penetrat-

Po@

40

‘I

4m

= Jdbo

-

bo, Az)

0

0

pl(b - bo, Az)

0

0

...

0

... 0 .. .. .. ... . . . pm(b- bo, Az)

where the propagation function with energy E, is given by

P,(b, Az)

e x p (inb2/1,Az). i&Az

=L

Here, hAm = Hn;(b, z)Az, and a’ = (l/vh). The equation for first-order approximation of (58) is derived by assuming

(60) Equation (60) has clear physical meanings. For the elastic scattered wave, 40, the first term represents simple elastic scattering, which is the elastic penetration of the incident elastic wave. The second term shows the transitions from excited states to the ground state, which is characterized by a complex correction potential associated with the polarization process in a solid. For the excited state, 4,,, the first term represents the elastic scattering of an inelastic wave and the second one the transmission from other states to the nth state. This latter term is considered the generation of the inelastic wave when the electron passes through a crystal. The practical applications of this theory were performed for the calculations of energy-filtered diffraction patterns and images, the energy-filtered

197


diffraction patterns from atomic inner-shell losses, and the contribution of thermal diffuse scattering to the high-angle annual-dark-field (ADF) scanning-transmission-electron-microscopy (STEM) lattice images (Wang, 1990). E. Inclined Illumination The previous discussion for the multislice method is based on the conditions that the crystal-zone axis is parallel to incident-beam direction and the surface is normal. When fitting simulated HRTEM images with experimental images, beam tilting is an important factor for HRTEM simulation as well as convergent-beam electron diffraction (CBED) experiment and composition analysis by the thickness-fringe (CAT) one. There are two ways to include the tilting effect in the multislice method. In the former, the effect is introduced only in the propagation function through the excitation error, and the projected potential need not be recalculated. The reciprocal-space form of the propagation function through Az is given by P(h, k ) = exp [ - 2xi[(h, k)Az], (61) where ( ( h , k ) is the excitation error (Allpress et al., 1972; Cowley, 1988). The excitation error is defined as negative when the reciprocal lattice point lies outside the Ewald sphere and is parallel to the surface normal. From the geometric arguments, the following relation is obtained:

l ( h , k) = [(l/i.)2 - ((h - h0)2a*2

+ (k - k0)2b**+ 2(h - h,)(k - k,)a*b* cos [(l/A)’ - {hia*2 + k;b*’ + 2h,koa*b*cos~*)]’~2, B*)]1’2

(62) where jl* is the angle between the reciprocal-lattice basis vectors and (h,, k,) the center of the Laue circle. Self and O’Keefe (1988) showed that when the beam is not aligned with crystal-zone axis, the error caused by this treatment is negligible in calculated diffraction-electron amplitudes and phases for the beam tilt of up to 10” away. As for the tilt of surface normal, the treatment is suitable to the inclined surface by up to 45” from the hk plane. With the exception of the definition (62), the paraboidal approximation to the Ewald sphere is utilized by many workers. A different approach for including the effect of crystal tilt in the multislice method has been reported (Lynch, 1971). The latter was proposed by Ishizuka (1982) based on the Schrodinger equation. The procedure for deriving the multislice equation of inclined illumination is almost the same as that in Section 1II.B. The multislice equation for inclined illumination for an orthogonal system in which the z -

198

KAZUTO WATANABE

FIGURE8. The relationship between the incident beam direction and the crystal coordinates. The shift of origin is denoted by b,.

axis is perpendicular to the crystal surface is found as where k

=

@ " + I (b) = [4fl(b)qfl(b)l* (kZ/k)Pfl(b), lkl, o = ( i / h ) ,k, = z component of k, and

(63)

jZZZn 2=zn+,

qn =ex+

i ( k /k . )c' ~

V(b,

Zk) dZk}.

When the c axis of the crystal coordinates is not perpendicular to the surface, i.e., a nonorthogonal system (Fig. S), the b coordinates of origins of phase grating function shift to a direction parallel to the surface. The origin of @ n + , must coincide with that of the next phase grating function qn+,during the next iteration. If this shift is denoted by b,, then Eq. (63) becomes - b,) = [4fl(b)qfl(b)l*(kz/k)Pfl(b). (64) This multislice method with inclined incidence was applied to throughthickness images of small MgO cubic crystals observed from the (1 10) direction with 200 kV and 400 kV high-resolution electron microscopes (Tanji, Masaoka, and Ito, 1989). Simulated through-thickness images were


199

compared with actual microscope images in Fig. 9 for the case of 400 kV. Simulated images show good agreement with the experimental images.

V. COUPLED DIFFERENTIAL EQUATIONS

A . Heal Space Method Van Dyck (1980) derived a new method for n-beam dynamical calculation, in which the entire calculation is done in real space. Thus, it is called the real space method (RS method). The domain of the validity of the RS method has been discussed by several authors (Self, 1982; Kilaas and Gronsky, 1983; Van Dyck and Coene, 1984). In the same way as other n-beam dynamical calculations, the RS method starts with Schrodinger equation:

A$

+ k2$ + V$ = 0,

(65)

where V = - 2me/h2U with crystal potential U. For high-energy electrons, it is convenient to rewrite the wave function as modulated plane wave:

$ = exp(ik

- r)4.

Substituting (66) into Eq. (65) gives

A 4 + i k - V 4 + V 4 = 0. When an incident beam is nearly parallel to the surface normal, as the most experimental situations, the normal component k, of wavevector is larger than the parallel component k, (Fig. 10). It is suitable to separate Eq. (67) into

where V, and A, are the gradient and Laplacian operators in the coordinates x, y , respectively. By making the assumption that 4 is a slowly varying function with respect to z , the second-order derivative with respect to z in Eq. (68) is neglected:

This amounts to ignoring backscattering electrons and a slight change in the electron wave vector when the electron tranverses the potential.

0

0

c-4

20 1

n-BEAM DYNAMICAL CALCULATIONS k.

0

E

FIGURE10. Schematic representation of the scattering problem. The system is divided into a series having thickness E .

Equation (68) is transformed into a first-order differential equation in z :

Using the shorthand notation:

i -V ( x , y ,

2kz

2) =

IV.

Eq. (70) can be reduced to

If the specimen is divided into thin slices of equal thickness, equation for each slice can be given by

E,

the integral

and it can be expanded in power in 1:

The expression of a second-order in I becomes

+

q5& Y , 8 ) = [1 + I { A X y & V,(x, Y>>+ ~ 2 { ( A x y ~ + ) 2V / 2, ( x ,y)'/2

+ A{&,

- Z(x, Y ) > V , ( X , Y )

where the projected potential,

+

P(x9

Y ) V , ( X , Y)Axy1q5(X, Y , 01, (74)

6 ,is defined as in the previous section, and

202

KAZUTO WATANABE

the center of potential given by

I ' z V ( x , y , z>dz T(x, Y ) =

I

E

V ( x , Y , z ) dz

'

Since Axv and V are noncommuting, a rapid calculation can be obtained in the case where Eq. (74) is expanded in alternation of a minimal number of the functions of the form: There is an expression that expands Eq. (74) up to the second order in AxJ and V in one slice E . It takes the form

44%.Y> E )

= exP{l/2iVP(x>Y)(l

+

v)>

*

exP(4y&)

x exp{l/22T/p(x, Y ) ( l - w , .Y))4(x, .Y> 01,

(75)

where the potential eccentricity, 6, is written as

This value presents the relative deviation between geometrical center 4 2 and that of the potential. The basic difference between the RS and multislice methods is that the former is carried out entirely in real space and eliminates the need to use periodic continuation, while the latter approach is carried out either entirely in reciprocal space or swapping between reciprocal and real space when the F F T algorithm is used. The original proposal of the RS method promised to further reduce computation time so that it is directly proportional to number of beams, N , while the multislice method is proportional to Nlog N using the FFT algorithm (Van Dyck, 1980). The method offers a considerable reduction in computation time over the multislice method, when identical sampling conditions are employed. However, keeping the same accuracy, the RS method requires more sampling points and more computation time than the multislice method. The validity and the comparison between the RS method and multislice one were discussed by Kilaas and Gronsky (1983). Van Dyck and Coene (1984) and Coene and Van Dyck (1984a,b) proposed the S 2 error criterion in order to optimize the algorithm and to select the parameters. Well known, the multislice expression is a solution of (73) up to the first order in 1,:

-

d x , Y , &I = exp (jk&A} exp {AK>qYx,Y , 01,

(76a)


203

or

4[x, y, E ] = exp (A&>

- exp {A&A}4tx9Y , 01.

(76b)

which is easily derived using expansion of exp { h A } and exp { A V , } in 1. The required wave function for a given thickness can be obtained accordingly by successive applications of (76a, b). Hence, the dynamical calculations in the slice theory can be considered as an alternation between phase grating operation of V, and electron propagation of 2-D Laplacian operator A,. Wang and Chen (1988) made clear the validity of this first-order RS method using a criterion that imposes a practical limitation in choosing the sampling interval and slice thickness. Furthermore, the superiority for the simulation of nonperiodic objects was discussed by Wang et al. (1990). Recently, using the usual approximation in the “elastic” RS method and applying a “single-elastic-into-inelastic” approach, an extended real space method for multiple elastic scattering and multiple inelastic scattering was set up based on the Yoshioka’s coupled equations (22, 23) (Coene and Van Dyck, 1990). B. Direct Integrated Method

Using 2-D periodicity for a thin crystal, Watanabe et al. (1988; 1990) derived two sets of coupled differential equations for n-beam dynamical calculation. 1. Analytical Integration Method

This method (Watanabe et a/., 1988) was derived from Schrodinger equation using 2-D periodicity. As a crystal potential is obtained by V,,,where g,/ is the projection of reciprocal lattice vector g on the surface plane, the wave function such a crystal can be expanded as

wx 2) = C4Mz)exp G O / / + Q) - x)/s1’2,

(77)

g//

where X = (x,y ) and S = the area of surface. Substituting (77) into the Schrodinger equation, the result is a set of coupled one-dimensional equations: [(d2/dz2)+ 2E - Ik,, + gill2 - 2KNg//(Z)= 2 C V,,//-g//+g,//(z), (78) g’//

where V,,, is the Fourier component of the crystal potential at z. Here, the left-hand side indicates the propagating part with oscillations and the right-hand side the scattering one. The preceding coupled equations were also derived on the basis of the same assumption by different workers

204

KAZUTO WATANABE

(Tounarie, 1962; Lynch and Moodie, 1972; Ichimiya, 1983). When the set of differential equations is solved with numerical integration, the integration step must be kept small enough to accommodate the most rapid oscillations. The oscillating term makes the calculation enormous and tedious. This problem, however, is bypassed by integrating the coupled second-order differential equations analytically (Payne et al., 1986). The analytic integration of these equations gives the coefficient $,,,(Az) at the next step as $,// (AZ) = 2 cos W Z ) $ , / / (0) - $g// ( - A 4

+ 4[1 - cos

c

vg‘//-g/,(o)$g’//(o)/K2,

(79)

g’//

K’ = 2E -

Ik,, + gill2 - 2V,,

(80)

where $,,/(O) and t+hgii( - Az) are the coefficients at the present and previous steps, respectively. In principle, it can describe the localized states along the incident beam direction, such as a disorder system and surface relaxation, and may involve the multiple elastic scattering and multiple inelastic scattering in the crystal. Furthermore, using an extended unit cell, simulations of defects are carried out, as in the multislice method. The n-beam dynamical calculations of aluminum, copper, and gold at 100 kV were carried out in a completely parallel manner by the analytical integration, multislice, and Bethe methods (Watanabe et aZ.,1988). The analytical integration method turned out to be more competitive with respect to accuracy than the latter two methods. However, the slice thickness is much thinner than that of multislice method, and it is hard to apply the method to simulations of defects at a high accelerating voltage. 2. Numerical Integration Method

The time-consuming requirement for the analytical integration method is mainly attributed to the first term of the solution (79). Watanabe et al. (1990) derived a new method with the use of modulated plane wave approximation for a fast electron like other n-beam dynamical calculations. The Gg,,( z ) in the wave function (77) is assumed to be represented by a modulated plane wave: $g//

(4 = &,,( z )exp (ikz).

(81)

Substituting (81) into Eq. (78), the coefficient $,/, satisfies, following a set of equations:

[(d’/dz’)

+ 2ik(d/dz) - (k2+ Ik,, + gi/12- 2E)I$,/,(Z)

= 2 c vg,/,-g,/(bgY(z). g’//

(82) 2 , result is a set of coupled firstProvided that kd$,,,/dz 9 d 2 $ g , , / d ~the


205

These equations remove the oscillating part of the propagating of electrons through a crystal. The right-hand side in Eq. (83) is very small for a high accelerating voltage, so that the integration step can be chosen to be much larger and much computation time is reduced compared with (78). Since the main part of the integration is the convolution sum at right-hand side in Eq. (83), it is possible to reduce computation time with the fast Fourier transform algorithm (Brigham, 1973) because the computational efficiency increases with the beam number. Compared with the multislice method, the slice thickness is so small that the calculation has little effect on slice position, unlike the multislice method. Therefore, it can be expanded not only to complex systems but also to defects using an extended unit cell. Equation (83) is also similar to the standard scattering equations (Howie and Basinski, 1968), except for a crystal potential. In this treatment, a unit cell is divided into many slices, and the crystal potential is constructed at each slice. On the other hand, the crystal potential for standard scattering equations is built up from the structure factors of the unit cell. The viewpoint of this method is quite different from the standard one in spite of its similar appearance. For RHEED, similar equations were also derived by Maksym and Beeby (1981). The Fourier transform to real space may correspond to the RS method. In this treatment, 2-D periodicity is used in deriving the equations to avoid the troublesome 2-D Laplacian calculation, whereas the RS method extracts the problem using a three- or five-point Laplacian approximation. In order to perform n-beam dynamical calculations accurately, it is indispensable to estimate the upper limit of slice thickness and the lower limit of beam number for various materials; that is, convergent conditions. A rigorous way of finding explicit convergent conditions is to calculate the sum of deviation functions (Ishizuka and Uyeda, 1977; Coene and Van Dyck, 1984a,b). The convergent conditions of aluminum, copper, and gold for (100) and (1 10) n-beam dynamical calculations at 100 and 300 kV are summarized in Table I. From this the (100) n-beam dynamical calculation demands fewer beams than the (1 10) one; and the beam number is independent of accelerating voltage. The slice thickness decreases with increasing atomic scattering power but almost does not depend on accelerating voltage. Figures 11 and 12 show thickness series of 000 and 220 beam intensities for (100) n-beam dynamical calculations simulated by the numerical integration, multislice, and Bethe methods at 100 and 300 kV, respectively (Watanabe et al., 1990). For the simulation of the multislice method, slice thickness was

206

KAZUTO WATANABE TABLE I MAXIMUM SLICETHICKNESS AND MINIMUM BEAN NUMBER FOR CONVERGENCE. IS THE LATTICE CONSTANT.)

(“A”

(100) n-beam dynamical calculations

(1 10) n-beam dynamical calculations

A1 11 x 11

cu

Au

I 1 x 11

11 x I I

cu

lO0kV

a/64

a/256

a/5 12

1 1 x 11

11 x I I

11 x 1 1

13 x 13

13 x 13

13 x 13

300kV

a/64

a/256

a/5 12

(a/2’”)/64

(a/2’I2)/128

(a/2’ 2)/256

Al 13 x 13 (a/2’I2)/64

KV

Au

13 x 13

13 x 13

(a/2”*)/128

(a/2’‘)/256

-

(1001

Al

220

~

~~

0.37--

.

.. .

OO

Z/a

15

20

0.3~

Au

220

L OO

A 5

, L

L

10

Z/a

U

_j

15

20

....

oo-o-qd

5

10

Z/B

~.

15

FIGURE11. Beam intensities of the 000 and 220 reflections for (100) n-beam dynamical calculations at 100 kV: the multislice (circles), Bethe (solid line), and numerical integration methods (dashed line).

207


L,

OO

I

5I

I

I

I

‘ 10 1

1

I

L

. . . 15

20

00

5

10

15

20

15

I

z/a

Z/a

L-,

OO

5

10

Z/a

Z/a

5

10

Z/a

15

20

OO

5

10

Z/a

FIGURE12. Beam intensities of the 000 and 220 reflections for (100) n-beam dynamical calculations at 300 kV: the multislice (circles), Bethe (solid line), and numerical integration methods (dashed line).

a (lattice constant) and beam number 32 x 32. The slice thickness is the common condition for aluminum, copper, and gold, and the beam number is large. An 11 x 1 1 beam number was adopted for the Bethe method. Results of the three methods are superimposed at low atomic scattering power independent of accelerating voltage. As atomic power increases, the numerical integration method at 100 kV shows little difference from the Bethe method and yields large disagreements with multislice method. The poor approximation of the multislice method has already been suggested by Lynch (1971). At 300 kV, the difference becomes appreciable. The discrepancy with the multislice method is qualitatively explained in terms of a sudden perturbed approximation (Gratias and Protier, 1983). According to this

208

KAZUTO WATANABE A :

100 KV

(110)

Al

111 ~

~~

0

AU

111 ~

7

FIGURE13. Beam intensities of the 000 and 11 1 reflections for (1 10) n-beam dynamical calculations at 100 kV: the multislice (circles), Bethe (solid line), and numerical integration methods (dashed line).

approximation, the slice thickness in the multislice method must be chosen thin enough to obey the following inequality: Az G 2 K / ( T I V J 2 ) ' * ,

where K = wave number. By selecting the slice thickness to be lattice constant and making the beam number large, the convergent results are obtained for gold at l00kV. However, this condition may be far from satisfactory for a sudden perturbed approximation. This poor approximation is dissolved with the thinner slice thickness (Self et al., 1983). In Figs. 13 and 14, the intensities of the 000 and 111 beams for (110)

209

n-BEAM DYNAMICAL CALCULATIONS Al

000 L..

-,

300KV

( 1 10)

Al

111

I

0.31

I

L

I

15

20

Au

> t0.2

t

I

FIGURE14. Beam intensities of the 000 and 1 1 1 reflections for (110) n-beam dynamical calculations at 300 kV: the multislice (circles), Bethe (solid line), and numerical integration methods (dashed line).

n-beam dynamical calculations simulated by the three methods are plotted against thickness (Watanabe et al., 1990). A 16 x 16 beam number was adopted for the Bethe method, and a 32 x 32 beam number and 42’’’ slice thickness were used for the multislice method. The numerical integration method is in good agreement with the Bethe method for all atomic scattering powers, whether accelerating voltage is 100 kV or 300 kV. While the multislice for aluminum is identical with other two, the deviation increases with atomic scattering power. Compared with the (100) n-beam dynamical calculations, the deviation is not so large and is not drastically diminished with accelerating voltage. This small deviation may be caused by a smaller slice thickness than in the (100) one. The effect of accelerating voltage,

210

KAZUTO WATANABE

however, cannot be interpreted simply by a sudden perturbed approximation, unlike in the (100). The numerical intergarion method is competitive with respect to accuracy as well as calculating speed. Therefore, using an extended unit cell and convolution sum calculation with FFT method, it also can be applied to dynamical calculations for complex systems and defects. In addition, an extended theory that involves multiple elastic scattering and multiple inelastic scattering is introduced with the same manner as the extended RS method (Coene and Van Dyck, 1990).

C. Scattering Matrix Method Zhao, Poon, and Tong (1988) and Nagano (1990) respectively proposed new approaches for RHEED calculation using the scattering matrix method. They derived scattering matrices for a slab using the technique for solving coupled second-order differential equations developed by Stechel, Walker, and Light (1978), Magnus (1954), and Light (1971). In this subsection, a new scattering matrix method for n-beam dynamical calculation is discussed on the basis of Nagano’s treatment, because it is flexible and efficient. Assuming 2-D periodicity, the crystal potential and wave function can be written by

where X = (x, y ) , gii = (gx,g,), k = (k,,, kz); and S = area of surface. Substituting Eq. (84) into the Schrodinger equation, t,hgii(z) obeys the 1-D second-order differential equations which are equivalent to (82):

where

with

Here, E is the incident electron energy.


21 1

Introducing the column vector Y as

(89) Equation (86) can be rewritten in the following form: d2Y dz2

-- -

m,

w,/,,/

where ( F),//,,,/ = ' Defining a column vector 8 to combine Y and its derivative as

8 = [dY/dz

1.

Equation (90) can be simply rewritten as

-d8 = [ a dz

718, Fa

where r'is unit matrix and 0 is zero matrix. Over the short range, h, the solution (Magunus, 1954; Light, 1971) can be obtained by an exponential series:

9 ( i )= Mi8 (i - I), f i i = exp [h;

q.

(93) (94)

For simplicity, a slab is divided equally into (n - 1) slices as shown in Fig. 15. Using Eq. (93) repeatedly results in

q ( n ) = M&(n - 1) = MnMn where

811 812 B=[821

8221

-

1 . . . M 2 9 ( 1) = B q ( l),

(95)

212

KAZUTO WATANABE z

0

2 0

~

FIGURE15. Slicing a slab from 0 to zo into n

-

1.

with

The matrix W is diagonalized by the unitary matrix

0:

On- W o n = A: I . In order to apply the layer-doubling method that had been originally

213


/I\

incident

transmitted waves

reflected waves c a s e

I

c a s e

I 1

FIGURE16. Schematic view of electron scattering processes for case I and case I1

developed for LEED, Nagano (1990) derived transmission and reflection coefficients for two scattering cases as shown in Fig. 16. The first one is where the incident electron comes from above the slab (case I) and the second is where it comes from below the slab (case 11). In the case I, the electron wave function is written as

Y;(r)

i

-

exp ( - ik,, X - ikglz )

c

&I//

=

+ 1rilg1,/exp {i(k// + gill - X + ikgz},

z

> zA

z

< zg,

g//

exp {i(k// + g//) * x

-

ikg4.

Pi/

Using the proper boundary conditions and calculating bjj,the scattering wave functions are uniquely determined, thereby enabling the transmission

214

KAZUTO WATANABE

coefficients (rgiig.//)and reflection ones

(rg;ig.ii) to be obtained rexP ( - ikglZA)

as

1

where

For case 11, where the incident electron comes from below the slab, the electron wave function is written as

As in case I, the columns for the transmission and reflection are expressed as

215


These columns have the complete information of every scattering process in each case. Scattering matrix for the combined system of two slabs can be considered as seen in Fig. 17. According to the layer-doubling scheme, scattering matrices in the cases I and I1 are given, respectively, by RAB-

=RA-

FAB-

=

RAB+

-R

TAB+

=

+ F A i R B - ( f -

FB-(T-

AA+RB-)-I

FA-,

( 102)

RA+RB-)-IFA-,

(103)

and B i + FB-RA+(f-

RB-RA+)-I

FB+ 7

FA+

(T- R B - R A + ) - I

FB+

( 104)

(105) Equations (102)-( 105) have very clear physical meanings. The scattering process is interpreted from right to left in these equations. For example, (102) shows the following processes: the incident electron is simply reflected by slab A , or transmits slab A , and after repeated multiple scattering between slab A and slab B, which is reflected by slab B and transmits slab A . In general, since scattering matrices are calculated at the center of the slab, phase matching becomes sensitive. Equations (102)-( 105) take care of the phase advancement automatically, so that the layer-doubling method of LEED can be used without worrying about phase matching at all. Using the layer-doubling method, therefore, a calculation for a perfect crystal is reduced to a slab corresponding to a unit cell, because other scattering matrices are identical, due to the periodicity of the potential in the z direction.

216

KAZUTO WATANABE

T

FIGURE 17. Schematic view of the layer-doubling method.

The results of (100) n-beam dynamical calculation using the scattering matrix method were compared with the multislice and Bethe methods (Watanabe ef a[.). The parameters used for the multislice and Bethe methods are the same as those in Fig. 11. For the simulations of the scattering matrix method, the convergent beam number was 135 and the convergent slice thickness 4200 (a = lattice constant). Figure 18 shows the thickness series of 000 and 220 beam intensities for aluminum, copper, and gold calculated with three methods. The scattering matrix method is in good agreement with the Bethe method for all atomic scattering power and is also identical with the multislice method except for gold. While this scattering matrix method requires an enormous memory, it is competitive with respect to accuracy and can take into account the inclined beam effect spontaneously. Furthermore, it may involve multiple inelastic scattering.

217


100 K V

A I

A1

t

-c n

- -0Mult1-9licc ~the

1

OScatterlng-Matrlx

t

50.5: P

f

~

t --&&the

5

10

5

15

10

Z/e

Z/a

000

220

oMul t 1-91 Ice O S c a t t s r i ng-Matr I x

fn

f.

20

15

cu

cu

I-

~

c

--&the OMul t I -91 I cc OScattcrIng-Matrix .

10

5

15

2 /e

20 - 0 0

5

Au

L &

Z10 /a

15

' ' ' 20

Au

2?!-

. . . 0.. 3 I

-Enthe

>

>

-

0

0

-

t. $0.56 k

f.

t0.2-

z w

L

L

1

I cc OScattcrlng-Matrlx

-

k

-

oMul t 1-91

-

20.1-

--&the

I

OMulti-slice OScattcring-Matrix

5

I0

Z/a

15

20

OO

5

10

15

Z/e

FIGURE18. Beam intensities of the 000 and 220 reflections for (100) n-beam dynamical calculations at 100kV.

VI. SUMMARY As early as 1928, Bethe developed the dynamical n-beam theory of electron diffraction, which is more complex than theories applied to two diffracted beams. Following this, the problems of n-beam dynamical scattering of fast electrons have been approached by a variety of methods. Initially, the most important factor when selecting a method for a given situation was the constraint placed on computing time and memory size, although currently most reported methods are evaluated on a real-time basis without having this constraint. In addition, a complete simulation system is now commercially available. Rapid progress in obtaining better HRTEM resolution requires

218

KAZUTO WATANABE

more precise simulations for n-beam dynamical calculations that account for various effects such as beam tilt and inelastic scattering (Bithell and Stobbs, 1989). Up to the present, the multislice method has been the most flexible and manageable technique to perform n-beam dynamical calculations of defects as well as perfect crystals, having been improved so as to treat the effects of bezm tilt and inelastic scattering. It has also applied to simulations performed using the advanced technology of electron microscope (ADFSTEM). However, the problems involved in selecting slice thickness using strong atomic power at low accelerating voltage and for complex material and determining optimal slice position have not been completely solved. Thus, the multislice method may not be the best method to use for solving various problems. The Bethe method, on the other hand, is the most precise and effective theory used for matching through-focus or throughthickness HRTEM images and those simulated, because the wave functions at each thickness can be easily calculated from the eigenvalues and eigenvectors. It should be noted that this method makes it difficult to evaluate n-beam dynamical calculations for complex systems and conceptually inadequate for defect evaluations. The real space method is a reliable method of simulating nonperiodic objects, although there is a little discrepancy in beam intensities for perfect crystals. The direct integrated method is competitive with respect to accuracy with Bethe and multislice methods, but the computation time and memory requirements are still greater than for other methods. From our elementary calculations, the scattering matrix method is shown to give accurate n-beam dynamical calculations for perfect crystals, although the simulation time and memory size are of the same order as the direct integrated method. The matrix scattering method has an advantage of being able to take into account the beam tilt effect automatically, and this may make it possible to incorporate the inelastic scattering effects in principle. Clearly, there are advantages and disadvantages when using each method. All methods should therefore be applied to various existing problems, making use of their particular advantages. For example, in the case of defect simulations, the thickness and instrumental parameters are determined using the Bethe method, with image simulations being subsequently performed using either the multislice or real space method. More advanced n-beam dynamical calculations will also be required in the future to provide higher resolutions for electron microscopes.

219


ACKNOWLEDGMENTS Fruitful discussions with Drs. Y. Kikuchi, K. Hiratsuka, N. Hashikawa, and K. Mituishi on multislice, Bethe’s eigenvalue, direct integrated, and scattering matrix methods are acknowledged. Additional thanks are due to Professors H. Yamaguchi and I. Hashimoto for drawing my attention to HRTEM. I would also like to thank Dr. P. Hawkes for his editional support. APPENDIX: CRYSTAL POTENTIAL As mentioned in Section I, knowledge of the crystal potential is an essential factor for n-beam dynamical calculation. The steps leading to conventional calculation of the crystal potentials are schematically shown in Fig. 19(a). The potential is produced by atomic scattering factorsfor ionic onesf;,, . The Fourier coefficient, V ( g ) , of the potential is obtained as

where R = the volume of unit cell. The indexj indicates a sum over all atoms in the unit cell, with the fractional coordinate of thejth atom being rj and g being the reciprocal lattice vector. The atomic scattering factor, f; , can be obtained either from tabulated values (Smith and Burge, 1962) or from the Mott formula (Mott and Massey, 1965). For n-beam dynamical calculation, it is convenient to store scattering factors in the form of parameterized fits to the scattering curve. While the most commonly used scattering factors are calculated by Doyle and Turner (1968), there is lack of complete table of parameterized fits of scattering factors. Then, Gaussian fits of the international table for x-ray crystallography for x-ray scattering factors, f”,are available for converting to the electron values with the Mott formula: f ’ ( s ) = (me2/2h2)[Z-f”(s)]/s‘.

( 107)

where s = sin 012. However, the nine-parameter Gaussian fits for the x-ray scattering factors is applicable only to an angular range s = 0 to 20 nm- and attempts to extend it to a higher angle met with large errors. Since the diffracted beams out of values of h, k, 1, corresponding to reciprocal lattice vectors of 30nm-’ are required to maintain sufficient precision, Fox et al. (1989) presented more accurate fitting for a higher angle than 20 nm-’ . The modification of the small angle region was proposed by Peng and Cowley (1988). Unfortunately, this approach cannot involve the screening effect or bonding due to valence charge electrons. In order to exactly incorporate the

’

r; calculate

N

N 0

solve

HY = E Y

I

calculate

calculate p

V I . .

I

= Y 'Y

solve

calc u 1 ate

I

FIGURE19. Block diagram of computational steps in calculating crystal potentials: (a) conventional crystal potential evaluated from atomic scattering factors, and (b) VT is constructed from the ionic potential and the screcning one.

F,,,is


22 1

screening potential due to valence charge electrons in the crystal potential, Watanabe et al. (1986) and Kikuchi (1988) proposed the calculation of the crystal potential that is divided into an ionic potential and a screening (Fig. 19(b)). The first step is started with solving the optimized Dirac-FockSlater equation (Lingren and Rosen, 1974) or the Hartree-Fock one, and the scattering factor of ions is calculated. Then, the ion potential is given by

The process of screening potential calculation is initiated using a band theory; i.e., the pseudopotential (Cohen and Chelikowsky, 1988), APW (Loucks, 1967), LMTO (Skriver, 1984), and so on. Using a suitable theory for a material, the electronic energy E,(k)and the wave function $nk can be determined. Hence, total valence charge density

is calculated. The charge density is calculated by the special point scheme of Chadi and Cohen (1973), which yields good agreement with a sum throughout the Brillouin zone. Once the valence charge density is known in terms of its Fourier transform, the Hartree-type screening potential can be evaluated easily. The Hartree screening potential is given by

The Hartree potential is cancelled exactly by the ionic potential at g = 0. As a simplification, the nonlocal Hartree-Fock exchange operator is often replaced by a local potential proportional P ' / ~ but , this approximation fails completely when applied to a high-energy one-particle state. Then, the suitable exchange potential for a fast electron is selected or the exchange potential is omitted because of small values compared with other potentials. The V, and V ,together form the electronic screening potential of the system. They are then added to an ionic potential. REFERENCES Allen, L. J., and Rossouw, C. J. (1990). Phys. Rev. B42, 1 1 6 4 4 1 1654. Allpress, J . G., Sanders, J. V., and Wadsley, A. D. (1969). Acta Cryst. 325, 1156-1164. Allpress, J. G., Hewat, E. A,, Moodie, A. F., and Sanders, J. V. (1972). Acta Cryst. A28, 528-536. Armigliato, A,, Parisine, A , , Hillerband, R., and Werner, P. (1985). Phys. Stat. Sol. ( a ) 90, 115-126.

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Bethe, H. A. (1928). Ann. Phys. (Leipzig) 87, 55-127. Bithell, E. G., and Stobbs, W. H. (1989). Philos. Mag. A@, 39-62. Bourret, A., Rouviere, J. L., and Spendeler, J. (1988). Phys. Stat. Sol. ( a ) 107, 481-501. Blume, J. (1966). Z . Phys. 191, 248-272. Brigham, E. A. (1973). “The Fast Fourier Transform,” Prentice-Hall, Englewood Cliffs, NJ. Chadi, D. J., and Cohen, L. M. (1973). Phys. Rev. B8, 5747-5453. Coene, W., and Van Dyck, D. (1984a). Ultramicroscopy 15, 41-50. Coene, W., and Van Dyck, D. (1984b). Ultramicroscopy 15, 287-300. Coene, W., and Van Dyck, D. (1990). Ultramicroscopy 33, 261-267. Cohen, L. M., and Chelikowsky, J. R. (1988). “Electric Structure and Optical Properties of Semiconductors,” Springer-Verlag, Berlin and Heidelberg. Cowley, J. M. (198 1). “Diffraction Physics,” North-Holland, Amsterdam. Cowley, J. M. (1988). In “High-Resolution Transmission Electron Microscopy and Associated Techniques” (P. R. Buseck, J. M. Cowley, and L. Eyring, eds.), 58-124, Oxford University Press, Oxford. Cowley, J. M., and Moodie, A. F. (1957). Acta Cryst. 10, 609-619. Cundy, S. L., Howie, A., and Valdre, U. (1969). Phil. Mag. 20, 147-163. Doyle, P. A,, and Turner, P. S . (1968). Acfa Crysf. A24, 390-397. Fields, P. M., and Cowley, J. M. (1978). Acta Cryst. A34, 103-112. Fox, A. G., OKeefe, M. A,, and Tabbernor, M. A. (1989). Acta Cryst. A45, 786-793. Frank, J. (1973). Optik 38, 519-536. Fujimoto, F. (1959). J. Phys. Soc. Jpn. 14, 1558-1568. Fukuhara, A. (1966). J. Phys. SOC.Jpn. 21, 2645-2662. Gratias, D., and Protier, R. (1983). Acta Cryst. A39, 576-584. Hashikawa, N., Watanabe, K., Hiratsuka, K., Tsuruta, C., Hasimoto, I., and Yamaguchi, H. (1991). Inst. Phys. Conf. Ser. No. 117, 11-16. Hiratsuka, K. (1991). Philos. Mug. B63, 1087-1 100. Hirsch, P. B., Howie, A,, Nicholson, R. B., Pashley, D. W., and Whelan, M. J. (1965). “Electron Microscopy of Thin Crystals,” Butterworths, London. Howie, A. (1963). Proc. R . Soc. A271, 268-287. Howie, A. (1966). Phil. Mag. 14, 223-230. Howie, A., and Basinski, Z. A. (1968). Phil. Mag. 17, 1039-1063. Humphreys, C. J., and Hirsch, P. B. (1968). Phil. Mag. 18, 115-122. Humphreys, C. J., and Whelan, M. J. (1969). Phil. Mag. 20, 165-172. Ichimiya, A. (1983). Jpn. J. Appl. Phys. 22, 176-180. “International Tables for X-ray Crystallography,” Kynoch, Birmingham, England. Ishizuka, K. (1980). Ultramicroscopy 5, 55-65. Ishizuka, K. (1982). Acta Crysr. A38, 773-779. Ishizuka, K., and Uyeda, N. (1977). Acta Cryst. A33, 740-749. Izui, K., Furuno, S., Nishida, T., Otsu, H., and Kuwabara, S. (1978). J. Electron Microsc. 27, 171-179. Jap, B. K., and Glasser, R. M. (1978). Acra Cryst. A34, 94-102. Kikuchi, Y. (1988). Philos. Mag. B57, 547-556. Kikuchi, Y., Watanabe, K., Naitoh, S., Hiratsuka, K., and Yamaguchi, H. (1988). Phys. Stat. Sol. ( a ) 108, 509-517. Kilaas, R.. and Gronsky, R. (1983). Ultramicroscopy 11, 289-298. Kogiso, M., and Takahasi, H. (1977). J. Phys. Soc. Jpn. 42, 223-229. Legoues, F. K., Copel, M., and Tromp, R. (1989). Phys. Rev. Lert. 63, 1826-1829. Light, J. C. (1971). In “Methods of Computational Physics” (M. Routenberg, ed.), 10, 1 1 1-140, Academic Press. New York.


223

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Watanabe, K., Kikuchi, Y., Hiratsuka, K., and Yamaguchi, H. (1990). Actu Cryst. AM, 94-98 Watanabe, K., Hiratsuka. K., and Yamaguchi, H. (1991). Phil. Mug. A64, 81-86. Watanabe, K., Mitsuishi, K., and Hashimoto, I. (to be published). Whelan, M. J. (1965). J . Appl. Phys. 36, 2103-2110. Wright, A. C., Ng, T. L., and Williams, J. 0. (1988). Phil. Mug. Lett. 57, 107-111. Yamashita, T., Ponce, F. A., Pirouz, P., and Sinclair, R. (1982). Phil. Mug. A45, 693-711. Yoshioka, H. (1957). J. Phys. SOC.Jpn. 12, 618-628. Zhang, J., Kuo, K. H., and Wu, Z. Q. (1986). Phil. Mug. A53, 677-685. Zhao, T. C., Poon, H. C., and Tong, S. Y. (1988). Phys. Rev. B38, 1172-1 182.

ADVANCES 1Y ELECTRONICS AND ELECTRON PHYSICS, VOL. 86

Methods for Calculation of Parasitic Aberrations and Machining Tolerances in Electron Optical Systems M. I. YAVOR Institute of Analytical Instrumentation. St. Petersburg. Russia

I. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11. Parasitic Aberrations Caused by Electron Optical Element Misalignment. . . 111. Effects of Electromagnetic Field Disturbances on Charged Particle Trajectories IV. General Methods for Calculation of Electromagnetic Field Disturbances due to Electrode or Pole Face Distortions . . . . . . . . . . . . . . . . . . . . A. Simple Example of the Exact Conformal Mapping . . . . . . . . . . . B. Bertein Perturbation Method . . . . . . . . . . . . . . . . . . . . . C. Coordinate Frame Variation Method. . . . . . . . . . . . . . . . . D. Method of Integral Equations “in Variations” . . . . . . . . . . . . . V. Field Disturbance in Electrostatic and Magnetic Sector Analyzers. . . . . . A. Electrostatic Toroidal Condenser. . . . . . . . . . . . . . . . . . . B. Inhomogeneous Sector Magnet . . . . . . . . . . . . . . . . . . . . VI. Application of Approximate Conformal Mappings . . . . . . . . . . . . VII. Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

.

.

225 221 235 245 246 248 253

. . 258 . 260 . 261 266

. 269 211 219

I. INTRODUCTION The calculation of parasitic aberrations and machining tolerances is a necessary stage of a design of any electron optical device. Since in practice manufacturing imperfections are inevitable, a designer needs to know their consequences. This knowledge can help provide for ways of the correction of parasitic aberrations. The correct estimation of tolerances allows a manufacturer to choose the manufacturing technology properly and also to optimize the adjustment of the device. It should be emphasized that the calculation of tolerances is important not only for the unique high precision electron optical systems but also for serially produced devices, because setting requirements too high for the manufacturing technology leads to the considerable rise in price of the production. In spite of the evident importance of the problem, there are practically no publications generalizing the experience of calculations of parasitic aberra225

English translation copyright 0 1993 by Academic Press, Inc. All rights of reproduction in any form reserved ISBN 0-12-014728-9

226

M. I . YAVOR

tions due to machining or assembling imperfections of electron optical systems. Only a number of papers exist where the effects of such imperfections on the properties of some types of devices are investigated. The attempt to review these papers was made recently by the author (Yavor, 1991b) but this review is too brief to penetrate deep enough into the problems involved. It is the goal of the present chapter to describe various methods of the parasitic aberration theory, to discuss their fields of applications as well as their merits and shortcomings, and to illustrate them with some examples. This review does not pretend to cover all achievements of the theory of tolerances but rather gives a general idea of its problems and methods. The review also does not contain the detailed investigation of parasitic aberrations and tolerances of any particular electron optical system. However, in order to make it useful not only for theorists who would like to learn how to calculate parasitic aberrations but also for practical engineers who are interested in the results and not in methods, the review is supplied with the exhaustive list of references. In addition to the notes made in the text, some brief comments to this list are found in the Conclusion. Generally speaking, the determination of tolerable limits for machining and assembling inaccuracies in electron optical devices does not reduce only to the calculation of parasitic aberrations due to these inaccuracies. The point is that most first order parasitic aberrations, such as, for example, variations of an image position or dispersion coefficients, can be more or less easily compensated for by means of some correcting elements. Therefore in reality tolerances depend on the possibility of such a compensation provided in the device under consideration. However, the ways for adjusting electron optical systems are the subject of a separate investigation, so in the present chapter we confine ourselves to discussion of the methods for calculation of parasitic aberrations. Section I1 of the chapter is devoted to the methods for calculation of parasitic aberrations due to misalignment of separate elements (lenses, deflectors, multipoles, etc.) of a complex multistage electron optical system. Since the electron optical properties of separate stages are assumed to be unchanged in this case, only geometrical considerations are needed here; and the technique involved is much simpler than that used when the elements themselves are manufactured inaccurately. The latter case is discussed in Section 111, where charged particle trajectories in a disturbed electromagnetic field are investigated. The particle trajectory equations discussed in Section I11 can be used for practical calculations only if the field disturbance inside an electron optical element due to its manufacturing imperfections is known. It is the problem of calculation of this disturbance that is most difficult to solve. Section IV of the review is devoted to the general methods for calculation of electromagnetic

METHODS FOR CALCULATION OF PARASITIC ABERRATIONS

227

field disturbances caused by distortions in shapes of electrodes or magnet pole faces. The special method that allows one to describe analytically field disturbances in sector electrostatic or magnet analyzers is described in Section V. Finally, in Section VI the application of the conformal mapping method to the field calculation for weakly distorted electron optical elements is discussed. Now we make some preliminary remarks. First of all, in the chapter we consider only current-free static fields. Furthermore, disturbances of fields and trajectories are calculated in the linear approximation with respect to geometrical parameters characterizing defects of the element manufacturing or assembling. This approach is generally used and justified, since as a rule manufacturing imperfections themselves cannot be described with a high accuracy. It should be noted that very often in the literature on the tolerance theory the linear approximation is used not only in the parameters mentioned previously but also in the geometrical parameters characterizing a charged particle beam. In other words, they consider the influence of imperfections only on the first order properties of a system. However, to our opinion that is not always sufficient. Many high-precision electron optical devices are designed so as to eliminate some higher order aberrations, and manufacturing imperfections break conditions of such an elimination. Moreover, higher order aberrations cannot be so easily adjusted as the first order properties. Thus in some cases it is useful to estimate both parasitic changes of the first order properties and, say, of the second order aberrations. For this reason we shall consider the second order properties when it is possible. BY ELECTRON OPTICALELEMENT 11. PARASITIC ABERRATIONS CAUSED MISALIGNMENT

In multistage electron optical systems parasitic aberrations may be attributed to two different types of defects. One is the manufacturing imperfections of electron optical elements (electrostatic or magnet lenses, sector fields, multipoles, etc.), leading to perturbations of their electromagnetic fields. These defects will be discussed in the following sections. However, even if all the elements are manufactured ideally, the system still possesses parasitic aberrations due to defects of the second type, those are displacements of elements relative to their nominal positions. It is the purpose of this section to describe the methods for calculation of the influence of such imperfections on properties of electron optical devices. The investigation of the aberrations in question is simple compared with that of the defects of the first type. The reason is that the misalignment of an

228

M. I. YAVOR

element does not change its influence on the charged particles and only makes it necessary to consider this influence in a displaced coordinate frame. Therefore the problem of the calculation of the element misalignment effects reduces to the derivation of relations connecting parameters of an arbitrary trajectory in the coordinate frames defined with respect to the ideal and misaligned element position. The first general investigation of the problem, known to the author, was undertaken in the paper by Bazhenova, Zinoviev, and Fjodorova (1967). The formulae were obtained in this paper that expressed the perturbance of an arbitrary paraxial trajectory going through an infinitely thin misaligned electron optical element (the words infinitely thin mean that the entrance and exit faces of an element are assumed to coincide). Later, the article by Matsuda, Matsuo, and Takahashi (1977) studied the influence of some particular types of a median plane misalignment of a two-stage mass spectrometer on its focusing properties. Changes in ion optical properties of a sector magnet analyzer due to its radial displacement was discussed in the paper by Malov and Trubatcheev (1978). The most complete theory of parasitic aberrations caused by misalignments was proposed in the article by Brown and Rothacker (1977). In this paper arbitrary misalignments of sector deflecting systems as well as thick lenses with straight axes were investigated. The corresponding algorithm was included in the computer program TRANSPORT (Brown et al., 1973). Similar techniques of the calculation were also used in some other computer codes; for example, COSY INFINITY (Berz, 1990). In all the publications just listed only the effects of misalignments on the first order properties of a charged particle beam were discussed; corrections affecting higher order aberrations were not taken into account. The calculations we present here are similar to those made by Bazhenova et al. (1967) and Brown and Rothacker (1977), but we retain the correction terms mentioned previously. Figure 1 shows the trajectory of a particle entering a misaligned element of an electron optical system from the outer field-free space. We bind the coordinate frame {x,y,z } with the ideal element position, the z axis pointing along its optical axis and the xy plane coinciding with the entrance face of the element. Suppose the element in question is to experience a small shift characterized by the vector 6r = (dx, 6y, 6z) and a small rotation described by , We bind the coordinate frame ( X , Y , Z } as the vector 6 6 = ( ~ 5 + ~6+?, shown in Fig. 1 with the misaligned position of the element. The X Y plane of the latter frame is the real entrance plane of the element. Y ,Z } In the linear approximation the relations between the {x, y , z } and {X,


229

FIGURE I . Shown are the coordinate frames bound with the ideal [x,y,z] and misaligned

[A', Y , Z ] positions of an electron optical element. The displacement of the element is defined by the shift 6r and rotation charged particle.

64 of its entrance profile plane xy.

T is a trajectory of an arbitrary

coordinates of an arbitrary point read

x = x + y s 4 , - zs4, - sx,

+ y + zs4, - sy, z= x&p,- ys4, + z - sz. y = -XS$,

In the field-free space the trajectory equations are

x(z)

= x,

Y ( Z > = Yo

+ x;z, +Y

k

with the vector (xo,xi,y o ,yh) = k, characterizing the coordinates and slopes of the trajectory at its intersection with the entrance face of the aligned element. Let the effect of the aligned element on a charged particle be described generally by the nonlinear operator

k, = M16, (2) where the vector k, = (,2c,,2L,ye,9:) contains the trajectory parameters at the exit face of the aligned element; the i axis of the (i,p, i} coordinate frame points along the optical axis of this element; the i jplane coincides with its exit face. Then the transformation of a trajectory by the misaligned element is described by the following relation:

K,

= MK,.

(3) Here K , = (&,Xi, Yo,Y;);K, = Xo = XJ,,,; X i = dX/dZI,,,; YO= Yll,o; Yi = dY/dZI,,,; the vector K, contains the analogous coordinates and slopes of the trajectory at the exit face 2 = 0 of the misaligned

(x,x,t,t);

230

M. I . YAVOR

element. Thus to obtain the relation between the vectors ko and k, determining (in the aligned coordinate frame) the trajectory transformation by a misaligned element, one should find the relation between the vectors ko and K, as well as between K, and k,. In the linear approximation with respect to the disturbance vectors 6r and S4 the point of the intersection of the trajectory with the X Y plane ( Z = 0 ) has the z-coordinate zo =

-

xos4,

+ y064, + 6z.

Thus

xo = X(Z0) + Y(Z0)64, - z o w , - 6 x = xo

yo =

-

+ y064, + x;sz - sx + x;yos~, - x;xos4,, x(zo)W, + Y ( Z J

= Yo - xow;

+Z O W

-

SY

+ Y 8 Z - 6Y - xoY;64, + Y;Y,64,,

(4)

The formulae obtained show that element shifts along the x and y axes lead to shifts of the corresponding coordinates only; a shift along the z axis is obviously equal to a change in the field-free interval length. A rotation about the z axis mixes x and y coordinates. Only rotations about the x and y axes give rise to terms of the second order with respect to the initial coordinates and slopes. If we neglect the second order terms in Eq. (4)then those equations can be rewritten in the matrix form

KO = Rko - D,

(5)

where

This result is identical to that obtained by Bazhenova er al. (1967) and by Brown and Rothacker (1977). Equation (5) can be applied if we are interested in only the first order properties of a system.


23 1

The derivation of relations between the components of the vectors K, and k, is straightforward. These relations read

x

a, = - f,S& 3, = + f,S& a: = 2;- Y;s&

*

+ 62 - fes&+ 2;&5&, - t / S i + S? + t/$sfjjv - t/ ts&, + s& + f;'sl$, - f;s&, - 2;si

*

+

(6)

+

2;s& - s& - f;2sfjjx 2;%s&. j: = Here the values (62,Sj,6.2) = Sf and (S$x, S$,) = S$ determine a displacement of the {T, p,21coordinate frame relative to the {a,9, i} frame. In the linear approximation Eq. (6) takes the form k, = R-IK,

+ D,

(7)

where

1

-6.2

-s&

O \

R-' = 0 -s& 0 1 I Combining Eqs. ( 2 ) and ( 3 ) with Eqs. ( 5 ) and (7) we come finally to the following result: k, = R-'M(R$ - D) + D,

(8) Equation (8) describes the paraxial trajectory transformation by the misaligned electron optical element. Note that one should be very careful when using Eq. (8), since sometimes the substitution into Eq. (8) of the operator M in the form of its linearized first order matrix representation can lead to the incorrect vector k, dependence on the parameters br and S4. Indeed, suppose that an electron optical element with two planes of symmetry possesses second order aberrations; then the trajectory coordinate 2eat the exit face of the element is

232

M. I. YAVOR

where (. . .} denotes terms of the second order with respect to the components of the vector k,. Thus we see that the nonlinear part of the operator M defined by the coefficients a,, , a,2, a,z, q4,and a- contributes to the ie coordinate in the linear approximation with respect to ax,6y, 64r, and 84,. This contribution is described by terms contained in square brackets in Eq. (10). To understand what parasitic aberrations can be caused by the displacement of the electron optical element, we now consider a system forming in a profile plane i = if a stigmatic image of an object situated in a profile plane z = z , . The relation between the trajectory position vectors k, = ( Y,,x,’ ,y , , yr’) in the object plane and k, = (if, ij,j,., 9;) in the image plane can be represented by means of the first order transfer matrix (see Wollnik, 1987):

k,=

[

\

0

0

/.,I

0

0

0

0

a33

0

a43

\

)

k,.

a441

where the coefficients aIkdepend on the system in question. Suppose that the object and image planes are located in the field-free space. It is easy to see from the preceding considerations that in the presence of a misaligned element in the system the relation between k, and k,. generally takes the following form \

where a, and t l I k (i, k = 1,2,3,4) are some small quantities depending on the misalignment. We see now that the plane 1 = 2, is no more the image plane, if a,2 # 0 and c(34 # 0. However, it is not difficult to find the new position 2, = 5,.+ A of the image plane. Since the transfer matrix MAof the field-free interval of a length A is /l

A

0

O\

\o

0

0

1/

233


= M,kf; and in the linear approximation with then k, = (2,,2,,$,,pA) Eqs. (12) and (13) we obtain

/a11

\

+ Ell +

4

1

A

a12

a4 1

+ a22A

a13

a42

a43

+ a43

au

a14

\

+

J

It is clear that the plane 2 = i, is the 2-image plane if A = - a 1 2 / a 2 2 . However, this image is slightly astigmatic, because the position of the 9-image plane is defined by the equation A = Furthermore, Eq. (14) shows that the image is shifted by a1in the 2-direction and by a3 in the ?-direction. It is evident that the magnification coefficients of the system are changed, too. But the most essential effect of the system element misalignments is that the 2, coordinate of the trajectory turns out to depend on both yo and y; (with a13 # 0 and aI4# 0),and vice versa, the 9, coordinate depends on both xo and x; (with a j l # 0 and a14 # 0). This means that the image experiences additional defocusing. The correction of such an image defocusing requires special efforts. To complete our considerations for general elements of an arbitrary length, we need to give relations between the vectors 6r, 66 (determining the displacement of the entrance face of an element) and hi, 6 6 (determining the displacement of its exit face). These relations were obtained by Brown and Rothacker (1977). Here we present only their results without details. For a sector electron optical element with the deflection angle $ and a circular optical axis of the radius p, the relations in question read

63 = O(6r + 64 x P),

sf$

=

064,

where 0 is the orthogonal matrix

/

cos$

0

sin$

\

234

M. I. YAVOR

and P is the vector

For an element with a straight axis (such as a quadrupole lens) of a length L we have p --* co, t j + 0, $p = L;then the matrix 0 reduces into the unity matrix 0 = I and the vector P takes the form P = (O,O,L). The method presented allows one to analyze the transformation not only of separate trajectories but also of the ensemble of charged particles represented as an area in the six-dimensional phase space. For the lack of space we do not discuss this subject here and refer an interested reader to the article by Brown and Rothacker (1977), where the beam envelope properties are studied. The technique just described is widely used not only for the calculations of possible distortions of a beam but also for a practical adjustment of multistage electron optical systems. This was illustrated by Matsuda et al. (1977). The authors faced some difficulties when adjusting a high precision double focusing mass spectrometer at Osaka University. Its real resolving power was less than 15,000, and significant deviations in the image size were observed, depending on the source slit height and the vertical aperture angle. The image positions for the point object located at the y-axis (xo = 0) were measured experimentally for various vertical object coordinates yo and trajectory slopes Po E y;l. The results, presented in Fig. 2, show that the image of the narrow vertical source slit turned out to be a parallelogram like area instead of a vertical line. This image distortion was attributed to the small mutual parallel shift, bending and rotation of the median planes of the analyzer electrostatic and magnetic stages. The results of measurements allowed the authors to apply the theory of parasitic aberrations for a numerical estimation of the median plane misalignment, and the final adjustment was made in accordance with the results of this estimation. The resolving power of 240,000 was achieved in this way. Besides the method considered previously, there is an alternative way of computing misalignment effects of electron optical units. According to the latter, instead of using the ideal transfer matrix in a misaligned coordinate frame, the perturbed transfer matrix in the ideal coordinate frame is calculated. This matrix is obtained by the direct integration of trajectory equations in the ideal coordinate frame, but in a changed field (trajectory equations of this type are discussed in Section 111). The electromagnetic field disturbance in the ideal coordinate frame is not difficult to determine if the ideal field as well as the connection between the ideal and misaligned coor-

235

METHODS FOR CALCULATION O F PARASITIC ABERRATIONS

____--

I r-

a

4

€ €

I

3

.4

Y

>

-

2 yo

1

=+o . o 02

0

-1 -2

' Ro=O

-3

' Ro=O.

-4

I

.

-40

-30

.

.

-20 -10

. 0

003

. 10

. 20

. 30

. 40

--_----10

0

10

FIGURE 2. Shown are the points of intersection with the image plane of particle trajectories outcoming from a narrow source slit of a double focusing mass spectrometer. The positions of the points depend on the initial vertical coordinate yo of the trajectory in the object plane and the initial trajectory vertical slope Po. (a) In the misaligned system such points fill the parallelogram like area, forming the defocused source slit image; (b) in the aligned system (after adjustment) all the points lie at the vertical line and form the perfect source slit image. After H. Matsuda et al. (1977), p. 234, Fig. 6.

dinate frames are known. Such approach was used by Kawakatsu, Vosburgh, and Siegal (1968) for the calculation of mechanical aberrations of magnetic quadrupole lenses and by Zhu and Liu (1987) and Liu and Zhu (1990) for magnetic and electrostatic lenses and deflectors. However, this method seems to be less general than the one considered previously, since it requires the specification of the form of the system electromagnetic field; furthermore, it is more complicated because recalculation of the transfer matrix is needed.

111. EFFECTS OF ELECTROMAGNETIC FIELDDISTURBANCES ON CHARGED PARTICLE TRAJECTORIES Imperfections in the machining and assembling of elements of electron optical systems inevitably change their electromagnetic fields. Thus the evaluation of parasitic aberrations due to these imperfections requires the calculation of charged particle trajectories in weakly disturbed fields. The derivation of the equations describing those trajectories usually does not

236

M. I . YAVOR

FIGURE3. The natural coordinate frame { e , , e , , e , ) is shown in the neighborhood of the reference particle trajectory S in an undisturbed field. T is an arbitrary particle trajectory in a disturbed field.

cause serious difficulties and can be made analogously to the derivation of equations for charged particle trajectories in an undisturbed field. However, one should always remember that perturbances generally break the symmetry conditions inherent in electromagnetic fields of most electron optical devices. For this reason, when investigating the trajectory distortions, one cannot directly use the equations valid for the perfectly made element, but has to base calculations on more general equations. In the present section we will discuss several useful equations for particle trajectories in weakly disturbed fields. As the first example we will obtain the linear equations for paraxial trajectories in an electron optical system with an arbitrary curvilinear axis. There exist various methods to derive such equations. One of them was proposed by Grinberg (1948), who obtained the equations for relativistic trajectories in a narrow beam with an arbitrary (but known) optical axis. We will base the following considerations on the Grinberg method; for reasons of simplicity we confine ourselves to a nonrelativistic case. However, since the calculations are rather cumbersome, we will represent them without detail. First of all we will obtain the equations for trajectories lying close by a fixed three-dimensional curve S. We assume this curve to be a real trajectory of a reference particle of mass m, and charge q in an undisturbed electromagnetic field. We will define the undisturbed field by the scalar electrostatic ii and magnetic B potentials. However, in a perturbed field determined by scalar potentials u = ii 6u and w = B 6w,the S curve does not necessarily coincide with any real trajectory. We will use the arc length s as the coordinate along the S curve. We introduce the “natural” coordinate frame in the neighborhood of an arbitrary point N lying on the S curve (Fig. 3). The origin of the coordinate frame coincides with the point N ; and unit vectors ex, e , , and e, are directed along the main normal, the binormal, and the tangent to the S curve. The vector ex is supposed to be directed toward the trajectory curvature center. We also assume that the curvature does not change its sign along the S curve.

+

+


237

Now the trajectory T of an arbitrary particle moving close by the S curve can be defined by the parameter s and the vector p(s) = x(s)e,(s) + y(s)e,(s). The equation of motion for this particle in a perturbed field reads d2

m - (R dt2

+ p) = q{E + v x B},

(15 )

where R is the position vector of the point N ; E = - grad u and B = - grad w are field strengths of the electrostatic and magnetic field; v is the velocity, m = m, 6m the mass, and q the charge of the particle. Suppose that the velocity of the reference particle moving along the S curve equals zero at the point where the electrostatic potential equals zero, too. Then the energy conservation law for an arbitrary particle has the following form:

+

mv2 -- -qu

+ 6,

2

where v = (v(,6 is a small energy deviation of the particle in question relative to the reference particle in some initial point where the potential disturbance 6u is assumed to equal zero. The derivative with respect to the time t in Eq. (1 5 ) can be replaced by the derivative with respect to the arc length s. Then, using Eq. (16) and the well-known formulae de,/ds = - e,/p e,/z, de,/ds = - e , / t , de,/ds = e,/p (where p and T are curvature and torsion radii for the S curve), we come after some cumbersome calculations to the following equations for x- and y-components of the trajectory:

+

2u

(

X"-

2y'

T

+Tyr' -2

">

+ P + -p ( U + xu, + yU,) -j

T

3 :; u,

+ U' (xf - -

2u

x

2x' (y''+----T

XT'

T2

- --

-

xu,,

') + U ' (y ' + -:>

T2

>

-

-

yu,,

u,-

xu,, - yu,,

(

=/Z[W 2u ' 2( u l2+ qu + x+ w , + yw, - -X I - yuy

:'>4

(17b) Here U = 0 6U and W = W 6 W (as well as their derivatives) denote the values of the potentials u and w (and their derivatives) at the S curve; prime

+

+

238

M. I. YAVOR

denotes the derivative with respect to the arc length s. Only the first order terms on x, y , and o are retained in Eqs. (17). Rewriting Eqs. (17) for the trajectory of the reference particle that moves in the undisturbed fields (characterized by the values 0 and of the potentials at the S curve), we come to the following conditions of coincidence of this trajectory with the S curve:

-4

+ sUj20)

With Eqs. (18) and the relation z ,,/=(l (1 - 6rn/2rn0),Eqs. (17) can be rewritten as follows:

2u

(

2y’

yt’ 20-9P

=

x

X ” - - + T - i + T 5 t T

P

- yu,,

- p g [ y ( % + ” -2u

2gu

(

U’ x’

P

xu,,

2s u +- su, P

“ >+ x w , , + y w , , -

+ ( ’>

2u y“ + - - - - 2x’ t xt’ T2 t2

(

” >+ - ( x U , + y U , ) +

U’

y‘

:>

+-

-

xu,,

-

(

y’

yu,,

-

su,

Generally these equations can be solved only numerically. Note that Eqs. (19) are inhomogeneous even if the mass and energy of the particle in question coincide with the mass and energy of the reference particle (drn = n = 0). This means that in the disturbed electromagnetic field the reference particle trajectory is displaced, and therefore the S curve no more can be a real trajectory for any particle. Equations (19) allow one to study variations of first order focusing and dispersing properties caused by field disturbances for various electron optical elements. As a simple example we consider the motion of achromatic


239

monomass particle beam (Sm = 0 = 0) in a round electrostatic lens with a straight axis ( p = z = 00). We assume the xz and y z planes to be the planes of symmetry for the perturbed potential (i.e., U, = U, = U, = 0). Such a disturbance can be caused, say, by a small ellipticity of one of the lens electrodes. Then. Eqs. (19) simplify to

y”

U’ - y - + y’ - 0. 2u 2u UYY

Since in an ideal round lens o;, = U,, = - 0 ”/2 , but the potential disturbance Su does not possess the axial symmetry (6Uxx# SUy,), the x- and y-focus positions of an imperfect lens do not coincide. This effect due to a small ellipticity of the lens electrodes is well-known and is called axial astigmatism. It was discussed in detail, for example, in the book by Strashkevitch (1959). Some interesting results on the axial astigmatism have been obtained by Janssen and Thiem (1988). If the ellipse axes in the lens in question do not coincide with x and y axes, then SU,, # 0. In that case Eqs. (19) take the following form:

U’ - y f’ + y’ -

2u

32- x u,= 0. 2u

2u

Now the x-focusing properties of the lens are different for trajectories with different y coordinates, and vice versa. The evident result of this defect is the rotation of the linear astigmatic x-image of a point object in the x-image plane. If the object has a finite dimension in the y-direction, then the x-image is defocused. The same effect is observed in the y-image plane. This effect is analogous to the image defocusing in a system containing a misaligned element, discussed in Section 11. Thus we see that the electromagnetic field perturbation in an electron optical system can lead to such parasitic aberrations as lateral and longitudinal displacement of an image, its rotation, astigmatism, and other kinds of defocusing. It is obvious from Eq. (19) that a perturbation also changes system dispersion properties. An interesting example of effects of manufacturing inaccuracies is the charged particle motion in crossed electrostatic and magnetic fields whose orthogonality is violated due to a small imperfection of a system. Changes in focusing and dispersing properties of such a system was studied by Kuzmin (1971).

240

M. I. YAVOR

Equations (19) are not valid for emission electron optical systems, such as cathode lens, where the charged particle energy near the cathode is small. The investigation of cathode lenses requires more sophisticated methods, though some simple defects of cathode lenses were studied as early as the 1950s. Vorobjev ( 1 959) investigated the axial astigmatism effect in round cathode lenses. Later Der-Shvartz and Kulikov (1 968) considered imperfections in electrostatic round cathode lenses with a plane cathode. In this paper the potential disturbance was represented by the Fourier series with respect to azimuthal angle. Der-Shvartz and Kulikov obtained the expressions for the third-order aberrations and estimated the effects of some special manufacturing defects. The most complete theory of parasitic aberrations in cathode lenses has been proposed by Kolesnikov and Monastyrsky (1988). This theory includes the evaluation of the third order space and time-of-flight aberrations caused by the violation of the axial symmetry. The paper by Kolesnikov and Monastyrsky contains both general relations and analysis of some specific types of field disturbances. Some preliminary theoretical results used in the paper were obtained in the early article by Monastyrsky (1978). For lack of space we shall not discuss the parasitic aberration theory for cathode lenses here. As was mentioned earlier, in some cases it is useful to investigate the field disturbance influence not only on the first order properties of a system, but also on the second order aberrations. As an example we will now obtain the equations for charged particle trajectories in a weakly disturbed inhomogeneous magnetic and electrostatic sector fields. We begin with a magnetic case. Suppose the charged particle beam axis in an undisturbed magnetic sector field with the symmetry plane z = 0 to be the circle arc of a radius r,, lying in the z = 0 plane. It is convenient to introduce the cylindrical coordinate frame ( r , z, $}, $ being the azimuthal angle, and the dimensionless coordinates r = ( r - ro)/ro,[ = z/roin the neighborhood of the optical axis r = y o . Any known method can be used to derive the equations for the 9- and (-components of charged particle trajectories in a magnetic field defined by its scalar potential w. These equations read 29'2 9'' - -

I+r

1 x ___ l+r

{

g

9 4 -f V '

pwl

+ (1 + 9)2] + (' aw 24

,


x

241

aw - 'I"' - - 'I' 1 { [ P+ (1 + 'I)']l+'I a'I ai 84 aw

awl .

(20b) Here mo and KO are the mass and energy of the reference particle moving along the optical axis in the undisturbed field, y = Sm/moand o = SK/Koare the relative deviations of the mass and energy of an arbitrary particle, prime denotes the derivative with respect to the angle 4. For the reference particle Eq. (20a) gives J w / q = 1 , if we represent the scalar potential I? of the undisturbed magnetic field by the expansion *('I, 0 the following equation is valid:

where

It means that x(5) = 5 + v(

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